diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS
index aaab077d255da..2ad0a006e0346 100644
--- a/.github/CODEOWNERS
+++ b/.github/CODEOWNERS
@@ -95,10 +95,10 @@ xpti/ @tovinkere @andykaylor
 xptifw/ @tovinkere  @andykaylor
 
 # DPC++ tools
-llvm/tools/file-table-tform/ @kbobrovs @AlexeySachkov
-llvm/tools/llvm-foreach/ @AlexeySachkov  @Fznamznon
-llvm/tools/llvm-no-spir-kernel/ @AGindinson @AlexeySachkov
-llvm/tools/sycl-post-link/ @kbobrovs @AlexeySachkov
+llvm/**/file-table-tform/ @kbobrovs @AlexeySachkov
+llvm/**/llvm-foreach/ @AlexeySachkov  @Fznamznon
+llvm/**/llvm-no-spir-kernel/ @AGindinson @AlexeySachkov
+llvm/**/sycl-post-link/ @kbobrovs @AlexeySachkov
 
 # Clang offload tools
 clang/tools/clang-offload-bundler/ @kbobrovs @sndmitriev
diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md
index 225a43ae1ad7d..03e363c191e7e 100644
--- a/CONTRIBUTING.md
+++ b/CONTRIBUTING.md
@@ -62,6 +62,14 @@ see [ABI Policy Guide](sycl/doc/ABIPolicyGuide.md) for more information.
 - For any DPC++-related commit, the `[SYCL]` tag should be present in the
   commit message title. To a reasonable extent, additional tags can be used
   to signify the component changed, e.g.: `[PI]`, `[CUDA]`, `[Doc]`.
+- For product changes which require modification in tests outside of the current repository
+  (see [Test DPC++ toolchain](sycl/doc/GetStartedGuide.md#test-dpc-toolchain)),
+  the commit message should contain the link to corresponding test PR, e.g.: E2E
+  test changes are available under intel/llvm-test-suite#88 or SYCL
+  conformance test changes are available under KhronosGroup/SYCL-CTS#65 (see
+  [Autolinked references and URLs](https://docs.github.com/en/free-pro-team/github/writing-on-github/autolinked-references-and-urls)
+  for more details). The same message should be present both in commit
+  message and in PR description.
 
 ### Review and acceptance testing
 
diff --git a/buildbot/check.py b/buildbot/check.py
index f07b248030a49..70e98c1a701ea 100644
--- a/buildbot/check.py
+++ b/buildbot/check.py
@@ -49,7 +49,7 @@ def main():
     parser.add_argument("-d", "--base-branch", metavar="BASE_BRANCH", help="pull request base branch")
     parser.add_argument("-r", "--pr-number", metavar="PR_NUM", help="pull request number")
     parser.add_argument("-w", "--builder-dir", metavar="BUILDER_DIR",
-                        help="builder directory, which is the directory contains source and build directories")
+                        help="builder directory, which is the directory containing source and build directories")
     parser.add_argument("-s", "--src-dir", metavar="SRC_DIR", help="source directory")
     parser.add_argument("-o", "--obj-dir", metavar="OBJ_DIR", help="build directory")
     parser.add_argument("-t", "--test-suite", metavar="TEST_SUITE", default="check-all", help="check-xxx target")
diff --git a/buildbot/clang_tidy.py b/buildbot/clang_tidy.py
index 1c045aa4cb00a..c9c9eb37d7b68 100644
--- a/buildbot/clang_tidy.py
+++ b/buildbot/clang_tidy.py
@@ -51,7 +51,7 @@ def main():
                         help="pull request base branch")
     parser.add_argument("-r", "--pr-number", metavar="PR_NUM", help="pull request number")
     parser.add_argument("-w", "--builder-dir", metavar="BUILDER_DIR", required=True,
-                        help="builder directory, which is the directory contains source and build directories")
+                        help="builder directory, which is the directory containing source and build directories")
     parser.add_argument("-s", "--src-dir", metavar="SRC_DIR", required=True, help="source directory")
     parser.add_argument("-o", "--obj-dir", metavar="OBJ_DIR", required=True, help="build directory")
 
diff --git a/buildbot/compile.py b/buildbot/compile.py
index 01a3936e65e05..53766ada61952 100644
--- a/buildbot/compile.py
+++ b/buildbot/compile.py
@@ -51,7 +51,7 @@ def main():
     parser.add_argument("-d", "--base-branch", metavar="BASE_BRANCH", help="pull request base branch")
     parser.add_argument("-r", "--pr-number", metavar="PR_NUM", help="pull request number")
     parser.add_argument("-w", "--builder-dir", metavar="BUILDER_DIR",
-                        help="builder directory, which is the directory contains source and build directories")
+                        help="builder directory, which is the directory containing source and build directories")
     parser.add_argument("-s", "--src-dir", metavar="SRC_DIR", help="source directory")
     parser.add_argument("-o", "--obj-dir", metavar="OBJ_DIR", help="build directory")
     parser.add_argument("-j", "--build-parallelism", metavar="BUILD_PARALLELISM", help="build parallelism")
diff --git a/buildbot/configure.py b/buildbot/configure.py
index 1e7781c4c6df3..c9be61f91d33a 100644
--- a/buildbot/configure.py
+++ b/buildbot/configure.py
@@ -123,7 +123,7 @@ def main():
     parser.add_argument("-d", "--base-branch", metavar="BASE_BRANCH", help="pull request base branch")
     parser.add_argument("-r", "--pr-number", metavar="PR_NUM", help="pull request number")
     parser.add_argument("-w", "--builder-dir", metavar="BUILDER_DIR",
-                        help="builder directory, which is the directory contains source and build directories")
+                        help="builder directory, which is the directory containing source and build directories")
     # User options
     parser.add_argument("-s", "--src-dir", metavar="SRC_DIR", help="source directory (autodetected by default)")
     parser.add_argument("-o", "--obj-dir", metavar="OBJ_DIR", help="build directory. (<src>/build by default)")
diff --git a/buildbot/dependency.conf b/buildbot/dependency.conf
index a0c8303dde9f4..560645df01304 100644
--- a/buildbot/dependency.conf
+++ b/buildbot/dependency.conf
@@ -4,8 +4,8 @@ ocl_cpu_rt_ver=2020.11.11.0.04
 # https://github.com/intel/llvm/releases/download/2020-WW45/win-oclcpuexp-2020.11.11.0.04_rel.zip
 ocl_cpu_rt_ver_win=2020.11.11.0.04
 # Same GPU driver supports Level Zero and OpenCL
-# https://github.com/intel/compute-runtime/releases/tag/20.52.18783
-ocl_gpu_rt_ver=20.52.18783
+# https://github.com/intel/compute-runtime/releases/tag/21.01.18793
+ocl_gpu_rt_ver=21.01.18793
 # Same GPU driver supports Level Zero and OpenCL
 # https://downloadmirror.intel.com/30066/a08/igfx_win10_100.9030.zip
 ocl_gpu_rt_ver_win=27.20.100.9030
@@ -26,7 +26,7 @@ ocloc_ver_win=27.20.100.8935
 [DRIVER VERSIONS]
 cpu_driver_lin=2020.11.11.0.04
 cpu_driver_win=2020.11.11.0.04
-gpu_driver_lin=20.52.18783
+gpu_driver_lin=21.01.18793
 gpu_driver_win=27.20.100.9030
 fpga_driver_lin=2020.11.11.0.04
 fpga_driver_win=2020.11.11.0.04
diff --git a/buildbot/dependency.py b/buildbot/dependency.py
index 21ee9258871d5..20ba0fc9041d7 100644
--- a/buildbot/dependency.py
+++ b/buildbot/dependency.py
@@ -97,7 +97,7 @@ def main():
     parser.add_argument("-d", "--base-branch", metavar="BASE_BRANCH", help="pull request base branch")
     parser.add_argument("-r", "--pr-number", metavar="PR_NUM", help="pull request number")
     parser.add_argument("-w", "--builder-dir", metavar="BUILDER_DIR",
-                        help="builder directory, which is the directory contains source and build directories")
+                        help="builder directory, which is the directory containing source and build directories")
     parser.add_argument("-s", "--src-dir", metavar="SRC_DIR", help="source directory")
     parser.add_argument("-o", "--obj-dir", metavar="OBJ_DIR", required=True, help="build directory")
     parser.add_argument("-c", "--clean-build", action="store_true", default=False,
diff --git a/clang-tools-extra/clang-tidy/ClangTidy.cpp b/clang-tools-extra/clang-tidy/ClangTidy.cpp
index 633655e5e24ab..12d2134026c41 100644
--- a/clang-tools-extra/clang-tidy/ClangTidy.cpp
+++ b/clang-tools-extra/clang-tidy/ClangTidy.cpp
@@ -22,13 +22,10 @@
 #include "ExpandModularHeadersPPCallbacks.h"
 #include "clang-tidy-config.h"
 #include "clang/AST/ASTConsumer.h"
-#include "clang/AST/ASTContext.h"
-#include "clang/AST/Decl.h"
 #include "clang/ASTMatchers/ASTMatchFinder.h"
 #include "clang/Format/Format.h"
 #include "clang/Frontend/ASTConsumers.h"
 #include "clang/Frontend/CompilerInstance.h"
-#include "clang/Frontend/FrontendActions.h"
 #include "clang/Frontend/FrontendDiagnostic.h"
 #include "clang/Frontend/MultiplexConsumer.h"
 #include "clang/Frontend/TextDiagnosticPrinter.h"
@@ -43,7 +40,6 @@
 #include "clang/Tooling/ReplacementsYaml.h"
 #include "clang/Tooling/Tooling.h"
 #include "llvm/Support/Process.h"
-#include "llvm/Support/Signals.h"
 #include <algorithm>
 #include <utility>
 
diff --git a/clang-tools-extra/clang-tidy/ClangTidyCheck.cpp b/clang-tools-extra/clang-tidy/ClangTidyCheck.cpp
index 3567aac42c062..e1bea430a89a5 100644
--- a/clang-tools-extra/clang-tidy/ClangTidyCheck.cpp
+++ b/clang-tools-extra/clang-tidy/ClangTidyCheck.cpp
@@ -10,9 +10,7 @@
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/Error.h"
-#include "llvm/Support/WithColor.h"
 #include "llvm/Support/YAMLParser.h"
-#include "llvm/Support/raw_ostream.h"
 
 namespace clang {
 namespace tidy {
diff --git a/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp b/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
index 2c3f51a4034eb..346fa66a662a1 100644
--- a/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
+++ b/clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
@@ -23,7 +23,6 @@
 #include "clang/AST/Attr.h"
 #include "clang/Basic/Diagnostic.h"
 #include "clang/Basic/DiagnosticOptions.h"
-#include "clang/Basic/FileManager.h"
 #include "clang/Basic/SourceManager.h"
 #include "clang/Frontend/DiagnosticRenderer.h"
 #include "clang/Tooling/Core/Diagnostic.h"
@@ -31,7 +30,6 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringMap.h"
-#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/FormatVariadic.h"
 #include "llvm/Support/Regex.h"
 #include <tuple>
@@ -39,6 +37,10 @@
 using namespace clang;
 using namespace tidy;
 
+#ifdef LLVM_CLANG_AST_ATTR_H
+//#error
+#endif
+
 namespace {
 class ClangTidyDiagnosticRenderer : public DiagnosticRenderer {
 public:
diff --git a/clang-tools-extra/clang-tidy/ClangTidyModule.h b/clang-tools-extra/clang-tidy/ClangTidyModule.h
index 7fd16c2a7b3c7..dd21a8dbc6a43 100644
--- a/clang-tools-extra/clang-tidy/ClangTidyModule.h
+++ b/clang-tools-extra/clang-tidy/ClangTidyModule.h
@@ -13,9 +13,7 @@
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
 #include <functional>
-#include <map>
 #include <memory>
-#include <string>
 
 namespace clang {
 namespace tidy {
diff --git a/clang-tools-extra/clang-tidy/ClangTidyOptions.cpp b/clang-tools-extra/clang-tidy/ClangTidyOptions.cpp
index 197552acf927c..472123f8b3068 100644
--- a/clang-tools-extra/clang-tidy/ClangTidyOptions.cpp
+++ b/clang-tools-extra/clang-tidy/ClangTidyOptions.cpp
@@ -16,7 +16,6 @@
 #include "llvm/Support/MemoryBufferRef.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/YAMLTraits.h"
-#include "llvm/Support/raw_ostream.h"
 #include <utility>
 
 #define DEBUG_TYPE "clang-tidy-options"
diff --git a/clang-tools-extra/clang-tidy/ClangTidyProfiling.cpp b/clang-tools-extra/clang-tidy/ClangTidyProfiling.cpp
index e60332d599a59..b107dd7385c65 100644
--- a/clang-tools-extra/clang-tidy/ClangTidyProfiling.cpp
+++ b/clang-tools-extra/clang-tidy/ClangTidyProfiling.cpp
@@ -7,11 +7,9 @@
 //===----------------------------------------------------------------------===//
 
 #include "ClangTidyProfiling.h"
-#include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
-#include "llvm/Support/YAMLTraits.h"
 #include "llvm/Support/raw_ostream.h"
 #include <system_error>
 #include <utility>
diff --git a/clang-tools-extra/clang-tidy/altera/SingleWorkItemBarrierCheck.cpp b/clang-tools-extra/clang-tidy/altera/SingleWorkItemBarrierCheck.cpp
index 759c81c34ca64..521126f990e97 100644
--- a/clang-tools-extra/clang-tidy/altera/SingleWorkItemBarrierCheck.cpp
+++ b/clang-tools-extra/clang-tidy/altera/SingleWorkItemBarrierCheck.cpp
@@ -57,8 +57,9 @@ void SingleWorkItemBarrierCheck::check(const MatchFinder::MatchResult &Result) {
     bool IsNDRange = false;
     if (MatchedDecl->hasAttr<ReqdWorkGroupSizeAttr>()) {
       const auto *Attribute = MatchedDecl->getAttr<ReqdWorkGroupSizeAttr>();
-      if (Attribute->getXDim() > 1 || Attribute->getYDim() > 1 ||
-          Attribute->getZDim() > 1)
+      if (*Attribute->getXDimVal(*Result.Context) > 1 ||
+          *Attribute->getYDimVal(*Result.Context) > 1 ||
+          *Attribute->getZDimVal(*Result.Context) > 1)
         IsNDRange = true;
     }
     if (IsNDRange) // No warning if kernel is treated as an NDRange.
diff --git a/clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp b/clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp
index 14a38c09ad9b0..e7c5f0ab05be9 100644
--- a/clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp
+++ b/clang-tools-extra/clang-tidy/readability/ContainerSizeEmptyCheck.cpp
@@ -16,6 +16,77 @@
 using namespace clang::ast_matchers;
 
 namespace clang {
+namespace ast_matchers {
+AST_POLYMORPHIC_MATCHER_P2(hasAnyArgumentWithParam,
+                           AST_POLYMORPHIC_SUPPORTED_TYPES(CallExpr,
+                                                           CXXConstructExpr),
+                           internal::Matcher<Expr>, ArgMatcher,
+                           internal::Matcher<ParmVarDecl>, ParamMatcher) {
+  BoundNodesTreeBuilder Result;
+  // The first argument of an overloaded member operator is the implicit object
+  // argument of the method which should not be matched against a parameter, so
+  // we skip over it here.
+  BoundNodesTreeBuilder Matches;
+  unsigned ArgIndex = cxxOperatorCallExpr(callee(cxxMethodDecl()))
+                              .matches(Node, Finder, &Matches)
+                          ? 1
+                          : 0;
+  int ParamIndex = 0;
+  for (; ArgIndex < Node.getNumArgs(); ++ArgIndex) {
+    BoundNodesTreeBuilder ArgMatches(*Builder);
+    if (ArgMatcher.matches(*(Node.getArg(ArgIndex)->IgnoreParenCasts()), Finder,
+                           &ArgMatches)) {
+      BoundNodesTreeBuilder ParamMatches(ArgMatches);
+      if (expr(anyOf(cxxConstructExpr(hasDeclaration(cxxConstructorDecl(
+                         hasParameter(ParamIndex, ParamMatcher)))),
+                     callExpr(callee(functionDecl(
+                         hasParameter(ParamIndex, ParamMatcher))))))
+              .matches(Node, Finder, &ParamMatches)) {
+        Result.addMatch(ParamMatches);
+        *Builder = std::move(Result);
+        return true;
+      }
+    }
+    ++ParamIndex;
+  }
+  return false;
+}
+
+AST_MATCHER(Expr, usedInBooleanContext) {
+  const char *ExprName = "__booleanContextExpr";
+  auto Result =
+      expr(expr().bind(ExprName),
+           anyOf(hasParent(varDecl(hasType(booleanType()))),
+                 hasParent(cxxConstructorDecl(
+                     hasAnyConstructorInitializer(cxxCtorInitializer(
+                         withInitializer(expr(equalsBoundNode(ExprName))),
+                         forField(hasType(booleanType())))))),
+                 hasParent(fieldDecl(hasType(booleanType()))),
+                 hasParent(stmt(anyOf(
+                     explicitCastExpr(hasDestinationType(booleanType())),
+                     ifStmt(hasCondition(expr(equalsBoundNode(ExprName)))),
+                     doStmt(hasCondition(expr(equalsBoundNode(ExprName)))),
+                     whileStmt(hasCondition(expr(equalsBoundNode(ExprName)))),
+                     forStmt(hasCondition(expr(equalsBoundNode(ExprName)))),
+                     conditionalOperator(
+                         hasCondition(expr(equalsBoundNode(ExprName)))),
+                     parenListExpr(hasParent(varDecl(hasType(booleanType())))),
+                     parenExpr(hasParent(
+                         explicitCastExpr(hasDestinationType(booleanType())))),
+                     returnStmt(forFunction(returns(booleanType()))),
+                     cxxUnresolvedConstructExpr(hasType(booleanType())),
+                     callExpr(hasAnyArgumentWithParam(
+                         expr(equalsBoundNode(ExprName)),
+                         parmVarDecl(hasType(booleanType())))),
+                     binaryOperator(hasAnyOperatorName("&&", "||")),
+                     unaryOperator(hasOperatorName("!")).bind("NegOnSize"))))))
+          .matches(Node, Finder, Builder);
+  Builder->removeBindings([ExprName](const BoundNodesMap &Nodes) {
+    return Nodes.getNode(ExprName).getNodeKind().isNone();
+  });
+  return Result;
+}
+} // namespace ast_matchers
 namespace tidy {
 namespace readability {
 
@@ -26,18 +97,27 @@ ContainerSizeEmptyCheck::ContainerSizeEmptyCheck(StringRef Name,
     : ClangTidyCheck(Name, Context) {}
 
 void ContainerSizeEmptyCheck::registerMatchers(MatchFinder *Finder) {
-  const auto ValidContainer = qualType(hasUnqualifiedDesugaredType(
-      recordType(hasDeclaration(cxxRecordDecl(isSameOrDerivedFrom(
-          namedDecl(
-              has(cxxMethodDecl(
-                      isConst(), parameterCountIs(0), isPublic(),
-                      hasName("size"),
-                      returns(qualType(isInteger(), unless(booleanType()))))
-                      .bind("size")),
-              has(cxxMethodDecl(isConst(), parameterCountIs(0), isPublic(),
-                                hasName("empty"), returns(booleanType()))
-                      .bind("empty")))
-              .bind("container")))))));
+  const auto ValidContainerRecord = cxxRecordDecl(isSameOrDerivedFrom(
+      namedDecl(
+          has(cxxMethodDecl(isConst(), parameterCountIs(0), isPublic(),
+                            hasName("size"),
+                            returns(qualType(isInteger(), unless(booleanType()),
+                                             unless(elaboratedType()))))
+                  .bind("size")),
+          has(cxxMethodDecl(isConst(), parameterCountIs(0), isPublic(),
+                            hasName("empty"), returns(booleanType()))
+                  .bind("empty")))
+          .bind("container")));
+
+  const auto ValidContainerNonTemplateType =
+      qualType(hasUnqualifiedDesugaredType(
+          recordType(hasDeclaration(ValidContainerRecord))));
+  const auto ValidContainerTemplateType =
+      qualType(hasUnqualifiedDesugaredType(templateSpecializationType(
+          hasDeclaration(classTemplateDecl(has(ValidContainerRecord))))));
+
+  const auto ValidContainer = qualType(
+      anyOf(ValidContainerNonTemplateType, ValidContainerTemplateType));
 
   const auto WrongUse = traverse(
       TK_AsIs,
@@ -52,18 +132,34 @@ void ContainerSizeEmptyCheck::registerMatchers(MatchFinder *Finder) {
               anyOf(hasParent(
                         unaryOperator(hasOperatorName("!")).bind("NegOnSize")),
                     anything()))),
-          hasParent(explicitCastExpr(hasDestinationType(booleanType())))));
+          usedInBooleanContext()));
 
   Finder->addMatcher(
-      cxxMemberCallExpr(on(expr(anyOf(hasType(ValidContainer),
+      cxxMemberCallExpr(unless(isInTemplateInstantiation()),
+                        on(expr(anyOf(hasType(ValidContainer),
                                       hasType(pointsTo(ValidContainer)),
-                                      hasType(references(ValidContainer))))),
+                                      hasType(references(ValidContainer))))
+                               .bind("MemberCallObject")),
                         callee(cxxMethodDecl(hasName("size"))), WrongUse,
                         unless(hasAncestor(cxxMethodDecl(
                             ofClass(equalsBoundNode("container"))))))
           .bind("SizeCallExpr"),
       this);
 
+  Finder->addMatcher(
+      callExpr(has(cxxDependentScopeMemberExpr(
+                   hasObjectExpression(
+                       expr(anyOf(hasType(ValidContainer),
+                                  hasType(pointsTo(ValidContainer)),
+                                  hasType(references(ValidContainer))))
+                           .bind("MemberCallObject")),
+                   hasMemberName("size"))),
+               WrongUse,
+               unless(hasAncestor(
+                   cxxMethodDecl(ofClass(equalsBoundNode("container"))))))
+          .bind("SizeCallExpr"),
+      this);
+
   // Empty constructor matcher.
   const auto DefaultConstructor = cxxConstructExpr(
           hasDeclaration(cxxConstructorDecl(isDefaultConstructor())));
@@ -72,12 +168,11 @@ void ContainerSizeEmptyCheck::registerMatchers(MatchFinder *Finder) {
       ignoringImpCasts(stringLiteral(hasSize(0))),
       ignoringImpCasts(cxxBindTemporaryExpr(has(DefaultConstructor))),
       ignoringImplicit(DefaultConstructor),
-      cxxConstructExpr(
-          hasDeclaration(cxxConstructorDecl(isCopyConstructor())),
-          has(expr(ignoringImpCasts(DefaultConstructor)))),
-      cxxConstructExpr(
-          hasDeclaration(cxxConstructorDecl(isMoveConstructor())),
-          has(expr(ignoringImpCasts(DefaultConstructor)))));
+      cxxConstructExpr(hasDeclaration(cxxConstructorDecl(isCopyConstructor())),
+                       has(expr(ignoringImpCasts(DefaultConstructor)))),
+      cxxConstructExpr(hasDeclaration(cxxConstructorDecl(isMoveConstructor())),
+                       has(expr(ignoringImpCasts(DefaultConstructor)))),
+      cxxUnresolvedConstructExpr(argumentCountIs(0)));
   // Match the object being compared.
   const auto STLArg =
       anyOf(unaryOperator(
@@ -87,6 +182,7 @@ void ContainerSizeEmptyCheck::registerMatchers(MatchFinder *Finder) {
             expr(hasType(ValidContainer)).bind("STLObject"));
   Finder->addMatcher(
       cxxOperatorCallExpr(
+          unless(isInTemplateInstantiation()),
           hasAnyOverloadedOperatorName("==", "!="),
           anyOf(allOf(hasArgument(0, WrongComparend), hasArgument(1, STLArg)),
                 allOf(hasArgument(0, STLArg), hasArgument(1, WrongComparend))),
@@ -94,24 +190,33 @@ void ContainerSizeEmptyCheck::registerMatchers(MatchFinder *Finder) {
               cxxMethodDecl(ofClass(equalsBoundNode("container"))))))
           .bind("BinCmp"),
       this);
+  Finder->addMatcher(
+      binaryOperator(hasAnyOperatorName("==", "!="),
+                     anyOf(allOf(hasLHS(WrongComparend), hasRHS(STLArg)),
+                           allOf(hasLHS(STLArg), hasRHS(WrongComparend))),
+                     unless(hasAncestor(
+                         cxxMethodDecl(ofClass(equalsBoundNode("container"))))))
+          .bind("BinCmp"),
+      this);
 }
 
 void ContainerSizeEmptyCheck::check(const MatchFinder::MatchResult &Result) {
-  const auto *MemberCall =
-      Result.Nodes.getNodeAs<CXXMemberCallExpr>("SizeCallExpr");
+  const auto *MemberCall = Result.Nodes.getNodeAs<Expr>("SizeCallExpr");
+  const auto *MemberCallObject =
+      Result.Nodes.getNodeAs<Expr>("MemberCallObject");
   const auto *BinCmp = Result.Nodes.getNodeAs<CXXOperatorCallExpr>("BinCmp");
+  const auto *BinCmpTempl = Result.Nodes.getNodeAs<BinaryOperator>("BinCmp");
   const auto *BinaryOp = Result.Nodes.getNodeAs<BinaryOperator>("SizeBinaryOp");
   const auto *Pointee = Result.Nodes.getNodeAs<Expr>("Pointee");
   const auto *E =
-      MemberCall
-          ? MemberCall->getImplicitObjectArgument()
+      MemberCallObject
+          ? MemberCallObject
           : (Pointee ? Pointee : Result.Nodes.getNodeAs<Expr>("STLObject"));
   FixItHint Hint;
   std::string ReplacementText = std::string(
       Lexer::getSourceText(CharSourceRange::getTokenRange(E->getSourceRange()),
                            *Result.SourceManager, getLangOpts()));
-  if (BinCmp && IsBinaryOrTernary(E)) {
-    // Not just a DeclRefExpr, so parenthesize to be on the safe side.
+  if (IsBinaryOrTernary(E) || isa<UnaryOperator>(E)) {
     ReplacementText = "(" + ReplacementText + ")";
   }
   if (E->getType()->isPointerType())
@@ -125,7 +230,13 @@ void ContainerSizeEmptyCheck::check(const MatchFinder::MatchResult &Result) {
     }
     Hint =
         FixItHint::CreateReplacement(BinCmp->getSourceRange(), ReplacementText);
-  } else if (BinaryOp) {  // Determine the correct transformation.
+  } else if (BinCmpTempl) {
+    if (BinCmpTempl->getOpcode() == BinaryOperatorKind::BO_NE) {
+      ReplacementText = "!" + ReplacementText;
+    }
+    Hint = FixItHint::CreateReplacement(BinCmpTempl->getSourceRange(),
+                                        ReplacementText);
+  } else if (BinaryOp) { // Determine the correct transformation.
     bool Negation = false;
     const bool ContainerIsLHS =
         !llvm::isa<IntegerLiteral>(BinaryOp->getLHS()->IgnoreImpCasts());
@@ -195,15 +306,17 @@ void ContainerSizeEmptyCheck::check(const MatchFinder::MatchResult &Result) {
                                           "!" + ReplacementText);
   }
 
-  if (MemberCall) {
-    diag(MemberCall->getBeginLoc(),
-         "the 'empty' method should be used to check "
-         "for emptiness instead of 'size'")
+  auto WarnLoc = MemberCall ? MemberCall->getBeginLoc() : SourceLocation{};
+
+  if (WarnLoc.isValid()) {
+    diag(WarnLoc, "the 'empty' method should be used to check "
+                  "for emptiness instead of 'size'")
         << Hint;
   } else {
-    diag(BinCmp->getBeginLoc(),
-         "the 'empty' method should be used to check "
-         "for emptiness instead of comparing to an empty object")
+    WarnLoc = BinCmpTempl ? BinCmpTempl->getBeginLoc()
+                          : (BinCmp ? BinCmp->getBeginLoc() : SourceLocation{});
+    diag(WarnLoc, "the 'empty' method should be used to check "
+                  "for emptiness instead of comparing to an empty object")
         << Hint;
   }
 
diff --git a/clang-tools-extra/clangd/CMakeLists.txt b/clang-tools-extra/clangd/CMakeLists.txt
index 919457f216c15..9e62e09480274 100644
--- a/clang-tools-extra/clangd/CMakeLists.txt
+++ b/clang-tools-extra/clangd/CMakeLists.txt
@@ -14,9 +14,12 @@ if (NOT DEFINED CLANGD_BUILD_XPC)
   unset(CLANGD_BUILD_XPC_DEFAULT)
 endif ()
 
+option(CLANGD_MALLOC_TRIM "Call malloc_trim(3) periodically in Clangd. (only takes effect when using glibc)" ON)
+
 llvm_canonicalize_cmake_booleans(
   CLANGD_BUILD_XPC
   CLANGD_ENABLE_REMOTE
+  CLANGD_MALLOC_TRIM
   LLVM_ENABLE_ZLIB
 )
 
diff --git a/clang-tools-extra/clangd/ClangdLSPServer.cpp b/clang-tools-extra/clangd/ClangdLSPServer.cpp
index b32c9e13973b6..c606ccae4fdc0 100644
--- a/clang-tools-extra/clangd/ClangdLSPServer.cpp
+++ b/clang-tools-extra/clangd/ClangdLSPServer.cpp
@@ -178,6 +178,7 @@ class ClangdLSPServer::MessageHandler : public Transport::MessageHandler {
     } else if (auto Handler = Notifications.lookup(Method)) {
       Handler(std::move(Params));
       Server.maybeExportMemoryProfile();
+      Server.maybeCleanupMemory();
     } else {
       log("unhandled notification {0}", Method);
     }
@@ -453,6 +454,7 @@ void ClangdLSPServer::callRaw(StringRef Method, llvm::json::Value Params,
 
 void ClangdLSPServer::notify(llvm::StringRef Method, llvm::json::Value Params) {
   log("--> {0}", Method);
+  maybeCleanupMemory();
   std::lock_guard<std::mutex> Lock(TranspWriter);
   Transp.notify(Method, std::move(Params));
 }
@@ -1283,13 +1285,7 @@ void ClangdLSPServer::publishDiagnostics(
 }
 
 void ClangdLSPServer::maybeExportMemoryProfile() {
-  if (!trace::enabled())
-    return;
-  // Profiling might be expensive, so we throttle it to happen once every 5
-  // minutes.
-  static constexpr auto ProfileInterval = std::chrono::minutes(5);
-  auto Now = std::chrono::steady_clock::now();
-  if (Now < NextProfileTime)
+  if (!trace::enabled() || !ShouldProfile())
     return;
 
   static constexpr trace::Metric MemoryUsage(
@@ -1298,7 +1294,12 @@ void ClangdLSPServer::maybeExportMemoryProfile() {
   MemoryTree MT;
   profile(MT);
   record(MT, "clangd_lsp_server", MemoryUsage);
-  NextProfileTime = Now + ProfileInterval;
+}
+
+void ClangdLSPServer::maybeCleanupMemory() {
+  if (!Opts.MemoryCleanup || !ShouldCleanupMemory())
+    return;
+  Opts.MemoryCleanup();
 }
 
 // FIXME: This function needs to be properly tested.
@@ -1458,10 +1459,15 @@ void ClangdLSPServer::onAST(const ASTParams &Params,
 ClangdLSPServer::ClangdLSPServer(class Transport &Transp,
                                  const ThreadsafeFS &TFS,
                                  const ClangdLSPServer::Options &Opts)
-    : BackgroundContext(Context::current().clone()), Transp(Transp),
+    : ShouldProfile(/*Period=*/std::chrono::minutes(5),
+                    /*Delay=*/std::chrono::minutes(1)),
+      ShouldCleanupMemory(/*Period=*/std::chrono::minutes(1),
+                          /*Delay=*/std::chrono::minutes(1)),
+      BackgroundContext(Context::current().clone()), Transp(Transp),
       MsgHandler(new MessageHandler(*this)), TFS(TFS),
       SupportedSymbolKinds(defaultSymbolKinds()),
       SupportedCompletionItemKinds(defaultCompletionItemKinds()), Opts(Opts) {
+
   // clang-format off
   MsgHandler->bind("initialize", &ClangdLSPServer::onInitialize);
   MsgHandler->bind("initialized", &ClangdLSPServer::onInitialized);
@@ -1506,9 +1512,6 @@ ClangdLSPServer::ClangdLSPServer(class Transport &Transp,
   if (Opts.FoldingRanges)
     MsgHandler->bind("textDocument/foldingRange", &ClangdLSPServer::onFoldingRange);
   // clang-format on
-
-  // Delay first profile until we've finished warming up.
-  NextProfileTime = std::chrono::steady_clock::now() + std::chrono::minutes(1);
 }
 
 ClangdLSPServer::~ClangdLSPServer() {
@@ -1621,6 +1624,10 @@ void ClangdLSPServer::onDiagnosticsReady(PathRef File, llvm::StringRef Version,
 void ClangdLSPServer::onBackgroundIndexProgress(
     const BackgroundQueue::Stats &Stats) {
   static const char ProgressToken[] = "backgroundIndexProgress";
+
+  // The background index did some work, maybe we need to cleanup
+  maybeCleanupMemory();
+
   std::lock_guard<std::mutex> Lock(BackgroundIndexProgressMutex);
 
   auto NotifyProgress = [this](const BackgroundQueue::Stats &Stats) {
diff --git a/clang-tools-extra/clangd/ClangdLSPServer.h b/clang-tools-extra/clangd/ClangdLSPServer.h
index e65fc0e8a0064..a41bc5666af33 100644
--- a/clang-tools-extra/clangd/ClangdLSPServer.h
+++ b/clang-tools-extra/clangd/ClangdLSPServer.h
@@ -19,6 +19,7 @@
 #include "support/Context.h"
 #include "support/MemoryTree.h"
 #include "support/Path.h"
+#include "support/Threading.h"
 #include "clang/Tooling/Core/Replacement.h"
 #include "llvm/ADT/Optional.h"
 #include "llvm/ADT/StringSet.h"
@@ -48,6 +49,9 @@ class ClangdLSPServer : private ClangdServer::Callbacks {
     llvm::Optional<Path> CompileCommandsDir;
     /// The offset-encoding to use, or None to negotiate it over LSP.
     llvm::Optional<OffsetEncoding> Encoding;
+    /// If set, periodically called to release memory.
+    /// Consider malloc_trim(3)
+    std::function<void()> MemoryCleanup = nullptr;
 
     /// Per-feature options. Generally ClangdServer lets these vary
     /// per-request, but LSP allows limited/no customizations.
@@ -183,10 +187,12 @@ class ClangdLSPServer : private ClangdServer::Callbacks {
   /// Runs profiling and exports memory usage metrics if tracing is enabled and
   /// profiling hasn't happened recently.
   void maybeExportMemoryProfile();
+  PeriodicThrottler ShouldProfile;
 
-  /// Timepoint until which profiling is off. It is used to throttle profiling
-  /// requests.
-  std::chrono::steady_clock::time_point NextProfileTime;
+  /// Run the MemoryCleanup callback if it's time.
+  /// This method is thread safe.
+  void maybeCleanupMemory();
+  PeriodicThrottler ShouldCleanupMemory;
 
   /// Since initialization of CDBs and ClangdServer is done lazily, the
   /// following context captures the one used while creating ClangdLSPServer and
diff --git a/clang-tools-extra/clangd/ClangdServer.cpp b/clang-tools-extra/clangd/ClangdServer.cpp
index 8b0d0591abe70..b760b31c0b87b 100644
--- a/clang-tools-extra/clangd/ClangdServer.cpp
+++ b/clang-tools-extra/clangd/ClangdServer.cpp
@@ -621,7 +621,7 @@ void ClangdServer::typeHierarchy(PathRef File, Position Pos, int Resolve,
                                 File));
   };
 
-  WorkScheduler.runWithAST("Type Hierarchy", File, std::move(Action));
+  WorkScheduler.runWithAST("TypeHierarchy", File, std::move(Action));
 }
 
 void ClangdServer::resolveTypeHierarchy(
@@ -642,7 +642,7 @@ void ClangdServer::prepareCallHierarchy(
       return CB(InpAST.takeError());
     CB(clangd::prepareCallHierarchy(InpAST->AST, Pos, File));
   };
-  WorkScheduler.runWithAST("Call Hierarchy", File, std::move(Action));
+  WorkScheduler.runWithAST("CallHierarchy", File, std::move(Action));
 }
 
 void ClangdServer::incomingCalls(
@@ -678,7 +678,7 @@ void ClangdServer::documentSymbols(llvm::StringRef File,
           return CB(InpAST.takeError());
         CB(clangd::getDocumentSymbols(InpAST->AST));
       };
-  WorkScheduler.runWithAST("documentSymbols", File, std::move(Action),
+  WorkScheduler.runWithAST("DocumentSymbols", File, std::move(Action),
                            TUScheduler::InvalidateOnUpdate);
 }
 
@@ -690,7 +690,7 @@ void ClangdServer::foldingRanges(llvm::StringRef File,
           return CB(InpAST.takeError());
         CB(clangd::getFoldingRanges(InpAST->AST));
       };
-  WorkScheduler.runWithAST("foldingRanges", File, std::move(Action),
+  WorkScheduler.runWithAST("FoldingRanges", File, std::move(Action),
                            TUScheduler::InvalidateOnUpdate);
 }
 
diff --git a/clang-tools-extra/clangd/CodeComplete.cpp b/clang-tools-extra/clangd/CodeComplete.cpp
index cc6b5dbc9904f..ebdbd56c286ac 100644
--- a/clang-tools-extra/clangd/CodeComplete.cpp
+++ b/clang-tools-extra/clangd/CodeComplete.cpp
@@ -182,12 +182,18 @@ struct CompletionCandidate {
     // strings (literal or URI) mapping to the same file. We still want to
     // bundle those, so we must resolve the header to be included here.
     std::string HeaderForHash;
-    if (Inserter)
-      if (auto Header = headerToInsertIfAllowed(Opts))
-        if (auto HeaderFile = toHeaderFile(*Header, FileName))
+    if (Inserter) {
+      if (auto Header = headerToInsertIfAllowed(Opts)) {
+        if (auto HeaderFile = toHeaderFile(*Header, FileName)) {
           if (auto Spelled =
                   Inserter->calculateIncludePath(*HeaderFile, FileName))
             HeaderForHash = *Spelled;
+        } else {
+          vlog("Code completion header path manipulation failed {0}",
+               HeaderFile.takeError());
+        }
+      }
+    }
 
     llvm::SmallString<256> Scratch;
     if (IndexResult) {
diff --git a/clang-tools-extra/clangd/DumpAST.cpp b/clang-tools-extra/clangd/DumpAST.cpp
index 8f1b3f3a1aae5..12698b42ef3e6 100644
--- a/clang-tools-extra/clangd/DumpAST.cpp
+++ b/clang-tools-extra/clangd/DumpAST.cpp
@@ -143,7 +143,6 @@ class DumpVisitor : public RecursiveASTVisitor<DumpVisitor> {
       TEMPLATE_ARGUMENT_KIND(Declaration);
       TEMPLATE_ARGUMENT_KIND(Template);
       TEMPLATE_ARGUMENT_KIND(TemplateExpansion);
-      TEMPLATE_ARGUMENT_KIND(UncommonValue);
 #undef TEMPLATE_ARGUMENT_KIND
     }
     llvm_unreachable("Unhandled ArgKind enum");
diff --git a/clang-tools-extra/clangd/Features.inc.in b/clang-tools-extra/clangd/Features.inc.in
index 6797232ddac7c..c21d2b1455710 100644
--- a/clang-tools-extra/clangd/Features.inc.in
+++ b/clang-tools-extra/clangd/Features.inc.in
@@ -1,2 +1,3 @@
 #define CLANGD_BUILD_XPC @CLANGD_BUILD_XPC@
 #define CLANGD_ENABLE_REMOTE @CLANGD_ENABLE_REMOTE@
+#define CLANGD_MALLOC_TRIM @CLANGD_MALLOC_TRIM@
diff --git a/clang-tools-extra/clangd/FindTarget.cpp b/clang-tools-extra/clangd/FindTarget.cpp
index c5c7d71be6618..3afd655226805 100644
--- a/clang-tools-extra/clangd/FindTarget.cpp
+++ b/clang-tools-extra/clangd/FindTarget.cpp
@@ -1069,7 +1069,6 @@ class ExplicitReferenceCollector
     case TemplateArgument::Pack:
     case TemplateArgument::Type:
     case TemplateArgument::Expression:
-    case TemplateArgument::UncommonValue:
       break; // Handled by VisitType and VisitExpression.
     };
     return RecursiveASTVisitor::TraverseTemplateArgumentLoc(A);
diff --git a/clang-tools-extra/clangd/GlobalCompilationDatabase.cpp b/clang-tools-extra/clangd/GlobalCompilationDatabase.cpp
index 41b549cefc7cc..86375fa11d3b1 100644
--- a/clang-tools-extra/clangd/GlobalCompilationDatabase.cpp
+++ b/clang-tools-extra/clangd/GlobalCompilationDatabase.cpp
@@ -511,11 +511,14 @@ void DirectoryBasedGlobalCompilationDatabase::broadcastCDB(
   // Given that we know that CDBs have been moved/generated, don't trust caches.
   // (This should be rare, so it's OK to add a little latency).
   constexpr auto IgnoreCache = std::chrono::steady_clock::time_point::max();
-  for (DirectoryCache *Dir : getDirectoryCaches(FileAncestors)) {
+  auto DirectoryCaches = getDirectoryCaches(FileAncestors);
+  assert(DirectoryCaches.size() == FileAncestors.size());
+  for (unsigned I = 0; I < DirectoryCaches.size(); ++I) {
     bool ShouldBroadcast = false;
-    if (Dir->get(Opts.TFS, ShouldBroadcast, /*FreshTime=*/IgnoreCache,
-                 /*FreshTimeMissing=*/IgnoreCache))
-      DirectoryHasCDB.find(Dir->Path)->setValue(true);
+    if (DirectoryCaches[I]->get(Opts.TFS, ShouldBroadcast,
+                                /*FreshTime=*/IgnoreCache,
+                                /*FreshTimeMissing=*/IgnoreCache))
+      DirectoryHasCDB.find(FileAncestors[I])->setValue(true);
   }
 
   std::vector<std::string> GovernedFiles;
diff --git a/clang-tools-extra/clangd/JSONTransport.cpp b/clang-tools-extra/clangd/JSONTransport.cpp
index eb5a83882b2bd..662e5df4e27bf 100644
--- a/clang-tools-extra/clangd/JSONTransport.cpp
+++ b/clang-tools-extra/clangd/JSONTransport.cpp
@@ -126,13 +126,13 @@ class JSONTransport : public Transport {
   bool handleMessage(llvm::json::Value Message, MessageHandler &Handler);
   // Writes outgoing message to Out stream.
   void sendMessage(llvm::json::Value Message) {
-    std::string S;
-    llvm::raw_string_ostream OS(S);
+    OutputBuffer.clear();
+    llvm::raw_svector_ostream OS(OutputBuffer);
     OS << llvm::formatv(Pretty ? "{0:2}" : "{0}", Message);
-    OS.flush();
-    Out << "Content-Length: " << S.size() << "\r\n\r\n" << S;
+    Out << "Content-Length: " << OutputBuffer.size() << "\r\n\r\n"
+        << OutputBuffer;
     Out.flush();
-    vlog(">>> {0}\n", S);
+    vlog(">>> {0}\n", OutputBuffer);
   }
 
   // Read raw string messages from input stream.
@@ -143,6 +143,7 @@ class JSONTransport : public Transport {
   llvm::Optional<std::string> readDelimitedMessage();
   llvm::Optional<std::string> readStandardMessage();
 
+  llvm::SmallVector<char, 0> OutputBuffer;
   std::FILE *In;
   llvm::raw_ostream &Out;
   llvm::raw_ostream &InMirror;
diff --git a/clang-tools-extra/clangd/TUScheduler.cpp b/clang-tools-extra/clangd/TUScheduler.cpp
index 813a000b41a5f..7a858664faa5a 100644
--- a/clang-tools-extra/clangd/TUScheduler.cpp
+++ b/clang-tools-extra/clangd/TUScheduler.cpp
@@ -1220,7 +1220,7 @@ std::string renderTUAction(const PreambleAction PA, const ASTAction &AA) {
   }
   if (Result.empty())
     return "idle";
-  return llvm::join(Result, ",");
+  return llvm::join(Result, ", ");
 }
 
 } // namespace
diff --git a/clang-tools-extra/clangd/index/Merge.cpp b/clang-tools-extra/clangd/index/Merge.cpp
index 97babacf2b38e..f66f47499624a 100644
--- a/clang-tools-extra/clangd/index/Merge.cpp
+++ b/clang-tools-extra/clangd/index/Merge.cpp
@@ -76,7 +76,13 @@ void MergedIndex::lookup(
   Dynamic->lookup(Req, [&](const Symbol &S) { B.insert(S); });
 
   auto RemainingIDs = Req.IDs;
+  auto DynamicContainsFile = Dynamic->indexedFiles();
   Static->lookup(Req, [&](const Symbol &S) {
+    // We expect the definition to see the canonical declaration, so it seems
+    // to be enough to check only the definition if it exists.
+    if (DynamicContainsFile(S.Definition ? S.Definition.FileURI
+                                         : S.CanonicalDeclaration.FileURI))
+      return;
     const Symbol *Sym = B.find(S.ID);
     RemainingIDs.erase(S.ID);
     if (!Sym)
diff --git a/clang-tools-extra/clangd/index/remote/Client.cpp b/clang-tools-extra/clangd/index/remote/Client.cpp
index a153a8812baff..b09dbf915e462 100644
--- a/clang-tools-extra/clangd/index/remote/Client.cpp
+++ b/clang-tools-extra/clangd/index/remote/Client.cpp
@@ -152,8 +152,7 @@ class IndexClient : public clangd::SymbolIndex {
               });
   }
 
-  llvm::unique_function<bool(llvm::StringRef) const>
-  indexedFiles() const override {
+  llvm::unique_function<bool(llvm::StringRef) const> indexedFiles() const {
     // FIXME: For now we always return "false" regardless of whether the file
     //        was indexed or not. A possible implementation could be based on
     //        the idea that we do not want to send a request at every
diff --git a/clang-tools-extra/clangd/support/Threading.cpp b/clang-tools-extra/clangd/support/Threading.cpp
index 5f95888ae3e2d..7f3bd62be306c 100644
--- a/clang-tools-extra/clangd/support/Threading.cpp
+++ b/clang-tools-extra/clangd/support/Threading.cpp
@@ -116,5 +116,17 @@ void wait(std::unique_lock<std::mutex> &Lock, std::condition_variable &CV,
   CV.wait_until(Lock, D.time());
 }
 
+bool PeriodicThrottler::operator()() {
+  Rep Now = Stopwatch::now().time_since_epoch().count();
+  Rep OldNext = Next.load(std::memory_order_acquire);
+  if (Now < OldNext)
+    return false;
+  // We're ready to run (but may be racing other threads).
+  // Work out the updated target time, and run if we successfully bump it.
+  Rep NewNext = Now + Period;
+  return Next.compare_exchange_strong(OldNext, NewNext,
+                                      std::memory_order_acq_rel);
+}
+
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/clangd/support/Threading.h b/clang-tools-extra/clangd/support/Threading.h
index 5155ac193fd18..da9e3b8ea8b68 100644
--- a/clang-tools-extra/clangd/support/Threading.h
+++ b/clang-tools-extra/clangd/support/Threading.h
@@ -169,6 +169,35 @@ template <typename Container> class Memoize {
   }
 };
 
+/// Used to guard an operation that should run at most every N seconds.
+///
+/// Usage:
+///   mutable PeriodicThrottler ShouldLog(std::chrono::seconds(1));
+///   void calledFrequently() {
+///     if (ShouldLog())
+///       log("this is not spammy");
+///   }
+///
+/// This class is threadsafe. If multiple threads are involved, then the guarded
+/// operation still needs to be threadsafe!
+class PeriodicThrottler {
+  using Stopwatch = std::chrono::steady_clock;
+  using Rep = Stopwatch::duration::rep;
+
+  Rep Period;
+  std::atomic<Rep> Next;
+
+public:
+  /// If Period is zero, the throttler will return true every time.
+  PeriodicThrottler(Stopwatch::duration Period, Stopwatch::duration Delay = {})
+      : Period(Period.count()),
+        Next((Stopwatch::now() + Delay).time_since_epoch().count()) {}
+
+  /// Returns whether the operation should run at this time.
+  /// operator() is safe to call concurrently.
+  bool operator()();
+};
+
 } // namespace clangd
 } // namespace clang
 #endif
diff --git a/clang-tools-extra/clangd/tool/ClangdMain.cpp b/clang-tools-extra/clangd/tool/ClangdMain.cpp
index 331241115302b..d2c52cf61c53b 100644
--- a/clang-tools-extra/clangd/tool/ClangdMain.cpp
+++ b/clang-tools-extra/clangd/tool/ClangdMain.cpp
@@ -50,6 +50,10 @@
 #include <unistd.h>
 #endif
 
+#ifdef __GLIBC__
+#include <malloc.h>
+#endif
+
 namespace clang {
 namespace clangd {
 
@@ -497,6 +501,29 @@ opt<bool> CollectMainFileRefs{
     init(ClangdServer::Options().CollectMainFileRefs),
 };
 
+#if defined(__GLIBC__) && CLANGD_MALLOC_TRIM
+opt<bool> EnableMallocTrim{
+    "malloc-trim",
+    cat(Misc),
+    desc("Release memory periodically via malloc_trim(3)."),
+    init(true),
+};
+
+std::function<void()> getMemoryCleanupFunction() {
+  if (!EnableMallocTrim)
+    return nullptr;
+  // Leave a few MB at the top of the heap: it is insignificant
+  // and will most likely be needed by the main thread
+  constexpr size_t MallocTrimPad = 20'000'000;
+  return []() {
+    if (malloc_trim(MallocTrimPad))
+      vlog("Released memory via malloc_trim");
+  };
+}
+#else
+std::function<void()> getMemoryCleanupFunction() { return nullptr; }
+#endif
+
 #if CLANGD_ENABLE_REMOTE
 opt<std::string> RemoteIndexAddress{
     "remote-index-address",
@@ -797,6 +824,7 @@ clangd accepts flags on the commandline, and in the CLANGD_FLAGS environment var
   Opts.BuildRecoveryAST = RecoveryAST;
   Opts.PreserveRecoveryASTType = RecoveryASTType;
   Opts.FoldingRanges = FoldingRanges;
+  Opts.MemoryCleanup = getMemoryCleanupFunction();
 
   Opts.CodeComplete.IncludeIneligibleResults = IncludeIneligibleResults;
   Opts.CodeComplete.Limit = LimitResults;
diff --git a/clang-tools-extra/clangd/unittests/IndexTests.cpp b/clang-tools-extra/clangd/unittests/IndexTests.cpp
index 8efc637d1250b..ce4845e3e1446 100644
--- a/clang-tools-extra/clangd/unittests/IndexTests.cpp
+++ b/clang-tools-extra/clangd/unittests/IndexTests.cpp
@@ -290,6 +290,40 @@ TEST(MergeIndexTest, Lookup) {
   EXPECT_THAT(lookup(M, {}), UnorderedElementsAre());
 }
 
+TEST(MergeIndexTest, LookupRemovedDefinition) {
+  FileIndex DynamicIndex, StaticIndex;
+  MergedIndex Merge(&DynamicIndex, &StaticIndex);
+
+  const char *HeaderCode = "class Foo;";
+  auto HeaderSymbols = TestTU::withHeaderCode(HeaderCode).headerSymbols();
+  auto Foo = findSymbol(HeaderSymbols, "Foo");
+
+  // Build static index for test.cc with Foo definition
+  TestTU Test;
+  Test.HeaderCode = HeaderCode;
+  Test.Code = "class Foo {};";
+  Test.Filename = "test.cc";
+  auto AST = Test.build();
+  StaticIndex.updateMain(testPath(Test.Filename), AST);
+
+  // Remove Foo definition from test.cc, i.e. build dynamic index for test.cc
+  // without Foo definition.
+  Test.Code = "class Foo;";
+  AST = Test.build();
+  DynamicIndex.updateMain(testPath(Test.Filename), AST);
+
+  // Merged index should not return the symbol definition if this definition
+  // location is inside a file from the dynamic index.
+  LookupRequest LookupReq;
+  LookupReq.IDs = {Foo.ID};
+  unsigned SymbolCounter = 0;
+  Merge.lookup(LookupReq, [&](const Symbol &Sym) {
+    ++SymbolCounter;
+    EXPECT_FALSE(Sym.Definition);
+  });
+  EXPECT_EQ(SymbolCounter, 1u);
+}
+
 TEST(MergeIndexTest, FuzzyFind) {
   auto I = MemIndex::build(generateSymbols({"ns::A", "ns::B"}), RefSlab(),
                            RelationSlab()),
diff --git a/clang-tools-extra/clangd/unittests/support/ThreadingTests.cpp b/clang-tools-extra/clangd/unittests/support/ThreadingTests.cpp
index e265ad2eabeae..87002d3cfa86a 100644
--- a/clang-tools-extra/clangd/unittests/support/ThreadingTests.cpp
+++ b/clang-tools-extra/clangd/unittests/support/ThreadingTests.cpp
@@ -10,6 +10,7 @@
 #include "llvm/ADT/DenseMap.h"
 #include "gmock/gmock.h"
 #include "gtest/gtest.h"
+#include <chrono>
 #include <mutex>
 
 namespace clang {
@@ -121,5 +122,25 @@ TEST_F(ThreadingTest, MemoizeDeterministic) {
   ASSERT_THAT(ValueA.load(), testing::AnyOf('A', 'B'));
 }
 
+// It's hard to write a real test of this class, std::chrono is awkward to mock.
+// But test some degenerate cases at least.
+TEST(PeriodicThrottlerTest, Minimal) {
+  PeriodicThrottler Once(std::chrono::hours(24));
+  EXPECT_TRUE(Once());
+  EXPECT_FALSE(Once());
+  EXPECT_FALSE(Once());
+
+  PeriodicThrottler Later(std::chrono::hours(24),
+                          /*Delay=*/std::chrono::hours(24));
+  EXPECT_FALSE(Later());
+  EXPECT_FALSE(Later());
+  EXPECT_FALSE(Later());
+
+  PeriodicThrottler Always(std::chrono::seconds(0));
+  EXPECT_TRUE(Always());
+  EXPECT_TRUE(Always());
+  EXPECT_TRUE(Always());
+}
+
 } // namespace clangd
 } // namespace clang
diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst
index 450b80fd45814..2960aad5a5569 100644
--- a/clang-tools-extra/docs/ReleaseNotes.rst
+++ b/clang-tools-extra/docs/ReleaseNotes.rst
@@ -47,7 +47,17 @@ Major New Features
 Improvements to clangd
 ----------------------
 
-The improvements are...
+- clangd's memory usage is significantly reduced on most Linux systems.
+  In particular, memory usage should not increase dramatically over time.
+
+  The standard allocator on most systems is glibc's ptmalloc2, and it creates
+  disproportionately large heaps when handling clangd's allocation patterns.
+  By default, clangd will now periodically call ``malloc_trim`` to release free
+  pages on glibc systems.
+
+  Users of other allocators (such as ``jemalloc`` or ``tcmalloc``) on glibc
+  systems can disable this using ``--malloc_trim=0`` or the CMake flag
+  ``-DCLANGD_MALLOC_TRIM=0``.
 
 Improvements to clang-doc
 -------------------------
diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability-container-size-empty.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability-container-size-empty.cpp
index 9100559233e3c..4fe75f46932d7 100644
--- a/clang-tools-extra/test/clang-tidy/checkers/readability-container-size-empty.cpp
+++ b/clang-tools-extra/test/clang-tidy/checkers/readability-container-size-empty.cpp
@@ -1,4 +1,4 @@
-// RUN: %check_clang_tidy %s readability-container-size-empty %t
+// RUN: %check_clang_tidy %s readability-container-size-empty %t -- -- -fno-delayed-template-parsing
 
 namespace std {
 template <typename T> struct vector {
@@ -96,6 +96,11 @@ class Container4 {
   bool empty() const { return *this == Container4(); }
 };
 
+struct Lazy {
+  constexpr unsigned size() const { return 0; }
+  constexpr bool empty() const { return true; }
+};
+
 std::string s_func() {
   return std::string();
 }
@@ -440,6 +445,43 @@ bool returnsBool() {
   // CHECK-FIXES: {{^  }}return !derived.empty();
 }
 
+class ConstructWithBoolField {
+  bool B;
+public:
+  ConstructWithBoolField(const std::vector<int> &C) : B(C.size()) {}
+// CHECK-MESSAGES: :[[@LINE-1]]:57: warning: the 'empty' method should be used
+// CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+// CHECK-FIXES: {{^  }}ConstructWithBoolField(const std::vector<int> &C) : B(!C.empty()) {}
+};
+
+struct StructWithNSDMI {
+  std::vector<int> C;
+  bool B = C.size();
+// CHECK-MESSAGES: :[[@LINE-1]]:12: warning: the 'empty' method should be used
+// CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+// CHECK-FIXES: {{^  }}bool B = !C.empty();
+};
+
+int func(const std::vector<int> &C) {
+  return C.size() ? 0 : 1;
+// CHECK-MESSAGES: :[[@LINE-1]]:10: warning: the 'empty' method should be used
+// CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+// CHECK-FIXES: {{^  }}return !C.empty() ? 0 : 1;
+}
+
+constexpr Lazy L;
+static_assert(!L.size(), "");
+// CHECK-MESSAGES: :[[@LINE-1]]:16: warning: the 'empty' method should be used
+// CHECK-MESSAGES: :101:18: note: method 'Lazy'::empty() defined here
+// CHECK-FIXES: {{^}}static_assert(L.empty(), "");
+
+struct StructWithLazyNoexcept {
+  void func() noexcept(L.size());
+// CHECK-MESSAGES: :[[@LINE-1]]:24: warning: the 'empty' method should be used
+// CHECK-MESSAGES: :101:18: note: method 'Lazy'::empty() defined here
+// CHECK-FIXES: {{^  }}void func() noexcept(!L.empty());
+};
+
 #define CHECKSIZE(x) if (x.size()) {}
 // CHECK-FIXES: #define CHECKSIZE(x) if (x.size()) {}
 
@@ -483,3 +525,177 @@ void g() {
   f<double>();
   f<char *>();
 }
+
+template <typename T>
+bool neverInstantiatedTemplate() {
+  std::vector<T> v;
+  if (v.size())
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:7: warning: the 'empty' method should be used to check for emptiness instead of 'size' [readability-container-size-empty]
+  // CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (!v.empty()){{$}}
+
+  if (v == std::vector<T>())
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:7: warning: the 'empty' method should be used to check for emptiness instead of comparing to an empty object [readability-container-size-empty]
+  // CHECK-FIXES: {{^  }}if (v.empty()){{$}}
+  // CHECK-FIXES-NEXT: ;
+  if (v.size() == 0)
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:7: warning: the 'empty' method should be used to check for emptiness instead of 'size' [readability-container-size-empty]
+  // CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (v.empty()){{$}}
+  if (v.size() != 0)
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:7: warning: the 'empty' method should be used to check for emptiness instead of 'size' [readability-container-size-empty]
+  // CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (!v.empty()){{$}}
+  if (v.size() < 1)
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:7: warning: the 'empty' method should be used to check for emptiness instead of 'size' [readability-container-size-empty]
+  // CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (v.empty()){{$}}
+  if (v.size() > 0)
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:7: warning: the 'empty' method should be used to check for emptiness instead of 'size' [readability-container-size-empty]
+  // CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (!v.empty()){{$}}
+  if (v.size() == 1)
+    ;
+  if (v.size() != 1)
+    ;
+  if (v.size() == 2)
+    ;
+  if (v.size() != 2)
+    ;
+
+  if (static_cast<bool>(v.size()))
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:25: warning: the 'empty' method should be used to check for emptiness instead of 'size' [readability-container-size-empty]
+  // CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (static_cast<bool>(!v.empty())){{$}}
+  if (v.size() && false)
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:7: warning: the 'empty' method should be used to check for emptiness instead of 'size' [readability-container-size-empty]
+  // CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (!v.empty() && false){{$}}
+  if (!v.size())
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:8: warning: the 'empty' method should be used to check for emptiness instead of 'size' [readability-container-size-empty]
+  // CHECK-MESSAGES: :9:8: note: method 'vector'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (v.empty()){{$}}
+
+  TemplatedContainer<T> templated_container;
+  if (templated_container.size())
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:7: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (!templated_container.empty()){{$}}
+  if (templated_container != TemplatedContainer<T>())
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:7: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (!templated_container.empty()){{$}}
+  // CHECK-FIXES-NEXT: ;
+  while (templated_container.size())
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:10: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}while (!templated_container.empty()){{$}}
+
+  do {
+  }
+  while (templated_container.size());
+  // CHECK-MESSAGES: :[[@LINE-1]]:10: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}while (!templated_container.empty());
+
+  for (; templated_container.size();)
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:10: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}for (; !templated_container.empty();){{$}}
+
+  if (true && templated_container.size())
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:15: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (true && !templated_container.empty()){{$}}
+
+  if (true || templated_container.size())
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:15: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (true || !templated_container.empty()){{$}}
+
+  if (!templated_container.size())
+    ;
+  // CHECK-MESSAGES: :[[@LINE-2]]:8: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}if (templated_container.empty()){{$}}
+
+  bool b1 = templated_container.size();
+  // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}bool b1 = !templated_container.empty();
+
+  bool b2(templated_container.size());
+  // CHECK-MESSAGES: :[[@LINE-1]]:11: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}bool b2(!templated_container.empty());
+
+  auto b3 = static_cast<bool>(templated_container.size());
+  // CHECK-MESSAGES: :[[@LINE-1]]:31: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}auto b3 = static_cast<bool>(!templated_container.empty());
+
+  auto b4 = (bool)templated_container.size();
+  // CHECK-MESSAGES: :[[@LINE-1]]:19: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}auto b4 = (bool)!templated_container.empty();
+
+  auto b5 = bool(templated_container.size());
+  // CHECK-MESSAGES: :[[@LINE-1]]:18: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}auto b5 = bool(!templated_container.empty());
+
+  takesBool(templated_container.size());
+  // We don't detect this one because we don't know the parameter of takesBool
+  // until the type of templated_container.size() is known
+
+  return templated_container.size();
+  // CHECK-MESSAGES: :[[@LINE-1]]:10: warning: the 'empty' method should be used
+  // CHECK-MESSAGES: :44:8: note: method 'TemplatedContainer'::empty() defined here
+  // CHECK-FIXES: {{^  }}return !templated_container.empty();
+}
+
+template <typename TypeRequiresSize>
+void instantiatedTemplateWithSizeCall() {
+  TypeRequiresSize t;
+  // The instantiation of the template with std::vector<int> should not
+  // result in changing the template, because we don't know that
+  // TypeRequiresSize generally has `.empty()`
+  if (t.size())
+    ;
+
+  if (t == TypeRequiresSize{})
+    ;
+
+  if (t != TypeRequiresSize{})
+    ;
+}
+
+class TypeWithSize {
+public:
+  TypeWithSize();
+  bool operator==(const TypeWithSize &other) const;
+  bool operator!=(const TypeWithSize &other) const;
+
+  unsigned size() const { return 0; }
+  // Does not have `.empty()`
+};
+
+void instantiator() {
+  instantiatedTemplateWithSizeCall<TypeWithSize>();
+  instantiatedTemplateWithSizeCall<std::vector<int>>();
+}
diff --git a/clang/docs/ClangFormatStyleOptions.rst b/clang/docs/ClangFormatStyleOptions.rst
index 32942648378bb..c58bb1af7ae6a 100644
--- a/clang/docs/ClangFormatStyleOptions.rst
+++ b/clang/docs/ClangFormatStyleOptions.rst
@@ -2839,6 +2839,16 @@ the configuration (without a prefix: ``Auto``).
      int a = 5;                     vs.     int a= 5;
      a += 42;                               a+= 42;
 
+**SpaceBeforeCaseColon** (``bool``)
+  If ``false``, spaces will be removed before case colon.
+
+  .. code-block:: c++
+
+    true:                                   false
+    switch (x) {                    vs.     switch (x) {
+      case 1 : break;                         case 1: break;
+    }                                       }
+
 **SpaceBeforeCpp11BracedList** (``bool``)
   If ``true``, a space will be inserted before a C++11 braced list
   used to initialize an object (after the preceding identifier or type).
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index a3038aa03cded..76d4b6bb5acd5 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -118,6 +118,10 @@ Modified Compiler Flags
   `-fno-delete-null-pointer-checks` has gained the power to remove the
   `nonnull` attribute on `this` for configurations that need it to be nullable.
 - ``-gsplit-dwarf`` no longer implies ``-g2``.
+- ``-fasynchronous-unwind-tables`` is now the default on Linux AArch64/PowerPC.
+  This behavior matches newer GCC.
+  (`D91760 <https://reviews.llvm.org/D91760>`_)
+  (`D92054 <https://reviews.llvm.org/D92054>`_)
 
 Removed Compiler Flags
 -------------------------
@@ -289,6 +293,9 @@ clang-format
 
 - Option ``IndentPragmas`` has been added to allow #pragma to indented with the current scope level. This is especially useful when using #pragma to mark OpenMP sections of code.
 
+- Option ``SpaceBeforeCaseColon`` has been added to add a space before the
+  colon in a case or default statement.
+
 
 libclang
 --------
diff --git a/clang/docs/tools/dump_format_style.py b/clang/docs/tools/dump_format_style.py
index 61167979b3e6b..d01c823a9a20e 100755
--- a/clang/docs/tools/dump_format_style.py
+++ b/clang/docs/tools/dump_format_style.py
@@ -144,7 +144,7 @@ class State(object):
         comment += clean_comment_line(line)
       elif line.startswith('enum'):
         state = State.InEnum
-        name = re.sub(r'enum\s+(\w+)\s*\{', '\\1', line)
+        name = re.sub(r'enum\s+(\w+)\s*(:((\s*\w+)+)\s*)?\{', '\\1', line)
         enum = Enum(name, comment)
       elif line.startswith('struct'):
         state = State.InNestedStruct
diff --git a/clang/examples/Attribute/Attribute.cpp b/clang/examples/Attribute/Attribute.cpp
index 998f175dae546..159b09e4b154d 100644
--- a/clang/examples/Attribute/Attribute.cpp
+++ b/clang/examples/Attribute/Attribute.cpp
@@ -23,9 +23,10 @@ namespace {
 
 struct ExampleAttrInfo : public ParsedAttrInfo {
   ExampleAttrInfo() {
-    // Can take an optional string argument (the check that the argument
-    // actually is a string happens in handleDeclAttribute).
-    OptArgs = 1;
+    // Can take up to 15 optional arguments, to emulate accepting a variadic
+    // number of arguments. This just illustrates how many arguments a
+    // `ParsedAttrInfo` can hold, we will not use that much in this example.
+    OptArgs = 15;
     // GNU-style __attribute__(("example")) and C++-style [[example]] and
     // [[plugin::example]] supported.
     static constexpr Spelling S[] = {{ParsedAttr::AS_GNU, "example"},
@@ -39,7 +40,7 @@ struct ExampleAttrInfo : public ParsedAttrInfo {
     // This attribute appertains to functions only.
     if (!isa<FunctionDecl>(D)) {
       S.Diag(Attr.getLoc(), diag::warn_attribute_wrong_decl_type_str)
-        << Attr << "functions";
+          << Attr << "functions";
       return false;
     }
     return true;
@@ -55,23 +56,39 @@ struct ExampleAttrInfo : public ParsedAttrInfo {
       S.Diag(Attr.getLoc(), ID);
       return AttributeNotApplied;
     }
-    // Check if we have an optional string argument.
-    StringRef Str = "";
+    // We make some rules here:
+    // 1. Only accept at most 3 arguments here.
+    // 2. The first argument must be a string literal if it exists.
+    if (Attr.getNumArgs() > 3) {
+      unsigned ID = S.getDiagnostics().getCustomDiagID(
+          DiagnosticsEngine::Error,
+          "'example' attribute only accepts at most three arguments");
+      S.Diag(Attr.getLoc(), ID);
+      return AttributeNotApplied;
+    }
+    // If there are arguments, the first argument should be a string literal.
     if (Attr.getNumArgs() > 0) {
-      Expr *ArgExpr = Attr.getArgAsExpr(0);
+      auto *Arg0 = Attr.getArgAsExpr(0);
       StringLiteral *Literal =
-          dyn_cast<StringLiteral>(ArgExpr->IgnoreParenCasts());
-      if (Literal) {
-        Str = Literal->getString();
-      } else {
-        S.Diag(ArgExpr->getExprLoc(), diag::err_attribute_argument_type)
-            << Attr.getAttrName() << AANT_ArgumentString;
+          dyn_cast<StringLiteral>(Arg0->IgnoreParenCasts());
+      if (!Literal) {
+        unsigned ID = S.getDiagnostics().getCustomDiagID(
+            DiagnosticsEngine::Error, "first argument to the 'example' "
+                                      "attribute must be a string literal");
+        S.Diag(Attr.getLoc(), ID);
         return AttributeNotApplied;
       }
+      SmallVector<Expr *, 16> ArgsBuf;
+      for (unsigned i = 0; i < Attr.getNumArgs(); i++) {
+        ArgsBuf.push_back(Attr.getArgAsExpr(i));
+      }
+      D->addAttr(AnnotateAttr::Create(S.Context, "example", ArgsBuf.data(),
+                                      ArgsBuf.size(), Attr.getRange()));
+    } else {
+      // Attach an annotate attribute to the Decl.
+      D->addAttr(AnnotateAttr::Create(S.Context, "example", nullptr, 0,
+                                      Attr.getRange()));
     }
-    // Attach an annotate attribute to the Decl.
-    D->addAttr(AnnotateAttr::Create(S.Context, "example(" + Str.str() + ")",
-                                    Attr.getRange()));
     return AttributeApplied;
   }
 };
diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h
index 52b14d02a9fff..9ae17692a9faa 100644
--- a/clang/include/clang/AST/ASTContext.h
+++ b/clang/include/clang/AST/ASTContext.h
@@ -2823,8 +2823,8 @@ class ASTContext : public RefCountedBase<ASTContext> {
   /// for destruction.
   template <typename T> void addDestruction(T *Ptr) const {
     if (!std::is_trivially_destructible<T>::value) {
-      auto DestroyPtr = [](void *V) { ((T*)V)->~T(); };
-      AddDeallocation(DestroyPtr, (void*)Ptr);
+      auto DestroyPtr = [](void *V) { static_cast<T *>(V)->~T(); };
+      AddDeallocation(DestroyPtr, Ptr);
     }
   }
 
diff --git a/clang/include/clang/AST/Decl.h b/clang/include/clang/AST/Decl.h
index 618fd3f8beb28..8786c02c52c94 100644
--- a/clang/include/clang/AST/Decl.h
+++ b/clang/include/clang/AST/Decl.h
@@ -1665,6 +1665,9 @@ class ParmVarDecl : public VarDecl {
     return ParmVarDeclBits.IsObjCMethodParam;
   }
 
+  /// Determines whether this parameter is destroyed in the callee function.
+  bool isDestroyedInCallee() const;
+
   unsigned getFunctionScopeDepth() const {
     if (ParmVarDeclBits.IsObjCMethodParam) return 0;
     return ParmVarDeclBits.ScopeDepthOrObjCQuals;
diff --git a/clang/include/clang/AST/DependenceFlags.h b/clang/include/clang/AST/DependenceFlags.h
index 8c47047a7526d..ca96b65574bdd 100644
--- a/clang/include/clang/AST/DependenceFlags.h
+++ b/clang/include/clang/AST/DependenceFlags.h
@@ -255,12 +255,6 @@ inline TypeDependence toTypeDependence(TemplateNameDependence D) {
 inline TypeDependence toTypeDependence(TemplateArgumentDependence D) {
   return Dependence(D).type();
 }
-/// Compute the dependence of a type that depends on the type of an expression,
-/// given the dependence of that expression and of its type.
-inline TypeDependence typeToTypeDependence(ExprDependence ED, TypeDependence TD) {
-  return Dependence(ED & ~ExprDependence::Value).type() |
-         (TD & TypeDependence::VariablyModified);
-}
 
 inline NestedNameSpecifierDependence
 toNestedNameSpecifierDependendence(TypeDependence D) {
diff --git a/clang/include/clang/AST/Expr.h b/clang/include/clang/AST/Expr.h
index 15b81202c11a9..c91f1ca518741 100644
--- a/clang/include/clang/AST/Expr.h
+++ b/clang/include/clang/AST/Expr.h
@@ -578,12 +578,12 @@ class Expr : public ValueStmt {
   struct EvalStatus {
     /// Whether the evaluated expression has side effects.
     /// For example, (f() && 0) can be folded, but it still has side effects.
-    bool HasSideEffects = false;
+    bool HasSideEffects;
 
     /// Whether the evaluation hit undefined behavior.
     /// For example, 1.0 / 0.0 can be folded to Inf, but has undefined behavior.
     /// Likewise, INT_MAX + 1 can be folded to INT_MIN, but has UB.
-    bool HasUndefinedBehavior = false;
+    bool HasUndefinedBehavior;
 
     /// Diag - If this is non-null, it will be filled in with a stack of notes
     /// indicating why evaluation failed (or why it failed to produce a constant
@@ -592,7 +592,10 @@ class Expr : public ValueStmt {
     /// foldable. If the expression is foldable, but not a constant expression,
     /// the notes will describes why it isn't a constant expression. If the
     /// expression *is* a constant expression, no notes will be produced.
-    SmallVectorImpl<PartialDiagnosticAt> *Diag = nullptr;
+    SmallVectorImpl<PartialDiagnosticAt> *Diag;
+
+    EvalStatus()
+        : HasSideEffects(false), HasUndefinedBehavior(false), Diag(nullptr) {}
 
     // hasSideEffects - Return true if the evaluated expression has
     // side effects.
@@ -603,11 +606,8 @@ class Expr : public ValueStmt {
 
   /// EvalResult is a struct with detailed info about an evaluated expression.
   struct EvalResult : EvalStatus {
-    /// This is the value the expression can be folded to.
+    /// Val - This is the value the expression can be folded to.
     APValue Val;
-    /// Indicates whether Val contains a pointer or reference or pointer to
-    /// member naming a templated entity, and thus the value is dependent.
-    bool Dependent = false;
 
     // isGlobalLValue - Return true if the evaluated lvalue expression
     // is global.
diff --git a/clang/include/clang/AST/PropertiesBase.td b/clang/include/clang/AST/PropertiesBase.td
index dbe75ab9de194..ba0f237a3bc3c 100644
--- a/clang/include/clang/AST/PropertiesBase.td
+++ b/clang/include/clang/AST/PropertiesBase.td
@@ -72,7 +72,6 @@ class CountPropertyType<string typeName = ""> : PropertyType<typeName> {
 
 def APInt : PropertyType<"llvm::APInt"> { let PassByReference = 1; }
 def APSInt : PropertyType<"llvm::APSInt"> { let PassByReference = 1; }
-def APValue : PropertyType { let PassByReference = 1; }
 def ArraySizeModifier : EnumPropertyType<"ArrayType::ArraySizeModifier">;
 def AttrKind : EnumPropertyType<"attr::Kind">;
 def AutoTypeKeyword : EnumPropertyType;
@@ -451,17 +450,6 @@ let Class = PropertyTypeCase<TemplateArgument, "Integral"> in {
     return TemplateArgument(ctx, value, type);
   }]>;
 }
-let Class = PropertyTypeCase<TemplateArgument, "UncommonValue"> in {
-  def : Property<"value", APValue> {
-    let Read = [{ node.getAsUncommonValue() }];
-  }
-  def : Property<"type", QualType> {
-    let Read = [{ node.getUncommonValueType() }];
-  }
-  def : Creator<[{
-    return TemplateArgument(ctx, type, value);
-  }]>;
-}
 let Class = PropertyTypeCase<TemplateArgument, "Template"> in {
   def : Property<"name", TemplateName> {
     let Read = [{ node.getAsTemplateOrTemplatePattern() }];
diff --git a/clang/include/clang/AST/RecursiveASTVisitor.h b/clang/include/clang/AST/RecursiveASTVisitor.h
index 61e524793ec70..505ea700fd0e0 100644
--- a/clang/include/clang/AST/RecursiveASTVisitor.h
+++ b/clang/include/clang/AST/RecursiveASTVisitor.h
@@ -468,6 +468,8 @@ template <typename Derived> class RecursiveASTVisitor {
   DEF_TRAVERSE_TMPL_INST(Function)
 #undef DEF_TRAVERSE_TMPL_INST
 
+  bool dataTraverseNode(Stmt *S, DataRecursionQueue *Queue);
+
 private:
   // These are helper methods used by more than one Traverse* method.
   bool TraverseTemplateParameterListHelper(TemplateParameterList *TPL);
@@ -497,7 +499,6 @@ template <typename Derived> class RecursiveASTVisitor {
   bool VisitOMPClauseWithPreInit(OMPClauseWithPreInit *Node);
   bool VisitOMPClauseWithPostUpdate(OMPClauseWithPostUpdate *Node);
 
-  bool dataTraverseNode(Stmt *S, DataRecursionQueue *Queue);
   bool PostVisitStmt(Stmt *S);
 };
 
@@ -767,7 +768,6 @@ bool RecursiveASTVisitor<Derived>::TraverseTemplateArgument(
   case TemplateArgument::Declaration:
   case TemplateArgument::Integral:
   case TemplateArgument::NullPtr:
-  case TemplateArgument::UncommonValue:
     return true;
 
   case TemplateArgument::Type:
@@ -801,7 +801,6 @@ bool RecursiveASTVisitor<Derived>::TraverseTemplateArgumentLoc(
   case TemplateArgument::Declaration:
   case TemplateArgument::Integral:
   case TemplateArgument::NullPtr:
-  case TemplateArgument::UncommonValue:
     return true;
 
   case TemplateArgument::Type: {
diff --git a/clang/include/clang/AST/TemplateArgumentVisitor.h b/clang/include/clang/AST/TemplateArgumentVisitor.h
index 8c0da70b25eb9..190aa97adf455 100644
--- a/clang/include/clang/AST/TemplateArgumentVisitor.h
+++ b/clang/include/clang/AST/TemplateArgumentVisitor.h
@@ -37,7 +37,6 @@ class Base {
       DISPATCH(Declaration);
       DISPATCH(NullPtr);
       DISPATCH(Integral);
-      DISPATCH(UncommonValue);
       DISPATCH(Template);
       DISPATCH(TemplateExpansion);
       DISPATCH(Expression);
@@ -60,7 +59,6 @@ class Base {
   VISIT_METHOD(Declaration);
   VISIT_METHOD(NullPtr);
   VISIT_METHOD(Integral);
-  VISIT_METHOD(UncommonValue);
   VISIT_METHOD(Template);
   VISIT_METHOD(TemplateExpansion);
   VISIT_METHOD(Expression);
diff --git a/clang/include/clang/AST/TemplateBase.h b/clang/include/clang/AST/TemplateBase.h
index 9968143e87610..7967f8a91214d 100644
--- a/clang/include/clang/AST/TemplateBase.h
+++ b/clang/include/clang/AST/TemplateBase.h
@@ -51,7 +51,6 @@ template <> struct PointerLikeTypeTraits<clang::Expr *> {
 
 namespace clang {
 
-class APValue;
 class ASTContext;
 class DiagnosticBuilder;
 class Expr;
@@ -83,12 +82,6 @@ class TemplateArgument {
     /// that was provided for an integral non-type template parameter.
     Integral,
 
-    /// The template argument is a non-type template argument that can't be
-    /// represented by the special-case Declaration, NullPtr, or Integral
-    /// forms. These values are only ever produced by constant evaluation,
-    /// so cannot be dependent.
-    UncommonValue,
-
     /// The template argument is a template name that was provided for a
     /// template template parameter.
     Template,
@@ -132,11 +125,6 @@ class TemplateArgument {
     };
     void *Type;
   };
-  struct V {
-    unsigned Kind;
-    const APValue *Value;
-    void *Type;
-  };
   struct A {
     unsigned Kind;
     unsigned NumArgs;
@@ -154,7 +142,6 @@ class TemplateArgument {
   union {
     struct DA DeclArg;
     struct I Integer;
-    struct V Value;
     struct A Args;
     struct TA TemplateArg;
     struct TV TypeOrValue;
@@ -170,8 +157,9 @@ class TemplateArgument {
     TypeOrValue.V = reinterpret_cast<uintptr_t>(T.getAsOpaquePtr());
   }
 
-  /// Construct a template argument that refers to a (non-dependent)
-  /// declaration.
+  /// Construct a template argument that refers to a
+  /// declaration, which is either an external declaration or a
+  /// template declaration.
   TemplateArgument(ValueDecl *D, QualType QT) {
     assert(D && "Expected decl");
     DeclArg.Kind = Declaration;
@@ -181,11 +169,7 @@ class TemplateArgument {
 
   /// Construct an integral constant template argument. The memory to
   /// store the value is allocated with Ctx.
-  TemplateArgument(const ASTContext &Ctx, const llvm::APSInt &Value,
-                   QualType Type);
-
-  /// Construct a template argument from an arbitrary constant value.
-  TemplateArgument(const ASTContext &Ctx, QualType Type, const APValue &Value);
+  TemplateArgument(ASTContext &Ctx, const llvm::APSInt &Value, QualType Type);
 
   /// Construct an integral constant template argument with the same
   /// value as Other but a different type.
@@ -268,12 +252,6 @@ class TemplateArgument {
   /// Whether this template argument is dependent on a template
   /// parameter such that its result can change from one instantiation to
   /// another.
-  ///
-  /// It's not always meaningful to ask whether a template argument is
-  /// dependent before it's been converted to match a template parameter;
-  /// whether a non-type template argument is dependent depends on the
-  /// corresponding parameter. For an unconverted template argument, this
-  /// returns true if the argument *might* be dependent.
   bool isDependent() const;
 
   /// Whether this template argument is dependent on a template
@@ -356,16 +334,6 @@ class TemplateArgument {
     Integer.Type = T.getAsOpaquePtr();
   }
 
-  /// Get the value of an UncommonValue.
-  const APValue &getAsUncommonValue() const {
-    return *Value.Value;
-  }
-
-  /// Get the type of an UncommonValue.
-  QualType getUncommonValueType() const {
-    return QualType::getFromOpaquePtr(Value.Type);
-  }
-
   /// If this is a non-type template argument, get its type. Otherwise,
   /// returns a null QualType.
   QualType getNonTypeTemplateArgumentType() const;
@@ -510,7 +478,6 @@ class TemplateArgumentLoc {
     assert(Argument.getKind() == TemplateArgument::NullPtr ||
            Argument.getKind() == TemplateArgument::Integral ||
            Argument.getKind() == TemplateArgument::Declaration ||
-           Argument.getKind() == TemplateArgument::UncommonValue ||
            Argument.getKind() == TemplateArgument::Expression);
   }
 
@@ -569,11 +536,6 @@ class TemplateArgumentLoc {
     return LocInfo.getAsExpr();
   }
 
-  Expr *getSourceUncommonValueExpression() const {
-    assert(Argument.getKind() == TemplateArgument::UncommonValue);
-    return LocInfo.getAsExpr();
-  }
-
   NestedNameSpecifierLoc getTemplateQualifierLoc() const {
     if (Argument.getKind() != TemplateArgument::Template &&
         Argument.getKind() != TemplateArgument::TemplateExpansion)
@@ -712,6 +674,13 @@ struct alignas(void *) ASTTemplateKWAndArgsInfo {
   void initializeFrom(SourceLocation TemplateKWLoc,
                       const TemplateArgumentListInfo &List,
                       TemplateArgumentLoc *OutArgArray);
+  // FIXME: The parameter Deps is the result populated by this method, the
+  // caller doesn't need it since it is populated by computeDependence. remove
+  // it.
+  void initializeFrom(SourceLocation TemplateKWLoc,
+                      const TemplateArgumentListInfo &List,
+                      TemplateArgumentLoc *OutArgArray,
+                      TemplateArgumentDependence &Deps);
   void initializeFrom(SourceLocation TemplateKWLoc);
 
   void copyInto(const TemplateArgumentLoc *ArgArray,
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index 1b19a1dfef25e..9db57f64b5921 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -5428,9 +5428,7 @@ class ElaboratedType final
   ElaboratedType(ElaboratedTypeKeyword Keyword, NestedNameSpecifier *NNS,
                  QualType NamedType, QualType CanonType, TagDecl *OwnedTagDecl)
       : TypeWithKeyword(Keyword, Elaborated, CanonType,
-                        NamedType->getDependence() |
-                            (NNS ? toTypeDependence(NNS->getDependence())
-                                 : TypeDependence::None)),
+                        NamedType->getDependence()),
         NNS(NNS), NamedType(NamedType) {
     ElaboratedTypeBits.HasOwnedTagDecl = false;
     if (OwnedTagDecl) {
diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td
index ca9a8a20a4458..ead6e7952b80c 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -1149,7 +1149,6 @@ def SYCLDevice : InheritableAttr {
   let Subjects = SubjectList<[Function]>;
   let LangOpts = [SYCLIsDevice];
   let Documentation = [SYCLDeviceDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 def SYCLKernel : InheritableAttr {
@@ -1167,7 +1166,6 @@ def SYCLSimd : InheritableAttr {
   let Subjects = SubjectList<[Function]>;
   let LangOpts = [SYCLExplicitSIMD];
   let Documentation = [SYCLSimdDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 // Available in SYCL explicit SIMD extension. Binds a file scope private
@@ -1180,7 +1178,6 @@ def SYCLRegisterNum : InheritableAttr {
   // for the host device as well
   let LangOpts = [SYCLExplicitSIMD];
   let Documentation = [SYCLRegisterNumDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 // Used to mark ESIMD kernel pointer parameters originating from accessors.
@@ -1190,7 +1187,6 @@ def SYCLSimdAccessorPtr : InheritableAttr {
   let Subjects = SubjectList<[ParmVar]>;
   let LangOpts = [SYCLExplicitSIMD];
   let Documentation = [SYCLSimdAccessorPtrDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 def SYCLScope : Attr {
@@ -1219,7 +1215,6 @@ def SYCLDeviceIndirectlyCallable : InheritableAttr {
   let Subjects = SubjectList<[Function]>;
   let LangOpts = [SYCLIsDevice];
   let Documentation = [SYCLDeviceIndirectlyCallableDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 def SYCLIntelBufferLocation : InheritableAttr {
@@ -1244,7 +1239,6 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr {
   let LangOpts = [ SYCLIsDevice, SYCLIsHost ];
   let Documentation = [ SYCLIntelKernelArgsRestrictDocs ];
   let SimpleHandler = 1;
-  let PragmaAttributeSupport = 0;
 }
 
 def SYCLIntelNumSimdWorkItems : InheritableAttr {
@@ -1254,7 +1248,6 @@ def SYCLIntelNumSimdWorkItems : InheritableAttr {
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let Subjects = SubjectList<[Function], ErrorDiag>;
   let Documentation = [SYCLIntelNumSimdWorkItemsAttrDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 def SYCLIntelUseStallEnableClusters : InheritableAttr {
@@ -1267,7 +1260,6 @@ def SYCLIntelUseStallEnableClusters : InheritableAttr {
     }
   }];
   let Documentation = [SYCLIntelUseStallEnableClustersAttrDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
@@ -1277,7 +1269,6 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let Subjects = SubjectList<[Function], ErrorDiag>;
   let Documentation = [SYCLIntelSchedulerTargetFmaxMhzAttrDocs];
-  let PragmaAttributeSupport = 0;
   let AdditionalMembers = [{
     static unsigned getMinValue() {
       return 0;
@@ -1286,7 +1277,6 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
       return 1024*1024;
     }
   }];
-
 }
 
 def SYCLIntelMaxWorkGroupSize : InheritableAttr {
@@ -1297,11 +1287,19 @@ def SYCLIntelMaxWorkGroupSize : InheritableAttr {
               ExprArgument<"ZDim">];
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let Subjects = SubjectList<[Function], ErrorDiag>;
-  let PragmaAttributeSupport = 0;
   let AdditionalMembers = [{
     ArrayRef<const Expr *> dimensions() const {
       return {getXDim(), getYDim(), getZDim()};
     }
+    Optional<llvm::APSInt> getXDimVal(ASTContext &Ctx) const {
+      return getXDim()->getIntegerConstantExpr(Ctx);
+    }
+    Optional<llvm::APSInt> getYDimVal(ASTContext &Ctx) const {
+      return getYDim()->getIntegerConstantExpr(Ctx);
+    }
+    Optional<llvm::APSInt> getZDimVal(ASTContext &Ctx) const {
+      return getZDim()->getIntegerConstantExpr(Ctx);
+    }
   }];
   let Documentation = [SYCLIntelMaxWorkGroupSizeAttrDocs];
 }
@@ -1313,7 +1311,6 @@ def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let Subjects = SubjectList<[Function], ErrorDiag>;
   let Documentation = [SYCLIntelMaxGlobalWorkDimAttrDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
@@ -1323,7 +1320,6 @@ def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let Subjects = SubjectList<[Function], ErrorDiag>;
   let Documentation = [SYCLIntelNoGlobalWorkOffsetAttrDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 def SYCLIntelLoopFuse : InheritableAttr {
@@ -1404,7 +1400,6 @@ def IntelReqdSubGroupSize: InheritableAttr {
   let Subjects = SubjectList<[Function, CXXMethod], ErrorDiag>;
   let Documentation = [IntelReqdSubGroupSizeDocs];
   let LangOpts = [OpenCL, SYCLIsDevice, SYCLIsHost];
-  let PragmaAttributeSupport = 0;
 }
 
 // This attribute is both a type attribute, and a declaration attribute (for
@@ -2124,7 +2119,6 @@ def SYCLIntelPipeIO : Attr {
   let LangOpts = [SYCLIsDevice, SYCLIsHost];
   let Subjects = SubjectList<[Var]>;
   let Documentation = [SYCLIntelPipeIOAttrDocs];
-  let PragmaAttributeSupport = 0;
 }
 
 // Variadic integral arguments.
@@ -2853,6 +2847,15 @@ def ReqdWorkGroupSize : InheritableAttr {
     ArrayRef<const Expr *> dimensions() const {
       return {getXDim(), getYDim(), getZDim()};
     }
+    Optional<llvm::APSInt> getXDimVal(ASTContext &Ctx) const {
+      return getXDim()->getIntegerConstantExpr(Ctx);
+    }
+    Optional<llvm::APSInt> getYDimVal(ASTContext &Ctx) const {
+      return getYDim()->getIntegerConstantExpr(Ctx);
+    }
+    Optional<llvm::APSInt> getZDimVal(ASTContext &Ctx) const {
+      return getZDim()->getIntegerConstantExpr(Ctx);
+    }
   }];
   let Documentation = [ReqdWorkGroupSizeAttrDocs];
 }
diff --git a/clang/include/clang/Basic/CodeGenOptions.h b/clang/include/clang/Basic/CodeGenOptions.h
index ef4fa31256cd4..5c540812ed312 100644
--- a/clang/include/clang/Basic/CodeGenOptions.h
+++ b/clang/include/clang/Basic/CodeGenOptions.h
@@ -30,8 +30,6 @@ namespace clang {
 /// Bitfields of CodeGenOptions, split out from CodeGenOptions to ensure
 /// that this large collection of bitfields is a trivial class type.
 class CodeGenOptionsBase {
-  friend class CompilerInvocation;
-
 public:
 #define CODEGENOPT(Name, Bits, Default) unsigned Name : Bits;
 #define ENUM_CODEGENOPT(Name, Type, Bits, Default)
diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td
index 61cdf13154818..2a3acc3efdfd0 100644
--- a/clang/include/clang/Basic/DiagnosticDriverKinds.td
+++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td
@@ -89,6 +89,8 @@ def err_drv_invalid_thread_model_for_target : Error<
   "invalid thread model '%0' in '%1' for this target">;
 def err_drv_invalid_linker_name : Error<
   "invalid linker name in argument '%0'">;
+def err_drv_invalid_pgo_instrumentor : Error<
+  "invalid PGO instrumentor in argument '%0'">;
 def err_drv_invalid_rtlib_name : Error<
   "invalid runtime library name in argument '%0'">;
 def err_drv_unsupported_rtlib_for_platform : Error<
diff --git a/clang/include/clang/Basic/DiagnosticFrontendKinds.td b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
index b9f8c78e43da8..def189f659947 100644
--- a/clang/include/clang/Basic/DiagnosticFrontendKinds.td
+++ b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
@@ -108,6 +108,8 @@ def err_fe_action_not_available : Error<
     "action %0 not compiled in">;
 def err_fe_invalid_alignment : Error<
     "invalid value '%1' in '%0'; alignment must be a power of 2">;
+def err_fe_invalid_wchar_type
+    : Error<"invalid wchar_t type '%0'; must be one of 'char', 'short', 'int'">;
 def err_fe_invalid_exception_model
    : Error<"invalid exception model '%select{none|dwarf|sjlj|arm|seh|wasm|aix}0' for target '%1'">;
 def warn_fe_concepts_ts_flag : Warning<
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index eafded7e4455e..9847824cfb291 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -4695,6 +4695,8 @@ def err_non_type_template_arg_subobject : Error<
   "non-type template argument refers to subobject '%0'">;
 def err_non_type_template_arg_addr_label_diff : Error<
   "template argument / label address difference / what did you expect?">;
+def err_non_type_template_arg_unsupported : Error<
+  "sorry, non-type template argument of type %0 is not yet supported">;
 def err_template_arg_not_convertible : Error<
   "non-type template argument of type %0 cannot be converted to a value "
   "of type %1">;
@@ -4746,6 +4748,9 @@ def err_template_arg_not_object_or_func : Error<
   "non-type template argument does not refer to an object or function">;
 def err_template_arg_not_pointer_to_member_form : Error<
   "non-type template argument is not a pointer to member constant">;
+def err_template_arg_member_ptr_base_derived_not_supported : Error<
+  "sorry, non-type template argument of pointer-to-member type %1 that refers "
+  "to member %q0 of a different class is not supported yet">;
 def ext_template_arg_extra_parens : ExtWarn<
   "address non-type template argument cannot be surrounded by parentheses">;
 def warn_cxx98_compat_template_arg_extra_parens : Warning<
diff --git a/clang/include/clang/Basic/FileEntry.h b/clang/include/clang/Basic/FileEntry.h
index aa7bedec44ac1..6e91b42e18b71 100644
--- a/clang/include/clang/Basic/FileEntry.h
+++ b/clang/include/clang/Basic/FileEntry.h
@@ -25,6 +25,9 @@
 #include "llvm/Support/FileSystem/UniqueID.h"
 
 namespace llvm {
+
+class MemoryBuffer;
+
 namespace vfs {
 
 class File;
@@ -67,6 +70,7 @@ class FileEntryRef {
   inline unsigned getUID() const;
   inline const llvm::sys::fs::UniqueID &getUniqueID() const;
   inline time_t getModificationTime() const;
+  inline bool isNamedPipe() const;
   inline void closeFile() const;
 
   /// Check if the underlying FileEntry is the same, intentially ignoring
@@ -339,6 +343,9 @@ class FileEntry {
   /// The open file, if it is owned by the \p FileEntry.
   mutable std::unique_ptr<llvm::vfs::File> File;
 
+  /// The file content, if it is owned by the \p FileEntry.
+  std::unique_ptr<llvm::MemoryBuffer> Content;
+
   // First access name for this FileEntry.
   //
   // This is Optional only to allow delayed construction (FileEntryRef has no
@@ -390,6 +397,8 @@ time_t FileEntryRef::getModificationTime() const {
   return getFileEntry().getModificationTime();
 }
 
+bool FileEntryRef::isNamedPipe() const { return getFileEntry().isNamedPipe(); }
+
 void FileEntryRef::closeFile() const { getFileEntry().closeFile(); }
 
 } // end namespace clang
diff --git a/clang/include/clang/Basic/FileManager.h b/clang/include/clang/Basic/FileManager.h
index 449aec2b3541e..974771a8f8f39 100644
--- a/clang/include/clang/Basic/FileManager.h
+++ b/clang/include/clang/Basic/FileManager.h
@@ -99,6 +99,9 @@ class FileManager : public RefCountedBase<FileManager> {
   std::unique_ptr<llvm::StringMap<llvm::ErrorOr<FileEntryRef::MapValue>>>
       SeenBypassFileEntries;
 
+  /// The file entry for stdin, if it has been accessed through the FileManager.
+  Optional<FileEntryRef> STDIN;
+
   /// The canonical names of files and directories .
   llvm::DenseMap<const void *, llvm::StringRef> CanonicalNames;
 
@@ -217,6 +220,14 @@ class FileManager : public RefCountedBase<FileManager> {
                                           bool OpenFile = false,
                                           bool CacheFailure = true);
 
+  /// Get the FileEntryRef for stdin, returning an error if stdin cannot be
+  /// read.
+  ///
+  /// This reads and caches stdin before returning. Subsequent calls return the
+  /// same file entry, and a reference to the cached input is returned by calls
+  /// to getBufferForFile.
+  llvm::Expected<FileEntryRef> getSTDIN();
+
   /// Get a FileEntryRef if it exists, without doing anything on error.
   llvm::Optional<FileEntryRef> getOptionalFileRef(StringRef Filename,
                                                   bool OpenFile = false,
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
index 4187eba05d459..1d22e07246e9b 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -698,7 +698,7 @@ def O_flag : Flag<["-"], "O">, Flags<[CC1Option]>, Alias<O>, AliasArgs<["1"]>;
 def Ofast : Joined<["-"], "Ofast">, Group<O_Group>, Flags<[CC1Option]>;
 def P : Flag<["-"], "P">, Flags<[CC1Option]>, Group<Preprocessor_Group>,
   HelpText<"Disable linemarker output in -E mode">,
-  MarshallingInfoNegativeFlag<"PreprocessorOutputOpts.ShowLineMarkers">;
+  MarshallingInfoFlag<"PreprocessorOutputOpts.ShowLineMarkers", "true">, IsNegative;
 def Qy : Flag<["-"], "Qy">, Flags<[CC1Option]>,
   HelpText<"Emit metadata containing compiler name and version">;
 def Qn : Flag<["-"], "Qn">, Flags<[CC1Option]>,
@@ -930,10 +930,8 @@ def fcuda_flush_denormals_to_zero : Flag<["-"], "fcuda-flush-denormals-to-zero">
 def fno_cuda_flush_denormals_to_zero : Flag<["-"], "fno-cuda-flush-denormals-to-zero">;
 defm cuda_approx_transcendentals : OptInFFlag<"cuda-approx-transcendentals", "Use", "Don't use",
   " approximate transcendental functions">;
-defm gpu_rdc : BoolFOption<"gpu-rdc",
-  "LangOpts->GPURelocatableDeviceCode", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Generate relocatable device code, also known as separate compilation mode">,
-  ResetBy<NegFlag>>;
+defm gpu_rdc : OptInFFlag<"gpu-rdc",
+  "Generate relocatable device code, also known as separate compilation mode", "", "">;
 def : Flag<["-"], "fcuda-rdc">, Alias<fgpu_rdc>;
 def : Flag<["-"], "fno-cuda-rdc">, Alias<fno_gpu_rdc>;
 defm cuda_short_ptr : OptInFFlag<"cuda-short-ptr",
@@ -950,21 +948,16 @@ def hip_version_EQ : Joined<["--"], "hip-version=">,
   HelpText<"HIP version in the format of major.minor.patch">;
 def fhip_dump_offload_linker_script : Flag<["-"], "fhip-dump-offload-linker-script">,
   Group<f_Group>, Flags<[NoArgumentUnused, HelpHidden]>;
-defm hip_new_launch_api : BoolFOption<"hip-new-launch-api",
-  "LangOpts->HIPUseNewLaunchAPI", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Use">, ResetBy<NegFlag, [], "Don't use">,
-  BothFlags<[], " new kernel launching API for HIP">>;
+defm hip_new_launch_api : OptInFFlag<"hip-new-launch-api",
+  "Use", "Don't use", " new kernel launching API for HIP">;
 defm gpu_allow_device_init : OptInFFlag<"gpu-allow-device-init",
   "Allow", "Don't allow", " device side init function in HIP">;
-defm gpu_defer_diag : BoolFOption<"gpu-defer-diag",
-  "LangOpts->GPUDeferDiag", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Defer">, ResetBy<NegFlag, [], "Don't defer">,
-  BothFlags<[], " host/device related diagnostic messages for CUDA/HIP">>;
-defm gpu_exclude_wrong_side_overloads : BoolFOption<"gpu-exclude-wrong-side-overloads",
-  "LangOpts->GPUExcludeWrongSideOverloads", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Always exclude wrong side overloads">,
-  ResetBy<NegFlag, [], "Exclude wrong side overloads only if there are same side overloads">,
-  BothFlags<[HelpHidden], " in overloading resolution for CUDA/HIP">>;
+defm gpu_defer_diag : OptInFFlag<"gpu-defer-diag",
+  "Defer", "Don't defer", " host/device related diagnostic messages"
+  " for CUDA/HIP">;
+defm gpu_exclude_wrong_side_overloads : OptInFFlag<"gpu-exclude-wrong-side-overloads",
+  "Always exclude wrong side overloads", "Exclude wrong side overloads only if there are same side overloads",
+  " in overloading resolution for CUDA/HIP", [HelpHidden]>;
 def gpu_max_threads_per_block_EQ : Joined<["--"], "gpu-max-threads-per-block=">,
   Flags<[CC1Option]>,
   HelpText<"Default max threads per block for kernel launch bounds for HIP">;
@@ -1016,31 +1009,21 @@ def interface_stub_version_EQ : JoinedOrSeparate<["-"], "interface-stub-version=
 def exported__symbols__list : Separate<["-"], "exported_symbols_list">;
 def e : JoinedOrSeparate<["-"], "e">, Flags<[LinkerInput]>, Group<Link_Group>;
 def fmax_tokens_EQ : Joined<["-"], "fmax-tokens=">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Max total number of preprocessed tokens for -Wmax-tokens.">,
-  MarshallingInfoStringInt<"LangOpts->MaxTokens">;
+  HelpText<"Max total number of preprocessed tokens for -Wmax-tokens.">;
 def fPIC : Flag<["-"], "fPIC">, Group<f_Group>;
 def fno_PIC : Flag<["-"], "fno-PIC">, Group<f_Group>;
 def fPIE : Flag<["-"], "fPIE">, Group<f_Group>;
 def fno_PIE : Flag<["-"], "fno-PIE">, Group<f_Group>;
-defm access_control : BoolFOption<"access-control",
-  "LangOpts->AccessControl", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Disable C++ access control">,
-  ResetBy<PosFlag>>;
+defm access_control : OptOutFFlag<"access-control", "", "Disable C++ access control">;
 def falign_functions : Flag<["-"], "falign-functions">, Group<f_Group>;
 def falign_functions_EQ : Joined<["-"], "falign-functions=">, Group<f_Group>;
 def fno_align_functions: Flag<["-"], "fno-align-functions">, Group<f_Group>;
-defm allow_editor_placeholders : BoolFOption<"allow-editor-placeholders",
-  "LangOpts->AllowEditorPlaceholders", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Treat editor placeholders as valid source code">,
-  ResetBy<NegFlag>>;
+defm allow_editor_placeholders : OptInFFlag<"allow-editor-placeholders", "Treat editor placeholders as valid source code">;
 def fallow_unsupported : Flag<["-"], "fallow-unsupported">, Group<f_Group>;
 def fapple_kext : Flag<["-"], "fapple-kext">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Use Apple's kernel extensions ABI">,
-  MarshallingInfoFlag<"LangOpts->AppleKext">;
-defm apple_pragma_pack : BoolFOption<"apple-pragma-pack",
-  "LangOpts->ApplePragmaPack", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable Apple gcc-compatible #pragma pack handling">,
-  ResetBy<NegFlag>>;
+  HelpText<"Use Apple's kernel extensions ABI">;
+def fapple_pragma_pack : Flag<["-"], "fapple-pragma-pack">, Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Enable Apple gcc-compatible #pragma pack handling">;
 def shared_libsan : Flag<["-"], "shared-libsan">,
   HelpText<"Dynamically link the sanitizer runtime">;
 def static_libsan : Flag<["-"], "static-libsan">,
@@ -1073,19 +1056,14 @@ defm coroutines_ts : OptInFFlag<"coroutines-ts", "Enable support for the C++ Cor
 
 def fembed_bitcode_EQ : Joined<["-"], "fembed-bitcode=">,
     Group<f_Group>, Flags<[NoXarchOption, CC1Option, CC1AsOption]>, MetaVarName<"<option>">,
-    HelpText<"Embed LLVM bitcode (option: off, all, bitcode, marker)">,
-    Values<"off,all,bitcode,marker">, NormalizedValuesScope<"CodeGenOptions">,
-    NormalizedValues<["Embed_Off", "Embed_All", "Embed_Bitcode", "Embed_Marker"]>,
-    MarshallingInfoString<"CodeGenOpts.EmbedBitcode", "Embed_Off">, AutoNormalizeEnum;
+    HelpText<"Embed LLVM bitcode (option: off, all, bitcode, marker)">;
 def fembed_bitcode : Flag<["-"], "fembed-bitcode">, Group<f_Group>,
   Alias<fembed_bitcode_EQ>, AliasArgs<["all"]>,
   HelpText<"Embed LLVM IR bitcode as data">;
 def fembed_bitcode_marker : Flag<["-"], "fembed-bitcode-marker">,
   Alias<fembed_bitcode_EQ>, AliasArgs<["marker"]>,
   HelpText<"Embed placeholder LLVM IR data as a marker">;
-defm gnu_inline_asm : BoolFOption<"gnu-inline-asm",
-  "LangOpts->GNUAsm", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Disable GNU style inline asm">, ResetBy<PosFlag>>;
+defm gnu_inline_asm : OptOutFFlag<"gnu-inline-asm", "", "Disable GNU style inline asm">;
 
 def fprofile_sample_use : Flag<["-"], "fprofile-sample-use">, Group<f_Group>,
     Flags<[CoreOption]>;
@@ -1093,16 +1071,14 @@ def fno_profile_sample_use : Flag<["-"], "fno-profile-sample-use">, Group<f_Grou
     Flags<[CoreOption]>;
 def fprofile_sample_use_EQ : Joined<["-"], "fprofile-sample-use=">,
     Group<f_Group>, Flags<[NoXarchOption, CC1Option]>,
-    HelpText<"Enable sample-based profile guided optimizations">,
-    MarshallingInfoString<"CodeGenOpts.SampleProfileFile">;
+    HelpText<"Enable sample-based profile guided optimizations">;
 def fprofile_sample_accurate : Flag<["-"], "fprofile-sample-accurate">,
     Group<f_Group>, Flags<[NoXarchOption, CC1Option]>,
     HelpText<"Specifies that the sample profile is accurate">,
     DocBrief<[{Specifies that the sample profile is accurate. If the sample
                profile is accurate, callsites without profile samples are marked
                as cold. Otherwise, treat callsites without profile samples as if
-               we have no profile}]>,
-   MarshallingInfoFlag<"CodeGenOpts.ProfileSampleAccurate">;
+               we have no profile}]>;
 def fno_profile_sample_accurate : Flag<["-"], "fno-profile-sample-accurate">,
   Group<f_Group>, Flags<[NoXarchOption]>;
 def fauto_profile : Flag<["-"], "fauto-profile">, Group<f_Group>,
@@ -1117,15 +1093,12 @@ def fno_auto_profile_accurate : Flag<["-"], "fno-auto-profile-accurate">,
     Group<f_Group>, Alias<fno_profile_sample_accurate>;
 def fdebug_compilation_dir : Separate<["-"], "fdebug-compilation-dir">,
     Group<f_Group>, Flags<[CC1Option, CC1AsOption, CoreOption]>,
-    HelpText<"The compilation directory to embed in the debug info.">,
-    MarshallingInfoString<"CodeGenOpts.DebugCompilationDir">;
+    HelpText<"The compilation directory to embed in the debug info.">;
 def fdebug_compilation_dir_EQ : Joined<["-"], "fdebug-compilation-dir=">,
     Group<f_Group>, Flags<[CC1Option, CC1AsOption, CoreOption]>,
     Alias<fdebug_compilation_dir>;
-defm debug_info_for_profiling : BoolFOption<"debug-info-for-profiling",
-  "CodeGenOpts.DebugInfoForProfiling", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Emit extra debug info to make sample profile more accurate">,
-  ResetBy<NegFlag>>;
+defm debug_info_for_profiling : OptInFFlag<"debug-info-for-profiling",
+  "Emit extra debug info to make sample profile more accurate">;
 def fprofile_instr_generate : Flag<["-"], "fprofile-instr-generate">,
     Group<f_Group>, Flags<[CoreOption]>,
     HelpText<"Generate instrumented code to collect execution counts into default.profraw file (overridden by '=' form of option or LLVM_PROFILE_FILE env var)">;
@@ -1139,14 +1112,12 @@ def fprofile_instr_use_EQ : Joined<["-"], "fprofile-instr-use=">,
     HelpText<"Use instrumentation data for profile-guided optimization">;
 def fprofile_remapping_file_EQ : Joined<["-"], "fprofile-remapping-file=">,
     Group<f_Group>, Flags<[CC1Option, CoreOption]>, MetaVarName<"<file>">,
-    HelpText<"Use the remappings described in <file> to match the profile data against names in the program">,
-    MarshallingInfoString<"CodeGenOpts.ProfileRemappingFile">;
+    HelpText<"Use the remappings described in <file> to match the profile data against names in the program">;
 def fprofile_remapping_file : Separate<["-"], "fprofile-remapping-file">,
     Group<f_Group>, Flags<[CoreOption]>, Alias<fprofile_remapping_file_EQ>;
-defm coverage_mapping : BoolFOption<"coverage-mapping",
-  "CodeGenOpts.CoverageMapping", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Generate coverage mapping to enable code coverage analysis">,
-  ResetBy<NegFlag, [], "Disable code coverage analysis">, BothFlags<[CoreOption]>>;
+defm coverage_mapping : OptInFFlag<"coverage-mapping",
+  "Generate coverage mapping to enable code coverage analysis", "Disable code coverage analysis", "",
+  [CoreOption]>;
 def fprofile_generate : Flag<["-"], "fprofile-generate">,
     Group<f_Group>, Flags<[CoreOption]>,
     HelpText<"Generate instrumented code to collect execution counts into default.profraw (overridden by LLVM_PROFILE_FILE env var)">;
@@ -1183,26 +1154,22 @@ def fprofile_exclude_files_EQ : Joined<["-"], "fprofile-exclude-files=">,
     HelpText<"Instrument only functions from files where names don't match all the regexes separated by a semi-colon">;
 def fprofile_update_EQ : Joined<["-"], "fprofile-update=">,
     Group<f_Group>, Flags<[CC1Option, CoreOption]>, Values<"atomic,prefer-atomic,single">,
-    MetaVarName<"<method>">, HelpText<"Set update method of profile counters (atomic,prefer-atomic,single)">,
-    MarshallingInfoFlag<"CodeGenOpts.AtomicProfileUpdate">;
-defm pseudo_probe_for_profiling : BoolFOption<"pseudo-probe-for-profiling",
-  "CodeGenOpts.PseudoProbeForProfiling", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Emit">, ResetBy<NegFlag, [], "Do not emit">,
-  BothFlags<[NoXarchOption, CC1Option], " pseudo probes for sample profiler">>;
+    MetaVarName<"<method>">, HelpText<"Set update method of profile counters (atomic,prefer-atomic,single)">;
+def fpseudo_probe_for_profiling : Flag<["-"], "fpseudo-probe-for-profiling">,
+    Group<f_Group>, Flags<[NoXarchOption, CC1Option]>,
+    HelpText<"Emit pseudo probes for sample profiler">;
+def fno_pseudo_probe_for_profiling : Flag<["-"], "fno-pseudo-probe-for-profiling">,
+    Group<f_Group>, Flags<[NoXarchOption, CC1Option]>,
+    HelpText<"Do not emit pseudo probes for sample profiler.">;
 def forder_file_instrumentation : Flag<["-"], "forder-file-instrumentation">,
     Group<f_Group>, Flags<[CC1Option, CoreOption]>,
     HelpText<"Generate instrumented code to collect order file into default.profraw file (overridden by '=' form of option or LLVM_PROFILE_FILE env var)">;
 
-defm addrsig : BoolFOption<"addrsig",
-  "CodeGenOpts.Addrsig", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Emit">, ResetBy<NegFlag, [], "Don't emit">,
-  BothFlags<[CoreOption], " an address-significance table">>;
+defm addrsig : OptInFFlag<"addrsig", "Emit", "Don't emit", " an address-significance table", [CoreOption]>;
 defm blocks : OptInFFlag<"blocks", "Enable the 'blocks' language feature", "", "", [CoreOption]>;
 def fbootclasspath_EQ : Joined<["-"], "fbootclasspath=">, Group<f_Group>;
-defm borland_extensions : BoolFOption<"borland-extensions",
-  "LangOpts->Borland", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Accept non-standard constructs supported by the Borland compiler">,
-  ResetBy<NegFlag>>;
+def fborland_extensions : Flag<["-"], "fborland-extensions">, Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Accept non-standard constructs supported by the Borland compiler">;
 def fbuiltin : Flag<["-"], "fbuiltin">, Group<f_Group>, Flags<[CoreOption]>;
 def fbuiltin_module_map : Flag <["-"], "fbuiltin-module-map">, Group<f_Group>,
   Flags<[NoXarchOption]>, HelpText<"Load the clang builtins module map file.">;
@@ -1231,39 +1198,29 @@ def fno_record_command_line : Flag<["-"], "fno-record-command-line">,
 def : Flag<["-"], "frecord-gcc-switches">, Alias<frecord_command_line>;
 def : Flag<["-"], "fno-record-gcc-switches">, Alias<fno_record_command_line>;
 def fcommon : Flag<["-"], "fcommon">, Group<f_Group>,
-  Flags<[CoreOption, CC1Option]>, HelpText<"Place uninitialized global variables in a common block">,
-  MarshallingInfoNegativeFlag<"CodeGenOpts.NoCommon">;
+  Flags<[CoreOption, CC1Option]>, HelpText<"Place uninitialized global variables in a common block">;
 def fcompile_resource_EQ : Joined<["-"], "fcompile-resource=">, Group<f_Group>;
-defm complete_member_pointers : BoolOption<"complete-member-pointers",
-  "LangOpts->CompleteMemberPointers", DefaultsToFalse,
-  ChangedBy<PosFlag, [CC1Option], "Require">, ResetBy<NegFlag, [], "Do not require">,
-  BothFlags<[CoreOption], " member pointer base types to be complete if they"
-            " would be significant under the Microsoft ABI">, "f">,
-  Group<f_clang_Group>;
+def fcomplete_member_pointers : Flag<["-"], "fcomplete-member-pointers">, Group<f_clang_Group>,
+   Flags<[CoreOption, CC1Option]>,
+   HelpText<"Require member pointer base types to be complete if they would be significant under the Microsoft ABI">;
+def fno_complete_member_pointers : Flag<["-"], "fno-complete-member-pointers">, Group<f_clang_Group>,
+   Flags<[CoreOption]>,
+   HelpText<"Do not require member pointer base types to be complete if they would be significant under the Microsoft ABI">;
 def fcf_runtime_abi_EQ : Joined<["-"], "fcf-runtime-abi=">, Group<f_Group>,
-    Flags<[CC1Option]>, Values<"unspecified,standalone,objc,swift,swift-5.0,swift-4.2,swift-4.1">,
-    NormalizedValuesScope<"LangOptions::CoreFoundationABI">,
-    NormalizedValues<["ObjectiveC", "ObjectiveC", "ObjectiveC", "Swift5_0", "Swift5_0", "Swift4_2", "Swift4_1"]>,
-    MarshallingInfoString<"LangOpts->CFRuntime", "ObjectiveC">, AutoNormalizeEnum;
-defm constant_cfstrings : BoolFOption<"constant-cfstrings",
-  "LangOpts->NoConstantCFStrings", DefaultsToFalse,
-  ChangedBy<NegFlag, [], "Disable creation of CodeFoundation-type constant strings">,
-  ResetBy<PosFlag>>;
+    Flags<[CC1Option]>;
+def fconstant_cfstrings : Flag<["-"], "fconstant-cfstrings">, Group<f_Group>;
 def fconstant_string_class_EQ : Joined<["-"], "fconstant-string-class=">, Group<f_Group>;
 def fconstexpr_depth_EQ : Joined<["-"], "fconstexpr-depth=">, Group<f_Group>;
 def fconstexpr_steps_EQ : Joined<["-"], "fconstexpr-steps=">, Group<f_Group>;
 def fexperimental_new_constant_interpreter : Flag<["-"], "fexperimental-new-constant-interpreter">, Group<f_Group>,
-  HelpText<"Enable the experimental new constant interpreter">, Flags<[CC1Option]>,
-  MarshallingInfoFlag<"LangOpts->EnableNewConstInterp">;
+  HelpText<"Enable the experimental new constant interpreter">, Flags<[CC1Option]>;
 def fconstexpr_backtrace_limit_EQ : Joined<["-"], "fconstexpr-backtrace-limit=">,
                                     Group<f_Group>;
 def fno_crash_diagnostics : Flag<["-"], "fno-crash-diagnostics">, Group<f_clang_Group>, Flags<[NoArgumentUnused, CoreOption]>,
   HelpText<"Disable auto-generation of preprocessed source files and a script for reproduction during a clang crash">;
 def fcrash_diagnostics_dir : Joined<["-"], "fcrash-diagnostics-dir=">, Group<f_clang_Group>, Flags<[NoArgumentUnused, CoreOption]>;
 def fcreate_profile : Flag<["-"], "fcreate-profile">, Group<f_Group>;
-defm cxx_exceptions: BoolFOption<"cxx-exceptions",
-  "LangOpts->CXXExceptions", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable C++ exceptions">, ResetBy<NegFlag>>;
+defm cxx_exceptions: OptInFFlag<"cxx-exceptions", "Enable C++ exceptions">;
 def fcxx_modules : Flag <["-"], "fcxx-modules">, Group<f_Group>,
   Flags<[NoXarchOption]>;
 def fdebug_pass_arguments : Flag<["-"], "fdebug-pass-arguments">, Group<f_Group>;
@@ -1276,10 +1233,8 @@ def fdiagnostics_parseable_fixits : Flag<["-"], "fdiagnostics-parseable-fixits">
 def fdiagnostics_print_source_range_info : Flag<["-"], "fdiagnostics-print-source-range-info">,
     Group<f_clang_Group>,  Flags<[CC1Option]>,
     HelpText<"Print source range spans in numeric form">;
-defm diagnostics_show_hotness : BoolFOption<"diagnostics-show-hotness",
-  "CodeGenOpts.DiagnosticsWithHotness", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable profile hotness information in diagnostic line">,
-  ResetBy<NegFlag>>;
+def fdiagnostics_show_hotness : Flag<["-"], "fdiagnostics-show-hotness">, Group<f_Group>,
+    Flags<[CC1Option]>, HelpText<"Enable profile hotness information in diagnostic line">;
 def fdiagnostics_hotness_threshold_EQ : Joined<["-"], "fdiagnostics-hotness-threshold=">,
     Group<f_Group>, Flags<[CC1Option]>, MetaVarName<"<value>">,
     HelpText<"Prevent optimization remarks from being output if they do not have at least this profile count. "
@@ -1303,13 +1258,8 @@ def fdollars_in_identifiers : Flag<["-"], "fdollars-in-identifiers">, Group<f_Gr
   HelpText<"Allow '$' in identifiers">, Flags<[CC1Option]>;
 def fdwarf2_cfi_asm : Flag<["-"], "fdwarf2-cfi-asm">, Group<clang_ignored_f_Group>;
 def fno_dwarf2_cfi_asm : Flag<["-"], "fno-dwarf2-cfi-asm">, Group<clang_ignored_f_Group>;
-defm dwarf_directory_asm : BoolFOption<"dwarf-directory-asm",
-  "CodeGenOpts.NoDwarfDirectoryAsm", DefaultsToFalse,
-  ChangedBy<NegFlag>, ResetBy<PosFlag>>;
-defm elide_constructors : BoolFOption<"elide-constructors",
-  "LangOpts->ElideConstructors", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Disable C++ copy constructor elision">,
-  ResetBy<PosFlag>>;
+defm dwarf_directory_asm : OptOutFFlag<"dwarf-directory-asm", "", "">;
+def felide_constructors : Flag<["-"], "felide-constructors">, Group<f_Group>;
 def fno_elide_type : Flag<["-"], "fno-elide-type">, Group<f_Group>,
     Flags<[CC1Option]>,
     HelpText<"Do not elide types when printing diagnostics">;
@@ -1317,17 +1267,13 @@ def feliminate_unused_debug_symbols : Flag<["-"], "feliminate-unused-debug-symbo
 defm eliminate_unused_debug_types : OptOutFFlag<"eliminate-unused-debug-types",
   "Do not emit ", "Emit ", " debug info for defined but unused types">;
 def femit_all_decls : Flag<["-"], "femit-all-decls">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Emit all declarations, even if unused">,
-  MarshallingInfoFlag<"LangOpts->EmitAllDecls">;
+  HelpText<"Emit all declarations, even if unused">;
 def femulated_tls : Flag<["-"], "femulated-tls">, Group<f_Group>, Flags<[CC1Option]>,
   HelpText<"Use emutls functions to access thread_local variables">;
 def fno_emulated_tls : Flag<["-"], "fno-emulated-tls">, Group<f_Group>, Flags<[CC1Option]>;
 def fencoding_EQ : Joined<["-"], "fencoding=">, Group<f_Group>;
 def ferror_limit_EQ : Joined<["-"], "ferror-limit=">, Group<f_Group>, Flags<[CoreOption]>;
-defm exceptions : BoolFOption<"exceptions",
-  "LangOpts->Exceptions", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable">, ResetBy<NegFlag, [], "Disable">,
-  BothFlags<[], " support for exception handling">>;
+defm exceptions : OptInFFlag<"exceptions", "Enable", "Disable", " support for exception handling">;
 def fdwarf_exceptions : Flag<["-"], "fdwarf-exceptions">, Group<f_Group>,
   HelpText<"Use DWARF style exceptions">;
 def fsjlj_exceptions : Flag<["-"], "fsjlj-exceptions">, Group<f_Group>,
@@ -1346,8 +1292,7 @@ def exception_model : Separate<["-"], "exception-model">,
 def exception_model_EQ : Joined<["-"], "exception-model=">,
   Flags<[CC1Option, NoDriverOption]>, Alias<exception_model>;
 def fignore_exceptions : Flag<["-"], "fignore-exceptions">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Enable support for ignoring exception handling constructs">,
-  MarshallingInfoFlag<"LangOpts->IgnoreExceptions">;
+  HelpText<"Enable support for ignoring exception handling constructs">;
 def fexcess_precision_EQ : Joined<["-"], "fexcess-precision=">,
     Group<clang_ignored_gcc_optimization_f_Group>;
 def : Flag<["-"], "fexpensive-optimizations">, Group<clang_ignored_gcc_optimization_f_Group>;
@@ -1373,22 +1318,14 @@ defm math_errno : OptInFFlag<"math-errno", "Require math functions to indicate e
 def fbracket_depth_EQ : Joined<["-"], "fbracket-depth=">, Group<f_Group>, Flags<[CoreOption]>;
 def fsignaling_math : Flag<["-"], "fsignaling-math">, Group<f_Group>;
 def fno_signaling_math : Flag<["-"], "fno-signaling-math">, Group<f_Group>;
-defm jump_tables : BoolFOption<"jump-tables",
-  "CodeGenOpts.NoUseJumpTables", DefaultsToFalse,
-  ChangedBy<NegFlag, [], "Do not use">, ResetBy<PosFlag, [], "Use">,
-  BothFlags<[], " jump tables for lowering switches">>;
+defm jump_tables : OptOutFFlag<"jump-tables", "Use", "Do not use", " jump tables for lowering switches">;
 defm force_enable_int128 : OptInFFlag<"force-enable-int128", "Enable", "Disable", " support for int128_t type", [], "TargetOpts->ForceEnableInt128">;
-defm keep_static_consts : BoolFOption<"keep-static-consts",
-  "CodeGenOpts.KeepStaticConsts", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Keep">, ResetBy<NegFlag, [], "Don't keep">,
-  BothFlags<[NoXarchOption], " static const variables if unused">>;
+defm keep_static_consts : OptInFFlag<"keep-static-consts", "Keep", "Don't keep", " static const variables if unused", [NoXarchOption]>;
 defm fixed_point : OptInFFlag<"fixed-point", "Enable", "Disable", " fixed point types">;
-defm cxx_static_destructors : BoolFOption<"c++-static-destructors",
-  "LangOpts->RegisterStaticDestructors", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Disable C++ static destructor registration">,
-  ResetBy<PosFlag>>;
+defm cxx_static_destructors : OptOutFFlag<"c++-static-destructors", "",
+  "Disable C++ static destructor registration">;
 def fsymbol_partition_EQ : Joined<["-"], "fsymbol-partition=">, Group<f_Group>,
-  Flags<[CC1Option]>, MarshallingInfoString<"CodeGenOpts.SymbolPartition">;
+  Flags<[CC1Option]>;
 
 defm memory_profile : OptInFFlag<"memory-profile", "Enable", "Disable", " heap memory profiling">;
 def fmemory_profile_EQ : Joined<["-"], "fmemory-profile=">,
@@ -1437,8 +1374,7 @@ def : Joined<["-"], "fsanitize-coverage-blacklist=">,
   HelpText<"Deprecated, use -fsanitize-coverage-blocklist= instead">;
 def fsanitize_memory_track_origins_EQ : Joined<["-"], "fsanitize-memory-track-origins=">,
                                         Group<f_clang_Group>,
-                                        HelpText<"Enable origins tracking in MemorySanitizer">,
-                                        MarshallingInfoStringInt<"CodeGenOpts.SanitizeMemoryTrackOrigins">;
+                                        HelpText<"Enable origins tracking in MemorySanitizer">;
 def fsanitize_memory_track_origins : Flag<["-"], "fsanitize-memory-track-origins">,
                                      Group<f_clang_Group>,
                                      HelpText<"Enable origins tracking in MemorySanitizer">;
@@ -1446,34 +1382,41 @@ def fno_sanitize_memory_track_origins : Flag<["-"], "fno-sanitize-memory-track-o
                                         Group<f_clang_Group>,
                                         Flags<[CoreOption, NoXarchOption]>,
                                         HelpText<"Disable origins tracking in MemorySanitizer">;
-defm sanitize_memory_use_after_dtor : BoolOption<"sanitize-memory-use-after-dtor",
-  "CodeGenOpts.SanitizeMemoryUseAfterDtor", DefaultsToFalse,
-  ChangedBy<PosFlag, [CC1Option], "Enable">, ResetBy<NegFlag, [], "Disable">,
-  BothFlags<[], " use-after-destroy detection in MemorySanitizer">, "f">,
-  Group<f_clang_Group>;
+def fsanitize_memory_use_after_dtor : Flag<["-"], "fsanitize-memory-use-after-dtor">,
+                                     Group<f_clang_Group>,
+                                     HelpText<"Enable use-after-destroy detection in MemorySanitizer">;
+def fno_sanitize_memory_use_after_dtor : Flag<["-"], "fno-sanitize-memory-use-after-dtor">,
+                                     Group<f_clang_Group>,
+                                     HelpText<"Disable use-after-destroy detection in MemorySanitizer">;
 def fsanitize_address_field_padding : Joined<["-"], "fsanitize-address-field-padding=">,
                                         Group<f_clang_Group>,
-                                        HelpText<"Level of field padding for AddressSanitizer">,
-                                        MarshallingInfoStringInt<"LangOpts->SanitizeAddressFieldPadding">;
-defm sanitize_address_use_after_scope : BoolOption<"sanitize-address-use-after-scope",
-  "CodeGenOpts.SanitizeAddressUseAfterScope", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable">, ResetBy<NegFlag, [CoreOption, NoXarchOption], "Disable">,
-  BothFlags<[], " use-after-scope detection in AddressSanitizer">, "f">,
-  Group<f_clang_Group>;
-defm sanitize_address_poison_custom_array_cookie : BoolOption<"sanitize-address-poison-custom-array-cookie",
-  "CodeGenOpts.SanitizeAddressPoisonCustomArrayCookie", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable">, ResetBy<NegFlag, [], "Disable">,
-  BothFlags<[], " poisoning array cookies when using custom operator new[] in AddressSanitizer">, "f">,
-  Group<f_clang_Group>;
+                                        HelpText<"Level of field padding for AddressSanitizer">;
+def fsanitize_address_use_after_scope : Flag<["-"], "fsanitize-address-use-after-scope">,
+                                        Group<f_clang_Group>,
+                                        HelpText<"Enable use-after-scope detection in AddressSanitizer">;
+def fno_sanitize_address_use_after_scope : Flag<["-"], "fno-sanitize-address-use-after-scope">,
+                                           Group<f_clang_Group>,
+                                           Flags<[CoreOption, NoXarchOption]>,
+                                           HelpText<"Disable use-after-scope detection in AddressSanitizer">;
+def fsanitize_address_poison_custom_array_cookie
+    : Flag<[ "-" ], "fsanitize-address-poison-custom-array-cookie">,
+      Group<f_clang_Group>,
+      HelpText<"Enable poisoning array cookies when using custom operator new[] in AddressSanitizer">;
+def fno_sanitize_address_poison_custom_array_cookie
+    : Flag<[ "-" ], "fno-sanitize-address-poison-custom-array-cookie">,
+      Group<f_clang_Group>,
+      HelpText<"Disable poisoning array cookies when using custom operator new[] in AddressSanitizer">;
 def fsanitize_address_globals_dead_stripping : Flag<["-"], "fsanitize-address-globals-dead-stripping">,
-  Group<f_clang_Group>, HelpText<"Enable linker dead stripping of globals in AddressSanitizer">,
-  MarshallingInfoFlag<"CodeGenOpts.SanitizeAddressGlobalsDeadStripping", "false">;
-defm sanitize_address_use_odr_indicator : BoolOption<"sanitize-address-use-odr-indicator",
-  "CodeGenOpts.SanitizeAddressUseOdrIndicator", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable ODR indicator globals to avoid false ODR violation"
-            " reports in partially sanitized programs at the cost of an increase in binary size">,
-  ResetBy<NegFlag, [], "Disable ODR indicator globals">, BothFlags<[]>, "f">,
-  Group<f_clang_Group>;
+                                        Group<f_clang_Group>,
+                                        HelpText<"Enable linker dead stripping of globals in AddressSanitizer">;
+def fsanitize_address_use_odr_indicator
+    : Flag<["-"], "fsanitize-address-use-odr-indicator">,
+      Group<f_clang_Group>,
+      HelpText<"Enable ODR indicator globals to avoid false ODR violation reports in partially sanitized programs at the cost of an increase in binary size">;
+def fno_sanitize_address_use_odr_indicator
+    : Flag<["-"], "fno-sanitize-address-use-odr-indicator">,
+      Group<f_clang_Group>,
+      HelpText<"Disable ODR indicator globals">;
 // Note: This flag was introduced when it was necessary to distinguish between
 //       ABI for correct codegen.  This is no longer needed, but the flag is
 //       not removed since targeting either ABI will behave the same.
@@ -1513,10 +1456,10 @@ def fsanitize_undefined_trap_on_error
 def fno_sanitize_undefined_trap_on_error
     : Flag<["-"], "fno-sanitize-undefined-trap-on-error">, Group<f_clang_Group>,
       Alias<fno_sanitize_trap_EQ>, AliasArgs<["undefined"]>;
-defm sanitize_minimal_runtime : BoolOption<"sanitize-minimal-runtime",
-  "CodeGenOpts.SanitizeMinimalRuntime", DefaultsToFalse,
-  ChangedBy<PosFlag>, ResetBy<NegFlag>, BothFlags<[]>, "f">,
-  Group<f_clang_Group>;
+def fsanitize_minimal_runtime : Flag<["-"], "fsanitize-minimal-runtime">,
+                                        Group<f_clang_Group>;
+def fno_sanitize_minimal_runtime : Flag<["-"], "fno-sanitize-minimal-runtime">,
+                                        Group<f_clang_Group>;
 def fsanitize_link_runtime : Flag<["-"], "fsanitize-link-runtime">,
                            Group<f_clang_Group>;
 def fno_sanitize_link_runtime : Flag<["-"], "fno-sanitize-link-runtime">,
@@ -1525,25 +1468,30 @@ def fsanitize_link_cxx_runtime : Flag<["-"], "fsanitize-link-c++-runtime">,
                                  Group<f_clang_Group>;
 def fno_sanitize_link_cxx_runtime : Flag<["-"], "fno-sanitize-link-c++-runtime">,
                                     Group<f_clang_Group>;
-defm sanitize_cfi_cross_dso : BoolOption<"sanitize-cfi-cross-dso",
-  "CodeGenOpts.SanitizeCfiCrossDso", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable">, ResetBy<NegFlag, [CoreOption, NoXarchOption], "Disable">,
-  BothFlags<[], " control flow integrity (CFI) checks for cross-DSO calls.">, "f">,
-  Group<f_clang_Group>;
+def fsanitize_cfi_cross_dso : Flag<["-"], "fsanitize-cfi-cross-dso">,
+                              Group<f_clang_Group>,
+                              HelpText<"Enable control flow integrity (CFI) checks for cross-DSO calls.">;
+def fno_sanitize_cfi_cross_dso : Flag<["-"], "fno-sanitize-cfi-cross-dso">,
+                                 Flags<[CoreOption, NoXarchOption]>,
+                                 Group<f_clang_Group>,
+                                 HelpText<"Disable control flow integrity (CFI) checks for cross-DSO calls.">;
 def fsanitize_cfi_icall_generalize_pointers : Flag<["-"], "fsanitize-cfi-icall-generalize-pointers">,
                                               Group<f_clang_Group>,
-                                              HelpText<"Generalize pointers in CFI indirect call type signature checks">,
-                                              MarshallingInfoFlag<"CodeGenOpts.SanitizeCfiICallGeneralizePointers">;
-defm sanitize_cfi_canonical_jump_tables : BoolOption<"sanitize-cfi-canonical-jump-tables",
-  "CodeGenOpts.SanitizeCfiCanonicalJumpTables", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Make">, ResetBy<NegFlag, [CoreOption, NoXarchOption], "Do not make">,
-  BothFlags<[], " the jump table addresses canonical in the symbol table">, "f">,
-  Group<f_clang_Group>;
-defm sanitize_stats : BoolOption<"sanitize-stats",
-  "CodeGenOpts.SanitizeStats", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable">, ResetBy<NegFlag, [CoreOption, NoXarchOption], "Disable">,
-  BothFlags<[], " sanitizer statistics gathering.">, "f">,
-  Group<f_clang_Group>;
+                                              HelpText<"Generalize pointers in CFI indirect call type signature checks">;
+def fsanitize_cfi_canonical_jump_tables : Flag<["-"], "fsanitize-cfi-canonical-jump-tables">,
+                                          Group<f_clang_Group>,
+                                          HelpText<"Make the jump table addresses canonical in the symbol table">;
+def fno_sanitize_cfi_canonical_jump_tables : Flag<["-"], "fno-sanitize-cfi-canonical-jump-tables">,
+                                             Group<f_clang_Group>,
+                                             Flags<[CoreOption, NoXarchOption]>,
+                                             HelpText<"Do not make the jump table addresses canonical in the symbol table">;
+def fsanitize_stats : Flag<["-"], "fsanitize-stats">,
+                              Group<f_clang_Group>,
+                              HelpText<"Enable sanitizer statistics gathering.">;
+def fno_sanitize_stats : Flag<["-"], "fno-sanitize-stats">,
+                                 Group<f_clang_Group>,
+                                 Flags<[CoreOption, NoXarchOption]>,
+                                 HelpText<"Disable sanitizer statistics gathering.">;
 def fsanitize_thread_memory_access : Flag<["-"], "fsanitize-thread-memory-access">,
                                      Group<f_clang_Group>,
                                      HelpText<"Enable memory access instrumentation in ThreadSanitizer (default)">;
@@ -1568,8 +1516,7 @@ def fno_sanitize_thread_atomics : Flag<["-"], "fno-sanitize-thread-atomics">,
 def fsanitize_undefined_strip_path_components_EQ : Joined<["-"], "fsanitize-undefined-strip-path-components=">,
   Group<f_clang_Group>, MetaVarName<"<number>">,
   HelpText<"Strip (or keep only, if negative) a given number of path components "
-           "when emitting check metadata.">,
-  MarshallingInfoStringInt<"CodeGenOpts.EmitCheckPathComponentsToStrip", "0", "int">;
+           "when emitting check metadata.">;
 
 } // end -f[no-]sanitize* flags
 
@@ -1597,9 +1544,7 @@ def fno_honor_infinities : Flag<["-"], "fno-honor-infinities">, Group<f_Group>;
 // This option was originally misspelt "infinites" [sic].
 def : Flag<["-"], "fhonor-infinites">, Alias<fhonor_infinities>;
 def : Flag<["-"], "fno-honor-infinites">, Alias<fno_honor_infinities>;
-def frounding_math : Flag<["-"], "frounding-math">, Group<f_Group>, Flags<[CC1Option]>,
-  MarshallingInfoFlag<"LangOpts->FPRoundingMode", "llvm::RoundingMode::NearestTiesToEven">,
-  Normalizer<"makeFlagToValueNormalizer(llvm::RoundingMode::Dynamic)">;
+def frounding_math : Flag<["-"], "frounding-math">, Group<f_Group>, Flags<[CC1Option]>;
 def fno_rounding_math : Flag<["-"], "fno-rounding-math">, Group<f_Group>, Flags<[CC1Option]>;
 def ftrapping_math : Flag<["-"], "ftrapping-math">, Group<f_Group>, Flags<[CC1Option]>;
 def fno_trapping_math : Flag<["-"], "fno-trapping-math">, Group<f_Group>, Flags<[CC1Option]>;
@@ -1612,11 +1557,9 @@ def ffp_contract : Joined<["-"], "ffp-contract=">, Group<f_Group>,
   " Default is 'fast' for CUDA, 'fast-honor-pragmas' for HIP, and 'on' otherwise.">,
   Values<"fast,on,off,fast-honor-pragmas">;
 
-defm strict_float_cast_overflow : BoolFOption<"strict-float-cast-overflow",
-  "CodeGenOpts.StrictFloatCastOverflow", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Relax language rules and try to match the behavior"
-            " of the target's native float-to-int conversion instructions">,
-  ResetBy<PosFlag, [], "Assume that overflowing float-to-int casts are undefined (default)">>;
+defm strict_float_cast_overflow : OptOutFFlag<"strict-float-cast-overflow",
+  "Assume that overflowing float-to-int casts are undefined (default)",
+  "Relax language rules and try to match the behavior of the target's native float-to-int conversion instructions">;
 
 def ffor_scope : Flag<["-"], "ffor-scope">, Group<f_Group>;
 def fno_for_scope : Flag<["-"], "fno-for-scope">, Group<f_Group>;
@@ -1628,11 +1571,10 @@ defm rewrite_includes : BoolFOption<"rewrite-includes",
   "PreprocessorOutputOpts.RewriteIncludes", DefaultsToFalse,
   ChangedBy<PosFlag>, ResetBy<NegFlag>>;
 
-defm delete_null_pointer_checks : BoolFOption<"delete-null-pointer-checks",
-  "CodeGenOpts.NullPointerIsValid", DefaultsToFalse,
-  ChangedBy<NegFlag, [], "Do not treat usage of null pointers as undefined behavior">,
-  ResetBy<PosFlag, [], "Treat usage of null pointers as undefined behavior (default)">,
-  BothFlags<[CoreOption]>>;
+defm delete_null_pointer_checks : OptOutFFlag<"delete-null-pointer-checks",
+  "Treat usage of null pointers as undefined behavior (default)",
+  "Do not treat usage of null pointers as undefined behavior",
+  "", [CoreOption]>;
 
 def frewrite_map_file : Separate<["-"], "frewrite-map-file">,
                         Group<f_Group>,
@@ -1646,8 +1588,7 @@ defm use_line_directives : BoolFOption<"use-line-directives",
   ChangedBy<PosFlag, [], "Use #line in preprocessed output">, ResetBy<NegFlag>>;
 
 def ffreestanding : Flag<["-"], "ffreestanding">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Assert that the compilation takes place in a freestanding environment">,
-  MarshallingInfoFlag<"LangOpts->Freestanding">;
+  HelpText<"Assert that the compilation takes place in a freestanding environment">;
 def fgnuc_version_EQ : Joined<["-"], "fgnuc-version=">, Group<f_Group>,
   HelpText<"Sets various macros to claim compatibility with the given GCC version (default is 4.2.1)">,
   Flags<[CC1Option, CoreOption]>;
@@ -1656,8 +1597,7 @@ def fgnu_keywords : Flag<["-"], "fgnu-keywords">, Group<f_Group>, Flags<[CC1Opti
 defm gnu89_inline : OptInFFlag<"gnu89-inline", "Use the gnu89 inline semantics">;
 def fgnu_runtime : Flag<["-"], "fgnu-runtime">, Group<f_Group>,
   HelpText<"Generate output compatible with the standard GNU Objective-C runtime">;
-def fheinous_gnu_extensions : Flag<["-"], "fheinous-gnu-extensions">, Flags<[CC1Option]>,
-  MarshallingInfoFlag<"LangOpts->HeinousExtensions">;
+def fheinous_gnu_extensions : Flag<["-"], "fheinous-gnu-extensions">, Flags<[CC1Option]>;
 def filelist : Separate<["-"], "filelist">, Flags<[LinkerInput]>,
                Group<Link_Group>;
 def : Flag<["-"], "findirect-virtual-calls">, Alias<fapple_kext>;
@@ -1686,14 +1626,11 @@ def fexperimental_strict_floating_point : Flag<["-"], "fexperimental-strict-floa
 def finput_charset_EQ : Joined<["-"], "finput-charset=">, Group<f_Group>;
 def fexec_charset_EQ : Joined<["-"], "fexec-charset=">, Group<f_Group>;
 def finstrument_functions : Flag<["-"], "finstrument-functions">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Generate calls to instrument function entry and exit">,
-  MarshallingInfoFlag<"CodeGenOpts.InstrumentFunctions">;
+  HelpText<"Generate calls to instrument function entry and exit">;
 def finstrument_functions_after_inlining : Flag<["-"], "finstrument-functions-after-inlining">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Like -finstrument-functions, but insert the calls after inlining">,
-  MarshallingInfoFlag<"CodeGenOpts.InstrumentFunctionsAfterInlining">;
+  HelpText<"Like -finstrument-functions, but insert the calls after inlining">;
 def finstrument_function_entry_bare : Flag<["-"], "finstrument-function-entry-bare">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Instrument function entry only, after inlining, without arguments to the instrumentation call">,
-  MarshallingInfoFlag<"CodeGenOpts.InstrumentFunctionEntryBare">;
+  HelpText<"Instrument function entry only, after inlining, without arguments to the instrumentation call">;
 def fcf_protection_EQ : Joined<["-"], "fcf-protection=">, Flags<[CoreOption, CC1Option]>, Group<f_Group>,
   HelpText<"Instrument control-flow architecture protection. Options: return, branch, full, none.">, Values<"return,branch,full,none">;
 def fcf_protection : Flag<["-"], "fcf-protection">, Group<f_Group>, Flags<[CoreOption, CC1Option]>,
@@ -1705,8 +1642,7 @@ defm xray_instrument : OptInFFlag<"xray-instrument", "Generate XRay instrumentat
 def fxray_instruction_threshold_EQ :
   JoinedOrSeparate<["-"], "fxray-instruction-threshold=">,
   Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Sets the minimum function size to instrument with XRay">,
-  MarshallingInfoStringInt<"CodeGenOpts.XRayInstructionThreshold", "200">;
+  HelpText<"Sets the minimum function size to instrument with XRay">;
 def fxray_instruction_threshold_ :
   JoinedOrSeparate<["-"], "fxray-instruction-threshold">,
   Group<f_Group>, Flags<[CC1Option]>;
@@ -1761,24 +1697,23 @@ def fxray_selected_function_group :
   HelpText<"When using -fxray-function-groups, select which group of functions to instrument. Valid range is 0 to fxray-function-groups - 1">;
 
 
-defm fine_grained_bitfield_accesses : BoolOption<"fine-grained-bitfield-accesses",
-  "CodeGenOpts.FineGrainedBitfieldAccesses", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Use separate accesses for consecutive bitfield runs with legal widths and alignments.">,
-  ResetBy<NegFlag, [], "Use large-integer access for consecutive bitfield runs.">,
-  BothFlags<[CC1Option]>, "f">,
-  Group<f_clang_Group>;
+def ffine_grained_bitfield_accesses : Flag<["-"],
+  "ffine-grained-bitfield-accesses">, Group<f_clang_Group>, Flags<[CC1Option]>,
+  HelpText<"Use separate accesses for consecutive bitfield runs with legal widths and alignments.">;
+def fno_fine_grained_bitfield_accesses : Flag<["-"],
+  "fno-fine-grained-bitfield-accesses">, Group<f_clang_Group>, Flags<[CC1Option]>,
+  HelpText<"Use large-integer access for consecutive bitfield runs.">;
 
-defm experimental_relative_cxx_abi_vtables : BoolFOption<"experimental-relative-c++-abi-vtables",
-  "LangOpts->RelativeCXXABIVTables", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Use">, ResetBy<NegFlag, [], "Do not use">,
-  BothFlags<[CC1Option], " the experimental C++ class ABI for classes with virtual tables">>;
+def fexperimental_relative_cxx_abi_vtables : Flag<["-"], "fexperimental-relative-c++-abi-vtables">,
+  Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Use the experimental C++ class ABI for classes with virtual tables">;
+def fno_experimental_relative_cxx_abi_vtables : Flag<["-"], "fno-experimental-relative-c++-abi-vtables">,
+  Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Do not use the experimental C++ class ABI for classes with virtual tables">;
 
 def flat__namespace : Flag<["-"], "flat_namespace">;
 def flax_vector_conversions_EQ : Joined<["-"], "flax-vector-conversions=">, Group<f_Group>,
-  HelpText<"Enable implicit vector bit-casts">, Values<"none,integer,all">, Flags<[CC1Option]>,
-  NormalizedValuesScope<"LangOptions::LaxVectorConversionKind">,
-  NormalizedValues<["None", "Integer", "All"]>,
-  MarshallingInfoString<"LangOpts->LaxVectorConversions", "All">, AutoNormalizeEnum;
+  HelpText<"Enable implicit vector bit-casts">, Values<"none,integer,all">, Flags<[CC1Option]>;
 def flax_vector_conversions : Flag<["-"], "flax-vector-conversions">, Group<f_Group>,
   Alias<flax_vector_conversions_EQ>, AliasArgs<["integer"]>;
 def flimited_precision_EQ : Joined<["-"], "flimited-precision=">, Group<f_Group>;
@@ -1800,23 +1735,18 @@ def fthinlto_index_EQ : Joined<["-"], "fthinlto-index=">,
   HelpText<"Perform ThinLTO importing using provided function summary index">;
 def fthin_link_bitcode_EQ : Joined<["-"], "fthin-link-bitcode=">,
   Flags<[CoreOption, CC1Option]>, Group<f_Group>,
-  HelpText<"Write minimized bitcode to <file> for the ThinLTO thin link only">,
-  MarshallingInfoString<"CodeGenOpts.ThinLinkBitcodeFile">;
+  HelpText<"Write minimized bitcode to <file> for the ThinLTO thin link only">;
 def fmacro_backtrace_limit_EQ : Joined<["-"], "fmacro-backtrace-limit=">,
                                 Group<f_Group>, Flags<[NoXarchOption, CoreOption]>;
-defm merge_all_constants : BoolFOption<"merge-all-constants",
-  "CodeGenOpts.MergeAllConstants", DefaultsToFalse,
-  ChangedBy<PosFlag, [CoreOption], "Allow">, ResetBy<NegFlag, [], "Disallow">,
-  BothFlags<[], " merging of constants">>;
+def fmerge_all_constants : Flag<["-"], "fmerge-all-constants">, Group<f_Group>,
+  Flags<[CC1Option, CoreOption]>, HelpText<"Allow merging of constants">;
 def fmessage_length_EQ : Joined<["-"], "fmessage-length=">, Group<f_Group>, Flags<[CC1Option]>,
   HelpText<"Format message diagnostics so that they fit within N columns">;
 def fms_extensions : Flag<["-"], "fms-extensions">, Group<f_Group>, Flags<[CC1Option, CoreOption]>,
   HelpText<"Accept some non-standard constructs supported by the Microsoft compiler">;
 def fms_compatibility : Flag<["-"], "fms-compatibility">, Group<f_Group>, Flags<[CC1Option, CoreOption]>,
-  HelpText<"Enable full Microsoft Visual C++ compatibility">,
-  MarshallingInfoFlag<"LangOpts->MSVCCompat">;
-def fms_volatile : Flag<["-"], "fms-volatile">, Group<f_Group>, Flags<[CC1Option]>,
-  MarshallingInfoFlag<"CodeGenOpts.MSVolatile">;
+  HelpText<"Enable full Microsoft Visual C++ compatibility">;
+def fms_volatile : Flag<["-"], "fms-volatile">, Group<f_Group>, Flags<[CC1Option]>;
 def fmsc_version : Joined<["-"], "fmsc-version=">, Group<f_Group>, Flags<[NoXarchOption, CoreOption]>,
   HelpText<"Microsoft compiler version number to report in _MSC_VER (0 = don't define it (default))">;
 def fms_compatibility_version
@@ -1826,17 +1756,10 @@ def fms_compatibility_version
       HelpText<"Dot-separated value representing the Microsoft compiler "
                "version number to report in _MSC_VER (0 = don't define it "
                "(default))">;
-defm delayed_template_parsing : BoolFOption<"delayed-template-parsing",
-  "LangOpts->DelayedTemplateParsing", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Parse templated function definitions at the end of the translation unit">,
-  ResetBy<NegFlag, [NoXarchOption], "Disable delayed template parsing">,
-  BothFlags<[CoreOption]>>;
-def fms_memptr_rep_EQ : Joined<["-"], "fms-memptr-rep=">, Group<f_Group>, Flags<[CC1Option]>,
-  Values<"single,multiple,virtual">, NormalizedValuesScope<"LangOptions">,
-  NormalizedValues<["PPTMK_FullGeneralitySingleInheritance", "PPTMK_FullGeneralityMultipleInheritance",
-                    "PPTMK_FullGeneralityVirtualInheritance"]>,
-  MarshallingInfoString<"LangOpts->MSPointerToMemberRepresentationMethod", "PPTMK_BestCase">,
-  AutoNormalizeEnum;
+def fdelayed_template_parsing : Flag<["-"], "fdelayed-template-parsing">, Group<f_Group>,
+  HelpText<"Parse templated function definitions at the end of the "
+           "translation unit">,  Flags<[CC1Option, CoreOption]>;
+def fms_memptr_rep_EQ : Joined<["-"], "fms-memptr-rep=">, Group<f_Group>, Flags<[CC1Option]>;
 def fmodules_cache_path : Joined<["-"], "fmodules-cache-path=">, Group<i_Group>,
   Flags<[NoXarchOption, CC1Option]>, MetaVarName<"<directory>">,
   HelpText<"Specify the module cache path">;
@@ -1876,7 +1799,7 @@ def fmodules_validate_once_per_build_session : Flag<["-"], "fmodules-validate-on
 def fmodules_disable_diagnostic_validation : Flag<["-"], "fmodules-disable-diagnostic-validation">,
   Group<i_Group>, Flags<[CC1Option]>,
   HelpText<"Disable validation of the diagnostic options when loading the module">,
-  MarshallingInfoNegativeFlag<"HeaderSearchOpts->ModulesValidateDiagnosticOptions">;
+  MarshallingInfoFlag<"HeaderSearchOpts->ModulesValidateDiagnosticOptions", "true">, IsNegative;
 defm modules_validate_system_headers : BoolOption<"modules-validate-system-headers",
   "HeaderSearchOpts->ModulesValidateSystemHeaders", DefaultsToFalse,
   ChangedBy<PosFlag, [CC1Option], "Validate the system headers that a module depends on when loading the module">,
@@ -1903,10 +1826,13 @@ def fpch_validate_input_files_content:
 def fno_pch_validate_input_files_content:
   Flag <["-"], "fno_pch-validate-input-files-content">,
   Group<f_Group>, Flags<[NoXarchOption]>;
-defm pch_instantiate_templates : BoolFOption<"pch-instantiate-templates",
-  "LangOpts->PCHInstantiateTemplates", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Instantiate templates already while building a PCH">,
-  ResetBy<NegFlag>, BothFlags<[CC1Option, CoreOption]>>;
+def fpch_instantiate_templates:
+  Flag <["-"], "fpch-instantiate-templates">,
+  Group<f_Group>, Flags<[CC1Option, CoreOption]>,
+  HelpText<"Instantiate templates already while building a PCH">;
+def fno_pch_instantiate_templates:
+  Flag <["-"], "fno-pch-instantiate-templates">,
+  Group<f_Group>, Flags<[CC1Option, CoreOption]>;
 defm pch_codegen: OptInFFlag<"pch-codegen", "Generate ", "Do not generate ",
   "code for uses of this PCH that assumes an explicit object file will be built for the PCH">;
 defm pch_debuginfo: OptInFFlag<"pch-debuginfo", "Generate ", "Do not generate ",
@@ -1920,13 +1846,11 @@ def fimplicit_module_maps : Flag <["-"], "fimplicit-module-maps">, Group<f_Group
   HelpText<"Implicitly search the file system for module map files.">,
   MarshallingInfoFlag<"HeaderSearchOpts->ImplicitModuleMaps">;
 def fmodules_ts : Flag <["-"], "fmodules-ts">, Group<f_Group>,
-  Flags<[CC1Option]>, HelpText<"Enable support for the C++ Modules TS">,
-  MarshallingInfoFlag<"LangOpts->ModulesTS">;
+  Flags<[CC1Option]>, HelpText<"Enable support for the C++ Modules TS">;
 def fmodule_maps : Flag <["-"], "fmodule-maps">, Alias<fimplicit_module_maps>;
 def fmodule_name_EQ : Joined<["-"], "fmodule-name=">, Group<f_Group>,
   Flags<[NoXarchOption,CC1Option]>, MetaVarName<"<name>">,
-  HelpText<"Specify the name of the module to build">,
-  MarshallingInfoString<"LangOpts->ModuleName">;
+  HelpText<"Specify the name of the module to build">;
 def fmodule_name : Separate<["-"], "fmodule-name">, Alias<fmodule_name_EQ>;
 def fmodule_implementation_of : Separate<["-"], "fmodule-implementation-of">,
   Flags<[CC1Option]>, Alias<fmodule_name_EQ>;
@@ -1946,25 +1870,25 @@ def fmodules_decluse : Flag <["-"], "fmodules-decluse">, Group<f_Group>,
   HelpText<"Require declaration of modules used within a module">;
 def fmodules_strict_decluse : Flag <["-"], "fmodules-strict-decluse">, Group<f_Group>,
   Flags<[NoXarchOption,CC1Option]>,
-  HelpText<"Like -fmodules-decluse but requires all headers to be in modules">,
-  MarshallingInfoFlag<"LangOpts->ModulesStrictDeclUse">;
+  HelpText<"Like -fmodules-decluse but requires all headers to be in modules">;
 def fno_modules_search_all : Flag <["-"], "fno-modules-search-all">, Group<f_Group>,
   Flags<[NoXarchOption, CC1Option]>;
-defm implicit_modules : BoolFOption<"implicit-modules",
-  "LangOpts->ImplicitModules", DefaultsToTrue,
-  ChangedBy<NegFlag>, ResetBy<PosFlag>, BothFlags<[NoXarchOption]>>;
-def fretain_comments_from_system_headers : Flag<["-"], "fretain-comments-from-system-headers">, Group<f_Group>, Flags<[CC1Option]>,
-  MarshallingInfoFlag<"LangOpts->RetainCommentsFromSystemHeaders">;
+def fno_implicit_modules :
+  Flag <["-"], "fno-implicit-modules">,
+  Group<f_Group>, Flags<[NoXarchOption, CC1Option]>;
+def fretain_comments_from_system_headers : Flag<["-"], "fretain-comments-from-system-headers">, Group<f_Group>, Flags<[CC1Option]>;
 
 def fmudflapth : Flag<["-"], "fmudflapth">, Group<f_Group>;
 def fmudflap : Flag<["-"], "fmudflap">, Group<f_Group>;
 def fnested_functions : Flag<["-"], "fnested-functions">, Group<f_Group>;
 def fnext_runtime : Flag<["-"], "fnext-runtime">, Group<f_Group>;
+def fno_apple_pragma_pack : Flag<["-"], "fno-apple-pragma-pack">, Group<f_Group>;
 def fno_asm : Flag<["-"], "fno-asm">, Group<f_Group>;
 def fno_asynchronous_unwind_tables : Flag<["-"], "fno-asynchronous-unwind-tables">, Group<f_Group>;
 def fno_assume_sane_operator_new : Flag<["-"], "fno-assume-sane-operator-new">, Group<f_Group>,
   HelpText<"Don't assume that C++'s global operator new can't alias any pointer">,
-  Flags<[CC1Option]>, MarshallingInfoNegativeFlag<"CodeGenOpts.AssumeSaneOperatorNew">;
+  Flags<[CC1Option]>;
+def fno_borland_extensions : Flag<["-"], "fno-borland-extensions">, Group<f_Group>;
 def fno_builtin : Flag<["-"], "fno-builtin">, Group<f_Group>, Flags<[CC1Option, CoreOption]>,
   HelpText<"Disable implicit builtin knowledge of functions">;
 def fno_builtin_ : Joined<["-"], "fno-builtin-">, Group<f_Group>, Flags<[CC1Option, CoreOption]>,
@@ -1973,10 +1897,14 @@ def fno_diagnostics_color : Flag<["-"], "fno-diagnostics-color">, Group<f_Group>
   Flags<[CoreOption, NoXarchOption]>;
 def fno_common : Flag<["-"], "fno-common">, Group<f_Group>, Flags<[CC1Option]>,
     HelpText<"Compile common globals like normal definitions">;
+def fno_constant_cfstrings : Flag<["-"], "fno-constant-cfstrings">, Group<f_Group>,
+  Flags<[CC1Option]>,
+  HelpText<"Disable creation of CodeFoundation-type constant strings">;
 def fno_cxx_modules : Flag <["-"], "fno-cxx-modules">, Group<f_Group>,
   Flags<[NoXarchOption]>;
 def fno_diagnostics_fixit_info : Flag<["-"], "fno-diagnostics-fixit-info">, Group<f_Group>,
   Flags<[CC1Option]>, HelpText<"Do not include fixit information in diagnostics">;
+def fno_diagnostics_show_hotness : Flag<["-"], "fno-diagnostics-show-hotness">, Group<f_Group>;
 def fno_diagnostics_show_option : Flag<["-"], "fno-diagnostics-show-option">, Group<f_Group>, Flags<[CC1Option]>;
 def fno_diagnostics_show_note_include_stack : Flag<["-"], "fno-diagnostics-show-note-include-stack">,
     Flags<[CC1Option]>, Group<f_Group>;
@@ -1988,6 +1916,8 @@ def fno_declspec : Flag<["-"], "fno-declspec">, Group<f_clang_Group>,
   HelpText<"Disallow __declspec as a keyword">, Flags<[CC1Option]>;
 def fno_dollars_in_identifiers : Flag<["-"], "fno-dollars-in-identifiers">, Group<f_Group>,
   HelpText<"Disallow '$' in identifiers">, Flags<[CC1Option]>;
+def fno_elide_constructors : Flag<["-"], "fno-elide-constructors">, Group<f_Group>,
+  HelpText<"Disable C++ copy constructor elision">, Flags<[CC1Option]>;
 def fno_eliminate_unused_debug_symbols : Flag<["-"], "fno-eliminate-unused-debug-symbols">, Group<f_Group>;
 def fno_gnu_keywords : Flag<["-"], "fno-gnu-keywords">, Group<f_Group>, Flags<[CC1Option]>;
 def fno_inline_functions : Flag<["-"], "fno-inline-functions">, Group<f_clang_Group>, Flags<[CC1Option]>;
@@ -1997,13 +1927,11 @@ def fno_global_isel : Flag<["-"], "fno-global-isel">, Group<f_clang_Group>,
 def fno_experimental_isel : Flag<["-"], "fno-experimental-isel">, Group<f_clang_Group>,
   Alias<fno_global_isel>;
 def fveclib : Joined<["-"], "fveclib=">, Group<f_Group>, Flags<[CC1Option]>,
-    HelpText<"Use the given vector functions library">,
-    Values<"Accelerate,libmvec,MASSV,SVML,none">,
-    NormalizedValuesScope<"CodeGenOptions">,
-    NormalizedValues<["Accelerate", "LIBMVEC", "MASSV", "SVML", "NoLibrary"]>,
-    MarshallingInfoString<"CodeGenOpts.VecLib", "NoLibrary">, AutoNormalizeEnum;
+    HelpText<"Use the given vector functions library">, Values<"Accelerate,libmvec,MASSV,SVML,none">;
 def fno_lax_vector_conversions : Flag<["-"], "fno-lax-vector-conversions">, Group<f_Group>,
   Alias<flax_vector_conversions_EQ>, AliasArgs<["none"]>;
+def fno_merge_all_constants : Flag<["-"], "fno-merge-all-constants">, Group<f_Group>,
+  HelpText<"Disallow merging of constants">;
 def fno_modules : Flag <["-"], "fno-modules">, Group<f_Group>,
   Flags<[NoXarchOption]>;
 def fno_implicit_module_maps : Flag <["-"], "fno-implicit-module-maps">, Group<f_Group>,
@@ -2013,6 +1941,8 @@ def fno_modules_decluse : Flag <["-"], "fno-modules-decluse">, Group<f_Group>,
   Flags<[NoXarchOption]>;
 def fno_modules_strict_decluse : Flag <["-"], "fno-strict-modules-decluse">, Group<f_Group>,
   Flags<[NoXarchOption]>;
+def fimplicit_modules : Flag <["-"], "fimplicit-modules">, Group<f_Group>,
+  Flags<[NoXarchOption]>;
 def fmodule_file_deps : Flag <["-"], "fmodule-file-deps">, Group<f_Group>,
   Flags<[NoXarchOption]>;
 def fno_module_file_deps : Flag <["-"], "fno-module-file-deps">, Group<f_Group>,
@@ -2021,16 +1951,24 @@ def fno_ms_extensions : Flag<["-"], "fno-ms-extensions">, Group<f_Group>,
   Flags<[CoreOption]>;
 def fno_ms_compatibility : Flag<["-"], "fno-ms-compatibility">, Group<f_Group>,
   Flags<[CoreOption]>;
+def fno_delayed_template_parsing : Flag<["-"], "fno-delayed-template-parsing">, Group<f_Group>,
+  HelpText<"Disable delayed template parsing">,
+  Flags<[NoXarchOption, CoreOption]>;
+def fno_objc_exceptions: Flag<["-"], "fno-objc-exceptions">, Group<f_Group>;
 def fno_objc_legacy_dispatch : Flag<["-"], "fno-objc-legacy-dispatch">, Group<f_Group>;
 def fno_objc_weak : Flag<["-"], "fno-objc-weak">, Group<f_Group>, Flags<[CC1Option]>;
 def fno_omit_frame_pointer : Flag<["-"], "fno-omit-frame-pointer">, Group<f_Group>;
 def fno_operator_names : Flag<["-"], "fno-operator-names">, Group<f_Group>,
   HelpText<"Do not treat C++ operator name keywords as synonyms for operators">,
   Flags<[CC1Option]>;
+def fno_pascal_strings : Flag<["-"], "fno-pascal-strings">, Group<f_Group>;
+def fno_short_enums : Flag<["-"], "fno-short-enums">, Group<f_Group>;
 def fno_show_source_location : Flag<["-"], "fno-show-source-location">, Group<f_Group>,
   Flags<[CC1Option]>, HelpText<"Do not include source location information with diagnostics">;
 def fdiagnostics_absolute_paths : Flag<["-"], "fdiagnostics-absolute-paths">, Group<f_Group>,
   Flags<[CC1Option, CoreOption]>, HelpText<"Print absolute paths in diagnostics">;
+def fno_spell_checking : Flag<["-"], "fno-spell-checking">, Group<f_Group>,
+  Flags<[CC1Option]>, HelpText<"Disable spell-checking">;
 def fno_stack_protector : Flag<["-"], "fno-stack-protector">, Group<f_Group>,
   HelpText<"Disable the use of stack protectors">;
 def fno_strict_aliasing : Flag<["-"], "fno-strict-aliasing">, Group<f_Group>,
@@ -2038,55 +1976,58 @@ def fno_strict_aliasing : Flag<["-"], "fno-strict-aliasing">, Group<f_Group>,
 def fstruct_path_tbaa : Flag<["-"], "fstruct-path-tbaa">, Group<f_Group>;
 def fno_struct_path_tbaa : Flag<["-"], "fno-struct-path-tbaa">, Group<f_Group>;
 def fno_strict_enums : Flag<["-"], "fno-strict-enums">, Group<f_Group>;
+def fno_strict_vtable_pointers: Flag<["-"], "fno-strict-vtable-pointers">,
+  Group<f_Group>;
 def fno_strict_overflow : Flag<["-"], "fno-strict-overflow">, Group<f_Group>;
 def fno_temp_file : Flag<["-"], "fno-temp-file">, Group<f_Group>,
   Flags<[CC1Option, CoreOption]>, HelpText<
   "Directly create compilation output files. This may lead to incorrect incremental builds if the compiler crashes">,
-  MarshallingInfoNegativeFlag<"FrontendOpts.UseTemporary">;
-defm use_cxa_atexit : BoolFOption<"use-cxa-atexit",
-  "CodeGenOpts.CXAAtExit", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Don't use __cxa_atexit for calling destructors">,
-  ResetBy<PosFlag>>;
+  MarshallingInfoFlag<"FrontendOpts.UseTemporary", "true">, IsNegative;
+def fno_threadsafe_statics : Flag<["-"], "fno-threadsafe-statics">, Group<f_Group>,
+  Flags<[CC1Option]>, HelpText<"Do not emit code to make initialization of local statics thread safe">;
+def fno_use_cxa_atexit : Flag<["-"], "fno-use-cxa-atexit">, Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Don't use __cxa_atexit for calling destructors">;
+def fno_register_global_dtors_with_atexit : Flag<["-"], "fno-register-global-dtors-with-atexit">, Group<f_Group>,
+  HelpText<"Don't use atexit or __cxa_atexit to register global destructors">;
 def fno_unit_at_a_time : Flag<["-"], "fno-unit-at-a-time">, Group<f_Group>;
 def fno_unwind_tables : Flag<["-"], "fno-unwind-tables">, Group<f_Group>;
-def fno_verbose_asm : Flag<["-"], "fno-verbose-asm">, Group<f_Group>, Flags<[CC1Option]>,
-  MarshallingInfoNegativeFlag<"CodeGenOpts.AsmVerbose">;
+def fno_verbose_asm : Flag<["-"], "fno-verbose-asm">, Group<f_Group>, Flags<[CC1Option]>;
 def fno_working_directory : Flag<["-"], "fno-working-directory">, Group<f_Group>;
 def fno_wrapv : Flag<["-"], "fno-wrapv">, Group<f_Group>;
 def fobjc_arc : Flag<["-"], "fobjc-arc">, Group<f_Group>, Flags<[CC1Option]>,
   HelpText<"Synthesize retain and release calls for Objective-C pointers">;
 def fno_objc_arc : Flag<["-"], "fno-objc-arc">, Group<f_Group>;
-defm objc_convert_messages_to_runtime_calls : BoolFOption<"objc-convert-messages-to-runtime-calls",
-  "CodeGenOpts.ObjCConvertMessagesToRuntimeCalls", DefaultsToTrue,
-  ChangedBy<NegFlag>, ResetBy<PosFlag>>;
-defm objc_arc_exceptions : OptInFFlag<"objc-arc-exceptions",
-  "Use EH-safe code when synthesizing retains and releases in -fobjc-arc",
-  "", "", [], "CodeGenOpts.ObjCAutoRefCountExceptions">;
+def fobjc_convert_messages_to_runtime_calls :
+  Flag<["-"], "fobjc-convert-messages-to-runtime-calls">, Group<f_Group>;
+def fno_objc_convert_messages_to_runtime_calls :
+  Flag<["-"], "fno-objc-convert-messages-to-runtime-calls">, Group<f_Group>, Flags<[CC1Option]>;
+def fobjc_arc_exceptions : Flag<["-"], "fobjc-arc-exceptions">, Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Use EH-safe code when synthesizing retains and releases in -fobjc-arc">;
+def fno_objc_arc_exceptions : Flag<["-"], "fno-objc-arc-exceptions">, Group<f_Group>;
 def fobjc_atdefs : Flag<["-"], "fobjc-atdefs">, Group<clang_ignored_f_Group>;
 def fobjc_call_cxx_cdtors : Flag<["-"], "fobjc-call-cxx-cdtors">, Group<clang_ignored_f_Group>;
-defm objc_exceptions : BoolFOption<"objc-exceptions",
-  "LangOpts->ObjCExceptions", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable Objective-C exceptions">, ResetBy<NegFlag>>;
-defm application_extension : BoolFOption<"application-extension",
-  "LangOpts->AppExt", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Restrict code to those available for App Extensions">,
-  ResetBy<NegFlag>>;
-defm relaxed_template_template_args : BoolFOption<"relaxed-template-template-args",
-  "LangOpts->RelaxedTemplateTemplateArgs", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable C++17 relaxed template template argument matching">,
-  ResetBy<NegFlag>>;
-defm sized_deallocation : BoolFOption<"sized-deallocation",
-  "LangOpts->SizedDeallocation", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable C++14 sized global deallocation functions">,
-  ResetBy<NegFlag>>;
+def fobjc_exceptions: Flag<["-"], "fobjc-exceptions">, Group<f_Group>,
+  HelpText<"Enable Objective-C exceptions">, Flags<[CC1Option]>;
+def fapplication_extension : Flag<["-"], "fapplication-extension">,
+  Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Restrict code to those available for App Extensions">;
+def fno_application_extension : Flag<["-"], "fno-application-extension">,
+  Group<f_Group>;
+def frelaxed_template_template_args : Flag<["-"], "frelaxed-template-template-args">,
+  Flags<[CC1Option]>, HelpText<"Enable C++17 relaxed template template argument matching">,
+  Group<f_Group>;
+def fno_relaxed_template_template_args : Flag<["-"], "fno-relaxed-template-template-args">,
+  Group<f_Group>;
+def fsized_deallocation : Flag<["-"], "fsized-deallocation">, Flags<[CC1Option]>,
+  HelpText<"Enable C++14 sized global deallocation functions">, Group<f_Group>;
+def fno_sized_deallocation: Flag<["-"], "fno-sized-deallocation">, Group<f_Group>;
 def faligned_allocation : Flag<["-"], "faligned-allocation">, Flags<[CC1Option]>,
   HelpText<"Enable C++17 aligned allocation functions">, Group<f_Group>;
 def fno_aligned_allocation: Flag<["-"], "fno-aligned-allocation">,
   Group<f_Group>, Flags<[CC1Option]>;
 def fnew_alignment_EQ : Joined<["-"], "fnew-alignment=">,
   HelpText<"Specifies the largest alignment guaranteed by '::operator new(size_t)'">,
-  MetaVarName<"<align>">, Group<f_Group>, Flags<[CC1Option]>,
-  MarshallingInfoStringInt<"LangOpts->NewAlignOverride">;
+  MetaVarName<"<align>">, Group<f_Group>, Flags<[CC1Option]>;
 def : Separate<["-"], "fnew-alignment">, Alias<fnew_alignment_EQ>;
 def : Flag<["-"], "faligned-new">, Alias<faligned_allocation>;
 def : Flag<["-"], "fno-aligned-new">, Alias<fno_aligned_allocation>;
@@ -2094,10 +2035,13 @@ def faligned_new_EQ : Joined<["-"], "faligned-new=">;
 
 def fobjc_legacy_dispatch : Flag<["-"], "fobjc-legacy-dispatch">, Group<f_Group>;
 def fobjc_new_property : Flag<["-"], "fobjc-new-property">, Group<clang_ignored_f_Group>;
-defm objc_infer_related_result_type : BoolFOption<"objc-infer-related-result-type",
-  "LangOpts->ObjCInferRelatedResultType", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "do not infer Objective-C related result type based on method family">,
-  ResetBy<PosFlag>>;
+def fobjc_infer_related_result_type : Flag<["-"], "fobjc-infer-related-result-type">,
+                                      Group<f_Group>;
+def fno_objc_infer_related_result_type : Flag<["-"],
+  "fno-objc-infer-related-result-type">, Group<f_Group>,
+  HelpText<
+    "do not infer Objective-C related result type based on method family">,
+  Flags<[CC1Option]>;
 def fobjc_link_runtime: Flag<["-"], "fobjc-link-runtime">, Group<f_Group>;
 def fobjc_weak : Flag<["-"], "fobjc-weak">, Group<f_Group>, Flags<[CC1Option]>,
   HelpText<"Enable ARC-style weak references in Objective-C">;
@@ -2115,8 +2059,7 @@ def foffload_static_lib_EQ : CommaJoined<["-"], "foffload-static-lib=">, Flags<[
 def foffload_whole_static_lib_EQ : CommaJoined<["-"], "foffload-whole-static-lib=">, Flags<[NoXarchOption, CoreOption]>, Group<offload_lib_Group>;
 def fomit_frame_pointer : Flag<["-"], "fomit-frame-pointer">, Group<f_Group>;
 def fopenmp : Flag<["-"], "fopenmp">, Group<f_Group>, Flags<[CC1Option, NoArgumentUnused]>,
-  HelpText<"Parse OpenMP pragmas and generate parallel code.">,
-  MarshallingInfoFlag<"LangOpts->OpenMP", "0u">, Normalizer<"makeFlagToValueNormalizer(50u)">;
+  HelpText<"Parse OpenMP pragmas and generate parallel code.">;
 def fno_openmp : Flag<["-"], "fno-openmp">, Group<f_Group>, Flags<[NoArgumentUnused]>;
 def fopenmp_version_EQ : Joined<["-"], "fopenmp-version=">, Group<f_Group>, Flags<[CC1Option, NoArgumentUnused]>;
 def fopenmp_EQ : Joined<["-"], "fopenmp=">, Group<f_Group>;
@@ -2149,9 +2092,10 @@ def fopenmp_cuda_blocks_per_sm_EQ : Joined<["-"], "fopenmp-cuda-blocks-per-sm=">
   Flags<[CC1Option, NoArgumentUnused, HelpHidden]>;
 def fopenmp_cuda_teams_reduction_recs_num_EQ : Joined<["-"], "fopenmp-cuda-teams-reduction-recs-num=">, Group<f_Group>,
   Flags<[CC1Option, NoArgumentUnused, HelpHidden]>;
-defm openmp_optimistic_collapse : BoolFOption<"openmp-optimistic-collapse",
-  "LangOpts->OpenMPOptimisticCollapse", DefaultsToFalse,
-  ChangedBy<PosFlag>, ResetBy<NegFlag>, BothFlags<[NoArgumentUnused, HelpHidden]>>;
+def fopenmp_optimistic_collapse : Flag<["-"], "fopenmp-optimistic-collapse">, Group<f_Group>,
+  Flags<[CC1Option, NoArgumentUnused, HelpHidden]>;
+def fno_openmp_optimistic_collapse : Flag<["-"], "fno-openmp-optimistic-collapse">, Group<f_Group>,
+  Flags<[NoArgumentUnused, HelpHidden]>;
 def fopenmp_cuda_parallel_target_regions : Flag<["-"], "fopenmp-cuda-parallel-target-regions">, Group<f_Group>,
   Flags<[CC1Option, NoArgumentUnused, HelpHidden]>,
   HelpText<"Support parallel execution of target regions on Cuda-based devices.">;
@@ -2162,9 +2106,8 @@ def static_openmp: Flag<["-"], "static-openmp">,
   HelpText<"Use the static host OpenMP runtime while linking.">;
 def fno_optimize_sibling_calls : Flag<["-"], "fno-optimize-sibling-calls">, Group<f_Group>;
 def foptimize_sibling_calls : Flag<["-"], "foptimize-sibling-calls">, Group<f_Group>;
-defm escaping_block_tail_calls : BoolFOption<"escaping-block-tail-calls",
-  "CodeGenOpts.NoEscapingBlockTailCalls", DefaultsToFalse,
-  ChangedBy<NegFlag>, ResetBy<PosFlag>>;
+def fno_escaping_block_tail_calls : Flag<["-"], "fno-escaping-block-tail-calls">, Group<f_Group>, Flags<[CC1Option]>;
+def fescaping_block_tail_calls : Flag<["-"], "fescaping-block-tail-calls">, Group<f_Group>;
 def force__cpusubtype__ALL : Flag<["-"], "force_cpusubtype_ALL">;
 def force__flat__namespace : Flag<["-"], "force_flat_namespace">;
 def force__load : Separate<["-"], "force_load">;
@@ -2173,22 +2116,14 @@ def foutput_class_dir_EQ : Joined<["-"], "foutput-class-dir=">, Group<f_Group>;
 def fpack_struct : Flag<["-"], "fpack-struct">, Group<f_Group>;
 def fno_pack_struct : Flag<["-"], "fno-pack-struct">, Group<f_Group>;
 def fpack_struct_EQ : Joined<["-"], "fpack-struct=">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Specify the default maximum struct packing alignment">,
-  MarshallingInfoStringInt<"LangOpts->PackStruct">;
+  HelpText<"Specify the default maximum struct packing alignment">;
 def fmax_type_align_EQ : Joined<["-"], "fmax-type-align=">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Specify the maximum alignment to enforce on pointers lacking an explicit alignment">,
-  MarshallingInfoStringInt<"LangOpts->MaxTypeAlign">;
+  HelpText<"Specify the maximum alignment to enforce on pointers lacking an explicit alignment">;
 def fno_max_type_align : Flag<["-"], "fno-max-type-align">, Group<f_Group>;
-defm pascal_strings : BoolFOption<"pascal-strings",
-  "LangOpts->PascalStrings", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Recognize and construct Pascal-style string literals">,
-  ResetBy<NegFlag>>;
-// Note: This flag has different semantics in the driver and in -cc1. The driver accepts -fpatchable-function-entry=M,N
-// and forwards it to -cc1 as -fpatchable-function-entry=M and -fpatchable-function-entry-offset=N. In -cc1, both flags
-// are treated as a single integer.
+def fpascal_strings : Flag<["-"], "fpascal-strings">, Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Recognize and construct Pascal-style string literals">;
 def fpatchable_function_entry_EQ : Joined<["-"], "fpatchable-function-entry=">, Group<f_Group>, Flags<[CC1Option]>,
-  MetaVarName<"<N,M>">, HelpText<"Generate M NOPs before function entry and N-M NOPs after function entry">,
-  MarshallingInfoStringInt<"CodeGenOpts.PatchableFunctionEntryCount">;
+  MetaVarName<"<N,M>">, HelpText<"Generate M NOPs before function entry and N-M NOPs after function entry">;
 def fpcc_struct_return : Flag<["-"], "fpcc-struct-return">, Group<f_Group>, Flags<[CC1Option]>,
   HelpText<"Override the default ABI to return all structs on the stack">;
 def fpch_preprocess : Flag<["-"], "fpch-preprocess">, Group<f_Group>;
@@ -2196,30 +2131,19 @@ def fpic : Flag<["-"], "fpic">, Group<f_Group>;
 def fno_pic : Flag<["-"], "fno-pic">, Group<f_Group>;
 def fpie : Flag<["-"], "fpie">, Group<f_Group>;
 def fno_pie : Flag<["-"], "fno-pie">, Group<f_Group>;
-defm plt : BoolFOption<"plt",
-  "CodeGenOpts.NoPLT", DefaultsToFalse,
-  ChangedBy<NegFlag, [], "Use GOT indirection instead of PLT to make external function calls (x86 only)">,
-  ResetBy<PosFlag>>;
-defm ropi : BoolFOption<"ropi",
-  "LangOpts->ROPI", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Generate read-only position independent code (ARM only)">,
-  ResetBy<NegFlag>>;
-defm rwpi : BoolFOption<"rwpi",
-  "LangOpts->RWPI", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Generate read-write position independent code (ARM only)">,
-  ResetBy<NegFlag>>;
+defm plt : OptOutFFlag<"plt", "",
+  "Use GOT indirection instead of PLT to make external function calls (x86 only)">;
+defm ropi : OptInFFlag<"ropi", "Generate read-only position independent code (ARM only)">;
+defm rwpi : OptInFFlag<"rwpi", "Generate read-write position independent code (ARM only)">;
 def fplugin_EQ : Joined<["-"], "fplugin=">, Group<f_Group>, Flags<[NoXarchOption]>, MetaVarName<"<dsopath>">,
   HelpText<"Load the named plugin (dynamic shared object)">;
 def fpass_plugin_EQ : Joined<["-"], "fpass-plugin=">,
   Group<f_Group>, Flags<[CC1Option]>, MetaVarName<"<dsopath>">,
   HelpText<"Load pass plugin from a dynamic shared object file (only with new pass manager).">;
-defm preserve_as_comments : BoolFOption<"preserve-as-comments",
-  "CodeGenOpts.PreserveAsmComments", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Do not preserve comments in inline assembly">,
-  ResetBy<PosFlag>>;
-defm profile_arcs : BoolFOption<"profile-arcs",
-  "CodeGenOpts.EmitGcovArcs", DefaultsToFalse,
-  ChangedBy<PosFlag, [LinkOption]>, ResetBy<NegFlag>>;
+defm preserve_as_comments : OptOutFFlag<"preserve-as-comments", "",
+  "Do not preserve comments in inline assembly">;
+def fprofile_arcs : Flag<["-"], "fprofile-arcs">, Group<f_Group>, Flags<[CC1Option,LinkOption]>;
+def fno_profile_arcs : Flag<["-"], "fno-profile-arcs">, Group<f_Group>;
 def framework : Separate<["-"], "framework">, Flags<[LinkerInput]>;
 def frandom_seed_EQ : Joined<["-"], "frandom-seed=">, Group<clang_ignored_f_Group>;
 def freg_struct_return : Flag<["-"], "freg-struct-return">, Group<f_Group>, Flags<[CC1Option]>,
@@ -2227,11 +2151,8 @@ def freg_struct_return : Flag<["-"], "freg-struct-return">, Group<f_Group>, Flag
 defm rtti : OptOutFFlag<"rtti", "", "Disable generation of rtti information">;
 defm rtti_data : OptOutFFlag<"rtti-data", "", "Disable generation of RTTI data">;
 def : Flag<["-"], "fsched-interblock">, Group<clang_ignored_f_Group>;
-defm short_enums : BoolFOption<"short-enums",
-  "LangOpts->ShortEnums", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Allocate to an enum type only as many bytes as it"
-           " needs for the declared range of possible values">,
-  ResetBy<NegFlag>>;
+def fshort_enums : Flag<["-"], "fshort-enums">, Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Allocate to an enum type only as many bytes as it needs for the declared range of possible values">;
 def fchar8__t : Flag<["-"], "fchar8_t">, Group<f_Group>, Flags<[CC1Option]>,
   HelpText<"Enable C++ builtin type char8_t">;
 def fno_char8__t : Flag<["-"], "fno-char8_t">, Group<f_Group>, Flags<[CC1Option]>,
@@ -2245,19 +2166,17 @@ def fshow_overloads_EQ : Joined<["-"], "fshow-overloads=">, Group<f_Group>, Flag
            "best|all; defaults to all">, Values<"best,all">;
 defm show_column : OptOutFFlag<"show-column", "", "Do not include column number on diagnostics">;
 def fshow_source_location : Flag<["-"], "fshow-source-location">, Group<f_Group>;
-defm spell_checking : BoolFOption<"spell-checking",
-  "LangOpts->SpellChecking", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Disable spell-checking">, ResetBy<PosFlag>>;
+def fspell_checking : Flag<["-"], "fspell-checking">, Group<f_Group>;
 def fspell_checking_limit_EQ : Joined<["-"], "fspell-checking-limit=">, Group<f_Group>;
 def fsigned_bitfields : Flag<["-"], "fsigned-bitfields">, Group<f_Group>;
 defm signed_char : OptOutFFlag<"signed-char", "char is signed", "char is unsigned">;
 def fsplit_stack : Flag<["-"], "fsplit-stack">, Group<f_Group>;
 def fstack_protector_all : Flag<["-"], "fstack-protector-all">, Group<f_Group>,
   HelpText<"Enable stack protectors for all functions">;
-defm stack_clash_protection : BoolFOption<"stack-clash-protection",
-  "CodeGenOpts.StackClashProtector", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable">, ResetBy<NegFlag, [], "Disable">,
-  BothFlags<[], " stack clash protection">>;
+def fstack_clash_protection : Flag<["-"], "fstack-clash-protection">, Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Enable stack clash protection">;
+def fno_stack_clash_protection : Flag<["-"], "fno-stack-clash-protection">, Group<f_Group>,
+  HelpText<"Disable stack clash protection">;
 def fstack_protector_strong : Flag<["-"], "fstack-protector-strong">, Group<f_Group>,
   HelpText<"Enable stack protectors for some functions vulnerable to stack smashing. "
            "Compared to -fstack-protector, this uses a stronger heuristic "
@@ -2276,16 +2195,12 @@ def fstack_protector : Flag<["-"], "fstack-protector">, Group<f_Group>,
            "address. The reference stack guard value is stored in a global variable.">;
 def ftrivial_auto_var_init : Joined<["-"], "ftrivial-auto-var-init=">, Group<f_Group>,
   Flags<[CC1Option, CoreOption]>, HelpText<"Initialize trivial automatic stack variables: uninitialized (default)"
-  " | pattern">, Values<"uninitialized,zero,pattern">,
-  NormalizedValuesScope<"LangOptions::TrivialAutoVarInitKind">,
-  NormalizedValues<["Uninitialized", "Zero", "Pattern"]>,
-  MarshallingInfoString<"LangOpts->TrivialAutoVarInit", "Uninitialized">, AutoNormalizeEnum;
+  " | pattern">, Values<"uninitialized,pattern">;
 def enable_trivial_var_init_zero : Flag<["-"], "enable-trivial-auto-var-init-zero-knowing-it-will-be-removed-from-clang">,
   Flags<[CC1Option, CoreOption]>,
   HelpText<"Trivial automatic variable initialization to zero is only here for benchmarks, it'll eventually be removed, and I'm OK with that because I'm only using it to benchmark">;
 def ftrivial_auto_var_init_stop_after : Joined<["-"], "ftrivial-auto-var-init-stop-after=">, Group<f_Group>,
-  Flags<[CC1Option, CoreOption]>, HelpText<"Stop initializing trivial automatic stack variables after the specified number of instances">,
-  MarshallingInfoStringInt<"LangOpts->TrivialAutoVarInitStopAfter">;
+  Flags<[CC1Option, CoreOption]>, HelpText<"Stop initializing trivial automatic stack variables after the specified number of instances">;
 def fstandalone_debug : Flag<["-"], "fstandalone-debug">, Group<f_Group>, Flags<[CoreOption]>,
   HelpText<"Emit full debug info for all types used by the program">;
 def fno_standalone_debug : Flag<["-"], "fno-standalone-debug">, Group<f_Group>, Flags<[CoreOption]>,
@@ -2300,13 +2215,11 @@ def fstrict_aliasing : Flag<["-"], "fstrict-aliasing">, Group<f_Group>,
   Flags<[NoXarchOption, CoreOption]>;
 def fstrict_enums : Flag<["-"], "fstrict-enums">, Group<f_Group>, Flags<[CC1Option]>,
   HelpText<"Enable optimizations based on the strict definition of an enum's "
-           "value range">,
-  MarshallingInfoFlag<"CodeGenOpts.StrictEnums">;
-defm strict_vtable_pointers : BoolFOption<"strict-vtable-pointers",
-  "CodeGenOpts.StrictVTablePointers", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable optimizations based on the strict rules for"
-            " overwriting polymorphic C++ objects">,
-  ResetBy<NegFlag>>;
+           "value range">;
+def fstrict_vtable_pointers: Flag<["-"], "fstrict-vtable-pointers">,
+  Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Enable optimizations based on the strict rules for overwriting "
+             "polymorphic C++ objects">;
 def fstrict_overflow : Flag<["-"], "fstrict-overflow">, Group<f_Group>;
 def fintelfpga : Flag<["-"], "fintelfpga">, Group<f_Group>,
   Flags<[CC1Option, CoreOption]>, HelpText<"Perform ahead of time compilation for FPGA">;
@@ -2378,9 +2291,8 @@ def foptimization_record_passes_EQ : Joined<["-"], "foptimization-record-passes=
   HelpText<"Only include passes which match a specified regular expression in the generated optimization record (by default, include all passes)">,
   MetaVarName<"<regex>">;
 
-defm test_coverage : BoolFOption<"test-coverage",
-  "CodeGenOpts.EmitGcovNotes", DefaultsToFalse,
-  ChangedBy<PosFlag>, ResetBy<NegFlag>>;
+def ftest_coverage : Flag<["-"], "ftest-coverage">, Flags<[CC1Option]>, Group<f_Group>;
+def fno_test_coverage : Flag<["-"], "fno-test-coverage">, Group<f_Group>;
 def fvectorize : Flag<["-"], "fvectorize">, Group<f_Group>,
   HelpText<"Enable the loop vectorization passes">;
 def fno_vectorize : Flag<["-"], "fno-vectorize">, Group<f_Group>;
@@ -2394,8 +2306,7 @@ def : Flag<["-"], "fno-tree-slp-vectorize">, Alias<fno_slp_vectorize>;
 def Wlarge_by_value_copy_def : Flag<["-"], "Wlarge-by-value-copy">,
   HelpText<"Warn if a function definition returns or accepts an object larger "
            "in bytes than a given value">, Flags<[HelpHidden]>;
-def Wlarge_by_value_copy_EQ : Joined<["-"], "Wlarge-by-value-copy=">, Flags<[CC1Option]>,
-  MarshallingInfoStringInt<"LangOpts->NumLargeByValueCopy">;
+def Wlarge_by_value_copy_EQ : Joined<["-"], "Wlarge-by-value-copy=">, Flags<[CC1Option]>;
 
 // These "special" warning flags are effectively processed as f_Group flags by the driver:
 // Just silence warnings about -Wlarger-than for now.
@@ -2404,10 +2315,7 @@ def Wlarger_than_ : Joined<["-"], "Wlarger-than-">, Alias<Wlarger_than_EQ>;
 def Wframe_larger_than_EQ : Joined<["-"], "Wframe-larger-than=">, Group<f_Group>, Flags<[NoXarchOption]>;
 
 def : Flag<["-"], "fterminated-vtables">, Alias<fapple_kext>;
-defm threadsafe_statics : BoolFOption<"threadsafe-statics",
-  "LangOpts->ThreadsafeStatics", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Do not emit code to make initialization of local statics thread safe">,
-  ResetBy<PosFlag>>;
+def fthreadsafe_statics : Flag<["-"], "fthreadsafe-statics">, Group<f_Group>;
 def ftime_report : Flag<["-"], "ftime-report">, Group<f_Group>, Flags<[CC1Option]>,
   MarshallingInfoFlag<"CodeGenOpts.TimePasses">;
 def ftime_report_EQ: Joined<["-"], "ftime-report=">, Group<f_Group>,
@@ -2431,11 +2339,7 @@ def fproc_stat_report : Joined<["-"], "fproc-stat-report">, Group<f_Group>,
   HelpText<"Print subprocess statistics">;
 def fproc_stat_report_EQ : Joined<["-"], "fproc-stat-report=">, Group<f_Group>,
   HelpText<"Save subprocess statistics to the given file">;
-def ftlsmodel_EQ : Joined<["-"], "ftls-model=">, Group<f_Group>, Flags<[CC1Option]>,
-  Values<"global-dynamic,local-dynamic,initial-exec,local-exec">,
-  NormalizedValuesScope<"CodeGenOptions">,
-  NormalizedValues<["GeneralDynamicTLSModel", "LocalDynamicTLSModel", "InitialExecTLSModel", "LocalExecTLSModel"]>,
-  MarshallingInfoString<"CodeGenOpts.DefaultTLSModel", "GeneralDynamicTLSModel">, AutoNormalizeEnum;
+def ftlsmodel_EQ : Joined<["-"], "ftls-model=">, Group<f_Group>, Flags<[CC1Option]>;
 def ftrapv : Flag<["-"], "ftrapv">, Group<f_Group>, Flags<[CC1Option]>,
   HelpText<"Trap on integer overflow">;
 def ftrapv_handler_EQ : Joined<["-"], "ftrapv-handler=">, Group<f_Group>,
@@ -2443,16 +2347,13 @@ def ftrapv_handler_EQ : Joined<["-"], "ftrapv-handler=">, Group<f_Group>,
   HelpText<"Specify the function to be called on overflow">;
 def ftrapv_handler : Separate<["-"], "ftrapv-handler">, Group<f_Group>, Flags<[CC1Option]>;
 def ftrap_function_EQ : Joined<["-"], "ftrap-function=">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Issue call to specified function rather than a trap instruction">,
-  MarshallingInfoString<"CodeGenOpts.TrapFuncName">;
+  HelpText<"Issue call to specified function rather than a trap instruction">;
 def funit_at_a_time : Flag<["-"], "funit-at-a-time">, Group<f_Group>;
 def funroll_loops : Flag<["-"], "funroll-loops">, Group<f_Group>,
   HelpText<"Turn on loop unroller">, Flags<[CC1Option]>;
 def fno_unroll_loops : Flag<["-"], "fno-unroll-loops">, Group<f_Group>,
   HelpText<"Turn off loop unroller">, Flags<[CC1Option]>;
-defm reroll_loops : BoolFOption<"reroll-loops",
-  "CodeGenOpts.RerollLoops", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Turn on loop reroller">, ResetBy<NegFlag>>;
+defm reroll_loops : OptInFFlag<"reroll-loops", "Turn on loop reroller">;
 def ftrigraphs : Flag<["-"], "ftrigraphs">, Group<f_Group>,
   HelpText<"Process trigraph sequences">, Flags<[CC1Option]>;
 def fno_trigraphs : Flag<["-"], "fno-trigraphs">, Group<f_Group>,
@@ -2461,14 +2362,10 @@ def funsigned_bitfields : Flag<["-"], "funsigned-bitfields">, Group<f_Group>;
 def funsigned_char : Flag<["-"], "funsigned-char">, Group<f_Group>;
 def fno_unsigned_char : Flag<["-"], "fno-unsigned-char">;
 def funwind_tables : Flag<["-"], "funwind-tables">, Group<f_Group>;
-defm register_global_dtors_with_atexit : BoolFOption<"register-global-dtors-with-atexit",
-  "CodeGenOpts.RegisterGlobalDtorsWithAtExit", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Use">, ResetBy<NegFlag, [], "Don't use">,
-  BothFlags<[], " atexit or __cxa_atexit to register global destructors">>;
-defm use_init_array : BoolFOption<"use-init-array",
-  "CodeGenOpts.UseInitArray", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Use .ctors/.dtors instead of .init_array/.fini_array">,
-  ResetBy<PosFlag>>;
+def fuse_cxa_atexit : Flag<["-"], "fuse-cxa-atexit">, Group<f_Group>;
+def fregister_global_dtors_with_atexit : Flag<["-"], "fregister-global-dtors-with-atexit">, Group<f_Group>, Flags<[CC1Option]>,
+  HelpText<"Use atexit or __cxa_atexit to register global destructors">;
+defm use_init_array : OptOutFFlag<"use-init-array", "", "Use .ctors/.dtors instead of .init_array/.fini_array">;
 def fno_var_tracking : Flag<["-"], "fno-var-tracking">, Group<clang_ignored_f_Group>;
 def fverbose_asm : Flag<["-"], "fverbose-asm">, Group<f_Group>,
   HelpText<"Generate verbose assembly output">;
@@ -2486,104 +2383,73 @@ def fvisibility_EQ : Joined<["-"], "fvisibility=">, Group<f_Group>,
   HelpText<"Set the default symbol visibility for all global declarations">, Values<"hidden,default">;
 def fvisibility_inlines_hidden : Flag<["-"], "fvisibility-inlines-hidden">, Group<f_Group>,
   HelpText<"Give inline C++ member functions hidden visibility by default">,
-  Flags<[CC1Option]>, MarshallingInfoFlag<"LangOpts->InlineVisibilityHidden">;
-defm visibility_inlines_hidden_static_local_var : BoolFOption<"visibility-inlines-hidden-static-local-var",
-  "LangOpts->VisibilityInlinesHiddenStaticLocalVar", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "When -fvisibility-inlines-hidden is enabled, static variables in"
-            " inline C++ member functions will also be given hidden visibility by default">,
-  ResetBy<NegFlag, [], "Disables -fvisibility-inlines-hidden-static-local-var"
-         " (this is the default on non-darwin targets)">, BothFlags<[CC1Option]>>;
+  Flags<[CC1Option]>;
+def fvisibility_inlines_hidden_static_local_var :
+  Flag<["-"], "fvisibility-inlines-hidden-static-local-var">, Group<f_Group>,
+  HelpText<"When -fvisibility-inlines-hidden is enabled, static variables in "
+           "inline C++ member functions will also be given hidden visibility "
+           "by default">,
+  Flags<[CC1Option]>;
+def fno_visibility_inlines_hidden_static_local_var :
+  Flag<["-"], "fno-visibility-inlines-hidden-static-local-var">, Group<f_Group>,
+  HelpText<"Disables -fvisibility-inlines-hidden-static-local-var "
+           "(this is the default on non-darwin targets)">,
+  Flags<[CC1Option]>;
 def fvisibility_ms_compat : Flag<["-"], "fvisibility-ms-compat">, Group<f_Group>,
   HelpText<"Give global types 'default' visibility and global functions and "
            "variables 'hidden' visibility by default">;
 def fvisibility_global_new_delete_hidden : Flag<["-"], "fvisibility-global-new-delete-hidden">, Group<f_Group>,
-  HelpText<"Give global C++ operator new and delete declarations hidden visibility">, Flags<[CC1Option]>,
-  MarshallingInfoFlag<"LangOpts->GlobalAllocationFunctionVisibilityHidden">;
-defm whole_program_vtables : BoolFOption<"whole-program-vtables",
-  "CodeGenOpts.WholeProgramVTables", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enables whole-program vtable optimization. Requires -flto">,
-  ResetBy<NegFlag>, BothFlags<[CoreOption]>>;
-defm split_lto_unit : BoolFOption<"split-lto-unit",
-  "CodeGenOpts.EnableSplitLTOUnit", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enables splitting of the LTO unit">,
-  ResetBy<NegFlag>, BothFlags<[CoreOption]>>;
-defm force_emit_vtables : BoolFOption<"force-emit-vtables",
-  "CodeGenOpts.ForceEmitVTables", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Emits more virtual tables to improve devirtualization">,
-  ResetBy<NegFlag>, BothFlags<[CoreOption]>>;
-defm virtual_function_elimination : BoolFOption<"virtual-function-elimination",
-  "CodeGenOpts.VirtualFunctionElimination", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enables dead virtual function elimination optimization. Requires -flto=full">,
-  ResetBy<NegFlag>, BothFlags<[CoreOption]>>;
+  HelpText<"Give global C++ operator new and delete declarations hidden visibility">, Flags<[CC1Option]>;
+defm whole_program_vtables : OptInFFlag<"whole-program-vtables",
+  "Enables whole-program vtable optimization. Requires -flto", "", "", [CoreOption]>;
+defm split_lto_unit : OptInFFlag<"split-lto-unit",
+  "Enables splitting of the LTO unit", "", "", [CoreOption]>;
+defm force_emit_vtables : OptInFFlag<"force-emit-vtables",
+  "Emits more virtual tables to improve devirtualization", "", "", [CoreOption]>;
+defm virtual_function_elimination : OptInFFlag<"virtual-function-elimination",
+  "Enables dead virtual function elimination optimization. Requires -flto=full", "", "", [CoreOption]>;
 
 def fwrapv : Flag<["-"], "fwrapv">, Group<f_Group>, Flags<[CC1Option]>,
   HelpText<"Treat signed integer overflow as two's complement">;
 def fwritable_strings : Flag<["-"], "fwritable-strings">, Group<f_Group>, Flags<[CC1Option]>,
-  HelpText<"Store string literals as writable data">,
-  MarshallingInfoFlag<"LangOpts->WritableStrings">;
-defm zero_initialized_in_bss : BoolFOption<"zero-initialized-in-bss",
-  "CodeGenOpts.NoZeroInitializedInBSS", DefaultsToFalse,
-  ChangedBy<NegFlag, [], "Don't place zero initialized data in BSS">,
-  ResetBy<PosFlag>>;
+  HelpText<"Store string literals as writable data">;
+defm zero_initialized_in_bss : OptOutFFlag<"zero-initialized-in-bss", "", "Don't place zero initialized data in BSS">;
 defm function_sections : OptInFFlag<"function-sections", "Place each function in its own section">;
 def fbasic_block_sections_EQ : Joined<["-"], "fbasic-block-sections=">, Group<f_Group>,
   Flags<[CC1Option, CC1AsOption]>,
   HelpText<"Place each function's basic blocks in unique sections (ELF Only) : all | labels | none | list=<file>">,
   DocBrief<[{Generate labels for each basic block or place each basic block or a subset of basic blocks in its own section.}]>,
-  Values<"all,labels,none,list=">,
-  MarshallingInfoString<"CodeGenOpts.BBSections", [{"none"}]>;
-defm data_sections : BoolFOption<"data-sections",
-  "CodeGenOpts.DataSections", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Place each data in its own section">, ResetBy<NegFlag>>;
-defm stack_size_section : BoolFOption<"stack-size-section",
-  "CodeGenOpts.StackSizeSection", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Emit section containing metadata on function stack sizes">,
-  ResetBy<NegFlag>>;
-
-defm unique_basic_block_section_names : BoolFOption<"unique-basic-block-section-names",
-  "CodeGenOpts.UniqueBasicBlockSectionNames", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Use unique names for basic block sections (ELF Only)">,
-  ResetBy<NegFlag>>;
-defm unique_internal_linkage_names : BoolFOption<"unique-internal-linkage-names",
-  "CodeGenOpts.UniqueInternalLinkageNames", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Uniqueify Internal Linkage Symbol Names by appending"
-            " the MD5 hash of the module path">,
-  ResetBy<NegFlag>>;
-defm unique_section_names : BoolFOption<"unique-section-names",
-  "CodeGenOpts.UniqueSectionNames", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Don't use unique names for text and data sections">,
-  ResetBy<PosFlag>>;
+  Values<"all,labels,none,list=">;
+defm data_sections : OptInFFlag<"data-sections", "Place each data in its own section">;
+defm stack_size_section : OptInFFlag<"stack-size-section", "Emit section containing metadata on function stack sizes">;
 
-defm split_machine_functions: BoolFOption<"split-machine-functions",
-  "CodeGenOpts.SplitMachineFunctions", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable">, ResetBy<NegFlag, [], "Disable">,
-  BothFlags<[], " late function splitting using profile information (x86 ELF)">>;
+defm unique_basic_block_section_names : OptInFFlag<"unique-basic-block-section-names",
+ "Use unique names for basic block sections (ELF Only)">;
+defm unique_internal_linkage_names : OptInFFlag<"unique-internal-linkage-names",
+ "Uniqueify Internal Linkage Symbol Names by appending the MD5 hash of the module path">;
+defm unique_section_names : OptOutFFlag<"unique-section-names",
+  "", "Don't use unique names for text and data sections">;
 
-defm strict_return : BoolFOption<"strict-return",
-  "CodeGenOpts.StrictReturn", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Don't treat control flow paths that fall off the end"
-            " of a non-void function as unreachable">,
-  ResetBy<PosFlag>>;
+defm split_machine_functions: OptInFFlag<"split-machine-functions",
+  "Enable", "Disable", " late function splitting using profile information (x86 ELF)">;
+
+defm strict_return : OptOutFFlag<"strict-return", "",
+  "Don't treat control flow paths that fall off the end of a non-void function as unreachable">;
 
 def fenable_matrix : Flag<["-"], "fenable-matrix">, Group<f_Group>,
     Flags<[CC1Option]>,
-    HelpText<"Enable matrix data type and related builtin functions">,
-    MarshallingInfoFlag<"LangOpts->MatrixTypes">;
+    HelpText<"Enable matrix data type and related builtin functions">;
 
 
 def fdebug_types_section: Flag <["-"], "fdebug-types-section">, Group<f_Group>,
   HelpText<"Place debug types in their own section (ELF Only)">;
 def fno_debug_types_section: Flag<["-"], "fno-debug-types-section">, Group<f_Group>;
-defm debug_ranges_base_address : BoolFOption<"debug-ranges-base-address",
-  "CodeGenOpts.DebugRangesBaseAddress", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Use DWARF base address selection entries in .debug_ranges">,
-  ResetBy<NegFlag>>;
-defm split_dwarf_inlining : BoolFOption<"split-dwarf-inlining",
-  "CodeGenOpts.SplitDwarfInlining", DefaultsToTrue,
-  ChangedBy<NegFlag>,
-  ResetBy<PosFlag, [], "Provide minimal debug info in the object/executable"
-          " to facilitate online symbolication/stack traces in the absence of"
-          " .dwo/.dwp files when using Split DWARF">>;
+defm debug_ranges_base_address : OptInFFlag<"debug-ranges-base-address",
+  "Use DWARF base address selection entries in .debug_ranges">;
+def fsplit_dwarf_inlining: Flag <["-"], "fsplit-dwarf-inlining">, Group<f_Group>,
+  HelpText<"Provide minimal debug info in the object/executable to facilitate online symbolication/stack traces in the absence of .dwo/.dwp files when using Split DWARF">;
+def fno_split_dwarf_inlining: Flag<["-"], "fno-split-dwarf-inlining">, Group<f_Group>,
+  Flags<[CC1Option]>;
 def fdebug_default_version: Joined<["-"], "fdebug-default-version=">, Group<f_Group>,
   HelpText<"Default DWARF version to use, if a -g option caused DWARF debug info to be produced">;
 def fdebug_prefix_map_EQ
@@ -2596,9 +2462,7 @@ def ffile_prefix_map_EQ
 def fmacro_prefix_map_EQ
   : Joined<["-"], "fmacro-prefix-map=">, Group<Preprocessor_Group>, Flags<[CC1Option]>,
     HelpText<"remap file source paths in predefined preprocessor macros">;
-defm force_dwarf_frame : BoolFOption<"force-dwarf-frame",
-  "CodeGenOpts.ForceDwarfFrameSection", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Always emit a debug frame section">, ResetBy<NegFlag>>;
+defm force_dwarf_frame : OptInFFlag<"force-dwarf-frame", "Always emit a debug frame section">;
 def g_Flag : Flag<["-"], "g">, Group<g_Group>,
   HelpText<"Generate source-level debug information">;
 def gline_tables_only : Flag<["-"], "gline-tables-only">, Group<gN_Group>,
@@ -2632,8 +2496,7 @@ def gdwarf_5 : Flag<["-"], "gdwarf-5">, Group<g_Group>,
 
 def gcodeview : Flag<["-"], "gcodeview">,
   HelpText<"Generate CodeView debug information">,
-  Flags<[CC1Option, CC1AsOption, CoreOption]>,
-  MarshallingInfoFlag<"CodeGenOpts.EmitCodeView">;
+  Flags<[CC1Option, CC1AsOption, CoreOption]>;
 defm codeview_ghash : BoolOption<"codeview-ghash",
   "CodeGenOpts.CodeViewGHash", DefaultsToFalse,
   ChangedBy<PosFlag, [CC1Option], "Emit type record hashes in a .debug$H section">,
@@ -2658,9 +2521,8 @@ def : Flag<["-"], "grecord-gcc-switches">, Alias<grecord_command_line>;
 def : Flag<["-"], "gno-record-gcc-switches">, Alias<gno_record_command_line>;
 def gstrict_dwarf : Flag<["-"], "gstrict-dwarf">, Group<g_flags_Group>;
 def gno_strict_dwarf : Flag<["-"], "gno-strict-dwarf">, Group<g_flags_Group>;
-defm column_info : BoolGOption<"column-info",
-  "CodeGenOpts.DebugColumnInfo", DefaultsToTrue,
-  ChangedBy<NegFlag>, ResetBy<PosFlag>, BothFlags<[CoreOption]>>;
+def gcolumn_info : Flag<["-"], "gcolumn-info">, Group<g_flags_Group>, Flags<[CoreOption]>;
+def gno_column_info : Flag<["-"], "gno-column-info">, Group<g_flags_Group>, Flags<[CoreOption, CC1Option]>;
 def gsplit_dwarf : Flag<["-"], "gsplit-dwarf">, Group<g_flags_Group>;
 def gsplit_dwarf_EQ : Joined<["-"], "gsplit-dwarf=">, Group<g_flags_Group>,
   HelpText<"Set DWARF fission mode to either 'split' or 'single'">,
@@ -2678,8 +2540,7 @@ def gz_EQ : Joined<["-"], "gz=">, Group<g_flags_Group>,
     HelpText<"DWARF debug sections compression type">;
 def gz : Flag<["-"], "gz">, Alias<gz_EQ>, AliasArgs<["zlib"]>, Group<g_flags_Group>;
 def gembed_source : Flag<["-"], "gembed-source">, Group<g_flags_Group>, Flags<[CC1Option]>,
-    HelpText<"Embed source text in DWARF debug sections">,
-    MarshallingInfoFlag<"CodeGenOpts.EmbedSource">;
+    HelpText<"Embed source text in DWARF debug sections">;
 def gno_embed_source : Flag<["-"], "gno-embed-source">, Group<g_flags_Group>,
     Flags<[NoXarchOption]>,
     HelpText<"Restore the default behavior of not embedding source text in DWARF debug sections">;
@@ -2754,8 +2615,7 @@ def EB : Flag<["-"], "EB">, Alias<mbig_endian>;
 def m16 : Flag<["-"], "m16">, Group<m_Group>, Flags<[NoXarchOption, CoreOption]>;
 def m32 : Flag<["-"], "m32">, Group<m_Group>, Flags<[NoXarchOption, CoreOption]>;
 def mqdsp6_compat : Flag<["-"], "mqdsp6-compat">, Group<m_Group>, Flags<[NoXarchOption,CC1Option]>,
-  HelpText<"Enable hexagon-qdsp6 backward compatibility">,
-  MarshallingInfoFlag<"LangOpts->HexagonQdsp6Compat">;
+  HelpText<"Enable hexagon-qdsp6 backward compatibility">;
 def m64 : Flag<["-"], "m64">, Group<m_Group>, Flags<[NoXarchOption, CoreOption]>;
 def mx32 : Flag<["-"], "mx32">, Group<m_Group>, Flags<[NoXarchOption, CoreOption]>;
 def mabi_EQ : Joined<["-"], "mabi=">, Group<m_Group>;
@@ -2777,8 +2637,7 @@ def mfancy_math_387 : Flag<["-"], "mfancy-math-387">, Group<clang_ignored_m_Grou
 def mlong_calls : Flag<["-"], "mlong-calls">, Group<m_Group>,
   HelpText<"Generate branches with extended addressability, usually via indirect jumps.">;
 def mdouble_EQ : Joined<["-"], "mdouble=">, Group<m_Group>, Values<"32,64">, Flags<[CC1Option]>,
-  HelpText<"Force double to be 32 bits or 64 bits">,
-  MarshallingInfoStringInt<"LangOpts->DoubleSize", "0">;
+  HelpText<"Force double to be 32 bits or 64 bits">;
 def LongDouble_Group : OptionGroup<"<LongDouble group>">, Group<m_Group>,
   DocName<"Long double flags">,
   DocBrief<[{Selects the long double implementation}]>;
@@ -2811,8 +2670,7 @@ def mcmodel_EQ : Joined<["-"], "mcmodel=">, Group<m_Group>, Flags<[CC1Option]>,
   MarshallingInfoString<"TargetOpts->CodeModel", [{"default"}]>;
 def mtls_size_EQ : Joined<["-"], "mtls-size=">, Group<m_Group>, Flags<[NoXarchOption, CC1Option]>,
   HelpText<"Specify bit size of immediate TLS offsets (AArch64 ELF only): "
-           "12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for 256TB, needs -mcmodel=large)">,
-  MarshallingInfoStringInt<"CodeGenOpts.TLSSize">;
+           "12 (for 4KB) | 24 (for 16MB, default) | 32 (for 4GB) | 48 (for 256TB, needs -mcmodel=large)">;
 def mimplicit_it_EQ : Joined<["-"], "mimplicit-it=">, Group<m_Group>;
 def mdefault_build_attributes : Joined<["-"], "mdefault-build-attributes">, Group<m_Group>;
 def mno_default_build_attributes : Joined<["-"], "mno-default-build-attributes">, Group<m_Group>;
@@ -2831,8 +2689,7 @@ def mieee_fp : Flag<["-"], "mieee-fp">, Group<clang_ignored_m_Group>;
 def minline_all_stringops : Flag<["-"], "minline-all-stringops">, Group<clang_ignored_m_Group>;
 def mno_inline_all_stringops : Flag<["-"], "mno-inline-all-stringops">, Group<clang_ignored_m_Group>;
 def malign_double : Flag<["-"], "malign-double">, Group<m_Group>, Flags<[CC1Option]>,
-  HelpText<"Align doubles to two words in structs (x86 only)">,
-  MarshallingInfoFlag<"LangOpts->AlignDouble">;
+  HelpText<"Align doubles to two words in structs (x86 only)">;
 def mfloat_abi_EQ : Joined<["-"], "mfloat-abi=">, Group<m_Group>, Values<"soft,softfp,hard">;
 def mfpmath_EQ : Joined<["-"], "mfpmath=">, Group<m_Group>;
 def mfpu_EQ : Joined<["-"], "mfpu=">, Group<m_Group>;
@@ -2856,8 +2713,7 @@ def mmacosx_version_min_EQ : Joined<["-"], "mmacosx-version-min=">,
 def mmacos_version_min_EQ : Joined<["-"], "mmacos-version-min=">,
   Group<m_Group>, Alias<mmacosx_version_min_EQ>;
 def mms_bitfields : Flag<["-"], "mms-bitfields">, Group<m_Group>, Flags<[CC1Option]>,
-  HelpText<"Set the default structure layout to be compatible with the Microsoft compiler standard">,
-  MarshallingInfoFlag<"LangOpts->MSBitfields">;
+  HelpText<"Set the default structure layout to be compatible with the Microsoft compiler standard">;
 def moutline : Flag<["-"], "moutline">, Group<f_clang_Group>, Flags<[CC1Option]>,
     HelpText<"Enable function outlining (AArch64 only)">;
 def mno_outline : Flag<["-"], "mno-outline">, Group<f_clang_Group>, Flags<[CC1Option]>,
@@ -2865,19 +2721,15 @@ def mno_outline : Flag<["-"], "mno-outline">, Group<f_clang_Group>, Flags<[CC1Op
 def mno_ms_bitfields : Flag<["-"], "mno-ms-bitfields">, Group<m_Group>,
   HelpText<"Do not set the default structure layout to be compatible with the Microsoft compiler standard">;
 def mstackrealign : Flag<["-"], "mstackrealign">, Group<m_Group>, Flags<[CC1Option]>,
-  HelpText<"Force realign the stack at entry to every function">,
-  MarshallingInfoFlag<"CodeGenOpts.StackRealignment">;
+  HelpText<"Force realign the stack at entry to every function">;
 def mstack_alignment : Joined<["-"], "mstack-alignment=">, Group<m_Group>, Flags<[CC1Option]>,
-  HelpText<"Set the stack alignment">,
-  MarshallingInfoStringInt<"CodeGenOpts.StackAlignment">;
+  HelpText<"Set the stack alignment">;
 def mstack_probe_size : Joined<["-"], "mstack-probe-size=">, Group<m_Group>, Flags<[CC1Option]>,
-  HelpText<"Set the stack probe size">,
-  MarshallingInfoStringInt<"CodeGenOpts.StackProbeSize", "4096">;
+  HelpText<"Set the stack probe size">;
 def mstack_arg_probe : Flag<["-"], "mstack-arg-probe">, Group<m_Group>,
   HelpText<"Enable stack probes">;
 def mno_stack_arg_probe : Flag<["-"], "mno-stack-arg-probe">, Group<m_Group>, Flags<[CC1Option]>,
-  HelpText<"Disable stack probes which are enabled by default">,
-  MarshallingInfoFlag<"CodeGenOpts.NoStackArgProbe">;
+  HelpText<"Disable stack probes which are enabled by default">;
 def mthread_model : Separate<["-"], "mthread-model">, Group<m_Group>, Flags<[CC1Option]>,
   HelpText<"The thread model to use, e.g. posix, single (posix by default)">, Values<"posix,single">;
 def meabi : Separate<["-"], "meabi">, Group<m_Group>, Flags<[CC1Option]>,
@@ -2893,8 +2745,7 @@ def mno_pascal_strings : Flag<["-"], "mno-pascal-strings">,
   Alias<fno_pascal_strings>;
 def mno_red_zone : Flag<["-"], "mno-red-zone">, Group<m_Group>;
 def mno_tls_direct_seg_refs : Flag<["-"], "mno-tls-direct-seg-refs">, Group<m_Group>, Flags<[CC1Option]>,
-  HelpText<"Disable direct TLS access through segment registers">,
-  MarshallingInfoFlag<"CodeGenOpts.IndirectTlsSegRefs">;
+  HelpText<"Disable direct TLS access through segment registers">;
 def mno_relax_all : Flag<["-"], "mno-relax-all">, Group<m_Group>;
 def mno_rtd: Flag<["-"], "mno-rtd">, Group<m_Group>;
 def mno_soft_float : Flag<["-"], "mno-soft-float">, Group<m_Group>;
@@ -2902,10 +2753,10 @@ def mno_stackrealign : Flag<["-"], "mno-stackrealign">, Group<m_Group>;
 
 def mretpoline : Flag<["-"], "mretpoline">, Group<m_Group>, Flags<[CoreOption,NoXarchOption]>;
 def mno_retpoline : Flag<["-"], "mno-retpoline">, Group<m_Group>, Flags<[CoreOption,NoXarchOption]>;
-defm speculative_load_hardening : BoolOption<"speculative-load-hardening",
-  "CodeGenOpts.SpeculativeLoadHardening", DefaultsToFalse,
-  ChangedBy<PosFlag, [CC1Option]>, ResetBy<NegFlag>, BothFlags<[CoreOption]>,
-  "m">, Group<m_Group>;
+def mspeculative_load_hardening : Flag<["-"], "mspeculative-load-hardening">,
+  Group<m_Group>, Flags<[CoreOption,CC1Option]>;
+def mno_speculative_load_hardening : Flag<["-"], "mno-speculative-load-hardening">,
+  Group<m_Group>, Flags<[CoreOption]>;
 def mlvi_hardening : Flag<["-"], "mlvi-hardening">, Group<m_Group>, Flags<[CoreOption,NoXarchOption]>,
   HelpText<"Enable all mitigations for Load Value Injection (LVI)">;
 def mno_lvi_hardening : Flag<["-"], "mno-lvi-hardening">, Group<m_Group>, Flags<[CoreOption,NoXarchOption]>,
@@ -2964,18 +2815,16 @@ def mno_neg_immediates: Flag<["-"], "mno-neg-immediates">, Group<m_arm_Features_
   HelpText<"Disallow converting instructions with negative immediates to their negation or inversion.">;
 def mcmse : Flag<["-"], "mcmse">, Group<m_arm_Features_Group>,
   Flags<[NoXarchOption,CC1Option]>,
-  HelpText<"Allow use of CMSE (Armv8-M Security Extensions)">,
-  MarshallingInfoFlag<"LangOpts->Cmse">;
+  HelpText<"Allow use of CMSE (Armv8-M Security Extensions)">;
 def ForceAAPCSBitfieldLoad : Flag<["-"], "faapcs-bitfield-load">, Group<m_arm_Features_Group>,
   Flags<[NoXarchOption,CC1Option]>,
-  HelpText<"Follows the AAPCS standard that all volatile bit-field write generates at least one load. (ARM only).">,
-  MarshallingInfoFlag<"CodeGenOpts.ForceAAPCSBitfieldLoad">;
-defm aapcs_bitfield_width : BoolOption<"aapcs-bitfield-width",
-  "CodeGenOpts.AAPCSBitfieldWidth", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Do not follow">, ResetBy<PosFlag, [], "Follow">,
-  BothFlags<[NoXarchOption, CC1Option], " the AAPCS standard requirement stating that"
-            " volatile bit-field width is dictated by the field container type. (ARM only).">,
-  "f">, Group<m_arm_Features_Group>;
+  HelpText<"Follows the AAPCS standard that all volatile bit-field write generates at least one load. (ARM only).">;
+def ForceNoAAPCSBitfieldWidth : Flag<["-"], "fno-aapcs-bitfield-width">, Group<m_arm_Features_Group>,
+  Flags<[NoXarchOption,CC1Option]>,
+  HelpText<"Do not follow the AAPCS standard requirement that volatile bit-field width is dictated by the field container type. (ARM only).">;
+def AAPCSBitfieldWidth : Flag<["-"], "faapcs-bitfield-width">, Group<m_arm_Features_Group>,
+  Flags<[NoXarchOption,CC1Option]>,
+  HelpText<"Follow the AAPCS standard requirement stating that volatile bit-field width is dictated by the field container type. (ARM only).">;
 
 def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group<m_aarch64_Features_Group>,
   HelpText<"Generate code which only uses the general purpose registers (AArch64 only)">;
@@ -3139,20 +2988,16 @@ def msvr4_struct_return : Flag<["-"], "msvr4-struct-return">,
 def mvx : Flag<["-"], "mvx">, Group<m_Group>;
 def mno_vx : Flag<["-"], "mno-vx">, Group<m_Group>;
 
-defm zvector : BoolFOption<"zvector",
-  "LangOpts->ZVector", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Enable System z vector language extension">,
-  ResetBy<NegFlag>>;
+defm zvector : OptInFFlag<"zvector", "Enable System z vector language extension">;
 def mzvector : Flag<["-"], "mzvector">, Alias<fzvector>;
 def mno_zvector : Flag<["-"], "mno-zvector">, Alias<fno_zvector>;
 
 def mignore_xcoff_visibility : Flag<["-"], "mignore-xcoff-visibility">, Group<m_Group>,
 HelpText<"Not emit the visibility attribute for asm in AIX OS or give all symbols 'unspecified' visibility in XCOFF object file">,
   Flags<[CC1Option]>;
-defm backchain : BoolOption<"backchain",
-  "CodeGenOpts.Backchain", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Link stack frames through backchain on System Z">,
-  ResetBy<NegFlag>, BothFlags<[NoXarchOption,CC1Option]>, "m">, Group<m_Group>;
+def mbackchain : Flag<["-"], "mbackchain">, Group<m_Group>, Flags<[NoXarchOption,CC1Option]>,
+  HelpText<"Link stack frames through backchain on System Z">;
+def mno_backchain : Flag<["-"], "mno-backchain">, Group<m_Group>, Flags<[NoXarchOption,CC1Option]>;
 
 def mno_warn_nonportable_cfstrings : Flag<["-"], "mno-warn-nonportable-cfstrings">, Group<m_Group>;
 def mno_omit_leaf_frame_pointer : Flag<["-"], "mno-omit-leaf-frame-pointer">, Group<m_Group>;
@@ -3165,12 +3010,10 @@ def mtls_direct_seg_refs : Flag<["-"], "mtls-direct-seg-refs">, Group<m_Group>,
   HelpText<"Enable direct TLS access through segment registers (default)">;
 def mregparm_EQ : Joined<["-"], "mregparm=">, Group<m_Group>;
 def mrelax_all : Flag<["-"], "mrelax-all">, Group<m_Group>, Flags<[CC1Option,CC1AsOption]>,
-  HelpText<"(integrated-as) Relax all machine instructions">,
-  MarshallingInfoFlag<"CodeGenOpts.RelaxAll">;
+  HelpText<"(integrated-as) Relax all machine instructions">;
 def mincremental_linker_compatible : Flag<["-"], "mincremental-linker-compatible">, Group<m_Group>,
   Flags<[CC1Option,CC1AsOption]>,
-  HelpText<"(integrated-as) Emit an object file which can be used with an incremental linker">,
-  MarshallingInfoFlag<"CodeGenOpts.IncrementalLinkerCompatible">;
+  HelpText<"(integrated-as) Emit an object file which can be used with an incremental linker">;
 def mno_incremental_linker_compatible : Flag<["-"], "mno-incremental-linker-compatible">, Group<m_Group>,
   HelpText<"(integrated-as) Emit an object file which cannot be used with an incremental linker">;
 def mrtd : Flag<["-"], "mrtd">, Group<m_Group>, Flags<[CC1Option]>,
@@ -3178,8 +3021,7 @@ def mrtd : Flag<["-"], "mrtd">, Group<m_Group>, Flags<[CC1Option]>,
 def msmall_data_threshold_EQ : Joined <["-"], "msmall-data-threshold=">,
   Group<m_Group>, Alias<G>;
 def msoft_float : Flag<["-"], "msoft-float">, Group<m_Group>, Flags<[CC1Option]>,
-  HelpText<"Use software floating point">,
-  MarshallingInfoFlag<"CodeGenOpts.SoftFloat">;
+  HelpText<"Use software floating point">;
 def moutline_atomics : Flag<["-"], "moutline-atomics">, Group<f_clang_Group>, Flags<[CC1Option]>,
   HelpText<"Generate local calls to out-of-line atomic operations">;
 def mno_outline_atomics : Flag<["-"], "mno-outline-atomics">, Group<f_clang_Group>, Flags<[CC1Option]>,
@@ -3190,30 +3032,25 @@ def mimplicit_float : Flag<["-"], "mimplicit-float">, Group<m_Group>;
 def mrecip : Flag<["-"], "mrecip">, Group<m_Group>;
 def mrecip_EQ : CommaJoined<["-"], "mrecip=">, Group<m_Group>, Flags<[CC1Option]>;
 def mprefer_vector_width_EQ : Joined<["-"], "mprefer-vector-width=">, Group<m_Group>, Flags<[CC1Option]>,
-  HelpText<"Specifies preferred vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.">,
-  MarshallingInfoString<"CodeGenOpts.PreferVectorWidth">;
+  HelpText<"Specifies preferred vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.">;
 def mstack_protector_guard_EQ : Joined<["-"], "mstack-protector-guard=">, Group<m_Group>, Flags<[CC1Option]>,
   HelpText<"Use the given guard (global, tls) for addressing the stack-protector guard">;
 def mstack_protector_guard_offset_EQ : Joined<["-"], "mstack-protector-guard-offset=">, Group<m_Group>, Flags<[CC1Option]>,
   HelpText<"Use the given offset for addressing the stack-protector guard">;
 def mstack_protector_guard_reg_EQ : Joined<["-"], "mstack-protector-guard-reg=">, Group<m_Group>, Flags<[CC1Option]>,
   HelpText<"Use the given reg for addressing the stack-protector guard">;
-defm pie_copy_relocations : BoolOption<"pie-copy-relocations",
-  "CodeGenOpts.PIECopyRelocations", DefaultsToFalse,
-  ChangedBy<PosFlag, [CC1Option], "Use copy relocations support for PIE builds">,
-  ResetBy<NegFlag>, BothFlags<[]>, "m">, Group<m_Group>;
+def mpie_copy_relocations : Flag<["-"], "mpie-copy-relocations">, Group<m_Group>,
+  Flags<[CC1Option]>,
+  HelpText<"Use copy relocations support for PIE builds">;
+def mno_pie_copy_relocations : Flag<["-"], "mno-pie-copy-relocations">, Group<m_Group>;
 def mfentry : Flag<["-"], "mfentry">, HelpText<"Insert calls to fentry at function entry (x86/SystemZ only)">,
-  Flags<[CC1Option]>, Group<m_Group>,
-  MarshallingInfoFlag<"CodeGenOpts.CallFEntry">;
+  Flags<[CC1Option]>, Group<m_Group>;
 def mnop_mcount : Flag<["-"], "mnop-mcount">, HelpText<"Generate mcount/__fentry__ calls as nops. To activate they need to be patched in.">,
-  Flags<[CC1Option]>, Group<m_Group>,
-  MarshallingInfoFlag<"CodeGenOpts.MNopMCount">;
+  Flags<[CC1Option]>, Group<m_Group>;
 def mrecord_mcount : Flag<["-"], "mrecord-mcount">, HelpText<"Generate a __mcount_loc section entry for each __fentry__ call.">,
-  Flags<[CC1Option]>, Group<m_Group>,
-  MarshallingInfoFlag<"CodeGenOpts.RecordMCount">;
+  Flags<[CC1Option]>, Group<m_Group>;
 def mpacked_stack : Flag<["-"], "mpacked-stack">, HelpText<"Use packed stack layout (SystemZ only).">,
-  Flags<[CC1Option]>, Group<m_Group>,
-  MarshallingInfoFlag<"CodeGenOpts.PackedStack">;
+  Flags<[CC1Option]>, Group<m_Group>;
 def mno_packed_stack : Flag<["-"], "mno-packed-stack">, Flags<[CC1Option]>, Group<m_Group>;
 def mips16 : Flag<["-"], "mips16">, Group<m_mips_Features_Group>;
 def mno_mips16 : Flag<["-"], "mno-mips16">, Group<m_mips_Features_Group>;
@@ -3379,7 +3216,7 @@ def no_pedantic : Flag<["-", "--"], "no-pedantic">, Group<pedantic_Group>;
 def no__dead__strip__inits__and__terms : Flag<["-"], "no_dead_strip_inits_and_terms">;
 def nobuiltininc : Flag<["-"], "nobuiltininc">, Flags<[CC1Option, CoreOption]>,
   HelpText<"Disable builtin #include directories">,
-  MarshallingInfoNegativeFlag<"HeaderSearchOpts->UseBuiltinIncludes">;
+  MarshallingInfoFlag<"HeaderSearchOpts->UseBuiltinIncludes", "true">, IsNegative;
 def nogpuinc : Flag<["-"], "nogpuinc">, HelpText<"Do not add include paths for CUDA/HIP and"
   " do not include the default CUDA/HIP wrapper headers">;
 def : Flag<["-"], "nocudainc">, Alias<nogpuinc>;
@@ -3400,7 +3237,7 @@ def nostdinc : Flag<["-"], "nostdinc">, Flags<[CoreOption]>;
 def nostdlibinc : Flag<["-"], "nostdlibinc">;
 def nostdincxx : Flag<["-"], "nostdinc++">, Flags<[CC1Option]>,
   HelpText<"Disable standard #include directories for the C++ standard library">,
-  MarshallingInfoNegativeFlag<"HeaderSearchOpts->UseStandardCXXIncludes">;
+  MarshallingInfoFlag<"HeaderSearchOpts->UseStandardCXXIncludes", "true">, IsNegative;
 def nostdlib : Flag<["-"], "nostdlib">, Group<Link_Group>;
 def nostdlibxx : Flag<["-"], "nostdlib++">;
 def nolibsycl : Flag<["-"], "nolibsycl">, Flags<[NoXarchOption, CoreOption]>,
@@ -3414,8 +3251,7 @@ def pagezero__size : JoinedOrSeparate<["-"], "pagezero_size">;
 def pass_exit_codes : Flag<["-", "--"], "pass-exit-codes">, Flags<[Unsupported]>;
 def pedantic_errors : Flag<["-", "--"], "pedantic-errors">, Group<pedantic_Group>, Flags<[CC1Option]>;
 def pedantic : Flag<["-", "--"], "pedantic">, Group<pedantic_Group>, Flags<[CC1Option]>;
-def pg : Flag<["-"], "pg">, HelpText<"Enable mcount instrumentation">, Flags<[CC1Option]>,
-  MarshallingInfoFlag<"CodeGenOpts.InstrumentForProfiling">;
+def pg : Flag<["-"], "pg">, HelpText<"Enable mcount instrumentation">, Flags<[CC1Option]>;
 def pipe : Flag<["-", "--"], "pipe">,
   HelpText<"Use pipes between commands, when possible">;
 def prebind__all__twolevel__modules : Flag<["-"], "prebind_all_twolevel_modules">;
@@ -3424,8 +3260,7 @@ def preload : Flag<["-"], "preload">;
 def print_file_name_EQ : Joined<["-", "--"], "print-file-name=">,
   HelpText<"Print the full library path of <file>">, MetaVarName<"<file>">;
 def print_ivar_layout : Flag<["-"], "print-ivar-layout">, Flags<[CC1Option]>,
-  HelpText<"Enable Objective-C Ivar layout bitmap print trace">,
-  MarshallingInfoFlag<"LangOpts->ObjCGCBitmapPrint">;
+  HelpText<"Enable Objective-C Ivar layout bitmap print trace">;
 def print_libgcc_file_name : Flag<["-", "--"], "print-libgcc-file-name">,
   HelpText<"Print the library path for the currently used compiler runtime "
            "library (\"libgcc.a\" or \"libclang_rt.builtins.*.a\")">;
@@ -3447,10 +3282,9 @@ def print_targets : Flag<["-", "--"], "print-targets">,
   HelpText<"Print the registered targets">;
 def private__bundle : Flag<["-"], "private_bundle">;
 def pthreads : Flag<["-"], "pthreads">;
-defm pthread : BoolOption<"pthread",
-  "LangOpts->POSIXThreads", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Support POSIX threads in generated code">,
-  ResetBy<NegFlag>, BothFlags<[CC1Option]>>;
+def pthread : Flag<["-"], "pthread">, Flags<[CC1Option]>,
+  HelpText<"Support POSIX threads in generated code">;
+def no_pthread : Flag<["-"], "no-pthread">, Flags<[CC1Option]>;
 def p : Flag<["-"], "p">;
 def pie : Flag<["-"], "pie">, Group<Link_Group>;
 def static_pie : Flag<["-"], "static-pie">, Group<Link_Group>;
@@ -3555,8 +3389,7 @@ def gcc_toolchain : Joined<["--"], "gcc-toolchain=">, Flags<[NoXarchOption]>,
 def time : Flag<["-"], "time">,
   HelpText<"Time individual commands">;
 def traditional_cpp : Flag<["-", "--"], "traditional-cpp">, Flags<[CC1Option]>,
-  HelpText<"Enable some traditional CPP emulation">,
-  MarshallingInfoFlag<"LangOpts->TraditionalCPP">;
+  HelpText<"Enable some traditional CPP emulation">;
 def traditional : Flag<["-", "--"], "traditional">;
 def trigraphs : Flag<["-", "--"], "trigraphs">, Alias<ftrigraphs>,
   HelpText<"Process trigraph sequences">;
@@ -3567,7 +3400,7 @@ def umbrella : Separate<["-"], "umbrella">;
 def undefined : JoinedOrSeparate<["-"], "undefined">, Group<u_Group>;
 def undef : Flag<["-"], "undef">, Group<u_Group>, Flags<[CC1Option]>,
   HelpText<"undef all system defines">,
-  MarshallingInfoNegativeFlag<"PreprocessorOpts->UsePredefines">;
+  MarshallingInfoFlag<"PreprocessorOpts->UsePredefines", "true">, IsNegative;
 def unexported__symbols__list : Separate<["-"], "unexported_symbols_list">;
 def u : JoinedOrSeparate<["-"], "u">, Group<u_Group>;
 def v : Flag<["-"], "v">, Flags<[CC1Option, CoreOption]>,
@@ -3587,10 +3420,7 @@ def x : JoinedOrSeparate<["-"], "x">, Flags<[NoXarchOption,CC1Option]>,
   MetaVarName<"<language>">;
 def y : Joined<["-"], "y">;
 
-defm integrated_as : BoolFOption<"integrated-as",
-  "CodeGenOpts.DisableIntegratedAS", DefaultsToFalse,
-  ChangedBy<NegFlag, [], "Disable">, ResetBy<PosFlag, [], "Enable">,
-  BothFlags<[], " the integrated assembler">>;
+defm integrated_as : OptOutFFlag<"integrated-as", "Enable the integrated assembler", "Disable the integrated assembler">;
 
 def fintegrated_cc1 : Flag<["-"], "fintegrated-cc1">,
                       Flags<[CoreOption, NoXarchOption]>, Group<f_Group>,
@@ -4030,11 +3860,8 @@ defm inline_small_functions : BooleanFFlag<"inline-small-functions">,
 defm ipa_cp : BooleanFFlag<"ipa-cp">,
     Group<clang_ignored_gcc_optimization_f_Group>;
 defm ivopts : BooleanFFlag<"ivopts">, Group<clang_ignored_gcc_optimization_f_Group>;
-def fsemantic_interposition : Flag<["-"], "fsemantic-interposition">, Group<f_Group>, Flags<[CC1Option]>,
-  MarshallingInfoFlag<"LangOpts->SemanticInterposition">;
-// An explicit -fno-semantic-interposition infers dso_local.
-def fno_semantic_interposition: Flag<["-"], "fno-semantic-interposition">, Group<f_Group>, Flags<[CC1Option]>,
-  MarshallingInfoFlag<"LangOpts->ExplicitNoSemanticInterposition">;
+def fsemantic_interposition : Flag<["-"], "fsemantic-interposition">, Group<f_Group>, Flags<[CC1Option]>;
+def fno_semantic_interposition: Flag<["-"], "fno-semantic-interposition">, Group<f_Group>, Flags<[CC1Option]>;
 defm non_call_exceptions : BooleanFFlag<"non-call-exceptions">, Group<clang_ignored_f_Group>;
 defm peel_loops : BooleanFFlag<"peel-loops">, Group<clang_ignored_gcc_optimization_f_Group>;
 defm permissive : BooleanFFlag<"permissive">, Group<clang_ignored_f_Group>;
@@ -4401,50 +4228,33 @@ def migrator_no_finalize_removal : Flag<["-"], "no-finalize-removal">,
 //===----------------------------------------------------------------------===//
 
 let Flags = [CC1Option, CC1AsOption, NoDriverOption] in {
-def debug_info_kind_EQ : Joined<["-"], "debug-info-kind=">,
-  Values<"line-tables-only,line-directives-only,constructor,limited,standalone,unused-types">,
-  NormalizedValuesScope<"codegenoptions">,
-  NormalizedValues<["DebugLineTablesOnly", "DebugDirectivesOnly", "DebugInfoConstructor",
-                    "LimitedDebugInfo", "FullDebugInfo", "UnusedTypeInfo"]>,
-  MarshallingInfoString<"CodeGenOpts.DebugInfo", "NoDebugInfo">, AutoNormalizeEnum;
+def debug_info_kind_EQ : Joined<["-"], "debug-info-kind=">;
 def debug_info_macro : Flag<["-"], "debug-info-macro">,
-  HelpText<"Emit macro debug information">,
-  MarshallingInfoFlag<"CodeGenOpts.MacroDebugInfo">;
+  HelpText<"Emit macro debug information">;
 def default_function_attr : Separate<["-"], "default-function-attr">,
   HelpText<"Apply given attribute to all functions">;
-def dwarf_version_EQ : Joined<["-"], "dwarf-version=">,
-  MarshallingInfoStringInt<"CodeGenOpts.DwarfVersion">;
-def debugger_tuning_EQ : Joined<["-"], "debugger-tuning=">,
-  Values<"gdb,lldb,sce">,
-  NormalizedValuesScope<"llvm::DebuggerKind">, NormalizedValues<["GDB", "LLDB", "SCE"]>,
-  MarshallingInfoString<"CodeGenOpts.DebuggerTuning", "Default">, AutoNormalizeEnum;
+def dwarf_version_EQ : Joined<["-"], "dwarf-version=">;
+def debugger_tuning_EQ : Joined<["-"], "debugger-tuning=">;
 def dwarf_debug_flags : Separate<["-"], "dwarf-debug-flags">,
-  HelpText<"The string to embed in the Dwarf debug flags record.">,
-  MarshallingInfoString<"CodeGenOpts.DwarfDebugFlags">;
+  HelpText<"The string to embed in the Dwarf debug flags record.">;
 def record_command_line : Separate<["-"], "record-command-line">,
-  HelpText<"The string to embed in the .LLVM.command.line section.">,
-  MarshallingInfoString<"CodeGenOpts.RecordCommandLine">;
+  HelpText<"The string to embed in the .LLVM.command.line section.">;
 def compress_debug_sections_EQ : Joined<["-", "--"], "compress-debug-sections=">,
     HelpText<"DWARF debug sections compression type">;
 def compress_debug_sections : Flag<["-", "--"], "compress-debug-sections">,
   Alias<compress_debug_sections_EQ>, AliasArgs<["zlib"]>;
 def mno_exec_stack : Flag<["-"], "mnoexecstack">,
-  HelpText<"Mark the file as not needing an executable stack">,
-  MarshallingInfoFlag<"CodeGenOpts.NoExecStack">;
+  HelpText<"Mark the file as not needing an executable stack">;
 def massembler_no_warn : Flag<["-"], "massembler-no-warn">,
-  HelpText<"Make assembler not emit warnings">,
-  MarshallingInfoFlag<"CodeGenOpts.NoWarn">;
+  HelpText<"Make assembler not emit warnings">;
 def massembler_fatal_warnings : Flag<["-"], "massembler-fatal-warnings">,
-  HelpText<"Make assembler warnings fatal">,
-  MarshallingInfoFlag<"CodeGenOpts.FatalWarnings">;
+  HelpText<"Make assembler warnings fatal">;
 def mrelax_relocations : Flag<["--"], "mrelax-relocations">,
-    HelpText<"Use relaxable elf relocations">,
-    MarshallingInfoFlag<"CodeGenOpts.RelaxELFRelocations">;
+    HelpText<"Use relaxable elf relocations">;
 def msave_temp_labels : Flag<["-"], "msave-temp-labels">,
   HelpText<"Save temporary labels in the symbol table. "
            "Note this may change .s semantics and shouldn't generally be used "
-           "on compiler-generated code.">,
-  MarshallingInfoFlag<"CodeGenOpts.SaveTempLabels">;
+           "on compiler-generated code.">;
 def mrelocation_model : Separate<["-"], "mrelocation-model">,
   HelpText<"The relocation model to use">, Values<"static,pic,ropi,rwpi,ropi-rwpi,dynamic-no-pic">,
   NormalizedValuesScope<"llvm::Reloc">,
@@ -4452,55 +4262,42 @@ def mrelocation_model : Separate<["-"], "mrelocation-model">,
   MarshallingInfoString<"CodeGenOpts.RelocationModel", "PIC_">,
   AutoNormalizeEnum;
 def fno_math_builtin : Flag<["-"], "fno-math-builtin">,
-  HelpText<"Disable implicit builtin knowledge of math functions">,
-  MarshallingInfoFlag<"LangOpts->NoMathBuiltin">;
+  HelpText<"Disable implicit builtin knowledge of math functions">;
 def fuse_ctor_homing: Flag<["-"], "fuse-ctor-homing">,
     HelpText<"Use constructor homing if we are using limited debug info already">;
 }
 
 def disable_llvm_verifier : Flag<["-"], "disable-llvm-verifier">,
-  HelpText<"Don't run the LLVM IR verifier pass">,
-  MarshallingInfoNegativeFlag<"CodeGenOpts.VerifyModule">;
+  HelpText<"Don't run the LLVM IR verifier pass">;
 def disable_llvm_passes : Flag<["-"], "disable-llvm-passes">,
   HelpText<"Use together with -emit-llvm to get pristine LLVM IR from the "
-           "frontend by not running any LLVM passes at all">,
-  MarshallingInfoFlag<"CodeGenOpts.DisableLLVMPasses">;
+           "frontend by not running any LLVM passes at all">;
 def disable_llvm_optzns : Flag<["-"], "disable-llvm-optzns">,
   Alias<disable_llvm_passes>;
 def disable_lifetimemarkers : Flag<["-"], "disable-lifetime-markers">,
   HelpText<"Disable lifetime-markers emission even when optimizations are "
-           "enabled">,
-  MarshallingInfoFlag<"CodeGenOpts.DisableLifetimeMarkers">;
+           "enabled">;
 def disable_O0_optnone : Flag<["-"], "disable-O0-optnone">,
-  HelpText<"Disable adding the optnone attribute to functions at O0">,
-  MarshallingInfoFlag<"CodeGenOpts.DisableO0ImplyOptNone">;
+  HelpText<"Disable adding the optnone attribute to functions at O0">;
 def disable_red_zone : Flag<["-"], "disable-red-zone">,
-  HelpText<"Do not emit code that uses the red zone.">,
-  MarshallingInfoFlag<"CodeGenOpts.DisableRedZone">;
+  HelpText<"Do not emit code that uses the red zone.">;
 def dwarf_ext_refs : Flag<["-"], "dwarf-ext-refs">,
   HelpText<"Generate debug info with external references to clang modules"
-           " or precompiled headers">,
-  MarshallingInfoFlag<"CodeGenOpts.DebugTypeExtRefs">;
+           " or precompiled headers">;
 def dwarf_explicit_import : Flag<["-"], "dwarf-explicit-import">,
   HelpText<"Generate explicit import from anonymous namespace to containing"
-           " scope">,
-  MarshallingInfoFlag<"CodeGenOpts.DebugExplicitImport">;
+           " scope">;
 def debug_forward_template_params : Flag<["-"], "debug-forward-template-params">,
   HelpText<"Emit complete descriptions of template parameters in forward"
-           " declarations">,
-  MarshallingInfoFlag<"CodeGenOpts.DebugFwdTemplateParams">;
+           " declarations">;
 def fforbid_guard_variables : Flag<["-"], "fforbid-guard-variables">,
-  HelpText<"Emit an error if a C++ static local initializer would need a guard variable">,
-  MarshallingInfoFlag<"CodeGenOpts.ForbidGuardVariables">;
+  HelpText<"Emit an error if a C++ static local initializer would need a guard variable">;
 def no_implicit_float : Flag<["-"], "no-implicit-float">,
-  HelpText<"Don't generate implicit floating point instructions">,
-  MarshallingInfoFlag<"CodeGenOpts.NoImplicitFloat">;
+  HelpText<"Don't generate implicit floating point instructions">;
 def fdump_vtable_layouts : Flag<["-"], "fdump-vtable-layouts">,
-  HelpText<"Dump the layouts of all vtables that will be emitted in a translation unit">,
-  MarshallingInfoFlag<"LangOpts->DumpVTableLayouts">;
+  HelpText<"Dump the layouts of all vtables that will be emitted in a translation unit">;
 def fmerge_functions : Flag<["-"], "fmerge-functions">,
-  HelpText<"Permit merging of identical functions when optimizing.">,
-  MarshallingInfoFlag<"CodeGenOpts.MergeFunctions">;
+  HelpText<"Permit merging of identical functions when optimizing.">;
 def coverage_data_file : Separate<["-"], "coverage-data-file">,
   HelpText<"Emit coverage data to this filename.">;
 def coverage_data_file_EQ : Joined<["-"], "coverage-data-file=">,
@@ -4512,29 +4309,21 @@ def coverage_notes_file_EQ : Joined<["-"], "coverage-notes-file=">,
 def coverage_version_EQ : Joined<["-"], "coverage-version=">,
   HelpText<"Four-byte version string for gcov files.">;
 def dump_coverage_mapping : Flag<["-"], "dump-coverage-mapping">,
-  HelpText<"Dump the coverage mapping records, for testing">,
-  MarshallingInfoFlag<"CodeGenOpts.DumpCoverageMapping">;
+  HelpText<"Dump the coverage mapping records, for testing">;
 def fuse_register_sized_bitfield_access: Flag<["-"], "fuse-register-sized-bitfield-access">,
-  HelpText<"Use register sized accesses to bit-fields, when possible.">,
-  MarshallingInfoFlag<"CodeGenOpts.UseRegisterSizedBitfieldAccess">;
+  HelpText<"Use register sized accesses to bit-fields, when possible.">;
 def relaxed_aliasing : Flag<["-"], "relaxed-aliasing">,
-  HelpText<"Turn off Type Based Alias Analysis">,
-  MarshallingInfoFlag<"CodeGenOpts.RelaxedAliasing">;
+  HelpText<"Turn off Type Based Alias Analysis">;
 def no_struct_path_tbaa : Flag<["-"], "no-struct-path-tbaa">,
-  HelpText<"Turn off struct-path aware Type Based Alias Analysis">,
-  MarshallingInfoNegativeFlag<"CodeGenOpts.StructPathTBAA">;
+  HelpText<"Turn off struct-path aware Type Based Alias Analysis">;
 def new_struct_path_tbaa : Flag<["-"], "new-struct-path-tbaa">,
   HelpText<"Enable enhanced struct-path aware Type Based Alias Analysis">;
 def mdebug_pass : Separate<["-"], "mdebug-pass">,
-  HelpText<"Enable additional debug output">,
-  MarshallingInfoString<"CodeGenOpts.DebugPass">;
+  HelpText<"Enable additional debug output">;
 def mframe_pointer_EQ : Joined<["-"], "mframe-pointer=">,
-  HelpText<"Specify which frame pointers to retain (all, non-leaf, none).">, Values<"all,non-leaf,none">,
-  NormalizedValuesScope<"CodeGenOptions::FramePointerKind">, NormalizedValues<["All", "NonLeaf", "None"]>,
-  MarshallingInfoString<"CodeGenOpts.FramePointer", "None">, AutoNormalizeEnum;
+  HelpText<"Specify which frame pointers to retain (all, non-leaf, none).">, Values<"all,non-leaf,none">;
 def mdisable_tail_calls : Flag<["-"], "mdisable-tail-calls">,
-  HelpText<"Disable tail call optimization, keeping the call stack accurate">,
-  MarshallingInfoFlag<"CodeGenOpts.DisableTailCalls">;
+  HelpText<"Disable tail call optimization, keeping the call stack accurate">;
 def menable_no_infinities : Flag<["-"], "menable-no-infs">,
   HelpText<"Allow optimization to assume there are no infinities.">,
   MarshallingInfoFlag<"LangOpts->NoHonorInfs">, ImpliedByAnyOf<[ffinite_math_only]>;
@@ -4545,31 +4334,23 @@ def mreassociate : Flag<["-"], "mreassociate">,
   HelpText<"Allow reassociation transformations for floating-point instructions">,
   MarshallingInfoFlag<"LangOpts->AllowFPReassoc">, ImpliedByAnyOf<[menable_unsafe_fp_math]>;
 def mabi_EQ_ieeelongdouble : Flag<["-"], "mabi=ieeelongdouble">,
-  HelpText<"Use IEEE 754 quadruple-precision for long double">,
-  MarshallingInfoFlag<"LangOpts->PPCIEEELongDouble">;
+  HelpText<"Use IEEE 754 quadruple-precision for long double">;
 def mfloat_abi : Separate<["-"], "mfloat-abi">,
-  HelpText<"The float ABI to use">,
-  MarshallingInfoString<"CodeGenOpts.FloatABI">;
+  HelpText<"The float ABI to use">;
 def mtp : Separate<["-"], "mtp">,
   HelpText<"Mode for reading thread pointer">;
 def mlimit_float_precision : Separate<["-"], "mlimit-float-precision">,
-  HelpText<"Limit float precision to the given value">,
-  MarshallingInfoString<"CodeGenOpts.LimitFloatPrecision">;
+  HelpText<"Limit float precision to the given value">;
 def split_stacks : Flag<["-"], "split-stacks">,
-  HelpText<"Try to use a split stack if possible.">,
-  MarshallingInfoFlag<"CodeGenOpts.EnableSegmentedStacks">;
+  HelpText<"Try to use a split stack if possible.">;
 def mregparm : Separate<["-"], "mregparm">,
-  HelpText<"Limit the number of registers available for integer arguments">,
-  MarshallingInfoStringInt<"CodeGenOpts.NumRegisterParameters">;
+  HelpText<"Limit the number of registers available for integer arguments">;
 def msmall_data_limit : Separate<["-"], "msmall-data-limit">,
-  HelpText<"Put global and static data smaller than the limit into a special section">,
-  MarshallingInfoStringInt<"CodeGenOpts.SmallDataLimit">;
+  HelpText<"Put global and static data smaller than the limit into a special section">;
 def munwind_tables : Flag<["-"], "munwind-tables">,
-  HelpText<"Generate unwinding tables for all functions">,
-  MarshallingInfoFlag<"CodeGenOpts.UnwindTables">;
+  HelpText<"Generate unwinding tables for all functions">;
 def mconstructor_aliases : Flag<["-"], "mconstructor-aliases">,
-  HelpText<"Emit complete constructors and destructors as aliases when possible">,
-  MarshallingInfoFlag<"CodeGenOpts.CXXCtorDtorAliases">;
+  HelpText<"Emit complete constructors and destructors as aliases when possible">;
 def mlink_bitcode_file : Separate<["-"], "mlink-bitcode-file">,
   HelpText<"Link the given bitcode file before performing optimizations.">;
 def mlink_builtin_bitcode : Separate<["-"], "mlink-builtin-bitcode">,
@@ -4578,96 +4359,72 @@ def mlink_builtin_bitcode : Separate<["-"], "mlink-builtin-bitcode">,
 def mlink_cuda_bitcode : Separate<["-"], "mlink-cuda-bitcode">,
   Alias<mlink_builtin_bitcode>;
 def vectorize_loops : Flag<["-"], "vectorize-loops">,
-  HelpText<"Run the Loop vectorization passes">,
-  MarshallingInfoFlag<"CodeGenOpts.VectorizeLoop">;
+  HelpText<"Run the Loop vectorization passes">;
 def vectorize_slp : Flag<["-"], "vectorize-slp">,
-  HelpText<"Run the SLP vectorization passes">,
-  MarshallingInfoFlag<"CodeGenOpts.VectorizeSLP">;
+  HelpText<"Run the SLP vectorization passes">;
 def dependent_lib : Joined<["--"], "dependent-lib=">,
   HelpText<"Add dependent library">;
 def linker_option : Joined<["--"], "linker-option=">,
   HelpText<"Add linker option">;
 def fsanitize_coverage_type : Joined<["-"], "fsanitize-coverage-type=">,
-                              HelpText<"Sanitizer coverage type">,
-                              MarshallingInfoStringInt<"CodeGenOpts.SanitizeCoverageType">;
+                              HelpText<"Sanitizer coverage type">;
 def fsanitize_coverage_indirect_calls
     : Flag<["-"], "fsanitize-coverage-indirect-calls">,
-      HelpText<"Enable sanitizer coverage for indirect calls">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageIndirectCalls">;
+      HelpText<"Enable sanitizer coverage for indirect calls">;
 def fsanitize_coverage_trace_bb
     : Flag<["-"], "fsanitize-coverage-trace-bb">,
-      HelpText<"Enable basic block tracing in sanitizer coverage">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageTraceBB">;
+      HelpText<"Enable basic block tracing in sanitizer coverage">;
 def fsanitize_coverage_trace_cmp
     : Flag<["-"], "fsanitize-coverage-trace-cmp">,
-      HelpText<"Enable cmp instruction tracing in sanitizer coverage">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageTraceCmp">;
+      HelpText<"Enable cmp instruction tracing in sanitizer coverage">;
 def fsanitize_coverage_trace_div
     : Flag<["-"], "fsanitize-coverage-trace-div">,
-      HelpText<"Enable div instruction tracing in sanitizer coverage">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageTraceDiv">;
+      HelpText<"Enable div instruction tracing in sanitizer coverage">;
 def fsanitize_coverage_trace_gep
     : Flag<["-"], "fsanitize-coverage-trace-gep">,
-      HelpText<"Enable gep instruction tracing in sanitizer coverage">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageTraceGep">;
+      HelpText<"Enable gep instruction tracing in sanitizer coverage">;
 def fsanitize_coverage_8bit_counters
     : Flag<["-"], "fsanitize-coverage-8bit-counters">,
-      HelpText<"Enable frequency counters in sanitizer coverage">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverage8bitCounters">;
+      HelpText<"Enable frequency counters in sanitizer coverage">;
 def fsanitize_coverage_inline_8bit_counters
     : Flag<["-"], "fsanitize-coverage-inline-8bit-counters">,
-      HelpText<"Enable inline 8-bit counters in sanitizer coverage">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageInline8bitCounters">;
+      HelpText<"Enable inline 8-bit counters in sanitizer coverage">;
 def fsanitize_coverage_inline_bool_flag
     : Flag<["-"], "fsanitize-coverage-inline-bool-flag">,
-      HelpText<"Enable inline bool flag in sanitizer coverage">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageInlineBoolFlag">;
+      HelpText<"Enable inline bool flag in sanitizer coverage">;
 def fsanitize_coverage_pc_table
     : Flag<["-"], "fsanitize-coverage-pc-table">,
-      HelpText<"Create a table of coverage-instrumented PCs">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoveragePCTable">;
+      HelpText<"Create a table of coverage-instrumented PCs">;
 def fsanitize_coverage_trace_pc
     : Flag<["-"], "fsanitize-coverage-trace-pc">,
-      HelpText<"Enable PC tracing in sanitizer coverage">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageTracePC">;
+      HelpText<"Enable PC tracing in sanitizer coverage">;
 def fsanitize_coverage_trace_pc_guard
     : Flag<["-"], "fsanitize-coverage-trace-pc-guard">,
-      HelpText<"Enable PC tracing with guard in sanitizer coverage">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageTracePCGuard">;
+      HelpText<"Enable PC tracing with guard in sanitizer coverage">;
 def fsanitize_coverage_no_prune
     : Flag<["-"], "fsanitize-coverage-no-prune">,
-      HelpText<"Disable coverage pruning (i.e. instrument all blocks/edges)">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageNoPrune">;
+      HelpText<"Disable coverage pruning (i.e. instrument all blocks/edges)">;
 def fsanitize_coverage_stack_depth
     : Flag<["-"], "fsanitize-coverage-stack-depth">,
-      HelpText<"Enable max stack depth tracing">,
-      MarshallingInfoFlag<"CodeGenOpts.SanitizeCoverageStackDepth">;
+      HelpText<"Enable max stack depth tracing">;
 def fpatchable_function_entry_offset_EQ
     : Joined<["-"], "fpatchable-function-entry-offset=">, MetaVarName<"<M>">,
-      HelpText<"Generate M NOPs before function entry">,
-      MarshallingInfoStringInt<"CodeGenOpts.PatchableFunctionEntryOffset">;
+      HelpText<"Generate M NOPs before function entry">;
 def fprofile_instrument_EQ : Joined<["-"], "fprofile-instrument=">,
     HelpText<"Enable PGO instrumentation. The accepted value is clang, llvm, "
-             "or none">, Values<"none,clang,llvm,csllvm">,
-    NormalizedValuesScope<"CodeGenOptions">,
-    NormalizedValues<["ProfileNone", "ProfileClangInstr", "ProfileIRInstr", "ProfileCSIRInstr"]>,
-    MarshallingInfoString<"CodeGenOpts.ProfileInstr", "ProfileNone">, AutoNormalizeEnum;
+             "or none">, Values<"none,clang,llvm">;
 def fprofile_instrument_path_EQ : Joined<["-"], "fprofile-instrument-path=">,
     HelpText<"Generate instrumented code to collect execution counts into "
-             "<file> (overridden by LLVM_PROFILE_FILE env var)">,
-    MarshallingInfoString<"CodeGenOpts.InstrProfileOutput">;
+             "<file> (overridden by LLVM_PROFILE_FILE env var)">;
 def fprofile_instrument_use_path_EQ :
     Joined<["-"], "fprofile-instrument-use-path=">,
-    HelpText<"Specify the profile path in PGO use compilation">,
-    MarshallingInfoString<"CodeGenOpts.ProfileInstrumentUsePath">;
+    HelpText<"Specify the profile path in PGO use compilation">;
 def flto_visibility_public_std:
     Flag<["-"], "flto-visibility-public-std">,
-    HelpText<"Use public LTO visibility for classes in std and stdext namespaces">,
-    MarshallingInfoFlag<"CodeGenOpts.LTOVisibilityPublicStd">;
-defm lto_unit : BoolFOption<"lto-unit",
-  "CodeGenOpts.LTOUnit", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Emit IR to support LTO unit features (CFI, whole program vtable opt)">,
-  ResetBy<NegFlag>>;
+    HelpText<"Use public LTO visibility for classes in std and stdext namespaces">;
+def flto_unit: Flag<["-"], "flto-unit">,
+    HelpText<"Emit IR to support LTO unit features (CFI, whole program vtable opt)">;
+def fno_lto_unit: Flag<["-"], "fno-lto-unit">;
 defm debug_pass_manager : BoolOption<"debug-pass-manager",
   "CodeGenOpts.DebugPassManager", DefaultsToFalse,
   ChangedBy<PosFlag, [], "Prints debug information for the new pass manager">,
@@ -4675,23 +4432,18 @@ defm debug_pass_manager : BoolOption<"debug-pass-manager",
   BothFlags<[]>, "f">;
 def fexperimental_debug_variable_locations : Flag<["-"],
     "fexperimental-debug-variable-locations">,
-    HelpText<"Use experimental new value-tracking variable locations">,
-    MarshallingInfoFlag<"CodeGenOpts.ValueTrackingVariableLocations">;
+    HelpText<"Use experimental new value-tracking variable locations">;
 // The driver option takes the key as a parameter to the -msign-return-address=
 // and -mbranch-protection= options, but CC1 has a separate option so we
 // don't have to parse the parameter twice.
 def msign_return_address_key_EQ : Joined<["-"], "msign-return-address-key=">,
     Values<"a_key,b_key">;
-def mbranch_target_enforce : Flag<["-"], "mbranch-target-enforce">,
-  MarshallingInfoFlag<"LangOpts->BranchTargetEnforcement">;
-def fno_dllexport_inlines : Flag<["-"], "fno-dllexport-inlines">,
-  MarshallingInfoNegativeFlag<"LangOpts->DllExportInlines">;
+def mbranch_target_enforce : Flag<["-"], "mbranch-target-enforce">;
+def fno_dllexport_inlines : Flag<["-"], "fno-dllexport-inlines">;
 def cfguard_no_checks : Flag<["-"], "cfguard-no-checks">,
-    HelpText<"Emit Windows Control Flow Guard tables only (no checks)">,
-    MarshallingInfoFlag<"CodeGenOpts.ControlFlowGuardNoChecks">;
+    HelpText<"Emit Windows Control Flow Guard tables only (no checks)">;
 def cfguard : Flag<["-"], "cfguard">,
-    HelpText<"Emit Windows Control Flow Guard tables and checks">,
-    MarshallingInfoFlag<"CodeGenOpts.ControlFlowGuard">;
+    HelpText<"Emit Windows Control Flow Guard tables and checks">;
 
 def fdenormal_fp_math_f32_EQ : Joined<["-"], "fdenormal-fp-math-f32=">,
    Group<f_Group>;
@@ -4793,10 +4545,10 @@ def code_completion_patterns : Flag<["-"], "code-completion-patterns">,
   MarshallingInfoFlag<"FrontendOpts.CodeCompleteOpts.IncludeCodePatterns">;
 def no_code_completion_globals : Flag<["-"], "no-code-completion-globals">,
   HelpText<"Do not include global declarations in code-completion results.">,
-  MarshallingInfoNegativeFlag<"FrontendOpts.CodeCompleteOpts.IncludeGlobals">;
+  MarshallingInfoFlag<"FrontendOpts.CodeCompleteOpts.IncludeGlobals", "true">, IsNegative;
 def no_code_completion_ns_level_decls : Flag<["-"], "no-code-completion-ns-level-decls">,
   HelpText<"Do not include declarations inside namespaces (incl. global namespace) in the code-completion results.">,
-  MarshallingInfoNegativeFlag<"FrontendOpts.CodeCompleteOpts.IncludeNamespaceLevelDecls">;
+  MarshallingInfoFlag<"FrontendOpts.CodeCompleteOpts.IncludeNamespaceLevelDecls", "true">, IsNegative;
 def code_completion_brief_comments : Flag<["-"], "code-completion-brief-comments">,
   HelpText<"Include brief documentation comments in code-completion results.">,
   MarshallingInfoFlag<"FrontendOpts.CodeCompleteOpts.IncludeBriefComments">;
@@ -4807,8 +4559,7 @@ def disable_free : Flag<["-"], "disable-free">,
   HelpText<"Disable freeing of memory on exit">,
   MarshallingInfoFlag<"FrontendOpts.DisableFree">;
 def discard_value_names : Flag<["-"], "discard-value-names">,
-  HelpText<"Discard value names in LLVM IR">,
-  MarshallingInfoFlag<"CodeGenOpts.DiscardValueNames">;
+  HelpText<"Discard value names in LLVM IR">;
 def load : Separate<["-"], "load">, MetaVarName<"<dsopath>">,
   HelpText<"Load the named plugin (dynamic shared object)">;
 def plugin : Separate<["-"], "plugin">, MetaVarName<"<name>">,
@@ -4826,10 +4577,9 @@ def ast_dump_filter : Separate<["-"], "ast-dump-filter">,
   MarshallingInfoString<"FrontendOpts.ASTDumpFilter">;
 def fno_modules_global_index : Flag<["-"], "fno-modules-global-index">,
   HelpText<"Do not automatically generate or update the global module index">,
-  MarshallingInfoNegativeFlag<"FrontendOpts.UseGlobalModuleIndex">;
+  MarshallingInfoFlag<"FrontendOpts.UseGlobalModuleIndex", "true">, IsNegative;
 def fno_modules_error_recovery : Flag<["-"], "fno-modules-error-recovery">,
-  HelpText<"Do not automatically import modules for error recovery">,
-  MarshallingInfoNegativeFlag<"LangOpts->ModulesErrorRecovery">;
+  HelpText<"Do not automatically import modules for error recovery">;
 def fmodule_map_file_home_is_cwd : Flag<["-"], "fmodule-map-file-home-is-cwd">,
   HelpText<"Use the current working directory as the home directory of "
            "module maps specified by -fmodule-map-file=<FILE>">,
@@ -4852,13 +4602,11 @@ def fmodules_local_submodule_visibility :
 def fmodules_codegen :
   Flag<["-"], "fmodules-codegen">,
   HelpText<"Generate code for uses of this module that assumes an explicit "
-           "object file will be built for the module">,
-  MarshallingInfoFlag<"LangOpts->ModulesCodegen">;
+           "object file will be built for the module">;
 def fmodules_debuginfo :
   Flag<["-"], "fmodules-debuginfo">,
   HelpText<"Generate debug info for types in an object file built from this "
-           "module and do not generate them elsewhere">,
-  MarshallingInfoFlag<"LangOpts->ModulesDebugInfo">;
+           "module and do not generate them elsewhere">;
 def fmodule_format_EQ : Joined<["-"], "fmodule-format=">,
   HelpText<"Select the container format for clang modules and PCH. "
            "Supported options are 'raw' and 'obj'.">,
@@ -4871,19 +4619,15 @@ def fconcepts_ts : Flag<["-"], "fconcepts-ts">,
   HelpText<"Enable C++ Extensions for Concepts. (deprecated - use -std=c++2a)">;
 def fno_concept_satisfaction_caching : Flag<["-"],
                                             "fno-concept-satisfaction-caching">,
-  HelpText<"Disable satisfaction caching for C++2a Concepts.">,
-  MarshallingInfoNegativeFlag<"LangOpts->ConceptSatisfactionCaching">;
+  HelpText<"Disable satisfaction caching for C++2a Concepts.">;
 
-defm recovery_ast : BoolOption<"recovery-ast",
-  "LangOpts->RecoveryAST", DefaultsToTrue,
-  ChangedBy<NegFlag>, ResetBy<PosFlag, [], "Preserve expressions in AST rather "
-                              "than dropping them when encountering semantic errors">,
-  BothFlags<[]>, "f">;
-defm recovery_ast_type : BoolOption<"recovery-ast-type",
-  "LangOpts->RecoveryASTType", DefaultsToTrue,
-  ChangedBy<NegFlag>, ResetBy<PosFlag, [], "Preserve the type for recovery "
-                              "expressions when possible">,
-  BothFlags<[]>, "f">;
+def frecovery_ast : Flag<["-"], "frecovery-ast">,
+  HelpText<"Preserve expressions in AST rather than dropping them when "
+           "encountering semantic errors">;
+def fno_recovery_ast : Flag<["-"], "fno-recovery-ast">;
+def frecovery_ast_type : Flag<["-"], "frecovery-ast-type">,
+  HelpText<"Preserve the type for recovery expressions when possible">;
+def fno_recovery_ast_type : Flag<["-"], "fno-recovery-ast-type">;
 
 let Group = Action_Group in {
 
@@ -4961,11 +4705,10 @@ def print_dependency_directives_minimized_source : Flag<["-"],
   HelpText<"Print the output of the dependency directives source minimizer">;
 }
 
-defm emit_llvm_uselists : BoolOption<"emit-llvm-uselists",
-  "CodeGenOpts.EmitLLVMUseLists", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Preserve">,
-  ResetBy<NegFlag, [], "Don't preserve">,
-  BothFlags<[], " order of LLVM use-lists when serializing">>;
+def emit_llvm_uselists : Flag<["-"], "emit-llvm-uselists">,
+  HelpText<"Preserve order of LLVM use-lists when serializing">;
+def no_emit_llvm_uselists : Flag<["-"], "no-emit-llvm-uselists">,
+  HelpText<"Don't preserve order of LLVM use-lists when serializing">;
 
 def mt_migrate_directory : Separate<["-"], "mt-migrate-directory">,
   HelpText<"Directory for temporary files produced during ARC or ObjC migration">,
@@ -4976,11 +4719,10 @@ def arcmt_action_EQ : Joined<["-"], "arcmt-action=">, Flags<[CC1Option, NoDriver
   NormalizedValuesScope<"FrontendOptions">,
   NormalizedValues<["ARCMT_Check", "ARCMT_Modify", "ARCMT_Migrate"]>,
   MarshallingInfoString<"FrontendOpts.ARCMTAction", "ARCMT_None">,
-  AutoNormalizeEnum;
+  AutoNormalizeEnumJoined;
 
 def opt_record_file : Separate<["-"], "opt-record-file">,
-  HelpText<"File name to use for YAML optimization record output">,
-  MarshallingInfoString<"CodeGenOpts.OptRecordFile">;
+  HelpText<"File name to use for YAML optimization record output">;
 def opt_record_passes : Separate<["-"], "opt-record-passes">,
   HelpText<"Only record remark information for passes whose names match the given regular expression">;
 def opt_record_format : Separate<["-"], "opt-record-format">,
@@ -4995,8 +4737,7 @@ def stats_file : Joined<["-"], "stats-file=">,
 def fdump_record_layouts : Flag<["-"], "fdump-record-layouts">,
   HelpText<"Dump record layout information">;
 def fdump_record_layouts_simple : Flag<["-"], "fdump-record-layouts-simple">,
-  HelpText<"Dump record layout information in a simple form used for testing">,
-  MarshallingInfoFlag<"LangOpts->DumpRecordLayoutsSimple">;
+  HelpText<"Dump record layout information in a simple form used for testing">;
 def fix_what_you_can : Flag<["-"], "fix-what-you-can">,
   HelpText<"Apply fix-it advice even in the presence of unfixable errors">,
   MarshallingInfoFlag<"FrontendOpts.FixWhatYouCan">;
@@ -5024,10 +4765,9 @@ def pch_through_hdrstop_use : Flag<["-"], "pch-through-hdrstop-use">,
   HelpText<"When using a PCH, skip tokens until after a #pragma hdrstop.">;
 def fno_pch_timestamp : Flag<["-"], "fno-pch-timestamp">,
   HelpText<"Disable inclusion of timestamp in precompiled headers">,
-  MarshallingInfoNegativeFlag<"FrontendOpts.IncludeTimestamps">;
+  MarshallingInfoFlag<"FrontendOpts.IncludeTimestamps", "true">, IsNegative;
 def building_pch_with_obj : Flag<["-"], "building-pch-with-obj">,
-  HelpText<"This compilation is part of building a PCH with corresponding object file.">,
-  MarshallingInfoFlag<"LangOpts->BuildingPCHWithObjectFile">;
+  HelpText<"This compilation is part of building a PCH with corresponding object file.">;
 
 def aligned_alloc_unavailable : Flag<["-"], "faligned-alloc-unavailable">,
   HelpText<"Aligned allocation/deallocation functions are unavailable">;
@@ -5042,29 +4782,23 @@ def version : Flag<["-"], "version">,
   HelpText<"Print the compiler version">,
   MarshallingInfoFlag<"FrontendOpts.ShowVersion">;
 def main_file_name : Separate<["-"], "main-file-name">,
-  HelpText<"Main file name to use for debug info and source if missing">,
-  MarshallingInfoString<"CodeGenOpts.MainFileName">;
+  HelpText<"Main file name to use for debug info and source if missing">;
 def split_dwarf_output : Separate<["-"], "split-dwarf-output">,
-  HelpText<"File name to use for split dwarf debug info output">,
-  MarshallingInfoString<"CodeGenOpts.SplitDwarfOutput">;
+  HelpText<"File name to use for split dwarf debug info output">;
 
 }
 
 def fblocks_runtime_optional : Flag<["-"], "fblocks-runtime-optional">,
-  HelpText<"Weakly link in the blocks runtime">,
-  MarshallingInfoFlag<"LangOpts->BlocksRuntimeOptional">;
+  HelpText<"Weakly link in the blocks runtime">;
 def fexternc_nounwind : Flag<["-"], "fexternc-nounwind">,
-  HelpText<"Assume all functions with C linkage do not unwind">,
-  MarshallingInfoFlag<"LangOpts->ExternCNoUnwind">;
+  HelpText<"Assume all functions with C linkage do not unwind">;
 def split_dwarf_file : Separate<["-"], "split-dwarf-file">,
-  HelpText<"Name of the split dwarf debug info file to encode in the object file">,
-  MarshallingInfoString<"CodeGenOpts.SplitDwarfFile">;
+  HelpText<"Name of the split dwarf debug info file to encode in the object file">;
 def fno_wchar : Flag<["-"], "fno-wchar">,
   HelpText<"Disable C++ builtin type wchar_t">;
 def fconstant_string_class : Separate<["-"], "fconstant-string-class">,
   MetaVarName<"<class name>">,
-  HelpText<"Specify the class to use for constant Objective-C string objects.">,
-  MarshallingInfoString<"LangOpts->ObjCConstantStringClass">;
+  HelpText<"Specify the class to use for constant Objective-C string objects.">;
 def fobjc_arc_cxxlib_EQ : Joined<["-"], "fobjc-arc-cxxlib=">,
   HelpText<"Objective-C++ Automatic Reference Counting standard library kind">, Values<"libc++,libstdc++,none">,
   NormalizedValues<["ARCXX_libcxx", "ARCXX_libstdcxx", "ARCXX_nolib"]>,
@@ -5072,23 +4806,17 @@ def fobjc_arc_cxxlib_EQ : Joined<["-"], "fobjc-arc-cxxlib=">,
 def fobjc_runtime_has_weak : Flag<["-"], "fobjc-runtime-has-weak">,
   HelpText<"The target Objective-C runtime supports ARC weak operations">;
 def fobjc_dispatch_method_EQ : Joined<["-"], "fobjc-dispatch-method=">,
-  HelpText<"Objective-C dispatch method to use">, Values<"legacy,non-legacy,mixed">,
-  NormalizedValuesScope<"CodeGenOptions">, NormalizedValues<["Legacy", "NonLegacy", "Mixed"]>,
-  MarshallingInfoString<"CodeGenOpts.ObjCDispatchMethod", "Legacy">, AutoNormalizeEnum;
+  HelpText<"Objective-C dispatch method to use">, Values<"legacy,non-legacy,mixed">;
 def disable_objc_default_synthesize_properties : Flag<["-"], "disable-objc-default-synthesize-properties">,
-  HelpText<"disable the default synthesis of Objective-C properties">,
-  MarshallingInfoNegativeFlag<"LangOpts->ObjCDefaultSynthProperties">;
+  HelpText<"disable the default synthesis of Objective-C properties">;
 def fencode_extended_block_signature : Flag<["-"], "fencode-extended-block-signature">,
-  HelpText<"enable extended encoding of block type signature">,
-  MarshallingInfoFlag<"LangOpts->EncodeExtendedBlockSig">;
+  HelpText<"enable extended encoding of block type signature">;
 def function_alignment : Separate<["-"], "function-alignment">,
-    HelpText<"default alignment for functions">,
-    MarshallingInfoStringInt<"LangOpts->FunctionAlignment">;
+    HelpText<"default alignment for functions">;
 def pic_level : Separate<["-"], "pic-level">,
   HelpText<"Value for __PIC__">;
 def pic_is_pie : Flag<["-"], "pic-is-pie">,
-  HelpText<"File is for a position independent executable">,
-  MarshallingInfoFlag<"LangOpts->PIE">;
+  HelpText<"File is for a position independent executable">;
 def fno_validate_pch : Flag<["-"], "fno-validate-pch">,
   HelpText<"Disable validation of precompiled headers">,
   MarshallingInfoFlag<"PreprocessorOpts->DisablePCHValidation">;
@@ -5104,79 +4832,53 @@ def error_on_deserialized_pch_decl : Separate<["-"], "error-on-deserialized-decl
 def error_on_deserialized_pch_decl_EQ : Joined<["-"], "error-on-deserialized-decl=">,
   Alias<error_on_deserialized_pch_decl>;
 def static_define : Flag<["-"], "static-define">,
-  HelpText<"Should __STATIC__ be defined">,
-  MarshallingInfoFlag<"LangOpts->Static">;
+  HelpText<"Should __STATIC__ be defined">;
 def stack_protector : Separate<["-"], "stack-protector">,
-  HelpText<"Enable stack protectors">, Values<"0,1,2,3">,
-  NormalizedValuesScope<"LangOptions">,
-  NormalizedValues<["SSPOff", "SSPOn", "SSPStrong", "SSPReq"]>,
-  MarshallingInfoString<"LangOpts->StackProtector", "SSPOff">, AutoNormalizeEnum;
+  HelpText<"Enable stack protectors">;
 def stack_protector_buffer_size : Separate<["-"], "stack-protector-buffer-size">,
-  HelpText<"Lower bound for a buffer to be considered for stack protection">,
-  MarshallingInfoStringInt<"CodeGenOpts.SSPBufferSize", "8">;
-// FIXME: diagnose if target does not support protected visibility
-// Good place for this is CompilerInvocation::fixupInvocation. Do the same for parseVisibility.
+  HelpText<"Lower bound for a buffer to be considered for stack protection">;
 def fvisibility : Separate<["-"], "fvisibility">,
-  HelpText<"Default type and symbol visibility">, Values<"default,hidden,internal,protected">,
-  NormalizedValues<["DefaultVisibility", "HiddenVisibility", "HiddenVisibility", "ProtectedVisibility"]>,
-  MarshallingInfoString<"LangOpts->ValueVisibilityMode", "DefaultVisibility">, AutoNormalizeEnum;
+  HelpText<"Default type and symbol visibility">;
 def ftype_visibility : Separate<["-"], "ftype-visibility">,
   HelpText<"Default type visibility">;
 def fapply_global_visibility_to_externs : Flag<["-"], "fapply-global-visibility-to-externs">,
-  HelpText<"Apply global symbol visibility to external declarations without an explicit visibility">,
-  MarshallingInfoFlag<"LangOpts->SetVisibilityForExternDecls">;
+  HelpText<"Apply global symbol visibility to external declarations without an explicit visibility">;
 def ftemplate_depth : Separate<["-"], "ftemplate-depth">,
-  HelpText<"Maximum depth of recursive template instantiation">,
-  MarshallingInfoStringInt<"LangOpts->InstantiationDepth", "1024">;
+  HelpText<"Maximum depth of recursive template instantiation">;
 def foperator_arrow_depth : Separate<["-"], "foperator-arrow-depth">,
-  HelpText<"Maximum number of 'operator->'s to call for a member access">,
-  MarshallingInfoStringInt<"LangOpts->ArrowDepth", "256">;
+  HelpText<"Maximum number of 'operator->'s to call for a member access">;
 def fconstexpr_depth : Separate<["-"], "fconstexpr-depth">,
-  HelpText<"Maximum depth of recursive constexpr function calls">,
-  MarshallingInfoStringInt<"LangOpts->ConstexprCallDepth", "512">;
+  HelpText<"Maximum depth of recursive constexpr function calls">;
 def fconstexpr_steps : Separate<["-"], "fconstexpr-steps">,
-  HelpText<"Maximum number of steps in constexpr function evaluation">,
-  MarshallingInfoStringInt<"LangOpts->ConstexprStepLimit", "1048576">;
+  HelpText<"Maximum number of steps in constexpr function evaluation">;
 def fbracket_depth : Separate<["-"], "fbracket-depth">,
-  HelpText<"Maximum nesting level for parentheses, brackets, and braces">,
-  MarshallingInfoStringInt<"LangOpts->BracketDepth", "256">;
-defm const_strings : BoolFOption<"const-strings",
-  "LangOpts->ConstStrings", DefaultsToFalse,
-  ChangedBy<PosFlag, [], "Use">, ResetBy<NegFlag, [], "Don't use">,
-  BothFlags<[], " a const qualified type for string literals in C and ObjC">>;
+  HelpText<"Maximum nesting level for parentheses, brackets, and braces">;
+def fconst_strings : Flag<["-"], "fconst-strings">,
+  HelpText<"Use a const qualified type for string literals in C and ObjC">;
+def fno_const_strings : Flag<["-"], "fno-const-strings">,
+  HelpText<"Don't use a const qualified type for string literals in C and ObjC">;
 def fno_bitfield_type_align : Flag<["-"], "fno-bitfield-type-align">,
-  HelpText<"Ignore bit-field types when aligning structures">,
-  MarshallingInfoFlag<"LangOpts->NoBitFieldTypeAlign">;
+  HelpText<"Ignore bit-field types when aligning structures">;
 def ffake_address_space_map : Flag<["-"], "ffake-address-space-map">,
-  HelpText<"Use a fake address space map; OpenCL testing purposes only">,
-  MarshallingInfoFlag<"LangOpts->FakeAddressSpaceMap">;
+  HelpText<"Use a fake address space map; OpenCL testing purposes only">;
 def faddress_space_map_mangling_EQ : Joined<["-"], "faddress-space-map-mangling=">, MetaVarName<"<yes|no|target>">,
-  HelpText<"Set the mode for address space map based mangling; OpenCL testing purposes only">,
-  Values<"target,no,yes">, NormalizedValuesScope<"LangOptions">,
-  NormalizedValues<["ASMM_Target", "ASMM_Off", "ASMM_On"]>,
-  MarshallingInfoString<"LangOpts->AddressSpaceMapMangling", "ASMM_Target">, AutoNormalizeEnum;
+  HelpText<"Set the mode for address space map based mangling; OpenCL testing purposes only">;
 def funknown_anytype : Flag<["-"], "funknown-anytype">,
-  HelpText<"Enable parser support for the __unknown_anytype type; for testing purposes only">,
-  MarshallingInfoFlag<"LangOpts->ParseUnknownAnytype">;
+  HelpText<"Enable parser support for the __unknown_anytype type; for testing purposes only">;
 def fdebugger_support : Flag<["-"], "fdebugger-support">,
-  HelpText<"Enable special debugger support behavior">,
-  MarshallingInfoFlag<"LangOpts->DebuggerSupport">;
+  HelpText<"Enable special debugger support behavior">;
 def fdebugger_cast_result_to_id : Flag<["-"], "fdebugger-cast-result-to-id">,
-  HelpText<"Enable casting unknown expression results to id">,
-  MarshallingInfoFlag<"LangOpts->DebuggerCastResultToId">;
+  HelpText<"Enable casting unknown expression results to id">;
 def fdebugger_objc_literal : Flag<["-"], "fdebugger-objc-literal">,
-  HelpText<"Enable special debugger support for Objective-C subscripting and literals">,
-  MarshallingInfoFlag<"LangOpts->DebuggerObjCLiteral">;
+  HelpText<"Enable special debugger support for Objective-C subscripting and literals">;
 def fdeprecated_macro : Flag<["-"], "fdeprecated-macro">,
   HelpText<"Defines the __DEPRECATED macro">;
 def fno_deprecated_macro : Flag<["-"], "fno-deprecated-macro">,
   HelpText<"Undefines the __DEPRECATED macro">;
 def fobjc_subscripting_legacy_runtime : Flag<["-"], "fobjc-subscripting-legacy-runtime">,
   HelpText<"Allow Objective-C array and dictionary subscripting in legacy runtime">;
-// TODO: Enforce values valid for MSVtorDispMode.
 def vtordisp_mode_EQ : Joined<["-"], "vtordisp-mode=">,
-  HelpText<"Control vtordisp placement on win32 targets">,
-  MarshallingInfoStringInt<"LangOpts->VtorDispMode", "1">;
+  HelpText<"Control vtordisp placement on win32 targets">;
 def fnative_half_type: Flag<["-"], "fnative-half-type">,
   HelpText<"Use the native half type for __fp16 instead of promoting to float">;
 def fnative_half_arguments_and_returns : Flag<["-"], "fnative-half-arguments-and-returns">,
@@ -5184,37 +4886,27 @@ def fnative_half_arguments_and_returns : Flag<["-"], "fnative-half-arguments-and
 def fallow_half_arguments_and_returns : Flag<["-"], "fallow-half-arguments-and-returns">,
   HelpText<"Allow function arguments and returns of type half">;
 def fdefault_calling_conv_EQ : Joined<["-"], "fdefault-calling-conv=">,
-  HelpText<"Set default calling convention">, Values<"cdecl,fastcall,stdcall,vectorcall,regcall">,
-  NormalizedValuesScope<"LangOptions">,
-  NormalizedValues<["DCC_CDecl", "DCC_FastCall", "DCC_StdCall", "DCC_VectorCall", "DCC_RegCall"]>,
-  MarshallingInfoString<"LangOpts->DefaultCallingConv", "DCC_None">, AutoNormalizeEnum;
+  HelpText<"Set default calling convention">, Values<"cdecl,fastcall,stdcall,vectorcall,regcall">;
 def finclude_default_header : Flag<["-"], "finclude-default-header">,
-  HelpText<"Include default header file for OpenCL">,
-  MarshallingInfoFlag<"LangOpts->IncludeDefaultHeader">;
+  HelpText<"Include default header file for OpenCL">;
 def fdeclare_opencl_builtins : Flag<["-"], "fdeclare-opencl-builtins">,
-  HelpText<"Add OpenCL builtin function declarations (experimental)">,
-  MarshallingInfoFlag<"LangOpts->DeclareOpenCLBuiltins">;
+  HelpText<"Add OpenCL builtin function declarations (experimental)">;
 def fdeclare_spirv_builtins : Flag<["-"], "fdeclare-spirv-builtins">,
   HelpText<"Add SPIR-V builtin function declarations (experimental)">;
 def fpreserve_vec3_type : Flag<["-"], "fpreserve-vec3-type">,
-  HelpText<"Preserve 3-component vector type">,
-  MarshallingInfoFlag<"CodeGenOpts.PreserveVec3Type">;
+  HelpText<"Preserve 3-component vector type">;
 def fwchar_type_EQ : Joined<["-"], "fwchar-type=">,
-  HelpText<"Select underlying type for wchar_t">, Values<"char,short,int">,
-  NormalizedValues<["1", "2", "4"]>,
-  MarshallingInfoString<"LangOpts->WCharSize", "0">, AutoNormalizeEnum;
-defm signed_wchar : BoolFOption<"signed-wchar",
-  "LangOpts->WCharIsSigned", DefaultsToTrue,
-  ChangedBy<NegFlag, [], "Use an unsigned">, ResetBy<PosFlag, [], "Use a signed">,
-  BothFlags<[], " type for wchar_t">>;
+  HelpText<"Select underlying type for wchar_t">, Values<"char,short,int">;
+def fsigned_wchar : Flag<["-"], "fsigned-wchar">,
+  HelpText<"Use a signed type for wchar_t">;
+def fno_signed_wchar : Flag<["-"], "fno-signed-wchar">,
+  HelpText<"Use an unsigned type for wchar_t">;
 def fcompatibility_qualified_id_block_param_type_checking : Flag<["-"], "fcompatibility-qualified-id-block-type-checking">,
   HelpText<"Allow using blocks with parameters of more specific type than "
-           "the type system guarantees when a parameter is qualified id">,
-  MarshallingInfoFlag<"LangOpts->CompatibilityQualifiedIdBlockParamTypeChecking">;
+           "the type system guarantees when a parameter is qualified id">;
 def fpass_by_value_is_noalias: Flag<["-"], "fpass-by-value-is-noalias">,
   HelpText<"Allows assuming by-value parameters do not alias any other value. "
-           "Has no effect on non-trivially-copyable classes in C++.">, Group<f_Group>,
-  MarshallingInfoFlag<"CodeGenOpts.PassByValueIsNoAlias">;
+           "Has no effect on non-trivially-copyable classes in C++.">, Group<f_Group>;
 
 // FIXME: Remove these entirely once functionality/tests have been excised.
 def fobjc_gc_only : Flag<["-"], "fobjc-gc-only">, Group<f_Group>,
@@ -5228,7 +4920,7 @@ def fobjc_gc : Flag<["-"], "fobjc-gc">, Group<f_Group>,
 
 def nostdsysteminc : Flag<["-"], "nostdsysteminc">,
   HelpText<"Disable standard system #include directories">,
-  MarshallingInfoNegativeFlag<"HeaderSearchOpts->UseStandardSystemIncludes">;
+  MarshallingInfoFlag<"HeaderSearchOpts->UseStandardSystemIncludes", "true">, IsNegative;
 def fdisable_module_hash : Flag<["-"], "fdisable-module-hash">,
   HelpText<"Disable the module hash">,
   MarshallingInfoFlag<"HeaderSearchOpts->DisableModuleHash">;
@@ -5290,17 +4982,13 @@ def cl_ext_EQ : CommaJoined<["-"], "cl-ext=">,
 //===----------------------------------------------------------------------===//
 
 def fcuda_is_device : Flag<["-"], "fcuda-is-device">,
-  HelpText<"Generate code for CUDA device">,
-  MarshallingInfoFlag<"LangOpts->CUDAIsDevice">;
+  HelpText<"Generate code for CUDA device">;
 def fcuda_include_gpubinary : Separate<["-"], "fcuda-include-gpubinary">,
-  HelpText<"Incorporate CUDA device-side binary into host object file.">,
-  MarshallingInfoString<"CodeGenOpts.CudaGpuBinaryFileName">;
+  HelpText<"Incorporate CUDA device-side binary into host object file.">;
 def fcuda_allow_variadic_functions : Flag<["-"], "fcuda-allow-variadic-functions">,
-  HelpText<"Allow variadic functions in CUDA device code.">,
-  MarshallingInfoFlag<"LangOpts->CUDAAllowVariadicFunctions">;
+  HelpText<"Allow variadic functions in CUDA device code.">;
 def fno_cuda_host_device_constexpr : Flag<["-"], "fno-cuda-host-device-constexpr">,
-  HelpText<"Don't treat unattributed constexpr functions as __host__ __device__.">,
-  MarshallingInfoNegativeFlag<"LangOpts->CUDAHostDeviceConstexpr">;
+  HelpText<"Don't treat unattributed constexpr functions as __host__ __device__.">;
 
 //===----------------------------------------------------------------------===//
 // OpenMP Options
diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h
index fd5c0e32c5c22..c6a9818a89406 100644
--- a/clang/include/clang/Format/Format.h
+++ b/clang/include/clang/Format/Format.h
@@ -56,7 +56,7 @@ struct FormatStyle {
   int AccessModifierOffset;
 
   /// Different styles for aligning after open brackets.
-  enum BracketAlignmentStyle {
+  enum BracketAlignmentStyle : unsigned char {
     /// Align parameters on the open bracket, e.g.:
     /// \code
     ///   someLongFunction(argument1,
@@ -131,7 +131,7 @@ struct FormatStyle {
   bool AlignConsecutiveDeclarations;
 
   /// Different styles for aligning escaped newlines.
-  enum EscapedNewlineAlignmentStyle {
+  enum EscapedNewlineAlignmentStyle : unsigned char {
     /// Don't align escaped newlines.
     /// \code
     ///   #define A \
@@ -165,7 +165,7 @@ struct FormatStyle {
   EscapedNewlineAlignmentStyle AlignEscapedNewlines;
 
   /// Different styles for aligning operands.
-  enum OperandAlignmentStyle {
+  enum OperandAlignmentStyle : unsigned char {
     /// Do not align operands of binary and ternary expressions.
     /// The wrapped lines are indented ``ContinuationIndentWidth`` spaces from
     /// the start of the line.
@@ -275,7 +275,7 @@ struct FormatStyle {
 
   /// Different styles for merging short blocks containing at most one
   /// statement.
-  enum ShortBlockStyle {
+  enum ShortBlockStyle : unsigned char {
     /// Never merge blocks into a single line.
     /// \code
     ///   while (true) {
@@ -320,7 +320,7 @@ struct FormatStyle {
 
   /// Different styles for merging short functions containing at most one
   /// statement.
-  enum ShortFunctionStyle {
+  enum ShortFunctionStyle : unsigned char {
     /// Never merge functions into a single line.
     SFS_None,
     /// Only merge functions defined inside a class. Same as "inline",
@@ -371,7 +371,7 @@ struct FormatStyle {
   ShortFunctionStyle AllowShortFunctionsOnASingleLine;
 
   /// Different styles for handling short if lines
-  enum ShortIfStyle {
+  enum ShortIfStyle : unsigned char {
     /// Never put short ifs on the same line.
     /// \code
     ///   if (a)
@@ -405,7 +405,7 @@ struct FormatStyle {
 
   /// Different styles for merging short lambdas containing at most one
   /// statement.
-  enum ShortLambdaStyle {
+  enum ShortLambdaStyle : unsigned char {
     /// Never merge lambdas into a single line.
     SLS_None,
     /// Only merge empty lambdas.
@@ -442,7 +442,7 @@ struct FormatStyle {
 
   /// Different ways to break after the function definition return type.
   /// This option is **deprecated** and is retained for backwards compatibility.
-  enum DefinitionReturnTypeBreakingStyle {
+  enum DefinitionReturnTypeBreakingStyle : unsigned char {
     /// Break after return type automatically.
     /// ``PenaltyReturnTypeOnItsOwnLine`` is taken into account.
     DRTBS_None,
@@ -454,7 +454,7 @@ struct FormatStyle {
 
   /// Different ways to break after the function definition or
   /// declaration return type.
-  enum ReturnTypeBreakingStyle {
+  enum ReturnTypeBreakingStyle : unsigned char {
     /// Break after return type automatically.
     /// ``PenaltyReturnTypeOnItsOwnLine`` is taken into account.
     /// \code
@@ -545,7 +545,7 @@ struct FormatStyle {
   bool AlwaysBreakBeforeMultilineStrings;
 
   /// Different ways to break after the template declaration.
-  enum BreakTemplateDeclarationsStyle {
+  enum BreakTemplateDeclarationsStyle : unsigned char {
     /// Do not force break before declaration.
     /// ``PenaltyBreakTemplateDeclaration`` is taken into account.
     /// \code
@@ -620,7 +620,7 @@ struct FormatStyle {
   bool BinPackArguments;
 
   /// The style of inserting trailing commas into container literals.
-  enum TrailingCommaStyle {
+  enum TrailingCommaStyle : unsigned char {
     /// Do not insert trailing commas.
     TCS_None,
     /// Insert trailing commas in container literals that were wrapped over
@@ -664,7 +664,7 @@ struct FormatStyle {
 
   /// The style of wrapping parameters on the same line (bin-packed) or
   /// on one line each.
-  enum BinPackStyle {
+  enum BinPackStyle : unsigned char {
     /// Automatically determine parameter bin-packing behavior.
     BPS_Auto,
     /// Always bin-pack parameters.
@@ -674,7 +674,7 @@ struct FormatStyle {
   };
 
   /// The style of breaking before or after binary operators.
-  enum BinaryOperatorStyle {
+  enum BinaryOperatorStyle : unsigned char {
     /// Break after operators.
     /// \code
     ///    LooooooooooongType loooooooooooooooooooooongVariable =
@@ -717,7 +717,7 @@ struct FormatStyle {
   BinaryOperatorStyle BreakBeforeBinaryOperators;
 
   /// Different ways to attach braces to their surrounding context.
-  enum BraceBreakingStyle {
+  enum BraceBreakingStyle : unsigned char {
     /// Always attach braces to surrounding context.
     /// \code
     ///   namespace N {
@@ -1151,7 +1151,7 @@ struct FormatStyle {
   BraceBreakingStyle BreakBeforeBraces;
 
   /// Different ways to wrap braces after control statements.
-  enum BraceWrappingAfterControlStatementStyle {
+  enum BraceWrappingAfterControlStatementStyle : unsigned char {
     /// Never wrap braces after a control statement.
     /// \code
     ///   if (foo()) {
@@ -1450,7 +1450,7 @@ struct FormatStyle {
   bool BreakBeforeTernaryOperators;
 
   /// Different ways to break initializers.
-  enum BreakConstructorInitializersStyle {
+  enum BreakConstructorInitializersStyle : unsigned char {
     /// Break constructor initializers before the colon and after the commas.
     /// \code
     ///    Constructor()
@@ -1517,7 +1517,7 @@ struct FormatStyle {
   std::string CommentPragmas;
 
   /// Different ways to break inheritance list.
-  enum BreakInheritanceListStyle {
+  enum BreakInheritanceListStyle : unsigned char {
     /// Break inheritance list before the colon and after the commas.
     /// \code
     ///    class Foo
@@ -1816,7 +1816,7 @@ struct FormatStyle {
   bool IndentPragmas;
 
   /// Options for indenting preprocessor directives.
-  enum PPDirectiveIndentStyle {
+  enum PPDirectiveIndentStyle : unsigned char {
     /// Does not indent any directives.
     /// \code
     ///    #if FOO
@@ -1850,7 +1850,7 @@ struct FormatStyle {
   PPDirectiveIndentStyle IndentPPDirectives;
 
   /// Indents extern blocks
-  enum IndentExternBlockStyle {
+  enum IndentExternBlockStyle : unsigned char {
     /// Backwards compatible with AfterExternBlock's indenting.
     /// \code
     ///    IndentExternBlock: AfterExternBlock
@@ -1967,7 +1967,7 @@ struct FormatStyle {
 
   /// Quotation styles for JavaScript strings. Does not affect template
   /// strings.
-  enum JavaScriptQuoteStyle {
+  enum JavaScriptQuoteStyle : unsigned char {
     /// Leave string quotes as they are.
     /// \code{.js}
     ///    string1 = "foo";
@@ -2022,7 +2022,7 @@ struct FormatStyle {
   /// When stored in a configuration file, specifies the language, that the
   /// configuration targets. When passed to the ``reformat()`` function, enables
   /// syntax features specific to the language.
-  enum LanguageKind {
+  enum LanguageKind : unsigned char {
     /// Do not use.
     LK_None,
     /// Should be used for C, C++.
@@ -2095,7 +2095,7 @@ struct FormatStyle {
   unsigned MaxEmptyLinesToKeep;
 
   /// Different ways to indent namespace contents.
-  enum NamespaceIndentationKind {
+  enum NamespaceIndentationKind : unsigned char {
     /// Don't indent in namespaces.
     /// \code
     ///    namespace out {
@@ -2234,7 +2234,7 @@ struct FormatStyle {
   unsigned PenaltyIndentedWhitespace;
 
   /// The ``&`` and ``*`` alignment style.
-  enum PointerAlignmentStyle {
+  enum PointerAlignmentStyle : unsigned char {
     /// Align pointer to the left.
     /// \code
     ///   int* a;
@@ -2339,7 +2339,7 @@ struct FormatStyle {
   bool SortIncludes;
 
   /// Position for Java Static imports.
-  enum SortJavaStaticImportOptions {
+  enum SortJavaStaticImportOptions : unsigned char {
     /// Static imports are placed before non-static imports.
     /// \code{.java}
     ///   import static org.example.function1;
@@ -2399,7 +2399,7 @@ struct FormatStyle {
   bool SpaceAfterTemplateKeyword;
 
   /// Different ways to put a space before opening parentheses.
-  enum SpaceAroundPointerQualifiersStyle {
+  enum SpaceAroundPointerQualifiersStyle : unsigned char {
     /// Don't ensure spaces around pointer qualifiers and use PointerAlignment
     /// instead.
     /// \code
@@ -2438,6 +2438,15 @@ struct FormatStyle {
   /// \endcode
   bool SpaceBeforeAssignmentOperators;
 
+  /// If ``false``, spaces will be removed before case colon.
+  /// \code
+  ///   true:                                   false
+  ///   switch (x) {                    vs.     switch (x) {
+  ///     case 1 : break;                         case 1: break;
+  ///   }                                       }
+  /// \endcode
+  bool SpaceBeforeCaseColon;
+
   /// If ``true``, a space will be inserted before a C++11 braced list
   /// used to initialize an object (after the preceding identifier or type).
   /// \code
@@ -2465,7 +2474,7 @@ struct FormatStyle {
   bool SpaceBeforeInheritanceColon;
 
   /// Different ways to put a space before opening parentheses.
-  enum SpaceBeforeParensOptions {
+  enum SpaceBeforeParensOptions : unsigned char {
     /// Never put a space before opening parentheses.
     /// \code
     ///    void f() {
@@ -2629,7 +2638,7 @@ struct FormatStyle {
   bool SpaceBeforeSquareBrackets;
 
   /// Styles for adding spacing around ``:`` in bitfield definitions.
-  enum BitFieldColonSpacingStyle {
+  enum BitFieldColonSpacingStyle : unsigned char {
     /// Add one space on each side of the ``:``
     /// \code
     ///   unsigned bf : 2;
@@ -2664,7 +2673,7 @@ struct FormatStyle {
   ///
   /// The correct way to spell a specific language version is e.g. ``c++11``.
   /// The historical aliases ``Cpp03`` and ``Cpp11`` are deprecated.
-  enum LanguageStandard {
+  enum LanguageStandard : unsigned char {
     /// Parse and format as C++03.
     /// ``Cpp03`` is a deprecated alias for ``c++03``
     LS_Cpp03, // c++03
@@ -2694,7 +2703,7 @@ struct FormatStyle {
   unsigned TabWidth;
 
   /// Different ways to use tab in formatting.
-  enum UseTabStyle {
+  enum UseTabStyle : unsigned char {
     /// Never use tab.
     UT_Never,
     /// Use tabs only for indentation.
@@ -2820,6 +2829,7 @@ struct FormatStyle {
            SpaceAfterLogicalNot == R.SpaceAfterLogicalNot &&
            SpaceAfterTemplateKeyword == R.SpaceAfterTemplateKeyword &&
            SpaceBeforeAssignmentOperators == R.SpaceBeforeAssignmentOperators &&
+           SpaceBeforeCaseColon == R.SpaceBeforeCaseColon &&
            SpaceBeforeCpp11BracedList == R.SpaceBeforeCpp11BracedList &&
            SpaceBeforeCtorInitializerColon ==
                R.SpaceBeforeCtorInitializerColon &&
@@ -2879,7 +2889,8 @@ struct FormatStyle {
 private:
   FormatStyleSet StyleSet;
 
-  friend std::error_code parseConfiguration(StringRef Text, FormatStyle *Style,
+  friend std::error_code parseConfiguration(llvm::MemoryBufferRef Config,
+                                            FormatStyle *Style,
                                             bool AllowUnknownOptions);
 };
 
@@ -2938,9 +2949,17 @@ bool getPredefinedStyle(StringRef Name, FormatStyle::LanguageKind Language,
 ///
 /// If AllowUnknownOptions is true, no errors are emitted if unknown
 /// format options are occured.
-std::error_code parseConfiguration(StringRef Text, FormatStyle *Style,
+std::error_code parseConfiguration(llvm::MemoryBufferRef Config,
+                                   FormatStyle *Style,
                                    bool AllowUnknownOptions = false);
 
+/// Like above but accepts an unnamed buffer.
+inline std::error_code parseConfiguration(StringRef Config, FormatStyle *Style,
+                                          bool AllowUnknownOptions = false) {
+  return parseConfiguration(llvm::MemoryBufferRef(Config, "YAML"), Style,
+                            AllowUnknownOptions);
+}
+
 /// Gets configuration in a YAML string.
 std::string configurationAsText(const FormatStyle &Style);
 
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index c74dcc1a7ce1d..faa6af40ebe87 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -3510,8 +3510,7 @@ class Sema final {
                                               llvm::APSInt &Value, CCEKind CCE);
   ExprResult CheckConvertedConstantExpression(Expr *From, QualType T,
                                               APValue &Value, CCEKind CCE,
-                                              NamedDecl *Dest = nullptr,
-                                              bool *ValueDependent = nullptr);
+                                              NamedDecl *Dest = nullptr);
 
   /// Abstract base class used to perform a contextual implicit
   /// conversion from an expression to any type passing a filter.
@@ -7790,8 +7789,8 @@ class Sema final {
                                           QualType ParamType,
                                           SourceLocation Loc);
   ExprResult
-  BuildExpressionFromNonTypeTemplateArgument(const TemplateArgument &Arg,
-                                             SourceLocation Loc);
+  BuildExpressionFromIntegralTemplateArgument(const TemplateArgument &Arg,
+                                              SourceLocation Loc);
 
   /// Enumeration describing how template parameter lists are compared
   /// for equality.
diff --git a/clang/include/clang/Serialization/ASTRecordWriter.h b/clang/include/clang/Serialization/ASTRecordWriter.h
index ff654f417dda9..e362463b23096 100644
--- a/clang/include/clang/Serialization/ASTRecordWriter.h
+++ b/clang/include/clang/Serialization/ASTRecordWriter.h
@@ -166,7 +166,6 @@ class ASTRecordWriter
 
   /// Emit an APvalue.
   void AddAPValue(const APValue &Value);
-  void writeAPValue(const APValue &Value) { AddAPValue(Value); }
 
   /// Emit a reference to an identifier.
   void AddIdentifierRef(const IdentifierInfo *II) {
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index f6e8d93d9b827..98e042ec7c198 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -5395,10 +5395,10 @@ QualType ASTContext::getDecltypeType(Expr *e, QualType UnderlyingType) const {
   DecltypeType *dt;
 
   // C++11 [temp.type]p2:
-  //   If an expression e is type-dependent, decltype(e) denotes a unique
-  //   dependent type. Two such decltype-specifiers refer to the same type only
-  //   if their expressions are equivalent (14.5.6.1).
-  if (e->isTypeDependent()) {
+  //   If an expression e involves a template parameter, decltype(e) denotes a
+  //   unique dependent type. Two such decltype-specifiers refer to the same
+  //   type only if their expressions are equivalent (14.5.6.1).
+  if (e->isInstantiationDependent()) {
     llvm::FoldingSetNodeID ID;
     DependentDecltypeType::Profile(ID, *this, e);
 
@@ -5953,11 +5953,6 @@ ASTContext::getCanonicalTemplateArgument(const TemplateArgument &Arg) const {
     case TemplateArgument::Integral:
       return TemplateArgument(Arg, getCanonicalType(Arg.getIntegralType()));
 
-    case TemplateArgument::UncommonValue:
-      return TemplateArgument(*this,
-                              getCanonicalType(Arg.getUncommonValueType()),
-                              Arg.getAsUncommonValue());
-
     case TemplateArgument::Type:
       return TemplateArgument(getCanonicalType(Arg.getAsType()));
 
diff --git a/clang/lib/AST/ASTImporter.cpp b/clang/lib/AST/ASTImporter.cpp
index ddfc654481e4e..0e7c3f5ca4067 100644
--- a/clang/lib/AST/ASTImporter.cpp
+++ b/clang/lib/AST/ASTImporter.cpp
@@ -808,17 +808,6 @@ ASTNodeImporter::import(const TemplateArgument &From) {
     return TemplateArgument(*ToTypeOrErr, /*isNullPtr*/true);
   }
 
-  case TemplateArgument::UncommonValue: {
-    ExpectedType ToTypeOrErr = import(From.getUncommonValueType());
-    if (!ToTypeOrErr)
-      return ToTypeOrErr.takeError();
-    Expected<APValue> ToValueOrErr = import(From.getAsUncommonValue());
-    if (!ToValueOrErr)
-      return ToValueOrErr.takeError();
-    return TemplateArgument(Importer.getToContext(), *ToTypeOrErr,
-                            *ToValueOrErr);
-  }
-
   case TemplateArgument::Template: {
     Expected<TemplateName> ToTemplateOrErr = import(From.getAsTemplate());
     if (!ToTemplateOrErr)
diff --git a/clang/lib/AST/ASTStructuralEquivalence.cpp b/clang/lib/AST/ASTStructuralEquivalence.cpp
index f7696bc7c9212..d004e443ae06a 100644
--- a/clang/lib/AST/ASTStructuralEquivalence.cpp
+++ b/clang/lib/AST/ASTStructuralEquivalence.cpp
@@ -565,10 +565,6 @@ static bool IsStructurallyEquivalent(StructuralEquivalenceContext &Context,
     return IsStructurallyEquivalent(Context, Arg1.getAsExpr(),
                                     Arg2.getAsExpr());
 
-  case TemplateArgument::UncommonValue:
-    // FIXME: Do we need to customize the comparison?
-    return Arg1.structurallyEquals(Arg2);
-
   case TemplateArgument::Pack:
     if (Arg1.pack_size() != Arg2.pack_size())
       return false;
diff --git a/clang/lib/AST/ComputeDependence.cpp b/clang/lib/AST/ComputeDependence.cpp
index 5262e3cbe233b..4026fdc76fd6f 100644
--- a/clang/lib/AST/ComputeDependence.cpp
+++ b/clang/lib/AST/ComputeDependence.cpp
@@ -64,7 +64,7 @@ ExprDependence clang::computeDependence(UnaryOperator *E,
       if (VD && VD->isTemplated()) {
         auto *VarD = dyn_cast<VarDecl>(VD);
         if (!VarD || !VarD->hasLocalStorage())
-          Dep |= ExprDependence::ValueInstantiation;
+          Dep |= ExprDependence::Value;
       }
     }
   }
@@ -443,21 +443,12 @@ ExprDependence clang::computeDependence(DeclRefExpr *E, const ASTContext &Ctx) {
   if (auto *FirstArg = E->getTemplateArgs()) {
     unsigned NumArgs = E->getNumTemplateArgs();
     for (auto *Arg = FirstArg, *End = FirstArg + NumArgs; Arg < End; ++Arg)
-      Deps |= toExprDependence(Arg->getArgument().getDependence() &
-                               ~TemplateArgumentDependence::Dependent);
+      Deps |= toExprDependence(Arg->getArgument().getDependence());
   }
 
   auto *Decl = E->getDecl();
-  auto *Found = E->getFoundDecl();
   auto Type = E->getType();
 
-  // FIXME: For a ParmVarDecl referenced in a function signature, we don't know
-  // its dependence yet!
-  if (!isa<ParmVarDecl>(Decl)) {
-    if (Decl->getDeclContext()->isDependentContext() ||
-        (Found && Found->getDeclContext()->isDependentContext()))
-      Deps |= ExprDependence::Instantiation;
-  }
   if (Decl->isParameterPack())
     Deps |= ExprDependence::UnexpandedPack;
   Deps |= toExprDependence(Type->getDependence()) & ExprDependence::Error;
diff --git a/clang/lib/AST/Decl.cpp b/clang/lib/AST/Decl.cpp
index 62ecefd02dc6f..7e24845816186 100644
--- a/clang/lib/AST/Decl.cpp
+++ b/clang/lib/AST/Decl.cpp
@@ -342,10 +342,6 @@ LinkageComputer::getLVForTemplateArgumentList(ArrayRef<TemplateArgument> Args,
       LV.merge(getTypeLinkageAndVisibility(Arg.getNullPtrType()));
       continue;
 
-    case TemplateArgument::UncommonValue:
-      LV.merge(getLVForValue(Arg.getAsUncommonValue(), computation));
-      continue;
-
     case TemplateArgument::Template:
     case TemplateArgument::TemplateExpansion:
       if (TemplateDecl *Template =
@@ -2746,6 +2742,17 @@ SourceRange ParmVarDecl::getSourceRange() const {
   return DeclaratorDecl::getSourceRange();
 }
 
+bool ParmVarDecl::isDestroyedInCallee() const {
+  if (hasAttr<NSConsumedAttr>())
+    return true;
+
+  auto *RT = getType()->getAs<RecordType>();
+  if (RT && RT->getDecl()->isParamDestroyedInCallee())
+    return true;
+
+  return false;
+}
+
 Expr *ParmVarDecl::getDefaultArg() {
   assert(!hasUnparsedDefaultArg() && "Default argument is not yet parsed!");
   assert(!hasUninstantiatedDefaultArg() &&
diff --git a/clang/lib/AST/Expr.cpp b/clang/lib/AST/Expr.cpp
index e6288139c7a30..d125750cd02b9 100644
--- a/clang/lib/AST/Expr.cpp
+++ b/clang/lib/AST/Expr.cpp
@@ -416,9 +416,12 @@ DeclRefExpr::DeclRefExpr(const ASTContext &Ctx,
       RefersToEnclosingVariableOrCapture;
   DeclRefExprBits.NonOdrUseReason = NOUR;
   if (TemplateArgs) {
+    auto Deps = TemplateArgumentDependence::None;
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
-        TemplateKWLoc, *TemplateArgs,
-        getTrailingObjects<TemplateArgumentLoc>());
+        TemplateKWLoc, *TemplateArgs, getTrailingObjects<TemplateArgumentLoc>(),
+        Deps);
+    assert(!(Deps & TemplateArgumentDependence::Dependent) &&
+           "built a DeclRefExpr with dependent template args");
   } else if (TemplateKWLoc.isValid()) {
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc);
@@ -1594,8 +1597,16 @@ MemberExpr *MemberExpr::Create(
   MemberExpr *E = new (Mem) MemberExpr(Base, IsArrow, OperatorLoc, MemberDecl,
                                        NameInfo, T, VK, OK, NOUR);
 
-  // FIXME: Move this into the constructor.
+  // FIXME: remove remaining dependence computation to computeDependence().
+  auto Deps = E->getDependence();
   if (HasQualOrFound) {
+    // FIXME: Wrong. We should be looking at the member declaration we found.
+    if (QualifierLoc && QualifierLoc.getNestedNameSpecifier()->isDependent())
+      Deps |= ExprDependence::TypeValueInstantiation;
+    else if (QualifierLoc &&
+             QualifierLoc.getNestedNameSpecifier()->isInstantiationDependent())
+      Deps |= ExprDependence::Instantiation;
+
     E->MemberExprBits.HasQualifierOrFoundDecl = true;
 
     MemberExprNameQualifier *NQ =
@@ -1608,26 +1619,16 @@ MemberExpr *MemberExpr::Create(
       TemplateArgs || TemplateKWLoc.isValid();
 
   if (TemplateArgs) {
+    auto TemplateArgDeps = TemplateArgumentDependence::None;
     E->getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc, *TemplateArgs,
-        E->getTrailingObjects<TemplateArgumentLoc>());
+        E->getTrailingObjects<TemplateArgumentLoc>(), TemplateArgDeps);
+    if (TemplateArgDeps & TemplateArgumentDependence::Instantiation)
+      Deps |= ExprDependence::Instantiation;
   } else if (TemplateKWLoc.isValid()) {
     E->getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc);
   }
-
-  // FIXME: remove remaining dependence computation to computeDependence().
-  auto Deps = E->getDependence();
-  if (NestedNameSpecifier *Qual = E->getQualifier()) {
-    // FIXME: Wrong. We should be looking at the member declaration we found.
-    if (Qual->isDependent())
-      Deps |= ExprDependence::TypeValueInstantiation;
-    else if (Qual->isInstantiationDependent())
-      Deps |= ExprDependence::Instantiation;
-  }
-  if (TemplateSpecializationType::anyInstantiationDependentTemplateArguments(
-          E->template_arguments()))
-    Deps |= ExprDependence::Instantiation;
   E->setDependence(Deps);
 
   return E;
diff --git a/clang/lib/AST/ExprCXX.cpp b/clang/lib/AST/ExprCXX.cpp
index e1f658923519a..8dc9d4296e149 100644
--- a/clang/lib/AST/ExprCXX.cpp
+++ b/clang/lib/AST/ExprCXX.cpp
@@ -433,8 +433,9 @@ OverloadExpr::OverloadExpr(StmtClass SC, const ASTContext &Context,
   }
 
   if (TemplateArgs) {
+    auto Deps = TemplateArgumentDependence::None;
     getTrailingASTTemplateKWAndArgsInfo()->initializeFrom(
-        TemplateKWLoc, *TemplateArgs, getTrailingTemplateArgumentLoc());
+        TemplateKWLoc, *TemplateArgs, getTrailingTemplateArgumentLoc(), Deps);
   } else if (TemplateKWLoc.isValid()) {
     getTrailingASTTemplateKWAndArgsInfo()->initializeFrom(TemplateKWLoc);
   }
@@ -463,8 +464,9 @@ DependentScopeDeclRefExpr::DependentScopeDeclRefExpr(
   DependentScopeDeclRefExprBits.HasTemplateKWAndArgsInfo =
       (Args != nullptr) || TemplateKWLoc.isValid();
   if (Args) {
+    auto Deps = TemplateArgumentDependence::None;
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
-        TemplateKWLoc, *Args, getTrailingObjects<TemplateArgumentLoc>());
+        TemplateKWLoc, *Args, getTrailingObjects<TemplateArgumentLoc>(), Deps);
   } else if (TemplateKWLoc.isValid()) {
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc);
@@ -1374,9 +1376,10 @@ CXXDependentScopeMemberExpr::CXXDependentScopeMemberExpr(
   CXXDependentScopeMemberExprBits.OperatorLoc = OperatorLoc;
 
   if (TemplateArgs) {
+    auto Deps = TemplateArgumentDependence::None;
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
-        TemplateKWLoc, *TemplateArgs,
-        getTrailingObjects<TemplateArgumentLoc>());
+        TemplateKWLoc, *TemplateArgs, getTrailingObjects<TemplateArgumentLoc>(),
+        Deps);
   } else if (TemplateKWLoc.isValid()) {
     getTrailingObjects<ASTTemplateKWAndArgsInfo>()->initializeFrom(
         TemplateKWLoc);
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index 405dd411ef91c..7056e1217e972 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -1819,8 +1819,7 @@ static bool EvaluateFloat(const Expr *E, APFloat &Result, EvalInfo &Info);
 static bool EvaluateComplex(const Expr *E, ComplexValue &Res, EvalInfo &Info);
 static bool EvaluateAtomic(const Expr *E, const LValue *This, APValue &Result,
                            EvalInfo &Info);
-static bool EvaluateAsRValue(EvalInfo &Info, const Expr *E, APValue &Result,
-                             bool &Dependent);
+static bool EvaluateAsRValue(EvalInfo &Info, const Expr *E, APValue &Result);
 
 /// Evaluate an integer or fixed point expression into an APResult.
 static bool EvaluateFixedPointOrInteger(const Expr *E, APFixedPoint &Result,
@@ -2108,8 +2107,7 @@ static bool CheckEvaluationResult(CheckEvaluationResultKind CERK,
                                   QualType Type, const APValue &Value,
                                   ConstantExprKind Kind,
                                   SourceLocation SubobjectLoc,
-                                  CheckedTemporaries &CheckedTemps,
-                                  bool &Dependent);
+                                  CheckedTemporaries &CheckedTemps);
 
 /// Check that this reference or pointer core constant expression is a valid
 /// value for an address or reference constant expression. Return true if we
@@ -2117,8 +2115,7 @@ static bool CheckEvaluationResult(CheckEvaluationResultKind CERK,
 static bool CheckLValueConstantExpression(EvalInfo &Info, SourceLocation Loc,
                                           QualType Type, const LValue &LVal,
                                           ConstantExprKind Kind,
-                                          CheckedTemporaries &CheckedTemps,
-                                          bool &Dependent) {
+                                          CheckedTemporaries &CheckedTemps) {
   bool IsReferenceType = Type->isReferenceType();
 
   APValue::LValueBase Base = LVal.getLValueBase();
@@ -2203,8 +2200,6 @@ static bool CheckLValueConstantExpression(EvalInfo &Info, SourceLocation Loc,
   }
 
   if (BaseVD) {
-    Dependent |= BaseVD->isTemplated();
-
     if (const VarDecl *Var = dyn_cast<const VarDecl>(BaseVD)) {
       // Check if this is a thread-local variable.
       if (Var->getTLSKind())
@@ -2235,9 +2230,6 @@ static bool CheckLValueConstantExpression(EvalInfo &Info, SourceLocation Loc,
     }
   } else if (const auto *MTE =
                  dyn_cast_or_null<MaterializeTemporaryExpr>(BaseE)) {
-    if (auto *Extending = MTE->getExtendingDecl())
-      Dependent |= Extending->isTemplated();
-
     if (CheckedTemps.insert(MTE).second) {
       QualType TempType = getType(Base);
       if (TempType.isDestructedType()) {
@@ -2250,8 +2242,8 @@ static bool CheckLValueConstantExpression(EvalInfo &Info, SourceLocation Loc,
       APValue *V = MTE->getOrCreateValue(false);
       assert(V && "evasluation result refers to uninitialised temporary");
       if (!CheckEvaluationResult(CheckEvaluationResultKind::ConstantExpression,
-                                 Info, MTE->getExprLoc(), TempType, *V, Kind,
-                                 SourceLocation(), CheckedTemps, Dependent))
+                                 Info, MTE->getExprLoc(), TempType, *V,
+                                 Kind, SourceLocation(), CheckedTemps))
         return false;
     }
   }
@@ -2280,15 +2272,13 @@ static bool CheckLValueConstantExpression(EvalInfo &Info, SourceLocation Loc,
 
 /// Member pointers are constant expressions unless they point to a
 /// non-virtual dllimport member function.
-static bool
-CheckMemberPointerConstantExpression(EvalInfo &Info, SourceLocation Loc,
-                                     QualType Type, const APValue &Value,
-                                     ConstantExprKind Kind, bool &Dependent) {
+static bool CheckMemberPointerConstantExpression(EvalInfo &Info,
+                                                 SourceLocation Loc,
+                                                 QualType Type,
+                                                 const APValue &Value,
+                                                 ConstantExprKind Kind) {
   const ValueDecl *Member = Value.getMemberPointerDecl();
-  if (!Member)
-    return true;
-  Dependent |= Member->isTemplated();
-  const auto *FD = dyn_cast<CXXMethodDecl>(Member);
+  const auto *FD = dyn_cast_or_null<CXXMethodDecl>(Member);
   if (!FD)
     return true;
   if (FD->isConsteval()) {
@@ -2337,8 +2327,7 @@ static bool CheckEvaluationResult(CheckEvaluationResultKind CERK,
                                   QualType Type, const APValue &Value,
                                   ConstantExprKind Kind,
                                   SourceLocation SubobjectLoc,
-                                  CheckedTemporaries &CheckedTemps,
-                                  bool &Dependent) {
+                                  CheckedTemporaries &CheckedTemps) {
   if (!Value.hasValue()) {
     Info.FFDiag(DiagLoc, diag::note_constexpr_uninitialized)
       << true << Type;
@@ -2360,20 +2349,20 @@ static bool CheckEvaluationResult(CheckEvaluationResultKind CERK,
     for (unsigned I = 0, N = Value.getArrayInitializedElts(); I != N; ++I) {
       if (!CheckEvaluationResult(CERK, Info, DiagLoc, EltTy,
                                  Value.getArrayInitializedElt(I), Kind,
-                                 SubobjectLoc, CheckedTemps, Dependent))
+                                 SubobjectLoc, CheckedTemps))
         return false;
     }
     if (!Value.hasArrayFiller())
       return true;
     return CheckEvaluationResult(CERK, Info, DiagLoc, EltTy,
                                  Value.getArrayFiller(), Kind, SubobjectLoc,
-                                 CheckedTemps, Dependent);
+                                 CheckedTemps);
   }
   if (Value.isUnion() && Value.getUnionField()) {
     return CheckEvaluationResult(
         CERK, Info, DiagLoc, Value.getUnionField()->getType(),
         Value.getUnionValue(), Kind, Value.getUnionField()->getLocation(),
-        CheckedTemps, Dependent);
+        CheckedTemps);
   }
   if (Value.isStruct()) {
     RecordDecl *RD = Type->castAs<RecordType>()->getDecl();
@@ -2382,7 +2371,7 @@ static bool CheckEvaluationResult(CheckEvaluationResultKind CERK,
       for (const CXXBaseSpecifier &BS : CD->bases()) {
         if (!CheckEvaluationResult(CERK, Info, DiagLoc, BS.getType(),
                                    Value.getStructBase(BaseIndex), Kind,
-                                   BS.getBeginLoc(), CheckedTemps, Dependent))
+                                   BS.getBeginLoc(), CheckedTemps))
           return false;
         ++BaseIndex;
       }
@@ -2392,8 +2381,8 @@ static bool CheckEvaluationResult(CheckEvaluationResultKind CERK,
         continue;
 
       if (!CheckEvaluationResult(CERK, Info, DiagLoc, I->getType(),
-                                 Value.getStructField(I->getFieldIndex()), Kind,
-                                 I->getLocation(), CheckedTemps, Dependent))
+                                 Value.getStructField(I->getFieldIndex()),
+                                 Kind, I->getLocation(), CheckedTemps))
         return false;
     }
   }
@@ -2403,13 +2392,12 @@ static bool CheckEvaluationResult(CheckEvaluationResultKind CERK,
     LValue LVal;
     LVal.setFrom(Info.Ctx, Value);
     return CheckLValueConstantExpression(Info, DiagLoc, Type, LVal, Kind,
-                                         CheckedTemps, Dependent);
+                                         CheckedTemps);
   }
 
   if (Value.isMemberPointer() &&
       CERK == CheckEvaluationResultKind::ConstantExpression)
-    return CheckMemberPointerConstantExpression(Info, DiagLoc, Type, Value,
-                                                Kind, Dependent);
+    return CheckMemberPointerConstantExpression(Info, DiagLoc, Type, Value, Kind);
 
   // Everything else is fine.
   return true;
@@ -2420,7 +2408,7 @@ static bool CheckEvaluationResult(CheckEvaluationResultKind CERK,
 /// check that the expression is of literal type.
 static bool CheckConstantExpression(EvalInfo &Info, SourceLocation DiagLoc,
                                     QualType Type, const APValue &Value,
-                                    ConstantExprKind Kind, bool &Dependent) {
+                                    ConstantExprKind Kind) {
   // Nothing to check for a constant expression of type 'cv void'.
   if (Type->isVoidType())
     return true;
@@ -2428,18 +2416,17 @@ static bool CheckConstantExpression(EvalInfo &Info, SourceLocation DiagLoc,
   CheckedTemporaries CheckedTemps;
   return CheckEvaluationResult(CheckEvaluationResultKind::ConstantExpression,
                                Info, DiagLoc, Type, Value, Kind,
-                               SourceLocation(), CheckedTemps, Dependent);
+                               SourceLocation(), CheckedTemps);
 }
 
 /// Check that this evaluated value is fully-initialized and can be loaded by
 /// an lvalue-to-rvalue conversion.
 static bool CheckFullyInitialized(EvalInfo &Info, SourceLocation DiagLoc,
                                   QualType Type, const APValue &Value) {
-  bool Dependent = false;
   CheckedTemporaries CheckedTemps;
   return CheckEvaluationResult(
       CheckEvaluationResultKind::FullyInitialized, Info, DiagLoc, Type, Value,
-      ConstantExprKind::Normal, SourceLocation(), CheckedTemps, Dependent);
+      ConstantExprKind::Normal, SourceLocation(), CheckedTemps);
 }
 
 /// Enforce C++2a [expr.const]/4.17, which disallows new-expressions unless
@@ -11116,9 +11103,7 @@ static bool EvaluateBuiltinConstantP(EvalInfo &Info, const Expr *Arg) {
       ArgType->isAnyComplexType() || ArgType->isPointerType() ||
       ArgType->isNullPtrType()) {
     APValue V;
-    bool Dependent = false;
-    if (!::EvaluateAsRValue(Info, Arg, V, Dependent) ||
-        Info.EvalStatus.HasSideEffects) {
+    if (!::EvaluateAsRValue(Info, Arg, V) || Info.EvalStatus.HasSideEffects) {
       Fold.keepDiagnostics();
       return false;
     }
@@ -11420,8 +11405,7 @@ static bool tryEvaluateBuiltinObjectSize(const Expr *E, unsigned Type,
       // It's possible for us to be given GLValues if we're called via
       // Expr::tryEvaluateObjectSize.
       APValue RVal;
-      bool Dependent = false;
-      if (!EvaluateAsRValue(Info, E, RVal, Dependent))
+      if (!EvaluateAsRValue(Info, E, RVal))
         return false;
       LVal.setFrom(Info.Ctx, RVal);
     } else if (!EvaluatePointer(ignorePointerCastsAndParens(E), LVal, Info,
@@ -12850,9 +12834,8 @@ bool RecordExprEvaluator::VisitBinCmp(const BinaryOperator *E) {
     LV.set(VD);
     if (!handleLValueToRValueConversion(Info, E, E->getType(), LV, Result))
       return false;
-    bool Dependent = false;
     return CheckConstantExpression(Info, E->getExprLoc(), E->getType(), Result,
-                                   ConstantExprKind::Normal, Dependent);
+                                   ConstantExprKind::Normal);
   };
   return EvaluateComparisonBinaryOperator(Info, E, OnSuccess, [&]() {
     return ExprEvaluatorBaseTy::VisitBinCmp(E);
@@ -14616,8 +14599,7 @@ static bool EvaluateInPlace(APValue &Result, EvalInfo &Info, const LValue &This,
 
 /// EvaluateAsRValue - Try to evaluate this expression, performing an implicit
 /// lvalue-to-rvalue cast if it is an lvalue.
-static bool EvaluateAsRValue(EvalInfo &Info, const Expr *E, APValue &Result,
-                             bool &Dependent) {
+static bool EvaluateAsRValue(EvalInfo &Info, const Expr *E, APValue &Result) {
   assert(!E->isValueDependent());
   if (Info.EnableNewConstInterp) {
     if (!Info.Ctx.getInterpContext().evaluateAsRValue(Info, E, Result))
@@ -14642,7 +14624,7 @@ static bool EvaluateAsRValue(EvalInfo &Info, const Expr *E, APValue &Result,
 
   // Check this core constant expression is a constant expression.
   return CheckConstantExpression(Info, E->getExprLoc(), E->getType(), Result,
-                                 ConstantExprKind::Normal, Dependent) &&
+                                 ConstantExprKind::Normal) &&
          CheckMemoryLeaks(Info);
 }
 
@@ -14688,7 +14670,7 @@ static bool EvaluateAsRValue(const Expr *E, Expr::EvalResult &Result,
   if (FastEvaluateAsRValue(E, Result, Ctx, IsConst))
     return IsConst;
 
-  return EvaluateAsRValue(Info, E, Result.Val, Result.Dependent);
+  return EvaluateAsRValue(Info, E, Result.Val);
 }
 
 static bool EvaluateAsInt(const Expr *E, Expr::EvalResult &ExprResult,
@@ -14798,9 +14780,9 @@ bool Expr::EvaluateAsLValue(EvalResult &Result, const ASTContext &Ctx,
   CheckedTemporaries CheckedTemps;
   if (!EvaluateLValue(this, LV, Info) || !Info.discardCleanups() ||
       Result.HasSideEffects ||
-      !CheckLValueConstantExpression(
-          Info, getExprLoc(), Ctx.getLValueReferenceType(getType()), LV,
-          ConstantExprKind::Normal, CheckedTemps, Result.Dependent))
+      !CheckLValueConstantExpression(Info, getExprLoc(),
+                                     Ctx.getLValueReferenceType(getType()), LV,
+                                     ConstantExprKind::Normal, CheckedTemps))
     return false;
 
   LV.moveInto(Result.Val);
@@ -14859,7 +14841,7 @@ bool Expr::EvaluateAsConstantExpr(EvalResult &Result, const ASTContext &Ctx,
     llvm_unreachable("Unhandled cleanup; missing full expression marker?");
 
   if (!CheckConstantExpression(Info, getExprLoc(), getStorageType(Ctx, this),
-                               Result.Val, Kind, Result.Dependent))
+                               Result.Val, Kind))
     return false;
   if (!CheckMemoryLeaks(Info))
     return false;
@@ -14923,9 +14905,8 @@ bool Expr::EvaluateAsInitializer(APValue &Value, const ASTContext &Ctx,
     if (!Info.discardCleanups())
       llvm_unreachable("Unhandled cleanup; missing full expression marker?");
   }
-  bool Dependent = false;
   return CheckConstantExpression(Info, DeclLoc, DeclTy, Value,
-                                 ConstantExprKind::Normal, Dependent) &&
+                                 ConstantExprKind::Normal) &&
          CheckMemoryLeaks(Info);
 }
 
@@ -14992,7 +14973,7 @@ APSInt Expr::EvaluateKnownConstIntCheckOverflow(
   Info.InConstantContext = true;
   Info.CheckingForUndefinedBehavior = true;
 
-  bool Result = ::EvaluateAsRValue(this, EVResult, Ctx, Info);
+  bool Result = ::EvaluateAsRValue(Info, this, EVResult.Val);
   (void)Result;
   assert(Result && "Could not evaluate expression");
   assert(EVResult.Val.isInt() && "Expression did not evaluate to integer");
@@ -15004,10 +14985,13 @@ void Expr::EvaluateForOverflow(const ASTContext &Ctx) const {
   assert(!isValueDependent() &&
          "Expression evaluator can't be called on a dependent expression.");
 
+  bool IsConst;
   EvalResult EVResult;
-  EvalInfo Info(Ctx, EVResult, EvalInfo::EM_IgnoreSideEffects);
-  Info.CheckingForUndefinedBehavior = true;
-  (void)::EvaluateAsRValue(this, EVResult, Ctx, Info);
+  if (!FastEvaluateAsRValue(this, EVResult, Ctx, IsConst)) {
+    EvalInfo Info(Ctx, EVResult, EvalInfo::EM_IgnoreSideEffects);
+    Info.CheckingForUndefinedBehavior = true;
+    (void)::EvaluateAsRValue(Info, this, EVResult.Val);
+  }
 }
 
 bool Expr::EvalResult::isGlobalLValue() const {
@@ -15557,9 +15541,8 @@ bool Expr::isCXX11ConstantExpr(const ASTContext &Ctx, APValue *Result,
   EvalInfo Info(Ctx, Status, EvalInfo::EM_ConstantExpression);
 
   APValue Scratch;
-  bool Dependent = false;
   bool IsConstExpr =
-      ::EvaluateAsRValue(Info, this, Result ? *Result : Scratch, Dependent) &&
+      ::EvaluateAsRValue(Info, this, Result ? *Result : Scratch) &&
       // FIXME: We don't produce a diagnostic for this, but the callers that
       // call us on arbitrary full-expressions should generally not care.
       Info.discardCleanups() && !Status.HasSideEffects;
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index bed637625450a..45121fc48a343 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -2617,15 +2617,6 @@ void CXXNameMangler::mangleType(QualType T) {
         if (!TST->isTypeAlias())
           break;
 
-      // FIXME: We presumably shouldn't strip off ElaboratedTypes with
-      // instantation-dependent qualifiers. See
-      // https://github.com/itanium-cxx-abi/cxx-abi/issues/114.
-
-      // Don't desugar instantiation-dependent decltype / typeof types. We need
-      // to mangle the expression as written.
-      if (isa<DecltypeType, TypeOfType>(T))
-        break;
-
       QualType Desugared
         = T.getSingleStepDesugaredType(Context.getASTContext());
       if (Desugared == T)
@@ -4126,28 +4117,10 @@ void CXXNameMangler::mangleExpression(const Expr *E, unsigned Arity) {
     mangleExpression(cast<CXXStdInitializerListExpr>(E)->getSubExpr(), Arity);
     break;
 
-  case Expr::SubstNonTypeTemplateParmExprClass: {
-    // Mangle a substituted parameter the same way we mangle the template
-    // argument.
-    // As proposed in https://github.com/itanium-cxx-abi/cxx-abi/issues/111.
-    auto *SNTTPE = cast<SubstNonTypeTemplateParmExpr>(E);
-    if (auto *CE = dyn_cast<ConstantExpr>(SNTTPE->getReplacement())) {
-      // Pull out the constant value and mangle it as a template argument.
-      QualType ParamType = SNTTPE->getParameterType(Context.getASTContext());
-      if (CE->hasAPValueResult())
-        mangleValueInTemplateArg(ParamType, CE->getResultAsAPValue(), false,
-                                 /*NeedExactType=*/true);
-      else
-        mangleValueInTemplateArg(ParamType, CE->getAPValueResult(), false,
-                                 /*NeedExactType=*/true);
-    } else {
-      // The remaining cases all happen to be substituted with expressions that
-      // mangle the same as a corresponding template argument anyway.
-      mangleExpression(cast<SubstNonTypeTemplateParmExpr>(E)->getReplacement(),
-                       Arity);
-    }
+  case Expr::SubstNonTypeTemplateParmExprClass:
+    mangleExpression(cast<SubstNonTypeTemplateParmExpr>(E)->getReplacement(),
+                     Arity);
     break;
-  }
 
   case Expr::UserDefinedLiteralClass:
     // We follow g++'s approach of mangling a UDL as a call to the literal
@@ -5104,10 +5077,6 @@ void CXXNameMangler::mangleTemplateArg(TemplateArgument A, bool NeedExactType) {
     mangleNullPointer(A.getNullPtrType());
     break;
   }
-  case TemplateArgument::UncommonValue:
-    mangleValueInTemplateArg(A.getUncommonValueType(), A.getAsUncommonValue(),
-                             /*TopLevel=*/true, NeedExactType);
-    break;
   case TemplateArgument::Pack: {
     //  <template-arg> ::= J <template-arg>* E
     Out << 'J';
@@ -5442,20 +5411,7 @@ void CXXNameMangler::mangleValueInTemplateArg(QualType T, const APValue &V,
       Out << "plcvPcad";
       Kind = Offset;
     } else {
-      // Clang 11 and before mangled an array subject to array-to-pointer decay
-      // as if it were the declaration itself.
-      bool IsArrayToPointerDecayMangledAsDecl = false;
-      if (TopLevel && Ctx.getLangOpts().getClangABICompat() <=
-                          LangOptions::ClangABI::Ver11) {
-        QualType BType = B.getType();
-        IsArrayToPointerDecayMangledAsDecl =
-            BType->isArrayType() && V.getLValuePath().size() == 1 &&
-            V.getLValuePath()[0].getAsArrayIndex() == 0 &&
-            Ctx.hasSimilarType(T, Ctx.getDecayedType(BType));
-      }
-
-      if ((!V.getLValuePath().empty() || V.isLValueOnePastTheEnd()) &&
-          !IsArrayToPointerDecayMangledAsDecl) {
+      if (!V.getLValuePath().empty() || V.isLValueOnePastTheEnd()) {
         NotPrimaryExpr();
         // A final conversion to the template parameter's type is usually
         // folded into the 'so' mangling, but we can't do that for 'void*'
diff --git a/clang/lib/AST/MicrosoftMangle.cpp b/clang/lib/AST/MicrosoftMangle.cpp
index 14b88666f51e9..c5f5165090925 100644
--- a/clang/lib/AST/MicrosoftMangle.cpp
+++ b/clang/lib/AST/MicrosoftMangle.cpp
@@ -1575,17 +1575,6 @@ void MicrosoftCXXNameMangler::mangleTemplateArg(const TemplateDecl *TD,
                          cast<NonTypeTemplateParmDecl>(Parm), T);
     break;
   }
-  case TemplateArgument::UncommonValue:
-    Out << "$";
-    if (cast<NonTypeTemplateParmDecl>(Parm)
-            ->getType()
-            ->getContainedDeducedType()) {
-      Out << "M";
-      mangleType(TA.getNonTypeTemplateArgumentType(), SourceRange(), QMM_Drop);
-    }
-    mangleTemplateArgValue(TA.getUncommonValueType(), TA.getAsUncommonValue(),
-                           /*WithScalarType=*/false);
-    break;
   case TemplateArgument::Expression:
     mangleExpression(TA.getAsExpr(), cast<NonTypeTemplateParmDecl>(Parm));
     break;
diff --git a/clang/lib/AST/ODRHash.cpp b/clang/lib/AST/ODRHash.cpp
index 92e3bc27fca07..735bcff8f1137 100644
--- a/clang/lib/AST/ODRHash.cpp
+++ b/clang/lib/AST/ODRHash.cpp
@@ -169,8 +169,6 @@ void ODRHash::AddTemplateArgument(TemplateArgument TA) {
       break;
     case TemplateArgument::NullPtr:
     case TemplateArgument::Integral:
-    case TemplateArgument::UncommonValue:
-      // FIXME: Include a representation of these arguments.
       break;
     case TemplateArgument::Template:
     case TemplateArgument::TemplateExpansion:
diff --git a/clang/lib/AST/StmtProfile.cpp b/clang/lib/AST/StmtProfile.cpp
index 569e3b06f3b20..de9de6ff463c6 100644
--- a/clang/lib/AST/StmtProfile.cpp
+++ b/clang/lib/AST/StmtProfile.cpp
@@ -2208,12 +2208,6 @@ void StmtProfiler::VisitTemplateArgument(const TemplateArgument &Arg) {
     Arg.getAsIntegral().Profile(ID);
     break;
 
-  case TemplateArgument::UncommonValue:
-    VisitType(Arg.getUncommonValueType());
-    // FIXME: Do we need to recursively decompose this ourselves?
-    Arg.getAsUncommonValue().Profile(ID);
-    break;
-
   case TemplateArgument::Expression:
     Visit(Arg.getAsExpr());
     break;
diff --git a/clang/lib/AST/TemplateBase.cpp b/clang/lib/AST/TemplateBase.cpp
index a746db315d858..b6af655deff04 100644
--- a/clang/lib/AST/TemplateBase.cpp
+++ b/clang/lib/AST/TemplateBase.cpp
@@ -84,8 +84,8 @@ static void printIntegral(const TemplateArgument &TemplArg,
 // TemplateArgument Implementation
 //===----------------------------------------------------------------------===//
 
-TemplateArgument::TemplateArgument(const ASTContext &Ctx,
-                                   const llvm::APSInt &Value, QualType Type) {
+TemplateArgument::TemplateArgument(ASTContext &Ctx, const llvm::APSInt &Value,
+                                   QualType Type) {
   Integer.Kind = Integral;
   // Copy the APSInt value into our decomposed form.
   Integer.BitWidth = Value.getBitWidth();
@@ -103,45 +103,6 @@ TemplateArgument::TemplateArgument(const ASTContext &Ctx,
   Integer.Type = Type.getAsOpaquePtr();
 }
 
-static const ValueDecl *getAsSimpleValueDeclRef(const ASTContext &Ctx,
-                                                QualType T, const APValue &V) {
-  // Pointers to members are relatively easy.
-  if (V.isMemberPointer() && V.getMemberPointerPath().empty())
-    return V.getMemberPointerDecl();
-
-  // We model class non-type template parameters as their template parameter
-  // object declaration.
-  if (V.isStruct() || V.isUnion())
-    return Ctx.getTemplateParamObjectDecl(T, V);
-
-  // Pointers and references with an empty path use the special 'Declaration'
-  // representation.
-  if (V.isLValue() && V.hasLValuePath() &&
-      V.getLValuePath().empty() && !V.isLValueOnePastTheEnd())
-    return V.getLValueBase().dyn_cast<const ValueDecl *>();
-
-  // Everything else uses the 'uncommon' representation.
-  return nullptr;
-}
-
-TemplateArgument::TemplateArgument(const ASTContext &Ctx, QualType Type,
-                                   const APValue &V) {
-  if (Type->isIntegralOrEnumerationType() && V.isInt())
-    *this = TemplateArgument(Ctx, V.getInt(), Type);
-  else if ((V.isLValue() && V.isNullPointer()) ||
-           (V.isMemberPointer() && !V.getMemberPointerDecl()))
-    *this = TemplateArgument(Type, /*isNullPtr=*/true);
-  else if (const ValueDecl *VD = getAsSimpleValueDeclRef(Ctx, Type, V))
-    // FIXME: The Declaration form should expose a const ValueDecl*.
-    *this = TemplateArgument(const_cast<ValueDecl*>(VD), Type);
-  else {
-    Value.Kind = UncommonValue;
-    Value.Value = new (Ctx) APValue(V);
-    Ctx.addDestruction(Value.Value);
-    Value.Type = Type.getAsOpaquePtr();
-  }
-}
-
 TemplateArgument
 TemplateArgument::CreatePackCopy(ASTContext &Context,
                                  ArrayRef<TemplateArgument> Args) {
@@ -170,18 +131,25 @@ TemplateArgumentDependence TemplateArgument::getDependence() const {
     return TemplateArgumentDependence::Dependent |
            TemplateArgumentDependence::Instantiation;
 
+  case Declaration: {
+    auto *DC = dyn_cast<DeclContext>(getAsDecl());
+    if (!DC)
+      DC = getAsDecl()->getDeclContext();
+    if (DC->isDependentContext())
+      Deps = TemplateArgumentDependence::Dependent |
+             TemplateArgumentDependence::Instantiation;
+    return Deps;
+  }
+
   case NullPtr:
   case Integral:
-  case Declaration:
-  case UncommonValue:
     return TemplateArgumentDependence::None;
 
   case Expression:
     Deps = toTemplateArgumentDependence(getAsExpr()->getDependence());
-    // Instantiation-dependent expression arguments are considered dependent
-    // until they're resolved to another form.
-    if (Deps & TemplateArgumentDependence::Instantiation)
-      Deps |= TemplateArgumentDependence::Dependent;
+    if (isa<PackExpansionExpr>(getAsExpr()))
+      Deps |= TemplateArgumentDependence::Dependent |
+              TemplateArgumentDependence::Instantiation;
     return Deps;
 
   case Pack:
@@ -205,7 +173,6 @@ bool TemplateArgument::isPackExpansion() const {
   case Null:
   case Declaration:
   case Integral:
-  case UncommonValue:
   case Pack:
   case Template:
   case NullPtr:
@@ -256,9 +223,6 @@ QualType TemplateArgument::getNonTypeTemplateArgumentType() const {
 
   case TemplateArgument::NullPtr:
     return getNullPtrType();
-
-  case TemplateArgument::UncommonValue:
-    return getUncommonValueType();
   }
 
   llvm_unreachable("Invalid TemplateArgument Kind!");
@@ -303,13 +267,8 @@ void TemplateArgument::Profile(llvm::FoldingSetNodeID &ID,
   }
 
   case Integral:
-    getIntegralType().Profile(ID);
     getAsIntegral().Profile(ID);
-    break;
-
-  case UncommonValue:
-    getUncommonValueType().Profile(ID);
-    getAsUncommonValue().Profile(ID);
+    getIntegralType().Profile(ID);
     break;
 
   case Expression:
@@ -345,16 +304,6 @@ bool TemplateArgument::structurallyEquals(const TemplateArgument &Other) const {
     return getIntegralType() == Other.getIntegralType() &&
            getAsIntegral() == Other.getAsIntegral();
 
-  case UncommonValue: {
-    if (getUncommonValueType() != Other.getUncommonValueType())
-      return false;
-
-    llvm::FoldingSetNodeID A, B;
-    getAsUncommonValue().Profile(A);
-    Other.getAsUncommonValue().Profile(B);
-    return A == B;
-  }
-
   case Pack:
     if (Args.NumArgs != Other.Args.NumArgs) return false;
     for (unsigned I = 0, E = Args.NumArgs; I != E; ++I)
@@ -381,7 +330,6 @@ TemplateArgument TemplateArgument::getPackExpansionPattern() const {
 
   case Declaration:
   case Integral:
-  case UncommonValue:
   case Pack:
   case Null:
   case Template:
@@ -421,10 +369,6 @@ void TemplateArgument::print(const PrintingPolicy &Policy,
     break;
   }
 
-  case UncommonValue:
-    getAsUncommonValue().printPretty(Out, Policy, getUncommonValueType());
-    break;
-
   case NullPtr:
     Out << "nullptr";
     break;
@@ -507,9 +451,6 @@ SourceRange TemplateArgumentLoc::getSourceRange() const {
   case TemplateArgument::Integral:
     return getSourceIntegralExpression()->getSourceRange();
 
-  case TemplateArgument::UncommonValue:
-    return getSourceUncommonValueExpression()->getSourceRange();
-
   case TemplateArgument::Pack:
   case TemplateArgument::Null:
     return SourceRange();
@@ -538,18 +479,6 @@ static const T &DiagTemplateArg(const T &DB, const TemplateArgument &Arg) {
   case TemplateArgument::Integral:
     return DB << Arg.getAsIntegral().toString(10);
 
-  case TemplateArgument::UncommonValue: {
-    // FIXME: We're guessing at LangOptions!
-    SmallString<32> Str;
-    llvm::raw_svector_ostream OS(Str);
-    LangOptions LangOpts;
-    LangOpts.CPlusPlus = true;
-    PrintingPolicy Policy(LangOpts);
-    Arg.getAsUncommonValue().printPretty(OS, Policy,
-                                         Arg.getUncommonValueType());
-    return DB << OS.str();
-  }
-
   case TemplateArgument::Template:
     return DB << Arg.getAsTemplate();
 
@@ -615,8 +544,8 @@ ASTTemplateArgumentListInfo::ASTTemplateArgumentListInfo(
   NumTemplateArgs = Info.size();
 
   TemplateArgumentLoc *ArgBuffer = getTrailingObjects<TemplateArgumentLoc>();
-  std::uninitialized_copy(Info.arguments().begin(), Info.arguments().end(),
-                          ArgBuffer);
+  for (unsigned i = 0; i != NumTemplateArgs; ++i)
+    new (&ArgBuffer[i]) TemplateArgumentLoc(Info[i]);
 }
 
 void ASTTemplateKWAndArgsInfo::initializeFrom(
@@ -626,8 +555,9 @@ void ASTTemplateKWAndArgsInfo::initializeFrom(
   LAngleLoc = Info.getLAngleLoc();
   RAngleLoc = Info.getRAngleLoc();
   NumTemplateArgs = Info.size();
-  std::uninitialized_copy(Info.arguments().begin(), Info.arguments().end(),
-                          OutArgArray);
+
+  for (unsigned i = 0; i != NumTemplateArgs; ++i)
+    new (&OutArgArray[i]) TemplateArgumentLoc(Info[i]);
 }
 
 void ASTTemplateKWAndArgsInfo::initializeFrom(SourceLocation TemplateKWLoc) {
@@ -638,6 +568,21 @@ void ASTTemplateKWAndArgsInfo::initializeFrom(SourceLocation TemplateKWLoc) {
   NumTemplateArgs = 0;
 }
 
+void ASTTemplateKWAndArgsInfo::initializeFrom(
+    SourceLocation TemplateKWLoc, const TemplateArgumentListInfo &Info,
+    TemplateArgumentLoc *OutArgArray, TemplateArgumentDependence &Deps) {
+  this->TemplateKWLoc = TemplateKWLoc;
+  LAngleLoc = Info.getLAngleLoc();
+  RAngleLoc = Info.getRAngleLoc();
+  NumTemplateArgs = Info.size();
+
+  for (unsigned i = 0; i != NumTemplateArgs; ++i) {
+    Deps |= Info[i].getArgument().getDependence();
+
+    new (&OutArgArray[i]) TemplateArgumentLoc(Info[i]);
+  }
+}
+
 void ASTTemplateKWAndArgsInfo::copyInto(const TemplateArgumentLoc *ArgArray,
                                         TemplateArgumentListInfo &Info) const {
   Info.setLAngleLoc(LAngleLoc);
diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index bd68501f14713..75cb2ae2455b8 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -125,7 +125,8 @@ ArrayType::ArrayType(TypeClass tc, QualType et, QualType can,
     //   template<int ...N> int arr[] = {N...};
     : Type(tc, can,
            et->getDependence() |
-               (sz ? toTypeDependence(sz->getDependence())
+               (sz ? toTypeDependence(
+                         turnValueToTypeDependence(sz->getDependence()))
                    : TypeDependence::None) |
                (tc == VariableArray ? TypeDependence::VariablyModified
                                     : TypeDependence::None) |
@@ -3401,8 +3402,9 @@ QualType MacroQualifiedType::getModifiedType() const {
 
 TypeOfExprType::TypeOfExprType(Expr *E, QualType can)
     : Type(TypeOfExpr, can,
-           typeToTypeDependence(E->getDependence(),
-                                E->getType()->getDependence())),
+           toTypeDependence(E->getDependence()) |
+               (E->getType()->getDependence() &
+                TypeDependence::VariablyModified)),
       TOExpr(E) {}
 
 bool TypeOfExprType::isSugared() const {
@@ -3422,12 +3424,18 @@ void DependentTypeOfExprType::Profile(llvm::FoldingSetNodeID &ID,
 }
 
 DecltypeType::DecltypeType(Expr *E, QualType underlyingType, QualType can)
+    // C++11 [temp.type]p2: "If an expression e involves a template parameter,
+    // decltype(e) denotes a unique dependent type." Hence a decltype type is
+    // type-dependent even if its expression is only instantiation-dependent.
     : Type(Decltype, can,
-           typeToTypeDependence(E->getDependence(),
-                                E->getType()->getDependence())),
+           toTypeDependence(E->getDependence()) |
+               (E->isInstantiationDependent() ? TypeDependence::Dependent
+                                              : TypeDependence::None) |
+               (E->getType()->getDependence() &
+                TypeDependence::VariablyModified)),
       E(E), UnderlyingType(underlyingType) {}
 
-bool DecltypeType::isSugared() const { return !E->isTypeDependent(); }
+bool DecltypeType::isSugared() const { return !E->isInstantiationDependent(); }
 
 QualType DecltypeType::desugar() const {
   if (isSugared())
diff --git a/clang/lib/AST/TypeLoc.cpp b/clang/lib/AST/TypeLoc.cpp
index 72d9d208bbc4c..ea15c5a0dbed8 100644
--- a/clang/lib/AST/TypeLoc.cpp
+++ b/clang/lib/AST/TypeLoc.cpp
@@ -567,7 +567,6 @@ void TemplateSpecializationTypeLoc::initializeArgLocs(ASTContext &Context,
     case TemplateArgument::Integral:
     case TemplateArgument::Declaration:
     case TemplateArgument::NullPtr:
-    case TemplateArgument::UncommonValue:
       ArgInfos[i] = TemplateArgumentLocInfo();
       break;
 
diff --git a/clang/lib/ASTMatchers/ASTMatchFinder.cpp b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
index cc95371445242..762885fa00527 100644
--- a/clang/lib/ASTMatchers/ASTMatchFinder.cpp
+++ b/clang/lib/ASTMatchers/ASTMatchFinder.cpp
@@ -463,6 +463,22 @@ class MatchASTVisitor : public RecursiveASTVisitor<MatchASTVisitor>,
   bool TraverseConstructorInitializer(CXXCtorInitializer *CtorInit);
   bool TraverseTemplateArgumentLoc(TemplateArgumentLoc TAL);
 
+  bool dataTraverseNode(Stmt *S, DataRecursionQueue *Queue) {
+    if (auto *RF = dyn_cast<CXXForRangeStmt>(S)) {
+      for (auto *SubStmt : RF->children()) {
+        if (SubStmt == RF->getInit() || SubStmt == RF->getLoopVarStmt() ||
+            SubStmt == RF->getRangeInit() || SubStmt == RF->getBody()) {
+          TraverseStmt(SubStmt, Queue);
+        } else {
+          ASTNodeNotSpelledInSourceScope RAII(this, true);
+          TraverseStmt(SubStmt, Queue);
+        }
+      }
+      return true;
+    }
+    return RecursiveASTVisitor<MatchASTVisitor>::dataTraverseNode(S, Queue);
+  }
+
   // Matches children or descendants of 'Node' with 'BaseMatcher'.
   bool memoizedMatchesRecursively(const DynTypedNode &Node, ASTContext &Ctx,
                                   const DynTypedMatcher &Matcher,
diff --git a/clang/lib/Basic/FileEntry.cpp b/clang/lib/Basic/FileEntry.cpp
index 2efdcbbd46aaa..5ee9bef9523ea 100644
--- a/clang/lib/Basic/FileEntry.cpp
+++ b/clang/lib/Basic/FileEntry.cpp
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "clang/Basic/FileEntry.h"
+#include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/VirtualFileSystem.h"
 
 using namespace clang;
diff --git a/clang/lib/Basic/FileManager.cpp b/clang/lib/Basic/FileManager.cpp
index c0d3685001eed..6e9d5d7fb4222 100644
--- a/clang/lib/Basic/FileManager.cpp
+++ b/clang/lib/Basic/FileManager.cpp
@@ -338,6 +338,25 @@ FileManager::getFileRef(StringRef Filename, bool openFile, bool CacheFailure) {
   return ReturnedRef;
 }
 
+llvm::Expected<FileEntryRef> FileManager::getSTDIN() {
+  // Only read stdin once.
+  if (STDIN)
+    return *STDIN;
+
+  std::unique_ptr<llvm::MemoryBuffer> Content;
+  if (auto ContentOrError = llvm::MemoryBuffer::getSTDIN())
+    Content = std::move(*ContentOrError);
+  else
+    return llvm::errorCodeToError(ContentOrError.getError());
+
+  STDIN = getVirtualFileRef(Content->getBufferIdentifier(),
+                            Content->getBufferSize(), 0);
+  FileEntry &FE = const_cast<FileEntry &>(STDIN->getFileEntry());
+  FE.Content = std::move(Content);
+  FE.IsNamedPipe = true;
+  return *STDIN;
+}
+
 const FileEntry *FileManager::getVirtualFile(StringRef Filename, off_t Size,
                                              time_t ModificationTime) {
   return &getVirtualFileRef(Filename, Size, ModificationTime).getFileEntry();
@@ -486,10 +505,14 @@ void FileManager::fillRealPathName(FileEntry *UFE, llvm::StringRef FileName) {
 llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>>
 FileManager::getBufferForFile(const FileEntry *Entry, bool isVolatile,
                               bool RequiresNullTerminator) {
+  // If the content is living on the file entry, return a reference to it.
+  if (Entry->Content)
+    return llvm::MemoryBuffer::getMemBuffer(Entry->Content->getMemBufferRef());
+
   uint64_t FileSize = Entry->getSize();
   // If there's a high enough chance that the file have changed since we
   // got its size, force a stat before opening it.
-  if (isVolatile)
+  if (isVolatile || Entry->isNamedPipe())
     FileSize = -1;
 
   StringRef Filename = Entry->getName();
diff --git a/clang/lib/Basic/SourceManager.cpp b/clang/lib/Basic/SourceManager.cpp
index b71b2be0cc412..56b233b517aa8 100644
--- a/clang/lib/Basic/SourceManager.cpp
+++ b/clang/lib/Basic/SourceManager.cpp
@@ -115,23 +115,6 @@ ContentCache::getBufferOrNone(DiagnosticsEngine &Diag, FileManager &FM,
   // return paths.
   IsBufferInvalid = true;
 
-  // Check that the file's size fits in an 'unsigned' (with room for a
-  // past-the-end value). This is deeply regrettable, but various parts of
-  // Clang (including elsewhere in this file!) use 'unsigned' to represent file
-  // offsets, line numbers, string literal lengths, and so on, and fail
-  // miserably on large source files.
-  if ((uint64_t)ContentsEntry->getSize() >=
-      std::numeric_limits<unsigned>::max()) {
-    if (Diag.isDiagnosticInFlight())
-      Diag.SetDelayedDiagnostic(diag::err_file_too_large,
-                                ContentsEntry->getName());
-    else
-      Diag.Report(Loc, diag::err_file_too_large)
-        << ContentsEntry->getName();
-
-    return None;
-  }
-
   auto BufferOrError = FM.getBufferForFile(ContentsEntry, IsFileVolatile);
 
   // If we were unable to open the file, then we are in an inconsistent
@@ -153,9 +136,31 @@ ContentCache::getBufferOrNone(DiagnosticsEngine &Diag, FileManager &FM,
 
   Buffer = std::move(*BufferOrError);
 
-  // Check that the file's size is the same as in the file entry (which may
+  // Check that the file's size fits in an 'unsigned' (with room for a
+  // past-the-end value). This is deeply regrettable, but various parts of
+  // Clang (including elsewhere in this file!) use 'unsigned' to represent file
+  // offsets, line numbers, string literal lengths, and so on, and fail
+  // miserably on large source files.
+  //
+  // Note: ContentsEntry could be a named pipe, in which case
+  // ContentsEntry::getSize() could have the wrong size. Use
+  // MemoryBuffer::getBufferSize() instead.
+  if (Buffer->getBufferSize() >= std::numeric_limits<unsigned>::max()) {
+    if (Diag.isDiagnosticInFlight())
+      Diag.SetDelayedDiagnostic(diag::err_file_too_large,
+                                ContentsEntry->getName());
+    else
+      Diag.Report(Loc, diag::err_file_too_large)
+        << ContentsEntry->getName();
+
+    return None;
+  }
+
+  // Unless this is a named pipe (in which case we can handle a mismatch),
+  // check that the file's size is the same as in the file entry (which may
   // have come from a stat cache).
-  if (Buffer->getBufferSize() != (size_t)ContentsEntry->getSize()) {
+  if (!ContentsEntry->isNamedPipe() &&
+      Buffer->getBufferSize() != (size_t)ContentsEntry->getSize()) {
     if (Diag.isDiagnosticInFlight())
       Diag.SetDelayedDiagnostic(diag::err_file_modified,
                                 ContentsEntry->getName());
@@ -409,6 +414,7 @@ ContentCache &SourceManager::getOrCreateContentCache(const FileEntry *FileEnt,
 
   Entry->IsFileVolatile = UserFilesAreVolatile && !isSystemFile;
   Entry->IsTransient = FilesAreTransient;
+  Entry->BufferOverridden |= FileEnt->isNamedPipe();
 
   return *Entry;
 }
@@ -541,6 +547,12 @@ FileID SourceManager::createFileID(FileEntryRef SourceFile,
                                    int LoadedID, unsigned LoadedOffset) {
   SrcMgr::ContentCache &IR = getOrCreateContentCache(&SourceFile.getFileEntry(),
                                                      isSystem(FileCharacter));
+
+  // If this is a named pipe, immediately load the buffer to ensure subsequent
+  // calls to ContentCache::getSize() are accurate.
+  if (IR.ContentsEntry->isNamedPipe())
+    (void)IR.getBufferOrNone(Diag, getFileManager(), SourceLocation());
+
   return createFileIDImpl(IR, SourceFile.getName(), IncludePos, FileCharacter,
                           LoadedID, LoadedOffset);
 }
diff --git a/clang/lib/CodeGen/CGCall.h b/clang/lib/CodeGen/CGCall.h
index 509ca43a97848..e3d9fec6d3634 100644
--- a/clang/lib/CodeGen/CGCall.h
+++ b/clang/lib/CodeGen/CGCall.h
@@ -110,7 +110,8 @@ class CGCallee {
   /// Construct a callee.  Call this constructor directly when this
   /// isn't a direct call.
   CGCallee(const CGCalleeInfo &abstractInfo, llvm::Value *functionPtr)
-      : KindOrFunctionPointer(SpecialKind(uintptr_t(functionPtr))) {
+      : KindOrFunctionPointer(
+            SpecialKind(reinterpret_cast<uintptr_t>(functionPtr))) {
     AbstractInfo = abstractInfo;
     assert(functionPtr && "configuring callee without function pointer");
     assert(functionPtr->getType()->isPointerTy());
@@ -186,7 +187,8 @@ class CGCallee {
   }
   void setFunctionPointer(llvm::Value *functionPtr) {
     assert(isOrdinary());
-    KindOrFunctionPointer = SpecialKind(uintptr_t(functionPtr));
+    KindOrFunctionPointer =
+        SpecialKind(reinterpret_cast<uintptr_t>(functionPtr));
   }
 
   bool isVirtual() const {
diff --git a/clang/lib/CodeGen/CGDebugInfo.cpp b/clang/lib/CodeGen/CGDebugInfo.cpp
index 3533758c8b31c..cad00f30c0cd6 100644
--- a/clang/lib/CodeGen/CGDebugInfo.cpp
+++ b/clang/lib/CodeGen/CGDebugInfo.cpp
@@ -1960,14 +1960,6 @@ CGDebugInfo::CollectTemplateParams(const TemplateParameterList *TPList,
       TemplateParams.push_back(DBuilder.createTemplateValueParameter(
           TheCU, Name, TTy, defaultParameter, V));
     } break;
-    case TemplateArgument::UncommonValue: {
-      QualType T = TA.getUncommonValueType();
-      llvm::DIType *TTy = getOrCreateType(T, Unit);
-      llvm::Constant *V = ConstantEmitter(CGM).emitAbstract(
-          SourceLocation(), TA.getAsUncommonValue(), T);
-      TemplateParams.push_back(DBuilder.createTemplateValueParameter(
-          TheCU, Name, TTy, defaultParameter, V));
-    } break;
     case TemplateArgument::Template:
       TemplateParams.push_back(DBuilder.createTemplateTemplateParameter(
           TheCU, Name, nullptr,
diff --git a/clang/lib/CodeGen/CGExprAgg.cpp b/clang/lib/CodeGen/CGExprAgg.cpp
index 60ea1b2af037f..a8bc1a2b93a88 100644
--- a/clang/lib/CodeGen/CGExprAgg.cpp
+++ b/clang/lib/CodeGen/CGExprAgg.cpp
@@ -499,6 +499,12 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr, llvm::ArrayType *AType,
     CodeGen::CodeGenModule &CGM = CGF.CGM;
     ConstantEmitter Emitter(CGF);
     LangAS AS = ArrayQTy.getAddressSpace();
+    if (CGM.getLangOpts().SYCLIsDevice && AS == LangAS::Default) {
+      // SYCL's default AS is 'generic', which can't be used to define constant
+      // initializer data in. It is reasonable to keep it in the same AS
+      // as string literals.
+      AS = CGM.getStringLiteralAddressSpace();
+    }
     if (llvm::Constant *C = Emitter.tryEmitForInitializer(E, AS, ArrayQTy)) {
       auto GV = new llvm::GlobalVariable(
           CGM.getModule(), C->getType(),
diff --git a/clang/lib/CodeGen/CGExprConstant.cpp b/clang/lib/CodeGen/CGExprConstant.cpp
index 840541a4af20a..ca1d3a937fa87 100644
--- a/clang/lib/CodeGen/CGExprConstant.cpp
+++ b/clang/lib/CodeGen/CGExprConstant.cpp
@@ -1366,11 +1366,11 @@ llvm::Constant *ConstantEmitter::tryEmitConstantExpr(const ConstantExpr *CE) {
   if (!CE->hasAPValueResult())
     return nullptr;
   const Expr *Inner = CE->getSubExpr()->IgnoreImplicit();
-  QualType RetType = Inner->getType();
-  if (Inner->isLValue())
-    RetType = CGF->getContext().getLValueReferenceType(RetType);
-  else if (Inner->isXValue())
-    RetType = CGF->getContext().getRValueReferenceType(RetType);
+  QualType RetType;
+  if (auto *Call = dyn_cast<CallExpr>(Inner))
+    RetType = Call->getCallReturnType(CGF->getContext());
+  else if (auto *Ctor = dyn_cast<CXXConstructExpr>(Inner))
+    RetType = Ctor->getType();
   llvm::Constant *Res =
       emitAbstract(CE->getBeginLoc(), CE->getAPValueResult(), RetType);
   return Res;
diff --git a/clang/lib/CodeGen/CGObjCMac.cpp b/clang/lib/CodeGen/CGObjCMac.cpp
index dff86744698d4..465d2c5449d55 100644
--- a/clang/lib/CodeGen/CGObjCMac.cpp
+++ b/clang/lib/CodeGen/CGObjCMac.cpp
@@ -1765,6 +1765,24 @@ struct NullReturnState {
           assert(RV.isScalar() &&
                  "NullReturnState::complete - arg not on object");
           CGF.EmitARCRelease(RV.getScalarVal(), ARCImpreciseLifetime);
+        } else {
+          QualType QT = ParamDecl->getType();
+          auto *RT = QT->getAs<RecordType>();
+          if (RT && RT->getDecl()->isParamDestroyedInCallee()) {
+            RValue RV = I->getRValue(CGF);
+            QualType::DestructionKind DtorKind = QT.isDestructedType();
+            switch (DtorKind) {
+            case QualType::DK_cxx_destructor:
+              CGF.destroyCXXObject(CGF, RV.getAggregateAddress(), QT);
+              break;
+            case QualType::DK_nontrivial_c_struct:
+              CGF.destroyNonTrivialCStruct(CGF, RV.getAggregateAddress(), QT);
+              break;
+            default:
+              llvm_unreachable("unexpected dtor kind");
+              break;
+            }
+          }
         }
       }
     }
@@ -2241,7 +2259,7 @@ CGObjCCommonMac::EmitMessageSend(CodeGen::CodeGenFunction &CGF,
   // Emit a null-check if there's a consumed argument other than the receiver.
   if (!RequiresNullCheck && CGM.getLangOpts().ObjCAutoRefCount && Method) {
     for (const auto *ParamDecl : Method->parameters()) {
-      if (ParamDecl->hasAttr<NSConsumedAttr>()) {
+      if (ParamDecl->isDestroyedInCallee()) {
         RequiresNullCheck = true;
         break;
       }
@@ -7350,7 +7368,7 @@ CGObjCNonFragileABIMac::EmitVTableMessageSend(CodeGenFunction &CGF,
   bool requiresnullCheck = false;
   if (CGM.getLangOpts().ObjCAutoRefCount && method)
     for (const auto *ParamDecl : method->parameters()) {
-      if (ParamDecl->hasAttr<NSConsumedAttr>()) {
+      if (ParamDecl->isDestroyedInCallee()) {
         if (!nullReturn.NullBB)
           nullReturn.init(CGF, arg0);
         requiresnullCheck = true;
diff --git a/clang/lib/CodeGen/CodeGenAction.cpp b/clang/lib/CodeGen/CodeGenAction.cpp
index 7a18397978ef5..80b504a700677 100644
--- a/clang/lib/CodeGen/CodeGenAction.cpp
+++ b/clang/lib/CodeGen/CodeGenAction.cpp
@@ -1091,78 +1091,74 @@ CodeGenAction::loadModule(MemoryBufferRef MBRef) {
 }
 
 void CodeGenAction::ExecuteAction() {
-  // If this is an IR file, we have to treat it specially.
-  if (getCurrentFileKind().getLanguage() == Language::LLVM_IR) {
-    BackendAction BA = static_cast<BackendAction>(Act);
-    CompilerInstance &CI = getCompilerInstance();
-    auto &CodeGenOpts = CI.getCodeGenOpts();
-    auto &Diagnostics = CI.getDiagnostics();
-    std::unique_ptr<raw_pwrite_stream> OS =
-        GetOutputStream(CI, getCurrentFile(), BA);
-    if (BA != Backend_EmitNothing && !OS)
-      return;
-
-    SourceManager &SM = CI.getSourceManager();
-    FileID FID = SM.getMainFileID();
-    Optional<MemoryBufferRef> MainFile = SM.getBufferOrNone(FID);
-    if (!MainFile)
-      return;
+  if (getCurrentFileKind().getLanguage() != Language::LLVM_IR) {
+    this->ASTFrontendAction::ExecuteAction();
+    return;
+  }
 
-    TheModule = loadModule(*MainFile);
-    if (!TheModule)
-      return;
+  // If this is an IR file, we have to treat it specially.
+  BackendAction BA = static_cast<BackendAction>(Act);
+  CompilerInstance &CI = getCompilerInstance();
+  auto &CodeGenOpts = CI.getCodeGenOpts();
+  auto &Diagnostics = CI.getDiagnostics();
+  std::unique_ptr<raw_pwrite_stream> OS =
+      GetOutputStream(CI, getCurrentFile(), BA);
+  if (BA != Backend_EmitNothing && !OS)
+    return;
 
-    const TargetOptions &TargetOpts = CI.getTargetOpts();
-    if (TheModule->getTargetTriple() != TargetOpts.Triple) {
-      Diagnostics.Report(SourceLocation(),
-                         diag::warn_fe_override_module)
-          << TargetOpts.Triple;
-      TheModule->setTargetTriple(TargetOpts.Triple);
-    }
+  SourceManager &SM = CI.getSourceManager();
+  FileID FID = SM.getMainFileID();
+  Optional<MemoryBufferRef> MainFile = SM.getBufferOrNone(FID);
+  if (!MainFile)
+    return;
 
-    EmbedBitcode(TheModule.get(), CodeGenOpts, *MainFile);
-
-    LLVMContext &Ctx = TheModule->getContext();
-    Ctx.setInlineAsmDiagnosticHandler(BitcodeInlineAsmDiagHandler,
-                                      &Diagnostics);
-
-    // Set clang diagnostic handler. To do this we need to create a fake
-    // BackendConsumer.
-    BackendConsumer Result(BA, CI.getDiagnostics(), CI.getHeaderSearchOpts(),
-                           CI.getPreprocessorOpts(), CI.getCodeGenOpts(),
-                           CI.getTargetOpts(), CI.getLangOpts(),
-                           std::move(LinkModules), *VMContext, nullptr);
-    // PR44896: Force DiscardValueNames as false. DiscardValueNames cannot be
-    // true here because the valued names are needed for reading textual IR.
-    Ctx.setDiscardValueNames(false);
-    Ctx.setDiagnosticHandler(
-        std::make_unique<ClangDiagnosticHandler>(CodeGenOpts, &Result));
-
-    Expected<std::unique_ptr<llvm::ToolOutputFile>> OptRecordFileOrErr =
-        setupLLVMOptimizationRemarks(
-            Ctx, CodeGenOpts.OptRecordFile, CodeGenOpts.OptRecordPasses,
-            CodeGenOpts.OptRecordFormat, CodeGenOpts.DiagnosticsWithHotness,
-            CodeGenOpts.DiagnosticsHotnessThreshold);
-
-    if (Error E = OptRecordFileOrErr.takeError()) {
-      reportOptRecordError(std::move(E), Diagnostics, CodeGenOpts);
-      return;
-    }
-    std::unique_ptr<llvm::ToolOutputFile> OptRecordFile =
-        std::move(*OptRecordFileOrErr);
+  TheModule = loadModule(*MainFile);
+  if (!TheModule)
+    return;
 
-    EmitBackendOutput(Diagnostics, CI.getHeaderSearchOpts(), CodeGenOpts,
-                      TargetOpts, CI.getLangOpts(),
-                      CI.getTarget().getDataLayout(), TheModule.get(), BA,
-                      std::move(OS));
+  const TargetOptions &TargetOpts = CI.getTargetOpts();
+  if (TheModule->getTargetTriple() != TargetOpts.Triple) {
+    Diagnostics.Report(SourceLocation(), diag::warn_fe_override_module)
+        << TargetOpts.Triple;
+    TheModule->setTargetTriple(TargetOpts.Triple);
+  }
 
-    if (OptRecordFile)
-      OptRecordFile->keep();
+  EmbedBitcode(TheModule.get(), CodeGenOpts, *MainFile);
+
+  LLVMContext &Ctx = TheModule->getContext();
+  Ctx.setInlineAsmDiagnosticHandler(BitcodeInlineAsmDiagHandler, &Diagnostics);
+
+  // Set clang diagnostic handler. To do this we need to create a fake
+  // BackendConsumer.
+  BackendConsumer Result(BA, CI.getDiagnostics(), CI.getHeaderSearchOpts(),
+                         CI.getPreprocessorOpts(), CI.getCodeGenOpts(),
+                         CI.getTargetOpts(), CI.getLangOpts(),
+                         std::move(LinkModules), *VMContext, nullptr);
+  // PR44896: Force DiscardValueNames as false. DiscardValueNames cannot be
+  // true here because the valued names are needed for reading textual IR.
+  Ctx.setDiscardValueNames(false);
+  Ctx.setDiagnosticHandler(
+      std::make_unique<ClangDiagnosticHandler>(CodeGenOpts, &Result));
+
+  Expected<std::unique_ptr<llvm::ToolOutputFile>> OptRecordFileOrErr =
+      setupLLVMOptimizationRemarks(
+          Ctx, CodeGenOpts.OptRecordFile, CodeGenOpts.OptRecordPasses,
+          CodeGenOpts.OptRecordFormat, CodeGenOpts.DiagnosticsWithHotness,
+          CodeGenOpts.DiagnosticsHotnessThreshold);
+
+  if (Error E = OptRecordFileOrErr.takeError()) {
+    reportOptRecordError(std::move(E), Diagnostics, CodeGenOpts);
     return;
   }
-
-  // Otherwise follow the normal AST path.
-  this->ASTFrontendAction::ExecuteAction();
+  std::unique_ptr<llvm::ToolOutputFile> OptRecordFile =
+      std::move(*OptRecordFileOrErr);
+
+  EmitBackendOutput(Diagnostics, CI.getHeaderSearchOpts(), CodeGenOpts,
+                    TargetOpts, CI.getLangOpts(),
+                    CI.getTarget().getDataLayout(), TheModule.get(), BA,
+                    std::move(OS));
+  if (OptRecordFile)
+    OptRecordFile->keep();
 }
 
 //
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index 75e9304bc3046..90dc5420baea6 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -621,12 +621,10 @@ void CodeGenFunction::EmitOpenCLKernelMetadata(const FunctionDecl *FD,
 
   if (const ReqdWorkGroupSizeAttr *A = FD->getAttr<ReqdWorkGroupSizeAttr>()) {
     llvm::LLVMContext &Context = getLLVMContext();
-    Optional<llvm::APSInt> XDimVal =
-        A->getXDim()->getIntegerConstantExpr(FD->getASTContext());
-    Optional<llvm::APSInt> YDimVal =
-        A->getYDim()->getIntegerConstantExpr(FD->getASTContext());
-    Optional<llvm::APSInt> ZDimVal =
-        A->getZDim()->getIntegerConstantExpr(FD->getASTContext());
+    ASTContext &ClangCtx = FD->getASTContext();
+    Optional<llvm::APSInt> XDimVal = A->getXDimVal(ClangCtx);
+    Optional<llvm::APSInt> YDimVal = A->getYDimVal(ClangCtx);
+    Optional<llvm::APSInt> ZDimVal = A->getZDimVal(ClangCtx);
 
     // For a SYCLDevice ReqdWorkGroupSizeAttr arguments are reversed.
     if (getLangOpts().SYCLIsDevice)
@@ -701,12 +699,10 @@ void CodeGenFunction::EmitOpenCLKernelMetadata(const FunctionDecl *FD,
   if (const SYCLIntelMaxWorkGroupSizeAttr *A =
           FD->getAttr<SYCLIntelMaxWorkGroupSizeAttr>()) {
     llvm::LLVMContext &Context = getLLVMContext();
-    Optional<llvm::APSInt> XDimVal =
-        A->getXDim()->getIntegerConstantExpr(FD->getASTContext());
-    Optional<llvm::APSInt> YDimVal =
-        A->getYDim()->getIntegerConstantExpr(FD->getASTContext());
-    Optional<llvm::APSInt> ZDimVal =
-        A->getZDim()->getIntegerConstantExpr(FD->getASTContext());
+    ASTContext &ClangCtx = FD->getASTContext();
+    Optional<llvm::APSInt> XDimVal = A->getXDimVal(ClangCtx);
+    Optional<llvm::APSInt> YDimVal = A->getYDimVal(ClangCtx);
+    Optional<llvm::APSInt> ZDimVal = A->getZDimVal(ClangCtx);
 
     // For a SYCLDevice SYCLIntelMaxWorkGroupSizeAttr arguments are reversed.
     if (getLangOpts().SYCLIsDevice)
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index b1990c00f32db..11555acc72609 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -8108,15 +8108,10 @@ void TCETargetCodeGenInfo::setTargetAttributes(
 
         SmallVector<llvm::Metadata *, 5> Operands;
         Operands.push_back(llvm::ConstantAsMetadata::get(F));
-        unsigned XDim = Attr->getXDim()
-                            ->EvaluateKnownConstInt(M.getContext())
-                            .getZExtValue();
-        unsigned YDim = Attr->getYDim()
-                            ->EvaluateKnownConstInt(M.getContext())
-                            .getZExtValue();
-        unsigned ZDim = Attr->getZDim()
-                            ->EvaluateKnownConstInt(M.getContext())
-                            .getZExtValue();
+        ASTContext &Ctx = M.getContext();
+        unsigned XDim = Attr->getXDimVal(Ctx)->getZExtValue();
+        unsigned YDim = Attr->getYDimVal(Ctx)->getZExtValue();
+        unsigned ZDim = Attr->getZDimVal(Ctx)->getZExtValue();
 
         Operands.push_back(llvm::ConstantAsMetadata::get(
             llvm::Constant::getIntegerValue(M.Int32Ty, llvm::APInt(32, XDim))));
@@ -9006,24 +9001,15 @@ void AMDGPUTargetCodeGenInfo::setTargetAttributes(
     unsigned XDim = 0;
     unsigned YDim = 0;
     unsigned ZDim = 0;
+    ASTContext &Ctx = M.getContext();
     if (FlatWGS) {
-      Min = FlatWGS->getMin()
-                ->EvaluateKnownConstInt(M.getContext())
-                .getExtValue();
-      Max = FlatWGS->getMax()
-                ->EvaluateKnownConstInt(M.getContext())
-                .getExtValue();
+      Min = FlatWGS->getMin()->EvaluateKnownConstInt(Ctx).getExtValue();
+      Max = FlatWGS->getMax()->EvaluateKnownConstInt(Ctx).getExtValue();
     }
     if (ReqdWGS) {
-      XDim = ReqdWGS->getXDim()
-                 ->EvaluateKnownConstInt(M.getContext())
-                 .getZExtValue();
-      YDim = ReqdWGS->getYDim()
-                 ->EvaluateKnownConstInt(M.getContext())
-                 .getZExtValue();
-      ZDim = ReqdWGS->getZDim()
-                 ->EvaluateKnownConstInt(M.getContext())
-                 .getZExtValue();
+      XDim = ReqdWGS->getXDimVal(Ctx)->getZExtValue();
+      YDim = ReqdWGS->getYDimVal(Ctx)->getZExtValue();
+      ZDim = ReqdWGS->getZDimVal(Ctx)->getZExtValue();
     }
     if (ReqdWGS && Min == 0 && Max == 0)
       Min = Max = XDim * YDim * ZDim;
diff --git a/clang/lib/Driver/ToolChains/AMDGPU.h b/clang/lib/Driver/ToolChains/AMDGPU.h
index f5448b76aee54..55ef6e01967ed 100644
--- a/clang/lib/Driver/ToolChains/AMDGPU.h
+++ b/clang/lib/Driver/ToolChains/AMDGPU.h
@@ -60,7 +60,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUToolChain : public Generic_ELF {
 public:
   AMDGPUToolChain(const Driver &D, const llvm::Triple &Triple,
                   const llvm::opt::ArgList &Args);
-  unsigned GetDefaultDwarfVersion() const override { return 5; }
+  unsigned GetDefaultDwarfVersion() const override { return 4; }
   bool IsIntegratedAssemblerDefault() const override { return true; }
   bool IsMathErrnoDefault() const override { return false; }
 
diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp
index a4378290b2976..0de6f44b04fb1 100644
--- a/clang/lib/Driver/ToolChains/Gnu.cpp
+++ b/clang/lib/Driver/ToolChains/Gnu.cpp
@@ -2742,6 +2742,9 @@ void Generic_GCC::printVerboseInfo(raw_ostream &OS) const {
 bool Generic_GCC::IsUnwindTablesDefault(const ArgList &Args) const {
   switch (getArch()) {
   case llvm::Triple::aarch64:
+  case llvm::Triple::ppc:
+  case llvm::Triple::ppc64:
+  case llvm::Triple::ppc64le:
   case llvm::Triple::x86_64:
     return true;
   default:
diff --git a/clang/lib/Driver/ToolChains/HIP.h b/clang/lib/Driver/ToolChains/HIP.h
index ff58c5451b0b8..5e2be7138579a 100644
--- a/clang/lib/Driver/ToolChains/HIP.h
+++ b/clang/lib/Driver/ToolChains/HIP.h
@@ -99,7 +99,7 @@ class LLVM_LIBRARY_VISIBILITY HIPToolChain final : public ROCMToolChain {
   computeMSVCVersion(const Driver *D,
                      const llvm::opt::ArgList &Args) const override;
 
-  unsigned GetDefaultDwarfVersion() const override { return 5; }
+  unsigned GetDefaultDwarfVersion() const override { return 4; }
 
   const ToolChain &HostTC;
 
diff --git a/clang/lib/Format/BreakableToken.cpp b/clang/lib/Format/BreakableToken.cpp
index ea5cc31af07a7..c5edc670393c5 100644
--- a/clang/lib/Format/BreakableToken.cpp
+++ b/clang/lib/Format/BreakableToken.cpp
@@ -41,8 +41,8 @@ static bool IsBlank(char C) {
 
 static StringRef getLineCommentIndentPrefix(StringRef Comment,
                                             const FormatStyle &Style) {
-  static const char *const KnownCStylePrefixes[] = {"///<", "//!<", "///", "//",
-                                                    "//!"};
+  static const char *const KnownCStylePrefixes[] = {"///<", "//!<", "///",
+                                                    "//",   "//!",  "//:"};
   static const char *const KnownTextProtoPrefixes[] = {"//", "#", "##", "###",
                                                        "####"};
   ArrayRef<const char *> KnownPrefixes(KnownCStylePrefixes);
@@ -789,9 +789,14 @@ BreakableLineCommentSection::BreakableLineCommentSection(
           Prefix[i] = "///< ";
         else if (Prefix[i] == "//!<")
           Prefix[i] = "//!< ";
-        else if (Prefix[i] == "#" &&
-                 Style.Language == FormatStyle::LK_TextProto)
+        else if (Prefix[i] == "#")
           Prefix[i] = "# ";
+        else if (Prefix[i] == "##")
+          Prefix[i] = "## ";
+        else if (Prefix[i] == "###")
+          Prefix[i] = "### ";
+        else if (Prefix[i] == "####")
+          Prefix[i] = "#### ";
       }
 
       Tokens[i] = LineTok;
diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp
index 23eee19b16404..54424ae190e24 100644
--- a/clang/lib/Format/Format.cpp
+++ b/clang/lib/Format/Format.cpp
@@ -608,6 +608,7 @@ template <> struct MappingTraits<FormatStyle> {
                    Style.SpaceAfterTemplateKeyword);
     IO.mapOptional("SpaceBeforeAssignmentOperators",
                    Style.SpaceBeforeAssignmentOperators);
+    IO.mapOptional("SpaceBeforeCaseColon", Style.SpaceBeforeCaseColon);
     IO.mapOptional("SpaceBeforeCpp11BracedList",
                    Style.SpaceBeforeCpp11BracedList);
     IO.mapOptional("SpaceBeforeCtorInitializerColon",
@@ -958,6 +959,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) {
   LLVMStyle.SpaceAfterLogicalNot = false;
   LLVMStyle.SpaceAfterTemplateKeyword = true;
   LLVMStyle.SpaceAroundPointerQualifiers = FormatStyle::SAPQ_Default;
+  LLVMStyle.SpaceBeforeCaseColon = false;
   LLVMStyle.SpaceBeforeCtorInitializerColon = true;
   LLVMStyle.SpaceBeforeInheritanceColon = true;
   LLVMStyle.SpaceBeforeParens = FormatStyle::SBPO_ControlStatements;
@@ -1327,16 +1329,17 @@ bool getPredefinedStyle(StringRef Name, FormatStyle::LanguageKind Language,
   return true;
 }
 
-std::error_code parseConfiguration(StringRef Text, FormatStyle *Style,
+std::error_code parseConfiguration(llvm::MemoryBufferRef Config,
+                                   FormatStyle *Style,
                                    bool AllowUnknownOptions) {
   assert(Style);
   FormatStyle::LanguageKind Language = Style->Language;
   assert(Language != FormatStyle::LK_None);
-  if (Text.trim().empty())
+  if (Config.getBuffer().trim().empty())
     return make_error_code(ParseError::Error);
   Style->StyleSet.Clear();
   std::vector<FormatStyle> Styles;
-  llvm::yaml::Input Input(Text);
+  llvm::yaml::Input Input(Config);
   // DocumentListTraits<vector<FormatStyle>> uses the context to get default
   // values for the fields, keys for which are missing from the configuration.
   // Mapping also uses the context to get the language to find the correct
@@ -2864,8 +2867,9 @@ llvm::Expected<FormatStyle> getStyle(StringRef StyleName, StringRef FileName,
 
   if (StyleName.startswith("{")) {
     // Parse YAML/JSON style from the command line.
-    if (std::error_code ec =
-            parseConfiguration(StyleName, &Style, AllowUnknownOptions))
+    if (std::error_code ec = parseConfiguration(
+            llvm::MemoryBufferRef(StyleName, "<command-line>"), &Style,
+            AllowUnknownOptions))
       return make_string_error("Error parsing -style: " + ec.message());
     return Style;
   }
@@ -2909,8 +2913,8 @@ llvm::Expected<FormatStyle> getStyle(StringRef StyleName, StringRef FileName,
             FS->getBufferForFile(ConfigFile.str());
         if (std::error_code EC = Text.getError())
           return make_string_error(EC.message());
-        if (std::error_code ec = parseConfiguration(
-                Text.get()->getBuffer(), &Style, AllowUnknownOptions)) {
+        if (std::error_code ec =
+                parseConfiguration(*Text.get(), &Style, AllowUnknownOptions)) {
           if (ec == ParseError::Unsuitable) {
             if (!UnsuitableConfigFiles.empty())
               UnsuitableConfigFiles.append(", ");
diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp
old mode 100644
new mode 100755
index 821b46b75f6bc..1588f7d08184e
--- a/clang/lib/Format/TokenAnnotator.cpp
+++ b/clang/lib/Format/TokenAnnotator.cpp
@@ -896,7 +896,8 @@ class AnnotatingParser {
       } else if (CurrentToken && CurrentToken->is(tok::numeric_constant)) {
         Tok->setType(TT_BitFieldColon);
       } else if (Contexts.size() == 1 &&
-                 !Line.First->isOneOf(tok::kw_enum, tok::kw_case)) {
+                 !Line.First->isOneOf(tok::kw_enum, tok::kw_case,
+                                      tok::kw_default)) {
         FormatToken *Prev = Tok->getPreviousNonComment();
         if (Prev->isOneOf(tok::r_paren, tok::kw_noexcept))
           Tok->setType(TT_CtorInitializerColon);
@@ -1915,6 +1916,13 @@ class AnnotatingParser {
     if (Tok.Next->isOneOf(tok::identifier, tok::kw_this))
       return true;
 
+    if (Tok.Next->is(tok::l_paren) &&
+        !(Tok.Previous && Tok.Previous->is(tok::identifier) &&
+          Tok.Previous->Previous &&
+          Tok.Previous->Previous->isOneOf(tok::arrowstar, tok::arrow,
+                                          tok::star)))
+      return true;
+
     if (!Tok.Next->Next)
       return false;
 
@@ -1964,9 +1972,9 @@ class AnnotatingParser {
 
     if (PrevToken->isOneOf(tok::l_paren, tok::l_square, tok::l_brace,
                            tok::comma, tok::semi, tok::kw_return, tok::colon,
-                           tok::kw_co_return, tok::kw_co_await, tok::kw_co_yield,
-                           tok::equal, tok::kw_delete, tok::kw_sizeof,
-                           tok::kw_throw) ||
+                           tok::kw_co_return, tok::kw_co_await,
+                           tok::kw_co_yield, tok::equal, tok::kw_delete,
+                           tok::kw_sizeof, tok::kw_throw) ||
         PrevToken->isOneOf(TT_BinaryOperator, TT_ConditionalExpr,
                            TT_UnaryOperator, TT_CastRParen))
       return TT_UnaryOperator;
@@ -3340,8 +3348,9 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line,
     return Style.BitFieldColonSpacing == FormatStyle::BFCS_Both ||
            Style.BitFieldColonSpacing == FormatStyle::BFCS_After;
   if (Right.is(tok::colon)) {
-    if (Line.First->isOneOf(tok::kw_case, tok::kw_default) ||
-        !Right.getNextNonComment() || Right.getNextNonComment()->is(tok::semi))
+    if (Line.First->isOneOf(tok::kw_default, tok::kw_case))
+      return Style.SpaceBeforeCaseColon;
+    if (!Right.getNextNonComment() || Right.getNextNonComment()->is(tok::semi))
       return false;
     if (Right.is(TT_ObjCMethodExpr))
       return false;
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp
index 4c2ee421d092c..99b8c28dca2be 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -2244,18 +2244,26 @@ void UnwrappedLineParser::parseLabel(bool LeftAlignLabel) {
     --Line->Level;
   if (LeftAlignLabel)
     Line->Level = 0;
+
+  bool RemoveWhitesmithsCaseIndent =
+      (!Style.IndentCaseBlocks &&
+       Style.BreakBeforeBraces == FormatStyle::BS_Whitesmiths);
+
+  if (RemoveWhitesmithsCaseIndent)
+    --Line->Level;
+
   if (!Style.IndentCaseBlocks && CommentsBeforeNextToken.empty() &&
       FormatTok->Tok.is(tok::l_brace)) {
-    CompoundStatementIndenter Indenter(this, Line->Level,
-                                       Style.BraceWrapping.AfterCaseLabel,
-                                       Style.BraceWrapping.IndentBraces);
+
+    CompoundStatementIndenter Indenter(
+        this, Line->Level, Style.BraceWrapping.AfterCaseLabel,
+        Style.BraceWrapping.IndentBraces || RemoveWhitesmithsCaseIndent);
     parseBlock(/*MustBeDeclaration=*/false);
     if (FormatTok->Tok.is(tok::kw_break)) {
       if (Style.BraceWrapping.AfterControlStatement ==
           FormatStyle::BWACS_Always) {
         addUnwrappedLine();
-        if (!Style.IndentCaseBlocks &&
-            Style.BreakBeforeBraces == FormatStyle::BS_Whitesmiths) {
+        if (RemoveWhitesmithsCaseIndent) {
           Line->Level++;
         }
       }
@@ -2276,6 +2284,7 @@ void UnwrappedLineParser::parseLabel(bool LeftAlignLabel) {
 
 void UnwrappedLineParser::parseCaseLabel() {
   assert(FormatTok->Tok.is(tok::kw_case) && "'case' expected");
+
   // FIXME: fix handling of complex expressions here.
   do {
     nextToken();
diff --git a/clang/lib/Frontend/CompilerInstance.cpp b/clang/lib/Frontend/CompilerInstance.cpp
index 6226cc086fb25..46d8f7299c51c 100644
--- a/clang/lib/Frontend/CompilerInstance.cpp
+++ b/clang/lib/Frontend/CompilerInstance.cpp
@@ -848,56 +848,22 @@ bool CompilerInstance::InitializeSourceManager(const FrontendInputFile &Input,
   StringRef InputFile = Input.getFile();
 
   // Figure out where to get and map in the main file.
-  if (InputFile != "-") {
-    auto FileOrErr = FileMgr.getFileRef(InputFile, /*OpenFile=*/true);
-    if (!FileOrErr) {
-      // FIXME: include the error in the diagnostic.
-      consumeError(FileOrErr.takeError());
+  auto FileOrErr = InputFile == "-"
+                       ? FileMgr.getSTDIN()
+                       : FileMgr.getFileRef(InputFile, /*OpenFile=*/true);
+  if (!FileOrErr) {
+    // FIXME: include the error in the diagnostic even when it's not stdin.
+    auto EC = llvm::errorToErrorCode(FileOrErr.takeError());
+    if (InputFile != "-")
       Diags.Report(diag::err_fe_error_reading) << InputFile;
-      return false;
-    }
-    FileEntryRef File = *FileOrErr;
-
-    // The natural SourceManager infrastructure can't currently handle named
-    // pipes, but we would at least like to accept them for the main
-    // file. Detect them here, read them with the volatile flag so FileMgr will
-    // pick up the correct size, and simply override their contents as we do for
-    // STDIN.
-    if (File.getFileEntry().isNamedPipe()) {
-      auto MB =
-          FileMgr.getBufferForFile(&File.getFileEntry(), /*isVolatile=*/true);
-      if (MB) {
-        // Create a new virtual file that will have the correct size.
-        FileEntryRef FE =
-            FileMgr.getVirtualFileRef(InputFile, (*MB)->getBufferSize(), 0);
-        SourceMgr.overrideFileContents(FE, std::move(*MB));
-        SourceMgr.setMainFileID(
-            SourceMgr.createFileID(FE, SourceLocation(), Kind));
-      } else {
-        Diags.Report(diag::err_cannot_open_file) << InputFile
-                                                 << MB.getError().message();
-        return false;
-      }
-    } else {
-      SourceMgr.setMainFileID(
-          SourceMgr.createFileID(File, SourceLocation(), Kind));
-    }
-  } else {
-    llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> SBOrErr =
-        llvm::MemoryBuffer::getSTDIN();
-    if (std::error_code EC = SBOrErr.getError()) {
+    else
       Diags.Report(diag::err_fe_error_reading_stdin) << EC.message();
-      return false;
-    }
-    std::unique_ptr<llvm::MemoryBuffer> SB = std::move(SBOrErr.get());
-
-    FileEntryRef File = FileMgr.getVirtualFileRef(SB->getBufferIdentifier(),
-                                                  SB->getBufferSize(), 0);
-    SourceMgr.setMainFileID(
-        SourceMgr.createFileID(File, SourceLocation(), Kind));
-    SourceMgr.overrideFileContents(File, std::move(SB));
+    return false;
   }
 
+  SourceMgr.setMainFileID(
+      SourceMgr.createFileID(*FileOrErr, SourceLocation(), Kind));
+
   assert(SourceMgr.getMainFileID().isValid() &&
          "Couldn't establish MainFileID!");
   return true;
diff --git a/clang/lib/Frontend/CompilerInvocation.cpp b/clang/lib/Frontend/CompilerInvocation.cpp
index 3bcc76279ae85..3f6262c3e7bb3 100644
--- a/clang/lib/Frontend/CompilerInvocation.cpp
+++ b/clang/lib/Frontend/CompilerInvocation.cpp
@@ -152,38 +152,31 @@ static Optional<bool> normalizeSimpleNegativeFlag(OptSpecifier Opt, unsigned,
 /// argument.
 static void denormalizeSimpleFlag(SmallVectorImpl<const char *> &Args,
                                   const char *Spelling,
-                                  CompilerInvocation::StringAllocator,
-                                  Option::OptionClass, unsigned, /*T*/...) {
+                                  CompilerInvocation::StringAllocator, unsigned,
+                                  /*T*/...) {
   Args.push_back(Spelling);
 }
 
-namespace {
-template <typename T> struct FlagToValueNormalizer {
-  T Value;
+template <typename T> static constexpr bool is_uint64_t_convertible() {
+  return !std::is_same<T, uint64_t>::value &&
+         llvm::is_integral_or_enum<T>::value;
+}
 
-  Optional<T> operator()(OptSpecifier Opt, unsigned, const ArgList &Args,
-                         DiagnosticsEngine &) {
+template <typename T,
+          std::enable_if_t<!is_uint64_t_convertible<T>(), bool> = false>
+static auto makeFlagToValueNormalizer(T Value) {
+  return [Value](OptSpecifier Opt, unsigned, const ArgList &Args,
+                 DiagnosticsEngine &) -> Optional<T> {
     if (Args.hasArg(Opt))
       return Value;
     return None;
-  }
-};
-} // namespace
-
-template <typename T> static constexpr bool is_int_convertible() {
-  return sizeof(T) <= sizeof(uint64_t) &&
-         std::is_trivially_constructible<T, uint64_t>::value &&
-         std::is_trivially_constructible<uint64_t, T>::value;
-}
-
-template <typename T, std::enable_if_t<is_int_convertible<T>(), bool> = false>
-static FlagToValueNormalizer<uint64_t> makeFlagToValueNormalizer(T Value) {
-  return FlagToValueNormalizer<uint64_t>{Value};
+  };
 }
 
-template <typename T, std::enable_if_t<!is_int_convertible<T>(), bool> = false>
-static FlagToValueNormalizer<T> makeFlagToValueNormalizer(T Value) {
-  return FlagToValueNormalizer<T>{std::move(Value)};
+template <typename T,
+          std::enable_if_t<is_uint64_t_convertible<T>(), bool> = false>
+static auto makeFlagToValueNormalizer(T Value) {
+  return makeFlagToValueNormalizer(uint64_t(Value));
 }
 
 static auto makeBooleanOptionNormalizer(bool Value, bool OtherValue,
@@ -200,41 +193,12 @@ static auto makeBooleanOptionNormalizer(bool Value, bool OtherValue,
 
 static auto makeBooleanOptionDenormalizer(bool Value) {
   return [Value](SmallVectorImpl<const char *> &Args, const char *Spelling,
-                 CompilerInvocation::StringAllocator, Option::OptionClass,
-                 unsigned, bool KeyPath) {
+                 CompilerInvocation::StringAllocator, unsigned, bool KeyPath) {
     if (KeyPath == Value)
       Args.push_back(Spelling);
   };
 }
 
-static void denormalizeStringImpl(SmallVectorImpl<const char *> &Args,
-                                  const char *Spelling,
-                                  CompilerInvocation::StringAllocator SA,
-                                  Option::OptionClass OptClass, unsigned,
-                                  Twine Value) {
-  switch (OptClass) {
-  case Option::SeparateClass:
-  case Option::JoinedOrSeparateClass:
-    Args.push_back(Spelling);
-    Args.push_back(SA(Value));
-    break;
-  case Option::JoinedClass:
-    Args.push_back(SA(Twine(Spelling) + Value));
-    break;
-  default:
-    llvm_unreachable("Cannot denormalize an option with option class "
-                     "incompatible with string denormalization.");
-  }
-}
-
-template <typename T>
-static void
-denormalizeString(SmallVectorImpl<const char *> &Args, const char *Spelling,
-                  CompilerInvocation::StringAllocator SA,
-                  Option::OptionClass OptClass, unsigned TableIndex, T Value) {
-  denormalizeStringImpl(Args, Spelling, SA, OptClass, TableIndex, Twine(Value));
-}
-
 static Optional<SimpleEnumValue>
 findValueTableByName(const SimpleEnumValueTable &Table, StringRef Name) {
   for (int I = 0, E = Table.Size; I != E; ++I)
@@ -276,13 +240,12 @@ static llvm::Optional<unsigned> normalizeSimpleEnum(OptSpecifier Opt,
 static void denormalizeSimpleEnumImpl(SmallVectorImpl<const char *> &Args,
                                       const char *Spelling,
                                       CompilerInvocation::StringAllocator SA,
-                                      Option::OptionClass OptClass,
                                       unsigned TableIndex, unsigned Value) {
   assert(TableIndex < SimpleEnumValueTablesSize);
   const SimpleEnumValueTable &Table = SimpleEnumValueTables[TableIndex];
   if (auto MaybeEnumVal = findValueTableByValue(Table, Value)) {
-    denormalizeString(Args, Spelling, SA, OptClass, TableIndex,
-                      MaybeEnumVal->Name);
+    Args.push_back(Spelling);
+    Args.push_back(MaybeEnumVal->Name);
   } else {
     llvm_unreachable("The simple enum value was not correctly defined in "
                      "the tablegen option description");
@@ -293,12 +256,24 @@ template <typename T>
 static void denormalizeSimpleEnum(SmallVectorImpl<const char *> &Args,
                                   const char *Spelling,
                                   CompilerInvocation::StringAllocator SA,
-                                  Option::OptionClass OptClass,
                                   unsigned TableIndex, T Value) {
-  return denormalizeSimpleEnumImpl(Args, Spelling, SA, OptClass, TableIndex,
+  return denormalizeSimpleEnumImpl(Args, Spelling, SA, TableIndex,
                                    static_cast<unsigned>(Value));
 }
 
+static void denormalizeSimpleEnumJoined(SmallVectorImpl<const char *> &Args,
+                                        const char *Spelling,
+                                        CompilerInvocation::StringAllocator SA,
+                                        unsigned TableIndex, unsigned Value) {
+  assert(TableIndex < SimpleEnumValueTablesSize);
+  const SimpleEnumValueTable &Table = SimpleEnumValueTables[TableIndex];
+  if (auto MaybeEnumVal = findValueTableByValue(Table, Value))
+    Args.push_back(SA(Twine(Spelling) + MaybeEnumVal->Name));
+  else
+    llvm_unreachable("The simple enum value was not correctly defined in "
+                     "the tablegen option description");
+}
+
 static Optional<std::string> normalizeString(OptSpecifier Opt, int TableIndex,
                                              const ArgList &Args,
                                              DiagnosticsEngine &Diags) {
@@ -308,6 +283,25 @@ static Optional<std::string> normalizeString(OptSpecifier Opt, int TableIndex,
   return std::string(Arg->getValue());
 }
 
+static void denormalizeString(SmallVectorImpl<const char *> &Args,
+                              const char *Spelling,
+                              CompilerInvocation::StringAllocator SA, unsigned,
+                              Twine Value) {
+  Args.push_back(Spelling);
+  Args.push_back(SA(Value));
+}
+
+template <typename T,
+          std::enable_if_t<!std::is_convertible<T, Twine>::value &&
+                               std::is_constructible<Twine, T>::value,
+                           bool> = false>
+static void denormalizeString(SmallVectorImpl<const char *> &Args,
+                              const char *Spelling,
+                              CompilerInvocation::StringAllocator SA,
+                              unsigned TableIndex, T Value) {
+  denormalizeString(Args, Spelling, SA, TableIndex, Twine(Value));
+}
+
 template <typename IntTy>
 static Optional<IntTy> normalizeStringIntegral(OptSpecifier Opt, int,
                                                const ArgList &Args,
@@ -351,8 +345,7 @@ static T extractMaskValue(T KeyPath) {
 }
 
 static void FixupInvocation(CompilerInvocation &Invocation,
-                            DiagnosticsEngine &Diags,
-                            const InputArgList &Args) {
+                            DiagnosticsEngine &Diags) {
   LangOptions &LangOpts = *Invocation.getLangOpts();
   DiagnosticOptions &DiagOpts = Invocation.getDiagnosticOpts();
   CodeGenOptions &CodeGenOpts = Invocation.getCodeGenOpts();
@@ -361,52 +354,16 @@ static void FixupInvocation(CompilerInvocation &Invocation,
   CodeGenOpts.XRayInstrumentFunctions = LangOpts.XRayInstrument;
   CodeGenOpts.XRayAlwaysEmitCustomEvents = LangOpts.XRayAlwaysEmitCustomEvents;
   CodeGenOpts.XRayAlwaysEmitTypedEvents = LangOpts.XRayAlwaysEmitTypedEvents;
-  CodeGenOpts.DisableFree = FrontendOpts.DisableFree;
   FrontendOpts.GenerateGlobalModuleIndex = FrontendOpts.UseGlobalModuleIndex;
 
-  LangOpts.ForceEmitVTables = CodeGenOpts.ForceEmitVTables;
-  LangOpts.SpeculativeLoadHardening = CodeGenOpts.SpeculativeLoadHardening;
-  LangOpts.CurrentModule = LangOpts.ModuleName;
-
   llvm::sys::Process::UseANSIEscapeCodes(DiagOpts.UseANSIEscapeCodes);
 
   llvm::Triple T(TargetOpts.Triple);
-  llvm::Triple::ArchType Arch = T.getArch();
 
   if (LangOpts.getExceptionHandling() != llvm::ExceptionHandling::None &&
       T.isWindowsMSVCEnvironment())
     Diags.Report(diag::err_fe_invalid_exception_model)
         << static_cast<unsigned>(LangOpts.getExceptionHandling()) << T.str();
-
-  if (LangOpts.AppleKext && !LangOpts.CPlusPlus)
-    Diags.Report(diag::warn_c_kext);
-
-  if (LangOpts.NewAlignOverride &&
-      !llvm::isPowerOf2_32(LangOpts.NewAlignOverride)) {
-    Arg *A = Args.getLastArg(OPT_fnew_alignment_EQ);
-    Diags.Report(diag::err_fe_invalid_alignment)
-        << A->getAsString(Args) << A->getValue();
-    LangOpts.NewAlignOverride = 0;
-  }
-
-  if (Arg *A = Args.getLastArg(OPT_fdefault_calling_conv_EQ)) {
-    auto DefaultCC = LangOpts.getDefaultCallingConv();
-
-    bool emitError = (DefaultCC == LangOptions::DCC_FastCall ||
-                      DefaultCC == LangOptions::DCC_StdCall) &&
-                     Arch != llvm::Triple::x86;
-    emitError |= (DefaultCC == LangOptions::DCC_VectorCall ||
-                  DefaultCC == LangOptions::DCC_RegCall) &&
-                 !T.isX86();
-    if (emitError)
-      Diags.Report(diag::err_drv_argument_not_allowed_with)
-          << A->getSpelling() << T.getTriple();
-  }
-
-  if (!CodeGenOpts.ProfileRemappingFile.empty() && CodeGenOpts.LegacyPassManager)
-    Diags.Report(diag::err_drv_argument_only_allowed_with)
-        << Args.getLastArg(OPT_fprofile_remapping_file_EQ)->getAsString(Args)
-        << "-fno-legacy-pass-manager";
 }
 
 //===----------------------------------------------------------------------===//
@@ -850,6 +807,28 @@ static void parseXRayInstrumentationBundle(StringRef FlagName, StringRef Bundle,
   }
 }
 
+// Set the profile kind for fprofile-instrument.
+static void setPGOInstrumentor(CodeGenOptions &Opts, ArgList &Args,
+                               DiagnosticsEngine &Diags) {
+  Arg *A = Args.getLastArg(OPT_fprofile_instrument_EQ);
+  if (A == nullptr)
+    return;
+  StringRef S = A->getValue();
+  unsigned I = llvm::StringSwitch<unsigned>(S)
+                   .Case("none", CodeGenOptions::ProfileNone)
+                   .Case("clang", CodeGenOptions::ProfileClangInstr)
+                   .Case("llvm", CodeGenOptions::ProfileIRInstr)
+                   .Case("csllvm", CodeGenOptions::ProfileCSIRInstr)
+                   .Default(~0U);
+  if (I == ~0U) {
+    Diags.Report(diag::err_drv_invalid_pgo_instrumentor) << A->getAsString(Args)
+                                                         << S;
+    return;
+  }
+  auto Instrumentor = static_cast<CodeGenOptions::ProfileInstrKind>(I);
+  Opts.setProfileInstr(Instrumentor);
+}
+
 // Set the profile kind using fprofile-instrument-use-path.
 static void setPGOUseInstrumentor(CodeGenOptions &Opts,
                                   const Twine &ProfileName) {
@@ -911,18 +890,90 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
     }
   }
 
+  if (Arg *A = Args.getLastArg(OPT_fveclib)) {
+    StringRef Name = A->getValue();
+    if (Name == "Accelerate")
+      Opts.setVecLib(CodeGenOptions::Accelerate);
+    else if (Name == "libmvec")
+      Opts.setVecLib(CodeGenOptions::LIBMVEC);
+    else if (Name == "MASSV")
+      Opts.setVecLib(CodeGenOptions::MASSV);
+    else if (Name == "SVML")
+      Opts.setVecLib(CodeGenOptions::SVML);
+    else if (Name == "none")
+      Opts.setVecLib(CodeGenOptions::NoLibrary);
+    else
+      Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Name;
+  }
+
+  if (Arg *A = Args.getLastArg(OPT_debug_info_kind_EQ)) {
+    unsigned Val =
+        llvm::StringSwitch<unsigned>(A->getValue())
+            .Case("line-tables-only", codegenoptions::DebugLineTablesOnly)
+            .Case("line-directives-only", codegenoptions::DebugDirectivesOnly)
+            .Case("constructor", codegenoptions::DebugInfoConstructor)
+            .Case("limited", codegenoptions::LimitedDebugInfo)
+            .Case("standalone", codegenoptions::FullDebugInfo)
+            .Case("unused-types", codegenoptions::UnusedTypeInfo)
+            .Default(~0U);
+    if (Val == ~0U)
+      Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args)
+                                                << A->getValue();
+    else
+      Opts.setDebugInfo(static_cast<codegenoptions::DebugInfoKind>(Val));
+  }
   // If -fuse-ctor-homing is set and limited debug info is already on, then use
   // constructor homing.
   if (Args.getLastArg(OPT_fuse_ctor_homing))
     if (Opts.getDebugInfo() == codegenoptions::LimitedDebugInfo)
       Opts.setDebugInfo(codegenoptions::DebugInfoConstructor);
 
+  if (Arg *A = Args.getLastArg(OPT_debugger_tuning_EQ)) {
+    unsigned Val = llvm::StringSwitch<unsigned>(A->getValue())
+                       .Case("gdb", unsigned(llvm::DebuggerKind::GDB))
+                       .Case("lldb", unsigned(llvm::DebuggerKind::LLDB))
+                       .Case("sce", unsigned(llvm::DebuggerKind::SCE))
+                       .Default(~0U);
+    if (Val == ~0U)
+      Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args)
+                                                << A->getValue();
+    else
+      Opts.setDebuggerTuning(static_cast<llvm::DebuggerKind>(Val));
+  }
+  Opts.DwarfVersion = getLastArgIntValue(Args, OPT_dwarf_version_EQ, 0, Diags);
+  Opts.DebugColumnInfo = !Args.hasArg(OPT_gno_column_info);
+  Opts.EmitCodeView = Args.hasArg(OPT_gcodeview);
+  Opts.MacroDebugInfo = Args.hasArg(OPT_debug_info_macro);
+  Opts.WholeProgramVTables = Args.hasArg(OPT_fwhole_program_vtables);
+  Opts.VirtualFunctionElimination =
+      Args.hasArg(OPT_fvirtual_function_elimination);
+  Opts.LTOVisibilityPublicStd = Args.hasArg(OPT_flto_visibility_public_std);
+  Opts.SplitDwarfFile = std::string(Args.getLastArgValue(OPT_split_dwarf_file));
+  Opts.SplitDwarfOutput =
+      std::string(Args.getLastArgValue(OPT_split_dwarf_output));
+  Opts.SplitDwarfInlining = !Args.hasArg(OPT_fno_split_dwarf_inlining);
+  Opts.DebugTypeExtRefs = Args.hasArg(OPT_dwarf_ext_refs);
+  Opts.DebugExplicitImport = Args.hasArg(OPT_dwarf_explicit_import);
+  Opts.DebugFwdTemplateParams = Args.hasArg(OPT_debug_forward_template_params);
+  Opts.EmbedSource = Args.hasArg(OPT_gembed_source);
+  Opts.ForceDwarfFrameSection = Args.hasArg(OPT_fforce_dwarf_frame);
+
   for (const auto &Arg : Args.getAllArgValues(OPT_fdebug_prefix_map_EQ)) {
     auto Split = StringRef(Arg).split('=');
     Opts.DebugPrefixMap.insert(
         {std::string(Split.first), std::string(Split.second)});
   }
 
+  if (const Arg *A =
+          Args.getLastArg(OPT_emit_llvm_uselists, OPT_no_emit_llvm_uselists))
+    Opts.EmitLLVMUseLists = A->getOption().getID() == OPT_emit_llvm_uselists;
+
+  Opts.DisableLLVMPasses =
+      Args.hasArg(OPT_disable_llvm_passes) ||
+      (Args.hasArg(OPT_fsycl_is_device) && Triple.isSPIR() &&
+       Args.hasArg(OPT_fno_sycl_early_optimizations));
+  Opts.DisableLifetimeMarkers = Args.hasArg(OPT_disable_lifetimemarkers);
+
   const llvm::Triple::ArchType DebugEntryValueArchs[] = {
       llvm::Triple::x86, llvm::Triple::x86_64, llvm::Triple::aarch64,
       llvm::Triple::arm, llvm::Triple::armeb, llvm::Triple::mips,
@@ -933,8 +984,29 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
       llvm::is_contained(DebugEntryValueArchs, T.getArch()))
     Opts.EmitCallSiteInfo = true;
 
+  Opts.ValueTrackingVariableLocations =
+      Args.hasArg(OPT_fexperimental_debug_variable_locations);
+
+  Opts.DisableO0ImplyOptNone = Args.hasArg(OPT_disable_O0_optnone);
+  Opts.DisableRedZone = Args.hasArg(OPT_disable_red_zone);
+  Opts.IndirectTlsSegRefs = Args.hasArg(OPT_mno_tls_direct_seg_refs);
+  Opts.ForbidGuardVariables = Args.hasArg(OPT_fforbid_guard_variables);
+  Opts.UseRegisterSizedBitfieldAccess = Args.hasArg(
+    OPT_fuse_register_sized_bitfield_access);
+  Opts.RelaxedAliasing = Args.hasArg(OPT_relaxed_aliasing);
+  Opts.StructPathTBAA = !Args.hasArg(OPT_no_struct_path_tbaa);
   Opts.NewStructPathTBAA = !Args.hasArg(OPT_no_struct_path_tbaa) &&
                            Args.hasArg(OPT_new_struct_path_tbaa);
+  Opts.FineGrainedBitfieldAccesses =
+      Args.hasFlag(OPT_ffine_grained_bitfield_accesses,
+                   OPT_fno_fine_grained_bitfield_accesses, false);
+  Opts.DwarfDebugFlags =
+      std::string(Args.getLastArgValue(OPT_dwarf_debug_flags));
+  Opts.RecordCommandLine =
+      std::string(Args.getLastArgValue(OPT_record_command_line));
+  Opts.MergeAllConstants = Args.hasArg(OPT_fmerge_all_constants);
+  Opts.NoCommon = !Args.hasArg(OPT_fcommon);
+  Opts.NoImplicitFloat = Args.hasArg(OPT_no_implicit_float);
   Opts.OptimizeSize = getOptimizationLevelSize(Args);
   Opts.SimplifyLibCalls = !(Args.hasArg(OPT_fno_builtin) ||
                             Args.hasArg(OPT_ffreestanding));
@@ -943,18 +1015,73 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
   Opts.UnrollLoops =
       Args.hasFlag(OPT_funroll_loops, OPT_fno_unroll_loops,
                    (Opts.OptimizationLevel > 1));
-
+  Opts.RerollLoops = Args.hasArg(OPT_freroll_loops);
+
+  Opts.DisableIntegratedAS = Args.hasArg(OPT_fno_integrated_as);
+  Opts.SampleProfileFile =
+      std::string(Args.getLastArgValue(OPT_fprofile_sample_use_EQ));
+  Opts.DebugInfoForProfiling = Args.hasFlag(
+      OPT_fdebug_info_for_profiling, OPT_fno_debug_info_for_profiling, false);
+  Opts.PseudoProbeForProfiling =
+      Args.hasFlag(OPT_fpseudo_probe_for_profiling,
+                   OPT_fno_pseudo_probe_for_profiling, false);
   Opts.DebugNameTable = static_cast<unsigned>(
       Args.hasArg(OPT_ggnu_pubnames)
           ? llvm::DICompileUnit::DebugNameTableKind::GNU
           : Args.hasArg(OPT_gpubnames)
                 ? llvm::DICompileUnit::DebugNameTableKind::Default
                 : llvm::DICompileUnit::DebugNameTableKind::None);
-
+  Opts.DebugRangesBaseAddress = Args.hasArg(OPT_fdebug_ranges_base_address);
+
+  setPGOInstrumentor(Opts, Args, Diags);
+  Opts.AtomicProfileUpdate = Args.hasArg(OPT_fprofile_update_EQ);
+  Opts.InstrProfileOutput =
+      std::string(Args.getLastArgValue(OPT_fprofile_instrument_path_EQ));
+  Opts.ProfileInstrumentUsePath =
+      std::string(Args.getLastArgValue(OPT_fprofile_instrument_use_path_EQ));
   if (!Opts.ProfileInstrumentUsePath.empty())
     setPGOUseInstrumentor(Opts, Opts.ProfileInstrumentUsePath);
+  Opts.ProfileRemappingFile =
+      std::string(Args.getLastArgValue(OPT_fprofile_remapping_file_EQ));
+  if (!Opts.ProfileRemappingFile.empty() && Opts.LegacyPassManager) {
+    Diags.Report(diag::err_drv_argument_only_allowed_with)
+        << Args.getLastArg(OPT_fprofile_remapping_file_EQ)->getAsString(Args)
+        << "-fno-legacy-pass-manager";
+  }
 
+  Opts.CoverageMapping =
+      Args.hasFlag(OPT_fcoverage_mapping, OPT_fno_coverage_mapping, false);
+  Opts.DumpCoverageMapping = Args.hasArg(OPT_dump_coverage_mapping);
+  Opts.AsmVerbose = !Args.hasArg(OPT_fno_verbose_asm);
+  Opts.PreserveAsmComments = !Args.hasArg(OPT_fno_preserve_as_comments);
+  Opts.AssumeSaneOperatorNew = !Args.hasArg(OPT_fno_assume_sane_operator_new);
+  Opts.ObjCAutoRefCountExceptions = Args.hasArg(OPT_fobjc_arc_exceptions);
+  Opts.CXAAtExit = !Args.hasArg(OPT_fno_use_cxa_atexit);
+  Opts.RegisterGlobalDtorsWithAtExit =
+      Args.hasArg(OPT_fregister_global_dtors_with_atexit);
+  Opts.CXXCtorDtorAliases = Args.hasArg(OPT_mconstructor_aliases);
   Opts.CodeModel = TargetOpts.CodeModel;
+  Opts.DebugPass = std::string(Args.getLastArgValue(OPT_mdebug_pass));
+
+  // Handle -mframe-pointer option.
+  if (Arg *A = Args.getLastArg(OPT_mframe_pointer_EQ)) {
+    CodeGenOptions::FramePointerKind FP;
+    StringRef Name = A->getValue();
+    bool ValidFP = true;
+    if (Name == "none")
+      FP = CodeGenOptions::FramePointerKind::None;
+    else if (Name == "non-leaf")
+      FP = CodeGenOptions::FramePointerKind::NonLeaf;
+    else if (Name == "all")
+      FP = CodeGenOptions::FramePointerKind::All;
+    else {
+      Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Name;
+      Success = false;
+      ValidFP = false;
+    }
+    if (ValidFP)
+      Opts.setFramePointer(FP);
+  }
 
   if (const Arg *A = Args.getLastArg(OPT_ftime_report, OPT_ftime_report_EQ)) {
     Opts.TimePasses = true;
@@ -976,13 +1103,69 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
     }
   }
 
+  Opts.DisableFree = Args.hasArg(OPT_disable_free);
+  Opts.DiscardValueNames = Args.hasArg(OPT_discard_value_names);
+  Opts.DisableTailCalls = Args.hasArg(OPT_mdisable_tail_calls);
+  Opts.NoEscapingBlockTailCalls =
+      Args.hasArg(OPT_fno_escaping_block_tail_calls);
+  Opts.FloatABI = std::string(Args.getLastArgValue(OPT_mfloat_abi));
+  Opts.LimitFloatPrecision =
+      std::string(Args.getLastArgValue(OPT_mlimit_float_precision));
   Opts.Reciprocals = Args.getAllArgValues(OPT_mrecip_EQ);
+  Opts.StrictFloatCastOverflow =
+      !Args.hasArg(OPT_fno_strict_float_cast_overflow);
+
+  Opts.NoZeroInitializedInBSS = Args.hasArg(OPT_fno_zero_initialized_in_bss);
+  Opts.NumRegisterParameters = getLastArgIntValue(Args, OPT_mregparm, 0, Diags);
+  Opts.NoExecStack = Args.hasArg(OPT_mno_exec_stack);
+  Opts.SmallDataLimit =
+      getLastArgIntValue(Args, OPT_msmall_data_limit, 0, Diags);
+  Opts.FatalWarnings = Args.hasArg(OPT_massembler_fatal_warnings);
+  Opts.NoWarn = Args.hasArg(OPT_massembler_no_warn);
+  Opts.EnableSegmentedStacks = Args.hasArg(OPT_split_stacks);
+  Opts.RelaxAll = Args.hasArg(OPT_mrelax_all);
+  Opts.IncrementalLinkerCompatible =
+      Args.hasArg(OPT_mincremental_linker_compatible);
+  Opts.PIECopyRelocations =
+      Args.hasArg(OPT_mpie_copy_relocations);
+  Opts.NoPLT = Args.hasArg(OPT_fno_plt);
+  Opts.SaveTempLabels = Args.hasArg(OPT_msave_temp_labels);
+  Opts.NoDwarfDirectoryAsm = Args.hasArg(OPT_fno_dwarf_directory_asm);
+  Opts.SoftFloat = Args.hasArg(OPT_msoft_float);
+  Opts.StrictEnums = Args.hasArg(OPT_fstrict_enums);
+  Opts.StrictReturn = !Args.hasArg(OPT_fno_strict_return);
+  Opts.StrictVTablePointers = Args.hasArg(OPT_fstrict_vtable_pointers);
+  Opts.ForceEmitVTables = Args.hasArg(OPT_fforce_emit_vtables);
+  Opts.UnwindTables = Args.hasArg(OPT_munwind_tables);
+  Opts.TrapFuncName = std::string(Args.getLastArgValue(OPT_ftrap_function_EQ));
+  Opts.UseInitArray = !Args.hasArg(OPT_fno_use_init_array);
+
+  Opts.BBSections =
+      std::string(Args.getLastArgValue(OPT_fbasic_block_sections_EQ, "none"));
 
   // Basic Block Sections implies Function Sections.
   Opts.FunctionSections =
       Args.hasArg(OPT_ffunction_sections) ||
       (Opts.BBSections != "none" && Opts.BBSections != "labels");
 
+  Opts.DataSections = Args.hasArg(OPT_fdata_sections);
+  Opts.StackSizeSection = Args.hasArg(OPT_fstack_size_section);
+  Opts.UniqueSectionNames = !Args.hasArg(OPT_fno_unique_section_names);
+  Opts.UniqueBasicBlockSectionNames =
+      Args.hasArg(OPT_funique_basic_block_section_names);
+  Opts.UniqueInternalLinkageNames =
+      Args.hasArg(OPT_funique_internal_linkage_names);
+
+  Opts.SplitMachineFunctions = Args.hasArg(OPT_fsplit_machine_functions);
+
+  Opts.MergeFunctions = Args.hasArg(OPT_fmerge_functions);
+
+  Opts.NoUseJumpTables = Args.hasArg(OPT_fno_jump_tables);
+
+  Opts.NullPointerIsValid = Args.hasArg(OPT_fno_delete_null_pointer_checks);
+
+  Opts.ProfileSampleAccurate = Args.hasArg(OPT_fprofile_sample_accurate);
+
   Opts.PrepareForLTO = Args.hasArg(OPT_flto, OPT_flto_EQ);
   Opts.PrepareForThinLTO = false;
   if (Arg *A = Args.getLastArg(OPT_flto_EQ)) {
@@ -992,6 +1175,8 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
     else if (S != "full")
       Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << S;
   }
+  Opts.LTOUnit = Args.hasFlag(OPT_flto_unit, OPT_fno_lto_unit, false);
+  Opts.EnableSplitLTOUnit = Args.hasArg(OPT_fsplit_lto_unit);
   if (Arg *A = Args.getLastArg(OPT_fthinlto_index_EQ)) {
     if (IK.getLanguage() != Language::LLVM_IR)
       Diags.Report(diag::err_drv_argument_only_allowed_with)
@@ -1005,6 +1190,9 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
             .Case("obj", FrontendOpts.OutputFile)
             .Default(llvm::sys::path::filename(FrontendOpts.OutputFile).str());
 
+  Opts.ThinLinkBitcodeFile =
+      std::string(Args.getLastArgValue(OPT_fthin_link_bitcode_EQ));
+
   // The memory profile runtime appends the pid to make this name more unique.
   const char *MemProfileBasename = "memprof.profraw";
   if (Args.hasArg(OPT_fmemory_profile_EQ)) {
@@ -1015,6 +1203,22 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
   } else if (Args.hasArg(OPT_fmemory_profile))
     Opts.MemoryProfileOutput = MemProfileBasename;
 
+  Opts.MSVolatile = Args.hasArg(OPT_fms_volatile);
+
+  Opts.VectorizeLoop = Args.hasArg(OPT_vectorize_loops);
+  Opts.VectorizeSLP = Args.hasArg(OPT_vectorize_slp);
+
+  Opts.PreferVectorWidth =
+      std::string(Args.getLastArgValue(OPT_mprefer_vector_width_EQ));
+
+  Opts.MainFileName = std::string(Args.getLastArgValue(OPT_main_file_name));
+  Opts.VerifyModule = !Args.hasArg(OPT_disable_llvm_verifier);
+
+  Opts.ControlFlowGuardNoChecks = Args.hasArg(OPT_cfguard_no_checks);
+  Opts.ControlFlowGuard = Args.hasArg(OPT_cfguard);
+
+  Opts.EmitGcovNotes = Args.hasArg(OPT_ftest_coverage);
+  Opts.EmitGcovArcs = Args.hasArg(OPT_fprofile_arcs);
   if (Opts.EmitGcovArcs || Opts.EmitGcovNotes) {
     Opts.CoverageDataFile =
         std::string(Args.getLastArgValue(OPT_coverage_data_file));
@@ -1035,6 +1239,22 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
       }
     }
   }
+  // Handle -fembed-bitcode option.
+  if (Arg *A = Args.getLastArg(OPT_fembed_bitcode_EQ)) {
+    StringRef Name = A->getValue();
+    unsigned Model = llvm::StringSwitch<unsigned>(Name)
+        .Case("off", CodeGenOptions::Embed_Off)
+        .Case("all", CodeGenOptions::Embed_All)
+        .Case("bitcode", CodeGenOptions::Embed_Bitcode)
+        .Case("marker", CodeGenOptions::Embed_Marker)
+        .Default(~0U);
+    if (Model == ~0U) {
+      Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Name;
+      Success = false;
+    } else
+      Opts.setEmbedBitcode(
+          static_cast<CodeGenOptions::EmbedBitcodeKind>(Model));
+  }
   // FIXME: For backend options that are not yet recorded as function
   // attributes in the IR, keep track of them so we can embed them in a
   // separate data section and use them when building the bitcode.
@@ -1056,6 +1276,15 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
     }
   }
 
+  Opts.PreserveVec3Type = Args.hasArg(OPT_fpreserve_vec3_type);
+  Opts.InstrumentFunctions = Args.hasArg(OPT_finstrument_functions);
+  Opts.InstrumentFunctionsAfterInlining =
+      Args.hasArg(OPT_finstrument_functions_after_inlining);
+  Opts.InstrumentFunctionEntryBare =
+      Args.hasArg(OPT_finstrument_function_entry_bare);
+
+  Opts.XRayInstructionThreshold =
+      getLastArgIntValue(Args, OPT_fxray_instruction_threshold_EQ, 200, Diags);
   Opts.XRayTotalFunctionGroups =
       getLastArgIntValue(Args, OPT_fxray_function_groups, 1, Diags);
   Opts.XRaySelectedFunctionGroup =
@@ -1070,6 +1299,16 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
       parseXRayInstrumentationBundle("-fxray-instrumentation-bundle=", A, Args,
                                      Diags, Opts.XRayInstrumentationBundle);
 
+  Opts.PatchableFunctionEntryCount =
+      getLastArgIntValue(Args, OPT_fpatchable_function_entry_EQ, 0, Diags);
+  Opts.PatchableFunctionEntryOffset = getLastArgIntValue(
+      Args, OPT_fpatchable_function_entry_offset_EQ, 0, Diags);
+  Opts.InstrumentForProfiling = Args.hasArg(OPT_pg);
+  Opts.CallFEntry = Args.hasArg(OPT_mfentry);
+  Opts.MNopMCount = Args.hasArg(OPT_mnop_mcount);
+  Opts.RecordMCount = Args.hasArg(OPT_mrecord_mcount);
+  Opts.PackedStack = Args.hasArg(OPT_mpacked_stack);
+
   if (const Arg *A = Args.getLastArg(OPT_fcf_protection_EQ)) {
     StringRef Name = A->getValue();
     if (Name == "full") {
@@ -1094,6 +1333,9 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
     Opts.setCompressDebugSections(DCT);
   }
 
+  Opts.RelaxELFRelocations = Args.hasArg(OPT_mrelax_relocations);
+  Opts.DebugCompilationDir =
+      std::string(Args.getLastArgValue(OPT_fdebug_compilation_dir));
   for (auto *A :
        Args.filtered(OPT_mlink_bitcode_file, OPT_mlink_builtin_bitcode)) {
     CodeGenOptions::BitcodeFileToLink F;
@@ -1107,10 +1349,63 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
     }
     Opts.LinkBitcodeFiles.push_back(F);
   }
+  Opts.SanitizeCoverageType =
+      getLastArgIntValue(Args, OPT_fsanitize_coverage_type, 0, Diags);
+  Opts.SanitizeCoverageIndirectCalls =
+      Args.hasArg(OPT_fsanitize_coverage_indirect_calls);
+  Opts.SanitizeCoverageTraceBB = Args.hasArg(OPT_fsanitize_coverage_trace_bb);
+  Opts.SanitizeCoverageTraceCmp = Args.hasArg(OPT_fsanitize_coverage_trace_cmp);
+  Opts.SanitizeCoverageTraceDiv = Args.hasArg(OPT_fsanitize_coverage_trace_div);
+  Opts.SanitizeCoverageTraceGep = Args.hasArg(OPT_fsanitize_coverage_trace_gep);
+  Opts.SanitizeCoverage8bitCounters =
+      Args.hasArg(OPT_fsanitize_coverage_8bit_counters);
+  Opts.SanitizeCoverageTracePC = Args.hasArg(OPT_fsanitize_coverage_trace_pc);
+  Opts.SanitizeCoverageTracePCGuard =
+      Args.hasArg(OPT_fsanitize_coverage_trace_pc_guard);
+  Opts.SanitizeCoverageNoPrune = Args.hasArg(OPT_fsanitize_coverage_no_prune);
+  Opts.SanitizeCoverageInline8bitCounters =
+      Args.hasArg(OPT_fsanitize_coverage_inline_8bit_counters);
+  Opts.SanitizeCoverageInlineBoolFlag =
+      Args.hasArg(OPT_fsanitize_coverage_inline_bool_flag);
+  Opts.SanitizeCoveragePCTable = Args.hasArg(OPT_fsanitize_coverage_pc_table);
+  Opts.SanitizeCoverageStackDepth =
+      Args.hasArg(OPT_fsanitize_coverage_stack_depth);
   Opts.SanitizeCoverageAllowlistFiles =
       Args.getAllArgValues(OPT_fsanitize_coverage_allowlist);
   Opts.SanitizeCoverageBlocklistFiles =
       Args.getAllArgValues(OPT_fsanitize_coverage_blocklist);
+  Opts.SanitizeMemoryTrackOrigins =
+      getLastArgIntValue(Args, OPT_fsanitize_memory_track_origins_EQ, 0, Diags);
+  Opts.SanitizeMemoryUseAfterDtor =
+      Args.hasFlag(OPT_fsanitize_memory_use_after_dtor,
+                   OPT_fno_sanitize_memory_use_after_dtor,
+                   false);
+  Opts.SanitizeMinimalRuntime = Args.hasArg(OPT_fsanitize_minimal_runtime);
+  Opts.SanitizeCfiCrossDso = Args.hasArg(OPT_fsanitize_cfi_cross_dso);
+  Opts.SanitizeCfiICallGeneralizePointers =
+      Args.hasArg(OPT_fsanitize_cfi_icall_generalize_pointers);
+  Opts.SanitizeCfiCanonicalJumpTables =
+      Args.hasArg(OPT_fsanitize_cfi_canonical_jump_tables);
+  Opts.SanitizeStats = Args.hasArg(OPT_fsanitize_stats);
+  if (Arg *A = Args.getLastArg(
+          OPT_fsanitize_address_poison_custom_array_cookie,
+          OPT_fno_sanitize_address_poison_custom_array_cookie)) {
+    Opts.SanitizeAddressPoisonCustomArrayCookie =
+        A->getOption().getID() ==
+        OPT_fsanitize_address_poison_custom_array_cookie;
+  }
+  if (Arg *A = Args.getLastArg(OPT_fsanitize_address_use_after_scope,
+                               OPT_fno_sanitize_address_use_after_scope)) {
+    Opts.SanitizeAddressUseAfterScope =
+        A->getOption().getID() == OPT_fsanitize_address_use_after_scope;
+  }
+  Opts.SanitizeAddressGlobalsDeadStripping =
+      Args.hasArg(OPT_fsanitize_address_globals_dead_stripping);
+  if (Arg *A = Args.getLastArg(OPT_fsanitize_address_use_odr_indicator,
+                               OPT_fno_sanitize_address_use_odr_indicator)) {
+    Opts.SanitizeAddressUseOdrIndicator =
+        A->getOption().getID() == OPT_fsanitize_address_use_odr_indicator;
+  }
   Opts.SSPBufferSize =
       getLastArgIntValue(Args, OPT_stack_protector_buffer_size, 8, Diags);
 
@@ -1128,6 +1423,44 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
       std::string(Args.getLastArgValue(OPT_mstack_protector_guard_reg_EQ,
                                        "none"));
 
+  Opts.StackRealignment = Args.hasArg(OPT_mstackrealign);
+  if (Arg *A = Args.getLastArg(OPT_mstack_alignment)) {
+    StringRef Val = A->getValue();
+    unsigned StackAlignment = Opts.StackAlignment;
+    Val.getAsInteger(10, StackAlignment);
+    Opts.StackAlignment = StackAlignment;
+  }
+
+  if (Arg *A = Args.getLastArg(OPT_mstack_probe_size)) {
+    StringRef Val = A->getValue();
+    unsigned StackProbeSize = Opts.StackProbeSize;
+    Val.getAsInteger(0, StackProbeSize);
+    Opts.StackProbeSize = StackProbeSize;
+  }
+
+  Opts.NoStackArgProbe = Args.hasArg(OPT_mno_stack_arg_probe);
+
+  Opts.StackClashProtector = Args.hasArg(OPT_fstack_clash_protection);
+
+  if (Arg *A = Args.getLastArg(OPT_fobjc_dispatch_method_EQ)) {
+    StringRef Name = A->getValue();
+    unsigned Method = llvm::StringSwitch<unsigned>(Name)
+      .Case("legacy", CodeGenOptions::Legacy)
+      .Case("non-legacy", CodeGenOptions::NonLegacy)
+      .Case("mixed", CodeGenOptions::Mixed)
+      .Default(~0U);
+    if (Method == ~0U) {
+      Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Name;
+      Success = false;
+    } else {
+      Opts.setObjCDispatchMethod(
+        static_cast<CodeGenOptions::ObjCDispatchMethodKind>(Method));
+    }
+  }
+
+
+  if (Args.hasArg(OPT_fno_objc_convert_messages_to_runtime_calls))
+    Opts.ObjCConvertMessagesToRuntimeCalls = 0;
 
   if (Args.getLastArg(OPT_femulated_tls) ||
       Args.getLastArg(OPT_fno_emulated_tls)) {
@@ -1136,6 +1469,24 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
         Args.hasFlag(OPT_femulated_tls, OPT_fno_emulated_tls, false);
   }
 
+  if (Arg *A = Args.getLastArg(OPT_ftlsmodel_EQ)) {
+    StringRef Name = A->getValue();
+    unsigned Model = llvm::StringSwitch<unsigned>(Name)
+        .Case("global-dynamic", CodeGenOptions::GeneralDynamicTLSModel)
+        .Case("local-dynamic", CodeGenOptions::LocalDynamicTLSModel)
+        .Case("initial-exec", CodeGenOptions::InitialExecTLSModel)
+        .Case("local-exec", CodeGenOptions::LocalExecTLSModel)
+        .Default(~0U);
+    if (Model == ~0U) {
+      Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Name;
+      Success = false;
+    } else {
+      Opts.setDefaultTLSModel(static_cast<CodeGenOptions::TLSModel>(Model));
+    }
+  }
+
+  Opts.TLSSize = getLastArgIntValue(Args, OPT_mtls_size_EQ, 0, Diags);
+
   if (Arg *A = Args.getLastArg(OPT_fdenormal_fp_math_EQ)) {
     StringRef Val = A->getValue();
     Opts.FPDenormalMode = llvm::parseDenormalFPAttribute(Val);
@@ -1196,6 +1547,7 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
   Opts.LinkerOptions = Args.getAllArgValues(OPT_linker_option);
   bool NeedLocTracking = false;
 
+  Opts.OptRecordFile = std::string(Args.getLastArgValue(OPT_opt_record_file));
   if (!Opts.OptRecordFile.empty())
     NeedLocTracking = true;
 
@@ -1227,6 +1579,8 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
     NeedLocTracking = true;
   }
 
+  Opts.DiagnosticsWithHotness =
+      Args.hasArg(options::OPT_fdiagnostics_show_hotness);
   bool UsingSampleProfile = !Opts.SampleProfileFile.empty();
   bool UsingProfile = UsingSampleProfile ||
       (Opts.getProfileUse() != CodeGenOptions::ProfileNone);
@@ -1278,12 +1632,35 @@ static bool ParseCodeGenArgs(CodeGenOptions &Opts, ArgList &Args, InputKind IK,
                       Args.getAllArgValues(OPT_fsanitize_trap_EQ), Diags,
                       Opts.SanitizeTrap);
 
+  Opts.CudaGpuBinaryFileName =
+      std::string(Args.getLastArgValue(OPT_fcuda_include_gpubinary));
+
+  Opts.Backchain = Args.hasArg(OPT_mbackchain);
+
+  Opts.EmitCheckPathComponentsToStrip = getLastArgIntValue(
+      Args, OPT_fsanitize_undefined_strip_path_components_EQ, 0, Diags);
+
   Opts.EmitVersionIdentMetadata = Args.hasFlag(OPT_Qy, OPT_Qn, true);
 
+  Opts.Addrsig = Args.hasArg(OPT_faddrsig);
+
+  Opts.KeepStaticConsts = Args.hasArg(OPT_fkeep_static_consts);
+
+  Opts.SpeculativeLoadHardening = Args.hasArg(OPT_mspeculative_load_hardening);
+
   Opts.DefaultFunctionAttrs = Args.getAllArgValues(OPT_default_function_attr);
 
   Opts.PassPlugins = Args.getAllArgValues(OPT_fpass_plugin_EQ);
 
+  Opts.SymbolPartition =
+      std::string(Args.getLastArgValue(OPT_fsymbol_partition_EQ));
+
+  Opts.ForceAAPCSBitfieldLoad = Args.hasArg(OPT_ForceAAPCSBitfieldLoad);
+  Opts.AAPCSBitfieldWidth =
+      Args.hasFlag(OPT_AAPCSBitfieldWidth, OPT_ForceNoAAPCSBitfieldWidth, true);
+
+  Opts.PassByValueIsNoAlias = Args.hasArg(OPT_fpass_by_value_is_noalias);
+
   return Success;
 }
 
@@ -2247,6 +2624,9 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
     }
   }
 
+  if (Args.hasArg(OPT_fno_dllexport_inlines))
+    Opts.DllExportInlines = false;
+
   if (const Arg *A = Args.getLastArg(OPT_fcf_protection_EQ)) {
     StringRef Name = A->getValue();
     if (Name == "full" || Name == "branch") {
@@ -2275,6 +2655,7 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
       LangStd = OpenCLLangStd;
   }
 
+  Opts.SYCL = Args.hasArg(options::OPT_fsycl);
   Opts.SYCLIsDevice = Opts.SYCL && Args.hasArg(options::OPT_fsycl_is_device);
   if (Opts.SYCL) {
     Opts.SYCLIsDevice = Args.hasArg(options::OPT_fsycl_is_device);
@@ -2311,6 +2692,8 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
   }
 
   Opts.DeclareSPIRVBuiltins = Args.hasArg(OPT_fdeclare_spirv_builtins);
+  Opts.IncludeDefaultHeader = Args.hasArg(OPT_finclude_default_header);
+  Opts.DeclareOpenCLBuiltins = Args.hasArg(OPT_fdeclare_opencl_builtins);
 
   llvm::Triple T(TargetOpts.Triple);
   CompilerInvocation::setLangDefaults(Opts, IK, T, PPOpts, LangStd);
@@ -2338,9 +2721,25 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
   if (Args.hasArg(OPT_fno_operator_names))
     Opts.CXXOperatorNames = 0;
 
+  if (Args.hasArg(OPT_fcuda_is_device))
+    Opts.CUDAIsDevice = 1;
+
+  if (Args.hasArg(OPT_fcuda_allow_variadic_functions))
+    Opts.CUDAAllowVariadicFunctions = 1;
+
+  if (Args.hasArg(OPT_fno_cuda_host_device_constexpr))
+    Opts.CUDAHostDeviceConstexpr = 0;
+
+  if (Args.hasArg(OPT_fgpu_exclude_wrong_side_overloads))
+    Opts.GPUExcludeWrongSideOverloads = 1;
+
+  if (Args.hasArg(OPT_fgpu_defer_diag))
+    Opts.GPUDeferDiag = 1;
+
   if (Opts.CUDAIsDevice && Args.hasArg(OPT_fcuda_approx_transcendentals))
     Opts.CUDADeviceApproxTranscendentals = 1;
 
+  Opts.GPURelocatableDeviceCode = Args.hasArg(OPT_fgpu_rdc);
   if (Args.hasArg(OPT_fgpu_allow_device_init)) {
     if (Opts.HIP)
       Opts.GPUAllowDeviceInit = 1;
@@ -2348,6 +2747,7 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
       Diags.Report(diag::warn_ignored_hip_only_option)
           << Args.getLastArg(OPT_fgpu_allow_device_init)->getAsString(Args);
   }
+  Opts.HIPUseNewLaunchAPI = Args.hasArg(OPT_fhip_new_launch_api);
   if (Opts.HIP)
     Opts.GPUMaxThreadsPerBlock = getLastArgIntValue(
         Args, OPT_gpu_max_threads_per_block_EQ, Opts.GPUMaxThreadsPerBlock);
@@ -2397,6 +2797,9 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
       Opts.ObjCWeak = Opts.ObjCWeakRuntime;
     }
 
+    if (Args.hasArg(OPT_fno_objc_infer_related_result_type))
+      Opts.ObjCInferRelatedResultType = 0;
+
     if (Args.hasArg(OPT_fobjc_subscripting_legacy_runtime))
       Opts.ObjCSubscriptingLegacyRuntime =
         (Opts.ObjCRuntime.getKind() == ObjCRuntime::FragileMacOSX);
@@ -2425,6 +2828,42 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
       Opts.GNUInline = 1;
   }
 
+  if (Args.hasArg(OPT_fapple_kext)) {
+    if (!Opts.CPlusPlus)
+      Diags.Report(diag::warn_c_kext);
+    else
+      Opts.AppleKext = 1;
+  }
+
+  if (Args.hasArg(OPT_print_ivar_layout))
+    Opts.ObjCGCBitmapPrint = 1;
+
+  if (Args.hasArg(OPT_fno_constant_cfstrings))
+    Opts.NoConstantCFStrings = 1;
+  if (const auto *A = Args.getLastArg(OPT_fcf_runtime_abi_EQ))
+    Opts.CFRuntime =
+        llvm::StringSwitch<LangOptions::CoreFoundationABI>(A->getValue())
+            .Cases("unspecified", "standalone", "objc",
+                   LangOptions::CoreFoundationABI::ObjectiveC)
+            .Cases("swift", "swift-5.0",
+                   LangOptions::CoreFoundationABI::Swift5_0)
+            .Case("swift-4.2", LangOptions::CoreFoundationABI::Swift4_2)
+            .Case("swift-4.1", LangOptions::CoreFoundationABI::Swift4_1)
+            .Default(LangOptions::CoreFoundationABI::ObjectiveC);
+
+  if (Args.hasArg(OPT_fzvector))
+    Opts.ZVector = 1;
+
+  if (Args.hasArg(OPT_pthread))
+    Opts.POSIXThreads = 1;
+
+  // The value-visibility mode defaults to "default".
+  if (Arg *visOpt = Args.getLastArg(OPT_fvisibility)) {
+    Opts.setValueVisibilityMode(parseVisibility(visOpt, Args, Diags));
+  } else {
+    Opts.setValueVisibilityMode(DefaultVisibility);
+  }
+
   // The type-visibility mode defaults to the value-visibility mode.
   if (Arg *typeVisOpt = Args.getLastArg(OPT_ftype_visibility)) {
     Opts.setTypeVisibilityMode(parseVisibility(typeVisOpt, Args, Diags));
@@ -2432,6 +2871,18 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
     Opts.setTypeVisibilityMode(Opts.getValueVisibilityMode());
   }
 
+  if (Args.hasArg(OPT_fvisibility_inlines_hidden))
+    Opts.InlineVisibilityHidden = 1;
+
+  if (Args.hasArg(OPT_fvisibility_inlines_hidden_static_local_var))
+    Opts.VisibilityInlinesHiddenStaticLocalVar = 1;
+
+  if (Args.hasArg(OPT_fvisibility_global_new_delete_hidden))
+    Opts.GlobalAllocationFunctionVisibilityHidden = 1;
+
+  if (Args.hasArg(OPT_fapply_global_visibility_to_externs))
+    Opts.SetVisibilityForExternDecls = 1;
+
   if (Args.hasArg(OPT_fvisibility_from_dllstorageclass)) {
     Opts.VisibilityFromDLLStorageClass = 1;
 
@@ -2473,6 +2924,7 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
   else if (Args.hasArg(OPT_fwrapv))
     Opts.setSignedOverflowBehavior(LangOptions::SOB_Defined);
 
+  Opts.MSVCCompat = Args.hasArg(OPT_fms_compatibility);
   Opts.MicrosoftExt = Opts.MSVCCompat || Args.hasArg(OPT_fms_extensions);
   Opts.AsmBlocks = Args.hasArg(OPT_fasm_blocks) || Opts.MicrosoftExt;
   Opts.MSCompatibilityVersion = 0;
@@ -2498,6 +2950,31 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
   Opts.DollarIdents = Args.hasFlag(OPT_fdollars_in_identifiers,
                                    OPT_fno_dollars_in_identifiers,
                                    Opts.DollarIdents);
+  Opts.PascalStrings = Args.hasArg(OPT_fpascal_strings);
+  Opts.setVtorDispMode(
+      MSVtorDispMode(getLastArgIntValue(Args, OPT_vtordisp_mode_EQ, 1, Diags)));
+  Opts.Borland = Args.hasArg(OPT_fborland_extensions);
+  Opts.WritableStrings = Args.hasArg(OPT_fwritable_strings);
+  Opts.ConstStrings = Args.hasFlag(OPT_fconst_strings, OPT_fno_const_strings,
+                                   Opts.ConstStrings);
+  if (Arg *A = Args.getLastArg(OPT_flax_vector_conversions_EQ)) {
+    using LaxKind = LangOptions::LaxVectorConversionKind;
+    if (auto Kind = llvm::StringSwitch<Optional<LaxKind>>(A->getValue())
+                        .Case("none", LaxKind::None)
+                        .Case("integer", LaxKind::Integer)
+                        .Case("all", LaxKind::All)
+                        .Default(llvm::None))
+      Opts.setLaxVectorConversions(*Kind);
+    else
+      Diags.Report(diag::err_drv_invalid_value)
+          << A->getAsString(Args) << A->getValue();
+  }
+  if (Args.hasArg(OPT_fno_threadsafe_statics))
+    Opts.ThreadsafeStatics = 0;
+  Opts.Exceptions = Args.hasArg(OPT_fexceptions);
+  Opts.IgnoreExceptions = Args.hasArg(OPT_fignore_exceptions);
+  Opts.ObjCExceptions = Args.hasArg(OPT_fobjc_exceptions);
+  Opts.CXXExceptions = Args.hasArg(OPT_fcxx_exceptions);
 
   // -ffixed-point
   Opts.FixedPoint =
@@ -2509,10 +2986,14 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
                    /*Default=*/false) &&
       Opts.FixedPoint;
 
+  Opts.ExternCNoUnwind = Args.hasArg(OPT_fexternc_nounwind);
+  Opts.TraditionalCPP = Args.hasArg(OPT_traditional_cpp);
+
   Opts.RTTI = Opts.CPlusPlus && !Args.hasArg(OPT_fno_rtti);
   Opts.RTTIData = Opts.RTTI && !Args.hasArg(OPT_fno_rtti_data);
   Opts.Blocks = Args.hasArg(OPT_fblocks) || (Opts.OpenCL
     && Opts.OpenCLVersion == 200);
+  Opts.BlocksRuntimeOptional = Args.hasArg(OPT_fblocks_runtime_optional);
   Opts.Coroutines = Opts.CPlusPlus20 || Args.hasArg(OPT_fcoroutines_ts);
 
   Opts.ConvergentFunctions = Opts.OpenCL || (Opts.CUDA && Opts.CUDAIsDevice) ||
@@ -2525,8 +3006,10 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
                    Opts.DoubleSquareBracketAttributes);
 
   Opts.CPlusPlusModules = Opts.CPlusPlus20;
+  Opts.ModulesTS = Args.hasArg(OPT_fmodules_ts);
   Opts.Modules =
       Args.hasArg(OPT_fmodules) || Opts.ModulesTS || Opts.CPlusPlusModules;
+  Opts.ModulesStrictDeclUse = Args.hasArg(OPT_fmodules_strict_decluse);
   Opts.ModulesDeclUse =
       Args.hasArg(OPT_fmodules_decluse) || Opts.ModulesStrictDeclUse;
   // FIXME: We only need this in C++ modules / Modules TS if we might textually
@@ -2534,32 +3017,113 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
   Opts.ModulesLocalVisibility =
       Args.hasArg(OPT_fmodules_local_submodule_visibility) || Opts.ModulesTS ||
       Opts.CPlusPlusModules;
+  Opts.ModulesCodegen = Args.hasArg(OPT_fmodules_codegen);
+  Opts.ModulesDebugInfo = Args.hasArg(OPT_fmodules_debuginfo);
   Opts.ModulesSearchAll = Opts.Modules &&
     !Args.hasArg(OPT_fno_modules_search_all) &&
     Args.hasArg(OPT_fmodules_search_all);
+  Opts.ModulesErrorRecovery = !Args.hasArg(OPT_fno_modules_error_recovery);
+  Opts.ImplicitModules = !Args.hasArg(OPT_fno_implicit_modules);
   Opts.CharIsSigned = Opts.OpenCL || !Args.hasArg(OPT_fno_signed_char);
   Opts.WChar = Opts.CPlusPlus && !Args.hasArg(OPT_fno_wchar);
   Opts.Char8 = Args.hasFlag(OPT_fchar8__t, OPT_fno_char8__t, Opts.CPlusPlus20);
+  if (const Arg *A = Args.getLastArg(OPT_fwchar_type_EQ)) {
+    Opts.WCharSize = llvm::StringSwitch<unsigned>(A->getValue())
+                         .Case("char", 1)
+                         .Case("short", 2)
+                         .Case("int", 4)
+                         .Default(0);
+    if (Opts.WCharSize == 0)
+      Diags.Report(diag::err_fe_invalid_wchar_type) << A->getValue();
+  }
+  Opts.WCharIsSigned = Args.hasFlag(OPT_fsigned_wchar, OPT_fno_signed_wchar, true);
+  Opts.ShortEnums = Args.hasArg(OPT_fshort_enums);
+  Opts.Freestanding = Args.hasArg(OPT_ffreestanding);
   Opts.NoBuiltin = Args.hasArg(OPT_fno_builtin) || Opts.Freestanding;
   if (!Opts.NoBuiltin)
     getAllNoBuiltinFuncValues(Args, Opts.NoBuiltinFuncs);
+  Opts.NoMathBuiltin = Args.hasArg(OPT_fno_math_builtin);
+  Opts.RelaxedTemplateTemplateArgs =
+      Args.hasArg(OPT_frelaxed_template_template_args);
+  Opts.SizedDeallocation = Args.hasArg(OPT_fsized_deallocation);
   Opts.AlignedAllocation =
       Args.hasFlag(OPT_faligned_allocation, OPT_fno_aligned_allocation,
                    Opts.AlignedAllocation);
   Opts.AlignedAllocationUnavailable =
       Opts.AlignedAllocation && Args.hasArg(OPT_aligned_alloc_unavailable);
+  Opts.NewAlignOverride =
+      getLastArgIntValue(Args, OPT_fnew_alignment_EQ, 0, Diags);
+  if (Opts.NewAlignOverride && !llvm::isPowerOf2_32(Opts.NewAlignOverride)) {
+    Arg *A = Args.getLastArg(OPT_fnew_alignment_EQ);
+    Diags.Report(diag::err_fe_invalid_alignment) << A->getAsString(Args)
+                                                 << A->getValue();
+    Opts.NewAlignOverride = 0;
+  }
+  Opts.ConceptSatisfactionCaching =
+      !Args.hasArg(OPT_fno_concept_satisfaction_caching);
   if (Args.hasArg(OPT_fconcepts_ts))
     Diags.Report(diag::warn_fe_concepts_ts_flag);
+  Opts.RecoveryAST = Args.hasFlag(OPT_frecovery_ast, OPT_fno_recovery_ast);
+  Opts.RecoveryASTType =
+      Args.hasFlag(OPT_frecovery_ast_type, OPT_fno_recovery_ast_type);
+  Opts.HeinousExtensions = Args.hasArg(OPT_fheinous_gnu_extensions);
+  Opts.AccessControl = !Args.hasArg(OPT_fno_access_control);
+  Opts.ElideConstructors = !Args.hasArg(OPT_fno_elide_constructors);
   Opts.MathErrno = !Opts.OpenCL && Args.hasArg(OPT_fmath_errno);
+  Opts.InstantiationDepth =
+      getLastArgIntValue(Args, OPT_ftemplate_depth, 1024, Diags);
+  Opts.ArrowDepth =
+      getLastArgIntValue(Args, OPT_foperator_arrow_depth, 256, Diags);
+  Opts.ConstexprCallDepth =
+      getLastArgIntValue(Args, OPT_fconstexpr_depth, 512, Diags);
+  Opts.ConstexprStepLimit =
+      getLastArgIntValue(Args, OPT_fconstexpr_steps, 1048576, Diags);
+  Opts.EnableNewConstInterp =
+      Args.hasArg(OPT_fexperimental_new_constant_interpreter);
+  Opts.BracketDepth = getLastArgIntValue(Args, OPT_fbracket_depth, 256, Diags);
+  Opts.DelayedTemplateParsing = Args.hasArg(OPT_fdelayed_template_parsing);
+  Opts.NumLargeByValueCopy =
+      getLastArgIntValue(Args, OPT_Wlarge_by_value_copy_EQ, 0, Diags);
+  Opts.MSBitfields = Args.hasArg(OPT_mms_bitfields);
+  Opts.ObjCConstantStringClass =
+      std::string(Args.getLastArgValue(OPT_fconstant_string_class));
+  Opts.ObjCDefaultSynthProperties =
+    !Args.hasArg(OPT_disable_objc_default_synthesize_properties);
+  Opts.EncodeExtendedBlockSig =
+    Args.hasArg(OPT_fencode_extended_block_signature);
+  Opts.EmitAllDecls = Args.hasArg(OPT_femit_all_decls);
+  Opts.PackStruct = getLastArgIntValue(Args, OPT_fpack_struct_EQ, 0, Diags);
+  Opts.MaxTypeAlign = getLastArgIntValue(Args, OPT_fmax_type_align_EQ, 0, Diags);
+  Opts.AlignDouble = Args.hasArg(OPT_malign_double);
+  Opts.DoubleSize = getLastArgIntValue(Args, OPT_mdouble_EQ, 0, Diags);
   Opts.LongDoubleSize = Args.hasArg(OPT_mlong_double_128)
                             ? 128
                             : Args.hasArg(OPT_mlong_double_64) ? 64 : 0;
+  Opts.PPCIEEELongDouble = Args.hasArg(OPT_mabi_EQ_ieeelongdouble);
   Opts.EnableAIXExtendedAltivecABI = Args.hasArg(OPT_mabi_EQ_vec_extabi);
   Opts.PICLevel = getLastArgIntValue(Args, OPT_pic_level, 0, Diags);
+  Opts.ROPI = Args.hasArg(OPT_fropi);
+  Opts.RWPI = Args.hasArg(OPT_frwpi);
+  Opts.PIE = Args.hasArg(OPT_pic_is_pie);
+  Opts.Static = Args.hasArg(OPT_static_define);
+  Opts.DumpRecordLayoutsSimple = Args.hasArg(OPT_fdump_record_layouts_simple);
   Opts.DumpRecordLayouts = Opts.DumpRecordLayoutsSimple
                         || Args.hasArg(OPT_fdump_record_layouts);
+  Opts.DumpVTableLayouts = Args.hasArg(OPT_fdump_vtable_layouts);
+  Opts.SpellChecking = !Args.hasArg(OPT_fno_spell_checking);
+  Opts.NoBitFieldTypeAlign = Args.hasArg(OPT_fno_bitfield_type_align);
   if (Opts.FastRelaxedMath)
     Opts.setDefaultFPContractMode(LangOptions::FPM_Fast);
+  Opts.HexagonQdsp6Compat = Args.hasArg(OPT_mqdsp6_compat);
+  Opts.FakeAddressSpaceMap = Args.hasArg(OPT_ffake_address_space_map);
+  Opts.ParseUnknownAnytype = Args.hasArg(OPT_funknown_anytype);
+  Opts.DebuggerSupport = Args.hasArg(OPT_fdebugger_support);
+  Opts.DebuggerCastResultToId = Args.hasArg(OPT_fdebugger_cast_result_to_id);
+  Opts.DebuggerObjCLiteral = Args.hasArg(OPT_fdebugger_objc_literal);
+  Opts.ApplePragmaPack = Args.hasArg(OPT_fapple_pragma_pack);
+  Opts.ModuleName = std::string(Args.getLastArgValue(OPT_fmodule_name_EQ));
+  Opts.CurrentModule = Opts.ModuleName;
+  Opts.AppExt = Args.hasArg(OPT_fapplication_extension);
   Opts.ModuleFeatures = Args.getAllArgValues(OPT_fmodule_feature);
   llvm::sort(Opts.ModuleFeatures);
   Opts.NativeHalfType |= Args.hasArg(OPT_fnative_half_type);
@@ -2568,6 +3132,8 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
   // is enabled.
   Opts.HalfArgsAndReturns = Args.hasArg(OPT_fallow_half_arguments_and_returns)
                             | Opts.NativeHalfArgsAndReturns;
+  Opts.GNUAsm = !Args.hasArg(OPT_fno_gnu_inline_asm);
+  Opts.Cmse = Args.hasArg(OPT_mcmse); // Armv8-M Security Extensions
 
   Opts.ArmSveVectorBits =
       getLastArgIntValue(Args, options::OPT_msve_vector_bits_EQ, 0, Diags);
@@ -2584,6 +3150,80 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
       Args.hasFlag(OPT_fdeclspec, OPT_fno_declspec,
                    (Opts.MicrosoftExt || Opts.Borland || Opts.CUDA));
 
+  if (Arg *A = Args.getLastArg(OPT_faddress_space_map_mangling_EQ)) {
+    switch (llvm::StringSwitch<unsigned>(A->getValue())
+      .Case("target", LangOptions::ASMM_Target)
+      .Case("no", LangOptions::ASMM_Off)
+      .Case("yes", LangOptions::ASMM_On)
+      .Default(255)) {
+    default:
+      Diags.Report(diag::err_drv_invalid_value)
+        << "-faddress-space-map-mangling=" << A->getValue();
+      break;
+    case LangOptions::ASMM_Target:
+      Opts.setAddressSpaceMapMangling(LangOptions::ASMM_Target);
+      break;
+    case LangOptions::ASMM_On:
+      Opts.setAddressSpaceMapMangling(LangOptions::ASMM_On);
+      break;
+    case LangOptions::ASMM_Off:
+      Opts.setAddressSpaceMapMangling(LangOptions::ASMM_Off);
+      break;
+    }
+  }
+
+  if (Arg *A = Args.getLastArg(OPT_fms_memptr_rep_EQ)) {
+    LangOptions::PragmaMSPointersToMembersKind InheritanceModel =
+        llvm::StringSwitch<LangOptions::PragmaMSPointersToMembersKind>(
+            A->getValue())
+            .Case("single",
+                  LangOptions::PPTMK_FullGeneralitySingleInheritance)
+            .Case("multiple",
+                  LangOptions::PPTMK_FullGeneralityMultipleInheritance)
+            .Case("virtual",
+                  LangOptions::PPTMK_FullGeneralityVirtualInheritance)
+            .Default(LangOptions::PPTMK_BestCase);
+    if (InheritanceModel == LangOptions::PPTMK_BestCase)
+      Diags.Report(diag::err_drv_invalid_value)
+          << "-fms-memptr-rep=" << A->getValue();
+
+    Opts.setMSPointerToMemberRepresentationMethod(InheritanceModel);
+  }
+
+  // Check for MS default calling conventions being specified.
+  if (Arg *A = Args.getLastArg(OPT_fdefault_calling_conv_EQ)) {
+    LangOptions::DefaultCallingConvention DefaultCC =
+        llvm::StringSwitch<LangOptions::DefaultCallingConvention>(A->getValue())
+            .Case("cdecl", LangOptions::DCC_CDecl)
+            .Case("fastcall", LangOptions::DCC_FastCall)
+            .Case("stdcall", LangOptions::DCC_StdCall)
+            .Case("vectorcall", LangOptions::DCC_VectorCall)
+            .Case("regcall", LangOptions::DCC_RegCall)
+            .Default(LangOptions::DCC_None);
+    if (DefaultCC == LangOptions::DCC_None)
+      Diags.Report(diag::err_drv_invalid_value)
+          << "-fdefault-calling-conv=" << A->getValue();
+
+    llvm::Triple T(TargetOpts.Triple);
+    llvm::Triple::ArchType Arch = T.getArch();
+    bool emitError = (DefaultCC == LangOptions::DCC_FastCall ||
+                      DefaultCC == LangOptions::DCC_StdCall) &&
+                     Arch != llvm::Triple::x86;
+    emitError |= (DefaultCC == LangOptions::DCC_VectorCall ||
+                  DefaultCC == LangOptions::DCC_RegCall) &&
+                 !T.isX86();
+    if (emitError)
+      Diags.Report(diag::err_drv_argument_not_allowed_with)
+          << A->getSpelling() << T.getTriple();
+    else
+      Opts.setDefaultCallingConv(DefaultCC);
+  }
+
+  Opts.SemanticInterposition = Args.hasArg(OPT_fsemantic_interposition);
+  // An explicit -fno-semantic-interposition infers dso_local.
+  Opts.ExplicitNoSemanticInterposition =
+      Args.hasArg(OPT_fno_semantic_interposition);
+
   // -mrtd option
   if (Arg *A = Args.getLastArg(OPT_mrtd)) {
     if (Opts.getDefaultCallingConv() != LangOptions::DCC_None)
@@ -2599,6 +3239,8 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
     }
   }
 
+  // Check if -fopenmp is specified and set default version to 5.0.
+  Opts.OpenMP = Args.hasArg(options::OPT_fopenmp) ? 50 : 0;
   // Check if -fopenmp-simd is specified.
   bool IsSimdSpecified =
       Args.hasFlag(options::OPT_fopenmp_simd, options::OPT_fno_openmp_simd,
@@ -2653,6 +3295,11 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
         Opts.OpenMPCUDAReductionBufNum, Diags);
   }
 
+  // Prevent auto-widening the representation of loop counters during an
+  // OpenMP collapse clause.
+  Opts.OpenMPOptimisticCollapse =
+      Args.hasArg(options::OPT_fopenmp_optimistic_collapse) ? 1 : 0;
+
   // Get the OpenMP target triples if any.
   if (Arg *A = Args.getLastArg(options::OPT_fopenmp_targets_EQ)) {
     enum ArchPtrSize { Arch16Bit, Arch32Bit, Arch64Bit };
@@ -2746,6 +3393,12 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
       Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Val;
   }
 
+  auto FPRM = llvm::RoundingMode::NearestTiesToEven;
+  if (Args.hasArg(OPT_frounding_math)) {
+    FPRM = llvm::RoundingMode::Dynamic;
+  }
+  Opts.setFPRoundingMode(FPRM);
+
   if (Args.hasArg(OPT_ftrapping_math)) {
     Opts.setFPExceptionMode(LangOptions::FPE_Strict);
   }
@@ -2768,9 +3421,45 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
   }
   Opts.setFPExceptionMode(FPEB);
 
+  Opts.RetainCommentsFromSystemHeaders =
+      Args.hasArg(OPT_fretain_comments_from_system_headers);
+
+  unsigned SSP = getLastArgIntValue(Args, OPT_stack_protector, 0, Diags);
+  switch (SSP) {
+  default:
+    Diags.Report(diag::err_drv_invalid_value)
+      << Args.getLastArg(OPT_stack_protector)->getAsString(Args) << SSP;
+    break;
+  case 0: Opts.setStackProtector(LangOptions::SSPOff); break;
+  case 1: Opts.setStackProtector(LangOptions::SSPOn);  break;
+  case 2: Opts.setStackProtector(LangOptions::SSPStrong); break;
+  case 3: Opts.setStackProtector(LangOptions::SSPReq); break;
+  }
+
+  if (Arg *A = Args.getLastArg(OPT_ftrivial_auto_var_init)) {
+    StringRef Val = A->getValue();
+    if (Val == "uninitialized")
+      Opts.setTrivialAutoVarInit(
+          LangOptions::TrivialAutoVarInitKind::Uninitialized);
+    else if (Val == "zero")
+      Opts.setTrivialAutoVarInit(LangOptions::TrivialAutoVarInitKind::Zero);
+    else if (Val == "pattern")
+      Opts.setTrivialAutoVarInit(LangOptions::TrivialAutoVarInitKind::Pattern);
+    else
+      Diags.Report(diag::err_drv_invalid_value) << A->getAsString(Args) << Val;
+  }
+
+  if (Arg *A = Args.getLastArg(OPT_ftrivial_auto_var_init_stop_after)) {
+    int Val = std::stoi(A->getValue());
+    Opts.TrivialAutoVarInitStopAfter = Val;
+  }
+
   // Parse -fsanitize= arguments.
   parseSanitizerKinds("-fsanitize=", Args.getAllArgValues(OPT_fsanitize_EQ),
                       Diags, Opts.Sanitize);
+  // -fsanitize-address-field-padding=N has to be a LangOpt, parse it here.
+  Opts.SanitizeAddressFieldPadding =
+      getLastArgIntValue(Args, OPT_fsanitize_address_field_padding, 0, Diags);
   Opts.SanitizerBlacklistFiles = Args.getAllArgValues(OPT_fsanitize_blacklist);
   std::vector<std::string> systemBlacklists =
       Args.getAllArgValues(OPT_fsanitize_system_blacklist);
@@ -2785,6 +3474,14 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
       Args.getAllArgValues(OPT_fxray_never_instrument);
   Opts.XRayAttrListFiles = Args.getAllArgValues(OPT_fxray_attr_list);
 
+  // -fforce-emit-vtables
+  Opts.ForceEmitVTables = Args.hasArg(OPT_fforce_emit_vtables);
+
+  // -fallow-editor-placeholders
+  Opts.AllowEditorPlaceholders = Args.hasArg(OPT_fallow_editor_placeholders);
+
+  Opts.RegisterStaticDestructors = !Args.hasArg(OPT_fno_cxx_static_destructors);
+
   if (Arg *A = Args.getLastArg(OPT_fclang_abi_compat_EQ)) {
     Opts.setClangABICompat(LangOptions::ClangABI::Latest);
 
@@ -2820,6 +3517,14 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
     }
   }
 
+  Opts.CompleteMemberPointers = Args.hasArg(OPT_fcomplete_member_pointers);
+  Opts.BuildingPCHWithObjectFile = Args.hasArg(OPT_building_pch_with_obj);
+  Opts.PCHInstantiateTemplates = Args.hasArg(OPT_fpch_instantiate_templates);
+
+  Opts.MatrixTypes = Args.hasArg(OPT_fenable_matrix);
+
+  Opts.MaxTokens = getLastArgIntValue(Args, OPT_fmax_tokens_EQ, 0, Diags);
+
   if (Arg *A = Args.getLastArg(OPT_msign_return_address_EQ)) {
     StringRef SignScope = A->getValue();
 
@@ -2852,6 +3557,17 @@ static void ParseLangArgs(LangOptions &Opts, ArgList &Args, InputKind IK,
     }
   }
 
+  Opts.BranchTargetEnforcement = Args.hasArg(OPT_mbranch_target_enforce);
+  Opts.SpeculativeLoadHardening = Args.hasArg(OPT_mspeculative_load_hardening);
+
+  Opts.CompatibilityQualifiedIdBlockParamTypeChecking =
+      Args.hasArg(OPT_fcompatibility_qualified_id_block_param_type_checking);
+
+  Opts.RelativeCXXABIVTables =
+      Args.hasFlag(OPT_fexperimental_relative_cxx_abi_vtables,
+                   OPT_fno_experimental_relative_cxx_abi_vtables,
+                   /*default=*/false);
+
   std::string ThreadModel =
       std::string(Args.getLastArgValue(OPT_mthread_model, "posix"));
   if (ThreadModel != "posix" && ThreadModel != "single")
@@ -3099,6 +3815,7 @@ bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,
     // PIClevel and PIELevel are needed during code generation and this should be
     // set regardless of the input type.
     LangOpts.PICLevel = getLastArgIntValue(Args, OPT_pic_level, 0, Diags);
+    LangOpts.PIE = Args.hasArg(OPT_pic_is_pie);
     parseSanitizerKinds("-fsanitize=", Args.getAllArgValues(OPT_fsanitize_EQ),
                         Diags, LangOpts.Sanitize);
   } else {
@@ -3116,6 +3833,9 @@ bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,
     }
   }
 
+  LangOpts.FunctionAlignment =
+      getLastArgIntValue(Args, OPT_function_alignment, 0, Diags);
+
   if (LangOpts.CUDA) {
     // During CUDA device-side compilation, the aux triple is the
     // triple used for host compilation.
@@ -3160,7 +3880,7 @@ bool CompilerInvocation::CreateFromArgs(CompilerInvocation &Res,
   Res.getCodeGenOpts().Argv0 = Argv0;
   Res.getCodeGenOpts().CommandLineArgs = CommandLineArgs;
 
-  FixupInvocation(Res, Diags, Args);
+  FixupInvocation(Res, Diags);
 
   return Success;
 }
@@ -3293,8 +4013,7 @@ void CompilerInvocation::generateCC1CommandLine(
           (Extracted !=                                                        \
            static_cast<decltype(this->KEYPATH)>(                               \
                (IMPLIED_CHECK) ? (IMPLIED_VALUE) : (DEFAULT_VALUE))))          \
-        DENORMALIZER(Args, SPELLING, SA, Option::KIND##Class, TABLE_INDEX,     \
-                     Extracted);                                               \
+        DENORMALIZER(Args, SPELLING, SA, TABLE_INDEX, Extracted);              \
     }(EXTRACTOR(this->KEYPATH));                                               \
   }
 
diff --git a/clang/lib/Headers/cuda_wrappers/algorithm b/clang/lib/Headers/cuda_wrappers/algorithm
index 01af18360d8d4..f14a0b00bb046 100644
--- a/clang/lib/Headers/cuda_wrappers/algorithm
+++ b/clang/lib/Headers/cuda_wrappers/algorithm
@@ -1,4 +1,4 @@
-/*===---- complex - CUDA wrapper for <algorithm> ----------------------------===
+/*===---- algorithm - CUDA wrapper for <algorithm> -------------------------===
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
diff --git a/clang/lib/Headers/cuda_wrappers/new b/clang/lib/Headers/cuda_wrappers/new
index 7f255314056ac..d5fb3b7011de9 100644
--- a/clang/lib/Headers/cuda_wrappers/new
+++ b/clang/lib/Headers/cuda_wrappers/new
@@ -1,4 +1,4 @@
-/*===---- complex - CUDA wrapper for <new> ------------------------------===
+/*===---- new - CUDA wrapper for <new> -------------------------------------===
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
diff --git a/clang/lib/Index/USRGeneration.cpp b/clang/lib/Index/USRGeneration.cpp
index 609a25a2fbc5a..5735847aba2a7 100644
--- a/clang/lib/Index/USRGeneration.cpp
+++ b/clang/lib/Index/USRGeneration.cpp
@@ -988,10 +988,6 @@ void USRGenerator::VisitTemplateArgument(const TemplateArgument &Arg) {
     VisitType(Arg.getIntegralType());
     Out << Arg.getAsIntegral();
     break;
-
-  case TemplateArgument::UncommonValue:
-    // FIXME: Visit value.
-    break;
   }
 }
 
diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index c2ac299bb5b7f..02bfecbb202af 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -3209,18 +3209,10 @@ static void checkDimensionsAndSetDiagnostics(Sema &S, FunctionDecl *New,
   if (!NewDeclAttr || !OldDeclAttr)
     return;
 
-  /// Returns the usigned constant integer value represented by
-  /// given expression.
-  auto getExprValue = [](const Expr *E, ASTContext &Ctx) {
-    return E->getIntegerConstantExpr(Ctx)->getZExtValue();
-  };
-
-  if ((getExprValue(NewDeclAttr->getXDim(), S.getASTContext()) !=
-       getExprValue(OldDeclAttr->getXDim(), S.getASTContext())) ||
-      (getExprValue(NewDeclAttr->getYDim(), S.getASTContext()) !=
-       getExprValue(OldDeclAttr->getYDim(), S.getASTContext())) ||
-      (getExprValue(NewDeclAttr->getZDim(), S.getASTContext()) !=
-       getExprValue(OldDeclAttr->getZDim(), S.getASTContext()))) {
+  ASTContext &Ctx = S.getASTContext();
+  if (NewDeclAttr->getXDimVal(Ctx) != OldDeclAttr->getXDimVal(Ctx) ||
+      NewDeclAttr->getYDimVal(Ctx) != OldDeclAttr->getYDimVal(Ctx) ||
+      NewDeclAttr->getZDimVal(Ctx) != OldDeclAttr->getZDimVal(Ctx)) {
     S.Diag(New->getLocation(), diag::err_conflicting_sycl_function_attributes)
         << OldDeclAttr << NewDeclAttr;
     S.Diag(New->getLocation(), diag::warn_duplicate_attribute) << OldDeclAttr;
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index fe42ea529342d..6851053a96e75 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -3096,23 +3096,17 @@ static void handleWorkGroupSize(Sema &S, Decl *D, const ParsedAttr &AL) {
   }
 
   if (WorkGroupAttr *ExistingAttr = D->getAttr<WorkGroupAttr>()) {
-    Optional<llvm::APSInt> XDimVal =
-        XDimExpr->getIntegerConstantExpr(S.getASTContext());
-    Optional<llvm::APSInt> YDimVal =
-        YDimExpr->getIntegerConstantExpr(S.getASTContext());
-    Optional<llvm::APSInt> ZDimVal =
-        ZDimExpr->getIntegerConstantExpr(S.getASTContext());
-    Optional<llvm::APSInt> ExistingXDimVal =
-        ExistingAttr->getXDim()->getIntegerConstantExpr(S.getASTContext());
-    Optional<llvm::APSInt> ExistingYDimVal =
-        ExistingAttr->getYDim()->getIntegerConstantExpr(S.getASTContext());
-    Optional<llvm::APSInt> ExistingZDimVal =
-        ExistingAttr->getZDim()->getIntegerConstantExpr(S.getASTContext());
+    ASTContext &Ctx = S.getASTContext();
+    Optional<llvm::APSInt> XDimVal = XDimExpr->getIntegerConstantExpr(Ctx);
+    Optional<llvm::APSInt> YDimVal = YDimExpr->getIntegerConstantExpr(Ctx);
+    Optional<llvm::APSInt> ZDimVal = ZDimExpr->getIntegerConstantExpr(Ctx);
+    Optional<llvm::APSInt> ExistingXDimVal = ExistingAttr->getXDimVal(Ctx);
+    Optional<llvm::APSInt> ExistingYDimVal = ExistingAttr->getYDimVal(Ctx);
+    Optional<llvm::APSInt> ExistingZDimVal = ExistingAttr->getZDimVal(Ctx);
 
     // Compare attribute arguments value and warn for a mismatch.
-    if (!((ExistingXDimVal->getZExtValue() == XDimVal->getZExtValue()) &&
-          (ExistingYDimVal->getZExtValue() == YDimVal->getZExtValue()) &&
-          (ExistingZDimVal->getZExtValue() == ZDimVal->getZExtValue()))) {
+    if (ExistingXDimVal != XDimVal || ExistingYDimVal != YDimVal ||
+        ExistingZDimVal != ZDimVal) {
       S.Diag(AL.getLoc(), diag::warn_duplicate_attribute) << AL;
       S.Diag(ExistingAttr->getLocation(), diag::note_conflicting_attribute);
     }
diff --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp
index a1c91d1403729..77b82f335a1af 100644
--- a/clang/lib/Sema/SemaLookup.cpp
+++ b/clang/lib/Sema/SemaLookup.cpp
@@ -2695,7 +2695,6 @@ addAssociatedClassesAndNamespaces(AssociatedLookup &Result,
     case TemplateArgument::Integral:
     case TemplateArgument::Expression:
     case TemplateArgument::NullPtr:
-    case TemplateArgument::UncommonValue:
       // [Note: non-type template arguments do not contribute to the set of
       //  associated namespaces. ]
       break;
diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp
index 5f4d5b9632e05..13d2125d1a28d 100644
--- a/clang/lib/Sema/SemaOverload.cpp
+++ b/clang/lib/Sema/SemaOverload.cpp
@@ -5619,8 +5619,7 @@ static ExprResult CheckConvertedConstantExpression(Sema &S, Expr *From,
                                                    QualType T, APValue &Value,
                                                    Sema::CCEKind CCE,
                                                    bool RequireInt,
-                                                   NamedDecl *Dest,
-                                                   bool *ValueDependent) {
+                                                   NamedDecl *Dest) {
   assert(S.getLangOpts().CPlusPlus11 &&
          "converted constant expression outside C++11");
 
@@ -5744,8 +5743,6 @@ static ExprResult CheckConvertedConstantExpression(Sema &S, Expr *From,
 
   if (Result.get()->isValueDependent()) {
     Value = APValue();
-    if (ValueDependent)
-      *ValueDependent = true;
     return Result;
   }
 
@@ -5769,14 +5766,10 @@ static ExprResult CheckConvertedConstantExpression(Sema &S, Expr *From,
     Result = ExprError();
   } else {
     Value = Eval.Val;
-    if (ValueDependent)
-      *ValueDependent = Eval.Dependent;
 
     if (Notes.empty()) {
       // It's a constant expression.
-      Expr *E = Result.get();
-      if (!isa<ConstantExpr>(E))
-        E = ConstantExpr::Create(S.Context, Result.get(), Value);
+      Expr *E = ConstantExpr::Create(S.Context, Result.get(), Value);
       if (ReturnPreNarrowingValue)
         Value = std::move(PreNarrowingValue);
       return E;
@@ -5803,10 +5796,9 @@ static ExprResult CheckConvertedConstantExpression(Sema &S, Expr *From,
 
 ExprResult Sema::CheckConvertedConstantExpression(Expr *From, QualType T,
                                                   APValue &Value, CCEKind CCE,
-                                                  NamedDecl *Dest,
-                                                  bool *ValueDependent) {
+                                                  NamedDecl *Dest) {
   return ::CheckConvertedConstantExpression(*this, From, T, Value, CCE, false,
-                                            Dest, ValueDependent);
+                                            Dest);
 }
 
 ExprResult Sema::CheckConvertedConstantExpression(Expr *From, QualType T,
@@ -5816,8 +5808,7 @@ ExprResult Sema::CheckConvertedConstantExpression(Expr *From, QualType T,
 
   APValue V;
   auto R = ::CheckConvertedConstantExpression(*this, From, T, V, CCE, true,
-                                              /*Dest=*/nullptr,
-                                              /*ValueDependent=*/nullptr);
+                                              /*Dest=*/nullptr);
   if (!R.isInvalid() && !R.get()->isValueDependent())
     Value = V.getInt();
   return R;
diff --git a/clang/lib/Sema/SemaSYCL.cpp b/clang/lib/Sema/SemaSYCL.cpp
index 907af88b74a58..1909c1d81a872 100644
--- a/clang/lib/Sema/SemaSYCL.cpp
+++ b/clang/lib/Sema/SemaSYCL.cpp
@@ -2705,15 +2705,10 @@ class SyclKernelIntHeaderCreator : public SyclKernelFieldHandler {
 
   // Sets a flag if the kernel is a parallel_for that calls the
   // free function API "this_item".
-  void setThisItemIsCalled(const CXXRecordDecl *KernelObj,
-                           FunctionDecl *KernelFunc) {
+  void setThisItemIsCalled(FunctionDecl *KernelFunc) {
     if (getKernelInvocationKind(KernelFunc) != InvokeParallelFor)
       return;
 
-    const CXXMethodDecl *WGLambdaFn = getOperatorParens(KernelObj);
-    if (!WGLambdaFn)
-      return;
-
     // The call graph for this translation unit.
     CallGraph SYCLCG;
     SYCLCG.addToCallGraph(SemaRef.getASTContext().getTranslationUnitDecl());
@@ -2721,7 +2716,7 @@ class SyclKernelIntHeaderCreator : public SyclKernelFieldHandler {
         std::pair<const FunctionDecl *, const FunctionDecl *>;
     llvm::SmallPtrSet<const FunctionDecl *, 16> Visited;
     llvm::SmallVector<ChildParentPair, 16> WorkList;
-    WorkList.push_back({WGLambdaFn, nullptr});
+    WorkList.push_back({KernelFunc, nullptr});
 
     while (!WorkList.empty()) {
       const FunctionDecl *FD = WorkList.back().first;
@@ -2772,7 +2767,7 @@ class SyclKernelIntHeaderCreator : public SyclKernelFieldHandler {
     bool IsSIMDKernel = isESIMDKernelType(KernelObj);
     Header.startKernel(Name, NameType, StableName, KernelObj->getLocation(),
                        IsSIMDKernel);
-    setThisItemIsCalled(KernelObj, KernelFunc);
+    setThisItemIsCalled(KernelFunc);
   }
 
   bool handleSyclAccessorType(const CXXRecordDecl *RD,
@@ -3302,32 +3297,28 @@ void Sema::MarkDevice(void) {
           break;
         }
         case attr::Kind::ReqdWorkGroupSize: {
-          auto *Attr = cast<ReqdWorkGroupSizeAttr>(A);
+          auto *RWGSA = cast<ReqdWorkGroupSizeAttr>(A);
           if (auto *Existing = SYCLKernel->getAttr<ReqdWorkGroupSizeAttr>()) {
-            if ((getIntExprValue(Existing->getXDim(), getASTContext()) !=
-                 getIntExprValue(Attr->getXDim(), getASTContext())) ||
-                (getIntExprValue(Existing->getYDim(), getASTContext()) !=
-                 getIntExprValue(Attr->getYDim(), getASTContext())) ||
-                (getIntExprValue(Existing->getZDim(), getASTContext()) !=
-                 getIntExprValue(Attr->getZDim(), getASTContext()))) {
+            ASTContext &Ctx = getASTContext();
+            if (Existing->getXDimVal(Ctx) != RWGSA->getXDimVal(Ctx) ||
+                Existing->getYDimVal(Ctx) != RWGSA->getYDimVal(Ctx) ||
+                Existing->getZDimVal(Ctx) != RWGSA->getZDimVal(Ctx)) {
               Diag(SYCLKernel->getLocation(),
                    diag::err_conflicting_sycl_kernel_attributes);
               Diag(Existing->getLocation(), diag::note_conflicting_attribute);
-              Diag(Attr->getLocation(), diag::note_conflicting_attribute);
+              Diag(RWGSA->getLocation(), diag::note_conflicting_attribute);
               SYCLKernel->setInvalidDecl();
             }
           } else if (auto *Existing =
                          SYCLKernel->getAttr<SYCLIntelMaxWorkGroupSizeAttr>()) {
-            if ((getIntExprValue(Existing->getXDim(), getASTContext()) <
-                 getIntExprValue(Attr->getXDim(), getASTContext())) ||
-                (getIntExprValue(Existing->getYDim(), getASTContext()) <
-                 getIntExprValue(Attr->getYDim(), getASTContext())) ||
-                (getIntExprValue(Existing->getZDim(), getASTContext()) <
-                 getIntExprValue(Attr->getZDim(), getASTContext()))) {
+            ASTContext &Ctx = getASTContext();
+            if (Existing->getXDimVal(Ctx) < RWGSA->getXDimVal(Ctx) ||
+                Existing->getYDimVal(Ctx) < RWGSA->getYDimVal(Ctx) ||
+                Existing->getZDimVal(Ctx) < RWGSA->getZDimVal(Ctx)) {
               Diag(SYCLKernel->getLocation(),
                    diag::err_conflicting_sycl_kernel_attributes);
               Diag(Existing->getLocation(), diag::note_conflicting_attribute);
-              Diag(Attr->getLocation(), diag::note_conflicting_attribute);
+              Diag(RWGSA->getLocation(), diag::note_conflicting_attribute);
               SYCLKernel->setInvalidDecl();
             } else {
               SYCLKernel->addAttr(A);
@@ -3338,18 +3329,16 @@ void Sema::MarkDevice(void) {
           break;
         }
         case attr::Kind::SYCLIntelMaxWorkGroupSize: {
-          auto *Attr = cast<SYCLIntelMaxWorkGroupSizeAttr>(A);
+          auto *SIMWGSA = cast<SYCLIntelMaxWorkGroupSizeAttr>(A);
           if (auto *Existing = SYCLKernel->getAttr<ReqdWorkGroupSizeAttr>()) {
-            if ((getIntExprValue(Existing->getXDim(), getASTContext()) >
-                 getIntExprValue(Attr->getXDim(), getASTContext())) ||
-                (getIntExprValue(Existing->getYDim(), getASTContext()) >
-                 getIntExprValue(Attr->getYDim(), getASTContext())) ||
-                (getIntExprValue(Existing->getZDim(), getASTContext()) >
-                 getIntExprValue(Attr->getZDim(), getASTContext()))) {
+            ASTContext &Ctx = getASTContext();
+            if (Existing->getXDimVal(Ctx) > SIMWGSA->getXDimVal(Ctx) ||
+                Existing->getYDimVal(Ctx) > SIMWGSA->getYDimVal(Ctx) ||
+                Existing->getZDimVal(Ctx) > SIMWGSA->getZDimVal(Ctx)) {
               Diag(SYCLKernel->getLocation(),
                    diag::err_conflicting_sycl_kernel_attributes);
               Diag(Existing->getLocation(), diag::note_conflicting_attribute);
-              Diag(Attr->getLocation(), diag::note_conflicting_attribute);
+              Diag(SIMWGSA->getLocation(), diag::note_conflicting_attribute);
               SYCLKernel->setInvalidDecl();
             } else {
               SYCLKernel->addAttr(A);
diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp
index 9d31a87012419..64259767d98a6 100644
--- a/clang/lib/Sema/SemaTemplate.cpp
+++ b/clang/lib/Sema/SemaTemplate.cpp
@@ -4086,7 +4086,6 @@ static bool isTemplateArgumentTemplateParameter(
   case TemplateArgument::NullPtr:
   case TemplateArgument::Integral:
   case TemplateArgument::Declaration:
-  case TemplateArgument::UncommonValue:
   case TemplateArgument::Pack:
   case TemplateArgument::TemplateExpansion:
     return false;
@@ -5420,7 +5419,6 @@ bool Sema::CheckTemplateArgument(NamedDecl *Param,
 
     case TemplateArgument::Declaration:
     case TemplateArgument::Integral:
-    case TemplateArgument::UncommonValue:
     case TemplateArgument::NullPtr:
       // We've already checked this template argument, so just copy
       // it to the list of converted arguments.
@@ -5567,10 +5565,11 @@ bool Sema::CheckTemplateArgument(NamedDecl *Param,
     return true;
 
   case TemplateArgument::Declaration:
+    llvm_unreachable("Declaration argument with template template parameter");
   case TemplateArgument::Integral:
-  case TemplateArgument::UncommonValue:
+    llvm_unreachable("Integral argument with template template parameter");
   case TemplateArgument::NullPtr:
-    llvm_unreachable("non-type argument with template template parameter");
+    llvm_unreachable("Null pointer argument with template template parameter");
 
   case TemplateArgument::Pack:
     llvm_unreachable("Caller must expand template argument packs");
@@ -6621,12 +6620,6 @@ CheckTemplateArgumentAddressOfObjectOrFunction(Sema &S,
                                                      Arg, ArgType))
     return true;
 
-  // Don't build a resolved template argument naming a dependent declaration.
-  if (Entity->isTemplated()) {
-    Converted = TemplateArgument(ArgIn);
-    return false;
-  }
-
   // Create the template argument.
   Converted = TemplateArgument(cast<ValueDecl>(Entity->getCanonicalDecl()),
                                S.Context.getCanonicalType(ParamType));
@@ -6641,6 +6634,8 @@ static bool CheckTemplateArgumentPointerToMember(Sema &S,
                                                  QualType ParamType,
                                                  Expr *&ResultArg,
                                                  TemplateArgument &Converted) {
+  bool Invalid = false;
+
   Expr *Arg = ResultArg;
   bool ObjCLifetimeConversion;
 
@@ -6656,7 +6651,7 @@ static bool CheckTemplateArgumentPointerToMember(Sema &S,
   // See http://www.open-std.org/jtc1/sc22/wg21/docs/cwg_defects.html#773
   bool ExtraParens = false;
   while (ParenExpr *Parens = dyn_cast<ParenExpr>(Arg)) {
-    if (!ExtraParens) {
+    if (!Invalid && !ExtraParens) {
       S.Diag(Arg->getBeginLoc(),
              S.getLangOpts().CPlusPlus11
                  ? diag::warn_cxx98_compat_template_arg_extra_parens
@@ -6685,8 +6680,13 @@ static bool CheckTemplateArgumentPointerToMember(Sema &S,
     ValueDecl *VD = DRE->getDecl();
     if (VD->getType()->isMemberPointerType()) {
       if (isa<NonTypeTemplateParmDecl>(VD)) {
-        Converted = TemplateArgument(Arg);
-        return false;
+        if (Arg->isTypeDependent() || Arg->isValueDependent()) {
+          Converted = TemplateArgument(Arg);
+        } else {
+          VD = cast<ValueDecl>(VD->getCanonicalDecl());
+          Converted = TemplateArgument(VD, ParamType);
+        }
+        return Invalid;
       }
     }
 
@@ -6745,7 +6745,7 @@ static bool CheckTemplateArgumentPointerToMember(Sema &S,
       ValueDecl *D = cast<ValueDecl>(DRE->getDecl()->getCanonicalDecl());
       Converted = TemplateArgument(D, S.Context.getCanonicalType(ParamType));
     }
-    return false;
+    return Invalid;
   }
 
   // We found something else, but we don't know specifically what it is.
@@ -6922,24 +6922,49 @@ ExprResult Sema::CheckTemplateArgument(NonTypeTemplateParmDecl *Param,
     //   A template-argument for a non-type template parameter shall be
     //   a converted constant expression of the type of the template-parameter.
     APValue Value;
-    bool ValueDependent = false;
     ExprResult ArgResult = CheckConvertedConstantExpression(
-        Arg, ParamType, Value, CCEK_TemplateArg, Param, &ValueDependent);
+        Arg, ParamType, Value, CCEK_TemplateArg, Param);
     if (ArgResult.isInvalid())
       return ExprError();
 
     // For a value-dependent argument, CheckConvertedConstantExpression is
-    // permitted (and expected) to be unable to determine a value. We might find
-    // the evaluated result refers to a dependent declaration even though the
-    // template argument is not a value-dependent expression.
-    if (ValueDependent) {
+    // permitted (and expected) to be unable to determine a value.
+    if (ArgResult.get()->isValueDependent()) {
       Converted = TemplateArgument(ArgResult.get());
       return ArgResult;
     }
 
-    // Prior to C++20, enforce restrictions on possible template argument
-    // values.
-    if (!getLangOpts().CPlusPlus20 && Value.isLValue()) {
+    // Convert the APValue to a TemplateArgument.
+    switch (Value.getKind()) {
+    case APValue::None:
+      assert(ParamType->isNullPtrType());
+      Converted = TemplateArgument(CanonParamType, /*isNullPtr*/true);
+      break;
+    case APValue::Indeterminate:
+      llvm_unreachable("result of constant evaluation should be initialized");
+      break;
+    case APValue::Int:
+      assert(ParamType->isIntegralOrEnumerationType());
+      Converted = TemplateArgument(Context, Value.getInt(), CanonParamType);
+      break;
+    case APValue::MemberPointer: {
+      assert(ParamType->isMemberPointerType());
+
+      // FIXME: We need TemplateArgument representation and mangling for these.
+      if (!Value.getMemberPointerPath().empty()) {
+        Diag(Arg->getBeginLoc(),
+             diag::err_template_arg_member_ptr_base_derived_not_supported)
+            << Value.getMemberPointerDecl() << ParamType
+            << Arg->getSourceRange();
+        return ExprError();
+      }
+
+      auto *VD = const_cast<ValueDecl*>(Value.getMemberPointerDecl());
+      Converted = VD ? TemplateArgument(VD, CanonParamType)
+                     : TemplateArgument(CanonParamType, /*isNullPtr*/true);
+      break;
+    }
+    case APValue::LValue: {
       //   For a non-type template-parameter of pointer or reference type,
       //   the value of the constant expression shall not refer to
       assert(ParamType->isPointerType() || ParamType->isReferenceType() ||
@@ -6955,7 +6980,8 @@ ExprResult Sema::CheckTemplateArgument(NonTypeTemplateParmDecl *Param,
             << Arg->getSourceRange();
         return ExprError();
       }
-      // -- a subobject [until C++20]
+      // -- a subobject
+      // FIXME: Until C++20
       if (Value.hasLValuePath() && Value.getLValuePath().size() == 1 &&
           VD && VD->getType()->isArrayType() &&
           Value.getLValuePath()[0].getAsArrayIndex() == 0 &&
@@ -6973,12 +6999,29 @@ ExprResult Sema::CheckTemplateArgument(NonTypeTemplateParmDecl *Param,
              "null reference should not be a constant expression");
       assert((!VD || !ParamType->isNullPtrType()) &&
              "non-null value of type nullptr_t?");
+      Converted = VD ? TemplateArgument(VD, CanonParamType)
+                     : TemplateArgument(CanonParamType, /*isNullPtr*/true);
+      break;
     }
-
-    if (Value.isAddrLabelDiff())
+    case APValue::Struct:
+    case APValue::Union:
+      // Get or create the corresponding template parameter object.
+      Converted = TemplateArgument(
+          Context.getTemplateParamObjectDecl(CanonParamType, Value),
+          CanonParamType);
+      break;
+    case APValue::AddrLabelDiff:
       return Diag(StartLoc, diag::err_non_type_template_arg_addr_label_diff);
+    case APValue::FixedPoint:
+    case APValue::Float:
+    case APValue::ComplexInt:
+    case APValue::ComplexFloat:
+    case APValue::Vector:
+    case APValue::Array:
+      return Diag(StartLoc, diag::err_non_type_template_arg_unsupported)
+             << ParamType;
+    }
 
-    Converted = TemplateArgument(Context, CanonParamType, Value);
     return ArgResult.get();
   }
 
@@ -7516,9 +7559,12 @@ Sema::BuildExpressionFromDeclTemplateArgument(const TemplateArgument &Arg,
 /// This routine takes care of the mapping from an integral template
 /// argument (which may have any integral type) to the appropriate
 /// literal value.
-static Expr *BuildExpressionFromIntegralTemplateArgumentValue(
-    Sema &S, QualType OrigT, const llvm::APSInt &Int, SourceLocation Loc) {
-  assert(OrigT->isIntegralOrEnumerationType());
+ExprResult
+Sema::BuildExpressionFromIntegralTemplateArgument(const TemplateArgument &Arg,
+                                                  SourceLocation Loc) {
+  assert(Arg.getKind() == TemplateArgument::Integral &&
+         "Operation is only valid for integral template arguments");
+  QualType OrigT = Arg.getIntegralType();
 
   // If this is an enum type that we're instantiating, we need to use an integer
   // type the same size as the enumerator.  We don't want to build an
@@ -7534,7 +7580,7 @@ static Expr *BuildExpressionFromIntegralTemplateArgumentValue(
     CharacterLiteral::CharacterKind Kind;
     if (T->isWideCharType())
       Kind = CharacterLiteral::Wide;
-    else if (T->isChar8Type() && S.getLangOpts().Char8)
+    else if (T->isChar8Type() && getLangOpts().Char8)
       Kind = CharacterLiteral::UTF8;
     else if (T->isChar16Type())
       Kind = CharacterLiteral::UTF16;
@@ -7543,133 +7589,29 @@ static Expr *BuildExpressionFromIntegralTemplateArgumentValue(
     else
       Kind = CharacterLiteral::Ascii;
 
-    E = new (S.Context) CharacterLiteral(Int.getZExtValue(), Kind, T, Loc);
+    E = new (Context) CharacterLiteral(Arg.getAsIntegral().getZExtValue(),
+                                       Kind, T, Loc);
   } else if (T->isBooleanType()) {
-    E = new (S.Context) CXXBoolLiteralExpr(Int.getBoolValue(), T, Loc);
+    E = new (Context) CXXBoolLiteralExpr(Arg.getAsIntegral().getBoolValue(),
+                                         T, Loc);
+  } else if (T->isNullPtrType()) {
+    E = new (Context) CXXNullPtrLiteralExpr(Context.NullPtrTy, Loc);
   } else {
-    E = IntegerLiteral::Create(S.Context, Int, T, Loc);
+    E = IntegerLiteral::Create(Context, Arg.getAsIntegral(), T, Loc);
   }
 
   if (OrigT->isEnumeralType()) {
     // FIXME: This is a hack. We need a better way to handle substituted
     // non-type template parameters.
-    E = CStyleCastExpr::Create(S.Context, OrigT, VK_RValue, CK_IntegralCast, E,
-                               nullptr, S.CurFPFeatureOverrides(),
-                               S.Context.getTrivialTypeSourceInfo(OrigT, Loc),
+    E = CStyleCastExpr::Create(Context, OrigT, VK_RValue, CK_IntegralCast, E,
+                               nullptr, CurFPFeatureOverrides(),
+                               Context.getTrivialTypeSourceInfo(OrigT, Loc),
                                Loc, Loc);
   }
 
   return E;
 }
 
-static Expr *BuildExpressionFromNonTypeTemplateArgumentValue(
-    Sema &S, QualType T, const APValue &Val, SourceLocation Loc) {
-  auto MakeInitList = [&] (ArrayRef<Expr*> Elts) -> Expr* {
-    auto *ILE = new (S.Context) InitListExpr(S.Context, Loc, Elts, Loc);
-    ILE->setType(T);
-    return ILE;
-  };
-
-  switch (Val.getKind()) {
-  case APValue::AddrLabelDiff:
-    // This cannot occur in a template argument at all.
-  case APValue::Array:
-  case APValue::Struct:
-  case APValue::Union:
-    // These can only occur within a template parameter object, which is
-    // represented as a TemplateArgument::Declaration.
-    llvm_unreachable("unexpected template argument value");
-
-  case APValue::Int:
-    return BuildExpressionFromIntegralTemplateArgumentValue(S, T, Val.getInt(),
-                                                            Loc);
-
-  case APValue::Float:
-    return FloatingLiteral::Create(S.Context, Val.getFloat(), /*IsExact=*/true,
-                                   T, Loc);
-
-  case APValue::FixedPoint:
-    return FixedPointLiteral::CreateFromRawInt(
-        S.Context, Val.getFixedPoint().getValue(), T, Loc,
-        Val.getFixedPoint().getScale());
-
-  case APValue::ComplexInt: {
-    QualType ElemT = T->castAs<ComplexType>()->getElementType();
-    return MakeInitList({BuildExpressionFromIntegralTemplateArgumentValue(
-                             S, ElemT, Val.getComplexIntReal(), Loc),
-                         BuildExpressionFromIntegralTemplateArgumentValue(
-                             S, ElemT, Val.getComplexIntImag(), Loc)});
-  }
-
-  case APValue::ComplexFloat: {
-    QualType ElemT = T->castAs<ComplexType>()->getElementType();
-    return MakeInitList(
-        {FloatingLiteral::Create(S.Context, Val.getComplexFloatReal(), true,
-                                 ElemT, Loc),
-         FloatingLiteral::Create(S.Context, Val.getComplexFloatImag(), true,
-                                 ElemT, Loc)});
-  }
-
-  case APValue::Vector: {
-    QualType ElemT = T->castAs<VectorType>()->getElementType();
-    llvm::SmallVector<Expr *, 8> Elts;
-    for (unsigned I = 0, N = Val.getVectorLength(); I != N; ++I)
-      Elts.push_back(BuildExpressionFromNonTypeTemplateArgumentValue(
-          S, ElemT, Val.getVectorElt(I), Loc));
-    return MakeInitList(Elts);
-  }
-
-  case APValue::None:
-  case APValue::Indeterminate:
-    // FIXME: Are these values possible?
-  case APValue::LValue:
-  case APValue::MemberPointer:
-    // There isn't necessarily a valid equivalent source-level syntax for
-    // these; in particular, a naive lowering might violate access control.
-    // So for now we lower to a ConstantExpr holding the value, wrapped around
-    // an OpaqueValueExpr.
-    // FIXME: We should have a better representation for this.
-    ExprValueKind VK = VK_RValue;
-    if (T->isReferenceType()) {
-      T = T->getPointeeType();
-      VK = VK_LValue;
-    }
-    auto *OVE = new (S.Context) OpaqueValueExpr(Loc, T, VK);
-    return ConstantExpr::Create(S.Context, OVE, Val);
-  }
-  llvm_unreachable("Unhandled APValue::ValueKind enum");
-}
-
-ExprResult
-Sema::BuildExpressionFromNonTypeTemplateArgument(const TemplateArgument &Arg,
-                                                 SourceLocation Loc) {
-  switch (Arg.getKind()) {
-  case TemplateArgument::Null:
-  case TemplateArgument::Type:
-  case TemplateArgument::Template:
-  case TemplateArgument::TemplateExpansion:
-  case TemplateArgument::Pack:
-    llvm_unreachable("not a non-type template argument");
-
-  case TemplateArgument::Expression:
-    return Arg.getAsExpr();
-
-  case TemplateArgument::NullPtr:
-  case TemplateArgument::Declaration:
-    return BuildExpressionFromDeclTemplateArgument(
-        Arg, Arg.getNonTypeTemplateArgumentType(), Loc);
-
-  case TemplateArgument::Integral:
-    return BuildExpressionFromIntegralTemplateArgumentValue(
-        *this, Arg.getIntegralType(), Arg.getAsIntegral(), Loc);
-
-  case TemplateArgument::UncommonValue:
-    return BuildExpressionFromNonTypeTemplateArgumentValue(
-        *this, Arg.getUncommonValueType(), Arg.getAsUncommonValue(), Loc);
-  }
-  llvm_unreachable("Unhandled TemplateArgument::ArgKind enum");
-}
-
 /// Match two template parameters within template parameter lists.
 static bool MatchTemplateParameterKind(Sema &S, NamedDecl *New, NamedDecl *Old,
                                        bool Complain,
diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp
index 23d4056ce254c..4a3b64cf54250 100644
--- a/clang/lib/Sema/SemaTemplateDeduction.cpp
+++ b/clang/lib/Sema/SemaTemplateDeduction.cpp
@@ -276,16 +276,6 @@ checkDeducedTemplateArguments(ASTContext &Context,
     // All other combinations are incompatible.
     return DeducedTemplateArgument();
 
-  case TemplateArgument::UncommonValue:
-    // If we deduced a value and a dependent expression, keep the value.
-    if (Y.getKind() == TemplateArgument::Expression ||
-        (Y.getKind() == TemplateArgument::UncommonValue &&
-         X.structurallyEquals(Y)))
-      return X;
-
-    // All other combinations are incompatible.
-    return DeducedTemplateArgument();
-
   case TemplateArgument::Template:
     if (Y.getKind() == TemplateArgument::Template &&
         Context.hasSameTemplateName(X.getAsTemplate(), Y.getAsTemplate()))
@@ -2371,18 +2361,20 @@ DeduceTemplateArguments(Sema &S,
     return Sema::TDK_NonDeducedMismatch;
 
   case TemplateArgument::Integral:
-    if (Arg.getKind() == TemplateArgument::Integral &&
-        hasSameExtendedValue(Param.getAsIntegral(), Arg.getAsIntegral()))
-      return Sema::TDK_Success;
+    if (Arg.getKind() == TemplateArgument::Integral) {
+      if (hasSameExtendedValue(Param.getAsIntegral(), Arg.getAsIntegral()))
+        return Sema::TDK_Success;
 
-    Info.FirstArg = Param;
-    Info.SecondArg = Arg;
-    return Sema::TDK_NonDeducedMismatch;
+      Info.FirstArg = Param;
+      Info.SecondArg = Arg;
+      return Sema::TDK_NonDeducedMismatch;
+    }
 
-  case TemplateArgument::UncommonValue:
-    if (Arg.getKind() == TemplateArgument::UncommonValue &&
-        Arg.structurallyEquals(Param))
-      return Sema::TDK_Success;
+    if (Arg.getKind() == TemplateArgument::Expression) {
+      Info.FirstArg = Param;
+      Info.SecondArg = Arg;
+      return Sema::TDK_NonDeducedMismatch;
+    }
 
     Info.FirstArg = Param;
     Info.SecondArg = Arg;
@@ -2391,34 +2383,28 @@ DeduceTemplateArguments(Sema &S,
   case TemplateArgument::Expression:
     if (const NonTypeTemplateParmDecl *NTTP =
             getDeducedParameterFromExpr(Info, Param.getAsExpr())) {
-      switch (Arg.getKind()) {
-      case TemplateArgument::Integral:
-      case TemplateArgument::Expression:
-      case TemplateArgument::UncommonValue:
-        return DeduceNonTypeTemplateArgument(
-            S, TemplateParams, NTTP, DeducedTemplateArgument(Arg),
-            Arg.getNonTypeTemplateArgumentType(), Info, Deduced);
-
-      case TemplateArgument::NullPtr:
-        return DeduceNullPtrTemplateArgument(
-            S, TemplateParams, NTTP, Arg.getNullPtrType(), Info, Deduced);
-
+      if (Arg.getKind() == TemplateArgument::Integral)
+        return DeduceNonTypeTemplateArgument(S, TemplateParams, NTTP,
+                                             Arg.getAsIntegral(),
+                                             Arg.getIntegralType(),
+                                             /*ArrayBound=*/false,
+                                             Info, Deduced);
+      if (Arg.getKind() == TemplateArgument::NullPtr)
+        return DeduceNullPtrTemplateArgument(S, TemplateParams, NTTP,
+                                             Arg.getNullPtrType(),
+                                             Info, Deduced);
+      if (Arg.getKind() == TemplateArgument::Expression)
+        return DeduceNonTypeTemplateArgument(S, TemplateParams, NTTP,
+                                             Arg.getAsExpr(), Info, Deduced);
+      if (Arg.getKind() == TemplateArgument::Declaration)
+        return DeduceNonTypeTemplateArgument(S, TemplateParams, NTTP,
+                                             Arg.getAsDecl(),
+                                             Arg.getParamTypeForDecl(),
+                                             Info, Deduced);
 
-      case TemplateArgument::Declaration:
-        return DeduceNonTypeTemplateArgument(
-            S, TemplateParams, NTTP, Arg.getAsDecl(), Arg.getParamTypeForDecl(),
-            Info, Deduced);
-
-      case TemplateArgument::Null:
-      case TemplateArgument::Type:
-      case TemplateArgument::Template:
-      case TemplateArgument::TemplateExpansion:
-      case TemplateArgument::Pack:
-        Info.FirstArg = Param;
-        Info.SecondArg = Arg;
-        return Sema::TDK_NonDeducedMismatch;
-      }
-      llvm_unreachable("Unknown template argument kind");
+      Info.FirstArg = Param;
+      Info.SecondArg = Arg;
+      return Sema::TDK_NonDeducedMismatch;
     }
 
     // Can't deduce anything, but that's okay.
@@ -2606,9 +2592,6 @@ static bool isSameTemplateArg(ASTContext &Context,
     case TemplateArgument::Integral:
       return hasSameExtendedValue(X.getAsIntegral(), Y.getAsIntegral());
 
-    case TemplateArgument::UncommonValue:
-      return X.structurallyEquals(Y);
-
     case TemplateArgument::Expression: {
       llvm::FoldingSetNodeID XID, YID;
       X.getAsExpr()->Profile(XID, Context, true);
@@ -2674,9 +2657,9 @@ Sema::getTrivialTemplateArgumentLoc(const TemplateArgument &Arg,
                                E);
   }
 
-  case TemplateArgument::Integral:
-  case TemplateArgument::UncommonValue: {
-    Expr *E = BuildExpressionFromNonTypeTemplateArgument(Arg, Loc).get();
+  case TemplateArgument::Integral: {
+    Expr *E =
+        BuildExpressionFromIntegralTemplateArgument(Arg, Loc).getAs<Expr>();
     return TemplateArgumentLoc(TemplateArgument(E), E);
   }
 
@@ -6120,8 +6103,11 @@ MarkUsedTemplateParameters(ASTContext &Ctx,
   case TemplateArgument::Null:
   case TemplateArgument::Integral:
   case TemplateArgument::Declaration:
+    break;
+
   case TemplateArgument::NullPtr:
-  case TemplateArgument::UncommonValue:
+    MarkUsedTemplateParameters(Ctx, TemplateArg.getNullPtrType(), OnlyDeduced,
+                               Depth, Used);
     break;
 
   case TemplateArgument::Type:
diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp
index f82fe90693366..173b566b5ed5c 100644
--- a/clang/lib/Sema/SemaTemplateInstantiate.cpp
+++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp
@@ -1672,18 +1672,16 @@ ExprResult TemplateInstantiator::transformNonTypeTemplateParmRef(
       VD = nullptr;
     }
 
-    QualType paramType = arg.getNonTypeTemplateArgumentType();
+    QualType paramType = VD ? arg.getParamTypeForDecl() : arg.getNullPtrType();
     assert(!paramType.isNull() && "type substitution failed for param type");
     assert(!paramType->isDependentType() && "param type still dependent");
     result = SemaRef.BuildExpressionFromDeclTemplateArgument(arg, paramType, loc);
     refParam = paramType->isReferenceType();
   } else {
-    QualType paramType = arg.getNonTypeTemplateArgumentType();
-    result = SemaRef.BuildExpressionFromNonTypeTemplateArgument(arg, loc);
-    refParam = paramType->isReferenceType();
+    result = SemaRef.BuildExpressionFromIntegralTemplateArgument(arg, loc);
     assert(result.isInvalid() ||
            SemaRef.Context.hasSameType(result.get()->getType(),
-                                       paramType.getNonReferenceType()));
+                                       arg.getIntegralType()));
   }
 
   if (result.isInvalid())
@@ -3345,8 +3343,7 @@ Sema::InstantiateClassMembers(SourceLocation PointOfInstantiation,
       if (FunctionDecl *Pattern =
               Function->getInstantiatedFromMemberFunction()) {
 
-        if (TSK != TSK_ImplicitInstantiation &&
-            Function->hasAttr<ExcludeFromExplicitInstantiationAttr>())
+        if (Function->hasAttr<ExcludeFromExplicitInstantiationAttr>())
           continue;
 
         MemberSpecializationInfo *MSInfo =
@@ -3391,8 +3388,7 @@ Sema::InstantiateClassMembers(SourceLocation PointOfInstantiation,
         continue;
 
       if (Var->isStaticDataMember()) {
-        if (TSK != TSK_ImplicitInstantiation &&
-            Var->hasAttr<ExcludeFromExplicitInstantiationAttr>())
+        if (Var->hasAttr<ExcludeFromExplicitInstantiationAttr>())
           continue;
 
         MemberSpecializationInfo *MSInfo = Var->getMemberSpecializationInfo();
@@ -3409,7 +3405,7 @@ Sema::InstantiateClassMembers(SourceLocation PointOfInstantiation,
             SuppressNew)
           continue;
 
-        if (TSK != TSK_ExplicitInstantiationDeclaration) {
+        if (TSK == TSK_ExplicitInstantiationDefinition) {
           // C++0x [temp.explicit]p8:
           //   An explicit instantiation definition that names a class template
           //   specialization explicitly instantiates the class template
diff --git a/clang/lib/Sema/SemaTemplateVariadic.cpp b/clang/lib/Sema/SemaTemplateVariadic.cpp
index 3c6365a075f48..1951aec3d17d9 100644
--- a/clang/lib/Sema/SemaTemplateVariadic.cpp
+++ b/clang/lib/Sema/SemaTemplateVariadic.cpp
@@ -1103,7 +1103,6 @@ Sema::getTemplateArgumentPackExpansionPattern(
   case TemplateArgument::NullPtr:
   case TemplateArgument::Template:
   case TemplateArgument::Integral:
-  case TemplateArgument::UncommonValue:
   case TemplateArgument::Pack:
   case TemplateArgument::Null:
     return TemplateArgumentLoc();
@@ -1154,7 +1153,6 @@ Optional<unsigned> Sema::getFullyPackExpandedSize(TemplateArgument Arg) {
   case TemplateArgument::NullPtr:
   case TemplateArgument::TemplateExpansion:
   case TemplateArgument::Integral:
-  case TemplateArgument::UncommonValue:
   case TemplateArgument::Pack:
   case TemplateArgument::Null:
     return None;
diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h
index ea0a9159b6680..2b39d79270b20 100644
--- a/clang/lib/Sema/TreeTransform.h
+++ b/clang/lib/Sema/TreeTransform.h
@@ -3561,7 +3561,6 @@ class TreeTransform {
     case TemplateArgument::Null:
     case TemplateArgument::Integral:
     case TemplateArgument::Declaration:
-    case TemplateArgument::UncommonValue:
     case TemplateArgument::Pack:
     case TemplateArgument::TemplateExpansion:
     case TemplateArgument::NullPtr:
@@ -4234,8 +4233,7 @@ bool TreeTransform<Derived>::TransformTemplateArgument(
 
   case TemplateArgument::Integral:
   case TemplateArgument::NullPtr:
-  case TemplateArgument::Declaration:
-  case TemplateArgument::UncommonValue: {
+  case TemplateArgument::Declaration: {
     // Transform a resolved template argument straight to a resolved template
     // argument. We get here when substituting into an already-substituted
     // template type argument during concept satisfaction checking.
@@ -4262,15 +4260,9 @@ bool TreeTransform<Derived>::TransformTemplateArgument(
     else if (Arg.getKind() == TemplateArgument::NullPtr)
       Output = TemplateArgumentLoc(TemplateArgument(NewT, /*IsNullPtr=*/true),
                                    TemplateArgumentLocInfo());
-    else if (Arg.getKind() == TemplateArgument::Declaration)
+    else
       Output = TemplateArgumentLoc(TemplateArgument(NewD, NewT),
                                    TemplateArgumentLocInfo());
-    else if (Arg.getKind() == TemplateArgument::UncommonValue)
-      Output = TemplateArgumentLoc(
-          TemplateArgument(getSema().Context, NewT, Arg.getAsUncommonValue()),
-          TemplateArgumentLocInfo());
-    else
-      llvm_unreachable("unexpected template argument kind");
 
     return false;
   }
diff --git a/clang/lib/Serialization/ASTReader.cpp b/clang/lib/Serialization/ASTReader.cpp
index 3e4409ca3006c..1ee23b32c3088 100644
--- a/clang/lib/Serialization/ASTReader.cpp
+++ b/clang/lib/Serialization/ASTReader.cpp
@@ -7107,7 +7107,6 @@ ASTRecordReader::readTemplateArgumentLocInfo(TemplateArgument::ArgKind Kind) {
   case TemplateArgument::Integral:
   case TemplateArgument::Declaration:
   case TemplateArgument::NullPtr:
-  case TemplateArgument::UncommonValue:
   case TemplateArgument::Pack:
     // FIXME: Is this right?
     return TemplateArgumentLocInfo();
diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp
index 87160b26d4210..3a281e492fde7 100644
--- a/clang/lib/Serialization/ASTWriter.cpp
+++ b/clang/lib/Serialization/ASTWriter.cpp
@@ -5350,7 +5350,6 @@ void ASTRecordWriter::AddTemplateArgumentLocInfo(
   case TemplateArgument::Integral:
   case TemplateArgument::Declaration:
   case TemplateArgument::NullPtr:
-  case TemplateArgument::UncommonValue:
   case TemplateArgument::Pack:
     // FIXME: Is this right?
     break;
diff --git a/clang/test/CXX/drs/dr15xx.cpp b/clang/test/CXX/drs/dr15xx.cpp
index 8bfa29a8b6676..478a0d7d00ddf 100644
--- a/clang/test/CXX/drs/dr15xx.cpp
+++ b/clang/test/CXX/drs/dr15xx.cpp
@@ -239,20 +239,6 @@ namespace dr1550 { // dr1550: yes
   }
 }
 
-namespace dr1558 { // dr1558: 12
-#if __cplusplus >= 201103L
-  template<class T, class...> using first_of = T;
-  template<class T> first_of<void, typename T::type> f(int); // expected-note {{'int' cannot be used prior to '::'}}
-  template<class T> void f(...) = delete; // expected-note {{deleted}}
-
-  struct X { typedef void type; };
-  void test() {
-    f<X>(0);
-    f<int>(0); // expected-error {{deleted}}
-  }
-#endif
-}
-
 namespace dr1560 { // dr1560: 3.5
   void f(bool b, int n) {
     (b ? throw 0 : n) = (b ? n : throw 0) = 0;
diff --git a/clang/test/CXX/drs/dr20xx.cpp b/clang/test/CXX/drs/dr20xx.cpp
index 6e1c0505a5ecc..56cc1161a00c8 100644
--- a/clang/test/CXX/drs/dr20xx.cpp
+++ b/clang/test/CXX/drs/dr20xx.cpp
@@ -49,18 +49,6 @@ namespace dr2026 { // dr2026: 11
   }
 }
 
-namespace dr2064 { // dr2064: 12
-#if __cplusplus >= 201103L
-  template<typename T> struct X {
-    template<typename U> struct Y {};
-  };
-  template<typename T> void f() {
-    X<decltype(sizeof(T))>::Y<int> y; // ok
-    return X<decltype(sizeof(T))>::f(); // expected-error {{no member named 'f' in 'dr2064::X<unsigned}}
-  }
-#endif
-}
-
 namespace dr2082 { // dr2082: 11
   void test1(int x, int = sizeof(x)); // ok
 #if __cplusplus >= 201103L
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
index 30d8a09d5bc9a..dcf2a046927f9 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c
@@ -41,7 +41,7 @@ void test_core(void) {
   // CHECK-ASM: vlvgg
 
   vd = vec_insert_and_zero(cptrd);
-  // CHECK: [[ZVEC:%[^ ]+]] = insertelement <2 x double> <double undef, double 0.000000e+00>, double {{.*}}, i32 0
+  // CHECK: [[ZVEC:%[^ ]+]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double {{.*}}, i32 0
   // CHECK-ASM: vllezg
 
   vd = vec_revb(vd);
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
index 9fe373b43a8c2..4c7254faedcf6 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c
@@ -194,31 +194,31 @@ void test_core(void) {
   // CHECK-ASM: vlvgg
 
   vsc = vec_insert_and_zero(cptrsc);
-  // CHECK: insertelement <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %{{.*}}, i32 7
+  // CHECK: insertelement <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 poison, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %{{.*}}, i32 7
   // CHECK-ASM: vllezb
   vuc = vec_insert_and_zero(cptruc);
-  // CHECK: insertelement <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %{{.*}}, i32 7
+  // CHECK: insertelement <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 poison, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, i8 %{{.*}}, i32 7
   // CHECK-ASM: vllezb
   vss = vec_insert_and_zero(cptrss);
-  // CHECK: insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 0>, i16 %{{.*}}, i32 3
+  // CHECK: insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 0, i16 0, i16 0, i16 0>, i16 %{{.*}}, i32 3
   // CHECK-ASM: vllezh
   vus = vec_insert_and_zero(cptrus);
-  // CHECK: insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 0>, i16 %{{.*}}, i32 3
+  // CHECK: insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 0, i16 0, i16 0, i16 0>, i16 %{{.*}}, i32 3
   // CHECK-ASM: vllezh
   vsi = vec_insert_and_zero(cptrsi);
-  // CHECK: insertelement <4 x i32> <i32 0, i32 undef, i32 0, i32 0>, i32 %{{.*}}, i32 1
+  // CHECK: insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 %{{.*}}, i32 1
   // CHECK-ASM: vllezf
   vui = vec_insert_and_zero(cptrui);
-  // CHECK: insertelement <4 x i32> <i32 0, i32 undef, i32 0, i32 0>, i32 %{{.*}}, i32 1
+  // CHECK: insertelement <4 x i32> <i32 0, i32 poison, i32 0, i32 0>, i32 %{{.*}}, i32 1
   // CHECK-ASM: vllezf
   vsl = vec_insert_and_zero(cptrsl);
-  // CHECK: insertelement <2 x i64> <i64 undef, i64 0>, i64 %{{.*}}, i32 0
+  // CHECK: insertelement <2 x i64> <i64 poison, i64 0>, i64 %{{.*}}, i32 0
   // CHECK-ASM: vllezg
   vul = vec_insert_and_zero(cptrul);
-  // CHECK: insertelement <2 x i64> <i64 undef, i64 0>, i64 %{{.*}}, i32 0
+  // CHECK: insertelement <2 x i64> <i64 poison, i64 0>, i64 %{{.*}}, i32 0
   // CHECK-ASM: vllezg
   vd = vec_insert_and_zero(cptrd);
-  // CHECK: insertelement <2 x double> <double undef, double 0.000000e+00>, double %{{.*}}, i32 0
+  // CHECK: insertelement <2 x double> <double poison, double 0.000000e+00>, double %{{.*}}, i32 0
   // CHECK-ASM: vllezg
 
   vsc = vec_perm(vsc, vsc, vuc);
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c
index 7b1b4c504782a..4b928ced71c0a 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c
@@ -77,10 +77,10 @@ void test_core(void) {
   // CHECK-ASM: vlvgg
 
   vf = vec_insert_and_zero(cptrf);
-  // CHECK: insertelement <4 x float> <float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00>, float {{.*}}, i32 1
+  // CHECK: insertelement <4 x float> <float 0.000000e+00, float poison, float 0.000000e+00, float 0.000000e+00>, float {{.*}}, i32 1
   // CHECK-ASM: vllezf
   vd = vec_insert_and_zero(cptrd);
-  // CHECK: insertelement <2 x double> <double undef, double 0.000000e+00>, double %{{.*}}, i32 0
+  // CHECK: insertelement <2 x double> <double poison, double 0.000000e+00>, double %{{.*}}, i32 0
   // CHECK-ASM: vllezg
 
   vf = vec_revb(vf);
diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
index 74e46b30a4b02..a1b580f8c56fe 100644
--- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
+++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c
@@ -109,10 +109,10 @@ void test_core(void) {
   // CHECK-ASM: vlvgg
 
   vf = vec_insert_and_zero(cptrf);
-  // CHECK: insertelement <4 x float> <float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00>, float %{{.*}}, i32 1
+  // CHECK: insertelement <4 x float> <float 0.000000e+00, float poison, float 0.000000e+00, float 0.000000e+00>, float %{{.*}}, i32 1
   // CHECK-ASM: vllezf
   vd = vec_insert_and_zero(cptrd);
-  // CHECK: insertelement <2 x double> <double undef, double 0.000000e+00>, double %{{.*}}, i32 0
+  // CHECK: insertelement <2 x double> <double poison, double 0.000000e+00>, double %{{.*}}, i32 0
   // CHECK-ASM: vllezg
 
   vf = vec_perm(vf, vf, vuc);
diff --git a/clang/test/CodeGen/basic-block-sections.c b/clang/test/CodeGen/basic-block-sections.c
index 805539f06f080..70cdeeebb0d3f 100644
--- a/clang/test/CodeGen/basic-block-sections.c
+++ b/clang/test/CodeGen/basic-block-sections.c
@@ -31,14 +31,14 @@ int another(int a) {
 // BB_WORLD: .section .text.world,"ax",@progbits{{$}}
 // BB_WORLD: world:
 // BB_WORLD: .section .text.world,"ax",@progbits,unique
-// BB_WORLD: world.1:
+// BB_WORLD: world.__part.1:
 // BB_WORLD: .section .text.another,"ax",@progbits
 // BB_ALL: .section .text.another,"ax",@progbits,unique
-// BB_ALL: another.1:
+// BB_ALL: another.__part.1:
 // BB_LIST-NOT: .section .text.another,"ax",@progbits,unique
 // BB_LIST: another:
-// BB_LIST-NOT: another.1:
+// BB_LIST-NOT: another.__part.1:
 //
-// UNIQUE: .section .text.world.world.1,
-// UNIQUE: .section .text.another.another.1,
+// UNIQUE: .section .text.world.world.__part.1,
+// UNIQUE: .section .text.another.another.__part.1,
 // ERROR: error:  unable to load basic block sections function list: '{{[Nn]}}o such file or directory'
diff --git a/clang/test/CodeGenCXX/mangle-ms-templates.cpp b/clang/test/CodeGenCXX/mangle-ms-templates.cpp
index c9149a473b6fa..7402d367ae3e9 100644
--- a/clang/test/CodeGenCXX/mangle-ms-templates.cpp
+++ b/clang/test/CodeGenCXX/mangle-ms-templates.cpp
@@ -2,7 +2,6 @@
 // RUN: %clang_cc1 -std=c++11 -fms-compatibility-version=19 -emit-llvm %s -o - -fms-extensions -fdelayed-template-parsing -triple=x86_64-pc-win32 | FileCheck -check-prefix X64 %s
 // RUN: %clang_cc1 -std=c++17 -fms-compatibility-version=19 -emit-llvm %s -o - -fms-extensions -fdelayed-template-parsing -triple=i386-pc-win32 | FileCheck %s
 // RUN: %clang_cc1 -std=c++17 -fms-compatibility-version=19 -emit-llvm %s -o - -fms-extensions -fdelayed-template-parsing -triple=x86_64-pc-win32 | FileCheck -check-prefix X64 %s
-// RUN: %clang_cc1 -std=c++20 -fms-compatibility-version=19 -emit-llvm %s -o - -fms-extensions -fdelayed-template-parsing -triple=x86_64-pc-win32 | FileCheck -check-prefix CXX20-X64 %s
 
 template<typename T>
 class Class {
@@ -328,12 +327,3 @@ void fun_uint128(UInt128<(unsigned __int128)-1>) {}
 // X64: define {{.*}} @"?fun_uint128@@YAXU?$UInt128@$0DPPPPPPPPPPPPPPPAAAAAAAAAAAAAAAB@@@@Z"(
 void fun_uint128(UInt128<(unsigned __int128)9223372036854775807 * (unsigned __int128)9223372036854775807>) {}
 #endif
-
-#if __cplusplus >= 202002L
-template<float> struct Float {};
-// CXX20-X64: define {{.*}} @"?f@@YAXU?$Float@$ADPIAAAAA@@@@Z"(
-void f(Float<1.0f>) {}
-template<auto> struct Auto {};
-// CXX20-X64: define {{.*}} @"?f@@YAXU?$Auto@$MMADPIAAAAA@@@@Z"(
-void f(Auto<1.0f>) {}
-#endif
diff --git a/clang/test/CodeGenCXX/mangle-template.cpp b/clang/test/CodeGenCXX/mangle-template.cpp
index 8326bf658f064..9b5220572c2e3 100644
--- a/clang/test/CodeGenCXX/mangle-template.cpp
+++ b/clang/test/CodeGenCXX/mangle-template.cpp
@@ -226,16 +226,6 @@ namespace test16 {
 namespace cxx20 {
   template<auto> struct A {};
   template<typename T, T V> struct B {};
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AILf3f800000EEE(
-  void f(A<1.0f>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AILd3ff0000000000000EEE(
-  void f(A<1.0>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AILe3fff8000000000000000EEE(
-  void f(A<1.0l>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXtlCiLi0ELi1EEEEE(
-  void f(A<1i>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXtlCdLd0000000000000000ELd3ff0000000000000EEEEE(
-  void f(A<1.0i>) {}
 
   int x;
   // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXadL_ZNS_1xEEEEE(
@@ -255,24 +245,7 @@ namespace cxx20 {
   // CXX20: define {{.*}} @_ZN5cxx201fENS_1BIPKvXadL_ZNS_1xEEEEE(
   void f(B<const void*, (const void*)&x>) {}
 
-  struct Q { int x; } q;
-
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXadsoiL_ZNS_1qEEEEEE(
-  void f(A<&q.x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1BIPiXadsoiL_ZNS_1qEEEEEE(
-  void f(B<int*, &q.x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXadsoKiL_ZNS_1qEEEEEE(
-  void f(A<(const int*)&q.x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1BIPKiXadsoS1_L_ZNS_1qEEEEEE
-  void f(B<const int*, (const int*)&q.x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXcvPvadsoiL_ZNS_1qEEEEEE(
-  void f(A<(void*)&q.x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1BIPvXadsoiL_ZNS_1qEEEEEE(
-  void f(B<void*, (void*)&q.x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXcvPKvadsoiL_ZNS_1qEEEEEE(
-  void f(A<(const void*)&q.x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1BIPKvXadsoiL_ZNS_1qEEEEEE(
-  void f(B<const void*, (const void*)&q.x>) {}
+  struct Q { int x; };
 
   // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXadL_ZNS_1Q1xEEEEE(
   void f(A<&Q::x>) {}
@@ -282,17 +255,6 @@ namespace cxx20 {
   void f(A<(const int Q::*)&Q::x>) {}
   // CXX20: define {{.*}} @_ZN5cxx201fENS_1BIMNS_1QEKiXadL_ZNS1_1xEEEEE(
   void f(B<const int Q::*, (const int Q::*)&Q::x>) {}
-
-  struct R : Q {};
-
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXmcMNS_1REiadL_ZNS_1Q1xEEEEEE(
-  void f(A<(int R::*)&Q::x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1BIMNS_1REiXmcS2_adL_ZNS_1Q1xEEEEEE(
-  void f(B<int R::*, (int R::*)&Q::x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1AIXmcMNS_1REKiadL_ZNS_1Q1xEEEEEE(
-  void f(A<(const int R::*)&Q::x>) {}
-  // CXX20: define {{.*}} @_ZN5cxx201fENS_1BIMNS_1REKiXmcS3_adL_ZNS_1Q1xEEEEEE(
-  void f(B<const int R::*, (const int R::*)&Q::x>) {}
 }
 #endif
 
@@ -380,23 +342,3 @@ namespace fixed_size_parameter_pack {
   template<int ...Ns> void f(A<unsigned, char, long long>::B<0, Ns...>);
   void g() { f<1, 2>({}); }
 }
-
-namespace type_qualifier {
-  template<typename T> using int_t = int;
-  template<typename T> void f(decltype(int_t<T*>() + 1)) {}
-  // FIXME: This mangling doesn't work: we need to mangle the
-  // instantiation-dependent 'int_t' operand.
-  // CHECK: @_ZN14type_qualifier1fIPiEEvDTplcvi_ELi1EE
-  template void f<int*>(int);
-
-  // Note that this template has different constraints but would mangle the
-  // same:
-  //template<typename T> void f(decltype(int_t<typename T::type>() + 1)) {}
-
-  struct impl { using type = void; };
-  template<typename T> using alias = impl;
-  template<typename T> void g(decltype(alias<T*>::type(), 1)) {}
-  // FIXME: Similarly we need to mangle the `T*` in here.
-  // CHECK: @_ZN14type_qualifier1gIPiEEvDTcmcvv_ELi1EE
-  template void g<int*>(int);
-}
diff --git a/clang/test/CodeGenCXX/template-arguments.cpp b/clang/test/CodeGenCXX/template-arguments.cpp
deleted file mode 100644
index fd6f469e88fcc..0000000000000
--- a/clang/test/CodeGenCXX/template-arguments.cpp
+++ /dev/null
@@ -1,81 +0,0 @@
-// RUN: %clang_cc1 -std=c++20 %s -emit-llvm -o - -triple x86_64-linux -DCONSTEXPR= | FileCheck %s
-// RUN: %clang_cc1 -std=c++20 %s -emit-llvm -o - -triple x86_64-linux -DCONSTEXPR=constexpr | FileCheck %s --check-prefix=CONST
-
-template<typename T> CONSTEXPR T id(T v) { return v; }
-template<auto V> auto value = id(V);
-
-// CHECK: call {{.*}} @_Z2idIiET_S0_(i32 1)
-// CONST: @_Z5valueILi1EE = weak_odr {{.*}} i32 1,
-template int value<1>;
-
-// CHECK: call {{.*}} @_Z2idIyET_S0_(i64 -1)
-// CONST: @_Z5valueILy18446744073709551615EE = weak_odr {{.*}} i64 -1,
-template unsigned long long value<-1ULL>;
-
-// CHECK: call {{.*}} @_Z2idIfET_S0_(float 1.000000e+00)
-// CONST: @_Z5valueILf3f800000EE = weak_odr {{.*}} float 1.000000e+00,
-template float value<1.0f>; 
-// CHECK: call {{.*}} @_Z2idIdET_S0_(double 1.000000e+00)
-// CONST: @_Z5valueILd3ff0000000000000EE = weak_odr {{.*}} double 1.000000e+00,
-template double value<1.0>;
-
-int n;
-// CHECK: call {{.*}} @_Z2idIPiET_S1_(i32* @n)
-// CONST: @_Z5valueIXadL_Z1nEEE = weak_odr {{.*}} i32* @n,
-template int *value<&n>;
-
-struct A { int a[3]; } a;
-// CHECK: call {{.*}} @_Z2idIPiET_S1_(i32* getelementptr inbounds (%struct.A, %struct.A* @a, i32 0, i32 0, i32 0))
-// CONST: @_Z5valueIXadsoiL_Z1aEEEE = weak_odr {{.*}} i32* getelementptr inbounds (%struct.A, %struct.A* @a, i32 0, i32 0, i32 0),
-template int *value<&a.a[0]>;
-// CHECK: call {{.*}} @_Z2idIPiET_S1_(i32* bitcast (i8* getelementptr (i8, i8* bitcast (%struct.A* @a to i8*), i64 4) to i32*))
-// CONST: @_Z5valueIXadsoiL_Z1aE4EEE = weak_odr {{.*}} i32* bitcast (i8* getelementptr (i8, i8* bitcast (%struct.A* @a to i8*), i64 4) to i32*),
-template int *value<&a.a[1]>;
-// CHECK: call {{.*}} @_Z2idIPiET_S1_(i32* bitcast (i8* getelementptr (i8, i8* bitcast (%struct.A* @a to i8*), i64 8) to i32*))
-// CONST: @_Z5valueIXadsoiL_Z1aE8EEE = weak_odr {{.*}} i32* bitcast (i8* getelementptr (i8, i8* bitcast (%struct.A* @a to i8*), i64 8) to i32*),
-template int *value<&a.a[2]>;
-// CHECK: call {{.*}} @_Z2idIPiET_S1_(i32* bitcast (i8* getelementptr (i8, i8* bitcast (%struct.A* @a to i8*), i64 12) to i32*))
-// CONST: @_Z5valueIXadsoiL_Z1aE12pEEE = weak_odr {{.*}} i32* bitcast (i8* getelementptr (i8, i8* bitcast (%struct.A* @a to i8*), i64 12) to i32*),
-template int *value<&a.a[3]>;
-
-struct B { int x, y; };
-// CHECK: call {{.*}} @_Z2idIM1BiET_S2_(i64 0)
-// CONST: @_Z5valueIXadL_ZN1B1xEEEE = weak_odr {{.*}} i64 0,
-template int B::*value<&B::x>;
-// CHECK: call {{.*}} @_Z2idIM1BiET_S2_(i64 4)
-// CONST: @_Z5valueIXadL_ZN1B1yEEEE = weak_odr {{.*}} i64 4,
-template int B::*value<&B::y>;
-
-struct C : A, B { int z; };
-// CHECK: call {{.*}} @_Z2idIM1CiET_S2_(i64 12)
-// CONST: @_Z5valueIXmcM1CiadL_ZN1B1xEE12EEE = weak_odr {{.*}} i64 12,
-template int C::*value<(int C::*)&B::x>;
-// CHECK: call {{.*}} @_Z2idIM1BiET_S2_(i64 8)
-// CONST: @_Z5valueIXmcM1BiadL_ZN1C1zEEn12EEE = weak_odr {{.*}} i64 8,
-template int B::*value<(int B::*)&C::z>;
-
-// CHECK: store i32 1, i32*
-// CHECK: store i32 2, i32*
-// CHECK: bitcast { i32, i32 }* %{{.*}} to i64*
-// CHECK: load i64,
-// CHECK: call {{.*}} @_Z2idICiET_S1_(i64 %
-// CONST: @_Z5valueIXtlCiLi1ELi2EEEE = weak_odr {{.*}} { i32, i32 } { i32 1, i32 2 },
-template _Complex int value<1 + 2j>;
-
-// CHECK: store float 1.000000e+00, float*
-// CHECK: store float 2.000000e+00, float*
-// CHECK: bitcast { float, float }* %{{.*}} to <2 x float>*
-// CHECK: load <2 x float>,
-// CHECK: call {{.*}} @_Z2idICfET_S1_(<2 x float> %
-// CONST: @_Z5valueIXtlCfLf3f800000ELf40000000EEEE = weak_odr {{.*}} { float, float } { float 1.000000e+00, float 2.000000e+00 },
-template _Complex float value<1.0f + 2.0fj>;
-
-using V3i __attribute__((ext_vector_type(3))) = int;
-// CHECK: call {{.*}} @_Z2idIDv3_iET_S1_(<3 x i32> <i32 1, i32 2, i32 3>)
-// CONST: @_Z5valueIXtlDv3_iLi1ELi2ELi3EEEE = weak_odr {{.*}} <3 x i32> <i32 1, i32 2, i32 3>
-template V3i value<V3i{1, 2, 3}>;
-
-using V3f [[gnu::vector_size(12)]] = float;
-// CHECK: call {{.*}} @_Z2idIDv3_fET_S1_(<3 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>)
-// CONST: @_Z5valueIXtlDv3_fLf3f800000ELf40000000ELf40400000EEEE = weak_odr {{.*}} <3 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>
-template V3f value<V3f{1, 2, 3}>;
diff --git a/clang/test/CodeGenObjC/objc-dispatch-null-check.m b/clang/test/CodeGenObjC/objc-dispatch-null-check.m
new file mode 100644
index 0000000000000..0c43955db2fa9
--- /dev/null
+++ b/clang/test/CodeGenObjC/objc-dispatch-null-check.m
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -triple x86_64-apple-darwin9 -fobjc-dispatch-method=non-legacy -fobjc-arc -emit-llvm -o - %s | FileCheck %s
+
+// CHECK: %[[STRUCT_STRONG:.*]] = type { i8* }
+
+typedef struct {
+  id x;
+} Strong;
+
+Strong getStrong(void);
+
+@interface I0
+- (void)passStrong:(Strong)a;
+@end
+
+// CHECK-LABEL: define void @test0(
+// CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_STRONG]], align 8
+// CHECK: %[[CALL:.*]] = call i8* @getStrong()
+// CHECK-NEXT: %[[COERCE_DIVE:.*]] = getelementptr inbounds %[[STRUCT_STRONG]], %[[STRUCT_STRONG]]* %[[AGG_TMP]], i32 0, i32 0
+// CHECK-NEXT: store i8* %[[CALL]], i8** %[[COERCE_DIVE]], align 8
+
+// CHECK: %[[MSGSEND_FN:.*]] = load i8*, i8**
+// CHECK: %[[V5:.*]] = bitcast i8* %[[MSGSEND_FN]] to void (i8*, i8*, i8*)*
+// CHECK: %[[COERCE_DIVE1:.*]] = getelementptr inbounds %[[STRUCT_STRONG]], %[[STRUCT_STRONG]]* %[[AGG_TMP]], i32 0, i32 0
+// CHECK: %[[V6:.*]] = load i8*, i8** %[[COERCE_DIVE1]], align 8
+// CHECK: call void %[[V5]]({{.*}}, i8* %[[V6]])
+// CHECK: br
+
+// CHECK: %[[V7:.*]] = bitcast %[[STRUCT_STRONG]]* %[[AGG_TMP]] to i8**
+// CHECK: call void @__destructor_8_s0(i8** %[[V7]])
+// CHECK: br
+
+void test0(I0 *a) {
+  [a passStrong:getStrong()];
+}
diff --git a/clang/test/CodeGenObjC/strong-in-c-struct.m b/clang/test/CodeGenObjC/strong-in-c-struct.m
index 4e098c352ab56..d9e503feafd28 100644
--- a/clang/test/CodeGenObjC/strong-in-c-struct.m
+++ b/clang/test/CodeGenObjC/strong-in-c-struct.m
@@ -91,6 +91,7 @@
 
 @interface C
 - (StrongSmall)getStrongSmall;
+- (void)m:(StrongSmall)s;
 + (StrongSmall)getStrongSmallClass;
 @end
 
@@ -944,4 +945,21 @@ id test_assignment1(void) {
   calleeStrongSmall(g2 = g1);
 }
 
+// CHECK-LABEL: define void @test_null_reveiver(
+// CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_STRONGSMALL]], align 8
+// CHECK: br i1
+
+// CHECK: %[[V7:.*]] = bitcast %[[STRUCT_STRONGSMALL]]* %[[AGG_TMP]] to [2 x i64]*
+// CHECK: %[[V8:.*]] = load [2 x i64], [2 x i64]* %[[V7]], align 8
+// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void ({{.*}}, [2 x i64] %[[V8]])
+// CHECK: br
+
+// CHECK: %[[V9:.*]] = bitcast %[[STRUCT_STRONGSMALL]]* %[[AGG_TMP]] to i8**
+// CHECK: call void @__destructor_8_s8(i8** %[[V9]]) #4
+// CHECK: br
+
+void test_null_reveiver(C *c) {
+  [c m:getStrongSmall()];
+}
+
 #endif /* USESTRUCT */
diff --git a/clang/test/CodeGenObjC/weak-in-c-struct.m b/clang/test/CodeGenObjC/weak-in-c-struct.m
index 4bebc20625eb8..ac844a8a89355 100644
--- a/clang/test/CodeGenObjC/weak-in-c-struct.m
+++ b/clang/test/CodeGenObjC/weak-in-c-struct.m
@@ -42,6 +42,10 @@
 // ARM64: %[[V3:.*]] = bitcast i8* %[[V2]] to i8**
 // ARM64: call void @llvm.objc.destroyWeak(i8** %[[V3]])
 
+@interface C
+- (void)m:(Weak)a;
+@end
+
 void test_constructor_destructor_Weak(void) {
   Weak t;
 }
@@ -191,3 +195,18 @@ void test_argument_Weak(Weak *a) {
 Weak test_return_Weak(Weak *a) {
   return *a;
 }
+
+// COMMON-LABEL: define void @test_null_receiver(
+// COMMON: %[[AGG_TMP:.*]] = alloca %[[STRUCT_WEAK]]
+// COMMON: br i1
+
+// COMMON: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_WEAK]]*)*)({{.*}}, %[[STRUCT_WEAK]]* %[[AGG_TMP]])
+// COMMON: br
+
+// COMMON: %[[V6:.*]] = bitcast %[[STRUCT_WEAK]]* %[[AGG_TMP]] to i8**
+// COMMON: call void @__destructor_{{.*}}(i8** %[[V6]])
+// COMMON: br
+
+void test_null_receiver(C *c) {
+  [c m:getWeak()];
+}
diff --git a/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm b/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm
index bd89c8629a7ce..efaced63aa42a 100644
--- a/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm
+++ b/clang/test/CodeGenObjCXX/objc-struct-cxx-abi.mm
@@ -13,6 +13,7 @@
 // CHECK: %[[STRUCT_STRONG:.*]] = type { i8* }
 // CHECK: %[[STRUCT_S:.*]] = type { i8* }
 // CHECK: %[[STRUCT_CONTAINSNONTRIVIAL:.*]] = type { %{{.*}}, i8* }
+// CHECK: %[[STRUCT_NONTRIVIAL:.*]] = type { i32* }
 
 #ifdef TRIVIALABI
 struct __attribute__((trivial_abi)) StrongWeak {
@@ -69,6 +70,12 @@ struct __attribute__((trivial_abi)) S {
   id f1;
 };
 
+@interface C
+- (void)passStrong:(Strong)a;
+- (void)passStrongWeak:(StrongWeak)a;
+- (void)passNonTrivial:(NonTrivial)a;
+@end
+
 // CHECK: define void @_Z19testParamStrongWeak10StrongWeak(%[[STRUCT_STRONGWEAK]]* %{{.*}})
 // CHECK: call %struct.StrongWeak* @_ZN10StrongWeakD1Ev(
 // CHECK-NEXT: ret void
@@ -207,3 +214,49 @@ void testCallContainsNonTrivial(ContainsNonTrivial *a) {
 Strong D0::m0() { return {}; }
 
 }
+
+namespace testNullReceiver {
+
+// CHECK-LABEL: define void @_ZN16testNullReceiver5test0EP1C(
+// CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_STRONG]], align 8
+// CHECK: br i1
+
+// CHECK: %[[COERCE_DIVE:.*]] = getelementptr inbounds %[[STRUCT_STRONG]], %[[STRUCT_STRONG]]* %[[AGG_TMP]], i32 0, i32 0
+// CHECK: %[[V7:.*]] = load i8*, i8** %[[COERCE_DIVE]], align 8
+// CHECK: %[[COERCE_VAL_PI:.*]] = ptrtoint i8* %[[V7]] to i64
+// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, i64)*)({{.*}}, i64 %[[COERCE_VAL_PI]])
+// CHECK: br
+
+// CHECK: %[[CALL1:.*]] = call %[[STRUCT_STRONG]]* @_ZN6StrongD1Ev(%[[STRUCT_STRONG]]* nonnull dereferenceable(8) %[[AGG_TMP]])
+// CHECK: br
+
+void test0(C *c) {
+  [c passStrong:Strong()];
+}
+
+// CHECK-LABEL: define void @_ZN16testNullReceiver5test1EP1C(
+// CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_STRONGWEAK]], align 8
+// CHECK: br i1
+
+// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void ({{.*}}, %[[STRUCT_STRONGWEAK]]* %[[AGG_TMP]])
+// CHECK: br
+
+// CHECK: %[[CALL1:.*]] = call %[[STRUCT_STRONGWEAK]]* @_ZN10StrongWeakD1Ev(%[[STRUCT_STRONGWEAK]]* nonnull dereferenceable(16) %[[AGG_TMP]])
+// CHECK: br
+
+void test1(C *c) {
+  [c passStrongWeak:StrongWeak()];
+}
+
+// No null check needed.
+
+// CHECK-LABEL: define void @_ZN16testNullReceiver5test2EP1C(
+// CHECK: %[[AGG_TMP:.*]] = alloca %[[STRUCT_NONTRIVIAL]], align 8
+// CHECK: call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %[[STRUCT_NONTRIVIAL]]*)*)({{.*}}, %[[STRUCT_NONTRIVIAL]]* %[[AGG_TMP]])
+// CHECK-NEXT: call %[[STRUCT_NONTRIVIAL]]* @_ZN10NonTrivialD1Ev(%[[STRUCT_NONTRIVIAL]]* nonnull dereferenceable(8) %[[AGG_TMP]])
+
+void test2(C *c) {
+  [c passNonTrivial:NonTrivial()];
+}
+
+}
diff --git a/clang/test/CodeGenSYCL/accessor_inheritance.cpp b/clang/test/CodeGenSYCL/accessor_inheritance.cpp
index 0233b80483b55..f0196d8be0e8e 100644
--- a/clang/test/CodeGenSYCL/accessor_inheritance.cpp
+++ b/clang/test/CodeGenSYCL/accessor_inheritance.cpp
@@ -23,7 +23,7 @@ int main() {
 // Check kernel parameters
 // CHECK: %[[RANGE_TYPE:"struct.*cl::sycl::range"]]
 // CHECK: %[[ID_TYPE:"struct.*cl::sycl::id"]]
-// CHECK: define spir_kernel void @_ZTSZ4mainE6kernel
+// CHECK: define {{.*}}spir_kernel void @_ZTSZ4mainE6kernel
 // CHECK-SAME: i32 [[ARG_A:%[a-zA-Z0-9_]+]],
 // CHECK-SAME: i32 [[ARG_B:%[a-zA-Z0-9_]+]],
 // CHECK-SAME: i8 addrspace(1)* [[ACC1_DATA:%[a-zA-Z0-9_]+]],
diff --git a/clang/test/CodeGenSYCL/address-space-new.cpp b/clang/test/CodeGenSYCL/address-space-new.cpp
index 788d7e0e2f13a..5e332e739b77c 100644
--- a/clang/test/CodeGenSYCL/address-space-new.cpp
+++ b/clang/test/CodeGenSYCL/address-space-new.cpp
@@ -103,7 +103,7 @@ void test() {
   //
   Y yy;
   baz(yy);
-  // CHECK: define spir_func void @{{.*}}baz{{.*}}
+  // CHECK: define {{.*}}spir_func void @{{.*}}baz{{.*}}
   // CHECK: %[[FIRST:[a-zA-Z0-9]+]] = bitcast %struct.{{.*}}.Y addrspace(4)* %{{.*}} to i8 addrspace(4)*
   // CHECK: %[[OFFSET:[a-zA-Z0-9]+]].ptr = getelementptr inbounds i8, i8 addrspace(4)* %[[FIRST]], i64 8
   // CHECK: %[[SECOND:[a-zA-Z0-9]+]] = bitcast i8 addrspace(4)* %[[OFFSET]].ptr to %struct.{{.*}}.HasX addrspace(4)*
diff --git a/clang/test/CodeGenSYCL/address-space-of-returns.cpp b/clang/test/CodeGenSYCL/address-space-of-returns.cpp
index 3b56e34bd5bed..a0b477c4e6d51 100644
--- a/clang/test/CodeGenSYCL/address-space-of-returns.cpp
+++ b/clang/test/CodeGenSYCL/address-space-of-returns.cpp
@@ -26,7 +26,7 @@ A ret_agg() {
   A a;
   return a;
 }
-// CHECK: define spir_func void @{{.*}}ret_agg{{.*}}(%struct.{{.*}}.A addrspace(4)* {{.*}} %agg.result)
+// CHECK: define {{.*}}spir_func void @{{.*}}ret_agg{{.*}}(%struct.{{.*}}.A addrspace(4)* {{.*}} %agg.result)
 
 template <typename name, typename Func>
 __attribute__((sycl_kernel)) void kernel_single_task(const Func &kernelFunc) {
diff --git a/clang/test/CodeGenSYCL/address-space-parameter-conversions.cpp b/clang/test/CodeGenSYCL/address-space-parameter-conversions.cpp
index cbb645009bb34..cc3ad88b64940 100644
--- a/clang/test/CodeGenSYCL/address-space-parameter-conversions.cpp
+++ b/clang/test/CodeGenSYCL/address-space-parameter-conversions.cpp
@@ -1,20 +1,20 @@
 // RUN: %clang_cc1 -fsycl -fsycl-is-device -triple spir64-unknown-unknown-sycldevice -disable-llvm-passes -emit-llvm %s -o - | FileCheck %s
 void bar(int & Data) {}
-// CHECK-DAG: define spir_func void @[[RAW_REF:[a-zA-Z0-9_]+]](i32 addrspace(4)* align 4 dereferenceable(4) %
+// CHECK-DAG: define {{.*}}spir_func void @[[RAW_REF:[a-zA-Z0-9_]+]](i32 addrspace(4)* align 4 dereferenceable(4) %
 void bar2(int & Data) {}
-// CHECK-DAG: define spir_func void @[[RAW_REF2:[a-zA-Z0-9_]+]](i32 addrspace(4)* align 4 dereferenceable(4) %
+// CHECK-DAG: define {{.*}}spir_func void @[[RAW_REF2:[a-zA-Z0-9_]+]](i32 addrspace(4)* align 4 dereferenceable(4) %
 void bar(__attribute__((opencl_local)) int &Data) {}
-// CHECK-DAG: define spir_func void [[LOC_REF:@[a-zA-Z0-9_]+]](i32 addrspace(3)* align 4 dereferenceable(4) %
+// CHECK-DAG: define {{.*}}spir_func void [[LOC_REF:@[a-zA-Z0-9_]+]](i32 addrspace(3)* align 4 dereferenceable(4) %
 void bar3(__attribute__((opencl_global)) int &Data) {}
-// CHECK-DAG: define spir_func void @[[GLOB_REF:[a-zA-Z0-9_]+]](i32 addrspace(1)* align 4 dereferenceable(4) %
+// CHECK-DAG: define {{.*}}spir_func void @[[GLOB_REF:[a-zA-Z0-9_]+]](i32 addrspace(1)* align 4 dereferenceable(4) %
 void foo(int * Data) {}
-// CHECK-DAG: define spir_func void @[[RAW_PTR:[a-zA-Z0-9_]+]](i32 addrspace(4)* %
+// CHECK-DAG: define {{.*}}spir_func void @[[RAW_PTR:[a-zA-Z0-9_]+]](i32 addrspace(4)* %
 void foo2(int * Data) {}
-// CHECK-DAG: define spir_func void @[[RAW_PTR2:[a-zA-Z0-9_]+]](i32 addrspace(4)* %
+// CHECK-DAG: define {{.*}}spir_func void @[[RAW_PTR2:[a-zA-Z0-9_]+]](i32 addrspace(4)* %
 void foo(__attribute__((opencl_local)) int *Data) {}
-// CHECK-DAG: define spir_func void [[LOC_PTR:@[a-zA-Z0-9_]+]](i32 addrspace(3)* %
+// CHECK-DAG: define {{.*}}spir_func void [[LOC_PTR:@[a-zA-Z0-9_]+]](i32 addrspace(3)* %
 void foo3(__attribute__((opencl_global)) int *Data) {}
-// CHECK-DAG: define spir_func void @[[GLOB_PTR:[a-zA-Z0-9_]+]](i32 addrspace(1)* %
+// CHECK-DAG: define {{.*}}spir_func void @[[GLOB_PTR:[a-zA-Z0-9_]+]](i32 addrspace(1)* %
 
 template<typename T>
 void tmpl(T t){}
diff --git a/clang/test/CodeGenSYCL/basic-kernel-wrapper.cpp b/clang/test/CodeGenSYCL/basic-kernel-wrapper.cpp
index 750ca8fe0908e..b381dad7b6fe3 100644
--- a/clang/test/CodeGenSYCL/basic-kernel-wrapper.cpp
+++ b/clang/test/CodeGenSYCL/basic-kernel-wrapper.cpp
@@ -19,7 +19,7 @@ int main() {
   return 0;
 }
 
-// CHECK: define spir_kernel void @{{.*}}kernel_function
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_function
 // CHECK-SAME: i32 addrspace(1)* [[MEM_ARG:%[a-zA-Z0-9_]+]],
 // CHECK-SAME: %"struct.{{.*}}.cl::sycl::range"* byval{{.*}}align 4 [[ACC_RANGE:%[a-zA-Z0-9_]+_1]],
 // CHECK-SAME: %"struct.{{.*}}.cl::sycl::range"* byval{{.*}}align 4 [[MEM_RANGE:%[a-zA-Z0-9_]+_2]],
diff --git a/clang/test/CodeGenSYCL/device-functions.cpp b/clang/test/CodeGenSYCL/device-functions.cpp
index 908c5647c6925..ff5db052a233f 100644
--- a/clang/test/CodeGenSYCL/device-functions.cpp
+++ b/clang/test/CodeGenSYCL/device-functions.cpp
@@ -21,7 +21,7 @@ int main() {
   kernel_single_task<class fake_kernel>([]() { foo(); });
   return 0;
 }
-// CHECK: define spir_kernel void @_ZTSZ4mainE11fake_kernel()
+// CHECK: define {{.*}}spir_kernel void @_ZTSZ4mainE11fake_kernel()
 // CHECK: define internal spir_func void @"_ZZ4mainENK3$_0clEv"(%"class.{{.*}}.anon" addrspace(4)* {{[^,]*}} %this)
-// CHECK: define spir_func void @_Z3foov()
+// CHECK: define {{.*}}spir_func void @_Z3foov()
 // CHECK: define linkonce_odr spir_func i32 @_Z3barIiET_S0_(i32 %arg)
diff --git a/clang/test/CodeGenSYCL/device-indirectly-callable-attr.cpp b/clang/test/CodeGenSYCL/device-indirectly-callable-attr.cpp
index 5310a067c0e9e..d70ebb277c4e3 100644
--- a/clang/test/CodeGenSYCL/device-indirectly-callable-attr.cpp
+++ b/clang/test/CodeGenSYCL/device-indirectly-callable-attr.cpp
@@ -7,10 +7,10 @@ void foo() {
   helper();
 }
 
-// CHECK: define spir_func void @{{.*foo.*}}() #[[ATTRS_INDIR_CALL:[0-9]+]]
+// CHECK: define {{.*}}spir_func void @{{.*foo.*}}() #[[ATTRS_INDIR_CALL:[0-9]+]]
 // CHECK: call spir_func void @{{.*helper.*}}()
 //
-// CHECK: define spir_func void @{{.*helper.*}}() #[[ATTRS_NOT_INDIR_CALL:[0-9]+]]
+// CHECK: define {{.*}}spir_func void @{{.*helper.*}}() #[[ATTRS_NOT_INDIR_CALL:[0-9]+]]
 //
 
 int bar20(int a) { return a + 20; }
@@ -18,7 +18,7 @@ int bar20(int a) { return a + 20; }
 class A {
 public:
   // CHECK-DAG: define linkonce_odr spir_func void @_ZN1A3fooEv{{.*}}#[[ATTRS_INDIR_CALL]]
-  // CHECK-DAG: define spir_func i32 @_Z5bar20{{.*}}#[[ATTRS_NOT_INDIR_CALL]]
+  // CHECK-DAG: define {{.*}}spir_func i32 @_Z5bar20{{.*}}#[[ATTRS_NOT_INDIR_CALL]]
   [[intel::device_indirectly_callable]] void foo() { bar20(10); }
 
   // CHECK-DAG: define linkonce_odr spir_func void @_ZN1AC1Ev{{.*}}#[[ATTRS_INDIR_CALL_1:[0-9]+]]
diff --git a/clang/test/CodeGenSYCL/emit-kernel-in-virtual-func.cpp b/clang/test/CodeGenSYCL/emit-kernel-in-virtual-func.cpp
index 2c4734b509c60..53e88969a3efe 100644
--- a/clang/test/CodeGenSYCL/emit-kernel-in-virtual-func.cpp
+++ b/clang/test/CodeGenSYCL/emit-kernel-in-virtual-func.cpp
@@ -26,5 +26,4 @@ int main() {
 }
 
 // Ensure that the SPIR-Kernel function is actually emitted.
-// CHECK: define spir_kernel void @_ZTSZN7DERIVEDIiE10initializeEvE2FF
-
+// CHECK: define {{.*}}spir_kernel void @_ZTSZN7DERIVEDIiE10initializeEvE2FF
diff --git a/clang/test/CodeGenSYCL/emit-kernel-in-virtual-func2.cpp b/clang/test/CodeGenSYCL/emit-kernel-in-virtual-func2.cpp
index 15d11b379fa2d..22cbde55c5839 100644
--- a/clang/test/CodeGenSYCL/emit-kernel-in-virtual-func2.cpp
+++ b/clang/test/CodeGenSYCL/emit-kernel-in-virtual-func2.cpp
@@ -31,5 +31,4 @@ int main() {
 }
 
 // Ensure that the SPIR-Kernel function is actually emitted.
-// CHECK: define spir_kernel void @_ZTSZ2TTIiEvvE2PP
-
+// CHECK: define {{.*}}spir_kernel void @_ZTSZ2TTIiEvvE2PP
diff --git a/clang/test/CodeGenSYCL/esimd-accessor-ptr-md.cpp b/clang/test/CodeGenSYCL/esimd-accessor-ptr-md.cpp
index c33526ff5619c..8a9e92b639a18 100644
--- a/clang/test/CodeGenSYCL/esimd-accessor-ptr-md.cpp
+++ b/clang/test/CodeGenSYCL/esimd-accessor-ptr-md.cpp
@@ -30,7 +30,7 @@ void test(int val) {
   });
 
   // --- Name
-  // CHECK-LABEL: define spir_kernel void @"_ZTSZZ4testiENK3$_0clERN2cl4sycl7handlerEE12esimd_kernel"(
+  // CHECK-LABEL: define {{.*}}spir_kernel void @"_ZTSZZ4testiENK3$_0clERN2cl4sycl7handlerEE12esimd_kernel"(
   // --- Signature
   // CHECK:   i32 addrspace(1)* "VCArgumentDesc"="buffer_t" "VCArgumentIOKind"="0" "VCArgumentKind"="2" %_arg_,
   // CHECK:   i32 "VCArgumentDesc" "VCArgumentIOKind"="0" "VCArgumentKind"="0" %_arg_1,
diff --git a/clang/test/CodeGenSYCL/esimd_metadata1.cpp b/clang/test/CodeGenSYCL/esimd_metadata1.cpp
index 39a424c75bf63..5699a68583b3e 100644
--- a/clang/test/CodeGenSYCL/esimd_metadata1.cpp
+++ b/clang/test/CodeGenSYCL/esimd_metadata1.cpp
@@ -15,7 +15,7 @@ void kernel(const Func &f) __attribute__((sycl_kernel)) {
 
 void bar() {
   kernel<class MyKernel>([=]() __attribute__((sycl_explicit_simd)){});
-  // CHECK: define spir_kernel void @_ZTSZ3barvE8MyKernel() {{.*}} !sycl_explicit_simd ![[EMPTY:[0-9]+]] !intel_reqd_sub_group_size ![[REQD_SIZE:[0-9]+]]
+  // CHECK: define {{.*}}spir_kernel void @_ZTSZ3barvE8MyKernel() {{.*}} !sycl_explicit_simd ![[EMPTY:[0-9]+]] !intel_reqd_sub_group_size ![[REQD_SIZE:[0-9]+]]
 }
 
 // CHECK: !spirv.Source = !{[[LANG:![0-9]+]]}
diff --git a/clang/test/CodeGenSYCL/esimd_metadata2.cpp b/clang/test/CodeGenSYCL/esimd_metadata2.cpp
index c14b0af75f3c1..ed88231692327 100644
--- a/clang/test/CodeGenSYCL/esimd_metadata2.cpp
+++ b/clang/test/CodeGenSYCL/esimd_metadata2.cpp
@@ -11,9 +11,9 @@ __attribute__((sycl_device)) void shared_func() { shared_func_decl(); }
 
 __attribute__((sycl_device)) __attribute__((sycl_explicit_simd)) void esimd_func() { shared_func(); }
 
-// CHECK-ESIMD-DAG: define spir_kernel void @{{.*}}kernel_cm() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {{.*}} !intel_reqd_sub_group_size ![[SGSIZE1:[0-9]+]] {{.*}}{
-// CHECK-ESIMD-DAG: define spir_func void @{{.*}}esimd_funcv() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {
-// CHECK-ESIMD-DAG: define spir_func void @{{.*}}shared_funcv() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {
+// CHECK-ESIMD-DAG: define {{.*}}spir_kernel void @{{.*}}kernel_cm() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {{.*}} !intel_reqd_sub_group_size ![[SGSIZE1:[0-9]+]] {{.*}}{
+// CHECK-ESIMD-DAG: define {{.*}}spir_func void @{{.*}}esimd_funcv() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {
+// CHECK-ESIMD-DAG: define {{.*}}spir_func void @{{.*}}shared_funcv() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {
 // CHECK-ESIMD-DAG: define linkonce_odr spir_func void @_ZN12ESIMDFunctorclEv({{.*}}) #{{[0-9]+}} {{.*}} !sycl_explicit_simd !{{[0-9]+}} {
 // CHECK-ESIMD-DAG: declare spir_func void @{{.*}}shared_func_declv() #{{[0-9]+}}
 
diff --git a/clang/test/CodeGenSYCL/esimd_metadata3.cpp b/clang/test/CodeGenSYCL/esimd_metadata3.cpp
index 02885b1b478db..f34119f4085eb 100644
--- a/clang/test/CodeGenSYCL/esimd_metadata3.cpp
+++ b/clang/test/CodeGenSYCL/esimd_metadata3.cpp
@@ -3,5 +3,5 @@
 __attribute__((sycl_device)) void funcWithSpirvIntrin() {}
 __attribute__((sycl_device)) __attribute__((sycl_explicit_simd)) void standaloneCmFunc() { funcWithSpirvIntrin(); }
 
-// CHECK-ESIMD-DAG: define spir_func void @{{.*}}funcWithSpirvIntrinv() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {
-// CHECK-ESIMD-DAG: define spir_func void @{{.*}}standaloneCmFuncv() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {
+// CHECK-ESIMD-DAG: define {{.*}}spir_func void @{{.*}}funcWithSpirvIntrinv() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {
+// CHECK-ESIMD-DAG: define {{.*}}spir_func void @{{.*}}standaloneCmFuncv() #{{[0-9]+}} !sycl_explicit_simd !{{[0-9]+}} {
diff --git a/clang/test/CodeGenSYCL/image_accessor.cpp b/clang/test/CodeGenSYCL/image_accessor.cpp
index 766667b8628dc..817fb7eec7095 100644
--- a/clang/test/CodeGenSYCL/image_accessor.cpp
+++ b/clang/test/CodeGenSYCL/image_accessor.cpp
@@ -7,27 +7,27 @@
 // RUN: FileCheck < %t.ll --enable-var-scope %s --check-prefix=CHECK-3DWO
 //
 // CHECK-1DRO: %opencl.image1d_ro_t = type opaque
-// CHECK-1DRO: define spir_kernel void @{{.*}}(%opencl.image1d_ro_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
+// CHECK-1DRO: define {{.*}}spir_kernel void @{{.*}}(%opencl.image1d_ro_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
 // CHECK-1DRO: call spir_func void @{{.*}}__init{{.*}}(%{{.*}}cl::sycl::accessor{{.*}} %{{[0-9]+}}, %opencl.image1d_ro_t addrspace(1)* %{{[0-9]+}})
 //
 // CHECK-2DRO: %opencl.image2d_ro_t = type opaque
-// CHECK-2DRO: define spir_kernel void @{{.*}}(%opencl.image2d_ro_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
+// CHECK-2DRO: define {{.*}}spir_kernel void @{{.*}}(%opencl.image2d_ro_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
 // CHECK-2DRO: call spir_func void @{{.*}}__init{{.*}}(%{{.*}}cl::sycl::accessor{{.*}} %{{[0-9]+}}, %opencl.image2d_ro_t addrspace(1)* %{{[0-9]+}})
 //
 // CHECK-3DRO: %opencl.image3d_ro_t = type opaque
-// CHECK-3DRO: define spir_kernel void @{{.*}}(%opencl.image3d_ro_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
+// CHECK-3DRO: define {{.*}}spir_kernel void @{{.*}}(%opencl.image3d_ro_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
 // CHECK-3DRO: call spir_func void @{{.*}}__init{{.*}}(%{{.*}}cl::sycl::accessor{{.*}} %{{[0-9]+}}, %opencl.image3d_ro_t addrspace(1)* %{{[0-9]+}})
 //
 // CHECK-1DWO: %opencl.image1d_wo_t = type opaque
-// CHECK-1DWO: define spir_kernel void @{{.*}}(%opencl.image1d_wo_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
+// CHECK-1DWO: define {{.*}}spir_kernel void @{{.*}}(%opencl.image1d_wo_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
 // CHECK-1DWO: call spir_func void @{{.*}}__init{{.*}}(%{{.*}}cl::sycl::accessor{{.*}} %{{[0-9]+}}, %opencl.image1d_wo_t addrspace(1)* %{{[0-9]+}})
 //
 // CHECK-2DWO: %opencl.image2d_wo_t = type opaque
-// CHECK-2DWO: define spir_kernel void @{{.*}}(%opencl.image2d_wo_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
+// CHECK-2DWO: define {{.*}}spir_kernel void @{{.*}}(%opencl.image2d_wo_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
 // CHECK-2DWO: call spir_func void @{{.*}}__init{{.*}}(%{{.*}}cl::sycl::accessor{{.*}} %{{[0-9]+}}, %opencl.image2d_wo_t addrspace(1)* %{{[0-9]+}})
 //
 // CHECK-3DWO: %opencl.image3d_wo_t = type opaque
-// CHECK-3DWO: define spir_kernel void @{{.*}}(%opencl.image3d_wo_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
+// CHECK-3DWO: define {{.*}}spir_kernel void @{{.*}}(%opencl.image3d_wo_t addrspace(1)* [[IMAGE_ARG:%[a-zA-Z0-9_]+]])
 // CHECK-3DWO: call spir_func void @{{.*}}__init{{.*}}(%{{.*}}cl::sycl::accessor{{.*}} %{{[0-9]+}}, %opencl.image3d_wo_t addrspace(1)* %{{[0-9]+}})
 //
 // TODO: Add tests for the image_array opencl datatype support.
diff --git a/clang/test/CodeGenSYCL/inheritance.cpp b/clang/test/CodeGenSYCL/inheritance.cpp
index b5007d1885447..bd5f996c64796 100644
--- a/clang/test/CodeGenSYCL/inheritance.cpp
+++ b/clang/test/CodeGenSYCL/inheritance.cpp
@@ -40,7 +40,7 @@ int main() {
 }
 
 // Check kernel paramters
-// CHECK: define spir_kernel void @{{.*}}derived(%struct.{{.*}}.base* byval(%struct.{{.*}}.base) align 4 %_arg__base, %struct.{{.*}}.__wrapper_class* byval(%struct.{{.*}}.__wrapper_class) align 8 %_arg_e, i32 %_arg_a)
+// CHECK: define {{.*}}spir_kernel void @{{.*}}derived(%struct.{{.*}}.base* byval(%struct.{{.*}}.base) align 4 %_arg__base, %struct.{{.*}}.__wrapper_class* byval(%struct.{{.*}}.__wrapper_class) align 8 %_arg_e, i32 %_arg_a)
 
 // Check alloca for kernel paramters
 // CHECK: %[[ARG_A:[a-zA-Z0-9_.]+]] = alloca i32, align 4
diff --git a/clang/test/CodeGenSYCL/intel-fpga-ivdep-array.cpp b/clang/test/CodeGenSYCL/intel-fpga-ivdep-array.cpp
index 6ba97282ffecc..9615d3da4a8a0 100644
--- a/clang/test/CodeGenSYCL/intel-fpga-ivdep-array.cpp
+++ b/clang/test/CodeGenSYCL/intel-fpga-ivdep-array.cpp
@@ -2,7 +2,7 @@
 
 // Array-specific ivdep - annotate the correspondent GEPs only
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_array_no_safelenv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_array_no_safelenv()
 void ivdep_array_no_safelen() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -18,7 +18,7 @@ void ivdep_array_no_safelen() {
 }
 
 // Array-specific ivdep w/ safelen - annotate the correspondent GEPs only
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_array_with_safelenv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_array_with_safelenv()
 void ivdep_array_with_safelen() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -35,7 +35,7 @@ void ivdep_array_with_safelen() {
 
 // Multiple array-specific ivdeps - annotate the correspondent GEPs
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_multiple_arraysv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_multiple_arraysv()
 void ivdep_multiple_arrays() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -63,7 +63,7 @@ void ivdep_multiple_arrays() {
 
 // Global ivdep with INF safelen & array-specific ivdep with the same safelen
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_array_and_globalv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_array_and_globalv()
 void ivdep_array_and_global() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -81,7 +81,7 @@ void ivdep_array_and_global() {
 
 // Global ivdep with INF safelen & array-specific ivdep with lesser safelen
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_array_and_inf_globalv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_array_and_inf_globalv()
 void ivdep_array_and_inf_global() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -99,7 +99,7 @@ void ivdep_array_and_inf_global() {
 
 // Global ivdep with specified safelen & array-specific ivdep with lesser safelen
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_array_and_greater_globalv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_array_and_greater_globalv()
 void ivdep_array_and_greater_global() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -117,7 +117,7 @@ void ivdep_array_and_greater_global() {
 
 // Global safelen, array-specific safelens
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_mul_arrays_and_globalv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_mul_arrays_and_globalv()
 void ivdep_mul_arrays_and_global() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -138,7 +138,7 @@ void ivdep_mul_arrays_and_global() {
   }
 }
 
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_ptrv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_ptrv()
 void ivdep_ptr() {
   int *ptr;
   // CHECK: %[[PTR:[0-9a-z]+]] = alloca i32 addrspace(4)*
@@ -149,7 +149,7 @@ void ivdep_ptr() {
   // CHECK: br label %for.cond, !llvm.loop ![[MD_LOOP_PTR:[0-9]+]]
 }
 
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_structv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_structv()
 void ivdep_struct() {
   struct S {
     int *ptr;
diff --git a/clang/test/CodeGenSYCL/intel-fpga-ivdep-embedded-loops.cpp b/clang/test/CodeGenSYCL/intel-fpga-ivdep-embedded-loops.cpp
index 9ce1de58e7738..a1511f0c3886d 100644
--- a/clang/test/CodeGenSYCL/intel-fpga-ivdep-embedded-loops.cpp
+++ b/clang/test/CodeGenSYCL/intel-fpga-ivdep-embedded-loops.cpp
@@ -2,7 +2,7 @@
 
 // Accesses from the inner loop only, various global safelens for the outer and the inner loops.
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_inner_loop_accessv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_inner_loop_accessv()
 void ivdep_inner_loop_access() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -19,7 +19,7 @@ void ivdep_inner_loop_access() {
 
 // Accesses from both inner and outer loop, same global (INF) safelen for both.
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_embedded_global_safelenv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_embedded_global_safelenv()
 void ivdep_embedded_global_safelen() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -39,7 +39,7 @@ void ivdep_embedded_global_safelen() {
 
 // Accesses from both inner and outer loop, with various safelens per loop.
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_embedded_various_safelensv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_embedded_various_safelensv()
 void ivdep_embedded_various_safelens() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -61,7 +61,7 @@ void ivdep_embedded_various_safelens() {
 // Outer loop: array-specific ivdeps for all arrays with various safelens
 // Inner loop: global ivdep with its own safelen
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_embedded_multiple_arraysv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_embedded_multiple_arraysv()
 void ivdep_embedded_multiple_arrays() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -90,7 +90,7 @@ void ivdep_embedded_multiple_arrays() {
 // As the outer loop's ivdep applies to a particular, other array(s) shouldn't be marked
 // into any index group at the outer loop level
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_embedded_multiple_arrays_globalv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_embedded_multiple_arrays_globalv()
 void ivdep_embedded_multiple_arrays_global() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -114,7 +114,7 @@ void ivdep_embedded_multiple_arrays_global() {
 }
 
 // Accesses within each dimension of a multi-dimensional (n > 2) loop
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_embedded_multiple_dimensionsv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_embedded_multiple_dimensionsv()
 void ivdep_embedded_multiple_dimensions() {
   int a[10];
   [[intel::ivdep]] for (int i = 0; i != 10; ++i) {
diff --git a/clang/test/CodeGenSYCL/intel-fpga-ivdep-global.cpp b/clang/test/CodeGenSYCL/intel-fpga-ivdep-global.cpp
index 84fc0cd0c6372..3ce59a1383510 100644
--- a/clang/test/CodeGenSYCL/intel-fpga-ivdep-global.cpp
+++ b/clang/test/CodeGenSYCL/intel-fpga-ivdep-global.cpp
@@ -2,7 +2,7 @@
 
 // Global ivdep - annotate all GEPs
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_no_paramv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_no_paramv()
 void ivdep_no_param() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -20,7 +20,7 @@ void ivdep_no_param() {
 // Global ivdep - annotate all GEPs
 // Make sure that ALL of the relevant GEPs for an array are marked into the array's index groups
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_no_param_multiple_gepsv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_no_param_multiple_gepsv()
 void ivdep_no_param_multiple_geps() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -42,7 +42,7 @@ void ivdep_no_param_multiple_geps() {
 
 // Global ivdep w/ safelen specified - annotate all GEPs
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_safelenv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_safelenv()
 void ivdep_safelen() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
@@ -59,7 +59,7 @@ void ivdep_safelen() {
 
 // Global ivdep, albeit conflicting safelens - annotate all GEPs
 //
-// CHECK: define spir_func void @_Z{{[0-9]+}}ivdep_conflicting_safelenv()
+// CHECK: define {{.*}}spir_func void @_Z{{[0-9]+}}ivdep_conflicting_safelenv()
 void ivdep_conflicting_safelen() {
   // CHECK: %[[ARRAY_A:[0-9a-z]+]] = alloca [10 x i32]
   int a[10];
diff --git a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp
index abc75cf10dd85..797d3de3a1199 100644
--- a/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp
+++ b/clang/test/CodeGenSYCL/intel-fpga-mem-builtin.cpp
@@ -12,7 +12,7 @@ struct State {
 // CHECK: [[ANN1:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:0}
 // CHECK: [[ANN2:@.str[\.]*[0-9]*]] = {{.*}}{params:384}{cache-size:127}
 
-// CHECK: define spir_func void @{{.*}}(float addrspace(4)* %A, i32 addrspace(4)* %B, [[STRUCT]] addrspace(4)* %C, [[STRUCT]] addrspace(4)*{{.*}}%D)
+// CHECK: define {{.*}}spir_func void @{{.*}}(float addrspace(4)* %A, i32 addrspace(4)* %B, [[STRUCT]] addrspace(4)* %C, [[STRUCT]] addrspace(4)*{{.*}}%D)
 void foo(float *A, int *B, State *C, State &D) {
   float *x;
   int *y;
diff --git a/clang/test/CodeGenSYCL/intel-fpga-no-global-work-offset.cpp b/clang/test/CodeGenSYCL/intel-fpga-no-global-work-offset.cpp
index a2d33c2ac2932..a360337a26bfb 100644
--- a/clang/test/CodeGenSYCL/intel-fpga-no-global-work-offset.cpp
+++ b/clang/test/CodeGenSYCL/intel-fpga-no-global-work-offset.cpp
@@ -40,10 +40,10 @@ int main() {
   return 0;
 }
 
-// CHECK: define spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !no_global_work_offset ![[NUM5:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !no_global_work_offset ![[NUM5]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} ![[NUM4:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !no_global_work_offset ![[NUM5]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name5"() #0 {{.*}} !no_global_work_offset ![[NUM5]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !no_global_work_offset ![[NUM5:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !no_global_work_offset ![[NUM5]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} ![[NUM4:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !no_global_work_offset ![[NUM5]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name5"() #0 {{.*}} !no_global_work_offset ![[NUM5]]
 // CHECK-NOT: ![[NUM4]]  = !{i32 0}
 // CHECK: ![[NUM5]] = !{}
diff --git a/clang/test/CodeGenSYCL/intel-max-global-work-dim.cpp b/clang/test/CodeGenSYCL/intel-max-global-work-dim.cpp
index cde0613a8971b..35f0e4d19cf11 100644
--- a/clang/test/CodeGenSYCL/intel-max-global-work-dim.cpp
+++ b/clang/test/CodeGenSYCL/intel-max-global-work-dim.cpp
@@ -30,8 +30,8 @@ int main() {
   return 0;
 }
 
-// CHECK: define spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !max_global_work_dim ![[NUM1:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !max_global_work_dim ![[NUM2:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !max_global_work_dim ![[NUM2]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !max_global_work_dim ![[NUM1:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !max_global_work_dim ![[NUM2:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !max_global_work_dim ![[NUM2]]
 // CHECK: ![[NUM1]] = !{i32 1}
 // CHECK: ![[NUM2]] = !{i32 2}
diff --git a/clang/test/CodeGenSYCL/intel-max-work-group-size.cpp b/clang/test/CodeGenSYCL/intel-max-work-group-size.cpp
index 575177da51106..5700ddfd16c1d 100644
--- a/clang/test/CodeGenSYCL/intel-max-work-group-size.cpp
+++ b/clang/test/CodeGenSYCL/intel-max-work-group-size.cpp
@@ -45,11 +45,11 @@ int main() {
   return 0;
 }
 
-// CHECK: define spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !max_work_group_size ![[NUM1:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !max_work_group_size ![[NUM8:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !max_work_group_size ![[NUM6:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !max_work_group_size ![[NUM2:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name5"() #0 {{.*}} !max_work_group_size ![[NUM4:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !max_work_group_size ![[NUM1:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !max_work_group_size ![[NUM8:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !max_work_group_size ![[NUM6:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !max_work_group_size ![[NUM2:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name5"() #0 {{.*}} !max_work_group_size ![[NUM4:[0-9]+]]
 // CHECK: ![[NUM1]] = !{i32 1, i32 1, i32 1}
 // CHECK: ![[NUM8]] = !{i32 8, i32 8, i32 8}
 // CHECK: ![[NUM6]] = !{i32 6, i32 3, i32 1}
diff --git a/clang/test/CodeGenSYCL/intel-restrict.cpp b/clang/test/CodeGenSYCL/intel-restrict.cpp
index 12b870ba625f1..9e24c0e85903c 100644
--- a/clang/test/CodeGenSYCL/intel-restrict.cpp
+++ b/clang/test/CodeGenSYCL/intel-restrict.cpp
@@ -11,7 +11,7 @@ int main() {
   int *c;
   kernel<class kernel_restrict>(
       [ a, b, c ]() [[intel::kernel_args_restrict]] { c[0] = a[0] + b[0]; });
-  // CHECK: define spir_kernel {{.*}}kernel_restrict(i32 addrspace(1)* noalias %{{.*}}, i32 addrspace(1)* noalias %{{.*}}, i32 addrspace(1)* noalias %{{.*}})
+  // CHECK: define {{.*}}spir_kernel {{.*}}kernel_restrict(i32 addrspace(1)* noalias %{{.*}}, i32 addrspace(1)* noalias %{{.*}}, i32 addrspace(1)* noalias %{{.*}})
 
   int *d;
   int *e;
@@ -19,10 +19,10 @@ int main() {
 
   kernel<class kernel_norestrict>(
       [d, e, f]() { f[0] = d[0] + e[0]; });
-  // CHECK: define spir_kernel {{.*}}kernel_norestrict(i32 addrspace(1)* %{{.*}}, i32 addrspace(1)* %{{.*}}, i32 addrspace(1)* %{{.*}})
+  // CHECK: define {{.*}}spir_kernel {{.*}}kernel_norestrict(i32 addrspace(1)* %{{.*}}, i32 addrspace(1)* %{{.*}}, i32 addrspace(1)* %{{.*}})
 
   int g = 42;
   kernel<class kernel_restrict_other_types>(
       [ a, b, c, g ]() [[intel::kernel_args_restrict]] { c[0] = a[0] + b[0] + g; });
-  // CHECK: define spir_kernel {{.*}}kernel_restrict_other_types(i32 addrspace(1)* noalias %{{.*}}, i32 addrspace(1)* noalias %{{.*}}, i32 addrspace(1)* noalias %{{.*}}, i32 %{{.*}})
+  // CHECK: define {{.*}}spir_kernel {{.*}}kernel_restrict_other_types(i32 addrspace(1)* noalias %{{.*}}, i32 addrspace(1)* noalias %{{.*}}, i32 addrspace(1)* noalias %{{.*}}, i32 %{{.*}})
 }
diff --git a/clang/test/CodeGenSYCL/kernel-early-optimization-pipeline.cpp b/clang/test/CodeGenSYCL/kernel-early-optimization-pipeline.cpp
new file mode 100644
index 0000000000000..5dd2c49fa7387
--- /dev/null
+++ b/clang/test/CodeGenSYCL/kernel-early-optimization-pipeline.cpp
@@ -0,0 +1,10 @@
+// Check LLVM optimization pipeline is run by default for SPIR-V compiled for
+// SYCL device target, and can be disabled with -fno-sycl-early-optimizations.
+//
+// RUN: %clang_cc1 -O2 -fsycl -fsycl-is-device -triple spir64-unknown-unknown-sycldevice %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-EARLYOPT
+// CHECK-EARLYOPT: Lower Work Group Scope Code
+// CHECK-EARLYOPT: Combine redundant instructions
+//
+// RUN: %clang_cc1 -O2 -fsycl -fsycl-is-device -fno-sycl-early-optimizations -triple spir64-unknown-unknown-sycldevice %s -mllvm -debug-pass=Structure -emit-llvm -o - 2>&1 | FileCheck %s --check-prefix=CHECK-NOEARLYOPT
+// CHECK-NOEARLYOPT: Lower Work Group Scope Code
+// CHECK-NOEARLYOPT-NOT: Combine redundant instructions
diff --git a/clang/test/CodeGenSYCL/kernel-name.cpp b/clang/test/CodeGenSYCL/kernel-name.cpp
index 167203fd266a7..08c47be78ac01 100644
--- a/clang/test/CodeGenSYCL/kernel-name.cpp
+++ b/clang/test/CodeGenSYCL/kernel-name.cpp
@@ -13,7 +13,7 @@ __attribute__((sycl_kernel)) void kernel_single_task(const Func &kernelFunc) {
   kernelFunc();
 }
 
-// CHECK: define spir_kernel {{.*}}2cl4sycl6kernel
+// CHECK: define {{.*}}spir_kernel {{.*}}2cl4sycl6kernel
 int main() {
   kernel_single_task<class kernel>([]() {});
   return 0;
diff --git a/clang/test/CodeGenSYCL/kernel-param-acc-array.cpp b/clang/test/CodeGenSYCL/kernel-param-acc-array.cpp
index a4def6d3df400..2bd2b52945015 100644
--- a/clang/test/CodeGenSYCL/kernel-param-acc-array.cpp
+++ b/clang/test/CodeGenSYCL/kernel-param-acc-array.cpp
@@ -24,7 +24,7 @@ int main() {
 }
 
 // Check kernel_A parameters
-// CHECK: define spir_kernel void @{{.*}}kernel_A
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_A
 // CHECK-SAME: i32 addrspace(1)* [[MEM_ARG1:%[a-zA-Z0-9_]+]],
 // CHECK-SAME: %"struct.{{.*}}.cl::sycl::range"* byval{{.*}}align 4 [[ACC_RANGE1:%[a-zA-Z0-9_]+_1]],
 // CHECK-SAME: %"struct.{{.*}}.cl::sycl::range"* byval{{.*}}align 4 [[MEM_RANGE1:%[a-zA-Z0-9_]+_2]],
diff --git a/clang/test/CodeGenSYCL/kernel-param-member-acc-array.cpp b/clang/test/CodeGenSYCL/kernel-param-member-acc-array.cpp
index 45d4b658abf83..672e80f0edc38 100644
--- a/clang/test/CodeGenSYCL/kernel-param-member-acc-array.cpp
+++ b/clang/test/CodeGenSYCL/kernel-param-member-acc-array.cpp
@@ -27,7 +27,7 @@ int main() {
 }
 
 // CHECK kernel_C parameters
-// CHECK: define spir_kernel void @{{.*}}kernel_C
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_C
 // CHECK-SAME: i32 addrspace(1)* [[MEM_ARG1:%[a-zA-Z0-9_]+]],
 // CHECK-SAME: %"struct.{{.*}}.cl::sycl::range"* byval({{.*}}) align 4 [[ACC_RANGE1:%[a-zA-Z0-9_]+1]],
 // CHECK-SAME: %"struct.{{.*}}.cl::sycl::range"* byval({{.*}}) align 4 [[MEM_RANGE1:%[a-zA-Z0-9_]+2]],
diff --git a/clang/test/CodeGenSYCL/kernel-param-pod-array.cpp b/clang/test/CodeGenSYCL/kernel-param-pod-array.cpp
index c9f602261a8f7..4c7ffe0d3c591 100644
--- a/clang/test/CodeGenSYCL/kernel-param-pod-array.cpp
+++ b/clang/test/CodeGenSYCL/kernel-param-pod-array.cpp
@@ -45,7 +45,7 @@ int main() {
 }
 
 // Check kernel_B parameters
-// CHECK: define spir_kernel void @{{.*}}kernel_B
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_B
 // CHECK-SAME:(%struct.{{.*}}.__wrapper_class* byval(%struct.{{.*}}.__wrapper_class) align 4 %[[ARR_ARG:.*]])
 
 // Check local lambda object alloca
@@ -69,7 +69,7 @@ int main() {
 // CHECK: br i1 %[[ISDONE]], label %{{.*}}, label %[[ARRAYINITBODY]]
 
 // Check kernel_C parameters
-// CHECK: define spir_kernel void @{{.*}}kernel_C
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_C
 // CHECK-SAME:(%struct.{{.*}}.__wrapper_class{{.*}}* byval(%struct.{{.*}}.__wrapper_class{{.*}}) align 4 %[[ARR_ARG:.*]])
 
 // Check local lambda object alloca
@@ -94,7 +94,7 @@ int main() {
 // CHECK: br i1 %[[ISDONE]], label %{{.*}}, label %[[ARRAYINITBODY]]
 
 // Check kernel_D parameters
-// CHECK: define spir_kernel void @{{.*}}kernel_D
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_D
 // CHECK-SAME:(%struct.{{.*}}.__wrapper_class{{.*}}* byval(%struct.{{.*}}.__wrapper_class{{.*}}) align 4 %[[ARR_ARG:.*]])
 
 // Check local lambda object alloca
diff --git a/clang/test/CodeGenSYCL/local_var_big_init_as.cpp b/clang/test/CodeGenSYCL/local_var_big_init_as.cpp
new file mode 100644
index 0000000000000..81461549d6a26
--- /dev/null
+++ b/clang/test/CodeGenSYCL/local_var_big_init_as.cpp
@@ -0,0 +1,30 @@
+// RUN: %clang_cc1 -fsycl -fsycl-is-device -triple spir64-unknown-unknown-sycldevice \
+// RUN: -emit-llvm -o - %s | FileCheck %s
+
+// This test checks that data for big constant initializer lists is placed
+// into the global address space by the SYCL compiler.
+
+struct Test {
+  Test() : set{
+               0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+               0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} {};
+  int set[32];
+};
+// CHECK-DAG: @constinit = private unnamed_addr addrspace(1) constant
+// CHECK: [32 x i32]
+// CHECK: [i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
+// CHECK:  i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15,
+// CHECK:  i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
+// CHECK:  i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15
+// CHECK: ], align 4
+// CHECK-NOT: @constinit = private unnamed_addr addrspace(0)
+// CHECK-NOT: @constinit = private unnamed_addr addrspace(2)
+// CHECK-NOT: @constinit = private unnamed_addr addrspace(3)
+// CHECK-NOT: @constinit = private unnamed_addr addrspace(4)
+
+__attribute__((sycl_device)) void bar(Test &x);
+
+__attribute__((sycl_device)) void zoo() {
+  Test mc;
+  bar(mc);
+}
diff --git a/clang/test/CodeGenSYCL/loop_fuse_device.cpp b/clang/test/CodeGenSYCL/loop_fuse_device.cpp
index 2789f05223716..41e281673e1b9 100644
--- a/clang/test/CodeGenSYCL/loop_fuse_device.cpp
+++ b/clang/test/CodeGenSYCL/loop_fuse_device.cpp
@@ -37,15 +37,15 @@ void bar() {
   });
 }
 
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_1"() {{.*}} !loop_fuse ![[LF5:[0-9]+]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_2"() {{.*}} !loop_fuse ![[LF1:[0-9]+]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_3"() {{.*}} !loop_fuse ![[LF0:[0-9]+]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_4"() {{.*}} !loop_fuse ![[LF1]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_5"() {{.*}} !loop_fuse ![[LF10:[0-9]+]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_6"()
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_1"() {{.*}} !loop_fuse ![[LF5:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_2"() {{.*}} !loop_fuse ![[LF1:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_3"() {{.*}} !loop_fuse ![[LF0:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_4"() {{.*}} !loop_fuse ![[LF1]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_5"() {{.*}} !loop_fuse ![[LF10:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_6"()
 // CHECK-NOT: !loop_fuse
 // CHECK-SAME: {
-// CHECK: define spir_func void @{{.*}}foo{{.*}} !loop_fuse ![[LF5]]
+// CHECK: define {{.*}}spir_func void @{{.*}}foo{{.*}} !loop_fuse ![[LF5]]
 // CHECK: ![[LF5]] = !{i32 5, i32 0}
 // CHECK: ![[LF1]] = !{i32 1, i32 0}
 // CHECK: ![[LF0]] = !{i32 0, i32 0}
diff --git a/clang/test/CodeGenSYCL/loop_fuse_ind_device.cpp b/clang/test/CodeGenSYCL/loop_fuse_ind_device.cpp
index a415abf74cf44..cab9c90177bc4 100644
--- a/clang/test/CodeGenSYCL/loop_fuse_ind_device.cpp
+++ b/clang/test/CodeGenSYCL/loop_fuse_ind_device.cpp
@@ -37,15 +37,15 @@ void bar() {
   });
 }
 
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_1"() {{.*}} !loop_fuse ![[LFI5:[0-9]+]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_2"() {{.*}} !loop_fuse ![[LFI1:[0-9]+]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_3"() {{.*}} !loop_fuse ![[LFI0:[0-9]+]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_4"() {{.*}} !loop_fuse ![[LFI1]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_5"() {{.*}} !loop_fuse ![[LFI10:[0-9]+]]
-// CHECK: define spir_kernel void @"{{.*}}kernel_name_6"()
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_1"() {{.*}} !loop_fuse ![[LFI5:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_2"() {{.*}} !loop_fuse ![[LFI1:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_3"() {{.*}} !loop_fuse ![[LFI0:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_4"() {{.*}} !loop_fuse ![[LFI1]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_5"() {{.*}} !loop_fuse ![[LFI10:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}kernel_name_6"()
 // CHECK-NOT: !loop_fuse
 // CHECK-SAME: {
-// CHECK: define spir_func void @{{.*}}foo{{.*}} !loop_fuse ![[LFI5]]
+// CHECK: define {{.*}}spir_func void @{{.*}}foo{{.*}} !loop_fuse ![[LFI5]]
 // CHECK: ![[LFI5]] = !{i32 5, i32 1}
 // CHECK: ![[LFI1]] = !{i32 1, i32 1}
 // CHECK: ![[LFI0]] = !{i32 0, i32 1}
diff --git a/clang/test/CodeGenSYCL/module-id.cpp b/clang/test/CodeGenSYCL/module-id.cpp
index 08ad6178ddbf9..879d6acd0d86b 100644
--- a/clang/test/CodeGenSYCL/module-id.cpp
+++ b/clang/test/CodeGenSYCL/module-id.cpp
@@ -9,6 +9,6 @@ int main() {
   kernel_single_task<class kernel>([]() {});
   return 0;
 }
-// CHECK: define spir_kernel void @{{.*}}kernel{{.*}}() #[[KERN_ATTR:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel{{.*}}() #[[KERN_ATTR:[0-9]+]]
 
 // CHECK: #[[KERN_ATTR]] = { {{.*}}"sycl-module-id"="{{.*}}module-id.cpp"{{.*}} }
diff --git a/clang/test/CodeGenSYCL/num-simd-work-items.cpp b/clang/test/CodeGenSYCL/num-simd-work-items.cpp
index d83142c29eace..4620ead8b7896 100644
--- a/clang/test/CodeGenSYCL/num-simd-work-items.cpp
+++ b/clang/test/CodeGenSYCL/num-simd-work-items.cpp
@@ -30,9 +30,9 @@ int main() {
   return 0;
 }
 
-// CHECK: define spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !num_simd_work_items ![[NUM1:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !num_simd_work_items ![[NUM42:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !num_simd_work_items ![[NUM2:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !num_simd_work_items ![[NUM1:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !num_simd_work_items ![[NUM42:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !num_simd_work_items ![[NUM2:[0-9]+]]
 // CHECK: ![[NUM1]] = !{i32 1}
 // CHECK: ![[NUM42]] = !{i32 42}
 // CHECK: ![[NUM2]] = !{i32 2}
diff --git a/clang/test/CodeGenSYCL/parallel_for_this_item.cpp b/clang/test/CodeGenSYCL/parallel_for_this_item.cpp
index dc484b33bfbb4..7c9bee0c4a69d 100755
--- a/clang/test/CodeGenSYCL/parallel_for_this_item.cpp
+++ b/clang/test/CodeGenSYCL/parallel_for_this_item.cpp
@@ -14,7 +14,8 @@
 // CHECK-NEXT:   "_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE3EMU",
 // CHECK-NEXT:   "_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE3OWL",
 // CHECK-NEXT:   "_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE3RAT",
-// CHECK-NEXT:   "_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE3FOX"
+// CHECK-NEXT:   "_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE3FOX",
+// CHECK-NEXT:   "_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE3BEE"
 // CHECK-NEXT: };
 
 // CHECK:template <> struct KernelInfo<class GNU> {
@@ -97,6 +98,22 @@
 // CHECK-NEXT: __SYCL_DLL_LOCAL
 // CHECK-NEXT:    static constexpr bool callsAnyThisFreeFunction() { return 1; }
 // CHECK-NEXT:};
+// CHECK-NEXT:template <> struct KernelInfo<class BEE> {
+// CHECK-NEXT:  __SYCL_DLL_LOCAL
+// CHECK-NEXT:    static constexpr const char* getName() { return "_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE3BEE"; }
+// CHECK-NEXT:  __SYCL_DLL_LOCAL
+// CHECK-NEXT:    static constexpr unsigned getNumParams() { return 0; }
+// CHECK-NEXT:  __SYCL_DLL_LOCAL
+// CHECK-NEXT:    static constexpr const kernel_param_desc_t& getParamDesc(unsigned i) {
+// CHECK-NEXT:    return kernel_signatures[i+0];
+// CHECK-NEXT:  }
+// CHECK-NEXT:  __SYCL_DLL_LOCAL
+// CHECK-NEXT:    static constexpr bool isESIMD() { return 0; }
+// CHECK-NEXT:  __SYCL_DLL_LOCAL
+// CHECK-NEXT:    static constexpr bool callsThisItem() { return 1; }
+// CHECK-NEXT: __SYCL_DLL_LOCAL
+// CHECK-NEXT:    static constexpr bool callsAnyThisFreeFunction() { return 1; }
+// CHECK-NEXT:};
 
 #include "sycl.hpp"
 
@@ -135,8 +152,10 @@ int main() {
     cgh.parallel_for<class RAT>(range<1>(1), [=](id<1> I) { f(); });
 
     // This kernel does not call sycl::this_item, but does call this_id
-    cgh.parallel_for<class FOX>(range<1>(1),
-                                [=](id<1> I) { this_id<1>(); });
+    cgh.parallel_for<class FOX>(range<1>(1), [=](id<1> I) { this_id<1>(); });
+
+    // This kernel calls sycl::this_item
+    cgh.parallel_for<class BEE>(range<1>(1), [=](auto I) { this_item<1>(); });
   });
 
   return 0;
diff --git a/clang/test/CodeGenSYCL/pointers-in-structs.cpp b/clang/test/CodeGenSYCL/pointers-in-structs.cpp
index 74d642fb695bf..2f41ad9852cf3 100644
--- a/clang/test/CodeGenSYCL/pointers-in-structs.cpp
+++ b/clang/test/CodeGenSYCL/pointers-in-structs.cpp
@@ -39,10 +39,10 @@ int main() {
 // CHECK: %[[WRAPPER_F4_1:[a-zA-Z0-9_.]+]] = type { i32 addrspace(1)* }
 // CHECK: %[[WRAPPER_F4_2:[a-zA-Z0-9_.]+]] = type { i32 addrspace(1)* }
 // CHECK: %[[WRAPPER_LAMBDA_PTR:[a-zA-Z0-9_.]+]] = type { float addrspace(1)* }
-// CHECK: define spir_kernel void @{{.*}}structs
+// CHECK: define {{.*}}spir_kernel void @{{.*}}structs
 // CHECK-SAME: %[[WRAPPER_F1]]* byval(%[[WRAPPER_F1]]) align 8 %_arg_F1,
 // CHECK-SAME: %[[WRAPPER_F2]]* byval(%[[WRAPPER_F2]]) align 8 %_arg_F2,
 // CHECK-SAME: %[[WRAPPER_F]]* byval(%[[WRAPPER_F]]) align 8 %_arg_F,
 // CHECK-SAME: %[[WRAPPER_F4_1]]* byval(%[[WRAPPER_F4_1]]) align 8 %_arg_F4
 // CHECK-SAME: %[[WRAPPER_F4_2]]* byval(%[[WRAPPER_F4_2]]) align 8 %_arg_F41
-// CHECK: define spir_kernel void @{{.*}}lambdas{{.*}}(%[[WRAPPER_LAMBDA_PTR]]* byval(%[[WRAPPER_LAMBDA_PTR]]) align 8 %_arg_)
+// CHECK: define {{.*}}spir_kernel void @{{.*}}lambdas{{.*}}(%[[WRAPPER_LAMBDA_PTR]]* byval(%[[WRAPPER_LAMBDA_PTR]]) align 8 %_arg_)
diff --git a/clang/test/CodeGenSYCL/reqd-sub-group-size.cpp b/clang/test/CodeGenSYCL/reqd-sub-group-size.cpp
index 27bcfeef79ac2..2bd724421a84e 100644
--- a/clang/test/CodeGenSYCL/reqd-sub-group-size.cpp
+++ b/clang/test/CodeGenSYCL/reqd-sub-group-size.cpp
@@ -42,10 +42,10 @@ int main() {
   return 0;
 }
 
-// CHECK: define spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !intel_reqd_sub_group_size ![[SGSIZE16:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !intel_reqd_sub_group_size ![[SGSIZE8:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !intel_reqd_sub_group_size ![[SGSIZE4:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !intel_reqd_sub_group_size ![[SGSIZE2:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !intel_reqd_sub_group_size ![[SGSIZE16:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !intel_reqd_sub_group_size ![[SGSIZE8:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !intel_reqd_sub_group_size ![[SGSIZE4:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !intel_reqd_sub_group_size ![[SGSIZE2:[0-9]+]]
 // CHECK: ![[SGSIZE16]] = !{i32 16}
 // CHECK: ![[SGSIZE8]] = !{i32 8}
 // CHECK: ![[SGSIZE4]] = !{i32 4}
diff --git a/clang/test/CodeGenSYCL/reqd-work-group-size.cpp b/clang/test/CodeGenSYCL/reqd-work-group-size.cpp
index e0578750af603..230494ee72e51 100644
--- a/clang/test/CodeGenSYCL/reqd-work-group-size.cpp
+++ b/clang/test/CodeGenSYCL/reqd-work-group-size.cpp
@@ -52,12 +52,12 @@ int main() {
   return 0;
 }
 
-// CHECK: define spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE32:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE8:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE88:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE22:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name5"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE44:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name6"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE2:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE32:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE8:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE88:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE22:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name5"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE44:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name6"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE2:[0-9]+]]
 // CHECK: ![[WGSIZE32]] = !{i32 16, i32 16, i32 32}
 // CHECK: ![[WGSIZE8]] = !{i32 1, i32 1, i32 8}
 // CHECK: ![[WGSIZE88]] = !{i32 8, i32 8, i32 8}
diff --git a/clang/test/CodeGenSYCL/sampler.cpp b/clang/test/CodeGenSYCL/sampler.cpp
index eb0adba66bc09..a5aa3ed837c4e 100644
--- a/clang/test/CodeGenSYCL/sampler.cpp
+++ b/clang/test/CodeGenSYCL/sampler.cpp
@@ -1,5 +1,5 @@
 // RUN: %clang_cc1 -fsycl -fsycl-is-device -triple spir64-unknown-unknown-sycldevice -disable-llvm-passes -emit-llvm %s -o - | FileCheck --enable-var-scope %s
-// CHECK: define spir_kernel void @{{[a-zA-Z0-9_]+}}(%opencl.sampler_t addrspace(2)* [[SAMPLER_ARG:%[a-zA-Z0-9_]+]])
+// CHECK: define {{.*}}spir_kernel void @{{[a-zA-Z0-9_]+}}(%opencl.sampler_t addrspace(2)* [[SAMPLER_ARG:%[a-zA-Z0-9_]+]])
 // CHECK-NEXT: entry:
 // CHECK-NEXT: [[SAMPLER_ARG]].addr = alloca %opencl.sampler_t addrspace(2)*, align 8
 // CHECK-NEXT: [[ANON:%[0-9]+]] = alloca %"class.{{.*}}.anon", align 8
@@ -12,7 +12,7 @@
 // CHECK-NEXT: call spir_func void @{{[a-zA-Z0-9_]+}}(%"class.{{.*}}.cl::sycl::sampler" addrspace(4)* {{[^,]*}} [[GEPCAST]], %opencl.sampler_t addrspace(2)* [[LOAD_SAMPLER_ARG]])
 //
 
-// CHECK: define spir_kernel void @{{[a-zA-Z0-9_]+}}(%opencl.sampler_t addrspace(2)* [[SAMPLER_ARG_WRAPPED:%[a-zA-Z0-9_]+]], i32 [[ARG_A:%[a-zA-Z0-9_]+]])
+// CHECK: define {{.*}}spir_kernel void @{{[a-zA-Z0-9_]+}}(%opencl.sampler_t addrspace(2)* [[SAMPLER_ARG_WRAPPED:%[a-zA-Z0-9_]+]], i32 [[ARG_A:%[a-zA-Z0-9_]+]])
 
 // Check alloca
 // CHECK: [[SAMPLER_ARG_WRAPPED]].addr = alloca %opencl.sampler_t addrspace(2)*, align 8
diff --git a/clang/test/CodeGenSYCL/scheduler-target-fmax-mhz.cpp b/clang/test/CodeGenSYCL/scheduler-target-fmax-mhz.cpp
index b5412279a08d0..1fb7fd2513bd2 100644
--- a/clang/test/CodeGenSYCL/scheduler-target-fmax-mhz.cpp
+++ b/clang/test/CodeGenSYCL/scheduler-target-fmax-mhz.cpp
@@ -17,9 +17,9 @@ int main() {
   cl::sycl::kernel_single_task<class test_kernel3>(
       []() { zoo<75>(); });
 }
-// CHECK: define spir_kernel void @{{.*}}test_kernel1() {{.*}} !scheduler_target_fmax_mhz ![[PARAM1:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}test_kernel2() {{.*}} !scheduler_target_fmax_mhz ![[PARAM2:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}test_kernel3() {{.*}} !scheduler_target_fmax_mhz ![[PARAM3:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}test_kernel1() {{.*}} !scheduler_target_fmax_mhz ![[PARAM1:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}test_kernel2() {{.*}} !scheduler_target_fmax_mhz ![[PARAM2:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}test_kernel3() {{.*}} !scheduler_target_fmax_mhz ![[PARAM3:[0-9]+]]
 // CHECK: ![[PARAM1]] = !{i32 2}
 // CHECK: ![[PARAM2]] = !{i32 5}
 // CHECK: ![[PARAM3]] = !{i32 75}
diff --git a/clang/test/CodeGenSYCL/spir-calling-conv.cpp b/clang/test/CodeGenSYCL/spir-calling-conv.cpp
index 0da99dc7b167a..2544b4e22f007 100644
--- a/clang/test/CodeGenSYCL/spir-calling-conv.cpp
+++ b/clang/test/CodeGenSYCL/spir-calling-conv.cpp
@@ -7,7 +7,7 @@ __attribute__((sycl_kernel)) void kernel_single_task(const Func &kernelFunc) {
 
 int main() {
 
-  // CHECK: define spir_kernel void @_ZTSZ4mainE15kernel_function()
+  // CHECK: define {{.*}}spir_kernel void @_ZTSZ4mainE15kernel_function()
 
   // CHECK: call spir_func void @"_ZZ4mainENK3$_0clEv"(%"class.{{.*}}.anon" addrspace(4)* {{[^,]*}} %2)
 
diff --git a/clang/test/CodeGenSYCL/spir-enum.cpp b/clang/test/CodeGenSYCL/spir-enum.cpp
index 81102d213fefa..121270b57642f 100644
--- a/clang/test/CodeGenSYCL/spir-enum.cpp
+++ b/clang/test/CodeGenSYCL/spir-enum.cpp
@@ -20,7 +20,7 @@ void test(enum_type val)
 
 int main() {
 
-  // CHECK: define spir_kernel void @_ZTSZ4test9enum_typeE15kernel_function(i32 %_arg_)
+  // CHECK: define {{.*}}spir_kernel void @_ZTSZ4test9enum_typeE15kernel_function(i32 %_arg_)
 
   // CHECK: getelementptr inbounds %"class.{{.*}}.anon", %"class.{{.*}}.anon"*
   // CHECK: call spir_func void @"_ZZ4test9enum_typeENK3$_0clEv"(%"class.{{.*}}.anon" addrspace(4)* {{[^,]*}} %4)
diff --git a/clang/test/CodeGenSYCL/stall_enable.cpp b/clang/test/CodeGenSYCL/stall_enable.cpp
index f0e213cc2d219..31acb62f42273 100644
--- a/clang/test/CodeGenSYCL/stall_enable.cpp
+++ b/clang/test/CodeGenSYCL/stall_enable.cpp
@@ -21,6 +21,6 @@ int main() {
   return 0;
 }
 
-// CHECK: define spir_kernel void @"{{.*}}test_kernel1"() #0 {{.*}} !stall_enable ![[NUM5:[0-9]+]]
-// CHECK: define spir_kernel void @"{{.*}}test_kernel2"() #0 {{.*}} !stall_enable ![[NUM5]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}test_kernel1"() #0 {{.*}} !stall_enable ![[NUM5:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}test_kernel2"() #0 {{.*}} !stall_enable ![[NUM5]]
 // CHECK: ![[NUM5]] = !{i32 1}
diff --git a/clang/test/CodeGenSYCL/stream.cpp b/clang/test/CodeGenSYCL/stream.cpp
index 476d705054acc..5f2c048438991 100644
--- a/clang/test/CodeGenSYCL/stream.cpp
+++ b/clang/test/CodeGenSYCL/stream.cpp
@@ -1,7 +1,7 @@
 // RUN: %clang_cc1 -fsycl -fsycl-is-device -triple spir64-unknown-unknown-sycldevice -disable-llvm-passes -emit-llvm %s -o %t.ll
 // RUN: FileCheck < %t.ll --enable-var-scope %s
 //
-// CHECK: define spir_kernel void @"{{.*}}StreamTester"(%"{{.*}}cl::sycl::stream"* byval(%"{{.*}}cl::sycl::stream") {{.*}}){{.*}}
+// CHECK: define {{.*}}spir_kernel void @"{{.*}}StreamTester"(%"{{.*}}cl::sycl::stream"* byval(%"{{.*}}cl::sycl::stream") {{.*}}){{.*}}
 // CHECK: call spir_func void @{{.*}}__init{{.*}}(%{{.*}}cl::sycl::stream{{.*}} addrspace(4)* {{[^,]*}} %{{[0-9]+}})
 // CHECK: call spir_func void @{{.*}}__finalize{{.*}}(%{{.*}}cl::sycl::stream{{.*}} addrspace(4)* {{[^,]*}} %{{[0-9]+}})
 //
diff --git a/clang/test/CodeGenSYCL/sycl-device-alias.cpp b/clang/test/CodeGenSYCL/sycl-device-alias.cpp
index 3a124901b471d..9f8de327c390e 100644
--- a/clang/test/CodeGenSYCL/sycl-device-alias.cpp
+++ b/clang/test/CodeGenSYCL/sycl-device-alias.cpp
@@ -1,7 +1,7 @@
 // RUN: %clang_cc1 -fsycl -fsycl-is-device -triple spir64-unknown-unknown-sycldevice -disable-llvm-passes -emit-llvm %s -o - | FileCheck %s
 // Test that aliasing does not force an unused entity to be emitted
 
-// CHECK-NOT: define spir_func void @unused_func()
+// CHECK-NOT: define {{.*}}spir_func void @unused_func()
 extern "C" void unused_func() {}
 // CHECK-NOT: @unused_aliaser
 extern "C" void unused_aliaser() __attribute__((alias("unused_func")));
@@ -10,29 +10,29 @@ int unused_int = 3;
 // CHECK-NOT: @alias_unused_int
 extern int alias_unused_int __attribute__((alias("unused_int")));
 
-// CHECK-DAG: define spir_func void @used_func()
+// CHECK-DAG: define {{.*}}spir_func void @used_func()
 extern "C" void used_func() {}
-// CHECK-DAG: @aliaser = alias void (), void ()* @used_func
+// CHECK-DAG: @aliaser = {{.*}}alias void (), void ()* @used_func
 extern "C" void aliaser() __attribute__((alias("used_func")));
 
-// CHECK-DAG: define spir_func void @func()
+// CHECK-DAG: define {{.*}}spir_func void @func()
 extern "C" void func() {}
-// CHECK-DAG: @used_aliaser = alias void (), void ()* @func
+// CHECK-DAG: @used_aliaser = {{.*}}alias void (), void ()* @func
 extern "C" void used_aliaser() __attribute__((alias("func")));
 
-// CHECK-DAG: @used_int = addrspace(1) constant i32 5, align 4
+// CHECK-DAG: @used_int = {{.*}}addrspace(1) constant i32 5, align 4
 extern "C" const int used_int = 5;
-// CHECK-DAG: @alias_used_int = alias i32, i32 addrspace(1)* @used_int
+// CHECK-DAG: @alias_used_int = {{.*}}alias i32, i32 addrspace(1)* @used_int
 extern "C" const int alias_used_int __attribute__((alias("used_int")));
-// CHECK-DAG: @vint = addrspace(1) constant i32 7, align 4
+// CHECK-DAG: @vint = {{.*}}addrspace(1) constant i32 7, align 4
 extern "C" const int vint = 7;
-// CHECK-DAG: @used_alias_used_int = alias i32, i32 addrspace(1)* @vint
+// CHECK-DAG: @used_alias_used_int = {{.*}}alias i32, i32 addrspace(1)* @vint
 extern "C" const int used_alias_used_int __attribute__((alias("vint")));
 
-// CHECK-DAG: define spir_func void @{{.*}}bar{{.*}}
+// CHECK-DAG: define {{.*}}spir_func void @{{.*}}bar{{.*}}
 void bar(const int &i) {}
 
-// CHECK-DAG: define spir_func void @{{.*}}foo{{.*}}
+// CHECK-DAG: define {{.*}}spir_func void @{{.*}}foo{{.*}}
 void __attribute__((sycl_device)) foo() {
   // CHECK-DAG: call spir_func void @{{.*}}bar{{.*}}@used_int
   bar(used_int);
diff --git a/clang/test/CodeGenSYCL/sycl-device-static-init.cpp b/clang/test/CodeGenSYCL/sycl-device-static-init.cpp
index 95b220388d894..6b037d632cc56 100644
--- a/clang/test/CodeGenSYCL/sycl-device-static-init.cpp
+++ b/clang/test/CodeGenSYCL/sycl-device-static-init.cpp
@@ -6,7 +6,7 @@
 // CHECK: @_ZN8BaseInitI12TestBaseTypeE3varE = weak_odr addrspace(1) constant i32 9, comdat, align 4
 // CHECK-NOT: @_ZN8BaseInitI12TestBaseTypeE15s_regbase_ncsdmE = weak_odr addrspace(1) global %struct._ZTS16RegisterBaseInit.RegisterBaseInit zeroinitializer, comdat, align 1
 // CHECK-NOT: @_ZGVN8BaseInitI12TestBaseTypeE15s_regbase_ncsdmE = weak_odr global i64 0, comdat($_ZN8BaseInitI12TestBaseTypeE9s_regbaseE), align 8
-// CHECK: define spir_kernel void @_ZTSZ4mainE11fake_kernel()
+// CHECK: define {{.*}}spir_kernel void @_ZTSZ4mainE11fake_kernel()
 // CHECK: call spir_func void @"_ZZ4mainENK3$_0clEv
 
 struct TestBaseType {};
diff --git a/clang/test/CodeGenSYCL/sycl-device.cpp b/clang/test/CodeGenSYCL/sycl-device.cpp
index 49f8def476d98..12a363476185b 100644
--- a/clang/test/CodeGenSYCL/sycl-device.cpp
+++ b/clang/test/CodeGenSYCL/sycl-device.cpp
@@ -9,11 +9,11 @@ int bar20(int a) { return a + 20; }
 class A {
 public:
   // CHECK-DAG: define linkonce_odr spir_func void @_ZN1A3fooEv
-  // CHECK-DAG: define spir_func i32 @_Z5bar20i
+  // CHECK-DAG: define {{.*}}spir_func i32 @_Z5bar20i
   __attribute__((sycl_device)) void foo() { bar20(10); }
 
   // CHECK-DAG: define linkonce_odr spir_func void @_ZN1AC1Ev
-  // CHECK-DAG: define spir_func i32 @_Z5bar10i
+  // CHECK-DAG: define {{.*}}spir_func i32 @_Z5bar10i
   __attribute__((sycl_device))
   A() { bar10(10); }
   // CHECK-DAG: define linkonce_odr spir_func void @_ZN1AD1Ev
@@ -81,26 +81,26 @@ struct Finalizer1 : Base {
   void BaseWithAttr() final { int a = 20; }
 };
 
-// CHECK-DAG: define spir_func i32 @_Z3fooii
+// CHECK-DAG: define {{.*}}spir_func i32 @_Z3fooii
 __attribute__((sycl_device))
 int foo(int a, int b) { return a + bar(b); }
 
-// CHECK-DAG: define spir_func i32 @_Z3bari
+// CHECK-DAG: define {{.*}}spir_func i32 @_Z3bari
 int bar(int b) { return b; }
 
-// CHECK-DAG: define spir_func i32 @_Z3fari
+// CHECK-DAG: define {{.*}}spir_func i32 @_Z3fari
 int far(int b) { return b; }
 
-// CHECK-DAG: define spir_func i32 @_Z3booii
+// CHECK-DAG: define {{.*}}spir_func i32 @_Z3booii
 __attribute__((sycl_device))
 int boo(int a, int b) { return a + far(b); }
 
-// CHECK-DAG: define spir_func i32 @_Z3cari
+// CHECK-DAG: define {{.*}}spir_func i32 @_Z3cari
 __attribute__((sycl_device))
 int car(int b);
 int car(int b) { return b; }
 
-// CHECK-DAG: define spir_func i32 @_Z3cazi
+// CHECK-DAG: define {{.*}}spir_func i32 @_Z3cazi
 int caz(int b);
 __attribute__((sycl_device))
 int caz(int b) { return b; }
@@ -112,13 +112,13 @@ void taf(T t) {}
 // CHECK-DAG: define weak_odr spir_func void @_Z3tafIiEvT_
 template void taf<int>(int t);
 
-// CHECK-DAG: define spir_func void @_Z3tafIcEvT_
+// CHECK-DAG: define {{.*}}spir_func void @_Z3tafIcEvT_
 template<> void taf<char>(char t) {}
 
 template<typename T>
 void tar(T t) {}
 
-// CHECK-DAG: define spir_func void @_Z3tarIcEvT_
+// CHECK-DAG: define {{.*}}spir_func void @_Z3tarIcEvT_
 template<>
 __attribute__((sycl_device))
 void tar<char>(char t) {}
diff --git a/clang/test/CodeGenSYCL/sycl-multi-kernel-attr.cpp b/clang/test/CodeGenSYCL/sycl-multi-kernel-attr.cpp
index 7fb26c1a8c09d..6f712f38e188a 100644
--- a/clang/test/CodeGenSYCL/sycl-multi-kernel-attr.cpp
+++ b/clang/test/CodeGenSYCL/sycl-multi-kernel-attr.cpp
@@ -42,10 +42,10 @@ int main() {
   return 0;
 }
 
-// CHECK: define spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE:[0-9]+]] !intel_reqd_sub_group_size ![[SGSIZE:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE1:[0-9]+]] !intel_reqd_sub_group_size ![[SGSIZE1:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE2:[0-9]+]]
-// CHECK: define spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE3:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name1"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE:[0-9]+]] !intel_reqd_sub_group_size ![[SGSIZE:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name2"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE1:[0-9]+]] !intel_reqd_sub_group_size ![[SGSIZE1:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name3"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE2:[0-9]+]]
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_name4"() #0 {{.*}} !reqd_work_group_size ![[WGSIZE3:[0-9]+]]
 // CHECK: ![[WGSIZE]] = !{i32 16, i32 16, i32 32}
 // CHECK: ![[SGSIZE]] = !{i32 4}
 // CHECK: ![[WGSIZE1]] = !{i32 32, i32 32, i32 64}
diff --git a/clang/test/CodeGenSYCL/sycl_kernel-host.cpp b/clang/test/CodeGenSYCL/sycl_kernel-host.cpp
index 3414c9deaae8a..e18da6798db6a 100644
--- a/clang/test/CodeGenSYCL/sycl_kernel-host.cpp
+++ b/clang/test/CodeGenSYCL/sycl_kernel-host.cpp
@@ -4,7 +4,7 @@
 // function object passed to the sycl kernel is marked 'alwaysinline'
 // on the host.
 
-// CHECK: define spir_func void @{{.*}}func{{.*}}() #[[NOSKA:[0-9]+]] {
+// CHECK: define {{.*}}spir_func void @{{.*}}func{{.*}}() #[[NOSKA:[0-9]+]] {
 // CHECK: define internal spir_func void @{{.*}}Kernel{{.*}}Foo{{.*}}({{.*}}) #[[SKA:[0-9]+]] {
 // CHECK: call spir_func void @{{.*}}KernelImpl{{.*}}({{.*}}, i32 1, double 2.000000e+00)
 // CHECK: define internal spir_func void @{{.*}}Kernel{{.*}}Bar{{.*}}({{.*}}) #[[SKA]] {
diff --git a/clang/test/CodeGenSYCL/union-kernel-param.cpp b/clang/test/CodeGenSYCL/union-kernel-param.cpp
index 3cb438802a4f0..45e950b8e48d2 100644
--- a/clang/test/CodeGenSYCL/union-kernel-param.cpp
+++ b/clang/test/CodeGenSYCL/union-kernel-param.cpp
@@ -28,7 +28,7 @@ int main() {
 }
 
 // CHECK kernel_A parameters
-// CHECK: define spir_kernel void @{{.*}}kernel_A(%union.{{.*}}.MyUnion* byval(%union.{{.*}}.MyUnion) align 4 [[MEM_ARG:%[a-zA-Z0-9_]+]])
+// CHECK: define {{.*}}spir_kernel void @{{.*}}kernel_A(%union.{{.*}}.MyUnion* byval(%union.{{.*}}.MyUnion) align 4 [[MEM_ARG:%[a-zA-Z0-9_]+]])
 
 // Check lambda object alloca
 // CHECK: [[LOCAL_OBJECT:%0]] = alloca %"class.{{.*}}.anon", align 4
diff --git a/clang/test/Driver/amdgpu-toolchain.c b/clang/test/Driver/amdgpu-toolchain.c
index cb92744eee6a3..ac558e0e26eb3 100644
--- a/clang/test/Driver/amdgpu-toolchain.c
+++ b/clang/test/Driver/amdgpu-toolchain.c
@@ -8,7 +8,7 @@
 // AS_LINK: clang{{.*}} "-cc1as"
 // AS_LINK: ld.lld{{.*}} "-shared"
 
-// DWARF_VER: "-dwarf-version=5"
+// DWARF_VER: "-dwarf-version=4"
 
 // RUN: %clang -### -target amdgcn-amd-amdhsa -mcpu=gfx906 -nogpulib \
 // RUN:   -flto %s 2>&1 | FileCheck -check-prefix=LTO %s
diff --git a/clang/test/Driver/clang-offload-bundler.c b/clang/test/Driver/clang-offload-bundler.c
index 3f8766bf167f2..be77417a0950d 100644
--- a/clang/test/Driver/clang-offload-bundler.c
+++ b/clang/test/Driver/clang-offload-bundler.c
@@ -268,8 +268,8 @@
 
 // RUN: clang-offload-bundler -type=o -targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu -inputs=%t.o,%t.tgt1,%t.tgt2 -outputs=%t.bundle3.o -### 2>&1 \
 // RUN: | FileCheck %s -DHOST=%itanium_abi_triple -DINOBJ1=%t.o -DINOBJ2=%t.tgt1 -DINOBJ3=%t.tgt2 -DOUTOBJ=%t.bundle3.o --check-prefix CK-OBJ-CMD
-// CK-OBJ-CMD: llvm-objcopy{{(.exe)?}}" "--add-section=__CLANG_OFFLOAD_BUNDLE__host-[[HOST]]={{.*}}" "--add-section=__CLANG_OFFLOAD_BUNDLE_SIZE__host-[[HOST]]={{.+}}.tmp" "--add-section=__CLANG_OFFLOAD_BUNDLE__openmp-powerpc64le-ibm-linux-gnu=[[INOBJ2]]" "--add-section=__CLANG_OFFLOAD_BUNDLE_SIZE__openmp-powerpc64le-ibm-linux-gnu={{.+}}.tmp" "--add-section=__CLANG_OFFLOAD_BUNDLE__openmp-x86_64-pc-linux-gnu=[[INOBJ3]]" "--add-section=__CLANG_OFFLOAD_BUNDLE_SIZE__openmp-x86_64-pc-linux-gnu={{.+}}.tmp" "[[INOBJ1]]" "[[TEMPOBJ:.*]]"
-// CK-OBJ-CMD: llvm-objcopy{{(.exe)?}}" "--set-section-flags=__CLANG_OFFLOAD_BUNDLE__host-[[HOST]]=readonly,exclude" "--set-section-flags=__CLANG_OFFLOAD_BUNDLE_SIZE__host-[[HOST]]=readonly,exclude" "--set-section-flags=__CLANG_OFFLOAD_BUNDLE__openmp-powerpc64le-ibm-linux-gnu=readonly,exclude" "--set-section-flags=__CLANG_OFFLOAD_BUNDLE_SIZE__openmp-powerpc64le-ibm-linux-gnu=readonly,exclude" "--set-section-flags=__CLANG_OFFLOAD_BUNDLE__openmp-x86_64-pc-linux-gnu=readonly,exclude" "--set-section-flags=__CLANG_OFFLOAD_BUNDLE_SIZE__openmp-x86_64-pc-linux-gnu=readonly,exclude" "[[TEMPOBJ]]" "[[OUTOBJ]]"
+// CK-OBJ-CMD: llvm-objcopy{{(.exe)?}}" "--add-section=__CLANG_OFFLOAD_BUNDLE__host-[[HOST]]={{.*}}" "--add-section=__CLANG_OFFLOAD_BUNDLE__openmp-powerpc64le-ibm-linux-gnu=[[INOBJ2]]" "--add-section=__CLANG_OFFLOAD_BUNDLE__openmp-x86_64-pc-linux-gnu=[[INOBJ3]]" "[[INOBJ1]]" "[[TEMPOBJ:.*]]"
+// CK-OBJ-CMD: llvm-objcopy{{(.exe)?}}" "--set-section-flags=__CLANG_OFFLOAD_BUNDLE__host-[[HOST]]=readonly,exclude" "--set-section-flags=__CLANG_OFFLOAD_BUNDLE__openmp-powerpc64le-ibm-linux-gnu=readonly,exclude" "--set-section-flags=__CLANG_OFFLOAD_BUNDLE__openmp-x86_64-pc-linux-gnu=readonly,exclude" "[[TEMPOBJ]]" "[[OUTOBJ]]"
 
 // RUN: clang-offload-bundler -type=o -targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu -inputs=%t.o,%t.tgt1,%t.tgt2 -outputs=%t.bundle3.o
 // RUN: clang-offload-bundler -type=o -targets=host-%itanium_abi_triple,openmp-powerpc64le-ibm-linux-gnu,openmp-x86_64-pc-linux-gnu -outputs=%t.res.o,%t.res.tgt1,%t.res.tgt2 -inputs=%t.bundle3.o -unbundle
diff --git a/clang/test/Driver/clang-offload-bundler1.cpp b/clang/test/Driver/clang-offload-bundler1.cpp
deleted file mode 100755
index 0835e8bd82680..0000000000000
--- a/clang/test/Driver/clang-offload-bundler1.cpp
+++ /dev/null
@@ -1,69 +0,0 @@
-// REQUIRES: x86-registered-target
-// RUN: %clangxx -c %s -o %t_fat.o
-// RUN: %clangxx %t_fat.o -o %t.exe
-// RUN: clang-offload-bundler -type=oo -targets=host-x86_64-unknown-linux-gnu,sycl-x86_64-unknown-linux-gnu -outputs=%t.o,%t_list.txt -inputs=%t_fat.o -unbundle
-// RUN: %t.exe %t_list.txt | FileCheck %s
-// CHECK:11
-// CHECK:222
-// CHECK:3333
-
-#include <cstdint>
-#include <iostream>
-#include <fstream>
-#include <string>
-#include <vector>
-using namespace std;
-
-#define BUNDLE_SECTION_PREFIX "__CLANG_OFFLOAD_BUNDLE__"
-#define BUNDLE_SIZE_SECTION_PREFIX "__CLANG_OFFLOAD_BUNDLE_SIZE__"
-
-#define TARGET0 "host-x86_64-unknown-linux-gnu"
-#define TARGET1 "sycl-x86_64-unknown-linux-gnu"
-
-// Populate section with special names recognized by the bundler;
-// this emulates fat object partially linked from 3 other fat objects.
-// The test uses the bundler to split the bundle into 3 objects and then prints
-// their contents to stdout.
-char str0[] __attribute__((section(BUNDLE_SECTION_PREFIX TARGET0))) = { 0, 0, 0 };
-int64_t size0[] __attribute__((section(BUNDLE_SIZE_SECTION_PREFIX TARGET0))) = { 1, 1, 1 };
-
-char str1[] __attribute__((section(BUNDLE_SECTION_PREFIX TARGET1))) = { "11\n222\n3333\n" };
-int64_t size1[] __attribute__((section(BUNDLE_SIZE_SECTION_PREFIX TARGET1))) = { 3, 4, 5 };
-
-void cat(const string& File) {
-  string Line;
-  ifstream F(File);
-  if (F.is_open()) {
-    while (getline(F, Line)) {
-      cout << Line << '\n';
-    }
-    F.close();
-  }
-  else cout << "Unable to open file " << File;
-}
-
-// main is invoked with the bundler output file as argument -
-// read this file and print their contents to stdout.
-int main(int argc, char **argv) {
-  string ListFile(argv[1]);
-  string Line;
-  ifstream F(ListFile);
-  vector<string> OutFiles;
-
-  if (F.is_open()) {
-    while (getline(F, Line)) {
-      OutFiles.push_back(Line);
-    }
-    F.close();
-  }
-  else {
-    cout << "Unable to open file " << ListFile;
-    return 1;
-  }
-
-  for (const auto &File : OutFiles) {
-    cat(File);
-  }
-  return 0;
-}
-
diff --git a/clang/test/Driver/hip-toolchain-dwarf.hip b/clang/test/Driver/hip-toolchain-dwarf.hip
index c853d5cf07cf5..44d66fe52e047 100644
--- a/clang/test/Driver/hip-toolchain-dwarf.hip
+++ b/clang/test/Driver/hip-toolchain-dwarf.hip
@@ -6,4 +6,4 @@
 // RUN:   -x hip --cuda-gpu-arch=gfx803 %s \
 // RUN:   -Xarch_gfx803 -g 2>&1 | FileCheck %s -check-prefix=DWARF_VER
 
-// DWARF_VER: "-dwarf-version=5"
+// DWARF_VER: "-dwarf-version=4"
diff --git a/clang/test/Driver/ppc-features.cpp b/clang/test/Driver/ppc-features.cpp
index 91ec459ce1816..fceda63f5a231 100644
--- a/clang/test/Driver/ppc-features.cpp
+++ b/clang/test/Driver/ppc-features.cpp
@@ -1,6 +1,7 @@
 /// Check default CC1 and linker options for ppc32.
 // RUN: %clang -### -target powerpc-unknown-linux-gnu %s 2>&1 | FileCheck --check-prefix=PPC32 %s
-// PPC32: "-mfloat-abi" "hard"
+// PPC32:      "-munwind-tables"
+// PPC32-SAME: "-mfloat-abi" "hard"
 
 // PPC32: "-m" "elf32ppclinux"
 
@@ -38,11 +39,12 @@
 
 
 /// Check default CC1 and linker options for ppc64.
-// RUN: %clang -### -target powerpc64le-unknown-linux-gnu %s 2>&1 | FileCheck --check-prefix=PPC64 %s
-// RUN: %clang -### -target powerpc64-unknown-linux-gnu %s 2>&1 | FileCheck -check-prefix=PPC64BE %s
-// PPC64: "-mfloat-abi" "hard"
+// RUN: %clang -### -target powerpc64le-unknown-linux-gnu %s 2>&1 | FileCheck --check-prefixes=PPC64,PPC64LE %s
+// RUN: %clang -### -target powerpc64-unknown-linux-gnu %s 2>&1 | FileCheck --check-prefixes=PPC64,PPC64BE %s
+// PPC64:      "-munwind-tables"
+// PPC64-SAME: "-mfloat-abi" "hard"
 
-// PPC64: "-m" "elf64lppc"
+// PPC64LE: "-m" "elf64lppc"
 // PPC64BE: "-m" "elf64ppc"
 
 // check -msoft-float option for ppc64
diff --git a/clang/test/Format/error-config.cpp b/clang/test/Format/error-config.cpp
index 7fbc869f3a3cc..9f73a9eb9507e 100644
--- a/clang/test/Format/error-config.cpp
+++ b/clang/test/Format/error-config.cpp
@@ -1,10 +1,10 @@
 // RUN: clang-format %s --Wno-error=unknown --style="{UnknownKey: true}" 2>&1 | FileCheck %s -check-prefix=CHECK
 // RUN: not clang-format %s --style="{UnknownKey: true}" 2>&1 | FileCheck %s -check-prefix=CHECK-FAIL
 
-// CHECK: YAML:1:2: warning: unknown key 'UnknownKey'
+// CHECK: <command-line>:1:2: warning: unknown key 'UnknownKey'
 // CHECK-NEXT: {UnknownKey: true}
 // CHECK-NEXT: ^~~~~~~~~~
-// CHECK-FAIL: YAML:1:2: error: unknown key 'UnknownKey'
+// CHECK-FAIL: <command-line>:1:2: error: unknown key 'UnknownKey'
 // CHECK-FAIL-NEXT: {UnknownKey: true}
 // CHECK-FAIL-NEXT: ^~~~~~~~~~
 
diff --git a/clang/test/Frontend/plugin-attribute.cpp b/clang/test/Frontend/plugin-attribute.cpp
index 571ede3dc0b11..f02932d56c687 100644
--- a/clang/test/Frontend/plugin-attribute.cpp
+++ b/clang/test/Frontend/plugin-attribute.cpp
@@ -1,25 +1,22 @@
-// RUN: %clang -fplugin=%llvmshlibdir/Attribute%pluginext -emit-llvm -S %s -o - 2>&1 | FileCheck %s --check-prefix=ATTRIBUTE
-// RUN: not %clang -fplugin=%llvmshlibdir/Attribute%pluginext -emit-llvm -DBAD_ATTRIBUTE -S %s -o - 2>&1 | FileCheck %s --check-prefix=BADATTRIBUTE
+// RUN: split-file %s %t
+// RUN: %clang -cc1 -load %llvmshlibdir/Attribute%pluginext -fsyntax-only -ast-dump -verify %t/good_attr.cpp | FileCheck %s
+// RUN: %clang -fplugin=%llvmshlibdir/Attribute%pluginext -fsyntax-only -Xclang -verify %t/bad_attr.cpp
 // REQUIRES: plugins, examples
+//--- good_attr.cpp
+// expected-no-diagnostics
+void fn1a() __attribute__((example)) {}
+[[example]] void fn1b() {}
+[[plugin::example]] void fn1c() {}
+void fn2() __attribute__((example("somestring", 1, 2.0))) {}
+// CHECK-COUNT-4: -AnnotateAttr 0x{{[0-9a-z]+}} {{<col:[0-9]+(, col:[0-9]+)?>}} "example"
+// CHECK: -StringLiteral 0x{{[0-9a-z]+}} {{<col:[0-9]+(, col:[0-9]+)?>}} 'const char [{{[0-9]+}}]' lvalue "somestring"
+// CHECK: -IntegerLiteral 0x{{[0-9a-z]+}} {{<col:[0-9]+(, col:[0-9]+)?>}} 'int' 1
+// CHECK: -FloatingLiteral 0x{{[0-9a-z]+}} {{<col:[0-9]+(, col:[0-9]+)?>}} 'double' 2.000000e+00
 
-void fn1a() __attribute__((example)) { }
-[[example]] void fn1b() { }
-[[plugin::example]] void fn1c() { }
-void fn2() __attribute__((example("somestring"))) { }
-// ATTRIBUTE: warning: 'example' attribute only applies to functions
-int var1 __attribute__((example("otherstring"))) = 1;
-
-// ATTRIBUTE: [[STR1_VAR:@.+]] = private unnamed_addr constant [10 x i8] c"example()\00"
-// ATTRIBUTE: [[STR2_VAR:@.+]] = private unnamed_addr constant [20 x i8] c"example(somestring)\00"
-// ATTRIBUTE: @llvm.global.annotations = {{.*}}@{{.*}}fn1a{{.*}}[[STR1_VAR]]{{.*}}@{{.*}}fn1b{{.*}}[[STR1_VAR]]{{.*}}@{{.*}}fn1c{{.*}}[[STR1_VAR]]{{.*}}@{{.*}}fn2{{.*}}[[STR2_VAR]]
-
-#ifdef BAD_ATTRIBUTE
+//--- bad_attr.cpp
+int var1 __attribute__((example("otherstring"))) = 1; // expected-warning {{'example' attribute only applies to functions}}
 class Example {
-  // BADATTRIBUTE: error: 'example' attribute only allowed at file scope
-  void __attribute__((example)) fn3();
+  void __attribute__((example)) fn3(); // expected-error {{'example' attribute only allowed at file scope}}
 };
-// BADATTRIBUTE: error: 'example' attribute requires a string
-void fn4() __attribute__((example(123))) { }
-// BADATTRIBUTE: error: 'example' attribute takes no more than 1 argument
-void fn5() __attribute__((example("a","b"))) { }
-#endif
+void fn4() __attribute__((example(123))) { } // expected-error {{first argument to the 'example' attribute must be a string literal}}
+void fn5() __attribute__((example("a","b", 3, 4.0))) { } // expected-error {{'example' attribute only accepts at most three arguments}}
diff --git a/clang/test/Misc/dev-fd-fs.c b/clang/test/Misc/dev-fd-fs.c
index f04b059a64364..ea94d950b0716 100644
--- a/clang/test/Misc/dev-fd-fs.c
+++ b/clang/test/Misc/dev-fd-fs.c
@@ -8,7 +8,13 @@
 // RUN: cat %s | %clang -x c /dev/fd/0 -E > %t
 // RUN: FileCheck --check-prefix DEV-FD-INPUT < %t %s
 //
+// RUN: cat %s | %clang -x c %s -E -DINCLUDE_FROM_STDIN > %t
+// RUN: FileCheck --check-prefix DEV-FD-INPUT \
+// RUN:           --check-prefix DEV-FD-INPUT-INCLUDE < %t %s
+//
+// DEV-FD-INPUT-INCLUDE: int w;
 // DEV-FD-INPUT: int x;
+// DEV-FD-INPUT-INCLUDE: int y;
 
 
 // Check writing to /dev/fd named pipes. We use cat here as before to ensure we
@@ -27,4 +33,11 @@
 //
 // DEV-FD-REG-OUTPUT: int x;
 
+#ifdef INCLUDE_FROM_STDIN
+#undef INCLUDE_FROM_STDIN
+int w;
+#include "/dev/fd/0"
+int y;
+#else
 int x;
+#endif
diff --git a/clang/test/Misc/pragma-attribute-supported-attributes-list.test b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
index dc139c1f7f4b5..1f1ce032cb23e 100644
--- a/clang/test/Misc/pragma-attribute-supported-attributes-list.test
+++ b/clang/test/Misc/pragma-attribute-supported-attributes-list.test
@@ -67,6 +67,7 @@
 // CHECK-NEXT: IBAction (SubjectMatchRule_objc_method_is_instance)
 // CHECK-NEXT: IFunc (SubjectMatchRule_function)
 // CHECK-NEXT: InitPriority (SubjectMatchRule_variable)
+// CHECK-NEXT: IntelReqdSubGroupSize (SubjectMatchRule_function, SubjectMatchRule_function_is_member)
 // CHECK-NEXT: InternalLinkage (SubjectMatchRule_variable, SubjectMatchRule_function, SubjectMatchRule_record)
 // CHECK-NEXT: LTOVisibilityPublic (SubjectMatchRule_record)
 // CHECK-NEXT: Leaf (SubjectMatchRule_function)
@@ -145,7 +146,19 @@
 // CHECK-NEXT: ReturnTypestate (SubjectMatchRule_function, SubjectMatchRule_variable_is_parameter)
 // CHECK-NEXT: ReturnsNonNull (SubjectMatchRule_objc_method, SubjectMatchRule_function)
 // CHECK-NEXT: ReturnsTwice (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLDevice (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLDeviceIndirectlyCallable (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelKernelArgsRestrict (SubjectMatchRule_function)
 // CHECK-NEXT: SYCLIntelLoopFuse (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelMaxGlobalWorkDim (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelMaxWorkGroupSize (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelNoGlobalWorkOffset (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelNumSimdWorkItems (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelPipeIO (SubjectMatchRule_variable)
+// CHECK-NEXT: SYCLIntelSchedulerTargetFmaxMhz (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLIntelUseStallEnableClusters (SubjectMatchRule_function)
+// CHECK-NEXT: SYCLRegisterNum (SubjectMatchRule_variable_is_global)
+// CHECK-NEXT: SYCLSimd (SubjectMatchRule_function)
 // CHECK-NEXT: ScopedLockable (SubjectMatchRule_record)
 // CHECK-NEXT: Section (SubjectMatchRule_function, SubjectMatchRule_variable_is_global, SubjectMatchRule_objc_method, SubjectMatchRule_objc_property)
 // CHECK-NEXT: SetTypestate (SubjectMatchRule_function_is_member)
diff --git a/clang/test/OpenMP/distribute_dist_schedule_messages.cpp b/clang/test/OpenMP/distribute_dist_schedule_messages.cpp
index 0f7b2172f5a54..cd232f40feb43 100644
--- a/clang/test/OpenMP/distribute_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/distribute_dist_schedule_messages.cpp
@@ -35,7 +35,7 @@ T tmain(T argc) {
   for (int i = 0; i < 10; ++i) foo();
   #pragma omp distribute dist_schedule (static, S1) // expected-error {{'S1' does not refer to a value}}
   for (int i = 0; i < 10; ++i) foo();
-  #pragma omp distribute dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+  #pragma omp distribute dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
   return T();
 }
diff --git a/clang/test/OpenMP/distribute_parallel_for_dist_schedule_messages.cpp b/clang/test/OpenMP/distribute_parallel_for_dist_schedule_messages.cpp
index 18dcac555f740..07e7704dffded 100644
--- a/clang/test/OpenMP/distribute_parallel_for_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/distribute_parallel_for_dist_schedule_messages.cpp
@@ -54,7 +54,7 @@ T tmain(T argc) {
   for (int i = 0; i < 10; ++i) foo();
 #pragma omp target
 #pragma omp teams
-#pragma omp distribute parallel for dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp distribute parallel for dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
   return T();
 }
diff --git a/clang/test/OpenMP/distribute_parallel_for_simd_dist_schedule_messages.cpp b/clang/test/OpenMP/distribute_parallel_for_simd_dist_schedule_messages.cpp
index 63f8cfe917cd4..ed7b19111dee8 100644
--- a/clang/test/OpenMP/distribute_parallel_for_simd_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/distribute_parallel_for_simd_dist_schedule_messages.cpp
@@ -55,7 +55,7 @@ T tmain(T argc) {
   for (int i = 0; i < 10; ++i) foo();
 #pragma omp target
 #pragma omp teams
-#pragma omp distribute parallel for simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp distribute parallel for simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
   return T();
 }
diff --git a/clang/test/OpenMP/distribute_simd_dist_schedule_messages.cpp b/clang/test/OpenMP/distribute_simd_dist_schedule_messages.cpp
index a6593cfbe0d3d..794681c02646c 100644
--- a/clang/test/OpenMP/distribute_simd_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/distribute_simd_dist_schedule_messages.cpp
@@ -63,7 +63,7 @@ T tmain(T argc) {
   for (int i = 0; i < 10; ++i) foo();
 #pragma omp target
 #pragma omp teams
-#pragma omp distribute simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp distribute simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
   return T();
 }
diff --git a/clang/test/OpenMP/target_parallel_for_simd_collapse_messages.cpp b/clang/test/OpenMP/target_parallel_for_simd_collapse_messages.cpp
index f829874864daa..7acb2587f976f 100644
--- a/clang/test/OpenMP/target_parallel_for_simd_collapse_messages.cpp
+++ b/clang/test/OpenMP/target_parallel_for_simd_collapse_messages.cpp
@@ -46,7 +46,7 @@ T tmain(T argc, S **argv) {
   #pragma omp target parallel for simd collapse (S) // expected-error {{'S' does not refer to a value}}
   for (int i = ST; i < N; i++) argv[0][i] = argv[0][i] - argv[0][i-ST];
 
-  // expected-error@+1 1+{{integral constant expression}} expected-note@+1 0+{{constant expression}}
+  // expected-error@+1 {{integral constant expression}} expected-note@+1 0+{{constant expression}}
   #pragma omp target parallel for simd collapse (j=2) // expected-error {{expected ')'}} expected-note {{to match this '('}}
   for (int i = ST; i < N; i++) argv[0][i] = argv[0][i] - argv[0][i-ST];
   #pragma omp target parallel for simd collapse (1)
diff --git a/clang/test/OpenMP/target_parallel_for_simd_ordered_messages.cpp b/clang/test/OpenMP/target_parallel_for_simd_ordered_messages.cpp
index 972aa5753e363..8dd7f68c25fd8 100644
--- a/clang/test/OpenMP/target_parallel_for_simd_ordered_messages.cpp
+++ b/clang/test/OpenMP/target_parallel_for_simd_ordered_messages.cpp
@@ -56,7 +56,7 @@ T tmain(T argc, S **argv) {
   for (int i = ST; i < N; i++)
     argv[0][i] = argv[0][i] - argv[0][i - ST];
 
-// expected-error@+1 {{'ordered' clause with a parameter can not be specified in '#pragma omp target parallel for simd' directive}}
+// expected-error@+1 {{integral constant expression}} expected-note@+1 0+{{constant expression}}
 #pragma omp target parallel for simd ordered(j = 2) // expected-error {{expected ')'}} expected-note {{to match this '('}}
   for (int i = ST; i < N; i++)
     argv[0][i] = argv[0][i] - argv[0][i - ST];
diff --git a/clang/test/OpenMP/target_simd_collapse_messages.cpp b/clang/test/OpenMP/target_simd_collapse_messages.cpp
index d8b0a91f97d7b..00fa3c85279f2 100644
--- a/clang/test/OpenMP/target_simd_collapse_messages.cpp
+++ b/clang/test/OpenMP/target_simd_collapse_messages.cpp
@@ -44,7 +44,7 @@ T tmain(T argc, S **argv) {
   #pragma omp target simd collapse (S) // expected-error {{'S' does not refer to a value}}
   for (int i = ST; i < N; i++) argv[0][i] = argv[0][i] - argv[0][i-ST];
 
-  // expected-error@+1 1+{{integral constant expression}} expected-note@+1 0+{{constant expression}}
+  // expected-error@+1 {{integral constant expression}} expected-note@+1 0+{{constant expression}}
   #pragma omp target simd collapse (j=2) // expected-error {{expected ')'}} expected-note {{to match this '('}}
   for (int i = ST; i < N; i++) argv[0][i] = argv[0][i] - argv[0][i-ST];
   #pragma omp target simd collapse (1)
diff --git a/clang/test/OpenMP/target_teams_distribute_dist_schedule_messages.cpp b/clang/test/OpenMP/target_teams_distribute_dist_schedule_messages.cpp
index e31df97ba31c9..69c1e55eeaa3b 100644
--- a/clang/test/OpenMP/target_teams_distribute_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_dist_schedule_messages.cpp
@@ -45,7 +45,7 @@ T tmain(T argc) {
 #pragma omp target teams distribute dist_schedule (static, S1) // expected-error {{'S1' does not refer to a value}}
   for (int i = 0; i < 10; ++i) foo();
 
-#pragma omp target teams distribute dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp target teams distribute dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
 
   return T();
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_messages.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_messages.cpp
index 4f3c581254469..a0efad18668e9 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_messages.cpp
@@ -45,7 +45,7 @@ T tmain(T argc) {
 #pragma omp target teams distribute parallel for dist_schedule (static, S1) // expected-error {{'S1' does not refer to a value}}
   for (int i = 0; i < 10; ++i) foo();
 
-#pragma omp target teams distribute parallel for dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp target teams distribute parallel for dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
 
   return T();
diff --git a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_messages.cpp b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_messages.cpp
index 8b272d4358f60..ec634c8ac01c9 100644
--- a/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_messages.cpp
@@ -45,7 +45,7 @@ T tmain(T argc) {
 #pragma omp target teams distribute parallel for simd dist_schedule (static, S1) // expected-error {{'S1' does not refer to a value}}
   for (int i = 0; i < 10; ++i) foo();
 
-#pragma omp target teams distribute parallel for simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp target teams distribute parallel for simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
 
   return T();
diff --git a/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_messages.cpp b/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_messages.cpp
index b583c14831e70..507ddabd2fc20 100644
--- a/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_messages.cpp
@@ -45,7 +45,7 @@ T tmain(T argc) {
 #pragma omp target teams distribute simd dist_schedule (static, S1) // expected-error {{'S1' does not refer to a value}}
   for (int i = 0; i < 10; ++i) foo();
 
-#pragma omp target teams distribute simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp target teams distribute simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
 
   return T();
diff --git a/clang/test/OpenMP/target_update_from_messages.cpp b/clang/test/OpenMP/target_update_from_messages.cpp
index 42ecc2814e125..3dc377c4ca4ce 100644
--- a/clang/test/OpenMP/target_update_from_messages.cpp
+++ b/clang/test/OpenMP/target_update_from_messages.cpp
@@ -131,7 +131,7 @@ T tmain(T argc) {
 #pragma omp target update from(x, s7.s6[:5].aa[6]) // expected-error {{OpenMP array section is not allowed here}}
 #pragma omp target update from(x, s7.s6[:5].aa[:6]) // expected-error {{OpenMP array section is not allowed here}}
 #pragma omp target update from(s7.p[:10])
-#pragma omp target update from(x, s7.bfa) // expected-error 2{{bit fields cannot be used to specify storage in a 'from' clause}}
+#pragma omp target update from(x, s7.bfa) // expected-error {{bit fields cannot be used to specify storage in a 'from' clause}}
 #pragma omp target update from(x, s7.p[:]) // expected-error {{section length is unspecified and cannot be inferred because subscripted value is not an array}}
 #pragma omp target data map(to: s7.i)
   {
diff --git a/clang/test/OpenMP/target_update_to_messages.cpp b/clang/test/OpenMP/target_update_to_messages.cpp
index 941c781119e6e..fca4e21304fce 100644
--- a/clang/test/OpenMP/target_update_to_messages.cpp
+++ b/clang/test/OpenMP/target_update_to_messages.cpp
@@ -138,7 +138,7 @@ T tmain(T argc) {
 #pragma omp target update to(x, s7.s6[:5].aa[6]) // expected-error {{OpenMP array section is not allowed here}}
 #pragma omp target update to(x, s7.s6[:5].aa[:6]) // expected-error {{OpenMP array section is not allowed here}}
 #pragma omp target update to(s7.p[:10])
-#pragma omp target update to(x, s7.bfa) // expected-error 2{{bit fields cannot be used to specify storage in a 'to' clause}}
+#pragma omp target update to(x, s7.bfa) // expected-error {{bit fields cannot be used to specify storage in a 'to' clause}}
 #pragma omp target update to(x, s7.p[:]) // expected-error {{section length is unspecified and cannot be inferred because subscripted value is not an array}}
 #pragma omp target data map(to: s7.i)
   {
diff --git a/clang/test/OpenMP/task_messages.cpp b/clang/test/OpenMP/task_messages.cpp
index 2f9ee9a44402e..13cbfb6c45693 100644
--- a/clang/test/OpenMP/task_messages.cpp
+++ b/clang/test/OpenMP/task_messages.cpp
@@ -156,11 +156,11 @@ int foo() {
 #pragma omp task detach(a) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'int'}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'S'}}
   ;
 #pragma omp task detach(evt) detach(evt) // omp45-error 2 {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{directive '#pragma omp task' cannot contain more than one 'detach' clause}}
-#pragma omp task detach(cevt) detach(revt) // omp45-error 2 {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{directive '#pragma omp task' cannot contain more than one 'detach' clause}}
+#pragma omp task detach(cevt) detach(revt) // omp45-error 2 {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} expected-error {{directive '#pragma omp task' cannot contain more than one 'detach' clause}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'const omp_event_handle_t' (aka 'const unsigned long')}} omp50-error {{expected variable of the 'omp_event_handle_t' type, not 'omp_event_handle_t &' (aka 'unsigned long &')}}
 #pragma omp task detach(evt) mergeable // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{'mergeable' and 'detach' clause are mutually exclusive and may not appear on the same directive}} omp50-note {{'detach' clause is specified here}}
   ;
 #pragma omp task mergeable detach(evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{'detach' and 'mergeable' clause are mutually exclusive and may not appear on the same directive}} omp50-note {{'mergeable' clause is specified here}}
-#pragma omp task detach(-evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}}
+#pragma omp task detach(-evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}} omp50-error {{expected variable of the 'omp_event_handle_t' type}}
   ;
 #pragma omp task detach(evt) shared(evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}}
 #pragma omp task detach(evt) firstprivate(evt) // omp45-error {{unexpected OpenMP clause 'detach' in directive '#pragma omp task'}}
diff --git a/clang/test/OpenMP/teams_distribute_dist_schedule_messages.cpp b/clang/test/OpenMP/teams_distribute_dist_schedule_messages.cpp
index bd1aaa5c62896..22d2408d3f178 100644
--- a/clang/test/OpenMP/teams_distribute_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/teams_distribute_dist_schedule_messages.cpp
@@ -55,7 +55,7 @@ T tmain(T argc) {
   for (int i = 0; i < 10; ++i) foo();
 
 #pragma omp target
-#pragma omp teams distribute dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp teams distribute dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
 
   return T();
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_messages.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_messages.cpp
index a70d80ad1251e..27ff4125daf7f 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_messages.cpp
@@ -55,7 +55,7 @@ T tmain(T argc) {
   for (int i = 0; i < 10; ++i) foo();
 
 #pragma omp target
-#pragma omp teams distribute parallel for dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp teams distribute parallel for dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
 
   return T();
diff --git a/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_messages.cpp b/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_messages.cpp
index b87301fa98d8a..cbd4ec4ce9793 100644
--- a/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_messages.cpp
@@ -55,7 +55,7 @@ T tmain(T argc) {
   for (int i = 0; i < 10; ++i) foo();
 
 #pragma omp target
-#pragma omp teams distribute parallel for simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp teams distribute parallel for simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
 
   return T();
diff --git a/clang/test/OpenMP/teams_distribute_simd_dist_schedule_messages.cpp b/clang/test/OpenMP/teams_distribute_simd_dist_schedule_messages.cpp
index 6e653fae08c81..424797576837f 100644
--- a/clang/test/OpenMP/teams_distribute_simd_dist_schedule_messages.cpp
+++ b/clang/test/OpenMP/teams_distribute_simd_dist_schedule_messages.cpp
@@ -55,7 +55,7 @@ T tmain(T argc) {
   for (int i = 0; i < 10; ++i) foo();
 
 #pragma omp target
-#pragma omp teams distribute simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error 2{{expression must have integral or unscoped enumeration type, not 'char *'}}
+#pragma omp teams distribute simd dist_schedule (static, argv[1]=2) // expected-error {{expected ')'}} expected-note {{to match this '('}} expected-error3 {{expression must have integral or unscoped enumeration type, not 'char *'}}
   for (int i = 0; i < 10; ++i) foo();
 
   return T();
diff --git a/clang/test/Profile/c-generate.c b/clang/test/Profile/c-generate.c
index 70ab757e64715..1e7a739e04e4a 100644
--- a/clang/test/Profile/c-generate.c
+++ b/clang/test/Profile/c-generate.c
@@ -7,7 +7,7 @@
 //
 // PROF-INSTR-NONE-NOT: __llvm_prf
 //
-// PROF-INSTR-GARBAGE: invalid value 'garbage' in '-fprofile-instrument=garbage'
+// PROF-INSTR-GARBAGE: invalid PGO instrumentor in argument '-fprofile-instrument=garbage'
 
 int main(void) {
   return 0;
diff --git a/clang/test/Sema/invalid-bitwidth-expr.mm b/clang/test/Sema/invalid-bitwidth-expr.mm
index 8ce498feb4aff..41ca9496de4f9 100644
--- a/clang/test/Sema/invalid-bitwidth-expr.mm
+++ b/clang/test/Sema/invalid-bitwidth-expr.mm
@@ -26,7 +26,6 @@ auto func() {
 auto func() {
   // error-bit should be propagated from TemplateArgument to NestNameSpecifier.
   class Base<decltype(Foo(T()))>::type C; // expected-error {{no matching function for call to 'Foo'}}
-  // expected-error@-1 {{no class named 'type' in 'Base<bool>'}}
   return C;
 }
 struct Z {
diff --git a/clang/test/SemaCXX/invalid-template-base-specifier.cpp b/clang/test/SemaCXX/invalid-template-base-specifier.cpp
index 77601402a85ca..7a1a7f801c45e 100644
--- a/clang/test/SemaCXX/invalid-template-base-specifier.cpp
+++ b/clang/test/SemaCXX/invalid-template-base-specifier.cpp
@@ -12,11 +12,11 @@ void test() { Crash<int>(); } // expected-note {{in instantiation of template cl
 template <typename T>
 using Alias = decltype(Foo(T())); // expected-error {{no matching function for call to 'Foo'}}
 template <typename T>
-struct Crash2 : decltype(Alias<T>()) { // expected-note {{in instantiation of template type alias 'Alias' requested here}} expected-error {{base specifier must name a class}}
+struct Crash2 : decltype(Alias<T>()) { // expected-note {{in instantiation of template type alias 'Alias' requested here}}
   Crash2(){};
 };
 
-void test2() { Crash2<int>(); } // expected-note 2{{in instantiation of template class 'Crash2<int>' requested here}}
+void test2() { Crash2<int>(); } // expected-note {{in instantiation of template class 'Crash2<int>' requested here}}
 
 template <typename T>
 class Base {};
diff --git a/clang/test/SemaCXX/warn-unused-lambda-capture.cpp b/clang/test/SemaCXX/warn-unused-lambda-capture.cpp
index 764a4a42a0846..52ec390b0bba6 100644
--- a/clang/test/SemaCXX/warn-unused-lambda-capture.cpp
+++ b/clang/test/SemaCXX/warn-unused-lambda-capture.cpp
@@ -147,7 +147,7 @@ void test_templated() {
 
   auto explicit_by_value_unused = [i] {}; // expected-warning{{lambda capture 'i' is not used}}
   auto explicit_by_value_unused_sizeof = [i] { return sizeof(i); }; // expected-warning{{lambda capture 'i' is not required to be captured for this use}}
-  auto explicit_by_value_unused_decltype = [i] { decltype(i) j = 0; }; // expected-warning{{lambda capture 'i' is not required to be captured for this use}}
+  auto explicit_by_value_unused_decltype = [i] { decltype(i) j = 0; }; // expected-warning{{lambda capture 'i' is not used}}
   auto explicit_by_value_unused_const = [k] { return k + 1; };         // expected-warning{{lambda capture 'k' is not required to be captured for this use}}
   auto explicit_by_value_unused_const_generic = [k](auto c) { return k + 1; }; // expected-warning{{lambda capture 'k' is not required to be captured for this use}}
 
diff --git a/clang/test/SemaTemplate/dependent-expr.cpp b/clang/test/SemaTemplate/dependent-expr.cpp
index dace7e28788d2..abdb8e9c4a9fd 100644
--- a/clang/test/SemaTemplate/dependent-expr.cpp
+++ b/clang/test/SemaTemplate/dependent-expr.cpp
@@ -129,12 +129,7 @@ namespace PR45083 {
   template<typename> void f() {
     decltype(({})) x; // expected-error {{incomplete type}}
   }
-  template void f<int>();
-
-  template<typename T> void f2() {
-    decltype(({T();})) x; // expected-error {{incomplete type}}
-  }
-  template void f2<void>(); // expected-note {{instantiation of}}
+  template void f<int>(); // expected-note {{instantiation of}}
 
   template<typename> auto g() {
     auto c = [](auto, int) -> decltype(({})) {};
diff --git a/clang/test/SemaTemplate/instantiation-dependence.cpp b/clang/test/SemaTemplate/instantiation-dependence.cpp
deleted file mode 100644
index 75eb510cb68d6..0000000000000
--- a/clang/test/SemaTemplate/instantiation-dependence.cpp
+++ /dev/null
@@ -1,74 +0,0 @@
-// RUN: %clang_cc1 -std=c++2b -verify %s
-
-// Ensure we substitute into instantiation-dependent but non-dependent
-// constructs. The poster-child for this is...
-template<class ...> using void_t = void;
-
-namespace PR24076 {
-  template<class T> T declval();
-  struct s {};
-
-  template<class T,
-           class = void_t<decltype(declval<T>() + 1)>>
-    void foo(T) {} // expected-note {{invalid operands to binary expression}}
-
-  void f() {
-    foo(s{}); // expected-error {{no matching function}}
-  }
-
-  template<class T,
-           class = void_t<decltype(declval<T>() + 1)>> // expected-error {{invalid operands to binary expression}}
-  struct bar {};
-
-  bar<s> bar; // expected-note {{in instantiation of}}
-}
-
-namespace PR33655 {
-  struct One { using x = int; };
-  struct Two { using y = int; };
-
-  template<typename T, void_t<typename T::x> * = nullptr> int &func() {}
-  template<typename T, void_t<typename T::y> * = nullptr> float &func() {}
-
-  int &test1 = func<One>();
-  float &test2 = func<Two>();
-
-  template<class ...Args> struct indirect_void_t_imp { using type = void; };
-  template<class ...Args> using indirect_void_t = typename indirect_void_t_imp<Args...>::type;
-
-  template<class T> void foo() {
-    static_assert(!__is_void(indirect_void_t<T>)); // "ok", dependent
-    static_assert(!__is_void(void_t<T>)); // expected-error {{failed}}
-  }
-}
-
-namespace PR46791 { // also PR45782
-  template<typename T, typename = void>
-  struct trait {
-    static constexpr int specialization = 0;
-  };
-
-  // FIXME: Per a strict interpretation of the C++ rules, the two void_t<...>
-  // types below are equivalent -- we only (effectively) do token-by-token
-  // comparison for *expressions* appearing within types. But all other
-  // implementations accept this, using rules that are unclear.
-  template<typename T>
-  struct trait<T, void_t<typename T::value_type>> { // expected-note {{previous}} FIXME-note {{matches}}
-    static constexpr int specialization = 1;
-  };
-
-  template<typename T>
-  struct trait<T, void_t<typename T::element_type>> { // expected-error {{redefinition}} FIXME-note {{matches}}
-    static constexpr int specialization = 2;
-  };
-
-  struct A {};
-  struct B { typedef int value_type; };
-  struct C { typedef int element_type; };
-  struct D : B, C {};
-
-  static_assert(trait<A>::specialization == 0);
-  static_assert(trait<B>::specialization == 1); // FIXME expected-error {{failed}}
-  static_assert(trait<C>::specialization == 2); // FIXME expected-error {{failed}}
-  static_assert(trait<D>::specialization == 0); // FIXME-error {{ambiguous partial specialization}}
-}
diff --git a/clang/test/SemaTemplate/partial-spec-instantiate.cpp b/clang/test/SemaTemplate/partial-spec-instantiate.cpp
index 3b7cee88c42ec..2fc0517ae3d3c 100644
--- a/clang/test/SemaTemplate/partial-spec-instantiate.cpp
+++ b/clang/test/SemaTemplate/partial-spec-instantiate.cpp
@@ -51,6 +51,8 @@ namespace rdar9169404 {
   X<bool, -1>::type value;
 #if __cplusplus >= 201103L
   // expected-error@-2 {{non-type template argument evaluates to -1, which cannot be narrowed to type 'bool'}}
+#else
+  // expected-no-diagnostics
 #endif
 }
 
@@ -96,19 +98,3 @@ namespace rdar39524996 {
     takesWrapperInContainer(c);
   }
 }
-
-namespace InstantiationDependent {
-  template<typename> using ignore = void; // expected-warning 0-1{{extension}}
-  template<typename T, typename = void> struct A {
-    static const bool specialized = false;
-  };
-  template<typename T> struct Hide { typedef void type; };
-  template<typename T> struct A<T, Hide<ignore<typename T::type> >::type> {
-    static const bool specialized = true;
-  };
-
-  struct X {};
-  struct Y { typedef int type; };
-  _Static_assert(!A<X>::specialized, "");
-  _Static_assert(A<Y>::specialized, "");
-}
diff --git a/clang/test/SemaTemplate/temp_arg_nontype_cxx17.cpp b/clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp
similarity index 90%
rename from clang/test/SemaTemplate/temp_arg_nontype_cxx17.cpp
rename to clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp
index bc8a22e890415..675f957ef6fad 100644
--- a/clang/test/SemaTemplate/temp_arg_nontype_cxx17.cpp
+++ b/clang/test/SemaTemplate/temp_arg_nontype_cxx1z.cpp
@@ -2,7 +2,7 @@
 
 template<typename T, T val> struct A {};
 
-template<typename T, typename U> constexpr bool is_same = false;
+template<typename T, typename U> constexpr bool is_same = false; // expected-note +{{here}}
 template<typename T> constexpr bool is_same<T, T> = true;
 
 namespace String {
@@ -84,32 +84,34 @@ namespace PtrMem {
   constexpr int B::*b = &B::b;
   constexpr int C::*cb = b;
   constexpr int D::*db = b;
-  constexpr int E::*ecb = cb;
-  constexpr int E::*edb = db;
+  constexpr int E::*ecb = cb; // expected-note +{{here}}
+  constexpr int E::*edb = db; // expected-note +{{here}}
 
   constexpr int E::*e = &E::e;
   constexpr int D::*de = (int D::*)e;
   constexpr int C::*ce = (int C::*)e;
-  constexpr int B::*bde = (int B::*)de;
-  constexpr int B::*bce = (int B::*)ce;
+  constexpr int B::*bde = (int B::*)de; // expected-note +{{here}}
+  constexpr int B::*bce = (int B::*)ce; // expected-note +{{here}}
 
+  // FIXME: This should all be accepted, but we don't yet have a representation
+  // nor mangling for this form of template argument.
   using Ab = A<int B::*, b>;
   using Ab = A<int B::*, &B::b>;
-  using Abce = A<int B::*, bce>;
-  using Abde = A<int B::*, bde>;
-  static_assert(!is_same<Ab, Abce>, "");
-  static_assert(!is_same<Ab, Abde>, "");
-  static_assert(!is_same<Abce, Abde>, "");
-  static_assert(is_same<Abce, A<int B::*, (int B::*)(int C::*)&E::e>>, "");
+  using Abce = A<int B::*, bce>; // expected-error {{not supported}}
+  using Abde = A<int B::*, bde>; // expected-error {{not supported}}
+  static_assert(!is_same<Ab, Abce>, ""); // expected-error {{undeclared}} expected-error {{must be a type}}
+  static_assert(!is_same<Ab, Abde>, ""); // expected-error {{undeclared}} expected-error {{must be a type}}
+  static_assert(!is_same<Abce, Abde>, ""); // expected-error 2{{undeclared}} expected-error {{must be a type}}
+  static_assert(is_same<Abce, A<int B::*, (int B::*)(int C::*)&E::e>>, ""); // expected-error {{undeclared}} expected-error {{not supported}}
 
   using Ae = A<int E::*, e>;
   using Ae = A<int E::*, &E::e>;
-  using Aecb = A<int E::*, ecb>;
-  using Aedb = A<int E::*, edb>;
-  static_assert(!is_same<Ae, Aecb>, "");
-  static_assert(!is_same<Ae, Aedb>, "");
-  static_assert(!is_same<Aecb, Aedb>, "");
-  static_assert(is_same<Aecb, A<int E::*, (int E::*)(int C::*)&B::b>>, "");
+  using Aecb = A<int E::*, ecb>; // expected-error {{not supported}}
+  using Aedb = A<int E::*, edb>; // expected-error {{not supported}}
+  static_assert(!is_same<Ae, Aecb>, ""); // expected-error {{undeclared}} expected-error {{must be a type}}
+  static_assert(!is_same<Ae, Aedb>, ""); // expected-error {{undeclared}} expected-error {{must be a type}}
+  static_assert(!is_same<Aecb, Aedb>, ""); // expected-error 2{{undeclared}} expected-error {{must be a type}}
+  static_assert(is_same<Aecb, A<int E::*, (int E::*)(int C::*)&B::b>>, ""); // expected-error {{undeclared}} expected-error {{not supported}}
 
   using An = A<int E::*, nullptr>;
   using A0 = A<int E::*, (int E::*)0>;
@@ -203,9 +205,9 @@ namespace Auto {
 
     struct Y : X {};
     void type_affects_identity(B<&X::n>) {}
-    void type_affects_identity(B<(int Y::*)&X::n>) {}
+    void type_affects_identity(B<(int Y::*)&X::n>) {} // FIXME: expected-error {{sorry}}
     void type_affects_identity(B<(const int X::*)&X::n>) {}
-    void type_affects_identity(B<(const int Y::*)&X::n>) {}
+    void type_affects_identity(B<(const int Y::*)&X::n>) {} // FIXME: expected-error {{sorry}}
 
     // A case where we need to do auto-deduction, and check whether the
     // resulting dependent types match during partial ordering. These
@@ -501,13 +503,3 @@ namespace PR48517 {
   template<> struct Q<&R<int>::n> { static constexpr int X = 1; };
   static_assert(R<int>().f() == 1);
 }
-
-namespace dependent_reference {
-  template<int &r> struct S { int *q = &r; };
-  template<int> auto f() { static int n; return S<n>(); }
-  auto v = f<0>();
-  auto w = f<1>();
-  static_assert(!is_same<decltype(v), decltype(w)>);
-  // Ensure that we can instantiate the definition of S<...>.
-  int n = *v.q + *w.q;
-}
diff --git a/clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp b/clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
index 48101cccfce0a..c42fda7804305 100644
--- a/clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
+++ b/clang/test/SemaTemplate/temp_arg_nontype_cxx20.cpp
@@ -8,8 +8,8 @@ namespace std {
 
 // floating-point arguments
 template<float> struct Float {};
-using F1 = Float<1.0f>;
-using F1 = Float<2.0f / 2>;
+using F1 = Float<1.0f>; // FIXME expected-error {{sorry}}
+using F1 = Float<2.0f / 2>; // FIXME expected-error {{sorry}}
 
 struct S { int n[3]; } s; // expected-note 1+{{here}}
 union U { int a, b; } u;
@@ -17,24 +17,24 @@ int n; // expected-note 1+{{here}}
 
 // pointers to subobjects
 template<int *> struct IntPtr {};
-using IPn = IntPtr<&n + 1>;
-using IPn = IntPtr<&n + 1>;
+using IPn = IntPtr<&n + 1>; // FIXME expected-error {{refers to subobject}}
+using IPn = IntPtr<&n + 1>; // FIXME expected-error {{refers to subobject}}
 
-using IP2 = IntPtr<&s.n[2]>;
-using IP2 = IntPtr<s.n + 2>;
+using IP2 = IntPtr<&s.n[2]>; // FIXME expected-error {{refers to subobject}}
+using IP2 = IntPtr<s.n + 2>; // FIXME expected-error {{refers to subobject}}
 
-using IP3 = IntPtr<&s.n[3]>;
-using IP3 = IntPtr<s.n + 3>;
+using IP3 = IntPtr<&s.n[3]>; // FIXME expected-error {{refers to subobject}}
+using IP3 = IntPtr<s.n + 3>; // FIXME expected-error {{refers to subobject}}
 
 template<int &> struct IntRef {};
-using IRn = IntRef<*(&n + 1)>; // expected-error {{not a constant expression}} expected-note {{dereferenced pointer past the end of 'n'}}
-using IRn = IntRef<*(&n + 1)>; // expected-error {{not a constant expression}} expected-note {{dereferenced pointer past the end of 'n'}}
+using IPn = IntRef<*(&n + 1)>; // expected-error {{not a constant expression}} expected-note {{dereferenced pointer past the end of 'n'}}
+using IPn = IntRef<*(&n + 1)>; // expected-error {{not a constant expression}} expected-note {{dereferenced pointer past the end of 'n'}}
 
-using IR2 = IntRef<s.n[2]>;
-using IR2 = IntRef<*(s.n + 2)>;
+using IP2 = IntRef<s.n[2]>; // FIXME expected-error {{refers to subobject}}
+using IP2 = IntRef<*(s.n + 2)>; // FIXME expected-error {{refers to subobject}}
 
-using IR3 = IntRef<s.n[3]>; // expected-error {{not a constant expression}} expected-note {{dereferenced pointer past the end of subobject of 's'}}
-using IR3 = IntRef<*(s.n + 3)>; // expected-error {{not a constant expression}} expected-note {{dereferenced pointer past the end of subobject of 's'}}
+using IP3 = IntRef<s.n[3]>; // expected-error {{not a constant expression}} expected-note {{dereferenced pointer past the end of subobject of 's'}}
+using IP3 = IntRef<*(s.n + 3)>; // expected-error {{not a constant expression}} expected-note {{dereferenced pointer past the end of subobject of 's'}}
 
 // classes
 template<S> struct Struct {};
@@ -48,12 +48,12 @@ using U1 = Union<U{.b = 1}>; // expected-error {{different types}}
 
 // miscellaneous scalar types
 template<_Complex int> struct ComplexInt {};
-using CI = ComplexInt<1 + 3i>;
-using CI = ComplexInt<3i + 1>;
+using CI = ComplexInt<1 + 3i>; // FIXME: expected-error {{sorry}}
+using CI = ComplexInt<1 + 3i>; // FIXME: expected-error {{sorry}}
 
 template<_Complex float> struct ComplexFloat {};
-using CF = ComplexFloat<1.0f + 3.0fi>;
-using CF = ComplexFloat<3.0fi + 1.0f>;
+using CF = ComplexFloat<1.0f + 3.0fi>; // FIXME: expected-error {{sorry}}
+using CF = ComplexFloat<1.0f + 3.0fi>; // FIXME: expected-error {{sorry}}
 
 namespace ClassNTTP {
   struct A { // expected-note 2{{candidate}}
@@ -292,47 +292,3 @@ namespace Predefined {
     Y<B{__func__[0]}>(); // expected-error {{reference to subobject of predefined '__func__' variable}}
   }
 }
-
-namespace dependent {
-  template<auto &V> struct R { static inline auto &v = V; };
-  template<auto &V, auto &W> constexpr bool operator==(R<V>, R<W>) { return &V == &W; }
-  template<auto *V> struct S { static inline auto *v = V; };
-  template<auto *V, auto *W> constexpr bool operator==(S<V>, S<W>) { return V == W; }
-  template<auto V> struct T { static inline const auto &v = V; };
-  template<auto V, auto W> constexpr bool operator==(T<V>, T<W>) { return &V == &W; }
-  template<typename T> struct V { T v; };
-  template<int N> auto f() {
-    static int n;
-    static V<int> vn;
-    if constexpr (N < 10)
-      return R<n>();
-    else if constexpr (N < 20)
-      return R<vn.v>();
-    else if constexpr (N < 30)
-      return S<&n>();
-    else if constexpr (N < 40)
-      return S<&vn.v>();
-    else if constexpr (N < 50)
-      return T<V<int&>{n}>();
-    else if constexpr (N < 60)
-      return T<V<int*>{&n}>();
-    else if constexpr (N < 70)
-      return T<V<int&>{vn.v}>();
-    else if constexpr (N < 80)
-      return T<V<int*>{&vn.v}>();
-  }
-  template<int Base> void check() {
-    auto v = f<Base + 0>();
-    auto w = f<Base + 1>();
-    static_assert(!__is_same(decltype(v), decltype(w)));
-    static_assert(v != w);
-  }
-  template void check<0>();
-  template void check<10>();
-  template void check<20>();
-  template void check<30>();
-  template void check<40>();
-  template void check<50>();
-  template void check<60>();
-  template void check<70>();
-}
diff --git a/clang/test/SemaTemplate/temp_arg_template_cxx1z.cpp b/clang/test/SemaTemplate/temp_arg_template_cxx1z.cpp
index b9a1c933560d2..03ef78f8cf14e 100644
--- a/clang/test/SemaTemplate/temp_arg_template_cxx1z.cpp
+++ b/clang/test/SemaTemplate/temp_arg_template_cxx1z.cpp
@@ -115,12 +115,6 @@ namespace Auto {
 
   int n;
   template<auto A, decltype(A) B = &n> struct SubstFailure;
-  TInt<SubstFailure> isf; // expected-error {{template template argument has different template parameters than its corresponding template template parameter}}
+  TInt<SubstFailure> isf; // FIXME: this should be ill-formed
   TIntPtr<SubstFailure> ipsf;
-
-  template<template<auto A, auto B, decltype(A)> typename C> struct TAutoAutoFirst {};
-  template<auto A, auto B, decltype(A)> struct AutoAutoFirst;
-  template<auto A, auto B, decltype(B)> struct AutoAutoSecond;
-  TAutoAutoFirst<AutoAutoFirst> aaf;
-  TAutoAutoFirst<AutoAutoSecond> aas; // FIXME: this should be rejected due to parameter mismatch
 }
diff --git a/clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp b/clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
index eda31171f60e2..af4562e008dd5 100644
--- a/clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
+++ b/clang/tools/clang-offload-bundler/ClangOffloadBundler.cpp
@@ -20,7 +20,6 @@
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/StringRef.h"
-#include "llvm/ADT/StringSet.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Bitcode/BitcodeReader.h"
@@ -33,7 +32,6 @@
 #include "llvm/Object/ObjectFile.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
-#include "llvm/Support/Endian.h"
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/ErrorOr.h"
@@ -92,7 +90,6 @@ static cl::opt<std::string> FilesType(
              "  bc  - llvm-bc\n"
              "  s   - assembler\n"
              "  o   - object\n"
-             "  oo  - object; output file is a list of unbundled objects\n"
              "  gch - precompiled-header\n"
              "  ast - clang AST file\n"
              "  a   - archive of objects\n"
@@ -134,9 +131,6 @@ static cl::opt<unsigned>
 /// Magic string that marks the existence of offloading data.
 #define OFFLOAD_BUNDLER_MAGIC_STR "__CLANG_OFFLOAD_BUNDLE__"
 
-/// Prefix of an added section name with bundle size.
-#define SIZE_SECTION_PREFIX "__CLANG_OFFLOAD_BUNDLE_SIZE__"
-
 /// Section name which holds target symbol names.
 #define SYMBOLS_SECTION_NAME ".tgtsym"
 
@@ -478,88 +472,40 @@ class TempFileHandlerRAII {
 /// |
 /// | binary data for the <target 1>'s bundle
 /// |
-/// <SIZE_SECTION_PREFIX><target triple 1>
-/// | size of the <target1>'s bundle (8 bytes)
 /// ...
 /// <OFFLOAD_BUNDLER_MAGIC_STR><target triple N>
 /// |
 /// | binary data for the <target N>'s bundle
 /// |
-/// <SIZE_SECTION_PREFIX><target triple N>
-/// | size of the <target N>'s bundle (8 bytes)
 /// ...
 /// <OFFLOAD_BUNDLER_MAGIC_STR><host target>
 /// | 0 (1 byte long)
-/// <SIZE_SECTION_PREFIX><host target>
-/// | 1 (8 bytes)
-/// ...
-///
-/// Further, these fat objects can be "partially" linked by a platform linker:
-/// 1) ld -r a_fat.o b_fat.o c_fat.o -o abc_fat.o
-/// 2) ld -r a_fat.o -L. -lbc -o abc_fat.o
-///   where libbc.a is a static library created from b_fat.o and c_fat.o.
-/// This will still result in a fat object. But this object will have bundle and
-/// size sections for the same triple concatenated:
-/// ...
-/// <OFFLOAD_BUNDLER_MAGIC_STR><target triple 1>
-/// | binary data for the <target 1>'s bundle (from a_fat.o)
-/// | binary data for the <target 1>'s bundle (from b_fat.o)
-/// | binary data for the <target 1>'s bundle (from c_fat.o)
-/// <SIZE_SECTION_PREFIX><target triple 1>
-/// | size of the <target1>'s bundle (8 bytes) (from a_fat.o)
-/// | size of the <target1>'s bundle (8 bytes) (from b_fat.o)
-/// | size of the <target1>'s bundle (8 bytes) (from c_fat.o)
 /// ...
 ///
 /// The alignment of all the added sections is set to one to avoid padding
 /// between concatenated parts.
 ///
-/// The unbundler is able to unbundle both kinds of the fat objects. The first
-/// one can be handled either with -type=o or -type=oo option, the second one -
-/// with -type=oo option only. In the latter case unbundling may result in
-/// multiple files per target, and the output file in this case is a list of
-/// actual outputs.
-///
 class ObjectFileHandler final : public FileHandler {
-  /// Keeps infomation about a bundle for a particular target.
-  struct BundleInfo final {
-    /// The section that contains bundle data, can be a concatenation of a
-    /// number of individual bundles if produced via partial linkage of multiple
-    /// fat objects.
-    section_iterator BundleSection;
-    /// The sizes (in correct order) of the individual bundles constituting
-    /// bundle data.
-    SmallVector<uint64_t, 4> ObjectSizes;
-
-    BundleInfo(section_iterator S) : BundleSection(S) {}
-  };
+
   /// The object file we are currently dealing with.
   std::unique_ptr<ObjectFile> Obj;
 
-  /// Maps triple string to its bundle information
-  StringMap<std::unique_ptr<BundleInfo>> TripleToBundleInfo;
-  /// The two iterators below are to support the
-  /// ReadBundleStart/ReadBundle/ReadBundleEnd iteration mechanism
-  StringMap<std::unique_ptr<BundleInfo>>::iterator CurBundle;
-  StringMap<std::unique_ptr<BundleInfo>>::iterator NextBundle;
-
   /// Return the input file contents.
   StringRef getInputFileContents() const { return Obj->getData(); }
 
   /// Return bundle name (<kind>-<triple>) if the provided section is an offload
   /// section.
-  static Expected<Optional<StringRef>> IsOffloadSection(SectionRef CurSection,
-                                                        StringRef NamePrefix) {
+  static Expected<Optional<StringRef>> IsOffloadSection(SectionRef CurSection) {
     Expected<StringRef> NameOrErr = CurSection.getName();
     if (!NameOrErr)
       return NameOrErr.takeError();
 
-    // If it does not start with given prefix, just skip this section.
-    if (!NameOrErr->startswith(NamePrefix))
+    // If it does not start with the reserved suffix, just skip this section.
+    if (!NameOrErr->startswith(OFFLOAD_BUNDLER_MAGIC_STR))
       return None;
 
-    // Return the suffix.
-    return NameOrErr->substr(NamePrefix.size());
+    // Return the triple that is right after the reserved prefix.
+    return NameOrErr->substr(sizeof(OFFLOAD_BUNDLER_MAGIC_STR) - 1);
   }
 
   /// Total number of inputs.
@@ -569,8 +515,9 @@ class ObjectFileHandler final : public FileHandler {
   /// read from the buffers.
   unsigned NumberOfProcessedInputs = 0;
 
-  /// Input sizes.
-  SmallVector<uint64_t, 16u> InputSizes;
+  /// Iterator of the current and next section.
+  section_iterator CurrentSection;
+  section_iterator NextSection;
 
   // Return a buffer with symbol names that are defined in target objects.
   // Each symbol name is prefixed by a target name <kind>-<triple> to uniquely
@@ -659,155 +606,43 @@ class ObjectFileHandler final : public FileHandler {
 public:
   ObjectFileHandler(std::unique_ptr<ObjectFile> ObjIn)
       : FileHandler(), Obj(std::move(ObjIn)),
-        CurBundle(TripleToBundleInfo.end()),
-        NextBundle(TripleToBundleInfo.end()) {}
+        CurrentSection(Obj->section_begin()),
+        NextSection(Obj->section_begin()) {}
 
   ~ObjectFileHandler() final {}
 
-  // Iterate through sections and create a map from triple to relevant bundle
-  // information.
-  Error ReadHeader(MemoryBuffer &Input) final {
-    for (section_iterator Sec = Obj->section_begin(); Sec != Obj->section_end();
-         ++Sec) {
-      // Test if current section is an offload bundle section
-      Expected<Optional<StringRef>> BundleOrErr =
-          IsOffloadSection(*Sec, OFFLOAD_BUNDLER_MAGIC_STR);
-      if (!BundleOrErr)
-        return BundleOrErr.takeError();
-      if (*BundleOrErr) {
-        StringRef OffloadTriple = **BundleOrErr;
-        std::unique_ptr<BundleInfo> &BI = TripleToBundleInfo[OffloadTriple];
-        assert(!BI.get() || BI->BundleSection == Obj->section_end());
-
-        if (!BI.get()) {
-          BI.reset(new BundleInfo(Sec));
-        } else {
-          BI->BundleSection = Sec;
-        }
-        continue;
-      }
-      // Test if current section is an offload bundle size section
-      BundleOrErr = IsOffloadSection(*Sec, SIZE_SECTION_PREFIX);
-      if (!BundleOrErr)
-        return BundleOrErr.takeError();
-      if (*BundleOrErr) {
-        StringRef OffloadTriple = **BundleOrErr;
-
-        // yes, it is - parse object sizes
-        Expected<StringRef> Content = Sec->getContents();
-        if (!Content)
-          return Content.takeError();
-        unsigned int ElemSize = sizeof(uint64_t);
-
-        // the size of the size section must be a multiple of ElemSize
-        if (Content->size() % ElemSize != 0)
-          return createStringError(
-              errc::invalid_argument,
-              "invalid size of the bundle size section for triple " +
-                  OffloadTriple + ": " + Twine(Content->size()));
-        // read sizes
-        llvm::support::endianness E = Obj->isLittleEndian()
-                                          ? llvm::support::endianness::little
-                                          : llvm::support::endianness::big;
-        std::unique_ptr<BundleInfo> &BI = TripleToBundleInfo[OffloadTriple];
-        assert(!BI.get() || BI->ObjectSizes.size() == 0);
-
-        if (!BI.get()) {
-          BI.reset(new BundleInfo(Obj->section_end()));
-        }
-        for (const char *Ptr = Content->data();
-             Ptr < Content->data() + Content->size(); Ptr += ElemSize) {
-          uint64_t Size = support::endian::read64(Ptr, E);
-          BI->ObjectSizes.push_back(Size);
-        }
-      }
-    }
-    NextBundle = TripleToBundleInfo.begin();
-    return Error::success();
-  }
+  Error ReadHeader(MemoryBuffer &Input) final { return Error::success(); }
 
   Expected<Optional<StringRef>> ReadBundleStart(MemoryBuffer &Input) final {
-    if (NextBundle == TripleToBundleInfo.end())
-      return None;
-    CurBundle = NextBundle;
-    NextBundle++;
-    return CurBundle->getKey();
+    while (NextSection != Obj->section_end()) {
+      CurrentSection = NextSection;
+      ++NextSection;
+
+      // Check if the current section name starts with the reserved prefix. If
+      // so, return the triple.
+      Expected<Optional<StringRef>> TripleOrErr =
+          IsOffloadSection(*CurrentSection);
+      if (!TripleOrErr)
+        return TripleOrErr.takeError();
+      if (*TripleOrErr)
+        return **TripleOrErr;
+    }
+    return None;
   }
 
   Error ReadBundleEnd(MemoryBuffer &Input) final { return Error::success(); }
 
   Error ReadBundle(raw_ostream &OS, MemoryBuffer &Input) final {
-    assert(CurBundle != TripleToBundleInfo.end() &&
-           "all bundles have been read already");
-
-    // TODO: temporary workaround to copy fat object to the host output until
-    // driver is fixed to correctly handle list file for the host bundle in
-    // 'oo' mode.
-    if (FilesType == "oo" && hasHostKind(CurBundle->getKey())) {
-      OS.write(Input.getBufferStart(), Input.getBufferSize());
-      return Error::success();
-    }
-
-    // Read content of the section representing the bundle
-    Expected<StringRef> Content =
-        CurBundle->second->BundleSection->getContents();
-    if (!Content)
-      return Content.takeError();
-    const char *ObjData = Content->data();
-    // Determine the number of "device objects" (or individual bundles
-    // concatenated by partial linkage) in the bundle:
-    const auto &SizeVec = CurBundle->second->ObjectSizes;
-    auto NumObjects = SizeVec.size();
-    bool FileListMode = FilesType == "oo";
-
-    if (NumObjects > 1 && !FileListMode)
-      return createStringError(
-          errc::invalid_argument,
-          "'o' file type is requested, but the fat object contains multiple "
-          "device objects; use 'oo' instead");
+    Expected<StringRef> ContentOrErr = CurrentSection->getContents();
+    if (!ContentOrErr)
+      return ContentOrErr.takeError();
+    StringRef Content = *ContentOrErr;
 
-    // Iterate through individual objects and extract them
-    for (size_t I = 0; I < NumObjects; ++I) {
-      uint64_t ObjSize = SizeVec[I];
+    // Copy fat object contents to the output when extracting host bundle.
+    if (Content.size() == 1u && Content.front() == 0)
+      Content = StringRef(Input.getBufferStart(), Input.getBufferSize());
 
-      // Flag for the special case used to "unbundle" host target object.
-      if (ObjSize == 1) {
-        // Copy fat object contents to the output when extracting host bundle.
-
-        // In the partially linked fat object multiple dummy host bundles were
-        // concatenated - check all of them were of size 1
-        for (size_t II = I; II < NumObjects; ++II)
-          if (SizeVec[II] != 1)
-            return createStringError(inconvertibleErrorCode(),
-                                     "inconsistent host triple bundle");
-        OS.write(Input.getBufferStart(), Input.getBufferSize());
-        break;
-      }
-
-      if (FileListMode) {
-        SmallString<128> ObjFileName;
-        std::error_code EC =
-            sys::fs::createTemporaryFile(TempFileNameBase, "devo", ObjFileName);
-        if (EC)
-          return createFileError(ObjFileName, EC);
-
-        raw_fd_ostream ObjOS(ObjFileName, EC);
-        if (EC)
-          return createFileError(ObjFileName, EC);
-
-        ObjOS.write(ObjData, ObjSize);
-        if (ObjOS.has_error())
-          return createFileError(ObjFileName, ObjOS.error());
-
-        // add the written file name to the output list of files
-        OS << ObjFileName << "\n";
-      } else
-        OS.write(ObjData, ObjSize);
-
-      // Move "object data" pointer to the next object within the concatenated
-      // bundle.
-      ObjData += ObjSize;
-    }
+    OS.write(Content.data(), Content.size());
     return Error::success();
   }
 
@@ -817,11 +652,6 @@ class ObjectFileHandler final : public FileHandler {
 
     // Record number of inputs.
     NumberOfInputs = Inputs.size();
-
-    // And input sizes.
-    for (unsigned I = 0; I < NumberOfInputs; ++I)
-      InputSizes.push_back(I == HostInputIndex ? 1u
-                                               : Inputs[I]->getBufferSize());
     return Error::success();
   }
 
@@ -891,17 +721,6 @@ class ObjectFileHandler final : public FileHandler {
       ObjcopyArgs.push_back(SS.save(Twine("--add-section=") +
                                     OFFLOAD_BUNDLER_MAGIC_STR + TargetNames[I] +
                                     "=" + InputFile));
-
-      // Create temporary file with the section size contents.
-      Expected<StringRef> SizeFileOrErr = TempFiles.Create(makeArrayRef(
-          reinterpret_cast<char *>(&InputSizes[I]), sizeof(InputSizes[I])));
-      if (!SizeFileOrErr)
-        return SizeFileOrErr.takeError();
-
-      // And add one more section with target object size.
-      ObjcopyArgs.push_back(SS.save(Twine("--add-section=") +
-                                    SIZE_SECTION_PREFIX + TargetNames[I] + "=" +
-                                    *SizeFileOrErr));
     }
 
     // Add a section with symbol names that are defined in target objects to the
@@ -930,14 +749,10 @@ class ObjectFileHandler final : public FileHandler {
 
     // And run llvm-objcopy for the second time to update section flags.
     ObjcopyArgs.resize(1);
-    for (unsigned I = 0; I < NumberOfInputs; ++I) {
+    for (unsigned I = 0; I < NumberOfInputs; ++I)
       ObjcopyArgs.push_back(SS.save(Twine("--set-section-flags=") +
                                     OFFLOAD_BUNDLER_MAGIC_STR + TargetNames[I] +
                                     "=readonly,exclude"));
-      ObjcopyArgs.push_back(SS.save(Twine("--set-section-flags=") +
-                                    SIZE_SECTION_PREFIX + TargetNames[I] +
-                                    "=readonly,exclude"));
-    }
     ObjcopyArgs.push_back(IntermediateObj);
     ObjcopyArgs.push_back(OutputFileNames.front());
 
@@ -1347,7 +1162,7 @@ CreateFileHandler(MemoryBuffer &FirstInput) {
     return std::make_unique<BinaryFileHandler>();
   if (FilesType == "s")
     return std::make_unique<TextFileHandler>(/*Comment=*/"#");
-  if (FilesType == "o" || FilesType == "oo")
+  if (FilesType == "o")
     return CreateObjectFileHandler(FirstInput);
   if (FilesType == "gch")
     return std::make_unique<BinaryFileHandler>();
diff --git a/clang/tools/clang-offload-deps/ClangOffloadDeps.cpp b/clang/tools/clang-offload-deps/ClangOffloadDeps.cpp
index a5929938e7224..bf048cca739fe 100644
--- a/clang/tools/clang-offload-deps/ClangOffloadDeps.cpp
+++ b/clang/tools/clang-offload-deps/ClangOffloadDeps.cpp
@@ -73,7 +73,7 @@ static void reportError(Error E) {
 
 int main(int argc, const char **argv) {
   sys::PrintStackTraceOnErrorSignal(argv[0]);
-  ToolPath = sys::fs::getMainExecutable(argv[0], &ToolPath);
+  ToolPath = argv[0];
 
   cl::HideUnrelatedOptions(ClangOffloadDepsCategory);
   cl::SetVersionPrinter([](raw_ostream &OS) {
diff --git a/clang/tools/clang-offload-wrapper/ClangOffloadWrapper.cpp b/clang/tools/clang-offload-wrapper/ClangOffloadWrapper.cpp
index 8e2a1d91a132e..ad97dfc15256d 100644
--- a/clang/tools/clang-offload-wrapper/ClangOffloadWrapper.cpp
+++ b/clang/tools/clang-offload-wrapper/ClangOffloadWrapper.cpp
@@ -625,19 +625,6 @@ class BinaryWrapper {
   std::pair<Constant *, Constant *>
   addDeviceImageToModule(ArrayRef<char> Buf, const Twine &Name,
                          OffloadKind Kind, StringRef TargetTriple) {
-    // Do not bother adding 'size' section if target triple was not provided
-    // since we anyway won't be able to construct what bundler expects to see in
-    // the fat object.
-    if (!TargetTriple.empty()) {
-      // Create global data object for the image size.
-      size_t BufSize = Buf.size();
-      addGlobalArrayVariable(
-          Name + ".size",
-          makeArrayRef(reinterpret_cast<char *>(&BufSize), sizeof(BufSize)),
-          "__CLANG_OFFLOAD_BUNDLE_SIZE__" + offloadKindToString(Kind) + "-" +
-              TargetTriple);
-    }
-
     // Create global variable for the image data.
     return addArrayToModule(Buf, Name,
                             TargetTriple.empty()
diff --git a/clang/tools/libclang/CIndex.cpp b/clang/tools/libclang/CIndex.cpp
index 969df52667978..52cef274e6c85 100644
--- a/clang/tools/libclang/CIndex.cpp
+++ b/clang/tools/libclang/CIndex.cpp
@@ -1493,11 +1493,6 @@ bool CursorVisitor::VisitTemplateArgumentLoc(const TemplateArgumentLoc &TAL) {
       return Visit(MakeCXCursor(E, StmtParent, TU, RegionOfInterest));
     return false;
 
-  case TemplateArgument::UncommonValue:
-    if (Expr *E = TAL.getSourceUncommonValueExpression())
-      return Visit(MakeCXCursor(E, StmtParent, TU, RegionOfInterest));
-    return false;
-
   case TemplateArgument::NullPtr:
     if (Expr *E = TAL.getSourceNullPtrExpression())
       return Visit(MakeCXCursor(E, StmtParent, TU, RegionOfInterest));
diff --git a/clang/tools/libclang/CXCursor.cpp b/clang/tools/libclang/CXCursor.cpp
index 851b418b6d7be..180cf1858d04c 100644
--- a/clang/tools/libclang/CXCursor.cpp
+++ b/clang/tools/libclang/CXCursor.cpp
@@ -1375,9 +1375,6 @@ enum CXTemplateArgumentKind clang_Cursor_getTemplateArgumentKind(CXCursor C,
     return CXTemplateArgumentKind_NullPtr;
   case TemplateArgument::Integral:
     return CXTemplateArgumentKind_Integral;
-  case TemplateArgument::UncommonValue:
-    // FIXME: Expose these values.
-    return CXTemplateArgumentKind_Invalid;
   case TemplateArgument::Template:
     return CXTemplateArgumentKind_Template;
   case TemplateArgument::TemplateExpansion:
diff --git a/clang/tools/scan-view/CMakeLists.txt b/clang/tools/scan-view/CMakeLists.txt
index 22edb974bac7e..dd3d33439299a 100644
--- a/clang/tools/scan-view/CMakeLists.txt
+++ b/clang/tools/scan-view/CMakeLists.txt
@@ -5,10 +5,7 @@ set(BinFiles
 
 set(ShareFiles
       ScanView.py
-      Reporter.py
       startfile.py
-      FileRadar.scpt
-      GetRadarVersion.scpt
       bugcatcher.ico)
 
 if(CLANG_INSTALL_SCANVIEW)
diff --git a/clang/tools/scan-view/share/FileRadar.scpt b/clang/tools/scan-view/share/FileRadar.scpt
deleted file mode 100644
index 1c7455285ccb0..0000000000000
Binary files a/clang/tools/scan-view/share/FileRadar.scpt and /dev/null differ
diff --git a/clang/tools/scan-view/share/GetRadarVersion.scpt b/clang/tools/scan-view/share/GetRadarVersion.scpt
deleted file mode 100644
index e69de29bb2d1d..0000000000000
diff --git a/clang/tools/scan-view/share/Reporter.py b/clang/tools/scan-view/share/Reporter.py
deleted file mode 100644
index b1ff16142e279..0000000000000
--- a/clang/tools/scan-view/share/Reporter.py
+++ /dev/null
@@ -1,251 +0,0 @@
-#!/usr/bin/env python
-# -*- coding: utf-8 -*-
-
-"""Methods for reporting bugs."""
-
-import subprocess, sys, os
-
-__all__ = ['ReportFailure', 'BugReport', 'getReporters']
-
-#
-
-class ReportFailure(Exception):
-    """Generic exception for failures in bug reporting."""
-    def __init__(self, value):        
-        self.value = value
-
-# Collect information about a bug.
-
-class BugReport(object):
-    def __init__(self, title, description, files):
-        self.title = title
-        self.description = description
-        self.files = files
-
-# Reporter interfaces.
-
-import os
-
-import email, mimetypes, smtplib
-from email import encoders
-from email.message import Message
-from email.mime.base import MIMEBase
-from email.mime.multipart import MIMEMultipart
-from email.mime.text import MIMEText
-
-#===------------------------------------------------------------------------===#
-# ReporterParameter
-#===------------------------------------------------------------------------===#
-
-class ReporterParameter(object):
-  def __init__(self, n):
-    self.name = n
-  def getName(self):
-    return self.name
-  def getValue(self,r,bugtype,getConfigOption):
-     return getConfigOption(r.getName(),self.getName())
-  def saveConfigValue(self):
-    return True
-
-class TextParameter (ReporterParameter):
-  def getHTML(self,r,bugtype,getConfigOption):
-    return """\
-<tr>
-<td class="form_clabel">%s:</td>
-<td class="form_value"><input type="text" name="%s_%s" value="%s"></td>
-</tr>"""%(self.getName(),r.getName(),self.getName(),self.getValue(r,bugtype,getConfigOption))
-
-class SelectionParameter (ReporterParameter):
-  def __init__(self, n, values):
-    ReporterParameter.__init__(self,n)
-    self.values = values
-    
-  def getHTML(self,r,bugtype,getConfigOption):
-    default = self.getValue(r,bugtype,getConfigOption)
-    return """\
-<tr>
-<td class="form_clabel">%s:</td><td class="form_value"><select name="%s_%s">
-%s
-</select></td>"""%(self.getName(),r.getName(),self.getName(),'\n'.join(["""\
-<option value="%s"%s>%s</option>"""%(o[0],
-                                     o[0] == default and ' selected="selected"' or '',
-                                     o[1]) for o in self.values]))
-
-#===------------------------------------------------------------------------===#
-# Reporters
-#===------------------------------------------------------------------------===#
-
-class EmailReporter(object):
-    def getName(self):
-        return 'Email'
-
-    def getParameters(self):
-        return [TextParameter(x) for x in ['To', 'From', 'SMTP Server', 'SMTP Port']]
-
-    # Lifted from python email module examples.
-    def attachFile(self, outer, path):
-        # Guess the content type based on the file's extension.  Encoding
-        # will be ignored, although we should check for simple things like
-        # gzip'd or compressed files.
-        ctype, encoding = mimetypes.guess_type(path)
-        if ctype is None or encoding is not None:
-            # No guess could be made, or the file is encoded (compressed), so
-            # use a generic bag-of-bits type.
-            ctype = 'application/octet-stream'
-        maintype, subtype = ctype.split('/', 1)
-        if maintype == 'text':
-            fp = open(path)
-            # Note: we should handle calculating the charset
-            msg = MIMEText(fp.read(), _subtype=subtype)
-            fp.close()
-        else:
-            fp = open(path, 'rb')
-            msg = MIMEBase(maintype, subtype)
-            msg.set_payload(fp.read())
-            fp.close()
-            # Encode the payload using Base64
-            encoders.encode_base64(msg)
-        # Set the filename parameter
-        msg.add_header('Content-Disposition', 'attachment', filename=os.path.basename(path))
-        outer.attach(msg)
-
-    def fileReport(self, report, parameters):
-        mainMsg = """\
-BUG REPORT
----
-Title: %s
-Description: %s
-"""%(report.title, report.description)
-
-        if not parameters.get('To'):
-            raise ReportFailure('No "To" address specified.')
-        if not parameters.get('From'):
-            raise ReportFailure('No "From" address specified.')
-
-        msg = MIMEMultipart()
-        msg['Subject'] = 'BUG REPORT: %s'%(report.title)
-        # FIXME: Get config parameters
-        msg['To'] = parameters.get('To')
-        msg['From'] = parameters.get('From')
-        msg.preamble = mainMsg
-
-        msg.attach(MIMEText(mainMsg, _subtype='text/plain'))
-        for file in report.files:
-            self.attachFile(msg, file)
-
-        try:
-            s = smtplib.SMTP(host=parameters.get('SMTP Server'),
-                             port=parameters.get('SMTP Port'))
-            s.sendmail(msg['From'], msg['To'], msg.as_string())
-            s.close()
-        except:
-            raise ReportFailure('Unable to send message via SMTP.')
-
-        return "Message sent!"
-
-class BugzillaReporter(object):
-    def getName(self):
-        return 'Bugzilla'
-    
-    def getParameters(self):
-        return [TextParameter(x) for x in ['URL','Product']]
-
-    def fileReport(self, report, parameters):
-        raise NotImplementedError
- 
-
-class RadarClassificationParameter(SelectionParameter):
-  def __init__(self):
-    SelectionParameter.__init__(self,"Classification",
-            [['1', 'Security'], ['2', 'Crash/Hang/Data Loss'],
-             ['3', 'Performance'], ['4', 'UI/Usability'], 
-             ['6', 'Serious Bug'], ['7', 'Other']])
-
-  def saveConfigValue(self):
-    return False
-    
-  def getValue(self,r,bugtype,getConfigOption):
-    if bugtype.find("leak") != -1:
-      return '3'
-    elif bugtype.find("dereference") != -1:
-      return '2'
-    elif bugtype.find("missing ivar release") != -1:
-      return '3'
-    else:
-      return '7'
-
-class RadarReporter(object):
-    @staticmethod
-    def isAvailable():
-        # FIXME: Find this .scpt better
-        path = os.path.join(os.path.dirname(__file__),'../share/scan-view/GetRadarVersion.scpt')
-        try:
-          p = subprocess.Popen(['osascript',path], 
-          stdout=subprocess.PIPE, stderr=subprocess.PIPE)
-        except:
-            return False
-        data,err = p.communicate()
-        res = p.wait()
-        # FIXME: Check version? Check for no errors?
-        return res == 0
-
-    def getName(self):
-        return 'Radar'
-
-    def getParameters(self):
-        return [ TextParameter('Component'), TextParameter('Component Version'),
-                 RadarClassificationParameter() ]
-
-    def fileReport(self, report, parameters):
-        component = parameters.get('Component', '')
-        componentVersion = parameters.get('Component Version', '')
-        classification = parameters.get('Classification', '')
-        personID = ""
-        diagnosis = ""
-        config = ""
-
-        if not component.strip():
-            component = 'Bugs found by clang Analyzer'
-        if not componentVersion.strip():
-            componentVersion = 'X'
-
-        script = os.path.join(os.path.dirname(__file__),'../share/scan-view/FileRadar.scpt')
-        args = ['osascript', script, component, componentVersion, classification, personID, report.title,
-                report.description, diagnosis, config] + [os.path.abspath(f) for f in report.files]
-#        print >>sys.stderr, args
-        try:
-          p = subprocess.Popen(args, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
-        except:
-            raise ReportFailure("Unable to file radar (AppleScript failure).")
-        data, err = p.communicate()
-        res = p.wait()
-
-        if res:
-            raise ReportFailure("Unable to file radar (AppleScript failure).")
-
-        try:
-            values = eval(data)
-        except:
-            raise ReportFailure("Unable to process radar results.")
-
-        # We expect (int: bugID, str: message)
-        if len(values) != 2 or not isinstance(values[0], int):
-            raise ReportFailure("Unable to process radar results.")
-
-        bugID,message = values
-        bugID = int(bugID)
-        
-        if not bugID:
-            raise ReportFailure(message)
-        
-        return "Filed: <a href=\"rdar://%d/\">%d</a>"%(bugID,bugID)
-
-###
-
-def getReporters():
-    reporters = []
-    if RadarReporter.isAvailable():
-        reporters.append(RadarReporter())
-    reporters.append(EmailReporter())
-    return reporters
-
diff --git a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
index 10d2d6ec3916a..a3a3a911b85c2 100644
--- a/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
+++ b/clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
@@ -2580,6 +2580,31 @@ struct CtorInitsNonTrivial : NonTrivial
     EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
     EXPECT_TRUE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
   }
+  {
+    auto M = binaryOperator(hasOperatorName("!="));
+    EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
+    EXPECT_FALSE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
+  }
+  {
+    auto M = unaryOperator(hasOperatorName("++"));
+    EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
+    EXPECT_FALSE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
+  }
+  {
+    auto M = declStmt(hasSingleDecl(varDecl(matchesName("__range"))));
+    EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
+    EXPECT_FALSE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
+  }
+  {
+    auto M = declStmt(hasSingleDecl(varDecl(matchesName("__begin"))));
+    EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
+    EXPECT_FALSE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
+  }
+  {
+    auto M = declStmt(hasSingleDecl(varDecl(matchesName("__end"))));
+    EXPECT_TRUE(matches(Code, traverse(TK_AsIs, M)));
+    EXPECT_FALSE(matches(Code, traverse(TK_IgnoreUnlessSpelledInSource, M)));
+  }
 
   Code = R"cpp(
   void rangeFor()
diff --git a/clang/unittests/CMakeLists.txt b/clang/unittests/CMakeLists.txt
index 4c222e24599f0..bb635dfff991a 100644
--- a/clang/unittests/CMakeLists.txt
+++ b/clang/unittests/CMakeLists.txt
@@ -24,13 +24,13 @@ add_subdirectory(Driver)
 if(CLANG_ENABLE_STATIC_ANALYZER)
   add_subdirectory(Analysis)
   add_subdirectory(StaticAnalyzer)
-  add_subdirectory(Frontend)
 endif()
 add_subdirectory(ASTMatchers)
 add_subdirectory(AST)
 add_subdirectory(CrossTU)
 add_subdirectory(Tooling)
 add_subdirectory(Format)
+add_subdirectory(Frontend)
 add_subdirectory(Rewrite)
 add_subdirectory(Sema)
 add_subdirectory(CodeGen)
diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp
index d2aed304f213a..bdf4abb26c7e1 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -11989,6 +11989,20 @@ TEST_F(FormatTest, ConfigurableSpacesInParentheses) {
                "  do_something((int) i);\n"
                "} while (something( ));",
                Spaces);
+
+  verifyFormat("size_t idx = (size_t) (ptr - ((char *) file));", Spaces);
+  verifyFormat("size_t idx = (size_t) a;", Spaces);
+  verifyFormat("size_t idx = (size_t) (a - 1);", Spaces);
+  verifyFormat("size_t idx = (a->*foo)(a - 1);", Spaces);
+  verifyFormat("size_t idx = (a->foo)(a - 1);", Spaces);
+  verifyFormat("size_t idx = (*foo)(a - 1);", Spaces);
+  Spaces.SpaceAfterCStyleCast = false;
+  verifyFormat("size_t idx = (size_t)(ptr - ((char *)file));", Spaces);
+  verifyFormat("size_t idx = (size_t)a;", Spaces);
+  verifyFormat("size_t idx = (size_t)(a - 1);", Spaces);
+  verifyFormat("size_t idx = (a->*foo)(a - 1);", Spaces);
+  verifyFormat("size_t idx = (a->foo)(a - 1);", Spaces);
+  verifyFormat("size_t idx = (*foo)(a - 1);", Spaces);
 }
 
 TEST_F(FormatTest, ConfigurableSpacesInSquareBrackets) {
@@ -12077,6 +12091,17 @@ TEST_F(FormatTest, ConfigurableSpaceBeforeColon) {
                "case 1:\n"
                "default:\n"
                "}");
+  verifyFormat("switch (allBraces) {\n"
+               "case 1: {\n"
+               "  break;\n"
+               "}\n"
+               "case 2: {\n"
+               "  [[fallthrough]];\n"
+               "}\n"
+               "default: {\n"
+               "  break;\n"
+               "}\n"
+               "}");
 
   FormatStyle CtorInitializerStyle = getLLVMStyleWithColumns(30);
   CtorInitializerStyle.SpaceBeforeCtorInitializerColon = false;
@@ -12094,6 +12119,18 @@ TEST_F(FormatTest, ConfigurableSpaceBeforeColon) {
                "default:\n"
                "}",
                CtorInitializerStyle);
+  verifyFormat("switch (allBraces) {\n"
+               "case 1: {\n"
+               "  break;\n"
+               "}\n"
+               "case 2: {\n"
+               "  [[fallthrough]];\n"
+               "}\n"
+               "default: {\n"
+               "  break;\n"
+               "}\n"
+               "}",
+               CtorInitializerStyle);
   CtorInitializerStyle.BreakConstructorInitializers =
       FormatStyle::BCIS_AfterColon;
   verifyFormat("Fooooooooooo::Fooooooooooo():\n"
@@ -12134,6 +12171,18 @@ TEST_F(FormatTest, ConfigurableSpaceBeforeColon) {
                "default:\n"
                "}",
                InheritanceStyle);
+  verifyFormat("switch (allBraces) {\n"
+               "case 1: {\n"
+               "  break;\n"
+               "}\n"
+               "case 2: {\n"
+               "  [[fallthrough]];\n"
+               "}\n"
+               "default: {\n"
+               "  break;\n"
+               "}\n"
+               "}",
+               InheritanceStyle);
   InheritanceStyle.BreakInheritanceList = FormatStyle::BILS_AfterColon;
   verifyFormat("class Foooooooooooooooooooooo:\n"
                "    public aaaaaaaaaaaaaaaaaa,\n"
@@ -12174,8 +12223,45 @@ TEST_F(FormatTest, ConfigurableSpaceBeforeColon) {
                "default:\n"
                "}",
                ForLoopStyle);
+  verifyFormat("switch (allBraces) {\n"
+               "case 1: {\n"
+               "  break;\n"
+               "}\n"
+               "case 2: {\n"
+               "  [[fallthrough]];\n"
+               "}\n"
+               "default: {\n"
+               "  break;\n"
+               "}\n"
+               "}",
+               ForLoopStyle);
+
+  FormatStyle CaseStyle = getLLVMStyle();
+  CaseStyle.SpaceBeforeCaseColon = true;
+  verifyFormat("class Foo : public Bar {};", CaseStyle);
+  verifyFormat("Foo::Foo() : foo(1) {}", CaseStyle);
+  verifyFormat("for (auto a : b) {\n}", CaseStyle);
+  verifyFormat("int x = a ? b : c;", CaseStyle);
+  verifyFormat("switch (x) {\n"
+               "case 1 :\n"
+               "default :\n"
+               "}",
+               CaseStyle);
+  verifyFormat("switch (allBraces) {\n"
+               "case 1 : {\n"
+               "  break;\n"
+               "}\n"
+               "case 2 : {\n"
+               "  [[fallthrough]];\n"
+               "}\n"
+               "default : {\n"
+               "  break;\n"
+               "}\n"
+               "}",
+               CaseStyle);
 
   FormatStyle NoSpaceStyle = getLLVMStyle();
+  EXPECT_EQ(NoSpaceStyle.SpaceBeforeCaseColon, false);
   NoSpaceStyle.SpaceBeforeCtorInitializerColon = false;
   NoSpaceStyle.SpaceBeforeInheritanceColon = false;
   NoSpaceStyle.SpaceBeforeRangeBasedForLoopColon = false;
@@ -12193,6 +12279,54 @@ TEST_F(FormatTest, ConfigurableSpaceBeforeColon) {
                "default:\n"
                "}",
                NoSpaceStyle);
+  verifyFormat("switch (allBraces) {\n"
+               "case 1: {\n"
+               "  break;\n"
+               "}\n"
+               "case 2: {\n"
+               "  [[fallthrough]];\n"
+               "}\n"
+               "default: {\n"
+               "  break;\n"
+               "}\n"
+               "}",
+               NoSpaceStyle);
+
+  FormatStyle InvertedSpaceStyle = getLLVMStyle();
+  InvertedSpaceStyle.SpaceBeforeCaseColon = true;
+  InvertedSpaceStyle.SpaceBeforeCtorInitializerColon = false;
+  InvertedSpaceStyle.SpaceBeforeInheritanceColon = false;
+  InvertedSpaceStyle.SpaceBeforeRangeBasedForLoopColon = false;
+  verifyFormat("class Foo: public Bar {};", InvertedSpaceStyle);
+  verifyFormat("Foo::Foo(): foo(1) {}", InvertedSpaceStyle);
+  verifyFormat("for (auto a: b) {\n}", InvertedSpaceStyle);
+  verifyFormat("int x = a ? b : c;", InvertedSpaceStyle);
+  verifyFormat("{\n"
+               "label3:\n"
+               "  int x = 0;\n"
+               "}",
+               InvertedSpaceStyle);
+  verifyFormat("switch (x) {\n"
+               "case 1 :\n"
+               "case 2 : {\n"
+               "  break;\n"
+               "}\n"
+               "default :\n"
+               "  break;\n"
+               "}",
+               InvertedSpaceStyle);
+  verifyFormat("switch (allBraces) {\n"
+               "case 1 : {\n"
+               "  break;\n"
+               "}\n"
+               "case 2 : {\n"
+               "  [[fallthrough]];\n"
+               "}\n"
+               "default : {\n"
+               "  break;\n"
+               "}\n"
+               "}",
+               InvertedSpaceStyle);
 }
 
 TEST_F(FormatTest, ConfigurableSpaceAroundPointerQualifiers) {
@@ -13524,7 +13658,7 @@ TEST_F(FormatTest, WhitesmithsBraceBreaking) {
                "  {\n"
                "  switch (a)\n"
                "    {\n"
-               "    case 2:\n"
+               "  case 2:\n"
                "    {\n"
                "    }\n"
                "    break;\n"
@@ -13536,18 +13670,18 @@ TEST_F(FormatTest, WhitesmithsBraceBreaking) {
                "  {\n"
                "  switch (a)\n"
                "    {\n"
-               "    case 0:\n"
+               "  case 0:\n"
                "    break;\n"
-               "    case 1:\n"
+               "  case 1:\n"
                "    {\n"
                "    foo();\n"
                "    break;\n"
                "    }\n"
-               "    case 2:\n"
+               "  case 2:\n"
                "    {\n"
                "    }\n"
                "    break;\n"
-               "    default:\n"
+               "  default:\n"
                "    break;\n"
                "    }\n"
                "  }\n",
@@ -13557,12 +13691,12 @@ TEST_F(FormatTest, WhitesmithsBraceBreaking) {
                "  {\n"
                "  switch (a)\n"
                "    {\n"
-               "    case 0:\n"
+               "  case 0:\n"
                "    {\n"
                "    foo(x);\n"
                "    }\n"
                "    break;\n"
-               "    default:\n"
+               "  default:\n"
                "    {\n"
                "    foo(1);\n"
                "    }\n"
@@ -14170,6 +14304,7 @@ TEST_F(FormatTest, ParsesConfigurationBools) {
   CHECK_PARSE_BOOL(SpaceAfterTemplateKeyword);
   CHECK_PARSE_BOOL(SpaceAfterLogicalNot);
   CHECK_PARSE_BOOL(SpaceBeforeAssignmentOperators);
+  CHECK_PARSE_BOOL(SpaceBeforeCaseColon);
   CHECK_PARSE_BOOL(SpaceBeforeCpp11BracedList);
   CHECK_PARSE_BOOL(SpaceBeforeCtorInitializerColon);
   CHECK_PARSE_BOOL(SpaceBeforeInheritanceColon);
diff --git a/clang/unittests/Format/FormatTestComments.cpp b/clang/unittests/Format/FormatTestComments.cpp
index 27dfe71367b30..457e7321ec759 100644
--- a/clang/unittests/Format/FormatTestComments.cpp
+++ b/clang/unittests/Format/FormatTestComments.cpp
@@ -702,6 +702,12 @@ TEST_F(FormatTestComments, SplitsLongCxxComments) {
                    "  // long 1 2 3 4 5 6\n"
                    "}",
                    getLLVMStyleWithColumns(20)));
+
+  EXPECT_EQ("//: A comment that\n"
+            "//: doesn't fit on\n"
+            "//: one line",
+            format("//: A comment that doesn't fit on one line",
+                   getLLVMStyleWithColumns(20)));
 }
 
 TEST_F(FormatTestComments, PreservesHangingIndentInCxxComments) {
diff --git a/clang/unittests/Format/FormatTestTextProto.cpp b/clang/unittests/Format/FormatTestTextProto.cpp
index 3ae13d1728657..1e25948938416 100644
--- a/clang/unittests/Format/FormatTestTextProto.cpp
+++ b/clang/unittests/Format/FormatTestTextProto.cpp
@@ -380,25 +380,29 @@ TEST_F(FormatTestTextProto, KeepsCommentsIndentedInList) {
                "cccccccccccccccccccccccc: 3849");
 }
 
-TEST_F(FormatTestTextProto, UnderstandsHashHashComments) {
+TEST_F(FormatTestTextProto, UnderstandsHashComments) {
   FormatStyle Style = getGoogleStyle(FormatStyle::LK_TextProto);
   Style.ColumnLimit = 60; // To make writing tests easier.
   EXPECT_EQ("aaa: 100\n"
-            "##this is a double-hash comment.\n"
+            "## this is a double-hash comment.\n"
             "bb: 100\n"
             "## another double-hash comment.\n"
             "### a triple-hash comment\n"
             "cc: 200\n"
+            "### another triple-hash comment\n"
             "#### a quadriple-hash comment\n"
-            "dd: 100\n",
+            "dd: 100\n"
+            "#### another quadriple-hash comment\n",
             format("aaa: 100\n"
                    "##this is a double-hash comment.\n"
                    "bb: 100\n"
                    "## another double-hash comment.\n"
-                   "### a triple-hash comment\n"
+                   "###a triple-hash comment\n"
                    "cc: 200\n"
-                   "#### a quadriple-hash comment\n"
-                   "dd: 100\n",
+                   "### another triple-hash comment\n"
+                   "####a quadriple-hash comment\n"
+                   "dd: 100\n"
+                   "#### another quadriple-hash comment\n",
                    Style));
 }
 
diff --git a/clang/unittests/Frontend/CompilerInvocationTest.cpp b/clang/unittests/Frontend/CompilerInvocationTest.cpp
index 71e8d0907fc8c..51b7ba8c147fe 100644
--- a/clang/unittests/Frontend/CompilerInvocationTest.cpp
+++ b/clang/unittests/Frontend/CompilerInvocationTest.cpp
@@ -342,70 +342,30 @@ TEST_F(CommandLineTest, CanGenerateCC1CommandLineSeparateRequiredAbsent) {
   ASSERT_THAT(GeneratedArgs, Contains(StrEq(DefaultTriple.c_str())));
 }
 
-TEST_F(CommandLineTest, SeparateEnumNonDefault) {
+TEST_F(CommandLineTest, CanGenerateCC1CommandLineSeparateEnumNonDefault) {
   const char *Args[] = {"-mrelocation-model", "static"};
 
   CompilerInvocation::CreateFromArgs(Invocation, Args, *Diags);
 
   ASSERT_FALSE(Diags->hasErrorOccurred());
-  ASSERT_EQ(Invocation.getCodeGenOpts().RelocationModel, Reloc::Model::Static);
 
   Invocation.generateCC1CommandLine(GeneratedArgs, *this);
 
   // Non default relocation model.
-  ASSERT_THAT(GeneratedArgs, Contains(StrEq("-mrelocation-model")));
   ASSERT_THAT(GeneratedArgs, Contains(StrEq("static")));
-  ASSERT_THAT(GeneratedArgs, Not(Contains(StrEq("-mrelocation-model=static"))));
 }
 
-TEST_F(CommandLineTest, SeparateEnumDefault) {
+TEST_F(CommandLineTest, CanGenerateCC1COmmandLineSeparateEnumDefault) {
   const char *Args[] = {"-mrelocation-model", "pic"};
 
   CompilerInvocation::CreateFromArgs(Invocation, Args, *Diags);
 
   ASSERT_FALSE(Diags->hasErrorOccurred());
-  ASSERT_EQ(Invocation.getCodeGenOpts().RelocationModel, Reloc::Model::PIC_);
 
   Invocation.generateCC1CommandLine(GeneratedArgs, *this);
 
   // Default relocation model.
-  ASSERT_THAT(GeneratedArgs, Not(Contains(StrEq("-mrelocation-model"))));
   ASSERT_THAT(GeneratedArgs, Not(Contains(StrEq("pic"))));
-  ASSERT_THAT(GeneratedArgs, Not(Contains(StrEq("-mrelocation-model=pic"))));
-}
-
-TEST_F(CommandLineTest, JoinedEnumNonDefault) {
-  const char *Args[] = {"-fobjc-dispatch-method=non-legacy"};
-
-  CompilerInvocation::CreateFromArgs(Invocation, Args, *Diags);
-
-  ASSERT_FALSE(Diags->hasErrorOccurred());
-  ASSERT_EQ(Invocation.getCodeGenOpts().getObjCDispatchMethod(),
-            CodeGenOptions::NonLegacy);
-
-  Invocation.generateCC1CommandLine(GeneratedArgs, *this);
-
-  ASSERT_THAT(GeneratedArgs,
-              Contains(StrEq("-fobjc-dispatch-method=non-legacy")));
-  ASSERT_THAT(GeneratedArgs, Not(Contains(StrEq("-fobjc-dispatch-method="))));
-  ASSERT_THAT(GeneratedArgs, Not(Contains(StrEq("non-legacy"))));
-}
-
-TEST_F(CommandLineTest, JoinedEnumDefault) {
-  const char *Args[] = {"-fobjc-dispatch-method=legacy"};
-
-  CompilerInvocation::CreateFromArgs(Invocation, Args, *Diags);
-
-  ASSERT_FALSE(Diags->hasErrorOccurred());
-  ASSERT_EQ(Invocation.getCodeGenOpts().getObjCDispatchMethod(),
-            CodeGenOptions::Legacy);
-
-  Invocation.generateCC1CommandLine(GeneratedArgs, *this);
-
-  ASSERT_THAT(GeneratedArgs,
-              Not(Contains(StrEq("-fobjc-dispatch-method=legacy"))));
-  ASSERT_THAT(GeneratedArgs, Not(Contains(StrEq("-fobjc-dispatch-method="))));
-  ASSERT_THAT(GeneratedArgs, Not(Contains(StrEq("legacy"))));
 }
 
 // Tree of boolean options that can be (directly or transitively) implied by
diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html
index 9be6f1262b681..f2f711b550946 100755
--- a/clang/www/cxx_dr_status.html
+++ b/clang/www/cxx_dr_status.html
@@ -9162,7 +9162,7 @@ <h2 id="cxxdr">C++ defect report implementation status</h2>
     <td><a href="https://wg21.link/cwg1558">1558</a></td>
     <td>CD4</td>
     <td>Unused arguments in alias template specializations</td>
-    <td class="unreleased" align="center">Clang 12</td>
+    <td class="none" align="center">Unknown</td>
   </tr>
   <tr id="1559">
     <td><a href="https://wg21.link/cwg1559">1559</a></td>
@@ -12198,7 +12198,7 @@ <h2 id="cxxdr">C++ defect report implementation status</h2>
     <td><a href="https://wg21.link/cwg2064">2064</a></td>
     <td>CD4</td>
     <td>Conflicting specifications for dependent <I>decltype-specifier</I>s</td>
-    <td class="unreleased" align="center">Clang 12</td>
+    <td class="none" align="center">Unknown</td>
   </tr>
   <tr class="open" id="2065">
     <td><a href="https://wg21.link/cwg2065">2065</a></td>
diff --git a/compiler-rt/lib/asan/asan_linux.cpp b/compiler-rt/lib/asan/asan_linux.cpp
index fb1a442b3d437..4bcbe5d02e334 100644
--- a/compiler-rt/lib/asan/asan_linux.cpp
+++ b/compiler-rt/lib/asan/asan_linux.cpp
@@ -55,6 +55,7 @@ extern Elf_Dyn _DYNAMIC;
 #else
 #include <sys/ucontext.h>
 #include <link.h>
+extern ElfW(Dyn) _DYNAMIC[];
 #endif
 
 // x86-64 FreeBSD 9.2 and older define 'ucontext_t' incorrectly in
@@ -84,7 +85,7 @@ bool IsSystemHeapAddress (uptr addr) { return false; }
 
 void *AsanDoesNotSupportStaticLinkage() {
   // This will fail to link with -static.
-  return &_DYNAMIC;  // defined in link.h
+  return &_DYNAMIC;
 }
 
 #if ASAN_PREMAP_SHADOW
diff --git a/compiler-rt/lib/memprof/memprof_linux.cpp b/compiler-rt/lib/memprof/memprof_linux.cpp
index 4846e988f58ec..61c833bfdf649 100644
--- a/compiler-rt/lib/memprof/memprof_linux.cpp
+++ b/compiler-rt/lib/memprof/memprof_linux.cpp
@@ -39,6 +39,8 @@
 #include <unistd.h>
 #include <unwind.h>
 
+extern ElfW(Dyn) _DYNAMIC[];
+
 typedef enum {
   MEMPROF_RT_VERSION_UNDEFINED = 0,
   MEMPROF_RT_VERSION_DYNAMIC,
@@ -58,7 +60,7 @@ void InitializePlatformExceptionHandlers() {}
 
 void *MemprofDoesNotSupportStaticLinkage() {
   // This will fail to link with -static.
-  return &_DYNAMIC; // defined in link.h
+  return &_DYNAMIC;
 }
 
 uptr FindDynamicShadowStart() {
diff --git a/compiler-rt/lib/memprof/memprof_mapping.h b/compiler-rt/lib/memprof/memprof_mapping.h
index f48018b1a8f2a..ba05b88db3070 100644
--- a/compiler-rt/lib/memprof/memprof_mapping.h
+++ b/compiler-rt/lib/memprof/memprof_mapping.h
@@ -37,7 +37,7 @@ extern uptr kHighMemEnd; // Initialized in __memprof_init.
 #define SHADOW_MASK ~(MEM_GRANULARITY - 1)
 
 #define MEM_TO_SHADOW(mem)                                                     \
-  (((mem & SHADOW_MASK) >> SHADOW_SCALE) + (SHADOW_OFFSET))
+  ((((mem) & SHADOW_MASK) >> SHADOW_SCALE) + (SHADOW_OFFSET))
 
 #define kLowMemBeg 0
 #define kLowMemEnd (SHADOW_OFFSET ? SHADOW_OFFSET - 1 : 0)
diff --git a/compiler-rt/lib/msan/msan_linux.cpp b/compiler-rt/lib/msan/msan_linux.cpp
index bfdae0b920c9b..d5baee38e7102 100644
--- a/compiler-rt/lib/msan/msan_linux.cpp
+++ b/compiler-rt/lib/msan/msan_linux.cpp
@@ -26,7 +26,6 @@
 #include <signal.h>
 #include <unistd.h>
 #include <unwind.h>
-#include <execinfo.h>
 #include <sys/time.h>
 #include <sys/resource.h>
 
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h
index 0350fe84b045b..15616f899d01e 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace.h
@@ -67,8 +67,6 @@ struct StackTrace {
   static uptr GetCurrentPc();
   static inline uptr GetPreviousInstructionPc(uptr pc);
   static uptr GetNextInstructionPc(uptr pc);
-  typedef bool (*SymbolizeCallback)(const void *pc, char *out_buffer,
-                                    int out_size);
 };
 
 // Performance-critical, must be in the header.
diff --git a/compiler-rt/lib/sanitizer_common/tests/sanitizer_test_utils.h b/compiler-rt/lib/sanitizer_common/tests/sanitizer_test_utils.h
index 525b1e4858529..016ce9e67d9ff 100644
--- a/compiler-rt/lib/sanitizer_common/tests/sanitizer_test_utils.h
+++ b/compiler-rt/lib/sanitizer_common/tests/sanitizer_test_utils.h
@@ -107,9 +107,7 @@ static inline uint32_t my_rand() {
 # define SANITIZER_TEST_HAS_MEMALIGN 0
 #endif
 
-#if !defined(__APPLE__) && !defined(__FreeBSD__) && !defined(__ANDROID__) && \
-    !defined(__NetBSD__) && !defined(_WIN32) && \
-    !(defined(__sun__) && defined(__svr4__))
+#if defined(__GLIBC__)
 # define SANITIZER_TEST_HAS_PVALLOC 1
 # define SANITIZER_TEST_HAS_MALLOC_USABLE_SIZE 1
 #else
diff --git a/compiler-rt/lib/scudo/standalone/allocator_config.h b/compiler-rt/lib/scudo/standalone/allocator_config.h
index 8f1757dab3227..12daaa2f6b440 100644
--- a/compiler-rt/lib/scudo/standalone/allocator_config.h
+++ b/compiler-rt/lib/scudo/standalone/allocator_config.h
@@ -25,13 +25,18 @@ namespace scudo {
 
 struct DefaultConfig {
   using SizeClassMap = DefaultSizeClassMap;
+  static const bool MaySupportMemoryTagging = false;
+
 #if SCUDO_CAN_USE_PRIMARY64
-  // 1GB Regions
-  typedef SizeClassAllocator64<SizeClassMap, 30U> Primary;
+  typedef SizeClassAllocator64<DefaultConfig> Primary;
+  static const uptr PrimaryRegionSizeLog = 30U;
 #else
-  // 512KB regions
-  typedef SizeClassAllocator32<SizeClassMap, 19U> Primary;
+  typedef SizeClassAllocator32<DefaultConfig> Primary;
+  static const uptr PrimaryRegionSizeLog = 19U;
 #endif
+  static const s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN;
+  static const s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX;
+
   typedef MapAllocatorCache<DefaultConfig> SecondaryCache;
   static const u32 SecondaryCacheEntriesArraySize = 32U;
   static const u32 SecondaryCacheDefaultMaxEntriesCount = 32U;
@@ -44,15 +49,18 @@ struct DefaultConfig {
 
 struct AndroidConfig {
   using SizeClassMap = AndroidSizeClassMap;
+  static const bool MaySupportMemoryTagging = true;
+
 #if SCUDO_CAN_USE_PRIMARY64
-  // 256MB regions
-  typedef SizeClassAllocator64<SizeClassMap, 28U, 1000, 1000,
-                               /*MaySupportMemoryTagging=*/true>
-      Primary;
+  typedef SizeClassAllocator64<AndroidConfig> Primary;
+  static const uptr PrimaryRegionSizeLog = 28U;
 #else
-  // 256KB regions
-  typedef SizeClassAllocator32<SizeClassMap, 18U, 1000, 1000> Primary;
+  typedef SizeClassAllocator32<AndroidConfig> Primary;
+  static const uptr PrimaryRegionSizeLog = 18U;
 #endif
+  static const s32 PrimaryMinReleaseToOsIntervalMs = 1000;
+  static const s32 PrimaryMaxReleaseToOsIntervalMs = 1000;
+
   typedef MapAllocatorCache<AndroidConfig> SecondaryCache;
   static const u32 SecondaryCacheEntriesArraySize = 256U;
   static const u32 SecondaryCacheDefaultMaxEntriesCount = 32U;
@@ -66,13 +74,18 @@ struct AndroidConfig {
 
 struct AndroidSvelteConfig {
   using SizeClassMap = SvelteSizeClassMap;
+  static const bool MaySupportMemoryTagging = false;
+
 #if SCUDO_CAN_USE_PRIMARY64
-  // 128MB regions
-  typedef SizeClassAllocator64<SizeClassMap, 27U, 1000, 1000> Primary;
+  typedef SizeClassAllocator64<AndroidSvelteConfig> Primary;
+  static const uptr PrimaryRegionSizeLog = 27U;
 #else
-  // 64KB regions
-  typedef SizeClassAllocator32<SizeClassMap, 16U, 1000, 1000> Primary;
+  typedef SizeClassAllocator32<AndroidSvelteConfig> Primary;
+  static const uptr PrimaryRegionSizeLog = 16U;
 #endif
+  static const s32 PrimaryMinReleaseToOsIntervalMs = 1000;
+  static const s32 PrimaryMaxReleaseToOsIntervalMs = 1000;
+
   typedef MapAllocatorCache<AndroidSvelteConfig> SecondaryCache;
   static const u32 SecondaryCacheEntriesArraySize = 16U;
   static const u32 SecondaryCacheDefaultMaxEntriesCount = 4U;
@@ -86,8 +99,14 @@ struct AndroidSvelteConfig {
 
 #if SCUDO_CAN_USE_PRIMARY64
 struct FuchsiaConfig {
-  // 1GB Regions
-  typedef SizeClassAllocator64<DefaultSizeClassMap, 30U> Primary;
+  using SizeClassMap = DefaultSizeClassMap;
+  static const bool MaySupportMemoryTagging = false;
+
+  typedef SizeClassAllocator64<FuchsiaConfig> Primary;
+  static const uptr PrimaryRegionSizeLog = 30U;
+  static const s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN;
+  static const s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX;
+
   typedef MapAllocatorNoCache SecondaryCache;
   template <class A>
   using TSDRegistryT = TSDRegistrySharedT<A, 8U, 4U>; // Shared, max 8 TSDs.
diff --git a/compiler-rt/lib/scudo/standalone/combined.h b/compiler-rt/lib/scudo/standalone/combined.h
index 7bf108e0b5e0e..911c49dcc3fd7 100644
--- a/compiler-rt/lib/scudo/standalone/combined.h
+++ b/compiler-rt/lib/scudo/standalone/combined.h
@@ -100,7 +100,7 @@ class Allocator {
 
       // Reset tag to 0 as this chunk may have been previously used for a tagged
       // user allocation.
-      if (UNLIKELY(Allocator.useMemoryTagging()))
+      if (UNLIKELY(useMemoryTagging<Params>(Allocator.Primary.Options.load())))
         storeTags(reinterpret_cast<uptr>(Ptr),
                   reinterpret_cast<uptr>(Ptr) + sizeof(QuarantineBatch));
 
@@ -161,6 +161,9 @@ class Allocator {
       Primary.Options.set(OptionBit::DeallocTypeMismatch);
     if (getFlags()->delete_size_mismatch)
       Primary.Options.set(OptionBit::DeleteSizeMismatch);
+    if (allocatorSupportsMemoryTagging<Params>() &&
+        systemSupportsMemoryTagging())
+      Primary.Options.set(OptionBit::UseMemoryTagging);
     Primary.Options.set(OptionBit::UseOddEvenTags);
 
     QuarantineMaxChunkSize =
@@ -240,7 +243,7 @@ class Allocator {
   }
 
   ALWAYS_INLINE void *untagPointerMaybe(void *Ptr) {
-    if (Primary.SupportsMemoryTagging)
+    if (allocatorSupportsMemoryTagging<Params>())
       return reinterpret_cast<void *>(
           untagPointer(reinterpret_cast<uptr>(Ptr)));
     return Ptr;
@@ -367,7 +370,7 @@ class Allocator {
       //
       // When memory tagging is enabled, zeroing the contents is done as part of
       // setting the tag.
-      if (UNLIKELY(useMemoryTagging(Options))) {
+      if (UNLIKELY(useMemoryTagging<Params>(Options))) {
         uptr PrevUserPtr;
         Chunk::UnpackedHeader Header;
         const uptr BlockSize = PrimaryT::getSizeByClassId(ClassId);
@@ -594,7 +597,7 @@ class Allocator {
                      : BlockEnd - (reinterpret_cast<uptr>(OldPtr) + NewSize)) &
             Chunk::SizeOrUnusedBytesMask;
         Chunk::compareExchangeHeader(Cookie, OldPtr, &NewHeader, &OldHeader);
-        if (UNLIKELY(ClassId && useMemoryTagging(Options))) {
+        if (UNLIKELY(ClassId && useMemoryTagging<Params>(Options))) {
           resizeTaggedChunk(reinterpret_cast<uptr>(OldTaggedPtr) + OldSize,
                             reinterpret_cast<uptr>(OldTaggedPtr) + NewSize,
                             BlockEnd);
@@ -692,7 +695,7 @@ class Allocator {
       if (getChunkFromBlock(Block, &Chunk, &Header) &&
           Header.State == Chunk::State::Allocated) {
         uptr TaggedChunk = Chunk;
-        if (useMemoryTagging(Primary.Options.load()))
+        if (useMemoryTagging<Params>(Primary.Options.load()))
           TaggedChunk = loadTag(Chunk);
         Callback(TaggedChunk, getSize(reinterpret_cast<void *>(Chunk), &Header),
                  Arg);
@@ -783,15 +786,14 @@ class Allocator {
            Header.State == Chunk::State::Allocated;
   }
 
-  bool useMemoryTagging() const {
-    return useMemoryTagging(Primary.Options.load());
+  bool useMemoryTaggingTestOnly() const {
+    return useMemoryTagging<Params>(Primary.Options.load());
   }
-  static bool useMemoryTagging(Options Options) {
-    return PrimaryT::useMemoryTagging(Options);
+  void disableMemoryTagging() {
+    if (allocatorSupportsMemoryTagging<Params>())
+      Primary.Options.clear(OptionBit::UseMemoryTagging);
   }
 
-  void disableMemoryTagging() { Primary.disableMemoryTagging(); }
-
   void setTrackAllocationStacks(bool Track) {
     initThreadMaybe();
     if (Track)
@@ -823,7 +825,7 @@ class Allocator {
                            const char *MemoryTags, uintptr_t MemoryAddr,
                            size_t MemorySize) {
     *ErrorInfo = {};
-    if (!PrimaryT::SupportsMemoryTagging ||
+    if (!allocatorSupportsMemoryTagging<Params>() ||
         MemoryAddr + MemorySize < MemoryAddr)
       return;
 
@@ -930,7 +932,7 @@ class Allocator {
   }
 
 private:
-  using SecondaryT = MapAllocator<typename Params::SecondaryCache>;
+  using SecondaryT = MapAllocator<Params>;
   typedef typename PrimaryT::SizeClassMap SizeClassMap;
 
   static const uptr MinAlignmentLog = SCUDO_MIN_ALIGNMENT_LOG;
@@ -942,7 +944,7 @@ class Allocator {
 
   static_assert(MinAlignment >= sizeof(Chunk::PackedHeader),
                 "Minimal alignment must at least cover a chunk header.");
-  static_assert(!PrimaryT::SupportsMemoryTagging ||
+  static_assert(!allocatorSupportsMemoryTagging<Params>() ||
                     MinAlignment >= archMemoryTagGranuleSize(),
                 "");
 
@@ -1037,7 +1039,7 @@ class Allocator {
   void quarantineOrDeallocateChunk(Options Options, void *Ptr,
                                    Chunk::UnpackedHeader *Header, uptr Size) {
     Chunk::UnpackedHeader NewHeader = *Header;
-    if (UNLIKELY(NewHeader.ClassId && useMemoryTagging(Options))) {
+    if (UNLIKELY(NewHeader.ClassId && useMemoryTagging<Params>(Options))) {
       u8 PrevTag = extractTag(loadTag(reinterpret_cast<uptr>(Ptr)));
       if (!TSDRegistry.getDisableMemInit()) {
         uptr TaggedBegin, TaggedEnd;
diff --git a/compiler-rt/lib/scudo/standalone/linux.cpp b/compiler-rt/lib/scudo/standalone/linux.cpp
index 12f3da620e123..d2464677b2792 100644
--- a/compiler-rt/lib/scudo/standalone/linux.cpp
+++ b/compiler-rt/lib/scudo/standalone/linux.cpp
@@ -35,10 +35,6 @@
 #define ANDROID_PR_SET_VMA_ANON_NAME 0
 #endif
 
-#ifdef ANDROID_EXPERIMENTAL_MTE
-#include <bionic/mte_kernel.h>
-#endif
-
 namespace scudo {
 
 uptr getPageSize() { return static_cast<uptr>(sysconf(_SC_PAGESIZE)); }
@@ -54,7 +50,10 @@ void *map(void *Addr, uptr Size, UNUSED const char *Name, uptr Flags,
     MmapProt = PROT_NONE;
   } else {
     MmapProt = PROT_READ | PROT_WRITE;
-#if defined(__aarch64__) && defined(ANDROID_EXPERIMENTAL_MTE)
+#if defined(__aarch64__)
+#ifndef PROT_MTE
+#define PROT_MTE 0x20
+#endif
     if (Flags & MAP_MEMTAG)
       MmapProt |= PROT_MTE;
 #endif
diff --git a/compiler-rt/lib/scudo/standalone/memtag.h b/compiler-rt/lib/scudo/standalone/memtag.h
index 4b22c727849db..d848e3a0b6c9b 100644
--- a/compiler-rt/lib/scudo/standalone/memtag.h
+++ b/compiler-rt/lib/scudo/standalone/memtag.h
@@ -14,9 +14,6 @@
 #if SCUDO_LINUX
 #include <sys/auxv.h>
 #include <sys/prctl.h>
-#if defined(ANDROID_EXPERIMENTAL_MTE)
-#include <bionic/mte_kernel.h>
-#endif
 #endif
 
 namespace scudo {
@@ -56,20 +53,28 @@ inline uint8_t extractTag(uptr Ptr) {
 #if defined(__aarch64__)
 
 inline bool systemSupportsMemoryTagging() {
-#if defined(ANDROID_EXPERIMENTAL_MTE)
-  return getauxval(AT_HWCAP2) & HWCAP2_MTE;
-#else
-  return false;
+#ifndef HWCAP2_MTE
+#define HWCAP2_MTE (1 << 18)
 #endif
+  return getauxval(AT_HWCAP2) & HWCAP2_MTE;
 }
 
 inline bool systemDetectsMemoryTagFaultsTestOnly() {
-#if defined(ANDROID_EXPERIMENTAL_MTE)
-  return (prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0) & PR_MTE_TCF_MASK) !=
-         PR_MTE_TCF_NONE;
-#else
-  return false;
+#ifndef PR_GET_TAGGED_ADDR_CTRL
+#define PR_GET_TAGGED_ADDR_CTRL 56
 #endif
+#ifndef PR_MTE_TCF_SHIFT
+#define PR_MTE_TCF_SHIFT 1
+#endif
+#ifndef PR_MTE_TCF_NONE
+#define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
+#endif
+#ifndef PR_MTE_TCF_MASK
+#define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
+#endif
+  return (static_cast<unsigned long>(
+              prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)) &
+          PR_MTE_TCF_MASK) != PR_MTE_TCF_NONE;
 }
 
 inline void disableMemoryTagChecksTestOnly() {
@@ -263,6 +268,11 @@ inline void setRandomTag(void *Ptr, uptr Size, uptr ExcludeMask,
   *TaggedEnd = storeTags(*TaggedBegin, *TaggedBegin + Size);
 }
 
+template <typename Config>
+inline constexpr bool allocatorSupportsMemoryTagging() {
+  return archSupportsMemoryTagging() && Config::MaySupportMemoryTagging;
+}
+
 } // namespace scudo
 
 #endif
diff --git a/compiler-rt/lib/scudo/standalone/options.h b/compiler-rt/lib/scudo/standalone/options.h
index 2cffc4d75c38c..91301bf5ec9c2 100644
--- a/compiler-rt/lib/scudo/standalone/options.h
+++ b/compiler-rt/lib/scudo/standalone/options.h
@@ -11,6 +11,7 @@
 
 #include "atomic_helpers.h"
 #include "common.h"
+#include "memtag.h"
 
 namespace scudo {
 
@@ -36,6 +37,11 @@ struct Options {
   }
 };
 
+template <typename Config> bool useMemoryTagging(Options Options) {
+  return allocatorSupportsMemoryTagging<Config>() &&
+         Options.get(OptionBit::UseMemoryTagging);
+}
+
 struct AtomicOptions {
   atomic_u32 Val;
 
diff --git a/compiler-rt/lib/scudo/standalone/primary32.h b/compiler-rt/lib/scudo/standalone/primary32.h
index 0db95d2e1f113..a88a2a67e9515 100644
--- a/compiler-rt/lib/scudo/standalone/primary32.h
+++ b/compiler-rt/lib/scudo/standalone/primary32.h
@@ -39,23 +39,17 @@ namespace scudo {
 // Memory used by this allocator is never unmapped but can be partially
 // reclaimed if the platform allows for it.
 
-template <class SizeClassMapT, uptr RegionSizeLog,
-          s32 MinReleaseToOsIntervalMs = INT32_MIN,
-          s32 MaxReleaseToOsIntervalMs = INT32_MAX>
-class SizeClassAllocator32 {
+template <typename Config> class SizeClassAllocator32 {
 public:
-  typedef SizeClassMapT SizeClassMap;
+  typedef typename Config::SizeClassMap SizeClassMap;
   // The bytemap can only track UINT8_MAX - 1 classes.
   static_assert(SizeClassMap::LargestClassId <= (UINT8_MAX - 1), "");
   // Regions should be large enough to hold the largest Block.
-  static_assert((1UL << RegionSizeLog) >= SizeClassMap::MaxSize, "");
-  typedef SizeClassAllocator32<SizeClassMapT, RegionSizeLog,
-                               MinReleaseToOsIntervalMs,
-                               MaxReleaseToOsIntervalMs>
-      ThisT;
+  static_assert((1UL << Config::PrimaryRegionSizeLog) >= SizeClassMap::MaxSize,
+                "");
+  typedef SizeClassAllocator32<Config> ThisT;
   typedef SizeClassAllocatorLocalCache<ThisT> CacheT;
   typedef typename CacheT::TransferBatch TransferBatch;
-  static const bool SupportsMemoryTagging = false;
 
   static uptr getSizeByClassId(uptr ClassId) {
     return (ClassId == SizeClassMap::BatchClassId)
@@ -199,9 +193,9 @@ class SizeClassAllocator32 {
 
   bool setOption(Option O, sptr Value) {
     if (O == Option::ReleaseInterval) {
-      const s32 Interval =
-          Max(Min(static_cast<s32>(Value), MaxReleaseToOsIntervalMs),
-              MinReleaseToOsIntervalMs);
+      const s32 Interval = Max(
+          Min(static_cast<s32>(Value), Config::PrimaryMaxReleaseToOsIntervalMs),
+          Config::PrimaryMinReleaseToOsIntervalMs);
       atomic_store_relaxed(&ReleaseToOsIntervalMs, Interval);
       return true;
     }
@@ -221,9 +215,6 @@ class SizeClassAllocator32 {
     return TotalReleasedBytes;
   }
 
-  static bool useMemoryTagging(UNUSED Options Options) { return false; }
-  void disableMemoryTagging() {}
-
   const char *getRegionInfoArrayAddress() const { return nullptr; }
   static uptr getRegionInfoArraySize() { return 0; }
 
@@ -236,8 +227,9 @@ class SizeClassAllocator32 {
 
 private:
   static const uptr NumClasses = SizeClassMap::NumClasses;
-  static const uptr RegionSize = 1UL << RegionSizeLog;
-  static const uptr NumRegions = SCUDO_MMAP_RANGE_SIZE >> RegionSizeLog;
+  static const uptr RegionSize = 1UL << Config::PrimaryRegionSizeLog;
+  static const uptr NumRegions =
+      SCUDO_MMAP_RANGE_SIZE >> Config::PrimaryRegionSizeLog;
   static const u32 MaxNumBatches = SCUDO_ANDROID ? 4U : 8U;
   typedef FlatByteMap<NumRegions> ByteMap;
 
@@ -270,7 +262,7 @@ class SizeClassAllocator32 {
   static_assert(sizeof(SizeClassInfo) % SCUDO_CACHE_LINE_SIZE == 0, "");
 
   uptr computeRegionId(uptr Mem) {
-    const uptr Id = Mem >> RegionSizeLog;
+    const uptr Id = Mem >> Config::PrimaryRegionSizeLog;
     CHECK_LT(Id, NumRegions);
     return Id;
   }
diff --git a/compiler-rt/lib/scudo/standalone/primary64.h b/compiler-rt/lib/scudo/standalone/primary64.h
index f9854cbfd4d68..2724a2529f759 100644
--- a/compiler-rt/lib/scudo/standalone/primary64.h
+++ b/compiler-rt/lib/scudo/standalone/primary64.h
@@ -40,21 +40,12 @@ namespace scudo {
 // The memory used by this allocator is never unmapped, but can be partially
 // released if the platform allows for it.
 
-template <class SizeClassMapT, uptr RegionSizeLog,
-          s32 MinReleaseToOsIntervalMs = INT32_MIN,
-          s32 MaxReleaseToOsIntervalMs = INT32_MAX,
-          bool MaySupportMemoryTagging = false>
-class SizeClassAllocator64 {
+template <typename Config> class SizeClassAllocator64 {
 public:
-  typedef SizeClassMapT SizeClassMap;
-  typedef SizeClassAllocator64<
-      SizeClassMap, RegionSizeLog, MinReleaseToOsIntervalMs,
-      MaxReleaseToOsIntervalMs, MaySupportMemoryTagging>
-      ThisT;
+  typedef typename Config::SizeClassMap SizeClassMap;
+  typedef SizeClassAllocator64<Config> ThisT;
   typedef SizeClassAllocatorLocalCache<ThisT> CacheT;
   typedef typename CacheT::TransferBatch TransferBatch;
-  static const bool SupportsMemoryTagging =
-      MaySupportMemoryTagging && archSupportsMemoryTagging();
 
   static uptr getSizeByClassId(uptr ClassId) {
     return (ClassId == SizeClassMap::BatchClassId)
@@ -83,9 +74,6 @@ class SizeClassAllocator64 {
       Region->ReleaseInfo.LastReleaseAtNs = Time;
     }
     setOption(Option::ReleaseInterval, static_cast<sptr>(ReleaseToOsInterval));
-
-    if (SupportsMemoryTagging && systemSupportsMemoryTagging())
-      Options.set(OptionBit::UseMemoryTagging);
   }
   void init(s32 ReleaseToOsInterval) {
     memset(this, 0, sizeof(*this));
@@ -178,9 +166,9 @@ class SizeClassAllocator64 {
 
   bool setOption(Option O, sptr Value) {
     if (O == Option::ReleaseInterval) {
-      const s32 Interval =
-          Max(Min(static_cast<s32>(Value), MaxReleaseToOsIntervalMs),
-              MinReleaseToOsIntervalMs);
+      const s32 Interval = Max(
+          Min(static_cast<s32>(Value), Config::PrimaryMaxReleaseToOsIntervalMs),
+          Config::PrimaryMinReleaseToOsIntervalMs);
       atomic_store_relaxed(&ReleaseToOsIntervalMs, Interval);
       return true;
     }
@@ -200,11 +188,6 @@ class SizeClassAllocator64 {
     return TotalReleasedBytes;
   }
 
-  static bool useMemoryTagging(Options Options) {
-    return SupportsMemoryTagging && Options.get(OptionBit::UseMemoryTagging);
-  }
-  void disableMemoryTagging() { Options.clear(OptionBit::UseMemoryTagging); }
-
   const char *getRegionInfoArrayAddress() const {
     return reinterpret_cast<const char *>(RegionInfoArray);
   }
@@ -258,7 +241,7 @@ class SizeClassAllocator64 {
   AtomicOptions Options;
 
 private:
-  static const uptr RegionSize = 1UL << RegionSizeLog;
+  static const uptr RegionSize = 1UL << Config::PrimaryRegionSizeLog;
   static const uptr NumClasses = SizeClassMap::NumClasses;
   static const uptr PrimarySize = RegionSize * NumClasses;
 
@@ -308,7 +291,7 @@ class SizeClassAllocator64 {
   }
 
   uptr getRegionBaseByClassId(uptr ClassId) const {
-    return PrimaryBase + (ClassId << RegionSizeLog);
+    return PrimaryBase + (ClassId << Config::PrimaryRegionSizeLog);
   }
 
   NOINLINE TransferBatch *populateFreeList(CacheT *C, uptr ClassId,
@@ -342,7 +325,7 @@ class SizeClassAllocator64 {
       if (!map(reinterpret_cast<void *>(RegionBeg + MappedUser), UserMapSize,
                "scudo:primary",
                MAP_ALLOWNOMEM | MAP_RESIZABLE |
-                   (useMemoryTagging(Options.load()) ? MAP_MEMTAG : 0),
+                   (useMemoryTagging<Config>(Options.load()) ? MAP_MEMTAG : 0),
                &Region->Data))
         return nullptr;
       Region->MappedUser += UserMapSize;
diff --git a/compiler-rt/lib/scudo/standalone/secondary.h b/compiler-rt/lib/scudo/standalone/secondary.h
index cccbeb239daea..063640106abb3 100644
--- a/compiler-rt/lib/scudo/standalone/secondary.h
+++ b/compiler-rt/lib/scudo/standalone/secondary.h
@@ -245,7 +245,7 @@ template <typename Config> class MapAllocatorCache {
   atomic_s32 ReleaseToOsIntervalMs;
 };
 
-template <class CacheT> class MapAllocator {
+template <typename Config> class MapAllocator {
 public:
   void initLinkerInitialized(GlobalStats *S, s32 ReleaseToOsInterval = -1) {
     Cache.initLinkerInitialized(ReleaseToOsInterval);
@@ -295,7 +295,7 @@ template <class CacheT> class MapAllocator {
   void releaseToOS() { Cache.releaseToOS(); }
 
 private:
-  CacheT Cache;
+  typename Config::SecondaryCache Cache;
 
   HybridMutex Mutex;
   DoublyLinkedList<LargeBlock::Header> InUseBlocks;
@@ -318,8 +318,8 @@ template <class CacheT> class MapAllocator {
 // For allocations requested with an alignment greater than or equal to a page,
 // the committed memory will amount to something close to Size - AlignmentHint
 // (pending rounding and headers).
-template <class CacheT>
-void *MapAllocator<CacheT>::allocate(uptr Size, uptr AlignmentHint,
+template <typename Config>
+void *MapAllocator<Config>::allocate(uptr Size, uptr AlignmentHint,
                                      uptr *BlockEnd,
                                      FillContentsMode FillContents) {
   DCHECK_GE(Size, AlignmentHint);
@@ -410,7 +410,7 @@ void *MapAllocator<CacheT>::allocate(uptr Size, uptr AlignmentHint,
   return reinterpret_cast<void *>(Ptr + LargeBlock::getHeaderSize());
 }
 
-template <class CacheT> void MapAllocator<CacheT>::deallocate(void *Ptr) {
+template <typename Config> void MapAllocator<Config>::deallocate(void *Ptr) {
   LargeBlock::Header *H = LargeBlock::getHeader(Ptr);
   const uptr Block = reinterpret_cast<uptr>(H);
   const uptr CommitSize = H->BlockEnd - Block;
@@ -430,8 +430,8 @@ template <class CacheT> void MapAllocator<CacheT>::deallocate(void *Ptr) {
   unmap(Addr, Size, UNMAP_ALL, &Data);
 }
 
-template <class CacheT>
-void MapAllocator<CacheT>::getStats(ScopedString *Str) const {
+template <typename Config>
+void MapAllocator<Config>::getStats(ScopedString *Str) const {
   Str->append(
       "Stats: MapAllocator: allocated %zu times (%zuK), freed %zu times "
       "(%zuK), remains %zu (%zuK) max %zuM\n",
diff --git a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
index b0ab0244e877f..7bb6725d3a520 100644
--- a/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
+++ b/compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
@@ -47,7 +47,7 @@ bool isPrimaryAllocation(scudo::uptr Size, scudo::uptr Alignment) {
 template <class AllocatorT>
 bool isTaggedAllocation(AllocatorT *Allocator, scudo::uptr Size,
                         scudo::uptr Alignment) {
-  return Allocator->useMemoryTagging() &&
+  return Allocator->useMemoryTaggingTestOnly() &&
          scudo::systemDetectsMemoryTagFaultsTestOnly() &&
          isPrimaryAllocation<AllocatorT>(Size, Alignment);
 }
@@ -162,7 +162,7 @@ template <class Config> static void testAllocator() {
       for (scudo::uptr I = 0; I < Size; I++) {
         unsigned char V = (reinterpret_cast<unsigned char *>(P))[I];
         if (isPrimaryAllocation<AllocatorT>(Size, 1U << MinAlignLog) &&
-            !Allocator->useMemoryTagging())
+            !Allocator->useMemoryTaggingTestOnly())
           ASSERT_EQ(V, scudo::PatternFillByte);
         else
           ASSERT_TRUE(V == scudo::PatternFillByte || V == 0);
@@ -248,7 +248,7 @@ template <class Config> static void testAllocator() {
 
   Allocator->releaseToOS();
 
-  if (Allocator->useMemoryTagging() &&
+  if (Allocator->useMemoryTaggingTestOnly() &&
       scudo::systemDetectsMemoryTagFaultsTestOnly()) {
     // Check that use-after-free is detected.
     for (scudo::uptr SizeLog = 0U; SizeLog <= 20U; SizeLog++) {
@@ -401,10 +401,15 @@ struct DeathSizeClassConfig {
 
 static const scudo::uptr DeathRegionSizeLog = 20U;
 struct DeathConfig {
+  static const bool MaySupportMemoryTagging = false;
+
   // Tiny allocator, its Primary only serves chunks of four sizes.
-  using DeathSizeClassMap = scudo::FixedSizeClassMap<DeathSizeClassConfig>;
-  typedef scudo::SizeClassAllocator64<DeathSizeClassMap, DeathRegionSizeLog>
-      Primary;
+  using SizeClassMap = scudo::FixedSizeClassMap<DeathSizeClassConfig>;
+  typedef scudo::SizeClassAllocator64<DeathConfig> Primary;
+  static const scudo::uptr PrimaryRegionSizeLog = DeathRegionSizeLog;
+  static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN;
+  static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX;
+
   typedef scudo::MapAllocatorNoCache SecondaryCache;
   template <class A> using TSDRegistryT = scudo::TSDRegistrySharedT<A, 1U, 1U>;
 };
@@ -460,13 +465,13 @@ TEST(ScudoCombinedTest, FullRegion) {
   std::vector<void *> V;
   scudo::uptr FailedAllocationsCount = 0;
   for (scudo::uptr ClassId = 1U;
-       ClassId <= DeathConfig::DeathSizeClassMap::LargestClassId; ClassId++) {
+       ClassId <= DeathConfig::SizeClassMap::LargestClassId; ClassId++) {
     const scudo::uptr Size =
-        DeathConfig::DeathSizeClassMap::getSizeByClassId(ClassId);
+        DeathConfig::SizeClassMap::getSizeByClassId(ClassId);
     // Allocate enough to fill all of the regions above this one.
     const scudo::uptr MaxNumberOfChunks =
         ((1U << DeathRegionSizeLog) / Size) *
-        (DeathConfig::DeathSizeClassMap::LargestClassId - ClassId + 1);
+        (DeathConfig::SizeClassMap::LargestClassId - ClassId + 1);
     void *P;
     for (scudo::uptr I = 0; I <= MaxNumberOfChunks; I++) {
       P = Allocator->allocate(Size - 64U, Origin);
@@ -488,7 +493,7 @@ TEST(ScudoCombinedTest, OddEven) {
   using SizeClassMap = AllocatorT::PrimaryT::SizeClassMap;
   auto Allocator = std::unique_ptr<AllocatorT>(new AllocatorT());
 
-  if (!Allocator->useMemoryTagging())
+  if (!Allocator->useMemoryTaggingTestOnly())
     return;
 
   auto CheckOddEven = [](scudo::uptr P1, scudo::uptr P2) {
diff --git a/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp b/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
index 67d1fe52acef9..eed64314cc3d0 100644
--- a/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
+++ b/compiler-rt/lib/scudo/standalone/tests/primary_test.cpp
@@ -52,20 +52,51 @@ template <typename Primary> static void testPrimary() {
   Str.output();
 }
 
+template <typename SizeClassMapT> struct TestConfig1 {
+  using SizeClassMap = SizeClassMapT;
+  static const scudo::uptr PrimaryRegionSizeLog = 18U;
+  static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN;
+  static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX;
+  static const bool MaySupportMemoryTagging = false;
+};
+
+template <typename SizeClassMapT> struct TestConfig2 {
+  using SizeClassMap = SizeClassMapT;
+  static const scudo::uptr PrimaryRegionSizeLog = 24U;
+  static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN;
+  static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX;
+  static const bool MaySupportMemoryTagging = false;
+};
+
+template <typename SizeClassMapT> struct TestConfig3 {
+  using SizeClassMap = SizeClassMapT;
+  static const scudo::uptr PrimaryRegionSizeLog = 24U;
+  static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN;
+  static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX;
+  static const bool MaySupportMemoryTagging = true;
+};
+
 TEST(ScudoPrimaryTest, BasicPrimary) {
   using SizeClassMap = scudo::DefaultSizeClassMap;
 #if !SCUDO_FUCHSIA
-  testPrimary<scudo::SizeClassAllocator32<SizeClassMap, 18U>>();
+  testPrimary<scudo::SizeClassAllocator32<TestConfig1<SizeClassMap>>>();
 #endif
-  testPrimary<scudo::SizeClassAllocator64<SizeClassMap, 24U>>();
-  testPrimary<scudo::SizeClassAllocator64<SizeClassMap, 24U, INT32_MIN,
-                                          INT32_MAX, true>>();
+  testPrimary<scudo::SizeClassAllocator64<TestConfig2<SizeClassMap>>>();
+  testPrimary<scudo::SizeClassAllocator64<TestConfig3<SizeClassMap>>>();
 }
 
+struct SmallRegionsConfig {
+  using SizeClassMap = scudo::DefaultSizeClassMap;
+  static const scudo::uptr PrimaryRegionSizeLog = 20U;
+  static const scudo::s32 PrimaryMinReleaseToOsIntervalMs = INT32_MIN;
+  static const scudo::s32 PrimaryMaxReleaseToOsIntervalMs = INT32_MAX;
+  static const bool MaySupportMemoryTagging = false;
+};
+
 // The 64-bit SizeClassAllocator can be easily OOM'd with small region sizes.
 // For the 32-bit one, it requires actually exhausting memory, so we skip it.
 TEST(ScudoPrimaryTest, Primary64OOM) {
-  using Primary = scudo::SizeClassAllocator64<scudo::DefaultSizeClassMap, 20U>;
+  using Primary = scudo::SizeClassAllocator64<SmallRegionsConfig>;
   using TransferBatch = Primary::CacheT::TransferBatch;
   Primary Allocator;
   Allocator.init(/*ReleaseToOsInterval=*/-1);
@@ -142,11 +173,10 @@ template <typename Primary> static void testIteratePrimary() {
 TEST(ScudoPrimaryTest, PrimaryIterate) {
   using SizeClassMap = scudo::DefaultSizeClassMap;
 #if !SCUDO_FUCHSIA
-  testIteratePrimary<scudo::SizeClassAllocator32<SizeClassMap, 18U>>();
+  testIteratePrimary<scudo::SizeClassAllocator32<TestConfig1<SizeClassMap>>>();
 #endif
-  testIteratePrimary<scudo::SizeClassAllocator64<SizeClassMap, 24U>>();
-  testIteratePrimary<scudo::SizeClassAllocator64<SizeClassMap, 24U, INT32_MIN,
-                                                 INT32_MAX, true>>();
+  testIteratePrimary<scudo::SizeClassAllocator64<TestConfig2<SizeClassMap>>>();
+  testIteratePrimary<scudo::SizeClassAllocator64<TestConfig3<SizeClassMap>>>();
 }
 
 static std::mutex Mutex;
@@ -204,11 +234,10 @@ template <typename Primary> static void testPrimaryThreaded() {
 TEST(ScudoPrimaryTest, PrimaryThreaded) {
   using SizeClassMap = scudo::SvelteSizeClassMap;
 #if !SCUDO_FUCHSIA
-  testPrimaryThreaded<scudo::SizeClassAllocator32<SizeClassMap, 18U>>();
+  testPrimaryThreaded<scudo::SizeClassAllocator32<TestConfig1<SizeClassMap>>>();
 #endif
-  testPrimaryThreaded<scudo::SizeClassAllocator64<SizeClassMap, 24U>>();
-  testPrimaryThreaded<scudo::SizeClassAllocator64<SizeClassMap, 24U, INT32_MIN,
-                                                  INT32_MAX, true>>();
+  testPrimaryThreaded<scudo::SizeClassAllocator64<TestConfig2<SizeClassMap>>>();
+  testPrimaryThreaded<scudo::SizeClassAllocator64<TestConfig3<SizeClassMap>>>();
 }
 
 // Through a simple allocation that spans two pages, verify that releaseToOS
@@ -236,9 +265,8 @@ template <typename Primary> static void testReleaseToOS() {
 TEST(ScudoPrimaryTest, ReleaseToOS) {
   using SizeClassMap = scudo::DefaultSizeClassMap;
 #if !SCUDO_FUCHSIA
-  testReleaseToOS<scudo::SizeClassAllocator32<SizeClassMap, 18U>>();
+  testReleaseToOS<scudo::SizeClassAllocator32<TestConfig1<SizeClassMap>>>();
 #endif
-  testReleaseToOS<scudo::SizeClassAllocator64<SizeClassMap, 24U>>();
-  testReleaseToOS<scudo::SizeClassAllocator64<SizeClassMap, 24U, INT32_MIN,
-                                              INT32_MAX, true>>();
+  testReleaseToOS<scudo::SizeClassAllocator64<TestConfig2<SizeClassMap>>>();
+  testReleaseToOS<scudo::SizeClassAllocator64<TestConfig3<SizeClassMap>>>();
 }
diff --git a/compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp b/compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
index 3c1e77987ec46..846ec8f6d6faa 100644
--- a/compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
+++ b/compiler-rt/lib/scudo/standalone/tests/secondary_test.cpp
@@ -19,7 +19,9 @@
 #include <thread>
 #include <vector>
 
-template <class SecondaryT> static void testSecondaryBasic(void) {
+template <typename Config> static void testSecondaryBasic(void) {
+  using SecondaryT = scudo::MapAllocator<Config>;
+
   scudo::GlobalStats S;
   S.init();
   std::unique_ptr<SecondaryT> L(new SecondaryT);
@@ -55,7 +57,12 @@ template <class SecondaryT> static void testSecondaryBasic(void) {
   Str.output();
 }
 
+struct NoCacheConfig {
+  typedef scudo::MapAllocatorNoCache SecondaryCache;
+};
+
 struct TestConfig {
+  typedef scudo::MapAllocatorCache<TestConfig> SecondaryCache;
   static const scudo::u32 SecondaryCacheEntriesArraySize = 128U;
   static const scudo::u32 SecondaryCacheDefaultMaxEntriesCount = 64U;
   static const scudo::uptr SecondaryCacheDefaultMaxEntrySize = 1UL << 20;
@@ -64,15 +71,12 @@ struct TestConfig {
 };
 
 TEST(ScudoSecondaryTest, SecondaryBasic) {
-  testSecondaryBasic<scudo::MapAllocator<scudo::MapAllocatorNoCache>>();
-  testSecondaryBasic<
-      scudo::MapAllocator<scudo::MapAllocatorCache<scudo::DefaultConfig>>>();
-  testSecondaryBasic<
-      scudo::MapAllocator<scudo::MapAllocatorCache<TestConfig>>>();
+  testSecondaryBasic<NoCacheConfig>();
+  testSecondaryBasic<scudo::DefaultConfig>();
+  testSecondaryBasic<TestConfig>();
 }
 
-using LargeAllocator =
-    scudo::MapAllocator<scudo::MapAllocatorCache<scudo::DefaultConfig>>;
+using LargeAllocator = scudo::MapAllocator<scudo::DefaultConfig>;
 
 // This exercises a variety of combinations of size and alignment for the
 // MapAllocator. The size computation done here mimic the ones done by the
diff --git a/compiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp b/compiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp
index 9da47facac276..4774993cdf328 100644
--- a/compiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp
+++ b/compiler-rt/test/asan/TestCases/Posix/unpoison-alternate-stack.cpp
@@ -1,4 +1,3 @@
-// UNSUPPORTED: powerpc64
 // Tests that __asan_handle_no_return properly unpoisons the signal alternate
 // stack.
 
diff --git a/compiler-rt/test/asan/TestCases/longjmp.cpp b/compiler-rt/test/asan/TestCases/longjmp.cpp
index bc4165ffd8139..8e9f2ae195c71 100644
--- a/compiler-rt/test/asan/TestCases/longjmp.cpp
+++ b/compiler-rt/test/asan/TestCases/longjmp.cpp
@@ -1,4 +1,3 @@
-// UNSUPPORTED: powerpc64
 // RUN: %clangxx_asan -O %s -o %t && %run %t
 
 #include <assert.h>
diff --git a/compiler-rt/test/builtins/Unit/atomic_test.c b/compiler-rt/test/builtins/Unit/atomic_test.c
index 955c08769e089..7c00841e2c0ba 100644
--- a/compiler-rt/test/builtins/Unit/atomic_test.c
+++ b/compiler-rt/test/builtins/Unit/atomic_test.c
@@ -24,9 +24,13 @@
 // should avoid confounding factors, ensuring that we actually test the
 // functions themselves, regardless of how the builtins are lowered. We need to
 // use asm labels because we can't redeclare the builtins.
+// Note: we need to prepend an underscore to this name for e.g. macOS.
+#define _STRINGIFY(x) #x
+#define STRINGIFY(x) _STRINGIFY(x)
+#define EXTERNAL_NAME(name) asm(STRINGIFY(__USER_LABEL_PREFIX__) #name)
 
-void __atomic_load_c(int size, const void *src, void *dest,
-                     int model) asm("__atomic_load");
+void __atomic_load_c(int size, void *src, void *dest,
+                     int model) EXTERNAL_NAME(__atomic_load);
 
 uint8_t __atomic_load_1(uint8_t *src, int model);
 uint16_t __atomic_load_2(uint16_t *src, int model);
@@ -34,7 +38,7 @@ uint32_t __atomic_load_4(uint32_t *src, int model);
 uint64_t __atomic_load_8(uint64_t *src, int model);
 
 void __atomic_store_c(int size, void *dest, const void *src,
-                      int model) asm("__atomic_store");
+                      int model) EXTERNAL_NAME(__atomic_store);
 
 void __atomic_store_1(uint8_t *dest, uint8_t val, int model);
 void __atomic_store_2(uint16_t *dest, uint16_t val, int model);
@@ -42,7 +46,7 @@ void __atomic_store_4(uint32_t *dest, uint32_t val, int model);
 void __atomic_store_8(uint64_t *dest, uint64_t val, int model);
 
 void __atomic_exchange_c(int size, void *ptr, const void *val, void *old,
-                         int model) asm("__atomic_exchange");
+                         int model) EXTERNAL_NAME(__atomic_exchange);
 
 uint8_t __atomic_exchange_1(uint8_t *dest, uint8_t val, int model);
 uint16_t __atomic_exchange_2(uint16_t *dest, uint16_t val, int model);
@@ -51,7 +55,7 @@ uint64_t __atomic_exchange_8(uint64_t *dest, uint64_t val, int model);
 
 int __atomic_compare_exchange_c(int size, void *ptr, void *expected,
                                 const void *desired, int success, int failure)
-                                asm("__atomic_compare_exchange");
+    EXTERNAL_NAME(__atomic_compare_exchange);
 
 bool __atomic_compare_exchange_1(uint8_t *ptr, uint8_t *expected,
                                  uint8_t desired, int success, int failure);
diff --git a/compiler-rt/test/lit.common.cfg.py b/compiler-rt/test/lit.common.cfg.py
index e2de463f85c0e..e487b4d955bfb 100644
--- a/compiler-rt/test/lit.common.cfg.py
+++ b/compiler-rt/test/lit.common.cfg.py
@@ -363,7 +363,7 @@ def get_macos_aligned_version(macos_vers):
   for required in [26, 28, 30]:
     if android_api_level >= required:
       config.available_features.add('android-%s' % required)
-  # FIXME: Replace with appropriate version when availible.  
+  # FIXME: Replace with appropriate version when availible.
   if android_api_level > 30 or (android_api_level == 30 and android_api_codename == 'S'):
     config.available_features.add('android-thread-properties-api')
 
@@ -380,18 +380,18 @@ def get_macos_aligned_version(macos_vers):
 
 if config.host_os == 'Linux':
   # detect whether we are using glibc, and which version
-  # NB: 'ldd' is just one of the tools commonly installed as part of glibc
+  # NB: 'ldd' is just one of the tools commonly installed as part of glibc/musl
   ldd_ver_cmd = subprocess.Popen(['ldd', '--version'],
                                  stdout=subprocess.PIPE,
                                  env={'LANG': 'C'})
   sout, _ = ldd_ver_cmd.communicate()
-  ver_line = sout.splitlines()[0]
-  if not config.android and ver_line.startswith(b"ldd "):
+  ver_lines = sout.splitlines()
+  if not config.android and len(ver_lines) and ver_lines[0].startswith(b"ldd "):
     from distutils.version import LooseVersion
-    ver = LooseVersion(ver_line.split()[-1].decode())
+    ver = LooseVersion(ver_lines[0].split()[-1].decode())
     for required in ["2.27", "2.30"]:
       if ver >= LooseVersion(required):
-        config.available_features.add("glibc-" + required)  
+        config.available_features.add("glibc-" + required)
 
 sancovcc_path = os.path.join(config.llvm_tools_dir, "sancov")
 if os.path.exists(sancovcc_path):
diff --git a/flang/docs/GettingInvolved.md b/flang/docs/GettingInvolved.md
index c8dbbf106fac7..24e2383a895e0 100644
--- a/flang/docs/GettingInvolved.md
+++ b/flang/docs/GettingInvolved.md
@@ -45,9 +45,11 @@ To understand the status of various developments in Flang please join the respec
 ### Flang Community Biweekly Call
 
 -   General updates on the Flang Project, both LLVM Flang and current Flang.
--   Join [Flang Community Biweekly Call](https://nvmeet.webex.com/nvmeet/j.php?MTID=mb4edb8c799f69ec2dc0554acc969a162)
+-   Join [Flang Community Biweekly Call](https://lanl-us.webex.com/lanl-us/j.php?MTID=m44f29d1fa15eab5cbedc54a5df6c12ae)
 -   Time: On Wednesdays 8:30 Pacific Time, on the weeks alternating with regular Flang Community Technical Biweekly Call.
--   Minutes: They are sent to [flang-dev](http://lists.llvm.org/mailman/listinfo/flang-dev). Search for `Flang Biweekly Sync - Notes`.
+-   Meeting minutes are available in this [Google Doc](https://docs.google.com/document/d/10T-S2J3GrahpG4Ooif93NSTz2zBW0MQc_RlwHi0-afY/edit?usp=sharing).
+    If you can not access the Google Doc, please send an email to Alexis Perry-Holby at aperry@lanl.gov requesting to be added to the access list.
+-   Minutes from older meetings were sent to [flang-dev](http://lists.llvm.org/mailman/listinfo/flang-dev). Search for `Flang Biweekly Sync - Notes`.
 
 ### Flang Community Technical Biweekly Call
 
diff --git a/flang/include/flang/Parser/dump-parse-tree.h b/flang/include/flang/Parser/dump-parse-tree.h
index 7e2d713c127fe..60e00002a2df2 100644
--- a/flang/include/flang/Parser/dump-parse-tree.h
+++ b/flang/include/flang/Parser/dump-parse-tree.h
@@ -68,7 +68,11 @@ class ParseTreeDumper {
 #include "llvm/Frontend/OpenACC/ACC.cpp.inc"
   NODE(parser, AccBindClause)
   NODE(parser, AccDefaultClause)
-  NODE_ENUM(parser::AccDefaultClause, Arg)
+  static std::string GetNodeName(const llvm::acc::DefaultValue &x) {
+    return llvm::Twine(
+        "llvm::acc::DefaultValue = ", llvm::acc::getOpenACCDefaultValueName(x))
+        .str();
+  }
   NODE(parser, AccClauseList)
   NODE(parser, AccCombinedDirective)
   NODE(parser, AccDataModifier)
@@ -481,7 +485,6 @@ class ParseTreeDumper {
   NODE_ENUM(OmpDependenceType, Type)
   NODE(parser, OmpDependSinkVec)
   NODE(parser, OmpDependSinkVecLength)
-  NODE(parser, OmpDistScheduleClause)
   NODE(parser, OmpEndAtomic)
   NODE(parser, OmpEndBlockDirective)
   NODE(parser, OmpEndCriticalDirective)
@@ -504,7 +507,6 @@ class ParseTreeDumper {
         "llvm::omp::Clause = ", llvm::omp::getOpenMPClauseName(x))
         .str();
   }
-  NODE(parser, OmpNowait)
   NODE(parser, OmpObject)
   NODE(parser, OmpObjectList)
   NODE(parser, OmpProcBindClause)
diff --git a/flang/include/flang/Parser/parse-tree.h b/flang/include/flang/Parser/parse-tree.h
index b9d88f6c66f8b..7e258b668576e 100644
--- a/flang/include/flang/Parser/parse-tree.h
+++ b/flang/include/flang/Parser/parse-tree.h
@@ -3456,13 +3456,6 @@ struct OmpDependClause {
   std::variant<Source, Sink, InOut> u;
 };
 
-// 2.7.1 nowait-clause -> NOWAIT
-EMPTY_CLASS(OmpNowait);
-
-// dist_schedule clause does not fit in generic clause class for tablegen.
-// Therefore it is declared separatly here.
-WRAPPER_CLASS(OmpDistScheduleClause, std::optional<ScalarIntExpr>);
-
 // OpenMP Clauses
 struct OmpClause {
   UNION_CLASS_BOILERPLATE(OmpClause);
@@ -3859,8 +3852,7 @@ struct AccBindClause {
 };
 
 struct AccDefaultClause {
-  ENUM_CLASS(Arg, None, Present)
-  WRAPPER_CLASS_BOILERPLATE(AccDefaultClause, Arg);
+  WRAPPER_CLASS_BOILERPLATE(AccDefaultClause, llvm::acc::DefaultValue);
   CharBlock source;
 };
 
diff --git a/flang/lib/Lower/OpenMP.cpp b/flang/lib/Lower/OpenMP.cpp
index 97946caa68a07..f765723bb9ae8 100644
--- a/flang/lib/Lower/OpenMP.cpp
+++ b/flang/lib/Lower/OpenMP.cpp
@@ -191,8 +191,9 @@ genOMP(Fortran::lower::AbstractConverter &converter,
     // Handle attribute based clauses.
     for (const auto &clause : parallelOpClauseList.v) {
       if (const auto &defaultClause =
-              std::get_if<Fortran::parser::OmpDefaultClause>(&clause.u)) {
-        switch (defaultClause->v) {
+              std::get_if<Fortran::parser::OmpClause::Default>(&clause.u)) {
+        const auto &ompDefaultClause{defaultClause->v};
+        switch (ompDefaultClause.v) {
         case Fortran::parser::OmpDefaultClause::Type::Private:
           parallelOp.default_valAttr(firOpBuilder.getStringAttr(
               omp::stringifyClauseDefault(omp::ClauseDefault::defprivate)));
@@ -213,8 +214,9 @@ genOMP(Fortran::lower::AbstractConverter &converter,
         }
       }
       if (const auto &procBindClause =
-              std::get_if<Fortran::parser::OmpProcBindClause>(&clause.u)) {
-        switch (procBindClause->v) {
+              std::get_if<Fortran::parser::OmpClause::ProcBind>(&clause.u)) {
+        const auto &ompProcBindClause{procBindClause->v};
+        switch (ompProcBindClause.v) {
         case Fortran::parser::OmpProcBindClause::Type::Master:
           parallelOp.proc_bind_valAttr(
               firOpBuilder.getStringAttr(omp::stringifyClauseProcBindKind(
diff --git a/flang/lib/Parser/openacc-parsers.cpp b/flang/lib/Parser/openacc-parsers.cpp
index 2447ed70b1a19..26cacc9135c8b 100644
--- a/flang/lib/Parser/openacc-parsers.cpp
+++ b/flang/lib/Parser/openacc-parsers.cpp
@@ -171,9 +171,9 @@ TYPE_PARSER(sourced(construct<AccBindClause>(parenthesized(name))) ||
     sourced(construct<AccBindClause>(parenthesized(scalarDefaultCharExpr))))
 
 // 2.5.14 Default clause
-TYPE_PARSER(construct<AccDefaultClause>(
-    parenthesized(first("NONE" >> pure(AccDefaultClause::Arg::None),
-        "PRESENT" >> pure(AccDefaultClause::Arg::Present)))))
+TYPE_PARSER(construct<AccDefaultClause>(parenthesized(
+    first("NONE" >> pure(llvm::acc::DefaultValue::ACC_Default_none),
+        "PRESENT" >> pure(llvm::acc::DefaultValue::ACC_Default_present)))))
 
 // SELF clause is either a simple optional condition for compute construct
 // or a synonym of the HOST clause for the update directive 2.14.4 holding
diff --git a/flang/lib/Parser/openmp-parsers.cpp b/flang/lib/Parser/openmp-parsers.cpp
index 67c377e798cae..1386b2b16a788 100644
--- a/flang/lib/Parser/openmp-parsers.cpp
+++ b/flang/lib/Parser/openmp-parsers.cpp
@@ -157,8 +157,8 @@ TYPE_PARSER(
     "ACQ_REL" >> construct<OmpClause>(construct<OmpClause::AcqRel>()) ||
     "ALIGNED" >>
         construct<OmpClause>(parenthesized(Parser<OmpAlignedClause>{})) ||
-    "ALLOCATE" >>
-        construct<OmpClause>(parenthesized(Parser<OmpAllocateClause>{})) ||
+    "ALLOCATE" >> construct<OmpClause>(construct<OmpClause::Allocate>(
+                      parenthesized(Parser<OmpAllocateClause>{}))) ||
     "ALLOCATOR" >> construct<OmpClause>(construct<OmpClause::Allocator>(
                        parenthesized(scalarIntExpr))) ||
     "COLLAPSE" >> construct<OmpClause>(construct<OmpClause::Collapse>(
@@ -167,8 +167,8 @@ TYPE_PARSER(
                     parenthesized(Parser<OmpObjectList>{}))) ||
     "COPYPRIVATE" >> construct<OmpClause>(construct<OmpClause::Copyprivate>(
                          (parenthesized(Parser<OmpObjectList>{})))) ||
-    "DEFAULT"_id >>
-        construct<OmpClause>(parenthesized(Parser<OmpDefaultClause>{})) ||
+    "DEFAULT"_id >> construct<OmpClause>(construct<OmpClause::Default>(
+                        parenthesized(Parser<OmpDefaultClause>{}))) ||
     "DEFAULTMAP" >>
         construct<OmpClause>(parenthesized(Parser<OmpDefaultmapClause>{})) ||
     "DEPEND" >>
@@ -176,7 +176,7 @@ TYPE_PARSER(
     "DEVICE" >> construct<OmpClause>(construct<OmpClause::Device>(
                     parenthesized(scalarIntExpr))) ||
     "DIST_SCHEDULE" >>
-        construct<OmpClause>(construct<OmpDistScheduleClause>(
+        construct<OmpClause>(construct<OmpClause::DistSchedule>(
             parenthesized("STATIC" >> maybe("," >> scalarIntExpr)))) ||
     "FINAL" >> construct<OmpClause>(construct<OmpClause::Final>(
                    parenthesized(scalarLogicalExpr))) ||
@@ -203,7 +203,7 @@ TYPE_PARSER(
     "NOGROUP" >> construct<OmpClause>(construct<OmpClause::Nogroup>()) ||
     "NOTINBRANCH" >>
         construct<OmpClause>(construct<OmpClause::Notinbranch>()) ||
-    "NOWAIT" >> construct<OmpClause>(construct<OmpNowait>()) ||
+    "NOWAIT" >> construct<OmpClause>(construct<OmpClause::Nowait>()) ||
     "NUM_TASKS" >> construct<OmpClause>(construct<OmpClause::NumTasks>(
                        parenthesized(scalarIntExpr))) ||
     "NUM_TEAMS" >> construct<OmpClause>(construct<OmpClause::NumTeams>(
@@ -216,8 +216,8 @@ TYPE_PARSER(
                       parenthesized(scalarIntExpr))) ||
     "PRIVATE" >> construct<OmpClause>(construct<OmpClause::Private>(
                      parenthesized(Parser<OmpObjectList>{}))) ||
-    "PROC_BIND" >>
-        construct<OmpClause>(parenthesized(Parser<OmpProcBindClause>{})) ||
+    "PROC_BIND" >> construct<OmpClause>(construct<OmpClause::ProcBind>(
+                       parenthesized(Parser<OmpProcBindClause>{}))) ||
     "REDUCTION" >>
         construct<OmpClause>(parenthesized(Parser<OmpReductionClause>{})) ||
     "RELAXED" >> construct<OmpClause>(construct<OmpClause::Relaxed>()) ||
diff --git a/flang/lib/Parser/unparse.cpp b/flang/lib/Parser/unparse.cpp
index b42b09ae723b0..fdb694f3d26f5 100644
--- a/flang/lib/Parser/unparse.cpp
+++ b/flang/lib/Parser/unparse.cpp
@@ -1850,10 +1850,10 @@ class UnparseVisitor {
   }
   void Unparse(const AccDefaultClause &x) {
     switch (x.v) {
-    case AccDefaultClause::Arg::None:
+    case llvm::acc::DefaultValue::ACC_Default_none:
       Put("NONE");
       break;
-    case AccDefaultClause::Arg::Present:
+    case llvm::acc::DefaultValue::ACC_Default_present:
       Put("PRESENT");
       break;
     }
@@ -2020,10 +2020,9 @@ class UnparseVisitor {
     Put(")");
   }
   void Unparse(const OmpAllocateClause &x) {
-    Word("ALLOCATE(");
-    Walk(std::get<std::optional<OmpAllocateClause::Allocator>>(x.t), ":");
+    Walk(std::get<std::optional<OmpAllocateClause::Allocator>>(x.t));
+    Put(":");
     Walk(std::get<OmpObjectList>(x.t));
-    Put(")");
   }
   void Unparse(const OmpDependSinkVecLength &x) {
     Walk(std::get<DefinedOperator>(x.t));
@@ -2059,16 +2058,6 @@ class UnparseVisitor {
                       },
         x.u);
   }
-  bool Pre(const OmpDefaultClause &) {
-    Word("DEFAULT(");
-    return true;
-  }
-  void Post(const OmpDefaultClause &) { Put(")"); }
-  bool Pre(const OmpProcBindClause &) {
-    Word("PROC_BIND(");
-    return true;
-  }
-  void Post(const OmpProcBindClause &) { Put(")"); }
   void Unparse(const OmpDefaultmapClause &x) {
     Word("DEFAULTMAP(");
     Walk(std::get<OmpDefaultmapClause::ImplicitBehavior>(x.t));
@@ -2076,12 +2065,6 @@ class UnparseVisitor {
         std::get<std::optional<OmpDefaultmapClause::VariableCategory>>(x.t));
     Word(")");
   }
-  void Unparse(const OmpNowait &) { Word("NOWAIT"); }
-  void Unparse(const OmpDistScheduleClause &x) {
-    Word("DIST_SCHEDULE(STATIC");
-    Walk(", ", x.v);
-    Put(")");
-  }
 #define GEN_FLANG_CLAUSE_UNPARSE
 #include "llvm/Frontend/OpenMP/OMP.inc"
   void Unparse(const OmpLoopDirective &x) {
diff --git a/flang/lib/Semantics/check-omp-structure.cpp b/flang/lib/Semantics/check-omp-structure.cpp
index 978e1c7962a49..e2c8333ce7ee4 100644
--- a/flang/lib/Semantics/check-omp-structure.cpp
+++ b/flang/lib/Semantics/check-omp-structure.cpp
@@ -403,8 +403,10 @@ void OmpStructureChecker::Enter(const parser::OmpClause &x) {
 
 // Following clauses do not have a seperate node in parse-tree.h.
 // They fall under 'struct OmpClause' in parse-tree.h.
+CHECK_SIMPLE_CLAUSE(Allocate, OMPC_allocate)
 CHECK_SIMPLE_CLAUSE(Copyin, OMPC_copyin)
 CHECK_SIMPLE_CLAUSE(Copyprivate, OMPC_copyprivate)
+CHECK_SIMPLE_CLAUSE(Default, OMPC_default)
 CHECK_SIMPLE_CLAUSE(Device, OMPC_device)
 CHECK_SIMPLE_CLAUSE(Final, OMPC_final)
 CHECK_SIMPLE_CLAUSE(Firstprivate, OMPC_firstprivate)
@@ -416,6 +418,7 @@ CHECK_SIMPLE_CLAUSE(Link, OMPC_link)
 CHECK_SIMPLE_CLAUSE(Mergeable, OMPC_mergeable)
 CHECK_SIMPLE_CLAUSE(Nogroup, OMPC_nogroup)
 CHECK_SIMPLE_CLAUSE(Notinbranch, OMPC_notinbranch)
+CHECK_SIMPLE_CLAUSE(Nowait, OMPC_nowait)
 CHECK_SIMPLE_CLAUSE(To, OMPC_to)
 CHECK_SIMPLE_CLAUSE(Uniform, OMPC_uniform)
 CHECK_SIMPLE_CLAUSE(Untied, OMPC_untied)
@@ -426,6 +429,8 @@ CHECK_SIMPLE_CLAUSE(SeqCst, OMPC_seq_cst)
 CHECK_SIMPLE_CLAUSE(Release, OMPC_release)
 CHECK_SIMPLE_CLAUSE(Relaxed, OMPC_relaxed)
 CHECK_SIMPLE_CLAUSE(Hint, OMPC_hint)
+CHECK_SIMPLE_CLAUSE(ProcBind, OMPC_proc_bind)
+CHECK_SIMPLE_CLAUSE(DistSchedule, OMPC_dist_schedule)
 
 CHECK_REQ_SCALAR_INT_CLAUSE(Allocator, OMPC_allocator)
 CHECK_REQ_SCALAR_INT_CLAUSE(Grainsize, OMPC_grainsize)
@@ -489,11 +494,6 @@ void OmpStructureChecker::CheckIsVarPartOfAnotherVar(
   }
 }
 // Following clauses have a seperate node in parse-tree.h.
-CHECK_SIMPLE_PARSER_CLAUSE(OmpAllocateClause, OMPC_allocate)
-CHECK_SIMPLE_PARSER_CLAUSE(OmpDefaultClause, OMPC_default)
-CHECK_SIMPLE_PARSER_CLAUSE(OmpDistScheduleClause, OMPC_dist_schedule)
-CHECK_SIMPLE_PARSER_CLAUSE(OmpNowait, OMPC_nowait)
-CHECK_SIMPLE_PARSER_CLAUSE(OmpProcBindClause, OMPC_proc_bind)
 CHECK_SIMPLE_PARSER_CLAUSE(OmpReductionClause, OMPC_reduction)
 // Atomic-clause
 CHECK_SIMPLE_PARSER_CLAUSE(OmpAtomicRead, OMPC_read)
diff --git a/flang/lib/Semantics/check-omp-structure.h b/flang/lib/Semantics/check-omp-structure.h
index 2949568f60447..a966eaf8c4a7d 100644
--- a/flang/lib/Semantics/check-omp-structure.h
+++ b/flang/lib/Semantics/check-omp-structure.h
@@ -126,17 +126,20 @@ class OmpStructureChecker
 
   void Leave(const parser::OmpClauseList &);
   void Enter(const parser::OmpClause &);
-  void Enter(const parser::OmpNowait &);
+  void Enter(const parser::OmpClause::Allocate &);
   void Enter(const parser::OmpClause::Allocator &);
   void Enter(const parser::OmpClause::Inbranch &);
   void Enter(const parser::OmpClause::Mergeable &);
   void Enter(const parser::OmpClause::Nogroup &);
+  void Enter(const parser::OmpClause::Nowait &);
   void Enter(const parser::OmpClause::Notinbranch &);
   void Enter(const parser::OmpClause::Untied &);
   void Enter(const parser::OmpClause::Collapse &);
   void Enter(const parser::OmpClause::Copyin &);
   void Enter(const parser::OmpClause::Copyprivate &);
+  void Enter(const parser::OmpClause::Default &);
   void Enter(const parser::OmpClause::Device &);
+  void Enter(const parser::OmpClause::DistSchedule &);
   void Enter(const parser::OmpClause::Final &);
   void Enter(const parser::OmpClause::Firstprivate &);
   void Enter(const parser::OmpClause::From &);
@@ -148,6 +151,7 @@ class OmpStructureChecker
   void Enter(const parser::OmpClause::Ordered &);
   void Enter(const parser::OmpClause::Priority &);
   void Enter(const parser::OmpClause::Private &);
+  void Enter(const parser::OmpClause::ProcBind &);
   void Enter(const parser::OmpClause::Safelen &);
   void Enter(const parser::OmpClause::Shared &);
   void Enter(const parser::OmpClause::Simdlen &);
@@ -174,15 +178,11 @@ class OmpStructureChecker
   void Enter(const parser::OmpAtomicCapture &);
   void Leave(const parser::OmpAtomic &);
   void Enter(const parser::OmpAlignedClause &);
-  void Enter(const parser::OmpAllocateClause &);
-  void Enter(const parser::OmpDefaultClause &);
   void Enter(const parser::OmpDefaultmapClause &);
   void Enter(const parser::OmpDependClause &);
-  void Enter(const parser::OmpDistScheduleClause &);
   void Enter(const parser::OmpIfClause &);
   void Enter(const parser::OmpLinearClause &);
   void Enter(const parser::OmpMapClause &);
-  void Enter(const parser::OmpProcBindClause &);
   void Enter(const parser::OmpReductionClause &);
   void Enter(const parser::OmpScheduleClause &);
 
diff --git a/flang/lib/Semantics/mod-file.cpp b/flang/lib/Semantics/mod-file.cpp
index 99ea65b753a6a..f8e5889e46986 100644
--- a/flang/lib/Semantics/mod-file.cpp
+++ b/flang/lib/Semantics/mod-file.cpp
@@ -319,6 +319,10 @@ void ModFileWriter::PutSubprogram(const Symbol &symbol) {
     bindAttrs.set(Attr::BIND_C, true);
     attrs.set(Attr::BIND_C, false);
   }
+  bool isAbstract{attrs.test(Attr::ABSTRACT)};
+  if (isAbstract) {
+    attrs.set(Attr::ABSTRACT, false);
+  }
   Attrs prefixAttrs{subprogramPrefixAttrs & attrs};
   // emit any non-prefix attributes in an attribute statement
   attrs &= ~subprogramPrefixAttrs;
@@ -331,7 +335,7 @@ void ModFileWriter::PutSubprogram(const Symbol &symbol) {
   bool isInterface{details.isInterface()};
   llvm::raw_ostream &os{isInterface ? decls_ : contains_};
   if (isInterface) {
-    os << "interface\n";
+    os << (isAbstract ? "abstract " : "") << "interface\n";
   }
   PutAttrs(os, prefixAttrs, std::nullopt, ""s, " "s);
   os << (details.isFunction() ? "function " : "subroutine ");
@@ -457,6 +461,11 @@ void CollectSymbols(
       }
     }
   }
+  // Sort most symbols by name: use of Symbol::ReplaceName ensures the source
+  // location of a symbol's name is the first "real" use.
+  std::sort(sorted.begin(), sorted.end(), [](SymbolRef x, SymbolRef y) {
+    return x->name().begin() < y->name().begin();
+  });
   sorted.insert(sorted.end(), namelist.begin(), namelist.end());
   for (const auto &pair : scope.commonBlocks()) {
     sorted.push_back(*pair.second);
diff --git a/flang/lib/Semantics/resolve-directives.cpp b/flang/lib/Semantics/resolve-directives.cpp
index 7ca42bac569af..e10d797d0308b 100644
--- a/flang/lib/Semantics/resolve-directives.cpp
+++ b/flang/lib/Semantics/resolve-directives.cpp
@@ -232,6 +232,18 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor<llvm::omp::Directive> {
     return true;
   }
 
+  bool Pre(const parser::StmtFunctionStmt &x) {
+    const auto &parsedExpr{std::get<parser::Scalar<parser::Expr>>(x.t)};
+    if (const auto *expr{GetExpr(parsedExpr)}) {
+      for (const Symbol &symbol : evaluate::CollectSymbols(*expr)) {
+        if (!IsStmtFunctionDummy(symbol)) {
+          stmtFunctionExprSymbols_.insert(symbol.GetUltimate());
+        }
+      }
+    }
+    return true;
+  }
+
   bool Pre(const parser::OpenMPBlockConstruct &);
   void Post(const parser::OpenMPBlockConstruct &);
 
@@ -342,6 +354,7 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor<llvm::omp::Directive> {
 
   std::vector<const parser::Name *> allocateNames_; // on one directive
   SymbolSet privateDataSharingAttributeObjects_; // on one directive
+  SymbolSet stmtFunctionExprSymbols_;
 
   void AddAllocateName(const parser::Name *&object) {
     allocateNames_.push_back(object);
@@ -377,7 +390,7 @@ class OmpAttributeVisitor : DirectiveAttributeVisitor<llvm::omp::Directive> {
       const parser::Name &, const Symbol &, Symbol::Flag);
 
   void CheckAssocLoopLevel(std::int64_t level, const parser::OmpClause *clause);
-  void CheckObjectInNamelist(
+  void CheckPrivateDSAObject(
       const parser::Name &, const Symbol &, Symbol::Flag);
 };
 
@@ -638,10 +651,10 @@ void AccAttributeVisitor::PrivatizeAssociatedLoopIndex(
 void AccAttributeVisitor::Post(const parser::AccDefaultClause &x) {
   if (!dirContext_.empty()) {
     switch (x.v) {
-    case parser::AccDefaultClause::Arg::Present:
+    case llvm::acc::DefaultValue::ACC_Default_present:
       SetContextDefaultDSA(Symbol::Flag::AccPresent);
       break;
-    case parser::AccDefaultClause::Arg::None:
+    case llvm::acc::DefaultValue::ACC_Default_none:
       SetContextDefaultDSA(Symbol::Flag::AccNone);
       break;
     }
@@ -1163,7 +1176,7 @@ void OmpAttributeVisitor::ResolveOmpObject(
                     CheckMultipleAppearances(*name, *symbol, ompFlag);
                   }
                   if (privateDataSharingAttributeFlags.test(ompFlag)) {
-                    CheckObjectInNamelist(*name, *symbol, ompFlag);
+                    CheckPrivateDSAObject(*name, *symbol, ompFlag);
                   }
 
                   if (ompFlag == Symbol::Flag::OmpAllocate) {
@@ -1317,18 +1330,28 @@ void OmpAttributeVisitor::CheckDataCopyingClause(
   }
 }
 
-void OmpAttributeVisitor::CheckObjectInNamelist(
+void OmpAttributeVisitor::CheckPrivateDSAObject(
     const parser::Name &name, const Symbol &symbol, Symbol::Flag ompFlag) {
-  if (symbol.GetUltimate().test(Symbol::Flag::InNamelist)) {
-    llvm::StringRef clauseName{"PRIVATE"};
-    if (ompFlag == Symbol::Flag::OmpFirstPrivate)
-      clauseName = "FIRSTPRIVATE";
-    else if (ompFlag == Symbol::Flag::OmpLastPrivate)
-      clauseName = "LASTPRIVATE";
+  const auto &ultimateSymbol{symbol.GetUltimate()};
+  llvm::StringRef clauseName{"PRIVATE"};
+  if (ompFlag == Symbol::Flag::OmpFirstPrivate)
+    clauseName = "FIRSTPRIVATE";
+  else if (ompFlag == Symbol::Flag::OmpLastPrivate)
+    clauseName = "LASTPRIVATE";
+
+  if (ultimateSymbol.test(Symbol::Flag::InNamelist)) {
     context_.Say(name.source,
         "Variable '%s' in NAMELIST cannot be in a %s clause"_err_en_US,
         name.ToString(), clauseName.str());
   }
+
+  if (stmtFunctionExprSymbols_.find(ultimateSymbol) !=
+      stmtFunctionExprSymbols_.end()) {
+    context_.Say(name.source,
+        "Variable '%s' in STATEMENT FUNCTION expression cannot be in a "
+        "%s clause"_err_en_US,
+        name.ToString(), clauseName.str());
+  }
 }
 
 } // namespace Fortran::semantics
diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp
index 8d5284131cc01..73c624aefa22f 100644
--- a/flang/lib/Semantics/resolve-names.cpp
+++ b/flang/lib/Semantics/resolve-names.cpp
@@ -3085,11 +3085,14 @@ Symbol &SubprogramVisitor::PushSubprogramScope(
     symbol = &MakeSymbol(name, SubprogramDetails{});
   }
   symbol->set(subpFlag);
+  symbol->ReplaceName(name.source);
   PushScope(Scope::Kind::Subprogram, symbol);
   auto &details{symbol->get<SubprogramDetails>()};
   if (inInterfaceBlock()) {
     details.set_isInterface();
-    if (!isAbstract()) {
+    if (isAbstract()) {
+      symbol->attrs().set(Attr::ABSTRACT);
+    } else {
       MakeExternal(*symbol);
     }
     if (isGeneric()) {
diff --git a/flang/test/Frontend/print-preprocessed-file.f90 b/flang/test/Frontend/print-preprocessed-file.f90
index 2ba4a4f957c65..873bb2b3e3700 100644
--- a/flang/test/Frontend/print-preprocessed-file.f90
+++ b/flang/test/Frontend/print-preprocessed-file.f90
@@ -8,15 +8,13 @@
 ! RUN: %flang-new -E %s  2>&1 | FileCheck %s
 
 !-----------------------------------------
-!   FRONTEND FLANG DRIVER (flang-new -fc1)
+! FRONTEND FLANG DRIVER (flang-new -fc1)
 !-----------------------------------------
 ! RUN: %flang-new -fc1 -E %s  2>&1 | FileCheck %s
 
-
 !-----------------------
 ! EXPECTED OUTPUT
 !-----------------------
-! flang-new -E  %s
 ! CHECK:program a
 ! CHECK-NOT:program b
 ! CHECK-NEXT:x = 1
diff --git a/flang/test/Semantics/modfile10.f90 b/flang/test/Semantics/modfile10.f90
index ef10f1f23e8e2..996178f5896db 100644
--- a/flang/test/Semantics/modfile10.f90
+++ b/flang/test/Semantics/modfile10.f90
@@ -90,3 +90,40 @@ subroutine test
 !  subroutine test()
 !  end
 !end
+
+! Ensure the type is emitted before its use
+module m2
+  private s
+  type :: t
+  contains
+    procedure :: foo
+  end type
+  abstract interface
+    subroutine s(x)
+      import
+      type(t) :: x
+    end subroutine
+  end interface
+contains
+  subroutine foo(x)
+    class(t) :: x
+  end subroutine
+end module
+!Expect: m2.mod
+!module m2
+!  type::t
+!  contains
+!    procedure::foo
+!  end type
+!  private::s
+!  abstract interface
+!    subroutine s(x)
+!      import::t
+!      type(t)::x
+!    end
+!  end interface
+!contains
+!  subroutine foo(x)
+!    class(t)::x
+!  end
+!end
diff --git a/flang/test/Semantics/omp-private03.f90 b/flang/test/Semantics/omp-private03.f90
new file mode 100644
index 0000000000000..50748f5508ed4
--- /dev/null
+++ b/flang/test/Semantics/omp-private03.f90
@@ -0,0 +1,39 @@
+! RUN: %S/test_errors.sh %s %t %f18 -fopenmp
+! OpenMP Version 4.5
+! Variables that appear in expressions for statement function definitions
+! may not appear in private, firstprivate or lastprivate clauses.
+
+subroutine stmt_function(temp)
+
+  integer :: i, p, q, r
+  real :: c, f, s, v, t(10)
+  real, intent(in) :: temp
+
+  c(temp) = p * (temp - q) / r
+  f(temp) = q + (temp * r/p)
+  v(temp) = c(temp) + f(temp)/2 - s
+
+  p = 5
+  q = 32
+  r = 9
+
+  !ERROR: Variable 'p' in STATEMENT FUNCTION expression cannot be in a PRIVATE clause
+  !$omp parallel private(p)
+  s = c(temp)
+  !$omp end parallel
+
+  !ERROR: Variable 's' in STATEMENT FUNCTION expression cannot be in a FIRSTPRIVATE clause
+  !$omp parallel firstprivate(s)
+  s = s + f(temp)
+  !$omp end parallel
+
+  !ERROR: Variable 's' in STATEMENT FUNCTION expression cannot be in a LASTPRIVATE clause
+  !$omp parallel do lastprivate(s, t)
+  do i = 1, 10
+    t(i) = v(temp) + i - s
+  end do
+  !$omp end parallel do
+
+  print *, t
+
+end subroutine stmt_function
diff --git a/flang/test/Semantics/procinterface01.f90 b/flang/test/Semantics/procinterface01.f90
index a960922d5637a..dd9fd3b660415 100644
--- a/flang/test/Semantics/procinterface01.f90
+++ b/flang/test/Semantics/procinterface01.f90
@@ -5,7 +5,7 @@
 !DEF: /module1 Module
 module module1
  abstract interface
-  !DEF: /module1/abstract1 PUBLIC (Function) Subprogram REAL(4)
+  !DEF: /module1/abstract1 ABSTRACT, PUBLIC (Function) Subprogram REAL(4)
   !DEF: /module1/abstract1/x INTENT(IN) ObjectEntity REAL(4)
   real function abstract1(x)
    !REF: /module1/abstract1/x
diff --git a/flang/test/Semantics/symbol15.f90 b/flang/test/Semantics/symbol15.f90
index ddd3772252dc5..cc230ff1fc031 100644
--- a/flang/test/Semantics/symbol15.f90
+++ b/flang/test/Semantics/symbol15.f90
@@ -5,7 +5,7 @@
 module m
  implicit none
  abstract interface
-  !DEF: /m/iface PUBLIC (Subroutine) Subprogram
+  !DEF: /m/iface ABSTRACT, PUBLIC (Subroutine) Subprogram
   subroutine iface
   end subroutine
  end interface
diff --git a/flang/unittests/Frontend/FrontendActionTest.cpp b/flang/unittests/Frontend/FrontendActionTest.cpp
index 78161f691effc..fb4de6d307cd8 100644
--- a/flang/unittests/Frontend/FrontendActionTest.cpp
+++ b/flang/unittests/Frontend/FrontendActionTest.cpp
@@ -8,6 +8,7 @@
 
 #include "gtest/gtest.h"
 #include "flang/Frontend/CompilerInstance.h"
+#include "flang/Frontend/CompilerInvocation.h"
 #include "flang/Frontend/FrontendOptions.h"
 #include "flang/FrontendTool/Utils.h"
 #include "llvm/Support/FileSystem.h"
@@ -17,119 +18,120 @@ using namespace Fortran::frontend;
 
 namespace {
 
-TEST(FrontendAction, PrintPreprocessedInput) {
-  std::string inputFile = "test-file.f";
-  std::error_code ec;
+class FrontendActionTest : public ::testing::Test {
+protected:
+  // AllSources (which is used to manage files inside every compiler
+  // instance), works with paths. So we need a filename and a path for the
+  // input file.
+  // TODO: We could use `-` for inputFilePath_, but then we'd need a way to
+  // write to stdin that's then read by AllSources. Ideally, AllSources should
+  // be capable of reading from any stream.
+  std::string inputFileName_;
+  std::string inputFilePath_;
+  // The output stream for the input file. Use this to populate the input.
+  std::unique_ptr<llvm::raw_fd_ostream> inputFileOs_;
+
+  std::error_code ec_;
+
+  CompilerInstance compInst_;
+  std::shared_ptr<CompilerInvocation> invocation_;
+
+  void SetUp() override {
+    // Generate a unique test file name.
+    const testing::TestInfo *const test_info =
+        testing::UnitTest::GetInstance()->current_test_info();
+    inputFileName_ = std::string(test_info->name()) + "_test-file.f";
+
+    // Create the input file stream. Note that this stream is populated
+    // separately in every test (i.e. the input is test specific).
+    inputFileOs_ = std::make_unique<llvm::raw_fd_ostream>(
+        inputFileName_, ec_, llvm::sys::fs::OF_None);
+    if (ec_)
+      FAIL() << "Failed to create the input file";
+
+    // Get the path of the input file.
+    llvm::SmallString<256> cwd;
+    if (std::error_code ec_ = llvm::sys::fs::current_path(cwd))
+      FAIL() << "Failed to obtain the current working directory";
+    inputFilePath_ = cwd.c_str();
+    inputFilePath_ += "/" + inputFileName_;
+
+    // Prepare the compiler (CompilerInvocation + CompilerInstance)
+    compInst_.CreateDiagnostics();
+    invocation_ = std::make_shared<CompilerInvocation>();
+
+    compInst_.set_invocation(std::move(invocation_));
+    compInst_.frontendOpts().inputs_.push_back(
+        FrontendInputFile(inputFilePath_, Language::Fortran));
+  }
+
+  void TearDown() override {
+    // Clear the input file.
+    llvm::sys::fs::remove(inputFileName_);
+
+    // Clear the output files.
+    // Note that these tests use an output buffer (as opposed to an output
+    // file), hence there are no physical output files to delete and
+    // `EraseFiles` is set to `false`. Also, some actions (e.g.
+    // `ParseSyntaxOnly`) don't generated output. In such cases there's no
+    // output to clear and `ClearOutputFile` returns immediately.
+    compInst_.ClearOutputFiles(/*EraseFiles=*/false);
+  }
+};
+
+TEST_F(FrontendActionTest, PrintPreprocessedInput) {
+  // Populate the input file with the pre-defined input and flush it.
+  *(inputFileOs_) << "#ifdef NEW\n"
+                  << "  Program A \n"
+                  << "#else\n"
+                  << "  Program B\n"
+                  << "#endif";
+  inputFileOs_.reset();
 
-  // 1. Create the input file for the file manager
-  // AllSources (which is used to manage files inside every compiler instance),
-  // works with paths. This means that it requires a physical file. Create one.
-  std::unique_ptr<llvm::raw_fd_ostream> os{
-      new llvm::raw_fd_ostream(inputFile, ec, llvm::sys::fs::OF_None)};
-  if (ec)
-    FAIL() << "Fail to create the file need by the test";
+  // Set-up the action kind.
+  compInst_.invocation().frontendOpts().programAction_ = PrintPreprocessedInput;
 
-  // Populate the input file with the pre-defined input and flush it.
-  *(os) << "! test-file.F:\n"
-        << "#ifdef NEW\n"
-        << "  Program A \n"
-        << "#else\n"
-        << "  Program B\n"
-        << "#endif";
-  os.reset();
-
-  // Get the path of the input file
-  llvm::SmallString<64> cwd;
-  if (std::error_code ec = llvm::sys::fs::current_path(cwd))
-    FAIL() << "Failed to obtain the current working directory";
-  std::string testFilePath(cwd.c_str());
-  testFilePath += "/" + inputFile;
-
-  // 2. Prepare the compiler (CompilerInvocation + CompilerInstance)
-  CompilerInstance compInst;
-  compInst.CreateDiagnostics();
-  auto invocation = std::make_shared<CompilerInvocation>();
-  invocation->frontendOpts().programAction_ = PrintPreprocessedInput;
-
-  compInst.set_invocation(std::move(invocation));
-  compInst.frontendOpts().inputs_.push_back(
-      FrontendInputFile(testFilePath, Language::Fortran));
-
-  // 3. Set-up the output stream. Using output buffer wrapped as an output
+  // Set-up the output stream. We are using output buffer wrapped as an output
   // stream, as opposed to an actual file (or a file descriptor).
   llvm::SmallVector<char, 256> outputFileBuffer;
   std::unique_ptr<llvm::raw_pwrite_stream> outputFileStream(
       new llvm::raw_svector_ostream(outputFileBuffer));
-  compInst.set_outputStream(std::move(outputFileStream));
+  compInst_.set_outputStream(std::move(outputFileStream));
 
-  // 4. Run the earlier defined FrontendAction
-  bool success = ExecuteCompilerInvocation(&compInst);
+  // Execute the action.
+  bool success = ExecuteCompilerInvocation(&compInst_);
 
-  // 5. Validate the expected output
+  // Validate the expected output.
   EXPECT_TRUE(success);
   EXPECT_TRUE(!outputFileBuffer.empty());
   EXPECT_TRUE(
       llvm::StringRef(outputFileBuffer.data()).startswith("program b\n"));
-
-  // 6. Clear the input and the output files. Since we used an output buffer,
-  // there are no physical output files to delete.
-  llvm::sys::fs::remove(inputFile);
-  compInst.ClearOutputFiles(/*EraseFiles=*/true);
 }
 
-TEST(FrontendAction, ParseSyntaxOnly) {
-  std::string inputFile = "test-file.f";
-  std::error_code ec;
+TEST_F(FrontendActionTest, ParseSyntaxOnly) {
+  // Populate the input file with the pre-defined input and flush it.
+  *(inputFileOs_) << "IF (A > 0.0) IF (B < 0.0) A = LOG (A)\n"
+                  << "END";
+  inputFileOs_.reset();
 
-  // 1. Create the input file for the file manager
-  // AllSources (which is used to manage files inside every compiler instance),
-  // works with paths. This means that it requires a physical file. Create one.
-  std::unique_ptr<llvm::raw_fd_ostream> os{
-      new llvm::raw_fd_ostream(inputFile, ec, llvm::sys::fs::OF_None)};
-  if (ec)
-    FAIL() << "Fail to create the file need by the test";
+  // Set-up the action kind.
+  compInst_.invocation().frontendOpts().programAction_ = ParseSyntaxOnly;
 
-  // Populate the input file with the pre-defined input and flush it.
-  *(os) << "! if_stmt.f90:\n"
-        << "IF (A > 0.0) IF (B < 0.0) A = LOG (A)\n"
-        << "END";
-  os.reset();
-
-  // Get the path of the input file
-  llvm::SmallString<64> cwd;
-  if (std::error_code ec = llvm::sys::fs::current_path(cwd))
-    FAIL() << "Failed to obtain the current working directory";
-  std::string testFilePath(cwd.c_str());
-  testFilePath += "/" + inputFile;
-
-  // 2. Prepare the compiler (CompilerInvocation + CompilerInstance)
-  CompilerInstance compInst;
-  compInst.CreateDiagnostics();
-  auto invocation = std::make_shared<CompilerInvocation>();
-  invocation->frontendOpts().programAction_ = ParseSyntaxOnly;
-
-  compInst.set_invocation(std::move(invocation));
-  compInst.frontendOpts().inputs_.push_back(
-      FrontendInputFile(testFilePath, Language::Fortran));
-
-  // 3. Set-up the output stream for the semantic diagnostics.
+  // Set-up the output stream for the semantic diagnostics.
   llvm::SmallVector<char, 256> outputDiagBuffer;
   std::unique_ptr<llvm::raw_pwrite_stream> outputStream(
       new llvm::raw_svector_ostream(outputDiagBuffer));
-  compInst.set_semaOutputStream(std::move(outputStream));
+  compInst_.set_semaOutputStream(std::move(outputStream));
 
-  // 4. Execute the ParseSyntaxOnly action
-  bool success = ExecuteCompilerInvocation(&compInst);
+  // Execute the action.
+  bool success = ExecuteCompilerInvocation(&compInst_);
 
-  // 5. Validate the expected output
+  // Validate the expected output.
   EXPECT_FALSE(success);
   EXPECT_TRUE(!outputDiagBuffer.empty());
   EXPECT_TRUE(
       llvm::StringRef(outputDiagBuffer.data())
           .startswith(
-              ":2:14: error: IF statement is not allowed in IF statement\n"));
-
-  // 6. Clear the input files.
-  llvm::sys::fs::remove(inputFile);
+              ":1:14: error: IF statement is not allowed in IF statement\n"));
 }
 } // namespace
diff --git a/libclc/ptx-nvidiacl/libspirv/group/collectives.cl b/libclc/ptx-nvidiacl/libspirv/group/collectives.cl
index fba9ad72d8a52..dcb9dbebfbd8e 100644
--- a/libclc/ptx-nvidiacl/libspirv/group/collectives.cl
+++ b/libclc/ptx-nvidiacl/libspirv/group/collectives.cl
@@ -239,31 +239,28 @@ __CLC_SUBGROUP_COLLECTIVE(FMax, __CLC_MAX, double, -DBL_MAX)
     }                                                                          \
     __spirv_ControlBarrier(Workgroup, 0, 0);                                   \
     /* Perform InclusiveScan over sub-group results */                         \
-    /* FIXME: Ideally, use an alternative algorithm that doesn't require two   \
-     * calls to __syncthreads() */                                             \
-    for (int o = 1; o < num_sg; o *= 2) {                                      \
-      TYPE contribution = IDENTITY;                                            \
-      if (sg_id >= o && sg_lid == 0) {                                         \
-        contribution = scratch[sg_id - o];                                     \
+    TYPE sg_prefix;                                                            \
+    TYPE sg_aggregate = scratch[0];                                            \
+    _Pragma("unroll") for (int s = 1; s < num_sg; ++s) {                       \
+      if (sg_id == s) {                                                        \
+        sg_prefix = sg_aggregate;                                              \
       }                                                                        \
-      __spirv_ControlBarrier(Workgroup, 0, 0);                                 \
-      if (sg_id >= o && sg_lid == 0) {                                         \
-        scratch[sg_id] = OP(scratch[sg_id], contribution);                     \
-      }                                                                        \
-      __spirv_ControlBarrier(Workgroup, 0, 0);                                 \
+      TYPE addend = scratch[s];                                                \
+      sg_aggregate = OP(sg_aggregate, addend);                                 \
     }                                                                          \
     /* For Reduce, broadcast result from final sub-group */                    \
     /* For Scan, combine results from previous sub-groups */                   \
     TYPE result;                                                               \
     if (op == Reduce) {                                                        \
-      result = scratch[num_sg - 1];                                            \
+      result = sg_aggregate;                                                   \
     } else if (op == InclusiveScan || op == ExclusiveScan) {                   \
       if (sg_id == 0) {                                                        \
         result = sg_x;                                                         \
       } else {                                                                 \
-        result = OP(sg_x, scratch[sg_id - 1]);                                 \
+        result = OP(sg_x, sg_prefix);                                          \
       }                                                                        \
     }                                                                          \
+    __spirv_ControlBarrier(Workgroup, 0, 0);                                   \
     return result;                                                             \
   }
 
diff --git a/libcxx/docs/Cxx2aStatusPaperStatus.csv b/libcxx/docs/Cxx2aStatusPaperStatus.csv
index c495e0210cf79..fe5b2f5d47710 100644
--- a/libcxx/docs/Cxx2aStatusPaperStatus.csv
+++ b/libcxx/docs/Cxx2aStatusPaperStatus.csv
@@ -109,7 +109,7 @@
 "`P0980 <https://wg21.link/P0980>`__","LWG","Making std::string constexpr","Cologne","",""
 "`P1004 <https://wg21.link/P1004>`__","LWG","Making std::vector constexpr","Cologne","",""
 "`P1035 <https://wg21.link/P1035>`__","LWG","Input Range Adaptors","Cologne","",""
-"`P1065 <https://wg21.link/P1065>`__","LWG","Constexpr INVOKE","Cologne","",""
+"`P1065 <https://wg21.link/P1065>`__","LWG","Constexpr INVOKE","Cologne","|Complete|","12.0"
 "`P1135 <https://wg21.link/P1135>`__","LWG","The C++20 Synchronization Library","Cologne","|Complete|","11.0"
 "`P1207 <https://wg21.link/P1207>`__","LWG","Movability of Single-pass Iterators","Cologne","",""
 "`P1208 <https://wg21.link/P1208>`__","LWG","Adopt source_location for C++20","Cologne","",""
diff --git a/libcxx/docs/FeatureTestMacroTable.rst b/libcxx/docs/FeatureTestMacroTable.rst
index 091d4b7952332..5930cdaffaec6 100644
--- a/libcxx/docs/FeatureTestMacroTable.rst
+++ b/libcxx/docs/FeatureTestMacroTable.rst
@@ -194,7 +194,7 @@ Status
     ------------------------------------------------- -----------------
     ``__cpp_lib_constexpr_dynamic_alloc``             ``201907L``
     ------------------------------------------------- -----------------
-    ``__cpp_lib_constexpr_misc``                      *unimplemented*
+    ``__cpp_lib_constexpr_functional``                ``201907L``
     ------------------------------------------------- -----------------
     ``__cpp_lib_constexpr_numeric``                   ``201911L``
     ------------------------------------------------- -----------------
diff --git a/libcxx/include/__functional_base b/libcxx/include/__functional_base
index c84e7eb115678..708c1a23e84b4 100644
--- a/libcxx/include/__functional_base
+++ b/libcxx/include/__functional_base
@@ -382,20 +382,23 @@ private:
 
 public:
     // construct/copy/destroy
-    _LIBCPP_INLINE_VISIBILITY reference_wrapper(type& __f) _NOEXCEPT
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
+    reference_wrapper(type& __f) _NOEXCEPT
         : __f_(_VSTD::addressof(__f)) {}
 #ifndef _LIBCPP_CXX03_LANG
     private: reference_wrapper(type&&); public: // = delete; // do not bind to temps
 #endif
 
     // access
-    _LIBCPP_INLINE_VISIBILITY operator type&    () const _NOEXCEPT {return *__f_;}
-    _LIBCPP_INLINE_VISIBILITY          type& get() const _NOEXCEPT {return *__f_;}
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
+    operator type&() const _NOEXCEPT {return *__f_;}
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
+    type& get() const _NOEXCEPT {return *__f_;}
 
 #ifndef _LIBCPP_CXX03_LANG
     // invoke
     template <class... _ArgTypes>
-    _LIBCPP_INLINE_VISIBILITY
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     typename __invoke_of<type&, _ArgTypes...>::type
     operator() (_ArgTypes&&... __args) const {
         return _VSTD::__invoke(get(), _VSTD::forward<_ArgTypes>(__args)...);
@@ -510,7 +513,7 @@ public:
 
 
 template <class _Tp>
-inline _LIBCPP_INLINE_VISIBILITY
+inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
 reference_wrapper<_Tp>
 ref(_Tp& __t) _NOEXCEPT
 {
@@ -518,7 +521,7 @@ ref(_Tp& __t) _NOEXCEPT
 }
 
 template <class _Tp>
-inline _LIBCPP_INLINE_VISIBILITY
+inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
 reference_wrapper<_Tp>
 ref(reference_wrapper<_Tp> __t) _NOEXCEPT
 {
@@ -526,7 +529,7 @@ ref(reference_wrapper<_Tp> __t) _NOEXCEPT
 }
 
 template <class _Tp>
-inline _LIBCPP_INLINE_VISIBILITY
+inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
 reference_wrapper<const _Tp>
 cref(const _Tp& __t) _NOEXCEPT
 {
@@ -534,7 +537,7 @@ cref(const _Tp& __t) _NOEXCEPT
 }
 
 template <class _Tp>
-inline _LIBCPP_INLINE_VISIBILITY
+inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
 reference_wrapper<const _Tp>
 cref(reference_wrapper<_Tp> __t) _NOEXCEPT
 {
diff --git a/libcxx/include/functional b/libcxx/include/functional
index a54868e822203..dbbebaf820176 100644
--- a/libcxx/include/functional
+++ b/libcxx/include/functional
@@ -213,7 +213,8 @@ public:
 template <class Predicate> // deprecated in C++17
 binary_negate<Predicate> not2(const Predicate& pred);
 
-template <class F> unspecified not_fn(F&& f); // C++17
+template <class F>
+constexpr unspecified not_fn(F&& f); // C++17, constexpr in C++20
 
 template<class T> struct is_bind_expression;
 template<class T> struct is_placeholder;
@@ -226,11 +227,12 @@ template <class T> inline constexpr int is_placeholder_v
 
 
 template<class Fn, class... BoundArgs>
-  unspecified bind(Fn&&, BoundArgs&&...);
+  constexpr unspecified bind(Fn&&, BoundArgs&&...);  // constexpr in C++20
 template<class R, class Fn, class... BoundArgs>
-  unspecified bind(Fn&&, BoundArgs&&...);
+  constexpr unspecified bind(Fn&&, BoundArgs&&...);  // constexpr in C++20
 
 template<class F, class... Args>
+ constexpr // constexpr in C++20
  invoke_result_t<F, Args...> invoke(F&& f, Args&&... args) // C++17
     noexcept(is_nothrow_invocable_v<F, Args...>);
 
@@ -376,7 +378,8 @@ public:
 template <class S, class T>          const_mem_fun_ref_t<S,T>    mem_fun_ref(S (T::*f)() const);   // deprecated in C++11, removed in C++17
 template <class S, class T, class A> const_mem_fun1_ref_t<S,T,A> mem_fun_ref(S (T::*f)(A) const);  // deprecated in C++11, removed in C++17
 
-template<class R, class T> unspecified mem_fn(R T::*);
+template<class R, class T>
+constexpr unspecified mem_fn(R T::*); // constexpr in C++20
 
 class bad_function_call
     : public exception
@@ -1288,12 +1291,13 @@ private:
     type __f_;
 
 public:
-    _LIBCPP_INLINE_VISIBILITY __mem_fn(type __f) _NOEXCEPT : __f_(__f) {}
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
+    __mem_fn(type __f) _NOEXCEPT : __f_(__f) {}
 
 #ifndef _LIBCPP_CXX03_LANG
     // invoke
     template <class... _ArgTypes>
-    _LIBCPP_INLINE_VISIBILITY
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     typename __invoke_return<type, _ArgTypes...>::type
     operator() (_ArgTypes&&... __args) const {
         return _VSTD::__invoke(__f_, _VSTD::forward<_ArgTypes>(__args)...);
@@ -1401,7 +1405,7 @@ public:
 };
 
 template<class _Rp, class _Tp>
-inline _LIBCPP_INLINE_VISIBILITY
+inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
 __mem_fn<_Rp _Tp::*>
 mem_fn(_Rp _Tp::* __pm) _NOEXCEPT
 {
@@ -2873,13 +2877,13 @@ public:
                                   !is_same<typename remove_reference<_Gp>::type,
                                            __bind>::value
                                >::type>
-      _LIBCPP_INLINE_VISIBILITY
+      _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
       explicit __bind(_Gp&& __f, _BA&& ...__bound_args)
         : __f_(_VSTD::forward<_Gp>(__f)),
           __bound_args_(_VSTD::forward<_BA>(__bound_args)...) {}
 
     template <class ..._Args>
-        _LIBCPP_INLINE_VISIBILITY
+        _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
         typename __bind_return<_Fd, _Td, tuple<_Args&&...> >::type
         operator()(_Args&& ...__args)
         {
@@ -2888,7 +2892,7 @@ public:
         }
 
     template <class ..._Args>
-        _LIBCPP_INLINE_VISIBILITY
+        _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
         typename __bind_return<const _Fd, const _Td, tuple<_Args&&...> >::type
         operator()(_Args&& ...__args) const
         {
@@ -2918,13 +2922,13 @@ public:
                                   !is_same<typename remove_reference<_Gp>::type,
                                            __bind_r>::value
                                >::type>
-      _LIBCPP_INLINE_VISIBILITY
+      _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
       explicit __bind_r(_Gp&& __f, _BA&& ...__bound_args)
         : base(_VSTD::forward<_Gp>(__f),
                _VSTD::forward<_BA>(__bound_args)...) {}
 
     template <class ..._Args>
-        _LIBCPP_INLINE_VISIBILITY
+        _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
         typename enable_if
         <
             is_convertible<typename __bind_return<_Fd, _Td, tuple<_Args&&...> >::type,
@@ -2938,7 +2942,7 @@ public:
         }
 
     template <class ..._Args>
-        _LIBCPP_INLINE_VISIBILITY
+        _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
         typename enable_if
         <
             is_convertible<typename __bind_return<const _Fd, const _Td, tuple<_Args&&...> >::type,
@@ -2956,7 +2960,7 @@ template<class _Rp, class _Fp, class ..._BoundArgs>
 struct __is_bind_expression<__bind_r<_Rp, _Fp, _BoundArgs...> > : public true_type {};
 
 template<class _Fp, class ..._BoundArgs>
-inline _LIBCPP_INLINE_VISIBILITY
+inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
 __bind<_Fp, _BoundArgs...>
 bind(_Fp&& __f, _BoundArgs&&... __bound_args)
 {
@@ -2965,7 +2969,7 @@ bind(_Fp&& __f, _BoundArgs&&... __bound_args)
 }
 
 template<class _Rp, class _Fp, class ..._BoundArgs>
-inline _LIBCPP_INLINE_VISIBILITY
+inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
 __bind_r<_Rp, _Fp, _BoundArgs...>
 bind(_Fp&& __f, _BoundArgs&&... __bound_args)
 {
@@ -2978,7 +2982,7 @@ bind(_Fp&& __f, _BoundArgs&&... __bound_args)
 #if _LIBCPP_STD_VER > 14
 
 template <class _Fn, class ..._Args>
-invoke_result_t<_Fn, _Args...>
+_LIBCPP_CONSTEXPR_AFTER_CXX17 invoke_result_t<_Fn, _Args...>
 invoke(_Fn&& __f, _Args&&... __args)
     noexcept(is_nothrow_invocable_v<_Fn, _Args...>)
 {
@@ -2993,21 +2997,21 @@ public:
     __not_fn_imp() = delete;
 
     template <class ..._Args>
-    _LIBCPP_INLINE_VISIBILITY
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     auto operator()(_Args&& ...__args) &
             noexcept(noexcept(!_VSTD::invoke(__fd, _VSTD::forward<_Args>(__args)...)))
         -> decltype(          !_VSTD::invoke(__fd, _VSTD::forward<_Args>(__args)...))
         { return              !_VSTD::invoke(__fd, _VSTD::forward<_Args>(__args)...); }
 
     template <class ..._Args>
-    _LIBCPP_INLINE_VISIBILITY
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     auto operator()(_Args&& ...__args) &&
             noexcept(noexcept(!_VSTD::invoke(_VSTD::move(__fd), _VSTD::forward<_Args>(__args)...)))
         -> decltype(          !_VSTD::invoke(_VSTD::move(__fd), _VSTD::forward<_Args>(__args)...))
         { return              !_VSTD::invoke(_VSTD::move(__fd), _VSTD::forward<_Args>(__args)...); }
 
     template <class ..._Args>
-    _LIBCPP_INLINE_VISIBILITY
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     auto operator()(_Args&& ...__args) const&
             noexcept(noexcept(!_VSTD::invoke(__fd, _VSTD::forward<_Args>(__args)...)))
         -> decltype(          !_VSTD::invoke(__fd, _VSTD::forward<_Args>(__args)...))
@@ -3015,7 +3019,7 @@ public:
 
 
     template <class ..._Args>
-    _LIBCPP_INLINE_VISIBILITY
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     auto operator()(_Args&& ...__args) const&&
             noexcept(noexcept(!_VSTD::invoke(_VSTD::move(__fd), _VSTD::forward<_Args>(__args)...)))
         -> decltype(          !_VSTD::invoke(_VSTD::move(__fd), _VSTD::forward<_Args>(__args)...))
@@ -3024,17 +3028,17 @@ public:
 private:
     template <class _RawFunc,
               class = enable_if_t<!is_same<decay_t<_RawFunc>, __not_fn_imp>::value>>
-    _LIBCPP_INLINE_VISIBILITY
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     explicit __not_fn_imp(_RawFunc&& __rf)
         : __fd(_VSTD::forward<_RawFunc>(__rf)) {}
 
     template <class _RawFunc>
-    friend inline _LIBCPP_INLINE_VISIBILITY
+    friend inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     __not_fn_imp<decay_t<_RawFunc>> not_fn(_RawFunc&&);
 };
 
 template <class _RawFunc>
-inline _LIBCPP_INLINE_VISIBILITY
+inline _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
 __not_fn_imp<decay_t<_RawFunc>> not_fn(_RawFunc&& __fn) {
     return __not_fn_imp<decay_t<_RawFunc>>(_VSTD::forward<_RawFunc>(__fn));
 }
@@ -3131,13 +3135,13 @@ __search(_RandomAccessIterator1 __first1, _RandomAccessIterator1 __last1,
 template<class _ForwardIterator, class _BinaryPredicate = equal_to<>>
 class _LIBCPP_TYPE_VIS default_searcher {
 public:
-    _LIBCPP_INLINE_VISIBILITY
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     default_searcher(_ForwardIterator __f, _ForwardIterator __l,
                        _BinaryPredicate __p = _BinaryPredicate())
         : __first_(__f), __last_(__l), __pred_(__p) {}
 
     template <typename _ForwardIterator2>
-    _LIBCPP_INLINE_VISIBILITY
+    _LIBCPP_INLINE_VISIBILITY _LIBCPP_CONSTEXPR_AFTER_CXX17
     pair<_ForwardIterator2, _ForwardIterator2>
     operator () (_ForwardIterator2 __f, _ForwardIterator2 __l) const
     {
diff --git a/libcxx/include/type_traits b/libcxx/include/type_traits
index c1633f19c51f6..99b2a8f9f025f 100644
--- a/libcxx/include/type_traits
+++ b/libcxx/include/type_traits
@@ -3584,7 +3584,7 @@ auto __invoke_constexpr(__any, _Args&& ...__args) -> __nat;
 template <class _Fp, class _A0, class ..._Args,
           class = __enable_if_bullet1<_Fp, _A0>>
 inline _LIBCPP_INLINE_VISIBILITY
-auto
+_LIBCPP_CONSTEXPR_AFTER_CXX17 auto
 __invoke(_Fp&& __f, _A0&& __a0, _Args&& ...__args)
 _LIBCPP_INVOKE_RETURN((_VSTD::forward<_A0>(__a0).*__f)(_VSTD::forward<_Args>(__args)...))
 
@@ -3598,7 +3598,7 @@ _LIBCPP_INVOKE_RETURN((_VSTD::forward<_A0>(__a0).*__f)(_VSTD::forward<_Args>(__a
 template <class _Fp, class _A0, class ..._Args,
           class = __enable_if_bullet2<_Fp, _A0>>
 inline _LIBCPP_INLINE_VISIBILITY
-auto
+_LIBCPP_CONSTEXPR_AFTER_CXX17 auto
 __invoke(_Fp&& __f, _A0&& __a0, _Args&& ...__args)
 _LIBCPP_INVOKE_RETURN((__a0.get().*__f)(_VSTD::forward<_Args>(__args)...))
 
@@ -3612,7 +3612,7 @@ _LIBCPP_INVOKE_RETURN((__a0.get().*__f)(_VSTD::forward<_Args>(__args)...))
 template <class _Fp, class _A0, class ..._Args,
           class = __enable_if_bullet3<_Fp, _A0>>
 inline _LIBCPP_INLINE_VISIBILITY
-auto
+_LIBCPP_CONSTEXPR_AFTER_CXX17 auto
 __invoke(_Fp&& __f, _A0&& __a0, _Args&& ...__args)
 _LIBCPP_INVOKE_RETURN(((*_VSTD::forward<_A0>(__a0)).*__f)(_VSTD::forward<_Args>(__args)...))
 
@@ -3628,7 +3628,7 @@ _LIBCPP_INVOKE_RETURN(((*_VSTD::forward<_A0>(__a0)).*__f)(_VSTD::forward<_Args>(
 template <class _Fp, class _A0,
           class = __enable_if_bullet4<_Fp, _A0>>
 inline _LIBCPP_INLINE_VISIBILITY
-auto
+_LIBCPP_CONSTEXPR_AFTER_CXX17 auto
 __invoke(_Fp&& __f, _A0&& __a0)
 _LIBCPP_INVOKE_RETURN(_VSTD::forward<_A0>(__a0).*__f)
 
@@ -3642,7 +3642,7 @@ _LIBCPP_INVOKE_RETURN(_VSTD::forward<_A0>(__a0).*__f)
 template <class _Fp, class _A0,
           class = __enable_if_bullet5<_Fp, _A0>>
 inline _LIBCPP_INLINE_VISIBILITY
-auto
+_LIBCPP_CONSTEXPR_AFTER_CXX17 auto
 __invoke(_Fp&& __f, _A0&& __a0)
 _LIBCPP_INVOKE_RETURN(__a0.get().*__f)
 
@@ -3656,7 +3656,7 @@ _LIBCPP_INVOKE_RETURN(__a0.get().*__f)
 template <class _Fp, class _A0,
           class = __enable_if_bullet6<_Fp, _A0>>
 inline _LIBCPP_INLINE_VISIBILITY
-auto
+_LIBCPP_CONSTEXPR_AFTER_CXX17 auto
 __invoke(_Fp&& __f, _A0&& __a0)
 _LIBCPP_INVOKE_RETURN((*_VSTD::forward<_A0>(__a0)).*__f)
 
@@ -3671,7 +3671,7 @@ _LIBCPP_INVOKE_RETURN((*_VSTD::forward<_A0>(__a0)).*__f)
 
 template <class _Fp, class ..._Args>
 inline _LIBCPP_INLINE_VISIBILITY
-auto
+_LIBCPP_CONSTEXPR_AFTER_CXX17 auto
 __invoke(_Fp&& __f, _Args&& ...__args)
 _LIBCPP_INVOKE_RETURN(_VSTD::forward<_Fp>(__f)(_VSTD::forward<_Args>(__args)...))
 
diff --git a/libcxx/include/version b/libcxx/include/version
index e32f47ae837aa..dde6ca165b354 100644
--- a/libcxx/include/version
+++ b/libcxx/include/version
@@ -46,8 +46,7 @@ __cpp_lib_clamp                                         201603L <algorithm>
 __cpp_lib_complex_udls                                  201309L <complex>
 __cpp_lib_concepts                                      201806L <concepts>
 __cpp_lib_constexpr_dynamic_alloc                       201907L <memory>
-__cpp_lib_constexpr_misc                                201811L <array> <functional> <iterator>
-                                                                <string_view> <tuple> <utility>
+__cpp_lib_constexpr_functional                          201907L <functional>
 __cpp_lib_constexpr_numeric                             201911L <numeric>
 __cpp_lib_constexpr_swap_algorithms                     201806L <algorithm>
 __cpp_lib_constexpr_utility                             201811L <utility>
@@ -254,7 +253,7 @@ __cpp_lib_void_t                                        201411L <type_traits>
 # endif
 // # define __cpp_lib_concepts                             201806L
 # define __cpp_lib_constexpr_dynamic_alloc              201907L
-// # define __cpp_lib_constexpr_misc                       201811L
+# define __cpp_lib_constexpr_functional                 201907L
 # define __cpp_lib_constexpr_numeric                    201911L
 // # define __cpp_lib_constexpr_swap_algorithms            201806L
 # define __cpp_lib_constexpr_utility                    201811L
diff --git a/libcxx/test/libcxx/atomics/atomics.align/align.pass.pass.cpp b/libcxx/test/libcxx/atomics/atomics.align/align.pass.pass.cpp
index ebe8fc82775c7..96a34e22069c8 100644
--- a/libcxx/test/libcxx/atomics/atomics.align/align.pass.pass.cpp
+++ b/libcxx/test/libcxx/atomics/atomics.align/align.pass.pass.cpp
@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 //
 // UNSUPPORTED: libcpp-has-no-threads, c++03
-// REQUIRES: non-lockfree-atomics
+// REQUIRES: is-lockfree-runtime-function
 
 // GCC currently fails because it needs -fabi-version=6 to fix mangling of
 // std::atomic when used with __attribute__((vector(X))).
diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/array.version.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/array.version.pass.cpp
index 933420be50c96..c2e831a3af317 100644
--- a/libcxx/test/std/language.support/support.limits/support.limits.general/array.version.pass.cpp
+++ b/libcxx/test/std/language.support/support.limits/support.limits.general/array.version.pass.cpp
@@ -16,7 +16,6 @@
 /*  Constant                                Value
     __cpp_lib_array_constexpr               201603L [C++17]
                                             201811L [C++2a]
-    __cpp_lib_constexpr_misc                201811L [C++2a]
     __cpp_lib_nonmember_container_access    201411L [C++17]
     __cpp_lib_to_array                      201907L [C++2a]
 */
@@ -30,10 +29,6 @@
 #   error "__cpp_lib_array_constexpr should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_nonmember_container_access
 #   error "__cpp_lib_nonmember_container_access should not be defined before c++17"
 # endif
@@ -48,10 +43,6 @@
 #   error "__cpp_lib_array_constexpr should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_nonmember_container_access
 #   error "__cpp_lib_nonmember_container_access should not be defined before c++17"
 # endif
@@ -69,10 +60,6 @@
 #   error "__cpp_lib_array_constexpr should have the value 201603L in c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifndef __cpp_lib_nonmember_container_access
 #   error "__cpp_lib_nonmember_container_access should be defined in c++17"
 # endif
@@ -93,19 +80,6 @@
 #   error "__cpp_lib_array_constexpr should have the value 201811L in c++2a"
 # endif
 
-# if !defined(_LIBCPP_VERSION)
-#   ifndef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should be defined in c++2a"
-#   endif
-#   if __cpp_lib_constexpr_misc != 201811L
-#     error "__cpp_lib_constexpr_misc should have the value 201811L in c++2a"
-#   endif
-# else // _LIBCPP_VERSION
-#   ifdef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should not be defined because it is unimplemented in libc++!"
-#   endif
-# endif
-
 # ifndef __cpp_lib_nonmember_container_access
 #   error "__cpp_lib_nonmember_container_access should be defined in c++2a"
 # endif
diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.pass.cpp
index a29a1d708a304..2b556010f00e1 100644
--- a/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.pass.cpp
+++ b/libcxx/test/std/language.support/support.limits/support.limits.general/functional.version.pass.cpp
@@ -16,7 +16,7 @@
 /*  Constant                           Value
     __cpp_lib_bind_front               201811L [C++2a]
     __cpp_lib_boyer_moore_searcher     201603L [C++17]
-    __cpp_lib_constexpr_misc           201811L [C++2a]
+    __cpp_lib_constexpr_functional     201907L [C++2a]
     __cpp_lib_invoke                   201411L [C++17]
     __cpp_lib_not_fn                   201603L [C++17]
     __cpp_lib_ranges                   201811L [C++2a]
@@ -38,8 +38,8 @@
 #   error "__cpp_lib_boyer_moore_searcher should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
+# ifdef __cpp_lib_constexpr_functional
+#   error "__cpp_lib_constexpr_functional should not be defined before c++2a"
 # endif
 
 # ifdef __cpp_lib_invoke
@@ -72,8 +72,8 @@
 #   error "__cpp_lib_boyer_moore_searcher should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
+# ifdef __cpp_lib_constexpr_functional
+#   error "__cpp_lib_constexpr_functional should not be defined before c++2a"
 # endif
 
 # ifdef __cpp_lib_invoke
@@ -121,8 +121,8 @@
 #   endif
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
+# ifdef __cpp_lib_constexpr_functional
+#   error "__cpp_lib_constexpr_functional should not be defined before c++2a"
 # endif
 
 # ifndef __cpp_lib_invoke
@@ -185,17 +185,11 @@
 #   endif
 # endif
 
-# if !defined(_LIBCPP_VERSION)
-#   ifndef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should be defined in c++2a"
-#   endif
-#   if __cpp_lib_constexpr_misc != 201811L
-#     error "__cpp_lib_constexpr_misc should have the value 201811L in c++2a"
-#   endif
-# else // _LIBCPP_VERSION
-#   ifdef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should not be defined because it is unimplemented in libc++!"
-#   endif
+# ifndef __cpp_lib_constexpr_functional
+#   error "__cpp_lib_constexpr_functional should be defined in c++2a"
+# endif
+# if __cpp_lib_constexpr_functional != 201907L
+#   error "__cpp_lib_constexpr_functional should have the value 201907L in c++2a"
 # endif
 
 # ifndef __cpp_lib_invoke
diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/iterator.version.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/iterator.version.pass.cpp
index 4e68cf9a72323..0c128f5a46dee 100644
--- a/libcxx/test/std/language.support/support.limits/support.limits.general/iterator.version.pass.cpp
+++ b/libcxx/test/std/language.support/support.limits/support.limits.general/iterator.version.pass.cpp
@@ -16,7 +16,6 @@
 /*  Constant                                Value
     __cpp_lib_array_constexpr               201603L [C++17]
                                             201811L [C++2a]
-    __cpp_lib_constexpr_misc                201811L [C++2a]
     __cpp_lib_make_reverse_iterator         201402L [C++14]
     __cpp_lib_nonmember_container_access    201411L [C++17]
     __cpp_lib_null_iterators                201304L [C++14]
@@ -32,10 +31,6 @@
 #   error "__cpp_lib_array_constexpr should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_make_reverse_iterator
 #   error "__cpp_lib_make_reverse_iterator should not be defined before c++14"
 # endif
@@ -58,10 +53,6 @@
 #   error "__cpp_lib_array_constexpr should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifndef __cpp_lib_make_reverse_iterator
 #   error "__cpp_lib_make_reverse_iterator should be defined in c++14"
 # endif
@@ -93,10 +84,6 @@
 #   error "__cpp_lib_array_constexpr should have the value 201603L in c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifndef __cpp_lib_make_reverse_iterator
 #   error "__cpp_lib_make_reverse_iterator should be defined in c++17"
 # endif
@@ -131,19 +118,6 @@
 #   error "__cpp_lib_array_constexpr should have the value 201811L in c++2a"
 # endif
 
-# if !defined(_LIBCPP_VERSION)
-#   ifndef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should be defined in c++2a"
-#   endif
-#   if __cpp_lib_constexpr_misc != 201811L
-#     error "__cpp_lib_constexpr_misc should have the value 201811L in c++2a"
-#   endif
-# else // _LIBCPP_VERSION
-#   ifdef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should not be defined because it is unimplemented in libc++!"
-#   endif
-# endif
-
 # ifndef __cpp_lib_make_reverse_iterator
 #   error "__cpp_lib_make_reverse_iterator should be defined in c++2a"
 # endif
diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/string_view.version.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/string_view.version.pass.cpp
index 816083e0d7f33..1fca20d41f8cd 100644
--- a/libcxx/test/std/language.support/support.limits/support.limits.general/string_view.version.pass.cpp
+++ b/libcxx/test/std/language.support/support.limits/support.limits.general/string_view.version.pass.cpp
@@ -13,10 +13,9 @@
 
 // Test the feature test macros defined by <string_view>
 
-/*  Constant                    Value
-    __cpp_lib_char8_t           201811L [C++2a]
-    __cpp_lib_constexpr_misc    201811L [C++2a]
-    __cpp_lib_string_view       201606L [C++17]
+/*  Constant                 Value
+    __cpp_lib_char8_t        201811L [C++2a]
+    __cpp_lib_string_view    201606L [C++17]
 */
 
 #include <string_view>
@@ -28,10 +27,6 @@
 #   error "__cpp_lib_char8_t should not be defined before c++2a"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_string_view
 #   error "__cpp_lib_string_view should not be defined before c++17"
 # endif
@@ -42,10 +37,6 @@
 #   error "__cpp_lib_char8_t should not be defined before c++2a"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_string_view
 #   error "__cpp_lib_string_view should not be defined before c++17"
 # endif
@@ -56,10 +47,6 @@
 #   error "__cpp_lib_char8_t should not be defined before c++2a"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifndef __cpp_lib_string_view
 #   error "__cpp_lib_string_view should be defined in c++17"
 # endif
@@ -82,19 +69,6 @@
 #   endif
 # endif
 
-# if !defined(_LIBCPP_VERSION)
-#   ifndef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should be defined in c++2a"
-#   endif
-#   if __cpp_lib_constexpr_misc != 201811L
-#     error "__cpp_lib_constexpr_misc should have the value 201811L in c++2a"
-#   endif
-# else // _LIBCPP_VERSION
-#   ifdef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should not be defined because it is unimplemented in libc++!"
-#   endif
-# endif
-
 # ifndef __cpp_lib_string_view
 #   error "__cpp_lib_string_view should be defined in c++2a"
 # endif
diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.pass.cpp
index 5c1e6580c57d6..e4c3d54d1982c 100644
--- a/libcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.pass.cpp
+++ b/libcxx/test/std/language.support/support.limits/support.limits.general/tuple.version.pass.cpp
@@ -15,7 +15,6 @@
 
 /*  Constant                     Value
     __cpp_lib_apply              201603L [C++17]
-    __cpp_lib_constexpr_misc     201811L [C++2a]
     __cpp_lib_make_from_tuple    201606L [C++17]
     __cpp_lib_tuple_element_t    201402L [C++14]
     __cpp_lib_tuples_by_type     201304L [C++14]
@@ -30,10 +29,6 @@
 #   error "__cpp_lib_apply should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_make_from_tuple
 #   error "__cpp_lib_make_from_tuple should not be defined before c++17"
 # endif
@@ -52,10 +47,6 @@
 #   error "__cpp_lib_apply should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_make_from_tuple
 #   error "__cpp_lib_make_from_tuple should not be defined before c++17"
 # endif
@@ -83,10 +74,6 @@
 #   error "__cpp_lib_apply should have the value 201603L in c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifndef __cpp_lib_make_from_tuple
 #   error "__cpp_lib_make_from_tuple should be defined in c++17"
 # endif
@@ -117,19 +104,6 @@
 #   error "__cpp_lib_apply should have the value 201603L in c++2a"
 # endif
 
-# if !defined(_LIBCPP_VERSION)
-#   ifndef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should be defined in c++2a"
-#   endif
-#   if __cpp_lib_constexpr_misc != 201811L
-#     error "__cpp_lib_constexpr_misc should have the value 201811L in c++2a"
-#   endif
-# else // _LIBCPP_VERSION
-#   ifdef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should not be defined because it is unimplemented in libc++!"
-#   endif
-# endif
-
 # ifndef __cpp_lib_make_from_tuple
 #   error "__cpp_lib_make_from_tuple should be defined in c++2a"
 # endif
diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/utility.version.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/utility.version.pass.cpp
index e595a99a749ff..63f755e66047f 100644
--- a/libcxx/test/std/language.support/support.limits/support.limits.general/utility.version.pass.cpp
+++ b/libcxx/test/std/language.support/support.limits/support.limits.general/utility.version.pass.cpp
@@ -15,7 +15,6 @@
 
 /*  Constant                       Value
     __cpp_lib_as_const             201510L [C++17]
-    __cpp_lib_constexpr_misc       201811L [C++2a]
     __cpp_lib_constexpr_utility    201811L [C++2a]
     __cpp_lib_exchange_function    201304L [C++14]
     __cpp_lib_integer_sequence     201304L [C++14]
@@ -32,10 +31,6 @@
 #   error "__cpp_lib_as_const should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_constexpr_utility
 #   error "__cpp_lib_constexpr_utility should not be defined before c++2a"
 # endif
@@ -62,10 +57,6 @@
 #   error "__cpp_lib_as_const should not be defined before c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_constexpr_utility
 #   error "__cpp_lib_constexpr_utility should not be defined before c++2a"
 # endif
@@ -104,10 +95,6 @@
 #   error "__cpp_lib_as_const should have the value 201510L in c++17"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
-# endif
-
 # ifdef __cpp_lib_constexpr_utility
 #   error "__cpp_lib_constexpr_utility should not be defined before c++2a"
 # endif
@@ -155,19 +142,6 @@
 #   error "__cpp_lib_as_const should have the value 201510L in c++2a"
 # endif
 
-# if !defined(_LIBCPP_VERSION)
-#   ifndef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should be defined in c++2a"
-#   endif
-#   if __cpp_lib_constexpr_misc != 201811L
-#     error "__cpp_lib_constexpr_misc should have the value 201811L in c++2a"
-#   endif
-# else // _LIBCPP_VERSION
-#   ifdef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should not be defined because it is unimplemented in libc++!"
-#   endif
-# endif
-
 # ifndef __cpp_lib_constexpr_utility
 #   error "__cpp_lib_constexpr_utility should be defined in c++2a"
 # endif
diff --git a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp
index 783c5449038c7..e37907185db13 100644
--- a/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp
+++ b/libcxx/test/std/language.support/support.limits/support.limits.general/version.version.pass.cpp
@@ -41,7 +41,7 @@
     __cpp_lib_complex_udls                         201309L [C++14]
     __cpp_lib_concepts                             201806L [C++2a]
     __cpp_lib_constexpr_dynamic_alloc              201907L [C++2a]
-    __cpp_lib_constexpr_misc                       201811L [C++2a]
+    __cpp_lib_constexpr_functional                 201907L [C++2a]
     __cpp_lib_constexpr_numeric                    201911L [C++2a]
     __cpp_lib_constexpr_swap_algorithms            201806L [C++2a]
     __cpp_lib_constexpr_utility                    201811L [C++2a]
@@ -224,8 +224,8 @@
 #   error "__cpp_lib_constexpr_dynamic_alloc should not be defined before c++2a"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
+# ifdef __cpp_lib_constexpr_functional
+#   error "__cpp_lib_constexpr_functional should not be defined before c++2a"
 # endif
 
 # ifdef __cpp_lib_constexpr_numeric
@@ -620,8 +620,8 @@
 #   error "__cpp_lib_constexpr_dynamic_alloc should not be defined before c++2a"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
+# ifdef __cpp_lib_constexpr_functional
+#   error "__cpp_lib_constexpr_functional should not be defined before c++2a"
 # endif
 
 # ifdef __cpp_lib_constexpr_numeric
@@ -1130,8 +1130,8 @@
 #   error "__cpp_lib_constexpr_dynamic_alloc should not be defined before c++2a"
 # endif
 
-# ifdef __cpp_lib_constexpr_misc
-#   error "__cpp_lib_constexpr_misc should not be defined before c++2a"
+# ifdef __cpp_lib_constexpr_functional
+#   error "__cpp_lib_constexpr_functional should not be defined before c++2a"
 # endif
 
 # ifdef __cpp_lib_constexpr_numeric
@@ -1904,17 +1904,11 @@
 #   error "__cpp_lib_constexpr_dynamic_alloc should have the value 201907L in c++2a"
 # endif
 
-# if !defined(_LIBCPP_VERSION)
-#   ifndef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should be defined in c++2a"
-#   endif
-#   if __cpp_lib_constexpr_misc != 201811L
-#     error "__cpp_lib_constexpr_misc should have the value 201811L in c++2a"
-#   endif
-# else // _LIBCPP_VERSION
-#   ifdef __cpp_lib_constexpr_misc
-#     error "__cpp_lib_constexpr_misc should not be defined because it is unimplemented in libc++!"
-#   endif
+# ifndef __cpp_lib_constexpr_functional
+#   error "__cpp_lib_constexpr_functional should be defined in c++2a"
+# endif
+# if __cpp_lib_constexpr_functional != 201907L
+#   error "__cpp_lib_constexpr_functional should have the value 201907L in c++2a"
 # endif
 
 # ifndef __cpp_lib_constexpr_numeric
diff --git a/libcxx/test/std/utilities/function.objects/func.invoke/invoke_constexpr.pass.cpp b/libcxx/test/std/utilities/function.objects/func.invoke/invoke_constexpr.pass.cpp
new file mode 100644
index 0000000000000..8bfc7428fad9d
--- /dev/null
+++ b/libcxx/test/std/utilities/function.objects/func.invoke/invoke_constexpr.pass.cpp
@@ -0,0 +1,279 @@
+//===----------------------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// UNSUPPORTED: c++03, c++11, c++14, c++17
+
+// <functional>
+
+// template<class F, class... Args>
+// constexpr  // constexpr in C++20
+// invoke_result_t<F, Args...> invoke(F&& f, Args&&... args)
+//     noexcept(is_nothrow_invocable_v<_Fn, _Args...>);
+
+/// C++14 [func.def] 20.9.0
+/// (1) The following definitions apply to this Clause:
+/// (2) A call signature is the name of a return type followed by a parenthesized
+///     comma-separated list of zero or more argument types.
+/// (3) A callable type is a function object type (20.9) or a pointer to member.
+/// (4) A callable object is an object of a callable type.
+/// (5) A call wrapper type is a type that holds a callable object and supports
+///     a call operation that forwards to that object.
+/// (6) A call wrapper is an object of a call wrapper type.
+/// (7) A target object is the callable object held by a call wrapper.
+
+/// C++14 [func.require] 20.9.1
+///
+/// Define INVOKE (f, t1, t2, ..., tN) as follows:
+///   (1.1) - (t1.*f)(t2, ..., tN) when f is a pointer to a member function of a class T and t1 is an object of
+///   type T or a reference to an object of type T or a reference to an object of a type derived from T;
+///   (1.2) - ((*t1).*f)(t2, ..., tN) when f is a pointer to a member function of a class T and t1 is not one of
+///   the types described in the previous item;
+///   (1.3) - t1.*f when N == 1 and f is a pointer to member data of a class T and t1 is an object of type T or a
+///   reference to an object of type T or a reference to an object of a type derived from T;
+///   (1.4) - (*t1).*f when N == 1 and f is a pointer to member data of a class T and t1 is not one of the types
+///   described in the previous item;
+///   (1.5) - f(t1, t2, ..., tN) in all other cases.
+
+#include <functional>
+#include <type_traits>
+#include <utility> // for std::move
+#include <cassert>
+
+#include "test_macros.h"
+
+struct NonCopyable {
+    constexpr NonCopyable() {}
+private:
+    NonCopyable(NonCopyable const&) = delete;
+    NonCopyable& operator=(NonCopyable const&) = delete;
+};
+
+struct TestClass {
+    constexpr explicit TestClass(int x) : data(x) {}
+
+    constexpr int& operator()(NonCopyable&&) & { return data; }
+    constexpr int const& operator()(NonCopyable&&) const & { return data; }
+
+    constexpr int&& operator()(NonCopyable&&) && { return std::move(data); }
+    constexpr int const&& operator()(NonCopyable&&) const && { return std::move(data); }
+
+    int data;
+private:
+    TestClass(TestClass const&) = delete;
+    TestClass& operator=(TestClass const&) = delete;
+};
+
+struct DerivedFromTestClass : public TestClass {
+    constexpr explicit DerivedFromTestClass(int x) : TestClass(x) {}
+};
+
+static constexpr int data = 42;
+constexpr const int& foo(NonCopyable&&) {
+    return data;
+}
+
+template <class Signature,  class Expect, class Functor>
+constexpr void test_b12(Functor&& f) {
+    // Create the callable object.
+    typedef Signature TestClass::*ClassFunc;
+    ClassFunc func_ptr = &TestClass::operator();
+
+    // Create the dummy arg.
+    NonCopyable arg;
+
+    // Check that the deduced return type of invoke is what is expected.
+    typedef decltype(
+        std::invoke(func_ptr, std::forward<Functor>(f), std::move(arg))
+    ) DeducedReturnType;
+    static_assert((std::is_same<DeducedReturnType, Expect>::value), "");
+
+    // Check that result_of_t matches Expect.
+    typedef typename std::result_of<ClassFunc&&(Functor&&, NonCopyable&&)>::type
+      ResultOfReturnType;
+    static_assert((std::is_same<ResultOfReturnType, Expect>::value), "");
+
+    // Run invoke and check the return value.
+    DeducedReturnType ret =
+            std::invoke(func_ptr, std::forward<Functor>(f), std::move(arg));
+    assert(ret == 42);
+}
+
+template <class Expect, class Functor>
+constexpr void test_b34(Functor&& f) {
+    // Create the callable object.
+    typedef int TestClass::*ClassFunc;
+    ClassFunc func_ptr = &TestClass::data;
+
+    // Check that the deduced return type of invoke is what is expected.
+    typedef decltype(
+        std::invoke(func_ptr, std::forward<Functor>(f))
+    ) DeducedReturnType;
+    static_assert((std::is_same<DeducedReturnType, Expect>::value), "");
+
+    // Check that result_of_t matches Expect.
+    typedef typename std::result_of<ClassFunc&&(Functor&&)>::type
+            ResultOfReturnType;
+    static_assert((std::is_same<ResultOfReturnType, Expect>::value), "");
+
+    // Run invoke and check the return value.
+    DeducedReturnType ret =
+            std::invoke(func_ptr, std::forward<Functor>(f));
+    assert(ret == 42);
+}
+
+template <class Expect, class Functor>
+constexpr void test_b5(Functor&& f) {
+    NonCopyable arg;
+
+    // Check that the deduced return type of invoke is what is expected.
+    typedef decltype(
+        std::invoke(std::forward<Functor>(f), std::move(arg))
+    ) DeducedReturnType;
+    static_assert((std::is_same<DeducedReturnType, Expect>::value), "");
+
+    // Check that result_of_t matches Expect.
+    typedef typename std::result_of<Functor&&(NonCopyable&&)>::type
+            ResultOfReturnType;
+    static_assert((std::is_same<ResultOfReturnType, Expect>::value), "");
+
+    // Run invoke and check the return value.
+    DeducedReturnType ret = std::invoke(std::forward<Functor>(f), std::move(arg));
+    assert(ret == 42);
+}
+
+constexpr bool bullet_one_two_tests() {
+    {
+        TestClass cl(42);
+        test_b12<int&(NonCopyable&&) &, int&>(cl);
+        test_b12<int const&(NonCopyable&&) const &, int const&>(cl);
+
+        test_b12<int&&(NonCopyable&&) &&, int&&>(std::move(cl));
+        test_b12<int const&&(NonCopyable&&) const &&, int const&&>(std::move(cl));
+    }
+    {
+        DerivedFromTestClass cl(42);
+        test_b12<int&(NonCopyable&&) &, int&>(cl);
+        test_b12<int const&(NonCopyable&&) const &, int const&>(cl);
+
+        test_b12<int&&(NonCopyable&&) &&, int&&>(std::move(cl));
+        test_b12<int const&&(NonCopyable&&) const &&, int const&&>(std::move(cl));
+    }
+    {
+        TestClass cl_obj(42);
+        std::reference_wrapper<TestClass> cl(cl_obj);
+        test_b12<int&(NonCopyable&&) &, int&>(cl);
+        test_b12<int const&(NonCopyable&&) const &, int const&>(cl);
+
+        test_b12<int&(NonCopyable&&) &, int&>(std::move(cl));
+        test_b12<int const&(NonCopyable&&) const &, int const&>(std::move(cl));
+    }
+    {
+        DerivedFromTestClass cl_obj(42);
+        std::reference_wrapper<DerivedFromTestClass> cl(cl_obj);
+        test_b12<int&(NonCopyable&&) &, int&>(cl);
+        test_b12<int const&(NonCopyable&&) const &, int const&>(cl);
+
+        test_b12<int&(NonCopyable&&) &, int&>(std::move(cl));
+        test_b12<int const&(NonCopyable&&) const &, int const&>(std::move(cl));
+    }
+    {
+        TestClass cl_obj(42);
+        TestClass *cl = &cl_obj;
+        test_b12<int&(NonCopyable&&) &, int&>(cl);
+        test_b12<int const&(NonCopyable&&) const &, int const&>(cl);
+    }
+    {
+        DerivedFromTestClass cl_obj(42);
+        DerivedFromTestClass *cl = &cl_obj;
+        test_b12<int&(NonCopyable&&) &, int&>(cl);
+        test_b12<int const&(NonCopyable&&) const &, int const&>(cl);
+    }
+    return true;
+}
+
+constexpr bool bullet_three_four_tests() {
+    {
+        typedef TestClass Fn;
+        Fn cl(42);
+        test_b34<int&>(cl);
+        test_b34<int const&>(static_cast<Fn const&>(cl));
+
+        test_b34<int&&>(static_cast<Fn &&>(cl));
+        test_b34<int const&&>(static_cast<Fn const&&>(cl));
+    }
+    {
+        typedef DerivedFromTestClass Fn;
+        Fn cl(42);
+        test_b34<int&>(cl);
+        test_b34<int const&>(static_cast<Fn const&>(cl));
+
+        test_b34<int&&>(static_cast<Fn &&>(cl));
+        test_b34<int const&&>(static_cast<Fn const&&>(cl));
+    }
+    {
+        typedef TestClass Fn;
+        Fn cl(42);
+        test_b34<int&>(std::reference_wrapper<Fn>(cl));
+        test_b34<int const&>(std::reference_wrapper<Fn const>(cl));
+    }
+    {
+        typedef DerivedFromTestClass Fn;
+        Fn cl(42);
+        test_b34<int&>(std::reference_wrapper<Fn>(cl));
+        test_b34<int const&>(std::reference_wrapper<Fn const>(cl));
+    }
+    {
+        typedef TestClass Fn;
+        Fn cl_obj(42);
+        Fn* cl = &cl_obj;
+        test_b34<int&>(cl);
+        test_b34<int const&>(static_cast<Fn const*>(cl));
+    }
+    {
+        typedef DerivedFromTestClass Fn;
+        Fn cl_obj(42);
+        Fn* cl = &cl_obj;
+        test_b34<int&>(cl);
+        test_b34<int const&>(static_cast<Fn const*>(cl));
+    }
+    return true;
+}
+
+constexpr bool bullet_five_tests() {
+    using FooType = const int&(NonCopyable&&);
+    {
+        FooType& fn = foo;
+        test_b5<const int &>(fn);
+    }
+    {
+        FooType* fn = foo;
+        test_b5<const int &>(fn);
+    }
+    {
+        typedef TestClass Fn;
+        Fn cl(42);
+        test_b5<int&>(cl);
+        test_b5<int const&>(static_cast<Fn const&>(cl));
+
+        test_b5<int&&>(static_cast<Fn &&>(cl));
+        test_b5<int const&&>(static_cast<Fn const&&>(cl));
+    }
+    return true;
+}
+
+int main(int, char**) {
+    bullet_one_two_tests();
+    bullet_three_four_tests();
+    bullet_five_tests();
+
+    static_assert(bullet_one_two_tests());
+    static_assert(bullet_three_four_tests());
+    static_assert(bullet_five_tests());
+
+    return 0;
+}
diff --git a/libcxx/test/std/utilities/function.objects/func.memfn/member_data.pass.cpp b/libcxx/test/std/utilities/function.objects/func.memfn/member_data.pass.cpp
index 0c340072da5a4..d6cd06cd8cd09 100644
--- a/libcxx/test/std/utilities/function.objects/func.memfn/member_data.pass.cpp
+++ b/libcxx/test/std/utilities/function.objects/func.memfn/member_data.pass.cpp
@@ -21,11 +21,11 @@ struct A
 };
 
 template <class F>
-void
+TEST_CONSTEXPR_CXX20 bool
 test(F f)
 {
     {
-    A a;
+    A a = {0.0};
     f(a) = 5;
     assert(a.data_ == 5);
     A* ap = &a;
@@ -36,11 +36,16 @@ test(F f)
     const F& cf = f;
     assert(cf(ap) == f(ap));
     }
+    return true;
 }
 
 int main(int, char**)
 {
     test(std::mem_fn(&A::data_));
 
-  return 0;
+#if TEST_STD_VER >= 20
+    static_assert(test(std::mem_fn(&A::data_)));
+#endif
+
+    return 0;
 }
diff --git a/libcxx/test/std/utilities/function.objects/func.memfn/member_function.pass.cpp b/libcxx/test/std/utilities/function.objects/func.memfn/member_function.pass.cpp
index a271c067008b9..88d4108e10ac0 100644
--- a/libcxx/test/std/utilities/function.objects/func.memfn/member_function.pass.cpp
+++ b/libcxx/test/std/utilities/function.objects/func.memfn/member_function.pass.cpp
@@ -18,13 +18,13 @@
 
 struct A
 {
-    char test0() {return 'a';}
-    char test1(int) {return 'b';}
-    char test2(int, double) {return 'c';}
+    TEST_CONSTEXPR_CXX14 char test0() {return 'a';}
+    TEST_CONSTEXPR_CXX14 char test1(int) {return 'b';}
+    TEST_CONSTEXPR_CXX14 char test2(int, double) {return 'c';}
 };
 
 template <class F>
-void
+TEST_CONSTEXPR_CXX20 bool
 test0(F f)
 {
     {
@@ -35,10 +35,11 @@ test0(F f)
     const F& cf = f;
     assert(cf(ap) == 'a');
     }
+    return true;
 }
 
 template <class F>
-void
+TEST_CONSTEXPR_CXX20 bool
 test1(F f)
 {
     {
@@ -49,10 +50,11 @@ test1(F f)
     const F& cf = f;
     assert(cf(ap, 2) == 'b');
     }
+    return true;
 }
 
 template <class F>
-void
+TEST_CONSTEXPR_CXX20 bool
 test2(F f)
 {
     {
@@ -63,6 +65,7 @@ test2(F f)
     const F& cf = f;
     assert(cf(ap, 2, 3.5) == 'c');
     }
+    return true;
 }
 
 int main(int, char**)
@@ -74,5 +77,11 @@ int main(int, char**)
     static_assert((noexcept(std::mem_fn(&A::test0))), ""); // LWG#2489
 #endif
 
-  return 0;
+#if TEST_STD_VER >= 20
+    static_assert(test0(std::mem_fn(&A::test0)));
+    static_assert(test1(std::mem_fn(&A::test1)));
+    static_assert(test2(std::mem_fn(&A::test2)));
+#endif
+
+    return 0;
 }
diff --git a/libcxx/test/std/utilities/function.objects/func.memfn/member_function_const.pass.cpp b/libcxx/test/std/utilities/function.objects/func.memfn/member_function_const.pass.cpp
index 006a5bec2d392..057998c7e6e55 100644
--- a/libcxx/test/std/utilities/function.objects/func.memfn/member_function_const.pass.cpp
+++ b/libcxx/test/std/utilities/function.objects/func.memfn/member_function_const.pass.cpp
@@ -18,13 +18,13 @@
 
 struct A
 {
-    char test0() const {return 'a';}
-    char test1(int) const {return 'b';}
-    char test2(int, double) const {return 'c';}
+    TEST_CONSTEXPR char test0() const {return 'a';}
+    TEST_CONSTEXPR char test1(int) const {return 'b';}
+    TEST_CONSTEXPR char test2(int, double) const {return 'c';}
 };
 
 template <class F>
-void
+TEST_CONSTEXPR_CXX20 bool
 test0(F f)
 {
     {
@@ -37,10 +37,11 @@ test0(F f)
     const F& cf = f;
     assert(cf(ap) == 'a');
     }
+    return true;
 }
 
 template <class F>
-void
+TEST_CONSTEXPR_CXX20 bool
 test1(F f)
 {
     {
@@ -53,10 +54,11 @@ test1(F f)
     const F& cf = f;
     assert(cf(ap, 2) == 'b');
     }
+    return true;
 }
 
 template <class F>
-void
+TEST_CONSTEXPR_CXX20 bool
 test2(F f)
 {
     {
@@ -69,6 +71,7 @@ test2(F f)
     const F& cf = f;
     assert(cf(ap, 2, 3.5) == 'c');
     }
+    return true;
 }
 
 int main(int, char**)
@@ -77,5 +80,11 @@ int main(int, char**)
     test1(std::mem_fn(&A::test1));
     test2(std::mem_fn(&A::test2));
 
-  return 0;
+#if TEST_STD_VER >= 20
+    static_assert(test0(std::mem_fn(&A::test0)));
+    static_assert(test1(std::mem_fn(&A::test1)));
+    static_assert(test2(std::mem_fn(&A::test2)));
+#endif
+
+    return 0;
 }
diff --git a/libcxx/test/std/utilities/function.objects/func.not_fn/not_fn.pass.cpp b/libcxx/test/std/utilities/function.objects/func.not_fn/not_fn.pass.cpp
index 56ed61500d3c3..bb86dc9a8b6fd 100644
--- a/libcxx/test/std/utilities/function.objects/func.not_fn/not_fn.pass.cpp
+++ b/libcxx/test/std/utilities/function.objects/func.not_fn/not_fn.pass.cpp
@@ -23,50 +23,50 @@
 //                       CALLABLE TEST TYPES
 ///////////////////////////////////////////////////////////////////////////////
 
-bool returns_true() { return true; }
+constexpr bool returns_true() { return true; }
 
 template <class Ret = bool>
 struct MoveOnlyCallable {
   MoveOnlyCallable(MoveOnlyCallable const&) = delete;
-  MoveOnlyCallable(MoveOnlyCallable&& other)
+  constexpr MoveOnlyCallable(MoveOnlyCallable&& other)
       : value(other.value)
   { other.value = !other.value; }
 
   template <class ...Args>
-  Ret operator()(Args&&...) { return Ret{value}; }
+  constexpr Ret operator()(Args&&...) { return Ret{value}; }
 
-  explicit MoveOnlyCallable(bool x) : value(x) {}
+  constexpr explicit MoveOnlyCallable(bool x) : value(x) {}
   Ret value;
 };
 
 template <class Ret = bool>
 struct CopyCallable {
-  CopyCallable(CopyCallable const& other)
+  constexpr CopyCallable(CopyCallable const& other)
       : value(other.value) {}
 
-  CopyCallable(CopyCallable&& other)
+  constexpr CopyCallable(CopyCallable&& other)
       : value(other.value) { other.value = !other.value; }
 
   template <class ...Args>
-  Ret operator()(Args&&...) { return Ret{value}; }
+  constexpr Ret operator()(Args&&...) { return Ret{value}; }
 
-  explicit CopyCallable(bool x) : value(x)  {}
+  constexpr explicit CopyCallable(bool x) : value(x)  {}
   Ret value;
 };
 
 
 template <class Ret = bool>
 struct ConstCallable {
-  ConstCallable(ConstCallable const& other)
+  constexpr ConstCallable(ConstCallable const& other)
       : value(other.value) {}
 
-  ConstCallable(ConstCallable&& other)
+  constexpr ConstCallable(ConstCallable&& other)
       : value(other.value) { other.value = !other.value; }
 
   template <class ...Args>
-  Ret operator()(Args&&...) const { return Ret{value}; }
+  constexpr Ret operator()(Args&&...) const { return Ret{value}; }
 
-  explicit ConstCallable(bool x) : value(x)  {}
+  constexpr explicit ConstCallable(bool x) : value(x)  {}
   Ret value;
 };
 
@@ -74,51 +74,51 @@ struct ConstCallable {
 
 template <class Ret = bool>
 struct NoExceptCallable {
-  NoExceptCallable(NoExceptCallable const& other)
+  constexpr NoExceptCallable(NoExceptCallable const& other)
       : value(other.value) {}
 
   template <class ...Args>
-  Ret operator()(Args&&...) noexcept { return Ret{value}; }
+  constexpr Ret operator()(Args&&...) noexcept { return Ret{value}; }
 
   template <class ...Args>
-  Ret operator()(Args&&...) const noexcept { return Ret{value}; }
+  constexpr Ret operator()(Args&&...) const noexcept { return Ret{value}; }
 
-  explicit NoExceptCallable(bool x) : value(x)  {}
+  constexpr explicit NoExceptCallable(bool x) : value(x)  {}
   Ret value;
 };
 
 struct CopyAssignableWrapper {
-  CopyAssignableWrapper(CopyAssignableWrapper const&) = default;
-  CopyAssignableWrapper(CopyAssignableWrapper&&) = default;
-  CopyAssignableWrapper& operator=(CopyAssignableWrapper const&) = default;
-  CopyAssignableWrapper& operator=(CopyAssignableWrapper &&) = default;
+  constexpr CopyAssignableWrapper(CopyAssignableWrapper const&) = default;
+  constexpr CopyAssignableWrapper(CopyAssignableWrapper&&) = default;
+  constexpr CopyAssignableWrapper& operator=(CopyAssignableWrapper const&) = default;
+  constexpr CopyAssignableWrapper& operator=(CopyAssignableWrapper &&) = default;
 
   template <class ...Args>
-  bool operator()(Args&&...) { return value; }
+  constexpr bool operator()(Args&&...) { return value; }
 
-  explicit CopyAssignableWrapper(bool x) : value(x) {}
+  constexpr explicit CopyAssignableWrapper(bool x) : value(x) {}
   bool value;
 };
 
 
 struct MoveAssignableWrapper {
-  MoveAssignableWrapper(MoveAssignableWrapper const&) = delete;
-  MoveAssignableWrapper(MoveAssignableWrapper&&) = default;
-  MoveAssignableWrapper& operator=(MoveAssignableWrapper const&) = delete;
-  MoveAssignableWrapper& operator=(MoveAssignableWrapper &&) = default;
+  constexpr MoveAssignableWrapper(MoveAssignableWrapper const&) = delete;
+  constexpr MoveAssignableWrapper(MoveAssignableWrapper&&) = default;
+  constexpr MoveAssignableWrapper& operator=(MoveAssignableWrapper const&) = delete;
+  constexpr MoveAssignableWrapper& operator=(MoveAssignableWrapper &&) = default;
 
   template <class ...Args>
-  bool operator()(Args&&...) { return value; }
+  constexpr bool operator()(Args&&...) { return value; }
 
-  explicit MoveAssignableWrapper(bool x) : value(x) {}
+  constexpr explicit MoveAssignableWrapper(bool x) : value(x) {}
   bool value;
 };
 
 struct MemFunCallable {
-  explicit MemFunCallable(bool x) : value(x) {}
+  constexpr explicit MemFunCallable(bool x) : value(x) {}
 
-  bool return_value() const { return value; }
-  bool return_value_nc() { return value; }
+  constexpr bool return_value() const { return value; }
+  constexpr bool return_value_nc() { return value; }
   bool value;
 };
 
@@ -135,59 +135,60 @@ inline constexpr CallType operator|(CallType LHS, CallType RHS) {
 }
 
 struct ForwardingCallObject {
+  struct State {
+    CallType      last_call_type = CT_None;
+    TypeID const& (*last_call_args)() = nullptr;
+
+    template <class ...Args>
+    constexpr void set_call(CallType type) {
+      assert(last_call_type == CT_None);
+      assert(last_call_args == nullptr);
+      last_call_type = type;
+      last_call_args = &makeArgumentID<Args...>;
+    }
+
+    template <class ...Args>
+    constexpr bool check_call(CallType type) {
+      bool result =
+           last_call_type == type
+        && last_call_args
+        && *last_call_args == &makeArgumentID<Args...>;
+      last_call_type = CT_None;
+      last_call_args = nullptr;
+      return result;
+    }
+  };
+
+  State *st_;
+
+  explicit constexpr ForwardingCallObject(State& st) : st_(&st) {}
 
   template <class ...Args>
-  bool operator()(Args&&...) & {
-      set_call<Args&&...>(CT_NonConst | CT_LValue);
+  constexpr bool operator()(Args&&...) & {
+      st_->set_call<Args&&...>(CT_NonConst | CT_LValue);
       return true;
   }
 
   template <class ...Args>
-  bool operator()(Args&&...) const & {
-      set_call<Args&&...>(CT_Const | CT_LValue);
+  constexpr bool operator()(Args&&...) const & {
+      st_->set_call<Args&&...>(CT_Const | CT_LValue);
       return true;
   }
 
   // Don't allow the call operator to be invoked as an rvalue.
   template <class ...Args>
-  bool operator()(Args&&...) && {
-      set_call<Args&&...>(CT_NonConst | CT_RValue);
+  constexpr bool operator()(Args&&...) && {
+      st_->set_call<Args&&...>(CT_NonConst | CT_RValue);
       return true;
   }
 
   template <class ...Args>
-  bool operator()(Args&&...) const && {
-      set_call<Args&&...>(CT_Const | CT_RValue);
+  constexpr bool operator()(Args&&...) const && {
+      st_->set_call<Args&&...>(CT_Const | CT_RValue);
       return true;
   }
-
-  template <class ...Args>
-  static void set_call(CallType type) {
-      assert(last_call_type == CT_None);
-      assert(last_call_args == nullptr);
-      last_call_type = type;
-      last_call_args = &makeArgumentID<Args...>();
-  }
-
-  template <class ...Args>
-  static bool check_call(CallType type) {
-      bool result =
-           last_call_type == type
-        && last_call_args
-        && *last_call_args == makeArgumentID<Args...>();
-      last_call_type = CT_None;
-      last_call_args = nullptr;
-      return result;
-  }
-
-  static CallType      last_call_type;
-  static TypeID const* last_call_args;
 };
 
-CallType ForwardingCallObject::last_call_type = CT_None;
-TypeID const* ForwardingCallObject::last_call_args = nullptr;
-
-
 
 ///////////////////////////////////////////////////////////////////////////////
 //                        BOOL TEST TYPES
@@ -209,7 +210,7 @@ struct EvilBool {
   friend struct CopyCallable<EvilBool>;
   friend struct NoExceptCallable<EvilBool>;
 
-  explicit EvilBool(bool x) : value(x) {}
+  constexpr explicit EvilBool(bool x) : value(x) {}
   EvilBool& operator=(EvilBool const& other) = default;
 
 public:
@@ -222,14 +223,14 @@ struct ExplicitBool {
   ExplicitBool(ExplicitBool const&) = default;
   ExplicitBool(ExplicitBool&&) = default;
 
-  explicit operator bool() const { return value; }
+  constexpr explicit operator bool() const { return value; }
 
 private:
   friend struct MoveOnlyCallable<ExplicitBool>;
   friend struct CopyCallable<ExplicitBool>;
 
-  explicit ExplicitBool(bool x) : value(x) {}
-  ExplicitBool& operator=(bool x) {
+  constexpr explicit ExplicitBool(bool x) : value(x) {}
+  constexpr ExplicitBool& operator=(bool x) {
       value = x;
       return *this;
   }
@@ -243,7 +244,7 @@ struct NoExceptEvilBool {
   NoExceptEvilBool(NoExceptEvilBool&&) = default;
   NoExceptEvilBool& operator=(NoExceptEvilBool const& other) = default;
 
-  explicit NoExceptEvilBool(bool x) : value(x) {}
+  constexpr explicit NoExceptEvilBool(bool x) : value(x) {}
 
   friend NoExceptEvilBool operator!(NoExceptEvilBool const& other) noexcept {
     return NoExceptEvilBool{!other.value};
@@ -254,7 +255,8 @@ struct NoExceptEvilBool {
 
 
 
-void constructor_tests()
+TEST_CONSTEXPR_CXX20
+bool constructor_tests()
 {
     {
         using T = MoveOnlyCallable<bool>;
@@ -334,6 +336,7 @@ void constructor_tests()
         assert(ret() == true);
 #endif // _LIBCPP_VERSION
     }
+    return true;
 }
 
 void return_type_tests()
@@ -368,7 +371,8 @@ void return_type_tests()
 
 // Other tests only test using objects with call operators. Test various
 // other callable types here.
-void other_callable_types_test()
+TEST_CONSTEXPR_CXX20
+bool other_callable_types_test()
 {
     { // test with function pointer
         auto ret = std::not_fn(returns_true);
@@ -407,6 +411,7 @@ void other_callable_types_test()
         assert(ret(&mt) == false);
         assert(ret(&mf) == true);
     }
+    return true;
 }
 
 void throws_in_constructor_test()
@@ -438,7 +443,8 @@ void throws_in_constructor_test()
 #endif
 }
 
-void call_operator_sfinae_test() {
+TEST_CONSTEXPR_CXX20
+bool call_operator_sfinae_test() {
     { // wrong number of arguments
         using T = decltype(std::not_fn(returns_true));
         static_assert(std::is_invocable<T>::value, ""); // callable only with no args
@@ -462,94 +468,100 @@ void call_operator_sfinae_test() {
         static_assert(std::is_invocable<T, bool>::value, "");
         static_assert(!std::is_invocable<T, std::string>::value, "");
     }
+    return true;
 }
 
-void call_operator_forwarding_test()
+TEST_CONSTEXPR_CXX20
+bool call_operator_forwarding_test()
 {
     using Fn = ForwardingCallObject;
-    auto obj = std::not_fn(Fn{});
+    Fn::State st;
+    auto obj = std::not_fn(Fn{st});
     const auto& c_obj = obj;
     { // test zero args
         obj();
-        assert(Fn::check_call<>(CT_NonConst | CT_LValue));
+        assert(st.check_call<>(CT_NonConst | CT_LValue));
         std::move(obj)();
-        assert(Fn::check_call<>(CT_NonConst | CT_RValue));
+        assert(st.check_call<>(CT_NonConst | CT_RValue));
         c_obj();
-        assert(Fn::check_call<>(CT_Const | CT_LValue));
+        assert(st.check_call<>(CT_Const | CT_LValue));
         std::move(c_obj)();
-        assert(Fn::check_call<>(CT_Const | CT_RValue));
+        assert(st.check_call<>(CT_Const | CT_RValue));
     }
     { // test value categories
         int x = 42;
         const int cx = 42;
         obj(x);
-        assert(Fn::check_call<int&>(CT_NonConst | CT_LValue));
+        assert(st.check_call<int&>(CT_NonConst | CT_LValue));
         obj(cx);
-        assert(Fn::check_call<const int&>(CT_NonConst | CT_LValue));
+        assert(st.check_call<const int&>(CT_NonConst | CT_LValue));
         obj(std::move(x));
-        assert(Fn::check_call<int&&>(CT_NonConst | CT_LValue));
+        assert(st.check_call<int&&>(CT_NonConst | CT_LValue));
         obj(std::move(cx));
-        assert(Fn::check_call<const int&&>(CT_NonConst | CT_LValue));
+        assert(st.check_call<const int&&>(CT_NonConst | CT_LValue));
         obj(42);
-        assert(Fn::check_call<int&&>(CT_NonConst | CT_LValue));
+        assert(st.check_call<int&&>(CT_NonConst | CT_LValue));
     }
     { // test value categories - rvalue
         int x = 42;
         const int cx = 42;
         std::move(obj)(x);
-        assert(Fn::check_call<int&>(CT_NonConst | CT_RValue));
+        assert(st.check_call<int&>(CT_NonConst | CT_RValue));
         std::move(obj)(cx);
-        assert(Fn::check_call<const int&>(CT_NonConst | CT_RValue));
+        assert(st.check_call<const int&>(CT_NonConst | CT_RValue));
         std::move(obj)(std::move(x));
-        assert(Fn::check_call<int&&>(CT_NonConst | CT_RValue));
+        assert(st.check_call<int&&>(CT_NonConst | CT_RValue));
         std::move(obj)(std::move(cx));
-        assert(Fn::check_call<const int&&>(CT_NonConst | CT_RValue));
+        assert(st.check_call<const int&&>(CT_NonConst | CT_RValue));
         std::move(obj)(42);
-        assert(Fn::check_call<int&&>(CT_NonConst | CT_RValue));
+        assert(st.check_call<int&&>(CT_NonConst | CT_RValue));
     }
     { // test value categories - const call
         int x = 42;
         const int cx = 42;
         c_obj(x);
-        assert(Fn::check_call<int&>(CT_Const | CT_LValue));
+        assert(st.check_call<int&>(CT_Const | CT_LValue));
         c_obj(cx);
-        assert(Fn::check_call<const int&>(CT_Const | CT_LValue));
+        assert(st.check_call<const int&>(CT_Const | CT_LValue));
         c_obj(std::move(x));
-        assert(Fn::check_call<int&&>(CT_Const | CT_LValue));
+        assert(st.check_call<int&&>(CT_Const | CT_LValue));
         c_obj(std::move(cx));
-        assert(Fn::check_call<const int&&>(CT_Const | CT_LValue));
+        assert(st.check_call<const int&&>(CT_Const | CT_LValue));
         c_obj(42);
-        assert(Fn::check_call<int&&>(CT_Const | CT_LValue));
+        assert(st.check_call<int&&>(CT_Const | CT_LValue));
     }
     { // test value categories - const call rvalue
         int x = 42;
         const int cx = 42;
         std::move(c_obj)(x);
-        assert(Fn::check_call<int&>(CT_Const | CT_RValue));
+        assert(st.check_call<int&>(CT_Const | CT_RValue));
         std::move(c_obj)(cx);
-        assert(Fn::check_call<const int&>(CT_Const | CT_RValue));
+        assert(st.check_call<const int&>(CT_Const | CT_RValue));
         std::move(c_obj)(std::move(x));
-        assert(Fn::check_call<int&&>(CT_Const | CT_RValue));
+        assert(st.check_call<int&&>(CT_Const | CT_RValue));
         std::move(c_obj)(std::move(cx));
-        assert(Fn::check_call<const int&&>(CT_Const | CT_RValue));
+        assert(st.check_call<const int&&>(CT_Const | CT_RValue));
         std::move(c_obj)(42);
-        assert(Fn::check_call<int&&>(CT_Const | CT_RValue));
+        assert(st.check_call<int&&>(CT_Const | CT_RValue));
     }
     { // test multi arg
+        using String = const char *;
         const double y = 3.14;
-        std::string s = "abc";
-        obj(42, std::move(y), s, std::string{"foo"});
-        Fn::check_call<int&&, const double&&, std::string&, std::string&&>(CT_NonConst | CT_LValue);
-        std::move(obj)(42, std::move(y), s, std::string{"foo"});
-        Fn::check_call<int&&, const double&&, std::string&, std::string&&>(CT_NonConst | CT_RValue);
-        c_obj(42, std::move(y), s, std::string{"foo"});
-        Fn::check_call<int&&, const double&&, std::string&, std::string&&>(CT_Const  | CT_LValue);
-        std::move(c_obj)(42, std::move(y), s, std::string{"foo"});
-        Fn::check_call<int&&, const double&&, std::string&, std::string&&>(CT_Const  | CT_RValue);
+        String s = "abc";
+        obj(42, std::move(y), s, String{"foo"});
+        assert((st.check_call<int&&, const double&&, String&, String&&>(CT_NonConst | CT_LValue)));
+        std::move(obj)(42, std::move(y), s, String{"foo"});
+        assert((st.check_call<int&&, const double&&, String&, String&&>(CT_NonConst | CT_RValue)));
+        c_obj(42, std::move(y), s, String{"foo"});
+        assert((st.check_call<int&&, const double&&, String&, String&&>(CT_Const  | CT_LValue)));
+        std::move(c_obj)(42, std::move(y), s, String{"foo"});
+        assert((st.check_call<int&&, const double&&, String&, String&&>(CT_Const  | CT_RValue)));
     }
+    return true;
 }
 
-void call_operator_noexcept_test()
+TEST_CONSTEXPR_CXX20
+bool call_operator_noexcept_test()
 {
     {
         using T = ConstCallable<bool>;
@@ -587,19 +599,22 @@ void call_operator_noexcept_test()
         auto const& cret = ret;
         static_assert(!noexcept(cret()), "call should not be noexcept");
     }
+    return true;
 }
 
-void test_lwg2767() {
+TEST_CONSTEXPR_CXX20
+bool test_lwg2767() {
     // See https://cplusplus.github.io/LWG/lwg-defects.html#2767
     struct Abstract { virtual void f() const = 0; };
     struct Derived : public Abstract { void f() const {} };
-    struct F { bool operator()(Abstract&&) { return false; } };
+    struct F { constexpr bool operator()(Abstract&&) { return false; } };
     {
         Derived d;
         Abstract &a = d;
         bool b = std::not_fn(F{})(std::move(a));
         assert(b);
     }
+    return true;
 }
 
 int main(int, char**)
@@ -613,5 +628,14 @@ int main(int, char**)
     call_operator_noexcept_test();
     test_lwg2767();
 
-  return 0;
+#if TEST_STD_VER >= 20
+    static_assert(constructor_tests());
+    static_assert(other_callable_types_test());
+    static_assert(call_operator_sfinae_test()); // somewhat of an extension
+    static_assert(call_operator_forwarding_test());
+    static_assert(call_operator_noexcept_test());
+    static_assert(test_lwg2767());
+#endif
+
+    return 0;
 }
diff --git a/libcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pass.cpp b/libcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pass.cpp
index 04c2de6bda500..9c51b3ac39f30 100644
--- a/libcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pass.cpp
+++ b/libcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pass.cpp
@@ -39,14 +39,15 @@
 #include "test_iterators.h"
 
 template <typename Iter1, typename Iter2>
+TEST_CONSTEXPR_CXX20
 void do_search(Iter1 b1, Iter1 e1, Iter2 b2, Iter2 e2, Iter1 result) {
     std::default_searcher<Iter2> s{b2, e2};
     assert(result == std::search(b1, e1, s));
 }
 
 template <class Iter1, class Iter2>
-void
-test()
+TEST_CONSTEXPR_CXX20
+bool test()
 {
     int ia[] = {0, 1, 2, 3, 4, 5};
     const unsigned sa = sizeof(ia)/sizeof(ia[0]);
@@ -81,6 +82,8 @@ test()
     int ik[] = {0, 0, 0, 0, 1, 1, 1, 1, 0, 0};
     const unsigned sk = sizeof(ik)/sizeof(ik[0]);
     do_search(Iter1(ij), Iter1(ij+sj), Iter2(ik), Iter2(ik+sk), Iter1(ij+6));
+
+    return true;
 }
 
 int main(int, char**) {
@@ -94,5 +97,17 @@ int main(int, char**) {
     test<random_access_iterator<const int*>, bidirectional_iterator<const int*> >();
     test<random_access_iterator<const int*>, random_access_iterator<const int*> >();
 
-  return 0;
+#if TEST_STD_VER >= 20
+    static_assert(test<forward_iterator<const int*>, forward_iterator<const int*>>());
+    static_assert(test<forward_iterator<const int*>, bidirectional_iterator<const int*>>());
+    static_assert(test<forward_iterator<const int*>, random_access_iterator<const int*>>());
+    static_assert(test<bidirectional_iterator<const int*>, forward_iterator<const int*>>());
+    static_assert(test<bidirectional_iterator<const int*>, bidirectional_iterator<const int*>>());
+    static_assert(test<bidirectional_iterator<const int*>, random_access_iterator<const int*>>());
+    static_assert(test<random_access_iterator<const int*>, forward_iterator<const int*>>());
+    static_assert(test<random_access_iterator<const int*>, bidirectional_iterator<const int*>>());
+    static_assert(test<random_access_iterator<const int*>, random_access_iterator<const int*>>());
+#endif
+
+    return 0;
 }
diff --git a/libcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pred.pass.cpp b/libcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pred.pass.cpp
index 6f3bdb5dfbae4..bc9ba2f860b44 100644
--- a/libcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pred.pass.cpp
+++ b/libcxx/test/std/utilities/function.objects/func.search/func.search.default/default.pred.pass.cpp
@@ -40,54 +40,59 @@
 
 struct count_equal
 {
-    static unsigned count;
+    unsigned *count;
+
     template <class T>
-    bool operator()(const T& x, const T& y) const
-        {++count; return x == y;}
+    TEST_CONSTEXPR_CXX14 bool operator()(const T& x, const T& y) const
+        {++*count; return x == y;}
 };
 
-unsigned count_equal::count = 0;
-
 template <typename Iter1, typename Iter2>
-void do_search(Iter1 b1, Iter1 e1, Iter2 b2, Iter2 e2, Iter1 result, unsigned max_count) {
-    std::default_searcher<Iter2, count_equal> s{b2, e2};
-    count_equal::count = 0;
+TEST_CONSTEXPR_CXX20
+void do_search(Iter1 b1, Iter1 e1, Iter2 b2, Iter2 e2, Iter1 result) {
+    unsigned count = 0;
+    std::default_searcher<Iter2, count_equal> s{b2, e2, count_equal{&count}};
     assert(result == std::search(b1, e1, s));
-    assert(count_equal::count <= max_count);
+    auto d1 = std::distance(b1, e1);
+    auto d2 = std::distance(b2, e2);
+    assert((count >= 1) || (d2 == 0) || (d1 < d2));
+    assert((d1 < d2) || count <= d1 * (d1 - d2 + 1));
 }
 
 template <class Iter1, class Iter2>
-void
-test()
+TEST_CONSTEXPR_CXX20
+bool test()
 {
     int ia[] = {0, 1, 2, 3, 4, 5};
     const unsigned sa = sizeof(ia)/sizeof(ia[0]);
-    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia),      Iter2(ia),    Iter1(ia),      0);
-    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia),      Iter2(ia+1),  Iter1(ia),      sa);
-    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+1),    Iter2(ia+2),  Iter1(ia+1),    sa);
-    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+2),    Iter2(ia+2),  Iter1(ia),      0);
-    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+2),    Iter2(ia+3),  Iter1(ia+2),    sa);
-    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+2),    Iter2(ia+3),  Iter1(ia+2),    sa);
-    do_search(Iter1(ia), Iter1(ia),      Iter2(ia+2),    Iter2(ia+3),  Iter1(ia),      0);
-    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+sa-1), Iter2(ia+sa), Iter1(ia+sa-1), sa);
-    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+sa-3), Iter2(ia+sa), Iter1(ia+sa-3), 3*sa);
-    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia),      Iter2(ia+sa), Iter1(ia),      sa*sa);
-    do_search(Iter1(ia), Iter1(ia+sa-1), Iter2(ia),      Iter2(ia+sa), Iter1(ia+sa-1), (sa-1)*sa);
-    do_search(Iter1(ia), Iter1(ia+1),    Iter2(ia),      Iter2(ia+sa), Iter1(ia+1),    sa);
+    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia),      Iter2(ia),    Iter1(ia));
+    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia),      Iter2(ia+1),  Iter1(ia));
+    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+1),    Iter2(ia+2),  Iter1(ia+1));
+    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+2),    Iter2(ia+2),  Iter1(ia));
+    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+2),    Iter2(ia+3),  Iter1(ia+2));
+    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+2),    Iter2(ia+3),  Iter1(ia+2));
+    do_search(Iter1(ia), Iter1(ia),      Iter2(ia+2),    Iter2(ia+3),  Iter1(ia));
+    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+sa-1), Iter2(ia+sa), Iter1(ia+sa-1));
+    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia+sa-3), Iter2(ia+sa), Iter1(ia+sa-3));
+    do_search(Iter1(ia), Iter1(ia+sa),   Iter2(ia),      Iter2(ia+sa), Iter1(ia));
+    do_search(Iter1(ia), Iter1(ia+sa-1), Iter2(ia),      Iter2(ia+sa), Iter1(ia+sa-1));
+    do_search(Iter1(ia), Iter1(ia+1),    Iter2(ia),      Iter2(ia+sa), Iter1(ia+1));
     int ib[] = {0, 1, 2, 0, 1, 2, 3, 0, 1, 2, 3, 4};
     const unsigned sb = sizeof(ib)/sizeof(ib[0]);
     int ic[] = {1};
-    do_search(Iter1(ib), Iter1(ib+sb), Iter2(ic), Iter2(ic+1), Iter1(ib+1), sb);
+    do_search(Iter1(ib), Iter1(ib+sb), Iter2(ic), Iter2(ic+1), Iter1(ib+1));
     int id[] = {1, 2};
-    do_search(Iter1(ib), Iter1(ib+sb), Iter2(id), Iter2(id+2), Iter1(ib+1), sb*2);
+    do_search(Iter1(ib), Iter1(ib+sb), Iter2(id), Iter2(id+2), Iter1(ib+1));
     int ie[] = {1, 2, 3};
-    do_search(Iter1(ib), Iter1(ib+sb), Iter2(ie), Iter2(ie+3), Iter1(ib+4), sb*3);
+    do_search(Iter1(ib), Iter1(ib+sb), Iter2(ie), Iter2(ie+3), Iter1(ib+4));
     int ig[] = {1, 2, 3, 4};
-    do_search(Iter1(ib), Iter1(ib+sb), Iter2(ig), Iter2(ig+4), Iter1(ib+8), sb*4);
+    do_search(Iter1(ib), Iter1(ib+sb), Iter2(ig), Iter2(ig+4), Iter1(ib+8));
     int ih[] = {0, 1, 1, 1, 1, 2, 3, 0, 1, 2, 3, 4};
     const unsigned sh = sizeof(ih)/sizeof(ih[0]);
     int ii[] = {1, 1, 2};
-    do_search(Iter1(ih), Iter1(ih+sh), Iter2(ii), Iter2(ii+3), Iter1(ih+3),  sh*3);
+    do_search(Iter1(ih), Iter1(ih+sh), Iter2(ii), Iter2(ii+3), Iter1(ih+3));
+
+    return true;
 }
 
 int main(int, char**) {
@@ -101,5 +106,17 @@ int main(int, char**) {
     test<random_access_iterator<const int*>, bidirectional_iterator<const int*> >();
     test<random_access_iterator<const int*>, random_access_iterator<const int*> >();
 
-  return 0;
+#if TEST_STD_VER >= 20
+    static_assert(test<forward_iterator<const int*>, forward_iterator<const int*>>());
+    static_assert(test<forward_iterator<const int*>, bidirectional_iterator<const int*>>());
+    static_assert(test<forward_iterator<const int*>, random_access_iterator<const int*>>());
+    static_assert(test<bidirectional_iterator<const int*>, forward_iterator<const int*>>());
+    static_assert(test<bidirectional_iterator<const int*>, bidirectional_iterator<const int*>>());
+    static_assert(test<bidirectional_iterator<const int*>, random_access_iterator<const int*>>());
+    static_assert(test<random_access_iterator<const int*>, forward_iterator<const int*>>());
+    static_assert(test<random_access_iterator<const int*>, bidirectional_iterator<const int*>>());
+    static_assert(test<random_access_iterator<const int*>, random_access_iterator<const int*>>());
+#endif
+
+    return 0;
 }
diff --git a/libcxx/utils/generate_feature_test_macro_components.py b/libcxx/utils/generate_feature_test_macro_components.py
index 5010c080c759c..091fea431384c 100755
--- a/libcxx/utils/generate_feature_test_macro_components.py
+++ b/libcxx/utils/generate_feature_test_macro_components.py
@@ -369,10 +369,9 @@ def add_version_header(tc):
     "headers": ["algorithm"],
     "unimplemented": True,
   }, {
-    "name": "__cpp_lib_constexpr_misc",
-    "values": { "c++2a": int(201811) },
-    "headers": ["array", "functional", "iterator", "string_view", "tuple", "utility"],
-    "unimplemented": True,
+    "name": "__cpp_lib_constexpr_functional",
+    "values": { "c++2a": int(201907) },
+    "headers": ["functional"],
   }, {
     "name": "__cpp_lib_constexpr_numeric",
     "values": { "c++2a": int(201911) },
diff --git a/libcxx/utils/libcxx/test/features.py b/libcxx/utils/libcxx/test/features.py
index 3023caeea5d3e..a435a938fdcdc 100644
--- a/libcxx/utils/libcxx/test/features.py
+++ b/libcxx/utils/libcxx/test/features.py
@@ -55,7 +55,16 @@
             #include <atomic>
             struct Large { int storage[100]; };
             std::atomic<Large> x;
-            int main(int, char**) { return x.load(), x.is_lock_free(); }
+            int main(int, char**) { (void)x.load(); return 0; }
+          """)),
+  # TODO: Remove this feature once compiler-rt includes __atomic_is_lockfree()
+  # on all supported platforms.
+  Feature(name='is-lockfree-runtime-function',
+          when=lambda cfg: sourceBuilds(cfg, """
+            #include <atomic>
+            struct Large { int storage[100]; };
+            std::atomic<Large> x;
+            int main(int, char**) { return x.is_lock_free(); }
           """)),
 
   Feature(name='apple-clang',                                                                                                      when=_isAppleClang),
diff --git a/lld/COFF/Options.td b/lld/COFF/Options.td
index 2b8e65587ad7c..5447c83121288 100644
--- a/lld/COFF/Options.td
+++ b/lld/COFF/Options.td
@@ -240,7 +240,7 @@ def lto_obj_path : P<
     "lto-obj-path",
     "output native object for merged LTO unit to this path">;
 def dash_dash_version : Flag<["--"], "version">,
-  HelpText<"Print version information">;
+  HelpText<"Display the version number and exit">;
 def threads
     : P<"threads", "Number of threads. '1' disables multi-threading. By "
                    "default all available hardware threads are used">;
diff --git a/lld/ELF/InputFiles.h b/lld/ELF/InputFiles.h
index 8c898280b85c4..7ffe4c29cb878 100644
--- a/lld/ELF/InputFiles.h
+++ b/lld/ELF/InputFiles.h
@@ -130,6 +130,10 @@ class InputFile {
   // [.got, .got + 0xFFFC].
   bool ppc64SmallCodeModelTocRelocs = false;
 
+  // True if the file has TLSGD/TLSLD GOT relocations without R_PPC64_TLSGD or
+  // R_PPC64_TLSLD. Disable TLS relaxation to avoid bad code generation.
+  bool ppc64DisableTLSRelax = false;
+
   // groupId is used for --warn-backrefs which is an optional error
   // checking feature. All files within the same --{start,end}-group or
   // --{start,end}-lib get the same group ID. Otherwise, each file gets a new
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 18151c064c355..875ecf78ca2c7 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -208,9 +208,13 @@ handleTlsRelocation(RelType type, Symbol &sym, InputSectionBase &c,
     return 1;
   }
 
+  // ARM, Hexagon and RISC-V do not support GD/LD to IE/LE relaxation.  For
+  // PPC64, if the file has missing R_PPC64_TLSGD/R_PPC64_TLSLD, disable
+  // relaxation as well.
   bool toExecRelax = !config->shared && config->emachine != EM_ARM &&
                      config->emachine != EM_HEXAGON &&
-                     config->emachine != EM_RISCV;
+                     config->emachine != EM_RISCV &&
+                     !c.file->ppc64DisableTLSRelax;
 
   // If we are producing an executable and the symbol is non-preemptable, it
   // must be defined and the code sequence can be relaxed to use Local-Exec.
@@ -1396,10 +1400,17 @@ static void scanReloc(InputSectionBase &sec, OffsetGetter &getOffset, RelTy *&i,
     in.got->hasGotOffRel = true;
   }
 
-  // Process some TLS relocations, including relaxing TLS relocations.
-  // Note that this function does not handle all TLS relocations.
-  if (unsigned processed =
-          handleTlsRelocation<ELFT>(type, sym, sec, offset, addend, expr)) {
+  // Process TLS relocations, including relaxing TLS relocations. Note that
+  // R_TPREL and R_TPREL_NEG relocations are resolved in processRelocAux.
+  if (expr == R_TPREL || expr == R_TPREL_NEG) {
+    if (config->shared) {
+      errorOrWarn("relocation " + toString(type) + " against " + toString(sym) +
+                  " cannot be used with -shared" +
+                  getLocation(sec, sym, offset));
+      return;
+    }
+  } else if (unsigned processed = handleTlsRelocation<ELFT>(
+                 type, sym, sec, offset, addend, expr)) {
     i += (processed - 1);
     return;
   }
@@ -1527,6 +1538,43 @@ static void scanReloc(InputSectionBase &sec, OffsetGetter &getOffset, RelTy *&i,
   processRelocAux<ELFT>(sec, expr, type, offset, sym, rel, addend);
 }
 
+// R_PPC64_TLSGD/R_PPC64_TLSLD is required to mark `bl __tls_get_addr` for
+// General Dynamic/Local Dynamic code sequences. If a GD/LD GOT relocation is
+// found but no R_PPC64_TLSGD/R_PPC64_TLSLD is seen, we assume that the
+// instructions are generated by very old IBM XL compilers. Work around the
+// issue by disabling GD/LD to IE/LE relaxation.
+template <class RelTy>
+static void checkPPC64TLSRelax(InputSectionBase &sec, ArrayRef<RelTy> rels) {
+  // Skip if sec is synthetic (sec.file is null) or if sec has been marked.
+  if (!sec.file || sec.file->ppc64DisableTLSRelax)
+    return;
+  bool hasGDLD = false;
+  for (const RelTy &rel : rels) {
+    RelType type = rel.getType(false);
+    switch (type) {
+    case R_PPC64_TLSGD:
+    case R_PPC64_TLSLD:
+      return; // Found a marker
+    case R_PPC64_GOT_TLSGD16:
+    case R_PPC64_GOT_TLSGD16_HA:
+    case R_PPC64_GOT_TLSGD16_HI:
+    case R_PPC64_GOT_TLSGD16_LO:
+    case R_PPC64_GOT_TLSLD16:
+    case R_PPC64_GOT_TLSLD16_HA:
+    case R_PPC64_GOT_TLSLD16_HI:
+    case R_PPC64_GOT_TLSLD16_LO:
+      hasGDLD = true;
+      break;
+    }
+  }
+  if (hasGDLD) {
+    sec.file->ppc64DisableTLSRelax = true;
+    warn(toString(sec.file) +
+         ": disable TLS relaxation due to R_PPC64_GOT_TLS* relocations without "
+         "R_PPC64_TLSGD/R_PPC64_TLSLD relocations");
+  }
+}
+
 template <class ELFT, class RelTy>
 static void scanRelocs(InputSectionBase &sec, ArrayRef<RelTy> rels) {
   OffsetGetter getOffset(sec);
@@ -1534,6 +1582,9 @@ static void scanRelocs(InputSectionBase &sec, ArrayRef<RelTy> rels) {
   // Not all relocations end up in Sec.Relocations, but a lot do.
   sec.relocations.reserve(rels.size());
 
+  if (config->emachine == EM_PPC64)
+    checkPPC64TLSRelax<RelTy>(sec, rels);
+
   for (auto i = rels.begin(), end = rels.end(); i != end;)
     scanReloc<ELFT>(sec, getOffset, i, rels.begin(), end);
 
diff --git a/lld/MachO/Driver.cpp b/lld/MachO/Driver.cpp
index 9838e67cd4a29..9780443fb85a2 100644
--- a/lld/MachO/Driver.cpp
+++ b/lld/MachO/Driver.cpp
@@ -524,7 +524,7 @@ static void replaceCommonSymbols() {
 
     replaceSymbol<Defined>(sym, sym->getName(), isec, /*value=*/0,
                            /*isWeakDef=*/false,
-                           /*isExternal=*/true);
+                           /*isExternal=*/true, common->privateExtern);
   }
 }
 
@@ -548,20 +548,19 @@ static void handlePlatformVersion(const opt::Arg *arg) {
 
   // TODO(compnerd) see if we can generate this case list via XMACROS
   config->platform.kind =
-      llvm::StringSwitch<llvm::MachO::PlatformKind>(lowerDash(platformStr))
-          .Cases("macos", "1", llvm::MachO::PlatformKind::macOS)
-          .Cases("ios", "2", llvm::MachO::PlatformKind::iOS)
-          .Cases("tvos", "3", llvm::MachO::PlatformKind::tvOS)
-          .Cases("watchos", "4", llvm::MachO::PlatformKind::watchOS)
-          .Cases("bridgeos", "5", llvm::MachO::PlatformKind::bridgeOS)
-          .Cases("mac-catalyst", "6", llvm::MachO::PlatformKind::macCatalyst)
-          .Cases("ios-simulator", "7", llvm::MachO::PlatformKind::iOSSimulator)
-          .Cases("tvos-simulator", "8",
-                 llvm::MachO::PlatformKind::tvOSSimulator)
-          .Cases("watchos-simulator", "9",
-                 llvm::MachO::PlatformKind::watchOSSimulator)
-          .Default(llvm::MachO::PlatformKind::unknown);
-  if (config->platform.kind == llvm::MachO::PlatformKind::unknown)
+      StringSwitch<PlatformKind>(lowerDash(platformStr))
+          .Cases("macos", "1", PlatformKind::macOS)
+          .Cases("ios", "2", PlatformKind::iOS)
+          .Cases("tvos", "3", PlatformKind::tvOS)
+          .Cases("watchos", "4", PlatformKind::watchOS)
+          .Cases("bridgeos", "5", PlatformKind::bridgeOS)
+          .Cases("mac-catalyst", "6", PlatformKind::macCatalyst)
+          .Cases("ios-simulator", "7", PlatformKind::iOSSimulator)
+          .Cases("tvos-simulator", "8", PlatformKind::tvOSSimulator)
+          .Cases("watchos-simulator", "9", PlatformKind::watchOSSimulator)
+          .Cases("driverkit", "10", PlatformKind::driverKit)
+          .Default(PlatformKind::unknown);
+  if (config->platform.kind == PlatformKind::unknown)
     error(Twine("malformed platform: ") + platformStr);
   // TODO: check validity of version strings, which varies by platform
   // NOTE: ld64 accepts version strings with 5 components
@@ -637,10 +636,14 @@ static bool isPie(opt::InputArgList &args) {
   // to PIE from 10.7, arm64 should always be PIE, etc
   assert(config->arch == AK_x86_64 || config->arch == AK_x86_64h);
 
-  if (config->platform.kind == MachO::PlatformKind::macOS &&
+  PlatformKind kind = config->platform.kind;
+  if (kind == PlatformKind::macOS &&
       config->platform.minimum >= VersionTuple(10, 6))
     return true;
 
+  if (kind == PlatformKind::iOSSimulator || kind == PlatformKind::driverKit)
+    return true;
+
   return args.hasArg(OPT_pie);
 }
 
@@ -690,10 +693,15 @@ bool macho::link(llvm::ArrayRef<const char *> argsArr, bool canExitEarly,
   if (args.hasArg(OPT_help_hidden)) {
     parser.printHelp(argsArr[0], /*showHidden=*/true);
     return true;
-  } else if (args.hasArg(OPT_help)) {
+  }
+  if (args.hasArg(OPT_help)) {
     parser.printHelp(argsArr[0], /*showHidden=*/false);
     return true;
   }
+  if (args.hasArg(OPT_version)) {
+    message(getLLDVersion());
+    return true;
+  }
 
   if (const char *path = getReproduceOption(args)) {
     // Note that --reproduce is a debug option so you can ignore it
diff --git a/lld/MachO/InputFiles.cpp b/lld/MachO/InputFiles.cpp
index 3a4466dd123a7..e2282f1fb2bb2 100644
--- a/lld/MachO/InputFiles.cpp
+++ b/lld/MachO/InputFiles.cpp
@@ -280,22 +280,33 @@ void ObjFile::parseRelocations(const section_64 &sec,
 static macho::Symbol *createDefined(const structs::nlist_64 &sym,
                                     StringRef name, InputSection *isec,
                                     uint32_t value) {
-  if (sym.n_type & N_EXT)
-    // Global defined symbol
-    return symtab->addDefined(name, isec, value, sym.n_desc & N_WEAK_DEF);
-  // Local defined symbol
+  // Symbol scope is determined by sym.n_type & (N_EXT | N_PEXT):
+  // N_EXT: Global symbols
+  // N_EXT | N_PEXT: Linkage unit (think: dylib) scoped
+  // N_PEXT: Does not occur in input files in practice,
+  //         a private extern must be external.
+  // 0: Translation-unit scoped. These are not in the symbol table.
+
+  if (sym.n_type & (N_EXT | N_PEXT)) {
+    assert((sym.n_type & N_EXT) && "invalid input");
+    return symtab->addDefined(name, isec, value, sym.n_desc & N_WEAK_DEF,
+                              sym.n_type & N_PEXT);
+  }
   return make<Defined>(name, isec, value, sym.n_desc & N_WEAK_DEF,
-                       /*isExternal=*/false);
+                       /*isExternal=*/false, /*isPrivateExtern=*/false);
 }
 
 // Absolute symbols are defined symbols that do not have an associated
 // InputSection. They cannot be weak.
 static macho::Symbol *createAbsolute(const structs::nlist_64 &sym,
                                      StringRef name) {
-  if (sym.n_type & N_EXT)
-    return symtab->addDefined(name, nullptr, sym.n_value, /*isWeakDef=*/false);
+  if (sym.n_type & (N_EXT | N_PEXT)) {
+    assert((sym.n_type & N_EXT) && "invalid input");
+    return symtab->addDefined(name, nullptr, sym.n_value, /*isWeakDef=*/false,
+                              sym.n_type & N_PEXT);
+  }
   return make<Defined>(name, nullptr, sym.n_value, /*isWeakDef=*/false,
-                       /*isExternal=*/false);
+                       /*isExternal=*/false, /*isPrivateExtern=*/false);
 }
 
 macho::Symbol *ObjFile::parseNonSectionSymbol(const structs::nlist_64 &sym,
@@ -306,7 +317,8 @@ macho::Symbol *ObjFile::parseNonSectionSymbol(const structs::nlist_64 &sym,
     return sym.n_value == 0
                ? symtab->addUndefined(name, sym.n_desc & N_WEAK_REF)
                : symtab->addCommon(name, this, sym.n_value,
-                                   1 << GET_COMM_ALIGN(sym.n_desc));
+                                   1 << GET_COMM_ALIGN(sym.n_desc),
+                                   sym.n_type & N_PEXT);
   case N_ABS:
     return createAbsolute(sym, name);
   case N_PBUD:
diff --git a/lld/MachO/Options.td b/lld/MachO/Options.td
index 1ab2f9109ee06..8e88c74efc0e9 100644
--- a/lld/MachO/Options.td
+++ b/lld/MachO/Options.td
@@ -18,6 +18,8 @@ def reproduce: Separate<["--"], "reproduce">;
 def reproduce_eq: Joined<["--"], "reproduce=">,
     Alias<!cast<Separate>(reproduce)>,
     HelpText<"Write tar file containing inputs and command to reproduce link">;
+def version: Flag<["--"], "version">,
+    HelpText<"Display the version number and exit">;
 
 
 // This is a complete Options.td compiled from Apple's ld(1) manpage
@@ -346,7 +348,7 @@ def bundle_loader : Separate<["-"], "bundle_loader">,
 def grp_object : OptionGroup<"object">, HelpText<"CREATING AN OBJECT FILE">;
 
 def keep_private_externs : Flag<["-"], "keep_private_externs">,
-     HelpText<"Do not convert private external symbols to static symbols">,
+     HelpText<"Do not convert private external symbols to static symbols (only valid with -r)">,
      Flags<[HelpHidden]>,
      Group<grp_object>;
 def d : Flag<["-"], "d">,
@@ -508,7 +510,7 @@ def bitcode_symbol_map : Separate<["-"], "bitcode_symbol_map">,
 def grp_rare : OptionGroup<"rare">, HelpText<"RARELY USED">;
 
 def v : Flag<["-"], "v">,
-     HelpText<"Print the linker version">,
+     HelpText<"Print the linker version and search paths and exit">,
      Group<grp_rare>;
 def version_details : Flag<["-"], "version_details">,
      HelpText<"Print the linker version in JSON form">,
diff --git a/lld/MachO/SymbolTable.cpp b/lld/MachO/SymbolTable.cpp
index ea231c9786e26..8a490083ebf1b 100644
--- a/lld/MachO/SymbolTable.cpp
+++ b/lld/MachO/SymbolTable.cpp
@@ -38,7 +38,8 @@ std::pair<Symbol *, bool> SymbolTable::insert(StringRef name) {
 }
 
 Symbol *SymbolTable::addDefined(StringRef name, InputSection *isec,
-                                uint32_t value, bool isWeakDef) {
+                                uint32_t value, bool isWeakDef,
+                                bool isPrivateExtern) {
   Symbol *s;
   bool wasInserted;
   bool overridesWeakDef = false;
@@ -46,8 +47,13 @@ Symbol *SymbolTable::addDefined(StringRef name, InputSection *isec,
 
   if (!wasInserted) {
     if (auto *defined = dyn_cast<Defined>(s)) {
-      if (isWeakDef)
+      if (isWeakDef) {
+        // Both old and new symbol weak (e.g. inline function in two TUs):
+        // If one of them isn't private extern, the merged symbol isn't.
+        if (defined->isWeakDef())
+          defined->privateExtern &= isPrivateExtern;
         return s;
+      }
       if (!defined->isWeakDef())
         error("duplicate symbol: " + name);
     } else if (auto *dysym = dyn_cast<DylibSymbol>(s)) {
@@ -57,8 +63,9 @@ Symbol *SymbolTable::addDefined(StringRef name, InputSection *isec,
     // of a name conflict, we fall through to the replaceSymbol() call below.
   }
 
-  Defined *defined = replaceSymbol<Defined>(s, name, isec, value, isWeakDef,
-                                            /*isExternal=*/true);
+  Defined *defined =
+      replaceSymbol<Defined>(s, name, isec, value, isWeakDef,
+                             /*isExternal=*/true, isPrivateExtern);
   defined->overridesWeakDef = overridesWeakDef;
   return s;
 }
@@ -82,7 +89,7 @@ Symbol *SymbolTable::addUndefined(StringRef name, bool isWeakRef) {
 }
 
 Symbol *SymbolTable::addCommon(StringRef name, InputFile *file, uint64_t size,
-                               uint32_t align) {
+                               uint32_t align, bool isPrivateExtern) {
   Symbol *s;
   bool wasInserted;
   std::tie(s, wasInserted) = insert(name);
@@ -98,7 +105,7 @@ Symbol *SymbolTable::addCommon(StringRef name, InputFile *file, uint64_t size,
     // a name conflict, we fall through to the replaceSymbol() call below.
   }
 
-  replaceSymbol<CommonSymbol>(s, name, file, size, align);
+  replaceSymbol<CommonSymbol>(s, name, file, size, align, isPrivateExtern);
   return s;
 }
 
diff --git a/lld/MachO/SymbolTable.h b/lld/MachO/SymbolTable.h
index 89c866594d725..871687f75eb7c 100644
--- a/lld/MachO/SymbolTable.h
+++ b/lld/MachO/SymbolTable.h
@@ -33,11 +33,12 @@ class Symbol;
 class SymbolTable {
 public:
   Symbol *addDefined(StringRef name, InputSection *isec, uint32_t value,
-                     bool isWeakDef);
+                     bool isWeakDef, bool isPrivateExtern);
 
   Symbol *addUndefined(StringRef name, bool isWeakRef);
 
-  Symbol *addCommon(StringRef name, InputFile *, uint64_t size, uint32_t align);
+  Symbol *addCommon(StringRef name, InputFile *, uint64_t size, uint32_t align,
+                    bool isPrivateExtern);
 
   Symbol *addDylib(StringRef name, DylibFile *file, bool isWeakDef, bool isTlv);
 
diff --git a/lld/MachO/Symbols.h b/lld/MachO/Symbols.h
index 80be27dd1c1fc..7f987c722a1fa 100644
--- a/lld/MachO/Symbols.h
+++ b/lld/MachO/Symbols.h
@@ -47,7 +47,11 @@ class Symbol {
 
   Kind kind() const { return static_cast<Kind>(symbolKind); }
 
-  StringRef getName() const { return {name.data, name.size}; }
+  StringRef getName() const {
+    if (nameSize == (uint32_t)-1)
+      nameSize = strlen(nameData);
+    return {nameData, nameSize};
+  }
 
   virtual uint64_t getVA() const { return 0; }
 
@@ -80,20 +84,26 @@ class Symbol {
   uint32_t symtabIndex = UINT32_MAX;
 
 protected:
-  Symbol(Kind k, StringRefZ name) : symbolKind(k), name(name) {}
+  Symbol(Kind k, StringRefZ name)
+      : symbolKind(k), nameData(name.data), nameSize(name.size) {}
 
   Kind symbolKind;
-  StringRefZ name;
+  const char *nameData;
+  mutable uint32_t nameSize;
 };
 
 class Defined : public Symbol {
 public:
   Defined(StringRefZ name, InputSection *isec, uint32_t value, bool isWeakDef,
-          bool isExternal)
+          bool isExternal, bool isPrivateExtern)
       : Symbol(DefinedKind, name), isec(isec), value(value),
-        overridesWeakDef(false), weakDef(isWeakDef), external(isExternal) {}
+        overridesWeakDef(false), privateExtern(isPrivateExtern),
+        weakDef(isWeakDef), external(isExternal) {}
 
   bool isWeakDef() const override { return weakDef; }
+  bool isExternalWeakDef() const {
+    return isWeakDef() && isExternal() && !privateExtern;
+  }
   bool isTlv() const override {
     return !isAbsolute() && isThreadLocalVariables(isec->flags);
   }
@@ -110,6 +120,7 @@ class Defined : public Symbol {
   uint32_t value;
 
   bool overridesWeakDef : 1;
+  bool privateExtern : 1;
 
 private:
   const bool weakDef : 1;
@@ -148,14 +159,17 @@ class Undefined : public Symbol {
 //
 // The compiler creates common symbols when it sees tentative definitions.
 // (You can suppress this behavior and let the compiler create a regular
-// defined symbol by passing -fno-common.) When linking the final binary, if
-// there are remaining common symbols after name resolution is complete, the
-// linker converts them to regular defined symbols in a __common section.
+// defined symbol by passing -fno-common. -fno-common is the default in clang
+// as of LLVM 11.0.) When linking the final binary, if there are remaining
+// common symbols after name resolution is complete, the linker converts them
+// to regular defined symbols in a __common section.
 class CommonSymbol : public Symbol {
 public:
-  CommonSymbol(StringRefZ name, InputFile *file, uint64_t size, uint32_t align)
+  CommonSymbol(StringRefZ name, InputFile *file, uint64_t size, uint32_t align,
+               bool isPrivateExtern)
       : Symbol(CommonKind, name), file(file), size(size),
-        align(align != 1 ? align : llvm::PowerOf2Ceil(size)) {
+        align(align != 1 ? align : llvm::PowerOf2Ceil(size)),
+        privateExtern(isPrivateExtern) {
     // TODO: cap maximum alignment
   }
 
@@ -164,6 +178,7 @@ class CommonSymbol : public Symbol {
   InputFile *const file;
   const uint64_t size;
   const uint32_t align;
+  const bool privateExtern;
 };
 
 class DylibSymbol : public Symbol {
diff --git a/lld/MachO/SyntheticSections.cpp b/lld/MachO/SyntheticSections.cpp
index 433e6aac02595..2ed1f2eb34fbe 100644
--- a/lld/MachO/SyntheticSections.cpp
+++ b/lld/MachO/SyntheticSections.cpp
@@ -362,12 +362,10 @@ void WeakBindingSection::writeTo(uint8_t *buf) const {
 }
 
 bool macho::needsBinding(const Symbol *sym) {
-  if (isa<DylibSymbol>(sym)) {
+  if (isa<DylibSymbol>(sym))
     return true;
-  } else if (const auto *defined = dyn_cast<Defined>(sym)) {
-    if (defined->isWeakDef() && defined->isExternal())
-      return true;
-  }
+  if (const auto *defined = dyn_cast<Defined>(sym))
+    return defined->isExternalWeakDef();
   return false;
 }
 
@@ -380,7 +378,7 @@ void macho::addNonLazyBindingEntries(const Symbol *sym,
       in.weakBinding->addEntry(sym, section, offset, addend);
   } else if (auto *defined = dyn_cast<Defined>(sym)) {
     in.rebase->addEntry(section, offset);
-    if (defined->isWeakDef() && defined->isExternal())
+    if (defined->isExternalWeakDef())
       in.weakBinding->addEntry(sym, section, offset, addend);
   } else if (isa<DSOHandle>(sym)) {
     error("cannot bind to " + DSOHandle::name);
@@ -446,8 +444,10 @@ void StubHelperSection::setup() {
   in.got->addEntry(stubBinder);
 
   inputSections.push_back(in.imageLoaderCache);
-  symtab->addDefined("__dyld_private", in.imageLoaderCache, 0,
-                     /*isWeakDef=*/false);
+  dyldPrivate =
+      make<Defined>("__dyld_private", in.imageLoaderCache, 0,
+                    /*isWeakDef=*/false,
+                    /*isExternal=*/false, /*isPrivateExtern=*/false);
 }
 
 ImageLoaderCacheSection::ImageLoaderCacheSection() {
@@ -555,7 +555,7 @@ void macho::prepareBranchTarget(Symbol *sym) {
       }
     }
   } else if (auto *defined = dyn_cast<Defined>(sym)) {
-    if (defined->isWeakDef() && defined->isExternal()) {
+    if (defined->isExternalWeakDef()) {
       if (in.stubs->addEntry(sym)) {
         in.rebase->addEntry(in.lazyPointers, sym->stubsIndex * WordSize);
         in.weakBinding->addEntry(sym, in.lazyPointers,
@@ -570,9 +570,10 @@ ExportSection::ExportSection()
 
 void ExportSection::finalizeContents() {
   trieBuilder.setImageBase(in.header->addr);
-  // TODO: We should check symbol visibility.
   for (const Symbol *sym : symtab->getSymbols()) {
     if (const auto *defined = dyn_cast<Defined>(sym)) {
+      if (defined->privateExtern)
+        continue;
       trieBuilder.addSymbol(*defined);
       hasWeakSymbol = hasWeakSymbol || sym->isWeakDef();
     }
@@ -693,6 +694,11 @@ void SymtabSection::emitStabs() {
 }
 
 void SymtabSection::finalizeContents() {
+  auto addSymbol = [&](std::vector<SymtabEntry> &symbols, Symbol *sym) {
+    uint32_t strx = stringTableSection.addString(sym->getName());
+    symbols.push_back({sym, strx});
+  };
+
   // Local symbols aren't in the SymbolTable, so we walk the list of object
   // files to gather them.
   for (InputFile *file : inputFiles) {
@@ -701,23 +707,25 @@ void SymtabSection::finalizeContents() {
         // TODO: when we implement -dead_strip, we should filter out symbols
         // that belong to dead sections.
         if (auto *defined = dyn_cast<Defined>(sym)) {
-          if (!defined->isExternal()) {
-            uint32_t strx = stringTableSection.addString(sym->getName());
-            localSymbols.push_back({sym, strx});
-          }
+          if (!defined->isExternal())
+            addSymbol(localSymbols, sym);
         }
       }
     }
   }
 
+  // __dyld_private is a local symbol too. It's linker-created and doesn't
+  // exist in any object file.
+  if (Defined* dyldPrivate = in.stubHelper->dyldPrivate)
+    addSymbol(localSymbols, dyldPrivate);
+
   for (Symbol *sym : symtab->getSymbols()) {
-    uint32_t strx = stringTableSection.addString(sym->getName());
     if (auto *defined = dyn_cast<Defined>(sym)) {
       assert(defined->isExternal());
-      externalSymbols.push_back({sym, strx});
+      addSymbol(externalSymbols, sym);
     } else if (auto *dysym = dyn_cast<DylibSymbol>(sym)) {
       if (dysym->isReferenced())
-        undefinedSymbols.push_back({sym, strx});
+        addSymbol(undefinedSymbols, sym);
     }
   }
 
@@ -752,18 +760,31 @@ void SymtabSection::writeTo(uint8_t *buf) const {
     nList->n_strx = entry.strx;
     // TODO populate n_desc with more flags
     if (auto *defined = dyn_cast<Defined>(entry.sym)) {
+      uint8_t scope = 0;
+      if (defined->privateExtern) {
+        // Private external -- dylib scoped symbol.
+        // Promote to non-external at link time.
+        assert(defined->isExternal() && "invalid input file");
+        scope = MachO::N_PEXT;
+      } else if (defined->isExternal()) {
+        // Normal global symbol.
+        scope = MachO::N_EXT;
+      } else {
+        // TU-local symbol from localSymbols.
+        scope = 0;
+      }
+
       if (defined->isAbsolute()) {
-        nList->n_type = MachO::N_EXT | MachO::N_ABS;
+        nList->n_type = scope | MachO::N_ABS;
         nList->n_sect = MachO::NO_SECT;
         nList->n_value = defined->value;
       } else {
-        nList->n_type =
-            (defined->isExternal() ? MachO::N_EXT : 0) | MachO::N_SECT;
+        nList->n_type = scope | MachO::N_SECT;
         nList->n_sect = defined->isec->parent->index;
         // For the N_SECT symbol type, n_value is the address of the symbol
         nList->n_value = defined->getVA();
       }
-      nList->n_desc |= defined->isWeakDef() ? MachO::N_WEAK_DEF : 0;
+      nList->n_desc |= defined->isExternalWeakDef() ? MachO::N_WEAK_DEF : 0;
     } else if (auto *dysym = dyn_cast<DylibSymbol>(entry.sym)) {
       uint16_t n_desc = nList->n_desc;
       MachO::SET_LIBRARY_ORDINAL(n_desc, dysym->file->ordinal);
diff --git a/lld/MachO/SyntheticSections.h b/lld/MachO/SyntheticSections.h
index 9384df6481f05..7bca28de13869 100644
--- a/lld/MachO/SyntheticSections.h
+++ b/lld/MachO/SyntheticSections.h
@@ -327,6 +327,7 @@ class StubHelperSection : public SyntheticSection {
   void setup();
 
   DylibSymbol *stubBinder = nullptr;
+  Defined *dyldPrivate = nullptr;
 };
 
 // This section contains space for just a single word, and will be used by dyld
diff --git a/lld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp b/lld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp
index 42ac711bc9dc3..ddfd1764f7e18 100644
--- a/lld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp
+++ b/lld/lib/ReaderWriter/MachO/MachONormalizedFileFromAtoms.cpp
@@ -1561,7 +1561,7 @@ void Util::addExportInfo(const lld::File &atomFile, NormalizedFile &nFile) {
 uint32_t Util::fileFlags() {
   // FIXME: these need to determined at runtime.
   if (_ctx.outputMachOType() == MH_OBJECT) {
-    return _subsectionsViaSymbols ? MH_SUBSECTIONS_VIA_SYMBOLS : 0;
+    return _subsectionsViaSymbols ? (uint32_t)MH_SUBSECTIONS_VIA_SYMBOLS : 0;
   } else {
     uint32_t flags = MH_DYLDLINK;
     if (!_ctx.useFlatNamespace())
diff --git a/lld/test/ELF/Inputs/i386-static-tls-model4.s b/lld/test/ELF/Inputs/i386-static-tls-model4.s
deleted file mode 100644
index 6006518bfd7ce..0000000000000
--- a/lld/test/ELF/Inputs/i386-static-tls-model4.s
+++ /dev/null
@@ -1,9 +0,0 @@
-.section ".tdata", "awT", @progbits
-.globl var
-var:
-
-.section .foo, "aw"
-.global _start
-_start:
- movl %gs:0, %eax
- leal var@ntpoff(%eax), %eax # R_386_TLS_LE
diff --git a/lld/test/ELF/aarch64-tls-le.s b/lld/test/ELF/aarch64-tls-le.s
index e63a379fcc45e..c43345e8e254f 100644
--- a/lld/test/ELF/aarch64-tls-le.s
+++ b/lld/test/ELF/aarch64-tls-le.s
@@ -8,6 +8,14 @@
 #RELOC:      Relocations [
 #RELOC-NEXT: ]
 
+## Reject local-exec TLS relocations for -shared.
+# RUN: not ld.lld -shared %tmain.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR --implicit-check-not=error:
+
+# ERR: error: relocation R_AARCH64_TLSLE_ADD_TPREL_HI12 against v1 cannot be used with -shared
+# ERR: error: relocation R_AARCH64_TLSLE_ADD_TPREL_LO12_NC against v1 cannot be used with -shared
+# ERR: error: relocation R_AARCH64_TLSLE_ADD_TPREL_HI12 against v2 cannot be used with -shared
+# ERR: error: relocation R_AARCH64_TLSLE_ADD_TPREL_LO12_NC against v2 cannot be used with -shared
+
 .globl _start
 _start:
  mrs x0, TPIDR_EL0
diff --git a/lld/test/ELF/arm-tls-le32.s b/lld/test/ELF/arm-tls-le32.s
index 739752209db44..49469c2b6bfa6 100644
--- a/lld/test/ELF/arm-tls-le32.s
+++ b/lld/test/ELF/arm-tls-le32.s
@@ -8,6 +8,13 @@
 /// statically for an application. The code sequences assume a thread pointer
 /// in r9
 
+/// Reject local-exec TLS relocations for -shared.
+// RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR --implicit-check-not=error:
+
+// ERR: error: relocation R_ARM_TLS_LE32 against x cannot be used with -shared
+// ERR: error: relocation R_ARM_TLS_LE32 against y cannot be used with -shared
+// ERR: error: relocation R_ARM_TLS_LE32 against z cannot be used with -shared
+
  .text
  .syntax unified
  .globl  _start
diff --git a/lld/test/ELF/i386-static-tls-model.s b/lld/test/ELF/i386-static-tls-model.s
index cfd7cf6ba9722..dfbbed25ef228 100644
--- a/lld/test/ELF/i386-static-tls-model.s
+++ b/lld/test/ELF/i386-static-tls-model.s
@@ -1,9 +1,5 @@
 # REQUIRES: x86
 
-# RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %S/Inputs/i386-static-tls-model1.s -o %t.o
-# RUN: ld.lld %t.o -o %t1 -shared
-# RUN: llvm-readobj --dynamic-table %t1 | FileCheck %s
-
 # RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %S/Inputs/i386-static-tls-model2.s -o %t.o
 # RUN: ld.lld %t.o -o %t2 -shared
 # RUN: llvm-readobj --dynamic-table %t2 | FileCheck %s
@@ -12,9 +8,5 @@
 # RUN: ld.lld %t.o -o %t3 -shared
 # RUN: llvm-readobj --dynamic-table %t3 | FileCheck %s
 
-# RUN: llvm-mc -filetype=obj -triple=i686-pc-linux %S/Inputs/i386-static-tls-model4.s -o %t.o
-# RUN: ld.lld %t.o -o %t4 -shared
-# RUN: llvm-readobj --dynamic-table %t4 | FileCheck %s
-
 # CHECK: DynamicSection [
 # CHECK: FLAGS STATIC_TLS
diff --git a/lld/test/ELF/i386-tls-le.s b/lld/test/ELF/i386-tls-le.s
index b94ffbb67f07e..bcb4a8e21abca 100644
--- a/lld/test/ELF/i386-tls-le.s
+++ b/lld/test/ELF/i386-tls-le.s
@@ -1,11 +1,19 @@
 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=i686 %s -o %t.o
 # RUN: ld.lld %t.o -o %t
-# RUN: ld.lld %t.o -shared -o %t.so
+# RUN: ld.lld %t.o -pie -o %t.pie
 # RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s --check-prefix=DIS
 # RUN: llvm-readobj -r %t | FileCheck %s --check-prefix=RELOC
-# RUN: llvm-objdump -d --no-show-raw-insn %t.so | FileCheck %s --check-prefix=DISSHARED
-# RUN: llvm-readobj -r %t.so | FileCheck %s --check-prefix=RELOCSHARED
+# RUN: llvm-objdump -d --no-show-raw-insn %t.pie | FileCheck %s --check-prefix=DIS
+# RUN: llvm-readobj -r %t.pie | FileCheck %s --check-prefix=RELOC
+
+## Reject local-exec TLS relocations for -shared.
+# RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR --implicit-check-not=error:
+
+# ERR: error: relocation R_386_TLS_LE_32 against var cannot be used with -shared
+# ERR: error: relocation R_386_TLS_LE_32 against var1 cannot be used with -shared
+# ERR: error: relocation R_386_TLS_LE against var cannot be used with -shared
+# ERR: error: relocation R_386_TLS_LE against var1 cannot be used with -shared
 
 .section ".tdata", "awT", @progbits
 .globl var
@@ -33,39 +41,16 @@ _start:
 # DIS:      Disassembly of section test:
 # DIS-EMPTY:
 # DIS-NEXT: <_start>:
-# DIS-NEXT: 402134:       movl    $8, %edx
-# DIS-NEXT: 402139:       movl    %gs:0, %ecx
-# DIS-NEXT: 402140:       subl    %edx, %eax
-# DIS-NEXT: 402142:       movl    $4, %edx
-# DIS-NEXT: 402147:       movl    %gs:0, %ecx
-# DIS-NEXT: 40214e:       subl    %edx, %eax
-# DIS-NEXT: 402150:       movl    %gs:0, %ecx
-# DIS-NEXT: 402157:       leal    -8(%ecx), %eax
-# DIS-NEXT: 40215d:       movl    %gs:0, %ecx
-# DIS-NEXT: 402164:       leal    119(%ecx), %eax
+# DIS-NEXT:   movl    $8, %edx
+# DIS-NEXT:   movl    %gs:0, %ecx
+# DIS-NEXT:   subl    %edx, %eax
+# DIS-NEXT:   movl    $4, %edx
+# DIS-NEXT:   movl    %gs:0, %ecx
+# DIS-NEXT:   subl    %edx, %eax
+# DIS-NEXT:   movl    %gs:0, %ecx
+# DIS-NEXT:   leal    -8(%ecx), %eax
+# DIS-NEXT:   movl    %gs:0, %ecx
+# DIS-NEXT:   leal    119(%ecx), %eax
 
 # RELOC: Relocations [
 # RELOC-NEXT: ]
-
-# DISSHARED: Disassembly of section test:
-# DISSHARED-EMPTY:
-# DISSHARED-NEXT: <_start>:
-# DISSHARED-NEXT: 2218:       movl    $0, %edx
-# DISSHARED-NEXT: 221d:       movl    %gs:0, %ecx
-# DISSHARED-NEXT: 2224:       subl    %edx, %eax
-# DISSHARED-NEXT: 2226:       movl    $0, %edx
-# DISSHARED-NEXT: 222b:       movl    %gs:0, %ecx
-# DISSHARED-NEXT: 2232:       subl    %edx, %eax
-# DISSHARED-NEXT: 2234:       movl    %gs:0, %ecx
-# DISSHARED-NEXT: 223b:       leal    (%ecx), %eax
-# DISSHARED-NEXT: 2241:       movl    %gs:0, %ecx
-# DISSHARED-NEXT: 2248:       leal    123(%ecx), %eax
-
-# RELOCSHARED:      Relocations [
-# RELOCSHARED-NEXT: Section (5) .rel.dyn {
-# RELOCSHARED-NEXT:   0x2219 R_386_TLS_TPOFF32 var
-# RELOCSHARED-NEXT:   0x223D R_386_TLS_TPOFF var
-# RELOCSHARED-NEXT:   0x2227 R_386_TLS_TPOFF32 var1
-# RELOCSHARED-NEXT:   0x224A R_386_TLS_TPOFF var1
-# RELOCSHARED-NEXT:  }
-# RELOCSHARED-NEXT: ]
diff --git a/lld/test/ELF/i386-zrel-zrela.s b/lld/test/ELF/i386-zrel-zrela.s
index 27ff3bcab9a53..5e73ca2035241 100644
--- a/lld/test/ELF/i386-zrel-zrela.s
+++ b/lld/test/ELF/i386-zrel-zrela.s
@@ -27,7 +27,7 @@
 # REL-NEXT: }
 
 # REL:      Hex dump of section '.data':
-# REL-NEXT: 0x000042cc cc420000 2a000000
+# REL-NEXT: 0x000042d0 d0420000 2a000000
 
 # RUN: ld.lld -shared -z rel -z rela %t.o -o %t2.so
 # RUN: llvm-readobj -d -r %t2.so | FileCheck --check-prefix=RELA %s
@@ -41,9 +41,9 @@
 # RELA-NEXT: PLTGOT    {{.*}}
 # RELA-NEXT: PLTREL    RELA
 # RELA:      .rela.dyn {
-# RELA-NEXT:   R_386_RELATIVE - 0x42EC
+# RELA-NEXT:   R_386_RELATIVE - 0x42F0
 # RELA-NEXT:   R_386_GLOB_DAT func 0x0
-# RELA-NEXT:   R_386_TLS_TPOFF tls 0x2A
+# RELA-NEXT:   R_386_TLS_TPOFF tls 0x0
 # RELA-NEXT:   R_386_32 _start 0x2A
 # RELA-NEXT: }
 # RELA-NEXT: .rela.plt {
@@ -56,7 +56,7 @@ _start:
   movl func@GOT(%eax), %eax
 
 .section .text1,"awx"
-  movl %gs:tls@NTPOFF+42, %eax
+  movl tls@GOTNTPOFF(%eax), %eax
 
 .data
   .long .data
diff --git a/lld/test/ELF/lto/basic-block-sections.ll b/lld/test/ELF/lto/basic-block-sections.ll
index 1f932ac50a879..35b638ac488a3 100644
--- a/lld/test/ELF/lto/basic-block-sections.ll
+++ b/lld/test/ELF/lto/basic-block-sections.ll
@@ -11,12 +11,12 @@
 ; SECNAMES: Name: .text.foo {{.*}}
 
 ; SECNAMES-FULL: Name: .text.foo {{.*}}
-; SECNAMES-FULL: Name: .text.foo.foo.1 {{.*}}
-; SECNAMES-FULL: Name: .text.foo.foo.2 {{.*}}
+; SECNAMES-FULL: Name: .text.foo.foo.__part.1 {{.*}}
+; SECNAMES-FULL: Name: .text.foo.foo.__part.2 {{.*}}
 
 ; SYMS: foo
-; SYMS: foo.1
-; SYMS: foo.2
+; SYMS: foo.__part.1
+; SYMS: foo.__part.2
 
 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
diff --git a/lld/test/ELF/mips-tls-hilo.s b/lld/test/ELF/mips-tls-hilo.s
index 4f1417d295258..92cf71be5ecc1 100644
--- a/lld/test/ELF/mips-tls-hilo.s
+++ b/lld/test/ELF/mips-tls-hilo.s
@@ -7,8 +7,10 @@
 # RUN: llvm-objdump -d -t --no-show-raw-insn %t.exe | FileCheck --check-prefix=DIS %s
 # RUN: llvm-readobj -r -A %t.exe | FileCheck %s
 
-# RUN: ld.lld %t.o -shared -o %t.so
-# RUN: llvm-readobj -r -A %t.so | FileCheck -check-prefix=SO %s
+# RUN: not ld.lld %t.o -shared -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR --implicit-check-not=error:
+
+# ERR: error: relocation R_MIPS_TLS_TPREL_HI16 against loc0 cannot be used with -shared
+# ERR: error: relocation R_MIPS_TLS_TPREL_LO16 against loc0 cannot be used with -shared
 
 # DIS: 00000000 l    O .tdata          00000000 loc0
 
diff --git a/lld/test/ELF/ppc64-local-exec-tls.s b/lld/test/ELF/ppc64-local-exec-tls.s
index f657d96ad1f14..51dcb1a7395a1 100644
--- a/lld/test/ELF/ppc64-local-exec-tls.s
+++ b/lld/test/ELF/ppc64-local-exec-tls.s
@@ -4,6 +4,18 @@
 // RUN: llvm-readelf -r %t.o | FileCheck --check-prefix=InputRelocs %s
 // RUN: llvm-objdump -d %t | FileCheck --check-prefix=Dis %s
 
+// RUN: not ld.lld -shared %t.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR
+
+/// Reject local-exec TLS relocations for -shared.
+// ERR: error: relocation R_PPC64_TPREL16_HA against a cannot be used with -shared
+// ERR: error: relocation R_PPC64_TPREL16_LO against a cannot be used with -shared
+// ERR: error: relocation R_PPC64_TPREL16 against b cannot be used with -shared
+// ERR: error: relocation R_PPC64_TPREL16_HI against b cannot be used with -shared
+// ERR: error: relocation R_PPC64_TPREL16_DS against b cannot be used with -shared
+// ERR: error: relocation R_PPC64_TPREL16_LO_DS against b cannot be used with -shared
+// ERR: error: relocation R_PPC64_TPREL16_HIGHESTA against b cannot be used with -shared
+// ERR: error: relocation R_PPC64_TPREL16_HIGHERA against b cannot be used with -shared
+
 	.text
 	.abiversion 2
 	.globl	test_local_exec                    # -- Begin function test_local_exec
diff --git a/lld/test/ELF/ppc64-tls-missing-gdld.s b/lld/test/ELF/ppc64-tls-missing-gdld.s
index fcc1a2c21a25d..a37a45c11cae5 100644
--- a/lld/test/ELF/ppc64-tls-missing-gdld.s
+++ b/lld/test/ELF/ppc64-tls-missing-gdld.s
@@ -1,37 +1,106 @@
 # REQUIRES: ppc
-# RUN: llvm-mc --triple=powerpc64le %s --filetype=obj -o %t1.o
-# RUN: llvm-mc --triple=powerpc64 %s --filetype=obj -o %t2.o
-# RUN: ld.lld --shared --fatal-warnings %t1.o -o /dev/null
-# RUN: ld.lld --shared --fatal-warnings %t2.o -o /dev/null
+# RUN: split-file %s %t
+# RUN: llvm-mc --triple=ppc64le %t/a.s --filetype=obj -o %t/a.o
+# RUN: llvm-mc --triple=ppc64le %t/b.s --filetype=obj -o %t/b.o
+# RUN: llvm-mc --triple=ppc64le %t/tga.s --filetype=obj -o %t/tga.o
 
 ## User code can call __tls_get_addr by specifying the tls_index parameter.
 ## We need to allow R_PPC64_REL24/R_PPC64_REL24_NOTOC referencing __tls_get_addr
 ## without a pairing R_PPC64_TLSGD/R_PPC64_TLSLD.
+# RUN: ld.lld --shared --fatal-warnings %t/b.o -o /dev/null
 
+## Warn missing R_PPC64_TLSGD/R_PPC64_TLSLD.
+# RUN: ld.lld --shared %t/a.o -o %t.so 2>&1 | FileCheck %s --check-prefix=WARN
+# RUN: llvm-objdump -d --no-leading-addr %t.so | FileCheck %s --check-prefix=DIS
+
+# RUN: ld.lld %t/a.o %t/tga.o -o %t2 2>&1 | FileCheck %s --check-prefix=WARN
+# RUN: llvm-readelf -x .got %t2 | FileCheck %s --check-prefix=HEX
+# RUN: llvm-objdump -d --no-leading-addr %t2 | FileCheck %s --check-prefix=DIS
+
+# WARN: warning: {{.*}}.o: disable TLS relaxation due to R_PPC64_GOT_TLS* relocations without R_PPC64_TLSGD/R_PPC64_TLSLD relocations
+
+## .got+0: x is local - relaxed to LE - its DTPMOD/DTPREL slots are link-time constants.
+## DTPMOD is 1. DTPREL is st_value-0x8000 = -0x8000.
+## .got+16: DTPMOD/DTPREL for _TLS_MODULE_BASE_ is 1 and 0, respectively.
+## .got+32: TPOFFSET for x = st_value-0x7000
+# HEX:      section '.got':
+# HEX-NEXT: [[#%x,IGNORE:]] 01000000 00000000 0080ffff ffffffff
+# HEX-NEXT: [[#%x,IGNORE:]] 01000000 00000000 00000000 00000000
+# HEX-NEXT: [[#%x,IGNORE:]] 0090ffff ffffffff
+
+## .TOC.-32768 = (.got+0x8000)-32768 = .got
+# DIS-LABEL: <GeneralDynamic>:
+# DIS-NEXT:    addis 3, 2, 0
+# DIS-NEXT:    addi 3, 3, -32768
+# DIS-NEXT:    bl [[#%x,TGA:]]
+# DIS-LABEL: <GeneralDynamic_NOTOC>:
+# DIS-NEXT:    addis 3, 2, 0
+# DIS-NEXT:    addi 3, 3, -32768
+# DIS-NEXT:    bl [[#TGA]]
+
+## LocalDynamic references _TLS_MODULE_BASE_.
+## .TOC.-32752 = (.got+0x8000)-32752 = .got+16
+# DIS-LABEL: <LocalDynamic>:
+# DIS-NEXT:    addis 3, 2, 0
+# DIS-NEXT:    addi 3, 3, -32752
+# DIS-NEXT:    bl [[#TGA]]
+# DIS-LABEL: <LocalDynamic_NOTOC>:
+# DIS-NEXT:    addis 3, 2, 0
+# DIS-NEXT:    addi 3, 3, -32752
+# DIS-NEXT:    bl [[#TGA]]
+
+## Technically we don't have to disable IE to LE relaxation,
+## but disabling it for implementation simplicity does not hurt.
+# DIS-LABEL: <InitialExec>:
+# DIS-NEXT:    addis 3, 2, 0
+# DIS-NEXT:    ld 3, -32736(3)
+# DIS-NEXT:    add 3, 3, 13
+
+#--- a.s
 GeneralDynamic:
   addis 3, 2, x@got@tlsgd@ha
   addi 3, 3, x@got@tlsgd@l
   bl __tls_get_addr
-  blr
+  nop
 
 GeneralDynamic_NOTOC:
   addis 3, 2, x@got@tlsgd@ha
   addi 3, 3, x@got@tlsgd@l
   bl __tls_get_addr@notoc
-  blr
+  nop
 
 LocalDynamic:
   addis 3, 2, x@got@tlsld@ha
   addi 3, 3, x@got@tlsld@l
   bl __tls_get_addr
-  blr
+  nop
 
 LocalDynamic_NOTOC:
   addis 3, 2, x@got@tlsld@ha
   addi 3, 3, x@got@tlsld@l
   bl __tls_get_addr@notoc
-  blr
+  nop
+
+InitialExec:
+  addis 3, 2, x@got@tprel@ha
+  ld 3, x@got@tprel@l(3)
+  add 3, 3, x@tls
 
+.globl _start
+_start:
+
+.section .tbss,"awT",@nobits
+.globl x
+x:
+  .quad 0
+
+#--- b.s
 CallOnly:
   bl __tls_get_addr
+  nop
+  blr
+
+#--- tga.s
+.globl __tls_get_addr
+__tls_get_addr:
   blr
diff --git a/lld/test/ELF/riscv-tls-le.s b/lld/test/ELF/riscv-tls-le.s
index 860e6884c5dae..96a10e940218d 100644
--- a/lld/test/ELF/riscv-tls-le.s
+++ b/lld/test/ELF/riscv-tls-le.s
@@ -13,6 +13,13 @@
 # RUN: ld.lld -pie %t.64.o -o %t.64
 # RUN: llvm-objdump -d --no-show-raw-insn %t.64 | FileCheck --check-prefixes=LE %s
 
+# RUN: not ld.lld -shared %t.32.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR --implicit-check-not=error:
+
+# ERR: error: relocation R_RISCV_TPREL_HI20 against .LANCHOR0 cannot be used with -shared
+# ERR: error: relocation R_RISCV_TPREL_LO12_I against .LANCHOR0 cannot be used with -shared
+# ERR: error: relocation R_RISCV_TPREL_HI20 against a cannot be used with -shared
+# ERR: error: relocation R_RISCV_TPREL_LO12_S against a cannot be used with -shared
+
 # NM: {{0*}}00000008 b .LANCHOR0
 # NM: {{0*}}0000000c B a
 
diff --git a/lld/test/ELF/tls.s b/lld/test/ELF/tls.s
index 353a056ee20d8..567e44600ab05 100644
--- a/lld/test/ELF/tls.s
+++ b/lld/test/ELF/tls.s
@@ -4,6 +4,26 @@
 // RUN: llvm-readobj -S -l --symbols %tout | FileCheck %s
 // RUN: llvm-objdump -d %tout | FileCheck %s --check-prefix=DIS
 
+/// Reject local-exec TLS relocations for -shared, regardless of the preemptibility.
+// RUN: not ld.lld -shared %t -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR
+// RUN: not ld.lld -shared -Bsymbolic %t -o /dev/null 2>&1 | FileCheck %s --check-prefix=ERR
+
+// ERR:       error: relocation R_X86_64_TPOFF32 against a cannot be used with -shared
+// ERR-NEXT:  defined in {{.*}}
+// ERR-NEXT:  referenced by {{.*}}:(.text+0x4)
+// ERR-EMPTY:
+// ERR-NEXT:  error: relocation R_X86_64_TPOFF32 against b cannot be used with -shared
+// ERR-NEXT:  defined in {{.*}}
+// ERR-NEXT:  referenced by {{.*}}:(.text+0xC)
+// ERR-EMPTY:
+// ERR-NEXT:  error: relocation R_X86_64_TPOFF32 against c cannot be used with -shared
+// ERR-NEXT:  defined in {{.*}}
+// ERR-NEXT:  referenced by {{.*}}:(.text+0x14)
+// ERR-EMPTY:
+// ERR-NEXT:  error: relocation R_X86_64_TPOFF32 against d cannot be used with -shared
+// ERR-NEXT:  defined in {{.*}}
+// ERR-NEXT:  referenced by {{.*}}:(.text+0x1C)
+
 .global _start
 _start:
   movl %fs:a@tpoff, %eax
diff --git a/lld/test/ELF/x86-64-reloc-tpoff32-fpic.s b/lld/test/ELF/x86-64-reloc-tpoff32-fpic.s
deleted file mode 100644
index edb04c1d4487b..0000000000000
--- a/lld/test/ELF/x86-64-reloc-tpoff32-fpic.s
+++ /dev/null
@@ -1,14 +0,0 @@
-# REQUIRES: x86
-# RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
-# RUN: not ld.lld %t.o -shared -o /dev/null 2>&1 | FileCheck %s
-
-# CHECK: relocation R_X86_64_TPOFF32 cannot be used against symbol var; recompile with -fPIC
-# CHECK: >>> defined in {{.*}}.o
-# CHECK: >>> referenced by {{.*}}.o:(.tdata+0xC)
-
-.section ".tdata", "awT", @progbits
-.globl var
-var:
-
-movq %fs:0, %rax
-leaq var@TPOFF(%rax),%rax
diff --git a/lld/test/MachO/Inputs/libfunction.s b/lld/test/MachO/Inputs/libfunction.s
deleted file mode 100644
index fe0b3879a41ab..0000000000000
--- a/lld/test/MachO/Inputs/libfunction.s
+++ /dev/null
@@ -1,6 +0,0 @@
-.section __TEXT,__text
-.globl _some_function
-
-_some_function:
-  mov $1, %rax
-  ret
diff --git a/lld/test/MachO/archive.s b/lld/test/MachO/archive.s
index abde623b07f4a..2ac2d302b88dd 100644
--- a/lld/test/MachO/archive.s
+++ b/lld/test/MachO/archive.s
@@ -1,11 +1,10 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
-# RUN: echo ".global _boo; _boo: ret"                           | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/2.o
-# RUN: echo ".global _bar; _bar: ret"                           | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/3.o
-# RUN: echo ".global _undefined; .global _unused; _unused: ret" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/4.o
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/main.o
+# RUN: rm -rf %t; split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/2.s -o %t/2.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/3.s -o %t/3.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/4.s -o %t/4.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/main.s -o %t/main.o
 
-# RUN: rm -f %t/test.a
 # RUN: llvm-ar rcs %t/test.a %t/2.o %t/3.o %t/4.o
 # RUN: %lld %t/main.o %t/test.a -o %t/test.out
 
@@ -33,9 +32,24 @@
 # ALL-LOAD: T _main
 # ALL-LOAD: T _unused
 
-.global _main
+#--- 2.s
+.globl _boo
+_boo:
+  ret
+
+#--- 3.s
+.globl _bar
+_bar:
+  ret
+
+#--- 4.s
+.globl _undefined, _unused
+_unused:
+  ret
+
+#--- main.s
+.globl _main
 _main:
   callq _boo
   callq _bar
-  mov $0, %rax
   ret
diff --git a/lld/test/MachO/common-symbol-resolution.s b/lld/test/MachO/common-symbol-resolution.s
index 2a88ef51e4604..1dc015816da4b 100644
--- a/lld/test/MachO/common-symbol-resolution.s
+++ b/lld/test/MachO/common-symbol-resolution.s
@@ -1,5 +1,5 @@
 # REQUIRES: x86
-# RUN: split-file %s %t
+# RUN: rm -rf %t; split-file %s %t
 
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/common.s -o %t/common.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/weak-common.s -o %t/weak-common.o
@@ -11,7 +11,6 @@
 
 # RUN: %lld -lSystem -order_file %t/order -dylib %t/libfoo.o -o %t/libfoo.dylib
 
-# RUN: rm -f %t/defined.a %t/weak-defined-and-common.a
 # RUN: llvm-ar rcs %t/defined.a %t/defined.o
 # RUN: llvm-ar rcs %t/weak-defined-and-common.a %t/weak-defined.o %t/common.o
 
diff --git a/lld/test/MachO/driver.test b/lld/test/MachO/driver.test
index 229ec3ef69639..5a0ccac01c316 100644
--- a/lld/test/MachO/driver.test
+++ b/lld/test/MachO/driver.test
@@ -1,5 +1,7 @@
-# RUN: not %lld ---help 2>&1 | FileCheck -check-prefix=SPELLHELP %s
+# RUN: %lld --version | FileCheck -check-prefix=VERSION %s
+VERSION: LLD
 
+# RUN: not %lld ---help 2>&1 | FileCheck -check-prefix=SPELLHELP %s
 SPELLHELP: error: unknown argument '---help', did you mean '--help'
 # FIXME: This should say "no input files" instead
 SPELLHELP: error: undefined symbol: _main
diff --git a/lld/test/MachO/dylink-lazy.s b/lld/test/MachO/dylink-lazy.s
index 8e3e0b6ae7170..a5f275e55f085 100644
--- a/lld/test/MachO/dylink-lazy.s
+++ b/lld/test/MachO/dylink-lazy.s
@@ -27,7 +27,7 @@
 # RUN: llvm-objdump --macho --rebase %t/dylink-lazy-pie | FileCheck %s --check-prefix=PIE
 
 # CHECK-LABEL: SYMBOL TABLE:
-# CHECK:       {{0*}}[[#%x, IMGLOADER:]] {{.*}} __DATA,__data __dyld_private
+# CHECK:       {{0*}}[[#%x, IMGLOADER:]] l {{.*}} __DATA,__data __dyld_private
 
 # CHECK-LABEL: Disassembly of section __TEXT,__text:
 # CHECK:         callq 0x[[#%x, HELLO_STUB:]]
diff --git a/lld/test/MachO/filelist.s b/lld/test/MachO/filelist.s
index 32be332aa507a..3d4846c4505a9 100644
--- a/lld/test/MachO/filelist.s
+++ b/lld/test/MachO/filelist.s
@@ -3,10 +3,10 @@
 ## This test verifies that the paths in -filelist get processed in command-line
 ## order.
 
-# RUN: mkdir -p %t
-# RUN: echo ".globl _foo; .weak_definition _foo; .section __TEXT,first; _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/first.o
-# RUN: echo ".globl _foo; .weak_definition _foo; .section __TEXT,second; _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/second.o
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
+# RUN: rm -rf %t; split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/first.s -o %t/first.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/second.s -o %t/second.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
 
 # FIRST: __TEXT,first _foo
 # SECOND: __TEXT,second _foo
@@ -34,7 +34,19 @@
 # RUN: %lld -filelist filelist-2 -filelist filelist-1 %t/test.o -o %t/test
 # RUN: llvm-objdump --syms %t/test | FileCheck %s --check-prefix=SECOND
 
-.globl _main
+#--- first.s
+.globl _foo
+.weak_definition _foo
+.section __TEXT,first
+_foo:
+
+#--- second.s
+.globl _foo
+.weak_definition _foo
+.section __TEXT,second
+_foo:
 
+#--- test.s
+.globl _main
 _main:
   ret
diff --git a/lld/test/MachO/force-load.s b/lld/test/MachO/force-load.s
index ffc2019eacd97..1cedae3173bca 100644
--- a/lld/test/MachO/force-load.s
+++ b/lld/test/MachO/force-load.s
@@ -1,10 +1,9 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
-# RUN: echo ".section __TEXT,archive; .globl _foo; .weak_definition _foo; _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/archive-foo.o
-# RUN: rm -f %t/foo.a
+# RUN: rm -rf %t; split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/archive-foo.s -o %t/archive-foo.o
 # RUN: llvm-ar rcs %t/foo.a %t/archive-foo.o
-# RUN: echo ".section __TEXT,obj; .globl _foo; .weak_definition _foo; _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/foo.o
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/foo.s -o %t/foo.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
 
 # RUN: %lld -force_load %t/foo.a %t/foo.o %t/test.o -o %t/test-force-load-first
 # FORCE-LOAD-FIRST:  __TEXT,archive _foo
@@ -14,6 +13,19 @@
 # RUN: llvm-objdump --syms %t/test-force-load-second | FileCheck %s --check-prefix=FORCE-LOAD-SECOND
 # FORCE-LOAD-SECOND: __TEXT,obj _foo
 
+#--- archive-foo.s
+.section __TEXT,archive
+.globl _foo
+.weak_definition _foo
+_foo:
+
+#--- foo.s
+.section __TEXT,obj
+.globl _foo
+.weak_definition _foo
+_foo:
+
+#--- test.s
 .globl _main
 _main:
   ret
diff --git a/lld/test/MachO/framework.s b/lld/test/MachO/framework.s
index 43e1ec4fccafb..7244387a022b3 100644
--- a/lld/test/MachO/framework.s
+++ b/lld/test/MachO/framework.s
@@ -1,13 +1,13 @@
 # REQUIRES: x86, shell
-# RUN: mkdir -p %t
-# RUN: echo ".globl _foo; _foo: ret" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/foo.o
+# RUN: rm -rf %t; split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/foo.s -o %t/foo.o
 # RUN: mkdir -p %t/Foo.framework/Versions/A
 # RUN: %lld -dylib -install_name %t/Foo.framework/Versions/A/Foo %t/foo.o -o %t/Foo.framework/Versions/A/Foo
 # RUN: %lld -dylib -install_name %t/Foo.framework/Versions/A/Foobar %t/foo.o -o %t/Foo.framework/Versions/A/Foobar
 # RUN: ln -sf %t/Foo.framework/Versions/A %t/Foo.framework/Versions/Current
 # RUN: ln -sf %t/Foo.framework/Versions/Current/Foo %t/Foo.framework/Foo
 
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/test.o %s
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
 # RUN: %lld -lSystem -F%t -framework Foo %t/test.o -o %t/test
 # RUN: llvm-objdump --macho --lazy-bind %t/test | FileCheck %s --check-prefix=NOSUFFIX
 # NOSUFFIX: __DATA __la_symbol_ptr 0x{{[0-9a-f]*}} {{.*}}Foo _foo
@@ -19,6 +19,12 @@
 # RUN: llvm-objdump --macho --lazy-bind %t/test-suffix | FileCheck %s --check-prefix=SUFFIX
 # SUFFIX: __DATA __la_symbol_ptr 0x{{[0-9a-f]*}} {{.*}}Foobar _foo
 
+#--- foo.s
+.globl _foo
+_foo:
+  ret
+
+#--- test.s
 .globl _main
 .text
 _main:
diff --git a/lld/test/MachO/headerpad.s b/lld/test/MachO/headerpad.s
index 0f4f19ce9d62a..750919438cb07 100644
--- a/lld/test/MachO/headerpad.s
+++ b/lld/test/MachO/headerpad.s
@@ -8,10 +8,12 @@
 ## just enforces a lower bound. We should consider implementing the same
 ## alignment behavior.
 
+# RUN: rm -rf %t; mkdir -p %t
+
 ################ Check default behavior
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t.o
-# RUN: %lld -o %t %t.o
-# RUN: llvm-objdump --macho --all-headers %t | FileCheck %s --check-prefix=PADx
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
+# RUN: %lld -o %t/test %t/test.o
+# RUN: llvm-objdump --macho --all-headers %t/test | FileCheck %s --check-prefix=PADx
 #
 # PADx:      magic        {{.+}}  ncmds  sizeofcmds         flags
 # PADx-NEXT: MH_MAGIC_64  {{.+}}  [[#]]  [[#%u, CMDSIZE:]]  {{.*}}
@@ -22,10 +24,10 @@
 # PADx-NEXT: offset [[#%u, CMDSIZE + 0x20 + 0x20]]
 
 ################ Zero pad, no LCDylibs
-# RUN: %lld -o %t %t.o -headerpad 0
-# RUN: llvm-objdump --macho --all-headers %t | FileCheck %s --check-prefix=PAD0
-# RUN: %lld -o %t %t.o -headerpad 0 -headerpad_max_install_names
-# RUN: llvm-objdump --macho --all-headers %t | FileCheck %s --check-prefix=PAD0
+# RUN: %lld -o %t/test %t/test.o -headerpad 0
+# RUN: llvm-objdump --macho --all-headers %t/test | FileCheck %s --check-prefix=PAD0
+# RUN: %lld -o %t/test %t/test.o -headerpad 0 -headerpad_max_install_names
+# RUN: llvm-objdump --macho --all-headers %t/test | FileCheck %s --check-prefix=PAD0
 #
 # PAD0:      magic        {{.+}}  ncmds  sizeofcmds         flags
 # PAD0-NEXT: MH_MAGIC_64  {{.+}}  [[#]]  [[#%u, CMDSIZE:]]  {{.*}}
@@ -36,12 +38,12 @@
 # PAD0-NEXT: offset [[#%u, CMDSIZE + 0x20 + 0]]
 
 ################ Each lexical form of a hex number, no LCDylibs
-# RUN: %lld -o %t %t.o -headerpad 11
-# RUN: llvm-objdump --macho --all-headers %t | FileCheck %s --check-prefix=PAD11
-# RUN: %lld -o %t %t.o -headerpad 0x11
-# RUN: llvm-objdump --macho --all-headers %t | FileCheck %s --check-prefix=PAD11
-# RUN: %lld -o %t %t.o -headerpad 0X11 -headerpad_max_install_names
-# RUN: llvm-objdump --macho --all-headers %t | FileCheck %s --check-prefix=PAD11
+# RUN: %lld -o %t/test %t/test.o -headerpad 11
+# RUN: llvm-objdump --macho --all-headers %t/test | FileCheck %s --check-prefix=PAD11
+# RUN: %lld -o %t/test %t/test.o -headerpad 0x11
+# RUN: llvm-objdump --macho --all-headers %t/test | FileCheck %s --check-prefix=PAD11
+# RUN: %lld -o %t/test %t/test.o -headerpad 0X11 -headerpad_max_install_names
+# RUN: llvm-objdump --macho --all-headers %t/test | FileCheck %s --check-prefix=PAD11
 #
 # PAD11:      magic        {{.+}}  ncmds  sizeofcmds         flags
 # PAD11-NEXT: MH_MAGIC_64  {{.+}}  [[#]]  [[#%u, CMDSIZE:]]  {{.*}}
@@ -52,17 +54,17 @@
 # PAD11-NEXT: offset [[#%u, CMDSIZE + 0x20 + 0x11]]
 
 ################ Each & all 3 kinds of LCDylib
-# RUN: echo "" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %T/null.o
-# RUN: %lld -o %T/libnull.dylib %T/null.o -dylib \
+# RUN: echo "" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/null.o
+# RUN: %lld -o %t/libnull.dylib %t/null.o -dylib \
 # RUN:     -headerpad_max_install_names
-# RUN: llvm-objdump --macho --all-headers %T/libnull.dylib | FileCheck %s --check-prefix=PADMAX
-# RUN: %lld -o %T/libnull.dylib %T/null.o -dylib \
+# RUN: llvm-objdump --macho --all-headers %t/libnull.dylib | FileCheck %s --check-prefix=PADMAX
+# RUN: %lld -o %t/libnull.dylib %t/null.o -dylib \
 # RUN:     -headerpad_max_install_names -lSystem
-# RUN: llvm-objdump --macho --all-headers %T/libnull.dylib | FileCheck %s --check-prefix=PADMAX
-# RUN: %lld -o %T/libnull.dylib %T/null.o -dylib \
+# RUN: llvm-objdump --macho --all-headers %t/libnull.dylib | FileCheck %s --check-prefix=PADMAX
+# RUN: %lld -o %t/libnull.dylib %t/null.o -dylib \
 # RUN:     -headerpad_max_install_names \
 # RUN:     -lSystem -sub_library libSystem
-# RUN: llvm-objdump --macho --all-headers %T/libnull.dylib | FileCheck %s --check-prefix=PADMAX
+# RUN: llvm-objdump --macho --all-headers %t/libnull.dylib | FileCheck %s --check-prefix=PADMAX
 #
 # PADMAX:      magic        {{.+}}  ncmds        sizeofcmds         flags
 # PADMAX-NEXT: MH_MAGIC_64  {{.+}}  [[#%u, N:]]  [[#%u, CMDSIZE:]]  {{.*}}
@@ -73,10 +75,10 @@
 # PADMAX-NEXT: offset [[#%u, CMDSIZE + 0x20 + mul(0x400, N - 7)]]
 
 ################ All 3 kinds of LCDylib swamped by a larger override
-# RUN: %lld -o %T/libnull.dylib %T/null.o -dylib \
+# RUN: %lld -o %t/libnull.dylib %t/null.o -dylib \
 # RUN:     -headerpad_max_install_names -headerpad 0x1001 \
 # RUN:     -lSystem -sub_library libSystem
-# RUN: llvm-objdump --macho --all-headers %T/libnull.dylib | FileCheck %s --check-prefix=PADOVR
+# RUN: llvm-objdump --macho --all-headers %t/libnull.dylib | FileCheck %s --check-prefix=PADOVR
 #
 # PADOVR:      magic        {{.+}}  ncmds        sizeofcmds         flags
 # PADOVR-NEXT: MH_MAGIC_64  {{.+}}  [[#%u, N:]]  [[#%u, CMDSIZE:]]  {{.*}}
diff --git a/lld/test/MachO/invalid/archive-no-index.s b/lld/test/MachO/invalid/archive-no-index.s
index d4d2afb449b7b..9cda945652500 100644
--- a/lld/test/MachO/invalid/archive-no-index.s
+++ b/lld/test/MachO/invalid/archive-no-index.s
@@ -1,16 +1,31 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
-# RUN: echo ".global _boo; _boo: ret"                           | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/2.o
-# RUN: echo ".global _bar; _bar: ret"                           | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/3.o
-# RUN: echo ".global _undefined; .global _unused; _unused: ret" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/4.o
+# RUN: rm -rf %t; split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/2.s -o %t/2.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/3.s -o %t/3.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/4.s -o %t/4.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/main.o
 
-# RUN: rm -f %t/test.a
 # RUN: llvm-ar rcS %t/test.a %t/2.o %t/3.o %t/4.o
 
 # RUN: not %lld %t/test.o %t/test.a -o /dev/null 2>&1 | FileCheck %s
 # CHECK: error: {{.*}}.a: archive has no index; run ranlib to add one
 
+#--- 2.s
+.globl _boo
+_boo:
+  ret
+
+#--- 3.s
+.globl _bar
+_bar:
+  ret
+
+#--- 4.s
+.globl _undefined, _unused
+_unused:
+  ret
+
+#--- main.s
 .global _main
 _main:
   mov $0, %rax
diff --git a/lld/test/MachO/invalid/bad-archive-member.s b/lld/test/MachO/invalid/bad-archive-member.s
index 15ab524476d32..a76cecf239b7a 100644
--- a/lld/test/MachO/invalid/bad-archive-member.s
+++ b/lld/test/MachO/invalid/bad-archive-member.s
@@ -1,9 +1,8 @@
 # REQUIRES: x86
-# RUN: split-file %s %t
+# RUN: rm -rf %t; split-file %s %t
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/foo.s -o %t/foo.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
 # RUN: %lld -dylib -lSystem %t/foo.o -o %t/foo.dylib
-# RUN: rm -f %t/foo.a
 # RUN: llvm-ar rcs %t/foo.a %t/foo.dylib
 # RUN: not %lld %t/test.o %t/foo.a -o /dev/null 2>&1 | FileCheck %s -DFILE=%t/foo.a
 # CHECK: error: [[FILE]]: archive member foo.dylib has unhandled file type
diff --git a/lld/test/MachO/lto-archive.ll b/lld/test/MachO/lto-archive.ll
index 42b2c0fb5759f..2aa7beb0c9511 100644
--- a/lld/test/MachO/lto-archive.ll
+++ b/lld/test/MachO/lto-archive.ll
@@ -1,8 +1,7 @@
 ; REQUIRES: x86
-; RUN: split-file %s %t
+; RUN: rm -rf %t; split-file %s %t
 ; RUN: llvm-as %t/foo.ll -o %t/foo.o
 ; RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
-; RUN: rm -f %t/foo.a
 ; RUN: llvm-ar rcs %t/foo.a %t/foo.o
 ; RUN: %lld -save-temps -lSystem %t/test.o %t/foo.a -o %t/test
 ; RUN: llvm-objdump -d --macho --no-show-raw-insn %t/test | FileCheck %s
diff --git a/lld/test/MachO/objc.s b/lld/test/MachO/objc.s
index 48ca60bc03225..53dd12e8f1909 100644
--- a/lld/test/MachO/objc.s
+++ b/lld/test/MachO/objc.s
@@ -1,12 +1,10 @@
 # REQUIRES: x86
-# RUN: split-file %s %t
+# RUN: rm -rf %t; split-file %s %t
 
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/has-objc-symbol.s -o %t/has-objc-symbol.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/has-objc-category.s -o %t/has-objc-category.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/has-swift.s -o %t/has-swift.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/no-objc.s -o %t/no-objc.o
-
-# RUN: rm -f %t/libHasSomeObjC.a
 # RUN: llvm-ar rcs %t/libHasSomeObjC.a %t/has-objc-symbol.o %t/has-objc-category.o %t/has-swift.o %t/no-objc.o
 
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
diff --git a/lld/test/MachO/order-file.s b/lld/test/MachO/order-file.s
index 83e6840c97861..c185572c23891 100644
--- a/lld/test/MachO/order-file.s
+++ b/lld/test/MachO/order-file.s
@@ -2,7 +2,6 @@
 # RUN: rm -rf %t; split-file %s %t
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/foo.s -o %t/foo.o
-# RUN: rm -f %t/foo.a
 # RUN: llvm-ar rcs %t/foo.a %t/foo.o
 
 # FOO-FIRST: <_bar>:
diff --git a/lld/test/MachO/platform-version.s b/lld/test/MachO/platform-version.s
index 326a74428cf41..0bfc46930c5b2 100644
--- a/lld/test/MachO/platform-version.s
+++ b/lld/test/MachO/platform-version.s
@@ -55,7 +55,7 @@
 # RUN:        -platform_version 0 1 5 \
 # RUN:     | FileCheck --check-prefix=FAIL-PLATFORM %s
 # RUN: not %lld -o %t %t.o 2>&1 \
-# RUN:        -platform_version 10 1 5 \
+# RUN:        -platform_version 11 1 5 \
 # RUN:     | FileCheck --check-prefix=FAIL-PLATFORM %s
 # FAIL-PLATFORM: malformed platform: {{.*}}
 # FAIL-PLATFORM-NOT: malformed {{minimum|sdk}} version: {{.*}}
diff --git a/lld/test/MachO/private-extern.s b/lld/test/MachO/private-extern.s
new file mode 100644
index 0000000000000..c8c96aa8e7b3a
--- /dev/null
+++ b/lld/test/MachO/private-extern.s
@@ -0,0 +1,143 @@
+# REQUIRES: x86
+
+# RUN: split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos \
+# RUN:     %t/basics.s -o %t/basics.o
+
+## Check that .private_extern symbols are marked as local in the symbol table
+## and aren't in the export trie.
+# RUN: %lld -dylib %t/basics.o -o %t/basics
+# RUN: llvm-objdump --syms --exports-trie %t/basics | \
+# RUN:     FileCheck --check-prefix=EXPORTS %s
+# RUN: llvm-nm -m %t/basics | FileCheck --check-prefix=EXPORTS-NM %s
+# EXPORTS-LABEL: SYMBOL TABLE:
+# EXPORTS-DAG:   [[#%x, FOO_ADDR:]] l {{.*}} _foo
+# EXPORTS-DAG:   [[#%x, BAR_ADDR:]] g {{.*}} _bar
+# EXPORTS-LABEL: Exports trie:
+# EXPORTS-NOT:   0x{{0*}}[[#%X, FOO_ADDR]] _foo
+# EXPORTS-DAG:   0x{{0*}}[[#%X, BAR_ADDR]] _bar
+# EXPORTS-NOT:   0x{{0*}}[[#%X, FOO_ADDR]] _foo
+# EXPORTS-NM-DAG: (__TEXT,__cstring) non-external (was a private external) _foo
+# EXPORTS-NM-DAG: (__TEXT,__cstring) external _bar
+
+#--- basics.s
+.section __TEXT,__cstring
+
+.globl _foo, _bar
+.private_extern _foo
+
+_foo:
+.asciz "Foo"
+
+_bar:
+.asciz "Bar"
+
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos \
+# RUN:     %t/strong-globl.s -o %t/strong-globl.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos \
+# RUN:     %t/weak-globl.s -o %t/weak-globl.o
+
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos \
+# RUN:     %t/strong-private.s -o %t/strong-private.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos \
+# RUN:     %t/weak-private.s -o %t/weak-private.o
+
+## weak + strong symbol takes privateness from strong symbol
+## - weak private extern + strong extern = strong extern (for both .o orderings)
+# RUN: %lld -dylib %t/weak-private.o %t/strong-globl.o -o %t/wpsg
+# RUN: llvm-nm -m %t/wpsg | FileCheck --check-prefix=EXTERNAL %s
+# RUN: %lld -dylib %t/strong-globl.o %t/weak-private.o -o %t/sgwp
+# RUN: llvm-nm -m %t/sgwp | FileCheck --check-prefix=EXTERNAL %s
+# EXTERNAL: (__TEXT,__text) external _foo
+## - weak extern + strong private extern = strong private extern
+##   (for both .o orderings)
+# RUN: %lld -dylib %t/weak-globl.o %t/strong-private.o -o %t/wgsp
+# RUN: llvm-nm -m %t/wgsp | FileCheck --check-prefix=NONEXTERNAL %s
+# RUN: %lld -dylib %t/strong-private.o %t/weak-globl.o -o %t/spwg
+# RUN: llvm-nm -m %t/spwg | FileCheck --check-prefix=NONEXTERNAL %s
+# NONEXTERNAL: (__TEXT,__text) non-external (was a private external) _foo
+
+## weak + weak symbol take weaker privateness
+## - weak extern + weak private extern = weak extern (both orders)
+# RUN: %lld -dylib %t/weak-private.o %t/weak-globl.o -o %t/wpwg
+# RUN: llvm-nm -m %t/wpwg | FileCheck --check-prefix=WEAK-EXTERNAL %s
+# RUN: %lld -dylib %t/weak-globl.o %t/weak-private.o -o %t/wgwp
+# RUN: llvm-nm -m %t/wgwp | FileCheck --check-prefix=WEAK-EXTERNAL %s
+# WEAK-EXTERNAL: (__TEXT,__text) weak external _foo
+## - weak private extern + weak private extern = weak private extern
+# RUN: %lld -dylib %t/weak-private.o %t/weak-private.o -o %t/wpwp
+# RUN: llvm-nm -m %t/wpwp | FileCheck --check-prefix=NONEXTERNAL %s
+
+#--- strong-globl.s
+.globl _foo
+_foo:
+  retq
+
+#--- weak-globl.s
+.globl _foo
+.weak_definition _foo
+_foo:
+  retq
+
+#--- strong-private.s
+.private_extern _foo
+.globl _foo
+_foo:
+  retq
+
+#--- weak-private.s
+.private_extern _foo
+.globl _foo
+.weak_definition _foo
+_foo:
+  retq
+
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos \
+# RUN:     %t/comm-small.s -o %t/comm-small.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos \
+# RUN:     %t/comm-large.s -o %t/comm-large.o
+
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos \
+# RUN:     %t/comm-small-private.s -o %t/comm-small-private.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos \
+# RUN:     %t/comm-large-private.s -o %t/comm-large-private.o
+
+## For common symbols the larger one wins.
+## - smaller private extern + larger extern = larger extern
+# RUN: %lld -dylib %t/comm-small-private.o %t/comm-large.o -o %t/cspcl
+# RUN: llvm-nm -m %t/cspcl | FileCheck --check-prefix=COMMON-EXTERNAL %s
+# RUN: %lld -dylib %t/comm-large.o %t/comm-small-private.o -o %t/clcsp
+# RUN: llvm-nm -m %t/clcsp | FileCheck --check-prefix=COMMON-EXTERNAL %s
+# COMMON-EXTERNAL: (__DATA,__common) external _foo
+## - smaller extern + larger private extern = larger private extern
+# RUN: %lld -dylib %t/comm-large-private.o %t/comm-small.o -o %t/clpcs
+# RUN: llvm-nm -m %t/clpcs | FileCheck --check-prefix=COMMON-NONEXTERNAL %s
+# RUN: %lld -dylib %t/comm-small.o %t/comm-large-private.o -o %t/csclp
+# RUN: llvm-nm -m %t/csclp | FileCheck --check-prefix=COMMON-NONEXTERNAL %s
+# COMMON-NONEXTERNAL: (__DATA,__common) non-external (was a private external) _foo
+
+# For common symbols with the same size, the privateness of the symbol seen
+# later wins (!).
+## - equal private extern + equal extern = equal extern (both orders)
+# RUN: %lld -dylib %t/comm-small-private.o %t/comm-small.o -o %t/cspcs
+# RUN: llvm-nm -m %t/cspcs | FileCheck --check-prefix=COMMON-EXTERNAL %s
+## - equal extern + equal private extern = equal private extern (both orders)
+# RUN: %lld -dylib %t/comm-small.o %t/comm-small-private.o -o %t/cscsp
+# RUN: llvm-nm -m %t/cscsp | FileCheck --check-prefix=COMMON-NONEXTERNAL %s
+## - equal private extern + equal private extern = equal private extern
+# RUN: %lld -dylib %t/comm-small-private.o %t/comm-small-private.o -o %t/cspcsp
+# RUN: llvm-nm -m %t/cspcsp | FileCheck --check-prefix=COMMON-NONEXTERNAL %s
+
+#--- comm-small.s
+.comm _foo,4,2
+
+#--- comm-large.s
+.comm _foo,8,3
+
+#--- comm-small-private.s
+.private_extern _foo
+.comm _foo,4,2
+
+#--- comm-large-private.s
+.private_extern _foo
+.comm _foo,8,3
diff --git a/lld/test/MachO/resolution.s b/lld/test/MachO/resolution.s
index 056324bddbde3..da6ed086548fd 100644
--- a/lld/test/MachO/resolution.s
+++ b/lld/test/MachO/resolution.s
@@ -1,18 +1,17 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
-# RUN: echo '.globl _foo, _bar, _baz; _foo: _bar: _baz:' | \
-# RUN:   llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/libresolution.o
+# RUN: rm -rf %t; split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/libresolution.s -o %t/libresolution.o
 # RUN: %lld -dylib -install_name \
 # RUN:   @executable_path/libresolution.dylib %t/libresolution.o -o %t/libresolution.dylib
 # RUN: %lld -dylib -install_name \
 # RUN:   @executable_path/libresolution2.dylib %t/libresolution.o -o %t/libresolution2.dylib
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/resolution.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/resolution.s -o %t/resolution.o
 
 ## Check that we select the symbol defined in the first dylib passed on the
 ## command line.
 # RUN: %lld -o %t/dylib-first -L%t -lresolution -lresolution2 %t/resolution.o
 # RUN: llvm-objdump --macho --bind %t/dylib-first | FileCheck %s --check-prefix=DYLIB-FIRST
-# DYLIB-FIRST:     libresolution _foo
+# DYLIB-FIRST: libresolution _foo
 
 # RUN: %lld -o %t/dylib2-first -L%t -lresolution2 -lresolution %t/resolution.o
 # RUN: llvm-objdump --macho --bind %t/dylib2-first | FileCheck %s --check-prefix=DYLIB2-FIRST
@@ -31,6 +30,13 @@
 # OBJ-FIRST-NOT: libresolution _bar
 # OBJ-FIRST-NOT: libresolution _baz
 
+#--- libresolution.s
+.globl _foo, _bar, _baz
+_foo:
+_bar:
+_baz:
+
+#--- resolution.s
 .globl _main, _bar
 # Global defined symbol
 _bar:
diff --git a/lld/test/MachO/section-merge.s b/lld/test/MachO/section-merge.s
index 7db41573d675e..4dc657a19b5c2 100644
--- a/lld/test/MachO/section-merge.s
+++ b/lld/test/MachO/section-merge.s
@@ -1,10 +1,10 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
+# RUN: rm -rf %t; split-file %s %t
 ## Verify that we preserve alignment when merging sections.
-# RUN: echo ".globl _foo; .data; .p2align 0; _foo: .byte 0xca" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/foo.o
-# RUN: echo ".globl _bar; .data; .p2align 2; _bar: .byte 0xfe" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/bar.o
-# RUN: echo ".globl _baz; .data; .p2align 3; _baz: .byte 0xba" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/baz.o
-# RUN: echo ".globl _qux; .data; .p2align 0; _qux: .quad 0xdeadbeef" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/qux.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/foo.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/bar.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/baz.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/qux.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/main.o
 # RUN: %lld -o %t/output %t/foo.o %t/bar.o %t/baz.o %t/qux.o %t/main.o
 
@@ -18,8 +18,37 @@
 # CHECK:      Contents of section __DATA,__data:
 # CHECK-NEXT: {{0*}}[[#ADDR]] ca000000 fe000000 baefbead de000000
 
+#--- foo.s
+.globl _foo
+.data
+.p2align 0
+_foo:
+  .byte 0xca
+
+#--- bar.s
+.globl _bar
+.data
+.p2align 2
+_bar:
+  .byte 0xfe
+
+#--- baz.s
+.globl _baz
+.data
+.p2align 3
+_baz:
+  .byte 0xba
+
+#--- qux.s
+.globl _qux
+.data
+.p2align 0
+_qux:
+  .quad 0xdeadbeef
+
+#--- main.s
 .section __TEXT,__text
-.global _main
+.globl _main
 
 _main:
   mov $0, %rax
diff --git a/lld/test/MachO/stabs.s b/lld/test/MachO/stabs.s
index 9634a95be4a29..ad9dacc62804e 100644
--- a/lld/test/MachO/stabs.s
+++ b/lld/test/MachO/stabs.s
@@ -1,13 +1,12 @@
 # REQUIRES: x86, shell
 # UNSUPPORTED: system-windows
-# RUN: split-file %s %t
+# RUN: rm -rf %t; split-file %s %t
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/foo.s -o %t/foo.o
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/no-debug.s -o %t/no-debug.o
 ## Set modtimes of the files for deterministic test output.
 # RUN: env TZ=UTC touch -t "197001010000.16" %t/test.o
 # RUN: env TZ=UTC touch -t "197001010000.32" %t/foo.o
-# RUN: rm -f %t/foo.a
 # RUN: llvm-ar rcsU %t/foo.a %t/foo.o
 
 # RUN: %lld -lSystem %t/test.o %t/foo.o %t/no-debug.o -o %t/test
diff --git a/lld/test/MachO/subsections-section-relocs.s b/lld/test/MachO/subsections-section-relocs.s
index 7b7ffe20e7baf..44ed5e56041d8 100644
--- a/lld/test/MachO/subsections-section-relocs.s
+++ b/lld/test/MachO/subsections-section-relocs.s
@@ -1,9 +1,6 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
-
-# RUN: echo "_bar_str" > %t/order-file
-# RUN: echo "_foo_str" >> %t/order-file
+# RUN: rm -rf %t; split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
 
 # RUN: %lld -o %t/test %t/test.o -order_file %t/order-file
 # RUN: llvm-objdump --section-headers -d --no-show-raw-insn %t/test | FileCheck %s
@@ -20,6 +17,11 @@
 # STRINGS: Private symbol
 # STRINGS: foo
 
+#--- order-file
+_bar_str
+_foo_str
+
+#--- test.s
 .text
 .globl _main, _foo_str, _bar_str
 
diff --git a/lld/test/MachO/subsections-symbol-relocs.s b/lld/test/MachO/subsections-symbol-relocs.s
index 8010a50e7444b..848ac756361b4 100644
--- a/lld/test/MachO/subsections-symbol-relocs.s
+++ b/lld/test/MachO/subsections-symbol-relocs.s
@@ -1,21 +1,6 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
-
-# RUN: echo "_bar" > %t/order-file-1
-# RUN: echo "_foo" >> %t/order-file-1
-# RUN: echo "_main" >> %t/order-file-1
-## _qux is marked as .alt_entry, so it should not create a new subsection and
-## its contents should move with _bar to the start of the output despite the
-## order file listing it at the end.
-# RUN: echo "_qux" >> %t/order-file-1
-
-## _bar and _baz point to the same address, so both order files should achieve
-## the same result.
-# RUN: echo "_baz" > %t/order-file-2
-# RUN: echo "_foo" >> %t/order-file-2
-# RUN: echo "_main" >> %t/order-file-2
-# RUN: echo "_qux" >> %t/order-file-2
+# RUN: rm -rf %t; split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
 
 # RUN: %lld -o %t/test-1 %t/test.o -order_file %t/order-file-1
 # RUN: llvm-objdump -d --no-show-raw-insn %t/test-1 | FileCheck %s
@@ -34,6 +19,24 @@
 # CHECK-NEXT:    movq $0, %rax
 # CHECK-NEXT:    retq
 
+#--- order-file-1
+_bar
+_foo
+_main
+## _qux is marked as .alt_entry, so it should not create a new subsection and
+## its contents should move with _bar to the start of the output despite the
+## order file listing it at the end.
+_qux
+
+#--- order-file-2
+## _bar and _baz point to the same address, so both order files should achieve
+## the same result.
+_baz
+_foo
+_main
+_qux
+
+#--- test.s
 .text
 .globl _main, _foo, _bar, _qux
 .alt_entry _qux
diff --git a/lld/test/MachO/symbol-order.s b/lld/test/MachO/symbol-order.s
index c61e7c830f6b5..0c904560e5244 100644
--- a/lld/test/MachO/symbol-order.s
+++ b/lld/test/MachO/symbol-order.s
@@ -1,16 +1,13 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
-# RUN: echo ".global f, g; .section __TEXT,test_g; g: callq f"          | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/g.o
-# RUN: echo ".global f; .section __TEXT,test_f1; f: ret"                | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/f1.o
-# RUN: echo ".global f; .section __TEXT,test_f2; f: ret"                | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/f2.o
-# RUN: echo ".global f, g; .section __TEXT,test_fg; f: ret; g: callq f" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/fg.o
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
+# RUN: rm -rf %t; split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/g.s  -o %t/g.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/f1.s -o %t/f1.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/f2.s -o %t/f2.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/fg.s -o %t/fg.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
 # RUN: %lld -dylib -o %t/libf1.dylib %t/f1.o -lSystem
 
-# RUN: rm -f %t/libf2_g.a
 # RUN: llvm-ar rcs %t/libf2_g.a %t/f2.o %t/g.o
-
-# RUN: rm -f %t/libfg.a
 # RUN: llvm-ar rcs %t/libfg.a %t/fg.o
 
 # RUN: %lld %t/libf1.dylib %t/libf2_g.a %t/test.o -o %t/test.out -lSystem
@@ -39,6 +36,33 @@
 # ARCHIVE-PRIORITY-NEXT: segment  section            address       dylib            symbol
 # ARCHIVE-PRIORITY-EMPTY:
 
+#--- g.s
+.global f, g
+.section __TEXT,test_g
+g:
+  callq f
+
+#--- f1.s
+.global f
+.section __TEXT,test_f1
+f:
+  ret
+
+#--- f2.s
+.global f
+.section __TEXT,test_f2
+f:
+  ret
+
+#--- fg.s
+.global f, g
+.section __TEXT,test_fg
+f:
+  ret
+g:
+  callq f
+
+#--- test.s
 .global g
 .global _main
 _main:
diff --git a/lld/test/MachO/symtab.s b/lld/test/MachO/symtab.s
index 222a35798909e..fa784a34e16a0 100644
--- a/lld/test/MachO/symtab.s
+++ b/lld/test/MachO/symtab.s
@@ -8,7 +8,7 @@
 # RUN: llvm-readobj --syms --macho-dysymtab %t/test | FileCheck %s
 # CHECK:      Symbols [
 # CHECK-NEXT:   Symbol {
-# CHECK-NEXT:     Name: _local (2)
+# CHECK-NEXT:     Name: _local
 # CHECK-NEXT:     Type: Section (0xE)
 # CHECK-NEXT:     Section: __data (0x4)
 # CHECK-NEXT:     RefType: UndefinedNonLazy (0x0)
@@ -17,48 +17,47 @@
 # CHECK-NEXT:     Value: 0x1{{[0-9a-f]*}}
 # CHECK-NEXT:   }
 # CHECK-NEXT:   Symbol {
-# CHECK-NEXT:     Name: _main (9)
-# CHECK-NEXT:     Extern
+# CHECK-NEXT:     Name: __dyld_private
 # CHECK-NEXT:     Type: Section (0xE)
-# CHECK-NEXT:     Section: __text (0x1)
+# CHECK-NEXT:     Section: __data (0x4)
 # CHECK-NEXT:     RefType: UndefinedNonLazy (0x0)
 # CHECK-NEXT:     Flags [ (0x0)
 # CHECK-NEXT:     ]
 # CHECK-NEXT:     Value: 0x1{{[0-9a-f]*}}
 # CHECK-NEXT:   }
 # CHECK-NEXT:   Symbol {
-# CHECK-NEXT:     Name: _external (55)
+# CHECK-NEXT:     Name: _main
 # CHECK-NEXT:     Extern
 # CHECK-NEXT:     Type: Section (0xE)
-# CHECK-NEXT:     Section: __data (0x4)
+# CHECK-NEXT:     Section: __text (0x1)
 # CHECK-NEXT:     RefType: UndefinedNonLazy (0x0)
 # CHECK-NEXT:     Flags [ (0x0)
 # CHECK-NEXT:     ]
 # CHECK-NEXT:     Value: 0x1{{[0-9a-f]*}}
 # CHECK-NEXT:   }
 # CHECK-NEXT:   Symbol {
-# CHECK-NEXT:     Name: _external_weak (65)
+# CHECK-NEXT:     Name: _external
 # CHECK-NEXT:     Extern
 # CHECK-NEXT:     Type: Section (0xE)
-# CHECK-NEXT:     Section: __text (0x1)
+# CHECK-NEXT:     Section: __data (0x4)
 # CHECK-NEXT:     RefType: UndefinedNonLazy (0x0)
-# CHECK-NEXT:     Flags [ (0x80)
-# CHECK-NEXT:       WeakDef (0x80)
+# CHECK-NEXT:     Flags [ (0x0)
 # CHECK-NEXT:     ]
 # CHECK-NEXT:     Value: 0x1{{[0-9a-f]*}}
 # CHECK-NEXT:   }
 # CHECK-NEXT:   Symbol {
-# CHECK-NEXT:     Name: __dyld_private (103)
+# CHECK-NEXT:     Name: _external_weak
 # CHECK-NEXT:     Extern
 # CHECK-NEXT:     Type: Section (0xE)
-# CHECK-NEXT:     Section: __data (0x4)
+# CHECK-NEXT:     Section: __text (0x1)
 # CHECK-NEXT:     RefType: UndefinedNonLazy (0x0)
-# CHECK-NEXT:     Flags [ (0x0)
+# CHECK-NEXT:     Flags [ (0x80)
+# CHECK-NEXT:       WeakDef (0x80)
 # CHECK-NEXT:     ]
 # CHECK-NEXT:     Value: 0x1{{[0-9a-f]*}}
 # CHECK-NEXT:   }
 # CHECK-NEXT:   Symbol {
-# CHECK-NEXT:     Name: dyld_stub_binder (15)
+# CHECK-NEXT:     Name: dyld_stub_binder
 # CHECK-NEXT:     Extern
 # CHECK-NEXT:     Type: Undef (0x0)
 # CHECK-NEXT:     Section:  (0x0)
@@ -68,7 +67,7 @@
 # CHECK-NEXT:     Value: 0x0
 # CHECK-NEXT:   }
 # CHECK-NEXT:   Symbol {
-# CHECK-NEXT:     Name: _dynamic (80)
+# CHECK-NEXT:     Name: _dynamic
 # CHECK-NEXT:     Extern
 # CHECK-NEXT:     Type: Undef (0x0)
 # CHECK-NEXT:     Section:  (0x0)
@@ -81,23 +80,25 @@
 # CHECK-NEXT: ]
 # CHECK-NEXT: Dysymtab {
 # CHECK-NEXT:   ilocalsym: 0
-# CHECK-NEXT:   nlocalsym: 1
-# CHECK-NEXT:   iextdefsym: 1
-# CHECK-NEXT:   nextdefsym: 4
+# CHECK-NEXT:   nlocalsym: 2
+# CHECK-NEXT:   iextdefsym: 2
+# CHECK-NEXT:   nextdefsym: 3
 # CHECK-NEXT:   iundefsym: 5
 # CHECK-NEXT:   nundefsym: 2
 
-## Verify that the first entry in the StringTable is a space.
+## Verify that the first entry in the StringTable is a space, and that
+## unreferenced symbols aren't emitted.
 # RUN: obj2yaml %t/test | FileCheck %s --check-prefix=YAML
 # YAML:      StringTable:
 # YAML-NEXT: ' '
+# YAML-NOT: _unreferenced
 
 #--- libfoo.s
 .globl _dynamic
 _dynamic:
 
 #--- test.s
-.globl _main, _external, _external_weak
+.globl _main, _external, _external_weak, _unreferenced
 
 .data
 _external:
diff --git a/lld/test/MachO/weak-definition-direct-fetch.s b/lld/test/MachO/weak-definition-direct-fetch.s
index 38b809c964817..28bbe65f05f10 100644
--- a/lld/test/MachO/weak-definition-direct-fetch.s
+++ b/lld/test/MachO/weak-definition-direct-fetch.s
@@ -1,12 +1,12 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
+# RUN: rm -rf %t; split-file %s %t
 
 ## This test exercises the various possible combinations of weak and non-weak
 ## symbols that get referenced directly by a relocation in an object file.
 
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
-# RUN: echo ".globl _foo; .section __TEXT,nonweak; _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/foo.o
-# RUN: echo ".globl _foo; .weak_definition _foo; .section __TEXT,weak; _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/weakfoo.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/foo.s -o %t/foo.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/weakfoo.s -o %t/weakfoo.o
 
 # RUN: %lld -dylib -install_name \
 # RUN:   @executable_path/libfoo.dylib %t/foo.o -o %t/libfoo.dylib
@@ -24,9 +24,7 @@
 # RUN: llvm-nm %t/libweakfoo.dylib 2>&1 | FileCheck %s --check-prefix=NOSYM
 # NOSYM: no symbols
 
-# RUN: rm -f %t/foo.a
 # RUN: llvm-ar --format=darwin rcs %t/foo.a %t/foo.o
-# RUN: rm -f %t/weakfoo.a
 # RUN: llvm-ar --format=darwin rcs %t/weakfoo.a %t/weakfoo.o
 
 ## End of input file setup. The following lines check which symbol "wins" when
@@ -84,6 +82,18 @@
 # RUN: %lld -lSystem -o %t/nonweak-ar-weak-obj -L%t %t/foo.a %t/weakfoo.o %t/test.o
 # RUN: llvm-objdump --macho --lazy-bind --syms %t/nonweak-ar-weak-obj | FileCheck %s --check-prefix=PREFER-WEAK-OBJECT
 
+#--- foo.s
+.globl _foo
+.section __TEXT,nonweak
+_foo:
+
+#--- weakfoo.s
+.globl _foo
+.weak_definition _foo
+.section __TEXT,weak
+_foo:
+
+#--- test.s
 .globl _main
 _main:
   callq _foo
diff --git a/lld/test/MachO/weak-definition-indirect-fetch.s b/lld/test/MachO/weak-definition-indirect-fetch.s
index 3a45852115e01..46ed62441b89a 100644
--- a/lld/test/MachO/weak-definition-indirect-fetch.s
+++ b/lld/test/MachO/weak-definition-indirect-fetch.s
@@ -1,5 +1,5 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
+# RUN: rm -rf %t; split-file %s %t
 
 ## This tests examines the effect of .weak_definition on symbols in an archive
 ## that are not referenced directly, but which are still loaded due to some
@@ -9,13 +9,11 @@
 ## will be fetched when linking against the main test file due to its references
 ## to _bar and _baz.
 
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
-# RUN: echo ".globl _foo, _bar; .section __TEXT,nonweak; _bar: _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/foo.o
-# RUN: echo ".globl _foo, _baz; .weak_definition _foo; .section __TEXT,weak; _baz: _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/weakfoo.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/foo.s -o %t/foo.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/weakfoo.s -o %t/weakfoo.o
 
-# RUN: rm -f %t/foo.a
 # RUN: llvm-ar --format=darwin rcs %t/foo.a %t/foo.o
-# RUN: rm -f %t/weakfoo.a
 # RUN: llvm-ar --format=darwin rcs %t/weakfoo.a %t/weakfoo.o
 
 # PREFER-NONWEAK-OBJECT: O __TEXT,nonweak _foo
@@ -35,6 +33,20 @@
 # RUN: %lld -lSystem -o %t/nonweak-ar-weak-obj -L%t %t/foo.a %t/weakfoo.o %t/test.o
 # RUN: llvm-objdump --syms %t/nonweak-ar-weak-obj | FileCheck %s --check-prefix=PREFER-NONWEAK-OBJECT
 
+#--- foo.s
+.globl _foo, _bar
+.section __TEXT,nonweak
+_bar:
+_foo:
+
+#--- weakfoo.s
+.globl _foo, _baz
+.weak_definition _foo
+.section __TEXT,weak
+_baz:
+_foo:
+
+#--- test.s
 .globl _main
 _main:
   callq _bar
diff --git a/lld/test/MachO/weak-definition-order.s b/lld/test/MachO/weak-definition-order.s
index 01875e82d5641..addf6ab8f8ec5 100644
--- a/lld/test/MachO/weak-definition-order.s
+++ b/lld/test/MachO/weak-definition-order.s
@@ -1,13 +1,13 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
+# RUN: rm -rf %t; split-file %s %t
 
 ## This test demonstrates that when we have two weak symbols of the same type,
 ## we pick the one whose containing file appears earlier in the command-line
 ## invocation.
 
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
-# RUN: echo ".globl _foo; .weak_definition _foo; .section __TEXT,weak1; _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/weak1.o
-# RUN: echo ".globl _foo; .weak_definition _foo; .section __TEXT,weak2; _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/weak2.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/weak1.s -o %t/weak1.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/weak2.s -o %t/weak2.o
 
 # RUN: %lld -lSystem -o %t/obj12 -L%t %t/weak1.o %t/weak2.o %t/test.o
 # RUN: llvm-objdump --syms %t/obj12 | FileCheck %s --check-prefix=WEAK1
@@ -29,6 +29,19 @@
 # DYLIB1: __DATA   __la_symbol_ptr    0x{{[0-9a-f]*}} pointer 0 libweak1         _foo
 # DYLIB2: __DATA   __la_symbol_ptr    0x{{[0-9a-f]*}} pointer 0 libweak2         _foo
 
+#--- weak1.s
+.globl _foo
+.weak_definition _foo
+.section __TEXT,weak1;
+_foo:
+
+#--- weak2.s
+.globl _foo
+.weak_definition _foo
+.section __TEXT,weak2
+_foo:
+
+#--- test.s
 .globl _main
 _main:
   callq _foo
diff --git a/lld/test/MachO/weak-definition-over-dysym.s b/lld/test/MachO/weak-definition-over-dysym.s
index ec1f3353c7c38..ff677a9d4a3f5 100644
--- a/lld/test/MachO/weak-definition-over-dysym.s
+++ b/lld/test/MachO/weak-definition-over-dysym.s
@@ -1,22 +1,19 @@
 # REQUIRES: x86
-# RUN: mkdir -p %t
+# RUN: rm -rf %t; split-file %s %t
 
 ## This test demonstrates that when an archive file is fetched, its symbols
 ## always override any conflicting dylib symbols, regardless of any weak
 ## definition flags.
 
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
-# RUN: echo ".globl _foo; _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/libfoo.o
-# RUN: %lld -dylib -install_name \
-# RUN:   @executable_path/libfoo.dylib %t/libfoo.o -o %t/libfoo.dylib
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/libfoo.s -o %t/libfoo.o
+# RUN: %lld -dylib -install_name @executable_path/libfoo.dylib %t/libfoo.o -o %t/libfoo.dylib
 
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t/test.o
-# RUN: echo ".globl _foo, _bar; .section __TEXT,nonweak; _bar: _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/foo.o
-# RUN: echo ".globl _foo, _bar; .weak_definition _foo; .section __TEXT,weak; _bar: _foo:" | llvm-mc -filetype=obj -triple=x86_64-apple-darwin -o %t/weakfoo.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/test.s -o %t/test.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/foo.s -o %t/foo.o
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %t/weakfoo.s -o %t/weakfoo.o
 
-# RUN: rm -f %t/foo.a
 # RUN: llvm-ar --format=darwin rcs %t/foo.a %t/foo.o
-# RUN: rm -f %t/weakfoo.a
 # RUN: llvm-ar --format=darwin rcs %t/weakfoo.a %t/weakfoo.o
 
 # PREFER-WEAK-OBJECT: O __TEXT,weak _foo
@@ -32,6 +29,24 @@
 # RUN: %lld -lSystem -o %t/nonweak-dylib-weak-obj -L%t -lfoo %t/weakfoo.o %t/test.o
 # RUN: llvm-objdump --macho --lazy-bind --syms %t/nonweak-dylib-weak-obj | FileCheck %s --check-prefix=PREFER-WEAK-OBJECT
 
+#--- libfoo.s
+.globl _foo
+_foo:
+
+#--- foo.s
+.globl _foo, _bar
+.section __TEXT,nonweak
+_bar:
+_foo:
+
+#--- weakfoo.s
+.globl _foo, _bar
+.weak_definition _foo
+.section __TEXT,weak
+_bar:
+_foo:
+
+#--- test.s
 .globl _main
 _main:
   callq _foo
diff --git a/lld/test/MachO/weak-private-extern.s b/lld/test/MachO/weak-private-extern.s
new file mode 100644
index 0000000000000..78fb4260999c6
--- /dev/null
+++ b/lld/test/MachO/weak-private-extern.s
@@ -0,0 +1,38 @@
+# REQUIRES: x86
+
+# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-macos %s -o %t.o
+# RUN: %lld -dylib %t.o -o %t.dylib -lSystem
+# RUN: llvm-objdump --macho --weak-bind %t.dylib | FileCheck %s
+# CHECK-NOT: __got
+# CHECK-NOT: __la_symbol_ptr
+
+# RUN: llvm-objdump --macho --all-headers %t.dylib | \
+# RUN:     FileCheck --check-prefix=HEADERS %s
+# HEADERS-NOT: WEAK_DEFINES
+# HEADERS-NOT: BINDS_TO_WEAK
+
+## Check that N_WEAK_DEF isn't set in the symbol table.
+## This is different from ld64, which makes private extern weak symbols non-weak
+## for binds and relocations, but it still marks them as weak in the symbol table.
+## Since `nm -m` doesn't look at N_WEAK_DEF for N_PEXT symbols this is not
+## observable, but it feels slightly more correct.
+# RUN: llvm-readobj --syms %t.dylib | FileCheck --check-prefix=SYMS %s
+# SYMS-NOT: WeakDef (0x80)
+
+.globl _use
+_use:
+  mov _weak_private_extern_gotpcrel@GOTPCREL(%rip), %rax
+  callq _weak_private_extern
+  retq
+
+.private_extern _weak_private_extern
+.globl _weak_private_extern
+.weak_definition _weak_private_extern
+_weak_private_extern:
+  retq
+
+.private_extern _weak_private_extern_gotpcrel
+.globl _weak_private_extern_gotpcrel
+.weak_definition _weak_private_extern_gotpcrel
+_weak_private_extern_gotpcrel:
+  .quad 0x1234
diff --git a/lld/test/MachO/x86-64-reloc-unsigned.s b/lld/test/MachO/x86-64-reloc-unsigned.s
index f1afc0cb70437..5fdbdf1f0627b 100644
--- a/lld/test/MachO/x86-64-reloc-unsigned.s
+++ b/lld/test/MachO/x86-64-reloc-unsigned.s
@@ -14,6 +14,10 @@
 # RUN: llvm-objdump --macho --rebase %t-pie | FileCheck %s --check-prefix=PIE
 # RUN: %lld -platform_version macos 10.5.0 11.0 -o %t-no-pie %t.o
 # RUN: llvm-objdump --macho --rebase %t-no-pie | FileCheck %s --check-prefix=NO-PIE
+# RUN: %lld -platform_version ios-simulator 11.0.0 14.2 -o %t-pie %t.o
+# RUN: llvm-objdump --macho --rebase %t-pie | FileCheck %s --check-prefix=PIE
+# RUN: %lld -platform_version driverkit 19.0 20.0 -o %t-pie %t.o
+# RUN: llvm-objdump --macho --rebase %t-pie | FileCheck %s --check-prefix=PIE
 
 # CHECK:       Contents of section __DATA,foo:
 # CHECK-NEXT:  100001000 08100000 01000000
diff --git a/lldb/bindings/interface/SBType.i b/lldb/bindings/interface/SBType.i
index fd2dda1884549..2d9a4a4d11d1d 100644
--- a/lldb/bindings/interface/SBType.i
+++ b/lldb/bindings/interface/SBType.i
@@ -220,6 +220,9 @@ public:
     bool
     IsAnonymousType ();
 
+    bool
+    IsScopedEnumerationType ();
+
     lldb::SBType
     GetPointerType();
 
@@ -241,6 +244,9 @@ public:
     lldb::SBType
     GetCanonicalType();
 
+    lldb::SBType
+    GetEnumerationIntegerType();
+
     lldb::SBType
     GetArrayElementType ();
 
diff --git a/lldb/include/lldb/API/SBType.h b/lldb/include/lldb/API/SBType.h
index 5f487aa5d2581..529b4d0eeffc4 100644
--- a/lldb/include/lldb/API/SBType.h
+++ b/lldb/include/lldb/API/SBType.h
@@ -131,6 +131,8 @@ class SBType {
 
   bool IsAnonymousType();
 
+  bool IsScopedEnumerationType();
+
   lldb::SBType GetPointerType();
 
   lldb::SBType GetPointeeType();
@@ -150,6 +152,9 @@ class SBType {
   lldb::SBType GetVectorElementType();
 
   lldb::SBType GetCanonicalType();
+
+  lldb::SBType GetEnumerationIntegerType();
+
   // Get the "lldb::BasicType" enumeration for a type. If a type is not a basic
   // type eBasicTypeInvalid will be returned
   lldb::BasicType GetBasicType();
diff --git a/lldb/include/lldb/Interpreter/CommandInterpreter.h b/lldb/include/lldb/Interpreter/CommandInterpreter.h
index d35f7e22b9ea1..c4f9dd2fdb37e 100644
--- a/lldb/include/lldb/Interpreter/CommandInterpreter.h
+++ b/lldb/include/lldb/Interpreter/CommandInterpreter.h
@@ -265,7 +265,7 @@ class CommandInterpreter : public Broadcaster,
                       bool can_replace);
 
   lldb::CommandObjectSP GetCommandSPExact(llvm::StringRef cmd,
-                                          bool include_aliases) const;
+                                          bool include_aliases = false) const;
 
   CommandObject *GetCommandObject(llvm::StringRef cmd,
                                   StringList *matches = nullptr,
diff --git a/lldb/include/lldb/Symbol/CompilerType.h b/lldb/include/lldb/Symbol/CompilerType.h
index f1cde0ac30849..5a0e8e57200df 100644
--- a/lldb/include/lldb/Symbol/CompilerType.h
+++ b/lldb/include/lldb/Symbol/CompilerType.h
@@ -82,6 +82,8 @@ class CompilerType {
 
   bool IsAnonymousType() const;
 
+  bool IsScopedEnumerationType() const;
+
   bool IsBeingDefined() const;
 
   bool IsCharType() const;
@@ -185,6 +187,8 @@ class CompilerType {
 
   CompilerType GetFullyUnqualifiedType() const;
 
+  CompilerType GetEnumerationIntegerType() const;
+
   /// Returns -1 if this isn't a function of if the function doesn't
   /// have a prototype Returns a value >= 0 if there is a prototype.
   int GetFunctionArgumentCount() const;
diff --git a/lldb/include/lldb/Symbol/TypeSystem.h b/lldb/include/lldb/Symbol/TypeSystem.h
index 4c51d290ad2c5..1fad8f61ac370 100644
--- a/lldb/include/lldb/Symbol/TypeSystem.h
+++ b/lldb/include/lldb/Symbol/TypeSystem.h
@@ -175,6 +175,8 @@ class TypeSystem : public PluginInterface {
     return false;
   }
 
+  virtual bool IsScopedEnumerationType(lldb::opaque_compiler_type_t type) = 0;
+
   virtual bool IsPossibleDynamicType(lldb::opaque_compiler_type_t type,
                                      CompilerType *target_type, // Can pass NULL
                                      bool check_cplusplus, bool check_objc) = 0;
@@ -225,6 +227,9 @@ class TypeSystem : public PluginInterface {
 
   virtual CompilerType GetCanonicalType(lldb::opaque_compiler_type_t type) = 0;
 
+  virtual CompilerType
+  GetEnumerationIntegerType(lldb::opaque_compiler_type_t type) = 0;
+
   // Returns -1 if this isn't a function of if the function doesn't have a
   // prototype Returns a value >= 0 if there is a prototype.
   virtual int GetFunctionArgumentCount(lldb::opaque_compiler_type_t type) = 0;
diff --git a/lldb/include/lldb/Utility/Timer.h b/lldb/include/lldb/Utility/Timer.h
index f97315b2db0fc..91f9c57c03c15 100644
--- a/lldb/include/lldb/Utility/Timer.h
+++ b/lldb/include/lldb/Utility/Timer.h
@@ -73,4 +73,11 @@ class Timer {
 
 } // namespace lldb_private
 
+#define LLDB_SCOPED_TIMER()                                                    \
+  static ::lldb_private::Timer::Category _cat(LLVM_PRETTY_FUNCTION);           \
+  ::lldb_private::Timer _scoped_timer(_cat, LLVM_PRETTY_FUNCTION)
+#define LLDB_SCOPED_TIMERF(...)                                                \
+  static ::lldb_private::Timer::Category _cat(LLVM_PRETTY_FUNCTION);           \
+  ::lldb_private::Timer _scoped_timer(_cat, __VA_ARGS__)
+
 #endif // LLDB_UTILITY_TIMER_H
diff --git a/lldb/include/lldb/lldb-enumerations.h b/lldb/include/lldb/lldb-enumerations.h
index ff4e15e7e070b..2679ee52136dc 100644
--- a/lldb/include/lldb/lldb-enumerations.h
+++ b/lldb/include/lldb/lldb-enumerations.h
@@ -816,7 +816,6 @@ enum TemplateArgumentKind {
   eTemplateArgumentKindExpression,
   eTemplateArgumentKindPack,
   eTemplateArgumentKindNullPtr,
-  eTemplateArgumentKindUncommonValue,
 };
 
 /// Options that can be set for a formatter to alter its behavior. Not
diff --git a/lldb/packages/Python/lldbsuite/test/decorators.py b/lldb/packages/Python/lldbsuite/test/decorators.py
index a17cd6ea33ab1..ff445fa0b926e 100644
--- a/lldb/packages/Python/lldbsuite/test/decorators.py
+++ b/lldb/packages/Python/lldbsuite/test/decorators.py
@@ -373,13 +373,11 @@ def should_skip_simulator_test():
 
 def debugserver_test(func):
     """Decorate the item as a debugserver test."""
-    func.debug_server = "debugserver"
     return add_test_categories(["debugserver"])(func)
 
 
 def llgs_test(func):
     """Decorate the item as a lldb-server test."""
-    func.debug_server = "llgs"
     return add_test_categories(["llgs"])(func)
 
 
diff --git a/lldb/packages/Python/lldbsuite/test/dotest.py b/lldb/packages/Python/lldbsuite/test/dotest.py
index 86ea34ee25821..c728bf3292029 100644
--- a/lldb/packages/Python/lldbsuite/test/dotest.py
+++ b/lldb/packages/Python/lldbsuite/test/dotest.py
@@ -852,11 +852,20 @@ def checkDebugInfoSupport():
 
 def checkDebugServerSupport():
     from lldbsuite.test import lldbplatformutil
+    import lldb
 
+    skip_msg = "Skipping %s tests, as they are not compatible with remote testing on this platform"
     if lldbplatformutil.platformIsDarwin():
         configuration.skip_categories.append("llgs")
+        if lldb.remote_platform:
+            # <rdar://problem/34539270>
+            configuration.skip_categories.append("debugserver")
+            print(skip_msg%"debugserver");
     else:
         configuration.skip_categories.append("debugserver")
+        if lldb.remote_platform and lldbplatformutil.getPlatform() == "windows":
+            configuration.skip_categories.append("llgs")
+            print(skip_msg%"lldb-server");
 
 def run_suite():
     # On MacOS X, check to make sure that domain for com.apple.DebugSymbols defaults
diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
index 0e3cde01520a0..71e75adbecb70 100644
--- a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
+++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
@@ -27,6 +27,39 @@ class _ConnectionRefused(IOError):
     pass
 
 
+class GdbRemoteTestCaseFactory(type):
+
+    def __new__(cls, name, bases, attrs):
+        newattrs = {}
+        for attrname, attrvalue in attrs.items():
+            if not attrname.startswith("test"):
+                newattrs[attrname] = attrvalue
+                continue
+
+            # If any debug server categories were explicitly tagged, assume
+            # that list to be authoritative. If none were specified, try
+            # all of them.
+            all_categories = set(["debugserver", "llgs"])
+            categories = set(
+                getattr(attrvalue, "categories", [])) & all_categories
+            if not categories:
+                categories = all_categories
+
+            for cat in categories:
+                @decorators.add_test_categories([cat])
+                @wraps(attrvalue)
+                def test_method(self, attrvalue=attrvalue):
+                    return attrvalue(self)
+
+                method_name = attrname + "_" + cat
+                test_method.__name__ = method_name
+                test_method.debug_server = cat
+                newattrs[method_name] = test_method
+
+        return super(GdbRemoteTestCaseFactory, cls).__new__(
+                cls, name, bases, newattrs)
+
+@add_metaclass(GdbRemoteTestCaseFactory)
 class GdbRemoteTestCaseBase(Base):
 
     # Default time out in seconds. The timeout is increased tenfold under Asan.
@@ -166,9 +199,7 @@ def _init_llgs_test(self):
             # Reverse connections may be tricky due to firewalls/NATs.
             reverse_connect = False
 
-            triple = self.dbg.GetSelectedPlatform().GetTriple()
-            if re.match(".*-.*-windows", triple):
-                self.skipTest("Remotely testing is not supported on Windows yet.")
+            # FIXME: This is extremely linux-oriented
 
             # Grab the ppid from /proc/[shell pid]/stat
             err, retcode, shell_stat = self.run_platform_command(
diff --git a/lldb/source/API/SBType.cpp b/lldb/source/API/SBType.cpp
index 0a99ac0f22923..550c4b065914a 100644
--- a/lldb/source/API/SBType.cpp
+++ b/lldb/source/API/SBType.cpp
@@ -271,6 +271,14 @@ bool SBType::IsAnonymousType() {
   return m_opaque_sp->GetCompilerType(true).IsAnonymousType();
 }
 
+bool SBType::IsScopedEnumerationType() {
+  LLDB_RECORD_METHOD_NO_ARGS(bool, SBType, IsScopedEnumerationType);
+
+  if (!IsValid())
+    return false;
+  return m_opaque_sp->GetCompilerType(true).IsScopedEnumerationType();
+}
+
 lldb::SBType SBType::GetFunctionReturnType() {
   LLDB_RECORD_METHOD_NO_ARGS(lldb::SBType, SBType, GetFunctionReturnType);
 
@@ -336,6 +344,16 @@ lldb::SBType SBType::GetCanonicalType() {
   return LLDB_RECORD_RESULT(SBType());
 }
 
+SBType SBType::GetEnumerationIntegerType() {
+  LLDB_RECORD_METHOD_NO_ARGS(lldb::SBType, SBType, GetEnumerationIntegerType);
+
+  if (IsValid()) {
+    return LLDB_RECORD_RESULT(
+        SBType(m_opaque_sp->GetCompilerType(true).GetEnumerationIntegerType()));
+  }
+  return LLDB_RECORD_RESULT(SBType());
+}
+
 lldb::BasicType SBType::GetBasicType() {
   LLDB_RECORD_METHOD_NO_ARGS(lldb::BasicType, SBType, GetBasicType);
 
@@ -935,6 +953,7 @@ void RegisterMethods<SBType>(Registry &R) {
   LLDB_REGISTER_METHOD(bool, SBType, IsPolymorphicClass, ());
   LLDB_REGISTER_METHOD(bool, SBType, IsTypedefType, ());
   LLDB_REGISTER_METHOD(bool, SBType, IsAnonymousType, ());
+  LLDB_REGISTER_METHOD(bool, SBType, IsScopedEnumerationType, ());
   LLDB_REGISTER_METHOD(lldb::SBType, SBType, GetFunctionReturnType, ());
   LLDB_REGISTER_METHOD(lldb::SBTypeList, SBType, GetFunctionArgumentTypes,
                        ());
@@ -943,6 +962,7 @@ void RegisterMethods<SBType>(Registry &R) {
                        GetMemberFunctionAtIndex, (uint32_t));
   LLDB_REGISTER_METHOD(lldb::SBType, SBType, GetUnqualifiedType, ());
   LLDB_REGISTER_METHOD(lldb::SBType, SBType, GetCanonicalType, ());
+  LLDB_REGISTER_METHOD(lldb::SBType, SBType, GetEnumerationIntegerType, ());
   LLDB_REGISTER_METHOD(lldb::BasicType, SBType, GetBasicType, ());
   LLDB_REGISTER_METHOD(lldb::SBType, SBType, GetBasicType, (lldb::BasicType));
   LLDB_REGISTER_METHOD(uint32_t, SBType, GetNumberOfDirectBaseClasses, ());
diff --git a/lldb/source/API/SystemInitializerFull.cpp b/lldb/source/API/SystemInitializerFull.cpp
index a6421d8f10d0c..0530f94580b3e 100644
--- a/lldb/source/API/SystemInitializerFull.cpp
+++ b/lldb/source/API/SystemInitializerFull.cpp
@@ -69,9 +69,6 @@ llvm::Error SystemInitializerFull::Initialize() {
 }
 
 void SystemInitializerFull::Terminate() {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
-
   Debugger::SettingsTerminate();
 
   // Terminate plug-ins in core LLDB
diff --git a/lldb/source/Commands/CommandObjectCommands.cpp b/lldb/source/Commands/CommandObjectCommands.cpp
index 0c441dd69c487..3b3cdde6ab9a6 100644
--- a/lldb/source/Commands/CommandObjectCommands.cpp
+++ b/lldb/source/Commands/CommandObjectCommands.cpp
@@ -464,7 +464,7 @@ rather than using a positional placeholder:"
         OptionArgVectorSP(new OptionArgVector);
 
     if (CommandObjectSP cmd_obj_sp =
-            m_interpreter.GetCommandSPExact(cmd_obj.GetCommandName(), false)) {
+            m_interpreter.GetCommandSPExact(cmd_obj.GetCommandName())) {
       if (m_interpreter.AliasExists(alias_command) ||
           m_interpreter.UserCommandExists(alias_command)) {
         result.AppendWarningWithFormat(
@@ -558,10 +558,9 @@ rather than using a positional placeholder:"
 
     if (!args.empty()) {
       CommandObjectSP tmp_sp =
-          m_interpreter.GetCommandSPExact(cmd_obj->GetCommandName(), false);
+          m_interpreter.GetCommandSPExact(cmd_obj->GetCommandName());
       if (use_subcommand)
-        tmp_sp = m_interpreter.GetCommandSPExact(sub_cmd_obj->GetCommandName(),
-                                                 false);
+        tmp_sp = m_interpreter.GetCommandSPExact(sub_cmd_obj->GetCommandName());
 
       args.GetCommandString(args_string);
     }
diff --git a/lldb/source/Commands/CommandObjectTarget.cpp b/lldb/source/Commands/CommandObjectTarget.cpp
index c033493d4196c..4bce4e7e0734a 100644
--- a/lldb/source/Commands/CommandObjectTarget.cpp
+++ b/lldb/source/Commands/CommandObjectTarget.cpp
@@ -299,8 +299,7 @@ class CommandObjectTargetCreate : public CommandObjectParsed {
       }
 
       const char *file_path = command.GetArgumentAtIndex(0);
-      static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-      Timer scoped_timer(func_cat, "(lldb) target create '%s'", file_path);
+      LLDB_SCOPED_TIMERF("(lldb) target create '%s'", file_path);
       FileSpec file_spec;
 
       if (file_path) {
diff --git a/lldb/source/Core/Disassembler.cpp b/lldb/source/Core/Disassembler.cpp
index 1015eafd252e8..3a975d9296f47 100644
--- a/lldb/source/Core/Disassembler.cpp
+++ b/lldb/source/Core/Disassembler.cpp
@@ -58,9 +58,7 @@ using namespace lldb_private;
 DisassemblerSP Disassembler::FindPlugin(const ArchSpec &arch,
                                         const char *flavor,
                                         const char *plugin_name) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "Disassembler::FindPlugin (arch = %s, plugin_name = %s)",
+  LLDB_SCOPED_TIMERF("Disassembler::FindPlugin (arch = %s, plugin_name = %s)",
                      arch.GetArchitectureName(), plugin_name);
 
   DisassemblerCreateInstance create_callback = nullptr;
diff --git a/lldb/source/Core/Mangled.cpp b/lldb/source/Core/Mangled.cpp
index 143ec8770bf47..627be94a303c6 100644
--- a/lldb/source/Core/Mangled.cpp
+++ b/lldb/source/Core/Mangled.cpp
@@ -14,7 +14,6 @@
 #include "lldb/Utility/Logging.h"
 #include "lldb/Utility/RegularExpression.h"
 #include "lldb/Utility/Stream.h"
-#include "lldb/Utility/Timer.h"
 #include "lldb/lldb-enumerations.h"
 
 #include "Plugins/Language/CPlusPlus/CPlusPlusLanguage.h"
@@ -227,12 +226,6 @@ static char *GetItaniumDemangledStr(const char *M) {
 // makes use of ItaniumPartialDemangler's rich demangle info
 bool Mangled::DemangleWithRichManglingInfo(
     RichManglingContext &context, SkipMangledNameFn *skip_mangled_name) {
-  // We need to generate and cache the demangled name.
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "Mangled::DemangleWithRichNameIndexInfo (m_mangled = %s)",
-                     m_mangled.GetCString());
-
   // Others are not meant to arrive here. ObjC names or C's main() for example
   // have their names stored in m_demangled, while m_mangled is empty.
   assert(m_mangled);
@@ -298,11 +291,6 @@ ConstString Mangled::GetDemangledName() const {
   // Check to make sure we have a valid mangled name and that we haven't
   // already decoded our mangled name.
   if (m_mangled && m_demangled.IsNull()) {
-    // We need to generate and cache the demangled name.
-    static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-    Timer scoped_timer(func_cat, "Mangled::GetDemangledName (m_mangled = %s)",
-                       m_mangled.GetCString());
-
     // Don't bother running anything that isn't mangled
     const char *mangled_name = m_mangled.GetCString();
     ManglingScheme mangling_scheme = GetManglingScheme(m_mangled.GetStringRef());
diff --git a/lldb/source/Core/Module.cpp b/lldb/source/Core/Module.cpp
index b76659ee3e074..1f9987c216588 100644
--- a/lldb/source/Core/Module.cpp
+++ b/lldb/source/Core/Module.cpp
@@ -419,8 +419,7 @@ void Module::DumpSymbolContext(Stream *s) {
 
 size_t Module::GetNumCompileUnits() {
   std::lock_guard<std::recursive_mutex> guard(m_mutex);
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "Module::GetNumCompileUnits (module = %p)",
+  LLDB_SCOPED_TIMERF("Module::GetNumCompileUnits (module = %p)",
                      static_cast<void *>(this));
   if (SymbolFile *symbols = GetSymbolFile())
     return symbols->GetNumCompileUnits();
@@ -441,9 +440,7 @@ CompUnitSP Module::GetCompileUnitAtIndex(size_t index) {
 
 bool Module::ResolveFileAddress(lldb::addr_t vm_addr, Address &so_addr) {
   std::lock_guard<std::recursive_mutex> guard(m_mutex);
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "Module::ResolveFileAddress (vm_addr = 0x%" PRIx64 ")",
+  LLDB_SCOPED_TIMERF("Module::ResolveFileAddress (vm_addr = 0x%" PRIx64 ")",
                      vm_addr);
   SectionList *section_list = GetSectionList();
   if (section_list)
@@ -594,9 +591,7 @@ uint32_t Module::ResolveSymbolContextsForFileSpec(
     const FileSpec &file_spec, uint32_t line, bool check_inlines,
     lldb::SymbolContextItem resolve_scope, SymbolContextList &sc_list) {
   std::lock_guard<std::recursive_mutex> guard(m_mutex);
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "Module::ResolveSymbolContextForFilePath (%s:%u, "
+  LLDB_SCOPED_TIMERF("Module::ResolveSymbolContextForFilePath (%s:%u, "
                      "check_inlines = %s, resolve_scope = 0x%8.8x)",
                      file_spec.GetPath().c_str(), line,
                      check_inlines ? "yes" : "no", resolve_scope);
@@ -940,8 +935,7 @@ void Module::FindTypes_Impl(
     size_t max_matches,
     llvm::DenseSet<lldb_private::SymbolFile *> &searched_symbol_files,
     TypeMap &types) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
   if (SymbolFile *symbols = GetSymbolFile())
     symbols->FindTypes(name, parent_decl_ctx, max_matches,
                        searched_symbol_files, types);
@@ -1028,8 +1022,7 @@ void Module::FindTypes(
     llvm::ArrayRef<CompilerContext> pattern, LanguageSet languages,
     llvm::DenseSet<lldb_private::SymbolFile *> &searched_symbol_files,
     TypeMap &types) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
   if (SymbolFile *symbols = GetSymbolFile())
     symbols->FindTypes(pattern, languages, searched_symbol_files, types);
 }
@@ -1040,8 +1033,7 @@ SymbolFile *Module::GetSymbolFile(bool can_create, Stream *feedback_strm) {
     if (!m_did_load_symfile.load() && can_create) {
       ObjectFile *obj_file = GetObjectFile();
       if (obj_file != nullptr) {
-        static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-        Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+        LLDB_SCOPED_TIMER();
         m_symfile_up.reset(
             SymbolVendor::FindPlugin(shared_from_this(), feedback_strm));
         m_did_load_symfile = true;
@@ -1244,8 +1236,7 @@ ObjectFile *Module::GetObjectFile() {
   if (!m_did_load_objfile.load()) {
     std::lock_guard<std::recursive_mutex> guard(m_mutex);
     if (!m_did_load_objfile.load()) {
-      static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-      Timer scoped_timer(func_cat, "Module::GetObjectFile () module = %s",
+      LLDB_SCOPED_TIMERF("Module::GetObjectFile () module = %s",
                          GetFileSpec().GetFilename().AsCString(""));
       lldb::offset_t data_offset = 0;
       lldb::offset_t file_size = 0;
@@ -1312,9 +1303,8 @@ SectionList *Module::GetUnifiedSectionList() {
 
 const Symbol *Module::FindFirstSymbolWithNameAndType(ConstString name,
                                                      SymbolType symbol_type) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(
-      func_cat, "Module::FindFirstSymbolWithNameAndType (name = %s, type = %i)",
+  LLDB_SCOPED_TIMERF(
+      "Module::FindFirstSymbolWithNameAndType (name = %s, type = %i)",
       name.AsCString(), symbol_type);
   if (Symtab *symtab = GetSymtab())
     return symtab->FindFirstSymbolWithNameAndType(
@@ -1342,9 +1332,7 @@ void Module::SymbolIndicesToSymbolContextList(
 void Module::FindFunctionSymbols(ConstString name,
                                    uint32_t name_type_mask,
                                    SymbolContextList &sc_list) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "Module::FindSymbolsFunctions (name = %s, mask = 0x%8.8x)",
+  LLDB_SCOPED_TIMERF("Module::FindSymbolsFunctions (name = %s, mask = 0x%8.8x)",
                      name.AsCString(), name_type_mask);
   if (Symtab *symtab = GetSymtab())
     symtab->FindFunctionSymbols(name, name_type_mask, sc_list);
@@ -1355,10 +1343,8 @@ void Module::FindSymbolsWithNameAndType(ConstString name,
                                           SymbolContextList &sc_list) {
   // No need to protect this call using m_mutex all other method calls are
   // already thread safe.
-
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(
-      func_cat, "Module::FindSymbolsWithNameAndType (name = %s, type = %i)",
+  LLDB_SCOPED_TIMERF(
+      "Module::FindSymbolsWithNameAndType (name = %s, type = %i)",
       name.AsCString(), symbol_type);
   if (Symtab *symtab = GetSymtab()) {
     std::vector<uint32_t> symbol_indexes;
@@ -1372,10 +1358,7 @@ void Module::FindSymbolsMatchingRegExAndType(const RegularExpression &regex,
                                              SymbolContextList &sc_list) {
   // No need to protect this call using m_mutex all other method calls are
   // already thread safe.
-
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(
-      func_cat,
+  LLDB_SCOPED_TIMERF(
       "Module::FindSymbolsMatchingRegExAndType (regex = %s, type = %i)",
       regex.GetText().str().c_str(), symbol_type);
   if (Symtab *symtab = GetSymtab()) {
diff --git a/lldb/source/Initialization/SystemInitializerCommon.cpp b/lldb/source/Initialization/SystemInitializerCommon.cpp
index b29138c4884f6..d9f69f57703c7 100644
--- a/lldb/source/Initialization/SystemInitializerCommon.cpp
+++ b/lldb/source/Initialization/SystemInitializerCommon.cpp
@@ -131,8 +131,7 @@ llvm::Error SystemInitializerCommon::Initialize() {
   if (error)
     return error;
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
 
   process_gdb_remote::ProcessGDBRemoteLog::Initialize();
 
@@ -147,8 +146,7 @@ llvm::Error SystemInitializerCommon::Initialize() {
 }
 
 void SystemInitializerCommon::Terminate() {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
 
 #if defined(_WIN32)
   ProcessWindowsLog::Terminate();
diff --git a/lldb/source/Interpreter/CommandInterpreter.cpp b/lldb/source/Interpreter/CommandInterpreter.cpp
index 4d33d17289074..fb503fe0afb0e 100644
--- a/lldb/source/Interpreter/CommandInterpreter.cpp
+++ b/lldb/source/Interpreter/CommandInterpreter.cpp
@@ -224,8 +224,7 @@ bool CommandInterpreter::GetSpaceReplPrompts() const {
 }
 
 void CommandInterpreter::Initialize() {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
 
   CommandReturnObject result(m_debugger.GetUseColor());
 
@@ -235,48 +234,48 @@ void CommandInterpreter::Initialize() {
   OptionArgVectorSP alias_arguments_vector_sp(new OptionArgVector);
 
   // Set up some initial aliases.
-  CommandObjectSP cmd_obj_sp = GetCommandSPExact("quit", false);
+  CommandObjectSP cmd_obj_sp = GetCommandSPExact("quit");
   if (cmd_obj_sp) {
     AddAlias("q", cmd_obj_sp);
     AddAlias("exit", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-attach", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-attach");
   if (cmd_obj_sp)
     AddAlias("attach", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
 
-  cmd_obj_sp = GetCommandSPExact("process detach", false);
+  cmd_obj_sp = GetCommandSPExact("process detach");
   if (cmd_obj_sp) {
     AddAlias("detach", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("process continue", false);
+  cmd_obj_sp = GetCommandSPExact("process continue");
   if (cmd_obj_sp) {
     AddAlias("c", cmd_obj_sp);
     AddAlias("continue", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-break", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-break");
   if (cmd_obj_sp)
     AddAlias("b", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-tbreak", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-tbreak");
   if (cmd_obj_sp)
     AddAlias("tbreak", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
 
-  cmd_obj_sp = GetCommandSPExact("thread step-inst", false);
+  cmd_obj_sp = GetCommandSPExact("thread step-inst");
   if (cmd_obj_sp) {
     AddAlias("stepi", cmd_obj_sp);
     AddAlias("si", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("thread step-inst-over", false);
+  cmd_obj_sp = GetCommandSPExact("thread step-inst-over");
   if (cmd_obj_sp) {
     AddAlias("nexti", cmd_obj_sp);
     AddAlias("ni", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("thread step-in", false);
+  cmd_obj_sp = GetCommandSPExact("thread step-in");
   if (cmd_obj_sp) {
     AddAlias("s", cmd_obj_sp);
     AddAlias("step", cmd_obj_sp);
@@ -290,86 +289,86 @@ void CommandInterpreter::Initialize() {
     }
   }
 
-  cmd_obj_sp = GetCommandSPExact("thread step-over", false);
+  cmd_obj_sp = GetCommandSPExact("thread step-over");
   if (cmd_obj_sp) {
     AddAlias("n", cmd_obj_sp);
     AddAlias("next", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("thread step-out", false);
+  cmd_obj_sp = GetCommandSPExact("thread step-out");
   if (cmd_obj_sp) {
     AddAlias("finish", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("frame select", false);
+  cmd_obj_sp = GetCommandSPExact("frame select");
   if (cmd_obj_sp) {
     AddAlias("f", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("thread select", false);
+  cmd_obj_sp = GetCommandSPExact("thread select");
   if (cmd_obj_sp) {
     AddAlias("t", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-jump", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-jump");
   if (cmd_obj_sp) {
     AddAlias("j", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
     AddAlias("jump", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
   }
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-list", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-list");
   if (cmd_obj_sp) {
     AddAlias("l", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
     AddAlias("list", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
   }
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-env", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-env");
   if (cmd_obj_sp)
     AddAlias("env", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
 
-  cmd_obj_sp = GetCommandSPExact("memory read", false);
+  cmd_obj_sp = GetCommandSPExact("memory read");
   if (cmd_obj_sp)
     AddAlias("x", cmd_obj_sp);
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-up", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-up");
   if (cmd_obj_sp)
     AddAlias("up", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-down", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-down");
   if (cmd_obj_sp)
     AddAlias("down", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-display", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-display");
   if (cmd_obj_sp)
     AddAlias("display", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
 
-  cmd_obj_sp = GetCommandSPExact("disassemble", false);
+  cmd_obj_sp = GetCommandSPExact("disassemble");
   if (cmd_obj_sp)
     AddAlias("dis", cmd_obj_sp);
 
-  cmd_obj_sp = GetCommandSPExact("disassemble", false);
+  cmd_obj_sp = GetCommandSPExact("disassemble");
   if (cmd_obj_sp)
     AddAlias("di", cmd_obj_sp);
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-undisplay", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-undisplay");
   if (cmd_obj_sp)
     AddAlias("undisplay", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
 
-  cmd_obj_sp = GetCommandSPExact("_regexp-bt", false);
+  cmd_obj_sp = GetCommandSPExact("_regexp-bt");
   if (cmd_obj_sp)
     AddAlias("bt", cmd_obj_sp)->SetSyntax(cmd_obj_sp->GetSyntax());
 
-  cmd_obj_sp = GetCommandSPExact("target create", false);
+  cmd_obj_sp = GetCommandSPExact("target create");
   if (cmd_obj_sp)
     AddAlias("file", cmd_obj_sp);
 
-  cmd_obj_sp = GetCommandSPExact("target modules", false);
+  cmd_obj_sp = GetCommandSPExact("target modules");
   if (cmd_obj_sp)
     AddAlias("image", cmd_obj_sp);
 
   alias_arguments_vector_sp = std::make_shared<OptionArgVector>();
 
-  cmd_obj_sp = GetCommandSPExact("expression", false);
+  cmd_obj_sp = GetCommandSPExact("expression");
   if (cmd_obj_sp) {
     AddAlias("p", cmd_obj_sp, "--")->SetHelpLong("");
     AddAlias("print", cmd_obj_sp, "--")->SetHelpLong("");
@@ -399,7 +398,7 @@ void CommandInterpreter::Initialize() {
     }
   }
 
-  cmd_obj_sp = GetCommandSPExact("platform shell", false);
+  cmd_obj_sp = GetCommandSPExact("platform shell");
   if (cmd_obj_sp) {
     CommandAlias *shell_alias = AddAlias("shell", cmd_obj_sp, " --host --");
     if (shell_alias) {
@@ -409,12 +408,12 @@ void CommandInterpreter::Initialize() {
     }
   }
 
-  cmd_obj_sp = GetCommandSPExact("process kill", false);
+  cmd_obj_sp = GetCommandSPExact("process kill");
   if (cmd_obj_sp) {
     AddAlias("kill", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("process launch", false);
+  cmd_obj_sp = GetCommandSPExact("process launch");
   if (cmd_obj_sp) {
     alias_arguments_vector_sp = std::make_shared<OptionArgVector>();
 #if defined(__arm__) || defined(__arm64__) || defined(__aarch64__)
@@ -438,29 +437,29 @@ void CommandInterpreter::Initialize() {
 #endif
   }
 
-  cmd_obj_sp = GetCommandSPExact("target symbols add", false);
+  cmd_obj_sp = GetCommandSPExact("target symbols add");
   if (cmd_obj_sp) {
     AddAlias("add-dsym", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("breakpoint set", false);
+  cmd_obj_sp = GetCommandSPExact("breakpoint set");
   if (cmd_obj_sp) {
     AddAlias("rbreak", cmd_obj_sp, "--func-regex %1");
   }
 
-  cmd_obj_sp = GetCommandSPExact("frame variable", false);
+  cmd_obj_sp = GetCommandSPExact("frame variable");
   if (cmd_obj_sp) {
     AddAlias("v", cmd_obj_sp);
     AddAlias("var", cmd_obj_sp);
     AddAlias("vo", cmd_obj_sp, "--object-description");
   }
 
-  cmd_obj_sp = GetCommandSPExact("register", false);
+  cmd_obj_sp = GetCommandSPExact("register");
   if (cmd_obj_sp) {
     AddAlias("re", cmd_obj_sp);
   }
 
-  cmd_obj_sp = GetCommandSPExact("session history", false);
+  cmd_obj_sp = GetCommandSPExact("session history");
   if (cmd_obj_sp) {
     AddAlias("history", cmd_obj_sp);
   }
@@ -487,8 +486,7 @@ const char *CommandInterpreter::ProcessEmbeddedScriptCommands(const char *arg) {
   m_command_dict[NAME] = std::make_shared<CLASS>(*this);
 
 void CommandInterpreter::LoadCommandDictionary() {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
 
   REGISTER_COMMAND_OBJECT("apropos", CommandObjectApropos);
   REGISTER_COMMAND_OBJECT("breakpoint", CommandObjectMultiwordBreakpoint);
@@ -1039,47 +1037,46 @@ bool CommandInterpreter::AddUserCommand(llvm::StringRef name,
   return false;
 }
 
-CommandObjectSP CommandInterpreter::GetCommandSPExact(llvm::StringRef cmd_str,
-                                                      bool include_aliases) const {
-  Args cmd_words(cmd_str);  // Break up the command string into words, in case
-                            // it's a multi-word command.
-  CommandObjectSP ret_val;  // Possibly empty return value.
+CommandObjectSP
+CommandInterpreter::GetCommandSPExact(llvm::StringRef cmd_str,
+                                      bool include_aliases) const {
+  // Break up the command string into words, in case it's a multi-word command.
+  Args cmd_words(cmd_str);
 
   if (cmd_str.empty())
-    return ret_val;
+    return {};
 
   if (cmd_words.GetArgumentCount() == 1)
-    return GetCommandSP(cmd_str, include_aliases, true, nullptr);
-  else {
-    // We have a multi-word command (seemingly), so we need to do more work.
-    // First, get the cmd_obj_sp for the first word in the command.
-    CommandObjectSP cmd_obj_sp = GetCommandSP(llvm::StringRef(cmd_words.GetArgumentAtIndex(0)),
-                                              include_aliases, true, nullptr);
-    if (cmd_obj_sp.get() != nullptr) {
-      // Loop through the rest of the words in the command (everything passed
-      // in was supposed to be part of a command name), and find the
-      // appropriate sub-command SP for each command word....
-      size_t end = cmd_words.GetArgumentCount();
-      for (size_t j = 1; j < end; ++j) {
-        if (cmd_obj_sp->IsMultiwordObject()) {
-          cmd_obj_sp =
-              cmd_obj_sp->GetSubcommandSP(cmd_words.GetArgumentAtIndex(j));
-          if (cmd_obj_sp.get() == nullptr)
-            // The sub-command name was invalid.  Fail and return the empty
-            // 'ret_val'.
-            return ret_val;
-        } else
-          // We have more words in the command name, but we don't have a
-          // multiword object. Fail and return empty 'ret_val'.
-          return ret_val;
-      }
-      // We successfully looped through all the command words and got valid
-      // command objects for them.  Assign the last object retrieved to
-      // 'ret_val'.
-      ret_val = cmd_obj_sp;
+    return GetCommandSP(cmd_str, include_aliases, true);
+
+  // We have a multi-word command (seemingly), so we need to do more work.
+  // First, get the cmd_obj_sp for the first word in the command.
+  CommandObjectSP cmd_obj_sp =
+      GetCommandSP(cmd_words.GetArgumentAtIndex(0), include_aliases, true);
+  if (!cmd_obj_sp)
+    return {};
+
+  // Loop through the rest of the words in the command (everything passed in
+  // was supposed to be part of a command name), and find the appropriate
+  // sub-command SP for each command word....
+  size_t end = cmd_words.GetArgumentCount();
+  for (size_t i = 1; i < end; ++i) {
+    if (!cmd_obj_sp->IsMultiwordObject()) {
+      // We have more words in the command name, but we don't have a
+      // multiword object. Fail and return.
+      return {};
+    }
+
+    cmd_obj_sp = cmd_obj_sp->GetSubcommandSP(cmd_words.GetArgumentAtIndex(i));
+    if (!cmd_obj_sp) {
+      // The sub-command name was invalid.  Fail and return.
+      return {};
     }
   }
-  return ret_val;
+
+  // We successfully looped through all the command words and got valid
+  // command objects for them.
+  return cmd_obj_sp;
 }
 
 CommandObject *
@@ -1649,9 +1646,7 @@ bool CommandInterpreter::HandleCommand(const char *command_line,
                                    command_line);
 
   LLDB_LOGF(log, "Processing command: %s", command_line);
-
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "Handling command: %s.", command_line);
+  LLDB_SCOPED_TIMERF("Processing command: %s.", command_line);
 
   if (!no_context_switching)
     UpdateExecutionContext(override_context);
diff --git a/lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp b/lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
index 067f5e0883808..24ab9cc5f238f 100644
--- a/lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
+++ b/lldb/source/Plugins/LanguageRuntime/CPlusPlus/CPPLanguageRuntime.cpp
@@ -99,9 +99,7 @@ line_entry_helper(Target &target, const SymbolContext &sc, Symbol *symbol,
 CPPLanguageRuntime::LibCppStdFunctionCallableInfo
 CPPLanguageRuntime::FindLibCppStdFunctionCallableInfo(
     lldb::ValueObjectSP &valobj_sp) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "CPPLanguageRuntime::FindLibCppStdFunctionCallableInfo");
+  LLDB_SCOPED_TIMER();
 
   LibCppStdFunctionCallableInfo optional_info;
 
diff --git a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
index 6afea05c4e745..4d23443d5d3b0 100644
--- a/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
+++ b/lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
@@ -1831,10 +1831,9 @@ lldb::addr_t AppleObjCRuntimeV2::GetSharedCacheReadOnlyAddress() {
 }
 
 void AppleObjCRuntimeV2::UpdateISAToDescriptorMapIfNeeded() {
-  Log *log(GetLogIfAnyCategoriesSet(LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_TYPES));
+  LLDB_SCOPED_TIMER();
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  Log *log(GetLogIfAnyCategoriesSet(LIBLLDB_LOG_PROCESS | LIBLLDB_LOG_TYPES));
 
   // Else we need to check with our process to see when the map was updated.
   Process *process = GetProcess();
diff --git a/lldb/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp b/lldb/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp
index 83cf9f8bd2694..211eb9ce0d3aa 100644
--- a/lldb/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp
+++ b/lldb/source/Plugins/ObjectContainer/BSD-Archive/ObjectContainerBSDArchive.cpp
@@ -300,9 +300,7 @@ ObjectContainer *ObjectContainerBSDArchive::CreateInstance(
     DataExtractor data;
     data.SetData(data_sp, data_offset, length);
     if (file && data_sp && ObjectContainerBSDArchive::MagicBytesMatch(data)) {
-      static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-      Timer scoped_timer(
-          func_cat,
+      LLDB_SCOPED_TIMERF(
           "ObjectContainerBSDArchive::CreateInstance (module = %s, file = "
           "%p, file_offset = 0x%8.8" PRIx64 ", file_size = 0x%8.8" PRIx64 ")",
           module_sp->GetFileSpec().GetPath().c_str(),
diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
index bca575b7f8842..82a08a235084d 100644
--- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -576,9 +576,7 @@ size_t ObjectFileELF::GetModuleSpecifications(
             uint32_t core_notes_crc = 0;
 
             if (!gnu_debuglink_crc) {
-              static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-              lldb_private::Timer scoped_timer(
-                  func_cat,
+              LLDB_SCOPED_TIMERF(
                   "Calculating module crc32 %s with size %" PRIu64 " KiB",
                   file.GetLastPathComponent().AsCString(),
                   (length - file_offset) / 1024);
diff --git a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
index aafd5ab746b3c..463a2a52f5df6 100644
--- a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
+++ b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
@@ -2161,8 +2161,7 @@ ParseNList(DataExtractor &nlist_data, lldb::offset_t &nlist_data_offset,
 enum { DebugSymbols = true, NonDebugSymbols = false };
 
 size_t ObjectFileMachO::ParseSymtab() {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "ObjectFileMachO::ParseSymtab () module = %s",
+  LLDB_SCOPED_TIMERF("ObjectFileMachO::ParseSymtab () module = %s",
                      m_file.GetFilename().AsCString(""));
   ModuleSP module_sp(GetModule());
   if (!module_sp)
diff --git a/lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp b/lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
index b3b4a6cb05784..d5052e7d1b3af 100644
--- a/lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
+++ b/lldb/source/Plugins/Process/FreeBSDRemote/NativeRegisterContextFreeBSD_x86_64.cpp
@@ -29,9 +29,6 @@
 using namespace lldb_private;
 using namespace lldb_private::process_freebsd;
 
-// Private namespace.
-
-namespace {
 // x86 64-bit general purpose registers.
 static const uint32_t g_gpr_regnums_x86_64[] = {
     lldb_rax_x86_64,    lldb_rbx_x86_64,    lldb_rcx_x86_64, lldb_rdx_x86_64,
@@ -138,7 +135,7 @@ static_assert((sizeof(g_dbr_regnums_x86_64) / sizeof(g_dbr_regnums_x86_64[0])) -
               "g_dbr_regnums_x86_64 has wrong number of register infos");
 
 // x86 32-bit general purpose registers.
-const uint32_t g_gpr_regnums_i386[] = {
+static const uint32_t g_gpr_regnums_i386[] = {
     lldb_eax_i386,      lldb_ebx_i386,    lldb_ecx_i386, lldb_edx_i386,
     lldb_edi_i386,      lldb_esi_i386,    lldb_ebp_i386, lldb_esp_i386,
     lldb_eip_i386,      lldb_eflags_i386, lldb_cs_i386,  lldb_fs_i386,
@@ -155,7 +152,7 @@ static_assert((sizeof(g_gpr_regnums_i386) / sizeof(g_gpr_regnums_i386[0])) -
               "g_gpr_regnums_i386 has wrong number of register infos");
 
 // x86 32-bit floating point registers.
-const uint32_t g_fpu_regnums_i386[] = {
+static const uint32_t g_fpu_regnums_i386[] = {
     lldb_fctrl_i386,    lldb_fstat_i386,     lldb_ftag_i386,  lldb_fop_i386,
     lldb_fiseg_i386,    lldb_fioff_i386,     lldb_foseg_i386, lldb_fooff_i386,
     lldb_mxcsr_i386,    lldb_mxcsrmask_i386, lldb_st0_i386,   lldb_st1_i386,
@@ -236,7 +233,6 @@ static const RegisterSet g_reg_sets_x86_64[k_num_register_sets] = {
 };
 
 #define REG_CONTEXT_SIZE (GetRegisterInfoInterface().GetGPRSize())
-} // namespace
 
 NativeRegisterContextFreeBSD *
 NativeRegisterContextFreeBSD::CreateHostNativeRegisterContextFreeBSD(
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
index 6462441249c04..c6aa320c0c142 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp
@@ -41,11 +41,8 @@ static inline int get_cpuid_count(unsigned int __leaf,
 using namespace lldb_private;
 using namespace lldb_private::process_linux;
 
-// Private namespace.
-
-namespace {
 // x86 32-bit general purpose registers.
-const uint32_t g_gpr_regnums_i386[] = {
+static const uint32_t g_gpr_regnums_i386[] = {
     lldb_eax_i386,      lldb_ebx_i386,    lldb_ecx_i386, lldb_edx_i386,
     lldb_edi_i386,      lldb_esi_i386,    lldb_ebp_i386, lldb_esp_i386,
     lldb_eip_i386,      lldb_eflags_i386, lldb_cs_i386,  lldb_fs_i386,
@@ -62,7 +59,7 @@ static_assert((sizeof(g_gpr_regnums_i386) / sizeof(g_gpr_regnums_i386[0])) -
               "g_gpr_regnums_i386 has wrong number of register infos");
 
 // x86 32-bit floating point registers.
-const uint32_t g_fpu_regnums_i386[] = {
+static const uint32_t g_fpu_regnums_i386[] = {
     lldb_fctrl_i386,    lldb_fstat_i386,     lldb_ftag_i386,  lldb_fop_i386,
     lldb_fiseg_i386,    lldb_fioff_i386,     lldb_foseg_i386, lldb_fooff_i386,
     lldb_mxcsr_i386,    lldb_mxcsrmask_i386, lldb_st0_i386,   lldb_st1_i386,
@@ -80,7 +77,7 @@ static_assert((sizeof(g_fpu_regnums_i386) / sizeof(g_fpu_regnums_i386[0])) -
               "g_fpu_regnums_i386 has wrong number of register infos");
 
 // x86 32-bit AVX registers.
-const uint32_t g_avx_regnums_i386[] = {
+static const uint32_t g_avx_regnums_i386[] = {
     lldb_ymm0_i386,     lldb_ymm1_i386, lldb_ymm2_i386, lldb_ymm3_i386,
     lldb_ymm4_i386,     lldb_ymm5_i386, lldb_ymm6_i386, lldb_ymm7_i386,
     LLDB_INVALID_REGNUM // register sets need to end with this flag
@@ -196,7 +193,7 @@ static_assert((sizeof(g_mpx_regnums_x86_64) / sizeof(g_mpx_regnums_x86_64[0])) -
               "g_mpx_regnums_x86_64 has wrong number of register infos");
 
 // Number of register sets provided by this context.
-enum { k_num_extended_register_sets = 2, k_num_register_sets = 4 };
+constexpr unsigned k_num_extended_register_sets = 2, k_num_register_sets = 4;
 
 // Register sets for x86 32-bit.
 static const RegisterSet g_reg_sets_i386[k_num_register_sets] = {
@@ -219,7 +216,6 @@ static const RegisterSet g_reg_sets_x86_64[k_num_register_sets] = {
      g_avx_regnums_x86_64},
     { "Memory Protection Extensions", "mpx", k_num_mpx_registers_x86_64,
      g_mpx_regnums_x86_64}};
-}
 
 #define REG_CONTEXT_SIZE (GetRegisterInfoInterface().GetGPRSize() + sizeof(FPR))
 
diff --git a/lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp b/lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
index 6672363164b16..239b409ac695c 100644
--- a/lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
+++ b/lldb/source/Plugins/ScriptInterpreter/Lua/ScriptInterpreterLua.cpp
@@ -110,8 +110,7 @@ bool ScriptInterpreterLua::ExecuteOneLine(llvm::StringRef command,
 }
 
 void ScriptInterpreterLua::ExecuteInterpreterLoop() {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
 
   // At the moment, the only time the debugger does not have an input file
   // handle is when this is called directly from lua, in which case it is
diff --git a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
index 5f950d42cac6f..6b53bd3a2edc4 100644
--- a/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
+++ b/lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
@@ -1001,8 +1001,7 @@ bool ScriptInterpreterPythonImpl::ExecuteOneLine(
 }
 
 void ScriptInterpreterPythonImpl::ExecuteInterpreterLoop() {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
 
   Debugger &debugger = m_debugger;
 
@@ -2220,8 +2219,7 @@ bool ScriptInterpreterPythonImpl::GetScriptedSummary(
     StructuredData::ObjectSP &callee_wrapper_sp,
     const TypeSummaryOptions &options, std::string &retval) {
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
 
   if (!valobj.get()) {
     retval.assign("<no object>");
@@ -3240,8 +3238,7 @@ void ScriptInterpreterPythonImpl::InitializePrivate() {
 
   g_initialized = true;
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
 
   // RAII-based initialization which correctly handles multiple-initialization,
   // version- specific differences among Python 2 and Python 3, and saving and
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugAranges.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugAranges.cpp
index 7062c9bfae235..9f190fbcee87e 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugAranges.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugAranges.cpp
@@ -78,8 +78,7 @@ void DWARFDebugAranges::AppendRange(dw_offset_t offset, dw_addr_t low_pc,
 }
 
 void DWARFDebugAranges::Sort(bool minimize) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%s this = %p", LLVM_PRETTY_FUNCTION,
+  LLDB_SCOPED_TIMERF("%s this = %p", LLVM_PRETTY_FUNCTION,
                      static_cast<void *>(this));
 
   m_aranges.Sort();
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
index 12e8b25130a9c..d0cfb5fca82fd 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
@@ -49,9 +49,7 @@ void DWARFUnit::ExtractUnitDIEIfNeeded() {
   if (m_first_die)
     return; // Already parsed
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%8.8x: DWARFUnit::ExtractUnitDIEIfNeeded()",
-                     GetOffset());
+  LLDB_SCOPED_TIMERF("%8.8x: DWARFUnit::ExtractUnitDIEIfNeeded()", GetOffset());
 
   // Set the offset to that of the first DIE and calculate the start of the
   // next compilation unit header.
@@ -145,9 +143,7 @@ DWARFUnit::ScopedExtractDIEs &DWARFUnit::ScopedExtractDIEs::operator=(
 void DWARFUnit::ExtractDIEsRWLocked() {
   llvm::sys::ScopedWriter first_die_lock(m_first_die_mutex);
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%8.8x: DWARFUnit::ExtractDIEsIfNeeded()",
-                     GetOffset());
+  LLDB_SCOPED_TIMERF("%8.8x: DWARFUnit::ExtractDIEsIfNeeded()", GetOffset());
 
   // Set the offset to that of the first DIE and calculate the start of the
   // next compilation unit header.
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
index 0642e8a10f888..dda599baffebf 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
@@ -28,8 +28,7 @@ void ManualDWARFIndex::Index() {
   SymbolFileDWARF &main_dwarf = *m_dwarf;
   m_dwarf = nullptr;
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%p", static_cast<void *>(&main_dwarf));
+  LLDB_SCOPED_TIMERF("%p", static_cast<void *>(&main_dwarf));
 
   DWARFDebugInfo &main_info = main_dwarf.DebugInfo();
   SymbolFileDWARFDwo *dwp_dwarf = main_dwarf.GetDwpSymbolFile().get();
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
index b19881ff929fb..afad21af240cd 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
@@ -623,8 +623,7 @@ DWARFDebugAbbrev *SymbolFileDWARF::DebugAbbrev() {
 
 DWARFDebugInfo &SymbolFileDWARF::DebugInfo() {
   llvm::call_once(m_info_once_flag, [&] {
-    static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-    Timer scoped_timer(func_cat, "%s this = %p", LLVM_PRETTY_FUNCTION,
+    LLDB_SCOPED_TIMERF("%s this = %p", LLVM_PRETTY_FUNCTION,
                        static_cast<void *>(this));
     m_info = std::make_unique<DWARFDebugInfo>(*this, m_context);
   });
@@ -646,8 +645,7 @@ DWARFCompileUnit *SymbolFileDWARF::GetDWARFCompileUnit(CompileUnit *comp_unit) {
 
 DWARFDebugRanges *SymbolFileDWARF::GetDebugRanges() {
   if (!m_ranges) {
-    static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-    Timer scoped_timer(func_cat, "%s this = %p", LLVM_PRETTY_FUNCTION,
+    LLDB_SCOPED_TIMERF("%s this = %p", LLVM_PRETTY_FUNCTION,
                        static_cast<void *>(this));
 
     if (m_context.getOrLoadRangesData().GetByteSize() > 0)
@@ -829,8 +827,7 @@ XcodeSDK SymbolFileDWARF::ParseXcodeSDK(CompileUnit &comp_unit) {
 }
 
 size_t SymbolFileDWARF::ParseFunctions(CompileUnit &comp_unit) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "SymbolFileDWARF::ParseFunctions");
+  LLDB_SCOPED_TIMER();
   std::lock_guard<std::recursive_mutex> guard(GetModuleMutex());
   DWARFUnit *dwarf_cu = GetDWARFCompileUnit(&comp_unit);
   if (!dwarf_cu)
@@ -1839,9 +1836,7 @@ uint32_t SymbolFileDWARF::ResolveSymbolContext(const Address &so_addr,
                                                SymbolContextItem resolve_scope,
                                                SymbolContext &sc) {
   std::lock_guard<std::recursive_mutex> guard(GetModuleMutex());
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "SymbolFileDWARF::"
+  LLDB_SCOPED_TIMERF("SymbolFileDWARF::"
                      "ResolveSymbolContext (so_addr = { "
                      "section = %p, offset = 0x%" PRIx64
                      " }, resolve_scope = 0x%8.8x)",
@@ -2277,8 +2272,7 @@ void SymbolFileDWARF::FindFunctions(ConstString name,
                                     bool include_inlines,
                                     SymbolContextList &sc_list) {
   std::lock_guard<std::recursive_mutex> guard(GetModuleMutex());
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "SymbolFileDWARF::FindFunctions (name = '%s')",
+  LLDB_SCOPED_TIMERF("SymbolFileDWARF::FindFunctions (name = '%s')",
                      name.AsCString());
 
   // eFunctionNameTypeAuto should be pre-resolved by a call to
@@ -2332,8 +2326,7 @@ void SymbolFileDWARF::FindFunctions(const RegularExpression &regex,
                                     bool include_inlines,
                                     SymbolContextList &sc_list) {
   std::lock_guard<std::recursive_mutex> guard(GetModuleMutex());
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "SymbolFileDWARF::FindFunctions (regex = '%s')",
+  LLDB_SCOPED_TIMERF("SymbolFileDWARF::FindFunctions (regex = '%s')",
                      regex.GetText().str().c_str());
 
   Log *log(LogChannelDWARF::GetLogIfAll(DWARF_LOG_LOOKUPS));
diff --git a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
index 6515d78b8f236..fa24f975b0730 100644
--- a/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
+++ b/lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
@@ -1013,9 +1013,7 @@ void SymbolFileDWARFDebugMap::FindFunctions(
     FunctionNameType name_type_mask, bool include_inlines,
     SymbolContextList &sc_list) {
   std::lock_guard<std::recursive_mutex> guard(GetModuleMutex());
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "SymbolFileDWARFDebugMap::FindFunctions (name = %s)",
+  LLDB_SCOPED_TIMERF("SymbolFileDWARFDebugMap::FindFunctions (name = %s)",
                      name.GetCString());
 
   ForEachSymbolFile([&](SymbolFileDWARF *oso_dwarf) -> bool {
@@ -1034,9 +1032,7 @@ void SymbolFileDWARFDebugMap::FindFunctions(const RegularExpression &regex,
                                             bool include_inlines,
                                             SymbolContextList &sc_list) {
   std::lock_guard<std::recursive_mutex> guard(GetModuleMutex());
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "SymbolFileDWARFDebugMap::FindFunctions (regex = '%s')",
+  LLDB_SCOPED_TIMERF("SymbolFileDWARFDebugMap::FindFunctions (regex = '%s')",
                      regex.GetText().str().c_str());
 
   ForEachSymbolFile([&](SymbolFileDWARF *oso_dwarf) -> bool {
@@ -1055,9 +1051,7 @@ void SymbolFileDWARFDebugMap::GetTypes(SymbolContextScope *sc_scope,
                                        lldb::TypeClass type_mask,
                                        TypeList &type_list) {
   std::lock_guard<std::recursive_mutex> guard(GetModuleMutex());
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat,
-                     "SymbolFileDWARFDebugMap::GetTypes (type_mask = 0x%8.8x)",
+  LLDB_SCOPED_TIMERF("SymbolFileDWARFDebugMap::GetTypes (type_mask = 0x%8.8x)",
                      type_mask);
 
   SymbolFileDWARF *oso_dwarf = nullptr;
diff --git a/lldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp b/lldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp
index 89b07d22e350d..4df5140bd7e1a 100644
--- a/lldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp
+++ b/lldb/source/Plugins/SymbolVendor/ELF/SymbolVendorELF.cpp
@@ -81,8 +81,7 @@ SymbolVendorELF::CreateInstance(const lldb::ModuleSP &module_sp,
   if (!fspec)
     fspec = obj_file->GetDebugLink().getValueOr(FileSpec());
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "SymbolVendorELF::CreateInstance (module = %s)",
+  LLDB_SCOPED_TIMERF("SymbolVendorELF::CreateInstance (module = %s)",
                      module_sp->GetFileSpec().GetPath().c_str());
 
   ModuleSpec module_spec;
diff --git a/lldb/source/Plugins/SymbolVendor/wasm/SymbolVendorWasm.cpp b/lldb/source/Plugins/SymbolVendor/wasm/SymbolVendorWasm.cpp
index 1c09dabc5622f..67a1ef5e4e515 100644
--- a/lldb/source/Plugins/SymbolVendor/wasm/SymbolVendorWasm.cpp
+++ b/lldb/source/Plugins/SymbolVendor/wasm/SymbolVendorWasm.cpp
@@ -72,8 +72,7 @@ SymbolVendorWasm::CreateInstance(const lldb::ModuleSP &module_sp,
           lldb::eSectionTypeDWARFDebugInfo, true))
     return nullptr;
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "SymbolVendorWasm::CreateInstance (module = %s)",
+  LLDB_SCOPED_TIMERF("SymbolVendorWasm::CreateInstance (module = %s)",
                      module_sp->GetFileSpec().GetPath().c_str());
 
   ModuleSpec module_spec;
diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
index 894faa8474507..c15b15e736fbe 100644
--- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
+++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
@@ -3147,6 +3147,20 @@ bool TypeSystemClang::IsEnumerationType(lldb::opaque_compiler_type_t type,
   return false;
 }
 
+bool TypeSystemClang::IsScopedEnumerationType(
+    lldb::opaque_compiler_type_t type) {
+  if (type) {
+    const clang::EnumType *enum_type = llvm::dyn_cast<clang::EnumType>(
+        GetCanonicalQualType(type)->getCanonicalTypeInternal());
+
+    if (enum_type) {
+      return enum_type->isScopedEnumeralType();
+    }
+  }
+
+  return false;
+}
+
 bool TypeSystemClang::IsPointerType(lldb::opaque_compiler_type_t type,
                                     CompilerType *pointee_type) {
   if (type) {
@@ -4181,6 +4195,13 @@ TypeSystemClang::GetFullyUnqualifiedType(lldb::opaque_compiler_type_t type) {
   return CompilerType();
 }
 
+CompilerType
+TypeSystemClang::GetEnumerationIntegerType(lldb::opaque_compiler_type_t type) {
+  if (type)
+    return GetEnumerationIntegerType(GetType(GetCanonicalQualType(type)));
+  return CompilerType();
+}
+
 int TypeSystemClang::GetFunctionArgumentCount(
     lldb::opaque_compiler_type_t type) {
   if (type) {
@@ -6981,9 +7002,6 @@ TypeSystemClang::GetTemplateArgumentKind(lldb::opaque_compiler_type_t type,
 
   case clang::TemplateArgument::Pack:
     return eTemplateArgumentKindPack;
-
-  case clang::TemplateArgument::UncommonValue:
-    return eTemplateArgumentKindUncommonValue;
   }
   llvm_unreachable("Unhandled clang::TemplateArgument::ArgKind");
 }
diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
index 484c251aa00e1..d24c5958204ff 100644
--- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
+++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.h
@@ -600,6 +600,8 @@ class TypeSystemClang : public TypeSystem {
   bool IsEnumerationType(lldb::opaque_compiler_type_t type,
                          bool &is_signed) override;
 
+  bool IsScopedEnumerationType(lldb::opaque_compiler_type_t type) override;
+
   static bool IsObjCClassType(const CompilerType &type);
 
   static bool IsObjCClassTypeAndHasIVars(const CompilerType &type,
@@ -676,6 +678,9 @@ class TypeSystemClang : public TypeSystem {
   CompilerType
   GetFullyUnqualifiedType(lldb::opaque_compiler_type_t type) override;
 
+  CompilerType
+  GetEnumerationIntegerType(lldb::opaque_compiler_type_t type) override;
+
   // Returns -1 if this isn't a function of if the function doesn't have a
   // prototype Returns a value >= 0 if there is a prototype.
   int GetFunctionArgumentCount(lldb::opaque_compiler_type_t type) override;
diff --git a/lldb/source/Symbol/CompileUnit.cpp b/lldb/source/Symbol/CompileUnit.cpp
index 0c67bf5b702a4..822f0df4da37a 100644
--- a/lldb/source/Symbol/CompileUnit.cpp
+++ b/lldb/source/Symbol/CompileUnit.cpp
@@ -75,8 +75,7 @@ void CompileUnit::ForeachFunction(
 
 lldb::FunctionSP CompileUnit::FindFunction(
     llvm::function_ref<bool(const FunctionSP &)> matching_lambda) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "CompileUnit::FindFunction");
+  LLDB_SCOPED_TIMER();
 
   lldb::ModuleSP module = CalculateSymbolContextModule();
 
diff --git a/lldb/source/Symbol/CompilerType.cpp b/lldb/source/Symbol/CompilerType.cpp
index c2f68283f6036..4f0c3b366af5b 100644
--- a/lldb/source/Symbol/CompilerType.cpp
+++ b/lldb/source/Symbol/CompilerType.cpp
@@ -40,6 +40,12 @@ bool CompilerType::IsAnonymousType() const {
   return false;
 }
 
+bool CompilerType::IsScopedEnumerationType() const {
+  if (IsValid())
+    return m_type_system->IsScopedEnumerationType(m_type);
+  return false;
+}
+
 bool CompilerType::IsArrayType(CompilerType *element_type_ptr, uint64_t *size,
                                bool *is_incomplete) const {
   if (IsValid())
@@ -344,6 +350,12 @@ CompilerType CompilerType::GetFullyUnqualifiedType() const {
   return CompilerType();
 }
 
+CompilerType CompilerType::GetEnumerationIntegerType() const {
+  if (IsValid())
+    return m_type_system->GetEnumerationIntegerType(m_type);
+  return CompilerType();
+}
+
 int CompilerType::GetFunctionArgumentCount() const {
   if (IsValid()) {
     return m_type_system->GetFunctionArgumentCount(m_type);
diff --git a/lldb/source/Symbol/DWARFCallFrameInfo.cpp b/lldb/source/Symbol/DWARFCallFrameInfo.cpp
index 3111c33c71088..f0dce8f4793a1 100644
--- a/lldb/source/Symbol/DWARFCallFrameInfo.cpp
+++ b/lldb/source/Symbol/DWARFCallFrameInfo.cpp
@@ -419,8 +419,7 @@ void DWARFCallFrameInfo::GetFDEIndex() {
   if (m_fde_index_initialized) // if two threads hit the locker
     return;
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%s - %s", LLVM_PRETTY_FUNCTION,
+  LLDB_SCOPED_TIMERF("%s - %s", LLVM_PRETTY_FUNCTION,
                      m_objfile.GetFileSpec().GetFilename().AsCString(""));
 
   bool clear_address_zeroth_bit = false;
diff --git a/lldb/source/Symbol/LocateSymbolFile.cpp b/lldb/source/Symbol/LocateSymbolFile.cpp
index af4bbb6e53608..ba79bf661cd37 100644
--- a/lldb/source/Symbol/LocateSymbolFile.cpp
+++ b/lldb/source/Symbol/LocateSymbolFile.cpp
@@ -209,9 +209,7 @@ static FileSpec LocateExecutableSymbolFileDsym(const ModuleSpec &module_spec) {
   const ArchSpec *arch = module_spec.GetArchitecturePtr();
   const UUID *uuid = module_spec.GetUUIDPtr();
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(
-      func_cat,
+  LLDB_SCOPED_TIMERF(
       "LocateExecutableSymbolFileDsym (file = %s, arch = %s, uuid = %p)",
       exec_fspec ? exec_fspec->GetFilename().AsCString("<NULL>") : "<NULL>",
       arch ? arch->GetArchitectureName() : "<NULL>", (const void *)uuid);
@@ -235,9 +233,8 @@ ModuleSpec Symbols::LocateExecutableObjectFile(const ModuleSpec &module_spec) {
   const FileSpec &exec_fspec = module_spec.GetFileSpec();
   const ArchSpec *arch = module_spec.GetArchitecturePtr();
   const UUID *uuid = module_spec.GetUUIDPtr();
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(
-      func_cat, "LocateExecutableObjectFile (file = %s, arch = %s, uuid = %p)",
+  LLDB_SCOPED_TIMERF(
+      "LocateExecutableObjectFile (file = %s, arch = %s, uuid = %p)",
       exec_fspec ? exec_fspec.GetFilename().AsCString("<NULL>") : "<NULL>",
       arch ? arch->GetArchitectureName() : "<NULL>", (const void *)uuid);
 
diff --git a/lldb/source/Symbol/ObjectFile.cpp b/lldb/source/Symbol/ObjectFile.cpp
index 79683284f36a7..f5dcbc5467f72 100644
--- a/lldb/source/Symbol/ObjectFile.cpp
+++ b/lldb/source/Symbol/ObjectFile.cpp
@@ -28,143 +28,121 @@ using namespace lldb_private;
 
 char ObjectFile::ID;
 
+static ObjectFileSP
+CreateObjectFromContainer(const lldb::ModuleSP &module_sp, const FileSpec *file,
+                          lldb::offset_t file_offset, lldb::offset_t file_size,
+                          DataBufferSP &data_sp, lldb::offset_t &data_offset) {
+  ObjectContainerCreateInstance callback;
+  for (uint32_t idx = 0;
+       (callback = PluginManager::GetObjectContainerCreateCallbackAtIndex(
+            idx)) != nullptr;
+       ++idx) {
+    std::unique_ptr<ObjectContainer> object_container_up(callback(
+        module_sp, data_sp, data_offset, file, file_offset, file_size));
+    if (object_container_up)
+      return object_container_up->GetObjectFile(file);
+  }
+  return {};
+}
+
 ObjectFileSP
 ObjectFile::FindPlugin(const lldb::ModuleSP &module_sp, const FileSpec *file,
                        lldb::offset_t file_offset, lldb::offset_t file_size,
                        DataBufferSP &data_sp, lldb::offset_t &data_offset) {
-  ObjectFileSP object_file_sp;
-
-  if (module_sp) {
-    static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-    Timer scoped_timer(
-        func_cat,
-        "ObjectFile::FindPlugin (module = %s, file = %p, file_offset = "
-        "0x%8.8" PRIx64 ", file_size = 0x%8.8" PRIx64 ")",
-        module_sp->GetFileSpec().GetPath().c_str(),
-        static_cast<const void *>(file), static_cast<uint64_t>(file_offset),
-        static_cast<uint64_t>(file_size));
-    if (file) {
-      FileSpec archive_file;
-      ObjectContainerCreateInstance create_object_container_callback;
-
-      if (!data_sp) {
-        const bool file_exists = FileSystem::Instance().Exists(*file);
-        // We have an object name which most likely means we have a .o file in
-        // a static archive (.a file). Try and see if we have a cached archive
-        // first without reading any data first
-        if (file_exists && module_sp->GetObjectName()) {
-          for (uint32_t idx = 0;
-               (create_object_container_callback =
-                    PluginManager::GetObjectContainerCreateCallbackAtIndex(
-                        idx)) != nullptr;
-               ++idx) {
-            std::unique_ptr<ObjectContainer> object_container_up(
-                create_object_container_callback(module_sp, data_sp,
-                                                 data_offset, file, file_offset,
-                                                 file_size));
-
-            if (object_container_up)
-              object_file_sp = object_container_up->GetObjectFile(file);
-
-            if (object_file_sp.get())
-              return object_file_sp;
-          }
-        }
-        // Ok, we didn't find any containers that have a named object, now lets
-        // read the first 512 bytes from the file so the object file and object
-        // container plug-ins can use these bytes to see if they can parse this
-        // file.
-        if (file_size > 0) {
-          data_sp = FileSystem::Instance().CreateDataBuffer(file->GetPath(),
-                                                            512, file_offset);
-          data_offset = 0;
-        }
-      }
+  LLDB_SCOPED_TIMERF(
+      "ObjectFile::FindPlugin (module = %s, file = %p, file_offset = "
+      "0x%8.8" PRIx64 ", file_size = 0x%8.8" PRIx64 ")",
+      module_sp->GetFileSpec().GetPath().c_str(),
+      static_cast<const void *>(file), static_cast<uint64_t>(file_offset),
+      static_cast<uint64_t>(file_size));
+
+  if (!module_sp)
+    return {};
+
+  if (!file)
+    return {};
+
+  if (!data_sp) {
+    const bool file_exists = FileSystem::Instance().Exists(*file);
+    // We have an object name which most likely means we have a .o file in
+    // a static archive (.a file). Try and see if we have a cached archive
+    // first without reading any data first
+    if (file_exists && module_sp->GetObjectName()) {
+      ObjectFileSP object_file_sp = CreateObjectFromContainer(
+          module_sp, file, file_offset, file_size, data_sp, data_offset);
+      if (object_file_sp)
+        return object_file_sp;
+    }
+    // Ok, we didn't find any containers that have a named object, now lets
+    // read the first 512 bytes from the file so the object file and object
+    // container plug-ins can use these bytes to see if they can parse this
+    // file.
+    if (file_size > 0) {
+      data_sp = FileSystem::Instance().CreateDataBuffer(file->GetPath(), 512,
+                                                        file_offset);
+      data_offset = 0;
+    }
+  }
 
-      if (!data_sp || data_sp->GetByteSize() == 0) {
-        // Check for archive file with format "/path/to/archive.a(object.o)"
-        llvm::SmallString<256> path_with_object;
-        module_sp->GetFileSpec().GetPath(path_with_object);
-
-        ConstString archive_object;
-        const bool must_exist = true;
-        if (ObjectFile::SplitArchivePathWithObject(
-                path_with_object, archive_file, archive_object, must_exist)) {
-          file_size = FileSystem::Instance().GetByteSize(archive_file);
-          if (file_size > 0) {
-            file = &archive_file;
-            module_sp->SetFileSpecAndObjectName(archive_file, archive_object);
-            // Check if this is a object container by iterating through all
-            // object container plugin instances and then trying to get an
-            // object file from the container plugins since we had a name.
-            // Also, don't read
-            // ANY data in case there is data cached in the container plug-ins
-            // (like BSD archives caching the contained objects within an
-            // file).
-            for (uint32_t idx = 0;
-                 (create_object_container_callback =
-                      PluginManager::GetObjectContainerCreateCallbackAtIndex(
-                          idx)) != nullptr;
-                 ++idx) {
-              std::unique_ptr<ObjectContainer> object_container_up(
-                  create_object_container_callback(module_sp, data_sp,
-                                                   data_offset, file,
-                                                   file_offset, file_size));
-
-              if (object_container_up)
-                object_file_sp = object_container_up->GetObjectFile(file);
-
-              if (object_file_sp.get())
-                return object_file_sp;
-            }
-            // We failed to find any cached object files in the container plug-
-            // ins, so lets read the first 512 bytes and try again below...
-            data_sp = FileSystem::Instance().CreateDataBuffer(
-                archive_file.GetPath(), 512, file_offset);
-          }
-        }
+  if (!data_sp || data_sp->GetByteSize() == 0) {
+    // Check for archive file with format "/path/to/archive.a(object.o)"
+    llvm::SmallString<256> path_with_object;
+    module_sp->GetFileSpec().GetPath(path_with_object);
+
+    FileSpec archive_file;
+    ConstString archive_object;
+    const bool must_exist = true;
+    if (ObjectFile::SplitArchivePathWithObject(path_with_object, archive_file,
+                                               archive_object, must_exist)) {
+      file_size = FileSystem::Instance().GetByteSize(archive_file);
+      if (file_size > 0) {
+        file = &archive_file;
+        module_sp->SetFileSpecAndObjectName(archive_file, archive_object);
+        // Check if this is a object container by iterating through all
+        // object container plugin instances and then trying to get an
+        // object file from the container plugins since we had a name.
+        // Also, don't read
+        // ANY data in case there is data cached in the container plug-ins
+        // (like BSD archives caching the contained objects within an
+        // file).
+        ObjectFileSP object_file_sp = CreateObjectFromContainer(
+            module_sp, file, file_offset, file_size, data_sp, data_offset);
+        if (object_file_sp)
+          return object_file_sp;
+        // We failed to find any cached object files in the container plug-
+        // ins, so lets read the first 512 bytes and try again below...
+        data_sp = FileSystem::Instance().CreateDataBuffer(
+            archive_file.GetPath(), 512, file_offset);
       }
+    }
+  }
 
-      if (data_sp && data_sp->GetByteSize() > 0) {
-        // Check if this is a normal object file by iterating through all
-        // object file plugin instances.
-        ObjectFileCreateInstance create_object_file_callback;
-        for (uint32_t idx = 0;
-             (create_object_file_callback =
-                  PluginManager::GetObjectFileCreateCallbackAtIndex(idx)) !=
-             nullptr;
-             ++idx) {
-          object_file_sp.reset(create_object_file_callback(
-              module_sp, data_sp, data_offset, file, file_offset, file_size));
-          if (object_file_sp.get())
-            return object_file_sp;
-        }
-
-        // Check if this is a object container by iterating through all object
-        // container plugin instances and then trying to get an object file
-        // from the container.
-        for (uint32_t idx = 0;
-             (create_object_container_callback =
-                  PluginManager::GetObjectContainerCreateCallbackAtIndex(
-                      idx)) != nullptr;
-             ++idx) {
-          std::unique_ptr<ObjectContainer> object_container_up(
-              create_object_container_callback(module_sp, data_sp, data_offset,
-                                               file, file_offset, file_size));
-
-          if (object_container_up)
-            object_file_sp = object_container_up->GetObjectFile(file);
-
-          if (object_file_sp.get())
-            return object_file_sp;
-        }
-      }
+  if (data_sp && data_sp->GetByteSize() > 0) {
+    // Check if this is a normal object file by iterating through all
+    // object file plugin instances.
+    ObjectFileCreateInstance callback;
+    for (uint32_t idx = 0;
+         (callback = PluginManager::GetObjectFileCreateCallbackAtIndex(idx)) !=
+         nullptr;
+         ++idx) {
+      ObjectFileSP object_file_sp(callback(module_sp, data_sp, data_offset,
+                                           file, file_offset, file_size));
+      if (object_file_sp.get())
+        return object_file_sp;
     }
+
+    // Check if this is a object container by iterating through all object
+    // container plugin instances and then trying to get an object file
+    // from the container.
+    ObjectFileSP object_file_sp = CreateObjectFromContainer(
+        module_sp, file, file_offset, file_size, data_sp, data_offset);
+    if (object_file_sp)
+      return object_file_sp;
   }
+
   // We didn't find it, so clear our shared pointer in case it contains
   // anything and return an empty shared pointer
-  object_file_sp.reset();
-  return object_file_sp;
+  return {};
 }
 
 ObjectFileSP ObjectFile::FindPlugin(const lldb::ModuleSP &module_sp,
@@ -174,9 +152,7 @@ ObjectFileSP ObjectFile::FindPlugin(const lldb::ModuleSP &module_sp,
   ObjectFileSP object_file_sp;
 
   if (module_sp) {
-    static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-    Timer scoped_timer(func_cat,
-                       "ObjectFile::FindPlugin (module = "
+    LLDB_SCOPED_TIMERF("ObjectFile::FindPlugin (module = "
                        "%s, process = %p, header_addr = "
                        "0x%" PRIx64 ")",
                        module_sp->GetFileSpec().GetPath().c_str(),
diff --git a/lldb/source/Symbol/Symtab.cpp b/lldb/source/Symbol/Symtab.cpp
index 3f697e6076b37..7f84243347089 100644
--- a/lldb/source/Symbol/Symtab.cpp
+++ b/lldb/source/Symbol/Symtab.cpp
@@ -251,8 +251,7 @@ void Symtab::InitNameIndexes() {
   // Protected function, no need to lock mutex...
   if (!m_name_indexes_computed) {
     m_name_indexes_computed = true;
-    static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-    Timer scoped_timer(func_cat, "%s", LLVM_PRETTY_FUNCTION);
+    LLDB_SCOPED_TIMER();
     // Create the name index vector to be able to quickly search by name
     const size_t num_symbols = m_symbols.size();
     m_name_to_index.Reserve(num_symbols);
@@ -411,9 +410,8 @@ void Symtab::PreloadSymbols() {
 void Symtab::AppendSymbolNamesToMap(const IndexCollection &indexes,
                                     bool add_demangled, bool add_mangled,
                                     NameToIndexMap &name_to_index_map) const {
+  LLDB_SCOPED_TIMER();
   if (add_demangled || add_mangled) {
-    static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-    Timer scoped_timer(func_cat, "%s", LLVM_PRETTY_FUNCTION);
     std::lock_guard<std::recursive_mutex> guard(m_mutex);
 
     // Create the name index vector to be able to quickly search by name
@@ -566,9 +564,7 @@ struct SymbolIndexComparator {
 void Symtab::SortSymbolIndexesByValue(std::vector<uint32_t> &indexes,
                                       bool remove_duplicates) const {
   std::lock_guard<std::recursive_mutex> guard(m_mutex);
-
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
   // No need to sort if we have zero or one items...
   if (indexes.size() <= 1)
     return;
@@ -594,8 +590,7 @@ uint32_t Symtab::AppendSymbolIndexesWithName(ConstString symbol_name,
                                              std::vector<uint32_t> &indexes) {
   std::lock_guard<std::recursive_mutex> guard(m_mutex);
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%s", LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
   if (symbol_name) {
     if (!m_name_indexes_computed)
       InitNameIndexes();
@@ -611,8 +606,7 @@ uint32_t Symtab::AppendSymbolIndexesWithName(ConstString symbol_name,
                                              std::vector<uint32_t> &indexes) {
   std::lock_guard<std::recursive_mutex> guard(m_mutex);
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%s", LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
   if (symbol_name) {
     const size_t old_size = indexes.size();
     if (!m_name_indexes_computed)
@@ -741,8 +735,7 @@ Symtab::FindAllSymbolsWithNameAndType(ConstString name,
                                       std::vector<uint32_t> &symbol_indexes) {
   std::lock_guard<std::recursive_mutex> guard(m_mutex);
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%s", LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
   // Initialize all of the lookup by name indexes before converting NAME to a
   // uniqued string NAME_STR below.
   if (!m_name_indexes_computed)
@@ -760,8 +753,7 @@ void Symtab::FindAllSymbolsWithNameAndType(
     Visibility symbol_visibility, std::vector<uint32_t> &symbol_indexes) {
   std::lock_guard<std::recursive_mutex> guard(m_mutex);
 
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%s", LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
   // Initialize all of the lookup by name indexes before converting NAME to a
   // uniqued string NAME_STR below.
   if (!m_name_indexes_computed)
@@ -790,9 +782,7 @@ Symbol *Symtab::FindFirstSymbolWithNameAndType(ConstString name,
                                                Debug symbol_debug_type,
                                                Visibility symbol_visibility) {
   std::lock_guard<std::recursive_mutex> guard(m_mutex);
-
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, "%s", LLVM_PRETTY_FUNCTION);
+  LLDB_SCOPED_TIMER();
   if (!m_name_indexes_computed)
     InitNameIndexes();
 
diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp
index bee87eb1b6c73..736864e021bbd 100644
--- a/lldb/source/Target/Target.cpp
+++ b/lldb/source/Target/Target.cpp
@@ -1400,9 +1400,7 @@ void Target::SetExecutableModule(ModuleSP &executable_sp,
   ClearModules(false);
 
   if (executable_sp) {
-    static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-    Timer scoped_timer(func_cat,
-                       "Target::SetExecutableModule (executable = '%s')",
+    LLDB_SCOPED_TIMERF("Target::SetExecutableModule (executable = '%s')",
                        executable_sp->GetFileSpec().GetPath().c_str());
 
     const bool notify = true;
diff --git a/lldb/source/Target/TargetList.cpp b/lldb/source/Target/TargetList.cpp
index 5bb6ca2a73e96..1e5856dd0b221 100644
--- a/lldb/source/Target/TargetList.cpp
+++ b/lldb/source/Target/TargetList.cpp
@@ -286,10 +286,9 @@ Status TargetList::CreateTargetInternal(Debugger &debugger,
                                         LoadDependentFiles load_dependent_files,
                                         lldb::PlatformSP &platform_sp,
                                         lldb::TargetSP &target_sp) {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(
-      func_cat, "TargetList::CreateTarget (file = '%s', arch = '%s')",
-      user_exe_path.str().c_str(), specified_arch.GetArchitectureName());
+  LLDB_SCOPED_TIMERF("TargetList::CreateTarget (file = '%s', arch = '%s')",
+                     user_exe_path.str().c_str(),
+                     specified_arch.GetArchitectureName());
   Status error;
   const bool is_dummy_target = false;
 
diff --git a/lldb/test/API/python_api/type/TestTypeList.py b/lldb/test/API/python_api/type/TestTypeList.py
index 901ddc62f4e56..ff560de2f96f1 100644
--- a/lldb/test/API/python_api/type/TestTypeList.py
+++ b/lldb/test/API/python_api/type/TestTypeList.py
@@ -144,3 +144,26 @@ def test(self):
         myint_type = target.FindFirstType('myint')
         self.DebugSBType(myint_type)
         self.assertTrue(myint_arr_element_type == myint_type)
+
+        # Test enum methods.
+        enum_type = target.FindFirstType('EnumType')
+        self.assertTrue(enum_type)
+        self.DebugSBType(enum_type)
+        self.assertFalse(enum_type.IsScopedEnumerationType())
+
+        scoped_enum_type = target.FindFirstType('ScopedEnumType')
+        self.assertTrue(scoped_enum_type)
+        self.DebugSBType(scoped_enum_type)
+        self.assertTrue(scoped_enum_type.IsScopedEnumerationType())
+        int_scoped_enum_type = scoped_enum_type.GetEnumerationIntegerType()
+        self.assertTrue(int_scoped_enum_type)
+        self.DebugSBType(int_scoped_enum_type)
+        self.assertEquals(int_scoped_enum_type.GetName(), 'int')
+
+        enum_uchar = target.FindFirstType('EnumUChar')
+        self.assertTrue(enum_uchar)
+        self.DebugSBType(enum_uchar)
+        int_enum_uchar = enum_uchar.GetEnumerationIntegerType()
+        self.assertTrue(int_enum_uchar)
+        self.DebugSBType(int_enum_uchar)
+        self.assertEquals(int_enum_uchar.GetName(), 'unsigned char')
diff --git a/lldb/test/API/python_api/type/main.cpp b/lldb/test/API/python_api/type/main.cpp
index 13e6bbc127ba6..b1ef625283855 100644
--- a/lldb/test/API/python_api/type/main.cpp
+++ b/lldb/test/API/python_api/type/main.cpp
@@ -29,6 +29,9 @@ class Task {
     {}
 };
 
+enum EnumType {};
+enum class ScopedEnumType {};
+enum class EnumUChar : unsigned char {};
 
 int main (int argc, char const *argv[])
 {
@@ -59,5 +62,9 @@ int main (int argc, char const *argv[])
     typedef int myint;
     myint myint_arr[] = {1, 2, 3};
 
+    EnumType enum_type;
+    ScopedEnumType scoped_enum_type;
+    EnumUChar scoped_enum_type_uchar;
+
     return 0; // Break at this line
 }
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteAttach.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteAttach.py
index 84d44b5e0b849..dd427b66ca894 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteAttach.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteAttach.py
@@ -1,18 +1,17 @@
-
-
 import gdbremote_testcase
 import lldbgdbserverutils
 from lldbsuite.test.decorators import *
 from lldbsuite.test.lldbtest import *
 from lldbsuite.test import lldbutil
 
-
 class TestGdbRemoteAttach(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    def attach_with_vAttach(self):
+    def test_attach_with_vAttach(self):
+        self.build()
+        self.set_inferior_startup_attach_manually()
+
         # Start the inferior, start the debug monitor, nothing is attached yet.
         procs = self.prep_debug_monitor_and_inferior(
             inferior_args=["sleep:60"])
@@ -50,15 +49,3 @@ def attach_with_vAttach(self):
         self.assertIsNotNone(pid_text)
         reported_pid = int(pid_text, base=16)
         self.assertEqual(reported_pid, inferior.pid)
-
-    @debugserver_test
-    def test_attach_with_vAttach_debugserver(self):
-        self.build()
-        self.set_inferior_startup_attach_manually()
-        self.attach_with_vAttach()
-
-    @llgs_test
-    def test_attach_with_vAttach_llgs(self):
-        self.build()
-        self.set_inferior_startup_attach_manually()
-        self.attach_with_vAttach()
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py
index f9c8fadc15b91..9d9c4d89e0b5e 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteAuxvSupport.py
@@ -10,7 +10,6 @@ class TestGdbRemoteAuxvSupport(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     AUXV_SUPPORT_FEATURE_NAME = "qXfer:auxv:read"
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def has_auxv_support(self):
         inferior_args = ["message:main entered", "sleep:5"]
         procs = self.prep_debug_monitor_and_inferior(
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteCompletion.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteCompletion.py
index 5eec3c44f67ad..22af21d132da8 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteCompletion.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteCompletion.py
@@ -34,8 +34,7 @@ def init_lldb_server(self):
     def generate_hex_path(self, target):
         return str(os.path.join(self.getBuildDir(), target)).encode().hex()
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @llgs_test
+    @add_test_categories(["llgs"])
     def test_autocomplete_path(self):
         self.build()
         self.init_lldb_server()
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteExitCode.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteExitCode.py
index 96ebbfb09bdc7..961409d3fec2f 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteExitCode.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteExitCode.py
@@ -12,46 +12,21 @@ class TestGdbRemoteExitCode(GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
 
-    def inferior_exit_0(self):
-        self.prep_debug_monitor_and_inferior()
-        self.test_sequence.add_log_lines(
-            ["read packet: $vCont;c#a8",
-             "send packet: $W00#00"],
-            True)
-
-        self.expect_gdbremote_sequence()
-
-    @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    def test_inferior_exit_0_debugserver(self):
+    def _test_inferior_exit(self, retval):
         self.build()
-        self.inferior_exit_0()
-
-    @llgs_test
-    def test_inferior_exit_0_llgs(self):
-        self.build()
-        self.inferior_exit_0()
-
-    def inferior_exit_42(self):
-        RETVAL = 42
 
         procs = self.prep_debug_monitor_and_inferior(
-            inferior_args=["retval:%d" % RETVAL])
+            inferior_args=["retval:%d" % retval])
 
         self.test_sequence.add_log_lines(
             ["read packet: $vCont;c#a8",
-             "send packet: $W{0:02x}#00".format(RETVAL)],
+             "send packet: $W{0:02x}#00".format(retval)],
             True)
 
         self.expect_gdbremote_sequence()
 
-    @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    def test_inferior_exit_42_debugserver(self):
-        self.build()
-        self.inferior_exit_42()
+    def test_inferior_exit_0(self):
+        self._test_inferior_exit(0)
 
-    @llgs_test
-    def test_inferior_exit_42_llgs(self):
-        self.build()
-        self.inferior_exit_42()
+    def test_inferior_exit_42(self):
+        self._test_inferior_exit(42)
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py
index a07e227b1a44f..fcf115647801c 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteExpeditedRegisters.py
@@ -9,7 +9,6 @@ class TestGdbRemoteExpeditedRegisters(
 
     mydir = TestBase.compute_mydir(__file__)
     # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @skipIfDarwinEmbedded
     def gather_expedited_registers(self):
         # Setup the stub and set the gdb remote command stream.
         procs = self.prep_debug_monitor_and_inferior(inferior_args=["sleep:2"])
@@ -58,45 +57,21 @@ def stop_notification_contains_generic_register(
         self.assertTrue(reg_info["lldb_register_index"] in expedited_registers)
         self.trace("{} reg_info:{}".format(generic_register_name, reg_info))
 
-    def stop_notification_contains_aarch64_vg_register(self):
-        # Generate a stop reply, parse out expedited registers from stop
-        # notification.
-        expedited_registers = self.gather_expedited_registers()
-        self.assertIsNotNone(expedited_registers)
-        self.assertTrue(len(expedited_registers) > 0)
-
-        # Gather target register infos.
-        reg_infos = self.gather_register_infos()
-
-        # Find the vg register.
-        reg_info = self.find_register_with_name_and_dwarf_regnum(
-            reg_infos, 'vg', '46')
-        self.assertIsNotNone(reg_info)
-
-        # Ensure the expedited registers contained it.
-        self.assertTrue(reg_info["lldb_register_index"] in expedited_registers)
-        self.trace("{} reg_info:{}".format('vg', reg_info))
+    def test_stop_notification_contains_any_registers(self):
+        self.build()
+        self.set_inferior_startup_launch()
 
-    def stop_notification_contains_any_registers(self):
         # Generate a stop reply, parse out expedited registers from stop
         # notification.
         expedited_registers = self.gather_expedited_registers()
         # Verify we have at least one expedited register.
         self.assertTrue(len(expedited_registers) > 0)
 
-    @debugserver_test
-    def test_stop_notification_contains_any_registers_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_notification_contains_any_registers()
 
-    @llgs_test
-    def test_stop_notification_contains_any_registers_llgs(self):
+    def test_stop_notification_contains_no_duplicate_registers(self):
         self.build()
         self.set_inferior_startup_launch()
-        self.stop_notification_contains_any_registers()
 
-    def stop_notification_contains_no_duplicate_registers(self):
         # Generate a stop reply, parse out expedited registers from stop
         # notification.
         expedited_registers = self.gather_expedited_registers()
@@ -107,72 +82,44 @@ def stop_notification_contains_no_duplicate_registers(self):
                     "expedited register number {} specified more than once ({} times)".format(
                         reg_num, len(value)))
 
-    @debugserver_test
-    def test_stop_notification_contains_no_duplicate_registers_debugserver(
-            self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_notification_contains_no_duplicate_registers()
-
-    @llgs_test
-    def test_stop_notification_contains_no_duplicate_registers_llgs(self):
+    def test_stop_notification_contains_pc_register(self):
         self.build()
         self.set_inferior_startup_launch()
-        self.stop_notification_contains_no_duplicate_registers()
-
-    def stop_notification_contains_pc_register(self):
         self.stop_notification_contains_generic_register("pc")
 
-    @debugserver_test
-    def test_stop_notification_contains_pc_register_debugserver(self):
+    @skipIf(triple='^powerpc64') # powerpc64 has no FP register
+    def test_stop_notification_contains_fp_register(self):
         self.build()
         self.set_inferior_startup_launch()
-        self.stop_notification_contains_pc_register()
-
-    @llgs_test
-    def test_stop_notification_contains_pc_register_llgs(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_notification_contains_pc_register()
-
-    # powerpc64 has no FP register
-    @skipIf(triple='^powerpc64')
-    def stop_notification_contains_fp_register(self):
         self.stop_notification_contains_generic_register("fp")
 
-    @debugserver_test
-    def test_stop_notification_contains_fp_register_debugserver(self):
+    def test_stop_notification_contains_sp_register(self):
         self.build()
         self.set_inferior_startup_launch()
-        self.stop_notification_contains_fp_register()
-
-    @llgs_test
-    def test_stop_notification_contains_fp_register_llgs(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_notification_contains_fp_register()
-
-    def stop_notification_contains_sp_register(self):
         self.stop_notification_contains_generic_register("sp")
 
-    @debugserver_test
-    def test_stop_notification_contains_sp_register_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_notification_contains_sp_register()
-
-    @llgs_test
-    def test_stop_notification_contains_sp_register_llgs(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_notification_contains_sp_register()
-
-    @llgs_test
     @skipIf(archs=no_match(["aarch64"]))
     @skipIf(oslist=no_match(['linux']))
-    def test_stop_notification_contains_vg_register_llgs(self):
+    def test_stop_notification_contains_vg_register(self):
         if not self.isAArch64SVE():
             self.skipTest('SVE registers must be supported.')
         self.build()
         self.set_inferior_startup_launch()
-        self.stop_notification_contains_aarch64_vg_register()
+
+        # Generate a stop reply, parse out expedited registers from stop
+        # notification.
+        expedited_registers = self.gather_expedited_registers()
+        self.assertIsNotNone(expedited_registers)
+        self.assertTrue(len(expedited_registers) > 0)
+
+        # Gather target register infos.
+        reg_infos = self.gather_register_infos()
+
+        # Find the vg register.
+        reg_info = self.find_register_with_name_and_dwarf_regnum(
+            reg_infos, 'vg', '46')
+        self.assertIsNotNone(reg_info)
+
+        # Ensure the expedited registers contained it.
+        self.assertTrue(reg_info["lldb_register_index"] in expedited_registers)
+        self.trace("{} reg_info:{}".format('vg', reg_info))
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteHostInfo.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteHostInfo.py
index abb1a003d1253..63126c15d471f 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteHostInfo.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteHostInfo.py
@@ -99,30 +99,12 @@ def validate_darwin_minimum_host_info_keys(self, host_info_dict):
                           "qHostInfo is missing the following required "
                           "keys: " + str(missing_keys))
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @debugserver_test
-    def test_qHostInfo_returns_at_least_one_key_val_pair_debugserver(self):
+    def test_qHostInfo_returns_at_least_one_key_val_pair(self):
         self.build()
         self.get_qHostInfo_response()
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @llgs_test
-    def test_qHostInfo_returns_at_least_one_key_val_pair_llgs(self):
-        self.build()
-        self.get_qHostInfo_response()
-
-    @skipUnlessDarwin
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @debugserver_test
-    def test_qHostInfo_contains_darwin_required_keys_debugserver(self):
-        self.build()
-        host_info_dict = self.get_qHostInfo_response()
-        self.validate_darwin_minimum_host_info_keys(host_info_dict)
-
     @skipUnlessDarwin
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @llgs_test
-    def test_qHostInfo_contains_darwin_required_keys_llgs(self):
+    def test_qHostInfo_contains_darwin_required_keys(self):
         self.build()
         host_info_dict = self.get_qHostInfo_response()
         self.validate_darwin_minimum_host_info_keys(host_info_dict)
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteKill.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteKill.py
index 175ecfed538b8..98f07f3014e06 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteKill.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteKill.py
@@ -10,9 +10,10 @@
 class TestGdbRemoteKill(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
 
-    def attach_commandline_kill_after_initial_stop(self):
+    def test_attach_commandline_kill_after_initial_stop(self):
+        self.build()
+        self.set_inferior_startup_attach()
         reg_expr = r"^\$[XW][0-9a-fA-F]+([^#]*)#[0-9A-Fa-f]{2}"
         procs = self.prep_debug_monitor_and_inferior()
         self.test_sequence.add_log_lines([
@@ -43,15 +44,3 @@ def attach_commandline_kill_after_initial_stop(self):
         self.assertFalse(
             lldbgdbserverutils.process_is_running(
                 procs["inferior"].pid, False))
-
-    @debugserver_test
-    def test_attach_commandline_kill_after_initial_stop_debugserver(self):
-        self.build()
-        self.set_inferior_startup_attach()
-        self.attach_commandline_kill_after_initial_stop()
-
-    @llgs_test
-    def test_attach_commandline_kill_after_initial_stop_llgs(self):
-        self.build()
-        self.set_inferior_startup_attach()
-        self.attach_commandline_kill_after_initial_stop()
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteModuleInfo.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteModuleInfo.py
index 8365b657f9323..bab097c313650 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteModuleInfo.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteModuleInfo.py
@@ -12,7 +12,10 @@ class TestGdbRemoteModuleInfo(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
 
-    def module_info(self):
+    @add_test_categories(["llgs"])
+    def test_module_info(self):
+        self.build()
+        self.set_inferior_startup_launch()
         procs = self.prep_debug_monitor_and_inferior()
         self.add_process_info_collection_packets()
         context = self.expect_gdbremote_sequence()
@@ -34,9 +37,3 @@ def module_info(self):
         self.assertRegexpMatches(spec, '"file_size":\d+')
         self.assertRegexpMatches(spec, '"triple":"\w*-\w*-.*"')
         self.assertRegexpMatches(spec, '"uuid":"[A-Fa-f0-9]+"')
-
-    @llgs_test
-    def test_module_info(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.module_info()
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteProcessInfo.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteProcessInfo.py
index a4708679e0d80..d1b4e5e3a7868 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteProcessInfo.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteProcessInfo.py
@@ -1,6 +1,3 @@
-
-
-
 import gdbremote_testcase
 import lldbgdbserverutils
 from lldbsuite.test.decorators import *
@@ -12,7 +9,8 @@ class TestGdbRemoteProcessInfo(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
 
-    def qProcessInfo_returns_running_process(self):
+    def test_qProcessInfo_returns_running_process(self):
+        self.build()
         procs = self.prep_debug_monitor_and_inferior()
         self.add_process_info_collection_packets()
 
@@ -33,18 +31,9 @@ def qProcessInfo_returns_running_process(self):
         # If possible, verify that the process is running.
         self.assertTrue(lldbgdbserverutils.process_is_running(pid, True))
 
-    @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    def test_qProcessInfo_returns_running_process_debugserver(self):
+    def test_attach_commandline_qProcessInfo_reports_correct_pid(self):
         self.build()
-        self.qProcessInfo_returns_running_process()
-
-    @llgs_test
-    def test_qProcessInfo_returns_running_process_llgs(self):
-        self.build()
-        self.qProcessInfo_returns_running_process()
-
-    def attach_commandline_qProcessInfo_reports_correct_pid(self):
+        self.set_inferior_startup_attach()
         procs = self.prep_debug_monitor_and_inferior()
         self.assertIsNotNone(procs)
         self.add_process_info_collection_packets()
@@ -63,21 +52,8 @@ def attach_commandline_qProcessInfo_reports_correct_pid(self):
         reported_pid = int(pid_text, base=16)
         self.assertEqual(reported_pid, procs["inferior"].pid)
 
-    @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    def test_attach_commandline_qProcessInfo_reports_correct_pid_debugserver(
-            self):
-        self.build()
-        self.set_inferior_startup_attach()
-        self.attach_commandline_qProcessInfo_reports_correct_pid()
-
-    @llgs_test
-    def test_attach_commandline_qProcessInfo_reports_correct_pid_llgs(self):
+    def test_qProcessInfo_reports_valid_endian(self):
         self.build()
-        self.set_inferior_startup_attach()
-        self.attach_commandline_qProcessInfo_reports_correct_pid()
-
-    def qProcessInfo_reports_valid_endian(self):
         procs = self.prep_debug_monitor_and_inferior()
         self.add_process_info_collection_packets()
 
@@ -92,18 +68,7 @@ def qProcessInfo_reports_valid_endian(self):
         # Ensure the process id looks reasonable.
         endian = process_info.get("endian")
         self.assertIsNotNone(endian)
-        self.assertTrue(endian in ["little", "big", "pdp"])
-
-    @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    def test_qProcessInfo_reports_valid_endian_debugserver(self):
-        self.build()
-        self.qProcessInfo_reports_valid_endian()
-
-    @llgs_test
-    def test_qProcessInfo_reports_valid_endian_llgs(self):
-        self.build()
-        self.qProcessInfo_reports_valid_endian()
+        self.assertIn(endian, ["little", "big", "pdp"])
 
     def qProcessInfo_contains_keys(self, expected_key_set):
         procs = self.prep_debug_monitor_and_inferior()
@@ -152,45 +117,25 @@ def qProcessInfo_does_not_contain_keys(self, absent_key_set):
             set(),
             "the listed keys were present but unexpected in qProcessInfo result")
 
-    @skipUnlessDarwin
-    @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    def test_qProcessInfo_contains_cputype_cpusubtype_debugserver_darwin(self):
-        self.build()
-        self.qProcessInfo_contains_keys(set(['cputype', 'cpusubtype']))
-
-    @skipUnlessDarwin
-    @llgs_test
-    def test_qProcessInfo_contains_cputype_cpusubtype_llgs_darwin(self):
+    @add_test_categories(["debugserver"])
+    def test_qProcessInfo_contains_cputype_cpusubtype(self):
         self.build()
         self.qProcessInfo_contains_keys(set(['cputype', 'cpusubtype']))
 
-    @llgs_test
-    def test_qProcessInfo_contains_triple_ppid_llgs(self):
+    @add_test_categories(["llgs"])
+    def test_qProcessInfo_contains_triple_ppid(self):
         self.build()
         self.qProcessInfo_contains_keys(set(['triple', 'parent-pid']))
 
-    @skipUnlessDarwin
-    @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    def test_qProcessInfo_does_not_contain_triple_debugserver_darwin(self):
-        self.build()
-        # We don't expect to see triple on darwin.  If we do, we'll prefer triple
-        # to cputype/cpusubtype and skip some darwin-based ProcessGDBRemote ArchSpec setup
-        # for the remote Host and Process.
-        self.qProcessInfo_does_not_contain_keys(set(['triple']))
-
-    @skipUnlessDarwin
-    @llgs_test
-    def test_qProcessInfo_does_not_contain_triple_llgs_darwin(self):
+    @add_test_categories(["debugserver"])
+    def test_qProcessInfo_does_not_contain_triple(self):
         self.build()
         # We don't expect to see triple on darwin.  If we do, we'll prefer triple
         # to cputype/cpusubtype and skip some darwin-based ProcessGDBRemote ArchSpec setup
         # for the remote Host and Process.
         self.qProcessInfo_does_not_contain_keys(set(['triple']))
 
-    @skipIfDarwin
-    @llgs_test
-    def test_qProcessInfo_does_not_contain_cputype_cpusubtype_llgs(self):
+    @add_test_categories(["llgs"])
+    def test_qProcessInfo_does_not_contain_cputype_cpusubtype(self):
         self.build()
         self.qProcessInfo_does_not_contain_keys(set(['cputype', 'cpusubtype']))
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteRegisterState.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteRegisterState.py
index 3d07e19d2d382..e3784f46d78f4 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteRegisterState.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteRegisterState.py
@@ -9,7 +9,6 @@ class TestGdbRemoteRegisterState(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def grp_register_save_restore_works(self, with_suffix):
         # Start up the process, use thread suffix, grab main thread id.
         inferior_args = ["message:main entered", "sleep:5"]
@@ -92,29 +91,13 @@ def grp_register_save_restore_works(self, with_suffix):
         self.assertIsNotNone(final_reg_values)
         self.assertEqual(final_reg_values, initial_reg_values)
 
-    @debugserver_test
-    def test_grp_register_save_restore_works_with_suffix_debugserver(self):
+    def test_grp_register_save_restore_works_with_suffix(self):
         USE_THREAD_SUFFIX = True
         self.build()
         self.set_inferior_startup_launch()
         self.grp_register_save_restore_works(USE_THREAD_SUFFIX)
 
-    @llgs_test
-    def test_grp_register_save_restore_works_with_suffix_llgs(self):
-        USE_THREAD_SUFFIX = True
-        self.build()
-        self.set_inferior_startup_launch()
-        self.grp_register_save_restore_works(USE_THREAD_SUFFIX)
-
-    @debugserver_test
-    def test_grp_register_save_restore_works_no_suffix_debugserver(self):
-        USE_THREAD_SUFFIX = False
-        self.build()
-        self.set_inferior_startup_launch()
-        self.grp_register_save_restore_works(USE_THREAD_SUFFIX)
-
-    @llgs_test
-    def test_grp_register_save_restore_works_no_suffix_llgs(self):
+    def test_grp_register_save_restore_works_no_suffix(self):
         USE_THREAD_SUFFIX = False
         self.build()
         self.set_inferior_startup_launch()
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteSingleStep.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteSingleStep.py
index fba8bec8ee6b8..2716390da8288 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteSingleStep.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteSingleStep.py
@@ -1,5 +1,3 @@
-
-
 import gdbremote_testcase
 from lldbsuite.test.decorators import *
 from lldbsuite.test.lldbtest import *
@@ -10,18 +8,9 @@ class TestGdbRemoteSingleStep(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @debugserver_test
-    def test_single_step_only_steps_one_instruction_with_s_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.single_step_only_steps_one_instruction(
-            use_Hc_packet=True, step_instruction="s")
-
     @skipIfWindows # No pty support to test any inferior std -i/e/o
-    @llgs_test
     @skipIf(triple='^mips')
-    def test_single_step_only_steps_one_instruction_with_s_llgs(self):
+    def test_single_step_only_steps_one_instruction_with_s(self):
         self.build()
         self.set_inferior_startup_launch()
         self.single_step_only_steps_one_instruction(
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemoteThreadsInStopReply.py b/lldb/test/API/tools/lldb-server/TestGdbRemoteThreadsInStopReply.py
index c83b4fbdd37dc..e66424f962957 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemoteThreadsInStopReply.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemoteThreadsInStopReply.py
@@ -1,4 +1,3 @@
-
 import json
 import re
 
@@ -166,7 +165,10 @@ def gather_threads_info_pcs(self, pc_register, little_endian):
 
         return thread_pcs
 
-    def QListThreadsInStopReply_supported(self):
+
+    def test_QListThreadsInStopReply_supported(self):
+        self.build()
+        self.set_inferior_startup_launch()
         procs = self.prep_debug_monitor_and_inferior()
         self.test_sequence.add_log_lines(
             self.ENABLE_THREADS_IN_STOP_REPLY_ENTRIES, True)
@@ -174,69 +176,39 @@ def QListThreadsInStopReply_supported(self):
         context = self.expect_gdbremote_sequence()
         self.assertIsNotNone(context)
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @debugserver_test
-    def test_QListThreadsInStopReply_supported_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.QListThreadsInStopReply_supported()
-
-    @llgs_test
-    def test_QListThreadsInStopReply_supported_llgs(self):
+    # In current implementation of llgs on Windows, as a response to '\x03' packet, the debugger
+    # of the native process will trigger a call to DebugBreakProcess that will create a new thread
+    # to handle the exception debug event. So one more stop thread will be notified to the
+    # delegate, e.g. llgs.  So tests below to assert the stop threads number will all fail.
+    @expectedFailureAll(oslist=["windows"])
+    @skipIfNetBSD
+    def test_stop_reply_reports_multiple_threads(self):
         self.build()
         self.set_inferior_startup_launch()
-        self.QListThreadsInStopReply_supported()
-
-    def stop_reply_reports_multiple_threads(self, thread_count):
         # Gather threads from stop notification when QThreadsInStopReply is
         # enabled.
         stop_reply_threads = self.gather_stop_reply_threads(
-            self.ENABLE_THREADS_IN_STOP_REPLY_ENTRIES, thread_count)
-        self.assertEqual(len(stop_reply_threads), thread_count)
+            self.ENABLE_THREADS_IN_STOP_REPLY_ENTRIES, 5)
+        self.assertEqual(len(stop_reply_threads), 5)
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @debugserver_test
-    def test_stop_reply_reports_multiple_threads_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_reply_reports_multiple_threads(5)
-
-    # In current implementation of llgs on Windows, as a response to '\x03' packet, the debugger
-    # of the native process will trigger a call to DebugBreakProcess that will create a new thread
-    # to handle the exception debug event. So one more stop thread will be notified to the
-    # delegate, e.g. llgs.  So tests below to assert the stop threads number will all fail.
     @expectedFailureAll(oslist=["windows"])
     @skipIfNetBSD
-    @llgs_test
-    def test_stop_reply_reports_multiple_threads_llgs(self):
+    def test_no_QListThreadsInStopReply_supplies_no_threads(self):
         self.build()
         self.set_inferior_startup_launch()
-        self.stop_reply_reports_multiple_threads(5)
-
-    def no_QListThreadsInStopReply_supplies_no_threads(self, thread_count):
         # Gather threads from stop notification when QThreadsInStopReply is not
         # enabled.
-        stop_reply_threads = self.gather_stop_reply_threads(None, thread_count)
+        stop_reply_threads = self.gather_stop_reply_threads(None, 5)
         self.assertEqual(len(stop_reply_threads), 0)
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @debugserver_test
-    def test_no_QListThreadsInStopReply_supplies_no_threads_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.no_QListThreadsInStopReply_supplies_no_threads(5)
-
     @expectedFailureAll(oslist=["windows"])
     @skipIfNetBSD
-    @llgs_test
-    def test_no_QListThreadsInStopReply_supplies_no_threads_llgs(self):
+    def test_stop_reply_reports_correct_threads(self):
         self.build()
         self.set_inferior_startup_launch()
-        self.no_QListThreadsInStopReply_supplies_no_threads(5)
-
-    def stop_reply_reports_correct_threads(self, thread_count):
         # Gather threads from stop notification when QThreadsInStopReply is
         # enabled.
+        thread_count = 5
         stop_reply_threads = self.gather_stop_reply_threads(
             self.ENABLE_THREADS_IN_STOP_REPLY_ENTRIES, thread_count)
         self.assertEqual(len(stop_reply_threads), thread_count)
@@ -254,24 +226,14 @@ def stop_reply_reports_correct_threads(self, thread_count):
 
         # Ensure each thread in q{f,s}ThreadInfo appears in stop reply threads
         for tid in threads:
-            self.assertTrue(tid in stop_reply_threads)
-
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @debugserver_test
-    def test_stop_reply_reports_correct_threads_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_reply_reports_correct_threads(5)
+            self.assertIn(tid, stop_reply_threads)
 
     @expectedFailureAll(oslist=["windows"])
     @skipIfNetBSD
-    @llgs_test
-    def test_stop_reply_reports_correct_threads_llgs(self):
+    def test_stop_reply_contains_thread_pcs(self):
         self.build()
         self.set_inferior_startup_launch()
-        self.stop_reply_reports_correct_threads(5)
-
-    def stop_reply_contains_thread_pcs(self, thread_count):
+        thread_count = 5
         results = self.gather_stop_reply_pcs(
                 self.ENABLE_THREADS_IN_STOP_REPLY_ENTRIES, thread_count)
         stop_reply_pcs = results["thread_pcs"]
@@ -284,21 +246,6 @@ def stop_reply_contains_thread_pcs(self, thread_count):
 
         self.assertEqual(len(threads_info_pcs), thread_count)
         for thread_id in stop_reply_pcs:
-            self.assertTrue(thread_id in threads_info_pcs)
-            self.assertTrue(int(stop_reply_pcs[thread_id], 16)
-                    == int(threads_info_pcs[thread_id], 16))
-
-    @expectedFailureAll(oslist=["windows"])
-    @skipIfNetBSD
-    @llgs_test
-    def test_stop_reply_contains_thread_pcs_llgs(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_reply_contains_thread_pcs(5)
-
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @debugserver_test
-    def test_stop_reply_contains_thread_pcs_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.stop_reply_contains_thread_pcs(5)
+            self.assertIn(thread_id, threads_info_pcs)
+            self.assertEqual(int(stop_reply_pcs[thread_id], 16),
+                    int(threads_info_pcs[thread_id], 16))
diff --git a/lldb/test/API/tools/lldb-server/TestGdbRemote_qThreadStopInfo.py b/lldb/test/API/tools/lldb-server/TestGdbRemote_qThreadStopInfo.py
index f8ecf5509b564..c2b944475fadd 100644
--- a/lldb/test/API/tools/lldb-server/TestGdbRemote_qThreadStopInfo.py
+++ b/lldb/test/API/tools/lldb-server/TestGdbRemote_qThreadStopInfo.py
@@ -1,20 +1,14 @@
-
-
-
 import unittest2
 import gdbremote_testcase
 from lldbsuite.test.decorators import *
 from lldbsuite.test.lldbtest import *
 from lldbsuite.test import lldbutil
 
-
 class TestGdbRemote_qThreadStopInfo(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
     THREAD_COUNT = 5
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @skipIfDarwinEmbedded # <rdar://problem/27005337>
     def gather_stop_replies_via_qThreadStopInfo(self, thread_count):
         # Set up the inferior args.
         inferior_args = []
@@ -106,31 +100,25 @@ def gather_stop_replies_via_qThreadStopInfo(self, thread_count):
 
         return (stop_replies, thread_dicts)
 
-    def qThreadStopInfo_works_for_multiple_threads(self, thread_count):
-        (stop_replies, _) = self.gather_stop_replies_via_qThreadStopInfo(thread_count)
+    @skipIfNetBSD
+    def test_qThreadStopInfo_works_for_multiple_threads(self):
+        self.build()
+        self.set_inferior_startup_launch()
+        (stop_replies, _) = self.gather_stop_replies_via_qThreadStopInfo(self.THREAD_COUNT)
         triple = self.dbg.GetSelectedPlatform().GetTriple()
         # Consider one more thread created by calling DebugBreakProcess.
         if re.match(".*-.*-windows", triple):
-            self.assertGreaterEqual(len(stop_replies), thread_count)
+            self.assertGreaterEqual(len(stop_replies), self.THREAD_COUNT)
         else:
-            self.assertEqual(len(stop_replies), thread_count)
+            self.assertEqual(len(stop_replies), self.THREAD_COUNT)
 
-    @debugserver_test
-    def test_qThreadStopInfo_works_for_multiple_threads_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.qThreadStopInfo_works_for_multiple_threads(self.THREAD_COUNT)
-
-    @llgs_test
-    @skipIfNetBSD
-    def test_qThreadStopInfo_works_for_multiple_threads_llgs(self):
+    @expectedFailureAll(oslist=["freebsd"], bugnumber="llvm.org/pr48418")
+    @expectedFailureNetBSD
+    def test_qThreadStopInfo_only_reports_one_thread_stop_reason_during_interrupt(self):
         self.build()
         self.set_inferior_startup_launch()
-        self.qThreadStopInfo_works_for_multiple_threads(self.THREAD_COUNT)
 
-    def qThreadStopInfo_only_reports_one_thread_stop_reason_during_interrupt(
-            self, thread_count):
-        (stop_replies, _) = self.gather_stop_replies_via_qThreadStopInfo(thread_count)
+        (stop_replies, _) = self.gather_stop_replies_via_qThreadStopInfo(self.THREAD_COUNT)
         self.assertIsNotNone(stop_replies)
 
         no_stop_reason_count = sum(
@@ -145,53 +133,9 @@ def qThreadStopInfo_only_reports_one_thread_stop_reason_during_interrupt(
 
         # Consider one more thread created by calling DebugBreakProcess.
         if re.match(".*-.*-windows", triple):
-            self.assertGreaterEqual(no_stop_reason_count, thread_count - 1)
+            self.assertGreaterEqual(no_stop_reason_count, self.THREAD_COUNT - 1)
         else:
-            self.assertEqual(no_stop_reason_count, thread_count - 1)
+            self.assertEqual(no_stop_reason_count, self.THREAD_COUNT - 1)
 
         # Only one thread should should indicate a stop reason.
         self.assertEqual(with_stop_reason_count, 1)
-
-    @debugserver_test
-    def test_qThreadStopInfo_only_reports_one_thread_stop_reason_during_interrupt_debugserver(
-            self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.qThreadStopInfo_only_reports_one_thread_stop_reason_during_interrupt(
-            self.THREAD_COUNT)
-
-    @expectedFailureAll(oslist=["freebsd"], bugnumber="llvm.org/pr48418")
-    @expectedFailureNetBSD
-    @llgs_test
-    def test_qThreadStopInfo_only_reports_one_thread_stop_reason_during_interrupt_llgs(
-            self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.qThreadStopInfo_only_reports_one_thread_stop_reason_during_interrupt(
-            self.THREAD_COUNT)
-
-    def qThreadStopInfo_has_valid_thread_names(
-            self, thread_count, expected_thread_name):
-        (_, thread_dicts) = self.gather_stop_replies_via_qThreadStopInfo(thread_count)
-        self.assertIsNotNone(thread_dicts)
-
-        for thread_dict in list(thread_dicts.values()):
-            name = thread_dict.get("name")
-            self.assertIsNotNone(name)
-            self.assertEqual(name, expected_thread_name)
-
-    @unittest2.skip("MacOSX doesn't have a default thread name")
-    @debugserver_test
-    def test_qThreadStopInfo_has_valid_thread_names_debugserver(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.qThreadStopInfo_has_valid_thread_names(self.THREAD_COUNT, "a.out")
-
-    # test requires OS with set, equal thread names by default.
-    # Windows thread does not have name property, equal names as the process's by default.
-    @skipUnlessPlatform(["linux", "windows"])
-    @llgs_test
-    def test_qThreadStopInfo_has_valid_thread_names_llgs(self):
-        self.build()
-        self.set_inferior_startup_launch()
-        self.qThreadStopInfo_has_valid_thread_names(self.THREAD_COUNT, "a.out")
diff --git a/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py b/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
index d3bbfe03dbd8c..0a93f2ceba089 100644
--- a/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
+++ b/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
@@ -25,7 +25,6 @@ class LldbGdbServerTestCase(gdbremote_testcase.GdbRemoteTestCaseBase, DwarfOpcod
     mydir = TestBase.compute_mydir(__file__)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_exe_starts_debugserver(self):
         server = self.connect_to_debug_monitor()
 
@@ -46,7 +45,6 @@ def thread_suffix_supported(self):
         self.expect_gdbremote_sequence()
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_thread_suffix_supported_debugserver(self):
         self.thread_suffix_supported()
 
@@ -66,7 +64,6 @@ def list_threads_in_stop_reply_supported(self):
         self.expect_gdbremote_sequence()
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_list_threads_in_stop_reply_supported_debugserver(self):
         self.list_threads_in_stop_reply_supported()
 
@@ -84,7 +81,6 @@ def c_packet_works(self):
         self.expect_gdbremote_sequence()
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_c_packet_works_debugserver(self):
         self.build()
         self.c_packet_works()
@@ -107,7 +103,6 @@ def inferior_print_exit(self):
         self.assertIsNotNone(context)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_inferior_print_exit_debugserver(self):
         self.build()
         self.inferior_print_exit()
@@ -133,7 +128,6 @@ def first_launch_stop_reply_thread_matches_first_qC(self):
         self.expect_gdbremote_sequence()
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_first_launch_stop_reply_thread_matches_first_qC_debugserver(self):
         self.build()
         self.first_launch_stop_reply_thread_matches_first_qC()
@@ -167,7 +161,6 @@ def attach_commandline_continue_app_exits(self):
                 procs["inferior"].pid, False))
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_attach_commandline_continue_app_exits_debugserver(self):
         self.build()
         self.set_inferior_startup_attach()
@@ -196,7 +189,6 @@ def qRegisterInfo_returns_one_valid_result(self):
             lldbgdbserverutils.parse_reg_info_response(reg_info_packet))
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qRegisterInfo_returns_one_valid_result_debugserver(self):
         self.build()
         self.qRegisterInfo_returns_one_valid_result()
@@ -219,7 +211,6 @@ def qRegisterInfo_returns_all_valid_results(self):
             self.assert_valid_reg_info(reg_info)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qRegisterInfo_returns_all_valid_results_debugserver(self):
         self.build()
         self.qRegisterInfo_returns_all_valid_results()
@@ -258,7 +249,6 @@ def qRegisterInfo_contains_required_generics(self):
         self.assertTrue('flags' in generic_regs)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qRegisterInfo_contains_required_generics_debugserver(self):
         self.build()
         self.qRegisterInfo_contains_required_generics()
@@ -285,7 +275,6 @@ def qRegisterInfo_contains_at_least_one_register_set(self):
         self.assertTrue(len(register_sets) >= 1)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qRegisterInfo_contains_at_least_one_register_set_debugserver(
             self):
         self.build()
@@ -357,7 +346,6 @@ def qThreadInfo_contains_thread(self):
         self.assertEqual(len(threads), 1)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qThreadInfo_contains_thread_launch_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -370,7 +358,6 @@ def test_qThreadInfo_contains_thread_launch_llgs(self):
         self.qThreadInfo_contains_thread()
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qThreadInfo_contains_thread_attach_debugserver(self):
         self.build()
         self.set_inferior_startup_attach()
@@ -412,7 +399,6 @@ def qThreadInfo_matches_qC(self):
         self.assertEqual(threads[0], QC_thread_id)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qThreadInfo_matches_qC_launch_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -425,7 +411,6 @@ def test_qThreadInfo_matches_qC_launch_llgs(self):
         self.qThreadInfo_matches_qC()
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qThreadInfo_matches_qC_attach_debugserver(self):
         self.build()
         self.set_inferior_startup_attach()
@@ -492,7 +477,6 @@ def p_returns_correct_data_size_for_each_qRegisterInfo(self):
             reg_index += 1
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_p_returns_correct_data_size_for_each_qRegisterInfo_launch_debugserver(
             self):
         self.build()
@@ -508,7 +492,6 @@ def test_p_returns_correct_data_size_for_each_qRegisterInfo_launch_llgs(
         self.p_returns_correct_data_size_for_each_qRegisterInfo()
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_p_returns_correct_data_size_for_each_qRegisterInfo_attach_debugserver(
             self):
         self.build()
@@ -556,7 +539,6 @@ def Hg_switches_to_3_threads(self):
             self.assertEqual(int(context.get("thread_id"), 16), thread)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_Hg_switches_to_3_threads_launch_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -570,7 +552,6 @@ def test_Hg_switches_to_3_threads_launch_llgs(self):
         self.Hg_switches_to_3_threads()
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_Hg_switches_to_3_threads_attach_debugserver(self):
         self.build()
         self.set_inferior_startup_attach()
@@ -696,7 +677,6 @@ def Hc_then_Csignal_signals_correct_thread(self, segfault_signo):
 
     @expectedFailure
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_Hc_then_Csignal_signals_correct_thread_launch_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -767,7 +747,6 @@ def m_packet_reads_memory(self):
         self.assertEqual(read_contents, MEMORY_CONTENTS)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_m_packet_reads_memory_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -792,7 +771,6 @@ def qMemoryRegionInfo_is_supported(self):
         self.expect_gdbremote_sequence()
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qMemoryRegionInfo_is_supported_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -853,7 +831,6 @@ def qMemoryRegionInfo_reports_code_address_as_executable(self):
         self.assert_address_within_memory_region(code_address, mem_region_dict)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qMemoryRegionInfo_reports_code_address_as_executable_debugserver(
             self):
         self.build()
@@ -917,7 +894,6 @@ def qMemoryRegionInfo_reports_stack_address_as_readable_writeable(self):
             stack_address, mem_region_dict)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qMemoryRegionInfo_reports_stack_address_as_readable_writeable_debugserver(
             self):
         self.build()
@@ -981,7 +957,6 @@ def qMemoryRegionInfo_reports_heap_address_as_readable_writeable(self):
         self.assert_address_within_memory_region(heap_address, mem_region_dict)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qMemoryRegionInfo_reports_heap_address_as_readable_writeable_debugserver(
             self):
         self.build()
@@ -1129,7 +1104,6 @@ def breakpoint_set_and_remove_work(self, want_hardware=False):
         self.assertIsNotNone(context)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_software_breakpoint_set_and_remove_work_debugserver(self):
         if self.getArchitecture() == "arm":
             # TODO: Handle case when setting breakpoint in thumb code
@@ -1155,7 +1129,6 @@ def test_software_breakpoint_set_and_remove_work_llgs(self):
     @skipUnlessPlatform(oslist=['linux'])
     @expectedFailureAndroid
     @skipIf(archs=no_match(['arm', 'aarch64']))
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_hardware_breakpoint_set_and_remove_work_debugserver(self):
         if self.getArchitecture() == "arm":
             # TODO: Handle case when setting breakpoint in thumb code
@@ -1192,7 +1165,6 @@ def qSupported_returns_known_stub_features(self):
         self.assertTrue(len(supported_dict) > 0)
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_qSupported_returns_known_stub_features_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -1264,7 +1236,6 @@ def written_M_content_reads_back_correctly(self):
         self.assertEqual(printed_message, TEST_MESSAGE + "X")
 
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_written_M_content_reads_back_correctly_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -1313,7 +1284,6 @@ def P_writes_all_gpr_registers(self):
     # Come back to this.  I have the test rigged to verify that at least some
     # of the bit-flip writes work.
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_P_writes_all_gpr_registers_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -1436,7 +1406,6 @@ def P_and_p_thread_suffix_work(self):
     # Note: as of this moment, a hefty number of the GPR writes are failing
     # with E32 (everything except rax-rdx, rdi, rsi, rbp).
     @debugserver_test
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def test_P_and_p_thread_suffix_work_debugserver(self):
         self.build()
         self.set_inferior_startup_launch()
diff --git a/lldb/test/API/tools/lldb-server/commandline/TestGdbRemoteConnection.py b/lldb/test/API/tools/lldb-server/commandline/TestGdbRemoteConnection.py
index dda7d707a56ff..5a7220f76fe06 100644
--- a/lldb/test/API/tools/lldb-server/commandline/TestGdbRemoteConnection.py
+++ b/lldb/test/API/tools/lldb-server/commandline/TestGdbRemoteConnection.py
@@ -11,35 +11,16 @@ class TestGdbRemoteConnection(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     mydir = TestBase.compute_mydir(__file__)
 
-    @debugserver_test
-    # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
-    @skipIfDarwinEmbedded
-    def test_reverse_connect_debugserver(self):
-        self._reverse_connect()
-
-    @llgs_test
     @skipIfRemote  # reverse connect is not a supported use case for now
     def test_reverse_connect_llgs(self):
-        self._reverse_connect()
-
-    def _reverse_connect(self):
         # Reverse connect is the default connection method.
         self.connect_to_debug_monitor()
         # Verify we can do the handshake.  If that works, we'll call it good.
         self.do_handshake(self.sock)
 
-    @debugserver_test
-    @skipIfRemote
-    def test_named_pipe_debugserver(self):
-        self._named_pipe()
-
-    @llgs_test
     @skipIfRemote
     @skipIfWindows
     def test_named_pipe_llgs(self):
-        self._named_pipe()
-
-    def _named_pipe(self):
         family, type, proto, _, addr = socket.getaddrinfo(
             self.stub_hostname, 0, proto=socket.IPPROTO_TCP)[0]
         self.sock = socket.socket(family, type, proto)
diff --git a/lldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteAbort.py b/lldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteAbort.py
index 8bce3b9aa87bd..7df73ce4cbced 100644
--- a/lldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteAbort.py
+++ b/lldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteAbort.py
@@ -9,7 +9,6 @@
 class TestGdbRemoteAbort(gdbremote_testcase.GdbRemoteTestCaseBase):
     mydir = TestBase.compute_mydir(__file__)
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def inferior_abort_received(self):
         procs = self.prep_debug_monitor_and_inferior(inferior_args=["abort"])
         self.assertIsNotNone(procs)
diff --git a/lldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteSegFault.py b/lldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteSegFault.py
index b9b4bef011771..7a018bfd7f868 100644
--- a/lldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteSegFault.py
+++ b/lldb/test/API/tools/lldb-server/inferior-crash/TestGdbRemoteSegFault.py
@@ -11,7 +11,6 @@ class TestGdbRemoteSegFault(gdbremote_testcase.GdbRemoteTestCaseBase):
 
     GDB_REMOTE_STOP_CODE_BAD_ACCESS = 0x91
 
-    @skipIfDarwinEmbedded # <rdar://problem/34539270> lldb-server tests not updated to work on ios etc yet
     def inferior_seg_fault_received(self, expected_signo):
         procs = self.prep_debug_monitor_and_inferior(
             inferior_args=["segfault"])
diff --git a/lldb/test/API/tools/lldb-server/register-reading/TestGdbRemoteGPacket.py b/lldb/test/API/tools/lldb-server/register-reading/TestGdbRemoteGPacket.py
index 1380b63955b79..fb4edc86f5b7b 100644
--- a/lldb/test/API/tools/lldb-server/register-reading/TestGdbRemoteGPacket.py
+++ b/lldb/test/API/tools/lldb-server/register-reading/TestGdbRemoteGPacket.py
@@ -51,7 +51,6 @@ def run_test_g_packet(self):
 
     @skipIfOutOfTreeDebugserver
     @debugserver_test
-    @skipIfDarwinEmbedded
     def test_g_packet_debugserver(self):
         self.run_test_g_packet()
 
diff --git a/lldb/test/API/tools/lldb-server/signal-filtering/TestGdbRemote_QPassSignals.py b/lldb/test/API/tools/lldb-server/signal-filtering/TestGdbRemote_QPassSignals.py
index 946d53341bef4..8d4f464b8dee0 100644
--- a/lldb/test/API/tools/lldb-server/signal-filtering/TestGdbRemote_QPassSignals.py
+++ b/lldb/test/API/tools/lldb-server/signal-filtering/TestGdbRemote_QPassSignals.py
@@ -46,7 +46,6 @@ def signal_name_to_hex(signame):
         context = self.expect_gdbremote_sequence()
         self.assertIsNotNone(context)
 
-    @llgs_test
     @skipUnlessPlatform(["linux", "android"])
     def test_q_pass_signals(self):
         self.build()
@@ -61,7 +60,6 @@ def test_q_pass_signals(self):
             self.expect_signal(signo)
         self.expect_exit_code(len(signals_to_ignore))
 
-    @llgs_test
     @skipUnlessPlatform(["linux", "android"])
     def test_change_signals_at_runtime(self):
         self.build()
@@ -80,7 +78,6 @@ def test_change_signals_at_runtime(self):
 
     @skipIfWindows # no signal support
     @expectedFailureNetBSD
-    @llgs_test
     def test_default_signals_behavior(self):
         self.build()
         self.set_inferior_startup_launch()
@@ -93,7 +90,6 @@ def test_default_signals_behavior(self):
         self.expect_exit_code(0)
 
 
-    @llgs_test
     @skipUnlessPlatform(["linux", "android"])
     def test_support_q_pass_signals(self):
         self.build()
diff --git a/lldb/test/Shell/Unwind/basic-block-sections.test b/lldb/test/Shell/Unwind/basic-block-sections.test
index 7b24a86758636..8e563b7310571 100644
--- a/lldb/test/Shell/Unwind/basic-block-sections.test
+++ b/lldb/test/Shell/Unwind/basic-block-sections.test
@@ -12,22 +12,22 @@
 # RUN: %lldb %t -s %s -o exit | FileCheck  %s --check-prefix=BBSECTIONS
 
 # Reorder basic blocks so that main's basic blocks are discontiguous
-# RUN: echo "main.3" > %t.order
+# RUN: echo "main.__part.3" > %t.order
 # RUN: echo "bar" >> %t.order
 # RUN: echo "main" >> %t.order
-# RUN: echo "main.2" >> %t.order
+# RUN: echo "main.__part.2" >> %t.order
 # RUN: echo "foo" >> %t.order
-# RUN: echo "main.1" >> %t.order
+# RUN: echo "main.__part.1" >> %t.order
 # RUN: %clang_host %p/Inputs/basic-block-sections.c -o %t -fbasic-block-sections=all -fuse-ld=lld -Wl,--symbol-ordering-file,%t.order -Wl,--warn-symbol-ordering -Wl,--fatal-warnings
 # RUN: %lldb %t -s %s -o exit | FileCheck  %s --check-prefix=BBSECTIONS
 
 # Test the reverse permutation too.
-# RUN: echo "main.1" > %t.order
+# RUN: echo "main.__part.1" > %t.order
 # RUN: echo "foo" >> %t.order
-# RUN: echo "main.2" >> %t.order
+# RUN: echo "main.__part.2" >> %t.order
 # RUN: echo "main" >> %t.order
 # RUN: echo "bar" >> %t.order
-# RUN: echo "main.3" >> %t.order
+# RUN: echo "main.__part.3" >> %t.order
 # RUN: %clang_host %p/Inputs/basic-block-sections.c -o %t -fbasic-block-sections=all -fuse-ld=lld -Wl,--symbol-ordering-file,%t.order -Wl,--warn-symbol-ordering -Wl,--fatal-warnings
 # RUN: %lldb %t -s %s -o exit | FileCheck  %s --check-prefix=BBSECTIONS
 
@@ -46,4 +46,4 @@ thread backtrace
 
 # BBSECTIONS: frame #0: {{.*}}`bar
 # BBSECTIONS: frame #1: {{.*}}`foo
-# BBSECTIONS: frame #2: {{.*}}`main.1 +
+# BBSECTIONS: frame #2: {{.*}}`main.__part.1 +
diff --git a/lldb/tools/driver/Driver.cpp b/lldb/tools/driver/Driver.cpp
index 870f763436a4e..e4a60127b65ed 100644
--- a/lldb/tools/driver/Driver.cpp
+++ b/lldb/tools/driver/Driver.cpp
@@ -732,7 +732,8 @@ void sigcont_handler(int signo) {
 
 void reproducer_handler(void *finalize_cmd) {
   if (SBReproducer::Generate()) {
-    std::system(static_cast<const char *>(finalize_cmd));
+    int result = std::system(static_cast<const char *>(finalize_cmd));
+    (void)result;
     fflush(stdout);
   }
 }
diff --git a/lldb/tools/lldb-test/SystemInitializerTest.cpp b/lldb/tools/lldb-test/SystemInitializerTest.cpp
index 10b90cdc64096..2f6eb8e21a21b 100644
--- a/lldb/tools/lldb-test/SystemInitializerTest.cpp
+++ b/lldb/tools/lldb-test/SystemInitializerTest.cpp
@@ -54,9 +54,6 @@ llvm::Error SystemInitializerTest::Initialize() {
 }
 
 void SystemInitializerTest::Terminate() {
-  static Timer::Category func_cat(LLVM_PRETTY_FUNCTION);
-  Timer scoped_timer(func_cat, LLVM_PRETTY_FUNCTION);
-
   Debugger::SettingsTerminate();
 
   // Terminate and unload and loaded system or user LLDB plug-ins
diff --git a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h
index 177155558df01..001adf1666b5d 100644
--- a/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h
+++ b/llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h
@@ -2721,51 +2721,55 @@ _SPIRV_OP(PowN, true, 10)
 
 class SPIRVAtomicInstBase : public SPIRVInstTemplateBase {
 public:
-  llvm::Optional<ExtensionID> getRequiredExtension() const override {
-    if (getOpCode() == OpAtomicFAddEXT)
-      return ExtensionID::SPV_EXT_shader_atomic_float_add;
-    return {};
-  }
-
   SPIRVCapVec getRequiredCapability() const override {
-    SPIRVCapVec CapVec;
-    if (!hasType())
-      return CapVec;
-
-    // Most atomic instructionsrequire a specific capability when
+    // Most of the atomic instructions require a specific capability when
     // operating on 64-bit integers.
-    if (getType()->isTypeInt(64)) {
-      // In SPIRV 1.2 spec only 2 atomic instructions have no result type:
-      // 1. OpAtomicStore - need to check type of the Value operand
-      // 2. OpAtomicFlagClear - doesn't require Int64Atomics capability.
-      CapVec.push_back(CapabilityInt64Atomics);
-    } else if (getOpCode() == OpAtomicFAddEXT) {
-      if (getType()->isTypeFloat(32))
-        CapVec.push_back(CapabilityAtomicFloat32AddEXT);
-      else if (getType()->isTypeFloat(64))
-        CapVec.push_back(CapabilityAtomicFloat64AddEXT);
-      else
-        llvm_unreachable(
-            "AtomicFAddEXT can only be generated for f32 or f64 types");
-    }
-    // Per the spec OpAtomicCompareExchangeWeak, OpAtomicFlagTestAndSet and
-    // OpAtomicFlagClear instructions require kernel capability. But this
-    // capability should be added by setting OpenCL memory model.
-    return CapVec;
+    // In SPIRV 1.2 spec, only 2 atomic instructions have no result type:
+    // 1. OpAtomicStore - need to check type of the Value operand
+    // 2. OpAtomicFlagClear - doesn't require Int64Atomics capability.
+    // Besides, OpAtomicCompareExchangeWeak, OpAtomicFlagTestAndSet and
+    // OpAtomicFlagClear instructions require the "kernel" capability. But this
+    // capability should be added by setting the OpenCL memory model.
+    if (hasType() && getType()->isTypeInt(64))
+      return {CapabilityInt64Atomics};
+    return {};
   }
 
   // Overriding the following method because of particular OpAtomic*
-  // instructions. We may have to declare additional capabilities,
-  // e.g. based on operand types.
+  // instructions that declare additional capabilities, e.g. based on operand
+  // types.
+  void setOpWords(const std::vector<SPIRVWord> &TheOps) override {
+    SPIRVInstTemplateBase::setOpWords(TheOps);
+    for (auto RC : getRequiredCapability())
+      Module->addCapability(RC);
+  }
+};
+
+class SPIRVAtomicStoreInst : public SPIRVAtomicInstBase {
+public:
+  // Overriding the following method because of 'const'-related
+  // issues with overriding getRequiredCapability(). TODO: Resolve.
   void setOpWords(const std::vector<SPIRVWord> &TheOps) override {
     SPIRVInstTemplateBase::setOpWords(TheOps);
     static const unsigned ValueOperandIndex = 3;
-    if (getOpCode() == OpAtomicStore &&
-        getOperand(ValueOperandIndex)->getType()->isTypeInt(64))
+    if (getOperand(ValueOperandIndex)->getType()->isTypeInt(64))
       Module->addCapability(CapabilityInt64Atomics);
-    if (getOpCode() == OpAtomicFAddEXT)
-      for (auto RC : getRequiredCapability())
-        Module->addCapability(RC);
+  }
+};
+
+class SPIRVAtomicFAddEXTInst : public SPIRVAtomicInstBase {
+public:
+  llvm::Optional<ExtensionID> getRequiredExtension() const override {
+    return ExtensionID::SPV_EXT_shader_atomic_float_add;
+  }
+
+  SPIRVCapVec getRequiredCapability() const override {
+    assert(hasType());
+    if (getType()->isTypeFloat(32))
+      return {CapabilityAtomicFloat32AddEXT};
+    assert(getType()->isTypeFloat(64) &&
+           "AtomicFAddEXT can only be generated for f32 or f64 types");
+    return {CapabilityAtomicFloat64AddEXT};
   }
 };
 
@@ -2775,7 +2779,6 @@ class SPIRVAtomicInstBase : public SPIRVInstTemplateBase {
 _SPIRV_OP(AtomicFlagTestAndSet, true, 6)
 _SPIRV_OP(AtomicFlagClear, false, 4)
 _SPIRV_OP(AtomicLoad, true, 6)
-_SPIRV_OP(AtomicStore, false, 5)
 _SPIRV_OP(AtomicExchange, true, 7)
 _SPIRV_OP(AtomicCompareExchange, true, 9)
 _SPIRV_OP(AtomicCompareExchangeWeak, true, 9)
@@ -2790,9 +2793,14 @@ _SPIRV_OP(AtomicSMax, true, 7)
 _SPIRV_OP(AtomicAnd, true, 7)
 _SPIRV_OP(AtomicOr, true, 7)
 _SPIRV_OP(AtomicXor, true, 7)
-_SPIRV_OP(AtomicFAddEXT, true, 7)
 _SPIRV_OP(MemoryBarrier, false, 3)
 #undef _SPIRV_OP
+#define _SPIRV_OP(x, BaseClass, ...)                                           \
+  typedef SPIRVInstTemplate<SPIRV##BaseClass, Op##x, __VA_ARGS__> SPIRV##x;
+// Specialized atomic builtins
+_SPIRV_OP(AtomicStore, AtomicStoreInst, false, 5)
+_SPIRV_OP(AtomicFAddEXT, AtomicFAddEXTInst, true, 7)
+#undef _SPIRV_OP
 
 class SPIRVImageInstBase : public SPIRVInstTemplateBase {
 public:
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 3dbdfa7764dcd..f9246000f3eb8 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -104,6 +104,11 @@ specify the AMDGPU processor together with optional target features. See
 :ref:`amdgpu-target-id` and :ref:`amdgpu-target-features` for AMD GPU target
 specific information.
 
+Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following exceptions:
+
+* ``amdhsa`` is not supported in ``r600`` architecture (see :ref:`amdgpu-architecture-table`).
+
+
   .. table:: AMDGPU Processors
      :name: amdgpu-processor-table
 
diff --git a/llvm/docs/CodingStandards.rst b/llvm/docs/CodingStandards.rst
index a5798bd73cb13..57d148df89f80 100644
--- a/llvm/docs/CodingStandards.rst
+++ b/llvm/docs/CodingStandards.rst
@@ -77,7 +77,7 @@ on the standard library facilities and the LLVM support libraries as much as
 possible.
 
 LLVM support libraries (for example, `ADT
-<https://github.com/llvm/llvm-project/tree/master/llvm/include/llvm/ADT>`_)
+<https://github.com/llvm/llvm-project/tree/main/llvm/include/llvm/ADT>`_)
 implement specialized data structures or functionality missing in the standard
 library. Such libraries are usually implemented in the ``llvm`` namespace and
 follow the expected standard interface, when there is one.
diff --git a/llvm/docs/Coroutines.rst b/llvm/docs/Coroutines.rst
index 77fb77d9a9673..268e9c79ac8fd 100644
--- a/llvm/docs/Coroutines.rst
+++ b/llvm/docs/Coroutines.rst
@@ -1389,6 +1389,48 @@ The following table summarizes the handling of `coro.end`_ intrinsic.
 |            | Landingpad  | nothing           | nothing                       |
 +------------+-------------+-------------------+-------------------------------+
 
+
+'llvm.coro.end.async' Intrinsic
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+::
+
+  declare i1 @llvm.coro.end.async(i8* <handle>, i1 <unwind>, ...)
+
+Overview:
+"""""""""
+
+The '``llvm.coro.end.async``' marks the point where execution of the resume part
+of the coroutine should end and control should return to the caller. As part of
+its variable tail arguments this instruction allows to specify a function and
+the function's arguments that are to be tail called as the last action before
+returning.
+
+
+Arguments:
+""""""""""
+
+The first argument should refer to the coroutine handle of the enclosing
+coroutine. A frontend is allowed to supply null as the first parameter, in this
+case `coro-early` pass will replace the null with an appropriate coroutine
+handle value.
+
+The second argument should be `true` if this coro.end is in the block that is
+part of the unwind sequence leaving the coroutine body due to an exception and
+`false` otherwise.
+
+The third argument if present should specify a function to be called.
+
+If the third argument is present, the remaining arguments are the arguments to
+the function call.
+
+.. code-block:: llvm
+
+  call i1 (i8*, i1, ...) @llvm.coro.end.async(
+                           i8* %hdl, i1 0,
+                           void (i8*, %async.task*, %async.actor*)* @must_tail_call_return,
+                           i8* %ctxt, %async.task* %task, %async.actor* %actor)
+  unreachable
+
 .. _coro.suspend:
 .. _suspend points:
 
diff --git a/llvm/docs/DeveloperPolicy.rst b/llvm/docs/DeveloperPolicy.rst
index 3fa629965318c..7bcb5664540a3 100644
--- a/llvm/docs/DeveloperPolicy.rst
+++ b/llvm/docs/DeveloperPolicy.rst
@@ -80,7 +80,7 @@ Making and Submitting a Patch
 When making a patch for review, the goal is to make it as easy for the reviewer
 to read it as possible.  As such, we recommend that you:
 
-#. Make your patch against git master, not a branch, and not an old version
+#. Make your patch against git main, not a branch, and not an old version
    of LLVM.  This makes it easy to apply the patch.  For information on how to
    clone from git, please see the :ref:`Getting Started Guide
    <checkout>`.
@@ -146,7 +146,7 @@ problem, we have a notion of an 'owner' for a piece of the code.  The sole
 responsibility of a code owner is to ensure that a commit to their area of the
 code is appropriately reviewed, either by themself or by someone else.  The list
 of current code owners can be found in the file `CODE_OWNERS.TXT
-<https://github.com/llvm/llvm-project/blob/master/llvm/CODE_OWNERS.TXT>`_ in the
+<https://github.com/llvm/llvm-project/blob/main/llvm/CODE_OWNERS.TXT>`_ in the
 root of the LLVM source tree.
 
 Note that code ownership is completely different than reviewers: anyone can
diff --git a/llvm/docs/FAQ.rst b/llvm/docs/FAQ.rst
index aef15d6dc711d..229ac99f703c1 100644
--- a/llvm/docs/FAQ.rst
+++ b/llvm/docs/FAQ.rst
@@ -13,7 +13,7 @@ Can I modify LLVM source code and redistribute the modified source?
 -------------------------------------------------------------------
 Yes.  The modified source distribution must retain the copyright notice and
 follow the conditions listed in the `Apache License v2.0 with LLVM Exceptions
-<https://github.com/llvm/llvm-project/blob/master/llvm/LICENSE.TXT>`_.
+<https://github.com/llvm/llvm-project/blob/main/llvm/LICENSE.TXT>`_.
 
 
 Can I modify the LLVM source code and redistribute binaries or other tools based on it, without redistributing the source?
diff --git a/llvm/docs/GettingStarted.rst b/llvm/docs/GettingStarted.rst
index d4e4a3b039280..a2274f80fc1f0 100644
--- a/llvm/docs/GettingStarted.rst
+++ b/llvm/docs/GettingStarted.rst
@@ -457,7 +457,7 @@ either via emailing to llvm-commits, or, preferably, via :ref:`Phabricator
 
 You'll generally want to make sure your branch has a single commit,
 corresponding to the review you wish to send, up-to-date with the upstream
-``origin/master`` branch, and doesn't contain merges. Once you have that, you
+``origin/main`` branch, and doesn't contain merges. Once you have that, you
 can start `a Phabricator review <Phabricator.html>`_ (or use ``git show`` or
 ``git format-patch`` to output the diff, and attach it to an email message).
 
@@ -501,7 +501,7 @@ For developers to commit changes from Git
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Once a patch is reviewed, you should rebase it, re-test locally, and commit the
-changes to LLVM's master branch. This is done using `git push` if you have the
+changes to LLVM's main branch. This is done using `git push` if you have the
 required access rights. See `committing a change
 <Phabricator.html#committing-a-change>`_ for Phabricator based commits or
 `obtaining commit access <DeveloperPolicy.html#obtaining-commit-access>`_
@@ -515,13 +515,13 @@ accepted commit on the branch named `branch-with-change`.
   # Go to the branch with your accepted commit.
   % git checkout branch-with-change
   # Rebase your change onto the latest commits on Github.
-  % git pull --rebase origin master
+  % git pull --rebase origin main
   # Rerun the appropriate tests if needed.
   % ninja check-$whatever
   # Check that the list of commits about to be pushed is correct.
-  % git log origin/master...HEAD --oneline
+  % git log origin/main...HEAD --oneline
   # Push to Github.
-  % git push origin HEAD:master
+  % git push origin HEAD:main
 
 LLVM currently has a linear-history policy, which means that merge commits are
 not allowed. The `llvm-project` repo on github is configured to reject pushes
diff --git a/llvm/docs/GitBisecting.rst b/llvm/docs/GitBisecting.rst
index 8f44e351a085f..81876c74caa7b 100644
--- a/llvm/docs/GitBisecting.rst
+++ b/llvm/docs/GitBisecting.rst
@@ -23,7 +23,7 @@ See https://git-scm.com/docs/git-bisect for a good overview. In summary:
   .. code-block:: bash
 
      git bisect start
-     git bisect bad master
+     git bisect bad main
      git bisect good f00ba
 
 git will check out a revision in between. Try to reproduce your problem at
@@ -33,8 +33,8 @@ If you can't repro at the current commit (maybe the build is broken), run
 ``git bisect skip`` and git will pick a nearby alternate commit.
 
 (To abort a bisect, run ``git bisect reset``, and if git complains about not
-being able to reset, do the usual ``git checkout -f master; git reset --hard
-origin/master`` dance and try again).
+being able to reset, do the usual ``git checkout -f main; git reset --hard
+origin/main`` dance and try again).
 
 ``git bisect run``
 ==================
diff --git a/llvm/docs/GlobalISel/IRTranslator.rst b/llvm/docs/GlobalISel/IRTranslator.rst
index 712fe95a82925..9e12fdcbcbe5b 100644
--- a/llvm/docs/GlobalISel/IRTranslator.rst
+++ b/llvm/docs/GlobalISel/IRTranslator.rst
@@ -91,5 +91,5 @@ This is beneficial as it allows us to fold constants into immediate operands
 during :ref:`instructionselect`, while still avoiding redundant materializations
 for expensive non-foldable constants. However, this can lead to unnecessary
 spills and reloads in an -O0 pipeline, as these virtual registers can have long
-live ranges. This can be mitigated by running a `localizer <https://github.com/llvm/llvm-project/blob/master/llvm/lib/CodeGen/GlobalISel/Localizer.cpp>`_
+live ranges. This can be mitigated by running a `localizer <https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/GlobalISel/Localizer.cpp>`_
 after the translator.
diff --git a/llvm/docs/HowToReleaseLLVM.rst b/llvm/docs/HowToReleaseLLVM.rst
index b0308a1841946..2fce4777175e0 100644
--- a/llvm/docs/HowToReleaseLLVM.rst
+++ b/llvm/docs/HowToReleaseLLVM.rst
@@ -50,9 +50,16 @@ The release process is roughly as follows:
 
 * Finally, release!
 
-The release process will be accelerated for dot releases.  If the first round
-of testing finds no critical bugs and no regressions since the last major release,
-then additional rounds of testing will not be required.
+* Announce bug fix release schedule to the LLVM community and update the website.
+
+* Tag bug fix -rc1 after 4 weeks have passed.
+
+* Tag bug fix -rc2 4 weeks after -rc1.
+
+* Tag additional -rc candidates, if needed, to fix critical issues in
+  previous -rc releases.
+
+* Tag final release.
 
 Release Process
 ===============
@@ -119,7 +126,7 @@ Tag release candidates:
 
   $ git tag -a llvmorg-X.Y.Z-rcN
 
-The Release Manager may supply pre-packaged source tarballs for users.  This can
+The Release Manager must supply pre-packaged source tarballs for users.  This can
 be done with the export.sh script in utils/release.
 
 Tarballs, release binaries,  or any other release artifacts must be uploaded to
@@ -153,23 +160,16 @@ The minimum required version of the tools you'll need are :doc:`here <GettingSta
 Release Qualification Criteria
 ------------------------------
 
-A release is qualified when it has no regressions from the previous release (or
-baseline).  Regressions are related to correctness first and performance second.
-(We may tolerate some minor performance regressions if they are deemed
-necessary for the general quality of the compiler.)
+There are no official release qualification criteria.  It is up to the
+the release manager to determine when a release is ready.  The release manager
+should pay attention to the results of community testing, the number of outstanding
+bugs, and then number of regressions when determining whether or not to make a
+release.
 
-More specifically, Clang/LLVM is qualified when it has a clean test with all
-supported sub-projects included (``make check-all``), per target, and it has no
-regressions with the ``test-suite`` in relation to the previous release.
-
-Regressions are new failures in the set of tests that are used to qualify
-each product and only include things on the list.  Every release will have
-some bugs in it.  It is the reality of developing a complex piece of
-software.  We need a very concrete and definitive release criteria that
-ensures we have monotonically improving quality on some metric.  The metric we
-use is described below.  This doesn't mean that we don't care about other
-criteria, but these are the criteria which we found to be most important and
-which must be satisfied before a release can go out.
+The community values time based releases, so releases should not be delayed for
+too long unless there are critical issues remaining.  In most cases, the only
+kind of bugs that are critical enough to block a release would be a major regression
+from a previous release.
 
 Official Testing
 ----------------
@@ -288,17 +288,26 @@ Below are the rules regarding patching the release branch:
    manager, the official release testers or the code owners with approval from
    the release manager.
 
-#. During the first round of testing, patches that fix regressions or that are
-   small and relatively risk free (verified by the appropriate code owner) are
-   applied to the branch.  Code owners are asked to be very conservative in
-   approving patches for the branch.  We reserve the right to reject any patch
-   that does not fix a regression as previously defined.
+#. Release managers are encouraged, but not required, to get approval from code
+   owners before approving patches.  If there is no code owner or the code owner
+   is unreachable then release managers can ask approval from patch reviewers or
+   other developers active in that area.
+
+#. *Before RC1* Patches should be limited to bug fixes, important optimization
+   improvements, or completion of features that were started before the branch
+   was created.  As with all phases, release managers and code owners can reject
+   patches that are deemed too invasive.
+
+#. *Before RC2* Patches should be limited to bug fixes or backend specific
+   improvements that are determined to be very safe.
+
+#. *Before RC3/Final Major Release* Patches should be limited to critical
+   bugs or regressions.
 
-#. During the remaining rounds of testing, only patches that fix critical
-   regressions may be applied.
+#. *Bug fix releases* Patches should be limited to bug fixes or very safe
+   and critical performance improvements.  Patches must maintain both API and
+   ABI compatibility with the previous major release.
 
-#. For dot releases all patches must maintain both API and ABI compatibility with
-   the previous major release.  Only bug-fixes will be accepted.
 
 Merging Patches
 ^^^^^^^^^^^^^^^
diff --git a/llvm/docs/LibFuzzer.rst b/llvm/docs/LibFuzzer.rst
index 70a3f029c6f3e..b251895bc8e90 100644
--- a/llvm/docs/LibFuzzer.rst
+++ b/llvm/docs/LibFuzzer.rst
@@ -571,7 +571,7 @@ Periodically restart both fuzzers so that they can use each other's findings.
 Currently, there is no simple way to run both fuzzing engines in parallel while sharing the same corpus dir.
 
 You may also use AFL on your target function ``LLVMFuzzerTestOneInput``:
-see an example `here <https://github.com/llvm/llvm-project/tree/master/compiler-rt/lib/fuzzer/afl>`__.
+see an example `here <https://github.com/llvm/llvm-project/tree/main/compiler-rt/lib/fuzzer/afl>`__.
 
 How good is my fuzzer?
 ----------------------
@@ -815,7 +815,7 @@ Trophies
 .. _AddressSanitizer: https://clang.llvm.org/docs/AddressSanitizer.html
 .. _LeakSanitizer: https://clang.llvm.org/docs/LeakSanitizer.html
 .. _Heartbleed: http://en.wikipedia.org/wiki/Heartbleed
-.. _FuzzerInterface.h: https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/fuzzer/FuzzerInterface.h
+.. _FuzzerInterface.h: https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/fuzzer/FuzzerInterface.h
 .. _3.7.0: https://llvm.org/releases/3.7.0/docs/LibFuzzer.html
 .. _building Clang from trunk: https://clang.llvm.org/get_started.html
 .. _MemorySanitizer: https://clang.llvm.org/docs/MemorySanitizer.html
diff --git a/llvm/docs/TableGen/ProgRef.rst b/llvm/docs/TableGen/ProgRef.rst
index 342b91a0c437b..f2ee7a7e549a8 100644
--- a/llvm/docs/TableGen/ProgRef.rst
+++ b/llvm/docs/TableGen/ProgRef.rst
@@ -216,7 +216,8 @@ TableGen provides "bang operators" that have a wide variety of uses:
                : !interleave !isa         !le          !listconcat  !listsplat
                : !lt         !mul         !ne          !not         !or
                : !setdagop   !shl         !size        !sra         !srl
-               : !strconcat  !sub         !subst       !tail        !xor
+               : !strconcat  !sub         !subst       !substr      !tail
+               : !xor
 
 The ``!cond`` operator has a slightly different
 syntax compared to other bang operators, so it is defined separately:
@@ -1723,6 +1724,13 @@ and non-0 as true.
     record if the *target* record name equals the *value* record name; otherwise it
     produces the *value*.
 
+``!substr(``\ *string*\ ``,`` *start*\ [``,`` *length*]\ ``)``
+    This operator extracts a substring of the given *string*. The starting
+    position of the substring is specified by *start*, which can range
+    between 0 and the length of the string. The length of the substring
+    is specified by *length*; if not specified, the rest of the string is
+    extracted. The *start* and *length* arguments must be integers.
+
 ``!tail(``\ *a*\ ``)``
     This operator produces a new list with all the elements
     of the list *a* except for the zeroth one. (See also ``!head``.)
diff --git a/llvm/docs/TestingGuide.rst b/llvm/docs/TestingGuide.rst
index 0f91292057569..2070e38427615 100644
--- a/llvm/docs/TestingGuide.rst
+++ b/llvm/docs/TestingGuide.rst
@@ -73,7 +73,7 @@ transforming it. They are tested in general using the same infrastructure as the
 regression tests, by creating a separate "Printer" pass to consume the analysis
 result and print it on the standard output in a textual format suitable for
 FileCheck.
-See `llvm/test/Analysis/BranchProbabilityInfo/loop.ll <https://github.com/llvm/llvm-project/blob/master/llvm/test/Analysis/BranchProbabilityInfo/loop.ll>`_
+See `llvm/test/Analysis/BranchProbabilityInfo/loop.ll <https://github.com/llvm/llvm-project/blob/main/llvm/test/Analysis/BranchProbabilityInfo/loop.ll>`_
 for an example of such test.
 
 ``test-suite``
diff --git a/llvm/docs/TypeMetadata.rst b/llvm/docs/TypeMetadata.rst
index 74d439411497e..5fa864dc8ab21 100644
--- a/llvm/docs/TypeMetadata.rst
+++ b/llvm/docs/TypeMetadata.rst
@@ -223,7 +223,7 @@ efficiently to minimize the sizes of the underlying bitsets.
       ret void
     }
 
-.. _GlobalLayoutBuilder: https://github.com/llvm/llvm-project/blob/master/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h
+.. _GlobalLayoutBuilder: https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Transforms/IPO/LowerTypeTests.h
 
 ``!vcall_visibility`` Metadata
 ==============================
diff --git a/llvm/include/llvm/ADT/SmallVector.h b/llvm/include/llvm/ADT/SmallVector.h
index 0a0f09c68060b..3bbde2d9c0fbc 100644
--- a/llvm/include/llvm/ADT/SmallVector.h
+++ b/llvm/include/llvm/ADT/SmallVector.h
@@ -460,7 +460,8 @@ class SmallVectorImpl : public SmallVectorTemplateBase<T> {
     this->Size = 0;
   }
 
-  void resize(size_type N) {
+private:
+  template <bool ForOverwrite> void resizeImpl(size_type N) {
     if (N < this->size()) {
       this->destroy_range(this->begin()+N, this->end());
       this->set_size(N);
@@ -468,11 +469,20 @@ class SmallVectorImpl : public SmallVectorTemplateBase<T> {
       if (this->capacity() < N)
         this->grow(N);
       for (auto I = this->end(), E = this->begin() + N; I != E; ++I)
-        new (&*I) T();
+        if (ForOverwrite)
+          new (&*I) T;
+        else
+          new (&*I) T();
       this->set_size(N);
     }
   }
 
+public:
+  void resize(size_type N) { resizeImpl<false>(N); }
+
+  /// Like resize, but \ref T is POD, the new values won't be initialized.
+  void resize_for_overwrite(size_type N) { resizeImpl<true>(N); }
+
   void resize(size_type N, const T &NV) {
     if (N == this->size())
       return;
diff --git a/llvm/include/llvm/Analysis/AliasAnalysis.h b/llvm/include/llvm/Analysis/AliasAnalysis.h
index b84febaeeeaa9..98a2a7fb075ae 100644
--- a/llvm/include/llvm/Analysis/AliasAnalysis.h
+++ b/llvm/include/llvm/Analysis/AliasAnalysis.h
@@ -1097,9 +1097,6 @@ template <typename DerivedT> class AAResultBase {
 /// Return true if this pointer is returned by a noalias function.
 bool isNoAliasCall(const Value *V);
 
-/// Return true if this is an argument with the noalias attribute.
-bool isNoAliasArgument(const Value *V);
-
 /// Return true if this pointer refers to a distinct and identifiable object.
 /// This returns true for:
 ///    Global Variables and Functions (but not Global Aliases)
diff --git a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
index 6eb37c1c4b07f..cffe9ed3c738f 100644
--- a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
+++ b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
@@ -117,6 +117,9 @@ class BasicAAResult : public AAResultBase<BasicAAResult> {
 
     APInt Scale;
 
+    // Context instruction to use when querying information about this index.
+    const Instruction *CxtI;
+
     bool operator==(const VariableGEPIndex &Other) const {
       return V == Other.V && ZExtBits == Other.ZExtBits &&
              SExtBits == Other.SExtBits && Scale == Other.Scale;
diff --git a/llvm/include/llvm/Analysis/BranchProbabilityInfo.h b/llvm/include/llvm/Analysis/BranchProbabilityInfo.h
index 64c3da80f6ea5..6a286236a80e8 100644
--- a/llvm/include/llvm/Analysis/BranchProbabilityInfo.h
+++ b/llvm/include/llvm/Analysis/BranchProbabilityInfo.h
@@ -27,6 +27,7 @@
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
+#include <memory>
 #include <utility>
 
 namespace llvm {
@@ -35,6 +36,7 @@ class Function;
 class Loop;
 class LoopInfo;
 class raw_ostream;
+class DominatorTree;
 class PostDominatorTree;
 class TargetLibraryInfo;
 class Value;
@@ -51,20 +53,79 @@ class Value;
 /// identify an edge, since we can have multiple edges from Src to Dst.
 /// As an example, we can have a switch which jumps to Dst with value 0 and
 /// value 10.
+///
+/// Process of computing branch probabilities can be logically viewed as three
+/// step process:
+///
+///   First, if there is a profile information associated with the branch then
+/// it is trivially translated to branch probabilities. There is one exception
+/// from this rule though. Probabilities for edges leading to "unreachable"
+/// blocks (blocks with the estimated weight not greater than
+/// UNREACHABLE_WEIGHT) are evaluated according to static estimation and
+/// override profile information. If no branch probabilities were calculated
+/// on this step then take the next one.
+///
+///   Second, estimate absolute execution weights for each block based on
+/// statically known information. Roots of such information are "cold",
+/// "unreachable", "noreturn" and "unwind" blocks. Those blocks get their
+/// weights set to BlockExecWeight::COLD, BlockExecWeight::UNREACHABLE,
+/// BlockExecWeight::NORETURN and BlockExecWeight::UNWIND respectively. Then the
+/// weights are propagated to the other blocks up the domination line. In
+/// addition, if all successors have estimated weights set then maximum of these
+/// weights assigned to the block itself (while this is not ideal heuristic in
+/// theory it's simple and works reasonably well in most cases) and the process
+/// repeats. Once the process of weights propagation converges branch
+/// probabilities are set for all such branches that have at least one successor
+/// with the weight set. Default execution weight (BlockExecWeight::DEFAULT) is
+/// used for any successors which doesn't have its weight set. For loop back
+/// branches we use their weights scaled by loop trip count equal to
+/// 'LBH_TAKEN_WEIGHT/LBH_NOTTAKEN_WEIGHT'.
+///
+/// Here is a simple example demonstrating how the described algorithm works.
+///
+///          BB1
+///         /   \
+///        v     v
+///      BB2     BB3
+///     /   \
+///    v     v
+///  ColdBB  UnreachBB
+///
+/// Initially, ColdBB is associated with COLD_WEIGHT and UnreachBB with
+/// UNREACHABLE_WEIGHT. COLD_WEIGHT is set to BB2 as maximum between its
+/// successors. BB1 and BB3 has no explicit estimated weights and assumed to
+/// have DEFAULT_WEIGHT. Based on assigned weights branches will have the
+/// following probabilities:
+/// P(BB1->BB2) = COLD_WEIGHT/(COLD_WEIGHT + DEFAULT_WEIGHT) =
+///   0xffff / (0xffff + 0xfffff) = 0.0588(5.9%)
+/// P(BB1->BB3) = DEFAULT_WEIGHT_WEIGHT/(COLD_WEIGHT + DEFAULT_WEIGHT) =
+///          0xfffff / (0xffff + 0xfffff) = 0.941(94.1%)
+/// P(BB2->ColdBB) = COLD_WEIGHT/(COLD_WEIGHT + UNREACHABLE_WEIGHT) = 1(100%)
+/// P(BB2->UnreachBB) =
+///   UNREACHABLE_WEIGHT/(COLD_WEIGHT+UNREACHABLE_WEIGHT) = 0(0%)
+///
+/// If no branch probabilities were calculated on this step then take the next
+/// one.
+///
+///   Third, apply different kinds of local heuristics for each individual
+/// branch until first match. For example probability of a pointer to be null is
+/// estimated as PH_TAKEN_WEIGHT/(PH_TAKEN_WEIGHT + PH_NONTAKEN_WEIGHT). If
+/// no local heuristic has been matched then branch is left with no explicit
+/// probability set and assumed to have default probability.
 class BranchProbabilityInfo {
 public:
   BranchProbabilityInfo() = default;
 
   BranchProbabilityInfo(const Function &F, const LoopInfo &LI,
                         const TargetLibraryInfo *TLI = nullptr,
+                        DominatorTree *DT = nullptr,
                         PostDominatorTree *PDT = nullptr) {
-    calculate(F, LI, TLI, PDT);
+    calculate(F, LI, TLI, DT, PDT);
   }
 
   BranchProbabilityInfo(BranchProbabilityInfo &&Arg)
       : Probs(std::move(Arg.Probs)), LastF(Arg.LastF),
-        PostDominatedByUnreachable(std::move(Arg.PostDominatedByUnreachable)),
-        PostDominatedByColdCall(std::move(Arg.PostDominatedByColdCall)) {}
+        EstimatedBlockWeight(std::move(Arg.EstimatedBlockWeight)) {}
 
   BranchProbabilityInfo(const BranchProbabilityInfo &) = delete;
   BranchProbabilityInfo &operator=(const BranchProbabilityInfo &) = delete;
@@ -72,8 +133,7 @@ class BranchProbabilityInfo {
   BranchProbabilityInfo &operator=(BranchProbabilityInfo &&RHS) {
     releaseMemory();
     Probs = std::move(RHS.Probs);
-    PostDominatedByColdCall = std::move(RHS.PostDominatedByColdCall);
-    PostDominatedByUnreachable = std::move(RHS.PostDominatedByUnreachable);
+    EstimatedBlockWeight = std::move(RHS.EstimatedBlockWeight);
     return *this;
   }
 
@@ -143,11 +203,13 @@ class BranchProbabilityInfo {
   }
 
   void calculate(const Function &F, const LoopInfo &LI,
-                 const TargetLibraryInfo *TLI, PostDominatorTree *PDT);
+                 const TargetLibraryInfo *TLI, DominatorTree *DT,
+                 PostDominatorTree *PDT);
 
   /// Forget analysis results for the given basic block.
   void eraseBlock(const BasicBlock *BB);
 
+  // Data structure to track SCCs for handling irreducible loops.
   class SccInfo {
     // Enum of types to classify basic blocks in SCC. Basic block belonging to
     // SCC is 'Inner' until it is either 'Header' or 'Exiting'. Note that a
@@ -236,6 +298,8 @@ class BranchProbabilityInfo {
                        const SccInfo &SccI);
 
     const BasicBlock *getBlock() const { return BB; }
+    BasicBlock *getBlock() { return const_cast<BasicBlock *>(BB); }
+    LoopData getLoopData() const { return LD; }
     Loop *getLoop() const { return LD.first; }
     int getSccNum() const { return LD.second; }
 
@@ -249,6 +313,7 @@ class BranchProbabilityInfo {
     const BasicBlock *const BB = nullptr;
     LoopData LD = {nullptr, -1};
   };
+
   // Pair of LoopBlocks representing an edge from first to second block.
   using LoopEdge = std::pair<const LoopBlock &, const LoopBlock &>;
 
@@ -258,27 +323,26 @@ class BranchProbabilityInfo {
   // a pair (PredBlock and an index in the successors) to specify an edge.
   using Edge = std::pair<const BasicBlock *, unsigned>;
 
-  // Default weight value. Used when we don't have information about the edge.
-  // TODO: DEFAULT_WEIGHT makes sense during static predication, when none of
-  // the successors have a weight yet. But it doesn't make sense when providing
-  // weight to an edge that may have siblings with non-zero weights. This can
-  // be handled various ways, but it's probably fine for an edge with unknown
-  // weight to just "inherit" the non-zero weight of an adjacent successor.
-  static const uint32_t DEFAULT_WEIGHT = 16;
-
   DenseMap<Edge, BranchProbability> Probs;
 
   /// Track the last function we run over for printing.
   const Function *LastF = nullptr;
 
+  const LoopInfo *LI = nullptr;
+
   /// Keeps information about all SCCs in a function.
   std::unique_ptr<const SccInfo> SccI;
 
-  /// Track the set of blocks directly succeeded by a returning block.
-  SmallPtrSet<const BasicBlock *, 16> PostDominatedByUnreachable;
+  /// Keeps mapping of a basic block to its estimated weight.
+  SmallDenseMap<const BasicBlock *, uint32_t> EstimatedBlockWeight;
+
+  /// Keeps mapping of a loop to estimated weight to enter the loop.
+  SmallDenseMap<LoopData, uint32_t> EstimatedLoopWeight;
 
-  /// Track the set of blocks that always lead to a cold call.
-  SmallPtrSet<const BasicBlock *, 16> PostDominatedByColdCall;
+  /// Helper to construct LoopBlock for \p BB.
+  LoopBlock getLoopBlock(const BasicBlock *BB) const {
+    return LoopBlock(BB, *LI, *SccI.get());
+  }
 
   /// Returns true if destination block belongs to some loop and source block is
   /// either doesn't belong to any loop or belongs to a loop which is not inner
@@ -301,18 +365,55 @@ class BranchProbabilityInfo {
   void getLoopExitBlocks(const LoopBlock &LB,
                          SmallVectorImpl<BasicBlock *> &Exits) const;
 
-  void computePostDominatedByUnreachable(const Function &F,
-                                         PostDominatorTree *PDT);
-  void computePostDominatedByColdCall(const Function &F,
-                                      PostDominatorTree *PDT);
-  bool calcUnreachableHeuristics(const BasicBlock *BB);
+  /// Returns estimated weight for \p BB. None if \p BB has no estimated weight.
+  Optional<uint32_t> getEstimatedBlockWeight(const BasicBlock *BB) const;
+
+  /// Returns estimated weight to enter \p L. In other words it is weight of
+  /// loop's header block not scaled by trip count. Returns None if \p L has no
+  /// no estimated weight.
+  Optional<uint32_t> getEstimatedLoopWeight(const LoopData &L) const;
+
+  /// Return estimated weight for \p Edge. Returns None if estimated weight is
+  /// unknown.
+  Optional<uint32_t> getEstimatedEdgeWeight(const LoopEdge &Edge) const;
+
+  /// Iterates over all edges leading from \p SrcBB to \p Successors and
+  /// returns maximum of all estimated weights. If at least one edge has unknown
+  /// estimated weight None is returned.
+  template <class IterT>
+  Optional<uint32_t>
+  getMaxEstimatedEdgeWeight(const LoopBlock &SrcBB,
+                            iterator_range<IterT> Successors) const;
+
+  /// If \p LoopBB has no estimated weight then set it to \p BBWeight and
+  /// return true. Otherwise \p BB's weight remains unchanged and false is
+  /// returned. In addition all blocks/loops that might need their weight to be
+  /// re-estimated are put into BlockWorkList/LoopWorkList.
+  bool updateEstimatedBlockWeight(LoopBlock &LoopBB, uint32_t BBWeight,
+                                  SmallVectorImpl<BasicBlock *> &BlockWorkList,
+                                  SmallVectorImpl<LoopBlock> &LoopWorkList);
+
+  /// Starting from \p LoopBB (including \p LoopBB itself) propagate \p BBWeight
+  /// up the domination tree.
+  void propagateEstimatedBlockWeight(const LoopBlock &LoopBB, DominatorTree *DT,
+                                     PostDominatorTree *PDT, uint32_t BBWeight,
+                                     SmallVectorImpl<BasicBlock *> &WorkList,
+                                     SmallVectorImpl<LoopBlock> &LoopWorkList);
+
+  /// Returns block's weight encoded in the IR.
+  Optional<uint32_t> getInitialEstimatedBlockWeight(const BasicBlock *BB);
+
+  // Computes estimated weights for all blocks in \p F.
+  void computeEestimateBlockWeight(const Function &F, DominatorTree *DT,
+                                   PostDominatorTree *PDT);
+
+  /// Based on computed weights by \p computeEstimatedBlockWeight set
+  /// probabilities on branches.
+  bool calcEstimatedHeuristics(const BasicBlock *BB);
   bool calcMetadataWeights(const BasicBlock *BB);
-  bool calcColdCallHeuristics(const BasicBlock *BB);
   bool calcPointerHeuristics(const BasicBlock *BB);
-  bool calcLoopBranchHeuristics(const BasicBlock *BB, const LoopInfo &LI);
   bool calcZeroHeuristics(const BasicBlock *BB, const TargetLibraryInfo *TLI);
   bool calcFloatingPointHeuristics(const BasicBlock *BB);
-  bool calcInvokeHeuristics(const BasicBlock *BB);
 };
 
 /// Analysis pass which computes \c BranchProbabilityInfo.
diff --git a/llvm/include/llvm/Analysis/CallGraph.h b/llvm/include/llvm/Analysis/CallGraph.h
index 98f9b0683fd45..4da448c9900b1 100644
--- a/llvm/include/llvm/Analysis/CallGraph.h
+++ b/llvm/include/llvm/Analysis/CallGraph.h
@@ -87,13 +87,6 @@ class CallGraph {
   /// or calling an external function.
   std::unique_ptr<CallGraphNode> CallsExternalNode;
 
-  /// Replace the function represented by this node by another.
-  ///
-  /// This does not rescan the body of the function, so it is suitable when
-  /// splicing the body of one function to another while also updating all
-  /// callers from the old function to the new.
-  void spliceFunction(const Function *From, const Function *To);
-
 public:
   explicit CallGraph(Module &M);
   CallGraph(CallGraph &&Arg);
diff --git a/llvm/include/llvm/Analysis/IRSimilarityIdentifier.h b/llvm/include/llvm/Analysis/IRSimilarityIdentifier.h
index 30f32492937a2..99a5fcb3a5781 100644
--- a/llvm/include/llvm/Analysis/IRSimilarityIdentifier.h
+++ b/llvm/include/llvm/Analysis/IRSimilarityIdentifier.h
@@ -122,6 +122,11 @@ struct IRInstructionData : ilist_node<IRInstructionData> {
   /// considered similar.
   bool Legal;
 
+  /// This is only relevant if we are wrapping a CmpInst where we needed to
+  /// change the predicate of a compare instruction from a greater than form
+  /// to a less than form.  It is None otherwise.
+  Optional<CmpInst::Predicate> RevisedPredicate;
+
   /// Gather the information that is difficult to gather for an Instruction, or
   /// is changed. i.e. the operands of an Instruction and the Types of those
   /// operands. This extra information allows for similarity matching to make
@@ -129,6 +134,17 @@ struct IRInstructionData : ilist_node<IRInstructionData> {
   /// Instruction performs the same operation.
   IRInstructionData(Instruction &I, bool Legality, IRInstructionDataList &IDL);
 
+  /// Get the predicate that the compare instruction is using for hashing the
+  /// instruction. the IRInstructionData must be wrapping a CmpInst.
+  CmpInst::Predicate getPredicate() const;
+
+  /// A function that swaps the predicates to their less than form if they are
+  /// in a greater than form. Otherwise, the predicate is unchanged.
+  ///
+  /// \param CI - The comparison operation to find a consistent preidcate for.
+  /// \return the consistent comparison predicate. 
+  static CmpInst::Predicate predicateForConsistency(CmpInst *CI);
+
   /// Hashes \p Value based on its opcode, types, and operand types.
   /// Two IRInstructionData instances produce the same hash when they perform
   /// the same operation.
@@ -161,6 +177,12 @@ struct IRInstructionData : ilist_node<IRInstructionData> {
     for (Value *V : ID.OperVals)
       OperTypes.push_back(V->getType());
 
+    if (isa<CmpInst>(ID.Inst))
+      return llvm::hash_combine(
+          llvm::hash_value(ID.Inst->getOpcode()),
+          llvm::hash_value(ID.Inst->getType()),
+          llvm::hash_value(ID.getPredicate()),
+          llvm::hash_combine_range(OperTypes.begin(), OperTypes.end()));
     return llvm::hash_combine(
         llvm::hash_value(ID.Inst->getOpcode()),
         llvm::hash_value(ID.Inst->getType()),
@@ -504,7 +526,20 @@ class IRSimilarityCandidate {
   /// \param B - The second IRInstructionCandidate, operand values, and current
   /// operand mappings to compare.
   /// \returns true if the IRSimilarityCandidates operands are compatible.
-  static bool compareOperandMapping(OperandMapping A, OperandMapping B);
+  static bool compareNonCommutativeOperandMapping(OperandMapping A,
+                                                  OperandMapping B);
+
+  /// Compare the operands in \p A and \p B and check that the current mapping
+  /// of global value numbers from \p A to \p B and \p B to \A is consistent
+  /// given that the operands are commutative.
+  ///
+  /// \param A - The first IRInstructionCandidate, operand values, and current
+  /// operand mappings to compare.
+  /// \param B - The second IRInstructionCandidate, operand values, and current
+  /// operand mappings to compare.
+  /// \returns true if the IRSimilarityCandidates operands are compatible.
+  static bool compareCommutativeOperandMapping(OperandMapping A,
+                                               OperandMapping B);
 
   /// Compare the start and end indices of the two IRSimilarityCandidates for
   /// whether they overlap. If the start instruction of one
diff --git a/llvm/include/llvm/Analysis/LazyBranchProbabilityInfo.h b/llvm/include/llvm/Analysis/LazyBranchProbabilityInfo.h
index f4249f74104cf..3c632f02905a7 100644
--- a/llvm/include/llvm/Analysis/LazyBranchProbabilityInfo.h
+++ b/llvm/include/llvm/Analysis/LazyBranchProbabilityInfo.h
@@ -63,7 +63,7 @@ class LazyBranchProbabilityInfoPass : public FunctionPass {
     BranchProbabilityInfo &getCalculated() {
       if (!Calculated) {
         assert(F && LI && "call setAnalysis");
-        BPI.calculate(*F, *LI, TLI, nullptr);
+        BPI.calculate(*F, *LI, TLI, nullptr, nullptr);
         Calculated = true;
       }
       return BPI;
diff --git a/llvm/include/llvm/Analysis/LazyCallGraph.h b/llvm/include/llvm/Analysis/LazyCallGraph.h
index f356aec9e0a17..7478e17263669 100644
--- a/llvm/include/llvm/Analysis/LazyCallGraph.h
+++ b/llvm/include/llvm/Analysis/LazyCallGraph.h
@@ -258,7 +258,6 @@ class LazyCallGraph {
     iterator begin() { return iterator(Edges.begin(), Edges.end()); }
     iterator end() { return iterator(Edges.end(), Edges.end()); }
 
-    Edge &operator[](int i) { return Edges[i]; }
     Edge &operator[](Node &N) {
       assert(EdgeIndexMap.find(&N) != EdgeIndexMap.end() && "No such edge!");
       auto &E = Edges[EdgeIndexMap.find(&N)->second];
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 6415e7bfe7c30..620bfb885b54b 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -46,7 +46,7 @@ class TargetTransformInfoImplBase {
 
   int getGEPCost(Type *PointeeType, const Value *Ptr,
                  ArrayRef<const Value *> Operands,
-                 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency) {
+                 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency) const {
     // In the basic model, we just assume that all-constant GEPs will be folded
     // into their uses via addressing modes.
     for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
@@ -59,28 +59,30 @@ class TargetTransformInfoImplBase {
   unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI,
                                             unsigned &JTSize,
                                             ProfileSummaryInfo *PSI,
-                                            BlockFrequencyInfo *BFI) {
+                                            BlockFrequencyInfo *BFI) const {
     (void)PSI;
     (void)BFI;
     JTSize = 0;
     return SI.getNumCases();
   }
 
-  unsigned getInliningThresholdMultiplier() { return 1; }
+  unsigned getInliningThresholdMultiplier() const { return 1; }
 
-  int getInlinerVectorBonusPercent() { return 150; }
+  int getInlinerVectorBonusPercent() const { return 150; }
 
-  unsigned getMemcpyCost(const Instruction *I) { return TTI::TCC_Expensive; }
+  unsigned getMemcpyCost(const Instruction *I) const {
+    return TTI::TCC_Expensive;
+  }
 
-  bool hasBranchDivergence() { return false; }
+  bool hasBranchDivergence() const { return false; }
 
-  bool useGPUDivergenceAnalysis() { return false; }
+  bool useGPUDivergenceAnalysis() const { return false; }
 
-  bool isSourceOfDivergence(const Value *V) { return false; }
+  bool isSourceOfDivergence(const Value *V) const { return false; }
 
-  bool isAlwaysUniform(const Value *V) { return false; }
+  bool isAlwaysUniform(const Value *V) const { return false; }
 
-  unsigned getFlatAddressSpace() { return -1; }
+  unsigned getFlatAddressSpace() const { return -1; }
 
   bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
                                   Intrinsic::ID IID) const {
@@ -96,7 +98,7 @@ class TargetTransformInfoImplBase {
     return nullptr;
   }
 
-  bool isLoweredToCall(const Function *F) {
+  bool isLoweredToCall(const Function *F) const {
     assert(F && "A concrete function must be provided to this routine.");
 
     // FIXME: These should almost certainly not be handled here, and instead
@@ -134,7 +136,7 @@ class TargetTransformInfoImplBase {
 
   bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
                                 AssumptionCache &AC, TargetLibraryInfo *LibInfo,
-                                HardwareLoopInfo &HWLoopInfo) {
+                                HardwareLoopInfo &HWLoopInfo) const {
     return false;
   }
 
@@ -170,39 +172,39 @@ class TargetTransformInfoImplBase {
   }
 
   void getUnrollingPreferences(Loop *, ScalarEvolution &,
-                               TTI::UnrollingPreferences &) {}
+                               TTI::UnrollingPreferences &) const {}
 
   void getPeelingPreferences(Loop *, ScalarEvolution &,
-                             TTI::PeelingPreferences &) {}
+                             TTI::PeelingPreferences &) const {}
 
-  bool isLegalAddImmediate(int64_t Imm) { return false; }
+  bool isLegalAddImmediate(int64_t Imm) const { return false; }
 
-  bool isLegalICmpImmediate(int64_t Imm) { return false; }
+  bool isLegalICmpImmediate(int64_t Imm) const { return false; }
 
   bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
                              bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
-                             Instruction *I = nullptr) {
+                             Instruction *I = nullptr) const {
     // Guess that only reg and reg+reg addressing is allowed. This heuristic is
     // taken from the implementation of LSR.
     return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
   }
 
-  bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) {
+  bool isLSRCostLess(TTI::LSRCost &C1, TTI::LSRCost &C2) const {
     return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
                     C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
            std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
                     C2.ScaleCost, C2.ImmCost, C2.SetupCost);
   }
 
-  bool isNumRegsMajorCostOfLSR() { return true; }
+  bool isNumRegsMajorCostOfLSR() const { return true; }
 
-  bool isProfitableLSRChainElement(Instruction *I) { return false; }
+  bool isProfitableLSRChainElement(Instruction *I) const { return false; }
 
-  bool canMacroFuseCmp() { return false; }
+  bool canMacroFuseCmp() const { return false; }
 
   bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI,
                   DominatorTree *DT, AssumptionCache *AC,
-                  TargetLibraryInfo *LibInfo) {
+                  TargetLibraryInfo *LibInfo) const {
     return false;
   }
 
@@ -210,40 +212,51 @@ class TargetTransformInfoImplBase {
 
   bool shouldFavorBackedgeIndex(const Loop *L) const { return false; }
 
-  bool isLegalMaskedStore(Type *DataType, Align Alignment) { return false; }
+  bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
+    return false;
+  }
 
-  bool isLegalMaskedLoad(Type *DataType, Align Alignment) { return false; }
+  bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
+    return false;
+  }
 
-  bool isLegalNTStore(Type *DataType, Align Alignment) {
+  bool isLegalNTStore(Type *DataType, Align Alignment) const {
     // By default, assume nontemporal memory stores are available for stores
     // that are aligned and have a size that is a power of 2.
     unsigned DataSize = DL.getTypeStoreSize(DataType);
     return Alignment >= DataSize && isPowerOf2_32(DataSize);
   }
 
-  bool isLegalNTLoad(Type *DataType, Align Alignment) {
+  bool isLegalNTLoad(Type *DataType, Align Alignment) const {
     // By default, assume nontemporal memory loads are available for loads that
     // are aligned and have a size that is a power of 2.
     unsigned DataSize = DL.getTypeStoreSize(DataType);
     return Alignment >= DataSize && isPowerOf2_32(DataSize);
   }
 
-  bool isLegalMaskedScatter(Type *DataType, Align Alignment) { return false; }
+  bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
+    return false;
+  }
 
-  bool isLegalMaskedGather(Type *DataType, Align Alignment) { return false; }
+  bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
+    return false;
+  }
 
-  bool isLegalMaskedCompressStore(Type *DataType) { return false; }
+  bool isLegalMaskedCompressStore(Type *DataType) const { return false; }
 
-  bool isLegalMaskedExpandLoad(Type *DataType) { return false; }
+  bool isLegalMaskedExpandLoad(Type *DataType) const { return false; }
 
-  bool hasDivRemOp(Type *DataType, bool IsSigned) { return false; }
+  bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
 
-  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) { return false; }
+  bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
+    return false;
+  }
 
-  bool prefersVectorizedAddressing() { return true; }
+  bool prefersVectorizedAddressing() const { return true; }
 
   int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
-                           bool HasBaseReg, int64_t Scale, unsigned AddrSpace) {
+                           bool HasBaseReg, int64_t Scale,
+                           unsigned AddrSpace) const {
     // Guess that all legal addressing mode are free.
     if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
                               AddrSpace))
@@ -251,83 +264,87 @@ class TargetTransformInfoImplBase {
     return -1;
   }
 
-  bool LSRWithInstrQueries() { return false; }
+  bool LSRWithInstrQueries() const { return false; }
 
-  bool isTruncateFree(Type *Ty1, Type *Ty2) { return false; }
+  bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
 
-  bool isProfitableToHoist(Instruction *I) { return true; }
+  bool isProfitableToHoist(Instruction *I) const { return true; }
 
-  bool useAA() { return false; }
+  bool useAA() const { return false; }
 
-  bool isTypeLegal(Type *Ty) { return false; }
+  bool isTypeLegal(Type *Ty) const { return false; }
 
-  unsigned getRegUsageForType(Type *Ty) { return 1; }
+  unsigned getRegUsageForType(Type *Ty) const { return 1; }
 
-  bool shouldBuildLookupTables() { return true; }
-  bool shouldBuildLookupTablesForConstant(Constant *C) { return true; }
+  bool shouldBuildLookupTables() const { return true; }
+  bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
 
-  bool useColdCCForColdCall(Function &F) { return false; }
+  bool useColdCCForColdCall(Function &F) const { return false; }
 
   unsigned getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts,
-                                    bool Insert, bool Extract) {
+                                    bool Insert, bool Extract) const {
     return 0;
   }
 
   unsigned getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
-                                            unsigned VF) {
+                                            unsigned VF) const {
     return 0;
   }
 
-  bool supportsEfficientVectorElementLoadStore() { return false; }
+  bool supportsEfficientVectorElementLoadStore() const { return false; }
 
-  bool enableAggressiveInterleaving(bool LoopHasReductions) { return false; }
+  bool enableAggressiveInterleaving(bool LoopHasReductions) const {
+    return false;
+  }
 
   TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
                                                     bool IsZeroCmp) const {
     return {};
   }
 
-  bool enableInterleavedAccessVectorization() { return false; }
+  bool enableInterleavedAccessVectorization() const { return false; }
 
-  bool enableMaskedInterleavedAccessVectorization() { return false; }
+  bool enableMaskedInterleavedAccessVectorization() const { return false; }
 
-  bool isFPVectorizationPotentiallyUnsafe() { return false; }
+  bool isFPVectorizationPotentiallyUnsafe() const { return false; }
 
   bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth,
                                       unsigned AddressSpace, unsigned Alignment,
-                                      bool *Fast) {
+                                      bool *Fast) const {
     return false;
   }
 
-  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) {
+  TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
     return TTI::PSK_Software;
   }
 
-  bool haveFastSqrt(Type *Ty) { return false; }
+  bool haveFastSqrt(Type *Ty) const { return false; }
 
-  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) { return true; }
+  bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
 
-  unsigned getFPOpCost(Type *Ty) { return TargetTransformInfo::TCC_Basic; }
+  unsigned getFPOpCost(Type *Ty) const {
+    return TargetTransformInfo::TCC_Basic;
+  }
 
   int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
-                            Type *Ty) {
+                            Type *Ty) const {
     return 0;
   }
 
   unsigned getIntImmCost(const APInt &Imm, Type *Ty,
-                         TTI::TargetCostKind CostKind) {
+                         TTI::TargetCostKind CostKind) const {
     return TTI::TCC_Basic;
   }
 
   unsigned getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm,
                              Type *Ty, TTI::TargetCostKind CostKind,
-                             Instruction *Inst = nullptr) {
+                             Instruction *Inst = nullptr) const {
     return TTI::TCC_Free;
   }
 
   unsigned getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
                                const APInt &Imm, Type *Ty,
-                               TTI::TargetCostKind CostKind) {
+                               TTI::TargetCostKind CostKind) const {
     return TTI::TCC_Free;
   }
 
@@ -350,7 +367,7 @@ class TargetTransformInfoImplBase {
 
   unsigned getRegisterBitWidth(bool Vector) const { return 32; }
 
-  unsigned getMinVectorRegisterBitWidth() { return 128; }
+  unsigned getMinVectorRegisterBitWidth() const { return 128; }
 
   bool shouldMaximizeVectorBandwidth(bool OptSize) const { return false; }
 
@@ -358,9 +375,8 @@ class TargetTransformInfoImplBase {
 
   unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
 
-  bool
-  shouldConsiderAddressTypePromotion(const Instruction &I,
-                                     bool &AllowPromotionWithoutCommonHeader) {
+  bool shouldConsiderAddressTypePromotion(
+      const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
     AllowPromotionWithoutCommonHeader = false;
     return false;
   }
@@ -399,7 +415,7 @@ class TargetTransformInfoImplBase {
   unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
   bool enableWritePrefetching() const { return false; }
 
-  unsigned getMaxInterleaveFactor(unsigned VF) { return 1; }
+  unsigned getMaxInterleaveFactor(unsigned VF) const { return 1; }
 
   unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
                                   TTI::TargetCostKind CostKind,
@@ -408,7 +424,7 @@ class TargetTransformInfoImplBase {
                                   TTI::OperandValueProperties Opd1PropInfo,
                                   TTI::OperandValueProperties Opd2PropInfo,
                                   ArrayRef<const Value *> Args,
-                                  const Instruction *CxtI = nullptr) {
+                                  const Instruction *CxtI = nullptr) const {
     // FIXME: A number of transformation tests seem to require these values
     // which seems a little odd for how arbitary there are.
     switch (Opcode) {
@@ -427,14 +443,14 @@ class TargetTransformInfoImplBase {
   }
 
   unsigned getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, int Index,
-                          VectorType *SubTp) {
+                          VectorType *SubTp) const {
     return 1;
   }
 
   unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
                             TTI::CastContextHint CCH,
                             TTI::TargetCostKind CostKind,
-                            const Instruction *I) {
+                            const Instruction *I) const {
     switch (Opcode) {
     default:
       break;
@@ -470,12 +486,11 @@ class TargetTransformInfoImplBase {
   }
 
   unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst,
-                                    VectorType *VecTy, unsigned Index) {
+                                    VectorType *VecTy, unsigned Index) const {
     return 1;
   }
 
-  unsigned getCFInstrCost(unsigned Opcode,
-                          TTI::TargetCostKind CostKind) {
+  unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind) const {
     // A phi would be free, unless we're costing the throughput because it
     // will require a register.
     if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
@@ -490,7 +505,8 @@ class TargetTransformInfoImplBase {
     return 1;
   }
 
-  unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
+  unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
+                              unsigned Index) const {
     return 1;
   }
 
@@ -502,26 +518,26 @@ class TargetTransformInfoImplBase {
 
   unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
                                  unsigned AddressSpace,
-                                 TTI::TargetCostKind CostKind) {
+                                 TTI::TargetCostKind CostKind) const {
     return 1;
   }
 
   unsigned getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
                                   const Value *Ptr, bool VariableMask,
                                   Align Alignment, TTI::TargetCostKind CostKind,
-                                  const Instruction *I = nullptr) {
+                                  const Instruction *I = nullptr) const {
     return 1;
   }
 
   unsigned getInterleavedMemoryOpCost(
       unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
       Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
-      bool UseMaskForCond, bool UseMaskForGaps) {
+      bool UseMaskForCond, bool UseMaskForGaps) const {
     return 1;
   }
 
   unsigned getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
-                                 TTI::TargetCostKind CostKind) {
+                                 TTI::TargetCostKind CostKind) const {
     switch (ICA.getID()) {
     default:
       break;
@@ -560,26 +576,32 @@ class TargetTransformInfoImplBase {
   }
 
   unsigned getCallInstrCost(Function *F, Type *RetTy, ArrayRef<Type *> Tys,
-                            TTI::TargetCostKind CostKind) {
+                            TTI::TargetCostKind CostKind) const {
     return 1;
   }
 
-  unsigned getNumberOfParts(Type *Tp) { return 0; }
+  unsigned getNumberOfParts(Type *Tp) const { return 0; }
 
   unsigned getAddressComputationCost(Type *Tp, ScalarEvolution *,
-                                     const SCEV *) {
+                                     const SCEV *) const {
     return 0;
   }
 
   unsigned getArithmeticReductionCost(unsigned, VectorType *, bool,
-                                      TTI::TargetCostKind) { return 1; }
+                                      TTI::TargetCostKind) const {
+    return 1;
+  }
 
   unsigned getMinMaxReductionCost(VectorType *, VectorType *, bool, bool,
-                                  TTI::TargetCostKind) { return 1; }
+                                  TTI::TargetCostKind) const {
+    return 1;
+  }
 
-  unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) { return 0; }
+  unsigned getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
+    return 0;
+  }
 
-  bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) {
+  bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const {
     return false;
   }
 
@@ -593,7 +615,7 @@ class TargetTransformInfoImplBase {
   }
 
   Value *getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst,
-                                           Type *ExpectedType) {
+                                           Type *ExpectedType) const {
     return nullptr;
   }
 
@@ -692,7 +714,7 @@ class TargetTransformInfoImplBase {
 protected:
   // Obtain the minimum required size to hold the value (without the sign)
   // In case of a vector it returns the min required size for one element.
-  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) {
+  unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
     if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
       const auto *VectorValue = cast<Constant>(Val);
 
@@ -746,12 +768,12 @@ class TargetTransformInfoImplBase {
     return Val->getType()->getScalarSizeInBits();
   }
 
-  bool isStridedAccess(const SCEV *Ptr) {
+  bool isStridedAccess(const SCEV *Ptr) const {
     return Ptr && isa<SCEVAddRecExpr>(Ptr);
   }
 
   const SCEVConstant *getConstantStrideStep(ScalarEvolution *SE,
-                                            const SCEV *Ptr) {
+                                            const SCEV *Ptr) const {
     if (!isStridedAccess(Ptr))
       return nullptr;
     const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
@@ -759,7 +781,7 @@ class TargetTransformInfoImplBase {
   }
 
   bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr,
-                                       int64_t MergeDistance) {
+                                       int64_t MergeDistance) const {
     const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
     if (!Step)
       return false;
diff --git a/llvm/include/llvm/CodeGen/Analysis.h b/llvm/include/llvm/CodeGen/Analysis.h
index fe610b5bdc8dc..bdfb416d9bd96 100644
--- a/llvm/include/llvm/CodeGen/Analysis.h
+++ b/llvm/include/llvm/CodeGen/Analysis.h
@@ -92,11 +92,6 @@ void computeValueLLTs(const DataLayout &DL, Type &Ty,
 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
 GlobalValue *ExtractTypeInfo(Value *V);
 
-/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
-/// processed uses a memory 'm' constraint.
-bool hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
-                               const TargetLowering &TLI);
-
 /// getFCmpCondCode - Return the ISD condition code corresponding to
 /// the given LLVM IR floating-point condition code.  This includes
 /// consideration of global floating-point math flags.
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
index 3357b0e1a6eb2..427906db66961 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
@@ -43,7 +43,7 @@ struct ConstantMatch {
   int64_t &CR;
   ConstantMatch(int64_t &C) : CR(C) {}
   bool match(const MachineRegisterInfo &MRI, Register Reg) {
-    if (auto MaybeCst = getConstantVRegVal(Reg, MRI)) {
+    if (auto MaybeCst = getConstantVRegSExtVal(Reg, MRI)) {
       CR = *MaybeCst;
       return true;
     }
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index 9fad903ea16b4..446aaf8c35512 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -121,14 +121,19 @@ void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
                         MachineOptimizationRemarkEmitter &MORE,
                         MachineOptimizationRemarkMissed &R);
 
+/// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
+Optional<APInt> getConstantVRegVal(Register VReg,
+                                   const MachineRegisterInfo &MRI);
+
 /// If \p VReg is defined by a G_CONSTANT fits in int64_t
 /// returns it.
-Optional<int64_t> getConstantVRegVal(Register VReg,
-                                     const MachineRegisterInfo &MRI);
+Optional<int64_t> getConstantVRegSExtVal(Register VReg,
+                                         const MachineRegisterInfo &MRI);
+
 /// Simple struct used to hold a constant integer value and a virtual
 /// register.
 struct ValueAndVReg {
-  int64_t Value;
+  APInt Value;
   Register VReg;
 };
 /// If \p VReg is defined by a statically evaluable chain of
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
index b31e9cdb0e903..115c501756043 100644
--- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -305,6 +305,9 @@ class MachineInstrBuilder {
       case MachineOperand::MO_BlockAddress:
         return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off,
                                TargetFlags);
+      case MachineOperand::MO_JumpTableIndex:
+        assert(off == 0 && "cannot create offset into jump tables");
+        return addJumpTableIndex(Disp.getIndex(), TargetFlags);
     }
   }
 
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
index 8a038752da0c5..50b186de2b051 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
@@ -388,10 +388,7 @@ namespace llvm {
 
   /// Returns an existing SUnit for this MI, or nullptr.
   inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
-    DenseMap<MachineInstr*, SUnit*>::const_iterator I = MISUnitMap.find(MI);
-    if (I == MISUnitMap.end())
-      return nullptr;
-    return I->second;
+    return MISUnitMap.lookup(MI);
   }
 
 } // end namespace llvm
diff --git a/llvm/include/llvm/CodeGen/VirtRegMap.h b/llvm/include/llvm/CodeGen/VirtRegMap.h
index 1775afb51bdf2..deef4b90279a0 100644
--- a/llvm/include/llvm/CodeGen/VirtRegMap.h
+++ b/llvm/include/llvm/CodeGen/VirtRegMap.h
@@ -151,7 +151,7 @@ class TargetInstrInfo;
     bool hasKnownPreference(Register VirtReg);
 
     /// records virtReg is a split live interval from SReg.
-    void setIsSplitFromReg(Register virtReg, unsigned SReg) {
+    void setIsSplitFromReg(Register virtReg, Register SReg) {
       Virt2SplitMap[virtReg.id()] = SReg;
       if (hasShape(SReg)) {
         Virt2ShapeMap[virtReg.id()] = getShape(SReg);
@@ -159,7 +159,7 @@ class TargetInstrInfo;
     }
 
     /// returns the live interval virtReg is split from.
-    unsigned getPreSplitReg(Register virtReg) const {
+    Register getPreSplitReg(Register virtReg) const {
       return Virt2SplitMap[virtReg.id()];
     }
 
@@ -167,8 +167,8 @@ class TargetInstrInfo;
     /// from through splitting.
     /// A register that was not created by splitting is its own original.
     /// This operation is idempotent.
-    unsigned getOriginal(unsigned VirtReg) const {
-      unsigned Orig = getPreSplitReg(VirtReg);
+    Register getOriginal(Register VirtReg) const {
+      Register Orig = getPreSplitReg(VirtReg);
       return Orig ? Orig : VirtReg;
     }
 
diff --git a/llvm/include/llvm/Frontend/OpenACC/ACC.td b/llvm/include/llvm/Frontend/OpenACC/ACC.td
index d5998845a8390..d53d3132c9694 100644
--- a/llvm/include/llvm/Frontend/OpenACC/ACC.td
+++ b/llvm/include/llvm/Frontend/OpenACC/ACC.td
@@ -80,8 +80,16 @@ def ACCC_Create : Clause<"create"> {
 }
 
 // 2.5.15
+def ACC_Default_none : ClauseVal<"none", 1, 0> { let isDefault = 1; }
+def ACC_Default_present : ClauseVal<"present", 0, 0> {}
+
 def ACCC_Default : Clause<"default"> {
   let flangClassValue = "AccDefaultClause";
+  let enumClauseValue = "DefaultValue";
+  let allowedClauseValues = [
+    ACC_Default_present,
+    ACC_Default_none
+  ];
 }
 
 // 2.14.3
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMP.td b/llvm/include/llvm/Frontend/OpenMP/OMP.td
index 58aa1bf23b685..fa67a64fa9970 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMP.td
+++ b/llvm/include/llvm/Frontend/OpenMP/OMP.td
@@ -62,7 +62,7 @@ def OMPC_Collapse : Clause<"collapse"> {
 }
 def OMPC_Default : Clause<"default"> {
   let clangClass = "OMPDefaultClause";
-  let flangClass = "OmpDefaultClause";
+  let flangClassValue = "OmpDefaultClause";
 }
 def OMPC_Private : Clause<"private"> {
   let clangClass = "OMPPrivateClause";
@@ -107,7 +107,7 @@ def OMP_PROC_BIND_default : ClauseVal<"default",5,0> {}
 def OMP_PROC_BIND_unknown : ClauseVal<"unknown",6,0> { let isDefault = true; }
 def OMPC_ProcBind : Clause<"proc_bind"> {
   let clangClass = "OMPProcBindClause";
-  let flangClass = "OmpProcBindClause";
+  let flangClassValue = "OmpProcBindClause";
   let enumClauseValue = "ProcBindKind";
   let allowedClauseValues = [
     OMP_PROC_BIND_master,
@@ -147,7 +147,6 @@ def OMPC_Ordered : Clause<"ordered"> {
 }
 def OMPC_NoWait : Clause<"nowait"> {
   let clangClass = "OMPNowaitClause";
-  let flangClass = "OmpNowait";
 }
 def OMPC_Untied : Clause<"untied"> { let clangClass = "OMPUntiedClause"; }
 def OMPC_Mergeable : Clause<"mergeable"> {
@@ -205,7 +204,6 @@ def OMPC_Hint : Clause<"hint"> {
 }
 def OMPC_DistSchedule : Clause<"dist_schedule"> {
   let clangClass = "OMPDistScheduleClause";
-  let flangClass = "OmpDistScheduleClause";
   let flangClassValue = "ScalarIntExpr";
   let isValueOptional = true;
 }
@@ -254,7 +252,7 @@ def OMPC_AtomicDefaultMemOrder : Clause<"atomic_default_mem_order"> {
 }
 def OMPC_Allocate : Clause<"allocate"> {
   let clangClass = "OMPAllocateClause";
-  let flangClass = "OmpAllocateClause";
+  let flangClassValue = "OmpAllocateClause";
 }
 def OMPC_NonTemporal : Clause<"nontemporal"> {
   let clangClass = "OMPNontemporalClause";
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index f71dc147416bb..aed498d80b026 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -1213,6 +1213,8 @@ def int_coro_free : Intrinsic<[llvm_ptr_ty], [llvm_token_ty, llvm_ptr_ty],
                                ReadOnly<ArgIndex<1>>,
                                NoCapture<ArgIndex<1>>]>;
 def int_coro_end : Intrinsic<[llvm_i1_ty], [llvm_ptr_ty, llvm_i1_ty], []>;
+def int_coro_end_async
+    : Intrinsic<[llvm_i1_ty], [llvm_ptr_ty, llvm_i1_ty, llvm_vararg_ty], []>;
 
 def int_coro_frame : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
 def int_coro_noop : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 055d6baa5b8d6..be11b518416c7 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -189,6 +189,12 @@ let TargetPrefix = "riscv" in {
                      LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
                     [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic;
+  // For destination vector type is the same as first and second source vector.
+  // Input: (vector_in, vector_in, vl)
+  class RISCVBinaryAAANoMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic;
   // For destination vector type is the same as first source vector.
   // Input: (vector_in, vector_in/scalar_in, vl)
   class RISCVBinaryAAXNoMask
@@ -254,6 +260,26 @@ let TargetPrefix = "riscv" in {
                     [IntrNoMem]>, RISCVVIntrinsic {
     let ExtendOperand = 2;
   }
+  // For binary operations with mask type output without mask.
+  // Output: (mask type output)
+  // Input: (vector_in, vector_in/scalar_in, vl)
+  class RISCVCompareNoMask
+        : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+                    [llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let ExtendOperand = 2;
+  }
+  // For binary operations with mask type output with mask.
+  // Output: (mask type output)
+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
+  class RISCVCompareMask
+        : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
+                    [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                     llvm_anyvector_ty, llvm_any_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let ExtendOperand = 3;
+  }
 
   // For Saturating binary operations.
   // The destination vector type is the same as first source vector.
@@ -294,14 +320,6 @@ let TargetPrefix = "riscv" in {
     let ExtendOperand = 3;
   }
 
-  // For vmv.v.v, vmv.v.x, vmv.v.i
-  // Input: (vector_in/scalar_in, vl)
-  class RISCVUnary : Intrinsic<[llvm_anyvector_ty],
-                               [llvm_any_ty, llvm_anyint_ty],
-                               [IntrNoMem] >, RISCVVIntrinsic {
-    let ExtendOperand = 1;
-  }
-
   class RISCVTernaryAAAXNoMask
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
@@ -312,6 +330,80 @@ let TargetPrefix = "riscv" in {
                     [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>],
                     [IntrNoMem]>, RISCVVIntrinsic;
+  class RISCVTernaryAAXANoMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
+                     llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let ExtendOperand = 2;
+  }
+  class RISCVTernaryAAXAMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let ExtendOperand = 2;
+  }
+  class RISCVTernaryWideNoMask
+        : Intrinsic< [llvm_anyvector_ty],
+                     [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
+                      llvm_anyint_ty],
+                     [IntrNoMem] >, RISCVVIntrinsic {
+    let ExtendOperand = 2;
+  }
+  class RISCVTernaryWideMask
+        : Intrinsic< [llvm_anyvector_ty],
+                     [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
+                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                     [IntrNoMem]>, RISCVVIntrinsic {
+    let ExtendOperand = 2;
+  }
+  // For Reduction ternary operations.
+  // For destination vector type is the same as first and third source vector.
+  // Input: (vector_in, vector_in, vector_in, vl)
+  class RISCVReductionNoMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>,
+                     llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic;
+  // For Reduction ternary operations with mask.
+  // For destination vector type is the same as first and third source vector.
+  // The mask type come from second source vector.
+  // Input: (maskedoff, vector_in, vector_in, vector_in, mask, vl)
+  class RISCVReductionMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>,
+                     LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic;
+  // For unary operations with scalar type output without mask
+  // Output: (scalar type)
+  // Input: (vector_in, vl)
+  class RISCVMaskUnarySOutNoMask
+        : Intrinsic<[llvm_anyint_ty],
+                    [llvm_anyvector_ty, LLVMMatchType<0>],
+                    [IntrNoMem]>, RISCVVIntrinsic;
+  // For unary operations with scalar type output with mask
+  // Output: (scalar type)
+  // Input: (vector_in, mask, vl)
+  class RISCVMaskUnarySOutMask
+        : Intrinsic<[llvm_anyint_ty],
+                    [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<0>],
+                    [IntrNoMem]>, RISCVVIntrinsic;
+  // For mask unary operations with mask type in/out without mask
+  // Output: (mask type output)
+  // Input: (mask type vector_in, vl)
+  class RISCVMaskUnaryMOutNoMask
+        : Intrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic;
+  // For mask unary operations with mask type in/out with mask
+  // Output: (mask type output)
+  // Input: (mask type maskedoff, mask type vector_in, mask, vl)
+  class RISCVMaskUnaryMOutMask
+        : Intrinsic<[llvm_anyint_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>,
+                     LLVMMatchType<0>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic;
 
   multiclass RISCVUSLoad {
     def "int_riscv_" # NAME : RISCVUSLoad;
@@ -333,14 +425,20 @@ let TargetPrefix = "riscv" in {
     def "int_riscv_" # NAME : RISCVSStore;
     def "int_riscv_" # NAME # "_mask" : RISCVSStoreMask;
   }
+
   multiclass RISCVIStore {
     def "int_riscv_" # NAME : RISCVIStore;
     def "int_riscv_" # NAME # "_mask" : RISCVIStoreMask;
   }
+
+  // AAX means the destination type(A) is the same as the first source
+  // type(A). X means any type for the second source operand.
   multiclass RISCVBinaryAAX {
     def "int_riscv_" # NAME : RISCVBinaryAAXNoMask;
     def "int_riscv_" # NAME # "_mask" : RISCVBinaryAAXMask;
   }
+  // ABX means the destination type(A) is different from the first source
+  // type(B). X means any type for the second source operand.
   multiclass RISCVBinaryABX {
     def "int_riscv_" # NAME : RISCVBinaryABXNoMask;
     def "int_riscv_" # NAME # "_mask" : RISCVBinaryABXMask;
@@ -366,8 +464,33 @@ let TargetPrefix = "riscv" in {
     def "int_riscv_" # NAME : RISCVTernaryAAAXNoMask;
     def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAAXMask;
   }
+  multiclass RISCVTernaryAAXA {
+    def "int_riscv_" # NAME : RISCVTernaryAAXANoMask;
+    def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAXAMask;
+  }
+  multiclass RISCVCompare {
+    def "int_riscv_" # NAME : RISCVCompareNoMask;
+    def "int_riscv_" # NAME # "_mask" : RISCVCompareMask;
+  }
+  multiclass RISCVTernaryWide {
+    def "int_riscv_" # NAME : RISCVTernaryWideNoMask;
+    def "int_riscv_" # NAME # "_mask" : RISCVTernaryWideMask;
+  }
+  multiclass RISCVReduction {
+    def "int_riscv_" # NAME : RISCVReductionNoMask;
+    def "int_riscv_" # NAME # "_mask" : RISCVReductionMask;
+  }
+  multiclass RISCVMaskUnarySOut {
+    def "int_riscv_" # NAME : RISCVMaskUnarySOutNoMask;
+    def "int_riscv_" # NAME # "_mask" : RISCVMaskUnarySOutMask;
+  }
+  multiclass RISCVMaskUnaryMOut {
+    def "int_riscv_" # NAME : RISCVMaskUnaryMOutNoMask;
+    def "int_riscv_" # NAME # "_mask" : RISCVMaskUnaryMOutMask;
+  }
 
   defm vle : RISCVUSLoad;
+  defm vleff : RISCVUSLoad;
   defm vse : RISCVUSStore;
   defm vlse: RISCVSLoad;
   defm vsse: RISCVSStore;
@@ -396,6 +519,10 @@ let TargetPrefix = "riscv" in {
   defm vmsbc_borrow_in : RISCVBinaryMaskOutWithV0;
   defm vmsbc : RISCVBinaryMaskOut;
 
+  defm vand : RISCVBinaryAAX;
+  defm vor : RISCVBinaryAAX;
+  defm vxor : RISCVBinaryAAX;
+
   defm vsll : RISCVBinaryAAX;
   defm vsrl : RISCVBinaryAAX;
   defm vsra : RISCVBinaryAAX;
@@ -403,6 +530,15 @@ let TargetPrefix = "riscv" in {
   defm vnsrl : RISCVBinaryABX;
   defm vnsra : RISCVBinaryABX;
 
+  defm vmseq : RISCVCompare;
+  defm vmsne : RISCVCompare;
+  defm vmsltu : RISCVCompare;
+  defm vmslt : RISCVCompare;
+  defm vmsleu : RISCVCompare;
+  defm vmsle : RISCVCompare;
+  defm vmsgtu : RISCVCompare;
+  defm vmsgt : RISCVCompare;
+
   defm vminu : RISCVBinaryAAX;
   defm vmin : RISCVBinaryAAX;
   defm vmaxu : RISCVBinaryAAX;
@@ -422,6 +558,16 @@ let TargetPrefix = "riscv" in {
   defm vwmulu : RISCVBinaryABX;
   defm vwmulsu : RISCVBinaryABX;
 
+  defm vmacc : RISCVTernaryAAXA;
+  defm vnmsac : RISCVTernaryAAXA;
+  defm vmadd : RISCVTernaryAAXA;
+  defm vnmsub : RISCVTernaryAAXA;
+
+  defm vwmaccu  : RISCVTernaryWide;
+  defm vwmacc   : RISCVTernaryWide;
+  defm vwmaccus : RISCVTernaryWide;
+  defm vwmaccsu : RISCVTernaryWide;
+
   defm vfadd : RISCVBinaryAAX;
   defm vfsub : RISCVBinaryAAX;
   defm vfrsub : RISCVBinaryAAX;
@@ -436,8 +582,19 @@ let TargetPrefix = "riscv" in {
   defm vssubu : RISCVSaturatingBinaryAAX;
   defm vssub : RISCVSaturatingBinaryAAX;
 
-  def int_riscv_vmv_v_v : RISCVUnary;
-  def int_riscv_vmv_v_x : RISCVUnary;
+  def int_riscv_vmerge : RISCVBinaryWithV0;
+
+  def int_riscv_vmv_v_v : Intrinsic<[llvm_anyvector_ty],
+                                    [LLVMMatchType<0>, llvm_anyint_ty],
+                                    [IntrNoMem]>, RISCVVIntrinsic;
+  def int_riscv_vmv_v_x : Intrinsic<[llvm_anyint_ty],
+                                    [LLVMVectorElementType<0>, llvm_anyint_ty],
+                                    [IntrNoMem]>, RISCVVIntrinsic {
+    let ExtendOperand = 1;
+  }
+  def int_riscv_vfmv_v_f : Intrinsic<[llvm_anyfloat_ty],
+                                     [LLVMVectorElementType<0>, llvm_anyint_ty],
+                                     [IntrNoMem]>, RISCVVIntrinsic;
 
   def int_riscv_vmv_x_s : Intrinsic<[LLVMVectorElementType<0>],
                                     [llvm_anyint_ty],
@@ -463,13 +620,39 @@ let TargetPrefix = "riscv" in {
 
   defm vfwmul : RISCVBinaryABX;
 
+  defm vfmacc : RISCVTernaryAAXA;
+  defm vfnmacc : RISCVTernaryAAXA;
+  defm vfmsac : RISCVTernaryAAXA;
+  defm vfnmsac : RISCVTernaryAAXA;
+  defm vfmadd : RISCVTernaryAAXA;
+  defm vfnmadd : RISCVTernaryAAXA;
+  defm vfmsub : RISCVTernaryAAXA;
+  defm vfnmsub : RISCVTernaryAAXA;
+
+  defm vfwmacc : RISCVTernaryWide;
+  defm vfwnmacc : RISCVTernaryWide;
+  defm vfwmsac : RISCVTernaryWide;
+  defm vfwnmsac : RISCVTernaryWide;
+
+  defm vfmin : RISCVBinaryAAX;
+  defm vfmax : RISCVBinaryAAX;
+
   defm vfsgnj : RISCVBinaryAAX;
   defm vfsgnjn : RISCVBinaryAAX;
   defm vfsgnjx : RISCVBinaryAAX;
 
+  defm vfmerge : RISCVBinaryWithV0;
+
   defm vslideup : RISCVTernaryAAAX;
   defm vslidedown : RISCVTernaryAAAX;
 
+  defm vslide1up : RISCVBinaryAAX;
+  defm vslide1down : RISCVBinaryAAX;
+  defm vfslide1up : RISCVBinaryAAX;
+  defm vfslide1down : RISCVBinaryAAX;
+
+  defm vrgather : RISCVBinaryAAX;
+
   defm vaaddu : RISCVSaturatingBinaryAAX;
   defm vaadd : RISCVSaturatingBinaryAAX;
   defm vasubu : RISCVSaturatingBinaryAAX;
@@ -482,4 +665,74 @@ let TargetPrefix = "riscv" in {
 
   defm vnclipu : RISCVSaturatingBinaryABX;
   defm vnclip : RISCVSaturatingBinaryABX;
+
+  defm vmfeq : RISCVCompare;
+  defm vmfne : RISCVCompare;
+  defm vmflt : RISCVCompare;
+  defm vmfle : RISCVCompare;
+  defm vmfgt : RISCVCompare;
+  defm vmfge : RISCVCompare;
+
+  defm vredsum : RISCVReduction;
+  defm vredand : RISCVReduction;
+  defm vredor : RISCVReduction;
+  defm vredxor : RISCVReduction;
+  defm vredminu : RISCVReduction;
+  defm vredmin : RISCVReduction;
+  defm vredmaxu : RISCVReduction;
+  defm vredmax : RISCVReduction;
+
+  defm vwredsumu : RISCVReduction;
+  defm vwredsum : RISCVReduction;
+
+  defm vfredosum : RISCVReduction;
+  defm vfredsum : RISCVReduction;
+  defm vfredmin : RISCVReduction;
+  defm vfredmax : RISCVReduction;
+
+  defm vfwredsum : RISCVReduction;
+  defm vfwredosum : RISCVReduction;
+
+  def int_riscv_vmand: RISCVBinaryAAANoMask;
+  def int_riscv_vmnand: RISCVBinaryAAANoMask;
+  def int_riscv_vmandnot: RISCVBinaryAAANoMask;
+  def int_riscv_vmxor: RISCVBinaryAAANoMask;
+  def int_riscv_vmor: RISCVBinaryAAANoMask;
+  def int_riscv_vmnor: RISCVBinaryAAANoMask;
+  def int_riscv_vmornot: RISCVBinaryAAANoMask;
+  def int_riscv_vmxnor: RISCVBinaryAAANoMask;
+
+  defm vpopc : RISCVMaskUnarySOut;
+  defm vfirst : RISCVMaskUnarySOut;
+  defm vmsbf : RISCVMaskUnaryMOut;
+  defm vmsof : RISCVMaskUnaryMOut;
+  defm vmsif : RISCVMaskUnaryMOut;
+
+  // Output: (vector)
+  // Input: (mask type input, vl)
+  def int_riscv_viota : Intrinsic<[llvm_anyvector_ty],
+                                  [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                                   llvm_anyint_ty],
+                                  [IntrNoMem]>, RISCVVIntrinsic;
+  // Output: (vector)
+  // Input: (maskedoff, mask type vector_in, mask, vl)
+  def int_riscv_viota_mask : Intrinsic<[llvm_anyvector_ty],
+                                       [LLVMMatchType<0>,
+                                        LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                                        LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                                        llvm_anyint_ty],
+                                       [IntrNoMem]>, RISCVVIntrinsic;
+  // Output: (vector)
+  // Input: (vl)
+  def int_riscv_vid : Intrinsic<[llvm_anyvector_ty],
+                                [llvm_anyint_ty],
+                                [IntrNoMem]>, RISCVVIntrinsic;
+  // Output: (vector)
+  // Input: (maskedoff, mask, vl)
+  def int_riscv_vid_mask : Intrinsic<[llvm_anyvector_ty],
+                                     [LLVMMatchType<0>,
+                                      LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                                      llvm_anyint_ty],
+                                     [IntrNoMem]>, RISCVVIntrinsic;
+
 } // TargetPrefix = "riscv"
diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h
index c25573b9f8a65..166ad23de969f 100644
--- a/llvm/include/llvm/IR/PatternMatch.h
+++ b/llvm/include/llvm/IR/PatternMatch.h
@@ -88,11 +88,6 @@ inline class_match<BinaryOperator> m_BinOp() {
 /// Matches any compare instruction and ignore it.
 inline class_match<CmpInst> m_Cmp() { return class_match<CmpInst>(); }
 
-/// Match an arbitrary ConstantInt and ignore it.
-inline class_match<ConstantInt> m_ConstantInt() {
-  return class_match<ConstantInt>();
-}
-
 /// Match an arbitrary undef constant.
 inline class_match<UndefValue> m_Undef() { return class_match<UndefValue>(); }
 
@@ -102,6 +97,21 @@ inline class_match<PoisonValue> m_Poison() { return class_match<PoisonValue>();
 /// Match an arbitrary Constant and ignore it.
 inline class_match<Constant> m_Constant() { return class_match<Constant>(); }
 
+/// Match an arbitrary ConstantInt and ignore it.
+inline class_match<ConstantInt> m_ConstantInt() {
+  return class_match<ConstantInt>();
+}
+
+/// Match an arbitrary ConstantFP and ignore it.
+inline class_match<ConstantFP> m_ConstantFP() {
+  return class_match<ConstantFP>();
+}
+
+/// Match an arbitrary ConstantExpr and ignore it.
+inline class_match<ConstantExpr> m_ConstantExpr() {
+  return class_match<ConstantExpr>();
+}
+
 /// Match an arbitrary basic block value and ignore it.
 inline class_match<BasicBlock> m_BasicBlock() {
   return class_match<BasicBlock>();
@@ -699,21 +709,38 @@ inline bind_ty<BinaryOperator> m_BinOp(BinaryOperator *&I) { return I; }
 /// Match a with overflow intrinsic, capturing it if we match.
 inline bind_ty<WithOverflowInst> m_WithOverflowInst(WithOverflowInst *&I) { return I; }
 
-/// Match a ConstantInt, capturing the value if we match.
-inline bind_ty<ConstantInt> m_ConstantInt(ConstantInt *&CI) { return CI; }
-
 /// Match a Constant, capturing the value if we match.
 inline bind_ty<Constant> m_Constant(Constant *&C) { return C; }
 
+/// Match a ConstantInt, capturing the value if we match.
+inline bind_ty<ConstantInt> m_ConstantInt(ConstantInt *&CI) { return CI; }
+
 /// Match a ConstantFP, capturing the value if we match.
 inline bind_ty<ConstantFP> m_ConstantFP(ConstantFP *&C) { return C; }
 
+/// Match a ConstantExpr, capturing the value if we match.
+inline bind_ty<ConstantExpr> m_ConstantExpr(ConstantExpr *&C) { return C; }
+
 /// Match a basic block value, capturing it if we match.
 inline bind_ty<BasicBlock> m_BasicBlock(BasicBlock *&V) { return V; }
 inline bind_ty<const BasicBlock> m_BasicBlock(const BasicBlock *&V) {
   return V;
 }
 
+/// Match an arbitrary immediate Constant and ignore it.
+inline match_combine_and<class_match<Constant>,
+                         match_unless<class_match<ConstantExpr>>>
+m_ImmConstant() {
+  return m_CombineAnd(m_Constant(), m_Unless(m_ConstantExpr()));
+}
+
+/// Match an immediate Constant, capturing the value if we match.
+inline match_combine_and<bind_ty<Constant>,
+                         match_unless<class_match<ConstantExpr>>>
+m_ImmConstant(Constant *&C) {
+  return m_CombineAnd(m_Constant(C), m_Unless(m_ConstantExpr()));
+}
+
 /// Match a specified Value*.
 struct specificval_ty {
   const Value *Val;
@@ -2360,6 +2387,58 @@ inline VScaleVal_match m_VScale(const DataLayout &DL) {
   return VScaleVal_match(DL);
 }
 
+template <typename LHS, typename RHS, unsigned Opcode>
+struct LogicalOp_match {
+  LHS L;
+  RHS R;
+
+  LogicalOp_match(const LHS &L, const RHS &R) : L(L), R(R) {}
+
+  template <typename T> bool match(T *V) {
+    if (auto *I = dyn_cast<Instruction>(V)) {
+      if (!I->getType()->isIntOrIntVectorTy(1))
+        return false;
+
+      if (I->getOpcode() == Opcode && L.match(I->getOperand(0)) &&
+          R.match(I->getOperand(1)))
+        return true;
+
+      if (auto *SI = dyn_cast<SelectInst>(I)) {
+        if (Opcode == Instruction::And) {
+          if (const auto *C = dyn_cast<Constant>(SI->getFalseValue()))
+            if (C->isNullValue() && L.match(SI->getCondition()) &&
+                R.match(SI->getTrueValue()))
+              return true;
+        } else {
+          assert(Opcode == Instruction::Or);
+          if (const auto *C = dyn_cast<Constant>(SI->getTrueValue()))
+            if (C->isOneValue() && L.match(SI->getCondition()) &&
+                R.match(SI->getFalseValue()))
+              return true;
+        }
+      }
+    }
+
+    return false;
+  }
+};
+
+/// Matches L && R either in the form of L & R or L ? R : false.
+/// Note that the latter form is poison-blocking.
+template <typename LHS, typename RHS>
+inline LogicalOp_match<LHS, RHS, Instruction::And>
+m_LogicalAnd(const LHS &L, const RHS &R) {
+  return LogicalOp_match<LHS, RHS, Instruction::And>(L, R);
+}
+
+/// Matches L || R either in the form of L | R or L ? true : R.
+/// Note that the latter form is poison-blocking.
+template <typename LHS, typename RHS>
+inline LogicalOp_match<LHS, RHS, Instruction::Or>
+m_LogicalOr(const LHS &L, const RHS &R) {
+  return LogicalOp_match<LHS, RHS, Instruction::Or>(L, R);
+}
+
 } // end namespace PatternMatch
 } // end namespace llvm
 
diff --git a/llvm/include/llvm/IR/SymbolTableListTraits.h b/llvm/include/llvm/IR/SymbolTableListTraits.h
index 5b793e5dbf283..8af712374bfaf 100644
--- a/llvm/include/llvm/IR/SymbolTableListTraits.h
+++ b/llvm/include/llvm/IR/SymbolTableListTraits.h
@@ -76,9 +76,11 @@ class SymbolTableListTraits : public ilist_alloc_traits<ValueSubClass> {
   /// getListOwner - Return the object that owns this list.  If this is a list
   /// of instructions, it returns the BasicBlock that owns them.
   ItemParentClass *getListOwner() {
-    size_t Offset(size_t(&((ItemParentClass*)nullptr->*ItemParentClass::
-                           getSublistAccess(static_cast<ValueSubClass*>(nullptr)))));
-    ListTy *Anchor(static_cast<ListTy *>(this));
+    size_t Offset = reinterpret_cast<size_t>(
+        &((ItemParentClass *)nullptr->*ItemParentClass::getSublistAccess(
+                                           static_cast<ValueSubClass *>(
+                                               nullptr))));
+    ListTy *Anchor = static_cast<ListTy *>(this);
     return reinterpret_cast<ItemParentClass*>(reinterpret_cast<char*>(Anchor)-
                                               Offset);
   }
diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def
index 3073866da4c97..981548c6dde93 100644
--- a/llvm/include/llvm/IR/VPIntrinsics.def
+++ b/llvm/include/llvm/IR/VPIntrinsics.def
@@ -131,7 +131,7 @@ HELPER_REGISTER_BINARY_INT_VP(vp_shl, VP_SHL, Shl)
 HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem)
 
 // llvm.vp.sub(x,y,mask,vlen)
-HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_Sub, Sub)
+HELPER_REGISTER_BINARY_INT_VP(vp_sub, VP_SUB, Sub)
 
 // llvm.vp.udiv(x,y,mask,vlen)
 HELPER_REGISTER_BINARY_INT_VP(vp_udiv, VP_UDIV, UDiv)
diff --git a/llvm/include/llvm/MC/MCContext.h b/llvm/include/llvm/MC/MCContext.h
index 75e6dbe069e22..49ab0ce8d6fd0 100644
--- a/llvm/include/llvm/MC/MCContext.h
+++ b/llvm/include/llvm/MC/MCContext.h
@@ -397,12 +397,16 @@ namespace llvm {
     /// unspecified name.
     MCSymbol *createLinkerPrivateTempSymbol();
 
-    /// Create and return a new assembler temporary symbol with a unique but
-    /// unspecified name.
-    MCSymbol *createTempSymbol(bool CanBeUnnamed = true);
-
-    MCSymbol *createTempSymbol(const Twine &Name, bool AlwaysAddSuffix,
-                               bool CanBeUnnamed = true);
+    /// Create a temporary symbol with a unique name. The name will be omitted
+    /// in the symbol table if UseNamesOnTempLabels is false (default except
+    /// MCAsmStreamer). The overload without Name uses an unspecified name.
+    MCSymbol *createTempSymbol();
+    MCSymbol *createTempSymbol(const Twine &Name, bool AlwaysAddSuffix = true);
+
+    /// Create a temporary symbol with a unique name whose name cannot be
+    /// omitted in the symbol table. This is rarely used.
+    MCSymbol *createNamedTempSymbol();
+    MCSymbol *createNamedTempSymbol(const Twine &Name);
 
     /// Create the definition of a directional local symbol for numbered label
     /// (used for "1:" definitions).
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 17454e3134a2f..cbb061fc64569 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -27,12 +27,22 @@ class MCInst;
 //===----------------------------------------------------------------------===//
 
 namespace MCOI {
-// Operand constraints
+/// Operand constraints. These are encoded in 16 bits with one of the
+/// low-order 3 bits specifying that a constraint is present and the
+/// corresponding high-order hex digit specifying the constraint value.
+/// This allows for a maximum of 3 constraints.
 enum OperandConstraint {
-  TIED_TO = 0,  // Must be allocated the same register as.
-  EARLY_CLOBBER // Operand is an early clobber register operand
+  TIED_TO = 0,  // Must be allocated the same register as specified value.
+  EARLY_CLOBBER // If present, operand is an early clobber register.
 };
 
+// Define a macro to produce each constraint value.
+#define MCOI_TIED_TO(op) \
+  ((1 << MCOI::TIED_TO) | ((op) << (4 + MCOI::TIED_TO * 4)))
+
+#define MCOI_EARLY_CLOBBER \
+  (1 << MCOI::EARLY_CLOBBER)
+
 /// These are flags set on operands, but should be considered
 /// private, all access should go through the MCOperandInfo accessors.
 /// See the accessors for a description of what these are.
@@ -84,10 +94,9 @@ class MCOperandInfo {
 
   /// Information about the type of the operand.
   uint8_t OperandType;
-  /// The lower 16 bits are used to specify which constraints are set.
-  /// The higher 16 bits are used to specify the value of constraints (4 bits
-  /// each).
-  uint32_t Constraints;
+
+  /// Operand constraints (see OperandConstraint enum).
+  uint16_t Constraints;
 
   /// Set if this operand is a pointer value and it requires a callback
   /// to look up its register class.
@@ -197,14 +206,14 @@ class MCInstrDesc {
   const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr
   const MCOperandInfo *OpInfo;   // 'NumOperands' entries about operands
 
-  /// Returns the value of the specific constraint if
-  /// it is set. Returns -1 if it is not set.
+  /// Returns the value of the specified operand constraint if
+  /// it is present. Returns -1 if it is not present.
   int getOperandConstraint(unsigned OpNum,
                            MCOI::OperandConstraint Constraint) const {
     if (OpNum < NumOperands &&
         (OpInfo[OpNum].Constraints & (1 << Constraint))) {
-      unsigned Pos = 16 + Constraint * 4;
-      return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
+      unsigned ValuePos = 4 + Constraint * 4;
+      return (int)(OpInfo[OpNum].Constraints >> ValuePos) & 0x0f;
     }
     return -1;
   }
diff --git a/llvm/include/llvm/Object/Binary.h b/llvm/include/llvm/Object/Binary.h
index e12e512d68b8f..dd98e1143e259 100644
--- a/llvm/include/llvm/Object/Binary.h
+++ b/llvm/include/llvm/Object/Binary.h
@@ -165,8 +165,8 @@ class Binary {
   static Error checkOffset(MemoryBufferRef M, uintptr_t Addr,
                            const uint64_t Size) {
     if (Addr + Size < Addr || Addr + Size < Size ||
-        Addr + Size > uintptr_t(M.getBufferEnd()) ||
-        Addr < uintptr_t(M.getBufferStart())) {
+        Addr + Size > reinterpret_cast<uintptr_t>(M.getBufferEnd()) ||
+        Addr < reinterpret_cast<uintptr_t>(M.getBufferStart())) {
       return errorCodeToError(object_error::unexpected_eof);
     }
     return Error::success();
diff --git a/llvm/include/llvm/Object/ELF.h b/llvm/include/llvm/Object/ELF.h
index a5233bd3ac100..bd224ada77839 100644
--- a/llvm/include/llvm/Object/ELF.h
+++ b/llvm/include/llvm/Object/ELF.h
@@ -90,32 +90,6 @@ template <class ELFT>
 class ELFFile {
 public:
   LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
-  using uintX_t = typename ELFT::uint;
-  using Elf_Ehdr = typename ELFT::Ehdr;
-  using Elf_Shdr = typename ELFT::Shdr;
-  using Elf_Sym = typename ELFT::Sym;
-  using Elf_Dyn = typename ELFT::Dyn;
-  using Elf_Phdr = typename ELFT::Phdr;
-  using Elf_Rel = typename ELFT::Rel;
-  using Elf_Rela = typename ELFT::Rela;
-  using Elf_Relr = typename ELFT::Relr;
-  using Elf_Verdef = typename ELFT::Verdef;
-  using Elf_Verdaux = typename ELFT::Verdaux;
-  using Elf_Verneed = typename ELFT::Verneed;
-  using Elf_Vernaux = typename ELFT::Vernaux;
-  using Elf_Versym = typename ELFT::Versym;
-  using Elf_Hash = typename ELFT::Hash;
-  using Elf_GnuHash = typename ELFT::GnuHash;
-  using Elf_Nhdr = typename ELFT::Nhdr;
-  using Elf_Note = typename ELFT::Note;
-  using Elf_Note_Iterator = typename ELFT::NoteIterator;
-  using Elf_Dyn_Range = typename ELFT::DynRange;
-  using Elf_Shdr_Range = typename ELFT::ShdrRange;
-  using Elf_Sym_Range = typename ELFT::SymRange;
-  using Elf_Rel_Range = typename ELFT::RelRange;
-  using Elf_Rela_Range = typename ELFT::RelaRange;
-  using Elf_Relr_Range = typename ELFT::RelrRange;
-  using Elf_Phdr_Range = typename ELFT::PhdrRange;
 
   // This is a callback that can be passed to a number of functions.
   // It can be used to ignore non-critical errors (warnings), which is
diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h
index ca4363572d90c..33b4c28db951e 100644
--- a/llvm/include/llvm/Object/ELFObjectFile.h
+++ b/llvm/include/llvm/Object/ELFObjectFile.h
@@ -233,15 +233,6 @@ template <class ELFT> class ELFObjectFile : public ELFObjectFileBase {
 public:
   LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
 
-  using uintX_t = typename ELFT::uint;
-
-  using Elf_Sym = typename ELFT::Sym;
-  using Elf_Shdr = typename ELFT::Shdr;
-  using Elf_Ehdr = typename ELFT::Ehdr;
-  using Elf_Rel = typename ELFT::Rel;
-  using Elf_Rela = typename ELFT::Rela;
-  using Elf_Dyn = typename ELFT::Dyn;
-
   SectionRef toSectionRef(const Elf_Shdr *Sec) const {
     return SectionRef(toDRI(Sec), this);
   }
diff --git a/llvm/include/llvm/Object/ELFTypes.h b/llvm/include/llvm/Object/ELFTypes.h
index 5e85e6cc4653a..f64e7c06e03b6 100644
--- a/llvm/include/llvm/Object/ELFTypes.h
+++ b/llvm/include/llvm/Object/ELFTypes.h
@@ -107,7 +107,34 @@ using ELF64BE = ELFType<support::big, true>;
   using Elf_Word = typename ELFT::Word;                                        \
   using Elf_Sword = typename ELFT::Sword;                                      \
   using Elf_Xword = typename ELFT::Xword;                                      \
-  using Elf_Sxword = typename ELFT::Sxword;
+  using Elf_Sxword = typename ELFT::Sxword;                                    \
+  using uintX_t = typename ELFT::uint;                                         \
+  using Elf_Ehdr = typename ELFT::Ehdr;                                        \
+  using Elf_Shdr = typename ELFT::Shdr;                                        \
+  using Elf_Sym = typename ELFT::Sym;                                          \
+  using Elf_Dyn = typename ELFT::Dyn;                                          \
+  using Elf_Phdr = typename ELFT::Phdr;                                        \
+  using Elf_Rel = typename ELFT::Rel;                                          \
+  using Elf_Rela = typename ELFT::Rela;                                        \
+  using Elf_Relr = typename ELFT::Relr;                                        \
+  using Elf_Verdef = typename ELFT::Verdef;                                    \
+  using Elf_Verdaux = typename ELFT::Verdaux;                                  \
+  using Elf_Verneed = typename ELFT::Verneed;                                  \
+  using Elf_Vernaux = typename ELFT::Vernaux;                                  \
+  using Elf_Versym = typename ELFT::Versym;                                    \
+  using Elf_Hash = typename ELFT::Hash;                                        \
+  using Elf_GnuHash = typename ELFT::GnuHash;                                  \
+  using Elf_Nhdr = typename ELFT::Nhdr;                                        \
+  using Elf_Note = typename ELFT::Note;                                        \
+  using Elf_Note_Iterator = typename ELFT::NoteIterator;                       \
+  using Elf_CGProfile = typename ELFT::CGProfile;                              \
+  using Elf_Dyn_Range = typename ELFT::DynRange;                               \
+  using Elf_Shdr_Range = typename ELFT::ShdrRange;                             \
+  using Elf_Sym_Range = typename ELFT::SymRange;                               \
+  using Elf_Rel_Range = typename ELFT::RelRange;                               \
+  using Elf_Rela_Range = typename ELFT::RelaRange;                             \
+  using Elf_Relr_Range = typename ELFT::RelrRange;                             \
+  using Elf_Phdr_Range = typename ELFT::PhdrRange;                             \
 
 #define LLVM_ELF_COMMA ,
 #define LLVM_ELF_IMPORT_TYPES(E, W)                                            \
@@ -269,7 +296,6 @@ struct Elf_Versym_Impl {
 template <class ELFT>
 struct Elf_Verdef_Impl {
   LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
-  using Elf_Verdaux = Elf_Verdaux_Impl<ELFT>;
   Elf_Half vd_version; // Version of this structure (e.g. VER_DEF_CURRENT)
   Elf_Half vd_flags;   // Bitwise flags (VER_DEF_*)
   Elf_Half vd_ndx;     // Version index, used in .gnu.version entries
diff --git a/llvm/include/llvm/Option/OptParser.td b/llvm/include/llvm/Option/OptParser.td
index d7d4e03b15f07..e96e541315695 100644
--- a/llvm/include/llvm/Option/OptParser.td
+++ b/llvm/include/llvm/Option/OptParser.td
@@ -173,12 +173,6 @@ class MarshallingInfoFlag<code keypath, code defaultvalue = "false">
   code Denormalizer = "denormalizeSimpleFlag";
 }
 
-class MarshallingInfoNegativeFlag<code keypath, code defaultvalue = "true">
-  : MarshallingInfo<keypath, defaultvalue> {
-  code Normalizer = "normalizeSimpleNegativeFlag";
-  code Denormalizer = "denormalizeSimpleFlag";
-}
-
 class MarshallingInfoBitfieldFlag<code keypath, code value>
   : MarshallingInfoFlag<keypath, "0u"> {
   code Normalizer = "makeFlagToValueNormalizer("#value#")";
@@ -196,6 +190,9 @@ class MarshallingInfoBooleanFlag<code keypath, code defaultvalue, code value, co
 
 // Mixins for additional marshalling attributes.
 
+class IsNegative {
+  code Normalizer = "normalizeSimpleNegativeFlag";
+}
 class AlwaysEmit { bit ShouldAlwaysEmit = true; }
 class Normalizer<code normalizer> { code Normalizer = normalizer; }
 class Denormalizer<code denormalizer> { code Denormalizer = denormalizer; }
@@ -205,6 +202,9 @@ class AutoNormalizeEnum {
   code Normalizer = "normalizeSimpleEnum";
   code Denormalizer = "denormalizeSimpleEnum";
 }
+class AutoNormalizeEnumJoined : AutoNormalizeEnum {
+  code Denormalizer = "denormalizeSimpleEnumJoined";
+}
 class ValueMerger<code merger> { code ValueMerger = merger; }
 class ValueExtractor<code extractor> { code ValueExtractor = extractor; }
 
diff --git a/llvm/include/llvm/Passes/PassBuilder.h b/llvm/include/llvm/Passes/PassBuilder.h
index e2d22031dd5ec..5a13df5b0c860 100644
--- a/llvm/include/llvm/Passes/PassBuilder.h
+++ b/llvm/include/llvm/Passes/PassBuilder.h
@@ -460,6 +460,9 @@ class PassBuilder {
 
   /// Build the default `AAManager` with the default alias analysis pipeline
   /// registered.
+  ///
+  /// This also adds target-specific alias analyses registered via
+  /// TargetMachine::registerAliasAnalyses().
   AAManager buildDefaultAAPipeline();
 
   /// Parse a textual pass pipeline description into a \c
diff --git a/llvm/include/llvm/Support/KnownBits.h b/llvm/include/llvm/Support/KnownBits.h
index f55839a35c136..ec88b9807174a 100644
--- a/llvm/include/llvm/Support/KnownBits.h
+++ b/llvm/include/llvm/Support/KnownBits.h
@@ -113,18 +113,38 @@ struct KnownBits {
     Zero.setSignBit();
   }
 
-  /// Return the minimal value possible given these KnownBits.
+  /// Return the minimal unsigned value possible given these KnownBits.
   APInt getMinValue() const {
     // Assume that all bits that aren't known-ones are zeros.
     return One;
   }
 
-  /// Return the maximal value possible given these KnownBits.
+  /// Return the minimal signed value possible given these KnownBits.
+  APInt getSignedMinValue() const {
+    // Assume that all bits that aren't known-ones are zeros.
+    APInt Min = One;
+    // Sign bit is unknown.
+    if (Zero.isSignBitClear() && One.isSignBitClear())
+      Min.setSignBit();
+    return Min;
+  }
+
+  /// Return the maximal unsigned value possible given these KnownBits.
   APInt getMaxValue() const {
     // Assume that all bits that aren't known-zeros are ones.
     return ~Zero;
   }
 
+  /// Return the maximal signed value possible given these KnownBits.
+  APInt getSignedMaxValue() const {
+    // Assume that all bits that aren't known-zeros are ones.
+    APInt Max = ~Zero;
+    // Sign bit is unknown.
+    if (Zero.isSignBitClear() && One.isSignBitClear())
+      Max.clearSignBit();
+    return Max;
+  }
+
   /// Return known bits for a truncation of the value we're tracking.
   KnownBits trunc(unsigned BitWidth) const {
     return KnownBits(Zero.trunc(BitWidth), One.trunc(BitWidth));
diff --git a/llvm/include/llvm/TableGen/Record.h b/llvm/include/llvm/TableGen/Record.h
index 3010b4dad09a8..a0c5b2778547d 100644
--- a/llvm/include/llvm/TableGen/Record.h
+++ b/llvm/include/llvm/TableGen/Record.h
@@ -829,7 +829,7 @@ class BinOpInit : public OpInit, public FoldingSetNode {
 /// !op (X, Y, Z) - Combine two inits.
 class TernOpInit : public OpInit, public FoldingSetNode {
 public:
-  enum TernaryOp : uint8_t { SUBST, FOREACH, FILTER, IF, DAG };
+  enum TernaryOp : uint8_t { SUBST, FOREACH, FILTER, IF, DAG, SUBSTR };
 
 private:
   Init *LHS, *MHS, *RHS;
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index d4fc2d8f0887d..55b35d9c0d075 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -23,6 +23,7 @@
 
 namespace llvm {
 
+class AAManager;
 class Function;
 class GlobalValue;
 class MachineModuleInfoWrapperPass;
@@ -322,6 +323,10 @@ class TargetMachine {
   virtual void registerPassBuilderCallbacks(PassBuilder &,
                                             bool DebugPassManager) {}
 
+  /// Allow the target to register alias analyses with the AAManager for use
+  /// with the new pass manager. Only affects the "default" AAManager.
+  virtual void registerAliasAnalyses(AAManager &) {}
+
   /// Add passes to the specified pass manager to get the specified file
   /// emitted.  Typically this will involve several steps of code generation.
   /// This method should return true if emission of this file type is not
diff --git a/llvm/include/llvm/Transforms/IPO/IROutliner.h b/llvm/include/llvm/Transforms/IPO/IROutliner.h
index 01f870097972b..87f276d82df7b 100644
--- a/llvm/include/llvm/Transforms/IPO/IROutliner.h
+++ b/llvm/include/llvm/Transforms/IPO/IROutliner.h
@@ -81,6 +81,12 @@ struct OutlinableRegion {
   DenseMap<unsigned, unsigned> ExtractedArgToAgg;
   DenseMap<unsigned, unsigned> AggArgToExtracted;
 
+  /// Mapping of the argument number in the deduplicated function
+  /// to a given constant, which is used when creating the arguments to the call
+  /// to the newly created deduplicated function.  This is handled separately
+  /// since the CodeExtractor does not recognize constants.
+  DenseMap<unsigned, Constant *> AggArgToConstant;
+
   /// Used to create an outlined function.
   CodeExtractor *CE = nullptr;
 
@@ -180,8 +186,11 @@ class IROutliner {
   /// function if needed.
   ///
   /// \param [in] M - The module to outline from.
-  /// \param [in,out] Region - The region to be extracted
-  void findAddInputsOutputs(Module &M, OutlinableRegion &Region);
+  /// \param [in,out] Region - The region to be extracted.
+  /// \param [in] NotSame - The global value numbers of the Values in the region
+  /// that do not have the same Constant in each strucutrally similar region.
+  void findAddInputsOutputs(Module &M, OutlinableRegion &Region,
+                            DenseSet<unsigned> &NotSame);
 
   /// Extract \p Region into its own function.
   ///
diff --git a/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h b/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
index a0bef89b36cf3..2a342fcda3c2e 100644
--- a/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
+++ b/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
@@ -53,6 +53,16 @@ namespace llvm {
 // Forward declarations of an update tracking API used in the pass manager.
 class LPMUpdater;
 
+namespace {
+
+template <typename PassT>
+using HasRunOnLoopT = decltype(std::declval<PassT>().run(
+    std::declval<Loop &>(), std::declval<LoopAnalysisManager &>(),
+    std::declval<LoopStandardAnalysisResults &>(),
+    std::declval<LPMUpdater &>()));
+
+} // namespace
+
 // Explicit specialization and instantiation declarations for the pass manager.
 // See the comments on the definition of the specialization for details on how
 // it differs from the primary template.
@@ -62,13 +72,6 @@ class PassManager<Loop, LoopAnalysisManager, LoopStandardAnalysisResults &,
     : public PassInfoMixin<
           PassManager<Loop, LoopAnalysisManager, LoopStandardAnalysisResults &,
                       LPMUpdater &>> {
-private:
-  template <typename PassT>
-  using HasRunOnLoopT = decltype(std::declval<PassT>().run(
-      std::declval<Loop &>(), std::declval<LoopAnalysisManager &>(),
-      std::declval<LoopStandardAnalysisResults &>(),
-      std::declval<LPMUpdater &>()));
-
 public:
   /// Construct a pass manager.
   ///
@@ -154,6 +157,9 @@ class PassManager<Loop, LoopAnalysisManager, LoopStandardAnalysisResults &,
 
   static bool isRequired() { return true; }
 
+  size_t getNumLoopPasses() const { return LoopPasses.size(); }
+  size_t getNumLoopNestPasses() const { return LoopNestPasses.size(); }
+
 protected:
   using LoopPassConceptT =
       detail::PassConcept<Loop, LoopAnalysisManager,
@@ -227,6 +233,13 @@ class FunctionToLoopPassAdaptor;
 /// A reference to an instance of this class is passed as an argument to each
 /// Loop pass, and Loop passes should use it to update LPM infrastructure if
 /// they modify the loop nest structure.
+///
+/// \c LPMUpdater comes with two modes: the loop mode and the loop-nest mode. In
+/// loop mode, all the loops in the function will be pushed into the worklist
+/// and when new loops are added to the pipeline, their subloops are also
+/// inserted recursively. On the other hand, in loop-nest mode, only top-level
+/// loops are contained in the worklist and the addition of new (top-level)
+/// loops will not trigger the addition of their subloops.
 class LPMUpdater {
 public:
   /// This can be queried by loop passes which run other loop passes (like pass
@@ -248,6 +261,8 @@ class LPMUpdater {
   /// state, this routine will mark that the current loop should be skipped by
   /// the rest of the pass management infrastructure.
   void markLoopAsDeleted(Loop &L, llvm::StringRef Name) {
+    assert((!LoopNestMode || L.isOutermost()) &&
+           "L should be a top-level loop in loop-nest mode.");
     LAM.clear(L, Name);
     assert((&L == CurrentL || CurrentL->contains(&L)) &&
            "Cannot delete a loop outside of the "
@@ -263,6 +278,8 @@ class LPMUpdater {
   /// loops within them will be visited in postorder as usual for the loop pass
   /// manager.
   void addChildLoops(ArrayRef<Loop *> NewChildLoops) {
+    assert(!LoopNestMode &&
+           "Child loops should not be pushed in loop-nest mode.");
     // Insert ourselves back into the worklist first, as this loop should be
     // revisited after all the children have been processed.
     Worklist.insert(CurrentL);
@@ -294,7 +311,10 @@ class LPMUpdater {
              "All of the new loops must be siblings of the current loop!");
 #endif
 
-    appendLoopsToWorklist(NewSibLoops, Worklist);
+    if (LoopNestMode)
+      Worklist.insert(NewSibLoops);
+    else
+      appendLoopsToWorklist(NewSibLoops, Worklist);
 
     // No need to skip the current loop or revisit it, as sibling loops
     // shouldn't impact anything.
@@ -324,6 +344,7 @@ class LPMUpdater {
 
   Loop *CurrentL;
   bool SkipCurrentLoop;
+  const bool LoopNestMode;
 
 #ifndef NDEBUG
   // In debug builds we also track the parent loop to implement asserts even in
@@ -332,8 +353,8 @@ class LPMUpdater {
 #endif
 
   LPMUpdater(SmallPriorityWorklist<Loop *, 4> &Worklist,
-             LoopAnalysisManager &LAM)
-      : Worklist(Worklist), LAM(LAM) {}
+             LoopAnalysisManager &LAM, bool LoopNestMode = false)
+      : Worklist(Worklist), LAM(LAM), LoopNestMode(LoopNestMode) {}
 };
 
 template <typename IRUnitT, typename PassT>
@@ -366,6 +387,15 @@ Optional<PreservedAnalyses> LoopPassManager::runSinglePass(
 /// FunctionAnalysisManager it will run the \c LoopAnalysisManagerFunctionProxy
 /// analysis prior to running the loop passes over the function to enable a \c
 /// LoopAnalysisManager to be used within this run safely.
+///
+/// The adaptor comes with two modes: the loop mode and the loop-nest mode, and
+/// the worklist updater lived inside will be in the same mode as the adaptor
+/// (refer to the documentation of \c LPMUpdater for more detailed explanation).
+/// Specifically, in loop mode, all loops in the funciton will be pushed into
+/// the worklist and processed by \p Pass, while only top-level loops are
+/// processed in loop-nest mode. Please refer to the various specializations of
+/// \fn createLoopFunctionToLoopPassAdaptor to see when loop mode and loop-nest
+/// mode are used.
 class FunctionToLoopPassAdaptor
     : public PassInfoMixin<FunctionToLoopPassAdaptor> {
 public:
@@ -376,10 +406,12 @@ class FunctionToLoopPassAdaptor
   explicit FunctionToLoopPassAdaptor(std::unique_ptr<PassConceptT> Pass,
                                      bool UseMemorySSA = false,
                                      bool UseBlockFrequencyInfo = false,
-                                     bool DebugLogging = false)
+                                     bool DebugLogging = false,
+                                     bool LoopNestMode = false)
       : Pass(std::move(Pass)), LoopCanonicalizationFPM(DebugLogging),
         UseMemorySSA(UseMemorySSA),
-        UseBlockFrequencyInfo(UseBlockFrequencyInfo) {
+        UseBlockFrequencyInfo(UseBlockFrequencyInfo),
+        LoopNestMode(LoopNestMode) {
     LoopCanonicalizationFPM.addPass(LoopSimplifyPass());
     LoopCanonicalizationFPM.addPass(LCSSAPass());
   }
@@ -389,6 +421,8 @@ class FunctionToLoopPassAdaptor
 
   static bool isRequired() { return true; }
 
+  bool isLoopNestMode() const { return LoopNestMode; }
+
 private:
   std::unique_ptr<PassConceptT> Pass;
 
@@ -396,12 +430,16 @@ class FunctionToLoopPassAdaptor
 
   bool UseMemorySSA = false;
   bool UseBlockFrequencyInfo = false;
+  const bool LoopNestMode;
 };
 
 /// A function to deduce a loop pass type and wrap it in the templated
 /// adaptor.
+///
+/// If \p Pass is a loop pass, the returned adaptor will be in loop mode.
 template <typename LoopPassT>
-FunctionToLoopPassAdaptor
+inline std::enable_if_t<is_detected<HasRunOnLoopT, LoopPassT>::value,
+                        FunctionToLoopPassAdaptor>
 createFunctionToLoopPassAdaptor(LoopPassT Pass, bool UseMemorySSA = false,
                                 bool UseBlockFrequencyInfo = false,
                                 bool DebugLogging = false) {
@@ -410,7 +448,46 @@ createFunctionToLoopPassAdaptor(LoopPassT Pass, bool UseMemorySSA = false,
                         LoopStandardAnalysisResults &, LPMUpdater &>;
   return FunctionToLoopPassAdaptor(
       std::make_unique<PassModelT>(std::move(Pass)), UseMemorySSA,
-      UseBlockFrequencyInfo, DebugLogging);
+      UseBlockFrequencyInfo, DebugLogging, false);
+}
+
+/// If \p Pass is a loop-nest pass, \p Pass will first be wrapped into a
+/// \c LoopPassManager and the returned adaptor will be in loop-nest mode.
+template <typename LoopNestPassT>
+inline std::enable_if_t<!is_detected<HasRunOnLoopT, LoopNestPassT>::value,
+                        FunctionToLoopPassAdaptor>
+createFunctionToLoopPassAdaptor(LoopNestPassT Pass, bool UseMemorySSA = false,
+                                bool UseBlockFrequencyInfo = false,
+                                bool DebugLogging = false) {
+  LoopPassManager LPM(DebugLogging);
+  LPM.addPass(std::move(Pass));
+  using PassModelT =
+      detail::PassModel<Loop, LoopPassManager, PreservedAnalyses,
+                        LoopAnalysisManager, LoopStandardAnalysisResults &,
+                        LPMUpdater &>;
+  return FunctionToLoopPassAdaptor(std::make_unique<PassModelT>(std::move(LPM)),
+                                   UseMemorySSA, UseBlockFrequencyInfo,
+                                   DebugLogging, true);
+}
+
+/// If \p Pass is an instance of \c LoopPassManager, the returned adaptor will
+/// be in loop-nest mode if the pass manager contains only loop-nest passes.
+template <>
+inline FunctionToLoopPassAdaptor
+createFunctionToLoopPassAdaptor<LoopPassManager>(LoopPassManager LPM,
+                                                 bool UseMemorySSA,
+                                                 bool UseBlockFrequencyInfo,
+                                                 bool DebugLogging) {
+  // Check if LPM contains any loop pass and if it does not, returns an adaptor
+  // in loop-nest mode.
+  using PassModelT =
+      detail::PassModel<Loop, LoopPassManager, PreservedAnalyses,
+                        LoopAnalysisManager, LoopStandardAnalysisResults &,
+                        LPMUpdater &>;
+  bool LoopNestMode = (LPM.getNumLoopPasses() == 0);
+  return FunctionToLoopPassAdaptor(std::make_unique<PassModelT>(std::move(LPM)),
+                                   UseMemorySSA, UseBlockFrequencyInfo,
+                                   DebugLogging, LoopNestMode);
 }
 
 /// Pass for printing a loop's contents as textual IR.
diff --git a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
index 7b8e2be17fa20..64c569de1f581 100644
--- a/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
+++ b/llvm/include/llvm/Transforms/Utils/BasicBlockUtils.h
@@ -74,7 +74,7 @@ bool EliminateUnreachableBlocks(Function &F, DomTreeUpdater *DTU = nullptr,
 /// in it, fold them away. This handles the case when all entries to the PHI
 /// nodes in a block are guaranteed equal, such as when the block has exactly
 /// one predecessor.
-void FoldSingleEntryPHINodes(BasicBlock *BB,
+bool FoldSingleEntryPHINodes(BasicBlock *BB,
                              MemoryDependenceResults *MemDep = nullptr);
 
 /// Examine each PHI in the given block and delete it if it is dead. Also
diff --git a/llvm/include/llvm/Transforms/Utils/Local.h b/llvm/include/llvm/Transforms/Utils/Local.h
index f62af365a27cc..ebfb62a48bbf8 100644
--- a/llvm/include/llvm/Transforms/Utils/Local.h
+++ b/llvm/include/llvm/Transforms/Utils/Local.h
@@ -150,20 +150,6 @@ bool replaceDbgUsesWithUndef(Instruction *I);
 //  Control Flow Graph Restructuring.
 //
 
-/// Like BasicBlock::removePredecessor, this method is called when we're about
-/// to delete Pred as a predecessor of BB. If BB contains any PHI nodes, this
-/// drops the entries in the PHI nodes for Pred.
-///
-/// Unlike the removePredecessor method, this attempts to simplify uses of PHI
-/// nodes that collapse into identity values.  For example, if we have:
-///   x = phi(1, 0, 0, 0)
-///   y = and x, z
-///
-/// .. and delete the predecessor corresponding to the '1', this will attempt to
-/// recursively fold the 'and' to 0.
-void RemovePredecessorAndSimplify(BasicBlock *BB, BasicBlock *Pred,
-                                  DomTreeUpdater *DTU = nullptr);
-
 /// BB is a block with one predecessor and its predecessor is known to have one
 /// successor (BB!). Eliminate the edge between them, moving the instructions in
 /// the predecessor into BB. This deletes the predecessor block.
diff --git a/llvm/lib/Analysis/AliasAnalysis.cpp b/llvm/lib/Analysis/AliasAnalysis.cpp
index 7d4969cc24c4d..f5b62ef06a23a 100644
--- a/llvm/lib/Analysis/AliasAnalysis.cpp
+++ b/llvm/lib/Analysis/AliasAnalysis.cpp
@@ -943,9 +943,9 @@ bool llvm::isNoAliasCall(const Value *V) {
   return false;
 }
 
-bool llvm::isNoAliasArgument(const Value *V) {
+static bool isNoAliasOrByValArgument(const Value *V) {
   if (const Argument *A = dyn_cast<Argument>(V))
-    return A->hasNoAliasAttr();
+    return A->hasNoAliasAttr() || A->hasByValAttr();
   return false;
 }
 
@@ -956,13 +956,13 @@ bool llvm::isIdentifiedObject(const Value *V) {
     return true;
   if (isNoAliasCall(V))
     return true;
-  if (const Argument *A = dyn_cast<Argument>(V))
-    return A->hasNoAliasAttr() || A->hasByValAttr();
+  if (isNoAliasOrByValArgument(V))
+    return true;
   return false;
 }
 
 bool llvm::isIdentifiedFunctionLocal(const Value *V) {
-  return isa<AllocaInst>(V) || isNoAliasCall(V) || isNoAliasArgument(V);
+  return isa<AllocaInst>(V) || isNoAliasCall(V) || isNoAliasOrByValArgument(V);
 }
 
 void llvm::getAAResultsAnalysisUsage(AnalysisUsage &AU) {
diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
index caa0635459b31..f9275daf12240 100644
--- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp
+++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
@@ -422,6 +422,7 @@ BasicAAResult::DecomposeGEPExpression(const Value *V, const DataLayout &DL,
   // Limit recursion depth to limit compile time in crazy cases.
   unsigned MaxLookup = MaxLookupSearchDepth;
   SearchTimes++;
+  const Instruction *CxtI = dyn_cast<Instruction>(V);
 
   unsigned MaxPointerSize = getMaxPointerSize(DL);
   DecomposedGEP Decomposed;
@@ -584,7 +585,7 @@ BasicAAResult::DecomposeGEPExpression(const Value *V, const DataLayout &DL,
       Scale = adjustToPointerSize(Scale, PointerSize);
 
       if (!!Scale) {
-        VariableGEPIndex Entry = {Index, ZExtBits, SExtBits, Scale};
+        VariableGEPIndex Entry = {Index, ZExtBits, SExtBits, Scale, CxtI};
         Decomposed.VarIndices.push_back(Entry);
       }
     }
@@ -1225,9 +1226,9 @@ AliasResult BasicAAResult::aliasGEP(
         // the Value this cycle may not hold in the next cycle. We'll just
         // give up if we can't determine conditions that hold for every cycle:
         const Value *V = DecompGEP1.VarIndices[i].V;
+        const Instruction *CxtI = DecompGEP1.VarIndices[i].CxtI;
 
-        KnownBits Known =
-            computeKnownBits(V, DL, 0, &AC, dyn_cast<Instruction>(GEP1), DT);
+        KnownBits Known = computeKnownBits(V, DL, 0, &AC, CxtI, DT);
         bool SignKnownZero = Known.isNonNegative();
         bool SignKnownOne = Known.isNegative();
 
@@ -1279,7 +1280,7 @@ AliasResult BasicAAResult::aliasGEP(
       if (DecompGEP1.VarIndices.size() == 1) {
         // VarIndex = Scale*V. If V != 0 then abs(VarIndex) >= abs(Scale).
         const VariableGEPIndex &Var = DecompGEP1.VarIndices[0];
-        if (isKnownNonZero(Var.V, DL))
+        if (isKnownNonZero(Var.V, DL, 0, &AC, Var.CxtI, DT))
           MinAbsVarIndex = Var.Scale.abs();
       } else if (DecompGEP1.VarIndices.size() == 2) {
         // VarIndex = Scale*V0 + (-Scale)*V1.
@@ -1290,7 +1291,7 @@ AliasResult BasicAAResult::aliasGEP(
         const VariableGEPIndex &Var1 = DecompGEP1.VarIndices[1];
         if (Var0.Scale == -Var1.Scale && Var0.ZExtBits == Var1.ZExtBits &&
             Var0.SExtBits == Var1.SExtBits && VisitedPhiBBs.empty() &&
-            isKnownNonEqual(Var0.V, Var1.V, DL))
+            isKnownNonEqual(Var0.V, Var1.V, DL, &AC, /* CxtI */ nullptr, DT))
           MinAbsVarIndex = Var0.Scale.abs();
       }
 
@@ -1755,7 +1756,7 @@ void BasicAAResult::GetIndexDifference(
 
     // If we didn't consume this entry, add it to the end of the Dest list.
     if (!!Scale) {
-      VariableGEPIndex Entry = {V, ZExtBits, SExtBits, -Scale};
+      VariableGEPIndex Entry = {V, ZExtBits, SExtBits, -Scale, Src[i].CxtI};
       Dest.push_back(Entry);
     }
   }
diff --git a/llvm/lib/Analysis/BranchProbabilityInfo.cpp b/llvm/lib/Analysis/BranchProbabilityInfo.cpp
index d4cb46c82e3a6..884ba484ae191 100644
--- a/llvm/lib/Analysis/BranchProbabilityInfo.cpp
+++ b/llvm/lib/Analysis/BranchProbabilityInfo.cpp
@@ -61,6 +61,7 @@ INITIALIZE_PASS_BEGIN(BranchProbabilityInfoWrapperPass, "branch-prob",
                       "Branch Probability Analysis", false, true)
 INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
+INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
 INITIALIZE_PASS_DEPENDENCY(PostDominatorTreeWrapperPass)
 INITIALIZE_PASS_END(BranchProbabilityInfoWrapperPass, "branch-prob",
                     "Branch Probability Analysis", false, true)
@@ -95,8 +96,6 @@ char BranchProbabilityInfoWrapperPass::ID = 0;
 // Probability of the edge BB2->BB3 = 4 / (124 + 4) = 0.03125
 static const uint32_t LBH_TAKEN_WEIGHT = 124;
 static const uint32_t LBH_NONTAKEN_WEIGHT = 4;
-// Unlikely edges within a loop are half as likely as other edges
-static const uint32_t LBH_UNLIKELY_WEIGHT = 62;
 
 /// Unreachable-terminating branch taken probability.
 ///
@@ -105,20 +104,6 @@ static const uint32_t LBH_UNLIKELY_WEIGHT = 62;
 /// All reachable probability will proportionally share the remaining part.
 static const BranchProbability UR_TAKEN_PROB = BranchProbability::getRaw(1);
 
-/// Weight for a branch taken going into a cold block.
-///
-/// This is the weight for a branch taken toward a block marked
-/// cold.  A block is marked cold if it's postdominated by a
-/// block containing a call to a cold function.  Cold functions
-/// are those marked with attribute 'cold'.
-static const uint32_t CC_TAKEN_WEIGHT = 4;
-
-/// Weight for a branch not-taken into a cold block.
-///
-/// This is the weight for a branch not taken toward a block marked
-/// cold.
-static const uint32_t CC_NONTAKEN_WEIGHT = 64;
-
 static const uint32_t PH_TAKEN_WEIGHT = 20;
 static const uint32_t PH_NONTAKEN_WEIGHT = 12;
 
@@ -135,18 +120,26 @@ static const uint32_t FPH_ORD_WEIGHT = 1024 * 1024 - 1;
 /// exceptional case, so the result is unlikely.
 static const uint32_t FPH_UNO_WEIGHT = 1;
 
-/// Invoke-terminating normal branch taken weight
-///
-/// This is the weight for branching to the normal destination of an invoke
-/// instruction. We expect this to happen most of the time. Set the weight to an
-/// absurdly high value so that nested loops subsume it.
-static const uint32_t IH_TAKEN_WEIGHT = 1024 * 1024 - 1;
-
-/// Invoke-terminating normal branch not-taken weight.
-///
-/// This is the weight for branching to the unwind destination of an invoke
-/// instruction. This is essentially never taken.
-static const uint32_t IH_NONTAKEN_WEIGHT = 1;
+/// Set of dedicated "absolute" execution weights for a block. These weights are
+/// meaningful relative to each other and their derivatives only.
+enum class BlockExecWeight : std::uint32_t {
+  /// Special weight used for cases with exact zero probability.
+  ZERO = 0x0,
+  /// Minimal possible non zero weight.
+  LOWEST_NON_ZERO = 0x1,
+  /// Weight to an 'unreachable' block.
+  UNREACHABLE = ZERO,
+  /// Weight to a block containing non returning call.
+  NORETURN = LOWEST_NON_ZERO,
+  /// Weight to 'unwind' block of an invoke instruction.
+  UNWIND = LOWEST_NON_ZERO,
+  /// Weight to a 'cold' block. Cold blocks are the ones containing calls marked
+  /// with attribute 'cold'.
+  COLD = 0xffff,
+  /// Default weight is used in cases when there is no dedicated execution
+  /// weight set. It is not propagated through the domination line either.
+  DEFAULT = 0xfffff
+};
 
 BranchProbabilityInfo::SccInfo::SccInfo(const Function &F) {
   // Record SCC numbers of blocks in the CFG to identify irreducible loops.
@@ -306,133 +299,6 @@ void BranchProbabilityInfo::getLoopExitBlocks(
   }
 }
 
-static void UpdatePDTWorklist(const BasicBlock *BB, PostDominatorTree *PDT,
-                              SmallVectorImpl<const BasicBlock *> &WorkList,
-                              SmallPtrSetImpl<const BasicBlock *> &TargetSet) {
-  SmallVector<BasicBlock *, 8> Descendants;
-  SmallPtrSet<const BasicBlock *, 16> NewItems;
-
-  PDT->getDescendants(const_cast<BasicBlock *>(BB), Descendants);
-  for (auto *BB : Descendants)
-    if (TargetSet.insert(BB).second)
-      for (pred_iterator PI = pred_begin(BB), E = pred_end(BB); PI != E; ++PI)
-        if (!TargetSet.count(*PI))
-          NewItems.insert(*PI);
-  WorkList.insert(WorkList.end(), NewItems.begin(), NewItems.end());
-}
-
-/// Compute a set of basic blocks that are post-dominated by unreachables.
-void BranchProbabilityInfo::computePostDominatedByUnreachable(
-    const Function &F, PostDominatorTree *PDT) {
-  SmallVector<const BasicBlock *, 8> WorkList;
-  for (auto &BB : F) {
-    const Instruction *TI = BB.getTerminator();
-    if (TI->getNumSuccessors() == 0) {
-      if (isa<UnreachableInst>(TI) ||
-          // If this block is terminated by a call to
-          // @llvm.experimental.deoptimize then treat it like an unreachable
-          // since the @llvm.experimental.deoptimize call is expected to
-          // practically never execute.
-          BB.getTerminatingDeoptimizeCall())
-        UpdatePDTWorklist(&BB, PDT, WorkList, PostDominatedByUnreachable);
-    }
-  }
-
-  while (!WorkList.empty()) {
-    const BasicBlock *BB = WorkList.pop_back_val();
-    if (PostDominatedByUnreachable.count(BB))
-      continue;
-    // If the terminator is an InvokeInst, check only the normal destination
-    // block as the unwind edge of InvokeInst is also very unlikely taken.
-    if (auto *II = dyn_cast<InvokeInst>(BB->getTerminator())) {
-      if (PostDominatedByUnreachable.count(II->getNormalDest()))
-        UpdatePDTWorklist(BB, PDT, WorkList, PostDominatedByUnreachable);
-    }
-    // If all the successors are unreachable, BB is unreachable as well.
-    else if (!successors(BB).empty() &&
-             llvm::all_of(successors(BB), [this](const BasicBlock *Succ) {
-               return PostDominatedByUnreachable.count(Succ);
-             }))
-      UpdatePDTWorklist(BB, PDT, WorkList, PostDominatedByUnreachable);
-  }
-}
-
-/// compute a set of basic blocks that are post-dominated by ColdCalls.
-void BranchProbabilityInfo::computePostDominatedByColdCall(
-    const Function &F, PostDominatorTree *PDT) {
-  SmallVector<const BasicBlock *, 8> WorkList;
-  for (auto &BB : F)
-    for (auto &I : BB)
-      if (const CallInst *CI = dyn_cast<CallInst>(&I))
-        if (CI->hasFnAttr(Attribute::Cold))
-          UpdatePDTWorklist(&BB, PDT, WorkList, PostDominatedByColdCall);
-
-  while (!WorkList.empty()) {
-    const BasicBlock *BB = WorkList.pop_back_val();
-
-    // If the terminator is an InvokeInst, check only the normal destination
-    // block as the unwind edge of InvokeInst is also very unlikely taken.
-    if (auto *II = dyn_cast<InvokeInst>(BB->getTerminator())) {
-      if (PostDominatedByColdCall.count(II->getNormalDest()))
-        UpdatePDTWorklist(BB, PDT, WorkList, PostDominatedByColdCall);
-    }
-    // If all of successor are post dominated then BB is also done.
-    else if (!successors(BB).empty() &&
-             llvm::all_of(successors(BB), [this](const BasicBlock *Succ) {
-               return PostDominatedByColdCall.count(Succ);
-             }))
-      UpdatePDTWorklist(BB, PDT, WorkList, PostDominatedByColdCall);
-  }
-}
-
-/// Calculate edge weights for successors lead to unreachable.
-///
-/// Predict that a successor which leads necessarily to an
-/// unreachable-terminated block as extremely unlikely.
-bool BranchProbabilityInfo::calcUnreachableHeuristics(const BasicBlock *BB) {
-  const Instruction *TI = BB->getTerminator();
-  (void) TI;
-  assert(TI->getNumSuccessors() > 1 && "expected more than one successor!");
-  assert(!isa<InvokeInst>(TI) &&
-         "Invokes should have already been handled by calcInvokeHeuristics");
-
-  SmallVector<unsigned, 4> UnreachableEdges;
-  SmallVector<unsigned, 4> ReachableEdges;
-
-  for (const_succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I)
-    if (PostDominatedByUnreachable.count(*I))
-      UnreachableEdges.push_back(I.getSuccessorIndex());
-    else
-      ReachableEdges.push_back(I.getSuccessorIndex());
-
-  // Skip probabilities if all were reachable.
-  if (UnreachableEdges.empty())
-    return false;
-
-  SmallVector<BranchProbability, 4> EdgeProbabilities(
-      BB->getTerminator()->getNumSuccessors(), BranchProbability::getUnknown());
-  if (ReachableEdges.empty()) {
-    BranchProbability Prob(1, UnreachableEdges.size());
-    for (unsigned SuccIdx : UnreachableEdges)
-      EdgeProbabilities[SuccIdx] = Prob;
-    setEdgeProbability(BB, EdgeProbabilities);
-    return true;
-  }
-
-  auto UnreachableProb = UR_TAKEN_PROB;
-  auto ReachableProb =
-      (BranchProbability::getOne() - UR_TAKEN_PROB * UnreachableEdges.size()) /
-      ReachableEdges.size();
-
-  for (unsigned SuccIdx : UnreachableEdges)
-    EdgeProbabilities[SuccIdx] = UnreachableProb;
-  for (unsigned SuccIdx : ReachableEdges)
-    EdgeProbabilities[SuccIdx] = ReachableProb;
-
-  setEdgeProbability(BB, EdgeProbabilities);
-  return true;
-}
-
 // Propagate existing explicit probabilities from either profile data or
 // 'expect' intrinsic processing. Examine metadata against unreachable
 // heuristic. The probability of the edge coming to unreachable block is
@@ -473,7 +339,12 @@ bool BranchProbabilityInfo::calcMetadataWeights(const BasicBlock *BB) {
            "Too many bits for uint32_t");
     Weights.push_back(Weight->getZExtValue());
     WeightSum += Weights.back();
-    if (PostDominatedByUnreachable.count(TI->getSuccessor(I - 1)))
+    const LoopBlock SrcLoopBB = getLoopBlock(BB);
+    const LoopBlock DstLoopBB = getLoopBlock(TI->getSuccessor(I - 1));
+    auto EstimatedWeight = getEstimatedEdgeWeight({SrcLoopBB, DstLoopBB});
+    if (EstimatedWeight &&
+        EstimatedWeight.getValue() <=
+            static_cast<uint32_t>(BlockExecWeight::UNREACHABLE))
       UnreachableIdxs.push_back(I - 1);
     else
       ReachableIdxs.push_back(I - 1);
@@ -578,60 +449,6 @@ bool BranchProbabilityInfo::calcMetadataWeights(const BasicBlock *BB) {
   return true;
 }
 
-/// Calculate edge weights for edges leading to cold blocks.
-///
-/// A cold block is one post-dominated by  a block with a call to a
-/// cold function.  Those edges are unlikely to be taken, so we give
-/// them relatively low weight.
-///
-/// Return true if we could compute the weights for cold edges.
-/// Return false, otherwise.
-bool BranchProbabilityInfo::calcColdCallHeuristics(const BasicBlock *BB) {
-  const Instruction *TI = BB->getTerminator();
-  (void) TI;
-  assert(TI->getNumSuccessors() > 1 && "expected more than one successor!");
-  assert(!isa<InvokeInst>(TI) &&
-         "Invokes should have already been handled by calcInvokeHeuristics");
-
-  // Determine which successors are post-dominated by a cold block.
-  SmallVector<unsigned, 4> ColdEdges;
-  SmallVector<unsigned, 4> NormalEdges;
-  for (const_succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I)
-    if (PostDominatedByColdCall.count(*I))
-      ColdEdges.push_back(I.getSuccessorIndex());
-    else
-      NormalEdges.push_back(I.getSuccessorIndex());
-
-  // Skip probabilities if no cold edges.
-  if (ColdEdges.empty())
-    return false;
-
-  SmallVector<BranchProbability, 4> EdgeProbabilities(
-      BB->getTerminator()->getNumSuccessors(), BranchProbability::getUnknown());
-  if (NormalEdges.empty()) {
-    BranchProbability Prob(1, ColdEdges.size());
-    for (unsigned SuccIdx : ColdEdges)
-      EdgeProbabilities[SuccIdx] = Prob;
-    setEdgeProbability(BB, EdgeProbabilities);
-    return true;
-  }
-
-  auto ColdProb = BranchProbability::getBranchProbability(
-      CC_TAKEN_WEIGHT,
-      (CC_TAKEN_WEIGHT + CC_NONTAKEN_WEIGHT) * uint64_t(ColdEdges.size()));
-  auto NormalProb = BranchProbability::getBranchProbability(
-      CC_NONTAKEN_WEIGHT,
-      (CC_TAKEN_WEIGHT + CC_NONTAKEN_WEIGHT) * uint64_t(NormalEdges.size()));
-
-  for (unsigned SuccIdx : ColdEdges)
-    EdgeProbabilities[SuccIdx] = ColdProb;
-  for (unsigned SuccIdx : NormalEdges)
-    EdgeProbabilities[SuccIdx] = NormalProb;
-
-  setEdgeProbability(BB, EdgeProbabilities);
-  return true;
-}
-
 // Calculate Edge Weights using "Pointer Heuristics". Predict a comparison
 // between two pointer or pointer and NULL will fail.
 bool BranchProbabilityInfo::calcPointerHeuristics(const BasicBlock *BB) {
@@ -775,81 +592,324 @@ computeUnlikelySuccessors(const BasicBlock *BB, Loop *L,
   }
 }
 
-// Calculate Edge Weights using "Loop Branch Heuristics". Predict backedges
-// as taken, exiting edges as not-taken.
-bool BranchProbabilityInfo::calcLoopBranchHeuristics(const BasicBlock *BB,
-                                                     const LoopInfo &LI) {
-  LoopBlock LB(BB, LI, *SccI.get());
-  if (!LB.belongsToLoop())
+Optional<uint32_t>
+BranchProbabilityInfo::getEstimatedBlockWeight(const BasicBlock *BB) const {
+  auto WeightIt = EstimatedBlockWeight.find(BB);
+  if (WeightIt == EstimatedBlockWeight.end())
+    return None;
+  return WeightIt->second;
+}
+
+Optional<uint32_t>
+BranchProbabilityInfo::getEstimatedLoopWeight(const LoopData &L) const {
+  auto WeightIt = EstimatedLoopWeight.find(L);
+  if (WeightIt == EstimatedLoopWeight.end())
+    return None;
+  return WeightIt->second;
+}
+
+Optional<uint32_t>
+BranchProbabilityInfo::getEstimatedEdgeWeight(const LoopEdge &Edge) const {
+  // For edges entering a loop take weight of a loop rather than an individual
+  // block in the loop.
+  return isLoopEnteringEdge(Edge)
+             ? getEstimatedLoopWeight(Edge.second.getLoopData())
+             : getEstimatedBlockWeight(Edge.second.getBlock());
+}
+
+template <class IterT>
+Optional<uint32_t> BranchProbabilityInfo::getMaxEstimatedEdgeWeight(
+    const LoopBlock &SrcLoopBB, iterator_range<IterT> Successors) const {
+  SmallVector<uint32_t, 4> Weights;
+  Optional<uint32_t> MaxWeight;
+  for (const BasicBlock *DstBB : Successors) {
+    const LoopBlock DstLoopBB = getLoopBlock(DstBB);
+    auto Weight = getEstimatedEdgeWeight({SrcLoopBB, DstLoopBB});
+
+    if (!Weight)
+      return None;
+
+    if (!MaxWeight || MaxWeight.getValue() < Weight.getValue())
+      MaxWeight = Weight;
+  }
+
+  return MaxWeight;
+}
+
+// Updates \p LoopBB's weight and returns true. If \p LoopBB has already
+// an associated weight it is unchanged and false is returned.
+//
+// Please note by the algorithm the weight is not expected to change once set
+// thus 'false' status is used to track visited blocks.
+bool BranchProbabilityInfo::updateEstimatedBlockWeight(
+    LoopBlock &LoopBB, uint32_t BBWeight,
+    SmallVectorImpl<BasicBlock *> &BlockWorkList,
+    SmallVectorImpl<LoopBlock> &LoopWorkList) {
+  BasicBlock *BB = LoopBB.getBlock();
+
+  // In general, weight is assigned to a block when it has final value and
+  // can't/shouldn't be changed.  However, there are cases when a block
+  // inherently has several (possibly "contradicting") weights. For example,
+  // "unwind" block may also contain "cold" call. In that case the first
+  // set weight is favored and all consequent weights are ignored.
+  if (!EstimatedBlockWeight.insert({BB, BBWeight}).second)
     return false;
 
-  SmallPtrSet<const BasicBlock*, 8> UnlikelyBlocks;
-  if (LB.getLoop())
-    computeUnlikelySuccessors(BB, LB.getLoop(), UnlikelyBlocks);
+  for (BasicBlock *PredBlock : predecessors(BB)) {
+    LoopBlock PredLoop = getLoopBlock(PredBlock);
+    // Add affected block/loop to a working list.
+    if (isLoopExitingEdge({PredLoop, LoopBB})) {
+      if (!EstimatedLoopWeight.count(PredLoop.getLoopData()))
+        LoopWorkList.push_back(PredLoop);
+    } else if (!EstimatedBlockWeight.count(PredBlock))
+      BlockWorkList.push_back(PredBlock);
+  }
+  return true;
+}
 
-  SmallVector<unsigned, 8> BackEdges;
-  SmallVector<unsigned, 8> ExitingEdges;
-  SmallVector<unsigned, 8> InEdges; // Edges from header to the loop.
-  SmallVector<unsigned, 8> UnlikelyEdges;
+// Starting from \p BB traverse through dominator blocks and assign \p BBWeight
+// to all such blocks that are post dominated by \BB. In other words to all
+// blocks that the one is executed if and only if another one is executed.
+// Importantly, we skip loops here for two reasons. First weights of blocks in
+// a loop should be scaled by trip count (yet possibly unknown). Second there is
+// no any value in doing that because that doesn't give any additional
+// information regarding distribution of probabilities inside the loop.
+// Exception is loop 'enter' and 'exit' edges that are handled in a special way
+// at calcEstimatedHeuristics.
+//
+// In addition, \p WorkList is populated with basic blocks if at leas one
+// successor has updated estimated weight.
+void BranchProbabilityInfo::propagateEstimatedBlockWeight(
+    const LoopBlock &LoopBB, DominatorTree *DT, PostDominatorTree *PDT,
+    uint32_t BBWeight, SmallVectorImpl<BasicBlock *> &BlockWorkList,
+    SmallVectorImpl<LoopBlock> &LoopWorkList) {
+  const BasicBlock *BB = LoopBB.getBlock();
+  const auto *DTStartNode = DT->getNode(BB);
+  const auto *PDTStartNode = PDT->getNode(BB);
+
+  // TODO: Consider propagating weight down the domination line as well.
+  for (const auto *DTNode = DTStartNode; DTNode != nullptr;
+       DTNode = DTNode->getIDom()) {
+    auto *DomBB = DTNode->getBlock();
+    // Consider blocks which lie on one 'line'.
+    if (!PDT->dominates(PDTStartNode, PDT->getNode(DomBB)))
+      // If BB doesn't post dominate DomBB it will not post dominate dominators
+      // of DomBB as well.
+      break;
 
-  for (const_succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) {
-    LoopBlock SuccLB(*I, LI, *SccI.get());
-    LoopEdge Edge(LB, SuccLB);
-    bool IsUnlikelyEdge = LB.getLoop() && UnlikelyBlocks.contains(*I);
-
-    if (IsUnlikelyEdge)
-      UnlikelyEdges.push_back(I.getSuccessorIndex());
-    else if (isLoopExitingEdge(Edge))
-      ExitingEdges.push_back(I.getSuccessorIndex());
-    else if (isLoopBackEdge(Edge))
-      BackEdges.push_back(I.getSuccessorIndex());
-    else {
-      InEdges.push_back(I.getSuccessorIndex());
+    LoopBlock DomLoopBB = getLoopBlock(DomBB);
+    const LoopEdge Edge{DomLoopBB, LoopBB};
+    // Don't propagate weight to blocks belonging to different loops.
+    if (!isLoopEnteringExitingEdge(Edge)) {
+      if (!updateEstimatedBlockWeight(DomLoopBB, BBWeight, BlockWorkList,
+                                      LoopWorkList))
+        // If DomBB has weight set then all it's predecessors are already
+        // processed (since we propagate weight up to the top of IR each time).
+        break;
+    } else if (isLoopExitingEdge(Edge)) {
+      LoopWorkList.push_back(DomLoopBB);
     }
   }
+}
+
+Optional<uint32_t> BranchProbabilityInfo::getInitialEstimatedBlockWeight(
+    const BasicBlock *BB) {
+  // Returns true if \p BB has call marked with "NoReturn" attribute.
+  auto hasNoReturn = [&](const BasicBlock *BB) {
+    for (const auto &I : reverse(*BB))
+      if (const CallInst *CI = dyn_cast<CallInst>(&I))
+        if (CI->hasFnAttr(Attribute::NoReturn))
+          return true;
 
-  if (BackEdges.empty() && ExitingEdges.empty() && UnlikelyEdges.empty())
     return false;
+  };
+
+  // Important note regarding the order of checks. They are ordered by weight
+  // from lowest to highest. Doing that allows to avoid "unstable" results
+  // when several conditions heuristics can be applied simultaneously.
+  if (isa<UnreachableInst>(BB->getTerminator()) ||
+      // If this block is terminated by a call to
+      // @llvm.experimental.deoptimize then treat it like an unreachable
+      // since it is expected to practically never execute.
+      // TODO: Should we actually treat as never returning call?
+      BB->getTerminatingDeoptimizeCall())
+    return hasNoReturn(BB)
+               ? static_cast<uint32_t>(BlockExecWeight::NORETURN)
+               : static_cast<uint32_t>(BlockExecWeight::UNREACHABLE);
+
+  // Check if the block is 'unwind' handler of  some invoke instruction.
+  for (const auto *Pred : predecessors(BB))
+    if (Pred)
+      if (const auto *II = dyn_cast<InvokeInst>(Pred->getTerminator()))
+        if (II->getUnwindDest() == BB)
+          return static_cast<uint32_t>(BlockExecWeight::UNWIND);
+
+  // Check if the block contains 'cold' call.
+  for (const auto &I : *BB)
+    if (const CallInst *CI = dyn_cast<CallInst>(&I))
+      if (CI->hasFnAttr(Attribute::Cold))
+        return static_cast<uint32_t>(BlockExecWeight::COLD);
+
+  return None;
+}
 
-  // Collect the sum of probabilities of back-edges/in-edges/exiting-edges, and
-  // normalize them so that they sum up to one.
-  unsigned Denom = (BackEdges.empty() ? 0 : LBH_TAKEN_WEIGHT) +
-                   (InEdges.empty() ? 0 : LBH_TAKEN_WEIGHT) +
-                   (UnlikelyEdges.empty() ? 0 : LBH_UNLIKELY_WEIGHT) +
-                   (ExitingEdges.empty() ? 0 : LBH_NONTAKEN_WEIGHT);
+// Does RPO traversal over all blocks in \p F and assigns weights to
+// 'unreachable', 'noreturn', 'cold', 'unwind' blocks. In addition it does its
+// best to propagate the weight to up/down the IR.
+void BranchProbabilityInfo::computeEestimateBlockWeight(
+    const Function &F, DominatorTree *DT, PostDominatorTree *PDT) {
+  SmallVector<BasicBlock *, 8> BlockWorkList;
+  SmallVector<LoopBlock, 8> LoopWorkList;
+
+  // By doing RPO we make sure that all predecessors already have weights
+  // calculated before visiting theirs successors.
+  ReversePostOrderTraversal<const Function *> RPOT(&F);
+  for (const auto *BB : RPOT)
+    if (auto BBWeight = getInitialEstimatedBlockWeight(BB))
+      // If we were able to find estimated weight for the block set it to this
+      // block and propagate up the IR.
+      propagateEstimatedBlockWeight(getLoopBlock(BB), DT, PDT,
+                                    BBWeight.getValue(), BlockWorkList,
+                                    LoopWorkList);
+
+  // BlockWorklist/LoopWorkList contains blocks/loops with at least one
+  // successor/exit having estimated weight. Try to propagate weight to such
+  // blocks/loops from successors/exits.
+  // Process loops and blocks. Order is not important.
+  do {
+    while (!LoopWorkList.empty()) {
+      const LoopBlock LoopBB = LoopWorkList.pop_back_val();
+
+      if (EstimatedLoopWeight.count(LoopBB.getLoopData()))
+        continue;
 
-  SmallVector<BranchProbability, 4> EdgeProbabilities(
-      BB->getTerminator()->getNumSuccessors(), BranchProbability::getUnknown());
-  if (uint32_t numBackEdges = BackEdges.size()) {
-    BranchProbability TakenProb = BranchProbability(LBH_TAKEN_WEIGHT, Denom);
-    auto Prob = TakenProb / numBackEdges;
-    for (unsigned SuccIdx : BackEdges)
-      EdgeProbabilities[SuccIdx] = Prob;
-  }
+      SmallVector<BasicBlock *, 4> Exits;
+      getLoopExitBlocks(LoopBB, Exits);
+      auto LoopWeight = getMaxEstimatedEdgeWeight(
+          LoopBB, make_range(Exits.begin(), Exits.end()));
 
-  if (uint32_t numInEdges = InEdges.size()) {
-    BranchProbability TakenProb = BranchProbability(LBH_TAKEN_WEIGHT, Denom);
-    auto Prob = TakenProb / numInEdges;
-    for (unsigned SuccIdx : InEdges)
-      EdgeProbabilities[SuccIdx] = Prob;
-  }
+      if (LoopWeight) {
+        // If we never exit the loop then we can enter it once at maximum.
+        if (LoopWeight <= static_cast<uint32_t>(BlockExecWeight::UNREACHABLE))
+          LoopWeight = static_cast<uint32_t>(BlockExecWeight::LOWEST_NON_ZERO);
+
+        EstimatedLoopWeight.insert(
+            {LoopBB.getLoopData(), LoopWeight.getValue()});
+        // Add all blocks entering the loop into working list.
+        getLoopEnterBlocks(LoopBB, BlockWorkList);
+      }
+    }
 
-  if (uint32_t numExitingEdges = ExitingEdges.size()) {
-    BranchProbability NotTakenProb = BranchProbability(LBH_NONTAKEN_WEIGHT,
-                                                       Denom);
-    auto Prob = NotTakenProb / numExitingEdges;
-    for (unsigned SuccIdx : ExitingEdges)
-      EdgeProbabilities[SuccIdx] = Prob;
+    while (!BlockWorkList.empty()) {
+      // We can reach here only if BlockWorkList is not empty.
+      const BasicBlock *BB = BlockWorkList.pop_back_val();
+      if (EstimatedBlockWeight.count(BB))
+        continue;
+
+      // We take maximum over all weights of successors. In other words we take
+      // weight of "hot" path. In theory we can probably find a better function
+      // which gives higher accuracy results (comparing to "maximum") but I
+      // can't
+      // think of any right now. And I doubt it will make any difference in
+      // practice.
+      const LoopBlock LoopBB = getLoopBlock(BB);
+      auto MaxWeight = getMaxEstimatedEdgeWeight(LoopBB, successors(BB));
+
+      if (MaxWeight)
+        propagateEstimatedBlockWeight(LoopBB, DT, PDT, MaxWeight.getValue(),
+                                      BlockWorkList, LoopWorkList);
+    }
+  } while (!BlockWorkList.empty() || !LoopWorkList.empty());
+}
+
+// Calculate edge probabilities based on block's estimated weight.
+// Note that gathered weights were not scaled for loops. Thus edges entering
+// and exiting loops requires special processing.
+bool BranchProbabilityInfo::calcEstimatedHeuristics(const BasicBlock *BB) {
+  assert(BB->getTerminator()->getNumSuccessors() > 1 &&
+         "expected more than one successor!");
+
+  const LoopBlock LoopBB = getLoopBlock(BB);
+
+  SmallPtrSet<const BasicBlock *, 8> UnlikelyBlocks;
+  uint32_t TC = LBH_TAKEN_WEIGHT / LBH_NONTAKEN_WEIGHT;
+  if (LoopBB.getLoop())
+    computeUnlikelySuccessors(BB, LoopBB.getLoop(), UnlikelyBlocks);
+
+  // Changed to 'true' if at least one successor has estimated weight.
+  bool FoundEstimatedWeight = false;
+  SmallVector<uint32_t, 4> SuccWeights;
+  uint64_t TotalWeight = 0;
+  // Go over all successors of BB and put their weights into SuccWeights.
+  for (const_succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) {
+    const BasicBlock *SuccBB = *I;
+    Optional<uint32_t> Weight;
+    const LoopBlock SuccLoopBB = getLoopBlock(SuccBB);
+    const LoopEdge Edge{LoopBB, SuccLoopBB};
+
+    Weight = getEstimatedEdgeWeight(Edge);
+
+    if (isLoopExitingEdge(Edge) &&
+        // Avoid adjustment of ZERO weight since it should remain unchanged.
+        Weight != static_cast<uint32_t>(BlockExecWeight::ZERO)) {
+      // Scale down loop exiting weight by trip count.
+      Weight = std::max(
+          static_cast<uint32_t>(BlockExecWeight::LOWEST_NON_ZERO),
+          Weight.getValueOr(static_cast<uint32_t>(BlockExecWeight::DEFAULT)) /
+              TC);
+    }
+    bool IsUnlikelyEdge = LoopBB.getLoop() && UnlikelyBlocks.contains(SuccBB);
+    if (IsUnlikelyEdge &&
+        // Avoid adjustment of ZERO weight since it should remain unchanged.
+        Weight != static_cast<uint32_t>(BlockExecWeight::ZERO)) {
+      // 'Unlikely' blocks have twice lower weight.
+      Weight = std::max(
+          static_cast<uint32_t>(BlockExecWeight::LOWEST_NON_ZERO),
+          Weight.getValueOr(static_cast<uint32_t>(BlockExecWeight::DEFAULT)) /
+              2);
+    }
+
+    if (Weight)
+      FoundEstimatedWeight = true;
+
+    auto WeightVal =
+        Weight.getValueOr(static_cast<uint32_t>(BlockExecWeight::DEFAULT));
+    TotalWeight += WeightVal;
+    SuccWeights.push_back(WeightVal);
   }
 
-  if (uint32_t numUnlikelyEdges = UnlikelyEdges.size()) {
-    BranchProbability UnlikelyProb = BranchProbability(LBH_UNLIKELY_WEIGHT,
-                                                       Denom);
-    auto Prob = UnlikelyProb / numUnlikelyEdges;
-    for (unsigned SuccIdx : UnlikelyEdges)
-      EdgeProbabilities[SuccIdx] = Prob;
+  // If non of blocks have estimated weight bail out.
+  // If TotalWeight is 0 that means weight of each successor is 0 as well and
+  // equally likely. Bail out early to not deal with devision by zero.
+  if (!FoundEstimatedWeight || TotalWeight == 0)
+    return false;
+
+  assert(SuccWeights.size() == succ_size(BB) && "Missed successor?");
+  const unsigned SuccCount = SuccWeights.size();
+
+  // If the sum of weights does not fit in 32 bits, scale every weight down
+  // accordingly.
+  if (TotalWeight > UINT32_MAX) {
+    uint64_t ScalingFactor = TotalWeight / UINT32_MAX + 1;
+    TotalWeight = 0;
+    for (unsigned Idx = 0; Idx < SuccCount; ++Idx) {
+      SuccWeights[Idx] /= ScalingFactor;
+      if (SuccWeights[Idx] == static_cast<uint32_t>(BlockExecWeight::ZERO))
+        SuccWeights[Idx] =
+            static_cast<uint32_t>(BlockExecWeight::LOWEST_NON_ZERO);
+      TotalWeight += SuccWeights[Idx];
+    }
+    assert(TotalWeight <= UINT32_MAX && "Total weight overflows");
   }
 
+  // Finally set probabilities to edges according to estimated block weights.
+  SmallVector<BranchProbability, 4> EdgeProbabilities(
+      SuccCount, BranchProbability::getUnknown());
+
+  for (unsigned Idx = 0; Idx < SuccCount; ++Idx) {
+    EdgeProbabilities[Idx] =
+        BranchProbability(SuccWeights[Idx], (uint32_t)TotalWeight);
+  }
   setEdgeProbability(BB, EdgeProbabilities);
   return true;
 }
@@ -1015,18 +1075,6 @@ bool BranchProbabilityInfo::calcFloatingPointHeuristics(const BasicBlock *BB) {
   return true;
 }
 
-bool BranchProbabilityInfo::calcInvokeHeuristics(const BasicBlock *BB) {
-  const InvokeInst *II = dyn_cast<InvokeInst>(BB->getTerminator());
-  if (!II)
-    return false;
-
-  BranchProbability TakenProb(IH_TAKEN_WEIGHT,
-                              IH_TAKEN_WEIGHT + IH_NONTAKEN_WEIGHT);
-  setEdgeProbability(
-      BB, SmallVector<BranchProbability, 2>({TakenProb, TakenProb.getCompl()}));
-  return true;
-}
-
 void BranchProbabilityInfo::releaseMemory() {
   Probs.clear();
   Handles.clear();
@@ -1202,26 +1250,34 @@ void BranchProbabilityInfo::eraseBlock(const BasicBlock *BB) {
   }
 }
 
-void BranchProbabilityInfo::calculate(const Function &F, const LoopInfo &LI,
+void BranchProbabilityInfo::calculate(const Function &F, const LoopInfo &LoopI,
                                       const TargetLibraryInfo *TLI,
+                                      DominatorTree *DT,
                                       PostDominatorTree *PDT) {
   LLVM_DEBUG(dbgs() << "---- Branch Probability Info : " << F.getName()
                     << " ----\n\n");
   LastF = &F; // Store the last function we ran on for printing.
-  assert(PostDominatedByUnreachable.empty());
-  assert(PostDominatedByColdCall.empty());
+  LI = &LoopI;
 
   SccI = std::make_unique<SccInfo>(F);
 
+  assert(EstimatedBlockWeight.empty());
+  assert(EstimatedLoopWeight.empty());
+
+  std::unique_ptr<DominatorTree> DTPtr;
   std::unique_ptr<PostDominatorTree> PDTPtr;
 
+  if (!DT) {
+    DTPtr = std::make_unique<DominatorTree>(const_cast<Function &>(F));
+    DT = DTPtr.get();
+  }
+
   if (!PDT) {
     PDTPtr = std::make_unique<PostDominatorTree>(const_cast<Function &>(F));
     PDT = PDTPtr.get();
   }
 
-  computePostDominatedByUnreachable(F, PDT);
-  computePostDominatedByColdCall(F, PDT);
+  computeEestimateBlockWeight(F, DT, PDT);
 
   // Walk the basic blocks in post-order so that we can build up state about
   // the successors of a block iteratively.
@@ -1233,13 +1289,7 @@ void BranchProbabilityInfo::calculate(const Function &F, const LoopInfo &LI,
       continue;
     if (calcMetadataWeights(BB))
       continue;
-    if (calcInvokeHeuristics(BB))
-      continue;
-    if (calcUnreachableHeuristics(BB))
-      continue;
-    if (calcColdCallHeuristics(BB))
-      continue;
-    if (calcLoopBranchHeuristics(BB, LI))
+    if (calcEstimatedHeuristics(BB))
       continue;
     if (calcPointerHeuristics(BB))
       continue;
@@ -1249,8 +1299,8 @@ void BranchProbabilityInfo::calculate(const Function &F, const LoopInfo &LI,
       continue;
   }
 
-  PostDominatedByUnreachable.clear();
-  PostDominatedByColdCall.clear();
+  EstimatedLoopWeight.clear();
+  EstimatedBlockWeight.clear();
   SccI.reset();
 
   if (PrintBranchProb &&
@@ -1268,6 +1318,7 @@ void BranchProbabilityInfoWrapperPass::getAnalysisUsage(
   AU.addRequired<DominatorTreeWrapperPass>();
   AU.addRequired<LoopInfoWrapperPass>();
   AU.addRequired<TargetLibraryInfoWrapperPass>();
+  AU.addRequired<DominatorTreeWrapperPass>();
   AU.addRequired<PostDominatorTreeWrapperPass>();
   AU.setPreservesAll();
 }
@@ -1276,9 +1327,10 @@ bool BranchProbabilityInfoWrapperPass::runOnFunction(Function &F) {
   const LoopInfo &LI = getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
   const TargetLibraryInfo &TLI =
       getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
+  DominatorTree &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
   PostDominatorTree &PDT =
       getAnalysis<PostDominatorTreeWrapperPass>().getPostDomTree();
-  BPI.calculate(F, LI, &TLI, &PDT);
+  BPI.calculate(F, LI, &TLI, &DT, &PDT);
   return false;
 }
 
@@ -1295,6 +1347,7 @@ BranchProbabilityAnalysis::run(Function &F, FunctionAnalysisManager &AM) {
   BranchProbabilityInfo BPI;
   BPI.calculate(F, AM.getResult<LoopAnalysis>(F),
                 &AM.getResult<TargetLibraryAnalysis>(F),
+                &AM.getResult<DominatorTreeAnalysis>(F),
                 &AM.getResult<PostDominatorTreeAnalysis>(F));
   return BPI;
 }
diff --git a/llvm/lib/Analysis/CallGraph.cpp b/llvm/lib/Analysis/CallGraph.cpp
index 19c128b6633c0..9b212e564a46e 100644
--- a/llvm/lib/Analysis/CallGraph.cpp
+++ b/llvm/lib/Analysis/CallGraph.cpp
@@ -167,20 +167,6 @@ Function *CallGraph::removeFunctionFromModule(CallGraphNode *CGN) {
   return F;
 }
 
-/// spliceFunction - Replace the function represented by this node by another.
-/// This does not rescan the body of the function, so it is suitable when
-/// splicing the body of the old function to the new while also updating all
-/// callers from old to new.
-void CallGraph::spliceFunction(const Function *From, const Function *To) {
-  assert(FunctionMap.count(From) && "No CallGraphNode for function!");
-  assert(!FunctionMap.count(To) &&
-         "Pointing CallGraphNode at a function that already exists");
-  FunctionMapTy::iterator I = FunctionMap.find(From);
-  I->second->F = const_cast<Function*>(To);
-  FunctionMap[To] = std::move(I->second);
-  FunctionMap.erase(I);
-}
-
 // getOrInsertFunction - This method is identical to calling operator[], but
 // it will insert a new CallGraphNode for the specified function if one does
 // not already exist.
diff --git a/llvm/lib/Analysis/IRSimilarityIdentifier.cpp b/llvm/lib/Analysis/IRSimilarityIdentifier.cpp
index 41e234651349c..4ee152450c05c 100644
--- a/llvm/lib/Analysis/IRSimilarityIdentifier.cpp
+++ b/llvm/lib/Analysis/IRSimilarityIdentifier.cpp
@@ -15,6 +15,7 @@
 #include "llvm/Analysis/IRSimilarityIdentifier.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/IR/Intrinsics.h"
+#include "llvm/IR/Operator.h"
 #include "llvm/IR/User.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Support/SuffixTree.h"
@@ -25,15 +26,84 @@ using namespace IRSimilarity;
 IRInstructionData::IRInstructionData(Instruction &I, bool Legality,
                                      IRInstructionDataList &IDList)
     : Inst(&I), Legal(Legality), IDL(&IDList) {
-  // Here we collect the operands to be used to determine whether two
-  // instructions are similar to one another.
-  for (Use &OI : I.operands())
+  // We check for whether we have a comparison instruction.  If it is, we
+  // find the "less than" version of the predicate for consistency for
+  // comparison instructions throught the program.
+  if (CmpInst *C = dyn_cast<CmpInst>(&I)) {
+    CmpInst::Predicate Predicate = predicateForConsistency(C);
+    if (Predicate != C->getPredicate())
+      RevisedPredicate = Predicate;
+  }
+
+  // Here we collect the operands and their types for determining whether
+  // the structure of the operand use matches between two different candidates.
+  for (Use &OI : I.operands()) {
+    if (isa<CmpInst>(I) && RevisedPredicate.hasValue()) {
+      // If we have a CmpInst where the predicate is reversed, it means the
+      // operands must be reversed as well.
+      OperVals.insert(OperVals.begin(), OI.get());
+      continue;
+    }
+
     OperVals.push_back(OI.get());
+  }
+}
+
+CmpInst::Predicate IRInstructionData::predicateForConsistency(CmpInst *CI) {
+  switch (CI->getPredicate()) {
+  case CmpInst::FCMP_OGT:
+  case CmpInst::FCMP_UGT:
+  case CmpInst::FCMP_OGE:
+  case CmpInst::FCMP_UGE:
+  case CmpInst::ICMP_SGT:
+  case CmpInst::ICMP_UGT:
+  case CmpInst::ICMP_SGE:
+  case CmpInst::ICMP_UGE:
+    return CI->getSwappedPredicate();
+  default:
+    return CI->getPredicate();
+  }
+}
+
+CmpInst::Predicate IRInstructionData::getPredicate() const {
+  assert(isa<CmpInst>(Inst) &&
+         "Can only get a predicate from a compare instruction");
+
+  if (RevisedPredicate.hasValue())
+    return RevisedPredicate.getValue();
+  
+  return cast<CmpInst>(Inst)->getPredicate();
 }
 
 bool IRSimilarity::isClose(const IRInstructionData &A,
                            const IRInstructionData &B) {
-  return A.Legal && A.Inst->isSameOperationAs(B.Inst);
+
+  if (!A.Legal || !B.Legal)
+    return false;
+
+  // Check if we are performing the same sort of operation on the same types
+  // but not on the same values.
+  if (A.Inst->isSameOperationAs(B.Inst))
+    return true;
+
+  // If there is a predicate, this means that either there is a swapped
+  // predicate, or that the types are different, we want to make sure that
+  // the predicates are equivalent via swapping.
+  if (isa<CmpInst>(A.Inst) && isa<CmpInst>(B.Inst)) {
+
+    if (A.getPredicate() != B.getPredicate())
+      return false;
+
+    // If the predicates are the same via swap, make sure that the types are
+    // still the same.
+    auto ZippedTypes = zip(A.OperVals, B.OperVals);
+
+    return all_of(ZippedTypes, [](std::tuple<llvm::Value *, llvm::Value *> R) {
+      return std::get<0>(R)->getType() == std::get<1>(R)->getType();
+    });
+  }
+
+  return false;
 }
 
 // TODO: This is the same as the MachineOutliner, and should be consolidated
@@ -241,6 +311,96 @@ bool IRSimilarityCandidate::isSimilar(const IRSimilarityCandidate &A,
                 });
 }
 
+/// Determine if one or more of the assigned global value numbers for the
+/// operands in \p TargetValueNumbers is in the current mapping set for operand
+/// numbers in \p SourceOperands.  The set of possible corresponding global
+/// value numbers are replaced with the most recent version of compatible
+/// values.
+///
+/// \param [in] SourceValueToNumberMapping - The mapping of a Value to global
+/// value number for the source IRInstructionCandidate.
+/// \param [in, out] CurrentSrcTgtNumberMapping - The current mapping of source
+/// IRSimilarityCandidate global value numbers to a set of possible numbers in
+/// the target.
+/// \param [in] SourceOperands - The operands in the original
+/// IRSimilarityCandidate in the current instruction.
+/// \param [in] TargetValueNumbers - The global value numbers of the operands in
+/// the corresponding Instruction in the other IRSimilarityCandidate.
+/// \returns true if there exists a possible mapping between the source
+/// Instruction operands and the target Instruction operands, and false if not.
+static bool checkNumberingAndReplaceCommutative(
+  const DenseMap<Value *, unsigned> &SourceValueToNumberMapping,
+  DenseMap<unsigned, DenseSet<unsigned>> &CurrentSrcTgtNumberMapping,
+  ArrayRef<Value *> &SourceOperands,
+  DenseSet<unsigned> &TargetValueNumbers){
+
+  DenseMap<unsigned, DenseSet<unsigned>>::iterator ValueMappingIt;
+
+  unsigned ArgVal;
+  bool WasInserted;
+
+  // Iterate over the operands in the source IRSimilarityCandidate to determine
+  // whether there exists an operand in the other IRSimilarityCandidate that
+  // creates a valid mapping of Value to Value between the
+  // IRSimilarityCaniddates.
+  for (Value *V : SourceOperands) {
+    ArgVal = SourceValueToNumberMapping.find(V)->second;
+
+    std::tie(ValueMappingIt, WasInserted) = CurrentSrcTgtNumberMapping.insert(
+        std::make_pair(ArgVal, TargetValueNumbers));
+
+    // Instead of finding a current mapping, we inserted a set.  This means a
+    // mapping did not exist for the source Instruction operand, it has no
+    // current constraints we need to check.
+    if (WasInserted)
+      continue;
+
+    // If a mapping already exists for the source operand to the values in the
+    // other IRSimilarityCandidate we need to iterate over the items in other
+    // IRSimilarityCandidate's Instruction to determine whether there is a valid
+    // mapping of Value to Value.
+    DenseSet<unsigned> NewSet;
+    for (unsigned &Curr : ValueMappingIt->second)
+      // If we can find the value in the mapping, we add it to the new set.
+      if (TargetValueNumbers.find(Curr) != TargetValueNumbers.end())
+        NewSet.insert(Curr);
+
+    // If we could not find a Value, return 0.
+    if (NewSet.empty())
+      return false;
+    
+    // Otherwise replace the old mapping with the newly constructed one.
+    if (NewSet.size() != ValueMappingIt->second.size())
+      ValueMappingIt->second.swap(NewSet);
+
+    // We have reached no conclusions about the mapping, and cannot remove
+    // any items from the other operands, so we move to check the next operand.
+    if (ValueMappingIt->second.size() != 1)
+      continue;
+
+
+    unsigned ValToRemove = *ValueMappingIt->second.begin();
+    // When there is only one item left in the mapping for and operand, remove
+    // the value from the other operands.  If it results in there being no
+    // mapping, return false, it means the mapping is wrong
+    for (Value *InnerV : SourceOperands) {
+      if (V == InnerV)
+        continue;
+
+      unsigned InnerVal = SourceValueToNumberMapping.find(InnerV)->second;
+      ValueMappingIt = CurrentSrcTgtNumberMapping.find(InnerVal);
+      if (ValueMappingIt == CurrentSrcTgtNumberMapping.end())
+        continue;
+
+      ValueMappingIt->second.erase(ValToRemove);
+      if (ValueMappingIt->second.empty())
+        return false;
+    }
+  }
+
+  return true;
+}
+
 /// Determine if operand number \p TargetArgVal is in the current mapping set
 /// for operand number \p SourceArgVal.
 ///
@@ -296,8 +456,8 @@ bool checkNumberingAndReplace(
   return TargetSet.contains(TargetArgVal);
 }
 
-bool IRSimilarityCandidate::compareOperandMapping(OperandMapping A,
-                                                  OperandMapping B) {
+bool IRSimilarityCandidate::compareNonCommutativeOperandMapping(
+    OperandMapping A, OperandMapping B) {
   // Iterators to keep track of where we are in the operands for each
   // Instruction.
   ArrayRef<Value *>::iterator VItA = A.OperVals.begin();
@@ -330,6 +490,41 @@ bool IRSimilarityCandidate::compareOperandMapping(OperandMapping A,
   return true;
 }
 
+bool IRSimilarityCandidate::compareCommutativeOperandMapping(
+    OperandMapping A, OperandMapping B) {
+  DenseSet<unsigned> ValueNumbersA;      
+  DenseSet<unsigned> ValueNumbersB;
+
+  ArrayRef<Value *>::iterator VItA = A.OperVals.begin();
+  ArrayRef<Value *>::iterator VItB = B.OperVals.begin();
+  unsigned OperandLength = A.OperVals.size();
+
+  // Find the value number sets for the operands.
+  for (unsigned Idx = 0; Idx < OperandLength;
+       Idx++, VItA++, VItB++) {
+    ValueNumbersA.insert(A.IRSC.ValueToNumber.find(*VItA)->second);
+    ValueNumbersB.insert(B.IRSC.ValueToNumber.find(*VItB)->second);
+  }
+
+  // Iterate over the operands in the first IRSimilarityCandidate and make sure
+  // there exists a possible mapping with the operands in the second
+  // IRSimilarityCandidate.
+  if (!checkNumberingAndReplaceCommutative(A.IRSC.ValueToNumber,
+                                           A.ValueNumberMapping, A.OperVals,
+                                           ValueNumbersB))
+    return false;
+
+  // Iterate over the operands in the second IRSimilarityCandidate and make sure
+  // there exists a possible mapping with the operands in the first
+  // IRSimilarityCandidate.
+  if (!checkNumberingAndReplaceCommutative(B.IRSC.ValueToNumber,
+                                           B.ValueNumberMapping, B.OperVals,
+                                           ValueNumbersA))
+    return false;
+
+  return true;
+}
+
 bool IRSimilarityCandidate::compareStructure(const IRSimilarityCandidate &A,
                                              const IRSimilarityCandidate &B) {
   if (A.getLength() != B.getLength())
@@ -383,10 +578,21 @@ bool IRSimilarityCandidate::compareStructure(const IRSimilarityCandidate &A,
     if (!WasInserted && !ValueMappingIt->second.contains(InstValA))
       return false;
 
-    // TODO: Handle commutative instructions by mapping one operand to many
-    // operands instead only mapping a single operand to a single operand.
-    if (!compareOperandMapping({A, OperValsA, ValueNumberMappingA},
-                               {B, OperValsB, ValueNumberMappingB}))
+    // We have different paths for commutative instructions and non-commutative
+    // instructions since commutative instructions could allow multiple mappings
+    // to certain values.
+    if (IA->isCommutative() && !isa<FPMathOperator>(IA)) {
+      if (!compareCommutativeOperandMapping(
+              {A, OperValsA, ValueNumberMappingA},
+              {B, OperValsB, ValueNumberMappingB}))
+        return false;
+      continue;
+    }
+
+    // Handle the non-commutative cases.
+    if (!compareNonCommutativeOperandMapping(
+            {A, OperValsA, ValueNumberMappingA},
+            {B, OperValsB, ValueNumberMappingB}))
       return false;
   }
   return true;
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp
index 55f3bc4f29236..30c7ecff79403 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -1999,6 +1999,30 @@ static Value *omitCheckForZeroBeforeInvertedMulWithOverflow(Value *Op0,
   return NotOp1;
 }
 
+/// Given a bitwise logic op, check if the operands are add/sub with a common
+/// source value and inverted constant (identity: C - X -> ~(X + ~C)).
+static Value *simplifyLogicOfAddSub(Value *Op0, Value *Op1,
+                                    Instruction::BinaryOps Opcode) {
+  assert(Op0->getType() == Op1->getType() && "Mismatched binop types");
+  assert(BinaryOperator::isBitwiseLogicOp(Opcode) && "Expected logic op");
+  Value *X;
+  Constant *C1, *C2;
+  if ((match(Op0, m_Add(m_Value(X), m_Constant(C1))) &&
+       match(Op1, m_Sub(m_Constant(C2), m_Specific(X)))) ||
+      (match(Op1, m_Add(m_Value(X), m_Constant(C1))) &&
+       match(Op0, m_Sub(m_Constant(C2), m_Specific(X))))) {
+    if (ConstantExpr::getNot(C1) == C2) {
+      // (X + C) & (~C - X) --> (X + C) & ~(X + C) --> 0
+      // (X + C) | (~C - X) --> (X + C) | ~(X + C) --> -1
+      // (X + C) ^ (~C - X) --> (X + C) ^ ~(X + C) --> -1
+      Type *Ty = Op0->getType();
+      return Opcode == Instruction::And ? ConstantInt::getNullValue(Ty)
+                                        : ConstantInt::getAllOnesValue(Ty);
+    }
+  }
+  return nullptr;
+}
+
 /// Given operands for an And, see if we can fold the result.
 /// If not, this returns null.
 static Value *SimplifyAndInst(Value *Op0, Value *Op1, const SimplifyQuery &Q,
@@ -2035,6 +2059,9 @@ static Value *SimplifyAndInst(Value *Op0, Value *Op1, const SimplifyQuery &Q,
   if (match(Op1, m_c_Or(m_Specific(Op0), m_Value())))
     return Op0;
 
+  if (Value *V = simplifyLogicOfAddSub(Op0, Op1, Instruction::And))
+    return V;
+
   // A mask that only clears known zeros of a shifted value is a no-op.
   Value *X;
   const APInt *Mask;
@@ -2194,6 +2221,9 @@ static Value *SimplifyOrInst(Value *Op0, Value *Op1, const SimplifyQuery &Q,
   if (match(Op1, m_Not(m_c_And(m_Specific(Op0), m_Value()))))
     return Constant::getAllOnesValue(Op0->getType());
 
+  if (Value *V = simplifyLogicOfAddSub(Op0, Op1, Instruction::Or))
+    return V;
+
   Value *A, *B;
   // (A & ~B) | (A ^ B) -> (A ^ B)
   // (~B & A) | (A ^ B) -> (A ^ B)
@@ -2323,6 +2353,9 @@ static Value *SimplifyXorInst(Value *Op0, Value *Op1, const SimplifyQuery &Q,
       match(Op1, m_Not(m_Specific(Op0))))
     return Constant::getAllOnesValue(Op0->getType());
 
+  if (Value *V = simplifyLogicOfAddSub(Op0, Op1, Instruction::Xor))
+    return V;
+
   // Try some generic simplifications for associative operations.
   if (Value *V = SimplifyAssociativeBinOp(Instruction::Xor, Op0, Op1, Q,
                                           MaxRecurse))
@@ -5213,6 +5246,15 @@ static Value *simplifyUnaryIntrinsic(Function *F, Value *Op0,
     // bitreverse(bitreverse(x)) -> x
     if (match(Op0, m_BitReverse(m_Value(X)))) return X;
     break;
+  case Intrinsic::ctpop: {
+    // If everything but the lowest bit is zero, that bit is the pop-count. Ex:
+    // ctpop(and X, 1) --> and X, 1
+    unsigned BitWidth = Op0->getType()->getScalarSizeInBits();
+    if (MaskedValueIsZero(Op0, APInt::getHighBitsSet(BitWidth, BitWidth - 1),
+                          Q.DL, 0, Q.AC, Q.CxtI, Q.DT))
+      return Op0;
+    break;
+  }
   case Intrinsic::exp:
     // exp(log(x)) -> x
     if (Q.CxtI->hasAllowReassoc() &&
diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp
index a2f0bd872573e..aadb90d372f4b 100644
--- a/llvm/lib/Analysis/LazyValueInfo.cpp
+++ b/llvm/lib/Analysis/LazyValueInfo.cpp
@@ -1205,22 +1205,20 @@ getValueFromConditionImpl(Value *Val, Value *Cond, bool isTrueDest,
   // true dest path both of the conditions hold. Similarly for conditions of
   // the form (cond1 || cond2), we know that on the false dest path neither
   // condition holds.
-  BinaryOperator *BO = dyn_cast<BinaryOperator>(Cond);
-  if (!BO || (isTrueDest && BO->getOpcode() != BinaryOperator::And) ||
-             (!isTrueDest && BO->getOpcode() != BinaryOperator::Or))
+  Value *L, *R;
+  if (isTrueDest ? !match(Cond, m_LogicalAnd(m_Value(L), m_Value(R)))
+                 : !match(Cond, m_LogicalOr(m_Value(L), m_Value(R))))
     return ValueLatticeElement::getOverdefined();
 
   // Prevent infinite recursion if Cond references itself as in this example:
   //  Cond: "%tmp4 = and i1 %tmp4, undef"
   //    BL: "%tmp4 = and i1 %tmp4, undef"
   //    BR: "i1 undef"
-  Value *BL = BO->getOperand(0);
-  Value *BR = BO->getOperand(1);
-  if (BL == Cond || BR == Cond)
+  if (L == Cond || R == Cond)
     return ValueLatticeElement::getOverdefined();
 
-  return intersect(getValueFromCondition(Val, BL, isTrueDest, Visited),
-                   getValueFromCondition(Val, BR, isTrueDest, Visited));
+  return intersect(getValueFromCondition(Val, L, isTrueDest, Visited),
+                   getValueFromCondition(Val, R, isTrueDest, Visited));
 }
 
 static ValueLatticeElement
diff --git a/llvm/lib/Analysis/MemoryBuiltins.cpp b/llvm/lib/Analysis/MemoryBuiltins.cpp
index cbb54e8efdc08..5d82d9dd6ea01 100644
--- a/llvm/lib/Analysis/MemoryBuiltins.cpp
+++ b/llvm/lib/Analysis/MemoryBuiltins.cpp
@@ -566,8 +566,16 @@ Value *llvm::lowerObjectSizeCall(IntrinsicInst *ObjectSize,
       Value *UseZero =
           Builder.CreateICmpULT(SizeOffsetPair.first, SizeOffsetPair.second);
       ResultSize = Builder.CreateZExtOrTrunc(ResultSize, ResultType);
-      return Builder.CreateSelect(UseZero, ConstantInt::get(ResultType, 0),
-                                  ResultSize);
+      Value *Ret = Builder.CreateSelect(
+          UseZero, ConstantInt::get(ResultType, 0), ResultSize);
+
+      // The non-constant size expression cannot evaluate to -1.
+      if (!isa<Constant>(SizeOffsetPair.first) ||
+          !isa<Constant>(SizeOffsetPair.second))
+        Builder.CreateAssumption(
+            Builder.CreateICmpNE(Ret, ConstantInt::get(ResultType, -1)));
+
+      return Ret;
     }
   }
 
diff --git a/llvm/lib/Analysis/MemorySSA.cpp b/llvm/lib/Analysis/MemorySSA.cpp
index 00b4d42892c9b..c9ad9ffab16e7 100644
--- a/llvm/lib/Analysis/MemorySSA.cpp
+++ b/llvm/lib/Analysis/MemorySSA.cpp
@@ -2017,8 +2017,7 @@ void MemorySSA::verifyOrderingDominationAndDefUses(Function &F) const {
              "Incomplete MemoryPhi Node");
       for (unsigned I = 0, E = Phi->getNumIncomingValues(); I != E; ++I) {
         verifyUseInDefs(Phi->getIncomingValue(I), Phi);
-        assert(find(predecessors(&B), Phi->getIncomingBlock(I)) !=
-                   pred_end(&B) &&
+        assert(is_contained(predecessors(&B), Phi->getIncomingBlock(I)) &&
                "Incoming phi block not a block predecessor");
       }
 #endif
diff --git a/llvm/lib/Analysis/OptimizationRemarkEmitter.cpp b/llvm/lib/Analysis/OptimizationRemarkEmitter.cpp
index 385666a21d05d..6f3d4d536c401 100644
--- a/llvm/lib/Analysis/OptimizationRemarkEmitter.cpp
+++ b/llvm/lib/Analysis/OptimizationRemarkEmitter.cpp
@@ -37,7 +37,7 @@ OptimizationRemarkEmitter::OptimizationRemarkEmitter(const Function *F)
   LI.analyze(DT);
 
   // Then compute BranchProbabilityInfo.
-  BranchProbabilityInfo BPI(*F, LI);
+  BranchProbabilityInfo BPI(*F, LI, nullptr, &DT, nullptr);
 
   // Finally compute BFI.
   OwnedBFI = std::make_unique<BlockFrequencyInfo>(*F, BPI, LI);
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index eeb5058687035..0e32e7f4b1023 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -590,41 +590,30 @@ bool llvm::isValidAssumeForContext(const Instruction *Inv,
   return false;
 }
 
+static bool cmpExcludesZero(CmpInst::Predicate Pred, const Value *RHS) {
+  // v u> y implies v != 0.
+  if (Pred == ICmpInst::ICMP_UGT)
+    return true;
+
+  // Special-case v != 0 to also handle v != null.
+  if (Pred == ICmpInst::ICMP_NE)
+    return match(RHS, m_Zero());
+
+  // All other predicates - rely on generic ConstantRange handling.
+  const APInt *C;
+  if (!match(RHS, m_APInt(C)))
+    return false;
+
+  ConstantRange TrueValues = ConstantRange::makeExactICmpRegion(Pred, *C);
+  return !TrueValues.contains(APInt::getNullValue(C->getBitWidth()));
+}
+
 static bool isKnownNonZeroFromAssume(const Value *V, const Query &Q) {
   // Use of assumptions is context-sensitive. If we don't have a context, we
   // cannot use them!
   if (!Q.AC || !Q.CxtI)
     return false;
 
-  // Note that the patterns below need to be kept in sync with the code
-  // in AssumptionCache::updateAffectedValues.
-
-  auto CmpExcludesZero = [V](ICmpInst *Cmp) {
-    auto m_V = m_CombineOr(m_Specific(V), m_PtrToInt(m_Specific(V)));
-
-    Value *RHS;
-    CmpInst::Predicate Pred;
-    if (!match(Cmp, m_c_ICmp(Pred, m_V, m_Value(RHS))))
-      return false;
-    // assume(v u> y) -> assume(v != 0)
-    if (Pred == ICmpInst::ICMP_UGT)
-      return true;
-
-    // assume(v != 0)
-    // We special-case this one to ensure that we handle `assume(v != null)`.
-    if (Pred == ICmpInst::ICMP_NE)
-      return match(RHS, m_Zero());
-
-    // All other predicates - rely on generic ConstantRange handling.
-    ConstantInt *CI;
-    if (!match(RHS, m_ConstantInt(CI)))
-      return false;
-    ConstantRange RHSRange(CI->getValue());
-    ConstantRange TrueValues =
-        ConstantRange::makeAllowedICmpRegion(Pred, RHSRange);
-    return !TrueValues.contains(APInt::getNullValue(CI->getBitWidth()));
-  };
-
   if (Q.CxtI && V->getType()->isPointerTy()) {
     SmallVector<Attribute::AttrKind, 2> AttrKinds{Attribute::NonNull};
     if (!NullPointerIsDefined(Q.CxtI->getFunction(),
@@ -651,12 +640,13 @@ static bool isKnownNonZeroFromAssume(const Value *V, const Query &Q) {
     assert(I->getCalledFunction()->getIntrinsicID() == Intrinsic::assume &&
            "must be an assume intrinsic");
 
-    Value *Arg = I->getArgOperand(0);
-    ICmpInst *Cmp = dyn_cast<ICmpInst>(Arg);
-    if (!Cmp)
-      continue;
+    Value *RHS;
+    CmpInst::Predicate Pred;
+    auto m_V = m_CombineOr(m_Specific(V), m_PtrToInt(m_Specific(V)));
+    if (!match(I->getArgOperand(0), m_c_ICmp(Pred, m_V, m_Value(RHS))))
+      return false;
 
-    if (CmpExcludesZero(Cmp) && isValidAssumeForContext(I, Q.CxtI, Q.DT))
+    if (cmpExcludesZero(Pred, RHS) && isValidAssumeForContext(I, Q.CxtI, Q.DT))
       return true;
   }
 
@@ -2113,10 +2103,17 @@ static bool isKnownNonNullFromDominatingCondition(const Value *V,
     }
 
     // Consider only compare instructions uniquely controlling a branch
+    Value *RHS;
     CmpInst::Predicate Pred;
-    if (!match(const_cast<User *>(U),
-               m_c_ICmp(Pred, m_Specific(V), m_Zero())) ||
-        (Pred != ICmpInst::ICMP_EQ && Pred != ICmpInst::ICMP_NE))
+    if (!match(U, m_c_ICmp(Pred, m_Specific(V), m_Value(RHS))))
+      continue;
+
+    bool NonNullIfTrue;
+    if (cmpExcludesZero(Pred, RHS))
+      NonNullIfTrue = true;
+    else if (cmpExcludesZero(CmpInst::getInversePredicate(Pred), RHS))
+      NonNullIfTrue = false;
+    else
       continue;
 
     SmallVector<const User *, 4> WorkList;
@@ -2133,24 +2130,23 @@ static bool isKnownNonNullFromDominatingCondition(const Value *V,
         // propagate "pred != null" condition through AND because it is only
         // correct to assume that all conditions of AND are met in true branch.
         // TODO: Support similar logic of OR and EQ predicate?
-        if (Pred == ICmpInst::ICMP_NE)
-          if (auto *BO = dyn_cast<BinaryOperator>(Curr))
-            if (BO->getOpcode() == Instruction::And) {
-              for (auto *BOU : BO->users())
-                if (Visited.insert(BOU).second)
-                  WorkList.push_back(BOU);
-              continue;
-            }
+        if (NonNullIfTrue)
+          if (match(Curr, m_LogicalAnd(m_Value(), m_Value()))) {
+            for (auto *CurrU : Curr->users())
+              if (Visited.insert(CurrU).second)
+                WorkList.push_back(CurrU);
+            continue;
+          }
 
         if (const BranchInst *BI = dyn_cast<BranchInst>(Curr)) {
           assert(BI->isConditional() && "uses a comparison!");
 
           BasicBlock *NonNullSuccessor =
-              BI->getSuccessor(Pred == ICmpInst::ICMP_EQ ? 1 : 0);
+              BI->getSuccessor(NonNullIfTrue ? 0 : 1);
           BasicBlockEdge Edge(BI->getParent(), NonNullSuccessor);
           if (Edge.isSingleEdge() && DT->dominates(Edge, CtxI->getParent()))
             return true;
-        } else if (Pred == ICmpInst::ICMP_NE && isGuard(Curr) &&
+        } else if (NonNullIfTrue && isGuard(Curr) &&
                    DT->dominates(cast<Instruction>(Curr), CtxI)) {
           return true;
         }
@@ -2533,14 +2529,14 @@ static bool isKnownNonEqual(const Value *V1, const Value *V2, unsigned Depth,
         return isKnownNonEqual(O1->getOperand(0), O2->getOperand(0),
                                Depth + 1, Q);
       break;
-    case Instruction::Mul:
+    case Instruction::Mul: {
       // invertible if A * B == (A * B) mod 2^N where A, and B are integers
       // and N is the bitwdith.  The nsw case is non-obvious, but proven by
       // alive2: https://alive2.llvm.org/ce/z/Z6D5qK
-      if ((!cast<BinaryOperator>(O1)->hasNoUnsignedWrap() ||
-           !cast<BinaryOperator>(O2)->hasNoUnsignedWrap()) &&
-          (!cast<BinaryOperator>(O1)->hasNoSignedWrap() ||
-           !cast<BinaryOperator>(O2)->hasNoSignedWrap()))
+      auto *OBO1 = cast<OverflowingBinaryOperator>(O1);
+      auto *OBO2 = cast<OverflowingBinaryOperator>(O2);
+      if ((!OBO1->hasNoUnsignedWrap() || !OBO2->hasNoUnsignedWrap()) &&
+          (!OBO1->hasNoSignedWrap() || !OBO2->hasNoSignedWrap()))
         break;
 
       // Assume operand order has been canonicalized
@@ -2550,6 +2546,7 @@ static bool isKnownNonEqual(const Value *V1, const Value *V2, unsigned Depth,
         return isKnownNonEqual(O1->getOperand(0), O2->getOperand(0),
                                Depth + 1, Q);
       break;
+    }
     case Instruction::SExt:
     case Instruction::ZExt:
       if (O1->getOperand(0)->getType() == O2->getOperand(0)->getType())
@@ -6159,25 +6156,25 @@ static Optional<bool> isImpliedCondICmps(const ICmpInst *LHS,
 
 /// Return true if LHS implies RHS is true.  Return false if LHS implies RHS is
 /// false.  Otherwise, return None if we can't infer anything.  We expect the
-/// RHS to be an icmp and the LHS to be an 'and' or an 'or' instruction.
+/// RHS to be an icmp and the LHS to be an 'and', 'or', or a 'select' instruction.
 static Optional<bool>
-isImpliedCondAndOr(const BinaryOperator *LHS, CmpInst::Predicate RHSPred,
+isImpliedCondAndOr(const Instruction *LHS, CmpInst::Predicate RHSPred,
                    const Value *RHSOp0, const Value *RHSOp1,
-
                    const DataLayout &DL, bool LHSIsTrue, unsigned Depth) {
-  // The LHS must be an 'or' or an 'and' instruction.
+  // The LHS must be an 'or', 'and', or a 'select' instruction.
   assert((LHS->getOpcode() == Instruction::And ||
-          LHS->getOpcode() == Instruction::Or) &&
-         "Expected LHS to be 'and' or 'or'.");
+          LHS->getOpcode() == Instruction::Or ||
+          LHS->getOpcode() == Instruction::Select) &&
+         "Expected LHS to be 'and', 'or', or 'select'.");
 
   assert(Depth <= MaxAnalysisRecursionDepth && "Hit recursion limit");
 
   // If the result of an 'or' is false, then we know both legs of the 'or' are
   // false.  Similarly, if the result of an 'and' is true, then we know both
   // legs of the 'and' are true.
-  Value *ALHS, *ARHS;
-  if ((!LHSIsTrue && match(LHS, m_Or(m_Value(ALHS), m_Value(ARHS)))) ||
-      (LHSIsTrue && match(LHS, m_And(m_Value(ALHS), m_Value(ARHS))))) {
+  const Value *ALHS, *ARHS;
+  if ((!LHSIsTrue && match(LHS, m_LogicalOr(m_Value(ALHS), m_Value(ARHS)))) ||
+      (LHSIsTrue && match(LHS, m_LogicalAnd(m_Value(ALHS), m_Value(ARHS))))) {
     // FIXME: Make this non-recursion.
     if (Optional<bool> Implication = isImpliedCondition(
             ALHS, RHSPred, RHSOp0, RHSOp1, DL, LHSIsTrue, Depth + 1))
@@ -6218,13 +6215,14 @@ llvm::isImpliedCondition(const Value *LHS, CmpInst::Predicate RHSPred,
     return isImpliedCondICmps(LHSCmp, RHSPred, RHSOp0, RHSOp1, DL, LHSIsTrue,
                               Depth);
 
-  /// The LHS should be an 'or' or an 'and' instruction.  We expect the RHS to
-  /// be / an icmp. FIXME: Add support for and/or on the RHS.
-  const BinaryOperator *LHSBO = dyn_cast<BinaryOperator>(LHS);
-  if (LHSBO) {
-    if ((LHSBO->getOpcode() == Instruction::And ||
-         LHSBO->getOpcode() == Instruction::Or))
-      return isImpliedCondAndOr(LHSBO, RHSPred, RHSOp0, RHSOp1, DL, LHSIsTrue,
+  /// The LHS should be an 'or', 'and', or a 'select' instruction.  We expect
+  /// the RHS to be an icmp.
+  /// FIXME: Add support for and/or/select on the RHS.
+  if (const Instruction *LHSI = dyn_cast<Instruction>(LHS)) {
+    if ((LHSI->getOpcode() == Instruction::And ||
+         LHSI->getOpcode() == Instruction::Or ||
+         LHSI->getOpcode() == Instruction::Select))
+      return isImpliedCondAndOr(LHSI, RHSPred, RHSOp0, RHSOp1, DL, LHSIsTrue,
                                 Depth);
   }
   return None;
diff --git a/llvm/lib/CodeGen/Analysis.cpp b/llvm/lib/CodeGen/Analysis.cpp
index 45099cdaf46fd..cfd53bf531153 100644
--- a/llvm/lib/CodeGen/Analysis.cpp
+++ b/llvm/lib/CodeGen/Analysis.cpp
@@ -174,27 +174,6 @@ GlobalValue *llvm::ExtractTypeInfo(Value *V) {
   return GV;
 }
 
-/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
-/// processed uses a memory 'm' constraint.
-bool
-llvm::hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
-                                const TargetLowering &TLI) {
-  for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
-    InlineAsm::ConstraintInfo &CI = CInfos[i];
-    for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
-      TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
-      if (CType == TargetLowering::C_Memory)
-        return true;
-    }
-
-    // Indirect operand accesses access memory.
-    if (CI.isIndirect)
-      return true;
-  }
-
-  return false;
-}
-
 /// getFCmpCondCode - Return the ISD condition code corresponding to
 /// the given LLVM IR floating-point condition code.  This includes
 /// consideration of global floating-point math flags.
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
index 75b4a2831b0fa..6127c503404f7 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
@@ -2477,13 +2477,13 @@ void DwarfDebug::emitDebugLocValue(const AsmPrinter &AP, const DIBasicType *BT,
       DwarfExpr.addExpression(std::move(ExprCursor));
       return;
   } else if (Value.isConstantFP()) {
-    if (AP.getDwarfVersion() >= 4 && !AP.getDwarfDebug()->tuneForSCE()) {
+    if (AP.getDwarfVersion() >= 4 && !AP.getDwarfDebug()->tuneForSCE() &&
+        !ExprCursor) {
       DwarfExpr.addConstantFP(Value.getConstantFP()->getValueAPF(), AP);
       return;
-    } else if (Value.getConstantFP()
-                   ->getValueAPF()
-                   .bitcastToAPInt()
-                   .getBitWidth() <= 64 /*bits*/)
+    }
+    if (Value.getConstantFP()->getValueAPF().bitcastToAPInt().getBitWidth() <=
+        64 /*bits*/)
       DwarfExpr.addUnsignedConstant(
           Value.getConstantFP()->getValueAPF().bitcastToAPInt());
     else
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
index eb8f2013f0b28..502aef481a3a8 100644
--- a/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
+++ b/llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h
@@ -787,8 +787,7 @@ class DwarfDebug : public DebugHandlerBase {
   }
 
   unsigned getStringTypeLoc(const DIStringType *ST) const {
-    auto I = StringTypeLocMap.find(ST);
-    return I != StringTypeLocMap.end() ? I->second : 0;
+    return StringTypeLocMap.lookup(ST);
   }
 
   void addStringTypeLoc(const DIStringType *ST, unsigned Loc) {
diff --git a/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp
index 8fa83f5159109..354b638b47a2c 100644
--- a/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp
@@ -145,9 +145,10 @@ void OcamlGCMetadataPrinter::finishAssembly(Module &M, GCModuleInfo &Info,
       report_fatal_error("Function '" + FI.getFunction().getName() +
                          "' is too large for the ocaml GC! "
                          "Frame size " +
-                         Twine(FrameSize) + ">= 65536.\n"
-                                            "(" +
-                         Twine(uintptr_t(&FI)) + ")");
+                         Twine(FrameSize) +
+                         ">= 65536.\n"
+                         "(" +
+                         Twine(reinterpret_cast<uintptr_t>(&FI)) + ")");
     }
 
     AP.OutStreamer->AddComment("live roots for " +
diff --git a/llvm/lib/CodeGen/DwarfEHPrepare.cpp b/llvm/lib/CodeGen/DwarfEHPrepare.cpp
index c75c957bff8aa..c7048337cdf2e 100644
--- a/llvm/lib/CodeGen/DwarfEHPrepare.cpp
+++ b/llvm/lib/CodeGen/DwarfEHPrepare.cpp
@@ -235,6 +235,7 @@ bool DwarfEHPrepare::InsertUnwindResumeCalls(Function &Fn) {
     CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME));
 
     // We never expect _Unwind_Resume to return.
+    CI->setDoesNotReturn();
     new UnreachableInst(Ctx, UnwindBB);
     return true;
   }
@@ -260,6 +261,7 @@ bool DwarfEHPrepare::InsertUnwindResumeCalls(Function &Fn) {
   CI->setCallingConv(TLI->getLibcallCallingConv(RTLIB::UNWIND_RESUME));
 
   // We never expect _Unwind_Resume to return.
+  CI->setDoesNotReturn();
   new UnreachableInst(Ctx, UnwindBB);
   return true;
 }
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 79f74a47d83c8..abc23da3d418b 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -1029,8 +1029,7 @@ static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) {
   unsigned NumBits = Ty.getScalarSizeInBits();
   auto ValVRegAndVal = getConstantVRegValWithLookThrough(Val, MRI);
   if (!Ty.isVector() && ValVRegAndVal) {
-    unsigned KnownVal = ValVRegAndVal->Value;
-    APInt Scalar = APInt(8, KnownVal);
+    APInt Scalar = ValVRegAndVal->Value.truncOrSelf(8);
     APInt SplatVal = APInt::getSplat(NumBits, Scalar);
     return MIB.buildConstant(Ty, SplatVal).getReg(0);
   }
@@ -1411,7 +1410,7 @@ bool CombinerHelper::tryCombineMemCpyFamily(MachineInstr &MI, unsigned MaxLen) {
   auto LenVRegAndVal = getConstantVRegValWithLookThrough(Len, MRI);
   if (!LenVRegAndVal)
     return false; // Leave it to the legalizer to lower it to a libcall.
-  unsigned KnownLen = LenVRegAndVal->Value;
+  unsigned KnownLen = LenVRegAndVal->Value.getZExtValue();
 
   if (KnownLen == 0) {
     MI.eraseFromParent();
@@ -1521,7 +1520,7 @@ bool CombinerHelper::matchPtrAddImmedChain(MachineInstr &MI,
     return false;
 
   // Pass the combined immediate to the apply function.
-  MatchInfo.Imm = MaybeImmVal->Value + MaybeImm2Val->Value;
+  MatchInfo.Imm = (MaybeImmVal->Value + MaybeImm2Val->Value).getSExtValue();
   MatchInfo.Base = Base;
   return true;
 }
@@ -1571,7 +1570,8 @@ bool CombinerHelper::matchShiftImmedChain(MachineInstr &MI,
     return false;
 
   // Pass the combined immediate to the apply function.
-  MatchInfo.Imm = MaybeImmVal->Value + MaybeImm2Val->Value;
+  MatchInfo.Imm =
+      (MaybeImmVal->Value.getSExtValue() + MaybeImm2Val->Value).getSExtValue();
   MatchInfo.Reg = Base;
 
   // There is no simple replacement for a saturating unsigned left shift that
@@ -1654,7 +1654,7 @@ bool CombinerHelper::matchShiftOfShiftedLogic(MachineInstr &MI,
   if (!MaybeImmVal)
     return false;
 
-  const uint64_t C1Val = MaybeImmVal->Value;
+  const uint64_t C1Val = MaybeImmVal->Value.getZExtValue();
 
   auto matchFirstShift = [&](const MachineInstr *MI, uint64_t &ShiftVal) {
     // Shift should match previous one and should be a one-use.
@@ -1668,7 +1668,7 @@ bool CombinerHelper::matchShiftOfShiftedLogic(MachineInstr &MI,
     if (!MaybeImmVal)
       return false;
 
-    ShiftVal = MaybeImmVal->Value;
+    ShiftVal = MaybeImmVal->Value.getSExtValue();
     return true;
   };
 
@@ -1738,10 +1738,11 @@ bool CombinerHelper::matchCombineMulToShl(MachineInstr &MI,
   assert(MI.getOpcode() == TargetOpcode::G_MUL && "Expected a G_MUL");
   auto MaybeImmVal =
       getConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI);
-  if (!MaybeImmVal || !isPowerOf2_64(MaybeImmVal->Value))
+  if (!MaybeImmVal)
     return false;
-  ShiftVal = Log2_64(MaybeImmVal->Value);
-  return true;
+
+  ShiftVal = MaybeImmVal->Value.exactLogBase2();
+  return (static_cast<int32_t>(ShiftVal) != -1);
 }
 
 bool CombinerHelper::applyCombineMulToShl(MachineInstr &MI,
@@ -1787,7 +1788,7 @@ bool CombinerHelper::matchCombineShlOfExtend(MachineInstr &MI,
       return false;
   }
 
-  int64_t ShiftAmt = MaybeShiftAmtVal->Value;
+  int64_t ShiftAmt = MaybeShiftAmtVal->Value.getSExtValue();
   MatchData.Reg = ExtSrc;
   MatchData.Imm = ShiftAmt;
 
@@ -2026,7 +2027,7 @@ bool CombinerHelper::matchCombineShiftToUnmerge(MachineInstr &MI,
   if (!MaybeImmVal)
     return false;
 
-  ShiftVal = MaybeImmVal->Value;
+  ShiftVal = MaybeImmVal->Value.getSExtValue();
   return ShiftVal >= Size / 2 && ShiftVal < Size;
 }
 
@@ -2200,7 +2201,7 @@ bool CombinerHelper::matchCombineConstPtrAddToI2P(MachineInstr &MI,
   Register RHS = MI.getOperand(2).getReg();
   MachineRegisterInfo &MRI = Builder.getMF().getRegInfo();
 
-  if (auto RHSCst = getConstantVRegVal(RHS, MRI)) {
+  if (auto RHSCst = getConstantVRegSExtVal(RHS, MRI)) {
     int64_t Cst;
     if (mi_match(LHS, MRI, m_GIntToPtr(m_ICst(Cst)))) {
       NewCst = Cst + *RHSCst;
@@ -2441,7 +2442,7 @@ bool CombinerHelper::matchConstantSelectCmp(MachineInstr &MI, unsigned &OpIdx) {
   assert(MI.getOpcode() == TargetOpcode::G_SELECT);
   if (auto MaybeCstCmp =
           getConstantVRegValWithLookThrough(MI.getOperand(1).getReg(), MRI)) {
-    OpIdx = MaybeCstCmp->Value ? 2 : 3;
+    OpIdx = MaybeCstCmp->Value.isNullValue() ? 3 : 2;
     return true;
   }
   return false;
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
index 2fedc034d315f..3eca16808ea61 100644
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
@@ -50,7 +50,7 @@ bool InstructionSelector::isOperandImmEqual(
     const MachineRegisterInfo &MRI) const {
   if (MO.isReg() && MO.getReg())
     if (auto VRegVal = getConstantVRegValWithLookThrough(MO.getReg(), MRI))
-      return VRegVal->Value == Value;
+      return VRegVal->Value.getSExtValue() == Value;
   return false;
 }
 
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp b/llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
index 9ca6d9a9a5517..1993f6033291e 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp
@@ -57,11 +57,10 @@ LegalityPredicate LegalityPredicates::typePairAndMemDescInSet(
     TypePairAndMemDesc Match = {Query.Types[TypeIdx0], Query.Types[TypeIdx1],
                                 Query.MMODescrs[MMOIdx].SizeInBits,
                                 Query.MMODescrs[MMOIdx].AlignInBits};
-    return std::find_if(
-      TypesAndMemDesc.begin(), TypesAndMemDesc.end(),
-      [=](const TypePairAndMemDesc &Entry) ->bool {
-        return Match.isCompatible(Entry);
-      }) != TypesAndMemDesc.end();
+    return llvm::any_of(TypesAndMemDesc,
+                        [=](const TypePairAndMemDesc &Entry) -> bool {
+                          return Match.isCompatible(Entry);
+                        });
   };
 }
 
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 4d9580de3b7bb..c19ee2e3860fd 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -255,8 +255,8 @@ void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
   reportGISelFailure(MF, TPC, MORE, R);
 }
 
-Optional<int64_t> llvm::getConstantVRegVal(Register VReg,
-                                           const MachineRegisterInfo &MRI) {
+Optional<APInt> llvm::getConstantVRegVal(Register VReg,
+                                         const MachineRegisterInfo &MRI) {
   Optional<ValueAndVReg> ValAndVReg =
       getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false);
   assert((!ValAndVReg || ValAndVReg->VReg == VReg) &&
@@ -266,6 +266,14 @@ Optional<int64_t> llvm::getConstantVRegVal(Register VReg,
   return ValAndVReg->Value;
 }
 
+Optional<int64_t> llvm::getConstantVRegSExtVal(Register VReg,
+                                               const MachineRegisterInfo &MRI) {
+  Optional<APInt> Val = getConstantVRegVal(VReg, MRI);
+  if (Val && Val->getBitWidth() <= 64)
+    return Val->getSExtValue();
+  return None;
+}
+
 Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough(
     Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
     bool HandleFConstant) {
@@ -337,10 +345,7 @@ Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough(
     }
   }
 
-  if (Val.getBitWidth() > 64)
-    return None;
-
-  return ValueAndVReg{Val.getSExtValue(), VReg};
+  return ValueAndVReg{Val, VReg};
 }
 
 const ConstantFP *
@@ -413,9 +418,8 @@ Optional<APInt> llvm::ConstantFoldBinOp(unsigned Opcode, const Register Op1,
   if (!MaybeOp1Cst)
     return None;
 
-  LLT Ty = MRI.getType(Op1);
-  APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true);
-  APInt C2(Ty.getSizeInBits(), *MaybeOp2Cst, true);
+  const APInt &C1 = *MaybeOp1Cst;
+  const APInt &C2 = *MaybeOp2Cst;
   switch (Opcode) {
   default:
     break;
@@ -535,13 +539,13 @@ Optional<APInt> llvm::ConstantFoldExtOp(unsigned Opcode, const Register Op1,
                                         const MachineRegisterInfo &MRI) {
   auto MaybeOp1Cst = getConstantVRegVal(Op1, MRI);
   if (MaybeOp1Cst) {
-    LLT Ty = MRI.getType(Op1);
-    APInt C1(Ty.getSizeInBits(), *MaybeOp1Cst, true);
     switch (Opcode) {
     default:
       break;
-    case TargetOpcode::G_SEXT_INREG:
-      return C1.trunc(Imm).sext(C1.getBitWidth());
+    case TargetOpcode::G_SEXT_INREG: {
+      LLT Ty = MRI.getType(Op1);
+      return MaybeOp1Cst->trunc(Imm).sext(Ty.getScalarSizeInBits());
+    }
     }
   }
   return None;
diff --git a/llvm/lib/CodeGen/LiveRangeEdit.cpp b/llvm/lib/CodeGen/LiveRangeEdit.cpp
index dbf02802d4735..037cb54262356 100644
--- a/llvm/lib/CodeGen/LiveRangeEdit.cpp
+++ b/llvm/lib/CodeGen/LiveRangeEdit.cpp
@@ -435,7 +435,7 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead,
     if (!SplitLIs.empty())
       ++NumFracRanges;
 
-    unsigned Original = VRM ? VRM->getOriginal(VReg) : 0;
+    Register Original = VRM ? VRM->getOriginal(VReg) : Register();
     for (const LiveInterval *SplitLI : SplitLIs) {
       // If LI is an original interval that hasn't been split yet, make the new
       // intervals their own originals instead of referring to LI. The original
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 5ba896b7037cb..43eaf86e50a67 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -369,10 +369,7 @@ static void initSlots2Values(const Function &F,
 const Value* PerFunctionMIParsingState::getIRValue(unsigned Slot) {
   if (Slots2Values.empty())
     initSlots2Values(MF.getFunction(), Slots2Values);
-  auto ValueInfo = Slots2Values.find(Slot);
-  if (ValueInfo == Slots2Values.end())
-    return nullptr;
-  return ValueInfo->second;
+  return Slots2Values.lookup(Slot);
 }
 
 namespace {
@@ -3169,10 +3166,7 @@ static void initSlots2BasicBlocks(
 static const BasicBlock *getIRBlockFromSlot(
     unsigned Slot,
     const DenseMap<unsigned, const BasicBlock *> &Slots2BasicBlocks) {
-  auto BlockInfo = Slots2BasicBlocks.find(Slot);
-  if (BlockInfo == Slots2BasicBlocks.end())
-    return nullptr;
-  return BlockInfo->second;
+  return Slots2BasicBlocks.lookup(Slot);
 }
 
 const BasicBlock *MIParser::getIRBlock(unsigned Slot) {
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 25f785342d04c..eae174019b562 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -415,7 +415,7 @@ void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
     YamlObject.ID = ID;
     if (const auto *Alloca = MFI.getObjectAllocation(I))
       YamlObject.Name.Value = std::string(
-          Alloca->hasName() ? Alloca->getName() : "<unnamed alloca>");
+          Alloca->hasName() ? Alloca->getName() : "");
     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
                           ? yaml::MachineStackObject::SpillSlot
                           : MFI.isVariableSizedObjectIndex(I)
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 0278999a8f724..14a270f994b4a 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -71,7 +71,10 @@ MCSymbol *MachineBasicBlock::getSymbol() const {
       } else if (SectionID == MBBSectionID::ExceptionSectionID) {
         Suffix += ".eh";
       } else {
-        Suffix += "." + std::to_string(SectionID.Number);
+        // For symbols that represent basic block sections, we add ".__part." to
+        // allow tools like symbolizers to know that this represents a part of
+        // the original function.
+        Suffix = (Suffix + Twine(".__part.") + Twine(SectionID.Number)).str();
       }
       CachedMCSymbol = Ctx.getOrCreateSymbol(MF->getName() + Suffix);
     } else {
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index bc7bb66a82fb6..7c356cf0e15b0 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -800,8 +800,13 @@ void MachineLICMBase::SinkIntoLoop() {
        I != Preheader->instr_end(); ++I) {
     // We need to ensure that we can safely move this instruction into the loop.
     // As such, it must not have side-effects, e.g. such as a call has.
-    if (IsLoopInvariantInst(*I) && !HasLoopPHIUse(&*I))
+    LLVM_DEBUG(dbgs() << "LICM: Analysing sink candidate: " << *I);
+    if (IsLoopInvariantInst(*I) && !HasLoopPHIUse(&*I)) {
+      LLVM_DEBUG(dbgs() << "LICM: Added as sink candidate.\n");
       Candidates.push_back(&*I);
+      continue;
+    }
+    LLVM_DEBUG(dbgs() << "LICM: Not added as sink candidate.\n");
   }
 
   for (MachineInstr *I : Candidates) {
@@ -811,8 +816,11 @@ void MachineLICMBase::SinkIntoLoop() {
     if (!MRI->hasOneDef(MO.getReg()))
       continue;
     bool CanSink = true;
-    MachineBasicBlock *B = nullptr;
+    MachineBasicBlock *SinkBlock = nullptr;
+    LLVM_DEBUG(dbgs() << "LICM: Try sinking: " << *I);
+
     for (MachineInstr &MI : MRI->use_instructions(MO.getReg())) {
+      LLVM_DEBUG(dbgs() << "LICM:    Analysing use: "; MI.dump());
       // FIXME: Come up with a proper cost model that estimates whether sinking
       // the instruction (and thus possibly executing it on every loop
       // iteration) is more expensive than a register.
@@ -821,24 +829,40 @@ void MachineLICMBase::SinkIntoLoop() {
         CanSink = false;
         break;
       }
-      if (!B) {
-        B = MI.getParent();
+      if (!SinkBlock) {
+        SinkBlock = MI.getParent();
+        LLVM_DEBUG(dbgs() << "LICM:   Setting sink block to: "
+                          << printMBBReference(*SinkBlock) << "\n");
         continue;
       }
-      B = DT->findNearestCommonDominator(B, MI.getParent());
-      if (!B) {
+      SinkBlock = DT->findNearestCommonDominator(SinkBlock, MI.getParent());
+      if (!SinkBlock) {
+        LLVM_DEBUG(dbgs() << "LICM:   Can't find nearest dominator\n");
         CanSink = false;
         break;
       }
+      LLVM_DEBUG(dbgs() << "LICM:   Setting nearest common dom block: " <<
+                 printMBBReference(*SinkBlock) << "\n");
+    }
+    if (!CanSink) {
+      LLVM_DEBUG(dbgs() << "LICM: Can't sink instruction.\n");
+      continue;
     }
-    if (!CanSink || !B || B == Preheader)
+    if (!SinkBlock) {
+      LLVM_DEBUG(dbgs() << "LICM: Not sinking, can't find sink block.\n");
       continue;
+    }
+    if (SinkBlock == Preheader) {
+      LLVM_DEBUG(dbgs() << "LICM: Not sinking, sink block is the preheader\n");
+      continue;
+    }
 
-    LLVM_DEBUG(dbgs() << "Sinking to " << printMBBReference(*B) << " from "
-                      << printMBBReference(*I->getParent()) << ": " << *I);
-    B->splice(B->getFirstNonPHI(), Preheader, I);
+    LLVM_DEBUG(dbgs() << "LICM: Sinking to " << printMBBReference(*SinkBlock)
+                      << " from " << printMBBReference(*I->getParent())
+                      << ": " << *I);
+    SinkBlock->splice(SinkBlock->getFirstNonPHI(), Preheader, I);
 
-    // The instruction is is moved from its basic block, so do not retain the
+    // The instruction is moved from its basic block, so do not retain the
     // debug information.
     assert(!I->isDebugInstr() && "Should not sink debug inst");
     I->setDebugLoc(DebugLoc());
@@ -1028,6 +1052,7 @@ bool MachineLICMBase::IsLICMCandidate(MachineInstr &I) {
   bool DontMoveAcrossStore = true;
   if ((!I.isSafeToMove(AA, DontMoveAcrossStore)) &&
       !(HoistConstStores && isInvariantStore(I, TRI, MRI))) {
+    LLVM_DEBUG(dbgs() << "LICM: Instruction not safe to move.\n");
     return false;
   }
 
@@ -1038,8 +1063,10 @@ bool MachineLICMBase::IsLICMCandidate(MachineInstr &I) {
   // indexed load from a jump table.
   // Stores and side effects are already checked by isSafeToMove.
   if (I.mayLoad() && !mayLoadFromGOTOrConstantPool(I) &&
-      !IsGuaranteedToExecute(I.getParent()))
+      !IsGuaranteedToExecute(I.getParent())) {
+    LLVM_DEBUG(dbgs() << "LICM: Load not guaranteed to execute.\n");
     return false;
+  }
 
   // Convergent attribute has been used on operations that involve inter-thread
   // communication which results are implicitly affected by the enclosing
@@ -1056,8 +1083,10 @@ bool MachineLICMBase::IsLICMCandidate(MachineInstr &I) {
 /// physical registers aren't accessed explicitly, and there are no side
 /// effects that aren't captured by the operands or other flags.
 bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I) {
-  if (!IsLICMCandidate(I))
+  if (!IsLICMCandidate(I)) {
+    LLVM_DEBUG(dbgs() << "LICM: Instruction not a LICM candidate\n");
     return false;
+  }
 
   // The instruction is loop invariant if all of its operands are.
   for (const MachineOperand &MO : I.operands()) {
diff --git a/llvm/lib/CodeGen/MachineModuleInfo.cpp b/llvm/lib/CodeGen/MachineModuleInfo.cpp
index f75acbb2494b5..5c2e2fb16b691 100644
--- a/llvm/lib/CodeGen/MachineModuleInfo.cpp
+++ b/llvm/lib/CodeGen/MachineModuleInfo.cpp
@@ -104,7 +104,8 @@ ArrayRef<MCSymbol *> MMIAddrLabelMap::getAddrLabelSymbolToEmit(BasicBlock *BB) {
   BBCallbacks.back().setMap(this);
   Entry.Index = BBCallbacks.size() - 1;
   Entry.Fn = BB->getParent();
-  MCSymbol *Sym = Context.createTempSymbol(!BB->hasAddressTaken());
+  MCSymbol *Sym = BB->hasAddressTaken() ? Context.createNamedTempSymbol()
+                                        : Context.createTempSymbol();
   Entry.Symbols.push_back(Sym);
   return Entry.Symbols;
 }
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 0abdf897b319f..265ca6dcb894b 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -79,6 +79,18 @@ static cl::opt<unsigned> SplitEdgeProbabilityThreshold(
         "splitted critical edge"),
     cl::init(40), cl::Hidden);
 
+static cl::opt<unsigned> SinkLoadInstsPerBlockThreshold(
+    "machine-sink-load-instrs-threshold",
+    cl::desc("Do not try to find alias store for a load if there is a in-path "
+             "block whose instruction number is higher than this threshold."),
+    cl::init(2000), cl::Hidden);
+
+static cl::opt<unsigned> SinkLoadBlocksThreshold(
+    "machine-sink-load-blocks-threshold",
+    cl::desc("Do not try to find alias store for a load if the block number in "
+             "the straight line is higher than this threshold."),
+    cl::init(20), cl::Hidden);
+
 STATISTIC(NumSunk,      "Number of machine instructions sunk");
 STATISTIC(NumSplit,     "Number of critical edges split");
 STATISTIC(NumCoalesces, "Number of copies coalesced");
@@ -1020,6 +1032,7 @@ bool MachineSinking::hasStoreBetween(MachineBasicBlock *From,
   bool SawStore = false;
   bool HasAliasedStore = false;
   DenseSet<MachineBasicBlock *> HandledBlocks;
+  DenseSet<MachineBasicBlock *> HandledDomBlocks;
   // Go through all reachable blocks from From.
   for (MachineBasicBlock *BB : depth_first(From)) {
     // We insert the instruction at the start of block To, so no need to worry
@@ -1036,10 +1049,33 @@ bool MachineSinking::hasStoreBetween(MachineBasicBlock *From,
     HandledBlocks.insert(BB);
     // To post dominates BB, it must be a path from block From.
     if (PDT->dominates(To, BB)) {
+      if (!HandledDomBlocks.count(BB))
+        HandledDomBlocks.insert(BB);
+
+      // If this BB is too big or the block number in straight line between From
+      // and To is too big, stop searching to save compiling time.
+      if (BB->size() > SinkLoadInstsPerBlockThreshold ||
+          HandledDomBlocks.size() > SinkLoadBlocksThreshold) {
+        for (auto *DomBB : HandledDomBlocks) {
+          if (DomBB != BB && DT->dominates(DomBB, BB))
+            HasStoreCache[std::make_pair(DomBB, To)] = true;
+          else if(DomBB != BB && DT->dominates(BB, DomBB))
+            HasStoreCache[std::make_pair(From, DomBB)] = true;
+        }
+        HasStoreCache[BlockPair] = true;
+        return true;
+      }
+
       for (MachineInstr &I : *BB) {
         // Treat as alias conservatively for a call or an ordered memory
         // operation.
         if (I.isCall() || I.hasOrderedMemoryRef()) {
+          for (auto *DomBB : HandledDomBlocks) {
+            if (DomBB != BB && DT->dominates(DomBB, BB))
+              HasStoreCache[std::make_pair(DomBB, To)] = true;
+            else if(DomBB != BB && DT->dominates(BB, DomBB))
+              HasStoreCache[std::make_pair(From, DomBB)] = true;
+          }
           HasStoreCache[BlockPair] = true;
           return true;
         }
diff --git a/llvm/lib/CodeGen/MultiHazardRecognizer.cpp b/llvm/lib/CodeGen/MultiHazardRecognizer.cpp
index d66110ba3ac07..e4cd92ac4868e 100644
--- a/llvm/lib/CodeGen/MultiHazardRecognizer.cpp
+++ b/llvm/lib/CodeGen/MultiHazardRecognizer.cpp
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/MultiHazardRecognizer.h"
+#include "llvm/ADT/STLExtras.h"
 #include <algorithm>
 #include <functional>
 #include <numeric>
@@ -25,8 +26,8 @@ void MultiHazardRecognizer::AddHazardRecognizer(
 }
 
 bool MultiHazardRecognizer::atIssueLimit() const {
-  return std::any_of(Recognizers.begin(), Recognizers.end(),
-                     std::mem_fn(&ScheduleHazardRecognizer::atIssueLimit));
+  return llvm::any_of(Recognizers,
+                      std::mem_fn(&ScheduleHazardRecognizer::atIssueLimit));
 }
 
 ScheduleHazardRecognizer::HazardType
@@ -72,7 +73,7 @@ bool MultiHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
   auto SPA = [=](std::unique_ptr<ScheduleHazardRecognizer> &R) {
     return R->ShouldPreferAnother(SU);
   };
-  return std::any_of(Recognizers.begin(), Recognizers.end(), SPA);
+  return llvm::any_of(Recognizers, SPA);
 }
 
 void MultiHazardRecognizer::AdvanceCycle() {
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 74d3e1adcd6cc..92b23df9e3afa 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10721,8 +10721,18 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
       (!LegalOperations || (TLI.isOperationLegal(ISD::ZERO_EXTEND, VT) &&
                             TLI.isOperationLegal(ISD::ADD, VT)))) {
     // If we can eliminate the 'not', the sext form should be better
-    if (SDValue NewXor = visitXOR(N0.getNode()))
-      return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, NewXor);
+    if (SDValue NewXor = visitXOR(N0.getNode())) {
+      // Returning N0 is a form of in-visit replacement that may have
+      // invalidated N0.
+      if (NewXor.getNode() == N0.getNode()) {
+        // Return SDValue here as the xor should have already been replaced in
+        // this sext.
+        return SDValue();
+      } else {
+        // Return a new sext with the new xor.
+        return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, NewXor);
+      }
+    }
 
     SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
     return DAG.getNode(ISD::ADD, DL, VT, Zext, DAG.getAllOnesConstant(DL, VT));
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index f21ec1dbdfe5f..57cb364f1939a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -4044,10 +4044,13 @@ SDValue DAGTypeLegalizer::WidenVecRes_MGATHER(MaskedGatherSDNode *N) {
   Index = ModifyToType(Index, WideIndexVT);
   SDValue Ops[] = { N->getChain(), PassThru, Mask, N->getBasePtr(), Index,
                     Scale };
+
+  // Widen the MemoryType
+  EVT WideMemVT = EVT::getVectorVT(*DAG.getContext(),
+                                   N->getMemoryVT().getScalarType(), NumElts);
   SDValue Res = DAG.getMaskedGather(DAG.getVTList(WideVT, MVT::Other),
-                                    N->getMemoryVT(), dl, Ops,
-                                    N->getMemOperand(), N->getIndexType(),
-                                    N->getExtensionType());
+                                    WideMemVT, dl, Ops, N->getMemOperand(),
+                                    N->getIndexType(), N->getExtensionType());
 
   // Legalize the chain result - switch anything that used the old chain to
   // use the new one.
@@ -4881,6 +4884,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
   SDValue Mask = MSC->getMask();
   SDValue Index = MSC->getIndex();
   SDValue Scale = MSC->getScale();
+  EVT WideMemVT = MSC->getMemoryVT();
 
   if (OpNo == 1) {
     DataOp = GetWidenedVector(DataOp);
@@ -4897,6 +4901,10 @@ SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
     EVT WideMaskVT = EVT::getVectorVT(*DAG.getContext(),
                                       MaskVT.getVectorElementType(), NumElts);
     Mask = ModifyToType(Mask, WideMaskVT, true);
+
+    // Widen the MemoryType
+    WideMemVT = EVT::getVectorVT(*DAG.getContext(),
+                                 MSC->getMemoryVT().getScalarType(), NumElts);
   } else if (OpNo == 4) {
     // Just widen the index. It's allowed to have extra elements.
     Index = GetWidenedVector(Index);
@@ -4905,9 +4913,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_MSCATTER(SDNode *N, unsigned OpNo) {
 
   SDValue Ops[] = {MSC->getChain(), DataOp, Mask, MSC->getBasePtr(), Index,
                    Scale};
-  return DAG.getMaskedScatter(DAG.getVTList(MVT::Other),
-                              MSC->getMemoryVT(), SDLoc(N), Ops,
-                              MSC->getMemOperand(), MSC->getIndexType(),
+  return DAG.getMaskedScatter(DAG.getVTList(MVT::Other), WideMemVT, SDLoc(N),
+                              Ops, MSC->getMemOperand(), MSC->getIndexType(),
                               MSC->isTruncatingStore());
 }
 
diff --git a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
index 2d2eb252e4e28..65ad5b0b5d8f2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
@@ -546,6 +546,18 @@ lowerStatepointMetaArgs(SmallVectorImpl<SDValue> &Ops,
   // Decide which deriver pointers will go on VRegs
   unsigned MaxVRegPtrs = MaxRegistersForGCPointers.getValue();
 
+  // Pointers used on exceptional path of invoke statepoint.
+  // We cannot assing them to VRegs.
+  SmallSet<SDValue, 8> LPadPointers;
+  if (auto *StInvoke = dyn_cast_or_null<InvokeInst>(SI.StatepointInstr)) {
+    LandingPadInst *LPI = StInvoke->getLandingPadInst();
+    for (auto *Relocate : SI.GCRelocates)
+      if (Relocate->getOperand(0) == LPI) {
+        LPadPointers.insert(Builder.getValue(Relocate->getBasePtr()));
+        LPadPointers.insert(Builder.getValue(Relocate->getDerivedPtr()));
+      }
+  }
+
   LLVM_DEBUG(dbgs() << "Deciding how to lower GC Pointers:\n");
 
   // List of unique lowered GC Pointer values.
@@ -555,6 +567,14 @@ lowerStatepointMetaArgs(SmallVectorImpl<SDValue> &Ops,
 
   unsigned CurNumVRegs = 0;
 
+  auto canPassGCPtrOnVReg = [&](SDValue SD) {
+    if (SD.getValueType().isVector())
+      return false;
+    if (LPadPointers.count(SD))
+      return false;
+    return !willLowerDirectly(SD);
+  };
+
   auto processGCPtr = [&](const Value *V) {
     SDValue PtrSD = Builder.getValue(V);
     if (!LoweredGCPtrs.insert(PtrSD))
@@ -564,7 +584,9 @@ lowerStatepointMetaArgs(SmallVectorImpl<SDValue> &Ops,
     assert(!LowerAsVReg.count(PtrSD) && "must not have been seen");
     if (LowerAsVReg.size() == MaxVRegPtrs)
       return;
-    if (willLowerDirectly(PtrSD) || V->getType()->isVectorTy()) {
+    assert(V->getType()->isVectorTy() == PtrSD.getValueType().isVector() &&
+           "IR and SD types disagree");
+    if (!canPassGCPtrOnVReg(PtrSD)) {
       LLVM_DEBUG(dbgs() << "direct/spill "; PtrSD.dump(&Builder.DAG));
       return;
     }
diff --git a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
index 7ed8a718ed3c1..c1e27410ce329 100644
--- a/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
+++ b/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
@@ -57,13 +57,6 @@ namespace {
 template <class ELFT> class DyldELFObject : public ELFObjectFile<ELFT> {
   LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
 
-  typedef Elf_Shdr_Impl<ELFT> Elf_Shdr;
-  typedef Elf_Sym_Impl<ELFT> Elf_Sym;
-  typedef Elf_Rel_Impl<ELFT, false> Elf_Rel;
-  typedef Elf_Rel_Impl<ELFT, true> Elf_Rela;
-
-  typedef Elf_Ehdr_Impl<ELFT> Elf_Ehdr;
-
   typedef typename ELFT::uint addr_type;
 
   DyldELFObject(ELFObjectFile<ELFT> &&Obj);
diff --git a/llvm/lib/ExecutionEngine/SectionMemoryManager.cpp b/llvm/lib/ExecutionEngine/SectionMemoryManager.cpp
index 138b18a1ddcb0..6690dd07d99b2 100644
--- a/llvm/lib/ExecutionEngine/SectionMemoryManager.cpp
+++ b/llvm/lib/ExecutionEngine/SectionMemoryManager.cpp
@@ -218,11 +218,9 @@ SectionMemoryManager::applyMemoryGroupPermissions(MemoryGroup &MemGroup,
   }
 
   // Remove all blocks which are now empty
-  MemGroup.FreeMem.erase(remove_if(MemGroup.FreeMem,
-                                   [](FreeMemBlock &FreeMB) {
-                                     return FreeMB.Free.allocatedSize() == 0;
-                                   }),
-                         MemGroup.FreeMem.end());
+  erase_if(MemGroup.FreeMem, [](FreeMemBlock &FreeMB) {
+    return FreeMB.Free.allocatedSize() == 0;
+  });
 
   return std::error_code();
 }
diff --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp
index b7a9beeeeb1a5..5eeba0c0c3e70 100644
--- a/llvm/lib/Linker/IRMover.cpp
+++ b/llvm/lib/Linker/IRMover.cpp
@@ -905,7 +905,7 @@ IRLinker::linkAppendingVarProto(GlobalVariable *DstGV,
   getArrayElements(SrcGV->getInitializer(), SrcElements);
 
   if (IsNewStructor) {
-    auto It = remove_if(SrcElements, [this](Constant *E) {
+    erase_if(SrcElements, [this](Constant *E) {
       auto *Key =
           dyn_cast<GlobalValue>(E->getAggregateElement(2)->stripPointerCasts());
       if (!Key)
@@ -913,7 +913,6 @@ IRLinker::linkAppendingVarProto(GlobalVariable *DstGV,
       GlobalValue *DGV = getLinkedToGlobal(Key);
       return !shouldLink(DGV, *Key);
     });
-    SrcElements.erase(It, SrcElements.end());
   }
   uint64_t NewSize = DstNumElements + SrcElements.size();
   ArrayType *NewType = ArrayType::get(EltTy, NewSize);
diff --git a/llvm/lib/MC/MCContext.cpp b/llvm/lib/MC/MCContext.cpp
index d054c93e37f48..9dab8a6c09101 100644
--- a/llvm/lib/MC/MCContext.cpp
+++ b/llvm/lib/MC/MCContext.cpp
@@ -232,11 +232,16 @@ MCSymbol *MCContext::createSymbol(StringRef Name, bool AlwaysAddSuffix,
   llvm_unreachable("Infinite loop");
 }
 
-MCSymbol *MCContext::createTempSymbol(const Twine &Name, bool AlwaysAddSuffix,
-                                      bool CanBeUnnamed) {
+MCSymbol *MCContext::createTempSymbol(const Twine &Name, bool AlwaysAddSuffix) {
   SmallString<128> NameSV;
   raw_svector_ostream(NameSV) << MAI->getPrivateGlobalPrefix() << Name;
-  return createSymbol(NameSV, AlwaysAddSuffix, CanBeUnnamed);
+  return createSymbol(NameSV, AlwaysAddSuffix, true);
+}
+
+MCSymbol *MCContext::createNamedTempSymbol(const Twine &Name) {
+  SmallString<128> NameSV;
+  raw_svector_ostream(NameSV) << MAI->getPrivateGlobalPrefix() << Name;
+  return createSymbol(NameSV, true, false);
 }
 
 MCSymbol *MCContext::createLinkerPrivateTempSymbol() {
@@ -245,8 +250,10 @@ MCSymbol *MCContext::createLinkerPrivateTempSymbol() {
   return createSymbol(NameSV, true, false);
 }
 
-MCSymbol *MCContext::createTempSymbol(bool CanBeUnnamed) {
-  return createTempSymbol("tmp", true, CanBeUnnamed);
+MCSymbol *MCContext::createTempSymbol() { return createTempSymbol("tmp"); }
+
+MCSymbol *MCContext::createNamedTempSymbol() {
+  return createNamedTempSymbol("tmp");
 }
 
 unsigned MCContext::NextInstance(unsigned LocalLabelVal) {
@@ -267,7 +274,7 @@ MCSymbol *MCContext::getOrCreateDirectionalLocalSymbol(unsigned LocalLabelVal,
                                                        unsigned Instance) {
   MCSymbol *&Sym = LocalSymbols[std::make_pair(LocalLabelVal, Instance)];
   if (!Sym)
-    Sym = createTempSymbol(false);
+    Sym = createNamedTempSymbol();
   return Sym;
 }
 
diff --git a/llvm/lib/MC/MCDwarf.cpp b/llvm/lib/MC/MCDwarf.cpp
index 7f72d062b7ac6..12a7d9b6e5899 100644
--- a/llvm/lib/MC/MCDwarf.cpp
+++ b/llvm/lib/MC/MCDwarf.cpp
@@ -46,10 +46,8 @@
 using namespace llvm;
 
 MCSymbol *mcdwarf::emitListsTableHeaderStart(MCStreamer &S) {
-  MCSymbol *Start =
-      S.getContext().createTempSymbol("debug_list_header_start", true, true);
-  MCSymbol *End =
-      S.getContext().createTempSymbol("debug_list_header_end", true, true);
+  MCSymbol *Start = S.getContext().createTempSymbol("debug_list_header_start");
+  MCSymbol *End = S.getContext().createTempSymbol("debug_list_header_end");
   auto DwarfFormat = S.getContext().getDwarfFormat();
   if (DwarfFormat == dwarf::DWARF64) {
     S.AddComment("DWARF64 mark");
@@ -1140,7 +1138,7 @@ static MCSymbol *emitGenDwarfRanges(MCStreamer *MCOS) {
     MCSymbol *EndSymbol = mcdwarf::emitListsTableHeaderStart(*MCOS);
     MCOS->AddComment("Offset entry count");
     MCOS->emitInt32(0);
-    RangesSymbol = context.createTempSymbol("debug_rnglist0_start", true, true);
+    RangesSymbol = context.createTempSymbol("debug_rnglist0_start");
     MCOS->emitLabel(RangesSymbol);
     for (MCSection *Sec : Sections) {
       const MCSymbol *StartSymbol = Sec->getBeginSymbol();
@@ -1157,7 +1155,7 @@ static MCSymbol *emitGenDwarfRanges(MCStreamer *MCOS) {
     MCOS->emitLabel(EndSymbol);
   } else {
     MCOS->SwitchSection(context.getObjectFileInfo()->getDwarfRangesSection());
-    RangesSymbol = context.createTempSymbol("debug_ranges_start", true, true);
+    RangesSymbol = context.createTempSymbol("debug_ranges_start");
     MCOS->emitLabel(RangesSymbol);
     for (MCSection *Sec : Sections) {
       const MCSymbol *StartSymbol = Sec->getBeginSymbol();
diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp
index 2f464f4b58b6f..1c23d31f8744a 100644
--- a/llvm/lib/MC/MCObjectStreamer.cpp
+++ b/llvm/lib/MC/MCObjectStreamer.cpp
@@ -248,7 +248,7 @@ void MCObjectStreamer::emitValueImpl(const MCExpr *Value, unsigned Size,
 }
 
 MCSymbol *MCObjectStreamer::emitCFILabel() {
-  MCSymbol *Label = getContext().createTempSymbol("cfi", true);
+  MCSymbol *Label = getContext().createTempSymbol("cfi");
   emitLabel(Label);
   return Label;
 }
diff --git a/llvm/lib/MC/MCSection.cpp b/llvm/lib/MC/MCSection.cpp
index 7c5834895e523..7997b237a7ebe 100644
--- a/llvm/lib/MC/MCSection.cpp
+++ b/llvm/lib/MC/MCSection.cpp
@@ -28,7 +28,7 @@ MCSection::MCSection(SectionVariant V, StringRef Name, SectionKind K,
 
 MCSymbol *MCSection::getEndSymbol(MCContext &Ctx) {
   if (!End)
-    End = Ctx.createTempSymbol("sec_end", true);
+    End = Ctx.createTempSymbol("sec_end");
   return End;
 }
 
diff --git a/llvm/lib/MC/MCStreamer.cpp b/llvm/lib/MC/MCStreamer.cpp
index 71a89ad46703b..4b5ae3cc202de 100644
--- a/llvm/lib/MC/MCStreamer.cpp
+++ b/llvm/lib/MC/MCStreamer.cpp
@@ -1076,7 +1076,7 @@ void MCStreamer::emitAbsoluteSymbolDiff(const MCSymbol *Hi, const MCSymbol *Lo,
   }
 
   // Otherwise, emit with .set (aka assignment).
-  MCSymbol *SetLabel = Context.createTempSymbol("set", true);
+  MCSymbol *SetLabel = Context.createTempSymbol("set");
   emitAssignment(SetLabel, Diff);
   emitSymbolValue(SetLabel, Size);
 }
diff --git a/llvm/lib/Object/COFFObjectFile.cpp b/llvm/lib/Object/COFFObjectFile.cpp
index c0902597fadf3..2e44a38ccdaaa 100644
--- a/llvm/lib/Object/COFFObjectFile.cpp
+++ b/llvm/lib/Object/COFFObjectFile.cpp
@@ -57,7 +57,7 @@ static bool checkSize(MemoryBufferRef M, std::error_code &EC, uint64_t Size) {
 template <typename T>
 static Error getObject(const T *&Obj, MemoryBufferRef M, const void *Ptr,
                        const uint64_t Size = sizeof(T)) {
-  uintptr_t Addr = uintptr_t(Ptr);
+  uintptr_t Addr = reinterpret_cast<uintptr_t>(Ptr);
   if (Error E = Binary::checkOffset(M, Addr, Size))
     return E;
   Obj = reinterpret_cast<const T *>(Addr);
@@ -103,10 +103,11 @@ const coff_symbol_type *COFFObjectFile::toSymb(DataRefImpl Ref) const {
   const coff_symbol_type *Addr =
       reinterpret_cast<const coff_symbol_type *>(Ref.p);
 
-  assert(!checkOffset(Data, uintptr_t(Addr), sizeof(*Addr)));
+  assert(!checkOffset(Data, reinterpret_cast<uintptr_t>(Addr), sizeof(*Addr)));
 #ifndef NDEBUG
   // Verify that the symbol points to a valid entry in the symbol table.
-  uintptr_t Offset = uintptr_t(Addr) - uintptr_t(base());
+  uintptr_t Offset =
+      reinterpret_cast<uintptr_t>(Addr) - reinterpret_cast<uintptr_t>(base());
 
   assert((Offset - getPointerToSymbolTable()) % sizeof(coff_symbol_type) == 0 &&
          "Symbol did not point to the beginning of a symbol");
@@ -123,7 +124,8 @@ const coff_section *COFFObjectFile::toSec(DataRefImpl Ref) const {
   if (Addr < SectionTable || Addr >= (SectionTable + getNumberOfSections()))
     report_fatal_error("Section was outside of section table.");
 
-  uintptr_t Offset = uintptr_t(Addr) - uintptr_t(SectionTable);
+  uintptr_t Offset = reinterpret_cast<uintptr_t>(Addr) -
+                     reinterpret_cast<uintptr_t>(SectionTable);
   assert(Offset % sizeof(coff_section) == 0 &&
          "Section did not point to the beginning of a section");
 #endif
@@ -332,7 +334,7 @@ bool COFFObjectFile::isDebugSection(StringRef SectionName) const {
 
 unsigned COFFObjectFile::getSectionID(SectionRef Sec) const {
   uintptr_t Offset =
-      uintptr_t(Sec.getRawDataRefImpl().p) - uintptr_t(SectionTable);
+      Sec.getRawDataRefImpl().p - reinterpret_cast<uintptr_t>(SectionTable);
   assert((Offset % sizeof(coff_section)) == 0);
   return (Offset / sizeof(coff_section)) + 1;
 }
@@ -376,7 +378,7 @@ getFirstReloc(const coff_section *Sec, MemoryBufferRef M, const uint8_t *Base) {
     // relocations.
     begin++;
   }
-  if (auto E = Binary::checkOffset(M, uintptr_t(begin),
+  if (auto E = Binary::checkOffset(M, reinterpret_cast<uintptr_t>(begin),
                                    sizeof(coff_relocation) * NumRelocs)) {
     consumeError(std::move(E));
     return nullptr;
@@ -467,7 +469,8 @@ Error COFFObjectFile::getRvaPtr(uint32_t Addr, uintptr_t &Res) const {
     uint32_t SectionEnd = Section->VirtualAddress + Section->VirtualSize;
     if (SectionStart <= Addr && Addr < SectionEnd) {
       uint32_t Offset = Addr - SectionStart;
-      Res = uintptr_t(base()) + Section->PointerToRawData + Offset;
+      Res = reinterpret_cast<uintptr_t>(base()) + Section->PointerToRawData +
+            Offset;
       return Error::success();
     }
   }
@@ -484,8 +487,8 @@ Error COFFObjectFile::getRvaAndSizeAsBytes(uint32_t RVA, uint32_t Size,
     uint32_t OffsetIntoSection = RVA - SectionStart;
     if (SectionStart <= RVA && OffsetIntoSection < Section->VirtualSize &&
         Size <= Section->VirtualSize - OffsetIntoSection) {
-      uintptr_t Begin =
-          uintptr_t(base()) + Section->PointerToRawData + OffsetIntoSection;
+      uintptr_t Begin = reinterpret_cast<uintptr_t>(base()) +
+                        Section->PointerToRawData + OffsetIntoSection;
       Contents =
           ArrayRef<uint8_t>(reinterpret_cast<const uint8_t *>(Begin), Size);
       return Error::success();
@@ -1127,7 +1130,8 @@ Error COFFObjectFile::getSectionContents(const coff_section *Sec,
   // The only thing that we need to verify is that the contents is contained
   // within the file bounds. We don't need to make sure it doesn't cover other
   // data, as there's nothing that says that is not allowed.
-  uintptr_t ConStart = uintptr_t(base()) + Sec->PointerToRawData;
+  uintptr_t ConStart =
+      reinterpret_cast<uintptr_t>(base()) + Sec->PointerToRawData;
   uint32_t SectionSize = getSectionSize(Sec);
   if (Error E = checkOffset(Data, ConStart, SectionSize))
     return E;
diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp
index c654c3fd3d6c1..91871a6255dc8 100644
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -73,7 +73,8 @@ ObjectFile::createELFObjectFile(MemoryBufferRef Obj, bool InitContent) {
   std::pair<unsigned char, unsigned char> Ident =
       getElfArchType(Obj.getBuffer());
   std::size_t MaxAlignment =
-      1ULL << countTrailingZeros(uintptr_t(Obj.getBufferStart()));
+      1ULL << countTrailingZeros(
+          reinterpret_cast<uintptr_t>(Obj.getBufferStart()));
 
   if (MaxAlignment < 2)
     return createError("Insufficient alignment");
diff --git a/llvm/lib/Object/XCOFFObjectFile.cpp b/llvm/lib/Object/XCOFFObjectFile.cpp
index fee468584f36a..b0d772b6ff212 100644
--- a/llvm/lib/Object/XCOFFObjectFile.cpp
+++ b/llvm/lib/Object/XCOFFObjectFile.cpp
@@ -31,7 +31,7 @@ static const uint16_t NoRelMask = 0x0001;
 template <typename T>
 static Expected<const T *> getObject(MemoryBufferRef M, const void *Ptr,
                                      const uint64_t Size = sizeof(T)) {
-  uintptr_t Addr = uintptr_t(Ptr);
+  uintptr_t Addr = reinterpret_cast<uintptr_t>(Ptr);
   if (Error E = Binary::checkOffset(M, Addr, Size))
     return std::move(E);
   return reinterpret_cast<const T *>(Addr);
@@ -283,7 +283,7 @@ XCOFFObjectFile::getSectionContents(DataRefImpl Sec) const {
 
   const uint8_t * ContentStart = base() + OffsetToRaw;
   uint64_t SectionSize = getSectionSize(Sec);
-  if (checkOffset(Data, uintptr_t(ContentStart), SectionSize))
+  if (checkOffset(Data, reinterpret_cast<uintptr_t>(ContentStart), SectionSize))
     return make_error<BinaryError>();
 
   return makeArrayRef(ContentStart,SectionSize);
diff --git a/llvm/lib/ObjectYAML/ELFEmitter.cpp b/llvm/lib/ObjectYAML/ELFEmitter.cpp
index 51efc00f52d4d..010a881379f31 100644
--- a/llvm/lib/ObjectYAML/ELFEmitter.cpp
+++ b/llvm/lib/ObjectYAML/ELFEmitter.cpp
@@ -168,15 +168,7 @@ struct Fragment {
 /// TODO: This class still has a ways to go before it is truly a "single
 /// point of truth".
 template <class ELFT> class ELFState {
-  typedef typename ELFT::Ehdr Elf_Ehdr;
-  typedef typename ELFT::Phdr Elf_Phdr;
-  typedef typename ELFT::Shdr Elf_Shdr;
-  typedef typename ELFT::Sym Elf_Sym;
-  typedef typename ELFT::Rel Elf_Rel;
-  typedef typename ELFT::Rela Elf_Rela;
-  typedef typename ELFT::Relr Elf_Relr;
-  typedef typename ELFT::Dyn Elf_Dyn;
-  typedef typename ELFT::uint uintX_t;
+  LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
 
   enum class SymtabType { Static, Dynamic };
 
@@ -1477,9 +1469,6 @@ template <class ELFT>
 void ELFState<ELFT>::writeSectionContent(Elf_Shdr &SHeader,
                                          const ELFYAML::VerdefSection &Section,
                                          ContiguousBlobAccumulator &CBA) {
-  typedef typename ELFT::Verdef Elf_Verdef;
-  typedef typename ELFT::Verdaux Elf_Verdaux;
-
   SHeader.sh_info = Section.Info;
 
   if (!Section.Entries)
@@ -1522,9 +1511,6 @@ template <class ELFT>
 void ELFState<ELFT>::writeSectionContent(Elf_Shdr &SHeader,
                                          const ELFYAML::VerneedSection &Section,
                                          ContiguousBlobAccumulator &CBA) {
-  typedef typename ELFT::Verneed Elf_Verneed;
-  typedef typename ELFT::Vernaux Elf_Vernaux;
-
   SHeader.sh_info = Section.Info;
 
   if (!Section.VerneedV)
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 4e8062c6a7890..635e7bab1a7af 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -1882,6 +1882,10 @@ AAManager PassBuilder::buildDefaultAAPipeline() {
   // results from `GlobalsAA` through a readonly proxy.
   AA.registerModuleAnalysis<GlobalsAA>();
 
+  // Add target-specific alias analyses.
+  if (TM)
+    TM->registerAliasAnalyses(AA);
+
   return AA;
 }
 
diff --git a/llvm/lib/Passes/PassRegistry.def b/llvm/lib/Passes/PassRegistry.def
index 977bd46b06337..b00a7bd14b4fd 100644
--- a/llvm/lib/Passes/PassRegistry.def
+++ b/llvm/lib/Passes/PassRegistry.def
@@ -81,7 +81,7 @@ MODULE_PASS("mergefunc", MergeFunctionsPass())
 MODULE_PASS("name-anon-globals", NameAnonGlobalPass())
 MODULE_PASS("no-op-module", NoOpModulePass())
 MODULE_PASS("objc-arc", ObjCARCOptPass())
-MODULE_PASS("objc-arc-apelim", ObjCARCOptPass())
+MODULE_PASS("objc-arc-apelim", ObjCARCAPElimPass())
 MODULE_PASS("objc-arc-contract", ObjCARCContractPass())
 MODULE_PASS("partial-inliner", PartialInlinerPass())
 MODULE_PASS("pgo-icall-prom", PGOIndirectCallPromotion())
diff --git a/llvm/lib/SYCLLowerIR/LowerESIMD.cpp b/llvm/lib/SYCLLowerIR/LowerESIMD.cpp
index c8b34111ac589..ea16039dbe40c 100644
--- a/llvm/lib/SYCLLowerIR/LowerESIMD.cpp
+++ b/llvm/lib/SYCLLowerIR/LowerESIMD.cpp
@@ -144,7 +144,7 @@ struct ESIMDIntrinDesc {
 
   std::string GenXSpelling;
   SmallVector<ArgRule, 16> ArgRules;
-  NameRule SuffixRule = {NO_RULE, 0};
+  NameRule SuffixRule = {NO_RULE, {0}};
 
   int getNumGenXArgs() const {
     auto NRules = ArgRules.size();
@@ -169,7 +169,7 @@ class ESIMDIntrinDescTable {
 
 #define DEF_ARG_RULE(Nm, Kind)                                                 \
   static constexpr ESIMDIntrinDesc::ArgRule Nm(int16_t N) {                    \
-    return ESIMDIntrinDesc::ArgRule{ESIMDIntrinDesc::Kind, N};                 \
+    return ESIMDIntrinDesc::ArgRule{ESIMDIntrinDesc::Kind, {{N, {}}}};         \
   }
   DEF_ARG_RULE(l, SRC_CALL_ALL)
   DEF_ARG_RULE(t, SRC_TMPL_ARG)
@@ -179,39 +179,39 @@ class ESIMDIntrinDescTable {
   static constexpr ESIMDIntrinDesc::ArgRule a(int16_t N) {
     return ESIMDIntrinDesc::ArgRule{
         ESIMDIntrinDesc::SRC_CALL_ARG,
-        {N, ESIMDIntrinDesc::GenXArgConversion::NONE}};
+        {{N, ESIMDIntrinDesc::GenXArgConversion::NONE}}};
   }
 
   static constexpr ESIMDIntrinDesc::ArgRule ai1(int16_t N) {
     return ESIMDIntrinDesc::ArgRule{
         ESIMDIntrinDesc::SRC_CALL_ARG,
-        {N, ESIMDIntrinDesc::GenXArgConversion::TO_I1}};
+        {{N, ESIMDIntrinDesc::GenXArgConversion::TO_I1}}};
   }
 
   static constexpr ESIMDIntrinDesc::ArgRule aSI(int16_t N) {
     return ESIMDIntrinDesc::ArgRule{
         ESIMDIntrinDesc::SRC_CALL_ARG,
-        {N, ESIMDIntrinDesc::GenXArgConversion::TO_SI}};
+        {{N, ESIMDIntrinDesc::GenXArgConversion::TO_SI}}};
   }
 
   static constexpr ESIMDIntrinDesc::ArgRule c16(int16_t N) {
-    return ESIMDIntrinDesc::ArgRule{ESIMDIntrinDesc::CONST_INT16, N};
+    return ESIMDIntrinDesc::ArgRule{ESIMDIntrinDesc::CONST_INT16, {{N, {}}}};
   }
 
   static constexpr ESIMDIntrinDesc::ArgRule c32(int16_t N) {
-    return ESIMDIntrinDesc::ArgRule{ESIMDIntrinDesc::CONST_INT32, N};
+    return ESIMDIntrinDesc::ArgRule{ESIMDIntrinDesc::CONST_INT32, {{N, {}}}};
   }
 
   static constexpr ESIMDIntrinDesc::ArgRule c64(int16_t N) {
-    return ESIMDIntrinDesc::ArgRule{ESIMDIntrinDesc::CONST_INT64, N};
+    return ESIMDIntrinDesc::ArgRule{ESIMDIntrinDesc::CONST_INT64, {{N, {}}}};
   }
 
   static constexpr ESIMDIntrinDesc::NameRule bo(int16_t N) {
-    return ESIMDIntrinDesc::NameRule{ESIMDIntrinDesc::BIN_OP, N};
+    return ESIMDIntrinDesc::NameRule{ESIMDIntrinDesc::BIN_OP, {N}};
   }
 
   static constexpr ESIMDIntrinDesc::NameRule nk(int16_t N) {
-    return ESIMDIntrinDesc::NameRule{ESIMDIntrinDesc::NUM_KIND, N};
+    return ESIMDIntrinDesc::NameRule{ESIMDIntrinDesc::NUM_KIND, {N}};
   }
 
 public:
@@ -1239,10 +1239,11 @@ PreservedAnalyses SYCLLowerESIMDPass::run(Function &F,
     if (auto CastOp = dyn_cast<llvm::CastInst>(&I)) {
       llvm::Type *DstTy = CastOp->getDestTy();
       auto CastOpcode = CastOp->getOpcode();
-      if ((CastOpcode == llvm::Instruction::FPToUI &&
-           DstTy->getScalarType()->getPrimitiveSizeInBits() <= 32) ||
-          (CastOpcode == llvm::Instruction::FPToSI &&
-           DstTy->getScalarType()->getPrimitiveSizeInBits() < 32)) {
+      if (isa<FixedVectorType>(DstTy) &&
+          ((CastOpcode == llvm::Instruction::FPToUI &&
+            DstTy->getScalarType()->getPrimitiveSizeInBits() <= 32) ||
+           (CastOpcode == llvm::Instruction::FPToSI &&
+            DstTy->getScalarType()->getPrimitiveSizeInBits() < 32))) {
         IRBuilder<> Builder(&I);
         llvm::Value *Src = CastOp->getOperand(0);
         auto TmpTy = llvm::FixedVectorType::get(
diff --git a/llvm/lib/Support/SourceMgr.cpp b/llvm/lib/Support/SourceMgr.cpp
index e50cf5b4a8344..499d9810677e6 100644
--- a/llvm/lib/Support/SourceMgr.cpp
+++ b/llvm/lib/Support/SourceMgr.cpp
@@ -267,7 +267,7 @@ SMDiagnostic SourceMgr::GetMessage(SMLoc Loc, SourceMgr::DiagKind Kind,
   SmallVector<std::pair<unsigned, unsigned>, 4> ColRanges;
   std::pair<unsigned, unsigned> LineAndCol;
   StringRef BufferID = "<unknown>";
-  std::string LineStr;
+  StringRef LineStr;
 
   if (Loc.isValid()) {
     unsigned CurBuf = FindBufferContainingLoc(Loc);
@@ -288,7 +288,7 @@ SMDiagnostic SourceMgr::GetMessage(SMLoc Loc, SourceMgr::DiagKind Kind,
     const char *BufEnd = CurMB->getBufferEnd();
     while (LineEnd != BufEnd && LineEnd[0] != '\n' && LineEnd[0] != '\r')
       ++LineEnd;
-    LineStr = std::string(LineStart, LineEnd);
+    LineStr = StringRef(LineStart, LineEnd - LineStart);
 
     // Convert any ranges to column ranges that only intersect the line of the
     // location.
@@ -370,8 +370,8 @@ SMDiagnostic::SMDiagnostic(const SourceMgr &sm, SMLoc L, StringRef FN, int Line,
                            ArrayRef<std::pair<unsigned, unsigned>> Ranges,
                            ArrayRef<SMFixIt> Hints)
     : SM(&sm), Loc(L), Filename(std::string(FN)), LineNo(Line), ColumnNo(Col),
-      Kind(Kind), Message(std::string(Msg)), LineContents(std::string(LineStr)),
-      Ranges(Ranges.vec()), FixIts(Hints.begin(), Hints.end()) {
+      Kind(Kind), Message(Msg), LineContents(LineStr), Ranges(Ranges.vec()),
+      FixIts(Hints.begin(), Hints.end()) {
   llvm::sort(FixIts);
 }
 
@@ -386,13 +386,12 @@ static void buildFixItLine(std::string &CaretLine, std::string &FixItLine,
 
   size_t PrevHintEndCol = 0;
 
-  for (ArrayRef<SMFixIt>::iterator I = FixIts.begin(), E = FixIts.end(); I != E;
-       ++I) {
+  for (const llvm::SMFixIt &Fixit : FixIts) {
     // If the fixit contains a newline or tab, ignore it.
-    if (I->getText().find_first_of("\n\r\t") != StringRef::npos)
+    if (Fixit.getText().find_first_of("\n\r\t") != StringRef::npos)
       continue;
 
-    SMRange R = I->getRange();
+    SMRange R = Fixit.getRange();
 
     // If the line doesn't contain any part of the range, then ignore it.
     if (R.Start.getPointer() > LineEnd || R.End.getPointer() < LineStart)
@@ -421,16 +420,15 @@ static void buildFixItLine(std::string &CaretLine, std::string &FixItLine,
     // FIXME: This assertion is intended to catch unintended use of multibyte
     // characters in fixits. If we decide to do this, we'll have to track
     // separate byte widths for the source and fixit lines.
-    assert((size_t)sys::locale::columnWidth(I->getText()) ==
-           I->getText().size());
+    assert((size_t)sys::locale::columnWidth(Fixit.getText()) ==
+           Fixit.getText().size());
 
     // This relies on one byte per column in our fixit hints.
-    unsigned LastColumnModified = HintCol + I->getText().size();
+    unsigned LastColumnModified = HintCol + Fixit.getText().size();
     if (LastColumnModified > FixItLine.size())
       FixItLine.resize(LastColumnModified, ' ');
 
-    std::copy(I->getText().begin(), I->getText().end(),
-              FixItLine.begin() + HintCol);
+    llvm::copy(Fixit.getText(), FixItLine.begin() + HintCol);
 
     PrevHintEndCol = LastColumnModified;
 
@@ -534,11 +532,9 @@ void SMDiagnostic::print(const char *ProgName, raw_ostream &OS, bool ShowColors,
   std::string CaretLine(NumColumns + 1, ' ');
 
   // Expand any ranges.
-  for (unsigned r = 0, e = Ranges.size(); r != e; ++r) {
-    std::pair<unsigned, unsigned> R = Ranges[r];
+  for (const std::pair<unsigned, unsigned> &R : Ranges)
     std::fill(&CaretLine[R.first],
               &CaretLine[std::min((size_t)R.second, CaretLine.size())], '~');
-  }
 
   // Add any fix-its.
   // FIXME: Find the beginning of the line properly for multibyte characters.
diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp
index cbdce04494f37..3e6daeb4d238b 100644
--- a/llvm/lib/TableGen/Record.cpp
+++ b/llvm/lib/TableGen/Record.cpp
@@ -856,14 +856,19 @@ static StringInit *interleaveStringList(const ListInit *List,
                                         const StringInit *Delim) {
   if (List->size() == 0)
     return StringInit::get("");
-  SmallString<80> Result(cast<StringInit>(List->getElement(0))->getValue());
+  StringInit *Element = dyn_cast<StringInit>(List->getElement(0));
+  if (!Element)
+    return nullptr;
+  SmallString<80> Result(Element->getValue());
   StringInit::StringFormat Fmt = StringInit::SF_String;
 
   for (unsigned I = 1, E = List->size(); I < E; ++I) {
     Result.append(Delim->getValue());
-    auto *StrInit = cast<StringInit>(List->getElement(I));
-    Result.append(StrInit->getValue());
-    Fmt = StringInit::determineFormat(Fmt, StrInit->getFormat());
+    StringInit *Element = dyn_cast<StringInit>(List->getElement(I));
+    if (!Element)
+      return nullptr;
+    Result.append(Element->getValue());
+    Fmt = StringInit::determineFormat(Fmt, Element->getFormat());
   }
   return StringInit::get(Result, Fmt);
 }
@@ -872,14 +877,21 @@ static StringInit *interleaveIntList(const ListInit *List,
                                      const StringInit *Delim) {
   if (List->size() == 0)
     return StringInit::get("");
-  SmallString<80> Result(
-      cast<IntInit>(List->getElement(0)->getCastTo(IntRecTy::get()))
-          ->getAsString());
+  IntInit *Element =
+      dyn_cast_or_null<IntInit>(List->getElement(0)
+                                    ->convertInitializerTo(IntRecTy::get()));
+  if (!Element)
+    return nullptr;
+  SmallString<80> Result(Element->getAsString());
 
   for (unsigned I = 1, E = List->size(); I < E; ++I) {
     Result.append(Delim->getValue());
-    Result.append(cast<IntInit>(List->getElement(I)->getCastTo(IntRecTy::get()))
-                      ->getAsString());
+    IntInit *Element =
+        dyn_cast_or_null<IntInit>(List->getElement(I)
+                                      ->convertInitializerTo(IntRecTy::get()));
+    if (!Element)
+      return nullptr;
+    Result.append(Element->getAsString());
   }
   return StringInit::get(Result);
 }
@@ -975,10 +987,13 @@ Init *BinOpInit::Fold(Record *CurRec) const {
     ListInit *List = dyn_cast<ListInit>(LHS);
     StringInit *Delim = dyn_cast<StringInit>(RHS);
     if (List && Delim) {
+      StringInit *Result;
       if (isa<StringRecTy>(List->getElementType()))
-        return interleaveStringList(List, Delim);
+        Result = interleaveStringList(List, Delim);
       else
-        return interleaveIntList(List, Delim);
+        Result = interleaveIntList(List, Delim);
+      if (Result)
+        return Result;
     }
     break;
   }
@@ -1325,6 +1340,27 @@ Init *TernOpInit::Fold(Record *CurRec) const {
     }
     break;
   }
+
+  case SUBSTR: {
+    StringInit *LHSs = dyn_cast<StringInit>(LHS);
+    IntInit *MHSi = dyn_cast<IntInit>(MHS);
+    IntInit *RHSi = dyn_cast<IntInit>(RHS);
+    if (LHSs && MHSi && RHSi) {
+      int64_t StringSize = LHSs->getValue().size();
+      int64_t Start = MHSi->getValue();
+      int64_t Length = RHSi->getValue();
+      if (Start < 0 || Start > StringSize)
+        PrintError(CurRec->getLoc(),
+                   Twine("!substr start position is out of range 0...") +
+                       std::to_string(StringSize) + ": " +
+                       std::to_string(Start));
+      if (Length < 0)
+        PrintError(CurRec->getLoc(), "!substr length must be nonnegative");
+      return StringInit::get(LHSs->getValue().substr(Start, Length),
+                             LHSs->getFormat());
+    }
+    break;
+  }
   }
 
   return const_cast<TernOpInit *>(this);
@@ -1364,11 +1400,12 @@ std::string TernOpInit::getAsString() const {
   std::string Result;
   bool UnquotedLHS = false;
   switch (getOpcode()) {
-  case SUBST: Result = "!subst"; break;
-  case FOREACH: Result = "!foreach"; UnquotedLHS = true; break;
+  case DAG: Result = "!dag"; break;
   case FILTER: Result = "!filter"; UnquotedLHS = true; break;
+  case FOREACH: Result = "!foreach"; UnquotedLHS = true; break;
   case IF: Result = "!if"; break;
-  case DAG: Result = "!dag"; break;
+  case SUBST: Result = "!subst"; break;
+  case SUBSTR: Result = "!substr"; break;
   }
   return (Result + "(" +
           (UnquotedLHS ? LHS->getAsUnquotedString() : LHS->getAsString()) +
diff --git a/llvm/lib/TableGen/TGLexer.cpp b/llvm/lib/TableGen/TGLexer.cpp
index df0df96f40eb7..a45ef6dc10c16 100644
--- a/llvm/lib/TableGen/TGLexer.cpp
+++ b/llvm/lib/TableGen/TGLexer.cpp
@@ -589,6 +589,7 @@ tgtok::TokKind TGLexer::LexExclaim() {
     .Case("listsplat", tgtok::XListSplat)
     .Case("strconcat", tgtok::XStrConcat)
     .Case("interleave", tgtok::XInterleave)
+    .Case("substr", tgtok::XSubstr)
     .Cases("setdagop", "setop", tgtok::XSetDagOp) // !setop is deprecated.
     .Cases("getdagop", "getop", tgtok::XGetDagOp) // !getop is deprecated.
     .Default(tgtok::Error);
diff --git a/llvm/lib/TableGen/TGLexer.h b/llvm/lib/TableGen/TGLexer.h
index 1856bef3ea9bd..ee568849ca887 100644
--- a/llvm/lib/TableGen/TGLexer.h
+++ b/llvm/lib/TableGen/TGLexer.h
@@ -53,9 +53,9 @@ namespace tgtok {
 
     // Bang operators.
     XConcat, XADD, XSUB, XMUL, XNOT, XAND, XOR, XXOR, XSRA, XSRL, XSHL,
-    XListConcat, XListSplat, XStrConcat, XInterleave, XCast, XSubst, XForEach,
-    XFilter, XFoldl, XHead, XTail, XSize, XEmpty, XIf, XCond, XEq, XIsA,
-    XDag, XNe, XLe, XLt, XGe, XGt, XSetDagOp, XGetDagOp,
+    XListConcat, XListSplat, XStrConcat, XInterleave, XSubstr, XCast,
+    XSubst, XForEach, XFilter, XFoldl, XHead, XTail, XSize, XEmpty, XIf,
+    XCond, XEq, XIsA, XDag, XNe, XLe, XLt, XGe, XGt, XSetDagOp, XGetDagOp,
 
     // Boolean literals.
     TrueVal, FalseVal,
diff --git a/llvm/lib/TableGen/TGParser.cpp b/llvm/lib/TableGen/TGParser.cpp
index 2671d29a72721..ebb66ccffc29a 100644
--- a/llvm/lib/TableGen/TGParser.cpp
+++ b/llvm/lib/TableGen/TGParser.cpp
@@ -25,6 +25,7 @@
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
+#include <limits>
 
 using namespace llvm;
 
@@ -1496,6 +1497,9 @@ Init *TGParser::ParseOperation(Record *CurRec, RecTy *ItemType) {
     return (TernOpInit::get(Code, LHS, MHS, RHS, Type))->Fold(CurRec);
   }
 
+  case tgtok::XSubstr:
+    return ParseOperationSubstr(CurRec, ItemType);
+
   case tgtok::XCond:
     return ParseOperationCond(CurRec, ItemType);
 
@@ -1655,6 +1659,94 @@ RecTy *TGParser::ParseOperatorType() {
   return Type;
 }
 
+/// Parse the !substr operation. Return null on error.
+///
+/// Substr ::= !substr(string, start-int [, length-int]) => string
+Init *TGParser::ParseOperationSubstr(Record *CurRec, RecTy *ItemType) {
+  TernOpInit::TernaryOp Code = TernOpInit::SUBSTR;
+  RecTy *Type = StringRecTy::get();
+
+  Lex.Lex(); // eat the operation
+
+  if (!consume(tgtok::l_paren)) {
+    TokError("expected '(' after !substr operator");
+    return nullptr;
+  }
+
+  Init *LHS = ParseValue(CurRec);
+  if (!LHS)
+    return nullptr;
+
+  if (!consume(tgtok::comma)) {
+    TokError("expected ',' in !substr operator");
+    return nullptr;
+  }
+
+  SMLoc MHSLoc = Lex.getLoc();
+  Init *MHS = ParseValue(CurRec);
+  if (!MHS)
+    return nullptr;
+
+  SMLoc RHSLoc = Lex.getLoc();
+  Init *RHS;
+  if (consume(tgtok::comma)) {
+    RHSLoc = Lex.getLoc();
+    RHS = ParseValue(CurRec);
+    if (!RHS)
+      return nullptr;
+  } else {
+    RHS = IntInit::get(std::numeric_limits<int64_t>::max());
+  }
+
+  if (!consume(tgtok::r_paren)) {
+    TokError("expected ')' in !substr operator");
+    return nullptr;
+  }
+
+  if (ItemType && !Type->typeIsConvertibleTo(ItemType)) {
+    Error(RHSLoc, Twine("expected value of type '") +
+                  ItemType->getAsString() + "', got '" +
+                  Type->getAsString() + "'");
+  }
+
+  TypedInit *LHSt = dyn_cast<TypedInit>(LHS);
+  if (!LHSt && !isa<UnsetInit>(LHS)) {
+    TokError("could not determine type of the string in !substr");
+    return nullptr;
+  }
+  if (LHSt && !isa<StringRecTy>(LHSt->getType())) {
+    TokError(Twine("expected string, got type '") +
+             LHSt->getType()->getAsString() + "'");
+    return nullptr;
+  }
+
+  TypedInit *MHSt = dyn_cast<TypedInit>(MHS);
+  if (!MHSt && !isa<UnsetInit>(MHS)) {
+    TokError("could not determine type of the start position in !substr");
+    return nullptr;
+  }
+  if (MHSt && !isa<IntRecTy>(MHSt->getType())) {
+    Error(MHSLoc, Twine("expected int, got type '") +
+                      MHSt->getType()->getAsString() + "'");
+    return nullptr;
+  }
+
+  if (RHS) {
+    TypedInit *RHSt = dyn_cast<TypedInit>(RHS);
+    if (!RHSt && !isa<UnsetInit>(RHS)) {
+      TokError("could not determine type of the length in !substr");
+      return nullptr;
+    }
+    if (RHSt && !isa<IntRecTy>(RHSt->getType())) {
+      TokError(Twine("expected int, got type '") +
+               RHSt->getType()->getAsString() + "'");
+      return nullptr;
+    }
+  }
+
+  return (TernOpInit::get(Code, LHS, MHS, RHS, Type))->Fold(CurRec);
+}
+
 /// Parse the !foreach and !filter operations. Return null on error.
 ///
 /// ForEach ::= !foreach(ID, list-or-dag, expr) => list<expr type>
@@ -2206,7 +2298,8 @@ Init *TGParser::ParseSimpleValue(Record *CurRec, RecTy *ItemType,
   case tgtok::XFoldl:
   case tgtok::XForEach:
   case tgtok::XFilter:
-  case tgtok::XSubst: { // Value ::= !ternop '(' Value ',' Value ',' Value ')'
+  case tgtok::XSubst:
+  case tgtok::XSubstr: { // Value ::= !ternop '(' Value ',' Value ',' Value ')'
     return ParseOperation(CurRec, ItemType);
   }
   }
diff --git a/llvm/lib/TableGen/TGParser.h b/llvm/lib/TableGen/TGParser.h
index bdeb4d35382b2..3ed78a23067ff 100644
--- a/llvm/lib/TableGen/TGParser.h
+++ b/llvm/lib/TableGen/TGParser.h
@@ -254,6 +254,7 @@ class TGParser {
                        TypedInit *FirstItem = nullptr);
   RecTy *ParseType();
   Init *ParseOperation(Record *CurRec, RecTy *ItemType);
+  Init *ParseOperationSubstr(Record *CurRec, RecTy *ItemType);
   Init *ParseOperationForEachFilter(Record *CurRec, RecTy *ItemType);
   Init *ParseOperationCond(Record *CurRec, RecTy *ItemType);
   RecTy *ParseOperatorType();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e74bc739ddafe..2012f1247a0f0 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -182,6 +182,8 @@ static bool isMergePassthruOpcode(unsigned Opc) {
   switch (Opc) {
   default:
     return false;
+  case AArch64ISD::BITREVERSE_MERGE_PASSTHRU:
+  case AArch64ISD::BSWAP_MERGE_PASSTHRU:
   case AArch64ISD::DUP_MERGE_PASSTHRU:
   case AArch64ISD::FNEG_MERGE_PASSTHRU:
   case AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU:
@@ -1066,6 +1068,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     // splat of 0 or undef) once vector selects supported in SVE codegen. See
     // D68877 for more details.
     for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64}) {
+      setOperationAction(ISD::BITREVERSE, VT, Custom);
+      setOperationAction(ISD::BSWAP, VT, Custom);
       setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
       setOperationAction(ISD::UINT_TO_FP, VT, Custom);
       setOperationAction(ISD::SINT_TO_FP, VT, Custom);
@@ -1183,6 +1187,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
         setOperationAction(ISD::FP_ROUND, VT, Expand);
 
       // These operations are not supported on NEON but SVE can do them.
+      setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom);
       setOperationAction(ISD::MUL, MVT::v1i64, Custom);
       setOperationAction(ISD::MUL, MVT::v2i64, Custom);
       setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
@@ -1217,6 +1222,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
       // Int operations with no NEON support.
       for (auto VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,
                       MVT::v2i32, MVT::v4i32, MVT::v2i64}) {
+        setOperationAction(ISD::BITREVERSE, VT, Custom);
         setOperationAction(ISD::VECREDUCE_AND, VT, Custom);
         setOperationAction(ISD::VECREDUCE_OR, VT, Custom);
         setOperationAction(ISD::VECREDUCE_XOR, VT, Custom);
@@ -1330,6 +1336,8 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
   setOperationAction(ISD::ADD, VT, Custom);
   setOperationAction(ISD::AND, VT, Custom);
   setOperationAction(ISD::ANY_EXTEND, VT, Custom);
+  setOperationAction(ISD::BITREVERSE, VT, Custom);
+  setOperationAction(ISD::BSWAP, VT, Custom);
   setOperationAction(ISD::FADD, VT, Custom);
   setOperationAction(ISD::FCEIL, VT, Custom);
   setOperationAction(ISD::FDIV, VT, Custom);
@@ -1934,6 +1942,8 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
     MAKE_CASE(AArch64ISD::LDP)
     MAKE_CASE(AArch64ISD::STP)
     MAKE_CASE(AArch64ISD::STNP)
+    MAKE_CASE(AArch64ISD::BITREVERSE_MERGE_PASSTHRU)
+    MAKE_CASE(AArch64ISD::BSWAP_MERGE_PASSTHRU)
     MAKE_CASE(AArch64ISD::DUP_MERGE_PASSTHRU)
     MAKE_CASE(AArch64ISD::INDEX_VECTOR)
     MAKE_CASE(AArch64ISD::UABD)
@@ -3646,7 +3656,13 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     return DAG.getNode(AArch64ISD::INSR, dl, Op.getValueType(),
                        Op.getOperand(1), Scalar);
   }
-
+  case Intrinsic::aarch64_sve_rbit:
+    return DAG.getNode(AArch64ISD::BITREVERSE_MERGE_PASSTHRU, dl,
+                       Op.getValueType(), Op.getOperand(2), Op.getOperand(3),
+                       Op.getOperand(1));
+  case Intrinsic::aarch64_sve_revb:
+    return DAG.getNode(AArch64ISD::BSWAP_MERGE_PASSTHRU, dl, Op.getValueType(),
+                       Op.getOperand(2), Op.getOperand(3), Op.getOperand(1));
   case Intrinsic::aarch64_sve_sxtb:
     return DAG.getNode(
         AArch64ISD::SIGN_EXTEND_INREG_MERGE_PASSTHRU, dl, Op.getValueType(),
@@ -4357,6 +4373,11 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
     return LowerFixedLengthVectorSelectToSVE(Op, DAG);
   case ISD::ABS:
     return LowerABS(Op, DAG);
+  case ISD::BITREVERSE:
+    return LowerToPredicatedOp(Op, DAG, AArch64ISD::BITREVERSE_MERGE_PASSTHRU,
+                               /*OverrideNEON=*/true);
+  case ISD::BSWAP:
+    return LowerToPredicatedOp(Op, DAG, AArch64ISD::BSWAP_MERGE_PASSTHRU);
   }
 }
 
@@ -15884,7 +15905,8 @@ void AArch64TargetLowering::ReplaceNodeResults(
     return;
 
   case ISD::CTPOP:
-    Results.push_back(LowerCTPOP(SDValue(N, 0), DAG));
+    if (SDValue Result = LowerCTPOP(SDValue(N, 0), DAG))
+      Results.push_back(Result);
     return;
   case AArch64ISD::SADDV:
     ReplaceReductionResults(N, Results, DAG, ISD::ADD, AArch64ISD::SADDV);
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 96da82e487619..36518a5349b4a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -305,6 +305,8 @@ enum NodeType : unsigned {
   PTEST,
   PTRUE,
 
+  BITREVERSE_MERGE_PASSTHRU,
+  BSWAP_MERGE_PASSTHRU,
   DUP_MERGE_PASSTHRU,
   INDEX_VECTOR,
 
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 86cfdf8f7cf97..954b0960fc027 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -333,9 +333,9 @@ bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF,
 }
 
 bool AArch64RegisterInfo::isAnyArgRegReserved(const MachineFunction &MF) const {
-  return std::any_of(std::begin(*AArch64::GPR64argRegClass.MC),
-                     std::end(*AArch64::GPR64argRegClass.MC),
-                     [this, &MF](MCPhysReg r){return isReservedReg(MF, r);});
+  return llvm::any_of(*AArch64::GPR64argRegClass.MC, [this, &MF](MCPhysReg r) {
+    return isReservedReg(MF, r);
+  });
 }
 
 void AArch64RegisterInfo::emitReservedArgRegCallError(
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index f28c55ae22e66..e9a823c6c4136 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -214,6 +214,8 @@ def AArch64frintn_mt : SDNode<"AArch64ISD::FROUNDEVEN_MERGE_PASSTHRU", SDT_AArch
 def AArch64frintz_mt : SDNode<"AArch64ISD::FTRUNC_MERGE_PASSTHRU", SDT_AArch64Arith>;
 def AArch64fsqrt_mt  : SDNode<"AArch64ISD::FSQRT_MERGE_PASSTHRU", SDT_AArch64Arith>;
 def AArch64frecpx_mt : SDNode<"AArch64ISD::FRECPX_MERGE_PASSTHRU", SDT_AArch64Arith>;
+def AArch64rbit_mt   : SDNode<"AArch64ISD::BITREVERSE_MERGE_PASSTHRU", SDT_AArch64Arith>;
+def AArch64revb_mt   : SDNode<"AArch64ISD::BSWAP_MERGE_PASSTHRU", SDT_AArch64Arith>;
 
 def SDT_AArch64FCVT : SDTypeProfile<1, 3, [
   SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>,
@@ -571,8 +573,8 @@ let Predicates = [HasSVE] in {
   defm INSR_ZV : sve_int_perm_insrv<"insr", AArch64insr>;
   defm EXT_ZZI : sve_int_perm_extract_i<"ext", AArch64ext>;
 
-  defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit", int_aarch64_sve_rbit>;
-  defm REVB_ZPmZ : sve_int_perm_rev_revb<"revb", int_aarch64_sve_revb, bswap>;
+  defm RBIT_ZPmZ : sve_int_perm_rev_rbit<"rbit", AArch64rbit_mt>;
+  defm REVB_ZPmZ : sve_int_perm_rev_revb<"revb", AArch64revb_mt>;
   defm REVH_ZPmZ : sve_int_perm_rev_revh<"revh", int_aarch64_sve_revh>;
   defm REVW_ZPmZ : sve_int_perm_rev_revw<"revw", int_aarch64_sve_revw>;
 
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 4126017c6fbde..c810fcaca7663 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -574,7 +574,7 @@ static Optional<uint64_t> getImmedFromMO(const MachineOperand &Root) {
         getConstantVRegValWithLookThrough(Root.getReg(), MRI, true);
     if (!ValAndVReg)
       return None;
-    Immed = ValAndVReg->Value;
+    Immed = ValAndVReg->Value.getSExtValue();
   } else
     return None;
   return Immed;
@@ -1109,8 +1109,8 @@ AArch64InstructionSelector::emitSelect(Register Dst, Register True,
 
     Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
     if (TrueCst && FalseCst) {
-      auto T = TrueCst->Value;
-      auto F = FalseCst->Value;
+      int64_t T = TrueCst->Value.getSExtValue();
+      int64_t F = FalseCst->Value.getSExtValue();
 
       if (T == 0 && F == 1) {
         // G_SELECT cc, 0, 1 -> CSINC zreg, zreg, cc
@@ -1130,7 +1130,7 @@ AArch64InstructionSelector::emitSelect(Register Dst, Register True,
     }
 
     if (TrueCst) {
-      auto T = TrueCst->Value;
+      int64_t T = TrueCst->Value.getSExtValue();
       if (T == 1) {
         // G_SELECT cc, 1, f -> CSINC f, zreg, inv_cc
         Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
@@ -1151,7 +1151,7 @@ AArch64InstructionSelector::emitSelect(Register Dst, Register True,
     }
 
     if (FalseCst) {
-      auto F = FalseCst->Value;
+      int64_t F = FalseCst->Value.getSExtValue();
       if (F == 1) {
         // G_SELECT cc, t, 1 -> CSINC t, zreg, cc
         Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
@@ -1304,7 +1304,7 @@ static Register getTestBitReg(Register Reg, uint64_t &Bit, bool &Invert,
         VRegAndVal = getConstantVRegValWithLookThrough(ConstantReg, MRI);
       }
       if (VRegAndVal)
-        C = VRegAndVal->Value;
+        C = VRegAndVal->Value.getSExtValue();
       break;
     }
     case TargetOpcode::G_ASHR:
@@ -1314,7 +1314,7 @@ static Register getTestBitReg(Register Reg, uint64_t &Bit, bool &Invert,
       auto VRegAndVal =
           getConstantVRegValWithLookThrough(MI->getOperand(2).getReg(), MRI);
       if (VRegAndVal)
-        C = VRegAndVal->Value;
+        C = VRegAndVal->Value.getSExtValue();
       break;
     }
     }
@@ -1442,10 +1442,13 @@ bool AArch64InstructionSelector::tryOptAndIntoCompareBranch(
   // (e.g, ANDing with 8 == ANDing with 000...100 == testing if bit 3 is set)
   auto MaybeBit = getConstantVRegValWithLookThrough(
       AndInst.getOperand(2).getReg(), *MIB.getMRI());
-  if (!MaybeBit || !isPowerOf2_64(MaybeBit->Value))
+  if (!MaybeBit)
+    return false;
+
+  int32_t Bit = MaybeBit->Value.exactLogBase2();
+  if (Bit < 0)
     return false;
 
-  uint64_t Bit = Log2_64(static_cast<uint64_t>(MaybeBit->Value));
   Register TestReg = AndInst.getOperand(1).getReg();
 
   // Emit a TB(N)Z.
@@ -1522,7 +1525,7 @@ bool AArch64InstructionSelector::tryOptCompareBranchFedByICmp(
   // Note that we don't want to do this when we have a G_AND because it can
   // become a tst. The tst will make the test bit in the TB(N)Z redundant.
   if (VRegAndVal && !AndInst) {
-    int64_t C = VRegAndVal->Value;
+    int64_t C = VRegAndVal->Value.getSExtValue();
 
     // When we have a greater-than comparison, we can just test if the msb is
     // zero.
@@ -1654,8 +1657,8 @@ static Optional<int64_t> getVectorShiftImm(Register Reg,
       return None;
 
     if (Idx == 1)
-      ImmVal = VRegAndVal->Value;
-    if (ImmVal != VRegAndVal->Value)
+      ImmVal = VRegAndVal->Value.getSExtValue();
+    if (ImmVal != VRegAndVal->Value.getSExtValue())
       return None;
   }
 
@@ -2735,7 +2738,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
 
   case TargetOpcode::G_PTRMASK: {
     Register MaskReg = I.getOperand(2).getReg();
-    Optional<int64_t> MaskVal = getConstantVRegVal(MaskReg, MRI);
+    Optional<int64_t> MaskVal = getConstantVRegSExtVal(MaskReg, MRI);
     // TODO: Implement arbitrary cases
     if (!MaskVal || !isShiftedMask_64(*MaskVal))
       return false;
@@ -3749,7 +3752,7 @@ bool AArch64InstructionSelector::selectExtractElt(
   auto VRegAndVal = getConstantVRegValWithLookThrough(LaneIdxOp.getReg(), MRI);
   if (!VRegAndVal)
     return false;
-  unsigned LaneIdx = VRegAndVal->Value;
+  unsigned LaneIdx = VRegAndVal->Value.getSExtValue();
 
   MachineIRBuilder MIRBuilder(I);
 
@@ -4116,10 +4119,11 @@ AArch64InstructionSelector::emitTST(MachineOperand &LHS, MachineOperand &RHS,
   // ANDS needs a logical immediate for its immediate form. Check if we can
   // fold one in.
   if (auto ValAndVReg = getConstantVRegValWithLookThrough(RHS.getReg(), MRI)) {
-    if (AArch64_AM::isLogicalImmediate(ValAndVReg->Value, RegSize)) {
+    int64_t Imm = ValAndVReg->Value.getSExtValue();
+
+    if (AArch64_AM::isLogicalImmediate(Imm, RegSize)) {
       auto TstMI = MIRBuilder.buildInstr(OpcTable[0][Is32Bit], {Ty}, {LHS});
-      TstMI.addImm(
-          AArch64_AM::encodeLogicalImmediate(ValAndVReg->Value, RegSize));
+      TstMI.addImm(AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
       constrainSelectedInstRegOperands(*TstMI, TII, TRI, RBI);
       return &*TstMI;
     }
@@ -4658,7 +4662,7 @@ bool AArch64InstructionSelector::selectInsertElt(
   auto VRegAndVal = getConstantVRegValWithLookThrough(IdxReg, MRI);
   if (!VRegAndVal)
     return false;
-  unsigned LaneIdx = VRegAndVal->Value;
+  unsigned LaneIdx = VRegAndVal->Value.getSExtValue();
 
   // Perform the lane insert.
   Register SrcReg = I.getOperand(1).getReg();
@@ -5198,7 +5202,7 @@ AArch64InstructionSelector::selectExtendedSHL(
 
   // The value must fit into 3 bits, and must be positive. Make sure that is
   // true.
-  int64_t ImmVal = ValAndVReg->Value;
+  int64_t ImmVal = ValAndVReg->Value.getSExtValue();
 
   // Since we're going to pull this into a shift, the constant value must be
   // a power of 2. If we got a multiply, then we need to check this.
@@ -5362,7 +5366,7 @@ AArch64InstructionSelector::selectAddrModeXRO(MachineOperand &Root,
       getConstantVRegValWithLookThrough(PtrAdd->getOperand(2).getReg(), MRI);
   if (ValAndVReg) {
     unsigned Scale = Log2_32(SizeInBytes);
-    int64_t ImmOff = ValAndVReg->Value;
+    int64_t ImmOff = ValAndVReg->Value.getSExtValue();
 
     // Skip immediates that can be selected in the load/store addresing
     // mode.
@@ -5821,7 +5825,8 @@ void AArch64InstructionSelector::renderTruncImm(MachineInstrBuilder &MIB,
   const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
          "Expected G_CONSTANT");
-  Optional<int64_t> CstVal = getConstantVRegVal(MI.getOperand(0).getReg(), MRI);
+  Optional<int64_t> CstVal =
+      getConstantVRegSExtVal(MI.getOperand(0).getReg(), MRI);
   assert(CstVal && "Expected constant value");
   MIB.addImm(CstVal.getValue());
 }
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 73a7b8e7b83ff..a611d68cb2e51 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -837,11 +837,13 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr(
   if (!VRegAndVal)
     return true;
   // Check the shift amount is in range for an immediate form.
-  int64_t Amount = VRegAndVal->Value;
+  int64_t Amount = VRegAndVal->Value.getSExtValue();
   if (Amount > 31)
     return true; // This will have to remain a register variant.
   auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount);
+  Observer.changingInstr(MI);
   MI.getOperand(2).setReg(ExtCst.getReg(0));
+  Observer.changedInstr(MI);
   return true;
 }
 
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index ce298c766e41f..fdd04cb77fad3 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -130,7 +130,7 @@ bool matchAArch64MulConstCombine(
   if (!Const)
     return false;
 
-  const APInt &ConstValue = APInt(Ty.getSizeInBits(), Const->Value, true);
+  const APInt ConstValue = Const->Value.sextOrSelf(Ty.getSizeInBits());
   // The following code is ported from AArch64ISelLowering.
   // Multiplication of a power of two plus/minus one can be done more
   // cheaply as as shift+add/sub. For now, this is true unilaterally. If
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index 43f28729baa1f..a06ff4b5417a6 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -438,7 +438,7 @@ tryAdjustICmpImmAndPred(Register RHS, CmpInst::Predicate P,
   auto ValAndVReg = getConstantVRegValWithLookThrough(RHS, MRI);
   if (!ValAndVReg)
     return None;
-  uint64_t C = ValAndVReg->Value;
+  uint64_t C = ValAndVReg->Value.getZExtValue();
   if (isLegalArithImmed(C))
     return None;
 
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index c4b4d95cd46d3..b5077cf263e74 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -6012,26 +6012,20 @@ multiclass sve_int_perm_rev_rbit<string asm, SDPatternOperator op> {
   def _S : sve_int_perm_rev<0b10, 0b11, asm, ZPR32>;
   def _D : sve_int_perm_rev<0b11, 0b11, asm, ZPR64>;
 
-  def : SVE_3_Op_Pat<nxv16i8, op, nxv16i8, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
-  def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv8i1,  nxv8i16, !cast<Instruction>(NAME # _H)>;
-  def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv4i1,  nxv4i32, !cast<Instruction>(NAME # _S)>;
-  def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i1,  nxv2i64, !cast<Instruction>(NAME # _D)>;
+  def : SVE_1_Op_Passthru_Pat<nxv16i8, op, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
+  def : SVE_1_Op_Passthru_Pat<nxv8i16, op, nxv8i1,  nxv8i16, !cast<Instruction>(NAME # _H)>;
+  def : SVE_1_Op_Passthru_Pat<nxv4i32, op, nxv4i1,  nxv4i32, !cast<Instruction>(NAME # _S)>;
+  def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1,  nxv2i64, !cast<Instruction>(NAME # _D)>;
 }
 
-multiclass sve_int_perm_rev_revb<string asm,
-                                 SDPatternOperator int_op,
-                                 SDPatternOperator ir_op> {
+multiclass sve_int_perm_rev_revb<string asm, SDPatternOperator op> {
   def _H : sve_int_perm_rev<0b01, 0b00, asm, ZPR16>;
   def _S : sve_int_perm_rev<0b10, 0b00, asm, ZPR32>;
   def _D : sve_int_perm_rev<0b11, 0b00, asm, ZPR64>;
 
-  def : SVE_3_Op_Pat<nxv8i16, int_op, nxv8i16, nxv8i1,  nxv8i16, !cast<Instruction>(NAME # _H)>;
-  def : SVE_3_Op_Pat<nxv4i32, int_op, nxv4i32, nxv4i1,  nxv4i32, !cast<Instruction>(NAME # _S)>;
-  def : SVE_3_Op_Pat<nxv2i64, int_op, nxv2i64, nxv2i1,  nxv2i64, !cast<Instruction>(NAME # _D)>;
-
-  def : SVE_1_Op_AllActive_Pat<nxv8i16, ir_op, nxv8i16, !cast<Instruction>(NAME # _H), PTRUE_H>;
-  def : SVE_1_Op_AllActive_Pat<nxv4i32, ir_op, nxv4i32, !cast<Instruction>(NAME # _S), PTRUE_S>;
-  def : SVE_1_Op_AllActive_Pat<nxv2i64, ir_op, nxv2i64, !cast<Instruction>(NAME # _D), PTRUE_D>;
+  def : SVE_1_Op_Passthru_Pat<nxv8i16, op, nxv8i1,  nxv8i16, !cast<Instruction>(NAME # _H)>;
+  def : SVE_1_Op_Passthru_Pat<nxv4i32, op, nxv4i1,  nxv4i32, !cast<Instruction>(NAME # _S)>;
+  def : SVE_1_Op_Passthru_Pat<nxv2i64, op, nxv2i1,  nxv2i64, !cast<Instruction>(NAME # _D)>;
 }
 
 multiclass sve_int_perm_rev_revh<string asm, SDPatternOperator op> {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 132036fbcfd03..22d264e2880b3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -10,8 +10,9 @@
 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
 #define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
 
-#include "llvm/IR/IntrinsicsR600.h" // TODO: Sink this.
 #include "llvm/IR/IntrinsicsAMDGPU.h" // TODO: Sink this.
+#include "llvm/IR/IntrinsicsR600.h"   // TODO: Sink this.
+#include "llvm/IR/PassManager.h"
 #include "llvm/Support/CodeGen.h"
 
 namespace llvm {
@@ -75,6 +76,14 @@ ModulePass *createAMDGPUPropagateAttributesLatePass(const TargetMachine *);
 FunctionPass *createAMDGPURewriteOutArgumentsPass();
 FunctionPass *createSIModeRegisterPass();
 
+struct AMDGPUSimplifyLibCallsPass : PassInfoMixin<AMDGPUSimplifyLibCallsPass> {
+  PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+};
+
+struct AMDGPUUseNativeCallsPass : PassInfoMixin<AMDGPUUseNativeCallsPass> {
+  PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+};
+
 void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
 
 void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
index 661b96a6a98e2..bba03736d01ae 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUGISel.td
@@ -85,6 +85,14 @@ def gi_mubuf_scratch_offen :
     GIComplexOperandMatcher<s32, "selectMUBUFScratchOffen">,
     GIComplexPatternEquiv<MUBUFScratchOffen>;
 
+def gi_flat_scratch_offset :
+    GIComplexOperandMatcher<s32, "selectFlatOffsetSigned">,
+    GIComplexPatternEquiv<ScratchOffset>;
+
+def gi_flat_scratch_saddr :
+    GIComplexOperandMatcher<s32, "selectScratchSAddr">,
+    GIComplexPatternEquiv<ScratchSAddr>;
+
 def gi_ds_1addr_1offset :
     GIComplexOperandMatcher<s32, "selectDS1Addr1Offset">,
     GIComplexPatternEquiv<DS1Addr1Offset>;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index b157c03672d12..bfac1b412051e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -611,8 +611,10 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR_TRUNC(
   if (ConstSrc1) {
     auto ConstSrc0 = getConstantVRegValWithLookThrough(Src0, *MRI, true, true);
     if (ConstSrc0) {
-      uint32_t Lo16 = static_cast<uint32_t>(ConstSrc0->Value) & 0xffff;
-      uint32_t Hi16 = static_cast<uint32_t>(ConstSrc1->Value) & 0xffff;
+      const int64_t K0 = ConstSrc0->Value.getSExtValue();
+      const int64_t K1 = ConstSrc1->Value.getSExtValue();
+      uint32_t Lo16 = static_cast<uint32_t>(K0) & 0xffff;
+      uint32_t Hi16 = static_cast<uint32_t>(K1) & 0xffff;
 
       BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_MOV_B32), Dst)
         .addImm(Lo16 | (Hi16 << 16));
@@ -820,7 +822,7 @@ bool AMDGPUInstructionSelector::selectWritelane(MachineInstr &MI) const {
     // The selector has to be an inline immediate, so we can use whatever for
     // the other operands.
     MIB.addReg(Val);
-    MIB.addImm(ConstSelect->Value &
+    MIB.addImm(ConstSelect->Value.getSExtValue() &
                maskTrailingOnes<uint64_t>(STI.getWavefrontSizeLog2()));
   } else {
     Optional<ValueAndVReg> ConstVal =
@@ -828,9 +830,9 @@ bool AMDGPUInstructionSelector::selectWritelane(MachineInstr &MI) const {
 
     // If the value written is an inline immediate, we can get away without a
     // copy to m0.
-    if (ConstVal && AMDGPU::isInlinableLiteral32(ConstVal->Value,
+    if (ConstVal && AMDGPU::isInlinableLiteral32(ConstVal->Value.getSExtValue(),
                                                  STI.hasInv2PiInlineImm())) {
-      MIB.addImm(ConstVal->Value);
+      MIB.addImm(ConstVal->Value.getSExtValue());
       MIB.addReg(LaneSelect);
     } else {
       MIB.addReg(Val);
@@ -1101,7 +1103,7 @@ bool AMDGPUInstructionSelector::selectBallot(MachineInstr &I) const {
       getConstantVRegValWithLookThrough(I.getOperand(2).getReg(), *MRI, true);
 
   if (Arg.hasValue()) {
-    const int64_t Value = Arg.getValue().Value;
+    const int64_t Value = Arg.getValue().Value.getSExtValue();
     if (Value == 0) {
       unsigned Opcode = Is64 ? AMDGPU::S_MOV_B64 : AMDGPU::S_MOV_B32;
       BuildMI(*BB, &I, DL, TII.get(Opcode), DstReg).addImm(0);
@@ -3425,22 +3427,18 @@ AMDGPUInstructionSelector::selectFlatOffsetImpl(MachineOperand &Root) const {
   if (!STI.hasFlatInstOffsets())
     return Default;
 
-  const MachineInstr *OpDef = MRI->getVRegDef(Root.getReg());
-  if (!OpDef || OpDef->getOpcode() != AMDGPU::G_PTR_ADD)
-    return Default;
-
-  Optional<int64_t> Offset =
-    getConstantVRegVal(OpDef->getOperand(2).getReg(), *MRI);
-  if (!Offset.hasValue())
+  Register PtrBase;
+  int64_t ConstOffset;
+  std::tie(PtrBase, ConstOffset) =
+      getPtrBaseWithConstantOffset(Root.getReg(), *MRI);
+  if (ConstOffset == 0)
     return Default;
 
   unsigned AddrSpace = (*MI->memoperands_begin())->getAddrSpace();
-  if (!TII.isLegalFLATOffset(Offset.getValue(), AddrSpace, Signed))
+  if (!TII.isLegalFLATOffset(ConstOffset, AddrSpace, Signed))
     return Default;
 
-  Register BasePtr = OpDef->getOperand(1).getReg();
-
-  return std::make_pair(BasePtr, Offset.getValue());
+  return std::make_pair(PtrBase, ConstOffset);
 }
 
 InstructionSelector::ComplexRendererFns
@@ -3589,6 +3587,67 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root) const {
            }}};
 }
 
+InstructionSelector::ComplexRendererFns
+AMDGPUInstructionSelector::selectScratchSAddr(MachineOperand &Root) const {
+  Register Addr = Root.getReg();
+  Register PtrBase;
+  int64_t ConstOffset;
+  int64_t ImmOffset = 0;
+
+  // Match the immediate offset first, which canonically is moved as low as
+  // possible.
+  std::tie(PtrBase, ConstOffset) = getPtrBaseWithConstantOffset(Addr, *MRI);
+
+  if (ConstOffset != 0 &&
+      TII.isLegalFLATOffset(ConstOffset, AMDGPUAS::PRIVATE_ADDRESS, true)) {
+    Addr = PtrBase;
+    ImmOffset = ConstOffset;
+  }
+
+  auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI);
+  if (!AddrDef)
+    return None;
+
+  if (AddrDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX) {
+    int FI = AddrDef->MI->getOperand(1).getIndex();
+    return {{
+        [=](MachineInstrBuilder &MIB) { MIB.addFrameIndex(FI); }, // saddr
+        [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset
+    }};
+  }
+
+  Register SAddr = AddrDef->Reg;
+
+  if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) {
+    Register LHS = AddrDef->MI->getOperand(1).getReg();
+    Register RHS = AddrDef->MI->getOperand(2).getReg();
+    auto LHSDef = getDefSrcRegIgnoringCopies(LHS, *MRI);
+    auto RHSDef = getDefSrcRegIgnoringCopies(RHS, *MRI);
+
+    if (LHSDef && RHSDef &&
+        LHSDef->MI->getOpcode() == AMDGPU::G_FRAME_INDEX &&
+        isSGPR(RHSDef->Reg)) {
+      int FI = LHSDef->MI->getOperand(1).getIndex();
+      MachineInstr &I = *Root.getParent();
+      MachineBasicBlock *BB = I.getParent();
+      const DebugLoc &DL = I.getDebugLoc();
+      SAddr = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass);
+
+      BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), SAddr)
+        .addFrameIndex(FI)
+        .addReg(RHSDef->Reg);
+    }
+  }
+
+  if (!isSGPR(SAddr))
+    return None;
+
+  return {{
+      [=](MachineInstrBuilder &MIB) { MIB.addReg(SAddr); }, // saddr
+      [=](MachineInstrBuilder &MIB) { MIB.addImm(ImmOffset); } // offset
+  }};
+}
+
 static bool isStackPtrRelative(const MachinePointerInfo &PtrInfo) {
   auto PSV = PtrInfo.V.dyn_cast<const PseudoSourceValue *>();
   return PSV && PSV->isStack();
@@ -3858,7 +3917,7 @@ AMDGPUInstructionSelector::getPtrBaseWithConstantOffset(
     = getConstantVRegValWithLookThrough(RHS.getReg(), MRI, true);
   if (!MaybeOffset)
     return {Root, 0};
-  return {RootI->getOperand(1).getReg(), MaybeOffset->Value};
+  return {RootI->getOperand(1).getReg(), MaybeOffset->Value.getSExtValue()};
 }
 
 static void addZeroImm(MachineInstrBuilder &MIB) {
@@ -4186,7 +4245,7 @@ AMDGPUInstructionSelector::selectMUBUFOffsetAtomic(MachineOperand &Root) const {
 static Optional<uint64_t> getConstantZext32Val(Register Reg,
                                                const MachineRegisterInfo &MRI) {
   // getConstantVRegVal sexts any values, so see if that matters.
-  Optional<int64_t> OffsetVal = getConstantVRegVal(Reg, MRI);
+  Optional<int64_t> OffsetVal = getConstantVRegSExtVal(Reg, MRI);
   if (!OffsetVal || !isInt<32>(*OffsetVal))
     return None;
   return Lo_32(*OffsetVal);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
index c575e7e9c8a5d..c6b26ea706596 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
@@ -200,6 +200,9 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
   InstructionSelector::ComplexRendererFns
   selectGlobalSAddr(MachineOperand &Root) const;
 
+  InstructionSelector::ComplexRendererFns
+  selectScratchSAddr(MachineOperand &Root) const;
+
   InstructionSelector::ComplexRendererFns
   selectMUBUFScratchOffen(MachineOperand &Root) const;
   InstructionSelector::ComplexRendererFns
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 9b39b86ae28fc..8c733a2afa032 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -240,7 +240,7 @@ static unsigned maxSizeForAddrSpace(const GCNSubtarget &ST, unsigned AS,
   switch (AS) {
   case AMDGPUAS::PRIVATE_ADDRESS:
     // FIXME: Private element size.
-    return 32;
+    return ST.enableFlatScratch() ? 128 : 32;
   case AMDGPUAS::LOCAL_ADDRESS:
     return ST.useDS128() ? 128 : 64;
   case AMDGPUAS::GLOBAL_ADDRESS:
@@ -2087,10 +2087,11 @@ bool AMDGPULegalizerInfo::legalizeExtractVectorElt(
   // FIXME: Artifact combiner probably should have replaced the truncated
   // constant before this, so we shouldn't need
   // getConstantVRegValWithLookThrough.
-  Optional<ValueAndVReg> IdxVal = getConstantVRegValWithLookThrough(
-    MI.getOperand(2).getReg(), MRI);
-  if (!IdxVal) // Dynamic case will be selected to register indexing.
+  Optional<ValueAndVReg> MaybeIdxVal =
+      getConstantVRegValWithLookThrough(MI.getOperand(2).getReg(), MRI);
+  if (!MaybeIdxVal) // Dynamic case will be selected to register indexing.
     return true;
+  const int64_t IdxVal = MaybeIdxVal->Value.getSExtValue();
 
   Register Dst = MI.getOperand(0).getReg();
   Register Vec = MI.getOperand(1).getReg();
@@ -2099,8 +2100,8 @@ bool AMDGPULegalizerInfo::legalizeExtractVectorElt(
   LLT EltTy = VecTy.getElementType();
   assert(EltTy == MRI.getType(Dst));
 
-  if (IdxVal->Value < VecTy.getNumElements())
-    B.buildExtract(Dst, Vec, IdxVal->Value * EltTy.getSizeInBits());
+  if (IdxVal < VecTy.getNumElements())
+    B.buildExtract(Dst, Vec, IdxVal * EltTy.getSizeInBits());
   else
     B.buildUndef(Dst);
 
@@ -2118,11 +2119,12 @@ bool AMDGPULegalizerInfo::legalizeInsertVectorElt(
   // FIXME: Artifact combiner probably should have replaced the truncated
   // constant before this, so we shouldn't need
   // getConstantVRegValWithLookThrough.
-  Optional<ValueAndVReg> IdxVal = getConstantVRegValWithLookThrough(
-    MI.getOperand(3).getReg(), MRI);
-  if (!IdxVal) // Dynamic case will be selected to register indexing.
+  Optional<ValueAndVReg> MaybeIdxVal =
+      getConstantVRegValWithLookThrough(MI.getOperand(3).getReg(), MRI);
+  if (!MaybeIdxVal) // Dynamic case will be selected to register indexing.
     return true;
 
+  int64_t IdxVal = MaybeIdxVal->Value.getSExtValue();
   Register Dst = MI.getOperand(0).getReg();
   Register Vec = MI.getOperand(1).getReg();
   Register Ins = MI.getOperand(2).getReg();
@@ -2131,8 +2133,8 @@ bool AMDGPULegalizerInfo::legalizeInsertVectorElt(
   LLT EltTy = VecTy.getElementType();
   assert(EltTy == MRI.getType(Ins));
 
-  if (IdxVal->Value < VecTy.getNumElements())
-    B.buildInsert(Dst, Vec, Ins, IdxVal->Value * EltTy.getSizeInBits());
+  if (IdxVal < VecTy.getNumElements())
+    B.buildInsert(Dst, Vec, Ins, IdxVal * EltTy.getSizeInBits());
   else
     B.buildUndef(Dst);
 
@@ -2643,7 +2645,7 @@ bool AMDGPULegalizerInfo::legalizeBuildVector(
 static bool isNot(const MachineRegisterInfo &MRI, const MachineInstr &MI) {
   if (MI.getOpcode() != TargetOpcode::G_XOR)
     return false;
-  auto ConstVal = getConstantVRegVal(MI.getOperand(2).getReg(), MRI);
+  auto ConstVal = getConstantVRegSExtVal(MI.getOperand(2).getReg(), MRI);
   return ConstVal && *ConstVal == -1;
 }
 
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
index a72f16956e727..eedcb2e1a793a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
@@ -26,6 +26,7 @@
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/Module.h"
+#include "llvm/IR/PassManager.h"
 #include "llvm/IR/ValueSymbolTable.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Support/Debug.h"
@@ -1750,6 +1751,40 @@ bool AMDGPUSimplifyLibCalls::runOnFunction(Function &F) {
   return Changed;
 }
 
+PreservedAnalyses AMDGPUSimplifyLibCallsPass::run(Function &F,
+                                                  FunctionAnalysisManager &AM) {
+  AMDGPULibCalls Simplifier;
+  Simplifier.initNativeFuncs();
+
+  bool Changed = false;
+  auto AA = &AM.getResult<AAManager>(F);
+
+  LLVM_DEBUG(dbgs() << "AMDIC: process function ";
+             F.printAsOperand(dbgs(), false, F.getParent()); dbgs() << '\n';);
+
+  for (auto &BB : F) {
+    for (BasicBlock::iterator I = BB.begin(), E = BB.end(); I != E;) {
+      // Ignore non-calls.
+      CallInst *CI = dyn_cast<CallInst>(I);
+      ++I;
+      // Ignore intrinsics that do not become real instructions.
+      if (!CI || isa<DbgInfoIntrinsic>(CI) || CI->isLifetimeStartOrEnd())
+        continue;
+
+      // Ignore indirect calls.
+      Function *Callee = CI->getCalledFunction();
+      if (Callee == 0)
+        continue;
+
+      LLVM_DEBUG(dbgs() << "AMDIC: try folding " << *CI << "\n";
+                 dbgs().flush());
+      if (Simplifier.fold(CI, AA))
+        Changed = true;
+    }
+  }
+  return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all();
+}
+
 bool AMDGPUUseNativeCalls::runOnFunction(Function &F) {
   if (skipFunction(F) || UseNative.empty())
     return false;
@@ -1772,3 +1807,32 @@ bool AMDGPUUseNativeCalls::runOnFunction(Function &F) {
   }
   return Changed;
 }
+
+PreservedAnalyses AMDGPUUseNativeCallsPass::run(Function &F,
+                                                FunctionAnalysisManager &AM) {
+  if (UseNative.empty())
+    return PreservedAnalyses::all();
+
+  AMDGPULibCalls Simplifier;
+  Simplifier.initNativeFuncs();
+
+  bool Changed = false;
+  for (auto &BB : F) {
+    for (BasicBlock::iterator I = BB.begin(), E = BB.end(); I != E;) {
+      // Ignore non-calls.
+      CallInst *CI = dyn_cast<CallInst>(I);
+      ++I;
+      if (!CI)
+        continue;
+
+      // Ignore indirect calls.
+      Function *Callee = CI->getCalledFunction();
+      if (Callee == 0)
+        continue;
+
+      if (Simplifier.useNative(CI))
+        Changed = true;
+    }
+  }
+  return Changed ? PreservedAnalyses::none() : PreservedAnalyses::all();
+}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index 6168b50f9cefd..54124d7b5a6eb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -1331,7 +1331,7 @@ static unsigned setBufferOffsets(MachineIRBuilder &B,
   const LLT S32 = LLT::scalar(32);
   MachineRegisterInfo *MRI = B.getMRI();
 
-  if (Optional<int64_t> Imm = getConstantVRegVal(CombinedOffset, *MRI)) {
+  if (Optional<int64_t> Imm = getConstantVRegSExtVal(CombinedOffset, *MRI)) {
     uint32_t SOffset, ImmOffset;
     if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget,
                                  Alignment)) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
index edc5fe2871678..85d26cd4d0ff7 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteOutArguments.cpp
@@ -325,9 +325,10 @@ bool AMDGPURewriteOutArguments::runOnFunction(Function &F) {
         Value *ReplVal = Store.second->getValueOperand();
 
         auto &ValVec = Replacements[Store.first];
-        if (llvm::find_if(ValVec,
-              [OutArg](const std::pair<Argument *, Value *> &Entry) {
-                 return Entry.first == OutArg;}) != ValVec.end()) {
+        if (llvm::any_of(ValVec,
+                         [OutArg](const std::pair<Argument *, Value *> &Entry) {
+                           return Entry.first == OutArg;
+                         })) {
           LLVM_DEBUG(dbgs()
                      << "Saw multiple out arg stores" << *OutArg << '\n');
           // It is possible to see stores to the same argument multiple times,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
index 8015eb5734e30..2b84107dcbea0 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp
@@ -89,7 +89,8 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
   // Assuming ECC is enabled is the conservative default.
   SmallString<256> FullFS("+promote-alloca,+load-store-opt,+enable-ds128,+sram-ecc,+xnack,");
 
-  if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA.
+  // Turn on features that HSA ABI requires. Also turn on FlatForGlobal by default
+  if (isAmdHsaOS())
     FullFS += "+flat-for-global,+unaligned-access-mode,+trap-handler,";
 
   FullFS += "+enable-prt-strict-null,"; // This is overridden by a disable in FS
@@ -108,15 +109,36 @@ GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
 
   ParseSubtargetFeatures(GPU, /*TuneCPU*/ GPU, FullFS);
 
+  // Implement the "generic" processors, which acts as the default when no
+  // generation features are enabled (e.g for -mcpu=''). HSA OS defaults to
+  // the first amdgcn target that supports flat addressing. Other OSes defaults
+  // to the first amdgcn target.
+  if (Gen == AMDGPUSubtarget::INVALID) {
+     Gen = TT.getOS() == Triple::AMDHSA ? AMDGPUSubtarget::SEA_ISLANDS
+                                        : AMDGPUSubtarget::SOUTHERN_ISLANDS;
+  }
+
   // We don't support FP64 for EG/NI atm.
   assert(!hasFP64() || (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS));
 
-  // Unless +-flat-for-global is specified, turn on FlatForGlobal for all OS-es
-  // on VI and newer hardware to avoid assertion failures due to missing ADDR64
-  // variants of MUBUF instructions.
-  if (!hasAddr64() && !FS.contains("flat-for-global")) {
+  // Targets must either support 64-bit offsets for MUBUF instructions, and/or
+  // support flat operations, otherwise they cannot access a 64-bit global
+  // address space
+  assert(hasAddr64() || hasFlat());
+  // Unless +-flat-for-global is specified, turn on FlatForGlobal for targets
+  // that do not support ADDR64 variants of MUBUF instructions. Such targets
+  // cannot use a 64 bit offset with a MUBUF instruction to access the global
+  // address space
+  if (!hasAddr64() && !FS.contains("flat-for-global") && !FlatForGlobal) {
+    ToggleFeature(AMDGPU::FeatureFlatForGlobal);
     FlatForGlobal = true;
   }
+  // Unless +-flat-for-global is specified, use MUBUF instructions for global
+  // address space access if flat operations are not available.
+  if (!hasFlat() && !FS.contains("flat-for-global") && FlatForGlobal) {
+    ToggleFeature(AMDGPU::FeatureFlatForGlobal);
+    FlatForGlobal = false;
+  }
 
   // Set defaults if needed.
   if (MaxPrivateElementSize == 0)
@@ -182,7 +204,7 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
     AMDGPUGenSubtargetInfo(TT, GPU, /*TuneCPU*/ GPU, FS),
     AMDGPUSubtarget(TT),
     TargetTriple(TT),
-    Gen(TT.getOS() == Triple::AMDHSA ? SEA_ISLANDS : SOUTHERN_ISLANDS),
+    Gen(INVALID),
     InstrItins(getInstrItineraryForCPU(GPU)),
     LDSBankCount(0),
     MaxPrivateElementSize(0),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
index 0b0e4a5bea635..80d314ee3c52c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -50,15 +50,16 @@ class StringRef;
 class AMDGPUSubtarget {
 public:
   enum Generation {
-    R600 = 0,
-    R700 = 1,
-    EVERGREEN = 2,
-    NORTHERN_ISLANDS = 3,
-    SOUTHERN_ISLANDS = 4,
-    SEA_ISLANDS = 5,
-    VOLCANIC_ISLANDS = 6,
-    GFX9 = 7,
-    GFX10 = 8
+    INVALID = 0,
+    R600 = 1,
+    R700 = 2,
+    EVERGREEN = 3,
+    NORTHERN_ISLANDS = 4,
+    SOUTHERN_ISLANDS = 5,
+    SEA_ISLANDS = 6,
+    VOLCANIC_ISLANDS = 7,
+    GFX9 = 8,
+    GFX10 = 9
   };
 
 private:
@@ -527,6 +528,10 @@ class GCNSubtarget : public AMDGPUGenSubtargetInfo,
     return (getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS);
   }
 
+  bool hasFlat() const {
+    return (getGeneration() > AMDGPUSubtarget::SOUTHERN_ISLANDS);
+  }
+
   // Return true if the target only has the reverse operand versions of VALU
   // shift instructions (e.g. v_lshrrev_b32, and no v_lshr_b32).
   bool hasOnlyRevVALUShifts() const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index ccfd62ea3e093..6ea99bdf9206d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -40,8 +40,10 @@
 #include "llvm/IR/Attributes.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/LegacyPassManager.h"
+#include "llvm/IR/PassManager.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Pass.h"
+#include "llvm/Passes/PassBuilder.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/TargetRegistry.h"
@@ -52,6 +54,7 @@
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Transforms/Scalar/GVN.h"
 #include "llvm/Transforms/Utils.h"
+#include "llvm/Transforms/Utils/SimplifyLibCalls.h"
 #include "llvm/Transforms/Vectorize.h"
 #include <memory>
 
@@ -482,6 +485,33 @@ void AMDGPUTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
   });
 }
 
+void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB,
+                                                       bool DebugPassManager) {
+  PB.registerPipelineParsingCallback(
+      [](StringRef PassName, FunctionPassManager &PM,
+         ArrayRef<PassBuilder::PipelineElement>) {
+        if (PassName == "amdgpu-simplifylib") {
+          PM.addPass(AMDGPUSimplifyLibCallsPass());
+          return true;
+        }
+        if (PassName == "amdgpu-usenative") {
+          PM.addPass(AMDGPUUseNativeCallsPass());
+          return true;
+        }
+        return false;
+      });
+
+  PB.registerPipelineStartEPCallback([DebugPassManager](
+                                         ModulePassManager &PM,
+                                         PassBuilder::OptimizationLevel Level) {
+    FunctionPassManager FPM(DebugPassManager);
+    FPM.addPass(AMDGPUUseNativeCallsPass());
+    if (EnableLibCallSimplify && Level != PassBuilder::OptimizationLevel::O0)
+      FPM.addPass(AMDGPUSimplifyLibCallsPass());
+    PM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
+  });
+}
+
 //===----------------------------------------------------------------------===//
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index 56d3237832bed..d5fd769912d02 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -56,6 +56,9 @@ class AMDGPUTargetMachine : public LLVMTargetMachine {
 
   void adjustPassManager(PassManagerBuilder &) override;
 
+  void registerPassBuilderCallbacks(PassBuilder &PB,
+                                    bool DebugPassManager) override;
+
   /// Get the integer value of a null pointer in the given address space.
   static int64_t getNullPointerValue(unsigned AddrSpace) {
     return (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 6597b627f0efe..ae10b47d2e9b1 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1434,7 +1434,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
   bool trySkipToken(const AsmToken::TokenKind Kind);
   bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);
   bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string");
-  bool parseId(StringRef &Val, const StringRef ErrMsg);
+  bool parseId(StringRef &Val, const StringRef ErrMsg = "");
 
   void peekTokens(MutableArrayRef<AsmToken> Tokens);
   AsmToken::TokenKind getTokenKind() const;
@@ -2529,11 +2529,11 @@ bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,
   int64_t OldCount;
 
   if (!Sym->isVariable())
-    return !Error(getParser().getTok().getLoc(),
+    return !Error(getLoc(),
                   ".amdgcn.next_free_{v,s}gpr symbols must be variable");
   if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount))
     return !Error(
-        getParser().getTok().getLoc(),
+        getLoc(),
         ".amdgcn.next_free_{v,s}gpr symbols must be absolute expressions");
 
   if (OldCount <= NewMax)
@@ -2544,7 +2544,7 @@ bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,
 
 std::unique_ptr<AMDGPUOperand>
 AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
-  const auto &Tok = Parser.getTok();
+  const auto &Tok = getToken();
   SMLoc StartLoc = Tok.getLoc();
   SMLoc EndLoc = Tok.getEndLoc();
   RegisterKind RegKind;
@@ -4058,7 +4058,7 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
 
 bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
   int64_t Tmp = -1;
-  if (getLexer().isNot(AsmToken::Integer) && getLexer().isNot(AsmToken::Identifier)) {
+  if (!isToken(AsmToken::Integer) && !isToken(AsmToken::Identifier)) {
     return true;
   }
   if (getParser().parseAbsoluteExpression(Tmp)) {
@@ -4073,9 +4073,8 @@ bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
   if (ParseAsAbsoluteExpression(Major))
     return TokError("invalid major version");
 
-  if (getLexer().isNot(AsmToken::Comma))
+  if (!trySkipToken(AsmToken::Comma))
     return TokError("minor version number required, comma expected");
-  Lex();
 
   if (ParseAsAbsoluteExpression(Minor))
     return TokError("invalid minor version");
@@ -4089,25 +4088,24 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
 
   std::string Target;
 
-  SMLoc TargetStart = getTok().getLoc();
+  SMLoc TargetStart = getLoc();
   if (getParser().parseEscapedString(Target))
     return true;
-  SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());
+  SMRange TargetRange = SMRange(TargetStart, getLoc());
 
   std::string ExpectedTarget;
   raw_string_ostream ExpectedTargetOS(ExpectedTarget);
   IsaInfo::streamIsaVersion(&getSTI(), ExpectedTargetOS);
 
   if (Target != ExpectedTargetOS.str())
-    return getParser().Error(TargetRange.Start, "target must match options",
-                             TargetRange);
+    return Error(TargetRange.Start, "target must match options", TargetRange);
 
   getTargetStreamer().EmitDirectiveAMDGCNTarget(Target);
   return false;
 }
 
 bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {
-  return getParser().Error(Range.Start, "value out of range", Range);
+  return Error(Range.Start, "value out of range", Range);
 }
 
 bool AMDGPUAsmParser::calculateGPRBlocks(
@@ -4178,15 +4176,12 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
   Optional<bool> EnableWavefrontSize32;
 
   while (true) {
-    while (getLexer().is(AsmToken::EndOfStatement))
-      Lex();
+    while (trySkipToken(AsmToken::EndOfStatement));
 
-    if (getLexer().isNot(AsmToken::Identifier))
-      return TokError("expected .amdhsa_ directive or .end_amdhsa_kernel");
-
-    StringRef ID = getTok().getIdentifier();
+    StringRef ID;
     SMRange IDRange = getTok().getLocRange();
-    Lex();
+    if (!parseId(ID, "expected .amdhsa_ directive or .end_amdhsa_kernel"))
+      return true;
 
     if (ID == ".end_amdhsa_kernel")
       break;
@@ -4195,11 +4190,11 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
       return TokError(".amdhsa_ directives cannot be repeated");
     Seen.insert(ID);
 
-    SMLoc ValStart = getTok().getLoc();
+    SMLoc ValStart = getLoc();
     int64_t IVal;
     if (getParser().parseAbsoluteExpression(IVal))
       return true;
-    SMLoc ValEnd = getTok().getLoc();
+    SMLoc ValEnd = getLoc();
     SMRange ValRange = SMRange(ValStart, ValEnd);
 
     if (IVal < 0)
@@ -4264,8 +4259,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
         UserSGPRCount += 1;
     } else if (ID == ".amdhsa_wavefront_size32") {
       if (IVersion.Major < 10)
-        return getParser().Error(IDRange.Start, "directive requires gfx10+",
-                                 IDRange);
+        return Error(IDRange.Start, "directive requires gfx10+", IDRange);
       EnableWavefrontSize32 = Val;
       PARSE_BITS_ENTRY(KD.kernel_code_properties,
                        KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
@@ -4307,15 +4301,13 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
       ReserveVCC = Val;
     } else if (ID == ".amdhsa_reserve_flat_scratch") {
       if (IVersion.Major < 7)
-        return getParser().Error(IDRange.Start, "directive requires gfx7+",
-                                 IDRange);
+        return Error(IDRange.Start, "directive requires gfx7+", IDRange);
       if (!isUInt<1>(Val))
         return OutOfRangeError(ValRange);
       ReserveFlatScr = Val;
     } else if (ID == ".amdhsa_reserve_xnack_mask") {
       if (IVersion.Major < 8)
-        return getParser().Error(IDRange.Start, "directive requires gfx8+",
-                                 IDRange);
+        return Error(IDRange.Start, "directive requires gfx8+", IDRange);
       if (!isUInt<1>(Val))
         return OutOfRangeError(ValRange);
       ReserveXNACK = Val;
@@ -4340,26 +4332,22 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
                        Val, ValRange);
     } else if (ID == ".amdhsa_fp16_overflow") {
       if (IVersion.Major < 9)
-        return getParser().Error(IDRange.Start, "directive requires gfx9+",
-                                 IDRange);
+        return Error(IDRange.Start, "directive requires gfx9+", IDRange);
       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val,
                        ValRange);
     } else if (ID == ".amdhsa_workgroup_processor_mode") {
       if (IVersion.Major < 10)
-        return getParser().Error(IDRange.Start, "directive requires gfx10+",
-                                 IDRange);
+        return Error(IDRange.Start, "directive requires gfx10+", IDRange);
       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE, Val,
                        ValRange);
     } else if (ID == ".amdhsa_memory_ordered") {
       if (IVersion.Major < 10)
-        return getParser().Error(IDRange.Start, "directive requires gfx10+",
-                                 IDRange);
+        return Error(IDRange.Start, "directive requires gfx10+", IDRange);
       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED, Val,
                        ValRange);
     } else if (ID == ".amdhsa_forward_progress") {
       if (IVersion.Major < 10)
-        return getParser().Error(IDRange.Start, "directive requires gfx10+",
-                                 IDRange);
+        return Error(IDRange.Start, "directive requires gfx10+", IDRange);
       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS, Val,
                        ValRange);
     } else if (ID == ".amdhsa_exception_fp_ieee_invalid_op") {
@@ -4393,8 +4381,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
                        COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
                        Val, ValRange);
     } else {
-      return getParser().Error(IDRange.Start,
-                               "unknown .amdhsa_kernel directive", IDRange);
+      return Error(IDRange.Start, "unknown .amdhsa_kernel directive", IDRange);
     }
 
 #undef PARSE_BITS_ENTRY
@@ -4458,7 +4445,7 @@ bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
 
   // If this directive has no arguments, then use the ISA version for the
   // targeted GPU.
-  if (getLexer().is(AsmToken::EndOfStatement)) {
+  if (isToken(AsmToken::EndOfStatement)) {
     AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
     getTargetStreamer().EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor,
                                                       ISA.Stepping,
@@ -4469,32 +4456,23 @@ bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
   if (ParseDirectiveMajorMinor(Major, Minor))
     return true;
 
-  if (getLexer().isNot(AsmToken::Comma))
+  if (!trySkipToken(AsmToken::Comma))
     return TokError("stepping version number required, comma expected");
-  Lex();
 
   if (ParseAsAbsoluteExpression(Stepping))
     return TokError("invalid stepping version");
 
-  if (getLexer().isNot(AsmToken::Comma))
+  if (!trySkipToken(AsmToken::Comma))
     return TokError("vendor name required, comma expected");
-  Lex();
 
-  if (getLexer().isNot(AsmToken::String))
-    return TokError("invalid vendor name");
-
-  VendorName = getLexer().getTok().getStringContents();
-  Lex();
+  if (!parseString(VendorName, "invalid vendor name"))
+    return true;
 
-  if (getLexer().isNot(AsmToken::Comma))
+  if (!trySkipToken(AsmToken::Comma))
     return TokError("arch name required, comma expected");
-  Lex();
-
-  if (getLexer().isNot(AsmToken::String))
-    return TokError("invalid arch name");
 
-  ArchName = getLexer().getTok().getStringContents();
-  Lex();
+  if (!parseString(ArchName, "invalid arch name"))
+    return true;
 
   getTargetStreamer().EmitDirectiveHSACodeObjectISA(Major, Minor, Stepping,
                                                     VendorName, ArchName);
@@ -4569,14 +4547,11 @@ bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
   while (true) {
     // Lex EndOfStatement.  This is in a while loop, because lexing a comment
     // will set the current token to EndOfStatement.
-    while(getLexer().is(AsmToken::EndOfStatement))
-      Lex();
+    while(trySkipToken(AsmToken::EndOfStatement));
 
-    if (getLexer().isNot(AsmToken::Identifier))
-      return TokError("expected value identifier or .end_amd_kernel_code_t");
-
-    StringRef ID = getLexer().getTok().getIdentifier();
-    Lex();
+    StringRef ID;
+    if (!parseId(ID, "expected value identifier or .end_amd_kernel_code_t"))
+      return true;
 
     if (ID == ".end_amd_kernel_code_t")
       break;
@@ -4591,14 +4566,12 @@ bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
 }
 
 bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
-  if (getLexer().isNot(AsmToken::Identifier))
-    return TokError("expected symbol name");
-
-  StringRef KernelName = Parser.getTok().getString();
+  StringRef KernelName;
+  if (!parseId(KernelName, "expected symbol name"))
+    return true;
 
   getTargetStreamer().EmitAMDGPUSymbolType(KernelName,
                                            ELF::STT_AMDGPU_HSA_KERNEL);
-  Lex();
 
   KernelScope.initialize(getContext());
   return false;
@@ -4606,19 +4579,19 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
 
 bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
   if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {
-    return Error(getParser().getTok().getLoc(),
+    return Error(getLoc(),
                  ".amd_amdgpu_isa directive is not available on non-amdgcn "
                  "architectures");
   }
 
-  auto ISAVersionStringFromASM = getLexer().getTok().getStringContents();
+  auto ISAVersionStringFromASM = getToken().getStringContents();
 
   std::string ISAVersionStringFromSTI;
   raw_string_ostream ISAVersionStreamFromSTI(ISAVersionStringFromSTI);
   IsaInfo::streamIsaVersion(&getSTI(), ISAVersionStreamFromSTI);
 
   if (ISAVersionStringFromASM != ISAVersionStreamFromSTI.str()) {
-    return Error(getParser().getTok().getLoc(),
+    return Error(getLoc(),
                  ".amd_amdgpu_isa directive does not match triple and/or mcpu "
                  "arguments specified through the command line");
   }
@@ -4640,7 +4613,7 @@ bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
                             HSAMD::AssemblerDirectiveEnd);
 
   if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {
-    return Error(getParser().getTok().getLoc(),
+    return Error(getLoc(),
                  (Twine(AssemblerDirectiveBegin) + Twine(" directive is "
                  "not available on non-amdhsa OSes")).str());
   }
@@ -4652,10 +4625,10 @@ bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
 
   if (isHsaAbiVersion3(&getSTI())) {
     if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString))
-      return Error(getParser().getTok().getLoc(), "invalid HSA metadata");
+      return Error(getLoc(), "invalid HSA metadata");
   } else {
     if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString))
-      return Error(getParser().getTok().getLoc(), "invalid HSA metadata");
+      return Error(getLoc(), "invalid HSA metadata");
   }
 
   return false;
@@ -4672,19 +4645,15 @@ bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,
   getLexer().setSkipSpace(false);
 
   bool FoundEnd = false;
-  while (!getLexer().is(AsmToken::Eof)) {
-    while (getLexer().is(AsmToken::Space)) {
-      CollectStream << getLexer().getTok().getString();
+  while (!isToken(AsmToken::Eof)) {
+    while (isToken(AsmToken::Space)) {
+      CollectStream << getTokenStr();
       Lex();
     }
 
-    if (getLexer().is(AsmToken::Identifier)) {
-      StringRef ID = getLexer().getTok().getIdentifier();
-      if (ID == AssemblerDirectiveEnd) {
-        Lex();
-        FoundEnd = true;
-        break;
-      }
+    if (trySkipId(AssemblerDirectiveEnd)) {
+      FoundEnd = true;
+      break;
     }
 
     CollectStream << Parser.parseStringToEndOfStatement()
@@ -4695,7 +4664,7 @@ bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,
 
   getLexer().setSkipSpace(true);
 
-  if (getLexer().is(AsmToken::Eof) && !FoundEnd) {
+  if (isToken(AsmToken::Eof) && !FoundEnd) {
     return TokError(Twine("expected directive ") +
                     Twine(AssemblerDirectiveEnd) + Twine(" not found"));
   }
@@ -4713,14 +4682,14 @@ bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() {
 
   auto PALMetadata = getTargetStreamer().getPALMetadata();
   if (!PALMetadata->setFromString(String))
-    return Error(getParser().getTok().getLoc(), "invalid PAL metadata");
+    return Error(getLoc(), "invalid PAL metadata");
   return false;
 }
 
 /// Parse the assembler directive for old linear-format PAL metadata.
 bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
   if (getSTI().getTargetTriple().getOS() != Triple::AMDPAL) {
-    return Error(getParser().getTok().getLoc(),
+    return Error(getLoc(),
                  (Twine(PALMD::AssemblerDirective) + Twine(" directive is "
                  "not available on non-amdpal OSes")).str());
   }
@@ -4733,19 +4702,17 @@ bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
       return TokError(Twine("invalid value in ") +
                       Twine(PALMD::AssemblerDirective));
     }
-    if (getLexer().isNot(AsmToken::Comma)) {
+    if (!trySkipToken(AsmToken::Comma)) {
       return TokError(Twine("expected an even number of values in ") +
                       Twine(PALMD::AssemblerDirective));
     }
-    Lex();
     if (ParseAsAbsoluteExpression(Value)) {
       return TokError(Twine("invalid value in ") +
                       Twine(PALMD::AssemblerDirective));
     }
     PALMetadata->setRegister(Key, Value);
-    if (getLexer().isNot(AsmToken::Comma))
+    if (!trySkipToken(AsmToken::Comma))
       break;
-    Lex();
   }
   return false;
 }
@@ -4757,7 +4724,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
     return true;
 
   StringRef Name;
-  SMLoc NameLoc = getLexer().getLoc();
+  SMLoc NameLoc = getLoc();
   if (getParser().parseIdentifier(Name))
     return TokError("expected identifier in directive");
 
@@ -4768,7 +4735,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
   unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI());
 
   int64_t Size;
-  SMLoc SizeLoc = getLexer().getLoc();
+  SMLoc SizeLoc = getLoc();
   if (getParser().parseAbsoluteExpression(Size))
     return true;
   if (Size < 0)
@@ -4777,9 +4744,8 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
     return Error(SizeLoc, "size is too large");
 
   int64_t Alignment = 4;
-  if (getLexer().is(AsmToken::Comma)) {
-    Lex();
-    SMLoc AlignLoc = getLexer().getLoc();
+  if (trySkipToken(AsmToken::Comma)) {
+    SMLoc AlignLoc = getLoc();
     if (getParser().parseAbsoluteExpression(Alignment))
       return true;
     if (Alignment < 0 || !isPowerOf2_64(Alignment))
@@ -4930,35 +4896,33 @@ AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic,
   // are appending default values to the Operands list.  This is only done
   // by custom parser, so we shouldn't continue on to the generic parsing.
   if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
-      getLexer().is(AsmToken::EndOfStatement))
+      isToken(AsmToken::EndOfStatement))
     return ResTy;
 
-  if (Mode == OperandMode_NSA && getLexer().is(AsmToken::LBrac)) {
+  SMLoc RBraceLoc;
+  SMLoc LBraceLoc = getLoc();
+  if (Mode == OperandMode_NSA && trySkipToken(AsmToken::LBrac)) {
     unsigned Prefix = Operands.size();
-    SMLoc LBraceLoc = getTok().getLoc();
-    Parser.Lex(); // eat the '['
 
     for (;;) {
       ResTy = parseReg(Operands);
       if (ResTy != MatchOperand_Success)
         return ResTy;
 
-      if (getLexer().is(AsmToken::RBrac))
+      RBraceLoc = getLoc();
+      if (trySkipToken(AsmToken::RBrac))
         break;
 
-      if (getLexer().isNot(AsmToken::Comma))
+      if (!trySkipToken(AsmToken::Comma))
         return MatchOperand_ParseFail;
-      Parser.Lex();
     }
 
     if (Operands.size() - Prefix > 1) {
       Operands.insert(Operands.begin() + Prefix,
                       AMDGPUOperand::CreateToken(this, "[", LBraceLoc));
-      Operands.push_back(AMDGPUOperand::CreateToken(this, "]",
-                                                    getTok().getLoc()));
+      Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));
     }
 
-    Parser.Lex(); // eat the ']'
     return MatchOperand_Success;
   }
 
@@ -4996,15 +4960,14 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
 
   bool IsMIMG = Name.startswith("image_");
 
-  while (!getLexer().is(AsmToken::EndOfStatement)) {
+  while (!trySkipToken(AsmToken::EndOfStatement)) {
     OperandMode Mode = OperandMode_Default;
     if (IsMIMG && isGFX10Plus() && Operands.size() == 2)
       Mode = OperandMode_NSA;
     OperandMatchResultTy Res = parseOperand(Operands, Name, Mode);
 
     // Eat the comma or space if there is one.
-    if (getLexer().is(AsmToken::Comma))
-      Parser.Lex();
+    trySkipToken(AsmToken::Comma);
 
     if (Res != MatchOperand_Success) {
       checkUnsupportedInstruction(Name, NameLoc);
@@ -5013,16 +4976,14 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
         StringRef Msg =
           (Res == MatchOperand_ParseFail) ? "failed parsing operand." :
                                             "not a valid operand.";
-        Error(getLexer().getLoc(), Msg);
+        Error(getLoc(), Msg);
       }
-      while (!getLexer().is(AsmToken::EndOfStatement)) {
+      while (!trySkipToken(AsmToken::EndOfStatement)) {
         Parser.Lex();
       }
-      Parser.Lex();
       return true;
     }
   }
-  Parser.Lex();
 
   return false;
 }
@@ -5109,14 +5070,14 @@ OperandMatchResultTy
 AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
                                AMDGPUOperand::ImmTy ImmTy) {
   int64_t Bit = 0;
-  SMLoc S = Parser.getTok().getLoc();
+  SMLoc S = getLoc();
 
   // We are at the end of the statement, and this is a default argument, so
   // use a default value.
-  if (getLexer().isNot(AsmToken::EndOfStatement)) {
-    switch(getLexer().getKind()) {
+  if (!isToken(AsmToken::EndOfStatement)) {
+    switch(getTokenKind()) {
       case AsmToken::Identifier: {
-        StringRef Tok = Parser.getTok().getString();
+        StringRef Tok = getTokenStr();
         if (Tok == Name) {
           if (Tok == "r128" && !hasMIMG_R128())
             Error(S, "r128 modifier is not supported on this GPU");
@@ -5163,26 +5124,10 @@ static void addOptionalImmOperand(
 
 OperandMatchResultTy
 AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) {
-  if (getLexer().isNot(AsmToken::Identifier)) {
-    return MatchOperand_NoMatch;
-  }
-  StringRef Tok = Parser.getTok().getString();
-  if (Tok != Prefix) {
+  if (!trySkipId(Prefix, AsmToken::Colon))
     return MatchOperand_NoMatch;
-  }
-
-  Parser.Lex();
-  if (getLexer().isNot(AsmToken::Colon)) {
-    return MatchOperand_ParseFail;
-  }
 
-  Parser.Lex();
-  if (getLexer().isNot(AsmToken::Identifier)) {
-    return MatchOperand_ParseFail;
-  }
-
-  Value = Parser.getTok().getString();
-  return MatchOperand_Success;
+  return parseId(Value) ? MatchOperand_Success : MatchOperand_ParseFail;
 }
 
 //===----------------------------------------------------------------------===//
@@ -5886,34 +5831,40 @@ bool AMDGPUOperand::isSendMsg() const {
 //===----------------------------------------------------------------------===//
 
 OperandMatchResultTy AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {
-  if (getLexer().getKind() != AsmToken::Identifier)
+  StringRef Str;
+  SMLoc S = getLoc();
+
+  if (!parseId(Str))
     return MatchOperand_NoMatch;
 
-  StringRef Str = Parser.getTok().getString();
   int Slot = StringSwitch<int>(Str)
     .Case("p10", 0)
     .Case("p20", 1)
     .Case("p0", 2)
     .Default(-1);
 
-  SMLoc S = Parser.getTok().getLoc();
-  if (Slot == -1)
+  if (Slot == -1) {
+    Error(S, "invalid interpolation slot");
     return MatchOperand_ParseFail;
+  }
 
-  Parser.Lex();
   Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,
                                               AMDGPUOperand::ImmTyInterpSlot));
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
-  if (getLexer().getKind() != AsmToken::Identifier)
-    return MatchOperand_NoMatch;
+  StringRef Str;
+  SMLoc S = getLoc();
 
-  StringRef Str = Parser.getTok().getString();
-  if (!Str.startswith("attr"))
+  if (!parseId(Str))
     return MatchOperand_NoMatch;
 
+  if (!Str.startswith("attr")) {
+    Error(S, "invalid interpolation attribute");
+    return MatchOperand_ParseFail;
+  }
+
   StringRef Chan = Str.take_back(2);
   int AttrChan = StringSwitch<int>(Chan)
     .Case(".x", 0)
@@ -5921,19 +5872,21 @@ OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
     .Case(".z", 2)
     .Case(".w", 3)
     .Default(-1);
-  if (AttrChan == -1)
+  if (AttrChan == -1) {
+    Error(S, "invalid or missing interpolation attribute channel");
     return MatchOperand_ParseFail;
+  }
 
   Str = Str.drop_back(2).drop_front(4);
 
   uint8_t Attr;
-  if (Str.getAsInteger(10, Attr))
+  if (Str.getAsInteger(10, Attr)) {
+    Error(S, "invalid or missing interpolation attribute number");
     return MatchOperand_ParseFail;
+  }
 
-  SMLoc S = Parser.getTok().getLoc();
-  Parser.Lex();
   if (Attr > 63) {
-    Error(S, "out of bounds attr");
+    Error(S, "out of bounds interpolation attribute number");
     return MatchOperand_ParseFail;
   }
 
@@ -6006,19 +5959,19 @@ OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
 }
 
 OperandMatchResultTy AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
-  if (!isToken(AsmToken::Identifier))
-    return MatchOperand_NoMatch;
-
+  StringRef Str;
   SMLoc S = getLoc();
 
+  if (!parseId(Str))
+    return MatchOperand_NoMatch;
+
   uint8_t Val;
-  auto Res = parseExpTgtImpl(getTokenStr(), Val);
+  auto Res = parseExpTgtImpl(Str, Val);
   if (Res != MatchOperand_Success) {
     Error(S, "invalid exp target");
     return Res;
   }
 
-  Parser.Lex();
   Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S,
                                               AMDGPUOperand::ImmTyExpTgt));
   return MatchOperand_Success;
@@ -6137,7 +6090,8 @@ AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {
     lex();
     return true;
   } else {
-    Error(getLoc(), ErrMsg);
+    if (!ErrMsg.empty())
+      Error(getLoc(), ErrMsg);
     return false;
   }
 }
@@ -6249,7 +6203,7 @@ AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,
   if (!skipToken(AsmToken::Comma, "expected a comma")) {
     return false;
   }
-  Loc = Parser.getTok().getLoc();
+  Loc = getLoc();
   if (!parseExpr(Op)) {
     return false;
   }
@@ -6372,7 +6326,7 @@ AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
   }
 
   StringRef Ctl;
-  SMLoc StrLoc = Parser.getTok().getLoc();
+  SMLoc StrLoc = getLoc();
   if (!parseString(Ctl)) {
     return false;
   }
@@ -6413,7 +6367,7 @@ AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
 bool
 AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {
 
-  SMLoc OffsetLoc = Parser.getTok().getLoc();
+  SMLoc OffsetLoc = getLoc();
 
   if (!parseExpr(Imm, "a swizzle macro")) {
     return false;
@@ -6431,7 +6385,7 @@ AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
 
   if (skipToken(AsmToken::LParen, "expected a left parentheses")) {
 
-    SMLoc ModeLoc = Parser.getTok().getLoc();
+    SMLoc ModeLoc = getLoc();
     bool Ok = false;
 
     if (trySkipId(IdSymbolic[ID_QUAD_PERM])) {
@@ -6456,7 +6410,7 @@ AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
 
 OperandMatchResultTy
 AMDGPUAsmParser::parseSwizzleOp(OperandVector &Operands) {
-  SMLoc S = Parser.getTok().getLoc();
+  SMLoc S = getLoc();
   int64_t Imm = 0;
 
   if (trySkipId("offset")) {
@@ -6501,7 +6455,7 @@ int64_t AMDGPUAsmParser::parseGPRIdxMacro() {
 
   while (true) {
     unsigned Mode = 0;
-    SMLoc S = Parser.getTok().getLoc();
+    SMLoc S = getLoc();
 
     for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
       if (trySkipId(IdSymbolic[ModeId])) {
@@ -6539,19 +6493,12 @@ AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {
   using namespace llvm::AMDGPU::VGPRIndexMode;
 
   int64_t Imm = 0;
-  SMLoc S = Parser.getTok().getLoc();
-
-  if (getLexer().getKind() == AsmToken::Identifier &&
-      Parser.getTok().getString() == "gpr_idx" &&
-      getLexer().peekTok().is(AsmToken::LParen)) {
-
-    Parser.Lex();
-    Parser.Lex();
+  SMLoc S = getLoc();
 
+  if (trySkipId("gpr_idx", AsmToken::LParen)) {
     Imm = parseGPRIdxMacro();
     if (Imm == UNDEF)
       return MatchOperand_ParseFail;
-
   } else {
     if (getParser().parseAbsoluteExpression(Imm))
       return MatchOperand_ParseFail;
@@ -6993,7 +6940,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseOptionalOpr(OperandVector &Operands)
 }
 
 OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) {
-  StringRef Name = Parser.getTok().getString();
+  StringRef Name = getTokenStr();
   if (Name == "mul") {
     return parseIntWithPrefix("mul", Operands,
                               AMDGPUOperand::ImmTyOModSI, ConvertOmodMul);
@@ -7296,32 +7243,24 @@ OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) {
   if (!isGFX10Plus())
     return MatchOperand_NoMatch;
 
-  SMLoc S = Parser.getTok().getLoc();
+  SMLoc S = getLoc();
 
-  if (getLexer().isNot(AsmToken::Identifier))
-    return MatchOperand_NoMatch;
-  if (getLexer().getTok().getString() != "dim")
+  if (!trySkipId("dim", AsmToken::Colon))
     return MatchOperand_NoMatch;
 
-  Parser.Lex();
-  if (getLexer().isNot(AsmToken::Colon))
-    return MatchOperand_ParseFail;
-
-  Parser.Lex();
-
   // We want to allow "dim:1D" etc., but the initial 1 is tokenized as an
   // integer.
   std::string Token;
-  if (getLexer().is(AsmToken::Integer)) {
-    SMLoc Loc = getLexer().getTok().getEndLoc();
-    Token = std::string(getLexer().getTok().getString());
+  if (isToken(AsmToken::Integer)) {
+    SMLoc Loc = getToken().getEndLoc();
+    Token = std::string(getTokenStr());
     Parser.Lex();
-    if (getLexer().getTok().getLoc() != Loc)
+    if (getLoc() != Loc)
       return MatchOperand_ParseFail;
   }
-  if (getLexer().isNot(AsmToken::Identifier))
+  if (!isToken(AsmToken::Identifier))
     return MatchOperand_ParseFail;
-  Token += getLexer().getTok().getString();
+  Token += getTokenStr();
 
   StringRef DimId = Token;
   if (DimId.startswith("SQ_RSRC_IMG_"))
@@ -7339,52 +7278,35 @@ OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) {
 }
 
 OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
-  SMLoc S = Parser.getTok().getLoc();
-  StringRef Prefix;
-
-  if (getLexer().getKind() == AsmToken::Identifier) {
-    Prefix = Parser.getTok().getString();
-  } else {
-    return MatchOperand_NoMatch;
-  }
+  SMLoc S = getLoc();
 
-  if (Prefix != "dpp8")
-    return parseDPPCtrl(Operands);
-  if (!isGFX10Plus())
+  if (!isGFX10Plus() || !trySkipId("dpp8", AsmToken::Colon))
     return MatchOperand_NoMatch;
 
   // dpp8:[%d,%d,%d,%d,%d,%d,%d,%d]
 
   int64_t Sels[8];
 
-  Parser.Lex();
-  if (getLexer().isNot(AsmToken::Colon))
+  if (!trySkipToken(AsmToken::LBrac))
     return MatchOperand_ParseFail;
 
-  Parser.Lex();
-  if (getLexer().isNot(AsmToken::LBrac))
-    return MatchOperand_ParseFail;
-
-  Parser.Lex();
   if (getParser().parseAbsoluteExpression(Sels[0]))
     return MatchOperand_ParseFail;
   if (0 > Sels[0] || 7 < Sels[0])
     return MatchOperand_ParseFail;
 
   for (size_t i = 1; i < 8; ++i) {
-    if (getLexer().isNot(AsmToken::Comma))
+    if (!trySkipToken(AsmToken::Comma))
       return MatchOperand_ParseFail;
 
-    Parser.Lex();
     if (getParser().parseAbsoluteExpression(Sels[i]))
       return MatchOperand_ParseFail;
     if (0 > Sels[i] || 7 < Sels[i])
       return MatchOperand_ParseFail;
   }
 
-  if (getLexer().isNot(AsmToken::RBrac))
+  if (!trySkipToken(AsmToken::RBrac))
     return MatchOperand_ParseFail;
-  Parser.Lex();
 
   unsigned DPP8 = 0;
   for (size_t i = 0; i < 8; ++i)
@@ -7398,12 +7320,12 @@ OperandMatchResultTy
 AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
   using namespace AMDGPU::DPP;
 
-  SMLoc S = Parser.getTok().getLoc();
+  SMLoc S = getLoc();
   StringRef Prefix;
   int64_t Int;
 
-  if (getLexer().getKind() == AsmToken::Identifier) {
-    Prefix = Parser.getTok().getString();
+  if (isToken(AsmToken::Identifier)) {
+    Prefix = getTokenStr();
   } else {
     return MatchOperand_NoMatch;
   }
@@ -7440,23 +7362,21 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
       return MatchOperand_NoMatch;
 
     Parser.Lex();
-    if (getLexer().isNot(AsmToken::Colon))
+    if (!isToken(AsmToken::Colon))
       return MatchOperand_ParseFail;
 
     if (Prefix == "quad_perm") {
       // quad_perm:[%d,%d,%d,%d]
       Parser.Lex();
-      if (getLexer().isNot(AsmToken::LBrac))
+      if (!trySkipToken(AsmToken::LBrac))
         return MatchOperand_ParseFail;
-      Parser.Lex();
 
       if (getParser().parseAbsoluteExpression(Int) || !(0 <= Int && Int <=3))
         return MatchOperand_ParseFail;
 
       for (int i = 0; i < 3; ++i) {
-        if (getLexer().isNot(AsmToken::Comma))
+        if (!trySkipToken(AsmToken::Comma))
           return MatchOperand_ParseFail;
-        Parser.Lex();
 
         int64_t Temp;
         if (getParser().parseAbsoluteExpression(Temp) || !(0 <= Temp && Temp <=3))
@@ -7465,9 +7385,8 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
         Int += (Temp << shift);
       }
 
-      if (getLexer().isNot(AsmToken::RBrac))
+      if (!trySkipToken(AsmToken::RBrac))
         return MatchOperand_ParseFail;
-      Parser.Lex();
     } else {
       // sel:%d
       Parser.Lex();
@@ -7604,7 +7523,7 @@ AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix,
                               AMDGPUOperand::ImmTy Type) {
   using namespace llvm::AMDGPU::SDWA;
 
-  SMLoc S = Parser.getTok().getLoc();
+  SMLoc S = getLoc();
   StringRef Value;
   OperandMatchResultTy res;
 
@@ -7623,7 +7542,6 @@ AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix,
         .Case("WORD_1", SdwaSel::WORD_1)
         .Case("DWORD", SdwaSel::DWORD)
         .Default(0xffffffff);
-  Parser.Lex(); // eat last token
 
   if (Int == 0xffffffff) {
     return MatchOperand_ParseFail;
@@ -7637,7 +7555,7 @@ OperandMatchResultTy
 AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
   using namespace llvm::AMDGPU::SDWA;
 
-  SMLoc S = Parser.getTok().getLoc();
+  SMLoc S = getLoc();
   StringRef Value;
   OperandMatchResultTy res;
 
@@ -7652,7 +7570,6 @@ AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
         .Case("UNUSED_SEXT", DstUnused::UNUSED_SEXT)
         .Case("UNUSED_PRESERVE", DstUnused::UNUSED_PRESERVE)
         .Default(0xffffffff);
-  Parser.Lex(); // eat last token
 
   if (Int == 0xffffffff) {
     return MatchOperand_ParseFail;
@@ -7868,7 +7785,7 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
 //===----------------------------------------------------------------------===//
 
 OperandMatchResultTy AMDGPUAsmParser::parseEndpgmOp(OperandVector &Operands) {
-  SMLoc S = Parser.getTok().getLoc();
+  SMLoc S = getLoc();
   int64_t Imm = 0;
 
   if (!parseExpr(Imm)) {
diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt
index 48846c82e7f78..9b02fb44b0ebf 100644
--- a/llvm/lib/Target/AMDGPU/CMakeLists.txt
+++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt
@@ -152,6 +152,7 @@ add_llvm_target(AMDGPUCodeGen
   Core
   IPO
   MC
+  Passes
   AMDGPUDesc
   AMDGPUInfo
   AMDGPUUtils
diff --git a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
index 3c41bf1fef5e9..016c3b2019fd9 100644
--- a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
@@ -313,8 +313,15 @@ void SIAnnotateControlFlow::closeControlFlow(BasicBlock *BB) {
 
   Value *Exec = popSaved();
   Instruction *FirstInsertionPt = &*BB->getFirstInsertionPt();
-  if (!isa<UndefValue>(Exec) && !isa<UnreachableInst>(FirstInsertionPt))
+  if (!isa<UndefValue>(Exec) && !isa<UnreachableInst>(FirstInsertionPt)) {
+    Instruction *ExecDef = cast<Instruction>(Exec);
+    BasicBlock *DefBB = ExecDef->getParent();
+    if (!DT->dominates(DefBB, BB)) {
+      // Split edge to make Def dominate Use
+      FirstInsertionPt = &*SplitEdge(DefBB, BB, DT, LI)->getFirstInsertionPt();
+    }
     CallInst::Create(EndCf, Exec, "", FirstInsertionPt);
+  }
 }
 
 /// Annotate the control flow with intrinsics so the backend can
@@ -327,7 +334,6 @@ bool SIAnnotateControlFlow::runOnFunction(Function &F) {
   const TargetMachine &TM = TPC.getTM<TargetMachine>();
 
   initialize(*F.getParent(), TM.getSubtarget<GCNSubtarget>(F));
-
   for (df_iterator<BasicBlock *> I = df_begin(&F.getEntryBlock()),
        E = df_end(&F.getEntryBlock()); I != E; ++I) {
     BasicBlock *BB = *I;
@@ -344,7 +350,8 @@ bool SIAnnotateControlFlow::runOnFunction(Function &F) {
       if (isTopOfStack(BB))
         closeControlFlow(BB);
 
-      handleLoop(Term);
+      if (DT->dominates(Term->getSuccessor(1), BB))
+        handleLoop(Term);
       continue;
     }
 
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index 75a54c0a412e9..d6c151d3d2cc2 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -213,8 +213,12 @@ static bool tryChangeVGPRtoSGPRinCopy(MachineInstr &MI,
     if (UseMI == &MI)
       continue;
     if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
-        UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END ||
-        !TII->isOperandLegal(*UseMI, UseMI->getOperandNo(&MO), &Src))
+        UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END)
+      return false;
+
+    unsigned OpIdx = UseMI->getOperandNo(&MO);
+    if (OpIdx >= UseMI->getDesc().getNumOperands() ||
+        !TII->isOperandLegal(*UseMI, OpIdx, &Src))
       return false;
   }
   // Change VGPR to SGPR destination.
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index bfba432848d4c..d86527df5c3cf 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -172,9 +172,23 @@ static bool frameIndexMayFold(const SIInstrInfo *TII,
                               const MachineInstr &UseMI,
                               int OpNo,
                               const MachineOperand &OpToFold) {
-  return OpToFold.isFI() &&
-    TII->isMUBUF(UseMI) &&
-    OpNo == AMDGPU::getNamedOperandIdx(UseMI.getOpcode(), AMDGPU::OpName::vaddr);
+  if (!OpToFold.isFI())
+    return false;
+
+  if (TII->isMUBUF(UseMI))
+    return OpNo == AMDGPU::getNamedOperandIdx(UseMI.getOpcode(),
+                                              AMDGPU::OpName::vaddr);
+  if (!TII->isFLATScratch(UseMI))
+    return false;
+
+  int SIdx = AMDGPU::getNamedOperandIdx(UseMI.getOpcode(),
+                                        AMDGPU::OpName::saddr);
+  if (OpNo == SIdx)
+    return true;
+
+  int VIdx = AMDGPU::getNamedOperandIdx(UseMI.getOpcode(),
+                                        AMDGPU::OpName::vaddr);
+  return OpNo == VIdx && SIdx == -1;
 }
 
 FunctionPass *llvm::createSIFoldOperandsPass() {
@@ -546,8 +560,9 @@ static bool tryToFoldACImm(const SIInstrInfo *TII,
   if (!UseReg.isVirtual())
     return false;
 
-  if (llvm::find_if(FoldList, [UseMI](const FoldCandidate &FC) {
-        return FC.UseMI == UseMI; }) != FoldList.end())
+  if (llvm::any_of(FoldList, [UseMI](const FoldCandidate &FC) {
+        return FC.UseMI == UseMI;
+      }))
     return false;
 
   MachineRegisterInfo &MRI = UseMI->getParent()->getParent()->getRegInfo();
@@ -631,25 +646,36 @@ void SIFoldOperands::foldOperand(
     // Sanity check that this is a stack access.
     // FIXME: Should probably use stack pseudos before frame lowering.
 
-    if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() !=
-        MFI->getScratchRSrcReg())
-      return;
+    if (TII->isMUBUF(*UseMI)) {
+      if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() !=
+          MFI->getScratchRSrcReg())
+        return;
 
-    // Ensure this is either relative to the current frame or the current wave.
-    MachineOperand &SOff =
-        *TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset);
-    if ((!SOff.isReg() || SOff.getReg() != MFI->getStackPtrOffsetReg()) &&
-        (!SOff.isImm() || SOff.getImm() != 0))
-      return;
+      // Ensure this is either relative to the current frame or the current
+      // wave.
+      MachineOperand &SOff =
+          *TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset);
+      if ((!SOff.isReg() || SOff.getReg() != MFI->getStackPtrOffsetReg()) &&
+          (!SOff.isImm() || SOff.getImm() != 0))
+        return;
+
+      // If this is relative to the current wave, update it to be relative to
+      // the current frame.
+      if (SOff.isImm())
+        SOff.ChangeToRegister(MFI->getStackPtrOffsetReg(), false);
+    }
 
     // A frame index will resolve to a positive constant, so it should always be
     // safe to fold the addressing mode, even pre-GFX9.
     UseMI->getOperand(UseOpIdx).ChangeToFrameIndex(OpToFold.getIndex());
 
-    // If this is relative to the current wave, update it to be relative to the
-    // current frame.
-    if (SOff.isImm())
-      SOff.ChangeToRegister(MFI->getStackPtrOffsetReg(), false);
+    if (TII->isFLATScratch(*UseMI) &&
+        AMDGPU::getNamedOperandIdx(UseMI->getOpcode(),
+                                   AMDGPU::OpName::vaddr) != -1) {
+      unsigned NewOpc = AMDGPU::getFlatScratchInstSSfromSV(UseMI->getOpcode());
+      UseMI->setDesc(TII->get(NewOpc));
+    }
+
     return;
   }
 
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 5fb1924bdd9fc..c7abc585d0d1c 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1470,12 +1470,21 @@ bool SITargetLowering::allowsMisalignedMemoryAccessesImpl(
     }
   }
 
+  if (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS) {
+    bool AlignedBy4 = Alignment >= Align(4);
+    if (IsFast)
+      *IsFast = AlignedBy4;
+
+    return AlignedBy4 ||
+           Subtarget->enableFlatScratch() ||
+           Subtarget->hasUnalignedScratchAccess();
+  }
+
   // FIXME: We have to be conservative here and assume that flat operations
   // will access scratch.  If we had access to the IR function, then we
   // could determine if any private memory was used in the function.
-  if (!Subtarget->hasUnalignedScratchAccess() &&
-      (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
-       AddrSpace == AMDGPUAS::FLAT_ADDRESS)) {
+  if (AddrSpace == AMDGPUAS::FLAT_ADDRESS &&
+      !Subtarget->hasUnalignedScratchAccess()) {
     bool AlignedBy4 = Alignment >= Align(4);
     if (IsFast)
       *IsFast = AlignedBy4;
@@ -10853,7 +10862,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
 /// Helper function for adjustWritemask
 static unsigned SubIdx2Lane(unsigned Idx) {
   switch (Idx) {
-  default: return 0;
+  default: return ~0u;
   case AMDGPU::sub0: return 0;
   case AMDGPU::sub1: return 1;
   case AMDGPU::sub2: return 2;
@@ -10913,6 +10922,8 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
     // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
     // set, etc.
     Lane = SubIdx2Lane(I->getConstantOperandVal(1));
+    if (Lane == ~0u)
+      return Node;
 
     // Check if the use is for the TFE/LWE generated result at VGPRn+1.
     if (UsesTFC && Lane == TFCLane) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 4625cefa1e3e4..75aedee1ec6bc 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1184,6 +1184,9 @@ namespace AMDGPU {
   LLVM_READONLY
   int getFlatScratchInstSTfromSS(uint16_t Opcode);
 
+  LLVM_READONLY
+  int getFlatScratchInstSSfromSV(uint16_t Opcode);
+
   const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
   const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
   const uint64_t RSRC_INDEX_STRIDE_SHIFT = (32 + 21);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 746d08b8ce0e9..e48138e56d71c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2524,6 +2524,13 @@ def getFlatScratchInstSTfromSS : InstrMapping {
   let ValueCols = [["ST"]];
 }
 
+def getFlatScratchInstSSfromSV : InstrMapping {
+  let FilterClass = "FlatScratchInst";
+  let RowFields = ["SVOp"];
+  let ColFields = ["Mode"];
+  let KeyCol = ["SV"];
+  let ValueCols = [["SS"]];
+}
 
 include "SIInstructions.td"
 
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 130edd83bef6e..939a9676ad3bd 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -98,7 +98,7 @@ static void insertCSRSaves(MachineBasicBlock &SaveBlock,
   if (!TFI->spillCalleeSavedRegisters(SaveBlock, I, CSI, TRI)) {
     for (const CalleeSavedInfo &CS : CSI) {
       // Insert the spill to the stack frame.
-      unsigned Reg = CS.getReg();
+      MCRegister Reg = CS.getReg();
 
       MachineInstrSpan MIS(I, &SaveBlock);
       const TargetRegisterClass *RC =
@@ -185,6 +185,16 @@ void SILowerSGPRSpills::calculateSaveRestoreBlocks(MachineFunction &MF) {
   }
 }
 
+// TODO: To support shrink wrapping, this would need to copy
+// PrologEpilogInserter's updateLiveness.
+static void updateLiveness(MachineFunction &MF, ArrayRef<CalleeSavedInfo> CSI) {
+  MachineBasicBlock &EntryBB = MF.front();
+
+  for (const CalleeSavedInfo &CSIReg : CSI)
+    EntryBB.addLiveIn(CSIReg.getReg());
+  EntryBB.sortUniqueLiveIns();
+}
+
 bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) {
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const Function &F = MF.getFunction();
@@ -207,7 +217,8 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) {
     const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
 
     for (unsigned I = 0; CSRegs[I]; ++I) {
-      unsigned Reg = CSRegs[I];
+      MCRegister Reg = CSRegs[I];
+
       if (SavedRegs.test(Reg)) {
         const TargetRegisterClass *RC =
           TRI->getMinimalPhysRegClass(Reg, MVT::i32);
@@ -222,6 +233,10 @@ bool SILowerSGPRSpills::spillCalleeSavedRegs(MachineFunction &MF) {
       for (MachineBasicBlock *SaveBlock : SaveBlocks)
         insertCSRSaves(*SaveBlock, CSI, LIS);
 
+      // Add live ins to save blocks.
+      assert(SaveBlocks.size() == 1 && "shrink wrapping not fully implemented");
+      updateLiveness(MF, CSI);
+
       for (MachineBasicBlock *RestoreBlock : RestoreBlocks)
         insertCSRRestores(*RestoreBlock, CSI, LIS);
       return true;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index ab203c44e022f..c91a59003319a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1498,6 +1498,10 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
       int64_t Offset = FrameInfo.getObjectOffset(Index);
       if (ST.enableFlatScratch()) {
         if (TII->isFLATScratch(*MI)) {
+          assert((int16_t)FIOperandNum ==
+                 AMDGPU::getNamedOperandIdx(MI->getOpcode(),
+                                            AMDGPU::OpName::saddr));
+
           // The offset is always swizzled, just replace it
           if (FrameReg)
             FIOp.ChangeToRegister(FrameReg, false);
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 8111346c74f6c..5d626e7d8e5a2 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -660,7 +660,8 @@ def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 
 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
                                    "Cortex-M3 ARM processors", []>;
-
+def ProcM7      : SubtargetFeature<"m7", "ARMProcFamily", "CortexM7",
+                                   "Cortex-M7 ARM processors", []>;
 
 //===----------------------------------------------------------------------===//
 // ARM Helper classes.
@@ -1191,6 +1192,7 @@ def : ProcessorModel<"cortex-m4", CortexM4Model,        [ARMv7em,
                                                          FeatureHasNoBranchPredictor]>;
 
 def : ProcessorModel<"cortex-m7", CortexM7Model,        [ARMv7em,
+                                                         ProcM7,
                                                          FeatureFPARMv8_D16,
                                                          FeatureUseMISched]>;
 
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index dd22e5dfe6e1b..04e21867d5711 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1897,7 +1897,7 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) {
     // LSJLJEH:
     Register SrcReg = MI->getOperand(0).getReg();
     Register ValReg = MI->getOperand(1).getReg();
-    MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
+    MCSymbol *Label = OutContext.createTempSymbol("SJLJEH");
     OutStreamer->AddComment("eh_setjmp begin");
     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
       .addReg(ValReg)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index def6312769502..563f2d38edf02 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -134,6 +134,31 @@ ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
   return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
 }
 
+// Called during:
+// - pre-RA scheduling
+// - post-RA scheduling when FeatureUseMISched is set
+ScheduleHazardRecognizer *ARMBaseInstrInfo::CreateTargetMIHazardRecognizer(
+    const InstrItineraryData *II, const ScheduleDAGMI *DAG) const {
+  MultiHazardRecognizer *MHR = new MultiHazardRecognizer();
+
+  // We would like to restrict this hazard recognizer to only
+  // post-RA scheduling; we can tell that we're post-RA because we don't
+  // track VRegLiveness.
+  // Cortex-M7: TRM indicates that there is a single ITCM bank and two DTCM
+  //            banks banked on bit 2.  Assume that TCMs are in use.
+  if (Subtarget.isCortexM7() && !DAG->hasVRegLiveness())
+    MHR->AddHazardRecognizer(
+        std::make_unique<ARMBankConflictHazardRecognizer>(DAG, 0x4, true));
+
+  // Not inserting ARMHazardRecognizerFPMLx because that would change
+  // legacy behavior
+
+  auto BHR = TargetInstrInfo::CreateTargetMIHazardRecognizer(II, DAG);
+  MHR->AddHazardRecognizer(std::unique_ptr<ScheduleHazardRecognizer>(BHR));
+  return MHR;
+}
+
+// Called during post-RA scheduling when FeatureUseMISched is not set
 ScheduleHazardRecognizer *ARMBaseInstrInfo::
 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
                                    const ScheduleDAG *DAG) const {
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 9b6572848ebef..deb008025b1d5 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -131,6 +131,10 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
   CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
                                const ScheduleDAG *DAG) const override;
 
+  ScheduleHazardRecognizer *
+  CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
+                                 const ScheduleDAGMI *DAG) const override;
+
   ScheduleHazardRecognizer *
   CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
                                      const ScheduleDAG *DAG) const override;
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
index 3cbc8da863c3d..f083fa6662e93 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
@@ -10,11 +10,19 @@
 #include "ARMBaseInstrInfo.h"
 #include "ARMBaseRegisterInfo.h"
 #include "ARMSubtarget.h"
+#include "llvm/Analysis/ValueTracking.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/Support/CommandLine.h"
+
 using namespace llvm;
 
+static cl::opt<int> DataBankMask("arm-data-bank-mask", cl::init(-1),
+                                 cl::Hidden);
+static cl::opt<bool> AssumeITCMConflict("arm-assume-itcm-bankconflict",
+                                        cl::init(false), cl::Hidden);
+
 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI,
                          const TargetRegisterInfo &TRI) {
   // FIXME: Detect integer instructions properly.
@@ -93,3 +101,168 @@ void ARMHazardRecognizerFPMLx::AdvanceCycle() {
 void ARMHazardRecognizerFPMLx::RecedeCycle() {
   llvm_unreachable("reverse ARM hazard checking unsupported");
 }
+
+///////// Bank conflicts handled as hazards //////////////
+
+static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp,
+                          int64_t &Offset) {
+
+  uint64_t TSFlags = MI.getDesc().TSFlags;
+  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
+  unsigned IndexMode =
+      (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
+
+  // Address mode tells us what we want to know about operands for T2
+  // instructions (but not size).  It tells us size (but not about operands)
+  // for T1 instructions.
+  switch (AddrMode) {
+  default:
+    return false;
+  case ARMII::AddrModeT2_i8:
+    // t2LDRBT, t2LDRB_POST, t2LDRB_PRE, t2LDRBi8,
+    // t2LDRHT, t2LDRH_POST, t2LDRH_PRE, t2LDRHi8,
+    // t2LDRSBT, t2LDRSB_POST, t2LDRSB_PRE, t2LDRSBi8,
+    // t2LDRSHT, t2LDRSH_POST, t2LDRSH_PRE, t2LDRSHi8,
+    // t2LDRT, t2LDR_POST, t2LDR_PRE, t2LDRi8
+    BaseOp = &MI.getOperand(1);
+    Offset = (IndexMode == ARMII::IndexModePost)
+                 ? 0
+                 : (IndexMode == ARMII::IndexModePre ||
+                    IndexMode == ARMII::IndexModeUpd)
+                       ? MI.getOperand(3).getImm()
+                       : MI.getOperand(2).getImm();
+    return true;
+  case ARMII::AddrModeT2_i12:
+    // t2LDRBi12, t2LDRHi12
+    // t2LDRSBi12, t2LDRSHi12
+    // t2LDRi12
+    BaseOp = &MI.getOperand(1);
+    Offset = MI.getOperand(2).getImm();
+    return true;
+  case ARMII::AddrModeT2_i8s4:
+    // t2LDRD_POST, t2LDRD_PRE, t2LDRDi8
+    BaseOp = &MI.getOperand(2);
+    Offset = (IndexMode == ARMII::IndexModePost)
+                 ? 0
+                 : (IndexMode == ARMII::IndexModePre ||
+                    IndexMode == ARMII::IndexModeUpd)
+                       ? MI.getOperand(4).getImm()
+                       : MI.getOperand(3).getImm();
+    return true;
+  case ARMII::AddrModeT1_1:
+    // tLDRBi, tLDRBr (watch out!), TLDRSB
+  case ARMII::AddrModeT1_2:
+    // tLDRHi, tLDRHr (watch out!), TLDRSH
+  case ARMII::AddrModeT1_4:
+    // tLDRi, tLDRr (watch out!)
+    BaseOp = &MI.getOperand(1);
+    Offset = MI.getOperand(2).isImm() ? MI.getOperand(2).getImm() : 0;
+    return MI.getOperand(2).isImm();
+  }
+  return false;
+}
+
+ARMBankConflictHazardRecognizer::ARMBankConflictHazardRecognizer(
+    const ScheduleDAG *DAG, int64_t CPUBankMask, bool CPUAssumeITCMConflict)
+    : ScheduleHazardRecognizer(), MF(DAG->MF), DL(DAG->MF.getDataLayout()),
+      DataMask(DataBankMask.getNumOccurrences() ? int64_t(DataBankMask)
+                                                : CPUBankMask),
+      AssumeITCMBankConflict(AssumeITCMConflict.getNumOccurrences()
+                                 ? AssumeITCMConflict
+                                 : CPUAssumeITCMConflict) {
+  MaxLookAhead = 1;
+}
+
+ScheduleHazardRecognizer::HazardType
+ARMBankConflictHazardRecognizer::CheckOffsets(unsigned O0, unsigned O1) {
+  return (((O0 ^ O1) & DataMask) != 0) ? NoHazard : Hazard;
+}
+
+ScheduleHazardRecognizer::HazardType
+ARMBankConflictHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
+  MachineInstr &L0 = *SU->getInstr();
+  if (!L0.mayLoad() || L0.mayStore() || L0.getNumMemOperands() != 1)
+    return NoHazard;
+
+  auto MO0 = *L0.memoperands().begin();
+  auto BaseVal0 = MO0->getValue();
+  auto BasePseudoVal0 = MO0->getPseudoValue();
+  int64_t Offset0 = 0;
+
+  if (MO0->getSize() > 4)
+    return NoHazard;
+
+  bool SPvalid = false;
+  const MachineOperand *SP = nullptr;
+  int64_t SPOffset0 = 0;
+
+  for (auto L1 : Accesses) {
+    auto MO1 = *L1->memoperands().begin();
+    auto BaseVal1 = MO1->getValue();
+    auto BasePseudoVal1 = MO1->getPseudoValue();
+    int64_t Offset1 = 0;
+
+    // Pointers to the same object
+    if (BaseVal0 && BaseVal1) {
+      const Value *Ptr0, *Ptr1;
+      Ptr0 = GetPointerBaseWithConstantOffset(BaseVal0, Offset0, DL, true);
+      Ptr1 = GetPointerBaseWithConstantOffset(BaseVal1, Offset1, DL, true);
+      if (Ptr0 == Ptr1 && Ptr0)
+        return CheckOffsets(Offset0, Offset1);
+    }
+
+    if (BasePseudoVal0 && BasePseudoVal1 &&
+        BasePseudoVal0->kind() == BasePseudoVal1->kind() &&
+        BasePseudoVal0->kind() == PseudoSourceValue::FixedStack) {
+      // Spills/fills
+      auto FS0 = cast<FixedStackPseudoSourceValue>(BasePseudoVal0);
+      auto FS1 = cast<FixedStackPseudoSourceValue>(BasePseudoVal1);
+      Offset0 = MF.getFrameInfo().getObjectOffset(FS0->getFrameIndex());
+      Offset1 = MF.getFrameInfo().getObjectOffset(FS1->getFrameIndex());
+      return CheckOffsets(Offset0, Offset1);
+    }
+
+    // Constant pools (likely in ITCM)
+    if (BasePseudoVal0 && BasePseudoVal1 &&
+        BasePseudoVal0->kind() == BasePseudoVal1->kind() &&
+        BasePseudoVal0->isConstantPool() && AssumeITCMBankConflict)
+      return Hazard;
+
+    // Is this a stack pointer-relative access?  We could in general try to
+    // use "is this the same register and is it unchanged?", but the
+    // memory operand tracking is highly likely to have already found that.
+    // What we're after here is bank conflicts between different objects in
+    // the stack frame.
+    if (!SPvalid) { // set up SP
+      if (!getBaseOffset(L0, SP, SPOffset0) || SP->getReg().id() != ARM::SP)
+        SP = nullptr;
+      SPvalid = true;
+    }
+    if (SP) {
+      int64_t SPOffset1;
+      const MachineOperand *SP1;
+      if (getBaseOffset(*L1, SP1, SPOffset1) && SP1->getReg().id() == ARM::SP)
+        return CheckOffsets(SPOffset0, SPOffset1);
+    }
+  }
+
+  return NoHazard;
+}
+
+void ARMBankConflictHazardRecognizer::Reset() { Accesses.clear(); }
+
+void ARMBankConflictHazardRecognizer::EmitInstruction(SUnit *SU) {
+  MachineInstr &MI = *SU->getInstr();
+  if (!MI.mayLoad() || MI.mayStore() || MI.getNumMemOperands() != 1)
+    return;
+
+  auto MO = *MI.memoperands().begin();
+  uint64_t Size1 = MO->getSize();
+  if (Size1 > 4)
+    return;
+  Accesses.push_back(&MI);
+}
+
+void ARMBankConflictHazardRecognizer::AdvanceCycle() { Accesses.clear(); }
+
+void ARMBankConflictHazardRecognizer::RecedeCycle() { Accesses.clear(); }
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.h b/llvm/lib/Target/ARM/ARMHazardRecognizer.h
index 6d29e0c82063f..c1f1bcd0a629b 100644
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.h
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.h
@@ -13,10 +13,21 @@
 #ifndef LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
 #define LLVM_LIB_TARGET_ARM_ARMHAZARDRECOGNIZER_H
 
+#include "ARMBaseInstrInfo.h"
+#include "llvm/ADT/BitmaskEnum.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
+#include "llvm/Support/DataTypes.h"
+#include <array>
+#include <initializer_list>
 
 namespace llvm {
 
+class DataLayout;
+class MachineFunction;
+class MachineInstr;
+class ScheduleDAG;
+
 // Hazards related to FP MLx instructions
 class ARMHazardRecognizerFPMLx : public ScheduleHazardRecognizer {
   MachineInstr *LastMI = nullptr;
@@ -32,6 +43,27 @@ class ARMHazardRecognizerFPMLx : public ScheduleHazardRecognizer {
   void RecedeCycle() override;
 };
 
+// Hazards related to bank conflicts
+class ARMBankConflictHazardRecognizer : public ScheduleHazardRecognizer {
+  SmallVector<MachineInstr *, 8> Accesses;
+  const MachineFunction &MF;
+  const DataLayout &DL;
+  int64_t DataMask;
+  bool AssumeITCMBankConflict;
+
+public:
+  ARMBankConflictHazardRecognizer(const ScheduleDAG *DAG, int64_t DDM,
+                                  bool ABC);
+  HazardType getHazardType(SUnit *SU, int Stalls) override;
+  void Reset() override;
+  void EmitInstruction(SUnit *SU) override;
+  void AdvanceCycle() override;
+  void RecedeCycle() override;
+
+private:
+  inline HazardType CheckOffsets(unsigned O0, unsigned O1);
+};
+
 } // end namespace llvm
 
 #endif
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index d90346df67da1..e2a3d302b1038 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -299,6 +299,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   case CortexR5:
   case CortexR7:
   case CortexM3:
+  case CortexM7:
   case CortexR52:
   case CortexX1:
     break;
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h
index 778d3ba22a2ff..ac7248ac29c98 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.h
+++ b/llvm/lib/Target/ARM/ARMSubtarget.h
@@ -66,6 +66,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
     CortexA8,
     CortexA9,
     CortexM3,
+    CortexM7,
     CortexR4,
     CortexR4F,
     CortexR5,
@@ -625,6 +626,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
   bool isCortexA15() const { return ARMProcFamily == CortexA15; }
   bool isSwift()    const { return ARMProcFamily == Swift; }
   bool isCortexM3() const { return ARMProcFamily == CortexM3; }
+  bool isCortexM7() const { return ARMProcFamily == CortexM7; }
   bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); }
   bool isCortexR5() const { return ARMProcFamily == CortexR5; }
   bool isKrait() const { return ARMProcFamily == Krait; }
diff --git a/llvm/lib/Target/CSKY/CMakeLists.txt b/llvm/lib/Target/CSKY/CMakeLists.txt
index 390b8ea4c8ce5..ec487ed34bbf9 100644
--- a/llvm/lib/Target/CSKY/CMakeLists.txt
+++ b/llvm/lib/Target/CSKY/CMakeLists.txt
@@ -4,6 +4,7 @@ set(LLVM_TARGET_DEFINITIONS CSKY.td)
 
 tablegen(LLVM CSKYGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info)
+tablegen(LLVM CSKYGenMCCodeEmitter.inc -gen-emitter)
 
 add_public_tablegen_target(CSKYCommonTableGen)
 
@@ -22,3 +23,4 @@ add_llvm_target(CSKYCodeGen
   )
 
 add_subdirectory(TargetInfo)
+add_subdirectory(MCTargetDesc)
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index afc82437e649d..7add217530e19 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -24,17 +24,17 @@ include "CSKYInstrFormats.td"
 
 class oimm<int num> : Operand<i32>,
   ImmLeaf<i32, "return isUInt<"#num#">(Imm - 1);"> {
-  let EncoderMethod = "getOImmOpValue<"#num#">";
+  let EncoderMethod = "getOImmOpValue";
 }
 
 class uimm<int num, int shift = 0> : Operand<i32>,
   ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(Imm);"> {
-  let EncoderMethod = "getImmOpValue<"#num#", "#shift#">";
+  let EncoderMethod = "getImmOpValue<"#shift#">";
 }
 
 class simm<int num, int shift = 0> : Operand<i32>,
   ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {
-  let EncoderMethod = "getImmOpValue<"#num#", "#shift#">";
+  let EncoderMethod = "getImmOpValue<"#shift#">";
 }
 
 def nimm_XFORM : SDNodeXForm<imm, [{
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/CSKY/MCTargetDesc/CMakeLists.txt
new file mode 100644
index 0000000000000..f5d7df002a881
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CMakeLists.txt
@@ -0,0 +1,15 @@
+add_llvm_component_library(LLVMCSKYDesc
+  CSKYAsmBackend.cpp
+  CSKYELFObjectWriter.cpp
+  CSKYMCAsmInfo.cpp
+  CSKYMCTargetDesc.cpp
+  CSKYMCCodeEmitter.cpp
+
+  LINK_COMPONENTS
+  MC
+  CSKYInfo
+  Support
+
+  ADD_TO_COMPONENT
+  CSKY
+)
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
new file mode 100644
index 0000000000000..e30123d64755e
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.cpp
@@ -0,0 +1,69 @@
+//===-- CSKYAsmBackend.cpp - CSKY Assembler Backend -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "CSKYAsmBackend.h"
+#include "MCTargetDesc/CSKYMCTargetDesc.h"
+#include "llvm/MC/MCAsmLayout.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCFixupKindInfo.h"
+#include "llvm/MC/MCObjectWriter.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "csky-asmbackend"
+
+using namespace llvm;
+
+std::unique_ptr<MCObjectTargetWriter>
+CSKYAsmBackend::createObjectTargetWriter() const {
+  return createCSKYELFObjectWriter();
+}
+
+unsigned int CSKYAsmBackend::getNumFixupKinds() const { return 1; }
+
+void CSKYAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
+                                const MCValue &Target,
+                                MutableArrayRef<char> Data, uint64_t Value,
+                                bool IsResolved,
+                                const MCSubtargetInfo *STI) const {
+  return;
+}
+
+bool CSKYAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
+                                          const MCRelaxableFragment *DF,
+                                          const MCAsmLayout &Layout) const {
+  return false;
+}
+
+void CSKYAsmBackend::relaxInstruction(MCInst &Inst,
+                                      const MCSubtargetInfo &STI) const {
+  llvm_unreachable("CSKYAsmBackend::relaxInstruction() unimplemented");
+}
+
+bool CSKYAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
+  if (Count % 2)
+    return false;
+
+  // MOV32 r0, r0
+  while (Count >= 4) {
+    OS.write("\xc4\x00\x48\x20", 4);
+    Count -= 4;
+  }
+  // MOV16 r0, r0
+  if (Count)
+    OS.write("\x6c\x03", 2);
+
+  return true;
+}
+
+MCAsmBackend *llvm::createCSKYAsmBackend(const Target &T,
+                                         const MCSubtargetInfo &STI,
+                                         const MCRegisterInfo &MRI,
+                                         const MCTargetOptions &Options) {
+  return new CSKYAsmBackend(STI, Options);
+}
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
new file mode 100644
index 0000000000000..b4cba4264e032
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h
@@ -0,0 +1,39 @@
+//===-- CSKYAsmBackend.h - CSKY Assembler Backend -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYASMBACKEND_H
+#define LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYASMBACKEND_H
+
+#include "llvm/MC/MCAsmBackend.h"
+#include "llvm/MC/MCTargetOptions.h"
+
+namespace llvm {
+
+class CSKYAsmBackend : public MCAsmBackend {
+
+public:
+  CSKYAsmBackend(const MCSubtargetInfo &STI, const MCTargetOptions &OP)
+      : MCAsmBackend(support::little) {}
+
+  unsigned int getNumFixupKinds() const override;
+  void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
+                  const MCValue &Target, MutableArrayRef<char> Data,
+                  uint64_t Value, bool IsResolved,
+                  const MCSubtargetInfo *STI) const override;
+  bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
+                            const MCRelaxableFragment *DF,
+                            const MCAsmLayout &Layout) const override;
+  void relaxInstruction(MCInst &Inst,
+                        const MCSubtargetInfo &STI) const override;
+  bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
+  std::unique_ptr<MCObjectTargetWriter>
+  createObjectTargetWriter() const override;
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYASMBACKEND_H
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
new file mode 100644
index 0000000000000..1636326322908
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYELFObjectWriter.cpp
@@ -0,0 +1,45 @@
+//===-- CSKYELFObjectWriter.cpp - CSKY ELF Writer -------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "CSKYMCTargetDesc.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCELFObjectWriter.h"
+#include "llvm/MC/MCObjectWriter.h"
+
+#define DEBUG_TYPE "csky-elf-object-writer"
+
+using namespace llvm;
+
+namespace {
+
+class CSKYELFObjectWriter : public MCELFObjectTargetWriter {
+public:
+  CSKYELFObjectWriter(uint8_t OSABI = 0)
+      : MCELFObjectTargetWriter(false, OSABI, ELF::EM_CSKY, true){};
+  ~CSKYELFObjectWriter() {}
+
+  unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
+                        const MCFixup &Fixup, bool IsPCRel) const override;
+};
+
+} // namespace
+
+unsigned CSKYELFObjectWriter::getRelocType(MCContext &Ctx,
+                                           const MCValue &Target,
+                                           const MCFixup &Fixup,
+                                           bool IsPCRel) const {
+  // Determine the type of the relocation.
+  switch ((unsigned)Fixup.getKind()) {
+  default:
+    llvm_unreachable("invalid fixup kind!");
+  }
+}
+
+std::unique_ptr<MCObjectTargetWriter> llvm::createCSKYELFObjectWriter() {
+  return std::make_unique<CSKYELFObjectWriter>();
+}
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp
new file mode 100644
index 0000000000000..668247bbbd87f
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.cpp
@@ -0,0 +1,25 @@
+//===-- CSKYMCAsmInfo.cpp - CSKY Asm properties ---------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declarations of the CSKYMCAsmInfo properties.
+//
+//===----------------------------------------------------------------------===//
+
+#include "CSKYMCAsmInfo.h"
+#include "llvm/BinaryFormat/Dwarf.h"
+#include "llvm/MC/MCStreamer.h"
+
+using namespace llvm;
+
+void CSKYMCAsmInfo::anchor() {}
+
+CSKYMCAsmInfo::CSKYMCAsmInfo(const Triple &TargetTriple) {
+  AlignmentIsInBytes = false;
+  SupportsDebugInformation = true;
+  CommentString = "#";
+}
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h
new file mode 100644
index 0000000000000..3e0609f195311
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h
@@ -0,0 +1,29 @@
+//===-- CSKYMCAsmInfo.h - CSKY Asm Info ------------------------*- C++ -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the declaration of the CSKYMCAsmInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCASMINFO_H
+#define LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCASMINFO_H
+
+#include "llvm/MC/MCAsmInfoELF.h"
+
+namespace llvm {
+class Triple;
+
+class CSKYMCAsmInfo : public MCAsmInfoELF {
+  void anchor() override;
+
+public:
+  explicit CSKYMCAsmInfo(const Triple &TargetTriple);
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCASMINFO_H
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
new file mode 100644
index 0000000000000..ed2b0e77b81af
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.cpp
@@ -0,0 +1,71 @@
+//===-- CSKYMCCodeEmitter.cpp - CSKY Code Emitter interface ---------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the CSKYMCCodeEmitter class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "CSKYMCCodeEmitter.h"
+#include "MCTargetDesc/CSKYMCTargetDesc.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/MC/MCInstBuilder.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/Support/EndianStream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "csky-mccode-emitter"
+
+STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
+
+unsigned CSKYMCCodeEmitter::getOImmOpValue(const MCInst &MI, unsigned Idx,
+                                           SmallVectorImpl<MCFixup> &Fixups,
+                                           const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(Idx);
+  assert(MO.isImm() && "Unexpected MO type.");
+  return MO.getImm() - 1;
+}
+
+void CSKYMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  const MCInstrDesc &Desc = MII.get(MI.getOpcode());
+  unsigned Size = Desc.getSize();
+  uint32_t Bin = getBinaryCodeForInstr(MI, Fixups, STI);
+
+  uint16_t LO16 = static_cast<uint16_t>(Bin);
+  uint16_t HI16 = static_cast<uint16_t>(Bin >> 16);
+
+  if (Size == 4)
+    support::endian::write<uint16_t>(OS, HI16, support::little);
+
+  support::endian::write<uint16_t>(OS, LO16, support::little);
+  ++MCNumEmitted; // Keep track of the # of mi's emitted.
+}
+
+unsigned
+CSKYMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
+                                     SmallVectorImpl<MCFixup> &Fixups,
+                                     const MCSubtargetInfo &STI) const {
+  if (MO.isReg())
+    return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
+
+  if (MO.isImm())
+    return static_cast<unsigned>(MO.getImm());
+
+  llvm_unreachable("Unhandled expression!");
+  return 0;
+}
+
+MCCodeEmitter *llvm::createCSKYMCCodeEmitter(const MCInstrInfo &MCII,
+                                             const MCRegisterInfo &MRI,
+                                             MCContext &Ctx) {
+  return new CSKYMCCodeEmitter(Ctx, MCII);
+}
+
+#include "CSKYGenMCCodeEmitter.inc"
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h
new file mode 100644
index 0000000000000..c850a4bab7450
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h
@@ -0,0 +1,61 @@
+//===-- CSKYMCCodeEmitter.cpp - CSKY Code Emitter interface ---------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the CSKYMCCodeEmitter class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCCODEEMITTER_H
+#define LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCCODEEMITTER_H
+
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCContext.h"
+
+namespace llvm {
+
+class CSKYMCCodeEmitter : public MCCodeEmitter {
+  MCContext &Ctx;
+  const MCInstrInfo &MII;
+
+public:
+  CSKYMCCodeEmitter(MCContext &Ctx, const MCInstrInfo &MII)
+      : Ctx(Ctx), MII(MII) {}
+
+  ~CSKYMCCodeEmitter() {}
+
+  void encodeInstruction(const MCInst &Inst, raw_ostream &OS,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const override;
+
+  // Generated by tablegen.
+  uint64_t getBinaryCodeForInstr(const MCInst &MI,
+                                 SmallVectorImpl<MCFixup> &Fixups,
+                                 const MCSubtargetInfo &STI) const;
+
+  // Default encoding method used by tablegen.
+  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
+                             SmallVectorImpl<MCFixup> &Fixups,
+                             const MCSubtargetInfo &STI) const;
+
+  template <int shift = 0>
+  unsigned getImmOpValue(const MCInst &MI, unsigned Idx,
+                         SmallVectorImpl<MCFixup> &Fixups,
+                         const MCSubtargetInfo &STI) const {
+    const MCOperand &MO = MI.getOperand(Idx);
+    assert(MO.isImm() && "Unexpected MO type.");
+    return (MO.getImm() >> shift);
+  }
+
+  unsigned getOImmOpValue(const MCInst &MI, unsigned Idx,
+                          SmallVectorImpl<MCFixup> &Fixups,
+                          const MCSubtargetInfo &STI) const;
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCCODEEMITTER_H
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp
new file mode 100644
index 0000000000000..876000a370047
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp
@@ -0,0 +1,62 @@
+//===-- CSKYMCTargetDesc.cpp - CSKY Target Descriptions -------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file provides CSKY specific target descriptions.
+///
+//===----------------------------------------------------------------------===//
+
+#include "CSKYMCTargetDesc.h"
+#include "CSKYAsmBackend.h"
+#include "CSKYMCAsmInfo.h"
+#include "CSKYMCCodeEmitter.h"
+#include "TargetInfo/CSKYTargetInfo.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/TargetRegistry.h"
+
+#define GET_INSTRINFO_MC_DESC
+#include "CSKYGenInstrInfo.inc"
+
+#define GET_REGINFO_MC_DESC
+#include "CSKYGenRegisterInfo.inc"
+
+using namespace llvm;
+
+static MCAsmInfo *createCSKYMCAsmInfo(const MCRegisterInfo &MRI,
+                                      const Triple &TT,
+                                      const MCTargetOptions &Options) {
+  MCAsmInfo *MAI = new CSKYMCAsmInfo(TT);
+
+  // Initial state of the frame pointer is SP.
+  unsigned Reg = MRI.getDwarfRegNum(CSKY::R14, true);
+  MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
+  MAI->addInitialFrameState(Inst);
+  return MAI;
+}
+
+static MCInstrInfo *createCSKYMCInstrInfo() {
+  MCInstrInfo *Info = new MCInstrInfo();
+  InitCSKYMCInstrInfo(Info);
+  return Info;
+}
+
+static MCRegisterInfo *createCSKYMCRegisterInfo(const Triple &TT) {
+  MCRegisterInfo *Info = new MCRegisterInfo();
+  InitCSKYMCRegisterInfo(Info, CSKY::R15);
+  return Info;
+}
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTargetMC() {
+  auto &CSKYTarget = getTheCSKYTarget();
+  TargetRegistry::RegisterMCAsmBackend(CSKYTarget, createCSKYAsmBackend);
+  TargetRegistry::RegisterMCAsmInfo(CSKYTarget, createCSKYMCAsmInfo);
+  TargetRegistry::RegisterMCInstrInfo(CSKYTarget, createCSKYMCInstrInfo);
+  TargetRegistry::RegisterMCRegInfo(CSKYTarget, createCSKYMCRegisterInfo);
+  TargetRegistry::RegisterMCCodeEmitter(CSKYTarget, createCSKYMCCodeEmitter);
+}
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h
new file mode 100644
index 0000000000000..da8a3b63a2f91
--- /dev/null
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h
@@ -0,0 +1,48 @@
+//===-- CSKYMCTargetDesc.h - CSKY Target Descriptions -----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides CSKY specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCTARGETDESC_H
+#define LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCTARGETDESC_H
+
+#include "llvm/MC/MCTargetOptions.h"
+#include <memory>
+
+namespace llvm {
+class MCAsmBackend;
+class MCCodeEmitter;
+class MCContext;
+class MCInstrInfo;
+class MCRegisterInfo;
+class MCObjectTargetWriter;
+class MCRegisterInfo;
+class MCSubtargetInfo;
+class Target;
+class Triple;
+
+std::unique_ptr<MCObjectTargetWriter> createCSKYELFObjectWriter();
+
+MCAsmBackend *createCSKYAsmBackend(const Target &T, const MCSubtargetInfo &STI,
+                                   const MCRegisterInfo &MRI,
+                                   const MCTargetOptions &Options);
+
+MCCodeEmitter *createCSKYMCCodeEmitter(const MCInstrInfo &MCII,
+                                       const MCRegisterInfo &MRI,
+                                       MCContext &Ctx);
+} // namespace llvm
+
+#define GET_REGINFO_ENUM
+#include "CSKYGenRegisterInfo.inc"
+
+#define GET_INSTRINFO_ENUM
+#include "CSKYGenInstrInfo.inc"
+
+#endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCTARGETDESC_H
diff --git a/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp b/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
index 45a84703370e9..800b10517aa7d 100644
--- a/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
+++ b/llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp
@@ -18,8 +18,3 @@ Target &llvm::getTheCSKYTarget() {
 extern "C" void LLVMInitializeCSKYTargetInfo() {
   RegisterTarget<Triple::csky> X(getTheCSKYTarget(), "csky", "C-SKY", "CSKY");
 }
-
-// FIXME: Temporary stub - this function must be defined for linking
-// to succeed and will be called unconditionally by llc, so must be a no-op.
-// Remove once this function is properly implemented.
-extern "C" void LLVMInitializeCSKYTargetMC() {}
diff --git a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
index a8e03a653e86a..04cd432f56c5c 100644
--- a/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp
@@ -472,10 +472,11 @@ static const NodeSet *node_class(GepNode *N, NodeSymRel &Rel) {
   // determining equality. The only purpose of the ordering is to eliminate
   // duplication due to the commutativity of equality/non-equality.
 static NodePair node_pair(GepNode *N1, GepNode *N2) {
-    uintptr_t P1 = uintptr_t(N1), P2 = uintptr_t(N2);
-    if (P1 <= P2)
-      return std::make_pair(N1, N2);
-    return std::make_pair(N2, N1);
+  uintptr_t P1 = reinterpret_cast<uintptr_t>(N1);
+  uintptr_t P2 = reinterpret_cast<uintptr_t>(N2);
+  if (P1 <= P2)
+    return std::make_pair(N1, N2);
+  return std::make_pair(N2, N1);
 }
 
 static unsigned node_hash(GepNode *N) {
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 2ff87c20ab25c..085acffdb5f05 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -1656,11 +1656,7 @@ bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
 
   // FIXME: Right now, the parser always allows any available
   // instruction, so the .machine directive is not useful.
-  // Implement ".machine any" (by doing nothing) for the benefit
-  // of existing assembler code.  Likewise, we can then implement
-  // ".machine push" and ".machine pop" as no-op.
-  if (CPU != "any" && CPU != "push" && CPU != "pop" && CPU != "ppc64")
-    return TokError("unrecognized machine type");
+  // In the wild, any/push/pop/ppc64/altivec/power[4-9] are seen.
 
   Parser.Lex();
 
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index b93322c155346..50ce11b8374fa 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -1644,11 +1644,18 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
     // offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red
     // zone add this offset back now.
 
+    // If the function has a base pointer, the stack pointer has been copied
+    // to it so we can restore it by copying in the other direction.
+    if (HasRedZone && HasBP) {
+      BuildMI(MBB, MBBI, dl, OrInst, RBReg).
+        addReg(BPReg).
+        addReg(BPReg);
+    }
     // If this function contained a fastcc call and GuaranteedTailCallOpt is
     // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
     // call which invalidates the stack pointer value in SP(0). So we use the
     // value of R31 in this case. Similar situation exists with setjmp.
-    if (FI->hasFastCall() || MF.exposesReturnsTwice()) {
+    else if (FI->hasFastCall() || MF.exposesReturnsTwice()) {
       assert(HasFP && "Expecting a valid frame pointer.");
       if (!HasRedZone)
         RBReg = FPReg;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 54e9adae40d7e..2f29811b20d85 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -2554,16 +2554,21 @@ let Predicates = [IsISA3_1, HasVSX] in {
             (COPY_TO_REGCLASS (XVCVBF16SPN RCCp.AToVSRC), VRRC)>;
 }
 
-let AddedComplexity = 400, Predicates = [IsISA3_1] in {
-  def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$rS, 0)), xoaddr:$src),
-            (STXVRBX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
-  def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$rS, 0)), xoaddr:$src),
-            (STXVRHX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
-  def : Pat<(store (i32 (vector_extract v4i32:$rS, 0)), xoaddr:$src),
-            (STXVRWX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
-  def : Pat<(store (i64 (vector_extract v2i64:$rS, 0)), xoaddr:$src),
-            (STXVRDX (COPY_TO_REGCLASS $rS, VSRC), xoaddr:$src)>;
-}
+let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in {
+  // Store element 0 of a VSX register to memory
+  def : Pat<(truncstorei8 (i32 (vector_extract v16i8:$src, 0)), xoaddr:$dst),
+            (STXVRBX (COPY_TO_REGCLASS v16i8:$src, VSRC), xoaddr:$dst)>;
+  def : Pat<(truncstorei16 (i32 (vector_extract v8i16:$src, 0)), xoaddr:$dst),
+            (STXVRHX (COPY_TO_REGCLASS v8i16:$src, VSRC), xoaddr:$dst)>;
+  def : Pat<(store (i32 (extractelt v4i32:$src, 0)), xoaddr:$dst),
+            (STXVRWX $src, xoaddr:$dst)>;
+  def : Pat<(store (f32 (extractelt v4f32:$src, 0)), xoaddr:$dst),
+            (STXVRWX $src, xoaddr:$dst)>;
+  def : Pat<(store (i64 (extractelt v2i64:$src, 0)), xoaddr:$dst),
+            (STXVRDX $src, xoaddr:$dst)>;
+  def : Pat<(store (f64 (extractelt v2f64:$src, 0)), xoaddr:$dst),
+            (STXVRDX $src, xoaddr:$dst)>;
+ }
 
 class xxevalPattern <dag pattern, bits<8> imm> :
   Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
index 1ae73bc8de43f..a8853609a7c87 100644
--- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp
@@ -338,8 +338,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) {
 
         // Create the symbol.
         MCContext &Context = MF->getContext();
-        MCSymbol *Symbol =
-            Context.createTempSymbol(Twine("pcrel"), false, false);
+        MCSymbol *Symbol = Context.createNamedTempSymbol("pcrel");
         MachineOperand PCRelLabel =
             MachineOperand::CreateMCSymbol(Symbol, PPCII::MO_PCREL_OPT_FLAG);
         Pair->DefInst->addOperand(*MF, PCRelLabel);
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 3225559f6c4d5..c735aaf5ec633 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2124,8 +2124,7 @@ void RISCVAsmParser::emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
   //             OP DestReg, TmpReg, %pcrel_lo(TmpLabel)
   MCContext &Ctx = getContext();
 
-  MCSymbol *TmpLabel = Ctx.createTempSymbol(
-      "pcrel_hi", /* AlwaysAddSuffix */ true, /* CanBeUnnamed */ false);
+  MCSymbol *TmpLabel = Ctx.createNamedTempSymbol("pcrel_hi");
   Out.emitLabel(TmpLabel);
 
   const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx);
@@ -2285,17 +2284,16 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
     return false;
 
   unsigned DestReg = Inst.getOperand(0).getReg();
-  unsigned CheckReg;
   // Operands[1] will be the first operand, DestReg.
   SMLoc Loc = Operands[1]->getStartLoc();
   if (TargetFlags & RISCVII::VS2Constraint) {
-    CheckReg = Inst.getOperand(1).getReg();
+    unsigned CheckReg = Inst.getOperand(1).getReg();
     if (DestReg == CheckReg)
       return Error(Loc, "The destination vector register group cannot overlap"
                         " the source vector register group.");
   }
   if ((TargetFlags & RISCVII::VS1Constraint) && (Inst.getOperand(2).isReg())) {
-    CheckReg = Inst.getOperand(2).getReg();
+    unsigned CheckReg = Inst.getOperand(2).getReg();
     if (DestReg == CheckReg)
       return Error(Loc, "The destination vector register group cannot overlap"
                         " the source vector register group.");
@@ -2315,10 +2313,10 @@ bool RISCVAsmParser::validateInstruction(MCInst &Inst,
     // same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister"
     // actually. We need to check the last operand to ensure whether it is
     // masked or not.
-    if ((TargetFlags & RISCVII::OneInput) && (Inst.getNumOperands() == 3))
-      CheckReg = Inst.getOperand(2).getReg();
-    else if (Inst.getNumOperands() == 4)
-      CheckReg = Inst.getOperand(3).getReg();
+    unsigned CheckReg = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
+    assert((CheckReg == RISCV::V0 || CheckReg == RISCV::NoRegister) &&
+           "Unexpected register for mask operand");
+
     if (DestReg == CheckReg)
       return Error(Loc, "The destination vector register group cannot overlap"
                         " the mask register.");
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index f06f7ea3f2afe..2a815863a81cf 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -432,6 +432,61 @@ bool RISCVDAGToDAGISel::SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
   return true;
 }
 
+bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
+  if (N.getOpcode() != ISD::SPLAT_VECTOR &&
+      N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64)
+    return false;
+  SplatVal = N.getOperand(0);
+  return true;
+}
+
+bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
+  if ((N.getOpcode() != ISD::SPLAT_VECTOR &&
+       N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64) ||
+      !isa<ConstantSDNode>(N.getOperand(0)))
+    return false;
+
+  int64_t SplatImm = cast<ConstantSDNode>(N.getOperand(0))->getSExtValue();
+
+  // Both ISD::SPLAT_VECTOR and RISCVISD::SPLAT_VECTOR_I64 share semantics when
+  // the operand type is wider than the resulting vector element type: an
+  // implicit truncation first takes place. Therefore, perform a manual
+  // truncation/sign-extension in order to ignore any truncated bits and catch
+  // any zero-extended immediate.
+  // For example, we wish to match (i8 -1) -> (XLenVT 255) as a simm5 by first
+  // sign-extending to (XLenVT -1).
+  auto XLenVT = Subtarget->getXLenVT();
+  assert(XLenVT == N.getOperand(0).getSimpleValueType() &&
+         "Unexpected splat operand type");
+  auto EltVT = N.getValueType().getVectorElementType();
+  if (EltVT.bitsLT(XLenVT)) {
+    SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits());
+  }
+
+  if (!isInt<5>(SplatImm))
+    return false;
+
+  SplatVal = CurDAG->getTargetConstant(SplatImm, SDLoc(N), XLenVT);
+  return true;
+}
+
+bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {
+  if ((N.getOpcode() != ISD::SPLAT_VECTOR &&
+       N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64) ||
+      !isa<ConstantSDNode>(N.getOperand(0)))
+    return false;
+
+  int64_t SplatImm = cast<ConstantSDNode>(N.getOperand(0))->getSExtValue();
+
+  if (!isUInt<5>(SplatImm))
+    return false;
+
+  SplatVal =
+      CurDAG->getTargetConstant(SplatImm, SDLoc(N), Subtarget->getXLenVT());
+
+  return true;
+}
+
 // Merge an ADDI into the offset of a load/store instruction where possible.
 // (load (addi base, off1), off2) -> (load base, off1+off2)
 // (store val, (addi base, off1), off2) -> (store val, base, off1+off2)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
index 4e382ee585002..34c8f1c824f51 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
@@ -50,6 +50,9 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
   bool SelectSLLIUW(SDValue N, SDValue &RS1, SDValue &Shamt);
   bool SelectSLOIW(SDValue N, SDValue &RS1, SDValue &Shamt);
   bool SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt);
+  bool selectVSplat(SDValue N, SDValue &SplatVal);
+  bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
+  bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
 
 // Include the pieces autogenerated from the target description.
 #include "RISCVGenDAGISel.inc"
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 5334666baf228..92bb316356c63 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -323,6 +323,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
   setOperationAction(ISD::BlockAddress, XLenVT, Custom);
   setOperationAction(ISD::ConstantPool, XLenVT, Custom);
+  setOperationAction(ISD::JumpTable, XLenVT, Custom);
 
   setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
 
@@ -360,6 +361,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
       setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
       setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
     }
+
+    for (auto VT : MVT::integer_scalable_vector_valuetypes())
+      setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
+
+    // We must custom-lower SPLAT_VECTOR vXi64 on RV32
+    if (!Subtarget.is64Bit())
+      setOperationAction(ISD::SPLAT_VECTOR, MVT::i64, Custom);
   }
 
   // Function alignments.
@@ -367,8 +375,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   setMinFunctionAlignment(FunctionAlignment);
   setPrefFunctionAlignment(FunctionAlignment);
 
-  // Effectively disable jump table generation.
-  setMinimumJumpTableEntries(INT_MAX);
+  setMinimumJumpTableEntries(5);
 
   // Jumps are expensive, compared to logic
   setJumpIsExpensive();
@@ -565,6 +572,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     return lowerBlockAddress(Op, DAG);
   case ISD::ConstantPool:
     return lowerConstantPool(Op, DAG);
+  case ISD::JumpTable:
+    return lowerJumpTable(Op, DAG);
   case ISD::GlobalTLSAddress:
     return lowerGlobalTLSAddress(Op, DAG);
   case ISD::SELECT:
@@ -623,6 +632,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
     return DAG.getNode(RISCVISD::GREVI, DL, VT, Op.getOperand(0),
                        DAG.getTargetConstant(Imm, DL, Subtarget.getXLenVT()));
   }
+  case ISD::SPLAT_VECTOR:
+    return lowerSPLATVECTOR(Op, DAG);
   }
 }
 
@@ -643,6 +654,11 @@ static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty,
                                    N->getOffset(), Flags);
 }
 
+static SDValue getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty,
+                             SelectionDAG &DAG, unsigned Flags) {
+  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
+}
+
 template <class NodeTy>
 SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
                                      bool IsLocal) const {
@@ -720,6 +736,13 @@ SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
   return getAddr(N, DAG);
 }
 
+SDValue RISCVTargetLowering::lowerJumpTable(SDValue Op,
+                                            SelectionDAG &DAG) const {
+  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
+
+  return getAddr(N, DAG);
+}
+
 SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
                                               SelectionDAG &DAG,
                                               bool UseGOT) const {
@@ -1028,6 +1051,53 @@ SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
   return DAG.getMergeValues(Parts, DL);
 }
 
+// Custom-lower a SPLAT_VECTOR where XLEN<SEW, as the SEW element type is
+// illegal (currently only vXi64 RV32).
+// FIXME: We could also catch non-constant sign-extended i32 values and lower
+// them to SPLAT_VECTOR_I64
+SDValue RISCVTargetLowering::lowerSPLATVECTOR(SDValue Op,
+                                              SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  EVT VecVT = Op.getValueType();
+  assert(!Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64 &&
+         "Unexpected SPLAT_VECTOR lowering");
+  SDValue SplatVal = Op.getOperand(0);
+
+  // If we can prove that the value is a sign-extended 32-bit value, lower this
+  // as a custom node in order to try and match RVV vector/scalar instructions.
+  if (auto *CVal = dyn_cast<ConstantSDNode>(SplatVal)) {
+    if (isInt<32>(CVal->getSExtValue()))
+      return DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT,
+                         DAG.getConstant(CVal->getSExtValue(), DL, MVT::i32));
+  }
+
+  // Else, on RV32 we lower an i64-element SPLAT_VECTOR thus, being careful not
+  // to accidentally sign-extend the 32-bit halves to the e64 SEW:
+  // vmv.v.x vX, hi
+  // vsll.vx vX, vX, /*32*/
+  // vmv.v.x vY, lo
+  // vsll.vx vY, vY, /*32*/
+  // vsrl.vx vY, vY, /*32*/
+  // vor.vv vX, vX, vY
+  SDValue One = DAG.getConstant(1, DL, MVT::i32);
+  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
+  SDValue ThirtyTwoV = DAG.getConstant(32, DL, VecVT);
+  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, SplatVal, Zero);
+  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, SplatVal, One);
+
+  Lo = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Lo);
+  Lo = DAG.getNode(ISD::SHL, DL, VecVT, Lo, ThirtyTwoV);
+  Lo = DAG.getNode(ISD::SRL, DL, VecVT, Lo, ThirtyTwoV);
+
+  if (isNullConstant(Hi))
+    return Lo;
+
+  Hi = DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Hi);
+  Hi = DAG.getNode(ISD::SHL, DL, VecVT, Hi, ThirtyTwoV);
+
+  return DAG.getNode(ISD::OR, DL, VecVT, Lo, Hi);
+}
+
 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
   unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
@@ -3364,7 +3434,7 @@ void RISCVTargetLowering::validateCCReservedRegs(
   const Function &F = MF.getFunction();
   const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
 
-  if (std::any_of(std::begin(Regs), std::end(Regs), [&STI](auto Reg) {
+  if (llvm::any_of(Regs, [&STI](auto Reg) {
         return STI.isRegisterReservedByUser(Reg.first);
       }))
     F.getContext().diagnose(DiagnosticInfoUnsupported{
@@ -3412,6 +3482,7 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
   NODE_NAME_CASE(GORCI)
   NODE_NAME_CASE(GORCIW)
   NODE_NAME_CASE(VMV_X_S)
+  NODE_NAME_CASE(SPLAT_VECTOR_I64)
   }
   // clang-format on
   return nullptr;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 28ce459e30278..3b71ed42b5ca6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -82,6 +82,9 @@ enum NodeType : unsigned {
   // sign extended from the vector element size. NOTE: The result size will
   // never be less than the vector element size.
   VMV_X_S,
+  // Splats an i64 scalar to a vector type (with element type i64) where the
+  // scalar is a sign-extended i32.
+  SPLAT_VECTOR_I64,
 };
 } // namespace RISCVISD
 
@@ -257,6 +260,7 @@ class RISCVTargetLowering : public TargetLowering {
   SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
@@ -264,6 +268,7 @@ class RISCVTargetLowering : public TargetLowering {
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
+  SDValue lowerSPLATVECTOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 21f0514146353..5c8d8fa65b308 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -49,33 +49,61 @@ def InstFormatCB     : InstFormat<15>;
 def InstFormatCJ     : InstFormat<16>;
 def InstFormatOther  : InstFormat<17>;
 
-class RISCVVConstraint<bits<4> val> {
-  bits<4> Value = val;
+class RISCVVConstraint<bits<3> val> {
+  bits<3> Value = val;
 }
-def NoConstraint  : RISCVVConstraint<0b0000>;
-def VS2Constraint : RISCVVConstraint<0b0001>;
-def VS1Constraint : RISCVVConstraint<0b0010>;
-def VMConstraint  : RISCVVConstraint<0b0100>;
-def OneInput      : RISCVVConstraint<0b1000>;
+def NoConstraint  : RISCVVConstraint<0b000>;
+def VS2Constraint : RISCVVConstraint<0b001>;
+def VS1Constraint : RISCVVConstraint<0b010>;
+def VMConstraint  : RISCVVConstraint<0b100>;
 
+// Illegal instructions:
+//
+// * The destination vector register group for a masked vector instruction
+// cannot overlap the source mask register (v0), unless the destination vector
+// register is being written with a mask value (e.g., comparisons) or the
+// scalar result of a reduction.
+//
+// * Widening: The destination vector register group cannot overlap a source
+// vector register group of a different EEW
+//
+// * Narrowing: The destination vector register group cannot overlap the
+// first source vector register group
+//
+// * For vadc and vsbc, an illegal instruction exception is raised if the
+// destination vector register is v0.
+//
+// * For vmadc and vmsbc, an illegal instruction exception is raised if the
+// destination vector register overlaps a source vector register group.
+//
+// * viota: An illegal instruction exception is raised if the destination
+// vector register group overlaps the source vector mask register. If the
+// instruction is masked, an illegal instruction exception is issued if the
+// destination vector register group overlaps v0.
+//
+// * v[f]slide[1]up: The destination vector register group for vslideup cannot
+// overlap the source vector register group.
+//
+// * vrgather: The destination vector register group cannot overlap with the
+// source vector register groups.
+//
+// * vcompress: The destination vector register group cannot overlap the
+// source vector register group or the source mask register
 def WidenV       : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VS1Constraint.Value,
                                         VMConstraint.Value)>;
 def WidenW       : RISCVVConstraint<!or(VS1Constraint.Value,
                                         VMConstraint.Value)>;
 def WidenCvt     : RISCVVConstraint<!or(VS2Constraint.Value,
-                                        VMConstraint.Value,
-                                        OneInput.Value)>;
+                                        VMConstraint.Value)>;
 def Narrow       : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value)>;
 def NarrowCvt    : RISCVVConstraint<!or(VS2Constraint.Value,
-                                        VMConstraint.Value,
-                                        OneInput.Value)>;
+                                        VMConstraint.Value)>;
 def Vmadc        : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VS1Constraint.Value)>;
 def Iota         : RISCVVConstraint<!or(VS2Constraint.Value,
-                                        VMConstraint.Value,
-                                        OneInput.Value)>;
+                                        VMConstraint.Value)>;
 def SlideUp      : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value)>;
 def Vrgather     : RISCVVConstraint<!or(VS2Constraint.Value,
@@ -138,7 +166,7 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
 
   // Defaults
   RISCVVConstraint RVVConstraint = NoConstraint;
-  let TSFlags{8-5} = RVVConstraint.Value;
+  let TSFlags{7-5} = RVVConstraint.Value;
 }
 
 // Pseudo instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 677d9f392bb34..b015ae0d2dba0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -111,6 +111,7 @@ class VWholeLoad<bits<3> nf, string opcodestr>
                 opcodestr, "$vd, (${rs1})"> {
   let vm = 1;
   let Uses = [];
+  let RVVConstraint = NoConstraint;
 }
 
 // segment load vd, (rs1), vm
@@ -700,7 +701,8 @@ defm VWMACCUS_V : VALUr_MV_X<"vwmaccus", 0b111110>;
 defm VMERGE_V : VALUm_IV_V_X_I<"vmerge", 0b010111>;
 
 // Vector Integer Move Instructions
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1,
+    RVVConstraint = NoConstraint  in {
 // op vd, vs1
 def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VR:$vd),
                        (ins VR:$vs1), "vmv.v.v", "$vd, $vs1">;
@@ -827,6 +829,7 @@ def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
 }
 
 // Vector Floating-Point Move Instruction
+let RVVConstraint = NoConstraint in
 def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VR:$vd),
                        (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> {
   let vs2 = 0;
@@ -912,6 +915,7 @@ defm VFWREDSUM : VALU_FV_V<"vfwredsum", 0b110001>;
 
 let Predicates = [HasStdExtV] in {
 // Vector Mask-Register Logical Instructions
+let RVVConstraint = NoConstraint in {
 defm VMAND_M : VALU_MV_Mask<"vmand", 0b011001, "m">;
 defm VMNAND_M : VALU_MV_Mask<"vmnand", 0b011101, "m">;
 defm VMANDNOT_M : VALU_MV_Mask<"vmandnot", 0b011000, "m">;
@@ -920,6 +924,7 @@ defm VMOR_M : VALU_MV_Mask<"vmor", 0b011010, "m">;
 defm VMNOR_M : VALU_MV_Mask<"vmnor", 0b011110, "m">;
 defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">;
 defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">;
+}
 
 def : InstAlias<"vmmv.m $vd, $vs",
                 (VMAND_MM VR:$vd, VR:$vs, VR:$vs)>;
@@ -930,7 +935,8 @@ def : InstAlias<"vmset.m $vd",
 def : InstAlias<"vmnot.m $vd, $vs",
                 (VMNAND_MM VR:$vd, VR:$vs, VR:$vs)>;
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+    RVVConstraint = NoConstraint  in {
 // Vector mask population count vpopc
 def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
                         (ins VR:$vs2, VMaskOp:$vm),
@@ -964,7 +970,7 @@ def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
 }
 
 // Integer Scalar Move Instructions
-let vm = 1 in {
+let vm = 1, RVVConstraint = NoConstraint in {
 def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
                       (ins VR:$vs2), "vmv.x.s", "$vd, $vs2">;
 let Constraints = "$vd = $vd_wb" in
@@ -976,7 +982,8 @@ def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VR:$vd_wb),
 } // Predicates = [HasStdExtV]
 
 let Predicates = [HasStdExtV, HasStdExtF] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1,
+    RVVConstraint = NoConstraint  in {
 // Floating-Point Scalar Move Instructions
 def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
                       (ins VR:$vs2), "vfmv.f.s", "$vd, $vs2">;
@@ -1018,7 +1025,8 @@ let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
 defm VCOMPRESS_V : VALU_MV_Mask<"vcompress", 0b010111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+    RVVConstraint = NoConstraint in {
 foreach nf = [1, 2, 4, 8] in {
   def VMV#nf#R_V  : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VR:$vd),
                             (ins VR:$vs2), "vmv" # nf # "r.v",
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 050b17c440f57..72e41daa0c3a9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -110,32 +110,35 @@ class GroupVTypeInfo<ValueType Vec, ValueType VecM1, ValueType Mas, int Sew,
 
 defset list<VTypeInfo> AllVectors = {
   defset list<VTypeInfo> AllIntegerVectors = {
-    def VI8MF8: VTypeInfo<vint8mf8_t,  vbool64_t,  8, VR, V_MF8>;
-    def VI8MF4: VTypeInfo<vint8mf4_t,  vbool32_t,  8, VR, V_MF4>;
-    def VI8MF2: VTypeInfo<vint8mf2_t,  vbool16_t,  8, VR, V_MF2>;
-    def VI8M1: VTypeInfo<vint8m1_t,   vbool8_t,   8, VR, V_M1>;
-    def VI16MF4: VTypeInfo<vint16mf4_t, vbool64_t, 16, VR, V_MF4>;
-    def VI16MF2: VTypeInfo<vint16mf2_t, vbool32_t, 16, VR, V_MF2>;
-    def VI16M1: VTypeInfo<vint16m1_t,  vbool16_t, 16, VR, V_M1>;
-    def VI32MF2: VTypeInfo<vint32mf2_t, vbool64_t, 32, VR, V_MF2>;
-    def VI32M1: VTypeInfo<vint32m1_t,  vbool32_t, 32, VR, V_M1>;
-    def VI64M1: VTypeInfo<vint64m1_t,  vbool64_t, 64, VR, V_M1>;
-
-    def VI8M2: GroupVTypeInfo<vint8m2_t, vint8m1_t, vbool4_t, 8, VRM2, V_M2>;
-    def VI8M4: GroupVTypeInfo<vint8m4_t, vint8m1_t, vbool2_t, 8, VRM4, V_M4>;
-    def VI8M8: GroupVTypeInfo<vint8m8_t, vint8m1_t, vbool1_t, 8, VRM8, V_M8>;
-
-    def VI16M2: GroupVTypeInfo<vint16m2_t,vint16m1_t,vbool8_t, 16,VRM2, V_M2>;
-    def VI16M4: GroupVTypeInfo<vint16m4_t,vint16m1_t,vbool4_t, 16,VRM4, V_M4>;
-    def VI16M8: GroupVTypeInfo<vint16m8_t,vint16m1_t,vbool2_t, 16,VRM8, V_M8>;
-
-    def VI32M2: GroupVTypeInfo<vint32m2_t,vint32m1_t,vbool16_t,32,VRM2, V_M2>;
-    def VI32M4: GroupVTypeInfo<vint32m4_t,vint32m1_t,vbool8_t, 32,VRM4, V_M4>;
-    def VI32M8: GroupVTypeInfo<vint32m8_t,vint32m1_t,vbool4_t, 32,VRM8, V_M8>;
-
-    def VI64M2: GroupVTypeInfo<vint64m2_t,vint64m1_t,vbool32_t,64,VRM2, V_M2>;
-    def VI64M4: GroupVTypeInfo<vint64m4_t,vint64m1_t,vbool16_t,64,VRM4, V_M4>;
-    def VI64M8: GroupVTypeInfo<vint64m8_t,vint64m1_t,vbool8_t, 64,VRM8, V_M8>;
+    defset list<VTypeInfo> NoGroupIntegerVectors = {
+      def VI8MF8: VTypeInfo<vint8mf8_t,  vbool64_t,  8, VR, V_MF8>;
+      def VI8MF4: VTypeInfo<vint8mf4_t,  vbool32_t,  8, VR, V_MF4>;
+      def VI8MF2: VTypeInfo<vint8mf2_t,  vbool16_t,  8, VR, V_MF2>;
+      def VI8M1: VTypeInfo<vint8m1_t,   vbool8_t,   8, VR, V_M1>;
+      def VI16MF4: VTypeInfo<vint16mf4_t, vbool64_t, 16, VR, V_MF4>;
+      def VI16MF2: VTypeInfo<vint16mf2_t, vbool32_t, 16, VR, V_MF2>;
+      def VI16M1: VTypeInfo<vint16m1_t,  vbool16_t, 16, VR, V_M1>;
+      def VI32MF2: VTypeInfo<vint32mf2_t, vbool64_t, 32, VR, V_MF2>;
+      def VI32M1: VTypeInfo<vint32m1_t,  vbool32_t, 32, VR, V_M1>;
+      def VI64M1: VTypeInfo<vint64m1_t,  vbool64_t, 64, VR, V_M1>;
+    }
+    defset list<GroupVTypeInfo> GroupIntegerVectors = {
+      def VI8M2: GroupVTypeInfo<vint8m2_t, vint8m1_t, vbool4_t, 8, VRM2, V_M2>;
+      def VI8M4: GroupVTypeInfo<vint8m4_t, vint8m1_t, vbool2_t, 8, VRM4, V_M4>;
+      def VI8M8: GroupVTypeInfo<vint8m8_t, vint8m1_t, vbool1_t, 8, VRM8, V_M8>;
+
+      def VI16M2: GroupVTypeInfo<vint16m2_t,vint16m1_t,vbool8_t, 16,VRM2, V_M2>;
+      def VI16M4: GroupVTypeInfo<vint16m4_t,vint16m1_t,vbool4_t, 16,VRM4, V_M4>;
+      def VI16M8: GroupVTypeInfo<vint16m8_t,vint16m1_t,vbool2_t, 16,VRM8, V_M8>;
+
+      def VI32M2: GroupVTypeInfo<vint32m2_t,vint32m1_t,vbool16_t,32,VRM2, V_M2>;
+      def VI32M4: GroupVTypeInfo<vint32m4_t,vint32m1_t,vbool8_t, 32,VRM4, V_M4>;
+      def VI32M8: GroupVTypeInfo<vint32m8_t,vint32m1_t,vbool4_t, 32,VRM8, V_M8>;
+
+      def VI64M2: GroupVTypeInfo<vint64m2_t,vint64m1_t,vbool32_t,64,VRM2, V_M2>;
+      def VI64M4: GroupVTypeInfo<vint64m4_t,vint64m1_t,vbool16_t,64,VRM4, V_M4>;
+      def VI64M8: GroupVTypeInfo<vint64m8_t,vint64m1_t,vbool8_t, 64,VRM8, V_M8>;
+    }
   }
 
   defset list<VTypeInfo> AllFloatVectors = {
@@ -175,6 +178,36 @@ defset list<VTypeInfo> AllVectors = {
   }
 }
 
+// This functor is used to obtain the int vector type that has the same SEW and
+// multiplier as the input parameter type
+class GetIntVTypeInfo<VTypeInfo vti>
+{
+  // Equivalent integer vector type. Eg.
+  //   VI8M1 → VI8M1 (identity)
+  //   VF64M4 → VI64M4
+  VTypeInfo Vti = !cast<VTypeInfo>(!subst("VF", "VI", !cast<string>(vti)));
+}
+
+class MTypeInfo<ValueType Mas, LMULInfo M, string Bx> {
+  ValueType Mask = Mas;
+  // {SEW, VLMul} values set a valid VType to deal with this mask type.
+  // we assume SEW=8 and set corresponding LMUL.
+  int SEW = 8;
+  LMULInfo LMul = M;
+  string BX = Bx; // Appendix of mask operations.
+}
+
+defset list<MTypeInfo> AllMasks = {
+  // vbool<n>_t, <n> = SEW/LMUL, we assume SEW=8 and corresponding LMUL.
+  def : MTypeInfo<vbool64_t, V_MF8, "B1">;
+  def : MTypeInfo<vbool32_t, V_MF4, "B2">;
+  def : MTypeInfo<vbool16_t, V_MF2, "B4">;
+  def : MTypeInfo<vbool8_t, V_M1, "B8">;
+  def : MTypeInfo<vbool4_t, V_M2, "B16">;
+  def : MTypeInfo<vbool2_t, V_M4, "B32">;
+  def : MTypeInfo<vbool1_t, V_M8, "B64">;
+}
+
 class VTypeInfoToWide<VTypeInfo vti, VTypeInfo wti>
 {
   VTypeInfo Vti = vti;
@@ -262,8 +295,15 @@ class PseudoToVInst<string PseudoInst> {
                  !subst("_MF2", "",
                  !subst("_MF4", "",
                  !subst("_MF8", "",
+                 !subst("_B1", "",
+                 !subst("_B2", "",
+                 !subst("_B4", "",
+                 !subst("_B8", "",
+                 !subst("_B16", "",
+                 !subst("_B32", "",
+                 !subst("_B64", "",
                  !subst("_MASK", "",
-                 !subst("Pseudo", "", PseudoInst)))))))));
+                 !subst("Pseudo", "", PseudoInst))))))))))))))));
 }
 
 // The destination vector register group for a masked vector instruction cannot
@@ -467,6 +507,103 @@ class VPseudoUnaryNoDummyMask<VReg RetClass,
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
+class VPseudoNullaryNoMask<VReg RegClass>:
+      Pseudo<(outs RegClass:$rd),
+             (ins GPR:$vl, ixlenimm:$sew),
+             []>, RISCVVPseudo {
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Uses = [VL, VTYPE];
+  let VLIndex = 1;
+  let SEWIndex = 2;
+  let HasDummyMask = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+class VPseudoNullaryMask<VReg RegClass>:
+      Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
+             (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, GPR:$vl,
+              ixlenimm:$sew), []>, RISCVVPseudo {
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Constraints ="$rd = $merge";
+  let Uses = [VL, VTYPE];
+  let VLIndex = 3;
+  let SEWIndex = 4;
+  let MergeOpIndex = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+// RetClass could be GPR or VReg.
+class VPseudoUnaryNoMask<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
+        Pseudo<(outs RetClass:$rd),
+               (ins OpClass:$rs2, GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Constraints = Constraint;
+  let Uses = [VL, VTYPE];
+  let VLIndex = 2;
+  let SEWIndex = 3;
+  let HasDummyMask = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
+        Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
+               (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
+                    VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
+  let Uses = [VL, VTYPE];
+  let VLIndex = 4;
+  let SEWIndex = 5;
+  let MergeOpIndex = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+// mask unary operation without maskedoff
+class VPseudoMaskUnarySOutMask:
+        Pseudo<(outs GPR:$rd),
+               (ins VR:$rs1, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Uses = [VL, VTYPE];
+  let VLIndex = 3;
+  let SEWIndex = 4;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
+// Masked mask operation have no $rd=$merge constraints
+class VPseudoUnaryMOutMask:
+        Pseudo<(outs VR:$rd),
+               (ins VR:$merge, VR:$rs1, VMaskOp:$vm, GPR:$vl, ixlenimm:$sew), []>,
+        RISCVVPseudo {
+  let mayLoad = 0;
+  let mayStore = 0;
+  let hasSideEffects = 0;
+  let usesCustomInserter = 1;
+  let Constraints = "$rd = $merge";
+  let Uses = [VL, VTYPE];
+  let VLIndex = 4;
+  let SEWIndex = 5;
+  let MergeOpIndex = 1;
+  let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
+}
+
 class VPseudoBinaryNoMask<VReg RetClass,
                           VReg Op1Class,
                           DAGOperand Op2Class,
@@ -543,7 +680,7 @@ class VPseudoBinaryCarryIn<VReg RetClass,
                            bit CarryIn,
                            string Constraint> :
         Pseudo<(outs RetClass:$rd),
-               !if(!eq(CarryIn, 1),
+               !if(CarryIn,
                   (ins Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, GPR:$vl,
                        ixlenimm:$sew),
                   (ins Op1Class:$rs2, Op2Class:$rs1, GPR:$vl, ixlenimm:$sew)), []>,
@@ -554,8 +691,8 @@ class VPseudoBinaryCarryIn<VReg RetClass,
   let usesCustomInserter = 1;
   let Constraints = Constraint;
   let Uses = [VL, VTYPE];
-  let VLIndex = !if(!eq(CarryIn, 1), 4, 3);
-  let SEWIndex = !if(!eq(CarryIn, 1), 5, 4);
+  let VLIndex = !if(CarryIn, 4, 3);
+  let SEWIndex = !if(CarryIn, 5, 4);
   let MergeOpIndex = InvalidIndex.V;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
   let VLMul = MInfo.value;
@@ -655,6 +792,45 @@ multiclass VPseudoIStore {
   }
 }
 
+multiclass VPseudoUnaryS_M {
+  foreach mti = AllMasks in
+  {
+    let VLMul = mti.LMul.value in {
+      def "_M_" # mti.BX : VPseudoUnaryNoMask<GPR, VR>;
+      def "_M_" # mti.BX # "_MASK" : VPseudoMaskUnarySOutMask;
+    }
+  }
+}
+
+multiclass VPseudoUnaryM_M {
+  foreach mti = AllMasks in
+  {
+    let VLMul = mti.LMul.value in {
+      def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR>;
+      def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR>;
+    }
+  }
+}
+
+multiclass VPseudoMaskNullaryV {
+  foreach m = MxList.m in {
+    let VLMul = m.value in {
+      def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>;
+      def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>;
+    }
+  }
+}
+
+multiclass VPseudoUnaryV_M {
+  defvar constraint = "@earlyclobber $rd";
+  foreach m = MxList.m in {
+    let VLMul = m.value in {
+      def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>;
+      def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>;
+    }
+  }
+}
+
 multiclass VPseudoBinary<VReg RetClass,
                          VReg Op1Class,
                          DAGOperand Op2Class,
@@ -668,20 +844,27 @@ multiclass VPseudoBinary<VReg RetClass,
   }
 }
 
-multiclass VPseudoBinaryV_VV {
+multiclass VPseudoBinaryV_VV<string Constraint = ""> {
   foreach m = MxList.m in
-    defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m>;
+    defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
 }
 
-multiclass VPseudoBinaryV_VX<bit IsFloat> {
+multiclass VPseudoBinaryV_VX<bit IsFloat, string Constraint = ""> {
   foreach m = MxList.m in
-    defm !if(!eq(IsFloat, 0), "_VX", "_VF") : VPseudoBinary<m.vrclass, m.vrclass,
-                             !if(!eq(IsFloat, 0), GPR, FPR32), m>;
+    defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.vrclass, m.vrclass,
+                             !if(IsFloat, FPR32, GPR), m, Constraint>;
 }
 
-multiclass VPseudoBinaryV_VI<Operand ImmType = simm5> {
+multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList.m in
-    defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m>;
+    defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
+}
+
+multiclass VPseudoBinaryM_MM {
+  foreach m = MxList.m in
+    let VLMul = m.value in {
+      def "_MM_" # m.MX : VPseudoBinaryNoMask<VR, VR, VR, "">;
+    }
 }
 
 // We use earlyclobber here due to
@@ -699,8 +882,8 @@ multiclass VPseudoBinaryW_VV {
 
 multiclass VPseudoBinaryW_VX<bit IsFloat> {
   foreach m = MxList.m[0-5] in
-    defm !if(!eq(IsFloat, 0), "_VX", "_VF") : VPseudoBinary<m.wvrclass, m.vrclass,
-                             !if(!eq(IsFloat, 0), GPR, FPR32), m,
+    defm !if(IsFloat, "_VF", "_VX") : VPseudoBinary<m.wvrclass, m.vrclass,
+                             !if(IsFloat, FPR32, GPR), m,
                              "@earlyclobber $rd">;
 }
 
@@ -712,8 +895,8 @@ multiclass VPseudoBinaryW_WV {
 
 multiclass VPseudoBinaryW_WX<bit IsFloat> {
   foreach m = MxList.m[0-5] in
-    defm !if(!eq(IsFloat, 0), "_WX", "_WF") : VPseudoBinary<m.wvrclass, m.wvrclass,
-                             !if(!eq(IsFloat, 0), GPR, FPR32), m,
+    defm !if(IsFloat, "_WF", "_WX") : VPseudoBinary<m.wvrclass, m.wvrclass,
+                             !if(IsFloat, FPR32, GPR), m,
                              "@earlyclobber $rd">;
 }
 
@@ -741,29 +924,30 @@ multiclass VPseudoBinaryV_WI {
 multiclass VPseudoBinaryV_VM<bit CarryOut = 0, bit CarryIn = 1,
                              string Constraint = ""> {
   foreach m = MxList.m in
-    def "_VV" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX :
-      VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR,
-                           !if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)),
+    def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
+      VPseudoBinaryCarryIn<!if(CarryOut, VR,
+                           !if(!and(CarryIn, !not(CarryOut)),
                                GetVRegNoV0<m.vrclass>.R, m.vrclass)),
                            m.vrclass, m.vrclass, m, CarryIn, Constraint>;
 }
 
 multiclass VPseudoBinaryV_XM<bit CarryOut = 0, bit CarryIn = 1,
-                             string Constraint = ""> {
+                             string Constraint = "", bit IsFloat = 0> {
   foreach m = MxList.m in
-    def "_VX" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX :
-      VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR,
-                           !if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)),
+    def !if(IsFloat, "_VF", "_VX") # !if(CarryIn, "M", "") # "_" # m.MX :
+      VPseudoBinaryCarryIn<!if(CarryOut, VR,
+                           !if(!and(CarryIn, !not(CarryOut)),
                                GetVRegNoV0<m.vrclass>.R, m.vrclass)),
-                           m.vrclass, GPR, m, CarryIn, Constraint>;
+                           m.vrclass, !if(IsFloat, FPR32, GPR),
+                           m, CarryIn, Constraint>;
 }
 
 multiclass VPseudoBinaryV_IM<bit CarryOut = 0, bit CarryIn = 1,
                              string Constraint = ""> {
   foreach m = MxList.m in
-    def "_VI" # !if(!eq(CarryIn, 1), "M", "") # "_" # m.MX :
-      VPseudoBinaryCarryIn<!if(!eq(CarryOut, 1), VR,
-                           !if(!and(!eq(CarryIn, 1), !eq(CarryOut, 0)),
+    def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
+      VPseudoBinaryCarryIn<!if(CarryOut, VR,
+                           !if(!and(CarryIn, !not(CarryOut)),
                                GetVRegNoV0<m.vrclass>.R, m.vrclass)),
                            m.vrclass, simm5, m, CarryIn, Constraint>;
 }
@@ -778,10 +962,39 @@ multiclass VPseudoUnaryV_V_X_I_NoDummyMask {
   }
 }
 
-multiclass VPseudoBinaryV_VV_VX_VI<Operand ImmType = simm5> {
-  defm "" : VPseudoBinaryV_VV;
-  defm "" : VPseudoBinaryV_VX</*IsFloat=*/0>;
-  defm "" : VPseudoBinaryV_VI<ImmType>;
+multiclass VPseudoUnaryV_F_NoDummyMask {
+  foreach m = MxList.m in {
+    let VLMul = m.value in {
+      def "_F_" # m.MX : VPseudoUnaryNoDummyMask<m.vrclass, FPR32>;
+    }
+  }
+}
+
+// The destination EEW is 1.
+// The source EEW is 8, 16, 32, or 64.
+// When the destination EEW is different from source EEW, we need to use
+// @earlyclobber to avoid the overlap between destination and source registers.
+multiclass VPseudoBinaryM_VV {
+  foreach m = MxList.m in
+    defm _VV : VPseudoBinary<VR, m.vrclass, m.vrclass, m, "@earlyclobber $rd">;
+}
+
+multiclass VPseudoBinaryM_VX<bit IsFloat> {
+  foreach m = MxList.m in
+    defm !if(IsFloat, "_VF", "_VX") :
+      VPseudoBinary<VR, m.vrclass, !if(IsFloat, FPR32, GPR), m,
+                    "@earlyclobber $rd">;
+}
+
+multiclass VPseudoBinaryM_VI {
+  foreach m = MxList.m in
+    defm _VI : VPseudoBinary<VR, m.vrclass, simm5, m, "@earlyclobber $rd">;
+}
+
+multiclass VPseudoBinaryV_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
+  defm "" : VPseudoBinaryV_VV<Constraint>;
+  defm "" : VPseudoBinaryV_VX</*IsFloat=*/false, Constraint>;
+  defm "" : VPseudoBinaryV_VI<ImmType, Constraint>;
 }
 
 multiclass VPseudoBinaryV_VV_VX<bit IsFloat = 0> {
@@ -854,76 +1067,138 @@ multiclass VPseudoTernary<VReg RetClass,
   }
 }
 
+multiclass VPseudoTernaryV_VV<string Constraint = ""> {
+  foreach m = MxList.m in
+    defm _VV : VPseudoTernary<m.vrclass, m.vrclass, m.vrclass, m, Constraint>;
+}
+
 multiclass VPseudoTernaryV_VX<string Constraint = ""> {
   foreach m = MxList.m in
     defm _VX : VPseudoTernary<m.vrclass, m.vrclass, GPR, m, Constraint>;
 }
 
+multiclass VPseudoTernaryV_VX_AAXA<bit IsFloat, string Constraint = ""> {
+  foreach m = MxList.m in
+    defm !if(IsFloat, "_VF", "_VX") : VPseudoTernary<m.vrclass,
+                             !if(IsFloat, FPR32, GPR), m.vrclass, m, Constraint>;
+}
+
+multiclass VPseudoTernaryW_VV {
+  defvar constraint = "@earlyclobber $rd";
+  foreach m = MxList.m in
+    defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>;
+}
+
+multiclass VPseudoTernaryW_VX<bit IsFloat> {
+  defvar constraint = "@earlyclobber $rd";
+  foreach m = MxList.m in
+    defm !if(IsFloat, "_VF", "_VX")  : VPseudoTernary<m.wvrclass,
+                             !if(IsFloat, FPR32, GPR), m.vrclass, m, constraint>;
+}
+
 multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList.m in
     defm _VI : VPseudoTernary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
 }
 
+multiclass VPseudoTernaryV_VV_VX_AAXA<bit IsFloat = 0, string Constraint = ""> {
+  defm "" : VPseudoTernaryV_VV<Constraint>;
+  defm "" : VPseudoTernaryV_VX_AAXA<IsFloat, Constraint>;
+}
+
 multiclass VPseudoTernaryV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   defm "" : VPseudoTernaryV_VX<Constraint>;
   defm "" : VPseudoTernaryV_VI<ImmType, Constraint>;
 }
 
-//===----------------------------------------------------------------------===//
-// Helpers to define the SDNode patterns.
-//===----------------------------------------------------------------------===//
+multiclass VPseudoTernaryW_VV_VX<bit IsFloat = false> {
+  defm "" : VPseudoTernaryW_VV;
+  defm "" : VPseudoTernaryW_VX<IsFloat>;
+}
 
-multiclass VPatUSLoadStoreSDNode<LLVMType type,
-                                 LLVMType mask_type,
-                                 int sew,
-                                 LMULInfo vlmul,
-                                 RegisterClass reg_rs1,
-                                 VReg reg_class>
-{
-  defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
-  defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
-  // Load
-  def : Pat<(type (load reg_rs1:$rs1)),
-            (load_instr reg_rs1:$rs1, VLMax, sew)>;
-  // Store
-  def : Pat<(store type:$rs2, reg_rs1:$rs1),
-            (store_instr reg_class:$rs2, reg_rs1:$rs1, VLMax, sew)>;
+multiclass VPseudoBinaryM_VV_VX_VI {
+  defm "" : VPseudoBinaryM_VV;
+  defm "" : VPseudoBinaryM_VX</*IsFloat=*/0>;
+  defm "" : VPseudoBinaryM_VI;
 }
 
-multiclass VPatUSLoadStoreSDNodes<RegisterClass reg_rs1> {
-  foreach vti = AllVectors in
-    defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.Mask, vti.SEW, vti.LMul,
-                                    reg_rs1, vti.RegClass>;
+multiclass VPseudoBinaryM_VV_VX<bit IsFloat = 0> {
+  defm "" : VPseudoBinaryM_VV;
+  defm "" : VPseudoBinaryM_VX<IsFloat>;
 }
 
-class VPatBinarySDNode<SDNode vop,
-                       string instruction_name,
-                       ValueType result_type,
-                       ValueType op_type,
-                       ValueType mask_type,
-                       int sew,
-                       LMULInfo vlmul,
-                       VReg RetClass,
-                       VReg op_reg_class> :
-    Pat<(result_type (vop
-                     (op_type op_reg_class:$rs1),
-                     (op_type op_reg_class:$rs2))),
-                     (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
-                     op_reg_class:$rs1,
-                     op_reg_class:$rs2,
-                     VLMax, sew)>;
-
-multiclass VPatBinarySDNode<SDNode vop, string instruction_name>
-{
-  foreach vti = AllIntegerVectors in
-    def : VPatBinarySDNode<vop, instruction_name,
-                           vti.Vector, vti.Vector, vti.Mask, vti.SEW,
-                           vti.LMul, vti.RegClass, vti.RegClass>;
+multiclass VPseudoBinaryM_VX_VI {
+  defm "" : VPseudoBinaryM_VX</*IsFloat=*/0>;
+  defm "" : VPseudoBinaryM_VI;
+}
+
+multiclass VPseudoReductionV_VS {
+  foreach m = MxList.m in
+    defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>;
 }
 
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns.
 //===----------------------------------------------------------------------===//
+
+class VPatUnaryNoMask<string intrinsic_name,
+                      string inst,
+                      string kind,
+                      ValueType result_type,
+                      ValueType op2_type,
+                      int sew,
+                      LMULInfo vlmul,
+                      VReg op2_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
+                   (op2_type op2_reg_class:$rs2),
+                   (XLenVT GPR:$vl))),
+                   (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
+                   (op2_type op2_reg_class:$rs2),
+                   (NoX0 GPR:$vl), sew)>;
+
+class VPatUnaryMask<string intrinsic_name,
+                    string inst,
+                    string kind,
+                    ValueType result_type,
+                    ValueType op2_type,
+                    ValueType mask_type,
+                    int sew,
+                    LMULInfo vlmul,
+                    VReg result_reg_class,
+                    VReg op2_reg_class> :
+  Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
+                   (result_type result_reg_class:$merge),
+                   (op2_type op2_reg_class:$rs2),
+                   (mask_type V0),
+                   (XLenVT GPR:$vl))),
+                   (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
+                   (result_type result_reg_class:$merge),
+                   (op2_type op2_reg_class:$rs2),
+                   (mask_type V0), (NoX0 GPR:$vl), sew)>;
+
+class VPatMaskUnaryNoMask<string intrinsic_name,
+                          string inst,
+                          MTypeInfo mti> :
+  Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name)
+                (mti.Mask VR:$rs2),
+                (XLenVT GPR:$vl))),
+                (!cast<Instruction>(inst#"_M_"#mti.BX)
+                (mti.Mask VR:$rs2),
+                (NoX0 GPR:$vl), mti.SEW)>;
+
+class VPatMaskUnaryMask<string intrinsic_name,
+                        string inst,
+                        MTypeInfo mti> :
+  Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name#"_mask")
+                (mti.Mask VR:$merge),
+                (mti.Mask VR:$rs2),
+                (mti.Mask V0),
+                (XLenVT GPR:$vl))),
+                (!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK")
+                (mti.Mask VR:$merge),
+                (mti.Mask VR:$rs2),
+                (mti.Mask V0), (NoX0 GPR:$vl), mti.SEW)>;
+
 class VPatBinaryNoMask<string intrinsic_name,
                        string inst,
                        string kind,
@@ -1139,6 +1414,56 @@ multiclass VPatIStore<string intrinsic,
               (PseudoMask $rs3, $rs1, $rs2, (mask_type V0), (NoX0 GPR:$vl), sew)>;
 }
 
+multiclass VPatUnaryS_M<string intrinsic_name,
+                             string inst>
+{
+  foreach mti = AllMasks in {
+    def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name)
+                      (mti.Mask VR:$rs1), GPR:$vl)),
+                      (!cast<Instruction>(inst#"_M_"#mti.BX) $rs1,
+                      (NoX0 GPR:$vl), mti.SEW)>;
+    def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name # "_mask")
+                      (mti.Mask VR:$rs1), (mti.Mask V0), GPR:$vl)),
+                      (!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK") $rs1,
+                      (mti.Mask V0), (NoX0 GPR:$vl), mti.SEW)>;
+  }
+}
+
+multiclass VPatUnaryM_M<string intrinsic,
+                         string inst>
+{
+  foreach mti = AllMasks in {
+    def : VPatMaskUnaryNoMask<intrinsic, inst, mti>;
+    def : VPatMaskUnaryMask<intrinsic, inst, mti>;
+  }
+}
+
+multiclass VPatUnaryV_M<string intrinsic, string instruction>
+{
+  foreach vti = AllIntegerVectors in {
+    def : VPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
+                          vti.SEW, vti.LMul, VR>;
+    def : VPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
+                        vti.Mask, vti.SEW, vti.LMul, vti.RegClass, VR>;
+  }
+}
+
+multiclass VPatNullaryV<string intrinsic, string instruction>
+{
+  foreach vti = AllIntegerVectors in {
+    def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
+                          (XLenVT GPR:$vl))),
+                          (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX)
+                          (NoX0 GPR:$vl), vti.SEW)>;
+    def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask")
+                          (vti.Vector vti.RegClass:$merge),
+                          (vti.Mask V0), (XLenVT GPR:$vl))),
+                          (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_MASK")
+                          vti.RegClass:$merge, (vti.Mask V0),
+                          (NoX0 GPR:$vl), vti.SEW)>;
+  }
+}
+
 multiclass VPatBinary<string intrinsic,
                       string inst,
                       string kind,
@@ -1212,6 +1537,17 @@ multiclass VPatBinaryV_VV<string intrinsic, string instruction,
                       vti.RegClass, vti.RegClass>;
 }
 
+multiclass VPatBinaryV_VV_INT<string intrinsic, string instruction,
+                          list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in {
+    defvar ivti = GetIntVTypeInfo<vti>.Vti;
+    defm : VPatBinary<intrinsic, instruction, "VV",
+                      vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
+                      vti.SEW, vti.LMul, vti.RegClass,
+                      vti.RegClass, vti.RegClass>;
+  }
+}
+
 multiclass VPatBinaryV_VX<string intrinsic, string instruction,
                           list<VTypeInfo> vtilist> {
   foreach vti = vtilist in
@@ -1222,6 +1558,15 @@ multiclass VPatBinaryV_VX<string intrinsic, string instruction,
                       vti.RegClass, vti.ScalarRegClass>;
 }
 
+multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,
+                          list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in
+    defm : VPatBinary<intrinsic, instruction, "VX",
+                      vti.Vector, vti.Vector, XLenVT, vti.Mask,
+                      vti.SEW, vti.LMul, vti.RegClass,
+                      vti.RegClass, GPR>;
+}
+
 multiclass VPatBinaryV_VI<string intrinsic, string instruction,
                           list<VTypeInfo> vtilist, Operand imm_type> {
   foreach vti = vtilist in
@@ -1231,6 +1576,13 @@ multiclass VPatBinaryV_VI<string intrinsic, string instruction,
                       vti.RegClass, imm_type>;
 }
 
+multiclass VPatBinaryM_MM<string intrinsic, string instruction> {
+  foreach mti = AllMasks in
+    def : VPatBinaryNoMask<intrinsic, instruction, "MM",
+                           mti.Mask, mti.Mask, mti.Mask,
+                           mti.SEW, mti.LMul, VR, VR>;
+}
+
 multiclass VPatBinaryW_VV<string intrinsic, string instruction,
                           list<VTypeInfoToWide> vtilist> {
   foreach VtiToWti = vtilist in {
@@ -1319,30 +1671,33 @@ multiclass VPatBinaryV_WI<string intrinsic, string instruction,
 }
 
 multiclass VPatBinaryV_VM<string intrinsic, string instruction,
-                          bit CarryOut = 0> {
-  foreach vti = AllIntegerVectors in
+                          bit CarryOut = 0,
+                          list<VTypeInfo> vtilist = AllIntegerVectors> {
+  foreach vti = vtilist in
     defm : VPatBinaryCarryIn<intrinsic, instruction, "VVM",
-                             !if(!eq(CarryOut, 1), vti.Mask, vti.Vector),
+                             !if(CarryOut, vti.Mask, vti.Vector),
                              vti.Vector, vti.Vector, vti.Mask,
                              vti.SEW, vti.LMul,
                              vti.RegClass, vti.RegClass>;
 }
 
 multiclass VPatBinaryV_XM<string intrinsic, string instruction,
-                          bit CarryOut = 0> {
-  foreach vti = AllIntegerVectors in
-    defm : VPatBinaryCarryIn<intrinsic, instruction, "VXM",
-                             !if(!eq(CarryOut, 1), vti.Mask, vti.Vector),
-                             vti.Vector, XLenVT, vti.Mask,
+                          bit CarryOut = 0,
+                          list<VTypeInfo> vtilist = AllIntegerVectors> {
+  foreach vti = vtilist in
+    defm : VPatBinaryCarryIn<intrinsic, instruction,
+                             !if(!eq(vti.Scalar, XLenVT), "VXM", "VFM"),
+                             !if(CarryOut, vti.Mask, vti.Vector),
+                             vti.Vector, vti.Scalar, vti.Mask,
                              vti.SEW, vti.LMul,
-                             vti.RegClass, GPR>;
+                             vti.RegClass, vti.ScalarRegClass>;
 }
 
 multiclass VPatBinaryV_IM<string intrinsic, string instruction,
                           bit CarryOut = 0> {
   foreach vti = AllIntegerVectors in
     defm : VPatBinaryCarryIn<intrinsic, instruction, "VIM",
-                             !if(!eq(CarryOut, 1), vti.Mask, vti.Vector),
+                             !if(CarryOut, vti.Mask, vti.Vector),
                              vti.Vector, XLenVT, vti.Mask,
                              vti.SEW, vti.LMul,
                              vti.RegClass, simm5>;
@@ -1372,6 +1727,34 @@ multiclass VPatBinaryV_I<string intrinsic, string instruction> {
                              vti.RegClass, simm5>;
 }
 
+multiclass VPatBinaryM_VV<string intrinsic, string instruction,
+                          list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in
+    defm : VPatBinary<intrinsic, instruction, "VV",
+                      vti.Mask, vti.Vector, vti.Vector, vti.Mask,
+                      vti.SEW, vti.LMul, VR,
+                      vti.RegClass, vti.RegClass>;
+}
+
+multiclass VPatBinaryM_VX<string intrinsic, string instruction,
+                          list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in
+    defm : VPatBinary<intrinsic, instruction,
+                      !if(!eq(vti.Scalar, XLenVT), "VX", "VF"),
+                      vti.Mask, vti.Vector, vti.Scalar, vti.Mask,
+                      vti.SEW, vti.LMul, VR,
+                      vti.RegClass, vti.ScalarRegClass>;
+}
+
+multiclass VPatBinaryM_VI<string intrinsic, string instruction,
+                          list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in
+    defm : VPatBinary<intrinsic, instruction, "VI",
+                      vti.Mask, vti.Vector, XLenVT, vti.Mask,
+                      vti.SEW, vti.LMul, VR,
+                      vti.RegClass, simm5>;
+}
+
 multiclass VPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
                                 list<VTypeInfo> vtilist, Operand ImmType = simm5>
 {
@@ -1475,6 +1858,15 @@ multiclass VPatTernary<string intrinsic,
                         op2_kind>;
 }
 
+multiclass VPatTernaryV_VV<string intrinsic, string instruction,
+                           list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in
+    defm : VPatTernary<intrinsic, instruction, "VV",
+                       vti.Vector, vti.Vector, vti.Vector, vti.Mask,
+                       vti.SEW, vti.LMul, vti.RegClass,
+                       vti.RegClass, vti.RegClass>;
+}
+
 multiclass VPatTernaryV_VX<string intrinsic, string instruction,
                            list<VTypeInfo> vtilist> {
   foreach vti = vtilist in
@@ -1484,6 +1876,16 @@ multiclass VPatTernaryV_VX<string intrinsic, string instruction,
                        vti.RegClass, GPR>;
 }
 
+multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction,
+                           list<VTypeInfo> vtilist> {
+  foreach vti = vtilist in
+    defm : VPatTernary<intrinsic, instruction,
+                       !if(!eq(vti.Scalar, XLenVT), "VX", "VF"),
+                       vti.Vector, vti.Scalar, vti.Vector, vti.Mask,
+                       vti.SEW, vti.LMul, vti.RegClass,
+                       vti.ScalarRegClass, vti.RegClass>;
+}
+
 multiclass VPatTernaryV_VI<string intrinsic, string instruction,
                            list<VTypeInfo> vtilist, Operand Imm_type> {
   foreach vti = vtilist in
@@ -1493,12 +1895,115 @@ multiclass VPatTernaryV_VI<string intrinsic, string instruction,
                       vti.RegClass, Imm_type>;
 }
 
+multiclass VPatTernaryW_VV<string intrinsic, string instruction,
+                           list<VTypeInfoToWide> vtilist> {
+  foreach vtiToWti = vtilist in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    defm : VPatTernary<intrinsic, instruction, "VV",
+                      wti.Vector, vti.Vector, vti.Vector,
+                      vti.Mask, vti.SEW, vti.LMul,
+                      wti.RegClass, vti.RegClass, vti.RegClass>;
+  }
+}
+
+multiclass VPatTernaryW_VX<string intrinsic, string instruction,
+                           list<VTypeInfoToWide> vtilist> {
+  foreach vtiToWti = vtilist in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    defm : VPatTernary<intrinsic, instruction,
+                       !if(!eq(vti.Scalar, XLenVT), "VX", "VF"),
+                       wti.Vector, vti.Scalar, vti.Vector,
+                       vti.Mask, vti.SEW, vti.LMul,
+                       wti.RegClass, vti.ScalarRegClass, vti.RegClass>;
+  }
+}
+
+multiclass VPatTernaryV_VV_VX_AAXA<string intrinsic, string instruction,
+                              list<VTypeInfo> vtilist> {
+  defm "" : VPatTernaryV_VV<intrinsic, instruction, vtilist>;
+  defm "" : VPatTernaryV_VX_AAXA<intrinsic, instruction, vtilist>;
+}
+
 multiclass VPatTernaryV_VX_VI<string intrinsic, string instruction,
                               list<VTypeInfo> vtilist, Operand Imm_type = simm5> {
   defm "" : VPatTernaryV_VX<intrinsic, instruction, vtilist>;
   defm "" : VPatTernaryV_VI<intrinsic, instruction, vtilist, Imm_type>;
 }
 
+multiclass VPatBinaryM_VV_VX_VI<string intrinsic, string instruction,
+                                list<VTypeInfo> vtilist>
+{
+  defm "" : VPatBinaryM_VV<intrinsic, instruction, vtilist>;
+  defm "" : VPatBinaryM_VX<intrinsic, instruction, vtilist>;
+  defm "" : VPatBinaryM_VI<intrinsic, instruction, vtilist>;
+}
+
+multiclass VPatTernaryW_VV_VX<string intrinsic, string instruction,
+                              list<VTypeInfoToWide> vtilist> {
+  defm "" : VPatTernaryW_VV<intrinsic, instruction, vtilist>;
+  defm "" : VPatTernaryW_VX<intrinsic, instruction, vtilist>;
+}
+
+multiclass VPatBinaryM_VV_VX<string intrinsic, string instruction,
+                             list<VTypeInfo> vtilist>
+{
+  defm "" : VPatBinaryM_VV<intrinsic, instruction, vtilist>;
+  defm "" : VPatBinaryM_VX<intrinsic, instruction, vtilist>;
+}
+
+multiclass VPatBinaryM_VX_VI<string intrinsic, string instruction,
+                             list<VTypeInfo> vtilist>
+{
+  defm "" : VPatBinaryM_VX<intrinsic, instruction, vtilist>;
+  defm "" : VPatBinaryM_VI<intrinsic, instruction, vtilist>;
+}
+
+multiclass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction,
+                                    list<VTypeInfo> vtilist, Operand ImmType = simm5>
+{
+  defm "" : VPatBinaryV_VV_INT<intrinsic, instruction, vtilist>;
+  defm "" : VPatBinaryV_VX_INT<intrinsic, instruction, vtilist>;
+  defm "" : VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
+}
+
+multiclass VPatReductionV_VS<string intrinsic, string instruction, bit IsFloat = 0> {
+  foreach vti = !if(IsFloat, NoGroupFloatVectors, NoGroupIntegerVectors) in
+  {
+    defvar vectorM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # vti.SEW # "M1");
+    defm : VPatTernary<intrinsic, instruction, "VS",
+                       vectorM1.Vector, vti.Vector,
+                       vectorM1.Vector, vti.Mask,
+                       vti.SEW, vti.LMul,
+                       VR, vti.RegClass, VR>;
+  }
+  foreach gvti = !if(IsFloat, GroupFloatVectors, GroupIntegerVectors) in
+  {
+    defm : VPatTernary<intrinsic, instruction, "VS",
+                       gvti.VectorM1, gvti.Vector,
+                       gvti.VectorM1, gvti.Mask,
+                       gvti.SEW, gvti.LMul,
+                       VR, gvti.RegClass, VR>;
+  }
+}
+
+multiclass VPatReductionW_VS<string intrinsic, string instruction, bit IsFloat = 0> {
+  foreach vti = !if(IsFloat, AllFloatVectors, AllIntegerVectors) in
+  {
+    defvar wtiSEW = !mul(vti.SEW, 2);
+    if !le(wtiSEW, 64) then {
+      defvar wtiM1 = !cast<VTypeInfo>(!if(IsFloat, "VF", "VI") # wtiSEW # "M1");
+      defm : VPatTernary<intrinsic, instruction, "VS",
+                         wtiM1.Vector, vti.Vector,
+                         wtiM1.Vector, vti.Mask,
+                         vti.SEW, vti.LMul,
+                         wtiM1.RegClass, vti.RegClass,
+                         wtiM1.RegClass>;
+    }
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Pseudo instructions and patterns.
 //===----------------------------------------------------------------------===//
@@ -1560,6 +2065,16 @@ foreach eew = EEWList in {
   defm PseudoVSUXEI # eew : VPseudoIStore;
 }
 
+//===----------------------------------------------------------------------===//
+// 7.7. Unit-stride Fault-Only-First Loads
+//===----------------------------------------------------------------------===//
+
+// vleff may update VL register
+let hasSideEffects = 1, Defs = [VL] in
+foreach eew = EEWList in {
+  defm PseudoVLE # eew # FF : VPseudoUSLoad;
+}
+
 //===----------------------------------------------------------------------===//
 // Pseudo Instructions
 //===----------------------------------------------------------------------===//
@@ -1598,6 +2113,13 @@ defm PseudoVSBC        : VPseudoBinaryV_VM_XM;
 defm PseudoVMSBC       : VPseudoBinaryM_VM_XM<"@earlyclobber $rd">;
 defm PseudoVMSBC       : VPseudoBinaryM_V_X<"@earlyclobber $rd">;
 
+//===----------------------------------------------------------------------===//
+// 12.5. Vector Bitwise Logical Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVAND        : VPseudoBinaryV_VV_VX_VI;
+defm PseudoVOR         : VPseudoBinaryV_VV_VX_VI;
+defm PseudoVXOR        : VPseudoBinaryV_VV_VX_VI;
+
 //===----------------------------------------------------------------------===//
 // 12.6. Vector Single-Width Bit Shift Instructions
 //===----------------------------------------------------------------------===//
@@ -1611,6 +2133,18 @@ defm PseudoVSRA        : VPseudoBinaryV_VV_VX_VI<uimm5>;
 defm PseudoVNSRL       : VPseudoBinaryV_WV_WX_WI;
 defm PseudoVNSRA       : VPseudoBinaryV_WV_WX_WI;
 
+//===----------------------------------------------------------------------===//
+// 12.8. Vector Integer Comparison Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVMSEQ       : VPseudoBinaryM_VV_VX_VI;
+defm PseudoVMSNE       : VPseudoBinaryM_VV_VX_VI;
+defm PseudoVMSLTU      : VPseudoBinaryM_VV_VX;
+defm PseudoVMSLT       : VPseudoBinaryM_VV_VX;
+defm PseudoVMSLEU      : VPseudoBinaryM_VV_VX_VI;
+defm PseudoVMSLE       : VPseudoBinaryM_VV_VX_VI;
+defm PseudoVMSGTU      : VPseudoBinaryM_VX_VI;
+defm PseudoVMSGT       : VPseudoBinaryM_VX_VI;
+
 //===----------------------------------------------------------------------===//
 // 12.9. Vector Integer Min/Max Instructions
 //===----------------------------------------------------------------------===//
@@ -1642,6 +2176,27 @@ defm PseudoVWMUL       : VPseudoBinaryW_VV_VX;
 defm PseudoVWMULU      : VPseudoBinaryW_VV_VX;
 defm PseudoVWMULSU     : VPseudoBinaryW_VV_VX;
 
+//===----------------------------------------------------------------------===//
+// 12.13. Vector Single-Width Integer Multiply-Add Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVMACC       : VPseudoTernaryV_VV_VX_AAXA;
+defm PseudoVNMSAC      : VPseudoTernaryV_VV_VX_AAXA;
+defm PseudoVMADD       : VPseudoTernaryV_VV_VX_AAXA;
+defm PseudoVNMSUB      : VPseudoTernaryV_VV_VX_AAXA;
+
+//===----------------------------------------------------------------------===//
+// 12.14. Vector Widening Integer Multiply-Add Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVWMACCU     : VPseudoTernaryW_VV_VX;
+defm PseudoVWMACC      : VPseudoTernaryW_VV_VX;
+defm PseudoVWMACCSU    : VPseudoTernaryW_VV_VX;
+defm PseudoVWMACCUS    : VPseudoTernaryW_VX</*IsFloat*/false>;
+
+//===----------------------------------------------------------------------===//
+// 12.15. Vector Integer Merge Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVMERGE      : VPseudoBinaryV_VM_XM_IM;
+
 //===----------------------------------------------------------------------===//
 // 12.17. Vector Integer Move Instructions
 //===----------------------------------------------------------------------===//
@@ -1721,6 +2276,32 @@ defm PseudoVFRDIV      : VPseudoBinaryV_VX</*IsFloat=*/1>;
 //===----------------------------------------------------------------------===//
 defm PseudoVFWMUL      : VPseudoBinaryW_VV_VX</*IsFloat=*/1>;
 
+//===----------------------------------------------------------------------===//
+// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVFMACC      : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
+defm PseudoVFNMACC     : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
+defm PseudoVFMSAC      : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
+defm PseudoVFNMSAC     : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
+defm PseudoVFMADD      : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
+defm PseudoVFNMADD     : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
+defm PseudoVFMSUB      : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
+defm PseudoVFNMSUB     : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
+
+//===----------------------------------------------------------------------===//
+// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVFWMACC     : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
+defm PseudoVFWNMACC    : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
+defm PseudoVFWMSAC     : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
+defm PseudoVFWNMSAC    : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
+
+//===----------------------------------------------------------------------===//
+// 14.9. Vector Floating-Point Min/Max Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVFMIN       : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
+defm PseudoVFMAX       : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
+
 //===----------------------------------------------------------------------===//
 // 14.12. Vector Floating-Point Sign-Injection Instructions
 //===----------------------------------------------------------------------===//
@@ -1728,8 +2309,122 @@ defm PseudoVFSGNJ      : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
 defm PseudoVFSGNJN     : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
 defm PseudoVFSGNJX     : VPseudoBinaryV_VV_VX</*IsFloat=*/1>;
 
+//===----------------------------------------------------------------------===//
+// 14.13. Vector Floating-Point Compare Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVMFEQ       : VPseudoBinaryM_VV_VX</*IsFloat=*/1>;
+defm PseudoVMFNE       : VPseudoBinaryM_VV_VX</*IsFloat=*/1>;
+defm PseudoVMFLT       : VPseudoBinaryM_VV_VX</*IsFloat=*/1>;
+defm PseudoVMFLE       : VPseudoBinaryM_VV_VX</*IsFloat=*/1>;
+defm PseudoVMFGT       : VPseudoBinaryM_VX</*IsFloat=*/1>;
+defm PseudoVMFGE       : VPseudoBinaryM_VX</*IsFloat=*/1>;
+
+//===----------------------------------------------------------------------===//
+// 14.14. Vector Floating-Point Move Instruction
+//===----------------------------------------------------------------------===//
+defm PseudoVFMV_V      : VPseudoUnaryV_F_NoDummyMask;
+
+//===----------------------------------------------------------------------===//
+// 14.15. Vector Floating-Point Merge Instruction
+//===----------------------------------------------------------------------===//
+defm PseudoVFMERGE     : VPseudoBinaryV_XM</*CarryOut =*/0,/*CarryIn =*/true,
+                                           /*Constraint =*/"", /*IsFloat=*/true>;
 } // Predicates = [HasStdExtV, HasStdExtF]
 
+let Predicates = [HasStdExtV] in {
+//===----------------------------------------------------------------------===//
+// 15.1. Vector Single-Width Integer Reduction Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVREDSUM     : VPseudoReductionV_VS;
+defm PseudoVREDAND     : VPseudoReductionV_VS;
+defm PseudoVREDOR      : VPseudoReductionV_VS;
+defm PseudoVREDXOR     : VPseudoReductionV_VS;
+defm PseudoVREDMINU    : VPseudoReductionV_VS;
+defm PseudoVREDMIN     : VPseudoReductionV_VS;
+defm PseudoVREDMAXU    : VPseudoReductionV_VS;
+defm PseudoVREDMAX     : VPseudoReductionV_VS;
+
+//===----------------------------------------------------------------------===//
+// 15.2. Vector Widening Integer Reduction Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVWREDSUMU   : VPseudoReductionV_VS;
+defm PseudoVWREDSUM    : VPseudoReductionV_VS;
+} // Predicates = [HasStdExtV]
+
+let Predicates = [HasStdExtV, HasStdExtF] in {
+//===----------------------------------------------------------------------===//
+// 15.3. Vector Single-Width Floating-Point Reduction Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVFREDOSUM   : VPseudoReductionV_VS;
+defm PseudoVFREDSUM    : VPseudoReductionV_VS;
+defm PseudoVFREDMIN    : VPseudoReductionV_VS;
+defm PseudoVFREDMAX    : VPseudoReductionV_VS;
+
+//===----------------------------------------------------------------------===//
+// 15.4. Vector Widening Floating-Point Reduction Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVFWREDSUM   : VPseudoReductionV_VS;
+defm PseudoVFWREDOSUM  : VPseudoReductionV_VS;
+} // Predicates = [HasStdExtV, HasStdExtF]
+
+//===----------------------------------------------------------------------===//
+// 16. Vector Mask Instructions
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// 16.1 Vector Mask-Register Logical Instructions
+//===----------------------------------------------------------------------===//
+
+defm PseudoVMAND: VPseudoBinaryM_MM;
+defm PseudoVMNAND: VPseudoBinaryM_MM;
+defm PseudoVMANDNOT: VPseudoBinaryM_MM;
+defm PseudoVMXOR: VPseudoBinaryM_MM;
+defm PseudoVMOR: VPseudoBinaryM_MM;
+defm PseudoVMNOR: VPseudoBinaryM_MM;
+defm PseudoVMORNOT: VPseudoBinaryM_MM;
+defm PseudoVMXNOR: VPseudoBinaryM_MM;
+
+//===----------------------------------------------------------------------===//
+// 16.2. Vector mask population count vpopc
+//===----------------------------------------------------------------------===//
+
+defm PseudoVPOPC: VPseudoUnaryS_M;
+
+//===----------------------------------------------------------------------===//
+// 16.3. vfirst find-first-set mask bit
+//===----------------------------------------------------------------------===//
+
+defm PseudoVFIRST: VPseudoUnaryS_M;
+
+//===----------------------------------------------------------------------===//
+// 16.4. vmsbf.m set-before-first mask bit
+//===----------------------------------------------------------------------===//
+defm PseudoVMSBF: VPseudoUnaryM_M;
+
+//===----------------------------------------------------------------------===//
+// 16.5. vmsif.m set-including-first mask bit
+//===----------------------------------------------------------------------===//
+defm PseudoVMSIF: VPseudoUnaryM_M;
+
+//===----------------------------------------------------------------------===//
+// 16.6. vmsof.m set-only-first mask bit
+//===----------------------------------------------------------------------===//
+defm PseudoVMSOF: VPseudoUnaryM_M;
+
+//===----------------------------------------------------------------------===//
+// 16.8.  Vector Iota Instruction
+//===----------------------------------------------------------------------===//
+defm PseudoVIOTA_M: VPseudoUnaryV_M;
+
+//===----------------------------------------------------------------------===//
+// 16.9. Vector Element Index Instruction
+//===----------------------------------------------------------------------===//
+defm PseudoVID : VPseudoMaskNullaryV;
+
+//===----------------------------------------------------------------------===//
+// 17. Vector Permutation Instructions
+//===----------------------------------------------------------------------===//
+
 //===----------------------------------------------------------------------===//
 // 17.1. Integer Scalar Move Instructions
 //===----------------------------------------------------------------------===//
@@ -1782,23 +2477,28 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0, usesCustomInserter = 1,
 //===----------------------------------------------------------------------===//
 // 17.3. Vector Slide Instructions
 //===----------------------------------------------------------------------===//
-defm PseudoVSLIDEUP    : VPseudoTernaryV_VX_VI<uimm5, "@earlyclobber $rd">;
-defm PseudoVSLIDEDOWN  : VPseudoTernaryV_VX_VI<uimm5>;
+let Predicates = [HasStdExtV] in {
+  defm PseudoVSLIDEUP    : VPseudoTernaryV_VX_VI<uimm5, "@earlyclobber $rd">;
+  defm PseudoVSLIDEDOWN  : VPseudoTernaryV_VX_VI<uimm5>;
+  defm PseudoVSLIDE1UP   : VPseudoBinaryV_VX</*IsFloat*/false, "@earlyclobber $rd">;
+  defm PseudoVSLIDE1DOWN : VPseudoBinaryV_VX</*IsFloat*/false>;
+} // Predicates = [HasStdExtV]
+
+let Predicates = [HasStdExtV, HasStdExtF] in {
+  defm PseudoVFSLIDE1UP  : VPseudoBinaryV_VX</*IsFloat*/true, "@earlyclobber $rd">;
+  defm PseudoVFSLIDE1DOWN : VPseudoBinaryV_VX</*IsFloat*/true>;
+} // Predicates = [HasStdExtV, HasStdExtF]
+
+//===----------------------------------------------------------------------===//
+// 17.4. Vector Register Gather Instructions
+//===----------------------------------------------------------------------===//
+defm PseudoVRGATHER    : VPseudoBinaryV_VV_VX_VI<uimm5, "@earlyclobber $rd">;
 
 //===----------------------------------------------------------------------===//
 // Patterns.
 //===----------------------------------------------------------------------===//
 let Predicates = [HasStdExtV] in {
 
-// Whole-register vector patterns.
-
-// 7.4. Vector Unit-Stride Instructions
-defm "" : VPatUSLoadStoreSDNodes<GPR>;
-defm "" : VPatUSLoadStoreSDNodes<AddrFI>;
-
-// 12.1. Vector Single-Width Integer Add and Subtract
-defm "" : VPatBinarySDNode<add, "PseudoVADD">;
-
 //===----------------------------------------------------------------------===//
 // 7. Vector Loads and Stores
 //===----------------------------------------------------------------------===//
@@ -1812,6 +2512,9 @@ foreach vti = AllVectors in
   defm : VPatUSLoad<"int_riscv_vle",
                     "PseudoVLE" # vti.SEW,
                     vti.Vector, vti.Mask, vti.SEW, vti.LMul, vti.RegClass>;
+  defm : VPatUSLoad<"int_riscv_vleff",
+                    "PseudoVLE" # vti.SEW # "FF",
+                    vti.Vector, vti.Mask, vti.SEW, vti.LMul, vti.RegClass>;
   defm : VPatUSStore<"int_riscv_vse",
                      "PseudoVSE" # vti.SEW,
                      vti.Vector, vti.Mask, vti.SEW, vti.LMul, vti.RegClass>;
@@ -1914,6 +2617,13 @@ defm "" : VPatBinaryV_VM_XM<"int_riscv_vsbc", "PseudoVSBC">;
 defm "" : VPatBinaryM_VM_XM<"int_riscv_vmsbc_borrow_in", "PseudoVMSBC">;
 defm "" : VPatBinaryM_V_X<"int_riscv_vmsbc", "PseudoVMSBC">;
 
+//===----------------------------------------------------------------------===//
+// 12.5. Vector Bitwise Logical Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vand", "PseudoVAND", AllIntegerVectors>;
+defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vor", "PseudoVOR", AllIntegerVectors>;
+defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vxor", "PseudoVXOR", AllIntegerVectors>;
+
 //===----------------------------------------------------------------------===//
 // 12.6. Vector Single-Width Bit Shift Instructions
 //===----------------------------------------------------------------------===//
@@ -1930,6 +2640,19 @@ defm "" : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors
 defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsrl", "PseudoVNSRL", AllWidenableIntVectors>;
 defm "" : VPatBinaryV_WV_WX_WI<"int_riscv_vnsra", "PseudoVNSRA", AllWidenableIntVectors>;
 
+//===----------------------------------------------------------------------===//
+// 12.8. Vector Integer Comparison Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatBinaryM_VV_VX_VI<"int_riscv_vmseq", "PseudoVMSEQ", AllIntegerVectors>;
+defm "" : VPatBinaryM_VV_VX_VI<"int_riscv_vmsne", "PseudoVMSNE", AllIntegerVectors>;
+defm "" : VPatBinaryM_VV_VX<"int_riscv_vmsltu", "PseudoVMSLTU", AllIntegerVectors>;
+defm "" : VPatBinaryM_VV_VX<"int_riscv_vmslt", "PseudoVMSLT", AllIntegerVectors>;
+defm "" : VPatBinaryM_VV_VX_VI<"int_riscv_vmsleu", "PseudoVMSLEU", AllIntegerVectors>;
+defm "" : VPatBinaryM_VV_VX_VI<"int_riscv_vmsle", "PseudoVMSLE", AllIntegerVectors>;
+
+defm "" : VPatBinaryM_VX_VI<"int_riscv_vmsgtu", "PseudoVMSGTU", AllIntegerVectors>;
+defm "" : VPatBinaryM_VX_VI<"int_riscv_vmsgt", "PseudoVMSGT", AllIntegerVectors>;
+
 //===----------------------------------------------------------------------===//
 // 12.9. Vector Integer Min/Max Instructions
 //===----------------------------------------------------------------------===//
@@ -1961,6 +2684,27 @@ defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmul", "PseudoVWMUL", AllWidenableIntVec
 defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulu", "PseudoVWMULU", AllWidenableIntVectors>;
 defm "" : VPatBinaryW_VV_VX<"int_riscv_vwmulsu", "PseudoVWMULSU", AllWidenableIntVectors>;
 
+//===----------------------------------------------------------------------===//
+// 12.13. Vector Single-Width Integer Multiply-Add Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vmadd", "PseudoVMADD", AllIntegerVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vnmsub", "PseudoVNMSUB", AllIntegerVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vmacc", "PseudoVMACC", AllIntegerVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vnmsac", "PseudoVNMSAC", AllIntegerVectors>;
+
+//===----------------------------------------------------------------------===//
+// 12.14. Vector Widening Integer Multiply-Add Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatTernaryW_VV_VX<"int_riscv_vwmaccu", "PseudoVWMACCU", AllWidenableIntVectors>;
+defm "" : VPatTernaryW_VV_VX<"int_riscv_vwmacc", "PseudoVWMACC", AllWidenableIntVectors>;
+defm "" : VPatTernaryW_VV_VX<"int_riscv_vwmaccsu", "PseudoVWMACCSU", AllWidenableIntVectors>;
+defm "" : VPatTernaryW_VX<"int_riscv_vwmaccus", "PseudoVWMACCUS", AllWidenableIntVectors>;
+
+//===----------------------------------------------------------------------===//
+// 12.15. Vector Integer Merge Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">;
+
 //===----------------------------------------------------------------------===//
 // 12.17. Vector Integer Move Instructions
 //===----------------------------------------------------------------------===//
@@ -2045,6 +2789,32 @@ defm "" : VPatBinaryV_VX<"int_riscv_vfrdiv", "PseudoVFRDIV", AllFloatVectors>;
 //===----------------------------------------------------------------------===//
 defm "" : VPatBinaryW_VV_VX<"int_riscv_vfwmul", "PseudoVFWMUL", AllWidenableFloatVectors>;
 
+//===----------------------------------------------------------------------===//
+// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmacc", "PseudoVFMACC", AllFloatVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmacc", "PseudoVFNMACC", AllFloatVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmsac", "PseudoVFMSAC", AllFloatVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsac", "PseudoVFNMSAC", AllFloatVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmadd", "PseudoVFMADD", AllFloatVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmadd", "PseudoVFNMADD", AllFloatVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmsub", "PseudoVFMSUB", AllFloatVectors>;
+defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsub", "PseudoVFNMSUB", AllFloatVectors>;
+
+//===----------------------------------------------------------------------===//
+// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwmacc", "PseudoVFWMACC", AllWidenableFloatVectors>;
+defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmacc", "PseudoVFWNMACC", AllWidenableFloatVectors>;
+defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwmsac", "PseudoVFWMSAC", AllWidenableFloatVectors>;
+defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors>;
+
+//===----------------------------------------------------------------------===//
+// 14.9. Vector Floating-Point Min/Max Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmin", "PseudoVFMIN", AllFloatVectors>;
+defm "" : VPatBinaryV_VV_VX<"int_riscv_vfmax", "PseudoVFMAX", AllFloatVectors>;
+
 //===----------------------------------------------------------------------===//
 // 14.12. Vector Floating-Point Sign-Injection Instructions
 //===----------------------------------------------------------------------===//
@@ -2052,8 +2822,134 @@ defm "" : VPatBinaryV_VV_VX<"int_riscv_vfsgnj", "PseudoVFSGNJ", AllFloatVectors>
 defm "" : VPatBinaryV_VV_VX<"int_riscv_vfsgnjn", "PseudoVFSGNJN", AllFloatVectors>;
 defm "" : VPatBinaryV_VV_VX<"int_riscv_vfsgnjx", "PseudoVFSGNJX", AllFloatVectors>;
 
+//===----------------------------------------------------------------------===//
+// 14.13. Vector Floating-Point Compare Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatBinaryM_VV_VX<"int_riscv_vmfeq", "PseudoVMFEQ", AllFloatVectors>;
+defm "" : VPatBinaryM_VV_VX<"int_riscv_vmfle", "PseudoVMFLE", AllFloatVectors>;
+defm "" : VPatBinaryM_VV_VX<"int_riscv_vmflt", "PseudoVMFLT", AllFloatVectors>;
+defm "" : VPatBinaryM_VV_VX<"int_riscv_vmfne", "PseudoVMFNE", AllFloatVectors>;
+defm "" : VPatBinaryM_VX<"int_riscv_vmfgt", "PseudoVMFGT", AllFloatVectors>;
+defm "" : VPatBinaryM_VX<"int_riscv_vmfge", "PseudoVMFGE", AllFloatVectors>;
+
+//===----------------------------------------------------------------------===//
+// 14.14. Vector Floating-Point Move Instruction
+//===----------------------------------------------------------------------===//
+foreach fvti = AllFloatVectors in {
+  // If we're splatting fpimm0, use vmv.v.x vd, x0.
+  def : Pat<(fvti.Vector (int_riscv_vfmv_v_f
+                         (fvti.Scalar (fpimm0)), GPR:$vl)),
+            (!cast<Instruction>("PseudoVMV_V_X_"#fvti.LMul.MX)
+             X0, (NoX0 GPR:$vl), fvti.SEW)>;
+
+  def : Pat<(fvti.Vector (int_riscv_vfmv_v_f
+                         (fvti.Scalar fvti.ScalarRegClass:$rs2), GPR:$vl)),
+            (!cast<Instruction>("PseudoVFMV_V_F_"#fvti.LMul.MX)
+             ToFPR32<fvti.Scalar, fvti.ScalarRegClass, "rs2">.ret,
+             (NoX0 GPR:$vl), fvti.SEW)>;
+}
+
+//===----------------------------------------------------------------------===//
+// 14.15. Vector Floating-Point Merge Instruction
+//===----------------------------------------------------------------------===//
+// We can use vmerge.vvm to support vector-vector vfmerge.
+defm "" : VPatBinaryV_VM<"int_riscv_vfmerge", "PseudoVMERGE",
+                         /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
+defm "" : VPatBinaryV_XM<"int_riscv_vfmerge", "PseudoVFMERGE",
+                         /*CarryOut = */0, /*vtilist=*/AllFloatVectors>;
+
 } // Predicates = [HasStdExtV, HasStdExtF]
 
+let Predicates = [HasStdExtV] in {
+//===----------------------------------------------------------------------===//
+// 15.1. Vector Single-Width Integer Reduction Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatReductionV_VS<"int_riscv_vredsum", "PseudoVREDSUM">;
+defm "" : VPatReductionV_VS<"int_riscv_vredand", "PseudoVREDAND">;
+defm "" : VPatReductionV_VS<"int_riscv_vredor", "PseudoVREDOR">;
+defm "" : VPatReductionV_VS<"int_riscv_vredxor", "PseudoVREDXOR">;
+defm "" : VPatReductionV_VS<"int_riscv_vredminu", "PseudoVREDMINU">;
+defm "" : VPatReductionV_VS<"int_riscv_vredmin", "PseudoVREDMIN">;
+defm "" : VPatReductionV_VS<"int_riscv_vredmaxu", "PseudoVREDMAXU">;
+defm "" : VPatReductionV_VS<"int_riscv_vredmax", "PseudoVREDMAX">;
+
+//===----------------------------------------------------------------------===//
+// 15.2. Vector Widening Integer Reduction Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatReductionW_VS<"int_riscv_vwredsumu", "PseudoVWREDSUMU">;
+defm "" : VPatReductionW_VS<"int_riscv_vwredsum", "PseudoVWREDSUM">;
+} // Predicates = [HasStdExtV]
+
+let Predicates = [HasStdExtV, HasStdExtF] in {
+//===----------------------------------------------------------------------===//
+// 15.3. Vector Single-Width Floating-Point Reduction Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatReductionV_VS<"int_riscv_vfredosum", "PseudoVFREDOSUM", /*IsFloat=*/1>;
+defm "" : VPatReductionV_VS<"int_riscv_vfredsum", "PseudoVFREDSUM", /*IsFloat=*/1>;
+defm "" : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", /*IsFloat=*/1>;
+defm "" : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", /*IsFloat=*/1>;
+
+//===----------------------------------------------------------------------===//
+// 15.4. Vector Widening Floating-Point Reduction Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatReductionW_VS<"int_riscv_vfwredsum", "PseudoVFWREDSUM", /*IsFloat=*/1>;
+defm "" : VPatReductionW_VS<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", /*IsFloat=*/1>;
+} // Predicates = [HasStdExtV, HasStdExtF]
+
+//===----------------------------------------------------------------------===//
+// 16. Vector Mask Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtV] in {
+//===----------------------------------------------------------------------===//
+// 16.1 Vector Mask-Register Logical Instructions
+//===----------------------------------------------------------------------===//
+defm "" : VPatBinaryM_MM<"int_riscv_vmand", "PseudoVMAND">;
+defm "" : VPatBinaryM_MM<"int_riscv_vmnand", "PseudoVMNAND">;
+defm "" : VPatBinaryM_MM<"int_riscv_vmandnot", "PseudoVMANDNOT">;
+defm "" : VPatBinaryM_MM<"int_riscv_vmxor", "PseudoVMXOR">;
+defm "" : VPatBinaryM_MM<"int_riscv_vmor", "PseudoVMOR">;
+defm "" : VPatBinaryM_MM<"int_riscv_vmnor", "PseudoVMNOR">;
+defm "" : VPatBinaryM_MM<"int_riscv_vmornot", "PseudoVMORNOT">;
+defm "" : VPatBinaryM_MM<"int_riscv_vmxnor", "PseudoVMXNOR">;
+
+//===----------------------------------------------------------------------===//
+// 16.2. Vector mask population count vpopc
+//===----------------------------------------------------------------------===//
+defm "" : VPatUnaryS_M<"int_riscv_vpopc", "PseudoVPOPC">;
+
+//===----------------------------------------------------------------------===//
+// 16.3. vfirst find-first-set mask bit
+//===----------------------------------------------------------------------===//
+defm "" : VPatUnaryS_M<"int_riscv_vfirst", "PseudoVFIRST">;
+
+//===----------------------------------------------------------------------===//
+// 16.4. vmsbf.m set-before-first mask bit
+//===----------------------------------------------------------------------===//
+defm "" : VPatUnaryM_M<"int_riscv_vmsbf", "PseudoVMSBF">;
+
+//===----------------------------------------------------------------------===//
+// 16.5. vmsif.m set-including-first mask bit
+//===----------------------------------------------------------------------===//
+defm "" : VPatUnaryM_M<"int_riscv_vmsif", "PseudoVMSIF">;
+
+//===----------------------------------------------------------------------===//
+// 16.6. vmsof.m set-only-first mask bit
+//===----------------------------------------------------------------------===//
+defm "" : VPatUnaryM_M<"int_riscv_vmsof", "PseudoVMSOF">;
+
+//===----------------------------------------------------------------------===//
+// 16.8.  Vector Iota Instruction
+//===----------------------------------------------------------------------===//
+defm "" : VPatUnaryV_M<"int_riscv_viota", "PseudoVIOTA">;
+
+//===----------------------------------------------------------------------===//
+// 16.9. Vector Element Index Instruction
+//===----------------------------------------------------------------------===//
+defm "" : VPatNullaryV<"int_riscv_vid", "PseudoVID">;
+
+} // Predicates = [HasStdExtV]
+
 //===----------------------------------------------------------------------===//
 // 17. Vector Permutation Instructions
 //===----------------------------------------------------------------------===//
@@ -2110,9 +3006,29 @@ foreach fvti = AllFloatVectors in {
 let Predicates = [HasStdExtV] in {
   defm "" : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllIntegerVectors, uimm5>;
   defm "" : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllIntegerVectors, uimm5>;
+  defm "" : VPatBinaryV_VX<"int_riscv_vslide1up", "PseudoVSLIDE1UP", AllIntegerVectors>;
+  defm "" : VPatBinaryV_VX<"int_riscv_vslide1down", "PseudoVSLIDE1DOWN", AllIntegerVectors>;
 } // Predicates = [HasStdExtV]
 
 let Predicates = [HasStdExtV, HasStdExtF] in {
   defm "" : VPatTernaryV_VX_VI<"int_riscv_vslideup", "PseudoVSLIDEUP", AllFloatVectors, uimm5>;
   defm "" : VPatTernaryV_VX_VI<"int_riscv_vslidedown", "PseudoVSLIDEDOWN", AllFloatVectors, uimm5>;
+  defm "" : VPatBinaryV_VX<"int_riscv_vfslide1up", "PseudoVFSLIDE1UP", AllFloatVectors>;
+  defm "" : VPatBinaryV_VX<"int_riscv_vfslide1down", "PseudoVFSLIDE1DOWN", AllFloatVectors>;
+} // Predicates = [HasStdExtV, HasStdExtF]
+
+//===----------------------------------------------------------------------===//
+// 17.4. Vector Register Gather Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasStdExtV] in {
+  defm "" : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
+                                     AllIntegerVectors, uimm5>;
+} // Predicates = [HasStdExtV]
+
+let Predicates = [HasStdExtV, HasStdExtF] in {
+  defm "" : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
+                                     AllFloatVectors, uimm5>;
 } // Predicates = [HasStdExtV, HasStdExtF]
+
+// Include the non-intrinsic ISel patterns
+include "RISCVInstrInfoVSDPatterns.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
new file mode 100644
index 0000000000000..b8c78451b287e
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -0,0 +1,166 @@
+//===- RISCVInstrInfoVSDPatterns.td - RVV SDNode patterns --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file contains the required infrastructure and SDNode patterns to
+/// support code generation for the standard 'V' (Vector) extension, version
+/// 0.9.  This version is still experimental as the 'V' extension hasn't been
+/// ratified yet.
+///
+/// This file is included from and depends upon RISCVInstrInfoVPseudos.td
+///
+/// Note: the patterns for RVV intrinsics are found in
+/// RISCVInstrInfoVPseudos.td.
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Helpers to define the SDNode patterns.
+//===----------------------------------------------------------------------===//
+
+def SDTSplatI64 : SDTypeProfile<1, 1, [
+  SDTCVecEltisVT<0, i64>, SDTCisVT<1, i32>
+]>;
+
+def rv32_splat_i64 : SDNode<"RISCVISD::SPLAT_VECTOR_I64", SDTSplatI64>;
+
+// Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants
+// precedence
+def SplatPat       : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;
+
+def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>;
+def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
+
+multiclass VPatUSLoadStoreSDNode<LLVMType type,
+                                 LLVMType mask_type,
+                                 int sew,
+                                 LMULInfo vlmul,
+                                 RegisterClass reg_rs1,
+                                 VReg reg_class>
+{
+  defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);
+  defvar store_instr = !cast<Instruction>("PseudoVSE"#sew#"_V_"#vlmul.MX);
+  // Load
+  def : Pat<(type (load reg_rs1:$rs1)),
+            (load_instr reg_rs1:$rs1, VLMax, sew)>;
+  // Store
+  def : Pat<(store type:$rs2, reg_rs1:$rs1),
+            (store_instr reg_class:$rs2, reg_rs1:$rs1, VLMax, sew)>;
+}
+
+multiclass VPatUSLoadStoreSDNodes<RegisterClass reg_rs1> {
+  foreach vti = AllVectors in
+    defm "" : VPatUSLoadStoreSDNode<vti.Vector, vti.Mask, vti.SEW, vti.LMul,
+                                    reg_rs1, vti.RegClass>;
+}
+
+class VPatBinarySDNode_VV<SDNode vop,
+                          string instruction_name,
+                          ValueType result_type,
+                          ValueType op_type,
+                          ValueType mask_type,
+                          int sew,
+                          LMULInfo vlmul,
+                          VReg RetClass,
+                          VReg op_reg_class> :
+    Pat<(result_type (vop
+                     (op_type op_reg_class:$rs1),
+                     (op_type op_reg_class:$rs2))),
+        (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
+                     op_reg_class:$rs1,
+                     op_reg_class:$rs2,
+                     VLMax, sew)>;
+
+class VPatBinarySDNode_XI<SDNode vop,
+                          string instruction_name,
+                          string suffix,
+                          ValueType result_type,
+                          ValueType vop_type,
+                          ValueType xop_type,
+                          ValueType mask_type,
+                          int sew,
+                          LMULInfo vlmul,
+                          VReg RetClass,
+                          VReg vop_reg_class,
+                          ComplexPattern SplatPatKind,
+                          DAGOperand xop_kind> :
+    Pat<(result_type (vop
+                     (vop_type vop_reg_class:$rs1),
+                     (vop_type (SplatPatKind xop_kind:$rs2)))),
+        (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX)
+                     vop_reg_class:$rs1,
+                     xop_kind:$rs2,
+                     VLMax, sew)>;
+
+multiclass VPatBinarySDNode_VV_VX_VI<SDNode vop, string instruction_name,
+                                     Operand ImmType = simm5>
+{
+  foreach vti = AllIntegerVectors in {
+    def : VPatBinarySDNode_VV<vop, instruction_name,
+                              vti.Vector, vti.Vector, vti.Mask, vti.SEW,
+                              vti.LMul, vti.RegClass, vti.RegClass>;
+    def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
+                              vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
+                              vti.LMul, vti.RegClass, vti.RegClass,
+                              SplatPat, GPR>;
+    def : VPatBinarySDNode_XI<vop, instruction_name, "VI",
+                              vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
+                              vti.LMul, vti.RegClass, vti.RegClass,
+                              !cast<ComplexPattern>(SplatPat#_#ImmType),
+                              ImmType>;
+  }
+}
+
+//===----------------------------------------------------------------------===//
+// Patterns.
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtV] in {
+
+// 7.4. Vector Unit-Stride Instructions
+defm "" : VPatUSLoadStoreSDNodes<GPR>;
+defm "" : VPatUSLoadStoreSDNodes<AddrFI>;
+
+// 12.1. Vector Single-Width Integer Add and Subtract
+defm "" : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
+
+// 12.5. Vector Bitwise Logical Instructions
+defm "" : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
+
+// 12.6. Vector Single-Width Bit Shift Instructions
+defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
+defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
+
+} // Predicates = [HasStdExtV]
+
+//===----------------------------------------------------------------------===//
+// Vector Splats
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtV] in {
+foreach vti = AllIntegerVectors in {
+  def : Pat<(vti.Vector (splat_vector GPR:$rs1)),
+            (!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
+              GPR:$rs1, VLMax, vti.SEW)>;
+  def : Pat<(vti.Vector (splat_vector simm5:$rs1)),
+            (!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
+              simm5:$rs1, VLMax, vti.SEW)>;
+}
+} // Predicates = [HasStdExtV]
+
+let Predicates = [HasStdExtV, IsRV32] in {
+foreach vti = AllIntegerVectors in {
+  if !eq(vti.SEW, 64) then {
+    def : Pat<(vti.Vector (rv32_splat_i64 GPR:$rs1)),
+              (!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
+                GPR:$rs1, VLMax, vti.SEW)>;
+    def : Pat<(vti.Vector (rv32_splat_i64 simm5:$rs1)),
+              (!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
+                simm5:$rs1, VLMax, vti.SEW)>;
+  }
+}
+} // Predicates = [HasStdExtV, IsRV32]
diff --git a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
index 4fd060a650140..a93a1e38c6569 100644
--- a/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
@@ -122,6 +122,9 @@ bool llvm::LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
   case MachineOperand::MO_ConstantPoolIndex:
     MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
     break;
+  case MachineOperand::MO_JumpTableIndex:
+    MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
+    break;
   }
   return true;
 }
diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
index b610661a3a846..4cd32b29b04d6 100644
--- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -48,59 +48,15 @@ enum {
   InstFormatMask = 31,
 
   ConstraintOffset = 5,
-  ConstraintMask = 0b1111
+  ConstraintMask = 0b111
 };
 
 // Match with the definitions in RISCVInstrFormatsV.td
 enum RVVConstraintType {
   NoConstraint = 0,
-  VS2Constraint = 0b0001,
-  VS1Constraint = 0b0010,
-  VMConstraint = 0b0100,
-  OneInput = 0b1000,
-
-  // Illegal instructions:
-  //
-  // * The destination vector register group for a masked vector instruction
-  // cannot overlap the source mask register (v0), unless the destination vector
-  // register is being written with a mask value (e.g., comparisons) or the
-  // scalar result of a reduction.
-  //
-  // * Widening: The destination vector register group cannot overlap a source
-  // vector register group of a different EEW
-  //
-  // * Narrowing: The destination vector register group cannot overlap the
-  // first source vector register group
-  //
-  // * For vadc and vsbc, an illegal instruction exception is raised if the
-  // destination vector register is v0.
-  //
-  // * For vmadc and vmsbc, an illegal instruction exception is raised if the
-  // destination vector register overlaps a source vector register group.
-  //
-  // * viota: An illegal instruction exception is raised if the destination
-  // vector register group overlaps the source vector mask register. If the
-  // instruction is masked, an illegal instruction exception is issued if the
-  // destination vector register group overlaps v0.
-  //
-  // * v[f]slide[1]up: The destination vector register group for vslideup cannot
-  // overlap the source vector register group.
-  //
-  // * vrgather: The destination vector register group cannot overlap with the
-  // source vector register groups.
-  //
-  // * vcompress: The destination vector register group cannot overlap the
-  // source vector register group or the source mask register
-  WidenV = VS2Constraint | VS1Constraint | VMConstraint,
-  WidenW = VS1Constraint | VMConstraint,
-  WidenCvt = VS2Constraint | VMConstraint | OneInput,
-  Narrow = VS2Constraint | VMConstraint,
-  NarrowCvt = VS2Constraint | VMConstraint | OneInput,
-  Vmadc = VS2Constraint | VS1Constraint,
-  Iota = VS2Constraint | VMConstraint | OneInput,
-  SlideUp = VS2Constraint | VMConstraint,
-  Vrgather = VS2Constraint | VS1Constraint | VMConstraint,
-  Vcompress = VS2Constraint | VS1Constraint,
+  VS2Constraint = 0b001,
+  VS1Constraint = 0b010,
+  VMConstraint = 0b100,
 };
 
 // RISC-V Specific Machine Operand Flags
diff --git a/llvm/lib/Target/VE/VECallingConv.td b/llvm/lib/Target/VE/VECallingConv.td
index 6741d1cc8eaf2..93899c2cae3d1 100644
--- a/llvm/lib/Target/VE/VECallingConv.td
+++ b/llvm/lib/Target/VE/VECallingConv.td
@@ -116,7 +116,7 @@ def CC_VE_Fast : CallingConv<[
   // pair of vector mask --> generic vector mask registers
   CCIfType<[v512i1],
            CCAssignToRegWithShadow<[VMP1, VMP2, VMP3],
-                                   [VM1, VM1, VM3]>>,
+                                   [VM1, VM3, VM5]>>,
 
   // Follow the standard C CC for scalars.
   CCDelegateTo<CC_VE_C>
@@ -137,7 +137,7 @@ def RetCC_VE_Fast : CallingConv<[
   // pair of vector mask --> generic vector mask registers
   CCIfType<[v512i1],
            CCAssignToRegWithShadow<[VMP1, VMP2, VMP3],
-                                   [VM1, VM1, VM3]>>,
+                                   [VM1, VM3, VM5]>>,
 
   // Follow the standard C CC for scalars.
   CCDelegateTo<RetCC_VE_C>
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 408c28205aa2f..ea9281a005021 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -135,6 +135,10 @@ void VETargetLowering::initSPUActions() {
   /// Stack {
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
+
+  // Use the default implementation.
+  setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
+  setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
   /// } Stack
 
   /// Branch {
@@ -1510,6 +1514,26 @@ static SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
   return FrameAddr;
 }
 
+static SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
+                               const VETargetLowering &TLI,
+                               const VESubtarget *Subtarget) {
+  MachineFunction &MF = DAG.getMachineFunction();
+  MachineFrameInfo &MFI = MF.getFrameInfo();
+  MFI.setReturnAddressIsTaken(true);
+
+  if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
+    return SDValue();
+
+  SDValue FrameAddr = lowerFRAMEADDR(Op, DAG, TLI, Subtarget);
+
+  SDLoc DL(Op);
+  EVT VT = Op.getValueType();
+  SDValue Offset = DAG.getConstant(8, DL, VT);
+  return DAG.getLoad(VT, DL, DAG.getEntryNode(),
+                     DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
+                     MachinePointerInfo());
+}
+
 static SDValue getSplatValue(SDNode *N) {
   if (auto *BuildVec = dyn_cast<BuildVectorSDNode>(N)) {
     return BuildVec->getSplatValue();
@@ -1560,6 +1584,8 @@ SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
     return lowerJumpTable(Op, DAG);
   case ISD::LOAD:
     return lowerLOAD(Op, DAG);
+  case ISD::RETURNADDR:
+    return lowerRETURNADDR(Op, DAG, *this, Subtarget);
   case ISD::BUILD_VECTOR:
     return lowerBUILD_VECTOR(Op, DAG);
   case ISD::STORE:
diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td
index fce3bf06b9d3f..debd00ff6f96d 100644
--- a/llvm/lib/Target/VE/VEInstrInfo.td
+++ b/llvm/lib/Target/VE/VEInstrInfo.td
@@ -1608,6 +1608,8 @@ def vehi_only : OutPatFrag<(ops node:$hi),
                            (LEASLzii 0, 0, $hi)>;
 def vehi_lo : OutPatFrag<(ops node:$hi, node:$lo),
                          (LEASLrii $lo, 0, $hi)>;
+def vehi_lo_imm : OutPatFrag<(ops node:$hi, node:$lo, node:$idx),
+                             (LEASLrii $lo, $idx, $hi)>;
 def vehi_baselo : OutPatFrag<(ops node:$base, node:$hi, node:$lo),
                              (LEASLrri $base, $lo, $hi)>;
 foreach type = [ "tblockaddress", "tconstpool", "texternalsym", "tglobaladdr",
@@ -1615,6 +1617,8 @@ foreach type = [ "tblockaddress", "tconstpool", "texternalsym", "tglobaladdr",
   def : Pat<(VElo !cast<SDNode>(type):$lo), (velo_only $lo)>;
   def : Pat<(VEhi !cast<SDNode>(type):$hi), (vehi_only $hi)>;
   def : Pat<(add (VEhi !cast<SDNode>(type):$hi), I64:$lo), (vehi_lo $hi, $lo)>;
+  def : Pat<(add (add (VEhi !cast<SDNode>(type):$hi), I64:$lo), simm7:$val),
+            (vehi_lo_imm $hi, $lo, (LO7 $val))>;
   def : Pat<(add I64:$base, (add (VEhi !cast<SDNode>(type):$hi), I64:$lo)),
             (vehi_baselo $base, $hi, $lo)>;
 }
diff --git a/llvm/lib/Target/VE/VVPInstrInfo.td b/llvm/lib/Target/VE/VVPInstrInfo.td
index 81fbfe03b48f3..2c88d5099a7b6 100644
--- a/llvm/lib/Target/VE/VVPInstrInfo.td
+++ b/llvm/lib/Target/VE/VVPInstrInfo.td
@@ -40,4 +40,7 @@ class vvp_commutative<SDNode RootOp> :
 def vvp_add    : SDNode<"VEISD::VVP_ADD",  SDTIntBinOpVVP>;
 def c_vvp_add  : vvp_commutative<vvp_add>;
 
+def vvp_and    : SDNode<"VEISD::VVP_AND",  SDTIntBinOpVVP>;
+def c_vvp_and  : vvp_commutative<vvp_and>;
+
 // } Binary Operators
diff --git a/llvm/lib/Target/VE/VVPInstrPatternsVec.td b/llvm/lib/Target/VE/VVPInstrPatternsVec.td
index 2345173314a4a..7003fb387670c 100644
--- a/llvm/lib/Target/VE/VVPInstrPatternsVec.td
+++ b/llvm/lib/Target/VE/VVPInstrPatternsVec.td
@@ -66,3 +66,6 @@ multiclass VectorBinaryArith_ShortLong<
 defm : VectorBinaryArith_ShortLong<c_vvp_add,
                                    i64, v256i64, "VADDSL",
                                    i32, v256i32, "VADDSWSX">;
+defm : VectorBinaryArith_ShortLong<c_vvp_and,
+                                   i64, v256i64, "VAND",
+                                   i32, v256i32, "PVANDLO">;
diff --git a/llvm/lib/Target/VE/VVPNodes.def b/llvm/lib/Target/VE/VVPNodes.def
index 4319b332388e1..1f9cbd7902351 100644
--- a/llvm/lib/Target/VE/VVPNodes.def
+++ b/llvm/lib/Target/VE/VVPNodes.def
@@ -27,6 +27,7 @@
 // Integer arithmetic.
 ADD_BINARY_VVP_OP(VVP_ADD,ADD)
 
+ADD_BINARY_VVP_OP(VVP_AND,AND)
 
 #undef ADD_BINARY_VVP_OP
 #undef ADD_VVP_OP
diff --git a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
index fccee4b96ed51..6c819f396ddc1 100644
--- a/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
+++ b/llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h
@@ -194,9 +194,9 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
   WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64)
   WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
   WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
-  WASM_LOAD_STORE(LOAD_SPLAT_v8x16)
-  WASM_LOAD_STORE(LOAD_LANE_v16i8)
-  WASM_LOAD_STORE(STORE_LANE_v16i8)
+  WASM_LOAD_STORE(LOAD8_SPLAT)
+  WASM_LOAD_STORE(LOAD_LANE_I8x16)
+  WASM_LOAD_STORE(STORE_LANE_I8x16)
   return 0;
   WASM_LOAD_STORE(LOAD16_S_I32)
   WASM_LOAD_STORE(LOAD16_U_I32)
@@ -222,9 +222,9 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
   WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64)
   WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
   WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
-  WASM_LOAD_STORE(LOAD_SPLAT_v16x8)
-  WASM_LOAD_STORE(LOAD_LANE_v8i16)
-  WASM_LOAD_STORE(STORE_LANE_v8i16)
+  WASM_LOAD_STORE(LOAD16_SPLAT)
+  WASM_LOAD_STORE(LOAD_LANE_I16x8)
+  WASM_LOAD_STORE(STORE_LANE_I16x8)
   return 1;
   WASM_LOAD_STORE(LOAD_I32)
   WASM_LOAD_STORE(LOAD_F32)
@@ -253,10 +253,10 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
   WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64)
   WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY)
   WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32)
-  WASM_LOAD_STORE(LOAD_SPLAT_v32x4)
-  WASM_LOAD_STORE(LOAD_ZERO_v4i32)
-  WASM_LOAD_STORE(LOAD_LANE_v4i32)
-  WASM_LOAD_STORE(STORE_LANE_v4i32)
+  WASM_LOAD_STORE(LOAD32_SPLAT)
+  WASM_LOAD_STORE(LOAD_ZERO_I32x4)
+  WASM_LOAD_STORE(LOAD_LANE_I32x4)
+  WASM_LOAD_STORE(STORE_LANE_I32x4)
   return 2;
   WASM_LOAD_STORE(LOAD_I64)
   WASM_LOAD_STORE(LOAD_F64)
@@ -272,16 +272,16 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
   WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64)
   WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64)
   WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64)
-  WASM_LOAD_STORE(LOAD_SPLAT_v64x2)
-  WASM_LOAD_STORE(LOAD_EXTEND_S_v8i16)
-  WASM_LOAD_STORE(LOAD_EXTEND_U_v8i16)
-  WASM_LOAD_STORE(LOAD_EXTEND_S_v4i32)
-  WASM_LOAD_STORE(LOAD_EXTEND_U_v4i32)
-  WASM_LOAD_STORE(LOAD_EXTEND_S_v2i64)
-  WASM_LOAD_STORE(LOAD_EXTEND_U_v2i64)
-  WASM_LOAD_STORE(LOAD_ZERO_v2i64)
-  WASM_LOAD_STORE(LOAD_LANE_v2i64)
-  WASM_LOAD_STORE(STORE_LANE_v2i64)
+  WASM_LOAD_STORE(LOAD64_SPLAT)
+  WASM_LOAD_STORE(LOAD_EXTEND_S_I16x8)
+  WASM_LOAD_STORE(LOAD_EXTEND_U_I16x8)
+  WASM_LOAD_STORE(LOAD_EXTEND_S_I32x4)
+  WASM_LOAD_STORE(LOAD_EXTEND_U_I32x4)
+  WASM_LOAD_STORE(LOAD_EXTEND_S_I64x2)
+  WASM_LOAD_STORE(LOAD_EXTEND_U_I64x2)
+  WASM_LOAD_STORE(LOAD_ZERO_I64x2)
+  WASM_LOAD_STORE(LOAD_LANE_I64x2)
+  WASM_LOAD_STORE(STORE_LANE_I64x2)
   return 3;
   WASM_LOAD_STORE(LOAD_V128)
   WASM_LOAD_STORE(STORE_V128)
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 191cdea0c0aee..df4de49ee4c8f 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -37,6 +37,75 @@ def ImmI#SIZE : ImmLeaf<i32,
 foreach SIZE = [2, 4, 8, 16, 32] in
 def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
 
+class Vec {
+  ValueType vt;
+  ValueType lane_vt;
+  WebAssemblyRegClass lane_rc;
+  int lane_bits;
+  ImmLeaf lane_idx;
+  string prefix;
+  Vec split;
+}
+
+def I8x16 : Vec {
+  let vt = v16i8;
+  let lane_vt = i32;
+  let lane_rc = I32;
+  let lane_bits = 8;
+  let lane_idx = LaneIdx16;
+  let prefix = "i8x16";
+}
+
+def I16x8 : Vec {
+  let vt = v8i16;
+  let lane_vt = i32;
+  let lane_rc = I32;
+  let lane_bits = 16;
+  let lane_idx = LaneIdx8;
+  let prefix = "i16x8";
+  let split = I8x16;
+}
+
+def I32x4 : Vec {
+  let vt = v4i32;
+  let lane_vt = i32;
+  let lane_rc = I32;
+  let lane_bits = 32;
+  let lane_idx = LaneIdx4;
+  let prefix = "i32x4";
+  let split = I16x8;
+}
+
+def I64x2 : Vec {
+  let vt = v2i64;
+  let lane_vt = i64;
+  let lane_rc = I64;
+  let lane_bits = 64;
+  let lane_idx = LaneIdx2;
+  let prefix = "i64x2";
+  let split = I32x4;
+}
+
+def F32x4 : Vec {
+  let vt = v4f32;
+  let lane_vt = f32;
+  let lane_rc = F32;
+  let lane_bits = 32;
+  let lane_idx = LaneIdx4;
+  let prefix = "f32x4";
+}
+
+def F64x2 : Vec {
+  let vt = v2f64;
+  let lane_vt = f64;
+  let lane_rc = F64;
+  let lane_bits = 64;
+  let lane_idx = LaneIdx2;
+  let prefix = "f64x2";
+}
+
+defvar AllVecs = [I8x16, I16x8, I32x4, I64x2, F32x4, F64x2];
+
 //===----------------------------------------------------------------------===//
 // Load and store
 //===----------------------------------------------------------------------===//
@@ -56,125 +125,113 @@ defm LOAD_V128_A64 :
 }
 
 // Def load patterns from WebAssemblyInstrMemory.td for vector types
-foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
-defm : LoadPatNoOffset<vec_t, load, "LOAD_V128">;
-defm : LoadPatImmOff<vec_t, load, regPlusImm, "LOAD_V128">;
-defm : LoadPatImmOff<vec_t, load, or_is_add, "LOAD_V128">;
-defm : LoadPatOffsetOnly<vec_t, load, "LOAD_V128">;
-defm : LoadPatGlobalAddrOffOnly<vec_t, load, "LOAD_V128">;
+foreach vec = AllVecs in {
+defm : LoadPatNoOffset<vec.vt, load, "LOAD_V128">;
+defm : LoadPatImmOff<vec.vt, load, regPlusImm, "LOAD_V128">;
+defm : LoadPatImmOff<vec.vt, load, or_is_add, "LOAD_V128">;
+defm : LoadPatOffsetOnly<vec.vt, load, "LOAD_V128">;
+defm : LoadPatGlobalAddrOffOnly<vec.vt, load, "LOAD_V128">;
 }
 
-// vNxM.load_splat
-multiclass SIMDLoadSplat<string vec, bits<32> simdop> {
+// v128.loadX_splat
+multiclass SIMDLoadSplat<int size, bits<32> simdop> {
   let mayLoad = 1, UseNamedOperandTable = 1 in {
-  defm LOAD_SPLAT_#vec#_A32 :
+  defm LOAD#size#_SPLAT_A32 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
            (outs),
            (ins P2Align:$p2align, offset32_op:$off), [],
-           vec#".load_splat\t$dst, ${off}(${addr})$p2align",
-           vec#".load_splat\t$off$p2align", simdop>;
-  defm LOAD_SPLAT_#vec#_A64 :
+           "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
+           "v128.load"#size#"_splat\t$off$p2align", simdop>;
+  defm LOAD#size#_SPLAT_A64 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
            (outs),
            (ins P2Align:$p2align, offset64_op:$off), [],
-           vec#".load_splat\t$dst, ${off}(${addr})$p2align",
-           vec#".load_splat\t$off$p2align", simdop>;
+           "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
+           "v128.load"#size#"_splat\t$off$p2align", simdop>;
   }
 }
 
-defm "" : SIMDLoadSplat<"v8x16", 7>;
-defm "" : SIMDLoadSplat<"v16x8", 8>;
-defm "" : SIMDLoadSplat<"v32x4", 9>;
-defm "" : SIMDLoadSplat<"v64x2", 10>;
+defm "" : SIMDLoadSplat<8, 7>;
+defm "" : SIMDLoadSplat<16, 8>;
+defm "" : SIMDLoadSplat<32, 9>;
+defm "" : SIMDLoadSplat<64, 10>;
 
 def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>;
 def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t,
                              [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>;
 
-foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"],
-                ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in {
-defm : LoadPatNoOffset<!cast<ValueType>(args[0]),
-                       load_splat,
-                       "LOAD_SPLAT_"#args[1]>;
-defm : LoadPatImmOff<!cast<ValueType>(args[0]),
-                     load_splat,
-                     regPlusImm,
-                     "LOAD_SPLAT_"#args[1]>;
-defm : LoadPatImmOff<!cast<ValueType>(args[0]),
-                     load_splat,
-                     or_is_add,
-                     "LOAD_SPLAT_"#args[1]>;
-defm : LoadPatOffsetOnly<!cast<ValueType>(args[0]),
-                         load_splat,
-                         "LOAD_SPLAT_"#args[1]>;
-defm : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]),
-                                load_splat,
-                                "LOAD_SPLAT_"#args[1]>;
+foreach vec = AllVecs in {
+defvar inst = "LOAD"#vec.lane_bits#"_SPLAT";
+defm : LoadPatNoOffset<vec.vt, load_splat, inst>;
+defm : LoadPatImmOff<vec.vt, load_splat, regPlusImm, inst>;
+defm : LoadPatImmOff<vec.vt, load_splat, or_is_add, inst>;
+defm : LoadPatOffsetOnly<vec.vt, load_splat, inst>;
+defm : LoadPatGlobalAddrOffOnly<vec.vt, load_splat, inst>;
 }
 
 // Load and extend
-multiclass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> {
+multiclass SIMDLoadExtend<Vec vec, string loadPat, bits<32> simdop> {
+  defvar signed = vec.prefix#".load"#loadPat#"_s";
+  defvar unsigned = vec.prefix#".load"#loadPat#"_u";
   let mayLoad = 1, UseNamedOperandTable = 1 in {
-  defm LOAD_EXTEND_S_#vec_t#_A32 :
+  defm LOAD_EXTEND_S_#vec#_A32 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
            (outs), (ins P2Align:$p2align, offset32_op:$off), [],
-           name#"_s\t$dst, ${off}(${addr})$p2align",
-           name#"_s\t$off$p2align", simdop>;
-  defm LOAD_EXTEND_U_#vec_t#_A32 :
+           signed#"\t$dst, ${off}(${addr})$p2align",
+           signed#"\t$off$p2align", simdop>;
+  defm LOAD_EXTEND_U_#vec#_A32 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
            (outs), (ins P2Align:$p2align, offset32_op:$off), [],
-           name#"_u\t$dst, ${off}(${addr})$p2align",
-           name#"_u\t$off$p2align", !add(simdop, 1)>;
-  defm LOAD_EXTEND_S_#vec_t#_A64 :
+           unsigned#"\t$dst, ${off}(${addr})$p2align",
+           unsigned#"\t$off$p2align", !add(simdop, 1)>;
+  defm LOAD_EXTEND_S_#vec#_A64 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
            (outs), (ins P2Align:$p2align, offset64_op:$off), [],
-           name#"_s\t$dst, ${off}(${addr})$p2align",
-           name#"_s\t$off$p2align", simdop>;
-  defm LOAD_EXTEND_U_#vec_t#_A64 :
+           signed#"\t$dst, ${off}(${addr})$p2align",
+           signed#"\t$off$p2align", simdop>;
+  defm LOAD_EXTEND_U_#vec#_A64 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
            (outs), (ins P2Align:$p2align, offset64_op:$off), [],
-           name#"_u\t$dst, ${off}(${addr})$p2align",
-           name#"_u\t$off$p2align", !add(simdop, 1)>;
+           unsigned#"\t$dst, ${off}(${addr})$p2align",
+           unsigned#"\t$off$p2align", !add(simdop, 1)>;
   }
 }
 
-defm "" : SIMDLoadExtend<v8i16, "i16x8.load8x8", 1>;
-defm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 3>;
-defm "" : SIMDLoadExtend<v2i64, "i64x2.load32x2", 5>;
-
-foreach types = [[v8i16, i8], [v4i32, i16], [v2i64, i32]] in
-foreach exts = [["sextloadv", "_S"],
-                ["zextloadv", "_U"],
-                ["extloadv", "_U"]] in {
-defm : LoadPatNoOffset<types[0], !cast<PatFrag>(exts[0]#types[1]),
-                       "LOAD_EXTEND"#exts[1]#"_"#types[0]>;
-defm : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), regPlusImm,
-                     "LOAD_EXTEND"#exts[1]#"_"#types[0]>;
-defm : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), or_is_add,
-                     "LOAD_EXTEND"#exts[1]#"_"#types[0]>;
-defm : LoadPatOffsetOnly<types[0], !cast<PatFrag>(exts[0]#types[1]),
-                         "LOAD_EXTEND"#exts[1]#"_"#types[0]>;
-defm : LoadPatGlobalAddrOffOnly<types[0], !cast<PatFrag>(exts[0]#types[1]),
-                                "LOAD_EXTEND"#exts[1]#"_"#types[0]>;
+defm "" : SIMDLoadExtend<I16x8, "8x8", 1>;
+defm "" : SIMDLoadExtend<I32x4, "16x4", 3>;
+defm "" : SIMDLoadExtend<I64x2, "32x2", 5>;
+
+foreach vec = [I16x8, I32x4, I64x2] in
+foreach exts = [["sextloadvi", "_S"],
+                ["zextloadvi", "_U"],
+                ["extloadvi", "_U"]] in {
+defvar loadpat = !cast<PatFrag>(exts[0]#vec.split.lane_bits);
+defvar inst = "LOAD_EXTEND"#exts[1]#"_"#vec;
+defm : LoadPatNoOffset<vec.vt, loadpat, inst>;
+defm : LoadPatImmOff<vec.vt, loadpat, regPlusImm, inst>;
+defm : LoadPatImmOff<vec.vt, loadpat, or_is_add, inst>;
+defm : LoadPatOffsetOnly<vec.vt, loadpat, inst>;
+defm : LoadPatGlobalAddrOffOnly<vec.vt, loadpat, inst>;
 }
 
 // Load lane into zero vector
-multiclass SIMDLoadZero<ValueType vec_t, string name, bits<32> simdop> {
+multiclass SIMDLoadZero<Vec vec, bits<32> simdop> {
+  defvar name = "v128.load"#vec.lane_bits#"_zero";
   let mayLoad = 1, UseNamedOperandTable = 1 in {
-  defm LOAD_ZERO_#vec_t#_A32 :
+  defm LOAD_ZERO_#vec#_A32 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
            (outs), (ins P2Align:$p2align, offset32_op:$off), [],
            name#"\t$dst, ${off}(${addr})$p2align",
            name#"\t$off$p2align", simdop>;
-  defm LOAD_ZERO_#vec_t#_A64 :
+  defm LOAD_ZERO_#vec#_A64 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
            (outs), (ins P2Align:$p2align, offset64_op:$off), [],
@@ -185,35 +242,31 @@ multiclass SIMDLoadZero<ValueType vec_t, string name, bits<32> simdop> {
 
 // TODO: Also support v4f32 and v2f64 once the instructions are merged
 // to the proposal
-defm "" : SIMDLoadZero<v4i32, "v128.load32_zero", 252>;
-defm "" : SIMDLoadZero<v2i64, "v128.load64_zero", 253>;
-
-defm : LoadPatNoOffset<v4i32, int_wasm_load32_zero, "LOAD_ZERO_v4i32">;
-defm : LoadPatNoOffset<v2i64, int_wasm_load64_zero, "LOAD_ZERO_v2i64">;
-
-defm : LoadPatImmOff<v4i32, int_wasm_load32_zero, regPlusImm, "LOAD_ZERO_v4i32">;
-defm : LoadPatImmOff<v2i64, int_wasm_load64_zero, regPlusImm, "LOAD_ZERO_v2i64">;
-
-defm : LoadPatImmOff<v4i32, int_wasm_load32_zero, or_is_add, "LOAD_ZERO_v4i32">;
-defm : LoadPatImmOff<v2i64, int_wasm_load64_zero, or_is_add, "LOAD_ZERO_v2i64">;
-
-defm : LoadPatOffsetOnly<v4i32, int_wasm_load32_zero, "LOAD_ZERO_v4i32">;
-defm : LoadPatOffsetOnly<v2i64, int_wasm_load64_zero, "LOAD_ZERO_v2i64">;
-
-defm : LoadPatGlobalAddrOffOnly<v4i32, int_wasm_load32_zero, "LOAD_ZERO_v4i32">;
-defm : LoadPatGlobalAddrOffOnly<v2i64, int_wasm_load64_zero, "LOAD_ZERO_v2i64">;
+defm "" : SIMDLoadZero<I32x4, 252>;
+defm "" : SIMDLoadZero<I64x2, 253>;
+
+foreach vec = [I32x4, I64x2] in {
+defvar loadpat = !cast<Intrinsic>("int_wasm_load"#vec.lane_bits#"_zero");
+defvar inst = "LOAD_ZERO_"#vec;
+defm : LoadPatNoOffset<vec.vt, loadpat, inst>;
+defm : LoadPatImmOff<vec.vt, loadpat, regPlusImm, inst>;
+defm : LoadPatImmOff<vec.vt, loadpat, or_is_add, inst>;
+defm : LoadPatOffsetOnly<vec.vt, loadpat, inst>;
+defm : LoadPatGlobalAddrOffOnly<vec.vt, loadpat, inst>;
+}
 
 // Load lane
-multiclass SIMDLoadLane<ValueType vec_t, string name, bits<32> simdop> {
+multiclass SIMDLoadLane<Vec vec, bits<32> simdop> {
+  defvar name = "v128.load"#vec.lane_bits#"_lane";
   let mayLoad = 1, UseNamedOperandTable = 1 in {
-  defm LOAD_LANE_#vec_t#_A32 :
+  defm LOAD_LANE_#vec#_A32 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx,
                 I32:$addr, V128:$vec),
            (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx),
            [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
            name#"\t$off$p2align, $idx", simdop>;
-  defm LOAD_LANE_#vec_t#_A64 :
+  defm LOAD_LANE_#vec#_A64 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx,
                 I64:$addr, V128:$vec),
@@ -225,25 +278,29 @@ multiclass SIMDLoadLane<ValueType vec_t, string name, bits<32> simdop> {
 
 // TODO: Also support v4f32 and v2f64 once the instructions are merged
 // to the proposal
-defm "" : SIMDLoadLane<v16i8, "v128.load8_lane", 88>;
-defm "" : SIMDLoadLane<v8i16, "v128.load16_lane", 89>;
-defm "" : SIMDLoadLane<v4i32, "v128.load32_lane", 90>;
-defm "" : SIMDLoadLane<v2i64, "v128.load64_lane", 91>;
+defm "" : SIMDLoadLane<I8x16, 88>;
+defm "" : SIMDLoadLane<I16x8, 89>;
+defm "" : SIMDLoadLane<I32x4, 90>;
+defm "" : SIMDLoadLane<I64x2, 91>;
 
 // Select loads with no constant offset.
-multiclass LoadLanePatNoOffset<ValueType ty, PatFrag kind, ImmLeaf lane_imm_t> {
-  def : Pat<(ty (kind (i32 I32:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx))),
-            (!cast<NI>("LOAD_LANE_"#ty#"_A32") 0, 0, imm:$idx, I32:$addr, V128:$vec)>,
+multiclass LoadLanePatNoOffset<Vec vec, PatFrag kind> {
+  defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32");
+  defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64");
+  def : Pat<(vec.vt (kind (i32 I32:$addr),
+              (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
+            (load_lane_a32 0, 0, imm:$idx, I32:$addr, V128:$vec)>,
         Requires<[HasAddr32]>;
-  def : Pat<(ty (kind (i64 I64:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx))),
-            (!cast<NI>("LOAD_LANE_"#ty#"_A64") 0, 0, imm:$idx, I64:$addr, V128:$vec)>,
+  def : Pat<(vec.vt (kind (i64 I64:$addr),
+              (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
+            (load_lane_a64 0, 0, imm:$idx, I64:$addr, V128:$vec)>,
         Requires<[HasAddr64]>;
 }
 
-defm : LoadLanePatNoOffset<v16i8, int_wasm_load8_lane, LaneIdx16>;
-defm : LoadLanePatNoOffset<v8i16, int_wasm_load16_lane, LaneIdx8>;
-defm : LoadLanePatNoOffset<v4i32, int_wasm_load32_lane, LaneIdx4>;
-defm : LoadLanePatNoOffset<v2i64, int_wasm_load64_lane, LaneIdx2>;
+defm : LoadLanePatNoOffset<I8x16, int_wasm_load8_lane>;
+defm : LoadLanePatNoOffset<I16x8, int_wasm_load16_lane>;
+defm : LoadLanePatNoOffset<I32x4, int_wasm_load32_lane>;
+defm : LoadLanePatNoOffset<I64x2, int_wasm_load64_lane>;
 
 // TODO: Also support the other load patterns for load_lane once the instructions
 // are merged to the proposal.
@@ -263,25 +320,26 @@ defm STORE_V128_A64 :
 }
 
 // Def store patterns from WebAssemblyInstrMemory.td for vector types
-foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
-defm : StorePatNoOffset<vec_t, store, "STORE_V128">;
-defm : StorePatImmOff<vec_t, store, regPlusImm, "STORE_V128">;
-defm : StorePatImmOff<vec_t, store, or_is_add, "STORE_V128">;
-defm : StorePatOffsetOnly<vec_t, store, "STORE_V128">;
-defm : StorePatGlobalAddrOffOnly<vec_t, store, "STORE_V128">;
+foreach vec = AllVecs in {
+defm : StorePatNoOffset<vec.vt, store, "STORE_V128">;
+defm : StorePatImmOff<vec.vt, store, regPlusImm, "STORE_V128">;
+defm : StorePatImmOff<vec.vt, store, or_is_add, "STORE_V128">;
+defm : StorePatOffsetOnly<vec.vt, store, "STORE_V128">;
+defm : StorePatGlobalAddrOffOnly<vec.vt, store, "STORE_V128">;
 }
 
 // Store lane
-multiclass SIMDStoreLane<ValueType vec_t, string name, bits<32> simdop> {
+multiclass SIMDStoreLane<Vec vec, bits<32> simdop> {
+  defvar name = "v128.store"#vec.lane_bits#"_lane";
   let mayStore = 1, UseNamedOperandTable = 1 in {
-  defm STORE_LANE_#vec_t#_A32 :
+  defm STORE_LANE_#vec#_A32 :
     SIMD_I<(outs),
            (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx,
                 I32:$addr, V128:$vec),
            (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx),
            [], name#"\t${off}(${addr})$p2align, $vec, $idx",
            name#"\t$off$p2align, $idx", simdop>;
-  defm STORE_LANE_#vec_t#_A64 :
+  defm STORE_LANE_#vec#_A64 :
     SIMD_I<(outs V128:$dst),
            (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx,
                 I64:$addr, V128:$vec),
@@ -293,27 +351,27 @@ multiclass SIMDStoreLane<ValueType vec_t, string name, bits<32> simdop> {
 
 // TODO: Also support v4f32 and v2f64 once the instructions are merged
 // to the proposal
-defm "" : SIMDStoreLane<v16i8, "v128.store8_lane", 92>;
-defm "" : SIMDStoreLane<v8i16, "v128.store16_lane", 93>;
-defm "" : SIMDStoreLane<v4i32, "v128.store32_lane", 94>;
-defm "" : SIMDStoreLane<v2i64, "v128.store64_lane", 95>;
+defm "" : SIMDStoreLane<I8x16, 92>;
+defm "" : SIMDStoreLane<I16x8, 93>;
+defm "" : SIMDStoreLane<I32x4, 94>;
+defm "" : SIMDStoreLane<I64x2, 95>;
 
 // Select stores with no constant offset.
-multiclass StoreLanePatNoOffset<ValueType ty, PatFrag kind, ImmLeaf lane_imm_t> {
-  def : Pat<(kind (i32 I32:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx)),
-            (!cast<NI>("STORE_LANE_"#ty#"_A32")
-              0, 0, imm:$idx, I32:$addr, ty:$vec)>,
+multiclass StoreLanePatNoOffset<Vec vec, PatFrag kind> {
+  def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
+            (!cast<NI>("STORE_LANE_"#vec#"_A32")
+              0, 0, imm:$idx, I32:$addr, vec.vt:$vec)>,
         Requires<[HasAddr32]>;
-  def : Pat<(kind (i64 I64:$addr), (ty V128:$vec), (i32 lane_imm_t:$idx)),
-            (!cast<NI>("STORE_LANE_"#ty#"_A64")
-              0, 0, imm:$idx, I64:$addr, ty:$vec)>,
+  def : Pat<(kind (i64 I64:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
+            (!cast<NI>("STORE_LANE_"#vec#"_A64")
+              0, 0, imm:$idx, I64:$addr, vec.vt:$vec)>,
         Requires<[HasAddr64]>;
 }
 
-defm : StoreLanePatNoOffset<v16i8, int_wasm_store8_lane, LaneIdx16>;
-defm : StoreLanePatNoOffset<v8i16, int_wasm_store16_lane, LaneIdx8>;
-defm : StoreLanePatNoOffset<v4i32, int_wasm_store32_lane, LaneIdx4>;
-defm : StoreLanePatNoOffset<v2i64, int_wasm_store64_lane, LaneIdx2>;
+defm : StoreLanePatNoOffset<I8x16, int_wasm_store8_lane>;
+defm : StoreLanePatNoOffset<I16x8, int_wasm_store16_lane>;
+defm : StoreLanePatNoOffset<I32x4, int_wasm_store32_lane>;
+defm : StoreLanePatNoOffset<I64x2, int_wasm_store64_lane>;
 
 // TODO: Also support the other store patterns for store_lane once the
 // instructions are merged to the proposal.
@@ -401,10 +459,10 @@ defm SHUFFLE :
            vec_i8imm_op:$mC, vec_i8imm_op:$mD,
            vec_i8imm_op:$mE, vec_i8imm_op:$mF),
          [],
-         "v8x16.shuffle\t$dst, $x, $y, "#
+         "i8x16.shuffle\t$dst, $x, $y, "#
            "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
            "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
-         "v8x16.shuffle\t"#
+         "i8x16.shuffle\t"#
            "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
            "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
          13>;
@@ -433,14 +491,14 @@ def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
             (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;
 }
 
-// Swizzle lanes: v8x16.swizzle
+// Swizzle lanes: i8x16.swizzle
 def wasm_swizzle_t : SDTypeProfile<1, 2, []>;
 def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>;
 defm SWIZZLE :
   SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
          [(set (v16i8 V128:$dst),
            (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
-         "v8x16.swizzle\t$dst, $src, $mask", "v8x16.swizzle", 14>;
+         "i8x16.swizzle\t$dst, $src, $mask", "i8x16.swizzle", 14>;
 
 def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
           (SWIZZLE V128:$src, V128:$mask)>;
diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 2a303dc2fa4d2..0c2b278fdd7b8 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -6505,7 +6505,7 @@ multiclass avx512_fma3p_213_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
 }
 
 defm VFMADD213    : avx512_fma3p_213_f<0xA8, "vfmadd213", any_fma,
-                                       X86Fmadd, X86FmaddRnd>;
+                                       fma, X86FmaddRnd>;
 defm VFMSUB213    : avx512_fma3p_213_f<0xAA, "vfmsub213", X86any_Fmsub,
                                        X86Fmsub, X86FmsubRnd>;
 defm VFMADDSUB213 : avx512_fma3p_213_f<0xA6, "vfmaddsub213", X86Fmaddsub,
@@ -6596,7 +6596,7 @@ multiclass avx512_fma3p_231_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
 }
 
 defm VFMADD231    : avx512_fma3p_231_f<0xB8, "vfmadd231", any_fma,
-                                       X86Fmadd, X86FmaddRnd>;
+                                       fma, X86FmaddRnd>;
 defm VFMSUB231    : avx512_fma3p_231_f<0xBA, "vfmsub231", X86any_Fmsub,
                                        X86Fmsub, X86FmsubRnd>;
 defm VFMADDSUB231 : avx512_fma3p_231_f<0xB6, "vfmaddsub231", X86Fmaddsub,
@@ -6688,7 +6688,7 @@ multiclass avx512_fma3p_132_f<bits<8> opc, string OpcodeStr, SDNode OpNode,
 }
 
 defm VFMADD132    : avx512_fma3p_132_f<0x98, "vfmadd132", any_fma,
-                                       X86Fmadd, X86FmaddRnd>;
+                                       fma, X86FmaddRnd>;
 defm VFMSUB132    : avx512_fma3p_132_f<0x9A, "vfmsub132", X86any_Fmsub,
                                        X86Fmsub, X86FmsubRnd>;
 defm VFMADDSUB132 : avx512_fma3p_132_f<0x96, "vfmaddsub132", X86Fmaddsub,
@@ -6998,7 +6998,7 @@ multiclass avx512_scalar_fma_patterns<SDNode Op, SDNode MaskedOp,
   }
 }
 
-defm : avx512_scalar_fma_patterns<any_fma, X86Fmadd, X86FmaddRnd, "VFMADD",
+defm : avx512_scalar_fma_patterns<any_fma, fma, X86FmaddRnd, "VFMADD",
                                   "SS", X86Movss, v4f32x_info, fp32imm0>;
 defm : avx512_scalar_fma_patterns<X86any_Fmsub, X86Fmsub, X86FmsubRnd, "VFMSUB",
                                   "SS", X86Movss, v4f32x_info, fp32imm0>;
@@ -7007,7 +7007,7 @@ defm : avx512_scalar_fma_patterns<X86any_Fnmadd, X86Fnmadd, X86FnmaddRnd, "VFNMA
 defm : avx512_scalar_fma_patterns<X86any_Fnmsub, X86Fnmsub, X86FnmsubRnd, "VFNMSUB",
                                   "SS", X86Movss, v4f32x_info, fp32imm0>;
 
-defm : avx512_scalar_fma_patterns<any_fma, X86Fmadd, X86FmaddRnd, "VFMADD",
+defm : avx512_scalar_fma_patterns<any_fma, fma, X86FmaddRnd, "VFMADD",
                                   "SD", X86Movsd, v2f64x_info, fp64imm0>;
 defm : avx512_scalar_fma_patterns<X86any_Fmsub, X86Fmsub, X86FmsubRnd, "VFMSUB",
                                   "SD", X86Movsd, v2f64x_info, fp64imm0>;
diff --git a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
index 9988395dce97a..777c5a158b4c3 100644
--- a/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ b/llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -536,8 +536,6 @@ def X86fgetexpSAE   : SDNode<"X86ISD::FGETEXP_SAE", SDTFPUnaryOp>;
 def X86fgetexps     : SDNode<"X86ISD::FGETEXPS", SDTFPBinOp>;
 def X86fgetexpSAEs  : SDNode<"X86ISD::FGETEXPS_SAE", SDTFPBinOp>;
 
-def X86Fmadd        : SDNode<"ISD::FMA",          SDTFPTernaryOp, [SDNPCommutative]>;
-def X86strict_Fmadd : SDNode<"ISD::STRICT_FMA",   SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>;
 def X86Fnmadd    : SDNode<"X86ISD::FNMADD",    SDTFPTernaryOp, [SDNPCommutative]>;
 def X86strict_Fnmadd : SDNode<"X86ISD::STRICT_FNMADD", SDTFPTernaryOp, [SDNPCommutative, SDNPHasChain]>;
 def X86any_Fnmadd : PatFrags<(ops node:$src1, node:$src2, node:$src3),
diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp
index 5b31b8e09c5c9..630df2715b899 100644
--- a/llvm/lib/Target/X86/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp
@@ -479,7 +479,7 @@ static void X86SelectAddress(const MachineInstr &I,
          "unsupported type.");
 
   if (I.getOpcode() == TargetOpcode::G_PTR_ADD) {
-    if (auto COff = getConstantVRegVal(I.getOperand(2).getReg(), MRI)) {
+    if (auto COff = getConstantVRegSExtVal(I.getOperand(2).getReg(), MRI)) {
       int64_t Imm = *COff;
       if (isInt<32>(Imm)) { // Check for displacement overflow.
         AM.Disp = static_cast<int32_t>(Imm);
diff --git a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
index e7fb699d9fda2..a7ae10d156d57 100644
--- a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+++ b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
@@ -21,6 +21,7 @@
 #include "llvm/Analysis/BasicAliasAnalysis.h"
 #include "llvm/Analysis/GlobalsModRef.h"
 #include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/Analysis/ValueTracking.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/Function.h"
@@ -39,6 +40,8 @@ using namespace PatternMatch;
 STATISTIC(NumAnyOrAllBitsSet, "Number of any/all-bits-set patterns folded");
 STATISTIC(NumGuardedRotates,
           "Number of guarded rotates transformed into funnel shifts");
+STATISTIC(NumGuardedFunnelShifts,
+          "Number of guarded funnel shifts transformed into funnel shifts");
 STATISTIC(NumPopCountRecognized, "Number of popcount idioms recognized");
 
 namespace {
@@ -67,17 +70,17 @@ class AggressiveInstCombinerLegacyPass : public FunctionPass {
 };
 } // namespace
 
-/// Match a pattern for a bitwise rotate operation that partially guards
-/// against undefined behavior by branching around the rotation when the shift
-/// amount is 0.
-static bool foldGuardedRotateToFunnelShift(Instruction &I) {
+/// Match a pattern for a bitwise funnel/rotate operation that partially guards
+/// against undefined behavior by branching around the funnel-shift/rotation
+/// when the shift amount is 0.
+static bool foldGuardedFunnelShift(Instruction &I, const DominatorTree &DT) {
   if (I.getOpcode() != Instruction::PHI || I.getNumOperands() != 2)
     return false;
 
   // As with the one-use checks below, this is not strictly necessary, but we
   // are being cautious to avoid potential perf regressions on targets that
-  // do not actually have a rotate instruction (where the funnel shift would be
-  // expanded back into math/shift/logic ops).
+  // do not actually have a funnel/rotate instruction (where the funnel shift
+  // would be expanded back into math/shift/logic ops).
   if (!isPowerOf2_32(I.getType()->getScalarSizeInBits()))
     return false;
 
@@ -111,30 +114,41 @@ static bool foldGuardedRotateToFunnelShift(Instruction &I) {
     return Intrinsic::not_intrinsic;
   };
 
-  // One phi operand must be a rotate operation, and the other phi operand must
-  // be the source value of that rotate operation:
+  // One phi operand must be a funnel/rotate operation, and the other phi
+  // operand must be the source value of that funnel/rotate operation:
   // phi [ rotate(RotSrc, ShAmt), FunnelBB ], [ RotSrc, GuardBB ]
+  // phi [ fshl(ShVal0, ShVal1, ShAmt), FunnelBB ], [ ShVal0, GuardBB ]
+  // phi [ fshr(ShVal0, ShVal1, ShAmt), FunnelBB ], [ ShVal1, GuardBB ]
   PHINode &Phi = cast<PHINode>(I);
   unsigned FunnelOp = 0, GuardOp = 1;
   Value *P0 = Phi.getOperand(0), *P1 = Phi.getOperand(1);
   Value *ShVal0, *ShVal1, *ShAmt;
   Intrinsic::ID IID = matchFunnelShift(P0, ShVal0, ShVal1, ShAmt);
-  if (IID == Intrinsic::not_intrinsic || ShVal0 != ShVal1 || ShVal0 != P1) {
+  if (IID == Intrinsic::not_intrinsic ||
+      (IID == Intrinsic::fshl && ShVal0 != P1) ||
+      (IID == Intrinsic::fshr && ShVal1 != P1)) {
     IID = matchFunnelShift(P1, ShVal0, ShVal1, ShAmt);
-    if (IID == Intrinsic::not_intrinsic || ShVal0 != ShVal1 || ShVal0 != P0)
+    if (IID == Intrinsic::not_intrinsic ||
+        (IID == Intrinsic::fshl && ShVal0 != P0) ||
+        (IID == Intrinsic::fshr && ShVal1 != P0))
       return false;
     assert((IID == Intrinsic::fshl || IID == Intrinsic::fshr) &&
            "Pattern must match funnel shift left or right");
     std::swap(FunnelOp, GuardOp);
   }
-  assert(ShVal0 == ShVal1 && "Rotation funnel shift pattern expected");
 
   // The incoming block with our source operand must be the "guard" block.
-  // That must contain a cmp+branch to avoid the rotate when the shift amount
-  // is equal to 0. The other incoming block is the block with the rotate.
+  // That must contain a cmp+branch to avoid the funnel/rotate when the shift
+  // amount is equal to 0. The other incoming block is the block with the
+  // funnel/rotate.
   BasicBlock *GuardBB = Phi.getIncomingBlock(GuardOp);
   BasicBlock *FunnelBB = Phi.getIncomingBlock(FunnelOp);
   Instruction *TermI = GuardBB->getTerminator();
+
+  // Ensure that the shift values dominate each block.
+  if (!DT.dominates(ShVal0, TermI) || !DT.dominates(ShVal1, TermI))
+    return false;
+
   ICmpInst::Predicate Pred;
   BasicBlock *PhiBB = Phi.getParent();
   if (!match(TermI, m_Br(m_ICmp(Pred, m_Specific(ShAmt), m_ZeroInt()),
@@ -144,24 +158,39 @@ static bool foldGuardedRotateToFunnelShift(Instruction &I) {
   if (Pred != CmpInst::ICMP_EQ)
     return false;
 
+  IRBuilder<> Builder(PhiBB, PhiBB->getFirstInsertionPt());
+
+  if (ShVal0 == ShVal1)
+    ++NumGuardedRotates;
+  else
+    ++NumGuardedFunnelShifts;
+
+  // If this is not a rotate then the select was blocking poison from the
+  // 'shift-by-zero' non-TVal, but a funnel shift won't - so freeze it.
+  bool IsFshl = IID == Intrinsic::fshl;
+  if (ShVal0 != ShVal1) {
+    if (IsFshl && !llvm::isGuaranteedNotToBePoison(ShVal1))
+      ShVal1 = Builder.CreateFreeze(ShVal1);
+    else if (!IsFshl && !llvm::isGuaranteedNotToBePoison(ShVal0))
+      ShVal0 = Builder.CreateFreeze(ShVal0);
+  }
+
   // We matched a variation of this IR pattern:
   // GuardBB:
   //   %cmp = icmp eq i32 %ShAmt, 0
   //   br i1 %cmp, label %PhiBB, label %FunnelBB
   // FunnelBB:
   //   %sub = sub i32 32, %ShAmt
-  //   %shr = lshr i32 %RotSrc, %sub
-  //   %shl = shl i32 %RotSrc, %ShAmt
-  //   %rot = or i32 %shr, %shl
+  //   %shr = lshr i32 %ShVal1, %sub
+  //   %shl = shl i32 %ShVal0, %ShAmt
+  //   %fsh = or i32 %shr, %shl
   //   br label %PhiBB
   // PhiBB:
-  //   %cond = phi i32 [ %RotSrc, %FunnelBB ], [ %RotSrc, %GuardBB ]
+  //   %cond = phi i32 [ %fsh, %FunnelBB ], [ %ShVal0, %GuardBB ]
   // -->
-  // llvm.fshl.i32(i32 %RotSrc, i32 %RotSrc, i32 %ShAmt)
-  IRBuilder<> Builder(PhiBB, PhiBB->getFirstInsertionPt());
+  // llvm.fshl.i32(i32 %ShVal0, i32 %ShVal1, i32 %ShAmt)
   Function *F = Intrinsic::getDeclaration(Phi.getModule(), IID, Phi.getType());
   Phi.replaceAllUsesWith(Builder.CreateCall(F, {ShVal0, ShVal1, ShAmt}));
-  ++NumGuardedRotates;
   return true;
 }
 
@@ -350,7 +379,7 @@ static bool foldUnusualPatterns(Function &F, DominatorTree &DT) {
     // iteratively in this loop rather than waiting until the end.
     for (Instruction &I : make_range(BB.rbegin(), BB.rend())) {
       MadeChange |= foldAnyOrAllBitsSet(I);
-      MadeChange |= foldGuardedRotateToFunnelShift(I);
+      MadeChange |= foldGuardedFunnelShift(I, DT);
       MadeChange |= tryToRecognizePopCount(I); 
     }
   }
diff --git a/llvm/lib/Transforms/Coroutines/CoroEarly.cpp b/llvm/lib/Transforms/Coroutines/CoroEarly.cpp
index 07c571a962b0f..e134ff7f45c67 100644
--- a/llvm/lib/Transforms/Coroutines/CoroEarly.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroEarly.cpp
@@ -164,10 +164,11 @@ bool Lowerer::lowerEarlyIntrinsics(Function &F) {
         if (cast<CoroSuspendInst>(&I)->isFinal())
           CB->setCannotDuplicate();
         break;
+      case Intrinsic::coro_end_async:
       case Intrinsic::coro_end:
         // Make sure that fallthrough coro.end is not duplicated as CoroSplit
         // pass expects that there is at most one fallthrough coro.end.
-        if (cast<CoroEndInst>(&I)->isFallthrough())
+        if (cast<AnyCoroEndInst>(&I)->isFallthrough())
           CB->setCannotDuplicate();
         break;
       case Intrinsic::coro_noop:
@@ -219,8 +220,8 @@ static bool declaresCoroEarlyIntrinsics(const Module &M) {
   return coro::declaresIntrinsics(
       M, {"llvm.coro.id", "llvm.coro.id.retcon", "llvm.coro.id.retcon.once",
           "llvm.coro.destroy", "llvm.coro.done", "llvm.coro.end",
-          "llvm.coro.noop", "llvm.coro.free", "llvm.coro.promise",
-          "llvm.coro.resume", "llvm.coro.suspend"});
+          "llvm.coro.end.async", "llvm.coro.noop", "llvm.coro.free",
+          "llvm.coro.promise", "llvm.coro.resume", "llvm.coro.suspend"});
 }
 
 PreservedAnalyses CoroEarlyPass::run(Function &F, FunctionAnalysisManager &) {
diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
index 48d52ff1d8dfa..c67d69a52fd2a 100644
--- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
@@ -2170,9 +2170,26 @@ void coro::buildCoroutineFrame(Function &F, Shape &Shape) {
   }
 
   // Put CoroEnds into their own blocks.
-  for (CoroEndInst *CE : Shape.CoroEnds)
+  for (AnyCoroEndInst *CE : Shape.CoroEnds) {
     splitAround(CE, "CoroEnd");
 
+    // Emit the musttail call function in a new block before the CoroEnd.
+    // We do this here so that the right suspend crossing info is computed for
+    // the uses of the musttail call function call. (Arguments to the coro.end
+    // instructions would be ignored)
+    if (auto *AsyncEnd = dyn_cast<CoroAsyncEndInst>(CE)) {
+      auto *MustTailCallFn = AsyncEnd->getMustTailCallFunction();
+      if (!MustTailCallFn)
+        continue;
+      IRBuilder<> Builder(AsyncEnd);
+      SmallVector<Value *, 8> Args(AsyncEnd->args());
+      auto Arguments = ArrayRef<Value *>(Args).drop_front(3);
+      auto *Call = createMustTailCall(AsyncEnd->getDebugLoc(), MustTailCallFn,
+                                      Arguments, Builder);
+      splitAround(Call, "MustTailCall.Before.CoroEnd");
+    }
+  }
+
   // Transforms multi-edge PHI Nodes, so that any value feeding into a PHI will
   // never has its definition separated from the PHI by the suspend point.
   rewritePHIs(F);
diff --git a/llvm/lib/Transforms/Coroutines/CoroInstr.h b/llvm/lib/Transforms/Coroutines/CoroInstr.h
index 1b83339224739..9fa2fd12f80b3 100644
--- a/llvm/lib/Transforms/Coroutines/CoroInstr.h
+++ b/llvm/lib/Transforms/Coroutines/CoroInstr.h
@@ -577,8 +577,7 @@ class LLVM_LIBRARY_VISIBILITY CoroSizeInst : public IntrinsicInst {
   }
 };
 
-/// This represents the llvm.coro.end instruction.
-class LLVM_LIBRARY_VISIBILITY CoroEndInst : public IntrinsicInst {
+class LLVM_LIBRARY_VISIBILITY AnyCoroEndInst : public IntrinsicInst {
   enum { FrameArg, UnwindArg };
 
 public:
@@ -587,6 +586,19 @@ class LLVM_LIBRARY_VISIBILITY CoroEndInst : public IntrinsicInst {
     return cast<Constant>(getArgOperand(UnwindArg))->isOneValue();
   }
 
+  // Methods to support type inquiry through isa, cast, and dyn_cast:
+  static bool classof(const IntrinsicInst *I) {
+    auto ID = I->getIntrinsicID();
+    return ID == Intrinsic::coro_end || ID == Intrinsic::coro_end_async;
+  }
+  static bool classof(const Value *V) {
+    return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
+  }
+};
+
+/// This represents the llvm.coro.end instruction.
+class LLVM_LIBRARY_VISIBILITY CoroEndInst : public AnyCoroEndInst {
+public:
   // Methods to support type inquiry through isa, cast, and dyn_cast:
   static bool classof(const IntrinsicInst *I) {
     return I->getIntrinsicID() == Intrinsic::coro_end;
@@ -596,6 +608,30 @@ class LLVM_LIBRARY_VISIBILITY CoroEndInst : public IntrinsicInst {
   }
 };
 
+/// This represents the llvm.coro.end instruction.
+class LLVM_LIBRARY_VISIBILITY CoroAsyncEndInst : public AnyCoroEndInst {
+  enum { FrameArg, UnwindArg, MustTailCallFuncArg };
+
+public:
+  void checkWellFormed() const;
+
+  Function *getMustTailCallFunction() const {
+    if (getNumArgOperands() < 3)
+      return nullptr;
+
+    return cast<Function>(
+        getArgOperand(MustTailCallFuncArg)->stripPointerCasts());
+  }
+
+  // Methods to support type inquiry through isa, cast, and dyn_cast:
+  static bool classof(const IntrinsicInst *I) {
+    return I->getIntrinsicID() == Intrinsic::coro_end_async;
+  }
+  static bool classof(const Value *V) {
+    return isa<IntrinsicInst>(V) && classof(cast<IntrinsicInst>(V));
+  }
+};
+
 /// This represents the llvm.coro.alloca.alloc instruction.
 class LLVM_LIBRARY_VISIBILITY CoroAllocaAllocInst : public IntrinsicInst {
   enum { SizeArg, AlignArg };
diff --git a/llvm/lib/Transforms/Coroutines/CoroInternal.h b/llvm/lib/Transforms/Coroutines/CoroInternal.h
index d08ed0aaa4b08..5d026b1edd419 100644
--- a/llvm/lib/Transforms/Coroutines/CoroInternal.h
+++ b/llvm/lib/Transforms/Coroutines/CoroInternal.h
@@ -92,7 +92,7 @@ enum class ABI {
 // values used during CoroSplit pass.
 struct LLVM_LIBRARY_VISIBILITY Shape {
   CoroBeginInst *CoroBegin;
-  SmallVector<CoroEndInst *, 4> CoroEnds;
+  SmallVector<AnyCoroEndInst *, 4> CoroEnds;
   SmallVector<CoroSizeInst *, 2> CoroSizes;
   SmallVector<AnyCoroSuspendInst *, 4> CoroSuspends;
   SmallVector<CallInst*, 2> SwiftErrorOps;
@@ -270,6 +270,8 @@ struct LLVM_LIBRARY_VISIBILITY Shape {
 };
 
 void buildCoroutineFrame(Function &F, Shape &Shape);
+CallInst *createMustTailCall(DebugLoc Loc, Function *MustTailCallFn,
+                             ArrayRef<Value *> Arguments, IRBuilder<> &);
 } // End namespace coro.
 } // End namespace llvm
 
diff --git a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp
index 7c4a204e953dc..7acd8bda00846 100644
--- a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp
@@ -173,8 +173,53 @@ static void maybeFreeRetconStorage(IRBuilder<> &Builder,
   Shape.emitDealloc(Builder, FramePtr, CG);
 }
 
+/// Replace an llvm.coro.end.async.
+/// Will inline the must tail call function call if there is one.
+/// \returns true if cleanup of the coro.end block is needed, false otherwise.
+static bool replaceCoroEndAsync(AnyCoroEndInst *End) {
+  IRBuilder<> Builder(End);
+
+  auto *EndAsync = dyn_cast<CoroAsyncEndInst>(End);
+  if (!EndAsync) {
+    Builder.CreateRetVoid();
+    return true /*needs cleanup of coro.end block*/;
+  }
+
+  auto *MustTailCallFunc = EndAsync->getMustTailCallFunction();
+  if (!MustTailCallFunc) {
+    Builder.CreateRetVoid();
+    return true /*needs cleanup of coro.end block*/;
+  }
+
+  // Move the must tail call from the predecessor block into the end block.
+  auto *CoroEndBlock = End->getParent();
+  auto *MustTailCallFuncBlock = CoroEndBlock->getSinglePredecessor();
+  assert(MustTailCallFuncBlock && "Must have a single predecessor block");
+  auto It = MustTailCallFuncBlock->getTerminator()->getIterator();
+  auto *MustTailCall = cast<CallInst>(&*std::prev(It));
+  CoroEndBlock->getInstList().splice(
+      End->getIterator(), MustTailCallFuncBlock->getInstList(), MustTailCall);
+
+  // Insert the return instruction.
+  Builder.SetInsertPoint(End);
+  Builder.CreateRetVoid();
+  InlineFunctionInfo FnInfo;
+
+  // Remove the rest of the block, by splitting it into an unreachable block.
+  auto *BB = End->getParent();
+  BB->splitBasicBlock(End);
+  BB->getTerminator()->eraseFromParent();
+
+  auto InlineRes = InlineFunction(*MustTailCall, FnInfo);
+  assert(InlineRes.isSuccess() && "Expected inlining to succeed");
+  (void)InlineRes;
+
+  // We have cleaned up the coro.end block above.
+  return false;
+}
+
 /// Replace a non-unwind call to llvm.coro.end.
-static void replaceFallthroughCoroEnd(CoroEndInst *End,
+static void replaceFallthroughCoroEnd(AnyCoroEndInst *End,
                                       const coro::Shape &Shape, Value *FramePtr,
                                       bool InResume, CallGraph *CG) {
   // Start inserting right before the coro.end.
@@ -192,9 +237,12 @@ static void replaceFallthroughCoroEnd(CoroEndInst *End,
     break;
 
   // In async lowering this returns.
-  case coro::ABI::Async:
-    Builder.CreateRetVoid();
+  case coro::ABI::Async: {
+    bool CoroEndBlockNeedsCleanup = replaceCoroEndAsync(End);
+    if (!CoroEndBlockNeedsCleanup)
+      return;
     break;
+  }
 
   // In unique continuation lowering, the continuations always return void.
   // But we may have implicitly allocated storage.
@@ -229,8 +277,9 @@ static void replaceFallthroughCoroEnd(CoroEndInst *End,
 }
 
 /// Replace an unwind call to llvm.coro.end.
-static void replaceUnwindCoroEnd(CoroEndInst *End, const coro::Shape &Shape,
-                                 Value *FramePtr, bool InResume, CallGraph *CG){
+static void replaceUnwindCoroEnd(AnyCoroEndInst *End, const coro::Shape &Shape,
+                                 Value *FramePtr, bool InResume,
+                                 CallGraph *CG) {
   IRBuilder<> Builder(End);
 
   switch (Shape.ABI) {
@@ -258,7 +307,7 @@ static void replaceUnwindCoroEnd(CoroEndInst *End, const coro::Shape &Shape,
   }
 }
 
-static void replaceCoroEnd(CoroEndInst *End, const coro::Shape &Shape,
+static void replaceCoroEnd(AnyCoroEndInst *End, const coro::Shape &Shape,
                            Value *FramePtr, bool InResume, CallGraph *CG) {
   if (End->isUnwind())
     replaceUnwindCoroEnd(End, Shape, FramePtr, InResume, CG);
@@ -511,10 +560,10 @@ void CoroCloner::replaceCoroSuspends() {
 }
 
 void CoroCloner::replaceCoroEnds() {
-  for (CoroEndInst *CE : Shape.CoroEnds) {
+  for (AnyCoroEndInst *CE : Shape.CoroEnds) {
     // We use a null call graph because there's no call graph node for
     // the cloned function yet.  We'll just be rebuilding that later.
-    auto NewCE = cast<CoroEndInst>(VMap[CE]);
+    auto *NewCE = cast<AnyCoroEndInst>(VMap[CE]);
     replaceCoroEnd(NewCE, Shape, NewFramePtr, /*in resume*/ true, nullptr);
   }
 }
@@ -1385,6 +1434,23 @@ static void coerceArguments(IRBuilder<> &Builder, FunctionType *FnTy,
   }
 }
 
+CallInst *coro::createMustTailCall(DebugLoc Loc, Function *MustTailCallFn,
+                                   ArrayRef<Value *> Arguments,
+                                   IRBuilder<> &Builder) {
+  auto *FnTy =
+      cast<FunctionType>(MustTailCallFn->getType()->getPointerElementType());
+  // Coerce the arguments, llvm optimizations seem to ignore the types in
+  // vaarg functions and throws away casts in optimized mode.
+  SmallVector<Value *, 8> CallArgs;
+  coerceArguments(Builder, FnTy, Arguments, CallArgs);
+
+  auto *TailCall = Builder.CreateCall(FnTy, MustTailCallFn, CallArgs);
+  TailCall->setTailCallKind(CallInst::TCK_MustTail);
+  TailCall->setDebugLoc(Loc);
+  TailCall->setCallingConv(MustTailCallFn->getCallingConv());
+  return TailCall;
+}
+
 static void splitAsyncCoroutine(Function &F, coro::Shape &Shape,
                                 SmallVectorImpl<Function *> &Clones) {
   assert(Shape.ABI == coro::ABI::Async);
@@ -1443,18 +1509,10 @@ static void splitAsyncCoroutine(Function &F, coro::Shape &Shape,
 
     // Insert the call to the tail call function and inline it.
     auto *Fn = Suspend->getMustTailCallFunction();
-    auto DbgLoc = Suspend->getDebugLoc();
-    SmallVector<Value *, 8> Args(Suspend->operand_values());
-    auto FnArgs = ArrayRef<Value *>(Args).drop_front(3).drop_back(1);
-    auto FnTy = cast<FunctionType>(Fn->getType()->getPointerElementType());
-    // Coerce the arguments, llvm optimizations seem to ignore the types in
-    // vaarg functions and throws away casts in optimized mode.
-    SmallVector<Value *, 8> CallArgs;
-    coerceArguments(Builder, FnTy, FnArgs, CallArgs);
-    auto *TailCall = Builder.CreateCall(FnTy, Fn, CallArgs);
-    TailCall->setDebugLoc(DbgLoc);
-    TailCall->setTailCall();
-    TailCall->setCallingConv(Fn->getCallingConv());
+    SmallVector<Value *, 8> Args(Suspend->args());
+    auto FnArgs = ArrayRef<Value *>(Args).drop_front(3);
+    auto *TailCall =
+        coro::createMustTailCall(Suspend->getDebugLoc(), Fn, FnArgs, Builder);
     Builder.CreateRetVoid();
     InlineFunctionInfo FnInfo;
     auto InlineRes = InlineFunction(*TailCall, FnInfo);
@@ -1683,7 +1741,7 @@ static void updateCallGraphAfterCoroutineSplit(
   if (!Shape.CoroBegin)
     return;
 
-  for (llvm::CoroEndInst *End : Shape.CoroEnds) {
+  for (llvm::AnyCoroEndInst *End : Shape.CoroEnds) {
     auto &Context = End->getContext();
     End->replaceAllUsesWith(ConstantInt::getFalse(Context));
     End->eraseFromParent();
diff --git a/llvm/lib/Transforms/Coroutines/Coroutines.cpp b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
index 726899f9c04c7..f0095a649b0ca 100644
--- a/llvm/lib/Transforms/Coroutines/Coroutines.cpp
+++ b/llvm/lib/Transforms/Coroutines/Coroutines.cpp
@@ -131,6 +131,7 @@ static bool isCoroutineIntrinsicName(StringRef Name) {
       "llvm.coro.destroy",
       "llvm.coro.done",
       "llvm.coro.end",
+      "llvm.coro.end.async",
       "llvm.coro.frame",
       "llvm.coro.free",
       "llvm.coro.id",
@@ -316,11 +317,16 @@ void coro::Shape::buildFrom(Function &F) {
         CoroBegin = CB;
         break;
       }
+      case Intrinsic::coro_end_async:
       case Intrinsic::coro_end:
-        CoroEnds.push_back(cast<CoroEndInst>(II));
-        if (CoroEnds.back()->isFallthrough()) {
+        CoroEnds.push_back(cast<AnyCoroEndInst>(II));
+        if (auto *AsyncEnd = dyn_cast<CoroAsyncEndInst>(II)) {
+          AsyncEnd->checkWellFormed();
+        }
+        if (CoroEnds.back()->isFallthrough() && isa<CoroEndInst>(II)) {
           // Make sure that the fallthrough coro.end is the first element in the
           // CoroEnds vector.
+          // Note: I don't think this is neccessary anymore.
           if (CoroEnds.size() > 1) {
             if (CoroEnds.front()->isFallthrough())
               report_fatal_error(
@@ -353,7 +359,7 @@ void coro::Shape::buildFrom(Function &F) {
     }
 
     // Replace all coro.ends with unreachable instruction.
-    for (CoroEndInst *CE : CoroEnds)
+    for (AnyCoroEndInst *CE : CoroEnds)
       changeToUnreachable(CE, /*UseLLVMTrap=*/false);
 
     return;
@@ -713,6 +719,19 @@ void CoroSuspendAsyncInst::checkWellFormed() const {
   checkAsyncContextProjectFunction(this, getAsyncContextProjectionFunction());
 }
 
+void CoroAsyncEndInst::checkWellFormed() const {
+  auto *MustTailCallFunc = getMustTailCallFunction();
+  if (!MustTailCallFunc)
+    return;
+  auto *FnTy =
+      cast<FunctionType>(MustTailCallFunc->getType()->getPointerElementType());
+  if (FnTy->getNumParams() != (getNumArgOperands() - 3))
+    fail(this,
+         "llvm.coro.end.async must tail call function argument type must "
+         "match the tail arguments",
+         MustTailCallFunc);
+}
+
 void LLVMAddCoroEarlyPass(LLVMPassManagerRef PM) {
   unwrap(PM)->add(createCoroEarlyLegacyPass());
 }
diff --git a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
index 260eb437a64a1..11c8d3b7a8d69 100644
--- a/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
+++ b/llvm/lib/Transforms/IPO/ArgumentPromotion.cpp
@@ -142,7 +142,7 @@ doPromotion(Function *F, SmallPtrSetImpl<Argument *> &ArgsToPromote,
       // Simple byval argument? Just add all the struct element types.
       Type *AgTy = cast<PointerType>(I->getType())->getElementType();
       StructType *STy = cast<StructType>(AgTy);
-      Params.insert(Params.end(), STy->element_begin(), STy->element_end());
+      llvm::append_range(Params, STy->elements());
       ArgAttrVec.insert(ArgAttrVec.end(), STy->getNumElements(),
                         AttributeSet());
       ++NumByValArgsPromoted;
@@ -825,7 +825,7 @@ static bool canPaddingBeAccessed(Argument *arg) {
     WorkList.pop_back();
     if (isa<GetElementPtrInst>(V) || isa<PHINode>(V)) {
       if (PtrValues.insert(V).second)
-        WorkList.insert(WorkList.end(), V->user_begin(), V->user_end());
+        llvm::append_range(WorkList, V->users());
     } else if (StoreInst *Store = dyn_cast<StoreInst>(V)) {
       Stores.push_back(Store);
     } else if (!isa<LoadInst>(V)) {
diff --git a/llvm/lib/Transforms/IPO/IROutliner.cpp b/llvm/lib/Transforms/IPO/IROutliner.cpp
index 4031eedced7c1..12a30744a6525 100644
--- a/llvm/lib/Transforms/IPO/IROutliner.cpp
+++ b/llvm/lib/Transforms/IPO/IROutliner.cpp
@@ -211,6 +211,8 @@ static bool
 collectRegionsConstants(OutlinableRegion &Region,
                         DenseMap<unsigned, Constant *> &GVNToConstant,
                         DenseSet<unsigned> &NotSame) {
+  bool ConstantsTheSame = true;
+
   IRSimilarityCandidate &C = *Region.Candidate;
   for (IRInstructionData &ID : C) {
 
@@ -222,11 +224,10 @@ collectRegionsConstants(OutlinableRegion &Region,
       assert(GVNOpt.hasValue() && "Expected a GVN for operand?");
       unsigned GVN = GVNOpt.getValue();
 
-      // If this global value has been found to not be the same, it could have
-      // just been a register, check that it is not a constant value.
+      // Check if this global value has been found to not be the same already.
       if (NotSame.find(GVN) != NotSame.end()) {
         if (isa<Constant>(V))
-          return false;
+          ConstantsTheSame = false;
         continue;
       }
 
@@ -239,30 +240,27 @@ collectRegionsConstants(OutlinableRegion &Region,
         if (ConstantMatches.getValue())
           continue;
         else
-          return false;
+          ConstantsTheSame = false;
       }
 
       // While this value is a register, it might not have been previously,
       // make sure we don't already have a constant mapped to this global value
       // number.
       if (GVNToConstant.find(GVN) != GVNToConstant.end())
-        return false;
+        ConstantsTheSame = false;
 
       NotSame.insert(GVN);
     }
   }
 
-  return true;
+  return ConstantsTheSame;
 }
 
 void OutlinableGroup::findSameConstants(DenseSet<unsigned> &NotSame) {
   DenseMap<unsigned, Constant *> GVNToConstant;
 
   for (OutlinableRegion *Region : Regions)
-    if (!collectRegionsConstants(*Region, GVNToConstant, NotSame)) {
-      IgnoreGroup = true;
-      return;
-    }
+    collectRegionsConstants(*Region, GVNToConstant, NotSame);
 }
 
 Function *IROutliner::createFunction(Module &M, OutlinableGroup &Group,
@@ -299,7 +297,7 @@ static BasicBlock *moveFunctionData(Function &Old, Function &New) {
     CurrBB->removeFromParent();
     CurrBB->insertInto(&New);
     Instruction *I = CurrBB->getTerminator();
-    if (ReturnInst *RI = dyn_cast<ReturnInst>(I))
+    if (isa<ReturnInst>(I))
       NewEnd = &(*CurrBB);
   }
 
@@ -307,16 +305,44 @@ static BasicBlock *moveFunctionData(Function &Old, Function &New) {
   return NewEnd;
 }
 
-/// Find the GVN for the inputs that have been found by the CodeExtractor,
-/// excluding the ones that will be removed by llvm.assumes as these will be
-/// removed by the CodeExtractor.
+/// Find the the constants that will need to be lifted into arguments
+/// as they are not the same in each instance of the region.
+///
+/// \param [in] C - The IRSimilarityCandidate containing the region we are
+/// analyzing.
+/// \param [in] NotSame - The set of global value numbers that do not have a
+/// single Constant across all OutlinableRegions similar to \p C.
+/// \param [out] Inputs - The list containing the global value numbers of the
+/// arguments needed for the region of code.
+static void findConstants(IRSimilarityCandidate &C, DenseSet<unsigned> &NotSame,
+                          std::vector<unsigned> &Inputs) {
+  DenseSet<unsigned> Seen;
+  // Iterate over the instructions, and find what constants will need to be
+  // extracted into arguments.
+  for (IRInstructionDataList::iterator IDIt = C.begin(), EndIDIt = C.end();
+       IDIt != EndIDIt; IDIt++) {
+    for (Value *V : (*IDIt).OperVals) {
+      // Since these are stored before any outlining, they will be in the
+      // global value numbering.
+      unsigned GVN = C.getGVN(V).getValue();
+      if (isa<Constant>(V))
+        if (NotSame.find(GVN) != NotSame.end() &&
+            Seen.find(GVN) == Seen.end()) {
+          Inputs.push_back(GVN);
+          Seen.insert(GVN);
+        }
+    }
+  }
+}
+
+/// Find the GVN for the inputs that have been found by the CodeExtractor.
 ///
 /// \param [in] C - The IRSimilarityCandidate containing the region we are
 /// analyzing.
 /// \param [in] CurrentInputs - The set of inputs found by the
 /// CodeExtractor.
-/// \param [out] CurrentInputNumbers - The global value numbers for the
-/// extracted arguments.
+/// \param [out] EndInputNumbers - The global value numbers for the extracted
+/// arguments.
 static void mapInputsToGVNs(IRSimilarityCandidate &C,
                             SetVector<Value *> &CurrentInputs,
                             std::vector<unsigned> &EndInputNumbers) {
@@ -332,16 +358,20 @@ static void mapInputsToGVNs(IRSimilarityCandidate &C,
 /// Find the input GVNs and the output values for a region of Instructions.
 /// Using the code extractor, we collect the inputs to the extracted function.
 ///
-/// The \p Region can be identifed as needing to be ignored in this function.
+/// The \p Region can be identified as needing to be ignored in this function.
 /// It should be checked whether it should be ignored after a call to this
 /// function.
 ///
 /// \param [in,out] Region - The region of code to be analyzed.
 /// \param [out] InputGVNs - The global value numbers for the extracted
 /// arguments.
+/// \param [in] NotSame - The global value numbers in the region that do not
+/// have the same constant value in the regions structurally similar to
+/// \p Region.
 /// \param [out] ArgInputs - The values of the inputs to the extracted function.
 static void getCodeExtractorArguments(OutlinableRegion &Region,
                                       std::vector<unsigned> &InputGVNs,
+                                      DenseSet<unsigned> &NotSame,
                                       SetVector<Value *> &ArgInputs) {
   IRSimilarityCandidate &C = *Region.Candidate;
 
@@ -389,13 +419,18 @@ static void getCodeExtractorArguments(OutlinableRegion &Region,
     return;
   }
 
+  findConstants(C, NotSame, InputGVNs);
   mapInputsToGVNs(C, OverallInputs, InputGVNs);
+
+  // Sort the GVNs, since we now have constants included in the \ref InputGVNs
+  // we need to make sure they are in a deterministic order.
+  stable_sort(InputGVNs.begin(), InputGVNs.end());
 }
 
 /// Look over the inputs and map each input argument to an argument in the
-/// overall function for the regions.  This creates a way to replace the
-/// arguments of the extracted function, with the arguments of the new overall
-/// function.
+/// overall function for the OutlinableRegions.  This creates a way to replace
+/// the arguments of the extracted function with the arguments of the new
+/// overall function.
 ///
 /// \param [in,out] Region - The region of code to be analyzed.
 /// \param [in] InputsGVNs - The global value numbering of the input values
@@ -417,7 +452,10 @@ findExtractedInputToOverallInputMapping(OutlinableRegion &Region,
   unsigned OriginalIndex = 0;
 
   // Find the mapping of the extracted arguments to the arguments for the
-  // overall function.
+  // overall function. Since there may be extra arguments in the overall
+  // function to account for the extracted constants, we have two different
+  // counters as we find extracted arguments, and as we come across overall
+  // arguments.
   for (unsigned InputVal : InputGVNs) {
     Optional<Value *> InputOpt = C.fromGVN(InputVal);
     assert(InputOpt.hasValue() && "Global value number not found?");
@@ -426,11 +464,17 @@ findExtractedInputToOverallInputMapping(OutlinableRegion &Region,
     if (!Group.InputTypesSet)
       Group.ArgumentTypes.push_back(Input->getType());
 
-    // It is not a constant, check if it is a sunken alloca.  If it is not,
-    // create the mapping from extracted to overall.  If it is, create the
-    // mapping of the index to the value.
-    unsigned Found = ArgInputs.count(Input);
-    assert(Found && "Input cannot be found!");
+    // Check if we have a constant. If we do add it to the overall argument
+    // number to Constant map for the region, and continue to the next input.
+    if (Constant *CST = dyn_cast<Constant>(Input)) {
+      Region.AggArgToConstant.insert(std::make_pair(TypeIndex, CST));
+      TypeIndex++;
+      continue;
+    }
+
+    // It is not a constant, we create the mapping from extracted argument list
+    // to the overall argument list.
+    assert(ArgInputs.count(Input) && "Input cannot be found!");
 
     Region.ExtractedArgToAgg.insert(std::make_pair(OriginalIndex, TypeIndex));
     Region.AggArgToExtracted.insert(std::make_pair(TypeIndex, OriginalIndex));
@@ -438,10 +482,10 @@ findExtractedInputToOverallInputMapping(OutlinableRegion &Region,
     TypeIndex++;
   }
 
-  // If we do not have definitions for the OutlinableGroup holding the region,
-  // set the length of the inputs here.  We should have the same inputs for
-  // all of the different regions contained in the OutlinableGroup since they
-  // are all structurally similar to one another
+  // If the function type definitions for the OutlinableGroup holding the region
+  // have not been set, set the length of the inputs here.  We should have the
+  // same inputs for all of the different regions contained in the
+  // OutlinableGroup since they are all structurally similar to one another.
   if (!Group.InputTypesSet) {
     Group.NumAggregateInputs = TypeIndex;
     Group.InputTypesSet = true;
@@ -450,11 +494,12 @@ findExtractedInputToOverallInputMapping(OutlinableRegion &Region,
   Region.NumExtractedInputs = OriginalIndex;
 }
 
-void IROutliner::findAddInputsOutputs(Module &M, OutlinableRegion &Region) {
+void IROutliner::findAddInputsOutputs(Module &M, OutlinableRegion &Region,
+                                      DenseSet<unsigned> &NotSame) {
   std::vector<unsigned> Inputs;
   SetVector<Value *> ArgInputs;
 
-  getCodeExtractorArguments(Region, Inputs, ArgInputs);
+  getCodeExtractorArguments(Region, Inputs, NotSame, ArgInputs);
 
   if (Region.IgnoreRegion)
     return;
@@ -486,12 +531,72 @@ CallInst *replaceCalledFunction(Module &M, OutlinableRegion &Region) {
   // If the arguments are the same size, there are not values that need to be
   // made argument, or different output registers to handle.  We can simply
   // replace the called function in this case.
-  assert(AggFunc->arg_size() == Call->arg_size() &&
-         "Can only replace calls with the same number of arguments!");
+  if (AggFunc->arg_size() == Call->arg_size()) {
+    LLVM_DEBUG(dbgs() << "Replace call to " << *Call << " with call to "
+                      << *AggFunc << " with same number of arguments\n");
+    Call->setCalledFunction(AggFunc);
+    return Call;
+  }
+
+  // We have a different number of arguments than the new function, so
+  // we need to use our previously mappings off extracted argument to overall
+  // function argument, and constants to overall function argument to create the
+  // new argument list.
+  for (unsigned AggArgIdx = 0; AggArgIdx < AggFunc->arg_size(); AggArgIdx++) {
+
+    ArgPair = Region.AggArgToExtracted.find(AggArgIdx);
+    if (ArgPair != Region.AggArgToExtracted.end()) {
+      Value *ArgumentValue = Call->getArgOperand(ArgPair->second);
+      // If we found the mapping from the extracted function to the overall
+      // function, we simply add it to the argument list.  We use the same
+      // value, it just needs to honor the new order of arguments.
+      LLVM_DEBUG(dbgs() << "Setting argument " << AggArgIdx << " to value "
+                        << *ArgumentValue << "\n");
+      NewCallArgs.push_back(ArgumentValue);
+      continue;
+    }
+
+    // If it is a constant, we simply add it to the argument list as a value.
+    if (Region.AggArgToConstant.find(AggArgIdx) !=
+        Region.AggArgToConstant.end()) {
+      Constant *CST = Region.AggArgToConstant.find(AggArgIdx)->second;
+      LLVM_DEBUG(dbgs() << "Setting argument " << AggArgIdx << " to value "
+                        << *CST << "\n");
+      NewCallArgs.push_back(CST);
+      continue;
+    }
+
+    // Add a nullptr value if the argument is not found in the extracted
+    // function.  If we cannot find a value, it means it is not in use
+    // for the region, so we should not pass anything to it.
+    LLVM_DEBUG(dbgs() << "Setting argument " << AggArgIdx << " to nullptr\n");
+    NewCallArgs.push_back(ConstantPointerNull::get(
+        static_cast<PointerType *>(AggFunc->getArg(AggArgIdx)->getType())));
+  }
 
   LLVM_DEBUG(dbgs() << "Replace call to " << *Call << " with call to "
-                    << *AggFunc << " with same number of arguments\n");
-  Call->setCalledFunction(AggFunc);
+                    << *AggFunc << " with new set of arguments\n");
+  // Create the new call instruction and erase the old one.
+  Call = CallInst::Create(AggFunc->getFunctionType(), AggFunc, NewCallArgs, "",
+                          Call);
+
+  // It is possible that the call to the outlined function is either the first
+  // instruction in the new block, the last instruction, or both.  If either of
+  // these is the case, we need to make sure that we replace the instruction in
+  // the IRInstructionData struct with the new call.
+  CallInst *OldCall = Region.Call;
+  if (Region.NewFront->Inst == OldCall)
+    Region.NewFront->Inst = Call;
+  if (Region.NewBack->Inst == OldCall)
+    Region.NewBack->Inst = Call;
+
+  // Transfer any debug information.
+  Call->setDebugLoc(Region.Call->getDebugLoc());
+
+  // Remove the old instruction.
+  OldCall->eraseFromParent();
+  Region.Call = Call;
+
   return Call;
 }
 
@@ -520,6 +625,37 @@ static void replaceArgumentUses(OutlinableRegion &Region) {
   }
 }
 
+/// Within an extracted function, replace the constants that need to be lifted
+/// into arguments with the actual argument.
+///
+/// \param Region [in] - The region of extracted code to be changed.
+void replaceConstants(OutlinableRegion &Region) {
+  OutlinableGroup &Group = *Region.Parent;
+  // Iterate over the constants that need to be elevated into arguments
+  for (std::pair<unsigned, Constant *> &Const : Region.AggArgToConstant) {
+    unsigned AggArgIdx = Const.first;
+    Function *OutlinedFunction = Group.OutlinedFunction;
+    assert(OutlinedFunction && "Overall Function is not defined?");
+    Constant *CST = Const.second;
+    Argument *Arg = Group.OutlinedFunction->getArg(AggArgIdx);
+    // Identify the argument it will be elevated to, and replace instances of
+    // that constant in the function.
+
+    // TODO: If in the future constants do not have one global value number,
+    // i.e. a constant 1 could be mapped to several values, this check will
+    // have to be more strict.  It cannot be using only replaceUsesWithIf.
+
+    LLVM_DEBUG(dbgs() << "Replacing uses of constant " << *CST
+                      << " in function " << *OutlinedFunction << " with "
+                      << *Arg << "\n");
+    CST->replaceUsesWithIf(Arg, [OutlinedFunction](Use &U) {
+      if (Instruction *I = dyn_cast<Instruction>(U.getUser()))
+        return I->getFunction() == OutlinedFunction;
+      return false;
+    });
+  }
+}
+
 /// Fill the new function that will serve as the replacement function for all of
 /// the extracted regions of a certain structure from the first region in the
 /// list of regions.  Replace this first region's extracted function with the
@@ -546,6 +682,7 @@ static void fillOverallFunction(Module &M, OutlinableGroup &CurrentGroup,
     CurrentGroup.OutlinedFunction->addFnAttr(A);
 
   replaceArgumentUses(*CurrentOS);
+  replaceConstants(*CurrentOS);
 
   // Replace the call to the extracted function with the outlined function.
   CurrentOS->Call = replaceCalledFunction(M, *CurrentOS);
@@ -740,7 +877,7 @@ unsigned IROutliner::doOutline(Module &M) {
       OS->CE = new (ExtractorAllocator.Allocate())
           CodeExtractor(BE, nullptr, false, nullptr, nullptr, nullptr, false,
                         false, "outlined");
-      findAddInputsOutputs(M, *OS);
+      findAddInputsOutputs(M, *OS, NotSame);
       if (!OS->IgnoreRegion)
         OutlinedRegions.push_back(OS);
       else
diff --git a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
index 17ffb27efa5a5..8bd3036f1fc34 100644
--- a/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
+++ b/llvm/lib/Transforms/IPO/LowerTypeTests.cpp
@@ -198,7 +198,7 @@ void GlobalLayoutBuilder::addFragment(const std::set<uint64_t> &F) {
       // indices from the old fragment in this fragment do not insert any more
       // indices.
       std::vector<uint64_t> &OldFragment = Fragments[OldFragmentIndex];
-      Fragment.insert(Fragment.end(), OldFragment.begin(), OldFragment.end());
+      llvm::append_range(Fragment, OldFragment);
       OldFragment.clear();
     }
   }
diff --git a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
index 5c3d060f4ba1e..9e962a2e0d689 100644
--- a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
+++ b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
@@ -1289,7 +1289,7 @@ void DevirtModule::applyICallBranchFunnel(VTableSlotInfo &SlotInfo,
       IRBuilder<> IRB(&CB);
       std::vector<Value *> Args;
       Args.push_back(IRB.CreateBitCast(VCallSite.VTable, Int8PtrTy));
-      Args.insert(Args.end(), CB.arg_begin(), CB.arg_end());
+      llvm::append_range(Args, CB.args());
 
       CallBase *NewCS = nullptr;
       if (isa<CallInst>(CB))
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index 74ba23d343a0e..c20861f20f07f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -1841,7 +1841,7 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
     Constant *C2;
 
     // C-(C2-X) --> X+(C-C2)
-    if (match(Op1, m_Sub(m_Constant(C2), m_Value(X))) && !isa<ConstantExpr>(C2))
+    if (match(Op1, m_Sub(m_ImmConstant(C2), m_Value(X))))
       return BinaryOperator::CreateAdd(X, ConstantExpr::getSub(C, C2));
   }
 
@@ -2198,7 +2198,7 @@ Instruction *InstCombinerImpl::visitFSub(BinaryOperator &I) {
   // X - C --> X + (-C)
   // But don't transform constant expressions because there's an inverse fold
   // for X + (-Y) --> X - Y.
-  if (match(Op1, m_Constant(C)) && !isa<ConstantExpr>(Op1))
+  if (match(Op1, m_ImmConstant(C)))
     return BinaryOperator::CreateFAddFMF(Op0, ConstantExpr::getFNeg(C), &I);
 
   // X - (-Y) --> X + Y
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
index 6b5fd571ecf50..c0823c950368f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
@@ -1883,6 +1883,13 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) {
     if (match(Op0, m_OneUse(m_c_Xor(m_Specific(Op1), m_Value(B)))))
       return BinaryOperator::CreateAnd(Op1, Builder.CreateNot(B));
 
+    // A & ~(A ^ B) --> A & B
+    if (match(Op1, m_Not(m_c_Xor(m_Specific(Op0), m_Value(B)))))
+      return BinaryOperator::CreateAnd(Op0, B);
+    // ~(A ^ B) & A --> A & B
+    if (match(Op0, m_Not(m_c_Xor(m_Specific(Op1), m_Value(B)))))
+      return BinaryOperator::CreateAnd(Op1, B);
+
     // (A ^ B) & ((B ^ C) ^ A) -> (A ^ B) & ~C
     if (match(Op0, m_Xor(m_Value(A), m_Value(B))))
       if (match(Op1, m_Xor(m_Xor(m_Specific(B), m_Value(C)), m_Specific(A))))
@@ -3450,5 +3457,13 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) {
   if (Instruction *NewXor = sinkNotIntoXor(I, Builder))
     return NewXor;
 
+  // Otherwise, if all else failed, try to hoist the xor-by-constant:
+  //   (X ^ C) ^ Y --> (X ^ Y) ^ C
+  // Just like we do in other places, we avoid the fold for constantexprs,
+  // at least to avoid endless combine loop.
+  if (match(&I, m_c_Xor(m_OneUse(m_Xor(m_Value(X), m_ImmConstant(C1))),
+                        m_Value(Y))))
+    return BinaryOperator::CreateXor(Builder.CreateXor(X, Y), C1);
+
   return nullptr;
 }
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
index 22e4fd7d99558..3dc8508aa7603 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
@@ -883,8 +883,8 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
     Type *Ty = II->getType();
     unsigned BitWidth = Ty->getScalarSizeInBits();
     Constant *ShAmtC;
-    if (match(II->getArgOperand(2), m_Constant(ShAmtC)) &&
-        !isa<ConstantExpr>(ShAmtC) && !ShAmtC->containsConstantExpression()) {
+    if (match(II->getArgOperand(2), m_ImmConstant(ShAmtC)) &&
+        !ShAmtC->containsConstantExpression()) {
       // Canonicalize a shift amount constant operand to modulo the bit-width.
       Constant *WidthC = ConstantInt::get(Ty, BitWidth);
       Constant *ModuloC = ConstantExpr::getURem(ShAmtC, WidthC);
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 139b04bb6a811..83b310bfcd053 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -96,45 +96,6 @@ static bool isSignTest(ICmpInst::Predicate &Pred, const APInt &C) {
   return false;
 }
 
-/// Given a signed integer type and a set of known zero and one bits, compute
-/// the maximum and minimum values that could have the specified known zero and
-/// known one bits, returning them in Min/Max.
-/// TODO: Move to method on KnownBits struct?
-static void computeSignedMinMaxValuesFromKnownBits(const KnownBits &Known,
-                                                   APInt &Min, APInt &Max) {
-  assert(Known.getBitWidth() == Min.getBitWidth() &&
-         Known.getBitWidth() == Max.getBitWidth() &&
-         "KnownZero, KnownOne and Min, Max must have equal bitwidth.");
-  APInt UnknownBits = ~(Known.Zero|Known.One);
-
-  // The minimum value is when all unknown bits are zeros, EXCEPT for the sign
-  // bit if it is unknown.
-  Min = Known.One;
-  Max = Known.One|UnknownBits;
-
-  if (UnknownBits.isNegative()) { // Sign bit is unknown
-    Min.setSignBit();
-    Max.clearSignBit();
-  }
-}
-
-/// Given an unsigned integer type and a set of known zero and one bits, compute
-/// the maximum and minimum values that could have the specified known zero and
-/// known one bits, returning them in Min/Max.
-/// TODO: Move to method on KnownBits struct?
-static void computeUnsignedMinMaxValuesFromKnownBits(const KnownBits &Known,
-                                                     APInt &Min, APInt &Max) {
-  assert(Known.getBitWidth() == Min.getBitWidth() &&
-         Known.getBitWidth() == Max.getBitWidth() &&
-         "Ty, KnownZero, KnownOne and Min, Max must have equal bitwidth.");
-  APInt UnknownBits = ~(Known.Zero|Known.One);
-
-  // The minimum value is when the unknown bits are all zeros.
-  Min = Known.One;
-  // The maximum value is when the unknown bits are all ones.
-  Max = Known.One|UnknownBits;
-}
-
 /// This is called when we see this pattern:
 ///   cmp pred (load (gep GV, ...)), cmpcst
 /// where GV is a global variable with a constant initializer. Try to simplify
@@ -5050,11 +5011,15 @@ Instruction *InstCombinerImpl::foldICmpUsingKnownBits(ICmpInst &I) {
   APInt Op0Min(BitWidth, 0), Op0Max(BitWidth, 0);
   APInt Op1Min(BitWidth, 0), Op1Max(BitWidth, 0);
   if (I.isSigned()) {
-    computeSignedMinMaxValuesFromKnownBits(Op0Known, Op0Min, Op0Max);
-    computeSignedMinMaxValuesFromKnownBits(Op1Known, Op1Min, Op1Max);
+    Op0Min = Op0Known.getSignedMinValue();
+    Op0Max = Op0Known.getSignedMaxValue();
+    Op1Min = Op1Known.getSignedMinValue();
+    Op1Max = Op1Known.getSignedMaxValue();
   } else {
-    computeUnsignedMinMaxValuesFromKnownBits(Op0Known, Op0Min, Op0Max);
-    computeUnsignedMinMaxValuesFromKnownBits(Op1Known, Op1Min, Op1Max);
+    Op0Min = Op0Known.getMinValue();
+    Op0Max = Op0Known.getMaxValue();
+    Op1Min = Op1Known.getMinValue();
+    Op1Max = Op1Known.getMaxValue();
   }
 
   // If Min and Max are known to be the same, then SimplifyDemandedBits figured
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
index ac617ecd4fd1b..6bc2a6832abd2 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
@@ -273,12 +273,7 @@ bool PointerReplacer::collectUsers(Instruction &I) {
   return true;
 }
 
-Value *PointerReplacer::getReplacement(Value *V) {
-  auto Loc = WorkMap.find(V);
-  if (Loc != WorkMap.end())
-    return Loc->second;
-  return nullptr;
-}
+Value *PointerReplacer::getReplacement(Value *V) { return WorkMap.lookup(V); }
 
 void PointerReplacer::replace(Instruction *I) {
   if (getReplacement(I))
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
index 5a72547ce519f..494c58e706e17 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp
@@ -220,8 +220,7 @@ LLVM_NODISCARD Value *Negator::visitImpl(Value *V, unsigned Depth) {
   }
 
   if (I->getOpcode() == Instruction::Sub &&
-      (I->hasOneUse() || (isa<Constant>(I->getOperand(0)) &&
-                          !isa<ConstantExpr>(I->getOperand(0))))) {
+      (I->hasOneUse() || match(I->getOperand(0), m_ImmConstant()))) {
     // `sub` is always negatible.
     // However, only do this either if the old `sub` doesn't stick around, or
     // it was subtracting from a constant. Otherwise, this isn't profitable.
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index e05fa4ffa4032..075667629c5f1 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -1058,15 +1058,16 @@ static Instruction *canonicalizeAbsNabs(SelectInst &Sel, ICmpInst &Cmp,
       SPF != SelectPatternFlavor::SPF_NABS)
     return nullptr;
 
-  bool IntMinIsPoison = match(RHS, m_NSWNeg(m_Specific(LHS)));
+  // Note that NSW flag can only be propagated for normal, non-negated abs!
+  bool IntMinIsPoison = SPF == SelectPatternFlavor::SPF_ABS &&
+                        match(RHS, m_NSWNeg(m_Specific(LHS)));
   Constant *IntMinIsPoisonC =
       ConstantInt::get(Type::getInt1Ty(Sel.getContext()), IntMinIsPoison);
   Instruction *Abs =
       IC.Builder.CreateBinaryIntrinsic(Intrinsic::abs, LHS, IntMinIsPoisonC);
 
   if (SPF == SelectPatternFlavor::SPF_NABS)
-    return IntMinIsPoison ? BinaryOperator::CreateNSWNeg(Abs)
-                          : BinaryOperator::CreateNeg(Abs);
+    return BinaryOperator::CreateNeg(Abs); // Always without NSW flag!
 
   return IC.replaceInstUsesWith(Sel, Abs);
 }
@@ -2606,7 +2607,10 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
   // select i1 %c, <2 x i8> <1, 1>, <2 x i8> <0, 0>
   // because that may need 3 instructions to splat the condition value:
   // extend, insertelement, shufflevector.
-  if (SelType->isIntOrIntVectorTy() &&
+  //
+  // Do not handle i1 TrueVal and FalseVal otherwise would result in
+  // zext/sext i1 to i1.
+  if (SelType->isIntOrIntVectorTy() && !SelType->isIntOrIntVectorTy(1) &&
       CondVal->getType()->isVectorTy() == SelType->isVectorTy()) {
     // select C, 1, 0 -> zext C to int
     if (match(TrueVal, m_One()) && match(FalseVal, m_Zero()))
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 5b0a4857f33db..c265516213aa4 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -1021,8 +1021,8 @@ Value *InstCombinerImpl::simplifyShrShlDemandedBits(
 }
 
 /// The specified value produces a vector with any number of elements.
-/// This method analyzes which elements of the operand are undef and returns
-/// that information in UndefElts.
+/// This method analyzes which elements of the operand are undef or poison and
+/// returns that information in UndefElts.
 ///
 /// DemandedElts contains the set of elements that are actually used by the
 /// caller, and by default (AllowMultipleUsers equals false) the value is
@@ -1048,14 +1048,14 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
   assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!");
 
   if (isa<UndefValue>(V)) {
-    // If the entire vector is undefined, just return this info.
+    // If the entire vector is undef or poison, just return this info.
     UndefElts = EltMask;
     return nullptr;
   }
 
-  if (DemandedElts.isNullValue()) { // If nothing is demanded, provide undef.
+  if (DemandedElts.isNullValue()) { // If nothing is demanded, provide poison.
     UndefElts = EltMask;
-    return UndefValue::get(V->getType());
+    return PoisonValue::get(V->getType());
   }
 
   UndefElts = 0;
@@ -1067,11 +1067,11 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
       return nullptr;
 
     Type *EltTy = cast<VectorType>(V->getType())->getElementType();
-    Constant *Undef = UndefValue::get(EltTy);
+    Constant *Poison = PoisonValue::get(EltTy);
     SmallVector<Constant*, 16> Elts;
     for (unsigned i = 0; i != VWidth; ++i) {
-      if (!DemandedElts[i]) {   // If not demanded, set to undef.
-        Elts.push_back(Undef);
+      if (!DemandedElts[i]) {   // If not demanded, set to poison.
+        Elts.push_back(Poison);
         UndefElts.setBit(i);
         continue;
       }
@@ -1079,12 +1079,9 @@ Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
       Constant *Elt = C->getAggregateElement(i);
       if (!Elt) return nullptr;
 
-      if (isa<UndefValue>(Elt)) {   // Already undef.
-        Elts.push_back(Undef);
+      Elts.push_back(Elt);
+      if (isa<UndefValue>(Elt))   // Already undef or poison.
         UndefElts.setBit(i);
-      } else {                               // Otherwise, defined.
-        Elts.push_back(Elt);
-      }
     }
 
     // If we changed the constant, return it.
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index ec932aaf0b9e3..5d8abe14327bb 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1056,7 +1056,7 @@ Instruction *InstCombinerImpl::foldOpIntoPhi(Instruction &I, PHINode *PN) {
   for (unsigned i = 0; i != NumPHIValues; ++i) {
     Value *InVal = PN->getIncomingValue(i);
     // If I is a freeze instruction, count undef as a non-constant.
-    if (isa<Constant>(InVal) && !isa<ConstantExpr>(InVal) &&
+    if (match(InVal, m_ImmConstant()) &&
         (!isa<FreezeInst>(I) || isGuaranteedNotToBeUndefOrPoison(InVal)))
       continue;
 
@@ -1118,7 +1118,7 @@ Instruction *InstCombinerImpl::foldOpIntoPhi(Instruction &I, PHINode *PN) {
       // FalseVInPred versus TrueVInPred. When we have individual nonzero
       // elements in the vector, we will incorrectly fold InC to
       // `TrueVInPred`.
-      if (InC && !isa<ConstantExpr>(InC) && isa<ConstantInt>(InC))
+      if (InC && isa<ConstantInt>(InC))
         InV = InC->isNullValue() ? FalseVInPred : TrueVInPred;
       else {
         // Generate the select in the same block as PN's current incoming block.
@@ -1608,8 +1608,7 @@ Instruction *InstCombinerImpl::foldVectorBinop(BinaryOperator &Inst) {
   if (InstVTy &&
       match(&Inst,
             m_c_BinOp(m_OneUse(m_Shuffle(m_Value(V1), m_Undef(), m_Mask(Mask))),
-                      m_Constant(C))) &&
-      !isa<ConstantExpr>(C) &&
+                      m_ImmConstant(C))) &&
       cast<FixedVectorType>(V1->getType())->getNumElements() <=
           InstVTy->getNumElements()) {
     assert(InstVTy->getScalarType() == V1->getType()->getScalarType() &&
diff --git a/llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp b/llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp
index ab7e0ae9d4a5a..d9416072793a8 100644
--- a/llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp
+++ b/llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp
@@ -260,10 +260,9 @@ class CHRScope {
           if (TailRegionSet.count(Parent))
             return false;
 
-          assert(llvm::find_if(RegInfos,
-                               [&Parent](const RegInfo &RI) {
-                                 return Parent == RI.R;
-                               }) != RegInfos.end() &&
+          assert(llvm::any_of(
+                     RegInfos,
+                     [&Parent](const RegInfo &RI) { return Parent == RI.R; }) &&
                  "Must be in head");
           return true;
         });
@@ -1248,7 +1247,7 @@ SmallVector<CHRScope *, 8> CHR::splitScope(
       SmallVector<CHRScope *, 8> SubSplits = splitScope(
           Sub, Split, &SplitConditionValues, SplitInsertPoint, Output,
           SplitUnhoistables);
-      NewSubs.insert(NewSubs.end(), SubSplits.begin(), SubSplits.end());
+      llvm::append_range(NewSubs, SubSplits);
     }
     Split->Subs = NewSubs;
   }
diff --git a/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
index 597f413e90437..1b14b8d569944 100644
--- a/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp
@@ -581,8 +581,7 @@ class DFSanVisitor : public InstVisitor<DFSanVisitor> {
 DataFlowSanitizer::DataFlowSanitizer(
     const std::vector<std::string> &ABIListFiles) {
   std::vector<std::string> AllABIListFiles(std::move(ABIListFiles));
-  AllABIListFiles.insert(AllABIListFiles.end(), ClABIListFiles.begin(),
-                         ClABIListFiles.end());
+  llvm::append_range(AllABIListFiles, ClABIListFiles);
   // FIXME: should we propagate vfs::FileSystem to this constructor?
   ABIList.set(
       SpecialCaseList::createOrDie(AllABIListFiles, *vfs::getRealFileSystem()));
diff --git a/llvm/lib/Transforms/Scalar/EarlyCSE.cpp b/llvm/lib/Transforms/Scalar/EarlyCSE.cpp
index be28609605002..f005f69519f74 100644
--- a/llvm/lib/Transforms/Scalar/EarlyCSE.cpp
+++ b/llvm/lib/Transforms/Scalar/EarlyCSE.cpp
@@ -1033,9 +1033,14 @@ bool EarlyCSE::handleBranchCondition(Instruction *CondInst,
   auto *TorF = (BI->getSuccessor(0) == BB)
                    ? ConstantInt::getTrue(BB->getContext())
                    : ConstantInt::getFalse(BB->getContext());
-  auto MatchBinOp = [](Instruction *I, unsigned Opcode) {
-    if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(I))
-      return BOp->getOpcode() == Opcode;
+  auto MatchBinOp = [](Instruction *I, unsigned Opcode, Value *&LHS,
+                       Value *&RHS) {
+    if (Opcode == Instruction::And &&
+        match(I, m_LogicalAnd(m_Value(LHS), m_Value(RHS))))
+      return true;
+    else if (Opcode == Instruction::Or &&
+             match(I, m_LogicalOr(m_Value(LHS), m_Value(RHS))))
+      return true;
     return false;
   };
   // If the condition is AND operation, we can propagate its operands into the
@@ -1066,8 +1071,9 @@ bool EarlyCSE::handleBranchCondition(Instruction *CondInst,
       }
     }
 
-    if (MatchBinOp(Curr, PropagateOpcode))
-      for (auto &Op : cast<BinaryOperator>(Curr)->operands())
+    Value *LHS, *RHS;
+    if (MatchBinOp(Curr, PropagateOpcode, LHS, RHS))
+      for (auto &Op : { LHS, RHS })
         if (Instruction *OPI = dyn_cast<Instruction>(Op))
           if (SimpleValue::canHandle(OPI) && Visited.insert(OPI).second)
             WorkList.push_back(OPI);
diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp
index 32b38fd97f31a..30d00758c6621 100644
--- a/llvm/lib/Transforms/Scalar/GVN.cpp
+++ b/llvm/lib/Transforms/Scalar/GVN.cpp
@@ -1472,13 +1472,14 @@ bool GVN::processNonLocalLoad(LoadInst *LI) {
     return false;
   }
 
+  bool Changed = false;
   // If this load follows a GEP, see if we can PRE the indices before analyzing.
   if (GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(LI->getOperand(0))) {
     for (GetElementPtrInst::op_iterator OI = GEP->idx_begin(),
                                         OE = GEP->idx_end();
          OI != OE; ++OI)
       if (Instruction *I = dyn_cast<Instruction>(OI->get()))
-        performScalarPRE(I);
+        Changed |= performScalarPRE(I);
   }
 
   // Step 2: Analyze the availability of the load
@@ -1489,7 +1490,7 @@ bool GVN::processNonLocalLoad(LoadInst *LI) {
   // If we have no predecessors that produce a known value for this load, exit
   // early.
   if (ValuesPerBlock.empty())
-    return false;
+    return Changed;
 
   // Step 3: Eliminate fully redundancy.
   //
@@ -1521,12 +1522,12 @@ bool GVN::processNonLocalLoad(LoadInst *LI) {
 
   // Step 4: Eliminate partial redundancy.
   if (!isPREEnabled() || !isLoadPREEnabled())
-    return false;
+    return Changed;
   if (!isLoadInLoopPREEnabled() && this->LI &&
       this->LI->getLoopFor(LI->getParent()))
-    return false;
+    return Changed;
 
-  return PerformLoadPRE(LI, ValuesPerBlock, UnavailableBlocks);
+  return Changed || PerformLoadPRE(LI, ValuesPerBlock, UnavailableBlocks);
 }
 
 static bool impliesEquivalanceIfTrue(CmpInst* Cmp) {
@@ -2087,8 +2088,8 @@ bool GVN::propagateEquality(Value *LHS, Value *RHS, const BasicBlockEdge &Root,
     // If "A && B" is known true then both A and B are known true.  If "A || B"
     // is known false then both A and B are known false.
     Value *A, *B;
-    if ((isKnownTrue && match(LHS, m_And(m_Value(A), m_Value(B)))) ||
-        (isKnownFalse && match(LHS, m_Or(m_Value(A), m_Value(B))))) {
+    if ((isKnownTrue && match(LHS, m_LogicalAnd(m_Value(A), m_Value(B)))) ||
+        (isKnownFalse && match(LHS, m_LogicalOr(m_Value(A), m_Value(B))))) {
       Worklist.push_back(std::make_pair(A, RHS));
       Worklist.push_back(std::make_pair(B, RHS));
       continue;
diff --git a/llvm/lib/Transforms/Scalar/GuardWidening.cpp b/llvm/lib/Transforms/Scalar/GuardWidening.cpp
index b09def442d7a1..1735266f0e58e 100644
--- a/llvm/lib/Transforms/Scalar/GuardWidening.cpp
+++ b/llvm/lib/Transforms/Scalar/GuardWidening.cpp
@@ -671,8 +671,7 @@ bool GuardWideningImpl::combineRangeChecks(
     assert(CurrentChecks.size() != 0 && "We know we have at least one!");
 
     if (CurrentChecks.size() < 3) {
-      RangeChecksOut.insert(RangeChecksOut.end(), CurrentChecks.begin(),
-                            CurrentChecks.end());
+      llvm::append_range(RangeChecksOut, CurrentChecks);
       continue;
     }
 
diff --git a/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp b/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
index 15d1e8da5baaf..3612f8cc1a712 100644
--- a/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
@@ -47,6 +47,7 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/Analysis/CmpInstAnalysis.h"
 #include "llvm/Analysis/LoopAccessAnalysis.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/LoopPass.h"
@@ -79,6 +80,7 @@
 #include "llvm/IR/LLVMContext.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/PassManager.h"
+#include "llvm/IR/PatternMatch.h"
 #include "llvm/IR/Type.h"
 #include "llvm/IR/User.h"
 #include "llvm/IR/Value.h"
@@ -106,6 +108,9 @@ using namespace llvm;
 
 STATISTIC(NumMemSet, "Number of memset's formed from loop stores");
 STATISTIC(NumMemCpy, "Number of memcpy's formed from loop load+stores");
+STATISTIC(
+    NumShiftUntilBitTest,
+    "Number of uncountable loops recognized as 'shift until bitttest' idiom");
 
 bool DisableLIRP::All;
 static cl::opt<bool, true>
@@ -227,6 +232,8 @@ class LoopIdiomRecognize {
                                 const DebugLoc &DL, bool ZeroCheck,
                                 bool IsCntPhiUsedOutsideLoop);
 
+  bool recognizeShiftUntilBitTest();
+
   /// @}
 };
 
@@ -1228,7 +1235,8 @@ bool LoopIdiomRecognize::runOnNoncountableLoop() {
                     << "] Noncountable Loop %"
                     << CurLoop->getHeader()->getName() << "\n");
 
-  return recognizePopcount() || recognizeAndInsertFFS();
+  return recognizePopcount() || recognizeAndInsertFFS() ||
+         recognizeShiftUntilBitTest();
 }
 
 /// Check if the given conditional branch is based on the comparison between
@@ -1911,3 +1919,343 @@ void LoopIdiomRecognize::transformLoopToPopcount(BasicBlock *PreCondBB,
   //   loop. The loop would otherwise not be deleted even if it becomes empty.
   SE->forgetLoop(CurLoop);
 }
+
+/// Match loop-invariant value.
+template <typename SubPattern_t> struct match_LoopInvariant {
+  SubPattern_t SubPattern;
+  const Loop *L;
+
+  match_LoopInvariant(const SubPattern_t &SP, const Loop *L)
+      : SubPattern(SP), L(L) {}
+
+  template <typename ITy> bool match(ITy *V) {
+    return L->isLoopInvariant(V) && SubPattern.match(V);
+  }
+};
+
+/// Matches if the value is loop-invariant.
+template <typename Ty>
+inline match_LoopInvariant<Ty> m_LoopInvariant(const Ty &M, const Loop *L) {
+  return match_LoopInvariant<Ty>(M, L);
+}
+
+/// Return true if the idiom is detected in the loop.
+///
+/// The core idiom we are trying to detect is:
+/// \code
+///   entry:
+///     <...>
+///     %bitmask = shl i32 1, %bitpos
+///     br label %loop
+///
+///   loop:
+///     %x.curr = phi i32 [ %x, %entry ], [ %x.next, %loop ]
+///     %x.curr.bitmasked = and i32 %x.curr, %bitmask
+///     %x.curr.isbitunset = icmp eq i32 %x.curr.bitmasked, 0
+///     %x.next = shl i32 %x.curr, 1
+///     <...>
+///     br i1 %x.curr.isbitunset, label %loop, label %end
+///
+///   end:
+///     %x.curr.res = phi i32 [ %x.curr, %loop ] <...>
+///     %x.next.res = phi i32 [ %x.next, %loop ] <...>
+///     <...>
+/// \endcode
+static bool detectShiftUntilBitTestIdiom(Loop *CurLoop, Value *&BaseX,
+                                         Value *&BitMask, Value *&BitPos,
+                                         Value *&CurrX, Instruction *&NextX) {
+  LLVM_DEBUG(dbgs() << DEBUG_TYPE
+             " Performing shift-until-bittest idiom detection.\n");
+
+  // Give up if the loop has multiple blocks or multiple backedges.
+  if (CurLoop->getNumBlocks() != 1 || CurLoop->getNumBackEdges() != 1) {
+    LLVM_DEBUG(dbgs() << DEBUG_TYPE " Bad block/backedge count.\n");
+    return false;
+  }
+
+  BasicBlock *LoopHeaderBB = CurLoop->getHeader();
+  BasicBlock *LoopPreheaderBB = CurLoop->getLoopPreheader();
+  assert(LoopPreheaderBB && "There is always a loop preheader.");
+
+  using namespace PatternMatch;
+
+  // Step 1: Check if the loop backedge is in desirable form.
+
+  ICmpInst::Predicate Pred;
+  Value *CmpLHS, *CmpRHS;
+  BasicBlock *TrueBB, *FalseBB;
+  if (!match(LoopHeaderBB->getTerminator(),
+             m_Br(m_ICmp(Pred, m_Value(CmpLHS), m_Value(CmpRHS)),
+                  m_BasicBlock(TrueBB), m_BasicBlock(FalseBB)))) {
+    LLVM_DEBUG(dbgs() << DEBUG_TYPE " Bad backedge structure.\n");
+    return false;
+  }
+
+  // Step 2: Check if the backedge's condition is in desirable form.
+
+  auto MatchVariableBitMask = [&]() {
+    return ICmpInst::isEquality(Pred) && match(CmpRHS, m_Zero()) &&
+           match(CmpLHS,
+                 m_c_And(m_Value(CurrX),
+                         m_CombineAnd(
+                             m_Value(BitMask),
+                             m_LoopInvariant(m_Shl(m_One(), m_Value(BitPos)),
+                                             CurLoop))));
+  };
+  auto MatchConstantBitMask = [&]() {
+    return ICmpInst::isEquality(Pred) && match(CmpRHS, m_Zero()) &&
+           match(CmpLHS, m_And(m_Value(CurrX),
+                               m_CombineAnd(m_Value(BitMask), m_Power2()))) &&
+           (BitPos = ConstantExpr::getExactLogBase2(cast<Constant>(BitMask)));
+  };
+  auto MatchDecomposableConstantBitMask = [&]() {
+    APInt Mask;
+    return llvm::decomposeBitTestICmp(CmpLHS, CmpRHS, Pred, CurrX, Mask) &&
+           ICmpInst::isEquality(Pred) && Mask.isPowerOf2() &&
+           (BitMask = ConstantInt::get(CurrX->getType(), Mask)) &&
+           (BitPos = ConstantInt::get(CurrX->getType(), Mask.logBase2()));
+  };
+
+  if (!MatchVariableBitMask() && !MatchConstantBitMask() &&
+      !MatchDecomposableConstantBitMask()) {
+    LLVM_DEBUG(dbgs() << DEBUG_TYPE " Bad backedge comparison.\n");
+    return false;
+  }
+
+  // Step 3: Check if the recurrence is in desirable form.
+  auto *CurrXPN = dyn_cast<PHINode>(CurrX);
+  if (!CurrXPN) {
+    LLVM_DEBUG(dbgs() << DEBUG_TYPE " Not a PHI node.\n");
+    return false;
+  }
+
+  BaseX = CurrXPN->getIncomingValueForBlock(LoopPreheaderBB);
+  NextX =
+      dyn_cast<Instruction>(CurrXPN->getIncomingValueForBlock(LoopHeaderBB));
+
+  if (!NextX || !match(NextX, m_Shl(m_Specific(CurrX), m_One()))) {
+    // FIXME: support right-shift?
+    LLVM_DEBUG(dbgs() << DEBUG_TYPE " Bad recurrence.\n");
+    return false;
+  }
+
+  // Step 4: Check if the backedge's destinations are in desirable form.
+
+  assert(ICmpInst::isEquality(Pred) &&
+         "Should only get equality predicates here.");
+
+  // cmp-br is commutative, so canonicalize to a single variant.
+  if (Pred != ICmpInst::Predicate::ICMP_EQ) {
+    Pred = ICmpInst::getInversePredicate(Pred);
+    std::swap(TrueBB, FalseBB);
+  }
+
+  // We expect to exit loop when comparison yields false,
+  // so when it yields true we should branch back to loop header.
+  if (TrueBB != LoopHeaderBB) {
+    LLVM_DEBUG(dbgs() << DEBUG_TYPE " Bad backedge flow.\n");
+    return false;
+  }
+
+  // Okay, idiom checks out.
+  return true;
+}
+
+/// Look for the following loop:
+/// \code
+///   entry:
+///     <...>
+///     %bitmask = shl i32 1, %bitpos
+///     br label %loop
+///
+///   loop:
+///     %x.curr = phi i32 [ %x, %entry ], [ %x.next, %loop ]
+///     %x.curr.bitmasked = and i32 %x.curr, %bitmask
+///     %x.curr.isbitunset = icmp eq i32 %x.curr.bitmasked, 0
+///     %x.next = shl i32 %x.curr, 1
+///     <...>
+///     br i1 %x.curr.isbitunset, label %loop, label %end
+///
+///   end:
+///     %x.curr.res = phi i32 [ %x.curr, %loop ] <...>
+///     %x.next.res = phi i32 [ %x.next, %loop ] <...>
+///     <...>
+/// \endcode
+///
+/// And transform it into:
+/// \code
+///   entry:
+///     %bitmask = shl i32 1, %bitpos
+///     %lowbitmask = add i32 %bitmask, -1
+///     %mask = or i32 %lowbitmask, %bitmask
+///     %x.masked = and i32 %x, %mask
+///     %x.masked.numleadingzeros = call i32 @llvm.ctlz.i32(i32 %x.masked,
+///                                                         i1 true)
+///     %x.masked.numactivebits = sub i32 32, %x.masked.numleadingzeros
+///     %x.masked.leadingonepos = add i32 %x.masked.numactivebits, -1
+///     %backedgetakencount = sub i32 %bitpos, %x.masked.leadingonepos
+///     %tripcount = add i32 %backedgetakencount, 1
+///     %x.curr = shl i32 %x, %backedgetakencount
+///     %x.next = shl i32 %x, %tripcount
+///     br label %loop
+///
+///   loop:
+///     %loop.iv = phi i32 [ 0, %entry ], [ %loop.iv.next, %loop ]
+///     %loop.iv.next = add nuw i32 %loop.iv, 1
+///     %loop.ivcheck = icmp eq i32 %loop.iv.next, %tripcount
+///     <...>
+///     br i1 %loop.ivcheck, label %end, label %loop
+///
+///   end:
+///     %x.curr.res = phi i32 [ %x.curr, %loop ] <...>
+///     %x.next.res = phi i32 [ %x.next, %loop ] <...>
+///     <...>
+/// \endcode
+bool LoopIdiomRecognize::recognizeShiftUntilBitTest() {
+  bool MadeChange = false;
+
+  Value *X, *BitMask, *BitPos, *XCurr;
+  Instruction *XNext;
+  if (!detectShiftUntilBitTestIdiom(CurLoop, X, BitMask, BitPos, XCurr,
+                                    XNext)) {
+    LLVM_DEBUG(dbgs() << DEBUG_TYPE
+               " shift-until-bittest idiom detection failed.\n");
+    return MadeChange;
+  }
+  LLVM_DEBUG(dbgs() << DEBUG_TYPE " shift-until-bittest idiom detected!\n");
+
+  // Ok, it is the idiom we were looking for, we *could* transform this loop,
+  // but is it profitable to transform?
+
+  BasicBlock *LoopHeaderBB = CurLoop->getHeader();
+  BasicBlock *LoopPreheaderBB = CurLoop->getLoopPreheader();
+  assert(LoopPreheaderBB && "There is always a loop preheader.");
+
+  BasicBlock *SuccessorBB = CurLoop->getExitBlock();
+  assert(LoopPreheaderBB && "There is only a single successor.");
+
+  IRBuilder<> Builder(LoopPreheaderBB->getTerminator());
+  Builder.SetCurrentDebugLocation(cast<Instruction>(XCurr)->getDebugLoc());
+
+  Intrinsic::ID IntrID = Intrinsic::ctlz;
+  Type *Ty = X->getType();
+
+  TargetTransformInfo::TargetCostKind CostKind =
+      TargetTransformInfo::TCK_SizeAndLatency;
+
+  // The rewrite is considered to be unprofitable iff and only iff the
+  // intrinsic/shift we'll use are not cheap. Note that we are okay with *just*
+  // making the loop countable, even if nothing else changes.
+  IntrinsicCostAttributes Attrs(
+      IntrID, Ty, {UndefValue::get(Ty), /*is_zero_undef=*/Builder.getTrue()});
+  int Cost = TTI->getIntrinsicInstrCost(Attrs, CostKind);
+  if (Cost > TargetTransformInfo::TCC_Basic) {
+    LLVM_DEBUG(dbgs() << DEBUG_TYPE
+               " Intrinsic is too costly, not beneficial\n");
+    return MadeChange;
+  }
+  if (TTI->getArithmeticInstrCost(Instruction::Shl, Ty, CostKind) >
+      TargetTransformInfo::TCC_Basic) {
+    LLVM_DEBUG(dbgs() << DEBUG_TYPE " Shift is too costly, not beneficial\n");
+    return MadeChange;
+  }
+
+  // Ok, transform appears worthwhile.
+  MadeChange = true;
+
+  // Step 1: Compute the loop trip count.
+
+  Value *LowBitMask = Builder.CreateAdd(BitMask, Constant::getAllOnesValue(Ty),
+                                        BitPos->getName() + ".lowbitmask");
+  Value *Mask =
+      Builder.CreateOr(LowBitMask, BitMask, BitPos->getName() + ".mask");
+  Value *XMasked = Builder.CreateAnd(X, Mask, X->getName() + ".masked");
+  CallInst *XMaskedNumLeadingZeros = Builder.CreateIntrinsic(
+      IntrID, Ty, {XMasked, /*is_zero_undef=*/Builder.getTrue()},
+      /*FMFSource=*/nullptr, XMasked->getName() + ".numleadingzeros");
+  Value *XMaskedNumActiveBits = Builder.CreateSub(
+      ConstantInt::get(Ty, Ty->getScalarSizeInBits()), XMaskedNumLeadingZeros,
+      XMasked->getName() + ".numactivebits");
+  Value *XMaskedLeadingOnePos =
+      Builder.CreateAdd(XMaskedNumActiveBits, Constant::getAllOnesValue(Ty),
+                        XMasked->getName() + ".leadingonepos");
+
+  Value *LoopBackedgeTakenCount = Builder.CreateSub(
+      BitPos, XMaskedLeadingOnePos, CurLoop->getName() + ".backedgetakencount");
+  // We know loop's backedge-taken count, but what's loop's trip count?
+  // Note that while NUW is always safe, while NSW is only for bitwidths != 2.
+  Value *LoopTripCount =
+      Builder.CreateNUWAdd(LoopBackedgeTakenCount, ConstantInt::get(Ty, 1),
+                           CurLoop->getName() + ".tripcount");
+
+  // Step 2: Compute the recurrence's final value without a loop.
+
+  // NewX is always safe to compute, because `LoopBackedgeTakenCount`
+  // will always be smaller than `bitwidth(X)`, i.e. we never get poison.
+  Value *NewX = Builder.CreateShl(X, LoopBackedgeTakenCount);
+  NewX->takeName(XCurr);
+  if (auto *I = dyn_cast<Instruction>(NewX))
+    I->copyIRFlags(XNext, /*IncludeWrapFlags=*/true);
+
+  Value *NewXNext;
+  // Rewriting XNext is more complicated, however, because `X << LoopTripCount`
+  // will be poison iff `LoopTripCount == bitwidth(X)` (which will happen
+  // iff `BitPos` is `bitwidth(x) - 1` and `X` is `1`). So unless we know
+  // that isn't the case, we'll need to emit an alternative, safe IR.
+  if (XNext->hasNoSignedWrap() || XNext->hasNoUnsignedWrap() ||
+      PatternMatch::match(
+          BitPos, PatternMatch::m_SpecificInt_ICMP(
+                      ICmpInst::ICMP_NE, APInt(Ty->getScalarSizeInBits(),
+                                               Ty->getScalarSizeInBits() - 1))))
+    NewXNext = Builder.CreateShl(X, LoopTripCount);
+  else {
+    // Otherwise, just additionally shift by one. It's the smallest solution,
+    // alternatively, we could check that NewX is INT_MIN (or BitPos is )
+    // and select 0 instead.
+    NewXNext = Builder.CreateShl(NewX, ConstantInt::get(Ty, 1));
+  }
+
+  NewXNext->takeName(XNext);
+  if (auto *I = dyn_cast<Instruction>(NewXNext))
+    I->copyIRFlags(XNext, /*IncludeWrapFlags=*/true);
+
+  // Step 3: Adjust the successor basic block to recieve the computed
+  //         recurrence's final value instead of the recurrence itself.
+
+  XCurr->replaceUsesOutsideBlock(NewX, LoopHeaderBB);
+  XNext->replaceUsesOutsideBlock(NewXNext, LoopHeaderBB);
+
+  // Step 4: Rewrite the loop into a countable form, with canonical IV.
+
+  // The new canonical induction variable.
+  Builder.SetInsertPoint(&LoopHeaderBB->front());
+  auto *IV = Builder.CreatePHI(Ty, 2, CurLoop->getName() + ".iv");
+
+  // The induction itself.
+  // Note that while NUW is always safe, while NSW is only for bitwidths != 2.
+  Builder.SetInsertPoint(LoopHeaderBB->getTerminator());
+  auto *IVNext = Builder.CreateNUWAdd(IV, ConstantInt::get(Ty, 1),
+                                      IV->getName() + ".next");
+
+  // The loop trip count check.
+  auto *IVCheck = Builder.CreateICmpEQ(IVNext, LoopTripCount,
+                                       CurLoop->getName() + ".ivcheck");
+  Builder.CreateCondBr(IVCheck, SuccessorBB, LoopHeaderBB);
+  LoopHeaderBB->getTerminator()->eraseFromParent();
+
+  // Populate the IV PHI.
+  IV->addIncoming(ConstantInt::get(Ty, 0), LoopPreheaderBB);
+  IV->addIncoming(IVNext, LoopHeaderBB);
+
+  // Step 5: Forget the "non-computable" trip-count SCEV associated with the
+  //   loop. The loop would otherwise not be deleted even if it becomes empty.
+
+  SE->forgetLoop(CurLoop);
+
+  // Other passes will take care of actually deleting the loop if possible.
+
+  LLVM_DEBUG(dbgs() << DEBUG_TYPE " shift-until-bittest idiom optimized!\n");
+
+  ++NumShiftUntilBitTest;
+  return MadeChange;
+}
diff --git a/llvm/lib/Transforms/Scalar/LoopPassManager.cpp b/llvm/lib/Transforms/Scalar/LoopPassManager.cpp
index 5bc41552e1a35..3fe8e72591143 100644
--- a/llvm/lib/Transforms/Scalar/LoopPassManager.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopPassManager.cpp
@@ -222,11 +222,16 @@ PreservedAnalyses FunctionToLoopPassAdaptor::run(Function &F,
 
   // Register the worklist and loop analysis manager so that loop passes can
   // update them when they mutate the loop nest structure.
-  LPMUpdater Updater(Worklist, LAM);
+  LPMUpdater Updater(Worklist, LAM, LoopNestMode);
 
   // Add the loop nests in the reverse order of LoopInfo. See method
   // declaration.
-  appendLoopsToWorklist(LI, Worklist);
+  if (!LoopNestMode) {
+    appendLoopsToWorklist(LI, Worklist);
+  } else {
+    for (Loop *L : LI)
+      Worklist.insert(L);
+  }
 
 #ifndef NDEBUG
   PI.pushBeforeNonSkippedPassCallback([&LAR, &LI](StringRef PassID, Any IR) {
@@ -247,6 +252,8 @@ PreservedAnalyses FunctionToLoopPassAdaptor::run(Function &F,
 
   do {
     Loop *L = Worklist.pop_back_val();
+    assert(!(LoopNestMode && L->getParentLoop()) &&
+           "L should be a top-level loop in loop-nest mode.");
 
     // Reset the update structure for this loop.
     Updater.CurrentL = L;
diff --git a/llvm/lib/Transforms/Scalar/LoopPredication.cpp b/llvm/lib/Transforms/Scalar/LoopPredication.cpp
index 3ca5b985c365e..4f97641e2027c 100644
--- a/llvm/lib/Transforms/Scalar/LoopPredication.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopPredication.cpp
@@ -362,7 +362,7 @@ PreservedAnalyses LoopPredicationPass::run(Loop &L, LoopAnalysisManager &AM,
   // For the new PM, we also can't use BranchProbabilityInfo as an analysis
   // pass. Function analyses need to be preserved across loop transformations
   // but BPI is not preserved, hence a newly built one is needed.
-  BranchProbabilityInfo BPI(*F, AR.LI, &AR.TLI);
+  BranchProbabilityInfo BPI(*F, AR.LI, &AR.TLI, &AR.DT, nullptr);
   LoopPredication LP(&AR.AA, &AR.DT, &AR.SE, &AR.LI, &BPI);
   if (!LP.runOnLoop(&L))
     return PreservedAnalyses::all();
diff --git a/llvm/lib/Transforms/Scalar/LoopSink.cpp b/llvm/lib/Transforms/Scalar/LoopSink.cpp
index bc4d6bbd3ebef..c20e5e0cbfb33 100644
--- a/llvm/lib/Transforms/Scalar/LoopSink.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopSink.cpp
@@ -222,8 +222,7 @@ static bool sinkInstruction(
   // of the loop block numbers as iterating the set doesn't give a useful
   // order. No need to stable sort as the block numbers are a total ordering.
   SmallVector<BasicBlock *, 2> SortedBBsToSinkInto;
-  SortedBBsToSinkInto.insert(SortedBBsToSinkInto.begin(), BBsToSinkInto.begin(),
-                             BBsToSinkInto.end());
+  llvm::append_range(SortedBBsToSinkInto, BBsToSinkInto);
   llvm::sort(SortedBBsToSinkInto, [&](BasicBlock *A, BasicBlock *B) {
     return LoopBlockNumber.find(A)->second < LoopBlockNumber.find(B)->second;
   });
diff --git a/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp b/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
index 50792d713b419..590b845082dc9 100644
--- a/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopUnswitch.cpp
@@ -1238,7 +1238,7 @@ void LoopUnswitch::unswitchNontrivialCondition(Value *LIC, Constant *Val,
   LoopBlocks.push_back(NewPreheader);
 
   // We want the loop to come after the preheader, but before the exit blocks.
-  LoopBlocks.insert(LoopBlocks.end(), L->block_begin(), L->block_end());
+  llvm::append_range(LoopBlocks, L->blocks());
 
   SmallVector<BasicBlock*, 8> ExitBlocks;
   L->getUniqueExitBlocks(ExitBlocks);
@@ -1252,7 +1252,7 @@ void LoopUnswitch::unswitchNontrivialCondition(Value *LIC, Constant *Val,
   L->getUniqueExitBlocks(ExitBlocks);
 
   // Add exit blocks to the loop blocks.
-  LoopBlocks.insert(LoopBlocks.end(), ExitBlocks.begin(), ExitBlocks.end());
+  llvm::append_range(LoopBlocks, ExitBlocks);
 
   // Next step, clone all of the basic blocks that make up the loop (including
   // the loop preheader and exit blocks), keeping track of the mapping between
diff --git a/llvm/lib/Transforms/Scalar/NewGVN.cpp b/llvm/lib/Transforms/Scalar/NewGVN.cpp
index 958014fcb1ed9..ee26c299c88c6 100644
--- a/llvm/lib/Transforms/Scalar/NewGVN.cpp
+++ b/llvm/lib/Transforms/Scalar/NewGVN.cpp
@@ -802,8 +802,6 @@ class NewGVN {
                             const BasicBlock *) const;
 
   // Various instruction touch utilities
-  template <typename Map, typename KeyType, typename Func>
-  void for_each_found(Map &, const KeyType &, Func);
   template <typename Map, typename KeyType>
   void touchAndErase(Map &, const KeyType &);
   void markUsersTouched(Value *);
@@ -1991,16 +1989,6 @@ NewGVN::performSymbolicEvaluation(Value *V,
   return E;
 }
 
-// Look up a container in a map, and then call a function for each thing in the
-// found container.
-template <typename Map, typename KeyType, typename Func>
-void NewGVN::for_each_found(Map &M, const KeyType &Key, Func F) {
-  const auto Result = M.find_as(Key);
-  if (Result != M.end())
-    for (typename Map::mapped_type::value_type Mapped : Result->second)
-      F(Mapped);
-}
-
 // Look up a container of values/instructions in a map, and touch all the
 // instructions in the container.  Then erase value from the map.
 template <typename Map, typename KeyType>
diff --git a/llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp b/llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp
index 028c98f93a70f..a110f7d5c2417 100644
--- a/llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp
+++ b/llvm/lib/Transforms/Scalar/PlaceSafepoints.cpp
@@ -589,8 +589,7 @@ bool PlaceSafepoints::runOnFunction(Function &F) {
   for (Instruction *PollLocation : PollsNeeded) {
     std::vector<CallBase *> RuntimeCalls;
     InsertSafepointPoll(PollLocation, RuntimeCalls, TLI);
-    ParsePointNeeded.insert(ParsePointNeeded.end(), RuntimeCalls.begin(),
-                            RuntimeCalls.end());
+    llvm::append_range(ParsePointNeeded, RuntimeCalls);
   }
 
   return Modified;
diff --git a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
index 42036a801c4f6..68ddebf113d18 100644
--- a/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
+++ b/llvm/lib/Transforms/Scalar/RewriteStatepointsForGC.cpp
@@ -2501,8 +2501,7 @@ static bool insertParsePoints(Function &F, DominatorTree &DT,
     // That Value* no longer exists and we need to use the new gc_result.
     // Thankfully, the live set is embedded in the statepoint (and updated), so
     // we just grab that.
-    Live.insert(Live.end(), Info.StatepointToken->gc_args_begin(),
-                Info.StatepointToken->gc_args_end());
+    llvm::append_range(Live, Info.StatepointToken->gc_args());
 #ifndef NDEBUG
     // Do some basic sanity checks on our liveness results before performing
     // relocation.  Relocation can and will turn mistakes in liveness results
@@ -2736,10 +2735,8 @@ bool RewriteStatepointsForGC::runOnFunction(Function &F, DominatorTree &DT,
   // of liveness sets for no good reason.  It may be harder to do this post
   // insertion since relocations and base phis can confuse things.
   for (BasicBlock &BB : F)
-    if (BB.getUniquePredecessor()) {
-      MadeChange = true;
-      FoldSingleEntryPHINodes(&BB);
-    }
+    if (BB.getUniquePredecessor())
+      MadeChange |= FoldSingleEntryPHINodes(&BB);
 
   // Before we start introducing relocations, we want to tweak the IR a bit to
   // avoid unfortunate code generation effects.  The main example is that we
diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
index 14795d450d3d0..5b8bc184daca0 100644
--- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
+++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
@@ -136,9 +136,10 @@ bool llvm::EliminateUnreachableBlocks(Function &F, DomTreeUpdater *DTU,
   return !DeadBlocks.empty();
 }
 
-void llvm::FoldSingleEntryPHINodes(BasicBlock *BB,
+bool llvm::FoldSingleEntryPHINodes(BasicBlock *BB,
                                    MemoryDependenceResults *MemDep) {
-  if (!isa<PHINode>(BB->begin())) return;
+  if (!isa<PHINode>(BB->begin()))
+    return false;
 
   while (PHINode *PN = dyn_cast<PHINode>(BB->begin())) {
     if (PN->getIncomingValue(0) != PN)
@@ -151,6 +152,7 @@ void llvm::FoldSingleEntryPHINodes(BasicBlock *BB,
 
     PN->eraseFromParent();
   }
+  return true;
 }
 
 bool llvm::DeleteDeadPHIs(BasicBlock *BB, const TargetLibraryInfo *TLI,
diff --git a/llvm/lib/Transforms/Utils/BuildLibCalls.cpp b/llvm/lib/Transforms/Utils/BuildLibCalls.cpp
index e8b14409c286f..92c85e3b95b8f 100644
--- a/llvm/lib/Transforms/Utils/BuildLibCalls.cpp
+++ b/llvm/lib/Transforms/Utils/BuildLibCalls.cpp
@@ -1159,7 +1159,7 @@ Value *llvm::emitSNPrintf(Value *Dest, Value *Size, Value *Fmt,
                           ArrayRef<Value *> VariadicArgs, IRBuilderBase &B,
                           const TargetLibraryInfo *TLI) {
   SmallVector<Value *, 8> Args{castToCStr(Dest, B), Size, castToCStr(Fmt, B)};
-  Args.insert(Args.end(), VariadicArgs.begin(), VariadicArgs.end());
+  llvm::append_range(Args, VariadicArgs);
   return emitLibCall(LibFunc_snprintf, B.getInt32Ty(),
                      {B.getInt8PtrTy(), Size->getType(), B.getInt8PtrTy()},
                      Args, B, TLI, /*IsVaArgs=*/true);
@@ -1169,7 +1169,7 @@ Value *llvm::emitSPrintf(Value *Dest, Value *Fmt,
                          ArrayRef<Value *> VariadicArgs, IRBuilderBase &B,
                          const TargetLibraryInfo *TLI) {
   SmallVector<Value *, 8> Args{castToCStr(Dest, B), castToCStr(Fmt, B)};
-  Args.insert(Args.end(), VariadicArgs.begin(), VariadicArgs.end());
+  llvm::append_range(Args, VariadicArgs);
   return emitLibCall(LibFunc_sprintf, B.getInt32Ty(),
                      {B.getInt8PtrTy(), B.getInt8PtrTy()}, Args, B, TLI,
                      /*IsVaArgs=*/true);
diff --git a/llvm/lib/Transforms/Utils/CodeMoverUtils.cpp b/llvm/lib/Transforms/Utils/CodeMoverUtils.cpp
index 08047dc0f96ee..ce982c7403aa4 100644
--- a/llvm/lib/Transforms/Utils/CodeMoverUtils.cpp
+++ b/llvm/lib/Transforms/Utils/CodeMoverUtils.cpp
@@ -355,35 +355,32 @@ bool llvm::isSafeToMoveBefore(Instruction &I, Instruction &InsertPoint,
   // Check if there exists instructions which may throw, may synchonize, or may
   // never return, from I to InsertPoint.
   if (!isSafeToSpeculativelyExecute(&I))
-    if (std::any_of(InstsToCheck.begin(), InstsToCheck.end(),
-                    [](Instruction *I) {
-                      if (I->mayThrow())
-                        return true;
-
-                      const CallBase *CB = dyn_cast<CallBase>(I);
-                      if (!CB)
-                        return false;
-                      if (!CB->hasFnAttr(Attribute::WillReturn))
-                        return true;
-                      if (!CB->hasFnAttr(Attribute::NoSync))
-                        return true;
-
-                      return false;
-                    })) {
+    if (llvm::any_of(InstsToCheck, [](Instruction *I) {
+          if (I->mayThrow())
+            return true;
+
+          const CallBase *CB = dyn_cast<CallBase>(I);
+          if (!CB)
+            return false;
+          if (!CB->hasFnAttr(Attribute::WillReturn))
+            return true;
+          if (!CB->hasFnAttr(Attribute::NoSync))
+            return true;
+
+          return false;
+        })) {
       return reportInvalidCandidate(I, MayThrowException);
     }
 
   // Check if I has any output/flow/anti dependences with instructions from \p
   // StartInst to \p EndInst.
-  if (std::any_of(InstsToCheck.begin(), InstsToCheck.end(),
-                  [&DI, &I](Instruction *CurInst) {
-                    auto DepResult = DI->depends(&I, CurInst, true);
-                    if (DepResult &&
-                        (DepResult->isOutput() || DepResult->isFlow() ||
-                         DepResult->isAnti()))
-                      return true;
-                    return false;
-                  }))
+  if (llvm::any_of(InstsToCheck, [&DI, &I](Instruction *CurInst) {
+        auto DepResult = DI->depends(&I, CurInst, true);
+        if (DepResult && (DepResult->isOutput() || DepResult->isFlow() ||
+                          DepResult->isAnti()))
+          return true;
+        return false;
+      }))
     return reportInvalidCandidate(I, HasDependences);
 
   return true;
diff --git a/llvm/lib/Transforms/Utils/Evaluator.cpp b/llvm/lib/Transforms/Utils/Evaluator.cpp
index a01dc7a4e6097..732b00635e29b 100644
--- a/llvm/lib/Transforms/Utils/Evaluator.cpp
+++ b/llvm/lib/Transforms/Utils/Evaluator.cpp
@@ -210,11 +210,7 @@ static Constant *getInitializer(Constant *C) {
 Constant *Evaluator::ComputeLoadResult(Constant *P) {
   // If this memory location has been recently stored, use the stored value: it
   // is the most up-to-date.
-  auto findMemLoc = [this](Constant *Ptr) {
-    DenseMap<Constant *, Constant *>::const_iterator I =
-        MutatedMemory.find(Ptr);
-    return I != MutatedMemory.end() ? I->second : nullptr;
-  };
+  auto findMemLoc = [this](Constant *Ptr) { return MutatedMemory.lookup(Ptr); };
 
   if (Constant *Val = findMemLoc(P))
     return Val;
diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp
index d4d32a7169ef0..aba2962733db1 100644
--- a/llvm/lib/Transforms/Utils/InlineFunction.cpp
+++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp
@@ -1850,11 +1850,8 @@ llvm::InlineResult llvm::InlineFunction(CallBase &CB, InlineFunctionInfo &IFI,
           MergedDeoptArgs.reserve(ParentDeopt->Inputs.size() +
                                   ChildOB.Inputs.size());
 
-          MergedDeoptArgs.insert(MergedDeoptArgs.end(),
-                                 ParentDeopt->Inputs.begin(),
-                                 ParentDeopt->Inputs.end());
-          MergedDeoptArgs.insert(MergedDeoptArgs.end(), ChildOB.Inputs.begin(),
-                                 ChildOB.Inputs.end());
+          llvm::append_range(MergedDeoptArgs, ParentDeopt->Inputs);
+          llvm::append_range(MergedDeoptArgs, ChildOB.Inputs);
 
           OpDefs.emplace_back("deopt", std::move(MergedDeoptArgs));
         }
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 125431d6afc80..e32b0f142f070 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -704,34 +704,6 @@ bool llvm::SimplifyInstructionsInBlock(BasicBlock *BB,
 //  Control Flow Graph Restructuring.
 //
 
-void llvm::RemovePredecessorAndSimplify(BasicBlock *BB, BasicBlock *Pred,
-                                        DomTreeUpdater *DTU) {
-  // This only adjusts blocks with PHI nodes.
-  if (!isa<PHINode>(BB->begin()))
-    return;
-
-  // Remove the entries for Pred from the PHI nodes in BB, but do not simplify
-  // them down.  This will leave us with single entry phi nodes and other phis
-  // that can be removed.
-  BB->removePredecessor(Pred, true);
-
-  WeakTrackingVH PhiIt = &BB->front();
-  while (PHINode *PN = dyn_cast<PHINode>(PhiIt)) {
-    PhiIt = &*++BasicBlock::iterator(cast<Instruction>(PhiIt));
-    Value *OldPhiIt = PhiIt;
-
-    if (!recursivelySimplifyInstruction(PN))
-      continue;
-
-    // If recursive simplification ended up deleting the next PHI node we would
-    // iterate to, then our iterator is invalid, restart scanning from the top
-    // of the block.
-    if (PhiIt != OldPhiIt) PhiIt = &BB->front();
-  }
-  if (DTU)
-    DTU->applyUpdatesPermissive({{DominatorTree::Delete, Pred, BB}});
-}
-
 void llvm::MergeBasicBlockIntoOnlyPred(BasicBlock *DestBB,
                                        DomTreeUpdater *DTU) {
 
diff --git a/llvm/lib/Transforms/Utils/LoopVersioning.cpp b/llvm/lib/Transforms/Utils/LoopVersioning.cpp
index 06e204060cb08..b54aee35d56d5 100644
--- a/llvm/lib/Transforms/Utils/LoopVersioning.cpp
+++ b/llvm/lib/Transforms/Utils/LoopVersioning.cpp
@@ -45,11 +45,13 @@ LoopVersioning::LoopVersioning(const LoopAccessInfo &LAI,
       Preds(LAI.getPSE().getUnionPredicate()), LAI(LAI), LI(LI), DT(DT),
       SE(SE) {
   assert(L->getExitBlock() && "No single exit block");
-  assert(L->isLoopSimplifyForm() && "Loop is not in loop-simplify form");
 }
 
 void LoopVersioning::versionLoop(
     const SmallVectorImpl<Instruction *> &DefsUsedOutside) {
+  assert(VersionedLoop->isLoopSimplifyForm() &&
+         "Loop is not in loop-simplify form");
+
   Instruction *FirstCheckInst;
   Instruction *MemRuntimeCheck;
   Value *SCEVRuntimeCheck;
diff --git a/llvm/lib/Transforms/Utils/SSAUpdater.cpp b/llvm/lib/Transforms/Utils/SSAUpdater.cpp
index 57df2334c750f..c3add49a7ccd1 100644
--- a/llvm/lib/Transforms/Utils/SSAUpdater.cpp
+++ b/llvm/lib/Transforms/Utils/SSAUpdater.cpp
@@ -64,8 +64,7 @@ bool SSAUpdater::HasValueForBlock(BasicBlock *BB) const {
 }
 
 Value *SSAUpdater::FindValueForBlock(BasicBlock *BB) const {
-  AvailableValsTy::iterator AVI = getAvailableVals(AV).find(BB);
-  return (AVI != getAvailableVals(AV).end()) ? AVI->second : nullptr;
+  return getAvailableVals(AV).lookup(BB);
 }
 
 void SSAUpdater::AddAvailableValue(BasicBlock *BB, Value *V) {
diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
index 777ec44cd0bd0..7d5f6daba7b27 100644
--- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
+++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp
@@ -2986,6 +2986,13 @@ bool llvm::FoldBranchToCommonDest(BranchInst *BI, DomTreeUpdater *DTU,
                      "Non-external users are never PHI instructions.");
               return false;
             }
+            if (User->getParent() == PredBlock) {
+              // The "exteral" use is in the block into which we just cloned the
+              // bonus instruction. This means two things: 1. we are in an
+              // unreachable block 2. the instruction is self-referencing.
+              // So let's just rewrite it...
+              return true;
+            }
             (void)BI;
             assert(isa<PHINode>(User) && "All external users must be PHI's.");
             auto *PN = cast<PHINode>(User);
@@ -4632,6 +4639,7 @@ bool SimplifyCFGOpt::simplifyUnreachable(UnreachableInst *UI) {
         Changed = true;
       }
     } else if (auto *CRI = dyn_cast<CleanupReturnInst>(TI)) {
+      (void)CRI;
       assert(CRI->hasUnwindDest() && CRI->getUnwindDest() == BB &&
              "Expected to always have an unwind to BB.");
       Updates.push_back({DominatorTree::Delete, Predecessor, BB});
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
index 60e1cc9a4a59a..65b3132dc3f17 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationLegality.cpp
@@ -1095,9 +1095,15 @@ bool LoopVectorizationLegality::canVectorizeLoopCFG(Loop *Lp,
       return false;
   }
 
-  // We must have a single exiting block.
-  if (!Lp->getExitingBlock()) {
-    reportVectorizationFailure("The loop must have an exiting block",
+  // We currently must have a single "exit block" after the loop. Note that
+  // multiple "exiting blocks" inside the loop are allowed, provided they all
+  // reach the single exit block.
+  // TODO: This restriction can be relaxed in the near future, it's here solely
+  // to allow separation of changes for review. We need to generalize the phi
+  // update logic in a number of places.
+  BasicBlock *ExitBB = Lp->getUniqueExitBlock();
+  if (!ExitBB) {
+    reportVectorizationFailure("The loop must have a unique exit block",
         "loop control flow is not understood by vectorizer",
         "CFGNotUnderstood", ORE, TheLoop);
     if (DoExtraAnalysis)
@@ -1106,11 +1112,14 @@ bool LoopVectorizationLegality::canVectorizeLoopCFG(Loop *Lp,
       return false;
   }
 
-  // We only handle bottom-tested loops, i.e. loop in which the condition is
-  // checked at the end of each iteration. With that we can assume that all
-  // instructions in the loop are executed the same number of times.
-  if (Lp->getExitingBlock() != Lp->getLoopLatch()) {
-    reportVectorizationFailure("The exiting block is not the loop latch",
+  // The existing code assumes that LCSSA implies that phis are single entry
+  // (which was true when we had at most a single exiting edge from the latch).
+  // In general, there's nothing which prevents an LCSSA phi in exit block from
+  // having two or more values if there are multiple exiting edges leading to
+  // the exit block.  (TODO: implement general case)
+  if (!llvm::empty(ExitBB->phis()) && !ExitBB->getSinglePredecessor()) {
+    reportVectorizationFailure("The loop must have no live-out values if "
+                               "it has more than one exiting block",
         "loop control flow is not understood by vectorizer",
         "CFGNotUnderstood", ORE, TheLoop);
     if (DoExtraAnalysis)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index e486f7110295c..c48b650c3c3e3 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -569,6 +569,7 @@ class InnerLoopVectorizer {
   /// BlockInMask is non-null. Use \p State to translate given VPValues to IR
   /// values in the vectorized loop.
   void vectorizeInterleaveGroup(const InterleaveGroup<Instruction> *Group,
+                                ArrayRef<VPValue *> VPDefs,
                                 VPTransformState &State, VPValue *Addr,
                                 ArrayRef<VPValue *> StoredValues,
                                 VPValue *BlockInMask = nullptr);
@@ -836,7 +837,8 @@ class InnerLoopVectorizer {
   /// Middle Block between the vector and the scalar.
   BasicBlock *LoopMiddleBlock;
 
-  /// The ExitBlock of the scalar loop.
+  /// The (unique) ExitBlock of the scalar loop.  Note that
+  /// there can be multiple exiting edges reaching this block.
   BasicBlock *LoopExitBlock;
 
   /// The vector loop body.
@@ -1547,11 +1549,16 @@ class LoopVectorizationCostModel {
     return InterleaveInfo.getInterleaveGroup(Instr);
   }
 
-  /// Returns true if an interleaved group requires a scalar iteration
-  /// to handle accesses with gaps, and there is nothing preventing us from
-  /// creating a scalar epilogue.
+  /// Returns true if we're required to use a scalar epilogue for at least
+  /// the final iteration of the original loop.
   bool requiresScalarEpilogue() const {
-    return isScalarEpilogueAllowed() && InterleaveInfo.requiresScalarEpilogue();
+    if (!isScalarEpilogueAllowed())
+      return false;
+    // If we might exit from anywhere but the latch, must run the exiting
+    // iteration in scalar form.
+    if (TheLoop->getExitingBlock() != TheLoop->getLoopLatch())
+      return true;
+    return InterleaveInfo.requiresScalarEpilogue();
   }
 
   /// Returns true if a scalar epilogue is not allowed due to optsize or a
@@ -2514,8 +2521,9 @@ static bool useMaskedInterleavedAccesses(const TargetTransformInfo &TTI) {
 //        <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>    ; Interleave R,G,B elements
 //   store <12 x i32> %interleaved.vec              ; Write 4 tuples of R,G,B
 void InnerLoopVectorizer::vectorizeInterleaveGroup(
-    const InterleaveGroup<Instruction> *Group, VPTransformState &State,
-    VPValue *Addr, ArrayRef<VPValue *> StoredValues, VPValue *BlockInMask) {
+    const InterleaveGroup<Instruction> *Group, ArrayRef<VPValue *> VPDefs,
+    VPTransformState &State, VPValue *Addr, ArrayRef<VPValue *> StoredValues,
+    VPValue *BlockInMask) {
   Instruction *Instr = Group->getInsertPos();
   const DataLayout &DL = Instr->getModule()->getDataLayout();
 
@@ -2617,6 +2625,7 @@ void InnerLoopVectorizer::vectorizeInterleaveGroup(
 
     // For each member in the group, shuffle out the appropriate data from the
     // wide loads.
+    unsigned J = 0;
     for (unsigned I = 0; I < InterleaveFactor; ++I) {
       Instruction *Member = Group->getMember(I);
 
@@ -2641,8 +2650,9 @@ void InnerLoopVectorizer::vectorizeInterleaveGroup(
         if (Group->isReverse())
           StridedVec = reverseVector(StridedVec);
 
-        VectorLoopValueMap.setVectorValue(Member, Part, StridedVec);
+        State.set(VPDefs[J], Member, StridedVec, Part);
       }
+      ++J;
     }
     return;
   }
@@ -2908,7 +2918,7 @@ PHINode *InnerLoopVectorizer::createInductionVariable(Loop *L, Value *Start,
   Induction->addIncoming(Next, Latch);
   // Create the compare.
   Value *ICmp = Builder.CreateICmpEQ(Next, End);
-  Builder.CreateCondBr(ICmp, L->getExitBlock(), Header);
+  Builder.CreateCondBr(ICmp, L->getUniqueExitBlock(), Header);
 
   // Now we have two terminators. Remove the old one from the block.
   Latch->getTerminator()->eraseFromParent();
@@ -2996,13 +3006,17 @@ Value *InnerLoopVectorizer::getOrCreateVectorTripCount(Loop *L) {
   // unroll factor (number of SIMD instructions).
   Value *R = Builder.CreateURem(TC, Step, "n.mod.vf");
 
-  // If there is a non-reversed interleaved group that may speculatively access
-  // memory out-of-bounds, we need to ensure that there will be at least one
-  // iteration of the scalar epilogue loop. Thus, if the step evenly divides
+  // There are two cases where we need to ensure (at least) the last iteration
+  // runs in the scalar remainder loop. Thus, if the step evenly divides
   // the trip count, we set the remainder to be equal to the step. If the step
   // does not evenly divide the trip count, no adjustment is necessary since
   // there will already be scalar iterations. Note that the minimum iterations
-  // check ensures that N >= Step.
+  // check ensures that N >= Step. The cases are:
+  // 1) If there is a non-reversed interleaved group that may speculatively 
+  //    access memory out-of-bounds.
+  // 2) If any instruction may follow a conditionally taken exit. That is, if
+  //    the loop contains multiple exiting blocks, or a single exiting block
+  //    which is not the latch.
   if (VF.isVector() && Cost->requiresScalarEpilogue()) {
     auto *IsZero = Builder.CreateICmpEQ(R, ConstantInt::get(R->getType(), 0));
     R = Builder.CreateSelect(IsZero, Step, R);
@@ -3297,7 +3311,7 @@ Value *InnerLoopVectorizer::emitTransformedIndex(
 Loop *InnerLoopVectorizer::createVectorLoopSkeleton(StringRef Prefix) {
   LoopScalarBody = OrigLoop->getHeader();
   LoopVectorPreHeader = OrigLoop->getLoopPreheader();
-  LoopExitBlock = OrigLoop->getExitBlock();
+  LoopExitBlock = OrigLoop->getUniqueExitBlock();
   assert(LoopExitBlock && "Must have an exit block");
   assert(LoopVectorPreHeader && "Invalid loop structure");
 
@@ -3307,6 +3321,16 @@ Loop *InnerLoopVectorizer::createVectorLoopSkeleton(StringRef Prefix) {
   LoopScalarPreHeader =
       SplitBlock(LoopMiddleBlock, LoopMiddleBlock->getTerminator(), DT, LI,
                  nullptr, Twine(Prefix) + "scalar.ph");
+
+  // Set up branch from middle block to the exit and scalar preheader blocks.
+  // completeLoopSkeleton will update the condition to use an iteration check,
+  // if required to decide whether to execute the remainder.
+  BranchInst *BrInst =
+      BranchInst::Create(LoopExitBlock, LoopScalarPreHeader, Builder.getTrue());
+  auto *ScalarLatchTerm = OrigLoop->getLoopLatch()->getTerminator();
+  BrInst->setDebugLoc(ScalarLatchTerm->getDebugLoc());
+  ReplaceInstWithInst(LoopMiddleBlock->getTerminator(), BrInst);
+
   // We intentionally don't let SplitBlock to update LoopInfo since
   // LoopVectorBody should belong to another loop than LoopVectorPreHeader.
   // LoopVectorBody is explicitly added to the correct place few lines later.
@@ -3415,24 +3439,19 @@ BasicBlock *InnerLoopVectorizer::completeLoopSkeleton(Loop *L,
   // all of the iterations in the first vector loop.
   // If (N - N%VF) == N, then we *don't* need to run the remainder.
   // If tail is to be folded, we know we don't need to run the remainder.
-  Value *CmpN = Builder.getTrue();
   if (!Cost->foldTailByMasking()) {
-    CmpN = CmpInst::Create(Instruction::ICmp, CmpInst::ICMP_EQ, Count,
-                           VectorTripCount, "cmp.n",
-                           LoopMiddleBlock->getTerminator());
+    Instruction *CmpN = CmpInst::Create(Instruction::ICmp, CmpInst::ICMP_EQ,
+                                        Count, VectorTripCount, "cmp.n",
+                                        LoopMiddleBlock->getTerminator());
 
     // Here we use the same DebugLoc as the scalar loop latch terminator instead
     // of the corresponding compare because they may have ended up with
     // different line numbers and we want to avoid awkward line stepping while
     // debugging. Eg. if the compare has got a line number inside the loop.
-    cast<Instruction>(CmpN)->setDebugLoc(ScalarLatchTerm->getDebugLoc());
+    CmpN->setDebugLoc(ScalarLatchTerm->getDebugLoc());
+    cast<BranchInst>(LoopMiddleBlock->getTerminator())->setCondition(CmpN);
   }
 
-  BranchInst *BrInst =
-      BranchInst::Create(LoopExitBlock, LoopScalarPreHeader, CmpN);
-  BrInst->setDebugLoc(ScalarLatchTerm->getDebugLoc());
-  ReplaceInstWithInst(LoopMiddleBlock->getTerminator(), BrInst);
-
   // Get ready to start creating new instructions into the vectorized body.
   assert(LoopVectorPreHeader == L->getLoopPreheader() &&
          "Inconsistent vector loop preheader");
@@ -3563,7 +3582,7 @@ void InnerLoopVectorizer::fixupIVUsers(PHINode *OrigPhi,
   // value (the value that feeds into the phi from the loop latch).
   // We allow both, but they, obviously, have different values.
 
-  assert(OrigLoop->getExitBlock() && "Expected a single exit block");
+  assert(OrigLoop->getUniqueExitBlock() && "Expected a single exit block");
 
   DenseMap<Value *, Value *> MissingVals;
 
@@ -5481,11 +5500,28 @@ LoopVectorizationCostModel::computeMaxVF(ElementCount UserVF, unsigned UserIC) {
     // for size.
     if (runtimeChecksRequired())
       return None;
+
     break;
   }
 
-  // Now try the tail folding
+  // The only loops we can vectorize without a scalar epilogue, are loops with
+  // a bottom-test and a single exiting block. We'd have to handle the fact
+  // that not every instruction executes on the last iteration.  This will
+  // require a lane mask which varies through the vector loop body.  (TODO)
+  if (TheLoop->getExitingBlock() != TheLoop->getLoopLatch()) {
+    // If there was a tail-folding hint/switch, but we can't fold the tail by
+    // masking, fallback to a vectorization with a scalar epilogue.
+    if (ScalarEpilogueStatus == CM_ScalarEpilogueNotNeededUsePredicate) {
+      LLVM_DEBUG(dbgs() << "LV: Cannot fold tail by masking: vectorize with a "
+                           "scalar epilogue instead.\n");
+      ScalarEpilogueStatus = CM_ScalarEpilogueAllowed;
+      return MaxVF;
+    }
+    return None;
+  }
 
+  // Now try the tail folding
+  
   // Invalidate interleave groups that require an epilogue if we can't mask
   // the interleave-group.
   if (!useMaskedInterleavedAccesses(TTI)) {
@@ -5502,7 +5538,15 @@ LoopVectorizationCostModel::computeMaxVF(ElementCount UserVF, unsigned UserIC) {
          "MaxVF must be a power of 2");
   unsigned MaxVFtimesIC =
       UserIC ? MaxVF.getFixedValue() * UserIC : MaxVF.getFixedValue();
-  if (TC > 0 && TC % MaxVFtimesIC == 0) {
+  // Avoid tail folding if the trip count is known to be a multiple of any VF we
+  // chose.
+  ScalarEvolution *SE = PSE.getSE();
+  const SCEV *BackedgeTakenCount = PSE.getBackedgeTakenCount();
+  const SCEV *ExitCount = SE->getAddExpr(
+      BackedgeTakenCount, SE->getOne(BackedgeTakenCount->getType()));
+  const SCEV *Rem = SE->getURemExpr(
+      ExitCount, SE->getConstant(BackedgeTakenCount->getType(), MaxVFtimesIC));
+  if (Rem->isZero()) {
     // Accept MaxVF if we do not have a tail.
     LLVM_DEBUG(dbgs() << "LV: No tail will remain for any chosen VF.\n");
     return MaxVF;
@@ -7904,6 +7948,12 @@ VPValue *VPRecipeBuilder::createEdgeMask(BasicBlock *Src, BasicBlock *Dst,
   if (!BI->isConditional() || BI->getSuccessor(0) == BI->getSuccessor(1))
     return EdgeMaskCache[Edge] = SrcMask;
 
+  // If source is an exiting block, we know the exit edge is dynamically dead
+  // in the vector loop, and thus we don't need to restrict the mask.  Avoid
+  // adding uses of an otherwise potentially dead instruction.
+  if (OrigLoop->isLoopExiting(Src))
+    return EdgeMaskCache[Edge] = SrcMask;
+
   VPValue *EdgeMask = Plan->getOrAddVPValue(BI->getCondition());
   assert(EdgeMask && "No Edge Mask found for condition");
 
@@ -7980,9 +8030,8 @@ VPValue *VPRecipeBuilder::createBlockInMask(BasicBlock *BB, VPlanPtr &Plan) {
   return BlockMaskCache[BB] = BlockMask;
 }
 
-VPWidenMemoryInstructionRecipe *
-VPRecipeBuilder::tryToWidenMemory(Instruction *I, VFRange &Range,
-                                  VPlanPtr &Plan) {
+VPRecipeBase *VPRecipeBuilder::tryToWidenMemory(Instruction *I, VFRange &Range,
+                                                VPlanPtr &Plan) {
   assert((isa<LoadInst>(I) || isa<StoreInst>(I)) &&
          "Must be called with either a load or store");
 
@@ -8417,11 +8466,10 @@ VPlanPtr LoopVectorizationPlanner::buildVPlanWithVPRecipes(
 
       if (auto Recipe =
               RecipeBuilder.tryToCreateWidenRecipe(Instr, Range, Plan)) {
-        // Check if the recipe can be converted to a VPValue. We need the extra
-        // down-casting step until VPRecipeBase inherits from VPValue.
-        VPValue *MaybeVPValue = Recipe->toVPValue();
-        if (!Instr->getType()->isVoidTy() && MaybeVPValue)
-          Plan->addVPValue(Instr, MaybeVPValue);
+        for (auto *Def : Recipe->definedValues()) {
+          auto *UV = Def->getUnderlyingValue();
+          Plan->addVPValue(UV, Def);
+        }
 
         RecipeBuilder.setRecipe(Instr, Recipe);
         VPBB->appendRecipe(Recipe);
@@ -8472,16 +8520,17 @@ VPlanPtr LoopVectorizationPlanner::buildVPlanWithVPRecipes(
       if (auto *SI = dyn_cast_or_null<StoreInst>(IG->getMember(i)))
         StoredValues.push_back(Plan->getOrAddVPValue(SI->getOperand(0)));
 
-    (new VPInterleaveRecipe(IG, Recipe->getAddr(), StoredValues,
-                            Recipe->getMask()))
-        ->insertBefore(Recipe);
-
+    auto *VPIG = new VPInterleaveRecipe(IG, Recipe->getAddr(), StoredValues,
+                                        Recipe->getMask());
+    VPIG->insertBefore(Recipe);
+    unsigned J = 0;
     for (unsigned i = 0; i < IG->getFactor(); ++i)
       if (Instruction *Member = IG->getMember(i)) {
         if (!Member->getType()->isVoidTy()) {
           VPValue *OriginalV = Plan->getVPValue(Member);
           Plan->removeVPValueFor(Member);
-          OriginalV->replaceAllUsesWith(Plan->getOrAddVPValue(Member));
+          OriginalV->replaceAllUsesWith(VPIG->getVPValue(J));
+          J++;
         }
         RecipeBuilder.getRecipe(Member)->eraseFromParent();
       }
@@ -8596,10 +8645,11 @@ void LoopVectorizationPlanner::adjustRecipesForInLoopReductions(
                          : nullptr;
       VPReductionRecipe *RedRecipe = new VPReductionRecipe(
           &RdxDesc, R, ChainOp, VecOp, CondOp, Legal->hasFunNoNaNAttr(), TTI);
-      WidenRecipe->toVPValue()->replaceAllUsesWith(RedRecipe);
+      WidenRecipe->getVPValue()->replaceAllUsesWith(RedRecipe);
       Plan->removeVPValueFor(R);
       Plan->addVPValue(R, RedRecipe);
       WidenRecipe->getParent()->insert(RedRecipe, WidenRecipe->getIterator());
+      WidenRecipe->getVPValue()->replaceAllUsesWith(RedRecipe);
       WidenRecipe->eraseFromParent();
 
       if (Kind == RecurrenceDescriptor::RK_IntegerMinMax ||
@@ -8608,7 +8658,7 @@ void LoopVectorizationPlanner::adjustRecipesForInLoopReductions(
             RecipeBuilder.getRecipe(cast<Instruction>(R->getOperand(0)));
         assert(isa<VPWidenRecipe>(CompareRecipe) &&
                "Expected to replace a VPWidenSC");
-        assert(CompareRecipe->toVPValue()->getNumUsers() == 0 &&
+        assert(cast<VPWidenRecipe>(CompareRecipe)->getNumUsers() == 0 &&
                "Expected no remaining users");
         CompareRecipe->eraseFromParent();
       }
@@ -8713,8 +8763,8 @@ void VPBlendRecipe::execute(VPTransformState &State) {
 
 void VPInterleaveRecipe::execute(VPTransformState &State) {
   assert(!State.Instance && "Interleave group being replicated.");
-  State.ILV->vectorizeInterleaveGroup(IG, State, getAddr(), getStoredValues(),
-                                      getMask());
+  State.ILV->vectorizeInterleaveGroup(IG, definedValues(), State, getAddr(),
+                                      getStoredValues(), getMask());
 }
 
 void VPReductionRecipe::execute(VPTransformState &State) {
@@ -8845,7 +8895,7 @@ void VPPredInstPHIRecipe::execute(VPTransformState &State) {
 void VPWidenMemoryInstructionRecipe::execute(VPTransformState &State) {
   VPValue *StoredValue = isStore() ? getStoredValue() : nullptr;
   State.ILV->vectorizeMemoryInstruction(&Ingredient, State,
-                                        StoredValue ? nullptr : toVPValue(),
+                                        StoredValue ? nullptr : getVPValue(),
                                         getAddr(), StoredValue, getMask());
 }
 
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index b03fb203c6d75..9f17689072272 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -1840,18 +1840,10 @@ class BoUpSLP {
   }
 #endif
 
-  TreeEntry *getTreeEntry(Value *V) {
-    auto I = ScalarToTreeEntry.find(V);
-    if (I != ScalarToTreeEntry.end())
-      return I->second;
-    return nullptr;
-  }
+  TreeEntry *getTreeEntry(Value *V) { return ScalarToTreeEntry.lookup(V); }
 
   const TreeEntry *getTreeEntry(Value *V) const {
-    auto I = ScalarToTreeEntry.find(V);
-    if (I != ScalarToTreeEntry.end())
-      return I->second;
-    return nullptr;
+    return ScalarToTreeEntry.lookup(V);
   }
 
   /// Maps a specific scalar to its tree entry.
@@ -2472,9 +2464,9 @@ template <> struct DOTGraphTraits<BoUpSLP *> : public DefaultDOTGraphTraits {
     }
     for (auto V : Entry->Scalars) {
       OS << *V;
-      if (std::any_of(
-              R->ExternalUses.begin(), R->ExternalUses.end(),
-              [&](const BoUpSLP::ExternalUser &EU) { return EU.Scalar == V; }))
+      if (llvm::any_of(R->ExternalUses, [&](const BoUpSLP::ExternalUser &EU) {
+            return EU.Scalar == V;
+          }))
         OS << " <extract>";
       OS << "\n";
     }
@@ -6422,17 +6414,16 @@ namespace {
 
 /// Model horizontal reductions.
 ///
-/// A horizontal reduction is a tree of reduction operations (currently add and
-/// fadd) that has operations that can be put into a vector as its leaf.
-/// For example, this tree:
+/// A horizontal reduction is a tree of reduction instructions that has values
+/// that can be put into a vector as its leaves. For example:
 ///
 /// mul mul mul mul
 ///  \  /    \  /
 ///   +       +
 ///    \     /
 ///       +
-/// This tree has "mul" as its reduced values and "+" as its reduction
-/// operations. A reduction might be feeding into a store or a binary operation
+/// This tree has "mul" as its leaf values and "+" as its reduction
+/// instructions. A reduction can feed into a store or a binary operation
 /// feeding a phi.
 ///    ...
 ///    \  /
@@ -6475,15 +6466,20 @@ class HorizontalReduction {
 
     /// Checks if the reduction operation can be vectorized.
     bool isVectorizable() const {
-      // We currently only support add/mul/logical && min/max reductions.
-      return ((Kind == RK_Arithmetic &&
-               (Opcode == Instruction::Add || Opcode == Instruction::FAdd ||
-                Opcode == Instruction::Mul || Opcode == Instruction::FMul ||
-                Opcode == Instruction::And || Opcode == Instruction::Or ||
-                Opcode == Instruction::Xor)) ||
-              (Opcode == Instruction::ICmp &&
-               (Kind == RK_SMin || Kind == RK_SMax ||
-                Kind == RK_UMin || Kind == RK_UMax)));
+      switch (Kind) {
+      case RK_Arithmetic:
+        return Opcode == Instruction::Add || Opcode == Instruction::FAdd ||
+               Opcode == Instruction::Mul || Opcode == Instruction::FMul ||
+               Opcode == Instruction::And || Opcode == Instruction::Or ||
+               Opcode == Instruction::Xor;
+      case RK_SMin:
+      case RK_SMax:
+      case RK_UMin:
+      case RK_UMax:
+        return Opcode == Instruction::ICmp;
+      default:
+        return false;
+      }
     }
 
     /// Creates reduction operation with the current opcode.
@@ -6751,10 +6747,10 @@ class HorizontalReduction {
   WeakTrackingVH ReductionRoot;
 
   /// The operation data of the reduction operation.
-  OperationData ReductionData;
+  OperationData RdxTreeInst;
 
-  /// The operation data of the values we perform a reduction on.
-  OperationData ReducedValueData;
+  /// The operation data for the leaf values that we perform a reduction on.
+  OperationData RdxLeafVal;
 
   /// Should we model this reduction as a pairwise reduction tree or a tree that
   /// splits the vector in halves and adds those halves.
@@ -6772,7 +6768,8 @@ class HorizontalReduction {
       // in this case.
       // Do not perform analysis of remaining operands of ParentStackElem.first
       // instruction, this whole instruction is an extra argument.
-      ParentStackElem.second = ParentStackElem.first->getNumOperands();
+      OperationData OpData = getOperationData(ParentStackElem.first);
+      ParentStackElem.second = OpData.getNumberOfOperands();
     } else {
       // We ran into something like:
       // ParentStackElem.first += ... + ExtraArg + ...
@@ -6869,24 +6866,24 @@ class HorizontalReduction {
     assert((!Phi || is_contained(Phi->operands(), B)) &&
            "Thi phi needs to use the binary operator");
 
-    ReductionData = getOperationData(B);
+    RdxTreeInst = getOperationData(B);
 
     // We could have a initial reductions that is not an add.
     //  r *= v1 + v2 + v3 + v4
     // In such a case start looking for a tree rooted in the first '+'.
     if (Phi) {
-      if (ReductionData.getLHS(B) == Phi) {
+      if (RdxTreeInst.getLHS(B) == Phi) {
         Phi = nullptr;
-        B = dyn_cast<Instruction>(ReductionData.getRHS(B));
-        ReductionData = getOperationData(B);
-      } else if (ReductionData.getRHS(B) == Phi) {
+        B = dyn_cast<Instruction>(RdxTreeInst.getRHS(B));
+        RdxTreeInst = getOperationData(B);
+      } else if (RdxTreeInst.getRHS(B) == Phi) {
         Phi = nullptr;
-        B = dyn_cast<Instruction>(ReductionData.getLHS(B));
-        ReductionData = getOperationData(B);
+        B = dyn_cast<Instruction>(RdxTreeInst.getLHS(B));
+        RdxTreeInst = getOperationData(B);
       }
     }
 
-    if (!ReductionData.isVectorizable(B))
+    if (!RdxTreeInst.isVectorizable(B))
       return false;
 
     Type *Ty = B->getType();
@@ -6895,19 +6892,19 @@ class HorizontalReduction {
     if (!Ty->isIntOrIntVectorTy() && !Ty->isFPOrFPVectorTy())
       return false;
 
-    ReducedValueData.clear();
+    RdxLeafVal.clear();
     ReductionRoot = B;
 
     // Post order traverse the reduction tree starting at B. We only handle true
     // trees containing only binary operators.
     SmallVector<std::pair<Instruction *, unsigned>, 32> Stack;
-    Stack.push_back(std::make_pair(B, ReductionData.getFirstOperandIndex()));
-    ReductionData.initReductionOps(ReductionOps);
+    Stack.push_back(std::make_pair(B, RdxTreeInst.getFirstOperandIndex()));
+    RdxTreeInst.initReductionOps(ReductionOps);
     while (!Stack.empty()) {
       Instruction *TreeN = Stack.back().first;
       unsigned EdgeToVisit = Stack.back().second++;
       OperationData OpData = getOperationData(TreeN);
-      bool IsReducedValue = OpData != ReductionData;
+      bool IsReducedValue = OpData != RdxTreeInst;
 
       // Postorder vist.
       if (IsReducedValue || EdgeToVisit == OpData.getNumberOfOperands()) {
@@ -6928,7 +6925,7 @@ class HorizontalReduction {
             markExtraArg(Stack[Stack.size() - 2], TreeN);
             ExtraArgs.erase(TreeN);
           } else
-            ReductionData.addReductionOps(TreeN, ReductionOps);
+            RdxTreeInst.addReductionOps(TreeN, ReductionOps);
         }
         // Retract.
         Stack.pop_back();
@@ -6944,12 +6941,10 @@ class HorizontalReduction {
         // (possibly) a reduced value. If the reduced value opcode is not set,
         // the first met operation != reduction operation is considered as the
         // reduced value class.
-        if (I && (!ReducedValueData || OpData == ReducedValueData ||
-                  OpData == ReductionData)) {
-          const bool IsReductionOperation = OpData == ReductionData;
+        const bool IsRdxInst = OpData == RdxTreeInst;
+        if (I && (!RdxLeafVal || OpData == RdxLeafVal || IsRdxInst)) {
           // Only handle trees in the current basic block.
-          if (!ReductionData.hasSameParent(I, B->getParent(),
-                                           IsReductionOperation)) {
+          if (!RdxTreeInst.hasSameParent(I, B->getParent(), IsRdxInst)) {
             // I is an extra argument for TreeN (its parent operation).
             markExtraArg(Stack.back(), I);
             continue;
@@ -6957,31 +6952,28 @@ class HorizontalReduction {
 
           // Each tree node needs to have minimal number of users except for the
           // ultimate reduction.
-          if (!ReductionData.hasRequiredNumberOfUses(I,
-                                                     OpData == ReductionData) &&
-              I != B) {
+          if (!RdxTreeInst.hasRequiredNumberOfUses(I, IsRdxInst) && I != B) {
             // I is an extra argument for TreeN (its parent operation).
             markExtraArg(Stack.back(), I);
             continue;
           }
 
-          if (IsReductionOperation) {
+          if (IsRdxInst) {
             // We need to be able to reassociate the reduction operations.
             if (!OpData.isAssociative(I)) {
               // I is an extra argument for TreeN (its parent operation).
               markExtraArg(Stack.back(), I);
               continue;
             }
-          } else if (ReducedValueData &&
-                     ReducedValueData != OpData) {
+          } else if (RdxLeafVal && RdxLeafVal != OpData) {
             // Make sure that the opcodes of the operations that we are going to
             // reduce match.
             // I is an extra argument for TreeN (its parent operation).
             markExtraArg(Stack.back(), I);
             continue;
-          } else if (!ReducedValueData)
-            ReducedValueData = OpData;
-
+          } else if (!RdxLeafVal) {
+            RdxLeafVal = OpData;
+          }
           Stack.push_back(std::make_pair(I, OpData.getFirstOperandIndex()));
           continue;
         }
@@ -7081,7 +7073,7 @@ class HorizontalReduction {
       }
       if (V.isTreeTinyAndNotFullyVectorizable())
         break;
-      if (V.isLoadCombineReductionCandidate(ReductionData.getOpcode()))
+      if (V.isLoadCombineReductionCandidate(RdxTreeInst.getOpcode()))
         break;
 
       V.computeMinimumValueSizes();
@@ -7124,7 +7116,7 @@ class HorizontalReduction {
       // Emit a reduction. For min/max, the root is a select, but the insertion
       // point is the compare condition of that select.
       Instruction *RdxRootInst = cast<Instruction>(ReductionRoot);
-      if (ReductionData.isMinMax())
+      if (RdxTreeInst.isMinMax())
         Builder.SetInsertPoint(getCmpForMinMaxReduction(RdxRootInst));
       else
         Builder.SetInsertPoint(RdxRootInst);
@@ -7138,7 +7130,7 @@ class HorizontalReduction {
       } else {
         // Update the final value in the reduction.
         Builder.SetCurrentDebugLocation(Loc);
-        VectorizedTree = ReductionData.createOp(
+        VectorizedTree = RdxTreeInst.createOp(
             Builder, VectorizedTree, ReducedSubTree, "op.rdx", ReductionOps);
       }
       i += ReduxWidth;
@@ -7150,15 +7142,15 @@ class HorizontalReduction {
       for (; i < NumReducedVals; ++i) {
         auto *I = cast<Instruction>(ReducedVals[i]);
         Builder.SetCurrentDebugLocation(I->getDebugLoc());
-        VectorizedTree = ReductionData.createOp(Builder, VectorizedTree, I, "",
-                                                ReductionOps);
+        VectorizedTree = RdxTreeInst.createOp(Builder, VectorizedTree, I, "",
+                                              ReductionOps);
       }
       for (auto &Pair : ExternallyUsedValues) {
         // Add each externally used value to the final reduction.
         for (auto *I : Pair.second) {
           Builder.SetCurrentDebugLocation(I->getDebugLoc());
-          VectorizedTree = ReductionData.createOp(Builder, VectorizedTree,
-                                                  Pair.first, "op.extra", I);
+          VectorizedTree = RdxTreeInst.createOp(Builder, VectorizedTree,
+                                                Pair.first, "op.extra", I);
         }
       }
 
@@ -7166,7 +7158,7 @@ class HorizontalReduction {
       // select, we also have to RAUW for the compare instruction feeding the
       // reduction root. That's because the original compare may have extra uses
       // besides the final select of the reduction.
-      if (ReductionData.isMinMax()) {
+      if (RdxTreeInst.isMinMax()) {
         if (auto *VecSelect = dyn_cast<SelectInst>(VectorizedTree)) {
           Instruction *ScalarCmp =
               getCmpForMinMaxReduction(cast<Instruction>(ReductionRoot));
@@ -7195,13 +7187,13 @@ class HorizontalReduction {
 
     int PairwiseRdxCost;
     int SplittingRdxCost;
-    switch (ReductionData.getKind()) {
+    switch (RdxTreeInst.getKind()) {
     case RK_Arithmetic:
       PairwiseRdxCost =
-          TTI->getArithmeticReductionCost(ReductionData.getOpcode(), VecTy,
+          TTI->getArithmeticReductionCost(RdxTreeInst.getOpcode(), VecTy,
                                           /*IsPairwiseForm=*/true);
       SplittingRdxCost =
-          TTI->getArithmeticReductionCost(ReductionData.getOpcode(), VecTy,
+          TTI->getArithmeticReductionCost(RdxTreeInst.getOpcode(), VecTy,
                                           /*IsPairwiseForm=*/false);
       break;
     case RK_SMin:
@@ -7209,8 +7201,8 @@ class HorizontalReduction {
     case RK_UMin:
     case RK_UMax: {
       auto *VecCondTy = cast<VectorType>(CmpInst::makeCmpResultType(VecTy));
-      bool IsUnsigned = ReductionData.getKind() == RK_UMin ||
-                        ReductionData.getKind() == RK_UMax;
+      bool IsUnsigned = RdxTreeInst.getKind() == RK_UMin ||
+                        RdxTreeInst.getKind() == RK_UMax;
       PairwiseRdxCost =
           TTI->getMinMaxReductionCost(VecTy, VecCondTy,
                                       /*IsPairwiseForm=*/true, IsUnsigned);
@@ -7227,17 +7219,17 @@ class HorizontalReduction {
     int VecReduxCost = IsPairwiseReduction ? PairwiseRdxCost : SplittingRdxCost;
 
     int ScalarReduxCost = 0;
-    switch (ReductionData.getKind()) {
+    switch (RdxTreeInst.getKind()) {
     case RK_Arithmetic:
       ScalarReduxCost =
-          TTI->getArithmeticInstrCost(ReductionData.getOpcode(), ScalarTy);
+          TTI->getArithmeticInstrCost(RdxTreeInst.getOpcode(), ScalarTy);
       break;
     case RK_SMin:
     case RK_SMax:
     case RK_UMin:
     case RK_UMax:
       ScalarReduxCost =
-          TTI->getCmpSelInstrCost(ReductionData.getOpcode(), ScalarTy) +
+          TTI->getCmpSelInstrCost(RdxTreeInst.getOpcode(), ScalarTy) +
           TTI->getCmpSelInstrCost(Instruction::Select, ScalarTy,
                                   CmpInst::makeCmpResultType(ScalarTy));
       break;
@@ -7267,8 +7259,8 @@ class HorizontalReduction {
       //        to 'fast'.
       assert(Builder.getFastMathFlags().isFast() && "Expected 'fast' FMF");
       return createSimpleTargetReduction(
-          Builder, TTI, ReductionData.getOpcode(), VectorizedValue,
-          ReductionData.getFlags(), ReductionOps.back());
+          Builder, TTI, RdxTreeInst.getOpcode(), VectorizedValue,
+          RdxTreeInst.getFlags(), ReductionOps.back());
     }
 
     Value *TmpVec = VectorizedValue;
@@ -7280,8 +7272,8 @@ class HorizontalReduction {
           Builder.CreateShuffleVector(TmpVec, LeftMask, "rdx.shuf.l");
       Value *RightShuf =
           Builder.CreateShuffleVector(TmpVec, RightMask, "rdx.shuf.r");
-      TmpVec = ReductionData.createOp(Builder, LeftShuf, RightShuf, "op.rdx",
-                                      ReductionOps);
+      TmpVec = RdxTreeInst.createOp(Builder, LeftShuf, RightShuf, "op.rdx",
+                                    ReductionOps);
     }
 
     // The result is in the first element of the vector.
diff --git a/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h b/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
index 6f055ca80ff29..41679637167d5 100644
--- a/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
+++ b/llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
@@ -61,8 +61,8 @@ class VPRecipeBuilder {
   /// Check if the load or store instruction \p I should widened for \p
   /// Range.Start and potentially masked. Such instructions are handled by a
   /// recipe that takes an additional VPInstruction for the mask.
-  VPWidenMemoryInstructionRecipe *
-  tryToWidenMemory(Instruction *I, VFRange &Range, VPlanPtr &Plan);
+  VPRecipeBase *tryToWidenMemory(Instruction *I, VFRange &Range,
+                                 VPlanPtr &Plan);
 
   /// Check if an induction recipe should be constructed for \I. If so build and
   /// return it. If not, return null.
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp
index 516a07998854b..f5ce1a3ccafb9 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp
@@ -119,54 +119,6 @@ VPUser *VPRecipeBase::toVPUser() {
   return nullptr;
 }
 
-VPValue *VPRecipeBase::toVPValue() {
-  if (auto *V = dyn_cast<VPInstruction>(this))
-    return V;
-  if (auto *V = dyn_cast<VPReductionRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPWidenMemoryInstructionRecipe>(this)) {
-    if (!V->isStore())
-      return V->getVPValue();
-    else
-      return nullptr;
-  }
-  if (auto *V = dyn_cast<VPWidenCallRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPWidenSelectRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPWidenGEPRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPWidenRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPReplicateRecipe>(this))
-    return V;
-  return nullptr;
-}
-
-const VPValue *VPRecipeBase::toVPValue() const {
-  if (auto *V = dyn_cast<VPInstruction>(this))
-    return V;
-  if (auto *V = dyn_cast<VPReductionRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPWidenMemoryInstructionRecipe>(this)) {
-    if (!V->isStore())
-      return V->getVPValue();
-    else
-      return nullptr;
-  }
-  if (auto *V = dyn_cast<VPWidenCallRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPWidenSelectRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPWidenGEPRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPWidenRecipe>(this))
-    return V;
-  if (auto *V = dyn_cast<VPReplicateRecipe>(this))
-    return V;
-  return nullptr;
-}
-
 // Get the top-most entry block of \p Start. This is the entry block of the
 // containing VPlan. This function is templated to support both const and non-const blocks
 template <typename T> static T *getPlanEntry(T *Start) {
@@ -384,8 +336,8 @@ void VPBasicBlock::execute(VPTransformState *State) {
 
 void VPBasicBlock::dropAllReferences(VPValue *NewValue) {
   for (VPRecipeBase &R : Recipes) {
-    if (auto *VPV = R.toVPValue())
-      VPV->replaceAllUsesWith(NewValue);
+    for (auto *Def : R.definedValues())
+      Def->replaceAllUsesWith(NewValue);
 
     if (auto *User = R.toVPUser())
       for (unsigned I = 0, E = User->getNumOperands(); I != E; I++)
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h
index 02ae60990c632..e6635e788e184 100644
--- a/llvm/lib/Transforms/Vectorize/VPlan.h
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h
@@ -620,47 +620,23 @@ class VPBlockBase {
 };
 
 /// VPRecipeBase is a base class modeling a sequence of one or more output IR
-/// instructions.
-class VPRecipeBase : public ilist_node_with_parent<VPRecipeBase, VPBasicBlock> {
+/// instructions. VPRecipeBase owns the the VPValues it defines through VPDef
+/// and is responsible for deleting its defined values. Single-value
+/// VPRecipeBases that also inherit from VPValue must make sure to inherit from
+/// VPRecipeBase before VPValue.
+class VPRecipeBase : public ilist_node_with_parent<VPRecipeBase, VPBasicBlock>,
+                     public VPDef {
   friend VPBasicBlock;
   friend class VPBlockUtils;
 
-  const unsigned char SubclassID; ///< Subclass identifier (for isa/dyn_cast).
 
   /// Each VPRecipe belongs to a single VPBasicBlock.
   VPBasicBlock *Parent = nullptr;
 
 public:
-  /// An enumeration for keeping track of the concrete subclass of VPRecipeBase
-  /// that is actually instantiated. Values of this enumeration are kept in the
-  /// SubclassID field of the VPRecipeBase objects. They are used for concrete
-  /// type identification.
-  using VPRecipeTy = enum {
-    VPBlendSC,
-    VPBranchOnMaskSC,
-    VPInstructionSC,
-    VPInterleaveSC,
-    VPPredInstPHISC,
-    VPReductionSC,
-    VPReplicateSC,
-    VPWidenCallSC,
-    VPWidenCanonicalIVSC,
-    VPWidenGEPSC,
-    VPWidenIntOrFpInductionSC,
-    VPWidenMemoryInstructionSC,
-    VPWidenPHISC,
-    VPWidenSC,
-    VPWidenSelectSC
-  };
-
-  VPRecipeBase(const unsigned char SC) : SubclassID(SC) {}
+  VPRecipeBase(const unsigned char SC) : VPDef(SC) {}
   virtual ~VPRecipeBase() = default;
 
-  /// \return an ID for the concrete type of this object.
-  /// This is used to implement the classof checks. This should not be used
-  /// for any other purpose, as the values may change as LLVM evolves.
-  unsigned getVPRecipeID() const { return SubclassID; }
-
   /// \return the VPBasicBlock which this VPRecipe belongs to.
   VPBasicBlock *getParent() { return Parent; }
   const VPBasicBlock *getParent() const { return Parent; }
@@ -701,44 +677,41 @@ class VPRecipeBase : public ilist_node_with_parent<VPRecipeBase, VPBasicBlock> {
   /// nullptr otherwise.
   VPUser *toVPUser();
 
-  /// Returns a pointer to a VPValue, if the recipe inherits from VPValue or
-  /// nullptr otherwise.
-  VPValue *toVPValue();
-  const VPValue *toVPValue() const;
-
   /// Returns the underlying instruction, if the recipe is a VPValue or nullptr
   /// otherwise.
   Instruction *getUnderlyingInstr() {
-    if (auto *VPV = toVPValue())
-      return cast_or_null<Instruction>(VPV->getUnderlyingValue());
-    return nullptr;
+    return cast<Instruction>(getVPValue()->getUnderlyingValue());
   }
   const Instruction *getUnderlyingInstr() const {
-    if (auto *VPV = toVPValue())
-      return cast_or_null<Instruction>(VPV->getUnderlyingValue());
-    return nullptr;
+    return cast<Instruction>(getVPValue()->getUnderlyingValue());
+  }
+
+  /// Method to support type inquiry through isa, cast, and dyn_cast.
+  static inline bool classof(const VPDef *D) {
+    // All VPDefs are also VPRecipeBases.
+    return true;
   }
 };
 
-inline bool VPUser::classof(const VPRecipeBase *Recipe) {
-  return Recipe->getVPRecipeID() == VPRecipeBase::VPInstructionSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPWidenSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPWidenCallSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPWidenSelectSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPWidenGEPSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPBlendSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPInterleaveSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPReplicateSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPReductionSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPBranchOnMaskSC ||
-         Recipe->getVPRecipeID() == VPRecipeBase::VPWidenMemoryInstructionSC;
+inline bool VPUser::classof(const VPDef *Def) {
+  return Def->getVPDefID() == VPRecipeBase::VPInstructionSC ||
+         Def->getVPDefID() == VPRecipeBase::VPWidenSC ||
+         Def->getVPDefID() == VPRecipeBase::VPWidenCallSC ||
+         Def->getVPDefID() == VPRecipeBase::VPWidenSelectSC ||
+         Def->getVPDefID() == VPRecipeBase::VPWidenGEPSC ||
+         Def->getVPDefID() == VPRecipeBase::VPBlendSC ||
+         Def->getVPDefID() == VPRecipeBase::VPInterleaveSC ||
+         Def->getVPDefID() == VPRecipeBase::VPReplicateSC ||
+         Def->getVPDefID() == VPRecipeBase::VPReductionSC ||
+         Def->getVPDefID() == VPRecipeBase::VPBranchOnMaskSC ||
+         Def->getVPDefID() == VPRecipeBase::VPWidenMemoryInstructionSC;
 }
 
 /// This is a concrete Recipe that models a single VPlan-level instruction.
 /// While as any Recipe it may generate a sequence of IR instructions when
 /// executed, these instructions would always form a single-def expression as
 /// the VPInstruction is also a single def-use vertex.
-class VPInstruction : public VPUser, public VPValue, public VPRecipeBase {
+class VPInstruction : public VPRecipeBase, public VPUser, public VPValue {
   friend class VPlanSlp;
 
 public:
@@ -764,8 +737,15 @@ class VPInstruction : public VPUser, public VPValue, public VPRecipeBase {
 
 public:
   VPInstruction(unsigned Opcode, ArrayRef<VPValue *> Operands)
-      : VPUser(Operands), VPValue(VPValue::VPVInstructionSC),
-        VPRecipeBase(VPRecipeBase::VPInstructionSC), Opcode(Opcode) {}
+      : VPRecipeBase(VPRecipeBase::VPInstructionSC), VPUser(Operands),
+        VPValue(VPValue::VPVInstructionSC, nullptr, this), Opcode(Opcode) {}
+
+  VPInstruction(unsigned Opcode, ArrayRef<VPInstruction *> Operands)
+      : VPRecipeBase(VPRecipeBase::VPInstructionSC), VPUser({}),
+        VPValue(VPValue::VPVInstructionSC, nullptr, this), Opcode(Opcode) {
+    for (auto *I : Operands)
+      addOperand(I->getVPValue());
+  }
 
   VPInstruction(unsigned Opcode, std::initializer_list<VPValue *> Operands)
       : VPInstruction(Opcode, ArrayRef<VPValue *>(Operands)) {}
@@ -781,8 +761,8 @@ class VPInstruction : public VPUser, public VPValue, public VPRecipeBase {
   }
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *R) {
-    return R->getVPRecipeID() == VPRecipeBase::VPInstructionSC;
+  static inline bool classof(const VPDef *R) {
+    return R->getVPDefID() == VPRecipeBase::VPInstructionSC;
   }
 
   unsigned getOpcode() const { return Opcode; }
@@ -836,14 +816,14 @@ class VPWidenRecipe : public VPRecipeBase, public VPValue, public VPUser {
 public:
   template <typename IterT>
   VPWidenRecipe(Instruction &I, iterator_range<IterT> Operands)
-      : VPRecipeBase(VPRecipeBase::VPWidenSC), VPValue(VPValue::VPVWidenSC, &I),
-        VPUser(Operands) {}
+      : VPRecipeBase(VPRecipeBase::VPWidenSC),
+        VPValue(VPValue::VPVWidenSC, &I, this), VPUser(Operands) {}
 
   ~VPWidenRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPWidenSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPWidenSC;
   }
   static inline bool classof(const VPValue *V) {
     return V->getVPValueID() == VPValue::VPVWidenSC;
@@ -858,10 +838,7 @@ class VPWidenRecipe : public VPRecipeBase, public VPValue, public VPUser {
 };
 
 /// A recipe for widening Call instructions.
-class VPWidenCallRecipe : public VPRecipeBase,
-                          public VPDef,
-                          public VPUser,
-                          public VPValue {
+class VPWidenCallRecipe : public VPRecipeBase, public VPUser, public VPValue {
 
 public:
   template <typename IterT>
@@ -872,8 +849,8 @@ class VPWidenCallRecipe : public VPRecipeBase,
   ~VPWidenCallRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPWidenCallSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPWidenCallSC;
   }
 
   /// Produce a widened version of the call instruction.
@@ -885,10 +862,7 @@ class VPWidenCallRecipe : public VPRecipeBase,
 };
 
 /// A recipe for widening select instructions.
-class VPWidenSelectRecipe : public VPRecipeBase,
-                            public VPDef,
-                            public VPUser,
-                            public VPValue {
+class VPWidenSelectRecipe : public VPRecipeBase, public VPUser, public VPValue {
 
   /// Is the condition of the select loop invariant?
   bool InvariantCond;
@@ -904,8 +878,8 @@ class VPWidenSelectRecipe : public VPRecipeBase,
   ~VPWidenSelectRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPWidenSelectSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPWidenSelectSC;
   }
 
   /// Produce a widened version of the select instruction.
@@ -918,7 +892,6 @@ class VPWidenSelectRecipe : public VPRecipeBase,
 
 /// A recipe for handling GEP instructions.
 class VPWidenGEPRecipe : public VPRecipeBase,
-                         public VPDef,
                          public VPUser,
                          public VPValue {
   bool IsPtrLoopInvariant;
@@ -945,8 +918,8 @@ class VPWidenGEPRecipe : public VPRecipeBase,
   ~VPWidenGEPRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPWidenGEPSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPWidenGEPSC;
   }
 
   /// Generate the gep nodes.
@@ -965,12 +938,17 @@ class VPWidenIntOrFpInductionRecipe : public VPRecipeBase {
 
 public:
   VPWidenIntOrFpInductionRecipe(PHINode *IV, TruncInst *Trunc = nullptr)
-      : VPRecipeBase(VPWidenIntOrFpInductionSC), IV(IV), Trunc(Trunc) {}
+      : VPRecipeBase(VPWidenIntOrFpInductionSC), IV(IV), Trunc(Trunc) {
+    if (Trunc)
+      new VPValue(Trunc, this);
+    else
+      new VPValue(IV, this);
+  }
   ~VPWidenIntOrFpInductionRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPWidenIntOrFpInductionSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPWidenIntOrFpInductionSC;
   }
 
   /// Generate the vectorized and scalarized versions of the phi node as
@@ -987,12 +965,14 @@ class VPWidenPHIRecipe : public VPRecipeBase {
   PHINode *Phi;
 
 public:
-  VPWidenPHIRecipe(PHINode *Phi) : VPRecipeBase(VPWidenPHISC), Phi(Phi) {}
+  VPWidenPHIRecipe(PHINode *Phi) : VPRecipeBase(VPWidenPHISC), Phi(Phi) {
+    new VPValue(Phi, this);
+  }
   ~VPWidenPHIRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPWidenPHISC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPWidenPHISC;
   }
 
   /// Generate the phi/select nodes.
@@ -1014,6 +994,7 @@ class VPBlendRecipe : public VPRecipeBase, public VPUser {
   /// might be incoming with a full mask for which there is no VPValue.
   VPBlendRecipe(PHINode *Phi, ArrayRef<VPValue *> Operands)
       : VPRecipeBase(VPBlendSC), VPUser(Operands), Phi(Phi) {
+    new VPValue(Phi, this);
     assert(Operands.size() > 0 &&
            ((Operands.size() == 1) || (Operands.size() % 2 == 0)) &&
            "Expected either a single incoming value or a positive even number "
@@ -1021,8 +1002,8 @@ class VPBlendRecipe : public VPRecipeBase, public VPUser {
   }
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPBlendSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPBlendSC;
   }
 
   /// Return the number of incoming values, taking into account that a single
@@ -1055,7 +1036,14 @@ class VPInterleaveRecipe : public VPRecipeBase, public VPUser {
 public:
   VPInterleaveRecipe(const InterleaveGroup<Instruction> *IG, VPValue *Addr,
                      ArrayRef<VPValue *> StoredValues, VPValue *Mask)
-      : VPRecipeBase(VPInterleaveSC), VPUser({Addr}), IG(IG) {
+      : VPRecipeBase(VPInterleaveSC), VPUser(Addr), IG(IG) {
+    for (unsigned i = 0; i < IG->getFactor(); ++i)
+      if (Instruction *I = IG->getMember(i)) {
+        if (I->getType()->isVoidTy())
+          continue;
+        new VPValue(I, this);
+      }
+
     for (auto *SV : StoredValues)
       addOperand(SV);
     if (Mask) {
@@ -1066,8 +1054,8 @@ class VPInterleaveRecipe : public VPRecipeBase, public VPUser {
   ~VPInterleaveRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPInterleaveSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPInterleaveSC;
   }
 
   /// Return the address accessed by this recipe.
@@ -1104,7 +1092,7 @@ class VPInterleaveRecipe : public VPRecipeBase, public VPUser {
 /// A recipe to represent inloop reduction operations, performing a reduction on
 /// a vector operand into a scalar value, and adding the result to a chain.
 /// The Operands are {ChainOp, VecOp, [Condition]}.
-class VPReductionRecipe : public VPRecipeBase, public VPValue, public VPUser {
+class VPReductionRecipe : public VPRecipeBase, public VPUser, public VPValue {
   /// The recurrence decriptor for the reduction in question.
   RecurrenceDescriptor *RdxDesc;
   /// Fast math flags to use for the resulting reduction operation.
@@ -1116,9 +1104,9 @@ class VPReductionRecipe : public VPRecipeBase, public VPValue, public VPUser {
   VPReductionRecipe(RecurrenceDescriptor *R, Instruction *I, VPValue *ChainOp,
                     VPValue *VecOp, VPValue *CondOp, bool NoNaN,
                     const TargetTransformInfo *TTI)
-      : VPRecipeBase(VPRecipeBase::VPReductionSC),
-        VPValue(VPValue::VPVReductionSC, I), VPUser({ChainOp, VecOp}),
-        RdxDesc(R), NoNaN(NoNaN), TTI(TTI) {
+      : VPRecipeBase(VPRecipeBase::VPReductionSC), VPUser({ChainOp, VecOp}),
+        VPValue(VPValue::VPVReductionSC, I, this), RdxDesc(R), NoNaN(NoNaN),
+        TTI(TTI) {
     if (CondOp)
       addOperand(CondOp);
   }
@@ -1129,8 +1117,9 @@ class VPReductionRecipe : public VPRecipeBase, public VPValue, public VPUser {
   static inline bool classof(const VPValue *V) {
     return V->getVPValueID() == VPValue::VPVReductionSC;
   }
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPReductionSC;
+
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPReductionSC;
   }
 
   /// Generate the reduction in the loop
@@ -1169,7 +1158,7 @@ class VPReplicateRecipe : public VPRecipeBase, public VPUser, public VPValue {
   VPReplicateRecipe(Instruction *I, iterator_range<IterT> Operands,
                     bool IsUniform, bool IsPredicated = false)
       : VPRecipeBase(VPReplicateSC), VPUser(Operands),
-        VPValue(VPVReplicateSC, I), IsUniform(IsUniform),
+        VPValue(VPVReplicateSC, I, this), IsUniform(IsUniform),
         IsPredicated(IsPredicated) {
     // Retain the previous behavior of predicateInstructions(), where an
     // insert-element of a predicated instruction got hoisted into the
@@ -1182,8 +1171,8 @@ class VPReplicateRecipe : public VPRecipeBase, public VPUser, public VPValue {
   ~VPReplicateRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPReplicateSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPReplicateSC;
   }
 
   static inline bool classof(const VPValue *V) {
@@ -1213,8 +1202,8 @@ class VPBranchOnMaskRecipe : public VPRecipeBase, public VPUser {
   }
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPBranchOnMaskSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPBranchOnMaskSC;
   }
 
   /// Generate the extraction of the appropriate bit from the block mask and the
@@ -1252,12 +1241,14 @@ class VPPredInstPHIRecipe : public VPRecipeBase, public VPUser {
   /// Construct a VPPredInstPHIRecipe given \p PredInst whose value needs a phi
   /// nodes after merging back from a Branch-on-Mask.
   VPPredInstPHIRecipe(VPValue *PredV)
-      : VPRecipeBase(VPPredInstPHISC), VPUser(PredV) {}
+      : VPRecipeBase(VPPredInstPHISC), VPUser(PredV) {
+    new VPValue(VPValue::VPValueSC, PredV->getUnderlyingValue(), this);
+  }
   ~VPPredInstPHIRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPPredInstPHISC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPPredInstPHISC;
   }
 
   /// Generates phi nodes for live-outs as needed to retain SSA form.
@@ -1275,7 +1266,6 @@ class VPPredInstPHIRecipe : public VPRecipeBase, public VPUser {
 /// TODO: We currently execute only per-part unless a specific instance is
 /// provided.
 class VPWidenMemoryInstructionRecipe : public VPRecipeBase,
-                                       public VPDef,
                                        public VPUser {
   Instruction &Ingredient;
 
@@ -1305,8 +1295,8 @@ class VPWidenMemoryInstructionRecipe : public VPRecipeBase,
   }
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPWidenMemoryInstructionSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPWidenMemoryInstructionSC;
   }
 
   /// Return the address accessed by this recipe.
@@ -1340,21 +1330,16 @@ class VPWidenMemoryInstructionRecipe : public VPRecipeBase,
 
 /// A Recipe for widening the canonical induction variable of the vector loop.
 class VPWidenCanonicalIVRecipe : public VPRecipeBase {
-  /// A VPValue representing the canonical vector IV.
-  VPValue Val;
-
 public:
-  VPWidenCanonicalIVRecipe() : VPRecipeBase(VPWidenCanonicalIVSC) {}
-  ~VPWidenCanonicalIVRecipe() override = default;
+  VPWidenCanonicalIVRecipe() : VPRecipeBase(VPWidenCanonicalIVSC) {
+    new VPValue(nullptr, this);
+  }
 
-  /// Return the VPValue representing the canonical vector induction variable of
-  /// the vector loop.
-  const VPValue *getVPValue() const { return &Val; }
-  VPValue *getVPValue() { return &Val; }
+  ~VPWidenCanonicalIVRecipe() override = default;
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *V) {
-    return V->getVPRecipeID() == VPRecipeBase::VPWidenCanonicalIVSC;
+  static inline bool classof(const VPDef *D) {
+    return D->getVPDefID() == VPRecipeBase::VPWidenCanonicalIVSC;
   }
 
   /// Generate a canonical vector induction variable of the vector loop, with
@@ -2028,9 +2013,7 @@ class VPInterleavedAccessInfo {
   /// \returns nullptr if doesn't have such group.
   InterleaveGroup<VPInstruction> *
   getInterleaveGroup(VPInstruction *Instr) const {
-    if (InterleaveGroupMap.count(Instr))
-      return InterleaveGroupMap.find(Instr)->second;
-    return nullptr;
+    return InterleaveGroupMap.lookup(Instr);
   }
 };
 
diff --git a/llvm/lib/Transforms/Vectorize/VPlanValue.h b/llvm/lib/Transforms/Vectorize/VPlanValue.h
index 609a56d3fa23e..1ebe1f8204a56 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanValue.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanValue.h
@@ -45,6 +45,7 @@ class VPWidenMemoryInstructionRecipe;
 class VPValue {
   friend class VPBuilder;
   friend class VPDef;
+  friend class VPInstruction;
   friend struct VPlanTransforms;
   friend class VPBasicBlock;
   friend class VPInterleavedAccessInfo;
@@ -74,10 +75,6 @@ class VPValue {
   // for multiple underlying IRs (Polly?) by providing a new VPlan front-end,
   // back-end and analysis information for the new IR.
 
-  /// Return the underlying Value attached to this VPValue.
-  Value *getUnderlyingValue() { return UnderlyingVal; }
-  const Value *getUnderlyingValue() const { return UnderlyingVal; }
-
   // Set \p Val as the underlying Value of this VPValue.
   void setUnderlyingValue(Value *Val) {
     assert(!UnderlyingVal && "Underlying Value is already set.");
@@ -85,6 +82,10 @@ class VPValue {
   }
 
 public:
+  /// Return the underlying Value attached to this VPValue.
+  Value *getUnderlyingValue() { return UnderlyingVal; }
+  const Value *getUnderlyingValue() const { return UnderlyingVal; }
+
   /// An enumeration for keeping track of the concrete subclass of VPValue that
   /// are actually instantiated. Values of this enumeration are kept in the
   /// SubclassID field of the VPValue objects. They are used for concrete
@@ -236,7 +237,7 @@ class VPUser {
   }
 
   /// Method to support type inquiry through isa, cast, and dyn_cast.
-  static inline bool classof(const VPRecipeBase *Recipe);
+  static inline bool classof(const VPDef *Recipe);
 };
 
 /// This class augments a recipe with a set of VPValues defined by the recipe.
@@ -247,6 +248,9 @@ class VPUser {
 class VPDef {
   friend class VPValue;
 
+  /// Subclass identifier (for isa/dyn_cast).
+  const unsigned char SubclassID;
+
   /// The VPValues defined by this VPDef.
   TinyPtrVector<VPValue *> DefinedValues;
 
@@ -269,6 +273,30 @@ class VPDef {
   }
 
 public:
+  /// An enumeration for keeping track of the concrete subclass of VPRecipeBase
+  /// that is actually instantiated. Values of this enumeration are kept in the
+  /// SubclassID field of the VPRecipeBase objects. They are used for concrete
+  /// type identification.
+  using VPRecipeTy = enum {
+    VPBlendSC,
+    VPBranchOnMaskSC,
+    VPInstructionSC,
+    VPInterleaveSC,
+    VPPredInstPHISC,
+    VPReductionSC,
+    VPReplicateSC,
+    VPWidenCallSC,
+    VPWidenCanonicalIVSC,
+    VPWidenGEPSC,
+    VPWidenIntOrFpInductionSC,
+    VPWidenMemoryInstructionSC,
+    VPWidenPHISC,
+    VPWidenSC,
+    VPWidenSelectSC
+  };
+
+  VPDef(const unsigned char SC) : SubclassID(SC) {}
+
   virtual ~VPDef() {
     for (VPValue *D : make_early_inc_range(DefinedValues)) {
       assert(D->Def == this &&
@@ -295,6 +323,11 @@ class VPDef {
 
   /// Returns the number of values defined by the VPDef.
   unsigned getNumDefinedValues() const { return DefinedValues.size(); }
+
+  /// \return an ID for the concrete type of this object.
+  /// This is used to implement the classof checks. This should not be used
+  /// for any other purpose, as the values may change as LLVM evolves.
+  unsigned getVPDefID() const { return SubclassID; }
 };
 
 class VPlan;
diff --git a/llvm/test/Analysis/BasicAA/assume-index-positive.ll b/llvm/test/Analysis/BasicAA/assume-index-positive.ll
index e8a039a1018e8..54eb34a2cdb94 100644
--- a/llvm/test/Analysis/BasicAA/assume-index-positive.ll
+++ b/llvm/test/Analysis/BasicAA/assume-index-positive.ll
@@ -113,4 +113,20 @@ define void @test4(double* %ptr, i32 %skip) {
   ret void
 }
 
+define void @symmetry([0 x i8]* %ptr, i32 %a, i32 %b, i32 %c) {
+; CHECK-LABEL: Function: symmetry
+; CHECK: NoAlias: i8* %gep1, i8* %gep2
+;
+  %b.cmp = icmp slt i32 %b, 0
+  call void @llvm.assume(i1 %b.cmp)
+  %gep1 = getelementptr [0 x i8], [0 x i8]* %ptr, i32 %a, i32 %b
+  call void @barrier()
+  %c.cmp = icmp sgt i32 %c, -1
+  call void @llvm.assume(i1 %c.cmp)
+  %c.off = add nuw nsw i32 %c, 1
+  %gep2 = getelementptr [0 x i8], [0 x i8]* %ptr, i32 %a, i32 %c.off
+  ret void
+}
+
 declare void @llvm.assume(i1 %cond)
+declare void @barrier()
diff --git a/llvm/test/Analysis/BasicAA/noalias-param.ll b/llvm/test/Analysis/BasicAA/noalias-param.ll
index aab55595da2a9..81c89feaabb41 100644
--- a/llvm/test/Analysis/BasicAA/noalias-param.ll
+++ b/llvm/test/Analysis/BasicAA/noalias-param.ll
@@ -22,9 +22,9 @@ entry:
   ret void
 }
 
-; TODO: Result should be the same for byval instead of noalias.
+; Result should be the same for byval instead of noalias.
 ; CHECK-LABEL: byval
-; CHECK: MayAlias: i32* %a, i32* %b
+; CHECK: NoAlias: i32* %a, i32* %b
 define void @byval(i32* byval(i32) %a, i32* %b) nounwind {
 entry:
   store i32 1, i32* %a
diff --git a/llvm/test/Analysis/BasicAA/sequential-gep.ll b/llvm/test/Analysis/BasicAA/sequential-gep.ll
index b6e84fa971380..d7a1af024cec1 100644
--- a/llvm/test/Analysis/BasicAA/sequential-gep.ll
+++ b/llvm/test/Analysis/BasicAA/sequential-gep.ll
@@ -110,6 +110,17 @@ define void @add_non_zero_with_offset(i32* %p, i32 %addend, i32* %q) {
   ret void
 }
 
+; CHECK-LABEL: Function: add_non_zero_assume
+; CHECK: NoAlias: i32* %gep1, i32* %gep2
+define void @add_non_zero_assume(i32* %p, i32 %addend, i32 %knownnonzero) {
+  %cmp = icmp ne i32 %knownnonzero, 0
+  call void @llvm.assume(i1 %cmp)
+  %add = add i32 %addend, %knownnonzero
+  %gep1 = getelementptr i32, i32* %p, i32 %addend
+  %gep2 = getelementptr i32, i32* %p, i32 %add
+  ret void
+}
+
 ; CHECK-LABEL: non_zero_index_simple
 ; CHECK: NoAlias: i32* %gep, i32* %p
 ; CHECK: NoAlias: i16* %gep.16, i32* %p
@@ -135,4 +146,15 @@ define void @non_zero_index_with_offset(i32* %p, i32* %q) {
   ret void
 }
 
+; CHECK-LABEL: non_zero_index_assume
+; CHECK: NoAlias: i32* %gep, i32* %p
+define void @non_zero_index_assume(i32* %p, i32 %knownnonzero) {
+  %cmp = icmp ne i32 %knownnonzero, 0
+  call void @llvm.assume(i1 %cmp)
+  %gep = getelementptr i32, i32* %p, i32 %knownnonzero
+  ret void
+}
+
+declare void @llvm.assume(i1)
+
 !0 = !{ i32 1, i32 5 }
diff --git a/llvm/test/Analysis/BlockFrequencyInfo/redundant_edges.ll b/llvm/test/Analysis/BlockFrequencyInfo/redundant_edges.ll
index 2db9e024c15b1..c4ae0191eaab6 100644
--- a/llvm/test/Analysis/BlockFrequencyInfo/redundant_edges.ll
+++ b/llvm/test/Analysis/BlockFrequencyInfo/redundant_edges.ll
@@ -9,7 +9,7 @@ define void @test1() {
 entry:
   br label %loop
 
-; CHECK-NEXT: loop: float = 32.0
+; CHECK-NEXT: loop: float = 16.5
 loop:
   switch i32 undef, label %loop [
     i32 0, label %return
diff --git a/llvm/test/Analysis/BranchProbabilityInfo/basic.ll b/llvm/test/Analysis/BranchProbabilityInfo/basic.ll
index 901dc9fce645b..84d801aab4cb0 100644
--- a/llvm/test/Analysis/BranchProbabilityInfo/basic.ll
+++ b/llvm/test/Analysis/BranchProbabilityInfo/basic.ll
@@ -124,8 +124,8 @@ define i32 @test5(i32 %a, i32 %b, i1 %flag) {
 ; CHECK: Printing analysis {{.*}} for function 'test5'
 entry:
   br i1 %flag, label %then, label %else
-; CHECK: edge entry -> then probability is 0x07878788 / 0x80000000 = 5.88%
-; CHECK: edge entry -> else probability is 0x78787878 / 0x80000000 = 94.12% [HOT edge]
+; CHECK: edge entry -> then probability is 0x078780e3 / 0x80000000 = 5.88%
+; CHECK: edge entry -> else probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
 
 then:
   call void @coldfunc()
@@ -145,15 +145,16 @@ define i32 @test_cold_loop(i32 %a, i32 %b) {
 entry:
   %cond1 = icmp eq i32 %a, 42
   br i1 %cond1, label %header, label %exit
-
+; CHECK: edge entry -> header probability is 0x40000000 / 0x80000000 = 50.00%
+; CHECK: edge entry -> exit probability is 0x40000000 / 0x80000000 = 50.00%
 header:
   br label %body
 
 body:
   %cond2 = icmp eq i32 %b, 42
   br i1 %cond2, label %header, label %exit
-; CHECK: edge body -> header probability is 0x40000000 / 0x80000000 = 50.00%
-
+; CHECK: edge body -> header probability is 0x7fbe1203 / 0x80000000 = 99.80% [HOT edge]
+; CHECK: edge body -> exit probability is 0x0041edfd / 0x80000000 = 0.20%
 exit:
   call void @coldfunc()
   ret i32 %b
@@ -165,8 +166,8 @@ define i32 @test_cold_call_sites_with_prof(i32 %a, i32 %b, i1 %flag, i1 %flag2)
 ; CHECK: Printing analysis {{.*}} for function 'test_cold_call_sites_with_prof'
 entry:
   br i1 %flag, label %then, label %else
-; CHECK: edge entry -> then probability is 0x07878788 / 0x80000000 = 5.88%
-; CHECK: edge entry -> else probability is 0x78787878 / 0x80000000 = 94.12% [HOT edge]
+; CHECK: edge entry -> then probability is 0x078780e3 / 0x80000000 = 5.88%
+; CHECK: edge entry -> else probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
 
 then:
   br i1 %flag2, label %then2, label %else2, !prof !3
@@ -206,8 +207,8 @@ define i32 @test_cold_call_sites(i32* %a) {
 ; after that is fixed.
 
 ; CHECK: Printing analysis {{.*}} for function 'test_cold_call_sites'
-; CHECK: edge entry -> then probability is 0x07878788 / 0x80000000 = 5.88%
-; CHECK: edge entry -> else probability is 0x78787878 / 0x80000000 = 94.12% [HOT edge]
+; CHECK: edge entry -> then probability is 0x078780e3 / 0x80000000 = 5.88%
+; CHECK: edge entry -> else probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
 
 entry:
   %gep1 = getelementptr i32, i32* %a, i32 1
@@ -238,14 +239,14 @@ entry:
 ; Edge "entry->if.end" should have higher probability based on the cold call
 ; heuristic which treat %if.then as a cold block because the normal destination
 ; of the invoke instruction in %if.then is post-dominated by ColdFunc().
-; CHECK:  edge entry -> if.then probability is 0x07878788 / 0x80000000 = 5.88%
-; CHECK:  edge entry -> if.end probability is 0x78787878 / 0x80000000 = 94.12% [HOT edge]
+; CHECK:  edge entry -> if.then probability is 0x078780e3 / 0x80000000 = 5.88%
+; CHECK:  edge entry -> if.end probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
 
 if.then:
   invoke i32 @InvokeCall()
           to label %invoke.cont unwind label %lpad
-; CHECK:  edge if.then -> invoke.cont probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
-; CHECK:  edge if.then -> lpad probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK:  edge if.then -> invoke.cont probability is 0x7fff8000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK:  edge if.then -> lpad probability is 0x00008000 / 0x80000000 = 0.00%
 
 invoke.cont:
   call void @ColdFunc() #0
@@ -267,13 +268,12 @@ entry:
 
 ; CHECK:  edge entry -> if.then probability is 0x40000000 / 0x80000000 = 50.00%
 ; CHECK:  edge entry -> if.end probability is 0x40000000 / 0x80000000 = 50.00%
-
 if.then:
   invoke i32 @InvokeCall()
           to label %invoke.cont unwind label %lpad
 ; The cold call heuristic should not kick in when the cold callsite is in EH path.
-; CHECK:  edge if.then -> invoke.cont probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
-; CHECK:  edge if.then -> lpad probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK: edge if.then -> invoke.cont probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge if.then -> lpad probability is 0x00000800 / 0x80000000 = 0.00%
 
 invoke.cont:
   br label %if.end
@@ -292,16 +292,16 @@ if.end:
 define i32 @test_invoke_code_callsite3(i1 %c) personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
 entry:
   br i1 %c, label %if.then, label %if.end
-; CHECK: edge entry -> if.then probability is 0x07878788 / 0x80000000 = 5.88%
-; CHECK: edge entry -> if.end probability is 0x78787878 / 0x80000000 = 94.12% [HOT edge]
+; CHECK: edge entry -> if.then probability is 0x078780e3 / 0x80000000 = 5.88%
+; CHECK: edge entry -> if.end probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
 
 if.then:
   invoke i32 @InvokeCall()
           to label %invoke.cont unwind label %lpad
 ; Regardless of cold calls, edge weights from a invoke instruction should be
 ; determined by the invoke heuristic.
-; CHECK: edge if.then -> invoke.cont probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
-; CHECK: edge if.then -> lpad probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK: edge if.then -> invoke.cont probability is 0x7fff8000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge if.then -> lpad probability is 0x00008000 / 0x80000000 = 0.00%
 
 invoke.cont:
   call void @ColdFunc() #0
diff --git a/llvm/test/Analysis/BranchProbabilityInfo/deopt-intrinsic.ll b/llvm/test/Analysis/BranchProbabilityInfo/deopt-intrinsic.ll
index 541d7d954fb24..b40b5d7913929 100644
--- a/llvm/test/Analysis/BranchProbabilityInfo/deopt-intrinsic.ll
+++ b/llvm/test/Analysis/BranchProbabilityInfo/deopt-intrinsic.ll
@@ -9,8 +9,8 @@ entry:
   %cond = icmp eq i32 %a, 42
   br i1 %cond, label %exit, label %deopt
 
-; CHECK:  edge entry -> exit probability is 0x7fffffff / 0x80000000 = 100.00% [HOT edge]
-; CHECK:  edge entry -> deopt probability is 0x00000001 / 0x80000000 = 0.00%
+; CHECK:  edge entry -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK:  edge entry -> deopt probability is 0x00000000 / 0x80000000 = 0.00%
 
 deopt:
   %rval = call i32(...) @llvm.experimental.deoptimize.i32() [ "deopt"() ]
diff --git a/llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll b/llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll
new file mode 100644
index 0000000000000..0a552c6dc4d79
--- /dev/null
+++ b/llvm/test/Analysis/BranchProbabilityInfo/deopt-invoke.ll
@@ -0,0 +1,107 @@
+; RUN: opt -analyze -branch-prob < %s -enable-new-pm=0 | FileCheck %s
+; RUN: opt < %s -passes='print<branch-prob>' -disable-output 2>&1 | FileCheck %s
+
+declare i32* @"personality_function"() #1
+declare void @foo(i32)
+declare void @bar() 
+declare void @llvm.experimental.deoptimize.isVoid(...)
+declare void @cold() cold
+
+; Even though the likeliness of 'invoke' to throw an exception is assessed as low
+; all other paths are even less likely. Check that hot paths leads to excepion handler.
+define void @test1(i32 %0) personality i32* ()* @"personality_function"  !prof !1 {
+;CHECK: edge entry -> unreached probability is 0x00000001 / 0x80000000 = 0.00%
+;CHECK: edge entry -> invoke probability is 0x7fffffff / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge invoke -> invoke.cont.unreached probability is 0x00000000 / 0x80000000 = 0.00%
+;CHECK: edge invoke -> land.pad probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge land.pad -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+  br i1 undef, label %unreached, label %invoke, !prof !2
+invoke:
+  invoke void @foo(i32 %0)
+          to label %invoke.cont.unreached unwind label %land.pad
+invoke.cont.unreached:
+  call void (...) @llvm.experimental.deoptimize.isVoid(i32 10) [ "deopt"() ]
+  ret void
+
+unreached:
+  unreachable
+
+land.pad:
+  %v20 = landingpad { i8*, i32 }
+          cleanup
+  %v21 = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(256)* inttoptr (i64 8 to i8 addrspace(1)* addrspace(256)*), align 8
+  br label %exit
+
+exit:
+  call void @bar()
+  ret void
+}
+
+define void @test2(i32 %0) personality i32* ()* @"personality_function" {
+;CHECK: edge entry -> unreached probability is 0x00000000 / 0x80000000 = 0.00%
+;CHECK: edge entry -> invoke probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge invoke -> invoke.cont.cold probability is 0x7fff8000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge invoke -> land.pad probability is 0x00008000 / 0x80000000 = 0.00%
+;CHECK: edge land.pad -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+  br i1 undef, label %unreached, label %invoke
+invoke:
+  invoke void @foo(i32 %0)
+          to label %invoke.cont.cold unwind label %land.pad
+invoke.cont.cold:
+  call void @cold()
+  ret void
+
+unreached:
+  unreachable
+
+land.pad:
+  %v20 = landingpad { i8*, i32 }
+          cleanup
+  %v21 = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(256)* inttoptr (i64 8 to i8 addrspace(1)* addrspace(256)*), align 8
+  br label %exit
+
+exit:
+  call void @bar()
+  ret void
+}
+
+define void @test3(i32 %0) personality i32* ()* @"personality_function" {
+;CHECK: edge entry -> unreached probability is 0x00000000 / 0x80000000 = 0.00%
+;CHECK: edge entry -> invoke probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge invoke -> invoke.cont.cold probability is 0x7fff8000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge invoke -> land.pad probability is 0x00008000 / 0x80000000 = 0.00%
+;CHECK: edge land.pad -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+entry:
+  br i1 undef, label %unreached, label %invoke
+invoke:
+  invoke void @foo(i32 %0)
+          to label %invoke.cont.cold unwind label %land.pad
+invoke.cont.cold:
+  call void @cold()
+  ret void
+
+unreached:
+  unreachable
+
+land.pad:
+  %v20 = landingpad { i8*, i32 }
+          cleanup
+  %v21 = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(256)* inttoptr (i64 8 to i8 addrspace(1)* addrspace(256)*), align 8
+  call void @cold()
+  br label %exit
+
+exit:
+  call void @bar()
+  ret void
+}
+
+
+attributes #1 = { nounwind }
+
+!1 = !{!"function_entry_count", i64 32768}
+!2 = !{!"branch_weights", i32 1, i32 983040}
+
diff --git a/llvm/test/Analysis/BranchProbabilityInfo/loop.ll b/llvm/test/Analysis/BranchProbabilityInfo/loop.ll
index 26e041b652841..b3fa908064eb6 100644
--- a/llvm/test/Analysis/BranchProbabilityInfo/loop.ll
+++ b/llvm/test/Analysis/BranchProbabilityInfo/loop.ll
@@ -428,9 +428,8 @@ for.body:
   %inc = add nsw i32 %count.0, 1
   %cmp1 = icmp sgt i32 %count.0, 6
   br i1 %cmp1, label %if.then, label %for.inc
-; CHECK: edge for.body -> if.then probability is 0x2aaaaaab / 0x80000000 = 33.33%
-; CHECK: edge for.body -> for.inc probability is 0x55555555 / 0x80000000 = 66.67%
-
+; CHECK: edge for.body -> if.then probability is 0x2aaaa8e4 / 0x80000000 = 33.33%
+; CHECK: edge for.body -> for.inc probability is 0x5555571c / 0x80000000 = 66.67%
 if.then:
   store i32 %add, i32* %arrayidx, align 4
   br label %for.inc
@@ -521,3 +520,207 @@ exit:
 }
 
 declare i32 @InvokeCall()
+declare void @cold() cold
+
+; If loop has single exit and it leads to 'cold' block then edge leading to loop enter
+; should be considered 'cold' as well.
+define void @test13() {
+; CHECK: edge entry -> loop probability is 0x078780e3 / 0x80000000 = 5.88%
+; CHECK: edge entry -> exit probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
+; CHECK: edge loop -> loop probability is 0x7fbe1203 / 0x80000000 = 99.80% [HOT edge]
+; CHECK: edge loop -> cold probability is 0x0041edfd / 0x80000000 = 0.20%
+; CHECK: edge cold -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+  br i1 undef, label %loop, label %exit
+
+loop:
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %loop ]
+  %inc = add nsw i32 %i.0, 1
+  br i1 undef, label %loop, label %cold
+
+cold:
+  call void @cold()
+  br label %exit
+
+exit:
+  ret void
+}
+
+; This is the same case as test13 but with additional loop 'preheader' block.
+define void @test14() {
+; CHECK: edge entry -> preheader probability is 0x078780e3 / 0x80000000 = 5.88%
+; CHECK: edge entry -> exit probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
+; CHECK: edge preheader -> loop probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge loop -> loop probability is 0x7fbe1203 / 0x80000000 = 99.80% [HOT edge]
+; CHECK: edge loop -> cold probability is 0x0041edfd / 0x80000000 = 0.20%
+; CHECK: edge cold -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+  br i1 undef, label %preheader, label %exit
+
+preheader:
+  br label %loop
+
+loop:
+  %i.0 = phi i32 [ 0, %preheader ], [ %inc, %loop ]
+  %inc = add nsw i32 %i.0, 1
+  br i1 undef, label %loop, label %cold
+
+cold:
+  call void @cold()
+  br label %exit
+
+exit:
+  ret void
+}
+
+; If loop has multiple low probability exits then edge leading to loop enter
+; should be considered low probable as well.
+define void @test15() {
+; CHECK: edge entry -> loop probability is 0x078780e3 / 0x80000000 = 5.88%
+; CHECK: edge entry -> exit probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
+; CHECK: edge loop -> cont probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge loop -> unreached probability is 0x00000000 / 0x80000000 = 0.00%
+; CHECK: edge cont -> loop probability is 0x7fbe1203 / 0x80000000 = 99.80% [HOT edge]
+; CHECK: edge cont -> cold probability is 0x0041edfd / 0x80000000 = 0.20%
+; CHECK: edge cold -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+  br i1 undef, label %loop, label %exit
+
+loop:
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %cont ]
+  %inc = add nsw i32 %i.0, 1
+  br i1 undef, label %cont, label %unreached
+
+cont:
+  br i1 undef, label %loop, label %cold
+
+unreached:
+  unreachable
+
+
+cold:
+  call void @cold()
+  br label %exit
+
+exit:
+  ret void
+}
+
+; This is the same case as test15 but with additional loop 'preheader' block.
+define void @test16() {
+; CHECK: edge entry -> preheader probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge preheader -> loop probability is 0x078780e3 / 0x80000000 = 5.88%
+; CHECK: edge preheader -> exit probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
+; CHECK: edge loop -> cont probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge loop -> unreached probability is 0x00000000 / 0x80000000 = 0.00%
+; CHECK: edge cont -> loop probability is 0x7fbe1203 / 0x80000000 = 99.80% [HOT edge]
+; CHECK: edge cont -> cold probability is 0x0041edfd / 0x80000000 = 0.20%
+; CHECK: edge cold -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+  br label %preheader
+
+preheader:
+  br i1 undef, label %loop, label %exit
+
+loop:
+  %i.0 = phi i32 [ 0, %preheader ], [ %inc, %cont ]
+  %inc = add nsw i32 %i.0, 1
+  br i1 undef, label %cont, label %unreached
+
+cont:
+  br i1 undef, label %loop, label %cold
+
+unreached:
+  unreachable
+
+
+cold:
+  call void @cold()
+  br label %exit
+
+exit:
+  ret void
+}
+
+declare void @abort() noreturn
+
+; Check that 'preheader' has 50/50 probability since there is one 'normal' exit.
+; Check that exit to 'cold' and 'noreturn' has lower probability than 'normal' exit.
+define void @test17() {
+; CHECK: edge entry -> preheader probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge preheader -> loop probability is 0x40000000 / 0x80000000 = 50.00%
+; CHECK: edge preheader -> exit probability is 0x40000000 / 0x80000000 = 50.00%
+; CHECK: edge loop -> cont probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge loop -> noreturn probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK: edge cont -> cont2 probability is 0x7fbe1203 / 0x80000000 = 99.80% [HOT edge]
+; CHECK: edge cont -> cold probability is 0x0041edfd / 0x80000000 = 0.20%
+; CHECK: edge cont2 -> loop probability is 0x7c000000 / 0x80000000 = 96.88% [HOT edge]
+; CHECK: edge cont2 -> exit probability is 0x04000000 / 0x80000000 = 3.12%
+; CHECK: edge cold -> exit probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+entry:
+  br label %preheader
+
+preheader:
+  br i1 undef, label %loop, label %exit
+
+loop:
+  %i.0 = phi i32 [ 0, %preheader ], [ %inc, %cont2 ]
+  %inc = add nsw i32 %i.0, 1
+  br i1 undef, label %cont, label %noreturn
+
+cont:
+  br i1 undef, label %cont2, label %cold
+
+cont2:
+  br i1 undef, label %loop, label %exit
+
+noreturn:
+  call void @abort()
+  unreachable
+
+cold:
+  call void @cold()
+  br label %exit
+
+exit:
+  ret void
+}
+
+
+; This is case with two loops where one nested into another. Nested loop has
+; low probable exit what encreases robability to take exit in the top level loop.
+define void @test18() {
+; CHECK: edge entry -> top.loop probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge top.loop -> loop probability is 0x546cd4b7 / 0x80000000 = 65.96%
+; CHECK: edge top.loop -> exit probability is 0x2b932b49 / 0x80000000 = 34.04%
+; CHECK: edge loop -> loop probability is 0x7fbe1203 / 0x80000000 = 99.80% [HOT edge]
+; CHECK: edge loop -> cold probability is 0x0041edfd / 0x80000000 = 0.20%
+; CHECK: edge cold -> top.loop probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+ br label %top.loop 
+
+top.loop:
+  %j.0 = phi i32 [ 0, %entry ], [ %j.inc, %cold ]
+  br i1 undef, label %loop, label %exit
+
+loop:
+  %i.0 = phi i32 [ %j.0, %top.loop ], [ %inc, %loop ]
+  %inc = add nsw i32 %i.0, 1
+  br i1 undef, label %loop, label %cold
+
+cold:
+  call void @cold()
+  %j.inc = add nsw i32 %j.0, 1
+  br label %top.loop
+
+exit:
+  ret void
+}
+
+
+
diff --git a/llvm/test/Analysis/BranchProbabilityInfo/noreturn.ll b/llvm/test/Analysis/BranchProbabilityInfo/noreturn.ll
index 8c23a1d3bfc9a..e42a2d83b0c6a 100644
--- a/llvm/test/Analysis/BranchProbabilityInfo/noreturn.ll
+++ b/llvm/test/Analysis/BranchProbabilityInfo/noreturn.ll
@@ -9,8 +9,8 @@ define i32 @test1(i32 %a, i32 %b) {
 entry:
   %cond = icmp eq i32 %a, 42
   br i1 %cond, label %exit, label %abort
-; CHECK: edge entry -> exit probability is 0x7fffffff / 0x80000000 = 100.00% [HOT edge]
-; CHECK: edge entry -> abort probability is 0x00000001 / 0x80000000 = 0.00%
+; CHECK: edge entry -> exit probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge entry -> abort probability is 0x00000800 / 0x80000000 = 0.00%
 
 abort:
   call void @abort() noreturn
@@ -27,11 +27,11 @@ entry:
                               i32 2, label %case_b
                               i32 3, label %case_c
                               i32 4, label %case_d]
-; CHECK: edge entry -> exit probability is 0x7ffffffc / 0x80000000 = 100.00% [HOT edge]
-; CHECK: edge entry -> case_a probability is 0x00000001 / 0x80000000 = 0.00%
-; CHECK: edge entry -> case_b probability is 0x00000001 / 0x80000000 = 0.00%
-; CHECK: edge entry -> case_c probability is 0x00000001 / 0x80000000 = 0.00%
-; CHECK: edge entry -> case_d probability is 0x00000001 / 0x80000000 = 0.00%
+; CHECK: edge entry -> exit probability is 0x7fffe000 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge entry -> case_a probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK: edge entry -> case_b probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK: edge entry -> case_c probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK: edge entry -> case_d probability is 0x00000800 / 0x80000000 = 0.00%
 
 case_a:
   br label %case_b
@@ -56,8 +56,8 @@ define i32 @test3(i32 %a, i32 %b) {
 entry:
   %cond1 = icmp eq i32 %a, 42
   br i1 %cond1, label %exit, label %dom
-; CHECK: edge entry -> exit probability is 0x7fffffff / 0x80000000 = 100.00% [HOT edge]
-; CHECK: edge entry -> dom probability is 0x00000001 / 0x80000000 = 0.00%
+; CHECK: edge entry -> exit probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge entry -> dom probability is 0x00000800 / 0x80000000 = 0.00%
 
 dom:
   %cond2 = icmp ult i32 %a, 42
@@ -85,8 +85,8 @@ define i32 @test4(i32 %a, i32 %b) {
 entry:
   %cond1 = icmp eq i32 %a, 42
   br i1 %cond1, label %header, label %exit
-; CHECK: edge entry -> header probability is 0x00000001 / 0x80000000 = 0.00%
-; CHECK: edge entry -> exit probability is 0x7fffffff / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge entry -> header probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK: edge entry -> exit probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
 
 header:
   br label %body
@@ -94,9 +94,8 @@ header:
 body:
   %cond2 = icmp eq i32 %a, 42
   br i1 %cond2, label %header, label %abort
-; CHECK: edge body -> header probability is 0x40000000 / 0x80000000 = 50.00%
-; CHECK: edge body -> abort probability is 0x40000000 / 0x80000000 = 50.00%
-
+; CHECK: edge body -> header probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge body -> abort probability is 0x00000800 / 0x80000000 = 0.00%
 abort:
   call void @abort() noreturn
   unreachable
@@ -113,15 +112,15 @@ define i32 @throwSmallException(i32 %idx, i32 %limit) #0 personality i8* bitcast
 entry:
   %cmp = icmp sge i32 %idx, %limit
   br i1 %cmp, label %if.then, label %if.end
-; CHECK: edge entry -> if.then probability is 0x00000001 / 0x80000000 = 0.00%
-; CHECK: edge entry -> if.end probability is 0x7fffffff / 0x80000000 = 100.00% [HOT edge]
+; CHECK: edge entry -> if.then probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK: edge entry -> if.end probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
 
 if.then:                                          ; preds = %entry
   %exception = call i8* @__cxa_allocate_exception(i64 1) #0
   invoke i32 @smallFunction(i32 %idx)
           to label %invoke.cont unwind label %lpad
-; CHECK: edge if.then -> invoke.cont probability is 0x7ffff800 / 0x80000000 = 100.00% [HOT edge]
-; CHECK: edge if.then -> lpad probability is 0x00000800 / 0x80000000 = 0.00%
+; CHECK: edge if.then -> invoke.cont probability is 0x40000000 / 0x80000000 = 50.00%
+; CHECK: edge if.then -> lpad probability is 0x40000000 / 0x80000000 = 50.00%
 
 invoke.cont:                                      ; preds = %if.then
   call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi  to i8*), i8* null) #1
diff --git a/llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll b/llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll
new file mode 100644
index 0000000000000..e7c9e0b447bee
--- /dev/null
+++ b/llvm/test/Analysis/BranchProbabilityInfo/unreachable.ll
@@ -0,0 +1,154 @@
+; RUN: opt -analyze -branch-prob < %s -enable-new-pm=0 | FileCheck %s
+; RUN: opt < %s -passes='print<branch-prob>' -disable-output 2>&1 | FileCheck %s
+
+declare void @bar() cold
+
+; Both 'l1' and 'r1' has one edge leading to 'cold' and another one to
+; 'unreachable' blocks. Check that 'cold' paths are preferred. Also ensure both
+; paths from 'entry' block are equal.
+define void @test1(i32 %0) {
+;CHECK: edge entry -> l1 probability is 0x40000000 / 0x80000000 = 50.00%
+;CHECK: edge entry -> r1 probability is 0x40000000 / 0x80000000 = 50.00%
+;CHECK: edge l1 -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge l1 -> unreached probability is 0x00000000 / 0x80000000 = 0.00%
+;CHECK: edge r1 -> unreached probability is 0x00000000 / 0x80000000 = 0.00%
+;CHECK: edge r1 -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+  br i1 undef, label %l1, label %r1
+
+l1:
+  br i1 undef, label %cold, label %unreached
+
+r1:
+  br i1 undef, label %unreached, label %cold
+
+unreached:
+  unreachable
+
+cold:
+  call void @bar()
+  ret void
+}
+
+; Both edges of 'l1' leads to 'cold' blocks while one edge of 'r1' leads to
+; 'unreachable' block. Check that 'l1' has 50/50 while 'r1' has 0/100
+; distributuion. Also ensure both paths from 'entry' block are equal.
+define void @test2(i32 %0) {
+;CHECK: edge entry -> l1 probability is 0x40000000 / 0x80000000 = 50.00%
+;CHECK: edge entry -> r1 probability is 0x40000000 / 0x80000000 = 50.00%
+;CHECK: edge l1 -> cold probability is 0x40000000 / 0x80000000 = 50.00%
+;CHECK: edge l1 -> cold2 probability is 0x40000000 / 0x80000000 = 50.00%
+;CHECK: edge r1 -> unreached probability is 0x00000000 / 0x80000000 = 0.00%
+;CHECK: edge r1 -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+  br i1 undef, label %l1, label %r1
+
+l1:
+  br i1 undef, label %cold, label %cold2
+
+r1:
+  br i1 undef, label %unreached, label %cold
+
+unreached:
+  unreachable
+
+cold:
+  call void @bar()
+  ret void
+
+cold2:
+  call void @bar()
+  ret void
+}
+
+; Both edges of 'r1' leads to 'unreachable' blocks while one edge of 'l1' leads to
+; 'cold' block. Ensure that path leading to 'cold' block is preferred.
+define void @test3(i32 %0) {
+;CHECK: edge entry -> l1 probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge entry -> r1 probability is 0x00000000 / 0x80000000 = 0.00%
+;CHECK: edge l1 -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge l1 -> unreached probability is 0x00000000 / 0x80000000 = 0.00%
+;CHECK: edge r1 -> unreached probability is 0x40000000 / 0x80000000 = 50.00%
+;CHECK: edge r1 -> unreached2 probability is 0x40000000 / 0x80000000 = 50.00%
+
+entry:
+  br i1 undef, label %l1, label %r1
+
+l1:
+  br i1 undef, label %cold, label %unreached
+
+r1:
+  br i1 undef, label %unreached, label %unreached2
+
+unreached:
+  unreachable
+
+unreached2:
+  unreachable
+
+cold:
+  call void @bar()
+  ret void
+}
+
+; Left edge of 'entry' leads to 'cold' block while right edge is 'normal' continuation.
+; Check that we able to propagate 'cold' weight to 'entry' block. Also ensure
+; both edges from 'l1' are equally likely.
+define void @test4(i32 %0) {
+;CHECK: edge entry -> l1 probability is 0x078780e3 / 0x80000000 = 5.88%
+;CHECK: edge entry -> r1 probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
+;CHECK: edge l1 -> l2 probability is 0x40000000 / 0x80000000 = 50.00%
+;CHECK: edge l1 -> r2 probability is 0x40000000 / 0x80000000 = 50.00%
+;CHECK: edge l2 -> to.cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge r2 -> to.cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge to.cold -> cold probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+
+entry:
+  br i1 undef, label %l1, label %r1
+
+l1:
+  br i1 undef, label %l2, label %r2
+
+l2:
+  br label %to.cold
+
+r2:
+  br label %to.cold
+
+to.cold:
+ br label %cold
+
+r1:
+ ret void
+
+cold:
+  call void @bar()
+  ret void
+}
+
+; Check that most likely path from 'entry' to 'l2' through 'r1' is preferred.
+define void @test5(i32 %0) {
+;CHECK: edge entry -> cold probability is 0x078780e3 / 0x80000000 = 5.88%
+;CHECK: edge entry -> r1 probability is 0x78787f1d / 0x80000000 = 94.12% [HOT edge]
+;CHECK: edge cold -> l2 probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge r1 -> l2 probability is 0x80000000 / 0x80000000 = 100.00% [HOT edge]
+;CHECK: edge r1 -> unreached probability is 0x00000000 / 0x80000000 = 0.00%
+
+entry:
+  br i1 undef, label %cold, label %r1
+
+cold:
+  call void @bar()
+  br label %l2
+
+r1:
+  br i1 undef, label %l2, label %unreached
+
+l2:
+  ret void
+
+unreached:
+  unreachable
+}
diff --git a/llvm/test/Analysis/CostModel/AArch64/kryo-inseltpoison.ll b/llvm/test/Analysis/CostModel/AArch64/kryo-inseltpoison.ll
new file mode 100644
index 0000000000000..cb9f992f6c88c
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/AArch64/kryo-inseltpoison.ll
@@ -0,0 +1,26 @@
+; RUN: opt < %s -cost-model -analyze -mcpu=kryo | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+; CHECK-LABEL: vectorInstrCost
+define void @vectorInstrCost() {
+
+    ; Vector extracts - extracting the first element should have a zero cost;
+    ; all other elements should have a cost of two.
+    ;
+    ; CHECK: cost of 0 {{.*}} extractelement <2 x i64> undef, i32 0
+    ; CHECK: cost of 2 {{.*}} extractelement <2 x i64> undef, i32 1
+    %t1 = extractelement <2 x i64> undef, i32 0
+    %t2 = extractelement <2 x i64> undef, i32 1
+
+    ; Vector inserts - inserting the first element should have a zero cost; all
+    ; other elements should have a cost of two.
+    ;
+    ; CHECK: cost of 0 {{.*}} insertelement <2 x i64> poison, i64 undef, i32 0
+    ; CHECK: cost of 2 {{.*}} insertelement <2 x i64> poison, i64 undef, i32 1
+    %t3 = insertelement <2 x i64> poison, i64 undef, i32 0
+    %t4 = insertelement <2 x i64> poison, i64 undef, i32 1
+
+    ret void
+}
diff --git a/llvm/test/Analysis/CostModel/PowerPC/insert_extract-inseltpoison.ll b/llvm/test/Analysis/CostModel/PowerPC/insert_extract-inseltpoison.ll
new file mode 100644
index 0000000000000..c2fc2cd0a90b0
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/PowerPC/insert_extract-inseltpoison.ll
@@ -0,0 +1,187 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck --check-prefix=CHECK-P7 %s
+; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=+vsx | FileCheck --check-prefix=CHECK-P8LE %s
+; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr9 -mattr=+vsx | FileCheck --check-prefix=CHECK-P9BE %s
+; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -mattr=+vsx | FileCheck --check-prefix=CHECK-P9LE %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+define i32 @insert(i32 %arg) {
+  ; CHECK: cost of 10 {{.*}} insertelement
+; CHECK-P7-LABEL: 'insert'
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %x = insertelement <4 x i32> poison, i32 %arg, i32 0
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; CHECK-P8LE-LABEL: 'insert'
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %x = insertelement <4 x i32> poison, i32 %arg, i32 0
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; CHECK-P9BE-LABEL: 'insert'
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %x = insertelement <4 x i32> poison, i32 %arg, i32 0
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; CHECK-P9LE-LABEL: 'insert'
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %x = insertelement <4 x i32> poison, i32 %arg, i32 0
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+  %x = insertelement <4 x i32> poison, i32 %arg, i32 0
+  ret i32 undef
+}
+
+define i32 @extract(<4 x i32> %arg) {
+  ; CHECK: cost of 3 {{.*}} extractelement
+; CHECK-P7-LABEL: 'extract'
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %x = extractelement <4 x i32> %arg, i32 0
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 %x
+;
+; CHECK-P8LE-LABEL: 'extract'
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %x = extractelement <4 x i32> %arg, i32 0
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 %x
+;
+; CHECK-P9BE-LABEL: 'extract'
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %x = extractelement <4 x i32> %arg, i32 0
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 %x
+;
+; CHECK-P9LE-LABEL: 'extract'
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %x = extractelement <4 x i32> %arg, i32 0
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 %x
+;
+  %x = extractelement <4 x i32> %arg, i32 0
+  ret i32 %x
+}
+
+define void @test2xdouble(<2 x double> %arg1) {
+; CHECK-P7-LABEL: 'test2xdouble'
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v1 = extractelement <2 x double> %arg1, i32 0
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2 = extractelement <2 x double> %arg1, i32 1
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P8LE-LABEL: 'test2xdouble'
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v1 = extractelement <2 x double> %arg1, i32 0
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2 = extractelement <2 x double> %arg1, i32 1
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9BE-LABEL: 'test2xdouble'
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v1 = extractelement <2 x double> %arg1, i32 0
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2 = extractelement <2 x double> %arg1, i32 1
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9LE-LABEL: 'test2xdouble'
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v1 = extractelement <2 x double> %arg1, i32 0
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2 = extractelement <2 x double> %arg1, i32 1
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %v1 = extractelement <2 x double> %arg1, i32 0
+  %v2 = extractelement <2 x double> %arg1, i32 1
+  ret void
+}
+
+define void @test4xi32(<4 x i32> %v1, i32 %x1) {
+; CHECK-P7-LABEL: 'test4xi32'
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %v2 = insertelement <4 x i32> %v1, i32 %x1, i32 2
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P8LE-LABEL: 'test4xi32'
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2 = insertelement <4 x i32> %v1, i32 %x1, i32 2
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9BE-LABEL: 'test4xi32'
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2 = insertelement <4 x i32> %v1, i32 %x1, i32 2
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9LE-LABEL: 'test4xi32'
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2 = insertelement <4 x i32> %v1, i32 %x1, i32 2
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %v2 = insertelement <4 x i32> %v1, i32 %x1, i32 2
+  ret void
+}
+
+define void @vexti32(<4 x i32> %p1) {
+; CHECK-P7-LABEL: 'vexti32'
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i1 = extractelement <4 x i32> %p1, i32 0
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i2 = extractelement <4 x i32> %p1, i32 1
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i3 = extractelement <4 x i32> %p1, i32 2
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i4 = extractelement <4 x i32> %p1, i32 3
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P8LE-LABEL: 'vexti32'
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i1 = extractelement <4 x i32> %p1, i32 0
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i2 = extractelement <4 x i32> %p1, i32 1
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i3 = extractelement <4 x i32> %p1, i32 2
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i4 = extractelement <4 x i32> %p1, i32 3
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9BE-LABEL: 'vexti32'
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i1 = extractelement <4 x i32> %p1, i32 0
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i2 = extractelement <4 x i32> %p1, i32 1
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i3 = extractelement <4 x i32> %p1, i32 2
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i4 = extractelement <4 x i32> %p1, i32 3
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9LE-LABEL: 'vexti32'
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i1 = extractelement <4 x i32> %p1, i32 0
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i2 = extractelement <4 x i32> %p1, i32 1
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i3 = extractelement <4 x i32> %p1, i32 2
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i4 = extractelement <4 x i32> %p1, i32 3
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %i1 = extractelement <4 x i32> %p1, i32 0
+  %i2 = extractelement <4 x i32> %p1, i32 1
+  %i3 = extractelement <4 x i32> %p1, i32 2
+  %i4 = extractelement <4 x i32> %p1, i32 3
+  ret void
+}
+
+define void @vexti64(<2 x i64> %p1) {
+; CHECK-P7-LABEL: 'vexti64'
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i1 = extractelement <2 x i64> %p1, i32 0
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i2 = extractelement <2 x i64> %p1, i32 1
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P8LE-LABEL: 'vexti64'
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i1 = extractelement <2 x i64> %p1, i32 0
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i2 = extractelement <2 x i64> %p1, i32 1
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9BE-LABEL: 'vexti64'
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i1 = extractelement <2 x i64> %p1, i32 0
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i2 = extractelement <2 x i64> %p1, i32 1
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9LE-LABEL: 'vexti64'
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i1 = extractelement <2 x i64> %p1, i32 0
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i2 = extractelement <2 x i64> %p1, i32 1
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %i1 = extractelement <2 x i64> %p1, i32 0
+  %i2 = extractelement <2 x i64> %p1, i32 1
+  ret void
+}
+
+define void @vext(<8 x i16> %p1, <16 x i8> %p2) {
+; CHECK-P7-LABEL: 'vext'
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i1 = extractelement <8 x i16> %p1, i32 0
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i2 = extractelement <16 x i8> %p2, i32 0
+; CHECK-P7-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P8LE-LABEL: 'vext'
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i1 = extractelement <8 x i16> %p1, i32 0
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %i2 = extractelement <16 x i8> %p2, i32 0
+; CHECK-P8LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9BE-LABEL: 'vext'
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i1 = extractelement <8 x i16> %p1, i32 0
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i2 = extractelement <16 x i8> %p2, i32 0
+; CHECK-P9BE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; CHECK-P9LE-LABEL: 'vext'
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i1 = extractelement <8 x i16> %p1, i32 0
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i2 = extractelement <16 x i8> %p2, i32 0
+; CHECK-P9LE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %i1 = extractelement <8 x i16> %p1, i32 0
+  %i2 = extractelement <16 x i8> %p2, i32 0
+  ret void
+}
diff --git a/llvm/test/Analysis/CostModel/SystemZ/vectorinstrs-inseltpoison.ll b/llvm/test/Analysis/CostModel/SystemZ/vectorinstrs-inseltpoison.ll
new file mode 100644
index 0000000000000..696550a861a51
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/SystemZ/vectorinstrs-inseltpoison.ll
@@ -0,0 +1,56 @@
+; RUN: opt < %s -cost-model -analyze -mtriple=systemz-unknown -mcpu=z13 | FileCheck %s
+
+; CHECK: vecinstrs
+define void @vecinstrs() {
+
+  ;; Extract element is penalized somewhat with a cost of 2 for index 0.
+  extractelement <16 x i8> undef, i32 0
+  extractelement <16 x i8> undef, i32 1
+
+  extractelement <8 x i16> undef, i32 0
+  extractelement <8 x i16> undef, i32 1
+
+  extractelement <4 x i32> undef, i32 0
+  extractelement <4 x i32> undef, i32 1
+
+  extractelement <2 x i64> undef, i32 0
+  extractelement <2 x i64> undef, i32 1
+
+  extractelement <2 x double> undef, i32 0
+  extractelement <2 x double> undef, i32 1
+
+  ; Extraction of i1 means extract + test under mask before branch.
+  extractelement <2 x i1> undef, i32 0
+  extractelement <4 x i1> undef, i32 1
+  extractelement <8 x i1> undef, i32 2
+
+  ;; Insert element
+  insertelement <16 x i8> poison, i8 undef, i32 0
+  insertelement <8 x i16> poison, i16 undef, i32 0
+  insertelement <4 x i32> poison, i32 undef, i32 0
+
+  ; vlvgp will do two grs into a vector register: only add cost half of the time.
+  insertelement <2 x i64> poison, i64 undef, i32 0
+  insertelement <2 x i64> poison, i64 undef, i32 1
+
+  ret void
+
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %1 = extractelement <16 x i8> undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %2 = extractelement <16 x i8> undef, i32 1
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %3 = extractelement <8 x i16> undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %4 = extractelement <8 x i16> undef, i32 1
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %5 = extractelement <4 x i32> undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %6 = extractelement <4 x i32> undef, i32 1
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %7 = extractelement <2 x i64> undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %8 = extractelement <2 x i64> undef, i32 1
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %9 = extractelement <2 x double> undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %10 = extractelement <2 x double> undef, i32 1
+; CHECK: Cost Model: Found an estimated cost of 3 for instruction:   %11 = extractelement <2 x i1> undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %12 = extractelement <4 x i1> undef, i32 1
+; CHECK: Cost Model: Found an estimated cost of 2 for instruction:   %13 = extractelement <8 x i1> undef, i32 2
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %14 = insertelement <16 x i8> poison, i8 undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %15 = insertelement <8 x i16> poison, i16 undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %16 = insertelement <4 x i32> poison, i32 undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 1 for instruction:   %17 = insertelement <2 x i64> poison, i64 undef, i32 0
+; CHECK: Cost Model: Found an estimated cost of 0 for instruction:   %18 = insertelement <2 x i64> poison, i64 undef, i32 1
+}
diff --git a/llvm/test/Analysis/CostModel/X86/insert-extract-at-zero-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/insert-extract-at-zero-inseltpoison.ll
new file mode 100644
index 0000000000000..0d5b07c4c0f81
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/insert-extract-at-zero-inseltpoison.ll
@@ -0,0 +1,40 @@
+; RUN: opt < %s  -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+define i32 @insert-extract-at-zero-idx(i32 %arg, float %fl) {
+  ;CHECK: cost of 0 {{.*}} extract
+  %A = extractelement <4 x float> undef, i32 0
+  ;CHECK: cost of 1 {{.*}} extract
+  %B = extractelement <4 x i32> undef, i32 0
+  ;CHECK: cost of 1 {{.*}} extract
+  %C = extractelement <4 x float> undef, i32 1
+
+  ;CHECK: cost of 0 {{.*}} extract
+  %D = extractelement <8 x float> undef, i32 0
+  ;CHECK: cost of 1 {{.*}} extract
+  %E = extractelement <8 x float> undef, i32 1
+
+  ;CHECK: cost of 1 {{.*}} extract
+  %F = extractelement <8 x float> undef, i32 %arg
+
+  ;CHECK: cost of 0 {{.*}} insert
+  %G = insertelement <4 x float> poison, float %fl, i32 0
+  ;CHECK: cost of 1 {{.*}} insert
+  %H = insertelement <4 x float> poison, float %fl, i32 1
+  ;CHECK: cost of 1 {{.*}} insert
+  %I = insertelement <4 x i32> poison, i32 %arg, i32 0
+
+  ;CHECK: cost of 0 {{.*}} insert
+  %J = insertelement <4 x double> poison, double undef, i32 0
+
+  ;CHECK: cost of 0 {{.*}} insert
+  %K = insertelement <8 x double> poison, double undef, i32 4
+  ;CHECK: cost of 0 {{.*}} insert
+  %L = insertelement <16 x double> poison, double undef, i32 8
+  ;CHECK: cost of 1 {{.*}} insert
+  %M = insertelement <16 x double> poison, double undef, i32 9
+  ret i32 0
+}
+
diff --git a/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll
new file mode 100644
index 0000000000000..ef411b5235fec
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/loop_v2-inseltpoison.ll
@@ -0,0 +1,39 @@
+; RUN: opt < %s  -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.9.0"
+
+define i32 @foo(i32* nocapture %A) nounwind uwtable readonly ssp {
+vector.ph:
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %vec.phi = phi <2 x i32> [ zeroinitializer, %vector.ph ], [ %12, %vector.body ]
+  %0 = getelementptr inbounds i32, i32* %A, i64 %index
+  %1 = bitcast i32* %0 to <2 x i32>*
+  %2 = load <2 x i32>, <2 x i32>* %1, align 4
+  %3 = sext <2 x i32> %2 to <2 x i64>
+  ;CHECK: cost of 1 {{.*}} extract
+  %4 = extractelement <2 x i64> %3, i32 0
+  %5 = getelementptr inbounds i32, i32* %A, i64 %4
+  ;CHECK: cost of 1 {{.*}} extract
+  %6 = extractelement <2 x i64> %3, i32 1
+  %7 = getelementptr inbounds i32, i32* %A, i64 %6
+  %8 = load i32, i32* %5, align 4
+  ;CHECK: cost of 1 {{.*}} insert
+  %9 = insertelement <2 x i32> poison, i32 %8, i32 0
+  %10 = load i32, i32* %7, align 4
+  ;CHECK: cost of 1 {{.*}} insert
+  %11 = insertelement <2 x i32> %9, i32 %10, i32 1
+  %12 = add nsw <2 x i32> %11, %vec.phi
+  %index.next = add i64 %index, 2
+  %13 = icmp eq i64 %index.next, 192
+  br i1 %13, label %for.end, label %vector.body
+
+for.end:                                          ; preds = %vector.body
+  %14 = extractelement <2 x i32> %12, i32 0
+  %15 = extractelement <2 x i32> %12, i32 1
+  %16 = add i32 %14, %15
+  ret i32 %16
+}
diff --git a/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
new file mode 100644
index 0000000000000..0f6f6e2177da0
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/masked-intrinsic-cost-inseltpoison.ll
@@ -0,0 +1,1911 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt < %s -S -mtriple=x86_64-apple-darwin -mattr=+sse2 -cost-model -analyze | FileCheck %s --check-prefixes=SSE2
+; RUN: opt < %s -S -mtriple=x86_64-apple-darwin -mattr=+sse4.2 -cost-model -analyze | FileCheck %s --check-prefixes=SSE42
+; RUN: opt < %s -S -mtriple=x86_64-apple-darwin -mattr=+avx -cost-model -analyze | FileCheck %s --check-prefixes=AVX,AVX1
+; RUN: opt < %s -S -mtriple=x86_64-apple-darwin -mattr=+avx2 -cost-model -analyze | FileCheck %s --check-prefixes=AVX,AVX2
+;
+; RUN: opt < %s -S -mtriple=x86_64-apple-darwin -mcpu=skylake -cost-model -analyze | FileCheck %s --check-prefixes=AVX,SKL
+; RUN: opt < %s -S -mtriple=x86_64-apple-darwin -mcpu=knl -cost-model -analyze | FileCheck %s --check-prefixes=AVX512,KNL
+; RUN: opt < %s -S -mtriple=x86_64-apple-darwin -mcpu=skx -cost-model -analyze | FileCheck %s --check-prefixes=AVX512,SKX
+
+define i32 @masked_load() {
+; SSE2-LABEL: 'masked_load'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 35 for instruction: %V8F64 = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: %V4F64 = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V2F64 = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1F64 = call <1 x double> @llvm.masked.load.v1f64.p0v1f64(<1 x double>* undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 75 for instruction: %V16F32 = call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 37 for instruction: %V8F32 = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %V4F32 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V2F32 = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 43 for instruction: %V8I64 = call <8 x i64> @llvm.masked.load.v8i64.p0v8i64(<8 x i64>* undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 21 for instruction: %V4I64 = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V2I64 = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = call <1 x i64> @llvm.masked.load.v1i64.p0v1i64(<1 x i64>* undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 91 for instruction: %V16I32 = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 45 for instruction: %V8I32 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %V4I32 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V2I32 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 158 for instruction: %V32I16 = call <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>* undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 79 for instruction: %V16I16 = call <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>* undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 39 for instruction: %V8I16 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 19 for instruction: %V4I16 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 376 for instruction: %V64I8 = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 188 for instruction: %V32I8 = call <32 x i8> @llvm.masked.load.v32i8.p0v32i8(<32 x i8>* undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 94 for instruction: %V16I8 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 46 for instruction: %V8I8 = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SSE42-LABEL: 'masked_load'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %V8F64 = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %V4F64 = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V2F64 = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1F64 = call <1 x double> @llvm.masked.load.v1f64.p0v1f64(<1 x double>* undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %V16F32 = call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %V8F32 = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: %V4F32 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V2F32 = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V8I64 = call <8 x i64> @llvm.masked.load.v8i64.p0v8i64(<8 x i64>* undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V4I64 = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V2I64 = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = call <1 x i64> @llvm.masked.load.v1i64.p0v1i64(<1 x i64>* undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V16I32 = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V8I32 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V4I32 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V2I32 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: %V32I16 = call <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>* undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V16I16 = call <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>* undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V8I16 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V4I16 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 256 for instruction: %V64I8 = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: %V32I8 = call <32 x i8> @llvm.masked.load.v32i8.p0v32i8(<32 x i8>* undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V16I8 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V8I8 = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; AVX-LABEL: 'masked_load'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V2F64 = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1F64 = call <1 x double> @llvm.masked.load.v1f64.p0v1f64(<1 x double>* undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V4F32 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V2F32 = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V8I64 = call <8 x i64> @llvm.masked.load.v8i64.p0v8i64(<8 x i64>* undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = call <1 x i64> @llvm.masked.load.v1i64.p0v1i64(<1 x i64>* undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V16I32 = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V2I32 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 148 for instruction: %V32I16 = call <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>* undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 66 for instruction: %V16I16 = call <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>* undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V8I16 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V4I16 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 292 for instruction: %V64I8 = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 146 for instruction: %V32I8 = call <32 x i8> @llvm.masked.load.v32i8.p0v32i8(<32 x i8>* undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V16I8 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V8I8 = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; KNL-LABEL: 'masked_load'
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1F64 = call <1 x double> @llvm.masked.load.v1f64.p0v1f64(<1 x double>* undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %V2F32 = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.load.v8i64.p0v8i64(<8 x i64>* undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = call <1 x i64> @llvm.masked.load.v1i64.p0v1i64(<1 x i64>* undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %V2I32 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 148 for instruction: %V32I16 = call <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>* undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 66 for instruction: %V16I16 = call <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>* undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V8I16 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V4I16 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 308 for instruction: %V64I8 = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 146 for instruction: %V32I8 = call <32 x i8> @llvm.masked.load.v32i8.p0v32i8(<32 x i8>* undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V16I8 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V8I8 = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SKX-LABEL: 'masked_load'
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8F64 = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V4F64 = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V2F64 = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1F64 = call <1 x double> @llvm.masked.load.v1f64.p0v1f64(<1 x double>* undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V16F32 = call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8F32 = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V4F32 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %V2F32 = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8I64 = call <8 x i64> @llvm.masked.load.v8i64.p0v8i64(<8 x i64>* undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V4I64 = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V2I64 = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = call <1 x i64> @llvm.masked.load.v1i64.p0v1i64(<1 x i64>* undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V16I32 = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8I32 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V4I32 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %V2I32 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V32I16 = call <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>* undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V16I16 = call <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>* undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V8I16 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 9 for instruction: %V4I16 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V64I8 = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V32I8 = call <32 x i8> @llvm.masked.load.v32i8.p0v32i8(<32 x i8>* undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V16I8 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: %V8I8 = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+  %V8F64 = call <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>* undef, i32 1, <8 x i1> undef, <8 x double> undef)
+  %V4F64 = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* undef, i32 1, <4 x i1> undef, <4 x double> undef)
+  %V2F64 = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* undef, i32 1, <2 x i1> undef, <2 x double> undef)
+  %V1F64 = call <1 x double> @llvm.masked.load.v1f64.p0v1f64(<1 x double>* undef, i32 1, <1 x i1> undef, <1 x double> undef)
+
+  %V16F32 = call <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>* undef, i32 1, <16 x i1> undef, <16 x float> undef)
+  %V8F32 = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* undef, i32 1, <8 x i1> undef, <8 x float> undef)
+  %V4F32 = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* undef, i32 1, <4 x i1> undef, <4 x float> undef)
+  %V2F32 = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* undef, i32 1, <2 x i1> undef, <2 x float> undef)
+
+  %V8I64 = call <8 x i64> @llvm.masked.load.v8i64.p0v8i64(<8 x i64>* undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+  %V4I64 = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+  %V2I64 = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+  %V1I64 = call <1 x i64> @llvm.masked.load.v1i64.p0v1i64(<1 x i64>* undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+
+  %V16I32 = call <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>* undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+  %V8I32 = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+  %V4I32 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+  %V2I32 = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+
+  %V32I16 = call <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>* undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+  %V16I16 = call <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>* undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+  %V8I16 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+  %V4I16 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+
+  %V64I8 = call <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>* undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+  %V32I8 = call <32 x i8> @llvm.masked.load.v32i8.p0v32i8(<32 x i8>* undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+  %V16I8 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+  %V8I8 = call <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>* undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+
+  ret i32 0
+}
+
+define i32 @masked_store() {
+; SSE2-LABEL: 'masked_store'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 35 for instruction: call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> undef, <8 x double>* undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> undef, <4 x double>* undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> undef, <2 x double>* undef, i32 1, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> undef, <1 x double>* undef, i32 1, <1 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 75 for instruction: call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> undef, <16 x float>* undef, i32 1, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 37 for instruction: call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> undef, <8 x float>* undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> undef, <4 x float>* undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> undef, <2 x float>* undef, i32 1, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.store.v8i64.p0v8i64(<8 x i64> undef, <8 x i64>* undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> undef, <4 x i64>* undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> undef, <2 x i64>* undef, i32 1, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1i64.p0v1i64(<1 x i64> undef, <1 x i64>* undef, i32 1, <1 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 91 for instruction: call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32> undef, <16 x i32>* undef, i32 1, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 45 for instruction: call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> undef, <8 x i32>* undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> undef, <4 x i32>* undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> undef, <2 x i32>* undef, i32 1, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 158 for instruction: call void @llvm.masked.store.v32i16.p0v32i16(<32 x i16> undef, <32 x i16>* undef, i32 1, <32 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 79 for instruction: call void @llvm.masked.store.v16i16.p0v16i16(<16 x i16> undef, <16 x i16>* undef, i32 1, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 39 for instruction: call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> undef, <8 x i16>* undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.store.v4i16.p0v4i16(<4 x i16> undef, <4 x i16>* undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 376 for instruction: call void @llvm.masked.store.v64i8.p0v64i8(<64 x i8> undef, <64 x i8>* undef, i32 1, <64 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 188 for instruction: call void @llvm.masked.store.v32i8.p0v32i8(<32 x i8> undef, <32 x i8>* undef, i32 1, <32 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 94 for instruction: call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> undef, <16 x i8>* undef, i32 1, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 46 for instruction: call void @llvm.masked.store.v8i8.p0v8i8(<8 x i8> undef, <8 x i8>* undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SSE42-LABEL: 'masked_store'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> undef, <8 x double>* undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> undef, <4 x double>* undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> undef, <2 x double>* undef, i32 1, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> undef, <1 x double>* undef, i32 1, <1 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> undef, <16 x float>* undef, i32 1, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> undef, <8 x float>* undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> undef, <4 x float>* undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> undef, <2 x float>* undef, i32 1, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.store.v8i64.p0v8i64(<8 x i64> undef, <8 x i64>* undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> undef, <4 x i64>* undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> undef, <2 x i64>* undef, i32 1, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1i64.p0v1i64(<1 x i64> undef, <1 x i64>* undef, i32 1, <1 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32> undef, <16 x i32>* undef, i32 1, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> undef, <8 x i32>* undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> undef, <4 x i32>* undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> undef, <2 x i32>* undef, i32 1, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: call void @llvm.masked.store.v32i16.p0v32i16(<32 x i16> undef, <32 x i16>* undef, i32 1, <32 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.store.v16i16.p0v16i16(<16 x i16> undef, <16 x i16>* undef, i32 1, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> undef, <8 x i16>* undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v4i16.p0v4i16(<4 x i16> undef, <4 x i16>* undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 256 for instruction: call void @llvm.masked.store.v64i8.p0v64i8(<64 x i8> undef, <64 x i8>* undef, i32 1, <64 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: call void @llvm.masked.store.v32i8.p0v32i8(<32 x i8> undef, <32 x i8>* undef, i32 1, <32 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> undef, <16 x i8>* undef, i32 1, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.store.v8i8.p0v8i8(<8 x i8> undef, <8 x i8>* undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; AVX-LABEL: 'masked_store'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> undef, <8 x double>* undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> undef, <4 x double>* undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> undef, <2 x double>* undef, i32 1, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> undef, <1 x double>* undef, i32 1, <1 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> undef, <16 x float>* undef, i32 1, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> undef, <8 x float>* undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> undef, <4 x float>* undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> undef, <2 x float>* undef, i32 1, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v8i64.p0v8i64(<8 x i64> undef, <8 x i64>* undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> undef, <4 x i64>* undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> undef, <2 x i64>* undef, i32 1, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1i64.p0v1i64(<1 x i64> undef, <1 x i64>* undef, i32 1, <1 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32> undef, <16 x i32>* undef, i32 1, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> undef, <8 x i32>* undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> undef, <4 x i32>* undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> undef, <2 x i32>* undef, i32 1, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.store.v32i16.p0v32i16(<32 x i16> undef, <32 x i16>* undef, i32 1, <32 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 72 for instruction: call void @llvm.masked.store.v16i16.p0v16i16(<16 x i16> undef, <16 x i16>* undef, i32 1, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> undef, <8 x i16>* undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v4i16.p0v4i16(<4 x i16> undef, <4 x i16>* undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 320 for instruction: call void @llvm.masked.store.v64i8.p0v64i8(<64 x i8> undef, <64 x i8>* undef, i32 1, <64 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.store.v32i8.p0v32i8(<32 x i8> undef, <32 x i8>* undef, i32 1, <32 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> undef, <16 x i8>* undef, i32 1, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.store.v8i8.p0v8i8(<8 x i8> undef, <8 x i8>* undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; KNL-LABEL: 'masked_store'
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> undef, <8 x double>* undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> undef, <4 x double>* undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> undef, <2 x double>* undef, i32 1, <2 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> undef, <1 x double>* undef, i32 1, <1 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> undef, <16 x float>* undef, i32 1, <16 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> undef, <8 x float>* undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> undef, <4 x float>* undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> undef, <2 x float>* undef, i32 1, <2 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v8i64.p0v8i64(<8 x i64> undef, <8 x i64>* undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> undef, <4 x i64>* undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> undef, <2 x i64>* undef, i32 1, <2 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1i64.p0v1i64(<1 x i64> undef, <1 x i64>* undef, i32 1, <1 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32> undef, <16 x i32>* undef, i32 1, <16 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> undef, <8 x i32>* undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> undef, <4 x i32>* undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> undef, <2 x i32>* undef, i32 1, <2 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 168 for instruction: call void @llvm.masked.store.v32i16.p0v32i16(<32 x i16> undef, <32 x i16>* undef, i32 1, <32 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 72 for instruction: call void @llvm.masked.store.v16i16.p0v16i16(<16 x i16> undef, <16 x i16>* undef, i32 1, <16 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> undef, <8 x i16>* undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v4i16.p0v4i16(<4 x i16> undef, <4 x i16>* undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 352 for instruction: call void @llvm.masked.store.v64i8.p0v64i8(<64 x i8> undef, <64 x i8>* undef, i32 1, <64 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.store.v32i8.p0v32i8(<32 x i8> undef, <32 x i8>* undef, i32 1, <32 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> undef, <16 x i8>* undef, i32 1, <16 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.store.v8i8.p0v8i8(<8 x i8> undef, <8 x i8>* undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SKX-LABEL: 'masked_store'
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> undef, <8 x double>* undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> undef, <4 x double>* undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> undef, <2 x double>* undef, i32 1, <2 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> undef, <1 x double>* undef, i32 1, <1 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> undef, <16 x float>* undef, i32 1, <16 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> undef, <8 x float>* undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> undef, <4 x float>* undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> undef, <2 x float>* undef, i32 1, <2 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v8i64.p0v8i64(<8 x i64> undef, <8 x i64>* undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> undef, <4 x i64>* undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> undef, <2 x i64>* undef, i32 1, <2 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: call void @llvm.masked.store.v1i64.p0v1i64(<1 x i64> undef, <1 x i64>* undef, i32 1, <1 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32> undef, <16 x i32>* undef, i32 1, <16 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> undef, <8 x i32>* undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> undef, <4 x i32>* undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> undef, <2 x i32>* undef, i32 1, <2 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v32i16.p0v32i16(<32 x i16> undef, <32 x i16>* undef, i32 1, <32 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v16i16.p0v16i16(<16 x i16> undef, <16 x i16>* undef, i32 1, <16 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> undef, <8 x i16>* undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.store.v4i16.p0v4i16(<4 x i16> undef, <4 x i16>* undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v64i8.p0v64i8(<64 x i8> undef, <64 x i8>* undef, i32 1, <64 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v32i8.p0v32i8(<32 x i8> undef, <32 x i8>* undef, i32 1, <32 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> undef, <16 x i8>* undef, i32 1, <16 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.store.v8i8.p0v8i8(<8 x i8> undef, <8 x i8>* undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+  call void @llvm.masked.store.v8f64.p0v8f64(<8 x double> undef, <8 x double>* undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.store.v4f64.p0v4f64(<4 x double> undef, <4 x double>* undef, i32 1, <4 x i1> undef)
+  call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> undef, <2 x double>* undef, i32 1, <2 x i1> undef)
+  call void @llvm.masked.store.v1f64.p0v1f64(<1 x double> undef, <1 x double>* undef, i32 1, <1 x i1> undef)
+
+  call void @llvm.masked.store.v16f32.p0v16f32(<16 x float> undef, <16 x float>* undef, i32 1, <16 x i1> undef)
+  call void @llvm.masked.store.v8f32.p0v8f32(<8 x float> undef, <8 x float>* undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> undef, <4 x float>* undef, i32 1, <4 x i1> undef)
+  call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> undef, <2 x float>* undef, i32 1, <2 x i1> undef)
+
+  call void @llvm.masked.store.v8i64.p0v8i64(<8 x i64> undef, <8 x i64>* undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> undef, <4 x i64>* undef, i32 1, <4 x i1> undef)
+  call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> undef, <2 x i64>* undef, i32 1, <2 x i1> undef)
+  call void @llvm.masked.store.v1i64.p0v1i64(<1 x i64> undef, <1 x i64>* undef, i32 1, <1 x i1> undef)
+
+  call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32> undef, <16 x i32>* undef, i32 1, <16 x i1> undef)
+  call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> undef, <8 x i32>* undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> undef, <4 x i32>* undef, i32 1, <4 x i1> undef)
+  call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> undef, <2 x i32>* undef, i32 1, <2 x i1> undef)
+
+  call void @llvm.masked.store.v32i16.p0v32i16(<32 x i16> undef, <32 x i16>* undef, i32 1, <32 x i1> undef)
+  call void @llvm.masked.store.v16i16.p0v16i16(<16 x i16> undef, <16 x i16>* undef, i32 1, <16 x i1> undef)
+  call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> undef, <8 x i16>* undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.store.v4i16.p0v4i16(<4 x i16> undef, <4 x i16>* undef, i32 1, <4 x i1> undef)
+
+  call void @llvm.masked.store.v64i8.p0v64i8(<64 x i8> undef, <64 x i8>* undef, i32 1, <64 x i1> undef)
+  call void @llvm.masked.store.v32i8.p0v32i8(<32 x i8> undef, <32 x i8>* undef, i32 1, <32 x i1> undef)
+  call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> undef, <16 x i8>* undef, i32 1, <16 x i1> undef)
+  call void @llvm.masked.store.v8i8.p0v8i8(<8 x i8> undef, <8 x i8>* undef, i32 1, <8 x i1> undef)
+
+  ret i32 0
+}
+
+define i32 @masked_gather() {
+; SSE2-LABEL: 'masked_gather'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*> undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 40 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*> undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0i16(<32 x i16*> undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*> undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 960 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0i8(<64 x i8*> undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 480 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 240 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 72 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SSE42-LABEL: 'masked_gather'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*> undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*> undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0i16(<32 x i16*> undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*> undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0i8(<64 x i8*> undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; AVX1-LABEL: 'masked_gather'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*> undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*> undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0i16(<32 x i16*> undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*> undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 192 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0i8(<64 x i8*> undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; AVX2-LABEL: 'masked_gather'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*> undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*> undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0i16(<32 x i16*> undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*> undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 192 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0i8(<64 x i8*> undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SKL-LABEL: 'masked_gather'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*> undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*> undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0i16(<32 x i16*> undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*> undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 192 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0i8(<64 x i8*> undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; KNL-LABEL: 'masked_gather'
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*> undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*> undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 112 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0i16(<32 x i16*> undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*> undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 224 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0i8(<64 x i8*> undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SKX-LABEL: 'masked_gather'
+; SKX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> undef, i32 1, <8 x i1> undef, <8 x double> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> undef, i32 1, <4 x i1> undef, <4 x double> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> undef, i32 1, <2 x i1> undef, <2 x double> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*> undef, i32 1, <1 x i1> undef, <1 x double> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> undef, i32 1, <16 x i1> undef, <16 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> undef, i32 1, <8 x i1> undef, <8 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> undef, i32 1, <4 x i1> undef, <4 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> undef, i32 1, <2 x i1> undef, <2 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*> undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 112 for instruction: %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0i16(<32 x i16*> undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*> undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 224 for instruction: %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0i8(<64 x i8*> undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+  %V8F64 = call <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*> undef, i32 1, <8 x i1> undef, <8 x double> undef)
+  %V4F64 = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> undef, i32 1, <4 x i1> undef, <4 x double> undef)
+  %V2F64 = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> undef, i32 1, <2 x i1> undef, <2 x double> undef)
+  %V1F64 = call <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*> undef, i32 1, <1 x i1> undef, <1 x double> undef)
+
+  %V16F32 = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> undef, i32 1, <16 x i1> undef, <16 x float> undef)
+  %V8F32 = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> undef, i32 1, <8 x i1> undef, <8 x float> undef)
+  %V4F32 = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> undef, i32 1, <4 x i1> undef, <4 x float> undef)
+  %V2F32 = call <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*> undef, i32 1, <2 x i1> undef, <2 x float> undef)
+
+  %V8I64 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> undef, i32 1, <8 x i1> undef, <8 x i64> undef)
+  %V4I64 = call <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*> undef, i32 1, <4 x i1> undef, <4 x i64> undef)
+  %V2I64 = call <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*> undef, i32 1, <2 x i1> undef, <2 x i64> undef)
+  %V1I64 = call <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*> undef, i32 1, <1 x i1> undef, <1 x i64> undef)
+
+  %V16I32 = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> undef, i32 1, <16 x i1> undef, <16 x i32> undef)
+  %V8I32 = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> undef, i32 1, <8 x i1> undef, <8 x i32> undef)
+  %V4I32 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> undef, i32 1, <4 x i1> undef, <4 x i32> undef)
+  %V2I32 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> undef, i32 1, <2 x i1> undef, <2 x i32> undef)
+
+  %V32I16 = call <32 x i16> @llvm.masked.gather.v32i16.v32p0i16(<32 x i16*> undef, i32 1, <32 x i1> undef, <32 x i16> undef)
+  %V16I16 = call <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*> undef, i32 1, <16 x i1> undef, <16 x i16> undef)
+  %V8I16 = call <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*> undef, i32 1, <8 x i1> undef, <8 x i16> undef)
+  %V4I16 = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> undef, i32 1, <4 x i1> undef, <4 x i16> undef)
+
+  %V64I8 = call <64 x i8> @llvm.masked.gather.v64i8.v64p0i8(<64 x i8*> undef, i32 1, <64 x i1> undef, <64 x i8> undef)
+  %V32I8 = call <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*> undef, i32 1, <32 x i1> undef, <32 x i8> undef)
+  %V16I8 = call <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*> undef, i32 1, <16 x i1> undef, <16 x i8> undef)
+  %V8I8 = call <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*> undef, i32 1, <8 x i1> undef, <8 x i8> undef)
+
+  ret i32 0
+}
+
+define i32 @masked_scatter() {
+; SSE2-LABEL: 'masked_scatter'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> undef, <8 x double*> undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double> undef, <4 x double*> undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> undef, <2 x double*> undef, i32 1, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1f64.v1p0f64(<1 x double> undef, <1 x double*> undef, i32 1, <1 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> undef, <16 x float*> undef, i32 1, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> undef, <8 x float*> undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float> undef, <4 x float*> undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> undef, <2 x float*> undef, i32 1, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> undef, <8 x i64*> undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64> undef, <4 x i64*> undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64> undef, <2 x i64*> undef, i32 1, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1i64.v1p0i64(<1 x i64> undef, <1 x i64*> undef, i32 1, <1 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> undef, <16 x i32*> undef, i32 1, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> undef, <8 x i32*> undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> undef, <4 x i32*> undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> undef, <2 x i32*> undef, i32 1, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.scatter.v32i16.v32p0i16(<32 x i16> undef, <32 x i16*> undef, i32 1, <32 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.v16i16.v16p0i16(<16 x i16> undef, <16 x i16*> undef, i32 1, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> undef, <8 x i16*> undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> undef, <4 x i16*> undef, i32 1, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 188 for instruction: call void @llvm.masked.scatter.v64i8.v64p0i8(<64 x i8> undef, <64 x i8*> undef, i32 1, <64 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 94 for instruction: call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> undef, <32 x i8*> undef, i32 1, <32 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8> undef, <16 x i8*> undef, i32 1, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> undef, <8 x i8*> undef, i32 1, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SSE42-LABEL: 'masked_scatter'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> undef, <8 x double*> undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double> undef, <4 x double*> undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> undef, <2 x double*> undef, i32 1, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1f64.v1p0f64(<1 x double> undef, <1 x double*> undef, i32 1, <1 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> undef, <16 x float*> undef, i32 1, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> undef, <8 x float*> undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float> undef, <4 x float*> undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> undef, <2 x float*> undef, i32 1, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> undef, <8 x i64*> undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64> undef, <4 x i64*> undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64> undef, <2 x i64*> undef, i32 1, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1i64.v1p0i64(<1 x i64> undef, <1 x i64*> undef, i32 1, <1 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> undef, <16 x i32*> undef, i32 1, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> undef, <8 x i32*> undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> undef, <4 x i32*> undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> undef, <2 x i32*> undef, i32 1, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.scatter.v32i16.v32p0i16(<32 x i16> undef, <32 x i16*> undef, i32 1, <32 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.v16i16.v16p0i16(<16 x i16> undef, <16 x i16*> undef, i32 1, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> undef, <8 x i16*> undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> undef, <4 x i16*> undef, i32 1, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: call void @llvm.masked.scatter.v64i8.v64p0i8(<64 x i8> undef, <64 x i8*> undef, i32 1, <64 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> undef, <32 x i8*> undef, i32 1, <32 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8> undef, <16 x i8*> undef, i32 1, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> undef, <8 x i8*> undef, i32 1, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; AVX-LABEL: 'masked_scatter'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> undef, <8 x double*> undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double> undef, <4 x double*> undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> undef, <2 x double*> undef, i32 1, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1f64.v1p0f64(<1 x double> undef, <1 x double*> undef, i32 1, <1 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> undef, <16 x float*> undef, i32 1, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> undef, <8 x float*> undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float> undef, <4 x float*> undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> undef, <2 x float*> undef, i32 1, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> undef, <8 x i64*> undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64> undef, <4 x i64*> undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64> undef, <2 x i64*> undef, i32 1, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1i64.v1p0i64(<1 x i64> undef, <1 x i64*> undef, i32 1, <1 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> undef, <16 x i32*> undef, i32 1, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> undef, <8 x i32*> undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> undef, <4 x i32*> undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> undef, <2 x i32*> undef, i32 1, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v32i16.v32p0i16(<32 x i16> undef, <32 x i16*> undef, i32 1, <32 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v16i16.v16p0i16(<16 x i16> undef, <16 x i16*> undef, i32 1, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> undef, <8 x i16*> undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> undef, <4 x i16*> undef, i32 1, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 160 for instruction: call void @llvm.masked.scatter.v64i8.v64p0i8(<64 x i8> undef, <64 x i8*> undef, i32 1, <64 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> undef, <32 x i8*> undef, i32 1, <32 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8> undef, <16 x i8*> undef, i32 1, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> undef, <8 x i8*> undef, i32 1, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; KNL-LABEL: 'masked_scatter'
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> undef, <8 x double*> undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double> undef, <4 x double*> undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> undef, <2 x double*> undef, i32 1, <2 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1f64.v1p0f64(<1 x double> undef, <1 x double*> undef, i32 1, <1 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> undef, <16 x float*> undef, i32 1, <16 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> undef, <8 x float*> undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float> undef, <4 x float*> undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> undef, <2 x float*> undef, i32 1, <2 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> undef, <8 x i64*> undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64> undef, <4 x i64*> undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64> undef, <2 x i64*> undef, i32 1, <2 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1i64.v1p0i64(<1 x i64> undef, <1 x i64*> undef, i32 1, <1 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> undef, <16 x i32*> undef, i32 1, <16 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> undef, <8 x i32*> undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> undef, <4 x i32*> undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> undef, <2 x i32*> undef, i32 1, <2 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 88 for instruction: call void @llvm.masked.scatter.v32i16.v32p0i16(<32 x i16> undef, <32 x i16*> undef, i32 1, <32 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v16i16.v16p0i16(<16 x i16> undef, <16 x i16*> undef, i32 1, <16 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> undef, <8 x i16*> undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> undef, <4 x i16*> undef, i32 1, <4 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 176 for instruction: call void @llvm.masked.scatter.v64i8.v64p0i8(<64 x i8> undef, <64 x i8*> undef, i32 1, <64 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> undef, <32 x i8*> undef, i32 1, <32 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8> undef, <16 x i8*> undef, i32 1, <16 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> undef, <8 x i8*> undef, i32 1, <8 x i1> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SKX-LABEL: 'masked_scatter'
+; SKX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> undef, <8 x double*> undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double> undef, <4 x double*> undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> undef, <2 x double*> undef, i32 1, <2 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1f64.v1p0f64(<1 x double> undef, <1 x double*> undef, i32 1, <1 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> undef, <16 x float*> undef, i32 1, <16 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> undef, <8 x float*> undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float> undef, <4 x float*> undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: call void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> undef, <2 x float*> undef, i32 1, <2 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> undef, <8 x i64*> undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64> undef, <4 x i64*> undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64> undef, <2 x i64*> undef, i32 1, <2 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.scatter.v1i64.v1p0i64(<1 x i64> undef, <1 x i64*> undef, i32 1, <1 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> undef, <16 x i32*> undef, i32 1, <16 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> undef, <8 x i32*> undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> undef, <4 x i32*> undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> undef, <2 x i32*> undef, i32 1, <2 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 88 for instruction: call void @llvm.masked.scatter.v32i16.v32p0i16(<32 x i16> undef, <32 x i16*> undef, i32 1, <32 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 40 for instruction: call void @llvm.masked.scatter.v16i16.v16p0i16(<16 x i16> undef, <16 x i16*> undef, i32 1, <16 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> undef, <8 x i16*> undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> undef, <4 x i16*> undef, i32 1, <4 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 176 for instruction: call void @llvm.masked.scatter.v64i8.v64p0i8(<64 x i8> undef, <64 x i8*> undef, i32 1, <64 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 80 for instruction: call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> undef, <32 x i8*> undef, i32 1, <32 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8> undef, <16 x i8*> undef, i32 1, <16 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> undef, <8 x i8*> undef, i32 1, <8 x i1> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+  call void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double> undef, <8 x double*> undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double> undef, <4 x double*> undef, i32 1, <4 x i1> undef)
+  call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> undef, <2 x double*> undef, i32 1, <2 x i1> undef)
+  call void @llvm.masked.scatter.v1f64.v1p0f64(<1 x double> undef, <1 x double*> undef, i32 1, <1 x i1> undef)
+
+  call void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float> undef, <16 x float*> undef, i32 1, <16 x i1> undef)
+  call void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float> undef, <8 x float*> undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float> undef, <4 x float*> undef, i32 1, <4 x i1> undef)
+  call void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float> undef, <2 x float*> undef, i32 1, <2 x i1> undef)
+
+  call void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64> undef, <8 x i64*> undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64> undef, <4 x i64*> undef, i32 1, <4 x i1> undef)
+  call void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64> undef, <2 x i64*> undef, i32 1, <2 x i1> undef)
+  call void @llvm.masked.scatter.v1i64.v1p0i64(<1 x i64> undef, <1 x i64*> undef, i32 1, <1 x i1> undef)
+
+  call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> undef, <16 x i32*> undef, i32 1, <16 x i1> undef)
+  call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> undef, <8 x i32*> undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> undef, <4 x i32*> undef, i32 1, <4 x i1> undef)
+  call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> undef, <2 x i32*> undef, i32 1, <2 x i1> undef)
+
+  call void @llvm.masked.scatter.v32i16.v32p0i16(<32 x i16> undef, <32 x i16*> undef, i32 1, <32 x i1> undef)
+  call void @llvm.masked.scatter.v16i16.v16p0i16(<16 x i16> undef, <16 x i16*> undef, i32 1, <16 x i1> undef)
+  call void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16> undef, <8 x i16*> undef, i32 1, <8 x i1> undef)
+  call void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16> undef, <4 x i16*> undef, i32 1, <4 x i1> undef)
+
+  call void @llvm.masked.scatter.v64i8.v64p0i8(<64 x i8> undef, <64 x i8*> undef, i32 1, <64 x i1> undef)
+  call void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8> undef, <32 x i8*> undef, i32 1, <32 x i1> undef)
+  call void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8> undef, <16 x i8*> undef, i32 1, <16 x i1> undef)
+  call void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8> undef, <8 x i8*> undef, i32 1, <8 x i1> undef)
+
+  ret i32 0
+}
+
+define i32 @masked_expandload() {
+; SSE2-LABEL: 'masked_expandload'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.masked.expandload.v8f64(double* undef, <8 x i1> undef, <8 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.expandload.v4f64(double* undef, <4 x i1> undef, <4 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.expandload.v2f64(double* undef, <2 x i1> undef, <2 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.expandload.v1f64(double* undef, <1 x i1> undef, <1 x double> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.masked.expandload.v16f32(float* undef, <16 x i1> undef, <16 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.masked.expandload.v8f32(float* undef, <8 x i1> undef, <8 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.masked.expandload.v4f32(float* undef, <4 x i1> undef, <4 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.masked.expandload.v2f32(float* undef, <2 x i1> undef, <2 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V8I64 = call <8 x i64> @llvm.masked.expandload.v8i64(i64* undef, <8 x i1> undef, <8 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V4I64 = call <4 x i64> @llvm.masked.expandload.v4i64(i64* undef, <4 x i1> undef, <4 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %V2I64 = call <2 x i64> @llvm.masked.expandload.v2i64(i64* undef, <2 x i1> undef, <2 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.expandload.v1i64(i64* undef, <1 x i1> undef, <1 x i64> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %V16I32 = call <16 x i32> @llvm.masked.expandload.v16i32(i32* undef, <16 x i1> undef, <16 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %V8I32 = call <8 x i32> @llvm.masked.expandload.v8i32(i32* undef, <8 x i1> undef, <8 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %V4I32 = call <4 x i32> @llvm.masked.expandload.v4i32(i32* undef, <4 x i1> undef, <4 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %V2I32 = call <2 x i32> @llvm.masked.expandload.v2i32(i32* undef, <2 x i1> undef, <2 x i32> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V32I16 = call <32 x i16> @llvm.masked.expandload.v32i16(i16* undef, <32 x i1> undef, <32 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I16 = call <16 x i16> @llvm.masked.expandload.v16i16(i16* undef, <16 x i1> undef, <16 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.expandload.v8i16(i16* undef, <8 x i1> undef, <8 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.expandload.v4i16(i16* undef, <4 x i1> undef, <4 x i16> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 188 for instruction: %V64I8 = call <64 x i8> @llvm.masked.expandload.v64i8(i8* undef, <64 x i1> undef, <64 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 94 for instruction: %V32I8 = call <32 x i8> @llvm.masked.expandload.v32i8(i8* undef, <32 x i1> undef, <32 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 47 for instruction: %V16I8 = call <16 x i8> @llvm.masked.expandload.v16i8(i8* undef, <16 x i1> undef, <16 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: %V8I8 = call <8 x i8> @llvm.masked.expandload.v8i8(i8* undef, <8 x i1> undef, <8 x i8> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SSE42-LABEL: 'masked_expandload'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %V8F64 = call <8 x double> @llvm.masked.expandload.v8f64(double* undef, <8 x i1> undef, <8 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %V4F64 = call <4 x double> @llvm.masked.expandload.v4f64(double* undef, <4 x i1> undef, <4 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.expandload.v2f64(double* undef, <2 x i1> undef, <2 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.expandload.v1f64(double* undef, <1 x i1> undef, <1 x double> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %V16F32 = call <16 x float> @llvm.masked.expandload.v16f32(float* undef, <16 x i1> undef, <16 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %V8F32 = call <8 x float> @llvm.masked.expandload.v8f32(float* undef, <8 x i1> undef, <8 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.masked.expandload.v4f32(float* undef, <4 x i1> undef, <4 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.masked.expandload.v2f32(float* undef, <2 x i1> undef, <2 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I64 = call <8 x i64> @llvm.masked.expandload.v8i64(i64* undef, <8 x i1> undef, <8 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I64 = call <4 x i64> @llvm.masked.expandload.v4i64(i64* undef, <4 x i1> undef, <4 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.expandload.v2i64(i64* undef, <2 x i1> undef, <2 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.expandload.v1i64(i64* undef, <1 x i1> undef, <1 x i64> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I32 = call <16 x i32> @llvm.masked.expandload.v16i32(i32* undef, <16 x i1> undef, <16 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I32 = call <8 x i32> @llvm.masked.expandload.v8i32(i32* undef, <8 x i1> undef, <8 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.masked.expandload.v4i32(i32* undef, <4 x i1> undef, <4 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.expandload.v2i32(i32* undef, <2 x i1> undef, <2 x i32> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V32I16 = call <32 x i16> @llvm.masked.expandload.v32i16(i16* undef, <32 x i1> undef, <32 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I16 = call <16 x i16> @llvm.masked.expandload.v16i16(i16* undef, <16 x i1> undef, <16 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.expandload.v8i16(i16* undef, <8 x i1> undef, <8 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.expandload.v4i16(i16* undef, <4 x i1> undef, <4 x i16> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: %V64I8 = call <64 x i8> @llvm.masked.expandload.v64i8(i8* undef, <64 x i1> undef, <64 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %V32I8 = call <32 x i8> @llvm.masked.expandload.v32i8(i8* undef, <32 x i1> undef, <32 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I8 = call <16 x i8> @llvm.masked.expandload.v16i8(i8* undef, <16 x i1> undef, <16 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I8 = call <8 x i8> @llvm.masked.expandload.v8i8(i8* undef, <8 x i1> undef, <8 x i8> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; AVX-LABEL: 'masked_expandload'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %V8F64 = call <8 x double> @llvm.masked.expandload.v8f64(double* undef, <8 x i1> undef, <8 x double> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.masked.expandload.v4f64(double* undef, <4 x i1> undef, <4 x double> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.expandload.v2f64(double* undef, <2 x i1> undef, <2 x double> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.expandload.v1f64(double* undef, <1 x i1> undef, <1 x double> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.masked.expandload.v16f32(float* undef, <16 x i1> undef, <16 x float> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.masked.expandload.v8f32(float* undef, <8 x i1> undef, <8 x float> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.masked.expandload.v4f32(float* undef, <4 x i1> undef, <4 x float> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.masked.expandload.v2f32(float* undef, <2 x i1> undef, <2 x float> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V8I64 = call <8 x i64> @llvm.masked.expandload.v8i64(i64* undef, <8 x i1> undef, <8 x i64> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V4I64 = call <4 x i64> @llvm.masked.expandload.v4i64(i64* undef, <4 x i1> undef, <4 x i64> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.expandload.v2i64(i64* undef, <2 x i1> undef, <2 x i64> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.expandload.v1i64(i64* undef, <1 x i1> undef, <1 x i64> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 36 for instruction: %V16I32 = call <16 x i32> @llvm.masked.expandload.v16i32(i32* undef, <16 x i1> undef, <16 x i32> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %V8I32 = call <8 x i32> @llvm.masked.expandload.v8i32(i32* undef, <8 x i1> undef, <8 x i32> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.masked.expandload.v4i32(i32* undef, <4 x i1> undef, <4 x i32> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.expandload.v2i32(i32* undef, <2 x i1> undef, <2 x i32> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 68 for instruction: %V32I16 = call <32 x i16> @llvm.masked.expandload.v32i16(i16* undef, <32 x i1> undef, <32 x i16> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 34 for instruction: %V16I16 = call <16 x i16> @llvm.masked.expandload.v16i16(i16* undef, <16 x i1> undef, <16 x i16> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.expandload.v8i16(i16* undef, <8 x i1> undef, <8 x i16> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.expandload.v4i16(i16* undef, <4 x i1> undef, <4 x i16> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 132 for instruction: %V64I8 = call <64 x i8> @llvm.masked.expandload.v64i8(i8* undef, <64 x i1> undef, <64 x i8> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 66 for instruction: %V32I8 = call <32 x i8> @llvm.masked.expandload.v32i8(i8* undef, <32 x i1> undef, <32 x i8> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I8 = call <16 x i8> @llvm.masked.expandload.v16i8(i8* undef, <16 x i1> undef, <16 x i8> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I8 = call <8 x i8> @llvm.masked.expandload.v8i8(i8* undef, <8 x i1> undef, <8 x i8> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; AVX512-LABEL: 'masked_expandload'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: %V8F64 = call <8 x double> @llvm.masked.expandload.v8f64(double* undef, <8 x i1> undef, <8 x double> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F64 = call <4 x double> @llvm.masked.expandload.v4f64(double* undef, <4 x i1> undef, <4 x double> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F64 = call <2 x double> @llvm.masked.expandload.v2f64(double* undef, <2 x i1> undef, <2 x double> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1F64 = call <1 x double> @llvm.masked.expandload.v1f64(double* undef, <1 x i1> undef, <1 x double> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16F32 = call <16 x float> @llvm.masked.expandload.v16f32(float* undef, <16 x i1> undef, <16 x float> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8F32 = call <8 x float> @llvm.masked.expandload.v8f32(float* undef, <8 x i1> undef, <8 x float> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %V4F32 = call <4 x float> @llvm.masked.expandload.v4f32(float* undef, <4 x i1> undef, <4 x float> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %V2F32 = call <2 x float> @llvm.masked.expandload.v2f32(float* undef, <2 x i1> undef, <2 x float> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %V8I64 = call <8 x i64> @llvm.masked.expandload.v8i64(i64* undef, <8 x i1> undef, <8 x i64> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %V4I64 = call <4 x i64> @llvm.masked.expandload.v4i64(i64* undef, <4 x i1> undef, <4 x i64> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.masked.expandload.v2i64(i64* undef, <2 x i1> undef, <2 x i64> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %V1I64 = call <1 x i64> @llvm.masked.expandload.v1i64(i64* undef, <1 x i1> undef, <1 x i64> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 36 for instruction: %V16I32 = call <16 x i32> @llvm.masked.expandload.v16i32(i32* undef, <16 x i1> undef, <16 x i32> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %V8I32 = call <8 x i32> @llvm.masked.expandload.v8i32(i32* undef, <8 x i1> undef, <8 x i32> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I32 = call <4 x i32> @llvm.masked.expandload.v4i32(i32* undef, <4 x i1> undef, <4 x i32> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %V2I32 = call <2 x i32> @llvm.masked.expandload.v2i32(i32* undef, <2 x i1> undef, <2 x i32> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 68 for instruction: %V32I16 = call <32 x i16> @llvm.masked.expandload.v32i16(i16* undef, <32 x i1> undef, <32 x i16> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 34 for instruction: %V16I16 = call <16 x i16> @llvm.masked.expandload.v16i16(i16* undef, <16 x i1> undef, <16 x i16> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I16 = call <8 x i16> @llvm.masked.expandload.v8i16(i16* undef, <8 x i1> undef, <8 x i16> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %V4I16 = call <4 x i16> @llvm.masked.expandload.v4i16(i16* undef, <4 x i1> undef, <4 x i16> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 132 for instruction: %V64I8 = call <64 x i8> @llvm.masked.expandload.v64i8(i8* undef, <64 x i1> undef, <64 x i8> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 66 for instruction: %V32I8 = call <32 x i8> @llvm.masked.expandload.v32i8(i8* undef, <32 x i1> undef, <32 x i8> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %V16I8 = call <16 x i8> @llvm.masked.expandload.v16i8(i8* undef, <16 x i1> undef, <16 x i8> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %V8I8 = call <8 x i8> @llvm.masked.expandload.v8i8(i8* undef, <8 x i1> undef, <8 x i8> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+  %V8F64 = call <8 x double> @llvm.masked.expandload.v8f64(double* undef, <8 x i1> undef, <8 x double> undef)
+  %V4F64 = call <4 x double> @llvm.masked.expandload.v4f64(double* undef, <4 x i1> undef, <4 x double> undef)
+  %V2F64 = call <2 x double> @llvm.masked.expandload.v2f64(double* undef, <2 x i1> undef, <2 x double> undef)
+  %V1F64 = call <1 x double> @llvm.masked.expandload.v1f64(double* undef, <1 x i1> undef, <1 x double> undef)
+
+  %V16F32 = call <16 x float> @llvm.masked.expandload.v16f32(float* undef, <16 x i1> undef, <16 x float> undef)
+  %V8F32 = call <8 x float> @llvm.masked.expandload.v8f32(float* undef, <8 x i1> undef, <8 x float> undef)
+  %V4F32 = call <4 x float> @llvm.masked.expandload.v4f32(float* undef, <4 x i1> undef, <4 x float> undef)
+  %V2F32 = call <2 x float> @llvm.masked.expandload.v2f32(float* undef, <2 x i1> undef, <2 x float> undef)
+
+  %V8I64 = call <8 x i64> @llvm.masked.expandload.v8i64(i64* undef, <8 x i1> undef, <8 x i64> undef)
+  %V4I64 = call <4 x i64> @llvm.masked.expandload.v4i64(i64* undef, <4 x i1> undef, <4 x i64> undef)
+  %V2I64 = call <2 x i64> @llvm.masked.expandload.v2i64(i64* undef, <2 x i1> undef, <2 x i64> undef)
+  %V1I64 = call <1 x i64> @llvm.masked.expandload.v1i64(i64* undef, <1 x i1> undef, <1 x i64> undef)
+
+  %V16I32 = call <16 x i32> @llvm.masked.expandload.v16i32(i32* undef, <16 x i1> undef, <16 x i32> undef)
+  %V8I32 = call <8 x i32> @llvm.masked.expandload.v8i32(i32* undef, <8 x i1> undef, <8 x i32> undef)
+  %V4I32 = call <4 x i32> @llvm.masked.expandload.v4i32(i32* undef, <4 x i1> undef, <4 x i32> undef)
+  %V2I32 = call <2 x i32> @llvm.masked.expandload.v2i32(i32* undef, <2 x i1> undef, <2 x i32> undef)
+
+  %V32I16 = call <32 x i16> @llvm.masked.expandload.v32i16(i16* undef, <32 x i1> undef, <32 x i16> undef)
+  %V16I16 = call <16 x i16> @llvm.masked.expandload.v16i16(i16* undef, <16 x i1> undef, <16 x i16> undef)
+  %V8I16 = call <8 x i16> @llvm.masked.expandload.v8i16(i16* undef, <8 x i1> undef, <8 x i16> undef)
+  %V4I16 = call <4 x i16> @llvm.masked.expandload.v4i16(i16* undef, <4 x i1> undef, <4 x i16> undef)
+
+  %V64I8 = call <64 x i8> @llvm.masked.expandload.v64i8(i8* undef, <64 x i1> undef, <64 x i8> undef)
+  %V32I8 = call <32 x i8> @llvm.masked.expandload.v32i8(i8* undef, <32 x i1> undef, <32 x i8> undef)
+  %V16I8 = call <16 x i8> @llvm.masked.expandload.v16i8(i8* undef, <16 x i1> undef, <16 x i8> undef)
+  %V8I8 = call <8 x i8> @llvm.masked.expandload.v8i8(i8* undef, <8 x i1> undef, <8 x i8> undef)
+
+  ret i32 0
+}
+
+define i32 @masked_compressstore() {
+; SSE2-LABEL: 'masked_compressstore'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.compressstore.v8f64(<8 x double> undef, double* undef, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.compressstore.v4f64(<4 x double> undef, double* undef, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.compressstore.v2f64(<2 x double> undef, double* undef, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.compressstore.v1f64(<1 x double> undef, double* undef, <1 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 58 for instruction: call void @llvm.masked.compressstore.v16f32(<16 x float> undef, float* undef, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.compressstore.v8f32(<8 x float> undef, float* undef, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 13 for instruction: call void @llvm.masked.compressstore.v4f32(<4 x float> undef, float* undef, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.compressstore.v2f32(<2 x float> undef, float* undef, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 27 for instruction: call void @llvm.masked.compressstore.v8i64(<8 x i64> undef, i64* undef, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.compressstore.v4i64(<4 x i64> undef, i64* undef, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.compressstore.v2i64(<2 x i64> undef, i64* undef, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.compressstore.v1i64(<1 x i64> undef, i64* undef, <1 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 74 for instruction: call void @llvm.masked.compressstore.v16i32(<16 x i32> undef, i32* undef, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.compressstore.v8i32(<8 x i32> undef, i32* undef, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 17 for instruction: call void @llvm.masked.compressstore.v4i32(<4 x i32> undef, i32* undef, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.compressstore.v2i32(<2 x i32> undef, i32* undef, <2 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 125 for instruction: call void @llvm.masked.compressstore.v32i16(<32 x i16> undef, i16* undef, <32 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 62 for instruction: call void @llvm.masked.compressstore.v16i16(<16 x i16> undef, i16* undef, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8i16(<8 x i16> undef, i16* undef, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: call void @llvm.masked.compressstore.v4i16(<4 x i16> undef, i16* undef, <4 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 311 for instruction: call void @llvm.masked.compressstore.v64i8(<64 x i8> undef, i8* undef, <64 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 155 for instruction: call void @llvm.masked.compressstore.v32i8(<32 x i8> undef, i8* undef, <32 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 77 for instruction: call void @llvm.masked.compressstore.v16i8(<16 x i8> undef, i8* undef, <16 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: call void @llvm.masked.compressstore.v8i8(<8 x i8> undef, i8* undef, <8 x i1> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; SSE42-LABEL: 'masked_compressstore'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 19 for instruction: call void @llvm.masked.compressstore.v8f64(<8 x double> undef, double* undef, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 9 for instruction: call void @llvm.masked.compressstore.v4f64(<4 x double> undef, double* undef, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.compressstore.v2f64(<2 x double> undef, double* undef, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.compressstore.v1f64(<1 x double> undef, double* undef, <1 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 43 for instruction: call void @llvm.masked.compressstore.v16f32(<16 x float> undef, float* undef, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 21 for instruction: call void @llvm.masked.compressstore.v8f32(<8 x float> undef, float* undef, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.compressstore.v4f32(<4 x float> undef, float* undef, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.compressstore.v2f32(<2 x float> undef, float* undef, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8i64(<8 x i64> undef, i64* undef, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.compressstore.v4i64(<4 x i64> undef, i64* undef, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.compressstore.v2i64(<2 x i64> undef, i64* undef, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.compressstore.v1i64(<1 x i64> undef, i64* undef, <1 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.compressstore.v16i32(<16 x i32> undef, i32* undef, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8i32(<8 x i32> undef, i32* undef, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.compressstore.v4i32(<4 x i32> undef, i32* undef, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.compressstore.v2i32(<2 x i32> undef, i32* undef, <2 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 95 for instruction: call void @llvm.masked.compressstore.v32i16(<32 x i16> undef, i16* undef, <32 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.compressstore.v16i16(<16 x i16> undef, i16* undef, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8i16(<8 x i16> undef, i16* undef, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.compressstore.v4i16(<4 x i16> undef, i16* undef, <4 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 191 for instruction: call void @llvm.masked.compressstore.v64i8(<64 x i8> undef, i8* undef, <64 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 95 for instruction: call void @llvm.masked.compressstore.v32i8(<32 x i8> undef, i8* undef, <32 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.compressstore.v16i8(<16 x i8> undef, i8* undef, <16 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8i8(<8 x i8> undef, i8* undef, <8 x i1> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; AVX-LABEL: 'masked_compressstore'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8f64(<8 x double> undef, double* undef, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.compressstore.v4f64(<4 x double> undef, double* undef, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.compressstore.v2f64(<2 x double> undef, double* undef, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.compressstore.v1f64(<1 x double> undef, double* undef, <1 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 51 for instruction: call void @llvm.masked.compressstore.v16f32(<16 x float> undef, float* undef, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 25 for instruction: call void @llvm.masked.compressstore.v8f32(<8 x float> undef, float* undef, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.compressstore.v4f32(<4 x float> undef, float* undef, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.compressstore.v2f32(<2 x float> undef, float* undef, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 27 for instruction: call void @llvm.masked.compressstore.v8i64(<8 x i64> undef, i64* undef, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 13 for instruction: call void @llvm.masked.compressstore.v4i64(<4 x i64> undef, i64* undef, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.compressstore.v2i64(<2 x i64> undef, i64* undef, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.compressstore.v1i64(<1 x i64> undef, i64* undef, <1 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 55 for instruction: call void @llvm.masked.compressstore.v16i32(<16 x i32> undef, i32* undef, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 27 for instruction: call void @llvm.masked.compressstore.v8i32(<8 x i32> undef, i32* undef, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.compressstore.v4i32(<4 x i32> undef, i32* undef, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.compressstore.v2i32(<2 x i32> undef, i32* undef, <2 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 127 for instruction: call void @llvm.masked.compressstore.v32i16(<32 x i16> undef, i16* undef, <32 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 55 for instruction: call void @llvm.masked.compressstore.v16i16(<16 x i16> undef, i16* undef, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8i16(<8 x i16> undef, i16* undef, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.compressstore.v4i16(<4 x i16> undef, i16* undef, <4 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 255 for instruction: call void @llvm.masked.compressstore.v64i8(<64 x i8> undef, i8* undef, <64 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 127 for instruction: call void @llvm.masked.compressstore.v32i8(<32 x i8> undef, i8* undef, <32 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.compressstore.v16i8(<16 x i8> undef, i8* undef, <16 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8i8(<8 x i8> undef, i8* undef, <8 x i1> undef)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+; AVX512-LABEL: 'masked_compressstore'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 25 for instruction: call void @llvm.masked.compressstore.v8f64(<8 x double> undef, double* undef, <8 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.compressstore.v4f64(<4 x double> undef, double* undef, <4 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.compressstore.v2f64(<2 x double> undef, double* undef, <2 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.compressstore.v1f64(<1 x double> undef, double* undef, <1 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 55 for instruction: call void @llvm.masked.compressstore.v16f32(<16 x float> undef, float* undef, <16 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 25 for instruction: call void @llvm.masked.compressstore.v8f32(<8 x float> undef, float* undef, <8 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.compressstore.v4f32(<4 x float> undef, float* undef, <4 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: call void @llvm.masked.compressstore.v2f32(<2 x float> undef, float* undef, <2 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 29 for instruction: call void @llvm.masked.compressstore.v8i64(<8 x i64> undef, i64* undef, <8 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 13 for instruction: call void @llvm.masked.compressstore.v4i64(<4 x i64> undef, i64* undef, <4 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.compressstore.v2i64(<2 x i64> undef, i64* undef, <2 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.compressstore.v1i64(<1 x i64> undef, i64* undef, <1 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 59 for instruction: call void @llvm.masked.compressstore.v16i32(<16 x i32> undef, i32* undef, <16 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 27 for instruction: call void @llvm.masked.compressstore.v8i32(<8 x i32> undef, i32* undef, <8 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.compressstore.v4i32(<4 x i32> undef, i32* undef, <4 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.compressstore.v2i32(<2 x i32> undef, i32* undef, <2 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 119 for instruction: call void @llvm.masked.compressstore.v32i16(<32 x i16> undef, i16* undef, <32 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 55 for instruction: call void @llvm.masked.compressstore.v16i16(<16 x i16> undef, i16* undef, <16 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8i16(<8 x i16> undef, i16* undef, <8 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: call void @llvm.masked.compressstore.v4i16(<4 x i16> undef, i16* undef, <4 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 239 for instruction: call void @llvm.masked.compressstore.v64i8(<64 x i8> undef, i8* undef, <64 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 111 for instruction: call void @llvm.masked.compressstore.v32i8(<32 x i8> undef, i8* undef, <32 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 47 for instruction: call void @llvm.masked.compressstore.v16i8(<16 x i8> undef, i8* undef, <16 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 23 for instruction: call void @llvm.masked.compressstore.v8i8(<8 x i8> undef, i8* undef, <8 x i1> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 0
+;
+  call void @llvm.masked.compressstore.v8f64(<8 x double> undef, double* undef, <8 x i1> undef)
+  call void @llvm.masked.compressstore.v4f64(<4 x double> undef, double* undef, <4 x i1> undef)
+  call void @llvm.masked.compressstore.v2f64(<2 x double> undef, double* undef, <2 x i1> undef)
+  call void @llvm.masked.compressstore.v1f64(<1 x double> undef, double* undef, <1 x i1> undef)
+
+  call void @llvm.masked.compressstore.v16f32(<16 x float> undef, float* undef, <16 x i1> undef)
+  call void @llvm.masked.compressstore.v8f32(<8 x float> undef, float* undef, <8 x i1> undef)
+  call void @llvm.masked.compressstore.v4f32(<4 x float> undef, float* undef, <4 x i1> undef)
+  call void @llvm.masked.compressstore.v2f32(<2 x float> undef, float* undef, <2 x i1> undef)
+
+  call void @llvm.masked.compressstore.v8i64(<8 x i64> undef, i64* undef, <8 x i1> undef)
+  call void @llvm.masked.compressstore.v4i64(<4 x i64> undef, i64* undef, <4 x i1> undef)
+  call void @llvm.masked.compressstore.v2i64(<2 x i64> undef, i64* undef, <2 x i1> undef)
+  call void @llvm.masked.compressstore.v1i64(<1 x i64> undef, i64* undef, <1 x i1> undef)
+
+  call void @llvm.masked.compressstore.v16i32(<16 x i32> undef, i32* undef, <16 x i1> undef)
+  call void @llvm.masked.compressstore.v8i32(<8 x i32> undef, i32* undef, <8 x i1> undef)
+  call void @llvm.masked.compressstore.v4i32(<4 x i32> undef, i32* undef, <4 x i1> undef)
+  call void @llvm.masked.compressstore.v2i32(<2 x i32> undef, i32* undef, <2 x i1> undef)
+
+  call void @llvm.masked.compressstore.v32i16(<32 x i16> undef, i16* undef, <32 x i1> undef)
+  call void @llvm.masked.compressstore.v16i16(<16 x i16> undef, i16* undef, <16 x i1> undef)
+  call void @llvm.masked.compressstore.v8i16(<8 x i16> undef, i16* undef, <8 x i1> undef)
+  call void @llvm.masked.compressstore.v4i16(<4 x i16> undef, i16* undef, <4 x i1> undef)
+
+  call void @llvm.masked.compressstore.v64i8(<64 x i8> undef, i8* undef, <64 x i1> undef)
+  call void @llvm.masked.compressstore.v32i8(<32 x i8> undef, i8* undef, <32 x i1> undef)
+  call void @llvm.masked.compressstore.v16i8(<16 x i8> undef, i8* undef, <16 x i1> undef)
+  call void @llvm.masked.compressstore.v8i8(<8 x i8> undef, i8* undef, <8 x i1> undef)
+
+  ret i32 0
+}
+
+define <2 x double> @test1(<2 x i64> %trigger, <2 x double>* %addr, <2 x double> %dst) {
+; SSE2-LABEL: 'test1'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %mask = icmp eq <2 x i64> %trigger, zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %addr, i32 4, <2 x i1> %mask, <2 x double> %dst)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+; SSE42-LABEL: 'test1'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i64> %trigger, zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %addr, i32 4, <2 x i1> %mask, <2 x double> %dst)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+; AVX-LABEL: 'test1'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i64> %trigger, zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %addr, i32 4, <2 x i1> %mask, <2 x double> %dst)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+; AVX512-LABEL: 'test1'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i64> %trigger, zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %addr, i32 4, <2 x i1> %mask, <2 x double> %dst)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+  %mask = icmp eq <2 x i64> %trigger, zeroinitializer
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %addr, i32 4, <2 x i1>%mask, <2 x double>%dst)
+  ret <2 x double> %res
+}
+
+define <4 x i32> @test2(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %dst) {
+; SSE2-LABEL: 'test2'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1> %mask, <4 x i32> %dst)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; SSE42-LABEL: 'test2'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1> %mask, <4 x i32> %dst)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; AVX-LABEL: 'test2'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1> %mask, <4 x i32> %dst)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; AVX512-LABEL: 'test2'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1> %mask, <4 x i32> %dst)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+  %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+  %res = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %addr, i32 4, <4 x i1>%mask, <4 x i32>%dst)
+  ret <4 x i32> %res
+}
+
+define void @test3(<4 x i32> %trigger, <4 x i32>* %addr, <4 x i32> %val) {
+; SSE2-LABEL: 'test3'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1> %mask)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SSE42-LABEL: 'test3'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1> %mask)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX-LABEL: 'test3'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1> %mask)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX512-LABEL: 'test3'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %addr, i32 4, <4 x i1> %mask)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %mask = icmp eq <4 x i32> %trigger, zeroinitializer
+  call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>%val, <4 x i32>* %addr, i32 4, <4 x i1>%mask)
+  ret void
+}
+
+define <8 x float> @test4(<8 x i32> %trigger, <8 x float>* %addr, <8 x float> %dst) {
+; SSE2-LABEL: 'test4'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %mask = icmp eq <8 x i32> %trigger, zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 37 for instruction: %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 4, <8 x i1> %mask, <8 x float> %dst)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x float> %res
+;
+; SSE42-LABEL: 'test4'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %mask = icmp eq <8 x i32> %trigger, zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 4, <8 x i1> %mask, <8 x float> %dst)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x float> %res
+;
+; AVX1-LABEL: 'test4'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %mask = icmp eq <8 x i32> %trigger, zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 4, <8 x i1> %mask, <8 x float> %dst)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x float> %res
+;
+; AVX2-LABEL: 'test4'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <8 x i32> %trigger, zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 4, <8 x i1> %mask, <8 x float> %dst)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x float> %res
+;
+; SKL-LABEL: 'test4'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <8 x i32> %trigger, zeroinitializer
+; SKL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 4, <8 x i1> %mask, <8 x float> %dst)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x float> %res
+;
+; AVX512-LABEL: 'test4'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <8 x i32> %trigger, zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 4, <8 x i1> %mask, <8 x float> %dst)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x float> %res
+;
+  %mask = icmp eq <8 x i32> %trigger, zeroinitializer
+  %res = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* %addr, i32 4, <8 x i1>%mask, <8 x float>%dst)
+  ret <8 x float> %res
+}
+
+define void @test5(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %val) {
+; SSE2-LABEL: 'test5'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> %val, <2 x float>* %addr, i32 4, <2 x i1> %mask)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SSE42-LABEL: 'test5'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> %val, <2 x float>* %addr, i32 4, <2 x i1> %mask)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX-LABEL: 'test5'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> %val, <2 x float>* %addr, i32 4, <2 x i1> %mask)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX512-LABEL: 'test5'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.store.v2f32.p0v2f32(<2 x float> %val, <2 x float>* %addr, i32 4, <2 x i1> %mask)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+  call void @llvm.masked.store.v2f32.p0v2f32(<2 x float>%val, <2 x float>* %addr, i32 4, <2 x i1>%mask)
+  ret void
+}
+
+define void @test6(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %val) {
+; SSE2-LABEL: 'test6'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> %val, <2 x i32>* %addr, i32 4, <2 x i1> %mask)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SSE42-LABEL: 'test6'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> %val, <2 x i32>* %addr, i32 4, <2 x i1> %mask)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX-LABEL: 'test6'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> %val, <2 x i32>* %addr, i32 4, <2 x i1> %mask)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX512-LABEL: 'test6'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> %val, <2 x i32>* %addr, i32 4, <2 x i1> %mask)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+  call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>%val, <2 x i32>* %addr, i32 4, <2 x i1>%mask)
+  ret void
+}
+
+define <2 x float> @test7(<2 x i32> %trigger, <2 x float>* %addr, <2 x float> %dst) {
+; SSE2-LABEL: 'test7'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* %addr, i32 4, <2 x i1> %mask, <2 x float> %dst)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x float> %res
+;
+; SSE42-LABEL: 'test7'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* %addr, i32 4, <2 x i1> %mask, <2 x float> %dst)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x float> %res
+;
+; AVX-LABEL: 'test7'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* %addr, i32 4, <2 x i1> %mask, <2 x float> %dst)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x float> %res
+;
+; AVX512-LABEL: 'test7'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %res = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* %addr, i32 4, <2 x i1> %mask, <2 x float> %dst)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x float> %res
+;
+  %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+  %res = call <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>* %addr, i32 4, <2 x i1>%mask, <2 x float>%dst)
+  ret <2 x float> %res
+}
+
+define <2 x i32> @test8(<2 x i32> %trigger, <2 x i32>* %addr, <2 x i32> %dst) {
+; SSE2-LABEL: 'test8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %res = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %addr, i32 4, <2 x i1> %mask, <2 x i32> %dst)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %res
+;
+; SSE42-LABEL: 'test8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %addr, i32 4, <2 x i1> %mask, <2 x i32> %dst)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %res
+;
+; AVX-LABEL: 'test8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %addr, i32 4, <2 x i1> %mask, <2 x i32> %dst)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %res
+;
+; AVX512-LABEL: 'test8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %res = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %addr, i32 4, <2 x i1> %mask, <2 x i32> %dst)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %res
+;
+  %mask = icmp eq <2 x i32> %trigger, zeroinitializer
+  %res = call <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>* %addr, i32 4, <2 x i1>%mask, <2 x i32>%dst)
+  ret <2 x i32> %res
+}
+
+define <2 x double> @test_gather_2f64(<2 x double*> %ptrs, <2 x i1> %mask, <2 x double> %src0)  {
+; SSE2-LABEL: 'test_gather_2f64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+; SSE42-LABEL: 'test_gather_2f64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+; AVX1-LABEL: 'test_gather_2f64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+; AVX2-LABEL: 'test_gather_2f64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+; SKL-LABEL: 'test_gather_2f64'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+; AVX512-LABEL: 'test_gather_2f64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %res
+;
+  %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %src0)
+  ret <2 x double> %res
+}
+
+define <4 x i32> @test_gather_4i32(<4 x i32*> %ptrs, <4 x i1> %mask, <4 x i32> %src0)  {
+; SSE2-LABEL: 'test_gather_4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 27 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; SSE42-LABEL: 'test_gather_4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; AVX1-LABEL: 'test_gather_4i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; AVX2-LABEL: 'test_gather_4i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; SKL-LABEL: 'test_gather_4i32'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; KNL-LABEL: 'test_gather_4i32'
+; KNL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; SKX-LABEL: 'test_gather_4i32'
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+  %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> %mask, <4 x i32> %src0)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_gather_4i32_const_mask(<4 x i32*> %ptrs, <4 x i32> %src0)  {
+; SSE2-LABEL: 'test_gather_4i32_const_mask'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> %src0)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; SSE42-LABEL: 'test_gather_4i32_const_mask'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> %src0)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; AVX1-LABEL: 'test_gather_4i32_const_mask'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> %src0)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; AVX2-LABEL: 'test_gather_4i32_const_mask'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> %src0)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; SKL-LABEL: 'test_gather_4i32_const_mask'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> %src0)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; KNL-LABEL: 'test_gather_4i32_const_mask'
+; KNL-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> %src0)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+; SKX-LABEL: 'test_gather_4i32_const_mask'
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> %src0)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %res
+;
+  %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> %src0)
+  ret <4 x i32> %res
+}
+
+define <16 x float> @test_gather_16f32_const_mask(float* %base, <16 x i32> %ind) {
+; SSE2-LABEL: 'test_gather_16f32_const_mask'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 40 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; SSE42-LABEL: 'test_gather_16f32_const_mask'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX1-LABEL: 'test_gather_16f32_const_mask'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX2-LABEL: 'test_gather_16f32_const_mask'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; SKL-LABEL: 'test_gather_16f32_const_mask'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; SKL-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX512-LABEL: 'test_gather_16f32_const_mask'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+  %sext_ind = sext <16 x i32> %ind to <16 x i64>
+  %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+
+  %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+  ret <16 x float>%res
+}
+
+define <16 x float> @test_gather_16f32_var_mask(float* %base, <16 x i32> %ind, <16 x i1>%mask) {
+; SSE2-LABEL: 'test_gather_16f32_var_mask'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 87 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; SSE42-LABEL: 'test_gather_16f32_var_mask'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX1-LABEL: 'test_gather_16f32_var_mask'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX2-LABEL: 'test_gather_16f32_var_mask'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; SKL-LABEL: 'test_gather_16f32_var_mask'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; SKL-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX512-LABEL: 'test_gather_16f32_var_mask'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+  %sext_ind = sext <16 x i32> %ind to <16 x i64>
+  %gep.v = getelementptr float, float* %base, <16 x i64> %sext_ind
+
+  %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+  ret <16 x float>%res
+}
+
+define <16 x float> @test_gather_16f32_ra_var_mask(<16 x float*> %ptrs, <16 x i32> %ind, <16 x i1>%mask) {
+; SSE2-LABEL: 'test_gather_16f32_ra_var_mask'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x float*> %ptrs, <16 x i64> %sext_ind
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 87 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; SSE42-LABEL: 'test_gather_16f32_ra_var_mask'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x float*> %ptrs, <16 x i64> %sext_ind
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX1-LABEL: 'test_gather_16f32_ra_var_mask'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x float*> %ptrs, <16 x i64> %sext_ind
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX2-LABEL: 'test_gather_16f32_ra_var_mask'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x float*> %ptrs, <16 x i64> %sext_ind
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 76 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; SKL-LABEL: 'test_gather_16f32_ra_var_mask'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x float*> %ptrs, <16 x i64> %sext_ind
+; SKL-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX512-LABEL: 'test_gather_16f32_ra_var_mask'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, <16 x float*> %ptrs, <16 x i64> %sext_ind
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+  %sext_ind = sext <16 x i32> %ind to <16 x i64>
+  %gep.v = getelementptr float, <16 x float*> %ptrs, <16 x i64> %sext_ind
+
+  %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.v, i32 4, <16 x i1> %mask, <16 x float> undef)
+  ret <16 x float>%res
+}
+
+define <16 x float> @test_gather_16f32_const_mask2(float* %base, <16 x i32> %ind) {
+; SSE2-LABEL: 'test_gather_16f32_const_mask2'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x float*> poison, float* %base, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 40 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; SSE42-LABEL: 'test_gather_16f32_const_mask2'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x float*> poison, float* %base, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX1-LABEL: 'test_gather_16f32_const_mask2'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x float*> poison, float* %base, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX2-LABEL: 'test_gather_16f32_const_mask2'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x float*> poison, float* %base, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; SKL-LABEL: 'test_gather_16f32_const_mask2'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x float*> poison, float* %base, i32 0
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
+; SKL-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+; AVX512-LABEL: 'test_gather_16f32_const_mask2'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x float*> poison, float* %base, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %sext_ind = sext <16 x i32> %ind to <16 x i64>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x float> %res
+;
+  %broadcast.splatinsert = insertelement <16 x float*> poison, float* %base, i32 0
+  %broadcast.splat = shufflevector <16 x float*> %broadcast.splatinsert, <16 x float*> undef, <16 x i32> zeroinitializer
+
+  %sext_ind = sext <16 x i32> %ind to <16 x i64>
+  %gep.random = getelementptr float, <16 x float*> %broadcast.splat, <16 x i64> %sext_ind
+
+  %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
+  ret <16 x float>%res
+}
+
+define void @test_scatter_16i32(i32* %base, <16 x i32> %ind, i16 %mask, <16 x i32>%val) {
+; SSE2-LABEL: 'test_scatter_16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splatinsert = insertelement <16 x i32*> poison, i32* %base, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 91 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SSE42-LABEL: 'test_scatter_16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x i32*> poison, i32* %base, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX1-LABEL: 'test_scatter_16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x i32*> poison, i32* %base, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 72 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX2-LABEL: 'test_scatter_16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x i32*> poison, i32* %base, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 72 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SKL-LABEL: 'test_scatter_16i32'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x i32*> poison, i32* %base, i32 0
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1>
+; SKL-NEXT:  Cost Model: Found an estimated cost of 72 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX512-LABEL: 'test_scatter_16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splatinsert = insertelement <16 x i32*> poison, i32* %base, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %imask = bitcast i16 %mask to <16 x i1>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 18 for instruction: call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32> %val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  %broadcast.splatinsert = insertelement <16 x i32*> poison, i32* %base, i32 0
+  %broadcast.splat = shufflevector <16 x i32*> %broadcast.splatinsert, <16 x i32*> undef, <16 x i32> zeroinitializer
+
+  %gep.random = getelementptr i32, <16 x i32*> %broadcast.splat, <16 x i32> %ind
+  %imask = bitcast i16 %mask to <16 x i1>
+  call void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32>%val, <16 x i32*> %gep.random, i32 4, <16 x i1> %imask)
+  ret void
+}
+
+define void @test_scatter_8i32(<8 x i32>%a1, <8 x i32*> %ptr, <8 x i1>%mask) {
+; SSE2-LABEL: 'test_scatter_8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 38 for instruction: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> %mask)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SSE42-LABEL: 'test_scatter_8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> %mask)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX-LABEL: 'test_scatter_8i32'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 36 for instruction: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> %mask)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX512-LABEL: 'test_scatter_8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> %mask)
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  call void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32> %a1, <8 x i32*> %ptr, i32 4, <8 x i1> %mask)
+  ret void
+}
+
+define void @test_scatter_4i32(<4 x i32>%a1, <4 x i32*> %ptr, <4 x i1>%mask) {
+; SSE2-LABEL: 'test_scatter_4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %a1, <4 x i32*> %ptr, i32 4, <4 x i1> %mask)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SSE42-LABEL: 'test_scatter_4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %a1, <4 x i32*> %ptr, i32 4, <4 x i1> %mask)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; AVX-LABEL: 'test_scatter_4i32'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %a1, <4 x i32*> %ptr, i32 4, <4 x i1> %mask)
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; KNL-LABEL: 'test_scatter_4i32'
+; KNL-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %a1, <4 x i32*> %ptr, i32 4, <4 x i1> %mask)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+; SKX-LABEL: 'test_scatter_4i32'
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %a1, <4 x i32*> %ptr, i32 4, <4 x i1> %mask)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %a1, <4 x i32*> %ptr, i32 4, <4 x i1> %mask)
+  ret void
+}
+
+define <4 x float> @test_gather_4f32(float* %ptr, <4 x i32> %ind, <4 x i1>%mask) {
+; SSE2-LABEL: 'test_gather_4f32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 21 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; SSE42-LABEL: 'test_gather_4f32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; AVX1-LABEL: 'test_gather_4f32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; AVX2-LABEL: 'test_gather_4f32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; SKL-LABEL: 'test_gather_4f32'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; KNL-LABEL: 'test_gather_4f32'
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; KNL-NEXT:  Cost Model: Found an estimated cost of 15 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; SKX-LABEL: 'test_gather_4f32'
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+  %sext_ind = sext <4 x i32> %ind to <4 x i64>
+  %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+
+  %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> %mask, <4 x float> undef)
+  ret <4 x float>%res
+}
+
+define <4 x float> @test_gather_4f32_const_mask(float* %ptr, <4 x i32> %ind) {
+; SSE2-LABEL: 'test_gather_4f32_const_mask'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; SSE42-LABEL: 'test_gather_4f32_const_mask'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; AVX1-LABEL: 'test_gather_4f32_const_mask'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; AVX2-LABEL: 'test_gather_4f32_const_mask'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; SKL-LABEL: 'test_gather_4f32_const_mask'
+; SKL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; SKL-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
+; SKL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; KNL-LABEL: 'test_gather_4f32_const_mask'
+; KNL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; KNL-NEXT:  Cost Model: Found an estimated cost of 7 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
+; KNL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+; SKX-LABEL: 'test_gather_4f32_const_mask'
+; SKX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %sext_ind = sext <4 x i32> %ind to <4 x i64>
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+; SKX-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
+; SKX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %res
+;
+  %sext_ind = sext <4 x i32> %ind to <4 x i64>
+  %gep.v = getelementptr float, float* %ptr, <4 x i64> %sext_ind
+
+  %res = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> %gep.v, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef)
+  ret <4 x float>%res
+}
+
+declare <8 x double> @llvm.masked.load.v8f64.p0v8f64(<8 x double>*, i32, <8 x i1>, <8 x double>)
+declare <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>*, i32, <4 x i1>, <4 x double>)
+declare <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>*, i32, <2 x i1>, <2 x double>)
+declare <1 x double> @llvm.masked.load.v1f64.p0v1f64(<1 x double>*, i32, <1 x i1>, <1 x double>)
+
+declare <16 x float> @llvm.masked.load.v16f32.p0v16f32(<16 x float>*, i32, <16 x i1>, <16 x float>)
+declare <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>*, i32, <8 x i1>, <8 x float>)
+declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>)
+declare <2 x float> @llvm.masked.load.v2f32.p0v2f32(<2 x float>*, i32, <2 x i1>, <2 x float>)
+
+declare <8 x i64> @llvm.masked.load.v8i64.p0v8i64(<8 x i64>*, i32, <8 x i1>, <8 x i64>)
+declare <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>*, i32, <4 x i1>, <4 x i64>)
+declare <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>*, i32, <2 x i1>, <2 x i64>)
+declare <1 x i64> @llvm.masked.load.v1i64.p0v1i64(<1 x i64>*, i32, <1 x i1>, <1 x i64>)
+
+declare <16 x i32> @llvm.masked.load.v16i32.p0v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
+declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>)
+declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)
+declare <2 x i32> @llvm.masked.load.v2i32.p0v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>)
+
+declare <32 x i16> @llvm.masked.load.v32i16.p0v32i16(<32 x i16>*, i32, <32 x i1>, <32 x i16>)
+declare <16 x i16> @llvm.masked.load.v16i16.p0v16i16(<16 x i16>*, i32, <16 x i1>, <16 x i16>)
+declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32, <8 x i1>, <8 x i16>)
+declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32, <4 x i1>, <4 x i16>)
+
+declare <64 x i8> @llvm.masked.load.v64i8.p0v64i8(<64 x i8>*, i32, <64 x i1>, <64 x i8>)
+declare <32 x i8> @llvm.masked.load.v32i8.p0v32i8(<32 x i8>*, i32, <32 x i1>, <32 x i8>)
+declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32, <16 x i1>, <16 x i8>)
+declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32, <8 x i1>, <8 x i8>)
+
+declare void @llvm.masked.store.v8f64.p0v8f64(<8 x double>, <8 x double>*, i32, <8 x i1>)
+declare void @llvm.masked.store.v4f64.p0v4f64(<4 x double>, <4 x double>*, i32, <4 x i1>)
+declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32, <2 x i1>)
+declare void @llvm.masked.store.v1f64.p0v1f64(<1 x double>, <1 x double>*, i32, <1 x i1>)
+
+declare void @llvm.masked.store.v16f32.p0v16f32(<16 x float>, <16 x float>*, i32, <16 x i1>)
+declare void @llvm.masked.store.v8f32.p0v8f32(<8 x float>, <8 x float>*, i32, <8 x i1>)
+declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>)
+declare void @llvm.masked.store.v2f32.p0v2f32(<2 x float>, <2 x float>*, i32, <2 x i1>)
+
+declare void @llvm.masked.store.v8i64.p0v8i64(<8 x i64>, <8 x i64>*, i32, <8 x i1>)
+declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>)
+declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)
+declare void @llvm.masked.store.v1i64.p0v1i64(<1 x i64>, <1 x i64>*, i32, <1 x i1>)
+
+declare void @llvm.masked.store.v16i32.p0v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
+declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
+declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
+declare void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)
+
+declare void @llvm.masked.store.v32i16.p0v32i16(<32 x i16>, <32 x i16>*, i32, <32 x i1>)
+declare void @llvm.masked.store.v16i16.p0v16i16(<16 x i16>, <16 x i16>*, i32, <16 x i1>)
+declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32, <8 x i1>)
+declare void @llvm.masked.store.v4i16.p0v4i16(<4 x i16>, <4 x i16>*, i32, <4 x i1>)
+
+declare void @llvm.masked.store.v64i8.p0v64i8(<64 x i8>, <64 x i8>*, i32, <64 x i1>)
+declare void @llvm.masked.store.v32i8.p0v32i8(<32 x i8>, <32 x i8>*, i32, <32 x i1>)
+declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32, <16 x i1>)
+declare void @llvm.masked.store.v8i8.p0v8i8(<8 x i8>, <8 x i8>*, i32, <8 x i1>)
+
+declare <8 x double> @llvm.masked.gather.v8f64.v8p0f64(<8 x double*>, i32, <8 x i1>, <8 x double>)
+declare <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*>, i32, <4 x i1>, <4 x double>)
+declare <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*>, i32, <2 x i1>, <2 x double>)
+declare <1 x double> @llvm.masked.gather.v1f64.v1p0f64(<1 x double*>, i32, <1 x i1>, <1 x double>)
+
+declare <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*>, i32, <16 x i1>, <16 x float>)
+declare <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*>, i32, <8 x i1>, <8 x float>)
+declare <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*>, i32, <4 x i1>, <4 x float>)
+declare <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*>, i32, <2 x i1>, <2 x float>)
+
+declare <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*>, i32, <8 x i1>, <8 x i64>)
+declare <4 x i64> @llvm.masked.gather.v4i64.v4p0i64(<4 x i64*>, i32, <4 x i1>, <4 x i64>)
+declare <2 x i64> @llvm.masked.gather.v2i64.v2p0i64(<2 x i64*>, i32, <2 x i1>, <2 x i64>)
+declare <1 x i64> @llvm.masked.gather.v1i64.v1p0i64(<1 x i64*>, i32, <1 x i1>, <1 x i64>)
+
+declare <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*>, i32, <16 x i1>, <16 x i32>)
+declare <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*>, i32, <8 x i1>, <8 x i32>)
+declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
+declare <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*>, i32, <2 x i1>, <2 x i32>)
+
+declare <32 x i16> @llvm.masked.gather.v32i16.v32p0i16(<32 x i16*>, i32, <32 x i1>, <32 x i16>)
+declare <16 x i16> @llvm.masked.gather.v16i16.v16p0i16(<16 x i16*>, i32, <16 x i1>, <16 x i16>)
+declare <8 x i16> @llvm.masked.gather.v8i16.v8p0i16(<8 x i16*>, i32, <8 x i1>, <8 x i16>)
+declare <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*>, i32, <4 x i1>, <4 x i16>)
+
+declare <64 x i8> @llvm.masked.gather.v64i8.v64p0i8(<64 x i8*>, i32, <64 x i1>, <64 x i8>)
+declare <32 x i8> @llvm.masked.gather.v32i8.v32p0i8(<32 x i8*>, i32, <32 x i1>, <32 x i8>)
+declare <16 x i8> @llvm.masked.gather.v16i8.v16p0i8(<16 x i8*>, i32, <16 x i1>, <16 x i8>)
+declare <8 x i8> @llvm.masked.gather.v8i8.v8p0i8(<8 x i8*>, i32, <8 x i1>, <8 x i8>)
+
+declare void @llvm.masked.scatter.v8f64.v8p0f64(<8 x double>, <8 x double*>, i32, <8 x i1>)
+declare void @llvm.masked.scatter.v4f64.v4p0f64(<4 x double>, <4 x double*>, i32, <4 x i1>)
+declare void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double>, <2 x double*>, i32, <2 x i1>)
+declare void @llvm.masked.scatter.v1f64.v1p0f64(<1 x double>, <1 x double*>, i32, <1 x i1>)
+
+declare void @llvm.masked.scatter.v16f32.v16p0f32(<16 x float>, <16 x float*>, i32, <16 x i1>)
+declare void @llvm.masked.scatter.v8f32.v8p0f32(<8 x float>, <8 x float*>, i32, <8 x i1>)
+declare void @llvm.masked.scatter.v4f32.v4p0f32(<4 x float>, <4 x float*>, i32, <4 x i1>)
+declare void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float>, <2 x float*>, i32, <2 x i1>)
+
+declare void @llvm.masked.scatter.v8i64.v8p0i64(<8 x i64>, <8 x i64*>, i32, <8 x i1>)
+declare void @llvm.masked.scatter.v4i64.v4p0i64(<4 x i64>, <4 x i64*>, i32, <4 x i1>)
+declare void @llvm.masked.scatter.v2i64.v2p0i64(<2 x i64>, <2 x i64*>, i32, <2 x i1>)
+declare void @llvm.masked.scatter.v1i64.v1p0i64(<1 x i64>, <1 x i64*>, i32, <1 x i1>)
+
+declare void @llvm.masked.scatter.v16i32.v16p0i32(<16 x i32>, <16 x i32*>, i32, <16 x i1>)
+declare void @llvm.masked.scatter.v8i32.v8p0i32(<8 x i32>, <8 x i32*>, i32, <8 x i1>)
+declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>)
+declare void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32>, <2 x i32*>, i32, <2 x i1>)
+
+declare void @llvm.masked.scatter.v32i16.v32p0i16(<32 x i16>, <32 x i16*>, i32, <32 x i1>)
+declare void @llvm.masked.scatter.v16i16.v16p0i16(<16 x i16>, <16 x i16*>, i32, <16 x i1>)
+declare void @llvm.masked.scatter.v8i16.v8p0i16(<8 x i16>, <8 x i16*>, i32, <8 x i1>)
+declare void @llvm.masked.scatter.v4i16.v4p0i16(<4 x i16>, <4 x i16*>, i32, <4 x i1>)
+
+declare void @llvm.masked.scatter.v64i8.v64p0i8(<64 x i8>, <64 x i8*>, i32, <64 x i1>)
+declare void @llvm.masked.scatter.v32i8.v32p0i8(<32 x i8>, <32 x i8*>, i32, <32 x i1>)
+declare void @llvm.masked.scatter.v16i8.v16p0i8(<16 x i8>, <16 x i8*>, i32, <16 x i1>)
+declare void @llvm.masked.scatter.v8i8.v8p0i8(<8 x i8>, <8 x i8*>, i32, <8 x i1>)
+
+declare <8 x double> @llvm.masked.expandload.v8f64(double*, <8 x i1>, <8 x double>)
+declare <4 x double> @llvm.masked.expandload.v4f64(double*, <4 x i1>, <4 x double>)
+declare <2 x double> @llvm.masked.expandload.v2f64(double*, <2 x i1>, <2 x double>)
+declare <1 x double> @llvm.masked.expandload.v1f64(double*, <1 x i1>, <1 x double>)
+
+declare <16 x float> @llvm.masked.expandload.v16f32(float*, <16 x i1>, <16 x float>)
+declare <8 x float> @llvm.masked.expandload.v8f32(float*, <8 x i1>, <8 x float>)
+declare <4 x float> @llvm.masked.expandload.v4f32(float*, <4 x i1>, <4 x float>)
+declare <2 x float> @llvm.masked.expandload.v2f32(float*, <2 x i1>, <2 x float>)
+
+declare <8 x i64> @llvm.masked.expandload.v8i64(i64*, <8 x i1>, <8 x i64>)
+declare <4 x i64> @llvm.masked.expandload.v4i64(i64*, <4 x i1>, <4 x i64>)
+declare <2 x i64> @llvm.masked.expandload.v2i64(i64*, <2 x i1>, <2 x i64>)
+declare <1 x i64> @llvm.masked.expandload.v1i64(i64*, <1 x i1>, <1 x i64>)
+
+declare <16 x i32> @llvm.masked.expandload.v16i32(i32*, <16 x i1>, <16 x i32>)
+declare <8 x i32> @llvm.masked.expandload.v8i32(i32*, <8 x i1>, <8 x i32>)
+declare <4 x i32> @llvm.masked.expandload.v4i32(i32*, <4 x i1>, <4 x i32>)
+declare <2 x i32> @llvm.masked.expandload.v2i32(i32*, <2 x i1>, <2 x i32>)
+
+declare <32 x i16> @llvm.masked.expandload.v32i16(i16*, <32 x i1>, <32 x i16>)
+declare <16 x i16> @llvm.masked.expandload.v16i16(i16*, <16 x i1>, <16 x i16>)
+declare <8 x i16> @llvm.masked.expandload.v8i16(i16*, <8 x i1>, <8 x i16>)
+declare <4 x i16> @llvm.masked.expandload.v4i16(i16*, <4 x i1>, <4 x i16>)
+
+declare <64 x i8> @llvm.masked.expandload.v64i8(i8*, <64 x i1>, <64 x i8>)
+declare <32 x i8> @llvm.masked.expandload.v32i8(i8*, <32 x i1>, <32 x i8>)
+declare <16 x i8> @llvm.masked.expandload.v16i8(i8*, <16 x i1>, <16 x i8>)
+declare <8 x i8> @llvm.masked.expandload.v8i8(i8*, <8 x i1>, <8 x i8>)
+
+declare void @llvm.masked.compressstore.v8f64(<8 x double>, double*, <8 x i1>)
+declare void @llvm.masked.compressstore.v4f64(<4 x double>, double*, <4 x i1>)
+declare void @llvm.masked.compressstore.v2f64(<2 x double>, double*, <2 x i1>)
+declare void @llvm.masked.compressstore.v1f64(<1 x double>, double*, <1 x i1>)
+
+declare void @llvm.masked.compressstore.v16f32(<16 x float>, float*, <16 x i1>)
+declare void @llvm.masked.compressstore.v8f32(<8 x float>, float*, <8 x i1>)
+declare void @llvm.masked.compressstore.v4f32(<4 x float>, float*, <4 x i1>)
+declare void @llvm.masked.compressstore.v2f32(<2 x float>, float*, <2 x i1>)
+
+declare void @llvm.masked.compressstore.v8i64(<8 x i64>, i64*, <8 x i1>)
+declare void @llvm.masked.compressstore.v4i64(<4 x i64>, i64*, <4 x i1>)
+declare void @llvm.masked.compressstore.v2i64(<2 x i64>, i64*, <2 x i1>)
+declare void @llvm.masked.compressstore.v1i64(<1 x i64>, i64*, <1 x i1>)
+
+declare void @llvm.masked.compressstore.v16i32(<16 x i32>, i32*, <16 x i1>)
+declare void @llvm.masked.compressstore.v8i32(<8 x i32>, i32*, <8 x i1>)
+declare void @llvm.masked.compressstore.v4i32(<4 x i32>, i32*, <4 x i1>)
+declare void @llvm.masked.compressstore.v2i32(<2 x i32>, i32*, <2 x i1>)
+
+declare void @llvm.masked.compressstore.v32i16(<32 x i16>, i16*, <32 x i1>)
+declare void @llvm.masked.compressstore.v16i16(<16 x i16>, i16*, <16 x i1>)
+declare void @llvm.masked.compressstore.v8i16(<8 x i16>, i16*, <8 x i1>)
+declare void @llvm.masked.compressstore.v4i16(<4 x i16>, i16*, <4 x i1>)
+
+declare void @llvm.masked.compressstore.v64i8(<64 x i8>, i8*, <64 x i1>)
+declare void @llvm.masked.compressstore.v32i8(<32 x i8>, i8*, <32 x i1>)
+declare void @llvm.masked.compressstore.v16i8(<16 x i8>, i8*, <16 x i1>)
+declare void @llvm.masked.compressstore.v8i8(<8 x i8>, i8*, <8 x i1>)
diff --git a/llvm/test/Analysis/CostModel/X86/uniformshift-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/uniformshift-inseltpoison.ll
new file mode 100644
index 0000000000000..bfbfcdbcd5e32
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/uniformshift-inseltpoison.ll
@@ -0,0 +1,39 @@
+; RUN: llc -mtriple=x86_64-apple-darwin -mattr=+sse2 < %s | FileCheck --check-prefix=SSE2-CODEGEN %s
+; RUN: opt -mtriple=x86_64-apple-darwin -mattr=+sse2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s
+
+define <4 x i32> @shl(<4 x i32> %vector, i32 %scalar) {
+entry:
+  ; SSE2: 'shl'
+  ; SSE2: cost of 1 {{.*}} shl
+  ; SSE2-CODEGEN: movd  %edi, %xmm1
+  ; SSE2-CODEGEN: pslld %xmm1, %xmm0
+  %insert = insertelement <4 x i32> poison, i32 %scalar, i32 0
+  %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %ret = shl <4 x i32> %vector , %splat
+  ret <4 x i32> %ret
+}
+
+define <4 x i32> @ashr(<4 x i32> %vector, i32 %scalar) {
+entry:
+  ; SSE2: 'ashr'
+  ; SSE2: cost of 1 {{.*}} ashr
+  ; SSE2-CODEGEN: movd  %edi, %xmm1
+  ; SSE2-CODEGEN: psrad %xmm1, %xmm0
+  %insert = insertelement <4 x i32> poison, i32 %scalar, i32 0
+  %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %ret = ashr <4 x i32> %vector , %splat
+  ret <4 x i32> %ret
+}
+
+define <4 x i32> @lshr(<4 x i32> %vector, i32 %scalar) {
+entry:
+  ; SSE2: 'lshr'
+  ; SSE2: cost of 1 {{.*}} lshr
+  ; SSE2-CODEGEN: movd  %edi, %xmm1
+  ; SSE2-CODEGEN: psrld %xmm1, %xmm0
+  %insert = insertelement <4 x i32> poison, i32 %scalar, i32 0
+  %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %ret = lshr <4 x i32> %vector , %splat
+  ret <4 x i32> %ret
+}
+
diff --git a/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll
new file mode 100644
index 0000000000000..f6f5ed8029b13
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/vector-insert-inseltpoison.ll
@@ -0,0 +1,1270 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mattr=+sse3 | FileCheck %s --check-prefixes=SSE,SSE3
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE4
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE4
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mattr=+avx | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mattr=+avx2 | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX512
+;
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mcpu=slm | FileCheck %s --check-prefixes=SSE,SLM
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mcpu=goldmont | FileCheck %s --check-prefixes=SSE,GLM
+; RUN: opt < %s -mtriple=x86_64-apple-macosx10.8.0 -cost-model -analyze -mcpu=btver2 | FileCheck %s --check-prefixes=AVX
+
+define i32 @insert_double(i32 %arg) {
+; SSE-LABEL: 'insert_double'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f64_a = insertelement <2 x double> poison, double undef, i32 %arg
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f64_0 = insertelement <2 x double> poison, double undef, i32 0
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f64_1 = insertelement <2 x double> poison, double undef, i32 1
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f64_a = insertelement <4 x double> poison, double undef, i32 %arg
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f64_0 = insertelement <4 x double> poison, double undef, i32 0
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f64_3 = insertelement <4 x double> poison, double undef, i32 3
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f64_a = insertelement <8 x double> poison, double undef, i32 %arg
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f64_0 = insertelement <8 x double> poison, double undef, i32 0
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f64_3 = insertelement <8 x double> poison, double undef, i32 3
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f64_4 = insertelement <8 x double> poison, double undef, i32 4
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f64_7 = insertelement <8 x double> poison, double undef, i32 7
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX-LABEL: 'insert_double'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f64_a = insertelement <2 x double> poison, double undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f64_0 = insertelement <2 x double> poison, double undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f64_1 = insertelement <2 x double> poison, double undef, i32 1
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f64_a = insertelement <4 x double> poison, double undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f64_0 = insertelement <4 x double> poison, double undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4f64_3 = insertelement <4 x double> poison, double undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f64_a = insertelement <8 x double> poison, double undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f64_0 = insertelement <8 x double> poison, double undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8f64_3 = insertelement <8 x double> poison, double undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f64_4 = insertelement <8 x double> poison, double undef, i32 4
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8f64_7 = insertelement <8 x double> poison, double undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX512-LABEL: 'insert_double'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f64_a = insertelement <2 x double> poison, double undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f64_0 = insertelement <2 x double> poison, double undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f64_1 = insertelement <2 x double> poison, double undef, i32 1
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f64_a = insertelement <4 x double> poison, double undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f64_0 = insertelement <4 x double> poison, double undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4f64_3 = insertelement <4 x double> poison, double undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f64_a = insertelement <8 x double> poison, double undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f64_0 = insertelement <8 x double> poison, double undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8f64_3 = insertelement <8 x double> poison, double undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8f64_4 = insertelement <8 x double> poison, double undef, i32 4
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8f64_7 = insertelement <8 x double> poison, double undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+  %v2f64_a = insertelement <2 x double> poison, double undef, i32 %arg
+  %v2f64_0 = insertelement <2 x double> poison, double undef, i32 0
+  %v2f64_1 = insertelement <2 x double> poison, double undef, i32 1
+
+  %v4f64_a = insertelement <4 x double> poison, double undef, i32 %arg
+  %v4f64_0 = insertelement <4 x double> poison, double undef, i32 0
+  %v4f64_3 = insertelement <4 x double> poison, double undef, i32 3
+
+  %v8f64_a = insertelement <8 x double> poison, double undef, i32 %arg
+  %v8f64_0 = insertelement <8 x double> poison, double undef, i32 0
+  %v8f64_3 = insertelement <8 x double> poison, double undef, i32 3
+  %v8f64_4 = insertelement <8 x double> poison, double undef, i32 4
+  %v8f64_7 = insertelement <8 x double> poison, double undef, i32 7
+
+  ret i32 undef
+}
+
+define i32 @insert_float(i32 %arg) {
+; SSE2-LABEL: 'insert_float'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_a = insertelement <2 x float> poison, float undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32_0 = insertelement <2 x float> poison, float undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2f32_1 = insertelement <2 x float> poison, float undef, i32 1
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_a = insertelement <4 x float> poison, float undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32_0 = insertelement <4 x float> poison, float undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4f32_3 = insertelement <4 x float> poison, float undef, i32 3
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_a = insertelement <8 x float> poison, float undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_0 = insertelement <8 x float> poison, float undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8f32_3 = insertelement <8 x float> poison, float undef, i32 3
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_4 = insertelement <8 x float> poison, float undef, i32 4
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8f32_7 = insertelement <8 x float> poison, float undef, i32 7
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_a = insertelement <16 x float> poison, float undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_0 = insertelement <16 x float> poison, float undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v16f32_3 = insertelement <16 x float> poison, float undef, i32 3
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_8 = insertelement <16 x float> poison, float undef, i32 8
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v16f32_15 = insertelement <16 x float> poison, float undef, i32 15
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE3-LABEL: 'insert_float'
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_a = insertelement <2 x float> poison, float undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32_0 = insertelement <2 x float> poison, float undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2f32_1 = insertelement <2 x float> poison, float undef, i32 1
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_a = insertelement <4 x float> poison, float undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32_0 = insertelement <4 x float> poison, float undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4f32_3 = insertelement <4 x float> poison, float undef, i32 3
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_a = insertelement <8 x float> poison, float undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_0 = insertelement <8 x float> poison, float undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8f32_3 = insertelement <8 x float> poison, float undef, i32 3
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_4 = insertelement <8 x float> poison, float undef, i32 4
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8f32_7 = insertelement <8 x float> poison, float undef, i32 7
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_a = insertelement <16 x float> poison, float undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_0 = insertelement <16 x float> poison, float undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v16f32_3 = insertelement <16 x float> poison, float undef, i32 3
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_8 = insertelement <16 x float> poison, float undef, i32 8
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v16f32_15 = insertelement <16 x float> poison, float undef, i32 15
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSSE3-LABEL: 'insert_float'
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_a = insertelement <2 x float> poison, float undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32_0 = insertelement <2 x float> poison, float undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2f32_1 = insertelement <2 x float> poison, float undef, i32 1
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_a = insertelement <4 x float> poison, float undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32_0 = insertelement <4 x float> poison, float undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4f32_3 = insertelement <4 x float> poison, float undef, i32 3
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_a = insertelement <8 x float> poison, float undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_0 = insertelement <8 x float> poison, float undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8f32_3 = insertelement <8 x float> poison, float undef, i32 3
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_4 = insertelement <8 x float> poison, float undef, i32 4
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8f32_7 = insertelement <8 x float> poison, float undef, i32 7
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_a = insertelement <16 x float> poison, float undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_0 = insertelement <16 x float> poison, float undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v16f32_3 = insertelement <16 x float> poison, float undef, i32 3
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_8 = insertelement <16 x float> poison, float undef, i32 8
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v16f32_15 = insertelement <16 x float> poison, float undef, i32 15
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE4-LABEL: 'insert_float'
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_a = insertelement <2 x float> poison, float undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32_0 = insertelement <2 x float> poison, float undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_1 = insertelement <2 x float> poison, float undef, i32 1
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_a = insertelement <4 x float> poison, float undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32_0 = insertelement <4 x float> poison, float undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_3 = insertelement <4 x float> poison, float undef, i32 3
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_a = insertelement <8 x float> poison, float undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_0 = insertelement <8 x float> poison, float undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_3 = insertelement <8 x float> poison, float undef, i32 3
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_4 = insertelement <8 x float> poison, float undef, i32 4
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_7 = insertelement <8 x float> poison, float undef, i32 7
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_a = insertelement <16 x float> poison, float undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_0 = insertelement <16 x float> poison, float undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_3 = insertelement <16 x float> poison, float undef, i32 3
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_8 = insertelement <16 x float> poison, float undef, i32 8
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_15 = insertelement <16 x float> poison, float undef, i32 15
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX-LABEL: 'insert_float'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_a = insertelement <2 x float> poison, float undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32_0 = insertelement <2 x float> poison, float undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_1 = insertelement <2 x float> poison, float undef, i32 1
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_a = insertelement <4 x float> poison, float undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32_0 = insertelement <4 x float> poison, float undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_3 = insertelement <4 x float> poison, float undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_a = insertelement <8 x float> poison, float undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_0 = insertelement <8 x float> poison, float undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_3 = insertelement <8 x float> poison, float undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8f32_4 = insertelement <8 x float> poison, float undef, i32 4
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8f32_7 = insertelement <8 x float> poison, float undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_a = insertelement <16 x float> poison, float undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_0 = insertelement <16 x float> poison, float undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_3 = insertelement <16 x float> poison, float undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_8 = insertelement <16 x float> poison, float undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16f32_15 = insertelement <16 x float> poison, float undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX512-LABEL: 'insert_float'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_a = insertelement <2 x float> poison, float undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32_0 = insertelement <2 x float> poison, float undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_1 = insertelement <2 x float> poison, float undef, i32 1
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_a = insertelement <4 x float> poison, float undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32_0 = insertelement <4 x float> poison, float undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_3 = insertelement <4 x float> poison, float undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_a = insertelement <8 x float> poison, float undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_0 = insertelement <8 x float> poison, float undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_3 = insertelement <8 x float> poison, float undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8f32_4 = insertelement <8 x float> poison, float undef, i32 4
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8f32_7 = insertelement <8 x float> poison, float undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_a = insertelement <16 x float> poison, float undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_0 = insertelement <16 x float> poison, float undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_3 = insertelement <16 x float> poison, float undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v16f32_8 = insertelement <16 x float> poison, float undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16f32_15 = insertelement <16 x float> poison, float undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SLM-LABEL: 'insert_float'
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_a = insertelement <2 x float> poison, float undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32_0 = insertelement <2 x float> poison, float undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_1 = insertelement <2 x float> poison, float undef, i32 1
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_a = insertelement <4 x float> poison, float undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32_0 = insertelement <4 x float> poison, float undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_3 = insertelement <4 x float> poison, float undef, i32 3
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_a = insertelement <8 x float> poison, float undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_0 = insertelement <8 x float> poison, float undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_3 = insertelement <8 x float> poison, float undef, i32 3
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_4 = insertelement <8 x float> poison, float undef, i32 4
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_7 = insertelement <8 x float> poison, float undef, i32 7
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_a = insertelement <16 x float> poison, float undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_0 = insertelement <16 x float> poison, float undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_3 = insertelement <16 x float> poison, float undef, i32 3
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_8 = insertelement <16 x float> poison, float undef, i32 8
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_15 = insertelement <16 x float> poison, float undef, i32 15
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; GLM-LABEL: 'insert_float'
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_a = insertelement <2 x float> poison, float undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v2f32_0 = insertelement <2 x float> poison, float undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2f32_1 = insertelement <2 x float> poison, float undef, i32 1
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_a = insertelement <4 x float> poison, float undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v4f32_0 = insertelement <4 x float> poison, float undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4f32_3 = insertelement <4 x float> poison, float undef, i32 3
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_a = insertelement <8 x float> poison, float undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_0 = insertelement <8 x float> poison, float undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_3 = insertelement <8 x float> poison, float undef, i32 3
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v8f32_4 = insertelement <8 x float> poison, float undef, i32 4
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8f32_7 = insertelement <8 x float> poison, float undef, i32 7
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_a = insertelement <16 x float> poison, float undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_0 = insertelement <16 x float> poison, float undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_3 = insertelement <16 x float> poison, float undef, i32 3
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %v16f32_8 = insertelement <16 x float> poison, float undef, i32 8
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16f32_15 = insertelement <16 x float> poison, float undef, i32 15
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+  %v2f32_a = insertelement <2 x float> poison, float undef, i32 %arg
+  %v2f32_0 = insertelement <2 x float> poison, float undef, i32 0
+  %v2f32_1 = insertelement <2 x float> poison, float undef, i32 1
+
+  %v4f32_a = insertelement <4 x float> poison, float undef, i32 %arg
+  %v4f32_0 = insertelement <4 x float> poison, float undef, i32 0
+  %v4f32_3 = insertelement <4 x float> poison, float undef, i32 3
+
+  %v8f32_a = insertelement <8 x float> poison, float undef, i32 %arg
+  %v8f32_0 = insertelement <8 x float> poison, float undef, i32 0
+  %v8f32_3 = insertelement <8 x float> poison, float undef, i32 3
+  %v8f32_4 = insertelement <8 x float> poison, float undef, i32 4
+  %v8f32_7 = insertelement <8 x float> poison, float undef, i32 7
+
+  %v16f32_a  = insertelement <16 x float> poison, float undef, i32 %arg
+  %v16f32_0  = insertelement <16 x float> poison, float undef, i32 0
+  %v16f32_3  = insertelement <16 x float> poison, float undef, i32 3
+  %v16f32_8  = insertelement <16 x float> poison, float undef, i32 8
+  %v16f32_15 = insertelement <16 x float> poison, float undef, i32 15
+
+  ret i32 undef
+}
+
+define i32 @insert_i64(i32 %arg) {
+; SSE2-LABEL: 'insert_i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_a = insertelement <2 x i64> poison, i64 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i64_0 = insertelement <2 x i64> poison, i64 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i64_1 = insertelement <2 x i64> poison, i64 undef, i32 1
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_a = insertelement <4 x i64> poison, i64 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i64_0 = insertelement <4 x i64> poison, i64 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i64_3 = insertelement <4 x i64> poison, i64 undef, i32 3
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_a = insertelement <8 x i64> poison, i64 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_0 = insertelement <8 x i64> poison, i64 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_3 = insertelement <8 x i64> poison, i64 undef, i32 3
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_4 = insertelement <8 x i64> poison, i64 undef, i32 4
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_7 = insertelement <8 x i64> poison, i64 undef, i32 7
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE3-LABEL: 'insert_i64'
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_a = insertelement <2 x i64> poison, i64 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i64_0 = insertelement <2 x i64> poison, i64 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i64_1 = insertelement <2 x i64> poison, i64 undef, i32 1
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_a = insertelement <4 x i64> poison, i64 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i64_0 = insertelement <4 x i64> poison, i64 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i64_3 = insertelement <4 x i64> poison, i64 undef, i32 3
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_a = insertelement <8 x i64> poison, i64 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_0 = insertelement <8 x i64> poison, i64 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_3 = insertelement <8 x i64> poison, i64 undef, i32 3
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_4 = insertelement <8 x i64> poison, i64 undef, i32 4
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_7 = insertelement <8 x i64> poison, i64 undef, i32 7
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSSE3-LABEL: 'insert_i64'
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_a = insertelement <2 x i64> poison, i64 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i64_0 = insertelement <2 x i64> poison, i64 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i64_1 = insertelement <2 x i64> poison, i64 undef, i32 1
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_a = insertelement <4 x i64> poison, i64 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i64_0 = insertelement <4 x i64> poison, i64 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i64_3 = insertelement <4 x i64> poison, i64 undef, i32 3
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_a = insertelement <8 x i64> poison, i64 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_0 = insertelement <8 x i64> poison, i64 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_3 = insertelement <8 x i64> poison, i64 undef, i32 3
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_4 = insertelement <8 x i64> poison, i64 undef, i32 4
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v8i64_7 = insertelement <8 x i64> poison, i64 undef, i32 7
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE4-LABEL: 'insert_i64'
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_a = insertelement <2 x i64> poison, i64 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_0 = insertelement <2 x i64> poison, i64 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_1 = insertelement <2 x i64> poison, i64 undef, i32 1
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_a = insertelement <4 x i64> poison, i64 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_0 = insertelement <4 x i64> poison, i64 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_3 = insertelement <4 x i64> poison, i64 undef, i32 3
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_a = insertelement <8 x i64> poison, i64 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_0 = insertelement <8 x i64> poison, i64 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_3 = insertelement <8 x i64> poison, i64 undef, i32 3
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_4 = insertelement <8 x i64> poison, i64 undef, i32 4
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_7 = insertelement <8 x i64> poison, i64 undef, i32 7
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX-LABEL: 'insert_i64'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_a = insertelement <2 x i64> poison, i64 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_0 = insertelement <2 x i64> poison, i64 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_1 = insertelement <2 x i64> poison, i64 undef, i32 1
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_a = insertelement <4 x i64> poison, i64 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_0 = insertelement <4 x i64> poison, i64 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i64_3 = insertelement <4 x i64> poison, i64 undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_a = insertelement <8 x i64> poison, i64 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_0 = insertelement <8 x i64> poison, i64 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i64_3 = insertelement <8 x i64> poison, i64 undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_4 = insertelement <8 x i64> poison, i64 undef, i32 4
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i64_7 = insertelement <8 x i64> poison, i64 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX512-LABEL: 'insert_i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_a = insertelement <2 x i64> poison, i64 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_0 = insertelement <2 x i64> poison, i64 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_1 = insertelement <2 x i64> poison, i64 undef, i32 1
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_a = insertelement <4 x i64> poison, i64 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_0 = insertelement <4 x i64> poison, i64 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i64_3 = insertelement <4 x i64> poison, i64 undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_a = insertelement <8 x i64> poison, i64 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_0 = insertelement <8 x i64> poison, i64 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i64_3 = insertelement <8 x i64> poison, i64 undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i64_4 = insertelement <8 x i64> poison, i64 undef, i32 4
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i64_7 = insertelement <8 x i64> poison, i64 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SLM-LABEL: 'insert_i64'
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_a = insertelement <2 x i64> poison, i64 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_0 = insertelement <2 x i64> poison, i64 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_1 = insertelement <2 x i64> poison, i64 undef, i32 1
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_a = insertelement <4 x i64> poison, i64 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_0 = insertelement <4 x i64> poison, i64 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_3 = insertelement <4 x i64> poison, i64 undef, i32 3
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_a = insertelement <8 x i64> poison, i64 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_0 = insertelement <8 x i64> poison, i64 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_3 = insertelement <8 x i64> poison, i64 undef, i32 3
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_4 = insertelement <8 x i64> poison, i64 undef, i32 4
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_7 = insertelement <8 x i64> poison, i64 undef, i32 7
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; GLM-LABEL: 'insert_i64'
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_a = insertelement <2 x i64> poison, i64 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_0 = insertelement <2 x i64> poison, i64 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i64_1 = insertelement <2 x i64> poison, i64 undef, i32 1
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_a = insertelement <4 x i64> poison, i64 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_0 = insertelement <4 x i64> poison, i64 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i64_3 = insertelement <4 x i64> poison, i64 undef, i32 3
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_a = insertelement <8 x i64> poison, i64 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_0 = insertelement <8 x i64> poison, i64 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_3 = insertelement <8 x i64> poison, i64 undef, i32 3
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_4 = insertelement <8 x i64> poison, i64 undef, i32 4
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i64_7 = insertelement <8 x i64> poison, i64 undef, i32 7
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+  %v2i64_a = insertelement <2 x i64> poison, i64 undef, i32 %arg
+  %v2i64_0 = insertelement <2 x i64> poison, i64 undef, i32 0
+  %v2i64_1 = insertelement <2 x i64> poison, i64 undef, i32 1
+
+  %v4i64_a = insertelement <4 x i64> poison, i64 undef, i32 %arg
+  %v4i64_0 = insertelement <4 x i64> poison, i64 undef, i32 0
+  %v4i64_3 = insertelement <4 x i64> poison, i64 undef, i32 3
+
+  %v8i64_a = insertelement <8 x i64> poison, i64 undef, i32 %arg
+  %v8i64_0 = insertelement <8 x i64> poison, i64 undef, i32 0
+  %v8i64_3 = insertelement <8 x i64> poison, i64 undef, i32 3
+  %v8i64_4 = insertelement <8 x i64> poison, i64 undef, i32 4
+  %v8i64_7 = insertelement <8 x i64> poison, i64 undef, i32 7
+
+  ret i32 undef
+}
+
+define i32 @insert_i32(i32 %arg) {
+; SSE2-LABEL: 'insert_i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE3-LABEL: 'insert_i32'
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSSE3-LABEL: 'insert_i32'
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE4-LABEL: 'insert_i32'
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX-LABEL: 'insert_i32'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX512-LABEL: 'insert_i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SLM-LABEL: 'insert_i32'
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; GLM-LABEL: 'insert_i32'
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_a = insertelement <16 x i32> poison, i32 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_0 = insertelement <16 x i32> poison, i32 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_3 = insertelement <16 x i32> poison, i32 undef, i32 3
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_8 = insertelement <16 x i32> poison, i32 undef, i32 8
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+  %v2i32_a = insertelement <2 x i32> poison, i32 undef, i32 %arg
+  %v2i32_0 = insertelement <2 x i32> poison, i32 undef, i32 0
+  %v2i32_1 = insertelement <2 x i32> poison, i32 undef, i32 1
+
+  %v4i32_a = insertelement <4 x i32> poison, i32 undef, i32 %arg
+  %v4i32_0 = insertelement <4 x i32> poison, i32 undef, i32 0
+  %v4i32_3 = insertelement <4 x i32> poison, i32 undef, i32 3
+
+  %v8i32_a = insertelement <8 x i32> poison, i32 undef, i32 %arg
+  %v8i32_0 = insertelement <8 x i32> poison, i32 undef, i32 0
+  %v8i32_3 = insertelement <8 x i32> poison, i32 undef, i32 3
+  %v8i32_4 = insertelement <8 x i32> poison, i32 undef, i32 4
+  %v8i32_7 = insertelement <8 x i32> poison, i32 undef, i32 7
+
+  %v16i32_a  = insertelement <16 x i32> poison, i32 undef, i32 %arg
+  %v16i32_0  = insertelement <16 x i32> poison, i32 undef, i32 0
+  %v16i32_3  = insertelement <16 x i32> poison, i32 undef, i32 3
+  %v16i32_8  = insertelement <16 x i32> poison, i32 undef, i32 8
+  %v16i32_15 = insertelement <16 x i32> poison, i32 undef, i32 15
+
+  ret i32 undef
+}
+
+define i32 @insert_i16(i32 %arg) {
+; SSE-LABEL: 'insert_i16'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16_a = insertelement <2 x i16> poison, i16 undef, i32 %arg
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16_0 = insertelement <2 x i16> poison, i16 undef, i32 0
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16_1 = insertelement <2 x i16> poison, i16 undef, i32 1
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i16_a = insertelement <4 x i16> poison, i16 undef, i32 %arg
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i16_0 = insertelement <4 x i16> poison, i16 undef, i32 0
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i16_3 = insertelement <4 x i16> poison, i16 undef, i32 3
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i16_a = insertelement <8 x i16> poison, i16 undef, i32 %arg
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i16_0 = insertelement <8 x i16> poison, i16 undef, i32 0
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i16_7 = insertelement <8 x i16> poison, i16 undef, i32 7
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_a = insertelement <16 x i16> poison, i16 undef, i32 %arg
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_0 = insertelement <16 x i16> poison, i16 undef, i32 0
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_7 = insertelement <16 x i16> poison, i16 undef, i32 7
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_8 = insertelement <16 x i16> poison, i16 undef, i32 8
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_15 = insertelement <16 x i16> poison, i16 undef, i32 15
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_a = insertelement <32 x i16> poison, i16 undef, i32 %arg
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_0 = insertelement <32 x i16> poison, i16 undef, i32 0
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_7 = insertelement <32 x i16> poison, i16 undef, i32 7
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_8 = insertelement <32 x i16> poison, i16 undef, i32 8
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_15 = insertelement <32 x i16> poison, i16 undef, i32 15
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_16 = insertelement <32 x i16> poison, i16 undef, i32 16
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_24 = insertelement <32 x i16> poison, i16 undef, i32 24
+; SSE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_31 = insertelement <32 x i16> poison, i16 undef, i32 31
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX-LABEL: 'insert_i16'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16_a = insertelement <2 x i16> poison, i16 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16_0 = insertelement <2 x i16> poison, i16 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16_1 = insertelement <2 x i16> poison, i16 undef, i32 1
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i16_a = insertelement <4 x i16> poison, i16 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i16_0 = insertelement <4 x i16> poison, i16 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i16_3 = insertelement <4 x i16> poison, i16 undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i16_a = insertelement <8 x i16> poison, i16 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i16_0 = insertelement <8 x i16> poison, i16 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i16_7 = insertelement <8 x i16> poison, i16 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_a = insertelement <16 x i16> poison, i16 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_0 = insertelement <16 x i16> poison, i16 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_7 = insertelement <16 x i16> poison, i16 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i16_8 = insertelement <16 x i16> poison, i16 undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i16_15 = insertelement <16 x i16> poison, i16 undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_a = insertelement <32 x i16> poison, i16 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_0 = insertelement <32 x i16> poison, i16 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_7 = insertelement <32 x i16> poison, i16 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i16_8 = insertelement <32 x i16> poison, i16 undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i16_15 = insertelement <32 x i16> poison, i16 undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_16 = insertelement <32 x i16> poison, i16 undef, i32 16
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i16_24 = insertelement <32 x i16> poison, i16 undef, i32 24
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i16_31 = insertelement <32 x i16> poison, i16 undef, i32 31
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX512-LABEL: 'insert_i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16_a = insertelement <2 x i16> poison, i16 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16_0 = insertelement <2 x i16> poison, i16 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16_1 = insertelement <2 x i16> poison, i16 undef, i32 1
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i16_a = insertelement <4 x i16> poison, i16 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i16_0 = insertelement <4 x i16> poison, i16 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i16_3 = insertelement <4 x i16> poison, i16 undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i16_a = insertelement <8 x i16> poison, i16 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i16_0 = insertelement <8 x i16> poison, i16 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i16_7 = insertelement <8 x i16> poison, i16 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_a = insertelement <16 x i16> poison, i16 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_0 = insertelement <16 x i16> poison, i16 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i16_7 = insertelement <16 x i16> poison, i16 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i16_8 = insertelement <16 x i16> poison, i16 undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v16i16_15 = insertelement <16 x i16> poison, i16 undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_a = insertelement <32 x i16> poison, i16 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_0 = insertelement <32 x i16> poison, i16 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i16_7 = insertelement <32 x i16> poison, i16 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i16_8 = insertelement <32 x i16> poison, i16 undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i16_15 = insertelement <32 x i16> poison, i16 undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i16_16 = insertelement <32 x i16> poison, i16 undef, i32 16
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i16_24 = insertelement <32 x i16> poison, i16 undef, i32 24
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i16_31 = insertelement <32 x i16> poison, i16 undef, i32 31
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+  %v2i16_a = insertelement <2 x i16> poison, i16 undef, i32 %arg
+  %v2i16_0 = insertelement <2 x i16> poison, i16 undef, i32 0
+  %v2i16_1 = insertelement <2 x i16> poison, i16 undef, i32 1
+
+  %v4i16_a = insertelement <4 x i16> poison, i16 undef, i32 %arg
+  %v4i16_0 = insertelement <4 x i16> poison, i16 undef, i32 0
+  %v4i16_3 = insertelement <4 x i16> poison, i16 undef, i32 3
+
+  %v8i16_a = insertelement <8 x i16> poison, i16 undef, i32 %arg
+  %v8i16_0 = insertelement <8 x i16> poison, i16 undef, i32 0
+  %v8i16_7 = insertelement <8 x i16> poison, i16 undef, i32 7
+
+  %v16i16_a  = insertelement <16 x i16> poison, i16 undef, i32 %arg
+  %v16i16_0  = insertelement <16 x i16> poison, i16 undef, i32 0
+  %v16i16_7  = insertelement <16 x i16> poison, i16 undef, i32 7
+  %v16i16_8  = insertelement <16 x i16> poison, i16 undef, i32 8
+  %v16i16_15 = insertelement <16 x i16> poison, i16 undef, i32 15
+
+  %v32i16_a  = insertelement <32 x i16> poison, i16 undef, i32 %arg
+  %v32i16_0  = insertelement <32 x i16> poison, i16 undef, i32 0
+  %v32i16_7  = insertelement <32 x i16> poison, i16 undef, i32 7
+  %v32i16_8  = insertelement <32 x i16> poison, i16 undef, i32 8
+  %v32i16_15 = insertelement <32 x i16> poison, i16 undef, i32 15
+  %v32i16_16 = insertelement <32 x i16> poison, i16 undef, i32 16
+  %v32i16_24 = insertelement <32 x i16> poison, i16 undef, i32 24
+  %v32i16_31 = insertelement <32 x i16> poison, i16 undef, i32 31
+
+  ret i32 undef
+}
+
+define i32 @insert_i8(i32 %arg) {
+; SSE2-LABEL: 'insert_i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE3-LABEL: 'insert_i8'
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSSE3-LABEL: 'insert_i8'
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE4-LABEL: 'insert_i8'
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX-LABEL: 'insert_i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX512-LABEL: 'insert_i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SLM-LABEL: 'insert_i8'
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; GLM-LABEL: 'insert_i8'
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_a = insertelement <2 x i8> poison, i8 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_0 = insertelement <2 x i8> poison, i8 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i8_3 = insertelement <2 x i8> poison, i8 undef, i32 1
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_a = insertelement <4 x i8> poison, i8 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_0 = insertelement <4 x i8> poison, i8 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i8_3 = insertelement <4 x i8> poison, i8 undef, i32 3
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_a = insertelement <8 x i8> poison, i8 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_0 = insertelement <8 x i8> poison, i8 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i8_7 = insertelement <8 x i8> poison, i8 undef, i32 7
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_a = insertelement <16 x i8> poison, i8 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_0 = insertelement <16 x i8> poison, i8 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_8 = insertelement <16 x i8> poison, i8 undef, i32 8
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_a = insertelement <32 x i8> poison, i8 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_0 = insertelement <32 x i8> poison, i8 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_7 = insertelement <32 x i8> poison, i8 undef, i32 7
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_8 = insertelement <32 x i8> poison, i8 undef, i32 8
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_a = insertelement <64 x i8> poison, i8 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_0 = insertelement <64 x i8> poison, i8 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_7 = insertelement <64 x i8> poison, i8 undef, i32 7
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_8 = insertelement <64 x i8> poison, i8 undef, i32 8
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+  %v2i8_a   = insertelement <2 x i8> poison, i8 undef, i32 %arg
+  %v2i8_0   = insertelement <2 x i8> poison, i8 undef, i32 0
+  %v2i8_3   = insertelement <2 x i8> poison, i8 undef, i32 1
+
+  %v4i8_a   = insertelement <4 x i8> poison, i8 undef, i32 %arg
+  %v4i8_0   = insertelement <4 x i8> poison, i8 undef, i32 0
+  %v4i8_3   = insertelement <4 x i8> poison, i8 undef, i32 3
+
+  %v8i8_a   = insertelement <8 x i8> poison, i8 undef, i32 %arg
+  %v8i8_0   = insertelement <8 x i8> poison, i8 undef, i32 0
+  %v8i8_7   = insertelement <8 x i8> poison, i8 undef, i32 7
+
+  %v16i8_a  = insertelement <16 x i8> poison, i8 undef, i32 %arg
+  %v16i8_0  = insertelement <16 x i8> poison, i8 undef, i32 0
+  %v16i8_8  = insertelement <16 x i8> poison, i8 undef, i32 8
+  %v16i8_15 = insertelement <16 x i8> poison, i8 undef, i32 15
+
+  %v32i8_a  = insertelement <32 x i8> poison, i8 undef, i32 %arg
+  %v32i8_0  = insertelement <32 x i8> poison, i8 undef, i32 0
+  %v32i8_7  = insertelement <32 x i8> poison, i8 undef, i32 7
+  %v32i8_8  = insertelement <32 x i8> poison, i8 undef, i32 8
+  %v32i8_15 = insertelement <32 x i8> poison, i8 undef, i32 15
+  %v32i8_24 = insertelement <32 x i8> poison, i8 undef, i32 24
+  %v32i8_31 = insertelement <32 x i8> poison, i8 undef, i32 31
+
+  %v64i8_a  = insertelement <64 x i8> poison, i8 undef, i32 %arg
+  %v64i8_0  = insertelement <64 x i8> poison, i8 undef, i32 0
+  %v64i8_7  = insertelement <64 x i8> poison, i8 undef, i32 7
+  %v64i8_8  = insertelement <64 x i8> poison, i8 undef, i32 8
+  %v64i8_15 = insertelement <64 x i8> poison, i8 undef, i32 15
+  %v64i8_24 = insertelement <64 x i8> poison, i8 undef, i32 24
+  %v64i8_31 = insertelement <64 x i8> poison, i8 undef, i32 31
+  %v64i8_32 = insertelement <64 x i8> poison, i8 undef, i32 32
+  %v64i8_48 = insertelement <64 x i8> poison, i8 undef, i32 48
+  %v64i8_63 = insertelement <64 x i8> poison, i8 undef, i32 63
+
+  ret i32 undef
+}
+
+define i32 @insert_i1(i32 %arg) {
+; SSE2-LABEL: 'insert_i1'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_a = insertelement <2 x i1> poison, i1 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i1_0 = insertelement <2 x i1> poison, i1 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i1_1 = insertelement <2 x i1> poison, i1 undef, i32 1
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_a = insertelement <4 x i1> poison, i1 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i1_0 = insertelement <4 x i1> poison, i1 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i1_2 = insertelement <4 x i1> poison, i1 undef, i32 2
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_a = insertelement <8 x i1> poison, i1 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_0 = insertelement <8 x i1> poison, i1 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_4 = insertelement <8 x i1> poison, i1 undef, i32 4
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_a = insertelement <16 x i1> poison, i1 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i1_0 = insertelement <16 x i1> poison, i1 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i1_8 = insertelement <16 x i1> poison, i1 undef, i32 8
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i1_15 = insertelement <16 x i1> poison, i1 undef, i32 15
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_a = insertelement <32 x i1> poison, i1 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_0 = insertelement <32 x i1> poison, i1 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_7 = insertelement <32 x i1> poison, i1 undef, i32 7
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_8 = insertelement <32 x i1> poison, i1 undef, i32 8
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_15 = insertelement <32 x i1> poison, i1 undef, i32 15
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_24 = insertelement <32 x i1> poison, i1 undef, i32 24
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_31 = insertelement <32 x i1> poison, i1 undef, i32 31
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_a = insertelement <64 x i1> poison, i1 undef, i32 %arg
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_0 = insertelement <64 x i1> poison, i1 undef, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_7 = insertelement <64 x i1> poison, i1 undef, i32 7
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_8 = insertelement <64 x i1> poison, i1 undef, i32 8
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_15 = insertelement <64 x i1> poison, i1 undef, i32 15
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_24 = insertelement <64 x i1> poison, i1 undef, i32 24
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_31 = insertelement <64 x i1> poison, i1 undef, i32 31
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_32 = insertelement <64 x i1> poison, i1 undef, i32 32
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_48 = insertelement <64 x i1> poison, i1 undef, i32 48
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_63 = insertelement <64 x i1> poison, i1 undef, i32 63
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE3-LABEL: 'insert_i1'
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_a = insertelement <2 x i1> poison, i1 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i1_0 = insertelement <2 x i1> poison, i1 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i1_1 = insertelement <2 x i1> poison, i1 undef, i32 1
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_a = insertelement <4 x i1> poison, i1 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i1_0 = insertelement <4 x i1> poison, i1 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i1_2 = insertelement <4 x i1> poison, i1 undef, i32 2
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_a = insertelement <8 x i1> poison, i1 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_0 = insertelement <8 x i1> poison, i1 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_4 = insertelement <8 x i1> poison, i1 undef, i32 4
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_a = insertelement <16 x i1> poison, i1 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i1_0 = insertelement <16 x i1> poison, i1 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i1_8 = insertelement <16 x i1> poison, i1 undef, i32 8
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v16i1_15 = insertelement <16 x i1> poison, i1 undef, i32 15
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_a = insertelement <32 x i1> poison, i1 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_0 = insertelement <32 x i1> poison, i1 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_7 = insertelement <32 x i1> poison, i1 undef, i32 7
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_8 = insertelement <32 x i1> poison, i1 undef, i32 8
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_15 = insertelement <32 x i1> poison, i1 undef, i32 15
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_24 = insertelement <32 x i1> poison, i1 undef, i32 24
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v32i1_31 = insertelement <32 x i1> poison, i1 undef, i32 31
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_a = insertelement <64 x i1> poison, i1 undef, i32 %arg
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_0 = insertelement <64 x i1> poison, i1 undef, i32 0
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_7 = insertelement <64 x i1> poison, i1 undef, i32 7
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_8 = insertelement <64 x i1> poison, i1 undef, i32 8
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_15 = insertelement <64 x i1> poison, i1 undef, i32 15
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_24 = insertelement <64 x i1> poison, i1 undef, i32 24
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_31 = insertelement <64 x i1> poison, i1 undef, i32 31
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_32 = insertelement <64 x i1> poison, i1 undef, i32 32
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_48 = insertelement <64 x i1> poison, i1 undef, i32 48
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %v64i1_63 = insertelement <64 x i1> poison, i1 undef, i32 63
+; SSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSSE3-LABEL: 'insert_i1'
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_a = insertelement <2 x i1> poison, i1 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i1_0 = insertelement <2 x i1> poison, i1 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i1_1 = insertelement <2 x i1> poison, i1 undef, i32 1
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_a = insertelement <4 x i1> poison, i1 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i1_0 = insertelement <4 x i1> poison, i1 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v4i1_2 = insertelement <4 x i1> poison, i1 undef, i32 2
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_a = insertelement <8 x i1> poison, i1 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_0 = insertelement <8 x i1> poison, i1 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_4 = insertelement <8 x i1> poison, i1 undef, i32 4
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_a = insertelement <16 x i1> poison, i1 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v16i1_0 = insertelement <16 x i1> poison, i1 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v16i1_8 = insertelement <16 x i1> poison, i1 undef, i32 8
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v16i1_15 = insertelement <16 x i1> poison, i1 undef, i32 15
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_a = insertelement <32 x i1> poison, i1 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i1_0 = insertelement <32 x i1> poison, i1 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i1_7 = insertelement <32 x i1> poison, i1 undef, i32 7
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i1_8 = insertelement <32 x i1> poison, i1 undef, i32 8
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i1_15 = insertelement <32 x i1> poison, i1 undef, i32 15
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i1_24 = insertelement <32 x i1> poison, i1 undef, i32 24
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v32i1_31 = insertelement <32 x i1> poison, i1 undef, i32 31
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_a = insertelement <64 x i1> poison, i1 undef, i32 %arg
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i1_0 = insertelement <64 x i1> poison, i1 undef, i32 0
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i1_7 = insertelement <64 x i1> poison, i1 undef, i32 7
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i1_8 = insertelement <64 x i1> poison, i1 undef, i32 8
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i1_15 = insertelement <64 x i1> poison, i1 undef, i32 15
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i1_24 = insertelement <64 x i1> poison, i1 undef, i32 24
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i1_31 = insertelement <64 x i1> poison, i1 undef, i32 31
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i1_32 = insertelement <64 x i1> poison, i1 undef, i32 32
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i1_48 = insertelement <64 x i1> poison, i1 undef, i32 48
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v64i1_63 = insertelement <64 x i1> poison, i1 undef, i32 63
+; SSSE3-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SSE4-LABEL: 'insert_i1'
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_a = insertelement <2 x i1> poison, i1 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_0 = insertelement <2 x i1> poison, i1 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_1 = insertelement <2 x i1> poison, i1 undef, i32 1
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_a = insertelement <4 x i1> poison, i1 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_0 = insertelement <4 x i1> poison, i1 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_2 = insertelement <4 x i1> poison, i1 undef, i32 2
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_a = insertelement <8 x i1> poison, i1 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_0 = insertelement <8 x i1> poison, i1 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_4 = insertelement <8 x i1> poison, i1 undef, i32 4
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_a = insertelement <16 x i1> poison, i1 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_0 = insertelement <16 x i1> poison, i1 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_8 = insertelement <16 x i1> poison, i1 undef, i32 8
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_15 = insertelement <16 x i1> poison, i1 undef, i32 15
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_a = insertelement <32 x i1> poison, i1 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_0 = insertelement <32 x i1> poison, i1 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_7 = insertelement <32 x i1> poison, i1 undef, i32 7
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_8 = insertelement <32 x i1> poison, i1 undef, i32 8
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_15 = insertelement <32 x i1> poison, i1 undef, i32 15
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_24 = insertelement <32 x i1> poison, i1 undef, i32 24
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_31 = insertelement <32 x i1> poison, i1 undef, i32 31
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_a = insertelement <64 x i1> poison, i1 undef, i32 %arg
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_0 = insertelement <64 x i1> poison, i1 undef, i32 0
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_7 = insertelement <64 x i1> poison, i1 undef, i32 7
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_8 = insertelement <64 x i1> poison, i1 undef, i32 8
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_15 = insertelement <64 x i1> poison, i1 undef, i32 15
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_24 = insertelement <64 x i1> poison, i1 undef, i32 24
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_31 = insertelement <64 x i1> poison, i1 undef, i32 31
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_32 = insertelement <64 x i1> poison, i1 undef, i32 32
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_48 = insertelement <64 x i1> poison, i1 undef, i32 48
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_63 = insertelement <64 x i1> poison, i1 undef, i32 63
+; SSE4-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX-LABEL: 'insert_i1'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_a = insertelement <2 x i1> poison, i1 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_0 = insertelement <2 x i1> poison, i1 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_1 = insertelement <2 x i1> poison, i1 undef, i32 1
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_a = insertelement <4 x i1> poison, i1 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_0 = insertelement <4 x i1> poison, i1 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_2 = insertelement <4 x i1> poison, i1 undef, i32 2
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_a = insertelement <8 x i1> poison, i1 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_0 = insertelement <8 x i1> poison, i1 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_4 = insertelement <8 x i1> poison, i1 undef, i32 4
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_a = insertelement <16 x i1> poison, i1 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_0 = insertelement <16 x i1> poison, i1 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_8 = insertelement <16 x i1> poison, i1 undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_15 = insertelement <16 x i1> poison, i1 undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_a = insertelement <32 x i1> poison, i1 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_0 = insertelement <32 x i1> poison, i1 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_7 = insertelement <32 x i1> poison, i1 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_8 = insertelement <32 x i1> poison, i1 undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_15 = insertelement <32 x i1> poison, i1 undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i1_24 = insertelement <32 x i1> poison, i1 undef, i32 24
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v32i1_31 = insertelement <32 x i1> poison, i1 undef, i32 31
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_a = insertelement <64 x i1> poison, i1 undef, i32 %arg
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_0 = insertelement <64 x i1> poison, i1 undef, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_7 = insertelement <64 x i1> poison, i1 undef, i32 7
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_8 = insertelement <64 x i1> poison, i1 undef, i32 8
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_15 = insertelement <64 x i1> poison, i1 undef, i32 15
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i1_24 = insertelement <64 x i1> poison, i1 undef, i32 24
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i1_31 = insertelement <64 x i1> poison, i1 undef, i32 31
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_32 = insertelement <64 x i1> poison, i1 undef, i32 32
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i1_48 = insertelement <64 x i1> poison, i1 undef, i32 48
+; AVX-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v64i1_63 = insertelement <64 x i1> poison, i1 undef, i32 63
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; AVX512-LABEL: 'insert_i1'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_a = insertelement <2 x i1> poison, i1 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_0 = insertelement <2 x i1> poison, i1 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_1 = insertelement <2 x i1> poison, i1 undef, i32 1
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_a = insertelement <4 x i1> poison, i1 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_0 = insertelement <4 x i1> poison, i1 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_2 = insertelement <4 x i1> poison, i1 undef, i32 2
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_a = insertelement <8 x i1> poison, i1 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_0 = insertelement <8 x i1> poison, i1 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_4 = insertelement <8 x i1> poison, i1 undef, i32 4
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_a = insertelement <16 x i1> poison, i1 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_0 = insertelement <16 x i1> poison, i1 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_8 = insertelement <16 x i1> poison, i1 undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_15 = insertelement <16 x i1> poison, i1 undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_a = insertelement <32 x i1> poison, i1 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_0 = insertelement <32 x i1> poison, i1 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_7 = insertelement <32 x i1> poison, i1 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_8 = insertelement <32 x i1> poison, i1 undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_15 = insertelement <32 x i1> poison, i1 undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_24 = insertelement <32 x i1> poison, i1 undef, i32 24
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_31 = insertelement <32 x i1> poison, i1 undef, i32 31
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_a = insertelement <64 x i1> poison, i1 undef, i32 %arg
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_0 = insertelement <64 x i1> poison, i1 undef, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_7 = insertelement <64 x i1> poison, i1 undef, i32 7
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_8 = insertelement <64 x i1> poison, i1 undef, i32 8
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_15 = insertelement <64 x i1> poison, i1 undef, i32 15
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_24 = insertelement <64 x i1> poison, i1 undef, i32 24
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_31 = insertelement <64 x i1> poison, i1 undef, i32 31
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_32 = insertelement <64 x i1> poison, i1 undef, i32 32
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_48 = insertelement <64 x i1> poison, i1 undef, i32 48
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_63 = insertelement <64 x i1> poison, i1 undef, i32 63
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; SLM-LABEL: 'insert_i1'
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_a = insertelement <2 x i1> poison, i1 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_0 = insertelement <2 x i1> poison, i1 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_1 = insertelement <2 x i1> poison, i1 undef, i32 1
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_a = insertelement <4 x i1> poison, i1 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_0 = insertelement <4 x i1> poison, i1 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_2 = insertelement <4 x i1> poison, i1 undef, i32 2
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_a = insertelement <8 x i1> poison, i1 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_0 = insertelement <8 x i1> poison, i1 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_4 = insertelement <8 x i1> poison, i1 undef, i32 4
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_a = insertelement <16 x i1> poison, i1 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_0 = insertelement <16 x i1> poison, i1 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_8 = insertelement <16 x i1> poison, i1 undef, i32 8
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_15 = insertelement <16 x i1> poison, i1 undef, i32 15
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_a = insertelement <32 x i1> poison, i1 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_0 = insertelement <32 x i1> poison, i1 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_7 = insertelement <32 x i1> poison, i1 undef, i32 7
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_8 = insertelement <32 x i1> poison, i1 undef, i32 8
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_15 = insertelement <32 x i1> poison, i1 undef, i32 15
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_24 = insertelement <32 x i1> poison, i1 undef, i32 24
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_31 = insertelement <32 x i1> poison, i1 undef, i32 31
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_a = insertelement <64 x i1> poison, i1 undef, i32 %arg
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_0 = insertelement <64 x i1> poison, i1 undef, i32 0
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_7 = insertelement <64 x i1> poison, i1 undef, i32 7
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_8 = insertelement <64 x i1> poison, i1 undef, i32 8
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_15 = insertelement <64 x i1> poison, i1 undef, i32 15
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_24 = insertelement <64 x i1> poison, i1 undef, i32 24
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_31 = insertelement <64 x i1> poison, i1 undef, i32 31
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_32 = insertelement <64 x i1> poison, i1 undef, i32 32
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_48 = insertelement <64 x i1> poison, i1 undef, i32 48
+; SLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_63 = insertelement <64 x i1> poison, i1 undef, i32 63
+; SLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+; GLM-LABEL: 'insert_i1'
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_a = insertelement <2 x i1> poison, i1 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_0 = insertelement <2 x i1> poison, i1 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i1_1 = insertelement <2 x i1> poison, i1 undef, i32 1
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_a = insertelement <4 x i1> poison, i1 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_0 = insertelement <4 x i1> poison, i1 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v4i1_2 = insertelement <4 x i1> poison, i1 undef, i32 2
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_a = insertelement <8 x i1> poison, i1 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_0 = insertelement <8 x i1> poison, i1 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v8i1_4 = insertelement <8 x i1> poison, i1 undef, i32 4
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_a = insertelement <16 x i1> poison, i1 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_0 = insertelement <16 x i1> poison, i1 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_8 = insertelement <16 x i1> poison, i1 undef, i32 8
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v16i1_15 = insertelement <16 x i1> poison, i1 undef, i32 15
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_a = insertelement <32 x i1> poison, i1 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_0 = insertelement <32 x i1> poison, i1 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_7 = insertelement <32 x i1> poison, i1 undef, i32 7
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_8 = insertelement <32 x i1> poison, i1 undef, i32 8
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_15 = insertelement <32 x i1> poison, i1 undef, i32 15
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_24 = insertelement <32 x i1> poison, i1 undef, i32 24
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v32i1_31 = insertelement <32 x i1> poison, i1 undef, i32 31
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_a = insertelement <64 x i1> poison, i1 undef, i32 %arg
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_0 = insertelement <64 x i1> poison, i1 undef, i32 0
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_7 = insertelement <64 x i1> poison, i1 undef, i32 7
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_8 = insertelement <64 x i1> poison, i1 undef, i32 8
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_15 = insertelement <64 x i1> poison, i1 undef, i32 15
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_24 = insertelement <64 x i1> poison, i1 undef, i32 24
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_31 = insertelement <64 x i1> poison, i1 undef, i32 31
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_32 = insertelement <64 x i1> poison, i1 undef, i32 32
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_48 = insertelement <64 x i1> poison, i1 undef, i32 48
+; GLM-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v64i1_63 = insertelement <64 x i1> poison, i1 undef, i32 63
+; GLM-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret i32 undef
+;
+  %v2i1_a  = insertelement <2 x i1> poison, i1 undef, i32 %arg
+  %v2i1_0  = insertelement <2 x i1> poison, i1 undef, i32 0
+  %v2i1_1  = insertelement <2 x i1> poison, i1 undef, i32 1
+
+  %v4i1_a  = insertelement <4 x i1> poison, i1 undef, i32 %arg
+  %v4i1_0  = insertelement <4 x i1> poison, i1 undef, i32 0
+  %v4i1_2  = insertelement <4 x i1> poison, i1 undef, i32 2
+
+  %v8i1_a  = insertelement <8 x i1> poison, i1 undef, i32 %arg
+  %v8i1_0  = insertelement <8 x i1> poison, i1 undef, i32 0
+  %v8i1_4  = insertelement <8 x i1> poison, i1 undef, i32 4
+
+  %v16i1_a  = insertelement <16 x i1> poison, i1 undef, i32 %arg
+  %v16i1_0  = insertelement <16 x i1> poison, i1 undef, i32 0
+  %v16i1_8  = insertelement <16 x i1> poison, i1 undef, i32 8
+  %v16i1_15 = insertelement <16 x i1> poison, i1 undef, i32 15
+
+  %v32i1_a  = insertelement <32 x i1> poison, i1 undef, i32 %arg
+  %v32i1_0  = insertelement <32 x i1> poison, i1 undef, i32 0
+  %v32i1_7  = insertelement <32 x i1> poison, i1 undef, i32 7
+  %v32i1_8  = insertelement <32 x i1> poison, i1 undef, i32 8
+  %v32i1_15 = insertelement <32 x i1> poison, i1 undef, i32 15
+  %v32i1_24 = insertelement <32 x i1> poison, i1 undef, i32 24
+  %v32i1_31 = insertelement <32 x i1> poison, i1 undef, i32 31
+
+  %v64i1_a  = insertelement <64 x i1> poison, i1 undef, i32 %arg
+  %v64i1_0  = insertelement <64 x i1> poison, i1 undef, i32 0
+  %v64i1_7  = insertelement <64 x i1> poison, i1 undef, i32 7
+  %v64i1_8  = insertelement <64 x i1> poison, i1 undef, i32 8
+  %v64i1_15 = insertelement <64 x i1> poison, i1 undef, i32 15
+  %v64i1_24 = insertelement <64 x i1> poison, i1 undef, i32 24
+  %v64i1_31 = insertelement <64 x i1> poison, i1 undef, i32 31
+  %v64i1_32 = insertelement <64 x i1> poison, i1 undef, i32 32
+  %v64i1_48 = insertelement <64 x i1> poison, i1 undef, i32 48
+  %v64i1_63 = insertelement <64 x i1> poison, i1 undef, i32 63
+
+  ret i32 undef
+}
diff --git a/llvm/test/Analysis/CostModel/X86/vector_gep-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/vector_gep-inseltpoison.ll
new file mode 100644
index 0000000000000..8e8d6cb9c25a2
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/vector_gep-inseltpoison.ll
@@ -0,0 +1,17 @@
+; RUN: opt < %s  -cost-model -analyze -mtriple=x86_64-linux-unknown-unknown -mattr=+avx512f | FileCheck %s
+
+%struct.S = type { [1000 x i32] }
+
+
+declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
+
+define <4 x i32> @foov(<4 x %struct.S*> %s, i64 %base){
+  %temp = insertelement <4 x i64> poison, i64 %base, i32 0
+  %vector = shufflevector <4 x i64> %temp, <4 x i64> undef, <4 x i32> zeroinitializer
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds %struct.S
+  %B = getelementptr inbounds %struct.S, <4 x %struct.S*> %s, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer
+;CHECK: cost of 0 for instruction: {{.*}} getelementptr inbounds [1000 x i32]
+  %arrayidx = getelementptr inbounds [1000 x i32], <4 x [1000 x i32]*> %B, <4 x i64> zeroinitializer, <4 x i64> %vector
+  %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %arrayidx, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+  ret <4 x i32> %res
+}
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
new file mode 100644
index 0000000000000..47a36874965da
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/vshift-ashr-cost-inseltpoison.ll
@@ -0,0 +1,1843 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+xop,+avx | FileCheck %s --check-prefixes=CHECK,XOP,XOPAVX1
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+xop,+avx2 | FileCheck %s --check-prefixes=CHECK,XOP,XOPAVX2
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512BW
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512VL
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512BWVL
+;
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=slm | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=goldmont | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=btver2 | FileCheck %s --check-prefixes=CHECK,AVX,BTVER2
+
+; Verify the cost of vector arithmetic shift right instructions.
+
+;
+; Variable Shifts
+;
+
+define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; SSE-LABEL: 'var_shift_v2i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <2 x i64> %a, %b
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX1-LABEL: 'var_shift_v2i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <2 x i64> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX2-LABEL: 'var_shift_v2i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <2 x i64> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOP-LABEL: 'var_shift_v2i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <2 x i64> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'var_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <2 x i64> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; BTVER2-LABEL: 'var_shift_v2i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <2 x i64> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %shift = ashr <2 x i64> %a, %b
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
+; SSE-LABEL: 'var_shift_v4i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <4 x i64> %a, %b
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'var_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = ashr <4 x i64> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'var_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <4 x i64> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOP-LABEL: 'var_shift_v4i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <4 x i64> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'var_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i64> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'var_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = ashr <4 x i64> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %shift = ashr <4 x i64> %a, %b
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @var_shift_v8i64(<8 x i64> %a, <8 x i64> %b) {
+; SSE-LABEL: 'var_shift_v8i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <8 x i64> %a, %b
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'var_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = ashr <8 x i64> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'var_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <8 x i64> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOP-LABEL: 'var_shift_v8i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <8 x i64> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'var_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i64> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'var_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = ashr <8 x i64> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %shift = ashr <8 x i64> %a, %b
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; SSE2-LABEL: 'var_shift_v4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = ashr <4 x i32> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; SSE42-LABEL: 'var_shift_v4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <4 x i32> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX1-LABEL: 'var_shift_v4i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <4 x i32> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX2-LABEL: 'var_shift_v4i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v4i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <4 x i32> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v4i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX512-LABEL: 'var_shift_v4i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; BTVER2-LABEL: 'var_shift_v4i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <4 x i32> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %shift = ashr <4 x i32> %a, %b
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; SSE2-LABEL: 'var_shift_v8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %shift = ashr <8 x i32> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; SSE42-LABEL: 'var_shift_v8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <8 x i32> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'var_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = ashr <8 x i32> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'var_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <8 x i32> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'var_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'var_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = ashr <8 x i32> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %shift = ashr <8 x i32> %a, %b
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @var_shift_v16i32(<16 x i32> %a, <16 x i32> %b) {
+; SSE2-LABEL: 'var_shift_v16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %shift = ashr <16 x i32> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; SSE42-LABEL: 'var_shift_v16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <16 x i32> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'var_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = ashr <16 x i32> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'var_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i32> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <16 x i32> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i32> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'var_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i32> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'var_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = ashr <16 x i32> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %shift = ashr <16 x i32> %a, %b
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; SSE2-LABEL: 'var_shift_v8i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %shift = ashr <8 x i16> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; SSE42-LABEL: 'var_shift_v8i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = ashr <8 x i16> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX-LABEL: 'var_shift_v8i16'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = ashr <8 x i16> %a, %b
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; XOP-LABEL: 'var_shift_v8i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <8 x i16> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512F-LABEL: 'var_shift_v8i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = ashr <8 x i16> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v8i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v8i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = ashr <8 x i16> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v8i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %shift = ashr <8 x i16> %a, %b
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
+; SSE2-LABEL: 'var_shift_v16i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %shift = ashr <16 x i16> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; SSE42-LABEL: 'var_shift_v16i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %shift = ashr <16 x i16> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'var_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = ashr <16 x i16> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'var_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <16 x i16> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOP-LABEL: 'var_shift_v16i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <16 x i16> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512F-LABEL: 'var_shift_v16i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <16 x i16> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v16i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v16i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <16 x i16> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v16i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'var_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = ashr <16 x i16> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %shift = ashr <16 x i16> %a, %b
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @var_shift_v32i16(<32 x i16> %a, <32 x i16> %b) {
+; SSE2-LABEL: 'var_shift_v32i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: %shift = ashr <32 x i16> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; SSE42-LABEL: 'var_shift_v32i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 56 for instruction: %shift = ashr <32 x i16> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'var_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = ashr <32 x i16> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'var_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <32 x i16> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOP-LABEL: 'var_shift_v32i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <32 x i16> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'var_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <32 x i16> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <32 x i16> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <32 x i16> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <32 x i16> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'var_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = ashr <32 x i16> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %shift = ashr <32 x i16> %a, %b
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; SSE2-LABEL: 'var_shift_v16i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 54 for instruction: %shift = ashr <16 x i8> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; SSE42-LABEL: 'var_shift_v16i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <16 x i8> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'var_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <16 x i8> %a, %b
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'var_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i8> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'var_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <16 x i8> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %shift = ashr <16 x i8> %a, %b
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
+; SSE2-LABEL: 'var_shift_v32i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 108 for instruction: %shift = ashr <32 x i8> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; SSE42-LABEL: 'var_shift_v32i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <32 x i8> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'var_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 50 for instruction: %shift = ashr <32 x i8> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'var_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <32 x i8> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOP-LABEL: 'var_shift_v32i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <32 x i8> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'var_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <32 x i8> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'var_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 50 for instruction: %shift = ashr <32 x i8> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %shift = ashr <32 x i8> %a, %b
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @var_shift_v64i8(<64 x i8> %a, <64 x i8> %b) {
+; SSE2-LABEL: 'var_shift_v64i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 216 for instruction: %shift = ashr <64 x i8> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; SSE42-LABEL: 'var_shift_v64i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %shift = ashr <64 x i8> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'var_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 100 for instruction: %shift = ashr <64 x i8> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'var_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <64 x i8> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOP-LABEL: 'var_shift_v64i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <64 x i8> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'var_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <64 x i8> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <64 x i8> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <64 x i8> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <64 x i8> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'var_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 100 for instruction: %shift = ashr <64 x i8> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %shift = ashr <64 x i8> %a, %b
+  ret <64 x i8> %shift
+}
+
+;
+; Uniform Variable Shifts
+;
+
+define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, i64 %b) {
+; SSE2-LABEL: 'splatvar_shift_v2i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <2 x i64> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v2i64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <2 x i64> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v2i64'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <2 x i64> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v2i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <2 x i64> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <2 x i64> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+  %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+  %shift = ashr <2 x i64> %a, %splat
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, i64 %b) {
+; SSE2-LABEL: 'splatvar_shift_v4i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <4 x i64> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v4i64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <4 x i64> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <4 x i64> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <4 x i64> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v4i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <4 x i64> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v4i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <4 x i64> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i64> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <4 x i64> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+  %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+  %shift = ashr <4 x i64> %a, %splat
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @splatvar_shift_v8i64(<8 x i64> %a, i64 %b) {
+; SSE2-LABEL: 'splatvar_shift_v8i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = ashr <8 x i64> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v8i64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = ashr <8 x i64> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <8 x i64> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <8 x i64> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v8i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <8 x i64> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v8i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <8 x i64> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i64> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <8 x i64> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+  %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+  %shift = ashr <8 x i64> %a, %splat
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, i32 %b) {
+; SSE2-LABEL: 'splatvar_shift_v4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v4i32'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v4i32'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v4i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %shift = ashr <4 x i32> %a, %splat
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, i32 %b) {
+; SSE2-LABEL: 'splatvar_shift_v8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <8 x i32> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <8 x i32> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <8 x i32> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <8 x i32> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <8 x i32> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+  %shift = ashr <8 x i32> %a, %splat
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, i32 %b) {
+; SSE2-LABEL: 'splatvar_shift_v16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i32> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i32> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <16 x i32> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i32> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <16 x i32> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i32> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i32> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <16 x i32> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+  %shift = ashr <16 x i32> %a, %splat
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, i16 %b) {
+; SSE2-LABEL: 'splatvar_shift_v8i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v8i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v8i16'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v8i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v8i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+  %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+  %shift = ashr <8 x i16> %a, %splat
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, i16 %b) {
+; SSE2-LABEL: 'splatvar_shift_v16i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i16> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v16i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i16> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i16> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v16i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <16 x i16> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v16i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v16i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i16> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+  %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+  %shift = ashr <16 x i16> %a, %splat
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, i16 %b) {
+; SSE2-LABEL: 'splatvar_shift_v32i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <32 x i16> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v32i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <32 x i16> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <32 x i16> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <32 x i16> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v32i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <32 x i16> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v32i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <32 x i16> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'splatvar_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <32 x i16> %a, %splat
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'splatvar_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <32 x i16> %a, %splat
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'splatvar_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <32 x i16> %a, %splat
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'splatvar_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <32 x i16> %a, %splat
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <32 x i16> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+  %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+  %shift = ashr <32 x i16> %a, %splat
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, i8 %b) {
+; SSE2-LABEL: 'splatvar_shift_v16i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 54 for instruction: %shift = ashr <16 x i8> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v16i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <16 x i8> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <16 x i8> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i8> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <16 x i8> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+  %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+  %shift = ashr <16 x i8> %a, %splat
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, i8 %b) {
+; SSE2-LABEL: 'splatvar_shift_v32i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 108 for instruction: %shift = ashr <32 x i8> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v32i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <32 x i8> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 50 for instruction: %shift = ashr <32 x i8> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <32 x i8> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v32i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <32 x i8> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v32i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = ashr <32 x i8> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <32 x i8> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 50 for instruction: %shift = ashr <32 x i8> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+  %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+  %shift = ashr <32 x i8> %a, %splat
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, i8 %b) {
+; SSE2-LABEL: 'splatvar_shift_v64i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 216 for instruction: %shift = ashr <64 x i8> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v64i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %shift = ashr <64 x i8> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 100 for instruction: %shift = ashr <64 x i8> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <64 x i8> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v64i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <64 x i8> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v64i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <64 x i8> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'splatvar_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <64 x i8> %a, %splat
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatvar_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <64 x i8> %a, %splat
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'splatvar_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <64 x i8> %a, %splat
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'splatvar_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <64 x i8> %a, %splat
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 100 for instruction: %shift = ashr <64 x i8> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+  %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+  %shift = ashr <64 x i8> %a, %splat
+  ret <64 x i8> %shift
+}
+
+;
+; Constant Shifts
+;
+
+define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) {
+; SSE-LABEL: 'constant_shift_v2i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <2 x i64> %a, <i64 1, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX1-LABEL: 'constant_shift_v2i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <2 x i64> %a, <i64 1, i64 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX2-LABEL: 'constant_shift_v2i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <2 x i64> %a, <i64 1, i64 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOP-LABEL: 'constant_shift_v2i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <2 x i64> %a, <i64 1, i64 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'constant_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <2 x i64> %a, <i64 1, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v2i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <2 x i64> %a, <i64 1, i64 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %shift = ashr <2 x i64> %a, <i64 1, i64 7>
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) {
+; SSE-LABEL: 'constant_shift_v4i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'constant_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = ashr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'constant_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOP-LABEL: 'constant_shift_v4i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'constant_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = ashr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %shift = ashr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @constant_shift_v8i64(<8 x i64> %a) {
+; SSE-LABEL: 'constant_shift_v8i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'constant_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = ashr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'constant_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOP-LABEL: 'constant_shift_v8i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'constant_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = ashr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %shift = ashr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) {
+; SSE2-LABEL: 'constant_shift_v4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; SSE42-LABEL: 'constant_shift_v4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX1-LABEL: 'constant_shift_v4i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX2-LABEL: 'constant_shift_v4i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOP-LABEL: 'constant_shift_v4i32'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX512-LABEL: 'constant_shift_v4i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v4i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %shift = ashr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) {
+; SSE2-LABEL: 'constant_shift_v8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; SSE42-LABEL: 'constant_shift_v8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'constant_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'constant_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'constant_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @constant_shift_v16i32(<16 x i32> %a) {
+; SSE2-LABEL: 'constant_shift_v16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; SSE42-LABEL: 'constant_shift_v16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'constant_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'constant_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'constant_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) {
+; SSE2-LABEL: 'constant_shift_v8i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; SSE42-LABEL: 'constant_shift_v8i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX-LABEL: 'constant_shift_v8i16'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; XOP-LABEL: 'constant_shift_v8i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v8i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v8i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v8i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v8i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %shift = ashr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) {
+; SSE2-LABEL: 'constant_shift_v16i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; SSE42-LABEL: 'constant_shift_v16i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'constant_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'constant_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOP-LABEL: 'constant_shift_v16i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v16i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v16i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v16i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v16i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @constant_shift_v32i16(<32 x i16> %a) {
+; SSE2-LABEL: 'constant_shift_v32i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; SSE42-LABEL: 'constant_shift_v32i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 56 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'constant_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'constant_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOP-LABEL: 'constant_shift_v32i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
+; SSE2-LABEL: 'constant_shift_v16i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 54 for instruction: %shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; SSE42-LABEL: 'constant_shift_v16i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'constant_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'constant_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'constant_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) {
+; SSE2-LABEL: 'constant_shift_v32i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 108 for instruction: %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; SSE42-LABEL: 'constant_shift_v32i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'constant_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 50 for instruction: %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'constant_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOP-LABEL: 'constant_shift_v32i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'constant_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 50 for instruction: %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @constant_shift_v64i8(<64 x i8> %a) {
+; SSE2-LABEL: 'constant_shift_v64i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 216 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; SSE42-LABEL: 'constant_shift_v64i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'constant_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 100 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'constant_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOP-LABEL: 'constant_shift_v64i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 100 for instruction: %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+  ret <64 x i8> %shift
+}
+
+;
+; Uniform Constant Shifts
+;
+
+define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
+; SSE-LABEL: 'splatconstant_shift_v2i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <2 x i64> %a, <i64 7, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX-LABEL: 'splatconstant_shift_v2i64'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <2 x i64> %a, <i64 7, i64 7>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOP-LABEL: 'splatconstant_shift_v2i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <2 x i64> %a, <i64 7, i64 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <2 x i64> %a, <i64 7, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %shift = ashr <2 x i64> %a, <i64 7, i64 7>
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
+; SSE-LABEL: 'splatconstant_shift_v4i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOP-LABEL: 'splatconstant_shift_v4i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %shift = ashr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @splatconstant_shift_v8i64(<8 x i64> %a) {
+; SSE-LABEL: 'splatconstant_shift_v8i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = ashr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOP-LABEL: 'splatconstant_shift_v8i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %shift = ashr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) {
+; CHECK-LABEL: 'splatconstant_shift_v4i32'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %shift = ashr <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) {
+; SSE-LABEL: 'splatconstant_shift_v8i32'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %shift = ashr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @splatconstant_shift_v16i32(<16 x i32> %a) {
+; SSE-LABEL: 'splatconstant_shift_v16i32'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) {
+; CHECK-LABEL: 'splatconstant_shift_v8i16'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %shift = ashr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) {
+; SSE-LABEL: 'splatconstant_shift_v16i16'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v16i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v16i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v16i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %shift = ashr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @splatconstant_shift_v32i16(<32 x i16> %a) {
+; SSE-LABEL: 'splatconstant_shift_v32i16'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v32i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v32i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'splatconstant_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'splatconstant_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'splatconstant_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
+; SSE-LABEL: 'splatconstant_shift_v16i8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'splatconstant_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'splatconstant_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
+; SSE-LABEL: 'splatconstant_shift_v32i8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOP-LABEL: 'splatconstant_shift_v32i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
+; SSE-LABEL: 'splatconstant_shift_v64i8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOP-LABEL: 'splatconstant_shift_v64i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'splatconstant_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'splatconstant_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'splatconstant_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <64 x i8> %shift
+}
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
new file mode 100644
index 0000000000000..2af629bb75185
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/vshift-lshr-cost-inseltpoison.ll
@@ -0,0 +1,1867 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+xop,+avx | FileCheck %s --check-prefixes=CHECK,XOP,XOPAVX1
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+xop,+avx2 | FileCheck %s --check-prefixes=CHECK,XOP,XOPAVX2
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512BW
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512VL
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512BWVL
+;
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=slm | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=goldmont | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=btver2 | FileCheck %s --check-prefixes=CHECK,AVX,BTVER2
+
+; Verify the cost of vector logical shift right instructions.
+
+;
+; Variable Shifts
+;
+
+define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; SSE-LABEL: 'var_shift_v2i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <2 x i64> %a, %b
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX1-LABEL: 'var_shift_v2i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <2 x i64> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX2-LABEL: 'var_shift_v2i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v2i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <2 x i64> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v2i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'var_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; BTVER2-LABEL: 'var_shift_v2i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <2 x i64> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %shift = lshr <2 x i64> %a, %b
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
+; SSE-LABEL: 'var_shift_v4i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <4 x i64> %a, %b
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'var_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <4 x i64> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'var_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v4i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <4 x i64> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v4i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'var_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'var_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <4 x i64> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %shift = lshr <4 x i64> %a, %b
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @var_shift_v8i64(<8 x i64> %a, <8 x i64> %b) {
+; SSE-LABEL: 'var_shift_v8i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = lshr <8 x i64> %a, %b
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'var_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <8 x i64> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'var_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i64> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v8i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <8 x i64> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v8i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i64> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'var_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i64> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'var_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <8 x i64> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %shift = lshr <8 x i64> %a, %b
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; SSE2-LABEL: 'var_shift_v4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = lshr <4 x i32> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; SSE42-LABEL: 'var_shift_v4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <4 x i32> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX1-LABEL: 'var_shift_v4i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <4 x i32> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX2-LABEL: 'var_shift_v4i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v4i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <4 x i32> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v4i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX512-LABEL: 'var_shift_v4i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; BTVER2-LABEL: 'var_shift_v4i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <4 x i32> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %shift = lshr <4 x i32> %a, %b
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; SSE2-LABEL: 'var_shift_v8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %shift = lshr <8 x i32> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; SSE42-LABEL: 'var_shift_v8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <8 x i32> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'var_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = lshr <8 x i32> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'var_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <8 x i32> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'var_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'var_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = lshr <8 x i32> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %shift = lshr <8 x i32> %a, %b
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @var_shift_v16i32(<16 x i32> %a, <16 x i32> %b) {
+; SSE2-LABEL: 'var_shift_v16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %shift = lshr <16 x i32> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; SSE42-LABEL: 'var_shift_v16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %shift = lshr <16 x i32> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'var_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = lshr <16 x i32> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'var_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i32> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i32> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i32> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'var_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i32> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'var_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = lshr <16 x i32> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %shift = lshr <16 x i32> %a, %b
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; SSE2-LABEL: 'var_shift_v8i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %shift = lshr <8 x i16> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; SSE42-LABEL: 'var_shift_v8i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = lshr <8 x i16> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX-LABEL: 'var_shift_v8i16'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = lshr <8 x i16> %a, %b
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; XOP-LABEL: 'var_shift_v8i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i16> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512F-LABEL: 'var_shift_v8i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = lshr <8 x i16> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v8i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v8i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = lshr <8 x i16> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v8i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %shift = lshr <8 x i16> %a, %b
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
+; SSE2-LABEL: 'var_shift_v16i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %shift = lshr <16 x i16> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; SSE42-LABEL: 'var_shift_v16i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %shift = lshr <16 x i16> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'var_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = lshr <16 x i16> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'var_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <16 x i16> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOP-LABEL: 'var_shift_v16i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <16 x i16> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512F-LABEL: 'var_shift_v16i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <16 x i16> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v16i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v16i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <16 x i16> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v16i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'var_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = lshr <16 x i16> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %shift = lshr <16 x i16> %a, %b
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @var_shift_v32i16(<32 x i16> %a, <32 x i16> %b) {
+; SSE2-LABEL: 'var_shift_v32i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: %shift = lshr <32 x i16> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; SSE42-LABEL: 'var_shift_v32i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 56 for instruction: %shift = lshr <32 x i16> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'var_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = lshr <32 x i16> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'var_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <32 x i16> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOP-LABEL: 'var_shift_v32i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <32 x i16> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'var_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <32 x i16> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <32 x i16> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <32 x i16> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <32 x i16> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'var_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = lshr <32 x i16> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %shift = lshr <32 x i16> %a, %b
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; SSE2-LABEL: 'var_shift_v16i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = lshr <16 x i8> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; SSE42-LABEL: 'var_shift_v16i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i8> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'var_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i8> %a, %b
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'var_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'var_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i8> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %shift = lshr <16 x i8> %a, %b
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
+; SSE2-LABEL: 'var_shift_v32i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = lshr <32 x i8> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; SSE42-LABEL: 'var_shift_v32i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = lshr <32 x i8> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'var_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = lshr <32 x i8> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'var_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <32 x i8> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOP-LABEL: 'var_shift_v32i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <32 x i8> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'var_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <32 x i8> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'var_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = lshr <32 x i8> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %shift = lshr <32 x i8> %a, %b
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @var_shift_v64i8(<64 x i8> %a, <64 x i8> %b) {
+; SSE2-LABEL: 'var_shift_v64i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 104 for instruction: %shift = lshr <64 x i8> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; SSE42-LABEL: 'var_shift_v64i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = lshr <64 x i8> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'var_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = lshr <64 x i8> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'var_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <64 x i8> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOP-LABEL: 'var_shift_v64i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <64 x i8> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'var_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <64 x i8> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <64 x i8> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <64 x i8> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <64 x i8> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'var_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = lshr <64 x i8> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %shift = lshr <64 x i8> %a, %b
+  ret <64 x i8> %shift
+}
+
+;
+; Uniform Variable Shifts
+;
+
+define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, i64 %b) {
+; SSE2-LABEL: 'splatvar_shift_v2i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v2i64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v2i64'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v2i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+  %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+  %shift = lshr <2 x i64> %a, %splat
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, i64 %b) {
+; SSE2-LABEL: 'splatvar_shift_v4i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <4 x i64> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v4i64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <4 x i64> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <4 x i64> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v4i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <4 x i64> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v4i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <4 x i64> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+  %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+  %shift = lshr <4 x i64> %a, %splat
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @splatvar_shift_v8i64(<8 x i64> %a, i64 %b) {
+; SSE2-LABEL: 'splatvar_shift_v8i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <8 x i64> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v8i64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <8 x i64> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <8 x i64> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i64> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v8i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <8 x i64> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v8i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i64> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i64> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <8 x i64> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+  %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+  %shift = lshr <8 x i64> %a, %splat
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, i32 %b) {
+; SSE2-LABEL: 'splatvar_shift_v4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v4i32'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v4i32'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v4i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %shift = lshr <4 x i32> %a, %splat
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, i32 %b) {
+; SSE2-LABEL: 'splatvar_shift_v8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i32> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i32> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <8 x i32> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <8 x i32> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <8 x i32> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+  %shift = lshr <8 x i32> %a, %splat
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, i32 %b) {
+; SSE2-LABEL: 'splatvar_shift_v16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <16 x i32> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <16 x i32> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <16 x i32> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i32> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i32> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i32> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i32> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <16 x i32> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+  %shift = lshr <16 x i32> %a, %splat
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, i16 %b) {
+; SSE2-LABEL: 'splatvar_shift_v8i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v8i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v8i16'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v8i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v8i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+  %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+  %shift = lshr <8 x i16> %a, %splat
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, i16 %b) {
+; SSE2-LABEL: 'splatvar_shift_v16i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i16> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v16i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i16> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <16 x i16> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v16i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <16 x i16> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v16i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v16i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <16 x i16> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+  %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+  %shift = lshr <16 x i16> %a, %splat
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, i16 %b) {
+; SSE2-LABEL: 'splatvar_shift_v32i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <32 x i16> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v32i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <32 x i16> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i16> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i16> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v32i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <32 x i16> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v32i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i16> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'splatvar_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i16> %a, %splat
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'splatvar_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <32 x i16> %a, %splat
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'splatvar_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i16> %a, %splat
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'splatvar_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <32 x i16> %a, %splat
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i16> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+  %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+  %shift = lshr <32 x i16> %a, %splat
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, i8 %b) {
+; SSE2-LABEL: 'splatvar_shift_v16i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = lshr <16 x i8> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v16i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i8> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i8> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i8> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+  %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+  %shift = lshr <16 x i8> %a, %splat
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, i8 %b) {
+; SSE2-LABEL: 'splatvar_shift_v32i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = lshr <32 x i8> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v32i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = lshr <32 x i8> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = lshr <32 x i8> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <32 x i8> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v32i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <32 x i8> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v32i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <32 x i8> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <32 x i8> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = lshr <32 x i8> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+  %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+  %shift = lshr <32 x i8> %a, %splat
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, i8 %b) {
+; SSE2-LABEL: 'splatvar_shift_v64i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 104 for instruction: %shift = lshr <64 x i8> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v64i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = lshr <64 x i8> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = lshr <64 x i8> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <64 x i8> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v64i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <64 x i8> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v64i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <64 x i8> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'splatvar_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <64 x i8> %a, %splat
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatvar_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <64 x i8> %a, %splat
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'splatvar_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <64 x i8> %a, %splat
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'splatvar_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <64 x i8> %a, %splat
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = lshr <64 x i8> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+  %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+  %shift = lshr <64 x i8> %a, %splat
+  ret <64 x i8> %shift
+}
+
+;
+; Constant Shifts
+;
+
+define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) {
+; SSE-LABEL: 'constant_shift_v2i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <2 x i64> %a, <i64 1, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX1-LABEL: 'constant_shift_v2i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <2 x i64> %a, <i64 1, i64 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX2-LABEL: 'constant_shift_v2i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, <i64 1, i64 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOP-LABEL: 'constant_shift_v2i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, <i64 1, i64 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'constant_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, <i64 1, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v2i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <2 x i64> %a, <i64 1, i64 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %shift = lshr <2 x i64> %a, <i64 1, i64 7>
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) {
+; SSE-LABEL: 'constant_shift_v4i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'constant_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'constant_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v4i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v4i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'constant_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @constant_shift_v8i64(<8 x i64> %a) {
+; SSE-LABEL: 'constant_shift_v8i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = lshr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'constant_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'constant_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v8i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v8i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'constant_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %shift = lshr <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) {
+; SSE2-LABEL: 'constant_shift_v4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; SSE42-LABEL: 'constant_shift_v4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX1-LABEL: 'constant_shift_v4i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX2-LABEL: 'constant_shift_v4i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOP-LABEL: 'constant_shift_v4i32'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX512-LABEL: 'constant_shift_v4i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v4i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) {
+; SSE2-LABEL: 'constant_shift_v8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; SSE42-LABEL: 'constant_shift_v8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'constant_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'constant_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'constant_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @constant_shift_v16i32(<16 x i32> %a) {
+; SSE2-LABEL: 'constant_shift_v16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; SSE42-LABEL: 'constant_shift_v16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'constant_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'constant_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'constant_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) {
+; SSE2-LABEL: 'constant_shift_v8i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; SSE42-LABEL: 'constant_shift_v8i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX-LABEL: 'constant_shift_v8i16'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; XOP-LABEL: 'constant_shift_v8i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v8i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v8i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v8i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v8i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) {
+; SSE2-LABEL: 'constant_shift_v16i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; SSE42-LABEL: 'constant_shift_v16i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'constant_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'constant_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOP-LABEL: 'constant_shift_v16i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v16i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v16i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v16i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v16i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @constant_shift_v32i16(<32 x i16> %a) {
+; SSE2-LABEL: 'constant_shift_v32i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; SSE42-LABEL: 'constant_shift_v32i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 56 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'constant_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'constant_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOP-LABEL: 'constant_shift_v32i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
+; SSE2-LABEL: 'constant_shift_v16i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; SSE42-LABEL: 'constant_shift_v16i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'constant_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'constant_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'constant_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) {
+; SSE2-LABEL: 'constant_shift_v32i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; SSE42-LABEL: 'constant_shift_v32i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'constant_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'constant_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOP-LABEL: 'constant_shift_v32i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'constant_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @constant_shift_v64i8(<64 x i8> %a) {
+; SSE2-LABEL: 'constant_shift_v64i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 104 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; SSE42-LABEL: 'constant_shift_v64i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'constant_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'constant_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOP-LABEL: 'constant_shift_v64i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+  ret <64 x i8> %shift
+}
+
+;
+; Uniform Constant Shifts
+;
+
+define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
+; CHECK-LABEL: 'splatconstant_shift_v2i64'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <2 x i64> %a, <i64 7, i64 7>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %shift = lshr <2 x i64> %a, <i64 7, i64 7>
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
+; SSE-LABEL: 'splatconstant_shift_v4i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v4i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v4i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %shift = lshr <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @splatconstant_shift_v8i64(<8 x i64> %a) {
+; SSE-LABEL: 'splatconstant_shift_v8i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v8i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v8i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %shift = lshr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) {
+; CHECK-LABEL: 'splatconstant_shift_v4i32'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %shift = lshr <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) {
+; SSE-LABEL: 'splatconstant_shift_v8i32'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %shift = lshr <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @splatconstant_shift_v16i32(<16 x i32> %a) {
+; SSE-LABEL: 'splatconstant_shift_v16i32'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %shift = lshr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) {
+; CHECK-LABEL: 'splatconstant_shift_v8i16'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %shift = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) {
+; SSE-LABEL: 'splatconstant_shift_v16i16'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v16i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v16i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v16i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %shift = lshr <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @splatconstant_shift_v32i16(<32 x i16> %a) {
+; SSE-LABEL: 'splatconstant_shift_v32i16'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v32i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v32i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'splatconstant_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'splatconstant_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'splatconstant_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
+; SSE-LABEL: 'splatconstant_shift_v16i8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'splatconstant_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'splatconstant_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
+; SSE-LABEL: 'splatconstant_shift_v32i8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v32i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v32i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
+; SSE-LABEL: 'splatconstant_shift_v64i8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v64i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v64i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'splatconstant_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'splatconstant_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'splatconstant_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <64 x i8> %shift
+}
diff --git a/llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll b/llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
new file mode 100644
index 0000000000000..cf6144e9f0143
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/X86/vshift-shl-cost-inseltpoison.ll
@@ -0,0 +1,2197 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+xop,+avx | FileCheck %s --check-prefixes=CHECK,XOP,XOPAVX1
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+xop,+avx2 | FileCheck %s --check-prefixes=CHECK,XOP,XOPAVX2
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512dq | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512BW
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512F
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512VL
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512,AVX512BWVL
+;
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=slm | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=goldmont | FileCheck %s --check-prefixes=CHECK,SSE,SSE42
+; RUN: opt < %s -mtriple=x86_64-unknown-linux-gnu -cost-model -analyze -mcpu=btver2 | FileCheck %s --check-prefixes=CHECK,AVX,BTVER2
+
+; Verify the cost of vector shift left instructions.
+
+;
+; Variable Shifts
+;
+
+define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; SSE-LABEL: 'var_shift_v2i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <2 x i64> %a, %b
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX1-LABEL: 'var_shift_v2i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <2 x i64> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX2-LABEL: 'var_shift_v2i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOP-LABEL: 'var_shift_v2i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'var_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; BTVER2-LABEL: 'var_shift_v2i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <2 x i64> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %shift = shl <2 x i64> %a, %b
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @var_shift_v4i64(<4 x i64> %a, <4 x i64> %b) {
+; SSE-LABEL: 'var_shift_v4i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <4 x i64> %a, %b
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'var_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <4 x i64> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'var_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v4i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i64> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v4i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'var_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'var_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <4 x i64> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %shift = shl <4 x i64> %a, %b
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @var_shift_v8i64(<8 x i64> %a, <8 x i64> %b) {
+; SSE-LABEL: 'var_shift_v8i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = shl <8 x i64> %a, %b
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'var_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <8 x i64> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'var_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i64> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v8i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <8 x i64> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v8i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i64> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'var_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i64> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'var_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <8 x i64> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %shift = shl <8 x i64> %a, %b
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; SSE2-LABEL: 'var_shift_v4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <4 x i32> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; SSE42-LABEL: 'var_shift_v4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i32> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX1-LABEL: 'var_shift_v4i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i32> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX2-LABEL: 'var_shift_v4i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOP-LABEL: 'var_shift_v4i32'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX512-LABEL: 'var_shift_v4i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; BTVER2-LABEL: 'var_shift_v4i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i32> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %shift = shl <4 x i32> %a, %b
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @var_shift_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; SSE2-LABEL: 'var_shift_v8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <8 x i32> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; SSE42-LABEL: 'var_shift_v8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <8 x i32> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'var_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <8 x i32> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'var_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'var_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'var_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <8 x i32> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %shift = shl <8 x i32> %a, %b
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @var_shift_v16i32(<16 x i32> %a, <16 x i32> %b) {
+; SSE2-LABEL: 'var_shift_v16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 40 for instruction: %shift = shl <16 x i32> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; SSE42-LABEL: 'var_shift_v16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = shl <16 x i32> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'var_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <16 x i32> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'var_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i32> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'var_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, %b
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'var_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i32> %a, %b
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'var_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i32> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'var_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <16 x i32> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %shift = shl <16 x i32> %a, %b
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; SSE2-LABEL: 'var_shift_v8i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 32 for instruction: %shift = shl <8 x i16> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; SSE42-LABEL: 'var_shift_v8i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = shl <8 x i16> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX-LABEL: 'var_shift_v8i16'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = shl <8 x i16> %a, %b
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; XOP-LABEL: 'var_shift_v8i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512F-LABEL: 'var_shift_v8i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = shl <8 x i16> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v8i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v8i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %shift = shl <8 x i16> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v8i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %shift = shl <8 x i16> %a, %b
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @var_shift_v16i16(<16 x i16> %a, <16 x i16> %b) {
+; SSE2-LABEL: 'var_shift_v16i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 64 for instruction: %shift = shl <16 x i16> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; SSE42-LABEL: 'var_shift_v16i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 28 for instruction: %shift = shl <16 x i16> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'var_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = shl <16 x i16> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'var_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <16 x i16> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOP-LABEL: 'var_shift_v16i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512F-LABEL: 'var_shift_v16i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <16 x i16> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v16i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v16i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <16 x i16> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v16i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'var_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 30 for instruction: %shift = shl <16 x i16> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %shift = shl <16 x i16> %a, %b
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @var_shift_v32i16(<32 x i16> %a, <32 x i16> %b) {
+; SSE2-LABEL: 'var_shift_v32i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 128 for instruction: %shift = shl <32 x i16> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; SSE42-LABEL: 'var_shift_v32i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 56 for instruction: %shift = shl <32 x i16> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'var_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = shl <32 x i16> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'var_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <32 x i16> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOP-LABEL: 'var_shift_v32i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'var_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <32 x i16> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <32 x i16> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <32 x i16> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <32 x i16> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'var_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 60 for instruction: %shift = shl <32 x i16> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %shift = shl <32 x i16> %a, %b
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; SSE2-LABEL: 'var_shift_v16i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = shl <16 x i8> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; SSE42-LABEL: 'var_shift_v16i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <16 x i8> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'var_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <16 x i8> %a, %b
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'var_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i8> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'var_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <16 x i8> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %shift = shl <16 x i8> %a, %b
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @var_shift_v32i8(<32 x i8> %a, <32 x i8> %b) {
+; SSE2-LABEL: 'var_shift_v32i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = shl <32 x i8> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; SSE42-LABEL: 'var_shift_v32i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <32 x i8> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'var_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = shl <32 x i8> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'var_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <32 x i8> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOP-LABEL: 'var_shift_v32i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i8> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'var_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <32 x i8> %a, %b
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'var_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = shl <32 x i8> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %shift = shl <32 x i8> %a, %b
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @var_shift_v64i8(<64 x i8> %a, <64 x i8> %b) {
+; SSE2-LABEL: 'var_shift_v64i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 104 for instruction: %shift = shl <64 x i8> %a, %b
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; SSE42-LABEL: 'var_shift_v64i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %shift = shl <64 x i8> %a, %b
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'var_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = shl <64 x i8> %a, %b
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'var_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <64 x i8> %a, %b
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOP-LABEL: 'var_shift_v64i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <64 x i8> %a, %b
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'var_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <64 x i8> %a, %b
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'var_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <64 x i8> %a, %b
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'var_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <64 x i8> %a, %b
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'var_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <64 x i8> %a, %b
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'var_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = shl <64 x i8> %a, %b
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %shift = shl <64 x i8> %a, %b
+  ret <64 x i8> %shift
+}
+
+;
+; Uniform Variable Shifts
+;
+
+define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, i64 %b) {
+; SSE2-LABEL: 'splatvar_shift_v2i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v2i64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v2i64'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v2i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %insert = insertelement <2 x i64> poison, i64 %b, i32 0
+  %splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
+  %shift = shl <2 x i64> %a, %splat
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @splatvar_shift_v4i64(<4 x i64> %a, i64 %b) {
+; SSE2-LABEL: 'splatvar_shift_v4i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <4 x i64> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v4i64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <4 x i64> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i64> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v4i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i64> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v4i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i64> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %insert = insertelement <4 x i64> poison, i64 %b, i32 0
+  %splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
+  %shift = shl <4 x i64> %a, %splat
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @splatvar_shift_v8i64(<8 x i64> %a, i64 %b) {
+; SSE2-LABEL: 'splatvar_shift_v8i64'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i64> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v8i64'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i64> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <8 x i64> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i64> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v8i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <8 x i64> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v8i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i64> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i64> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <8 x i64> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %insert = insertelement <8 x i64> poison, i64 %b, i32 0
+  %splat = shufflevector <8 x i64> %insert, <8 x i64> undef, <8 x i32> zeroinitializer
+  %shift = shl <8 x i64> %a, %splat
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, i32 %b) {
+; SSE2-LABEL: 'splatvar_shift_v4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v4i32'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v4i32'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v4i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %insert = insertelement <4 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %shift = shl <4 x i32> %a, %splat
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @splatvar_shift_v8i32(<8 x i32> %a, i32 %b) {
+; SSE2-LABEL: 'splatvar_shift_v8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i32> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i32> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %insert = insertelement <8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
+  %shift = shl <8 x i32> %a, %splat
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, i32 %b) {
+; SSE2-LABEL: 'splatvar_shift_v16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i32> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i32> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i32> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i32> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i32> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %insert = insertelement <16 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <16 x i32> %insert, <16 x i32> undef, <16 x i32> zeroinitializer
+  %shift = shl <16 x i32> %a, %splat
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, i16 %b) {
+; SSE2-LABEL: 'splatvar_shift_v8i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v8i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v8i16'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v8i16'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v8i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %insert = insertelement <8 x i16> poison, i16 %b, i32 0
+  %splat = shufflevector <8 x i16> %insert, <8 x i16> undef, <8 x i32> zeroinitializer
+  %shift = shl <8 x i16> %a, %splat
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @splatvar_shift_v16i16(<16 x i16> %a, i16 %b) {
+; SSE2-LABEL: 'splatvar_shift_v16i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i16> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v16i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i16> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v16i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v16i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v16i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %insert = insertelement <16 x i16> poison, i16 %b, i32 0
+  %splat = shufflevector <16 x i16> %insert, <16 x i16> undef, <16 x i32> zeroinitializer
+  %shift = shl <16 x i16> %a, %splat
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, i16 %b) {
+; SSE2-LABEL: 'splatvar_shift_v32i16'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i16> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v32i16'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i16> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v32i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v32i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'splatvar_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, %splat
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'splatvar_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <32 x i16> %a, %splat
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'splatvar_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, %splat
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'splatvar_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <32 x i16> %a, %splat
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %insert = insertelement <32 x i16> poison, i16 %b, i32 0
+  %splat = shufflevector <32 x i16> %insert, <32 x i16> undef, <32 x i32> zeroinitializer
+  %shift = shl <32 x i16> %a, %splat
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, i8 %b) {
+; SSE2-LABEL: 'splatvar_shift_v16i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = shl <16 x i8> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v16i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <16 x i8> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'splatvar_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; AVX-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; AVX-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <16 x i8> %a, %splat
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'splatvar_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i8> %a, %splat
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <16 x i8> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %insert = insertelement <16 x i8> poison, i8 %b, i32 0
+  %splat = shufflevector <16 x i8> %insert, <16 x i8> undef, <16 x i32> zeroinitializer
+  %shift = shl <16 x i8> %a, %splat
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, i8 %b) {
+; SSE2-LABEL: 'splatvar_shift_v32i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = shl <32 x i8> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v32i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <32 x i8> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = shl <32 x i8> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <32 x i8> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v32i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i8> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v32i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i8> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'splatvar_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <32 x i8> %a, %splat
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = shl <32 x i8> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %insert = insertelement <32 x i8> poison, i8 %b, i32 0
+  %splat = shufflevector <32 x i8> %insert, <32 x i8> undef, <32 x i32> zeroinitializer
+  %shift = shl <32 x i8> %a, %splat
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, i8 %b) {
+; SSE2-LABEL: 'splatvar_shift_v64i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 14 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 104 for instruction: %shift = shl <64 x i8> %a, %splat
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; SSE42-LABEL: 'splatvar_shift_v64i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %shift = shl <64 x i8> %a, %splat
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'splatvar_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = shl <64 x i8> %a, %splat
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'splatvar_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <64 x i8> %a, %splat
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatvar_shift_v64i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <64 x i8> %a, %splat
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatvar_shift_v64i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <64 x i8> %a, %splat
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'splatvar_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <64 x i8> %a, %splat
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatvar_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <64 x i8> %a, %splat
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'splatvar_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <64 x i8> %a, %splat
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'splatvar_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <64 x i8> %a, %splat
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'splatvar_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = shl <64 x i8> %a, %splat
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %insert = insertelement <64 x i8> poison, i8 %b, i32 0
+  %splat = shufflevector <64 x i8> %insert, <64 x i8> undef, <64 x i32> zeroinitializer
+  %shift = shl <64 x i8> %a, %splat
+  ret <64 x i8> %shift
+}
+
+;
+; Constant Shifts
+;
+
+define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) {
+; SSE-LABEL: 'constant_shift_v2i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <2 x i64> %a, <i64 1, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX1-LABEL: 'constant_shift_v2i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <2 x i64> %a, <i64 1, i64 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX2-LABEL: 'constant_shift_v2i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, <i64 1, i64 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; XOP-LABEL: 'constant_shift_v2i64'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, <i64 1, i64 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; AVX512-LABEL: 'constant_shift_v2i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, <i64 1, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v2i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <2 x i64> %a, <i64 1, i64 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %shift = shl <2 x i64> %a, <i64 1, i64 7>
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @constant_shift_v4i64(<4 x i64> %a) {
+; SSE-LABEL: 'constant_shift_v4i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'constant_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'constant_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v4i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v4i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'constant_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 15, i64 31>
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @constant_shift_v8i64(<8 x i64> %a) {
+; SSE-LABEL: 'constant_shift_v8i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shift = shl <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'constant_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'constant_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v8i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v8i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'constant_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shift = shl <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %shift = shl <8 x i64> %a, <i64 1, i64 7, i64 15, i64 31, i64 1, i64 7, i64 15, i64 31>
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) {
+; SSE2-LABEL: 'constant_shift_v4i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; SSE42-LABEL: 'constant_shift_v4i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX1-LABEL: 'constant_shift_v4i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX2-LABEL: 'constant_shift_v4i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; XOP-LABEL: 'constant_shift_v4i32'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; AVX512-LABEL: 'constant_shift_v4i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v4i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %shift = shl <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) {
+; SSE2-LABEL: 'constant_shift_v8i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; SSE42-LABEL: 'constant_shift_v8i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'constant_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'constant_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'constant_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @constant_shift_v16i32(<16 x i32> %a) {
+; SSE2-LABEL: 'constant_shift_v16i32'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; SSE42-LABEL: 'constant_shift_v16i32'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'constant_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'constant_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'constant_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) {
+; CHECK-LABEL: 'constant_shift_v8i16'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %shift = shl <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) {
+; SSE-LABEL: 'constant_shift_v16i16'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'constant_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'constant_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v16i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v16i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512-LABEL: 'constant_shift_v16i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @constant_shift_v32i16(<32 x i16> %a) {
+; SSE-LABEL: 'constant_shift_v32i16'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'constant_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'constant_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX1-LABEL: 'constant_shift_v32i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX2-LABEL: 'constant_shift_v32i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) {
+; SSE2-LABEL: 'constant_shift_v16i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 26 for instruction: %shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; SSE42-LABEL: 'constant_shift_v16i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'constant_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'constant_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'constant_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) {
+; SSE2-LABEL: 'constant_shift_v32i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 52 for instruction: %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; SSE42-LABEL: 'constant_shift_v32i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'constant_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'constant_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOP-LABEL: 'constant_shift_v32i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'constant_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @constant_shift_v64i8(<64 x i8> %a) {
+; SSE2-LABEL: 'constant_shift_v64i8'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 104 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; SSE42-LABEL: 'constant_shift_v64i8'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 44 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'constant_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'constant_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOP-LABEL: 'constant_shift_v64i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'constant_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'constant_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'constant_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 22 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'constant_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 11 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'constant_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
+  ret <64 x i8> %shift
+}
+
+;
+; Uniform Constant Shifts
+;
+
+define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) {
+; CHECK-LABEL: 'splatconstant_shift_v2i64'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <2 x i64> %a, <i64 7, i64 7>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shift
+;
+  %shift = shl <2 x i64> %a, <i64 7, i64 7>
+  ret <2 x i64> %shift
+}
+
+define <4 x i64> @splatconstant_shift_v4i64(<4 x i64> %a) {
+; SSE-LABEL: 'splatconstant_shift_v4i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v4i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v4i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v4i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v4i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v4i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v4i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shift
+;
+  %shift = shl <4 x i64> %a, <i64 7, i64 7, i64 7, i64 7>
+  ret <4 x i64> %shift
+}
+
+define <8 x i64> @splatconstant_shift_v8i64(<8 x i64> %a) {
+; SSE-LABEL: 'splatconstant_shift_v8i64'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v8i64'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v8i64'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v8i64'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v8i64'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v8i64'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v8i64'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shift
+;
+  %shift = shl <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
+  ret <8 x i64> %shift
+}
+
+define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) {
+; CHECK-LABEL: 'splatconstant_shift_v4i32'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shift
+;
+  %shift = shl <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
+  ret <4 x i32> %shift
+}
+
+define <8 x i32> @splatconstant_shift_v8i32(<8 x i32> %a) {
+; SSE-LABEL: 'splatconstant_shift_v8i32'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v8i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v8i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v8i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v8i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v8i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v8i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shift
+;
+  %shift = shl <8 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+  ret <8 x i32> %shift
+}
+
+define <16 x i32> @splatconstant_shift_v16i32(<16 x i32> %a) {
+; SSE-LABEL: 'splatconstant_shift_v16i32'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v16i32'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v16i32'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v16i32'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v16i32'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v16i32'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v16i32'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shift
+;
+  %shift = shl <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
+  ret <16 x i32> %shift
+}
+
+define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) {
+; CHECK-LABEL: 'splatconstant_shift_v8i16'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shift
+;
+  %shift = shl <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <8 x i16> %shift
+}
+
+define <16 x i16> @splatconstant_shift_v16i16(<16 x i16> %a) {
+; SSE-LABEL: 'splatconstant_shift_v16i16'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v16i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v16i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v16i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v16i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v16i16'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v16i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shift
+;
+  %shift = shl <16 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <16 x i16> %shift
+}
+
+define <32 x i16> @splatconstant_shift_v32i16(<32 x i16> %a) {
+; SSE-LABEL: 'splatconstant_shift_v32i16'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v32i16'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v32i16'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v32i16'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v32i16'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512F-LABEL: 'splatconstant_shift_v32i16'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v32i16'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512VL-LABEL: 'splatconstant_shift_v32i16'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; AVX512BWVL-LABEL: 'splatconstant_shift_v32i16'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v32i16'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shift
+;
+  %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
+  ret <32 x i16> %shift
+}
+
+define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) {
+; SSE-LABEL: 'splatconstant_shift_v16i8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX-LABEL: 'splatconstant_shift_v16i8'
+; AVX-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; XOP-LABEL: 'splatconstant_shift_v16i8'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v16i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %shift
+;
+  %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <16 x i8> %shift
+}
+
+define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) {
+; SSE-LABEL: 'splatconstant_shift_v32i8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v32i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v32i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v32i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v32i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; AVX512-LABEL: 'splatconstant_shift_v32i8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v32i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i8> %shift
+;
+  %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <32 x i8> %shift
+}
+
+define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) {
+; SSE-LABEL: 'splatconstant_shift_v64i8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX1-LABEL: 'splatconstant_shift_v64i8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX2-LABEL: 'splatconstant_shift_v64i8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX1-LABEL: 'splatconstant_shift_v64i8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; XOPAVX2-LABEL: 'splatconstant_shift_v64i8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512F-LABEL: 'splatconstant_shift_v64i8'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BW-LABEL: 'splatconstant_shift_v64i8'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512VL-LABEL: 'splatconstant_shift_v64i8'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; AVX512BWVL-LABEL: 'splatconstant_shift_v64i8'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+; BTVER2-LABEL: 'splatconstant_shift_v64i8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <64 x i8> %shift
+;
+  %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+  ret <64 x i8> %shift
+}
+
+;
+; Special Cases
+;
+
+; We always emit a single pmullw in the case of v8i16 vector shifts by
+; non-uniform constant.
+
+define <8 x i16> @test1(<8 x i16> %a) {
+; CHECK-LABEL: 'test1'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <8 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shl
+;
+  %shl = shl <8 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+  ret <8 x i16> %shl
+}
+
+define <8 x i16> @test2(<8 x i16> %a) {
+; CHECK-LABEL: 'test2'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <8 x i16> %a, <i16 0, i16 undef, i16 0, i16 0, i16 1, i16 undef, i16 -1, i16 1>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %shl
+;
+  %shl = shl <8 x i16> %a, <i16 0, i16 undef, i16 0, i16 0, i16 1, i16 undef, i16 -1, i16 1>
+  ret <8 x i16> %shl
+}
+
+; With SSE4.1, v4i32 shifts can be lowered into a single pmulld instruction.
+; Make sure that the estimated cost is always 2 except for the case where
+; we only have SSE2 support. With SSE2, we are forced to special lower the
+; v4i32 mul as a 2x shuffle, 2x pmuludq, 2x shuffle.
+
+define <4 x i32> @test3(<4 x i32> %a) {
+; SSE2-LABEL: 'test3'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; SSE42-LABEL: 'test3'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; AVX1-LABEL: 'test3'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; AVX2-LABEL: 'test3'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; XOP-LABEL: 'test3'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; AVX512-LABEL: 'test3'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; BTVER2-LABEL: 'test3'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+  %shl = shl <4 x i32> %a, <i32 1, i32 -1, i32 2, i32 -3>
+  ret <4 x i32> %shl
+}
+
+define <4 x i32> @test4(<4 x i32> %a) {
+; SSE2-LABEL: 'test4'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; SSE42-LABEL: 'test4'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; AVX1-LABEL: 'test4'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; AVX2-LABEL: 'test4'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; XOP-LABEL: 'test4'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; AVX512-LABEL: 'test4'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+; BTVER2-LABEL: 'test4'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %shl
+;
+  %shl = shl <4 x i32> %a, <i32 0, i32 0, i32 1, i32 1>
+  ret <4 x i32> %shl
+}
+
+; On AVX2 we are able to lower the following shift into a single
+; vpsllvq. Therefore, the expected cost is only 1.
+; In all other cases, this shift is scalarized as the target does not support
+; vpsllv instructions.
+
+define <2 x i64> @test5(<2 x i64> %a) {
+; SSE-LABEL: 'test5'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <2 x i64> %a, <i64 2, i64 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shl
+;
+; AVX1-LABEL: 'test5'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <2 x i64> %a, <i64 2, i64 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shl
+;
+; AVX2-LABEL: 'test5'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <2 x i64> %a, <i64 2, i64 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shl
+;
+; XOP-LABEL: 'test5'
+; XOP-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <2 x i64> %a, <i64 2, i64 3>
+; XOP-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shl
+;
+; AVX512-LABEL: 'test5'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <2 x i64> %a, <i64 2, i64 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shl
+;
+; BTVER2-LABEL: 'test5'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <2 x i64> %a, <i64 2, i64 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %shl
+;
+  %shl = shl <2 x i64> %a, <i64 2, i64 3>
+  ret <2 x i64> %shl
+}
+
+; v16i16 and v8i32 shift left by non-uniform constant are lowered into
+; vector multiply instructions.  With AVX (but not AVX2), the vector multiply
+; is lowered into a sequence of: 1 extract + 2 vpmullw + 1 insert.
+;
+; With AVX2, instruction vpmullw works with 256bit quantities and
+; therefore there is no need to split the resulting vector multiply into
+; a sequence of two multiply.
+;
+; With SSE2 and SSE4.1, the vector shift cost for 'test6' is twice
+; the cost computed in the case of 'test1'. That is because the backend
+; simply emits 2 pmullw with no extract/insert.
+
+define <16 x i16> @test6(<16 x i16> %a) {
+; SSE-LABEL: 'test6'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shl
+;
+; AVX1-LABEL: 'test6'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shl
+;
+; AVX2-LABEL: 'test6'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shl
+;
+; XOPAVX1-LABEL: 'test6'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shl
+;
+; XOPAVX2-LABEL: 'test6'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shl
+;
+; AVX512-LABEL: 'test6'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shl
+;
+; BTVER2-LABEL: 'test6'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i16> %shl
+;
+  %shl = shl <16 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+  ret <16 x i16> %shl
+}
+
+; With SSE2 and SSE4.1, the vector shift cost for 'test7' is twice
+; the cost computed in the case of 'test3'. That is because the multiply
+; is type-legalized into two 4i32 vector multiply.
+
+define <8 x i32> @test7(<8 x i32> %a) {
+; SSE2-LABEL: 'test7'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shl
+;
+; SSE42-LABEL: 'test7'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shl
+;
+; AVX1-LABEL: 'test7'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shl
+;
+; AVX2-LABEL: 'test7'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shl
+;
+; XOPAVX1-LABEL: 'test7'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shl
+;
+; XOPAVX2-LABEL: 'test7'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shl
+;
+; AVX512-LABEL: 'test7'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shl
+;
+; BTVER2-LABEL: 'test7'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i32> %shl
+;
+  %shl = shl <8 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+  ret <8 x i32> %shl
+}
+
+; On AVX2 we are able to lower the following shift into a single
+; vpsllvq. Therefore, the expected cost is only 1.
+; In all other cases, this shift is scalarized as the target does not support
+; vpsllv instructions.
+
+define <4 x i64> @test8(<4 x i64> %a) {
+; SSE-LABEL: 'test8'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shl = shl <4 x i64> %a, <i64 1, i64 2, i64 3, i64 4>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shl
+;
+; AVX1-LABEL: 'test8'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shl = shl <4 x i64> %a, <i64 1, i64 2, i64 3, i64 4>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shl
+;
+; AVX2-LABEL: 'test8'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <4 x i64> %a, <i64 1, i64 2, i64 3, i64 4>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shl
+;
+; XOPAVX1-LABEL: 'test8'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <4 x i64> %a, <i64 1, i64 2, i64 3, i64 4>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shl
+;
+; XOPAVX2-LABEL: 'test8'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <4 x i64> %a, <i64 1, i64 2, i64 3, i64 4>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shl
+;
+; AVX512-LABEL: 'test8'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <4 x i64> %a, <i64 1, i64 2, i64 3, i64 4>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shl
+;
+; BTVER2-LABEL: 'test8'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: %shl = shl <4 x i64> %a, <i64 1, i64 2, i64 3, i64 4>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i64> %shl
+;
+  %shl = shl <4 x i64> %a, <i64 1, i64 2, i64 3, i64 4>
+  ret <4 x i64> %shl
+}
+
+; Same as 'test6', with the difference that the cost is double.
+
+define <32 x i16> @test9(<32 x i16> %a) {
+; SSE-LABEL: 'test9'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+; AVX1-LABEL: 'test9'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+; AVX2-LABEL: 'test9'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+; XOPAVX1-LABEL: 'test9'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+; XOPAVX2-LABEL: 'test9'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+; AVX512F-LABEL: 'test9'
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; AVX512F-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+; AVX512BW-LABEL: 'test9'
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; AVX512BW-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+; AVX512VL-LABEL: 'test9'
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; AVX512VL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+; AVX512BWVL-LABEL: 'test9'
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; AVX512BWVL-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+; BTVER2-LABEL: 'test9'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <32 x i16> %shl
+;
+  %shl = shl <32 x i16> %a, <i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11, i16 1, i16 1, i16 2, i16 3, i16 7, i16 0, i16 9, i16 11>
+  ret <32 x i16> %shl
+}
+
+; Same as 'test7', except that now the cost is double.
+
+define <16 x i32> @test10(<16 x i32> %a) {
+; SSE2-LABEL: 'test10'
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 24 for instruction: %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; SSE2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shl
+;
+; SSE42-LABEL: 'test10'
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; SSE42-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shl
+;
+; AVX1-LABEL: 'test10'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shl
+;
+; AVX2-LABEL: 'test10'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shl
+;
+; XOPAVX1-LABEL: 'test10'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shl
+;
+; XOPAVX2-LABEL: 'test10'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shl
+;
+; AVX512-LABEL: 'test10'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shl
+;
+; BTVER2-LABEL: 'test10'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i32> %shl
+;
+  %shl = shl <16 x i32> %a, <i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3, i32 1, i32 1, i32 2, i32 3>
+  ret <16 x i32> %shl
+}
+
+; On AVX2 we are able to lower the following shift into a sequence of
+; two vpsllvq instructions. Therefore, the expected cost is only 2.
+; In all other cases, this shift is scalarized as we don't have vpsllv
+; instructions.
+
+define <8 x i64> @test11(<8 x i64> %a) {
+; SSE-LABEL: 'test11'
+; SSE-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
+; SSE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shl
+;
+; AVX1-LABEL: 'test11'
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
+; AVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shl
+;
+; AVX2-LABEL: 'test11'
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
+; AVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shl
+;
+; XOPAVX1-LABEL: 'test11'
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
+; XOPAVX1-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shl
+;
+; XOPAVX2-LABEL: 'test11'
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
+; XOPAVX2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shl
+;
+; AVX512-LABEL: 'test11'
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
+; AVX512-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shl
+;
+; BTVER2-LABEL: 'test11'
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 20 for instruction: %shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
+; BTVER2-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i64> %shl
+;
+  %shl = shl <8 x i64> %a, <i64 1, i64 1, i64 2, i64 3, i64 1, i64 1, i64 2, i64 3>
+  ret <8 x i64> %shl
+}
diff --git a/llvm/test/Analysis/DemandedBits/vectors-inseltpoison.ll b/llvm/test/Analysis/DemandedBits/vectors-inseltpoison.ll
new file mode 100644
index 0000000000000..ce735a289c6c5
--- /dev/null
+++ b/llvm/test/Analysis/DemandedBits/vectors-inseltpoison.ll
@@ -0,0 +1,136 @@
+; RUN: opt -S -demanded-bits -analyze -enable-new-pm=0 < %s | FileCheck %s
+; RUN: opt -S -disable-output -passes="print<demanded-bits>" < %s 2>&1 | FileCheck %s
+
+; CHECK-DAG: DemandedBits: 0xff00 for   %x = or <2 x i32> %a, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xff00 for   %y = or <2 x i32> %b, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xff00 for   %z = or <2 x i32> %x, %y
+; CHECK-DAG: DemandedBits: 0xff for   %u = lshr <2 x i32> %z, <i32 8, i32 8>
+; CHECK-DAG: DemandedBits: 0xff for   %r = trunc <2 x i32> %u to <2 x i8>
+define <2 x i8> @test_basic(<2 x i32> %a, <2 x i32> %b) {
+  %x = or <2 x i32> %a, zeroinitializer
+  %y = or <2 x i32> %b, zeroinitializer
+  %z = or <2 x i32> %x, %y
+  %u = lshr <2 x i32> %z, <i32 8, i32 8>
+  %r = trunc <2 x i32> %u to <2 x i8>
+  ret <2 x i8> %r
+}
+
+; Vector-specific instructions
+
+; CHECK-DAG: DemandedBits: 0xff for   %x = or <2 x i32> %a, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xf0 for   %z = extractelement <2 x i32> %x, i32 1
+; CHECK-DAG: DemandedBits: 0xf for   %y = extractelement <2 x i32> %x, i32 0
+; CHECK-DAG: DemandedBits: 0xffffffff for   %u = and i32 %y, 15
+; CHECK-DAG: DemandedBits: 0xffffffff for   %v = and i32 %z, 240
+; CHECK-DAG: DemandedBits: 0xffffffff for   %r = or i32 %u, %v
+define i32 @test_extractelement(<2 x i32> %a) {
+  %x = or <2 x i32> %a, zeroinitializer
+  %y = extractelement <2 x i32> %x, i32 0
+  %z = extractelement <2 x i32> %x, i32 1
+  %u = and i32 %y, 15
+  %v = and i32 %z, 240
+  %r = or i32 %u, %v
+  ret i32 %r
+}
+
+; CHECK-DAG: DemandedBits: 0xff for   %x = or i32 %a, 0
+; CHECK-DAG: DemandedBits: 0xff for   %y = or i32 %b, 0
+; CHECK-DAG: DemandedBits: 0xff for   %z = insertelement <2 x i32> poison, i32 %x, i32 0
+; CHECK-DAG: DemandedBits: 0xff for   %u = insertelement <2 x i32> %z, i32 %y, i32 1
+; CHECK-DAG: DemandedBits: 0xffffffff for   %r = and <2 x i32> %u, <i32 255, i32 127>
+define <2 x i32> @test_insertelement(i32 %a, i32 %b) {
+  %x = or i32 %a, 0
+  %y = or i32 %b, 0
+  %z = insertelement <2 x i32> poison, i32 %x, i32 0
+  %u = insertelement <2 x i32> %z, i32 %y, i32 1
+  %r = and <2 x i32> %u, <i32 255, i32 127>
+  ret <2 x i32> %r
+}
+
+; CHECK-DAG: DemandedBits: 0xff for   %x = or <2 x i32> %a, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xff for   %y = or <2 x i32> %b, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xff for   %z = shufflevector <2 x i32> %x, <2 x i32> %y, <3 x i32> <i32 0, i32 3, i32 1>
+; CHECK-DAG: DemandedBits: 0xffffffff for   %r = and <3 x i32> %z, <i32 255, i32 127, i32 0>
+define <3 x i32> @test_shufflevector(<2 x i32> %a, <2 x i32> %b) {
+  %x = or <2 x i32> %a, zeroinitializer
+  %y = or <2 x i32> %b, zeroinitializer
+  %z = shufflevector <2 x i32> %x, <2 x i32> %y, <3 x i32> <i32 0, i32 3, i32 1>
+  %r = and <3 x i32> %z, <i32 255, i32 127, i32 0>
+  ret <3 x i32> %r
+}
+
+; Shifts with splat shift amounts
+
+; CHECK-DAG: DemandedBits: 0xf for   %x = or <2 x i32> %a, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xf0 for   %y = shl <2 x i32> %x, <i32 4, i32 4>
+; CHECK-DAG: DemandedBits: 0xffffffff for   %r = and <2 x i32> %y, <i32 240, i32 240>
+define <2 x i32> @test_shl(<2 x i32> %a) {
+  %x = or <2 x i32> %a, zeroinitializer
+  %y = shl <2 x i32> %x, <i32 4, i32 4>
+  %r = and <2 x i32> %y, <i32 240, i32 240>
+  ret <2 x i32> %r
+}
+
+; CHECK-DAG: DemandedBits: 0xf00 for   %x = or <2 x i32> %a, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xf0 for   %y = ashr <2 x i32> %x, <i32 4, i32 4>
+; CHECK-DAG: DemandedBits: 0xffffffff for   %r = and <2 x i32> %y, <i32 240, i32 240>
+define <2 x i32> @test_ashr(<2 x i32> %a) {
+  %x = or <2 x i32> %a, zeroinitializer
+  %y = ashr <2 x i32> %x, <i32 4, i32 4>
+  %r = and <2 x i32> %y, <i32 240, i32 240>
+  ret <2 x i32> %r
+}
+
+; CHECK-DAG: DemandedBits: 0xf00 for   %x = or <2 x i32> %a, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xf0 for   %y = lshr <2 x i32> %x, <i32 4, i32 4>
+; CHECK-DAG: DemandedBits: 0xffffffff for   %r = and <2 x i32> %y, <i32 240, i32 240>
+define <2 x i32> @test_lshr(<2 x i32> %a) {
+  %x = or <2 x i32> %a, zeroinitializer
+  %y = lshr <2 x i32> %x, <i32 4, i32 4>
+  %r = and <2 x i32> %y, <i32 240, i32 240>
+  ret <2 x i32> %r
+}
+
+declare <2 x i32> @llvm.fshl.i32(<2 x i32>, <2 x i32>, <2 x i32>)
+declare <2 x i32> @llvm.fshr.i32(<2 x i32>, <2 x i32>, <2 x i32>)
+
+; CHECK-DAG: DemandedBits: 0xf for   %x = or <2 x i32> %a, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xf0000000 for   %y = or <2 x i32> %b, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xff for   %z = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 4, i32 4>)
+; CHECK-DAG: DemandedBits: 0xffffffff for   %r = and <2 x i32> %z, <i32 255, i32 255>
+define <2 x i32> @test_fshl(<2 x i32> %a, <2 x i32> %b) {
+  %x = or <2 x i32> %a, zeroinitializer
+  %y = or <2 x i32> %b, zeroinitializer
+  %z = call <2 x i32> @llvm.fshl.i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 4, i32 4>)
+  %r = and <2 x i32> %z, <i32 255, i32 255>
+  ret <2 x i32> %r
+}
+
+; CHECK-DAG: DemandedBits: 0xf for   %x = or <2 x i32> %a, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xf0000000 for   %y = or <2 x i32> %b, zeroinitializer
+; CHECK-DAG: DemandedBits: 0xff for   %z = call <2 x i32> @llvm.fshr.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 28, i32 28>)
+; CHECK-DAG: DemandedBits: 0xffffffff for   %r = and <2 x i32> %z, <i32 255, i32 255>
+define <2 x i32> @test_fshr(<2 x i32> %a, <2 x i32> %b) {
+  %x = or <2 x i32> %a, zeroinitializer
+  %y = or <2 x i32> %b, zeroinitializer
+  %z = call <2 x i32> @llvm.fshr.i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 28, i32 28>)
+  %r = and <2 x i32> %z, <i32 255, i32 255>
+  ret <2 x i32> %r
+}
+
+; FP / Int conversion. These have different input / output types.
+
+; CHECK-DAG: DemandedBits: 0xffffffff for   %x = or <2 x i32> %a, zeroinitializer
+define <2 x float> @test_uitofp(<2 x i32> %a) {
+  %x = or <2 x i32> %a, zeroinitializer
+  %r = uitofp <2 x i32> %x to <2 x float>
+  ret <2 x float> %r
+}
+
+; CHECK-DAG: DemandedBits: 0xffffffff for   %y = fptoui <2 x float> %x to <2 x i32>
+define <2 x i32> @test_fptoui(<2 x float> %a) {
+  %x = fadd <2 x float> %a, <float 1.0, float 1.0>
+  %y = fptoui <2 x float> %x to <2 x i32>
+  %r = and <2 x i32> %y, <i32 255, i32 255>
+  ret <2 x i32> %y
+}
diff --git a/llvm/test/Analysis/ValueTracking/known-non-equal.ll b/llvm/test/Analysis/ValueTracking/known-non-equal.ll
index 8bc9a86c9a93d..197088a85e814 100644
--- a/llvm/test/Analysis/ValueTracking/known-non-equal.ll
+++ b/llvm/test/Analysis/ValueTracking/known-non-equal.ll
@@ -201,5 +201,17 @@ define i1 @mul5(i8 %B, i8 %C) {
   ret i1 %cmp
 }
 
+@g = external global i16, align 1
+
+define i1 @mul_constantexpr(i16 %a) {
+; CHECK-LABEL: @mul_constantexpr(
+; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i16 [[A:%.*]], 3
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i16 mul nsw (i16 ptrtoint (i16* @g to i16), i16 -1), [[MUL]]
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul = mul nsw i16 %a, 3
+  %cmp = icmp eq i16 mul nsw (i16 ptrtoint (i16* @g to i16), i16 -1), %mul
+  ret i1 %cmp
+}
 
 !0 = !{ i8 1, i8 5 }
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
new file mode 100644
index 0000000000000..481c71fbed60b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-shift-immed-mismatch-crash.mir
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
+---
+name:            shift_immed_chain_mismatch_size_crash
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0' }
+body:             |
+  ; CHECK-LABEL: name: shift_immed_chain_mismatch_size_crash
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  ; CHECK:   liveins: $x0
+  ; CHECK:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
+  ; CHECK:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+  ; CHECK:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
+  ; CHECK:   [[DEF1:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
+  ; CHECK:   G_BRCOND [[DEF1]](s1), %bb.2
+  ; CHECK:   G_BR %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   successors:
+  ; CHECK: bb.2:
+  ; CHECK:   [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4 from `i32* undef`, align 8)
+  ; CHECK:   [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[C]], [[LOAD]]
+  ; CHECK:   [[MUL1:%[0-9]+]]:_(s32) = nsw G_MUL [[MUL]], [[C1]]
+  ; CHECK:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+  ; CHECK:   [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL1]], [[C2]](s64)
+  ; CHECK:   $w0 = COPY [[SHL]](s32)
+  ; CHECK:   RET_ReallyLR implicit $w0
+  bb.1:
+    liveins: $x0
+
+    %0:_(p0) = COPY $x0
+    %1:_(s1) = G_IMPLICIT_DEF
+    %3:_(p0) = G_IMPLICIT_DEF
+    %4:_(s32) = G_CONSTANT i32 16
+    %6:_(s32) = G_CONSTANT i32 9
+    %8:_(s32) = G_CONSTANT i32 2
+    %11:_(s64) = G_CONSTANT i64 2
+    G_BRCOND %1(s1), %bb.2
+    G_BR %bb.3
+
+  bb.2:
+    successors:
+
+
+  bb.3:
+    %2:_(s32) = G_LOAD %3(p0) :: (load 4 from `i32* undef`, align 8)
+    %5:_(s32) = nsw G_MUL %4, %2
+    %7:_(s32) = nsw G_MUL %5, %6
+    %9:_(s32) = nsw G_MUL %7, %8
+    %10:_(s64) = G_SEXT %9(s32)
+    %12:_(s64) = G_MUL %10, %11
+    %13:_(s32) = G_TRUNC %12(s64)
+    $w0 = COPY %13(s32)
+    RET_ReallyLR implicit $w0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-invoke-probabilities.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-invoke-probabilities.ll
index 95dc96ee63efd..473216e9f1701 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-invoke-probabilities.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-invoke-probabilities.ll
@@ -11,7 +11,7 @@ declare i32 @hoge(...)
 define void @pluto() align 2 personality i8* bitcast (i32 (...)* @hoge to i8*) {
 ; CHECK-LABEL: @pluto
 ; CHECK: bb.1.bb
-; CHECK: successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
+; CHECK: successors: %bb.2(0x00000000), %bb.3(0x80000000)
 ; CHECK: EH_LABEL <mcsymbol >
 ; CHECK: G_BR %bb.2
 
diff --git a/llvm/test/CodeGen/AArch64/aarch64-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
index 5828106357cad..17a21e566ec41 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-smull.ll
@@ -1,8 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s -o -| FileCheck %s
 
 define <8 x i16> @smull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ; CHECK-LABEL: smull_v8i8_v8i16:
-; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    smull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
@@ -13,7 +18,11 @@ define <8 x i16> @smull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 
 define <4 x i32> @smull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ; CHECK-LABEL: smull_v4i16_v4i32:
-; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
   %tmp1 = load <4 x i16>, <4 x i16>* %A
   %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
@@ -24,7 +33,11 @@ define <4 x i32> @smull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 
 define <2 x i64> @smull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ; CHECK-LABEL: smull_v2i32_v2i64:
-; CHECK:  smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    smull v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
   %tmp1 = load <2 x i32>, <2 x i32>* %A
   %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
@@ -35,7 +48,11 @@ define <2 x i64> @smull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 
 define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ; CHECK-LABEL: umull_v8i8_v8i16:
-; CHECK: umull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    umull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
@@ -46,7 +63,11 @@ define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 
 define <4 x i32> @umull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 ; CHECK-LABEL: umull_v4i16_v4i32:
-; CHECK: umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    umull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
   %tmp1 = load <4 x i16>, <4 x i16>* %A
   %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
@@ -57,7 +78,11 @@ define <4 x i32> @umull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 
 define <2 x i64> @umull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
 ; CHECK-LABEL: umull_v2i32_v2i64:
-; CHECK:  umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    umull v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
   %tmp1 = load <2 x i32>, <2 x i32>* %A
   %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
@@ -66,9 +91,80 @@ define <2 x i64> @umull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
   ret <2 x i64> %tmp5
 }
 
+define <8 x i16> @amull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
+; CHECK-LABEL: amull_v8i8_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
+; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+  %tmp1 = load <8 x i8>, <8 x i8>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
+  %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
+  %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+  %tmp5 = mul <8 x i16> %tmp3, %tmp4
+  %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @amull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
+; CHECK-LABEL: amull_v4i16_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %tmp1 = load <4 x i16>, <4 x i16>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
+  %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+  %tmp5 = mul <4 x i32> %tmp3, %tmp4
+  %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @amull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
+; CHECK-LABEL: amull_v2i32_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-NEXT:    ushll v1.2d, v1.2s, #0
+; CHECK-NEXT:    fmov x10, d1
+; CHECK-NEXT:    fmov x11, d0
+; CHECK-NEXT:    mov x8, v1.d[1]
+; CHECK-NEXT:    mov x9, v0.d[1]
+; CHECK-NEXT:    mul x10, x11, x10
+; CHECK-NEXT:    mul x8, x9, x8
+; CHECK-NEXT:    fmov d0, x10
+; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %tmp1 = load <2 x i32>, <2 x i32>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
+  %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+  %tmp5 = mul <2 x i64> %tmp3, %tmp4
+  %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i16> @smlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ; CHECK-LABEL: smlal_v8i8_v8i16:
-; CHECK:  smlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    smlal v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
   %tmp1 = load <8 x i16>, <8 x i16>* %A
   %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = load <8 x i8>, <8 x i8>* %C
@@ -81,7 +177,12 @@ define <8 x i16> @smlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no
 
 define <4 x i32> @smlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ; CHECK-LABEL: smlal_v4i16_v4i32:
-; CHECK: smlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    smlal v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
   %tmp1 = load <4 x i32>, <4 x i32>* %A
   %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = load <4 x i16>, <4 x i16>* %C
@@ -94,7 +195,12 @@ define <4 x i32> @smlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C)
 
 define <2 x i64> @smlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ; CHECK-LABEL: smlal_v2i32_v2i64:
-; CHECK: smlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    smlal v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
   %tmp1 = load <2 x i64>, <2 x i64>* %A
   %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = load <2 x i32>, <2 x i32>* %C
@@ -107,7 +213,12 @@ define <2 x i64> @smlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C)
 
 define <8 x i16> @umlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ; CHECK-LABEL: umlal_v8i8_v8i16:
-; CHECK:  umlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    umlal v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
   %tmp1 = load <8 x i16>, <8 x i16>* %A
   %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = load <8 x i8>, <8 x i8>* %C
@@ -120,7 +231,12 @@ define <8 x i16> @umlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no
 
 define <4 x i32> @umlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ; CHECK-LABEL: umlal_v4i16_v4i32:
-; CHECK: umlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    umlal v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
   %tmp1 = load <4 x i32>, <4 x i32>* %A
   %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = load <4 x i16>, <4 x i16>* %C
@@ -133,7 +249,12 @@ define <4 x i32> @umlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C)
 
 define <2 x i64> @umlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ; CHECK-LABEL: umlal_v2i32_v2i64:
-; CHECK: umlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    umlal v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
   %tmp1 = load <2 x i64>, <2 x i64>* %A
   %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = load <2 x i32>, <2 x i32>* %C
@@ -144,9 +265,90 @@ define <2 x i64> @umlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C)
   ret <2 x i64> %tmp7
 }
 
+define <8 x i16> @amlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+; CHECK-LABEL: amlal_v8i8_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
+; CHECK-NEXT:    ushll v2.8h, v2.8b, #0
+; CHECK-NEXT:    mla v0.8h, v1.8h, v2.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
+  %tmp3 = load <8 x i8>, <8 x i8>* %C
+  %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+  %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
+  %tmp6 = mul <8 x i16> %tmp4, %tmp5
+  %tmp7 = add <8 x i16> %tmp1, %tmp6
+  %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @amlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+; CHECK-LABEL: amlal_v4i16_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x1]
+; CHECK-NEXT:    ldr d1, [x2]
+; CHECK-NEXT:    ldr q2, [x0]
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v0.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v2.16b, v0.16b
+; CHECK-NEXT:    ret
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i16>, <4 x i16>* %C
+  %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+  %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
+  %tmp6 = mul <4 x i32> %tmp4, %tmp5
+  %tmp7 = add <4 x i32> %tmp1, %tmp6
+  %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @amlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+; CHECK-LABEL: amlal_v2i32_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x1]
+; CHECK-NEXT:    ldr d1, [x2]
+; CHECK-NEXT:    ldr q2, [x0]
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-NEXT:    ushll v1.2d, v1.2s, #0
+; CHECK-NEXT:    fmov x10, d1
+; CHECK-NEXT:    fmov x11, d0
+; CHECK-NEXT:    mov x8, v1.d[1]
+; CHECK-NEXT:    mov x9, v0.d[1]
+; CHECK-NEXT:    mul x10, x11, x10
+; CHECK-NEXT:    mul x8, x9, x8
+; CHECK-NEXT:    fmov d0, x10
+; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    add v0.2d, v2.2d, v0.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %tmp1 = load <2 x i64>, <2 x i64>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i32>, <2 x i32>* %C
+  %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+  %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
+  %tmp6 = mul <2 x i64> %tmp4, %tmp5
+  %tmp7 = add <2 x i64> %tmp1, %tmp6
+  %and = and <2 x i64> %tmp7, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i16> @smlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ; CHECK-LABEL: smlsl_v8i8_v8i16:
-; CHECK:  smlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    smlsl v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
   %tmp1 = load <8 x i16>, <8 x i16>* %A
   %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = load <8 x i8>, <8 x i8>* %C
@@ -159,7 +361,12 @@ define <8 x i16> @smlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no
 
 define <4 x i32> @smlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ; CHECK-LABEL: smlsl_v4i16_v4i32:
-; CHECK: smlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    smlsl v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
   %tmp1 = load <4 x i32>, <4 x i32>* %A
   %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = load <4 x i16>, <4 x i16>* %C
@@ -172,7 +379,12 @@ define <4 x i32> @smlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C)
 
 define <2 x i64> @smlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ; CHECK-LABEL: smlsl_v2i32_v2i64:
-; CHECK: smlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    smlsl v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
   %tmp1 = load <2 x i64>, <2 x i64>* %A
   %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = load <2 x i32>, <2 x i32>* %C
@@ -185,7 +397,12 @@ define <2 x i64> @smlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C)
 
 define <8 x i16> @umlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
 ; CHECK-LABEL: umlsl_v8i8_v8i16:
-; CHECK:  umlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    umlsl v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
   %tmp1 = load <8 x i16>, <8 x i16>* %A
   %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = load <8 x i8>, <8 x i8>* %C
@@ -198,7 +415,12 @@ define <8 x i16> @umlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) no
 
 define <4 x i32> @umlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
 ; CHECK-LABEL: umlsl_v4i16_v4i32:
-; CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    umlsl v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
   %tmp1 = load <4 x i32>, <4 x i32>* %A
   %tmp2 = load <4 x i16>, <4 x i16>* %B
   %tmp3 = load <4 x i16>, <4 x i16>* %C
@@ -211,7 +433,12 @@ define <4 x i32> @umlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C)
 
 define <2 x i64> @umlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
 ; CHECK-LABEL: umlsl_v2i32_v2i64:
-; CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    umlsl v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
   %tmp1 = load <2 x i64>, <2 x i64>* %A
   %tmp2 = load <2 x i32>, <2 x i32>* %B
   %tmp3 = load <2 x i32>, <2 x i32>* %C
@@ -222,10 +449,89 @@ define <2 x i64> @umlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C)
   ret <2 x i64> %tmp7
 }
 
+define <8 x i16> @amlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
+; CHECK-LABEL: amlsl_v8i8_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d1, [x1]
+; CHECK-NEXT:    ldr d2, [x2]
+; CHECK-NEXT:    ldr q0, [x0]
+; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
+; CHECK-NEXT:    ushll v2.8h, v2.8b, #0
+; CHECK-NEXT:    mls v0.8h, v1.8h, v2.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+  %tmp1 = load <8 x i16>, <8 x i16>* %A
+  %tmp2 = load <8 x i8>, <8 x i8>* %B
+  %tmp3 = load <8 x i8>, <8 x i8>* %C
+  %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+  %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
+  %tmp6 = mul <8 x i16> %tmp4, %tmp5
+  %tmp7 = sub <8 x i16> %tmp1, %tmp6
+  %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @amlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
+; CHECK-LABEL: amlsl_v4i16_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x1]
+; CHECK-NEXT:    ldr d1, [x2]
+; CHECK-NEXT:    ldr q2, [x0]
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:    mls v2.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v0.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v2.16b, v0.16b
+; CHECK-NEXT:    ret
+  %tmp1 = load <4 x i32>, <4 x i32>* %A
+  %tmp2 = load <4 x i16>, <4 x i16>* %B
+  %tmp3 = load <4 x i16>, <4 x i16>* %C
+  %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+  %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
+  %tmp6 = mul <4 x i32> %tmp4, %tmp5
+  %tmp7 = sub <4 x i32> %tmp1, %tmp6
+  %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @amlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
+; CHECK-LABEL: amlsl_v2i32_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ldr d0, [x1]
+; CHECK-NEXT:    ldr d1, [x2]
+; CHECK-NEXT:    ldr q2, [x0]
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-NEXT:    ushll v1.2d, v1.2s, #0
+; CHECK-NEXT:    fmov x10, d1
+; CHECK-NEXT:    fmov x11, d0
+; CHECK-NEXT:    mov x8, v1.d[1]
+; CHECK-NEXT:    mov x9, v0.d[1]
+; CHECK-NEXT:    mul x10, x11, x10
+; CHECK-NEXT:    mul x8, x9, x8
+; CHECK-NEXT:    fmov d0, x10
+; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    sub v0.2d, v2.2d, v0.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %tmp1 = load <2 x i64>, <2 x i64>* %A
+  %tmp2 = load <2 x i32>, <2 x i32>* %B
+  %tmp3 = load <2 x i32>, <2 x i32>* %C
+  %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+  %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
+  %tmp6 = mul <2 x i64> %tmp4, %tmp5
+  %tmp7 = sub <2 x i64> %tmp1, %tmp6
+  %and = and <2 x i64> %tmp7, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 ; SMULL recognizing BUILD_VECTORs with sign/zero-extended elements.
 define <8 x i16> @smull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
 ; CHECK-LABEL: smull_extvec_v8i8_v8i16:
-; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8b, #244
+; CHECK-NEXT:    smull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
   %tmp3 = sext <8 x i8> %arg to <8 x i16>
   %tmp4 = mul <8 x i16> %tmp3, <i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12>
   ret <8 x i16> %tmp4
@@ -234,8 +540,12 @@ define <8 x i16> @smull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
 define <8 x i16> @smull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
 ; Do not use SMULL if the BUILD_VECTOR element values are too big.
 ; CHECK-LABEL: smull_noextvec_v8i8_v8i16:
-; CHECK: mov
-; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #64537
+; CHECK-NEXT:    sshll v0.8h, v0.8b, #0
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    ret
   %tmp3 = sext <8 x i8> %arg to <8 x i16>
   %tmp4 = mul <8 x i16> %tmp3, <i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999>
   ret <8 x i16> %tmp4
@@ -243,15 +553,22 @@ define <8 x i16> @smull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
 
 define <4 x i32> @smull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind {
 ; CHECK-LABEL: smull_extvec_v4i16_v4i32:
-; CHECK:  smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mvni v1.4h, #11
+; CHECK-NEXT:    smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
   %tmp3 = sext <4 x i16> %arg to <4 x i32>
   %tmp4 = mul <4 x i32> %tmp3, <i32 -12, i32 -12, i32 -12, i32 -12>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @smull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind {
-; CHECK: smull_extvec_v2i32_v2i64
-; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK-LABEL: smull_extvec_v2i32_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #-1234
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    smull v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
   %tmp3 = sext <2 x i32> %arg to <2 x i64>
   %tmp4 = mul <2 x i64> %tmp3, <i64 -1234, i64 -1234>
   ret <2 x i64> %tmp4
@@ -259,7 +576,10 @@ define <2 x i64> @smull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind {
 
 define <8 x i16> @umull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
 ; CHECK-LABEL: umull_extvec_v8i8_v8i16:
-; CHECK: umull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v1.8b, #12
+; CHECK-NEXT:    umull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
   %tmp3 = zext <8 x i8> %arg to <8 x i16>
   %tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
   ret <8 x i16> %tmp4
@@ -268,8 +588,12 @@ define <8 x i16> @umull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
 define <8 x i16> @umull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
 ; Do not use SMULL if the BUILD_VECTOR element values are too big.
 ; CHECK-LABEL: umull_noextvec_v8i8_v8i16:
-; CHECK: mov
-; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #999
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-NEXT:    dup v1.8h, w8
+; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    ret
   %tmp3 = zext <8 x i8> %arg to <8 x i16>
   %tmp4 = mul <8 x i16> %tmp3, <i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999>
   ret <8 x i16> %tmp4
@@ -277,7 +601,11 @@ define <8 x i16> @umull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
 
 define <4 x i32> @umull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind {
 ; CHECK-LABEL: umull_extvec_v4i16_v4i32:
-; CHECK:  umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1234
+; CHECK-NEXT:    dup v1.4h, w8
+; CHECK-NEXT:    umull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
   %tmp3 = zext <4 x i16> %arg to <4 x i32>
   %tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234>
   ret <4 x i32> %tmp4
@@ -285,17 +613,76 @@ define <4 x i32> @umull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind {
 
 define <2 x i64> @umull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind {
 ; CHECK-LABEL: umull_extvec_v2i32_v2i64:
-; CHECK: umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1234
+; CHECK-NEXT:    dup v1.2s, w8
+; CHECK-NEXT:    umull v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
   %tmp3 = zext <2 x i32> %arg to <2 x i64>
   %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>
   ret <2 x i64> %tmp4
 }
 
+define <8 x i16> @amull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
+; CHECK-LABEL: amull_extvec_v8i8_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-NEXT:    movi v1.8h, #12
+; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+  %tmp3 = zext <8 x i8> %arg to <8 x i16>
+  %tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
+  %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @amull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind {
+; CHECK-LABEL: amull_extvec_v4i16_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #1234
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    dup v1.4s, w8
+; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %tmp3 = zext <4 x i16> %arg to <4 x i32>
+  %tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234>
+  %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @amull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind {
+; CHECK-LABEL: amull_extvec_v2i32_v2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-NEXT:    mov w8, #1234
+; CHECK-NEXT:    fmov x10, d0
+; CHECK-NEXT:    mov x9, v0.d[1]
+; CHECK-NEXT:    mul x10, x10, x8
+; CHECK-NEXT:    mul x8, x9, x8
+; CHECK-NEXT:    fmov d0, x10
+; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+  %tmp3 = zext <2 x i32> %arg to <2 x i64>
+  %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>
+  %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define i16 @smullWithInconsistentExtensions(<8 x i8> %x, <8 x i8> %y) {
 ; If one operand has a zero-extend and the other a sign-extend, smull
 ; cannot be used.
 ; CHECK-LABEL: smullWithInconsistentExtensions:
-; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sshll v0.8h, v0.8b, #0
+; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
+; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    umov w0, v0.h[0]
+; CHECK-NEXT:    ret
   %s = sext <8 x i8> %x to <8 x i16>
   %z = zext <8 x i8> %y to <8 x i16>
   %m = mul <8 x i16> %s, %z
@@ -303,15 +690,21 @@ define i16 @smullWithInconsistentExtensions(<8 x i8> %x, <8 x i8> %y) {
   ret i16 %r
 }
 
-define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {
-entry:
+define void @distribute(<8 x i16>* %dst, <16 x i8>* %src, i32 %mul) nounwind {
 ; CHECK-LABEL: distribute:
-; CHECK: umull [[REG1:(v[0-9]+.8h)]], {{v[0-9]+}}.8b, [[REG2:(v[0-9]+.8b)]]
-; CHECK: umlal [[REG1]], {{v[0-9]+}}.8b, [[REG2]]
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ldr q0, [x1]
+; CHECK-NEXT:    dup v1.8b, w2
+; CHECK-NEXT:    mov d2, v0.d[1]
+; CHECK-NEXT:    umull v2.8h, v2.8b, v1.8b
+; CHECK-NEXT:    umlal v2.8h, v0.8b, v1.8b
+; CHECK-NEXT:    str q2, [x0]
+; CHECK-NEXT:    ret
+entry:
   %0 = trunc i32 %mul to i8
   %1 = insertelement <8 x i8> undef, i8 %0, i32 0
   %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
-  %3 = tail call <16 x i8> @llvm.aarch64.neon.vld1.v16i8(i8* %src, i32 1)
+  %3 = load <16 x i8>, <16 x i8>* %src, align 1
   %4 = bitcast <16 x i8> %3 to <2 x double>
   %5 = extractelement <2 x double> %4, i32 1
   %6 = bitcast double %5 to <8 x i8>
@@ -322,15 +715,17 @@ entry:
   %11 = zext <8 x i8> %10 to <8 x i16>
   %12 = add <8 x i16> %7, %11
   %13 = mul <8 x i16> %12, %8
-  %14 = bitcast i16* %dst to i8*
-  tail call void @llvm.aarch64.neon.vst1.v8i16(i8* %14, <8 x i16> %13, i32 2)
+  store <8 x i16> %13, <8 x i16>* %dst, align 2
   ret void
 }
 
 define <16 x i16> @umull2_i8(<16 x i8> %arg1, <16 x i8> %arg2) {
 ; CHECK-LABEL: umull2_i8:
-; CHECK-DAG: umull2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
-; CHECK-DAG: umull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umull2 v2.8h, v0.16b, v1.16b
+; CHECK-NEXT:    umull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    mov v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %arg1_ext = zext <16 x i8> %arg1 to <16 x i16>
   %arg2_ext = zext <16 x i8> %arg2 to <16 x i16>
   %mul = mul <16 x i16> %arg1_ext, %arg2_ext
@@ -339,8 +734,11 @@ define <16 x i16> @umull2_i8(<16 x i8> %arg1, <16 x i8> %arg2) {
 
 define <16 x i16> @smull2_i8(<16 x i8> %arg1, <16 x i8> %arg2) {
 ; CHECK-LABEL: smull2_i8:
-; CHECK-DAG: smull2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
-; CHECK-DAG: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smull2 v2.8h, v0.16b, v1.16b
+; CHECK-NEXT:    smull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    mov v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %arg1_ext = sext <16 x i8> %arg1 to <16 x i16>
   %arg2_ext = sext <16 x i8> %arg2 to <16 x i16>
   %mul = mul <16 x i16> %arg1_ext, %arg2_ext
@@ -349,8 +747,11 @@ define <16 x i16> @smull2_i8(<16 x i8> %arg1, <16 x i8> %arg2) {
 
 define <8 x i32> @umull2_i16(<8 x i16> %arg1, <8 x i16> %arg2) {
 ; CHECK-LABEL: umull2_i16:
-; CHECK-DAG: umull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
-; CHECK-DAG: umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umull2 v2.4s, v0.8h, v1.8h
+; CHECK-NEXT:    umull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    mov v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %arg1_ext = zext <8 x i16> %arg1 to <8 x i32>
   %arg2_ext = zext <8 x i16> %arg2 to <8 x i32>
   %mul = mul <8 x i32> %arg1_ext, %arg2_ext
@@ -359,8 +760,11 @@ define <8 x i32> @umull2_i16(<8 x i16> %arg1, <8 x i16> %arg2) {
 
 define <8 x i32> @smull2_i16(<8 x i16> %arg1, <8 x i16> %arg2) {
 ; CHECK-LABEL: smull2_i16:
-; CHECK-DAG: smull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
-; CHECK-DAG: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smull2 v2.4s, v0.8h, v1.8h
+; CHECK-NEXT:    smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    mov v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %arg1_ext = sext <8 x i16> %arg1 to <8 x i32>
   %arg2_ext = sext <8 x i16> %arg2 to <8 x i32>
   %mul = mul <8 x i32> %arg1_ext, %arg2_ext
@@ -369,8 +773,11 @@ define <8 x i32> @smull2_i16(<8 x i16> %arg1, <8 x i16> %arg2) {
 
 define <4 x i64> @umull2_i32(<4 x i32> %arg1, <4 x i32> %arg2) {
 ; CHECK-LABEL: umull2_i32:
-; CHECK-DAG: umull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
-; CHECK-DAG: umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    umull2 v2.2d, v0.4s, v1.4s
+; CHECK-NEXT:    umull v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    mov v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %arg1_ext = zext <4 x i32> %arg1 to <4 x i64>
   %arg2_ext = zext <4 x i32> %arg2 to <4 x i64>
   %mul = mul <4 x i64> %arg1_ext, %arg2_ext
@@ -379,15 +786,87 @@ define <4 x i64> @umull2_i32(<4 x i32> %arg1, <4 x i32> %arg2) {
 
 define <4 x i64> @smull2_i32(<4 x i32> %arg1, <4 x i32> %arg2) {
 ; CHECK-LABEL: smull2_i32:
-; CHECK-DAG: smull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
-; CHECK-DAG: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    smull2 v2.2d, v0.4s, v1.4s
+; CHECK-NEXT:    smull v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    mov v1.16b, v2.16b
+; CHECK-NEXT:    ret
   %arg1_ext = sext <4 x i32> %arg1 to <4 x i64>
   %arg2_ext = sext <4 x i32> %arg2 to <4 x i64>
   %mul = mul <4 x i64> %arg1_ext, %arg2_ext
   ret <4 x i64> %mul
 }
 
-declare <16 x i8> @llvm.aarch64.neon.vld1.v16i8(i8*, i32) nounwind readonly
-
-declare void @llvm.aarch64.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind
+define <16 x i16> @amull2_i8(<16 x i8> %arg1, <16 x i8> %arg2) {
+; CHECK-LABEL: amull2_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll2 v2.8h, v0.16b, #0
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-NEXT:    ushll2 v3.8h, v1.16b, #0
+; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
+; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    mul v1.8h, v2.8h, v3.8h
+; CHECK-NEXT:    bic v1.8h, #255, lsl #8
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+  %arg1_ext = zext <16 x i8> %arg1 to <16 x i16>
+  %arg2_ext = zext <16 x i8> %arg2 to <16 x i16>
+  %mul = mul <16 x i16> %arg1_ext, %arg2_ext
+  %and = and <16 x i16> %mul, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <16 x i16> %and
+}
+
+define <8 x i32> @amull2_i16(<8 x i16> %arg1, <8 x i16> %arg2) {
+; CHECK-LABEL: amull2_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll2 v2.4s, v0.8h, #0
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    ushll2 v3.4s, v1.8h, #0
+; CHECK-NEXT:    ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:    movi v4.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    mul v1.4s, v2.4s, v3.4s
+; CHECK-NEXT:    and v1.16b, v1.16b, v4.16b
+; CHECK-NEXT:    and v0.16b, v0.16b, v4.16b
+; CHECK-NEXT:    ret
+  %arg1_ext = zext <8 x i16> %arg1 to <8 x i32>
+  %arg2_ext = zext <8 x i16> %arg2 to <8 x i32>
+  %mul = mul <8 x i32> %arg1_ext, %arg2_ext
+  %and = and <8 x i32> %mul, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <8 x i32> %and
+}
+
+define <4 x i64> @amull2_i32(<4 x i32> %arg1, <4 x i32> %arg2) {
+; CHECK-LABEL: amull2_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ushll2 v2.2d, v0.4s, #0
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-NEXT:    ushll2 v3.2d, v1.4s, #0
+; CHECK-NEXT:    ushll v1.2d, v1.2s, #0
+; CHECK-NEXT:    fmov x10, d1
+; CHECK-NEXT:    fmov x11, d0
+; CHECK-NEXT:    fmov x13, d3
+; CHECK-NEXT:    fmov x14, d2
+; CHECK-NEXT:    mov x8, v1.d[1]
+; CHECK-NEXT:    mov x9, v0.d[1]
+; CHECK-NEXT:    mul x10, x11, x10
+; CHECK-NEXT:    mov x11, v3.d[1]
+; CHECK-NEXT:    mov x12, v2.d[1]
+; CHECK-NEXT:    mul x13, x14, x13
+; CHECK-NEXT:    mul x8, x9, x8
+; CHECK-NEXT:    fmov d0, x10
+; CHECK-NEXT:    mul x9, x12, x11
+; CHECK-NEXT:    fmov d1, x13
+; CHECK-NEXT:    movi v2.2d, #0x000000ffffffff
+; CHECK-NEXT:    mov v0.d[1], x8
+; CHECK-NEXT:    mov v1.d[1], x9
+; CHECK-NEXT:    and v1.16b, v1.16b, v2.16b
+; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
+; CHECK-NEXT:    ret
+  %arg1_ext = zext <4 x i32> %arg1 to <4 x i64>
+  %arg2_ext = zext <4 x i32> %arg2 to <4 x i64>
+  %mul = mul <4 x i64> %arg1_ext, %arg2_ext
+  %and = and <4 x i64> %mul, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
+  ret <4 x i64> %and
+}
 
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll b/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
index cb9b36c4c183b..344b047d97b31 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll
@@ -1,58 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
 
 declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>)
-
+declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64) #5
 declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>)
-
 declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)
-
 declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)
-
 declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)
-
 declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)
-
 declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)
-
 declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>)
-
 declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>)
-
 declare <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8>, <8 x i8>)
-
 declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>)
-
 declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>)
-
 declare <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8>, <8 x i8>)
-
 declare <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32>, <2 x i32>)
-
 declare <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16>, <4 x i16>)
-
 declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>)
-
 declare <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32>, <2 x i32>)
-
 declare <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16>, <4 x i16>)
-
 declare <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8>, <8 x i8>)
-
 declare <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64>, <2 x i64>)
-
 declare <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32>, <4 x i32>)
-
 declare <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16>, <8 x i16>)
-
 declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>)
-
 declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>)
-
 declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>)
 
 define <8 x i16> @test_vaddl_s8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vaddl_s8:
-; CHECK: saddl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddl v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <8 x i8> %a to <8 x i16>
   %vmovl.i2.i = sext <8 x i8> %b to <8 x i16>
@@ -62,7 +42,9 @@ entry:
 
 define <4 x i32> @test_vaddl_s16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vaddl_s16:
-; CHECK: saddl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddl v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <4 x i16> %a to <4 x i32>
   %vmovl.i2.i = sext <4 x i16> %b to <4 x i32>
@@ -72,7 +54,9 @@ entry:
 
 define <2 x i64> @test_vaddl_s32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vaddl_s32:
-; CHECK: saddl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddl v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <2 x i32> %a to <2 x i64>
   %vmovl.i2.i = sext <2 x i32> %b to <2 x i64>
@@ -82,7 +66,9 @@ entry:
 
 define <8 x i16> @test_vaddl_u8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vaddl_u8:
-; CHECK: uaddl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddl v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <8 x i8> %a to <8 x i16>
   %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>
@@ -92,7 +78,9 @@ entry:
 
 define <4 x i32> @test_vaddl_u16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vaddl_u16:
-; CHECK: uaddl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddl v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <4 x i16> %a to <4 x i32>
   %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>
@@ -102,7 +90,9 @@ entry:
 
 define <2 x i64> @test_vaddl_u32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vaddl_u32:
-; CHECK: uaddl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddl v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <2 x i32> %a to <2 x i64>
   %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>
@@ -110,9 +100,61 @@ entry:
   ret <2 x i64> %add.i
 }
 
+define <8 x i16> @test_vaddl_a8(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: test_vaddl_a8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
+; CHECK-NEXT:    add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <8 x i8> %a to <8 x i16>
+  %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>
+  %add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i
+  %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @test_vaddl_a16(<4 x i16> %a, <4 x i16> %b) {
+; CHECK-LABEL: test_vaddl_a16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <4 x i16> %a to <4 x i32>
+  %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>
+  %add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i
+  %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @test_vaddl_a32(<2 x i32> %a, <2 x i32> %b) {
+; CHECK-LABEL: test_vaddl_a32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-NEXT:    ushll v1.2d, v1.2s, #0
+; CHECK-NEXT:    add v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <2 x i32> %a to <2 x i64>
+  %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>
+  %add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i
+  %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i16> @test_vaddl_high_s8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vaddl_high_s8:
-; CHECK: saddl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddl2 v0.8h, v0.16b, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %0 = sext <8 x i8> %shuffle.i.i.i to <8 x i16>
@@ -124,7 +166,9 @@ entry:
 
 define <4 x i32> @test_vaddl_high_s16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vaddl_high_s16:
-; CHECK: saddl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddl2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %0 = sext <4 x i16> %shuffle.i.i.i to <4 x i32>
@@ -136,7 +180,9 @@ entry:
 
 define <2 x i64> @test_vaddl_high_s32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vaddl_high_s32:
-; CHECK: saddl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddl2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %0 = sext <2 x i32> %shuffle.i.i.i to <2 x i64>
@@ -148,7 +194,9 @@ entry:
 
 define <8 x i16> @test_vaddl_high_u8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vaddl_high_u8:
-; CHECK: uaddl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddl2 v0.8h, v0.16b, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>
@@ -160,7 +208,9 @@ entry:
 
 define <4 x i32> @test_vaddl_high_u16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vaddl_high_u16:
-; CHECK: uaddl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddl2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
@@ -172,7 +222,9 @@ entry:
 
 define <2 x i64> @test_vaddl_high_u32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vaddl_high_u32:
-; CHECK: uaddl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddl2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
@@ -182,9 +234,67 @@ entry:
   ret <2 x i64> %add.i
 }
 
+define <8 x i16> @test_vaddl_high_a8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vaddl_high_a8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v0.8h, v0.16b, #0
+; CHECK-NEXT:    ushll2 v1.8h, v1.16b, #0
+; CHECK-NEXT:    add v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>
+  %shuffle.i.i2.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %1 = zext <8 x i8> %shuffle.i.i2.i to <8 x i16>
+  %add.i = add <8 x i16> %0, %1
+  %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @test_vaddl_high_a16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vaddl_high_a16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v0.4s, v0.8h, #0
+; CHECK-NEXT:    ushll2 v1.4s, v1.8h, #0
+; CHECK-NEXT:    add v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
+  %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32>
+  %add.i = add <4 x i32> %0, %1
+  %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @test_vaddl_high_a32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vaddl_high_a32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v0.2d, v0.4s, #0
+; CHECK-NEXT:    ushll2 v1.2d, v1.4s, #0
+; CHECK-NEXT:    add v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+  %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
+  %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+  %1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64>
+  %add.i = add <2 x i64> %0, %1
+  %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i16> @test_vaddw_s8(<8 x i16> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vaddw_s8:
-; CHECK: saddw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddw v0.8h, v0.8h, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <8 x i8> %b to <8 x i16>
   %add.i = add <8 x i16> %vmovl.i.i, %a
@@ -193,7 +303,9 @@ entry:
 
 define <4 x i32> @test_vaddw_s16(<4 x i32> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vaddw_s16:
-; CHECK: saddw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddw v0.4s, v0.4s, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <4 x i16> %b to <4 x i32>
   %add.i = add <4 x i32> %vmovl.i.i, %a
@@ -202,7 +314,9 @@ entry:
 
 define <2 x i64> @test_vaddw_s32(<2 x i64> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vaddw_s32:
-; CHECK: saddw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddw v0.2d, v0.2d, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <2 x i32> %b to <2 x i64>
   %add.i = add <2 x i64> %vmovl.i.i, %a
@@ -211,7 +325,9 @@ entry:
 
 define <8 x i16> @test_vaddw_u8(<8 x i16> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vaddw_u8:
-; CHECK: uaddw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddw v0.8h, v0.8h, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <8 x i8> %b to <8 x i16>
   %add.i = add <8 x i16> %vmovl.i.i, %a
@@ -220,7 +336,9 @@ entry:
 
 define <4 x i32> @test_vaddw_u16(<4 x i32> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vaddw_u16:
-; CHECK: uaddw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddw v0.4s, v0.4s, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <4 x i16> %b to <4 x i32>
   %add.i = add <4 x i32> %vmovl.i.i, %a
@@ -229,16 +347,64 @@ entry:
 
 define <2 x i64> @test_vaddw_u32(<2 x i64> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vaddw_u32:
-; CHECK: uaddw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddw v0.2d, v0.2d, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <2 x i32> %b to <2 x i64>
   %add.i = add <2 x i64> %vmovl.i.i, %a
   ret <2 x i64> %add.i
 }
 
+define <8 x i16> @test_vaddw_a8(<8 x i16> %a, <8 x i8> %b) {
+; CHECK-LABEL: test_vaddw_a8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
+; CHECK-NEXT:    add v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <8 x i8> %b to <8 x i16>
+  %add.i = add <8 x i16> %vmovl.i.i, %a
+  %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @test_vaddw_a16(<4 x i32> %a, <4 x i16> %b) {
+; CHECK-LABEL: test_vaddw_a16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:    add v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <4 x i16> %b to <4 x i32>
+  %add.i = add <4 x i32> %vmovl.i.i, %a
+  %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @test_vaddw_a32(<2 x i64> %a, <2 x i32> %b) {
+; CHECK-LABEL: test_vaddw_a32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v1.2d, v1.2s, #0
+; CHECK-NEXT:    add v0.2d, v1.2d, v0.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <2 x i32> %b to <2 x i64>
+  %add.i = add <2 x i64> %vmovl.i.i, %a
+  %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i16> @test_vaddw_high_s8(<8 x i16> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vaddw_high_s8:
-; CHECK: saddw2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddw2 v0.8h, v0.8h, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %0 = sext <8 x i8> %shuffle.i.i.i to <8 x i16>
@@ -248,7 +414,9 @@ entry:
 
 define <4 x i32> @test_vaddw_high_s16(<4 x i32> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vaddw_high_s16:
-; CHECK: saddw2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddw2 v0.4s, v0.4s, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %0 = sext <4 x i16> %shuffle.i.i.i to <4 x i32>
@@ -258,7 +426,9 @@ entry:
 
 define <2 x i64> @test_vaddw_high_s32(<2 x i64> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vaddw_high_s32:
-; CHECK: saddw2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    saddw2 v0.2d, v0.2d, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %0 = sext <2 x i32> %shuffle.i.i.i to <2 x i64>
@@ -268,7 +438,9 @@ entry:
 
 define <8 x i16> @test_vaddw_high_u8(<8 x i16> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vaddw_high_u8:
-; CHECK: uaddw2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddw2 v0.8h, v0.8h, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>
@@ -278,7 +450,9 @@ entry:
 
 define <4 x i32> @test_vaddw_high_u16(<4 x i32> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vaddw_high_u16:
-; CHECK: uaddw2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddw2 v0.4s, v0.4s, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
@@ -288,7 +462,9 @@ entry:
 
 define <2 x i64> @test_vaddw_high_u32(<2 x i64> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vaddw_high_u32:
-; CHECK: uaddw2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uaddw2 v0.2d, v0.2d, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
@@ -296,9 +472,58 @@ entry:
   ret <2 x i64> %add.i
 }
 
+define <8 x i16> @test_vaddw_high_a8(<8 x i16> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vaddw_high_a8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v1.8h, v1.16b, #0
+; CHECK-NEXT:    add v0.8h, v1.8h, v0.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>
+  %add.i = add <8 x i16> %0, %a
+  %and = and <8 x i16> %add.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @test_vaddw_high_a16(<4 x i32> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vaddw_high_a16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v1.4s, v1.8h, #0
+; CHECK-NEXT:    add v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
+  %add.i = add <4 x i32> %0, %a
+  %and = and <4 x i32> %add.i, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @test_vaddw_high_a32(<2 x i64> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vaddw_high_a32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v1.2d, v1.4s, #0
+; CHECK-NEXT:    add v0.2d, v1.2d, v0.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+  %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
+  %add.i = add <2 x i64> %0, %a
+  %and = and <2 x i64> %add.i, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i16> @test_vsubl_s8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vsubl_s8:
-; CHECK: ssubl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubl v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <8 x i8> %a to <8 x i16>
   %vmovl.i2.i = sext <8 x i8> %b to <8 x i16>
@@ -308,7 +533,9 @@ entry:
 
 define <4 x i32> @test_vsubl_s16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vsubl_s16:
-; CHECK: ssubl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubl v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <4 x i16> %a to <4 x i32>
   %vmovl.i2.i = sext <4 x i16> %b to <4 x i32>
@@ -318,7 +545,9 @@ entry:
 
 define <2 x i64> @test_vsubl_s32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vsubl_s32:
-; CHECK: ssubl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubl v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <2 x i32> %a to <2 x i64>
   %vmovl.i2.i = sext <2 x i32> %b to <2 x i64>
@@ -328,7 +557,9 @@ entry:
 
 define <8 x i16> @test_vsubl_u8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vsubl_u8:
-; CHECK: usubl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubl v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <8 x i8> %a to <8 x i16>
   %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>
@@ -338,7 +569,9 @@ entry:
 
 define <4 x i32> @test_vsubl_u16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vsubl_u16:
-; CHECK: usubl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubl v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <4 x i16> %a to <4 x i32>
   %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>
@@ -348,7 +581,9 @@ entry:
 
 define <2 x i64> @test_vsubl_u32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vsubl_u32:
-; CHECK: usubl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubl v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <2 x i32> %a to <2 x i64>
   %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>
@@ -356,9 +591,61 @@ entry:
   ret <2 x i64> %sub.i
 }
 
+define <8 x i16> @test_vsubl_a8(<8 x i8> %a, <8 x i8> %b) {
+; CHECK-LABEL: test_vsubl_a8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
+; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
+; CHECK-NEXT:    sub v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <8 x i8> %a to <8 x i16>
+  %vmovl.i2.i = zext <8 x i8> %b to <8 x i16>
+  %sub.i = sub <8 x i16> %vmovl.i.i, %vmovl.i2.i
+  %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @test_vsubl_a16(<4 x i16> %a, <4 x i16> %b) {
+; CHECK-LABEL: test_vsubl_a16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
+; CHECK-NEXT:    ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <4 x i16> %a to <4 x i32>
+  %vmovl.i2.i = zext <4 x i16> %b to <4 x i32>
+  %sub.i = sub <4 x i32> %vmovl.i.i, %vmovl.i2.i
+  %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @test_vsubl_a32(<2 x i32> %a, <2 x i32> %b) {
+; CHECK-LABEL: test_vsubl_a32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v0.2d, v0.2s, #0
+; CHECK-NEXT:    ushll v1.2d, v1.2s, #0
+; CHECK-NEXT:    sub v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <2 x i32> %a to <2 x i64>
+  %vmovl.i2.i = zext <2 x i32> %b to <2 x i64>
+  %sub.i = sub <2 x i64> %vmovl.i.i, %vmovl.i2.i
+  %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i16> @test_vsubl_high_s8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vsubl_high_s8:
-; CHECK: ssubl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubl2 v0.8h, v0.16b, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %0 = sext <8 x i8> %shuffle.i.i.i to <8 x i16>
@@ -370,7 +657,9 @@ entry:
 
 define <4 x i32> @test_vsubl_high_s16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vsubl_high_s16:
-; CHECK: ssubl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubl2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %0 = sext <4 x i16> %shuffle.i.i.i to <4 x i32>
@@ -382,7 +671,9 @@ entry:
 
 define <2 x i64> @test_vsubl_high_s32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vsubl_high_s32:
-; CHECK: ssubl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubl2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %0 = sext <2 x i32> %shuffle.i.i.i to <2 x i64>
@@ -394,7 +685,9 @@ entry:
 
 define <8 x i16> @test_vsubl_high_u8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vsubl_high_u8:
-; CHECK: usubl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubl2 v0.8h, v0.16b, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>
@@ -406,7 +699,9 @@ entry:
 
 define <4 x i32> @test_vsubl_high_u16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vsubl_high_u16:
-; CHECK: usubl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubl2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
@@ -418,7 +713,9 @@ entry:
 
 define <2 x i64> @test_vsubl_high_u32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vsubl_high_u32:
-; CHECK: usubl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubl2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
@@ -428,9 +725,67 @@ entry:
   ret <2 x i64> %sub.i
 }
 
+define <8 x i16> @test_vsubl_high_a8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsubl_high_a8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v0.8h, v0.16b, #0
+; CHECK-NEXT:    ushll2 v1.8h, v1.16b, #0
+; CHECK-NEXT:    sub v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>
+  %shuffle.i.i2.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %1 = zext <8 x i8> %shuffle.i.i2.i to <8 x i16>
+  %sub.i = sub <8 x i16> %0, %1
+  %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @test_vsubl_high_a16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vsubl_high_a16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v0.4s, v0.8h, #0
+; CHECK-NEXT:    ushll2 v1.4s, v1.8h, #0
+; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
+  %shuffle.i.i2.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %1 = zext <4 x i16> %shuffle.i.i2.i to <4 x i32>
+  %sub.i = sub <4 x i32> %0, %1
+  %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @test_vsubl_high_a32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vsubl_high_a32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v0.2d, v0.4s, #0
+; CHECK-NEXT:    ushll2 v1.2d, v1.4s, #0
+; CHECK-NEXT:    sub v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+  %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
+  %shuffle.i.i2.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+  %1 = zext <2 x i32> %shuffle.i.i2.i to <2 x i64>
+  %sub.i = sub <2 x i64> %0, %1
+  %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i16> @test_vsubw_s8(<8 x i16> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vsubw_s8:
-; CHECK: ssubw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubw v0.8h, v0.8h, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <8 x i8> %b to <8 x i16>
   %sub.i = sub <8 x i16> %a, %vmovl.i.i
@@ -439,7 +794,9 @@ entry:
 
 define <4 x i32> @test_vsubw_s16(<4 x i32> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vsubw_s16:
-; CHECK: ssubw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubw v0.4s, v0.4s, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <4 x i16> %b to <4 x i32>
   %sub.i = sub <4 x i32> %a, %vmovl.i.i
@@ -448,7 +805,9 @@ entry:
 
 define <2 x i64> @test_vsubw_s32(<2 x i64> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vsubw_s32:
-; CHECK: ssubw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubw v0.2d, v0.2d, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = sext <2 x i32> %b to <2 x i64>
   %sub.i = sub <2 x i64> %a, %vmovl.i.i
@@ -457,7 +816,9 @@ entry:
 
 define <8 x i16> @test_vsubw_u8(<8 x i16> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vsubw_u8:
-; CHECK: usubw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubw v0.8h, v0.8h, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <8 x i8> %b to <8 x i16>
   %sub.i = sub <8 x i16> %a, %vmovl.i.i
@@ -466,7 +827,9 @@ entry:
 
 define <4 x i32> @test_vsubw_u16(<4 x i32> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vsubw_u16:
-; CHECK: usubw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubw v0.4s, v0.4s, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <4 x i16> %b to <4 x i32>
   %sub.i = sub <4 x i32> %a, %vmovl.i.i
@@ -475,16 +838,64 @@ entry:
 
 define <2 x i64> @test_vsubw_u32(<2 x i64> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vsubw_u32:
-; CHECK: usubw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubw v0.2d, v0.2d, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmovl.i.i = zext <2 x i32> %b to <2 x i64>
   %sub.i = sub <2 x i64> %a, %vmovl.i.i
   ret <2 x i64> %sub.i
 }
 
+define <8 x i16> @test_vsubw_a8(<8 x i16> %a, <8 x i8> %b) {
+; CHECK-LABEL: test_vsubw_a8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v1.8h, v1.8b, #0
+; CHECK-NEXT:    sub v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <8 x i8> %b to <8 x i16>
+  %sub.i = sub <8 x i16> %a, %vmovl.i.i
+  %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @test_vsubw_a16(<4 x i32> %a, <4 x i16> %b) {
+; CHECK-LABEL: test_vsubw_a16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v1.4s, v1.4h, #0
+; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <4 x i16> %b to <4 x i32>
+  %sub.i = sub <4 x i32> %a, %vmovl.i.i
+  %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @test_vsubw_a32(<2 x i64> %a, <2 x i32> %b) {
+; CHECK-LABEL: test_vsubw_a32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll v1.2d, v1.2s, #0
+; CHECK-NEXT:    sub v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %vmovl.i.i = zext <2 x i32> %b to <2 x i64>
+  %sub.i = sub <2 x i64> %a, %vmovl.i.i
+  %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i16> @test_vsubw_high_s8(<8 x i16> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vsubw_high_s8:
-; CHECK: ssubw2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubw2 v0.8h, v0.8h, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %0 = sext <8 x i8> %shuffle.i.i.i to <8 x i16>
@@ -494,7 +905,9 @@ entry:
 
 define <4 x i32> @test_vsubw_high_s16(<4 x i32> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vsubw_high_s16:
-; CHECK: ssubw2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubw2 v0.4s, v0.4s, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %0 = sext <4 x i16> %shuffle.i.i.i to <4 x i32>
@@ -504,7 +917,9 @@ entry:
 
 define <2 x i64> @test_vsubw_high_s32(<2 x i64> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vsubw_high_s32:
-; CHECK: ssubw2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ssubw2 v0.2d, v0.2d, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %0 = sext <2 x i32> %shuffle.i.i.i to <2 x i64>
@@ -514,7 +929,9 @@ entry:
 
 define <8 x i16> @test_vsubw_high_u8(<8 x i16> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vsubw_high_u8:
-; CHECK: usubw2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubw2 v0.8h, v0.8h, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>
@@ -524,7 +941,9 @@ entry:
 
 define <4 x i32> @test_vsubw_high_u16(<4 x i32> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vsubw_high_u16:
-; CHECK: usubw2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubw2 v0.4s, v0.4s, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
@@ -534,7 +953,9 @@ entry:
 
 define <2 x i64> @test_vsubw_high_u32(<2 x i64> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vsubw_high_u32:
-; CHECK: usubw2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    usubw2 v0.2d, v0.2d, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
@@ -542,9 +963,58 @@ entry:
   ret <2 x i64> %sub.i
 }
 
+define <8 x i16> @test_vsubw_high_a8(<8 x i16> %a, <16 x i8> %b) {
+; CHECK-LABEL: test_vsubw_high_a8:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v1.8h, v1.16b, #0
+; CHECK-NEXT:    sub v0.8h, v0.8h, v1.8h
+; CHECK-NEXT:    bic v0.8h, #255, lsl #8
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %0 = zext <8 x i8> %shuffle.i.i.i to <8 x i16>
+  %sub.i = sub <8 x i16> %a, %0
+  %and = and <8 x i16> %sub.i, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @test_vsubw_high_a16(<4 x i32> %a, <8 x i16> %b) {
+; CHECK-LABEL: test_vsubw_high_a16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v1.4s, v1.8h, #0
+; CHECK-NEXT:    sub v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    movi v1.2d, #0x00ffff0000ffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %0 = zext <4 x i16> %shuffle.i.i.i to <4 x i32>
+  %sub.i = sub <4 x i32> %a, %0
+  %and = and <4 x i32> %sub.i, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @test_vsubw_high_a32(<2 x i64> %a, <4 x i32> %b) {
+; CHECK-LABEL: test_vsubw_high_a32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ushll2 v1.2d, v1.4s, #0
+; CHECK-NEXT:    sub v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    movi v1.2d, #0x000000ffffffff
+; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    ret
+entry:
+  %shuffle.i.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
+  %0 = zext <2 x i32> %shuffle.i.i.i to <2 x i64>
+  %sub.i = sub <2 x i64> %a, %0
+  %and = and <2 x i64> %sub.i, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 define <8 x i8> @test_vaddhn_s16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vaddhn_s16:
-; CHECK: addhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    addhn v0.8b, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i = add <8 x i16> %a, %b
   %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -554,7 +1024,9 @@ entry:
 
 define <4 x i16> @test_vaddhn_s32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vaddhn_s32:
-; CHECK: addhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    addhn v0.4h, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i = add <4 x i32> %a, %b
   %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>
@@ -564,7 +1036,9 @@ entry:
 
 define <2 x i32> @test_vaddhn_s64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vaddhn_s64:
-; CHECK: addhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    addhn v0.2s, v0.2d, v1.2d
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i = add <2 x i64> %a, %b
   %vaddhn1.i = lshr <2 x i64> %vaddhn.i, <i64 32, i64 32>
@@ -574,7 +1048,9 @@ entry:
 
 define <8 x i8> @test_vaddhn_u16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vaddhn_u16:
-; CHECK: addhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    addhn v0.8b, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i = add <8 x i16> %a, %b
   %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -584,7 +1060,9 @@ entry:
 
 define <4 x i16> @test_vaddhn_u32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vaddhn_u32:
-; CHECK: addhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    addhn v0.4h, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i = add <4 x i32> %a, %b
   %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>
@@ -594,7 +1072,9 @@ entry:
 
 define <2 x i32> @test_vaddhn_u64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vaddhn_u64:
-; CHECK: addhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    addhn v0.2s, v0.2d, v1.2d
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i = add <2 x i64> %a, %b
   %vaddhn1.i = lshr <2 x i64> %vaddhn.i, <i64 32, i64 32>
@@ -604,7 +1084,10 @@ entry:
 
 define <16 x i8> @test_vaddhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vaddhn_high_s16:
-; CHECK: addhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    addhn2 v0.16b, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i.i = add <8 x i16> %a, %b
   %vaddhn1.i.i = lshr <8 x i16> %vaddhn.i.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -618,7 +1101,10 @@ entry:
 
 define <8 x i16> @test_vaddhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vaddhn_high_s32:
-; CHECK: addhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    addhn2 v0.8h, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i.i = add <4 x i32> %a, %b
   %vaddhn1.i.i = lshr <4 x i32> %vaddhn.i.i, <i32 16, i32 16, i32 16, i32 16>
@@ -632,7 +1118,10 @@ entry:
 
 define <4 x i32> @test_vaddhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vaddhn_high_s64:
-; CHECK: addhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    addhn2 v0.4s, v1.2d, v2.2d
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i.i = add <2 x i64> %a, %b
   %vaddhn1.i.i = lshr <2 x i64> %vaddhn.i.i, <i64 32, i64 32>
@@ -646,7 +1135,10 @@ entry:
 
 define <16 x i8> @test_vaddhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vaddhn_high_u16:
-; CHECK: addhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    addhn2 v0.16b, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i.i = add <8 x i16> %a, %b
   %vaddhn1.i.i = lshr <8 x i16> %vaddhn.i.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -660,7 +1152,10 @@ entry:
 
 define <8 x i16> @test_vaddhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vaddhn_high_u32:
-; CHECK: addhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    addhn2 v0.8h, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i.i = add <4 x i32> %a, %b
   %vaddhn1.i.i = lshr <4 x i32> %vaddhn.i.i, <i32 16, i32 16, i32 16, i32 16>
@@ -674,7 +1169,10 @@ entry:
 
 define <4 x i32> @test_vaddhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vaddhn_high_u64:
-; CHECK: addhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    addhn2 v0.4s, v1.2d, v2.2d
+; CHECK-NEXT:    ret
 entry:
   %vaddhn.i.i = add <2 x i64> %a, %b
   %vaddhn1.i.i = lshr <2 x i64> %vaddhn.i.i, <i64 32, i64 32>
@@ -688,7 +1186,9 @@ entry:
 
 define <8 x i8> @test_vraddhn_s16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vraddhn_s16:
-; CHECK: raddhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    raddhn v0.8b, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)
   ret <8 x i8> %vraddhn2.i
@@ -696,7 +1196,9 @@ entry:
 
 define <4 x i16> @test_vraddhn_s32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vraddhn_s32:
-; CHECK: raddhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    raddhn v0.4h, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)
   ret <4 x i16> %vraddhn2.i
@@ -704,7 +1206,9 @@ entry:
 
 define <2 x i32> @test_vraddhn_s64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vraddhn_s64:
-; CHECK: raddhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    raddhn v0.2s, v0.2d, v1.2d
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i32> %vraddhn2.i
@@ -712,7 +1216,9 @@ entry:
 
 define <8 x i8> @test_vraddhn_u16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vraddhn_u16:
-; CHECK: raddhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    raddhn v0.8b, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)
   ret <8 x i8> %vraddhn2.i
@@ -720,7 +1226,9 @@ entry:
 
 define <4 x i16> @test_vraddhn_u32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vraddhn_u32:
-; CHECK: raddhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    raddhn v0.4h, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)
   ret <4 x i16> %vraddhn2.i
@@ -728,7 +1236,9 @@ entry:
 
 define <2 x i32> @test_vraddhn_u64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vraddhn_u64:
-; CHECK: raddhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    raddhn v0.2s, v0.2d, v1.2d
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i32> %vraddhn2.i
@@ -736,7 +1246,10 @@ entry:
 
 define <16 x i8> @test_vraddhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vraddhn_high_s16:
-; CHECK: raddhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    raddhn2 v0.16b, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)
   %0 = bitcast <8 x i8> %r to <1 x i64>
@@ -748,7 +1261,10 @@ entry:
 
 define <8 x i16> @test_vraddhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vraddhn_high_s32:
-; CHECK: raddhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    raddhn2 v0.8h, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)
   %0 = bitcast <4 x i16> %r to <1 x i64>
@@ -760,7 +1276,10 @@ entry:
 
 define <4 x i32> @test_vraddhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vraddhn_high_s64:
-; CHECK: raddhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    raddhn2 v0.4s, v1.2d, v2.2d
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)
   %0 = bitcast <2 x i32> %r to <1 x i64>
@@ -772,7 +1291,10 @@ entry:
 
 define <16 x i8> @test_vraddhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vraddhn_high_u16:
-; CHECK: raddhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    raddhn2 v0.16b, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b)
   %0 = bitcast <8 x i8> %r to <1 x i64>
@@ -784,7 +1306,10 @@ entry:
 
 define <8 x i16> @test_vraddhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vraddhn_high_u32:
-; CHECK: raddhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    raddhn2 v0.8h, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b)
   %0 = bitcast <4 x i16> %r to <1 x i64>
@@ -796,7 +1321,10 @@ entry:
 
 define <4 x i32> @test_vraddhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vraddhn_high_u64:
-; CHECK: raddhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    raddhn2 v0.4s, v1.2d, v2.2d
+; CHECK-NEXT:    ret
 entry:
   %vraddhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b)
   %0 = bitcast <2 x i32> %r to <1 x i64>
@@ -808,7 +1336,9 @@ entry:
 
 define <8 x i8> @test_vsubhn_s16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vsubhn_s16:
-; CHECK: subhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    subhn v0.8b, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i = sub <8 x i16> %a, %b
   %vsubhn1.i = lshr <8 x i16> %vsubhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -818,7 +1348,9 @@ entry:
 
 define <4 x i16> @test_vsubhn_s32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vsubhn_s32:
-; CHECK: subhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    subhn v0.4h, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i = sub <4 x i32> %a, %b
   %vsubhn1.i = lshr <4 x i32> %vsubhn.i, <i32 16, i32 16, i32 16, i32 16>
@@ -828,7 +1360,9 @@ entry:
 
 define <2 x i32> @test_vsubhn_s64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vsubhn_s64:
-; CHECK: subhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    subhn v0.2s, v0.2d, v1.2d
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i = sub <2 x i64> %a, %b
   %vsubhn1.i = lshr <2 x i64> %vsubhn.i, <i64 32, i64 32>
@@ -838,7 +1372,9 @@ entry:
 
 define <8 x i8> @test_vsubhn_u16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vsubhn_u16:
-; CHECK: subhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    subhn v0.8b, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i = sub <8 x i16> %a, %b
   %vsubhn1.i = lshr <8 x i16> %vsubhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -848,7 +1384,9 @@ entry:
 
 define <4 x i16> @test_vsubhn_u32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vsubhn_u32:
-; CHECK: subhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    subhn v0.4h, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i = sub <4 x i32> %a, %b
   %vsubhn1.i = lshr <4 x i32> %vsubhn.i, <i32 16, i32 16, i32 16, i32 16>
@@ -858,7 +1396,9 @@ entry:
 
 define <2 x i32> @test_vsubhn_u64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vsubhn_u64:
-; CHECK: subhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    subhn v0.2s, v0.2d, v1.2d
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i = sub <2 x i64> %a, %b
   %vsubhn1.i = lshr <2 x i64> %vsubhn.i, <i64 32, i64 32>
@@ -868,7 +1408,10 @@ entry:
 
 define <16 x i8> @test_vsubhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vsubhn_high_s16:
-; CHECK: subhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    subhn2 v0.16b, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i.i = sub <8 x i16> %a, %b
   %vsubhn1.i.i = lshr <8 x i16> %vsubhn.i.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -882,7 +1425,10 @@ entry:
 
 define <8 x i16> @test_vsubhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vsubhn_high_s32:
-; CHECK: subhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    subhn2 v0.8h, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i.i = sub <4 x i32> %a, %b
   %vsubhn1.i.i = lshr <4 x i32> %vsubhn.i.i, <i32 16, i32 16, i32 16, i32 16>
@@ -896,7 +1442,10 @@ entry:
 
 define <4 x i32> @test_vsubhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vsubhn_high_s64:
-; CHECK: subhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    subhn2 v0.4s, v1.2d, v2.2d
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i.i = sub <2 x i64> %a, %b
   %vsubhn1.i.i = lshr <2 x i64> %vsubhn.i.i, <i64 32, i64 32>
@@ -910,7 +1459,10 @@ entry:
 
 define <16 x i8> @test_vsubhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vsubhn_high_u16:
-; CHECK: subhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    subhn2 v0.16b, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i.i = sub <8 x i16> %a, %b
   %vsubhn1.i.i = lshr <8 x i16> %vsubhn.i.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
@@ -924,7 +1476,10 @@ entry:
 
 define <8 x i16> @test_vsubhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vsubhn_high_u32:
-; CHECK: subhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    subhn2 v0.8h, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i.i = sub <4 x i32> %a, %b
   %vsubhn1.i.i = lshr <4 x i32> %vsubhn.i.i, <i32 16, i32 16, i32 16, i32 16>
@@ -938,7 +1493,10 @@ entry:
 
 define <4 x i32> @test_vsubhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vsubhn_high_u64:
-; CHECK: subhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    subhn2 v0.4s, v1.2d, v2.2d
+; CHECK-NEXT:    ret
 entry:
   %vsubhn.i.i = sub <2 x i64> %a, %b
   %vsubhn1.i.i = lshr <2 x i64> %vsubhn.i.i, <i64 32, i64 32>
@@ -952,7 +1510,9 @@ entry:
 
 define <8 x i8> @test_vrsubhn_s16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vrsubhn_s16:
-; CHECK: rsubhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rsubhn v0.8b, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)
   ret <8 x i8> %vrsubhn2.i
@@ -960,7 +1520,9 @@ entry:
 
 define <4 x i16> @test_vrsubhn_s32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vrsubhn_s32:
-; CHECK: rsubhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rsubhn v0.4h, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)
   ret <4 x i16> %vrsubhn2.i
@@ -968,7 +1530,9 @@ entry:
 
 define <2 x i32> @test_vrsubhn_s64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vrsubhn_s64:
-; CHECK: rsubhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rsubhn v0.2s, v0.2d, v1.2d
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i32> %vrsubhn2.i
@@ -976,7 +1540,9 @@ entry:
 
 define <8 x i8> @test_vrsubhn_u16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vrsubhn_u16:
-; CHECK: rsubhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rsubhn v0.8b, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)
   ret <8 x i8> %vrsubhn2.i
@@ -984,7 +1550,9 @@ entry:
 
 define <4 x i16> @test_vrsubhn_u32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vrsubhn_u32:
-; CHECK: rsubhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rsubhn v0.4h, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)
   ret <4 x i16> %vrsubhn2.i
@@ -992,7 +1560,9 @@ entry:
 
 define <2 x i32> @test_vrsubhn_u64(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vrsubhn_u64:
-; CHECK: rsubhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rsubhn v0.2s, v0.2d, v1.2d
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)
   ret <2 x i32> %vrsubhn2.i
@@ -1000,7 +1570,10 @@ entry:
 
 define <16 x i8> @test_vrsubhn_high_s16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vrsubhn_high_s16:
-; CHECK: rsubhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    rsubhn2 v0.16b, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)
   %0 = bitcast <8 x i8> %r to <1 x i64>
@@ -1012,7 +1585,10 @@ entry:
 
 define <8 x i16> @test_vrsubhn_high_s32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vrsubhn_high_s32:
-; CHECK: rsubhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    rsubhn2 v0.8h, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)
   %0 = bitcast <4 x i16> %r to <1 x i64>
@@ -1024,7 +1600,10 @@ entry:
 
 define <4 x i32> @test_vrsubhn_high_s64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vrsubhn_high_s64:
-; CHECK: rsubhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    rsubhn2 v0.4s, v1.2d, v2.2d
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)
   %0 = bitcast <2 x i32> %r to <1 x i64>
@@ -1036,7 +1615,10 @@ entry:
 
 define <16 x i8> @test_vrsubhn_high_u16(<8 x i8> %r, <8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vrsubhn_high_u16:
-; CHECK: rsubhn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    rsubhn2 v0.16b, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i.i = tail call <8 x i8> @llvm.aarch64.neon.rsubhn.v8i8(<8 x i16> %a, <8 x i16> %b)
   %0 = bitcast <8 x i8> %r to <1 x i64>
@@ -1048,7 +1630,10 @@ entry:
 
 define <8 x i16> @test_vrsubhn_high_u32(<4 x i16> %r, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vrsubhn_high_u32:
-; CHECK: rsubhn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    rsubhn2 v0.8h, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i.i = tail call <4 x i16> @llvm.aarch64.neon.rsubhn.v4i16(<4 x i32> %a, <4 x i32> %b)
   %0 = bitcast <4 x i16> %r to <1 x i64>
@@ -1060,7 +1645,10 @@ entry:
 
 define <4 x i32> @test_vrsubhn_high_u64(<2 x i32> %r, <2 x i64> %a, <2 x i64> %b) {
 ; CHECK-LABEL: test_vrsubhn_high_u64:
-; CHECK: rsubhn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    rsubhn2 v0.4s, v1.2d, v2.2d
+; CHECK-NEXT:    ret
 entry:
   %vrsubhn2.i.i = tail call <2 x i32> @llvm.aarch64.neon.rsubhn.v2i32(<2 x i64> %a, <2 x i64> %b)
   %0 = bitcast <2 x i32> %r to <1 x i64>
@@ -1072,7 +1660,9 @@ entry:
 
 define <8 x i16> @test_vabdl_s8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vabdl_s8:
-; CHECK: sabdl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabdl v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vabd.i.i = tail call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %a, <8 x i8> %b)
   %vmovl.i.i = zext <8 x i8> %vabd.i.i to <8 x i16>
@@ -1081,7 +1671,9 @@ entry:
 
 define <4 x i32> @test_vabdl_s16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vabdl_s16:
-; CHECK: sabdl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabdl v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vabd2.i.i = tail call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %a, <4 x i16> %b)
   %vmovl.i.i = zext <4 x i16> %vabd2.i.i to <4 x i32>
@@ -1090,7 +1682,9 @@ entry:
 
 define <2 x i64> @test_vabdl_s32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vabdl_s32:
-; CHECK: sabdl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabdl v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vabd2.i.i = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %a, <2 x i32> %b)
   %vmovl.i.i = zext <2 x i32> %vabd2.i.i to <2 x i64>
@@ -1099,7 +1693,9 @@ entry:
 
 define <8 x i16> @test_vabdl_u8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vabdl_u8:
-; CHECK: uabdl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabdl v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vabd.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %a, <8 x i8> %b)
   %vmovl.i.i = zext <8 x i8> %vabd.i.i to <8 x i16>
@@ -1108,7 +1704,9 @@ entry:
 
 define <4 x i32> @test_vabdl_u16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vabdl_u16:
-; CHECK: uabdl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabdl v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vabd2.i.i = tail call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %a, <4 x i16> %b)
   %vmovl.i.i = zext <4 x i16> %vabd2.i.i to <4 x i32>
@@ -1117,7 +1715,9 @@ entry:
 
 define <2 x i64> @test_vabdl_u32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vabdl_u32:
-; CHECK: uabdl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabdl v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vabd2.i.i = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %a, <2 x i32> %b)
   %vmovl.i.i = zext <2 x i32> %vabd2.i.i to <2 x i64>
@@ -1126,7 +1726,9 @@ entry:
 
 define <8 x i16> @test_vabal_s8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {
 ; CHECK-LABEL: test_vabal_s8:
-; CHECK: sabal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabal v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
 entry:
   %vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %b, <8 x i8> %c)
   %vmovl.i.i.i = zext <8 x i8> %vabd.i.i.i to <8 x i16>
@@ -1136,7 +1738,9 @@ entry:
 
 define <4 x i32> @test_vabal_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {
 ; CHECK-LABEL: test_vabal_s16:
-; CHECK: sabal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabal v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
 entry:
   %vabd2.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %b, <4 x i16> %c)
   %vmovl.i.i.i = zext <4 x i16> %vabd2.i.i.i to <4 x i32>
@@ -1146,7 +1750,9 @@ entry:
 
 define <2 x i64> @test_vabal_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
 ; CHECK-LABEL: test_vabal_s32:
-; CHECK: sabal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabal v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
 entry:
   %vabd2.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %b, <2 x i32> %c)
   %vmovl.i.i.i = zext <2 x i32> %vabd2.i.i.i to <2 x i64>
@@ -1156,7 +1762,9 @@ entry:
 
 define <8 x i16> @test_vabal_u8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {
 ; CHECK-LABEL: test_vabal_u8:
-; CHECK: uabal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabal v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
 entry:
   %vabd.i.i.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %b, <8 x i8> %c)
   %vmovl.i.i.i = zext <8 x i8> %vabd.i.i.i to <8 x i16>
@@ -1166,7 +1774,9 @@ entry:
 
 define <4 x i32> @test_vabal_u16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {
 ; CHECK-LABEL: test_vabal_u16:
-; CHECK: uabal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabal v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
 entry:
   %vabd2.i.i.i = tail call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %b, <4 x i16> %c)
   %vmovl.i.i.i = zext <4 x i16> %vabd2.i.i.i to <4 x i32>
@@ -1176,7 +1786,9 @@ entry:
 
 define <2 x i64> @test_vabal_u32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
 ; CHECK-LABEL: test_vabal_u32:
-; CHECK: uabal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabal v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
 entry:
   %vabd2.i.i.i = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %b, <2 x i32> %c)
   %vmovl.i.i.i = zext <2 x i32> %vabd2.i.i.i to <2 x i64>
@@ -1186,7 +1798,9 @@ entry:
 
 define <8 x i16> @test_vabdl_high_s8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vabdl_high_s8:
-; CHECK: sabdl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabdl2 v0.8h, v0.16b, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1197,7 +1811,9 @@ entry:
 
 define <4 x i32> @test_vabdl_high_s16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vabdl_high_s16:
-; CHECK: sabdl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabdl2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1208,7 +1824,9 @@ entry:
 
 define <2 x i64> @test_vabdl_high_s32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vabdl_high_s32:
-; CHECK: sabdl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabdl2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1219,7 +1837,9 @@ entry:
 
 define <8 x i16> @test_vabdl_high_u8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vabdl_high_u8:
-; CHECK: uabdl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabdl2 v0.8h, v0.16b, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1230,7 +1850,9 @@ entry:
 
 define <4 x i32> @test_vabdl_high_u16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vabdl_high_u16:
-; CHECK: uabdl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabdl2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1241,7 +1863,9 @@ entry:
 
 define <2 x i64> @test_vabdl_high_u32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vabdl_high_u32:
-; CHECK: uabdl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabdl2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1252,7 +1876,9 @@ entry:
 
 define <8 x i16> @test_vabal_high_s8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vabal_high_s8:
-; CHECK: sabal2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabal2 v0.8h, v1.16b, v2.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1264,7 +1890,9 @@ entry:
 
 define <4 x i32> @test_vabal_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {
 ; CHECK-LABEL: test_vabal_high_s16:
-; CHECK: sabal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1276,7 +1904,9 @@ entry:
 
 define <2 x i64> @test_vabal_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: test_vabal_high_s32:
-; CHECK: sabal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sabal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1288,7 +1918,9 @@ entry:
 
 define <8 x i16> @test_vabal_high_u8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vabal_high_u8:
-; CHECK: uabal2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabal2 v0.8h, v1.16b, v2.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1300,7 +1932,9 @@ entry:
 
 define <4 x i32> @test_vabal_high_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {
 ; CHECK-LABEL: test_vabal_high_u16:
-; CHECK: uabal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1312,7 +1946,9 @@ entry:
 
 define <2 x i64> @test_vabal_high_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: test_vabal_high_u32:
-; CHECK: uabal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    uabal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1324,7 +1960,9 @@ entry:
 
 define <8 x i16> @test_vmull_s8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vmull_s8:
-; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %a, <8 x i8> %b)
   ret <8 x i16> %vmull.i
@@ -1332,7 +1970,9 @@ entry:
 
 define <4 x i32> @test_vmull_s16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vmull_s16:
-; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %a, <4 x i16> %b)
   ret <4 x i32> %vmull2.i
@@ -1340,7 +1980,9 @@ entry:
 
 define <2 x i64> @test_vmull_s32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vmull_s32:
-; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %a, <2 x i32> %b)
   ret <2 x i64> %vmull2.i
@@ -1348,7 +1990,9 @@ entry:
 
 define <8 x i16> @test_vmull_u8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vmull_u8:
-; CHECK: umull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %a, <8 x i8> %b)
   ret <8 x i16> %vmull.i
@@ -1356,7 +2000,9 @@ entry:
 
 define <4 x i32> @test_vmull_u16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vmull_u16:
-; CHECK: umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %a, <4 x i16> %b)
   ret <4 x i32> %vmull2.i
@@ -1364,7 +2010,9 @@ entry:
 
 define <2 x i64> @test_vmull_u32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vmull_u32:
-; CHECK: umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umull v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %a, <2 x i32> %b)
   ret <2 x i64> %vmull2.i
@@ -1372,7 +2020,9 @@ entry:
 
 define <8 x i16> @test_vmull_high_s8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vmull_high_s8:
-; CHECK: smull2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull2 v0.8h, v0.16b, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1382,7 +2032,9 @@ entry:
 
 define <4 x i32> @test_vmull_high_s16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vmull_high_s16:
-; CHECK: smull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1392,7 +2044,9 @@ entry:
 
 define <2 x i64> @test_vmull_high_s32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vmull_high_s32:
-; CHECK: smull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1402,7 +2056,9 @@ entry:
 
 define <8 x i16> @test_vmull_high_u8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vmull_high_u8:
-; CHECK: umull2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umull2 v0.8h, v0.16b, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1412,7 +2068,9 @@ entry:
 
 define <4 x i32> @test_vmull_high_u16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vmull_high_u16:
-; CHECK: umull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umull2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1422,7 +2080,9 @@ entry:
 
 define <2 x i64> @test_vmull_high_u32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vmull_high_u32:
-; CHECK: umull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umull2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1432,7 +2092,9 @@ entry:
 
 define <8 x i16> @test_vmlal_s8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {
 ; CHECK-LABEL: test_vmlal_s8:
-; CHECK: smlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlal v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
 entry:
   %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %b, <8 x i8> %c)
   %add.i = add <8 x i16> %vmull.i.i, %a
@@ -1441,7 +2103,9 @@ entry:
 
 define <4 x i32> @test_vmlal_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {
 ; CHECK-LABEL: test_vmlal_s16:
-; CHECK: smlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlal v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %b, <4 x i16> %c)
   %add.i = add <4 x i32> %vmull2.i.i, %a
@@ -1450,7 +2114,9 @@ entry:
 
 define <2 x i64> @test_vmlal_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
 ; CHECK-LABEL: test_vmlal_s32:
-; CHECK: smlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlal v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %b, <2 x i32> %c)
   %add.i = add <2 x i64> %vmull2.i.i, %a
@@ -1459,7 +2125,9 @@ entry:
 
 define <8 x i16> @test_vmlal_u8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {
 ; CHECK-LABEL: test_vmlal_u8:
-; CHECK: umlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlal v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
 entry:
   %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %b, <8 x i8> %c)
   %add.i = add <8 x i16> %vmull.i.i, %a
@@ -1468,7 +2136,9 @@ entry:
 
 define <4 x i32> @test_vmlal_u16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {
 ; CHECK-LABEL: test_vmlal_u16:
-; CHECK: umlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlal v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %b, <4 x i16> %c)
   %add.i = add <4 x i32> %vmull2.i.i, %a
@@ -1477,7 +2147,9 @@ entry:
 
 define <2 x i64> @test_vmlal_u32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
 ; CHECK-LABEL: test_vmlal_u32:
-; CHECK: umlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlal v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %b, <2 x i32> %c)
   %add.i = add <2 x i64> %vmull2.i.i, %a
@@ -1486,7 +2158,9 @@ entry:
 
 define <8 x i16> @test_vmlal_high_s8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vmlal_high_s8:
-; CHECK: smlal2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlal2 v0.8h, v1.16b, v2.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1497,7 +2171,9 @@ entry:
 
 define <4 x i32> @test_vmlal_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {
 ; CHECK-LABEL: test_vmlal_high_s16:
-; CHECK: smlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1508,7 +2184,9 @@ entry:
 
 define <2 x i64> @test_vmlal_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: test_vmlal_high_s32:
-; CHECK: smlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1519,7 +2197,9 @@ entry:
 
 define <8 x i16> @test_vmlal_high_u8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vmlal_high_u8:
-; CHECK: umlal2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlal2 v0.8h, v1.16b, v2.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1530,7 +2210,9 @@ entry:
 
 define <4 x i32> @test_vmlal_high_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {
 ; CHECK-LABEL: test_vmlal_high_u16:
-; CHECK: umlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1541,7 +2223,9 @@ entry:
 
 define <2 x i64> @test_vmlal_high_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: test_vmlal_high_u32:
-; CHECK: umlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1552,7 +2236,9 @@ entry:
 
 define <8 x i16> @test_vmlsl_s8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {
 ; CHECK-LABEL: test_vmlsl_s8:
-; CHECK: smlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlsl v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
 entry:
   %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %b, <8 x i8> %c)
   %sub.i = sub <8 x i16> %a, %vmull.i.i
@@ -1561,7 +2247,9 @@ entry:
 
 define <4 x i32> @test_vmlsl_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {
 ; CHECK-LABEL: test_vmlsl_s16:
-; CHECK: smlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlsl v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %b, <4 x i16> %c)
   %sub.i = sub <4 x i32> %a, %vmull2.i.i
@@ -1570,7 +2258,9 @@ entry:
 
 define <2 x i64> @test_vmlsl_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
 ; CHECK-LABEL: test_vmlsl_s32:
-; CHECK: smlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlsl v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %b, <2 x i32> %c)
   %sub.i = sub <2 x i64> %a, %vmull2.i.i
@@ -1579,7 +2269,9 @@ entry:
 
 define <8 x i16> @test_vmlsl_u8(<8 x i16> %a, <8 x i8> %b, <8 x i8> %c) {
 ; CHECK-LABEL: test_vmlsl_u8:
-; CHECK: umlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlsl v0.8h, v1.8b, v2.8b
+; CHECK-NEXT:    ret
 entry:
   %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %b, <8 x i8> %c)
   %sub.i = sub <8 x i16> %a, %vmull.i.i
@@ -1588,7 +2280,9 @@ entry:
 
 define <4 x i32> @test_vmlsl_u16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {
 ; CHECK-LABEL: test_vmlsl_u16:
-; CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlsl v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %b, <4 x i16> %c)
   %sub.i = sub <4 x i32> %a, %vmull2.i.i
@@ -1597,7 +2291,9 @@ entry:
 
 define <2 x i64> @test_vmlsl_u32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
 ; CHECK-LABEL: test_vmlsl_u32:
-; CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlsl v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %b, <2 x i32> %c)
   %sub.i = sub <2 x i64> %a, %vmull2.i.i
@@ -1606,7 +2302,9 @@ entry:
 
 define <8 x i16> @test_vmlsl_high_s8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vmlsl_high_s8:
-; CHECK: smlsl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlsl2 v0.8h, v1.16b, v2.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1617,7 +2315,9 @@ entry:
 
 define <4 x i32> @test_vmlsl_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {
 ; CHECK-LABEL: test_vmlsl_high_s16:
-; CHECK: smlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1628,7 +2328,9 @@ entry:
 
 define <2 x i64> @test_vmlsl_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: test_vmlsl_high_s32:
-; CHECK: smlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1639,7 +2341,9 @@ entry:
 
 define <8 x i16> @test_vmlsl_high_u8(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) {
 ; CHECK-LABEL: test_vmlsl_high_u8:
-; CHECK: umlsl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlsl2 v0.8h, v1.16b, v2.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %c, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1650,7 +2354,9 @@ entry:
 
 define <4 x i32> @test_vmlsl_high_u16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {
 ; CHECK-LABEL: test_vmlsl_high_u16:
-; CHECK: umlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1661,7 +2367,9 @@ entry:
 
 define <2 x i64> @test_vmlsl_high_u32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: test_vmlsl_high_u32:
-; CHECK: umlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1672,7 +2380,9 @@ entry:
 
 define <4 x i32> @test_vqdmull_s16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: test_vqdmull_s16:
-; CHECK: sqdmull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmull v0.4s, v0.4h, v1.4h
+; CHECK-NEXT:    ret
 entry:
   %vqdmull2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %a, <4 x i16> %b)
   ret <4 x i32> %vqdmull2.i
@@ -1680,7 +2390,9 @@ entry:
 
 define <2 x i64> @test_vqdmull_s32(<2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: test_vqdmull_s32:
-; CHECK: sqdmull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmull v0.2d, v0.2s, v1.2s
+; CHECK-NEXT:    ret
 entry:
   %vqdmull2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %a, <2 x i32> %b)
   ret <2 x i64> %vqdmull2.i
@@ -1688,7 +2400,9 @@ entry:
 
 define <4 x i32> @test_vqdmlal_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {
 ; CHECK-LABEL: test_vqdmlal_s16:
-; CHECK: sqdmlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmlal v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
 entry:
   %vqdmlal2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %c)
   %vqdmlal4.i = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %a, <4 x i32> %vqdmlal2.i)
@@ -1697,7 +2411,9 @@ entry:
 
 define <2 x i64> @test_vqdmlal_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
 ; CHECK-LABEL: test_vqdmlal_s32:
-; CHECK: sqdmlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmlal v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
 entry:
   %vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %c)
   %vqdmlal4.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %a, <2 x i64> %vqdmlal2.i)
@@ -1706,7 +2422,9 @@ entry:
 
 define <4 x i32> @test_vqdmlsl_s16(<4 x i32> %a, <4 x i16> %b, <4 x i16> %c) {
 ; CHECK-LABEL: test_vqdmlsl_s16:
-; CHECK: sqdmlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmlsl v0.4s, v1.4h, v2.4h
+; CHECK-NEXT:    ret
 entry:
   %vqdmlsl2.i = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %b, <4 x i16> %c)
   %vqdmlsl4.i = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %a, <4 x i32> %vqdmlsl2.i)
@@ -1715,7 +2433,9 @@ entry:
 
 define <2 x i64> @test_vqdmlsl_s32(<2 x i64> %a, <2 x i32> %b, <2 x i32> %c) {
 ; CHECK-LABEL: test_vqdmlsl_s32:
-; CHECK: sqdmlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmlsl v0.2d, v1.2s, v2.2s
+; CHECK-NEXT:    ret
 entry:
   %vqdmlsl2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %b, <2 x i32> %c)
   %vqdmlsl4.i = tail call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %a, <2 x i64> %vqdmlsl2.i)
@@ -1724,7 +2444,9 @@ entry:
 
 define <4 x i32> @test_vqdmull_high_s16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: test_vqdmull_high_s16:
-; CHECK: sqdmull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmull2 v0.4s, v0.8h, v1.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1734,7 +2456,9 @@ entry:
 
 define <2 x i64> @test_vqdmull_high_s32(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: test_vqdmull_high_s32:
-; CHECK: sqdmull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmull2 v0.2d, v0.4s, v1.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1744,7 +2468,9 @@ entry:
 
 define <4 x i32> @test_vqdmlal_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {
 ; CHECK-LABEL: test_vqdmlal_high_s16:
-; CHECK: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmlal2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1755,7 +2481,9 @@ entry:
 
 define <2 x i64> @test_vqdmlal_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: test_vqdmlal_high_s32:
-; CHECK: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmlal2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1766,7 +2494,9 @@ entry:
 
 define <4 x i32> @test_vqdmlsl_high_s16(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) {
 ; CHECK-LABEL: test_vqdmlsl_high_s16:
-; CHECK: sqdmlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmlsl2 v0.4s, v1.8h, v2.8h
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
   %shuffle.i3.i = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -1777,7 +2507,9 @@ entry:
 
 define <2 x i64> @test_vqdmlsl_high_s32(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) {
 ; CHECK-LABEL: test_vqdmlsl_high_s32:
-; CHECK: sqdmlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    sqdmlsl2 v0.2d, v1.4s, v2.4s
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
   %shuffle.i3.i = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -1788,7 +2520,9 @@ entry:
 
 define <8 x i16> @test_vmull_p8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: test_vmull_p8:
-; CHECK: pmull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    pmull v0.8h, v0.8b, v1.8b
+; CHECK-NEXT:    ret
 entry:
   %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %a, <8 x i8> %b)
   ret <8 x i16> %vmull.i
@@ -1796,7 +2530,9 @@ entry:
 
 define <8 x i16> @test_vmull_high_p8(<16 x i8> %a, <16 x i8> %b) {
 ; CHECK-LABEL: test_vmull_high_p8:
-; CHECK: pmull2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    pmull2 v0.8h, v0.16b, v1.16b
+; CHECK-NEXT:    ret
 entry:
   %shuffle.i.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   %shuffle.i3.i = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -1805,8 +2541,14 @@ entry:
 }
 
 define i128 @test_vmull_p64(i64 %a, i64 %b) #4 {
-; CHECK-LABEL: test_vmull_p64
-; CHECK: pmull {{v[0-9]+}}.1q, {{v[0-9]+}}.1d, {{v[0-9]+}}.1d
+; CHECK-LABEL: test_vmull_p64:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fmov d0, x0
+; CHECK-NEXT:    fmov d1, x1
+; CHECK-NEXT:    pmull v0.1q, v0.1d, v1.1d
+; CHECK-NEXT:    mov x1, v0.d[1]
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    ret
 entry:
   %vmull2.i = tail call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %a, i64 %b)
   %vmull3.i = bitcast <16 x i8> %vmull2.i to i128
@@ -1814,8 +2556,12 @@ entry:
 }
 
 define i128 @test_vmull_high_p64(<2 x i64> %a, <2 x i64> %b) #4 {
-; CHECK-LABEL: test_vmull_high_p64
-; CHECK: pmull2 {{v[0-9]+}}.1q, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
+; CHECK-LABEL: test_vmull_high_p64:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    pmull2 v0.1q, v0.2d, v1.2d
+; CHECK-NEXT:    mov x1, v0.d[1]
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    ret
 entry:
   %0 = extractelement <2 x i64> %a, i32 1
   %1 = extractelement <2 x i64> %b, i32 1
@@ -1824,6 +2570,4 @@ entry:
   ret i128 %vmull3.i.i
 }
 
-declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64) #5
-
 
diff --git a/llvm/test/CodeGen/AArch64/ctpop-nonean.ll b/llvm/test/CodeGen/AArch64/ctpop-nonean.ll
new file mode 100644
index 0000000000000..a6cc9c6fa9be9
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/ctpop-nonean.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=-neon < %s | FileCheck %s
+
+declare i128 @llvm.ctpop.i128(i128)
+
+define i128 @ctpop_i128(i128 %i) {
+; CHECK-LABEL: ctpop_i128:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    lsr x8, x1, #1
+; CHECK-NEXT:    and x8, x8, #0x5555555555555555
+; CHECK-NEXT:    sub x8, x1, x8
+; CHECK-NEXT:    lsr x10, x0, #1
+; CHECK-NEXT:    and x10, x10, #0x5555555555555555
+; CHECK-NEXT:    and x11, x8, #0x3333333333333333
+; CHECK-NEXT:    lsr x8, x8, #2
+; CHECK-NEXT:    sub x10, x0, x10
+; CHECK-NEXT:    and x8, x8, #0x3333333333333333
+; CHECK-NEXT:    add x8, x11, x8
+; CHECK-NEXT:    and x11, x10, #0x3333333333333333
+; CHECK-NEXT:    lsr x10, x10, #2
+; CHECK-NEXT:    and x10, x10, #0x3333333333333333
+; CHECK-NEXT:    add x10, x11, x10
+; CHECK-NEXT:    add x8, x8, x8, lsr #4
+; CHECK-NEXT:    add x10, x10, x10, lsr #4
+; CHECK-NEXT:    mov x9, #72340172838076673
+; CHECK-NEXT:    and x8, x8, #0xf0f0f0f0f0f0f0f
+; CHECK-NEXT:    and x10, x10, #0xf0f0f0f0f0f0f0f
+; CHECK-NEXT:    mul x8, x8, x9
+; CHECK-NEXT:    mul x9, x10, x9
+; CHECK-NEXT:    lsr x9, x9, #56
+; CHECK-NEXT:    add x0, x9, x8, lsr #56
+; CHECK-NEXT:    mov x1, xzr
+; CHECK-NEXT:    ret
+  %c = call i128 @llvm.ctpop.i128(i128 %i)
+  ret i128 %c
+}
diff --git a/llvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll b/llvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll
new file mode 100644
index 0000000000000..f8d53a574dd2f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/machine-licm-sink-instr.ll
@@ -0,0 +1,176 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64 -sink-insts-to-avoid-spills | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+
+@A = external dso_local global [100 x i32], align 4
+
+define i32 @sink_load_and_copy(i32 %n) {
+; CHECK-LABEL: sink_load_and_copy:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT:    stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset w19, -8
+; CHECK-NEXT:    .cfi_offset w20, -16
+; CHECK-NEXT:    .cfi_offset w21, -24
+; CHECK-NEXT:    .cfi_offset w30, -32
+; CHECK-NEXT:    mov w19, w0
+; CHECK-NEXT:    cmp w0, #1 // =1
+; CHECK-NEXT:    b.lt .LBB0_3
+; CHECK-NEXT:  // %bb.1: // %for.body.preheader
+; CHECK-NEXT:    adrp x8, A
+; CHECK-NEXT:    ldr w21, [x8, :lo12:A]
+; CHECK-NEXT:    mov w20, w19
+; CHECK-NEXT:  .LBB0_2: // %for.body
+; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    mov w0, w21
+; CHECK-NEXT:    bl _Z3usei
+; CHECK-NEXT:    subs w19, w19, #1 // =1
+; CHECK-NEXT:    sdiv w20, w20, w0
+; CHECK-NEXT:    b.ne .LBB0_2
+; CHECK-NEXT:    b .LBB0_4
+; CHECK-NEXT:  .LBB0_3:
+; CHECK-NEXT:    mov w20, w19
+; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
+; CHECK-NEXT:    mov w0, w20
+; CHECK-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    ldp x30, x21, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT:    ret
+entry:
+  %cmp63 = icmp sgt i32 %n, 0
+  br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
+
+for.body.preheader:
+  %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
+  br label %for.body
+
+for.cond.cleanup:
+  %sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
+  ret i32 %sum.0.lcssa
+
+for.body:
+  %lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
+  %sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
+  %call = tail call i32 @_Z3usei(i32 %0)
+  %div = sdiv i32 %sum.065, %call
+  %lsr.iv.next = add i32 %lsr.iv, -1
+  %exitcond.not = icmp eq i32 %lsr.iv.next, 0
+  br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+}
+
+define i32 @cant_sink_successive_call(i32 %n) {
+; CHECK-LABEL: cant_sink_successive_call:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT:    stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset w19, -8
+; CHECK-NEXT:    .cfi_offset w20, -16
+; CHECK-NEXT:    .cfi_offset w21, -24
+; CHECK-NEXT:    .cfi_offset w30, -32
+; CHECK-NEXT:    mov w19, w0
+; CHECK-NEXT:    cmp w0, #1 // =1
+; CHECK-NEXT:    b.lt .LBB1_3
+; CHECK-NEXT:  // %bb.1: // %for.body.preheader
+; CHECK-NEXT:    adrp x8, A
+; CHECK-NEXT:    ldr w20, [x8, :lo12:A]
+; CHECK-NEXT:    mov w0, w19
+; CHECK-NEXT:    bl _Z3usei
+; CHECK-NEXT:    mov w21, w19
+; CHECK-NEXT:  .LBB1_2: // %for.body
+; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    mov w0, w20
+; CHECK-NEXT:    bl _Z3usei
+; CHECK-NEXT:    subs w19, w19, #1 // =1
+; CHECK-NEXT:    sdiv w21, w21, w0
+; CHECK-NEXT:    b.ne .LBB1_2
+; CHECK-NEXT:    b .LBB1_4
+; CHECK-NEXT:  .LBB1_3:
+; CHECK-NEXT:    mov w21, w19
+; CHECK-NEXT:  .LBB1_4: // %for.cond.cleanup
+; CHECK-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    mov w0, w21
+; CHECK-NEXT:    ldp x30, x21, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT:    ret
+entry:
+  %cmp63 = icmp sgt i32 %n, 0
+  br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
+
+for.body.preheader:
+  %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
+  %call0 = tail call i32 @_Z3usei(i32 %n)
+  br label %for.body
+
+for.cond.cleanup:
+  %sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
+  ret i32 %sum.0.lcssa
+
+for.body:
+  %lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
+  %sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
+  %call = tail call i32 @_Z3usei(i32 %0)
+  %div = sdiv i32 %sum.065, %call
+  %lsr.iv.next = add i32 %lsr.iv, -1
+  %exitcond.not = icmp eq i32 %lsr.iv.next, 0
+  br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+}
+
+define i32 @cant_sink_successive_store(i32* nocapture readnone %store, i32 %n) {
+; CHECK-LABEL: cant_sink_successive_store:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    stp x30, x21, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT:    stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    .cfi_offset w19, -8
+; CHECK-NEXT:    .cfi_offset w20, -16
+; CHECK-NEXT:    .cfi_offset w21, -24
+; CHECK-NEXT:    .cfi_offset w30, -32
+; CHECK-NEXT:    mov w19, w1
+; CHECK-NEXT:    cmp w1, #1 // =1
+; CHECK-NEXT:    b.lt .LBB2_3
+; CHECK-NEXT:  // %bb.1: // %for.body.preheader
+; CHECK-NEXT:    adrp x8, A
+; CHECK-NEXT:    ldr w20, [x8, :lo12:A]
+; CHECK-NEXT:    mov w8, #42
+; CHECK-NEXT:    mov w21, w19
+; CHECK-NEXT:    str w8, [x0]
+; CHECK-NEXT:  .LBB2_2: // %for.body
+; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    mov w0, w20
+; CHECK-NEXT:    bl _Z3usei
+; CHECK-NEXT:    subs w19, w19, #1 // =1
+; CHECK-NEXT:    sdiv w21, w21, w0
+; CHECK-NEXT:    b.ne .LBB2_2
+; CHECK-NEXT:    b .LBB2_4
+; CHECK-NEXT:  .LBB2_3:
+; CHECK-NEXT:    mov w21, w19
+; CHECK-NEXT:  .LBB2_4: // %for.cond.cleanup
+; CHECK-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    mov w0, w21
+; CHECK-NEXT:    ldp x30, x21, [sp], #32 // 16-byte Folded Reload
+; CHECK-NEXT:    ret
+entry:
+  %cmp63 = icmp sgt i32 %n, 0
+  br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
+
+for.body.preheader:
+  %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
+  store i32 42, i32* %store, align 4
+  br label %for.body
+
+for.cond.cleanup:
+  %sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
+  ret i32 %sum.0.lcssa
+
+for.body:
+  %lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
+  %sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
+  %call = tail call i32 @_Z3usei(i32 %0)
+  %div = sdiv i32 %sum.065, %call
+  %lsr.iv.next = add i32 %lsr.iv, -1
+  %exitcond.not = icmp eq i32 %lsr.iv.next, 0
+  br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+}
+
+declare i32 @_Z3usei(i32)
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
index cc9e172de5f88..e94abe815f3c3 100644
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-int-minmax.ll
@@ -69,14 +69,14 @@ define void @smax_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
 ; Ensure sensible type legalisation.
 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32
 ; VBITS_EQ_256-DAG: mov w[[A:[0-9]+]], #32
-; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
-; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0]
-; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1, x[[A]]]
-; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1]
+; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
+; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1]
+; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1, x[[A]]]
 ; VBITS_EQ_256-DAG: smax [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[OP1_LO]].b, [[OP2_LO]].b
 ; VBITS_EQ_256-DAG: smax [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[OP1_HI]].b, [[OP2_HI]].b
-; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0, x[[A]]]
-; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[A]]]
 ; VBITS_EQ_256-NEXT: ret
   %op1 = load <64 x i8>, <64 x i8>* %a
   %op2 = load <64 x i8>, <64 x i8>* %b
@@ -442,14 +442,14 @@ define void @smin_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
 ; Ensure sensible type legalisation.
 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32
 ; VBITS_EQ_256-DAG: mov w[[A:[0-9]+]], #32
-; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
-; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0]
-; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1, x[[A]]]
-; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1]
+; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
+; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1]
+; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1, x[[A]]]
 ; VBITS_EQ_256-DAG: smin [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[OP1_LO]].b, [[OP2_LO]].b
 ; VBITS_EQ_256-DAG: smin [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[OP1_HI]].b, [[OP2_HI]].b
-; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0, x[[A]]]
-; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[A]]]
   %op1 = load <64 x i8>, <64 x i8>* %a
   %op2 = load <64 x i8>, <64 x i8>* %b
   %res = call <64 x i8> @llvm.smin.v64i8(<64 x i8> %op1, <64 x i8> %op2)
@@ -814,14 +814,14 @@ define void @umax_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
 ; Ensure sensible type legalisation.
 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32
 ; VBITS_EQ_256-DAG: mov w[[A:[0-9]+]], #32
-; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
-; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0]
-; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1, x[[A]]]
-; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1]
+; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
+; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1]
+; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1, x[[A]]]
 ; VBITS_EQ_256-DAG: umax [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[OP1_LO]].b, [[OP2_LO]].b
 ; VBITS_EQ_256-DAG: umax [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[OP1_HI]].b, [[OP2_HI]].b
-; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0, x[[A]]]
-; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[A]]]
 ; VBITS_EQ_256-NEXT: ret
   %op1 = load <64 x i8>, <64 x i8>* %a
   %op2 = load <64 x i8>, <64 x i8>* %b
@@ -1187,14 +1187,14 @@ define void @umin_v64i8(<64 x i8>* %a, <64 x i8>* %b) #0 {
 ; Ensure sensible type legalisation.
 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32
 ; VBITS_EQ_256-DAG: mov w[[A:[0-9]+]], #32
-; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
-; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0]
-; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1, x[[A]]]
-; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1]
+; VBITS_EQ_256-DAG: ld1b { [[OP1_LO:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1b { [[OP1_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
+; VBITS_EQ_256-DAG: ld1b { [[OP2_LO:z[0-9]+]].b }, [[PG]]/z, [x1]
+; VBITS_EQ_256-DAG: ld1b { [[OP2_HI:z[0-9]+]].b }, [[PG]]/z, [x1, x[[A]]]
 ; VBITS_EQ_256-DAG: umin [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[OP1_LO]].b, [[OP2_LO]].b
 ; VBITS_EQ_256-DAG: umin [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[OP1_HI]].b, [[OP2_HI]].b
-; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0, x[[A]]]
-; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[A]]]
   %op1 = load <64 x i8>, <64 x i8>* %a
   %op2 = load <64 x i8>, <64 x i8>* %b
   %res = call <64 x i8> @llvm.umin.v64i8(<64 x i8> %op1, <64 x i8> %op2)
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
new file mode 100644
index 0000000000000..0e85c9e28defd
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-rev.ll
@@ -0,0 +1,643 @@
+; RUN: llc -aarch64-sve-vector-bits-min=128  -asm-verbose=0 < %s | FileCheck %s -check-prefix=NO_SVE
+; RUN: llc -aarch64-sve-vector-bits-min=256  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_EQ_256
+; RUN: llc -aarch64-sve-vector-bits-min=384  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK
+; RUN: llc -aarch64-sve-vector-bits-min=512  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
+; RUN: llc -aarch64-sve-vector-bits-min=640  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
+; RUN: llc -aarch64-sve-vector-bits-min=768  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
+; RUN: llc -aarch64-sve-vector-bits-min=896  -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
+; RUN: llc -aarch64-sve-vector-bits-min=1024 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1152 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1280 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1408 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1536 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1664 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1792 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=1920 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024
+; RUN: llc -aarch64-sve-vector-bits-min=2048 -asm-verbose=0 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512,VBITS_GE_1024,VBITS_GE_2048
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; Don't use SVE when its registers are no bigger than NEON.
+; NO_SVE-NOT: ptrue
+
+;
+; RBIT
+;
+
+define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) #0 {
+; CHECK-LABEL: bitreverse_v8i8:
+; CHECK: ptrue [[PG:p[0-9]+]].b, vl8
+; CHECK-NEXT: rbit z0.b, [[PG]]/m, z0.b
+; CHECK-NEXT: ret
+  %res = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %op)
+  ret <8 x i8> %res
+}
+
+define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) #0 {
+; CHECK-LABEL: bitreverse_v16i8:
+; CHECK: ptrue [[PG:p[0-9]+]].b, vl16
+; CHECK-NEXT: rbit z0.b, [[PG]]/m, z0.b
+; CHECK-NEXT: ret
+  %res = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %op)
+  ret <16 x i8> %res
+}
+
+define void @bitreverse_v32i8(<32 x i8>* %a) #0 {
+; CHECK-LABEL: bitreverse_v32i8:
+; CHECK: ptrue [[PG:p[0-9]+]].b, vl32
+; CHECK-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; CHECK-NEXT: rbit [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b
+; CHECK-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  %op = load <32 x i8>, <32 x i8>* %a
+  %res = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %op)
+  store <32 x i8> %res, <32 x i8>* %a
+  ret void
+}
+
+define void @bitreverse_v64i8(<64 x i8>* %a) #0 {
+; CHECK-LABEL: bitreverse_v64i8:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].b, vl64
+; VBITS_GE_512-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: rbit [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b
+; VBITS_GE_512-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
+; VBITS_GE_512-NEXT: ret
+;
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].b, vl32
+; VBITS_EQ_256-DAG: mov w[[A:[0-9]+]], #32
+; VBITS_EQ_256-DAG: ld1b { [[OP_LO:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1b { [[OP_HI:z[0-9]+]].b }, [[PG]]/z, [x0, x[[A]]]
+; VBITS_EQ_256-DAG: rbit [[RES_LO:z[0-9]+]].b, [[PG]]/m, [[OP_LO]].b
+; VBITS_EQ_256-DAG: rbit [[RES_HI:z[0-9]+]].b, [[PG]]/m, [[OP_HI]].b
+; VBITS_EQ_256-DAG: st1b { [[RES_LO]].b }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1b { [[RES_HI]].b }, [[PG]], [x0, x[[A]]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <64 x i8>, <64 x i8>* %a
+  %res = call <64 x i8> @llvm.bitreverse.v64i8(<64 x i8> %op)
+  store <64 x i8> %res, <64 x i8>* %a
+  ret void
+}
+
+define void @bitreverse_v128i8(<128 x i8>* %a) #0 {
+; CHECK-LABEL: bitreverse_v128i8:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].b, vl128
+; VBITS_GE_1024-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: rbit [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b
+; VBITS_GE_1024-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <128 x i8>, <128 x i8>* %a
+  %res = call <128 x i8> @llvm.bitreverse.v128i8(<128 x i8> %op)
+  store <128 x i8> %res, <128 x i8>* %a
+  ret void
+}
+
+define void @bitreverse_v256i8(<256 x i8>* %a) #0 {
+; CHECK-LABEL: bitreverse_v256i8:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].b, vl256
+; VBITS_GE_2048-NEXT: ld1b { [[OP:z[0-9]+]].b }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: rbit [[RES:z[0-9]+]].b, [[PG]]/m, [[OP]].b
+; VBITS_GE_2048-NEXT: st1b { [[RES]].b }, [[PG]], [x0]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <256 x i8>, <256 x i8>* %a
+  %res = call <256 x i8> @llvm.bitreverse.v256i8(<256 x i8> %op)
+  store <256 x i8> %res, <256 x i8>* %a
+  ret void
+}
+
+define <4 x i16> @bitreverse_v4i16(<4 x i16> %op) #0 {
+; CHECK-LABEL: bitreverse_v4i16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl4
+; CHECK-NEXT: rbit z0.h, [[PG]]/m, z0.h
+; CHECK-NEXT: ret
+  %res = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %op)
+  ret <4 x i16> %res
+}
+
+define <8 x i16> @bitreverse_v8i16(<8 x i16> %op) #0 {
+; CHECK-LABEL: bitreverse_v8i16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl8
+; CHECK-NEXT: rbit z0.h, [[PG]]/m, z0.h
+; CHECK-NEXT: ret
+  %res = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %op)
+  ret <8 x i16> %res
+}
+
+define void @bitreverse_v16i16(<16 x i16>* %a) #0 {
+; CHECK-LABEL: bitreverse_v16i16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl16
+; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; CHECK-NEXT: rbit [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  %op = load <16 x i16>, <16 x i16>* %a
+  %res = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %op)
+  store <16 x i16> %res, <16 x i16>* %a
+  ret void
+}
+
+define void @bitreverse_v32i16(<32 x i16>* %a) #0 {
+; CHECK-LABEL: bitreverse_v32i16:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32
+; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: rbit [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1h { [[OP_LO:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1h { [[OP_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: rbit [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[OP_LO]].h
+; VBITS_EQ_256-DAG: rbit [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[OP_HI]].h
+; VBITS_EQ_256-DAG: st1h { [[RES_LO]].h }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1h { [[RES_HI]].h }, [[PG]], [x[[A_HI]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <32 x i16>, <32 x i16>* %a
+  %res = call <32 x i16> @llvm.bitreverse.v32i16(<32 x i16> %op)
+  store <32 x i16> %res, <32 x i16>* %a
+  ret void
+}
+
+define void @bitreverse_v64i16(<64 x i16>* %a) #0 {
+; CHECK-LABEL: bitreverse_v64i16:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64
+; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: rbit [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <64 x i16>, <64 x i16>* %a
+  %res = call <64 x i16> @llvm.bitreverse.v64i16(<64 x i16> %op)
+  store <64 x i16> %res, <64 x i16>* %a
+  ret void
+}
+
+define void @bitreverse_v128i16(<128 x i16>* %a) #0 {
+; CHECK-LABEL: bitreverse_v128i16:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128
+; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: rbit [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <128 x i16>, <128 x i16>* %a
+  %res = call <128 x i16> @llvm.bitreverse.v128i16(<128 x i16> %op)
+  store <128 x i16> %res, <128 x i16>* %a
+  ret void
+}
+
+define <2 x i32> @bitreverse_v2i32(<2 x i32> %op) #0 {
+; CHECK-LABEL: bitreverse_v2i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl2
+; CHECK-NEXT: rbit z0.s, [[PG]]/m, z0.s
+; CHECK-NEXT: ret
+  %res = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %op)
+  ret <2 x i32> %res
+}
+
+define <4 x i32> @bitreverse_v4i32(<4 x i32> %op) #0 {
+; CHECK-LABEL: bitreverse_v4i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl4
+; CHECK-NEXT: rbit z0.s, [[PG]]/m, z0.s
+; CHECK-NEXT: ret
+  %res = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %op)
+  ret <4 x i32> %res
+}
+
+define void @bitreverse_v8i32(<8 x i32>* %a) #0 {
+; CHECK-LABEL: bitreverse_v8i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
+; CHECK-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; CHECK-NEXT: rbit [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  %op = load <8 x i32>, <8 x i32>* %a
+  %res = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %op)
+  store <8 x i32> %res, <8 x i32>* %a
+  ret void
+}
+
+define void @bitreverse_v16i32(<16 x i32>* %a) #0 {
+; CHECK-LABEL: bitreverse_v16i32:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
+; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: rbit [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1w { [[OP_LO:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1w { [[OP_HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: rbit [[RES_LO:z[0-9]+]].s, [[PG]]/m, [[OP_LO]].s
+; VBITS_EQ_256-DAG: rbit [[RES_HI:z[0-9]+]].s, [[PG]]/m, [[OP_HI]].s
+; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <16 x i32>, <16 x i32>* %a
+  %res = call <16 x i32> @llvm.bitreverse.v16i32(<16 x i32> %op)
+  store <16 x i32> %res, <16 x i32>* %a
+  ret void
+}
+
+define void @bitreverse_v32i32(<32 x i32>* %a) #0 {
+; CHECK-LABEL: bitreverse_v32i32:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32
+; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: rbit [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <32 x i32>, <32 x i32>* %a
+  %res = call <32 x i32> @llvm.bitreverse.v32i32(<32 x i32> %op)
+  store <32 x i32> %res, <32 x i32>* %a
+  ret void
+}
+
+define void @bitreverse_v64i32(<64 x i32>* %a) #0 {
+; CHECK-LABEL: bitreverse_v64i32:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64
+; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: rbit [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <64 x i32>, <64 x i32>* %a
+  %res = call <64 x i32> @llvm.bitreverse.v64i32(<64 x i32> %op)
+  store <64 x i32> %res, <64 x i32>* %a
+  ret void
+}
+
+define <1 x i64> @bitreverse_v1i64(<1 x i64> %op) #0 {
+; CHECK-LABEL: bitreverse_v1i64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl1
+; CHECK-NEXT: rbit z0.d, [[PG]]/m, z0.d
+; CHECK-NEXT: ret
+  %res = call <1 x i64> @llvm.bitreverse.v1i64(<1 x i64> %op)
+  ret <1 x i64> %res
+}
+
+define <2 x i64> @bitreverse_v2i64(<2 x i64> %op) #0 {
+; CHECK-LABEL: bitreverse_v2i64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl2
+; CHECK-NEXT: rbit z0.d, [[PG]]/m, z0.d
+; CHECK-NEXT: ret
+  %res = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %op)
+  ret <2 x i64> %res
+}
+
+define void @bitreverse_v4i64(<4 x i64>* %a) #0 {
+; CHECK-LABEL: bitreverse_v4i64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl4
+; CHECK-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; CHECK-NEXT: rbit [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  %op = load <4 x i64>, <4 x i64>* %a
+  %res = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %op)
+  store <4 x i64> %res, <4 x i64>* %a
+  ret void
+}
+
+define void @bitreverse_v8i64(<8 x i64>* %a) #0 {
+; CHECK-LABEL: bitreverse_v8i64:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8
+; VBITS_GE_512-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: rbit [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1d { [[OP_LO:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1d { [[OP_HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: rbit [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[OP_LO]].d
+; VBITS_EQ_256-DAG: rbit [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[OP_HI]].d
+; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <8 x i64>, <8 x i64>* %a
+  %res = call <8 x i64> @llvm.bitreverse.v8i64(<8 x i64> %op)
+  store <8 x i64> %res, <8 x i64>* %a
+  ret void
+}
+
+define void @bitreverse_v16i64(<16 x i64>* %a) #0 {
+; CHECK-LABEL: bitreverse_v16i64:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16
+; VBITS_GE_1024-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: rbit [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <16 x i64>, <16 x i64>* %a
+  %res = call <16 x i64> @llvm.bitreverse.v16i64(<16 x i64> %op)
+  store <16 x i64> %res, <16 x i64>* %a
+  ret void
+}
+
+define void @bitreverse_v32i64(<32 x i64>* %a) #0 {
+; CHECK-LABEL: bitreverse_v32i64:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32
+; VBITS_GE_2048-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: rbit [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <32 x i64>, <32 x i64>* %a
+  %res = call <32 x i64> @llvm.bitreverse.v32i64(<32 x i64> %op)
+  store <32 x i64> %res, <32 x i64>* %a
+  ret void
+}
+
+;
+; REVB
+;
+
+; Don't use SVE for 64-bit vectors.
+define <4 x i16> @bswap_v4i16(<4 x i16> %op) #0 {
+; CHECK-LABEL: bswap_v4i16:
+; CHECK: rev16 v0.8b, v0.8b
+; CHECK-NEXT: ret
+  %res = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %op)
+  ret <4 x i16> %res
+}
+
+; Don't use SVE for 128-bit vectors.
+define <8 x i16> @bswap_v8i16(<8 x i16> %op) #0 {
+; CHECK-LABEL: bswap_v8i16:
+; CHECK: rev16 v0.16b, v0.16b
+; CHECK-NEXT: ret
+  %res = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %op)
+  ret <8 x i16> %res
+}
+
+define void @bswap_v16i16(<16 x i16>* %a) #0 {
+; CHECK-LABEL: bswap_v16i16:
+; CHECK: ptrue [[PG:p[0-9]+]].h, vl16
+; CHECK-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; CHECK-NEXT: revb [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; CHECK-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  %op = load <16 x i16>, <16 x i16>* %a
+  %res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %op)
+  store <16 x i16> %res, <16 x i16>* %a
+  ret void
+}
+
+define void @bswap_v32i16(<32 x i16>* %a) #0 {
+; CHECK-LABEL: bswap_v32i16:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].h, vl32
+; VBITS_GE_512-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: revb [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; VBITS_GE_512-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].h, vl16
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1h { [[OP_LO:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1h { [[OP_HI:z[0-9]+]].h }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: revb [[RES_LO:z[0-9]+]].h, [[PG]]/m, [[OP_LO]].h
+; VBITS_EQ_256-DAG: revb [[RES_HI:z[0-9]+]].h, [[PG]]/m, [[OP_HI]].h
+; VBITS_EQ_256-DAG: st1h { [[RES_LO]].h }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1h { [[RES_HI]].h }, [[PG]], [x[[A_HI]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <32 x i16>, <32 x i16>* %a
+  %res = call <32 x i16> @llvm.bswap.v32i16(<32 x i16> %op)
+  store <32 x i16> %res, <32 x i16>* %a
+  ret void
+}
+
+define void @bswap_v64i16(<64 x i16>* %a) #0 {
+; CHECK-LABEL: bswap_v64i16:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].h, vl64
+; VBITS_GE_1024-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: revb [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; VBITS_GE_1024-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <64 x i16>, <64 x i16>* %a
+  %res = call <64 x i16> @llvm.bswap.v64i16(<64 x i16> %op)
+  store <64 x i16> %res, <64 x i16>* %a
+  ret void
+}
+
+define void @bswap_v128i16(<128 x i16>* %a) #0 {
+; CHECK-LABEL: bswap_v128i16:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].h, vl128
+; VBITS_GE_2048-NEXT: ld1h { [[OP:z[0-9]+]].h }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: revb [[RES:z[0-9]+]].h, [[PG]]/m, [[OP]].h
+; VBITS_GE_2048-NEXT: st1h { [[RES]].h }, [[PG]], [x0]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <128 x i16>, <128 x i16>* %a
+  %res = call <128 x i16> @llvm.bswap.v128i16(<128 x i16> %op)
+  store <128 x i16> %res, <128 x i16>* %a
+  ret void
+}
+
+; Don't use SVE for 64-bit vectors.
+define <2 x i32> @bswap_v2i32(<2 x i32> %op) #0 {
+; CHECK-LABEL: bswap_v2i32:
+; CHECK: rev32 v0.8b, v0.8b
+; CHECK-NEXT: ret
+  %res = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %op)
+  ret <2 x i32> %res
+}
+
+; Don't use SVE for 128-bit vectors.
+define <4 x i32> @bswap_v4i32(<4 x i32> %op) #0 {
+; CHECK-LABEL: bswap_v4i32:
+; CHECK: rev32 v0.16b, v0.16b
+; CHECK-NEXT: ret
+  %res = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %op)
+  ret <4 x i32> %res
+}
+
+define void @bswap_v8i32(<8 x i32>* %a) #0 {
+; CHECK-LABEL: bswap_v8i32:
+; CHECK: ptrue [[PG:p[0-9]+]].s, vl8
+; CHECK-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; CHECK-NEXT: revb [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  %op = load <8 x i32>, <8 x i32>* %a
+  %res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %op)
+  store <8 x i32> %res, <8 x i32>* %a
+  ret void
+}
+
+define void @bswap_v16i32(<16 x i32>* %a) #0 {
+; CHECK-LABEL: bswap_v16i32:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].s, vl16
+; VBITS_GE_512-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: revb [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1w { [[OP_LO:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1w { [[OP_HI:z[0-9]+]].s }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: revb [[RES_LO:z[0-9]+]].s, [[PG]]/m, [[OP_LO]].s
+; VBITS_EQ_256-DAG: revb [[RES_HI:z[0-9]+]].s, [[PG]]/m, [[OP_HI]].s
+; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <16 x i32>, <16 x i32>* %a
+  %res = call <16 x i32> @llvm.bswap.v16i32(<16 x i32> %op)
+  store <16 x i32> %res, <16 x i32>* %a
+  ret void
+}
+
+define void @bswap_v32i32(<32 x i32>* %a) #0 {
+; CHECK-LABEL: bswap_v32i32:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].s, vl32
+; VBITS_GE_1024-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: revb [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <32 x i32>, <32 x i32>* %a
+  %res = call <32 x i32> @llvm.bswap.v32i32(<32 x i32> %op)
+  store <32 x i32> %res, <32 x i32>* %a
+  ret void
+}
+
+define void @bswap_v64i32(<64 x i32>* %a) #0 {
+; CHECK-LABEL: bswap_v64i32:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].s, vl64
+; VBITS_GE_2048-NEXT: ld1w { [[OP:z[0-9]+]].s }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: revb [[RES:z[0-9]+]].s, [[PG]]/m, [[OP]].s
+; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <64 x i32>, <64 x i32>* %a
+  %res = call <64 x i32> @llvm.bswap.v64i32(<64 x i32> %op)
+  store <64 x i32> %res, <64 x i32>* %a
+  ret void
+}
+
+; Don't use SVE for 64-bit vectors.
+define <1 x i64> @bswap_v1i64(<1 x i64> %op) #0 {
+; CHECK-LABEL: bswap_v1i64:
+; CHECK: rev64 v0.8b, v0.8b
+; CHECK-NEXT: ret
+  %res = call <1 x i64> @llvm.bswap.v1i64(<1 x i64> %op)
+  ret <1 x i64> %res
+}
+
+; Don't use SVE for 128-bit vectors.
+define <2 x i64> @bswap_v2i64(<2 x i64> %op) #0 {
+; CHECK-LABEL: bswap_v2i64:
+; CHECK: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ret
+  %res = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %op)
+  ret <2 x i64> %res
+}
+
+define void @bswap_v4i64(<4 x i64>* %a) #0 {
+; CHECK-LABEL: bswap_v4i64:
+; CHECK: ptrue [[PG:p[0-9]+]].d, vl4
+; CHECK-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; CHECK-NEXT: revb [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; CHECK-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; CHECK-NEXT: ret
+  %op = load <4 x i64>, <4 x i64>* %a
+  %res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %op)
+  store <4 x i64> %res, <4 x i64>* %a
+  ret void
+}
+
+define void @bswap_v8i64(<8 x i64>* %a) #0 {
+; CHECK-LABEL: bswap_v8i64:
+; VBITS_GE_512: ptrue [[PG:p[0-9]+]].d, vl8
+; VBITS_GE_512-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_512-NEXT: revb [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; VBITS_GE_512-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_512-NEXT: ret
+
+; Ensure sensible type legalisation.
+; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
+; VBITS_EQ_256-DAG: add x[[A_HI:[0-9]+]], x0, #32
+; VBITS_EQ_256-DAG: ld1d { [[OP_LO:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_EQ_256-DAG: ld1d { [[OP_HI:z[0-9]+]].d }, [[PG]]/z, [x[[A_HI]]]
+; VBITS_EQ_256-DAG: revb [[RES_LO:z[0-9]+]].d, [[PG]]/m, [[OP_LO]].d
+; VBITS_EQ_256-DAG: revb [[RES_HI:z[0-9]+]].d, [[PG]]/m, [[OP_HI]].d
+; VBITS_EQ_256-DAG: st1d { [[RES_LO]].d }, [[PG]], [x0]
+; VBITS_EQ_256-DAG: st1d { [[RES_HI]].d }, [[PG]], [x[[A_HI]]
+; VBITS_EQ_256-NEXT: ret
+  %op = load <8 x i64>, <8 x i64>* %a
+  %res = call <8 x i64> @llvm.bswap.v8i64(<8 x i64> %op)
+  store <8 x i64> %res, <8 x i64>* %a
+  ret void
+}
+
+define void @bswap_v16i64(<16 x i64>* %a) #0 {
+; CHECK-LABEL: bswap_v16i64:
+; VBITS_GE_1024: ptrue [[PG:p[0-9]+]].d, vl16
+; VBITS_GE_1024-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_1024-NEXT: revb [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; VBITS_GE_1024-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_1024-NEXT: ret
+  %op = load <16 x i64>, <16 x i64>* %a
+  %res = call <16 x i64> @llvm.bswap.v16i64(<16 x i64> %op)
+  store <16 x i64> %res, <16 x i64>* %a
+  ret void
+}
+
+define void @bswap_v32i64(<32 x i64>* %a) #0 {
+; CHECK-LABEL: bswap_v32i64:
+; VBITS_GE_2048: ptrue [[PG:p[0-9]+]].d, vl32
+; VBITS_GE_2048-NEXT: ld1d { [[OP:z[0-9]+]].d }, [[PG]]/z, [x0]
+; VBITS_GE_2048-NEXT: revb [[RES:z[0-9]+]].d, [[PG]]/m, [[OP]].d
+; VBITS_GE_2048-NEXT: st1d { [[RES]].d }, [[PG]], [x0]
+; VBITS_GE_2048-NEXT: ret
+  %op = load <32 x i64>, <32 x i64>* %a
+  %res = call <32 x i64> @llvm.bswap.v32i64(<32 x i64> %op)
+  store <32 x i64> %res, <32 x i64>* %a
+  ret void
+}
+
+attributes #0 = { "target-features"="+sve" }
+
+declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>)
+declare <16 x i8> @llvm.bitreverse.v16i8(<16 x i8>)
+declare <32 x i8> @llvm.bitreverse.v32i8(<32 x i8>)
+declare <64 x i8> @llvm.bitreverse.v64i8(<64 x i8>)
+declare <128 x i8> @llvm.bitreverse.v128i8(<128 x i8>)
+declare <256 x i8> @llvm.bitreverse.v256i8(<256 x i8>)
+declare <4 x i16> @llvm.bitreverse.v4i16(<4 x i16>)
+declare <8 x i16> @llvm.bitreverse.v8i16(<8 x i16>)
+declare <16 x i16> @llvm.bitreverse.v16i16(<16 x i16>)
+declare <32 x i16> @llvm.bitreverse.v32i16(<32 x i16>)
+declare <64 x i16> @llvm.bitreverse.v64i16(<64 x i16>)
+declare <128 x i16> @llvm.bitreverse.v128i16(<128 x i16>)
+declare <2 x i32> @llvm.bitreverse.v2i32(<2 x i32>)
+declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>)
+declare <8 x i32> @llvm.bitreverse.v8i32(<8 x i32>)
+declare <16 x i32> @llvm.bitreverse.v16i32(<16 x i32>)
+declare <32 x i32> @llvm.bitreverse.v32i32(<32 x i32>)
+declare <64 x i32> @llvm.bitreverse.v64i32(<64 x i32>)
+declare <1 x i64> @llvm.bitreverse.v1i64(<1 x i64>)
+declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>)
+declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>)
+declare <8 x i64> @llvm.bitreverse.v8i64(<8 x i64>)
+declare <16 x i64> @llvm.bitreverse.v16i64(<16 x i64>)
+declare <32 x i64> @llvm.bitreverse.v32i64(<32 x i64>)
+
+declare <4 x i16> @llvm.bswap.v4i16(<4 x i16>)
+declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
+declare <16 x i16> @llvm.bswap.v16i16(<16 x i16>)
+declare <32 x i16> @llvm.bswap.v32i16(<32 x i16>)
+declare <64 x i16> @llvm.bswap.v64i16(<64 x i16>)
+declare <128 x i16> @llvm.bswap.v128i16(<128 x i16>)
+declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>)
+declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
+declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>)
+declare <16 x i32> @llvm.bswap.v16i32(<16 x i32>)
+declare <32 x i32> @llvm.bswap.v32i32(<32 x i32>)
+declare <64 x i32> @llvm.bswap.v64i32(<64 x i32>)
+declare <1 x i64> @llvm.bswap.v1i64(<1 x i64>)
+declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
+declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)
+declare <8 x i64> @llvm.bswap.v8i64(<8 x i64>)
+declare <16 x i64> @llvm.bswap.v16i64(<16 x i64>)
+declare <32 x i64> @llvm.bswap.v32i64(<32 x i64>)
+
diff --git a/llvm/test/CodeGen/AArch64/sve-intrinsics-reversal.ll b/llvm/test/CodeGen/AArch64/sve-intrinsics-reversal.ll
index ae3fa5c419ba0..33034f7bac01e 100644
--- a/llvm/test/CodeGen/AArch64/sve-intrinsics-reversal.ll
+++ b/llvm/test/CodeGen/AArch64/sve-intrinsics-reversal.ll
@@ -82,37 +82,6 @@ define <vscale x 2 x i64> @revb_i64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg
   ret <vscale x 2 x i64> %out
 }
 
-;
-; REVB (bswap)
-;
-
-define <vscale x 8 x i16> @revb_i16_bswap(<vscale x 8 x i16> %a) {
-; CHECK-LABEL: revb_i16_bswap:
-; CHECK: ptrue [[PG:p[0-9]+]].h
-; CHECK-NEXT: revb z0.h, [[PG]]/m, z0.h
-; CHECK-NEXT: ret
-  %res = call <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16> %a)
-  ret <vscale x 8 x i16> %res
-}
-
-define <vscale x 4 x i32> @revb_i32_bswap(<vscale x 4 x i32> %a) {
-; CHECK-LABEL: revb_i32_bswap:
-; CHECK: ptrue [[PG:p[0-9]+]].s
-; CHECK-NEXT: revb z0.s, [[PG]]/m, z0.s
-; CHECK-NEXT: ret
-  %res = call <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32> %a)
-  ret <vscale x 4 x i32> %res
-}
-
-define <vscale x 2 x i64> @revb_i64_bswap(<vscale x 2 x i64> %a) {
-; CHECK-LABEL: revb_i64_bswap:
-; CHECK: ptrue [[PG:p[0-9]+]].d
-; CHECK-NEXT: revb z0.d, [[PG]]/m, z0.d
-; CHECK-NEXT: ret
-  %res = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %a)
-  ret <vscale x 2 x i64> %res
-}
-
 ;
 ; REVH
 ;
@@ -160,10 +129,6 @@ declare <vscale x 8 x i16> @llvm.aarch64.sve.revb.nxv8i16(<vscale x 8 x i16>, <v
 declare <vscale x 4 x i32> @llvm.aarch64.sve.revb.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
 declare <vscale x 2 x i64> @llvm.aarch64.sve.revb.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
 
-declare <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16>)
-declare <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32>)
-declare <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64>)
-
 declare <vscale x 4 x i32> @llvm.aarch64.sve.revh.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x i32>)
 declare <vscale x 2 x i64> @llvm.aarch64.sve.revh.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x i64>)
 
diff --git a/llvm/test/CodeGen/AArch64/sve-rev.ll b/llvm/test/CodeGen/AArch64/sve-rev.ll
new file mode 100644
index 0000000000000..c1f9eda489885
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-rev.ll
@@ -0,0 +1,97 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
+
+target triple = "aarch64-unknown-linux-gnu"
+
+;
+; RBIT
+;
+
+define <vscale x 16 x i8> @bitreverse_i8(<vscale x 16 x i8> %a) #0 {
+; CHECK-LABEL: bitreverse_i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.b
+; CHECK-NEXT:    rbit z0.b, p0/m, z0.b
+; CHECK-NEXT:    ret
+  %res = call <vscale x 16 x i8> @llvm.bitreverse.nxv16i8(<vscale x 16 x i8> %a)
+  ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 8 x i16> @bitreverse_i16(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: bitreverse_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    rbit z0.h, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = call <vscale x 8 x i16> @llvm.bitreverse.nxv8i16(<vscale x 8 x i16> %a)
+  ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @bitreverse_i32(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: bitreverse_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    rbit z0.s, p0/m, z0.s
+; CHECK-NEXT:    ret
+  %res = call <vscale x 4 x i32> @llvm.bitreverse.nxv4i32(<vscale x 4 x i32> %a)
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @bitreverse_i64(<vscale x 2 x i64> %a) #0 {
+; CHECK-LABEL: bitreverse_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    rbit z0.d, p0/m, z0.d
+; CHECK-NEXT:    ret
+  %res = call <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64> %a)
+  ret <vscale x 2 x i64> %res
+}
+
+;
+; REVB
+;
+
+define <vscale x 8 x i16> @byteswap_i16(<vscale x 8 x i16> %a) #0 {
+; CHECK-LABEL: byteswap_i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    revb z0.h, p0/m, z0.h
+; CHECK-NEXT:    ret
+  %res = call <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16> %a)
+  ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @byteswap_i32(<vscale x 4 x i32> %a) #0 {
+; CHECK-LABEL: byteswap_i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    revb z0.s, p0/m, z0.s
+; CHECK-NEXT:    ret
+  %res = call <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32> %a)
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @byteswap_i64(<vscale x 2 x i64> %a) #0 {
+; CHECK-LABEL: byteswap_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    revb z0.d, p0/m, z0.d
+; CHECK-NEXT:    ret
+  %res = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %a)
+  ret <vscale x 2 x i64> %res
+}
+
+attributes #0 = { "target-features"="+sve" }
+
+declare <vscale x 16 x i8> @llvm.bitreverse.nxv16i8(<vscale x 16 x i8>)
+declare <vscale x 8 x i16> @llvm.bitreverse.nxv8i16(<vscale x 8 x i16>)
+declare <vscale x 4 x i32> @llvm.bitreverse.nxv4i32(<vscale x 4 x i32>)
+declare <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64>)
+
+declare <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16>)
+declare <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32>)
+declare <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64>)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
index 6fd99b8406d75..f0eefbd44bfb4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
@@ -8,279 +8,316 @@ define i32 @v_extract_v64i32_varidx(<64 x i32> addrspace(1)* %ptr, i32 %idx) {
 ; GCN-LABEL: v_extract_v64i32_varidx:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v15, v0
 ; GCN-NEXT:    s_add_u32 s4, s32, 0x3fc0
-; GCN-NEXT:    s_mov_b32 s5, 0
+; GCN-NEXT:    v_add_co_u32_e32 v12, vcc, 64, v0
 ; GCN-NEXT:    s_mov_b32 s6, s33
 ; GCN-NEXT:    s_and_b32 s33, s4, 0xffffc000
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
+; GCN-NEXT:    global_load_dwordx4 v[4:7], v[12:13], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[12:13], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[12:13], off offset:48
+; GCN-NEXT:    s_mov_b32 s5, 0
 ; GCN-NEXT:    s_movk_i32 s4, 0x80
-; GCN-NEXT:    v_mov_b32_e32 v12, s5
-; GCN-NEXT:    v_mov_b32_e32 v16, v1
-; GCN-NEXT:    v_add_co_u32_e32 v31, vcc, 64, v15
-; GCN-NEXT:    v_mov_b32_e32 v11, s4
-; GCN-NEXT:    v_addc_co_u32_e32 v32, vcc, 0, v16, vcc
-; GCN-NEXT:    v_add_co_u32_e32 v48, vcc, v15, v11
-; GCN-NEXT:    v_addc_co_u32_e32 v49, vcc, v16, v12, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
 ; GCN-NEXT:    s_movk_i32 s4, 0xc0
-; GCN-NEXT:    v_mov_b32_e32 v12, s5
-; GCN-NEXT:    v_mov_b32_e32 v11, s4
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v62, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT:    v_add_co_u32_e32 v59, vcc, v15, v11
-; GCN-NEXT:    global_load_dwordx4 v[3:6], v[15:16], off
-; GCN-NEXT:    global_load_dwordx4 v[7:10], v[15:16], off offset:16
-; GCN-NEXT:    v_addc_co_u32_e32 v60, vcc, v16, v12, vcc
-; GCN-NEXT:    global_load_dwordx4 v[11:14], v[15:16], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[15:18], v[15:16], off offset:48
-; GCN-NEXT:    global_load_dwordx4 v[19:22], v[31:32], off
-; GCN-NEXT:    global_load_dwordx4 v[23:26], v[31:32], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[27:30], v[31:32], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[31:34], v[31:32], off offset:48
-; GCN-NEXT:    global_load_dwordx4 v[35:38], v[48:49], off
-; GCN-NEXT:    global_load_dwordx4 v[39:42], v[48:49], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[43:46], v[48:49], off offset:32
-; GCN-NEXT:    v_lshrrev_b32_e64 v0, 6, s33
-; GCN-NEXT:    v_add_u32_e32 v0, 0x100, v0
-; GCN-NEXT:    v_add_u32_e32 v1, 16, v0
 ; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
 ; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v35, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v36, off, s[0:3], s33 offset:580 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v37, off, s[0:3], s33 offset:584 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v38, off, s[0:3], s33 offset:588 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v39, off, s[0:3], s33 offset:592 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:596 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:600 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:604 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:608 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:612 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:616 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:620 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:624 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[47:50], v[48:49], off offset:48
-; GCN-NEXT:    global_load_dwordx4 v[43:46], v[59:60], off
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[51:54], v[59:60], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[55:58], v[59:60], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[59:62], v[59:60], off offset:48
-; GCN-NEXT:    buffer_store_dword v7, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 20, v0
-; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 24, v0
-; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 28, v0
-; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 32, v0
-; GCN-NEXT:    buffer_store_dword v11, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 36, v0
-; GCN-NEXT:    buffer_store_dword v12, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 40, v0
-; GCN-NEXT:    buffer_store_dword v13, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 44, v0
-; GCN-NEXT:    buffer_store_dword v14, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 48, v0
-; GCN-NEXT:    buffer_store_dword v15, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 52, v0
-; GCN-NEXT:    buffer_store_dword v16, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 56, v0
-; GCN-NEXT:    buffer_store_dword v17, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 60, v0
-; GCN-NEXT:    buffer_store_dword v18, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 64, v0
-; GCN-NEXT:    buffer_store_dword v19, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x44, v0
-; GCN-NEXT:    buffer_store_dword v20, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x48, v0
-; GCN-NEXT:    buffer_store_dword v21, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x4c, v0
-; GCN-NEXT:    buffer_store_dword v22, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x50, v0
-; GCN-NEXT:    buffer_store_dword v23, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x54, v0
-; GCN-NEXT:    buffer_store_dword v24, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x58, v0
-; GCN-NEXT:    buffer_store_dword v25, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x5c, v0
-; GCN-NEXT:    buffer_store_dword v26, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x60, v0
-; GCN-NEXT:    buffer_store_dword v27, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x64, v0
-; GCN-NEXT:    buffer_store_dword v28, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x68, v0
-; GCN-NEXT:    buffer_store_dword v29, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x6c, v0
-; GCN-NEXT:    buffer_store_dword v30, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x70, v0
-; GCN-NEXT:    buffer_store_dword v31, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x74, v0
-; GCN-NEXT:    buffer_store_dword v32, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x78, v0
-; GCN-NEXT:    buffer_store_dword v33, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x7c, v0
-; GCN-NEXT:    buffer_store_dword v34, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x80, v0
-; GCN-NEXT:    buffer_store_dword v35, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x84, v0
-; GCN-NEXT:    buffer_store_dword v36, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x88, v0
-; GCN-NEXT:    buffer_store_dword v37, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x8c, v0
-; GCN-NEXT:    buffer_store_dword v38, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x90, v0
-; GCN-NEXT:    buffer_store_dword v39, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x94, v0
-; GCN-NEXT:    buffer_store_dword v40, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x98, v0
-; GCN-NEXT:    buffer_store_dword v41, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x9c, v0
-; GCN-NEXT:    buffer_store_dword v42, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:588 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:592 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:596 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:600 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:604 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:608 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:612 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:616 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:620 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:624 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:628 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
-; GCN-NEXT:    v_add_u32_e32 v1, 0xa0, v0
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v8, v15
-; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_mov_b32_e32 v9, v16
-; GCN-NEXT:    v_add_u32_e32 v1, 0xa4, v0
-; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_mov_b32_e32 v10, v17
-; GCN-NEXT:    v_add_u32_e32 v1, 0xa8, v0
-; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_mov_b32_e32 v11, v18
-; GCN-NEXT:    v_add_u32_e32 v1, 0xac, v0
-; GCN-NEXT:    buffer_store_dword v11, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xb0, v0
-; GCN-NEXT:    buffer_store_dword v47, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xb4, v0
-; GCN-NEXT:    buffer_store_dword v48, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xb8, v0
-; GCN-NEXT:    buffer_store_dword v49, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xbc, v0
-; GCN-NEXT:    buffer_store_dword v50, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
-; GCN-NEXT:    v_add_u32_e32 v1, 0xc0, v0
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v7, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xc4, v0
-; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xc8, v0
-; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xcc, v0
-; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 4, v0
-; GCN-NEXT:    buffer_store_dword v4, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 8, v0
-; GCN-NEXT:    buffer_store_dword v5, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 12, v0
-; GCN-NEXT:    buffer_store_dword v6, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:256
-; GCN-NEXT:    v_add_u32_e32 v1, 0xd0, v0
-; GCN-NEXT:    buffer_store_dword v51, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xd4, v0
-; GCN-NEXT:    buffer_store_dword v52, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xd8, v0
-; GCN-NEXT:    buffer_store_dword v53, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xdc, v0
-; GCN-NEXT:    buffer_store_dword v54, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xe0, v0
-; GCN-NEXT:    buffer_store_dword v55, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xe4, v0
-; GCN-NEXT:    buffer_store_dword v56, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xe8, v0
-; GCN-NEXT:    buffer_store_dword v57, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xec, v0
-; GCN-NEXT:    buffer_store_dword v58, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xf0, v0
-; GCN-NEXT:    buffer_store_dword v59, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xf4, v0
-; GCN-NEXT:    buffer_store_dword v60, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xf8, v0
-; GCN-NEXT:    buffer_store_dword v61, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xfc, v0
-; GCN-NEXT:    buffer_store_dword v62, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_and_b32_e32 v1, 63, v2
-; GCN-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
-; GCN-NEXT:    v_add_u32_e32 v0, v0, v1
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:580 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:584 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:588 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:592 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:596 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:600 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:604 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:608 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:612 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:616 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:620 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:624 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
+; GCN-NEXT:    v_lshrrev_b32_e64 v3, 6, s33
+; GCN-NEXT:    v_add_u32_e32 v3, 0x100, v3
+; GCN-NEXT:    v_add_u32_e32 v60, 16, v3
+; GCN-NEXT:    v_add_co_u32_e32 v52, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v53, vcc, v1, v17, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    v_add_co_u32_e32 v56, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v57, vcc, v1, v17, vcc
+; GCN-NEXT:    global_load_dwordx4 v[16:19], v[0:1], off
+; GCN-NEXT:    global_load_dwordx4 v[20:23], v[0:1], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[24:27], v[0:1], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[28:31], v[0:1], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[32:35], v[0:1], off offset:64
+; GCN-NEXT:    global_load_dwordx4 v[36:39], v[0:1], off offset:128
+; GCN-NEXT:    global_load_dwordx4 v[40:43], v[0:1], off offset:192
+; GCN-NEXT:    global_load_dwordx4 v[44:47], v[52:53], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[52:53], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[52:55], v[52:53], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[56:57], off offset:16
+; GCN-NEXT:    v_add_u32_e32 v0, 20, v3
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v20, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v21, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v22, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v23, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[56:57], off offset:32
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[56:59], v[56:57], off offset:48
+; GCN-NEXT:    buffer_store_dword v21, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 24, v3
+; GCN-NEXT:    buffer_store_dword v22, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 28, v3
+; GCN-NEXT:    buffer_store_dword v23, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 32, v3
+; GCN-NEXT:    buffer_store_dword v24, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 36, v3
+; GCN-NEXT:    buffer_store_dword v25, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 40, v3
+; GCN-NEXT:    buffer_store_dword v26, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 44, v3
+; GCN-NEXT:    buffer_store_dword v27, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 48, v3
+; GCN-NEXT:    buffer_store_dword v28, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 52, v3
+; GCN-NEXT:    buffer_store_dword v29, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 56, v3
+; GCN-NEXT:    buffer_store_dword v30, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 60, v3
+; GCN-NEXT:    buffer_store_dword v31, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 64, v3
+; GCN-NEXT:    buffer_store_dword v32, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x44, v3
+; GCN-NEXT:    buffer_store_dword v33, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x48, v3
+; GCN-NEXT:    buffer_store_dword v34, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x4c, v3
+; GCN-NEXT:    buffer_store_dword v35, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x50, v3
+; GCN-NEXT:    buffer_store_dword v20, v60, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x54, v3
+; GCN-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x58, v3
+; GCN-NEXT:    buffer_store_dword v6, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x5c, v3
+; GCN-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x60, v3
+; GCN-NEXT:    buffer_store_dword v8, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x64, v3
+; GCN-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x68, v3
+; GCN-NEXT:    buffer_store_dword v10, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x6c, v3
+; GCN-NEXT:    buffer_store_dword v11, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:588 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v24, off, s[0:3], s33 offset:592 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v25, off, s[0:3], s33 offset:596 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v26, off, s[0:3], s33 offset:600 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v27, off, s[0:3], s33 offset:604 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v28, off, s[0:3], s33 offset:608 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v29, off, s[0:3], s33 offset:612 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v30, off, s[0:3], s33 offset:616 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v31, off, s[0:3], s33 offset:620 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v32, off, s[0:3], s33 offset:624 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v33, off, s[0:3], s33 offset:628 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v34, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v35, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
+; GCN-NEXT:    v_add_u32_e32 v0, 0x70, v3
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v12, v32
+; GCN-NEXT:    buffer_store_dword v12, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v13, v33
+; GCN-NEXT:    v_add_u32_e32 v0, 0x74, v3
+; GCN-NEXT:    buffer_store_dword v13, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v14, v34
+; GCN-NEXT:    v_add_u32_e32 v0, 0x78, v3
+; GCN-NEXT:    buffer_store_dword v14, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v15, v35
+; GCN-NEXT:    v_add_u32_e32 v0, 0x7c, v3
+; GCN-NEXT:    buffer_store_dword v15, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x80, v3
+; GCN-NEXT:    buffer_store_dword v36, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x84, v3
+; GCN-NEXT:    buffer_store_dword v37, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x88, v3
+; GCN-NEXT:    buffer_store_dword v38, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x8c, v3
+; GCN-NEXT:    buffer_store_dword v39, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x90, v3
+; GCN-NEXT:    buffer_store_dword v44, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x94, v3
+; GCN-NEXT:    buffer_store_dword v45, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x98, v3
+; GCN-NEXT:    buffer_store_dword v46, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x9c, v3
+; GCN-NEXT:    buffer_store_dword v47, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xa0, v3
+; GCN-NEXT:    buffer_store_dword v48, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xa4, v3
+; GCN-NEXT:    buffer_store_dword v49, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xa8, v3
+; GCN-NEXT:    buffer_store_dword v50, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xac, v3
+; GCN-NEXT:    buffer_store_dword v51, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xb0, v3
+; GCN-NEXT:    buffer_store_dword v52, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xb4, v3
+; GCN-NEXT:    buffer_store_dword v53, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xb8, v3
+; GCN-NEXT:    buffer_store_dword v54, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xbc, v3
+; GCN-NEXT:    buffer_store_dword v55, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xc0, v3
+; GCN-NEXT:    buffer_store_dword v40, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xc4, v3
+; GCN-NEXT:    buffer_store_dword v41, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xc8, v3
+; GCN-NEXT:    buffer_store_dword v42, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xcc, v3
+; GCN-NEXT:    buffer_store_dword v43, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 4, v3
+; GCN-NEXT:    buffer_store_dword v17, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 8, v3
+; GCN-NEXT:    buffer_store_dword v18, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 12, v3
+; GCN-NEXT:    buffer_store_dword v19, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:256
+; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
+; GCN-NEXT:    v_add_u32_e32 v0, 0xd0, v3
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v4, v8
+; GCN-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v5, v9
+; GCN-NEXT:    v_add_u32_e32 v0, 0xd4, v3
+; GCN-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v6, v10
+; GCN-NEXT:    v_add_u32_e32 v0, 0xd8, v3
+; GCN-NEXT:    buffer_store_dword v6, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v7, v11
+; GCN-NEXT:    v_add_u32_e32 v0, 0xdc, v3
+; GCN-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
+; GCN-NEXT:    v_add_u32_e32 v0, 0xe0, v3
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v8, v12
+; GCN-NEXT:    buffer_store_dword v8, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v9, v13
+; GCN-NEXT:    v_add_u32_e32 v0, 0xe4, v3
+; GCN-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v10, v14
+; GCN-NEXT:    v_add_u32_e32 v0, 0xe8, v3
+; GCN-NEXT:    buffer_store_dword v10, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v11, v15
+; GCN-NEXT:    v_add_u32_e32 v0, 0xec, v3
+; GCN-NEXT:    buffer_store_dword v11, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xf0, v3
+; GCN-NEXT:    buffer_store_dword v56, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xf4, v3
+; GCN-NEXT:    buffer_store_dword v57, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xf8, v3
+; GCN-NEXT:    buffer_store_dword v58, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xfc, v3
+; GCN-NEXT:    buffer_store_dword v59, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_and_b32_e32 v0, 63, v2
+; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GCN-NEXT:    v_add_u32_e32 v0, v3, v0
 ; GCN-NEXT:    buffer_load_dword v0, v0, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v62, off, s[0:3], s33 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_mov_b32 s33, s6
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
@@ -293,284 +330,321 @@ define i16 @v_extract_v128i16_varidx(<128 x i16> addrspace(1)* %ptr, i32 %idx) {
 ; GCN-LABEL: v_extract_v128i16_varidx:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v15, v0
 ; GCN-NEXT:    s_add_u32 s4, s32, 0x3fc0
-; GCN-NEXT:    s_mov_b32 s5, 0
+; GCN-NEXT:    v_add_co_u32_e32 v12, vcc, 64, v0
 ; GCN-NEXT:    s_mov_b32 s6, s33
 ; GCN-NEXT:    s_and_b32 s33, s4, 0xffffc000
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
+; GCN-NEXT:    global_load_dwordx4 v[4:7], v[12:13], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[12:13], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[12:13], off offset:48
+; GCN-NEXT:    s_mov_b32 s5, 0
 ; GCN-NEXT:    s_movk_i32 s4, 0x80
-; GCN-NEXT:    v_mov_b32_e32 v12, s5
-; GCN-NEXT:    v_mov_b32_e32 v16, v1
-; GCN-NEXT:    v_add_co_u32_e32 v31, vcc, 64, v15
-; GCN-NEXT:    v_mov_b32_e32 v11, s4
-; GCN-NEXT:    v_addc_co_u32_e32 v32, vcc, 0, v16, vcc
-; GCN-NEXT:    v_add_co_u32_e32 v48, vcc, v15, v11
-; GCN-NEXT:    v_addc_co_u32_e32 v49, vcc, v16, v12, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
 ; GCN-NEXT:    s_movk_i32 s4, 0xc0
-; GCN-NEXT:    v_mov_b32_e32 v12, s5
-; GCN-NEXT:    v_mov_b32_e32 v11, s4
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v62, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT:    v_add_co_u32_e32 v59, vcc, v15, v11
-; GCN-NEXT:    global_load_dwordx4 v[3:6], v[15:16], off
-; GCN-NEXT:    global_load_dwordx4 v[7:10], v[15:16], off offset:16
-; GCN-NEXT:    v_addc_co_u32_e32 v60, vcc, v16, v12, vcc
-; GCN-NEXT:    global_load_dwordx4 v[11:14], v[15:16], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[15:18], v[15:16], off offset:48
-; GCN-NEXT:    global_load_dwordx4 v[19:22], v[31:32], off
-; GCN-NEXT:    global_load_dwordx4 v[23:26], v[31:32], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[27:30], v[31:32], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[31:34], v[31:32], off offset:48
-; GCN-NEXT:    global_load_dwordx4 v[35:38], v[48:49], off
-; GCN-NEXT:    global_load_dwordx4 v[39:42], v[48:49], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[43:46], v[48:49], off offset:32
-; GCN-NEXT:    v_lshrrev_b32_e64 v0, 6, s33
-; GCN-NEXT:    v_add_u32_e32 v0, 0x100, v0
-; GCN-NEXT:    v_add_u32_e32 v1, 16, v0
 ; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
 ; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v35, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v36, off, s[0:3], s33 offset:580 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v37, off, s[0:3], s33 offset:584 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v38, off, s[0:3], s33 offset:588 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v39, off, s[0:3], s33 offset:592 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:596 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:600 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:604 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:608 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:612 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:616 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:620 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:624 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[47:50], v[48:49], off offset:48
-; GCN-NEXT:    global_load_dwordx4 v[43:46], v[59:60], off
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[51:54], v[59:60], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[55:58], v[59:60], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[59:62], v[59:60], off offset:48
-; GCN-NEXT:    buffer_store_dword v7, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 20, v0
-; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 24, v0
-; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 28, v0
-; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 32, v0
-; GCN-NEXT:    buffer_store_dword v11, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 36, v0
-; GCN-NEXT:    buffer_store_dword v12, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 40, v0
-; GCN-NEXT:    buffer_store_dword v13, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 44, v0
-; GCN-NEXT:    buffer_store_dword v14, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 48, v0
-; GCN-NEXT:    buffer_store_dword v15, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 52, v0
-; GCN-NEXT:    buffer_store_dword v16, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 56, v0
-; GCN-NEXT:    buffer_store_dword v17, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 60, v0
-; GCN-NEXT:    buffer_store_dword v18, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 64, v0
-; GCN-NEXT:    buffer_store_dword v19, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x44, v0
-; GCN-NEXT:    buffer_store_dword v20, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x48, v0
-; GCN-NEXT:    buffer_store_dword v21, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x4c, v0
-; GCN-NEXT:    buffer_store_dword v22, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x50, v0
-; GCN-NEXT:    buffer_store_dword v23, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x54, v0
-; GCN-NEXT:    buffer_store_dword v24, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x58, v0
-; GCN-NEXT:    buffer_store_dword v25, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x5c, v0
-; GCN-NEXT:    buffer_store_dword v26, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x60, v0
-; GCN-NEXT:    buffer_store_dword v27, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x64, v0
-; GCN-NEXT:    buffer_store_dword v28, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x68, v0
-; GCN-NEXT:    buffer_store_dword v29, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x6c, v0
-; GCN-NEXT:    buffer_store_dword v30, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x70, v0
-; GCN-NEXT:    buffer_store_dword v31, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x74, v0
-; GCN-NEXT:    buffer_store_dword v32, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x78, v0
-; GCN-NEXT:    buffer_store_dword v33, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x7c, v0
-; GCN-NEXT:    buffer_store_dword v34, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x80, v0
-; GCN-NEXT:    buffer_store_dword v35, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x84, v0
-; GCN-NEXT:    buffer_store_dword v36, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x88, v0
-; GCN-NEXT:    buffer_store_dword v37, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x8c, v0
-; GCN-NEXT:    buffer_store_dword v38, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x90, v0
-; GCN-NEXT:    buffer_store_dword v39, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x94, v0
-; GCN-NEXT:    buffer_store_dword v40, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x98, v0
-; GCN-NEXT:    buffer_store_dword v41, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x9c, v0
-; GCN-NEXT:    buffer_store_dword v42, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:588 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:592 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:596 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:600 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:604 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:608 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:612 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:616 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:620 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:624 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:628 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
-; GCN-NEXT:    v_add_u32_e32 v1, 0xa0, v0
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v8, v15
-; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_mov_b32_e32 v9, v16
-; GCN-NEXT:    v_add_u32_e32 v1, 0xa4, v0
-; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_mov_b32_e32 v10, v17
-; GCN-NEXT:    v_add_u32_e32 v1, 0xa8, v0
-; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_mov_b32_e32 v11, v18
-; GCN-NEXT:    v_add_u32_e32 v1, 0xac, v0
-; GCN-NEXT:    buffer_store_dword v11, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xb0, v0
-; GCN-NEXT:    buffer_store_dword v47, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xb4, v0
-; GCN-NEXT:    buffer_store_dword v48, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xb8, v0
-; GCN-NEXT:    buffer_store_dword v49, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xbc, v0
-; GCN-NEXT:    buffer_store_dword v50, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
-; GCN-NEXT:    v_add_u32_e32 v1, 0xc0, v0
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:580 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:584 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:588 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:592 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:596 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:600 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:604 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:608 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:612 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:616 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:620 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:624 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
+; GCN-NEXT:    v_lshrrev_b32_e64 v3, 6, s33
+; GCN-NEXT:    v_add_u32_e32 v3, 0x100, v3
+; GCN-NEXT:    v_add_u32_e32 v60, 16, v3
+; GCN-NEXT:    v_add_co_u32_e32 v52, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v53, vcc, v1, v17, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    v_add_co_u32_e32 v56, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v57, vcc, v1, v17, vcc
+; GCN-NEXT:    global_load_dwordx4 v[16:19], v[0:1], off
+; GCN-NEXT:    global_load_dwordx4 v[20:23], v[0:1], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[24:27], v[0:1], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[28:31], v[0:1], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[32:35], v[0:1], off offset:64
+; GCN-NEXT:    global_load_dwordx4 v[36:39], v[0:1], off offset:128
+; GCN-NEXT:    global_load_dwordx4 v[40:43], v[0:1], off offset:192
+; GCN-NEXT:    global_load_dwordx4 v[44:47], v[52:53], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[52:53], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[52:55], v[52:53], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[56:57], off offset:16
+; GCN-NEXT:    v_add_u32_e32 v0, 20, v3
+; GCN-NEXT:    v_add_u32_e32 v1, 0xd0, v3
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v20, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v21, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v22, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v23, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[56:57], off offset:32
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[56:59], v[56:57], off offset:48
+; GCN-NEXT:    buffer_store_dword v21, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 24, v3
+; GCN-NEXT:    buffer_store_dword v22, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 28, v3
+; GCN-NEXT:    buffer_store_dword v23, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 32, v3
+; GCN-NEXT:    buffer_store_dword v24, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 36, v3
+; GCN-NEXT:    buffer_store_dword v25, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 40, v3
+; GCN-NEXT:    buffer_store_dword v26, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 44, v3
+; GCN-NEXT:    buffer_store_dword v27, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 48, v3
+; GCN-NEXT:    buffer_store_dword v28, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 52, v3
+; GCN-NEXT:    buffer_store_dword v29, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 56, v3
+; GCN-NEXT:    buffer_store_dword v30, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 60, v3
+; GCN-NEXT:    buffer_store_dword v31, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 64, v3
+; GCN-NEXT:    buffer_store_dword v32, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x44, v3
+; GCN-NEXT:    buffer_store_dword v33, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x48, v3
+; GCN-NEXT:    buffer_store_dword v34, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x4c, v3
+; GCN-NEXT:    buffer_store_dword v35, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x50, v3
+; GCN-NEXT:    buffer_store_dword v20, v60, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x54, v3
+; GCN-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x58, v3
+; GCN-NEXT:    buffer_store_dword v6, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x5c, v3
+; GCN-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x60, v3
+; GCN-NEXT:    buffer_store_dword v8, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x64, v3
+; GCN-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x68, v3
+; GCN-NEXT:    buffer_store_dword v10, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x6c, v3
+; GCN-NEXT:    buffer_store_dword v11, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:588 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v24, off, s[0:3], s33 offset:592 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v25, off, s[0:3], s33 offset:596 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v26, off, s[0:3], s33 offset:600 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v27, off, s[0:3], s33 offset:604 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v28, off, s[0:3], s33 offset:608 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v29, off, s[0:3], s33 offset:612 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v30, off, s[0:3], s33 offset:616 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v31, off, s[0:3], s33 offset:620 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v32, off, s[0:3], s33 offset:624 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v33, off, s[0:3], s33 offset:628 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v34, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v35, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
+; GCN-NEXT:    v_add_u32_e32 v0, 0x70, v3
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v12, v32
+; GCN-NEXT:    buffer_store_dword v12, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v13, v33
+; GCN-NEXT:    v_add_u32_e32 v0, 0x74, v3
+; GCN-NEXT:    buffer_store_dword v13, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v14, v34
+; GCN-NEXT:    v_add_u32_e32 v0, 0x78, v3
+; GCN-NEXT:    buffer_store_dword v14, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v15, v35
+; GCN-NEXT:    v_add_u32_e32 v0, 0x7c, v3
+; GCN-NEXT:    buffer_store_dword v15, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x80, v3
+; GCN-NEXT:    buffer_store_dword v36, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x84, v3
+; GCN-NEXT:    buffer_store_dword v37, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x88, v3
+; GCN-NEXT:    buffer_store_dword v38, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x8c, v3
+; GCN-NEXT:    buffer_store_dword v39, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x90, v3
+; GCN-NEXT:    buffer_store_dword v44, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x94, v3
+; GCN-NEXT:    buffer_store_dword v45, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x98, v3
+; GCN-NEXT:    buffer_store_dword v46, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x9c, v3
+; GCN-NEXT:    buffer_store_dword v47, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xa0, v3
+; GCN-NEXT:    buffer_store_dword v48, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xa4, v3
+; GCN-NEXT:    buffer_store_dword v49, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xa8, v3
+; GCN-NEXT:    buffer_store_dword v50, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xac, v3
+; GCN-NEXT:    buffer_store_dword v51, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xb0, v3
+; GCN-NEXT:    buffer_store_dword v52, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xb4, v3
+; GCN-NEXT:    buffer_store_dword v53, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xb8, v3
+; GCN-NEXT:    buffer_store_dword v54, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xbc, v3
+; GCN-NEXT:    buffer_store_dword v55, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xc0, v3
+; GCN-NEXT:    buffer_store_dword v40, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xc4, v3
+; GCN-NEXT:    buffer_store_dword v41, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xc8, v3
+; GCN-NEXT:    buffer_store_dword v42, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xcc, v3
+; GCN-NEXT:    buffer_store_dword v43, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 4, v3
+; GCN-NEXT:    buffer_store_dword v17, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 8, v3
+; GCN-NEXT:    buffer_store_dword v18, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 12, v3
+; GCN-NEXT:    buffer_store_dword v19, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:256
+; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
+; GCN-NEXT:    v_lshrrev_b32_e32 v0, 1, v2
+; GCN-NEXT:    v_and_b32_e32 v0, 63, v0
+; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GCN-NEXT:    v_add_u32_e32 v0, v3, v0
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v4, v8
+; GCN-NEXT:    buffer_store_dword v4, v1, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v5, v9
+; GCN-NEXT:    v_add_u32_e32 v1, 0xd4, v3
+; GCN-NEXT:    buffer_store_dword v5, v1, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v6, v10
+; GCN-NEXT:    v_add_u32_e32 v1, 0xd8, v3
+; GCN-NEXT:    buffer_store_dword v6, v1, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v7, v11
+; GCN-NEXT:    v_add_u32_e32 v1, 0xdc, v3
 ; GCN-NEXT:    buffer_store_dword v7, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xc4, v0
+; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
+; GCN-NEXT:    v_add_u32_e32 v1, 0xe0, v3
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v8, v12
 ; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xc8, v0
+; GCN-NEXT:    v_mov_b32_e32 v9, v13
+; GCN-NEXT:    v_add_u32_e32 v1, 0xe4, v3
 ; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xcc, v0
+; GCN-NEXT:    v_mov_b32_e32 v10, v14
+; GCN-NEXT:    v_add_u32_e32 v1, 0xe8, v3
 ; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 4, v0
-; GCN-NEXT:    buffer_store_dword v4, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 8, v0
-; GCN-NEXT:    buffer_store_dword v5, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 12, v0
-; GCN-NEXT:    buffer_store_dword v6, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:256
-; GCN-NEXT:    v_add_u32_e32 v3, 0xd0, v0
-; GCN-NEXT:    buffer_store_dword v51, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xd4, v0
-; GCN-NEXT:    buffer_store_dword v52, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xd8, v0
-; GCN-NEXT:    buffer_store_dword v53, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xdc, v0
-; GCN-NEXT:    buffer_store_dword v54, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xe0, v0
-; GCN-NEXT:    buffer_store_dword v55, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xe4, v0
-; GCN-NEXT:    buffer_store_dword v56, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xe8, v0
-; GCN-NEXT:    buffer_store_dword v57, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xec, v0
-; GCN-NEXT:    buffer_store_dword v58, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xf0, v0
-; GCN-NEXT:    v_lshrrev_b32_e32 v1, 1, v2
-; GCN-NEXT:    buffer_store_dword v59, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xf4, v0
-; GCN-NEXT:    v_and_b32_e32 v1, 63, v1
-; GCN-NEXT:    buffer_store_dword v60, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xf8, v0
-; GCN-NEXT:    buffer_store_dword v61, v3, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v3, 0xfc, v0
-; GCN-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
-; GCN-NEXT:    v_add_u32_e32 v0, v0, v1
-; GCN-NEXT:    buffer_store_dword v62, v3, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v11, v15
+; GCN-NEXT:    v_add_u32_e32 v1, 0xec, v3
+; GCN-NEXT:    buffer_store_dword v11, v1, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v1, 0xf0, v3
+; GCN-NEXT:    buffer_store_dword v56, v1, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v1, 0xf4, v3
+; GCN-NEXT:    buffer_store_dword v57, v1, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v1, 0xf8, v3
+; GCN-NEXT:    buffer_store_dword v58, v1, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v1, 0xfc, v3
+; GCN-NEXT:    buffer_store_dword v59, v1, s[0:3], 0 offen
 ; GCN-NEXT:    buffer_load_dword v0, v0, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v62, off, s[0:3], s33 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
 ; GCN-NEXT:    v_and_b32_e32 v1, 1, v2
 ; GCN-NEXT:    v_lshlrev_b32_e32 v1, 4, v1
 ; GCN-NEXT:    s_mov_b32 s33, s6
-; GCN-NEXT:    s_waitcnt vmcnt(15)
+; GCN-NEXT:    s_waitcnt vmcnt(13)
 ; GCN-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
@@ -583,22 +657,10 @@ define i64 @v_extract_v32i64_varidx(<32 x i64> addrspace(1)* %ptr, i32 %idx) {
 ; GCN-LABEL: v_extract_v32i64_varidx:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v15, v0
 ; GCN-NEXT:    s_add_u32 s4, s32, 0x3fc0
-; GCN-NEXT:    s_mov_b32 s5, 0
+; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, 64, v0
 ; GCN-NEXT:    s_mov_b32 s6, s33
 ; GCN-NEXT:    s_and_b32 s33, s4, 0xffffc000
-; GCN-NEXT:    s_movk_i32 s4, 0x80
-; GCN-NEXT:    v_mov_b32_e32 v12, s5
-; GCN-NEXT:    v_mov_b32_e32 v16, v1
-; GCN-NEXT:    v_add_co_u32_e32 v31, vcc, 64, v15
-; GCN-NEXT:    v_mov_b32_e32 v11, s4
-; GCN-NEXT:    v_addc_co_u32_e32 v32, vcc, 0, v16, vcc
-; GCN-NEXT:    v_add_co_u32_e32 v48, vcc, v15, v11
-; GCN-NEXT:    v_addc_co_u32_e32 v49, vcc, v16, v12, vcc
-; GCN-NEXT:    s_movk_i32 s4, 0xc0
-; GCN-NEXT:    v_mov_b32_e32 v12, s5
-; GCN-NEXT:    v_mov_b32_e32 v11, s4
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:56 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
@@ -614,232 +676,323 @@ define i64 @v_extract_v32i64_varidx(<32 x i64> addrspace(1)* %ptr, i32 %idx) {
 ; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v62, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT:    v_add_co_u32_e32 v59, vcc, v15, v11
-; GCN-NEXT:    global_load_dwordx4 v[3:6], v[15:16], off
-; GCN-NEXT:    global_load_dwordx4 v[7:10], v[15:16], off offset:16
-; GCN-NEXT:    v_addc_co_u32_e32 v60, vcc, v16, v12, vcc
-; GCN-NEXT:    global_load_dwordx4 v[11:14], v[15:16], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[15:18], v[15:16], off offset:48
-; GCN-NEXT:    global_load_dwordx4 v[19:22], v[31:32], off
-; GCN-NEXT:    global_load_dwordx4 v[23:26], v[31:32], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[27:30], v[31:32], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[31:34], v[31:32], off offset:48
-; GCN-NEXT:    global_load_dwordx4 v[35:38], v[48:49], off
-; GCN-NEXT:    global_load_dwordx4 v[39:42], v[48:49], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[43:46], v[48:49], off offset:32
-; GCN-NEXT:    v_lshrrev_b32_e64 v0, 6, s33
-; GCN-NEXT:    v_add_u32_e32 v0, 0x100, v0
-; GCN-NEXT:    v_add_u32_e32 v1, 16, v0
-; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
+; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
+; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
+; GCN-NEXT:    global_load_dwordx4 v[7:10], v[3:4], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[11:14], v[3:4], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[56:59], v[3:4], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[15:18], v[0:1], off
+; GCN-NEXT:    s_movk_i32 s4, 0x80
+; GCN-NEXT:    s_mov_b32 s5, 0
+; GCN-NEXT:    v_mov_b32_e32 v3, s4
+; GCN-NEXT:    v_mov_b32_e32 v4, s5
+; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v3
+; GCN-NEXT:    s_movk_i32 s4, 0xc0
+; GCN-NEXT:    v_mov_b32_e32 v6, s5
+; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, v1, v4, vcc
+; GCN-NEXT:    v_mov_b32_e32 v5, s4
+; GCN-NEXT:    v_add_co_u32_e32 v60, vcc, v0, v5
+; GCN-NEXT:    v_addc_co_u32_e32 v61, vcc, v1, v6, vcc
+; GCN-NEXT:    v_lshrrev_b32_e64 v62, 6, s33
+; GCN-NEXT:    v_add_u32_e32 v62, 0x100, v62
+; GCN-NEXT:    v_add_u32_e32 v2, 16, v62
+; GCN-NEXT:    s_add_u32 s32, s32, 0x14000
+; GCN-NEXT:    s_sub_u32 s32, s32, 0x14000
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v35, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v36, off, s[0:3], s33 offset:580 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v37, off, s[0:3], s33 offset:584 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v38, off, s[0:3], s33 offset:588 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v39, off, s[0:3], s33 offset:592 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:596 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:600 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:604 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:608 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:612 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:616 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:620 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:624 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[47:50], v[48:49], off offset:48
-; GCN-NEXT:    global_load_dwordx4 v[43:46], v[59:60], off
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[51:54], v[59:60], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[55:58], v[59:60], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[59:62], v[59:60], off offset:48
-; GCN-NEXT:    buffer_store_dword v7, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 20, v0
-; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 24, v0
-; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 28, v0
-; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 32, v0
-; GCN-NEXT:    buffer_store_dword v11, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 36, v0
-; GCN-NEXT:    buffer_store_dword v12, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 40, v0
-; GCN-NEXT:    buffer_store_dword v13, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 44, v0
-; GCN-NEXT:    buffer_store_dword v14, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 48, v0
-; GCN-NEXT:    buffer_store_dword v15, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 52, v0
-; GCN-NEXT:    buffer_store_dword v16, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 56, v0
-; GCN-NEXT:    buffer_store_dword v17, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 60, v0
-; GCN-NEXT:    buffer_store_dword v18, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 64, v0
-; GCN-NEXT:    buffer_store_dword v19, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x44, v0
-; GCN-NEXT:    buffer_store_dword v20, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x48, v0
-; GCN-NEXT:    buffer_store_dword v21, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x4c, v0
-; GCN-NEXT:    buffer_store_dword v22, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x50, v0
-; GCN-NEXT:    buffer_store_dword v23, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x54, v0
-; GCN-NEXT:    buffer_store_dword v24, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x58, v0
-; GCN-NEXT:    buffer_store_dword v25, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x5c, v0
-; GCN-NEXT:    buffer_store_dword v26, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x60, v0
-; GCN-NEXT:    buffer_store_dword v27, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x64, v0
-; GCN-NEXT:    buffer_store_dword v28, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x68, v0
-; GCN-NEXT:    buffer_store_dword v29, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x6c, v0
-; GCN-NEXT:    buffer_store_dword v30, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x70, v0
-; GCN-NEXT:    buffer_store_dword v31, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x74, v0
-; GCN-NEXT:    buffer_store_dword v32, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x78, v0
-; GCN-NEXT:    buffer_store_dword v33, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x7c, v0
-; GCN-NEXT:    buffer_store_dword v34, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x80, v0
-; GCN-NEXT:    buffer_store_dword v35, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x84, v0
-; GCN-NEXT:    buffer_store_dword v36, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x88, v0
-; GCN-NEXT:    buffer_store_dword v37, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x8c, v0
-; GCN-NEXT:    buffer_store_dword v38, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x90, v0
-; GCN-NEXT:    buffer_store_dword v39, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x94, v0
-; GCN-NEXT:    buffer_store_dword v40, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x98, v0
-; GCN-NEXT:    buffer_store_dword v41, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0x9c, v0
-; GCN-NEXT:    buffer_store_dword v42, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:588 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:592 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:596 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:600 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:604 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:608 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:612 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:616 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:620 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:624 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:628 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
-; GCN-NEXT:    v_add_u32_e32 v1, 0xa0, v0
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v8, v15
-; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_mov_b32_e32 v9, v16
-; GCN-NEXT:    v_add_u32_e32 v1, 0xa4, v0
-; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_mov_b32_e32 v10, v17
-; GCN-NEXT:    v_add_u32_e32 v1, 0xa8, v0
-; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_mov_b32_e32 v11, v18
-; GCN-NEXT:    v_add_u32_e32 v1, 0xac, v0
-; GCN-NEXT:    buffer_store_dword v11, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xb0, v0
-; GCN-NEXT:    buffer_store_dword v47, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xb4, v0
-; GCN-NEXT:    buffer_store_dword v48, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xb8, v0
-; GCN-NEXT:    buffer_store_dword v49, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xbc, v0
-; GCN-NEXT:    buffer_store_dword v50, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
-; GCN-NEXT:    v_add_u32_e32 v1, 0xc0, v0
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v7, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xc4, v0
-; GCN-NEXT:    buffer_store_dword v8, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xc8, v0
-; GCN-NEXT:    buffer_store_dword v9, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xcc, v0
-; GCN-NEXT:    buffer_store_dword v10, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 4, v0
-; GCN-NEXT:    buffer_store_dword v4, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 8, v0
-; GCN-NEXT:    buffer_store_dword v5, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 12, v0
-; GCN-NEXT:    buffer_store_dword v6, v1, s[0:3], 0 offen
-; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:256
-; GCN-NEXT:    v_add_u32_e32 v1, 0xd0, v0
-; GCN-NEXT:    buffer_store_dword v51, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xd4, v0
-; GCN-NEXT:    buffer_store_dword v52, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xd8, v0
-; GCN-NEXT:    buffer_store_dword v53, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xdc, v0
-; GCN-NEXT:    buffer_store_dword v54, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xe0, v0
-; GCN-NEXT:    buffer_store_dword v55, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xe4, v0
-; GCN-NEXT:    buffer_store_dword v56, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xe8, v0
-; GCN-NEXT:    buffer_store_dword v57, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xec, v0
-; GCN-NEXT:    buffer_store_dword v58, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xf0, v0
-; GCN-NEXT:    buffer_store_dword v59, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xf4, v0
-; GCN-NEXT:    buffer_store_dword v60, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xf8, v0
-; GCN-NEXT:    buffer_store_dword v61, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_add_u32_e32 v1, 0xfc, v0
-; GCN-NEXT:    buffer_store_dword v62, v1, s[0:3], 0 offen
-; GCN-NEXT:    v_and_b32_e32 v1, 31, v2
-; GCN-NEXT:    v_lshlrev_b32_e32 v1, 3, v1
-; GCN-NEXT:    v_add_u32_e32 v0, v0, v1
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v20, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v21, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v22, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v23, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v24, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v25, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v26, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v27, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v28, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v29, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v30, off, s[0:3], s33 offset:704 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[20:23], v[0:1], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[24:27], v[0:1], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[28:31], v[0:1], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[32:35], v[0:1], off offset:64
+; GCN-NEXT:    global_load_dwordx4 v[36:39], v[0:1], off offset:128
+; GCN-NEXT:    global_load_dwordx4 v[40:43], v[0:1], off offset:192
+; GCN-NEXT:    global_load_dwordx4 v[44:47], v[3:4], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[3:4], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[52:55], v[3:4], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[15:18], v[60:61], off offset:16
+; GCN-NEXT:    v_add_u32_e32 v0, 20, v62
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:708 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:712 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:716 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:720 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:724 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:728 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:732 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:736 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:740 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v20, off, s[0:3], s33 offset:744 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v21, off, s[0:3], s33 offset:748 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v22, off, s[0:3], s33 offset:752 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v23, off, s[0:3], s33 offset:756 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v24, off, s[0:3], s33 offset:760 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v25, off, s[0:3], s33 offset:764 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v26, off, s[0:3], s33 offset:768 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[15:18], v[60:61], off offset:32
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:580 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:584 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:588 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:592 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:596 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:600 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:604 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:608 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:612 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:616 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:620 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:624 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v20, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v21, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v22, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[15:18], v[60:61], off offset:48
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v20, v2, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v21, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 24, v62
+; GCN-NEXT:    buffer_store_dword v22, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 28, v62
+; GCN-NEXT:    buffer_store_dword v23, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 32, v62
+; GCN-NEXT:    buffer_store_dword v24, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 36, v62
+; GCN-NEXT:    buffer_store_dword v25, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 40, v62
+; GCN-NEXT:    buffer_store_dword v26, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 44, v62
+; GCN-NEXT:    buffer_store_dword v27, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 48, v62
+; GCN-NEXT:    buffer_store_dword v28, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 52, v62
+; GCN-NEXT:    buffer_store_dword v29, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 56, v62
+; GCN-NEXT:    buffer_store_dword v30, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 60, v62
+; GCN-NEXT:    buffer_store_dword v31, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 64, v62
+; GCN-NEXT:    buffer_store_dword v32, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x44, v62
+; GCN-NEXT:    buffer_store_dword v33, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x48, v62
+; GCN-NEXT:    buffer_store_dword v34, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x4c, v62
+; GCN-NEXT:    buffer_store_dword v35, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x50, v62
+; GCN-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x54, v62
+; GCN-NEXT:    buffer_store_dword v8, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x58, v62
+; GCN-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x5c, v62
+; GCN-NEXT:    buffer_store_dword v10, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x60, v62
+; GCN-NEXT:    buffer_store_dword v11, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x64, v62
+; GCN-NEXT:    buffer_store_dword v12, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x68, v62
+; GCN-NEXT:    buffer_store_dword v13, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x6c, v62
+; GCN-NEXT:    buffer_store_dword v14, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x70, v62
+; GCN-NEXT:    buffer_store_dword v56, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x74, v62
+; GCN-NEXT:    buffer_store_dword v57, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x78, v62
+; GCN-NEXT:    buffer_store_dword v58, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x7c, v62
+; GCN-NEXT:    buffer_store_dword v59, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x80, v62
+; GCN-NEXT:    buffer_store_dword v36, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x84, v62
+; GCN-NEXT:    buffer_store_dword v37, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x88, v62
+; GCN-NEXT:    buffer_store_dword v38, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x8c, v62
+; GCN-NEXT:    buffer_store_dword v39, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x90, v62
+; GCN-NEXT:    buffer_store_dword v44, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x94, v62
+; GCN-NEXT:    buffer_store_dword v45, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x98, v62
+; GCN-NEXT:    buffer_store_dword v46, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0x9c, v62
+; GCN-NEXT:    buffer_store_dword v47, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xa0, v62
+; GCN-NEXT:    buffer_store_dword v48, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xa4, v62
+; GCN-NEXT:    buffer_store_dword v49, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xa8, v62
+; GCN-NEXT:    buffer_store_dword v50, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xac, v62
+; GCN-NEXT:    buffer_store_dword v51, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xb0, v62
+; GCN-NEXT:    buffer_store_dword v52, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xb4, v62
+; GCN-NEXT:    buffer_store_dword v53, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xb8, v62
+; GCN-NEXT:    buffer_store_dword v54, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xbc, v62
+; GCN-NEXT:    buffer_store_dword v55, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xc0, v62
+; GCN-NEXT:    buffer_store_dword v40, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xc4, v62
+; GCN-NEXT:    buffer_store_dword v41, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xc8, v62
+; GCN-NEXT:    buffer_store_dword v42, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xcc, v62
+; GCN-NEXT:    buffer_store_dword v43, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_load_dword v1, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v2, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:704 ; 4-byte Folded Reload
+; GCN-NEXT:    v_add_u32_e32 v0, 4, v62
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v2, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 8, v62
+; GCN-NEXT:    buffer_store_dword v3, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 12, v62
+; GCN-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:256
+; GCN-NEXT:    buffer_load_dword v1, off, s[0:3], s33 offset:708 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v2, off, s[0:3], s33 offset:712 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:716 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:720 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:724 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:728 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:732 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:736 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:740 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:744 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:748 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:752 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:756 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:760 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:764 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:768 ; 4-byte Folded Reload
+; GCN-NEXT:    v_add_u32_e32 v0, 0xd0, v62
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v4, v5
+; GCN-NEXT:    v_mov_b32_e32 v5, v6
+; GCN-NEXT:    buffer_store_dword v4, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xd4, v62
+; GCN-NEXT:    v_mov_b32_e32 v6, v7
+; GCN-NEXT:    buffer_store_dword v5, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xd8, v62
+; GCN-NEXT:    buffer_store_dword v6, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v7, v8
+; GCN-NEXT:    v_add_u32_e32 v0, 0xdc, v62
+; GCN-NEXT:    buffer_store_dword v7, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_load_dword v1, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v2, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:588 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:592 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:596 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:600 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:604 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:608 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:612 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:616 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:620 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:624 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:628 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
+; GCN-NEXT:    v_add_u32_e32 v0, 0xe0, v62
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v8, v9
+; GCN-NEXT:    v_mov_b32_e32 v9, v10
+; GCN-NEXT:    buffer_store_dword v8, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xe4, v62
+; GCN-NEXT:    v_mov_b32_e32 v10, v11
+; GCN-NEXT:    buffer_store_dword v9, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xe8, v62
+; GCN-NEXT:    buffer_store_dword v10, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v11, v12
+; GCN-NEXT:    v_add_u32_e32 v0, 0xec, v62
+; GCN-NEXT:    buffer_store_dword v11, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_load_dword v1, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v2, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
+; GCN-NEXT:    v_add_u32_e32 v0, 0xf0, v62
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v12, v13
+; GCN-NEXT:    v_mov_b32_e32 v13, v14
+; GCN-NEXT:    buffer_store_dword v12, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xf4, v62
+; GCN-NEXT:    v_mov_b32_e32 v14, v15
+; GCN-NEXT:    buffer_store_dword v13, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_add_u32_e32 v0, 0xf8, v62
+; GCN-NEXT:    buffer_store_dword v14, v0, s[0:3], 0 offen
+; GCN-NEXT:    v_mov_b32_e32 v15, v16
+; GCN-NEXT:    v_add_u32_e32 v0, 0xfc, v62
+; GCN-NEXT:    buffer_store_dword v15, v0, s[0:3], 0 offen
+; GCN-NEXT:    buffer_load_dword v0, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_and_b32_e32 v0, 31, v0
+; GCN-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
+; GCN-NEXT:    v_add_u32_e32 v0, v62, v0
 ; GCN-NEXT:    v_add_u32_e32 v1, 4, v0
 ; GCN-NEXT:    buffer_load_dword v0, v0, s[0:3], 0 offen
 ; GCN-NEXT:    buffer_load_dword v1, v1, s[0:3], 0 offen
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
index 02d9d3cfbb85b..5f04b3681dae4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll
@@ -2520,13 +2520,7 @@ define i32 @v_extract_v64i32_32(<64 x i32> addrspace(1)* %ptr) {
 ; GPRIDX-LABEL: v_extract_v64i32_32:
 ; GPRIDX:       ; %bb.0:
 ; GPRIDX-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GPRIDX-NEXT:    s_movk_i32 s4, 0x80
-; GPRIDX-NEXT:    s_mov_b32 s5, 0
-; GPRIDX-NEXT:    v_mov_b32_e32 v2, s4
-; GPRIDX-NEXT:    v_mov_b32_e32 v3, s5
-; GPRIDX-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
-; GPRIDX-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GPRIDX-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GPRIDX-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off offset:128
 ; GPRIDX-NEXT:    s_waitcnt vmcnt(0)
 ; GPRIDX-NEXT:    s_setpc_b64 s[30:31]
 ;
@@ -2551,13 +2545,7 @@ define i32 @v_extract_v64i32_33(<64 x i32> addrspace(1)* %ptr) {
 ; GPRIDX-LABEL: v_extract_v64i32_33:
 ; GPRIDX:       ; %bb.0:
 ; GPRIDX-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GPRIDX-NEXT:    s_movk_i32 s4, 0x80
-; GPRIDX-NEXT:    s_mov_b32 s5, 0
-; GPRIDX-NEXT:    v_mov_b32_e32 v2, s4
-; GPRIDX-NEXT:    v_mov_b32_e32 v3, s5
-; GPRIDX-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
-; GPRIDX-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
-; GPRIDX-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off
+; GPRIDX-NEXT:    global_load_dwordx4 v[0:3], v[0:1], off offset:128
 ; GPRIDX-NEXT:    s_waitcnt vmcnt(0)
 ; GPRIDX-NEXT:    v_mov_b32_e32 v0, v1
 ; GPRIDX-NEXT:    s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
new file mode 100644
index 0000000000000..ff28280ba9b45
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
@@ -0,0 +1,749 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx900 -global-isel -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1030 -global-isel -mattr=-promote-alloca -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
+
+define amdgpu_kernel void @store_load_sindex_kernel(i32 %idx) {
+; GFX9-LABEL: store_load_sindex_kernel:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_load_dword s0, s[0:1], 0x24
+; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5
+; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0
+; GFX9-NEXT:    v_mov_b32_e32 v0, 15
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_lshl_b32 s1, s0, 2
+; GFX9-NEXT:    s_and_b32 s0, s0, 15
+; GFX9-NEXT:    s_lshl_b32 s0, s0, 2
+; GFX9-NEXT:    s_add_u32 s1, 4, s1
+; GFX9-NEXT:    scratch_store_dword off, v0, s1
+; GFX9-NEXT:    s_add_u32 s0, 4, s0
+; GFX9-NEXT:    scratch_load_dword v0, off, s0
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: store_load_sindex_kernel:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_add_u32 s2, s2, s5
+; GFX10-NEXT:    s_addc_u32 s3, s3, 0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
+; GFX10-NEXT:    s_load_dword s0, s[0:1], 0x24
+; GFX10-NEXT:    v_mov_b32_e32 v0, 15
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_and_b32 s1, s0, 15
+; GFX10-NEXT:    s_lshl_b32 s0, s0, 2
+; GFX10-NEXT:    s_lshl_b32 s1, s1, 2
+; GFX10-NEXT:    s_add_u32 s0, 4, s0
+; GFX10-NEXT:    s_add_u32 s1, 4, s1
+; GFX10-NEXT:    scratch_store_dword off, v0, s0
+; GFX10-NEXT:    scratch_load_dword v0, off, s1
+; GFX10-NEXT:    s_endpgm
+bb:
+  %i = alloca [32 x float], align 4, addrspace(5)
+  %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
+  %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
+  %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
+  store volatile i32 15, i32 addrspace(5)* %i8, align 4
+  %i9 = and i32 %idx, 15
+  %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
+  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
+  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
+  ret void
+}
+
+define amdgpu_kernel void @store_load_vindex_kernel() {
+; GFX9-LABEL: store_load_vindex_kernel:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
+; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
+; GFX9-NEXT:    v_sub_u32_e32 v0, 0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 4
+; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
+; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-NEXT:    scratch_store_dword v1, v3, off
+; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: store_load_vindex_kernel:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_add_u32 s0, s0, s3
+; GFX10-NEXT:    s_addc_u32 s1, s1, 0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
+; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, 4
+; GFX10-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
+; GFX10-NEXT:    scratch_store_dword v0, v3, off
+; GFX10-NEXT:    scratch_load_dword v0, v1, off offset:124
+; GFX10-NEXT:    s_endpgm
+bb:
+  %i = alloca [32 x float], align 4, addrspace(5)
+  %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
+  %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %i3 = zext i32 %i2 to i64
+  %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2
+  %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
+  store volatile i32 15, i32 addrspace(5)* %i8, align 4
+  %i9 = sub nsw i32 31, %i2
+  %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
+  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
+  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
+  ret void
+}
+
+define void @store_load_vindex_foo(i32 %idx) {
+; GFX9-LABEL: store_load_vindex_foo:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
+; GFX9-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, s32
+; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-NEXT:    scratch_store_dword v1, v3, off
+; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT:    scratch_load_dword v0, v0, off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_vindex_foo:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_and_b32_e32 v1, 15, v0
+; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, s32
+; GFX10-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
+; GFX10-NEXT:    scratch_store_dword v0, v3, off
+; GFX10-NEXT:    scratch_load_dword v0, v1, off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  %i = alloca [32 x float], align 4, addrspace(5)
+  %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
+  %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
+  %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
+  store volatile i32 15, i32 addrspace(5)* %i8, align 4
+  %i9 = and i32 %idx, 15
+  %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
+  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
+  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
+  ret void
+}
+
+define void @private_ptr_foo(float addrspace(5)* nocapture %arg) {
+; GFX9-LABEL: private_ptr_foo:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0x41200000
+; GFX9-NEXT:    scratch_store_dword v0, v1, off offset:4
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: private_ptr_foo:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_mov_b32_e32 v1, 0x41200000
+; GFX10-NEXT:    scratch_store_dword v0, v1, off offset:4
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %gep = getelementptr inbounds float, float addrspace(5)* %arg, i32 1
+  store float 1.000000e+01, float addrspace(5)* %gep, align 4
+  ret void
+}
+
+define amdgpu_kernel void @store_load_sindex_small_offset_kernel(i32 %idx) {
+; GFX9-LABEL: store_load_sindex_small_offset_kernel:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_load_dword s0, s[0:1], 0x24
+; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5
+; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0
+; GFX9-NEXT:    s_add_u32 s2, 4, 0
+; GFX9-NEXT:    v_mov_b32_e32 v0, 15
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_lshl_b32 s1, s0, 2
+; GFX9-NEXT:    s_and_b32 s0, s0, 15
+; GFX9-NEXT:    s_lshl_b32 s0, s0, 2
+; GFX9-NEXT:    s_add_u32 s1, 0x104, s1
+; GFX9-NEXT:    scratch_load_dword v1, off, s2
+; GFX9-NEXT:    scratch_store_dword off, v0, s1
+; GFX9-NEXT:    s_add_u32 s0, 0x104, s0
+; GFX9-NEXT:    scratch_load_dword v0, off, s0
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: store_load_sindex_small_offset_kernel:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_add_u32 s2, s2, s5
+; GFX10-NEXT:    s_addc_u32 s3, s3, 0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
+; GFX10-NEXT:    s_load_dword s0, s[0:1], 0x24
+; GFX10-NEXT:    s_add_u32 s1, 4, 0
+; GFX10-NEXT:    scratch_load_dword v0, off, s1
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, 15
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_and_b32 s1, s0, 15
+; GFX10-NEXT:    s_lshl_b32 s0, s0, 2
+; GFX10-NEXT:    s_lshl_b32 s1, s1, 2
+; GFX10-NEXT:    s_add_u32 s0, 0x104, s0
+; GFX10-NEXT:    s_add_u32 s1, 0x104, s1
+; GFX10-NEXT:    scratch_store_dword off, v0, s0
+; GFX10-NEXT:    scratch_load_dword v0, off, s1
+; GFX10-NEXT:    s_endpgm
+bb:
+  %padding = alloca [64 x i32], align 4, addrspace(5)
+  %i = alloca [32 x float], align 4, addrspace(5)
+  %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
+  %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
+  %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
+  %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
+  %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
+  store volatile i32 15, i32 addrspace(5)* %i8, align 4
+  %i9 = and i32 %idx, 15
+  %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
+  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
+  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
+  ret void
+}
+
+define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
+; GFX9-LABEL: store_load_vindex_small_offset_kernel:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
+; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
+; GFX9-NEXT:    s_add_u32 s0, 4, 0
+; GFX9-NEXT:    scratch_load_dword v1, off, s0
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
+; GFX9-NEXT:    v_sub_u32_e32 v0, 0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x104
+; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-NEXT:    scratch_store_dword v1, v3, off
+; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: store_load_vindex_small_offset_kernel:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_add_u32 s0, s0, s3
+; GFX10-NEXT:    s_addc_u32 s1, s1, 0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
+; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0x104
+; GFX10-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-NEXT:    s_add_u32 s0, 4, 0
+; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
+; GFX10-NEXT:    scratch_load_dword v2, off, s0
+; GFX10-NEXT:    scratch_store_dword v0, v3, off
+; GFX10-NEXT:    scratch_load_dword v0, v1, off offset:124
+; GFX10-NEXT:    s_endpgm
+bb:
+  %padding = alloca [64 x i32], align 4, addrspace(5)
+  %i = alloca [32 x float], align 4, addrspace(5)
+  %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
+  %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
+  %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
+  %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %i3 = zext i32 %i2 to i64
+  %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2
+  %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
+  store volatile i32 15, i32 addrspace(5)* %i8, align 4
+  %i9 = sub nsw i32 31, %i2
+  %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
+  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
+  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
+  ret void
+}
+
+define void @store_load_vindex_small_offset_foo(i32 %idx) {
+; GFX9-LABEL: store_load_vindex_small_offset_foo:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_add_u32 s0, s32, 0
+; GFX9-NEXT:    scratch_load_dword v1, off, s0
+; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x100
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
+; GFX9-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, vcc_hi
+; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-NEXT:    scratch_store_dword v1, v3, off
+; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT:    scratch_load_dword v0, v0, off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_vindex_small_offset_foo:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_and_b32_e32 v1, 15, v0
+; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x100
+; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, vcc_lo
+; GFX10-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
+; GFX10-NEXT:    s_add_u32 s0, s32, 0
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
+; GFX10-NEXT:    scratch_load_dword v2, off, s0
+; GFX10-NEXT:    scratch_store_dword v0, v3, off
+; GFX10-NEXT:    scratch_load_dword v0, v1, off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  %padding = alloca [64 x i32], align 4, addrspace(5)
+  %i = alloca [32 x float], align 4, addrspace(5)
+  %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
+  %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
+  %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
+  %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
+  %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
+  store volatile i32 15, i32 addrspace(5)* %i8, align 4
+  %i9 = and i32 %idx, 15
+  %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
+  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
+  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
+  ret void
+}
+
+define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) {
+; GFX9-LABEL: store_load_sindex_large_offset_kernel:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_load_dword s0, s[0:1], 0x24
+; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5
+; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0
+; GFX9-NEXT:    s_add_u32 s2, 4, 0
+; GFX9-NEXT:    v_mov_b32_e32 v0, 15
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_lshl_b32 s1, s0, 2
+; GFX9-NEXT:    s_and_b32 s0, s0, 15
+; GFX9-NEXT:    s_lshl_b32 s0, s0, 2
+; GFX9-NEXT:    s_add_u32 s1, 0x4004, s1
+; GFX9-NEXT:    scratch_load_dword v1, off, s2
+; GFX9-NEXT:    scratch_store_dword off, v0, s1
+; GFX9-NEXT:    s_add_u32 s0, 0x4004, s0
+; GFX9-NEXT:    scratch_load_dword v0, off, s0
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: store_load_sindex_large_offset_kernel:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_add_u32 s2, s2, s5
+; GFX10-NEXT:    s_addc_u32 s3, s3, 0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
+; GFX10-NEXT:    s_load_dword s0, s[0:1], 0x24
+; GFX10-NEXT:    s_add_u32 s1, 4, 0
+; GFX10-NEXT:    scratch_load_dword v0, off, s1
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    v_mov_b32_e32 v0, 15
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    s_and_b32 s1, s0, 15
+; GFX10-NEXT:    s_lshl_b32 s0, s0, 2
+; GFX10-NEXT:    s_lshl_b32 s1, s1, 2
+; GFX10-NEXT:    s_add_u32 s0, 0x4004, s0
+; GFX10-NEXT:    s_add_u32 s1, 0x4004, s1
+; GFX10-NEXT:    scratch_store_dword off, v0, s0
+; GFX10-NEXT:    scratch_load_dword v0, off, s1
+; GFX10-NEXT:    s_endpgm
+bb:
+  %padding = alloca [4096 x i32], align 4, addrspace(5)
+  %i = alloca [32 x float], align 4, addrspace(5)
+  %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
+  %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
+  %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
+  %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
+  %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
+  store volatile i32 15, i32 addrspace(5)* %i8, align 4
+  %i9 = and i32 %idx, 15
+  %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
+  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
+  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
+  ret void
+}
+
+define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
+; GFX9-LABEL: store_load_vindex_large_offset_kernel:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
+; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
+; GFX9-NEXT:    s_add_u32 s0, 4, 0
+; GFX9-NEXT:    scratch_load_dword v1, off, s0
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
+; GFX9-NEXT:    v_sub_u32_e32 v0, 0, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0x4004
+; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-NEXT:    scratch_store_dword v1, v3, off
+; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:124
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: store_load_vindex_large_offset_kernel:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_add_u32 s0, s0, s3
+; GFX10-NEXT:    s_addc_u32 s1, s1, 0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
+; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0x4004
+; GFX10-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-NEXT:    s_add_u32 s0, 4, 0
+; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
+; GFX10-NEXT:    scratch_load_dword v2, off, s0
+; GFX10-NEXT:    scratch_store_dword v0, v3, off
+; GFX10-NEXT:    scratch_load_dword v0, v1, off offset:124
+; GFX10-NEXT:    s_endpgm
+bb:
+  %padding = alloca [4096 x i32], align 4, addrspace(5)
+  %i = alloca [32 x float], align 4, addrspace(5)
+  %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
+  %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
+  %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
+  %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %i3 = zext i32 %i2 to i64
+  %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2
+  %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
+  store volatile i32 15, i32 addrspace(5)* %i8, align 4
+  %i9 = sub nsw i32 31, %i2
+  %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
+  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
+  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
+  ret void
+}
+
+define void @store_load_vindex_large_offset_foo(i32 %idx) {
+; GFX9-LABEL: store_load_vindex_large_offset_foo:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_add_u32 s0, s32, 0
+; GFX9-NEXT:    scratch_load_dword v1, off, s0
+; GFX9-NEXT:    s_add_u32 vcc_hi, s32, 0x4000
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 2, v0
+; GFX9-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX9-NEXT:    v_mov_b32_e32 v2, vcc_hi
+; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
+; GFX9-NEXT:    v_mov_b32_e32 v3, 15
+; GFX9-NEXT:    scratch_store_dword v1, v3, off
+; GFX9-NEXT:    v_add_u32_e32 v0, v2, v0
+; GFX9-NEXT:    scratch_load_dword v0, v0, off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_vindex_large_offset_foo:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_and_b32_e32 v1, 15, v0
+; GFX10-NEXT:    s_add_u32 vcc_lo, s32, 0x4000
+; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT:    v_mov_b32_e32 v2, vcc_lo
+; GFX10-NEXT:    v_mov_b32_e32 v3, 15
+; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 2, v1
+; GFX10-NEXT:    s_add_u32 s0, s32, 0
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, v2, v0
+; GFX10-NEXT:    v_add_nc_u32_e32 v1, v2, v1
+; GFX10-NEXT:    scratch_load_dword v2, off, s0
+; GFX10-NEXT:    scratch_store_dword v0, v3, off
+; GFX10-NEXT:    scratch_load_dword v0, v1, off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  %padding = alloca [4096 x i32], align 4, addrspace(5)
+  %i = alloca [32 x float], align 4, addrspace(5)
+  %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
+  %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
+  %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
+  %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
+  %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
+  store volatile i32 15, i32 addrspace(5)* %i8, align 4
+  %i9 = and i32 %idx, 15
+  %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
+  %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
+  %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
+  ret void
+}
+
+define amdgpu_kernel void @store_load_large_imm_offset_kernel() {
+; GFX9-LABEL: store_load_large_imm_offset_kernel:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s0, s3
+; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s1, 0
+; GFX9-NEXT:    v_mov_b32_e32 v0, 13
+; GFX9-NEXT:    s_add_u32 s0, 4, 0
+; GFX9-NEXT:    scratch_store_dword off, v0, s0
+; GFX9-NEXT:    s_movk_i32 s0, 0x3e80
+; GFX9-NEXT:    v_mov_b32_e32 v0, 15
+; GFX9-NEXT:    s_add_u32 s0, 4, s0
+; GFX9-NEXT:    scratch_store_dword off, v0, s0
+; GFX9-NEXT:    scratch_load_dword v0, off, s0
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: store_load_large_imm_offset_kernel:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_add_u32 s0, s0, s3
+; GFX10-NEXT:    s_addc_u32 s1, s1, 0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
+; GFX10-NEXT:    v_mov_b32_e32 v0, 13
+; GFX10-NEXT:    v_mov_b32_e32 v1, 15
+; GFX10-NEXT:    s_movk_i32 s0, 0x3e80
+; GFX10-NEXT:    s_add_u32 s1, 4, 0
+; GFX10-NEXT:    s_add_u32 s0, 4, s0
+; GFX10-NEXT:    scratch_store_dword off, v0, s1
+; GFX10-NEXT:    scratch_store_dword off, v1, s0
+; GFX10-NEXT:    scratch_load_dword v0, off, s0
+; GFX10-NEXT:    s_endpgm
+bb:
+  %i = alloca [4096 x i32], align 4, addrspace(5)
+  %i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef
+  store volatile i32 13, i32 addrspace(5)* %i1, align 4
+  %i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
+  store volatile i32 15, i32 addrspace(5)* %i7, align 4
+  %i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
+  %i12 = load volatile i32, i32 addrspace(5)* %i10, align 4
+  ret void
+}
+
+define void @store_load_large_imm_offset_foo() {
+; GFX9-LABEL: store_load_large_imm_offset_foo:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, 13
+; GFX9-NEXT:    s_add_u32 s0, s32, 0
+; GFX9-NEXT:    scratch_store_dword off, v0, s0
+; GFX9-NEXT:    s_movk_i32 s0, 0x3e80
+; GFX9-NEXT:    v_mov_b32_e32 v0, 15
+; GFX9-NEXT:    s_add_u32 s0, s32, s0
+; GFX9-NEXT:    scratch_store_dword off, v0, s0
+; GFX9-NEXT:    scratch_load_dword v0, off, s0
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_large_imm_offset_foo:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_mov_b32_e32 v0, 13
+; GFX10-NEXT:    v_mov_b32_e32 v1, 15
+; GFX10-NEXT:    s_movk_i32 s0, 0x3e80
+; GFX10-NEXT:    s_add_u32 s1, s32, 0
+; GFX10-NEXT:    s_add_u32 s0, s32, s0
+; GFX10-NEXT:    scratch_store_dword off, v0, s1
+; GFX10-NEXT:    scratch_store_dword off, v1, s0
+; GFX10-NEXT:    scratch_load_dword v0, off, s0
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  %i = alloca [4096 x i32], align 4, addrspace(5)
+  %i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef
+  store volatile i32 13, i32 addrspace(5)* %i1, align 4
+  %i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
+  store volatile i32 15, i32 addrspace(5)* %i7, align 4
+  %i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
+  %i12 = load volatile i32, i32 addrspace(5)* %i10, align 4
+  ret void
+}
+
+define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
+; GFX9-LABEL: store_load_vidx_sidx_offset:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_load_dword s0, s[0:1], 0x24
+; GFX9-NEXT:    s_add_u32 flat_scratch_lo, s2, s5
+; GFX9-NEXT:    s_addc_u32 flat_scratch_hi, s3, 0
+; GFX9-NEXT:    v_mov_b32_e32 v1, 15
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_add_lshl_u32 v0, s0, v0, 2
+; GFX9-NEXT:    v_add_u32_e32 v0, 4, v0
+; GFX9-NEXT:    scratch_store_dword v0, v1, off offset:1024
+; GFX9-NEXT:    scratch_load_dword v0, v0, off offset:1024
+; GFX9-NEXT:    s_endpgm
+;
+; GFX10-LABEL: store_load_vidx_sidx_offset:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_add_u32 s2, s2, s5
+; GFX10-NEXT:    s_addc_u32 s3, s3, 0
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
+; GFX10-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
+; GFX10-NEXT:    s_load_dword s0, s[0:1], 0x24
+; GFX10-NEXT:    v_mov_b32_e32 v1, 15
+; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX10-NEXT:    v_add_lshl_u32 v0, s0, v0, 2
+; GFX10-NEXT:    v_add_nc_u32_e32 v0, 4, v0
+; GFX10-NEXT:    scratch_store_dword v0, v1, off offset:1024
+; GFX10-NEXT:    scratch_load_dword v0, v0, off offset:1024
+; GFX10-NEXT:    s_endpgm
+bb:
+  %alloca = alloca [32 x i32], align 4, addrspace(5)
+  %vidx = tail call i32 @llvm.amdgcn.workitem.id.x()
+  %add1 = add nsw i32 %sidx, %vidx
+  %add2 = add nsw i32 %add1, 256
+  %gep = getelementptr inbounds [32 x i32], [32 x i32] addrspace(5)* %alloca, i32 0, i32 %add2
+  store volatile i32 15, i32 addrspace(5)* %gep, align 4
+  %load = load volatile i32, i32 addrspace(5)* %gep, align 4
+  ret void
+}
+
+define void @store_load_i64_aligned(i64 addrspace(5)* nocapture %arg) {
+; GFX9-LABEL: store_load_i64_aligned:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, 15
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    scratch_store_dwordx2 v0, v[1:2], off
+; GFX9-NEXT:    scratch_load_dwordx2 v[0:1], v0, off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_i64_aligned:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_mov_b32_e32 v1, 15
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    scratch_store_dwordx2 v0, v[1:2], off
+; GFX10-NEXT:    scratch_load_dwordx2 v[0:1], v0, off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  store volatile i64 15, i64 addrspace(5)* %arg, align 8
+  %load = load volatile i64, i64 addrspace(5)* %arg, align 8
+  ret void
+}
+
+define void @store_load_i64_unaligned(i64 addrspace(5)* nocapture %arg) {
+; GFX9-LABEL: store_load_i64_unaligned:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v1, 15
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    scratch_store_dwordx2 v0, v[1:2], off
+; GFX9-NEXT:    scratch_load_dwordx2 v[0:1], v0, off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_i64_unaligned:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_mov_b32_e32 v1, 15
+; GFX10-NEXT:    v_mov_b32_e32 v2, 0
+; GFX10-NEXT:    scratch_store_dwordx2 v0, v[1:2], off
+; GFX10-NEXT:    scratch_load_dwordx2 v[0:1], v0, off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  store volatile i64 15, i64 addrspace(5)* %arg, align 1
+  %load = load volatile i64, i64 addrspace(5)* %arg, align 1
+  ret void
+}
+
+define void @store_load_v3i32_unaligned(<3 x i32> addrspace(5)* nocapture %arg) {
+; GFX9-LABEL: store_load_v3i32_unaligned:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_mov_b32 s2, 3
+; GFX9-NEXT:    s_mov_b32 s1, 2
+; GFX9-NEXT:    s_mov_b32 s0, 1
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
+; GFX9-NEXT:    v_mov_b32_e32 v2, s1
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NEXT:    scratch_store_dwordx3 v0, v[1:3], off
+; GFX9-NEXT:    scratch_load_dwordx3 v[0:2], v0, off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_v3i32_unaligned:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_mov_b32 s2, 3
+; GFX10-NEXT:    s_mov_b32 s1, 2
+; GFX10-NEXT:    s_mov_b32 s0, 1
+; GFX10-NEXT:    v_mov_b32_e32 v3, s2
+; GFX10-NEXT:    v_mov_b32_e32 v2, s1
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
+; GFX10-NEXT:    scratch_store_dwordx3 v0, v[1:3], off
+; GFX10-NEXT:    scratch_load_dwordx3 v[0:2], v0, off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  store volatile <3 x i32> <i32 1, i32 2, i32 3>, <3 x i32> addrspace(5)* %arg, align 1
+  %load = load volatile <3 x i32>, <3 x i32> addrspace(5)* %arg, align 1
+  ret void
+}
+
+define void @store_load_v4i32_unaligned(<4 x i32> addrspace(5)* nocapture %arg) {
+; GFX9-LABEL: store_load_v4i32_unaligned:
+; GFX9:       ; %bb.0: ; %bb
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_mov_b32 s3, 4
+; GFX9-NEXT:    s_mov_b32 s2, 3
+; GFX9-NEXT:    s_mov_b32 s1, 2
+; GFX9-NEXT:    s_mov_b32 s0, 1
+; GFX9-NEXT:    v_mov_b32_e32 v4, s3
+; GFX9-NEXT:    v_mov_b32_e32 v3, s2
+; GFX9-NEXT:    v_mov_b32_e32 v2, s1
+; GFX9-NEXT:    v_mov_b32_e32 v1, s0
+; GFX9-NEXT:    scratch_store_dwordx4 v0, v[1:4], off
+; GFX9-NEXT:    scratch_load_dwordx4 v[0:3], v0, off
+; GFX9-NEXT:    s_waitcnt vmcnt(0)
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: store_load_v4i32_unaligned:
+; GFX10:       ; %bb.0: ; %bb
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_mov_b32 s3, 4
+; GFX10-NEXT:    s_mov_b32 s2, 3
+; GFX10-NEXT:    s_mov_b32 s1, 2
+; GFX10-NEXT:    s_mov_b32 s0, 1
+; GFX10-NEXT:    v_mov_b32_e32 v4, s3
+; GFX10-NEXT:    v_mov_b32_e32 v3, s2
+; GFX10-NEXT:    v_mov_b32_e32 v2, s1
+; GFX10-NEXT:    v_mov_b32_e32 v1, s0
+; GFX10-NEXT:    scratch_store_dwordx4 v0, v[1:4], off
+; GFX10-NEXT:    scratch_load_dwordx4 v[0:3], v0, off
+; GFX10-NEXT:    s_waitcnt vmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+bb:
+  store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %arg, align 1
+  %load = load volatile <4 x i32>, <4 x i32> addrspace(5)* %arg, align 1
+  ret void
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
index 5fc598b3dcbfb..d4fac6bcc8eb3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll
@@ -999,21 +999,51 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32(i32* %out, i32* %ptr) #0 {
 }
 
 define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(i32* %out, i32* %ptr) #0 {
-; GCN-LABEL: flat_atomic_inc_ret_i32_offset:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-NEXT:    v_mov_b32_e32 v2, 42
-; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_add_u32 s2, s2, 16
-; GCN-NEXT:    s_addc_u32 s3, s3, 0
-; GCN-NEXT:    v_mov_b32_e32 v0, s2
-; GCN-NEXT:    v_mov_b32_e32 v1, s3
-; GCN-NEXT:    flat_atomic_inc v2, v[0:1], v2 glc
-; GCN-NEXT:    v_mov_b32_e32 v0, s0
-; GCN-NEXT:    v_mov_b32_e32 v1, s1
-; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN-NEXT:    flat_store_dword v[0:1], v2
-; GCN-NEXT:    s_endpgm
+; CI-LABEL: flat_atomic_inc_ret_i32_offset:
+; CI:       ; %bb.0:
+; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
+; CI-NEXT:    v_mov_b32_e32 v2, 42
+; CI-NEXT:    s_waitcnt lgkmcnt(0)
+; CI-NEXT:    s_add_u32 s2, s2, 16
+; CI-NEXT:    s_addc_u32 s3, s3, 0
+; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v1, s3
+; CI-NEXT:    flat_atomic_inc v2, v[0:1], v2 glc
+; CI-NEXT:    v_mov_b32_e32 v0, s0
+; CI-NEXT:    v_mov_b32_e32 v1, s1
+; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; CI-NEXT:    flat_store_dword v[0:1], v2
+; CI-NEXT:    s_endpgm
+;
+; VI-LABEL: flat_atomic_inc_ret_i32_offset:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
+; VI-NEXT:    v_mov_b32_e32 v2, 42
+; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    s_add_u32 s2, s2, 16
+; VI-NEXT:    s_addc_u32 s3, s3, 0
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    flat_atomic_inc v2, v[0:1], v2 glc
+; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    flat_store_dword v[0:1], v2
+; VI-NEXT:    s_endpgm
+;
+; GFX9-LABEL: flat_atomic_inc_ret_i32_offset:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 42
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NEXT:    v_mov_b32_e32 v1, s3
+; GFX9-NEXT:    flat_atomic_inc v2, v[0:1], v2 offset:16 glc
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    flat_store_dword v[0:1], v2
+; GFX9-NEXT:    s_endpgm
   %gep = getelementptr i32, i32* %ptr, i32 4
   %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
   store i32 %result, i32* %out
@@ -1035,17 +1065,39 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32(i32* %ptr) nounwind {
 }
 
 define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(i32* %ptr) nounwind {
-; GCN-LABEL: flat_atomic_inc_noret_i32_offset:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GCN-NEXT:    v_mov_b32_e32 v2, 42
-; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_add_u32 s0, s0, 16
-; GCN-NEXT:    s_addc_u32 s1, s1, 0
-; GCN-NEXT:    v_mov_b32_e32 v0, s0
-; GCN-NEXT:    v_mov_b32_e32 v1, s1
-; GCN-NEXT:    flat_atomic_inc v0, v[0:1], v2 glc
-; GCN-NEXT:    s_endpgm
+; CI-LABEL: flat_atomic_inc_noret_i32_offset:
+; CI:       ; %bb.0:
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CI-NEXT:    v_mov_b32_e32 v2, 42
+; CI-NEXT:    s_waitcnt lgkmcnt(0)
+; CI-NEXT:    s_add_u32 s0, s0, 16
+; CI-NEXT:    s_addc_u32 s1, s1, 0
+; CI-NEXT:    v_mov_b32_e32 v0, s0
+; CI-NEXT:    v_mov_b32_e32 v1, s1
+; CI-NEXT:    flat_atomic_inc v0, v[0:1], v2 glc
+; CI-NEXT:    s_endpgm
+;
+; VI-LABEL: flat_atomic_inc_noret_i32_offset:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; VI-NEXT:    v_mov_b32_e32 v2, 42
+; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    s_add_u32 s0, s0, 16
+; VI-NEXT:    s_addc_u32 s1, s1, 0
+; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    flat_atomic_inc v0, v[0:1], v2 glc
+; VI-NEXT:    s_endpgm
+;
+; GFX9-LABEL: flat_atomic_inc_noret_i32_offset:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX9-NEXT:    v_mov_b32_e32 v2, 42
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v0, s0
+; GFX9-NEXT:    v_mov_b32_e32 v1, s1
+; GFX9-NEXT:    flat_atomic_inc v0, v[0:1], v2 offset:16 glc
+; GFX9-NEXT:    s_endpgm
   %gep = getelementptr i32, i32* %ptr, i32 4
   %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
   ret void
@@ -1097,22 +1149,20 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32*
 ; GFX9-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s0
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 20, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_mov_b32_e32 v2, s0
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 42
-; GFX9-NEXT:    flat_atomic_inc v2, v[2:3], v4 glc
+; GFX9-NEXT:    flat_atomic_inc v0, v[0:1], v4 offset:20 glc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    flat_store_dword v[0:1], v2
+; GFX9-NEXT:    flat_store_dword v[2:3], v0
 ; GFX9-NEXT:    s_endpgm
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.tid = getelementptr i32, i32* %ptr, i32 %id
@@ -1163,10 +1213,8 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 20, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 42
-; GFX9-NEXT:    flat_atomic_inc v0, v[0:1], v2 glc
+; GFX9-NEXT:    flat_atomic_inc v0, v[0:1], v2 offset:20 glc
 ; GFX9-NEXT:    s_endpgm
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.tid = getelementptr i32, i32* %ptr, i32 %id
@@ -1257,22 +1305,54 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64(i64* %out, i64* %ptr) #0 {
 }
 
 define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64* %out, i64* %ptr) #0 {
-; GCN-LABEL: flat_atomic_inc_ret_i64_offset:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-NEXT:    v_mov_b32_e32 v2, 42
-; GCN-NEXT:    v_mov_b32_e32 v3, 0
-; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_add_u32 s2, s2, 32
-; GCN-NEXT:    s_addc_u32 s3, s3, 0
-; GCN-NEXT:    v_mov_b32_e32 v0, s2
-; GCN-NEXT:    v_mov_b32_e32 v1, s3
-; GCN-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
-; GCN-NEXT:    v_mov_b32_e32 v3, s1
-; GCN-NEXT:    v_mov_b32_e32 v2, s0
-; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
-; GCN-NEXT:    s_endpgm
+; CI-LABEL: flat_atomic_inc_ret_i64_offset:
+; CI:       ; %bb.0:
+; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
+; CI-NEXT:    v_mov_b32_e32 v2, 42
+; CI-NEXT:    v_mov_b32_e32 v3, 0
+; CI-NEXT:    s_waitcnt lgkmcnt(0)
+; CI-NEXT:    s_add_u32 s2, s2, 32
+; CI-NEXT:    s_addc_u32 s3, s3, 0
+; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v1, s3
+; CI-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
+; CI-NEXT:    v_mov_b32_e32 v3, s1
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; CI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; CI-NEXT:    s_endpgm
+;
+; VI-LABEL: flat_atomic_inc_ret_i64_offset:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
+; VI-NEXT:    v_mov_b32_e32 v2, 42
+; VI-NEXT:    v_mov_b32_e32 v3, 0
+; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    s_add_u32 s2, s2, 32
+; VI-NEXT:    s_addc_u32 s3, s3, 0
+; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v1, s3
+; VI-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
+; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; VI-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; VI-NEXT:    s_endpgm
+;
+; GFX9-LABEL: flat_atomic_inc_ret_i64_offset:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-NEXT:    v_mov_b32_e32 v0, 42
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v2, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s3
+; GFX9-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] offset:32 glc
+; GFX9-NEXT:    v_mov_b32_e32 v3, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s0
+; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
+; GFX9-NEXT:    s_endpgm
   %gep = getelementptr i64, i64* %ptr, i32 4
   %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
   store i64 %result, i64* %out
@@ -1295,18 +1375,42 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64(i64* %ptr) nounwind {
 }
 
 define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(i64* %ptr) nounwind {
-; GCN-LABEL: flat_atomic_inc_noret_i64_offset:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GCN-NEXT:    v_mov_b32_e32 v2, 42
-; GCN-NEXT:    v_mov_b32_e32 v3, 0
-; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_add_u32 s0, s0, 32
-; GCN-NEXT:    s_addc_u32 s1, s1, 0
-; GCN-NEXT:    v_mov_b32_e32 v0, s0
-; GCN-NEXT:    v_mov_b32_e32 v1, s1
-; GCN-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
-; GCN-NEXT:    s_endpgm
+; CI-LABEL: flat_atomic_inc_noret_i64_offset:
+; CI:       ; %bb.0:
+; CI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; CI-NEXT:    v_mov_b32_e32 v2, 42
+; CI-NEXT:    v_mov_b32_e32 v3, 0
+; CI-NEXT:    s_waitcnt lgkmcnt(0)
+; CI-NEXT:    s_add_u32 s0, s0, 32
+; CI-NEXT:    s_addc_u32 s1, s1, 0
+; CI-NEXT:    v_mov_b32_e32 v0, s0
+; CI-NEXT:    v_mov_b32_e32 v1, s1
+; CI-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
+; CI-NEXT:    s_endpgm
+;
+; VI-LABEL: flat_atomic_inc_noret_i64_offset:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; VI-NEXT:    v_mov_b32_e32 v2, 42
+; VI-NEXT:    v_mov_b32_e32 v3, 0
+; VI-NEXT:    s_waitcnt lgkmcnt(0)
+; VI-NEXT:    s_add_u32 s0, s0, 32
+; VI-NEXT:    s_addc_u32 s1, s1, 0
+; VI-NEXT:    v_mov_b32_e32 v0, s0
+; VI-NEXT:    v_mov_b32_e32 v1, s1
+; VI-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
+; VI-NEXT:    s_endpgm
+;
+; GFX9-LABEL: flat_atomic_inc_noret_i64_offset:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX9-NEXT:    v_mov_b32_e32 v0, 42
+; GFX9-NEXT:    v_mov_b32_e32 v1, 0
+; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    v_mov_b32_e32 v3, s1
+; GFX9-NEXT:    v_mov_b32_e32 v2, s0
+; GFX9-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] offset:32 glc
+; GFX9-NEXT:    s_endpgm
   %gep = getelementptr i64, i64* %ptr, i32 4
   %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
   ret void
@@ -1360,23 +1464,21 @@ define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64*
 ; GFX9-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
+; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v0, s0
-; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, 40, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_mov_b32_e32 v2, s0
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 42
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
-; GFX9-NEXT:    flat_atomic_inc_x2 v[2:3], v[2:3], v[4:5] glc
+; GFX9-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] offset:40 glc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
+; GFX9-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; GFX9-NEXT:    s_endpgm
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.tid = getelementptr i64, i64* %ptr, i32 %id
@@ -1428,12 +1530,10 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 40, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 42
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v3, 0
-; GFX9-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
+; GFX9-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] offset:40 glc
 ; GFX9-NEXT:    s_endpgm
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.tid = getelementptr i64, i64* %ptr, i32 %id
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll
index 70651280003e5..4f0c1586cad19 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.fadd.ll
@@ -16,13 +16,7 @@ define void @global_atomic_fadd_f32_off_2048(float addrspace(1)* %ptr, float %da
 ; GFX908-LABEL: global_atomic_fadd_f32_off_2048:
 ; GFX908:       ; %bb.0:
 ; GFX908-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT:    s_movk_i32 s4, 0x800
-; GFX908-NEXT:    s_mov_b32 s5, 0
-; GFX908-NEXT:    v_mov_b32_e32 v3, s4
-; GFX908-NEXT:    v_mov_b32_e32 v4, s5
-; GFX908-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
-; GFX908-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
-; GFX908-NEXT:    global_atomic_add_f32 v[0:1], v2, off
+; GFX908-NEXT:    global_atomic_add_f32 v[0:1], v2, off offset:2048
 ; GFX908-NEXT:    s_waitcnt vmcnt(0)
 ; GFX908-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr float, float addrspace(1)* %ptr, i64 512
@@ -34,13 +28,7 @@ define void @global_atomic_fadd_f32_off_neg2047(float addrspace(1)* %ptr, float
 ; GFX908-LABEL: global_atomic_fadd_f32_off_neg2047:
 ; GFX908:       ; %bb.0:
 ; GFX908-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT:    s_mov_b32 s4, 0xfffff804
-; GFX908-NEXT:    s_mov_b32 s5, -1
-; GFX908-NEXT:    v_mov_b32_e32 v3, s4
-; GFX908-NEXT:    v_mov_b32_e32 v4, s5
-; GFX908-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
-; GFX908-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
-; GFX908-NEXT:    global_atomic_add_f32 v[0:1], v2, off
+; GFX908-NEXT:    global_atomic_add_f32 v[0:1], v2, off offset:-2044
 ; GFX908-NEXT:    s_waitcnt vmcnt(0)
 ; GFX908-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr float, float addrspace(1)* %ptr, i64 -511
@@ -54,12 +42,10 @@ define amdgpu_kernel void @global_atomic_fadd_f32_off_ss(float addrspace(1)* %pt
 ; GFX908-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
 ; GFX908-NEXT:    s_load_dword s2, s[4:5], 0x8
 ; GFX908-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX908-NEXT:    s_add_u32 s0, s0, 0x800
-; GFX908-NEXT:    s_addc_u32 s1, s1, 0
 ; GFX908-NEXT:    v_mov_b32_e32 v0, s0
-; GFX908-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX908-NEXT:    v_mov_b32_e32 v2, s2
-; GFX908-NEXT:    global_atomic_add_f32 v[0:1], v2, off
+; GFX908-NEXT:    v_mov_b32_e32 v1, s1
+; GFX908-NEXT:    global_atomic_add_f32 v[0:1], v2, off offset:2048
 ; GFX908-NEXT:    s_endpgm
   %gep = getelementptr float, float addrspace(1)* %ptr, i64 512
   %ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %gep, float %data)
@@ -81,13 +67,7 @@ define void @global_atomic_fadd_v2f16_off_neg2047(<2 x half> addrspace(1)* %ptr,
 ; GFX908-LABEL: global_atomic_fadd_v2f16_off_neg2047:
 ; GFX908:       ; %bb.0:
 ; GFX908-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX908-NEXT:    s_mov_b32 s4, 0xfffff804
-; GFX908-NEXT:    s_mov_b32 s5, -1
-; GFX908-NEXT:    v_mov_b32_e32 v3, s4
-; GFX908-NEXT:    v_mov_b32_e32 v4, s5
-; GFX908-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
-; GFX908-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
-; GFX908-NEXT:    global_atomic_pk_add_f16 v[0:1], v2, off
+; GFX908-NEXT:    global_atomic_pk_add_f16 v[0:1], v2, off offset:-2044
 ; GFX908-NEXT:    s_waitcnt vmcnt(0)
 ; GFX908-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr <2 x half>, <2 x half> addrspace(1)* %ptr, i64 -511
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
index 291f40e4f22a7..ff6467afde03d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
@@ -18,54 +18,52 @@ define <3 x i32> @v_load_constant_v3i32_align1(<3 x i32> addrspace(4)* %ptr) {
 ; GFX9-NOUNALIGNED-LABEL: v_load_constant_v3i32_align1:
 ; GFX9-NOUNALIGNED:       ; %bb.0:
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NOUNALIGNED-NEXT:    v_add_co_u32_e32 v2, vcc, 11, v0
-; GFX9-NOUNALIGNED-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v0, v[0:1], off
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v1, v[2:3], off offset:-10
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v4, v[2:3], off offset:-9
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v5, v[2:3], off offset:-8
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v6, v[2:3], off offset:-7
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v7, v[2:3], off offset:-6
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v8, v[2:3], off offset:-5
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v9, v[2:3], off offset:-4
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v10, v[2:3], off offset:-3
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v11, v[2:3], off offset:-2
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v12, v[2:3], off offset:-1
-; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v2, v[2:3], off
-; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v3, 0xff
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v2, v[0:1], off
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v3, v[0:1], off offset:1
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v4, v[0:1], off offset:2
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v5, v[0:1], off offset:3
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v6, v[0:1], off offset:4
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v7, v[0:1], off offset:5
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v8, v[0:1], off offset:6
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v9, v[0:1], off offset:7
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v10, v[0:1], off offset:8
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v11, v[0:1], off offset:9
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v12, v[0:1], off offset:10
+; GFX9-NOUNALIGNED-NEXT:    global_load_ubyte v0, v[0:1], off offset:11
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v1, 0xff
 ; GFX9-NOUNALIGNED-NEXT:    s_movk_i32 s4, 0xff
-; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v13, 8
 ; GFX9-NOUNALIGNED-NEXT:    s_mov_b32 s5, 8
+; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v13, 8
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(10)
-; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v3, s5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(9)
 ; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v4, s4, v4
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(8)
 ; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v5, s4, v5
-; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v0, v0, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v2, v2, s4, v3
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(6)
-; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v7, v13, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v7, s5, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(5)
-; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v8, v8, v3
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v8, v8, v1
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(4)
-; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v9, v9, v3
-; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 16, v4
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v9, v9, v1
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v3, 16, v4
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(2)
 ; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_sdwa v11, v13, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(1)
-; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v12, v12, v3
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v12, v12, v1
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, v2, v3
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v0, v0, v1
 ; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v4, 24, v5
-; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v5, v6, v3, v7
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v5, v6, s4, v7
 ; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v6, 16, v8
 ; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v7, 24, v9
-; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v3, v10, v3, v11
-; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v8, 16, v12
-; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 24, v2
-; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v0, v0, v1, v4
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v8, v10, v1, v11
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v10, 24, v0
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v9, 16, v12
+; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v0, v2, v3, v4
 ; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v1, v5, v6, v7
-; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v2, v3, v8, v2
+; GFX9-NOUNALIGNED-NEXT:    v_or3_b32 v2, v8, v9, v10
 ; GFX9-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX7-UNALIGNED-LABEL: v_load_constant_v3i32_align1:
@@ -156,28 +154,25 @@ define <3 x i32> @v_load_constant_v3i32_align2(<3 x i32> addrspace(4)* %ptr) {
 ; GFX9-NOUNALIGNED-LABEL: v_load_constant_v3i32_align2:
 ; GFX9-NOUNALIGNED:       ; %bb.0:
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NOUNALIGNED-NEXT:    v_add_co_u32_e32 v2, vcc, 10, v0
-; GFX9-NOUNALIGNED-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
-; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v0, v[0:1], off
-; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v1, v[2:3], off offset:-8
-; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v4, v[2:3], off offset:-6
-; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v5, v[2:3], off offset:-4
-; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v6, v[2:3], off offset:-2
-; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v2, v[2:3], off
-; GFX9-NOUNALIGNED-NEXT:    v_mov_b32_e32 v3, 0xffff
+; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v2, v[0:1], off
+; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v3, v[0:1], off offset:2
+; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v4, v[0:1], off offset:4
+; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v5, v[0:1], off offset:6
+; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v6, v[0:1], off offset:8
+; GFX9-NOUNALIGNED-NEXT:    global_load_ushort v0, v[0:1], off offset:10
 ; GFX9-NOUNALIGNED-NEXT:    s_mov_b32 s4, 0xffff
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(4)
-; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v1, s4, v3
 ; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(2)
-; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v5, v5, v3
-; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v3, s4, v5
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
 ; GFX9-NOUNALIGNED-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v2, v2, v3
-; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v0, v0, s4, v1
-; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v1, v4, v3, v5
-; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v2, v6, v3, v2
+; GFX9-NOUNALIGNED-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX9-NOUNALIGNED-NEXT:    v_lshlrev_b32_e32 v5, 16, v0
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v0, v2, s4, v1
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v1, v4, s4, v3
+; GFX9-NOUNALIGNED-NEXT:    v_and_or_b32 v2, v6, s4, v5
 ; GFX9-NOUNALIGNED-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX7-UNALIGNED-LABEL: v_load_constant_v3i32_align2:
diff --git a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
index 271f6c703980a..8e37b413ddf58 100644
--- a/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
+++ b/llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
@@ -271,16 +271,9 @@ define amdgpu_kernel void @vload2_private(i16 addrspace(1)* nocapture readonly %
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:    scratch_store_short off, v0, vcc_hi offset:8
 ; FLATSCR-NEXT:    s_mov_b32 vcc_hi, 0
-; FLATSCR-NEXT:    scratch_load_ushort v0, off, vcc_hi offset:4
+; FLATSCR-NEXT:    scratch_load_dword v0, off, vcc_hi offset:4
 ; FLATSCR-NEXT:    s_mov_b32 vcc_hi, 0
-; FLATSCR-NEXT:    scratch_load_ushort v3, off, vcc_hi offset:6
-; FLATSCR-NEXT:    s_mov_b32 vcc_hi, 0
-; FLATSCR-NEXT:    s_waitcnt vmcnt(1)
-; FLATSCR-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
-; FLATSCR-NEXT:    v_mov_b32_e32 v1, v3
-; FLATSCR-NEXT:    scratch_load_short_d16_hi v1, off, vcc_hi offset:8
-; FLATSCR-NEXT:    v_lshl_or_b32 v0, v3, 16, v0
+; FLATSCR-NEXT:    scratch_load_dword v1, off, vcc_hi offset:6
 ; FLATSCR-NEXT:    s_waitcnt vmcnt(0)
 ; FLATSCR-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; FLATSCR-NEXT:    s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir b/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
new file mode 100644
index 0000000000000..6bc94455e0a8b
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/csr-sgpr-spill-live-ins.mir
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx906 -run-pass=si-lower-sgpr-spills,prologepilog -o - %s | FileCheck %s
+
+# Make sure the modified CSR VGPRs are added as live-in to the entry
+# block.
+
+---
+name: def_csr_sgpr
+tracksRegLiveness: true
+machineFunctionInfo:
+  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
+  stackPtrOffsetReg: $sgpr32
+body: |
+  ; CHECK-LABEL: name: def_csr_sgpr
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $sgpr42, $sgpr43, $sgpr46, $sgpr47, $vgpr0
+  ; CHECK:   $vgpr0 = V_WRITELANE_B32 killed $sgpr42, 0, $vgpr0
+  ; CHECK:   $vgpr0 = V_WRITELANE_B32 killed $sgpr43, 1, $vgpr0
+  ; CHECK:   $vgpr0 = V_WRITELANE_B32 killed $sgpr46, 2, $vgpr0
+  ; CHECK:   $vgpr0 = V_WRITELANE_B32 killed $sgpr47, 3, $vgpr0
+  ; CHECK:   S_NOP 0
+  ; CHECK: bb.1:
+  ; CHECK:   liveins: $vgpr0
+  ; CHECK:   $sgpr42 = S_MOV_B32 0
+  ; CHECK:   $sgpr43 = S_MOV_B32 1
+  ; CHECK:   $sgpr46_sgpr47 = S_MOV_B64 2
+  bb.0:
+    S_NOP 0
+
+  bb.1:
+    $sgpr42 = S_MOV_B32 0
+    $sgpr43 = S_MOV_B32 1
+    $sgpr46_sgpr47 = S_MOV_B64 2
+...
diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir b/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
new file mode 100644
index 0000000000000..37cec99ae0ac9
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir
@@ -0,0 +1,88 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx900 -amdgpu-enable-flat-scratch -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+
+---
+name:            test_fold_fi_scratch_load_vgpr
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 }
+body:             |
+  bb.0.entry:
+    ; GCN-LABEL: name: test_fold_fi_scratch_load_vgpr
+    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
+    ; GCN: [[SCRATCH_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR %stack.0, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %stack.0, addrspace 5)
+    ; GCN: S_ENDPGM 0
+    %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
+    %1:vgpr_32 = SCRATCH_LOAD_DWORD %0:vgpr_32, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %stack.0, addrspace 5)
+    S_ENDPGM 0
+
+...
+
+---
+name:            test_fold_fi_scratch_load_sgpr
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 }
+body:             |
+  bb.0.entry:
+    ; GCN-LABEL: name: test_fold_fi_scratch_load_sgpr
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 %stack.0
+    ; GCN: [[SCRATCH_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR %stack.0, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %stack.0, addrspace 5)
+    ; GCN: S_ENDPGM 0
+    %0:sgpr_32 = S_MOV_B32 %stack.0
+    %1:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR %0:sgpr_32, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4 from %stack.0, addrspace 5)
+    S_ENDPGM 0
+
+...
+
+---
+name:            test_fold_fi_scratch_store_vgpr
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 }
+body:             |
+  bb.0.entry:
+    ; GCN-LABEL: name: test_fold_fi_scratch_store_vgpr
+    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
+    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN: SCRATCH_STORE_DWORD_SADDR [[DEF]], %stack.0, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %stack.0, addrspace 5)
+    ; GCN: S_ENDPGM 0
+    %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
+    %1:vgpr_32 = IMPLICIT_DEF
+    SCRATCH_STORE_DWORD %1:vgpr_32, %0:vgpr_32, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %stack.0, addrspace 5)
+    S_ENDPGM 0
+
+...
+
+---
+name:            test_no_fold_fi_scratch_store_vgpr
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 }
+body:             |
+  bb.0.entry:
+    ; GCN-LABEL: name: test_no_fold_fi_scratch_store_vgpr
+    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
+    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN: SCRATCH_STORE_DWORD [[V_MOV_B32_e32_]], [[DEF]], 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %stack.0, addrspace 5)
+    ; GCN: S_ENDPGM 0
+    %0:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
+    %1:vgpr_32 = IMPLICIT_DEF
+    SCRATCH_STORE_DWORD %0:vgpr_32, %1:vgpr_32, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %stack.0, addrspace 5)
+    S_ENDPGM 0
+
+...
+
+---
+name:            test_fold_fi_scratch_store_sgpr
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4 }
+body:             |
+  bb.0.entry:
+    ; GCN-LABEL: name: test_fold_fi_scratch_store_sgpr
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 %stack.0
+    ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN: SCRATCH_STORE_DWORD_SADDR [[DEF]], %stack.0, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %stack.0, addrspace 5)
+    ; GCN: S_ENDPGM 0
+    %0:sgpr_32 = S_MOV_B32 %stack.0
+    %1:vgpr_32 = IMPLICIT_DEF
+    SCRATCH_STORE_DWORD_SADDR %1:vgpr_32, %0:sgpr_32, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4 into %stack.0, addrspace 5)
+    S_ENDPGM 0
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
index 2c18e724278fd..fcd37840002a1 100644
--- a/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
+++ b/llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
@@ -166,7 +166,7 @@ define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* b
 
 ; GFX9: v_add_u32_e32 [[GEP:v[0-9]+]], 4, [[SP]]
 ; GFX9-MUBUF:   buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:4{{$}}
-; GFX9-FLATSCR: scratch_load_dword v{{[0-9]+}}, [[SP]], off offset:4{{$}}
+; GFX9-FLATSCR: scratch_load_dword v{{[0-9]+}}, off, s32 offset:4{{$}}
 
 ; GCN: ds_write_b32 v{{[0-9]+}}, [[GEP]]
 define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, i32 %arg2) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll b/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
index 4d03f827ac2f1..a9ebd798f33ac 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
@@ -533,10 +533,7 @@ define amdgpu_kernel void @kern_lds_ptr(i32 addrspace(3)* %lds) #0 {
 define amdgpu_kernel void @kern_lds_ptr_si(i32 addrspace(3)* %lds) #2 {
 ; HSA-LABEL: @kern_lds_ptr_si(
 ; HSA-NEXT:    [[KERN_LDS_PTR_SI_KERNARG_SEGMENT:%.*]] = call nonnull align 16 dereferenceable(8) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
-; HSA-NEXT:    [[LDS_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, i8 addrspace(4)* [[KERN_LDS_PTR_SI_KERNARG_SEGMENT]], i64 0
-; HSA-NEXT:    [[LDS_KERNARG_OFFSET_CAST:%.*]] = bitcast i8 addrspace(4)* [[LDS_KERNARG_OFFSET]] to i32 addrspace(3)* addrspace(4)*
-; HSA-NEXT:    [[LDS_LOAD:%.*]] = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(4)* [[LDS_KERNARG_OFFSET_CAST]], align 16, !invariant.load !0
-; HSA-NEXT:    store i32 0, i32 addrspace(3)* [[LDS_LOAD]], align 4
+; HSA-NEXT:    store i32 0, i32 addrspace(3)* [[LDS:%.*]], align 4
 ; HSA-NEXT:    ret void
 ;
 ; MESA-LABEL: @kern_lds_ptr_si(
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
index e7ca50248d482..85dfa08bc461d 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
index 679a56b3805f5..9beeb850b8d24 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,8 +8,8 @@
 define amdgpu_kernel void @global_agent_unordered_load(
 ; GFX6-LABEL: global_agent_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -82,8 +82,8 @@ entry:
 define amdgpu_kernel void @global_agent_monotonic_load(
 ; GFX6-LABEL: global_agent_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -156,8 +156,8 @@ entry:
 define amdgpu_kernel void @global_agent_acquire_load(
 ; GFX6-LABEL: global_agent_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -236,8 +236,8 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_load(
 ; GFX6-LABEL: global_agent_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -321,12 +321,12 @@ entry:
 define amdgpu_kernel void @global_agent_unordered_store(
 ; GFX6-LABEL: global_agent_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -382,12 +382,12 @@ entry:
 define amdgpu_kernel void @global_agent_monotonic_store(
 ; GFX6-LABEL: global_agent_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -443,12 +443,12 @@ entry:
 define amdgpu_kernel void @global_agent_release_store(
 ; GFX6-LABEL: global_agent_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -511,12 +511,12 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_store(
 ; GFX6-LABEL: global_agent_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -579,13 +579,13 @@ entry:
 define amdgpu_kernel void @global_agent_monotonic_atomicrmw(
 ; GFX6-LABEL: global_agent_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_monotonic_atomicrmw:
@@ -640,13 +640,13 @@ entry:
 define amdgpu_kernel void @global_agent_acquire_atomicrmw(
 ; GFX6-LABEL: global_agent_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -714,14 +714,14 @@ entry:
 define amdgpu_kernel void @global_agent_release_atomicrmw(
 ; GFX6-LABEL: global_agent_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_release_atomicrmw:
@@ -782,14 +782,14 @@ entry:
 define amdgpu_kernel void @global_agent_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_agent_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -863,14 +863,14 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_agent_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -944,16 +944,16 @@ entry:
 define amdgpu_kernel void @global_agent_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_agent_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_acquire_ret_atomicrmw:
@@ -1022,17 +1022,17 @@ entry:
 define amdgpu_kernel void @global_agent_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_agent_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_acq_rel_ret_atomicrmw:
@@ -1107,17 +1107,17 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_agent_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_seq_cst_ret_atomicrmw:
@@ -1192,14 +1192,14 @@ entry:
 define amdgpu_kernel void @global_agent_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_monotonic_monotonic_cmpxchg:
@@ -1261,14 +1261,14 @@ entry:
 define amdgpu_kernel void @global_agent_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1343,15 +1343,15 @@ entry:
 define amdgpu_kernel void @global_agent_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_release_monotonic_cmpxchg:
@@ -1419,15 +1419,15 @@ entry:
 define amdgpu_kernel void @global_agent_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1508,15 +1508,15 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1597,14 +1597,14 @@ entry:
 define amdgpu_kernel void @global_agent_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_agent_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1679,15 +1679,15 @@ entry:
 define amdgpu_kernel void @global_agent_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_agent_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1768,15 +1768,15 @@ entry:
 define amdgpu_kernel void @global_agent_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_agent_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1857,15 +1857,15 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_agent_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1946,15 +1946,15 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_agent_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -2035,17 +2035,17 @@ entry:
 define amdgpu_kernel void @global_agent_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_acquire_monotonic_ret_cmpxchg:
@@ -2124,18 +2124,18 @@ entry:
 define amdgpu_kernel void @global_agent_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_acq_rel_monotonic_ret_cmpxchg:
@@ -2220,18 +2220,18 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_seq_cst_monotonic_ret_cmpxchg:
@@ -2316,17 +2316,17 @@ entry:
 define amdgpu_kernel void @global_agent_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_acquire_acquire_ret_cmpxchg:
@@ -2405,18 +2405,18 @@ entry:
 define amdgpu_kernel void @global_agent_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_release_acquire_ret_cmpxchg:
@@ -2501,18 +2501,18 @@ entry:
 define amdgpu_kernel void @global_agent_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_acq_rel_acquire_ret_cmpxchg:
@@ -2597,18 +2597,18 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_seq_cst_acquire_ret_cmpxchg:
@@ -2693,18 +2693,18 @@ entry:
 define amdgpu_kernel void @global_agent_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_seq_cst_seq_cst_ret_cmpxchg:
@@ -2789,8 +2789,8 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_unordered_load(
 ; GFX6-LABEL: global_agent_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2863,8 +2863,8 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_monotonic_load(
 ; GFX6-LABEL: global_agent_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2937,8 +2937,8 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acquire_load(
 ; GFX6-LABEL: global_agent_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -3017,8 +3017,8 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_load(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -3102,12 +3102,12 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_unordered_store(
 ; GFX6-LABEL: global_agent_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3163,12 +3163,12 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_monotonic_store(
 ; GFX6-LABEL: global_agent_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3224,12 +3224,12 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_release_store(
 ; GFX6-LABEL: global_agent_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -3292,12 +3292,12 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_store(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -3360,13 +3360,13 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: global_agent_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_monotonic_atomicrmw:
@@ -3421,13 +3421,13 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: global_agent_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -3493,14 +3493,14 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_release_atomicrmw(
 ; GFX6-LABEL: global_agent_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_release_atomicrmw:
@@ -3561,14 +3561,14 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_agent_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -3640,14 +3640,14 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -3719,16 +3719,16 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_agent_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_acquire_ret_atomicrmw:
@@ -3797,17 +3797,17 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_agent_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_acq_rel_ret_atomicrmw:
@@ -3882,17 +3882,17 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_seq_cst_ret_atomicrmw:
@@ -3967,14 +3967,14 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_monotonic_monotonic_cmpxchg:
@@ -4036,14 +4036,14 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4116,15 +4116,15 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_release_monotonic_cmpxchg:
@@ -4192,15 +4192,15 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4279,15 +4279,15 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4366,14 +4366,14 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4446,15 +4446,15 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4533,15 +4533,15 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4620,15 +4620,15 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4707,15 +4707,15 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4794,17 +4794,17 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_acquire_monotonic_ret_cmpxchg:
@@ -4883,18 +4883,18 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
@@ -4979,18 +4979,18 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
@@ -5075,17 +5075,17 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_acquire_acquire_ret_cmpxchg:
@@ -5164,18 +5164,18 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_release_acquire_ret_cmpxchg:
@@ -5260,18 +5260,18 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_acq_rel_acquire_ret_cmpxchg:
@@ -5356,18 +5356,18 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_seq_cst_acquire_ret_cmpxchg:
@@ -5452,18 +5452,18 @@ entry:
 define amdgpu_kernel void @global_agent_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
index 58d803761fa77..d88b87626f084 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,8 +8,8 @@
 define amdgpu_kernel void @global_nontemporal_load_0(
 ; GFX6-LABEL: global_nontemporal_load_0:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s7, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_load_dword s0, s[0:1], 0x0
@@ -77,8 +77,8 @@ entry:
 define amdgpu_kernel void @global_nontemporal_load_1(
 ; GFX6-LABEL: global_nontemporal_load_1:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX6-NEXT:    s_mov_b32 s2, -1
@@ -157,8 +157,8 @@ entry:
 define amdgpu_kernel void @global_nontemporal_store_0(
 ; GFX6-LABEL: global_nontemporal_store_0:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s7, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_load_dword s0, s[0:1], 0x0
@@ -226,8 +226,8 @@ entry:
 define amdgpu_kernel void @global_nontemporal_store_1(
 ; GFX6-LABEL: global_nontemporal_store_1:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s7, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s6, 0
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
index dd50b95e8691f..5cb013b6c2bcd 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,8 +8,8 @@
 define amdgpu_kernel void @global_singlethread_unordered_load(
 ; GFX6-LABEL: global_singlethread_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -82,8 +82,8 @@ entry:
 define amdgpu_kernel void @global_singlethread_monotonic_load(
 ; GFX6-LABEL: global_singlethread_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -156,8 +156,8 @@ entry:
 define amdgpu_kernel void @global_singlethread_acquire_load(
 ; GFX6-LABEL: global_singlethread_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -230,8 +230,8 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_load(
 ; GFX6-LABEL: global_singlethread_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -304,12 +304,12 @@ entry:
 define amdgpu_kernel void @global_singlethread_unordered_store(
 ; GFX6-LABEL: global_singlethread_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -365,12 +365,12 @@ entry:
 define amdgpu_kernel void @global_singlethread_monotonic_store(
 ; GFX6-LABEL: global_singlethread_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -426,12 +426,12 @@ entry:
 define amdgpu_kernel void @global_singlethread_release_store(
 ; GFX6-LABEL: global_singlethread_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -487,12 +487,12 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_store(
 ; GFX6-LABEL: global_singlethread_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -548,13 +548,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_monotonic_atomicrmw(
 ; GFX6-LABEL: global_singlethread_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_monotonic_atomicrmw:
@@ -609,13 +609,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_acquire_atomicrmw(
 ; GFX6-LABEL: global_singlethread_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acquire_atomicrmw:
@@ -670,13 +670,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_release_atomicrmw(
 ; GFX6-LABEL: global_singlethread_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_release_atomicrmw:
@@ -731,13 +731,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_singlethread_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acq_rel_atomicrmw:
@@ -792,13 +792,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_singlethread_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_seq_cst_atomicrmw:
@@ -853,15 +853,15 @@ entry:
 define amdgpu_kernel void @global_singlethread_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_singlethread_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acquire_ret_atomicrmw:
@@ -925,15 +925,15 @@ entry:
 define amdgpu_kernel void @global_singlethread_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_singlethread_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acq_rel_ret_atomicrmw:
@@ -997,15 +997,15 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_singlethread_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_seq_cst_ret_atomicrmw:
@@ -1069,14 +1069,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_monotonic_monotonic_cmpxchg:
@@ -1138,14 +1138,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acquire_monotonic_cmpxchg:
@@ -1207,14 +1207,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_release_monotonic_cmpxchg:
@@ -1276,14 +1276,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acq_rel_monotonic_cmpxchg:
@@ -1345,14 +1345,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_seq_cst_monotonic_cmpxchg:
@@ -1414,14 +1414,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_singlethread_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acquire_acquire_cmpxchg:
@@ -1483,14 +1483,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_singlethread_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_release_acquire_cmpxchg:
@@ -1552,14 +1552,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_singlethread_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acq_rel_acquire_cmpxchg:
@@ -1621,14 +1621,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_singlethread_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_seq_cst_acquire_cmpxchg:
@@ -1690,14 +1690,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_singlethread_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_seq_cst_seq_cst_cmpxchg:
@@ -1759,16 +1759,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acquire_monotonic_ret_cmpxchg:
@@ -1842,16 +1842,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acq_rel_monotonic_ret_cmpxchg:
@@ -1925,16 +1925,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_seq_cst_monotonic_ret_cmpxchg:
@@ -2008,16 +2008,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acquire_acquire_ret_cmpxchg:
@@ -2091,16 +2091,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_release_acquire_ret_cmpxchg:
@@ -2174,16 +2174,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_acq_rel_acquire_ret_cmpxchg:
@@ -2257,16 +2257,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_seq_cst_acquire_ret_cmpxchg:
@@ -2340,16 +2340,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_seq_cst_seq_cst_ret_cmpxchg:
@@ -2423,8 +2423,8 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_unordered_load(
 ; GFX6-LABEL: global_singlethread_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2497,8 +2497,8 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_monotonic_load(
 ; GFX6-LABEL: global_singlethread_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2571,8 +2571,8 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acquire_load(
 ; GFX6-LABEL: global_singlethread_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2645,8 +2645,8 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_load(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2719,12 +2719,12 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_unordered_store(
 ; GFX6-LABEL: global_singlethread_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2780,12 +2780,12 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_monotonic_store(
 ; GFX6-LABEL: global_singlethread_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2841,12 +2841,12 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_release_store(
 ; GFX6-LABEL: global_singlethread_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2902,12 +2902,12 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_store(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2963,13 +2963,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: global_singlethread_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_monotonic_atomicrmw:
@@ -3024,13 +3024,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: global_singlethread_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acquire_atomicrmw:
@@ -3085,13 +3085,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_release_atomicrmw(
 ; GFX6-LABEL: global_singlethread_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_release_atomicrmw:
@@ -3146,13 +3146,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_singlethread_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acq_rel_atomicrmw:
@@ -3207,13 +3207,13 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_seq_cst_atomicrmw:
@@ -3268,15 +3268,15 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_singlethread_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acquire_ret_atomicrmw:
@@ -3340,15 +3340,15 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_singlethread_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acq_rel_ret_atomicrmw:
@@ -3412,15 +3412,15 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_seq_cst_ret_atomicrmw:
@@ -3484,14 +3484,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_monotonic_monotonic_cmpxchg:
@@ -3553,14 +3553,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acquire_monotonic_cmpxchg:
@@ -3622,14 +3622,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_release_monotonic_cmpxchg:
@@ -3691,14 +3691,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acq_rel_monotonic_cmpxchg:
@@ -3760,14 +3760,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_seq_cst_monotonic_cmpxchg:
@@ -3829,14 +3829,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acquire_acquire_cmpxchg:
@@ -3898,14 +3898,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_release_acquire_cmpxchg:
@@ -3967,14 +3967,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acq_rel_acquire_cmpxchg:
@@ -4036,14 +4036,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_seq_cst_acquire_cmpxchg:
@@ -4105,14 +4105,14 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_seq_cst_seq_cst_cmpxchg:
@@ -4174,16 +4174,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acquire_monotonic_ret_cmpxchg:
@@ -4257,16 +4257,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acq_rel_monotonic_ret_cmpxchg:
@@ -4340,16 +4340,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_seq_cst_monotonic_ret_cmpxchg:
@@ -4423,16 +4423,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acquire_acquire_ret_cmpxchg:
@@ -4506,16 +4506,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_release_acquire_ret_cmpxchg:
@@ -4589,16 +4589,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_acq_rel_acquire_ret_cmpxchg:
@@ -4672,16 +4672,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_seq_cst_acquire_ret_cmpxchg:
@@ -4755,16 +4755,16 @@ entry:
 define amdgpu_kernel void @global_singlethread_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_singlethread_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_singlethread_one_as_seq_cst_seq_cst_ret_cmpxchg:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
index e4b0b29e74375..0874452577959 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,8 +8,8 @@
 define amdgpu_kernel void @global_system_unordered_load(
 ; GFX6-LABEL: global_system_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -82,8 +82,8 @@ entry:
 define amdgpu_kernel void @global_system_monotonic_load(
 ; GFX6-LABEL: global_system_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -156,8 +156,8 @@ entry:
 define amdgpu_kernel void @global_system_acquire_load(
 ; GFX6-LABEL: global_system_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -236,8 +236,8 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_load(
 ; GFX6-LABEL: global_system_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -321,12 +321,12 @@ entry:
 define amdgpu_kernel void @global_system_unordered_store(
 ; GFX6-LABEL: global_system_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -382,12 +382,12 @@ entry:
 define amdgpu_kernel void @global_system_monotonic_store(
 ; GFX6-LABEL: global_system_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -443,12 +443,12 @@ entry:
 define amdgpu_kernel void @global_system_release_store(
 ; GFX6-LABEL: global_system_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -511,12 +511,12 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_store(
 ; GFX6-LABEL: global_system_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -579,13 +579,13 @@ entry:
 define amdgpu_kernel void @global_system_monotonic_atomicrmw(
 ; GFX6-LABEL: global_system_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_monotonic_atomicrmw:
@@ -640,13 +640,13 @@ entry:
 define amdgpu_kernel void @global_system_acquire_atomicrmw(
 ; GFX6-LABEL: global_system_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -714,14 +714,14 @@ entry:
 define amdgpu_kernel void @global_system_release_atomicrmw(
 ; GFX6-LABEL: global_system_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_release_atomicrmw:
@@ -782,14 +782,14 @@ entry:
 define amdgpu_kernel void @global_system_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_system_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -863,14 +863,14 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_system_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -944,16 +944,16 @@ entry:
 define amdgpu_kernel void @global_system_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_system_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_acquire_ret_atomicrmw:
@@ -1022,17 +1022,17 @@ entry:
 define amdgpu_kernel void @global_system_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_system_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_acq_rel_ret_atomicrmw:
@@ -1107,17 +1107,17 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_system_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_seq_cst_ret_atomicrmw:
@@ -1192,14 +1192,14 @@ entry:
 define amdgpu_kernel void @global_system_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_monotonic_monotonic_cmpxchg:
@@ -1261,14 +1261,14 @@ entry:
 define amdgpu_kernel void @global_system_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1343,15 +1343,15 @@ entry:
 define amdgpu_kernel void @global_system_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_release_monotonic_cmpxchg:
@@ -1419,15 +1419,15 @@ entry:
 define amdgpu_kernel void @global_system_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1508,15 +1508,15 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1597,14 +1597,14 @@ entry:
 define amdgpu_kernel void @global_system_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_system_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1679,15 +1679,15 @@ entry:
 define amdgpu_kernel void @global_system_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_system_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1768,15 +1768,15 @@ entry:
 define amdgpu_kernel void @global_system_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_system_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1857,15 +1857,15 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_system_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -1946,15 +1946,15 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_system_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -2035,17 +2035,17 @@ entry:
 define amdgpu_kernel void @global_system_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_system_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_acquire_monotonic_ret_cmpxchg:
@@ -2124,18 +2124,18 @@ entry:
 define amdgpu_kernel void @global_system_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_system_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_acq_rel_monotonic_ret_cmpxchg:
@@ -2220,18 +2220,18 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_system_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_seq_cst_monotonic_ret_cmpxchg:
@@ -2316,17 +2316,17 @@ entry:
 define amdgpu_kernel void @global_system_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_system_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_acquire_acquire_ret_cmpxchg:
@@ -2405,18 +2405,18 @@ entry:
 define amdgpu_kernel void @global_system_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_system_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_release_acquire_ret_cmpxchg:
@@ -2501,18 +2501,18 @@ entry:
 define amdgpu_kernel void @global_system_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_system_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_acq_rel_acquire_ret_cmpxchg:
@@ -2597,18 +2597,18 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_system_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_seq_cst_acquire_ret_cmpxchg:
@@ -2693,18 +2693,18 @@ entry:
 define amdgpu_kernel void @global_system_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_system_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_seq_cst_seq_cst_ret_cmpxchg:
@@ -2789,8 +2789,8 @@ entry:
 define amdgpu_kernel void @global_system_one_as_unordered_load(
 ; GFX6-LABEL: global_system_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2863,8 +2863,8 @@ entry:
 define amdgpu_kernel void @global_system_one_as_monotonic_load(
 ; GFX6-LABEL: global_system_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2937,8 +2937,8 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acquire_load(
 ; GFX6-LABEL: global_system_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -3017,8 +3017,8 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_load(
 ; GFX6-LABEL: global_system_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -3102,12 +3102,12 @@ entry:
 define amdgpu_kernel void @global_system_one_as_unordered_store(
 ; GFX6-LABEL: global_system_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3163,12 +3163,12 @@ entry:
 define amdgpu_kernel void @global_system_one_as_monotonic_store(
 ; GFX6-LABEL: global_system_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3224,12 +3224,12 @@ entry:
 define amdgpu_kernel void @global_system_one_as_release_store(
 ; GFX6-LABEL: global_system_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -3292,12 +3292,12 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_store(
 ; GFX6-LABEL: global_system_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -3360,13 +3360,13 @@ entry:
 define amdgpu_kernel void @global_system_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: global_system_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_monotonic_atomicrmw:
@@ -3421,13 +3421,13 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: global_system_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -3493,14 +3493,14 @@ entry:
 define amdgpu_kernel void @global_system_one_as_release_atomicrmw(
 ; GFX6-LABEL: global_system_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_release_atomicrmw:
@@ -3561,14 +3561,14 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_system_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -3640,14 +3640,14 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_system_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -3719,16 +3719,16 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_system_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_acquire_ret_atomicrmw:
@@ -3797,17 +3797,17 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_system_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_acq_rel_ret_atomicrmw:
@@ -3882,17 +3882,17 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_system_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_seq_cst_ret_atomicrmw:
@@ -3967,14 +3967,14 @@ entry:
 define amdgpu_kernel void @global_system_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_monotonic_monotonic_cmpxchg:
@@ -4036,14 +4036,14 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4116,15 +4116,15 @@ entry:
 define amdgpu_kernel void @global_system_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_release_monotonic_cmpxchg:
@@ -4192,15 +4192,15 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4279,15 +4279,15 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4366,14 +4366,14 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4446,15 +4446,15 @@ entry:
 define amdgpu_kernel void @global_system_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4533,15 +4533,15 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4620,15 +4620,15 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4707,15 +4707,15 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
 ; GFX6-NEXT:    s_endpgm
@@ -4794,17 +4794,17 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_acquire_monotonic_ret_cmpxchg:
@@ -4883,18 +4883,18 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_acq_rel_monotonic_ret_cmpxchg:
@@ -4979,18 +4979,18 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_seq_cst_monotonic_ret_cmpxchg:
@@ -5075,17 +5075,17 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_acquire_acquire_ret_cmpxchg:
@@ -5164,18 +5164,18 @@ entry:
 define amdgpu_kernel void @global_system_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_release_acquire_ret_cmpxchg:
@@ -5260,18 +5260,18 @@ entry:
 define amdgpu_kernel void @global_system_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_acq_rel_acquire_ret_cmpxchg:
@@ -5356,18 +5356,18 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_seq_cst_acquire_ret_cmpxchg:
@@ -5452,18 +5452,18 @@ entry:
 define amdgpu_kernel void @global_system_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_system_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_system_one_as_seq_cst_seq_cst_ret_cmpxchg:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
index 9aab2f3b6123f..cb32f3a3e310a 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,8 +8,8 @@
 define amdgpu_kernel void @global_wavefront_unordered_load(
 ; GFX6-LABEL: global_wavefront_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -82,8 +82,8 @@ entry:
 define amdgpu_kernel void @global_wavefront_monotonic_load(
 ; GFX6-LABEL: global_wavefront_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -156,8 +156,8 @@ entry:
 define amdgpu_kernel void @global_wavefront_acquire_load(
 ; GFX6-LABEL: global_wavefront_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -230,8 +230,8 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_load(
 ; GFX6-LABEL: global_wavefront_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -304,12 +304,12 @@ entry:
 define amdgpu_kernel void @global_wavefront_unordered_store(
 ; GFX6-LABEL: global_wavefront_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -365,12 +365,12 @@ entry:
 define amdgpu_kernel void @global_wavefront_monotonic_store(
 ; GFX6-LABEL: global_wavefront_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -426,12 +426,12 @@ entry:
 define amdgpu_kernel void @global_wavefront_release_store(
 ; GFX6-LABEL: global_wavefront_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -487,12 +487,12 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_store(
 ; GFX6-LABEL: global_wavefront_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -548,13 +548,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_monotonic_atomicrmw(
 ; GFX6-LABEL: global_wavefront_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_monotonic_atomicrmw:
@@ -609,13 +609,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_acquire_atomicrmw(
 ; GFX6-LABEL: global_wavefront_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acquire_atomicrmw:
@@ -670,13 +670,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_release_atomicrmw(
 ; GFX6-LABEL: global_wavefront_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_release_atomicrmw:
@@ -731,13 +731,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_wavefront_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acq_rel_atomicrmw:
@@ -792,13 +792,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_wavefront_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_seq_cst_atomicrmw:
@@ -853,15 +853,15 @@ entry:
 define amdgpu_kernel void @global_wavefront_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_wavefront_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acquire_ret_atomicrmw:
@@ -925,15 +925,15 @@ entry:
 define amdgpu_kernel void @global_wavefront_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_wavefront_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acq_rel_ret_atomicrmw:
@@ -997,15 +997,15 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_wavefront_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_seq_cst_ret_atomicrmw:
@@ -1069,14 +1069,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_monotonic_monotonic_cmpxchg:
@@ -1138,14 +1138,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acquire_monotonic_cmpxchg:
@@ -1207,14 +1207,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_release_monotonic_cmpxchg:
@@ -1276,14 +1276,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acq_rel_monotonic_cmpxchg:
@@ -1345,14 +1345,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_seq_cst_monotonic_cmpxchg:
@@ -1414,14 +1414,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_wavefront_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acquire_acquire_cmpxchg:
@@ -1483,14 +1483,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_wavefront_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_release_acquire_cmpxchg:
@@ -1552,14 +1552,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_wavefront_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acq_rel_acquire_cmpxchg:
@@ -1621,14 +1621,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_wavefront_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_seq_cst_acquire_cmpxchg:
@@ -1690,14 +1690,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_wavefront_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_seq_cst_seq_cst_cmpxchg:
@@ -1759,16 +1759,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acquire_monotonic_ret_cmpxchg:
@@ -1842,16 +1842,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acq_rel_monotonic_ret_cmpxchg:
@@ -1925,16 +1925,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_seq_cst_monotonic_ret_cmpxchg:
@@ -2008,16 +2008,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acquire_acquire_ret_cmpxchg:
@@ -2091,16 +2091,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_release_acquire_ret_cmpxchg:
@@ -2174,16 +2174,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_acq_rel_acquire_ret_cmpxchg:
@@ -2257,16 +2257,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_seq_cst_acquire_ret_cmpxchg:
@@ -2340,16 +2340,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_seq_cst_seq_cst_ret_cmpxchg:
@@ -2423,8 +2423,8 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_unordered_load(
 ; GFX6-LABEL: global_wavefront_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2497,8 +2497,8 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_monotonic_load(
 ; GFX6-LABEL: global_wavefront_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2571,8 +2571,8 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acquire_load(
 ; GFX6-LABEL: global_wavefront_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2645,8 +2645,8 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_load(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2719,12 +2719,12 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_unordered_store(
 ; GFX6-LABEL: global_wavefront_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2780,12 +2780,12 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_monotonic_store(
 ; GFX6-LABEL: global_wavefront_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2841,12 +2841,12 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_release_store(
 ; GFX6-LABEL: global_wavefront_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2902,12 +2902,12 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_store(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2963,13 +2963,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: global_wavefront_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_monotonic_atomicrmw:
@@ -3024,13 +3024,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: global_wavefront_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acquire_atomicrmw:
@@ -3085,13 +3085,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_release_atomicrmw(
 ; GFX6-LABEL: global_wavefront_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_release_atomicrmw:
@@ -3146,13 +3146,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_wavefront_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acq_rel_atomicrmw:
@@ -3207,13 +3207,13 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_seq_cst_atomicrmw:
@@ -3268,15 +3268,15 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_wavefront_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acquire_ret_atomicrmw:
@@ -3340,15 +3340,15 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_wavefront_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acq_rel_ret_atomicrmw:
@@ -3412,15 +3412,15 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_seq_cst_ret_atomicrmw:
@@ -3484,14 +3484,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_monotonic_monotonic_cmpxchg:
@@ -3553,14 +3553,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acquire_monotonic_cmpxchg:
@@ -3622,14 +3622,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_release_monotonic_cmpxchg:
@@ -3691,14 +3691,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acq_rel_monotonic_cmpxchg:
@@ -3760,14 +3760,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_seq_cst_monotonic_cmpxchg:
@@ -3829,14 +3829,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acquire_acquire_cmpxchg:
@@ -3898,14 +3898,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_release_acquire_cmpxchg:
@@ -3967,14 +3967,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acq_rel_acquire_cmpxchg:
@@ -4036,14 +4036,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_seq_cst_acquire_cmpxchg:
@@ -4105,14 +4105,14 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_seq_cst_seq_cst_cmpxchg:
@@ -4174,16 +4174,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acquire_monotonic_ret_cmpxchg:
@@ -4257,16 +4257,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acq_rel_monotonic_ret_cmpxchg:
@@ -4340,16 +4340,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_seq_cst_monotonic_ret_cmpxchg:
@@ -4423,16 +4423,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acquire_acquire_ret_cmpxchg:
@@ -4506,16 +4506,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_release_acquire_ret_cmpxchg:
@@ -4589,16 +4589,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_acq_rel_acquire_ret_cmpxchg:
@@ -4672,16 +4672,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_seq_cst_acquire_ret_cmpxchg:
@@ -4755,16 +4755,16 @@ entry:
 define amdgpu_kernel void @global_wavefront_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_wavefront_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_wavefront_one_as_seq_cst_seq_cst_ret_cmpxchg:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
index 1fd85e6acb9fb..a1ec279d1c247 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,8 +8,8 @@
 define amdgpu_kernel void @global_workgroup_unordered_load(
 ; GFX6-LABEL: global_workgroup_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -82,8 +82,8 @@ entry:
 define amdgpu_kernel void @global_workgroup_monotonic_load(
 ; GFX6-LABEL: global_workgroup_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -156,8 +156,8 @@ entry:
 define amdgpu_kernel void @global_workgroup_acquire_load(
 ; GFX6-LABEL: global_workgroup_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -231,8 +231,8 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_load(
 ; GFX6-LABEL: global_workgroup_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -310,12 +310,12 @@ entry:
 define amdgpu_kernel void @global_workgroup_unordered_store(
 ; GFX6-LABEL: global_workgroup_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -371,12 +371,12 @@ entry:
 define amdgpu_kernel void @global_workgroup_monotonic_store(
 ; GFX6-LABEL: global_workgroup_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -432,12 +432,12 @@ entry:
 define amdgpu_kernel void @global_workgroup_release_store(
 ; GFX6-LABEL: global_workgroup_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -499,12 +499,12 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_store(
 ; GFX6-LABEL: global_workgroup_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
@@ -566,13 +566,13 @@ entry:
 define amdgpu_kernel void @global_workgroup_monotonic_atomicrmw(
 ; GFX6-LABEL: global_workgroup_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_monotonic_atomicrmw:
@@ -627,13 +627,13 @@ entry:
 define amdgpu_kernel void @global_workgroup_acquire_atomicrmw(
 ; GFX6-LABEL: global_workgroup_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -695,14 +695,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_release_atomicrmw(
 ; GFX6-LABEL: global_workgroup_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_release_atomicrmw:
@@ -762,14 +762,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_workgroup_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -836,14 +836,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_workgroup_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -910,15 +910,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_workgroup_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_acquire_ret_atomicrmw:
@@ -983,16 +983,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_workgroup_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_acq_rel_ret_atomicrmw:
@@ -1062,16 +1062,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_workgroup_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_seq_cst_ret_atomicrmw:
@@ -1141,14 +1141,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_monotonic_monotonic_cmpxchg:
@@ -1210,14 +1210,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -1286,15 +1286,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_release_monotonic_cmpxchg:
@@ -1361,15 +1361,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -1443,15 +1443,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -1525,14 +1525,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_workgroup_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -1601,15 +1601,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_workgroup_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -1683,15 +1683,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_workgroup_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -1765,15 +1765,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_workgroup_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -1847,15 +1847,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_workgroup_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -1929,16 +1929,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_acquire_monotonic_ret_cmpxchg:
@@ -2014,17 +2014,17 @@ entry:
 define amdgpu_kernel void @global_workgroup_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_acq_rel_monotonic_ret_cmpxchg:
@@ -2105,17 +2105,17 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_seq_cst_monotonic_ret_cmpxchg:
@@ -2196,16 +2196,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_acquire_acquire_ret_cmpxchg:
@@ -2281,17 +2281,17 @@ entry:
 define amdgpu_kernel void @global_workgroup_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_release_acquire_ret_cmpxchg:
@@ -2372,17 +2372,17 @@ entry:
 define amdgpu_kernel void @global_workgroup_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_acq_rel_acquire_ret_cmpxchg:
@@ -2463,17 +2463,17 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_seq_cst_acquire_ret_cmpxchg:
@@ -2554,17 +2554,17 @@ entry:
 define amdgpu_kernel void @global_workgroup_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_seq_cst_seq_cst_ret_cmpxchg:
@@ -2645,8 +2645,8 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_unordered_load(
 ; GFX6-LABEL: global_workgroup_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2719,8 +2719,8 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_monotonic_load(
 ; GFX6-LABEL: global_workgroup_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2793,8 +2793,8 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acquire_load(
 ; GFX6-LABEL: global_workgroup_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2868,8 +2868,8 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_load(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_mov_b32 s0, s4
@@ -2944,12 +2944,12 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_unordered_store(
 ; GFX6-LABEL: global_workgroup_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3005,12 +3005,12 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_monotonic_store(
 ; GFX6-LABEL: global_workgroup_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3066,12 +3066,12 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_release_store(
 ; GFX6-LABEL: global_workgroup_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3129,12 +3129,12 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_store(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3192,13 +3192,13 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: global_workgroup_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_monotonic_atomicrmw:
@@ -3253,13 +3253,13 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: global_workgroup_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acquire_atomicrmw:
@@ -3316,13 +3316,13 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_release_atomicrmw(
 ; GFX6-LABEL: global_workgroup_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_release_atomicrmw:
@@ -3379,13 +3379,13 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: global_workgroup_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acq_rel_atomicrmw:
@@ -3444,13 +3444,13 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_seq_cst_atomicrmw:
@@ -3509,15 +3509,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: global_workgroup_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acquire_ret_atomicrmw:
@@ -3582,15 +3582,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: global_workgroup_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acq_rel_ret_atomicrmw:
@@ -3657,15 +3657,15 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s4, s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    buffer_atomic_swap v0, off, s[4:7], 0 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    buffer_atomic_swap v0, off, s[0:3], 0 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_seq_cst_ret_atomicrmw:
@@ -3732,14 +3732,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_monotonic_monotonic_cmpxchg:
@@ -3801,14 +3801,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acquire_monotonic_cmpxchg:
@@ -3872,14 +3872,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_release_monotonic_cmpxchg:
@@ -3943,14 +3943,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acq_rel_monotonic_cmpxchg:
@@ -4016,14 +4016,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_seq_cst_monotonic_cmpxchg:
@@ -4089,14 +4089,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acquire_acquire_cmpxchg:
@@ -4160,14 +4160,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_release_acquire_cmpxchg:
@@ -4233,14 +4233,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acq_rel_acquire_cmpxchg:
@@ -4306,14 +4306,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_seq_cst_acquire_cmpxchg:
@@ -4379,14 +4379,14 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_seq_cst_seq_cst_cmpxchg:
@@ -4452,16 +4452,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acquire_monotonic_ret_cmpxchg:
@@ -4536,16 +4536,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg:
@@ -4622,16 +4622,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg:
@@ -4708,16 +4708,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acquire_acquire_ret_cmpxchg:
@@ -4792,16 +4792,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_release_acquire_ret_cmpxchg:
@@ -4878,16 +4878,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_acq_rel_acquire_ret_cmpxchg:
@@ -4964,16 +4964,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_seq_cst_acquire_ret_cmpxchg:
@@ -5050,16 +5050,16 @@ entry:
 define amdgpu_kernel void @global_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: global_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[4:5], 0x2
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[4:7], 0 offset:16 glc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v1, s5
+; GFX6-NEXT:    buffer_atomic_cmpswap v[0:1], off, s[0:3], 0 offset:16 glc
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: global_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg:
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
index 49499b7570e99..afb020f5314c1 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,13 +8,13 @@
 define amdgpu_kernel void @local_agent_unordered_load(
 ; GFX6-LABEL: local_agent_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -74,13 +74,13 @@ entry:
 define amdgpu_kernel void @local_agent_monotonic_load(
 ; GFX6-LABEL: local_agent_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -140,15 +140,15 @@ entry:
 define amdgpu_kernel void @local_agent_acquire_load(
 ; GFX6-LABEL: local_agent_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -212,16 +212,16 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_load(
 ; GFX6-LABEL: local_agent_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_read_b32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -291,12 +291,12 @@ entry:
 define amdgpu_kernel void @local_agent_unordered_store(
 ; GFX6-LABEL: local_agent_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -346,12 +346,12 @@ entry:
 define amdgpu_kernel void @local_agent_monotonic_store(
 ; GFX6-LABEL: local_agent_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -401,12 +401,12 @@ entry:
 define amdgpu_kernel void @local_agent_release_store(
 ; GFX6-LABEL: local_agent_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
@@ -463,12 +463,12 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_store(
 ; GFX6-LABEL: local_agent_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
@@ -525,12 +525,12 @@ entry:
 define amdgpu_kernel void @local_agent_monotonic_atomicrmw(
 ; GFX6-LABEL: local_agent_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -580,12 +580,12 @@ entry:
 define amdgpu_kernel void @local_agent_acquire_atomicrmw(
 ; GFX6-LABEL: local_agent_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
@@ -648,12 +648,12 @@ entry:
 define amdgpu_kernel void @local_agent_release_atomicrmw(
 ; GFX6-LABEL: local_agent_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
@@ -710,12 +710,12 @@ entry:
 define amdgpu_kernel void @local_agent_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_agent_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -785,12 +785,12 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_agent_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -860,12 +860,12 @@ entry:
 define amdgpu_kernel void @local_agent_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_agent_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
@@ -934,12 +934,12 @@ entry:
 define amdgpu_kernel void @local_agent_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_agent_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1015,12 +1015,12 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_agent_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1096,8 +1096,8 @@ entry:
 define amdgpu_kernel void @local_agent_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1158,8 +1158,8 @@ entry:
 define amdgpu_kernel void @local_agent_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1233,8 +1233,8 @@ entry:
 define amdgpu_kernel void @local_agent_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1302,8 +1302,8 @@ entry:
 define amdgpu_kernel void @local_agent_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1384,8 +1384,8 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1466,8 +1466,8 @@ entry:
 define amdgpu_kernel void @local_agent_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_agent_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1541,8 +1541,8 @@ entry:
 define amdgpu_kernel void @local_agent_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_agent_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1623,8 +1623,8 @@ entry:
 define amdgpu_kernel void @local_agent_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_agent_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1705,8 +1705,8 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_agent_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1787,8 +1787,8 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_agent_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1869,8 +1869,8 @@ entry:
 define amdgpu_kernel void @local_agent_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1949,8 +1949,8 @@ entry:
 define amdgpu_kernel void @local_agent_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2036,8 +2036,8 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2123,8 +2123,8 @@ entry:
 define amdgpu_kernel void @local_agent_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2203,8 +2203,8 @@ entry:
 define amdgpu_kernel void @local_agent_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2290,8 +2290,8 @@ entry:
 define amdgpu_kernel void @local_agent_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2377,8 +2377,8 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2464,8 +2464,8 @@ entry:
 define amdgpu_kernel void @local_agent_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2551,13 +2551,13 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_unordered_load(
 ; GFX6-LABEL: local_agent_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2617,13 +2617,13 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_monotonic_load(
 ; GFX6-LABEL: local_agent_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2683,13 +2683,13 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acquire_load(
 ; GFX6-LABEL: local_agent_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2749,13 +2749,13 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_load(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2815,12 +2815,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_unordered_store(
 ; GFX6-LABEL: local_agent_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2870,12 +2870,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_monotonic_store(
 ; GFX6-LABEL: local_agent_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2925,12 +2925,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_release_store(
 ; GFX6-LABEL: local_agent_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2980,12 +2980,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_store(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3035,12 +3035,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: local_agent_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3090,12 +3090,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: local_agent_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3145,12 +3145,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_release_atomicrmw(
 ; GFX6-LABEL: local_agent_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3200,12 +3200,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_agent_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3255,12 +3255,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3310,12 +3310,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_agent_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3376,12 +3376,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_agent_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3442,12 +3442,12 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3508,8 +3508,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3570,8 +3570,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3632,8 +3632,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3694,8 +3694,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3756,8 +3756,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3818,8 +3818,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3880,8 +3880,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3942,8 +3942,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4004,8 +4004,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4066,8 +4066,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4128,8 +4128,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4202,8 +4202,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4276,8 +4276,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4350,8 +4350,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4424,8 +4424,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4498,8 +4498,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4572,8 +4572,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4646,8 +4646,8 @@ entry:
 define amdgpu_kernel void @local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_agent_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
index db3b8b2a5f22a..9885036a78c80 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,13 +8,13 @@
 define amdgpu_kernel void @local_nontemporal_load_0(
 ; GFX6-LABEL: local_nontemporal_load_0:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
 ; GFX6-NEXT:    s_mov_b32 m0, -1
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    ds_read_b32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
@@ -83,13 +83,13 @@ entry:
 define amdgpu_kernel void @local_nontemporal_load_1(
 ; GFX6-LABEL: local_nontemporal_load_1:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX6-NEXT:    s_mov_b32 m0, -1
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s6, v0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
@@ -163,14 +163,14 @@ entry:
 define amdgpu_kernel void @local_nontemporal_store_0(
 ; GFX6-LABEL: local_nontemporal_store_0:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x2
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_load_dword s1, s[2:3], 0x0
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    s_load_dword s0, s[0:1], 0x0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -235,15 +235,15 @@ entry:
 define amdgpu_kernel void @local_nontemporal_store_1(
 ; GFX6-LABEL: local_nontemporal_store_1:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x2
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_load_dword s1, s[2:3], 0x0
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    s_load_dword s0, s[0:1], 0x0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s2, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
index cb45b58da5ac8..4e521c3dce8b3 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,13 +8,13 @@
 define amdgpu_kernel void @local_singlethread_unordered_load(
 ; GFX6-LABEL: local_singlethread_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -74,13 +74,13 @@ entry:
 define amdgpu_kernel void @local_singlethread_monotonic_load(
 ; GFX6-LABEL: local_singlethread_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -140,13 +140,13 @@ entry:
 define amdgpu_kernel void @local_singlethread_acquire_load(
 ; GFX6-LABEL: local_singlethread_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -206,13 +206,13 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_load(
 ; GFX6-LABEL: local_singlethread_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -272,12 +272,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_unordered_store(
 ; GFX6-LABEL: local_singlethread_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -327,12 +327,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_monotonic_store(
 ; GFX6-LABEL: local_singlethread_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -382,12 +382,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_release_store(
 ; GFX6-LABEL: local_singlethread_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -437,12 +437,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_store(
 ; GFX6-LABEL: local_singlethread_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -492,12 +492,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_monotonic_atomicrmw(
 ; GFX6-LABEL: local_singlethread_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -547,12 +547,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_acquire_atomicrmw(
 ; GFX6-LABEL: local_singlethread_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -602,12 +602,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_release_atomicrmw(
 ; GFX6-LABEL: local_singlethread_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -657,12 +657,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_singlethread_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -712,12 +712,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_singlethread_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -767,12 +767,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_singlethread_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -833,12 +833,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_singlethread_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -899,12 +899,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_singlethread_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -965,8 +965,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1027,8 +1027,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1089,8 +1089,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1151,8 +1151,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1213,8 +1213,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1275,8 +1275,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_singlethread_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1337,8 +1337,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_singlethread_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1399,8 +1399,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_singlethread_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1461,8 +1461,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_singlethread_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1523,8 +1523,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_singlethread_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1585,8 +1585,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1659,8 +1659,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1733,8 +1733,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1807,8 +1807,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1881,8 +1881,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1955,8 +1955,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2029,8 +2029,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2103,8 +2103,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2177,13 +2177,13 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_unordered_load(
 ; GFX6-LABEL: local_singlethread_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2243,13 +2243,13 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_monotonic_load(
 ; GFX6-LABEL: local_singlethread_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2309,13 +2309,13 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acquire_load(
 ; GFX6-LABEL: local_singlethread_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2375,13 +2375,13 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_load(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2441,12 +2441,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_unordered_store(
 ; GFX6-LABEL: local_singlethread_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2496,12 +2496,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_monotonic_store(
 ; GFX6-LABEL: local_singlethread_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2551,12 +2551,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_release_store(
 ; GFX6-LABEL: local_singlethread_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2606,12 +2606,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_store(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2661,12 +2661,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: local_singlethread_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2716,12 +2716,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: local_singlethread_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2771,12 +2771,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_release_atomicrmw(
 ; GFX6-LABEL: local_singlethread_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2826,12 +2826,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_singlethread_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2881,12 +2881,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2936,12 +2936,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_singlethread_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3002,12 +3002,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_singlethread_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3068,12 +3068,12 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3134,8 +3134,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3196,8 +3196,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3258,8 +3258,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3320,8 +3320,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3382,8 +3382,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3444,8 +3444,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3506,8 +3506,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3568,8 +3568,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3630,8 +3630,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3692,8 +3692,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3754,8 +3754,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3828,8 +3828,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3902,8 +3902,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3976,8 +3976,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4050,8 +4050,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4124,8 +4124,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4198,8 +4198,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4272,8 +4272,8 @@ entry:
 define amdgpu_kernel void @local_singlethread_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_singlethread_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
index 7e500d4415e6b..4ef62030ef5c7 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,13 +8,13 @@
 define amdgpu_kernel void @local_system_unordered_load(
 ; GFX6-LABEL: local_system_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -74,13 +74,13 @@ entry:
 define amdgpu_kernel void @local_system_monotonic_load(
 ; GFX6-LABEL: local_system_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -140,15 +140,15 @@ entry:
 define amdgpu_kernel void @local_system_acquire_load(
 ; GFX6-LABEL: local_system_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -212,16 +212,16 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_load(
 ; GFX6-LABEL: local_system_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_read_b32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -291,12 +291,12 @@ entry:
 define amdgpu_kernel void @local_system_unordered_store(
 ; GFX6-LABEL: local_system_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -346,12 +346,12 @@ entry:
 define amdgpu_kernel void @local_system_monotonic_store(
 ; GFX6-LABEL: local_system_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -401,12 +401,12 @@ entry:
 define amdgpu_kernel void @local_system_release_store(
 ; GFX6-LABEL: local_system_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
@@ -463,12 +463,12 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_store(
 ; GFX6-LABEL: local_system_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
@@ -525,12 +525,12 @@ entry:
 define amdgpu_kernel void @local_system_monotonic_atomicrmw(
 ; GFX6-LABEL: local_system_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -580,12 +580,12 @@ entry:
 define amdgpu_kernel void @local_system_acquire_atomicrmw(
 ; GFX6-LABEL: local_system_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
@@ -648,12 +648,12 @@ entry:
 define amdgpu_kernel void @local_system_release_atomicrmw(
 ; GFX6-LABEL: local_system_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
@@ -710,12 +710,12 @@ entry:
 define amdgpu_kernel void @local_system_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_system_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -785,12 +785,12 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_system_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -860,12 +860,12 @@ entry:
 define amdgpu_kernel void @local_system_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_system_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    buffer_wbinvl1
@@ -934,12 +934,12 @@ entry:
 define amdgpu_kernel void @local_system_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_system_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1015,12 +1015,12 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_system_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
@@ -1096,8 +1096,8 @@ entry:
 define amdgpu_kernel void @local_system_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1158,8 +1158,8 @@ entry:
 define amdgpu_kernel void @local_system_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1233,8 +1233,8 @@ entry:
 define amdgpu_kernel void @local_system_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1302,8 +1302,8 @@ entry:
 define amdgpu_kernel void @local_system_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1384,8 +1384,8 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1466,8 +1466,8 @@ entry:
 define amdgpu_kernel void @local_system_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_system_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1541,8 +1541,8 @@ entry:
 define amdgpu_kernel void @local_system_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_system_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1623,8 +1623,8 @@ entry:
 define amdgpu_kernel void @local_system_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_system_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1705,8 +1705,8 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_system_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1787,8 +1787,8 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_system_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1869,8 +1869,8 @@ entry:
 define amdgpu_kernel void @local_system_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_system_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1949,8 +1949,8 @@ entry:
 define amdgpu_kernel void @local_system_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_system_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2036,8 +2036,8 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_system_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2123,8 +2123,8 @@ entry:
 define amdgpu_kernel void @local_system_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_system_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2203,8 +2203,8 @@ entry:
 define amdgpu_kernel void @local_system_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_system_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2290,8 +2290,8 @@ entry:
 define amdgpu_kernel void @local_system_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_system_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2377,8 +2377,8 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_system_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2464,8 +2464,8 @@ entry:
 define amdgpu_kernel void @local_system_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_system_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2551,13 +2551,13 @@ entry:
 define amdgpu_kernel void @local_system_one_as_unordered_load(
 ; GFX6-LABEL: local_system_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2617,13 +2617,13 @@ entry:
 define amdgpu_kernel void @local_system_one_as_monotonic_load(
 ; GFX6-LABEL: local_system_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2683,13 +2683,13 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acquire_load(
 ; GFX6-LABEL: local_system_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2749,13 +2749,13 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_load(
 ; GFX6-LABEL: local_system_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2815,12 +2815,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_unordered_store(
 ; GFX6-LABEL: local_system_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2870,12 +2870,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_monotonic_store(
 ; GFX6-LABEL: local_system_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2925,12 +2925,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_release_store(
 ; GFX6-LABEL: local_system_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2980,12 +2980,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_store(
 ; GFX6-LABEL: local_system_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3035,12 +3035,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: local_system_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3090,12 +3090,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: local_system_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3145,12 +3145,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_release_atomicrmw(
 ; GFX6-LABEL: local_system_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3200,12 +3200,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_system_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3255,12 +3255,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_system_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3310,12 +3310,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_system_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3376,12 +3376,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_system_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3442,12 +3442,12 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_system_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3508,8 +3508,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3570,8 +3570,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3632,8 +3632,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3694,8 +3694,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3756,8 +3756,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3818,8 +3818,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3880,8 +3880,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3942,8 +3942,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4004,8 +4004,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4066,8 +4066,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4128,8 +4128,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4202,8 +4202,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4276,8 +4276,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4350,8 +4350,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4424,8 +4424,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4498,8 +4498,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4572,8 +4572,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4646,8 +4646,8 @@ entry:
 define amdgpu_kernel void @local_system_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_system_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
index 1bc5c14992e4c..cb5265b8f0858 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,13 +8,13 @@
 define amdgpu_kernel void @local_wavefront_unordered_load(
 ; GFX6-LABEL: local_wavefront_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -74,13 +74,13 @@ entry:
 define amdgpu_kernel void @local_wavefront_monotonic_load(
 ; GFX6-LABEL: local_wavefront_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -140,13 +140,13 @@ entry:
 define amdgpu_kernel void @local_wavefront_acquire_load(
 ; GFX6-LABEL: local_wavefront_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -206,13 +206,13 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_load(
 ; GFX6-LABEL: local_wavefront_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -272,12 +272,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_unordered_store(
 ; GFX6-LABEL: local_wavefront_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -327,12 +327,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_monotonic_store(
 ; GFX6-LABEL: local_wavefront_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -382,12 +382,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_release_store(
 ; GFX6-LABEL: local_wavefront_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -437,12 +437,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_store(
 ; GFX6-LABEL: local_wavefront_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -492,12 +492,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_monotonic_atomicrmw(
 ; GFX6-LABEL: local_wavefront_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -547,12 +547,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_acquire_atomicrmw(
 ; GFX6-LABEL: local_wavefront_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -602,12 +602,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_release_atomicrmw(
 ; GFX6-LABEL: local_wavefront_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -657,12 +657,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_wavefront_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -712,12 +712,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_wavefront_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -767,12 +767,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_wavefront_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -833,12 +833,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_wavefront_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -899,12 +899,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_wavefront_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -965,8 +965,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1027,8 +1027,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1089,8 +1089,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1151,8 +1151,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1213,8 +1213,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1275,8 +1275,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_wavefront_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1337,8 +1337,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_wavefront_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1399,8 +1399,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_wavefront_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1461,8 +1461,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_wavefront_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1523,8 +1523,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_wavefront_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1585,8 +1585,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1659,8 +1659,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1733,8 +1733,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1807,8 +1807,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1881,8 +1881,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1955,8 +1955,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2029,8 +2029,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2103,8 +2103,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2177,13 +2177,13 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_unordered_load(
 ; GFX6-LABEL: local_wavefront_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2243,13 +2243,13 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_monotonic_load(
 ; GFX6-LABEL: local_wavefront_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2309,13 +2309,13 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acquire_load(
 ; GFX6-LABEL: local_wavefront_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2375,13 +2375,13 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_load(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2441,12 +2441,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_unordered_store(
 ; GFX6-LABEL: local_wavefront_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2496,12 +2496,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_monotonic_store(
 ; GFX6-LABEL: local_wavefront_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2551,12 +2551,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_release_store(
 ; GFX6-LABEL: local_wavefront_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2606,12 +2606,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_store(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2661,12 +2661,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: local_wavefront_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2716,12 +2716,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: local_wavefront_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2771,12 +2771,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_release_atomicrmw(
 ; GFX6-LABEL: local_wavefront_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2826,12 +2826,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_wavefront_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2881,12 +2881,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2936,12 +2936,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_wavefront_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3002,12 +3002,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_wavefront_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3068,12 +3068,12 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3134,8 +3134,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3196,8 +3196,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3258,8 +3258,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3320,8 +3320,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3382,8 +3382,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3444,8 +3444,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3506,8 +3506,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3568,8 +3568,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3630,8 +3630,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3692,8 +3692,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3754,8 +3754,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3828,8 +3828,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3902,8 +3902,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3976,8 +3976,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4050,8 +4050,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4124,8 +4124,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4198,8 +4198,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4272,8 +4272,8 @@ entry:
 define amdgpu_kernel void @local_wavefront_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_wavefront_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
index 1823f3ad88822..deca37d76f7d0 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,13 +8,13 @@
 define amdgpu_kernel void @local_workgroup_unordered_load(
 ; GFX6-LABEL: local_workgroup_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -74,13 +74,13 @@ entry:
 define amdgpu_kernel void @local_workgroup_monotonic_load(
 ; GFX6-LABEL: local_workgroup_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -140,14 +140,14 @@ entry:
 define amdgpu_kernel void @local_workgroup_acquire_load(
 ; GFX6-LABEL: local_workgroup_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -207,15 +207,15 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_load(
 ; GFX6-LABEL: local_workgroup_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_read_b32 v0, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -280,12 +280,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_unordered_store(
 ; GFX6-LABEL: local_workgroup_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -335,12 +335,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_monotonic_store(
 ; GFX6-LABEL: local_workgroup_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -390,12 +390,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_release_store(
 ; GFX6-LABEL: local_workgroup_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
@@ -451,12 +451,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_store(
 ; GFX6-LABEL: local_workgroup_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
@@ -512,12 +512,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_monotonic_atomicrmw(
 ; GFX6-LABEL: local_workgroup_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -567,12 +567,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_acquire_atomicrmw(
 ; GFX6-LABEL: local_workgroup_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_endpgm
@@ -629,12 +629,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_release_atomicrmw(
 ; GFX6-LABEL: local_workgroup_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
@@ -690,12 +690,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_workgroup_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
@@ -758,12 +758,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_workgroup_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
@@ -826,12 +826,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_workgroup_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -894,12 +894,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_workgroup_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
@@ -968,12 +968,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_workgroup_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
@@ -1042,8 +1042,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1104,8 +1104,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1173,8 +1173,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1241,8 +1241,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1316,8 +1316,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1391,8 +1391,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_workgroup_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1460,8 +1460,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_workgroup_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1535,8 +1535,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_workgroup_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1610,8 +1610,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_workgroup_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1685,8 +1685,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_workgroup_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1760,8 +1760,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1835,8 +1835,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1916,8 +1916,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -1997,8 +1997,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2072,8 +2072,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2153,8 +2153,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2234,8 +2234,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2315,8 +2315,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -2396,13 +2396,13 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_unordered_load(
 ; GFX6-LABEL: local_workgroup_one_as_unordered_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2462,13 +2462,13 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_monotonic_load(
 ; GFX6-LABEL: local_workgroup_one_as_monotonic_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2528,13 +2528,13 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acquire_load(
 ; GFX6-LABEL: local_workgroup_one_as_acquire_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2594,13 +2594,13 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_load(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_load:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX6-NEXT:    ds_read_b32 v0, v0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v1, v0
 ; GFX6-NEXT:    s_endpgm
@@ -2660,12 +2660,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_unordered_store(
 ; GFX6-LABEL: local_workgroup_one_as_unordered_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2715,12 +2715,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_monotonic_store(
 ; GFX6-LABEL: local_workgroup_one_as_monotonic_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2770,12 +2770,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_release_store(
 ; GFX6-LABEL: local_workgroup_one_as_release_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2825,12 +2825,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_store(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_store:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX6-NEXT:    ds_write_b32 v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2880,12 +2880,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_monotonic_atomicrmw(
 ; GFX6-LABEL: local_workgroup_one_as_monotonic_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2935,12 +2935,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acquire_atomicrmw(
 ; GFX6-LABEL: local_workgroup_one_as_acquire_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -2990,12 +2990,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_release_atomicrmw(
 ; GFX6-LABEL: local_workgroup_one_as_release_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3045,12 +3045,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acq_rel_atomicrmw(
 ; GFX6-LABEL: local_workgroup_one_as_acq_rel_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3100,12 +3100,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_atomicrmw(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v0, v0, v1
 ; GFX6-NEXT:    s_endpgm
 ;
@@ -3155,12 +3155,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acquire_ret_atomicrmw(
 ; GFX6-LABEL: local_workgroup_one_as_acquire_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3221,12 +3221,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acq_rel_ret_atomicrmw(
 ; GFX6-LABEL: local_workgroup_one_as_acq_rel_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3287,12 +3287,12 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_ret_atomicrmw(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_ret_atomicrmw:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s0, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s1, s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX6-NEXT:    ds_wrxchg_rtn_b32 v1, v0, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    ds_write_b32 v0, v1
@@ -3353,8 +3353,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_monotonic_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_monotonic_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3415,8 +3415,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acquire_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_acquire_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3477,8 +3477,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_release_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_release_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3539,8 +3539,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acq_rel_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_acq_rel_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3601,8 +3601,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_monotonic_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_monotonic_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3663,8 +3663,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acquire_acquire_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_acquire_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3725,8 +3725,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_release_acquire_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_release_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3787,8 +3787,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acq_rel_acquire_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_acq_rel_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3849,8 +3849,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_acquire_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_acquire_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3911,8 +3911,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_seq_cst_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_seq_cst_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -3973,8 +3973,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acquire_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_acquire_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4047,8 +4047,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_acq_rel_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4121,8 +4121,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_monotonic_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4195,8 +4195,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acquire_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_acquire_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4269,8 +4269,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_release_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_release_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4343,8 +4343,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_acq_rel_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_acq_rel_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4417,8 +4417,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_acquire_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_acquire_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
@@ -4491,8 +4491,8 @@ entry:
 define amdgpu_kernel void @local_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg(
 ; GFX6-LABEL: local_workgroup_one_as_seq_cst_seq_cst_ret_cmpxchg:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xa
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x1
 ; GFX6-NEXT:    s_mov_b32 m0, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
index 03977d8550057..03fb7d3eba4b4 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
@@ -8,18 +8,16 @@
 define amdgpu_kernel void @private_nontemporal_load_0(
 ; GFX6-LABEL: private_nontemporal_load_0:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
-; GFX6-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s10, -1
-; GFX6-NEXT:    s_mov_b32 s11, 0xe8f000
-; GFX6-NEXT:    s_add_u32 s8, s8, s3
+; GFX6-NEXT:    s_mov_b64 s[10:11], s[2:3]
+; GFX6-NEXT:    s_mov_b64 s[8:9], s[0:1]
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_add_u32 s8, s8, s7
 ; GFX6-NEXT:    s_addc_u32 s9, s9, 0
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s4
+; GFX6-NEXT:    v_mov_b32_e32 v0, s6
 ; GFX6-NEXT:    buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
@@ -103,19 +101,17 @@ entry:
 define amdgpu_kernel void @private_nontemporal_load_1(
 ; GFX6-LABEL: private_nontemporal_load_1:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
-; GFX6-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
-; GFX6-NEXT:    s_load_dword s4, s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s10, -1
-; GFX6-NEXT:    s_mov_b32 s11, 0xe8f000
-; GFX6-NEXT:    s_add_u32 s8, s8, s3
+; GFX6-NEXT:    s_mov_b64 s[10:11], s[2:3]
+; GFX6-NEXT:    s_mov_b64 s[8:9], s[0:1]
+; GFX6-NEXT:    s_load_dword s6, s[4:5], 0x0
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x2
+; GFX6-NEXT:    s_add_u32 s8, s8, s7
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX6-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s6, v0
 ; GFX6-NEXT:    buffer_load_dword v0, v0, s[8:11], 0 offen glc slc
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s3, 0x100f000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt vmcnt(0)
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
@@ -203,20 +199,18 @@ entry:
 define amdgpu_kernel void @private_nontemporal_store_0(
 ; GFX6-LABEL: private_nontemporal_store_0:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; GFX6-NEXT:    s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    s_mov_b32 s7, 0xe8f000
-; GFX6-NEXT:    s_add_u32 s4, s4, s3
-; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_addc_u32 s5, s5, 0
+; GFX6-NEXT:    s_mov_b64 s[10:11], s[2:3]
+; GFX6-NEXT:    s_mov_b64 s[8:9], s[0:1]
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x2
+; GFX6-NEXT:    s_add_u32 s8, s8, s7
+; GFX6-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_load_dword s1, s[2:3], 0x0
-; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    s_load_dword s0, s[0:1], 0x0
+; GFX6-NEXT:    v_mov_b32_e32 v1, s2
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v0, s1
-; GFX6-NEXT:    buffer_store_dword v0, v1, s[4:7], 0 offen glc slc
+; GFX6-NEXT:    v_mov_b32_e32 v0, s0
+; GFX6-NEXT:    buffer_store_dword v0, v1, s[8:11], 0 offen glc slc
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: private_nontemporal_store_0:
@@ -296,21 +290,19 @@ entry:
 define amdgpu_kernel void @private_nontemporal_store_1(
 ; GFX6-LABEL: private_nontemporal_store_1:
 ; GFX6:       ; %bb.0: ; %entry
-; GFX6-NEXT:    s_mov_b32 s4, SCRATCH_RSRC_DWORD0
-; GFX6-NEXT:    s_mov_b32 s5, SCRATCH_RSRC_DWORD1
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    s_mov_b32 s7, 0xe8f000
-; GFX6-NEXT:    s_add_u32 s4, s4, s3
-; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT:    s_mov_b64 s[10:11], s[2:3]
+; GFX6-NEXT:    s_mov_b64 s[8:9], s[0:1]
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX6-NEXT:    s_load_dword s2, s[4:5], 0x2
+; GFX6-NEXT:    s_add_u32 s8, s8, s7
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
-; GFX6-NEXT:    s_addc_u32 s5, s5, 0
+; GFX6-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_load_dword s1, s[2:3], 0x0
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    s_load_dword s0, s[0:1], 0x0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s2, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s1
-; GFX6-NEXT:    buffer_store_dword v1, v0, s[4:7], 0 offen glc slc
+; GFX6-NEXT:    v_mov_b32_e32 v1, s0
+; GFX6-NEXT:    buffer_store_dword v1, v0, s[8:11], 0 offen glc slc
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX7-LABEL: private_nontemporal_store_1:
diff --git a/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
index e96f2839ab029..6c438d80e5327 100644
--- a/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
+++ b/llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
@@ -72,3 +72,19 @@ body: |
     %1:sreg_32_xm0 = COPY %0
     S_ENDPGM 0, implicit %1
 ...
+
+# Make sure there's no assert when looking at the implicit use on S_ENDPGM
+# GCN-LABEL: name: s_to_v_copy_implicit_use
+# GCN: %0:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef %1:sreg_64, 0, 0, 0 :: (load 4, addrspace 4)
+# GCN-NEXT: %2:vgpr_32 = COPY %0
+# GCN-NEXT: S_ENDPGM 0, implicit %2
+---
+name: s_to_v_copy_implicit_use
+tracksRegLiveness: true
+body:               |
+  bb.0:
+    %0:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef %2:sreg_64, 0, 0, 0 :: (load 4, addrspace 4)
+    %1:vgpr_32 = COPY %0
+    S_ENDPGM 0, implicit %1
+
+...
diff --git a/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll b/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
index 40e7f6e7f8f65..2ae332ffa4374 100644
--- a/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
+++ b/llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll
@@ -1,6 +1,9 @@
 ; RUN: opt -S -O1 -mtriple=amdgcn-- -amdgpu-simplify-libcall < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GCN-POSTLINK %s
 ; RUN: opt -S -O1 -mtriple=amdgcn-- -amdgpu-simplify-libcall -amdgpu-prelink  <%s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GCN-PRELINK %s
 ; RUN: opt -S -O1 -mtriple=amdgcn-- -amdgpu-use-native -amdgpu-prelink < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GCN-NATIVE %s
+; RUN: opt -S -passes='default<O1>' -mtriple=amdgcn-- -amdgpu-simplify-libcall < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GCN-POSTLINK %s
+; RUN: opt -S -passes='default<O1>' -mtriple=amdgcn-- -amdgpu-simplify-libcall -amdgpu-prelink  <%s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GCN-PRELINK %s
+; RUN: opt -S -passes='default<O1>' -mtriple=amdgcn-- -amdgpu-use-native -amdgpu-prelink < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GCN-NATIVE %s
 
 ; GCN-LABEL: {{^}}define amdgpu_kernel void @test_sincos
 ; GCN-POSTLINK: call fast float @_Z3sinf(
diff --git a/llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll b/llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll
index 16150d0dd7c35..50a34fac05a64 100644
--- a/llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll
+++ b/llvm/test/CodeGen/AMDGPU/simplify-libcalls2.ll
@@ -1,5 +1,6 @@
 ; REQUIRES: asserts
 ; RUN: opt -S -amdgpu-simplifylib -debug-only=amdgpu-simplifylib -mtriple=amdgcn-unknown-amdhsa -disable-output < %s 2>&1 | FileCheck %s
+; RUN: opt -S -passes=amdgpu-simplifylib -debug-only=amdgpu-simplifylib -mtriple=amdgcn-unknown-amdhsa -disable-output < %s 2>&1 | FileCheck %s
 
 ; CHECK-NOT: AMDIC: try folding   call void @llvm.lifetime.start.p0i8
 ; CHECK-NOT: AMDIC: try folding   call void @llvm.lifetime.end.p0i8
diff --git a/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll b/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
index 416a72d51f992..c2f1bde56bff0 100644
--- a/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
+++ b/llvm/test/CodeGen/AMDGPU/transform-block-with-return-to-epilog.ll
@@ -14,7 +14,7 @@ entry:
 define amdgpu_ps float @test_return_to_epilog_into_end_block(i32 inreg %a, float %b) #0 {
   ; GCN-LABEL: name: test_return_to_epilog_into_end_block
   ; GCN: bb.0.entry:
-  ; GCN:   successors: %bb.1(0x7fffffff), %bb.2(0x00000001)
+  ; GCN:   successors: %bb.1(0x80000000), %bb.2(0x00000000)
   ; GCN:   liveins: $sgpr2, $vgpr0
   ; GCN:   S_CMP_LT_I32 killed renamable $sgpr2, 1, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC1 %bb.2, implicit killed $scc
@@ -49,7 +49,7 @@ define amdgpu_ps float @test_unify_return_to_epilog_into_end_block(i32 inreg %a,
   ; GCN:   liveins: $vgpr0
   ; GCN:   S_BRANCH %bb.5
   ; GCN: bb.2.else.if.cond:
-  ; GCN:   successors: %bb.3(0x7fffffff), %bb.4(0x00000001)
+  ; GCN:   successors: %bb.3(0x80000000), %bb.4(0x00000000)
   ; GCN:   liveins: $sgpr3, $vgpr1
   ; GCN:   S_CMP_LT_I32 killed renamable $sgpr3, 1, implicit-def $scc
   ; GCN:   S_CBRANCH_SCC1 %bb.4, implicit killed $scc
diff --git a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
index 5d5cfd318edfb..645eead8c2971 100644
--- a/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
@@ -1,6 +1,7 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=+unaligned-access-mode -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=UNALIGNED %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s
+; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefixes=SI,MUBUF,ALIGNED %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=+unaligned-access-mode -verify-machineinstrs< %s | FileCheck -check-prefixes=SI,MUBUF,UNALIGNED %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs< %s | FileCheck -check-prefixes=SI,MUBUF,ALIGNED %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-enable-flat-scratch -verify-machineinstrs < %s | FileCheck -check-prefixes=SI,FLATSCR,ALIGNED %s
 
 ; SI-LABEL: {{^}}local_unaligned_load_store_i16:
 ; SI: ds_read_u8
@@ -602,64 +603,70 @@ define amdgpu_kernel void @local_store_align1_v16i8(<16 x i8> addrspace(3)* %out
 }
 
 ; SI-LABEL: {{^}}private_load_align1_f64:
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
-; SI: buffer_load_ubyte
+; MUBUF: buffer_load_ubyte
+; MUBUF: buffer_load_ubyte
+; MUBUF: buffer_load_ubyte
+; MUBUF: buffer_load_ubyte
+; MUBUF: buffer_load_ubyte
+; MUBUF: buffer_load_ubyte
+; MUBUF: buffer_load_ubyte
+; MUBUF: buffer_load_ubyte
+; FLATSCR: scratch_load_dwordx2
 define double @private_load_align1_f64(double addrspace(5)* %in) {
   %x = load double, double addrspace(5)* %in, align 1
   ret double %x
 }
 
 ; SI-LABEL: {{^}}private_store_align1_f64:
-; SI: buffer_store_byte
-; SI: buffer_store_byte
-; SI: buffer_store_byte
-; SI: buffer_store_byte
-; SI: buffer_store_byte
-; SI: buffer_store_byte
-; SI: buffer_store_byte
-; SI: buffer_store_byte
+; MUBUF: buffer_store_byte
+; MUBUF: buffer_store_byte
+; MUBUF: buffer_store_byte
+; MUBUF: buffer_store_byte
+; MUBUF: buffer_store_byte
+; MUBUF: buffer_store_byte
+; MUBUF: buffer_store_byte
+; MUBUF: buffer_store_byte
+; FLATSCR: scratch_store_dwordx2
 define void @private_store_align1_f64(double addrspace(5)* %out, double %x) #0 {
   store double %x, double addrspace(5)* %out, align 1
   ret void
 }
 
 ; SI-LABEL: {{^}}private_load_align4_f64:
-; SI: buffer_load_dword
-; SI: buffer_load_dword
+; MUBUF: buffer_load_dword
+; MUBUF: buffer_load_dword
+; FLATSCR: scratch_load_dwordx2
 define double @private_load_align4_f64(double addrspace(5)* %in) {
   %x = load double, double addrspace(5)* %in, align 4
   ret double %x
 }
 
 ; SI-LABEL: {{^}}private_store_align4_f64:
-; SI: buffer_store_dword
-; SI: buffer_store_dword
+; MUBUF: buffer_store_dword
+; MUBUF: buffer_store_dword
+; FLATSCR: scratch_store_dwordx2
 define void @private_store_align4_f64(double addrspace(5)* %out, double %x) #0 {
   store double %x, double addrspace(5)* %out, align 4
   ret void
 }
 
 ; SI-LABEL: {{^}}private_load_align2_f64:
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
-; SI: buffer_load_ushort
+; MUBUF: buffer_load_ushort
+; MUBUF: buffer_load_ushort
+; MUBUF: buffer_load_ushort
+; MUBUF: buffer_load_ushort
+; FLATSCR: scratch_load_dwordx2
 define double @private_load_align2_f64(double addrspace(5)* %in) {
   %x = load double, double addrspace(5)* %in, align 2
   ret double %x
 }
 
 ; SI-LABEL: {{^}}private_store_align2_f64:
-; SI: buffer_store_short
-; SI: buffer_store_short
-; SI: buffer_store_short
-; SI: buffer_store_short
+; MUBUF: buffer_store_short
+; MUBUF: buffer_store_short
+; MUBUF: buffer_store_short
+; MUBUF: buffer_store_short
+; FLATSCR: scratch_store_dwordx2
 define void @private_store_align2_f64(double addrspace(5)* %out, double %x) #0 {
   store double %x, double addrspace(5)* %out, align 2
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
new file mode 100644
index 0000000000000..60990267bd6ca
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
@@ -0,0 +1,333 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
+; RUN: opt -S -si-annotate-control-flow -mtriple=amdgcn-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=SI-OPT %s
+
+define hidden void @widget() {
+; GCN-LABEL: widget:
+; GCN:       ; %bb.0: ; %bb
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-NEXT:    s_mov_b64 exec, s[4:5]
+; GCN-NEXT:    v_writelane_b32 v40, s33, 2
+; GCN-NEXT:    s_mov_b32 s33, s32
+; GCN-NEXT:    s_add_u32 s32, s32, 0x400
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    flat_load_dword v0, v[0:1]
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc, 21, v0
+; GCN-NEXT:    s_and_b64 vcc, exec, vcc
+; GCN-NEXT:    v_writelane_b32 v40, s30, 0
+; GCN-NEXT:    v_writelane_b32 v40, s31, 1
+; GCN-NEXT:    s_cbranch_vccz BB0_3
+; GCN-NEXT:  ; %bb.1: ; %bb4
+; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 9, v0
+; GCN-NEXT:    s_and_b64 vcc, exec, vcc
+; GCN-NEXT:    s_cbranch_vccnz BB0_4
+; GCN-NEXT:  ; %bb.2: ; %bb7
+; GCN-NEXT:    s_getpc_b64 s[4:5]
+; GCN-NEXT:    s_add_u32 s4, s4, wibble@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s5, s5, wibble@rel32@hi+12
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[4:5]
+; GCN-NEXT:    s_branch BB0_7
+; GCN-NEXT:  BB0_3: ; %bb2
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 21, v0
+; GCN-NEXT:    s_and_b64 vcc, exec, vcc
+; GCN-NEXT:    s_cbranch_vccnz BB0_6
+; GCN-NEXT:  BB0_4: ; %bb9
+; GCN-NEXT:    s_getpc_b64 s[4:5]
+; GCN-NEXT:    s_add_u32 s4, s4, wibble@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s5, s5, wibble@rel32@hi+12
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[4:5]
+; GCN-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v0
+; GCN-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GCN-NEXT:    s_cbranch_execnz BB0_7
+; GCN-NEXT:  ; %bb.5: ; %bb9.bb12_crit_edge
+; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GCN-NEXT:  BB0_6: ; %bb12
+; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_mov_b32_e32 v0, 0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    flat_store_dword v[0:1], v2
+; GCN-NEXT:  BB0_7: ; %UnifiedReturnBlock
+; GCN-NEXT:    v_readlane_b32 s4, v40, 0
+; GCN-NEXT:    v_readlane_b32 s5, v40, 1
+; GCN-NEXT:    s_sub_u32 s32, s32, 0x400
+; GCN-NEXT:    v_readlane_b32 s33, v40, 2
+; GCN-NEXT:    s_or_saveexec_b64 s[6:7], -1
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-NEXT:    s_mov_b64 exec, s[6:7]
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    s_setpc_b64 s[4:5]
+; SI-OPT-LABEL: @widget(
+; SI-OPT-NEXT:  bb:
+; SI-OPT-NEXT:    [[TMP:%.*]] = load i32, i32 addrspace(1)* null, align 16
+; SI-OPT-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[TMP]], 21
+; SI-OPT-NEXT:    br i1 [[TMP1]], label [[BB4:%.*]], label [[BB2:%.*]]
+; SI-OPT:       bb2:
+; SI-OPT-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[TMP]], 21
+; SI-OPT-NEXT:    br i1 [[TMP3]], label [[BB12:%.*]], label [[BB9:%.*]]
+; SI-OPT:       bb4:
+; SI-OPT-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP]], 9
+; SI-OPT-NEXT:    br i1 [[TMP5]], label [[BB7:%.*]], label [[BB9]]
+; SI-OPT:       bb6:
+; SI-OPT-NEXT:    ret void
+; SI-OPT:       bb7:
+; SI-OPT-NEXT:    [[TMP8:%.*]] = call float @wibble()
+; SI-OPT-NEXT:    ret void
+; SI-OPT:       bb9:
+; SI-OPT-NEXT:    [[TMP10:%.*]] = call float @wibble()
+; SI-OPT-NEXT:    [[TMP11:%.*]] = fcmp nsz ogt float [[TMP10]], 0.000000e+00
+; SI-OPT-NEXT:    [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP11]])
+; SI-OPT-NEXT:    [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0
+; SI-OPT-NEXT:    [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1
+; SI-OPT-NEXT:    br i1 [[TMP1]], label [[BB6:%.*]], label [[BB9_BB12_CRIT_EDGE:%.*]]
+; SI-OPT:       bb9.bb12_crit_edge:
+; SI-OPT-NEXT:    call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
+; SI-OPT-NEXT:    br label [[BB12]]
+; SI-OPT:       bb12:
+; SI-OPT-NEXT:    store float 0.000000e+00, float addrspace(1)* null, align 8
+; SI-OPT-NEXT:    ret void
+;
+bb:
+  %tmp = load i32, i32 addrspace(1)* null, align 16
+  %tmp1 = icmp slt i32 %tmp, 21
+  br i1 %tmp1, label %bb4, label %bb2
+
+bb2:                                              ; preds = %bb
+  %tmp3 = icmp eq i32 %tmp, 21
+  br i1 %tmp3, label %bb12, label %bb9
+
+bb4:                                              ; preds = %bb
+  %tmp5 = icmp eq i32 %tmp, 9
+  br i1 %tmp5, label %bb7, label %bb9
+
+bb6:                                              ; preds = %bb9
+  ret void
+
+bb7:                                              ; preds = %bb4
+  %tmp8 = call float @wibble()
+  ret void
+
+bb9:                                              ; preds = %bb4, %bb2
+  %tmp10 = call float @wibble()
+  %tmp11 = fcmp nsz ogt float %tmp10, 0.000000e+00
+  br i1 %tmp11, label %bb6, label %bb12
+
+bb12:                                             ; preds = %bb9, %bb2
+  store float 0.000000e+00, float addrspace(1)* null, align 8
+  ret void
+}
+
+declare hidden float @wibble() local_unnamed_addr
+
+
+define hidden void @blam() {
+; SI-OPT-LABEL: @blam(
+; SI-OPT-NEXT:  bb:
+; SI-OPT-NEXT:    [[TMP:%.*]] = load float, float* null, align 16
+; SI-OPT-NEXT:    br label [[BB2:%.*]]
+; SI-OPT:       bb1:
+; SI-OPT-NEXT:    br label [[BB2]]
+; SI-OPT:       bb2:
+; SI-OPT-NEXT:    [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
+; SI-OPT-NEXT:    [[GEP:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* null, i32 [[TID]]
+; SI-OPT-NEXT:    [[TMP3:%.*]] = load i32, i32 addrspace(1)* [[GEP]], align 16
+; SI-OPT-NEXT:    store float 0.000000e+00, float addrspace(5)* null, align 8
+; SI-OPT-NEXT:    br label [[BB4:%.*]]
+; SI-OPT:       bb4:
+; SI-OPT-NEXT:    [[TMP5:%.*]] = icmp slt i32 [[TMP3]], 3
+; SI-OPT-NEXT:    [[TMP0:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP5]])
+; SI-OPT-NEXT:    [[TMP1:%.*]] = extractvalue { i1, i64 } [[TMP0]], 0
+; SI-OPT-NEXT:    [[TMP2:%.*]] = extractvalue { i1, i64 } [[TMP0]], 1
+; SI-OPT-NEXT:    br i1 [[TMP1]], label [[BB8:%.*]], label [[BB6:%.*]]
+; SI-OPT:       bb6:
+; SI-OPT-NEXT:    call void @llvm.amdgcn.end.cf.i64(i64 [[TMP2]])
+; SI-OPT-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP3]], 3
+; SI-OPT-NEXT:    br i1 [[TMP7]], label [[BB11:%.*]], label [[BB1:%.*]]
+; SI-OPT:       bb8:
+; SI-OPT-NEXT:    [[TMP9:%.*]] = icmp eq i32 [[TMP3]], 1
+; SI-OPT-NEXT:    [[TMP3:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP9]])
+; SI-OPT-NEXT:    [[TMP4:%.*]] = extractvalue { i1, i64 } [[TMP3]], 0
+; SI-OPT-NEXT:    [[TMP5:%.*]] = extractvalue { i1, i64 } [[TMP3]], 1
+; SI-OPT-NEXT:    br i1 [[TMP4]], label [[BB10:%.*]], label [[BB8_BB1_CRIT_EDGE:%.*]]
+; SI-OPT:       bb8.bb1_crit_edge:
+; SI-OPT-NEXT:    call void @llvm.amdgcn.end.cf.i64(i64 [[TMP5]])
+; SI-OPT-NEXT:    br label [[BB1]]
+; SI-OPT:       bb10:
+; SI-OPT-NEXT:    store float 0x7FF8000000000000, float addrspace(5)* null, align 16
+; SI-OPT-NEXT:    br label [[BB18:%.*]]
+; SI-OPT:       bb11:
+; SI-OPT-NEXT:    [[TMP12:%.*]] = call float @spam()
+; SI-OPT-NEXT:    [[TMP13:%.*]] = fcmp nsz oeq float [[TMP12]], 0.000000e+00
+; SI-OPT-NEXT:    [[TMP6:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP13]])
+; SI-OPT-NEXT:    [[TMP7:%.*]] = extractvalue { i1, i64 } [[TMP6]], 0
+; SI-OPT-NEXT:    [[TMP8:%.*]] = extractvalue { i1, i64 } [[TMP6]], 1
+; SI-OPT-NEXT:    br i1 [[TMP7]], label [[BB2]], label [[BB14:%.*]]
+; SI-OPT:       bb14:
+; SI-OPT-NEXT:    call void @llvm.amdgcn.end.cf.i64(i64 [[TMP8]])
+; SI-OPT-NEXT:    [[TMP15:%.*]] = fcmp nsz oeq float [[TMP]], 0.000000e+00
+; SI-OPT-NEXT:    [[TMP9:%.*]] = call { i1, i64 } @llvm.amdgcn.if.i64(i1 [[TMP15]])
+; SI-OPT-NEXT:    [[TMP10:%.*]] = extractvalue { i1, i64 } [[TMP9]], 0
+; SI-OPT-NEXT:    [[TMP11:%.*]] = extractvalue { i1, i64 } [[TMP9]], 1
+; SI-OPT-NEXT:    br i1 [[TMP10]], label [[BB17:%.*]], label [[BB16:%.*]]
+; SI-OPT:       bb16:
+; SI-OPT-NEXT:    call void @llvm.amdgcn.end.cf.i64(i64 [[TMP11]])
+; SI-OPT-NEXT:    store float 0x7FF8000000000000, float addrspace(5)* null, align 16
+; SI-OPT-NEXT:    br label [[BB17]]
+; SI-OPT:       bb17:
+; SI-OPT-NEXT:    store float [[TMP]], float addrspace(5)* null, align 16
+; SI-OPT-NEXT:    br label [[BB18]]
+; SI-OPT:       bb18:
+; SI-OPT-NEXT:    store float 0x7FF8000000000000, float addrspace(5)* null, align 4
+; SI-OPT-NEXT:    br label [[BB2]]
+;
+; GCN-LABEL: blam:
+; GCN:       ; %bb.0: ; %bb
+; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT:    s_or_saveexec_b64 s[4:5], -1
+; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
+; GCN-NEXT:    s_mov_b64 exec, s[4:5]
+; GCN-NEXT:    v_writelane_b32 v43, s33, 4
+; GCN-NEXT:    s_mov_b32 s33, s32
+; GCN-NEXT:    s_add_u32 s32, s32, 0x800
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT:    v_writelane_b32 v43, s34, 0
+; GCN-NEXT:    v_writelane_b32 v43, s35, 1
+; GCN-NEXT:    v_writelane_b32 v43, s36, 2
+; GCN-NEXT:    v_writelane_b32 v43, s37, 3
+; GCN-NEXT:    s_mov_b64 s[4:5], 0
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
+; GCN-NEXT:    flat_load_dword v40, v[1:2]
+; GCN-NEXT:    v_mov_b32_e32 v42, 0
+; GCN-NEXT:    s_getpc_b64 s[36:37]
+; GCN-NEXT:    s_add_u32 s36, s36, spam@rel32@lo+4
+; GCN-NEXT:    s_addc_u32 s37, s37, spam@rel32@hi+12
+; GCN-NEXT:    v_lshlrev_b32_e32 v41, 2, v0
+; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; GCN-NEXT:    v_cmp_eq_f32_e64 s[34:35], 0, v40
+; GCN-NEXT:    s_branch BB1_3
+; GCN-NEXT:  BB1_1: ; %bb10
+; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
+; GCN-NEXT:    s_or_b64 exec, exec, s[6:7]
+; GCN-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; GCN-NEXT:  BB1_2: ; %bb18
+; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
+; GCN-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
+; GCN-NEXT:    s_mov_b64 s[4:5], 0
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; GCN-NEXT:  BB1_3: ; %bb2
+; GCN-NEXT:    ; =>This Loop Header: Depth=1
+; GCN-NEXT:    ; Child Loop BB1_4 Depth 2
+; GCN-NEXT:    s_mov_b64 s[6:7], 0
+; GCN-NEXT:  BB1_4: ; %bb2
+; GCN-NEXT:    ; Parent Loop BB1_3 Depth=1
+; GCN-NEXT:    ; => This Inner Loop Header: Depth=2
+; GCN-NEXT:    flat_load_dword v0, v[41:42]
+; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], 0
+; GCN-NEXT:    s_waitcnt vmcnt(1)
+; GCN-NEXT:    v_cmp_gt_i32_e32 vcc, 3, v0
+; GCN-NEXT:    s_and_saveexec_b64 s[8:9], vcc
+; GCN-NEXT:    s_cbranch_execz BB1_6
+; GCN-NEXT:  ; %bb.5: ; %bb8
+; GCN-NEXT:    ; in Loop: Header=BB1_4 Depth=2
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GCN-NEXT:    s_or_b64 s[6:7], vcc, s[6:7]
+; GCN-NEXT:    s_mov_b64 s[4:5], 0
+; GCN-NEXT:    s_andn2_b64 exec, exec, s[6:7]
+; GCN-NEXT:    s_cbranch_execnz BB1_4
+; GCN-NEXT:    s_branch BB1_1
+; GCN-NEXT:  BB1_6: ; %bb6
+; GCN-NEXT:    ; in Loop: Header=BB1_4 Depth=2
+; GCN-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 3, v0
+; GCN-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GCN-NEXT:    s_mov_b64 s[6:7], 0
+; GCN-NEXT:    s_andn2_b64 exec, exec, s[4:5]
+; GCN-NEXT:    s_cbranch_execnz BB1_4
+; GCN-NEXT:  ; %bb.7: ; %bb11
+; GCN-NEXT:    ; in Loop: Header=BB1_4 Depth=2
+; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GCN-NEXT:    s_swappc_b64 s[30:31], s[36:37]
+; GCN-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v0
+; GCN-NEXT:    s_mov_b64 s[4:5], 0
+; GCN-NEXT:    s_mov_b64 s[6:7], 0
+; GCN-NEXT:    s_and_saveexec_b64 s[8:9], vcc
+; GCN-NEXT:    s_cbranch_execnz BB1_4
+; GCN-NEXT:  ; %bb.8: ; %bb14
+; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
+; GCN-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GCN-NEXT:    s_and_saveexec_b64 s[4:5], s[34:35]
+; GCN-NEXT:    s_cbranch_execnz BB1_10
+; GCN-NEXT:  ; %bb.9: ; %bb16
+; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
+; GCN-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GCN-NEXT:    v_mov_b32_e32 v0, 0x7fc00000
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; GCN-NEXT:  BB1_10: ; %bb17
+; GCN-NEXT:    ; in Loop: Header=BB1_3 Depth=1
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], 0
+; GCN-NEXT:    s_branch BB1_2
+bb:
+  %tmp = load float, float* null, align 16
+  br label %bb2
+
+bb1:                                              ; preds = %bb8, %bb6
+  br label %bb2
+
+bb2:
+  %tid = call i32 @llvm.amdgcn.workitem.id.x()
+  %gep  = getelementptr inbounds i32, i32 addrspace(1)* null, i32 %tid
+  %tmp3 = load i32, i32 addrspace(1)* %gep, align 16
+  store float 0.000000e+00, float addrspace(5)* null, align 8
+  br label %bb4
+
+bb4:                                              ; preds = %bb2
+  %tmp5 = icmp slt i32 %tmp3, 3
+  br i1 %tmp5, label %bb8, label %bb6
+
+bb6:                                              ; preds = %bb4
+  %tmp7 = icmp eq i32 %tmp3, 3
+  br i1 %tmp7, label %bb11, label %bb1
+
+bb8:                                              ; preds = %bb4
+  %tmp9 = icmp eq i32 %tmp3, 1
+  br i1 %tmp9, label %bb10, label %bb1
+
+bb10:                                             ; preds = %bb8
+  store float 0x7FF8000000000000, float addrspace(5)* null, align 16
+  br label %bb18
+
+bb11:                                             ; preds = %bb6
+  %tmp12 = call float @spam()
+  %tmp13 = fcmp nsz oeq float %tmp12, 0.000000e+00
+  br i1 %tmp13, label %bb2, label %bb14
+
+bb14:                                             ; preds = %bb11
+  %tmp15 = fcmp nsz oeq float %tmp, 0.000000e+00
+  br i1 %tmp15, label %bb17, label %bb16
+
+bb16:                                             ; preds = %bb14
+  store float 0x7FF8000000000000, float addrspace(5)* null, align 16
+  br label %bb17
+
+bb17:                                             ; preds = %bb16, %bb14
+  store float %tmp, float addrspace(5)* null, align 16
+  br label %bb18
+
+bb18:                                             ; preds = %bb17, %bb10
+  store float 0x7FF8000000000000, float addrspace(5)* null, align 4
+  br label %bb2
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x()
+
+declare hidden float @spam()
diff --git a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
index de326d50e166f..9e3971b602c56 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
@@ -284,7 +284,7 @@ bb13:                                             ; preds = %.preheader
 ; OPT-NEXT: %x = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %tmp, i64 0, i64 0
 ; OPT-NEXT: store i32 0, i32 addrspace(5)* %x, align 16
 ; OPT-NEXT: %0 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp, align 16
-; OPT-NEXT: %1 = shufflevector <4 x i32> %0, <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+; OPT-NEXT: %1 = shufflevector <4 x i32> %0, <4 x i32> <i32 poison, i32 1, i32 2, i32 3>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
 ; OPT-NEXT: store <4 x i32> %1, <4 x i32> addrspace(5)* %tmp, align 16
 ; OPT-NEXT: %2 = extractelement <4 x i32> %1, i32 %index
 ; OPT-NEXT: store i32 %2, i32 addrspace(1)* %out, align 4
diff --git a/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
index 2f4143547a01a..af2009c7a2526 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
+++ b/llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll
@@ -22,7 +22,7 @@ entry:
 ; for.body -> for.cond.backedge (100%)
 ;          -> cond.false.i (0%)
 ; CHECK: bb.1.for.body:
-; CHECK: successors: %bb.2(0x80000000), %bb.4(0x00000001)
+; CHECK: successors: %bb.2(0x80000000), %bb.4(0x00000000)
 for.body:
   br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1
 
diff --git a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
index 9720df795eb6d..ef907ee3ff499 100644
--- a/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
+++ b/llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
@@ -168,7 +168,7 @@ entry:
 ; CHECK-LABEL: cmp_slt0
 ; CHECK: sub
 ; CHECK: cmn
-; CHECK: bgt
+; CHECK: ble
   %load = load i32, i32* @t, align 4
   %sub = sub i32 %load, 17
   %cmp = icmp slt i32 %sub, 0
diff --git a/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll b/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
index 8d45c3cd06413..eab750d2b8466 100644
--- a/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
+++ b/llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll
@@ -23,7 +23,7 @@ define void @main() {
 ; CHECK-NEXT:    bne .LBB0_8
 ; CHECK-NEXT:  .LBB0_2: @ %for.cond14.preheader.us.i.i.i
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    cbnz r0, .LBB0_7
+; CHECK-NEXT:    cbnz r0, .LBB0_6
 ; CHECK-NEXT:  @ %bb.3: @ %for.cond14.preheader.us.i.i.i
 ; CHECK-NEXT:    @ in Loop: Header=BB0_2 Depth=1
 ; CHECK-NEXT:    lsls r1, r0, #2
@@ -34,22 +34,22 @@ define void @main() {
 ; CHECK-NEXT:    .p2align 2
 ; CHECK-NEXT:  .LJTI0_0:
 ; CHECK-NEXT:    b.w .LBB0_5
-; CHECK-NEXT:    b.w .LBB0_7
 ; CHECK-NEXT:    b.w .LBB0_6
-; CHECK-NEXT:    b.w .LBB0_8
-; CHECK-NEXT:    b.w .LBB0_7
-; CHECK-NEXT:    b.w .LBB0_7
-; CHECK-NEXT:    b.w .LBB0_7
-; CHECK-NEXT:    b.w .LBB0_7
-; CHECK-NEXT:    b.w .LBB0_7
-; CHECK-NEXT:    b.w .LBB0_7
 ; CHECK-NEXT:    b.w .LBB0_7
+; CHECK-NEXT:    b.w .LBB0_8
+; CHECK-NEXT:    b.w .LBB0_6
+; CHECK-NEXT:    b.w .LBB0_6
+; CHECK-NEXT:    b.w .LBB0_6
+; CHECK-NEXT:    b.w .LBB0_6
+; CHECK-NEXT:    b.w .LBB0_6
+; CHECK-NEXT:    b.w .LBB0_6
+; CHECK-NEXT:    b.w .LBB0_6
 ; CHECK-NEXT:    b.w .LBB0_5
 ; CHECK-NEXT:  .LBB0_5: @ %for.cond14.preheader.us.i.i.i
 ; CHECK-NEXT:    @ in Loop: Header=BB0_2 Depth=1
 ; CHECK-NEXT:    b .LBB0_2
-; CHECK-NEXT:  .LBB0_6: @ %lbl_1394.i.i.i.loopexit
-; CHECK-NEXT:  .LBB0_7: @ %func_1.exit.loopexit
+; CHECK-NEXT:  .LBB0_6: @ %func_1.exit.loopexit
+; CHECK-NEXT:  .LBB0_7: @ %lbl_1394.i.i.i.loopexit
 ; CHECK-NEXT:  .LBB0_8: @ %for.end476.i.i.i.loopexit
 entry:
   %0 = load volatile i32**, i32*** @g_566, align 4
diff --git a/llvm/test/CodeGen/ARM/vadd.ll b/llvm/test/CodeGen/ARM/vadd.ll
index dd35dd1ccfb9b..5f0ddd17c8c7c 100644
--- a/llvm/test/CodeGen/ARM/vadd.ll
+++ b/llvm/test/CodeGen/ARM/vadd.ll
@@ -1,275 +1,370 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-
-define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddi8:
-;CHECK: vadd.i8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = add <8 x i8> %tmp1, %tmp2
-	ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddi16:
-;CHECK: vadd.i16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = add <4 x i16> %tmp1, %tmp2
-	ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddi32:
-;CHECK: vadd.i32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = add <2 x i32> %tmp1, %tmp2
-	ret <2 x i32> %tmp3
-}
-
-define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK-LABEL: vaddi64:
-;CHECK: vadd.i64
-	%tmp1 = load <1 x i64>, <1 x i64>* %A
-	%tmp2 = load <1 x i64>, <1 x i64>* %B
-	%tmp3 = add <1 x i64> %tmp1, %tmp2
-	ret <1 x i64> %tmp3
-}
-
-define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vaddf32:
-;CHECK: vadd.f32
-	%tmp1 = load <2 x float>, <2 x float>* %A
-	%tmp2 = load <2 x float>, <2 x float>* %B
-	%tmp3 = fadd <2 x float> %tmp1, %tmp2
-	ret <2 x float> %tmp3
-}
-
-define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddQi8:
-;CHECK: vadd.i8
-	%tmp1 = load <16 x i8>, <16 x i8>* %A
-	%tmp2 = load <16 x i8>, <16 x i8>* %B
-	%tmp3 = add <16 x i8> %tmp1, %tmp2
-	ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddQi16:
-;CHECK: vadd.i16
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i16>, <8 x i16>* %B
-	%tmp3 = add <8 x i16> %tmp1, %tmp2
-	ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddQi32:
-;CHECK: vadd.i32
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i32>, <4 x i32>* %B
-	%tmp3 = add <4 x i32> %tmp1, %tmp2
-	ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vaddQi64:
-;CHECK: vadd.i64
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i64>, <2 x i64>* %B
-	%tmp3 = add <2 x i64> %tmp1, %tmp2
-	ret <2 x i64> %tmp3
-}
-
-define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vaddQf32:
-;CHECK: vadd.f32
-	%tmp1 = load <4 x float>, <4 x float>* %A
-	%tmp2 = load <4 x float>, <4 x float>* %B
-	%tmp3 = fadd <4 x float> %tmp1, %tmp2
-	ret <4 x float> %tmp3
-}
-
-define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vraddhni16:
-;CHECK: vraddhn.i16
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i16>, <8 x i16>* %B
-	%tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
-	ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vraddhni32:
-;CHECK: vraddhn.i32
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i32>, <4 x i32>* %B
-	%tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
-	ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vraddhni64:
-;CHECK: vraddhn.i64
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i64>, <2 x i64>* %B
-	%tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
-	ret <2 x i32> %tmp3
-}
-
-declare <8 x i8>  @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i8> @vaddhni16_natural(<8 x i16> %A, <8 x i16> %B) nounwind {
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vaddi8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddi8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.i8 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = add <8 x i8> %A, %B
+  ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vaddi16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddi16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.i16 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = add <4 x i16> %A, %B
+  ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vaddi32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddi32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.i32 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = add <2 x i32> %A, %B
+  ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vaddi64(<1 x i64> %A, <1 x i64> %B) {
+; CHECK-LABEL: vaddi64:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.i64 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = add <1 x i64> %A, %B
+  ret <1 x i64> %tmp3
+}
+
+define <2 x float> @vaddf32(<2 x float> %A, <2 x float> %B) {
+; CHECK-LABEL: vaddf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.f32 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = fadd <2 x float> %A, %B
+  ret <2 x float> %tmp3
+}
+
+define <16 x i8> @vaddQi8(<16 x i8> %A, <16 x i8> %B) {
+; CHECK-LABEL: vaddQi8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.i8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = add <16 x i8> %A, %B
+  ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vaddQi16(<8 x i16> %A, <8 x i16> %B) {
+; CHECK-LABEL: vaddQi16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.i16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = add <8 x i16> %A, %B
+  ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vaddQi32(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: vaddQi32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.i32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = add <4 x i32> %A, %B
+  ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vaddQi64(<2 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: vaddQi64:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.i64 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = add <2 x i64> %A, %B
+  ret <2 x i64> %tmp3
+}
+
+define <4 x float> @vaddQf32(<4 x float> %A, <4 x float> %B) {
+; CHECK-LABEL: vaddQf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vadd.f32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = fadd <4 x float> %A, %B
+  ret <4 x float> %tmp3
+}
+
+define <8 x i8> @vraddhni16(<8 x i16> %A, <8 x i16> %B) {
+; CHECK-LABEL: vraddhni16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vraddhn.i16 d0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = call <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16> %A, <8 x i16> %B)
+  ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vraddhni32(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: vraddhni32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vraddhn.i32 d0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = call <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32> %A, <4 x i32> %B)
+  ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vraddhni64(<2 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: vraddhni64:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vraddhn.i64 d0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = call <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64> %A, <2 x i64> %B)
+  ret <2 x i32> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) readnone
+declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) readnone
+declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) readnone
+
+define <8 x i8> @vaddhni16_natural(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: vaddhni16_natural:
-; CHECK: vaddhn.i16
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddhn.i16 d0, q0, q1
+; CHECK-NEXT:    bx lr
   %sum = add <8 x i16> %A, %B
   %shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
   %trunc = trunc <8 x i16> %shift to <8 x i8>
   ret <8 x i8> %trunc
 }
 
-define <4 x i16> @vaddhni32_natural(<4 x i32> %A, <4 x i32> %B) nounwind {
+define <4 x i16> @vaddhni32_natural(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: vaddhni32_natural:
-; CHECK: vaddhn.i32
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddhn.i32 d0, q0, q1
+; CHECK-NEXT:    bx lr
   %sum = add <4 x i32> %A, %B
   %shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
   %trunc = trunc <4 x i32> %shift to <4 x i16>
   ret <4 x i16> %trunc
 }
 
-define <2 x i32> @vaddhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind {
+define <2 x i32> @vaddhni64_natural(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: vaddhni64_natural:
-; CHECK: vaddhn.i64
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddhn.i64 d0, q0, q1
+; CHECK-NEXT:    bx lr
   %sum = add <2 x i64> %A, %B
   %shift = lshr <2 x i64> %sum, <i64 32, i64 32>
   %trunc = trunc <2 x i64> %shift to <2 x i32>
   ret <2 x i32> %trunc
 }
 
-define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddls8:
-;CHECK: vaddl.s8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
-	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
-	%tmp5 = add <8 x i16> %tmp3, %tmp4
-	ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddls16:
-;CHECK: vaddl.s16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
-	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
-	%tmp5 = add <4 x i32> %tmp3, %tmp4
-	ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddls32:
-;CHECK: vaddl.s32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
-	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
-	%tmp5 = add <2 x i64> %tmp3, %tmp4
-	ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddlu8:
-;CHECK: vaddl.u8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
-	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
-	%tmp5 = add <8 x i16> %tmp3, %tmp4
-	ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddlu16:
-;CHECK: vaddl.u16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
-	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
-	%tmp5 = add <4 x i32> %tmp3, %tmp4
-	ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddlu32:
-;CHECK: vaddl.u32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
-	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
-	%tmp5 = add <2 x i64> %tmp3, %tmp4
-	ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddws8:
-;CHECK: vaddw.s8
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
-	%tmp4 = add <8 x i16> %tmp1, %tmp3
-	ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddws16:
-;CHECK: vaddw.s16
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
-	%tmp4 = add <4 x i32> %tmp1, %tmp3
-	ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddws32:
-;CHECK: vaddw.s32
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
-	%tmp4 = add <2 x i64> %tmp1, %tmp3
-	ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vaddwu8:
-;CHECK: vaddw.u8
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
-	%tmp4 = add <8 x i16> %tmp1, %tmp3
-	ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vaddwu16:
-;CHECK: vaddw.u16
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
-	%tmp4 = add <4 x i32> %tmp1, %tmp3
-	ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vaddwu32:
-;CHECK: vaddw.u32
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
-	%tmp4 = add <2 x i64> %tmp1, %tmp3
-	ret <2 x i64> %tmp4
+define <8 x i16> @vaddls8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddls8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddl.s8 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <8 x i8> %A to <8 x i16>
+  %tmp4 = sext <8 x i8> %B to <8 x i16>
+  %tmp5 = add <8 x i16> %tmp3, %tmp4
+  ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vaddls16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddls16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddl.s16 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <4 x i16> %A to <4 x i32>
+  %tmp4 = sext <4 x i16> %B to <4 x i32>
+  %tmp5 = add <4 x i32> %tmp3, %tmp4
+  ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @vaddls32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddls32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddl.s32 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <2 x i32> %A to <2 x i64>
+  %tmp4 = sext <2 x i32> %B to <2 x i64>
+  %tmp5 = add <2 x i64> %tmp3, %tmp4
+  ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @vaddlu8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddlu8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddl.u8 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <8 x i8> %A to <8 x i16>
+  %tmp4 = zext <8 x i8> %B to <8 x i16>
+  %tmp5 = add <8 x i16> %tmp3, %tmp4
+  ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vaddlu16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddlu16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddl.u16 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <4 x i16> %A to <4 x i32>
+  %tmp4 = zext <4 x i16> %B to <4 x i32>
+  %tmp5 = add <4 x i32> %tmp3, %tmp4
+  ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @vaddlu32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddlu32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddl.u32 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <2 x i32> %A to <2 x i64>
+  %tmp4 = zext <2 x i32> %B to <2 x i64>
+  %tmp5 = add <2 x i64> %tmp3, %tmp4
+  ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @vaddla8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddla8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u8 q8, d1
+; CHECK-NEXT:    vmovl.u8 q9, d0
+; CHECK-NEXT:    vadd.i16 q0, q9, q8
+; CHECK-NEXT:    vbic.i16 q0, #0xff00
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <8 x i8> %A to <8 x i16>
+  %tmp4 = zext <8 x i8> %B to <8 x i16>
+  %tmp5 = add <8 x i16> %tmp3, %tmp4
+  %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @vaddla16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddla16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u16 q8, d1
+; CHECK-NEXT:    vmovl.u16 q9, d0
+; CHECK-NEXT:    vmov.i32 q10, #0xffff
+; CHECK-NEXT:    vadd.i32 q8, q9, q8
+; CHECK-NEXT:    vand q0, q8, q10
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <4 x i16> %A to <4 x i32>
+  %tmp4 = zext <4 x i16> %B to <4 x i32>
+  %tmp5 = add <4 x i32> %tmp3, %tmp4
+  %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @vaddla32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddla32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u32 q8, d1
+; CHECK-NEXT:    vmovl.u32 q9, d0
+; CHECK-NEXT:    vmov.i64 q10, #0xffffffff
+; CHECK-NEXT:    vadd.i64 q8, q9, q8
+; CHECK-NEXT:    vand q0, q8, q10
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <2 x i32> %A to <2 x i64>
+  %tmp4 = zext <2 x i32> %B to <2 x i64>
+  %tmp5 = add <2 x i64> %tmp3, %tmp4
+  %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
+define <8 x i16> @vaddws8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddws8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddw.s8 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <8 x i8> %B to <8 x i16>
+  %tmp4 = add <8 x i16> %A, %tmp3
+  ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vaddws16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddws16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddw.s16 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <4 x i16> %B to <4 x i32>
+  %tmp4 = add <4 x i32> %A, %tmp3
+  ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vaddws32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddws32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddw.s32 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <2 x i32> %B to <2 x i64>
+  %tmp4 = add <2 x i64> %A, %tmp3
+  ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vaddwu8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddwu8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddw.u8 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <8 x i8> %B to <8 x i16>
+  %tmp4 = add <8 x i16> %A, %tmp3
+  ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vaddwu16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddwu16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddw.u16 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <4 x i16> %B to <4 x i32>
+  %tmp4 = add <4 x i32> %A, %tmp3
+  ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vaddwu32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddwu32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vaddw.u32 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <2 x i32> %B to <2 x i64>
+  %tmp4 = add <2 x i64> %A, %tmp3
+  ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vaddwa8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vaddwa8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u8 q8, d2
+; CHECK-NEXT:    vadd.i16 q0, q0, q8
+; CHECK-NEXT:    vbic.i16 q0, #0xff00
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <8 x i8> %B to <8 x i16>
+  %tmp4 = add <8 x i16> %A, %tmp3
+  %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @vaddwa16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vaddwa16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u16 q8, d2
+; CHECK-NEXT:    vmov.i32 q9, #0xffff
+; CHECK-NEXT:    vadd.i32 q8, q0, q8
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <4 x i16> %B to <4 x i32>
+  %tmp4 = add <4 x i32> %A, %tmp3
+  %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @vaddwa32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vaddwa32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u32 q8, d2
+; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
+; CHECK-NEXT:    vadd.i64 q8, q0, q8
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <2 x i32> %B to <2 x i64>
+  %tmp4 = add <2 x i64> %A, %tmp3
+  %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
 }
diff --git a/llvm/test/CodeGen/ARM/vmla.ll b/llvm/test/CodeGen/ARM/vmla.ll
index 8ca33a9eecacd..14d425da2df48 100644
--- a/llvm/test/CodeGen/ARM/vmla.ll
+++ b/llvm/test/CodeGen/ARM/vmla.ll
@@ -1,175 +1,234 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-
-define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK-LABEL: vmlai8:
-;CHECK: vmla.i8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = load <8 x i8>, <8 x i8>* %C
-	%tmp4 = mul <8 x i8> %tmp2, %tmp3
-	%tmp5 = add <8 x i8> %tmp1, %tmp4
-	ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlai16:
-;CHECK: vmla.i16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = load <4 x i16>, <4 x i16>* %C
-	%tmp4 = mul <4 x i16> %tmp2, %tmp3
-	%tmp5 = add <4 x i16> %tmp1, %tmp4
-	ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlai32:
-;CHECK: vmla.i32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = load <2 x i32>, <2 x i32>* %C
-	%tmp4 = mul <2 x i32> %tmp2, %tmp3
-	%tmp5 = add <2 x i32> %tmp1, %tmp4
-	ret <2 x i32> %tmp5
-}
-
-define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK-LABEL: vmlaf32:
-;CHECK: vmla.f32
-	%tmp1 = load <2 x float>, <2 x float>* %A
-	%tmp2 = load <2 x float>, <2 x float>* %B
-	%tmp3 = load <2 x float>, <2 x float>* %C
-	%tmp4 = fmul <2 x float> %tmp2, %tmp3
-	%tmp5 = fadd <2 x float> %tmp1, %tmp4
-	ret <2 x float> %tmp5
-}
-
-define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK-LABEL: vmlaQi8:
-;CHECK: vmla.i8
-	%tmp1 = load <16 x i8>, <16 x i8>* %A
-	%tmp2 = load <16 x i8>, <16 x i8>* %B
-	%tmp3 = load <16 x i8>, <16 x i8>* %C
-	%tmp4 = mul <16 x i8> %tmp2, %tmp3
-	%tmp5 = add <16 x i8> %tmp1, %tmp4
-	ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlaQi16:
-;CHECK: vmla.i16
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i16>, <8 x i16>* %B
-	%tmp3 = load <8 x i16>, <8 x i16>* %C
-	%tmp4 = mul <8 x i16> %tmp2, %tmp3
-	%tmp5 = add <8 x i16> %tmp1, %tmp4
-	ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlaQi32:
-;CHECK: vmla.i32
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i32>, <4 x i32>* %B
-	%tmp3 = load <4 x i32>, <4 x i32>* %C
-	%tmp4 = mul <4 x i32> %tmp2, %tmp3
-	%tmp5 = add <4 x i32> %tmp1, %tmp4
-	ret <4 x i32> %tmp5
-}
-
-define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK-LABEL: vmlaQf32:
-;CHECK: vmla.f32
-	%tmp1 = load <4 x float>, <4 x float>* %A
-	%tmp2 = load <4 x float>, <4 x float>* %B
-	%tmp3 = load <4 x float>, <4 x float>* %C
-	%tmp4 = fmul <4 x float> %tmp2, %tmp3
-	%tmp5 = fadd <4 x float> %tmp1, %tmp4
-	ret <4 x float> %tmp5
-}
-
-define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: vmlals8:
-;CHECK: vmlal.s8
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = load <8 x i8>, <8 x i8>* %C
-	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
-	%tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
-	%tmp6 = mul <8 x i16> %tmp4, %tmp5
-	%tmp7 = add <8 x i16> %tmp1, %tmp6
-	ret <8 x i16> %tmp7
-}
-
-define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlals16:
-;CHECK: vmlal.s16
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = load <4 x i16>, <4 x i16>* %C
-	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
-	%tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
-	%tmp6 = mul <4 x i32> %tmp4, %tmp5
-	%tmp7 = add <4 x i32> %tmp1, %tmp6
-	ret <4 x i32> %tmp7
-}
-
-define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlals32:
-;CHECK: vmlal.s32
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = load <2 x i32>, <2 x i32>* %C
-	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
-	%tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
-	%tmp6 = mul <2 x i64> %tmp4, %tmp5
-	%tmp7 = add <2 x i64> %tmp1, %tmp6
-	ret <2 x i64> %tmp7
-}
-
-define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: vmlalu8:
-;CHECK: vmlal.u8
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = load <8 x i8>, <8 x i8>* %C
-	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
-	%tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
-	%tmp6 = mul <8 x i16> %tmp4, %tmp5
-	%tmp7 = add <8 x i16> %tmp1, %tmp6
-	ret <8 x i16> %tmp7
-}
-
-define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlalu16:
-;CHECK: vmlal.u16
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = load <4 x i16>, <4 x i16>* %C
-	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
-	%tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
-	%tmp6 = mul <4 x i32> %tmp4, %tmp5
-	%tmp7 = add <4 x i32> %tmp1, %tmp6
-	ret <4 x i32> %tmp7
-}
-
-define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlalu32:
-;CHECK: vmlal.u32
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = load <2 x i32>, <2 x i32>* %C
-	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
-	%tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
-	%tmp6 = mul <2 x i64> %tmp4, %tmp5
-	%tmp7 = add <2 x i64> %tmp1, %tmp6
-	ret <2 x i64> %tmp7
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vmlai8(<8 x i8> %A, <8 x i8> %B, <8 x i8>  %C) nounwind {
+; CHECK-LABEL: vmlai8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmla.i8 d0, d1, d2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <8 x i8> %B, %C
+  %tmp5 = add <8 x i8> %A, %tmp4
+  ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vmlai16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlai16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmla.i16 d0, d1, d2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <4 x i16> %B, %C
+  %tmp5 = add <4 x i16> %A, %tmp4
+  ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vmlai32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlai32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmla.i32 d0, d1, d2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <2 x i32> %B, %C
+  %tmp5 = add <2 x i32> %A, %tmp4
+  ret <2 x i32> %tmp5
+}
+
+define <2 x float> @vmlaf32(<2 x float> %A, <2 x float> %B, <2 x float> %C) nounwind {
+; CHECK-LABEL: vmlaf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmla.f32 d0, d1, d2
+; CHECK-NEXT:    bx lr
+  %tmp4 = fmul <2 x float> %B, %C
+  %tmp5 = fadd <2 x float> %A, %tmp4
+  ret <2 x float> %tmp5
+}
+
+define <16 x i8> @vmlaQi8(<16 x i8> %A, <16 x i8> %B, <16 x i8>  %C) nounwind {
+; CHECK-LABEL: vmlaQi8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmla.i8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <16 x i8> %B, %C
+  %tmp5 = add <16 x i8> %A, %tmp4
+  ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vmlaQi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) nounwind {
+; CHECK-LABEL: vmlaQi16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmla.i16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <8 x i16> %B, %C
+  %tmp5 = add <8 x i16> %A, %tmp4
+  ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vmlaQi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) nounwind {
+; CHECK-LABEL: vmlaQi32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmla.i32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <4 x i32> %B, %C
+  %tmp5 = add <4 x i32> %A, %tmp4
+  ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vmlaQf32(<4 x float> %A, <4 x float> %B, <4 x float> %C) nounwind {
+; CHECK-LABEL: vmlaQf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmla.f32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+  %tmp4 = fmul <4 x float> %B, %C
+  %tmp5 = fadd <4 x float> %A, %tmp4
+  ret <4 x float> %tmp5
+}
+
+define <8 x i16> @vmlals8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlals8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlal.s8 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = sext <8 x i8> %B to <8 x i16>
+  %tmp5 = sext <8 x i8> %C to <8 x i16>
+  %tmp6 = mul <8 x i16> %tmp4, %tmp5
+  %tmp7 = add <8 x i16> %A, %tmp6
+  ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @vmlals16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlals16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlal.s16 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = sext <4 x i16> %B to <4 x i32>
+  %tmp5 = sext <4 x i16> %C to <4 x i32>
+  %tmp6 = mul <4 x i32> %tmp4, %tmp5
+  %tmp7 = add <4 x i32> %A, %tmp6
+  ret <4 x i32> %tmp7
+}
+
+define <2 x i64> @vmlals32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlals32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlal.s32 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = sext <2 x i32> %B to <2 x i64>
+  %tmp5 = sext <2 x i32> %C to <2 x i64>
+  %tmp6 = mul <2 x i64> %tmp4, %tmp5
+  %tmp7 = add <2 x i64> %A, %tmp6
+  ret <2 x i64> %tmp7
+}
+
+define <8 x i16> @vmlalu8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlalu8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlal.u8 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <8 x i8> %B to <8 x i16>
+  %tmp5 = zext <8 x i8> %C to <8 x i16>
+  %tmp6 = mul <8 x i16> %tmp4, %tmp5
+  %tmp7 = add <8 x i16> %A, %tmp6
+  ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @vmlalu16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlalu16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlal.u16 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <4 x i16> %B to <4 x i32>
+  %tmp5 = zext <4 x i16> %C to <4 x i32>
+  %tmp6 = mul <4 x i32> %tmp4, %tmp5
+  %tmp7 = add <4 x i32> %A, %tmp6
+  ret <4 x i32> %tmp7
+}
+
+define <2 x i64> @vmlalu32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlalu32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlal.u32 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <2 x i32> %B to <2 x i64>
+  %tmp5 = zext <2 x i32> %C to <2 x i64>
+  %tmp6 = mul <2 x i64> %tmp4, %tmp5
+  %tmp7 = add <2 x i64> %A, %tmp6
+  ret <2 x i64> %tmp7
+}
+
+define <8 x i16> @vmlala8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlala8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u8 q8, d3
+; CHECK-NEXT:    vmovl.u8 q9, d2
+; CHECK-NEXT:    vmla.i16 q0, q9, q8
+; CHECK-NEXT:    vbic.i16 q0, #0xff00
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <8 x i8> %B to <8 x i16>
+  %tmp5 = zext <8 x i8> %C to <8 x i16>
+  %tmp6 = mul <8 x i16> %tmp4, %tmp5
+  %tmp7 = add <8 x i16> %A, %tmp6
+  %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @vmlala16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlala16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u16 q8, d3
+; CHECK-NEXT:    vmovl.u16 q9, d2
+; CHECK-NEXT:    vmla.i32 q0, q9, q8
+; CHECK-NEXT:    vmov.i32 q8, #0xffff
+; CHECK-NEXT:    vand q0, q0, q8
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <4 x i16> %B to <4 x i32>
+  %tmp5 = zext <4 x i16> %C to <4 x i32>
+  %tmp6 = mul <4 x i32> %tmp4, %tmp5
+  %tmp7 = add <4 x i32> %A, %tmp6
+  %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @vmlala32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlala32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    vmovl.u32 q8, d3
+; CHECK-NEXT:    vmovl.u32 q9, d2
+; CHECK-NEXT:    vmov.32 r0, d16[0]
+; CHECK-NEXT:    vmov.32 r1, d18[0]
+; CHECK-NEXT:    vmov.32 r12, d16[1]
+; CHECK-NEXT:    vmov.32 r3, d17[0]
+; CHECK-NEXT:    vmov.32 r2, d19[0]
+; CHECK-NEXT:    vmov.32 lr, d17[1]
+; CHECK-NEXT:    vmov.32 r6, d19[1]
+; CHECK-NEXT:    umull r7, r5, r1, r0
+; CHECK-NEXT:    mla r1, r1, r12, r5
+; CHECK-NEXT:    umull r5, r4, r2, r3
+; CHECK-NEXT:    mla r2, r2, lr, r4
+; CHECK-NEXT:    vmov.32 r4, d18[1]
+; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
+; CHECK-NEXT:    mla r2, r6, r3, r2
+; CHECK-NEXT:    vmov.32 d17[0], r5
+; CHECK-NEXT:    vmov.32 d16[0], r7
+; CHECK-NEXT:    vmov.32 d17[1], r2
+; CHECK-NEXT:    mla r0, r4, r0, r1
+; CHECK-NEXT:    vmov.32 d16[1], r0
+; CHECK-NEXT:    vadd.i64 q8, q0, q8
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, pc}
+  %tmp4 = zext <2 x i32> %B to <2 x i64>
+  %tmp5 = zext <2 x i32> %C to <2 x i64>
+  %tmp6 = mul <2 x i64> %tmp4, %tmp5
+  %tmp7 = add <2 x i64> %A, %tmp6
+  %and = and <2 x i64> %tmp7, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_lanes16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlal.s16 q0, d2, d3[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmlal_lanes16
-; CHECK: vmlal.s16 q0, d2, d3[1]
   %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
   %1 = sext <4 x i16> %arg1_int16x4_t to <4 x i32>
   %2 = sext <4 x i16> %0 to <4 x i32>
@@ -179,9 +238,11 @@ entry:
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_lanes32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlal.s32 q0, d2, d3[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmlal_lanes32
-; CHECK: vmlal.s32 q0, d2, d3[1]
   %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = sext <2 x i32> %arg1_int32x2_t to <2 x i64>
   %2 = sext <2 x i32> %0 to <2 x i64>
@@ -191,9 +252,11 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlal_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_laneu16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlal.u16 q0, d2, d3[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmlal_laneu16
-; CHECK: vmlal.u16 q0, d2, d3[1]
   %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
   %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
   %2 = zext <4 x i16> %0 to <4 x i32>
@@ -203,9 +266,11 @@ entry:
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmlal_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_laneu32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlal.u32 q0, d2, d3[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmlal_laneu32
-; CHECK: vmlal.u32 q0, d2, d3[1]
   %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
   %2 = zext <2 x i32> %0 to <2 x i64>
@@ -213,3 +278,63 @@ entry:
   %4 = add <2 x i64> %arg0_uint64x2_t, %3
   ret <2 x i64> %4
 }
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlal_lanea16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_lanea16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vdup.16 d16, d3[1]
+; CHECK-NEXT:    vmovl.u16 q9, d2
+; CHECK-NEXT:    vmovl.u16 q8, d16
+; CHECK-NEXT:    vmla.i32 q0, q9, q8
+; CHECK-NEXT:    vmov.i32 q8, #0xffff
+; CHECK-NEXT:    vand q0, q0, q8
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+  %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
+  %2 = zext <4 x i16> %0 to <4 x i32>
+  %3 = mul <4 x i32> %1, %2
+  %4 = add <4 x i32> %arg0_uint32x4_t, %3
+  %and = and <4 x i32> %4, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlal_lanea32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlal_lanea32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    vdup.32 d16, d3[1]
+; CHECK-NEXT:    vmovl.u32 q9, d2
+; CHECK-NEXT:    vmovl.u32 q8, d16
+; CHECK-NEXT:    vmov.32 r0, d18[0]
+; CHECK-NEXT:    vmov.32 r3, d19[0]
+; CHECK-NEXT:    vmov.32 r1, d16[0]
+; CHECK-NEXT:    vmov.32 r12, d16[1]
+; CHECK-NEXT:    vmov.32 r2, d17[0]
+; CHECK-NEXT:    vmov.32 lr, d17[1]
+; CHECK-NEXT:    vmov.32 r6, d19[1]
+; CHECK-NEXT:    umull r7, r5, r0, r1
+; CHECK-NEXT:    mla r0, r0, r12, r5
+; CHECK-NEXT:    umull r5, r4, r3, r2
+; CHECK-NEXT:    mla r3, r3, lr, r4
+; CHECK-NEXT:    vmov.32 r4, d18[1]
+; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
+; CHECK-NEXT:    mla r2, r6, r2, r3
+; CHECK-NEXT:    vmov.32 d17[0], r5
+; CHECK-NEXT:    vmov.32 d16[0], r7
+; CHECK-NEXT:    vmov.32 d17[1], r2
+; CHECK-NEXT:    mla r0, r4, r1, r0
+; CHECK-NEXT:    vmov.32 d16[1], r0
+; CHECK-NEXT:    vadd.i64 q8, q0, q8
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, pc}
+entry:
+  %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+  %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
+  %2 = zext <2 x i32> %0 to <2 x i64>
+  %3 = mul <2 x i64> %1, %2
+  %4 = add <2 x i64> %arg0_uint64x2_t, %3
+  %and = and <2 x i64> %4, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
diff --git a/llvm/test/CodeGen/ARM/vmls.ll b/llvm/test/CodeGen/ARM/vmls.ll
index d14928147a36c..eef90041b96fc 100644
--- a/llvm/test/CodeGen/ARM/vmls.ll
+++ b/llvm/test/CodeGen/ARM/vmls.ll
@@ -1,175 +1,234 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-
-define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK-LABEL: vmlsi8:
-;CHECK: vmls.i8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = load <8 x i8>, <8 x i8>* %C
-	%tmp4 = mul <8 x i8> %tmp2, %tmp3
-	%tmp5 = sub <8 x i8> %tmp1, %tmp4
-	ret <8 x i8> %tmp5
-}
-
-define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlsi16:
-;CHECK: vmls.i16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = load <4 x i16>, <4 x i16>* %C
-	%tmp4 = mul <4 x i16> %tmp2, %tmp3
-	%tmp5 = sub <4 x i16> %tmp1, %tmp4
-	ret <4 x i16> %tmp5
-}
-
-define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlsi32:
-;CHECK: vmls.i32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = load <2 x i32>, <2 x i32>* %C
-	%tmp4 = mul <2 x i32> %tmp2, %tmp3
-	%tmp5 = sub <2 x i32> %tmp1, %tmp4
-	ret <2 x i32> %tmp5
-}
-
-define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK-LABEL: vmlsf32:
-;CHECK: vmls.f32
-	%tmp1 = load <2 x float>, <2 x float>* %A
-	%tmp2 = load <2 x float>, <2 x float>* %B
-	%tmp3 = load <2 x float>, <2 x float>* %C
-	%tmp4 = fmul <2 x float> %tmp2, %tmp3
-	%tmp5 = fsub <2 x float> %tmp1, %tmp4
-	ret <2 x float> %tmp5
-}
-
-define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK-LABEL: vmlsQi8:
-;CHECK: vmls.i8
-	%tmp1 = load <16 x i8>, <16 x i8>* %A
-	%tmp2 = load <16 x i8>, <16 x i8>* %B
-	%tmp3 = load <16 x i8>, <16 x i8>* %C
-	%tmp4 = mul <16 x i8> %tmp2, %tmp3
-	%tmp5 = sub <16 x i8> %tmp1, %tmp4
-	ret <16 x i8> %tmp5
-}
-
-define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlsQi16:
-;CHECK: vmls.i16
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i16>, <8 x i16>* %B
-	%tmp3 = load <8 x i16>, <8 x i16>* %C
-	%tmp4 = mul <8 x i16> %tmp2, %tmp3
-	%tmp5 = sub <8 x i16> %tmp1, %tmp4
-	ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlsQi32:
-;CHECK: vmls.i32
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i32>, <4 x i32>* %B
-	%tmp3 = load <4 x i32>, <4 x i32>* %C
-	%tmp4 = mul <4 x i32> %tmp2, %tmp3
-	%tmp5 = sub <4 x i32> %tmp1, %tmp4
-	ret <4 x i32> %tmp5
-}
-
-define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK-LABEL: vmlsQf32:
-;CHECK: vmls.f32
-	%tmp1 = load <4 x float>, <4 x float>* %A
-	%tmp2 = load <4 x float>, <4 x float>* %B
-	%tmp3 = load <4 x float>, <4 x float>* %C
-	%tmp4 = fmul <4 x float> %tmp2, %tmp3
-	%tmp5 = fsub <4 x float> %tmp1, %tmp4
-	ret <4 x float> %tmp5
-}
-
-define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: vmlsls8:
-;CHECK: vmlsl.s8
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = load <8 x i8>, <8 x i8>* %C
-	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
-	%tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
-	%tmp6 = mul <8 x i16> %tmp4, %tmp5
-	%tmp7 = sub <8 x i16> %tmp1, %tmp6
-	ret <8 x i16> %tmp7
-}
-
-define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlsls16:
-;CHECK: vmlsl.s16
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = load <4 x i16>, <4 x i16>* %C
-	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
-	%tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
-	%tmp6 = mul <4 x i32> %tmp4, %tmp5
-	%tmp7 = sub <4 x i32> %tmp1, %tmp6
-	ret <4 x i32> %tmp7
-}
-
-define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlsls32:
-;CHECK: vmlsl.s32
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = load <2 x i32>, <2 x i32>* %C
-	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
-	%tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
-	%tmp6 = mul <2 x i64> %tmp4, %tmp5
-	%tmp7 = sub <2 x i64> %tmp1, %tmp6
-	ret <2 x i64> %tmp7
-}
-
-define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK-LABEL: vmlslu8:
-;CHECK: vmlsl.u8
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = load <8 x i8>, <8 x i8>* %C
-	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
-	%tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
-	%tmp6 = mul <8 x i16> %tmp4, %tmp5
-	%tmp7 = sub <8 x i16> %tmp1, %tmp6
-	ret <8 x i16> %tmp7
-}
-
-define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK-LABEL: vmlslu16:
-;CHECK: vmlsl.u16
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = load <4 x i16>, <4 x i16>* %C
-	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
-	%tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
-	%tmp6 = mul <4 x i32> %tmp4, %tmp5
-	%tmp7 = sub <4 x i32> %tmp1, %tmp6
-	ret <4 x i32> %tmp7
-}
-
-define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK-LABEL: vmlslu32:
-;CHECK: vmlsl.u32
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = load <2 x i32>, <2 x i32>* %C
-	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
-	%tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
-	%tmp6 = mul <2 x i64> %tmp4, %tmp5
-	%tmp7 = sub <2 x i64> %tmp1, %tmp6
-	ret <2 x i64> %tmp7
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vmlsi8(<8 x i8> %A, <8 x i8> %B, <8 x i8>  %C) nounwind {
+; CHECK-LABEL: vmlsi8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmls.i8 d0, d1, d2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <8 x i8> %B, %C
+  %tmp5 = sub <8 x i8> %A, %tmp4
+  ret <8 x i8> %tmp5
+}
+
+define <4 x i16> @vmlsi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlsi16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmls.i16 d0, d1, d2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <4 x i16> %B, %C
+  %tmp5 = sub <4 x i16> %A, %tmp4
+  ret <4 x i16> %tmp5
+}
+
+define <2 x i32> @vmlsi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlsi32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmls.i32 d0, d1, d2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <2 x i32> %B, %C
+  %tmp5 = sub <2 x i32> %A, %tmp4
+  ret <2 x i32> %tmp5
+}
+
+define <2 x float> @vmlsf32(<2 x float> %A, <2 x float> %B, <2 x float> %C) nounwind {
+; CHECK-LABEL: vmlsf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmls.f32 d0, d1, d2
+; CHECK-NEXT:    bx lr
+  %tmp4 = fmul <2 x float> %B, %C
+  %tmp5 = fsub <2 x float> %A, %tmp4
+  ret <2 x float> %tmp5
+}
+
+define <16 x i8> @vmlsQi8(<16 x i8> %A, <16 x i8> %B, <16 x i8>  %C) nounwind {
+; CHECK-LABEL: vmlsQi8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmls.i8 q0, q1, q2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <16 x i8> %B, %C
+  %tmp5 = sub <16 x i8> %A, %tmp4
+  ret <16 x i8> %tmp5
+}
+
+define <8 x i16> @vmlsQi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) nounwind {
+; CHECK-LABEL: vmlsQi16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmls.i16 q0, q1, q2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <8 x i16> %B, %C
+  %tmp5 = sub <8 x i16> %A, %tmp4
+  ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vmlsQi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) nounwind {
+; CHECK-LABEL: vmlsQi32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmls.i32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+  %tmp4 = mul <4 x i32> %B, %C
+  %tmp5 = sub <4 x i32> %A, %tmp4
+  ret <4 x i32> %tmp5
+}
+
+define <4 x float> @vmlsQf32(<4 x float> %A, <4 x float> %B, <4 x float> %C) nounwind {
+; CHECK-LABEL: vmlsQf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmls.f32 q0, q1, q2
+; CHECK-NEXT:    bx lr
+  %tmp4 = fmul <4 x float> %B, %C
+  %tmp5 = fsub <4 x float> %A, %tmp4
+  ret <4 x float> %tmp5
+}
+
+define <8 x i16> @vmlsls8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlsls8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlsl.s8 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = sext <8 x i8> %B to <8 x i16>
+  %tmp5 = sext <8 x i8> %C to <8 x i16>
+  %tmp6 = mul <8 x i16> %tmp4, %tmp5
+  %tmp7 = sub <8 x i16> %A, %tmp6
+  ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @vmlsls16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlsls16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlsl.s16 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = sext <4 x i16> %B to <4 x i32>
+  %tmp5 = sext <4 x i16> %C to <4 x i32>
+  %tmp6 = mul <4 x i32> %tmp4, %tmp5
+  %tmp7 = sub <4 x i32> %A, %tmp6
+  ret <4 x i32> %tmp7
+}
+
+define <2 x i64> @vmlsls32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlsls32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlsl.s32 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = sext <2 x i32> %B to <2 x i64>
+  %tmp5 = sext <2 x i32> %C to <2 x i64>
+  %tmp6 = mul <2 x i64> %tmp4, %tmp5
+  %tmp7 = sub <2 x i64> %A, %tmp6
+  ret <2 x i64> %tmp7
+}
+
+define <8 x i16> @vmlslu8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlslu8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlsl.u8 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <8 x i8> %B to <8 x i16>
+  %tmp5 = zext <8 x i8> %C to <8 x i16>
+  %tmp6 = mul <8 x i16> %tmp4, %tmp5
+  %tmp7 = sub <8 x i16> %A, %tmp6
+  ret <8 x i16> %tmp7
+}
+
+define <4 x i32> @vmlslu16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlslu16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlsl.u16 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <4 x i16> %B to <4 x i32>
+  %tmp5 = zext <4 x i16> %C to <4 x i32>
+  %tmp6 = mul <4 x i32> %tmp4, %tmp5
+  %tmp7 = sub <4 x i32> %A, %tmp6
+  ret <4 x i32> %tmp7
+}
+
+define <2 x i64> @vmlslu32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlslu32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmlsl.u32 q0, d2, d3
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <2 x i32> %B to <2 x i64>
+  %tmp5 = zext <2 x i32> %C to <2 x i64>
+  %tmp6 = mul <2 x i64> %tmp4, %tmp5
+  %tmp7 = sub <2 x i64> %A, %tmp6
+  ret <2 x i64> %tmp7
+}
+
+define <8 x i16> @vmlsla8(<8 x i16> %A, <8 x i8> %B, <8 x i8> %C) nounwind {
+; CHECK-LABEL: vmlsla8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u8 q8, d3
+; CHECK-NEXT:    vmovl.u8 q9, d2
+; CHECK-NEXT:    vmls.i16 q0, q9, q8
+; CHECK-NEXT:    vbic.i16 q0, #0xff00
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <8 x i8> %B to <8 x i16>
+  %tmp5 = zext <8 x i8> %C to <8 x i16>
+  %tmp6 = mul <8 x i16> %tmp4, %tmp5
+  %tmp7 = sub <8 x i16> %A, %tmp6
+  %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @vmlsla16(<4 x i32> %A, <4 x i16> %B, <4 x i16> %C) nounwind {
+; CHECK-LABEL: vmlsla16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u16 q8, d3
+; CHECK-NEXT:    vmovl.u16 q9, d2
+; CHECK-NEXT:    vmls.i32 q0, q9, q8
+; CHECK-NEXT:    vmov.i32 q8, #0xffff
+; CHECK-NEXT:    vand q0, q0, q8
+; CHECK-NEXT:    bx lr
+  %tmp4 = zext <4 x i16> %B to <4 x i32>
+  %tmp5 = zext <4 x i16> %C to <4 x i32>
+  %tmp6 = mul <4 x i32> %tmp4, %tmp5
+  %tmp7 = sub <4 x i32> %A, %tmp6
+  %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @vmlsla32(<2 x i64> %A, <2 x i32> %B, <2 x i32> %C) nounwind {
+; CHECK-LABEL: vmlsla32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    vmovl.u32 q8, d3
+; CHECK-NEXT:    vmovl.u32 q9, d2
+; CHECK-NEXT:    vmov.32 r0, d16[0]
+; CHECK-NEXT:    vmov.32 r1, d18[0]
+; CHECK-NEXT:    vmov.32 r12, d16[1]
+; CHECK-NEXT:    vmov.32 r3, d17[0]
+; CHECK-NEXT:    vmov.32 r2, d19[0]
+; CHECK-NEXT:    vmov.32 lr, d17[1]
+; CHECK-NEXT:    vmov.32 r6, d19[1]
+; CHECK-NEXT:    umull r7, r5, r1, r0
+; CHECK-NEXT:    mla r1, r1, r12, r5
+; CHECK-NEXT:    umull r5, r4, r2, r3
+; CHECK-NEXT:    mla r2, r2, lr, r4
+; CHECK-NEXT:    vmov.32 r4, d18[1]
+; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
+; CHECK-NEXT:    mla r2, r6, r3, r2
+; CHECK-NEXT:    vmov.32 d17[0], r5
+; CHECK-NEXT:    vmov.32 d16[0], r7
+; CHECK-NEXT:    vmov.32 d17[1], r2
+; CHECK-NEXT:    mla r0, r4, r0, r1
+; CHECK-NEXT:    vmov.32 d16[1], r0
+; CHECK-NEXT:    vsub.i64 q8, q0, q8
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, pc}
+  %tmp4 = zext <2 x i32> %B to <2 x i64>
+  %tmp5 = zext <2 x i32> %C to <2 x i64>
+  %tmp6 = mul <2 x i64> %tmp4, %tmp5
+  %tmp7 = sub <2 x i64> %A, %tmp6
+  %and = and <2 x i64> %tmp7, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_lanes16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlsl.s16 q0, d2, d3[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmlsl_lanes16
-; CHECK: vmlsl.s16 q0, d2, d3[1]
   %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
   %1 = sext <4 x i16> %arg1_int16x4_t to <4 x i32>
   %2 = sext <4 x i16> %0 to <4 x i32>
@@ -179,9 +238,11 @@ entry:
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_lanes32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlsl.s32 q0, d2, d3[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmlsl_lanes32
-; CHECK: vmlsl.s32 q0, d2, d3[1]
   %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = sext <2 x i32> %arg1_int32x2_t to <2 x i64>
   %2 = sext <2 x i32> %0 to <2 x i64>
@@ -191,9 +252,11 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_laneu16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_laneu16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlsl.u16 q0, d2, d3[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmlsl_laneu16
-; CHECK: vmlsl.u16 q0, d2, d3[1]
   %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
   %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
   %2 = zext <4 x i16> %0 to <4 x i32>
@@ -203,9 +266,11 @@ entry:
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_laneu32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_laneu32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmlsl.u32 q0, d2, d3[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmlsl_laneu32
-; CHECK: vmlsl.u32 q0, d2, d3[1]
   %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
   %2 = zext <2 x i32> %0 to <2 x i64>
@@ -213,3 +278,63 @@ entry:
   %4 = sub <2 x i64> %arg0_uint64x2_t, %3
   ret <2 x i64> %4
 }
+
+define arm_aapcs_vfpcc <4 x i32> @test_vmlsl_lanea16(<4 x i32> %arg0_uint32x4_t, <4 x i16> %arg1_uint16x4_t, <4 x i16> %arg2_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_lanea16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vdup.16 d16, d3[1]
+; CHECK-NEXT:    vmovl.u16 q9, d2
+; CHECK-NEXT:    vmovl.u16 q8, d16
+; CHECK-NEXT:    vmls.i32 q0, q9, q8
+; CHECK-NEXT:    vmov.i32 q8, #0xffff
+; CHECK-NEXT:    vand q0, q0, q8
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = shufflevector <4 x i16> %arg2_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+  %1 = zext <4 x i16> %arg1_uint16x4_t to <4 x i32>
+  %2 = zext <4 x i16> %0 to <4 x i32>
+  %3 = mul <4 x i32> %1, %2
+  %4 = sub <4 x i32> %arg0_uint32x4_t, %3
+  %and = and <4 x i32> %4, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmlsl_lanea32(<2 x i64> %arg0_uint64x2_t, <2 x i32> %arg1_uint32x2_t, <2 x i32> %arg2_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmlsl_lanea32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    vdup.32 d16, d3[1]
+; CHECK-NEXT:    vmovl.u32 q9, d2
+; CHECK-NEXT:    vmovl.u32 q8, d16
+; CHECK-NEXT:    vmov.32 r0, d18[0]
+; CHECK-NEXT:    vmov.32 r3, d19[0]
+; CHECK-NEXT:    vmov.32 r1, d16[0]
+; CHECK-NEXT:    vmov.32 r12, d16[1]
+; CHECK-NEXT:    vmov.32 r2, d17[0]
+; CHECK-NEXT:    vmov.32 lr, d17[1]
+; CHECK-NEXT:    vmov.32 r6, d19[1]
+; CHECK-NEXT:    umull r7, r5, r0, r1
+; CHECK-NEXT:    mla r0, r0, r12, r5
+; CHECK-NEXT:    umull r5, r4, r3, r2
+; CHECK-NEXT:    mla r3, r3, lr, r4
+; CHECK-NEXT:    vmov.32 r4, d18[1]
+; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
+; CHECK-NEXT:    mla r2, r6, r2, r3
+; CHECK-NEXT:    vmov.32 d17[0], r5
+; CHECK-NEXT:    vmov.32 d16[0], r7
+; CHECK-NEXT:    vmov.32 d17[1], r2
+; CHECK-NEXT:    mla r0, r4, r1, r0
+; CHECK-NEXT:    vmov.32 d16[1], r0
+; CHECK-NEXT:    vsub.i64 q8, q0, q8
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, pc}
+entry:
+  %0 = shufflevector <2 x i32> %arg2_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+  %1 = zext <2 x i32> %arg1_uint32x2_t to <2 x i64>
+  %2 = zext <2 x i32> %0 to <2 x i64>
+  %3 = mul <2 x i64> %1, %2
+  %4 = sub <2 x i64> %arg0_uint64x2_t, %3
+  %and = and <2 x i64> %4, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
diff --git a/llvm/test/CodeGen/ARM/vmul.ll b/llvm/test/CodeGen/ARM/vmul.ll
index e8cf8d9b27b6f..c57ace2a6c673 100644
--- a/llvm/test/CodeGen/ARM/vmul.ll
+++ b/llvm/test/CodeGen/ARM/vmul.ll
@@ -1,92 +1,93 @@
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
-
-define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmuli8:
-;CHECK: vmul.i8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = mul <8 x i8> %tmp1, %tmp2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vmuli8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmuli8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.i8 d0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = mul <8 x i8> %A, %B
 	ret <8 x i8> %tmp3
 }
 
-define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmuli16:
-;CHECK: vmul.i16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = mul <4 x i16> %tmp1, %tmp2
+define <4 x i16> @vmuli16(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmuli16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.i16 d0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = mul <4 x i16> %A, %B
 	ret <4 x i16> %tmp3
 }
 
-define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmuli32:
-;CHECK: vmul.i32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = mul <2 x i32> %tmp1, %tmp2
+define <2 x i32> @vmuli32(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmuli32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.i32 d0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = mul <2 x i32> %A, %B
 	ret <2 x i32> %tmp3
 }
 
-define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vmulf32:
-;CHECK: vmul.f32
-	%tmp1 = load <2 x float>, <2 x float>* %A
-	%tmp2 = load <2 x float>, <2 x float>* %B
-	%tmp3 = fmul <2 x float> %tmp1, %tmp2
+define <2 x float> @vmulf32(<2 x float> %A, <2 x float> %B) nounwind {
+; CHECK-LABEL: vmulf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.f32 d0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = fmul <2 x float> %A, %B
 	ret <2 x float> %tmp3
 }
 
-define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulp8:
-;CHECK: vmul.p8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
+define <8 x i8> @vmulp8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmulp8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.p8 d0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = call <8 x i8> @llvm.arm.neon.vmulp.v8i8(<8 x i8> %A, <8 x i8> %B)
 	ret <8 x i8> %tmp3
 }
 
-define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulQi8:
-;CHECK: vmul.i8
-	%tmp1 = load <16 x i8>, <16 x i8>* %A
-	%tmp2 = load <16 x i8>, <16 x i8>* %B
-	%tmp3 = mul <16 x i8> %tmp1, %tmp2
+define <16 x i8> @vmulQi8(<16 x i8> %A, <16 x i8> %B) nounwind {
+; CHECK-LABEL: vmulQi8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.i8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+	%tmp3 = mul <16 x i8> %A, %B
 	ret <16 x i8> %tmp3
 }
 
-define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vmulQi16:
-;CHECK: vmul.i16
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i16>, <8 x i16>* %B
-	%tmp3 = mul <8 x i16> %tmp1, %tmp2
+define <8 x i16> @vmulQi16(<8 x i16> %A, <8 x i16> %B) nounwind {
+; CHECK-LABEL: vmulQi16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.i16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+	%tmp3 = mul <8 x i16> %A, %B
 	ret <8 x i16> %tmp3
 }
 
-define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vmulQi32:
-;CHECK: vmul.i32
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i32>, <4 x i32>* %B
-	%tmp3 = mul <4 x i32> %tmp1, %tmp2
+define <4 x i32> @vmulQi32(<4 x i32> %A, <4 x i32> %B) nounwind {
+; CHECK-LABEL: vmulQi32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.i32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+	%tmp3 = mul <4 x i32> %A, %B
 	ret <4 x i32> %tmp3
 }
 
-define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vmulQf32:
-;CHECK: vmul.f32
-	%tmp1 = load <4 x float>, <4 x float>* %A
-	%tmp2 = load <4 x float>, <4 x float>* %B
-	%tmp3 = fmul <4 x float> %tmp1, %tmp2
+define <4 x float> @vmulQf32(<4 x float> %A, <4 x float> %B) nounwind {
+; CHECK-LABEL: vmulQf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.f32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+	%tmp3 = fmul <4 x float> %A, %B
 	ret <4 x float> %tmp3
 }
 
-define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulQp8:
-;CHECK: vmul.p8
-	%tmp1 = load <16 x i8>, <16 x i8>* %A
-	%tmp2 = load <16 x i8>, <16 x i8>* %B
-	%tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
+define <16 x i8> @vmulQp8(<16 x i8> %A, <16 x i8> %B) nounwind {
+; CHECK-LABEL: vmulQp8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmul.p8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+	%tmp3 = call <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8> %A, <16 x i8> %B)
 	ret <16 x i8> %tmp3
 }
 
@@ -94,192 +95,275 @@ declare <8 x i8>  @llvm.arm.neon.vmulp.v8i8(<8 x i8>, <8 x i8>) nounwind readnon
 declare <16 x i8>  @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
 
 define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
-entry:
 ; CHECK-LABEL: test_vmul_lanef32:
-; CHECK: vmul.f32 d0, d0, d1[0]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmul.f32 d0, d0, d1[0]
+; CHECK-NEXT:    bx lr
+entry:
   %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]
   %1 = fmul <2 x float> %0, %arg0_float32x2_t     ; <<2 x float>> [#uses=1]
   ret <2 x float> %1
 }
 
 define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
-entry:
 ; CHECK-LABEL: test_vmul_lanes16:
-; CHECK: vmul.i16 d0, d0, d1[1]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmul.i16 d0, d0, d1[1]
+; CHECK-NEXT:    bx lr
+entry:
   %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$
   %1 = mul <4 x i16> %0, %arg0_int16x4_t          ; <<4 x i16>> [#uses=1]
   ret <4 x i16> %1
 }
 
 define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
-entry:
 ; CHECK-LABEL: test_vmul_lanes32:
-; CHECK: vmul.i32 d0, d0, d1[1]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmul.i32 d0, d0, d1[1]
+; CHECK-NEXT:    bx lr
+entry:
   %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = mul <2 x i32> %0, %arg0_int32x2_t          ; <<2 x i32>> [#uses=1]
   ret <2 x i32> %1
 }
 
 define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
-entry:
 ; CHECK-LABEL: test_vmulQ_lanef32:
-; CHECK: vmul.f32 q0, q0, d2[1]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d2 killed $d2 def $q1
+; CHECK-NEXT:    vmul.f32 q0, q0, d2[1]
+; CHECK-NEXT:    bx lr
+entry:
   %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$
   %1 = fmul <4 x float> %0, %arg0_float32x4_t     ; <<4 x float>> [#uses=1]
   ret <4 x float> %1
 }
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
-entry:
 ; CHECK-LABEL: test_vmulQ_lanes16:
-; CHECK: vmul.i16 q0, q0, d2[1]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d2 killed $d2 def $q1
+; CHECK-NEXT:    vmul.i16 q0, q0, d2[1]
+; CHECK-NEXT:    bx lr
+entry:
   %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   %1 = mul <8 x i16> %0, %arg0_int16x8_t          ; <<8 x i16>> [#uses=1]
   ret <8 x i16> %1
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
-entry:
 ; CHECK-LABEL: test_vmulQ_lanes32:
-; CHECK: vmul.i32 q0, q0, d2[1]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    @ kill: def $d2 killed $d2 def $q1
+; CHECK-NEXT:    vmul.i32 q0, q0, d2[1]
+; CHECK-NEXT:    bx lr
+entry:
   %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$
   %1 = mul <4 x i32> %0, %arg0_int32x4_t          ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %1
 }
 
-define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulls8:
-;CHECK: vmull.s8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
-	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
+define <8 x i16> @vmulls8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmulls8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.s8 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = sext <8 x i8> %A to <8 x i16>
+	%tmp4 = sext <8 x i8> %B to <8 x i16>
 	%tmp5 = mul <8 x i16> %tmp3, %tmp4
 	ret <8 x i16> %tmp5
 }
 
-define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmulls8_int:
-;CHECK: vmull.s8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+define <8 x i16> @vmulls8_int(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmulls8_int:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.s8 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8> %A, <8 x i8> %B)
 	ret <8 x i16> %tmp3
 }
 
-define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmulls16:
-;CHECK: vmull.s16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
-	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
+define <4 x i32> @vmulls16(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmulls16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.s16 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = sext <4 x i16> %A to <4 x i32>
+	%tmp4 = sext <4 x i16> %B to <4 x i32>
 	%tmp5 = mul <4 x i32> %tmp3, %tmp4
 	ret <4 x i32> %tmp5
 }
 
-define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmulls16_int:
-;CHECK: vmull.s16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+define <4 x i32> @vmulls16_int(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmulls16_int:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.s16 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %A, <4 x i16> %B)
 	ret <4 x i32> %tmp3
 }
 
-define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmulls32:
-;CHECK: vmull.s32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
-	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
+define <2 x i64> @vmulls32(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmulls32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.s32 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = sext <2 x i32> %A to <2 x i64>
+	%tmp4 = sext <2 x i32> %B to <2 x i64>
 	%tmp5 = mul <2 x i64> %tmp3, %tmp4
 	ret <2 x i64> %tmp5
 }
 
-define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmulls32_int:
-;CHECK: vmull.s32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+define <2 x i64> @vmulls32_int(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmulls32_int:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.s32 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %A, <2 x i32> %B)
 	ret <2 x i64> %tmp3
 }
 
-define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmullu8:
-;CHECK: vmull.u8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
-	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
+define <8 x i16> @vmullu8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmullu8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.u8 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = zext <8 x i8> %A to <8 x i16>
+	%tmp4 = zext <8 x i8> %B to <8 x i16>
 	%tmp5 = mul <8 x i16> %tmp3, %tmp4
 	ret <8 x i16> %tmp5
 }
 
-define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmullu8_int:
-;CHECK: vmull.u8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+define <8 x i16> @vmullu8_int(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmullu8_int:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.u8 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %A, <8 x i8> %B)
 	ret <8 x i16> %tmp3
 }
 
-define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmullu16:
-;CHECK: vmull.u16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
-	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
+define <4 x i32> @vmullu16(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmullu16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.u16 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = zext <4 x i16> %A to <4 x i32>
+	%tmp4 = zext <4 x i16> %B to <4 x i32>
 	%tmp5 = mul <4 x i32> %tmp3, %tmp4
 	ret <4 x i32> %tmp5
 }
 
-define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vmullu16_int:
-;CHECK: vmull.u16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %tmp1, <4 x i16> %tmp2)
+define <4 x i32> @vmullu16_int(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmullu16_int:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.u16 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %A, <4 x i16> %B)
 	ret <4 x i32> %tmp3
 }
 
-define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmullu32:
-;CHECK: vmull.u32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
-	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
+define <2 x i64> @vmullu32(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmullu32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.u32 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = zext <2 x i32> %A to <2 x i64>
+	%tmp4 = zext <2 x i32> %B to <2 x i64>
 	%tmp5 = mul <2 x i64> %tmp3, %tmp4
 	ret <2 x i64> %tmp5
 }
 
-define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vmullu32_int:
-;CHECK: vmull.u32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %tmp1, <2 x i32> %tmp2)
+define <2 x i64> @vmullu32_int(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmullu32_int:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.u32 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %A, <2 x i32> %B)
 	ret <2 x i64> %tmp3
 }
 
-define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vmullp8:
-;CHECK: vmull.p8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %tmp1, <8 x i8> %tmp2)
+define <8 x i16> @vmulla8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmulla8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u8 q8, d1
+; CHECK-NEXT:    vmovl.u8 q9, d0
+; CHECK-NEXT:    vmul.i16 q0, q9, q8
+; CHECK-NEXT:    vbic.i16 q0, #0xff00
+; CHECK-NEXT:    bx lr
+	%tmp3 = zext <8 x i8> %A to <8 x i16>
+	%tmp4 = zext <8 x i8> %B to <8 x i16>
+	%tmp5 = mul <8 x i16> %tmp3, %tmp4
+  %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+	ret <8 x i16> %and
+}
+
+define <4 x i32> @vmulla16(<4 x i16> %A, <4 x i16> %B) nounwind {
+; CHECK-LABEL: vmulla16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u16 q8, d1
+; CHECK-NEXT:    vmovl.u16 q9, d0
+; CHECK-NEXT:    vmul.i32 q8, q9, q8
+; CHECK-NEXT:    vmov.i32 q9, #0xffff
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    bx lr
+	%tmp3 = zext <4 x i16> %A to <4 x i32>
+	%tmp4 = zext <4 x i16> %B to <4 x i32>
+	%tmp5 = mul <4 x i32> %tmp3, %tmp4
+  %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
+	ret <4 x i32> %and
+}
+
+define <2 x i64> @vmulla32(<2 x i32> %A, <2 x i32> %B) nounwind {
+; CHECK-LABEL: vmulla32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    vmovl.u32 q8, d1
+; CHECK-NEXT:    vmovl.u32 q9, d0
+; CHECK-NEXT:    vmov.32 r0, d16[0]
+; CHECK-NEXT:    vmov.32 r1, d18[0]
+; CHECK-NEXT:    vmov.32 r12, d16[1]
+; CHECK-NEXT:    vmov.32 r3, d17[0]
+; CHECK-NEXT:    vmov.32 r2, d19[0]
+; CHECK-NEXT:    vmov.32 lr, d17[1]
+; CHECK-NEXT:    vmov.32 r6, d19[1]
+; CHECK-NEXT:    umull r7, r5, r1, r0
+; CHECK-NEXT:    mla r1, r1, r12, r5
+; CHECK-NEXT:    umull r5, r4, r2, r3
+; CHECK-NEXT:    mla r2, r2, lr, r4
+; CHECK-NEXT:    vmov.32 r4, d18[1]
+; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
+; CHECK-NEXT:    mla r2, r6, r3, r2
+; CHECK-NEXT:    vmov.32 d17[0], r5
+; CHECK-NEXT:    vmov.32 d16[0], r7
+; CHECK-NEXT:    vmov.32 d17[1], r2
+; CHECK-NEXT:    mla r0, r4, r0, r1
+; CHECK-NEXT:    vmov.32 d16[1], r0
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, pc}
+	%tmp3 = zext <2 x i32> %A to <2 x i64>
+	%tmp4 = zext <2 x i32> %B to <2 x i64>
+	%tmp5 = mul <2 x i64> %tmp3, %tmp4
+  %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
+	ret <2 x i64> %and
+}
+
+define <8 x i16> @vmullp8(<8 x i8> %A, <8 x i8> %B) nounwind {
+; CHECK-LABEL: vmullp8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmull.p8 q0, d0, d1
+; CHECK-NEXT:    bx lr
+	%tmp3 = call <8 x i16> @llvm.arm.neon.vmullp.v8i16(<8 x i8> %A, <8 x i8> %B)
 	ret <8 x i16> %tmp3
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanes16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmull.s16 q0, d0, d1[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmull_lanes16
-; CHECK: vmull.s16 q0, d0, d1[1]
   %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
   %1 = sext <4 x i16> %arg0_int16x4_t to <4 x i32>
   %2 = sext <4 x i16> %0 to <4 x i32>
@@ -288,18 +372,22 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanes16_int(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanes16_int:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmull.s16 q0, d0, d1[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmull_lanes16_int
-; CHECK: vmull.s16 q0, d0, d1[1]
   %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
   %1 = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %arg0_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %1
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanes32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmull.s32 q0, d0, d1[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmull_lanes32
-; CHECK: vmull.s32 q0, d0, d1[1]
   %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = sext <2 x i32> %arg0_int32x2_t to <2 x i64>
   %2 = sext <2 x i32> %0 to <2 x i64>
@@ -308,18 +396,22 @@ entry:
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanes32_int(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanes32_int:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmull.s32 q0, d0, d1[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmull_lanes32_int
-; CHECK: vmull.s32 q0, d0, d1[1]
   %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = tail call <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32> %arg0_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %1
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_laneu16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmull.u16 q0, d0, d1[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmull_laneu16
-; CHECK: vmull.u16 q0, d0, d1[1]
   %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
   %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32>
   %2 = zext <4 x i16> %0 to <4 x i32>
@@ -328,18 +420,22 @@ entry:
 }
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmull_laneu16_int(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_laneu16_int:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmull.u16 q0, d0, d1[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmull_laneu16_int
-; CHECK: vmull.u16 q0, d0, d1[1]
   %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
   %1 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %arg0_uint16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1]
   ret <4 x i32> %1
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_laneu32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmull.u32 q0, d0, d1[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmull_laneu32
-; CHECK: vmull.u32 q0, d0, d1[1]
   %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64>
   %2 = zext <2 x i32> %0 to <2 x i64>
@@ -348,14 +444,73 @@ entry:
 }
 
 define arm_aapcs_vfpcc <2 x i64> @test_vmull_laneu32_int(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_laneu32_int:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmull.u32 q0, d0, d1[1]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: test_vmull_laneu32_int
-; CHECK: vmull.u32 q0, d0, d1[1]
   %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = tail call <2 x i64> @llvm.arm.neon.vmullu.v2i64(<2 x i32> %arg0_uint32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1]
   ret <2 x i64> %1
 }
 
+define arm_aapcs_vfpcc <4 x i32> @test_vmull_lanea16(<4 x i16> %arg0_uint16x4_t, <4 x i16> %arg1_uint16x4_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanea16:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vdup.16 d16, d1[1]
+; CHECK-NEXT:    vmovl.u16 q9, d0
+; CHECK-NEXT:    vmovl.u16 q8, d16
+; CHECK-NEXT:    vmul.i32 q8, q9, q8
+; CHECK-NEXT:    vmov.i32 q9, #0xffff
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    bx lr
+entry:
+  %0 = shufflevector <4 x i16> %arg1_uint16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1]
+  %1 = zext <4 x i16> %arg0_uint16x4_t to <4 x i32>
+  %2 = zext <4 x i16> %0 to <4 x i32>
+  %3 = mul <4 x i32> %1, %2
+  %and = and <4 x i32> %3, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define arm_aapcs_vfpcc <2 x i64> @test_vmull_lanea32(<2 x i32> %arg0_uint32x2_t, <2 x i32> %arg1_uint32x2_t) nounwind readnone {
+; CHECK-LABEL: test_vmull_lanea32:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT:    vdup.32 d16, d1[1]
+; CHECK-NEXT:    vmovl.u32 q9, d0
+; CHECK-NEXT:    vmovl.u32 q8, d16
+; CHECK-NEXT:    vmov.32 r0, d18[0]
+; CHECK-NEXT:    vmov.32 r3, d19[0]
+; CHECK-NEXT:    vmov.32 r1, d16[0]
+; CHECK-NEXT:    vmov.32 r12, d16[1]
+; CHECK-NEXT:    vmov.32 r2, d17[0]
+; CHECK-NEXT:    vmov.32 lr, d17[1]
+; CHECK-NEXT:    vmov.32 r6, d19[1]
+; CHECK-NEXT:    umull r7, r5, r0, r1
+; CHECK-NEXT:    mla r0, r0, r12, r5
+; CHECK-NEXT:    umull r5, r4, r3, r2
+; CHECK-NEXT:    mla r3, r3, lr, r4
+; CHECK-NEXT:    vmov.32 r4, d18[1]
+; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
+; CHECK-NEXT:    mla r2, r6, r2, r3
+; CHECK-NEXT:    vmov.32 d17[0], r5
+; CHECK-NEXT:    vmov.32 d16[0], r7
+; CHECK-NEXT:    vmov.32 d17[1], r2
+; CHECK-NEXT:    mla r0, r4, r1, r0
+; CHECK-NEXT:    vmov.32 d16[1], r0
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    pop {r4, r5, r6, r7, r11, pc}
+entry:
+  %0 = shufflevector <2 x i32> %arg1_uint32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
+  %1 = zext <2 x i32> %arg0_uint32x2_t to <2 x i64>
+  %2 = zext <2 x i32> %0 to <2 x i64>
+  %3 = mul <2 x i64> %1, %2
+  %and = and <2 x i64> %3, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
 declare <8 x i16> @llvm.arm.neon.vmulls.v8i16(<8 x i8>, <8 x i8>) nounwind readnone
 declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
 declare <2 x i64> @llvm.arm.neon.vmulls.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
@@ -371,16 +526,22 @@ declare <8 x i16>  @llvm.arm.neon.vmullp.v8i16(<8 x i8>, <8 x i8>) nounwind read
 ; VMULL needs to recognize BUILD_VECTORs with sign/zero-extended elements.
 
 define <8 x i16> @vmull_extvec_s8(<8 x i8> %arg) nounwind {
-; CHECK: vmull_extvec_s8
-; CHECK: vmull.s8
+; CHECK-LABEL: vmull_extvec_s8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmov.i8 d16, #0xf4
+; CHECK-NEXT:    vmull.s8 q0, d0, d16
+; CHECK-NEXT:    bx lr
   %tmp3 = sext <8 x i8> %arg to <8 x i16>
   %tmp4 = mul <8 x i16> %tmp3, <i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12>
   ret <8 x i16> %tmp4
 }
 
 define <8 x i16> @vmull_extvec_u8(<8 x i8> %arg) nounwind {
-; CHECK: vmull_extvec_u8
-; CHECK: vmull.u8
+; CHECK-LABEL: vmull_extvec_u8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmov.i8 d16, #0xc
+; CHECK-NEXT:    vmull.u8 q0, d0, d16
+; CHECK-NEXT:    bx lr
   %tmp3 = zext <8 x i8> %arg to <8 x i16>
   %tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
   ret <8 x i16> %tmp4
@@ -388,9 +549,24 @@ define <8 x i16> @vmull_extvec_u8(<8 x i8> %arg) nounwind {
 
 define <8 x i16> @vmull_noextvec_s8(<8 x i8> %arg) nounwind {
 ; Do not use VMULL if the BUILD_VECTOR element values are too big.
-; CHECK: vmull_noextvec_s8
-; CHECK: vmovl.s8
-; CHECK: vmul.i16
+; CHECK-LABEL: vmull_noextvec_s8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.s8 q8, d0
+; CHECK-NEXT:    adr r0, .LCPI44_0
+; CHECK-NEXT:    vld1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT:    vmul.i16 q0, q8, q9
+; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI44_0:
+; CHECK-NEXT:    .short 64537 @ 0xfc19
+; CHECK-NEXT:    .short 64537 @ 0xfc19
+; CHECK-NEXT:    .short 64537 @ 0xfc19
+; CHECK-NEXT:    .short 64537 @ 0xfc19
+; CHECK-NEXT:    .short 64537 @ 0xfc19
+; CHECK-NEXT:    .short 64537 @ 0xfc19
+; CHECK-NEXT:    .short 64537 @ 0xfc19
+; CHECK-NEXT:    .short 64537 @ 0xfc19
   %tmp3 = sext <8 x i8> %arg to <8 x i16>
   %tmp4 = mul <8 x i16> %tmp3, <i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999>
   ret <8 x i16> %tmp4
@@ -398,41 +574,85 @@ define <8 x i16> @vmull_noextvec_s8(<8 x i8> %arg) nounwind {
 
 define <8 x i16> @vmull_noextvec_u8(<8 x i8> %arg) nounwind {
 ; Do not use VMULL if the BUILD_VECTOR element values are too big.
-; CHECK: vmull_noextvec_u8
-; CHECK: vmovl.u8
-; CHECK: vmul.i16
+; CHECK-LABEL: vmull_noextvec_u8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u8 q8, d0
+; CHECK-NEXT:    adr r0, .LCPI45_0
+; CHECK-NEXT:    vld1.64 {d18, d19}, [r0:128]
+; CHECK-NEXT:    vmul.i16 q0, q8, q9
+; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI45_0:
+; CHECK-NEXT:    .short 999 @ 0x3e7
+; CHECK-NEXT:    .short 999 @ 0x3e7
+; CHECK-NEXT:    .short 999 @ 0x3e7
+; CHECK-NEXT:    .short 999 @ 0x3e7
+; CHECK-NEXT:    .short 999 @ 0x3e7
+; CHECK-NEXT:    .short 999 @ 0x3e7
+; CHECK-NEXT:    .short 999 @ 0x3e7
+; CHECK-NEXT:    .short 999 @ 0x3e7
   %tmp3 = zext <8 x i8> %arg to <8 x i16>
   %tmp4 = mul <8 x i16> %tmp3, <i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999>
   ret <8 x i16> %tmp4
 }
 
 define <4 x i32> @vmull_extvec_s16(<4 x i16> %arg) nounwind {
-; CHECK: vmull_extvec_s16
-; CHECK: vmull.s16
+; CHECK-LABEL: vmull_extvec_s16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmvn.i16 d16, #0xb
+; CHECK-NEXT:    vmull.s16 q0, d0, d16
+; CHECK-NEXT:    bx lr
   %tmp3 = sext <4 x i16> %arg to <4 x i32>
   %tmp4 = mul <4 x i32> %tmp3, <i32 -12, i32 -12, i32 -12, i32 -12>
   ret <4 x i32> %tmp4
 }
 
 define <4 x i32> @vmull_extvec_u16(<4 x i16> %arg) nounwind {
-; CHECK: vmull_extvec_u16
-; CHECK: vmull.u16
+; CHECK-LABEL: vmull_extvec_u16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr d16, .LCPI47_0
+; CHECK-NEXT:    vmull.u16 q0, d0, d16
+; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 3
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI47_0:
+; CHECK-NEXT:    .short 1234 @ 0x4d2
+; CHECK-NEXT:    .short 1234 @ 0x4d2
+; CHECK-NEXT:    .short 1234 @ 0x4d2
+; CHECK-NEXT:    .short 1234 @ 0x4d2
   %tmp3 = zext <4 x i16> %arg to <4 x i32>
   %tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234>
   ret <4 x i32> %tmp4
 }
 
 define <2 x i64> @vmull_extvec_s32(<2 x i32> %arg) nounwind {
-; CHECK: vmull_extvec_s32
-; CHECK: vmull.s32
+; CHECK-LABEL: vmull_extvec_s32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr d16, .LCPI48_0
+; CHECK-NEXT:    vmull.s32 q0, d0, d16
+; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 3
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI48_0:
+; CHECK-NEXT:    .long 4294966062 @ 0xfffffb2e
+; CHECK-NEXT:    .long 4294966062 @ 0xfffffb2e
   %tmp3 = sext <2 x i32> %arg to <2 x i64>
   %tmp4 = mul <2 x i64> %tmp3, <i64 -1234, i64 -1234>
   ret <2 x i64> %tmp4
 }
 
 define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind {
-; CHECK: vmull_extvec_u32
-; CHECK: vmull.u32
+; CHECK-LABEL: vmull_extvec_u32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vldr d16, .LCPI49_0
+; CHECK-NEXT:    vmull.u32 q0, d0, d16
+; CHECK-NEXT:    bx lr
+; CHECK-NEXT:    .p2align 3
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI49_0:
+; CHECK-NEXT:    .long 1234 @ 0x4d2
+; CHECK-NEXT:    .long 1234 @ 0x4d2
   %tmp3 = zext <2 x i32> %arg to <2 x i64>
   %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>
   ret <2 x i64> %tmp4
@@ -440,10 +660,15 @@ define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind {
 
 ; rdar://9197392
 define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {
-entry:
 ; CHECK-LABEL: distribute:
-; CHECK: vmull.u8 [[REG1:(q[0-9]+)]], d{{.*}}, [[REG2:(d[0-9]+)]]
-; CHECK: vmlal.u8 [[REG1]], d{{.*}}, [[REG2]]
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vld1.8 {d16, d17}, [r1]
+; CHECK-NEXT:    vdup.8 d18, r2
+; CHECK-NEXT:    vmull.u8 q10, d17, d18
+; CHECK-NEXT:    vmlal.u8 q10, d16, d18
+; CHECK-NEXT:    vst1.16 {d20, d21}, [r0]
+; CHECK-NEXT:    bx lr
+entry:
   %0 = trunc i32 %mul to i8
   %1 = insertelement <8 x i8> undef, i8 %0, i32 0
   %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -472,11 +697,15 @@ declare void @llvm.arm.neon.vst1.p0i8.v8i16(i8*, <8 x i16>, i32) nounwind
 %struct.uint8x8_t = type { <8 x i8> }
 
 define void @distribute2(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind {
+; CHECK-LABEL: distribute2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vld1.8 {d16, d17}, [r1]
+; CHECK-NEXT:    vadd.i8 d16, d17, d16
+; CHECK-NEXT:    vdup.8 d17, r2
+; CHECK-NEXT:    vmul.i8 d16, d16, d17
+; CHECK-NEXT:    vstr d16, [r0]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: distribute2
-; CHECK-NOT: vadd.i8
-; CHECK: vmul.i8
-; CHECK: vmla.i8
   %0 = trunc i32 %mul to i8
   %1 = insertelement <8 x i8> undef, i8 %0, i32 0
   %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -494,11 +723,15 @@ entry:
 }
 
 define void @distribute2_commutative(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind {
+; CHECK-LABEL: distribute2_commutative:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vld1.8 {d16, d17}, [r1]
+; CHECK-NEXT:    vadd.i8 d16, d17, d16
+; CHECK-NEXT:    vdup.8 d17, r2
+; CHECK-NEXT:    vmul.i8 d16, d17, d16
+; CHECK-NEXT:    vstr d16, [r0]
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: distribute2_commutative
-; CHECK-NOT: vadd.i8
-; CHECK: vmul.i8
-; CHECK: vmla.i8
   %0 = trunc i32 %mul to i8
   %1 = insertelement <8 x i8> undef, i8 %0, i32 0
   %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
@@ -516,11 +749,12 @@ entry:
 }
 
 define <8 x i8> @no_distribute(<8 x i8> %a, <8 x i8> %b) nounwind {
+; CHECK-LABEL: no_distribute:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vadd.i8 d16, d0, d1
+; CHECK-NEXT:    vmul.i8 d0, d16, d16
+; CHECK-NEXT:    bx lr
 entry:
-; CHECK: no_distribute
-; CHECK: vadd.i8
-; CHECK: vmul.i8
-; CHECK-NOT: vmla.i8
   %0 = add <8 x i8> %a, %b
   %1 = mul <8x i8> %0, %0
   ret <8 x i8> %1
@@ -529,8 +763,13 @@ entry:
 ; If one operand has a zero-extend and the other a sign-extend, vmull
 ; cannot be used.
 define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {
-; CHECK: vmullWithInconsistentExtensions
-; CHECK-NOT: vmull.s8
+; CHECK-LABEL: vmullWithInconsistentExtensions:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.s8 q8, d0
+; CHECK-NEXT:    vmov.i16 q9, #0xff
+; CHECK-NEXT:    vmul.i16 q8, q8, q9
+; CHECK-NEXT:    vmov.u16 r0, d16[0]
+; CHECK-NEXT:    bx lr
   %1 = sext <8 x i8> %vec to <8 x i16>
   %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
   %3 = extractelement <8 x i16> %2, i32 0
@@ -540,7 +779,13 @@ define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {
 ; A constant build_vector created for a vmull with half-width elements must
 ; not introduce illegal types. <rdar://problem/11324364>
 define void @vmull_buildvector() nounwind optsize ssp align 2 {
-; CHECK: vmull_buildvector
+; CHECK-LABEL: vmull_buildvector:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    bxne lr
+; CHECK-NEXT:  .LBB55_1: @ %for.body33.lr.ph
+; CHECK-NEXT:    .inst 0xe7ffdefe
 entry:
   br i1 undef, label %for.end179, label %for.body.lr.ph
 
@@ -615,6 +860,9 @@ declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone
 ; creating an illegal type during legalization and causing an assert.
 ; PR15970
 define void @no_illegal_types_vmull_sext(<4 x i32> %a) {
+; CHECK-LABEL: no_illegal_types_vmull_sext:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .inst 0xe7ffdefe
 entry:
   %wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1
   %0 = sext <4 x i8> %wide.load283.i to <4 x i32>
@@ -625,6 +873,9 @@ entry:
   ret void
 }
 define void @no_illegal_types_vmull_zext(<4 x i32> %a) {
+; CHECK-LABEL: no_illegal_types_vmull_zext:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    .inst 0xe7ffdefe
 entry:
   %wide.load283.i = load <4 x i8>, <4 x i8>* undef, align 1
   %0 = zext <4 x i8> %wide.load283.i to <4 x i32>
@@ -635,11 +886,16 @@ entry:
   ret void
 }
 
-define void @fmul_splat(<4 x float> * %a, <4 x float>* nocapture %dst, float %tmp) nounwind {
+define void @fmul_splat(<4 x float>* %A, <4 x float>* nocapture %dst, float %tmp) nounwind {
 ; Look for a scalar float rather than a splat, then a vector*scalar multiply.
-; CHECK: vmov s0, r2
-; CHECK: vmul.f32  q8, q8, d0[0]
-  %tmp5 = load <4 x float>, <4 x float>* %a, align 4
+; CHECK-LABEL: fmul_splat:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vld1.32 {d16, d17}, [r0]
+; CHECK-NEXT:    @ kill: def $s0 killed $s0 def $d0
+; CHECK-NEXT:    vmul.f32 q8, q8, d0[0]
+; CHECK-NEXT:    vst1.32 {d16, d17}, [r1]
+; CHECK-NEXT:    bx lr
+  %tmp5 = load <4 x float>, <4 x float>* %A, align 4
   %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0
   %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1
   %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2
@@ -649,14 +905,19 @@ define void @fmul_splat(<4 x float> * %a, <4 x float>* nocapture %dst, float %tm
   ret void
 }
 
-define void @fmul_splat_load(<4 x float> * %a, <4 x float>* nocapture %dst, float* nocapture readonly %src) nounwind {
+define void @fmul_splat_load(<4 x float>* %A, <4 x float>* nocapture %dst, float* nocapture readonly %src) nounwind {
 ; Look for doing a normal scalar FP load rather than an to-all-lanes load,
 ; then a vector*scalar multiply.
 ; FIXME: Temporarily broken due to splat representation changes.
-; CHECK: vld1.32 {d18[], d19[]}, [r2:32]
-; CHECK: vmul.f32  q8, q9, q8
+; CHECK-LABEL: fmul_splat_load:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vld1.32 {d16, d17}, [r0]
+; CHECK-NEXT:    vld1.32 {d18[], d19[]}, [r2:32]
+; CHECK-NEXT:    vmul.f32 q8, q9, q8
+; CHECK-NEXT:    vst1.32 {d16, d17}, [r1]
+; CHECK-NEXT:    bx lr
   %tmp = load float, float* %src, align 4
-  %tmp5 = load <4 x float>, <4 x float>* %a, align 4
+  %tmp5 = load <4 x float>, <4 x float>* %A, align 4
   %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0
   %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1
   %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2
diff --git a/llvm/test/CodeGen/ARM/vsub.ll b/llvm/test/CodeGen/ARM/vsub.ll
index 75fb7d493a59f..8743fcc478890 100644
--- a/llvm/test/CodeGen/ARM/vsub.ll
+++ b/llvm/test/CodeGen/ARM/vsub.ll
@@ -1,275 +1,370 @@
-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
-
-define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubi8:
-;CHECK: vsub.i8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = sub <8 x i8> %tmp1, %tmp2
-	ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubi16:
-;CHECK: vsub.i16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = sub <4 x i16> %tmp1, %tmp2
-	ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubi32:
-;CHECK: vsub.i32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = sub <2 x i32> %tmp1, %tmp2
-	ret <2 x i32> %tmp3
-}
-
-define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK-LABEL: vsubi64:
-;CHECK: vsub.i64
-	%tmp1 = load <1 x i64>, <1 x i64>* %A
-	%tmp2 = load <1 x i64>, <1 x i64>* %B
-	%tmp3 = sub <1 x i64> %tmp1, %tmp2
-	ret <1 x i64> %tmp3
-}
-
-define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK-LABEL: vsubf32:
-;CHECK: vsub.f32
-	%tmp1 = load <2 x float>, <2 x float>* %A
-	%tmp2 = load <2 x float>, <2 x float>* %B
-	%tmp3 = fsub <2 x float> %tmp1, %tmp2
-	ret <2 x float> %tmp3
-}
-
-define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubQi8:
-;CHECK: vsub.i8
-	%tmp1 = load <16 x i8>, <16 x i8>* %A
-	%tmp2 = load <16 x i8>, <16 x i8>* %B
-	%tmp3 = sub <16 x i8> %tmp1, %tmp2
-	ret <16 x i8> %tmp3
-}
-
-define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubQi16:
-;CHECK: vsub.i16
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i16>, <8 x i16>* %B
-	%tmp3 = sub <8 x i16> %tmp1, %tmp2
-	ret <8 x i16> %tmp3
-}
-
-define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubQi32:
-;CHECK: vsub.i32
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i32>, <4 x i32>* %B
-	%tmp3 = sub <4 x i32> %tmp1, %tmp2
-	ret <4 x i32> %tmp3
-}
-
-define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vsubQi64:
-;CHECK: vsub.i64
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i64>, <2 x i64>* %B
-	%tmp3 = sub <2 x i64> %tmp1, %tmp2
-	ret <2 x i64> %tmp3
-}
-
-define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK-LABEL: vsubQf32:
-;CHECK: vsub.f32
-	%tmp1 = load <4 x float>, <4 x float>* %A
-	%tmp2 = load <4 x float>, <4 x float>* %B
-	%tmp3 = fsub <4 x float> %tmp1, %tmp2
-	ret <4 x float> %tmp3
-}
-
-define <8 x i8> @vsubhni16_natural(<8 x i16> %A, <8 x i16> %B) nounwind {
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a-eabi -mattr=+neon -float-abi=hard %s -o - | FileCheck %s
+
+define <8 x i8> @vsubi8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubi8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.i8 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sub <8 x i8> %A, %B
+  ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vsubi16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubi16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.i16 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sub <4 x i16> %A, %B
+  ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vsubi32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubi32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.i32 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sub <2 x i32> %A, %B
+  ret <2 x i32> %tmp3
+}
+
+define <1 x i64> @vsubi64(<1 x i64> %A, <1 x i64> %B) {
+; CHECK-LABEL: vsubi64:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.i64 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sub <1 x i64> %A, %B
+  ret <1 x i64> %tmp3
+}
+
+define <2 x float> @vsubf32(<2 x float> %A, <2 x float> %B) {
+; CHECK-LABEL: vsubf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.f32 d0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = fsub <2 x float> %A, %B
+  ret <2 x float> %tmp3
+}
+
+define <16 x i8> @vsubQi8(<16 x i8> %A, <16 x i8> %B) {
+; CHECK-LABEL: vsubQi8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.i8 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sub <16 x i8> %A, %B
+  ret <16 x i8> %tmp3
+}
+
+define <8 x i16> @vsubQi16(<8 x i16> %A, <8 x i16> %B) {
+; CHECK-LABEL: vsubQi16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.i16 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sub <8 x i16> %A, %B
+  ret <8 x i16> %tmp3
+}
+
+define <4 x i32> @vsubQi32(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: vsubQi32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.i32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sub <4 x i32> %A, %B
+  ret <4 x i32> %tmp3
+}
+
+define <2 x i64> @vsubQi64(<2 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: vsubQi64:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.i64 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sub <2 x i64> %A, %B
+  ret <2 x i64> %tmp3
+}
+
+define <4 x float> @vsubQf32(<4 x float> %A, <4 x float> %B) {
+; CHECK-LABEL: vsubQf32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsub.f32 q0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = fsub <4 x float> %A, %B
+  ret <4 x float> %tmp3
+}
+
+define <8 x i8> @vrsubhni16(<8 x i16> %A, <8 x i16> %B) {
+; CHECK-LABEL: vrsubhni16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vrsubhn.i16 d0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %A, <8 x i16> %B)
+  ret <8 x i8> %tmp3
+}
+
+define <4 x i16> @vrsubhni32(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: vrsubhni32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vrsubhn.i32 d0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %A, <4 x i32> %B)
+  ret <4 x i16> %tmp3
+}
+
+define <2 x i32> @vrsubhni64(<2 x i64> %A, <2 x i64> %B) {
+; CHECK-LABEL: vrsubhni64:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vrsubhn.i64 d0, q0, q1
+; CHECK-NEXT:    bx lr
+  %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %A, <2 x i64> %B)
+  ret <2 x i32> %tmp3
+}
+
+declare <8 x i8>  @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) readnone
+declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) readnone
+declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) readnone
+
+define <8 x i8> @vsubhni16_natural(<8 x i16> %A, <8 x i16> %B) {
 ; CHECK-LABEL: vsubhni16_natural:
-; CHECK: vsubhn.i16
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubhn.i16 d0, q0, q1
+; CHECK-NEXT:    bx lr
   %sum = sub <8 x i16> %A, %B
   %shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
   %trunc = trunc <8 x i16> %shift to <8 x i8>
   ret <8 x i8> %trunc
 }
 
-define <4 x i16> @vsubhni32_natural(<4 x i32> %A, <4 x i32> %B) nounwind {
+define <4 x i16> @vsubhni32_natural(<4 x i32> %A, <4 x i32> %B) {
 ; CHECK-LABEL: vsubhni32_natural:
-; CHECK: vsubhn.i32
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubhn.i32 d0, q0, q1
+; CHECK-NEXT:    bx lr
   %sum = sub <4 x i32> %A, %B
   %shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>
   %trunc = trunc <4 x i32> %shift to <4 x i16>
   ret <4 x i16> %trunc
 }
 
-define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind {
+define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) {
 ; CHECK-LABEL: vsubhni64_natural:
-; CHECK: vsubhn.i64
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubhn.i64 d0, q0, q1
+; CHECK-NEXT:    bx lr
   %sum = sub <2 x i64> %A, %B
   %shift = lshr <2 x i64> %sum, <i64 32, i64 32>
   %trunc = trunc <2 x i64> %shift to <2 x i32>
   ret <2 x i32> %trunc
 }
 
-define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK-LABEL: vrsubhni16:
-;CHECK: vrsubhn.i16
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i16>, <8 x i16>* %B
-	%tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
-	ret <8 x i8> %tmp3
-}
-
-define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK-LABEL: vrsubhni32:
-;CHECK: vrsubhn.i32
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i32>, <4 x i32>* %B
-	%tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
-	ret <4 x i16> %tmp3
-}
-
-define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK-LABEL: vrsubhni64:
-;CHECK: vrsubhn.i64
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i64>, <2 x i64>* %B
-	%tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
-	ret <2 x i32> %tmp3
-}
-
-declare <8 x i8>  @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
-declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
-declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
-
-define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubls8:
-;CHECK: vsubl.s8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
-	%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
-	%tmp5 = sub <8 x i16> %tmp3, %tmp4
-	ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubls16:
-;CHECK: vsubl.s16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
-	%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
-	%tmp5 = sub <4 x i32> %tmp3, %tmp4
-	ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubls32:
-;CHECK: vsubl.s32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
-	%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
-	%tmp5 = sub <2 x i64> %tmp3, %tmp4
-	ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsublu8:
-;CHECK: vsubl.u8
-	%tmp1 = load <8 x i8>, <8 x i8>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
-	%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
-	%tmp5 = sub <8 x i16> %tmp3, %tmp4
-	ret <8 x i16> %tmp5
-}
-
-define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsublu16:
-;CHECK: vsubl.u16
-	%tmp1 = load <4 x i16>, <4 x i16>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
-	%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
-	%tmp5 = sub <4 x i32> %tmp3, %tmp4
-	ret <4 x i32> %tmp5
-}
-
-define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsublu32:
-;CHECK: vsubl.u32
-	%tmp1 = load <2 x i32>, <2 x i32>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
-	%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
-	%tmp5 = sub <2 x i64> %tmp3, %tmp4
-	ret <2 x i64> %tmp5
-}
-
-define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubws8:
-;CHECK: vsubw.s8
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = sext <8 x i8> %tmp2 to <8 x i16>
-	%tmp4 = sub <8 x i16> %tmp1, %tmp3
-	ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubws16:
-;CHECK: vsubw.s16
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = sext <4 x i16> %tmp2 to <4 x i32>
-	%tmp4 = sub <4 x i32> %tmp1, %tmp3
-	ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubws32:
-;CHECK: vsubw.s32
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = sext <2 x i32> %tmp2 to <2 x i64>
-	%tmp4 = sub <2 x i64> %tmp1, %tmp3
-	ret <2 x i64> %tmp4
-}
-
-define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK-LABEL: vsubwu8:
-;CHECK: vsubw.u8
-	%tmp1 = load <8 x i16>, <8 x i16>* %A
-	%tmp2 = load <8 x i8>, <8 x i8>* %B
-	%tmp3 = zext <8 x i8> %tmp2 to <8 x i16>
-	%tmp4 = sub <8 x i16> %tmp1, %tmp3
-	ret <8 x i16> %tmp4
-}
-
-define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK-LABEL: vsubwu16:
-;CHECK: vsubw.u16
-	%tmp1 = load <4 x i32>, <4 x i32>* %A
-	%tmp2 = load <4 x i16>, <4 x i16>* %B
-	%tmp3 = zext <4 x i16> %tmp2 to <4 x i32>
-	%tmp4 = sub <4 x i32> %tmp1, %tmp3
-	ret <4 x i32> %tmp4
-}
-
-define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK-LABEL: vsubwu32:
-;CHECK: vsubw.u32
-	%tmp1 = load <2 x i64>, <2 x i64>* %A
-	%tmp2 = load <2 x i32>, <2 x i32>* %B
-	%tmp3 = zext <2 x i32> %tmp2 to <2 x i64>
-	%tmp4 = sub <2 x i64> %tmp1, %tmp3
-	ret <2 x i64> %tmp4
+define <8 x i16> @vsubls8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubls8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubl.s8 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <8 x i8> %A to <8 x i16>
+  %tmp4 = sext <8 x i8> %B to <8 x i16>
+  %tmp5 = sub <8 x i16> %tmp3, %tmp4
+  ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vsubls16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubls16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubl.s16 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <4 x i16> %A to <4 x i32>
+  %tmp4 = sext <4 x i16> %B to <4 x i32>
+  %tmp5 = sub <4 x i32> %tmp3, %tmp4
+  ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @vsubls32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubls32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubl.s32 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <2 x i32> %A to <2 x i64>
+  %tmp4 = sext <2 x i32> %B to <2 x i64>
+  %tmp5 = sub <2 x i64> %tmp3, %tmp4
+  ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @vsublu8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsublu8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubl.u8 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <8 x i8> %A to <8 x i16>
+  %tmp4 = zext <8 x i8> %B to <8 x i16>
+  %tmp5 = sub <8 x i16> %tmp3, %tmp4
+  ret <8 x i16> %tmp5
+}
+
+define <4 x i32> @vsublu16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsublu16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubl.u16 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <4 x i16> %A to <4 x i32>
+  %tmp4 = zext <4 x i16> %B to <4 x i32>
+  %tmp5 = sub <4 x i32> %tmp3, %tmp4
+  ret <4 x i32> %tmp5
+}
+
+define <2 x i64> @vsublu32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsublu32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubl.u32 q0, d0, d1
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <2 x i32> %A to <2 x i64>
+  %tmp4 = zext <2 x i32> %B to <2 x i64>
+  %tmp5 = sub <2 x i64> %tmp3, %tmp4
+  ret <2 x i64> %tmp5
+}
+
+define <8 x i16> @vsubla8(<8 x i8> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubla8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u8 q8, d1
+; CHECK-NEXT:    vmovl.u8 q9, d0
+; CHECK-NEXT:    vsub.i16 q0, q9, q8
+; CHECK-NEXT:    vbic.i16 q0, #0xff00
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <8 x i8> %A to <8 x i16>
+  %tmp4 = zext <8 x i8> %B to <8 x i16>
+  %tmp5 = sub <8 x i16> %tmp3, %tmp4
+  %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @vsubla16(<4 x i16> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubla16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u16 q8, d1
+; CHECK-NEXT:    vmovl.u16 q9, d0
+; CHECK-NEXT:    vmov.i32 q10, #0xffff
+; CHECK-NEXT:    vsub.i32 q8, q9, q8
+; CHECK-NEXT:    vand q0, q8, q10
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <4 x i16> %A to <4 x i32>
+  %tmp4 = zext <4 x i16> %B to <4 x i32>
+  %tmp5 = sub <4 x i32> %tmp3, %tmp4
+  %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @vsubla32(<2 x i32> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubla32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u32 q8, d1
+; CHECK-NEXT:    vmovl.u32 q9, d0
+; CHECK-NEXT:    vmov.i64 q10, #0xffffffff
+; CHECK-NEXT:    vsub.i64 q8, q9, q8
+; CHECK-NEXT:    vand q0, q8, q10
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <2 x i32> %A to <2 x i64>
+  %tmp4 = zext <2 x i32> %B to <2 x i64>
+  %tmp5 = sub <2 x i64> %tmp3, %tmp4
+  %and = and <2 x i64> %tmp5, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
+}
+
+define <8 x i16> @vsubws8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubws8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubw.s8 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <8 x i8> %B to <8 x i16>
+  %tmp4 = sub <8 x i16> %A, %tmp3
+  ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsubws16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubws16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubw.s16 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <4 x i16> %B to <4 x i32>
+  %tmp4 = sub <4 x i32> %A, %tmp3
+  ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsubws32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubws32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubw.s32 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = sext <2 x i32> %B to <2 x i64>
+  %tmp4 = sub <2 x i64> %A, %tmp3
+  ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vsubwu8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubwu8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubw.u8 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <8 x i8> %B to <8 x i16>
+  %tmp4 = sub <8 x i16> %A, %tmp3
+  ret <8 x i16> %tmp4
+}
+
+define <4 x i32> @vsubwu16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubwu16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubw.u16 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <4 x i16> %B to <4 x i32>
+  %tmp4 = sub <4 x i32> %A, %tmp3
+  ret <4 x i32> %tmp4
+}
+
+define <2 x i64> @vsubwu32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubwu32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vsubw.u32 q0, q0, d2
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <2 x i32> %B to <2 x i64>
+  %tmp4 = sub <2 x i64> %A, %tmp3
+  ret <2 x i64> %tmp4
+}
+
+define <8 x i16> @vsubwa8(<8 x i16> %A, <8 x i8> %B) {
+; CHECK-LABEL: vsubwa8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u8 q8, d2
+; CHECK-NEXT:    vsub.i16 q0, q0, q8
+; CHECK-NEXT:    vbic.i16 q0, #0xff00
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <8 x i8> %B to <8 x i16>
+  %tmp4 = sub <8 x i16> %A, %tmp3
+  %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  ret <8 x i16> %and
+}
+
+define <4 x i32> @vsubwa16(<4 x i32> %A, <4 x i16> %B) {
+; CHECK-LABEL: vsubwa16:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u16 q8, d2
+; CHECK-NEXT:    vmov.i32 q9, #0xffff
+; CHECK-NEXT:    vsub.i32 q8, q0, q8
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <4 x i16> %B to <4 x i32>
+  %tmp4 = sub <4 x i32> %A, %tmp3
+  %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
+  ret <4 x i32> %and
+}
+
+define <2 x i64> @vsubwa32(<2 x i64> %A, <2 x i32> %B) {
+; CHECK-LABEL: vsubwa32:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    vmovl.u32 q8, d2
+; CHECK-NEXT:    vmov.i64 q9, #0xffffffff
+; CHECK-NEXT:    vsub.i64 q8, q0, q8
+; CHECK-NEXT:    vand q0, q8, q9
+; CHECK-NEXT:    bx lr
+  %tmp3 = zext <2 x i32> %B to <2 x i64>
+  %tmp4 = sub <2 x i64> %A, %tmp3
+  %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
+  ret <2 x i64> %and
 }
diff --git a/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll b/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
new file mode 100644
index 0000000000000..c7e87e3f62a6a
--- /dev/null
+++ b/llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
@@ -0,0 +1,23 @@
+; RUN: llc -O0 -march aarch64 -global-isel -stop-after=irtranslator -o - %s | llc -x mir -march aarch64 -run-pass=none -o - | FileCheck %s
+
+define i16 @unnamed_stack() {
+entry:
+  ; CHECK-NAME: unnamed_stack
+  ; CHECK:      stack:
+  ; CHECK-NEXT:   - { id: 0, name: '',
+  ; CHECK:      %0:_(p0) = G_FRAME_INDEX %stack.0
+  %0 = alloca i16
+  %1 = load i16, i16* %0
+  ret i16 %1
+}
+
+define i16 @named_stack() {
+entry:
+  ; CHECK-NAME: named_stack
+  ; CHECK:      stack:
+  ; CHECK-NEXT:   - { id: 0, name: ptr,
+  ; CHECK:      %0:_(p0) = G_FRAME_INDEX %stack.0.ptr
+  %ptr = alloca i16
+  %0 = load i16, i16* %ptr
+  ret i16 %0
+}
diff --git a/llvm/test/CodeGen/PowerPC/aix-base-pointer.ll b/llvm/test/CodeGen/PowerPC/aix-base-pointer.ll
index 2b1cc0c45db4c..c6e1107d47387 100644
--- a/llvm/test/CodeGen/PowerPC/aix-base-pointer.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-base-pointer.ll
@@ -27,7 +27,7 @@ declare void @callee(i32*)
 ; 32BIT:         stwux 1, 1, 0
 ; 32BIT:         addi 3, 1, 64
 ; 32BIT:         bl .callee
-; 32BIT:         lwz 1, 0(1)
+; 32BIT:         mr 1, 30
 ; 32BIT:         lwz 30, -16(1)
 
 ; 64BIT-LABEL: .caller:
@@ -38,5 +38,5 @@ declare void @callee(i32*)
 ; 64BIT:         stdux 1, 1, 0
 ; 64BIT:         addi 3, 1, 128
 ; 64BIT:         bl .callee
-; 64BIT:         ld 1, 0(1)
+; 64BIT:         mr 1, 30
 ; 64BIT:         ld 30, -24(1)
diff --git a/llvm/test/CodeGen/PowerPC/alloca-crspill.ll b/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
index f52e305fb05c4..b71a9ff6d49b3 100644
--- a/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
+++ b/llvm/test/CodeGen/PowerPC/alloca-crspill.ll
@@ -49,8 +49,8 @@ declare signext i32 @do_something(double*)
 ; CHECK64-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 
 ; CHECK64-NEXT: stack:
-; CHECK64-NEXT:   - { id: 0, name: '<unnamed alloca>', type: variable-sized, offset: -8,
-; CHECK64-NEXT:       alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+; CHECK64-NEXT:   - { id: 0, name: '', type: variable-sized, offset: -8, alignment: 1, 
+; CHECK64-NEXT:       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
 ; CHECK64-NEXT:       local-offset: 0, debug-info-variable: '', debug-info-expression: '',
 ; CHECK64-NEXT:       debug-info-location: '' }
 ; CHECK64-NEXT:   - { id: 1, name: '', type: default, offset: -16, size: 8, alignment: 8,
@@ -68,8 +68,8 @@ declare signext i32 @do_something(double*)
 ; CHECK32-NEXT:       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 
 ; CHECK32-NEXT: stack:
-; CHECK32-NEXT:   - { id: 0, name: '<unnamed alloca>', type: variable-sized, offset: -4,
-; CHECK32-NEXT:       alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+; CHECK32-NEXT:   - { id: 0, name: '', type: variable-sized, offset: -4, alignment: 1, 
+; CHECK32-NEXT:       stack-id: default, callee-saved-register: '', callee-saved-restored: true,
 ; CHECK32-NEXT:       local-offset: 0, debug-info-variable: '', debug-info-expression: '',
 ; CHECK32-NEXT:       debug-info-location: '' }
 ; CHECK32-NEXT:   - { id: 1, name: '', type: default, offset: -8, size: 4, alignment: 4,
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
index 17617e90a01f4..9e8f8d073a1ae 100644
--- a/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
@@ -1,13 +1,13 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
-; RUN:   FileCheck %s
+; RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-LE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
-; RUN:   FileCheck %s
+; RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-BE
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O0 \
 ; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
-; RUN:   FileCheck %s --check-prefix=CHECK-O0
+; RUN:   FileCheck %s --check-prefixes=CHECK,CHECK-O0
 
 ; These test cases aims to test the builtins for the Power10 VSX vector
 ; instructions introduced in ISA 3.1.
@@ -22,14 +22,6 @@ define signext i32 @test_vec_test_lsbb_all_ones(<16 x i8> %vuca) {
 ; CHECK-NEXT:    srwi r3, r3, 31
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
-;
-; CHECK-O0-LABEL: test_vec_test_lsbb_all_ones:
-; CHECK-O0:       # %bb.0: # %entry
-; CHECK-O0-NEXT:    xvtlsbb cr0, v2
-; CHECK-O0-NEXT:    mfocrf r3, 128
-; CHECK-O0-NEXT:    srwi r3, r3, 31
-; CHECK-O0-NEXT:    extsw r3, r3
-; CHECK-O0-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 1)
   ret i32 %0
@@ -43,24 +35,22 @@ define signext i32 @test_vec_test_lsbb_all_zeros(<16 x i8> %vuca) {
 ; CHECK-NEXT:    rlwinm r3, r3, 3, 31, 31
 ; CHECK-NEXT:    extsw r3, r3
 ; CHECK-NEXT:    blr
-;
-; CHECK-O0-LABEL: test_vec_test_lsbb_all_zeros:
-; CHECK-O0:       # %bb.0: # %entry
-; CHECK-O0-NEXT:    xvtlsbb cr0, v2
-; CHECK-O0-NEXT:    mfocrf r3, 128
-; CHECK-O0-NEXT:    rlwinm r3, r3, 3, 31, 31
-; CHECK-O0-NEXT:    extsw r3, r3
-; CHECK-O0-NEXT:    blr
 entry:
   %0 = tail call i32 @llvm.ppc.vsx.xvtlsbb(<16 x i8> %vuca, i32 0)
   ret i32 %0
 }
 
 define void @vec_xst_trunc_sc(<1 x i128> %__vec, i64 %__offset, i8* nocapture %__ptr) {
-; CHECK-LABEL: vec_xst_trunc_sc:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrbx v2, r6, r5
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xst_trunc_sc:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    stxvrbx v2, r6, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xst_trunc_sc:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 9
+; CHECK-BE-NEXT:    stxsibx v2, r6, r5
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xst_trunc_sc:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -79,10 +69,16 @@ entry:
 }
 
 define void @vec_xst_trunc_uc(<1 x i128> %__vec, i64 %__offset, i8* nocapture %__ptr) {
-; CHECK-LABEL: vec_xst_trunc_uc:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    stxvrbx v2, r6, r5
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xst_trunc_uc:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    stxvrbx v2, r6, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xst_trunc_uc:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 9
+; CHECK-BE-NEXT:    stxsibx v2, r6, r5
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xst_trunc_uc:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -101,11 +97,18 @@ entry:
 }
 
 define void @vec_xst_trunc_ss(<1 x i128> %__vec, i64 %__offset, i16* nocapture %__ptr) {
-; CHECK-LABEL: vec_xst_trunc_ss:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sldi r3, r5, 1
-; CHECK-NEXT:    stxvrhx v2, r6, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xst_trunc_ss:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    sldi r3, r5, 1
+; CHECK-LE-NEXT:    stxvrhx v2, r6, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xst_trunc_ss:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
+; CHECK-BE-NEXT:    sldi r3, r5, 1
+; CHECK-BE-NEXT:    stxsihx v2, r6, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xst_trunc_ss:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -125,11 +128,18 @@ entry:
 }
 
 define void @vec_xst_trunc_us(<1 x i128> %__vec, i64 %__offset, i16* nocapture %__ptr) {
-; CHECK-LABEL: vec_xst_trunc_us:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sldi r3, r5, 1
-; CHECK-NEXT:    stxvrhx v2, r6, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xst_trunc_us:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    sldi r3, r5, 1
+; CHECK-LE-NEXT:    stxvrhx v2, r6, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xst_trunc_us:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
+; CHECK-BE-NEXT:    sldi r3, r5, 1
+; CHECK-BE-NEXT:    stxsihx v2, r6, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xst_trunc_us:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -149,11 +159,18 @@ entry:
 }
 
 define void @vec_xst_trunc_si(<1 x i128> %__vec, i64 %__offset, i32* nocapture %__ptr) {
-; CHECK-LABEL: vec_xst_trunc_si:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sldi r3, r5, 2
-; CHECK-NEXT:    stxvrwx v2, r6, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xst_trunc_si:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    sldi r3, r5, 2
+; CHECK-LE-NEXT:    stxvrwx v2, r6, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xst_trunc_si:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    sldi r3, r5, 2
+; CHECK-BE-NEXT:    stfiwx f0, r6, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xst_trunc_si:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -173,11 +190,18 @@ entry:
 }
 
 define void @vec_xst_trunc_ui(<1 x i128> %__vec, i64 %__offset, i32* nocapture %__ptr) {
-; CHECK-LABEL: vec_xst_trunc_ui:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sldi r3, r5, 2
-; CHECK-NEXT:    stxvrwx v2, r6, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xst_trunc_ui:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    sldi r3, r5, 2
+; CHECK-LE-NEXT:    stxvrwx v2, r6, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xst_trunc_ui:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    sldi r3, r5, 2
+; CHECK-BE-NEXT:    stfiwx f0, r6, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xst_trunc_ui:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -197,11 +221,17 @@ entry:
 }
 
 define void @vec_xst_trunc_sll(<1 x i128> %__vec, i64 %__offset, i64* nocapture %__ptr)  {
-; CHECK-LABEL: vec_xst_trunc_sll:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sldi r3, r5, 3
-; CHECK-NEXT:    stxvrdx v2, r6, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xst_trunc_sll:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    sldi r3, r5, 3
+; CHECK-LE-NEXT:    stxvrdx v2, r6, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xst_trunc_sll:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    sldi r3, r5, 3
+; CHECK-BE-NEXT:    stxsdx v2, r6, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xst_trunc_sll:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -219,11 +249,17 @@ entry:
 }
 
 define void @vec_xst_trunc_ull(<1 x i128> %__vec, i64 %__offset, i64* nocapture %__ptr)  {
-; CHECK-LABEL: vec_xst_trunc_ull:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sldi r3, r5, 3
-; CHECK-NEXT:    stxvrdx v2, r6, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xst_trunc_ull:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    sldi r3, r5, 3
+; CHECK-LE-NEXT:    stxvrdx v2, r6, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xst_trunc_ull:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    sldi r3, r5, 3
+; CHECK-BE-NEXT:    stxsdx v2, r6, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xst_trunc_ull:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -245,11 +281,6 @@ define dso_local <1 x i128> @vec_xl_zext(i64 %__offset, i8* nocapture readonly %
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    lxvrbx v2, r4, r3
 ; CHECK-NEXT:    blr
-;
-; CHECK-O0-LABEL: vec_xl_zext:
-; CHECK-O0:       # %bb.0: # %entry
-; CHECK-O0-NEXT:    lxvrbx v2, r4, r3
-; CHECK-O0-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, i8* %__pointer, i64 %__offset
   %0 = load i8, i8* %add.ptr, align 1
@@ -264,12 +295,6 @@ define dso_local <1 x i128> @vec_xl_zext_short(i64 %__offset, i16* nocapture rea
 ; CHECK-NEXT:    sldi r3, r3, 1
 ; CHECK-NEXT:    lxvrhx v2, r4, r3
 ; CHECK-NEXT:    blr
-;
-; CHECK-O0-LABEL: vec_xl_zext_short:
-; CHECK-O0:       # %bb.0: # %entry
-; CHECK-O0-NEXT:    sldi r3, r3, 1
-; CHECK-O0-NEXT:    lxvrhx v2, r4, r3
-; CHECK-O0-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i16, i16* %__pointer, i64 %__offset
   %0 = load i16, i16* %add.ptr, align 2
@@ -284,12 +309,6 @@ define dso_local <1 x i128> @vec_xl_zext_word(i64 %__offset, i32* nocapture read
 ; CHECK-NEXT:    sldi r3, r3, 2
 ; CHECK-NEXT:    lxvrwx v2, r4, r3
 ; CHECK-NEXT:    blr
-;
-; CHECK-O0-LABEL: vec_xl_zext_word:
-; CHECK-O0:       # %bb.0: # %entry
-; CHECK-O0-NEXT:    sldi r3, r3, 2
-; CHECK-O0-NEXT:    lxvrwx v2, r4, r3
-; CHECK-O0-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i32, i32* %__pointer, i64 %__offset
   %0 = load i32, i32* %add.ptr, align 4
@@ -304,12 +323,6 @@ define dso_local <1 x i128> @vec_xl_zext_dw(i64 %__offset, i64* nocapture readon
 ; CHECK-NEXT:    sldi r3, r3, 3
 ; CHECK-NEXT:    lxvrdx v2, r4, r3
 ; CHECK-NEXT:    blr
-;
-; CHECK-O0-LABEL: vec_xl_zext_dw:
-; CHECK-O0:       # %bb.0: # %entry
-; CHECK-O0-NEXT:    sldi r3, r3, 3
-; CHECK-O0-NEXT:    lxvrdx v2, r4, r3
-; CHECK-O0-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i64, i64* %__pointer, i64 %__offset
   %0 = load i64, i64* %add.ptr, align 8
@@ -319,13 +332,21 @@ entry:
 }
 
 define dso_local <1 x i128> @vec_xl_sext_b(i64 %offset, i8* %p) {
-; CHECK-LABEL: vec_xl_sext_b:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lbzx r3, r4, r3
-; CHECK-NEXT:    extsb r3, r3
-; CHECK-NEXT:    sradi r4, r3, 63
-; CHECK-NEXT:    mtvsrdd v2, r4, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xl_sext_b:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    lbzx r3, r4, r3
+; CHECK-LE-NEXT:    extsb r3, r3
+; CHECK-LE-NEXT:    sradi r4, r3, 63
+; CHECK-LE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xl_sext_b:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    lbzx r3, r4, r3
+; CHECK-BE-NEXT:    extsb r3, r3
+; CHECK-BE-NEXT:    sradi r4, r3, 63
+; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xl_sext_b:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -343,13 +364,21 @@ entry:
 }
 
 define dso_local <1 x i128> @vec_xl_sext_h(i64 %offset, i16* %p) {
-; CHECK-LABEL: vec_xl_sext_h:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sldi r3, r3, 1
-; CHECK-NEXT:    lhax r3, r4, r3
-; CHECK-NEXT:    sradi r4, r3, 63
-; CHECK-NEXT:    mtvsrdd v2, r4, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xl_sext_h:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    sldi r3, r3, 1
+; CHECK-LE-NEXT:    lhax r3, r4, r3
+; CHECK-LE-NEXT:    sradi r4, r3, 63
+; CHECK-LE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xl_sext_h:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    sldi r3, r3, 1
+; CHECK-BE-NEXT:    lhax r3, r4, r3
+; CHECK-BE-NEXT:    sradi r4, r3, 63
+; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xl_sext_h:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -367,13 +396,21 @@ entry:
 }
 
 define dso_local <1 x i128> @vec_xl_sext_w(i64 %offset, i32* %p) {
-; CHECK-LABEL: vec_xl_sext_w:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sldi r3, r3, 2
-; CHECK-NEXT:    lwax r3, r4, r3
-; CHECK-NEXT:    sradi r4, r3, 63
-; CHECK-NEXT:    mtvsrdd v2, r4, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xl_sext_w:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    sldi r3, r3, 2
+; CHECK-LE-NEXT:    lwax r3, r4, r3
+; CHECK-LE-NEXT:    sradi r4, r3, 63
+; CHECK-LE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xl_sext_w:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    sldi r3, r3, 2
+; CHECK-BE-NEXT:    lwax r3, r4, r3
+; CHECK-BE-NEXT:    sradi r4, r3, 63
+; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xl_sext_w:
 ; CHECK-O0:       # %bb.0: # %entry
@@ -391,13 +428,21 @@ entry:
 }
 
 define dso_local <1 x i128> @vec_xl_sext_d(i64 %offset, i64* %p) {
-; CHECK-LABEL: vec_xl_sext_d:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    sldi r3, r3, 3
-; CHECK-NEXT:    ldx r3, r4, r3
-; CHECK-NEXT:    sradi r4, r3, 63
-; CHECK-NEXT:    mtvsrdd v2, r4, r3
-; CHECK-NEXT:    blr
+; CHECK-LE-LABEL: vec_xl_sext_d:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    sldi r3, r3, 3
+; CHECK-LE-NEXT:    ldx r3, r4, r3
+; CHECK-LE-NEXT:    sradi r4, r3, 63
+; CHECK-LE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: vec_xl_sext_d:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    sldi r3, r3, 3
+; CHECK-BE-NEXT:    ldx r3, r4, r3
+; CHECK-BE-NEXT:    sradi r4, r3, 63
+; CHECK-BE-NEXT:    mtvsrdd v2, r4, r3
+; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-O0-LABEL: vec_xl_sext_d:
 ; CHECK-O0:       # %bb.0: # %entry
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
index 39e3e80f542cc..b4166bde22ab8 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
@@ -23,8 +23,8 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-NEXT:    mfcr r12
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stw r12, 8(r1)
-; CHECK-NEXT:    stdu r1, -80(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    stdu r1, -64(r1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset r29, -24
 ; CHECK-NEXT:    .cfi_offset r30, -16
@@ -32,32 +32,31 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-NEXT:    .cfi_offset cr3, 8
 ; CHECK-NEXT:    .cfi_offset cr4, 8
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    std r29, 56(r1) # 8-byte Folded Spill
-; CHECK-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r29, 40(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r30, 48(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    paddi r29, 0, .LJTI0_0@PCREL, 1
 ; CHECK-NEXT:    srwi r4, r3, 4
 ; CHECK-NEXT:    srwi r3, r3, 5
 ; CHECK-NEXT:    andi. r4, r4, 1
 ; CHECK-NEXT:    li r4, 0
-; CHECK-NEXT:    crmove 4*cr4+lt, gt
+; CHECK-NEXT:    crmove 4*cr2+gt, gt
 ; CHECK-NEXT:    andi. r3, r3, 1
-; CHECK-NEXT:    setnbc r3, gt
-; CHECK-NEXT:    stw r3, 52(r1)
+; CHECK-NEXT:    crmove 4*cr2+lt, gt
 ; CHECK-NEXT:    cmplwi cr3, r3, 336
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    sldi r30, r3, 2
 ; CHECK-NEXT:    b .LBB0_2
-; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_1: # %bb43
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    bl call_1@notoc
 ; CHECK-NEXT:    li r4, 0
-; CHECK-NEXT:    setnbc r3, 4*cr2+eq
+; CHECK-NEXT:    setnbc r3, 4*cr4+eq
 ; CHECK-NEXT:    stb r4, 0(r3)
 ; CHECK-NEXT:    li r4, 0
+; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_2: # %bb5
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    bc 12, 4*cr4+lt, .LBB0_31
+; CHECK-NEXT:    bc 12, 4*cr2+gt, .LBB0_31
 ; CHECK-NEXT:  # %bb.3: # %bb10
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    bgt cr3, .LBB0_5
@@ -66,7 +65,7 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-NEXT:    mr r3, r4
 ; CHECK-NEXT:    lwz r5, 0(r3)
 ; CHECK-NEXT:    rlwinm r4, r5, 0, 21, 22
-; CHECK-NEXT:    cmpwi cr2, r4, 512
+; CHECK-NEXT:    cmpwi cr4, r4, 512
 ; CHECK-NEXT:    lwax r4, r30, r29
 ; CHECK-NEXT:    add r4, r4, r29
 ; CHECK-NEXT:    mtctr r4
@@ -105,11 +104,11 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_12
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_13: # %bb47
+; CHECK-NEXT:  .LBB0_13: # %bb61
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_13
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_14: # %bb58
+; CHECK-NEXT:  .LBB0_14: # %bb47
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_14
 ; CHECK-NEXT:    .p2align 4
@@ -121,51 +120,51 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_16
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_17: # %bb23
+; CHECK-NEXT:  .LBB0_17: # %bb59
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_17
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_18: # %bb60
+; CHECK-NEXT:  .LBB0_18: # %bb46
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_18
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_19: # %bb59
+; CHECK-NEXT:  .LBB0_19: # %bb49
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_19
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_20: # %bb46
+; CHECK-NEXT:  .LBB0_20: # %bb57
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_20
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_21: # %bb49
+; CHECK-NEXT:  .LBB0_21: # %bb18
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_21
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_22: # %bb57
+; CHECK-NEXT:  .LBB0_22: # %bb58
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_22
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_23: # %bb56
+; CHECK-NEXT:  .LBB0_23: # %bb23
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_23
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_24: # %bb20
+; CHECK-NEXT:  .LBB0_24: # %bb60
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_24
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_25: # %bb18
+; CHECK-NEXT:  .LBB0_25: # %bb55
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_25
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_26: # %bb61
+; CHECK-NEXT:  .LBB0_26: # %bb62
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_26
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_27: # %bb55
+; CHECK-NEXT:  .LBB0_27: # %bb56
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_27
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_28: # %bb62
+; CHECK-NEXT:  .LBB0_28: # %bb20
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_28
 ; CHECK-NEXT:    .p2align 4
@@ -177,9 +176,9 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    b .LBB0_30
 ; CHECK-NEXT:  .LBB0_31: # %bb9
-; CHECK-NEXT:    ld r30, 64(r1) # 8-byte Folded Reload
-; CHECK-NEXT:    ld r29, 56(r1) # 8-byte Folded Reload
-; CHECK-NEXT:    addi r1, r1, 80
+; CHECK-NEXT:    ld r30, 48(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    ld r29, 40(r1) # 8-byte Folded Reload
+; CHECK-NEXT:    addi r1, r1, 64
 ; CHECK-NEXT:    ld r0, 16(r1)
 ; CHECK-NEXT:    lwz r12, 8(r1)
 ; CHECK-NEXT:    mtlr r0
@@ -188,29 +187,26 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-NEXT:    mtocrf 8, r12
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_32: # %bb29
-; CHECK-NEXT:    lwz r4, 52(r1)
-; CHECK-NEXT:    cmpwi cr4, r3, 0
-; CHECK-NEXT:    setnbc r30, 4*cr2+eq
-; CHECK-NEXT:    # implicit-def: $cr2lt
-; CHECK-NEXT:    mfocrf r3, 32
+; CHECK-NEXT:    mcrf cr0, cr4
 ; CHECK-NEXT:    cmpwi cr3, r5, 366
+; CHECK-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-NEXT:    li r29, 0
-; CHECK-NEXT:    rlwimi r3, r4, 24, 8, 8
-; CHECK-NEXT:    mtocrf 32, r3
+; CHECK-NEXT:    setnbc r30, eq
+; CHECK-NEXT:    bc 12, 4*cr2+lt, .LBB0_36
 ; CHECK-NEXT:    .p2align 5
-; CHECK-NEXT:  .LBB0_33: # %bb32
-; CHECK-NEXT:    #
-; CHECK-NEXT:    bc 4, 4*cr2+lt, .LBB0_35
-; CHECK-NEXT:  # %bb.34: # %bb33
-; CHECK-NEXT:    #
-; CHECK-NEXT:    stb r29, 0(r30)
-; CHECK-NEXT:  .LBB0_35: # %bb36
-; CHECK-NEXT:    #
-; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_33
-; CHECK-NEXT:  # %bb.36: # %bb39
-; CHECK-NEXT:    #
+; CHECK-NEXT:  .LBB0_33: # %bb36
+; CHECK-NEXT:    bc 12, 4*cr4+eq, .LBB0_35
+; CHECK-NEXT:  .LBB0_34: # %bb32
+; CHECK-NEXT:    bc 4, 4*cr2+lt, .LBB0_33
+; CHECK-NEXT:    b .LBB0_36
+; CHECK-NEXT:    .p2align 5
+; CHECK-NEXT:  .LBB0_35: # %bb39
 ; CHECK-NEXT:    bl call_2@notoc
-; CHECK-NEXT:    b .LBB0_33
+; CHECK-NEXT:    bc 4, 4*cr2+lt, .LBB0_33
+; CHECK-NEXT:  .LBB0_36: # %bb33
+; CHECK-NEXT:    stb r29, 0(r30)
+; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_34
+; CHECK-NEXT:    b .LBB0_35
 ;
 ; CHECK-BE-LABEL: P10_Spill_CR_GT:
 ; CHECK-BE:       # %bb.0: # %bb
@@ -218,8 +214,8 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-BE-NEXT:    mfcr r12
 ; CHECK-BE-NEXT:    std r0, 16(r1)
 ; CHECK-BE-NEXT:    stw r12, 8(r1)
-; CHECK-BE-NEXT:    stdu r1, -160(r1)
-; CHECK-BE-NEXT:    .cfi_def_cfa_offset 160
+; CHECK-BE-NEXT:    stdu r1, -144(r1)
+; CHECK-BE-NEXT:    .cfi_def_cfa_offset 144
 ; CHECK-BE-NEXT:    .cfi_offset lr, 16
 ; CHECK-BE-NEXT:    .cfi_offset r29, -24
 ; CHECK-BE-NEXT:    .cfi_offset r30, -16
@@ -227,34 +223,33 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    lwz r3, 0(r3)
-; CHECK-BE-NEXT:    std r29, 136(r1) # 8-byte Folded Spill
-; CHECK-BE-NEXT:    std r30, 144(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    std r29, 120(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    std r30, 128(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    srwi r4, r3, 4
 ; CHECK-BE-NEXT:    srwi r3, r3, 5
 ; CHECK-BE-NEXT:    andi. r4, r4, 1
 ; CHECK-BE-NEXT:    li r4, 0
-; CHECK-BE-NEXT:    crmove 4*cr4+lt, gt
+; CHECK-BE-NEXT:    crmove 4*cr2+gt, gt
 ; CHECK-BE-NEXT:    andi. r3, r3, 1
-; CHECK-BE-NEXT:    setnbc r3, gt
-; CHECK-BE-NEXT:    stw r3, 132(r1)
+; CHECK-BE-NEXT:    crmove 4*cr2+lt, gt
 ; CHECK-BE-NEXT:    cmplwi cr3, r3, 336
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    sldi r30, r3, 2
 ; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    ld r29, .LC0@toc@l(r3)
 ; CHECK-BE-NEXT:    b .LBB0_2
-; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_1: # %bb43
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    bl call_1
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    li r4, 0
-; CHECK-BE-NEXT:    setnbc r3, 4*cr2+eq
+; CHECK-BE-NEXT:    setnbc r3, 4*cr4+eq
 ; CHECK-BE-NEXT:    stb r4, 0(r3)
 ; CHECK-BE-NEXT:    li r4, 0
+; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_2: # %bb5
 ; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    bc 12, 4*cr4+lt, .LBB0_31
+; CHECK-BE-NEXT:    bc 12, 4*cr2+gt, .LBB0_31
 ; CHECK-BE-NEXT:  # %bb.3: # %bb10
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    bgt cr3, .LBB0_5
@@ -263,7 +258,7 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-BE-NEXT:    mr r3, r4
 ; CHECK-BE-NEXT:    lwz r5, 0(r3)
 ; CHECK-BE-NEXT:    rlwinm r4, r5, 0, 21, 22
-; CHECK-BE-NEXT:    cmpwi cr2, r4, 512
+; CHECK-BE-NEXT:    cmpwi cr4, r4, 512
 ; CHECK-BE-NEXT:    lwax r4, r30, r29
 ; CHECK-BE-NEXT:    add r4, r4, r29
 ; CHECK-BE-NEXT:    mtctr r4
@@ -302,11 +297,11 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_12
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_13: # %bb47
+; CHECK-BE-NEXT:  .LBB0_13: # %bb61
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_13
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_14: # %bb58
+; CHECK-BE-NEXT:  .LBB0_14: # %bb47
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_14
 ; CHECK-BE-NEXT:    .p2align 4
@@ -318,51 +313,51 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_16
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_17: # %bb23
+; CHECK-BE-NEXT:  .LBB0_17: # %bb59
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_17
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_18: # %bb60
+; CHECK-BE-NEXT:  .LBB0_18: # %bb46
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_18
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_19: # %bb59
+; CHECK-BE-NEXT:  .LBB0_19: # %bb49
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_19
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_20: # %bb46
+; CHECK-BE-NEXT:  .LBB0_20: # %bb57
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_20
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_21: # %bb49
+; CHECK-BE-NEXT:  .LBB0_21: # %bb18
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_21
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_22: # %bb57
+; CHECK-BE-NEXT:  .LBB0_22: # %bb58
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_22
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_23: # %bb56
+; CHECK-BE-NEXT:  .LBB0_23: # %bb23
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_23
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_24: # %bb20
+; CHECK-BE-NEXT:  .LBB0_24: # %bb60
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_24
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_25: # %bb18
+; CHECK-BE-NEXT:  .LBB0_25: # %bb55
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_25
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_26: # %bb61
+; CHECK-BE-NEXT:  .LBB0_26: # %bb62
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_26
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_27: # %bb55
+; CHECK-BE-NEXT:  .LBB0_27: # %bb56
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_27
 ; CHECK-BE-NEXT:    .p2align 4
-; CHECK-BE-NEXT:  .LBB0_28: # %bb62
+; CHECK-BE-NEXT:  .LBB0_28: # %bb20
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_28
 ; CHECK-BE-NEXT:    .p2align 4
@@ -374,9 +369,9 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-BE-NEXT:    #
 ; CHECK-BE-NEXT:    b .LBB0_30
 ; CHECK-BE-NEXT:  .LBB0_31: # %bb9
-; CHECK-BE-NEXT:    ld r30, 144(r1) # 8-byte Folded Reload
-; CHECK-BE-NEXT:    ld r29, 136(r1) # 8-byte Folded Reload
-; CHECK-BE-NEXT:    addi r1, r1, 160
+; CHECK-BE-NEXT:    ld r30, 128(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    ld r29, 120(r1) # 8-byte Folded Reload
+; CHECK-BE-NEXT:    addi r1, r1, 144
 ; CHECK-BE-NEXT:    ld r0, 16(r1)
 ; CHECK-BE-NEXT:    lwz r12, 8(r1)
 ; CHECK-BE-NEXT:    mtlr r0
@@ -385,30 +380,27 @@ define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-BE-NEXT:    mtocrf 8, r12
 ; CHECK-BE-NEXT:    blr
 ; CHECK-BE-NEXT:  .LBB0_32: # %bb29
-; CHECK-BE-NEXT:    lwz r4, 132(r1)
-; CHECK-BE-NEXT:    cmpwi cr4, r3, 0
-; CHECK-BE-NEXT:    setnbc r30, 4*cr2+eq
-; CHECK-BE-NEXT:    # implicit-def: $cr2lt
-; CHECK-BE-NEXT:    mfocrf r3, 32
+; CHECK-BE-NEXT:    mcrf cr0, cr4
 ; CHECK-BE-NEXT:    cmpwi cr3, r5, 366
+; CHECK-BE-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-BE-NEXT:    li r29, 0
-; CHECK-BE-NEXT:    rlwimi r3, r4, 24, 8, 8
-; CHECK-BE-NEXT:    mtocrf 32, r3
-; CHECK-BE-NEXT:    .p2align 5
-; CHECK-BE-NEXT:  .LBB0_33: # %bb32
-; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    bc 4, 4*cr2+lt, .LBB0_35
-; CHECK-BE-NEXT:  # %bb.34: # %bb33
-; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    stb r29, 0(r30)
-; CHECK-BE-NEXT:  .LBB0_35: # %bb36
-; CHECK-BE-NEXT:    #
-; CHECK-BE-NEXT:    bc 4, 4*cr4+eq, .LBB0_33
-; CHECK-BE-NEXT:  # %bb.36: # %bb39
-; CHECK-BE-NEXT:    #
+; CHECK-BE-NEXT:    setnbc r30, eq
+; CHECK-BE-NEXT:    bc 12, 4*cr2+lt, .LBB0_36
+; CHECK-BE-NEXT:    .p2align 4
+; CHECK-BE-NEXT:  .LBB0_33: # %bb36
+; CHECK-BE-NEXT:    bc 12, 4*cr4+eq, .LBB0_35
+; CHECK-BE-NEXT:  .LBB0_34: # %bb32
+; CHECK-BE-NEXT:    bc 4, 4*cr2+lt, .LBB0_33
+; CHECK-BE-NEXT:    b .LBB0_36
+; CHECK-BE-NEXT:    .p2align 4
+; CHECK-BE-NEXT:  .LBB0_35: # %bb39
 ; CHECK-BE-NEXT:    bl call_2
 ; CHECK-BE-NEXT:    nop
-; CHECK-BE-NEXT:    b .LBB0_33
+; CHECK-BE-NEXT:    bc 4, 4*cr2+lt, .LBB0_33
+; CHECK-BE-NEXT:  .LBB0_36: # %bb33
+; CHECK-BE-NEXT:    stb r29, 0(r30)
+; CHECK-BE-NEXT:    bc 4, 4*cr4+eq, .LBB0_34
+; CHECK-BE-NEXT:    b .LBB0_35
 bb:
   %tmp = load i32, i32* undef, align 8
   %tmp1 = and i32 %tmp, 16
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
index 04f63a302c345..12a8a76c85e64 100644
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crun.ll
@@ -105,8 +105,8 @@ define dso_local void @P10_Spill_CR_UN(%2* %arg, %1* %arg1, i32 %arg2) local_unn
 ; CHECK-NEXT:    paddi r4, 0, global_4@PCREL, 1
 ; CHECK-NEXT:    stw r3, 176(r1)
 ; CHECK-NEXT:    pld r3, global_3@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel:
-; CHECK-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; CHECK-NEXT:  .Lpcrel0:
+; CHECK-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; CHECK-NEXT:    ld r12, 0(r3)
 ; CHECK-NEXT:    mtctr r12
 ; CHECK-NEXT:    bctrl
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll
index 8fa86ef50ea57..1eb48991db708 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll
@@ -67,8 +67,8 @@ define dso_local signext i32 @DirectCallLocal2(i32 signext %a, i32 signext %b) l
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    bl localCall@notoc
 ; CHECK-S-NEXT:    pld r4, externGlobalVar@got@pcrel(0), 1
-; CHECK-S-NEXT: .Lpcrel:
-; CHECK-S-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; CHECK-S-NEXT: .Lpcrel0:
+; CHECK-S-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    mullw r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
@@ -152,8 +152,8 @@ define dso_local signext i32 @DirectCallExtern2(i32 signext %a, i32 signext %b)
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    bl externCall@notoc
 ; CHECK-S-NEXT:    pld r4, externGlobalVar@got@pcrel(0), 1
-; CHECK-S-NEXT:  .Lpcrel0:
-; CHECK-S-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
+; CHECK-S-NEXT:  .Lpcrel1:
+; CHECK-S-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    mullw r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
@@ -216,8 +216,8 @@ define dso_local signext i32 @TailCallLocal2(i32 signext %a) local_unnamed_addr
 ; CHECK-S:         .localentry     TailCallLocal2
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S:         pld r4, externGlobalVar@got@pcrel(0), 1
-; CHECK-S-NEXT:  .Lpcrel1:
-; CHECK-S-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
+; CHECK-S-NEXT:  .Lpcrel2:
+; CHECK-S-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    add r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
@@ -260,8 +260,8 @@ define dso_local signext i32 @TailCallExtern2(i32 signext %a) local_unnamed_addr
 ; CHECK-S:         .localentry     TailCallExtern2
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S:         pld r4, externGlobalVar@got@pcrel(0), 1
-; CHECK-S-NEXT:  .Lpcrel2:
-; CHECK-S-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
+; CHECK-S-NEXT:  .Lpcrel3:
+; CHECK-S-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    add r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
@@ -327,8 +327,8 @@ define dso_local signext i32 @IndirectCall2(i32 signext %a, i32 signext %b) loca
 ; CHECK-S-NEXT:    mtctr r12
 ; CHECK-S-NEXT:    bctrl
 ; CHECK-S-NEXT:    pld r4, externGlobalVar@got@pcrel(0), 1
-; CHECK-S-NEXT:  .Lpcrel3:
-; CHECK-S-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
+; CHECK-S-NEXT:  .Lpcrel4:
+; CHECK-S-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
 ; CHECK-S-NEXT:    lwz r4, 0(r4)
 ; CHECK-S-NEXT:    mullw r3, r4, r3
 ; CHECK-S-NEXT:    extsw r3, r3
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll b/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
index 4d61b66d3bb77..7ade41ced3538 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-got-indirect.ll
@@ -23,16 +23,16 @@ define dso_local signext i32 @ReadGlobalVarChar() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarChar:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valChar@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel:
-; LE-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; LE-NEXT:  .Lpcrel0:
+; LE-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; LE-NEXT:    lbz r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarChar:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valChar@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel:
-; BE-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; BE-NEXT:  .Lpcrel0:
+; BE-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; BE-NEXT:    lbz r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
@@ -64,16 +64,16 @@ define dso_local signext i32 @ReadGlobalVarShort() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarShort:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valShort@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel0:
-; LE-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
+; LE-NEXT:  .Lpcrel1:
+; LE-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
 ; LE-NEXT:    lha r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarShort:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valShort@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel0:
-; BE-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
+; BE-NEXT:  .Lpcrel1:
+; BE-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
 ; BE-NEXT:    lha r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
@@ -105,16 +105,16 @@ define dso_local signext i32 @ReadGlobalVarInt() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarInt:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valInt@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel1:
-; LE-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
+; LE-NEXT:  .Lpcrel2:
+; LE-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
 ; LE-NEXT:    lwa r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarInt:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valInt@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel1:
-; BE-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
+; BE-NEXT:  .Lpcrel2:
+; BE-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
 ; BE-NEXT:    lwa r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
@@ -145,16 +145,16 @@ define dso_local signext i32 @ReadGlobalVarUnsigned() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarUnsigned:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valUnsigned@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel2:
-; LE-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
+; LE-NEXT:  .Lpcrel3:
+; LE-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
 ; LE-NEXT:    lwa r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarUnsigned:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valUnsigned@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel2:
-; BE-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
+; BE-NEXT:  .Lpcrel3:
+; BE-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
 ; BE-NEXT:    lwa r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
@@ -185,16 +185,16 @@ define dso_local signext i32 @ReadGlobalVarLong() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalVarLong:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, valLong@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel3:
-; LE-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
+; LE-NEXT:  .Lpcrel4:
+; LE-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
 ; LE-NEXT:    lwa r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalVarLong:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, valLong@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel3:
-; BE-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
+; BE-NEXT:  .Lpcrel4:
+; BE-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
 ; BE-NEXT:    lwa r3, 4(r3)
 ; BE-NEXT:    blr
 entry:
@@ -226,16 +226,16 @@ define dso_local i32* @ReadGlobalPtr() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalPtr:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, ptr@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel4:
-; LE-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
+; LE-NEXT:  .Lpcrel5:
+; LE-NEXT:    .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
 ; LE-NEXT:    ld r3, 0(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalPtr:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, ptr@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel4:
-; BE-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
+; BE-NEXT:  .Lpcrel5:
+; BE-NEXT:    .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
 ; BE-NEXT:    ld r3, 0(r3)
 ; BE-NEXT:    blr
 entry:
@@ -247,9 +247,9 @@ define dso_local void @WriteGlobalPtr() local_unnamed_addr  {
 ; LE-LABEL: WriteGlobalPtr:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, ptr@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel5:
+; LE-NEXT:  .Lpcrel6:
 ; LE-NEXT:    li r4, 3
-; LE-NEXT:    .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
+; LE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
 ; LE-NEXT:    ld r3, 0(r3)
 ; LE-NEXT:    stw r4, 0(r3)
 ; LE-NEXT:    blr
@@ -257,9 +257,9 @@ define dso_local void @WriteGlobalPtr() local_unnamed_addr  {
 ; BE-LABEL: WriteGlobalPtr:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, ptr@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel5:
+; BE-NEXT:  .Lpcrel6:
 ; BE-NEXT:    li r4, 3
-; BE-NEXT:    .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
+; BE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
 ; BE-NEXT:    ld r3, 0(r3)
 ; BE-NEXT:    stw r4, 0(r3)
 ; BE-NEXT:    blr
@@ -287,16 +287,16 @@ define dso_local signext i32 @ReadGlobalArray() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalArray:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, array@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel6:
-; LE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
+; LE-NEXT:  .Lpcrel7:
+; LE-NEXT:    .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8)
 ; LE-NEXT:    lwa r3, 12(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalArray:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, array@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel6:
-; BE-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
+; BE-NEXT:  .Lpcrel7:
+; BE-NEXT:    .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8)
 ; BE-NEXT:    lwa r3, 12(r3)
 ; BE-NEXT:    blr
 entry:
@@ -327,16 +327,16 @@ define dso_local signext i32 @ReadGlobalStruct() local_unnamed_addr  {
 ; LE-LABEL: ReadGlobalStruct:
 ; LE:       # %bb.0: # %entry
 ; LE-NEXT:    pld r3, structure@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel7:
-; LE-NEXT:    .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8)
+; LE-NEXT:  .Lpcrel8:
+; LE-NEXT:    .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
 ; LE-NEXT:    lwa r3, 4(r3)
 ; LE-NEXT:    blr
 ;
 ; BE-LABEL: ReadGlobalStruct:
 ; BE:       # %bb.0: # %entry
 ; BE-NEXT:    pld r3, structure@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel7:
-; BE-NEXT:    .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8)
+; BE-NEXT:  .Lpcrel8:
+; BE-NEXT:    .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
 ; BE-NEXT:    lwa r3, 4(r3)
 ; BE-NEXT:    blr
 entry:
@@ -368,8 +368,8 @@ define dso_local void @ReadFuncPtr() local_unnamed_addr  {
 ; LE:         .localentry ReadFuncPtr, 1
 ; LE-NEXT:  # %bb.0: # %entry
 ; LE-NEXT:    pld r3, ptrfunc@got@pcrel(0), 1
-; LE-NEXT:  .Lpcrel8:
-; LE-NEXT:    .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
+; LE-NEXT:  .Lpcrel9:
+; LE-NEXT:    .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
 ; LE-NEXT:    ld r12, 0(r3)
 ; LE-NEXT:    mtctr r12
 ; LE-NEXT:    bctr
@@ -379,8 +379,8 @@ define dso_local void @ReadFuncPtr() local_unnamed_addr  {
 ; BE:         .localentry ReadFuncPtr, 1
 ; BE-NEXT:  # %bb.0: # %entry
 ; BE-NEXT:    pld r3, ptrfunc@got@pcrel(0), 1
-; BE-NEXT:  .Lpcrel8:
-; BE-NEXT:    .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
+; BE-NEXT:  .Lpcrel9:
+; BE-NEXT:    .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
 ; BE-NEXT:    ld r12, 0(r3)
 ; BE-NEXT:    mtctr r12
 ; BE-NEXT:    bctr
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll
index 8e470b6f8ccba..564bd29f181a3 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt-option.ll
@@ -15,16 +15,16 @@ define dso_local i8 @Read8() local_unnamed_addr {
 ; DEFAULT-LABEL: Read8:
 ; DEFAULT:       # %bb.0: # %entry
 ; DEFAULT-NEXT:    pld r3, input8@got@pcrel(0), 1
-; DEFAULT-NEXT:  .Lpcrel:
-; DEFAULT-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; DEFAULT-NEXT:  .Lpcrel0:
+; DEFAULT-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; DEFAULT-NEXT:    lbz r3, 0(r3)
 ; DEFAULT-NEXT:    blr
 ;
 ; ON-LABEL: Read8:
 ; ON:       # %bb.0: # %entry
 ; ON-NEXT:    pld r3, input8@got@pcrel(0), 1
-; ON-NEXT:  .Lpcrel:
-; ON-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; ON-NEXT:  .Lpcrel0:
+; ON-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; ON-NEXT:    lbz r3, 0(r3)
 ; ON-NEXT:    blr
 ;
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll
index e878e74399115..604d57aa7f853 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-linkeropt.ll
@@ -38,9 +38,9 @@ define dso_local void @ReadWrite8() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadWrite8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, input8@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel:
+; CHECK-NEXT:  .Lpcrel0:
 ; CHECK-NEXT:    pld r4, output8@got@pcrel(0), 1
-; CHECK-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; CHECK-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; CHECK-NEXT:    lbz r3, 0(r3)
 ; In this test the stb r3, 0(r4) cannot be optimized because it
 ; uses the register r3 and that register is defined by lbz r3, 0(r3)
@@ -57,9 +57,9 @@ define dso_local void @ReadWrite16() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadWrite16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, input16@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel0:
+; CHECK-NEXT:  .Lpcrel1:
 ; CHECK-NEXT:    pld r4, output16@got@pcrel(0), 1
-; CHECK-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
+; CHECK-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
 ; CHECK-NEXT:    lhz r3, 0(r3)
 ; In this test the sth r3, 0(r4) cannot be optimized because it
 ; uses the register r3 and that register is defined by lhz r3, 0(r3)
@@ -76,9 +76,9 @@ define dso_local void @ReadWrite32() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadWrite32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, input32@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel1:
+; CHECK-NEXT:  .Lpcrel2:
 ; CHECK-NEXT:    pld r4, output32@got@pcrel(0), 1
-; CHECK-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
+; CHECK-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
 ; CHECK-NEXT:    lwz r3, 0(r3)
 ; CHECK-NEXT:    stw r3, 0(r4)
 ; CHECK-NEXT:    blr
@@ -92,9 +92,9 @@ define dso_local void @ReadWrite64() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadWrite64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, input64@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel2:
+; CHECK-NEXT:  .Lpcrel3:
 ; CHECK-NEXT:    pld r4, output64@got@pcrel(0), 1
-; CHECK-NEXT:    .reloc .Lpcrel2-8,R_PPC64_PCREL_OPT,.-(.Lpcrel2-8)
+; CHECK-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
@@ -124,9 +124,9 @@ define dso_local void @ReadWritef32() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadWritef32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, inputf32@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel3:
+; CHECK-NEXT:  .Lpcrel4:
 ; CHECK-NEXT:    xxspltidp vs1, 1078103900
-; CHECK-NEXT:    .reloc .Lpcrel3-8,R_PPC64_PCREL_OPT,.-(.Lpcrel3-8)
+; CHECK-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
 ; CHECK-NEXT:    lfs f0, 0(r3)
 ; CHECK-NEXT:    pld r3, outputf32@got@pcrel(0), 1
 ; CHECK-NEXT:    xsaddsp f0, f0, f1
@@ -143,9 +143,9 @@ define dso_local void @ReadWritef64() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadWritef64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, inputf64@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel4:
+; CHECK-NEXT:  .Lpcrel5:
 ; CHECK-NEXT:    plfd f1, .LCPI6_0@PCREL(0), 1
-; CHECK-NEXT:    .reloc .Lpcrel4-8,R_PPC64_PCREL_OPT,.-(.Lpcrel4-8)
+; CHECK-NEXT:    .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
 ; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    pld r3, outputf64@got@pcrel(0), 1
 ; CHECK-NEXT:    xsadddp f0, f0, f1
@@ -196,9 +196,9 @@ define dso_local void @ReadWriteArray() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadWriteArray:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, ArrayIn@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel5:
+; CHECK-NEXT:  .Lpcrel6:
 ; CHECK-NEXT:    pld r4, ArrayOut@got@pcrel(0), 1
-; CHECK-NEXT:    .reloc .Lpcrel5-8,R_PPC64_PCREL_OPT,.-(.Lpcrel5-8)
+; CHECK-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
 ; CHECK-NEXT:    lwz r3, 28(r3)
 ; CHECK-NEXT:    addi r3, r3, 42
 ; CHECK-NEXT:    stw r3, 8(r4)
@@ -229,12 +229,12 @@ define dso_local void @ReadWriteIntPtr() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadWriteIntPtr:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, IntPtrIn@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel6:
-; CHECK-NEXT:    pld r4, IntPtrOut@got@pcrel(0), 1
 ; CHECK-NEXT:  .Lpcrel7:
-; CHECK-NEXT:    .reloc .Lpcrel6-8,R_PPC64_PCREL_OPT,.-(.Lpcrel6-8)
-; CHECK-NEXT:    ld r3, 0(r3)
+; CHECK-NEXT:    pld r4, IntPtrOut@got@pcrel(0), 1
+; CHECK-NEXT:  .Lpcrel8:
 ; CHECK-NEXT:    .reloc .Lpcrel7-8,R_PPC64_PCREL_OPT,.-(.Lpcrel7-8)
+; CHECK-NEXT:    ld r3, 0(r3)
+; CHECK-NEXT:    .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
 ; CHECK-NEXT:    ld r4, 0(r4)
 ; CHECK-NEXT:    lwz r5, 216(r3)
 ; CHECK-NEXT:    lwz r3, 48(r3)
@@ -258,9 +258,9 @@ define dso_local void @ReadWriteFuncPtr() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadWriteFuncPtr:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, FuncPtrIn@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel8:
+; CHECK-NEXT:  .Lpcrel9:
 ; CHECK-NEXT:    pld r4, FuncPtrOut@got@pcrel(0), 1
-; CHECK-NEXT:    .reloc .Lpcrel8-8,R_PPC64_PCREL_OPT,.-(.Lpcrel8-8)
+; CHECK-NEXT:    .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    std r3, 0(r4)
 ; CHECK-NEXT:    blr
@@ -289,8 +289,8 @@ define dso_local void @FuncPtrCall() local_unnamed_addr #0 {
 ; CHECK:         .localentry FuncPtrCall, 1
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, FuncPtrIn@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel9:
-; CHECK-NEXT:    .reloc .Lpcrel9-8,R_PPC64_PCREL_OPT,.-(.Lpcrel9-8)
+; CHECK-NEXT:  .Lpcrel10:
+; CHECK-NEXT:    .reloc .Lpcrel10-8,R_PPC64_PCREL_OPT,.-(.Lpcrel10-8)
 ; CHECK-NEXT:    ld r12, 0(r3)
 ; CHECK-NEXT:    mtctr r12
 ; CHECK-NEXT:    bctr
@@ -305,8 +305,8 @@ define dso_local signext i32 @ReadVecElement() local_unnamed_addr #0 {
 ; CHECK-LABEL: ReadVecElement:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, inputVi32@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel10:
-; CHECK-NEXT:    .reloc .Lpcrel10-8,R_PPC64_PCREL_OPT,.-(.Lpcrel10-8)
+; CHECK-NEXT:  .Lpcrel11:
+; CHECK-NEXT:    .reloc .Lpcrel11-8,R_PPC64_PCREL_OPT,.-(.Lpcrel11-8)
 ; CHECK-NEXT:    lwa r3, 4(r3)
 ; CHECK-NEXT:    blr
 entry:
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll b/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll
index 44d3f7a50e9bf..98ea41f7bb26f 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll
@@ -50,8 +50,8 @@ define dso_local signext i32 @getElementExtern4() local_unnamed_addr {
 ; CHECK-S-LABEL: getElementExtern4:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    pld r3, array1@got@pcrel(0), 1
-; CHECK-S-NEXT:  .Lpcrel:
-; CHECK-S-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; CHECK-S-NEXT:  .Lpcrel0:
+; CHECK-S-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; CHECK-S-NEXT:    lwa r3, 16(r3)
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementExtern4>:
@@ -69,8 +69,8 @@ define dso_local signext i32 @getElementExternNegative() local_unnamed_addr {
 ; CHECK-S-LABEL: getElementExternNegative:
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    pld r3, array1@got@pcrel(0), 1
-; CHECK-S-NEXT:  .Lpcrel0:
-; CHECK-S-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
+; CHECK-S-NEXT:  .Lpcrel1:
+; CHECK-S-NEXT:    .reloc .Lpcrel1-8,R_PPC64_PCREL_OPT,.-(.Lpcrel1-8)
 ; CHECK-S-NEXT:    lwa r3, -4(r3)
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementExternNegative>:
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll b/llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll
index 1340197b3ccba..583e7950b6d53 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll
@@ -51,8 +51,8 @@ define dso_local void @TailCallExtrnFuncPtr() local_unnamed_addr {
 ; CHECK:         .localentry TailCallExtrnFuncPtr, 1
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    pld r3, Func@got@pcrel(0), 1
-; CHECK-NEXT:  .Lpcrel:
-; CHECK-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; CHECK-NEXT:  .Lpcrel0:
+; CHECK-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; CHECK-NEXT:    ld r12, 0(r3)
 ; CHECK-NEXT:    mtctr r12
 ; CHECK-NEXT:    bctr
diff --git a/llvm/test/CodeGen/PowerPC/pcrel.ll b/llvm/test/CodeGen/PowerPC/pcrel.ll
index 55783180cfaca..1d3d96a92904f 100644
--- a/llvm/test/CodeGen/PowerPC/pcrel.ll
+++ b/llvm/test/CodeGen/PowerPC/pcrel.ll
@@ -41,8 +41,8 @@ define dso_local signext i32 @ReadGlobalVarInt() local_unnamed_addr  {
 ; CHECK-S-LABEL: ReadGlobalVarInt
 ; CHECK-S:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    pld r3, valIntGlob@got@pcrel(0), 1
-; CHECK-S-NEXT: .Lpcrel:
-; CHECK-S-NEXT:    .reloc .Lpcrel-8,R_PPC64_PCREL_OPT,.-(.Lpcrel-8)
+; CHECK-S-NEXT: .Lpcrel0:
+; CHECK-S-NEXT:    .reloc .Lpcrel0-8,R_PPC64_PCREL_OPT,.-(.Lpcrel0-8)
 ; CHECK-S-NEXT:    lwa r3, 0(r3)
 ; CHECK-S-NEXT:    blr
 
diff --git a/llvm/test/CodeGen/PowerPC/pr36292.ll b/llvm/test/CodeGen/PowerPC/pr36292.ll
index a859121bb505c..883d26b669088 100644
--- a/llvm/test/CodeGen/PowerPC/pr36292.ll
+++ b/llvm/test/CodeGen/PowerPC/pr36292.ll
@@ -15,7 +15,8 @@ define void @test() nounwind comdat {
 ; CHECK-NEXT:    ld 29, 0(3)
 ; CHECK-NEXT:    ld 30, 32(1)
 ; CHECK-NEXT:    cmpld 30, 29
-; CHECK-NEXT:    bge 0, .LBB0_2
+; CHECK-NEXT:    bge- 0, .LBB0_2
+; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_1: # %bounds.ok
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    lfsx 2, 0, 3
@@ -25,7 +26,7 @@ define void @test() nounwind comdat {
 ; CHECK-NEXT:    addi 30, 30, 1
 ; CHECK-NEXT:    stfsx 1, 0, 3
 ; CHECK-NEXT:    cmpld 30, 29
-; CHECK-NEXT:    blt 0, .LBB0_1
+; CHECK-NEXT:    blt+ 0, .LBB0_1
 ; CHECK-NEXT:  .LBB0_2: # %bounds.fail
 ; CHECK-NEXT:    std 30, 32(1)
   %pos = alloca i64, align 8
diff --git a/llvm/test/CodeGen/PowerPC/pr46759.ll b/llvm/test/CodeGen/PowerPC/pr46759.ll
index 716e050cdbeef..33b44b720b6e1 100644
--- a/llvm/test/CodeGen/PowerPC/pr46759.ll
+++ b/llvm/test/CodeGen/PowerPC/pr46759.ll
@@ -61,7 +61,7 @@ define void @foo(i32 %vla_size) #0 {
 ; CHECK-LE-NEXT:  .LBB0_6: # %entry
 ; CHECK-LE-NEXT:    addi r3, r1, 2048
 ; CHECK-LE-NEXT:    lbz r3, 0(r3)
-; CHECK-LE-NEXT:    ld r1, 0(r1)
+; CHECK-LE-NEXT:    mr r1, r30
 ; CHECK-LE-NEXT:    ld r31, -8(r1)
 ; CHECK-LE-NEXT:    ld r30, -16(r1)
 ; CHECK-LE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
index 6605a1fd78cc4..be4e3908944aa 100644
--- a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
+++ b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
@@ -44,6 +44,7 @@ define void @print_res() nounwind {
 ; CHECK-NEXT:    addi 8, 8, -1
 ; CHECK-NEXT:    lbz 5, 0(5)
 ; CHECK-NEXT:    bdz .LBB0_4
+; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    clrldi 10, 8, 32
diff --git a/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll b/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll
index e4d5fa216b453..6443059c97046 100644
--- a/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll
@@ -544,7 +544,7 @@ define i32 @f8(i64 %i) local_unnamed_addr #0 {
 ; CHECK-LE-NEXT:    li r5, 1
 ; CHECK-LE-NEXT:    stwx r5, r4, r3
 ; CHECK-LE-NEXT:    lwz r3, 64(r1)
-; CHECK-LE-NEXT:    ld r1, 0(r1)
+; CHECK-LE-NEXT:    mr r1, r30
 ; CHECK-LE-NEXT:    ld r30, -16(r1)
 ; CHECK-LE-NEXT:    blr
 ;
@@ -562,7 +562,7 @@ define i32 @f8(i64 %i) local_unnamed_addr #0 {
 ; CHECK-BE-NEXT:    sldi r3, r3, 2
 ; CHECK-BE-NEXT:    stwx r5, r4, r3
 ; CHECK-BE-NEXT:    lwz r3, 64(r1)
-; CHECK-BE-NEXT:    ld r1, 0(r1)
+; CHECK-BE-NEXT:    mr r1, r30
 ; CHECK-BE-NEXT:    ld r30, -16(r1)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -631,7 +631,7 @@ define i32 @f9(i64 %i) local_unnamed_addr #0 {
 ; CHECK-LE-NEXT:    li r5, 1
 ; CHECK-LE-NEXT:    stwx r5, r4, r3
 ; CHECK-LE-NEXT:    lwz r3, 2048(r1)
-; CHECK-LE-NEXT:    ld r1, 0(r1)
+; CHECK-LE-NEXT:    mr r1, r30
 ; CHECK-LE-NEXT:    ld r30, -16(r1)
 ; CHECK-LE-NEXT:    blr
 ;
@@ -669,7 +669,7 @@ define i32 @f9(i64 %i) local_unnamed_addr #0 {
 ; CHECK-BE-NEXT:    sldi r3, r3, 2
 ; CHECK-BE-NEXT:    stwx r5, r4, r3
 ; CHECK-BE-NEXT:    lwz r3, 2048(r1)
-; CHECK-BE-NEXT:    ld r1, 0(r1)
+; CHECK-BE-NEXT:    mr r1, r30
 ; CHECK-BE-NEXT:    ld r30, -16(r1)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -743,7 +743,7 @@ define i32 @f10(i64 %i) local_unnamed_addr #0 {
 ; CHECK-LE-NEXT:    li r5, 1
 ; CHECK-LE-NEXT:    stwx r5, r4, r3
 ; CHECK-LE-NEXT:    lwz r3, 1024(r1)
-; CHECK-LE-NEXT:    ld r1, 0(r1)
+; CHECK-LE-NEXT:    mr r1, r30
 ; CHECK-LE-NEXT:    ld r30, -16(r1)
 ; CHECK-LE-NEXT:    blr
 ;
@@ -780,7 +780,7 @@ define i32 @f10(i64 %i) local_unnamed_addr #0 {
 ; CHECK-BE-NEXT:    sldi r3, r3, 2
 ; CHECK-BE-NEXT:    stwx r5, r4, r3
 ; CHECK-BE-NEXT:    lwz r3, 1024(r1)
-; CHECK-BE-NEXT:    ld r1, 0(r1)
+; CHECK-BE-NEXT:    mr r1, r30
 ; CHECK-BE-NEXT:    ld r30, -16(r1)
 ; CHECK-BE-NEXT:    blr
 ;
@@ -884,7 +884,7 @@ define void @f11(i32 %vla_size, i64 %i) #0 {
 ; CHECK-LE-NEXT:  .LBB11_8:
 ; CHECK-LE-NEXT:    addi r3, r1, -32768
 ; CHECK-LE-NEXT:    lbz r3, 0(r3)
-; CHECK-LE-NEXT:    ld r1, 0(r1)
+; CHECK-LE-NEXT:    mr r1, r30
 ; CHECK-LE-NEXT:    ld r31, -8(r1)
 ; CHECK-LE-NEXT:    ld r30, -16(r1)
 ; CHECK-LE-NEXT:    blr
@@ -954,7 +954,7 @@ define void @f11(i32 %vla_size, i64 %i) #0 {
 ; CHECK-BE-NEXT:  .LBB11_8:
 ; CHECK-BE-NEXT:    addi r3, r1, -32768
 ; CHECK-BE-NEXT:    lbz r3, 0(r3)
-; CHECK-BE-NEXT:    ld r1, 0(r1)
+; CHECK-BE-NEXT:    mr r1, r30
 ; CHECK-BE-NEXT:    ld r31, -8(r1)
 ; CHECK-BE-NEXT:    ld r30, -16(r1)
 ; CHECK-BE-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/stack-realign.ll b/llvm/test/CodeGen/PowerPC/stack-realign.ll
index abb608797f072..8638592ab8b8e 100644
--- a/llvm/test/CodeGen/PowerPC/stack-realign.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-realign.ll
@@ -43,7 +43,7 @@ entry:
 
 ; CHECK: std 3, 48(30)
 
-; CHECK: ld 1, 0(1)
+; CHECK: mr 1, 30
 ; CHECK-DAG: ld [[SR:[0-9]+]], 16(1)
 ; CHECK-DAG: ld 30, -16(1)
 ; CHECK-DAG: mtlr [[SR]]
@@ -69,7 +69,7 @@ entry:
 
 ; CHECK-FP: std 3, 48(30)
 
-; CHECK-FP: ld 1, 0(1)
+; CHECK-FP: mr 1, 30
 ; CHECK-FP-DAG: ld [[SR:[0-9]+]], 16(1)
 ; CHECK-FP-DAG: ld 31, -8(1)
 ; CHECK-FP-DAG: ld 30, -16(1)
diff --git a/llvm/test/CodeGen/PowerPC/store-rightmost-vector-elt.ll b/llvm/test/CodeGen/PowerPC/store-rightmost-vector-elt.ll
new file mode 100644
index 0000000000000..5fbcafecfb3d2
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/store-rightmost-vector-elt.ll
@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
+; RUN:     < %s | FileCheck %s --check-prefix=CHECK-LE
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
+; RUN:     < %s | FileCheck %s --check-prefix=CHECK-BE
+
+define void @test1(<4 x i32> %A, i32* %a) {
+; CHECK-LE-LABEL: test1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    stxvrwx v2, 0, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: test1:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    stfiwx f0, 0, r5
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <4 x i32> %A, i32 0
+  store i32 %vecext, i32* %a, align 4
+  ret void
+}
+
+define void @test2(<4 x float> %A, float* %a) {
+; CHECK-LE-LABEL: test2:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    stxvrwx v2, 0, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: test2:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; CHECK-BE-NEXT:    stfiwx f0, 0, r5
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <4 x float> %A, i32 0
+  store float %vecext, float* %a, align 4
+  ret void
+}
+
+define void @test3(<2 x double> %A, double* %a) {
+; CHECK-LE-LABEL: test3:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    stxvrdx v2, 0, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: test3:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    stxsd v2, 0(r5)
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <2 x double> %A, i32 0
+  store double %vecext, double* %a, align 8
+  ret void
+}
+
+define void @test4(<2 x i64> %A, i64* %a) {
+; CHECK-LE-LABEL: test4:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    stxvrdx v2, 0, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: test4:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    stxsd v2, 0(r5)
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <2 x i64> %A, i32 0
+  store i64 %vecext, i64* %a, align 8
+  ret void
+}
+
+define void @test5(<8 x i16> %A, i16* %a) {
+; CHECK-LE-LABEL: test5:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    stxvrhx v2, 0, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: test5:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 10
+; CHECK-BE-NEXT:    stxsihx v2, 0, r5
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <8 x i16> %A, i32 0
+  store i16 %vecext, i16* %a, align 2
+  ret void
+}
+
+define void @test6(<16 x i8> %A, i8* %a) {
+; CHECK-LE-LABEL: test6:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    stxvrbx v2, 0, r5
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: test6:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    vsldoi v2, v2, v2, 9
+; CHECK-BE-NEXT:    stxsibx v2, 0, r5
+; CHECK-BE-NEXT:    blr
+entry:
+  %vecext = extractelement <16 x i8> %A, i32 0
+  store i8 %vecext, i8* %a, align 1
+  ret void
+}
+
diff --git a/llvm/test/CodeGen/RISCV/jumptable.ll b/llvm/test/CodeGen/RISCV/jumptable.ll
index 5a5f5b65111a1..0eebc698759d3 100644
--- a/llvm/test/CodeGen/RISCV/jumptable.ll
+++ b/llvm/test/CodeGen/RISCV/jumptable.ll
@@ -1,39 +1,145 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I-SMALL
+; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I-MEDIUM
+; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I-SMALL
+; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I-MEDIUM
 
-define void @jt(i32 %in, i32* %out) nounwind {
-; RV32I-LABEL: jt:
-; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    addi a2, zero, 2
-; RV32I-NEXT:    blt a2, a0, .LBB0_4
-; RV32I-NEXT:  # %bb.1: # %entry
-; RV32I-NEXT:    addi a2, zero, 1
-; RV32I-NEXT:    beq a0, a2, .LBB0_7
-; RV32I-NEXT:  # %bb.2: # %entry
-; RV32I-NEXT:    addi a2, zero, 2
-; RV32I-NEXT:    bne a0, a2, .LBB0_10
-; RV32I-NEXT:  # %bb.3: # %bb2
-; RV32I-NEXT:    addi a0, zero, 3
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_4: # %entry
-; RV32I-NEXT:    addi a2, zero, 3
-; RV32I-NEXT:    beq a0, a2, .LBB0_8
-; RV32I-NEXT:  # %bb.5: # %entry
-; RV32I-NEXT:    addi a2, zero, 4
-; RV32I-NEXT:    bne a0, a2, .LBB0_10
-; RV32I-NEXT:  # %bb.6: # %bb4
-; RV32I-NEXT:    addi a0, zero, 1
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_7: # %bb1
-; RV32I-NEXT:    addi a0, zero, 4
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_8: # %bb3
-; RV32I-NEXT:    addi a0, zero, 2
-; RV32I-NEXT:  .LBB0_9: # %exit
-; RV32I-NEXT:    sw a0, 0(a1)
-; RV32I-NEXT:  .LBB0_10: # %exit
-; RV32I-NEXT:    ret
+define void @below_threshold(i32 %in, i32* %out) nounwind {
+; RV32I-SMALL-LABEL: below_threshold:
+; RV32I-SMALL:       # %bb.0: # %entry
+; RV32I-SMALL-NEXT:    addi a2, zero, 2
+; RV32I-SMALL-NEXT:    blt a2, a0, .LBB0_4
+; RV32I-SMALL-NEXT:  # %bb.1: # %entry
+; RV32I-SMALL-NEXT:    addi a2, zero, 1
+; RV32I-SMALL-NEXT:    beq a0, a2, .LBB0_7
+; RV32I-SMALL-NEXT:  # %bb.2: # %entry
+; RV32I-SMALL-NEXT:    addi a2, zero, 2
+; RV32I-SMALL-NEXT:    bne a0, a2, .LBB0_10
+; RV32I-SMALL-NEXT:  # %bb.3: # %bb2
+; RV32I-SMALL-NEXT:    addi a0, zero, 3
+; RV32I-SMALL-NEXT:    j .LBB0_9
+; RV32I-SMALL-NEXT:  .LBB0_4: # %entry
+; RV32I-SMALL-NEXT:    addi a2, zero, 3
+; RV32I-SMALL-NEXT:    beq a0, a2, .LBB0_8
+; RV32I-SMALL-NEXT:  # %bb.5: # %entry
+; RV32I-SMALL-NEXT:    addi a2, zero, 4
+; RV32I-SMALL-NEXT:    bne a0, a2, .LBB0_10
+; RV32I-SMALL-NEXT:  # %bb.6: # %bb4
+; RV32I-SMALL-NEXT:    addi a0, zero, 1
+; RV32I-SMALL-NEXT:    j .LBB0_9
+; RV32I-SMALL-NEXT:  .LBB0_7: # %bb1
+; RV32I-SMALL-NEXT:    addi a0, zero, 4
+; RV32I-SMALL-NEXT:    j .LBB0_9
+; RV32I-SMALL-NEXT:  .LBB0_8: # %bb3
+; RV32I-SMALL-NEXT:    addi a0, zero, 2
+; RV32I-SMALL-NEXT:  .LBB0_9: # %exit
+; RV32I-SMALL-NEXT:    sw a0, 0(a1)
+; RV32I-SMALL-NEXT:  .LBB0_10: # %exit
+; RV32I-SMALL-NEXT:    ret
+;
+; RV32I-MEDIUM-LABEL: below_threshold:
+; RV32I-MEDIUM:       # %bb.0: # %entry
+; RV32I-MEDIUM-NEXT:    addi a2, zero, 2
+; RV32I-MEDIUM-NEXT:    blt a2, a0, .LBB0_4
+; RV32I-MEDIUM-NEXT:  # %bb.1: # %entry
+; RV32I-MEDIUM-NEXT:    addi a2, zero, 1
+; RV32I-MEDIUM-NEXT:    beq a0, a2, .LBB0_7
+; RV32I-MEDIUM-NEXT:  # %bb.2: # %entry
+; RV32I-MEDIUM-NEXT:    addi a2, zero, 2
+; RV32I-MEDIUM-NEXT:    bne a0, a2, .LBB0_10
+; RV32I-MEDIUM-NEXT:  # %bb.3: # %bb2
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 3
+; RV32I-MEDIUM-NEXT:    j .LBB0_9
+; RV32I-MEDIUM-NEXT:  .LBB0_4: # %entry
+; RV32I-MEDIUM-NEXT:    addi a2, zero, 3
+; RV32I-MEDIUM-NEXT:    beq a0, a2, .LBB0_8
+; RV32I-MEDIUM-NEXT:  # %bb.5: # %entry
+; RV32I-MEDIUM-NEXT:    addi a2, zero, 4
+; RV32I-MEDIUM-NEXT:    bne a0, a2, .LBB0_10
+; RV32I-MEDIUM-NEXT:  # %bb.6: # %bb4
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 1
+; RV32I-MEDIUM-NEXT:    j .LBB0_9
+; RV32I-MEDIUM-NEXT:  .LBB0_7: # %bb1
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 4
+; RV32I-MEDIUM-NEXT:    j .LBB0_9
+; RV32I-MEDIUM-NEXT:  .LBB0_8: # %bb3
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 2
+; RV32I-MEDIUM-NEXT:  .LBB0_9: # %exit
+; RV32I-MEDIUM-NEXT:    sw a0, 0(a1)
+; RV32I-MEDIUM-NEXT:  .LBB0_10: # %exit
+; RV32I-MEDIUM-NEXT:    ret
+;
+; RV64I-SMALL-LABEL: below_threshold:
+; RV64I-SMALL:       # %bb.0: # %entry
+; RV64I-SMALL-NEXT:    slli a0, a0, 32
+; RV64I-SMALL-NEXT:    srli a0, a0, 32
+; RV64I-SMALL-NEXT:    addi a2, zero, 2
+; RV64I-SMALL-NEXT:    blt a2, a0, .LBB0_4
+; RV64I-SMALL-NEXT:  # %bb.1: # %entry
+; RV64I-SMALL-NEXT:    addi a2, zero, 1
+; RV64I-SMALL-NEXT:    beq a0, a2, .LBB0_7
+; RV64I-SMALL-NEXT:  # %bb.2: # %entry
+; RV64I-SMALL-NEXT:    addi a2, zero, 2
+; RV64I-SMALL-NEXT:    bne a0, a2, .LBB0_10
+; RV64I-SMALL-NEXT:  # %bb.3: # %bb2
+; RV64I-SMALL-NEXT:    addi a0, zero, 3
+; RV64I-SMALL-NEXT:    j .LBB0_9
+; RV64I-SMALL-NEXT:  .LBB0_4: # %entry
+; RV64I-SMALL-NEXT:    addi a2, zero, 3
+; RV64I-SMALL-NEXT:    beq a0, a2, .LBB0_8
+; RV64I-SMALL-NEXT:  # %bb.5: # %entry
+; RV64I-SMALL-NEXT:    addi a2, zero, 4
+; RV64I-SMALL-NEXT:    bne a0, a2, .LBB0_10
+; RV64I-SMALL-NEXT:  # %bb.6: # %bb4
+; RV64I-SMALL-NEXT:    addi a0, zero, 1
+; RV64I-SMALL-NEXT:    j .LBB0_9
+; RV64I-SMALL-NEXT:  .LBB0_7: # %bb1
+; RV64I-SMALL-NEXT:    addi a0, zero, 4
+; RV64I-SMALL-NEXT:    j .LBB0_9
+; RV64I-SMALL-NEXT:  .LBB0_8: # %bb3
+; RV64I-SMALL-NEXT:    addi a0, zero, 2
+; RV64I-SMALL-NEXT:  .LBB0_9: # %exit
+; RV64I-SMALL-NEXT:    sw a0, 0(a1)
+; RV64I-SMALL-NEXT:  .LBB0_10: # %exit
+; RV64I-SMALL-NEXT:    ret
+;
+; RV64I-MEDIUM-LABEL: below_threshold:
+; RV64I-MEDIUM:       # %bb.0: # %entry
+; RV64I-MEDIUM-NEXT:    slli a0, a0, 32
+; RV64I-MEDIUM-NEXT:    srli a0, a0, 32
+; RV64I-MEDIUM-NEXT:    addi a2, zero, 2
+; RV64I-MEDIUM-NEXT:    blt a2, a0, .LBB0_4
+; RV64I-MEDIUM-NEXT:  # %bb.1: # %entry
+; RV64I-MEDIUM-NEXT:    addi a2, zero, 1
+; RV64I-MEDIUM-NEXT:    beq a0, a2, .LBB0_7
+; RV64I-MEDIUM-NEXT:  # %bb.2: # %entry
+; RV64I-MEDIUM-NEXT:    addi a2, zero, 2
+; RV64I-MEDIUM-NEXT:    bne a0, a2, .LBB0_10
+; RV64I-MEDIUM-NEXT:  # %bb.3: # %bb2
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 3
+; RV64I-MEDIUM-NEXT:    j .LBB0_9
+; RV64I-MEDIUM-NEXT:  .LBB0_4: # %entry
+; RV64I-MEDIUM-NEXT:    addi a2, zero, 3
+; RV64I-MEDIUM-NEXT:    beq a0, a2, .LBB0_8
+; RV64I-MEDIUM-NEXT:  # %bb.5: # %entry
+; RV64I-MEDIUM-NEXT:    addi a2, zero, 4
+; RV64I-MEDIUM-NEXT:    bne a0, a2, .LBB0_10
+; RV64I-MEDIUM-NEXT:  # %bb.6: # %bb4
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 1
+; RV64I-MEDIUM-NEXT:    j .LBB0_9
+; RV64I-MEDIUM-NEXT:  .LBB0_7: # %bb1
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 4
+; RV64I-MEDIUM-NEXT:    j .LBB0_9
+; RV64I-MEDIUM-NEXT:  .LBB0_8: # %bb3
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 2
+; RV64I-MEDIUM-NEXT:  .LBB0_9: # %exit
+; RV64I-MEDIUM-NEXT:    sw a0, 0(a1)
+; RV64I-MEDIUM-NEXT:  .LBB0_10: # %exit
+; RV64I-MEDIUM-NEXT:    ret
 entry:
   switch i32 %in, label %exit [
     i32 1, label %bb1
@@ -56,3 +162,178 @@ bb4:
 exit:
   ret void
 }
+
+define void @above_threshold(i32 %in, i32* %out) nounwind {
+; RV32I-SMALL-LABEL: above_threshold:
+; RV32I-SMALL:       # %bb.0: # %entry
+; RV32I-SMALL-NEXT:    addi a0, a0, -1
+; RV32I-SMALL-NEXT:    addi a2, zero, 5
+; RV32I-SMALL-NEXT:    bltu a2, a0, .LBB1_9
+; RV32I-SMALL-NEXT:  # %bb.1: # %entry
+; RV32I-SMALL-NEXT:    slli a0, a0, 2
+; RV32I-SMALL-NEXT:    lui a2, %hi(.LJTI1_0)
+; RV32I-SMALL-NEXT:    addi a2, a2, %lo(.LJTI1_0)
+; RV32I-SMALL-NEXT:    add a0, a0, a2
+; RV32I-SMALL-NEXT:    lw a0, 0(a0)
+; RV32I-SMALL-NEXT:    jr a0
+; RV32I-SMALL-NEXT:  .LBB1_2: # %bb1
+; RV32I-SMALL-NEXT:    addi a0, zero, 4
+; RV32I-SMALL-NEXT:    j .LBB1_8
+; RV32I-SMALL-NEXT:  .LBB1_3: # %bb2
+; RV32I-SMALL-NEXT:    addi a0, zero, 3
+; RV32I-SMALL-NEXT:    j .LBB1_8
+; RV32I-SMALL-NEXT:  .LBB1_4: # %bb3
+; RV32I-SMALL-NEXT:    addi a0, zero, 2
+; RV32I-SMALL-NEXT:    j .LBB1_8
+; RV32I-SMALL-NEXT:  .LBB1_5: # %bb4
+; RV32I-SMALL-NEXT:    addi a0, zero, 1
+; RV32I-SMALL-NEXT:    j .LBB1_8
+; RV32I-SMALL-NEXT:  .LBB1_6: # %bb5
+; RV32I-SMALL-NEXT:    addi a0, zero, 100
+; RV32I-SMALL-NEXT:    j .LBB1_8
+; RV32I-SMALL-NEXT:  .LBB1_7: # %bb6
+; RV32I-SMALL-NEXT:    addi a0, zero, 200
+; RV32I-SMALL-NEXT:  .LBB1_8: # %exit
+; RV32I-SMALL-NEXT:    sw a0, 0(a1)
+; RV32I-SMALL-NEXT:  .LBB1_9: # %exit
+; RV32I-SMALL-NEXT:    ret
+;
+; RV32I-MEDIUM-LABEL: above_threshold:
+; RV32I-MEDIUM:       # %bb.0: # %entry
+; RV32I-MEDIUM-NEXT:    addi a0, a0, -1
+; RV32I-MEDIUM-NEXT:    addi a2, zero, 5
+; RV32I-MEDIUM-NEXT:    bltu a2, a0, .LBB1_9
+; RV32I-MEDIUM-NEXT:  # %bb.1: # %entry
+; RV32I-MEDIUM-NEXT:    slli a0, a0, 2
+; RV32I-MEDIUM-NEXT:  .LBB1_10: # %entry
+; RV32I-MEDIUM-NEXT:    # Label of block must be emitted
+; RV32I-MEDIUM-NEXT:    auipc a2, %pcrel_hi(.LJTI1_0)
+; RV32I-MEDIUM-NEXT:    addi a2, a2, %pcrel_lo(.LBB1_10)
+; RV32I-MEDIUM-NEXT:    add a0, a0, a2
+; RV32I-MEDIUM-NEXT:    lw a0, 0(a0)
+; RV32I-MEDIUM-NEXT:    jr a0
+; RV32I-MEDIUM-NEXT:  .LBB1_2: # %bb1
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 4
+; RV32I-MEDIUM-NEXT:    j .LBB1_8
+; RV32I-MEDIUM-NEXT:  .LBB1_3: # %bb2
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 3
+; RV32I-MEDIUM-NEXT:    j .LBB1_8
+; RV32I-MEDIUM-NEXT:  .LBB1_4: # %bb3
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 2
+; RV32I-MEDIUM-NEXT:    j .LBB1_8
+; RV32I-MEDIUM-NEXT:  .LBB1_5: # %bb4
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 1
+; RV32I-MEDIUM-NEXT:    j .LBB1_8
+; RV32I-MEDIUM-NEXT:  .LBB1_6: # %bb5
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 100
+; RV32I-MEDIUM-NEXT:    j .LBB1_8
+; RV32I-MEDIUM-NEXT:  .LBB1_7: # %bb6
+; RV32I-MEDIUM-NEXT:    addi a0, zero, 200
+; RV32I-MEDIUM-NEXT:  .LBB1_8: # %exit
+; RV32I-MEDIUM-NEXT:    sw a0, 0(a1)
+; RV32I-MEDIUM-NEXT:  .LBB1_9: # %exit
+; RV32I-MEDIUM-NEXT:    ret
+;
+; RV64I-SMALL-LABEL: above_threshold:
+; RV64I-SMALL:       # %bb.0: # %entry
+; RV64I-SMALL-NEXT:    slli a0, a0, 32
+; RV64I-SMALL-NEXT:    srli a0, a0, 32
+; RV64I-SMALL-NEXT:    addi a0, a0, -1
+; RV64I-SMALL-NEXT:    addi a2, zero, 5
+; RV64I-SMALL-NEXT:    bltu a2, a0, .LBB1_9
+; RV64I-SMALL-NEXT:  # %bb.1: # %entry
+; RV64I-SMALL-NEXT:    slli a0, a0, 3
+; RV64I-SMALL-NEXT:    lui a2, %hi(.LJTI1_0)
+; RV64I-SMALL-NEXT:    addi a2, a2, %lo(.LJTI1_0)
+; RV64I-SMALL-NEXT:    add a0, a0, a2
+; RV64I-SMALL-NEXT:    ld a0, 0(a0)
+; RV64I-SMALL-NEXT:    jr a0
+; RV64I-SMALL-NEXT:  .LBB1_2: # %bb1
+; RV64I-SMALL-NEXT:    addi a0, zero, 4
+; RV64I-SMALL-NEXT:    j .LBB1_8
+; RV64I-SMALL-NEXT:  .LBB1_3: # %bb2
+; RV64I-SMALL-NEXT:    addi a0, zero, 3
+; RV64I-SMALL-NEXT:    j .LBB1_8
+; RV64I-SMALL-NEXT:  .LBB1_4: # %bb3
+; RV64I-SMALL-NEXT:    addi a0, zero, 2
+; RV64I-SMALL-NEXT:    j .LBB1_8
+; RV64I-SMALL-NEXT:  .LBB1_5: # %bb4
+; RV64I-SMALL-NEXT:    addi a0, zero, 1
+; RV64I-SMALL-NEXT:    j .LBB1_8
+; RV64I-SMALL-NEXT:  .LBB1_6: # %bb5
+; RV64I-SMALL-NEXT:    addi a0, zero, 100
+; RV64I-SMALL-NEXT:    j .LBB1_8
+; RV64I-SMALL-NEXT:  .LBB1_7: # %bb6
+; RV64I-SMALL-NEXT:    addi a0, zero, 200
+; RV64I-SMALL-NEXT:  .LBB1_8: # %exit
+; RV64I-SMALL-NEXT:    sw a0, 0(a1)
+; RV64I-SMALL-NEXT:  .LBB1_9: # %exit
+; RV64I-SMALL-NEXT:    ret
+;
+; RV64I-MEDIUM-LABEL: above_threshold:
+; RV64I-MEDIUM:       # %bb.0: # %entry
+; RV64I-MEDIUM-NEXT:    slli a0, a0, 32
+; RV64I-MEDIUM-NEXT:    srli a0, a0, 32
+; RV64I-MEDIUM-NEXT:    addi a0, a0, -1
+; RV64I-MEDIUM-NEXT:    addi a2, zero, 5
+; RV64I-MEDIUM-NEXT:    bltu a2, a0, .LBB1_9
+; RV64I-MEDIUM-NEXT:  # %bb.1: # %entry
+; RV64I-MEDIUM-NEXT:    slli a0, a0, 3
+; RV64I-MEDIUM-NEXT:  .LBB1_10: # %entry
+; RV64I-MEDIUM-NEXT:    # Label of block must be emitted
+; RV64I-MEDIUM-NEXT:    auipc a2, %pcrel_hi(.LJTI1_0)
+; RV64I-MEDIUM-NEXT:    addi a2, a2, %pcrel_lo(.LBB1_10)
+; RV64I-MEDIUM-NEXT:    add a0, a0, a2
+; RV64I-MEDIUM-NEXT:    ld a0, 0(a0)
+; RV64I-MEDIUM-NEXT:    jr a0
+; RV64I-MEDIUM-NEXT:  .LBB1_2: # %bb1
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 4
+; RV64I-MEDIUM-NEXT:    j .LBB1_8
+; RV64I-MEDIUM-NEXT:  .LBB1_3: # %bb2
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 3
+; RV64I-MEDIUM-NEXT:    j .LBB1_8
+; RV64I-MEDIUM-NEXT:  .LBB1_4: # %bb3
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 2
+; RV64I-MEDIUM-NEXT:    j .LBB1_8
+; RV64I-MEDIUM-NEXT:  .LBB1_5: # %bb4
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 1
+; RV64I-MEDIUM-NEXT:    j .LBB1_8
+; RV64I-MEDIUM-NEXT:  .LBB1_6: # %bb5
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 100
+; RV64I-MEDIUM-NEXT:    j .LBB1_8
+; RV64I-MEDIUM-NEXT:  .LBB1_7: # %bb6
+; RV64I-MEDIUM-NEXT:    addi a0, zero, 200
+; RV64I-MEDIUM-NEXT:  .LBB1_8: # %exit
+; RV64I-MEDIUM-NEXT:    sw a0, 0(a1)
+; RV64I-MEDIUM-NEXT:  .LBB1_9: # %exit
+; RV64I-MEDIUM-NEXT:    ret
+entry:
+  switch i32 %in, label %exit [
+    i32 1, label %bb1
+    i32 2, label %bb2
+    i32 3, label %bb3
+    i32 4, label %bb4
+    i32 5, label %bb5
+    i32 6, label %bb6
+  ]
+bb1:
+  store i32 4, i32* %out
+  br label %exit
+bb2:
+  store i32 3, i32* %out
+  br label %exit
+bb3:
+  store i32 2, i32* %out
+  br label %exit
+bb4:
+  store i32 1, i32* %out
+  br label %exit
+bb5:
+  store i32 100, i32* %out
+  br label %exit
+bb6:
+  store i32 200, i32* %out
+  br label %exit
+exit:
+  ret void
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
new file mode 100644
index 0000000000000..98b30b565a3b6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
@@ -0,0 +1,822 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vadd_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vadd_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vadd_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vadd_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vadd_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vadd_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vadd_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vadd_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vadd_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vadd_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vadd_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vadd_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv32i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = add <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vadd_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = add <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vadd_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv64i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = add <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vadd_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vadd_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vadd_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vadd_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vadd_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vadd_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vadd_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vadd_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vadd_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vadd_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vadd_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vadd_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv32i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vadd_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vadd_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vadd_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vadd_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vadd_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vadd_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vadd_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vadd_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vadd_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vadd_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
+; CHECK-LABEL: vadd_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vadd_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vadd_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vadd_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vadd.vv v16, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vadd_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vadd_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 2, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vadd_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vsrl.vx v28, v28, a1
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vadd.vv v16, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vadd_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vadd_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 2, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vadd_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vsrl.vx v8, v8, a1
+; CHECK-NEXT:    vor.vv v28, v8, v28
+; CHECK-NEXT:    vadd.vv v16, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vadd_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vadd_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 2, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vadd_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vadd.vv v16, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll
new file mode 100644
index 0000000000000..724954d3cdf3a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll
@@ -0,0 +1,794 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vadd_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vadd_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vadd_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vadd_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vadd_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vadd_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vadd_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vadd_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vadd_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vadd_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vadd_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vadd_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vadd_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vadd_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vadd_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vadd_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vadd_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv32i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vadd_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = add <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vadd_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = add <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vadd_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vadd_vx_nxv64i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 2, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = add <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vadd_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vadd_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vadd_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vadd_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vadd_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vadd_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vadd_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vadd_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vadd_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vadd_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vadd_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vadd_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vadd_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vadd_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vadd_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vadd_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vadd_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 -1, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vadd_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vadd_vx_nxv32i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 2, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = add <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vadd_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vadd_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vadd_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vadd_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vadd_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vadd_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vadd_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vadd_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vadd_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vadd_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vadd_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vadd_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 -1, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vadd_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vadd_vx_nxv16i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 2, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = add <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vadd_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vadd_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vadd_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vadd_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv1i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 2, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = add <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vadd_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vadd_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vadd_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vadd_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv2i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 2, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = add <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vadd_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vadd_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vadd_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vadd_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv4i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 2, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = add <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vadd_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vadd.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, -1
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vadd_vx_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vadd.vi v16, v16, 2
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
new file mode 100644
index 0000000000000..0dd0a556e2a85
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
@@ -0,0 +1,1945 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i8> %2,
+    <vscale x 64 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vand_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vand_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vand_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vand_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vand_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vand_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vand_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vand_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vand_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vand_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vand_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vand_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vand_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vand_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vand_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vand_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vand_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vand_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vand_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vand_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vand_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vand_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vand_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vand_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vand_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 9,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vand_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vand_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vand_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vand_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vand_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vand_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vand_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vand_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vand_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vand_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vand_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
new file mode 100644
index 0000000000000..e6ae2578f5703
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-rv64.ll
@@ -0,0 +1,2377 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i8> %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vand_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vand_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vand_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vand_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vand_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vand_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vand_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vv_nxv8i64_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vv_nxv8i64_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vand.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vand_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vand_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vand_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vand_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vand_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vand_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vand_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vand_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vand_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vand_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vand_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vand_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vand_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vand_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vand_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vand_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vand_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vand_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vand_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vand_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vand_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  i64,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vand_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vx_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vx_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vand.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vand_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vand.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vand_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vand.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vand_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vand.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vand_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vand.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vand_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vand.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vand_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vand.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vand_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vand.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 9,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vand_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vand.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vand_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vand.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vand_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vand.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vand_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vand.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vand_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vand.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vand_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vand.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vand_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vand.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vand_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vand.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vand_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vand.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vand_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vand.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vand_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vand.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vand_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i64> @llvm.riscv.vand.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vand_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vand.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vand_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i64> @llvm.riscv.vand.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vand_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vand.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vand_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i64> @llvm.riscv.vand.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vand_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vand.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vand_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_vi_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i64> @llvm.riscv.vand.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vand_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vand_mask_vi_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vand.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vand.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll
new file mode 100644
index 0000000000000..1acdc7f06e3c6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare i32 @llvm.riscv.vfirst.i64.nxv1i1(
+  <vscale x 1 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_m_i64_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vfirst.i64.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.mask.i64.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_mask_m_i64_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vfirst.mask.i64.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.i64.nxv2i1(
+  <vscale x 2 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_m_i64_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vfirst.i64.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.mask.i64.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_mask_m_i64_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vfirst.mask.i64.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.i64.nxv4i1(
+  <vscale x 4 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_m_i64_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vfirst.i64.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.mask.i64.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_mask_m_i64_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vfirst.mask.i64.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.i64.nxv8i1(
+  <vscale x 8 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_m_i64_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vfirst.i64.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.mask.i64.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_mask_m_i64_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vfirst.mask.i64.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.i64.nxv16i1(
+  <vscale x 16 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_m_i64_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vfirst.i64.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.mask.i64.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_mask_m_i64_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vfirst.mask.i64.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.i64.nxv32i1(
+  <vscale x 32 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_m_i64_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vfirst.i64.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.mask.i64.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_mask_m_i64_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vfirst.mask.i64.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.i64.nxv64i1(
+  <vscale x 64 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_m_i64_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vfirst.i64.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vfirst.mask.i64.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define i32 @intrinsic_vfirst_mask_m_i64_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vfirst.mask.i64.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll
new file mode 100644
index 0000000000000..d1437cc79ffe1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare i64 @llvm.riscv.vfirst.i64.nxv1i1(
+  <vscale x 1 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_m_i64_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vfirst.i64.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.mask.i64.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_mask_m_i64_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.i64.nxv2i1(
+  <vscale x 2 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_m_i64_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vfirst.i64.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.mask.i64.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_mask_m_i64_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.i64.nxv4i1(
+  <vscale x 4 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_m_i64_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vfirst.i64.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.mask.i64.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_mask_m_i64_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.i64.nxv8i1(
+  <vscale x 8 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_m_i64_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vfirst.i64.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.mask.i64.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_mask_m_i64_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.i64.nxv16i1(
+  <vscale x 16 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_m_i64_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vfirst.i64.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.mask.i64.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_mask_m_i64_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.i64.nxv32i1(
+  <vscale x 32 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_m_i64_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vfirst.i64.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.mask.i64.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_mask_m_i64_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.i64.nxv64i1(
+  <vscale x 64 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_m_i64_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_m_i64_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vfirst.i64.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vfirst.mask.i64.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define i64 @intrinsic_vfirst_mask_m_i64_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfirst_mask_m_i64_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vfirst.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vfirst.mask.i64.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
new file mode 100644
index 0000000000000..44f0ecb2f0d5f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv32.ll
@@ -0,0 +1,856 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
new file mode 100644
index 0000000000000..6b83445292a3c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc-rv64.ll
@@ -0,0 +1,1142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
new file mode 100644
index 0000000000000..344a21bb08950
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv32.ll
@@ -0,0 +1,856 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll
new file mode 100644
index 0000000000000..993f535777e05
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd-rv64.ll
@@ -0,0 +1,1142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
new file mode 100644
index 0000000000000..5c7b025f4f9ce
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll
@@ -0,0 +1,881 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i32 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i32 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i32 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i32 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i32 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    i32 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x half> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    i32 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmax_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmax_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmax_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmax_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmax_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmax_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmax_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmax_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmax_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmax_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmax_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    half %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmax_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmax_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmax_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmax_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmax_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmax_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmax_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmax_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmax_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    float %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
new file mode 100644
index 0000000000000..c24eccdb84a81
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll
@@ -0,0 +1,1201 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i64 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i64 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i64 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i64 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i64 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    i64 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x half> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i64 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i64 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i64 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i64 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    i64 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmax.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmax_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmax.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    i64 %2)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmax_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmax.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmax_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv2f64_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmax.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    i64 %2)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmax_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv2f64_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmax.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmax_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv4f64_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmax.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    i64 %2)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmax_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv4f64_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmax.nxv8f64.nxv8f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmax_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vv_nxv8f64_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmax.nxv8f64.nxv8f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    i64 %2)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vv_nxv8f64_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfmax.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.nxv8f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 8 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmax_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmax.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmax_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmax.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmax_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmax.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmax_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmax.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmax_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmax.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmax_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmax.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmax_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmax.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmax_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmax.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmax_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmax.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmax_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmax.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmax_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmax.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmax.mask.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    half %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmax_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmax.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmax_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmax.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmax_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmax.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmax_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmax.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmax_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmax.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmax_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmax.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmax_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmax.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmax_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmax.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmax_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmax.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmax.mask.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    float %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmax.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmax_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv1f64_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmax.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmax_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv1f64_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmax.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmax.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmax_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv2f64_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmax.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmax_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv2f64_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmax.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmax.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmax_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv4f64_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmax.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmax_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv4f64_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmax.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmax.nxv8f64.f64(
+  <vscale x 8 x double>,
+  double,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmax_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_vf_nxv8f64_nxv8f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmax.nxv8f64.f64(
+    <vscale x 8 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  double,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmax_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmax_mask_vf_nxv8f64_nxv8f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfmax.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmax.mask.nxv8f64.f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    double %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll
new file mode 100644
index 0000000000000..a6b09704c8a67
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll
@@ -0,0 +1,441 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll
new file mode 100644
index 0000000000000..6f3cafce40e66
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll
@@ -0,0 +1,601 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmerge.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmerge.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmerge.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmerge.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmerge.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmerge.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmerge.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmerge.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmerge.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmerge.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.nxv8f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.nxv8f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64(
+  <vscale x 8 x double>,
+  double,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8
+; CHECK:       vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64(
+    <vscale x 8 x double> %0,
+    double %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
new file mode 100644
index 0000000000000..ea6f019ebd61f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll
@@ -0,0 +1,881 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i32 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmin_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i32 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmin.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmin_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmin.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmin_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i32 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmin.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmin_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmin.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmin_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i32 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmin.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmin_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmin.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmin_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i32 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmin.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmin_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmin.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmin.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmin_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmin.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    i32 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x half> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmin_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmin.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmin_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmin.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmin.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmin_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmin.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmin.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmin_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmin.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmin_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmin.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmin_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmin.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmin.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmin_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmin.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmin.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmin_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmin.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmin.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmin_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmin.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    i32 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmin_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmin_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmin_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmin.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmin_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmin.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmin_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmin.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmin_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmin.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmin_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmin.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmin_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmin.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmin_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmin.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmin_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmin.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmin.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmin_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmin.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmin_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    half %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmin_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmin.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmin_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmin.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmin.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmin_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmin.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmin.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmin_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmin.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmin_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmin.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmin_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmin.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmin.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmin_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmin.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmin.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmin_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmin.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmin.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmin_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmin.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmin_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    float %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
new file mode 100644
index 0000000000000..815badcfc75a5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll
@@ -0,0 +1,1201 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i64 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f16_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmin_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i64 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmin.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmin_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f16_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmin.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmin_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i64 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmin.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmin_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmin.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmin_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i64 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmin.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmin_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f16_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmin.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmin_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i64 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmin.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmin_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f16_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmin.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmin.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmin_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmin.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    i64 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv32f16_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x half> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmin_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i64 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmin.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmin_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f32_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmin.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmin.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmin_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmin.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i64 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmin.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmin_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmin.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmin_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i64 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmin.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmin_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f32_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmin.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmin.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmin_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmin.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i64 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmin.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmin_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f32_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmin.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmin.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmin_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmin.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    i64 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv16f32_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x float> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmin.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmin_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmin.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    i64 %2)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmin.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmin_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmin.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmin.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmin_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv2f64_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmin.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    i64 %2)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmin.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmin_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv2f64_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmin.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmin.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmin_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv4f64_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmin.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    i64 %2)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmin.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmin_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv4f64_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmin.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmin.nxv8f64.nxv8f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmin_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vv_nxv8f64_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmin.nxv8f64.nxv8f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    i64 %2)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vv_nxv8f64_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfmin.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.nxv8f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 8 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmin_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmin.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmin_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f16_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmin.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmin_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmin.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmin.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmin_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f16_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmin.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmin_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmin.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmin.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmin_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f16_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmin.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmin_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmin.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmin.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmin_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f16_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmin.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmin_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmin.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmin.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmin_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16f16_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmin.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmin.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmin_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmin.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmin_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv32f16_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmin.mask.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    half %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmin_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmin.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmin.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmin_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f32_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmin.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmin.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmin_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmin.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmin.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmin_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f32_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmin.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmin_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmin.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmin.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmin_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f32_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmin.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmin.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmin_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmin.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmin.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmin_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f32_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmin.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmin.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmin_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmin.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmin_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv16f32_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmin.mask.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    float %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmin.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmin_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv1f64_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmin.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmin.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmin_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv1f64_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmin.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmin.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmin_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv2f64_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmin.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmin.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmin_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv2f64_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmin.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmin.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmin_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv4f64_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmin.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmin.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmin_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv4f64_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmin.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmin.nxv8f64.f64(
+  <vscale x 8 x double>,
+  double,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmin_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_vf_nxv8f64_nxv8f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmin.nxv8f64.f64(
+    <vscale x 8 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  double,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmin_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmin_mask_vf_nxv8f64_nxv8f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfmin.vf {{v[0-9]+}}, {{v[0-9]+}}, {{(a|ft)[0-9]+}}, v0.t
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmin.mask.nxv8f64.f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    double %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
new file mode 100644
index 0000000000000..d86f9462c6f2a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv32.ll
@@ -0,0 +1,856 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
new file mode 100644
index 0000000000000..03364aba84307
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac-rv64.ll
@@ -0,0 +1,1142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
new file mode 100644
index 0000000000000..1d8cb060e3222
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv32.ll
@@ -0,0 +1,856 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
new file mode 100644
index 0000000000000..347731829812e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub-rv64.ll
@@ -0,0 +1,1142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
new file mode 100644
index 0000000000000..521c6b4ccbf9d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll
@@ -0,0 +1,421 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -target-abi ilp32d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.f16(
+  half,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16_f16(half %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.f16(
+    half %0,
+    i32 %1)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.f16(
+  half,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16_f16(half %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.f16(
+    half %0,
+    i32 %1)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.f16(
+  half,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16_f16(half %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.f16(
+    half %0,
+    i32 %1)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.f16(
+  half,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16_f16(half %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.f16(
+    half %0,
+    i32 %1)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.f16(
+  half,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16_f16(half %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.f16(
+    half %0,
+    i32 %1)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.f16(
+  half,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16_f16(half %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.f16(
+    half %0,
+    i32 %1)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.f32(
+  float,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfmv.v.f_f_nxv1f32_f32(float %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.f32(
+    float %0,
+    i32 %1)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(
+  float,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfmv.v.f_f_nxv2f32_f32(float %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(
+    float %0,
+    i32 %1)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.f32(
+  float,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfmv.v.f_f_nxv4f32_f32(float %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.f32(
+    float %0,
+    i32 %1)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.f32(
+  float,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfmv.v.f_f_nxv8f32_f32(float %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.f32(
+    float %0,
+    i32 %1)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.f32(
+  float,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfmv.v.f_f_nxv16f32_f32(float %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.f32(
+    float %0,
+    i32 %1)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(
+  double,
+  i32);
+
+define <vscale x 1 x double> @intrinsic_vfmv.v.f_f_nxv1f64_f64(double %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(
+    double %0,
+    i32 %1)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.f64(
+  double,
+  i32);
+
+define <vscale x 2 x double> @intrinsic_vfmv.v.f_f_nxv2f64_f64(double %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.f64(
+    double %0,
+    i32 %1)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.f64(
+  double,
+  i32);
+
+define <vscale x 4 x double> @intrinsic_vfmv.v.f_f_nxv4f64_f64(double %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.f64(
+    double %0,
+    i32 %1)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64.f64(
+  double,
+  i32);
+
+define <vscale x 8 x double> @intrinsic_vfmv.v.f_f_nxv8f64_f64(double %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64.f64(
+    double %0,
+    i32 %1)
+
+  ret <vscale x 8 x double> %a
+}
+
+define <vscale x 1 x half> @intrinsic_vfmv.v.f_zero_nxv1f16_f16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.f16(
+    half 0.0,
+    i32 %0)
+
+  ret <vscale x 1 x half> %a
+}
+
+define <vscale x 2 x half> @intrinsic_vmv.v.x_zero_nxv2f16_f16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.f16(
+    half 0.0,
+    i32 %0)
+
+  ret <vscale x 2 x half> %a
+}
+
+define <vscale x 4 x half> @intrinsic_vmv.v.x_zero_nxv4f16_f16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.f16(
+    half 0.0,
+    i32 %0)
+
+  ret <vscale x 4 x half> %a
+}
+
+define <vscale x 8 x half> @intrinsic_vmv.v.x_zero_nxv8f16_f16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.f16(
+    half 0.0,
+    i32 %0)
+
+  ret <vscale x 8 x half> %a
+}
+
+define <vscale x 16 x half> @intrinsic_vmv.v.x_zero_nxv16f16_f16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.f16(
+    half 0.0,
+    i32 %0)
+
+  ret <vscale x 16 x half> %a
+}
+
+define <vscale x 32 x half> @intrinsic_vmv.v.x_zero_nxv32f16_f16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.f16(
+    half 0.0,
+    i32 %0)
+
+  ret <vscale x 32 x half> %a
+}
+
+define <vscale x 1 x float> @intrinsic_vmv.v.x_zero_nxv1f32_f32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.f32(
+    float 0.0,
+    i32 %0)
+
+  ret <vscale x 1 x float> %a
+}
+
+define <vscale x 2 x float> @intrinsic_vmv.v.x_zero_nxv2f32_f32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(
+    float 0.0,
+    i32 %0)
+
+  ret <vscale x 2 x float> %a
+}
+
+define <vscale x 4 x float> @intrinsic_vmv.v.x_zero_nxv4f32_f32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.f32(
+    float 0.0,
+    i32 %0)
+
+  ret <vscale x 4 x float> %a
+}
+
+define <vscale x 8 x float> @intrinsic_vmv.v.x_zero_nxv8f32_f32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.f32(
+    float 0.0,
+    i32 %0)
+
+  ret <vscale x 8 x float> %a
+}
+
+define <vscale x 16 x float> @intrinsic_vmv.v.x_zero_nxv16f32_f32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.f32(
+    float 0.0,
+    i32 %0)
+
+  ret <vscale x 16 x float> %a
+}
+
+define <vscale x 1 x double> @intrinsic_vmv.v.x_zero_nxv1f64_f64(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(
+    double 0.0,
+    i32 %0)
+
+  ret <vscale x 1 x double> %a
+}
+
+define <vscale x 2 x double> @intrinsic_vmv.v.x_zero_nxv2f64_f64(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.f64(
+    double 0.0,
+    i32 %0)
+
+  ret <vscale x 2 x double> %a
+}
+
+define <vscale x 4 x double> @intrinsic_vmv.v.x_zero_nxv4f64_f64(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.f64(
+    double 0.0,
+    i32 %0)
+
+  ret <vscale x 4 x double> %a
+}
+
+define <vscale x 8 x double> @intrinsic_vmv.v.x_zero_nxv8f64_f64(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv8f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64.f64(
+    double 0.0,
+    i32 %0)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll
new file mode 100644
index 0000000000000..525fa09275262
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll
@@ -0,0 +1,421 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -target-abi lp64d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.f16(
+  half,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfmv.v.f_f_nxv1f16_f16(half %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.f16(
+    half %0,
+    i64 %1)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.f16(
+  half,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfmv.v.f_f_nxv2f16_f16(half %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.f16(
+    half %0,
+    i64 %1)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.f16(
+  half,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfmv.v.f_f_nxv4f16_f16(half %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.f16(
+    half %0,
+    i64 %1)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.f16(
+  half,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfmv.v.f_f_nxv8f16_f16(half %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.f16(
+    half %0,
+    i64 %1)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.f16(
+  half,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfmv.v.f_f_nxv16f16_f16(half %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.f16(
+    half %0,
+    i64 %1)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.f16(
+  half,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfmv.v.f_f_nxv32f16_f16(half %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.f16(
+    half %0,
+    i64 %1)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.f32(
+  float,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfmv.v.f_f_nxv1f32_f32(float %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.f32(
+    float %0,
+    i64 %1)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(
+  float,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfmv.v.f_f_nxv2f32_f32(float %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(
+    float %0,
+    i64 %1)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.f32(
+  float,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfmv.v.f_f_nxv4f32_f32(float %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.f32(
+    float %0,
+    i64 %1)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.f32(
+  float,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfmv.v.f_f_nxv8f32_f32(float %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.f32(
+    float %0,
+    i64 %1)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.f32(
+  float,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfmv.v.f_f_nxv16f32_f32(float %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.f32(
+    float %0,
+    i64 %1)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(
+  double,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfmv.v.f_f_nxv1f64_f64(double %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(
+    double %0,
+    i64 %1)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.f64(
+  double,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfmv.v.f_f_nxv2f64_f64(double %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.f64(
+    double %0,
+    i64 %1)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.f64(
+  double,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfmv.v.f_f_nxv4f64_f64(double %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.f64(
+    double %0,
+    i64 %1)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64.f64(
+  double,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfmv.v.f_f_nxv8f64_f64(double %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8,ta,mu
+; CHECK:       vfmv.v.f {{v[0-9]+}}, fa0
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64.f64(
+    double %0,
+    i64 %1)
+
+  ret <vscale x 8 x double> %a
+}
+
+define <vscale x 1 x half> @intrinsic_vfmv.v.f_zero_nxv1f16_f16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfmv.v.f_zero_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16.f16(
+    half 0.0,
+    i64 %0)
+
+  ret <vscale x 1 x half> %a
+}
+
+define <vscale x 2 x half> @intrinsic_vmv.v.x_zero_nxv2f16_f16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 2 x half> @llvm.riscv.vfmv.v.f.nxv2f16.f16(
+    half 0.0,
+    i64 %0)
+
+  ret <vscale x 2 x half> %a
+}
+
+define <vscale x 4 x half> @intrinsic_vmv.v.x_zero_nxv4f16_f16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 4 x half> @llvm.riscv.vfmv.v.f.nxv4f16.f16(
+    half 0.0,
+    i64 %0)
+
+  ret <vscale x 4 x half> %a
+}
+
+define <vscale x 8 x half> @intrinsic_vmv.v.x_zero_nxv8f16_f16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 8 x half> @llvm.riscv.vfmv.v.f.nxv8f16.f16(
+    half 0.0,
+    i64 %0)
+
+  ret <vscale x 8 x half> %a
+}
+
+define <vscale x 16 x half> @intrinsic_vmv.v.x_zero_nxv16f16_f16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 16 x half> @llvm.riscv.vfmv.v.f.nxv16f16.f16(
+    half 0.0,
+    i64 %0)
+
+  ret <vscale x 16 x half> %a
+}
+
+define <vscale x 32 x half> @intrinsic_vmv.v.x_zero_nxv32f16_f16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv32f16_f16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 32 x half> @llvm.riscv.vfmv.v.f.nxv32f16.f16(
+    half 0.0,
+    i64 %0)
+
+  ret <vscale x 32 x half> %a
+}
+
+define <vscale x 1 x float> @intrinsic_vmv.v.x_zero_nxv1f32_f32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 1 x float> @llvm.riscv.vfmv.v.f.nxv1f32.f32(
+    float 0.0,
+    i64 %0)
+
+  ret <vscale x 1 x float> %a
+}
+
+define <vscale x 2 x float> @intrinsic_vmv.v.x_zero_nxv2f32_f32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 2 x float> @llvm.riscv.vfmv.v.f.nxv2f32.f32(
+    float 0.0,
+    i64 %0)
+
+  ret <vscale x 2 x float> %a
+}
+
+define <vscale x 4 x float> @intrinsic_vmv.v.x_zero_nxv4f32_f32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 4 x float> @llvm.riscv.vfmv.v.f.nxv4f32.f32(
+    float 0.0,
+    i64 %0)
+
+  ret <vscale x 4 x float> %a
+}
+
+define <vscale x 8 x float> @intrinsic_vmv.v.x_zero_nxv8f32_f32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 8 x float> @llvm.riscv.vfmv.v.f.nxv8f32.f32(
+    float 0.0,
+    i64 %0)
+
+  ret <vscale x 8 x float> %a
+}
+
+define <vscale x 16 x float> @intrinsic_vmv.v.x_zero_nxv16f32_f32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv16f32_f32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 16 x float> @llvm.riscv.vfmv.v.f.nxv16f32.f32(
+    float 0.0,
+    i64 %0)
+
+  ret <vscale x 16 x float> %a
+}
+
+define <vscale x 1 x double> @intrinsic_vmv.v.x_zero_nxv1f64_f64(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 1 x double> @llvm.riscv.vfmv.v.f.nxv1f64.f64(
+    double 0.0,
+    i64 %0)
+
+  ret <vscale x 1 x double> %a
+}
+
+define <vscale x 2 x double> @intrinsic_vmv.v.x_zero_nxv2f64_f64(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 2 x double> @llvm.riscv.vfmv.v.f.nxv2f64.f64(
+    double 0.0,
+    i64 %0)
+
+  ret <vscale x 2 x double> %a
+}
+
+define <vscale x 4 x double> @intrinsic_vmv.v.x_zero_nxv4f64_f64(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 4 x double> @llvm.riscv.vfmv.v.f.nxv4f64.f64(
+    double 0.0,
+    i64 %0)
+
+  ret <vscale x 4 x double> %a
+}
+
+define <vscale x 8 x double> @intrinsic_vmv.v.x_zero_nxv8f64_f64(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.x_zero_nxv8f64_f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8,ta,mu
+; CHECK:       vmv.v.x {{v[0-9]+}}, zero
+  %a = call <vscale x 8 x double> @llvm.riscv.vfmv.v.f.nxv8f64.f64(
+    double 0.0,
+    i64 %0)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
new file mode 100644
index 0000000000000..d90664c7eb372
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll
@@ -0,0 +1,856 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll
new file mode 100644
index 0000000000000..9e113de8e9ca7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll
@@ -0,0 +1,1142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
new file mode 100644
index 0000000000000..abea8d688fa31
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll
@@ -0,0 +1,856 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll
new file mode 100644
index 0000000000000..4b4b8136fe5a4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll
@@ -0,0 +1,1142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmadd.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
new file mode 100644
index 0000000000000..7b090881a3360
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll
@@ -0,0 +1,856 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
new file mode 100644
index 0000000000000..23d83c29e247f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll
@@ -0,0 +1,1142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
new file mode 100644
index 0000000000000..4cbeb71a86533
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll
@@ -0,0 +1,856 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
new file mode 100644
index 0000000000000..c25fee55ba368
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll
@@ -0,0 +1,1142 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x half>  @intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half>  @intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half>  @intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half>  @intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half>  @intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfnmsub.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
new file mode 100644
index 0000000000000..6d2fa56686f86
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll
@@ -0,0 +1,463 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16.nxv1i1(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16.nxv1i1(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16.nxv2i1(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16.nxv2i1(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16.nxv4i1(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16.nxv4i1(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16.nxv8i1(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16.nxv8i1(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16.nxv16i1(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16.nxv16i1(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.nxv32i1(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.nxv32i1(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.nxv1i1(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.nxv1i1(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.nxv2i1(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.nxv2i1(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.nxv4i1(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.nxv4i1(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.nxv8i1(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.nxv8i1(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.nxv16i1(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.nxv16i1(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll
new file mode 100644
index 0000000000000..2977a633a4a37
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll
@@ -0,0 +1,631 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16.nxv1i1(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16.nxv1i1(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16.nxv2i1(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16.nxv2i1(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16.nxv4i1(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16.nxv4i1(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16.nxv8i1(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16.nxv8i1(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16.nxv16i1(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16.nxv16i1(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.nxv32i1(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.nxv32i1(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.nxv1i1(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.nxv1i1(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.nxv2i1(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.nxv2i1(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.nxv4i1(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.nxv4i1(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.nxv8i1(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.nxv8i1(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.nxv16i1(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.nxv16i1(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64.nxv1i1(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64.nxv1i1(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64(
+  <vscale x 1 x double>,
+  <vscale x 2 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64(
+    <vscale x 1 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64.nxv2i1(
+  <vscale x 1 x double>,
+  <vscale x 2 x double>,
+  <vscale x 1 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64.nxv2i1(
+    <vscale x 1 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64(
+  <vscale x 1 x double>,
+  <vscale x 4 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64(
+    <vscale x 1 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64.nxv4i1(
+  <vscale x 1 x double>,
+  <vscale x 4 x double>,
+  <vscale x 1 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64.nxv4i1(
+    <vscale x 1 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64(
+  <vscale x 1 x double>,
+  <vscale x 8 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64(
+    <vscale x 1 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.nxv8i1(
+  <vscale x 1 x double>,
+  <vscale x 8 x double>,
+  <vscale x 1 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.nxv8i1(
+    <vscale x 1 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
new file mode 100644
index 0000000000000..fefa2e5de06a9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll
@@ -0,0 +1,463 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16.nxv1i1(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16.nxv1i1(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16.nxv2i1(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16.nxv2i1(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16.nxv4i1(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16.nxv4i1(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16.nxv8i1(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16.nxv8i1(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16.nxv16i1(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16.nxv16i1(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.nxv32i1(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.nxv32i1(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.nxv1i1(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.nxv1i1(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32.nxv2i1(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32.nxv2i1(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32.nxv4i1(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32.nxv4i1(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32.nxv8i1(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32.nxv8i1(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32.nxv16i1(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32.nxv16i1(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll
new file mode 100644
index 0000000000000..60da063f56985
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll
@@ -0,0 +1,631 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16.nxv1i1(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16.nxv1i1(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16.nxv2i1(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16.nxv2i1(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16.nxv4i1(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16.nxv4i1(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16.nxv8i1(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16.nxv8i1(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16.nxv16i1(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16.nxv16i1(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.nxv32i1(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.nxv32i1(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.nxv1i1(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.nxv1i1(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32.nxv2i1(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32.nxv2i1(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32.nxv4i1(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32.nxv4i1(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32.nxv8i1(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32.nxv8i1(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32.nxv16i1(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32.nxv16i1(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64.nxv1i1(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64.nxv1i1(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64(
+  <vscale x 1 x double>,
+  <vscale x 2 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64(
+    <vscale x 1 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64.nxv2i1(
+  <vscale x 1 x double>,
+  <vscale x 2 x double>,
+  <vscale x 1 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64.nxv2i1(
+    <vscale x 1 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64(
+  <vscale x 1 x double>,
+  <vscale x 4 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64(
+    <vscale x 1 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64.nxv4i1(
+  <vscale x 1 x double>,
+  <vscale x 4 x double>,
+  <vscale x 1 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64.nxv4i1(
+    <vscale x 1 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64(
+  <vscale x 1 x double>,
+  <vscale x 8 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64(
+    <vscale x 1 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64.nxv8i1(
+  <vscale x 1 x double>,
+  <vscale x 8 x double>,
+  <vscale x 1 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64.nxv8i1(
+    <vscale x 1 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
new file mode 100644
index 0000000000000..e50e92a6bd20e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll
@@ -0,0 +1,463 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll
new file mode 100644
index 0000000000000..948ad9f18da1e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll
@@ -0,0 +1,631 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64(
+  <vscale x 1 x double>,
+  <vscale x 2 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64(
+    <vscale x 1 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1(
+  <vscale x 1 x double>,
+  <vscale x 2 x double>,
+  <vscale x 1 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1(
+    <vscale x 1 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64(
+  <vscale x 1 x double>,
+  <vscale x 4 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64(
+    <vscale x 1 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1(
+  <vscale x 1 x double>,
+  <vscale x 4 x double>,
+  <vscale x 1 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1(
+    <vscale x 1 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64(
+  <vscale x 1 x double>,
+  <vscale x 8 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64(
+    <vscale x 1 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1(
+  <vscale x 1 x double>,
+  <vscale x 8 x double>,
+  <vscale x 1 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1(
+    <vscale x 1 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll
new file mode 100644
index 0000000000000..87393c291ca87
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll
@@ -0,0 +1,463 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll
new file mode 100644
index 0000000000000..7000191c9a644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll
@@ -0,0 +1,631 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1(
+  <vscale x 4 x half>,
+  <vscale x 1 x half>,
+  <vscale x 4 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1(
+    <vscale x 4 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1(
+  <vscale x 4 x half>,
+  <vscale x 2 x half>,
+  <vscale x 4 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1(
+    <vscale x 4 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1(
+  <vscale x 4 x half>,
+  <vscale x 8 x half>,
+  <vscale x 4 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1(
+    <vscale x 4 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1(
+  <vscale x 4 x half>,
+  <vscale x 16 x half>,
+  <vscale x 4 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1(
+    <vscale x 4 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1(
+  <vscale x 4 x half>,
+  <vscale x 32 x half>,
+  <vscale x 4 x half>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1(
+    <vscale x 4 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1(
+  <vscale x 2 x float>,
+  <vscale x 1 x float>,
+  <vscale x 2 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1(
+    <vscale x 2 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1(
+  <vscale x 2 x float>,
+  <vscale x 4 x float>,
+  <vscale x 2 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1(
+    <vscale x 2 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1(
+  <vscale x 2 x float>,
+  <vscale x 8 x float>,
+  <vscale x 2 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1(
+    <vscale x 2 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1(
+  <vscale x 2 x float>,
+  <vscale x 16 x float>,
+  <vscale x 2 x float>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1(
+    <vscale x 2 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.nxv1i1(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.nxv1i1(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64(
+  <vscale x 1 x double>,
+  <vscale x 2 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64(
+    <vscale x 1 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.nxv2i1(
+  <vscale x 1 x double>,
+  <vscale x 2 x double>,
+  <vscale x 1 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.nxv2i1(
+    <vscale x 1 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64(
+  <vscale x 1 x double>,
+  <vscale x 4 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64(
+    <vscale x 1 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.nxv4i1(
+  <vscale x 1 x double>,
+  <vscale x 4 x double>,
+  <vscale x 1 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.nxv4i1(
+    <vscale x 1 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64(
+  <vscale x 1 x double>,
+  <vscale x 8 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64(
+    <vscale x 1 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.nxv8i1(
+  <vscale x 1 x double>,
+  <vscale x 8 x double>,
+  <vscale x 1 x double>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vfredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.nxv8i1(
+    <vscale x 1 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
new file mode 100644
index 0000000000000..c1e49e56602d1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll
@@ -0,0 +1,512 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfslide1down.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfslide1down_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f16_nxv1f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfslide1down.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfslide1down_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f16_nxv2f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfslide1down.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfslide1down_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f16_nxv2f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfslide1down.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfslide1down_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f16_nxv4f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfslide1down.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfslide1down_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f16_nxv4f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfslide1down.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfslide1down_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f16_nxv8f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfslide1down.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfslide1down_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f16_nxv8f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfslide1down.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfslide1down_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv16f16_nxv16f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfslide1down.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfslide1down_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f16_nxv16f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfslide1down.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfslide1down_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv32f16_nxv32f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfslide1down.mask.nxv32f16.f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    fmv.h.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfslide1down.mask.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    half %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfslide1down_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f32_nxv1f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfslide1down_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f32_nxv1f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfslide1down_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f32_nxv2f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfslide1down_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f32_nxv2f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfslide1down_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f32_nxv4f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfslide1down_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f32_nxv8f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfslide1down_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f32_nxv8f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfslide1down_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv16f32_nxv16f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    fmv.w.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    float %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
new file mode 100644
index 0000000000000..0344da54fe43a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll
@@ -0,0 +1,698 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f16_nxv1f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfslide1down.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfslide1down.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfslide1down_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f16_nxv1f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfslide1down.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfslide1down_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f16_nxv2f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfslide1down.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfslide1down.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfslide1down_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f16_nxv2f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfslide1down.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfslide1down_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f16_nxv4f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfslide1down.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfslide1down.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfslide1down_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f16_nxv4f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfslide1down.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfslide1down_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f16_nxv8f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfslide1down.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfslide1down.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfslide1down_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f16_nxv8f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfslide1down.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfslide1down_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv16f16_nxv16f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfslide1down.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfslide1down.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfslide1down_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f16_nxv16f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfslide1down.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfslide1down_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv32f16_nxv32f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfslide1down.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfslide1down.mask.nxv32f16.f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv32f16_nxv32f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    fmv.h.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfslide1down.mask.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    half %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfslide1down_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f32_nxv1f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfslide1down.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfslide1down_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f32_nxv1f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfslide1down.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfslide1down_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f32_nxv2f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfslide1down.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfslide1down_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f32_nxv2f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfslide1down.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f32_nxv4f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfslide1down_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f32_nxv4f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfslide1down.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfslide1down_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f32_nxv8f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfslide1down.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfslide1down_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f32_nxv8f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfslide1down.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfslide1down_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv16f32_nxv16f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfslide1down.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv16f32_nxv16f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    fmv.w.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfslide1down.mask.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    float %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfslide1down.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfslide1down_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv1f64_nxv1f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfslide1down.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfslide1down.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfslide1down_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv1f64_nxv1f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfslide1down.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfslide1down.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfslide1down_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv2f64_nxv2f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfslide1down.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfslide1down.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfslide1down_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv2f64_nxv2f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfslide1down.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfslide1down.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfslide1down_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv4f64_nxv4f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfslide1down.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfslide1down.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfslide1down_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv4f64_nxv4f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfslide1down.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfslide1down.nxv8f64.f64(
+  <vscale x 8 x double>,
+  double,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfslide1down_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_vf_nxv8f64_nxv8f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v16, ft0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfslide1down.nxv8f64.f64(
+    <vscale x 8 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfslide1down.mask.nxv8f64.f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  double,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfslide1down_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1down_mask_vf_nxv8f64_nxv8f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    fmv.d.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
+; CHECK-NEXT:    vfslide1down.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfslide1down.mask.nxv8f64.f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    double %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
new file mode 100644
index 0000000000000..ce849b6d286ee
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll
@@ -0,0 +1,523 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfslide1up.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfslide1up.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v26, v16, ft0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfslide1up.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v28, v16, ft0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfslide1up.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v8, v16, ft0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfslide1up.mask.nxv32f16.f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    fmv.h.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.mask.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    half %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v26, v16, ft0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v28, v16, ft0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v8, v16, ft0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    fmv.w.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    float %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
new file mode 100644
index 0000000000000..765e186116ae6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll
@@ -0,0 +1,713 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f16_nxv1f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f16_nxv1f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vfslide1up.mask.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f16_nxv2f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vfslide1up.mask.nxv2f16.f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f16_nxv2f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vfslide1up.mask.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f16_nxv4f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vfslide1up.mask.nxv4f16.f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f16_nxv4f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vfslide1up.mask.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f16_nxv8f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v26, v16, ft0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vfslide1up.mask.nxv8f16.f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f16_nxv8f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vfslide1up.mask.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f16_nxv16f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v28, v16, ft0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vfslide1up.mask.nxv16f16.f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f16_nxv16f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vfslide1up.mask.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16(
+  <vscale x 32 x half>,
+  half,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv32f16_nxv32f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v8, v16, ft0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vfslide1up.mask.nxv32f16.f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  half,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, half %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv32f16_nxv32f16_f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    fmv.h.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vfslide1up.mask.nxv32f16.f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    half %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f32_nxv1f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f32_nxv1f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfslide1up.mask.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f32_nxv2f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f32_nxv2f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfslide1up.mask.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f32_nxv4f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v26, v16, ft0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f32_nxv4f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfslide1up.mask.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f32_nxv8f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v28, v16, ft0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f32_nxv8f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfslide1up.mask.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32(
+  <vscale x 16 x float>,
+  float,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, float %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv16f32_nxv16f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v8, v16, ft0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  float,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, float %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv16f32_nxv16f32_f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    fmv.w.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfslide1up.mask.nxv16f32.f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    float %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv1f64_nxv1f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v25, v16, ft0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfslide1up.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfslide1up.mask.nxv1f64.f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfslide1up_mask_vf_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv1f64_nxv1f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v17, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfslide1up.mask.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv2f64_nxv2f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v26, v16, ft0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfslide1up.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfslide1up.mask.nxv2f64.f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfslide1up_mask_vf_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv2f64_nxv2f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v18, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfslide1up.mask.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv4f64_nxv4f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v28, v16, ft0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfslide1up.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfslide1up.mask.nxv4f64.f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfslide1up_mask_vf_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv4f64_nxv4f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v20, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfslide1up.mask.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfslide1up.nxv8f64.f64(
+  <vscale x 8 x double>,
+  double,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfslide1up_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_vf_nxv8f64_nxv8f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.d.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v8, v16, ft0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfslide1up.nxv8f64.f64(
+    <vscale x 8 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfslide1up.mask.nxv8f64.f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  double,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfslide1up_mask_vf_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, double %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfslide1up_mask_vf_nxv8f64_nxv8f64_f64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    fmv.d.x ft0, a1
+; CHECK-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
+; CHECK-NEXT:    vfslide1up.vf v16, v8, ft0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfslide1up.mask.nxv8f64.f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    double %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
new file mode 100644
index 0000000000000..6825ecb121b34
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
@@ -0,0 +1,482 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
new file mode 100644
index 0000000000000..ccd970ef6af33
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
@@ -0,0 +1,868 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32(
+  <vscale x 1 x double>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32(
+  <vscale x 1 x double>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.nxv2f32(
+  <vscale x 2 x double>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.nxv2f32(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32(
+  <vscale x 2 x double>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.nxv4f32(
+  <vscale x 4 x double>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.nxv4f32(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32(
+  <vscale x 4 x double>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.nxv8f32(
+  <vscale x 8 x double>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.nxv8f32(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32(
+  <vscale x 8 x double>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.f32(
+  <vscale x 1 x double>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwmacc_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f64_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.f32(
+    <vscale x 1 x double> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32(
+  <vscale x 1 x double>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32(
+    <vscale x 1 x double> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.f32(
+  <vscale x 2 x double>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwmacc_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f64_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.f32(
+    <vscale x 2 x double> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32(
+  <vscale x 2 x double>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32(
+    <vscale x 2 x double> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.f32(
+  <vscale x 4 x double>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwmacc_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f64_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.f32(
+    <vscale x 4 x double> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32(
+  <vscale x 4 x double>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32(
+    <vscale x 4 x double> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.f32(
+  <vscale x 8 x double>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.f32(
+    <vscale x 8 x double> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32(
+  <vscale x 8 x double>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwmacc.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32(
+    <vscale x 8 x double> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
new file mode 100644
index 0000000000000..27b22f94f12ae
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
@@ -0,0 +1,482 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
new file mode 100644
index 0000000000000..b5149780a79ef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
@@ -0,0 +1,868 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32(
+  <vscale x 1 x double>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32(
+  <vscale x 1 x double>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.nxv2f32(
+  <vscale x 2 x double>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.nxv2f32(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32(
+  <vscale x 2 x double>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.nxv4f32(
+  <vscale x 4 x double>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.nxv4f32(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32(
+  <vscale x 4 x double>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.nxv8f32(
+  <vscale x 8 x double>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.nxv8f32(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32(
+  <vscale x 8 x double>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.f32(
+  <vscale x 1 x double>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwmsac_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f64_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.f32(
+    <vscale x 1 x double> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32(
+  <vscale x 1 x double>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32(
+    <vscale x 1 x double> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.f32(
+  <vscale x 2 x double>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwmsac_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f64_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.f32(
+    <vscale x 2 x double> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32(
+  <vscale x 2 x double>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32(
+    <vscale x 2 x double> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.f32(
+  <vscale x 4 x double>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwmsac_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f64_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.f32(
+    <vscale x 4 x double> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32(
+  <vscale x 4 x double>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32(
+    <vscale x 4 x double> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.f32(
+  <vscale x 8 x double>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.f32(
+    <vscale x 8 x double> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32(
+  <vscale x 8 x double>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwmsac.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32(
+    <vscale x 8 x double> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
new file mode 100644
index 0000000000000..1b00a96f93d27
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
@@ -0,0 +1,482 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
new file mode 100644
index 0000000000000..66d284f1067d6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
@@ -0,0 +1,868 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32(
+  <vscale x 1 x double>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32(
+  <vscale x 1 x double>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32(
+  <vscale x 2 x double>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32(
+  <vscale x 2 x double>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32(
+  <vscale x 4 x double>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32(
+  <vscale x 4 x double>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32(
+  <vscale x 8 x double>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32(
+  <vscale x 8 x double>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.f32(
+  <vscale x 1 x double>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.f32(
+    <vscale x 1 x double> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32(
+  <vscale x 1 x double>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32(
+    <vscale x 1 x double> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.f32(
+  <vscale x 2 x double>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.f32(
+    <vscale x 2 x double> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32(
+  <vscale x 2 x double>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32(
+    <vscale x 2 x double> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.f32(
+  <vscale x 4 x double>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.f32(
+    <vscale x 4 x double> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32(
+  <vscale x 4 x double>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32(
+    <vscale x 4 x double> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.f32(
+  <vscale x 8 x double>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.f32(
+    <vscale x 8 x double> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32(
+  <vscale x 8 x double>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwnmacc.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32(
+    <vscale x 8 x double> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
new file mode 100644
index 0000000000000..40bd6c0688da6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
@@ -0,0 +1,482 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
new file mode 100644
index 0000000000000..95bcc7cbec905
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
@@ -0,0 +1,868 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
+  <vscale x 1 x float>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
+  <vscale x 2 x float>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
+  <vscale x 4 x float>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
+  <vscale x 8 x float>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
+  <vscale x 16 x float>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32(
+  <vscale x 1 x double>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32(
+  <vscale x 1 x double>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32(
+  <vscale x 2 x double>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32(
+  <vscale x 2 x double>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32(
+  <vscale x 4 x double>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32(
+  <vscale x 4 x double>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32(
+  <vscale x 8 x double>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32(
+  <vscale x 8 x double>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x float>  @intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
+  <vscale x 1 x float>,
+  half,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
+    <vscale x 1 x float> %0,
+    half %1,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x float>  @intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
+  <vscale x 2 x float>,
+  half,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
+    <vscale x 2 x float> %0,
+    half %1,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x float>  @intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
+  <vscale x 4 x float>,
+  half,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
+    <vscale x 4 x float> %0,
+    half %1,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x float>  @intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
+  <vscale x 8 x float>,
+  half,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
+    <vscale x 8 x float> %0,
+    half %1,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x float>  @intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
+  <vscale x 16 x float>,
+  half,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    fmv.h.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
+    <vscale x 16 x float> %0,
+    half %1,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.f32(
+  <vscale x 1 x double>,
+  float,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x double>  @intrinsic_vfwnmsac_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f64_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.f32(
+    <vscale x 1 x double> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32(
+  <vscale x 1 x double>,
+  float,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32(
+    <vscale x 1 x double> %0,
+    float %1,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.f32(
+  <vscale x 2 x double>,
+  float,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x double>  @intrinsic_vfwnmsac_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f64_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.f32(
+    <vscale x 2 x double> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32(
+  <vscale x 2 x double>,
+  float,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32(
+    <vscale x 2 x double> %0,
+    float %1,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.f32(
+  <vscale x 4 x double>,
+  float,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x double>  @intrinsic_vfwnmsac_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f64_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.f32(
+    <vscale x 4 x double> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32(
+  <vscale x 4 x double>,
+  float,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32(
+    <vscale x 4 x double> %0,
+    float %1,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.f32(
+  <vscale x 8 x double>,
+  float,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x double>  @intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.f32(
+    <vscale x 8 x double> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32(
+  <vscale x 8 x double>,
+  float,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    fmv.w.x ft0, a0
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vfwnmsac.vf v16, ft0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32(
+    <vscale x 8 x double> %0,
+    float %1,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll
new file mode 100644
index 0000000000000..91b86cf4058b4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll
@@ -0,0 +1,43 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
+  <vscale x 2 x float>,
+  <vscale x 32 x half>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
+    <vscale x 2 x float> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.nxv32i1(
+  <vscale x 2 x float>,
+  <vscale x 32 x half>,
+  <vscale x 2 x float>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.nxv32i1(
+    <vscale x 2 x float> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll
new file mode 100644
index 0000000000000..1a9b1cde8226a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll
@@ -0,0 +1,85 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
+  <vscale x 2 x float>,
+  <vscale x 32 x half>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
+    <vscale x 2 x float> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.nxv32i1(
+  <vscale x 2 x float>,
+  <vscale x 32 x half>,
+  <vscale x 2 x float>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16.nxv32i1(
+    <vscale x 2 x float> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
+  <vscale x 1 x double>,
+  <vscale x 16 x float>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
+    <vscale x 1 x double> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv16i1(
+  <vscale x 1 x double>,
+  <vscale x 16 x float>,
+  <vscale x 1 x double>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfwredosum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv16i1(
+    <vscale x 1 x double> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll
new file mode 100644
index 0000000000000..dcc16b1b07ea3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll
@@ -0,0 +1,43 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
+  <vscale x 2 x float>,
+  <vscale x 32 x half>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
+    <vscale x 2 x float> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 2 x float> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16.nxv32i1(
+  <vscale x 2 x float>,
+  <vscale x 32 x half>,
+  <vscale x 2 x float>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16.nxv32i1(
+    <vscale x 2 x float> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll
new file mode 100644
index 0000000000000..ce2eb047c1b0a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll
@@ -0,0 +1,85 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
+  <vscale x 2 x float>,
+  <vscale x 32 x half>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
+    <vscale x 2 x float> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 2 x float> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16.nxv32i1(
+  <vscale x 2 x float>,
+  <vscale x 32 x half>,
+  <vscale x 2 x float>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16.nxv32i1(
+    <vscale x 2 x float> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 2 x float> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32(
+  <vscale x 1 x double>,
+  <vscale x 16 x float>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32(
+    <vscale x 1 x double> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 1 x double> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv16i1(
+  <vscale x 1 x double>,
+  <vscale x 16 x float>,
+  <vscale x 1 x double>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vfwredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv16i1(
+    <vscale x 1 x double> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 1 x double> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll
new file mode 100644
index 0000000000000..9e2d395a44ec6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll
@@ -0,0 +1,545 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv1i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
+    i32 %0)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vid_v_nxv2i8(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv2i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
+    i32 %0)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vid_mask_v_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vid_v_nxv4i8(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv4i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
+    i32 %0)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vid_mask_v_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vid_v_nxv8i8(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv8i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
+    i32 %0)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vid_mask_v_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vid_v_nxv16i8(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv16i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
+    i32 %0)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vid_mask_v_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vid_v_nxv32i8(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv32i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
+    i32 %0)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vid_mask_v_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vid_v_nxv1i16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv1i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
+    i32 %0)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vid_mask_v_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vid_v_nxv2i16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv2i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
+    i32 %0)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vid_mask_v_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vid_v_nxv4i16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv4i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
+    i32 %0)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vid_mask_v_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vid_v_nxv8i16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv8i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
+    i32 %0)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vid_mask_v_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vid_v_nxv16i16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv16i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
+    i32 %0)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vid_mask_v_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vid_v_nxv32i16(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv32i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
+    i32 %0)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vid_mask_v_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vid_v_nxv1i32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv1i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
+    i32 %0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vid_mask_v_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vid_v_nxv2i32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv2i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
+    i32 %0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vid_mask_v_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vid_v_nxv4i32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv4i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
+    i32 %0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vid_mask_v_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vid_v_nxv8i32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv8i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
+    i32 %0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vid_mask_v_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vid_v_nxv16i32(i32 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv16i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
+    i32 %0)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vid_mask_v_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll
new file mode 100644
index 0000000000000..53aa6aa02104f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll
@@ -0,0 +1,673 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vid_v_nxv1i8(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv1i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
+    i64 %0)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vid_v_nxv2i8(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv2i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
+    i64 %0)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vid_mask_v_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vid_v_nxv4i8(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv4i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
+    i64 %0)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vid_mask_v_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vid_v_nxv8i8(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv8i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
+    i64 %0)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vid_mask_v_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vid_v_nxv16i8(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv16i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
+    i64 %0)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vid_mask_v_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vid_v_nxv32i8(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv32i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
+    i64 %0)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vid_mask_v_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vid_v_nxv1i16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv1i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
+    i64 %0)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vid_mask_v_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vid_v_nxv2i16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv2i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
+    i64 %0)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vid_mask_v_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vid_v_nxv4i16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv4i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
+    i64 %0)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vid_mask_v_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vid_v_nxv8i16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv8i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
+    i64 %0)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vid_mask_v_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vid_v_nxv16i16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv16i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
+    i64 %0)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vid_mask_v_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vid_v_nxv32i16(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv32i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
+    i64 %0)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vid_mask_v_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vid_v_nxv1i32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv1i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
+    i64 %0)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vid_mask_v_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vid_v_nxv2i32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv2i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
+    i64 %0)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vid_mask_v_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vid_v_nxv4i32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv4i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
+    i64 %0)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vid_mask_v_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vid_v_nxv8i32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv8i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
+    i64 %0)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vid_mask_v_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vid_v_nxv16i32(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv16i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
+    i64 %0)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vid_mask_v_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vid_v_nxv1i64(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv1i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
+    i64 %0)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vid_mask_v_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vid_v_nxv2i64(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv2i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
+    i64 %0)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vid_mask_v_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vid_v_nxv4i64(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv4i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
+    i64 %0)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vid_mask_v_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vid_v_nxv8i64(i64 %0) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_v_nxv8i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
+    i64 %0)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vid_mask_v_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8,ta,mu
+; CHECK:       vid.v {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll
new file mode 100644
index 0000000000000..bc1b1c56bb636
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll
@@ -0,0 +1,722 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
+    <vscale x 1 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_viota_m_nxv2i8_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
+    <vscale x 2 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_viota_mask_m_nxv2i8_nxv2i1(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_viota_m_nxv4i8_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
+    <vscale x 4 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_viota_mask_m_nxv4i8_nxv4i1(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_viota_m_nxv8i8_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
+    <vscale x 8 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_viota_mask_m_nxv8i8_nxv8i1(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_viota_m_nxv16i8_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
+    <vscale x 16 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_viota_mask_m_nxv16i8_nxv16i1(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_viota_m_nxv32i8_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
+    <vscale x 32 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_viota_mask_m_nxv32i8_nxv32i1(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_viota_m_nxv64i8_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
+    <vscale x 64 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_viota_mask_m_nxv64i8_nxv64i1(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i1> %1,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_viota_m_nxv1i16_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
+    <vscale x 1 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_viota_mask_m_nxv1i16_nxv1i1(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_viota_m_nxv2i16_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
+    <vscale x 2 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_viota_mask_m_nxv2i16_nxv2i1(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_viota_m_nxv4i16_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
+    <vscale x 4 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_viota_mask_m_nxv4i16_nxv4i1(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_viota_m_nxv8i16_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
+    <vscale x 8 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_viota_mask_m_nxv8i16_nxv8i1(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_viota_m_nxv16i16_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
+    <vscale x 16 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_viota_mask_m_nxv16i16_nxv16i1(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_viota_m_nxv32i16_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
+    <vscale x 32 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_viota_mask_m_nxv32i16_nxv32i1(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i16_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_viota_m_nxv1i32_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
+    <vscale x 1 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_viota_mask_m_nxv1i32_nxv1i1(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i32_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_viota_m_nxv2i32_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
+    <vscale x 2 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_viota_mask_m_nxv2i32_nxv2i1(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i32_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_viota_m_nxv4i32_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
+    <vscale x 4 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_viota_mask_m_nxv4i32_nxv4i1(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i32_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_viota_m_nxv8i32_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
+    <vscale x 8 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_viota_mask_m_nxv8i32_nxv8i1(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i32_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_viota_m_nxv16i32_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
+    <vscale x 16 x i1> %0,
+    i32 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_viota_mask_m_nxv16i32_nxv16i1(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i32_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll
new file mode 100644
index 0000000000000..7a2783c29a1e7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll
@@ -0,0 +1,882 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_viota_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.viota.nxv1i8(
+    <vscale x 1 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_viota_m_nxv2i8_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv2i8_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
+    <vscale x 2 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_viota_mask_m_nxv2i8_nxv2i1(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_viota_m_nxv4i8_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv4i8_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
+    <vscale x 4 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_viota_mask_m_nxv4i8_nxv4i1(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_viota_m_nxv8i8_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv8i8_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
+    <vscale x 8 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_viota_mask_m_nxv8i8_nxv8i1(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_viota_m_nxv16i8_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv16i8_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
+    <vscale x 16 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_viota_mask_m_nxv16i8_nxv16i1(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_viota_m_nxv32i8_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv32i8_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
+    <vscale x 32 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_viota_mask_m_nxv32i8_nxv32i1(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_viota_m_nxv64i8_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv64i8_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
+    <vscale x 64 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_viota_mask_m_nxv64i8_nxv64i1(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i1> %1,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_viota_m_nxv1i16_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv1i16_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
+    <vscale x 1 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_viota_mask_m_nxv1i16_nxv1i1(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_viota_m_nxv2i16_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv2i16_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
+    <vscale x 2 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_viota_mask_m_nxv2i16_nxv2i1(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_viota_m_nxv4i16_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv4i16_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
+    <vscale x 4 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_viota_mask_m_nxv4i16_nxv4i1(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_viota_m_nxv8i16_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv8i16_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
+    <vscale x 8 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_viota_mask_m_nxv8i16_nxv8i1(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_viota_m_nxv16i16_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv16i16_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
+    <vscale x 16 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_viota_mask_m_nxv16i16_nxv16i1(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_viota_m_nxv32i16_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv32i16_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
+    <vscale x 32 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_viota_mask_m_nxv32i16_nxv32i1(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i16_nxv32i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_viota_m_nxv1i32_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv1i32_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
+    <vscale x 1 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_viota_mask_m_nxv1i32_nxv1i1(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i32_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_viota_m_nxv2i32_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv2i32_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
+    <vscale x 2 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_viota_mask_m_nxv2i32_nxv2i1(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i32_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_viota_m_nxv4i32_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv4i32_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
+    <vscale x 4 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_viota_mask_m_nxv4i32_nxv4i1(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i32_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_viota_m_nxv8i32_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv8i32_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
+    <vscale x 8 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_viota_mask_m_nxv8i32_nxv8i1(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i32_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_viota_m_nxv16i32_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv16i32_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
+    <vscale x 16 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_viota_mask_m_nxv16i32_nxv16i1(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i32_nxv16i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_viota_m_nxv1i64_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv1i64_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(
+    <vscale x 1 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_viota_mask_m_nxv1i64_nxv1i1(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i64_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_viota_m_nxv2i64_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv2i64_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(
+    <vscale x 2 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_viota_mask_m_nxv2i64_nxv2i1(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i64_nxv2i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_viota_m_nxv4i64_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv4i64_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(
+    <vscale x 4 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_viota_mask_m_nxv4i64_nxv4i1(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i64_nxv4i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_viota_m_nxv8i64_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_viota_m_nxv8i64_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(
+    <vscale x 8 x i1> %0,
+    i64 %1)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_viota_mask_m_nxv8i64_nxv8i1(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i64_nxv8i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m8,ta,mu
+; CHECK-NEXT:    viota.m v16, v0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
new file mode 100644
index 0000000000000..ea882a5bf5876
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll
@@ -0,0 +1,1045 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh,+f,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i32> @llvm.riscv.vleff.nxv1i32(
+  <vscale x 1 x i32>*,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vleff_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x i32> @llvm.riscv.vleff.nxv1i32(
+    <vscale x 1 x i32>* %0,
+    i32 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vleff.mask.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vleff_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vleff.mask.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32>* %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vleff.nxv2i32(
+  <vscale x 2 x i32>*,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vleff_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x i32> @llvm.riscv.vleff.nxv2i32(
+    <vscale x 2 x i32>* %0,
+    i32 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vleff.mask.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vleff_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vleff.mask.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32>* %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vleff.nxv4i32(
+  <vscale x 4 x i32>*,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vleff_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x i32> @llvm.riscv.vleff.nxv4i32(
+    <vscale x 4 x i32>* %0,
+    i32 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vleff.mask.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vleff_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vleff.mask.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32>* %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vleff.nxv8i32(
+  <vscale x 8 x i32>*,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vleff_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x i32> @llvm.riscv.vleff.nxv8i32(
+    <vscale x 8 x i32>* %0,
+    i32 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vleff.mask.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vleff_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vleff.mask.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32>* %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vleff.nxv16i32(
+  <vscale x 16 x i32>*,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vleff_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x i32> @llvm.riscv.vleff.nxv16i32(
+    <vscale x 16 x i32>* %0,
+    i32 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vleff.mask.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vleff_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vleff.mask.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32>* %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vleff.nxv1f32(
+  <vscale x 1 x float>*,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vleff_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x float> @llvm.riscv.vleff.nxv1f32(
+    <vscale x 1 x float>* %0,
+    i32 %1)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vleff.mask.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>*,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vleff_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vleff.mask.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float>* %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vleff.nxv2f32(
+  <vscale x 2 x float>*,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vleff_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x float> @llvm.riscv.vleff.nxv2f32(
+    <vscale x 2 x float>* %0,
+    i32 %1)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vleff.mask.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>*,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vleff_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vleff.mask.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float>* %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vleff.nxv4f32(
+  <vscale x 4 x float>*,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vleff_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x float> @llvm.riscv.vleff.nxv4f32(
+    <vscale x 4 x float>* %0,
+    i32 %1)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vleff.mask.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>*,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vleff_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vleff.mask.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float>* %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vleff.nxv8f32(
+  <vscale x 8 x float>*,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vleff_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x float> @llvm.riscv.vleff.nxv8f32(
+    <vscale x 8 x float>* %0,
+    i32 %1)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vleff.mask.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>*,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vleff_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vleff.mask.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float>* %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vleff.nxv16f32(
+  <vscale x 16 x float>*,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vleff_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x float> @llvm.riscv.vleff.nxv16f32(
+    <vscale x 16 x float>* %0,
+    i32 %1)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vleff.mask.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>*,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vleff_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vleff.mask.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float>* %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vleff.nxv1i16(
+  <vscale x 1 x i16>*,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vleff_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x i16> @llvm.riscv.vleff.nxv1i16(
+    <vscale x 1 x i16>* %0,
+    i32 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vleff.mask.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>*,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vleff_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vleff.mask.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16>* %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vleff.nxv2i16(
+  <vscale x 2 x i16>*,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vleff_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x i16> @llvm.riscv.vleff.nxv2i16(
+    <vscale x 2 x i16>* %0,
+    i32 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vleff.mask.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>*,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vleff_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vleff.mask.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16>* %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vleff.nxv4i16(
+  <vscale x 4 x i16>*,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vleff_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x i16> @llvm.riscv.vleff.nxv4i16(
+    <vscale x 4 x i16>* %0,
+    i32 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vleff.mask.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>*,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vleff_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vleff.mask.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16>* %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vleff.nxv8i16(
+  <vscale x 8 x i16>*,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vleff_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x i16> @llvm.riscv.vleff.nxv8i16(
+    <vscale x 8 x i16>* %0,
+    i32 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vleff.mask.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>*,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vleff_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vleff.mask.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16>* %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vleff.nxv16i16(
+  <vscale x 16 x i16>*,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vleff_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x i16> @llvm.riscv.vleff.nxv16i16(
+    <vscale x 16 x i16>* %0,
+    i32 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vleff.mask.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>*,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vleff_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vleff.mask.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16>* %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vleff.nxv32i16(
+  <vscale x 32 x i16>*,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vleff_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 32 x i16> @llvm.riscv.vleff.nxv32i16(
+    <vscale x 32 x i16>* %0,
+    i32 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vleff.mask.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>*,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vleff_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vleff.mask.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16>* %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vleff.nxv1f16(
+  <vscale x 1 x half>*,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vleff_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x half> @llvm.riscv.vleff.nxv1f16(
+    <vscale x 1 x half>* %0,
+    i32 %1)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vleff.mask.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>*,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vleff_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vleff.mask.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half>* %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vleff.nxv2f16(
+  <vscale x 2 x half>*,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vleff_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x half> @llvm.riscv.vleff.nxv2f16(
+    <vscale x 2 x half>* %0,
+    i32 %1)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vleff.mask.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>*,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vleff_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vleff.mask.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half>* %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vleff.nxv4f16(
+  <vscale x 4 x half>*,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vleff_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x half> @llvm.riscv.vleff.nxv4f16(
+    <vscale x 4 x half>* %0,
+    i32 %1)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vleff.mask.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>*,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vleff_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vleff.mask.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half>* %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vleff.nxv8f16(
+  <vscale x 8 x half>*,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vleff_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x half> @llvm.riscv.vleff.nxv8f16(
+    <vscale x 8 x half>* %0,
+    i32 %1)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vleff.mask.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>*,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vleff_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vleff.mask.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half>* %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vleff.nxv16f16(
+  <vscale x 16 x half>*,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vleff_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x half> @llvm.riscv.vleff.nxv16f16(
+    <vscale x 16 x half>* %0,
+    i32 %1)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vleff.mask.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>*,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vleff_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vleff.mask.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half>* %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vleff.nxv32f16(
+  <vscale x 32 x half>*,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vleff_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 32 x half> @llvm.riscv.vleff.nxv32f16(
+    <vscale x 32 x half>* %0,
+    i32 %1)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vleff.mask.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>*,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vleff_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vleff.mask.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half>* %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vleff.nxv1i8(
+  <vscale x 1 x i8>*,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vleff_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x i8> @llvm.riscv.vleff.nxv1i8(
+    <vscale x 1 x i8>* %0,
+    i32 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vleff.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>*,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vleff_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vleff.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8>* %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vleff.nxv2i8(
+  <vscale x 2 x i8>*,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vleff_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x i8> @llvm.riscv.vleff.nxv2i8(
+    <vscale x 2 x i8>* %0,
+    i32 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vleff.mask.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>*,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vleff_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vleff.mask.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8>* %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vleff.nxv4i8(
+  <vscale x 4 x i8>*,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vleff_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x i8> @llvm.riscv.vleff.nxv4i8(
+    <vscale x 4 x i8>* %0,
+    i32 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vleff.mask.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>*,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vleff_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vleff.mask.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8>* %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vleff.nxv8i8(
+  <vscale x 8 x i8>*,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vleff_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x i8> @llvm.riscv.vleff.nxv8i8(
+    <vscale x 8 x i8>* %0,
+    i32 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vleff.mask.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>*,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vleff_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vleff.mask.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8>* %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vleff.nxv16i8(
+  <vscale x 16 x i8>*,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vleff_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x i8> @llvm.riscv.vleff.nxv16i8(
+    <vscale x 16 x i8>* %0,
+    i32 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vleff.mask.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>*,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vleff_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vleff.mask.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8>* %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vleff.nxv32i8(
+  <vscale x 32 x i8>*,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vleff_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 32 x i8> @llvm.riscv.vleff.nxv32i8(
+    <vscale x 32 x i8>* %0,
+    i32 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vleff.mask.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>*,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vleff_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vleff.mask.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8>* %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vleff.nxv64i8(
+  <vscale x 64 x i8>*,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vleff_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 64 x i8> @llvm.riscv.vleff.nxv64i8(
+    <vscale x 64 x i8>* %0,
+    i32 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vleff.mask.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>*,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vleff_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vleff.mask.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8>* %1,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 64 x i8> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
new file mode 100644
index 0000000000000..560221c2536b1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll
@@ -0,0 +1,1333 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh,+f,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i64> @llvm.riscv.vleff.nxv1i64(
+  <vscale x 1 x i64>*,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vleff_v_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x i64> @llvm.riscv.vleff.nxv1i64(
+    <vscale x 1 x i64>* %0,
+    i64 %1)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vleff.mask.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>*,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vleff_mask_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vleff.mask.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64>* %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vleff.nxv2i64(
+  <vscale x 2 x i64>*,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vleff_v_nxv2i64_nxv2i64(<vscale x 2 x i64>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x i64> @llvm.riscv.vleff.nxv2i64(
+    <vscale x 2 x i64>* %0,
+    i64 %1)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vleff.mask.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>*,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vleff_mask_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64>* %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vleff.mask.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64>* %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vleff.nxv4i64(
+  <vscale x 4 x i64>*,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vleff_v_nxv4i64_nxv4i64(<vscale x 4 x i64>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x i64> @llvm.riscv.vleff.nxv4i64(
+    <vscale x 4 x i64>* %0,
+    i64 %1)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vleff.mask.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>*,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vleff_mask_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64>* %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vleff.mask.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64>* %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vleff.nxv8i64(
+  <vscale x 8 x i64>*,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vleff_v_nxv8i64_nxv8i64(<vscale x 8 x i64>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x i64> @llvm.riscv.vleff.nxv8i64(
+    <vscale x 8 x i64>* %0,
+    i64 %1)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vleff.mask.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>*,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vleff_mask_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64>* %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vleff.mask.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64>* %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vleff.nxv1f64(
+  <vscale x 1 x double>*,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vleff_v_nxv1f64_nxv1f64(<vscale x 1 x double>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x double> @llvm.riscv.vleff.nxv1f64(
+    <vscale x 1 x double>* %0,
+    i64 %1)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vleff.mask.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>*,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vleff_mask_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x double> @llvm.riscv.vleff.mask.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double>* %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vleff.nxv2f64(
+  <vscale x 2 x double>*,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vleff_v_nxv2f64_nxv2f64(<vscale x 2 x double>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x double> @llvm.riscv.vleff.nxv2f64(
+    <vscale x 2 x double>* %0,
+    i64 %1)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vleff.mask.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>*,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vleff_mask_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double>* %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x double> @llvm.riscv.vleff.mask.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double>* %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vleff.nxv4f64(
+  <vscale x 4 x double>*,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vleff_v_nxv4f64_nxv4f64(<vscale x 4 x double>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x double> @llvm.riscv.vleff.nxv4f64(
+    <vscale x 4 x double>* %0,
+    i64 %1)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vleff.mask.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>*,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vleff_mask_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double>* %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x double> @llvm.riscv.vleff.mask.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double>* %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vleff.nxv8f64(
+  <vscale x 8 x double>*,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vleff_v_nxv8f64_nxv8f64(<vscale x 8 x double>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x double> @llvm.riscv.vleff.nxv8f64(
+    <vscale x 8 x double>* %0,
+    i64 %1)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vleff.mask.nxv8f64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>*,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vleff_mask_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double>* %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vle64ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x double> @llvm.riscv.vleff.mask.nxv8f64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double>* %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vleff.nxv1i32(
+  <vscale x 1 x i32>*,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vleff_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x i32> @llvm.riscv.vleff.nxv1i32(
+    <vscale x 1 x i32>* %0,
+    i64 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vleff.mask.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>*,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vleff_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vleff.mask.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32>* %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vleff.nxv2i32(
+  <vscale x 2 x i32>*,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vleff_v_nxv2i32_nxv2i32(<vscale x 2 x i32>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x i32> @llvm.riscv.vleff.nxv2i32(
+    <vscale x 2 x i32>* %0,
+    i64 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vleff.mask.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>*,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vleff_mask_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32>* %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vleff.mask.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32>* %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vleff.nxv4i32(
+  <vscale x 4 x i32>*,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vleff_v_nxv4i32_nxv4i32(<vscale x 4 x i32>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x i32> @llvm.riscv.vleff.nxv4i32(
+    <vscale x 4 x i32>* %0,
+    i64 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vleff.mask.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>*,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vleff_mask_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32>* %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vleff.mask.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32>* %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vleff.nxv8i32(
+  <vscale x 8 x i32>*,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vleff_v_nxv8i32_nxv8i32(<vscale x 8 x i32>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x i32> @llvm.riscv.vleff.nxv8i32(
+    <vscale x 8 x i32>* %0,
+    i64 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vleff.mask.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>*,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vleff_mask_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32>* %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vleff.mask.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32>* %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vleff.nxv16i32(
+  <vscale x 16 x i32>*,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vleff_v_nxv16i32_nxv16i32(<vscale x 16 x i32>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x i32> @llvm.riscv.vleff.nxv16i32(
+    <vscale x 16 x i32>* %0,
+    i64 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vleff.mask.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>*,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vleff_mask_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32>* %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vleff.mask.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32>* %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vleff.nxv1f32(
+  <vscale x 1 x float>*,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vleff_v_nxv1f32_nxv1f32(<vscale x 1 x float>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x float> @llvm.riscv.vleff.nxv1f32(
+    <vscale x 1 x float>* %0,
+    i64 %1)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vleff.mask.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>*,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vleff_mask_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x float> @llvm.riscv.vleff.mask.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float>* %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vleff.nxv2f32(
+  <vscale x 2 x float>*,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vleff_v_nxv2f32_nxv2f32(<vscale x 2 x float>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x float> @llvm.riscv.vleff.nxv2f32(
+    <vscale x 2 x float>* %0,
+    i64 %1)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vleff.mask.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>*,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vleff_mask_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float>* %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x float> @llvm.riscv.vleff.mask.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float>* %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vleff.nxv4f32(
+  <vscale x 4 x float>*,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vleff_v_nxv4f32_nxv4f32(<vscale x 4 x float>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x float> @llvm.riscv.vleff.nxv4f32(
+    <vscale x 4 x float>* %0,
+    i64 %1)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vleff.mask.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>*,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vleff_mask_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float>* %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x float> @llvm.riscv.vleff.mask.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float>* %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vleff.nxv8f32(
+  <vscale x 8 x float>*,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vleff_v_nxv8f32_nxv8f32(<vscale x 8 x float>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x float> @llvm.riscv.vleff.nxv8f32(
+    <vscale x 8 x float>* %0,
+    i64 %1)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vleff.mask.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>*,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vleff_mask_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float>* %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x float> @llvm.riscv.vleff.mask.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float>* %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vleff.nxv16f32(
+  <vscale x 16 x float>*,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vleff_v_nxv16f32_nxv16f32(<vscale x 16 x float>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x float> @llvm.riscv.vleff.nxv16f32(
+    <vscale x 16 x float>* %0,
+    i64 %1)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vleff.mask.nxv16f32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>*,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vleff_mask_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float>* %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16f32_nxv16f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vle32ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x float> @llvm.riscv.vleff.mask.nxv16f32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float>* %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vleff.nxv1i16(
+  <vscale x 1 x i16>*,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vleff_v_nxv1i16_nxv1i16(<vscale x 1 x i16>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x i16> @llvm.riscv.vleff.nxv1i16(
+    <vscale x 1 x i16>* %0,
+    i64 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vleff.mask.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>*,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vleff_mask_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vleff.mask.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16>* %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vleff.nxv2i16(
+  <vscale x 2 x i16>*,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vleff_v_nxv2i16_nxv2i16(<vscale x 2 x i16>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x i16> @llvm.riscv.vleff.nxv2i16(
+    <vscale x 2 x i16>* %0,
+    i64 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vleff.mask.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>*,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vleff_mask_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16>* %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vleff.mask.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16>* %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vleff.nxv4i16(
+  <vscale x 4 x i16>*,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vleff_v_nxv4i16_nxv4i16(<vscale x 4 x i16>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x i16> @llvm.riscv.vleff.nxv4i16(
+    <vscale x 4 x i16>* %0,
+    i64 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vleff.mask.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>*,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vleff_mask_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16>* %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vleff.mask.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16>* %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vleff.nxv8i16(
+  <vscale x 8 x i16>*,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vleff_v_nxv8i16_nxv8i16(<vscale x 8 x i16>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x i16> @llvm.riscv.vleff.nxv8i16(
+    <vscale x 8 x i16>* %0,
+    i64 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vleff.mask.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>*,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vleff_mask_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16>* %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vleff.mask.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16>* %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vleff.nxv16i16(
+  <vscale x 16 x i16>*,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vleff_v_nxv16i16_nxv16i16(<vscale x 16 x i16>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x i16> @llvm.riscv.vleff.nxv16i16(
+    <vscale x 16 x i16>* %0,
+    i64 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vleff.mask.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>*,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vleff_mask_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16>* %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vleff.mask.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16>* %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vleff.nxv32i16(
+  <vscale x 32 x i16>*,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vleff_v_nxv32i16_nxv32i16(<vscale x 32 x i16>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 32 x i16> @llvm.riscv.vleff.nxv32i16(
+    <vscale x 32 x i16>* %0,
+    i64 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vleff.mask.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>*,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vleff_mask_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16>* %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vleff.mask.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16>* %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vleff.nxv1f16(
+  <vscale x 1 x half>*,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vleff_v_nxv1f16_nxv1f16(<vscale x 1 x half>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x half> @llvm.riscv.vleff.nxv1f16(
+    <vscale x 1 x half>* %0,
+    i64 %1)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vleff.mask.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>*,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vleff_mask_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x half> @llvm.riscv.vleff.mask.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half>* %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vleff.nxv2f16(
+  <vscale x 2 x half>*,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vleff_v_nxv2f16_nxv2f16(<vscale x 2 x half>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x half> @llvm.riscv.vleff.nxv2f16(
+    <vscale x 2 x half>* %0,
+    i64 %1)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vleff.mask.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>*,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vleff_mask_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half>* %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x half> @llvm.riscv.vleff.mask.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half>* %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vleff.nxv4f16(
+  <vscale x 4 x half>*,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vleff_v_nxv4f16_nxv4f16(<vscale x 4 x half>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x half> @llvm.riscv.vleff.nxv4f16(
+    <vscale x 4 x half>* %0,
+    i64 %1)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vleff.mask.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>*,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vleff_mask_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half>* %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x half> @llvm.riscv.vleff.mask.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half>* %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vleff.nxv8f16(
+  <vscale x 8 x half>*,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vleff_v_nxv8f16_nxv8f16(<vscale x 8 x half>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x half> @llvm.riscv.vleff.nxv8f16(
+    <vscale x 8 x half>* %0,
+    i64 %1)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vleff.mask.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>*,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vleff_mask_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half>* %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x half> @llvm.riscv.vleff.mask.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half>* %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vleff.nxv16f16(
+  <vscale x 16 x half>*,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vleff_v_nxv16f16_nxv16f16(<vscale x 16 x half>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x half> @llvm.riscv.vleff.nxv16f16(
+    <vscale x 16 x half>* %0,
+    i64 %1)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vleff.mask.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>*,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vleff_mask_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half>* %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x half> @llvm.riscv.vleff.mask.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half>* %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vleff.nxv32f16(
+  <vscale x 32 x half>*,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vleff_v_nxv32f16_nxv32f16(<vscale x 32 x half>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 32 x half> @llvm.riscv.vleff.nxv32f16(
+    <vscale x 32 x half>* %0,
+    i64 %1)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vleff.mask.nxv32f16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>*,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vleff_mask_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half>* %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32f16_nxv32f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vle16ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 32 x half> @llvm.riscv.vleff.mask.nxv32f16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half>* %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vleff.nxv1i8(
+  <vscale x 1 x i8>*,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vleff_v_nxv1i8_nxv1i8(<vscale x 1 x i8>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 1 x i8> @llvm.riscv.vleff.nxv1i8(
+    <vscale x 1 x i8>* %0,
+    i64 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vleff.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>*,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vleff_mask_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8>* %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vleff.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8>* %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vleff.nxv2i8(
+  <vscale x 2 x i8>*,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vleff_v_nxv2i8_nxv2i8(<vscale x 2 x i8>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 2 x i8> @llvm.riscv.vleff.nxv2i8(
+    <vscale x 2 x i8>* %0,
+    i64 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vleff.mask.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>*,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vleff_mask_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8>* %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vleff.mask.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8>* %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vleff.nxv4i8(
+  <vscale x 4 x i8>*,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vleff_v_nxv4i8_nxv4i8(<vscale x 4 x i8>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 4 x i8> @llvm.riscv.vleff.nxv4i8(
+    <vscale x 4 x i8>* %0,
+    i64 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vleff.mask.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>*,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vleff_mask_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8>* %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vleff.mask.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8>* %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vleff.nxv8i8(
+  <vscale x 8 x i8>*,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vleff_v_nxv8i8_nxv8i8(<vscale x 8 x i8>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 8 x i8> @llvm.riscv.vleff.nxv8i8(
+    <vscale x 8 x i8>* %0,
+    i64 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vleff.mask.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>*,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vleff_mask_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8>* %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vleff.mask.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8>* %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vleff.nxv16i8(
+  <vscale x 16 x i8>*,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vleff_v_nxv16i8_nxv16i8(<vscale x 16 x i8>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 16 x i8> @llvm.riscv.vleff.nxv16i8(
+    <vscale x 16 x i8>* %0,
+    i64 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vleff.mask.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>*,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vleff_mask_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8>* %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vleff.mask.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8>* %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vleff.nxv32i8(
+  <vscale x 32 x i8>*,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vleff_v_nxv32i8_nxv32i8(<vscale x 32 x i8>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 32 x i8> @llvm.riscv.vleff.nxv32i8(
+    <vscale x 32 x i8>* %0,
+    i64 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vleff.mask.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>*,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vleff_mask_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8>* %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vleff.mask.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8>* %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vleff.nxv64i8(
+  <vscale x 64 x i8>*,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vleff_v_nxv64i8_nxv64i8(<vscale x 64 x i8>* %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_v_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0)
+  %a = call <vscale x 64 x i8> @llvm.riscv.vleff.nxv64i8(
+    <vscale x 64 x i8>* %0,
+    i64 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vleff.mask.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>*,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vleff_mask_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8>* %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vleff_mask_v_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vle8ff.v {{v[0-9]+}}, (a0), v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vleff.mask.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8>* %1,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 64 x i8> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
new file mode 100644
index 0000000000000..24a2a82f6ff05
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
@@ -0,0 +1,1261 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
new file mode 100644
index 0000000000000..9e7d36368d34f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll
@@ -0,0 +1,1513 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vmacc_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vmacc_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vmacc_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmacc.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmacc.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmacc.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmacc.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmacc.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmacc.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmacc.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmacc.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmacc.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmacc.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmacc.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmacc.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmacc.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmacc.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmacc.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmacc.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv1i64_i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv1i64_i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmacc.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv2i64_i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv2i64_i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmacc.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_vx_nxv4i64_i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmacc_mask_vx_nxv4i64_i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmacc.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmacc.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
new file mode 100644
index 0000000000000..92744c6e7df40
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
@@ -0,0 +1,1261 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
new file mode 100644
index 0000000000000..a6d229dcc7066
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmadd-rv64.ll
@@ -0,0 +1,1513 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vmadd_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vmadd_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vmadd_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmadd.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmadd.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmadd.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmadd.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmadd.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmadd.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmadd.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmadd.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmadd.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmadd.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmadd.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmadd.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmadd.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmadd.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmadd.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmadd.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv1i64_i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv1i64_i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmadd.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv2i64_i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv2i64_i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmadd.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_vx_nxv4i64_i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmadd_mask_vx_nxv4i64_i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmadd.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmadd.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll
new file mode 100644
index 0000000000000..58155699a9541
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll
new file mode 100644
index 0000000000000..28710a511ecb2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmand_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll
new file mode 100644
index 0000000000000..efc39d222235d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmandnot.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmandnot_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmandnot.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmandnot.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmandnot_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmandnot.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmandnot.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmandnot_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmandnot.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmandnot.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmandnot_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmandnot.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmandnot.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmandnot_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmandnot.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmandnot.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmandnot_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmandnot.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmandnot.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmandnot_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmandnot.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll
new file mode 100644
index 0000000000000..51061af58af69
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmandnot.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmandnot_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmandnot.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmandnot.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmandnot_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmandnot.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmandnot.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmandnot_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmandnot.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmandnot.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmandnot_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmandnot.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmandnot.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmandnot_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmandnot.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmandnot.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmandnot_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmandnot.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmandnot.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmandnot_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmandnot_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmandnot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmandnot.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
new file mode 100644
index 0000000000000..320925f178d07
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll
@@ -0,0 +1,973 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
new file mode 100644
index 0000000000000..c8a8f113bf4ef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll
@@ -0,0 +1,1189 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vvm_nxv8i64_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8
+; CHECK:       vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
+  %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  i64,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vxm_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8
+; CHECK:       vmerge.vxm {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0
+  %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmerge.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmerge.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmerge.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmerge.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmerge.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmerge.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 64 x i8> @llvm.riscv.vmerge.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmerge.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmerge.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmerge.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmerge.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmerge.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 32 x i16> @llvm.riscv.vmerge.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmerge.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmerge.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmerge.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 16 x i32> @llvm.riscv.vmerge.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmerge.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmerge.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmerge.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmerge_vim_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8
+; CHECK:       vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 9, v0
+  %a = call <vscale x 8 x i64> @llvm.riscv.vmerge.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 9,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
new file mode 100644
index 0000000000000..256263bae0bb2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll
@@ -0,0 +1,757 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x half> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x half> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x half> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x half> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfeq_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x half> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x float> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x float> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x float> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x float> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfeq_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
new file mode 100644
index 0000000000000..577fa6d2ce198
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll
@@ -0,0 +1,1009 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x half> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x half> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x half> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x half> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfeq_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x half> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x float> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x float> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x float> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x float> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x double> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x double> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vv_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfeq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x double> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfeq_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfeq.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
new file mode 100644
index 0000000000000..42189c52c2285
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll
@@ -0,0 +1,361 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfge_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
new file mode 100644
index 0000000000000..8d6af219ce133
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll
@@ -0,0 +1,481 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfge_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfge_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfge.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
new file mode 100644
index 0000000000000..724d0e8afc0f6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll
@@ -0,0 +1,361 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfgt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
new file mode 100644
index 0000000000000..6145ac78ae073
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll
@@ -0,0 +1,481 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfgt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfgt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfgt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
new file mode 100644
index 0000000000000..870c1fdd7bc54
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll
@@ -0,0 +1,757 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x half> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x half> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x half> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x half> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfle_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x half> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x float> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x float> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x float> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x float> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
new file mode 100644
index 0000000000000..5d5f3cc4de9a8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
@@ -0,0 +1,1009 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x half> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x half> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x half> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x half> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfle_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x half> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x float> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x float> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x float> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x float> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x double> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x double> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vv_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x double> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfle_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfle.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
new file mode 100644
index 0000000000000..95d1046eb9925
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
@@ -0,0 +1,757 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x half> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x half> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x half> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x half> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmflt_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x half> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x float> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x float> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x float> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x float> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmflt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
new file mode 100644
index 0000000000000..80eebbe0c8dc9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
@@ -0,0 +1,1009 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x half> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x half> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x half> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x half> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmflt_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x half> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x float> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x float> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x float> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x float> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x double> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x double> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vv_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmflt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x double> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmflt_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmflt.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
new file mode 100644
index 0000000000000..e98d68159bf48
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
@@ -0,0 +1,757 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x half> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x half> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x half> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x half> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfne_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x half> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x float> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x float> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x float> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x float> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfne_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
new file mode 100644
index 0000000000000..59e85968efbfb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
@@ -0,0 +1,1009 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
+    <vscale x 1 x half> %1,
+    <vscale x 1 x half> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %2,
+    <vscale x 1 x half> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
+    <vscale x 2 x half> %1,
+    <vscale x 2 x half> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %2,
+    <vscale x 2 x half> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
+    <vscale x 4 x half> %1,
+    <vscale x 4 x half> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %2,
+    <vscale x 4 x half> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
+    <vscale x 8 x half> %1,
+    <vscale x 8 x half> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %2,
+    <vscale x 8 x half> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfne_vv_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
+    <vscale x 16 x half> %1,
+    <vscale x 16 x half> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %2,
+    <vscale x 16 x half> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
+    <vscale x 1 x float> %1,
+    <vscale x 1 x float> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %2,
+    <vscale x 1 x float> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
+    <vscale x 2 x float> %1,
+    <vscale x 2 x float> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %2,
+    <vscale x 2 x float> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
+    <vscale x 4 x float> %1,
+    <vscale x 4 x float> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %2,
+    <vscale x 4 x float> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_vv_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
+    <vscale x 8 x float> %1,
+    <vscale x 8 x float> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %2,
+    <vscale x 8 x float> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vv_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
+    <vscale x 1 x double> %1,
+    <vscale x 1 x double> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %2,
+    <vscale x 1 x double> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vv_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
+    <vscale x 2 x double> %1,
+    <vscale x 2 x double> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %2,
+    <vscale x 2 x double> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vv_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vv_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
+    <vscale x 4 x double> %1,
+    <vscale x 4 x double> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %2,
+    <vscale x 4 x double> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
+  <vscale x 1 x half>,
+  half,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f16_f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
+    <vscale x 1 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x half>,
+  half,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x half> %1,
+    half %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
+  <vscale x 2 x half>,
+  half,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f16_f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
+    <vscale x 2 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x half>,
+  half,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x half> %1,
+    half %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
+  <vscale x 4 x half>,
+  half,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f16_f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
+    <vscale x 4 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x half>,
+  half,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x half> %1,
+    half %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
+  <vscale x 8 x half>,
+  half,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f16_f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
+    <vscale x 8 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x half>,
+  half,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x half> %1,
+    half %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
+  <vscale x 16 x half>,
+  half,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfne_vf_nxv16f16_f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
+    <vscale x 16 x half> %0,
+    half %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x half>,
+  half,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x half> %1,
+    half %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
+  <vscale x 1 x float>,
+  float,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f32_f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
+    <vscale x 1 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x float>,
+  float,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x float> %1,
+    float %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
+  <vscale x 2 x float>,
+  float,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f32_f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
+    <vscale x 2 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x float>,
+  float,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x float> %1,
+    float %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
+  <vscale x 4 x float>,
+  float,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f32_f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
+    <vscale x 4 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x float>,
+  float,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x float> %1,
+    float %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
+  <vscale x 8 x float>,
+  float,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_vf_nxv8f32_f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
+    <vscale x 8 x float> %0,
+    float %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x float>,
+  float,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x float> %1,
+    float %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
+  <vscale x 1 x double>,
+  double,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_vf_nxv1f64_f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
+    <vscale x 1 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x double>,
+  double,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x double> %1,
+    double %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
+  <vscale x 2 x double>,
+  double,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_vf_nxv2f64_f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
+    <vscale x 2 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x double>,
+  double,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x double> %1,
+    double %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
+  <vscale x 4 x double>,
+  double,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_vf_nxv4f64_f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
+    <vscale x 4 x double> %0,
+    double %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x double>,
+  double,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmfne.vf {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x double> %1,
+    double %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll
new file mode 100644
index 0000000000000..5e5d1f613ce7a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmnand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmnand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmnand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmnand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmnand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmnand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmnand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll
new file mode 100644
index 0000000000000..aa4c2b3e927a2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmnand_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmnand_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmnand_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmnand_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmnand_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmnand_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmnand_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnand_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmnand.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll
new file mode 100644
index 0000000000000..ae9ff38377ac0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll
new file mode 100644
index 0000000000000..454599c19913a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmnor.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmnor.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmnor.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmnor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmnor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmnor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmnor_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmnor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll
new file mode 100644
index 0000000000000..09db9ddb2b69e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll
new file mode 100644
index 0000000000000..ee9cd0ba85ceb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmor.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmor.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmor.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmor_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll
new file mode 100644
index 0000000000000..175bf26051af5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmornot.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmornot_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmornot.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmornot.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmornot_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmornot.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmornot.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmornot_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmornot.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmornot.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmornot_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmornot.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmornot.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmornot_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmornot.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmornot.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmornot_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmornot.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmornot.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmornot_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmornot.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll
new file mode 100644
index 0000000000000..96cf32b3640d2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmornot.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmornot_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmornot.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmornot.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmornot_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmornot.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmornot.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmornot_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmornot.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmornot.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmornot_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmornot.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmornot.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmornot_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmornot.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmornot.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmornot_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmornot.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmornot.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmornot_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmornot_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmornot.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmornot.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
new file mode 100644
index 0000000000000..b0ee5ab3a27fa
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i32 %1)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i32 %1)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i32 %1)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i32 %1)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i32 %1)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i32 %1)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i32 %1)
+  ret <vscale x 64 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
new file mode 100644
index 0000000000000..3dce4a5375237
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i64 %1)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i64 %1)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i64 %1)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i64 %1)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i64 %1)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i64 %1)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i64 %1)
+  ret <vscale x 64 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsbf.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
new file mode 100644
index 0000000000000..bc96a2394d5eb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
@@ -0,0 +1,1681 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmseq_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmseq_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmseq_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmseq_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
new file mode 100644
index 0000000000000..7e7fc156096aa
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll
@@ -0,0 +1,2017 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmseq_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmseq.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmseq_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmseq.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmseq_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmseq_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmseq_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmseq_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmseq_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmseq_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmseq_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmseq_mask_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmseq.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
new file mode 100644
index 0000000000000..13d77814f9729
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
@@ -0,0 +1,1021 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
new file mode 100644
index 0000000000000..3a05a5e04c6b8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll
@@ -0,0 +1,1225 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsgt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgt_mask_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsgt.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
new file mode 100644
index 0000000000000..6cd44a8d2d896
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
@@ -0,0 +1,1021 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
new file mode 100644
index 0000000000000..ca2d4c3c21568
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll
@@ -0,0 +1,1225 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsgtu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsgtu_mask_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsgtu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
new file mode 100644
index 0000000000000..97fca5b2bc4a4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i32 %1)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i32 %1)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i32 %1)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i32 %1)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i32 %1)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i32 %1)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i32 %1)
+  ret <vscale x 64 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
new file mode 100644
index 0000000000000..280509a63fe4e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsif_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i64 %1)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i64 %1)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i64 %1)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i64 %1)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i64 %1)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i64 %1)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i64 %1)
+  ret <vscale x 64 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsif.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
new file mode 100644
index 0000000000000..e86b0ef34494e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
@@ -0,0 +1,1681 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsle_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsle_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsle_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsle_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
new file mode 100644
index 0000000000000..2f33fb15d0fd4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll
@@ -0,0 +1,2017 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsle_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsle.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsle_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsle.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsle_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsle_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsle_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsle_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsle_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsle_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsle_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsle_mask_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsle.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
new file mode 100644
index 0000000000000..7ac727aa494e5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
@@ -0,0 +1,1681 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
new file mode 100644
index 0000000000000..bc91e3f98696e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll
@@ -0,0 +1,2017 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsleu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsleu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsleu_mask_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsleu.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
new file mode 100644
index 0000000000000..68997a6e45556
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
@@ -0,0 +1,1261 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmslt_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmslt_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
new file mode 100644
index 0000000000000..78178c05c58b7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
@@ -0,0 +1,1513 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmslt_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmslt.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmslt_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmslt.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
new file mode 100644
index 0000000000000..5bb1497604ed0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
@@ -0,0 +1,1261 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsltu_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsltu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
new file mode 100644
index 0000000000000..e085ab569720f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll
@@ -0,0 +1,1513 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsltu_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsltu.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsltu_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsltu.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
new file mode 100644
index 0000000000000..0d36d104357fd
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
@@ -0,0 +1,1681 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsne_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsne_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsne_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsne_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
new file mode 100644
index 0000000000000..960b9d0d03d6d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll
@@ -0,0 +1,2017 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vv_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i8> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vv_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i8> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vv_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i8> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vv_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i8> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vv_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i8> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsne_vv_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %4)
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i8> %3,
+    <vscale x 32 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vv_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i16> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vv_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i16> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vv_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i16> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vv_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i16> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vv_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %4)
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i16> %3,
+    <vscale x 16 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vv_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i32> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vv_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i32> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vv_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i32> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vv_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %4)
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i32> %3,
+    <vscale x 8 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vv_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i64> %3,
+    <vscale x 1 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vv_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i64> %3,
+    <vscale x 2 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vv_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsne.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %4)
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i64> %3,
+    <vscale x 4 x i1> %mask,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vx_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vx_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsne_vx_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vx_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vx_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vx_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vx_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vx_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vx_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsne.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsne_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 32 x i1> @intrinsic_vmsne_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 16 x i1> @intrinsic_vmsne_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 8 x i1> @intrinsic_vmsne_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 1 x i1> @intrinsic_vmsne_mask_vi_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 2 x i1> @intrinsic_vmsne_mask_vi_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i1> %a
+}
+
+define <vscale x 4 x i1> @intrinsic_vmsne_mask_vi_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsne_mask_vi_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vmsne.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
new file mode 100644
index 0000000000000..8fa635bf3fe1f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i32 %1)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i32 %1)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i32 %1)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i32 %1)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i32 %1)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i32 %1)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i32 %1)
+  ret <vscale x 64 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
new file mode 100644
index 0000000000000..fab86d873002d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsof_m_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i64 %1)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i64 %1)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i64 %1)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i64 %1)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i64 %1)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i64 %1)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i64 %1)
+  ret <vscale x 64 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vmsof.m {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll
index d22ac605a20b6..2fff963c5d195 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv32.ll
@@ -1,505 +1,593 @@
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i8(
-  i8,
+declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
+  <vscale x 1 x i8>,
   i32);
 
-define <vscale x 1 x i8> @intrinsic_vmv.v.x_x_nxv1i8_i8(i8 %0, i32 %1) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,mf8
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
+    <vscale x 1 x i8> %0,
     i32 %1)
 
   ret <vscale x 1 x i8> %a
 }
 
-declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i8(
-  i8,
+declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8(
+  <vscale x 2 x i8>,
   i32);
 
-define <vscale x 2 x i8> @intrinsic_vmv.v.x_x_nxv2i8_i8(i8 %0, i32 %1) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmv.v.v_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,mf4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8(
+    <vscale x 2 x i8> %0,
     i32 %1)
 
   ret <vscale x 2 x i8> %a
 }
 
-declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i8(
-  i8,
+declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8(
+  <vscale x 4 x i8>,
   i32);
 
-define <vscale x 4 x i8> @intrinsic_vmv.v.x_x_nxv4i8_i8(i8 %0, i32 %1) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmv.v.v_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,mf2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8(
+    <vscale x 4 x i8> %0,
     i32 %1)
 
   ret <vscale x 4 x i8> %a
 }
 
-declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i8(
-  i8,
+declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8(
+  <vscale x 8 x i8>,
   i32);
 
-define <vscale x 8 x i8> @intrinsic_vmv.v.x_x_nxv8i8_i8(i8 %0, i32 %1) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmv.v.v_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,m1
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8(
+    <vscale x 8 x i8> %0,
     i32 %1)
 
   ret <vscale x 8 x i8> %a
 }
 
-declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i8(
-  i8,
+declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8(
+  <vscale x 16 x i8>,
   i32);
 
-define <vscale x 16 x i8> @intrinsic_vmv.v.x_x_nxv16i8_i8(i8 %0, i32 %1) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmv.v.v_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,m2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8(
+    <vscale x 16 x i8> %0,
     i32 %1)
 
   ret <vscale x 16 x i8> %a
 }
 
-declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i8(
-  i8,
+declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8(
+  <vscale x 32 x i8>,
   i32);
 
-define <vscale x 32 x i8> @intrinsic_vmv.v.x_x_nxv32i8_i8(i8 %0, i32 %1) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmv.v.v_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,m4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8(
+    <vscale x 32 x i8> %0,
     i32 %1)
 
   ret <vscale x 32 x i8> %a
 }
 
-declare <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i8(
-  i8,
+declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8(
+  <vscale x 64 x i8>,
   i32);
 
-define <vscale x 64 x i8> @intrinsic_vmv.v.x_x_nxv64i8_i8(i8 %0, i32 %1) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmv.v.v_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,m8
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8(
+    <vscale x 64 x i8> %0,
     i32 %1)
 
   ret <vscale x 64 x i8> %a
 }
 
-declare <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i16(
-  i16,
+declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16(
+  <vscale x 1 x i16>,
   i32);
 
-define <vscale x 1 x i16> @intrinsic_vmv.v.x_x_nxv1i16_i16(i16 %0, i32 %1) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmv.v.v_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,mf4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16(
+    <vscale x 1 x i16> %0,
     i32 %1)
 
   ret <vscale x 1 x i16> %a
 }
 
-declare <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i16(
-  i16,
+declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16(
+  <vscale x 2 x i16>,
   i32);
 
-define <vscale x 2 x i16> @intrinsic_vmv.v.x_x_nxv2i16_i16(i16 %0, i32 %1) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmv.v.v_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,mf2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16(
+    <vscale x 2 x i16> %0,
     i32 %1)
 
   ret <vscale x 2 x i16> %a
 }
 
-declare <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i16(
-  i16,
+declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16(
+  <vscale x 4 x i16>,
   i32);
 
-define <vscale x 4 x i16> @intrinsic_vmv.v.x_x_nxv4i16_i16(i16 %0, i32 %1) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmv.v.v_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,m1
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16(
+    <vscale x 4 x i16> %0,
     i32 %1)
 
   ret <vscale x 4 x i16> %a
 }
 
-declare <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i16(
-  i16,
+declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16(
+  <vscale x 8 x i16>,
   i32);
 
-define <vscale x 8 x i16> @intrinsic_vmv.v.x_x_nxv8i16_i16(i16 %0, i32 %1) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmv.v.v_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,m2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16(
+    <vscale x 8 x i16> %0,
     i32 %1)
 
   ret <vscale x 8 x i16> %a
 }
 
-declare <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i16(
-  i16,
+declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16(
+  <vscale x 16 x i16>,
   i32);
 
-define <vscale x 16 x i16> @intrinsic_vmv.v.x_x_nxv16i16_i16(i16 %0, i32 %1) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmv.v.v_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,m4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16(
+    <vscale x 16 x i16> %0,
     i32 %1)
 
   ret <vscale x 16 x i16> %a
 }
 
-declare <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i16(
-  i16,
+declare <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16(
+  <vscale x 32 x i16>,
   i32);
 
-define <vscale x 32 x i16> @intrinsic_vmv.v.x_x_nxv32i16_i16(i16 %0, i32 %1) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmv.v.v_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,m8
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16(
+    <vscale x 32 x i16> %0,
     i32 %1)
 
   ret <vscale x 32 x i16> %a
 }
 
-declare <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i32(
-  i32,
+declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32(
+  <vscale x 1 x i32>,
   i32);
 
-define <vscale x 1 x i32> @intrinsic_vmv.v.x_x_nxv1i32_i32(i32 %0, i32 %1) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmv.v.v_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,mf2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32(
+    <vscale x 1 x i32> %0,
     i32 %1)
 
   ret <vscale x 1 x i32> %a
 }
 
-declare <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i32(
-  i32,
+declare <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(
+  <vscale x 2 x i32>,
   i32);
 
-define <vscale x 2 x i32> @intrinsic_vmv.v.x_x_nxv2i32_i32(i32 %0, i32 %1) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmv.v.v_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,m1
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(
+    <vscale x 2 x i32> %0,
     i32 %1)
 
   ret <vscale x 2 x i32> %a
 }
 
-declare <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i32(
-  i32,
+declare <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32(
+  <vscale x 4 x i32>,
   i32);
 
-define <vscale x 4 x i32> @intrinsic_vmv.v.x_x_nxv4i32_i32(i32 %0, i32 %1) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmv.v.v_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,m2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32(
+    <vscale x 4 x i32> %0,
     i32 %1)
 
   ret <vscale x 4 x i32> %a
 }
 
-declare <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i32(
-  i32,
+declare <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32(
+  <vscale x 8 x i32>,
   i32);
 
-define <vscale x 8 x i32> @intrinsic_vmv.v.x_x_nxv8i32_i32(i32 %0, i32 %1) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmv.v.v_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,m4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32(
+    <vscale x 8 x i32> %0,
     i32 %1)
 
   ret <vscale x 8 x i32> %a
 }
 
-declare <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i32(
-  i32,
+declare <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32(
+  <vscale x 16 x i32>,
   i32);
 
-define <vscale x 16 x i32> @intrinsic_vmv.v.x_x_nxv16i32_i32(i32 %0, i32 %1) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmv.v.v_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,m8
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32(
+    <vscale x 16 x i32> %0,
     i32 %1)
 
   ret <vscale x 16 x i32> %a
 }
 
-define <vscale x 1 x i8> @intrinsic_vmv.v.x_i_nxv1i8_i8(i32 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,mf8
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i8(
-    i8 9,
-    i32 %0)
-
-  ret <vscale x 1 x i8> %a
-}
+declare <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(
+  <vscale x 1 x i64>,
+  i32);
 
-define <vscale x 2 x i8> @intrinsic_vmv.v.x_i_nxv2i8_i8(i32 %0) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmv.v.v_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,mf4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i8(
-    i8 9,
-    i32 %0)
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(
+    <vscale x 1 x i64> %0,
+    i32 %1)
 
-  ret <vscale x 2 x i8> %a
+  ret <vscale x 1 x i64> %a
 }
 
-define <vscale x 4 x i8> @intrinsic_vmv.v.x_i_nxv4i8_i8(i32 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,mf2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i8(
-    i8 9,
-    i32 %0)
-
-  ret <vscale x 4 x i8> %a
-}
+declare <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64(
+  <vscale x 2 x i64>,
+  i32);
 
-define <vscale x 8 x i8> @intrinsic_vmv.v.x_i_nxv8i8_i8(i32 %0) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmv.v.v_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,m1
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i8(
-    i8 9,
-    i32 %0)
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64(
+    <vscale x 2 x i64> %0,
+    i32 %1)
 
-  ret <vscale x 8 x i8> %a
+  ret <vscale x 2 x i64> %a
 }
 
-define <vscale x 16 x i8> @intrinsic_vmv.v.x_i_nxv16i8_i8(i32 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,m2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i8(
-    i8 9,
-    i32 %0)
-
-  ret <vscale x 16 x i8> %a
-}
+declare <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64(
+  <vscale x 4 x i64>,
+  i32);
 
-define <vscale x 32 x i8> @intrinsic_vmv.v.x_i_nxv32i8_i8(i32 %0) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmv.v.v_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,m4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i8(
-    i8 9,
-    i32 %0)
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64(
+    <vscale x 4 x i64> %0,
+    i32 %1)
 
-  ret <vscale x 32 x i8> %a
+  ret <vscale x 4 x i64> %a
 }
 
-define <vscale x 64 x i8> @intrinsic_vmv.v.x_i_nxv64i8_i8(i32 %0) nounwind {
+declare <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64(
+  <vscale x 8 x i64>,
+  i32);
+
+define <vscale x 8 x i64> @intrinsic_vmv.v.v_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,m8
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i8(
-    i8 9,
-    i32 %0)
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64(
+    <vscale x 8 x i64> %0,
+    i32 %1)
 
-  ret <vscale x 64 x i8> %a
+  ret <vscale x 8 x i64> %a
 }
 
-define <vscale x 1 x i16> @intrinsic_vmv.v.x_i_nxv1i16_i16(i32 %0) nounwind {
+declare <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16(
+  <vscale x 1 x half>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vmv.v.v_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,mf4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i16(
-    i16 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16(
+    <vscale x 1 x half> %0,
+    i32 %1)
 
-  ret <vscale x 1 x i16> %a
+  ret <vscale x 1 x half> %a
 }
 
-define <vscale x 2 x i16> @intrinsic_vmv.v.x_i_nxv2i16_i16(i32 %0) nounwind {
+declare <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16(
+  <vscale x 2 x half>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vmv.v.v_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,mf2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i16(
-    i16 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16(
+    <vscale x 2 x half> %0,
+    i32 %1)
 
-  ret <vscale x 2 x i16> %a
+  ret <vscale x 2 x half> %a
 }
 
-define <vscale x 4 x i16> @intrinsic_vmv.v.x_i_nxv4i16_i16(i32 %0) nounwind {
+declare <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16(
+  <vscale x 4 x half>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vmv.v.v_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,m1
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i16(
-    i16 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16(
+    <vscale x 4 x half> %0,
+    i32 %1)
 
-  ret <vscale x 4 x i16> %a
+  ret <vscale x 4 x half> %a
 }
 
-define <vscale x 8 x i16> @intrinsic_vmv.v.x_i_nxv8i16_i16(i32 %0) nounwind {
+declare <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16(
+  <vscale x 8 x half>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vmv.v.v_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,m2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i16(
-    i16 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16(
+    <vscale x 8 x half> %0,
+    i32 %1)
 
-  ret <vscale x 8 x i16> %a
+  ret <vscale x 8 x half> %a
 }
 
-define <vscale x 16 x i16> @intrinsic_vmv.v.x_i_nxv16i16_i16(i32 %0) nounwind {
+declare <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16(
+  <vscale x 16 x half>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vmv.v.v_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,m4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i16(
-    i16 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16(
+    <vscale x 16 x half> %0,
+    i32 %1)
 
-  ret <vscale x 16 x i16> %a
+  ret <vscale x 16 x half> %a
 }
 
-define <vscale x 32 x i16> @intrinsic_vmv.v.x_i_nxv32i16_i16(i32 %0) nounwind {
+declare <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16(
+  <vscale x 32 x half>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vmv.v.v_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,m8
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i16(
-    i16 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16(
+    <vscale x 32 x half> %0,
+    i32 %1)
 
-  ret <vscale x 32 x i16> %a
+  ret <vscale x 32 x half> %a
 }
 
-define <vscale x 1 x i32> @intrinsic_vmv.v.x_i_nxv1i32_i32(i32 %0) nounwind {
+declare <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
+  <vscale x 1 x float>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,mf2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i32(
-    i32 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
+    <vscale x 1 x float> %0,
+    i32 %1)
 
-  ret <vscale x 1 x i32> %a
+  ret <vscale x 1 x float> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vmv.v.x_i_nxv2i32_i32(i32 %0) nounwind {
+declare <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32(
+  <vscale x 2 x float>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vmv.v.v_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,m1
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i32(
-    i32 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32(
+    <vscale x 2 x float> %0,
+    i32 %1)
 
-  ret <vscale x 2 x i32> %a
+  ret <vscale x 2 x float> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vmv.v.x_i_nxv4i32_i32(i32 %0) nounwind {
+declare <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32(
+  <vscale x 4 x float>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vmv.v.v_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,m2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i32(
-    i32 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32(
+    <vscale x 4 x float> %0,
+    i32 %1)
 
-  ret <vscale x 4 x i32> %a
+  ret <vscale x 4 x float> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vmv.v.x_i_nxv8i32_i32(i32 %0) nounwind {
+declare <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32(
+  <vscale x 8 x float>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vmv.v.v_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,m4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i32(
-    i32 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32(
+    <vscale x 8 x float> %0,
+    i32 %1)
 
-  ret <vscale x 8 x i32> %a
+  ret <vscale x 8 x float> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vmv.v.x_i_nxv16i32_i32(i32 %0) nounwind {
+declare <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32(
+  <vscale x 16 x float>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vmv.v.v_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i32 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,m8
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i32(
-    i32 9,
-    i32 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32(
+    <vscale x 16 x float> %0,
+    i32 %1)
 
-  ret <vscale x 16 x i32> %a
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64(
+  <vscale x 1 x double>,
+  i32);
+
+define <vscale x 1 x double> @intrinsic_vmv.v.v_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64(
+    <vscale x 1 x double> %0,
+    i32 %1)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64(
+  <vscale x 2 x double>,
+  i32);
+
+define <vscale x 2 x double> @intrinsic_vmv.v.v_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64(
+    <vscale x 2 x double> %0,
+    i32 %1)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64(
+  <vscale x 4 x double>,
+  i32);
+
+define <vscale x 4 x double> @intrinsic_vmv.v.v_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64(
+    <vscale x 4 x double> %0,
+    i32 %1)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64(
+  <vscale x 8 x double>,
+  i32);
+
+define <vscale x 8 x double> @intrinsic_vmv.v.v_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64(
+    <vscale x 8 x double> %0,
+    i32 %1)
+
+  ret <vscale x 8 x double> %a
 }
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll
index 21b22f6c3f0fc..2b0a414c64c74 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmv.v.v-rv64.ll
@@ -1,617 +1,593 @@
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
 ; RUN:   --riscv-no-aliases < %s | FileCheck %s
-declare <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i8(
-  i8,
+declare <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
+  <vscale x 1 x i8>,
   i64);
 
-define <vscale x 1 x i8> @intrinsic_vmv.v.x_x_nxv1i8_i8(i8 %0, i64 %1) nounwind {
+define <vscale x 1 x i8> @intrinsic_vmv.v.v_v_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,mf8
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.v.nxv1i8(
+    <vscale x 1 x i8> %0,
     i64 %1)
 
   ret <vscale x 1 x i8> %a
 }
 
-declare <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i8(
-  i8,
+declare <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8(
+  <vscale x 2 x i8>,
   i64);
 
-define <vscale x 2 x i8> @intrinsic_vmv.v.x_x_nxv2i8_i8(i8 %0, i64 %1) nounwind {
+define <vscale x 2 x i8> @intrinsic_vmv.v.v_v_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,mf4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.v.nxv2i8(
+    <vscale x 2 x i8> %0,
     i64 %1)
 
   ret <vscale x 2 x i8> %a
 }
 
-declare <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i8(
-  i8,
+declare <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8(
+  <vscale x 4 x i8>,
   i64);
 
-define <vscale x 4 x i8> @intrinsic_vmv.v.x_x_nxv4i8_i8(i8 %0, i64 %1) nounwind {
+define <vscale x 4 x i8> @intrinsic_vmv.v.v_v_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,mf2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.v.nxv4i8(
+    <vscale x 4 x i8> %0,
     i64 %1)
 
   ret <vscale x 4 x i8> %a
 }
 
-declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i8(
-  i8,
+declare <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8(
+  <vscale x 8 x i8>,
   i64);
 
-define <vscale x 8 x i8> @intrinsic_vmv.v.x_x_nxv8i8_i8(i8 %0, i64 %1) nounwind {
+define <vscale x 8 x i8> @intrinsic_vmv.v.v_v_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,m1
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m1
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.v.nxv8i8(
+    <vscale x 8 x i8> %0,
     i64 %1)
 
   ret <vscale x 8 x i8> %a
 }
 
-declare <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i8(
-  i8,
+declare <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8(
+  <vscale x 16 x i8>,
   i64);
 
-define <vscale x 16 x i8> @intrinsic_vmv.v.x_x_nxv16i8_i8(i8 %0, i64 %1) nounwind {
+define <vscale x 16 x i8> @intrinsic_vmv.v.v_v_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,m2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.v.nxv16i8(
+    <vscale x 16 x i8> %0,
     i64 %1)
 
   ret <vscale x 16 x i8> %a
 }
 
-declare <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i8(
-  i8,
+declare <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8(
+  <vscale x 32 x i8>,
   i64);
 
-define <vscale x 32 x i8> @intrinsic_vmv.v.x_x_nxv32i8_i8(i8 %0, i64 %1) nounwind {
+define <vscale x 32 x i8> @intrinsic_vmv.v.v_v_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,m4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.v.nxv32i8(
+    <vscale x 32 x i8> %0,
     i64 %1)
 
   ret <vscale x 32 x i8> %a
 }
 
-declare <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i8(
-  i8,
+declare <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8(
+  <vscale x 64 x i8>,
   i64);
 
-define <vscale x 64 x i8> @intrinsic_vmv.v.x_x_nxv64i8_i8(i8 %0, i64 %1) nounwind {
+define <vscale x 64 x i8> @intrinsic_vmv.v.v_v_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, a1, e8,m8
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i8(
-    i8 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, a0, e8,m8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.v.nxv64i8(
+    <vscale x 64 x i8> %0,
     i64 %1)
 
   ret <vscale x 64 x i8> %a
 }
 
-declare <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i16(
-  i16,
+declare <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16(
+  <vscale x 1 x i16>,
   i64);
 
-define <vscale x 1 x i16> @intrinsic_vmv.v.x_x_nxv1i16_i16(i16 %0, i64 %1) nounwind {
+define <vscale x 1 x i16> @intrinsic_vmv.v.v_v_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,mf4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.v.nxv1i16(
+    <vscale x 1 x i16> %0,
     i64 %1)
 
   ret <vscale x 1 x i16> %a
 }
 
-declare <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i16(
-  i16,
+declare <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16(
+  <vscale x 2 x i16>,
   i64);
 
-define <vscale x 2 x i16> @intrinsic_vmv.v.x_x_nxv2i16_i16(i16 %0, i64 %1) nounwind {
+define <vscale x 2 x i16> @intrinsic_vmv.v.v_v_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,mf2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, a0, e16,mf2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.v.nxv2i16(
+    <vscale x 2 x i16> %0,
     i64 %1)
 
   ret <vscale x 2 x i16> %a
 }
 
-declare <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i16(
-  i16,
+declare <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16(
+  <vscale x 4 x i16>,
   i64);
 
-define <vscale x 4 x i16> @intrinsic_vmv.v.x_x_nxv4i16_i16(i16 %0, i64 %1) nounwind {
+define <vscale x 4 x i16> @intrinsic_vmv.v.v_v_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,m1
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m1
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.v.nxv4i16(
+    <vscale x 4 x i16> %0,
     i64 %1)
 
   ret <vscale x 4 x i16> %a
 }
 
-declare <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i16(
-  i16,
+declare <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16(
+  <vscale x 8 x i16>,
   i64);
 
-define <vscale x 8 x i16> @intrinsic_vmv.v.x_x_nxv8i16_i16(i16 %0, i64 %1) nounwind {
+define <vscale x 8 x i16> @intrinsic_vmv.v.v_v_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,m2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.v.nxv8i16(
+    <vscale x 8 x i16> %0,
     i64 %1)
 
   ret <vscale x 8 x i16> %a
 }
 
-declare <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i16(
-  i16,
+declare <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16(
+  <vscale x 16 x i16>,
   i64);
 
-define <vscale x 16 x i16> @intrinsic_vmv.v.x_x_nxv16i16_i16(i16 %0, i64 %1) nounwind {
+define <vscale x 16 x i16> @intrinsic_vmv.v.v_v_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,m4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.v.nxv16i16(
+    <vscale x 16 x i16> %0,
     i64 %1)
 
   ret <vscale x 16 x i16> %a
 }
 
-declare <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i16(
-  i16,
+declare <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16(
+  <vscale x 32 x i16>,
   i64);
 
-define <vscale x 32 x i16> @intrinsic_vmv.v.x_x_nxv32i16_i16(i16 %0, i64 %1) nounwind {
+define <vscale x 32 x i16> @intrinsic_vmv.v.v_v_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv32i16_i16
-; CHECK:       vsetvli {{.*}}, a1, e16,m8
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i16(
-    i16 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, a0, e16,m8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.v.nxv32i16(
+    <vscale x 32 x i16> %0,
     i64 %1)
 
   ret <vscale x 32 x i16> %a
 }
 
-declare <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i32(
-  i32,
+declare <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32(
+  <vscale x 1 x i32>,
   i64);
 
-define <vscale x 1 x i32> @intrinsic_vmv.v.x_x_nxv1i32_i32(i32 %0, i64 %1) nounwind {
+define <vscale x 1 x i32> @intrinsic_vmv.v.v_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,mf2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, a0, e32,mf2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.v.nxv1i32(
+    <vscale x 1 x i32> %0,
     i64 %1)
 
   ret <vscale x 1 x i32> %a
 }
 
-declare <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i32(
-  i32,
+declare <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(
+  <vscale x 2 x i32>,
   i64);
 
-define <vscale x 2 x i32> @intrinsic_vmv.v.x_x_nxv2i32_i32(i32 %0, i64 %1) nounwind {
+define <vscale x 2 x i32> @intrinsic_vmv.v.v_v_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,m1
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m1
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.v.nxv2i32(
+    <vscale x 2 x i32> %0,
     i64 %1)
 
   ret <vscale x 2 x i32> %a
 }
 
-declare <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i32(
-  i32,
+declare <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32(
+  <vscale x 4 x i32>,
   i64);
 
-define <vscale x 4 x i32> @intrinsic_vmv.v.x_x_nxv4i32_i32(i32 %0, i64 %1) nounwind {
+define <vscale x 4 x i32> @intrinsic_vmv.v.v_v_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,m2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.v.nxv4i32(
+    <vscale x 4 x i32> %0,
     i64 %1)
 
   ret <vscale x 4 x i32> %a
 }
 
-declare <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i32(
-  i32,
+declare <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32(
+  <vscale x 8 x i32>,
   i64);
 
-define <vscale x 8 x i32> @intrinsic_vmv.v.x_x_nxv8i32_i32(i32 %0, i64 %1) nounwind {
+define <vscale x 8 x i32> @intrinsic_vmv.v.v_v_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,m4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.v.nxv8i32(
+    <vscale x 8 x i32> %0,
     i64 %1)
 
   ret <vscale x 8 x i32> %a
 }
 
-declare <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i32(
-  i32,
+declare <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32(
+  <vscale x 16 x i32>,
   i64);
 
-define <vscale x 16 x i32> @intrinsic_vmv.v.x_x_nxv16i32_i32(i32 %0, i64 %1) nounwind {
+define <vscale x 16 x i32> @intrinsic_vmv.v.v_v_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv16i32_i32
-; CHECK:       vsetvli {{.*}}, a1, e32,m8
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i32(
-    i32 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, a0, e32,m8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.v.nxv16i32(
+    <vscale x 16 x i32> %0,
     i64 %1)
 
   ret <vscale x 16 x i32> %a
 }
 
-declare <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64.i64(
-  i64,
+declare <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(
+  <vscale x 1 x i64>,
   i64);
 
-define <vscale x 1 x i64> @intrinsic_vmv.v.x_x_nxv1i64_i64(i64 %0, i64 %1) nounwind {
+define <vscale x 1 x i64> @intrinsic_vmv.v.v_v_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv1i64_i64
-; CHECK:       vsetvli {{.*}}, a1, e64,m1
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64.i64(
-    i64 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m1
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(
+    <vscale x 1 x i64> %0,
     i64 %1)
 
   ret <vscale x 1 x i64> %a
 }
 
-declare <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64.i64(
-  i64,
+declare <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64(
+  <vscale x 2 x i64>,
   i64);
 
-define <vscale x 2 x i64> @intrinsic_vmv.v.x_x_nxv2i64_i64(i64 %0, i64 %1) nounwind {
+define <vscale x 2 x i64> @intrinsic_vmv.v.v_v_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv2i64_i64
-; CHECK:       vsetvli {{.*}}, a1, e64,m2
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64.i64(
-    i64 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m2
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.v.nxv2i64(
+    <vscale x 2 x i64> %0,
     i64 %1)
 
   ret <vscale x 2 x i64> %a
 }
 
-declare <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64.i64(
-  i64,
+declare <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64(
+  <vscale x 4 x i64>,
   i64);
 
-define <vscale x 4 x i64> @intrinsic_vmv.v.x_x_nxv4i64_i64(i64 %0, i64 %1) nounwind {
+define <vscale x 4 x i64> @intrinsic_vmv.v.v_v_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv4i64_i64
-; CHECK:       vsetvli {{.*}}, a1, e64,m4
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64.i64(
-    i64 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m4
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.v.nxv4i64(
+    <vscale x 4 x i64> %0,
     i64 %1)
 
   ret <vscale x 4 x i64> %a
 }
 
-declare <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64.i64(
-  i64,
+declare <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64(
+  <vscale x 8 x i64>,
   i64);
 
-define <vscale x 8 x i64> @intrinsic_vmv.v.x_x_nxv8i64_i64(i64 %0, i64 %1) nounwind {
+define <vscale x 8 x i64> @intrinsic_vmv.v.v_v_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_x_nxv8i64_i64
-; CHECK:       vsetvli {{.*}}, a1, e64,m8
-; CHECK:       vmv.v.x {{v[0-9]+}}, a0
-  %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64.i64(
-    i64 %0,
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, a0, e64,m8
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.v.nxv8i64(
+    <vscale x 8 x i64> %0,
     i64 %1)
 
   ret <vscale x 8 x i64> %a
 }
 
-define <vscale x 1 x i8> @intrinsic_vmv.v.x_i_nxv1i8_i8(i64 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,mf8
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 1 x i8> @llvm.riscv.vmv.v.x.nxv1i8.i8(
-    i8 9,
-    i64 %0)
-
-  ret <vscale x 1 x i8> %a
-}
-
-define <vscale x 2 x i8> @intrinsic_vmv.v.x_i_nxv2i8_i8(i64 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,mf4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 2 x i8> @llvm.riscv.vmv.v.x.nxv2i8.i8(
-    i8 9,
-    i64 %0)
-
-  ret <vscale x 2 x i8> %a
-}
-
-define <vscale x 4 x i8> @intrinsic_vmv.v.x_i_nxv4i8_i8(i64 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,mf2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 4 x i8> @llvm.riscv.vmv.v.x.nxv4i8.i8(
-    i8 9,
-    i64 %0)
-
-  ret <vscale x 4 x i8> %a
-}
-
-define <vscale x 8 x i8> @intrinsic_vmv.v.x_i_nxv8i8_i8(i64 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,m1
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.i8(
-    i8 9,
-    i64 %0)
-
-  ret <vscale x 8 x i8> %a
-}
-
-define <vscale x 16 x i8> @intrinsic_vmv.v.x_i_nxv16i8_i8(i64 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,m2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 16 x i8> @llvm.riscv.vmv.v.x.nxv16i8.i8(
-    i8 9,
-    i64 %0)
-
-  ret <vscale x 16 x i8> %a
-}
-
-define <vscale x 32 x i8> @intrinsic_vmv.v.x_i_nxv32i8_i8(i64 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,m4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 32 x i8> @llvm.riscv.vmv.v.x.nxv32i8.i8(
-    i8 9,
-    i64 %0)
-
-  ret <vscale x 32 x i8> %a
-}
-
-define <vscale x 64 x i8> @intrinsic_vmv.v.x_i_nxv64i8_i8(i64 %0) nounwind {
-entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv64i8_i8
-; CHECK:       vsetvli {{.*}}, a0, e8,m8
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 64 x i8> @llvm.riscv.vmv.v.x.nxv64i8.i8(
-    i8 9,
-    i64 %0)
-
-  ret <vscale x 64 x i8> %a
-}
+declare <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16(
+  <vscale x 1 x half>,
+  i64);
 
-define <vscale x 1 x i16> @intrinsic_vmv.v.x_i_nxv1i16_i16(i64 %0) nounwind {
+define <vscale x 1 x half> @intrinsic_vmv.v.v_v_nxv1f16_nxv1f16(<vscale x 1 x half> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f16_nxv1f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,mf4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 1 x i16> @llvm.riscv.vmv.v.x.nxv1i16.i16(
-    i16 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x half> @llvm.riscv.vmv.v.v.nxv1f16(
+    <vscale x 1 x half> %0,
+    i64 %1)
 
-  ret <vscale x 1 x i16> %a
+  ret <vscale x 1 x half> %a
 }
 
-define <vscale x 2 x i16> @intrinsic_vmv.v.x_i_nxv2i16_i16(i64 %0) nounwind {
+declare <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16(
+  <vscale x 2 x half>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vmv.v.v_v_nxv2f16_nxv2f16(<vscale x 2 x half> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f16_nxv2f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,mf2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 2 x i16> @llvm.riscv.vmv.v.x.nxv2i16.i16(
-    i16 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x half> @llvm.riscv.vmv.v.v.nxv2f16(
+    <vscale x 2 x half> %0,
+    i64 %1)
 
-  ret <vscale x 2 x i16> %a
+  ret <vscale x 2 x half> %a
 }
 
-define <vscale x 4 x i16> @intrinsic_vmv.v.x_i_nxv4i16_i16(i64 %0) nounwind {
+declare <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16(
+  <vscale x 4 x half>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vmv.v.v_v_nxv4f16_nxv4f16(<vscale x 4 x half> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f16_nxv4f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,m1
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 4 x i16> @llvm.riscv.vmv.v.x.nxv4i16.i16(
-    i16 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x half> @llvm.riscv.vmv.v.v.nxv4f16(
+    <vscale x 4 x half> %0,
+    i64 %1)
 
-  ret <vscale x 4 x i16> %a
+  ret <vscale x 4 x half> %a
 }
 
-define <vscale x 8 x i16> @intrinsic_vmv.v.x_i_nxv8i16_i16(i64 %0) nounwind {
+declare <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16(
+  <vscale x 8 x half>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vmv.v.v_v_nxv8f16_nxv8f16(<vscale x 8 x half> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f16_nxv8f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,m2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 8 x i16> @llvm.riscv.vmv.v.x.nxv8i16.i16(
-    i16 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x half> @llvm.riscv.vmv.v.v.nxv8f16(
+    <vscale x 8 x half> %0,
+    i64 %1)
 
-  ret <vscale x 8 x i16> %a
+  ret <vscale x 8 x half> %a
 }
 
-define <vscale x 16 x i16> @intrinsic_vmv.v.x_i_nxv16i16_i16(i64 %0) nounwind {
+declare <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16(
+  <vscale x 16 x half>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vmv.v.v_v_nxv16f16_nxv16f16(<vscale x 16 x half> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f16_nxv16f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,m4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 16 x i16> @llvm.riscv.vmv.v.x.nxv16i16.i16(
-    i16 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x half> @llvm.riscv.vmv.v.v.nxv16f16(
+    <vscale x 16 x half> %0,
+    i64 %1)
 
-  ret <vscale x 16 x i16> %a
+  ret <vscale x 16 x half> %a
 }
 
-define <vscale x 32 x i16> @intrinsic_vmv.v.x_i_nxv32i16_i16(i64 %0) nounwind {
+declare <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16(
+  <vscale x 32 x half>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vmv.v.v_v_nxv32f16_nxv32f16(<vscale x 32 x half> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv32i16_i16
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv32f16_nxv32f16
 ; CHECK:       vsetvli {{.*}}, a0, e16,m8
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 32 x i16> @llvm.riscv.vmv.v.x.nxv32i16.i16(
-    i16 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x half> @llvm.riscv.vmv.v.v.nxv32f16(
+    <vscale x 32 x half> %0,
+    i64 %1)
 
-  ret <vscale x 32 x i16> %a
+  ret <vscale x 32 x half> %a
 }
 
-define <vscale x 1 x i32> @intrinsic_vmv.v.x_i_nxv1i32_i32(i64 %0) nounwind {
+declare <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
+  <vscale x 1 x float>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vmv.v.v_v_nxv1f32_nxv1f32(<vscale x 1 x float> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f32_nxv1f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,mf2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 1 x i32> @llvm.riscv.vmv.v.x.nxv1i32.i32(
-    i32 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x float> @llvm.riscv.vmv.v.v.nxv1f32(
+    <vscale x 1 x float> %0,
+    i64 %1)
 
-  ret <vscale x 1 x i32> %a
+  ret <vscale x 1 x float> %a
 }
 
-define <vscale x 2 x i32> @intrinsic_vmv.v.x_i_nxv2i32_i32(i64 %0) nounwind {
+declare <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32(
+  <vscale x 2 x float>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vmv.v.v_v_nxv2f32_nxv2f32(<vscale x 2 x float> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f32_nxv2f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,m1
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 2 x i32> @llvm.riscv.vmv.v.x.nxv2i32.i32(
-    i32 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x float> @llvm.riscv.vmv.v.v.nxv2f32(
+    <vscale x 2 x float> %0,
+    i64 %1)
 
-  ret <vscale x 2 x i32> %a
+  ret <vscale x 2 x float> %a
 }
 
-define <vscale x 4 x i32> @intrinsic_vmv.v.x_i_nxv4i32_i32(i64 %0) nounwind {
+declare <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32(
+  <vscale x 4 x float>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vmv.v.v_v_nxv4f32_nxv4f32(<vscale x 4 x float> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f32_nxv4f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,m2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 4 x i32> @llvm.riscv.vmv.v.x.nxv4i32.i32(
-    i32 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x float> @llvm.riscv.vmv.v.v.nxv4f32(
+    <vscale x 4 x float> %0,
+    i64 %1)
 
-  ret <vscale x 4 x i32> %a
+  ret <vscale x 4 x float> %a
 }
 
-define <vscale x 8 x i32> @intrinsic_vmv.v.x_i_nxv8i32_i32(i64 %0) nounwind {
+declare <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32(
+  <vscale x 8 x float>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vmv.v.v_v_nxv8f32_nxv8f32(<vscale x 8 x float> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f32_nxv8f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,m4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 8 x i32> @llvm.riscv.vmv.v.x.nxv8i32.i32(
-    i32 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x float> @llvm.riscv.vmv.v.v.nxv8f32(
+    <vscale x 8 x float> %0,
+    i64 %1)
 
-  ret <vscale x 8 x i32> %a
+  ret <vscale x 8 x float> %a
 }
 
-define <vscale x 16 x i32> @intrinsic_vmv.v.x_i_nxv16i32_i32(i64 %0) nounwind {
+declare <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32(
+  <vscale x 16 x float>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vmv.v.v_v_nxv16f32_nxv16f32(<vscale x 16 x float> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv16i32_i32
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv16f32_nxv16f32
 ; CHECK:       vsetvli {{.*}}, a0, e32,m8
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 16 x i32> @llvm.riscv.vmv.v.x.nxv16i32.i32(
-    i32 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x float> @llvm.riscv.vmv.v.v.nxv16f32(
+    <vscale x 16 x float> %0,
+    i64 %1)
 
-  ret <vscale x 16 x i32> %a
+  ret <vscale x 16 x float> %a
 }
 
-define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64_i64(i64 %0) nounwind {
+declare <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64(
+  <vscale x 1 x double>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vmv.v.v_v_nxv1f64_nxv1f64(<vscale x 1 x double> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64_i64
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv1f64_nxv1f64
 ; CHECK:       vsetvli {{.*}}, a0, e64,m1
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64.i64(
-    i64 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x double> @llvm.riscv.vmv.v.v.nxv1f64(
+    <vscale x 1 x double> %0,
+    i64 %1)
 
-  ret <vscale x 1 x i64> %a
+  ret <vscale x 1 x double> %a
 }
 
-define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64_i64(i64 %0) nounwind {
+declare <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64(
+  <vscale x 2 x double>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vmv.v.v_v_nxv2f64_nxv2f64(<vscale x 2 x double> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64_i64
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv2f64_nxv2f64
 ; CHECK:       vsetvli {{.*}}, a0, e64,m2
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64.i64(
-    i64 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x double> @llvm.riscv.vmv.v.v.nxv2f64(
+    <vscale x 2 x double> %0,
+    i64 %1)
 
-  ret <vscale x 2 x i64> %a
+  ret <vscale x 2 x double> %a
 }
 
-define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64_i64(i64 %0) nounwind {
+declare <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64(
+  <vscale x 4 x double>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vmv.v.v_v_nxv4f64_nxv4f64(<vscale x 4 x double> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64_i64
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv4f64_nxv4f64
 ; CHECK:       vsetvli {{.*}}, a0, e64,m4
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64.i64(
-    i64 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x double> @llvm.riscv.vmv.v.v.nxv4f64(
+    <vscale x 4 x double> %0,
+    i64 %1)
 
-  ret <vscale x 4 x i64> %a
+  ret <vscale x 4 x double> %a
 }
 
-define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64_i64(i64 %0) nounwind {
+declare <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64(
+  <vscale x 8 x double>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vmv.v.v_v_nxv8f64_nxv8f64(<vscale x 8 x double> %0, i64 %1) nounwind {
 entry:
-; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64_i64
+; CHECK-LABEL: intrinsic_vmv.v.v_v_nxv8f64_nxv8f64
 ; CHECK:       vsetvli {{.*}}, a0, e64,m8
-; CHECK:       vmv.v.i {{v[0-9]+}}, 9
-  %a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64.i64(
-    i64 9,
-    i64 %0)
+; CHECK:       vmv.v.v {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x double> @llvm.riscv.vmv.v.v.nxv8f64(
+    <vscale x 8 x double> %0,
+    i64 %1)
 
-  ret <vscale x 8 x i64> %a
+  ret <vscale x 8 x double> %a
 }
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll
new file mode 100644
index 0000000000000..878def5f43628
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmxnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmxnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmxnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmxnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmxnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmxnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmxnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll
new file mode 100644
index 0000000000000..073509fc5c940
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmxnor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmxnor.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmxnor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmxnor.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmxnor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmxnor.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmxnor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmxnor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmxnor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmxnor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmxnor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmxnor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmxnor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxnor_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmxnor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmxnor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll
new file mode 100644
index 0000000000000..743aff55e3ebb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i1> @intrinsic_vmxor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i1> @intrinsic_vmxor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i1> @intrinsic_vmxor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i1> @intrinsic_vmxor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i1> @intrinsic_vmxor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i1> @intrinsic_vmxor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i1> @intrinsic_vmxor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll
new file mode 100644
index 0000000000000..fc9d15a88f476
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll
@@ -0,0 +1,127 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i1> @intrinsic_vmxor_mm_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv1i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i1> @llvm.riscv.vmxor.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i1> %a
+}
+
+declare <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i1> @intrinsic_vmxor_mm_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv2i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i1> @llvm.riscv.vmxor.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i1> %a
+}
+
+declare <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i1> @intrinsic_vmxor_mm_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv4i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i1> @llvm.riscv.vmxor.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i1> %a
+}
+
+declare <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i1> @intrinsic_vmxor_mm_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv8i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i1> @llvm.riscv.vmxor.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i1> %a
+}
+
+declare <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i1> @intrinsic_vmxor_mm_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv16i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i1> @llvm.riscv.vmxor.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i1> %a
+}
+
+declare <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i1> @intrinsic_vmxor_mm_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv32i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i1> @llvm.riscv.vmxor.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i1> %a
+}
+
+declare <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i1> @intrinsic_vmxor_mm_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vmxor_mm_nxv64i1
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vmxor.mm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i1> @llvm.riscv.vmxor.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i1> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
new file mode 100644
index 0000000000000..e6997482a8701
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
@@ -0,0 +1,1261 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
new file mode 100644
index 0000000000000..d79c4f6deeffd
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vnmsac-rv64.ll
@@ -0,0 +1,1513 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vnmsac_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vnmsac_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vnmsac_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vnmsac.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsac.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsac.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsac.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsac.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsac.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsac.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsac.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsac.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsac.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsac.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsac.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsac.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsac.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsac.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsac.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv1i64_i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv1i64_i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vnmsac.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv2i64_i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv2i64_i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vnmsac.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_vx_nxv4i64_i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsac_mask_vx_nxv4i64_i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vnmsac.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vnmsac.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
new file mode 100644
index 0000000000000..3c01f60e9df5a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
@@ -0,0 +1,1261 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
new file mode 100644
index 0000000000000..dd9d6ec2280b6
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vnmsub-rv64.ll
@@ -0,0 +1,1513 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vnmsub_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vnmsub_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vnmsub_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vnmsub.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8>  @intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i8_i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vnmsub.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8>  @intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8(<vscale x 2 x i8> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i8_i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vnmsub.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8>  @intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8(<vscale x 4 x i8> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i8_i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vnmsub.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8>  @intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8(<vscale x 8 x i8> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i8_i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vnmsub.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8>  @intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8(<vscale x 16 x i8> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i8_i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vnmsub.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8>  @intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8(<vscale x 32 x i8> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv32i8_i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vnmsub.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16(<vscale x 1 x i16> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i16_i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vnmsub.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16(<vscale x 2 x i16> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i16_i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vnmsub.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16(<vscale x 4 x i16> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i16_i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vnmsub.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16(<vscale x 8 x i16> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i16_i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vnmsub.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16(<vscale x 16 x i16> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv16i16_i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vnmsub.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32(<vscale x 1 x i32> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i32_i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vnmsub.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32(<vscale x 2 x i32> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i32_i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vnmsub.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32(<vscale x 4 x i32> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i32_i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vnmsub.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32(<vscale x 8 x i32> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv8i32_i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vnmsub.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv1i64_i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv1i64_i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vnmsub.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv2i64_i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    <vscale x 2 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64(<vscale x 2 x i64> %0, i64 %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv2i64_i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vnmsub.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_vx_nxv4i64_i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    <vscale x 4 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64(<vscale x 4 x i64> %0, i64 %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vnmsub_mask_vx_nxv4i64_i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vnmsub.vx {{v[0-9]+}}, a0, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vnmsub.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
new file mode 100644
index 0000000000000..1ac44ba020ea1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
@@ -0,0 +1,1945 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i8> %2,
+    <vscale x 64 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vor_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vor_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vor_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vor_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vor_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vor_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vor_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vor_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vor_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vor_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vor_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vor_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vor_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vor_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vor_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vor_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vor_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vor_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vor_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vor_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vor_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vor_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vor_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vor_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vor_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 9,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vor_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vor_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vor_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vor_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vor_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vor_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vor_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vor_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vor_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vor_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vor_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
new file mode 100644
index 0000000000000..ce2107138f93a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-rv64.ll
@@ -0,0 +1,2377 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i8> %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vor_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vor_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vor_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vor_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vor_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vor_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vor_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vv_nxv8i64_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vv_nxv8i64_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vor_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vor_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vor_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vor_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vor_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vor_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vor_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vor_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vor_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vor_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vor_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vor_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vor_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vor_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vor_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vor_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vor_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vor_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  i64,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vor_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vx_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vx_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vor_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vor.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vor_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vor.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vor_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vor.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vor_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vor.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vor_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vor.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vor_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vor.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vor_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vor.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 9,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vor_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vor.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vor_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vor.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vor_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vor.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vor_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vor.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vor_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vor.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vor_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vor.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vor_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vor.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vor_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vor.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vor_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vor.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vor_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vor.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vor_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vor.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vor_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i64> @llvm.riscv.vor.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vor_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vor.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vor_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i64> @llvm.riscv.vor.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vor_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vor.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vor_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i64> @llvm.riscv.vor.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vor_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vor.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vor_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_vi_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i64> @llvm.riscv.vor.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vor_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vor_mask_vi_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vor.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
new file mode 100644
index 0000000000000..410da16bc3ab7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
@@ -0,0 +1,1109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vor_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vor_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vor_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv1i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vor_vx_nxv1i8_2(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv1i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vor_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vor_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vor_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv2i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vor_vx_nxv2i8_2(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv2i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vor_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vor_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vor_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv4i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vor_vx_nxv4i8_2(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv4i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vor_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vor_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vor_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vor_vx_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vor_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vor_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vor_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv16i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vor_vx_nxv16i8_2(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv16i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vor_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vor_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vor_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv32i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vor_vx_nxv32i8_2(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv32i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vor_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = or <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vor_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = or <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vor_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv64i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = or <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vor_vx_nxv64i8_2(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv64i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = or <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vor_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vor_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vor_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv1i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vor_vx_nxv1i16_2(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv1i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vor_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vor_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vor_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv2i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vor_vx_nxv2i16_2(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv2i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vor_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vor_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vor_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv4i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vor_vx_nxv4i16_2(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv4i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vor_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vor_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vor_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vor_vx_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vor_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vor_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vor_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv16i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vor_vx_nxv16i16_2(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv16i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vor_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vor_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vor_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv32i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vor_vx_nxv32i16_2(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv32i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vor_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vor_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vor_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vor_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vor_vx_nxv1i32_2(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv1i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vor_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vor_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vor_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vor_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vor_vx_nxv2i32_2(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv2i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vor_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vor_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vor_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vor_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vor_vx_nxv4i32_2(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv4i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vor_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vor_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
+; CHECK-LABEL: vor_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vor_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vor_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv16i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vor_vx_nxv16i32_2(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv16i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vor_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vor.vv v16, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vor_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 -12, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vor_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv1i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vor_vx_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv1i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vor_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vsrl.vx v28, v28, a1
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vor.vv v16, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vor_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 -12, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vor_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv2i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vor_vx_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv2i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vor_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vsrl.vx v8, v8, a1
+; CHECK-NEXT:    vor.vv v28, v8, v28
+; CHECK-NEXT:    vor.vv v16, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vor_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 -12, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vor_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv4i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vor_vx_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv4i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vor_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vor.vv v16, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vor_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -12, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vor_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vor_vx_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
new file mode 100644
index 0000000000000..04aa0de912a5b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll
@@ -0,0 +1,1081 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vor_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vor_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vor_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv1i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vor_vx_nxv1i8_2(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv1i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vor_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vor_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vor_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv2i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vor_vx_nxv2i8_2(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv2i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vor_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vor_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vor_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv4i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vor_vx_nxv4i8_2(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv4i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vor_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vor_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vor_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vor_vx_nxv8i8_2(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv8i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vor_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vor_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vor_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv16i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vor_vx_nxv16i8_2(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv16i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vor_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vor_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vor_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv32i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vor_vx_nxv32i8_2(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv32i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vor_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vor_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = or <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vor_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 -12, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = or <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vor_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv64i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 15, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = or <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vor_vx_nxv64i8_2(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vor_vx_nxv64i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 16, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = or <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vor_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vor_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vor_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv1i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vor_vx_nxv1i16_2(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv1i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vor_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vor_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vor_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv2i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vor_vx_nxv2i16_2(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv2i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vor_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vor_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vor_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv4i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vor_vx_nxv4i16_2(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv4i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vor_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vor_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vor_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vor_vx_nxv8i16_2(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv8i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vor_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vor_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vor_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv16i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vor_vx_nxv16i16_2(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv16i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vor_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vor_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vor_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 -12, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vor_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv32i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 15, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vor_vx_nxv32i16_2(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vor_vx_nxv32i16_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 16, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = or <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vor_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vor_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vor_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vor_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vor_vx_nxv1i32_2(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv1i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vor_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vor_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vor_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vor_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vor_vx_nxv2i32_2(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv2i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vor_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vor_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vor_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vor_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vor_vx_nxv4i32_2(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv4i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vor_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_nxv8i32_2(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv8i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vor_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vor_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vor_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 -12, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vor_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv16i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 15, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vor_vx_nxv16i32_2(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vor_vx_nxv16i32_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 16, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = or <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vor_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vor_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vor_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 -12, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vor_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv1i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vor_vx_nxv1i64_2(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv1i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = or <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vor_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vor_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vor_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 -12, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vor_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv2i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vor_vx_nxv2i64_2(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv2i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = or <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vor_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vor_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vor_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 -12, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vor_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv4i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vor_vx_nxv4i64_2(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv4i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = or <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vor_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vor_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vor_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, -12
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -12, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vor_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vor.vi v16, v16, 15
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vor_vx_nxv8i64_2(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vor_vx_nxv8i64_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vor.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll
new file mode 100644
index 0000000000000..a12745886ea12
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare i32 @llvm.riscv.vpopc.i64.nxv1i1(
+  <vscale x 1 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_m_i64_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vpopc.i64.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.mask.i64.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_mask_m_i64_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vpopc.mask.i64.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.i64.nxv2i1(
+  <vscale x 2 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_m_i64_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vpopc.i64.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.mask.i64.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_mask_m_i64_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vpopc.mask.i64.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.i64.nxv4i1(
+  <vscale x 4 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_m_i64_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vpopc.i64.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.mask.i64.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_mask_m_i64_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vpopc.mask.i64.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.i64.nxv8i1(
+  <vscale x 8 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_m_i64_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vpopc.i64.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.mask.i64.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_mask_m_i64_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vpopc.mask.i64.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.i64.nxv16i1(
+  <vscale x 16 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_m_i64_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vpopc.i64.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.mask.i64.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_mask_m_i64_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vpopc.mask.i64.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.i64.nxv32i1(
+  <vscale x 32 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_m_i64_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vpopc.i64.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.mask.i64.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_mask_m_i64_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vpopc.mask.i64.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.i64.nxv64i1(
+  <vscale x 64 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_m_i64_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i32 @llvm.riscv.vpopc.i64.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i32 %1)
+
+  ret i32 %a
+}
+
+declare i32 @llvm.riscv.vpopc.mask.i64.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i32);
+
+define i32 @intrinsic_vpopc_mask_m_i64_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i32 @llvm.riscv.vpopc.mask.i64.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i32 %2)
+
+  ret i32 %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll
new file mode 100644
index 0000000000000..59eacd2011457
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll
@@ -0,0 +1,239 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare i64 @llvm.riscv.vpopc.i64.nxv1i1(
+  <vscale x 1 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_m_i64_nxv1i1(<vscale x 1 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vpopc.i64.nxv1i1(
+    <vscale x 1 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.mask.i64.nxv1i1(
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_mask_m_i64_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv1i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf8,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv1i1(
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.i64.nxv2i1(
+  <vscale x 2 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_m_i64_nxv2i1(<vscale x 2 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vpopc.i64.nxv2i1(
+    <vscale x 2 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.mask.i64.nxv2i1(
+  <vscale x 2 x i1>,
+  <vscale x 2 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_mask_m_i64_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv2i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf4,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv2i1(
+    <vscale x 2 x i1> %0,
+    <vscale x 2 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.i64.nxv4i1(
+  <vscale x 4 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_m_i64_nxv4i1(<vscale x 4 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vpopc.i64.nxv4i1(
+    <vscale x 4 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.mask.i64.nxv4i1(
+  <vscale x 4 x i1>,
+  <vscale x 4 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_mask_m_i64_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv4i1
+; CHECK:       vsetvli {{.*}}, a0, e8,mf2,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv4i1(
+    <vscale x 4 x i1> %0,
+    <vscale x 4 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.i64.nxv8i1(
+  <vscale x 8 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_m_i64_nxv8i1(<vscale x 8 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vpopc.i64.nxv8i1(
+    <vscale x 8 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.mask.i64.nxv8i1(
+  <vscale x 8 x i1>,
+  <vscale x 8 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_mask_m_i64_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv8i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m1,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv8i1(
+    <vscale x 8 x i1> %0,
+    <vscale x 8 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.i64.nxv16i1(
+  <vscale x 16 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_m_i64_nxv16i1(<vscale x 16 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vpopc.i64.nxv16i1(
+    <vscale x 16 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.mask.i64.nxv16i1(
+  <vscale x 16 x i1>,
+  <vscale x 16 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_mask_m_i64_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv16i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m2,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv16i1(
+    <vscale x 16 x i1> %0,
+    <vscale x 16 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.i64.nxv32i1(
+  <vscale x 32 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_m_i64_nxv32i1(<vscale x 32 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vpopc.i64.nxv32i1(
+    <vscale x 32 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.mask.i64.nxv32i1(
+  <vscale x 32 x i1>,
+  <vscale x 32 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_mask_m_i64_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv32i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m4,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv32i1(
+    <vscale x 32 x i1> %0,
+    <vscale x 32 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.i64.nxv64i1(
+  <vscale x 64 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_m_i64_nxv64i1(<vscale x 64 x i1> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_m_i64_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}
+  %a = call i64 @llvm.riscv.vpopc.i64.nxv64i1(
+    <vscale x 64 x i1> %0,
+    i64 %1)
+
+  ret i64 %a
+}
+
+declare i64 @llvm.riscv.vpopc.mask.i64.nxv64i1(
+  <vscale x 64 x i1>,
+  <vscale x 64 x i1>,
+  i64);
+
+define i64 @intrinsic_vpopc_mask_m_i64_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vpopc_mask_m_i64_nxv64i1
+; CHECK:       vsetvli {{.*}}, a0, e8,m8,ta,mu
+; CHECK:       vpopc.m a0, {{v[0-9]+}}, v0.t
+  %a = call i64 @llvm.riscv.vpopc.mask.i64.nxv64i1(
+    <vscale x 64 x i1> %0,
+    <vscale x 64 x i1> %1,
+    i64 %2)
+
+  ret i64 %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
new file mode 100644
index 0000000000000..305efe8803618
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll
@@ -0,0 +1,715 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
new file mode 100644
index 0000000000000..eeeeb92424677
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll
@@ -0,0 +1,883 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64.nxv1i1(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64.nxv1i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64.nxv2i1(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64.nxv2i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64.nxv4i1(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64.nxv4i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64.nxv8i1(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredand.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64.nxv8i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
new file mode 100644
index 0000000000000..5a2c7ab416c73
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll
@@ -0,0 +1,715 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
new file mode 100644
index 0000000000000..939ae4599031a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll
@@ -0,0 +1,883 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64.nxv1i1(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64.nxv1i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64.nxv2i1(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64.nxv2i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64.nxv4i1(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64.nxv4i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64.nxv8i1(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredmax.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64.nxv8i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
new file mode 100644
index 0000000000000..734fc33ba4fd8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll
@@ -0,0 +1,715 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
new file mode 100644
index 0000000000000..68af5ac3897ad
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll
@@ -0,0 +1,883 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64.nxv1i1(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64.nxv1i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64.nxv2i1(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64.nxv2i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64.nxv4i1(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64.nxv4i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64.nxv8i1(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredmaxu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64.nxv8i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
new file mode 100644
index 0000000000000..6da1738afe206
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll
@@ -0,0 +1,715 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
new file mode 100644
index 0000000000000..6c6bc85ca1597
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll
@@ -0,0 +1,883 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64.nxv1i1(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64.nxv1i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64.nxv2i1(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64.nxv2i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64.nxv4i1(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64.nxv4i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64.nxv8i1(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredmin.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64.nxv8i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
new file mode 100644
index 0000000000000..9f26f5dea4916
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll
@@ -0,0 +1,715 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
new file mode 100644
index 0000000000000..559a870c8354a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll
@@ -0,0 +1,883 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64.nxv1i1(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64.nxv1i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64.nxv2i1(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64.nxv2i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64.nxv4i1(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64.nxv4i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64.nxv8i1(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredminu.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64.nxv8i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
new file mode 100644
index 0000000000000..5b0e2f0996750
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll
@@ -0,0 +1,715 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
new file mode 100644
index 0000000000000..9b80220814114
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll
@@ -0,0 +1,883 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64.nxv1i1(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64.nxv1i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64.nxv2i1(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64.nxv2i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64.nxv4i1(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64.nxv4i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64.nxv8i1(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64.nxv8i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
new file mode 100644
index 0000000000000..b2b95979526d3
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll
@@ -0,0 +1,715 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
new file mode 100644
index 0000000000000..7641b6ca0a4d9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll
@@ -0,0 +1,883 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64.nxv1i1(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64.nxv1i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64.nxv2i1(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64.nxv2i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64.nxv4i1(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64.nxv4i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64.nxv8i1(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredsum.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64.nxv8i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
new file mode 100644
index 0000000000000..3ea6a25320858
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll
@@ -0,0 +1,715 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
new file mode 100644
index 0000000000000..b61705eb81597
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll
@@ -0,0 +1,883 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8.nxv1i1(
+  <vscale x 8 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8.nxv1i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8.nxv2i1(
+  <vscale x 8 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8.nxv2i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8.nxv4i1(
+  <vscale x 8 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8.nxv4i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8.nxv8i1(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8.nxv8i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8.nxv16i1(
+  <vscale x 8 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8.nxv16i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8.nxv32i1(
+  <vscale x 8 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8.nxv32i1(
+    <vscale x 8 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16.nxv1i1(
+  <vscale x 4 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16.nxv1i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16.nxv2i1(
+  <vscale x 4 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16.nxv2i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16.nxv4i1(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16.nxv4i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16.nxv8i1(
+  <vscale x 4 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16.nxv8i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16.nxv16i1(
+  <vscale x 4 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16.nxv16i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16.nxv32i1(
+  <vscale x 4 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16.nxv32i1(
+    <vscale x 4 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.nxv1i1(
+  <vscale x 2 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32.nxv1i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32.nxv2i1(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32.nxv2i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32.nxv4i1(
+  <vscale x 2 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32.nxv4i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32.nxv8i1(
+  <vscale x 2 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32.nxv8i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32.nxv16i1(
+  <vscale x 2 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32.nxv16i1(
+    <vscale x 2 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64.nxv1i1(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64.nxv1i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64.nxv2i1(
+  <vscale x 1 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64.nxv2i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64.nxv4i1(
+  <vscale x 1 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64.nxv4i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64.nxv8i1(
+  <vscale x 1 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vredxor.vs {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64.nxv8i1(
+    <vscale x 1 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
new file mode 100644
index 0000000000000..cbe399a77c564
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll
@@ -0,0 +1,3624 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vle8.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i8> %2,
+    <vscale x 64 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.nxv1i16(
+  <vscale x 1 x half>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.nxv1i16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.nxv1i16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.nxv1i16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.nxv2i16(
+  <vscale x 2 x half>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.nxv2i16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.nxv2i16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.nxv2i16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.nxv4i16(
+  <vscale x 4 x half>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.nxv4i16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.nxv4i16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.nxv4i16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.nxv8i16(
+  <vscale x 8 x half>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.nxv8i16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.nxv8i16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.nxv8i16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.nxv16i16(
+  <vscale x 16 x half>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.nxv16i16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.nxv16i16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.nxv16i16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.nxv32i16(
+  <vscale x 32 x half>,
+  <vscale x 32 x i16>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.nxv32i16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.nxv1i32(
+  <vscale x 1 x float>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.nxv1i32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.nxv1i32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.nxv1i32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.nxv2i32(
+  <vscale x 2 x float>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.nxv2i32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.nxv2i32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.nxv2i32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.nxv4i32(
+  <vscale x 4 x float>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.nxv4i32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.nxv4i32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.nxv4i32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.nxv8i32(
+  <vscale x 8 x float>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.nxv8i32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.nxv8i32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.nxv8i32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.nxv16i32(
+  <vscale x 16 x float>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.nxv16i32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vrgather_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vrgather_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vrgather_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vrgather_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vrgather_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vrgather_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vrgather_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vrgather_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vrgather_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vrgather_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vrgather_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vrgather_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vrgather_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vrgather_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vrgather_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.i16(
+  <vscale x 1 x half>,
+  i16,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vrgather_vx_nxv1f16_nxv1f16_i16(<vscale x 1 x half> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f16_nxv1f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.i16(
+    <vscale x 1 x half> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.i16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x half> @intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16_i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.i16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.i16(
+  <vscale x 2 x half>,
+  i16,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vrgather_vx_nxv2f16_nxv2f16_i16(<vscale x 2 x half> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f16_nxv2f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.i16(
+    <vscale x 2 x half> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.i16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x half> @intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16_i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.i16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.i16(
+  <vscale x 4 x half>,
+  i16,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vrgather_vx_nxv4f16_nxv4f16_i16(<vscale x 4 x half> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.i16(
+    <vscale x 4 x half> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.i16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x half> @intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.i16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.i16(
+  <vscale x 8 x half>,
+  i16,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vrgather_vx_nxv8f16_nxv8f16_i16(<vscale x 8 x half> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.i16(
+    <vscale x 8 x half> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.i16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x half> @intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.i16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.i16(
+  <vscale x 16 x half>,
+  i16,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vrgather_vx_nxv16f16_nxv16f16_i16(<vscale x 16 x half> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.i16(
+    <vscale x 16 x half> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.i16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x half> @intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.i16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.i16(
+  <vscale x 32 x half>,
+  i16,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vrgather_vx_nxv32f16_nxv32f16_i16(<vscale x 32 x half> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv32f16_nxv32f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.i16(
+    <vscale x 32 x half> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.i16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  i16,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x half> @intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.i16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.i32(
+  <vscale x 1 x float>,
+  i32,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vrgather_vx_nxv1f32_nxv1f32_i32(<vscale x 1 x float> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f32_nxv1f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.i32(
+    <vscale x 1 x float> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.i32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x float> @intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32_i32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.i32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.i32(
+  <vscale x 2 x float>,
+  i32,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32(<vscale x 2 x float> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.i32(
+    <vscale x 2 x float> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.i32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x float> @intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.i32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.i32(
+  <vscale x 4 x float>,
+  i32,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32(<vscale x 4 x float> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.i32(
+    <vscale x 4 x float> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.i32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x float> @intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.i32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.i32(
+  <vscale x 8 x float>,
+  i32,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32(<vscale x 8 x float> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.i32(
+    <vscale x 8 x float> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.i32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x float> @intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.i32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.i32(
+  <vscale x 16 x float>,
+  i32,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vrgather_vx_nxv16f32_nxv16f32_i32(<vscale x 16 x float> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f32_nxv16f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.i32(
+    <vscale x 16 x float> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.i32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  i32,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x float> @intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.i32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vrgather_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vrgather_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vrgather_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vrgather_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vrgather_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vrgather_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vrgather_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 9,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vrgather_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vrgather_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vrgather_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vrgather_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vrgather_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vrgather_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vrgather_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vrgather_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x half> @intrinsic_vrgather_vi_nxv1f16_nxv1f16_i16(<vscale x 1 x half> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f16_nxv1f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.i16(
+    <vscale x 1 x half> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x half> %a
+}
+
+define <vscale x 1 x half> @intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16_i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.i16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+define <vscale x 2 x half> @intrinsic_vrgather_vi_nxv2f16_nxv2f16_i16(<vscale x 2 x half> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f16_nxv2f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.i16(
+    <vscale x 2 x half> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x half> %a
+}
+
+define <vscale x 2 x half> @intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16_i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.i16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+define <vscale x 4 x half> @intrinsic_vrgather_vi_nxv4f16_nxv4f16_i16(<vscale x 4 x half> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.i16(
+    <vscale x 4 x half> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x half> %a
+}
+
+define <vscale x 4 x half> @intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.i16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+define <vscale x 8 x half> @intrinsic_vrgather_vi_nxv8f16_nxv8f16_i16(<vscale x 8 x half> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.i16(
+    <vscale x 8 x half> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x half> %a
+}
+
+define <vscale x 8 x half> @intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.i16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+define <vscale x 16 x half> @intrinsic_vrgather_vi_nxv16f16_nxv16f16_i16(<vscale x 16 x half> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.i16(
+    <vscale x 16 x half> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x half> %a
+}
+
+define <vscale x 16 x half> @intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.i16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+define <vscale x 32 x half> @intrinsic_vrgather_vi_nxv32f16_nxv32f16_i16(<vscale x 32 x half> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv32f16_nxv32f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.i16(
+    <vscale x 32 x half> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 32 x half> %a
+}
+
+define <vscale x 32 x half> @intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.i16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+define <vscale x 1 x float> @intrinsic_vrgather_vi_nxv1f32_nxv1f32_i32(<vscale x 1 x float> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f32_nxv1f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.i32(
+    <vscale x 1 x float> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x float> %a
+}
+
+define <vscale x 1 x float> @intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32_i32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.i32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+define <vscale x 2 x float> @intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32(<vscale x 2 x float> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.i32(
+    <vscale x 2 x float> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x float> %a
+}
+
+define <vscale x 2 x float> @intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.i32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+define <vscale x 4 x float> @intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32(<vscale x 4 x float> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.i32(
+    <vscale x 4 x float> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x float> %a
+}
+
+define <vscale x 4 x float> @intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.i32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+define <vscale x 8 x float> @intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32(<vscale x 8 x float> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.i32(
+    <vscale x 8 x float> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x float> %a
+}
+
+define <vscale x 8 x float> @intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.i32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+define <vscale x 16 x float> @intrinsic_vrgather_vi_nxv16f32_nxv16f32_i32(<vscale x 16 x float> %0, i32 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f32_nxv16f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.i32(
+    <vscale x 16 x float> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 16 x float> %a
+}
+
+define <vscale x 16 x float> @intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.i32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x float> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
new file mode 100644
index 0000000000000..c9c0a7221433d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll
@@ -0,0 +1,4630 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i8_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i8_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i8_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i8_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv64i8_nxv64i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv64i8_nxv64i8_nxv64i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a1)
+; CHECK-NEXT:    vle8.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i8> %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i16_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i16_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i16_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i16_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i16_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i16_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i16_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i16_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i16_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i16_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv32i16_nxv32i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32i16_nxv32i16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i32_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i32_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i32_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i32_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i32_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i32_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i32_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i32_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16i32_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16i32_nxv16i32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vrgather.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1i64_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vrgather.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vrgather_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1i64_nxv1i64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vrgather.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2i64_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vrgather.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vrgather_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2i64_nxv2i64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vrgather.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4i64_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vrgather.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4i64_nxv4i64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vrgather.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8i64_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vrgather.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8i64_nxv8i64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vle64.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.nxv1i16(
+  <vscale x 1 x half>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f16_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.nxv1i16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.nxv1i16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f16_nxv1f16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.nxv1i16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.nxv2i16(
+  <vscale x 2 x half>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f16_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.nxv2i16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.nxv2i16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f16_nxv2f16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.nxv2i16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.nxv4i16(
+  <vscale x 4 x half>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f16_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.nxv4i16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.nxv4i16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f16_nxv4f16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.nxv4i16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.nxv8i16(
+  <vscale x 8 x half>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f16_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.nxv8i16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.nxv8i16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f16_nxv8f16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.nxv8i16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.nxv16i16(
+  <vscale x 16 x half>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f16_nxv16f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.nxv16i16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.nxv16i16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f16_nxv16f16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.nxv16i16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.nxv32i16(
+  <vscale x 32 x half>,
+  <vscale x 32 x i16>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv32f16_nxv32f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.nxv32i16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv32f16_nxv32f16_nxv32i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a1)
+; CHECK-NEXT:    vle16.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.nxv32i16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.nxv1i32(
+  <vscale x 1 x float>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f32_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.nxv1i32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.nxv1i32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f32_nxv1f32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.nxv1i32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.nxv2i32(
+  <vscale x 2 x float>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f32_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.nxv2i32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.nxv2i32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f32_nxv2f32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.nxv2i32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.nxv4i32(
+  <vscale x 4 x float>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f32_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.nxv4i32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.nxv4i32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f32_nxv4f32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.nxv4i32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.nxv8i32(
+  <vscale x 8 x float>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f32_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.nxv8i32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.nxv8i32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f32_nxv8f32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.nxv8i32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.nxv16i32(
+  <vscale x 16 x float>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv16f32_nxv16f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.nxv16i32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv16f32_nxv16f32_nxv16i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vle32.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.nxv16i32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vrgather.nxv1f64.nxv1i64(
+  <vscale x 1 x double>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv1f64_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v25, v16, v17
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.nxv1f64.nxv1i64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vrgather.mask.nxv1f64.nxv1i64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv1f64_nxv1f64_nxv1i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.mask.nxv1f64.nxv1i64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vrgather.nxv2f64.nxv2i64(
+  <vscale x 2 x double>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv2f64_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v26, v16, v18
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.nxv2f64.nxv2i64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vrgather.mask.nxv2f64.nxv2i64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv2f64_nxv2f64_nxv2i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v18, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.mask.nxv2f64.nxv2i64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vrgather.nxv4f64.nxv4i64(
+  <vscale x 4 x double>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv4f64_nxv4f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v28, v16, v20
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.nxv4f64.nxv4i64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vrgather.mask.nxv4f64.nxv4i64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv4f64_nxv4f64_nxv4i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v20, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.mask.nxv4f64.nxv4i64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vrgather.nxv8f64.nxv8i64(
+  <vscale x 8 x double>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vv_nxv8f64_nxv8f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v8, v16, v24
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.nxv8f64.nxv8i64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.nxv8i64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vv_nxv8f64_nxv8f64_nxv8i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vle64.v v24, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vv v16, v24, v8, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.nxv8i64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vrgather_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vrgather_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vrgather_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vrgather_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vrgather_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vrgather_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vrgather_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vrgather_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vrgather_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vrgather_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vrgather_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vrgather_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vrgather_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vrgather_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vrgather_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vrgather.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vrgather_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vrgather.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vrgather_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vrgather.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vrgather_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vrgather.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vrgather_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vrgather.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vrgather_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vrgather.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vrgather_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vrgather.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  i64,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vrgather_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vrgather.mask.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.i16(
+  <vscale x 1 x half>,
+  i16,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vrgather_vx_nxv1f16_nxv1f16_i16(<vscale x 1 x half> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f16_nxv1f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.i16(
+    <vscale x 1 x half> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.i16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x half> @intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16_i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f16_nxv1f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.i16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.i16(
+  <vscale x 2 x half>,
+  i16,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vrgather_vx_nxv2f16_nxv2f16_i16(<vscale x 2 x half> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f16_nxv2f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.i16(
+    <vscale x 2 x half> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.i16(
+  <vscale x 2 x half>,
+  <vscale x 2 x half>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x half> @intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16_i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f16_nxv2f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.i16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.i16(
+  <vscale x 4 x half>,
+  i16,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vrgather_vx_nxv4f16_nxv4f16_i16(<vscale x 4 x half> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f16_nxv4f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.i16(
+    <vscale x 4 x half> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.i16(
+  <vscale x 4 x half>,
+  <vscale x 4 x half>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x half> @intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f16_nxv4f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.i16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.i16(
+  <vscale x 8 x half>,
+  i16,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vrgather_vx_nxv8f16_nxv8f16_i16(<vscale x 8 x half> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f16_nxv8f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.i16(
+    <vscale x 8 x half> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.i16(
+  <vscale x 8 x half>,
+  <vscale x 8 x half>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x half> @intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f16_nxv8f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.i16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.i16(
+  <vscale x 16 x half>,
+  i16,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vrgather_vx_nxv16f16_nxv16f16_i16(<vscale x 16 x half> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f16_nxv16f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.i16(
+    <vscale x 16 x half> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.i16(
+  <vscale x 16 x half>,
+  <vscale x 16 x half>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x half> @intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f16_nxv16f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.i16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.i16(
+  <vscale x 32 x half>,
+  i16,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vrgather_vx_nxv32f16_nxv32f16_i16(<vscale x 32 x half> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv32f16_nxv32f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.i16(
+    <vscale x 32 x half> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.i16(
+  <vscale x 32 x half>,
+  <vscale x 32 x half>,
+  i16,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x half> @intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv32f16_nxv32f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.i16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x half> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.i32(
+  <vscale x 1 x float>,
+  i32,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vrgather_vx_nxv1f32_nxv1f32_i32(<vscale x 1 x float> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f32_nxv1f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.i32(
+    <vscale x 1 x float> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.i32(
+  <vscale x 1 x float>,
+  <vscale x 1 x float>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x float> @intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32_i32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f32_nxv1f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.i32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.i32(
+  <vscale x 2 x float>,
+  i32,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32(<vscale x 2 x float> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f32_nxv2f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.i32(
+    <vscale x 2 x float> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.i32(
+  <vscale x 2 x float>,
+  <vscale x 2 x float>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x float> @intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f32_nxv2f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.i32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.i32(
+  <vscale x 4 x float>,
+  i32,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32(<vscale x 4 x float> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f32_nxv4f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.i32(
+    <vscale x 4 x float> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.i32(
+  <vscale x 4 x float>,
+  <vscale x 4 x float>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x float> @intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f32_nxv4f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.i32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.i32(
+  <vscale x 8 x float>,
+  i32,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32(<vscale x 8 x float> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f32_nxv8f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.i32(
+    <vscale x 8 x float> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.i32(
+  <vscale x 8 x float>,
+  <vscale x 8 x float>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x float> @intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f32_nxv8f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.i32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.i32(
+  <vscale x 16 x float>,
+  i32,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vrgather_vx_nxv16f32_nxv16f32_i32(<vscale x 16 x float> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv16f32_nxv16f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.i32(
+    <vscale x 16 x float> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.i32(
+  <vscale x 16 x float>,
+  <vscale x 16 x float>,
+  i32,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x float> @intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv16f32_nxv16f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.i32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x float> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vrgather.nxv1f64.i64(
+  <vscale x 1 x double>,
+  i64,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vrgather_vx_nxv1f64_nxv1f64_i64(<vscale x 1 x double> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv1f64_nxv1f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.nxv1f64.i64(
+    <vscale x 1 x double> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 1 x double> @llvm.riscv.vrgather.mask.nxv1f64.i64(
+  <vscale x 1 x double>,
+  <vscale x 1 x double>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x double> @intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64_i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv1f64_nxv1f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.mask.nxv1f64.i64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vrgather.nxv2f64.i64(
+  <vscale x 2 x double>,
+  i64,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vrgather_vx_nxv2f64_nxv2f64_i64(<vscale x 2 x double> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv2f64_nxv2f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.nxv2f64.i64(
+    <vscale x 2 x double> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 2 x double> @llvm.riscv.vrgather.mask.nxv2f64.i64(
+  <vscale x 2 x double>,
+  <vscale x 2 x double>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x double> @intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64_i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv2f64_nxv2f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.mask.nxv2f64.i64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vrgather.nxv4f64.i64(
+  <vscale x 4 x double>,
+  i64,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vrgather_vx_nxv4f64_nxv4f64_i64(<vscale x 4 x double> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv4f64_nxv4f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.nxv4f64.i64(
+    <vscale x 4 x double> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 4 x double> @llvm.riscv.vrgather.mask.nxv4f64.i64(
+  <vscale x 4 x double>,
+  <vscale x 4 x double>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x double> @intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64_i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv4f64_nxv4f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.mask.nxv4f64.i64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vrgather.nxv8f64.i64(
+  <vscale x 8 x double>,
+  i64,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vrgather_vx_nxv8f64_nxv8f64_i64(<vscale x 8 x double> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vx_nxv8f64_nxv8f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.nxv8f64.i64(
+    <vscale x 8 x double> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 8 x double> %a
+}
+
+declare <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.i64(
+  <vscale x 8 x double>,
+  <vscale x 8 x double>,
+  i64,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x double> @intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64_i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vx_nxv8f64_nxv8f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.i64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    i64 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x double> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vrgather_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vrgather.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vrgather_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vrgather.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vrgather_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vrgather.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vrgather_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vrgather.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vrgather_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vrgather.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vrgather_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vrgather.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vrgather_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vrgather.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 9,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vrgather_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vrgather.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vrgather_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vrgather.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vrgather_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vrgather.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vrgather_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vrgather.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vrgather_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vrgather.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vrgather_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vrgather.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vrgather_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vrgather.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vrgather.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vrgather.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vrgather.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vrgather_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vrgather.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vrgather_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vrgather_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vrgather.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vrgather_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vrgather_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vrgather.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vrgather_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vrgather_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vrgather.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vrgather_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vrgather.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 1 x half> @intrinsic_vrgather_vi_nxv1f16_nxv1f16_i16(<vscale x 1 x half> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f16_nxv1f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.nxv1f16.i16(
+    <vscale x 1 x half> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x half> %a
+}
+
+define <vscale x 1 x half> @intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16_i16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f16_nxv1f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x half> @llvm.riscv.vrgather.mask.nxv1f16.i16(
+    <vscale x 1 x half> %0,
+    <vscale x 1 x half> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x half> %a
+}
+
+define <vscale x 2 x half> @intrinsic_vrgather_vi_nxv2f16_nxv2f16_i16(<vscale x 2 x half> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f16_nxv2f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.nxv2f16.i16(
+    <vscale x 2 x half> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x half> %a
+}
+
+define <vscale x 2 x half> @intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16_i16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f16_nxv2f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x half> @llvm.riscv.vrgather.mask.nxv2f16.i16(
+    <vscale x 2 x half> %0,
+    <vscale x 2 x half> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x half> %a
+}
+
+define <vscale x 4 x half> @intrinsic_vrgather_vi_nxv4f16_nxv4f16_i16(<vscale x 4 x half> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f16_nxv4f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.nxv4f16.i16(
+    <vscale x 4 x half> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x half> %a
+}
+
+define <vscale x 4 x half> @intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f16_nxv4f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x half> @llvm.riscv.vrgather.mask.nxv4f16.i16(
+    <vscale x 4 x half> %0,
+    <vscale x 4 x half> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x half> %a
+}
+
+define <vscale x 8 x half> @intrinsic_vrgather_vi_nxv8f16_nxv8f16_i16(<vscale x 8 x half> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f16_nxv8f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.nxv8f16.i16(
+    <vscale x 8 x half> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x half> %a
+}
+
+define <vscale x 8 x half> @intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f16_nxv8f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x half> @llvm.riscv.vrgather.mask.nxv8f16.i16(
+    <vscale x 8 x half> %0,
+    <vscale x 8 x half> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x half> %a
+}
+
+define <vscale x 16 x half> @intrinsic_vrgather_vi_nxv16f16_nxv16f16_i16(<vscale x 16 x half> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f16_nxv16f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.nxv16f16.i16(
+    <vscale x 16 x half> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x half> %a
+}
+
+define <vscale x 16 x half> @intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f16_nxv16f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x half> @llvm.riscv.vrgather.mask.nxv16f16.i16(
+    <vscale x 16 x half> %0,
+    <vscale x 16 x half> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x half> %a
+}
+
+define <vscale x 32 x half> @intrinsic_vrgather_vi_nxv32f16_nxv32f16_i16(<vscale x 32 x half> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv32f16_nxv32f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.nxv32f16.i16(
+    <vscale x 32 x half> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 32 x half> %a
+}
+
+define <vscale x 32 x half> @intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv32f16_nxv32f16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x half> @llvm.riscv.vrgather.mask.nxv32f16.i16(
+    <vscale x 32 x half> %0,
+    <vscale x 32 x half> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x half> %a
+}
+
+define <vscale x 1 x float> @intrinsic_vrgather_vi_nxv1f32_nxv1f32_i32(<vscale x 1 x float> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f32_nxv1f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.nxv1f32.i32(
+    <vscale x 1 x float> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x float> %a
+}
+
+define <vscale x 1 x float> @intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32_i32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f32_nxv1f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x float> @llvm.riscv.vrgather.mask.nxv1f32.i32(
+    <vscale x 1 x float> %0,
+    <vscale x 1 x float> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x float> %a
+}
+
+define <vscale x 2 x float> @intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32(<vscale x 2 x float> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f32_nxv2f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.nxv2f32.i32(
+    <vscale x 2 x float> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x float> %a
+}
+
+define <vscale x 2 x float> @intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f32_nxv2f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x float> @llvm.riscv.vrgather.mask.nxv2f32.i32(
+    <vscale x 2 x float> %0,
+    <vscale x 2 x float> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x float> %a
+}
+
+define <vscale x 4 x float> @intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32(<vscale x 4 x float> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f32_nxv4f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.nxv4f32.i32(
+    <vscale x 4 x float> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x float> %a
+}
+
+define <vscale x 4 x float> @intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f32_nxv4f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x float> @llvm.riscv.vrgather.mask.nxv4f32.i32(
+    <vscale x 4 x float> %0,
+    <vscale x 4 x float> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x float> %a
+}
+
+define <vscale x 8 x float> @intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32(<vscale x 8 x float> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f32_nxv8f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.nxv8f32.i32(
+    <vscale x 8 x float> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x float> %a
+}
+
+define <vscale x 8 x float> @intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f32_nxv8f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x float> @llvm.riscv.vrgather.mask.nxv8f32.i32(
+    <vscale x 8 x float> %0,
+    <vscale x 8 x float> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x float> %a
+}
+
+define <vscale x 16 x float> @intrinsic_vrgather_vi_nxv16f32_nxv16f32_i32(<vscale x 16 x float> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv16f32_nxv16f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.nxv16f32.i32(
+    <vscale x 16 x float> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 16 x float> %a
+}
+
+define <vscale x 16 x float> @intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv16f32_nxv16f32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x float> @llvm.riscv.vrgather.mask.nxv16f32.i32(
+    <vscale x 16 x float> %0,
+    <vscale x 16 x float> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x float> %a
+}
+
+define <vscale x 1 x double> @intrinsic_vrgather_vi_nxv1f64_nxv1f64_i64(<vscale x 1 x double> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv1f64_nxv1f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v25, v16, 9
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.nxv1f64.i64(
+    <vscale x 1 x double> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x double> %a
+}
+
+define <vscale x 1 x double> @intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64_i64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv1f64_nxv1f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m1,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v17, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x double> @llvm.riscv.vrgather.mask.nxv1f64.i64(
+    <vscale x 1 x double> %0,
+    <vscale x 1 x double> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x double> %a
+}
+
+define <vscale x 2 x double> @intrinsic_vrgather_vi_nxv2f64_nxv2f64_i64(<vscale x 2 x double> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv2f64_nxv2f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v26, v16, 9
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.nxv2f64.i64(
+    <vscale x 2 x double> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x double> %a
+}
+
+define <vscale x 2 x double> @intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64_i64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv2f64_nxv2f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m2,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v18, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x double> @llvm.riscv.vrgather.mask.nxv2f64.i64(
+    <vscale x 2 x double> %0,
+    <vscale x 2 x double> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x double> %a
+}
+
+define <vscale x 4 x double> @intrinsic_vrgather_vi_nxv4f64_nxv4f64_i64(<vscale x 4 x double> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv4f64_nxv4f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v28, v16, 9
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.nxv4f64.i64(
+    <vscale x 4 x double> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x double> %a
+}
+
+define <vscale x 4 x double> @intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64_i64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv4f64_nxv4f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m4,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v20, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x double> @llvm.riscv.vrgather.mask.nxv4f64.i64(
+    <vscale x 4 x double> %0,
+    <vscale x 4 x double> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x double> %a
+}
+
+define <vscale x 8 x double> @intrinsic_vrgather_vi_nxv8f64_nxv8f64_i64(<vscale x 8 x double> %0, i64 %1) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_vi_nxv8f64_nxv8f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v8, v16, 9
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.nxv8f64.i64(
+    <vscale x 8 x double> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 8 x double> %a
+}
+
+define <vscale x 8 x double> @intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64_i64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vrgather_mask_vi_nxv8f64_nxv8f64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vrgather.vi v16, v8, 9, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x double> @llvm.riscv.vrgather.mask.nxv8f64.i64(
+    <vscale x 8 x double> %0,
+    <vscale x 8 x double> %1,
+    i64 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x double> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
new file mode 100644
index 0000000000000..34d055777cc3f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
@@ -0,0 +1,845 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vshl_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vshl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vshl_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vshl_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vshl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vshl_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vshl_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vshl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vshl_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vshl_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vshl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vshl_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vshl_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vshl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vshl_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vshl_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vshl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vshl_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv32i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vshl_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = shl <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vshl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = shl <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vshl_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv64i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = shl <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vshl_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vshl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vshl_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vshl_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vshl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vshl_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vshl_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vshl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vshl_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vshl_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vshl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vshl_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vshl_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vshl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vshl_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vshl_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vshl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vshl_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv32i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vshl_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vshl_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vshl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vshl_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vshl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vshl_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vshl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vshl_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vshl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vshl_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vshl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vshl_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vshl_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vshl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
+; CHECK-LABEL: vshl_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vshl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vshl_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vshl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vshl_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vsll.vv v16, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vshl_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vshl_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vshl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vshl_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vsrl.vx v28, v28, a1
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vsll.vv v16, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vshl_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vshl_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vshl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vshl_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vsrl.vx v8, v8, a1
+; CHECK-NEXT:    vor.vv v28, v8, v28
+; CHECK-NEXT:    vsll.vv v16, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vshl_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vshl_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vshl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vshl_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vsll.vv v16, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vshl_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vshl_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
new file mode 100644
index 0000000000000..23c51934743f0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll
@@ -0,0 +1,817 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vshl_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vshl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vshl_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vshl_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vshl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vshl_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vshl_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vshl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vshl_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vshl_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vshl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vshl_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vshl_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vshl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vshl_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vshl_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vshl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vshl_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv32i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vshl_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = shl <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vshl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = shl <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vshl_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vshl_vx_nxv64i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = shl <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vshl_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vshl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vshl_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vshl_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vshl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vshl_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vshl_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vshl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vshl_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vshl_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vshl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vshl_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vshl_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vshl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vshl_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vshl_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vshl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vshl_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vshl_vx_nxv32i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = shl <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vshl_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vshl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vshl_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vshl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vshl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vshl_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vshl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vshl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vshl_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vshl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vshl_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vshl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vshl_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vshl_vx_nxv16i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = shl <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vshl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vshl_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vshl_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vshl_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv1i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = shl <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vshl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vshl_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vshl_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vshl_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv2i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = shl <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vshl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vshl_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vshl_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vshl_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv4i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = shl <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vshl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vshl_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vshl_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsll.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vshl_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vshl_vx_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsll.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
new file mode 100644
index 0000000000000..1ff3600d7c9ad
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll
@@ -0,0 +1,800 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll
new file mode 100644
index 0000000000000..c86475c750567
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vslide1down-rv64.ll
@@ -0,0 +1,978 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vslide1down.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vslide1down.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vslide1down.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vslide1down.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vslide1down.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vslide1down.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vslide1down.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vslide1down.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vslide1down.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vslide1down.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vslide1down.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vslide1down.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vslide1down.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vslide1down.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vslide1down.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vslide1down.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vslide1down.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vslide1down.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vslide1down.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vslide1down.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vslide1down.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  i64,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_vx_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v16, a0
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vslide1down.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1down_mask_vx_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
+; CHECK-NEXT:    vslide1down.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vslide1down.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
new file mode 100644
index 0000000000000..29e2421732641
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
new file mode 100644
index 0000000000000..f514b60528917
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll
@@ -0,0 +1,1000 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i8_nxv1i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vslide1up.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vslide1up.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vslide1up_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i8_nxv2i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i8> @llvm.riscv.vslide1up.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vslide1up.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vslide1up_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i8_nxv4i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i8> @llvm.riscv.vslide1up.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vslide1up.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i8_nxv8i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i8> @llvm.riscv.vslide1up.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vslide1up.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i8_nxv16i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i8> @llvm.riscv.vslide1up.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vslide1up.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i8_nxv32i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i8> @llvm.riscv.vslide1up.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vslide1up.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv64i8_nxv64i8_i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 64 x i8> @llvm.riscv.vslide1up.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vslide1up.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vslide1up_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i16_nxv1i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vslide1up.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vslide1up.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vslide1up_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i16_nxv2i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vslide1up.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vslide1up.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i16_nxv4i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vslide1up.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vslide1up.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i16_nxv8i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vslide1up.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vslide1up.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i16_nxv16i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vslide1up.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vslide1up.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv32i16_nxv32i16_i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vslide1up.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vslide1up.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vslide1up_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i32_nxv1i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vslide1up.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vslide1up.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i32_nxv2i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vslide1up.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vslide1up.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i32_nxv4i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vslide1up.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vslide1up.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i32_nxv8i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vslide1up.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vslide1up.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv16i32_nxv16i32_i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vslide1up.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vslide1up.vx v25, v16, a0
+; CHECK-NEXT:    vmv1r.v v16, v25
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv1i64_nxv1i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m1,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v17, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vslide1up.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v26, v16, a0
+; CHECK-NEXT:    vmv2r.v v16, v26
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv2i64_nxv2i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m2,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v18, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vslide1up.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v28, v16, a0
+; CHECK-NEXT:    vmv4r.v v16, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv4i64_nxv4i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m4,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v20, a0, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vslide1up.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  i64,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_vx_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e64,m8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v8, v16, a0
+; CHECK-NEXT:    vmv8r.v v16, v8
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vslide1up.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vslide1up_mask_vx_nxv8i64_nxv8i64_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e64,m8,ta,mu
+; CHECK-NEXT:    vslide1up.vx v16, v8, a1, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vslide1up.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
new file mode 100644
index 0000000000000..4c6931af261a1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
@@ -0,0 +1,266 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV32V
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64V
+
+define <vscale x 8 x i64> @vsplat_nxv8i64_1() {
+; RV32V-LABEL: vsplat_nxv8i64_1:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vmv.v.i v16, -1
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vsplat_nxv8i64_1:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vmv.v.i v16, -1
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i64> %splat
+}
+
+define <vscale x 8 x i64> @vsplat_nxv8i64_2() {
+; RV32V-LABEL: vsplat_nxv8i64_2:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vmv.v.i v16, 4
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vsplat_nxv8i64_2:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vmv.v.i v16, 4
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 4, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i64> %splat
+}
+
+define <vscale x 8 x i64> @vsplat_nxv8i64_3() {
+; RV32V-LABEL: vsplat_nxv8i64_3:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    addi a0, zero, 255
+; RV32V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vmv.v.x v16, a0
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vsplat_nxv8i64_3:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    addi a0, zero, 255
+; RV64V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vmv.v.x v16, a0
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 255, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i64> %splat
+}
+
+define <vscale x 8 x i64> @vsplat_nxv8i64_4() {
+; RV32V-LABEL: vsplat_nxv8i64_4:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    lui a0, 1028096
+; RV32V-NEXT:    addi a0, a0, -1281
+; RV32V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vmv.v.x v8, a0
+; RV32V-NEXT:    addi a0, zero, 32
+; RV32V-NEXT:    vsll.vx v8, v8, a0
+; RV32V-NEXT:    vsrl.vx v16, v8, a0
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vsplat_nxv8i64_4:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    addi a0, zero, 251
+; RV64V-NEXT:    slli a0, a0, 24
+; RV64V-NEXT:    addi a0, a0, -1281
+; RV64V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vmv.v.x v16, a0
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 4211079935, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i64> %splat
+}
+
+define <vscale x 8 x i64> @vsplat_nxv8i64_5(i64 %a) {
+; RV32V-LABEL: vsplat_nxv8i64_5:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vmv.v.x v8, a1
+; RV32V-NEXT:    addi a1, zero, 32
+; RV32V-NEXT:    vsll.vx v8, v8, a1
+; RV32V-NEXT:    vmv.v.x v16, a0
+; RV32V-NEXT:    vsll.vx v16, v16, a1
+; RV32V-NEXT:    vsrl.vx v16, v16, a1
+; RV32V-NEXT:    vor.vv v16, v16, v8
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vsplat_nxv8i64_5:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vmv.v.x v16, a0
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %a, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i64> %splat
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_6(<vscale x 8 x i64> %v) {
+; RV32V-LABEL: vadd_vx_nxv8i64_6:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vadd.vi v16, v16, 2
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vadd_vx_nxv8i64_6:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vadd.vi v16, v16, 2
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 2, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vret = add <vscale x 8 x i64> %v, %splat
+  ret <vscale x 8 x i64> %vret
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_7(<vscale x 8 x i64> %v) {
+; RV32V-LABEL: vadd_vx_nxv8i64_7:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vadd.vi v16, v16, -1
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vadd_vx_nxv8i64_7:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vadd.vi v16, v16, -1
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vret = add <vscale x 8 x i64> %v, %splat
+  ret <vscale x 8 x i64> %vret
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_8(<vscale x 8 x i64> %v) {
+; RV32V-LABEL: vadd_vx_nxv8i64_8:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    addi a0, zero, 255
+; RV32V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vadd.vx v16, v16, a0
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vadd_vx_nxv8i64_8:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    addi a0, zero, 255
+; RV64V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vadd.vx v16, v16, a0
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 255, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vret = add <vscale x 8 x i64> %v, %splat
+  ret <vscale x 8 x i64> %vret
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_9(<vscale x 8 x i64> %v) {
+; RV32V-LABEL: vadd_vx_nxv8i64_9:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    lui a0, 503808
+; RV32V-NEXT:    addi a0, a0, -1281
+; RV32V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vadd.vx v16, v16, a0
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vadd_vx_nxv8i64_9:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    lui a0, 503808
+; RV64V-NEXT:    addiw a0, a0, -1281
+; RV64V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vadd.vx v16, v16, a0
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 2063596287, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vret = add <vscale x 8 x i64> %v, %splat
+  ret <vscale x 8 x i64> %vret
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_10(<vscale x 8 x i64> %v) {
+; RV32V-LABEL: vadd_vx_nxv8i64_10:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    lui a0, 1028096
+; RV32V-NEXT:    addi a0, a0, -1281
+; RV32V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vmv.v.x v8, a0
+; RV32V-NEXT:    addi a0, zero, 32
+; RV32V-NEXT:    vsll.vx v8, v8, a0
+; RV32V-NEXT:    vsrl.vx v8, v8, a0
+; RV32V-NEXT:    vadd.vv v16, v16, v8
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vadd_vx_nxv8i64_10:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    addi a0, zero, 251
+; RV64V-NEXT:    slli a0, a0, 24
+; RV64V-NEXT:    addi a0, a0, -1281
+; RV64V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vadd.vx v16, v16, a0
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 4211079935, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vret = add <vscale x 8 x i64> %v, %splat
+  ret <vscale x 8 x i64> %vret
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_11(<vscale x 8 x i64> %v) {
+; RV32V-LABEL: vadd_vx_nxv8i64_11:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vmv.v.i v8, 1
+; RV32V-NEXT:    addi a0, zero, 32
+; RV32V-NEXT:    vsll.vx v8, v8, a0
+; RV32V-NEXT:    lui a1, 1028096
+; RV32V-NEXT:    addi a1, a1, -1281
+; RV32V-NEXT:    vmv.v.x v24, a1
+; RV32V-NEXT:    vsll.vx v24, v24, a0
+; RV32V-NEXT:    vsrl.vx v24, v24, a0
+; RV32V-NEXT:    vor.vv v8, v24, v8
+; RV32V-NEXT:    vadd.vv v16, v16, v8
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vadd_vx_nxv8i64_11:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    addi a0, zero, 507
+; RV64V-NEXT:    slli a0, a0, 24
+; RV64V-NEXT:    addi a0, a0, -1281
+; RV64V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vadd.vx v16, v16, a0
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 8506047231, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vret = add <vscale x 8 x i64> %v, %splat
+  ret <vscale x 8 x i64> %vret
+}
+
+define <vscale x 8 x i64> @vadd_vx_nxv8i64_12(<vscale x 8 x i64> %v, i64 %a) {
+; RV32V-LABEL: vadd_vx_nxv8i64_12:
+; RV32V:       # %bb.0:
+; RV32V-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; RV32V-NEXT:    vmv.v.x v8, a1
+; RV32V-NEXT:    addi a1, zero, 32
+; RV32V-NEXT:    vsll.vx v8, v8, a1
+; RV32V-NEXT:    vmv.v.x v24, a0
+; RV32V-NEXT:    vsll.vx v24, v24, a1
+; RV32V-NEXT:    vsrl.vx v24, v24, a1
+; RV32V-NEXT:    vor.vv v8, v24, v8
+; RV32V-NEXT:    vadd.vv v16, v16, v8
+; RV32V-NEXT:    ret
+;
+; RV64V-LABEL: vadd_vx_nxv8i64_12:
+; RV64V:       # %bb.0:
+; RV64V-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; RV64V-NEXT:    vadd.vx v16, v16, a0
+; RV64V-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %a, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vret = add <vscale x 8 x i64> %v, %splat
+  ret <vscale x 8 x i64> %vret
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
new file mode 100644
index 0000000000000..7d0b1af014deb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
@@ -0,0 +1,845 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vsrl_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsrl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsrl_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsrl_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsrl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsrl_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsrl_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsrl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsrl_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsrl_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsrl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsrl_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsrl_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsrl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsrl_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsrl_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsrl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsrl_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv32i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsrl_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = lshr <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsrl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = lshr <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsrl_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv64i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = lshr <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vsrl_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsrl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsrl_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsrl_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsrl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsrl_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsrl_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsrl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsrl_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsrl_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsrl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsrl_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsrl_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsrl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsrl_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsrl_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsrl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsrl_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv32i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vsrl_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsrl_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsrl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsrl_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsrl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsrl_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsrl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsrl_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsrl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsrl_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsrl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsrl_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsrl_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsrl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b) {
+; CHECK-LABEL: vsrl_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsrl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsrl_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vsrl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsrl_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.x v25, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v25, v25, a1
+; CHECK-NEXT:    vmv.v.x v26, a0
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vsrl.vx v26, v26, a1
+; CHECK-NEXT:    vor.vv v25, v26, v25
+; CHECK-NEXT:    vsrl.vv v16, v16, v25
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsrl_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsrl_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsrl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsrl_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vmv.v.x v26, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v26, v26, a1
+; CHECK-NEXT:    vmv.v.x v28, a0
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vsrl.vx v28, v28, a1
+; CHECK-NEXT:    vor.vv v26, v28, v26
+; CHECK-NEXT:    vsrl.vv v16, v16, v26
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsrl_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsrl_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsrl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsrl_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vmv.v.x v28, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v28, v28, a1
+; CHECK-NEXT:    vmv.v.x v8, a0
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vsrl.vx v8, v8, a1
+; CHECK-NEXT:    vor.vv v28, v8, v28
+; CHECK-NEXT:    vsrl.vv v16, v16, v28
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsrl_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsrl_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsrl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsrl_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a2, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vmv.v.x v8, a1
+; CHECK-NEXT:    addi a1, zero, 32
+; CHECK-NEXT:    vsll.vx v8, v8, a1
+; CHECK-NEXT:    vmv.v.x v24, a0
+; CHECK-NEXT:    vsll.vx v24, v24, a1
+; CHECK-NEXT:    vsrl.vx v24, v24, a1
+; CHECK-NEXT:    vor.vv v8, v24, v8
+; CHECK-NEXT:    vsrl.vv v16, v16, v8
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsrl_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsrl_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
new file mode 100644
index 0000000000000..d1aa31746f8b4
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll
@@ -0,0 +1,817 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i8> @vsrl_vx_nxv1i8(<vscale x 1 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv1i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsrl_vx_nxv1i8_0(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 1 x i8> @vsrl_vx_nxv1i8_1(<vscale x 1 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i8> %va, %splat
+  ret <vscale x 1 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsrl_vx_nxv2i8(<vscale x 2 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv2i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsrl_vx_nxv2i8_0(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 2 x i8> @vsrl_vx_nxv2i8_1(<vscale x 2 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i8> %va, %splat
+  ret <vscale x 2 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsrl_vx_nxv4i8(<vscale x 4 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv4i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsrl_vx_nxv4i8_0(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 4 x i8> @vsrl_vx_nxv4i8_1(<vscale x 4 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i8> %va, %splat
+  ret <vscale x 4 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsrl_vx_nxv8i8(<vscale x 8 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv8i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsrl_vx_nxv8i8_0(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @vsrl_vx_nxv8i8_1(<vscale x 8 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsrl_vx_nxv16i8(<vscale x 16 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv16i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsrl_vx_nxv16i8_0(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 16 x i8> @vsrl_vx_nxv16i8_1(<vscale x 16 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i8> %va, %splat
+  ret <vscale x 16 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsrl_vx_nxv32i8(<vscale x 32 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv32i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsrl_vx_nxv32i8_0(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv32i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 32 x i8> @vsrl_vx_nxv32i8_1(<vscale x 32 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv32i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i8> %va, %splat
+  ret <vscale x 32 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsrl_vx_nxv64i8(<vscale x 64 x i8> %va, i8 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv64i8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = lshr <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsrl_vx_nxv64i8_0(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv64i8_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 31, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = lshr <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 64 x i8> @vsrl_vx_nxv64i8_1(<vscale x 64 x i8> %va) {
+; CHECK-LABEL: vsrl_vx_nxv64i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 64 x i8> undef, i8 32, i32 0
+  %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
+  %vc = lshr <vscale x 64 x i8> %va, %splat
+  ret <vscale x 64 x i8> %vc
+}
+
+define <vscale x 1 x i16> @vsrl_vx_nxv1i16(<vscale x 1 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv1i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsrl_vx_nxv1i16_0(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 1 x i16> @vsrl_vx_nxv1i16_1(<vscale x 1 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i16> %va, %splat
+  ret <vscale x 1 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsrl_vx_nxv2i16(<vscale x 2 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv2i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsrl_vx_nxv2i16_0(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 2 x i16> @vsrl_vx_nxv2i16_1(<vscale x 2 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i16> %va, %splat
+  ret <vscale x 2 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsrl_vx_nxv4i16(<vscale x 4 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv4i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsrl_vx_nxv4i16_0(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 4 x i16> @vsrl_vx_nxv4i16_1(<vscale x 4 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i16> %va, %splat
+  ret <vscale x 4 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsrl_vx_nxv8i16(<vscale x 8 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv8i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsrl_vx_nxv8i16_0(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 8 x i16> @vsrl_vx_nxv8i16_1(<vscale x 8 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i16> %va, %splat
+  ret <vscale x 8 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsrl_vx_nxv16i16(<vscale x 16 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv16i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsrl_vx_nxv16i16_0(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 16 x i16> @vsrl_vx_nxv16i16_1(<vscale x 16 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i16> %va, %splat
+  ret <vscale x 16 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsrl_vx_nxv32i16(<vscale x 32 x i16> %va, i16 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv32i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 %b, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsrl_vx_nxv32i16_0(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 31, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 32 x i16> @vsrl_vx_nxv32i16_1(<vscale x 32 x i16> %va) {
+; CHECK-LABEL: vsrl_vx_nxv32i16_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e16,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 32 x i16> undef, i16 32, i32 0
+  %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
+  %vc = lshr <vscale x 32 x i16> %va, %splat
+  ret <vscale x 32 x i16> %vc
+}
+
+define <vscale x 1 x i32> @vsrl_vx_nxv1i32(<vscale x 1 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsrl_vx_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 1 x i32> @vsrl_vx_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i32> %va, %splat
+  ret <vscale x 1 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsrl_vx_nxv2i32(<vscale x 2 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsrl_vx_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 2 x i32> @vsrl_vx_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i32> %va, %splat
+  ret <vscale x 2 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsrl_vx_nxv4i32(<vscale x 4 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsrl_vx_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 4 x i32> @vsrl_vx_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i32> %va, %splat
+  ret <vscale x 4 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vx_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vx_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vx_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %splat
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsrl_vx_nxv16i32(<vscale x 16 x i32> %va, i32 signext %b) {
+; CHECK-LABEL: vsrl_vx_nxv16i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 %b, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsrl_vx_nxv16i32_0(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 31, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 16 x i32> @vsrl_vx_nxv16i32_1(<vscale x 16 x i32> %va) {
+; CHECK-LABEL: vsrl_vx_nxv16i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i32> undef, i32 32, i32 0
+  %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
+  %vc = lshr <vscale x 16 x i32> %va, %splat
+  ret <vscale x 16 x i32> %vc
+}
+
+define <vscale x 1 x i64> @vsrl_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsrl_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsrl_vx_nxv1i64_0(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 1 x i64> @vsrl_vx_nxv1i64_1(<vscale x 1 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv1i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vc = lshr <vscale x 1 x i64> %va, %splat
+  ret <vscale x 1 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsrl_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsrl_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsrl_vx_nxv2i64_0(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 2 x i64> @vsrl_vx_nxv2i64_1(<vscale x 2 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv2i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m2,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vc = lshr <vscale x 2 x i64> %va, %splat
+  ret <vscale x 2 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsrl_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsrl_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsrl_vx_nxv4i64_0(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 4 x i64> @vsrl_vx_nxv4i64_1(<vscale x 4 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv4i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m4,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vc = lshr <vscale x 4 x i64> %va, %splat
+  ret <vscale x 4 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsrl_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
+; CHECK-LABEL: vsrl_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsrl_vx_nxv8i64_0(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i64_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsrl.vi v16, v16, 31
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 31, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
+define <vscale x 8 x i64> @vsrl_vx_nxv8i64_1(<vscale x 8 x i64> %va) {
+; CHECK-LABEL: vsrl_vx_nxv8i64_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 32
+; CHECK-NEXT:    vsetvli a1, zero, e64,m8,ta,mu
+; CHECK-NEXT:    vsrl.vx v16, v16, a0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i64> %va, %splat
+  ret <vscale x 8 x i64> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
new file mode 100644
index 0000000000000..539177f8d78e2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv32.ll
@@ -0,0 +1,1034 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmacc_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmacc_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmacc_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmacc_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmacc_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmacc_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmacc_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmacc_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmacc_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmacc_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmacc_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmacc_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmacc_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmacc_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmacc_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmacc_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmacc_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmacc_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmacc_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmacc_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmacc_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmacc_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
new file mode 100644
index 0000000000000..a6ed911b77365
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmacc-rv64.ll
@@ -0,0 +1,1412 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmacc_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmacc_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmacc_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmacc_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmacc_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmacc_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmacc_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmacc_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmacc_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmacc_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmacc_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmacc_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv1i64_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv1i64_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmacc_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv2i64_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv2i64_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmacc_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv4i64_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv4i64_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmacc_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vv_nxv8i64_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vv_nxv8i64_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmacc_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmacc.mask.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmacc_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmacc.mask.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmacc_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmacc.mask.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmacc_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmacc.mask.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmacc_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmacc.mask.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmacc_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmacc.mask.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmacc_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmacc.mask.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmacc_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmacc.mask.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmacc_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmacc.mask.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmacc_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmacc.mask.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmacc_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmacc.mask.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.i32(
+  <vscale x 1 x i64>,
+  i32,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmacc_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv1i64_i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.nxv1i64.i32(
+    <vscale x 1 x i64> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32(
+  <vscale x 1 x i64>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv1i64_i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmacc.mask.nxv1i64.i32(
+    <vscale x 1 x i64> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.i32(
+  <vscale x 2 x i64>,
+  i32,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmacc_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv2i64_i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.nxv2i64.i32(
+    <vscale x 2 x i64> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32(
+  <vscale x 2 x i64>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv2i64_i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmacc.mask.nxv2i64.i32(
+    <vscale x 2 x i64> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.i32(
+  <vscale x 4 x i64>,
+  i32,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmacc_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv4i64_i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.nxv4i64.i32(
+    <vscale x 4 x i64> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32(
+  <vscale x 4 x i64>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv4i64_i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmacc.mask.nxv4i64.i32(
+    <vscale x 4 x i64> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.i32(
+  <vscale x 8 x i64>,
+  i32,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmacc_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_vx_nxv8i64_i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.nxv8i64.i32(
+    <vscale x 8 x i64> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32(
+  <vscale x 8 x i64>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmacc_mask_vx_nxv8i64_i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmacc.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmacc.mask.nxv8i64.i32(
+    <vscale x 8 x i64> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
new file mode 100644
index 0000000000000..2d39ba95db2ef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv32.ll
@@ -0,0 +1,1034 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccsu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccsu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccsu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccsu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccsu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccsu_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccsu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccsu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccsu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccsu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccsu_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccsu_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccsu_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccsu_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccsu_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccsu_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccsu_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccsu_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccsu_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccsu_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccsu_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccsu_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
new file mode 100644
index 0000000000000..c274246b7b530
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccsu-rv64.ll
@@ -0,0 +1,1412 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccsu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccsu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccsu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccsu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccsu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccsu_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccsu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccsu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccsu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccsu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccsu_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmaccsu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv1i64_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv1i64_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmaccsu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv2i64_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv2i64_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmaccsu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv4i64_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv4i64_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmaccsu_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vv_nxv8i64_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vv_nxv8i64_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccsu_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccsu.mask.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccsu_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccsu.mask.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccsu_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccsu.mask.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccsu_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccsu.mask.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccsu_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccsu.mask.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccsu_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccsu.mask.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccsu_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccsu.mask.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccsu_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccsu.mask.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccsu_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccsu.mask.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccsu_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccsu.mask.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccsu_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccsu.mask.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.i32(
+  <vscale x 1 x i64>,
+  i32,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmaccsu_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv1i64_i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.nxv1i64.i32(
+    <vscale x 1 x i64> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32(
+  <vscale x 1 x i64>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv1i64_i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccsu.mask.nxv1i64.i32(
+    <vscale x 1 x i64> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.i32(
+  <vscale x 2 x i64>,
+  i32,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmaccsu_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv2i64_i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.nxv2i64.i32(
+    <vscale x 2 x i64> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32(
+  <vscale x 2 x i64>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv2i64_i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccsu.mask.nxv2i64.i32(
+    <vscale x 2 x i64> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.i32(
+  <vscale x 4 x i64>,
+  i32,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmaccsu_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv4i64_i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.nxv4i64.i32(
+    <vscale x 4 x i64> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32(
+  <vscale x 4 x i64>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv4i64_i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccsu.mask.nxv4i64.i32(
+    <vscale x 4 x i64> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.i32(
+  <vscale x 8 x i64>,
+  i32,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmaccsu_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_vx_nxv8i64_i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.nxv8i64.i32(
+    <vscale x 8 x i64> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32(
+  <vscale x 8 x i64>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccsu_mask_vx_nxv8i64_i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccsu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccsu.mask.nxv8i64.i32(
+    <vscale x 8 x i64> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
new file mode 100644
index 0000000000000..2bc594e82d6b5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv32.ll
@@ -0,0 +1,1034 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccu_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccu_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccu_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccu_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccu_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccu_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccu_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccu_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccu_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
new file mode 100644
index 0000000000000..be5d1779a22c9
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccu-rv64.ll
@@ -0,0 +1,1412 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8(<vscale x 1 x i16> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i16_nxv1i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.nxv1i8(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccu_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8(<vscale x 2 x i16> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i16_nxv2i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.nxv2i8(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccu_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i16_nxv4i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.nxv4i8(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccu_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8(<vscale x 8 x i16> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i16_nxv8i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.nxv8i8(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccu_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8(<vscale x 16 x i16> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i16_nxv16i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.nxv16i8(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8(<vscale x 32 x i16> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv32i16_nxv32i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.nxv32i8(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccu_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i32_nxv1i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.nxv1i16(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccu_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i32_nxv2i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.nxv2i16(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccu_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16(<vscale x 4 x i32> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i32_nxv4i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.nxv4i16(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccu_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16(<vscale x 8 x i32> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i32_nxv8i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.nxv8i16(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16(<vscale x 16 x i32> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv16i32_nxv16i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vle16.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.nxv16i16(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmaccu_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv1i64_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv1i64_nxv1i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v17, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmaccu_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv2i64_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32(<vscale x 2 x i64> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv2i64_nxv2i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v18, v19, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.nxv2i32(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmaccu_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv4i64_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32(<vscale x 4 x i64> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv4i64_nxv4i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a0, a0, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v20, v22, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.nxv4i32(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmaccu_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vv_nxv8i64_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32(<vscale x 8 x i64> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vv_nxv8i64_nxv8i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetvli a0, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vv v16, v8, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.nxv8i32(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccu_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccu.mask.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccu_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccu.mask.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccu_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccu.mask.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccu_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccu.mask.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccu_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccu.mask.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccu.mask.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccu_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccu.mask.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccu_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccu.mask.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccu_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccu.mask.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccu_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccu.mask.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccu.mask.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.i32(
+  <vscale x 1 x i64>,
+  i32,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmaccu_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv1i64_i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.nxv1i64.i32(
+    <vscale x 1 x i64> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32(
+  <vscale x 1 x i64>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv1i64_i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccu.mask.nxv1i64.i32(
+    <vscale x 1 x i64> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.i32(
+  <vscale x 2 x i64>,
+  i32,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmaccu_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv2i64_i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.nxv2i64.i32(
+    <vscale x 2 x i64> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32(
+  <vscale x 2 x i64>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv2i64_i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccu.mask.nxv2i64.i32(
+    <vscale x 2 x i64> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.i32(
+  <vscale x 4 x i64>,
+  i32,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmaccu_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv4i64_i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.nxv4i64.i32(
+    <vscale x 4 x i64> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32(
+  <vscale x 4 x i64>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv4i64_i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccu.mask.nxv4i64.i32(
+    <vscale x 4 x i64> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.i32(
+  <vscale x 8 x i64>,
+  i32,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmaccu_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_vx_nxv8i64_i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.nxv8i64.i32(
+    <vscale x 8 x i64> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32(
+  <vscale x 8 x i64>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccu_mask_vx_nxv8i64_i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccu.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccu.mask.nxv8i64.i32(
+    <vscale x 8 x i64> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
new file mode 100644
index 0000000000000..b9e0207f381ab
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv32.ll
@@ -0,0 +1,516 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccus_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccus_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccus_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccus_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccus_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccus_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccus_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccus_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, i32 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll
new file mode 100644
index 0000000000000..56964b8819d7b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vwmaccus-rv64.ll
@@ -0,0 +1,704 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i16>  @intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8(
+  <vscale x 1 x i16>,
+  i8,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8(<vscale x 1 x i16> %0, i8 %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i16_i8_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf8,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i16> @llvm.riscv.vwmaccus.mask.nxv1i16.i8(
+    <vscale x 1 x i16> %0,
+    i8 %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i16>  @intrinsic_vwmaccus_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8(
+  <vscale x 2 x i16>,
+  i8,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8(<vscale x 2 x i16> %0, i8 %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i16_i8_nxv2i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i16> @llvm.riscv.vwmaccus.mask.nxv2i16.i8(
+    <vscale x 2 x i16> %0,
+    i8 %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i16>  @intrinsic_vwmaccus_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8(
+  <vscale x 4 x i16>,
+  i8,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8(<vscale x 4 x i16> %0, i8 %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i16_i8_nxv4i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i16> @llvm.riscv.vwmaccus.mask.nxv4i16.i8(
+    <vscale x 4 x i16> %0,
+    i8 %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i16>  @intrinsic_vwmaccus_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8(
+  <vscale x 8 x i16>,
+  i8,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8(<vscale x 8 x i16> %0, i8 %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i16_i8_nxv8i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i16> @llvm.riscv.vwmaccus.mask.nxv8i16.i8(
+    <vscale x 8 x i16> %0,
+    i8 %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i16>  @intrinsic_vwmaccus_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8(
+  <vscale x 16 x i16>,
+  i8,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8(<vscale x 16 x i16> %0, i8 %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i16_i8_nxv16i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i16> @llvm.riscv.vwmaccus.mask.nxv16i16.i8(
+    <vscale x 16 x i16> %0,
+    i8 %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i16>  @intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8(
+  <vscale x 32 x i16>,
+  i8,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8(<vscale x 32 x i16> %0, i8 %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv32i16_i8_nxv32i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e8,m4,ta,mu
+; CHECK-NEXT:    vle8.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e8,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 32 x i16> @llvm.riscv.vwmaccus.mask.nxv32i16.i8(
+    <vscale x 32 x i16> %0,
+    i8 %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i32>  @intrinsic_vwmaccus_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16(
+  <vscale x 1 x i32>,
+  i16,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16(<vscale x 1 x i32> %0, i16 %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i32_i16_nxv1i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i32> @llvm.riscv.vwmaccus.mask.nxv1i32.i16(
+    <vscale x 1 x i32> %0,
+    i16 %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i32>  @intrinsic_vwmaccus_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16(
+  <vscale x 2 x i32>,
+  i16,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16(<vscale x 2 x i32> %0, i16 %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i32_i16_nxv2i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i32> @llvm.riscv.vwmaccus.mask.nxv2i32.i16(
+    <vscale x 2 x i32> %0,
+    i16 %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i32>  @intrinsic_vwmaccus_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16(
+  <vscale x 4 x i32>,
+  i16,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16(<vscale x 4 x i32> %0, i16 %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i32_i16_nxv4i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i32> @llvm.riscv.vwmaccus.mask.nxv4i32.i16(
+    <vscale x 4 x i32> %0,
+    i16 %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i32>  @intrinsic_vwmaccus_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16(
+  <vscale x 8 x i32>,
+  i16,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16(<vscale x 8 x i32> %0, i16 %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i32_i16_nxv8i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e16,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i32> @llvm.riscv.vwmaccus.mask.nxv8i32.i16(
+    <vscale x 8 x i32> %0,
+    i16 %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i32>  @intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16(
+  <vscale x 16 x i32>,
+  i16,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16(<vscale x 16 x i32> %0, i16 %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv16i32_i16_nxv16i16:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e16,m4,ta,mu
+; CHECK-NEXT:    vle16.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e16,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 16 x i32> @llvm.riscv.vwmaccus.mask.nxv16i32.i16(
+    <vscale x 16 x i32> %0,
+    i16 %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.nxv1i64.i32(
+  <vscale x 1 x i64>,
+  i32,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i64>  @intrinsic_vwmaccus_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv1i64_i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.nxv1i64.i32(
+    <vscale x 1 x i64> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32(
+  <vscale x 1 x i64>,
+  i32,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32(<vscale x 1 x i64> %0, i32 %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv1i64_i32_nxv1i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,mf2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v17, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 1 x i64> @llvm.riscv.vwmaccus.mask.nxv1i64.i32(
+    <vscale x 1 x i64> %0,
+    i32 %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.nxv2i64.i32(
+  <vscale x 2 x i64>,
+  i32,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i64>  @intrinsic_vwmaccus_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv2i64_i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.nxv2i64.i32(
+    <vscale x 2 x i64> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32(
+  <vscale x 2 x i64>,
+  i32,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32(<vscale x 2 x i64> %0, i32 %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv2i64_i32_nxv2i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m1,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v18, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 2 x i64> @llvm.riscv.vwmaccus.mask.nxv2i64.i32(
+    <vscale x 2 x i64> %0,
+    i32 %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.nxv4i64.i32(
+  <vscale x 4 x i64>,
+  i32,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i64>  @intrinsic_vwmaccus_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv4i64_i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.nxv4i64.i32(
+    <vscale x 4 x i64> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32(
+  <vscale x 4 x i64>,
+  i32,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32(<vscale x 4 x i64> %0, i32 %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv4i64_i32_nxv4i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a1, a1, e32,m2,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v20, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 4 x i64> @llvm.riscv.vwmaccus.mask.nxv4i64.i32(
+    <vscale x 4 x i64> %0,
+    i32 %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.nxv8i64.i32(
+  <vscale x 8 x i64>,
+  i32,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i64>  @intrinsic_vwmaccus_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, i64 %3) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_vx_nxv8i64_i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.nxv8i64.i32(
+    <vscale x 8 x i64> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32(
+  <vscale x 8 x i64>,
+  i32,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32(<vscale x 8 x i64> %0, i32 %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+; CHECK-LABEL: intrinsic_vwmaccus_mask_vx_nxv8i64_i32_nxv8i32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,ta,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, a2, e32,m4,ta,mu
+; CHECK-NEXT:    vwmaccus.vx v16, a0, v28, v0.t
+; CHECK-NEXT:    jalr zero, 0(ra)
+entry:
+  %a = call <vscale x 8 x i64> @llvm.riscv.vwmaccus.mask.nxv8i64.i32(
+    <vscale x 8 x i64> %0,
+    i32 %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
new file mode 100644
index 0000000000000..ee631bd6623bc
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
@@ -0,0 +1,1945 @@
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i8> %2,
+    <vscale x 64 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vxor_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i8> @intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vxor_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i8> @intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vxor_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i8> @intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vxor_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i8> @intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vxor_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i8> @intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vxor_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i8> @intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vxor_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i32 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i32);
+
+define <vscale x 64 x i8> @intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vxor_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i16> @intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vxor_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i16> @intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vxor_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i16> @intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vxor_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i16> @intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vxor_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i16> @intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vxor_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i32 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i32);
+
+define <vscale x 32 x i16> @intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vxor_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i32);
+
+define <vscale x 1 x i32> @intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vxor_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i32);
+
+define <vscale x 2 x i32> @intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vxor_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i32);
+
+define <vscale x 4 x i32> @intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vxor_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i32);
+
+define <vscale x 8 x i32> @intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vxor_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i32 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i32);
+
+define <vscale x 16 x i32> @intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i32 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vxor_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vxor_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vxor_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vxor_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vxor_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vxor_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vxor_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    i32 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 9,
+    <vscale x 64 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vxor_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vxor_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vxor_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vxor_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vxor_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vxor_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    i32 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vxor_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vxor_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vxor_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vxor_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vxor_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    i32 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i32 %3)
+
+  ret <vscale x 16 x i32> %a
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll
new file mode 100644
index 0000000000000..5395e42429d0b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-rv64.ll
@@ -0,0 +1,2377 @@
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d -verify-machineinstrs \
+; RUN:   --riscv-no-aliases < %s | FileCheck %s
+declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i8_nxv1i8_nxv1i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    <vscale x 1 x i8> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.nxv2i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i8_nxv2i8_nxv2i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.nxv2i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    <vscale x 2 x i8> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.nxv4i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i8_nxv4i8_nxv4i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.nxv4i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    <vscale x 4 x i8> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.nxv8i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i8_nxv8i8_nxv8i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.nxv8i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    <vscale x 8 x i8> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.nxv16i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i8_nxv16i8_nxv16i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.nxv16i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    <vscale x 16 x i8> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.nxv32i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i8_nxv32i8_nxv32i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.nxv32i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    <vscale x 32 x i8> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv64i8_nxv64i8_nxv64i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.nxv64i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    <vscale x 64 x i8> %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.nxv1i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i16_nxv1i16_nxv1i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.nxv1i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    <vscale x 1 x i16> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.nxv2i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i16_nxv2i16_nxv2i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.nxv2i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    <vscale x 2 x i16> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.nxv4i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i16_nxv4i16_nxv4i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.nxv4i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    <vscale x 4 x i16> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.nxv8i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i16_nxv8i16_nxv8i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.nxv8i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    <vscale x 8 x i16> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.nxv16i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i16_nxv16i16_nxv16i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.nxv16i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    <vscale x 16 x i16> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv32i16_nxv32i16_nxv32i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.nxv32i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    <vscale x 32 x i16> %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i32_nxv1i32_nxv1i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.nxv1i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    <vscale x 1 x i32> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.nxv2i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i32_nxv2i32_nxv2i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.nxv2i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    <vscale x 2 x i32> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.nxv4i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i32_nxv4i32_nxv4i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.nxv4i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    <vscale x 4 x i32> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.nxv8i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i32_nxv8i32_nxv8i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.nxv8i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    <vscale x 8 x i32> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv16i32_nxv16i32_nxv16i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.nxv16i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    <vscale x 16 x i32> %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vxor_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.nxv1i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vxor_mask_vv_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv1i64_nxv1i64_nxv1i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.nxv1i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    <vscale x 1 x i64> %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vxor_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.nxv2i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vxor_mask_vv_nxv2i64_nxv2i64_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv2i64_nxv2i64_nxv2i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.nxv2i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    <vscale x 2 x i64> %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vxor_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.nxv4i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vxor_mask_vv_nxv4i64_nxv4i64_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv4i64_nxv4i64_nxv4i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.nxv4i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    <vscale x 4 x i64> %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vxor_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vv_nxv8i64_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.nxv8i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vv_nxv8i64_nxv8i64_nxv8i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vxor.vv {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.nxv8i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    <vscale x 8 x i64> %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  i8,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vxor_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i8>,
+  i8,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i8> @intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  i8,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vxor_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(
+  <vscale x 2 x i8>,
+  <vscale x 2 x i8>,
+  i8,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i8> @intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  i8,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vxor_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(
+  <vscale x 4 x i8>,
+  <vscale x 4 x i8>,
+  i8,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i8> @intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  i8,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vxor_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(
+  <vscale x 8 x i8>,
+  <vscale x 8 x i8>,
+  i8,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i8> @intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  i8,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vxor_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(
+  <vscale x 16 x i8>,
+  <vscale x 16 x i8>,
+  i8,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i8> @intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  i8,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vxor_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(
+  <vscale x 32 x i8>,
+  <vscale x 32 x i8>,
+  i8,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i8> @intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  i8,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vxor_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 %1,
+    i64 %2)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(
+  <vscale x 64 x i8>,
+  <vscale x 64 x i8>,
+  i8,
+  <vscale x 64 x i1>,
+  i64);
+
+define <vscale x 64 x i8> @intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, i8 %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 %2,
+    <vscale x 64 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 64 x i8> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  i16,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vxor_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(
+  <vscale x 1 x i16>,
+  <vscale x 1 x i16>,
+  i16,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i16> @intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  i16,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vxor_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(
+  <vscale x 2 x i16>,
+  <vscale x 2 x i16>,
+  i16,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i16> @intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  i16,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vxor_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(
+  <vscale x 4 x i16>,
+  <vscale x 4 x i16>,
+  i16,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i16> @intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  i16,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vxor_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(
+  <vscale x 8 x i16>,
+  <vscale x 8 x i16>,
+  i16,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i16> @intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  i16,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vxor_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(
+  <vscale x 16 x i16>,
+  <vscale x 16 x i16>,
+  i16,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i16> @intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  i16,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vxor_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 %1,
+    i64 %2)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(
+  <vscale x 32 x i16>,
+  <vscale x 32 x i16>,
+  i16,
+  <vscale x 32 x i1>,
+  i64);
+
+define <vscale x 32 x i16> @intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, i16 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 %2,
+    <vscale x 32 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 32 x i16> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  i32,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vxor_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(
+  <vscale x 1 x i32>,
+  <vscale x 1 x i32>,
+  i32,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i32> @intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  i32,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vxor_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(
+  <vscale x 2 x i32>,
+  <vscale x 2 x i32>,
+  i32,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i32> @intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  i32,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vxor_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(
+  <vscale x 4 x i32>,
+  <vscale x 4 x i32>,
+  i32,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i32> @intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  i32,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vxor_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(
+  <vscale x 8 x i32>,
+  <vscale x 8 x i32>,
+  i32,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i32> @intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  i32,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vxor_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 %1,
+    i64 %2)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(
+  <vscale x 16 x i32>,
+  <vscale x 16 x i32>,
+  i32,
+  <vscale x 16 x i1>,
+  i64);
+
+define <vscale x 16 x i32> @intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, i32 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 %2,
+    <vscale x 16 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 16 x i32> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  i64,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vxor_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.i64(
+  <vscale x 1 x i64>,
+  <vscale x 1 x i64>,
+  i64,
+  <vscale x 1 x i1>,
+  i64);
+
+define <vscale x 1 x i64> @intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 %2,
+    <vscale x 1 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 1 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  i64,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vxor_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.i64(
+  <vscale x 2 x i64>,
+  <vscale x 2 x i64>,
+  i64,
+  <vscale x 2 x i1>,
+  i64);
+
+define <vscale x 2 x i64> @intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 %2,
+    <vscale x 2 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 2 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  i64,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vxor_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.i64(
+  <vscale x 4 x i64>,
+  <vscale x 4 x i64>,
+  i64,
+  <vscale x 4 x i1>,
+  i64);
+
+define <vscale x 4 x i64> @intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 %2,
+    <vscale x 4 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 4 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  i64,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vxor_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vx_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 %1,
+    i64 %2)
+
+  ret <vscale x 8 x i64> %a
+}
+
+declare <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.i64(
+  <vscale x 8 x i64>,
+  <vscale x 8 x i64>,
+  i64,
+  <vscale x 8 x i1>,
+  i64);
+
+define <vscale x 8 x i64> @intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, i64 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vx_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vxor.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 %2,
+    <vscale x 8 x i1> %3,
+    i64 %4)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vxor_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 1 x i8> @intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i8_nxv1i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i8> @llvm.riscv.vxor.mask.nxv1i8.i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i8> %1,
+    i8 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vxor_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 2 x i8> @intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i8_nxv2i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i8> @llvm.riscv.vxor.mask.nxv2i8.i8(
+    <vscale x 2 x i8> %0,
+    <vscale x 2 x i8> %1,
+    i8 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vxor_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 4 x i8> @intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i8_nxv4i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i8> @llvm.riscv.vxor.mask.nxv4i8.i8(
+    <vscale x 4 x i8> %0,
+    <vscale x 4 x i8> %1,
+    i8 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vxor_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 8 x i8> @intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i8_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i8> @llvm.riscv.vxor.mask.nxv8i8.i8(
+    <vscale x 8 x i8> %0,
+    <vscale x 8 x i8> %1,
+    i8 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vxor_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 16 x i8> @intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i8_nxv16i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i8> @llvm.riscv.vxor.mask.nxv16i8.i8(
+    <vscale x 16 x i8> %0,
+    <vscale x 16 x i8> %1,
+    i8 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vxor_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 32 x i8> @intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i8_nxv32i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i8> @llvm.riscv.vxor.mask.nxv32i8.i8(
+    <vscale x 32 x i8> %0,
+    <vscale x 32 x i8> %1,
+    i8 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vxor_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    i8 9,
+    i64 %1)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 64 x i8> @intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv64i8_nxv64i8_i8
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e8,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 64 x i8> @llvm.riscv.vxor.mask.nxv64i8.i8(
+    <vscale x 64 x i8> %0,
+    <vscale x 64 x i8> %1,
+    i8 9,
+    <vscale x 64 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 64 x i8> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vxor_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 1 x i16> @intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i16_nxv1i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i16> @llvm.riscv.vxor.mask.nxv1i16.i16(
+    <vscale x 1 x i16> %0,
+    <vscale x 1 x i16> %1,
+    i16 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vxor_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 2 x i16> @intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i16_nxv2i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i16> @llvm.riscv.vxor.mask.nxv2i16.i16(
+    <vscale x 2 x i16> %0,
+    <vscale x 2 x i16> %1,
+    i16 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vxor_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 4 x i16> @intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i16_nxv4i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i16> @llvm.riscv.vxor.mask.nxv4i16.i16(
+    <vscale x 4 x i16> %0,
+    <vscale x 4 x i16> %1,
+    i16 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vxor_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 8 x i16> @intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i16_nxv8i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i16> @llvm.riscv.vxor.mask.nxv8i16.i16(
+    <vscale x 8 x i16> %0,
+    <vscale x 8 x i16> %1,
+    i16 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vxor_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 16 x i16> @intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i16_nxv16i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i16> @llvm.riscv.vxor.mask.nxv16i16.i16(
+    <vscale x 16 x i16> %0,
+    <vscale x 16 x i16> %1,
+    i16 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vxor_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    i16 9,
+    i64 %1)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 32 x i16> @intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv32i16_nxv32i16_i16
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e16,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 32 x i16> @llvm.riscv.vxor.mask.nxv32i16.i16(
+    <vscale x 32 x i16> %0,
+    <vscale x 32 x i16> %1,
+    i16 9,
+    <vscale x 32 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 32 x i16> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vxor_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 1 x i32> @intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i32_nxv1i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,mf2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i32> @llvm.riscv.vxor.mask.nxv1i32.i32(
+    <vscale x 1 x i32> %0,
+    <vscale x 1 x i32> %1,
+    i32 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vxor_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 2 x i32> @intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i32_nxv2i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i32> @llvm.riscv.vxor.mask.nxv2i32.i32(
+    <vscale x 2 x i32> %0,
+    <vscale x 2 x i32> %1,
+    i32 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vxor_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 4 x i32> @intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i32_nxv4i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i32> @llvm.riscv.vxor.mask.nxv4i32.i32(
+    <vscale x 4 x i32> %0,
+    <vscale x 4 x i32> %1,
+    i32 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vxor_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 8 x i32> @intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i32_nxv8i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i32> @llvm.riscv.vxor.mask.nxv8i32.i32(
+    <vscale x 8 x i32> %0,
+    <vscale x 8 x i32> %1,
+    i32 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vxor_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    i32 9,
+    i64 %1)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 16 x i32> @intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv16i32_nxv16i32_i32
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e32,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 16 x i32> @llvm.riscv.vxor.mask.nxv16i32.i32(
+    <vscale x 16 x i32> %0,
+    <vscale x 16 x i32> %1,
+    i32 9,
+    <vscale x 16 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 16 x i32> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vxor_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 1 x i64> @intrinsic_vxor_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv1i64_nxv1i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 1 x i64> @llvm.riscv.vxor.mask.nxv1i64.i64(
+    <vscale x 1 x i64> %0,
+    <vscale x 1 x i64> %1,
+    i64 9,
+    <vscale x 1 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 1 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vxor_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 2 x i64> @intrinsic_vxor_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv2i64_nxv2i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 2 x i64> @llvm.riscv.vxor.mask.nxv2i64.i64(
+    <vscale x 2 x i64> %0,
+    <vscale x 2 x i64> %1,
+    i64 9,
+    <vscale x 2 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 2 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vxor_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 4 x i64> @intrinsic_vxor_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv4i64_nxv4i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 4 x i64> @llvm.riscv.vxor.mask.nxv4i64.i64(
+    <vscale x 4 x i64> %0,
+    <vscale x 4 x i64> %1,
+    i64 9,
+    <vscale x 4 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 4 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vxor_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_vi_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9
+  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    i64 9,
+    i64 %1)
+
+  ret <vscale x 8 x i64> %a
+}
+
+define <vscale x 8 x i64> @intrinsic_vxor_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
+entry:
+; CHECK-LABEL: intrinsic_vxor_mask_vi_nxv8i64_nxv8i64_i64
+; CHECK:       vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
+; CHECK:       vxor.vi {{v[0-9]+}}, {{v[0-9]+}}, 9, v0.t
+  %a = call <vscale x 8 x i64> @llvm.riscv.vxor.mask.nxv8i64.i64(
+    <vscale x 8 x i64> %0,
+    <vscale x 8 x i64> %1,
+    i64 9,
+    <vscale x 8 x i1> %2,
+    i64 %3)
+
+  ret <vscale x 8 x i64> %a
+}
diff --git a/llvm/test/CodeGen/SPARC/missinglabel.ll b/llvm/test/CodeGen/SPARC/missinglabel.ll
index 60a3641ccea0f..792af8eec3bdf 100644
--- a/llvm/test/CodeGen/SPARC/missinglabel.ll
+++ b/llvm/test/CodeGen/SPARC/missinglabel.ll
@@ -13,13 +13,13 @@ define void @f(i64 %a0) align 2 {
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    ba .LBB0_1
 ; CHECK-NEXT:    nop
+; CHECK-NEXT:  .LBB0_1: ! %cond.false
 ; CHECK-NEXT:  .LBB0_2: ! %targetblock
 ; CHECK-NEXT:    mov %g0, %o0
 ; CHECK-NEXT:    cmp %o0, 0
 ; CHECK-NEXT:    bne .LBB0_4
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:  ! %bb.3: ! %cond.false.i83
-; CHECK-NEXT:  .LBB0_1: ! %cond.false
 ; CHECK-NEXT:  .LBB0_4: ! %exit.i85
 entry:
   %cmp = icmp eq i64 %a0, 0
diff --git a/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir b/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir
index f61ca33007349..37a1bd776fd84 100644
--- a/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir
+++ b/llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir
@@ -4,9 +4,9 @@
 # RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=codegenprepare \
 # RUN:   -stop-after codegenprepare -o - | FileCheck %s
 #
-# CHECK-LABEL: bb2:
+# CHECK-LABEL: bb1:
 # CHECK:       ret
-# CHECK-LABEL: bb4:
+# CHECK-LABEL: bb2:
 # CHECK:       ret
 
 
diff --git a/llvm/test/CodeGen/SystemZ/sext-zext.ll b/llvm/test/CodeGen/SystemZ/sext-zext.ll
index d48e4ba835887..fbe1c44c1e504 100644
--- a/llvm/test/CodeGen/SystemZ/sext-zext.ll
+++ b/llvm/test/CodeGen/SystemZ/sext-zext.ll
@@ -28,6 +28,25 @@ define i32 @sext_of_not_cmp(i32 %x) {
   ret i32 %sext
 }
 
+;; fold (sext (not (setcc a, b, cc))) -> (sext (setcc a, b, !cc))
+;; make sure we don't crash if the not gets replaced in-visit
+define i32 @sext_of_not_fsetccs(double %x) {
+; CHECK-LABEL: sext_of_not_fsetccs:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    ltdbr %f0, %f0
+; CHECK-NEXT:    ipm %r0
+; CHECK-NEXT:    afi %r0, 1879048192
+; CHECK-NEXT:    srl %r0, 31
+; CHECK-NEXT:    lcr %r2, %r0
+; CHECK-NEXT:    br %r14
+  %cmp = call i1 @llvm.experimental.constrained.fcmp.f64(double %x, double 0.000000e+00, metadata !"oeq", metadata !"fpexcept.ignore")
+  %xor = xor i1 %cmp, 1
+  %sext = sext i1 %xor to i32
+  ret i32 %sext
+}
+
+declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
+
 ;; TODO: fold (add (zext (setcc a, b, cc)), -1) -> (sext (setcc a, b, !cc))
 define i32 @dec_of_zexted_cmp(i32 %x) {
 ; CHECK-LABEL: dec_of_zexted_cmp:
diff --git a/llvm/test/CodeGen/Thumb2/schedm7-hazard.ll b/llvm/test/CodeGen/Thumb2/schedm7-hazard.ll
new file mode 100644
index 0000000000000..9572300d8e228
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/schedm7-hazard.ll
@@ -0,0 +1,38 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CHECK
+; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m7 -arm-data-bank-mask=-1 | FileCheck %s --check-prefix=NOBANK
+
+; This tests the cortex-m7 bank conflict hazard recognizer.
+; Normally both loads would be scheduled early (both in the first cycle) due to
+; their latency. But will bank conflict to TCM so are scheduled in different
+; cycles.
+
+define i32 @test(i32* %x0, i32 %y, i32 %z) {
+; CHECK-LABEL: test:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    ldr r3, [r0]
+; CHECK-NEXT:    subs r1, r3, r1
+; CHECK-NEXT:    ldr r0, [r0, #8]
+; CHECK-NEXT:    subs r1, r1, r2
+; CHECK-NEXT:    adds r1, #1
+; CHECK-NEXT:    muls r0, r1, r0
+; CHECK-NEXT:    bx lr
+; NOBANK-LABEL: test:
+; NOBANK:       @ %bb.0: @ %entry
+; NOBANK-NEXT:    ldr r3, [r0]
+; NOBANK-NEXT:    ldr r0, [r0, #8]
+; NOBANK-NEXT:    subs r1, r3, r1
+; NOBANK-NEXT:    subs r1, r1, r2
+; NOBANK-NEXT:    adds r1, #1
+; NOBANK-NEXT:    muls r0, r1, r0
+; NOBANK-NEXT:    bx lr
+entry:
+  %0 = load i32, i32* %x0, align 4
+  %mul3 = add nsw i32 %0, 1
+  %mul = sub nsw i32 %mul3, %y
+  %sub = sub nsw i32 %mul, %z
+  %arrayidx1 = getelementptr inbounds i32, i32* %x0, i32 2
+  %1 = load i32, i32* %arrayidx1, align 4
+  %mul2 = mul nsw i32 %sub, %1
+  ret i32 %mul2
+}
diff --git a/llvm/test/CodeGen/VE/Scalar/lea-opt.ll b/llvm/test/CodeGen/VE/Scalar/lea-opt.ll
new file mode 100644
index 0000000000000..356b27653f4fe
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/lea-opt.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+; RUN: llc < %s -mtriple=ve -relocation-model=pic \
+; RUN:     | FileCheck %s --check-prefix=PIC
+
+;;; Tests for lea instruction and its optimizations
+
+%struct.buffer = type { i64, [1 x i8] }
+
+@data = internal global i8 0, align 1
+@buf = internal global %struct.buffer zeroinitializer, align 8
+
+; Function Attrs: norecurse nounwind readnone
+define nonnull i8* @lea_basic() {
+; CHECK-LABEL: lea_basic:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, data@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s0, data@hi(, %s0)
+; CHECK-NEXT:    b.l.t (, %s10)
+;
+; PIC-LABEL: lea_basic:
+; PIC:       # %bb.0:
+; PIC-NEXT:    st %s15, 24(, %s11)
+; PIC-NEXT:    st %s16, 32(, %s11)
+; PIC-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
+; PIC-NEXT:    and %s15, %s15, (32)0
+; PIC-NEXT:    sic %s16
+; PIC-NEXT:    lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
+; PIC-NEXT:    lea %s0, data@gotoff_lo
+; PIC-NEXT:    and %s0, %s0, (32)0
+; PIC-NEXT:    lea.sl %s0, data@gotoff_hi(%s0, %s15)
+; PIC-NEXT:    ld %s16, 32(, %s11)
+; PIC-NEXT:    ld %s15, 24(, %s11)
+; PIC-NEXT:    b.l.t (, %s10)
+  ret i8* @data
+}
+
+; Function Attrs: norecurse nounwind readnone
+define i8* @lea_offset() {
+; CHECK-LABEL: lea_offset:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, buf@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s0, buf@hi(8, %s0)
+; CHECK-NEXT:    b.l.t (, %s10)
+;
+; PIC-LABEL: lea_offset:
+; PIC:       # %bb.0:
+; PIC-NEXT:    st %s15, 24(, %s11)
+; PIC-NEXT:    st %s16, 32(, %s11)
+; PIC-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
+; PIC-NEXT:    and %s15, %s15, (32)0
+; PIC-NEXT:    sic %s16
+; PIC-NEXT:    lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
+; PIC-NEXT:    lea %s0, buf@gotoff_lo
+; PIC-NEXT:    and %s0, %s0, (32)0
+; PIC-NEXT:    lea.sl %s0, buf@gotoff_hi(, %s0)
+; PIC-NEXT:    lea %s0, 8(%s0, %s15)
+; PIC-NEXT:    ld %s16, 32(, %s11)
+; PIC-NEXT:    ld %s15, 24(, %s11)
+; PIC-NEXT:    b.l.t (, %s10)
+  ret i8* getelementptr inbounds (%struct.buffer, %struct.buffer* @buf, i64 0, i32 1, i64 0)
+}
diff --git a/llvm/test/CodeGen/VE/Scalar/returnaddr.ll b/llvm/test/CodeGen/VE/Scalar/returnaddr.ll
new file mode 100644
index 0000000000000..ea1b5f687c9da
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/returnaddr.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=ve-- | FileCheck %s
+
+define i8* @h() nounwind readnone optsize {
+; CHECK-LABEL: h:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    st %s9, (, %s11)
+; CHECK-NEXT:    st %s10, 8(, %s11)
+; CHECK-NEXT:    or %s9, 0, %s11
+; CHECK-NEXT:    lea %s11, -176(, %s11)
+; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ld %s61, 24(, %s14)
+; CHECK-NEXT:    or %s62, 0, %s0
+; CHECK-NEXT:    lea %s63, 315
+; CHECK-NEXT:    shm.l %s63, (%s61)
+; CHECK-NEXT:    shm.l %s8, 8(%s61)
+; CHECK-NEXT:    shm.l %s11, 16(%s61)
+; CHECK-NEXT:    monc
+; CHECK-NEXT:    or %s0, 0, %s62
+; CHECK-NEXT:  .LBB0_2: # %entry
+; CHECK-NEXT:    ld %s0, (, %s9)
+; CHECK-NEXT:    ld %s0, (, %s0)
+; CHECK-NEXT:    ld %s0, 8(, %s0)
+; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s10, 8(, %s11)
+; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
+entry:
+  %ret = tail call i8* @llvm.returnaddress(i32 2)
+  ret i8* %ret
+}
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @g() nounwind readnone optsize {
+; CHECK-LABEL: g:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    st %s9, (, %s11)
+; CHECK-NEXT:    st %s10, 8(, %s11)
+; CHECK-NEXT:    or %s9, 0, %s11
+; CHECK-NEXT:    lea %s11, -176(, %s11)
+; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ld %s61, 24(, %s14)
+; CHECK-NEXT:    or %s62, 0, %s0
+; CHECK-NEXT:    lea %s63, 315
+; CHECK-NEXT:    shm.l %s63, (%s61)
+; CHECK-NEXT:    shm.l %s8, 8(%s61)
+; CHECK-NEXT:    shm.l %s11, 16(%s61)
+; CHECK-NEXT:    monc
+; CHECK-NEXT:    or %s0, 0, %s62
+; CHECK-NEXT:  .LBB1_2: # %entry
+; CHECK-NEXT:    ld %s0, (, %s9)
+; CHECK-NEXT:    ld %s0, 8(, %s0)
+; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s10, 8(, %s11)
+; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
+entry:
+  %ret = tail call i8* @llvm.returnaddress(i32 1)
+  ret i8* %ret
+}
+
+define i8* @f() nounwind readnone optsize {
+; CHECK-LABEL: f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    st %s9, (, %s11)
+; CHECK-NEXT:    st %s10, 8(, %s11)
+; CHECK-NEXT:    or %s9, 0, %s11
+; CHECK-NEXT:    lea %s11, -176(, %s11)
+; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB2_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ld %s61, 24(, %s14)
+; CHECK-NEXT:    or %s62, 0, %s0
+; CHECK-NEXT:    lea %s63, 315
+; CHECK-NEXT:    shm.l %s63, (%s61)
+; CHECK-NEXT:    shm.l %s8, 8(%s61)
+; CHECK-NEXT:    shm.l %s11, 16(%s61)
+; CHECK-NEXT:    monc
+; CHECK-NEXT:    or %s0, 0, %s62
+; CHECK-NEXT:  .LBB2_2: # %entry
+; CHECK-NEXT:    ld %s0, 8(, %s9)
+; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s10, 8(, %s11)
+; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
+entry:
+  %ret = tail call i8* @llvm.returnaddress(i32 0)
+  ret i8* %ret
+}
diff --git a/llvm/test/CodeGen/VE/Scalar/stacksave.ll b/llvm/test/CodeGen/VE/Scalar/stacksave.ll
new file mode 100644
index 0000000000000..336f9b83455fd
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Scalar/stacksave.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+; Function Attrs: noinline nounwind optnone
+define i8* @stacksave() {
+; CHECK-LABEL: stacksave:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s0, 0, %s11
+; CHECK-NEXT:    or %s11, 0, %s9
+  %ret = call i8* @llvm.stacksave()
+  ret i8* %ret
+}
+
+; Function Attrs: noinline nounwind optnone
+define void @stackrestore(i8* %ptr) {
+; CHECK-LABEL: stackrestore:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    or %s11, 0, %s0
+; CHECK-NEXT:    or %s11, 0, %s9
+  call void @llvm.stackrestore(i8* %ptr)
+  ret void
+}
+
+; Function Attrs: nounwind
+declare i8* @llvm.stacksave()
+; Function Attrs: nounwind
+declare void @llvm.stackrestore(i8*)
diff --git a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
index c0ad247d0e745..aa7b4944e7e44 100644
--- a/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
+++ b/llvm/test/CodeGen/VE/Vector/fastcc_callee.ll
@@ -137,3 +137,11 @@ define fastcc <512 x i1> @vreg_arg_v512i1_vmp3(<512 x i1> %vmp1, <512 x i1> %vmp
 ; CHECK-NEXT:    b.l.t (, %s10)
   ret <512 x i1> %vmp3
 }
+
+define fastcc <256 x i1> @vmp_cc_bug(<256 x i1> %vm1, <256 x i1> %vm2, <512 x i1> %vmp2, <256 x i1> %vm6) {
+; CHECK-LABEL: vmp_cc_bug:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andm %vm1, %vm0, %vm6
+; CHECK-NEXT:    b.l.t (, %s10)
+  ret <256 x i1> %vm6
+}
diff --git a/llvm/test/CodeGen/VE/Vector/vec_and.ll b/llvm/test/CodeGen/VE/Vector/vec_and.ll
new file mode 100644
index 0000000000000..8597e1aa511ed
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Vector/vec_and.ll
@@ -0,0 +1,132 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+; <256 x i32>
+
+; Function Attrs: nounwind
+define fastcc <256 x i32> @and_vv_v256i32(<256 x i32> %x, <256 x i32> %y) {
+; CHECK-LABEL: and_vv_v256i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvand.lo %v0, %v0, %v1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = and <256 x i32> %x, %y
+  ret <256 x i32> %z
+}
+
+; Function Attrs: nounwind
+define fastcc <256 x i32> @and_sv_v256i32(i32 %x, <256 x i32> %y) {
+; CHECK-LABEL: and_sv_v256i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    pvand.lo %v0, %s0, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %xins = insertelement <256 x i32> undef, i32 %x, i32 0
+  %vx = shufflevector <256 x i32> %xins, <256 x i32> undef, <256 x i32> zeroinitializer
+  %z = and <256 x i32> %vx, %y
+  ret <256 x i32> %z
+}
+
+; Function Attrs: nounwind
+define fastcc <256 x i32> @and_vs_v256i32(<256 x i32> %x, i32 %y) {
+; CHECK-LABEL: and_vs_v256i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    pvand.lo %v0, %s0, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %yins = insertelement <256 x i32> undef, i32 %y, i32 0
+  %vy = shufflevector <256 x i32> %yins, <256 x i32> undef, <256 x i32> zeroinitializer
+  %z = and <256 x i32> %x, %vy
+  ret <256 x i32> %z
+}
+
+
+
+; <256 x i64>
+
+; Function Attrs: nounwind
+define fastcc <256 x i64> @and_vv_v256i64(<256 x i64> %x, <256 x i64> %y) {
+; CHECK-LABEL: and_vv_v256i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vand %v0, %v0, %v1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = and <256 x i64> %x, %y
+  ret <256 x i64> %z
+}
+
+; Function Attrs: nounwind
+define fastcc <256 x i64> @and_sv_v256i64(i64 %x, <256 x i64> %y) {
+; CHECK-LABEL: and_sv_v256i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    vand %v0, %s0, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %xins = insertelement <256 x i64> undef, i64 %x, i32 0
+  %vx = shufflevector <256 x i64> %xins, <256 x i64> undef, <256 x i32> zeroinitializer
+  %z = and <256 x i64> %vx, %y
+  ret <256 x i64> %z
+}
+
+; Function Attrs: nounwind
+define fastcc <256 x i64> @and_vs_v256i64(<256 x i64> %x, i64 %y) {
+; CHECK-LABEL: and_vs_v256i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    vand %v0, %s0, %v0
+; CHECK-NEXT:    b.l.t (, %s10)
+  %yins = insertelement <256 x i64> undef, i64 %y, i32 0
+  %vy = shufflevector <256 x i64> %yins, <256 x i64> undef, <256 x i32> zeroinitializer
+  %z = and <256 x i64> %x, %vy
+  ret <256 x i64> %z
+}
+
+; <128 x i64>
+; We expect this to be widened.
+
+; Function Attrs: nounwind
+define fastcc <128 x i64> @and_vv_v128i64(<128 x i64> %x, <128 x i64> %y) {
+; CHECK-LABEL: and_vv_v128i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    vand %v0, %v0, %v1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = and <128 x i64> %x, %y
+  ret <128 x i64> %z
+}
+
+; <256 x i16>
+; We expect promotion.
+
+; Function Attrs: nounwind
+define fastcc <256 x i16> @and_vv_v256i16(<256 x i16> %x, <256 x i16> %y) {
+; CHECK-LABEL: and_vv_v256i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lea %s0, 256
+; CHECK-NEXT:    lvl %s0
+; CHECK-NEXT:    pvand.lo %v0, %v0, %v1
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = and <256 x i16> %x, %y
+  ret <256 x i16> %z
+}
+
+; <128 x i16>
+; We expect this to be scalarized (for now).
+
+; Function Attrs: nounwind
+define fastcc <128 x i16> @and_vv_v128i16(<128 x i16> %x, <128 x i16> %y) {
+; CHECK-LABEL: and_vv_v128i16:
+; CHECK-NOT:       vand
+  %z = and <128 x i16> %x, %y
+  ret <128 x i16> %z
+}
+
diff --git a/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll b/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
index 4f75887873784..1360e0172d3fd 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-build-vector.ll
@@ -178,7 +178,7 @@ define <8 x i16> @splat_common_arg_i16x8(i16 %a, i16 %b, i16 %c) {
 
 ; CHECK-LABEL: swizzle_one_i8x16:
 ; CHECK-NEXT:  .functype       swizzle_one_i8x16 (v128, v128) -> (v128)
-; CHECK-NEXT:  v8x16.swizzle   $push[[L0:[0-9]+]]=, $0, $1
+; CHECK-NEXT:  i8x16.swizzle   $push[[L0:[0-9]+]]=, $0, $1
 ; CHECK-NEXT:  return          $pop[[L0]]
 define <16 x i8> @swizzle_one_i8x16(<16 x i8> %src, <16 x i8> %mask) {
   %m0 = extractelement <16 x i8> %mask, i32 0
@@ -189,7 +189,7 @@ define <16 x i8> @swizzle_one_i8x16(<16 x i8> %src, <16 x i8> %mask) {
 
 ; CHECK-LABEL: swizzle_all_i8x16:
 ; CHECK-NEXT:  .functype       swizzle_all_i8x16 (v128, v128) -> (v128)
-; CHECK-NEXT:  v8x16.swizzle   $push[[L0:[0-9]+]]=, $0, $1
+; CHECK-NEXT:  i8x16.swizzle   $push[[L0:[0-9]+]]=, $0, $1
 ; CHECK-NEXT:  return          $pop[[L0]]
 define <16 x i8> @swizzle_all_i8x16(<16 x i8> %src, <16 x i8> %mask) {
   %m0 = extractelement <16 x i8> %mask, i32 0
@@ -256,7 +256,7 @@ define <8 x i16> @swizzle_one_i16x8(<8 x i16> %src, <8 x i16> %mask) {
 
 ; CHECK-LABEL: mashup_swizzle_i8x16:
 ; CHECK-NEXT:  .functype       mashup_swizzle_i8x16 (v128, v128, i32) -> (v128)
-; CHECK-NEXT:  v8x16.swizzle   $push[[L0:[0-9]+]]=, $0, $1
+; CHECK-NEXT:  i8x16.swizzle   $push[[L0:[0-9]+]]=, $0, $1
 ; CHECK:       i8x16.replace_lane
 ; CHECK:       i8x16.replace_lane
 ; CHECK:       i8x16.replace_lane
diff --git a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
index 23a7bfbde927a..da7343770de77 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -13,7 +13,7 @@ target triple = "wasm32-unknown-unknown"
 ; ==============================================================================
 ; CHECK-LABEL: swizzle_v16i8:
 ; SIMD128-NEXT: .functype swizzle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
+; SIMD128-NEXT: i8x16.swizzle $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>)
 define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
@@ -164,9 +164,9 @@ define <16 x i8> @narrow_unsigned_v16i8(<8 x i16> %low, <8 x i16> %high) {
 }
 
 ; CHECK-LABEL: shuffle_v16i8:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.wasm.shuffle(
@@ -180,9 +180,9 @@ define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
 }
 
 ; CHECK-LABEL: shuffle_undef_v16i8:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
diff --git a/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll b/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
index 4e693c285a3fa..3d08a586edb5a 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-load-splat.ll
@@ -9,7 +9,7 @@ target triple = "wasm32-unknown-unknown"
 ; CHECK-LABEL: load_splat:
 ; CHECK-NEXT: .functype load_splat (i32, i32) -> (i32)
 ; CHECK-NEXT: i32.load8_u $[[E:[0-9]+]]=, 0($0){{$}}
-; CHECK-NEXT: v8x16.load_splat $push[[V:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load8_splat $push[[V:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: v128.store 0($1), $pop[[V]]{{$}}
 ; CHECK-NEXT: return $[[E]]{{$}}
 define i8 @load_splat(i8* %p, <16 x i8>* %out) {
diff --git a/llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll b/llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
index 8ebeb15ccc9a2..000b7730e3bf2 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-load-store-alignment.ll
@@ -89,11 +89,11 @@ define void @store_v16i8_a32(<16 x i8> *%p, <16 x i8> %v) {
   ret void
 }
 
-; 1 is the default alignment for v8x16.load_splat so no attribute is needed.
+; 1 is the default alignment for v128.load8_splat so no attribute is needed.
 
 ; CHECK-LABEL: load_splat_v16i8_a1:
 ; CHECK-NEXT: .functype load_splat_v16i8_a1 (i32) -> (v128){{$}}
-; CHECK-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load8_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_splat_v16i8_a1(i8* %p) {
   %e = load i8, i8* %p, align 1
@@ -106,7 +106,7 @@ define <16 x i8> @load_splat_v16i8_a1(i8* %p) {
 
 ; CHECK-LABEL: load_splat_v16i8_a2:
 ; CHECK-NEXT: .functype load_splat_v16i8_a2 (i32) -> (v128){{$}}
-; CHECK-NEXT: v8x16.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load8_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @load_splat_v16i8_a2(i8* %p) {
   %e = load i8, i8* %p, align 2
@@ -304,7 +304,7 @@ define <8 x i16> @load_sext_v8i16_a16(<8 x i8>* %p) {
 
 ; CHECK-LABEL: load_splat_v8i16_a1:
 ; CHECK-NEXT: .functype load_splat_v8i16_a1 (i32) -> (v128){{$}}
-; CHECK-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
+; CHECK-NEXT: v128.load16_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_splat_v8i16_a1(i16* %p) {
   %e = load i16, i16* %p, align 1
@@ -313,11 +313,11 @@ define <8 x i16> @load_splat_v8i16_a1(i16* %p) {
   ret <8 x i16> %v2
 }
 
-; 2 is the default alignment for v16x8.load_splat so no attribute is needed.
+; 2 is the default alignment for v128.load16_splat so no attribute is needed.
 
 ; CHECK-LABEL: load_splat_v8i16_a2:
 ; CHECK-NEXT: .functype load_splat_v8i16_a2 (i32) -> (v128){{$}}
-; CHECK-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load16_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_splat_v8i16_a2(i16* %p) {
   %e = load i16, i16* %p, align 2
@@ -330,7 +330,7 @@ define <8 x i16> @load_splat_v8i16_a2(i16* %p) {
 
 ; CHECK-LABEL: load_splat_v8i16_a4:
 ; CHECK-NEXT: .functype load_splat_v8i16_a4 (i32) -> (v128){{$}}
-; CHECK-NEXT: v16x8.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load16_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @load_splat_v8i16_a4(i16* %p) {
   %e = load i16, i16* %p, align 4
@@ -528,7 +528,7 @@ define <4 x i32> @load_sext_v4i32_a16(<4 x i16>* %p) {
 
 ; CHECK-LABEL: load_splat_v4i32_a1:
 ; CHECK-NEXT: .functype load_splat_v4i32_a1 (i32) -> (v128){{$}}
-; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
+; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_splat_v4i32_a1(i32* %addr) {
   %e = load i32, i32* %addr, align 1
@@ -539,7 +539,7 @@ define <4 x i32> @load_splat_v4i32_a1(i32* %addr) {
 
 ; CHECK-LABEL: load_splat_v4i32_a2:
 ; CHECK-NEXT: .functype load_splat_v4i32_a2 (i32) -> (v128){{$}}
-; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
+; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_splat_v4i32_a2(i32* %addr) {
   %e = load i32, i32* %addr, align 2
@@ -548,11 +548,11 @@ define <4 x i32> @load_splat_v4i32_a2(i32* %addr) {
   ret <4 x i32> %v2
 }
 
-; 4 is the default alignment for v32x4.load_splat so no attribute is needed.
+; 4 is the default alignment for v128.load32_splat so no attribute is needed.
 
 ; CHECK-LABEL: load_splat_v4i32_a4:
 ; CHECK-NEXT: .functype load_splat_v4i32_a4 (i32) -> (v128){{$}}
-; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_splat_v4i32_a4(i32* %addr) {
   %e = load i32, i32* %addr, align 4
@@ -565,7 +565,7 @@ define <4 x i32> @load_splat_v4i32_a4(i32* %addr) {
 
 ; CHECK-LABEL: load_splat_v4i32_a8:
 ; CHECK-NEXT: .functype load_splat_v4i32_a8 (i32) -> (v128){{$}}
-; CHECK-NEXT: v32x4.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load32_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @load_splat_v4i32_a8(i32* %addr) {
   %e = load i32, i32* %addr, align 8
@@ -660,7 +660,7 @@ define void @store_v2i64_a32(<2 x i64> *%p, <2 x i64> %v) {
 
 ; CHECK-LABEL: load_splat_v2i64_a1:
 ; CHECK-NEXT: .functype load_splat_v2i64_a1 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0):p2align=0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_a1(i64* %p) {
   %e = load i64, i64* %p, align 1
@@ -671,7 +671,7 @@ define <2 x i64> @load_splat_v2i64_a1(i64* %p) {
 
 ; CHECK-LABEL: load_splat_v2i64_a2:
 ; CHECK-NEXT: .functype load_splat_v2i64_a2 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0):p2align=1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_a2(i64* %p) {
   %e = load i64, i64* %p, align 2
@@ -682,7 +682,7 @@ define <2 x i64> @load_splat_v2i64_a2(i64* %p) {
 
 ; CHECK-LABEL: load_splat_v2i64_a4:
 ; CHECK-NEXT: .functype load_splat_v2i64_a4 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0):p2align=2{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_a4(i64* %p) {
   %e = load i64, i64* %p, align 4
@@ -691,11 +691,11 @@ define <2 x i64> @load_splat_v2i64_a4(i64* %p) {
   ret <2 x i64> %v2
 }
 
-; 8 is the default alignment for v64x2.load_splat so no attribute is needed.
+; 8 is the default alignment for v128.load64_splat so no attribute is needed.
 
 ; CHECK-LABEL: load_splat_v2i64_a8:
 ; CHECK-NEXT: .functype load_splat_v2i64_a8 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_a8(i64* %p) {
   %e = load i64, i64* %p, align 8
@@ -708,7 +708,7 @@ define <2 x i64> @load_splat_v2i64_a8(i64* %p) {
 
 ; CHECK-LABEL: load_splat_v2i64_a16:
 ; CHECK-NEXT: .functype load_splat_v2i64_a16 (i32) -> (v128){{$}}
-; CHECK-NEXT: v64x2.load_splat $push[[R:[0-9]+]]=, 0($0){{$}}
+; CHECK-NEXT: v128.load64_splat $push[[R:[0-9]+]]=, 0($0){{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @load_splat_v2i64_a16(i64* %p) {
   %e = load i64, i64* %p, align 16
diff --git a/llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll b/llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
index 597ab58e879e0..b72086a2d6cb9 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-nested-shuffles.ll
@@ -6,7 +6,7 @@
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
-; CHECK: v8x16.shuffle
+; CHECK: i8x16.shuffle
 define <4 x i32> @foo(<4 x i32> %x) {
   %1 = shufflevector <4 x i32> %x, <4 x i32> undef,
     <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
diff --git a/llvm/test/CodeGen/WebAssembly/simd-offset.ll b/llvm/test/CodeGen/WebAssembly/simd-offset.ll
index b2d32936df130..fb41653a514a0 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-offset.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-offset.ll
@@ -25,7 +25,7 @@ define <16 x i8> @load_splat_v16i8(i8* %p) {
 ; CHECK:         .functype load_splat_v16i8 (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v8x16.load_splat 0
+; CHECK-NEXT:    v128.load8_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %e = load i8, i8* %p
   %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
@@ -52,7 +52,7 @@ define <16 x i8> @load_splat_v16i8_with_folded_offset(i8* %p) {
 ; CHECK:         .functype load_splat_v16i8_with_folded_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v8x16.load_splat 16
+; CHECK-NEXT:    v128.load8_splat 16
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint i8* %p to i32
   %r = add nuw i32 %q, 16
@@ -80,7 +80,7 @@ define <16 x i8> @load_splat_v16i8_with_folded_gep_offset(i8* %p) {
 ; CHECK:         .functype load_splat_v16i8_with_folded_gep_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v8x16.load_splat 1
+; CHECK-NEXT:    v128.load8_splat 1
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds i8, i8* %p, i32 1
   %e = load i8, i8* %s
@@ -110,7 +110,7 @@ define <16 x i8> @load_splat_v16i8_with_unfolded_gep_negative_offset(i8* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const -1
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v8x16.load_splat 0
+; CHECK-NEXT:    v128.load8_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds i8, i8* %p, i32 -1
   %e = load i8, i8* %s
@@ -142,7 +142,7 @@ define <16 x i8> @load_splat_v16i8_with_unfolded_offset(i8* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v8x16.load_splat 0
+; CHECK-NEXT:    v128.load8_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint i8* %p to i32
   %r = add nsw i32 %q, 16
@@ -174,7 +174,7 @@ define <16 x i8> @load_splat_v16i8_with_unfolded_gep_offset(i8* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 1
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v8x16.load_splat 0
+; CHECK-NEXT:    v128.load8_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr i8, i8* %p, i32 1
   %e = load i8, i8* %s
@@ -200,7 +200,7 @@ define <16 x i8> @load_splat_v16i8_from_numeric_address() {
 ; CHECK:         .functype load_splat_v16i8_from_numeric_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v8x16.load_splat 32
+; CHECK-NEXT:    v128.load8_splat 32
 ; CHECK-NEXT:    # fallthrough-return
   %s = inttoptr i32 32 to i8*
   %e = load i8, i8* %s
@@ -227,7 +227,7 @@ define <16 x i8> @load_splat_v16i8_from_global_address() {
 ; CHECK:         .functype load_splat_v16i8_from_global_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v8x16.load_splat gv_i8
+; CHECK-NEXT:    v128.load8_splat gv_i8
 ; CHECK-NEXT:    # fallthrough-return
   %e = load i8, i8* @gv_i8
   %v1 = insertelement <16 x i8> undef, i8 %e, i32 0
@@ -366,7 +366,7 @@ define <8 x i16> @load_splat_v8i16(i16* %p) {
 ; CHECK:         .functype load_splat_v8i16 (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v16x8.load_splat 0
+; CHECK-NEXT:    v128.load16_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %e = load i16, i16* %p
   %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
@@ -428,7 +428,7 @@ define <8 x i16> @load_splat_v8i16_with_folded_offset(i16* %p) {
 ; CHECK:         .functype load_splat_v8i16_with_folded_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v16x8.load_splat 16
+; CHECK-NEXT:    v128.load16_splat 16
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint i16* %p to i32
   %r = add nuw i32 %q, 16
@@ -500,7 +500,7 @@ define <8 x i16> @load_splat_v8i16_with_folded_gep_offset(i16* %p) {
 ; CHECK:         .functype load_splat_v8i16_with_folded_gep_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v16x8.load_splat 2
+; CHECK-NEXT:    v128.load16_splat 2
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds i16, i16* %p, i32 1
   %e = load i16, i16* %s
@@ -568,7 +568,7 @@ define <8 x i16> @load_splat_v8i16_with_unfolded_gep_negative_offset(i16* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const -2
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v16x8.load_splat 0
+; CHECK-NEXT:    v128.load16_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds i16, i16* %p, i32 -1
   %e = load i16, i16* %s
@@ -644,7 +644,7 @@ define <8 x i16> @load_splat_v8i16_with_unfolded_offset(i16* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v16x8.load_splat 0
+; CHECK-NEXT:    v128.load16_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint i16* %p to i32
   %r = add nsw i32 %q, 16
@@ -726,7 +726,7 @@ define <8 x i16> @load_splat_v8i16_with_unfolded_gep_offset(i16* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 2
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v16x8.load_splat 0
+; CHECK-NEXT:    v128.load16_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr i16, i16* %p, i32 1
   %e = load i16, i16* %s
@@ -796,7 +796,7 @@ define <8 x i16> @load_splat_v8i16_from_numeric_address() {
 ; CHECK:         .functype load_splat_v8i16_from_numeric_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v16x8.load_splat 32
+; CHECK-NEXT:    v128.load16_splat 32
 ; CHECK-NEXT:    # fallthrough-return
   %s = inttoptr i32 32 to i16*
   %e = load i16, i16* %s
@@ -861,7 +861,7 @@ define <8 x i16> @load_splat_v8i16_from_global_address() {
 ; CHECK:         .functype load_splat_v8i16_from_global_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v16x8.load_splat gv_i16
+; CHECK-NEXT:    v128.load16_splat gv_i16
 ; CHECK-NEXT:    # fallthrough-return
   %e = load i16, i16* @gv_i16
   %v1 = insertelement <8 x i16> undef, i16 %e, i32 0
@@ -1197,7 +1197,7 @@ define <4 x i32> @load_splat_v4i32(i32* %addr) {
 ; CHECK:         .functype load_splat_v4i32 (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v32x4.load_splat 0
+; CHECK-NEXT:    v128.load32_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %e = load i32, i32* %addr, align 4
   %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
@@ -1259,7 +1259,7 @@ define <4 x i32> @load_splat_v4i32_with_folded_offset(i32* %p) {
 ; CHECK:         .functype load_splat_v4i32_with_folded_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v32x4.load_splat 16
+; CHECK-NEXT:    v128.load32_splat 16
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint i32* %p to i32
   %r = add nuw i32 %q, 16
@@ -1331,7 +1331,7 @@ define <4 x i32> @load_splat_v4i32_with_folded_gep_offset(i32* %p) {
 ; CHECK:         .functype load_splat_v4i32_with_folded_gep_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v32x4.load_splat 4
+; CHECK-NEXT:    v128.load32_splat 4
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds i32, i32* %p, i32 1
   %e = load i32, i32* %s
@@ -1399,7 +1399,7 @@ define <4 x i32> @load_splat_v4i32_with_unfolded_gep_negative_offset(i32* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const -4
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v32x4.load_splat 0
+; CHECK-NEXT:    v128.load32_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds i32, i32* %p, i32 -1
   %e = load i32, i32* %s
@@ -1475,7 +1475,7 @@ define <4 x i32> @load_splat_v4i32_with_unfolded_offset(i32* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v32x4.load_splat 0
+; CHECK-NEXT:    v128.load32_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint i32* %p to i32
   %r = add nsw i32 %q, 16
@@ -1557,7 +1557,7 @@ define <4 x i32> @load_splat_v4i32_with_unfolded_gep_offset(i32* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 4
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v32x4.load_splat 0
+; CHECK-NEXT:    v128.load32_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr i32, i32* %p, i32 1
   %e = load i32, i32* %s
@@ -1627,7 +1627,7 @@ define <4 x i32> @load_splat_v4i32_from_numeric_address() {
 ; CHECK:         .functype load_splat_v4i32_from_numeric_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v32x4.load_splat 32
+; CHECK-NEXT:    v128.load32_splat 32
 ; CHECK-NEXT:    # fallthrough-return
   %s = inttoptr i32 32 to i32*
   %e = load i32, i32* %s
@@ -1692,7 +1692,7 @@ define <4 x i32> @load_splat_v4i32_from_global_address() {
 ; CHECK:         .functype load_splat_v4i32_from_global_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v32x4.load_splat gv_i32
+; CHECK-NEXT:    v128.load32_splat gv_i32
 ; CHECK-NEXT:    # fallthrough-return
   %e = load i32, i32* @gv_i32
   %v1 = insertelement <4 x i32> undef, i32 %e, i32 0
@@ -2027,7 +2027,7 @@ define <2 x i64> @load_splat_v2i64(i64* %p) {
 ; CHECK:         .functype load_splat_v2i64 (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v64x2.load_splat 0
+; CHECK-NEXT:    v128.load64_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %e = load i64, i64* %p
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
@@ -2089,7 +2089,7 @@ define <2 x i64> @load_splat_v2i64_with_folded_offset(i64* %p) {
 ; CHECK:         .functype load_splat_v2i64_with_folded_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v64x2.load_splat 16
+; CHECK-NEXT:    v128.load64_splat 16
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint i64* %p to i32
   %r = add nuw i32 %q, 16
@@ -2161,7 +2161,7 @@ define <2 x i64> @load_splat_v2i64_with_folded_gep_offset(i64* %p) {
 ; CHECK:         .functype load_splat_v2i64_with_folded_gep_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v64x2.load_splat 8
+; CHECK-NEXT:    v128.load64_splat 8
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds i64, i64* %p, i32 1
   %e = load i64, i64* %s
@@ -2229,7 +2229,7 @@ define <2 x i64> @load_splat_v2i64_with_unfolded_gep_negative_offset(i64* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const -8
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v64x2.load_splat 0
+; CHECK-NEXT:    v128.load64_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds i64, i64* %p, i32 -1
   %e = load i64, i64* %s
@@ -2305,7 +2305,7 @@ define <2 x i64> @load_splat_v2i64_with_unfolded_offset(i64* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v64x2.load_splat 0
+; CHECK-NEXT:    v128.load64_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint i64* %p to i32
   %r = add nsw i32 %q, 16
@@ -2387,7 +2387,7 @@ define <2 x i64> @load_splat_v2i64_with_unfolded_gep_offset(i64* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 8
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v64x2.load_splat 0
+; CHECK-NEXT:    v128.load64_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr i64, i64* %p, i32 1
   %e = load i64, i64* %s
@@ -2457,7 +2457,7 @@ define <2 x i64> @load_splat_v2i64_from_numeric_address() {
 ; CHECK:         .functype load_splat_v2i64_from_numeric_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v64x2.load_splat 32
+; CHECK-NEXT:    v128.load64_splat 32
 ; CHECK-NEXT:    # fallthrough-return
   %s = inttoptr i32 32 to i64*
   %e = load i64, i64* %s
@@ -2522,7 +2522,7 @@ define <2 x i64> @load_splat_v2i64_from_global_address() {
 ; CHECK:         .functype load_splat_v2i64_from_global_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v64x2.load_splat gv_i64
+; CHECK-NEXT:    v128.load64_splat gv_i64
 ; CHECK-NEXT:    # fallthrough-return
   %e = load i64, i64* @gv_i64
   %v1 = insertelement <2 x i64> undef, i64 %e, i32 0
@@ -2697,7 +2697,7 @@ define <4 x float> @load_splat_v4f32(float* %p) {
 ; CHECK:         .functype load_splat_v4f32 (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v32x4.load_splat 0
+; CHECK-NEXT:    v128.load32_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %e = load float, float* %p
   %v1 = insertelement <4 x float> undef, float %e, i32 0
@@ -2724,7 +2724,7 @@ define <4 x float> @load_splat_v4f32_with_folded_offset(float* %p) {
 ; CHECK:         .functype load_splat_v4f32_with_folded_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v32x4.load_splat 16
+; CHECK-NEXT:    v128.load32_splat 16
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint float* %p to i32
   %r = add nuw i32 %q, 16
@@ -2752,7 +2752,7 @@ define <4 x float> @load_splat_v4f32_with_folded_gep_offset(float* %p) {
 ; CHECK:         .functype load_splat_v4f32_with_folded_gep_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v32x4.load_splat 4
+; CHECK-NEXT:    v128.load32_splat 4
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds float, float* %p, i32 1
   %e = load float, float* %s
@@ -2782,7 +2782,7 @@ define <4 x float> @load_splat_v4f32_with_unfolded_gep_negative_offset(float* %p
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const -4
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v32x4.load_splat 0
+; CHECK-NEXT:    v128.load32_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds float, float* %p, i32 -1
   %e = load float, float* %s
@@ -2814,7 +2814,7 @@ define <4 x float> @load_splat_v4f32_with_unfolded_offset(float* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v32x4.load_splat 0
+; CHECK-NEXT:    v128.load32_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint float* %p to i32
   %r = add nsw i32 %q, 16
@@ -2846,7 +2846,7 @@ define <4 x float> @load_splat_v4f32_with_unfolded_gep_offset(float* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 4
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v32x4.load_splat 0
+; CHECK-NEXT:    v128.load32_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr float, float* %p, i32 1
   %e = load float, float* %s
@@ -2872,7 +2872,7 @@ define <4 x float> @load_splat_v4f32_from_numeric_address() {
 ; CHECK:         .functype load_splat_v4f32_from_numeric_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v32x4.load_splat 32
+; CHECK-NEXT:    v128.load32_splat 32
 ; CHECK-NEXT:    # fallthrough-return
   %s = inttoptr i32 32 to float*
   %e = load float, float* %s
@@ -2899,7 +2899,7 @@ define <4 x float> @load_splat_v4f32_from_global_address() {
 ; CHECK:         .functype load_splat_v4f32_from_global_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v32x4.load_splat gv_f32
+; CHECK-NEXT:    v128.load32_splat gv_f32
 ; CHECK-NEXT:    # fallthrough-return
   %e = load float, float* @gv_f32
   %v1 = insertelement <4 x float> undef, float %e, i32 0
@@ -3038,7 +3038,7 @@ define <2 x double> @load_splat_v2f64(double* %p) {
 ; CHECK:         .functype load_splat_v2f64 (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v64x2.load_splat 0
+; CHECK-NEXT:    v128.load64_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %e = load double, double* %p
   %v1 = insertelement <2 x double> undef, double %e, i32 0
@@ -3065,7 +3065,7 @@ define <2 x double> @load_splat_v2f64_with_folded_offset(double* %p) {
 ; CHECK:         .functype load_splat_v2f64_with_folded_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v64x2.load_splat 16
+; CHECK-NEXT:    v128.load64_splat 16
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint double* %p to i32
   %r = add nuw i32 %q, 16
@@ -3093,7 +3093,7 @@ define <2 x double> @load_splat_v2f64_with_folded_gep_offset(double* %p) {
 ; CHECK:         .functype load_splat_v2f64_with_folded_gep_offset (i32) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    v64x2.load_splat 8
+; CHECK-NEXT:    v128.load64_splat 8
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds double, double* %p, i32 1
   %e = load double, double* %s
@@ -3123,7 +3123,7 @@ define <2 x double> @load_splat_v2f64_with_unfolded_gep_negative_offset(double*
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const -8
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v64x2.load_splat 0
+; CHECK-NEXT:    v128.load64_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr inbounds double, double* %p, i32 -1
   %e = load double, double* %s
@@ -3155,7 +3155,7 @@ define <2 x double> @load_splat_v2f64_with_unfolded_offset(double* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v64x2.load_splat 0
+; CHECK-NEXT:    v128.load64_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %q = ptrtoint double* %p to i32
   %r = add nsw i32 %q, 16
@@ -3187,7 +3187,7 @@ define <2 x double> @load_splat_v2f64_with_unfolded_gep_offset(double* %p) {
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i32.const 8
 ; CHECK-NEXT:    i32.add
-; CHECK-NEXT:    v64x2.load_splat 0
+; CHECK-NEXT:    v128.load64_splat 0
 ; CHECK-NEXT:    # fallthrough-return
   %s = getelementptr double, double* %p, i32 1
   %e = load double, double* %s
@@ -3213,7 +3213,7 @@ define <2 x double> @load_splat_v2f64_from_numeric_address() {
 ; CHECK:         .functype load_splat_v2f64_from_numeric_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v64x2.load_splat 32
+; CHECK-NEXT:    v128.load64_splat 32
 ; CHECK-NEXT:    # fallthrough-return
   %s = inttoptr i32 32 to double*
   %e = load double, double* %s
@@ -3240,7 +3240,7 @@ define <2 x double> @load_splat_v2f64_from_global_address() {
 ; CHECK:         .functype load_splat_v2f64_from_global_address () -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    i32.const 0
-; CHECK-NEXT:    v64x2.load_splat gv_f64
+; CHECK-NEXT:    v128.load64_splat gv_f64
 ; CHECK-NEXT:    # fallthrough-return
   %e = load double, double* @gv_f64
   %v1 = insertelement <2 x double> undef, double %e, i32 0
diff --git a/llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll b/llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
index 2473f0b27b7e8..4582bc62216a7 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-shift-complex-splats.ll
@@ -67,7 +67,7 @@ define <16 x i8> @shl_abs(<16 x i8> %v, i8 %a) {
 ; CHECK-NEXT: i8x16.splat $push1=, $1
 ; CHECK-NEXT: i8x16.splat $push0=, $2
 ; CHECK-NEXT: i8x16.add $push2=, $pop1, $pop0
-; CHECK-NEXT: v8x16.shuffle $push3=, $pop2, $0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-NEXT: i8x16.shuffle $push3=, $pop2, $0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
 ; CHECK-NEXT: i8x16.abs $push101=, $pop3
 ; CHECK-NEXT: local.tee $push100=, $3=, $pop101
 ; CHECK-NEXT: i8x16.extract_lane_u $push9=, $pop100, 0
diff --git a/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll b/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
index b3e2db98861d5..3e73b47c5a5b8 100644
--- a/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd-shuffle-bitcast.ll
@@ -21,7 +21,7 @@ define <4 x i32> @f32x4_splat(float %x) {
 ; CHECK-LABEL: not_a_vec:
 ; CHECK-NEXT: .functype not_a_vec (i64, i64) -> (v128){{$}}
 ; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $0{{$}}
-; CHECK-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $pop[[L1]], $2, 0, 1, 2, 3
+; CHECK-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $pop[[L1]], $2, 0, 1, 2, 3
 ; CHECK-NEXT: return $pop[[R]]
 define <4 x i32> @not_a_vec(i128 %x) {
   %a = bitcast i128 %x to <4 x i32>
diff --git a/llvm/test/CodeGen/WebAssembly/simd.ll b/llvm/test/CodeGen/WebAssembly/simd.ll
index 25e647f07230a..c8053293ebac0 100644
--- a/llvm/test/CodeGen/WebAssembly/simd.ll
+++ b/llvm/test/CodeGen/WebAssembly/simd.ll
@@ -202,9 +202,9 @@ define <16 x i8> @replace_zero_v16i8(<16 x i8> %v, i8 %x) {
 }
 
 ; CHECK-LABEL: shuffle_v16i8:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
@@ -215,9 +215,9 @@ define <16 x i8> @shuffle_v16i8(<16 x i8> %x, <16 x i8> %y) {
 }
 
 ; CHECK-LABEL: shuffle_undef_v16i8:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_undef_v16i8 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
@@ -472,9 +472,9 @@ define <8 x i16> @replace_zero_v8i16(<8 x i16> %v, i16 %x) {
 }
 
 ; CHECK-LABEL: shuffle_v8i16:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 18, 19, 4, 5, 22, 23, 8, 9, 26, 27, 12, 13, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shuffle_v8i16(<8 x i16> %x, <8 x i16> %y) {
@@ -484,9 +484,9 @@ define <8 x i16> @shuffle_v8i16(<8 x i16> %x, <8 x i16> %y) {
 }
 
 ; CHECK-LABEL: shuffle_undef_v8i16:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_undef_v8i16 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 2, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <8 x i16> @shuffle_undef_v8i16(<8 x i16> %x, <8 x i16> %y) {
@@ -634,9 +634,9 @@ define <4 x i32> @replace_zero_v4i32(<4 x i32> %v, i32 %x) {
 }
 
 ; CHECK-LABEL: shuffle_v4i32:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 2, 3, 20, 21, 22, 23, 8, 9, 10, 11, 28, 29, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shuffle_v4i32(<4 x i32> %x, <4 x i32> %y) {
@@ -646,9 +646,9 @@ define <4 x i32> @shuffle_v4i32(<4 x i32> %x, <4 x i32> %y) {
 }
 
 ; CHECK-LABEL: shuffle_undef_v4i32:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_undef_v4i32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x i32> @shuffle_undef_v4i32(<4 x i32> %x, <4 x i32> %y) {
@@ -785,9 +785,9 @@ define <2 x i64> @replace_zero_v2i64(<2 x i64> %v, i64 %x) {
 }
 
 ; CHECK-LABEL: shuffle_v2i64:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shuffle_v2i64(<2 x i64> %x, <2 x i64> %y) {
@@ -796,9 +796,9 @@ define <2 x i64> @shuffle_v2i64(<2 x i64> %x, <2 x i64> %y) {
 }
 
 ; CHECK-LABEL: shuffle_undef_v2i64:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_undef_v2i64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x i64> @shuffle_undef_v2i64(<2 x i64> %x, <2 x i64> %y) {
@@ -934,9 +934,9 @@ define <4 x float> @replace_zero_v4f32(<4 x float> %v, float %x) {
 }
 
 ; CHECK-LABEL: shuffle_v4f32:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 2, 3, 20, 21, 22, 23, 8, 9, 10, 11, 28, 29, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @shuffle_v4f32(<4 x float> %x, <4 x float> %y) {
@@ -946,9 +946,9 @@ define <4 x float> @shuffle_v4f32(<4 x float> %x, <4 x float> %y) {
 }
 
 ; CHECK-LABEL: shuffle_undef_v4f32:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_undef_v4f32 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 4, 5, 6, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <4 x float> @shuffle_undef_v4f32(<4 x float> %x, <4 x float> %y) {
@@ -1085,9 +1085,9 @@ define <2 x double> @replace_zero_v2f64(<2 x double> %v, double %x) {
 }
 
 ; CHECK-LABEL: shuffle_v2f64:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $1,
 ; SIMD128-SAME: 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @shuffle_v2f64(<2 x double> %x, <2 x double> %y) {
@@ -1097,9 +1097,9 @@ define <2 x double> @shuffle_v2f64(<2 x double> %x, <2 x double> %y) {
 }
 
 ; CHECK-LABEL: shuffle_undef_v2f64:
-; NO-SIMD128-NOT: v8x16
+; NO-SIMD128-NOT: i8x16
 ; SIMD128-NEXT: .functype shuffle_undef_v2f64 (v128, v128) -> (v128){{$}}
-; SIMD128-NEXT: v8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
+; SIMD128-NEXT: i8x16.shuffle $push[[R:[0-9]+]]=, $0, $0,
 ; SIMD128-SAME: 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 0, 0, 0, 0{{$}}
 ; SIMD128-NEXT: return $pop[[R]]{{$}}
 define <2 x double> @shuffle_undef_v2f64(<2 x double> %x, <2 x double> %y) {
diff --git a/llvm/test/CodeGen/WebAssembly/switch-unreachable-default.ll b/llvm/test/CodeGen/WebAssembly/switch-unreachable-default.ll
index 0f345642d4106..af941da577cc2 100644
--- a/llvm/test/CodeGen/WebAssembly/switch-unreachable-default.ll
+++ b/llvm/test/CodeGen/WebAssembly/switch-unreachable-default.ll
@@ -43,10 +43,10 @@ unreachable:
 ; CHECK:    br_if 0
 ; CHECK:    block
 ; CHECK:    block
-; CHECK:    br_table {1, 1, 1, 1, 1, 1, 1, 0}
+; CHECK:    br_table {1, 1, 0}
 ; CHECK: .LBB1_2
 ; CHECK:    end_block
-; CHECK:    br_table {0, 0, 0}
+; CHECK:    br_table {0, 0, 0, 0, 0, 0, 0, 0}
 ; CHECK: .LBB1_3
 ; CHECK:    end_block
 ; CHECK:    unreachable
diff --git a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
index 5454d7ef1bb4c..2ba3cf23774a6 100644
--- a/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
+++ b/llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll
@@ -47,7 +47,6 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(%struct.wxString* noalia
 ; CHECK-NEXT:    movb $1, %bh
 ; CHECK-NEXT:    movl $274877907, %ebp ## imm = 0x10624DD3
 ; CHECK-NEXT:    jmp LBB0_5
-; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_23: ## %bb7806
 ; CHECK-NEXT:    ## in Loop: Header=BB0_5 Depth=1
 ; CHECK-NEXT:  Ltmp16:
@@ -153,15 +152,6 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(%struct.wxString* noalia
 ; CHECK-NEXT:    calll __ZN12wxStringBase10ConcatSelfEmPKwm
 ; CHECK-NEXT:  Ltmp11:
 ; CHECK-NEXT:    jmp LBB0_5
-; CHECK-NEXT:  LBB0_22: ## %bb5968
-; CHECK-NEXT:  Ltmp2:
-; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
-; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
-; CHECK-NEXT:    movl $0, (%esp)
-; CHECK-NEXT:    calll __ZN8wxString6FormatEPKwz
-; CHECK-NEXT:    subl $4, %esp
-; CHECK-NEXT:  Ltmp3:
-; CHECK-NEXT:    jmp LBB0_27
 ; CHECK-NEXT:  LBB0_9: ## %bb5657
 ; CHECK-NEXT:  Ltmp13:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
@@ -170,6 +160,15 @@ define void @_ZNK10wxDateTime6FormatEPKwRKNS_8TimeZoneE(%struct.wxString* noalia
 ; CHECK-NEXT:    movl %eax, (%esp)
 ; CHECK-NEXT:    calll __ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE
 ; CHECK-NEXT:  Ltmp14:
+; CHECK-NEXT:    jmp LBB0_27
+; CHECK-NEXT:  LBB0_22: ## %bb5968
+; CHECK-NEXT:  Ltmp2:
+; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl $0, (%esp)
+; CHECK-NEXT:    calll __ZN8wxString6FormatEPKwz
+; CHECK-NEXT:    subl $4, %esp
+; CHECK-NEXT:  Ltmp3:
 ; CHECK-NEXT:  LBB0_27: ## %bb115.critedge.i
 ; CHECK-NEXT:    movl %esi, %eax
 ; CHECK-NEXT:    addl $28, %esp
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-blockaddress-taken.ll b/llvm/test/CodeGen/X86/basic-block-sections-blockaddress-taken.ll
index aaae1cf2a942c..4957916ddc99b 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-blockaddress-taken.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-blockaddress-taken.ll
@@ -18,7 +18,7 @@ bb1:                                                ; preds = %entry
   ret void
 ; CHECK:         .section .text,"ax",@progbits,unique,1
 ; CHECK-NEXT:  .Ltmp0:
-; CHECK-NEXT:  foo.1
+; CHECK-NEXT:  foo.__part.1
 ; CHECK-NEXT:    callq   bar
 ;
 
@@ -27,7 +27,7 @@ bb2:                                                ; preds = %entry
   ret void
 ; CHECK:         .section .text,"ax",@progbits,unique,2
 ; CHECK-NEXT:  .Ltmp1:
-; CHECK-NEXT:  foo.2
+; CHECK-NEXT:  foo.__part.2
 ; CHECK-NEXT:    callq   baz
 }
 
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-clusters-branches.ll b/llvm/test/CodeGen/X86/basic-block-sections-clusters-branches.ll
index 914ebd0cff7a8..1cf8ac17ea21c 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-clusters-branches.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-clusters-branches.ll
@@ -43,23 +43,23 @@ declare i32 @baz() #1
 
 ; LINUX-SECTIONS1:	   	.section	.text.foo,"ax",@progbits
 ; LINUX-SECTIONS1-LABEL:	foo:
-; LINUX-SECTIONS1:		jne foo.1
+; LINUX-SECTIONS1:		jne foo.__part.1
 ; LINUX-SECTIONS1-NOT:		{{jne|je|jmp}}
 ; LINUX-SECTIONS1-LABEL:	# %bb.2:
 ; LINUX-SECTIONS1:		jmp foo.cold
 ; LINUX-SECTIONS1:		.section        .text.foo,"ax",@progbits,unique,1
-; LINUX-SECTIONS1-LABEL:	foo.1:
+; LINUX-SECTIONS1-LABEL:	foo.__part.1:
 ; LINUX-SECTIONS1:		jmp foo.cold
 ; LINUX-SECTIONS1:		.section        .text.split.foo,"ax",@progbits
 ; LINUX-SECTIONS1-LABEL:	foo.cold:
 
 ; LINUX-SECTIONS2:		.section        .text.foo,"ax",@progbits
 ; LINUX-SECTIONS2-LABEL:	foo:
-; LINUX-SECTIONS2:		jne foo.0
+; LINUX-SECTIONS2:		jne foo.__part.0
 ; LINUX-SECTIONS2-NOT:		{{jne|je|jmp}}
 ; LINUX-SECTIONS2-LABEL:	# %bb.2:
 ; LINUX-SECTIONS2:		jmp .LBB0_3
 ; LINUX-SECTIONS2:		.section        .text.foo,"ax",@progbits,unique,1
-; LINUX-SECTIONS2:		foo.0:
+; LINUX-SECTIONS2:		foo.__part.0:
 ; LINUX-SECTIONS2-NOT:		{{jne|je|jmp}}
 ; LINUX-SECTIONS2:		.LBB0_3:
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-clusters-eh.ll b/llvm/test/CodeGen/X86/basic-block-sections-clusters-eh.ll
index 4e80c72f11036..fe53b1290a1b6 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-clusters-eh.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-clusters-eh.ll
@@ -60,7 +60,7 @@ declare i32 @__gxx_personality_v0(...)
 ; LINUX-SECTIONS1-NOT: 		.section
 ; LINUX-SECTIONS1-LABEL:	.LBB0_6:
 ; LINUX-SECTIONS1: 		.section	.text.main,"ax",@progbits,unique,1
-; LINUX-SECTIONS1-LABEL:	main.0:
+; LINUX-SECTIONS1-LABEL:	main.__part.0:
 ; LINUX-SECTIONS1:		.section	.text.eh.main,"ax",@progbits
 ; LINUX-SECTIONS1-LABEL: 	main.eh:
 ; LINUX-SECTIONS1-NOT: 		.section
@@ -79,7 +79,7 @@ declare i32 @__gxx_personality_v0(...)
 ; LINUX-SECTIONS2-NOT: 		.section
 ; LINUX-SECTIONS2-LABEL:	.LBB0_6:
 ; LINUX-SECTIONS2: 		.section	.text.main,"ax",@progbits,unique,1
-; LINUX-SECTIONS2-LABEL: 	main.0:
+; LINUX-SECTIONS2-LABEL: 	main.__part.0:
 ; LINUX-SECTIONS2-NOT: 		.section
 ; LINUX-SECTIONS2-LABEL:	.LBB0_2:
 ; LINUX-SECTIONS2-NOT: 		.section
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-clusters.ll b/llvm/test/CodeGen/X86/basic-block-sections-clusters.ll
index ce0e7589c0966..c133653f9a03b 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-clusters.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-clusters.ll
@@ -46,9 +46,9 @@ declare i32 @baz() #1
 ; LINUX-SECTIONS1-LABEL:	# %bb.2:
 ; LINUX-SECTIONS1-NOT:  	.LBB_END0_{{0-9}}+
 ; LINUX-SECTIONS1:		.section        .text.foo,"ax",@progbits,unique,1
-; LINUX-SECTIONS1-LABEL:	foo.1:
+; LINUX-SECTIONS1-LABEL:	foo.__part.1:
 ; LINUX-SECTIONS1-LABEL:	.LBB_END0_1:
-; LINUX-SECTIONS1-NEXT:        .size   foo.1, .LBB_END0_1-foo.1
+; LINUX-SECTIONS1-NEXT:        .size   foo.__part.1, .LBB_END0_1-foo.__part.1
 ; LINUX-SECTIONS1-NOT:  	.section
 ; LINUX-SECTIONS1:		.section        .text.split.foo,"ax",@progbits
 ; LINUX-SECTIONS1-LABEL:	foo.cold:
@@ -66,12 +66,12 @@ declare i32 @baz() #1
 ; LINUX-SECTIONS2-LABEL:	# %bb.2:
 ; LINUX-SECTIONS2-NOT:  	.LBB_END0_{{0-9}}+
 ; LINUX-SECTIONS2:		.section        .text.foo,"ax",@progbits,unique,1
-; LINUX-SECTIONS2-NEXT:		foo.0:
+; LINUX-SECTIONS2-NEXT:		foo.__part.0:
 ; LINUX-SECTIONS2-NOT:  	.LBB_END0_{{0-9}}+
 ; LINUX-SECTIONS2-NOT:  	.section
 ; LINUX-SECTIONS2-LABEL:	.LBB0_3:
 ; LINUX-SECTIONS2-LABEL:	.LBB_END0_3:
-; LINUX-SECTIONS2-NEXT:        .size   foo.0, .LBB_END0_3-foo.0
+; LINUX-SECTIONS2-NEXT:        .size   foo.__part.0, .LBB_END0_3-foo.__part.0
 ; LINUX-SECTIONS2:		.section        .text.foo,"ax",@progbits
 ; LINUX-SECTIONS2-NOT:  	.LBB_END0_{{0-9}}+
 ; LINUX-SECTIONS2-LABEL:	.Lfunc_end0:
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-directjumps.ll b/llvm/test/CodeGen/X86/basic-block-sections-directjumps.ll
index 99a64ef130319..4acaffff11d8f 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-directjumps.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-directjumps.ll
@@ -29,10 +29,10 @@ declare i32 @_Z3foov() #1
 
 ; LINUX-SECTIONS: .section        .text._Z3bazb,"ax",@progbits
 ; LINUX-SECTIONS: _Z3bazb:
-; LINUX-SECTIONS: jmp _Z3bazb.1
-; LINUX-SECTIONS: .section        .text._Z3bazb._Z3bazb.1,"ax",@progbits
-; LINUX-SECTIONS: _Z3bazb.1:
-; LINUX-SECTIONS: jmp _Z3bazb.2
-; LINUX-SECTIONS: .section        .text._Z3bazb._Z3bazb.2,"ax",@progbits
-; LINUX-SECTIONS: _Z3bazb.2:
-; LINUX-SECTIONS: jmp _Z3bazb.3
+; LINUX-SECTIONS: jmp _Z3bazb.__part.1
+; LINUX-SECTIONS: .section        .text._Z3bazb._Z3bazb.__part.1,"ax",@progbits
+; LINUX-SECTIONS: _Z3bazb.__part.1:
+; LINUX-SECTIONS: jmp _Z3bazb.__part.2
+; LINUX-SECTIONS: .section        .text._Z3bazb._Z3bazb.__part.2,"ax",@progbits
+; LINUX-SECTIONS: _Z3bazb.__part.2:
+; LINUX-SECTIONS: jmp _Z3bazb.__part.3
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-eh.ll b/llvm/test/CodeGen/X86/basic-block-sections-eh.ll
index f12e0fd386a06..743ffa3ad3368 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-eh.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-eh.ll
@@ -80,6 +80,6 @@ declare void @__cxa_end_catch()
 
 ;LINUX-SECTIONS: .section	.text._Z3foob,"ax",@progbits
 ;LINUX-SECTIONS: _Z3foob:
-;LINUX-SECTIONS: .section       .text._Z3foob._Z3foob.{{[0-9]+}},"ax",@progbits
-;LINUX-SECTIONS-LABEL: _Z3foob.{{[0-9]+}}:
+;LINUX-SECTIONS: .section       .text._Z3foob._Z3foob.__part.{{[0-9]+}},"ax",@progbits
+;LINUX-SECTIONS-LABEL: _Z3foob.__part.{{[0-9]+}}:
 ;LINUX-SECTIONS:        calll   __cxa_begin_catch
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-list.ll b/llvm/test/CodeGen/X86/basic-block-sections-list.ll
index 7c48628f73a8c..8d788ffb12348 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-list.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-list.ll
@@ -59,14 +59,14 @@ define i32 @_Z3zipb(i1 zeroext %0) nounwind {
 
 ; LINUX-SECTIONS: .section        .text._Z3foob,"ax",@progbits
 ; LINUX-SECTIONS: _Z3foob:
-; LINUX-SECTIONS: .section        .text._Z3foob._Z3foob.1,"ax",@progbits
-; LINUX-SECTIONS: _Z3foob.1:
-; LINUX-SECTIONS: .section        .text._Z3foob._Z3foob.2,"ax",@progbits
-; LINUX-SECTIONS: _Z3foob.2:
-; LINUX-SECTIONS: .section        .text._Z3foob._Z3foob.3,"ax",@progbits
-; LINUX-SECTIONS: _Z3foob.3:
+; LINUX-SECTIONS: .section        .text._Z3foob._Z3foob.__part.1,"ax",@progbits
+; LINUX-SECTIONS: _Z3foob.__part.1:
+; LINUX-SECTIONS: .section        .text._Z3foob._Z3foob.__part.2,"ax",@progbits
+; LINUX-SECTIONS: _Z3foob.__part.2:
+; LINUX-SECTIONS: .section        .text._Z3foob._Z3foob.__part.3,"ax",@progbits
+; LINUX-SECTIONS: _Z3foob.__part.3:
 
 ; LINUX-SECTIONS: .section        .text._Z3zipb,"ax",@progbits
 ; LINUX-SECTIONS: _Z3zipb:
-; LINUX-SECTIONS-NOT: .section        .text._Z3zipb._Z3zipb.{{[0-9]+}},"ax",@progbits
-; LINUX-SECTIONS-NOT: _Z3zipb.{{[0-9]+}}:
+; LINUX-SECTIONS-NOT: .section        .text._Z3zipb._Z3zipb.__part.{{[0-9]+}},"ax",@progbits
+; LINUX-SECTIONS-NOT: _Z3zipb.__part.{{[0-9]+}}:
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-listbb.ll b/llvm/test/CodeGen/X86/basic-block-sections-listbb.ll
index 53bf56e67fe58..fd6522236987d 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-listbb.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-listbb.ll
@@ -33,10 +33,10 @@ declare i32 @_Z3foov() #1
 ; LINUX-SECTIONS: .section        .text._Z3bazb,"ax",@progbits
 ; LINUX-SECTIONS: _Z3bazb:
 ; Check that the basic block with id 1 doesn't get a section.
-; LINUX-SECTIONS-NOT: .section        .text._Z3bazb._Z3bazb.{{[0-9]+}},"ax",@progbits
+; LINUX-SECTIONS-NOT: .section        .text._Z3bazb._Z3bazb.__part.{{[0-9]+}},"ax",@progbits
 ; LINUX-SECTIONS-LABEL: # %bb.1:
 ; LINUX-SECTIONS-NEXT:        callq   _Z3barv
-; LINUX-SECTIONS: .section        .text._Z3bazb.[[SECTION_LABEL:_Z3bazb.[0-9]+]],"ax",@progbits
+; LINUX-SECTIONS: .section        .text._Z3bazb.[[SECTION_LABEL:_Z3bazb.__part.[0-9]+]],"ax",@progbits
 ; LINUX-SECTIONS-NEXT: [[SECTION_LABEL]]:
 ; LINUX-SECTIONS-NEXT:        callq   _Z3foov
 ; LINUX-SECTIONS: .LBB_END0_2:
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir b/llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir
index a4219fa1509d5..6a2cee05ec88e 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir
+++ b/llvm/test/CodeGen/X86/basic-block-sections-mir-parse.mir
@@ -124,8 +124,8 @@ body:             |
 
 # CHECK: _Z3foob:
 # CHECK: .section	.text,"ax",@progbits,unique
-# CHECK: _Z3foob.1:
+# CHECK: _Z3foob.__part.1:
 # CHECK: .section	.text,"ax",@progbits,unique
-# CHECK: _Z3foob.2:
+# CHECK: _Z3foob.__part.2:
 # CHECK: .section	.text,"ax",@progbits,unique
-# CHECK: _Z3foob.3:
+# CHECK: _Z3foob.__part.3:
diff --git a/llvm/test/CodeGen/X86/basic-block-sections-unreachable.ll b/llvm/test/CodeGen/X86/basic-block-sections-unreachable.ll
index 6501d7ba44ec3..8c77070a02787 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections-unreachable.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections-unreachable.ll
@@ -14,5 +14,5 @@ default:
   unreachable
 ; CHECK-NOSECTIONS:     # %bb.2:     # %default
 ; CHECK-SECTIONS:       .section .text,"ax",@progbits,unique,2
-; CHECK-SECTIONS-NEXT:  foo.2:       # %default
+; CHECK-SECTIONS-NEXT:  foo.__part.2:       # %default
 }
diff --git a/llvm/test/CodeGen/X86/basic-block-sections.ll b/llvm/test/CodeGen/X86/basic-block-sections.ll
index 81bb5d5b4c91b..7b93076eb434e 100644
--- a/llvm/test/CodeGen/X86/basic-block-sections.ll
+++ b/llvm/test/CodeGen/X86/basic-block-sections.ll
@@ -28,11 +28,11 @@ declare i32 @_Z3foov() #1
 
 ; LINUX-SECTIONS: .section        .text._Z3bazb,"ax",@progbits
 ; LINUX-SECTIONS: _Z3bazb:
-; LINUX-SECTIONS: .section        .text._Z3bazb._Z3bazb.1,"ax",@progbits
-; LINUX-SECTIONS: _Z3bazb.1:
+; LINUX-SECTIONS: .section        .text._Z3bazb.[[SECTION_LABEL_1:_Z3bazb.__part.[0-9]+]],"ax",@progbits
+; LINUX-SECTIONS: [[SECTION_LABEL_1]]:
 ; LINUX-SECTIONS: .LBB_END0_1:
-; LINUX-SECTIONS-NEXT: .size   _Z3bazb.1, .LBB_END0_1-_Z3bazb.1
-; LINUX-SECTIONS: .section        .text._Z3bazb._Z3bazb.2,"ax",@progbits
-; LINUX-SECTIONS: _Z3bazb.2:
+; LINUX-SECTIONS-NEXT: .size  [[SECTION_LABEL_1]], .LBB_END0_1-[[SECTION_LABEL_1]]
+; LINUX-SECTIONS: .section        .text._Z3bazb.[[SECTION_LABEL_2:_Z3bazb.__part.[0-9]+]],"ax",@progbits
+; LINUX-SECTIONS: [[SECTION_LABEL_2]]:
 ; LINUX-SECTIONS: .LBB_END0_2:
-; LINUX-SECTIONS-NEXT: .size   _Z3bazb.2, .LBB_END0_2-_Z3bazb.2
+; LINUX-SECTIONS-NEXT: .size   [[SECTION_LABEL_2]], .LBB_END0_2-[[SECTION_LABEL_2]]
diff --git a/llvm/test/CodeGen/X86/basic-block-sections_2.ll b/llvm/test/CodeGen/X86/basic-block-sections_2.ll
new file mode 100644
index 0000000000000..66c4c5afe729f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/basic-block-sections_2.ll
@@ -0,0 +1,61 @@
+; Check that the basic block sections suffix naming does not conflict with __cxx_global_var_init.N naming.
+; How to  generate this file:
+;; class A {
+;;  public:
+;;    A(bool a) { }
+;; };
+;;
+;; extern bool bar(int);
+;; A g_a(bar(5) ? bar(3) : false), g_b(true);
+;;
+;; $ clang -O1 -emit-llvm -S
+;;
+; __cxx_global_var_init has multiple basic blocks which will produce many sections.
+; RUN: llc < %s -mtriple=x86_64-pc-linux -function-sections -basic-block-sections=all -unique-basic-block-section-names | FileCheck %s
+
+; CHECK-LABEL: __cxx_global_var_init:
+; CHECK-LABEL: __cxx_global_var_init.__part.1:
+; CHECK-LABEL: __cxx_global_var_init.1:
+
+%class.A = type { i8 }
+
+$_ZN1AC2Eb = comdat any
+
+@g_a = dso_local global %class.A zeroinitializer, align 1
+@g_b = dso_local global %class.A zeroinitializer, align 1
+@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @_GLOBAL__sub_I_symcollision.cc, i8* null }]
+
+define internal fastcc void @__cxx_global_var_init() unnamed_addr section ".text.startup" {
+entry:
+  %call = call zeroext i1 @_Z3bari(i32 5)
+  br i1 %call, label %cond.true, label %cond.end
+
+cond.true:                                        ; preds = %entry
+  %call1 = call zeroext i1 @_Z3bari(i32 3)
+  br label %cond.end
+
+cond.end:                                         ; preds = %entry, %cond.true
+  %cond = phi i1 [ %call1, %cond.true ], [ false, %entry ]
+  call void @_ZN1AC2Eb(%class.A* nonnull @g_a, i1 zeroext %cond)
+  ret void
+}
+
+declare dso_local zeroext i1 @_Z3bari(i32) local_unnamed_addr
+
+define linkonce_odr dso_local void @_ZN1AC2Eb(%class.A* %this, i1 zeroext %a) unnamed_addr comdat align 2 {
+entry:
+  ret void
+}
+
+define internal fastcc void @__cxx_global_var_init.1() unnamed_addr  section ".text.startup" {
+entry:
+  call void @_ZN1AC2Eb(%class.A* nonnull @g_b, i1 zeroext true)
+  ret void
+}
+
+define internal void @_GLOBAL__sub_I_symcollision.cc()  section ".text.startup" {
+entry:
+  call fastcc void @__cxx_global_var_init()
+  call fastcc void @__cxx_global_var_init.1()
+  ret void
+}
diff --git a/llvm/test/CodeGen/X86/block-placement.ll b/llvm/test/CodeGen/X86/block-placement.ll
index 258cc2031ae8b..acc4b7e138118 100644
--- a/llvm/test/CodeGen/X86/block-placement.ll
+++ b/llvm/test/CodeGen/X86/block-placement.ll
@@ -358,11 +358,11 @@ define void @unnatural_cfg2(i32* %p0, i32 %a0) {
 ; CHECK: %loop.header
 ; CHECK: %loop.body1
 ; CHECK: %loop.body2
-; CHECK: %loop.body3
-; CHECK: %loop.inner1.begin
 ; CHECK: %loop.body4
 ; CHECK: %loop.inner2.begin
 ; CHECK: %loop.inner2.begin
+; CHECK: %loop.body3
+; CHECK: %loop.inner1.begin
 ; CHECK: %bail
 
 entry:
diff --git a/llvm/test/CodeGen/X86/cfi-basic-block-sections-1.ll b/llvm/test/CodeGen/X86/cfi-basic-block-sections-1.ll
index a5a6d697451fc..6010c629c0101 100644
--- a/llvm/test/CodeGen/X86/cfi-basic-block-sections-1.ll
+++ b/llvm/test/CodeGen/X86/cfi-basic-block-sections-1.ll
@@ -16,13 +16,13 @@
 ; SECTIONS_CFI: .cfi_def_cfa_register %rbp
 ; SECTIONS_CFI: .cfi_endproc
 
-; SECTIONS_CFI: _Z2f3b.1:
+; SECTIONS_CFI: _Z2f3b.__part.1:
 ; SECTIONS_CFI-NEXT: .cfi_startproc
 ; SECTIONS_CFI-NEXT: .cfi_def_cfa %rbp, 16
 ; SECTIONS_CFI-NEXT: .cfi_offset %rbp, -16
 ; SECTIONS_CFI: .cfi_endproc
 
-; SECTIONS_CFI: _Z2f3b.2:
+; SECTIONS_CFI: _Z2f3b.__part.2:
 ; SECTIONS_CFI-NEXT: .cfi_startproc
 ; SECTIONS_CFI-NEXT: .cfi_def_cfa %rbp, 16
 ; SECTIONS_CFI-NEXT: .cfi_offset %rbp, -16
@@ -35,12 +35,12 @@
 ; SECTIONS_NOFP_CFI: .cfi_def_cfa_offset 16
 ; SECTIONS_NOFP_CFI: .cfi_endproc
 
-; SECTIONS_NOFP_CFI: _Z2f3b.1:
+; SECTIONS_NOFP_CFI: _Z2f3b.__part.1:
 ; SECTIONS_NOFP_CFI-NEXT: .cfi_startproc
 ; SECTIONS_NOFP_CFI-NEXT: .cfi_def_cfa %rsp, 16
 ; SECTIONS_NOFP_CFI: .cfi_endproc
 
-; SECTIONS_NOFP_CFI: _Z2f3b.2:
+; SECTIONS_NOFP_CFI: _Z2f3b.__part.2:
 ; SECTIONS_NOFP_CFI-NEXT: .cfi_startproc
 ; SECTIONS_NOFP_CFI-NEXT: .cfi_def_cfa %rsp, 16
 ; SECTIONS_NOFP_CFI: .cfi_endproc
diff --git a/llvm/test/CodeGen/X86/cfi-inserter-basic-block-sections-callee-save-registers.ll b/llvm/test/CodeGen/X86/cfi-inserter-basic-block-sections-callee-save-registers.ll
index d87ead0e864cf..2b207e8ae9ef5 100644
--- a/llvm/test/CodeGen/X86/cfi-inserter-basic-block-sections-callee-save-registers.ll
+++ b/llvm/test/CodeGen/X86/cfi-inserter-basic-block-sections-callee-save-registers.ll
@@ -10,7 +10,7 @@
 ; SECTIONS_CFI-NEXT: .cfi_offset [[RD:%r.+]], -32
 ; SECTIONS_CFI-NEXT: .cfi_offset [[RE:%r.+]], -24
 
-; SECTIONS_CFI:      _Z3foob.1:
+; SECTIONS_CFI:      _Z3foob.__part.1:
 ; SECTIONS_CFI:      .cfi_offset %rbp, -16
 ; SECTIONS_CFI:      .cfi_offset [[RA]], -56
 ; SECTIONS_CFI-NEXT: .cfi_offset [[RB]], -48
@@ -18,7 +18,7 @@
 ; SECTIONS_CFI-NEXT: .cfi_offset [[RD]], -32
 ; SECTIONS_CFI-NEXT: .cfi_offset [[RE]], -24
 
-; SECTIONS_CFI:      _Z3foob.2:
+; SECTIONS_CFI:      _Z3foob.__part.2:
 ; SECTIONS_CFI:      .cfi_offset %rbp, -16
 ; SECTIONS_CFI:      .cfi_offset [[RA]], -56
 ; SECTIONS_CFI-NEXT: .cfi_offset [[RB]], -48
diff --git a/llvm/test/CodeGen/X86/dwarf_eh_resume.ll b/llvm/test/CodeGen/X86/dwarf_eh_resume.ll
new file mode 100644
index 0000000000000..f44f0bc1e503a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dwarf_eh_resume.ll
@@ -0,0 +1,23 @@
+; RUN: opt -mtriple=x86_64-linux-gnu -dwarfehprepare -S %s | FileCheck %s
+
+declare i32 @hoge(...)
+
+; Check that 'resume' is lowered to _Unwind_Resume which marked as 'noreturn'
+define void @pluto() align 2 personality i8* bitcast (i32 (...)* @hoge to i8*) {
+;CHECK: call void @_Unwind_Resume(i8* %exn.obj) [[A:#.*]]
+;CHECK: attributes [[A]] = { noreturn }
+bb:
+  invoke void @spam()
+          to label %bb1 unwind label %bb2
+
+bb1:                                              ; preds = %bb
+  ret void
+
+bb2:                                              ; preds = %bb
+  %tmp = landingpad { i8*, i32 }
+          cleanup
+  resume { i8*, i32 } %tmp
+
+}
+
+declare void @spam()
diff --git a/llvm/test/CodeGen/X86/gcc_except_table_bb_sections.ll b/llvm/test/CodeGen/X86/gcc_except_table_bb_sections.ll
index ce0cc55b54e37..e0aae5be7c390 100644
--- a/llvm/test/CodeGen/X86/gcc_except_table_bb_sections.ll
+++ b/llvm/test/CodeGen/X86/gcc_except_table_bb_sections.ll
@@ -27,7 +27,7 @@ define i32 @main() uwtable optsize ssp personality i8* bitcast (i32 (...)* @__gx
 
 ; CHECK-NOT:            .cfi_lsda
 
-; CHECK-LABEL:        main.1:
+; CHECK-LABEL:        main.__part.1:
 ; CHECK-NEXT:           .cfi_startproc
 
 ; CHECK-NON-PIC-NEXT:   .cfi_personality 3, __gxx_personality_v0
@@ -38,7 +38,7 @@ define i32 @main() uwtable optsize ssp personality i8* bitcast (i32 (...)* @__gx
 
 ; CHECK-NOT:            .cfi_lsda
 
-; CHECK-LABEL:        main.2:
+; CHECK-LABEL:        main.__part.2:
 ; CHECK-NEXT:           .cfi_startproc
 
 ; CHECK-NON-PIC-NEXT:   .cfi_personality 3, __gxx_personality_v0
@@ -82,12 +82,12 @@ declare i32 @__gxx_personality_v0(...)
 
 ;; Verify @LPStart encoding for NON-PIC mode.
 ; CHECK-NON-PIC-NEXT:   .byte	0                       # @LPStart Encoding = absptr
-; CHECK-NON-PIC-NEXT:   .quad	main.2
+; CHECK-NON-PIC-NEXT:   .quad	main.__part.2
 
 ;; Verify @LPStart encoding for PIC mode.
 ; CHECK-PIC-NEXT:       .byte	16                      # @LPStart Encoding = pcrel
 ; CHECK-PIC-NEXT:     [[DOT:\.Ltmp[0-9]+]]:
-; CHECK-PIC-NEXT:       .quad	main.2-[[DOT]]
+; CHECK-PIC-NEXT:       .quad	main.__part.2-[[DOT]]
 
 ;; Verify @TType encoding for NON-PIC mode.
 ; CHECK-NON-PIC-NEXT:   .byte	3                       # @TType Encoding = udata4
@@ -102,17 +102,17 @@ declare i32 @__gxx_personality_v0(...)
 ; CHECK-NEXT:         .Lcst_begin0:
 ; CHECK-NEXT:           .uleb128 .Ltmp0-.Lfunc_begin0   # >> Call Site 1 <<
 ; CHECK-NEXT:           .uleb128 .Ltmp1-.Ltmp0          #   Call between .Ltmp0 and .Ltmp1
-; CHECK-NEXT:           .uleb128 .Ltmp2-main.2          #     jumps to .Ltmp2
+; CHECK-NEXT:           .uleb128 .Ltmp2-main.__part.2          #     jumps to .Ltmp2
 ; CHECK-NEXT:           .byte	3                       #   On action: 2
 ; CHECK-NEXT:           .p2align	2
 ; CHECK-NEXT:         .Lexception1:
 
 ; CHECK-NON-PIC-NEXT:   .byte	0                       # @LPStart Encoding = absptr
-; CHECK-NON-PIC-NEXT:   .quad	main.2
+; CHECK-NON-PIC-NEXT:   .quad	main.__part.2
 
 ; CHECK-PIC-NEXT:       .byte	16                      # @LPStart Encoding = pcrel
 ; CHECK-PIC-NEXT:     [[DOT:\.Ltmp[0-9]+]]:
-; CHECK-PIC-NEXT:       .quad	main.2-[[DOT]]
+; CHECK-PIC-NEXT:       .quad	main.__part.2-[[DOT]]
 
 ; CHECK-NON-PIC-NEXT:   .byte	3                       # @TType Encoding = udata4
 
@@ -127,11 +127,11 @@ declare i32 @__gxx_personality_v0(...)
 ; CHECK-NEXT:         .Lexception2:
 
 ; CHECK-NON-PIC-NEXT:   .byte	0                       # @LPStart Encoding = absptr
-; CHECK-NON-PIC-NEXT:   .quad	main.2
+; CHECK-NON-PIC-NEXT:   .quad	main.__part.2
 
 ; CHECK-PIC-NEXT:       .byte	16                      # @LPStart Encoding = pcrel
 ; CHECK-PIC-NEXT:     [[DOT:\.Ltmp[0-9]+]]:
-; CHECK-PIC-NEXT:       .quad	main.2-[[DOT]]
+; CHECK-PIC-NEXT:       .quad	main.__part.2-[[DOT]]
 
 ; CHECK-NON-PIC-NEXT:   .byte	3                       # @TType Encoding = udata4
 
@@ -142,8 +142,8 @@ declare i32 @__gxx_personality_v0(...)
 ; CHECK-NEXT:           .byte	1                       # Call site Encoding = uleb128
 ; CHECK-NEXT:           .uleb128 .Laction_table_base0-.Lcst_begin2
 ; CHECK-NEXT:         .Lcst_begin2:
-; CHECK-NEXT:           .uleb128 main.2-main.2          # >> Call Site 2 <<
-; CHECK-NEXT:           .uleb128 .LBB_END0_2-main.2     #   Call between main.2 and .LBB_END0_2
+; CHECK-NEXT:           .uleb128 main.__part.2-main.__part.2          # >> Call Site 2 <<
+; CHECK-NEXT:           .uleb128 .LBB_END0_2-main.__part.2     #   Call between main.__part.2 and .LBB_END0_2
 ; CHECK-NEXT:           .byte	0                       #     has no landing pad
 ; CHECK-NEXT:           .byte	0                       #   On action: cleanup
 ; CHECK-NEXT:         .Laction_table_base0:
diff --git a/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll b/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
index ab62c3b926926..517553d455ae7 100644
--- a/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
+++ b/llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
@@ -247,6 +247,303 @@ define void @test_scatter_v2i32_data_index(<2 x i32> %a1, i32* %base, <2 x i32>
   ret void
 }
 
+define void @test_mscatter_v17f32(float* %base, <17 x i32> %index, <17 x float> %val)
+; WIDEN_SKX-LABEL: test_mscatter_v17f32:
+; WIDEN_SKX:       # %bb.0:
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
+; WIDEN_SKX-NEXT:    vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; WIDEN_SKX-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
+; WIDEN_SKX-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
+; WIDEN_SKX-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
+; WIDEN_SKX-NEXT:    vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; WIDEN_SKX-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; WIDEN_SKX-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_SKX-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_SKX-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_SKX-NEXT:    vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_SKX-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_SKX-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_SKX-NEXT:    vinserti128 $1, %xmm2, %ymm1, %ymm1
+; WIDEN_SKX-NEXT:    vmovd %esi, %xmm2
+; WIDEN_SKX-NEXT:    vpinsrd $1, %edx, %xmm2, %xmm2
+; WIDEN_SKX-NEXT:    vpinsrd $2, %ecx, %xmm2, %xmm2
+; WIDEN_SKX-NEXT:    vpinsrd $3, %r8d, %xmm2, %xmm2
+; WIDEN_SKX-NEXT:    vmovd %r9d, %xmm3
+; WIDEN_SKX-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm3, %xmm3
+; WIDEN_SKX-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm3, %xmm3
+; WIDEN_SKX-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm3, %xmm3
+; WIDEN_SKX-NEXT:    vinserti128 $1, %xmm3, %ymm2, %ymm2
+; WIDEN_SKX-NEXT:    vinserti64x4 $1, %ymm1, %zmm2, %zmm1
+; WIDEN_SKX-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    kxnorw %k0, %k0, %k1
+; WIDEN_SKX-NEXT:    vscatterdps %zmm0, (%rdi,%zmm1,4) {%k1}
+; WIDEN_SKX-NEXT:    movw $1, %ax
+; WIDEN_SKX-NEXT:    kmovw %eax, %k1
+; WIDEN_SKX-NEXT:    vscatterdps %zmm2, (%rdi,%zmm3,4) {%k1}
+; WIDEN_SKX-NEXT:    vzeroupper
+; WIDEN_SKX-NEXT:    retq
+;
+; WIDEN_KNL-LABEL: test_mscatter_v17f32:
+; WIDEN_KNL:       # %bb.0:
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[2,3]
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm4 = xmm4[0,1],xmm6[0],xmm4[3]
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm4 = xmm4[0,1,2],xmm7[0]
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
+; WIDEN_KNL-NEXT:    vinsertf128 $1, %xmm4, %ymm0, %ymm0
+; WIDEN_KNL-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1],mem[0],xmm1[3]
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],mem[0]
+; WIDEN_KNL-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
+; WIDEN_KNL-NEXT:    vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
+; WIDEN_KNL-NEXT:    vinsertf128 $1, %xmm2, %ymm1, %ymm1
+; WIDEN_KNL-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; WIDEN_KNL-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_KNL-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_KNL-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_KNL-NEXT:    vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_KNL-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_KNL-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_KNL-NEXT:    vinserti128 $1, %xmm2, %ymm1, %ymm1
+; WIDEN_KNL-NEXT:    vmovd %esi, %xmm2
+; WIDEN_KNL-NEXT:    vpinsrd $1, %edx, %xmm2, %xmm2
+; WIDEN_KNL-NEXT:    vpinsrd $2, %ecx, %xmm2, %xmm2
+; WIDEN_KNL-NEXT:    vpinsrd $3, %r8d, %xmm2, %xmm2
+; WIDEN_KNL-NEXT:    vmovd %r9d, %xmm3
+; WIDEN_KNL-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm3, %xmm3
+; WIDEN_KNL-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm3, %xmm3
+; WIDEN_KNL-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm3, %xmm3
+; WIDEN_KNL-NEXT:    vinserti128 $1, %xmm3, %ymm2, %ymm2
+; WIDEN_KNL-NEXT:    vinserti64x4 $1, %ymm1, %zmm2, %zmm1
+; WIDEN_KNL-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    kxnorw %k0, %k0, %k1
+; WIDEN_KNL-NEXT:    vscatterdps %zmm0, (%rdi,%zmm1,4) {%k1}
+; WIDEN_KNL-NEXT:    movw $1, %ax
+; WIDEN_KNL-NEXT:    kmovw %eax, %k1
+; WIDEN_KNL-NEXT:    vscatterdps %zmm2, (%rdi,%zmm3,4) {%k1}
+; WIDEN_KNL-NEXT:    vzeroupper
+; WIDEN_KNL-NEXT:    retq
+;
+; WIDEN_AVX2-LABEL: test_mscatter_v17f32:
+; WIDEN_AVX2:       # %bb.0:
+; WIDEN_AVX2-NEXT:    vmovq %rdi, %xmm8
+; WIDEN_AVX2-NEXT:    vpbroadcastq %xmm8, %ymm9
+; WIDEN_AVX2-NEXT:    vmovd %esi, %xmm10
+; WIDEN_AVX2-NEXT:    vpinsrd $1, %edx, %xmm10, %xmm10
+; WIDEN_AVX2-NEXT:    vpinsrd $2, %ecx, %xmm10, %xmm10
+; WIDEN_AVX2-NEXT:    vpinsrd $3, %r8d, %xmm10, %xmm10
+; WIDEN_AVX2-NEXT:    vpmovsxdq %xmm10, %ymm10
+; WIDEN_AVX2-NEXT:    vpsllq $2, %ymm10, %ymm10
+; WIDEN_AVX2-NEXT:    vpaddq %ymm10, %ymm9, %ymm10
+; WIDEN_AVX2-NEXT:    vmovq %xmm10, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm0, (%rax)
+; WIDEN_AVX2-NEXT:    vpextrq $1, %xmm10, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm1, (%rax)
+; WIDEN_AVX2-NEXT:    vextracti128 $1, %ymm10, %xmm0
+; WIDEN_AVX2-NEXT:    vmovq %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm2, (%rax)
+; WIDEN_AVX2-NEXT:    vpextrq $1, %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm3, (%rax)
+; WIDEN_AVX2-NEXT:    vmovd %r9d, %xmm0
+; WIDEN_AVX2-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpmovsxdq %xmm0, %ymm0
+; WIDEN_AVX2-NEXT:    vpsllq $2, %ymm0, %ymm0
+; WIDEN_AVX2-NEXT:    vpaddq %ymm0, %ymm9, %ymm0
+; WIDEN_AVX2-NEXT:    vmovq %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm4, (%rax)
+; WIDEN_AVX2-NEXT:    vpextrq $1, %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm5, (%rax)
+; WIDEN_AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm0
+; WIDEN_AVX2-NEXT:    vmovq %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm6, (%rax)
+; WIDEN_AVX2-NEXT:    vpextrq $1, %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpmovsxdq %xmm0, %ymm0
+; WIDEN_AVX2-NEXT:    vpsllq $2, %ymm0, %ymm0
+; WIDEN_AVX2-NEXT:    vpaddq %ymm0, %ymm9, %ymm0
+; WIDEN_AVX2-NEXT:    vmovss %xmm7, (%rax)
+; WIDEN_AVX2-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_AVX2-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_AVX2-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_AVX2-NEXT:    vpmovsxdq %xmm1, %ymm1
+; WIDEN_AVX2-NEXT:    vpsllq $2, %ymm1, %ymm1
+; WIDEN_AVX2-NEXT:    vpaddq %ymm1, %ymm9, %ymm1
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vmovq %xmm1, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm2, (%rax)
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vpextrq $1, %xmm1, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm2, (%rax)
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vextracti128 $1, %ymm1, %xmm1
+; WIDEN_AVX2-NEXT:    vmovq %xmm1, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm2, (%rax)
+; WIDEN_AVX2-NEXT:    vpextrq $1, %xmm1, %rax
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vmovss %xmm1, (%rax)
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vmovq %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm1, (%rax)
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vpextrq $1, %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm1, (%rax)
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm0
+; WIDEN_AVX2-NEXT:    vmovq %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss %xmm1, (%rax)
+; WIDEN_AVX2-NEXT:    vpextrq $1, %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vmovss %xmm0, (%rax)
+; WIDEN_AVX2-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vpmovsxdq %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpsllq $2, %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpaddq %xmm0, %xmm8, %xmm0
+; WIDEN_AVX2-NEXT:    vmovq %xmm0, %rax
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vmovss %xmm0, (%rax)
+; WIDEN_AVX2-NEXT:    vzeroupper
+; WIDEN_AVX2-NEXT:    retq
+{
+  %gep = getelementptr float, float* %base, <17 x i32> %index
+  call void @llvm.masked.scatter.v17f32.v17p0f32(<17 x float> %val, <17 x float*> %gep, i32 4, <17 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>)
+  ret void
+}
+
+define <17 x float> @test_mgather_v17f32(float* %base, <17 x i32> %index)
+; WIDEN_SKX-LABEL: test_mgather_v17f32:
+; WIDEN_SKX:       # %bb.0:
+; WIDEN_SKX-NEXT:    movq %rdi, %rax
+; WIDEN_SKX-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_SKX-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_SKX-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_SKX-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_SKX-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_SKX-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_SKX-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; WIDEN_SKX-NEXT:    vmovd %edx, %xmm1
+; WIDEN_SKX-NEXT:    vpinsrd $1, %ecx, %xmm1, %xmm1
+; WIDEN_SKX-NEXT:    vpinsrd $2, %r8d, %xmm1, %xmm1
+; WIDEN_SKX-NEXT:    vpinsrd $3, %r9d, %xmm1, %xmm1
+; WIDEN_SKX-NEXT:    vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_SKX-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_SKX-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_SKX-NEXT:    vinserti128 $1, %xmm2, %ymm1, %ymm1
+; WIDEN_SKX-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
+; WIDEN_SKX-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_SKX-NEXT:    kxnorw %k0, %k0, %k1
+; WIDEN_SKX-NEXT:    vgatherdps (%rsi,%zmm0,4), %zmm2 {%k1}
+; WIDEN_SKX-NEXT:    movw $1, %cx
+; WIDEN_SKX-NEXT:    kmovw %ecx, %k1
+; WIDEN_SKX-NEXT:    vgatherdps (%rsi,%zmm1,4), %zmm0 {%k1}
+; WIDEN_SKX-NEXT:    vmovss %xmm0, 64(%rdi)
+; WIDEN_SKX-NEXT:    vmovaps %zmm2, (%rdi)
+; WIDEN_SKX-NEXT:    vzeroupper
+; WIDEN_SKX-NEXT:    retq
+;
+; WIDEN_KNL-LABEL: test_mgather_v17f32:
+; WIDEN_KNL:       # %bb.0:
+; WIDEN_KNL-NEXT:    movq %rdi, %rax
+; WIDEN_KNL-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_KNL-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_KNL-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_KNL-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_KNL-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_KNL-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_KNL-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; WIDEN_KNL-NEXT:    vmovd %edx, %xmm1
+; WIDEN_KNL-NEXT:    vpinsrd $1, %ecx, %xmm1, %xmm1
+; WIDEN_KNL-NEXT:    vpinsrd $2, %r8d, %xmm1, %xmm1
+; WIDEN_KNL-NEXT:    vpinsrd $3, %r9d, %xmm1, %xmm1
+; WIDEN_KNL-NEXT:    vmovd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_KNL-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_KNL-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm2, %xmm2
+; WIDEN_KNL-NEXT:    vinserti128 $1, %xmm2, %ymm1, %ymm1
+; WIDEN_KNL-NEXT:    vinserti64x4 $1, %ymm0, %zmm1, %zmm0
+; WIDEN_KNL-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_KNL-NEXT:    kxnorw %k0, %k0, %k1
+; WIDEN_KNL-NEXT:    vgatherdps (%rsi,%zmm0,4), %zmm2 {%k1}
+; WIDEN_KNL-NEXT:    movw $1, %cx
+; WIDEN_KNL-NEXT:    kmovw %ecx, %k1
+; WIDEN_KNL-NEXT:    vgatherdps (%rsi,%zmm1,4), %zmm0 {%k1}
+; WIDEN_KNL-NEXT:    vmovss %xmm0, 64(%rdi)
+; WIDEN_KNL-NEXT:    vmovaps %zmm2, (%rdi)
+; WIDEN_KNL-NEXT:    vzeroupper
+; WIDEN_KNL-NEXT:    retq
+;
+; WIDEN_AVX2-LABEL: test_mgather_v17f32:
+; WIDEN_AVX2:       # %bb.0:
+; WIDEN_AVX2-NEXT:    vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm0, %xmm0
+; WIDEN_AVX2-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_AVX2-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_AVX2-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_AVX2-NEXT:    movq %rdi, %rax
+; WIDEN_AVX2-NEXT:    vmovd %edx, %xmm2
+; WIDEN_AVX2-NEXT:    vpinsrd $1, %ecx, %xmm2, %xmm2
+; WIDEN_AVX2-NEXT:    vpinsrd $2, %r8d, %xmm2, %xmm2
+; WIDEN_AVX2-NEXT:    vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vpinsrd $3, %r9d, %xmm2, %xmm2
+; WIDEN_AVX2-NEXT:    vmovd {{.*#+}} xmm4 = mem[0],zero,zero,zero
+; WIDEN_AVX2-NEXT:    vpinsrd $1, {{[0-9]+}}(%rsp), %xmm4, %xmm4
+; WIDEN_AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; WIDEN_AVX2-NEXT:    vpinsrd $2, {{[0-9]+}}(%rsp), %xmm4, %xmm1
+; WIDEN_AVX2-NEXT:    vpinsrd $3, {{[0-9]+}}(%rsp), %xmm1, %xmm1
+; WIDEN_AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm2, %ymm1
+; WIDEN_AVX2-NEXT:    vpcmpeqd %ymm2, %ymm2, %ymm2
+; WIDEN_AVX2-NEXT:    vgatherdps %ymm2, (%rsi,%ymm1,4), %ymm4
+; WIDEN_AVX2-NEXT:    vpcmpeqd %ymm1, %ymm1, %ymm1
+; WIDEN_AVX2-NEXT:    vgatherdps %ymm1, (%rsi,%ymm0,4), %ymm2
+; WIDEN_AVX2-NEXT:    vmovaps {{.*#+}} xmm0 = [4294967295,0,0,0]
+; WIDEN_AVX2-NEXT:    vgatherdps %ymm0, (%rsi,%ymm3,4), %ymm1
+; WIDEN_AVX2-NEXT:    vmovss %xmm1, 64(%rdi)
+; WIDEN_AVX2-NEXT:    vmovaps %ymm2, 32(%rdi)
+; WIDEN_AVX2-NEXT:    vmovaps %ymm4, (%rdi)
+; WIDEN_AVX2-NEXT:    vzeroupper
+; WIDEN_AVX2-NEXT:    retq
+{
+  %gep = getelementptr float, float* %base, <17 x i32> %index
+  %res = call <17 x float> @llvm.masked.gather.v17f32.v17p0f32(<17 x float*> %gep, i32 4, <17 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <17 x float> undef)
+  ret <17 x float> %res
+}
+
+declare <17 x float> @llvm.masked.gather.v17f32.v17p0f32(<17 x float*>, i32 immarg, <17 x i1>, <17 x float>)
+declare void @llvm.masked.scatter.v17f32.v17p0f32(<17 x float> , <17 x float*> , i32 , <17 x i1>)
+
 declare <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*>, i32, <2 x i1>, <2 x double>)
 declare void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double>, <2 x double*>, i32, <2 x i1>)
 declare <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*>, i32, <2 x i1>, <2 x i32>)
diff --git a/llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll b/llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll
index 7231ea35b7856..93e52ded59aff 100644
--- a/llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll
+++ b/llvm/test/CodeGen/X86/misched_phys_reg_assign_order.ll
@@ -27,10 +27,10 @@ define void @g() #0 {
 ; CHECK-NEXT:    xorl %ebx, %ebx
 ; CHECK-NEXT:    lock cmpxchg8b (%esi)
 ; CHECK-NEXT:    cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
-; CHECK-NEXT:    jne .LBB0_1
-; CHECK-NEXT:  # %bb.2: # %k.end
-; CHECK-NEXT:  .LBB0_1: # %.
+; CHECK-NEXT:    je .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %.
 ; CHECK-NEXT:    calll m
+; CHECK-NEXT:  .LBB0_2: # %k.end
 entry:
   %p = load i8*, i8** @f
   %v1 = load atomic i8, i8* %p monotonic, align 1
diff --git a/llvm/test/CodeGen/X86/pr27501.ll b/llvm/test/CodeGen/X86/pr27501.ll
index bde41214471db..e5da4ddde239e 100644
--- a/llvm/test/CodeGen/X86/pr27501.ll
+++ b/llvm/test/CodeGen/X86/pr27501.ll
@@ -6,15 +6,15 @@ define void @test1(i64* %result.repack) personality i32 (...)* @__CxxFrameHandle
 bb:
   invoke void @may_throw(i32 1)
           to label %postinvoke unwind label %cleanuppad
+; CHECK:         movq    %rcx, [[SpillLoc:.*\(%rbp\)]]
 ; CHECK:        movl    $1, %ecx
 ; CHECK:        callq   may_throw
 
 postinvoke:                                       ; preds = %bb
   store i64 19, i64* %result.repack, align 8
-
-; CHECK:        movq    $19, (%rsi)
+; CHECK:        movq	[[SpillLoc]], [[R1:%r..]]
+; CHECK:        movq    $19, ([[R1]])
 ; CHECK:        movl    $2, %ecx
-; CHECK-NEXT:   movq    %rsi, -8(%rbp)
 ; CHECK-NEXT:   callq   may_throw
   invoke void @may_throw(i32 2)
           to label %assertFailed unwind label %catch.dispatch
@@ -38,8 +38,8 @@ try.success.or.caught:                            ; preds = %catchhandler
 
 postinvoke27:                                     ; preds = %try.success.or.caught
   store i64 42, i64* %result.repack, align 8
-; CHECK:        movq    -8(%rbp), %[[reload:r..]]
-; CHECK-NEXT:   movq    $42, (%[[reload]])
+; CHECK:        movq    [[SpillLoc]], [[R2:%r..]]
+; CHECK-NEXT:   movq    $42, ([[R2]])
   ret void
 
 cleanuppad24:                                     ; preds = %try.success.or.caught
diff --git a/llvm/test/CodeGen/X86/pr37916.ll b/llvm/test/CodeGen/X86/pr37916.ll
index 84b8c08f9ea4c..270266b9bddbf 100644
--- a/llvm/test/CodeGen/X86/pr37916.ll
+++ b/llvm/test/CodeGen/X86/pr37916.ll
@@ -7,7 +7,7 @@
 define void @fn1() local_unnamed_addr {
 ; CHECK-LABEL: fn1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:  .LBB0_1: # %if.end
+; CHECK:       .LBB0_1: # %if.end
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movl a+4, %eax
 ; CHECK-NEXT:    orl a, %eax
diff --git a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
index 670477c4c2851..69dada8a884e1 100644
--- a/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
+++ b/llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
@@ -68,7 +68,7 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:    je LBB0_55
 ; CHECK-NEXT:  ## %bb.6: ## %SyTime.exit2720
 ; CHECK-NEXT:    movq %rdx, %rbx
-; CHECK-NEXT:    movq %rdi, %r14
+; CHECK-NEXT:    movq %rdi, %rbp
 ; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rax
 ; CHECK-NEXT:    leaq {{[0-9]+}}(%rsp), %rcx
 ; CHECK-NEXT:    cmpq %rax, %rcx
@@ -80,8 +80,7 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:  LBB0_8: ## %while.body.preheader
 ; CHECK-NEXT:    imulq $1040, %rbx, %rax ## imm = 0x410
 ; CHECK-NEXT:    movq _syBuf@{{.*}}(%rip), %rcx
-; CHECK-NEXT:    leaq 8(%rcx,%rax), %rax
-; CHECK-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
+; CHECK-NEXT:    leaq 8(%rcx,%rax), %rdx
 ; CHECK-NEXT:    movl $1, %r15d
 ; CHECK-NEXT:    movq _syCTRO@{{.*}}(%rip), %rax
 ; CHECK-NEXT:    movb $1, %cl
@@ -92,70 +91,71 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:    testb %cl, %cl
 ; CHECK-NEXT:    jne LBB0_9
 ; CHECK-NEXT:  ## %bb.10: ## %do.end
-; CHECK-NEXT:    xorl %ebp, %ebp
-; CHECK-NEXT:    testb %bpl, %bpl
+; CHECK-NEXT:    movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
+; CHECK-NEXT:    movq %rbp, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
+; CHECK-NEXT:    xorl %r13d, %r13d
+; CHECK-NEXT:    testb %r13b, %r13b
 ; CHECK-NEXT:    jne LBB0_11
 ; CHECK-NEXT:  ## %bb.12: ## %while.body200.preheader
-; CHECK-NEXT:    xorl %ebx, %ebx
-; CHECK-NEXT:    leaq {{.*}}(%rip), %r13
-; CHECK-NEXT:    movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
 ; CHECK-NEXT:    xorl %r12d, %r12d
-; CHECK-NEXT:    movq %r14, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
+; CHECK-NEXT:    leaq {{.*}}(%rip), %rdx
+; CHECK-NEXT:    leaq {{.*}}(%rip), %rbx
+; CHECK-NEXT:    movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
+; CHECK-NEXT:    xorl %r14d, %r14d
 ; CHECK-NEXT:    jmp LBB0_13
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_20: ## %sw.bb256
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl %ebp, %r12d
+; CHECK-NEXT:    movl %r13d, %r14d
 ; CHECK-NEXT:  LBB0_21: ## %while.cond197.backedge
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    decl %r15d
 ; CHECK-NEXT:    testl %r15d, %r15d
-; CHECK-NEXT:    movl %r12d, %ebp
+; CHECK-NEXT:    movl %r14d, %r13d
 ; CHECK-NEXT:    jle LBB0_22
 ; CHECK-NEXT:  LBB0_13: ## %while.body200
 ; CHECK-NEXT:    ## =>This Loop Header: Depth=1
 ; CHECK-NEXT:    ## Child Loop BB0_29 Depth 2
 ; CHECK-NEXT:    ## Child Loop BB0_38 Depth 2
-; CHECK-NEXT:    leal -268(%rbp), %eax
+; CHECK-NEXT:    leal -268(%r13), %eax
 ; CHECK-NEXT:    cmpl $105, %eax
 ; CHECK-NEXT:    ja LBB0_14
 ; CHECK-NEXT:  ## %bb.56: ## %while.body200
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movslq (%r13,%rax,4), %rax
-; CHECK-NEXT:    addq %r13, %rax
+; CHECK-NEXT:    movslq (%rbx,%rax,4), %rax
+; CHECK-NEXT:    addq %rbx, %rax
 ; CHECK-NEXT:    jmpq *%rax
 ; CHECK-NEXT:  LBB0_44: ## %while.cond1037.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    testb %bl, %bl
-; CHECK-NEXT:    movl %ebp, %r12d
+; CHECK-NEXT:    testb %r12b, %r12b
+; CHECK-NEXT:    movl %r13d, %r14d
 ; CHECK-NEXT:    jne LBB0_21
 ; CHECK-NEXT:    jmp LBB0_55
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_14: ## %while.body200
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    leal 1(%rbp), %eax
+; CHECK-NEXT:    leal 1(%r13), %eax
 ; CHECK-NEXT:    cmpl $21, %eax
 ; CHECK-NEXT:    ja LBB0_20
 ; CHECK-NEXT:  ## %bb.15: ## %while.body200
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl $-1, %r12d
-; CHECK-NEXT:    leaq {{.*}}(%rip), %rcx
-; CHECK-NEXT:    movslq (%rcx,%rax,4), %rax
-; CHECK-NEXT:    addq %rcx, %rax
+; CHECK-NEXT:    movl $-1, %r14d
+; CHECK-NEXT:    movslq (%rdx,%rax,4), %rax
+; CHECK-NEXT:    addq %rdx, %rax
 ; CHECK-NEXT:    jmpq *%rax
 ; CHECK-NEXT:  LBB0_18: ## %while.cond201.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl $1, %r12d
+; CHECK-NEXT:    movl $1, %r14d
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:  LBB0_26: ## %sw.bb474
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    testb %bl, %bl
-; CHECK-NEXT:    ## implicit-def: $r14
+; CHECK-NEXT:    testb %r12b, %r12b
+; CHECK-NEXT:    ## implicit-def: $rbp
 ; CHECK-NEXT:    jne LBB0_34
 ; CHECK-NEXT:  ## %bb.27: ## %do.body479.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    testb %bl, %bl
-; CHECK-NEXT:    ## implicit-def: $r14
+; CHECK-NEXT:    testb %r12b, %r12b
+; CHECK-NEXT:    ## implicit-def: $rbp
 ; CHECK-NEXT:    jne LBB0_34
 ; CHECK-NEXT:  ## %bb.28: ## %land.rhs485.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
@@ -164,8 +164,8 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_32: ## %do.body479.backedge
 ; CHECK-NEXT:    ## in Loop: Header=BB0_29 Depth=2
-; CHECK-NEXT:    leaq 1(%r14), %rax
-; CHECK-NEXT:    testb %bl, %bl
+; CHECK-NEXT:    leaq 1(%rbp), %rax
+; CHECK-NEXT:    testb %r12b, %r12b
 ; CHECK-NEXT:    je LBB0_33
 ; CHECK-NEXT:  LBB0_29: ## %land.rhs485
 ; CHECK-NEXT:    ## Parent Loop BB0_13 Depth=1
@@ -174,14 +174,14 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:    js LBB0_55
 ; CHECK-NEXT:  ## %bb.30: ## %cond.true.i.i2780
 ; CHECK-NEXT:    ## in Loop: Header=BB0_29 Depth=2
-; CHECK-NEXT:    movq %rax, %r14
-; CHECK-NEXT:    testb %bl, %bl
+; CHECK-NEXT:    movq %rax, %rbp
+; CHECK-NEXT:    testb %r12b, %r12b
 ; CHECK-NEXT:    jne LBB0_32
 ; CHECK-NEXT:  ## %bb.31: ## %lor.rhs500
 ; CHECK-NEXT:    ## in Loop: Header=BB0_29 Depth=2
 ; CHECK-NEXT:    movl $256, %esi ## imm = 0x100
 ; CHECK-NEXT:    callq ___maskrune
-; CHECK-NEXT:    testb %bl, %bl
+; CHECK-NEXT:    testb %r12b, %r12b
 ; CHECK-NEXT:    jne LBB0_32
 ; CHECK-NEXT:    jmp LBB0_34
 ; CHECK-NEXT:  LBB0_45: ## %sw.bb1134
@@ -192,22 +192,22 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:    jb LBB0_55
 ; CHECK-NEXT:  ## %bb.46: ## in Loop: Header=BB0_13 Depth=1
 ; CHECK-NEXT:    movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
-; CHECK-NEXT:    movl $268, %r12d ## imm = 0x10C
+; CHECK-NEXT:    movl $268, %r14d ## imm = 0x10C
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:  LBB0_40: ## %sw.bb566
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl $20, %r12d
+; CHECK-NEXT:    movl $20, %r14d
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:  LBB0_19: ## %sw.bb243
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    movl $2, %r12d
+; CHECK-NEXT:    movl $2, %r14d
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:  LBB0_33: ## %if.end517.loopexitsplit
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    incq %r14
+; CHECK-NEXT:    incq %rbp
 ; CHECK-NEXT:  LBB0_34: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    leal -324(%r12), %eax
+; CHECK-NEXT:    leal -324(%r14), %eax
 ; CHECK-NEXT:    cmpl $59, %eax
 ; CHECK-NEXT:    ja LBB0_35
 ; CHECK-NEXT:  ## %bb.57: ## %if.end517
@@ -217,11 +217,11 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:    jb LBB0_38
 ; CHECK-NEXT:  LBB0_35: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    cmpl $11, %r12d
+; CHECK-NEXT:    cmpl $11, %r14d
 ; CHECK-NEXT:    je LBB0_38
 ; CHECK-NEXT:  ## %bb.36: ## %if.end517
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    cmpl $24, %r12d
+; CHECK-NEXT:    cmpl $24, %r14d
 ; CHECK-NEXT:    je LBB0_38
 ; CHECK-NEXT:  ## %bb.37: ## %if.then532
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
@@ -231,14 +231,14 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:  LBB0_38: ## %for.cond534
 ; CHECK-NEXT:    ## Parent Loop BB0_13 Depth=1
 ; CHECK-NEXT:    ## => This Inner Loop Header: Depth=2
-; CHECK-NEXT:    testb %bl, %bl
+; CHECK-NEXT:    testb %r12b, %r12b
 ; CHECK-NEXT:    jne LBB0_38
 ; CHECK-NEXT:  ## %bb.39: ## %for.cond542.preheader
 ; CHECK-NEXT:    ## in Loop: Header=BB0_13 Depth=1
-; CHECK-NEXT:    testb %bl, %bl
-; CHECK-NEXT:    movb $0, (%r14)
-; CHECK-NEXT:    movl %ebp, %r12d
-; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %r14 ## 8-byte Reload
+; CHECK-NEXT:    testb %r12b, %r12b
+; CHECK-NEXT:    movb $0, (%rbp)
+; CHECK-NEXT:    movl %r13d, %r14d
+; CHECK-NEXT:    leaq {{.*}}(%rip), %rdx
 ; CHECK-NEXT:    jmp LBB0_21
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_42: ## %while.cond864
@@ -254,30 +254,32 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:    jmp LBB0_25
 ; CHECK-NEXT:  LBB0_11:
 ; CHECK-NEXT:    movl $0, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
-; CHECK-NEXT:    xorl %r12d, %r12d
+; CHECK-NEXT:    xorl %r14d, %r14d
 ; CHECK-NEXT:  LBB0_22: ## %while.end1465
-; CHECK-NEXT:    incl %r12d
-; CHECK-NEXT:    cmpl $16, %r12d
+; CHECK-NEXT:    incl %r14d
+; CHECK-NEXT:    cmpl $16, %r14d
 ; CHECK-NEXT:    ja LBB0_50
 ; CHECK-NEXT:  ## %bb.23: ## %while.end1465
 ; CHECK-NEXT:    movl $83969, %eax ## imm = 0x14801
-; CHECK-NEXT:    btl %r12d, %eax
+; CHECK-NEXT:    btl %r14d, %eax
 ; CHECK-NEXT:    jae LBB0_50
 ; CHECK-NEXT:  ## %bb.24:
-; CHECK-NEXT:    xorl %ebx, %ebx
+; CHECK-NEXT:    xorl %ebp, %ebp
+; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload
 ; CHECK-NEXT:  LBB0_48: ## %if.then1477
 ; CHECK-NEXT:    movl $1, %edx
 ; CHECK-NEXT:    callq _write
-; CHECK-NEXT:    subq %rbx, %r14
+; CHECK-NEXT:    subq %rbp, %rbx
 ; CHECK-NEXT:    movq _syHistory@{{.*}}(%rip), %rax
-; CHECK-NEXT:    leaq 8189(%r14,%rax), %rax
+; CHECK-NEXT:    leaq 8189(%rbx,%rax), %rax
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_49: ## %for.body1723
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    decq %rax
 ; CHECK-NEXT:    jmp LBB0_49
 ; CHECK-NEXT:  LBB0_47: ## %if.then1477.loopexit
-; CHECK-NEXT:    movq %r14, %rbx
+; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload
+; CHECK-NEXT:    movq %rbx, %rbp
 ; CHECK-NEXT:    jmp LBB0_48
 ; CHECK-NEXT:  LBB0_16: ## %while.cond635.preheader
 ; CHECK-NEXT:    xorl %eax, %eax
@@ -298,17 +300,18 @@ define i8* @SyFgets(i8* %line, i64 %length, i64 %fid) {
 ; CHECK-NEXT:  ## %bb.51: ## %for.body1664.lr.ph
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx ## 8-byte Reload
+; CHECK-NEXT:    movl {{[-0-9]+}}(%r{{[sb]}}p), %ebp ## 4-byte Reload
 ; CHECK-NEXT:    jne LBB0_54
 ; CHECK-NEXT:  ## %bb.52: ## %while.body1679.preheader
-; CHECK-NEXT:    incl {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Folded Spill
+; CHECK-NEXT:    incl %ebp
+; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  LBB0_53: ## %while.body1679
 ; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax ## 8-byte Reload
-; CHECK-NEXT:    movq (%rax), %rdi
+; CHECK-NEXT:    movq (%rbx), %rdi
 ; CHECK-NEXT:    callq _fileno
-; CHECK-NEXT:    movslq {{[-0-9]+}}(%r{{[sb]}}p), %rax ## 4-byte Folded Reload
-; CHECK-NEXT:    leal 1(%rax), %ecx
-; CHECK-NEXT:    movl %ecx, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
+; CHECK-NEXT:    movslq %ebp, %rax
+; CHECK-NEXT:    leal 1(%rax), %ebp
 ; CHECK-NEXT:    cmpq %rax, %rax
 ; CHECK-NEXT:    jl LBB0_53
 ; CHECK-NEXT:  LBB0_54: ## %while.cond1683.preheader
diff --git a/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll b/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
index b734dca622ae0..7c5a734acd6af 100644
--- a/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
+++ b/llvm/test/CodeGen/X86/statepoint-vreg-invoke.ll
@@ -10,14 +10,16 @@ declare dso_local i32* @personality_function()
 define i64 addrspace(1)* @test_basic_invoke(i64 addrspace(1)* %obj, i64 addrspace(1)* %obj1)
 ; CHECK-LABEL:    name: test_basic_invoke
 ; CHECK:          bb.0.entry:
-; CHECK:          renamable $r14, renamable $rbx = STATEPOINT 0, 0, 1, @some_call, $rdi, 2, 0, 2, 0, 2, 5, 2, 0, 2, -1, 2, 0, 2, 0, 2, 0, 2, 2, killed renamable $r14(tied-def 0), killed renamable $rbx(tied-def 1), 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp
+; CHECK:          MOV64mr %stack.1, 1, $noreg, 0, $noreg, renamable $rdi :: (store 8 into %stack.1)
+; CHECK:          MOV64mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $rsi :: (store 8 into %stack.0)
+; CHECK:          STATEPOINT 0, 0, 1, @some_call, $rdi, 2, 0, 2, 0, 2, 5, 2, 0, 2, -1, 2, 0, 2, 0, 2, 0, 2, 2, 1, 8, %stack.0, 0, 1, 8, %stack.1, 0, 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store 8 on %stack.0), (volatile load store 8 on %stack.1)
 ; CHECK:          JMP_1 %bb.1
 ; CHECK:          bb.1.safepoint_normal_dest:
+; CHECK:          renamable $rax = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load 8 from %stack.1)
 ; CHECK:          bb.2.normal_return:
-; CHECK:          $rax = COPY killed renamable $rbx
 ; CHECK:          RET 0, $rax
 ; CHECK:          bb.3.exceptional_return (landing-pad):
-; CHECK:          $rax = COPY killed renamable $r14
+; CHECK:          renamable $rax = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
 ; CHECK:          RET 0, $rax
   gc "statepoint-example" personality i32* ()* @"personality_function" {
 entry:
@@ -43,35 +45,37 @@ exceptional_return:
 define i64 addrspace(1)* @test_invoke_same_val(i1 %cond, i64 addrspace(1)* %val1, i64 addrspace(1)* %val2, i64 addrspace(1)* %val3)
 ; CHECK-LABEL:    name: test_invoke_same_val
 ; CHECK:          bb.0.entry:
-; CHECK:          renamable $r15 = COPY $rcx
-; CHECK:          renamable $rbx = COPY $rdx
-; CHECK:          renamable $rbp = COPY $rsi
+; CHECK:          renamable $rbx = COPY $rcx
+; CHECK:          renamable $rbp = COPY $rdx
 ; CHECK:          renamable $r14d = COPY $edi
 ; CHECK:          TEST8ri renamable $r14b, 1, implicit-def $eflags
 ; CHECK:          JCC_1 %bb.3, 4, implicit killed $eflags
 ; CHECK:          JMP_1 %bb.1
 ; CHECK:          bb.1.left:
-; CHECK:          $rdi = COPY renamable $rbp
-; CHECK:          renamable $rbx, renamable $rbp = STATEPOINT 0, 0, 1, @some_call, $rdi, 2, 0, 2, 0, 2, 0, 2, 2, killed renamable $rbx(tied-def 0), killed renamable $rbp(tied-def 1), 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp
+; CHECK:          MOV64mr %stack.0, 1, $noreg, 0, $noreg, renamable $rsi :: (store 8 into %stack.0)
+; CHECK:          $rdi = COPY killed renamable $rsi
+; CHECK:          renamable $rbp = STATEPOINT 0, 0, 1, @some_call, $rdi, 2, 0, 2, 0, 2, 0, 2, 2, killed renamable $rbp(tied-def 0), 1, 8, %stack.0, 0, 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store 8 on %stack.0)
 ; CHECK:          JMP_1 %bb.2
 ; CHECK:          bb.2.left.relocs:
+; CHECK:          renamable $rbx = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
 ; CHECK:          JMP_1 %bb.5
 ; CHECK:          bb.3.right:
-; CHECK:          $rdi = COPY killed renamable $rbp
-; CHECK:          renamable $r15, renamable $rbx = STATEPOINT 0, 0, 1, @some_call, $rdi, 2, 0, 2, 0, 2, 0, 2, 2, killed renamable $r15(tied-def 0), killed renamable $rbx(tied-def 1), 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp
+; CHECK:          MOV64mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $rbp :: (store 8 into %stack.0)
+; CHECK:          $rdi = COPY killed renamable $rsi
+; CHECK:          renamable $rbx = STATEPOINT 0, 0, 1, @some_call, $rdi, 2, 0, 2, 0, 2, 0, 2, 2, killed renamable $rbx(tied-def 0), 1, 8, %stack.0, 0, 2, 0, 2, 2, 0, 0, 1, 1, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store 8 on %stack.0)
 ; CHECK:          JMP_1 %bb.4
 ; CHECK:          bb.4.right.relocs:
-; CHECK:          renamable $rbp = COPY killed renamable $r15
+; CHECK:          renamable $rbp = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
 ; CHECK:          bb.5.normal_return:
 ; CHECK:          TEST8ri renamable $r14b, 1, implicit-def $eflags, implicit killed $r14d
-; CHECK:          renamable $rbp = CMOV64rr killed renamable $rbp, killed renamable $rbx, 4, implicit killed $eflags
-; CHECK:          $rax = COPY killed renamable $rbp
+; CHECK:          renamable $rbx = CMOV64rr killed renamable $rbx, killed renamable $rbp, 4, implicit killed $eflags
+; CHECK:          $rax = COPY killed renamable $rbx
 ; CHECK:          RET 0, $rax
 ; CHECK:          bb.6.exceptional_return.left (landing-pad):
-; CHECK:          $rax = COPY killed renamable $rbp
+; CHECK:          renamable $rax = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
 ; CHECK:          RET 0, $rax
 ; CHECK:          bb.7.exceptional_return.right (landing-pad):
-; CHECK:          $rax = COPY killed renamable $rbx
+; CHECK:          renamable $rax = MOV64rm %stack.0, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)
 ; CHECK:          RET 0, $rax
   gc "statepoint-example" personality i32* ()* @"personality_function" {
 entry:
@@ -117,17 +121,16 @@ exceptional_return.right:
 define void @test_duplicate_ir_values() gc "statepoint-example" personality i32* ()* @personality_function {
 ; CHECK-LABEL:    name: test_duplicate_ir_values
 ; CHECK:          bb.0.entry:
-; CHECK:          renamable $rbx = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg :: (load 8 from `i8 addrspace(1)* addrspace(1)* undef`, addrspace 1)
-; CHECK:          renamable $rbx = STATEPOINT 1, 16, 5, undef renamable $rax, undef $edi, undef $rsi, undef $edx, undef $ecx, undef $r8d, 2, 0, 2, 0, 2, 0, 2, 1, killed renamable $rbx(tied-def 0), 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax
+; CHECK:          renamable $rax = MOV64rm undef renamable $rax, 1, $noreg, 0, $noreg :: (load 8 from `i8 addrspace(1)* addrspace(1)* undef`, addrspace 1)
+; CHECK:          MOV64mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $rax :: (store 8 into %stack.0)
+; CHECK:          STATEPOINT 1, 16, 5, undef renamable $rax, undef $edi, undef $rsi, undef $edx, undef $ecx, undef $r8d, 2, 0, 2, 0, 2, 0, 2, 1, 1, 8, %stack.0, 0, 2, 0, 2, 1, 0, 0, csr_64, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax :: (volatile load store 8 on %stack.0)
 ; CHECK:          JMP_1 %bb.1
 ; CHECK:          bb.1.normal_continue:
-; CHECK:          MOV64mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $rbx :: (store 8 into %stack.0)
 ; CHECK:          $edi = MOV32ri 10
-; CHECK:          STATEPOINT 2882400000, 0, 1, target-flags(x86-plt) @__llvm_deoptimize, killed $edi, 2, 0, 2, 2, 2, 2, 1, 8, %stack.0, 0, 1, 8, %stack.0, 0, 2, 0, 2, 0, 2, 0, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store 8 on %stack.0)
+; CHECK:          STATEPOINT 2882400000, 0, 1, target-flags(x86-plt) @__llvm_deoptimize, killed $edi, 2, 0, 2, 2, 2, 2, 1, 8, %stack.0, 0, 1, 8, %stack.0, 0, 2, 0, 2, 0, 2, 0, csr_64, implicit-def $rsp, implicit-def $ssp
 ; CHECK:          bb.2.exceptional_return (landing-pad):
-; CHECK:          MOV64mr %stack.0, 1, $noreg, 0, $noreg, killed renamable $rbx :: (store 8 into %stack.0)
 ; CHECK:          $edi = MOV32ri -271
-; CHECK:          STATEPOINT 2882400000, 0, 1, target-flags(x86-plt) @__llvm_deoptimize, killed $edi, 2, 0, 2, 0, 2, 1, 1, 8, %stack.0, 0, 2, 0, 2, 0, 2, 0, csr_64, implicit-def $rsp, implicit-def $ssp :: (volatile load store 8 on %stack.0)
+; CHECK:          STATEPOINT 2882400000, 0, 1, target-flags(x86-plt) @__llvm_deoptimize, killed $edi, 2, 0, 2, 0, 2, 1, 1, 8, %stack.0, 0, 2, 0, 2, 0, 2, 0, csr_64, implicit-def $rsp, implicit-def $ssp
 entry:
   %val1 = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef, align 8
   %val2 = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef, align 8
diff --git a/llvm/test/DebugInfo/X86/basic-block-sections_1.ll b/llvm/test/DebugInfo/X86/basic-block-sections_1.ll
index 98728d5e8605c..959ba6728f4e0 100644
--- a/llvm/test/DebugInfo/X86/basic-block-sections_1.ll
+++ b/llvm/test/DebugInfo/X86/basic-block-sections_1.ll
@@ -16,33 +16,33 @@
 ; NO-SECTIONS: DW_AT_high_pc [DW_FORM_data4] ({{.*}})
 ; BB-SECTIONS: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000)
 ; BB-SECTIONS-NEXT: DW_AT_ranges [DW_FORM_sec_offset]
-; BB-SECTIONS-NEXT: [{{.*}}) ".text._Z3fooi.1"
-; BB-SECTIONS-NEXT: [{{.*}}) ".text._Z3fooi.2"
-; BB-SECTIONS-NEXT: [{{.*}}) ".text._Z3fooi.3"
+; BB-SECTIONS-NEXT: [{{.*}}) ".text._Z3fooi.__part.1"
+; BB-SECTIONS-NEXT: [{{.*}}) ".text._Z3fooi.__part.2"
+; BB-SECTIONS-NEXT: [{{.*}}) ".text._Z3fooi.__part.3"
 ; BB-SECTIONS-NEXT: [{{.*}}) ".text"
 ; BB-SECTIONS-ASM: _Z3fooi:
 ; BB-SECTIONS-ASM: .Ltmp{{[0-9]+}}:
 ; BB-SECTIONS-ASM-NEXT: .loc 1 2 9 prologue_end
 ; BB-SECTIONS-ASM: .Ltmp{{[0-9]+}}:
 ; BB-SECTIONS-ASM-NEXT: .loc 1 2 7 is_stmt
-; BB-SECTIONS-ASM: _Z3fooi.1:
+; BB-SECTIONS-ASM: _Z3fooi.__part.1:
 ; BB-SECTIONS-ASM: .LBB_END0_{{[0-9]+}}:
-; BB-SECTIONS-ASM: .size	_Z3fooi.1, .LBB_END0_{{[0-9]+}}-_Z3fooi.1
-; BB-SECTIONS-ASM: _Z3fooi.2:
+; BB-SECTIONS-ASM: .size	_Z3fooi.__part.1, .LBB_END0_{{[0-9]+}}-_Z3fooi.__part.1
+; BB-SECTIONS-ASM: _Z3fooi.__part.2:
 ; BB-SECTIONS-ASM: .Ltmp{{[0-9]+}}:
 ; BB-SECTIONS-ASM-NEXT: .LBB_END0_{{[0-9]+}}:
-; BB-SECTIONS-ASM: .size	_Z3fooi.2, .LBB_END0_{{[0-9]+}}-_Z3fooi.2
-; BB-SECTIONS-ASM: _Z3fooi.3:
+; BB-SECTIONS-ASM: .size	_Z3fooi.__part.2, .LBB_END0_{{[0-9]+}}-_Z3fooi.__part.2
+; BB-SECTIONS-ASM: _Z3fooi.__part.3:
 ; BB-SECTIONS-ASM: .Ltmp{{[0-9]+}}:
 ; BB-SECTIONS-ASM-NEXT: .LBB_END0_{{[0-9]+}}:
-; BB-SECTIONS-ASM: .size	_Z3fooi.3, .LBB_END0_{{[0-9]+}}-_Z3fooi.3
+; BB-SECTIONS-ASM: .size	_Z3fooi.__part.3, .LBB_END0_{{[0-9]+}}-_Z3fooi.__part.3
 ; BB-SECTIONS-ASM: .Lfunc_end0:
 ; BB-SECTIONS-ASM: .Ldebug_ranges0:
-; BB-SECTIONS-ASM-NEXT:	.quad	_Z3fooi.1
+; BB-SECTIONS-ASM-NEXT:	.quad	_Z3fooi.__part.1
 ; BB-SECTIONS-ASM-NEXT:	.quad	.LBB_END0_{{[0-9]+}}
-; BB-SECTIONS-ASM-NEXT:	.quad	_Z3fooi.2
+; BB-SECTIONS-ASM-NEXT:	.quad	_Z3fooi.__part.2
 ; BB-SECTIONS-ASM-NEXT:	.quad	.LBB_END0_{{[0-9]+}}
-; BB-SECTIONS-ASM-NEXT:	.quad	_Z3fooi.3
+; BB-SECTIONS-ASM-NEXT:	.quad	_Z3fooi.__part.3
 ; BB-SECTIONS-ASM-NEXT:	.quad	.LBB_END0_{{[0-9]+}}
 ; BB-SECTIONS-ASM-NEXT:	.quad	.Lfunc_begin0
 ; BB-SECTIONS-ASM-NEXT:	.quad	.Lfunc_end0
diff --git a/llvm/test/DebugInfo/X86/implicit_value-double.ll b/llvm/test/DebugInfo/X86/implicit_value-double.ll
index f205cb9a68eec..956c896b8d34b 100644
--- a/llvm/test/DebugInfo/X86/implicit_value-double.ll
+++ b/llvm/test/DebugInfo/X86/implicit_value-double.ll
@@ -1,8 +1,8 @@
 ;; This test checks for emission of DW_OP_implicit_value operation
 ;; for double type.
 
-; RUN: llc -debugger-tune=gdb -filetype=obj %s -o -  | llvm-dwarfdump - | FileCheck %s
-; RUN: llc -debugger-tune=lldb -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s
+; RUN: llc -O0 -debugger-tune=gdb -filetype=obj %s -o -  | llvm-dwarfdump - | FileCheck %s --check-prefixes=CHECK,BOTH
+; RUN: llc -O0 -debugger-tune=lldb -filetype=obj %s -o - | llvm-dwarfdump - | FileCheck %s --check-prefixes=CHECK,BOTH
 
 ; CHECK: .debug_info contents:
 ; CHECK: DW_TAG_variable
@@ -10,7 +10,7 @@
 ; CHECK-NEXT:                     [{{.*}}): DW_OP_implicit_value 0x8 0x1f 0x85 0xeb 0x51 0xb8 0x1e 0x09 0x40)
 ; CHECK-NEXT:  DW_AT_name    ("d")
 
-; RUN: llc -debugger-tune=sce -filetype=obj %s -o -  | llvm-dwarfdump - | FileCheck %s -check-prefix=SCE-CHECK
+; RUN: llc -O0 -debugger-tune=sce -filetype=obj %s -o -  | llvm-dwarfdump - | FileCheck %s -check-prefixes=SCE-CHECK,BOTH
 
 ; SCE-CHECK: .debug_info contents:
 ; SCE-CHECK: DW_TAG_variable
@@ -18,13 +18,11 @@
 ; SCE-CHECK-NEXT:                     [{{.*}}): DW_OP_constu 0x40091eb851eb851f, DW_OP_stack_value)
 ; SCE-CHECK-NEXT:  DW_AT_name    ("d")
 
-;; Generated from: clang -ggdb -O1
-;;int main() {
-;;        double d = 3.14;
-;;        printf("dummy\n");
-;;        d *= d;
-;;        return 0;
-;;}
+;; Using DW_OP_implicit_value for fragments is not currently supported.
+; BOTH: DW_TAG_variable
+; BOTH-NEXT:  DW_AT_location        ({{.*}}
+; BOTH-NEXT:                     [{{.*}}): DW_OP_constu 0x4047800000000000, DW_OP_stack_value, DW_OP_piece 0x8, DW_OP_constu 0x4052800000000000, DW_OP_stack_value, DW_OP_piece 0x8)
+; BOTH-NEXT:  DW_AT_name    ("c")
 
 ; ModuleID = 'implicit_value-double.c'
 source_filename = "implicit_value-double.c"
@@ -37,6 +35,8 @@ target triple = "x86_64-unknown-linux-gnu"
 define dso_local i32 @main() local_unnamed_addr #0 !dbg !7 {
 entry:
   call void @llvm.dbg.value(metadata double 3.140000e+00, metadata !12, metadata !DIExpression()), !dbg !14
+  call void @llvm.dbg.value(metadata double 4.700000e+01, metadata !17, metadata !DIExpression(DW_OP_LLVM_fragment, 0, 64)), !dbg !14
+  call void @llvm.dbg.value(metadata double 7.400000e+01, metadata !17, metadata !DIExpression(DW_OP_LLVM_fragment, 64, 64)), !dbg !14
   %puts = call i32 @puts(i8* nonnull dereferenceable(1) getelementptr inbounds ([6 x i8], [6 x i8]* @str, i64 0, i64 0)), !dbg !15
   call void @llvm.dbg.value(metadata double undef, metadata !12, metadata !DIExpression()), !dbg !14
   ret i32 0, !dbg !16
@@ -67,9 +67,11 @@ attributes #2 = { nofree nounwind }
 !8 = !DISubroutineType(types: !9)
 !9 = !{!10}
 !10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
-!11 = !{!12}
+!11 = !{!12, !17}
 !12 = !DILocalVariable(name: "d", scope: !7, file: !1, line: 2, type: !13)
 !13 = !DIBasicType(name: "double", size: 64, encoding: DW_ATE_float)
 !14 = !DILocation(line: 0, scope: !7)
 !15 = !DILocation(line: 3, column: 2, scope: !7)
 !16 = !DILocation(line: 5, column: 2, scope: !7)
+!17 = !DILocalVariable(name: "c", scope: !7, file: !1, line: 2, type: !18)
+!18 = !DIBasicType(name: "complex", size: 128, encoding: DW_ATE_complex_float)
diff --git a/llvm/test/DebugInfo/X86/stack-value-piece-inseltpoison.ll b/llvm/test/DebugInfo/X86/stack-value-piece-inseltpoison.ll
new file mode 100644
index 0000000000000..69362f74b34c2
--- /dev/null
+++ b/llvm/test/DebugInfo/X86/stack-value-piece-inseltpoison.ll
@@ -0,0 +1,114 @@
+; RUN: llc %s -filetype=obj -o - | llvm-dwarfdump -debug-info -debug-loc - | FileCheck %s
+; Test that DW_OP_piece is emitted for constants.
+;
+; // Generated from:
+; typedef struct { int a, b; } I;
+; I i(int i) {
+;   I r = {i, 0};
+;   return r;
+; }
+;
+; typedef struct { float a, b; } F;
+; F f(float f) {
+;   F r = {f, 0};
+;   return r;
+; }
+
+; CHECK: .debug_info contents:
+; CHECK: DW_TAG_subprogram
+; CHECK:   DW_AT_name ("i")
+; CHECK:   DW_TAG_variable
+; CHECK-NEXT:   DW_AT_location ([[I:0x[0-9a-f]+]]
+; CHECK-NEXT:     [{{.*}}, {{.*}}): DW_OP_reg5 RDI, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4)
+; CHECK-NEXT:   DW_AT_name ("r")
+;
+; CHECK: DW_TAG_subprogram
+; CHECK:   DW_AT_name ("f")
+; CHECK:   DW_TAG_variable
+; CHECK-NEXT:   DW_AT_location ([[F:0x[0-9a-f]+]]
+; CHECK-NEXT:     [{{.*}}, {{.*}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, {{(DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4|DW_OP_implicit_value 0x4 0x00 0x00 0x00 0x00)}}
+; CHECK-NEXT:     [{{.*}}, {{.*}}): DW_OP_piece 0x4, {{(DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4|DW_OP_implicit_value 0x4 0x00 0x00 0x00 0x00)}})
+; CHECK-NEXT:   DW_AT_name ("r")
+;
+; CHECK: .debug_loc contents:
+; CHECK:      [[I]]:
+; CHECK-NEXT:   ({{.*}}, {{.*}}): DW_OP_reg5 RDI, DW_OP_piece 0x4, DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4
+; CHECK:      [[F]]:
+; CHECK-NEXT:   ({{.*}}, {{.*}}): DW_OP_reg17 XMM0, DW_OP_piece 0x4, {{DW_OP_lit0, DW_OP_stack_value, DW_OP_piece 0x4|DW_OP_implicit_value 0x4 0x00 0x00 0x00 0x00}}
+
+source_filename = "stack-value-piece.c"
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.12.0"
+
+%struct.I = type { i32, i32 }
+%struct.F = type { float, float }
+
+; Function Attrs: nounwind readnone ssp uwtable
+define i64 @i(i32 %i) local_unnamed_addr #0 !dbg !7 {
+entry:
+  tail call void @llvm.dbg.value(metadata i32 %i, metadata !18, metadata !22), !dbg !21
+  tail call void @llvm.dbg.value(metadata i32 0, metadata !18, metadata !23), !dbg !21
+  %retval.sroa.0.0.insert.ext = zext i32 %i to i64, !dbg !24
+  ret i64 %retval.sroa.0.0.insert.ext, !dbg !24
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+; Function Attrs: nounwind readnone ssp uwtable
+define <2 x float> @f(float %f) local_unnamed_addr #0 !dbg !25 {
+entry:
+  tail call void @llvm.dbg.value(metadata float %f, metadata !36, metadata !22), !dbg !38
+  tail call void @llvm.dbg.value(metadata float 0.000000e+00, metadata !36, metadata !23), !dbg !38
+  %retval.sroa.0.0.vec.insert = insertelement <2 x float> poison, float %f, i32 0, !dbg !39
+  %retval.sroa.0.4.vec.insert = insertelement <2 x float> %retval.sroa.0.0.vec.insert, float 0.000000e+00, i32 1, !dbg !39
+  ret <2 x float> %retval.sroa.0.4.vec.insert, !dbg !40
+}
+
+; Function Attrs: nounwind readnone
+declare void @llvm.dbg.value(metadata, metadata, metadata) #1
+
+attributes #0 = { nounwind readnone ssp uwtable }
+attributes #1 = { nounwind readnone }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4, !5}
+!llvm.ident = !{!6}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 4.0.0 (trunk 285655) (llvm/trunk 285654)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+!1 = !DIFile(filename: "stack-value-piece.c", directory: "/")
+!2 = !{}
+!3 = !{i32 2, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = !{i32 1, !"PIC Level", i32 2}
+!6 = !{!"clang version 4.0.0 (trunk 285655) (llvm/trunk 285654)"}
+!7 = distinct !DISubprogram(name: "i", scope: !1, file: !1, line: 2, type: !8, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
+!8 = !DISubroutineType(types: !9)
+!9 = !{!10, !14}
+!10 = !DIDerivedType(tag: DW_TAG_typedef, name: "I", file: !1, line: 1, baseType: !11)
+!11 = distinct !DICompositeType(tag: DW_TAG_structure_type, file: !1, line: 1, size: 64, elements: !12)
+!12 = !{!13, !15}
+!13 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !11, file: !1, line: 1, baseType: !14, size: 32)
+!14 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+!15 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !11, file: !1, line: 1, baseType: !14, size: 32, offset: 32)
+!18 = !DILocalVariable(name: "r", scope: !7, file: !1, line: 3, type: !10)
+!19 = !DIExpression()
+!20 = !DILocation(line: 2, column: 9, scope: !7)
+!21 = !DILocation(line: 3, column: 5, scope: !7)
+!22 = !DIExpression(DW_OP_LLVM_fragment, 0, 32)
+!23 = !DIExpression(DW_OP_LLVM_fragment, 32, 32)
+!24 = !DILocation(line: 5, column: 1, scope: !7)
+!25 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 8, type: !26, isLocal: false, isDefinition: true, scopeLine: 8, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
+!26 = !DISubroutineType(types: !27)
+!27 = !{!28, !32}
+!28 = !DIDerivedType(tag: DW_TAG_typedef, name: "F", file: !1, line: 7, baseType: !29)
+!29 = distinct !DICompositeType(tag: DW_TAG_structure_type, file: !1, line: 7, size: 64, elements: !30)
+!30 = !{!31, !33}
+!31 = !DIDerivedType(tag: DW_TAG_member, name: "a", scope: !29, file: !1, line: 7, baseType: !32, size: 32)
+!32 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
+!33 = !DIDerivedType(tag: DW_TAG_member, name: "b", scope: !29, file: !1, line: 7, baseType: !32, size: 32, offset: 32)
+!36 = !DILocalVariable(name: "r", scope: !25, file: !1, line: 9, type: !28)
+!37 = !DILocation(line: 8, column: 11, scope: !25)
+!38 = !DILocation(line: 9, column: 5, scope: !25)
+!39 = !DILocation(line: 10, column: 10, scope: !25)
+!40 = !DILocation(line: 11, column: 1, scope: !25)
diff --git a/llvm/test/MC/AMDGPU/flat-gfx9.s b/llvm/test/MC/AMDGPU/flat-gfx9.s
index 858907ce436ea..da1ec062decee 100644
--- a/llvm/test/MC/AMDGPU/flat-gfx9.s
+++ b/llvm/test/MC/AMDGPU/flat-gfx9.s
@@ -12,7 +12,6 @@ flat_load_dword v1, v[3:4] offset:-1
 // VI-ERR: :28: error: flat offset modifier is not supported on this GPU
 // GFX9-ERR: :28: error: expected a 12-bit unsigned offset
 
-// FIXME: Error on VI in wrong column
 flat_load_dword v1, v[3:4] offset:4095
 // GFX9: flat_load_dword v1, v[3:4] offset:4095 ; encoding: [0xff,0x0f,0x50,0xdc,0x03,0x00,0x00,0x01]
 // VI-ERR: :28: error: flat offset modifier is not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/flat-global.s b/llvm/test/MC/AMDGPU/flat-global.s
index 91c10ae137234..10f152cc2f859 100644
--- a/llvm/test/MC/AMDGPU/flat-global.s
+++ b/llvm/test/MC/AMDGPU/flat-global.s
@@ -85,7 +85,6 @@ global_load_dwordx4 v[1:4], v[3:4], off dlc
 // GFX9-ERR: error: failed parsing operand
 // VI-ERR: error: instruction not supported on this GPU
 
-// FIXME: VI error should be instruction nto supported
 global_load_dword v1, v[3:4], off offset:0
 // GFX10: encoding: [0x00,0x80,0x30,0xdc,0x03,0x00,0x7d,0x01]
 // GFX9: global_load_dword v1, v[3:4], off    ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x7f,0x01]
@@ -242,6 +241,26 @@ global_atomic_cmpswap v1, v3, v[5:6], s[2:3] glc
 // GFX9: global_atomic_cmpswap v1, v3, v[5:6], s[2:3] glc ; encoding: [0x00,0x80,0x05,0xdd,0x03,0x05,0x02,0x01]
 // VI-ERR: error: instruction not supported on this GPU
 
+global_atomic_cmpswap v1, v[2:3], v[4:5], off offset:-1 glc
+// GCN: global_atomic_cmpswap v1, v[2:3], v[4:5], off offset:-1 glc ; encoding: [0xff,0x9f,0x05,0xdd,0x02,0x04,0x7f,0x01]
+// GFX10: global_atomic_cmpswap v1, v[2:3], v[4:5], off offset:-1 glc ; encoding: [0xff,0x8f,0xc5,0xdc,0x02,0x04,0x7d,0x01]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_cmpswap v1, v[2:3], v[254:255], off offset:-1 glc
+// GCN: global_atomic_cmpswap v1, v[2:3], v[254:255], off offset:-1 glc ; encoding: [0xff,0x9f,0x05,0xdd,0x02,0xfe,0x7f,0x01]
+// GFX10: global_atomic_cmpswap v1, v[2:3], v[254:255], off offset:-1 glc ; encoding: [0xff,0x8f,0xc5,0xdc,0x02,0xfe,0x7d,0x01]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_cmpswap v1, v2, v[4:5], s[2:3] offset:-1 glc
+// GCN: global_atomic_cmpswap v1, v2, v[4:5], s[2:3] offset:-1 glc ; encoding: [0xff,0x9f,0x05,0xdd,0x02,0x04,0x02,0x01]
+// GFX10: global_atomic_cmpswap v1, v2, v[4:5], s[2:3] offset:-1 glc ; encoding: [0xff,0x8f,0xc5,0xdc,0x02,0x04,0x02,0x01]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_cmpswap v1, v[2:3], v[4:5], off glc
+// GCN: global_atomic_cmpswap v1, v[2:3], v[4:5], off glc ; encoding: [0x00,0x80,0x05,0xdd,0x02,0x04,0x7f,0x01]
+// GFX10: global_atomic_cmpswap v1, v[2:3], v[4:5], off glc ; encoding: [0x00,0x80,0xc5,0xdc,0x02,0x04,0x7d,0x01]
+// VI-ERR: error: instruction not supported on this GPU
+
 global_atomic_cmpswap_x2 v[5:6], v[7:10], off
 // GFX10: encoding: [0x00,0x80,0x44,0xdd,0x05,0x07,0x7d,0x00]
 // GFX9: global_atomic_cmpswap_x2 v[5:6], v[7:10], off ; encoding: [0x00,0x80,0x84,0xdd,0x05,0x07,0x7f,0x00]
@@ -257,6 +276,26 @@ global_atomic_cmpswap_x2 v[1:2], v5, v[7:10], s[2:3] glc
 // GFX9: global_atomic_cmpswap_x2 v[1:2], v5, v[7:10], s[2:3] glc ; encoding: [0x00,0x80,0x85,0xdd,0x05,0x07,0x02,0x01]
 // VI-ERR: error: instruction not supported on this GPU
 
+global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off offset:-1 glc
+// GCN: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off offset:-1 glc ; encoding: [0xff,0x9f,0x85,0xdd,0x05,0x07,0x7f,0x01]
+// GFX10: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off offset:-1 glc ; encoding: [0xff,0x8f,0x45,0xdd,0x05,0x07,0x7d,0x01]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_cmpswap_x2 v[1:2], v[5:6], v[252:255], off offset:-1 glc
+// GCN: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[252:255], off offset:-1 glc ; encoding: [0xff,0x9f,0x85,0xdd,0x05,0xfc,0x7f,0x01]
+// GFX10: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[252:255], off offset:-1 glc ; encoding: [0xff,0x8f,0x45,0xdd,0x05,0xfc,0x7d,0x01]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_cmpswap_x2 v[1:2], v5, v[252:255], s[2:3] offset:-1 glc
+// GCN: global_atomic_cmpswap_x2 v[1:2], v5, v[252:255], s[2:3] offset:-1 glc ; encoding: [0xff,0x9f,0x85,0xdd,0x05,0xfc,0x02,0x01]
+// GFX10: global_atomic_cmpswap_x2 v[1:2], v5, v[252:255], s[2:3] offset:-1 glc ; encoding: [0xff,0x8f,0x45,0xdd,0x05,0xfc,0x02,0x01]
+// VI-ERR: error: instruction not supported on this GPU
+
+global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off glc
+// GCN: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off glc ; encoding: [0x00,0x80,0x85,0xdd,0x05,0x07,0x7f,0x01]
+// GFX10: global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off glc ; encoding: [0x00,0x80,0x45,0xdd,0x05,0x07,0x7d,0x01]
+// VI-ERR: error: instruction not supported on this GPU
+
 global_atomic_swap v[3:4], v5, off
 // GFX10: encoding: [0x00,0x80,0xc0,0xdc,0x03,0x05,0x7d,0x00]
 // GFX9: global_atomic_swap v[3:4], v5, off   ; encoding: [0x00,0x80,0x00,0xdd,0x03,0x05,0x7f,0x00]
diff --git a/llvm/test/MC/AMDGPU/flat.s b/llvm/test/MC/AMDGPU/flat.s
index 31dd4f0500f1e..f307ae30a759a 100644
--- a/llvm/test/MC/AMDGPU/flat.s
+++ b/llvm/test/MC/AMDGPU/flat.s
@@ -1,12 +1,6 @@
 // RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=CI
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=CIVI --check-prefix=VI
 
-// FIXME: For missing instruction the error message is:
-//  error: too few operands for instruction
-// It should be:
-//  error: instruction not supported on this GPU
-//
-
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s --check-prefix=NOVI --implicit-check-not=error:
 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti %s 2>&1 | FileCheck %s --check-prefix=NOSI --implicit-check-not=error:
diff --git a/llvm/test/MC/AMDGPU/fma-mix.s b/llvm/test/MC/AMDGPU/fma-mix.s
index 6bd293e467f94..f062664bf8c1b 100644
--- a/llvm/test/MC/AMDGPU/fma-mix.s
+++ b/llvm/test/MC/AMDGPU/fma-mix.s
@@ -22,8 +22,6 @@ v_fma_mix_f32 v0, abs(v1), v2, v3
 // GFX9-FMAMIX: v_fma_mix_f32 v0, |v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 // GFX9-MADMIX-ERR: error: instruction not supported on this GPU
 
-// FIXME: Improve error messages
-
 v_fma_mix_f32 v0, v1, abs(v2), v3
 // GFX9-FMAMIX: v_fma_mix_f32 v0, v1, |v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 // GFX9-MADMIX-ERR: error: instruction not supported on this GPU
@@ -80,8 +78,6 @@ v_fma_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0]
 // GFX9-FMAMIX: v_fma_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 // GFX9-MADMIX-ERR: error: instruction not supported on this GPU
 
-// FIXME: Improve error messages
-
 v_fma_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0]
 // GFX9-FMAMIX: v_fma_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 // GFX9-MADMIX-ERR: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_all.s b/llvm/test/MC/AMDGPU/gfx10_asm_all.s
deleted file mode 100644
index d05101b7d634d..0000000000000
--- a/llvm/test/MC/AMDGPU/gfx10_asm_all.s
+++ /dev/null
@@ -1,126143 +0,0 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR --implicit-check-not=error: %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W64-ERR --implicit-check-not=error: %s
-
-//===----------------------------------------------------------------------===//
-// ENC_DS.
-//===----------------------------------------------------------------------===//
-
-ds_add_u32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x00,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_u32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x00,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_u32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x00,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_u32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x00,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_u32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x00,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_u32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x00,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_u32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x00,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_u32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x00,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_u32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x00,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_u32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x00,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_u32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x00,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_u32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x00,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_u32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_u32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_u32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_u32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_u32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x02,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_u32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x02,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_u32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x02,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_u32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x02,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_u32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x02,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_u32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x02,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_u32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x02,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_u32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x02,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_u32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x02,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_u32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x02,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_u32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x02,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_u32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x02,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_u32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x02,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_u32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x02,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_u32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x02,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_u32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x02,0xd8,0xff,0x01,0x00,0x00]
-
-ds_sub_u32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x04,0xd8,0x00,0x01,0x00,0x00]
-
-ds_sub_u32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x04,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_sub_u32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x04,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_sub_u32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x04,0xd8,0xff,0x01,0x00,0x00]
-
-ds_sub_u32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x04,0xd8,0x00,0x01,0x00,0x00]
-
-ds_sub_u32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x04,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_sub_u32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x04,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_sub_u32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x04,0xd8,0xff,0x01,0x00,0x00]
-
-ds_sub_u32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x04,0xd8,0x00,0x01,0x00,0x00]
-
-ds_sub_u32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x04,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_sub_u32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x04,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_sub_u32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x04,0xd8,0xff,0x01,0x00,0x00]
-
-ds_sub_u32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xd8,0x00,0x01,0x00,0x00]
-
-ds_sub_u32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_sub_u32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_sub_u32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xd8,0xff,0x01,0x00,0x00]
-
-ds_sub_u32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x06,0xd8,0x00,0x01,0x00,0x00]
-
-ds_sub_u32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x06,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_sub_u32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x06,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_sub_u32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x06,0xd8,0xff,0x01,0x00,0x00]
-
-ds_sub_u32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x06,0xd8,0x00,0x01,0x00,0x00]
-
-ds_sub_u32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x06,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_sub_u32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x06,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_sub_u32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x06,0xd8,0xff,0x01,0x00,0x00]
-
-ds_sub_u32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x06,0xd8,0x00,0x01,0x00,0x00]
-
-ds_sub_u32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x06,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_sub_u32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x06,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_sub_u32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x06,0xd8,0xff,0x01,0x00,0x00]
-
-ds_sub_u32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x06,0xd8,0x00,0x01,0x00,0x00]
-
-ds_sub_u32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x06,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_sub_u32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x06,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_sub_u32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x06,0xd8,0xff,0x01,0x00,0x00]
-
-ds_rsub_u32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x08,0xd8,0x00,0x01,0x00,0x00]
-
-ds_rsub_u32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x08,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_rsub_u32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x08,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_rsub_u32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x08,0xd8,0xff,0x01,0x00,0x00]
-
-ds_rsub_u32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x08,0xd8,0x00,0x01,0x00,0x00]
-
-ds_rsub_u32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x08,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_rsub_u32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x08,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_rsub_u32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x08,0xd8,0xff,0x01,0x00,0x00]
-
-ds_rsub_u32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x08,0xd8,0x00,0x01,0x00,0x00]
-
-ds_rsub_u32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x08,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_rsub_u32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x08,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_rsub_u32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x08,0xd8,0xff,0x01,0x00,0x00]
-
-ds_rsub_u32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xd8,0x00,0x01,0x00,0x00]
-
-ds_rsub_u32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_rsub_u32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_rsub_u32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xd8,0xff,0x01,0x00,0x00]
-
-ds_rsub_u32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_rsub_u32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_rsub_u32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_rsub_u32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_rsub_u32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_rsub_u32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_rsub_u32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_rsub_u32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_rsub_u32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x0a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_rsub_u32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x0a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_rsub_u32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x0a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_rsub_u32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x0a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_rsub_u32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_rsub_u32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_rsub_u32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_rsub_u32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_inc_u32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_inc_u32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_inc_u32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_inc_u32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_inc_u32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_inc_u32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_inc_u32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_inc_u32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_inc_u32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x0c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_inc_u32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x0c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_inc_u32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x0c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_inc_u32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x0c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_inc_u32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_inc_u32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_inc_u32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_inc_u32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_inc_u32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_inc_u32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_inc_u32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_inc_u32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_inc_u32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_inc_u32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_inc_u32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_inc_u32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_inc_u32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x0e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_inc_u32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x0e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_inc_u32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x0e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_inc_u32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x0e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_inc_u32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_inc_u32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_inc_u32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_inc_u32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_dec_u32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x10,0xd8,0x00,0x01,0x00,0x00]
-
-ds_dec_u32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x10,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_dec_u32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x10,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_dec_u32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x10,0xd8,0xff,0x01,0x00,0x00]
-
-ds_dec_u32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x10,0xd8,0x00,0x01,0x00,0x00]
-
-ds_dec_u32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x10,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_dec_u32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x10,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_dec_u32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x10,0xd8,0xff,0x01,0x00,0x00]
-
-ds_dec_u32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x10,0xd8,0x00,0x01,0x00,0x00]
-
-ds_dec_u32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x10,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_dec_u32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x10,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_dec_u32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x10,0xd8,0xff,0x01,0x00,0x00]
-
-ds_dec_u32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xd8,0x00,0x01,0x00,0x00]
-
-ds_dec_u32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_dec_u32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_dec_u32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xd8,0xff,0x01,0x00,0x00]
-
-ds_dec_u32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x12,0xd8,0x00,0x01,0x00,0x00]
-
-ds_dec_u32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x12,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_dec_u32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x12,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_dec_u32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x12,0xd8,0xff,0x01,0x00,0x00]
-
-ds_dec_u32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x12,0xd8,0x00,0x01,0x00,0x00]
-
-ds_dec_u32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x12,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_dec_u32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x12,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_dec_u32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x12,0xd8,0xff,0x01,0x00,0x00]
-
-ds_dec_u32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x12,0xd8,0x00,0x01,0x00,0x00]
-
-ds_dec_u32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x12,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_dec_u32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x12,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_dec_u32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x12,0xd8,0xff,0x01,0x00,0x00]
-
-ds_dec_u32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x12,0xd8,0x00,0x01,0x00,0x00]
-
-ds_dec_u32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x12,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_dec_u32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x12,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_dec_u32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x12,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_i32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x14,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_i32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x14,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_i32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x14,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_i32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x14,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_i32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x14,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_i32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x14,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_i32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x14,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_i32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x14,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_i32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x14,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_i32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x14,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_i32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x14,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_i32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x14,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_i32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_i32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_i32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_i32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_i32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x16,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_i32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x16,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_i32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x16,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_i32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x16,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_i32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x16,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_i32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x16,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_i32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x16,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_i32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x16,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_i32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x16,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_i32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x16,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_i32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x16,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_i32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x16,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_i32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x16,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_i32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x16,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_i32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x16,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_i32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x16,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_i32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x18,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_i32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x18,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_i32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x18,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_i32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x18,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_i32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x18,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_i32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x18,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_i32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x18,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_i32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x18,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_i32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x18,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_i32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x18,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_i32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x18,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_i32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x18,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_i32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_i32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_i32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_i32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_i32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_i32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_i32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_i32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_i32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_i32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_i32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_i32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_i32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x1a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_i32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x1a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_i32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x1a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_i32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x1a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_i32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_i32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_i32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_i32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_u32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_u32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_u32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_u32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_u32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_u32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_u32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_u32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_u32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x1c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_u32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x1c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_u32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x1c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_u32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x1c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_u32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_u32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_u32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_u32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_u32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_u32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_u32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_u32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_u32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_u32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_u32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_u32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_u32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x1e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_u32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x1e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_u32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x1e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_u32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x1e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_u32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_u32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_u32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_u32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_u32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x20,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_u32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x20,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_u32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x20,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_u32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x20,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_u32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x20,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_u32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x20,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_u32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x20,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_u32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x20,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_u32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x20,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_u32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x20,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_u32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x20,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_u32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x20,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_u32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_u32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_u32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_u32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_u32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x22,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_u32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x22,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_u32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x22,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_u32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x22,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_u32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x22,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_u32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x22,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_u32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x22,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_u32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x22,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_u32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x22,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_u32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x22,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_u32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x22,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_u32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x22,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_u32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x22,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_u32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x22,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_u32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x22,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_u32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x22,0xd8,0xff,0x01,0x00,0x00]
-
-ds_and_b32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x24,0xd8,0x00,0x01,0x00,0x00]
-
-ds_and_b32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x24,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_and_b32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x24,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_and_b32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x24,0xd8,0xff,0x01,0x00,0x00]
-
-ds_and_b32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x24,0xd8,0x00,0x01,0x00,0x00]
-
-ds_and_b32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x24,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_and_b32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x24,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_and_b32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x24,0xd8,0xff,0x01,0x00,0x00]
-
-ds_and_b32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x24,0xd8,0x00,0x01,0x00,0x00]
-
-ds_and_b32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x24,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_and_b32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x24,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_and_b32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x24,0xd8,0xff,0x01,0x00,0x00]
-
-ds_and_b32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xd8,0x00,0x01,0x00,0x00]
-
-ds_and_b32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_and_b32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_and_b32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xd8,0xff,0x01,0x00,0x00]
-
-ds_and_b32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x26,0xd8,0x00,0x01,0x00,0x00]
-
-ds_and_b32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x26,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_and_b32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x26,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_and_b32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x26,0xd8,0xff,0x01,0x00,0x00]
-
-ds_and_b32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x26,0xd8,0x00,0x01,0x00,0x00]
-
-ds_and_b32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x26,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_and_b32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x26,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_and_b32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x26,0xd8,0xff,0x01,0x00,0x00]
-
-ds_and_b32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x26,0xd8,0x00,0x01,0x00,0x00]
-
-ds_and_b32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x26,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_and_b32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x26,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_and_b32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x26,0xd8,0xff,0x01,0x00,0x00]
-
-ds_and_b32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x26,0xd8,0x00,0x01,0x00,0x00]
-
-ds_and_b32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x26,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_and_b32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x26,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_and_b32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x26,0xd8,0xff,0x01,0x00,0x00]
-
-ds_or_b32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x28,0xd8,0x00,0x01,0x00,0x00]
-
-ds_or_b32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x28,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_or_b32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x28,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_or_b32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x28,0xd8,0xff,0x01,0x00,0x00]
-
-ds_or_b32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x28,0xd8,0x00,0x01,0x00,0x00]
-
-ds_or_b32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x28,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_or_b32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x28,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_or_b32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x28,0xd8,0xff,0x01,0x00,0x00]
-
-ds_or_b32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x28,0xd8,0x00,0x01,0x00,0x00]
-
-ds_or_b32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x28,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_or_b32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x28,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_or_b32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x28,0xd8,0xff,0x01,0x00,0x00]
-
-ds_or_b32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xd8,0x00,0x01,0x00,0x00]
-
-ds_or_b32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_or_b32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_or_b32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xd8,0xff,0x01,0x00,0x00]
-
-ds_or_b32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_or_b32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_or_b32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_or_b32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_or_b32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_or_b32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_or_b32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_or_b32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_or_b32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x2a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_or_b32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x2a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_or_b32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x2a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_or_b32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x2a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_or_b32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_or_b32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_or_b32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_or_b32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_xor_b32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_xor_b32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_xor_b32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_xor_b32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_xor_b32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_xor_b32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_xor_b32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_xor_b32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_xor_b32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x2c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_xor_b32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x2c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_xor_b32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x2c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_xor_b32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x2c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_xor_b32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_xor_b32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_xor_b32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_xor_b32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_xor_b32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_xor_b32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_xor_b32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_xor_b32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_xor_b32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_xor_b32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_xor_b32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_xor_b32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_xor_b32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x2e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_xor_b32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x2e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_xor_b32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x2e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_xor_b32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x2e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_xor_b32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_xor_b32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_xor_b32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_xor_b32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_mskor_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0x00,0x01,0x02,0x00]
-
-ds_mskor_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_mskor_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_mskor_b32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0x00,0x01,0x02,0x00]
-
-ds_mskor_b32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_mskor_b32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_mskor_b32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x30,0xd8,0x00,0x01,0x02,0x00]
-
-ds_mskor_b32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x30,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x30,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x30,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_mskor_b32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x30,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_mskor_b32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x30,0xd8,0x00,0x01,0x02,0x00]
-
-ds_mskor_b32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x30,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x30,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x30,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_mskor_b32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x30,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_mskor_b32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0x00,0x01,0x02,0x00]
-
-ds_mskor_b32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_mskor_b32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_mskor_b32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0x00,0x01,0x02,0x00]
-
-ds_mskor_b32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_mskor_b32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_mskor_b32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x32,0xd8,0x00,0x01,0x02,0x00]
-
-ds_mskor_b32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x32,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x32,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x32,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_mskor_b32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x32,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_mskor_b32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x32,0xd8,0x00,0x01,0x02,0x00]
-
-ds_mskor_b32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x32,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x32,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_mskor_b32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x32,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_mskor_b32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x32,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write_b32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x34,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x34,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x34,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x34,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x34,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x34,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x34,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x34,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x34,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x34,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x34,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x34,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x36,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x36,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x36,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x36,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x36,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x36,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x36,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x36,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x36,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x36,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x36,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x36,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x36,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x36,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x36,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x36,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write2_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x38,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x38,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x38,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x38,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x38,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x38,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x38,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x38,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x38,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x38,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x38,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x38,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x38,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x38,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x38,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x38,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x38,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x38,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x38,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x38,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2_b32 v0, v1, v2 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2_b32 v255, v254, v253 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2_b32 v0, v254, v253 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2_b32 v255, v1, v253 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2_b32 v255, v254, v2 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:0 offset1:123
-// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:123 offset1:0
-// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:64 offset1:123
-// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:123 offset1:64
-// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:64 offset1:255
-// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:255 offset1:64
-// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:255 offset1:255
-// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:0 offset1:123 gds
-// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:123 offset1:0 gds
-// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:64 offset1:123 gds
-// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:123 offset1:64 gds
-// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:64 offset1:255 gds
-// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:255 offset1:64 gds
-// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_write2st64_b32 v0, v1, v2 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0x00,0x01,0x02,0x00]
-
-ds_write2st64_b32 v255, v254, v253 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v0, v254, v253 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_write2st64_b32 v255, v1, v253 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_write2st64_b32 v255, v254, v2 offset0:255 offset1:255 gds
-// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_b32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_b32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_b32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_b32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x40,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_b32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x40,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x40,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x40,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_b32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x40,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_b32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x40,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_b32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x40,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x40,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x40,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_b32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x40,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_b32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_b32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_b32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_b32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_b32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_b32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_b32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x42,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_b32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x42,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x42,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x42,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_b32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x42,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_b32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x42,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_b32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x42,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x42,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_b32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x42,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_b32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x42,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_f32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_f32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_f32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_f32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_f32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_f32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_f32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x44,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_f32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x44,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x44,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x44,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_f32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x44,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_f32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x44,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_f32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x44,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x44,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x44,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_f32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x44,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_f32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_f32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_f32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_f32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_f32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_f32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_f32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x46,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_f32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x46,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x46,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x46,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_f32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x46,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_cmpst_f32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x46,0xd8,0x00,0x01,0x02,0x00]
-
-ds_cmpst_f32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x46,0xd8,0xff,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x46,0xd8,0x00,0xfe,0xfd,0x00]
-
-ds_cmpst_f32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x46,0xd8,0xff,0x01,0xfd,0x00]
-
-ds_cmpst_f32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x46,0xd8,0xff,0xfe,0x02,0x00]
-
-ds_min_f32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x48,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_f32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x48,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_f32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x48,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_f32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x48,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_f32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x48,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_f32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x48,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_f32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x48,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_f32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x48,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_f32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x48,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_f32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x48,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_f32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x48,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_f32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x48,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_f32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_f32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_f32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_f32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_f32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_f32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_f32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_f32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_f32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_f32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_f32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_f32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_f32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x4a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_f32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x4a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_f32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x4a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_f32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x4a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_min_f32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_min_f32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_min_f32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_min_f32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_f32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_f32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_f32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_f32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_f32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_f32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_f32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_f32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_f32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x4c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_f32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x4c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_f32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x4c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_f32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x4c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_f32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_f32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_f32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_f32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_f32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_f32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_f32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_f32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_f32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_f32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_f32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_f32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_f32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x4e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_f32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x4e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_f32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x4e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_f32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x4e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_max_f32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_max_f32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_max_f32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_max_f32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_nop
-// GFX10: encoding: [0x00,0x00,0x50,0xd8,0x00,0x00,0x00,0x00]
-
-ds_add_f32 v0, v1
-// GFX10: encoding: [0x00,0x00,0x54,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_f32 v255, v254
-// GFX10: encoding: [0x00,0x00,0x54,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_f32 v0, v254
-// GFX10: encoding: [0x00,0x00,0x54,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_f32 v255, v1
-// GFX10: encoding: [0x00,0x00,0x54,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_f32 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_f32 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_f32 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_f32 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_f32 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x54,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_f32 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x54,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_f32 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x54,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_f32 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x54,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_f32 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_f32 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_f32 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_f32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_f32 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_f32 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_f32 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_f32 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_f32 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_f32 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_f32 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_f32 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_f32 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x56,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_f32 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x56,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_f32 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x56,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_f32 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x56,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_f32 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xd8,0x00,0x01,0x00,0x00]
-
-ds_add_f32 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_add_f32 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_add_f32 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xd8,0xff,0x01,0x00,0x00]
-
-ds_gws_sema_release_all gds
-// GFX10: encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x62,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_init v0 gds
-// GFX10: encoding: [0x00,0x00,0x66,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_init v255 gds
-// GFX10: encoding: [0x00,0x00,0x66,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_init v0 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x66,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_init v255 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x66,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_init v0 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x66,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_init v255 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x66,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_init v0 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x66,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_init v255 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x66,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_sema_v gds
-// GFX10: encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x6a,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x6a,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_br v0 gds
-// GFX10: encoding: [0x00,0x00,0x6e,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_br v255 gds
-// GFX10: encoding: [0x00,0x00,0x6e,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_sema_br v0 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x6e,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_br v255 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x6e,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_sema_br v0 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x6e,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_br v255 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x6e,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_sema_br v0 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x6e,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_br v255 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_sema_p gds
-// GFX10: encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x72,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_barrier v0 gds
-// GFX10: encoding: [0x00,0x00,0x76,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_barrier v255 gds
-// GFX10: encoding: [0x00,0x00,0x76,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_barrier v0 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x76,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_barrier v255 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x76,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_barrier v0 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x76,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_barrier v255 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x76,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_barrier v0 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x76,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_barrier v255 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x76,0xd8,0xff,0x00,0x00,0x00]
-
-ds_write_b8 v0, v1
-// GFX10: encoding: [0x00,0x00,0x78,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b8 v255, v254
-// GFX10: encoding: [0x00,0x00,0x78,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b8 v0, v254
-// GFX10: encoding: [0x00,0x00,0x78,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b8 v255, v1
-// GFX10: encoding: [0x00,0x00,0x78,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b8 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x78,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b8 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x78,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b8 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x78,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b8 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x78,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b8 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x78,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b8 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x78,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b8 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x78,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b8 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x78,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b8 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x78,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b8 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x78,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b8 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x78,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b8 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x78,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b8 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b8 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b8 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b8 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b8 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b8 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b8 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b8 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b8 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x7a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b8 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x7a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b8 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x7a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b8 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x7a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b8 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7a,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b8 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7a,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b8 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7a,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b8 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7a,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b16 v0, v1
-// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b16 v255, v254
-// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b16 v0, v254
-// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b16 v255, v1
-// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b16 v0, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b16 v255, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b16 v0, v254 offset:0
-// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b16 v255, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b16 v0, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x7c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b16 v255, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x7c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b16 v0, v254 offset:4660
-// GFX10: encoding: [0x34,0x12,0x7c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b16 v255, v1 offset:4660
-// GFX10: encoding: [0x34,0x12,0x7c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b16 v0, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x7c,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b16 v255, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x7c,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b16 v0, v254 offset:65535
-// GFX10: encoding: [0xff,0xff,0x7c,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b16 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x7c,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b16 v0, v1 gds
-// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b16 v255, v254 gds
-// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b16 v0, v254 gds
-// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b16 v255, v1 gds
-// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b16 v0, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b16 v255, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b16 v0, v254 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b16 v255, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b16 v0, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x7e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b16 v255, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x7e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b16 v0, v254 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x7e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b16 v255, v1 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x7e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_write_b16 v0, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7e,0xd8,0x00,0x01,0x00,0x00]
-
-ds_write_b16 v255, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7e,0xd8,0xff,0xfe,0x00,0x00]
-
-ds_write_b16 v0, v254 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7e,0xd8,0x00,0xfe,0x00,0x00]
-
-ds_write_b16 v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7e,0xd8,0xff,0x01,0x00,0x00]
-
-ds_add_rtn_u32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_u32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_u32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x80,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x80,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_u32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x80,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x80,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_u32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_u32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_u32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x82,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x82,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_u32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x82,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x82,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x82,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x82,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_u32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x82,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_u32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x82,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x84,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x84,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x84,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x84,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x86,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x86,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x86,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x86,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x86,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x86,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_sub_rtn_u32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x86,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_sub_rtn_u32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x86,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x88,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x88,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x88,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x88,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_rsub_rtn_u32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_rsub_rtn_u32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_inc_rtn_u32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_inc_rtn_u32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x90,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x90,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x90,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x90,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x92,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x92,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x92,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x92,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x92,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x92,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_dec_rtn_u32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x92,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_dec_rtn_u32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x92,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_i32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_i32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_i32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_i32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_i32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x94,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x94,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_i32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x94,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x94,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_i32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_i32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_i32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_i32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_i32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_i32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_i32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x96,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x96,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_i32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x96,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x96,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_i32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x96,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x96,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_i32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x96,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_i32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x96,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_i32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_i32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_i32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_i32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x98,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_i32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x98,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x98,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_i32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x98,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x98,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_i32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_i32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_i32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_i32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_i32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_i32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_i32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_i32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_i32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_i32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_i32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_u32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_u32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_u32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_u32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_u32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_u32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_u32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_u32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_u32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_u32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_u32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_u32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_u32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_u32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_rtn_u32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_min_rtn_u32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_min_rtn_u32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_u32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_u32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_u32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_u32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_u32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_u32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_u32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_u32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_u32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_u32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_u32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_u32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_u32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_u32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_rtn_u32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_max_rtn_u32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_max_rtn_u32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_rtn_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_and_rtn_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_rtn_b32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_and_rtn_b32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_rtn_b32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_and_rtn_b32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_rtn_b32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_and_rtn_b32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_rtn_b32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_and_rtn_b32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_rtn_b32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_and_rtn_b32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_rtn_b32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_and_rtn_b32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_rtn_b32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_and_rtn_b32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_and_rtn_b32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_rtn_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_or_rtn_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_rtn_b32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_or_rtn_b32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_rtn_b32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_or_rtn_b32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_rtn_b32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_or_rtn_b32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_rtn_b32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_or_rtn_b32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_rtn_b32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_or_rtn_b32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_rtn_b32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_or_rtn_b32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_rtn_b32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_or_rtn_b32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_or_rtn_b32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xac,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xac,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xac,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xac,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xac,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xac,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xac,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xac,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xac,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xac,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xae,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xae,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xae,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xae,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xae,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xae,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xae,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xae,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_xor_rtn_b32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xae,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_xor_rtn_b32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xae,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_mskor_rtn_b32 v0, v1, v2, v3
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_rtn_b32 v255, v254, v253, v252
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v0, v254, v253, v252
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0xfc,0x00]
-
-ds_mskor_rtn_b32 v255, v1, v253, v252
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0x01,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v2, v252
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0x02,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v253, v3
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0x03,0xff]
-
-ds_mskor_rtn_b32 v0, v1, v2, v3 offset:0
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_rtn_b32 v255, v254, v253, v252 offset:0
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v0, v254, v253, v252 offset:0
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0xfc,0x00]
-
-ds_mskor_rtn_b32 v255, v1, v253, v252 offset:0
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0x01,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v2, v252 offset:0
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0x02,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v253, v3 offset:0
-// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0x03,0xff]
-
-ds_mskor_rtn_b32 v0, v1, v2, v3 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_rtn_b32 v255, v254, v253, v252 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0xfe,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v0, v254, v253, v252 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0xfe,0xfd,0xfc,0x00]
-
-ds_mskor_rtn_b32 v255, v1, v253, v252 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0x01,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v2, v252 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0xfe,0x02,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v253, v3 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0xfe,0xfd,0x03,0xff]
-
-ds_mskor_rtn_b32 v0, v1, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_rtn_b32 v255, v254, v253, v252 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0xfe,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v0, v254, v253, v252 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0xfe,0xfd,0xfc,0x00]
-
-ds_mskor_rtn_b32 v255, v1, v253, v252 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0x01,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v2, v252 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0xfe,0x02,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v253, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0xfe,0xfd,0x03,0xff]
-
-ds_mskor_rtn_b32 v0, v1, v2, v3 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_rtn_b32 v255, v254, v253, v252 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v0, v254, v253, v252 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0xfc,0x00]
-
-ds_mskor_rtn_b32 v255, v1, v253, v252 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0x01,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v2, v252 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0x02,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v253, v3 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0x03,0xff]
-
-ds_mskor_rtn_b32 v0, v1, v2, v3 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_rtn_b32 v255, v254, v253, v252 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v0, v254, v253, v252 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0xfc,0x00]
-
-ds_mskor_rtn_b32 v255, v1, v253, v252 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0x01,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v2, v252 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0x02,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v253, v3 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0x03,0xff]
-
-ds_mskor_rtn_b32 v0, v1, v2, v3 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_rtn_b32 v255, v254, v253, v252 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0xfe,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v0, v254, v253, v252 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0xfe,0xfd,0xfc,0x00]
-
-ds_mskor_rtn_b32 v255, v1, v253, v252 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0x01,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v2, v252 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0xfe,0x02,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v253, v3 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0xfe,0xfd,0x03,0xff]
-
-ds_mskor_rtn_b32 v0, v1, v2, v3 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_rtn_b32 v255, v254, v253, v252 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0xfe,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v0, v254, v253, v252 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0xfe,0xfd,0xfc,0x00]
-
-ds_mskor_rtn_b32 v255, v1, v253, v252 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0x01,0xfd,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v2, v252 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0xfe,0x02,0xfc,0xff]
-
-ds_mskor_rtn_b32 v255, v254, v253, v3 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0xfe,0xfd,0x03,0xff]
-
-ds_wrxchg_rtn_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0xfe,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0xfe,0xfd,0x00,0x00]
-
-ds_wrxchg_rtn_b32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0x01,0xfd,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0xfe,0x02,0x00,0xff]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_wrxchg2_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset1:255
-// GFX10: encoding: [0x00,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127
-// GFX10: encoding: [0x7f,0x00,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0xba,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset1:255
-// GFX10: encoding: [0x00,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127
-// GFX10: encoding: [0x7f,0x00,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0xbe,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v255, v1, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x03,0xff]
-
-ds_cmpst_rtn_b32 v5, v255, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v255, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0x01,0xff,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0x01,0x02,0xff,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:0
-// GFX10: encoding: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:4
-// GFX10: encoding: [0x04,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v255, v1, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x03,0xff]
-
-ds_cmpst_rtn_f32 v5, v255, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v255, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0x01,0xff,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0x01,0x02,0xff,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:0
-// GFX10: encoding: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:4
-// GFX10: encoding: [0x04,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x03,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v255, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_f32 v5, v255, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2
-// GFX10: encoding: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:4
-// GFX10: encoding: [0x04,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v255, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_f32 v5, v255, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2
-// GFX10: encoding: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:4
-// GFX10: encoding: [0x04,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
-
-ds_wrap_rtn_b32 v5, v255, v2, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v255, v3 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:0
-// GFX10: encoding: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:4
-// GFX10: encoding: [0x04,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_swizzle_b32 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
-
-ds_swizzle_b32 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1
-// GFX10: encoding: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd8,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_b32 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd8,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1
-// GFX10: encoding: [0x00,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xda,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xdc,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read2_b32 v[5:6], v255 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xdc,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset1:255
-// GFX10: encoding: [0x00,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127
-// GFX10: encoding: [0x7f,0x00,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0xde,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xe0,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read2st64_b32 v[5:6], v255 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xe0,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset1:255
-// GFX10: encoding: [0x00,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127
-// GFX10: encoding: [0x7f,0x00,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0xe2,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xe4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xe4,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i8 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xe4,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1
-// GFX10: encoding: [0x00,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xe6,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xe8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xe8,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u8 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xe8,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1
-// GFX10: encoding: [0x00,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xea,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i16 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xec,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1
-// GFX10: encoding: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf0,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u16 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf0,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1
-// GFX10: encoding: [0x00,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xf2,0xd8,0x01,0x00,0x00,0x05]
-
-ds_consume v5 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf4,0xd8,0x00,0x00,0x00,0x05]
-
-ds_consume v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf4,0xd8,0x00,0x00,0x00,0xff]
-
-ds_consume v5
-// GFX10: encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:0
-// GFX10: encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:4
-// GFX10: encoding: [0x04,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xf6,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf8,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf8,0xd8,0x00,0x00,0x00,0xff]
-
-ds_append v5
-// GFX10: encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:0
-// GFX10: encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:4
-// GFX10: encoding: [0x04,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xfa,0xd8,0x00,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xfe,0xd8,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v255, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xfe,0xd8,0x01,0x00,0x00,0xff]
-
-ds_ordered_count v5, v255 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xfe,0xd8,0xff,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 gds
-// GFX10: encoding: [0x00,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:4 gds
-// GFX10: encoding: [0x04,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
-
-ds_add_u64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xd9,0xff,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_add_u64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x02,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x06,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xd9,0xff,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0a,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xd9,0xff,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0e,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xd9,0xff,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x12,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xd9,0xff,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_min_i64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x16,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xd9,0xff,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_max_i64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1a,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xd9,0xff,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_min_u64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1e,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xd9,0xff,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_max_u64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x22,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xd9,0xff,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_and_b64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x26,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xd9,0xff,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_or_b64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2a,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xd9,0xff,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2e,0xd9,0x01,0x02,0x00,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x30,0xd9,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v255, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x30,0xd9,0xff,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[254:255], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x30,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x30,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4]
-// GFX10: encoding: [0x00,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:0
-// GFX10: encoding: [0x00,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:4
-// GFX10: encoding: [0x04,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x32,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write_b64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xd9,0xff,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_write_b64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x36,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0x38,0xd9,0xff,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0x38,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0x38,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
-// GFX10: encoding: [0x00,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
-// GFX10: encoding: [0x7f,0x00,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0x3a,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0x3c,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0x3c,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset1:255
-// GFX10: encoding: [0x00,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127
-// GFX10: encoding: [0x7f,0x00,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0x3e,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x40,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v255, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x40,0xd9,0xff,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[254:255], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x40,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x40,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4]
-// GFX10: encoding: [0x00,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:0
-// GFX10: encoding: [0x00,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:4
-// GFX10: encoding: [0x04,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x42,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x44,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v255, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x44,0xd9,0xff,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[254:255], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x44,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x44,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4]
-// GFX10: encoding: [0x00,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:0
-// GFX10: encoding: [0x00,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:4
-// GFX10: encoding: [0x04,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x46,0xd9,0x01,0x02,0x03,0x00]
-
-ds_min_f64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xd9,0xff,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_min_f64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4a,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xd9,0xff,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_max_f64 v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4e,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_f32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_f32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_f32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_f32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_f32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_f32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_f32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x54,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_f32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x54,0xd9,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x54,0xd9,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_f32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0x54,0xd9,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0x54,0xd9,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_f32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_f32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xd9,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xd9,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_f32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xd9,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xd9,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_f32 v0, v1, v2 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_f32 v255, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v0, v254, v253 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_f32 v255, v1, v253 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v255, v254, v2 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_f32 v0, v1, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_f32 v255, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v0, v254, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_f32 v255, v1, v253 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v255, v254, v2 offset:0 gds
-// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_f32 v0, v1, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x56,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_f32 v255, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x56,0xd9,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v0, v254, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x56,0xd9,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_f32 v255, v1, v253 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x56,0xd9,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v255, v254, v2 offset:4660 gds
-// GFX10: encoding: [0x34,0x12,0x56,0xd9,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_f32 v0, v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_f32 v255, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xd9,0xfe,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v0, v254, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xd9,0xfe,0xfd,0x00,0x00]
-
-ds_add_rtn_f32 v255, v1, v253 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xd9,0x01,0xfd,0x00,0xff]
-
-ds_add_rtn_f32 v255, v254, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xd9,0xfe,0x02,0x00,0xff]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xd9,0xff,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x82,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_sub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xd9,0xff,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x86,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_rsub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xd9,0xff,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8a,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_inc_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xd9,0xff,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8e,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_dec_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xd9,0xff,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x92,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_i64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xd9,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x96,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_i64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xd9,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9a,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xd9,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9e,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa0,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa0,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa0,0xd9,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa0,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa2,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa4,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_and_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa4,0xd9,0xff,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa4,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xa6,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa8,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_or_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa8,0xd9,0xff,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xa8,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xaa,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xac,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xac,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_xor_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xac,0xd9,0xff,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xac,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xae,0xd9,0x01,0x02,0x00,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0x01,0x02,0x03,0xfe]
-
-ds_mskor_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0xff,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// GFX10: encoding: [0x00,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// GFX10: encoding: [0x04,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb2,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xb4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xb4,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_wrxchg_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xb4,0xd9,0xff,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xb4,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xb6,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0x03,0xfc]
-
-ds_wrxchg2_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
-// GFX10: encoding: [0x00,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
-// GFX10: encoding: [0x7f,0x00,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0xba,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0x03,0xfc]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
-// GFX10: encoding: [0x00,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
-// GFX10: encoding: [0x7f,0x00,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0xbe,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0x01,0x02,0x03,0xfe]
-
-ds_cmpst_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
-// GFX10: encoding: [0x00,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// GFX10: encoding: [0x00,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// GFX10: encoding: [0x04,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xc2,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0x01,0x02,0x03,0xfe]
-
-ds_cmpst_rtn_f64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4]
-// GFX10: encoding: [0x00,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// GFX10: encoding: [0x00,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// GFX10: encoding: [0x04,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xc6,0xd9,0x01,0x02,0x03,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_f64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xd9,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xca,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_f64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xd9,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xce,0xd9,0x01,0x02,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd8,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[254:255], v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd8,0xd9,0x01,0x00,0x00,0xfe]
-
-ds_read_b64 v[5:6], v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xd8,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1
-// GFX10: encoding: [0x00,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xda,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xdc,0xd9,0x01,0x00,0x00,0xfc]
-
-ds_read2_b64 v[5:8], v255 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xdc,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset1:255
-// GFX10: encoding: [0x00,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127
-// GFX10: encoding: [0x7f,0x00,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0xde,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xe0,0xd9,0x01,0x00,0x00,0xfc]
-
-ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255
-// GFX10: encoding: [0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset1:255
-// GFX10: encoding: [0x00,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:0 offset1:255
-// GFX10: encoding: [0x00,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:16 offset1:255
-// GFX10: encoding: [0x10,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127
-// GFX10: encoding: [0x7f,0x00,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:0
-// GFX10: encoding: [0x7f,0x00,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:1
-// GFX10: encoding: [0x7f,0x01,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255 gds
-// GFX10: encoding: [0x7f,0xff,0xe2,0xd9,0x01,0x00,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xf8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xf8,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_condxchg32_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// GFX10: encoding: [0xff,0xff,0xf8,0xd9,0xff,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0xf8,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// GFX10: encoding: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// GFX10: encoding: [0x04,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xfa,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_src2_u32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xda,0xff,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1
-// GFX10: encoding: [0x00,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x02,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xda,0xff,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1
-// GFX10: encoding: [0x00,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x06,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xda,0xff,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1
-// GFX10: encoding: [0x00,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0a,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xda,0xff,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1
-// GFX10: encoding: [0x00,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0e,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xda,0xff,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1
-// GFX10: encoding: [0x00,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x12,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xda,0xff,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1
-// GFX10: encoding: [0x00,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x16,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xda,0xff,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1
-// GFX10: encoding: [0x00,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1a,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xda,0xff,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1
-// GFX10: encoding: [0x00,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1e,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xda,0xff,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1
-// GFX10: encoding: [0x00,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x22,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xda,0xff,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1
-// GFX10: encoding: [0x00,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x26,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xda,0xff,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1
-// GFX10: encoding: [0x00,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2a,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xda,0xff,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1
-// GFX10: encoding: [0x00,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2e,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xda,0xff,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1
-// GFX10: encoding: [0x00,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x36,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xda,0xff,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1
-// GFX10: encoding: [0x00,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4a,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xda,0xff,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1
-// GFX10: encoding: [0x00,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4e,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_f32 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_f32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x54,0xda,0xff,0x00,0x00,0x00]
-
-ds_add_src2_f32 v1
-// GFX10: encoding: [0x00,0x00,0x54,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_f32 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x54,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_f32 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x54,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_f32 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x56,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xda,0x01,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v255, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xda,0xff,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x80,0xda,0x01,0xff,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2
-// GFX10: encoding: [0x00,0x00,0x80,0xda,0x01,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x80,0xda,0x01,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2 offset:4
-// GFX10: encoding: [0x04,0x00,0x80,0xda,0x01,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x82,0xda,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xda,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v255, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xda,0xff,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x84,0xda,0x01,0xff,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2
-// GFX10: encoding: [0x00,0x00,0x84,0xda,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0x84,0xda,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2 offset:4
-// GFX10: encoding: [0x04,0x00,0x84,0xda,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x86,0xda,0x01,0x02,0x00,0x00]
-
-ds_read_u8_d16 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xda,0x01,0x00,0x00,0xff]
-
-ds_read_u8_d16 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x88,0xda,0xff,0x00,0x00,0x05]
-
-ds_read_u8_d16 v5, v1
-// GFX10: encoding: [0x00,0x00,0x88,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x88,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x88,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8a,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xda,0x01,0x00,0x00,0xff]
-
-ds_read_u8_d16_hi v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x8c,0xda,0xff,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1
-// GFX10: encoding: [0x00,0x00,0x8c,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x8c,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x8c,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x8e,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xda,0x01,0x00,0x00,0xff]
-
-ds_read_i8_d16 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x90,0xda,0xff,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1
-// GFX10: encoding: [0x00,0x00,0x90,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x90,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x90,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x92,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xda,0x01,0x00,0x00,0xff]
-
-ds_read_i8_d16_hi v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x94,0xda,0xff,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1
-// GFX10: encoding: [0x00,0x00,0x94,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x94,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x94,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x96,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xda,0x01,0x00,0x00,0xff]
-
-ds_read_u16_d16 v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x98,0xda,0xff,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1
-// GFX10: encoding: [0x00,0x00,0x98,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x98,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x98,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9a,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v255, v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xda,0x01,0x00,0x00,0xff]
-
-ds_read_u16_d16_hi v5, v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x9c,0xda,0xff,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1
-// GFX10: encoding: [0x00,0x00,0x9c,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x9c,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x9c,0xda,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x9e,0xda,0x01,0x00,0x00,0x05]
-
-ds_write_addtid_b32 v5 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
-
-ds_write_addtid_b32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0xff,0x00,0x00]
-
-ds_write_addtid_b32 v5
-// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
-
-ds_write_addtid_b32 v5 offset:0
-// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
-
-ds_write_addtid_b32 v5 offset:4
-// GFX10: encoding: [0x04,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
-
-ds_write_addtid_b32 v5 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xc2,0xda,0x00,0x05,0x00,0x00]
-
-ds_read_addtid_b32 v5 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
-
-ds_read_addtid_b32 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0xff]
-
-ds_read_addtid_b32 v5
-// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
-
-ds_read_addtid_b32 v5 offset:0
-// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
-
-ds_read_addtid_b32 v5 offset:4
-// GFX10: encoding: [0x04,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
-
-ds_read_addtid_b32 v5 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xc6,0xda,0x00,0x00,0x00,0x05]
-
-ds_permute_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0x02,0x00,0x00]
-
-ds_permute_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0xfd,0x00,0xff]
-
-ds_permute_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0xfd,0x00,0x00]
-
-ds_permute_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0xfd,0x00,0xff]
-
-ds_permute_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0x02,0x00,0xff]
-
-ds_permute_b32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0x02,0x00,0x00]
-
-ds_permute_b32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0xfd,0x00,0xff]
-
-ds_permute_b32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0xfd,0x00,0x00]
-
-ds_permute_b32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0xfd,0x00,0xff]
-
-ds_permute_b32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0x02,0x00,0xff]
-
-ds_permute_b32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xc8,0xda,0x01,0x02,0x00,0x00]
-
-ds_permute_b32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xc8,0xda,0xfe,0xfd,0x00,0xff]
-
-ds_permute_b32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xc8,0xda,0xfe,0xfd,0x00,0x00]
-
-ds_permute_b32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xc8,0xda,0x01,0xfd,0x00,0xff]
-
-ds_permute_b32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xc8,0xda,0xfe,0x02,0x00,0xff]
-
-ds_permute_b32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xda,0x01,0x02,0x00,0x00]
-
-ds_permute_b32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xda,0xfe,0xfd,0x00,0xff]
-
-ds_permute_b32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xda,0xfe,0xfd,0x00,0x00]
-
-ds_permute_b32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xda,0x01,0xfd,0x00,0xff]
-
-ds_permute_b32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xc8,0xda,0xfe,0x02,0x00,0xff]
-
-ds_bpermute_b32 v0, v1, v2
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0x01,0x02,0x00,0x00]
-
-ds_bpermute_b32 v255, v254, v253
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0xfd,0x00,0xff]
-
-ds_bpermute_b32 v0, v254, v253
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0xfd,0x00,0x00]
-
-ds_bpermute_b32 v255, v1, v253
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0x01,0xfd,0x00,0xff]
-
-ds_bpermute_b32 v255, v254, v2
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0x02,0x00,0xff]
-
-ds_bpermute_b32 v0, v1, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0x01,0x02,0x00,0x00]
-
-ds_bpermute_b32 v255, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0xfd,0x00,0xff]
-
-ds_bpermute_b32 v0, v254, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0xfd,0x00,0x00]
-
-ds_bpermute_b32 v255, v1, v253 offset:0
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0x01,0xfd,0x00,0xff]
-
-ds_bpermute_b32 v255, v254, v2 offset:0
-// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0x02,0x00,0xff]
-
-ds_bpermute_b32 v0, v1, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xcc,0xda,0x01,0x02,0x00,0x00]
-
-ds_bpermute_b32 v255, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xcc,0xda,0xfe,0xfd,0x00,0xff]
-
-ds_bpermute_b32 v0, v254, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xcc,0xda,0xfe,0xfd,0x00,0x00]
-
-ds_bpermute_b32 v255, v1, v253 offset:4660
-// GFX10: encoding: [0x34,0x12,0xcc,0xda,0x01,0xfd,0x00,0xff]
-
-ds_bpermute_b32 v255, v254, v2 offset:4660
-// GFX10: encoding: [0x34,0x12,0xcc,0xda,0xfe,0x02,0x00,0xff]
-
-ds_bpermute_b32 v0, v1, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xda,0x01,0x02,0x00,0x00]
-
-ds_bpermute_b32 v255, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xda,0xfe,0xfd,0x00,0xff]
-
-ds_bpermute_b32 v0, v254, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xda,0xfe,0xfd,0x00,0x00]
-
-ds_bpermute_b32 v255, v1, v253 offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xda,0x01,0xfd,0x00,0xff]
-
-ds_bpermute_b32 v255, v254, v2 offset:65535
-// GFX10: encoding: [0xff,0xff,0xcc,0xda,0xfe,0x02,0x00,0xff]
-
-ds_add_src2_u64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xdb,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x00,0xdb,0xff,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1
-// GFX10: encoding: [0x00,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x02,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x04,0xdb,0xff,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1
-// GFX10: encoding: [0x00,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x06,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x08,0xdb,0xff,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1
-// GFX10: encoding: [0x00,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0a,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x0c,0xdb,0xff,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1
-// GFX10: encoding: [0x00,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x0e,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x10,0xdb,0xff,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1
-// GFX10: encoding: [0x00,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x12,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x14,0xdb,0xff,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1
-// GFX10: encoding: [0x00,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x16,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x18,0xdb,0xff,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1
-// GFX10: encoding: [0x00,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1a,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x1c,0xdb,0xff,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1
-// GFX10: encoding: [0x00,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x1e,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x20,0xdb,0xff,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1
-// GFX10: encoding: [0x00,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x22,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x24,0xdb,0xff,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1
-// GFX10: encoding: [0x00,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x26,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x28,0xdb,0xff,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1
-// GFX10: encoding: [0x00,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2a,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x2c,0xdb,0xff,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1
-// GFX10: encoding: [0x00,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x2e,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x34,0xdb,0xff,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1
-// GFX10: encoding: [0x00,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x36,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x48,0xdb,0xff,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1
-// GFX10: encoding: [0x00,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4a,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0x4c,0xdb,0xff,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1
-// GFX10: encoding: [0x00,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:0
-// GFX10: encoding: [0x00,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:4
-// GFX10: encoding: [0x04,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x4e,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x78,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v255, v[2:4] offset:65535
-// GFX10: encoding: [0xff,0xff,0x78,0xdb,0xff,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[253:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x78,0xdb,0x01,0xfd,0x00,0x00]
-
-ds_write_b96 v1, v[2:4]
-// GFX10: encoding: [0x00,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:0
-// GFX10: encoding: [0x00,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:4
-// GFX10: encoding: [0x04,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7a,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:65535
-// GFX10: encoding: [0xff,0xff,0x7c,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v255, v[2:5] offset:65535
-// GFX10: encoding: [0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[252:255] offset:65535
-// GFX10: encoding: [0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00]
-
-ds_write_b128 v1, v[2:5]
-// GFX10: encoding: [0x00,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:0
-// GFX10: encoding: [0x00,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:4
-// GFX10: encoding: [0x04,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0x7e,0xdb,0x01,0x02,0x00,0x00]
-
-ds_read_b96 v[5:7], v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf8,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[253:255], v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf8,0xdb,0x01,0x00,0x00,0xfd]
-
-ds_read_b96 v[5:7], v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xf8,0xdb,0xff,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1
-// GFX10: encoding: [0x00,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xfa,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[252:255], v1 offset:65535
-// GFX10: encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc]
-
-ds_read_b128 v[5:8], v255 offset:65535
-// GFX10: encoding: [0xff,0xff,0xfc,0xdb,0xff,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1
-// GFX10: encoding: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:0
-// GFX10: encoding: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:4
-// GFX10: encoding: [0x04,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:65535 gds
-// GFX10: encoding: [0xff,0xff,0xfe,0xdb,0x01,0x00,0x00,0x05]
-
-//===----------------------------------------------------------------------===//
-// ENC_FLAT.
-//===----------------------------------------------------------------------===//
-
-flat_load_ubyte v5, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x20,0xdc,0x01,0x00,0x7d,0x05]
-
-flat_load_sbyte v5, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x24,0xdc,0x01,0x00,0x7d,0x05]
-
-flat_load_ushort v5, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x28,0xdc,0x01,0x00,0x7d,0x05]
-
-flat_load_sshort v5, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x2c,0xdc,0x01,0x00,0x7d,0x05]
-
-flat_load_dword v5, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x30,0xdc,0x01,0x00,0x7d,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2]
-// GFX10: encoding: [0x00,0x00,0x34,0xdc,0x01,0x00,0x7d,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2]
-// GFX10: encoding: [0x00,0x00,0x3c,0xdc,0x01,0x00,0x7d,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2]
-// GFX10: encoding: [0x00,0x00,0x38,0xdc,0x01,0x00,0x7d,0x05]
-
-flat_store_byte v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0x60,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_store_short v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0x68,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_store_dword v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0x70,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x74,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4]
-// GFX10: encoding: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5]
-// GFX10: encoding: [0x00,0x00,0x78,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_swap v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xc0,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xc4,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_add v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xc8,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_sub v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xcc,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_smin v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_umin v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_smax v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_umax v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xe0,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_and v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xe4,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_or v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xe8,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_xor v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xec,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_inc v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xf0,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_dec v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xf4,0xdc,0x01,0x02,0x7d,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x40,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5]
-// GFX10: encoding: [0x00,0x00,0x44,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x48,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x4c,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x54,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x58,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x5c,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x60,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x64,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x68,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x6c,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x70,0xdd,0x01,0x02,0x7d,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x74,0xdd,0x01,0x02,0x7d,0x00]
-
-// Also see flat-gfx10.s, flat-global.s, flat-scratch-instructions.s.
-
-//===----------------------------------------------------------------------===//
-// ENC_MUBUF.
-//===----------------------------------------------------------------------===//
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_format_x v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_x v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_x v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_x v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_x v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x00,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xy v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x04,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0xfd,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x08,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0xfc,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x0c,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v255, off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_format_x v1, off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_x v1, off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_x v1, off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_x v1, off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_x v1, off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x10,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xy v[1:2], off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x14,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0xfd,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x18,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0xfc,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x1c,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ubyte v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_ubyte v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ubyte v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ubyte v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ubyte v5, off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ubyte v5, off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ubyte v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x20,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sbyte v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_sbyte v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sbyte v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sbyte v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sbyte v5, off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sbyte v5, off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sbyte v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x24,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ushort v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ushort v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_ushort v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ushort v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ushort v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ushort v5, off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ushort v5, off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x28,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sshort v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sshort v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_sshort v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sshort v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sshort v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sshort v5, off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sshort v5, off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sshort v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x2c,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_dword v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dword v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dword v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dword v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dword v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dword v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dword v5, off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dword v5, off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dword v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x30,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x34,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[253:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0xfd,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x3c,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[252:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0xfc,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x38,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v255, off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_byte v1, off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_byte v1, off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_byte v1, off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_byte v1, off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_byte v1, off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_byte v1, off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_byte v1, off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_byte v1, off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_byte v1, v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x60,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v255, off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_short v1, off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_short v1, off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_short v1, off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_short v1, off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_short v1, off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_short v1, off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_short v1, off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_short v1, off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_short v1, v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x68,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v255, off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_dword v1, off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dword v1, off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dword v1, off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dword v1, off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dword v1, off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dword v1, off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dword v1, off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dword v1, off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dword v1, v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x70,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[254:255], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x74,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[253:255], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0xfd,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x7c,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[252:255], off, s[12:15], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0xfc,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[16:19], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[96:99], s4 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], 0.5 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], -4.0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4
-// GFX10: encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:7
-// GFX10: encoding: [0x07,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 dlc
-// GFX10: encoding: [0xff,0x8f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc slc dlc
-// GFX10: encoding: [0xff,0xcf,0x78,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_swap v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_swap v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_swap v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_swap v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_swap v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xc0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xc0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xc0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xc0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xc0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xc4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xc4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xc4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xc4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xc4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_add v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_add v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_add v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_add v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_add v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_add v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xc8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xc8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xc8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xc8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xc8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_sub v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_sub v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_sub v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_sub v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_sub v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xcc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xcc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xcc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xcc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xcc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smin v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smin v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smin v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smin v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smin v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xd4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xd4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xd4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xd4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xd4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umin v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umin v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umin v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umin v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umin v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xd8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xd8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xd8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xd8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xd8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smax v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smax v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smax v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smax v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smax v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xdc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xdc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xdc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xdc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xdc,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umax v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umax v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umax v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umax v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umax v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xe0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xe0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xe0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xe0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xe0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_and v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_and v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_and v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_and v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_and v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_and v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xe4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xe4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xe4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xe4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xe4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_or v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_or v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_or v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_or v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_or v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_or v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xe8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xe8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xe8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xe8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xe8,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_xor v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_xor v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_xor v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_xor v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_xor v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xec,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xec,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xec,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xec,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xec,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_inc v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_inc v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_inc v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_inc v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_inc v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xf0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xf0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xf0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xf0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xf0,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v255, off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_atomic_dec v5, off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_atomic_dec v5, off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_dec v5, off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_atomic_dec v5, off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_dec v5, v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0xf4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0xf4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0xf4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0xf4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0xf4,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x40,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x40,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x40,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x40,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x40,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[252:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0xfc,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x44,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x44,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x44,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x44,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x44,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x48,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x48,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x48,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x48,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x48,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x4c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x4c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x4c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x4c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x4c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x54,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x54,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x54,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x54,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x54,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x58,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x58,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x58,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x58,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x58,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x5c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x5c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x5c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x5c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x5c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x60,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x60,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x60,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x60,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x60,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x64,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x64,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x64,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x64,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x64,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x68,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x68,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x68,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x68,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x68,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x6c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x6c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x6c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x6c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x6c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x70,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x70,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x70,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x70,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x70,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[254:255], off, s[8:11], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[12:15], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[96:99], s3 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s101 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], m0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], -1 offset:4095
-// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// GFX10: encoding: [0xff,0x2f,0x74,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// GFX10: encoding: [0xff,0x1f,0x74,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3
-// GFX10: encoding: [0x00,0x00,0x74,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:7
-// GFX10: encoding: [0x07,0x00,0x74,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// GFX10: encoding: [0xff,0x4f,0x74,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x42,0x03]
-
-buffer_gl0_inv
-// GFX10: encoding: [0x00,0x00,0xc4,0xe1,0x00,0x00,0x00,0x00]
-
-buffer_gl1_inv
-// GFX10: encoding: [0x00,0x00,0xc8,0xe1,0x00,0x00,0x00,0x00]
-
-//===----------------------------------------------------------------------===//
-// ENC_SMEM.
-//===----------------------------------------------------------------------===//
-
-s_load_dword s5, s[2:3], s0
-// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword s101, s[2:3], s0
-// GFX10: encoding: [0x41,0x19,0x00,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword vcc_lo, s[2:3], s0
-// GFX10: encoding: [0x81,0x1a,0x00,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword vcc_hi, s[2:3], s0
-// GFX10: encoding: [0xc1,0x1a,0x00,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[4:5], s0
-// GFX10: encoding: [0x42,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[100:101], s0
-// GFX10: encoding: [0x72,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, vcc, s0
-// GFX10: encoding: [0x75,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xca]
-
-s_load_dword s5, s[2:3], vcc_lo
-// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xd4]
-
-s_load_dword s5, s[2:3], vcc_hi
-// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xd6]
-
-s_load_dword s5, s[2:3], m0
-// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xf8]
-
-s_load_dword s5, s[2:3], 0x0
-// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa]
-
-s_load_dword s5, s[2:3], s0 glc
-// GFX10: encoding: [0x41,0x01,0x01,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], s0 dlc
-// GFX10: encoding: [0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], s0 glc dlc
-// GFX10: encoding: [0x41,0x41,0x01,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], 0x1234 glc dlc
-// GFX10: encoding: [0x41,0x41,0x01,0xf4,0x34,0x12,0x00,0xfa]
-
-s_load_dwordx2 s[10:11], s[2:3], s0
-// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[12:13], s[2:3], s0
-// GFX10: encoding: [0x01,0x03,0x04,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[100:101], s[2:3], s0
-// GFX10: encoding: [0x01,0x19,0x04,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 vcc, s[2:3], s0
-// GFX10: encoding: [0x81,0x1a,0x04,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[4:5], s0
-// GFX10: encoding: [0x82,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[100:101], s0
-// GFX10: encoding: [0xb2,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], vcc, s0
-// GFX10: encoding: [0xb5,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], s101
-// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xca]
-
-s_load_dwordx2 s[10:11], s[2:3], vcc_lo
-// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xd4]
-
-s_load_dwordx2 s[10:11], s[2:3], vcc_hi
-// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xd6]
-
-s_load_dwordx2 s[10:11], s[2:3], m0
-// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xf8]
-
-s_load_dwordx2 s[10:11], s[2:3], 0x0
-// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xfa]
-
-s_load_dwordx2 s[10:11], s[2:3], s0 glc
-// GFX10: encoding: [0x81,0x02,0x05,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], s0 dlc
-// GFX10: encoding: [0x81,0x42,0x04,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], s0 glc dlc
-// GFX10: encoding: [0x81,0x42,0x05,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], 0x1234 glc dlc
-// GFX10: encoding: [0x81,0x42,0x05,0xf4,0x34,0x12,0x00,0xfa]
-
-s_load_dwordx4 s[20:23], s[2:3], s0
-// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[24:27], s[2:3], s0
-// GFX10: encoding: [0x01,0x06,0x08,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[96:99], s[2:3], s0
-// GFX10: encoding: [0x01,0x18,0x08,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[4:5], s0
-// GFX10: encoding: [0x02,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[100:101], s0
-// GFX10: encoding: [0x32,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], vcc, s0
-// GFX10: encoding: [0x35,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], s101
-// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xca]
-
-s_load_dwordx4 s[20:23], s[2:3], vcc_lo
-// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xd4]
-
-s_load_dwordx4 s[20:23], s[2:3], vcc_hi
-// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xd6]
-
-s_load_dwordx4 s[20:23], s[2:3], m0
-// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xf8]
-
-s_load_dwordx4 s[20:23], s[2:3], 0x0
-// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xfa]
-
-s_load_dwordx4 s[20:23], s[2:3], s0 glc
-// GFX10: encoding: [0x01,0x05,0x09,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], s0 dlc
-// GFX10: encoding: [0x01,0x45,0x08,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], s0 glc dlc
-// GFX10: encoding: [0x01,0x45,0x09,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], 0x1234 glc dlc
-// GFX10: encoding: [0x01,0x45,0x09,0xf4,0x34,0x12,0x00,0xfa]
-
-s_load_dwordx8 s[20:27], s[2:3], s0
-// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[24:31], s[2:3], s0
-// GFX10: encoding: [0x01,0x06,0x0c,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[92:99], s[2:3], s0
-// GFX10: encoding: [0x01,0x17,0x0c,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[4:5], s0
-// GFX10: encoding: [0x02,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[100:101], s0
-// GFX10: encoding: [0x32,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], vcc, s0
-// GFX10: encoding: [0x35,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], s101
-// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xca]
-
-s_load_dwordx8 s[20:27], s[2:3], vcc_lo
-// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xd4]
-
-s_load_dwordx8 s[20:27], s[2:3], vcc_hi
-// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xd6]
-
-s_load_dwordx8 s[20:27], s[2:3], m0
-// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xf8]
-
-s_load_dwordx8 s[20:27], s[2:3], 0x0
-// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xfa]
-
-s_load_dwordx8 s[20:27], s[2:3], s0 glc
-// GFX10: encoding: [0x01,0x05,0x0d,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], s0 dlc
-// GFX10: encoding: [0x01,0x45,0x0c,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], s0 glc dlc
-// GFX10: encoding: [0x01,0x45,0x0d,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], 0x1234 glc dlc
-// GFX10: encoding: [0x01,0x45,0x0d,0xf4,0x34,0x12,0x00,0xfa]
-
-s_load_dwordx16 s[20:35], s[2:3], s0
-// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[24:39], s[2:3], s0
-// GFX10: encoding: [0x01,0x06,0x10,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[84:99], s[2:3], s0
-// GFX10: encoding: [0x01,0x15,0x10,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[4:5], s0
-// GFX10: encoding: [0x02,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[100:101], s0
-// GFX10: encoding: [0x32,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], vcc, s0
-// GFX10: encoding: [0x35,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], s101
-// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xca]
-
-s_load_dwordx16 s[20:35], s[2:3], vcc_lo
-// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xd4]
-
-s_load_dwordx16 s[20:35], s[2:3], vcc_hi
-// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xd6]
-
-s_load_dwordx16 s[20:35], s[2:3], m0
-// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xf8]
-
-s_load_dwordx16 s[20:35], s[2:3], 0x0
-// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xfa]
-
-s_load_dwordx16 s[20:35], s[2:3], s0 glc
-// GFX10: encoding: [0x01,0x05,0x11,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], s0 dlc
-// GFX10: encoding: [0x01,0x45,0x10,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], s0 glc dlc
-// GFX10: encoding: [0x01,0x45,0x11,0xf4,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], 0x1234 glc dlc
-// GFX10: encoding: [0x01,0x45,0x11,0xf4,0x34,0x12,0x00,0xfa]
-
-s_buffer_load_dword s5, s[4:7], s0
-// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s101, s[4:7], s0
-// GFX10: encoding: [0x42,0x19,0x20,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword vcc_lo, s[4:7], s0
-// GFX10: encoding: [0x82,0x1a,0x20,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword vcc_hi, s[4:7], s0
-// GFX10: encoding: [0xc2,0x1a,0x20,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[8:11], s0
-// GFX10: encoding: [0x44,0x01,0x20,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[96:99], s0
-// GFX10: encoding: [0x70,0x01,0x20,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], s101
-// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xca]
-
-s_buffer_load_dword s5, s[4:7], vcc_lo
-// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xd4]
-
-s_buffer_load_dword s5, s[4:7], vcc_hi
-// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xd6]
-
-s_buffer_load_dword s5, s[4:7], m0
-// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xf8]
-
-s_buffer_load_dword s5, s[4:7], 0x0
-// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xfa]
-
-s_buffer_load_dword s5, s[4:7], s0 glc
-// GFX10: encoding: [0x42,0x01,0x21,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], s0 dlc
-// GFX10: encoding: [0x42,0x41,0x20,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], s0 glc dlc
-// GFX10: encoding: [0x42,0x41,0x21,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], 0x1234 glc dlc
-// GFX10: encoding: [0x42,0x41,0x21,0xf4,0x34,0x12,0x00,0xfa]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s0
-// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[12:13], s[4:7], s0
-// GFX10: encoding: [0x02,0x03,0x24,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[100:101], s[4:7], s0
-// GFX10: encoding: [0x02,0x19,0x24,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 vcc, s[4:7], s0
-// GFX10: encoding: [0x82,0x1a,0x24,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[8:11], s0
-// GFX10: encoding: [0x84,0x02,0x24,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[96:99], s0
-// GFX10: encoding: [0xb0,0x02,0x24,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s101
-// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xca]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_lo
-// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xd4]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
-// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xd6]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], m0
-// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xf8]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], 0x0
-// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xfa]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc
-// GFX10: encoding: [0x82,0x02,0x25,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s0 dlc
-// GFX10: encoding: [0x82,0x42,0x24,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc dlc
-// GFX10: encoding: [0x82,0x42,0x25,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], 0x1234 glc dlc
-// GFX10: encoding: [0x82,0x42,0x25,0xf4,0x34,0x12,0x00,0xfa]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s0
-// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[24:27], s[4:7], s0
-// GFX10: encoding: [0x02,0x06,0x28,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[96:99], s[4:7], s0
-// GFX10: encoding: [0x02,0x18,0x28,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[8:11], s0
-// GFX10: encoding: [0x04,0x05,0x28,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[96:99], s0
-// GFX10: encoding: [0x30,0x05,0x28,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s101
-// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xca]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_lo
-// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xd4]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
-// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xd6]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], m0
-// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xf8]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], 0x0
-// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xfa]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc
-// GFX10: encoding: [0x02,0x05,0x29,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s0 dlc
-// GFX10: encoding: [0x02,0x45,0x28,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc dlc
-// GFX10: encoding: [0x02,0x45,0x29,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], 0x1234 glc dlc
-// GFX10: encoding: [0x02,0x45,0x29,0xf4,0x34,0x12,0x00,0xfa]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s0
-// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[24:31], s[4:7], s0
-// GFX10: encoding: [0x02,0x06,0x2c,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[92:99], s[4:7], s0
-// GFX10: encoding: [0x02,0x17,0x2c,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[8:11], s0
-// GFX10: encoding: [0x04,0x05,0x2c,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[96:99], s0
-// GFX10: encoding: [0x30,0x05,0x2c,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s101
-// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xca]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_lo
-// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xd4]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
-// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xd6]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], m0
-// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xf8]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], 0x0
-// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xfa]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc
-// GFX10: encoding: [0x02,0x05,0x2d,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s0 dlc
-// GFX10: encoding: [0x02,0x45,0x2c,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc dlc
-// GFX10: encoding: [0x02,0x45,0x2d,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], 0x1234 glc dlc
-// GFX10: encoding: [0x02,0x45,0x2d,0xf4,0x34,0x12,0x00,0xfa]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s0
-// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[24:39], s[4:7], s0
-// GFX10: encoding: [0x02,0x06,0x30,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[84:99], s[4:7], s0
-// GFX10: encoding: [0x02,0x15,0x30,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[8:11], s0
-// GFX10: encoding: [0x04,0x05,0x30,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[96:99], s0
-// GFX10: encoding: [0x30,0x05,0x30,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s101
-// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xca]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_lo
-// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xd4]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
-// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xd6]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], m0
-// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xf8]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], 0x0
-// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xfa]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc
-// GFX10: encoding: [0x02,0x05,0x31,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s0 dlc
-// GFX10: encoding: [0x02,0x45,0x30,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc dlc
-// GFX10: encoding: [0x02,0x45,0x31,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], 0x1234 glc dlc
-// GFX10: encoding: [0x02,0x45,0x31,0xf4,0x34,0x12,0x00,0xfa]
-
-s_store_dword s1, s[4:5], s0
-// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword s101, s[4:5], s0
-// GFX10: encoding: [0x42,0x19,0x40,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword vcc_lo, s[4:5], s0
-// GFX10: encoding: [0x82,0x1a,0x40,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword vcc_hi, s[4:5], s0
-// GFX10: encoding: [0xc2,0x1a,0x40,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[6:7], s0
-// GFX10: encoding: [0x43,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[100:101], s0
-// GFX10: encoding: [0x72,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, vcc, s0
-// GFX10: encoding: [0x75,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], s101
-// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xca]
-
-s_store_dword s1, s[4:5], vcc_lo
-// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xd4]
-
-s_store_dword s1, s[4:5], vcc_hi
-// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xd6]
-
-s_store_dword s1, s[4:5], m0
-// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xf8]
-
-s_store_dword s1, s[4:5], 0x0
-// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xfa]
-
-s_store_dword s1, s[4:5], s0 glc
-// GFX10: encoding: [0x42,0x00,0x41,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], s0 dlc
-// GFX10: encoding: [0x42,0x40,0x40,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], s0 glc dlc
-// GFX10: encoding: [0x42,0x40,0x41,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], 0x1234 glc dlc
-// GFX10: encoding: [0x42,0x40,0x41,0xf4,0x34,0x12,0x00,0xfa]
-
-s_store_dwordx2 s[2:3], s[4:5], s0
-// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[4:5], s[4:5], s0
-// GFX10: encoding: [0x02,0x01,0x44,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[100:101], s[4:5], s0
-// GFX10: encoding: [0x02,0x19,0x44,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 vcc, s[4:5], s0
-// GFX10: encoding: [0x82,0x1a,0x44,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[6:7], s0
-// GFX10: encoding: [0x83,0x00,0x44,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[100:101], s0
-// GFX10: encoding: [0xb2,0x00,0x44,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], vcc, s0
-// GFX10: encoding: [0xb5,0x00,0x44,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], s101
-// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xca]
-
-s_store_dwordx2 s[2:3], s[4:5], vcc_lo
-// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xd4]
-
-s_store_dwordx2 s[2:3], s[4:5], vcc_hi
-// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xd6]
-
-s_store_dwordx2 s[2:3], s[4:5], m0
-// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xf8]
-
-s_store_dwordx2 s[2:3], s[4:5], 0x0
-// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xfa]
-
-s_store_dwordx2 s[2:3], s[4:5], s0 glc
-// GFX10: encoding: [0x82,0x00,0x45,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], s0 dlc
-// GFX10: encoding: [0x82,0x40,0x44,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], s0 glc dlc
-// GFX10: encoding: [0x82,0x40,0x45,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], 0x1234 glc dlc
-// GFX10: encoding: [0x82,0x40,0x45,0xf4,0x34,0x12,0x00,0xfa]
-
-s_store_dwordx4 s[4:7], s[4:5], s0
-// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[8:11], s[4:5], s0
-// GFX10: encoding: [0x02,0x02,0x48,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[96:99], s[4:5], s0
-// GFX10: encoding: [0x02,0x18,0x48,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[6:7], s0
-// GFX10: encoding: [0x03,0x01,0x48,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[100:101], s0
-// GFX10: encoding: [0x32,0x01,0x48,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], vcc, s0
-// GFX10: encoding: [0x35,0x01,0x48,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], s101
-// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xca]
-
-s_store_dwordx4 s[4:7], s[4:5], vcc_lo
-// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xd4]
-
-s_store_dwordx4 s[4:7], s[4:5], vcc_hi
-// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xd6]
-
-s_store_dwordx4 s[4:7], s[4:5], m0
-// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xf8]
-
-s_store_dwordx4 s[4:7], s[4:5], 0x0
-// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xfa]
-
-s_store_dwordx4 s[4:7], s[4:5], s0 glc
-// GFX10: encoding: [0x02,0x01,0x49,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], s0 dlc
-// GFX10: encoding: [0x02,0x41,0x48,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], s0 glc dlc
-// GFX10: encoding: [0x02,0x41,0x49,0xf4,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], 0x1234 glc dlc
-// GFX10: encoding: [0x02,0x41,0x49,0xf4,0x34,0x12,0x00,0xfa]
-
-s_buffer_store_dword s1, s[8:11], s0
-// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s101, s[8:11], s0
-// GFX10: encoding: [0x44,0x19,0x60,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword vcc_lo, s[8:11], s0
-// GFX10: encoding: [0x84,0x1a,0x60,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword vcc_hi, s[8:11], s0
-// GFX10: encoding: [0xc4,0x1a,0x60,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[12:15], s0
-// GFX10: encoding: [0x46,0x00,0x60,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[96:99], s0
-// GFX10: encoding: [0x70,0x00,0x60,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], s101
-// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xca]
-
-s_buffer_store_dword s1, s[8:11], vcc_lo
-// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xd4]
-
-s_buffer_store_dword s1, s[8:11], vcc_hi
-// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xd6]
-
-s_buffer_store_dword s1, s[8:11], m0
-// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xf8]
-
-s_buffer_store_dword s1, s[8:11], 0x0
-// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xfa]
-
-s_buffer_store_dword s1, s[8:11], s0 glc
-// GFX10: encoding: [0x44,0x00,0x61,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], s0 dlc
-// GFX10: encoding: [0x44,0x40,0x60,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], s0 glc dlc
-// GFX10: encoding: [0x44,0x40,0x61,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], 0x1234 glc dlc
-// GFX10: encoding: [0x44,0x40,0x61,0xf4,0x34,0x12,0x00,0xfa]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], s0
-// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[4:5], s[8:11], s0
-// GFX10: encoding: [0x04,0x01,0x64,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[100:101], s[8:11], s0
-// GFX10: encoding: [0x04,0x19,0x64,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 vcc, s[8:11], s0
-// GFX10: encoding: [0x84,0x1a,0x64,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[12:15], s0
-// GFX10: encoding: [0x86,0x00,0x64,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[96:99], s0
-// GFX10: encoding: [0xb0,0x00,0x64,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], s101
-// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xca]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], vcc_lo
-// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xd4]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], vcc_hi
-// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xd6]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], m0
-// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xf8]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], 0x0
-// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xfa]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], s0 glc
-// GFX10: encoding: [0x84,0x00,0x65,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], s0 dlc
-// GFX10: encoding: [0x84,0x40,0x64,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], s0 glc dlc
-// GFX10: encoding: [0x84,0x40,0x65,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], 0x1234 glc dlc
-// GFX10: encoding: [0x84,0x40,0x65,0xf4,0x34,0x12,0x00,0xfa]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], s0
-// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[8:11], s[8:11], s0
-// GFX10: encoding: [0x04,0x02,0x68,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[96:99], s[8:11], s0
-// GFX10: encoding: [0x04,0x18,0x68,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[12:15], s0
-// GFX10: encoding: [0x06,0x01,0x68,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[96:99], s0
-// GFX10: encoding: [0x30,0x01,0x68,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], s101
-// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xca]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], vcc_lo
-// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xd4]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], vcc_hi
-// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xd6]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], m0
-// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xf8]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], 0x0
-// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xfa]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], s0 glc
-// GFX10: encoding: [0x04,0x01,0x69,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], s0 dlc
-// GFX10: encoding: [0x04,0x41,0x68,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], s0 glc dlc
-// GFX10: encoding: [0x04,0x41,0x69,0xf4,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], 0x1234 glc dlc
-// GFX10: encoding: [0x04,0x41,0x69,0xf4,0x34,0x12,0x00,0xfa]
-
-s_memrealtime s[10:11]
-// GFX10: encoding: [0x80,0x02,0x94,0xf4,0x00,0x00,0x00,0x00]
-
-s_memrealtime s[12:13]
-// GFX10: encoding: [0x00,0x03,0x94,0xf4,0x00,0x00,0x00,0x00]
-
-s_memrealtime s[100:101]
-// GFX10: encoding: [0x00,0x19,0x94,0xf4,0x00,0x00,0x00,0x00]
-
-s_memrealtime vcc
-// GFX10: encoding: [0x80,0x1a,0x94,0xf4,0x00,0x00,0x00,0x00]
-
-s_memtime s[10:11]
-// GFX10: encoding: [0x80,0x02,0x90,0xf4,0x00,0x00,0x00,0x00]
-
-s_memtime s[12:13]
-// GFX10: encoding: [0x00,0x03,0x90,0xf4,0x00,0x00,0x00,0x00]
-
-s_memtime s[100:101]
-// GFX10: encoding: [0x00,0x19,0x90,0xf4,0x00,0x00,0x00,0x00]
-
-s_memtime vcc
-// GFX10: encoding: [0x80,0x1a,0x90,0xf4,0x00,0x00,0x00,0x00]
-
-s_dcache_inv
-// GFX10: encoding: [0x00,0x00,0x80,0xf4,0x00,0x00,0x00,0x00]
-
-s_gl1_inv
-// GFX10: encoding: [0x00,0x00,0x7c,0xf4,0x00,0x00,0x00,0x00]
-
-s_dcache_wb
-// GFX10: encoding: [0x00,0x00,0x84,0xf4,0x00,0x00,0x00,0x00]
-
-s_get_waveid_in_workgroup s0
-// GFX10: encoding: [0x00,0x00,0xa8,0xf4,0x00,0x00,0x00,0x00]
-
-s_get_waveid_in_workgroup vcc_lo
-// GFX10: encoding: [0x80,0x1a,0xa8,0xf4,0x00,0x00,0x00,0x00]
-
-s_scratch_load_dword s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x14,0xf4,0x00,0x00,0x00,0xca]
-
-s_scratch_load_dword s5, s[2:3], s0 glc
-// GFX10: encoding: [0x41,0x01,0x15,0xf4,0x00,0x00,0x00,0x00]
-
-s_scratch_load_dwordx2 s[100:101], s[2:3], s0
-// GFX10: encoding: [0x01,0x19,0x18,0xf4,0x00,0x00,0x00,0x00]
-
-s_scratch_load_dwordx2 s[10:11], s[2:3], 0x1 glc
-// GFX10: encoding: [0x81,0x02,0x19,0xf4,0x01,0x00,0x00,0xfa]
-
-s_scratch_load_dwordx4 s[20:23], s[4:5], s0
-// GFX10: encoding: [0x02,0x05,0x1c,0xf4,0x00,0x00,0x00,0x00]
-
-s_scratch_store_dword s101, s[4:5], s0
-// GFX10: encoding: [0x42,0x19,0x54,0xf4,0x00,0x00,0x00,0x00]
-
-s_scratch_store_dword s1, s[4:5], 0x123 glc
-// GFX10: encoding: [0x42,0x00,0x55,0xf4,0x23,0x01,0x00,0xfa]
-
-s_scratch_store_dwordx2 s[2:3], s[4:5], s101 glc
-// GFX10: encoding: [0x82,0x00,0x59,0xf4,0x00,0x00,0x00,0xca]
-
-s_scratch_store_dwordx4 s[4:7], s[4:5], s0 glc
-// GFX10: encoding: [0x02,0x01,0x5d,0xf4,0x00,0x00,0x00,0x00]
-
-s_atc_probe 0x7, s[4:5], s2
-// GFX10: s_atc_probe 7, s[4:5], s2 ; encoding: [0xc2,0x01,0x98,0xf4,0x00,0x00,0x00,0x04]
-
-s_atc_probe 0x7, s[4:5], 100
-// GFX10: s_atc_probe 7, s[4:5], 0x64 ; encoding: [0xc2,0x01,0x98,0xf4,0x64,0x00,0x00,0xfa]
-
-s_atc_probe_buffer 0x7, s[8:11], s2
-// GFX10: s_atc_probe_buffer 7, s[8:11], s2 ; encoding: [0xc4,0x01,0x9c,0xf4,0x00,0x00,0x00,0x04]
-
-s_atc_probe_buffer 0x7, s[8:11], 100
-// GFX10: s_atc_probe_buffer 7, s[8:11], 0x64 ; encoding: [0xc4,0x01,0x9c,0xf4,0x64,0x00,0x00,0xfa]
-
-s_dcache_discard s[2:3], s2
-// GFX10: s_dcache_discard s[2:3], s2 ; encoding: [0x01,0x00,0xa0,0xf4,0x00,0x00,0x00,0x04]
-
-s_dcache_discard s[2:3], 100
-// GFX10: s_dcache_discard s[2:3], 0x64 ; encoding: [0x01,0x00,0xa0,0xf4,0x64,0x00,0x00,0xfa]
-
-s_dcache_discard_x2 s[2:3], s2
-// GFX10: s_dcache_discard_x2 s[2:3], s2 ; encoding: [0x01,0x00,0xa4,0xf4,0x00,0x00,0x00,0x04]
-
-s_dcache_discard_x2 s[2:3], 100
-// GFX10: s_dcache_discard_x2 s[2:3], 0x64 ; encoding: [0x01,0x00,0xa4,0xf4,0x64,0x00,0x00,0xfa]
-
-s_atomic_add s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x08,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_add s5, s[2:3], 0x64
-// GFX10: encoding: [0x41,0x01,0x08,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_add_x2 s[10:11], s[2:3], s101
-// GFX10: encoding: [0x81,0x02,0x88,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_and s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x20,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_and_x2 s[10:11], s[2:3], 0x64
-// GFX10: encoding: [0x81,0x02,0xa0,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_cmpswap s[10:11], s[2:3], s101
-// GFX10: encoding: [0x81,0x02,0x04,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_cmpswap s[10:11], s[2:3], 0x64
-// GFX10: encoding: [0x81,0x02,0x04,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_cmpswap_x2 s[20:23], s[2:3], s101
-// GFX10: encoding: [0x01,0x05,0x84,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_cmpswap_x2 s[20:23], s[2:3], 0x64
-// GFX10: encoding: [0x01,0x05,0x84,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_dec_x2 s[10:11], s[2:3], s101
-// GFX10: encoding: [0x81,0x02,0xb0,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_inc_x2 s[10:11], s[2:3], s101
-// GFX10: encoding: [0x81,0x02,0xac,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_or s5, s[2:3], 0x64
-// GFX10: encoding: [0x41,0x01,0x24,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_smax s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x18,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_smin s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x10,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_sub s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x0c,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_swap s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x00,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_umax_x2 s[10:11], s[2:3], s101
-// GFX10: encoding: [0x81,0x02,0x9c,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_umin s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x14,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_xor s5, s[2:3], s101
-// GFX10: encoding: [0x41,0x01,0x28,0xf6,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_add s5, s[4:7], s101
-// GFX10: encoding: [0x42,0x01,0x08,0xf5,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_add s5, s[4:7], 0x64
-// GFX10: encoding: [0x42,0x01,0x08,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_add_x2 s[10:11], s[4:7], s2
-// GFX10: encoding: [0x82,0x02,0x88,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_and s101, s[4:7], s2
-// GFX10: encoding: [0x42,0x19,0x20,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_and_x2 s[10:11], s[8:11], s2
-// GFX10: encoding: [0x84,0x02,0xa0,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_cmpswap s[10:11], s[4:7], s2
-// GFX10: encoding: [0x82,0x02,0x04,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_cmpswap s[10:11], s[4:7], 0x64
-// GFX10: encoding: [0x82,0x02,0x04,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], s101
-// GFX10: encoding: [0x02,0x05,0x84,0xf5,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], 0x64
-// GFX10: encoding: [0x02,0x05,0x84,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_dec s5, s[4:7], s2
-// GFX10: encoding: [0x42,0x01,0x30,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_inc s101, s[4:7], s2
-// GFX10: encoding: [0x42,0x19,0x2c,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_inc_x2 s[10:11], s[4:7], 0x64
-// GFX10: encoding: [0x82,0x02,0xac,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_or s5, s[8:11], s2
-// GFX10: encoding: [0x44,0x01,0x24,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_or_x2 s[10:11], s[96:99], s2
-// GFX10: encoding: [0xb0,0x02,0xa4,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_smax s5, s[4:7], s101
-// GFX10: encoding: [0x42,0x01,0x18,0xf5,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_smax_x2 s[100:101], s[4:7], s2
-// GFX10: encoding: [0x02,0x19,0x98,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_smin s5, s[4:7], 0x64
-// GFX10: encoding: [0x42,0x01,0x10,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_smin_x2 s[12:13], s[4:7], s2
-// GFX10: encoding: [0x02,0x03,0x90,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_sub_x2 s[10:11], s[4:7], s2
-// GFX10: encoding: [0x82,0x02,0x8c,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_swap s5, s[4:7], s2
-// GFX10: encoding: [0x42,0x01,0x00,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_umax s5, s[4:7], s2
-// GFX10: encoding: [0x42,0x01,0x1c,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_umin s5, s[4:7], s2
-// GFX10: encoding: [0x42,0x01,0x14,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_xor s5, s[4:7], s2
-// GFX10: encoding: [0x42,0x01,0x28,0xf5,0x00,0x00,0x00,0x04]
-
-s_atomic_add s5, s[2:3], s101 glc
-// GFX10: encoding: [0x41,0x01,0x09,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_add s5, s[2:3], 0x64 glc
-// GFX10: encoding: [0x41,0x01,0x09,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_add_x2 s[10:11], s[2:3], s101 glc
-// GFX10: encoding: [0x81,0x02,0x89,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_and s5, s[2:3], s101 glc
-// GFX10: encoding: [0x41,0x01,0x21,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_and_x2 s[10:11], s[2:3], 0x64 glc
-// GFX10: encoding: [0x81,0x02,0xa1,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_cmpswap s[10:11], s[2:3], s101 glc
-// GFX10: encoding: [0x81,0x02,0x05,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_cmpswap s[10:11], s[2:3], 0x64 glc
-// GFX10: encoding: [0x81,0x02,0x05,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_cmpswap_x2 s[20:23], s[2:3], s101 glc
-// GFX10: encoding: [0x01,0x05,0x85,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_cmpswap_x2 s[20:23], s[2:3], 0x64 glc
-// GFX10: encoding: [0x01,0x05,0x85,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_dec_x2 s[10:11], s[2:3], s101 glc
-// GFX10: encoding: [0x81,0x02,0xb1,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_inc_x2 s[10:11], s[2:3], s101 glc
-// GFX10: encoding: [0x81,0x02,0xad,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_or s5, s[2:3], 0x64 glc
-// GFX10: encoding: [0x41,0x01,0x25,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_smax s5, s[2:3], s101 glc
-// GFX10: encoding: [0x41,0x01,0x19,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_smin s5, s[2:3], s101 glc
-// GFX10: encoding: [0x41,0x01,0x11,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_sub s5, s[2:3], s101 glc
-// GFX10: encoding: [0x41,0x01,0x0d,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_swap s5, s[2:3], s101 glc
-// GFX10: encoding: [0x41,0x01,0x01,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_umax_x2 s[10:11], s[2:3], s101 glc
-// GFX10: encoding: [0x81,0x02,0x9d,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_umin s5, s[2:3], s101 glc
-// GFX10: encoding: [0x41,0x01,0x15,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_xor s5, s[2:3], s101 glc
-// GFX10: encoding: [0x41,0x01,0x29,0xf6,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_add s5, s[4:7], s101 glc
-// GFX10: encoding: [0x42,0x01,0x09,0xf5,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_add s5, s[4:7], 0x64 glc
-// GFX10: encoding: [0x42,0x01,0x09,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_add_x2 s[10:11], s[4:7], s2 glc
-// GFX10: encoding: [0x82,0x02,0x89,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_and s101, s[4:7], s2 glc
-// GFX10: encoding: [0x42,0x19,0x21,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_and_x2 s[10:11], s[8:11], s2 glc
-// GFX10: encoding: [0x84,0x02,0xa1,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_cmpswap s[10:11], s[4:7], s2 glc
-// GFX10: encoding: [0x82,0x02,0x05,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_cmpswap s[10:11], s[4:7], 0x64 glc
-// GFX10: encoding: [0x82,0x02,0x05,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], s101 glc
-// GFX10: encoding: [0x02,0x05,0x85,0xf5,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], 0x64 glc
-// GFX10: encoding: [0x02,0x05,0x85,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_dec s5, s[4:7], s2 glc
-// GFX10: encoding: [0x42,0x01,0x31,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_inc s101, s[4:7], s2 glc
-// GFX10: encoding: [0x42,0x19,0x2d,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_inc_x2 s[10:11], s[4:7], 0x64 glc
-// GFX10: encoding: [0x82,0x02,0xad,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_or s5, s[8:11], s2 glc
-// GFX10: encoding: [0x44,0x01,0x25,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_or_x2 s[10:11], s[96:99], s2 glc
-// GFX10: encoding: [0xb0,0x02,0xa5,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_smax s5, s[4:7], s101 glc
-// GFX10: encoding: [0x42,0x01,0x19,0xf5,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_smax_x2 s[100:101], s[4:7], s2 glc
-// GFX10: encoding: [0x02,0x19,0x99,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_smin s5, s[4:7], 0x64 glc
-// GFX10: encoding: [0x42,0x01,0x11,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_smin_x2 s[12:13], s[4:7], s2 glc
-// GFX10: encoding: [0x02,0x03,0x91,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_sub_x2 s[10:11], s[4:7], s2 glc
-// GFX10: encoding: [0x82,0x02,0x8d,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_swap s5, s[4:7], s2 glc
-// GFX10: encoding: [0x42,0x01,0x01,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_umax s5, s[4:7], s2 glc
-// GFX10: encoding: [0x42,0x01,0x1d,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_umin s5, s[4:7], s2 glc
-// GFX10: encoding: [0x42,0x01,0x15,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_xor s5, s[4:7], s2 glc
-// GFX10: encoding: [0x42,0x01,0x29,0xf5,0x00,0x00,0x00,0x04]
-
-s_atomic_add s5, s[2:3], s101 dlc
-// GFX10: encoding: [0x41,0x41,0x08,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_add s5, s[2:3], 0x64 dlc
-// GFX10: encoding: [0x41,0x41,0x08,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_add_x2 s[10:11], s[2:3], s101 dlc
-// GFX10: encoding: [0x81,0x42,0x88,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_and s5, s[2:3], s101 dlc
-// GFX10: encoding: [0x41,0x41,0x20,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_and_x2 s[10:11], s[2:3], 0x64 dlc
-// GFX10: encoding: [0x81,0x42,0xa0,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_cmpswap s[10:11], s[2:3], s101 dlc
-// GFX10: encoding: [0x81,0x42,0x04,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_cmpswap s[10:11], s[2:3], 0x64 dlc
-// GFX10: encoding: [0x81,0x42,0x04,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_cmpswap_x2 s[20:23], s[2:3], s101 dlc
-// GFX10: encoding: [0x01,0x45,0x84,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_cmpswap_x2 s[20:23], s[2:3], 0x64 dlc
-// GFX10: encoding: [0x01,0x45,0x84,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_dec_x2 s[10:11], s[2:3], s101 dlc
-// GFX10: encoding: [0x81,0x42,0xb0,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_inc_x2 s[10:11], s[2:3], s101 dlc
-// GFX10: encoding: [0x81,0x42,0xac,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_or s5, s[2:3], 0x64 dlc
-// GFX10: encoding: [0x41,0x41,0x24,0xf6,0x64,0x00,0x00,0xfa]
-
-s_atomic_smax s5, s[2:3], s101 dlc
-// GFX10: encoding: [0x41,0x41,0x18,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_smin s5, s[2:3], s101 dlc
-// GFX10: encoding: [0x41,0x41,0x10,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_sub s5, s[2:3], s101 dlc
-// GFX10: encoding: [0x41,0x41,0x0c,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_swap s5, s[2:3], s101 dlc
-// GFX10: encoding: [0x41,0x41,0x00,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_umax_x2 s[10:11], s[2:3], s101 dlc
-// GFX10: encoding: [0x81,0x42,0x9c,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_umin s5, s[2:3], s101 dlc
-// GFX10: encoding: [0x41,0x41,0x14,0xf6,0x00,0x00,0x00,0xca]
-
-s_atomic_xor s5, s[2:3], s101 dlc
-// GFX10: encoding: [0x41,0x41,0x28,0xf6,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_add s5, s[4:7], s101 dlc
-// GFX10: encoding: [0x42,0x41,0x08,0xf5,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_add s5, s[4:7], 0x64 dlc
-// GFX10: encoding: [0x42,0x41,0x08,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_add_x2 s[10:11], s[4:7], s2 dlc
-// GFX10: encoding: [0x82,0x42,0x88,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_and s101, s[4:7], s2 dlc
-// GFX10: encoding: [0x42,0x59,0x20,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_and_x2 s[10:11], s[8:11], s2 dlc
-// GFX10: encoding: [0x84,0x42,0xa0,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_cmpswap s[10:11], s[4:7], s2 dlc
-// GFX10: encoding: [0x82,0x42,0x04,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_cmpswap s[10:11], s[4:7], 0x64 dlc
-// GFX10: encoding: [0x82,0x42,0x04,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], s101 dlc
-// GFX10: encoding: [0x02,0x45,0x84,0xf5,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], 0x64 dlc
-// GFX10: encoding: [0x02,0x45,0x84,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_dec s5, s[4:7], s2 dlc
-// GFX10: encoding: [0x42,0x41,0x30,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_inc s101, s[4:7], s2 dlc
-// GFX10: encoding: [0x42,0x59,0x2c,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_inc_x2 s[10:11], s[4:7], 0x64 dlc
-// GFX10: encoding: [0x82,0x42,0xac,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_or s5, s[8:11], s2 dlc
-// GFX10: encoding: [0x44,0x41,0x24,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_or_x2 s[10:11], s[96:99], s2 dlc
-// GFX10: encoding: [0xb0,0x42,0xa4,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_smax s5, s[4:7], s101 dlc
-// GFX10: encoding: [0x42,0x41,0x18,0xf5,0x00,0x00,0x00,0xca]
-
-s_buffer_atomic_smax_x2 s[100:101], s[4:7], s2 dlc
-// GFX10: encoding: [0x02,0x59,0x98,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_smin s5, s[4:7], 0x64 dlc
-// GFX10: encoding: [0x42,0x41,0x10,0xf5,0x64,0x00,0x00,0xfa]
-
-s_buffer_atomic_smin_x2 s[12:13], s[4:7], s2 dlc
-// GFX10: encoding: [0x02,0x43,0x90,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_sub_x2 s[10:11], s[4:7], s2 dlc
-// GFX10: encoding: [0x82,0x42,0x8c,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_swap s5, s[4:7], s2 dlc
-// GFX10: encoding: [0x42,0x41,0x00,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_umax s5, s[4:7], s2 dlc
-// GFX10: encoding: [0x42,0x41,0x1c,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_umin s5, s[4:7], s2 dlc
-// GFX10: encoding: [0x42,0x41,0x14,0xf5,0x00,0x00,0x00,0x04]
-
-s_buffer_atomic_xor s5, s[4:7], s2 dlc
-// GFX10: encoding: [0x42,0x41,0x28,0xf5,0x00,0x00,0x00,0x04]
-
-//===----------------------------------------------------------------------===//
-// ENC_SOP1.
-//===----------------------------------------------------------------------===//
-
-s_mov_b32 s0, s1
-// GFX10: encoding: [0x01,0x03,0x80,0xbe]
-
-s_mov_b32 s105, s104
-// GFX10: encoding: [0x68,0x03,0xe9,0xbe]
-
-s_mov_b32 s0, s104
-// GFX10: encoding: [0x68,0x03,0x80,0xbe]
-
-s_mov_b32 s105, s1
-// GFX10: encoding: [0x01,0x03,0xe9,0xbe]
-
-s_mov_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x03,0xfe,0xbe]
-
-s_mov_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x03,0xff,0xbe]
-
-s_mov_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x03,0xea,0xbe]
-
-s_mov_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x03,0xeb,0xbe]
-
-s_mov_b32 m0, s1
-// GFX10: encoding: [0x01,0x03,0xfc,0xbe]
-
-s_mov_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x03,0x80,0xbe]
-
-s_mov_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x03,0x80,0xbe]
-
-s_mov_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x03,0x80,0xbe]
-
-s_mov_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x03,0x80,0xbe]
-
-s_mov_b32 s0, m0
-// GFX10: encoding: [0x7c,0x03,0x80,0xbe]
-
-s_mov_b32 s0, 0
-// GFX10: encoding: [0x80,0x03,0x80,0xbe]
-
-s_mov_b32 s0, -1
-// GFX10: encoding: [0xc1,0x03,0x80,0xbe]
-
-s_mov_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x03,0x80,0xbe]
-
-s_mov_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x03,0x80,0xbe]
-
-s_mov_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x03,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_mov_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_mov_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x04,0x80,0xbe]
-
-s_mov_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x04,0xe8,0xbe]
-
-s_mov_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x04,0x80,0xbe]
-
-s_mov_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x04,0xe8,0xbe]
-
-s_mov_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x04,0xfe,0xbe]
-
-s_mov_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x04,0xea,0xbe]
-
-s_mov_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x04,0x80,0xbe]
-
-s_mov_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x04,0x80,0xbe]
-
-s_mov_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x04,0x80,0xbe]
-
-s_mov_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x04,0x80,0xbe]
-
-s_mov_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x04,0x80,0xbe]
-
-s_mov_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x04,0x80,0xbe]
-
-s_mov_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x04,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_mov_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x04,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_cmov_b32 s0, s1
-// GFX10: encoding: [0x01,0x05,0x80,0xbe]
-
-s_cmov_b32 s105, s104
-// GFX10: encoding: [0x68,0x05,0xe9,0xbe]
-
-s_cmov_b32 s0, s104
-// GFX10: encoding: [0x68,0x05,0x80,0xbe]
-
-s_cmov_b32 s105, s1
-// GFX10: encoding: [0x01,0x05,0xe9,0xbe]
-
-s_cmov_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x05,0xfe,0xbe]
-
-s_cmov_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x05,0xff,0xbe]
-
-s_cmov_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x05,0xea,0xbe]
-
-s_cmov_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x05,0xeb,0xbe]
-
-s_cmov_b32 m0, s1
-// GFX10: encoding: [0x01,0x05,0xfc,0xbe]
-
-s_cmov_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x05,0x80,0xbe]
-
-s_cmov_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x05,0x80,0xbe]
-
-s_cmov_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x05,0x80,0xbe]
-
-s_cmov_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x05,0x80,0xbe]
-
-s_cmov_b32 s0, m0
-// GFX10: encoding: [0x7c,0x05,0x80,0xbe]
-
-s_cmov_b32 s0, 0
-// GFX10: encoding: [0x80,0x05,0x80,0xbe]
-
-s_cmov_b32 s0, -1
-// GFX10: encoding: [0xc1,0x05,0x80,0xbe]
-
-s_cmov_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x05,0x80,0xbe]
-
-s_cmov_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x05,0x80,0xbe]
-
-s_cmov_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x05,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cmov_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_cmov_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x06,0x80,0xbe]
-
-s_cmov_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x06,0xe8,0xbe]
-
-s_cmov_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x06,0x80,0xbe]
-
-s_cmov_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x06,0xe8,0xbe]
-
-s_cmov_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x06,0xfe,0xbe]
-
-s_cmov_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x06,0xea,0xbe]
-
-s_cmov_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x06,0x80,0xbe]
-
-s_cmov_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x06,0x80,0xbe]
-
-s_cmov_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x06,0x80,0xbe]
-
-s_cmov_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x06,0x80,0xbe]
-
-s_cmov_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x06,0x80,0xbe]
-
-s_cmov_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x06,0x80,0xbe]
-
-s_cmov_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x06,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cmov_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x06,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_not_b32 s0, s1
-// GFX10: encoding: [0x01,0x07,0x80,0xbe]
-
-s_not_b32 s105, s104
-// GFX10: encoding: [0x68,0x07,0xe9,0xbe]
-
-s_not_b32 s0, s104
-// GFX10: encoding: [0x68,0x07,0x80,0xbe]
-
-s_not_b32 s105, s1
-// GFX10: encoding: [0x01,0x07,0xe9,0xbe]
-
-s_not_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x07,0xfe,0xbe]
-
-s_not_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x07,0xff,0xbe]
-
-s_not_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x07,0xea,0xbe]
-
-s_not_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x07,0xeb,0xbe]
-
-s_not_b32 m0, s1
-// GFX10: encoding: [0x01,0x07,0xfc,0xbe]
-
-s_not_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x07,0x80,0xbe]
-
-s_not_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x07,0x80,0xbe]
-
-s_not_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x07,0x80,0xbe]
-
-s_not_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x07,0x80,0xbe]
-
-s_not_b32 s0, m0
-// GFX10: encoding: [0x7c,0x07,0x80,0xbe]
-
-s_not_b32 s0, 0
-// GFX10: encoding: [0x80,0x07,0x80,0xbe]
-
-s_not_b32 s0, -1
-// GFX10: encoding: [0xc1,0x07,0x80,0xbe]
-
-s_not_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x07,0x80,0xbe]
-
-s_not_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x07,0x80,0xbe]
-
-s_not_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x07,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_not_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x07,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_not_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x08,0x80,0xbe]
-
-s_not_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x08,0xe8,0xbe]
-
-s_not_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x08,0x80,0xbe]
-
-s_not_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x08,0xe8,0xbe]
-
-s_not_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x08,0xfe,0xbe]
-
-s_not_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x08,0xea,0xbe]
-
-s_not_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x08,0x80,0xbe]
-
-s_not_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x08,0x80,0xbe]
-
-s_not_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x08,0x80,0xbe]
-
-s_not_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x08,0x80,0xbe]
-
-s_not_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x08,0x80,0xbe]
-
-s_not_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x08,0x80,0xbe]
-
-s_not_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x08,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_not_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x08,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_wqm_b32 s0, s1
-// GFX10: encoding: [0x01,0x09,0x80,0xbe]
-
-s_wqm_b32 s105, s104
-// GFX10: encoding: [0x68,0x09,0xe9,0xbe]
-
-s_wqm_b32 s0, s104
-// GFX10: encoding: [0x68,0x09,0x80,0xbe]
-
-s_wqm_b32 s105, s1
-// GFX10: encoding: [0x01,0x09,0xe9,0xbe]
-
-s_wqm_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x09,0xfe,0xbe]
-
-s_wqm_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x09,0xff,0xbe]
-
-s_wqm_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x09,0xea,0xbe]
-
-s_wqm_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x09,0xeb,0xbe]
-
-s_wqm_b32 m0, s1
-// GFX10: encoding: [0x01,0x09,0xfc,0xbe]
-
-s_wqm_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x09,0x80,0xbe]
-
-s_wqm_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x09,0x80,0xbe]
-
-s_wqm_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x09,0x80,0xbe]
-
-s_wqm_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x09,0x80,0xbe]
-
-s_wqm_b32 s0, m0
-// GFX10: encoding: [0x7c,0x09,0x80,0xbe]
-
-s_wqm_b32 s0, 0
-// GFX10: encoding: [0x80,0x09,0x80,0xbe]
-
-s_wqm_b32 s0, -1
-// GFX10: encoding: [0xc1,0x09,0x80,0xbe]
-
-s_wqm_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x09,0x80,0xbe]
-
-s_wqm_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x09,0x80,0xbe]
-
-s_wqm_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x09,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_wqm_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_wqm_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x0a,0x80,0xbe]
-
-s_wqm_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x0a,0xe8,0xbe]
-
-s_wqm_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x0a,0x80,0xbe]
-
-s_wqm_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x0a,0xe8,0xbe]
-
-s_wqm_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x0a,0xfe,0xbe]
-
-s_wqm_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x0a,0xea,0xbe]
-
-s_wqm_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x0a,0x80,0xbe]
-
-s_wqm_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x0a,0x80,0xbe]
-
-s_wqm_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x0a,0x80,0xbe]
-
-s_wqm_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x0a,0x80,0xbe]
-
-s_wqm_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x0a,0x80,0xbe]
-
-s_wqm_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x0a,0x80,0xbe]
-
-s_wqm_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x0a,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_wqm_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x0a,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_brev_b32 s0, s1
-// GFX10: encoding: [0x01,0x0b,0x80,0xbe]
-
-s_brev_b32 s105, s104
-// GFX10: encoding: [0x68,0x0b,0xe9,0xbe]
-
-s_brev_b32 s0, s104
-// GFX10: encoding: [0x68,0x0b,0x80,0xbe]
-
-s_brev_b32 s105, s1
-// GFX10: encoding: [0x01,0x0b,0xe9,0xbe]
-
-s_brev_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x0b,0xfe,0xbe]
-
-s_brev_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x0b,0xff,0xbe]
-
-s_brev_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x0b,0xea,0xbe]
-
-s_brev_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x0b,0xeb,0xbe]
-
-s_brev_b32 m0, s1
-// GFX10: encoding: [0x01,0x0b,0xfc,0xbe]
-
-s_brev_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x0b,0x80,0xbe]
-
-s_brev_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x0b,0x80,0xbe]
-
-s_brev_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x0b,0x80,0xbe]
-
-s_brev_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x0b,0x80,0xbe]
-
-s_brev_b32 s0, m0
-// GFX10: encoding: [0x7c,0x0b,0x80,0xbe]
-
-s_brev_b32 s0, 0
-// GFX10: encoding: [0x80,0x0b,0x80,0xbe]
-
-s_brev_b32 s0, -1
-// GFX10: encoding: [0xc1,0x0b,0x80,0xbe]
-
-s_brev_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x0b,0x80,0xbe]
-
-s_brev_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x0b,0x80,0xbe]
-
-s_brev_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x0b,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_brev_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_brev_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x0c,0x80,0xbe]
-
-s_brev_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x0c,0xe8,0xbe]
-
-s_brev_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x0c,0x80,0xbe]
-
-s_brev_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x0c,0xe8,0xbe]
-
-s_brev_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x0c,0xfe,0xbe]
-
-s_brev_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x0c,0xea,0xbe]
-
-s_brev_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x0c,0x80,0xbe]
-
-s_brev_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x0c,0x80,0xbe]
-
-s_brev_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x0c,0x80,0xbe]
-
-s_brev_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x0c,0x80,0xbe]
-
-s_brev_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x0c,0x80,0xbe]
-
-s_brev_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x0c,0x80,0xbe]
-
-s_brev_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x0c,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_brev_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x0c,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt0_i32_b32 s0, s1
-// GFX10: encoding: [0x01,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s105, s104
-// GFX10: encoding: [0x68,0x0d,0xe9,0xbe]
-
-s_bcnt0_i32_b32 s0, s104
-// GFX10: encoding: [0x68,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s105, s1
-// GFX10: encoding: [0x01,0x0d,0xe9,0xbe]
-
-s_bcnt0_i32_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x0d,0xfe,0xbe]
-
-s_bcnt0_i32_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x0d,0xff,0xbe]
-
-s_bcnt0_i32_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x0d,0xea,0xbe]
-
-s_bcnt0_i32_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x0d,0xeb,0xbe]
-
-s_bcnt0_i32_b32 m0, s1
-// GFX10: encoding: [0x01,0x0d,0xfc,0xbe]
-
-s_bcnt0_i32_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s0, m0
-// GFX10: encoding: [0x7c,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s0, 0
-// GFX10: encoding: [0x80,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s0, -1
-// GFX10: encoding: [0xc1,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x0d,0x80,0xbe]
-
-s_bcnt0_i32_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x0d,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt0_i32_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt0_i32_b64 s0, s[2:3]
-// GFX10: encoding: [0x02,0x0e,0x80,0xbe]
-
-s_bcnt0_i32_b64 s105, s[102:103]
-// GFX10: encoding: [0x66,0x0e,0xe9,0xbe]
-
-s_bcnt0_i32_b64 s0, s[102:103]
-// GFX10: encoding: [0x66,0x0e,0x80,0xbe]
-
-s_bcnt0_i32_b64 s105, s[2:3]
-// GFX10: encoding: [0x02,0x0e,0xe9,0xbe]
-
-s_bcnt0_i32_b64 exec_lo, s[2:3]
-// GFX10: encoding: [0x02,0x0e,0xfe,0xbe]
-
-s_bcnt0_i32_b64 exec_hi, s[2:3]
-// GFX10: encoding: [0x02,0x0e,0xff,0xbe]
-
-s_bcnt0_i32_b64 vcc_lo, s[2:3]
-// GFX10: encoding: [0x02,0x0e,0xea,0xbe]
-
-s_bcnt0_i32_b64 vcc_hi, s[2:3]
-// GFX10: encoding: [0x02,0x0e,0xeb,0xbe]
-
-s_bcnt0_i32_b64 m0, s[2:3]
-// GFX10: encoding: [0x02,0x0e,0xfc,0xbe]
-
-s_bcnt0_i32_b64 s0, exec
-// GFX10: encoding: [0x7e,0x0e,0x80,0xbe]
-
-s_bcnt0_i32_b64 s0, vcc
-// GFX10: encoding: [0x6a,0x0e,0x80,0xbe]
-
-s_bcnt0_i32_b64 s0, 0
-// GFX10: encoding: [0x80,0x0e,0x80,0xbe]
-
-s_bcnt0_i32_b64 s0, -1
-// GFX10: encoding: [0xc1,0x0e,0x80,0xbe]
-
-s_bcnt0_i32_b64 s0, 0.5
-// GFX10: encoding: [0xf0,0x0e,0x80,0xbe]
-
-s_bcnt0_i32_b64 s0, -4.0
-// GFX10: encoding: [0xf7,0x0e,0x80,0xbe]
-
-s_bcnt0_i32_b64 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x0e,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt0_i32_b64 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x0e,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt1_i32_b32 s0, s1
-// GFX10: encoding: [0x01,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s105, s104
-// GFX10: encoding: [0x68,0x0f,0xe9,0xbe]
-
-s_bcnt1_i32_b32 s0, s104
-// GFX10: encoding: [0x68,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s105, s1
-// GFX10: encoding: [0x01,0x0f,0xe9,0xbe]
-
-s_bcnt1_i32_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x0f,0xfe,0xbe]
-
-s_bcnt1_i32_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x0f,0xff,0xbe]
-
-s_bcnt1_i32_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x0f,0xea,0xbe]
-
-s_bcnt1_i32_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x0f,0xeb,0xbe]
-
-s_bcnt1_i32_b32 m0, s1
-// GFX10: encoding: [0x01,0x0f,0xfc,0xbe]
-
-s_bcnt1_i32_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s0, m0
-// GFX10: encoding: [0x7c,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s0, 0
-// GFX10: encoding: [0x80,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s0, -1
-// GFX10: encoding: [0xc1,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x0f,0x80,0xbe]
-
-s_bcnt1_i32_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x0f,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt1_i32_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x0f,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt1_i32_b64 s0, s[2:3]
-// GFX10: encoding: [0x02,0x10,0x80,0xbe]
-
-s_bcnt1_i32_b64 s105, s[102:103]
-// GFX10: encoding: [0x66,0x10,0xe9,0xbe]
-
-s_bcnt1_i32_b64 s0, s[102:103]
-// GFX10: encoding: [0x66,0x10,0x80,0xbe]
-
-s_bcnt1_i32_b64 s105, s[2:3]
-// GFX10: encoding: [0x02,0x10,0xe9,0xbe]
-
-s_bcnt1_i32_b64 exec_lo, s[2:3]
-// GFX10: encoding: [0x02,0x10,0xfe,0xbe]
-
-s_bcnt1_i32_b64 exec_hi, s[2:3]
-// GFX10: encoding: [0x02,0x10,0xff,0xbe]
-
-s_bcnt1_i32_b64 vcc_lo, s[2:3]
-// GFX10: encoding: [0x02,0x10,0xea,0xbe]
-
-s_bcnt1_i32_b64 vcc_hi, s[2:3]
-// GFX10: encoding: [0x02,0x10,0xeb,0xbe]
-
-s_bcnt1_i32_b64 m0, s[2:3]
-// GFX10: encoding: [0x02,0x10,0xfc,0xbe]
-
-s_bcnt1_i32_b64 s0, exec
-// GFX10: encoding: [0x7e,0x10,0x80,0xbe]
-
-s_bcnt1_i32_b64 s0, vcc
-// GFX10: encoding: [0x6a,0x10,0x80,0xbe]
-
-s_bcnt1_i32_b64 s0, 0
-// GFX10: encoding: [0x80,0x10,0x80,0xbe]
-
-s_bcnt1_i32_b64 s0, -1
-// GFX10: encoding: [0xc1,0x10,0x80,0xbe]
-
-s_bcnt1_i32_b64 s0, 0.5
-// GFX10: encoding: [0xf0,0x10,0x80,0xbe]
-
-s_bcnt1_i32_b64 s0, -4.0
-// GFX10: encoding: [0xf7,0x10,0x80,0xbe]
-
-s_bcnt1_i32_b64 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x10,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt1_i32_b64 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x10,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff0_i32_b32 s0, s1
-// GFX10: encoding: [0x01,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s105, s104
-// GFX10: encoding: [0x68,0x11,0xe9,0xbe]
-
-s_ff0_i32_b32 s0, s104
-// GFX10: encoding: [0x68,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s105, s1
-// GFX10: encoding: [0x01,0x11,0xe9,0xbe]
-
-s_ff0_i32_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x11,0xfe,0xbe]
-
-s_ff0_i32_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x11,0xff,0xbe]
-
-s_ff0_i32_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x11,0xea,0xbe]
-
-s_ff0_i32_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x11,0xeb,0xbe]
-
-s_ff0_i32_b32 m0, s1
-// GFX10: encoding: [0x01,0x11,0xfc,0xbe]
-
-s_ff0_i32_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s0, m0
-// GFX10: encoding: [0x7c,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s0, 0
-// GFX10: encoding: [0x80,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s0, -1
-// GFX10: encoding: [0xc1,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x11,0x80,0xbe]
-
-s_ff0_i32_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x11,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff0_i32_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x11,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff0_i32_b64 s0, s[2:3]
-// GFX10: encoding: [0x02,0x12,0x80,0xbe]
-
-s_ff0_i32_b64 s105, s[102:103]
-// GFX10: encoding: [0x66,0x12,0xe9,0xbe]
-
-s_ff0_i32_b64 s0, s[102:103]
-// GFX10: encoding: [0x66,0x12,0x80,0xbe]
-
-s_ff0_i32_b64 s105, s[2:3]
-// GFX10: encoding: [0x02,0x12,0xe9,0xbe]
-
-s_ff0_i32_b64 exec_lo, s[2:3]
-// GFX10: encoding: [0x02,0x12,0xfe,0xbe]
-
-s_ff0_i32_b64 exec_hi, s[2:3]
-// GFX10: encoding: [0x02,0x12,0xff,0xbe]
-
-s_ff0_i32_b64 vcc_lo, s[2:3]
-// GFX10: encoding: [0x02,0x12,0xea,0xbe]
-
-s_ff0_i32_b64 vcc_hi, s[2:3]
-// GFX10: encoding: [0x02,0x12,0xeb,0xbe]
-
-s_ff0_i32_b64 m0, s[2:3]
-// GFX10: encoding: [0x02,0x12,0xfc,0xbe]
-
-s_ff0_i32_b64 s0, exec
-// GFX10: encoding: [0x7e,0x12,0x80,0xbe]
-
-s_ff0_i32_b64 s0, vcc
-// GFX10: encoding: [0x6a,0x12,0x80,0xbe]
-
-s_ff0_i32_b64 s0, 0
-// GFX10: encoding: [0x80,0x12,0x80,0xbe]
-
-s_ff0_i32_b64 s0, -1
-// GFX10: encoding: [0xc1,0x12,0x80,0xbe]
-
-s_ff0_i32_b64 s0, 0.5
-// GFX10: encoding: [0xf0,0x12,0x80,0xbe]
-
-s_ff0_i32_b64 s0, -4.0
-// GFX10: encoding: [0xf7,0x12,0x80,0xbe]
-
-s_ff0_i32_b64 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x12,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff0_i32_b64 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x12,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff1_i32_b32 s0, s1
-// GFX10: encoding: [0x01,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s105, s104
-// GFX10: encoding: [0x68,0x13,0xe9,0xbe]
-
-s_ff1_i32_b32 s0, s104
-// GFX10: encoding: [0x68,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s105, s1
-// GFX10: encoding: [0x01,0x13,0xe9,0xbe]
-
-s_ff1_i32_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x13,0xfe,0xbe]
-
-s_ff1_i32_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x13,0xff,0xbe]
-
-s_ff1_i32_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x13,0xea,0xbe]
-
-s_ff1_i32_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x13,0xeb,0xbe]
-
-s_ff1_i32_b32 m0, s1
-// GFX10: encoding: [0x01,0x13,0xfc,0xbe]
-
-s_ff1_i32_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s0, m0
-// GFX10: encoding: [0x7c,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s0, 0
-// GFX10: encoding: [0x80,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s0, -1
-// GFX10: encoding: [0xc1,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x13,0x80,0xbe]
-
-s_ff1_i32_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x13,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff1_i32_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x13,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff1_i32_b64 s0, s[2:3]
-// GFX10: encoding: [0x02,0x14,0x80,0xbe]
-
-s_ff1_i32_b64 s105, s[102:103]
-// GFX10: encoding: [0x66,0x14,0xe9,0xbe]
-
-s_ff1_i32_b64 s0, s[102:103]
-// GFX10: encoding: [0x66,0x14,0x80,0xbe]
-
-s_ff1_i32_b64 s105, s[2:3]
-// GFX10: encoding: [0x02,0x14,0xe9,0xbe]
-
-s_ff1_i32_b64 exec_lo, s[2:3]
-// GFX10: encoding: [0x02,0x14,0xfe,0xbe]
-
-s_ff1_i32_b64 exec_hi, s[2:3]
-// GFX10: encoding: [0x02,0x14,0xff,0xbe]
-
-s_ff1_i32_b64 vcc_lo, s[2:3]
-// GFX10: encoding: [0x02,0x14,0xea,0xbe]
-
-s_ff1_i32_b64 vcc_hi, s[2:3]
-// GFX10: encoding: [0x02,0x14,0xeb,0xbe]
-
-s_ff1_i32_b64 m0, s[2:3]
-// GFX10: encoding: [0x02,0x14,0xfc,0xbe]
-
-s_ff1_i32_b64 s0, exec
-// GFX10: encoding: [0x7e,0x14,0x80,0xbe]
-
-s_ff1_i32_b64 s0, vcc
-// GFX10: encoding: [0x6a,0x14,0x80,0xbe]
-
-s_ff1_i32_b64 s0, 0
-// GFX10: encoding: [0x80,0x14,0x80,0xbe]
-
-s_ff1_i32_b64 s0, -1
-// GFX10: encoding: [0xc1,0x14,0x80,0xbe]
-
-s_ff1_i32_b64 s0, 0.5
-// GFX10: encoding: [0xf0,0x14,0x80,0xbe]
-
-s_ff1_i32_b64 s0, -4.0
-// GFX10: encoding: [0xf7,0x14,0x80,0xbe]
-
-s_ff1_i32_b64 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x14,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff1_i32_b64 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x14,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_b32 s0, s1
-// GFX10: encoding: [0x01,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s105, s104
-// GFX10: encoding: [0x68,0x15,0xe9,0xbe]
-
-s_flbit_i32_b32 s0, s104
-// GFX10: encoding: [0x68,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s105, s1
-// GFX10: encoding: [0x01,0x15,0xe9,0xbe]
-
-s_flbit_i32_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x15,0xfe,0xbe]
-
-s_flbit_i32_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x15,0xff,0xbe]
-
-s_flbit_i32_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x15,0xea,0xbe]
-
-s_flbit_i32_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x15,0xeb,0xbe]
-
-s_flbit_i32_b32 m0, s1
-// GFX10: encoding: [0x01,0x15,0xfc,0xbe]
-
-s_flbit_i32_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s0, m0
-// GFX10: encoding: [0x7c,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s0, 0
-// GFX10: encoding: [0x80,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s0, -1
-// GFX10: encoding: [0xc1,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x15,0x80,0xbe]
-
-s_flbit_i32_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x15,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x15,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_b64 s0, s[2:3]
-// GFX10: encoding: [0x02,0x16,0x80,0xbe]
-
-s_flbit_i32_b64 s105, s[102:103]
-// GFX10: encoding: [0x66,0x16,0xe9,0xbe]
-
-s_flbit_i32_b64 s0, s[102:103]
-// GFX10: encoding: [0x66,0x16,0x80,0xbe]
-
-s_flbit_i32_b64 s105, s[2:3]
-// GFX10: encoding: [0x02,0x16,0xe9,0xbe]
-
-s_flbit_i32_b64 exec_lo, s[2:3]
-// GFX10: encoding: [0x02,0x16,0xfe,0xbe]
-
-s_flbit_i32_b64 exec_hi, s[2:3]
-// GFX10: encoding: [0x02,0x16,0xff,0xbe]
-
-s_flbit_i32_b64 vcc_lo, s[2:3]
-// GFX10: encoding: [0x02,0x16,0xea,0xbe]
-
-s_flbit_i32_b64 vcc_hi, s[2:3]
-// GFX10: encoding: [0x02,0x16,0xeb,0xbe]
-
-s_flbit_i32_b64 m0, s[2:3]
-// GFX10: encoding: [0x02,0x16,0xfc,0xbe]
-
-s_flbit_i32_b64 s0, exec
-// GFX10: encoding: [0x7e,0x16,0x80,0xbe]
-
-s_flbit_i32_b64 s0, vcc
-// GFX10: encoding: [0x6a,0x16,0x80,0xbe]
-
-s_flbit_i32_b64 s0, 0
-// GFX10: encoding: [0x80,0x16,0x80,0xbe]
-
-s_flbit_i32_b64 s0, -1
-// GFX10: encoding: [0xc1,0x16,0x80,0xbe]
-
-s_flbit_i32_b64 s0, 0.5
-// GFX10: encoding: [0xf0,0x16,0x80,0xbe]
-
-s_flbit_i32_b64 s0, -4.0
-// GFX10: encoding: [0xf7,0x16,0x80,0xbe]
-
-s_flbit_i32_b64 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x16,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_b64 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x16,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32 s0, s1
-// GFX10: encoding: [0x01,0x17,0x80,0xbe]
-
-s_flbit_i32 s105, s104
-// GFX10: encoding: [0x68,0x17,0xe9,0xbe]
-
-s_flbit_i32 s0, s104
-// GFX10: encoding: [0x68,0x17,0x80,0xbe]
-
-s_flbit_i32 s105, s1
-// GFX10: encoding: [0x01,0x17,0xe9,0xbe]
-
-s_flbit_i32 exec_lo, s1
-// GFX10: encoding: [0x01,0x17,0xfe,0xbe]
-
-s_flbit_i32 exec_hi, s1
-// GFX10: encoding: [0x01,0x17,0xff,0xbe]
-
-s_flbit_i32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x17,0xea,0xbe]
-
-s_flbit_i32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x17,0xeb,0xbe]
-
-s_flbit_i32 m0, s1
-// GFX10: encoding: [0x01,0x17,0xfc,0xbe]
-
-s_flbit_i32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x17,0x80,0xbe]
-
-s_flbit_i32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x17,0x80,0xbe]
-
-s_flbit_i32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x17,0x80,0xbe]
-
-s_flbit_i32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x17,0x80,0xbe]
-
-s_flbit_i32 s0, m0
-// GFX10: encoding: [0x7c,0x17,0x80,0xbe]
-
-s_flbit_i32 s0, 0
-// GFX10: encoding: [0x80,0x17,0x80,0xbe]
-
-s_flbit_i32 s0, -1
-// GFX10: encoding: [0xc1,0x17,0x80,0xbe]
-
-s_flbit_i32 s0, 0.5
-// GFX10: encoding: [0xf0,0x17,0x80,0xbe]
-
-s_flbit_i32 s0, -4.0
-// GFX10: encoding: [0xf7,0x17,0x80,0xbe]
-
-s_flbit_i32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x17,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_i64 s0, s[2:3]
-// GFX10: encoding: [0x02,0x18,0x80,0xbe]
-
-s_flbit_i32_i64 s105, s[102:103]
-// GFX10: encoding: [0x66,0x18,0xe9,0xbe]
-
-s_flbit_i32_i64 s0, s[102:103]
-// GFX10: encoding: [0x66,0x18,0x80,0xbe]
-
-s_flbit_i32_i64 s105, s[2:3]
-// GFX10: encoding: [0x02,0x18,0xe9,0xbe]
-
-s_flbit_i32_i64 exec_lo, s[2:3]
-// GFX10: encoding: [0x02,0x18,0xfe,0xbe]
-
-s_flbit_i32_i64 exec_hi, s[2:3]
-// GFX10: encoding: [0x02,0x18,0xff,0xbe]
-
-s_flbit_i32_i64 vcc_lo, s[2:3]
-// GFX10: encoding: [0x02,0x18,0xea,0xbe]
-
-s_flbit_i32_i64 vcc_hi, s[2:3]
-// GFX10: encoding: [0x02,0x18,0xeb,0xbe]
-
-s_flbit_i32_i64 m0, s[2:3]
-// GFX10: encoding: [0x02,0x18,0xfc,0xbe]
-
-s_flbit_i32_i64 s0, exec
-// GFX10: encoding: [0x7e,0x18,0x80,0xbe]
-
-s_flbit_i32_i64 s0, vcc
-// GFX10: encoding: [0x6a,0x18,0x80,0xbe]
-
-s_flbit_i32_i64 s0, 0
-// GFX10: encoding: [0x80,0x18,0x80,0xbe]
-
-s_flbit_i32_i64 s0, -1
-// GFX10: encoding: [0xc1,0x18,0x80,0xbe]
-
-s_flbit_i32_i64 s0, 0.5
-// GFX10: encoding: [0xf0,0x18,0x80,0xbe]
-
-s_flbit_i32_i64 s0, -4.0
-// GFX10: encoding: [0xf7,0x18,0x80,0xbe]
-
-s_flbit_i32_i64 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x18,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_i64 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x18,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_sext_i32_i8 s0, s1
-// GFX10: encoding: [0x01,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s105, s104
-// GFX10: encoding: [0x68,0x19,0xe9,0xbe]
-
-s_sext_i32_i8 s0, s104
-// GFX10: encoding: [0x68,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s105, s1
-// GFX10: encoding: [0x01,0x19,0xe9,0xbe]
-
-s_sext_i32_i8 exec_lo, s1
-// GFX10: encoding: [0x01,0x19,0xfe,0xbe]
-
-s_sext_i32_i8 exec_hi, s1
-// GFX10: encoding: [0x01,0x19,0xff,0xbe]
-
-s_sext_i32_i8 vcc_lo, s1
-// GFX10: encoding: [0x01,0x19,0xea,0xbe]
-
-s_sext_i32_i8 vcc_hi, s1
-// GFX10: encoding: [0x01,0x19,0xeb,0xbe]
-
-s_sext_i32_i8 m0, s1
-// GFX10: encoding: [0x01,0x19,0xfc,0xbe]
-
-s_sext_i32_i8 s0, exec_lo
-// GFX10: encoding: [0x7e,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s0, exec_hi
-// GFX10: encoding: [0x7f,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s0, m0
-// GFX10: encoding: [0x7c,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s0, 0
-// GFX10: encoding: [0x80,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s0, -1
-// GFX10: encoding: [0xc1,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s0, 0.5
-// GFX10: encoding: [0xf0,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s0, -4.0
-// GFX10: encoding: [0xf7,0x19,0x80,0xbe]
-
-s_sext_i32_i8 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x19,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_sext_i32_i8 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_sext_i32_i16 s0, s1
-// GFX10: encoding: [0x01,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s105, s104
-// GFX10: encoding: [0x68,0x1a,0xe9,0xbe]
-
-s_sext_i32_i16 s0, s104
-// GFX10: encoding: [0x68,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s105, s1
-// GFX10: encoding: [0x01,0x1a,0xe9,0xbe]
-
-s_sext_i32_i16 exec_lo, s1
-// GFX10: encoding: [0x01,0x1a,0xfe,0xbe]
-
-s_sext_i32_i16 exec_hi, s1
-// GFX10: encoding: [0x01,0x1a,0xff,0xbe]
-
-s_sext_i32_i16 vcc_lo, s1
-// GFX10: encoding: [0x01,0x1a,0xea,0xbe]
-
-s_sext_i32_i16 vcc_hi, s1
-// GFX10: encoding: [0x01,0x1a,0xeb,0xbe]
-
-s_sext_i32_i16 m0, s1
-// GFX10: encoding: [0x01,0x1a,0xfc,0xbe]
-
-s_sext_i32_i16 s0, exec_lo
-// GFX10: encoding: [0x7e,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s0, exec_hi
-// GFX10: encoding: [0x7f,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s0, m0
-// GFX10: encoding: [0x7c,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s0, 0
-// GFX10: encoding: [0x80,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s0, -1
-// GFX10: encoding: [0xc1,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s0, 0.5
-// GFX10: encoding: [0xf0,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s0, -4.0
-// GFX10: encoding: [0xf7,0x1a,0x80,0xbe]
-
-s_sext_i32_i16 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x1a,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_sext_i32_i16 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x1a,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset0_b32 s0, s1
-// GFX10: encoding: [0x01,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s105, s104
-// GFX10: encoding: [0x68,0x1b,0xe9,0xbe]
-
-s_bitset0_b32 s0, s104
-// GFX10: encoding: [0x68,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s105, s1
-// GFX10: encoding: [0x01,0x1b,0xe9,0xbe]
-
-s_bitset0_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x1b,0xfe,0xbe]
-
-s_bitset0_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x1b,0xff,0xbe]
-
-s_bitset0_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x1b,0xea,0xbe]
-
-s_bitset0_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x1b,0xeb,0xbe]
-
-s_bitset0_b32 m0, s1
-// GFX10: encoding: [0x01,0x1b,0xfc,0xbe]
-
-s_bitset0_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s0, m0
-// GFX10: encoding: [0x7c,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s0, 0
-// GFX10: encoding: [0x80,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s0, -1
-// GFX10: encoding: [0xc1,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x1b,0x80,0xbe]
-
-s_bitset0_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x1b,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset0_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset0_b64 s[0:1], s2
-// GFX10: encoding: [0x02,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[104:105], s102
-// GFX10: encoding: [0x66,0x1c,0xe8,0xbe]
-
-s_bitset0_b64 s[0:1], s102
-// GFX10: encoding: [0x66,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[104:105], s2
-// GFX10: encoding: [0x02,0x1c,0xe8,0xbe]
-
-s_bitset0_b64 exec, s2
-// GFX10: encoding: [0x02,0x1c,0xfe,0xbe]
-
-s_bitset0_b64 vcc, s2
-// GFX10: encoding: [0x02,0x1c,0xea,0xbe]
-
-s_bitset0_b64 s[0:1], exec_lo
-// GFX10: encoding: [0x7e,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[0:1], exec_hi
-// GFX10: encoding: [0x7f,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[0:1], vcc_lo
-// GFX10: encoding: [0x6a,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[0:1], vcc_hi
-// GFX10: encoding: [0x6b,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[0:1], m0
-// GFX10: encoding: [0x7c,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x1c,0x80,0xbe]
-
-s_bitset0_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x1c,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset0_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x1c,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset1_b32 s0, s1
-// GFX10: encoding: [0x01,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s105, s104
-// GFX10: encoding: [0x68,0x1d,0xe9,0xbe]
-
-s_bitset1_b32 s0, s104
-// GFX10: encoding: [0x68,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s105, s1
-// GFX10: encoding: [0x01,0x1d,0xe9,0xbe]
-
-s_bitset1_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x1d,0xfe,0xbe]
-
-s_bitset1_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x1d,0xff,0xbe]
-
-s_bitset1_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x1d,0xea,0xbe]
-
-s_bitset1_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x1d,0xeb,0xbe]
-
-s_bitset1_b32 m0, s1
-// GFX10: encoding: [0x01,0x1d,0xfc,0xbe]
-
-s_bitset1_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s0, m0
-// GFX10: encoding: [0x7c,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s0, 0
-// GFX10: encoding: [0x80,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s0, -1
-// GFX10: encoding: [0xc1,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x1d,0x80,0xbe]
-
-s_bitset1_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x1d,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset1_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset1_b64 s[0:1], s2
-// GFX10: encoding: [0x02,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[104:105], s102
-// GFX10: encoding: [0x66,0x1e,0xe8,0xbe]
-
-s_bitset1_b64 s[0:1], s102
-// GFX10: encoding: [0x66,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[104:105], s2
-// GFX10: encoding: [0x02,0x1e,0xe8,0xbe]
-
-s_bitset1_b64 exec, s2
-// GFX10: encoding: [0x02,0x1e,0xfe,0xbe]
-
-s_bitset1_b64 vcc, s2
-// GFX10: encoding: [0x02,0x1e,0xea,0xbe]
-
-s_bitset1_b64 s[0:1], exec_lo
-// GFX10: encoding: [0x7e,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[0:1], exec_hi
-// GFX10: encoding: [0x7f,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[0:1], vcc_lo
-// GFX10: encoding: [0x6a,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[0:1], vcc_hi
-// GFX10: encoding: [0x6b,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[0:1], m0
-// GFX10: encoding: [0x7c,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x1e,0x80,0xbe]
-
-s_bitset1_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x1e,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset1_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x1e,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_getpc_b64 s[0:1]
-// GFX10: encoding: [0x00,0x1f,0x80,0xbe]
-
-s_getpc_b64 s[104:105]
-// GFX10: encoding: [0x00,0x1f,0xe8,0xbe]
-
-s_getpc_b64 exec
-// GFX10: encoding: [0x00,0x1f,0xfe,0xbe]
-
-s_getpc_b64 vcc
-// GFX10: encoding: [0x00,0x1f,0xea,0xbe]
-
-s_setpc_b64 s[0:1]
-// GFX10: encoding: [0x00,0x20,0x80,0xbe]
-
-s_setpc_b64 s[104:105]
-// GFX10: encoding: [0x68,0x20,0x80,0xbe]
-
-s_setpc_b64 vcc
-// GFX10: encoding: [0x6a,0x20,0x80,0xbe]
-
-s_swappc_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x21,0x80,0xbe]
-
-s_swappc_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x21,0xe8,0xbe]
-
-s_swappc_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x21,0x80,0xbe]
-
-s_swappc_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x21,0xe8,0xbe]
-
-s_swappc_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x21,0xea,0xbe]
-
-s_swappc_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x21,0x80,0xbe]
-
-s_rfe_b64 s[0:1]
-// GFX10: encoding: [0x00,0x22,0x80,0xbe]
-
-s_rfe_b64 s[104:105]
-// GFX10: encoding: [0x68,0x22,0x80,0xbe]
-
-s_rfe_b64 vcc
-// GFX10: encoding: [0x6a,0x22,0x80,0xbe]
-
-s_and_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x24,0x80,0xbe]
-
-s_and_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x24,0xe8,0xbe]
-
-s_and_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x24,0x80,0xbe]
-
-s_and_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x24,0xe8,0xbe]
-
-s_and_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x24,0xfe,0xbe]
-
-s_and_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x24,0xea,0xbe]
-
-s_and_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x24,0x80,0xbe]
-
-s_and_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x24,0x80,0xbe]
-
-s_and_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x24,0x80,0xbe]
-
-s_and_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x24,0x80,0xbe]
-
-s_and_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x24,0x80,0xbe]
-
-s_and_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x24,0x80,0xbe]
-
-s_and_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x24,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_and_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x24,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_or_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x25,0x80,0xbe]
-
-s_or_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x25,0xe8,0xbe]
-
-s_or_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x25,0x80,0xbe]
-
-s_or_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x25,0xe8,0xbe]
-
-s_or_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x25,0xfe,0xbe]
-
-s_or_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x25,0xea,0xbe]
-
-s_or_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x25,0x80,0xbe]
-
-s_or_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x25,0x80,0xbe]
-
-s_or_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x25,0x80,0xbe]
-
-s_or_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x25,0x80,0xbe]
-
-s_or_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x25,0x80,0xbe]
-
-s_or_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x25,0x80,0xbe]
-
-s_or_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x25,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_or_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xor_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x26,0x80,0xbe]
-
-s_xor_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x26,0xe8,0xbe]
-
-s_xor_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x26,0x80,0xbe]
-
-s_xor_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x26,0xe8,0xbe]
-
-s_xor_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x26,0xfe,0xbe]
-
-s_xor_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x26,0xea,0xbe]
-
-s_xor_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x26,0x80,0xbe]
-
-s_xor_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x26,0x80,0xbe]
-
-s_xor_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x26,0x80,0xbe]
-
-s_xor_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x26,0x80,0xbe]
-
-s_xor_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x26,0x80,0xbe]
-
-s_xor_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x26,0x80,0xbe]
-
-s_xor_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x26,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xor_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x26,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn2_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x27,0x80,0xbe]
-
-s_andn2_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x27,0xe8,0xbe]
-
-s_andn2_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x27,0x80,0xbe]
-
-s_andn2_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x27,0xe8,0xbe]
-
-s_andn2_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x27,0xfe,0xbe]
-
-s_andn2_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x27,0xea,0xbe]
-
-s_andn2_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x27,0x80,0xbe]
-
-s_andn2_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x27,0x80,0xbe]
-
-s_andn2_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x27,0x80,0xbe]
-
-s_andn2_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x27,0x80,0xbe]
-
-s_andn2_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x27,0x80,0xbe]
-
-s_andn2_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x27,0x80,0xbe]
-
-s_andn2_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x27,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn2_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_orn2_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x28,0x80,0xbe]
-
-s_orn2_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x28,0xe8,0xbe]
-
-s_orn2_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x28,0x80,0xbe]
-
-s_orn2_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x28,0xe8,0xbe]
-
-s_orn2_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x28,0xfe,0xbe]
-
-s_orn2_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x28,0xea,0xbe]
-
-s_orn2_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x28,0x80,0xbe]
-
-s_orn2_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x28,0x80,0xbe]
-
-s_orn2_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x28,0x80,0xbe]
-
-s_orn2_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x28,0x80,0xbe]
-
-s_orn2_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x28,0x80,0xbe]
-
-s_orn2_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x28,0x80,0xbe]
-
-s_orn2_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x28,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_orn2_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x28,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nand_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x29,0x80,0xbe]
-
-s_nand_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x29,0xe8,0xbe]
-
-s_nand_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x29,0x80,0xbe]
-
-s_nand_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x29,0xe8,0xbe]
-
-s_nand_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x29,0xfe,0xbe]
-
-s_nand_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x29,0xea,0xbe]
-
-s_nand_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x29,0x80,0xbe]
-
-s_nand_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x29,0x80,0xbe]
-
-s_nand_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x29,0x80,0xbe]
-
-s_nand_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x29,0x80,0xbe]
-
-s_nand_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x29,0x80,0xbe]
-
-s_nand_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x29,0x80,0xbe]
-
-s_nand_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x29,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nand_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nor_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x2a,0x80,0xbe]
-
-s_nor_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x2a,0xe8,0xbe]
-
-s_nor_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x2a,0x80,0xbe]
-
-s_nor_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x2a,0xe8,0xbe]
-
-s_nor_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x2a,0xfe,0xbe]
-
-s_nor_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x2a,0xea,0xbe]
-
-s_nor_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x2a,0x80,0xbe]
-
-s_nor_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x2a,0x80,0xbe]
-
-s_nor_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x2a,0x80,0xbe]
-
-s_nor_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x2a,0x80,0xbe]
-
-s_nor_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x2a,0x80,0xbe]
-
-s_nor_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x2a,0x80,0xbe]
-
-s_nor_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x2a,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nor_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x2a,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xnor_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x2b,0x80,0xbe]
-
-s_xnor_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x2b,0xe8,0xbe]
-
-s_xnor_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x2b,0x80,0xbe]
-
-s_xnor_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x2b,0xe8,0xbe]
-
-s_xnor_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x2b,0xfe,0xbe]
-
-s_xnor_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x2b,0xea,0xbe]
-
-s_xnor_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x2b,0x80,0xbe]
-
-s_xnor_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x2b,0x80,0xbe]
-
-s_xnor_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x2b,0x80,0xbe]
-
-s_xnor_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x2b,0x80,0xbe]
-
-s_xnor_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x2b,0x80,0xbe]
-
-s_xnor_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x2b,0x80,0xbe]
-
-s_xnor_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x2b,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xnor_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_quadmask_b32 s0, s1
-// GFX10: encoding: [0x01,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s105, s104
-// GFX10: encoding: [0x68,0x2c,0xe9,0xbe]
-
-s_quadmask_b32 s0, s104
-// GFX10: encoding: [0x68,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s105, s1
-// GFX10: encoding: [0x01,0x2c,0xe9,0xbe]
-
-s_quadmask_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x2c,0xfe,0xbe]
-
-s_quadmask_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x2c,0xff,0xbe]
-
-s_quadmask_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x2c,0xea,0xbe]
-
-s_quadmask_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x2c,0xeb,0xbe]
-
-s_quadmask_b32 m0, s1
-// GFX10: encoding: [0x01,0x2c,0xfc,0xbe]
-
-s_quadmask_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s0, m0
-// GFX10: encoding: [0x7c,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s0, 0
-// GFX10: encoding: [0x80,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s0, -1
-// GFX10: encoding: [0xc1,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x2c,0x80,0xbe]
-
-s_quadmask_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x2c,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_quadmask_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x2c,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_quadmask_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x2d,0x80,0xbe]
-
-s_quadmask_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x2d,0xe8,0xbe]
-
-s_quadmask_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x2d,0x80,0xbe]
-
-s_quadmask_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x2d,0xe8,0xbe]
-
-s_quadmask_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x2d,0xfe,0xbe]
-
-s_quadmask_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x2d,0xea,0xbe]
-
-s_quadmask_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x2d,0x80,0xbe]
-
-s_quadmask_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x2d,0x80,0xbe]
-
-s_quadmask_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x2d,0x80,0xbe]
-
-s_quadmask_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x2d,0x80,0xbe]
-
-s_quadmask_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x2d,0x80,0xbe]
-
-s_quadmask_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x2d,0x80,0xbe]
-
-s_quadmask_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x2d,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_quadmask_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_movrels_b32 s0, s1
-// GFX10: encoding: [0x01,0x2e,0x80,0xbe]
-
-s_movrels_b32 s105, s104
-// GFX10: encoding: [0x68,0x2e,0xe9,0xbe]
-
-s_movrels_b32 s0, s104
-// GFX10: encoding: [0x68,0x2e,0x80,0xbe]
-
-s_movrels_b32 s105, s1
-// GFX10: encoding: [0x01,0x2e,0xe9,0xbe]
-
-s_movrels_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x2e,0xfe,0xbe]
-
-s_movrels_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x2e,0xff,0xbe]
-
-s_movrels_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x2e,0xea,0xbe]
-
-s_movrels_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x2e,0xeb,0xbe]
-
-s_movrels_b32 m0, s1
-// GFX10: encoding: [0x01,0x2e,0xfc,0xbe]
-
-s_movrels_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x2e,0x80,0xbe]
-
-s_movrels_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x2e,0x80,0xbe]
-
-s_movrels_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x2f,0x80,0xbe]
-
-s_movrels_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x2f,0xe8,0xbe]
-
-s_movrels_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x2f,0x80,0xbe]
-
-s_movrels_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x2f,0xe8,0xbe]
-
-s_movrels_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x2f,0xfe,0xbe]
-
-s_movrels_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x2f,0xea,0xbe]
-
-s_movrels_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x2f,0x80,0xbe]
-
-s_movreld_b32 s0, s1
-// GFX10: encoding: [0x01,0x30,0x80,0xbe]
-
-s_movreld_b32 s105, s104
-// GFX10: encoding: [0x68,0x30,0xe9,0xbe]
-
-s_movreld_b32 s0, s104
-// GFX10: encoding: [0x68,0x30,0x80,0xbe]
-
-s_movreld_b32 s105, s1
-// GFX10: encoding: [0x01,0x30,0xe9,0xbe]
-
-s_movreld_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x30,0xea,0xbe]
-
-s_movreld_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x30,0xeb,0xbe]
-
-s_movreld_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x30,0x80,0xbe]
-
-s_movreld_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x30,0x80,0xbe]
-
-s_movreld_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x30,0x80,0xbe]
-
-s_movreld_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x30,0x80,0xbe]
-
-s_movreld_b32 s0, m0
-// GFX10: encoding: [0x7c,0x30,0x80,0xbe]
-
-s_movreld_b32 s0, 0
-// GFX10: encoding: [0x80,0x30,0x80,0xbe]
-
-s_movreld_b32 s0, -1
-// GFX10: encoding: [0xc1,0x30,0x80,0xbe]
-
-s_movreld_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x30,0x80,0xbe]
-
-s_movreld_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x30,0x80,0xbe]
-
-s_movreld_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x30,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_movreld_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x30,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_movreld_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x31,0x80,0xbe]
-
-s_movreld_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x31,0xe8,0xbe]
-
-s_movreld_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x31,0x80,0xbe]
-
-s_movreld_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x31,0xe8,0xbe]
-
-s_movreld_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x31,0xea,0xbe]
-
-s_movreld_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x31,0x80,0xbe]
-
-s_movreld_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x31,0x80,0xbe]
-
-s_movreld_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x31,0x80,0xbe]
-
-s_movreld_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x31,0x80,0xbe]
-
-s_movreld_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x31,0x80,0xbe]
-
-s_movreld_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x31,0x80,0xbe]
-
-s_movreld_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x31,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_movreld_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_abs_i32 s0, s1
-// GFX10: encoding: [0x01,0x34,0x80,0xbe]
-
-s_abs_i32 s105, s104
-// GFX10: encoding: [0x68,0x34,0xe9,0xbe]
-
-s_abs_i32 s0, s104
-// GFX10: encoding: [0x68,0x34,0x80,0xbe]
-
-s_abs_i32 s105, s1
-// GFX10: encoding: [0x01,0x34,0xe9,0xbe]
-
-s_abs_i32 exec_lo, s1
-// GFX10: encoding: [0x01,0x34,0xfe,0xbe]
-
-s_abs_i32 exec_hi, s1
-// GFX10: encoding: [0x01,0x34,0xff,0xbe]
-
-s_abs_i32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x34,0xea,0xbe]
-
-s_abs_i32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x34,0xeb,0xbe]
-
-s_abs_i32 m0, s1
-// GFX10: encoding: [0x01,0x34,0xfc,0xbe]
-
-s_abs_i32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x34,0x80,0xbe]
-
-s_abs_i32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x34,0x80,0xbe]
-
-s_abs_i32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x34,0x80,0xbe]
-
-s_abs_i32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x34,0x80,0xbe]
-
-s_abs_i32 s0, m0
-// GFX10: encoding: [0x7c,0x34,0x80,0xbe]
-
-s_abs_i32 s0, 0
-// GFX10: encoding: [0x80,0x34,0x80,0xbe]
-
-s_abs_i32 s0, -1
-// GFX10: encoding: [0xc1,0x34,0x80,0xbe]
-
-s_abs_i32 s0, 0.5
-// GFX10: encoding: [0xf0,0x34,0x80,0xbe]
-
-s_abs_i32 s0, -4.0
-// GFX10: encoding: [0xf7,0x34,0x80,0xbe]
-
-s_abs_i32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x34,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_abs_i32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x34,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn1_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x37,0x80,0xbe]
-
-s_andn1_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x37,0xe8,0xbe]
-
-s_andn1_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x37,0x80,0xbe]
-
-s_andn1_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x37,0xe8,0xbe]
-
-s_andn1_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x37,0xfe,0xbe]
-
-s_andn1_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x37,0xea,0xbe]
-
-s_andn1_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x37,0x80,0xbe]
-
-s_andn1_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x37,0x80,0xbe]
-
-s_andn1_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x37,0x80,0xbe]
-
-s_andn1_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x37,0x80,0xbe]
-
-s_andn1_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x37,0x80,0xbe]
-
-s_andn1_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x37,0x80,0xbe]
-
-s_andn1_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x37,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn1_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_orn1_saveexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x38,0x80,0xbe]
-
-s_orn1_saveexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x38,0xe8,0xbe]
-
-s_orn1_saveexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x38,0x80,0xbe]
-
-s_orn1_saveexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x38,0xe8,0xbe]
-
-s_orn1_saveexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x38,0xfe,0xbe]
-
-s_orn1_saveexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x38,0xea,0xbe]
-
-s_orn1_saveexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x38,0x80,0xbe]
-
-s_orn1_saveexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x38,0x80,0xbe]
-
-s_orn1_saveexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x38,0x80,0xbe]
-
-s_orn1_saveexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x38,0x80,0xbe]
-
-s_orn1_saveexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x38,0x80,0xbe]
-
-s_orn1_saveexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x38,0x80,0xbe]
-
-s_orn1_saveexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x38,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_orn1_saveexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x38,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn1_wrexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x39,0x80,0xbe]
-
-s_andn1_wrexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x39,0xe8,0xbe]
-
-s_andn1_wrexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x39,0x80,0xbe]
-
-s_andn1_wrexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x39,0xe8,0xbe]
-
-s_andn1_wrexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x39,0xfe,0xbe]
-
-s_andn1_wrexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x39,0xea,0xbe]
-
-s_andn1_wrexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x39,0x80,0xbe]
-
-s_andn1_wrexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x39,0x80,0xbe]
-
-s_andn1_wrexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x39,0x80,0xbe]
-
-s_andn1_wrexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x39,0x80,0xbe]
-
-s_andn1_wrexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x39,0x80,0xbe]
-
-s_andn1_wrexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x39,0x80,0xbe]
-
-s_andn1_wrexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x39,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn1_wrexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x39,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn2_wrexec_b64 s[0:1], s[2:3]
-// GFX10: encoding: [0x02,0x3a,0x80,0xbe]
-
-s_andn2_wrexec_b64 s[104:105], s[102:103]
-// GFX10: encoding: [0x66,0x3a,0xe8,0xbe]
-
-s_andn2_wrexec_b64 s[0:1], s[102:103]
-// GFX10: encoding: [0x66,0x3a,0x80,0xbe]
-
-s_andn2_wrexec_b64 s[104:105], s[2:3]
-// GFX10: encoding: [0x02,0x3a,0xe8,0xbe]
-
-s_andn2_wrexec_b64 exec, s[2:3]
-// GFX10: encoding: [0x02,0x3a,0xfe,0xbe]
-
-s_andn2_wrexec_b64 vcc, s[2:3]
-// GFX10: encoding: [0x02,0x3a,0xea,0xbe]
-
-s_andn2_wrexec_b64 s[0:1], exec
-// GFX10: encoding: [0x7e,0x3a,0x80,0xbe]
-
-s_andn2_wrexec_b64 s[0:1], vcc
-// GFX10: encoding: [0x6a,0x3a,0x80,0xbe]
-
-s_andn2_wrexec_b64 s[0:1], 0
-// GFX10: encoding: [0x80,0x3a,0x80,0xbe]
-
-s_andn2_wrexec_b64 s[0:1], -1
-// GFX10: encoding: [0xc1,0x3a,0x80,0xbe]
-
-s_andn2_wrexec_b64 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x3a,0x80,0xbe]
-
-s_andn2_wrexec_b64 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x3a,0x80,0xbe]
-
-s_andn2_wrexec_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x3a,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn2_wrexec_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x3a,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitreplicate_b64_b32 s[0:1], s2
-// GFX10: encoding: [0x02,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[104:105], s102
-// GFX10: encoding: [0x66,0x3b,0xe8,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], s102
-// GFX10: encoding: [0x66,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[104:105], s2
-// GFX10: encoding: [0x02,0x3b,0xe8,0xbe]
-
-s_bitreplicate_b64_b32 exec, s2
-// GFX10: encoding: [0x02,0x3b,0xfe,0xbe]
-
-s_bitreplicate_b64_b32 vcc, s2
-// GFX10: encoding: [0x02,0x3b,0xea,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], exec_lo
-// GFX10: encoding: [0x7e,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], exec_hi
-// GFX10: encoding: [0x7f,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], vcc_lo
-// GFX10: encoding: [0x6a,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], vcc_hi
-// GFX10: encoding: [0x6b,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], m0
-// GFX10: encoding: [0x7c,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], 0
-// GFX10: encoding: [0x80,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], -1
-// GFX10: encoding: [0xc1,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], 0.5
-// GFX10: encoding: [0xf0,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], -4.0
-// GFX10: encoding: [0xf7,0x3b,0x80,0xbe]
-
-s_bitreplicate_b64_b32 s[0:1], 0x3f717273
-// GFX10: encoding: [0xff,0x3b,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitreplicate_b64_b32 s[0:1], 0xaf123456
-// GFX10: encoding: [0xff,0x3b,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_and_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x3c,0xe9,0xbe]
-
-s_and_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x3c,0xe9,0xbe]
-
-s_and_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x3c,0xfe,0xbe]
-
-s_and_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x3c,0xff,0xbe]
-
-s_and_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x3c,0xea,0xbe]
-
-s_and_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x3c,0xeb,0xbe]
-
-s_and_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x3c,0xfc,0xbe]
-
-s_and_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x3c,0x80,0xbe]
-
-s_and_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x3c,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_and_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x3c,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_or_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x3d,0xe9,0xbe]
-
-s_or_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x3d,0xe9,0xbe]
-
-s_or_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x3d,0xfe,0xbe]
-
-s_or_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x3d,0xff,0xbe]
-
-s_or_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x3d,0xea,0xbe]
-
-s_or_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x3d,0xeb,0xbe]
-
-s_or_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x3d,0xfc,0xbe]
-
-s_or_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x3d,0x80,0xbe]
-
-s_or_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x3d,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_or_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x3d,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xor_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x3e,0xe9,0xbe]
-
-s_xor_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x3e,0xe9,0xbe]
-
-s_xor_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x3e,0xfe,0xbe]
-
-s_xor_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x3e,0xff,0xbe]
-
-s_xor_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x3e,0xea,0xbe]
-
-s_xor_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x3e,0xeb,0xbe]
-
-s_xor_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x3e,0xfc,0xbe]
-
-s_xor_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x3e,0x80,0xbe]
-
-s_xor_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x3e,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xor_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x3e,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn2_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x3f,0xe9,0xbe]
-
-s_andn2_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x3f,0xe9,0xbe]
-
-s_andn2_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x3f,0xfe,0xbe]
-
-s_andn2_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x3f,0xff,0xbe]
-
-s_andn2_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x3f,0xea,0xbe]
-
-s_andn2_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x3f,0xeb,0xbe]
-
-s_andn2_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x3f,0xfc,0xbe]
-
-s_andn2_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x3f,0x80,0xbe]
-
-s_andn2_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x3f,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn2_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x3f,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_orn2_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x40,0xe9,0xbe]
-
-s_orn2_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x40,0xe9,0xbe]
-
-s_orn2_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x40,0xfe,0xbe]
-
-s_orn2_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x40,0xff,0xbe]
-
-s_orn2_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x40,0xea,0xbe]
-
-s_orn2_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x40,0xeb,0xbe]
-
-s_orn2_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x40,0xfc,0xbe]
-
-s_orn2_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x40,0x80,0xbe]
-
-s_orn2_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x40,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_orn2_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x40,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nand_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x41,0xe9,0xbe]
-
-s_nand_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x41,0xe9,0xbe]
-
-s_nand_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x41,0xfe,0xbe]
-
-s_nand_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x41,0xff,0xbe]
-
-s_nand_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x41,0xea,0xbe]
-
-s_nand_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x41,0xeb,0xbe]
-
-s_nand_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x41,0xfc,0xbe]
-
-s_nand_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x41,0x80,0xbe]
-
-s_nand_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x41,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nand_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x41,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nor_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x42,0xe9,0xbe]
-
-s_nor_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x42,0xe9,0xbe]
-
-s_nor_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x42,0xfe,0xbe]
-
-s_nor_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x42,0xff,0xbe]
-
-s_nor_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x42,0xea,0xbe]
-
-s_nor_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x42,0xeb,0xbe]
-
-s_nor_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x42,0xfc,0xbe]
-
-s_nor_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x42,0x80,0xbe]
-
-s_nor_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x42,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nor_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x42,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xnor_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x43,0xe9,0xbe]
-
-s_xnor_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x43,0xe9,0xbe]
-
-s_xnor_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x43,0xfe,0xbe]
-
-s_xnor_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x43,0xff,0xbe]
-
-s_xnor_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x43,0xea,0xbe]
-
-s_xnor_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x43,0xeb,0xbe]
-
-s_xnor_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x43,0xfc,0xbe]
-
-s_xnor_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x43,0x80,0xbe]
-
-s_xnor_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x43,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xnor_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn1_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x44,0xe9,0xbe]
-
-s_andn1_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x44,0xe9,0xbe]
-
-s_andn1_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x44,0xfe,0xbe]
-
-s_andn1_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x44,0xff,0xbe]
-
-s_andn1_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x44,0xea,0xbe]
-
-s_andn1_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x44,0xeb,0xbe]
-
-s_andn1_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x44,0xfc,0xbe]
-
-s_andn1_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x44,0x80,0xbe]
-
-s_andn1_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x44,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn1_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x44,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_orn1_saveexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x45,0xe9,0xbe]
-
-s_orn1_saveexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x45,0xe9,0xbe]
-
-s_orn1_saveexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x45,0xfe,0xbe]
-
-s_orn1_saveexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x45,0xff,0xbe]
-
-s_orn1_saveexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x45,0xea,0xbe]
-
-s_orn1_saveexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x45,0xeb,0xbe]
-
-s_orn1_saveexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x45,0xfc,0xbe]
-
-s_orn1_saveexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x45,0x80,0xbe]
-
-s_orn1_saveexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x45,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_orn1_saveexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x45,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn1_wrexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x46,0xe9,0xbe]
-
-s_andn1_wrexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x46,0xe9,0xbe]
-
-s_andn1_wrexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x46,0xfe,0xbe]
-
-s_andn1_wrexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x46,0xff,0xbe]
-
-s_andn1_wrexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x46,0xea,0xbe]
-
-s_andn1_wrexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x46,0xeb,0xbe]
-
-s_andn1_wrexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x46,0xfc,0xbe]
-
-s_andn1_wrexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x46,0x80,0xbe]
-
-s_andn1_wrexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x46,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn1_wrexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x46,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn2_wrexec_b32 s0, s1
-// GFX10: encoding: [0x01,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s105, s104
-// GFX10: encoding: [0x68,0x47,0xe9,0xbe]
-
-s_andn2_wrexec_b32 s0, s104
-// GFX10: encoding: [0x68,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s105, s1
-// GFX10: encoding: [0x01,0x47,0xe9,0xbe]
-
-s_andn2_wrexec_b32 exec_lo, s1
-// GFX10: encoding: [0x01,0x47,0xfe,0xbe]
-
-s_andn2_wrexec_b32 exec_hi, s1
-// GFX10: encoding: [0x01,0x47,0xff,0xbe]
-
-s_andn2_wrexec_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x47,0xea,0xbe]
-
-s_andn2_wrexec_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x47,0xeb,0xbe]
-
-s_andn2_wrexec_b32 m0, s1
-// GFX10: encoding: [0x01,0x47,0xfc,0xbe]
-
-s_andn2_wrexec_b32 s0, exec_lo
-// GFX10: encoding: [0x7e,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s0, exec_hi
-// GFX10: encoding: [0x7f,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s0, m0
-// GFX10: encoding: [0x7c,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s0, 0
-// GFX10: encoding: [0x80,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s0, -1
-// GFX10: encoding: [0xc1,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s0, 0.5
-// GFX10: encoding: [0xf0,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s0, -4.0
-// GFX10: encoding: [0xf7,0x47,0x80,0xbe]
-
-s_andn2_wrexec_b32 s0, 0x3f717273
-// GFX10: encoding: [0xff,0x47,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn2_wrexec_b32 s0, 0xaf123456
-// GFX10: encoding: [0xff,0x47,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_movrelsd_2_b32 s0, s1
-// GFX10: encoding: [0x01,0x49,0x80,0xbe]
-
-s_movrelsd_2_b32 s105, s104
-// GFX10: encoding: [0x68,0x49,0xe9,0xbe]
-
-s_movrelsd_2_b32 s0, s104
-// GFX10: encoding: [0x68,0x49,0x80,0xbe]
-
-s_movrelsd_2_b32 s105, s1
-// GFX10: encoding: [0x01,0x49,0xe9,0xbe]
-
-s_movrelsd_2_b32 vcc_lo, s1
-// GFX10: encoding: [0x01,0x49,0xea,0xbe]
-
-s_movrelsd_2_b32 vcc_hi, s1
-// GFX10: encoding: [0x01,0x49,0xeb,0xbe]
-
-s_movrelsd_2_b32 s0, vcc_lo
-// GFX10: encoding: [0x6a,0x49,0x80,0xbe]
-
-s_movrelsd_2_b32 s0, vcc_hi
-// GFX10: encoding: [0x6b,0x49,0x80,0xbe]
-
-//===----------------------------------------------------------------------===//
-// ENC_SOP2.
-//===----------------------------------------------------------------------===//
-
-s_add_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x80]
-
-s_add_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x80]
-
-s_add_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x80]
-
-s_add_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x80]
-
-s_add_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x80]
-
-s_add_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x80]
-
-s_add_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x80]
-
-s_add_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x80]
-
-s_add_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x80]
-
-s_add_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x80]
-
-s_add_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x80]
-
-s_add_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x80]
-
-s_add_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x80]
-
-s_add_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x80]
-
-s_add_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x80]
-
-s_add_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x80]
-
-s_add_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x80]
-
-s_add_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x80]
-
-s_add_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x80]
-
-s_add_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x80]
-
-s_add_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x80]
-
-s_add_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x80]
-
-s_add_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x80,0x73,0x72,0x71,0x3f]
-
-s_add_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x80,0x56,0x34,0x12,0xaf]
-
-s_add_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x80]
-
-s_add_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x80]
-
-s_add_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x80]
-
-s_add_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x80]
-
-s_add_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x80]
-
-s_add_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x80]
-
-s_add_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x80]
-
-s_add_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x80]
-
-s_add_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x80]
-
-s_add_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x80,0x73,0x72,0x71,0x3f]
-
-s_add_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x80,0x56,0x34,0x12,0xaf]
-
-s_sub_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x80]
-
-s_sub_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x80]
-
-s_sub_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x80]
-
-s_sub_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x80]
-
-s_sub_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x80]
-
-s_sub_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x80]
-
-s_sub_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x80]
-
-s_sub_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x80]
-
-s_sub_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x80]
-
-s_sub_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x80]
-
-s_sub_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x80]
-
-s_sub_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x80]
-
-s_sub_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x80]
-
-s_sub_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x80]
-
-s_sub_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x80]
-
-s_sub_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x80]
-
-s_sub_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x80]
-
-s_sub_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x80]
-
-s_sub_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x80]
-
-s_sub_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x80]
-
-s_sub_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x80]
-
-s_sub_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x80]
-
-s_sub_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x80,0x73,0x72,0x71,0x3f]
-
-s_sub_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x80,0x56,0x34,0x12,0xaf]
-
-s_sub_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x80]
-
-s_sub_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x80]
-
-s_sub_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x80]
-
-s_sub_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x80]
-
-s_sub_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x80]
-
-s_sub_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x80]
-
-s_sub_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x80]
-
-s_sub_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x80]
-
-s_sub_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x80]
-
-s_sub_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x80,0x73,0x72,0x71,0x3f]
-
-s_sub_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x80,0x56,0x34,0x12,0xaf]
-
-s_add_i32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x81]
-
-s_add_i32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x81]
-
-s_add_i32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x81]
-
-s_add_i32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x81]
-
-s_add_i32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x81]
-
-s_add_i32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x81]
-
-s_add_i32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x81]
-
-s_add_i32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x81]
-
-s_add_i32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x81]
-
-s_add_i32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x81]
-
-s_add_i32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x81]
-
-s_add_i32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x81]
-
-s_add_i32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x81]
-
-s_add_i32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x81]
-
-s_add_i32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x81]
-
-s_add_i32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x81]
-
-s_add_i32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x81]
-
-s_add_i32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x81]
-
-s_add_i32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x81]
-
-s_add_i32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x81]
-
-s_add_i32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x81]
-
-s_add_i32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x81]
-
-s_add_i32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x81,0x73,0x72,0x71,0x3f]
-
-s_add_i32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x81,0x56,0x34,0x12,0xaf]
-
-s_add_i32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x81]
-
-s_add_i32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x81]
-
-s_add_i32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x81]
-
-s_add_i32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x81]
-
-s_add_i32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x81]
-
-s_add_i32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x81]
-
-s_add_i32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x81]
-
-s_add_i32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x81]
-
-s_add_i32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x81]
-
-s_add_i32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x81,0x73,0x72,0x71,0x3f]
-
-s_add_i32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x81,0x56,0x34,0x12,0xaf]
-
-s_sub_i32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x81]
-
-s_sub_i32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x81]
-
-s_sub_i32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x81]
-
-s_sub_i32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x81]
-
-s_sub_i32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x81]
-
-s_sub_i32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x81]
-
-s_sub_i32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x81]
-
-s_sub_i32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x81]
-
-s_sub_i32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x81]
-
-s_sub_i32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x81]
-
-s_sub_i32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x81]
-
-s_sub_i32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x81]
-
-s_sub_i32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x81]
-
-s_sub_i32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x81]
-
-s_sub_i32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x81]
-
-s_sub_i32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x81]
-
-s_sub_i32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x81]
-
-s_sub_i32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x81]
-
-s_sub_i32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x81]
-
-s_sub_i32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x81]
-
-s_sub_i32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x81]
-
-s_sub_i32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x81]
-
-s_sub_i32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x81,0x73,0x72,0x71,0x3f]
-
-s_sub_i32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x81,0x56,0x34,0x12,0xaf]
-
-s_sub_i32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x81]
-
-s_sub_i32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x81]
-
-s_sub_i32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x81]
-
-s_sub_i32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x81]
-
-s_sub_i32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x81]
-
-s_sub_i32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x81]
-
-s_sub_i32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x81]
-
-s_sub_i32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x81]
-
-s_sub_i32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x81]
-
-s_sub_i32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x81,0x73,0x72,0x71,0x3f]
-
-s_sub_i32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x81,0x56,0x34,0x12,0xaf]
-
-s_addc_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x82]
-
-s_addc_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x82]
-
-s_addc_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x82]
-
-s_addc_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x82]
-
-s_addc_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x82]
-
-s_addc_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x82]
-
-s_addc_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x82]
-
-s_addc_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x82]
-
-s_addc_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x82]
-
-s_addc_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x82]
-
-s_addc_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x82]
-
-s_addc_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x82]
-
-s_addc_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x82]
-
-s_addc_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x82]
-
-s_addc_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x82]
-
-s_addc_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x82]
-
-s_addc_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x82]
-
-s_addc_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x82]
-
-s_addc_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x82]
-
-s_addc_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x82]
-
-s_addc_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x82]
-
-s_addc_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x82]
-
-s_addc_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x82,0x73,0x72,0x71,0x3f]
-
-s_addc_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x82,0x56,0x34,0x12,0xaf]
-
-s_addc_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x82]
-
-s_addc_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x82]
-
-s_addc_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x82]
-
-s_addc_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x82]
-
-s_addc_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x82]
-
-s_addc_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x82]
-
-s_addc_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x82]
-
-s_addc_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x82]
-
-s_addc_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x82]
-
-s_addc_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x82,0x73,0x72,0x71,0x3f]
-
-s_addc_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x82,0x56,0x34,0x12,0xaf]
-
-s_subb_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x82]
-
-s_subb_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x82]
-
-s_subb_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x82]
-
-s_subb_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x82]
-
-s_subb_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x82]
-
-s_subb_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x82]
-
-s_subb_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x82]
-
-s_subb_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x82]
-
-s_subb_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x82]
-
-s_subb_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x82]
-
-s_subb_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x82]
-
-s_subb_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x82]
-
-s_subb_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x82]
-
-s_subb_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x82]
-
-s_subb_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x82]
-
-s_subb_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x82]
-
-s_subb_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x82]
-
-s_subb_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x82]
-
-s_subb_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x82]
-
-s_subb_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x82]
-
-s_subb_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x82]
-
-s_subb_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x82]
-
-s_subb_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x82,0x73,0x72,0x71,0x3f]
-
-s_subb_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x82,0x56,0x34,0x12,0xaf]
-
-s_subb_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x82]
-
-s_subb_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x82]
-
-s_subb_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x82]
-
-s_subb_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x82]
-
-s_subb_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x82]
-
-s_subb_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x82]
-
-s_subb_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x82]
-
-s_subb_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x82]
-
-s_subb_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x82]
-
-s_subb_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x82,0x73,0x72,0x71,0x3f]
-
-s_subb_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x82,0x56,0x34,0x12,0xaf]
-
-s_min_i32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x83]
-
-s_min_i32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x83]
-
-s_min_i32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x83]
-
-s_min_i32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x83]
-
-s_min_i32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x83]
-
-s_min_i32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x83]
-
-s_min_i32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x83]
-
-s_min_i32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x83]
-
-s_min_i32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x83]
-
-s_min_i32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x83]
-
-s_min_i32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x83]
-
-s_min_i32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x83]
-
-s_min_i32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x83]
-
-s_min_i32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x83]
-
-s_min_i32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x83]
-
-s_min_i32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x83]
-
-s_min_i32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x83]
-
-s_min_i32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x83]
-
-s_min_i32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x83]
-
-s_min_i32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x83]
-
-s_min_i32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x83]
-
-s_min_i32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x83]
-
-s_min_i32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_i32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_i32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x83]
-
-s_min_i32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x83]
-
-s_min_i32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x83]
-
-s_min_i32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x83]
-
-s_min_i32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x83]
-
-s_min_i32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x83]
-
-s_min_i32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x83]
-
-s_min_i32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x83]
-
-s_min_i32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x83]
-
-s_min_i32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_i32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x83]
-
-s_min_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x83]
-
-s_min_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x83]
-
-s_min_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x83]
-
-s_min_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x83]
-
-s_min_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x83]
-
-s_min_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x83]
-
-s_min_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x83]
-
-s_min_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x83]
-
-s_min_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x83]
-
-s_min_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x83]
-
-s_min_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x83]
-
-s_min_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x83]
-
-s_min_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x83]
-
-s_min_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x83]
-
-s_min_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x83]
-
-s_min_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x83]
-
-s_min_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x83]
-
-s_min_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x83]
-
-s_min_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x83]
-
-s_min_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x83]
-
-s_min_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x83]
-
-s_min_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x83]
-
-s_min_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x83]
-
-s_min_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x83]
-
-s_min_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x83]
-
-s_min_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x83]
-
-s_min_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x83]
-
-s_min_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x83]
-
-s_min_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x83]
-
-s_min_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x83]
-
-s_min_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x83,0x56,0x34,0x12,0xaf]
-
-s_max_i32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x84]
-
-s_max_i32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x84]
-
-s_max_i32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x84]
-
-s_max_i32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x84]
-
-s_max_i32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x84]
-
-s_max_i32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x84]
-
-s_max_i32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x84]
-
-s_max_i32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x84]
-
-s_max_i32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x84]
-
-s_max_i32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x84]
-
-s_max_i32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x84]
-
-s_max_i32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x84]
-
-s_max_i32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x84]
-
-s_max_i32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x84]
-
-s_max_i32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x84]
-
-s_max_i32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x84]
-
-s_max_i32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x84]
-
-s_max_i32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x84]
-
-s_max_i32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x84]
-
-s_max_i32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x84]
-
-s_max_i32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x84]
-
-s_max_i32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x84]
-
-s_max_i32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_i32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_i32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x84]
-
-s_max_i32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x84]
-
-s_max_i32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x84]
-
-s_max_i32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x84]
-
-s_max_i32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x84]
-
-s_max_i32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x84]
-
-s_max_i32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x84]
-
-s_max_i32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x84]
-
-s_max_i32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x84]
-
-s_max_i32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_i32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x84]
-
-s_max_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x84]
-
-s_max_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x84]
-
-s_max_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x84]
-
-s_max_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x84]
-
-s_max_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x84]
-
-s_max_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x84]
-
-s_max_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x84]
-
-s_max_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x84]
-
-s_max_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x84]
-
-s_max_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x84]
-
-s_max_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x84]
-
-s_max_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x84]
-
-s_max_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x84]
-
-s_max_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x84]
-
-s_max_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x84]
-
-s_max_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x84]
-
-s_max_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x84]
-
-s_max_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x84]
-
-s_max_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x84]
-
-s_max_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x84]
-
-s_max_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x84]
-
-s_max_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x84]
-
-s_max_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x84]
-
-s_max_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x84]
-
-s_max_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x84]
-
-s_max_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x84]
-
-s_max_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x84]
-
-s_max_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x84]
-
-s_max_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x84]
-
-s_max_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x84]
-
-s_max_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x84,0x56,0x34,0x12,0xaf]
-
-s_cselect_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x85]
-
-s_cselect_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x85]
-
-s_cselect_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x85]
-
-s_cselect_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x85]
-
-s_cselect_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x85]
-
-s_cselect_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x85]
-
-s_cselect_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x85]
-
-s_cselect_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x85]
-
-s_cselect_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x85]
-
-s_cselect_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x85]
-
-s_cselect_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x85]
-
-s_cselect_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x85]
-
-s_cselect_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x85]
-
-s_cselect_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x85]
-
-s_cselect_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x85]
-
-s_cselect_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x85]
-
-s_cselect_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x85]
-
-s_cselect_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x85]
-
-s_cselect_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x85]
-
-s_cselect_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x85]
-
-s_cselect_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x85]
-
-s_cselect_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x85]
-
-s_cselect_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x85]
-
-s_cselect_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x85]
-
-s_cselect_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x85]
-
-s_cselect_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x85]
-
-s_cselect_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x85]
-
-s_cselect_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x85]
-
-s_cselect_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x85]
-
-s_cselect_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x85]
-
-s_cselect_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x85]
-
-s_cselect_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b64 s[0:1], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0x80,0x85]
-
-s_cselect_b64 s[104:105], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0xe8,0x85]
-
-s_cselect_b64 s[0:1], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0x80,0x85]
-
-s_cselect_b64 s[104:105], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0xe8,0x85]
-
-s_cselect_b64 s[104:105], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0xe8,0x85]
-
-s_cselect_b64 s[104:105], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xe8,0x85]
-
-s_cselect_b64 s[0:1], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0x80,0x85]
-
-s_cselect_b64 s[0:1], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0x80,0x85]
-
-s_cselect_b64 exec, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xfe,0x85]
-
-s_cselect_b64 vcc, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xea,0x85]
-
-s_cselect_b64 s[0:1], exec, s[4:5]
-// GFX10: encoding: [0x7e,0x04,0x80,0x85]
-
-s_cselect_b64 s[0:1], vcc, s[4:5]
-// GFX10: encoding: [0x6a,0x04,0x80,0x85]
-
-s_cselect_b64 s[0:1], 0, s[4:5]
-// GFX10: encoding: [0x80,0x04,0x80,0x85]
-
-s_cselect_b64 s[0:1], -1, s[4:5]
-// GFX10: encoding: [0xc1,0x04,0x80,0x85]
-
-s_cselect_b64 s[0:1], 0.5, s[4:5]
-// GFX10: encoding: [0xf0,0x04,0x80,0x85]
-
-s_cselect_b64 s[0:1], -4.0, s[4:5]
-// GFX10: encoding: [0xf7,0x04,0x80,0x85]
-
-s_cselect_b64 s[0:1], 0x3f717273, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b64 s[0:1], 0xaf123456, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b64 s[0:1], s[2:3], exec
-// GFX10: encoding: [0x02,0x7e,0x80,0x85]
-
-s_cselect_b64 s[0:1], s[2:3], vcc
-// GFX10: encoding: [0x02,0x6a,0x80,0x85]
-
-s_cselect_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x85]
-
-s_cselect_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x85]
-
-s_cselect_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x85]
-
-s_cselect_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x85]
-
-s_cselect_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x85,0x56,0x34,0x12,0xaf]
-
-s_and_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x87]
-
-s_and_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x87]
-
-s_and_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x87]
-
-s_and_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x87]
-
-s_and_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x87]
-
-s_and_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x87]
-
-s_and_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x87]
-
-s_and_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x87]
-
-s_and_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x87]
-
-s_and_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x87]
-
-s_and_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x87]
-
-s_and_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x87]
-
-s_and_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x87]
-
-s_and_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x87]
-
-s_and_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x87]
-
-s_and_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x87]
-
-s_and_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x87]
-
-s_and_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x87]
-
-s_and_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x87]
-
-s_and_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x87]
-
-s_and_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x87]
-
-s_and_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x87]
-
-s_and_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x87,0x73,0x72,0x71,0x3f]
-
-s_and_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x87,0x56,0x34,0x12,0xaf]
-
-s_and_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x87]
-
-s_and_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x87]
-
-s_and_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x87]
-
-s_and_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x87]
-
-s_and_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x87]
-
-s_and_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x87]
-
-s_and_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x87]
-
-s_and_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x87]
-
-s_and_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x87]
-
-s_and_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x87,0x73,0x72,0x71,0x3f]
-
-s_and_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x87,0x56,0x34,0x12,0xaf]
-
-s_and_b64 s[0:1], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0x80,0x87]
-
-s_and_b64 s[104:105], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0xe8,0x87]
-
-s_and_b64 s[0:1], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0x80,0x87]
-
-s_and_b64 s[104:105], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0xe8,0x87]
-
-s_and_b64 s[104:105], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0xe8,0x87]
-
-s_and_b64 s[104:105], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xe8,0x87]
-
-s_and_b64 s[0:1], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0x80,0x87]
-
-s_and_b64 s[0:1], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0x80,0x87]
-
-s_and_b64 exec, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xfe,0x87]
-
-s_and_b64 vcc, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xea,0x87]
-
-s_and_b64 s[0:1], exec, s[4:5]
-// GFX10: encoding: [0x7e,0x04,0x80,0x87]
-
-s_and_b64 s[0:1], vcc, s[4:5]
-// GFX10: encoding: [0x6a,0x04,0x80,0x87]
-
-s_and_b64 s[0:1], 0, s[4:5]
-// GFX10: encoding: [0x80,0x04,0x80,0x87]
-
-s_and_b64 s[0:1], -1, s[4:5]
-// GFX10: encoding: [0xc1,0x04,0x80,0x87]
-
-s_and_b64 s[0:1], 0.5, s[4:5]
-// GFX10: encoding: [0xf0,0x04,0x80,0x87]
-
-s_and_b64 s[0:1], -4.0, s[4:5]
-// GFX10: encoding: [0xf7,0x04,0x80,0x87]
-
-s_and_b64 s[0:1], 0x3f717273, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x87,0x73,0x72,0x71,0x3f]
-
-s_and_b64 s[0:1], 0xaf123456, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x87,0x56,0x34,0x12,0xaf]
-
-s_and_b64 s[0:1], s[2:3], exec
-// GFX10: encoding: [0x02,0x7e,0x80,0x87]
-
-s_and_b64 s[0:1], s[2:3], vcc
-// GFX10: encoding: [0x02,0x6a,0x80,0x87]
-
-s_and_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x87]
-
-s_and_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x87]
-
-s_and_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x87]
-
-s_and_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x87]
-
-s_and_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x87,0x73,0x72,0x71,0x3f]
-
-s_and_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x87,0x56,0x34,0x12,0xaf]
-
-s_or_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x88]
-
-s_or_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x88]
-
-s_or_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x88]
-
-s_or_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x88]
-
-s_or_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x88]
-
-s_or_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x88]
-
-s_or_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x88]
-
-s_or_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x88]
-
-s_or_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x88]
-
-s_or_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x88]
-
-s_or_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x88]
-
-s_or_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x88]
-
-s_or_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x88]
-
-s_or_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x88]
-
-s_or_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x88]
-
-s_or_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x88]
-
-s_or_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x88]
-
-s_or_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x88]
-
-s_or_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x88]
-
-s_or_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x88]
-
-s_or_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x88]
-
-s_or_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x88]
-
-s_or_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x88,0x73,0x72,0x71,0x3f]
-
-s_or_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x88,0x56,0x34,0x12,0xaf]
-
-s_or_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x88]
-
-s_or_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x88]
-
-s_or_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x88]
-
-s_or_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x88]
-
-s_or_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x88]
-
-s_or_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x88]
-
-s_or_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x88]
-
-s_or_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x88]
-
-s_or_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x88]
-
-s_or_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x88,0x73,0x72,0x71,0x3f]
-
-s_or_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x88,0x56,0x34,0x12,0xaf]
-
-s_or_b64 s[0:1], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0x80,0x88]
-
-s_or_b64 s[104:105], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0xe8,0x88]
-
-s_or_b64 s[0:1], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0x80,0x88]
-
-s_or_b64 s[104:105], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0xe8,0x88]
-
-s_or_b64 s[104:105], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0xe8,0x88]
-
-s_or_b64 s[104:105], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xe8,0x88]
-
-s_or_b64 s[0:1], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0x80,0x88]
-
-s_or_b64 s[0:1], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0x80,0x88]
-
-s_or_b64 exec, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xfe,0x88]
-
-s_or_b64 vcc, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xea,0x88]
-
-s_or_b64 s[0:1], exec, s[4:5]
-// GFX10: encoding: [0x7e,0x04,0x80,0x88]
-
-s_or_b64 s[0:1], vcc, s[4:5]
-// GFX10: encoding: [0x6a,0x04,0x80,0x88]
-
-s_or_b64 s[0:1], 0, s[4:5]
-// GFX10: encoding: [0x80,0x04,0x80,0x88]
-
-s_or_b64 s[0:1], -1, s[4:5]
-// GFX10: encoding: [0xc1,0x04,0x80,0x88]
-
-s_or_b64 s[0:1], 0.5, s[4:5]
-// GFX10: encoding: [0xf0,0x04,0x80,0x88]
-
-s_or_b64 s[0:1], -4.0, s[4:5]
-// GFX10: encoding: [0xf7,0x04,0x80,0x88]
-
-s_or_b64 s[0:1], 0x3f717273, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x88,0x73,0x72,0x71,0x3f]
-
-s_or_b64 s[0:1], 0xaf123456, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x88,0x56,0x34,0x12,0xaf]
-
-s_or_b64 s[0:1], s[2:3], exec
-// GFX10: encoding: [0x02,0x7e,0x80,0x88]
-
-s_or_b64 s[0:1], s[2:3], vcc
-// GFX10: encoding: [0x02,0x6a,0x80,0x88]
-
-s_or_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x88]
-
-s_or_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x88]
-
-s_or_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x88]
-
-s_or_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x88]
-
-s_or_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x88,0x73,0x72,0x71,0x3f]
-
-s_or_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x88,0x56,0x34,0x12,0xaf]
-
-s_xor_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x89]
-
-s_xor_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x89]
-
-s_xor_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x89]
-
-s_xor_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x89]
-
-s_xor_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x89]
-
-s_xor_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x89]
-
-s_xor_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x89]
-
-s_xor_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x89]
-
-s_xor_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x89]
-
-s_xor_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x89]
-
-s_xor_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x89]
-
-s_xor_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x89]
-
-s_xor_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x89]
-
-s_xor_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x89]
-
-s_xor_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x89]
-
-s_xor_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x89]
-
-s_xor_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x89]
-
-s_xor_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x89]
-
-s_xor_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x89]
-
-s_xor_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x89]
-
-s_xor_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x89]
-
-s_xor_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x89]
-
-s_xor_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x89,0x73,0x72,0x71,0x3f]
-
-s_xor_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x89,0x56,0x34,0x12,0xaf]
-
-s_xor_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x89]
-
-s_xor_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x89]
-
-s_xor_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x89]
-
-s_xor_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x89]
-
-s_xor_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x89]
-
-s_xor_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x89]
-
-s_xor_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x89]
-
-s_xor_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x89]
-
-s_xor_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x89]
-
-s_xor_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x89,0x73,0x72,0x71,0x3f]
-
-s_xor_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x89,0x56,0x34,0x12,0xaf]
-
-s_xor_b64 s[0:1], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0x80,0x89]
-
-s_xor_b64 s[104:105], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0xe8,0x89]
-
-s_xor_b64 s[0:1], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0x80,0x89]
-
-s_xor_b64 s[104:105], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0xe8,0x89]
-
-s_xor_b64 s[104:105], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0xe8,0x89]
-
-s_xor_b64 s[104:105], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xe8,0x89]
-
-s_xor_b64 s[0:1], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0x80,0x89]
-
-s_xor_b64 s[0:1], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0x80,0x89]
-
-s_xor_b64 exec, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xfe,0x89]
-
-s_xor_b64 vcc, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xea,0x89]
-
-s_xor_b64 s[0:1], exec, s[4:5]
-// GFX10: encoding: [0x7e,0x04,0x80,0x89]
-
-s_xor_b64 s[0:1], vcc, s[4:5]
-// GFX10: encoding: [0x6a,0x04,0x80,0x89]
-
-s_xor_b64 s[0:1], 0, s[4:5]
-// GFX10: encoding: [0x80,0x04,0x80,0x89]
-
-s_xor_b64 s[0:1], -1, s[4:5]
-// GFX10: encoding: [0xc1,0x04,0x80,0x89]
-
-s_xor_b64 s[0:1], 0.5, s[4:5]
-// GFX10: encoding: [0xf0,0x04,0x80,0x89]
-
-s_xor_b64 s[0:1], -4.0, s[4:5]
-// GFX10: encoding: [0xf7,0x04,0x80,0x89]
-
-s_xor_b64 s[0:1], 0x3f717273, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x89,0x73,0x72,0x71,0x3f]
-
-s_xor_b64 s[0:1], 0xaf123456, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x89,0x56,0x34,0x12,0xaf]
-
-s_xor_b64 s[0:1], s[2:3], exec
-// GFX10: encoding: [0x02,0x7e,0x80,0x89]
-
-s_xor_b64 s[0:1], s[2:3], vcc
-// GFX10: encoding: [0x02,0x6a,0x80,0x89]
-
-s_xor_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x89]
-
-s_xor_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x89]
-
-s_xor_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x89]
-
-s_xor_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x89]
-
-s_xor_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x89,0x73,0x72,0x71,0x3f]
-
-s_xor_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x89,0x56,0x34,0x12,0xaf]
-
-s_andn2_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x8a]
-
-s_andn2_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x8a]
-
-s_andn2_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x8a]
-
-s_andn2_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x8a]
-
-s_andn2_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x8a]
-
-s_andn2_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x8a]
-
-s_andn2_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x8a]
-
-s_andn2_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x8a]
-
-s_andn2_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x8a]
-
-s_andn2_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x8a]
-
-s_andn2_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x8a]
-
-s_andn2_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x8a]
-
-s_andn2_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x8a]
-
-s_andn2_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8a,0x73,0x72,0x71,0x3f]
-
-s_andn2_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8a,0x56,0x34,0x12,0xaf]
-
-s_andn2_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x8a]
-
-s_andn2_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x8a]
-
-s_andn2_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x8a]
-
-s_andn2_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x8a]
-
-s_andn2_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x8a]
-
-s_andn2_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x8a]
-
-s_andn2_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x8a]
-
-s_andn2_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x8a]
-
-s_andn2_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x8a]
-
-s_andn2_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x8a,0x73,0x72,0x71,0x3f]
-
-s_andn2_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x8a,0x56,0x34,0x12,0xaf]
-
-s_andn2_b64 s[0:1], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0x80,0x8a]
-
-s_andn2_b64 s[104:105], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0xe8,0x8a]
-
-s_andn2_b64 s[0:1], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0x80,0x8a]
-
-s_andn2_b64 s[104:105], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0xe8,0x8a]
-
-s_andn2_b64 s[104:105], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0xe8,0x8a]
-
-s_andn2_b64 s[104:105], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xe8,0x8a]
-
-s_andn2_b64 s[0:1], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0x80,0x8a]
-
-s_andn2_b64 s[0:1], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0x80,0x8a]
-
-s_andn2_b64 exec, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xfe,0x8a]
-
-s_andn2_b64 vcc, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xea,0x8a]
-
-s_andn2_b64 s[0:1], exec, s[4:5]
-// GFX10: encoding: [0x7e,0x04,0x80,0x8a]
-
-s_andn2_b64 s[0:1], vcc, s[4:5]
-// GFX10: encoding: [0x6a,0x04,0x80,0x8a]
-
-s_andn2_b64 s[0:1], 0, s[4:5]
-// GFX10: encoding: [0x80,0x04,0x80,0x8a]
-
-s_andn2_b64 s[0:1], -1, s[4:5]
-// GFX10: encoding: [0xc1,0x04,0x80,0x8a]
-
-s_andn2_b64 s[0:1], 0.5, s[4:5]
-// GFX10: encoding: [0xf0,0x04,0x80,0x8a]
-
-s_andn2_b64 s[0:1], -4.0, s[4:5]
-// GFX10: encoding: [0xf7,0x04,0x80,0x8a]
-
-s_andn2_b64 s[0:1], 0x3f717273, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8a,0x73,0x72,0x71,0x3f]
-
-s_andn2_b64 s[0:1], 0xaf123456, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8a,0x56,0x34,0x12,0xaf]
-
-s_andn2_b64 s[0:1], s[2:3], exec
-// GFX10: encoding: [0x02,0x7e,0x80,0x8a]
-
-s_andn2_b64 s[0:1], s[2:3], vcc
-// GFX10: encoding: [0x02,0x6a,0x80,0x8a]
-
-s_andn2_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x8a]
-
-s_andn2_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x8a]
-
-s_andn2_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x8a]
-
-s_andn2_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x8a]
-
-s_andn2_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x8a,0x73,0x72,0x71,0x3f]
-
-s_andn2_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x8a,0x56,0x34,0x12,0xaf]
-
-s_orn2_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x8b]
-
-s_orn2_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x8b]
-
-s_orn2_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x8b]
-
-s_orn2_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x8b]
-
-s_orn2_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x8b]
-
-s_orn2_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x8b]
-
-s_orn2_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x8b]
-
-s_orn2_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x8b]
-
-s_orn2_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x8b]
-
-s_orn2_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x8b]
-
-s_orn2_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x8b]
-
-s_orn2_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x8b]
-
-s_orn2_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x8b]
-
-s_orn2_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8b,0x73,0x72,0x71,0x3f]
-
-s_orn2_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8b,0x56,0x34,0x12,0xaf]
-
-s_orn2_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x8b]
-
-s_orn2_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x8b]
-
-s_orn2_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x8b]
-
-s_orn2_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x8b]
-
-s_orn2_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x8b]
-
-s_orn2_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x8b]
-
-s_orn2_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x8b]
-
-s_orn2_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x8b]
-
-s_orn2_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x8b]
-
-s_orn2_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x8b,0x73,0x72,0x71,0x3f]
-
-s_orn2_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x8b,0x56,0x34,0x12,0xaf]
-
-s_orn2_b64 s[0:1], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0x80,0x8b]
-
-s_orn2_b64 s[104:105], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0xe8,0x8b]
-
-s_orn2_b64 s[0:1], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0x80,0x8b]
-
-s_orn2_b64 s[104:105], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0xe8,0x8b]
-
-s_orn2_b64 s[104:105], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0xe8,0x8b]
-
-s_orn2_b64 s[104:105], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xe8,0x8b]
-
-s_orn2_b64 s[0:1], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0x80,0x8b]
-
-s_orn2_b64 s[0:1], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0x80,0x8b]
-
-s_orn2_b64 exec, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xfe,0x8b]
-
-s_orn2_b64 vcc, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xea,0x8b]
-
-s_orn2_b64 s[0:1], exec, s[4:5]
-// GFX10: encoding: [0x7e,0x04,0x80,0x8b]
-
-s_orn2_b64 s[0:1], vcc, s[4:5]
-// GFX10: encoding: [0x6a,0x04,0x80,0x8b]
-
-s_orn2_b64 s[0:1], 0, s[4:5]
-// GFX10: encoding: [0x80,0x04,0x80,0x8b]
-
-s_orn2_b64 s[0:1], -1, s[4:5]
-// GFX10: encoding: [0xc1,0x04,0x80,0x8b]
-
-s_orn2_b64 s[0:1], 0.5, s[4:5]
-// GFX10: encoding: [0xf0,0x04,0x80,0x8b]
-
-s_orn2_b64 s[0:1], -4.0, s[4:5]
-// GFX10: encoding: [0xf7,0x04,0x80,0x8b]
-
-s_orn2_b64 s[0:1], 0x3f717273, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8b,0x73,0x72,0x71,0x3f]
-
-s_orn2_b64 s[0:1], 0xaf123456, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf]
-
-s_orn2_b64 s[0:1], s[2:3], exec
-// GFX10: encoding: [0x02,0x7e,0x80,0x8b]
-
-s_orn2_b64 s[0:1], s[2:3], vcc
-// GFX10: encoding: [0x02,0x6a,0x80,0x8b]
-
-s_orn2_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x8b]
-
-s_orn2_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x8b]
-
-s_orn2_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x8b]
-
-s_orn2_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x8b]
-
-s_orn2_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x8b,0x73,0x72,0x71,0x3f]
-
-s_orn2_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x8b,0x56,0x34,0x12,0xaf]
-
-s_nand_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x8c]
-
-s_nand_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x8c]
-
-s_nand_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x8c]
-
-s_nand_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x8c]
-
-s_nand_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x8c]
-
-s_nand_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x8c]
-
-s_nand_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x8c]
-
-s_nand_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x8c]
-
-s_nand_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x8c]
-
-s_nand_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x8c]
-
-s_nand_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x8c]
-
-s_nand_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x8c]
-
-s_nand_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x8c]
-
-s_nand_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x8c]
-
-s_nand_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x8c]
-
-s_nand_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x8c]
-
-s_nand_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x8c]
-
-s_nand_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x8c]
-
-s_nand_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x8c]
-
-s_nand_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x8c]
-
-s_nand_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x8c]
-
-s_nand_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x8c]
-
-s_nand_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nand_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nand_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x8c]
-
-s_nand_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x8c]
-
-s_nand_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x8c]
-
-s_nand_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x8c]
-
-s_nand_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x8c]
-
-s_nand_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x8c]
-
-s_nand_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x8c]
-
-s_nand_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x8c]
-
-s_nand_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x8c]
-
-s_nand_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nand_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nand_b64 s[0:1], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0x80,0x8c]
-
-s_nand_b64 s[104:105], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0xe8,0x8c]
-
-s_nand_b64 s[0:1], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0x80,0x8c]
-
-s_nand_b64 s[104:105], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0xe8,0x8c]
-
-s_nand_b64 s[104:105], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0xe8,0x8c]
-
-s_nand_b64 s[104:105], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xe8,0x8c]
-
-s_nand_b64 s[0:1], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0x80,0x8c]
-
-s_nand_b64 s[0:1], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0x80,0x8c]
-
-s_nand_b64 exec, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xfe,0x8c]
-
-s_nand_b64 vcc, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xea,0x8c]
-
-s_nand_b64 s[0:1], exec, s[4:5]
-// GFX10: encoding: [0x7e,0x04,0x80,0x8c]
-
-s_nand_b64 s[0:1], vcc, s[4:5]
-// GFX10: encoding: [0x6a,0x04,0x80,0x8c]
-
-s_nand_b64 s[0:1], 0, s[4:5]
-// GFX10: encoding: [0x80,0x04,0x80,0x8c]
-
-s_nand_b64 s[0:1], -1, s[4:5]
-// GFX10: encoding: [0xc1,0x04,0x80,0x8c]
-
-s_nand_b64 s[0:1], 0.5, s[4:5]
-// GFX10: encoding: [0xf0,0x04,0x80,0x8c]
-
-s_nand_b64 s[0:1], -4.0, s[4:5]
-// GFX10: encoding: [0xf7,0x04,0x80,0x8c]
-
-s_nand_b64 s[0:1], 0x3f717273, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nand_b64 s[0:1], 0xaf123456, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nand_b64 s[0:1], s[2:3], exec
-// GFX10: encoding: [0x02,0x7e,0x80,0x8c]
-
-s_nand_b64 s[0:1], s[2:3], vcc
-// GFX10: encoding: [0x02,0x6a,0x80,0x8c]
-
-s_nand_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x8c]
-
-s_nand_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x8c]
-
-s_nand_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x8c]
-
-s_nand_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x8c]
-
-s_nand_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nand_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nor_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x8d]
-
-s_nor_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x8d]
-
-s_nor_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x8d]
-
-s_nor_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x8d]
-
-s_nor_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x8d]
-
-s_nor_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x8d]
-
-s_nor_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x8d]
-
-s_nor_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x8d]
-
-s_nor_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x8d]
-
-s_nor_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x8d]
-
-s_nor_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x8d]
-
-s_nor_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x8d]
-
-s_nor_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x8d]
-
-s_nor_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x8d]
-
-s_nor_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x8d]
-
-s_nor_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x8d]
-
-s_nor_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x8d]
-
-s_nor_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x8d]
-
-s_nor_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x8d]
-
-s_nor_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x8d]
-
-s_nor_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x8d]
-
-s_nor_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x8d]
-
-s_nor_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8d,0x73,0x72,0x71,0x3f]
-
-s_nor_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8d,0x56,0x34,0x12,0xaf]
-
-s_nor_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x8d]
-
-s_nor_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x8d]
-
-s_nor_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x8d]
-
-s_nor_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x8d]
-
-s_nor_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x8d]
-
-s_nor_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x8d]
-
-s_nor_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x8d]
-
-s_nor_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x8d]
-
-s_nor_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x8d]
-
-s_nor_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x8d,0x73,0x72,0x71,0x3f]
-
-s_nor_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x8d,0x56,0x34,0x12,0xaf]
-
-s_nor_b64 s[0:1], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0x80,0x8d]
-
-s_nor_b64 s[104:105], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0xe8,0x8d]
-
-s_nor_b64 s[0:1], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0x80,0x8d]
-
-s_nor_b64 s[104:105], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0xe8,0x8d]
-
-s_nor_b64 s[104:105], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0xe8,0x8d]
-
-s_nor_b64 s[104:105], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xe8,0x8d]
-
-s_nor_b64 s[0:1], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0x80,0x8d]
-
-s_nor_b64 s[0:1], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0x80,0x8d]
-
-s_nor_b64 exec, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xfe,0x8d]
-
-s_nor_b64 vcc, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xea,0x8d]
-
-s_nor_b64 s[0:1], exec, s[4:5]
-// GFX10: encoding: [0x7e,0x04,0x80,0x8d]
-
-s_nor_b64 s[0:1], vcc, s[4:5]
-// GFX10: encoding: [0x6a,0x04,0x80,0x8d]
-
-s_nor_b64 s[0:1], 0, s[4:5]
-// GFX10: encoding: [0x80,0x04,0x80,0x8d]
-
-s_nor_b64 s[0:1], -1, s[4:5]
-// GFX10: encoding: [0xc1,0x04,0x80,0x8d]
-
-s_nor_b64 s[0:1], 0.5, s[4:5]
-// GFX10: encoding: [0xf0,0x04,0x80,0x8d]
-
-s_nor_b64 s[0:1], -4.0, s[4:5]
-// GFX10: encoding: [0xf7,0x04,0x80,0x8d]
-
-s_nor_b64 s[0:1], 0x3f717273, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8d,0x73,0x72,0x71,0x3f]
-
-s_nor_b64 s[0:1], 0xaf123456, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf]
-
-s_nor_b64 s[0:1], s[2:3], exec
-// GFX10: encoding: [0x02,0x7e,0x80,0x8d]
-
-s_nor_b64 s[0:1], s[2:3], vcc
-// GFX10: encoding: [0x02,0x6a,0x80,0x8d]
-
-s_nor_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x8d]
-
-s_nor_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x8d]
-
-s_nor_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x8d]
-
-s_nor_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x8d]
-
-s_nor_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x8d,0x73,0x72,0x71,0x3f]
-
-s_nor_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x8d,0x56,0x34,0x12,0xaf]
-
-s_xnor_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x8e]
-
-s_xnor_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x8e]
-
-s_xnor_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x8e]
-
-s_xnor_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x8e]
-
-s_xnor_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x8e]
-
-s_xnor_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x8e]
-
-s_xnor_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x8e]
-
-s_xnor_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x8e]
-
-s_xnor_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x8e]
-
-s_xnor_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x8e]
-
-s_xnor_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x8e]
-
-s_xnor_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x8e]
-
-s_xnor_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x8e]
-
-s_xnor_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8e,0x73,0x72,0x71,0x3f]
-
-s_xnor_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8e,0x56,0x34,0x12,0xaf]
-
-s_xnor_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x8e]
-
-s_xnor_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x8e]
-
-s_xnor_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x8e]
-
-s_xnor_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x8e]
-
-s_xnor_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x8e]
-
-s_xnor_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x8e]
-
-s_xnor_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x8e]
-
-s_xnor_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x8e]
-
-s_xnor_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x8e]
-
-s_xnor_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x8e,0x73,0x72,0x71,0x3f]
-
-s_xnor_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x8e,0x56,0x34,0x12,0xaf]
-
-s_xnor_b64 s[0:1], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0x80,0x8e]
-
-s_xnor_b64 s[104:105], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0xe8,0x8e]
-
-s_xnor_b64 s[0:1], s[102:103], s[100:101]
-// GFX10: encoding: [0x66,0x64,0x80,0x8e]
-
-s_xnor_b64 s[104:105], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0xe8,0x8e]
-
-s_xnor_b64 s[104:105], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0xe8,0x8e]
-
-s_xnor_b64 s[104:105], s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xe8,0x8e]
-
-s_xnor_b64 s[0:1], s[102:103], s[4:5]
-// GFX10: encoding: [0x66,0x04,0x80,0x8e]
-
-s_xnor_b64 s[0:1], s[2:3], s[100:101]
-// GFX10: encoding: [0x02,0x64,0x80,0x8e]
-
-s_xnor_b64 exec, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xfe,0x8e]
-
-s_xnor_b64 vcc, s[2:3], s[4:5]
-// GFX10: encoding: [0x02,0x04,0xea,0x8e]
-
-s_xnor_b64 s[0:1], exec, s[4:5]
-// GFX10: encoding: [0x7e,0x04,0x80,0x8e]
-
-s_xnor_b64 s[0:1], vcc, s[4:5]
-// GFX10: encoding: [0x6a,0x04,0x80,0x8e]
-
-s_xnor_b64 s[0:1], 0, s[4:5]
-// GFX10: encoding: [0x80,0x04,0x80,0x8e]
-
-s_xnor_b64 s[0:1], -1, s[4:5]
-// GFX10: encoding: [0xc1,0x04,0x80,0x8e]
-
-s_xnor_b64 s[0:1], 0.5, s[4:5]
-// GFX10: encoding: [0xf0,0x04,0x80,0x8e]
-
-s_xnor_b64 s[0:1], -4.0, s[4:5]
-// GFX10: encoding: [0xf7,0x04,0x80,0x8e]
-
-s_xnor_b64 s[0:1], 0x3f717273, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8e,0x73,0x72,0x71,0x3f]
-
-s_xnor_b64 s[0:1], 0xaf123456, s[4:5]
-// GFX10: encoding: [0xff,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf]
-
-s_xnor_b64 s[0:1], s[2:3], exec
-// GFX10: encoding: [0x02,0x7e,0x80,0x8e]
-
-s_xnor_b64 s[0:1], s[2:3], vcc
-// GFX10: encoding: [0x02,0x6a,0x80,0x8e]
-
-s_xnor_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x8e]
-
-s_xnor_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x8e]
-
-s_xnor_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x8e]
-
-s_xnor_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x8e]
-
-s_xnor_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x8e,0x73,0x72,0x71,0x3f]
-
-s_xnor_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x8e,0x56,0x34,0x12,0xaf]
-
-s_lshl_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x8f]
-
-s_lshl_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x8f]
-
-s_lshl_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x8f]
-
-s_lshl_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x8f]
-
-s_lshl_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x8f]
-
-s_lshl_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x8f]
-
-s_lshl_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x8f]
-
-s_lshl_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x8f]
-
-s_lshl_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x8f]
-
-s_lshl_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x8f]
-
-s_lshl_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x8f]
-
-s_lshl_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x8f]
-
-s_lshl_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x8f]
-
-s_lshl_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshl_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshl_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x8f]
-
-s_lshl_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x8f]
-
-s_lshl_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x8f]
-
-s_lshl_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x8f]
-
-s_lshl_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x8f]
-
-s_lshl_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x8f]
-
-s_lshl_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x8f]
-
-s_lshl_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x8f]
-
-s_lshl_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x8f]
-
-s_lshl_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshl_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshl_b64 s[0:1], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0x80,0x8f]
-
-s_lshl_b64 s[104:105], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0xe8,0x8f]
-
-s_lshl_b64 s[0:1], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0x80,0x8f]
-
-s_lshl_b64 s[104:105], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0xe8,0x8f]
-
-s_lshl_b64 s[104:105], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0xe8,0x8f]
-
-s_lshl_b64 s[104:105], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xe8,0x8f]
-
-s_lshl_b64 s[0:1], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0x80,0x8f]
-
-s_lshl_b64 s[0:1], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0x80,0x8f]
-
-s_lshl_b64 exec, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xfe,0x8f]
-
-s_lshl_b64 vcc, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xea,0x8f]
-
-s_lshl_b64 s[0:1], exec, s4
-// GFX10: encoding: [0x7e,0x04,0x80,0x8f]
-
-s_lshl_b64 s[0:1], vcc, s4
-// GFX10: encoding: [0x6a,0x04,0x80,0x8f]
-
-s_lshl_b64 s[0:1], 0, s4
-// GFX10: encoding: [0x80,0x04,0x80,0x8f]
-
-s_lshl_b64 s[0:1], -1, s4
-// GFX10: encoding: [0xc1,0x04,0x80,0x8f]
-
-s_lshl_b64 s[0:1], 0.5, s4
-// GFX10: encoding: [0xf0,0x04,0x80,0x8f]
-
-s_lshl_b64 s[0:1], -4.0, s4
-// GFX10: encoding: [0xf7,0x04,0x80,0x8f]
-
-s_lshl_b64 s[0:1], 0x3f717273, s4
-// GFX10: encoding: [0xff,0x04,0x80,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshl_b64 s[0:1], 0xaf123456, s4
-// GFX10: encoding: [0xff,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshl_b64 s[0:1], s[2:3], exec_lo
-// GFX10: encoding: [0x02,0x7e,0x80,0x8f]
-
-s_lshl_b64 s[0:1], s[2:3], vcc_lo
-// GFX10: encoding: [0x02,0x6a,0x80,0x8f]
-
-s_lshl_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x8f]
-
-s_lshl_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x8f]
-
-s_lshl_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x8f]
-
-s_lshl_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x8f]
-
-s_lshl_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshl_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshr_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x90]
-
-s_lshr_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x90]
-
-s_lshr_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x90]
-
-s_lshr_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x90]
-
-s_lshr_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x90]
-
-s_lshr_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x90]
-
-s_lshr_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x90]
-
-s_lshr_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x90]
-
-s_lshr_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x90]
-
-s_lshr_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x90]
-
-s_lshr_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x90]
-
-s_lshr_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x90]
-
-s_lshr_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x90]
-
-s_lshr_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x90]
-
-s_lshr_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x90]
-
-s_lshr_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x90]
-
-s_lshr_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x90]
-
-s_lshr_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x90]
-
-s_lshr_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x90]
-
-s_lshr_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x90]
-
-s_lshr_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x90]
-
-s_lshr_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x90]
-
-s_lshr_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x90,0x73,0x72,0x71,0x3f]
-
-s_lshr_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x90,0x56,0x34,0x12,0xaf]
-
-s_lshr_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x90]
-
-s_lshr_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x90]
-
-s_lshr_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x90]
-
-s_lshr_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x90]
-
-s_lshr_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x90]
-
-s_lshr_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x90]
-
-s_lshr_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x90]
-
-s_lshr_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x90]
-
-s_lshr_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x90]
-
-s_lshr_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x90,0x73,0x72,0x71,0x3f]
-
-s_lshr_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x90,0x56,0x34,0x12,0xaf]
-
-s_lshr_b64 s[0:1], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0x80,0x90]
-
-s_lshr_b64 s[104:105], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0xe8,0x90]
-
-s_lshr_b64 s[0:1], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0x80,0x90]
-
-s_lshr_b64 s[104:105], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0xe8,0x90]
-
-s_lshr_b64 s[104:105], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0xe8,0x90]
-
-s_lshr_b64 s[104:105], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xe8,0x90]
-
-s_lshr_b64 s[0:1], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0x80,0x90]
-
-s_lshr_b64 s[0:1], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0x80,0x90]
-
-s_lshr_b64 exec, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xfe,0x90]
-
-s_lshr_b64 vcc, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xea,0x90]
-
-s_lshr_b64 s[0:1], exec, s4
-// GFX10: encoding: [0x7e,0x04,0x80,0x90]
-
-s_lshr_b64 s[0:1], vcc, s4
-// GFX10: encoding: [0x6a,0x04,0x80,0x90]
-
-s_lshr_b64 s[0:1], 0, s4
-// GFX10: encoding: [0x80,0x04,0x80,0x90]
-
-s_lshr_b64 s[0:1], -1, s4
-// GFX10: encoding: [0xc1,0x04,0x80,0x90]
-
-s_lshr_b64 s[0:1], 0.5, s4
-// GFX10: encoding: [0xf0,0x04,0x80,0x90]
-
-s_lshr_b64 s[0:1], -4.0, s4
-// GFX10: encoding: [0xf7,0x04,0x80,0x90]
-
-s_lshr_b64 s[0:1], 0x3f717273, s4
-// GFX10: encoding: [0xff,0x04,0x80,0x90,0x73,0x72,0x71,0x3f]
-
-s_lshr_b64 s[0:1], 0xaf123456, s4
-// GFX10: encoding: [0xff,0x04,0x80,0x90,0x56,0x34,0x12,0xaf]
-
-s_lshr_b64 s[0:1], s[2:3], exec_lo
-// GFX10: encoding: [0x02,0x7e,0x80,0x90]
-
-s_lshr_b64 s[0:1], s[2:3], vcc_lo
-// GFX10: encoding: [0x02,0x6a,0x80,0x90]
-
-s_lshr_b64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x90]
-
-s_lshr_b64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x90]
-
-s_lshr_b64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x90]
-
-s_lshr_b64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x90]
-
-s_lshr_b64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x90,0x73,0x72,0x71,0x3f]
-
-s_lshr_b64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x90,0x56,0x34,0x12,0xaf]
-
-s_ashr_i32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x91]
-
-s_ashr_i32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x91]
-
-s_ashr_i32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x91]
-
-s_ashr_i32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x91]
-
-s_ashr_i32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x91]
-
-s_ashr_i32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x91]
-
-s_ashr_i32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x91]
-
-s_ashr_i32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x91]
-
-s_ashr_i32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x91]
-
-s_ashr_i32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x91]
-
-s_ashr_i32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x91]
-
-s_ashr_i32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x91]
-
-s_ashr_i32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x91]
-
-s_ashr_i32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x91]
-
-s_ashr_i32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x91]
-
-s_ashr_i32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x91]
-
-s_ashr_i32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x91]
-
-s_ashr_i32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x91]
-
-s_ashr_i32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x91]
-
-s_ashr_i32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x91]
-
-s_ashr_i32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x91]
-
-s_ashr_i32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x91]
-
-s_ashr_i32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x91,0x73,0x72,0x71,0x3f]
-
-s_ashr_i32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x91,0x56,0x34,0x12,0xaf]
-
-s_ashr_i32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x91]
-
-s_ashr_i32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x91]
-
-s_ashr_i32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x91]
-
-s_ashr_i32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x91]
-
-s_ashr_i32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x91]
-
-s_ashr_i32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x91]
-
-s_ashr_i32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x91]
-
-s_ashr_i32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x91]
-
-s_ashr_i32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x91]
-
-s_ashr_i32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x91,0x73,0x72,0x71,0x3f]
-
-s_ashr_i32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x91,0x56,0x34,0x12,0xaf]
-
-s_ashr_i64 s[0:1], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0x80,0x91]
-
-s_ashr_i64 s[104:105], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0xe8,0x91]
-
-s_ashr_i64 s[0:1], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0x80,0x91]
-
-s_ashr_i64 s[104:105], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0xe8,0x91]
-
-s_ashr_i64 s[104:105], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0xe8,0x91]
-
-s_ashr_i64 s[104:105], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xe8,0x91]
-
-s_ashr_i64 s[0:1], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0x80,0x91]
-
-s_ashr_i64 s[0:1], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0x80,0x91]
-
-s_ashr_i64 exec, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xfe,0x91]
-
-s_ashr_i64 vcc, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xea,0x91]
-
-s_ashr_i64 s[0:1], exec, s4
-// GFX10: encoding: [0x7e,0x04,0x80,0x91]
-
-s_ashr_i64 s[0:1], vcc, s4
-// GFX10: encoding: [0x6a,0x04,0x80,0x91]
-
-s_ashr_i64 s[0:1], 0, s4
-// GFX10: encoding: [0x80,0x04,0x80,0x91]
-
-s_ashr_i64 s[0:1], -1, s4
-// GFX10: encoding: [0xc1,0x04,0x80,0x91]
-
-s_ashr_i64 s[0:1], 0.5, s4
-// GFX10: encoding: [0xf0,0x04,0x80,0x91]
-
-s_ashr_i64 s[0:1], -4.0, s4
-// GFX10: encoding: [0xf7,0x04,0x80,0x91]
-
-s_ashr_i64 s[0:1], 0x3f717273, s4
-// GFX10: encoding: [0xff,0x04,0x80,0x91,0x73,0x72,0x71,0x3f]
-
-s_ashr_i64 s[0:1], 0xaf123456, s4
-// GFX10: encoding: [0xff,0x04,0x80,0x91,0x56,0x34,0x12,0xaf]
-
-s_ashr_i64 s[0:1], s[2:3], exec_lo
-// GFX10: encoding: [0x02,0x7e,0x80,0x91]
-
-s_ashr_i64 s[0:1], s[2:3], vcc_lo
-// GFX10: encoding: [0x02,0x6a,0x80,0x91]
-
-s_ashr_i64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x91]
-
-s_ashr_i64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x91]
-
-s_ashr_i64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x91]
-
-s_ashr_i64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x91]
-
-s_ashr_i64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x91,0x73,0x72,0x71,0x3f]
-
-s_ashr_i64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x91,0x56,0x34,0x12,0xaf]
-
-s_bfm_b32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x92]
-
-s_bfm_b32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x92]
-
-s_bfm_b32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x92]
-
-s_bfm_b32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x92]
-
-s_bfm_b32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x92]
-
-s_bfm_b32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x92]
-
-s_bfm_b32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x92]
-
-s_bfm_b32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x92]
-
-s_bfm_b32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x92]
-
-s_bfm_b32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x92]
-
-s_bfm_b32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x92]
-
-s_bfm_b32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x92]
-
-s_bfm_b32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x92]
-
-s_bfm_b32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x92]
-
-s_bfm_b32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x92]
-
-s_bfm_b32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x92]
-
-s_bfm_b32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x92]
-
-s_bfm_b32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x92]
-
-s_bfm_b32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x92]
-
-s_bfm_b32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x92]
-
-s_bfm_b32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x92]
-
-s_bfm_b32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x92]
-
-s_bfm_b32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfm_b32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfm_b32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x92]
-
-s_bfm_b32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x92]
-
-s_bfm_b32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x92]
-
-s_bfm_b32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x92]
-
-s_bfm_b32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x92]
-
-s_bfm_b32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x92]
-
-s_bfm_b32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x92]
-
-s_bfm_b32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x92]
-
-s_bfm_b32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x92]
-
-s_bfm_b32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfm_b32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfm_b64 s[0:1], s2, s3
-// GFX10: encoding: [0x02,0x03,0x80,0x92]
-
-s_bfm_b64 s[104:105], s103, s102
-// GFX10: encoding: [0x67,0x66,0xe8,0x92]
-
-s_bfm_b64 s[0:1], s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x92]
-
-s_bfm_b64 s[104:105], s2, s103
-// GFX10: encoding: [0x02,0x67,0xe8,0x92]
-
-s_bfm_b64 s[104:105], s104, s3
-// GFX10: encoding: [0x68,0x03,0xe8,0x92]
-
-s_bfm_b64 s[104:105], s2, s3
-// GFX10: encoding: [0x02,0x03,0xe8,0x92]
-
-s_bfm_b64 s[0:1], s104, s3
-// GFX10: encoding: [0x68,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, s103
-// GFX10: encoding: [0x02,0x67,0x80,0x92]
-
-s_bfm_b64 exec, s2, s3
-// GFX10: encoding: [0x02,0x03,0xfe,0x92]
-
-s_bfm_b64 vcc, s2, s3
-// GFX10: encoding: [0x02,0x03,0xea,0x92]
-
-s_bfm_b64 s[0:1], exec_lo, s3
-// GFX10: encoding: [0x7e,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], exec_hi, s3
-// GFX10: encoding: [0x7f,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], vcc_lo, s3
-// GFX10: encoding: [0x6a,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], vcc_hi, s3
-// GFX10: encoding: [0x6b,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], m0, s3
-// GFX10: encoding: [0x7c,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], 0, s3
-// GFX10: encoding: [0x80,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], -1, s3
-// GFX10: encoding: [0xc1,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], 0.5, s3
-// GFX10: encoding: [0xf0,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], -4.0, s3
-// GFX10: encoding: [0xf7,0x03,0x80,0x92]
-
-s_bfm_b64 s[0:1], 0x3f717273, s3
-// GFX10: encoding: [0xff,0x03,0x80,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfm_b64 s[0:1], 0xaf123456, s3
-// GFX10: encoding: [0xff,0x03,0x80,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfm_b64 s[0:1], s2, exec_lo
-// GFX10: encoding: [0x02,0x7e,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, exec_hi
-// GFX10: encoding: [0x02,0x7f,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, vcc_lo
-// GFX10: encoding: [0x02,0x6a,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, vcc_hi
-// GFX10: encoding: [0x02,0x6b,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, m0
-// GFX10: encoding: [0x02,0x7c,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, 0
-// GFX10: encoding: [0x02,0x80,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x92]
-
-s_bfm_b64 s[0:1], s2, 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfm_b64 s[0:1], s2, 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x92,0x56,0x34,0x12,0xaf]
-
-s_mul_i32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x93]
-
-s_mul_i32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x93]
-
-s_mul_i32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x93]
-
-s_mul_i32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x93]
-
-s_mul_i32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x93]
-
-s_mul_i32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x93]
-
-s_mul_i32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x93]
-
-s_mul_i32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x93]
-
-s_mul_i32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x93]
-
-s_mul_i32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x93]
-
-s_mul_i32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x93]
-
-s_mul_i32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x93]
-
-s_mul_i32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x93]
-
-s_mul_i32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x93]
-
-s_mul_i32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x93]
-
-s_mul_i32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x93]
-
-s_mul_i32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x93]
-
-s_mul_i32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x93]
-
-s_mul_i32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x93]
-
-s_mul_i32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x93]
-
-s_mul_i32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x93]
-
-s_mul_i32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x93]
-
-s_mul_i32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x93,0x73,0x72,0x71,0x3f]
-
-s_mul_i32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x93,0x56,0x34,0x12,0xaf]
-
-s_mul_i32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x93]
-
-s_mul_i32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x93]
-
-s_mul_i32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x93]
-
-s_mul_i32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x93]
-
-s_mul_i32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x93]
-
-s_mul_i32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x93]
-
-s_mul_i32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x93]
-
-s_mul_i32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x93]
-
-s_mul_i32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x93]
-
-s_mul_i32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x93,0x73,0x72,0x71,0x3f]
-
-s_mul_i32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x93]
-
-s_bfe_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x93]
-
-s_bfe_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x93]
-
-s_bfe_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x93]
-
-s_bfe_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x93]
-
-s_bfe_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x93]
-
-s_bfe_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x93]
-
-s_bfe_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x93]
-
-s_bfe_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x93]
-
-s_bfe_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x93]
-
-s_bfe_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x93]
-
-s_bfe_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x93]
-
-s_bfe_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x93]
-
-s_bfe_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x93]
-
-s_bfe_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x93]
-
-s_bfe_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x93]
-
-s_bfe_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x93]
-
-s_bfe_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x93]
-
-s_bfe_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x93]
-
-s_bfe_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x93]
-
-s_bfe_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x93]
-
-s_bfe_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x93]
-
-s_bfe_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x93]
-
-s_bfe_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x93]
-
-s_bfe_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x93]
-
-s_bfe_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x93]
-
-s_bfe_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x93]
-
-s_bfe_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x93]
-
-s_bfe_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x93]
-
-s_bfe_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x93]
-
-s_bfe_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x93]
-
-s_bfe_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_i32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x94]
-
-s_bfe_i32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x94]
-
-s_bfe_i32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x94]
-
-s_bfe_i32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x94]
-
-s_bfe_i32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x94]
-
-s_bfe_i32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x94]
-
-s_bfe_i32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x94]
-
-s_bfe_i32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x94]
-
-s_bfe_i32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x94]
-
-s_bfe_i32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x94]
-
-s_bfe_i32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x94]
-
-s_bfe_i32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x94]
-
-s_bfe_i32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x94]
-
-s_bfe_i32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x94]
-
-s_bfe_i32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x94]
-
-s_bfe_i32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x94]
-
-s_bfe_i32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x94]
-
-s_bfe_i32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x94]
-
-s_bfe_i32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x94]
-
-s_bfe_i32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x94]
-
-s_bfe_i32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x94]
-
-s_bfe_i32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x94]
-
-s_bfe_i32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_i32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_i32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x94]
-
-s_bfe_i32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x94]
-
-s_bfe_i32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x94]
-
-s_bfe_i32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x94]
-
-s_bfe_i32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x94]
-
-s_bfe_i32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x94]
-
-s_bfe_i32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x94]
-
-s_bfe_i32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x94]
-
-s_bfe_i32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x94]
-
-s_bfe_i32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_i32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_u64 s[0:1], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0x80,0x94]
-
-s_bfe_u64 s[104:105], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0xe8,0x94]
-
-s_bfe_u64 s[0:1], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0x80,0x94]
-
-s_bfe_u64 s[104:105], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0xe8,0x94]
-
-s_bfe_u64 s[104:105], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0xe8,0x94]
-
-s_bfe_u64 s[104:105], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xe8,0x94]
-
-s_bfe_u64 s[0:1], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0x80,0x94]
-
-s_bfe_u64 s[0:1], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0x80,0x94]
-
-s_bfe_u64 exec, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xfe,0x94]
-
-s_bfe_u64 vcc, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0xea,0x94]
-
-s_bfe_u64 s[0:1], exec, s4
-// GFX10: encoding: [0x7e,0x04,0x80,0x94]
-
-s_bfe_u64 s[0:1], vcc, s4
-// GFX10: encoding: [0x6a,0x04,0x80,0x94]
-
-s_bfe_u64 s[0:1], 0, s4
-// GFX10: encoding: [0x80,0x04,0x80,0x94]
-
-s_bfe_u64 s[0:1], -1, s4
-// GFX10: encoding: [0xc1,0x04,0x80,0x94]
-
-s_bfe_u64 s[0:1], 0.5, s4
-// GFX10: encoding: [0xf0,0x04,0x80,0x94]
-
-s_bfe_u64 s[0:1], -4.0, s4
-// GFX10: encoding: [0xf7,0x04,0x80,0x94]
-
-s_bfe_u64 s[0:1], 0x3f717273, s4
-// GFX10: encoding: [0xff,0x04,0x80,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_u64 s[0:1], 0xaf123456, s4
-// GFX10: encoding: [0xff,0x04,0x80,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_u64 s[0:1], s[2:3], exec_lo
-// GFX10: encoding: [0x02,0x7e,0x80,0x94]
-
-s_bfe_u64 s[0:1], s[2:3], vcc_lo
-// GFX10: encoding: [0x02,0x6a,0x80,0x94]
-
-s_bfe_u64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x80,0x94]
-
-s_bfe_u64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x80,0x94]
-
-s_bfe_u64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x80,0x94]
-
-s_bfe_u64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x80,0x94]
-
-s_bfe_u64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x80,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_u64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x80,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_i64 s[0:1], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0x00,0x95]
-
-s_bfe_i64 s[104:105], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0x68,0x95]
-
-s_bfe_i64 s[0:1], s[102:103], s100
-// GFX10: encoding: [0x66,0x64,0x00,0x95]
-
-s_bfe_i64 s[104:105], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0x68,0x95]
-
-s_bfe_i64 s[104:105], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0x68,0x95]
-
-s_bfe_i64 s[104:105], s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0x68,0x95]
-
-s_bfe_i64 s[0:1], s[102:103], s4
-// GFX10: encoding: [0x66,0x04,0x00,0x95]
-
-s_bfe_i64 s[0:1], s[2:3], s100
-// GFX10: encoding: [0x02,0x64,0x00,0x95]
-
-s_bfe_i64 exec, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0x7e,0x95]
-
-s_bfe_i64 vcc, s[2:3], s4
-// GFX10: encoding: [0x02,0x04,0x6a,0x95]
-
-s_bfe_i64 s[0:1], exec, s4
-// GFX10: encoding: [0x7e,0x04,0x00,0x95]
-
-s_bfe_i64 s[0:1], vcc, s4
-// GFX10: encoding: [0x6a,0x04,0x00,0x95]
-
-s_bfe_i64 s[0:1], 0, s4
-// GFX10: encoding: [0x80,0x04,0x00,0x95]
-
-s_bfe_i64 s[0:1], -1, s4
-// GFX10: encoding: [0xc1,0x04,0x00,0x95]
-
-s_bfe_i64 s[0:1], 0.5, s4
-// GFX10: encoding: [0xf0,0x04,0x00,0x95]
-
-s_bfe_i64 s[0:1], -4.0, s4
-// GFX10: encoding: [0xf7,0x04,0x00,0x95]
-
-s_bfe_i64 s[0:1], 0x3f717273, s4
-// GFX10: encoding: [0xff,0x04,0x00,0x95,0x73,0x72,0x71,0x3f]
-
-s_bfe_i64 s[0:1], 0xaf123456, s4
-// GFX10: encoding: [0xff,0x04,0x00,0x95,0x56,0x34,0x12,0xaf]
-
-s_bfe_i64 s[0:1], s[2:3], exec_lo
-// GFX10: encoding: [0x02,0x7e,0x00,0x95]
-
-s_bfe_i64 s[0:1], s[2:3], vcc_lo
-// GFX10: encoding: [0x02,0x6a,0x00,0x95]
-
-s_bfe_i64 s[0:1], s[2:3], 0
-// GFX10: encoding: [0x02,0x80,0x00,0x95]
-
-s_bfe_i64 s[0:1], s[2:3], -1
-// GFX10: encoding: [0x02,0xc1,0x00,0x95]
-
-s_bfe_i64 s[0:1], s[2:3], 0.5
-// GFX10: encoding: [0x02,0xf0,0x00,0x95]
-
-s_bfe_i64 s[0:1], s[2:3], -4.0
-// GFX10: encoding: [0x02,0xf7,0x00,0x95]
-
-s_bfe_i64 s[0:1], s[2:3], 0x3f717273
-// GFX10: encoding: [0x02,0xff,0x00,0x95,0x73,0x72,0x71,0x3f]
-
-s_bfe_i64 s[0:1], s[2:3], 0xaf123456
-// GFX10: encoding: [0x02,0xff,0x00,0x95,0x56,0x34,0x12,0xaf]
-
-s_absdiff_i32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x96]
-
-s_absdiff_i32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x96]
-
-s_absdiff_i32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x96]
-
-s_absdiff_i32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x96]
-
-s_absdiff_i32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x96]
-
-s_absdiff_i32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x96]
-
-s_absdiff_i32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x96]
-
-s_absdiff_i32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x96]
-
-s_absdiff_i32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x96]
-
-s_absdiff_i32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x96]
-
-s_absdiff_i32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x96]
-
-s_absdiff_i32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x96]
-
-s_absdiff_i32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x96]
-
-s_absdiff_i32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x96,0x73,0x72,0x71,0x3f]
-
-s_absdiff_i32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x96,0x56,0x34,0x12,0xaf]
-
-s_absdiff_i32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x96]
-
-s_absdiff_i32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x96]
-
-s_absdiff_i32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x96]
-
-s_absdiff_i32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x96]
-
-s_absdiff_i32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x96]
-
-s_absdiff_i32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x96]
-
-s_absdiff_i32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x96]
-
-s_absdiff_i32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x96]
-
-s_absdiff_i32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x96]
-
-s_absdiff_i32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x96,0x73,0x72,0x71,0x3f]
-
-s_absdiff_i32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x96,0x56,0x34,0x12,0xaf]
-
-s_lshl1_add_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x97]
-
-s_lshl1_add_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x97]
-
-s_lshl1_add_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x97]
-
-s_lshl1_add_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x97]
-
-s_lshl1_add_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x97]
-
-s_lshl1_add_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x97]
-
-s_lshl1_add_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x97]
-
-s_lshl1_add_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x97]
-
-s_lshl1_add_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x97]
-
-s_lshl1_add_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x97]
-
-s_lshl1_add_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x97]
-
-s_lshl1_add_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x97]
-
-s_lshl1_add_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x97,0x73,0x72,0x71,0x3f]
-
-s_lshl1_add_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x97,0x56,0x34,0x12,0xaf]
-
-s_lshl1_add_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x97]
-
-s_lshl1_add_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x97,0x73,0x72,0x71,0x3f]
-
-s_lshl1_add_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x97,0x56,0x34,0x12,0xaf]
-
-s_lshl2_add_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x97]
-
-s_lshl2_add_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x97]
-
-s_lshl2_add_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x97]
-
-s_lshl2_add_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x97]
-
-s_lshl2_add_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x97]
-
-s_lshl2_add_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x97]
-
-s_lshl2_add_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x97]
-
-s_lshl2_add_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x97]
-
-s_lshl2_add_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x97]
-
-s_lshl2_add_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x97]
-
-s_lshl2_add_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x97]
-
-s_lshl2_add_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x97]
-
-s_lshl2_add_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x97,0x73,0x72,0x71,0x3f]
-
-s_lshl2_add_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x97,0x56,0x34,0x12,0xaf]
-
-s_lshl2_add_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x97]
-
-s_lshl2_add_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x97,0x73,0x72,0x71,0x3f]
-
-s_lshl2_add_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x97,0x56,0x34,0x12,0xaf]
-
-s_lshl3_add_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x98]
-
-s_lshl3_add_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x98]
-
-s_lshl3_add_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x98]
-
-s_lshl3_add_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x98]
-
-s_lshl3_add_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x98]
-
-s_lshl3_add_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x98]
-
-s_lshl3_add_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x98]
-
-s_lshl3_add_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x98]
-
-s_lshl3_add_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x98]
-
-s_lshl3_add_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x98]
-
-s_lshl3_add_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x98]
-
-s_lshl3_add_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x98]
-
-s_lshl3_add_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x98,0x73,0x72,0x71,0x3f]
-
-s_lshl3_add_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x98,0x56,0x34,0x12,0xaf]
-
-s_lshl3_add_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x98]
-
-s_lshl3_add_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x98,0x73,0x72,0x71,0x3f]
-
-s_lshl3_add_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x98,0x56,0x34,0x12,0xaf]
-
-s_lshl4_add_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x98]
-
-s_lshl4_add_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x98]
-
-s_lshl4_add_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x98]
-
-s_lshl4_add_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x98]
-
-s_lshl4_add_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x98]
-
-s_lshl4_add_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x98]
-
-s_lshl4_add_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x98]
-
-s_lshl4_add_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x98]
-
-s_lshl4_add_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x98]
-
-s_lshl4_add_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x98]
-
-s_lshl4_add_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x98]
-
-s_lshl4_add_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x98]
-
-s_lshl4_add_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x98,0x73,0x72,0x71,0x3f]
-
-s_lshl4_add_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x98,0x56,0x34,0x12,0xaf]
-
-s_lshl4_add_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x98]
-
-s_lshl4_add_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x98,0x73,0x72,0x71,0x3f]
-
-s_lshl4_add_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x98,0x56,0x34,0x12,0xaf]
-
-s_pack_ll_b32_b16 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x99]
-
-s_pack_ll_b32_b16 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x99]
-
-s_pack_ll_b32_b16 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x99]
-
-s_pack_ll_b32_b16 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x99]
-
-s_pack_ll_b32_b16 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x99]
-
-s_pack_ll_b32_b16 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x99]
-
-s_pack_ll_b32_b16 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x99]
-
-s_pack_ll_b32_b16 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x99]
-
-s_pack_ll_b32_b16 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x99]
-
-s_pack_ll_b32_b16 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x99]
-
-s_pack_ll_b32_b16 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x99]
-
-s_pack_ll_b32_b16 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x99,0x73,0x72,0x71,0x3f]
-
-s_pack_ll_b32_b16 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x99,0x56,0x34,0x12,0xaf]
-
-s_pack_ll_b32_b16 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x99]
-
-s_pack_ll_b32_b16 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x99,0x73,0x72,0x71,0x3f]
-
-s_pack_ll_b32_b16 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x99,0x56,0x34,0x12,0xaf]
-
-s_pack_lh_b32_b16 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x99]
-
-s_pack_lh_b32_b16 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x99]
-
-s_pack_lh_b32_b16 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x99]
-
-s_pack_lh_b32_b16 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x99]
-
-s_pack_lh_b32_b16 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x99]
-
-s_pack_lh_b32_b16 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x99]
-
-s_pack_lh_b32_b16 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x99]
-
-s_pack_lh_b32_b16 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x99]
-
-s_pack_lh_b32_b16 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x99]
-
-s_pack_lh_b32_b16 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x99]
-
-s_pack_lh_b32_b16 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x99]
-
-s_pack_lh_b32_b16 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x99,0x73,0x72,0x71,0x3f]
-
-s_pack_lh_b32_b16 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x99,0x56,0x34,0x12,0xaf]
-
-s_pack_lh_b32_b16 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x99]
-
-s_pack_lh_b32_b16 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x99,0x73,0x72,0x71,0x3f]
-
-s_pack_lh_b32_b16 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x99,0x56,0x34,0x12,0xaf]
-
-s_pack_hh_b32_b16 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x9a]
-
-s_pack_hh_b32_b16 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x9a]
-
-s_pack_hh_b32_b16 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x9a]
-
-s_pack_hh_b32_b16 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x9a]
-
-s_pack_hh_b32_b16 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x9a]
-
-s_pack_hh_b32_b16 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x9a]
-
-s_pack_hh_b32_b16 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x9a]
-
-s_pack_hh_b32_b16 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x9a]
-
-s_pack_hh_b32_b16 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x9a]
-
-s_pack_hh_b32_b16 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x9a]
-
-s_pack_hh_b32_b16 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x9a]
-
-s_pack_hh_b32_b16 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x9a,0x73,0x72,0x71,0x3f]
-
-s_pack_hh_b32_b16 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x9a,0x56,0x34,0x12,0xaf]
-
-s_pack_hh_b32_b16 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x9a]
-
-s_pack_hh_b32_b16 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x9a,0x73,0x72,0x71,0x3f]
-
-s_pack_hh_b32_b16 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x9a,0x56,0x34,0x12,0xaf]
-
-s_mul_hi_u32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0xe9,0x9a]
-
-s_mul_hi_u32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x80,0x9a]
-
-s_mul_hi_u32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0xe9,0x9a]
-
-s_mul_hi_u32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0xe9,0x9a]
-
-s_mul_hi_u32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0xe9,0x9a]
-
-s_mul_hi_u32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x80,0x9a]
-
-s_mul_hi_u32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfe,0x9a]
-
-s_mul_hi_u32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xff,0x9a]
-
-s_mul_hi_u32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0xea,0x9a]
-
-s_mul_hi_u32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0xeb,0x9a]
-
-s_mul_hi_u32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0xfc,0x9a]
-
-s_mul_hi_u32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x80,0x9a]
-
-s_mul_hi_u32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x9a,0x73,0x72,0x71,0x3f]
-
-s_mul_hi_u32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x80,0x9a,0x56,0x34,0x12,0xaf]
-
-s_mul_hi_u32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x80,0x9a]
-
-s_mul_hi_u32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x80,0x9a,0x73,0x72,0x71,0x3f]
-
-s_mul_hi_u32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x80,0x9a,0x56,0x34,0x12,0xaf]
-
-s_mul_hi_i32 s0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s105, s104, s103
-// GFX10: encoding: [0x68,0x67,0x69,0x9b]
-
-s_mul_hi_i32 s0, s104, s103
-// GFX10: encoding: [0x68,0x67,0x00,0x9b]
-
-s_mul_hi_i32 s105, s1, s103
-// GFX10: encoding: [0x01,0x67,0x69,0x9b]
-
-s_mul_hi_i32 s105, s104, s2
-// GFX10: encoding: [0x68,0x02,0x69,0x9b]
-
-s_mul_hi_i32 s105, s1, s2
-// GFX10: encoding: [0x01,0x02,0x69,0x9b]
-
-s_mul_hi_i32 s0, s104, s2
-// GFX10: encoding: [0x68,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, s103
-// GFX10: encoding: [0x01,0x67,0x00,0x9b]
-
-s_mul_hi_i32 exec_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7e,0x9b]
-
-s_mul_hi_i32 exec_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7f,0x9b]
-
-s_mul_hi_i32 vcc_lo, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6a,0x9b]
-
-s_mul_hi_i32 vcc_hi, s1, s2
-// GFX10: encoding: [0x01,0x02,0x6b,0x9b]
-
-s_mul_hi_i32 m0, s1, s2
-// GFX10: encoding: [0x01,0x02,0x7c,0x9b]
-
-s_mul_hi_i32 s0, exec_lo, s2
-// GFX10: encoding: [0x7e,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, exec_hi, s2
-// GFX10: encoding: [0x7f,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, vcc_lo, s2
-// GFX10: encoding: [0x6a,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, vcc_hi, s2
-// GFX10: encoding: [0x6b,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, m0, s2
-// GFX10: encoding: [0x7c,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, 0, s2
-// GFX10: encoding: [0x80,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, -1, s2
-// GFX10: encoding: [0xc1,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, 0.5, s2
-// GFX10: encoding: [0xf0,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, -4.0, s2
-// GFX10: encoding: [0xf7,0x02,0x00,0x9b]
-
-s_mul_hi_i32 s0, 0x3f717273, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x9b,0x73,0x72,0x71,0x3f]
-
-s_mul_hi_i32 s0, 0xaf123456, s2
-// GFX10: encoding: [0xff,0x02,0x00,0x9b,0x56,0x34,0x12,0xaf]
-
-s_mul_hi_i32 s0, s1, exec_lo
-// GFX10: encoding: [0x01,0x7e,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, exec_hi
-// GFX10: encoding: [0x01,0x7f,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, vcc_lo
-// GFX10: encoding: [0x01,0x6a,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, vcc_hi
-// GFX10: encoding: [0x01,0x6b,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, m0
-// GFX10: encoding: [0x01,0x7c,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, 0
-// GFX10: encoding: [0x01,0x80,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, -1
-// GFX10: encoding: [0x01,0xc1,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, 0.5
-// GFX10: encoding: [0x01,0xf0,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, -4.0
-// GFX10: encoding: [0x01,0xf7,0x00,0x9b]
-
-s_mul_hi_i32 s0, s1, 0x3f717273
-// GFX10: encoding: [0x01,0xff,0x00,0x9b,0x73,0x72,0x71,0x3f]
-
-s_mul_hi_i32 s0, s1, 0xaf123456
-// GFX10: encoding: [0x01,0xff,0x00,0x9b,0x56,0x34,0x12,0xaf]
-
-//===----------------------------------------------------------------------===//
-// ENC_SOPC.
-//===----------------------------------------------------------------------===//
-
-s_cmp_eq_i32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x00,0xbf]
-
-s_cmp_eq_i32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x00,0xbf]
-
-s_cmp_eq_i32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x00,0xbf]
-
-s_cmp_eq_i32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x00,0xbf]
-
-s_cmp_eq_i32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x00,0xbf]
-
-s_cmp_eq_i32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x00,0xbf]
-
-s_cmp_eq_i32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x00,0xbf]
-
-s_cmp_eq_i32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x00,0xbf]
-
-s_cmp_eq_i32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x00,0xbf]
-
-s_cmp_eq_i32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x00,0xbf]
-
-s_cmp_eq_i32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x00,0xbf]
-
-s_cmp_eq_i32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x00,0xbf]
-
-s_cmp_eq_i32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x00,0xbf]
-
-s_cmp_eq_i32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x00,0xbf]
-
-s_cmp_eq_i32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x00,0xbf]
-
-s_cmp_eq_i32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x00,0xbf]
-
-s_cmp_eq_i32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x00,0xbf]
-
-s_cmp_eq_i32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x00,0xbf]
-
-s_cmp_eq_i32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_i32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_i32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x01,0xbf]
-
-s_cmp_lg_i32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x01,0xbf]
-
-s_cmp_lg_i32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x01,0xbf]
-
-s_cmp_lg_i32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x01,0xbf]
-
-s_cmp_lg_i32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x01,0xbf]
-
-s_cmp_lg_i32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x01,0xbf]
-
-s_cmp_lg_i32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x01,0xbf]
-
-s_cmp_lg_i32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x01,0xbf]
-
-s_cmp_lg_i32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x01,0xbf]
-
-s_cmp_lg_i32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x01,0xbf]
-
-s_cmp_lg_i32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x01,0xbf]
-
-s_cmp_lg_i32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x01,0xbf]
-
-s_cmp_lg_i32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x01,0xbf]
-
-s_cmp_lg_i32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x01,0xbf]
-
-s_cmp_lg_i32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x01,0xbf]
-
-s_cmp_lg_i32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x01,0xbf]
-
-s_cmp_lg_i32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x01,0xbf]
-
-s_cmp_lg_i32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x01,0xbf]
-
-s_cmp_lg_i32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_i32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_i32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x02,0xbf]
-
-s_cmp_gt_i32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x02,0xbf]
-
-s_cmp_gt_i32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x02,0xbf]
-
-s_cmp_gt_i32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x02,0xbf]
-
-s_cmp_gt_i32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x02,0xbf]
-
-s_cmp_gt_i32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x02,0xbf]
-
-s_cmp_gt_i32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x02,0xbf]
-
-s_cmp_gt_i32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x02,0xbf]
-
-s_cmp_gt_i32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x02,0xbf]
-
-s_cmp_gt_i32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x02,0xbf]
-
-s_cmp_gt_i32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x02,0xbf]
-
-s_cmp_gt_i32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x02,0xbf]
-
-s_cmp_gt_i32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x02,0xbf]
-
-s_cmp_gt_i32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x02,0xbf]
-
-s_cmp_gt_i32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x02,0xbf]
-
-s_cmp_gt_i32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x02,0xbf]
-
-s_cmp_gt_i32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x02,0xbf]
-
-s_cmp_gt_i32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x02,0xbf]
-
-s_cmp_gt_i32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_i32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_i32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x03,0xbf]
-
-s_cmp_ge_i32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x03,0xbf]
-
-s_cmp_ge_i32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x03,0xbf]
-
-s_cmp_ge_i32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x03,0xbf]
-
-s_cmp_ge_i32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x03,0xbf]
-
-s_cmp_ge_i32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x03,0xbf]
-
-s_cmp_ge_i32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x03,0xbf]
-
-s_cmp_ge_i32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x03,0xbf]
-
-s_cmp_ge_i32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x03,0xbf]
-
-s_cmp_ge_i32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x03,0xbf]
-
-s_cmp_ge_i32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x03,0xbf]
-
-s_cmp_ge_i32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x03,0xbf]
-
-s_cmp_ge_i32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x03,0xbf]
-
-s_cmp_ge_i32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x03,0xbf]
-
-s_cmp_ge_i32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x03,0xbf]
-
-s_cmp_ge_i32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x03,0xbf]
-
-s_cmp_ge_i32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x03,0xbf]
-
-s_cmp_ge_i32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x03,0xbf]
-
-s_cmp_ge_i32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_i32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_i32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x04,0xbf]
-
-s_cmp_lt_i32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x04,0xbf]
-
-s_cmp_lt_i32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x04,0xbf]
-
-s_cmp_lt_i32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x04,0xbf]
-
-s_cmp_lt_i32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x04,0xbf]
-
-s_cmp_lt_i32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x04,0xbf]
-
-s_cmp_lt_i32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x04,0xbf]
-
-s_cmp_lt_i32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x04,0xbf]
-
-s_cmp_lt_i32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x04,0xbf]
-
-s_cmp_lt_i32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x04,0xbf]
-
-s_cmp_lt_i32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x04,0xbf]
-
-s_cmp_lt_i32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x04,0xbf]
-
-s_cmp_lt_i32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x04,0xbf]
-
-s_cmp_lt_i32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x04,0xbf]
-
-s_cmp_lt_i32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x04,0xbf]
-
-s_cmp_lt_i32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x04,0xbf]
-
-s_cmp_lt_i32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x04,0xbf]
-
-s_cmp_lt_i32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x04,0xbf]
-
-s_cmp_lt_i32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_i32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_i32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x05,0xbf]
-
-s_cmp_le_i32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x05,0xbf]
-
-s_cmp_le_i32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x05,0xbf]
-
-s_cmp_le_i32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x05,0xbf]
-
-s_cmp_le_i32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x05,0xbf]
-
-s_cmp_le_i32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x05,0xbf]
-
-s_cmp_le_i32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x05,0xbf]
-
-s_cmp_le_i32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x05,0xbf]
-
-s_cmp_le_i32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x05,0xbf]
-
-s_cmp_le_i32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x05,0xbf]
-
-s_cmp_le_i32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x05,0xbf]
-
-s_cmp_le_i32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x05,0xbf]
-
-s_cmp_le_i32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x05,0xbf]
-
-s_cmp_le_i32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x05,0xbf]
-
-s_cmp_le_i32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x05,0xbf]
-
-s_cmp_le_i32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x05,0xbf]
-
-s_cmp_le_i32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x05,0xbf]
-
-s_cmp_le_i32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x05,0xbf]
-
-s_cmp_le_i32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_i32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x06,0xbf]
-
-s_cmp_eq_u32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x06,0xbf]
-
-s_cmp_eq_u32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x06,0xbf]
-
-s_cmp_eq_u32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x06,0xbf]
-
-s_cmp_eq_u32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x06,0xbf]
-
-s_cmp_eq_u32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x06,0xbf]
-
-s_cmp_eq_u32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x06,0xbf]
-
-s_cmp_eq_u32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x06,0xbf]
-
-s_cmp_eq_u32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x06,0xbf]
-
-s_cmp_eq_u32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x06,0xbf]
-
-s_cmp_eq_u32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x06,0xbf]
-
-s_cmp_eq_u32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x06,0xbf]
-
-s_cmp_eq_u32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x06,0xbf]
-
-s_cmp_eq_u32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x06,0xbf]
-
-s_cmp_eq_u32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x06,0xbf]
-
-s_cmp_eq_u32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x06,0xbf]
-
-s_cmp_eq_u32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x06,0xbf]
-
-s_cmp_eq_u32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x06,0xbf]
-
-s_cmp_eq_u32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x07,0xbf]
-
-s_cmp_lg_u32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x07,0xbf]
-
-s_cmp_lg_u32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x07,0xbf]
-
-s_cmp_lg_u32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x07,0xbf]
-
-s_cmp_lg_u32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x07,0xbf]
-
-s_cmp_lg_u32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x07,0xbf]
-
-s_cmp_lg_u32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x07,0xbf]
-
-s_cmp_lg_u32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x07,0xbf]
-
-s_cmp_lg_u32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x07,0xbf]
-
-s_cmp_lg_u32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x07,0xbf]
-
-s_cmp_lg_u32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x07,0xbf]
-
-s_cmp_lg_u32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x07,0xbf]
-
-s_cmp_lg_u32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x07,0xbf]
-
-s_cmp_lg_u32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x07,0xbf]
-
-s_cmp_lg_u32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x07,0xbf]
-
-s_cmp_lg_u32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x07,0xbf]
-
-s_cmp_lg_u32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x07,0xbf]
-
-s_cmp_lg_u32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x07,0xbf]
-
-s_cmp_lg_u32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_u32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x08,0xbf]
-
-s_cmp_gt_u32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x08,0xbf]
-
-s_cmp_gt_u32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x08,0xbf]
-
-s_cmp_gt_u32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x08,0xbf]
-
-s_cmp_gt_u32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x08,0xbf]
-
-s_cmp_gt_u32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x08,0xbf]
-
-s_cmp_gt_u32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x08,0xbf]
-
-s_cmp_gt_u32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x08,0xbf]
-
-s_cmp_gt_u32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x08,0xbf]
-
-s_cmp_gt_u32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x08,0xbf]
-
-s_cmp_gt_u32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x08,0xbf]
-
-s_cmp_gt_u32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x08,0xbf]
-
-s_cmp_gt_u32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x08,0xbf]
-
-s_cmp_gt_u32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x08,0xbf]
-
-s_cmp_gt_u32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x08,0xbf]
-
-s_cmp_gt_u32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x08,0xbf]
-
-s_cmp_gt_u32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x08,0xbf]
-
-s_cmp_gt_u32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x08,0xbf]
-
-s_cmp_gt_u32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_u32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_u32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x09,0xbf]
-
-s_cmp_ge_u32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x09,0xbf]
-
-s_cmp_ge_u32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x09,0xbf]
-
-s_cmp_ge_u32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x09,0xbf]
-
-s_cmp_ge_u32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x09,0xbf]
-
-s_cmp_ge_u32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x09,0xbf]
-
-s_cmp_ge_u32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x09,0xbf]
-
-s_cmp_ge_u32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x09,0xbf]
-
-s_cmp_ge_u32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x09,0xbf]
-
-s_cmp_ge_u32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x09,0xbf]
-
-s_cmp_ge_u32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x09,0xbf]
-
-s_cmp_ge_u32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x09,0xbf]
-
-s_cmp_ge_u32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x09,0xbf]
-
-s_cmp_ge_u32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x09,0xbf]
-
-s_cmp_ge_u32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x09,0xbf]
-
-s_cmp_ge_u32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x09,0xbf]
-
-s_cmp_ge_u32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x09,0xbf]
-
-s_cmp_ge_u32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x09,0xbf]
-
-s_cmp_ge_u32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_u32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_u32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x0a,0xbf]
-
-s_cmp_lt_u32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x0a,0xbf]
-
-s_cmp_lt_u32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x0a,0xbf]
-
-s_cmp_lt_u32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x0a,0xbf]
-
-s_cmp_lt_u32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x0a,0xbf]
-
-s_cmp_lt_u32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x0a,0xbf]
-
-s_cmp_lt_u32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x0a,0xbf]
-
-s_cmp_lt_u32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x0a,0xbf]
-
-s_cmp_lt_u32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_u32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_u32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x0b,0xbf]
-
-s_cmp_le_u32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x0b,0xbf]
-
-s_cmp_le_u32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x0b,0xbf]
-
-s_cmp_le_u32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x0b,0xbf]
-
-s_cmp_le_u32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x0b,0xbf]
-
-s_cmp_le_u32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x0b,0xbf]
-
-s_cmp_le_u32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x0b,0xbf]
-
-s_cmp_le_u32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x0b,0xbf]
-
-s_cmp_le_u32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x0b,0xbf]
-
-s_cmp_le_u32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x0b,0xbf]
-
-s_cmp_le_u32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x0b,0xbf]
-
-s_cmp_le_u32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x0b,0xbf]
-
-s_cmp_le_u32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x0b,0xbf]
-
-s_cmp_le_u32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x0b,0xbf]
-
-s_cmp_le_u32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x0b,0xbf]
-
-s_cmp_le_u32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x0b,0xbf]
-
-s_cmp_le_u32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x0b,0xbf]
-
-s_cmp_le_u32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x0b,0xbf]
-
-s_cmp_le_u32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_u32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x0c,0xbf]
-
-s_bitcmp0_b32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x0c,0xbf]
-
-s_bitcmp0_b32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x0c,0xbf]
-
-s_bitcmp0_b32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x0c,0xbf]
-
-s_bitcmp0_b32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x0c,0xbf]
-
-s_bitcmp0_b32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x0c,0xbf]
-
-s_bitcmp0_b32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x0c,0xbf]
-
-s_bitcmp0_b32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x0c,0xbf]
-
-s_bitcmp0_b32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b32 s0, s1
-// GFX10: encoding: [0x00,0x01,0x0d,0xbf]
-
-s_bitcmp1_b32 s105, s104
-// GFX10: encoding: [0x69,0x68,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, s104
-// GFX10: encoding: [0x00,0x68,0x0d,0xbf]
-
-s_bitcmp1_b32 s105, s1
-// GFX10: encoding: [0x69,0x01,0x0d,0xbf]
-
-s_bitcmp1_b32 exec_lo, s1
-// GFX10: encoding: [0x7e,0x01,0x0d,0xbf]
-
-s_bitcmp1_b32 exec_hi, s1
-// GFX10: encoding: [0x7f,0x01,0x0d,0xbf]
-
-s_bitcmp1_b32 vcc_lo, s1
-// GFX10: encoding: [0x6a,0x01,0x0d,0xbf]
-
-s_bitcmp1_b32 vcc_hi, s1
-// GFX10: encoding: [0x6b,0x01,0x0d,0xbf]
-
-s_bitcmp1_b32 m0, s1
-// GFX10: encoding: [0x7c,0x01,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, exec_lo
-// GFX10: encoding: [0x00,0x7e,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, exec_hi
-// GFX10: encoding: [0x00,0x7f,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, m0
-// GFX10: encoding: [0x00,0x7c,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, 0
-// GFX10: encoding: [0x00,0x80,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, -1
-// GFX10: encoding: [0x00,0xc1,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, 0.5
-// GFX10: encoding: [0x00,0xf0,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, -4.0
-// GFX10: encoding: [0x00,0xf7,0x0d,0xbf]
-
-s_bitcmp1_b32 s0, 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b32 s0, 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b64 s[0:1], s2
-// GFX10: encoding: [0x00,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 s[104:105], s102
-// GFX10: encoding: [0x68,0x66,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], s102
-// GFX10: encoding: [0x00,0x66,0x0e,0xbf]
-
-s_bitcmp0_b64 s[104:105], s2
-// GFX10: encoding: [0x68,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 exec, s2
-// GFX10: encoding: [0x7e,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 vcc, s2
-// GFX10: encoding: [0x6a,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], exec_lo
-// GFX10: encoding: [0x00,0x7e,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], exec_hi
-// GFX10: encoding: [0x00,0x7f,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], m0
-// GFX10: encoding: [0x00,0x7c,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], 0
-// GFX10: encoding: [0x00,0x80,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], -1
-// GFX10: encoding: [0x00,0xc1,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], 0.5
-// GFX10: encoding: [0x00,0xf0,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], -4.0
-// GFX10: encoding: [0x00,0xf7,0x0e,0xbf]
-
-s_bitcmp0_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b64 s[0:1], s2
-// GFX10: encoding: [0x00,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 s[104:105], s102
-// GFX10: encoding: [0x68,0x66,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], s102
-// GFX10: encoding: [0x00,0x66,0x0f,0xbf]
-
-s_bitcmp1_b64 s[104:105], s2
-// GFX10: encoding: [0x68,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 exec, s2
-// GFX10: encoding: [0x7e,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 vcc, s2
-// GFX10: encoding: [0x6a,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], exec_lo
-// GFX10: encoding: [0x00,0x7e,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], exec_hi
-// GFX10: encoding: [0x00,0x7f,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], vcc_lo
-// GFX10: encoding: [0x00,0x6a,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], vcc_hi
-// GFX10: encoding: [0x00,0x6b,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], m0
-// GFX10: encoding: [0x00,0x7c,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], 0
-// GFX10: encoding: [0x00,0x80,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], -1
-// GFX10: encoding: [0x00,0xc1,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], 0.5
-// GFX10: encoding: [0x00,0xf0,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], -4.0
-// GFX10: encoding: [0x00,0xf7,0x0f,0xbf]
-
-s_bitcmp1_b64 s[0:1], 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b64 s[0:1], 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u64 s[0:1], s[2:3]
-// GFX10: encoding: [0x00,0x02,0x12,0xbf]
-
-s_cmp_eq_u64 s[104:105], s[102:103]
-// GFX10: encoding: [0x68,0x66,0x12,0xbf]
-
-s_cmp_eq_u64 s[0:1], s[102:103]
-// GFX10: encoding: [0x00,0x66,0x12,0xbf]
-
-s_cmp_eq_u64 s[104:105], s[2:3]
-// GFX10: encoding: [0x68,0x02,0x12,0xbf]
-
-s_cmp_eq_u64 exec, s[2:3]
-// GFX10: encoding: [0x7e,0x02,0x12,0xbf]
-
-s_cmp_eq_u64 vcc, s[2:3]
-// GFX10: encoding: [0x6a,0x02,0x12,0xbf]
-
-s_cmp_eq_u64 s[0:1], exec
-// GFX10: encoding: [0x00,0x7e,0x12,0xbf]
-
-s_cmp_eq_u64 s[0:1], vcc
-// GFX10: encoding: [0x00,0x6a,0x12,0xbf]
-
-s_cmp_eq_u64 s[0:1], 0
-// GFX10: encoding: [0x00,0x80,0x12,0xbf]
-
-s_cmp_eq_u64 s[0:1], -1
-// GFX10: encoding: [0x00,0xc1,0x12,0xbf]
-
-s_cmp_eq_u64 s[0:1], 0.5
-// GFX10: encoding: [0x00,0xf0,0x12,0xbf]
-
-s_cmp_eq_u64 s[0:1], -4.0
-// GFX10: encoding: [0x00,0xf7,0x12,0xbf]
-
-s_cmp_eq_u64 s[0:1], 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x12,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u64 s[0:1], 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x12,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u64 s[0:1], s[2:3]
-// GFX10: encoding: [0x00,0x02,0x13,0xbf]
-
-s_cmp_lg_u64 s[104:105], s[102:103]
-// GFX10: encoding: [0x68,0x66,0x13,0xbf]
-
-s_cmp_lg_u64 s[0:1], s[102:103]
-// GFX10: encoding: [0x00,0x66,0x13,0xbf]
-
-s_cmp_lg_u64 s[104:105], s[2:3]
-// GFX10: encoding: [0x68,0x02,0x13,0xbf]
-
-s_cmp_lg_u64 exec, s[2:3]
-// GFX10: encoding: [0x7e,0x02,0x13,0xbf]
-
-s_cmp_lg_u64 vcc, s[2:3]
-// GFX10: encoding: [0x6a,0x02,0x13,0xbf]
-
-s_cmp_lg_u64 s[0:1], exec
-// GFX10: encoding: [0x00,0x7e,0x13,0xbf]
-
-s_cmp_lg_u64 s[0:1], vcc
-// GFX10: encoding: [0x00,0x6a,0x13,0xbf]
-
-s_cmp_lg_u64 s[0:1], 0
-// GFX10: encoding: [0x00,0x80,0x13,0xbf]
-
-s_cmp_lg_u64 s[0:1], -1
-// GFX10: encoding: [0x00,0xc1,0x13,0xbf]
-
-s_cmp_lg_u64 s[0:1], 0.5
-// GFX10: encoding: [0x00,0xf0,0x13,0xbf]
-
-s_cmp_lg_u64 s[0:1], -4.0
-// GFX10: encoding: [0x00,0xf7,0x13,0xbf]
-
-s_cmp_lg_u64 s[0:1], 0x3f717273
-// GFX10: encoding: [0x00,0xff,0x13,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u64 s[0:1], 0xaf123456
-// GFX10: encoding: [0x00,0xff,0x13,0xbf,0x56,0x34,0x12,0xaf]
-
-//===----------------------------------------------------------------------===//
-// ENC_SOPK.
-//===----------------------------------------------------------------------===//
-
-s_movk_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb0]
-
-s_movk_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb0]
-
-s_movk_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb0]
-
-s_movk_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb0]
-
-s_movk_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb0]
-
-s_movk_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb0]
-
-s_movk_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb0]
-
-s_movk_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb0]
-
-s_version 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xb0]
-
-s_version 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xb0]
-
-s_cmovk_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb1]
-
-s_cmovk_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb1]
-
-s_cmovk_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb1]
-
-s_cmovk_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb1]
-
-s_cmovk_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb1]
-
-s_cmovk_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb1]
-
-s_cmovk_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb1]
-
-s_cmovk_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb1]
-
-s_cmpk_eq_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xb1]
-
-s_cmpk_eq_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xb1]
-
-s_cmpk_eq_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xb1]
-
-s_cmpk_eq_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xb1]
-
-s_cmpk_eq_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xb1]
-
-s_cmpk_eq_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xb1]
-
-s_cmpk_eq_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xb1]
-
-s_cmpk_eq_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xb1]
-
-s_cmpk_lg_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb2]
-
-s_cmpk_lg_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb2]
-
-s_cmpk_lg_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb2]
-
-s_cmpk_lg_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb2]
-
-s_cmpk_lg_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb2]
-
-s_cmpk_lg_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb2]
-
-s_cmpk_lg_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb2]
-
-s_cmpk_lg_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb2]
-
-s_cmpk_gt_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xb2]
-
-s_cmpk_gt_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xb2]
-
-s_cmpk_gt_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xb2]
-
-s_cmpk_gt_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xb2]
-
-s_cmpk_gt_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xb2]
-
-s_cmpk_gt_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xb2]
-
-s_cmpk_gt_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xb2]
-
-s_cmpk_gt_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xb2]
-
-s_cmpk_ge_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb3]
-
-s_cmpk_ge_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb3]
-
-s_cmpk_ge_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb3]
-
-s_cmpk_ge_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb3]
-
-s_cmpk_ge_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb3]
-
-s_cmpk_ge_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb3]
-
-s_cmpk_ge_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb3]
-
-s_cmpk_ge_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb3]
-
-s_cmpk_lt_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xb3]
-
-s_cmpk_lt_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xb3]
-
-s_cmpk_lt_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xb3]
-
-s_cmpk_lt_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xb3]
-
-s_cmpk_lt_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xb3]
-
-s_cmpk_lt_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xb3]
-
-s_cmpk_lt_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xb3]
-
-s_cmpk_lt_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xb3]
-
-s_cmpk_le_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb4]
-
-s_cmpk_le_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb4]
-
-s_cmpk_le_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb4]
-
-s_cmpk_le_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb4]
-
-s_cmpk_le_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb4]
-
-s_cmpk_le_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb4]
-
-s_cmpk_le_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb4]
-
-s_cmpk_le_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb4]
-
-s_cmpk_eq_u32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xb4]
-
-s_cmpk_eq_u32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xb4]
-
-s_cmpk_eq_u32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xb4]
-
-s_cmpk_eq_u32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xb4]
-
-s_cmpk_eq_u32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xb4]
-
-s_cmpk_eq_u32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xb4]
-
-s_cmpk_eq_u32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xb4]
-
-s_cmpk_eq_u32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xb4]
-
-s_cmpk_lg_u32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb5]
-
-s_cmpk_lg_u32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb5]
-
-s_cmpk_lg_u32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb5]
-
-s_cmpk_lg_u32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb5]
-
-s_cmpk_lg_u32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb5]
-
-s_cmpk_lg_u32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb5]
-
-s_cmpk_lg_u32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb5]
-
-s_cmpk_lg_u32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb5]
-
-s_cmpk_gt_u32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xb5]
-
-s_cmpk_gt_u32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xb5]
-
-s_cmpk_gt_u32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xb5]
-
-s_cmpk_gt_u32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xb5]
-
-s_cmpk_gt_u32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xb5]
-
-s_cmpk_gt_u32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xb5]
-
-s_cmpk_gt_u32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xb5]
-
-s_cmpk_gt_u32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xb5]
-
-s_cmpk_ge_u32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb6]
-
-s_cmpk_ge_u32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb6]
-
-s_cmpk_ge_u32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb6]
-
-s_cmpk_ge_u32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb6]
-
-s_cmpk_ge_u32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb6]
-
-s_cmpk_ge_u32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb6]
-
-s_cmpk_ge_u32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb6]
-
-s_cmpk_ge_u32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb6]
-
-s_cmpk_lt_u32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xb6]
-
-s_cmpk_lt_u32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xb6]
-
-s_cmpk_lt_u32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xb6]
-
-s_cmpk_lt_u32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xb6]
-
-s_cmpk_lt_u32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xb6]
-
-s_cmpk_lt_u32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xb6]
-
-s_cmpk_lt_u32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xb6]
-
-s_cmpk_lt_u32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xb6]
-
-s_cmpk_le_u32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb7]
-
-s_cmpk_le_u32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb7]
-
-s_cmpk_le_u32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb7]
-
-s_cmpk_le_u32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb7]
-
-s_cmpk_le_u32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb7]
-
-s_cmpk_le_u32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb7]
-
-s_cmpk_le_u32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb7]
-
-s_cmpk_le_u32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb7]
-
-s_addk_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xb7]
-
-s_addk_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xb7]
-
-s_addk_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xb7]
-
-s_addk_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xb7]
-
-s_addk_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xb7]
-
-s_addk_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xb7]
-
-s_addk_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xb7]
-
-s_addk_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xb7]
-
-s_mulk_i32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb8]
-
-s_mulk_i32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb8]
-
-s_mulk_i32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb8]
-
-s_mulk_i32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb8]
-
-s_mulk_i32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb8]
-
-s_mulk_i32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb8]
-
-s_mulk_i32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb8]
-
-s_mulk_i32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb8]
-
-s_getreg_b32 s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xb9]
-
-s_getreg_b32 s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xb9]
-
-s_getreg_b32 s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xb9]
-
-s_getreg_b32 exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xb9]
-
-s_getreg_b32 exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xb9]
-
-s_getreg_b32 vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xb9]
-
-s_getreg_b32 vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xb9]
-
-s_getreg_b32 m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xb9]
-
-s_setreg_b32 0x1234, s0
-// GFX10: encoding: [0x34,0x12,0x80,0xb9]
-
-s_setreg_b32 0xc1d1, s0
-// GFX10: encoding: [0xd1,0xc1,0x80,0xb9]
-
-s_setreg_b32 0x1234, s105
-// GFX10: encoding: [0x34,0x12,0xe9,0xb9]
-
-s_setreg_b32 0x1234, exec_lo
-// GFX10: encoding: [0x34,0x12,0xfe,0xb9]
-
-s_setreg_b32 0x1234, exec_hi
-// GFX10: encoding: [0x34,0x12,0xff,0xb9]
-
-s_setreg_b32 0x1234, vcc_lo
-// GFX10: encoding: [0x34,0x12,0xea,0xb9]
-
-s_setreg_b32 0x1234, vcc_hi
-// GFX10: encoding: [0x34,0x12,0xeb,0xb9]
-
-s_setreg_b32 0x1234, m0
-// GFX10: encoding: [0x34,0x12,0xfc,0xb9]
-
-s_setreg_imm32_b32 0x1234, 0x11213141
-// GFX10: encoding: [0x34,0x12,0x80,0xba,0x41,0x31,0x21,0x11]
-
-s_setreg_imm32_b32 0xc1d1, 0x11213141
-// GFX10: encoding: [0xd1,0xc1,0x80,0xba,0x41,0x31,0x21,0x11]
-
-s_setreg_imm32_b32 0x1234, 0xa1b1c1d1
-// GFX10: encoding: [0x34,0x12,0x80,0xba,0xd1,0xc1,0xb1,0xa1]
-
-s_setreg_imm32_b32 0xc1d1, 0xa1b1c1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xba,0xd1,0xc1,0xb1,0xa1]
-
-s_call_b64 s[0:1], 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xbb]
-
-s_call_b64 s[0:1], 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xbb]
-
-s_call_b64 s[104:105], 0x1234
-// GFX10: encoding: [0x34,0x12,0x68,0xbb]
-
-s_call_b64 exec, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xbb]
-
-s_call_b64 vcc, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xbb]
-
-s_waitcnt_vscnt s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xbb]
-
-s_waitcnt_vscnt s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xbb]
-
-s_waitcnt_vscnt s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xbb]
-
-s_waitcnt_vscnt exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xbb]
-
-s_waitcnt_vscnt exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xbb]
-
-s_waitcnt_vscnt vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xbb]
-
-s_waitcnt_vscnt vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xbb]
-
-s_waitcnt_vscnt m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xbb]
-
-s_waitcnt_vmcnt s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xbc]
-
-s_waitcnt_vmcnt s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xbc]
-
-s_waitcnt_vmcnt s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xbc]
-
-s_waitcnt_vmcnt exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xbc]
-
-s_waitcnt_vmcnt exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xbc]
-
-s_waitcnt_vmcnt vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xbc]
-
-s_waitcnt_vmcnt vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xbc]
-
-s_waitcnt_vmcnt m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xbc]
-
-s_waitcnt_expcnt s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xbc]
-
-s_waitcnt_expcnt s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xbc]
-
-s_waitcnt_expcnt s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xbc]
-
-s_waitcnt_expcnt exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xbc]
-
-s_waitcnt_expcnt exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xbc]
-
-s_waitcnt_expcnt vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xbc]
-
-s_waitcnt_expcnt vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xbc]
-
-s_waitcnt_expcnt m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xbc]
-
-s_waitcnt_lgkmcnt s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xbd]
-
-s_waitcnt_lgkmcnt s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xbd]
-
-s_waitcnt_lgkmcnt s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xbd]
-
-s_waitcnt_lgkmcnt exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xbd]
-
-s_waitcnt_lgkmcnt exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xbd]
-
-s_waitcnt_lgkmcnt vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xbd]
-
-s_waitcnt_lgkmcnt vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xbd]
-
-s_waitcnt_lgkmcnt m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xbd]
-
-s_waitcnt_depctr 0xfffe
-// GFX10: encoding: [0xfe,0xff,0xa3,0xbf]
-
-s_waitcnt_depctr 0
-// GFX10: encoding: [0x00,0x00,0xa3,0xbf]
-
-s_wait_idle
-// GFX10: encoding: [0x00,0x00,0xa2,0xbf]
-
-s_subvector_loop_begin s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xbd]
-
-s_subvector_loop_begin s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xbd]
-
-s_subvector_loop_begin s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0xe9,0xbd]
-
-s_subvector_loop_begin exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfe,0xbd]
-
-s_subvector_loop_begin exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xff,0xbd]
-
-s_subvector_loop_begin vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0xea,0xbd]
-
-s_subvector_loop_begin vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0xeb,0xbd]
-
-s_subvector_loop_begin m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0xfc,0xbd]
-
-s_subvector_loop_end s0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x00,0xbe]
-
-s_subvector_loop_end s0, 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x00,0xbe]
-
-s_subvector_loop_end s105, 0x1234
-// GFX10: encoding: [0x34,0x12,0x69,0xbe]
-
-s_subvector_loop_end exec_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7e,0xbe]
-
-s_subvector_loop_end exec_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7f,0xbe]
-
-s_subvector_loop_end vcc_lo, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6a,0xbe]
-
-s_subvector_loop_end vcc_hi, 0x1234
-// GFX10: encoding: [0x34,0x12,0x6b,0xbe]
-
-s_subvector_loop_end m0, 0x1234
-// GFX10: encoding: [0x34,0x12,0x7c,0xbe]
-
-//===----------------------------------------------------------------------===//
-// ENC_SOPP.
-//===----------------------------------------------------------------------===//
-
-s_nop 0x0
-// GFX10: encoding: [0x00,0x00,0x80,0xbf]
-
-s_nop 0x1234
-// GFX10: encoding: [0x34,0x12,0x80,0xbf]
-
-s_nop 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x80,0xbf]
-
-s_endpgm
-// GFX10: encoding: [0x00,0x00,0x81,0xbf]
-
-s_branch 0x0
-// GFX10: encoding: [0x00,0x00,0x82,0xbf]
-
-s_branch 0x1234
-// GFX10: encoding: [0x34,0x12,0x82,0xbf]
-
-s_branch 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x82,0xbf]
-
-s_wakeup
-// GFX10: encoding: [0x00,0x00,0x83,0xbf]
-
-s_cbranch_scc0 0x0
-// GFX10: encoding: [0x00,0x00,0x84,0xbf]
-
-s_cbranch_scc0 0x1234
-// GFX10: encoding: [0x34,0x12,0x84,0xbf]
-
-s_cbranch_scc0 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x84,0xbf]
-
-s_cbranch_scc1 0x0
-// GFX10: encoding: [0x00,0x00,0x85,0xbf]
-
-s_cbranch_scc1 0x1234
-// GFX10: encoding: [0x34,0x12,0x85,0xbf]
-
-s_cbranch_scc1 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x85,0xbf]
-
-s_cbranch_vccz 0x0
-// GFX10: encoding: [0x00,0x00,0x86,0xbf]
-
-s_cbranch_vccz 0x1234
-// GFX10: encoding: [0x34,0x12,0x86,0xbf]
-
-s_cbranch_vccz 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x86,0xbf]
-
-s_cbranch_vccnz 0x0
-// GFX10: encoding: [0x00,0x00,0x87,0xbf]
-
-s_cbranch_vccnz 0x1234
-// GFX10: encoding: [0x34,0x12,0x87,0xbf]
-
-s_cbranch_vccnz 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x87,0xbf]
-
-s_cbranch_execz 0x0
-// GFX10: encoding: [0x00,0x00,0x88,0xbf]
-
-s_cbranch_execz 0x1234
-// GFX10: encoding: [0x34,0x12,0x88,0xbf]
-
-s_cbranch_execz 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x88,0xbf]
-
-s_cbranch_execnz 0x0
-// GFX10: encoding: [0x00,0x00,0x89,0xbf]
-
-s_cbranch_execnz 0x1234
-// GFX10: encoding: [0x34,0x12,0x89,0xbf]
-
-s_cbranch_execnz 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x89,0xbf]
-
-s_barrier
-// GFX10: encoding: [0x00,0x00,0x8a,0xbf]
-
-s_setkill 0x0
-// GFX10: encoding: [0x00,0x00,0x8b,0xbf]
-
-s_setkill 0x1234
-// GFX10: encoding: [0x34,0x12,0x8b,0xbf]
-
-s_setkill 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x8b,0xbf]
-
-s_waitcnt 0x0
-// GFX10: encoding: [0x00,0x00,0x8c,0xbf]
-
-s_waitcnt 0x1234
-// GFX10: encoding: [0x34,0x12,0x8c,0xbf]
-
-s_waitcnt 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x8c,0xbf]
-
-s_sethalt 0x0
-// GFX10: encoding: [0x00,0x00,0x8d,0xbf]
-
-s_sethalt 0x1234
-// GFX10: encoding: [0x34,0x12,0x8d,0xbf]
-
-s_sethalt 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x8d,0xbf]
-
-s_sleep 0x0
-// GFX10: encoding: [0x00,0x00,0x8e,0xbf]
-
-s_sleep 0x1234
-// GFX10: encoding: [0x34,0x12,0x8e,0xbf]
-
-s_sleep 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x8e,0xbf]
-
-s_setprio 0x0
-// GFX10: encoding: [0x00,0x00,0x8f,0xbf]
-
-s_setprio 0x1234
-// GFX10: encoding: [0x34,0x12,0x8f,0xbf]
-
-s_setprio 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x8f,0xbf]
-
-s_sendmsg 0x0
-// GFX10: encoding: [0x00,0x00,0x90,0xbf]
-
-s_sendmsg 0x1234
-// GFX10: encoding: [0x34,0x12,0x90,0xbf]
-
-s_sendmsg 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x90,0xbf]
-
-s_sendmsghalt 0x0
-// GFX10: encoding: [0x00,0x00,0x91,0xbf]
-
-s_sendmsghalt 0x1234
-// GFX10: encoding: [0x34,0x12,0x91,0xbf]
-
-s_sendmsghalt 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x91,0xbf]
-
-s_trap 0x0
-// GFX10: encoding: [0x00,0x00,0x92,0xbf]
-
-s_trap 0x1234
-// GFX10: encoding: [0x34,0x12,0x92,0xbf]
-
-s_trap 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x92,0xbf]
-
-s_icache_inv
-// GFX10: encoding: [0x00,0x00,0x93,0xbf]
-
-s_incperflevel 0x0
-// GFX10: encoding: [0x00,0x00,0x94,0xbf]
-
-s_incperflevel 0x1234
-// GFX10: encoding: [0x34,0x12,0x94,0xbf]
-
-s_incperflevel 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x94,0xbf]
-
-s_decperflevel 0x0
-// GFX10: encoding: [0x00,0x00,0x95,0xbf]
-
-s_decperflevel 0x1234
-// GFX10: encoding: [0x34,0x12,0x95,0xbf]
-
-s_decperflevel 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x95,0xbf]
-
-s_ttracedata
-// GFX10: encoding: [0x00,0x00,0x96,0xbf]
-
-s_cbranch_cdbgsys 0x0
-// GFX10: encoding: [0x00,0x00,0x97,0xbf]
-
-s_cbranch_cdbgsys 0x1234
-// GFX10: encoding: [0x34,0x12,0x97,0xbf]
-
-s_cbranch_cdbgsys 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x97,0xbf]
-
-s_cbranch_cdbguser 0x0
-// GFX10: encoding: [0x00,0x00,0x98,0xbf]
-
-s_cbranch_cdbguser 0x1234
-// GFX10: encoding: [0x34,0x12,0x98,0xbf]
-
-s_cbranch_cdbguser 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x98,0xbf]
-
-s_cbranch_cdbgsys_or_user 0x0
-// GFX10: encoding: [0x00,0x00,0x99,0xbf]
-
-s_cbranch_cdbgsys_or_user 0x1234
-// GFX10: encoding: [0x34,0x12,0x99,0xbf]
-
-s_cbranch_cdbgsys_or_user 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x99,0xbf]
-
-s_cbranch_cdbgsys_and_user 0x0
-// GFX10: encoding: [0x00,0x00,0x9a,0xbf]
-
-s_cbranch_cdbgsys_and_user 0x1234
-// GFX10: encoding: [0x34,0x12,0x9a,0xbf]
-
-s_cbranch_cdbgsys_and_user 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0x9a,0xbf]
-
-s_endpgm_saved
-// GFX10: encoding: [0x00,0x00,0x9b,0xbf]
-
-s_endpgm_ordered_ps_done
-// GFX10: encoding: [0x00,0x00,0x9e,0xbf]
-
-s_code_end
-// GFX10: encoding: [0x00,0x00,0x9f,0xbf]
-
-s_inst_prefetch 0x0
-// GFX10: encoding: [0x00,0x00,0xa0,0xbf]
-
-s_inst_prefetch 0x1234
-// GFX10: encoding: [0x34,0x12,0xa0,0xbf]
-
-s_inst_prefetch 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0xa0,0xbf]
-
-s_clause 0x0
-// GFX10: encoding: [0x00,0x00,0xa1,0xbf]
-
-s_clause 0x1234
-// GFX10: encoding: [0x34,0x12,0xa1,0xbf]
-
-s_clause 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0xa1,0xbf]
-
-s_round_mode 0x0
-// GFX10: encoding: [0x00,0x00,0xa4,0xbf]
-
-s_round_mode 0x1234
-// GFX10: encoding: [0x34,0x12,0xa4,0xbf]
-
-s_round_mode 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0xa4,0xbf]
-
-s_denorm_mode 0x0
-// GFX10: encoding: [0x00,0x00,0xa5,0xbf]
-
-s_denorm_mode 0x1234
-// GFX10: encoding: [0x34,0x12,0xa5,0xbf]
-
-s_denorm_mode 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0xa5,0xbf]
-
-s_ttracedata_imm 0x0
-// GFX10: encoding: [0x00,0x00,0xa8,0xbf]
-
-s_ttracedata_imm 0x1234
-// GFX10: encoding: [0x34,0x12,0xa8,0xbf]
-
-s_ttracedata_imm 0xc1d1
-// GFX10: encoding: [0xd1,0xc1,0xa8,0xbf]
-
-//===----------------------------------------------------------------------===//
-// ENC_VOP1.
-//===----------------------------------------------------------------------===//
-
-v_nop_e32
-// GFX10: encoding: [0x00,0x00,0x00,0x7e]
-
-v_nop_e64
-// GFX10: encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
-
-v_mov_b32_e32 v5, v1
-// GFX10: encoding: [0x01,0x03,0x0a,0x7e]
-
-v_mov_b32_e32 v255, v1
-// GFX10: encoding: [0x01,0x03,0xfe,0x7f]
-
-v_mov_b32_e32 v5, v255
-// GFX10: encoding: [0xff,0x03,0x0a,0x7e]
-
-v_mov_b32_e32 v5, s1
-// GFX10: encoding: [0x01,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, s103
-// GFX10: encoding: [0x67,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, ttmp11
-// GFX10: encoding: [0x77,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, m0
-// GFX10: encoding: [0x7c,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, 0
-// GFX10: encoding: [0x80,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, -1
-// GFX10: encoding: [0xc1,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0x02,0x0a,0x7e]
-
-v_mov_b32_e32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x02,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_mov_b32_e32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x02,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_mov_b32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x01,0x01,0x00,0x00]
-
-v_mov_b32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x81,0xd5,0x01,0x01,0x00,0x00]
-
-v_mov_b32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0xff,0x01,0x00,0x00]
-
-v_mov_b32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x01,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x65,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x6a,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x6b,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x7c,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x7e,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x7f,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x80,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0xc1,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0xf0,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x81,0xd5,0xf7,0x00,0x00,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_mov_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_mov_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_mov_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_mov_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_mov_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_readfirstlane_b32 s5, v1
-// GFX10: encoding: [0x01,0x05,0x0a,0x7e]
-
-v_readfirstlane_b32 s103, v1
-// GFX10: encoding: [0x01,0x05,0xce,0x7e]
-
-v_readfirstlane_b32 ttmp11, v1
-// GFX10: encoding: [0x01,0x05,0xee,0x7e]
-
-v_readfirstlane_b32 s5, v255
-// GFX10: encoding: [0xff,0x05,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, v[1:2]
-// GFX10: encoding: [0x01,0x07,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v255, v[1:2]
-// GFX10: encoding: [0x01,0x07,0xfe,0x7f]
-
-v_cvt_i32_f64_e32 v5, v[254:255]
-// GFX10: encoding: [0xfe,0x07,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, s[2:3]
-// GFX10: encoding: [0x02,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, s[4:5]
-// GFX10: encoding: [0x04,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, s[102:103]
-// GFX10: encoding: [0x66,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, vcc
-// GFX10: encoding: [0x6a,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, ttmp[10:11]
-// GFX10: encoding: [0x76,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, exec
-// GFX10: encoding: [0x7e,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, 0
-// GFX10: encoding: [0x80,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, -1
-// GFX10: encoding: [0xc1,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64_e32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x06,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_i32_f64_e32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x06,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_i32_f64_e64 v5, v[1:2]
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v255, v[1:2]
-// GFX10: encoding: [0xff,0x00,0x83,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, v[254:255]
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0xfe,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[2:3]
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x02,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[4:5]
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x04,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[100:101]
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x64,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, vcc
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, exec
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -v[1:2]
-// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_i32_f64_e64 v5, |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0x83,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0x83,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e32 v[5:6], v1
-// GFX10: encoding: [0x01,0x09,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[254:255], v1
-// GFX10: encoding: [0x01,0x09,0xfc,0x7f]
-
-v_cvt_f64_i32_e32 v[5:6], v255
-// GFX10: encoding: [0xff,0x09,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], s1
-// GFX10: encoding: [0x01,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], s103
-// GFX10: encoding: [0x67,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], vcc_lo
-// GFX10: encoding: [0x6a,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], vcc_hi
-// GFX10: encoding: [0x6b,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], ttmp11
-// GFX10: encoding: [0x77,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], m0
-// GFX10: encoding: [0x7c,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], exec_lo
-// GFX10: encoding: [0x7e,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], exec_hi
-// GFX10: encoding: [0x7f,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], 0
-// GFX10: encoding: [0x80,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], -1
-// GFX10: encoding: [0xc1,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32_e32 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x08,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_i32_e32 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x08,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_i32_e64 v[5:6], v1
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[254:255], v1
-// GFX10: encoding: [0xfe,0x00,0x84,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v255
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], s1
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], s101
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], vcc_lo
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], vcc_hi
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], m0
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], exec_lo
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], exec_hi
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v1 clamp
-// GFX10: encoding: [0x05,0x80,0x84,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_i32_e64 v[5:6], v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_i32_e64 v[5:6], v1 div:2
-// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_i32_e32 v5, v1
-// GFX10: encoding: [0x01,0x0b,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v255, v1
-// GFX10: encoding: [0x01,0x0b,0xfe,0x7f]
-
-v_cvt_f32_i32_e32 v5, v255
-// GFX10: encoding: [0xff,0x0b,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, s1
-// GFX10: encoding: [0x01,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, s103
-// GFX10: encoding: [0x67,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, ttmp11
-// GFX10: encoding: [0x77,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, m0
-// GFX10: encoding: [0x7c,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, 0
-// GFX10: encoding: [0x80,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, -1
-// GFX10: encoding: [0xc1,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32_e32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x0a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_i32_e32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x0a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_i32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x85,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x85,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_i32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_i32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_f32_u32_e32 v5, v1
-// GFX10: encoding: [0x01,0x0d,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v255, v1
-// GFX10: encoding: [0x01,0x0d,0xfe,0x7f]
-
-v_cvt_f32_u32_e32 v5, v255
-// GFX10: encoding: [0xff,0x0d,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, s1
-// GFX10: encoding: [0x01,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, s103
-// GFX10: encoding: [0x67,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, ttmp11
-// GFX10: encoding: [0x77,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, m0
-// GFX10: encoding: [0x7c,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, 0
-// GFX10: encoding: [0x80,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, -1
-// GFX10: encoding: [0xc1,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32_e32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x0c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_u32_e32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x0c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_u32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x86,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x86,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_u32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_u32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_u32_f32_e32 v5, v1
-// GFX10: encoding: [0x01,0x0f,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v255, v1
-// GFX10: encoding: [0x01,0x0f,0xfe,0x7f]
-
-v_cvt_u32_f32_e32 v5, v255
-// GFX10: encoding: [0xff,0x0f,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, s1
-// GFX10: encoding: [0x01,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, s103
-// GFX10: encoding: [0x67,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, ttmp11
-// GFX10: encoding: [0x77,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, m0
-// GFX10: encoding: [0x7c,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, 0
-// GFX10: encoding: [0x80,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, -1
-// GFX10: encoding: [0xc1,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32_e32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x0e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_u32_f32_e32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x0e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_u32_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x87,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_u32_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0x87,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x87,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_u32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_u32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_u32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_u32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_i32_f32_e32 v5, v1
-// GFX10: encoding: [0x01,0x11,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v255, v1
-// GFX10: encoding: [0x01,0x11,0xfe,0x7f]
-
-v_cvt_i32_f32_e32 v5, v255
-// GFX10: encoding: [0xff,0x11,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, s1
-// GFX10: encoding: [0x01,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, s103
-// GFX10: encoding: [0x67,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, ttmp11
-// GFX10: encoding: [0x77,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, m0
-// GFX10: encoding: [0x7c,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, 0
-// GFX10: encoding: [0x80,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, -1
-// GFX10: encoding: [0xc1,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32_e32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x10,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_i32_f32_e32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x10,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_i32_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x88,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_i32_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0x88,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x88,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_f16_f32 v5, v1
-// GFX10: encoding: [0x01,0x15,0x0a,0x7e]
-
-v_cvt_f16_f32 v255, v1
-// GFX10: encoding: [0x01,0x15,0xfe,0x7f]
-
-v_cvt_f16_f32 v5, v255
-// GFX10: encoding: [0xff,0x15,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, s1
-// GFX10: encoding: [0x01,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, s103
-// GFX10: encoding: [0x67,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, m0
-// GFX10: encoding: [0x7c,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0
-// GFX10: encoding: [0x80,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, -1
-// GFX10: encoding: [0xc1,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x14,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f16_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x14,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f16_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_f16_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0x8a,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x8a,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f16_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f16_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f16_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_f16_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_f32_f16 v5, v1
-// GFX10: encoding: [0x01,0x17,0x0a,0x7e]
-
-v_cvt_f32_f16 v255, v1
-// GFX10: encoding: [0x01,0x17,0xfe,0x7f]
-
-v_cvt_f32_f16 v5, v255
-// GFX10: encoding: [0xff,0x17,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, s1
-// GFX10: encoding: [0x01,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, s103
-// GFX10: encoding: [0x67,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, ttmp11
-// GFX10: encoding: [0x77,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, m0
-// GFX10: encoding: [0x7c,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, exec_lo
-// GFX10: encoding: [0x7e,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, exec_hi
-// GFX10: encoding: [0x7f,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, 0
-// GFX10: encoding: [0x80,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, -1
-// GFX10: encoding: [0xc1,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x8b,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_f32_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0x8b,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x8b,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_f16_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_f16_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_f32_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_rpi_i32_f32 v5, v1
-// GFX10: encoding: [0x01,0x19,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v255, v1
-// GFX10: encoding: [0x01,0x19,0xfe,0x7f]
-
-v_cvt_rpi_i32_f32 v5, v255
-// GFX10: encoding: [0xff,0x19,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, s1
-// GFX10: encoding: [0x01,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, s103
-// GFX10: encoding: [0x67,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, m0
-// GFX10: encoding: [0x7c,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0
-// GFX10: encoding: [0x80,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, -1
-// GFX10: encoding: [0xc1,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x18,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_rpi_i32_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x18,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_rpi_i32_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x8c,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_rpi_i32_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0x8c,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x8c,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_flr_i32_f32 v5, v1
-// GFX10: encoding: [0x01,0x1b,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v255, v1
-// GFX10: encoding: [0x01,0x1b,0xfe,0x7f]
-
-v_cvt_flr_i32_f32 v5, v255
-// GFX10: encoding: [0xff,0x1b,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, s1
-// GFX10: encoding: [0x01,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, s103
-// GFX10: encoding: [0x67,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, m0
-// GFX10: encoding: [0x7c,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0
-// GFX10: encoding: [0x80,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, -1
-// GFX10: encoding: [0xc1,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x1a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_flr_i32_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x1a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_flr_i32_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x8d,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_flr_i32_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0x8d,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x8d,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_off_f32_i4 v5, v1
-// GFX10: encoding: [0x01,0x1d,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v255, v1
-// GFX10: encoding: [0x01,0x1d,0xfe,0x7f]
-
-v_cvt_off_f32_i4 v5, v255
-// GFX10: encoding: [0xff,0x1d,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, s1
-// GFX10: encoding: [0x01,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, s103
-// GFX10: encoding: [0x67,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, ttmp11
-// GFX10: encoding: [0x77,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, m0
-// GFX10: encoding: [0x7c,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, exec_lo
-// GFX10: encoding: [0x7e,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, exec_hi
-// GFX10: encoding: [0x7f,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0
-// GFX10: encoding: [0x80,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, -1
-// GFX10: encoding: [0xc1,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0.5
-// GFX10: encoding: [0xf0,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, -4.0
-// GFX10: encoding: [0xf7,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0x4f
-// GFX10: encoding: [0xff,0x1c,0x0a,0x7e,0x4f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4 v5, 0x41
-// GFX10: encoding: [0xff,0x1c,0x0a,0x7e,0x41,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x8e,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x8e,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_off_f32_i4_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_off_f32_i4_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_f32_f64 v5, v[1:2]
-// GFX10: encoding: [0x01,0x1f,0x0a,0x7e]
-
-v_cvt_f32_f64 v255, v[1:2]
-// GFX10: encoding: [0x01,0x1f,0xfe,0x7f]
-
-v_cvt_f32_f64 v5, v[254:255]
-// GFX10: encoding: [0xfe,0x1f,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[2:3]
-// GFX10: encoding: [0x02,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[4:5]
-// GFX10: encoding: [0x04,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[102:103]
-// GFX10: encoding: [0x66,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, vcc
-// GFX10: encoding: [0x6a,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, ttmp[10:11]
-// GFX10: encoding: [0x76,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, exec
-// GFX10: encoding: [0x7e,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0
-// GFX10: encoding: [0x80,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, -1
-// GFX10: encoding: [0xc1,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0.5
-// GFX10: encoding: [0xf0,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, -4.0
-// GFX10: encoding: [0xf7,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x1e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_f64 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x1e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_f64_e64 v5, v[1:2]
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v255, v[1:2]
-// GFX10: encoding: [0xff,0x00,0x8f,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[254:255]
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0xfe,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[2:3]
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x02,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[4:5]
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x04,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[100:101]
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x64,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, vcc
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, exec
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -v[1:2]
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_f32_f64_e64 v5, |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0x8f,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0x8f,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_f64_e64 v5, v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_f64_e64 v5, v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f64_f32 v[5:6], v1
-// GFX10: encoding: [0x01,0x21,0x0a,0x7e]
-
-v_cvt_f64_f32 v[254:255], v1
-// GFX10: encoding: [0x01,0x21,0xfc,0x7f]
-
-v_cvt_f64_f32 v[5:6], v255
-// GFX10: encoding: [0xff,0x21,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], s1
-// GFX10: encoding: [0x01,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], s103
-// GFX10: encoding: [0x67,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], vcc_lo
-// GFX10: encoding: [0x6a,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], vcc_hi
-// GFX10: encoding: [0x6b,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], ttmp11
-// GFX10: encoding: [0x77,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], m0
-// GFX10: encoding: [0x7c,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], exec_lo
-// GFX10: encoding: [0x7e,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], exec_hi
-// GFX10: encoding: [0x7f,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0
-// GFX10: encoding: [0x80,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], -1
-// GFX10: encoding: [0xc1,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x20,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_f32 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x20,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_f32_e64 v[5:6], v1
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[254:255], v1
-// GFX10: encoding: [0xfe,0x00,0x90,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v255
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], s1
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], s101
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], vcc_lo
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], vcc_hi
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], m0
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], exec_lo
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], exec_hi
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -v1
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_f64_f32_e64 v[5:6], |v1|
-// GFX10: encoding: [0x05,0x01,0x90,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v1 clamp
-// GFX10: encoding: [0x05,0x80,0x90,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_f32_e64 v[5:6], v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_f32_e64 v[5:6], v1 div:2
-// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte0 v5, v1
-// GFX10: encoding: [0x01,0x23,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v255, v1
-// GFX10: encoding: [0x01,0x23,0xfe,0x7f]
-
-v_cvt_f32_ubyte0 v5, v255
-// GFX10: encoding: [0xff,0x23,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, s1
-// GFX10: encoding: [0x01,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, s103
-// GFX10: encoding: [0x67,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, ttmp11
-// GFX10: encoding: [0x77,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, m0
-// GFX10: encoding: [0x7c,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, exec_lo
-// GFX10: encoding: [0x7e,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, exec_hi
-// GFX10: encoding: [0x7f,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0
-// GFX10: encoding: [0x80,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, -1
-// GFX10: encoding: [0xc1,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0.5
-// GFX10: encoding: [0xf0,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, -4.0
-// GFX10: encoding: [0xf7,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x22,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte0 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x22,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte0_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x91,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x91,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte0_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte0_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_f32_ubyte1 v5, v1
-// GFX10: encoding: [0x01,0x25,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v255, v1
-// GFX10: encoding: [0x01,0x25,0xfe,0x7f]
-
-v_cvt_f32_ubyte1 v5, v255
-// GFX10: encoding: [0xff,0x25,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, s1
-// GFX10: encoding: [0x01,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, s103
-// GFX10: encoding: [0x67,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, ttmp11
-// GFX10: encoding: [0x77,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, m0
-// GFX10: encoding: [0x7c,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, exec_lo
-// GFX10: encoding: [0x7e,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, exec_hi
-// GFX10: encoding: [0x7f,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0
-// GFX10: encoding: [0x80,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, -1
-// GFX10: encoding: [0xc1,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0.5
-// GFX10: encoding: [0xf0,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, -4.0
-// GFX10: encoding: [0xf7,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x24,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte1 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x24,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte1_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x92,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x92,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte1_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte1_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_f32_ubyte2 v5, v1
-// GFX10: encoding: [0x01,0x27,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v255, v1
-// GFX10: encoding: [0x01,0x27,0xfe,0x7f]
-
-v_cvt_f32_ubyte2 v5, v255
-// GFX10: encoding: [0xff,0x27,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, s1
-// GFX10: encoding: [0x01,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, s103
-// GFX10: encoding: [0x67,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, ttmp11
-// GFX10: encoding: [0x77,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, m0
-// GFX10: encoding: [0x7c,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, exec_lo
-// GFX10: encoding: [0x7e,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, exec_hi
-// GFX10: encoding: [0x7f,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0
-// GFX10: encoding: [0x80,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, -1
-// GFX10: encoding: [0xc1,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0.5
-// GFX10: encoding: [0xf0,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, -4.0
-// GFX10: encoding: [0xf7,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x26,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte2 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x26,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte2_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x93,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x93,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte2_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte2_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_f32_ubyte3 v5, v1
-// GFX10: encoding: [0x01,0x29,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v255, v1
-// GFX10: encoding: [0x01,0x29,0xfe,0x7f]
-
-v_cvt_f32_ubyte3 v5, v255
-// GFX10: encoding: [0xff,0x29,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, s1
-// GFX10: encoding: [0x01,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, s103
-// GFX10: encoding: [0x67,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, ttmp11
-// GFX10: encoding: [0x77,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, m0
-// GFX10: encoding: [0x7c,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, exec_lo
-// GFX10: encoding: [0x7e,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, exec_hi
-// GFX10: encoding: [0x7f,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0
-// GFX10: encoding: [0x80,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, -1
-// GFX10: encoding: [0xc1,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0.5
-// GFX10: encoding: [0xf0,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, -4.0
-// GFX10: encoding: [0xf7,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x28,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte3 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x28,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte3_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0x94,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0x94,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte3_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte3_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_u32_f64 v5, v[1:2]
-// GFX10: encoding: [0x01,0x2b,0x0a,0x7e]
-
-v_cvt_u32_f64 v255, v[1:2]
-// GFX10: encoding: [0x01,0x2b,0xfe,0x7f]
-
-v_cvt_u32_f64 v5, v[254:255]
-// GFX10: encoding: [0xfe,0x2b,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[2:3]
-// GFX10: encoding: [0x02,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[4:5]
-// GFX10: encoding: [0x04,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[102:103]
-// GFX10: encoding: [0x66,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, vcc
-// GFX10: encoding: [0x6a,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, ttmp[10:11]
-// GFX10: encoding: [0x76,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, exec
-// GFX10: encoding: [0x7e,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0
-// GFX10: encoding: [0x80,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, -1
-// GFX10: encoding: [0xc1,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0.5
-// GFX10: encoding: [0xf0,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, -4.0
-// GFX10: encoding: [0xf7,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x2a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_u32_f64 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x2a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_u32_f64_e64 v5, v[1:2]
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v255, v[1:2]
-// GFX10: encoding: [0xff,0x00,0x95,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, v[254:255]
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0xfe,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[2:3]
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x02,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[4:5]
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x04,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[100:101]
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x64,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, vcc
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, exec
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -v[1:2]
-// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_u32_f64_e64 v5, |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0x95,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0x95,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32 v[5:6], v1
-// GFX10: encoding: [0x01,0x2d,0x0a,0x7e]
-
-v_cvt_f64_u32 v[254:255], v1
-// GFX10: encoding: [0x01,0x2d,0xfc,0x7f]
-
-v_cvt_f64_u32 v[5:6], v255
-// GFX10: encoding: [0xff,0x2d,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], s1
-// GFX10: encoding: [0x01,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], s103
-// GFX10: encoding: [0x67,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], vcc_lo
-// GFX10: encoding: [0x6a,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], vcc_hi
-// GFX10: encoding: [0x6b,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], ttmp11
-// GFX10: encoding: [0x77,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], m0
-// GFX10: encoding: [0x7c,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], exec_lo
-// GFX10: encoding: [0x7e,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], exec_hi
-// GFX10: encoding: [0x7f,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0
-// GFX10: encoding: [0x80,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], -1
-// GFX10: encoding: [0xc1,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x2c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_u32 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x2c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_u32_e64 v[5:6], v1
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[254:255], v1
-// GFX10: encoding: [0xfe,0x00,0x96,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v255
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], s1
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], s101
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], vcc_lo
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], vcc_hi
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], m0
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], exec_lo
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], exec_hi
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v1 clamp
-// GFX10: encoding: [0x05,0x80,0x96,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v1 mul:2
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_u32_e64 v[5:6], v1 mul:4
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_u32_e64 v[5:6], v1 div:2
-// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x18]
-
-v_trunc_f64 v[5:6], v[1:2]
-// GFX10: encoding: [0x01,0x2f,0x0a,0x7e]
-
-v_trunc_f64 v[254:255], v[1:2]
-// GFX10: encoding: [0x01,0x2f,0xfc,0x7f]
-
-v_trunc_f64 v[5:6], v[254:255]
-// GFX10: encoding: [0xfe,0x2f,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[2:3]
-// GFX10: encoding: [0x02,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[4:5]
-// GFX10: encoding: [0x04,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[102:103]
-// GFX10: encoding: [0x66,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], vcc
-// GFX10: encoding: [0x6a,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], ttmp[10:11]
-// GFX10: encoding: [0x76,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], exec
-// GFX10: encoding: [0x7e,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0
-// GFX10: encoding: [0x80,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], -1
-// GFX10: encoding: [0xc1,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x2e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_trunc_f64 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x2e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_trunc_f64_e64 v[5:6], v[1:2]
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[254:255], v[1:2]
-// GFX10: encoding: [0xfe,0x00,0x97,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0xfe,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[2:3]
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x02,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[4:5]
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x04,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[100:101]
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x64,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], vcc
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x6a,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], exec
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x7e,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x80,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0xc1,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0xf0,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0xf7,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -v[1:2]
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x20]
-
-v_trunc_f64_e64 v[5:6], |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0x97,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0x97,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x08]
-
-v_trunc_f64_e64 v[5:6], v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x10]
-
-v_trunc_f64_e64 v[5:6], v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x18]
-
-v_ceil_f64 v[5:6], v[1:2]
-// GFX10: encoding: [0x01,0x31,0x0a,0x7e]
-
-v_ceil_f64 v[254:255], v[1:2]
-// GFX10: encoding: [0x01,0x31,0xfc,0x7f]
-
-v_ceil_f64 v[5:6], v[254:255]
-// GFX10: encoding: [0xfe,0x31,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[2:3]
-// GFX10: encoding: [0x02,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[4:5]
-// GFX10: encoding: [0x04,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[102:103]
-// GFX10: encoding: [0x66,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], vcc
-// GFX10: encoding: [0x6a,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], ttmp[10:11]
-// GFX10: encoding: [0x76,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], exec
-// GFX10: encoding: [0x7e,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0
-// GFX10: encoding: [0x80,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], -1
-// GFX10: encoding: [0xc1,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x30,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ceil_f64 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x30,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ceil_f64_e64 v[5:6], v[1:2]
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[254:255], v[1:2]
-// GFX10: encoding: [0xfe,0x00,0x98,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0xfe,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[2:3]
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x02,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[4:5]
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x04,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[100:101]
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x64,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], vcc
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x6a,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], exec
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x7e,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x80,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0xc1,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0xf0,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0xf7,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -v[1:2]
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x20]
-
-v_ceil_f64_e64 v[5:6], |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0x98,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0x98,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x08]
-
-v_ceil_f64_e64 v[5:6], v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x10]
-
-v_ceil_f64_e64 v[5:6], v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x18]
-
-v_rndne_f64 v[5:6], v[1:2]
-// GFX10: encoding: [0x01,0x33,0x0a,0x7e]
-
-v_rndne_f64 v[254:255], v[1:2]
-// GFX10: encoding: [0x01,0x33,0xfc,0x7f]
-
-v_rndne_f64 v[5:6], v[254:255]
-// GFX10: encoding: [0xfe,0x33,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[2:3]
-// GFX10: encoding: [0x02,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[4:5]
-// GFX10: encoding: [0x04,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[102:103]
-// GFX10: encoding: [0x66,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], vcc
-// GFX10: encoding: [0x6a,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], ttmp[10:11]
-// GFX10: encoding: [0x76,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], exec
-// GFX10: encoding: [0x7e,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0
-// GFX10: encoding: [0x80,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], -1
-// GFX10: encoding: [0xc1,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x32,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rndne_f64 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x32,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rndne_f64_e64 v[5:6], v[1:2]
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[254:255], v[1:2]
-// GFX10: encoding: [0xfe,0x00,0x99,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0xfe,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[2:3]
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x02,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[4:5]
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x04,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[100:101]
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x64,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], vcc
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], exec
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x80,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -v[1:2]
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x20]
-
-v_rndne_f64_e64 v[5:6], v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0x99,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x08]
-
-v_rndne_f64_e64 v[5:6], v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x10]
-
-v_rndne_f64_e64 v[5:6], v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x18]
-
-v_floor_f64 v[5:6], v[1:2]
-// GFX10: encoding: [0x01,0x35,0x0a,0x7e]
-
-v_floor_f64 v[254:255], v[1:2]
-// GFX10: encoding: [0x01,0x35,0xfc,0x7f]
-
-v_floor_f64 v[5:6], v[254:255]
-// GFX10: encoding: [0xfe,0x35,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[2:3]
-// GFX10: encoding: [0x02,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[4:5]
-// GFX10: encoding: [0x04,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[102:103]
-// GFX10: encoding: [0x66,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], vcc
-// GFX10: encoding: [0x6a,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], ttmp[10:11]
-// GFX10: encoding: [0x76,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], exec
-// GFX10: encoding: [0x7e,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0
-// GFX10: encoding: [0x80,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], -1
-// GFX10: encoding: [0xc1,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x34,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_floor_f64 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x34,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_floor_f64_e64 v[5:6], v[1:2]
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[254:255], v[1:2]
-// GFX10: encoding: [0xfe,0x00,0x9a,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0xfe,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[2:3]
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x02,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[4:5]
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x04,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[100:101]
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x64,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], vcc
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x6a,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], exec
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x7e,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x80,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0xc1,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0xf0,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0xf7,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -v[1:2]
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x20]
-
-v_floor_f64_e64 v[5:6], v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0x9a,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x08]
-
-v_floor_f64_e64 v[5:6], v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x10]
-
-v_floor_f64_e64 v[5:6], v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x18]
-
-v_pipeflush
-// GFX10: encoding: [0x00,0x36,0x00,0x7e]
-
-v_pipeflush_e64
-// GFX10: encoding: [0x00,0x00,0x9b,0xd5,0x00,0x00,0x00,0x00]
-
-v_fract_f32 v5, v1
-// GFX10: encoding: [0x01,0x41,0x0a,0x7e]
-
-v_fract_f32 v255, v1
-// GFX10: encoding: [0x01,0x41,0xfe,0x7f]
-
-v_fract_f32 v5, v255
-// GFX10: encoding: [0xff,0x41,0x0a,0x7e]
-
-v_fract_f32 v5, s1
-// GFX10: encoding: [0x01,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, s103
-// GFX10: encoding: [0x67,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, m0
-// GFX10: encoding: [0x7c,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, 0
-// GFX10: encoding: [0x80,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, -1
-// GFX10: encoding: [0xc1,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x40,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_fract_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x40,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_fract_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xa0,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0xff,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x65,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x6a,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x6b,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x7c,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x7e,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x7f,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x80,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0xc1,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0xf0,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0xf7,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x20]
-
-v_fract_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xa0,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x08]
-
-v_fract_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x10]
-
-v_fract_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x18]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_fract_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_fract_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_fract_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_fract_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_fract_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_fract_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_trunc_f32 v5, v1
-// GFX10: encoding: [0x01,0x43,0x0a,0x7e]
-
-v_trunc_f32 v255, v1
-// GFX10: encoding: [0x01,0x43,0xfe,0x7f]
-
-v_trunc_f32 v5, v255
-// GFX10: encoding: [0xff,0x43,0x0a,0x7e]
-
-v_trunc_f32 v5, s1
-// GFX10: encoding: [0x01,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, s103
-// GFX10: encoding: [0x67,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, m0
-// GFX10: encoding: [0x7c,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, 0
-// GFX10: encoding: [0x80,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, -1
-// GFX10: encoding: [0xc1,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x42,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_trunc_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x42,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_trunc_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xa1,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0xff,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x65,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x6a,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x6b,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x7c,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x7e,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x7f,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x80,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0xc1,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0xf0,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0xf7,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x20]
-
-v_trunc_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xa1,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x08]
-
-v_trunc_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x10]
-
-v_trunc_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x18]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_trunc_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_trunc_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_trunc_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_trunc_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_trunc_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_trunc_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_ceil_f32 v5, v1
-// GFX10: encoding: [0x01,0x45,0x0a,0x7e]
-
-v_ceil_f32 v255, v1
-// GFX10: encoding: [0x01,0x45,0xfe,0x7f]
-
-v_ceil_f32 v5, v255
-// GFX10: encoding: [0xff,0x45,0x0a,0x7e]
-
-v_ceil_f32 v5, s1
-// GFX10: encoding: [0x01,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, s103
-// GFX10: encoding: [0x67,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, m0
-// GFX10: encoding: [0x7c,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, 0
-// GFX10: encoding: [0x80,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, -1
-// GFX10: encoding: [0xc1,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x44,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ceil_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x44,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ceil_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xa2,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0xff,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x65,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x6a,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x6b,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x7c,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x7e,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x7f,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x80,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0xc1,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0xf0,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0xf7,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x20]
-
-v_ceil_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xa2,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x08]
-
-v_ceil_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x10]
-
-v_ceil_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x18]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ceil_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_ceil_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ceil_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ceil_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ceil_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ceil_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_rndne_f32 v5, v1
-// GFX10: encoding: [0x01,0x47,0x0a,0x7e]
-
-v_rndne_f32 v255, v1
-// GFX10: encoding: [0x01,0x47,0xfe,0x7f]
-
-v_rndne_f32 v5, v255
-// GFX10: encoding: [0xff,0x47,0x0a,0x7e]
-
-v_rndne_f32 v5, s1
-// GFX10: encoding: [0x01,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, s103
-// GFX10: encoding: [0x67,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, m0
-// GFX10: encoding: [0x7c,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, 0
-// GFX10: encoding: [0x80,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, -1
-// GFX10: encoding: [0xc1,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x46,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rndne_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x46,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rndne_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xa3,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0xff,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x65,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x6b,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x7c,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x7f,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x80,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x20]
-
-v_rndne_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xa3,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x08]
-
-v_rndne_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x10]
-
-v_rndne_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x18]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rndne_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rndne_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rndne_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rndne_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rndne_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rndne_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_floor_f32 v5, v1
-// GFX10: encoding: [0x01,0x49,0x0a,0x7e]
-
-v_floor_f32 v255, v1
-// GFX10: encoding: [0x01,0x49,0xfe,0x7f]
-
-v_floor_f32 v5, v255
-// GFX10: encoding: [0xff,0x49,0x0a,0x7e]
-
-v_floor_f32 v5, s1
-// GFX10: encoding: [0x01,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, s103
-// GFX10: encoding: [0x67,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, m0
-// GFX10: encoding: [0x7c,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, 0
-// GFX10: encoding: [0x80,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, -1
-// GFX10: encoding: [0xc1,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x48,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_floor_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x48,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_floor_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xa4,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0xff,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x65,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x6a,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x6b,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x7c,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x7e,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x7f,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x80,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0xc1,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0xf0,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0xf7,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x20]
-
-v_floor_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xa4,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xa4,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x08]
-
-v_floor_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x10]
-
-v_floor_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x18]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_floor_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_floor_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_floor_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_floor_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_floor_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_floor_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_exp_f32 v5, v1
-// GFX10: encoding: [0x01,0x4b,0x0a,0x7e]
-
-v_exp_f32 v255, v1
-// GFX10: encoding: [0x01,0x4b,0xfe,0x7f]
-
-v_exp_f32 v5, v255
-// GFX10: encoding: [0xff,0x4b,0x0a,0x7e]
-
-v_exp_f32 v5, s1
-// GFX10: encoding: [0x01,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, s103
-// GFX10: encoding: [0x67,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, m0
-// GFX10: encoding: [0x7c,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, 0
-// GFX10: encoding: [0x80,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, -1
-// GFX10: encoding: [0xc1,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x4a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_exp_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x4a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_exp_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xa5,0xd5,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0xff,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x65,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x6a,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x6b,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x7c,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x7e,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x7f,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x80,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0xc1,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0xf0,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0xf7,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x20]
-
-v_exp_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xa5,0xd5,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xa5,0xd5,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x08]
-
-v_exp_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x10]
-
-v_exp_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x18]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_exp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_exp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_exp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_exp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_exp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_exp_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_log_f32 v5, v1
-// GFX10: encoding: [0x01,0x4f,0x0a,0x7e]
-
-v_log_f32 v255, v1
-// GFX10: encoding: [0x01,0x4f,0xfe,0x7f]
-
-v_log_f32 v5, v255
-// GFX10: encoding: [0xff,0x4f,0x0a,0x7e]
-
-v_log_f32 v5, s1
-// GFX10: encoding: [0x01,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, s103
-// GFX10: encoding: [0x67,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, m0
-// GFX10: encoding: [0x7c,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, 0
-// GFX10: encoding: [0x80,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, -1
-// GFX10: encoding: [0xc1,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x4e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_log_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x4e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_log_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xa7,0xd5,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0xff,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x65,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x6a,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x6b,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x7c,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x7e,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x7f,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x80,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0xc1,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0xf0,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0xf7,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x20]
-
-v_log_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xa7,0xd5,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xa7,0xd5,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x08]
-
-v_log_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x10]
-
-v_log_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x18]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_log_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_log_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_log_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_log_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_log_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_log_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_rcp_f32 v5, v1
-// GFX10: encoding: [0x01,0x55,0x0a,0x7e]
-
-v_rcp_f32 v255, v1
-// GFX10: encoding: [0x01,0x55,0xfe,0x7f]
-
-v_rcp_f32 v5, v255
-// GFX10: encoding: [0xff,0x55,0x0a,0x7e]
-
-v_rcp_f32 v5, s1
-// GFX10: encoding: [0x01,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, s103
-// GFX10: encoding: [0x67,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, m0
-// GFX10: encoding: [0x7c,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, 0
-// GFX10: encoding: [0x80,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, -1
-// GFX10: encoding: [0xc1,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x54,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x54,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xaa,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0xff,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x65,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x6b,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x7c,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x7f,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x80,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x20]
-
-v_rcp_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xaa,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xaa,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x08]
-
-v_rcp_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x10]
-
-v_rcp_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x18]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rcp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rcp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rcp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rcp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rcp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rcp_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_rcp_iflag_f32 v5, v1
-// GFX10: encoding: [0x01,0x57,0x0a,0x7e]
-
-v_rcp_iflag_f32 v255, v1
-// GFX10: encoding: [0x01,0x57,0xfe,0x7f]
-
-v_rcp_iflag_f32 v5, v255
-// GFX10: encoding: [0xff,0x57,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, s1
-// GFX10: encoding: [0x01,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, s103
-// GFX10: encoding: [0x67,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, m0
-// GFX10: encoding: [0x7c,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0
-// GFX10: encoding: [0x80,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, -1
-// GFX10: encoding: [0xc1,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x56,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_iflag_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x56,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_iflag_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xab,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0xff,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x65,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x6b,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x7c,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x7f,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x80,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x20]
-
-v_rcp_iflag_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xab,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xab,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x08]
-
-v_rcp_iflag_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x10]
-
-v_rcp_iflag_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x18]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rcp_iflag_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rcp_iflag_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_rsq_f32 v5, v1
-// GFX10: encoding: [0x01,0x5d,0x0a,0x7e]
-
-v_rsq_f32 v255, v1
-// GFX10: encoding: [0x01,0x5d,0xfe,0x7f]
-
-v_rsq_f32 v5, v255
-// GFX10: encoding: [0xff,0x5d,0x0a,0x7e]
-
-v_rsq_f32 v5, s1
-// GFX10: encoding: [0x01,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, s103
-// GFX10: encoding: [0x67,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, m0
-// GFX10: encoding: [0x7c,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, 0
-// GFX10: encoding: [0x80,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, -1
-// GFX10: encoding: [0xc1,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x5c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x5c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xae,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0xff,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x65,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x6b,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x7c,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x7f,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x80,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x20]
-
-v_rsq_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xae,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xae,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x08]
-
-v_rsq_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x10]
-
-v_rsq_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x18]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rsq_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rsq_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rsq_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rsq_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rsq_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rsq_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_rcp_f64 v[5:6], v[1:2]
-// GFX10: encoding: [0x01,0x5f,0x0a,0x7e]
-
-v_rcp_f64 v[254:255], v[1:2]
-// GFX10: encoding: [0x01,0x5f,0xfc,0x7f]
-
-v_rcp_f64 v[5:6], v[254:255]
-// GFX10: encoding: [0xfe,0x5f,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[2:3]
-// GFX10: encoding: [0x02,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[4:5]
-// GFX10: encoding: [0x04,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[102:103]
-// GFX10: encoding: [0x66,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], vcc
-// GFX10: encoding: [0x6a,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], ttmp[10:11]
-// GFX10: encoding: [0x76,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], exec
-// GFX10: encoding: [0x7e,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0
-// GFX10: encoding: [0x80,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], -1
-// GFX10: encoding: [0xc1,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x5e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_f64 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x5e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_f64_e64 v[5:6], v[1:2]
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[254:255], v[1:2]
-// GFX10: encoding: [0xfe,0x00,0xaf,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[254:255]
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0xfe,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[2:3]
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x02,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[4:5]
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x04,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[100:101]
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x64,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], vcc
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], exec
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x80,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -v[1:2]
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x20]
-
-v_rcp_f64_e64 v[5:6], |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0xaf,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0xaf,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x08]
-
-v_rcp_f64_e64 v[5:6], v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x10]
-
-v_rcp_f64_e64 v[5:6], v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x18]
-
-v_rsq_f64 v[5:6], v[1:2]
-// GFX10: encoding: [0x01,0x63,0x0a,0x7e]
-
-v_rsq_f64 v[254:255], v[1:2]
-// GFX10: encoding: [0x01,0x63,0xfc,0x7f]
-
-v_rsq_f64 v[5:6], v[254:255]
-// GFX10: encoding: [0xfe,0x63,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[2:3]
-// GFX10: encoding: [0x02,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[4:5]
-// GFX10: encoding: [0x04,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[102:103]
-// GFX10: encoding: [0x66,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], vcc
-// GFX10: encoding: [0x6a,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], ttmp[10:11]
-// GFX10: encoding: [0x76,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], exec
-// GFX10: encoding: [0x7e,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0
-// GFX10: encoding: [0x80,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], -1
-// GFX10: encoding: [0xc1,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x62,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_f64 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x62,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_f64_e64 v[5:6], v[1:2]
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[254:255], v[1:2]
-// GFX10: encoding: [0xfe,0x00,0xb1,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[254:255]
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0xfe,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[2:3]
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x02,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[4:5]
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x04,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[100:101]
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x64,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], vcc
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], exec
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x80,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -v[1:2]
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x20]
-
-v_rsq_f64_e64 v[5:6], |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0xb1,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0xb1,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x08]
-
-v_rsq_f64_e64 v[5:6], v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x10]
-
-v_rsq_f64_e64 v[5:6], v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x18]
-
-v_sqrt_f32 v5, v1
-// GFX10: encoding: [0x01,0x67,0x0a,0x7e]
-
-v_sqrt_f32 v255, v1
-// GFX10: encoding: [0x01,0x67,0xfe,0x7f]
-
-v_sqrt_f32 v5, v255
-// GFX10: encoding: [0xff,0x67,0x0a,0x7e]
-
-v_sqrt_f32 v5, s1
-// GFX10: encoding: [0x01,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, s103
-// GFX10: encoding: [0x67,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, m0
-// GFX10: encoding: [0x7c,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0
-// GFX10: encoding: [0x80,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, -1
-// GFX10: encoding: [0xc1,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x66,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sqrt_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x66,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sqrt_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xb3,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0xff,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x65,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x6b,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x7c,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x7f,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x80,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x20]
-
-v_sqrt_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xb3,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xb3,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x08]
-
-v_sqrt_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x10]
-
-v_sqrt_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x18]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sqrt_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sqrt_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_sqrt_f64 v[5:6], v[1:2]
-// GFX10: encoding: [0x01,0x69,0x0a,0x7e]
-
-v_sqrt_f64 v[254:255], v[1:2]
-// GFX10: encoding: [0x01,0x69,0xfc,0x7f]
-
-v_sqrt_f64 v[5:6], v[254:255]
-// GFX10: encoding: [0xfe,0x69,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[2:3]
-// GFX10: encoding: [0x02,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[4:5]
-// GFX10: encoding: [0x04,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[102:103]
-// GFX10: encoding: [0x66,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], vcc
-// GFX10: encoding: [0x6a,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], ttmp[10:11]
-// GFX10: encoding: [0x76,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], exec
-// GFX10: encoding: [0x7e,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0
-// GFX10: encoding: [0x80,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], -1
-// GFX10: encoding: [0xc1,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x68,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sqrt_f64 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x68,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sqrt_f64_e64 v[5:6], v[1:2]
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[254:255], v[1:2]
-// GFX10: encoding: [0xfe,0x00,0xb4,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[254:255]
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0xfe,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[2:3]
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x02,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[4:5]
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x04,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[100:101]
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x64,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], vcc
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], exec
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x80,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -v[1:2]
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x20]
-
-v_sqrt_f64_e64 v[5:6], |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0xb4,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0xb4,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x08]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x10]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x18]
-
-v_sin_f32 v5, v1
-// GFX10: encoding: [0x01,0x6b,0x0a,0x7e]
-
-v_sin_f32 v255, v1
-// GFX10: encoding: [0x01,0x6b,0xfe,0x7f]
-
-v_sin_f32 v5, v255
-// GFX10: encoding: [0xff,0x6b,0x0a,0x7e]
-
-v_sin_f32 v5, s1
-// GFX10: encoding: [0x01,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, s103
-// GFX10: encoding: [0x67,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, m0
-// GFX10: encoding: [0x7c,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, 0
-// GFX10: encoding: [0x80,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, -1
-// GFX10: encoding: [0xc1,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x6a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sin_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x6a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sin_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xb5,0xd5,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0xff,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x65,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x6a,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x6b,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x7c,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x7e,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x7f,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x80,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0xc1,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0xf0,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0xf7,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x20]
-
-v_sin_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xb5,0xd5,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xb5,0xd5,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x08]
-
-v_sin_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x10]
-
-v_sin_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x18]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sin_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sin_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sin_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sin_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sin_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sin_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cos_f32 v5, v1
-// GFX10: encoding: [0x01,0x6d,0x0a,0x7e]
-
-v_cos_f32 v255, v1
-// GFX10: encoding: [0x01,0x6d,0xfe,0x7f]
-
-v_cos_f32 v5, v255
-// GFX10: encoding: [0xff,0x6d,0x0a,0x7e]
-
-v_cos_f32 v5, s1
-// GFX10: encoding: [0x01,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, s103
-// GFX10: encoding: [0x67,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, m0
-// GFX10: encoding: [0x7c,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, 0
-// GFX10: encoding: [0x80,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, -1
-// GFX10: encoding: [0xc1,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x6c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cos_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x6c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cos_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xb6,0xd5,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0xff,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x65,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x80,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x20]
-
-v_cos_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xb6,0xd5,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xb6,0xd5,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x08]
-
-v_cos_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x10]
-
-v_cos_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x18]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cos_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cos_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cos_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cos_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cos_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cos_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_not_b32 v5, v1
-// GFX10: encoding: [0x01,0x6f,0x0a,0x7e]
-
-v_not_b32 v255, v1
-// GFX10: encoding: [0x01,0x6f,0xfe,0x7f]
-
-v_not_b32 v5, v255
-// GFX10: encoding: [0xff,0x6f,0x0a,0x7e]
-
-v_not_b32 v5, s1
-// GFX10: encoding: [0x01,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, s103
-// GFX10: encoding: [0x67,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, ttmp11
-// GFX10: encoding: [0x77,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, m0
-// GFX10: encoding: [0x7c,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, 0
-// GFX10: encoding: [0x80,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, -1
-// GFX10: encoding: [0xc1,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, 0.5
-// GFX10: encoding: [0xf0,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, -4.0
-// GFX10: encoding: [0xf7,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x6e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_not_b32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_not_b32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x01,0x01,0x00,0x00]
-
-v_not_b32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xb7,0xd5,0x01,0x01,0x00,0x00]
-
-v_not_b32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0xff,0x01,0x00,0x00]
-
-v_not_b32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x01,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x65,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x6a,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x6b,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x7c,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x7e,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x7f,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x80,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0xc1,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0xf0,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0xf7,0x00,0x00,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_not_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_not_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_not_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_not_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_not_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_bfrev_b32 v5, v1
-// GFX10: encoding: [0x01,0x71,0x0a,0x7e]
-
-v_bfrev_b32 v255, v1
-// GFX10: encoding: [0x01,0x71,0xfe,0x7f]
-
-v_bfrev_b32 v5, v255
-// GFX10: encoding: [0xff,0x71,0x0a,0x7e]
-
-v_bfrev_b32 v5, s1
-// GFX10: encoding: [0x01,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, s103
-// GFX10: encoding: [0x67,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, ttmp11
-// GFX10: encoding: [0x77,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, m0
-// GFX10: encoding: [0x7c,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0
-// GFX10: encoding: [0x80,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, -1
-// GFX10: encoding: [0xc1,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0.5
-// GFX10: encoding: [0xf0,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, -4.0
-// GFX10: encoding: [0xf7,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x70,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_bfrev_b32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x70,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_bfrev_b32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0xff,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x01,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x65,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x6a,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x6b,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x7c,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x7e,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x7f,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x80,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0xc1,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0xf0,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0xf7,0x00,0x00,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_bfrev_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_bfrev_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_bfrev_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_ffbh_u32 v5, v1
-// GFX10: encoding: [0x01,0x73,0x0a,0x7e]
-
-v_ffbh_u32 v255, v1
-// GFX10: encoding: [0x01,0x73,0xfe,0x7f]
-
-v_ffbh_u32 v5, v255
-// GFX10: encoding: [0xff,0x73,0x0a,0x7e]
-
-v_ffbh_u32 v5, s1
-// GFX10: encoding: [0x01,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, s103
-// GFX10: encoding: [0x67,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, ttmp11
-// GFX10: encoding: [0x77,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, m0
-// GFX10: encoding: [0x7c,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0
-// GFX10: encoding: [0x80,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, -1
-// GFX10: encoding: [0xc1,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0.5
-// GFX10: encoding: [0xf0,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, -4.0
-// GFX10: encoding: [0xf7,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x72,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbh_u32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x72,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbh_u32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x01,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xb9,0xd5,0x01,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0xff,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x01,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x65,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x6a,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x6b,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x7c,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x7e,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x7f,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x80,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0xc1,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0xf0,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0xf7,0x00,0x00,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ffbh_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ffbh_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ffbh_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_ffbl_b32 v5, v1
-// GFX10: encoding: [0x01,0x75,0x0a,0x7e]
-
-v_ffbl_b32 v255, v1
-// GFX10: encoding: [0x01,0x75,0xfe,0x7f]
-
-v_ffbl_b32 v5, v255
-// GFX10: encoding: [0xff,0x75,0x0a,0x7e]
-
-v_ffbl_b32 v5, s1
-// GFX10: encoding: [0x01,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, s103
-// GFX10: encoding: [0x67,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, ttmp11
-// GFX10: encoding: [0x77,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, m0
-// GFX10: encoding: [0x7c,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0
-// GFX10: encoding: [0x80,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, -1
-// GFX10: encoding: [0xc1,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0.5
-// GFX10: encoding: [0xf0,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, -4.0
-// GFX10: encoding: [0xf7,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x74,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbl_b32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x74,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbl_b32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x01,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xba,0xd5,0x01,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0xff,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x01,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x65,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x6a,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x6b,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x7c,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x7e,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x7f,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x80,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0xc1,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0xf0,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xba,0xd5,0xf7,0x00,0x00,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ffbl_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ffbl_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ffbl_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_ffbh_i32 v5, v1
-// GFX10: encoding: [0x01,0x77,0x0a,0x7e]
-
-v_ffbh_i32 v255, v1
-// GFX10: encoding: [0x01,0x77,0xfe,0x7f]
-
-v_ffbh_i32 v5, v255
-// GFX10: encoding: [0xff,0x77,0x0a,0x7e]
-
-v_ffbh_i32 v5, s1
-// GFX10: encoding: [0x01,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, s103
-// GFX10: encoding: [0x67,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, ttmp11
-// GFX10: encoding: [0x77,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, m0
-// GFX10: encoding: [0x7c,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0
-// GFX10: encoding: [0x80,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, -1
-// GFX10: encoding: [0xc1,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0.5
-// GFX10: encoding: [0xf0,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, -4.0
-// GFX10: encoding: [0xf7,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x76,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbh_i32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x76,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbh_i32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x01,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xbb,0xd5,0x01,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0xff,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x01,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x65,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x6a,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x6b,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x7c,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x7e,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x7f,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x80,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0xc1,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0xf0,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0xf7,0x00,0x00,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ffbh_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ffbh_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ffbh_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_frexp_exp_i32_f64 v5, v[1:2]
-// GFX10: encoding: [0x01,0x79,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v255, v[1:2]
-// GFX10: encoding: [0x01,0x79,0xfe,0x7f]
-
-v_frexp_exp_i32_f64 v5, v[254:255]
-// GFX10: encoding: [0xfe,0x79,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[2:3]
-// GFX10: encoding: [0x02,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[4:5]
-// GFX10: encoding: [0x04,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[102:103]
-// GFX10: encoding: [0x66,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, vcc
-// GFX10: encoding: [0x6a,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, ttmp[10:11]
-// GFX10: encoding: [0x76,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, exec
-// GFX10: encoding: [0x7e,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0
-// GFX10: encoding: [0x80,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, -1
-// GFX10: encoding: [0xc1,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0.5
-// GFX10: encoding: [0xf0,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, -4.0
-// GFX10: encoding: [0xf7,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x78,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_exp_i32_f64 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x78,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_exp_i32_f64_e64 v5, v[1:2]
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v255, v[1:2]
-// GFX10: encoding: [0xff,0x00,0xbc,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, v[254:255]
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0xfe,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[2:3]
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x02,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[4:5]
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x04,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[100:101]
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x64,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, vcc
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, exec
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -v[1:2]
-// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0xbc,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0xbc,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64 v[5:6], v[1:2]
-// GFX10: encoding: [0x01,0x7b,0x0a,0x7e]
-
-v_frexp_mant_f64 v[254:255], v[1:2]
-// GFX10: encoding: [0x01,0x7b,0xfc,0x7f]
-
-v_frexp_mant_f64 v[5:6], v[254:255]
-// GFX10: encoding: [0xfe,0x7b,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[2:3]
-// GFX10: encoding: [0x02,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[4:5]
-// GFX10: encoding: [0x04,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[102:103]
-// GFX10: encoding: [0x66,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], vcc
-// GFX10: encoding: [0x6a,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], ttmp[10:11]
-// GFX10: encoding: [0x76,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], exec
-// GFX10: encoding: [0x7e,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0
-// GFX10: encoding: [0x80,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], -1
-// GFX10: encoding: [0xc1,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x7a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_mant_f64 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x7a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2]
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[254:255], v[1:2]
-// GFX10: encoding: [0xfe,0x00,0xbd,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[254:255]
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0xfe,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[2:3]
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x02,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[4:5]
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x04,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[100:101]
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x64,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], vcc
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], exec
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -v[1:2]
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f64_e64 v[5:6], |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0xbd,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0xbd,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x08]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x10]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x18]
-
-v_fract_f64 v[5:6], v[1:2]
-// GFX10: encoding: [0x01,0x7d,0x0a,0x7e]
-
-v_fract_f64 v[254:255], v[1:2]
-// GFX10: encoding: [0x01,0x7d,0xfc,0x7f]
-
-v_fract_f64 v[5:6], v[254:255]
-// GFX10: encoding: [0xfe,0x7d,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[2:3]
-// GFX10: encoding: [0x02,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[4:5]
-// GFX10: encoding: [0x04,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[102:103]
-// GFX10: encoding: [0x66,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], vcc
-// GFX10: encoding: [0x6a,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], ttmp[10:11]
-// GFX10: encoding: [0x76,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], exec
-// GFX10: encoding: [0x7e,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0
-// GFX10: encoding: [0x80,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], -1
-// GFX10: encoding: [0xc1,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0.5
-// GFX10: encoding: [0xf0,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], -4.0
-// GFX10: encoding: [0xf7,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0xaf123456
-// GFX10: encoding: [0xff,0x7c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_fract_f64 v[5:6], 0x3f717273
-// GFX10: encoding: [0xff,0x7c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_fract_f64_e64 v[5:6], v[1:2]
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[254:255], v[1:2]
-// GFX10: encoding: [0xfe,0x00,0xbe,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[254:255]
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0xfe,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[2:3]
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x02,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[4:5]
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x04,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[100:101]
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x64,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], vcc
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x6a,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], exec
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x7e,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], 0
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x80,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -1
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0xc1,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], 0.5
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0xf0,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -4.0
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0xf7,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -v[1:2]
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x20]
-
-v_fract_f64_e64 v[5:6], |v[1:2]|
-// GFX10: encoding: [0x05,0x01,0xbe,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[1:2] clamp
-// GFX10: encoding: [0x05,0x80,0xbe,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[1:2] mul:2
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x08]
-
-v_fract_f64_e64 v[5:6], v[1:2] mul:4
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x10]
-
-v_fract_f64_e64 v[5:6], v[1:2] div:2
-// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x18]
-
-v_frexp_exp_i32_f32 v5, v1
-// GFX10: encoding: [0x01,0x7f,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v255, v1
-// GFX10: encoding: [0x01,0x7f,0xfe,0x7f]
-
-v_frexp_exp_i32_f32 v5, v255
-// GFX10: encoding: [0xff,0x7f,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, s1
-// GFX10: encoding: [0x01,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, s103
-// GFX10: encoding: [0x67,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, m0
-// GFX10: encoding: [0x7c,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0
-// GFX10: encoding: [0x80,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, -1
-// GFX10: encoding: [0xc1,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x7e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_exp_i32_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x7e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_exp_i32_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xbf,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0xff,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x01,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x65,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x6b,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x7c,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x7f,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i32_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xbf,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xbf,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_frexp_mant_f32 v5, v1
-// GFX10: encoding: [0x01,0x81,0x0a,0x7e]
-
-v_frexp_mant_f32 v255, v1
-// GFX10: encoding: [0x01,0x81,0xfe,0x7f]
-
-v_frexp_mant_f32 v5, v255
-// GFX10: encoding: [0xff,0x81,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, s1
-// GFX10: encoding: [0x01,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, s103
-// GFX10: encoding: [0x67,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, ttmp11
-// GFX10: encoding: [0x77,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, m0
-// GFX10: encoding: [0x7c,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, exec_lo
-// GFX10: encoding: [0x7e,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, exec_hi
-// GFX10: encoding: [0x7f,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0
-// GFX10: encoding: [0x80,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, -1
-// GFX10: encoding: [0xc1,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0.5
-// GFX10: encoding: [0xf0,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, -4.0
-// GFX10: encoding: [0xf7,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0xaf123456
-// GFX10: encoding: [0xff,0x80,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_mant_f32 v5, 0x3f717273
-// GFX10: encoding: [0xff,0x80,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_mant_f32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xc0,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0xff,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x65,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x6b,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x7c,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x7f,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f32_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xc0,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xc0,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v1 mul:2
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x08]
-
-v_frexp_mant_f32_e64 v5, v1 mul:4
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x10]
-
-v_frexp_mant_f32_e64 v5, v1 div:2
-// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x18]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_mant_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_mant_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_clrexcp_e32
-// GFX10: encoding: [0x00,0x82,0x00,0x7e]
-
-v_clrexcp_e64
-// GFX10: encoding: [0x00,0x00,0xc1,0xd5,0x00,0x00,0x00,0x00]
-
-v_movreld_b32 v5, v1
-// GFX10: encoding: [0x01,0x85,0x0a,0x7e]
-
-v_movreld_b32 v255, v1
-// GFX10: encoding: [0x01,0x85,0xfe,0x7f]
-
-v_movreld_b32 v5, v255
-// GFX10: encoding: [0xff,0x85,0x0a,0x7e]
-
-v_movreld_b32 v5, m0
-// GFX10: encoding: [0x7c,0x84,0x0a,0x7e]
-
-v_movreld_b32 v5, 0
-// GFX10: encoding: [0x80,0x84,0x0a,0x7e]
-
-v_movreld_b32 v5, -1
-// GFX10: encoding: [0xc1,0x84,0x0a,0x7e]
-
-v_movreld_b32 v5, 0.5
-// GFX10: encoding: [0xf0,0x84,0x0a,0x7e]
-
-v_movreld_b32 v5, -4.0
-// GFX10: encoding: [0xf7,0x84,0x0a,0x7e]
-
-v_movreld_b32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0x01,0x01,0x00,0x00]
-
-v_movreld_b32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xc2,0xd5,0x01,0x01,0x00,0x00]
-
-v_movreld_b32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00]
-
-v_movreld_b32_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0x7c,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0x80,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xc1,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xf0,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xf7,0x00,0x00,0x00]
-
-v_movreld_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00]
-
-v_movreld_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00]
-
-v_movreld_b32_sdwa v0, 64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00]
-
-v_movreld_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00]
-
-v_movrels_b32 v5, v1
-// GFX10: encoding: [0x01,0x87,0x0a,0x7e]
-
-v_movrels_b32 v255, v1
-// GFX10: encoding: [0x01,0x87,0xfe,0x7f]
-
-v_movrels_b32 v5, v255
-// GFX10: encoding: [0xff,0x87,0x0a,0x7e]
-
-v_movrels_b32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xc3,0xd5,0x01,0x01,0x00,0x00]
-
-v_movrels_b32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xc3,0xd5,0x01,0x01,0x00,0x00]
-
-v_movrels_b32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
-
-v_movrels_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00]
-
-v_movrels_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00]
-
-v_movrels_b32_e32 v5, s1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrels_b32_e32 v5, 1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrels_b32_e64 v5, s1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrels_b32_e64 v5, 1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrels_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
-
-v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
-
-v_movrelsd_b32 v5, v1
-// GFX10: encoding: [0x01,0x89,0x0a,0x7e]
-
-v_movrelsd_b32 v255, v1
-// GFX10: encoding: [0x01,0x89,0xfe,0x7f]
-
-v_movrelsd_b32 v5, v255
-// GFX10: encoding: [0xff,0x89,0x0a,0x7e]
-
-v_movrelsd_b32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
-
-v_movrelsd_b32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
-
-v_movrelsd_b32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
-
-v_movrelsd_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00]
-
-v_movrelsd_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00]
-
-v_movrelsd_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00]
-
-v_movrelsd_b32_e32 v5, s1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrelsd_b32_e32 v5, 1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrelsd_b32_e64 v5, s1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrelsd_b32_e64 v5, 1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrelsd_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
-
-v_movrelsd_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
-
-v_movrelsd_2_b32 v5, v1
-// GFX10: encoding: [0x01,0x91,0x0a,0x7e]
-
-v_movrelsd_2_b32 v255, v1
-// GFX10: encoding: [0x01,0x91,0xfe,0x7f]
-
-v_movrelsd_2_b32 v5, v255
-// GFX10: encoding: [0xff,0x91,0x0a,0x7e]
-
-v_movrelsd_2_b32_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00]
-
-v_movrelsd_2_b32_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00]
-
-v_movrelsd_2_b32_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
-
-v_movrelsd_2_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00]
-
-v_movrelsd_2_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00]
-
-v_movrelsd_2_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00]
-
-v_movrelsd_2_b32_e32 v5, s1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrelsd_2_b32_e32 v5, 1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrelsd_2_b32_e64 v5, s1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrelsd_2_b32_e64 v5, 1
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_movrelsd_2_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
-
-v_movrelsd_2_b32_sdwa v0, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
-
-v_movrelsd_2_b32_sdwa v0, null dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
-
-v_cvt_f16_u16_e32 v5, v1
-// GFX10: encoding: [0x01,0xa1,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v255, v1
-// GFX10: encoding: [0x01,0xa1,0xfe,0x7f]
-
-v_cvt_f16_u16_e32 v5, v255
-// GFX10: encoding: [0xff,0xa1,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, s1
-// GFX10: encoding: [0x01,0xa0,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, s101
-// GFX10: encoding: [0x65,0xa0,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xa0,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xa0,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xa0,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xa0,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xa0,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, 0
-// GFX10: encoding: [0x80,0xa0,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xa0,0x0a,0x7e]
-
-v_cvt_f16_u16_e32 v5, 0.5
-// GFX10: encoding: [0xff,0xa0,0x0a,0x7e,0x00,0x38,0x00,0x00]
-
-v_cvt_f16_u16_e32 v5, -4.0
-// GFX10: encoding: [0xff,0xa0,0x0a,0x7e,0x00,0xc4,0x00,0x00]
-
-v_cvt_f16_u16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xa0,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_f16_u16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xa0,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_u16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd0,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0xff,0x00,0x00,0x00,0x00,0x38,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0xff,0x00,0x00,0x00,0x00,0xc4,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd0,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f16_u16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_u16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_u16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_f16_i16_e32 v5, v1
-// GFX10: encoding: [0x01,0xa3,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v255, v1
-// GFX10: encoding: [0x01,0xa3,0xfe,0x7f]
-
-v_cvt_f16_i16_e32 v5, v255
-// GFX10: encoding: [0xff,0xa3,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, s1
-// GFX10: encoding: [0x01,0xa2,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, s101
-// GFX10: encoding: [0x65,0xa2,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xa2,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xa2,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xa2,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xa2,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xa2,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, 0
-// GFX10: encoding: [0x80,0xa2,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xa2,0x0a,0x7e]
-
-v_cvt_f16_i16_e32 v5, 0.5
-// GFX10: encoding: [0xff,0xa2,0x0a,0x7e,0x00,0x38,0x00,0x00]
-
-v_cvt_f16_i16_e32 v5, -4.0
-// GFX10: encoding: [0xff,0xa2,0x0a,0x7e,0x00,0xc4,0x00,0x00]
-
-v_cvt_f16_i16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xa2,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_f16_i16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xa2,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_i16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd1,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0xff,0x00,0x00,0x00,0x00,0x38,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0xff,0x00,0x00,0x00,0x00,0xc4,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd1,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f16_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_i16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_i16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_u16_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xa5,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xa5,0xfe,0x7f]
-
-v_cvt_u16_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xa5,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xa4,0x0a,0x7e]
-
-v_cvt_u16_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xa4,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_u16_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xa4,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd2,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_u16_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xd2,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd2,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_u16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_u16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_u16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_i16_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xa7,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xa7,0xfe,0x7f]
-
-v_cvt_i16_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xa7,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xa6,0x0a,0x7e]
-
-v_cvt_i16_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xa6,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_i16_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xa6,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd3,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_i16_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xd3,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd3,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_rcp_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xa9,0x0a,0x7e]
-
-v_rcp_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xa9,0xfe,0x7f]
-
-v_rcp_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xa9,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xa8,0x0a,0x7e]
-
-v_rcp_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xa8,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_rcp_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xa8,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_rcp_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd4,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0xff,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x01,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x65,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x6b,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x7c,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x7f,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x80,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x01,0x01,0x00,0x20]
-
-v_rcp_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xd4,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd4,0xd5,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rcp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rcp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rcp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rcp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rcp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rcp_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_sqrt_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xab,0x0a,0x7e]
-
-v_sqrt_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xab,0xfe,0x7f]
-
-v_sqrt_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xab,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xaa,0x0a,0x7e]
-
-v_sqrt_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xaa,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_sqrt_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xaa,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_sqrt_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd5,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0xff,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x01,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x65,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x6b,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x7c,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x7f,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x80,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x01,0x01,0x00,0x20]
-
-v_sqrt_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xd5,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd5,0xd5,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sqrt_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sqrt_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_rsq_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xad,0x0a,0x7e]
-
-v_rsq_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xad,0xfe,0x7f]
-
-v_rsq_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xad,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xac,0x0a,0x7e]
-
-v_rsq_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xac,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_rsq_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xac,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_rsq_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd6,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0xff,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x01,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x65,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x6b,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x7c,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x7f,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x80,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x01,0x01,0x00,0x20]
-
-v_rsq_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xd6,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd6,0xd5,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rsq_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rsq_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rsq_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rsq_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rsq_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rsq_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_log_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xaf,0x0a,0x7e]
-
-v_log_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xaf,0xfe,0x7f]
-
-v_log_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xaf,0x0a,0x7e]
-
-v_log_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xae,0x0a,0x7e]
-
-v_log_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xae,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_log_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xae,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_log_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x01,0x01,0x00,0x00]
-
-v_log_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd7,0xd5,0x01,0x01,0x00,0x00]
-
-v_log_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0xff,0x01,0x00,0x00]
-
-v_log_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x01,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x65,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x6a,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x6b,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x7c,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x7e,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x7f,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x80,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0xc1,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0xf0,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0xf7,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x01,0x01,0x00,0x20]
-
-v_log_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xd7,0xd5,0x01,0x01,0x00,0x00]
-
-v_log_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd7,0xd5,0x01,0x01,0x00,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_log_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_log_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_log_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_log_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_log_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_log_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_exp_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xb1,0x0a,0x7e]
-
-v_exp_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xb1,0xfe,0x7f]
-
-v_exp_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xb1,0x0a,0x7e]
-
-v_exp_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xb0,0x0a,0x7e]
-
-v_exp_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xb0,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_exp_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xb0,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_exp_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x01,0x01,0x00,0x00]
-
-v_exp_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd8,0xd5,0x01,0x01,0x00,0x00]
-
-v_exp_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0xff,0x01,0x00,0x00]
-
-v_exp_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x01,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x65,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x6a,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x6b,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x7c,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x7e,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x7f,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x80,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0xc1,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0xf0,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0xf7,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x01,0x01,0x00,0x20]
-
-v_exp_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xd8,0xd5,0x01,0x01,0x00,0x00]
-
-v_exp_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd8,0xd5,0x01,0x01,0x00,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_exp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_exp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_exp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_exp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_exp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_exp_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_frexp_mant_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xb3,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xb3,0xfe,0x7f]
-
-v_frexp_mant_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xb3,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xb2,0x0a,0x7e]
-
-v_frexp_mant_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xb2,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_frexp_mant_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xb2,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xd9,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0xff,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x01,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x65,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x6b,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x7c,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x7f,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xd9,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xd9,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_mant_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_mant_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_frexp_exp_i16_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xb5,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xb5,0xfe,0x7f]
-
-v_frexp_exp_i16_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xb5,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xb4,0x0a,0x7e]
-
-v_frexp_exp_i16_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xb4,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_frexp_exp_i16_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xb4,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xda,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0xff,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x01,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x65,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x6b,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x7c,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x7f,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i16_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xda,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xda,0xd5,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_floor_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xb7,0x0a,0x7e]
-
-v_floor_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xb7,0xfe,0x7f]
-
-v_floor_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xb7,0x0a,0x7e]
-
-v_floor_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xb6,0x0a,0x7e]
-
-v_floor_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xb6,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_floor_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xb6,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_floor_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xdb,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0xff,0x01,0x00,0x00]
-
-v_floor_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x01,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x65,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x6a,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x6b,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x7c,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x7e,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x7f,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x80,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0xc1,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0xf0,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0xf7,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x01,0x01,0x00,0x20]
-
-v_floor_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xdb,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xdb,0xd5,0x01,0x01,0x00,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_floor_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_floor_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_floor_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_floor_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_floor_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_floor_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_ceil_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xb9,0x0a,0x7e]
-
-v_ceil_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xb9,0xfe,0x7f]
-
-v_ceil_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xb9,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xb8,0x0a,0x7e]
-
-v_ceil_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xb8,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_ceil_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xb8,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_ceil_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0xff,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x01,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x65,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x6a,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x6b,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x7c,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x7e,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x7f,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x80,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0xc1,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0xf0,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0xf7,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x20]
-
-v_ceil_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xdc,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xdc,0xd5,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ceil_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_ceil_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ceil_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ceil_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ceil_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ceil_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_trunc_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xbb,0x0a,0x7e]
-
-v_trunc_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xbb,0xfe,0x7f]
-
-v_trunc_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xbb,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xba,0x0a,0x7e]
-
-v_trunc_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xba,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_trunc_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xba,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_trunc_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xdd,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0xff,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x01,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x65,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x6a,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x6b,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x7c,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x7e,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x7f,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x80,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0xc1,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0xf0,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0xf7,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x01,0x01,0x00,0x20]
-
-v_trunc_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xdd,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xdd,0xd5,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_trunc_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_trunc_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_trunc_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_rndne_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xbd,0x0a,0x7e]
-
-v_rndne_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xbd,0xfe,0x7f]
-
-v_rndne_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xbd,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xbc,0x0a,0x7e]
-
-v_rndne_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xbc,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_rndne_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xbc,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_rndne_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xde,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0xff,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x01,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x65,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x6a,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x6b,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x7c,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x7e,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x7f,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x80,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0xc1,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0xf0,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0xf7,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x01,0x01,0x00,0x20]
-
-v_rndne_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xde,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xde,0xd5,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rndne_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rndne_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rndne_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rndne_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rndne_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rndne_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_fract_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xbf,0x0a,0x7e]
-
-v_fract_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xbf,0xfe,0x7f]
-
-v_fract_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xbf,0x0a,0x7e]
-
-v_fract_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xbe,0x0a,0x7e]
-
-v_fract_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xbe,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_fract_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xbe,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_fract_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xdf,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0xff,0x01,0x00,0x00]
-
-v_fract_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x01,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x65,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x6a,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x6b,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x7c,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x7e,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x7f,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x80,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0xc1,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0xf0,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0xf7,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x01,0x01,0x00,0x20]
-
-v_fract_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xdf,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xdf,0xd5,0x01,0x01,0x00,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_fract_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_fract_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_fract_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_fract_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_fract_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_fract_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_sin_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xc1,0x0a,0x7e]
-
-v_sin_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xc1,0xfe,0x7f]
-
-v_sin_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xc1,0x0a,0x7e]
-
-v_sin_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xc0,0x0a,0x7e]
-
-v_sin_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xc0,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_sin_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xc0,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_sin_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x01,0x01,0x00,0x00]
-
-v_sin_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xe0,0xd5,0x01,0x01,0x00,0x00]
-
-v_sin_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0xff,0x01,0x00,0x00]
-
-v_sin_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x01,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x65,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x6a,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x6b,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x7c,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x7e,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x7f,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x80,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0xc1,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0xf0,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0xf7,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x01,0x01,0x00,0x20]
-
-v_sin_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xe0,0xd5,0x01,0x01,0x00,0x00]
-
-v_sin_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xe0,0xd5,0x01,0x01,0x00,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sin_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sin_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sin_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sin_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sin_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sin_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cos_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xc3,0x0a,0x7e]
-
-v_cos_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xc3,0xfe,0x7f]
-
-v_cos_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xc3,0x0a,0x7e]
-
-v_cos_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xc2,0x0a,0x7e]
-
-v_cos_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xc2,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cos_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xc2,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cos_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00]
-
-v_cos_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00]
-
-v_cos_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0xff,0x01,0x00,0x00]
-
-v_cos_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x01,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x65,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x80,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x01,0x01,0x00,0x20]
-
-v_cos_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xe1,0xd5,0x01,0x01,0x00,0x00]
-
-v_cos_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xe1,0xd5,0x01,0x01,0x00,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cos_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cos_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cos_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cos_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cos_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cos_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_norm_i16_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xc7,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xc7,0xfe,0x7f]
-
-v_cvt_norm_i16_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xc7,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xc6,0x0a,0x7e]
-
-v_cvt_norm_i16_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xc6,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_norm_i16_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xc6,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xe3,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_norm_i16_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xe3,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_norm_i16_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xe3,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_norm_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_norm_i16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_cvt_norm_u16_f16_e32 v5, v1
-// GFX10: encoding: [0x01,0xc9,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v255, v1
-// GFX10: encoding: [0x01,0xc9,0xfe,0x7f]
-
-v_cvt_norm_u16_f16_e32 v5, v255
-// GFX10: encoding: [0xff,0xc9,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, s1
-// GFX10: encoding: [0x01,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, s101
-// GFX10: encoding: [0x65,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, vcc_lo
-// GFX10: encoding: [0x6a,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, vcc_hi
-// GFX10: encoding: [0x6b,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, m0
-// GFX10: encoding: [0x7c,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, exec_lo
-// GFX10: encoding: [0x7e,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, exec_hi
-// GFX10: encoding: [0x7f,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, 0
-// GFX10: encoding: [0x80,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, -1
-// GFX10: encoding: [0xc1,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, 0.5
-// GFX10: encoding: [0xf0,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, -4.0
-// GFX10: encoding: [0xf7,0xc8,0x0a,0x7e]
-
-v_cvt_norm_u16_f16_e32 v5, 0xfe0b
-// GFX10: encoding: [0xff,0xc8,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_norm_u16_f16_e32 v5, 0x3456
-// GFX10: encoding: [0xff,0xc8,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, v1
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v255, v1
-// GFX10: encoding: [0xff,0x00,0xe4,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, v255
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0xff,0x01,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, s1
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x01,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, s101
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x65,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, vcc_lo
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x6a,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, vcc_hi
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x6b,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, m0
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x7c,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, exec_lo
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x7e,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, exec_hi
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x7f,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, 0
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x80,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, -1
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0xc1,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, 0.5
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0xf0,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, -4.0
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0xf7,0x00,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, -v1
-// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x01,0x01,0x00,0x20]
-
-v_cvt_norm_u16_f16_e64 v5, |v1|
-// GFX10: encoding: [0x05,0x01,0xe4,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_norm_u16_f16_e64 v5, v1 clamp
-// GFX10: encoding: [0x05,0x80,0xe4,0xd5,0x01,0x01,0x00,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_norm_u16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_norm_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x51,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x5f,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x61,0x01,0x00]
-
-v_cvt_norm_u16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x6f,0x01,0x00]
-
-v_swap_b32 v5, v1
-// GFX10: encoding: [0x01,0xcb,0x0a,0x7e]
-
-v_swap_b32 v255, v1
-// GFX10: encoding: [0x01,0xcb,0xfe,0x7f]
-
-v_swap_b32 v5, v255
-// GFX10: encoding: [0xff,0xcb,0x0a,0x7e]
-
-v_swaprel_b32 v5, v1
-// GFX10: encoding: [0x01,0xd1,0x0a,0x7e]
-
-v_swaprel_b32 v255, v1
-// GFX10: encoding: [0x01,0xd1,0xfe,0x7f]
-
-v_swaprel_b32 v5, v255
-// GFX10: encoding: [0xff,0xd1,0x0a,0x7e]
-
-//===----------------------------------------------------------------------===//
-// ENC_VOP2.
-//===----------------------------------------------------------------------===//
-
-v_cndmask_b32_e32 v5, v1, v2, vcc
-// W64: encoding: [0x01,0x05,0x0a,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v255, v1, v2, vcc
-// W64: encoding: [0x01,0x05,0xfe,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, v255, v2, vcc
-// W64: encoding: [0xff,0x05,0x0a,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, 0, v2, vcc
-// W64: encoding: [0x80,0x04,0x0a,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, -1, v2, vcc
-// W64: encoding: [0xc1,0x04,0x0a,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, 0.5, v2, vcc
-// W64: encoding: [0xf0,0x04,0x0a,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, -4.0, v2, vcc
-// W64: encoding: [0xf7,0x04,0x0a,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, v1, v255, vcc
-// W64: encoding: [0x01,0xff,0x0b,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e64 v5, v1, v2, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v255, v1, v2, s[6:7]
-// W64: encoding: [0xff,0x00,0x01,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v255, v2, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, 0, v2, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x80,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, -1, v2, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0xc1,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, 0.5, v2, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0xf0,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, -4.0, v2, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0xf7,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, v255, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x1b,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, 0, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x01,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, -1, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x83,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, 0.5, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0xe1,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, -4.0, s[6:7]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0xef,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, v2, s[8:9]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x22,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, v2, s[100:101]
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x92,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, v2, vcc
-// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, v1, v2, vcc_lo
-// W32: encoding: [0x01,0x05,0x0a,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v255, v1, v2, vcc_lo
-// W32: encoding: [0x01,0x05,0xfe,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, v255, v2, vcc_lo
-// W32: encoding: [0xff,0x05,0x0a,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, 0, v2, vcc_lo
-// W32: encoding: [0x80,0x04,0x0a,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, -1, v2, vcc_lo
-// W32: encoding: [0xc1,0x04,0x0a,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, 0.5, v2, vcc_lo
-// W32: encoding: [0xf0,0x04,0x0a,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, -4.0, v2, vcc_lo
-// W32: encoding: [0xf7,0x04,0x0a,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e32 v5, v1, v255, vcc_lo
-// W32: encoding: [0x01,0xff,0x0b,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cndmask_b32_e64 v5, v1, v2, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v255, v1, v2, s6
-// W32: encoding: [0xff,0x00,0x01,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v255, v2, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, 0, v2, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x80,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, -1, v2, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0xc1,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, 0.5, v2, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0xf0,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, -4.0, v2, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0xf7,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, v255, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x1b,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, 0, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x01,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, -1, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x83,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, 0.5, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0xe1,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, -4.0, s6
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0xef,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, v2, s8
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x22,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, v2, s100
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x92,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cndmask_b32_e64 v5, v1, v2, vcc_lo
-// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x06]
-
-v_add_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x07]
-
-v_add_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x06]
-
-v_add_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x06]
-
-v_add_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x06,0x56,0x34,0x12,0xaf]
-
-v_add_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x06,0x73,0x72,0x71,0x3f]
-
-v_add_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x06]
-
-v_add_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x03,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0xff,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x65,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x6a,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x6b,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x7c,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x7e,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x7f,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x80,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0xc1,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0xf0,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0xf7,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xff,0x03,0x00]
-
-v_add_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x00,0x00]
-
-v_add_f32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xcb,0x00,0x00]
-
-v_add_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xd5,0x00,0x00]
-
-v_add_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xd7,0x00,0x00]
-
-v_add_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xf9,0x00,0x00]
-
-v_add_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xfd,0x00,0x00]
-
-v_add_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xff,0x00,0x00]
-
-v_add_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x01,0x01,0x00]
-
-v_add_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x83,0x01,0x00]
-
-v_add_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xe1,0x01,0x00]
-
-v_add_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xef,0x01,0x00]
-
-v_add_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x20]
-
-v_add_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x40]
-
-v_add_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x60]
-
-v_add_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x03,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x03,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x03,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x03,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x08]
-
-v_add_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x10]
-
-v_add_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x18]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x07,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0xff,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x65,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x6a,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x6b,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x7c,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x7e,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x7f,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x06,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x26,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x46,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x86,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0xc6,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x00,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x01,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x02,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x03,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x04,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x05,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x0e,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x00,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x01,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x02,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x03,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x04,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x05,0x06]
-
-v_add_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x16,0x06]
-
-v_add_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x26,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x00]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x01]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x02]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x03]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x04]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x05]
-
-v_add_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x16]
-
-v_add_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x26]
-
-v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x00]
-
-v_add_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0x00]
-
-v_add_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0xff,0xe4,0x00,0x00]
-
-v_add_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x06,0x01,0xe4,0x00,0x00]
-
-v_add_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x10]
-
-v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x30]
-
-v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
-
-v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01]
-
-v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
-
-v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
-
-v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
-
-v_add_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00]
-
-v_add_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00]
-
-v_add_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x40,0x00]
-
-v_add_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x80,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x51,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x61,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x6f,0x01,0x00]
-
-v_sub_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x08]
-
-v_sub_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x09]
-
-v_sub_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x08]
-
-v_sub_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x08]
-
-v_sub_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x08,0x56,0x34,0x12,0xaf]
-
-v_sub_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x08,0x73,0x72,0x71,0x3f]
-
-v_sub_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x08]
-
-v_sub_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x04,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0xff,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x65,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x6a,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x6b,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x7c,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x7e,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x7f,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x80,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0xc1,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0xf0,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0xf7,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xff,0x03,0x00]
-
-v_sub_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xcb,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xd5,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xd7,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xf9,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xfd,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xff,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x01,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x83,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xe1,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xef,0x01,0x00]
-
-v_sub_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x20]
-
-v_sub_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x40]
-
-v_sub_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x60]
-
-v_sub_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x04,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x04,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x04,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x04,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x08]
-
-v_sub_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x10]
-
-v_sub_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x18]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x09,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0xff,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x65,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x6a,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x6b,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x7c,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x7e,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x7f,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x08,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x26,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x46,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x86,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0xc6,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x00,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x01,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x02,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x03,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x04,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x05,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x0e,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x00,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x01,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x02,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x03,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x04,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x05,0x06]
-
-v_sub_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x16,0x06]
-
-v_sub_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x26,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x00]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x01]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x02]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x03]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x04]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x05]
-
-v_sub_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x16]
-
-v_sub_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x26]
-
-v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x09,0x01,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0xff,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x08,0x01,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x10]
-
-v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x30]
-
-v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
-
-v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01]
-
-v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
-
-v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
-
-v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
-
-v_sub_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00]
-
-v_sub_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00]
-
-v_sub_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x40,0x00]
-
-v_sub_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x80,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x51,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x61,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x6f,0x01,0x00]
-
-v_subrev_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x0a]
-
-v_subrev_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x0b]
-
-v_subrev_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x0a]
-
-v_subrev_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x0a,0x56,0x34,0x12,0xaf]
-
-v_subrev_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x0a,0x73,0x72,0x71,0x3f]
-
-v_subrev_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x0a]
-
-v_subrev_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x05,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0xff,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x65,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x6a,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x6b,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x7c,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x7e,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x7f,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x80,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0xc1,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0xf0,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0xf7,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xff,0x03,0x00]
-
-v_subrev_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xcb,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xd5,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xd7,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xf9,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xfd,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xff,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x01,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x83,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xe1,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xef,0x01,0x00]
-
-v_subrev_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x20]
-
-v_subrev_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x40]
-
-v_subrev_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x60]
-
-v_subrev_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x05,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x05,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x05,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x05,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x08]
-
-v_subrev_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x10]
-
-v_subrev_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x18]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x0b,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0xff,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x65,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x6a,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x6b,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x7c,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x7e,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x7f,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x0a,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x26,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x46,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x86,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0xc6,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x00,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x01,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x02,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x03,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x04,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x05,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x0e,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x00,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x01,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x02,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x03,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x04,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x05,0x06]
-
-v_subrev_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x16,0x06]
-
-v_subrev_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x26,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x00]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x01]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x02]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x03]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x04]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x05]
-
-v_subrev_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x16]
-
-v_subrev_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x26]
-
-v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x0b,0x01,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0xff,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x0a,0x01,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x10]
-
-v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x30]
-
-v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01]
-
-v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
-
-v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
-
-v_subrev_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00]
-
-v_subrev_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00]
-
-v_subrev_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x40,0x00]
-
-v_subrev_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x80,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x51,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x61,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x6f,0x01,0x00]
-
-v_mac_legacy_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x0d]
-
-v_mac_legacy_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x0c,0x56,0x34,0x12,0xaf]
-
-v_mac_legacy_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x0c,0x73,0x72,0x71,0x3f]
-
-v_mac_legacy_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x0c]
-
-v_mac_legacy_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x06,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0xff,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x67,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x77,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x80,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xff,0x03,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xcf,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xef,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xff,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x01,0x01,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x83,0x01,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xef,0x01,0x00]
-
-v_mac_legacy_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x20]
-
-v_mac_legacy_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x40]
-
-v_mac_legacy_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x60]
-
-v_mac_legacy_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x06,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x06,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x06,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x06,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x08]
-
-v_mac_legacy_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x10]
-
-v_mac_legacy_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x18]
-
-v_mul_legacy_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x0f]
-
-v_mul_legacy_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x0e,0x56,0x34,0x12,0xaf]
-
-v_mul_legacy_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x0e,0x73,0x72,0x71,0x3f]
-
-v_mul_legacy_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x0e]
-
-v_mul_legacy_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x07,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x65,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xcb,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x20]
-
-v_mul_legacy_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x40]
-
-v_mul_legacy_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x60]
-
-v_mul_legacy_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x07,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x07,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x07,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x07,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x08]
-
-v_mul_legacy_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x10]
-
-v_mul_legacy_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x18]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0xff,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x65,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x6a,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x6b,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x7c,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x7e,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x7f,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x26,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x46,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x86,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0xc6,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x00,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x01,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x02,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x03,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x04,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x05,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x0e,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x00,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x01,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x02,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x03,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x04,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x05,0x06]
-
-v_mul_legacy_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x16,0x06]
-
-v_mul_legacy_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x26,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x00]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x01]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x02]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x03]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x04]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x05]
-
-v_mul_legacy_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x16]
-
-v_mul_legacy_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x26]
-
-v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x0f,0x01,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0xff,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x0e,0x01,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x10]
-
-v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x30]
-
-v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
-
-v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01]
-
-v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
-
-v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
-
-v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
-
-v_mul_legacy_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x10,0x00]
-
-v_mul_legacy_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x20,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x40,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x80,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x51,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x61,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x6f,0x01,0x00]
-
-v_mul_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x10]
-
-v_mul_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x11]
-
-v_mul_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x10]
-
-v_mul_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x10]
-
-v_mul_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x10,0x56,0x34,0x12,0xaf]
-
-v_mul_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x10,0x73,0x72,0x71,0x3f]
-
-v_mul_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x10]
-
-v_mul_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x08,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x65,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xcb,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x20]
-
-v_mul_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x40]
-
-v_mul_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x60]
-
-v_mul_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x08,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x08,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x08,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x08,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x08]
-
-v_mul_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x10]
-
-v_mul_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x18]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0xff,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x65,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x6a,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x6b,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x7c,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x7e,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x7f,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x26,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x46,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x86,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0xc6,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x00,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x01,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x02,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x03,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x04,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x05,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x0e,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x00,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x01,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x02,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x03,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x04,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x05,0x06]
-
-v_mul_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x16,0x06]
-
-v_mul_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x26,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x00]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x01]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x02]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x03]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x04]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x05]
-
-v_mul_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x16]
-
-v_mul_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x26]
-
-v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x11,0x01,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0xff,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x10,0x01,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x10]
-
-v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x30]
-
-v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
-
-v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01]
-
-v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
-
-v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
-
-v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
-
-v_mul_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x10,0x00]
-
-v_mul_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x20,0x00]
-
-v_mul_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x40,0x00]
-
-v_mul_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x80,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x51,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x61,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x6f,0x01,0x00]
-
-v_mul_i32_i24_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x12]
-
-v_mul_i32_i24_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x13]
-
-v_mul_i32_i24_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x12]
-
-v_mul_i32_i24_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0xaf]
-
-v_mul_i32_i24_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x3f]
-
-v_mul_i32_i24_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x12]
-
-v_mul_i32_i24_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x09,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x65,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_i32_i24_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xcb,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, -4.0 clamp
-// GFX10: encoding: [0x05,0x80,0x09,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0xff,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x65,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x6a,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x6b,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x7c,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x7e,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x7f,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x26,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x00,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x01,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x02,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x03,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x04,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x05,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x0e,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x00,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x01,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x02,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x03,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x04,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x05,0x06]
-
-v_mul_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x0e,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x00]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x01]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x02]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x03]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x04]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x05]
-
-v_mul_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x0e]
-
-v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x13,0x01,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0xff,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x12,0x01,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x10]
-
-v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x30]
-
-v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
-
-v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01]
-
-v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
-
-v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
-
-v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x51,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x61,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x6f,0x01,0x00]
-
-v_mul_hi_i32_i24_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x15]
-
-v_mul_hi_i32_i24_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x14,0x56,0x34,0x12,0xaf]
-
-v_mul_hi_i32_i24_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x14,0x73,0x72,0x71,0x3f]
-
-v_mul_hi_i32_i24_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x14]
-
-v_mul_hi_i32_i24_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x0a,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x65,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0xff,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x65,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x6a,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x6b,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x7c,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x7e,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x7f,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x14,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x26,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x00,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x01,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x02,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x03,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x04,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x05,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x0e,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x00,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x01,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x02,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x03,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x04,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x05,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x0e,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x00]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x01]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x02]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x03]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x04]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x05]
-
-v_mul_hi_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x0e]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x15,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0xff,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x14,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x10]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x30]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x51,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x61,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x6f,0x01,0x00]
-
-v_mul_u32_u24_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x16]
-
-v_mul_u32_u24_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x17]
-
-v_mul_u32_u24_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x16]
-
-v_mul_u32_u24_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x16,0x56,0x34,0x12,0xaf]
-
-v_mul_u32_u24_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x16,0x73,0x72,0x71,0x3f]
-
-v_mul_u32_u24_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x16]
-
-v_mul_u32_u24_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x0b,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x65,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_u32_u24_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xcb,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, -4.0 clamp
-// GFX10: encoding: [0x05,0x80,0x0b,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0xff,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x65,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x6a,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x6b,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x7c,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x7e,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x7f,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x16,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x26,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x00,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x01,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x02,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x03,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x04,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x05,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x0e,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x00,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x01,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x02,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x03,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x04,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x05,0x06]
-
-v_mul_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x0e,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x00]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x01]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x02]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x03]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x04]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x05]
-
-v_mul_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x0e]
-
-v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x17,0x01,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0xff,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x16,0x01,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x10]
-
-v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x30]
-
-v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
-
-v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01]
-
-v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
-
-v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
-
-v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x51,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x61,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x6f,0x01,0x00]
-
-v_mul_hi_u32_u24_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x19]
-
-v_mul_hi_u32_u24_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x18,0x56,0x34,0x12,0xaf]
-
-v_mul_hi_u32_u24_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x18,0x73,0x72,0x71,0x3f]
-
-v_mul_hi_u32_u24_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x18]
-
-v_mul_hi_u32_u24_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x0c,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x65,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x19,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0xff,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x65,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x6a,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x6b,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x7c,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x7e,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x7f,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x18,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x26,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x00,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x01,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x02,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x03,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x04,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x05,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x0e,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x00,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x01,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x02,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x03,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x04,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x05,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x0e,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x00]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x01]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x02]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x03]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x04]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x05]
-
-v_mul_hi_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x0e]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x19,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0xff,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x18,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x10]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x30]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x51,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x61,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x6f,0x01,0x00]
-
-v_min_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x1e]
-
-v_min_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x1f]
-
-v_min_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x1e]
-
-v_min_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x1e]
-
-v_min_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x1e,0x56,0x34,0x12,0xaf]
-
-v_min_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x1e,0x73,0x72,0x71,0x3f]
-
-v_min_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x1e]
-
-v_min_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x0f,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0xff,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x65,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x6a,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x6b,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x7c,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x7e,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x7f,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x80,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0xc1,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0xf0,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0xf7,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xff,0x03,0x00]
-
-v_min_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x00,0x00]
-
-v_min_f32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xcb,0x00,0x00]
-
-v_min_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xd5,0x00,0x00]
-
-v_min_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xd7,0x00,0x00]
-
-v_min_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xf9,0x00,0x00]
-
-v_min_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xfd,0x00,0x00]
-
-v_min_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xff,0x00,0x00]
-
-v_min_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x01,0x01,0x00]
-
-v_min_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x83,0x01,0x00]
-
-v_min_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xe1,0x01,0x00]
-
-v_min_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xef,0x01,0x00]
-
-v_min_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x20]
-
-v_min_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x40]
-
-v_min_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x60]
-
-v_min_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x0f,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x0f,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x0f,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x0f,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x08]
-
-v_min_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x10]
-
-v_min_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x18]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0xff,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x65,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x6a,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x6b,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x7c,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x7e,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x7f,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x1e,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x26,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x46,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x86,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0xc6,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x00,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x01,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x02,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x03,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x04,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x05,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x0e,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x00,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x01,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x02,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x03,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x04,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x05,0x06]
-
-v_min_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x16,0x06]
-
-v_min_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x26,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x00]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x01]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x02]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x03]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x04]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x05]
-
-v_min_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x16]
-
-v_min_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x26]
-
-v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x00]
-
-v_min_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x1f,0x01,0xe4,0x00,0x00]
-
-v_min_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0xff,0xe4,0x00,0x00]
-
-v_min_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x1e,0x01,0xe4,0x00,0x00]
-
-v_min_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x10]
-
-v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x30]
-
-v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
-
-v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01]
-
-v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
-
-v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
-
-v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
-
-v_min_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x10,0x00]
-
-v_min_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x20,0x00]
-
-v_min_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x40,0x00]
-
-v_min_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x80,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x51,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x5f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x61,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x6f,0x01,0x00]
-
-v_max_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x20]
-
-v_max_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x21]
-
-v_max_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x20]
-
-v_max_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x20]
-
-v_max_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x20,0x56,0x34,0x12,0xaf]
-
-v_max_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x20,0x73,0x72,0x71,0x3f]
-
-v_max_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x20]
-
-v_max_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x10,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0xff,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x65,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x6a,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x6b,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x7c,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x7e,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x7f,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x80,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0xc1,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0xf0,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0xf7,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xff,0x03,0x00]
-
-v_max_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x00,0x00]
-
-v_max_f32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xcb,0x00,0x00]
-
-v_max_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xd5,0x00,0x00]
-
-v_max_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xd7,0x00,0x00]
-
-v_max_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xf9,0x00,0x00]
-
-v_max_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xfd,0x00,0x00]
-
-v_max_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xff,0x00,0x00]
-
-v_max_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x01,0x01,0x00]
-
-v_max_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x83,0x01,0x00]
-
-v_max_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xe1,0x01,0x00]
-
-v_max_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xef,0x01,0x00]
-
-v_max_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x20]
-
-v_max_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x40]
-
-v_max_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x60]
-
-v_max_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x10,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x10,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x10,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x10,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x08]
-
-v_max_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x10]
-
-v_max_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x18]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0xff,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x65,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x6a,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x6b,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x7c,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x7e,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x7f,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x20,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x26,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x46,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x86,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0xc6,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x00,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x01,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x02,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x03,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x04,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x05,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x0e,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x00,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x01,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x02,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x03,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x04,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x05,0x06]
-
-v_max_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x16,0x06]
-
-v_max_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x26,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x00]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x01]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x02]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x03]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x04]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x05]
-
-v_max_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x16]
-
-v_max_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x26]
-
-v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x00]
-
-v_max_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x21,0x01,0xe4,0x00,0x00]
-
-v_max_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0xff,0xe4,0x00,0x00]
-
-v_max_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x20,0x01,0xe4,0x00,0x00]
-
-v_max_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x10]
-
-v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x30]
-
-v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
-
-v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01]
-
-v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
-
-v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
-
-v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
-
-v_max_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x10,0x00]
-
-v_max_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x20,0x00]
-
-v_max_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x40,0x00]
-
-v_max_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x80,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x51,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x5f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x61,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x6f,0x01,0x00]
-
-v_min_i32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x22]
-
-v_min_i32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x23]
-
-v_min_i32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x22]
-
-v_min_i32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x22]
-
-v_min_i32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x22,0x56,0x34,0x12,0xaf]
-
-v_min_i32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x22,0x73,0x72,0x71,0x3f]
-
-v_min_i32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x22]
-
-v_min_i32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_i32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x11,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_i32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0xff,0x05,0x02,0x00]
-
-v_min_i32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x65,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x6a,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x6b,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x7c,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x7e,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x7f,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x80,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0xc1,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0xf0,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0xf7,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xff,0x03,0x00]
-
-v_min_i32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x05,0x00,0x00]
-
-v_min_i32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xcb,0x00,0x00]
-
-v_min_i32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xd5,0x00,0x00]
-
-v_min_i32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xd7,0x00,0x00]
-
-v_min_i32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xf9,0x00,0x00]
-
-v_min_i32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xfd,0x00,0x00]
-
-v_min_i32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xff,0x00,0x00]
-
-v_min_i32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x01,0x01,0x00]
-
-v_min_i32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x83,0x01,0x00]
-
-v_min_i32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xe1,0x01,0x00]
-
-v_min_i32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xef,0x01,0x00]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0xff,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x65,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x6a,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x6b,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x7c,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x7e,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x7f,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x22,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x26,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x00,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x01,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x02,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x03,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x04,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x05,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x0e,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x00,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x01,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x02,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x03,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x04,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x05,0x06]
-
-v_min_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x0e,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x00]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x01]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x02]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x03]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x04]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x05]
-
-v_min_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x0e]
-
-v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00]
-
-v_min_i32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00]
-
-v_min_i32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0xff,0xe4,0x00,0x00]
-
-v_min_i32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x22,0x01,0xe4,0x00,0x00]
-
-v_min_i32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x10]
-
-v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x30]
-
-v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
-
-v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01]
-
-v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
-
-v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
-
-v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x51,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x61,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x6f,0x01,0x00]
-
-v_max_i32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x24]
-
-v_max_i32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x25]
-
-v_max_i32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x24]
-
-v_max_i32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x24]
-
-v_max_i32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x24,0x56,0x34,0x12,0xaf]
-
-v_max_i32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x24,0x73,0x72,0x71,0x3f]
-
-v_max_i32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x24]
-
-v_max_i32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_i32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x12,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_i32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0xff,0x05,0x02,0x00]
-
-v_max_i32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x65,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x6a,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x6b,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x7c,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x7e,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x7f,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x80,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0xc1,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0xf0,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0xf7,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xff,0x03,0x00]
-
-v_max_i32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x05,0x00,0x00]
-
-v_max_i32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xcb,0x00,0x00]
-
-v_max_i32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xd5,0x00,0x00]
-
-v_max_i32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xd7,0x00,0x00]
-
-v_max_i32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xf9,0x00,0x00]
-
-v_max_i32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xfd,0x00,0x00]
-
-v_max_i32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xff,0x00,0x00]
-
-v_max_i32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x01,0x01,0x00]
-
-v_max_i32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x83,0x01,0x00]
-
-v_max_i32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xe1,0x01,0x00]
-
-v_max_i32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xef,0x01,0x00]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0xff,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x65,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x6a,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x6b,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x7c,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x7e,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x7f,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x24,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x26,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x00,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x01,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x02,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x03,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x04,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x05,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x0e,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x00,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x01,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x02,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x03,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x04,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x05,0x06]
-
-v_max_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x0e,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x00]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x01]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x02]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x03]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x04]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x05]
-
-v_max_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x0e]
-
-v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00]
-
-v_max_i32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00]
-
-v_max_i32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0xff,0xe4,0x00,0x00]
-
-v_max_i32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x24,0x01,0xe4,0x00,0x00]
-
-v_max_i32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x10]
-
-v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x30]
-
-v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
-
-v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01]
-
-v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
-
-v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
-
-v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x51,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x61,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x6f,0x01,0x00]
-
-v_min_u32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x26]
-
-v_min_u32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x27]
-
-v_min_u32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x26]
-
-v_min_u32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x26]
-
-v_min_u32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x26,0x56,0x34,0x12,0xaf]
-
-v_min_u32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x26,0x73,0x72,0x71,0x3f]
-
-v_min_u32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x26]
-
-v_min_u32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_u32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x13,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_u32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0xff,0x05,0x02,0x00]
-
-v_min_u32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x65,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x6a,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x6b,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x7c,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x7e,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x7f,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x80,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0xc1,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0xf0,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0xf7,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xff,0x03,0x00]
-
-v_min_u32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x05,0x00,0x00]
-
-v_min_u32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xcb,0x00,0x00]
-
-v_min_u32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xd5,0x00,0x00]
-
-v_min_u32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xd7,0x00,0x00]
-
-v_min_u32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xf9,0x00,0x00]
-
-v_min_u32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xfd,0x00,0x00]
-
-v_min_u32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xff,0x00,0x00]
-
-v_min_u32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x01,0x01,0x00]
-
-v_min_u32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x83,0x01,0x00]
-
-v_min_u32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xe1,0x01,0x00]
-
-v_min_u32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xef,0x01,0x00]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0xff,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x65,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x6a,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x6b,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x7c,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x7e,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x7f,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x26,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x26,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x00,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x01,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x02,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x03,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x04,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x05,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x0e,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x00,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x01,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x02,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x03,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x04,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x05,0x06]
-
-v_min_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x0e,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x00]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x01]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x02]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x03]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x04]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x05]
-
-v_min_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x0e]
-
-v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00]
-
-v_min_u32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00]
-
-v_min_u32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0xff,0xe4,0x00,0x00]
-
-v_min_u32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x26,0x01,0xe4,0x00,0x00]
-
-v_min_u32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x10]
-
-v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x30]
-
-v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
-
-v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01]
-
-v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
-
-v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
-
-v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x51,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x61,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x6f,0x01,0x00]
-
-v_max_u32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x28]
-
-v_max_u32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x29]
-
-v_max_u32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x28]
-
-v_max_u32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x28]
-
-v_max_u32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x28,0x56,0x34,0x12,0xaf]
-
-v_max_u32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x28,0x73,0x72,0x71,0x3f]
-
-v_max_u32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x28]
-
-v_max_u32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_u32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x14,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_u32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0xff,0x05,0x02,0x00]
-
-v_max_u32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x65,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x6a,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x6b,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x7c,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x7e,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x7f,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x80,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0xc1,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0xf0,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0xf7,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xff,0x03,0x00]
-
-v_max_u32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x05,0x00,0x00]
-
-v_max_u32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xcb,0x00,0x00]
-
-v_max_u32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xd5,0x00,0x00]
-
-v_max_u32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xd7,0x00,0x00]
-
-v_max_u32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xf9,0x00,0x00]
-
-v_max_u32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xfd,0x00,0x00]
-
-v_max_u32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xff,0x00,0x00]
-
-v_max_u32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x01,0x01,0x00]
-
-v_max_u32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x83,0x01,0x00]
-
-v_max_u32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xe1,0x01,0x00]
-
-v_max_u32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xef,0x01,0x00]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0xff,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x65,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x6a,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x6b,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x7c,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x7e,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x7f,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x28,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x26,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x00,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x01,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x02,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x03,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x04,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x05,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x0e,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x00,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x01,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x02,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x03,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x04,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x05,0x06]
-
-v_max_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x0e,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x00]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x01]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x02]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x03]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x04]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x05]
-
-v_max_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x0e]
-
-v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00]
-
-v_max_u32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00]
-
-v_max_u32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0xff,0xe4,0x00,0x00]
-
-v_max_u32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x28,0x01,0xe4,0x00,0x00]
-
-v_max_u32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x10]
-
-v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x30]
-
-v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
-
-v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01]
-
-v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
-
-v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
-
-v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x51,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x61,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x6f,0x01,0x00]
-
-v_lshrrev_b32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x2d]
-
-v_lshrrev_b32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x2c]
-
-v_lshrrev_b32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x2c,0x56,0x34,0x12,0xaf]
-
-v_lshrrev_b32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x2c,0x73,0x72,0x71,0x3f]
-
-v_lshrrev_b32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x2c]
-
-v_lshrrev_b32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x16,0xd5,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x65,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0xf0,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0xf7,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xff,0x03,0x00]
-
-v_lshrrev_b32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x05,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xcb,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xd7,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xf9,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xff,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xe1,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xef,0x01,0x00]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x2d,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0xff,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x65,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x6a,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x6b,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x7c,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x7e,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x7f,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x2c,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x00,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x01,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x02,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x03,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x04,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x05,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x0e,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x00,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x01,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x02,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x03,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x04,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x05,0x06]
-
-v_lshrrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x0e,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x00]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x01]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x02]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x03]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x04]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x05]
-
-v_lshrrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x0e]
-
-v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0xff,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x2c,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x10]
-
-v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x30]
-
-v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
-
-v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01]
-
-v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
-
-v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
-
-v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x51,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x5f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x61,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x6f,0x01,0x00]
-
-v_ashrrev_i32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x30]
-
-v_ashrrev_i32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x31]
-
-v_ashrrev_i32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x30]
-
-v_ashrrev_i32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x30,0x56,0x34,0x12,0xaf]
-
-v_ashrrev_i32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x30,0x73,0x72,0x71,0x3f]
-
-v_ashrrev_i32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x30]
-
-v_ashrrev_i32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x18,0xd5,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x65,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0xf0,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0xf7,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xff,0x03,0x00]
-
-v_ashrrev_i32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x05,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xcb,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xd7,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xf9,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xff,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xe1,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xef,0x01,0x00]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x31,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0xff,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x65,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x6a,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x6b,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x7c,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x7e,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x7f,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x30,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x00,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x01,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x02,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x03,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x04,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x05,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x0e,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x00,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x01,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x02,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x03,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x04,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x05,0x06]
-
-v_ashrrev_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x0e,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x00]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x01]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x02]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x03]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x04]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x05]
-
-v_ashrrev_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x0e]
-
-v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x31,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0xff,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x30,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x10]
-
-v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x30]
-
-v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xf0]
-
-v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x01]
-
-v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x03]
-
-v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x0f]
-
-v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x08,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x51,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x61,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x6f,0x01,0x00]
-
-v_lshlrev_b32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x34]
-
-v_lshlrev_b32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x35]
-
-v_lshlrev_b32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x34]
-
-v_lshlrev_b32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x34,0x56,0x34,0x12,0xaf]
-
-v_lshlrev_b32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x34,0x73,0x72,0x71,0x3f]
-
-v_lshlrev_b32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x34]
-
-v_lshlrev_b32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x1a,0xd5,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x65,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0xf0,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0xf7,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xff,0x03,0x00]
-
-v_lshlrev_b32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x05,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xcb,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xd7,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xf9,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xff,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xe1,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xef,0x01,0x00]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0xff,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x65,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x6a,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x6b,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x7c,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x7e,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x7f,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x34,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x00,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x01,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x02,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x03,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x04,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x05,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x0e,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x00,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x01,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x02,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x03,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x04,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x05,0x06]
-
-v_lshlrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x0e,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x00]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x01]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x02]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x03]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x04]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x05]
-
-v_lshlrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x0e]
-
-v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0xff,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x34,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x10]
-
-v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x30]
-
-v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
-
-v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01]
-
-v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
-
-v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
-
-v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x51,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x61,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x6f,0x01,0x00]
-
-v_and_b32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x36]
-
-v_and_b32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x37]
-
-v_and_b32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x36]
-
-v_and_b32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x36]
-
-v_and_b32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x36,0x56,0x34,0x12,0xaf]
-
-v_and_b32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x36,0x73,0x72,0x71,0x3f]
-
-v_and_b32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x36]
-
-v_and_b32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x05,0x02,0x00]
-
-v_and_b32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x1b,0xd5,0x01,0x05,0x02,0x00]
-
-v_and_b32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0xff,0x05,0x02,0x00]
-
-v_and_b32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x65,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x6a,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x6b,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x7c,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x7e,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x7f,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x80,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0xc1,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0xf0,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0xf7,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xff,0x03,0x00]
-
-v_and_b32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x05,0x00,0x00]
-
-v_and_b32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xcb,0x00,0x00]
-
-v_and_b32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xd5,0x00,0x00]
-
-v_and_b32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xd7,0x00,0x00]
-
-v_and_b32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xf9,0x00,0x00]
-
-v_and_b32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xfd,0x00,0x00]
-
-v_and_b32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xff,0x00,0x00]
-
-v_and_b32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x01,0x01,0x00]
-
-v_and_b32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x83,0x01,0x00]
-
-v_and_b32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xe1,0x01,0x00]
-
-v_and_b32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xef,0x01,0x00]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0xff,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x65,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x6a,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x6b,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x7c,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x7e,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x7f,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x36,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x00,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x01,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x02,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x03,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x04,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x05,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x0e,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x00,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x01,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x02,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x03,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x04,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x05,0x06]
-
-v_and_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x0e,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x00]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x01]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x02]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x03]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x04]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x05]
-
-v_and_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x0e]
-
-v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x00]
-
-v_and_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x37,0x01,0xe4,0x00,0x00]
-
-v_and_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0xff,0xe4,0x00,0x00]
-
-v_and_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x36,0x01,0xe4,0x00,0x00]
-
-v_and_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x10]
-
-v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x30]
-
-v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
-
-v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01]
-
-v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
-
-v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
-
-v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x51,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x61,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x6f,0x01,0x00]
-
-v_or_b32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x38]
-
-v_or_b32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x39]
-
-v_or_b32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x38]
-
-v_or_b32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x38]
-
-v_or_b32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x38,0x56,0x34,0x12,0xaf]
-
-v_or_b32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x38,0x73,0x72,0x71,0x3f]
-
-v_or_b32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x38]
-
-v_or_b32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x05,0x02,0x00]
-
-v_or_b32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x1c,0xd5,0x01,0x05,0x02,0x00]
-
-v_or_b32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0xff,0x05,0x02,0x00]
-
-v_or_b32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x65,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x6a,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x6b,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x7c,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x7e,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x7f,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x80,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0xc1,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0xf0,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0xf7,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xff,0x03,0x00]
-
-v_or_b32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x05,0x00,0x00]
-
-v_or_b32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xcb,0x00,0x00]
-
-v_or_b32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xd5,0x00,0x00]
-
-v_or_b32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xd7,0x00,0x00]
-
-v_or_b32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xf9,0x00,0x00]
-
-v_or_b32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xfd,0x00,0x00]
-
-v_or_b32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xff,0x00,0x00]
-
-v_or_b32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x01,0x01,0x00]
-
-v_or_b32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x83,0x01,0x00]
-
-v_or_b32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xe1,0x01,0x00]
-
-v_or_b32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xef,0x01,0x00]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0xff,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x65,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x6a,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x6b,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x7c,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x7e,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x7f,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x38,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x00,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x01,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x02,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x03,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x04,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x05,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x0e,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x00,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x01,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x02,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x03,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x04,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x05,0x06]
-
-v_or_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x0e,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x00]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x01]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x02]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x03]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x04]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x05]
-
-v_or_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x0e]
-
-v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x00]
-
-v_or_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x39,0x01,0xe4,0x00,0x00]
-
-v_or_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0xff,0xe4,0x00,0x00]
-
-v_or_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x38,0x01,0xe4,0x00,0x00]
-
-v_or_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x10]
-
-v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x30]
-
-v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
-
-v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01]
-
-v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
-
-v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
-
-v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x51,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x61,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x6f,0x01,0x00]
-
-v_xor_b32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x3a]
-
-v_xor_b32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x3b]
-
-v_xor_b32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x3a]
-
-v_xor_b32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x3a]
-
-v_xor_b32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x3a,0x56,0x34,0x12,0xaf]
-
-v_xor_b32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x3a,0x73,0x72,0x71,0x3f]
-
-v_xor_b32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x3a]
-
-v_xor_b32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x05,0x02,0x00]
-
-v_xor_b32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x1d,0xd5,0x01,0x05,0x02,0x00]
-
-v_xor_b32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0xff,0x05,0x02,0x00]
-
-v_xor_b32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x65,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x6a,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x6b,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x7c,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x7e,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x7f,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x80,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0xc1,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0xf0,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0xf7,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xff,0x03,0x00]
-
-v_xor_b32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x05,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xcb,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xd5,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xd7,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xf9,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xfd,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xff,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x01,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x83,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xe1,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xef,0x01,0x00]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0xff,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x65,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x6b,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x7c,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x7e,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x7f,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x3a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x00,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x01,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x02,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x03,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x04,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x05,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x0e,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x00,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x01,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x02,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x03,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x04,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x05,0x06]
-
-v_xor_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x0e,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x00]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x01]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x02]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x03]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x04]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x05]
-
-v_xor_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x0e]
-
-v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x3b,0x01,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0xff,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x3a,0x01,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x10]
-
-v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x30]
-
-v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
-
-v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01]
-
-v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
-
-v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
-
-v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x51,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x61,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x6f,0x01,0x00]
-
-v_xnor_b32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x3c]
-
-v_xnor_b32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x3d]
-
-v_xnor_b32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x3c]
-
-v_xnor_b32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x3c,0x56,0x34,0x12,0xaf]
-
-v_xnor_b32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x3c,0x73,0x72,0x71,0x3f]
-
-v_xnor_b32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x3c]
-
-v_xnor_b32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x05,0x02,0x00]
-
-v_xnor_b32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x1e,0xd5,0x01,0x05,0x02,0x00]
-
-v_xnor_b32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0xff,0x05,0x02,0x00]
-
-v_xnor_b32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x65,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x6a,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x6b,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x7c,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x7e,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x7f,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x80,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0xc1,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0xf0,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0xf7,0x04,0x02,0x00]
-
-v_xnor_b32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xff,0x03,0x00]
-
-v_xnor_b32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x05,0x00,0x00]
-
-v_xnor_b32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xcb,0x00,0x00]
-
-v_xnor_b32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xd5,0x00,0x00]
-
-v_xnor_b32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xd7,0x00,0x00]
-
-v_xnor_b32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xf9,0x00,0x00]
-
-v_xnor_b32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xfd,0x00,0x00]
-
-v_xnor_b32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xff,0x00,0x00]
-
-v_xnor_b32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x01,0x01,0x00]
-
-v_xnor_b32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x83,0x01,0x00]
-
-v_xnor_b32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xe1,0x01,0x00]
-
-v_xnor_b32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xef,0x01,0x00]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_xnor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0xff,0x06,0x06,0x06]
-
-v_xnor_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x86,0x06]
-
-v_xnor_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x65,0x06,0x86,0x06]
-
-v_xnor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x6a,0x06,0x86,0x06]
-
-v_xnor_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x6b,0x06,0x86,0x06]
-
-v_xnor_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x7c,0x06,0x86,0x06]
-
-v_xnor_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x7e,0x06,0x86,0x06]
-
-v_xnor_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x7f,0x06,0x86,0x06]
-
-v_xnor_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x3c,0x01,0x06,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x00,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x01,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x02,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x03,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x04,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x05,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x0e,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x00,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x01,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x02,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x03,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x04,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x05,0x06]
-
-v_xnor_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x0e,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x00]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x01]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x02]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x03]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x04]
-
-v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x05]
-
-v_xnor_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x0e]
-
-v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x00]
-
-v_xnor_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x3d,0x01,0xe4,0x00,0x00]
-
-v_xnor_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0xff,0xe4,0x00,0x00]
-
-v_xnor_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x3c,0x01,0xe4,0x00,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x10]
-
-v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x30]
-
-v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
-
-v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01]
-
-v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
-
-v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
-
-v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x51,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x61,0x01,0x00]
-
-v_xnor_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x6f,0x01,0x00]
-
-v_mac_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x3e]
-
-v_mac_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x3f]
-
-v_mac_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x3e]
-
-v_mac_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x3e]
-
-v_mac_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x3e,0x56,0x34,0x12,0xaf]
-
-v_mac_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x3e,0x73,0x72,0x71,0x3f]
-
-v_mac_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x3e]
-
-v_mac_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x1f,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0xff,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x65,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x80,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xff,0x03,0x00]
-
-v_mac_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xcb,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xff,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x01,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x83,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xef,0x01,0x00]
-
-v_mac_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x20]
-
-v_mac_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x40]
-
-v_mac_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x60]
-
-v_mac_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x1f,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x1f,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x1f,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x1f,0xd5,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x08]
-
-v_mac_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x10]
-
-v_mac_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x18]
-
-v_madmk_f32 v5, v1, 0x11213141, v3
-// GFX10: encoding: [0x01,0x07,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v255, v1, 0x11213141, v3
-// GFX10: encoding: [0x01,0x07,0xfe,0x41,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, v255, 0x11213141, v3
-// GFX10: encoding: [0xff,0x07,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, 0, 0x11213141, v3
-// GFX10: encoding: [0x80,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, -1, 0x11213141, v3
-// GFX10: encoding: [0xc1,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, 0.5, 0x11213141, v3
-// GFX10: encoding: [0xf0,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, -4.0, 0x11213141, v3
-// GFX10: encoding: [0xf7,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, v1, 0xa1b1c1d1, v3
-// GFX10: encoding: [0x01,0x07,0x0a,0x40,0xd1,0xc1,0xb1,0xa1]
-
-v_madmk_f32 v5, v1, 0x11213141, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x40,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v2, 0x11213141
-// GFX10: encoding: [0x01,0x05,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v255, v1, v2, 0x11213141
-// GFX10: encoding: [0x01,0x05,0xfe,0x43,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v255, v2, 0x11213141
-// GFX10: encoding: [0xff,0x05,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, 0, v2, 0x11213141
-// GFX10: encoding: [0x80,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, -1, v2, 0x11213141
-// GFX10: encoding: [0xc1,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, 0.5, v2, 0x11213141
-// GFX10: encoding: [0xf0,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, -4.0, v2, 0x11213141
-// GFX10: encoding: [0xf7,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v255, 0x11213141
-// GFX10: encoding: [0x01,0xff,0x0b,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v2, 0xa1b1c1d1
-// GFX10: encoding: [0x01,0x05,0x0a,0x42,0xd1,0xc1,0xb1,0xa1]
-
-v_add_nc_u32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x4a]
-
-v_add_nc_u32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x4b]
-
-v_add_nc_u32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x4a]
-
-v_add_nc_u32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x4a,0x56,0x34,0x12,0xaf]
-
-v_add_nc_u32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x4a,0x73,0x72,0x71,0x3f]
-
-v_add_nc_u32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x4a]
-
-v_add_nc_u32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_nc_u32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x25,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_nc_u32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0xff,0x05,0x02,0x00]
-
-v_add_nc_u32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x65,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x6a,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x6b,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x7c,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x7e,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x7f,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x80,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0xc1,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0xf0,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0xf7,0x04,0x02,0x00]
-
-v_add_nc_u32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xff,0x03,0x00]
-
-v_add_nc_u32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x05,0x00,0x00]
-
-v_add_nc_u32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xcb,0x00,0x00]
-
-v_add_nc_u32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xd5,0x00,0x00]
-
-v_add_nc_u32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xd7,0x00,0x00]
-
-v_add_nc_u32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xf9,0x00,0x00]
-
-v_add_nc_u32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xfd,0x00,0x00]
-
-v_add_nc_u32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xff,0x00,0x00]
-
-v_add_nc_u32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x01,0x01,0x00]
-
-v_add_nc_u32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x83,0x01,0x00]
-
-v_add_nc_u32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xe1,0x01,0x00]
-
-v_add_nc_u32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xef,0x01,0x00]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x06]
-
-v_add_nc_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x4b,0x01,0x06,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0xff,0x06,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x86,0x06]
-
-v_add_nc_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x65,0x06,0x86,0x06]
-
-v_add_nc_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x6a,0x06,0x86,0x06]
-
-v_add_nc_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x6b,0x06,0x86,0x06]
-
-v_add_nc_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x7c,0x06,0x86,0x06]
-
-v_add_nc_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x7e,0x06,0x86,0x06]
-
-v_add_nc_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x7f,0x06,0x86,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x4a,0x01,0x06,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x26,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x00,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x01,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x02,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x03,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x04,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x05,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x0e,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x16,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x16,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x00,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x01,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x02,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x03,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x04,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x05,0x06]
-
-v_add_nc_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x0e,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x06]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x00]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x01]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x02]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x03]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x04]
-
-v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x05]
-
-v_add_nc_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x0e]
-
-v_sub_nc_u32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x4d]
-
-v_sub_nc_u32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x4c]
-
-v_sub_nc_u32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x4c,0x56,0x34,0x12,0xaf]
-
-v_sub_nc_u32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x4c,0x73,0x72,0x71,0x3f]
-
-v_sub_nc_u32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x4c]
-
-v_sub_nc_u32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_nc_u32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x26,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0xff,0x05,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x65,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x6a,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x6b,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x7c,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x7e,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x7f,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x80,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0xc1,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0xf0,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0xf7,0x04,0x02,0x00]
-
-v_sub_nc_u32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xff,0x03,0x00]
-
-v_sub_nc_u32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x05,0x00,0x00]
-
-v_sub_nc_u32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xcb,0x00,0x00]
-
-v_sub_nc_u32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xd5,0x00,0x00]
-
-v_sub_nc_u32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xd7,0x00,0x00]
-
-v_sub_nc_u32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xf9,0x00,0x00]
-
-v_sub_nc_u32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xfd,0x00,0x00]
-
-v_sub_nc_u32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xff,0x00,0x00]
-
-v_sub_nc_u32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x01,0x01,0x00]
-
-v_sub_nc_u32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x83,0x01,0x00]
-
-v_sub_nc_u32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xe1,0x01,0x00]
-
-v_sub_nc_u32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xef,0x01,0x00]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_sub_nc_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x4d,0x01,0x06,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0xff,0x06,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x86,0x06]
-
-v_sub_nc_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x65,0x06,0x86,0x06]
-
-v_sub_nc_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x6a,0x06,0x86,0x06]
-
-v_sub_nc_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x6b,0x06,0x86,0x06]
-
-v_sub_nc_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x7c,0x06,0x86,0x06]
-
-v_sub_nc_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x7e,0x06,0x86,0x06]
-
-v_sub_nc_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x7f,0x06,0x86,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x4c,0x01,0x06,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x26,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x00,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x01,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x02,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x03,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x04,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x05,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x0e,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x00,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x01,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x02,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x03,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x04,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x05,0x06]
-
-v_sub_nc_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x0e,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x00]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x01]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x02]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x03]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x04]
-
-v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x05]
-
-v_sub_nc_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x0e]
-
-v_subrev_nc_u32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x4f]
-
-v_subrev_nc_u32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x4e]
-
-v_subrev_nc_u32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x4e,0x56,0x34,0x12,0xaf]
-
-v_subrev_nc_u32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x4e,0x73,0x72,0x71,0x3f]
-
-v_subrev_nc_u32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x4e]
-
-v_subrev_nc_u32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_nc_u32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x27,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0xff,0x05,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x65,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x6a,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x6b,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x7c,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x7e,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x7f,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x80,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0xc1,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0xf0,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0xf7,0x04,0x02,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xff,0x03,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x05,0x00,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xcb,0x00,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xd5,0x00,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xd7,0x00,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xf9,0x00,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xfd,0x00,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xff,0x00,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x01,0x01,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x83,0x01,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xe1,0x01,0x00]
-
-v_subrev_nc_u32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xef,0x01,0x00]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0xff,0x06,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x86,0x06]
-
-v_subrev_nc_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x65,0x06,0x86,0x06]
-
-v_subrev_nc_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x6a,0x06,0x86,0x06]
-
-v_subrev_nc_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x6b,0x06,0x86,0x06]
-
-v_subrev_nc_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x7c,0x06,0x86,0x06]
-
-v_subrev_nc_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x7e,0x06,0x86,0x06]
-
-v_subrev_nc_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x7f,0x06,0x86,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x4e,0x01,0x06,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x26,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x00,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x01,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x02,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x03,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x04,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x05,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x0e,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x00,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x01,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x02,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x03,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x04,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x05,0x06]
-
-v_subrev_nc_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x0e,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x00]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x01]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x02]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x03]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x04]
-
-v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x05]
-
-v_subrev_nc_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x0e]
-
-v_add_co_ci_u32_e32 v5, vcc, v1, v2, vcc
-// W64: encoding: [0x01,0x05,0x0a,0x50]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v255, vcc, v1, v2, vcc
-// W64: encoding: [0x01,0x05,0xfe,0x51]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc, v255, v2, vcc
-// W64: encoding: [0xff,0x05,0x0a,0x50]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc, 0, v2, vcc
-// W64: encoding: [0x80,0x04,0x0a,0x50]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc, -1, v2, vcc
-// W64: encoding: [0xc1,0x04,0x0a,0x50]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc
-// W64: encoding: [0xf0,0x04,0x0a,0x50]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc, -4.0, v2, vcc
-// W64: encoding: [0xf7,0x04,0x0a,0x50]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc, v1, v255, vcc
-// W64: encoding: [0x01,0xff,0x0b,0x50]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// W64: encoding: [0xff,0x0c,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x0e,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[102:103], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x66,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, vcc, v1, v2, s[6:7]
-// W64: encoding: [0x05,0x6a,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0xff,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x80,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0xc1,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0xf0,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0xf7,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xff,0x1b,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x01,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x83,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xe1,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xef,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x22,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], v1, v2, s[102:103]
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x9a,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s[12:13], v1, v2, vcc
-// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0xaa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
-// W32: encoding: [0x01,0x05,0x0a,0x50]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v255, vcc_lo, v1, v2, vcc_lo
-// W32: encoding: [0x01,0x05,0xfe,0x51]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo
-// W32: encoding: [0xff,0x05,0x0a,0x50]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
-// W32: encoding: [0x80,0x04,0x0a,0x50]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo
-// W32: encoding: [0xc1,0x04,0x0a,0x50]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo
-// W32: encoding: [0xf0,0x04,0x0a,0x50]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc_lo, -4.0, v2, vcc_lo
-// W32: encoding: [0xf7,0x04,0x0a,0x50]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e32 v5, vcc_lo, v1, v255, vcc_lo
-// W32: encoding: [0x01,0xff,0x0b,0x50]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_e64 v5, s12, v1, v2, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v255, s12, v1, v2, s6
-// W32: encoding: [0xff,0x0c,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s14, v1, v2, s6
-// W32: encoding: [0x05,0x0e,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s102, v1, v2, s6
-// W32: encoding: [0x05,0x66,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, vcc_lo, v1, v2, s6
-// W32: encoding: [0x05,0x6a,0x28,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, v255, v2, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0xff,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, 0, v2, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x80,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, -1, v2, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0xc1,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, 0.5, v2, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0xf0,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, -4.0, v2, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0xf7,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, v1, v255, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xff,0x1b,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, v1, 0, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x01,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, v1, -1, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x83,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, v1, 0.5, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xe1,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, v1, -4.0, s6
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xef,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, v1, v2, s8
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x22,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, v1, v2, s102
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x9a,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_e64 v5, s12, v1, v2, vcc_lo
-// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0xaa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x26,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x01,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x02,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x03,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x04,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x05,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x0e,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v255, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v255, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v255, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x26,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x01,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x02,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x03,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x04,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x05,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x0e,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, sext(v1), v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_add_co_ci_u32_sdwa v5, vcc_lo, v1, sext(v2), vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc, v1, v2, vcc
-// W64: encoding: [0x01,0x05,0x0a,0x52]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v255, vcc, v1, v2, vcc
-// W64: encoding: [0x01,0x05,0xfe,0x53]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc, v255, v2, vcc
-// W64: encoding: [0xff,0x05,0x0a,0x52]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc, 0, v2, vcc
-// W64: encoding: [0x80,0x04,0x0a,0x52]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc, -1, v2, vcc
-// W64: encoding: [0xc1,0x04,0x0a,0x52]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc
-// W64: encoding: [0xf0,0x04,0x0a,0x52]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc, -4.0, v2, vcc
-// W64: encoding: [0xf7,0x04,0x0a,0x52]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc, v1, v255, vcc
-// W64: encoding: [0x01,0xff,0x0b,0x52]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// W64: encoding: [0xff,0x0c,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x0e,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[102:103], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x66,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, vcc, v1, v2, s[6:7]
-// W64: encoding: [0x05,0x6a,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0xff,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x80,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0xc1,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0xf0,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0xf7,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xff,0x1b,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x01,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x83,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xe1,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xef,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x22,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v1, v2, s[102:103]
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x9a,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s[12:13], v1, v2, vcc
-// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0xaa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
-// W32: encoding: [0x01,0x05,0x0a,0x52]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v255, vcc_lo, v1, v2, vcc_lo
-// W32: encoding: [0x01,0x05,0xfe,0x53]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo
-// W32: encoding: [0xff,0x05,0x0a,0x52]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
-// W32: encoding: [0x80,0x04,0x0a,0x52]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo
-// W32: encoding: [0xc1,0x04,0x0a,0x52]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo
-// W32: encoding: [0xf0,0x04,0x0a,0x52]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc_lo, -4.0, v2, vcc_lo
-// W32: encoding: [0xf7,0x04,0x0a,0x52]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v255, vcc_lo
-// W32: encoding: [0x01,0xff,0x0b,0x52]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_e64 v5, s12, v1, v2, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v255, s12, v1, v2, s6
-// W32: encoding: [0xff,0x0c,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s14, v1, v2, s6
-// W32: encoding: [0x05,0x0e,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s102, v1, v2, s6
-// W32: encoding: [0x05,0x66,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, vcc_lo, v1, v2, s6
-// W32: encoding: [0x05,0x6a,0x29,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, v255, v2, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0xff,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, 0, v2, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x80,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, -1, v2, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0xc1,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, 0.5, v2, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0xf0,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, -4.0, v2, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0xf7,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, v1, v255, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xff,0x1b,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, v1, 0, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x01,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, v1, -1, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x83,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, v1, 0.5, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xe1,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, v1, -4.0, s6
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xef,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, v1, v2, s8
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x22,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, v1, v2, s102
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x9a,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_e64 v5, s12, v1, v2, vcc_lo
-// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0xaa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x26,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x01,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x02,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x03,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x04,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x05,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x0e,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v255, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v255, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v255, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x26,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x01,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x02,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x03,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x04,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x05,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x0e,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, sext(v1), v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, sext(v2), vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc, v1, v2, vcc
-// W64: encoding: [0x01,0x05,0x0a,0x54]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v255, vcc, v1, v2, vcc
-// W64: encoding: [0x01,0x05,0xfe,0x55]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc, v255, v2, vcc
-// W64: encoding: [0xff,0x05,0x0a,0x54]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc, 0, v2, vcc
-// W64: encoding: [0x80,0x04,0x0a,0x54]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc, -1, v2, vcc
-// W64: encoding: [0xc1,0x04,0x0a,0x54]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc
-// W64: encoding: [0xf0,0x04,0x0a,0x54]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc, -4.0, v2, vcc
-// W64: encoding: [0xf7,0x04,0x0a,0x54]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc, v1, v255, vcc
-// W64: encoding: [0x01,0xff,0x0b,0x54]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// W64: encoding: [0xff,0x0c,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x0e,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[102:103], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x66,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, vcc, v1, v2, s[6:7]
-// W64: encoding: [0x05,0x6a,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0xff,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x80,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0xc1,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0xf0,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0xf7,0x04,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xff,0x1b,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x01,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x83,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xe1,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xef,0x19,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x22,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v2, s[102:103]
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x9a,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v2, vcc
-// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0xaa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
-// W32: encoding: [0x01,0x05,0x0a,0x54]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v255, vcc_lo, v1, v2, vcc_lo
-// W32: encoding: [0x01,0x05,0xfe,0x55]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo
-// W32: encoding: [0xff,0x05,0x0a,0x54]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
-// W32: encoding: [0x80,0x04,0x0a,0x54]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo
-// W32: encoding: [0xc1,0x04,0x0a,0x54]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo
-// W32: encoding: [0xf0,0x04,0x0a,0x54]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc_lo, -4.0, v2, vcc_lo
-// W32: encoding: [0xf7,0x04,0x0a,0x54]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e32 v5, vcc_lo, v1, v255, vcc_lo
-// W32: encoding: [0x01,0xff,0x0b,0x54]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_e64 v5, s12, v1, v2, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v255, s12, v1, v2, s6
-// W32: encoding: [0xff,0x0c,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s14, v1, v2, s6
-// W32: encoding: [0x05,0x0e,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s102, v1, v2, s6
-// W32: encoding: [0x05,0x66,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, vcc_lo, v1, v2, s6
-// W32: encoding: [0x05,0x6a,0x2a,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, v255, v2, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0xff,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, 0, v2, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x80,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, -1, v2, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0xc1,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, 0.5, v2, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0xf0,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, -4.0, v2, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0xf7,0x04,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, v1, v255, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xff,0x1b,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, v1, 0, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x01,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, v1, -1, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x83,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, v1, 0.5, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xe1,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, v1, -4.0, s6
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xef,0x19,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, v1, v2, s8
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x22,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, v1, v2, s102
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x9a,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_e64 v5, s12, v1, v2, vcc_lo
-// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0xaa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x26,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x01,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x02,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x03,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x04,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x05,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x0e,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v255, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v255, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v255, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x26,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x01,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x02,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x03,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x04,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x05,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x0e,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, sext(v1), v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, sext(v2), vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_fmac_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x56]
-
-v_fmac_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x57]
-
-v_fmac_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x56]
-
-v_fmac_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x56]
-
-v_fmac_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x56,0x56,0x34,0x12,0xaf]
-
-v_fmac_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x56,0x73,0x72,0x71,0x3f]
-
-v_fmac_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x56]
-
-v_fmac_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0xff,0x05,0x02,0x00]
-
-v_fmac_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x65,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x6a,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x6b,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x7c,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x7e,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x7f,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x80,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0xc1,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0xf0,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0xf7,0x04,0x02,0x00]
-
-v_fmac_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xff,0x03,0x00]
-
-v_fmac_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x00,0x00]
-
-v_fmac_f32_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xcb,0x00,0x00]
-
-v_fmac_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xd5,0x00,0x00]
-
-v_fmac_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xd7,0x00,0x00]
-
-v_fmac_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xf9,0x00,0x00]
-
-v_fmac_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xfd,0x00,0x00]
-
-v_fmac_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xff,0x00,0x00]
-
-v_fmac_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x01,0x01,0x00]
-
-v_fmac_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x83,0x01,0x00]
-
-v_fmac_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xe1,0x01,0x00]
-
-v_fmac_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xef,0x01,0x00]
-
-v_fmac_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x20]
-
-v_fmac_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x40]
-
-v_fmac_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x60]
-
-v_fmac_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x2b,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x2b,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x2b,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f32_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x2b,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f32_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x08]
-
-v_fmac_f32_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x10]
-
-v_fmac_f32_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x18]
-
-v_fmamk_f32 v5, v1, 0x11213141, v3
-// GFX10: encoding: [0x01,0x07,0x0a,0x58,0x41,0x31,0x21,0x11]
-
-v_fmamk_f32 v255, v1, 0x11213141, v3
-// GFX10: encoding: [0x01,0x07,0xfe,0x59,0x41,0x31,0x21,0x11]
-
-v_fmamk_f32 v5, v255, 0x11213141, v3
-// GFX10: encoding: [0xff,0x07,0x0a,0x58,0x41,0x31,0x21,0x11]
-
-v_fmamk_f32 v5, 0, 0x11213141, v3
-// GFX10: encoding: [0x80,0x06,0x0a,0x58,0x41,0x31,0x21,0x11]
-
-v_fmamk_f32 v5, -1, 0x11213141, v3
-// GFX10: encoding: [0xc1,0x06,0x0a,0x58,0x41,0x31,0x21,0x11]
-
-v_fmamk_f32 v5, 0.5, 0x11213141, v3
-// GFX10: encoding: [0xf0,0x06,0x0a,0x58,0x41,0x31,0x21,0x11]
-
-v_fmamk_f32 v5, -4.0, 0x11213141, v3
-// GFX10: encoding: [0xf7,0x06,0x0a,0x58,0x41,0x31,0x21,0x11]
-
-v_fmamk_f32 v5, v1, 0xa1b1c1d1, v3
-// GFX10: encoding: [0x01,0x07,0x0a,0x58,0xd1,0xc1,0xb1,0xa1]
-
-v_fmamk_f32 v5, v1, 0x11213141, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x58,0x41,0x31,0x21,0x11]
-
-v_fmaak_f32 v5, v1, v2, 0x11213141
-// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0x41,0x31,0x21,0x11]
-
-v_fmaak_f32 v255, v1, v2, 0x11213141
-// GFX10: encoding: [0x01,0x05,0xfe,0x5b,0x41,0x31,0x21,0x11]
-
-v_fmaak_f32 v5, v255, v2, 0x11213141
-// GFX10: encoding: [0xff,0x05,0x0a,0x5a,0x41,0x31,0x21,0x11]
-
-v_fmaak_f32 v5, 0, v2, 0x11213141
-// GFX10: encoding: [0x80,0x04,0x0a,0x5a,0x41,0x31,0x21,0x11]
-
-v_fmaak_f32 v5, -1, v2, 0x11213141
-// GFX10: encoding: [0xc1,0x04,0x0a,0x5a,0x41,0x31,0x21,0x11]
-
-v_fmaak_f32 v5, 0.5, v2, 0x11213141
-// GFX10: encoding: [0xf0,0x04,0x0a,0x5a,0x41,0x31,0x21,0x11]
-
-v_fmaak_f32 v5, -4.0, v2, 0x11213141
-// GFX10: encoding: [0xf7,0x04,0x0a,0x5a,0x41,0x31,0x21,0x11]
-
-v_fmaak_f32 v5, v1, v255, 0x11213141
-// GFX10: encoding: [0x01,0xff,0x0b,0x5a,0x41,0x31,0x21,0x11]
-
-v_fmaak_f32 v5, v1, v2, 0xa1b1c1d1
-// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xd1,0xc1,0xb1,0xa1]
-
-v_cvt_pkrtz_f16_f32_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x5f]
-
-v_cvt_pkrtz_f16_f32_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32_e32 v5, 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x5e,0x56,0x34,0x12,0xaf]
-
-v_cvt_pkrtz_f16_f32_e32 v5, 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x5e,0x73,0x72,0x71,0x3f]
-
-v_cvt_pkrtz_f16_f32_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x5e]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x2f,0xd5,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0xff,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x67,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x6a,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x6b,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x77,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x7c,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x7e,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x7f,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x80,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0xc1,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0xf0,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0xf7,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xff,0x03,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xcf,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xd5,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xd7,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xef,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xf9,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xfd,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xff,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x01,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x83,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xe1,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xef,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x20]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x40]
-
-v_cvt_pkrtz_f16_f32_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x60]
-
-v_cvt_pkrtz_f16_f32_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x2f,0xd5,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x2f,0xd5,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x2f,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f16_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x64]
-
-v_add_f16_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x65]
-
-v_add_f16_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x64]
-
-v_add_f16_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x64]
-
-v_add_f16_e32 v5, 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x64,0x0b,0xfe,0x00,0x00]
-
-v_add_f16_e32 v5, 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x64,0x56,0x34,0x00,0x00]
-
-v_add_f16_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x64]
-
-v_add_f16_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x32,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0xff,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x65,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x6a,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x6b,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x7c,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x7e,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x7f,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x80,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0xc1,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0xf0,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0xf7,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xff,0x03,0x00]
-
-v_add_f16_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x00,0x00]
-
-v_add_f16_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xcb,0x00,0x00]
-
-v_add_f16_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xd5,0x00,0x00]
-
-v_add_f16_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xd7,0x00,0x00]
-
-v_add_f16_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xf9,0x00,0x00]
-
-v_add_f16_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xfd,0x00,0x00]
-
-v_add_f16_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xff,0x00,0x00]
-
-v_add_f16_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x01,0x01,0x00]
-
-v_add_f16_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x83,0x01,0x00]
-
-v_add_f16_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xe1,0x01,0x00]
-
-v_add_f16_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xef,0x01,0x00]
-
-v_add_f16_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x20]
-
-v_add_f16_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x40]
-
-v_add_f16_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x60]
-
-v_add_f16_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x32,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x32,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x32,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x32,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0xff,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x65,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x6a,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x6b,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x7c,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x7e,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x7f,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x64,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x26,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x00,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x01,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x02,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x03,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x04,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x05,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x0e,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x00,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x01,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x02,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x03,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x04,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x05,0x06]
-
-v_add_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x16,0x06]
-
-v_add_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x26,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x00]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x01]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x02]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x03]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x04]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x05]
-
-v_add_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x16]
-
-v_add_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x26]
-
-v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x00]
-
-v_add_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00]
-
-v_add_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0xff,0xe4,0x00,0x00]
-
-v_add_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x64,0x01,0xe4,0x00,0x00]
-
-v_add_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x10]
-
-v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x30]
-
-v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
-
-v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01]
-
-v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
-
-v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
-
-v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
-
-v_add_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x10,0x00]
-
-v_add_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x20,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x51,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x61,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x6f,0x01,0x00]
-
-v_sub_f16_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x66]
-
-v_sub_f16_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x67]
-
-v_sub_f16_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x66]
-
-v_sub_f16_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x66]
-
-v_sub_f16_e32 v5, 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x66,0x0b,0xfe,0x00,0x00]
-
-v_sub_f16_e32 v5, 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x66,0x56,0x34,0x00,0x00]
-
-v_sub_f16_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x66]
-
-v_sub_f16_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x33,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0xff,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x65,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x6a,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x6b,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x7c,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x7e,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x7f,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x80,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0xc1,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0xf0,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0xf7,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xff,0x03,0x00]
-
-v_sub_f16_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xcb,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xd5,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xd7,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xf9,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xfd,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xff,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x01,0x01,0x00]
-
-v_sub_f16_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x83,0x01,0x00]
-
-v_sub_f16_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xe1,0x01,0x00]
-
-v_sub_f16_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xef,0x01,0x00]
-
-v_sub_f16_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x20]
-
-v_sub_f16_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x40]
-
-v_sub_f16_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x60]
-
-v_sub_f16_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x33,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x33,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x33,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x33,0xd5,0x01,0x05,0x02,0x00]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0xff,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x65,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x6a,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x6b,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x7c,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x7e,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x7f,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x66,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x26,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x00,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x01,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x02,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x03,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x04,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x05,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x0e,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x00,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x01,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x02,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x03,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x04,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x05,0x06]
-
-v_sub_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x16,0x06]
-
-v_sub_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x26,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x00]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x01]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x02]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x03]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x04]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x05]
-
-v_sub_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x16]
-
-v_sub_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x26]
-
-v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0xff,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x66,0x01,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x10]
-
-v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x30]
-
-v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
-
-v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01]
-
-v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
-
-v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
-
-v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
-
-v_sub_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
-
-v_sub_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x51,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x61,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x6f,0x01,0x00]
-
-v_subrev_f16_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x68]
-
-v_subrev_f16_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x69]
-
-v_subrev_f16_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x68]
-
-v_subrev_f16_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x68]
-
-v_subrev_f16_e32 v5, 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x68,0x0b,0xfe,0x00,0x00]
-
-v_subrev_f16_e32 v5, 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x68,0x56,0x34,0x00,0x00]
-
-v_subrev_f16_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x68]
-
-v_subrev_f16_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0xff,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x65,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x6a,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x6b,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x7c,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x7e,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x7f,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x80,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0xc1,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0xf0,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0xf7,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x03,0x00]
-
-v_subrev_f16_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xcb,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xd5,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xd7,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xf9,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xfd,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x01,0x01,0x00]
-
-v_subrev_f16_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x83,0x01,0x00]
-
-v_subrev_f16_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xe1,0x01,0x00]
-
-v_subrev_f16_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xef,0x01,0x00]
-
-v_subrev_f16_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x20]
-
-v_subrev_f16_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x40]
-
-v_subrev_f16_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x60]
-
-v_subrev_f16_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x34,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x34,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x34,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x34,0xd5,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x69,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0xff,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x65,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x6a,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x6b,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x7c,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x7e,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x7f,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x68,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x26,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x00,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x01,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x02,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x03,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x04,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x05,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x0e,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x16,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x16,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x00,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x01,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x02,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x03,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x04,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x05,0x06]
-
-v_subrev_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x16,0x06]
-
-v_subrev_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x26,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x00]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x01]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x02]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x03]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x04]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x05]
-
-v_subrev_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x16]
-
-v_subrev_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x26]
-
-v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x69,0x01,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0xff,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x68,0x01,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x10]
-
-v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x30]
-
-v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x01]
-
-v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x03]
-
-v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00]
-
-v_subrev_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x10,0x00]
-
-v_subrev_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x20,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x51,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x61,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x6f,0x01,0x00]
-
-v_mul_f16_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x6a]
-
-v_mul_f16_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x6b]
-
-v_mul_f16_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x6a]
-
-v_mul_f16_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x6a]
-
-v_mul_f16_e32 v5, 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x6a,0x0b,0xfe,0x00,0x00]
-
-v_mul_f16_e32 v5, 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x6a,0x56,0x34,0x00,0x00]
-
-v_mul_f16_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x6a]
-
-v_mul_f16_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x65,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_f16_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xcb,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_f16_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_f16_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_f16_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_f16_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x20]
-
-v_mul_f16_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x40]
-
-v_mul_f16_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x60]
-
-v_mul_f16_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x35,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x35,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x35,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x35,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x6b,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0xff,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x65,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x6a,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x6b,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x7c,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x7e,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x7f,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x6a,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x26,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x00,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x01,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x02,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x03,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x04,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x05,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x0e,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x16,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x16,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x00,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x01,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x02,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x03,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x04,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x05,0x06]
-
-v_mul_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x16,0x06]
-
-v_mul_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x26,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x00]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x01]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x02]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x03]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x04]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x05]
-
-v_mul_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x16]
-
-v_mul_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x26]
-
-v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x6b,0x01,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0xff,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x6a,0x01,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x10]
-
-v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x30]
-
-v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xf0]
-
-v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x01]
-
-v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x03]
-
-v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x0f]
-
-v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00]
-
-v_mul_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x10,0x00]
-
-v_mul_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x20,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x51,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x61,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x6f,0x01,0x00]
-
-v_fmac_f16_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x6c]
-
-v_fmac_f16_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x6d]
-
-v_fmac_f16_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x6c]
-
-v_fmac_f16_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x6c]
-
-v_fmac_f16 v5, 0x1234, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x6c,0x34,0x12,0x00,0x00]
-
-v_fmac_f16_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x6c]
-
-v_fmac_f16_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f16_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f16_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0xff,0x05,0x02,0x00]
-
-v_fmac_f16_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x65,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x6a,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x6b,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x7c,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x7e,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x7f,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x80,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0xc1,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0xf0,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0xf7,0x04,0x02,0x00]
-
-v_fmac_f16_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xff,0x03,0x00]
-
-v_fmac_f16_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x00,0x00]
-
-v_fmac_f16_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xcb,0x00,0x00]
-
-v_fmac_f16_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xd5,0x00,0x00]
-
-v_fmac_f16_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xd7,0x00,0x00]
-
-v_fmac_f16_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xf9,0x00,0x00]
-
-v_fmac_f16_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xfd,0x00,0x00]
-
-v_fmac_f16_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xff,0x00,0x00]
-
-v_fmac_f16_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x01,0x01,0x00]
-
-v_fmac_f16_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x83,0x01,0x00]
-
-v_fmac_f16_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xe1,0x01,0x00]
-
-v_fmac_f16_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xef,0x01,0x00]
-
-v_fmac_f16_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x20]
-
-v_fmac_f16_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x40]
-
-v_fmac_f16_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x60]
-
-v_fmac_f16_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x36,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f16_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x36,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f16_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x36,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f16_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x36,0xd5,0x01,0x05,0x02,0x00]
-
-v_fmac_f16_e64 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x08]
-
-v_fmac_f16_e64 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x10]
-
-v_fmac_f16_e64 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x18]
-
-v_fmamk_f32 v5, v1, 0x1121, v3
-// GFX10: encoding: [0x01,0x07,0x0a,0x58,0x21,0x11,0x00,0x00]
-
-v_fmamk_f32 v255, v1, 0x1121, v3
-// GFX10: encoding: [0x01,0x07,0xfe,0x59,0x21,0x11,0x00,0x00]
-
-v_fmamk_f32 v5, v255, 0x1121, v3
-// GFX10: encoding: [0xff,0x07,0x0a,0x58,0x21,0x11,0x00,0x00]
-
-v_fmamk_f32 v5, 0, 0x1121, v3
-// GFX10: encoding: [0x80,0x06,0x0a,0x58,0x21,0x11,0x00,0x00]
-
-v_fmamk_f32 v5, -1, 0x1121, v3
-// GFX10: encoding: [0xc1,0x06,0x0a,0x58,0x21,0x11,0x00,0x00]
-
-v_fmamk_f32 v5, 0.5, 0x1121, v3
-// GFX10: encoding: [0xf0,0x06,0x0a,0x58,0x21,0x11,0x00,0x00]
-
-v_fmamk_f32 v5, -4.0, 0x1121, v3
-// GFX10: encoding: [0xf7,0x06,0x0a,0x58,0x21,0x11,0x00,0x00]
-
-v_fmamk_f32 v5, v1, 0xa1b1, v3
-// GFX10: encoding: [0x01,0x07,0x0a,0x58,0xb1,0xa1,0x00,0x00]
-
-v_fmamk_f32 v5, v1, 0x1121, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x58,0x21,0x11,0x00,0x00]
-
-v_fmaak_f32 v5, v1, v2, 0x1121
-// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0x21,0x11,0x00,0x00]
-
-v_fmaak_f32 v255, v1, v2, 0x1121
-// GFX10: encoding: [0x01,0x05,0xfe,0x5b,0x21,0x11,0x00,0x00]
-
-v_fmaak_f32 v5, v255, v2, 0x1121
-// GFX10: encoding: [0xff,0x05,0x0a,0x5a,0x21,0x11,0x00,0x00]
-
-v_fmaak_f32 v5, 0, v2, 0x1121
-// GFX10: encoding: [0x80,0x04,0x0a,0x5a,0x21,0x11,0x00,0x00]
-
-v_fmaak_f32 v5, -1, v2, 0x1121
-// GFX10: encoding: [0xc1,0x04,0x0a,0x5a,0x21,0x11,0x00,0x00]
-
-v_fmaak_f32 v5, 0.5, v2, 0x1121
-// GFX10: encoding: [0xf0,0x04,0x0a,0x5a,0x21,0x11,0x00,0x00]
-
-v_fmaak_f32 v5, -4.0, v2, 0x1121
-// GFX10: encoding: [0xf7,0x04,0x0a,0x5a,0x21,0x11,0x00,0x00]
-
-v_fmaak_f32 v5, v1, v255, 0x1121
-// GFX10: encoding: [0x01,0xff,0x0b,0x5a,0x21,0x11,0x00,0x00]
-
-v_fmaak_f32 v5, v1, v2, 0xa1b1
-// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xb1,0xa1,0x00,0x00]
-
-v_max_f16_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x72]
-
-v_max_f16_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x73]
-
-v_max_f16_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x72]
-
-v_max_f16_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x72]
-
-v_max_f16_e32 v5, 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x72,0x0b,0xfe,0x00,0x00]
-
-v_max_f16_e32 v5, 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x72,0x56,0x34,0x00,0x00]
-
-v_max_f16_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x72]
-
-v_max_f16_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x39,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0xff,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x65,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x6a,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x6b,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x7c,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x7e,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x7f,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x80,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0xc1,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0xf0,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0xf7,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xff,0x03,0x00]
-
-v_max_f16_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x00,0x00]
-
-v_max_f16_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xcb,0x00,0x00]
-
-v_max_f16_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xd5,0x00,0x00]
-
-v_max_f16_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xd7,0x00,0x00]
-
-v_max_f16_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xf9,0x00,0x00]
-
-v_max_f16_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xfd,0x00,0x00]
-
-v_max_f16_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xff,0x00,0x00]
-
-v_max_f16_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x01,0x01,0x00]
-
-v_max_f16_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x83,0x01,0x00]
-
-v_max_f16_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xe1,0x01,0x00]
-
-v_max_f16_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xef,0x01,0x00]
-
-v_max_f16_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x02,0x20]
-
-v_max_f16_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x02,0x40]
-
-v_max_f16_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x02,0x60]
-
-v_max_f16_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x39,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x39,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x39,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x39,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x73,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0xff,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x65,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x6a,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x6b,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x7c,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x7e,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x7f,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x72,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x26,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x00,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x01,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x02,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x03,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x04,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x05,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x0e,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x16,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x16,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x00,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x01,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x02,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x03,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x04,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x05,0x06]
-
-v_max_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x16,0x06]
-
-v_max_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x26,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x00]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x01]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x02]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x03]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x04]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x05]
-
-v_max_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x16]
-
-v_max_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x26]
-
-v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x00]
-
-v_max_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x73,0x01,0xe4,0x00,0x00]
-
-v_max_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0xff,0xe4,0x00,0x00]
-
-v_max_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x72,0x01,0xe4,0x00,0x00]
-
-v_max_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x40,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x41,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x01,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x0f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x11,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x21,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x2f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x10]
-
-v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x30]
-
-v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xf0]
-
-v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x01]
-
-v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x03]
-
-v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x0f]
-
-v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x08,0x00]
-
-v_max_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x10,0x00]
-
-v_max_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x20,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x51,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x5f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x61,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x6f,0x01,0x00]
-
-v_min_f16_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x74]
-
-v_min_f16_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x75]
-
-v_min_f16_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x74]
-
-v_min_f16_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x74]
-
-v_min_f16_e32 v5, 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x74,0x0b,0xfe,0x00,0x00]
-
-v_min_f16_e32 v5, 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x74,0x56,0x34,0x00,0x00]
-
-v_min_f16_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x74]
-
-v_min_f16_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x3a,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0xff,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x65,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x6a,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x6b,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x7c,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x7e,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x7f,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x80,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0xc1,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0xf0,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0xf7,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xff,0x03,0x00]
-
-v_min_f16_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x00,0x00]
-
-v_min_f16_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xcb,0x00,0x00]
-
-v_min_f16_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xd5,0x00,0x00]
-
-v_min_f16_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xd7,0x00,0x00]
-
-v_min_f16_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xf9,0x00,0x00]
-
-v_min_f16_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xfd,0x00,0x00]
-
-v_min_f16_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xff,0x00,0x00]
-
-v_min_f16_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x01,0x01,0x00]
-
-v_min_f16_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x83,0x01,0x00]
-
-v_min_f16_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xe1,0x01,0x00]
-
-v_min_f16_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xef,0x01,0x00]
-
-v_min_f16_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x02,0x20]
-
-v_min_f16_e64 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x02,0x40]
-
-v_min_f16_e64 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x02,0x60]
-
-v_min_f16_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x3a,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x3a,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x3a,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x3a,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x75,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0xff,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x65,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x6a,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x6b,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x7c,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x7e,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x7f,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x74,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x26,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x00,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x01,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x02,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x03,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x04,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x05,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x0e,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x16,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x16,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x00,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x01,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x02,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x03,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x04,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x05,0x06]
-
-v_min_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x16,0x06]
-
-v_min_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x26,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x00]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x01]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x02]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x03]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x04]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x05]
-
-v_min_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x16]
-
-v_min_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x26]
-
-v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x00]
-
-v_min_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x75,0x01,0xe4,0x00,0x00]
-
-v_min_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0xff,0xe4,0x00,0x00]
-
-v_min_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x74,0x01,0xe4,0x00,0x00]
-
-v_min_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x40,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x41,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x01,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x0f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x11,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x21,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x2f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x10]
-
-v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x30]
-
-v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xf0]
-
-v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x01]
-
-v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x03]
-
-v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f]
-
-v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
-
-v_min_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x10,0x00]
-
-v_min_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x20,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x51,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x5f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x61,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x6f,0x01,0x00]
-
-v_ldexp_f16_e32 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x76]
-
-v_ldexp_f16_e32 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x77]
-
-v_ldexp_f16_e32 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, s101, v2
-// GFX10: encoding: [0x65,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x76]
-
-v_ldexp_f16_e32 v5, 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x76,0x0b,0xfe,0x00,0x00]
-
-v_ldexp_f16_e32 v5, 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x0a,0x76,0x56,0x34,0x00,0x00]
-
-v_ldexp_f16_e32 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x76]
-
-v_ldexp_f16_e64 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x3b,0xd5,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0xff,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x65,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x6b,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x7c,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x7f,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x80,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xff,0x03,0x00]
-
-v_ldexp_f16_e64 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x05,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xcb,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xff,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x01,0x01,0x00]
-
-v_ldexp_f16_e64 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x83,0x01,0x00]
-
-v_ldexp_f16_e64 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f16_e64 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xef,0x01,0x00]
-
-v_ldexp_f16_e64 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x05,0x02,0x20]
-
-v_ldexp_f16_e64 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x3b,0xd5,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x3b,0xd5,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x77,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0xff,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x65,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x6a,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x6b,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x7c,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x7e,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x7f,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x0b,0x76,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x26,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x00,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x01,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x02,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x03,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x04,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x05,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x0e,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x16,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x16,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x00,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x01,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x02,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x03,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x04,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x05,0x06]
-
-v_ldexp_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x16,0x06]
-
-v_ldexp_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x26,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x00]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x01]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x02]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x03]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x04]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x05]
-
-v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0xfe,0x77,0x01,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0xff,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0xfe,0x0b,0x76,0x01,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x10]
-
-v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x30]
-
-v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xf0]
-
-v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x01]
-
-v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x03]
-
-v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x0f]
-
-v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x08,0x00]
-
-v_ldexp_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x10,0x00]
-
-v_ldexp_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x20,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x51,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x61,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
-// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x6f,0x01,0x00]
-
-//===----------------------------------------------------------------------===//
-// ENC_VOP3.
-//===----------------------------------------------------------------------===//
-
-v_readlane_b32 s5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 s101, v1, s2
-// GFX10: encoding: [0x65,0x00,0x60,0xd7,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 s5, v255, s2
-// GFX10: encoding: [0x05,0x00,0x60,0xd7,0xff,0x05,0x00,0x00]
-
-v_readlane_b32 s5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0xcb,0x00,0x00]
-
-v_readlane_b32 s5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0xd5,0x00,0x00]
-
-v_readlane_b32 s5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0xd7,0x00,0x00]
-
-v_readlane_b32 s5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0xf9,0x00,0x00]
-
-v_readlane_b32 s5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0x01,0x01,0x00]
-
-v_writelane_b32 v5, 0, s2
-// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
-
-v_writelane_b32 v255, 0, s2
-// GFX10: encoding: [0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
-
-v_writelane_b32 v5, -1, s2
-// GFX10: encoding: [0x05,0x00,0x61,0xd7,0xc1,0x04,0x00,0x00]
-
-v_writelane_b32 v5, 0.5, s2
-// GFX10: encoding: [0x05,0x00,0x61,0xd7,0xf0,0x04,0x00,0x00]
-
-v_writelane_b32 v5, -4.0, s2
-// GFX10: encoding: [0x05,0x00,0x61,0xd7,0xf7,0x04,0x00,0x00]
-
-v_writelane_b32 v5, 0, s101
-// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0xca,0x00,0x00]
-
-v_writelane_b32 v5, 0, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0xd4,0x00,0x00]
-
-v_writelane_b32 v5, 0, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0xd6,0x00,0x00]
-
-v_writelane_b32 v5, 0, m0
-// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0xf8,0x00,0x00]
-
-v_writelane_b32 v5, 0, 0
-// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0x00,0x01,0x00]
-
-v_bfm_b32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
-
-v_bfm_b32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
-
-v_bfm_b32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0xff,0x05,0x02,0x00]
-
-v_bfm_b32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x04,0x02,0x00]
-
-v_bfm_b32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x67,0x04,0x02,0x00]
-
-v_bfm_b32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x6a,0x04,0x02,0x00]
-
-v_bfm_b32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x6b,0x04,0x02,0x00]
-
-v_bfm_b32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x77,0x04,0x02,0x00]
-
-v_bfm_b32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x7c,0x04,0x02,0x00]
-
-v_bfm_b32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x7e,0x04,0x02,0x00]
-
-v_bfm_b32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x7f,0x04,0x02,0x00]
-
-v_bfm_b32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x80,0x04,0x02,0x00]
-
-v_bfm_b32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0xc1,0x04,0x02,0x00]
-
-v_bfm_b32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0xf0,0x04,0x02,0x00]
-
-v_bfm_b32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0xf7,0x04,0x02,0x00]
-
-v_bfm_b32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xff,0x03,0x00]
-
-v_bfm_b32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x00,0x00]
-
-v_bfm_b32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xcf,0x00,0x00]
-
-v_bfm_b32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xd5,0x00,0x00]
-
-v_bfm_b32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xd7,0x00,0x00]
-
-v_bfm_b32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xef,0x00,0x00]
-
-v_bfm_b32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xf9,0x00,0x00]
-
-v_bfm_b32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xfd,0x00,0x00]
-
-v_bfm_b32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xff,0x00,0x00]
-
-v_bfm_b32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x01,0x01,0x00]
-
-v_bfm_b32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x83,0x01,0x00]
-
-v_bfm_b32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xe1,0x01,0x00]
-
-v_bfm_b32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xef,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
-
-v_bcnt_u32_b32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
-
-v_bcnt_u32_b32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0xff,0x05,0x02,0x00]
-
-v_bcnt_u32_b32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x67,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x6a,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x6b,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x77,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x7c,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x7e,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x7f,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x80,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0xc1,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0xf0,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0xf7,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xff,0x03,0x00]
-
-v_bcnt_u32_b32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xcf,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xd5,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xd7,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xef,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xf9,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xfd,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xff,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x01,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x83,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xe1,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xef,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x65,0xd7,0x01,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0xff,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x67,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x6a,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x6b,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x77,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x7c,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x7e,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x7f,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x80,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0xc1,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0xf0,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0xf7,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xff,0x03,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xcf,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xd5,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xd7,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xef,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xf9,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xfd,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xff,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x01,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x83,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xe1,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xef,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x66,0xd7,0x01,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0xff,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x67,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x6a,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x6b,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x77,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x7c,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x7e,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x7f,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x80,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0xc1,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0xf0,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0xf7,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xff,0x03,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xcf,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xd5,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xd7,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xef,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xf9,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xfd,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xff,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x01,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x83,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xe1,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xef,0x01,0x00]
-
-v_add_co_u32 v5, s0, v1, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v255, s0, v1, v2
-// W32: encoding: [0xff,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v255, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, s1, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, s103, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x67,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, vcc_lo, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, vcc_hi, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, ttmp11, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x77,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, m0, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, exec_lo, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, exec_hi, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, 0, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, -1, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, 0.5, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, -4.0, v2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, v255
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, s2
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, s103
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xcf,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, vcc_lo
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, vcc_hi
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, ttmp11
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, m0
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, exec_lo
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, exec_hi
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, 0
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, -1
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, 0.5
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s0, v1, -4.0
-// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v255, s[0:1], v1, v2
-// W64: encoding: [0xff,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v255, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], s1, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], s103, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x67,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], vcc_lo, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], vcc_hi, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], ttmp11, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x77,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], m0, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], exec_lo, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], exec_hi, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], 0, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], -1, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], 0.5, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], -4.0, v2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, v255
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, s2
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, s103
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xcf,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, vcc_lo
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, vcc_hi
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, ttmp11
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, m0
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, exec_lo
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, exec_hi
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, 0
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, -1
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, 0.5
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_add_co_u32 v5, s[0:1], v1, -4.0
-// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v255, s0, v1, v2
-// W32: encoding: [0xff,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v255, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, s1, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, s103, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x67,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, vcc_lo, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, vcc_hi, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, ttmp11, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x77,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, m0, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, exec_lo, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, exec_hi, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, 0, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, -1, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, 0.5, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, -4.0, v2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, v255
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, s2
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, s103
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xcf,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, vcc_lo
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, vcc_hi
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, ttmp11
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, m0
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, exec_lo
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, exec_hi
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, 0
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, -1
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, 0.5
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s0, v1, -4.0
-// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v255, s[0:1], v1, v2
-// W64: encoding: [0xff,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v255, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], s1, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], s103, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x67,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], vcc_lo, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], vcc_hi, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], ttmp11, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x77,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], m0, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], exec_lo, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], exec_hi, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], 0, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], -1, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], 0.5, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], -4.0, v2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, v255
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, s2
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, s103
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xcf,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, vcc_lo
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, vcc_hi
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, ttmp11
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, m0
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, exec_lo
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, exec_hi
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, 0
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, -1
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, 0.5
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_sub_co_u32 v5, s[0:1], v1, -4.0
-// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v255, s0, v1, v2
-// W32: encoding: [0xff,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v255, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, s1, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, s103, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x67,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, vcc_lo, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, vcc_hi, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, ttmp11, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x77,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, m0, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, exec_lo, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, exec_hi, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, 0, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, -1, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, 0.5, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, -4.0, v2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, v255
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, s2
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, s103
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xcf,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, vcc_lo
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, vcc_hi
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, ttmp11
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, m0
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, exec_lo
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, exec_hi
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, 0
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, -1
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, 0.5
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s0, v1, -4.0
-// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v255, s[0:1], v1, v2
-// W64: encoding: [0xff,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v255, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], s1, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], s103, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x67,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], vcc_lo, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], vcc_hi, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], ttmp11, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x77,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], m0, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], exec_lo, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], exec_hi, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], 0, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], -1, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], 0.5, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], -4.0, v2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, v255
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, s2
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, s103
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xcf,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, vcc_lo
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, vcc_hi
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, ttmp11
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, m0
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, exec_lo
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, exec_hi
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, 0
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, -1
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, 0.5
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_subrev_co_u32 v5, s[0:1], v1, -4.0
-// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_ldexp_f32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0xff,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x67,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x6b,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x77,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x7c,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x7f,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x80,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xff,0x03,0x00]
-
-v_ldexp_f32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x00,0x00]
-
-v_ldexp_f32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xef,0x00,0x00]
-
-v_ldexp_f32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xff,0x00,0x00]
-
-v_ldexp_f32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x01,0x01,0x00]
-
-v_ldexp_f32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x83,0x01,0x00]
-
-v_ldexp_f32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xef,0x01,0x00]
-
-v_ldexp_f32 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x20]
-
-v_ldexp_f32 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x62,0xd7,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x62,0xd7,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, v1, v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x08]
-
-v_ldexp_f32 v5, v1, v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x10]
-
-v_ldexp_f32 v5, v1, v2 div:2
-// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x18]
-
-v_cvt_pknorm_i16_f32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x68,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x77,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xef,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_i16_f32 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_i16_f32 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_i16_f32 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x68,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x68,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x68,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x68,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x69,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x77,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xef,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_u16_f32 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_u16_f32 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_u16_f32 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x69,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x69,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x69,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, v2 clamp
-// GFX10: encoding: [0x05,0x80,0x69,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0xff,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x67,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x6a,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x6b,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x77,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x7c,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x7e,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x7f,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x80,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0xc1,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0xf0,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0xf7,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xff,0x03,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x05,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xcf,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xd5,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xd7,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xef,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xf9,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xfd,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xff,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x01,0x01,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x83,0x01,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xe1,0x01,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xef,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0xff,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x67,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x6a,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x6b,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x77,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x7c,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x7e,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x7f,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x80,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0xc1,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0xf0,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0xf7,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xff,0x03,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x05,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xcf,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xd5,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xd7,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xef,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xf9,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xfd,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xff,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x01,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x83,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xe1,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xef,0x01,0x00]
-
-v_mad_legacy_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x40,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0xff,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x67,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x77,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x80,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xff,0x0f,0x04]
-
-v_mad_legacy_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xef,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xff,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x01,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x83,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xef,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xfe,0x07]
-
-v_mad_legacy_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x00]
-
-v_mad_legacy_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x9e,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xaa,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xae,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xde,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xf2,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xfa,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xfe,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x02,0x02]
-
-v_mad_legacy_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x06,0x03]
-
-v_mad_legacy_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xc2,0x03]
-
-v_mad_legacy_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xde,0x03]
-
-v_mad_legacy_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x24]
-
-v_mad_legacy_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x44]
-
-v_mad_legacy_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x84]
-
-v_mad_legacy_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_mad_legacy_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x40,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x40,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x40,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x40,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x40,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_mad_legacy_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x14]
-
-v_mad_legacy_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_mad_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x41,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0xff,0x05,0x0e,0x04]
-
-v_mad_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x04,0x0e,0x04]
-
-v_mad_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x67,0x04,0x0e,0x04]
-
-v_mad_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_mad_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_mad_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x77,0x04,0x0e,0x04]
-
-v_mad_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_mad_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_mad_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_mad_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x80,0x04,0x0e,0x04]
-
-v_mad_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_mad_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_mad_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_mad_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xff,0x0f,0x04]
-
-v_mad_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0c,0x04]
-
-v_mad_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_mad_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_mad_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_mad_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xef,0x0c,0x04]
-
-v_mad_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_mad_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_mad_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xff,0x0c,0x04]
-
-v_mad_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x01,0x0d,0x04]
-
-v_mad_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x83,0x0d,0x04]
-
-v_mad_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_mad_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xef,0x0d,0x04]
-
-v_mad_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xfe,0x07]
-
-v_mad_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x00]
-
-v_mad_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x9e,0x01]
-
-v_mad_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xaa,0x01]
-
-v_mad_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xae,0x01]
-
-v_mad_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xde,0x01]
-
-v_mad_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xf2,0x01]
-
-v_mad_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xfa,0x01]
-
-v_mad_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xfe,0x01]
-
-v_mad_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x02,0x02]
-
-v_mad_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x06,0x03]
-
-v_mad_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xc2,0x03]
-
-v_mad_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xde,0x03]
-
-v_mad_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x24]
-
-v_mad_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x44]
-
-v_mad_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x84]
-
-v_mad_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_mad_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x41,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x41,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x41,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x41,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x41,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_mad_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x14]
-
-v_mad_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_mad_i32_i24 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x42,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0xff,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x67,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x77,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x80,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xff,0x0f,0x04]
-
-v_mad_i32_i24 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xef,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xff,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x01,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x83,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xef,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xfe,0x07]
-
-v_mad_i32_i24 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x0e,0x00]
-
-v_mad_i32_i24 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x9e,0x01]
-
-v_mad_i32_i24 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xaa,0x01]
-
-v_mad_i32_i24 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xae,0x01]
-
-v_mad_i32_i24 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xde,0x01]
-
-v_mad_i32_i24 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xf2,0x01]
-
-v_mad_i32_i24 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xfa,0x01]
-
-v_mad_i32_i24 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xfe,0x01]
-
-v_mad_i32_i24 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x02,0x02]
-
-v_mad_i32_i24 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x06,0x03]
-
-v_mad_i32_i24 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xc2,0x03]
-
-v_mad_i32_i24 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xde,0x03]
-
-v_mad_u32_u24 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x43,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0xff,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x67,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x77,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x80,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xff,0x0f,0x04]
-
-v_mad_u32_u24 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xef,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xff,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x01,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x83,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xef,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xfe,0x07]
-
-v_mad_u32_u24 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x0e,0x00]
-
-v_mad_u32_u24 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x9e,0x01]
-
-v_mad_u32_u24 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xaa,0x01]
-
-v_mad_u32_u24 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xae,0x01]
-
-v_mad_u32_u24 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xde,0x01]
-
-v_mad_u32_u24 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xf2,0x01]
-
-v_mad_u32_u24 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xfa,0x01]
-
-v_mad_u32_u24 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xfe,0x01]
-
-v_mad_u32_u24 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x02,0x02]
-
-v_mad_u32_u24 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x06,0x03]
-
-v_mad_u32_u24 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xc2,0x03]
-
-v_mad_u32_u24 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xde,0x03]
-
-v_cubeid_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x44,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0xff,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x67,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x77,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x80,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xff,0x0f,0x04]
-
-v_cubeid_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xef,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xff,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x01,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x83,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xef,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xfe,0x07]
-
-v_cubeid_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x00]
-
-v_cubeid_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x9e,0x01]
-
-v_cubeid_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xaa,0x01]
-
-v_cubeid_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xae,0x01]
-
-v_cubeid_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xde,0x01]
-
-v_cubeid_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xf2,0x01]
-
-v_cubeid_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xfa,0x01]
-
-v_cubeid_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xfe,0x01]
-
-v_cubeid_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x02,0x02]
-
-v_cubeid_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x06,0x03]
-
-v_cubeid_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xc2,0x03]
-
-v_cubeid_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xde,0x03]
-
-v_cubeid_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x24]
-
-v_cubeid_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x44]
-
-v_cubeid_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x84]
-
-v_cubeid_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_cubeid_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x44,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x44,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x44,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x44,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x44,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_cubeid_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x14]
-
-v_cubeid_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_cubesc_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x45,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0xff,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x67,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x77,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x80,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xff,0x0f,0x04]
-
-v_cubesc_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xef,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xff,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x01,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x83,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xef,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xfe,0x07]
-
-v_cubesc_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x00]
-
-v_cubesc_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x9e,0x01]
-
-v_cubesc_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xaa,0x01]
-
-v_cubesc_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xae,0x01]
-
-v_cubesc_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xde,0x01]
-
-v_cubesc_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xf2,0x01]
-
-v_cubesc_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xfa,0x01]
-
-v_cubesc_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xfe,0x01]
-
-v_cubesc_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x02,0x02]
-
-v_cubesc_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x06,0x03]
-
-v_cubesc_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xc2,0x03]
-
-v_cubesc_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xde,0x03]
-
-v_cubesc_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x24]
-
-v_cubesc_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x44]
-
-v_cubesc_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x84]
-
-v_cubesc_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_cubesc_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x45,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x45,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x45,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x45,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x45,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_cubesc_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x14]
-
-v_cubesc_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_cubetc_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x46,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0xff,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x67,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x77,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x80,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xff,0x0f,0x04]
-
-v_cubetc_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xef,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xff,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x01,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x83,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xef,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xfe,0x07]
-
-v_cubetc_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x00]
-
-v_cubetc_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x9e,0x01]
-
-v_cubetc_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xaa,0x01]
-
-v_cubetc_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xae,0x01]
-
-v_cubetc_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xde,0x01]
-
-v_cubetc_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xf2,0x01]
-
-v_cubetc_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xfa,0x01]
-
-v_cubetc_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xfe,0x01]
-
-v_cubetc_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x02,0x02]
-
-v_cubetc_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x06,0x03]
-
-v_cubetc_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xc2,0x03]
-
-v_cubetc_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xde,0x03]
-
-v_cubetc_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x24]
-
-v_cubetc_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x44]
-
-v_cubetc_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x84]
-
-v_cubetc_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_cubetc_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x46,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x46,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x46,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x46,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x46,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_cubetc_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x14]
-
-v_cubetc_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_cubema_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x47,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0xff,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x67,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x77,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x80,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xff,0x0f,0x04]
-
-v_cubema_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0c,0x04]
-
-v_cubema_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_cubema_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_cubema_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_cubema_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xef,0x0c,0x04]
-
-v_cubema_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_cubema_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_cubema_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xff,0x0c,0x04]
-
-v_cubema_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x01,0x0d,0x04]
-
-v_cubema_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x83,0x0d,0x04]
-
-v_cubema_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_cubema_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xef,0x0d,0x04]
-
-v_cubema_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xfe,0x07]
-
-v_cubema_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x00]
-
-v_cubema_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x9e,0x01]
-
-v_cubema_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xaa,0x01]
-
-v_cubema_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xae,0x01]
-
-v_cubema_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xde,0x01]
-
-v_cubema_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xf2,0x01]
-
-v_cubema_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xfa,0x01]
-
-v_cubema_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xfe,0x01]
-
-v_cubema_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x02,0x02]
-
-v_cubema_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x06,0x03]
-
-v_cubema_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xc2,0x03]
-
-v_cubema_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xde,0x03]
-
-v_cubema_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x24]
-
-v_cubema_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x44]
-
-v_cubema_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x84]
-
-v_cubema_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_cubema_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x47,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x47,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x47,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x47,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x47,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_cubema_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x14]
-
-v_cubema_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_bfe_u32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x0e,0x04]
-
-v_bfe_u32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x48,0xd5,0x01,0x05,0x0e,0x04]
-
-v_bfe_u32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0xff,0x05,0x0e,0x04]
-
-v_bfe_u32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x67,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x77,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x80,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xff,0x0f,0x04]
-
-v_bfe_u32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x0c,0x04]
-
-v_bfe_u32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_bfe_u32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_bfe_u32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_bfe_u32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xef,0x0c,0x04]
-
-v_bfe_u32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_bfe_u32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_bfe_u32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xff,0x0c,0x04]
-
-v_bfe_u32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x01,0x0d,0x04]
-
-v_bfe_u32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x83,0x0d,0x04]
-
-v_bfe_u32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_bfe_u32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xef,0x0d,0x04]
-
-v_bfe_u32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xfe,0x07]
-
-v_bfe_u32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x0e,0x00]
-
-v_bfe_u32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x9e,0x01]
-
-v_bfe_u32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xaa,0x01]
-
-v_bfe_u32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xae,0x01]
-
-v_bfe_u32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xde,0x01]
-
-v_bfe_u32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xf2,0x01]
-
-v_bfe_u32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xfa,0x01]
-
-v_bfe_u32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xfe,0x01]
-
-v_bfe_u32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x02,0x02]
-
-v_bfe_u32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x06,0x03]
-
-v_bfe_u32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xc2,0x03]
-
-v_bfe_u32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xde,0x03]
-
-v_bfe_i32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x0e,0x04]
-
-v_bfe_i32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x49,0xd5,0x01,0x05,0x0e,0x04]
-
-v_bfe_i32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0xff,0x05,0x0e,0x04]
-
-v_bfe_i32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x67,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x77,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x80,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xff,0x0f,0x04]
-
-v_bfe_i32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x0c,0x04]
-
-v_bfe_i32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_bfe_i32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_bfe_i32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_bfe_i32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xef,0x0c,0x04]
-
-v_bfe_i32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_bfe_i32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_bfe_i32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xff,0x0c,0x04]
-
-v_bfe_i32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x01,0x0d,0x04]
-
-v_bfe_i32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x83,0x0d,0x04]
-
-v_bfe_i32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_bfe_i32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xef,0x0d,0x04]
-
-v_bfe_i32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xfe,0x07]
-
-v_bfe_i32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x0e,0x00]
-
-v_bfe_i32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x9e,0x01]
-
-v_bfe_i32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xaa,0x01]
-
-v_bfe_i32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xae,0x01]
-
-v_bfe_i32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xde,0x01]
-
-v_bfe_i32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xf2,0x01]
-
-v_bfe_i32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xfa,0x01]
-
-v_bfe_i32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xfe,0x01]
-
-v_bfe_i32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x02,0x02]
-
-v_bfe_i32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x06,0x03]
-
-v_bfe_i32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xc2,0x03]
-
-v_bfe_i32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xde,0x03]
-
-v_bfi_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x0e,0x04]
-
-v_bfi_b32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x4a,0xd5,0x01,0x05,0x0e,0x04]
-
-v_bfi_b32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0xff,0x05,0x0e,0x04]
-
-v_bfi_b32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x67,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x77,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x80,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xff,0x0f,0x04]
-
-v_bfi_b32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x0c,0x04]
-
-v_bfi_b32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_bfi_b32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_bfi_b32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_bfi_b32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xef,0x0c,0x04]
-
-v_bfi_b32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_bfi_b32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_bfi_b32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xff,0x0c,0x04]
-
-v_bfi_b32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x01,0x0d,0x04]
-
-v_bfi_b32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x83,0x0d,0x04]
-
-v_bfi_b32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_bfi_b32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xef,0x0d,0x04]
-
-v_bfi_b32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xfe,0x07]
-
-v_bfi_b32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x0e,0x00]
-
-v_bfi_b32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x9e,0x01]
-
-v_bfi_b32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xaa,0x01]
-
-v_bfi_b32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xae,0x01]
-
-v_bfi_b32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xde,0x01]
-
-v_bfi_b32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xf2,0x01]
-
-v_bfi_b32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xfa,0x01]
-
-v_bfi_b32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xfe,0x01]
-
-v_bfi_b32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x02,0x02]
-
-v_bfi_b32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x06,0x03]
-
-v_bfi_b32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xc2,0x03]
-
-v_bfi_b32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xde,0x03]
-
-v_fma_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0xff,0x05,0x0e,0x04]
-
-v_fma_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x04,0x0e,0x04]
-
-v_fma_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x67,0x04,0x0e,0x04]
-
-v_fma_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_fma_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_fma_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x77,0x04,0x0e,0x04]
-
-v_fma_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_fma_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_fma_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_fma_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x80,0x04,0x0e,0x04]
-
-v_fma_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_fma_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_fma_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_fma_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xff,0x0f,0x04]
-
-v_fma_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0c,0x04]
-
-v_fma_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_fma_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_fma_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_fma_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xef,0x0c,0x04]
-
-v_fma_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_fma_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_fma_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xff,0x0c,0x04]
-
-v_fma_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x01,0x0d,0x04]
-
-v_fma_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x83,0x0d,0x04]
-
-v_fma_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_fma_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xef,0x0d,0x04]
-
-v_fma_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xfe,0x07]
-
-v_fma_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x00]
-
-v_fma_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x9e,0x01]
-
-v_fma_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xaa,0x01]
-
-v_fma_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xae,0x01]
-
-v_fma_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xde,0x01]
-
-v_fma_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xf2,0x01]
-
-v_fma_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xfa,0x01]
-
-v_fma_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xfe,0x01]
-
-v_fma_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x02,0x02]
-
-v_fma_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x06,0x03]
-
-v_fma_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xc2,0x03]
-
-v_fma_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xde,0x03]
-
-v_fma_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x24]
-
-v_fma_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x44]
-
-v_fma_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x84]
-
-v_fma_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_fma_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x4b,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x4b,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x4b,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x4b,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x4b,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_fma_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x14]
-
-v_fma_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// GFX10: encoding: [0xfe,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0xfe,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[2:3], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x02,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[4:5], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x04,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[102:103], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x66,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], vcc, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x76,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], exec, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], 0, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x80,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], -1, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xfd,0x0f,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[4:5], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x09,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[6:7], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x0d,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[102:103], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xcd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], vcc, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xed,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], exec, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], 0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x01,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], -1, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x83,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xef,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xfa,0x07]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[6:7]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x1a,0x00]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[8:9]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x22,0x00]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[102:103]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x9a,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], vcc
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xaa,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xda,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], exec
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xfa,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], 0
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x02,0x02]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -1
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x06,0x03]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], 0.5
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xc2,0x03]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -4.0
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xde,0x03]
-
-v_fma_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x24]
-
-v_fma_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x44]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x84]
-
-v_fma_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_fma_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x01,0x4c,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// GFX10: encoding: [0x05,0x02,0x4c,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// GFX10: encoding: [0x05,0x04,0x4c,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// GFX10: encoding: [0x05,0x07,0x4c,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// GFX10: encoding: [0x05,0x80,0x4c,0xd5,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x14]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_lerp_u8 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x0e,0x04]
-
-v_lerp_u8 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x4d,0xd5,0x01,0x05,0x0e,0x04]
-
-v_lerp_u8 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0xff,0x05,0x0e,0x04]
-
-v_lerp_u8 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x67,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x77,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x80,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xff,0x0f,0x04]
-
-v_lerp_u8 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x0c,0x04]
-
-v_lerp_u8 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_lerp_u8 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_lerp_u8 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_lerp_u8 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xef,0x0c,0x04]
-
-v_lerp_u8 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_lerp_u8 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_lerp_u8 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xff,0x0c,0x04]
-
-v_lerp_u8 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x01,0x0d,0x04]
-
-v_lerp_u8 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x83,0x0d,0x04]
-
-v_lerp_u8 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_lerp_u8 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xef,0x0d,0x04]
-
-v_lerp_u8 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xfe,0x07]
-
-v_lerp_u8 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x0e,0x00]
-
-v_lerp_u8 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x9e,0x01]
-
-v_lerp_u8 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xaa,0x01]
-
-v_lerp_u8 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xae,0x01]
-
-v_lerp_u8 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xde,0x01]
-
-v_lerp_u8 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xf2,0x01]
-
-v_lerp_u8 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xfa,0x01]
-
-v_lerp_u8 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xfe,0x01]
-
-v_lerp_u8 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x02,0x02]
-
-v_lerp_u8 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x06,0x03]
-
-v_lerp_u8 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xc2,0x03]
-
-v_lerp_u8 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xde,0x03]
-
-v_alignbit_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0x0e,0x04]
-
-v_alignbit_b32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x4e,0xd5,0x01,0x05,0x0e,0x04]
-
-v_alignbit_b32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0xff,0x05,0x0e,0x04]
-
-v_alignbit_b32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x67,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x77,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xff,0x0f,0x04]
-
-v_alignbit_b32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xef,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xff,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xfe,0x07]
-
-v_alignbit_b32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0x0e,0x00]
-
-v_alignbit_b32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0x9e,0x01]
-
-v_alignbit_b32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xaa,0x01]
-
-v_alignbit_b32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xae,0x01]
-
-v_alignbit_b32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xde,0x01]
-
-v_alignbit_b32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xf2,0x01]
-
-v_alignbit_b32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xfa,0x01]
-
-v_alignbit_b32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xfe,0x01]
-
-v_alignbyte_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0xff,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x67,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x77,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xff,0x0f,0x04]
-
-v_alignbyte_b32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xef,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xff,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xfe,0x07]
-
-v_alignbyte_b32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x00]
-
-v_alignbyte_b32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x9e,0x01]
-
-v_alignbyte_b32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xaa,0x01]
-
-v_alignbyte_b32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xae,0x01]
-
-v_alignbyte_b32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xde,0x01]
-
-v_alignbyte_b32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xf2,0x01]
-
-v_alignbyte_b32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xfa,0x01]
-
-v_alignbyte_b32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xfe,0x01]
-
-v_mullit_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x50,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0xff,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x67,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x77,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x80,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xff,0x0f,0x04]
-
-v_mullit_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0c,0x04]
-
-v_mullit_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_mullit_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_mullit_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_mullit_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xef,0x0c,0x04]
-
-v_mullit_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_mullit_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_mullit_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xff,0x0c,0x04]
-
-v_mullit_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x01,0x0d,0x04]
-
-v_mullit_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x83,0x0d,0x04]
-
-v_mullit_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_mullit_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xef,0x0d,0x04]
-
-v_mullit_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xfe,0x07]
-
-v_mullit_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x00]
-
-v_mullit_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x9e,0x01]
-
-v_mullit_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xaa,0x01]
-
-v_mullit_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xae,0x01]
-
-v_mullit_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xde,0x01]
-
-v_mullit_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xf2,0x01]
-
-v_mullit_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xfa,0x01]
-
-v_mullit_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xfe,0x01]
-
-v_mullit_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x02,0x02]
-
-v_mullit_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x06,0x03]
-
-v_mullit_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xc2,0x03]
-
-v_mullit_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xde,0x03]
-
-v_mullit_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x24]
-
-v_mullit_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x44]
-
-v_mullit_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x84]
-
-v_mullit_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_mullit_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x50,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x50,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x50,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x50,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x50,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_mullit_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x14]
-
-v_mullit_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_min3_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x51,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0xff,0x05,0x0e,0x04]
-
-v_min3_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x04,0x0e,0x04]
-
-v_min3_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x67,0x04,0x0e,0x04]
-
-v_min3_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_min3_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_min3_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x77,0x04,0x0e,0x04]
-
-v_min3_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_min3_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_min3_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_min3_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x80,0x04,0x0e,0x04]
-
-v_min3_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_min3_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_min3_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_min3_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xff,0x0f,0x04]
-
-v_min3_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0c,0x04]
-
-v_min3_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_min3_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_min3_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_min3_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xef,0x0c,0x04]
-
-v_min3_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_min3_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_min3_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xff,0x0c,0x04]
-
-v_min3_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x01,0x0d,0x04]
-
-v_min3_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x83,0x0d,0x04]
-
-v_min3_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_min3_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xef,0x0d,0x04]
-
-v_min3_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xfe,0x07]
-
-v_min3_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x00]
-
-v_min3_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x9e,0x01]
-
-v_min3_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xaa,0x01]
-
-v_min3_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xae,0x01]
-
-v_min3_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xde,0x01]
-
-v_min3_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xf2,0x01]
-
-v_min3_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xfa,0x01]
-
-v_min3_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xfe,0x01]
-
-v_min3_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x02,0x02]
-
-v_min3_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x06,0x03]
-
-v_min3_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xc2,0x03]
-
-v_min3_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xde,0x03]
-
-v_min3_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x24]
-
-v_min3_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x44]
-
-v_min3_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x84]
-
-v_min3_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_min3_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x51,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x51,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x51,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x51,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x51,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_min3_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x14]
-
-v_min3_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_min3_i32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_i32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x52,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_i32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0xff,0x05,0x0e,0x04]
-
-v_min3_i32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x04,0x0e,0x04]
-
-v_min3_i32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x67,0x04,0x0e,0x04]
-
-v_min3_i32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_min3_i32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_min3_i32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x77,0x04,0x0e,0x04]
-
-v_min3_i32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_min3_i32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_min3_i32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_min3_i32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x80,0x04,0x0e,0x04]
-
-v_min3_i32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_min3_i32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_min3_i32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_min3_i32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xff,0x0f,0x04]
-
-v_min3_i32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x0c,0x04]
-
-v_min3_i32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_min3_i32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_min3_i32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_min3_i32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xef,0x0c,0x04]
-
-v_min3_i32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_min3_i32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_min3_i32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xff,0x0c,0x04]
-
-v_min3_i32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x01,0x0d,0x04]
-
-v_min3_i32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x83,0x0d,0x04]
-
-v_min3_i32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_min3_i32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xef,0x0d,0x04]
-
-v_min3_i32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xfe,0x07]
-
-v_min3_i32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x0e,0x00]
-
-v_min3_i32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x9e,0x01]
-
-v_min3_i32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xaa,0x01]
-
-v_min3_i32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xae,0x01]
-
-v_min3_i32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xde,0x01]
-
-v_min3_i32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xf2,0x01]
-
-v_min3_i32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xfa,0x01]
-
-v_min3_i32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xfe,0x01]
-
-v_min3_i32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x02,0x02]
-
-v_min3_i32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x06,0x03]
-
-v_min3_i32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xc2,0x03]
-
-v_min3_i32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xde,0x03]
-
-v_min3_u32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_u32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x53,0xd5,0x01,0x05,0x0e,0x04]
-
-v_min3_u32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0xff,0x05,0x0e,0x04]
-
-v_min3_u32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x04,0x0e,0x04]
-
-v_min3_u32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x67,0x04,0x0e,0x04]
-
-v_min3_u32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_min3_u32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_min3_u32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x77,0x04,0x0e,0x04]
-
-v_min3_u32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_min3_u32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_min3_u32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_min3_u32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x80,0x04,0x0e,0x04]
-
-v_min3_u32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_min3_u32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_min3_u32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_min3_u32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xff,0x0f,0x04]
-
-v_min3_u32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x0c,0x04]
-
-v_min3_u32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_min3_u32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_min3_u32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_min3_u32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xef,0x0c,0x04]
-
-v_min3_u32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_min3_u32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_min3_u32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xff,0x0c,0x04]
-
-v_min3_u32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x01,0x0d,0x04]
-
-v_min3_u32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x83,0x0d,0x04]
-
-v_min3_u32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_min3_u32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xef,0x0d,0x04]
-
-v_min3_u32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xfe,0x07]
-
-v_min3_u32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x0e,0x00]
-
-v_min3_u32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x9e,0x01]
-
-v_min3_u32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xaa,0x01]
-
-v_min3_u32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xae,0x01]
-
-v_min3_u32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xde,0x01]
-
-v_min3_u32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xf2,0x01]
-
-v_min3_u32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xfa,0x01]
-
-v_min3_u32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xfe,0x01]
-
-v_min3_u32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x02,0x02]
-
-v_min3_u32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x06,0x03]
-
-v_min3_u32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xc2,0x03]
-
-v_min3_u32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xde,0x03]
-
-v_max3_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x54,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0xff,0x05,0x0e,0x04]
-
-v_max3_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x04,0x0e,0x04]
-
-v_max3_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x67,0x04,0x0e,0x04]
-
-v_max3_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_max3_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_max3_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x77,0x04,0x0e,0x04]
-
-v_max3_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_max3_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_max3_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_max3_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x80,0x04,0x0e,0x04]
-
-v_max3_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_max3_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_max3_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_max3_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xff,0x0f,0x04]
-
-v_max3_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0c,0x04]
-
-v_max3_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_max3_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_max3_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_max3_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xef,0x0c,0x04]
-
-v_max3_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_max3_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_max3_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xff,0x0c,0x04]
-
-v_max3_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x01,0x0d,0x04]
-
-v_max3_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x83,0x0d,0x04]
-
-v_max3_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_max3_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xef,0x0d,0x04]
-
-v_max3_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xfe,0x07]
-
-v_max3_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x00]
-
-v_max3_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x9e,0x01]
-
-v_max3_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xaa,0x01]
-
-v_max3_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xae,0x01]
-
-v_max3_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xde,0x01]
-
-v_max3_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xf2,0x01]
-
-v_max3_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xfa,0x01]
-
-v_max3_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xfe,0x01]
-
-v_max3_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x02,0x02]
-
-v_max3_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x06,0x03]
-
-v_max3_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xc2,0x03]
-
-v_max3_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xde,0x03]
-
-v_max3_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x24]
-
-v_max3_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x44]
-
-v_max3_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x84]
-
-v_max3_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_max3_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x54,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x54,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x54,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x54,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x54,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_max3_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x14]
-
-v_max3_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_max3_i32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_i32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x55,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_i32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0xff,0x05,0x0e,0x04]
-
-v_max3_i32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x04,0x0e,0x04]
-
-v_max3_i32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x67,0x04,0x0e,0x04]
-
-v_max3_i32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_max3_i32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_max3_i32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x77,0x04,0x0e,0x04]
-
-v_max3_i32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_max3_i32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_max3_i32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_max3_i32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x80,0x04,0x0e,0x04]
-
-v_max3_i32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_max3_i32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_max3_i32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_max3_i32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xff,0x0f,0x04]
-
-v_max3_i32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x0c,0x04]
-
-v_max3_i32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_max3_i32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_max3_i32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_max3_i32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xef,0x0c,0x04]
-
-v_max3_i32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_max3_i32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_max3_i32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xff,0x0c,0x04]
-
-v_max3_i32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x01,0x0d,0x04]
-
-v_max3_i32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x83,0x0d,0x04]
-
-v_max3_i32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_max3_i32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xef,0x0d,0x04]
-
-v_max3_i32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xfe,0x07]
-
-v_max3_i32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x0e,0x00]
-
-v_max3_i32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x9e,0x01]
-
-v_max3_i32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xaa,0x01]
-
-v_max3_i32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xae,0x01]
-
-v_max3_i32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xde,0x01]
-
-v_max3_i32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xf2,0x01]
-
-v_max3_i32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xfa,0x01]
-
-v_max3_i32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xfe,0x01]
-
-v_max3_i32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x02,0x02]
-
-v_max3_i32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x06,0x03]
-
-v_max3_i32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xc2,0x03]
-
-v_max3_i32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xde,0x03]
-
-v_max3_u32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_u32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x56,0xd5,0x01,0x05,0x0e,0x04]
-
-v_max3_u32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0xff,0x05,0x0e,0x04]
-
-v_max3_u32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x04,0x0e,0x04]
-
-v_max3_u32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x67,0x04,0x0e,0x04]
-
-v_max3_u32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_max3_u32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_max3_u32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x77,0x04,0x0e,0x04]
-
-v_max3_u32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_max3_u32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_max3_u32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_max3_u32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x80,0x04,0x0e,0x04]
-
-v_max3_u32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_max3_u32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_max3_u32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_max3_u32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xff,0x0f,0x04]
-
-v_max3_u32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x0c,0x04]
-
-v_max3_u32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_max3_u32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_max3_u32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_max3_u32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xef,0x0c,0x04]
-
-v_max3_u32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_max3_u32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_max3_u32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xff,0x0c,0x04]
-
-v_max3_u32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x01,0x0d,0x04]
-
-v_max3_u32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x83,0x0d,0x04]
-
-v_max3_u32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_max3_u32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xef,0x0d,0x04]
-
-v_max3_u32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xfe,0x07]
-
-v_max3_u32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x0e,0x00]
-
-v_max3_u32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x9e,0x01]
-
-v_max3_u32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xaa,0x01]
-
-v_max3_u32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xae,0x01]
-
-v_max3_u32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xde,0x01]
-
-v_max3_u32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xf2,0x01]
-
-v_max3_u32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xfa,0x01]
-
-v_max3_u32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xfe,0x01]
-
-v_max3_u32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x02,0x02]
-
-v_max3_u32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x06,0x03]
-
-v_max3_u32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xc2,0x03]
-
-v_max3_u32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xde,0x03]
-
-v_med3_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x57,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0xff,0x05,0x0e,0x04]
-
-v_med3_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x04,0x0e,0x04]
-
-v_med3_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x67,0x04,0x0e,0x04]
-
-v_med3_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_med3_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_med3_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x77,0x04,0x0e,0x04]
-
-v_med3_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_med3_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_med3_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_med3_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x80,0x04,0x0e,0x04]
-
-v_med3_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_med3_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_med3_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_med3_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xff,0x0f,0x04]
-
-v_med3_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0c,0x04]
-
-v_med3_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_med3_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_med3_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_med3_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xef,0x0c,0x04]
-
-v_med3_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_med3_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_med3_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xff,0x0c,0x04]
-
-v_med3_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x01,0x0d,0x04]
-
-v_med3_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x83,0x0d,0x04]
-
-v_med3_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_med3_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xef,0x0d,0x04]
-
-v_med3_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xfe,0x07]
-
-v_med3_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x00]
-
-v_med3_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x9e,0x01]
-
-v_med3_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xaa,0x01]
-
-v_med3_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xae,0x01]
-
-v_med3_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xde,0x01]
-
-v_med3_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xf2,0x01]
-
-v_med3_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xfa,0x01]
-
-v_med3_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xfe,0x01]
-
-v_med3_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x02,0x02]
-
-v_med3_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x06,0x03]
-
-v_med3_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xc2,0x03]
-
-v_med3_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xde,0x03]
-
-v_med3_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x24]
-
-v_med3_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x44]
-
-v_med3_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x84]
-
-v_med3_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_med3_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x57,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x57,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x57,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x57,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x57,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_med3_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x14]
-
-v_med3_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_med3_i32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_i32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x58,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_i32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0xff,0x05,0x0e,0x04]
-
-v_med3_i32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x04,0x0e,0x04]
-
-v_med3_i32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x67,0x04,0x0e,0x04]
-
-v_med3_i32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_med3_i32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_med3_i32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x77,0x04,0x0e,0x04]
-
-v_med3_i32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_med3_i32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_med3_i32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_med3_i32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x80,0x04,0x0e,0x04]
-
-v_med3_i32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_med3_i32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_med3_i32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_med3_i32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xff,0x0f,0x04]
-
-v_med3_i32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x0c,0x04]
-
-v_med3_i32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_med3_i32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_med3_i32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_med3_i32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xef,0x0c,0x04]
-
-v_med3_i32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_med3_i32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_med3_i32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xff,0x0c,0x04]
-
-v_med3_i32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x01,0x0d,0x04]
-
-v_med3_i32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x83,0x0d,0x04]
-
-v_med3_i32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_med3_i32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xef,0x0d,0x04]
-
-v_med3_i32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xfe,0x07]
-
-v_med3_i32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x0e,0x00]
-
-v_med3_i32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x9e,0x01]
-
-v_med3_i32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xaa,0x01]
-
-v_med3_i32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xae,0x01]
-
-v_med3_i32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xde,0x01]
-
-v_med3_i32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xf2,0x01]
-
-v_med3_i32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xfa,0x01]
-
-v_med3_i32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xfe,0x01]
-
-v_med3_i32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x02,0x02]
-
-v_med3_i32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x06,0x03]
-
-v_med3_i32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xc2,0x03]
-
-v_med3_i32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xde,0x03]
-
-v_med3_u32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_u32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x59,0xd5,0x01,0x05,0x0e,0x04]
-
-v_med3_u32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0xff,0x05,0x0e,0x04]
-
-v_med3_u32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x04,0x0e,0x04]
-
-v_med3_u32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x67,0x04,0x0e,0x04]
-
-v_med3_u32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_med3_u32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_med3_u32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x77,0x04,0x0e,0x04]
-
-v_med3_u32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_med3_u32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_med3_u32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_med3_u32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x80,0x04,0x0e,0x04]
-
-v_med3_u32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_med3_u32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_med3_u32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_med3_u32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xff,0x0f,0x04]
-
-v_med3_u32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x0c,0x04]
-
-v_med3_u32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_med3_u32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_med3_u32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_med3_u32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xef,0x0c,0x04]
-
-v_med3_u32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_med3_u32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_med3_u32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xff,0x0c,0x04]
-
-v_med3_u32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x01,0x0d,0x04]
-
-v_med3_u32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x83,0x0d,0x04]
-
-v_med3_u32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_med3_u32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xef,0x0d,0x04]
-
-v_med3_u32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xfe,0x07]
-
-v_med3_u32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x0e,0x00]
-
-v_med3_u32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x9e,0x01]
-
-v_med3_u32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xaa,0x01]
-
-v_med3_u32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xae,0x01]
-
-v_med3_u32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xde,0x01]
-
-v_med3_u32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xf2,0x01]
-
-v_med3_u32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xfa,0x01]
-
-v_med3_u32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xfe,0x01]
-
-v_med3_u32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x02,0x02]
-
-v_med3_u32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x06,0x03]
-
-v_med3_u32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xc2,0x03]
-
-v_med3_u32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xde,0x03]
-
-v_sad_u8 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x0e,0x04]
-
-v_sad_u8 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x5a,0xd5,0x01,0x05,0x0e,0x04]
-
-v_sad_u8 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0xff,0x05,0x0e,0x04]
-
-v_sad_u8 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x04,0x0e,0x04]
-
-v_sad_u8 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x67,0x04,0x0e,0x04]
-
-v_sad_u8 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_sad_u8 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_sad_u8 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x77,0x04,0x0e,0x04]
-
-v_sad_u8 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_sad_u8 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_sad_u8 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_sad_u8 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x80,0x04,0x0e,0x04]
-
-v_sad_u8 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_sad_u8 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_sad_u8 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_sad_u8 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xff,0x0f,0x04]
-
-v_sad_u8 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x0c,0x04]
-
-v_sad_u8 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_sad_u8 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_sad_u8 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_sad_u8 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xef,0x0c,0x04]
-
-v_sad_u8 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_sad_u8 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_sad_u8 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xff,0x0c,0x04]
-
-v_sad_u8 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x01,0x0d,0x04]
-
-v_sad_u8 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x83,0x0d,0x04]
-
-v_sad_u8 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_sad_u8 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xef,0x0d,0x04]
-
-v_sad_u8 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xfe,0x07]
-
-v_sad_u8 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x0e,0x00]
-
-v_sad_u8 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x9e,0x01]
-
-v_sad_u8 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xaa,0x01]
-
-v_sad_u8 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xae,0x01]
-
-v_sad_u8 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xde,0x01]
-
-v_sad_u8 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xf2,0x01]
-
-v_sad_u8 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xfa,0x01]
-
-v_sad_u8 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xfe,0x01]
-
-v_sad_u8 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x02,0x02]
-
-v_sad_u8 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x06,0x03]
-
-v_sad_u8 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xc2,0x03]
-
-v_sad_u8 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xde,0x03]
-
-v_sad_hi_u8 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x5b,0xd5,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0xff,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x67,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x77,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x80,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xff,0x0f,0x04]
-
-v_sad_hi_u8 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xef,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xff,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x01,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x83,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xef,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xfe,0x07]
-
-v_sad_hi_u8 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x0e,0x00]
-
-v_sad_hi_u8 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x9e,0x01]
-
-v_sad_hi_u8 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xaa,0x01]
-
-v_sad_hi_u8 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xae,0x01]
-
-v_sad_hi_u8 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xde,0x01]
-
-v_sad_hi_u8 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xf2,0x01]
-
-v_sad_hi_u8 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xfa,0x01]
-
-v_sad_hi_u8 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xfe,0x01]
-
-v_sad_hi_u8 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x02,0x02]
-
-v_sad_hi_u8 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x06,0x03]
-
-v_sad_hi_u8 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xc2,0x03]
-
-v_sad_hi_u8 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xde,0x03]
-
-v_sad_u16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x5c,0xd5,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0xff,0x05,0x0e,0x04]
-
-v_sad_u16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x04,0x0e,0x04]
-
-v_sad_u16 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x67,0x04,0x0e,0x04]
-
-v_sad_u16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_sad_u16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_sad_u16 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x77,0x04,0x0e,0x04]
-
-v_sad_u16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_sad_u16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_sad_u16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_sad_u16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x80,0x04,0x0e,0x04]
-
-v_sad_u16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_sad_u16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_sad_u16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_sad_u16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xff,0x0f,0x04]
-
-v_sad_u16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x0c,0x04]
-
-v_sad_u16 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_sad_u16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_sad_u16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_sad_u16 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xef,0x0c,0x04]
-
-v_sad_u16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_sad_u16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_sad_u16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xff,0x0c,0x04]
-
-v_sad_u16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x01,0x0d,0x04]
-
-v_sad_u16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x83,0x0d,0x04]
-
-v_sad_u16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_sad_u16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xef,0x0d,0x04]
-
-v_sad_u16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xfe,0x07]
-
-v_sad_u16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x0e,0x00]
-
-v_sad_u16 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x9e,0x01]
-
-v_sad_u16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xaa,0x01]
-
-v_sad_u16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xae,0x01]
-
-v_sad_u16 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xde,0x01]
-
-v_sad_u16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xf2,0x01]
-
-v_sad_u16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xfa,0x01]
-
-v_sad_u16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xfe,0x01]
-
-v_sad_u16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x02,0x02]
-
-v_sad_u16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x06,0x03]
-
-v_sad_u16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xc2,0x03]
-
-v_sad_u16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xde,0x03]
-
-v_sad_u32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x5d,0xd5,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0xff,0x05,0x0e,0x04]
-
-v_sad_u32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x04,0x0e,0x04]
-
-v_sad_u32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x67,0x04,0x0e,0x04]
-
-v_sad_u32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_sad_u32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_sad_u32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x77,0x04,0x0e,0x04]
-
-v_sad_u32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_sad_u32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_sad_u32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_sad_u32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x80,0x04,0x0e,0x04]
-
-v_sad_u32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_sad_u32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_sad_u32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_sad_u32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xff,0x0f,0x04]
-
-v_sad_u32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x0c,0x04]
-
-v_sad_u32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_sad_u32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_sad_u32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_sad_u32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xef,0x0c,0x04]
-
-v_sad_u32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_sad_u32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_sad_u32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xff,0x0c,0x04]
-
-v_sad_u32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x01,0x0d,0x04]
-
-v_sad_u32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x83,0x0d,0x04]
-
-v_sad_u32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_sad_u32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xef,0x0d,0x04]
-
-v_sad_u32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xfe,0x07]
-
-v_sad_u32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x0e,0x00]
-
-v_sad_u32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x9e,0x01]
-
-v_sad_u32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xaa,0x01]
-
-v_sad_u32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xae,0x01]
-
-v_sad_u32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xde,0x01]
-
-v_sad_u32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xf2,0x01]
-
-v_sad_u32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xfa,0x01]
-
-v_sad_u32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xfe,0x01]
-
-v_sad_u32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x02,0x02]
-
-v_sad_u32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x06,0x03]
-
-v_sad_u32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xc2,0x03]
-
-v_sad_u32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xde,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0xff,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x67,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x77,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x80,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xff,0x0f,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xef,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xff,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x01,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x83,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xef,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xfe,0x07]
-
-v_cvt_pk_u8_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x00]
-
-v_cvt_pk_u8_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x9e,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xaa,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xae,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xde,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xf2,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xfa,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xfe,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x02,0x02]
-
-v_cvt_pk_u8_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x06,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xc2,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xde,0x03]
-
-v_cvt_pk_u8_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x24]
-
-v_cvt_pk_u8_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x5e,0xd5,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x5e,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0xff,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x67,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x77,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xff,0x0f,0x04]
-
-v_div_fixup_f32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xef,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xff,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xfe,0x07]
-
-v_div_fixup_f32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x00]
-
-v_div_fixup_f32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x9e,0x01]
-
-v_div_fixup_f32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xae,0x01]
-
-v_div_fixup_f32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xde,0x01]
-
-v_div_fixup_f32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xf2,0x01]
-
-v_div_fixup_f32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xfe,0x01]
-
-v_div_fixup_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x5f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x5f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x5f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x5f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x5f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_div_fixup_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x14]
-
-v_div_fixup_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// GFX10: encoding: [0xfe,0x00,0x60,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0xfe,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[2:3], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x02,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[4:5], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x04,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[102:103], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x66,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], vcc, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x76,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], exec, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], 0, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], -1, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xfd,0x0f,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[4:5], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x09,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[6:7], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x0d,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[102:103], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xcd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], vcc, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xed,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], exec, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], 0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], -1, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xfa,0x07]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[6:7]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x1a,0x00]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[8:9]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x22,0x00]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[102:103]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x9a,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], vcc
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xda,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], exec
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -1
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0.5
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -4.0
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x01,0x60,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// GFX10: encoding: [0x05,0x02,0x60,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// GFX10: encoding: [0x05,0x04,0x60,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// GFX10: encoding: [0x05,0x07,0x60,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// GFX10: encoding: [0x05,0x80,0x60,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x14]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_add_f64 v[5:6], v[1:2], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[254:255], v[1:2], v[2:3]
-// GFX10: encoding: [0xfe,0x00,0x64,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[254:255], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0xfe,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], s[2:3], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x02,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], s[4:5], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x04,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], s[102:103], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x66,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], vcc, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x6a,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], ttmp[10:11], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x76,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], exec, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x7e,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], 0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x80,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], -1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0xc1,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], 0.5, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0xf0,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], -4.0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0xf7,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xfd,0x03,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[4:5]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x09,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[6:7]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x0d,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[102:103]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xcd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], vcc
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xd5,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], ttmp[10:11]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xed,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], exec
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xfd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], 0
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x01,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], -1
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x83,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], 0.5
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xe1,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], -4.0
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xef,0x01,0x00]
-
-v_add_f64 v[5:6], -v[1:2], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x20]
-
-v_add_f64 v[5:6], v[1:2], -v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x40]
-
-v_add_f64 v[5:6], -v[1:2], -v[2:3]
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x60]
-
-v_add_f64 v[5:6], |v[1:2]|, v[2:3]
-// GFX10: encoding: [0x05,0x01,0x64,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], |v[2:3]|
-// GFX10: encoding: [0x05,0x02,0x64,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// GFX10: encoding: [0x05,0x03,0x64,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] clamp
-// GFX10: encoding: [0x05,0x80,0x64,0xd5,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] mul:2
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x08]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] mul:4
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x10]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] div:2
-// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x18]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[254:255], v[1:2], v[2:3]
-// GFX10: encoding: [0xfe,0x00,0x65,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[254:255], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0xfe,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], s[2:3], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x02,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], s[4:5], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x04,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], s[102:103], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x66,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], vcc, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], ttmp[10:11], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x76,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], exec, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], 0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], -1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], 0.5, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], -4.0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xfd,0x03,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[4:5]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x09,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[6:7]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x0d,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[102:103]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xcd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], vcc
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], ttmp[10:11]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xed,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], exec
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], 0
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], -1
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], 0.5
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], -4.0
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_f64 v[5:6], -v[1:2], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x20]
-
-v_mul_f64 v[5:6], v[1:2], -v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x40]
-
-v_mul_f64 v[5:6], -v[1:2], -v[2:3]
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x60]
-
-v_mul_f64 v[5:6], |v[1:2]|, v[2:3]
-// GFX10: encoding: [0x05,0x01,0x65,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], |v[2:3]|
-// GFX10: encoding: [0x05,0x02,0x65,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// GFX10: encoding: [0x05,0x03,0x65,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] clamp
-// GFX10: encoding: [0x05,0x80,0x65,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] mul:2
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x08]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] mul:4
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x10]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] div:2
-// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x18]
-
-v_min_f64 v[5:6], v[1:2], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[254:255], v[1:2], v[2:3]
-// GFX10: encoding: [0xfe,0x00,0x66,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[254:255], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0xfe,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], s[2:3], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x02,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], s[4:5], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x04,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], s[102:103], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x66,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], vcc, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x6a,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], ttmp[10:11], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x76,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], exec, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x7e,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], 0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x80,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], -1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0xc1,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], 0.5, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0xf0,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], -4.0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0xf7,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xfd,0x03,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[4:5]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x09,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[6:7]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x0d,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[102:103]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xcd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], vcc
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xd5,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], ttmp[10:11]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xed,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], exec
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xfd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], 0
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x01,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], -1
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x83,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], 0.5
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xe1,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], -4.0
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xef,0x01,0x00]
-
-v_min_f64 v[5:6], -v[1:2], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x20]
-
-v_min_f64 v[5:6], v[1:2], -v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x40]
-
-v_min_f64 v[5:6], -v[1:2], -v[2:3]
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x60]
-
-v_min_f64 v[5:6], |v[1:2]|, v[2:3]
-// GFX10: encoding: [0x05,0x01,0x66,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], |v[2:3]|
-// GFX10: encoding: [0x05,0x02,0x66,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// GFX10: encoding: [0x05,0x03,0x66,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] clamp
-// GFX10: encoding: [0x05,0x80,0x66,0xd5,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] mul:2
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x08]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] mul:4
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x10]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] div:2
-// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x18]
-
-v_max_f64 v[5:6], v[1:2], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[254:255], v[1:2], v[2:3]
-// GFX10: encoding: [0xfe,0x00,0x67,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[254:255], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0xfe,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], s[2:3], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x02,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], s[4:5], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x04,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], s[102:103], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x66,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], vcc, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x6a,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], ttmp[10:11], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x76,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], exec, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x7e,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], 0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x80,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], -1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0xc1,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], 0.5, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0xf0,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], -4.0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0xf7,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xfd,0x03,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[4:5]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x09,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[6:7]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x0d,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[102:103]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xcd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], vcc
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xd5,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], ttmp[10:11]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xed,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], exec
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xfd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], 0
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x01,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], -1
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x83,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], 0.5
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xe1,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], -4.0
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xef,0x01,0x00]
-
-v_max_f64 v[5:6], -v[1:2], v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x20]
-
-v_max_f64 v[5:6], v[1:2], -v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x40]
-
-v_max_f64 v[5:6], -v[1:2], -v[2:3]
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x60]
-
-v_max_f64 v[5:6], |v[1:2]|, v[2:3]
-// GFX10: encoding: [0x05,0x01,0x67,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], |v[2:3]|
-// GFX10: encoding: [0x05,0x02,0x67,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// GFX10: encoding: [0x05,0x03,0x67,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] clamp
-// GFX10: encoding: [0x05,0x80,0x67,0xd5,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] mul:2
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x08]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] mul:4
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x10]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] div:2
-// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x18]
-
-v_ldexp_f64 v[5:6], v[1:2], v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[254:255], v[1:2], v2
-// GFX10: encoding: [0xfe,0x00,0x68,0xd5,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[254:255], v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0xfe,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[2:3], v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x02,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[4:5], v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x04,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[102:103], v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x66,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], vcc, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], ttmp[10:11], v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x76,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], exec, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], 0, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x80,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], -1, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v255
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xff,0x03,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], s2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], s103
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], vcc_lo
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], vcc_hi
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], ttmp11
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xef,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], m0
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], exec_lo
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], exec_hi
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xff,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], 0
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x01,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], -1
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x83,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], 0.5
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], -4.0
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xef,0x01,0x00]
-
-v_ldexp_f64 v[5:6], -v[1:2], v2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x20]
-
-v_ldexp_f64 v[5:6], |v[1:2]|, v2
-// GFX10: encoding: [0x05,0x01,0x68,0xd5,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 clamp
-// GFX10: encoding: [0x05,0x80,0x68,0xd5,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x08]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x10]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 div:2
-// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x18]
-
-v_mul_lo_u32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x69,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_lo_u32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x67,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x77,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_lo_u32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xcf,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xef,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x6a,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_hi_u32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x67,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x77,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_hi_u32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xef,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xef,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x6c,0xd5,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0xff,0x05,0x02,0x00]
-
-v_mul_hi_i32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x67,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x77,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x80,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xff,0x03,0x00]
-
-v_mul_hi_i32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x05,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xef,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xff,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x83,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xef,0x01,0x00]
-
-v_div_scale_f32 v5, s0, v1, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v255, s0, v1, v2, v3
-// W32: encoding: [0xff,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v255, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0xff,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, s1, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, s103, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x67,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, vcc_lo, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x6a,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, vcc_hi, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x6b,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, ttmp11, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x77,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, m0, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x7c,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, exec_lo, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x7e,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, exec_hi, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x7f,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, 0, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x80,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, -1, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0xc1,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, 0.5, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0xf0,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, -4.0, v2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0xf7,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v255, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xff,0x0f,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, s2, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, s103, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xcf,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, vcc_lo, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xd5,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, vcc_hi, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xd7,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, ttmp11, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xef,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, m0, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xf9,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, exec_lo, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xfd,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, exec_hi, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xff,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, 0, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x01,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, -1, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x83,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, 0.5, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xe1,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, -4.0, v3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xef,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, v255
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfe,0x07]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, s3
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, s103
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x9e,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, vcc_lo
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xaa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, vcc_hi
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xae,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, ttmp11
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xde,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, m0
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xf2,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, exec_lo
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, exec_hi
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfe,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, 0
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x02,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, -1
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, 0.5
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xc2,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s0, v1, v2, -4.0
-// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xde,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v255, s[0:1], v1, v2, v3
-// W64: encoding: [0xff,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v255, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0xff,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], s1, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], s103, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x67,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], vcc_lo, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x6a,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], vcc_hi, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x6b,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], ttmp11, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x77,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], m0, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x7c,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], exec_lo, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x7e,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], exec_hi, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x7f,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], 0, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x80,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], -1, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0xc1,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], 0.5, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0xf0,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], -4.0, v2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0xf7,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v255, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xff,0x0f,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, s2, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, s103, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xcf,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, vcc_lo, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xd5,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, vcc_hi, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xd7,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, ttmp11, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xef,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, m0, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xf9,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, exec_lo, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xfd,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, exec_hi, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xff,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, 0, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x01,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, -1, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x83,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, 0.5, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xe1,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, -4.0, v3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xef,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, v255
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfe,0x07]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, s3
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, s103
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x9e,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, vcc_lo
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xaa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, vcc_hi
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xae,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, ttmp11
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xde,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, m0
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xf2,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, exec_lo
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, exec_hi
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfe,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, 0
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x02,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, -1
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, 0.5
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xc2,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_scale_f32 v5, s[0:1], v1, v2, -4.0
-// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xde,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_div_fmas_f32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0xff,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x80,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0xff,0x0f,0x04]
-
-v_div_fmas_f32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x01,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x83,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0xef,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0xfe,0x07]
-
-v_div_fmas_f32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x02,0x02]
-
-v_div_fmas_f32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x06,0x03]
-
-v_div_fmas_f32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0xc2,0x03]
-
-v_div_fmas_f32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f32 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x24]
-
-v_div_fmas_f32 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x44]
-
-v_div_fmas_f32 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x84]
-
-v_div_fmas_f32 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_div_fmas_f32 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x6f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x6f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x6f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x6f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x6f,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_div_fmas_f32 v5, v1, v2, v3 mul:4
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x14]
-
-v_div_fmas_f32 v5, v1, v2, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// GFX10: encoding: [0xfe,0x00,0x70,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0xfe,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], 0, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x80,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], -1, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0xfd,0x0f,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], 0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x01,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], -1, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x83,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0xef,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0xfa,0x07]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x02,0x02]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -1
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x06,0x03]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0.5
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0xc2,0x03]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -4.0
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x24]
-
-v_div_fmas_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x44]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x84]
-
-v_div_fmas_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0xe4]
-
-v_div_fmas_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// GFX10: encoding: [0x05,0x01,0x70,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// GFX10: encoding: [0x05,0x02,0x70,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// GFX10: encoding: [0x05,0x04,0x70,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// GFX10: encoding: [0x05,0x07,0x70,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// GFX10: encoding: [0x05,0x80,0x70,0xd5,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x0c]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x14]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x1c]
-
-v_msad_u8 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x0e,0x04]
-
-v_msad_u8 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x71,0xd5,0x01,0x05,0x0e,0x04]
-
-v_msad_u8 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0xff,0x05,0x0e,0x04]
-
-v_msad_u8 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x04,0x0e,0x04]
-
-v_msad_u8 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x67,0x04,0x0e,0x04]
-
-v_msad_u8 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_msad_u8 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_msad_u8 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x77,0x04,0x0e,0x04]
-
-v_msad_u8 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_msad_u8 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_msad_u8 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_msad_u8 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x80,0x04,0x0e,0x04]
-
-v_msad_u8 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_msad_u8 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_msad_u8 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_msad_u8 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xff,0x0f,0x04]
-
-v_msad_u8 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x0c,0x04]
-
-v_msad_u8 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_msad_u8 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_msad_u8 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_msad_u8 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xef,0x0c,0x04]
-
-v_msad_u8 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_msad_u8 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_msad_u8 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xff,0x0c,0x04]
-
-v_msad_u8 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x01,0x0d,0x04]
-
-v_msad_u8 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x83,0x0d,0x04]
-
-v_msad_u8 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_msad_u8 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xef,0x0d,0x04]
-
-v_msad_u8 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xfe,0x07]
-
-v_msad_u8 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x0e,0x00]
-
-v_msad_u8 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x9e,0x01]
-
-v_msad_u8 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xaa,0x01]
-
-v_msad_u8 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xae,0x01]
-
-v_msad_u8 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xde,0x01]
-
-v_msad_u8 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xf2,0x01]
-
-v_msad_u8 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xfa,0x01]
-
-v_msad_u8 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xfe,0x01]
-
-v_msad_u8 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x02,0x02]
-
-v_msad_u8 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x06,0x03]
-
-v_msad_u8 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xc2,0x03]
-
-v_msad_u8 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xde,0x03]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
-// GFX10: encoding: [0xfe,0x00,0x72,0xd5,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0xfe,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x02,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x04,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[102:103], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x66,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x76,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x80,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xff,0x0f,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], s103, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xef,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xff,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x01,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x83,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0xfa,0x07]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x1a,0x00]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x22,0x00]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[102:103]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x9a,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0xaa,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0xda,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0xfa,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x02,0x02]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
-// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x06,0x03]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
-// GFX10: encoding: [0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0xfe,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x02,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x04,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[102:103], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x66,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x76,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x80,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xff,0x0f,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], s103, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xef,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xff,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x01,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x83,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0xfa,0x07]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x1a,0x00]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x22,0x00]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[102:103]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x9a,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0xaa,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0xda,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0xfa,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x02,0x02]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
-// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x06,0x03]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[254:255], v[1:2], v2
-// GFX10: encoding: [0xfe,0x00,0x74,0xd5,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[254:255], v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0xfe,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[2:3], v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x02,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[4:5], v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x04,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[102:103], v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x66,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], vcc, v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x6a,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], ttmp[10:11], v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x76,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], exec, v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x7e,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], 0, v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x80,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], -1, v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0xc1,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0xf0,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0xf7,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v255
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xff,0x03,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], s2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], s103
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xcf,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], vcc_lo
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xd5,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], vcc_hi
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xd7,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], ttmp11
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xef,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], m0
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xf9,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], exec_lo
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xfd,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], exec_hi
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xff,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], 0
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x01,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], -1
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x83,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], 0.5
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xe1,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], -4.0
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xef,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], -v[1:2], v2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x20]
-
-v_trig_preop_f64 v[5:6], |v[1:2]|, v2
-// GFX10: encoding: [0x05,0x01,0x74,0xd5,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 clamp
-// GFX10: encoding: [0x05,0x80,0x74,0xd5,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 mul:2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x08]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 mul:4
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x10]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 div:2
-// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x18]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0x05,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[2:3], v2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x02,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[4:5], v2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x04,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[102:103], v2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x66,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], vcc, v2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], ttmp[10:11], v2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x76,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], exec, v2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], 0, v2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x80,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], -1, v2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], s2, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0x05,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], s103, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], vcc_lo, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], vcc_hi, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], ttmp11, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xef,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], m0, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], exec_lo, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], exec_hi, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xff,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], 0, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0x01,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], -1, v[3:6]
-// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0x83,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[254:255], s12, v1, v2, v[3:4]
-// W32: encoding: [0xfe,0x0c,0x76,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s14, v1, v2, v[3:4]
-// W32: encoding: [0x05,0x0e,0x76,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s100, v1, v2, v[3:4]
-// W32: encoding: [0x05,0x64,0x76,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v255, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0xff,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, s1, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, s101, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x65,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, vcc_lo, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x6a,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, vcc_hi, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x6b,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, m0, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x7c,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, exec_lo, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x7e,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, exec_hi, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x7f,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, 0, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x80,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, -1, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0xc1,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, 0.5, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0xf0,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, -4.0, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0xf7,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v255, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xff,0x0f,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, s2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, s101, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xcb,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, vcc_lo, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xd5,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, vcc_hi, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xd7,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, m0, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xf9,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, exec_lo, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xfd,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, exec_hi, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xff,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, 0, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x01,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, -1, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x83,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, 0.5, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xe1,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, -4.0, v[3:4]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xef,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, v[254:255]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xfa,0x07]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, s[6:7]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, s[8:9]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x22,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, s[100:101]
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x92,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, vcc
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xaa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, exec
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xfa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, 0
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x02,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, -1
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, 0.5
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xc2,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s12, v1, v2, -4.0
-// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xde,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[254:255], s[12:13], v1, v2, v[3:4]
-// W64: encoding: [0xfe,0x0c,0x76,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[14:15], v1, v2, v[3:4]
-// W64: encoding: [0x05,0x0e,0x76,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[100:101], v1, v2, v[3:4]
-// W64: encoding: [0x05,0x64,0x76,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v255, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0xff,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], s1, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], s101, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x65,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x6a,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x6b,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], m0, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x7c,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x7e,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x7f,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], 0, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x80,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], -1, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0xc1,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], 0.5, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0xf0,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], -4.0, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0xf7,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v255, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xff,0x0f,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, s2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, s101, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xcb,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xd5,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xd7,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, m0, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xf9,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xfd,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xff,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, 0, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x01,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, -1, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x83,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, 0.5, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xe1,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, -4.0, v[3:4]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xef,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[254:255]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xfa,0x07]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[8:9]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x22,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[100:101]
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x92,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, vcc
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xaa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, exec
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xfa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x02,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -1
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0.5
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xc2,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -4.0
-// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xde,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[254:255], s12, v1, v2, v[3:4]
-// W32: encoding: [0xfe,0x0c,0x77,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s14, v1, v2, v[3:4]
-// W32: encoding: [0x05,0x0e,0x77,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s100, v1, v2, v[3:4]
-// W32: encoding: [0x05,0x64,0x77,0xd5,0x01,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v255, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0xff,0x05,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, s1, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, s101, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x65,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, vcc_lo, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x6a,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, vcc_hi, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x6b,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, m0, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x7c,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, exec_lo, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x7e,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, exec_hi, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x7f,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, 0, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x80,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, -1, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0xc1,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, 0.5, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0xf0,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, -4.0, v2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0xf7,0x04,0x0e,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v255, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xff,0x0f,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, s2, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, s101, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xcb,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, vcc_lo, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xd5,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, vcc_hi, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xd7,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, m0, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xf9,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, exec_lo, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xfd,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, exec_hi, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xff,0x0c,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, 0, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x01,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, -1, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x83,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, 0.5, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xe1,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, -4.0, v[3:4]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xef,0x0d,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, v[254:255]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xfa,0x07]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, s[6:7]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x1a,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, s[8:9]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x22,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, s[100:101]
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x92,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, vcc
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xaa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, exec
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xfa,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, 0
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x02,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, -1
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, 0.5
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xc2,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s12, v1, v2, -4.0
-// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xde,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[254:255], s[12:13], v1, v2, v[3:4]
-// W64: encoding: [0xfe,0x0c,0x77,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[14:15], v1, v2, v[3:4]
-// W64: encoding: [0x05,0x0e,0x77,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[100:101], v1, v2, v[3:4]
-// W64: encoding: [0x05,0x64,0x77,0xd5,0x01,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v255, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0xff,0x05,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], s1, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], s101, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x65,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x6a,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x6b,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], m0, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x7c,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x7e,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x7f,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], 0, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x80,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], -1, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0xc1,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], 0.5, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0xf0,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], -4.0, v2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0xf7,0x04,0x0e,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v255, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xff,0x0f,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, s2, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, s101, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xcb,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xd5,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xd7,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, m0, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xf9,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xfd,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xff,0x0c,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, 0, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x01,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, -1, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x83,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, 0.5, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xe1,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, -4.0, v[3:4]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xef,0x0d,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[254:255]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xfa,0x07]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[6:7]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x1a,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[8:9]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x22,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[100:101]
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x92,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, vcc
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xaa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, exec
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xfa,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x02,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -1
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0.5
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xc2,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -4.0
-// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xde,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_xor3_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x0e,0x04]
-
-v_xor3_b32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x78,0xd5,0x01,0x05,0x0e,0x04]
-
-v_xor3_b32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0xff,0x05,0x0e,0x04]
-
-v_xor3_b32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, s103, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x67,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x6a,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x6b,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, ttmp11, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x77,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x7c,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x7e,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x7f,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x80,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0xc1,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0xf0,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0xf7,0x04,0x0e,0x04]
-
-v_xor3_b32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xff,0x0f,0x04]
-
-v_xor3_b32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x0c,0x04]
-
-v_xor3_b32 v5, v1, s103, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xcf,0x0c,0x04]
-
-v_xor3_b32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xd5,0x0c,0x04]
-
-v_xor3_b32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xd7,0x0c,0x04]
-
-v_xor3_b32 v5, v1, ttmp11, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xef,0x0c,0x04]
-
-v_xor3_b32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xf9,0x0c,0x04]
-
-v_xor3_b32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xfd,0x0c,0x04]
-
-v_xor3_b32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xff,0x0c,0x04]
-
-v_xor3_b32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x01,0x0d,0x04]
-
-v_xor3_b32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x83,0x0d,0x04]
-
-v_xor3_b32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xe1,0x0d,0x04]
-
-v_xor3_b32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xef,0x0d,0x04]
-
-v_xor3_b32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xfe,0x07]
-
-v_xor3_b32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x0e,0x00]
-
-v_xor3_b32 v5, v1, v2, s103
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x9e,0x01]
-
-v_xor3_b32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xaa,0x01]
-
-v_xor3_b32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xae,0x01]
-
-v_xor3_b32 v5, v1, v2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xde,0x01]
-
-v_xor3_b32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xf2,0x01]
-
-v_xor3_b32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xfa,0x01]
-
-v_xor3_b32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xfe,0x01]
-
-v_xor3_b32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x02,0x02]
-
-v_xor3_b32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x06,0x03]
-
-v_xor3_b32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xc2,0x03]
-
-v_xor3_b32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xde,0x03]
-
-v_lshlrev_b64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b64 v[254:255], v1, v[2:3]
-// GFX10: encoding: [0xfe,0x00,0xff,0xd6,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], v255, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], s1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], s101, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x65,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], vcc_lo, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], vcc_hi, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], m0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], exec_lo, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], exec_hi, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], 0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], -1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], 0.5, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0xf0,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], -4.0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0xf7,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], v1, v[254:255]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xfd,0x03,0x00]
-
-v_lshlrev_b64 v[5:6], v1, s[4:5]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x09,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, s[6:7]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x0d,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, s[100:101]
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xc9,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, vcc
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, exec
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, 0
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, -1
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, 0.5
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xe1,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, -4.0
-// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xef,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b64 v[254:255], v1, v[2:3]
-// GFX10: encoding: [0xfe,0x00,0x00,0xd7,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], v255, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], s1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], s101, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x65,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], vcc_lo, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], vcc_hi, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], m0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], exec_lo, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], exec_hi, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], 0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], -1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], 0.5, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0xf0,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], -4.0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0xf7,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], v1, v[254:255]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xfd,0x03,0x00]
-
-v_lshrrev_b64 v[5:6], v1, s[4:5]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x09,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, s[6:7]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x0d,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, s[100:101]
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xc9,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, vcc
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, exec
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, 0
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, -1
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xe1,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xef,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i64 v[254:255], v1, v[2:3]
-// GFX10: encoding: [0xfe,0x00,0x01,0xd7,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], v255, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], s1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], s101, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x65,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], vcc_lo, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], vcc_hi, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], m0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], exec_lo, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], exec_hi, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], 0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], -1, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], 0.5, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0xf0,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], -4.0, v[2:3]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0xf7,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], v1, v[254:255]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xfd,0x03,0x00]
-
-v_ashrrev_i64 v[5:6], v1, s[4:5]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x09,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, s[6:7]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x0d,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, s[100:101]
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xc9,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, vcc
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, exec
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, 0
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, -1
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xe1,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xef,0x01,0x00]
-
-v_add_nc_u16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
-
-v_add_nc_u16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
-
-v_add_nc_u16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0xff,0x05,0x02,0x00]
-
-v_add_nc_u16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x04,0x02,0x00]
-
-v_add_nc_u16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x65,0x04,0x02,0x00]
-
-v_add_nc_u16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00]
-
-v_add_nc_u16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00]
-
-v_add_nc_u16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x7c,0x04,0x02,0x00]
-
-v_add_nc_u16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x7e,0x04,0x02,0x00]
-
-v_add_nc_u16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x7f,0x04,0x02,0x00]
-
-v_add_nc_u16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x80,0x04,0x02,0x00]
-
-v_add_nc_u16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0xc1,0x04,0x02,0x00]
-
-v_add_nc_u16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_add_nc_u16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_add_nc_u16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x03,0x00]
-
-v_add_nc_u16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x00,0x00]
-
-v_add_nc_u16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xcb,0x00,0x00]
-
-v_add_nc_u16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xd5,0x00,0x00]
-
-v_add_nc_u16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xd7,0x00,0x00]
-
-v_add_nc_u16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xf9,0x00,0x00]
-
-v_add_nc_u16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xfd,0x00,0x00]
-
-v_add_nc_u16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x00,0x00]
-
-v_add_nc_u16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x01,0x01,0x00]
-
-v_add_nc_u16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x83,0x01,0x00]
-
-v_add_nc_u16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_add_nc_u16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_add_nc_u16 v5, v1, -4.0 clamp
-// GFX10: encoding: [0x05,0x80,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
-
-v_sub_nc_u16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
-
-v_sub_nc_u16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00]
-
-v_sub_nc_u16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x04,0x02,0x00]
-
-v_sub_nc_u16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x65,0x04,0x02,0x00]
-
-v_sub_nc_u16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00]
-
-v_sub_nc_u16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00]
-
-v_sub_nc_u16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x7c,0x04,0x02,0x00]
-
-v_sub_nc_u16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x7e,0x04,0x02,0x00]
-
-v_sub_nc_u16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x7f,0x04,0x02,0x00]
-
-v_sub_nc_u16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x80,0x04,0x02,0x00]
-
-v_sub_nc_u16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0xc1,0x04,0x02,0x00]
-
-v_sub_nc_u16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_sub_nc_u16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x03,0x00]
-
-v_sub_nc_u16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xcb,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xd5,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xd7,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xf9,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xfd,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x01,0x01,0x00]
-
-v_sub_nc_u16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x83,0x01,0x00]
-
-v_sub_nc_u16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_sub_nc_u16 v5, v1, -4.0 clamp
-// GFX10: encoding: [0x05,0x80,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0xff,0x05,0x02,0x00]
-
-v_mul_lo_u16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x04,0x02,0x00]
-
-v_mul_lo_u16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x65,0x04,0x02,0x00]
-
-v_mul_lo_u16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x6a,0x04,0x02,0x00]
-
-v_mul_lo_u16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x6b,0x04,0x02,0x00]
-
-v_mul_lo_u16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x7c,0x04,0x02,0x00]
-
-v_mul_lo_u16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x7e,0x04,0x02,0x00]
-
-v_mul_lo_u16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x7f,0x04,0x02,0x00]
-
-v_mul_lo_u16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x80,0x04,0x02,0x00]
-
-v_mul_lo_u16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0xc1,0x04,0x02,0x00]
-
-v_mul_lo_u16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_mul_lo_u16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x03,0x00]
-
-v_mul_lo_u16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xcb,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xd5,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xd7,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xf9,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xfd,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x01,0x01,0x00]
-
-v_mul_lo_u16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x83,0x01,0x00]
-
-v_mul_lo_u16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x65,0x04,0x02,0x00]
-
-v_lshrrev_b16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_lshrrev_b16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x03,0x00]
-
-v_lshrrev_b16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xcb,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xd7,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xf9,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x08,0xd7,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x65,0x04,0x02,0x00]
-
-v_ashrrev_i16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_ashrrev_i16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x03,0x00]
-
-v_ashrrev_i16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x05,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xcb,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xd7,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xf9,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_max_u16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
-
-v_max_u16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
-
-v_max_u16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0xff,0x05,0x02,0x00]
-
-v_max_u16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x04,0x02,0x00]
-
-v_max_u16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x65,0x04,0x02,0x00]
-
-v_max_u16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x6a,0x04,0x02,0x00]
-
-v_max_u16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x6b,0x04,0x02,0x00]
-
-v_max_u16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x7c,0x04,0x02,0x00]
-
-v_max_u16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x7e,0x04,0x02,0x00]
-
-v_max_u16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x7f,0x04,0x02,0x00]
-
-v_max_u16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x80,0x04,0x02,0x00]
-
-v_max_u16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0xc1,0x04,0x02,0x00]
-
-v_max_u16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_max_u16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_max_u16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x03,0x00]
-
-v_max_u16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x00,0x00]
-
-v_max_u16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xcb,0x00,0x00]
-
-v_max_u16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xd5,0x00,0x00]
-
-v_max_u16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xd7,0x00,0x00]
-
-v_max_u16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xf9,0x00,0x00]
-
-v_max_u16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xfd,0x00,0x00]
-
-v_max_u16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x00,0x00]
-
-v_max_u16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x01,0x01,0x00]
-
-v_max_u16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x83,0x01,0x00]
-
-v_max_u16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_max_u16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_max_i16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
-
-v_max_i16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
-
-v_max_i16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0xff,0x05,0x02,0x00]
-
-v_max_i16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x04,0x02,0x00]
-
-v_max_i16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x65,0x04,0x02,0x00]
-
-v_max_i16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x6a,0x04,0x02,0x00]
-
-v_max_i16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x6b,0x04,0x02,0x00]
-
-v_max_i16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x7c,0x04,0x02,0x00]
-
-v_max_i16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x7e,0x04,0x02,0x00]
-
-v_max_i16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x7f,0x04,0x02,0x00]
-
-v_max_i16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x80,0x04,0x02,0x00]
-
-v_max_i16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0xc1,0x04,0x02,0x00]
-
-v_max_i16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_max_i16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_max_i16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x03,0x00]
-
-v_max_i16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x00,0x00]
-
-v_max_i16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xcb,0x00,0x00]
-
-v_max_i16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xd5,0x00,0x00]
-
-v_max_i16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xd7,0x00,0x00]
-
-v_max_i16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xf9,0x00,0x00]
-
-v_max_i16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xfd,0x00,0x00]
-
-v_max_i16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x00,0x00]
-
-v_max_i16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x01,0x01,0x00]
-
-v_max_i16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x83,0x01,0x00]
-
-v_max_i16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_max_i16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_min_u16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
-
-v_min_u16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
-
-v_min_u16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0xff,0x05,0x02,0x00]
-
-v_min_u16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x04,0x02,0x00]
-
-v_min_u16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x65,0x04,0x02,0x00]
-
-v_min_u16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x6a,0x04,0x02,0x00]
-
-v_min_u16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x6b,0x04,0x02,0x00]
-
-v_min_u16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x7c,0x04,0x02,0x00]
-
-v_min_u16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x7e,0x04,0x02,0x00]
-
-v_min_u16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x7f,0x04,0x02,0x00]
-
-v_min_u16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x80,0x04,0x02,0x00]
-
-v_min_u16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0xc1,0x04,0x02,0x00]
-
-v_min_u16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_min_u16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_min_u16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x03,0x00]
-
-v_min_u16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x00,0x00]
-
-v_min_u16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xcb,0x00,0x00]
-
-v_min_u16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xd5,0x00,0x00]
-
-v_min_u16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xd7,0x00,0x00]
-
-v_min_u16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xf9,0x00,0x00]
-
-v_min_u16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xfd,0x00,0x00]
-
-v_min_u16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x00,0x00]
-
-v_min_u16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x01,0x01,0x00]
-
-v_min_u16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x83,0x01,0x00]
-
-v_min_u16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_min_u16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_min_i16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
-
-v_min_i16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
-
-v_min_i16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0xff,0x05,0x02,0x00]
-
-v_min_i16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x04,0x02,0x00]
-
-v_min_i16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x65,0x04,0x02,0x00]
-
-v_min_i16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x6a,0x04,0x02,0x00]
-
-v_min_i16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x6b,0x04,0x02,0x00]
-
-v_min_i16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x7c,0x04,0x02,0x00]
-
-v_min_i16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x7e,0x04,0x02,0x00]
-
-v_min_i16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x7f,0x04,0x02,0x00]
-
-v_min_i16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x80,0x04,0x02,0x00]
-
-v_min_i16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0xc1,0x04,0x02,0x00]
-
-v_min_i16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_min_i16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_min_i16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x03,0x00]
-
-v_min_i16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x00,0x00]
-
-v_min_i16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xcb,0x00,0x00]
-
-v_min_i16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xd5,0x00,0x00]
-
-v_min_i16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xd7,0x00,0x00]
-
-v_min_i16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xf9,0x00,0x00]
-
-v_min_i16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xfd,0x00,0x00]
-
-v_min_i16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x00,0x00]
-
-v_min_i16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x01,0x01,0x00]
-
-v_min_i16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x83,0x01,0x00]
-
-v_min_i16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_min_i16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_add_nc_i16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x05,0x02,0x00]
-
-v_add_nc_i16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x0d,0xd7,0x01,0x05,0x02,0x00]
-
-v_add_nc_i16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0xff,0x05,0x02,0x00]
-
-v_add_nc_i16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x04,0x02,0x00]
-
-v_add_nc_i16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x65,0x04,0x02,0x00]
-
-v_add_nc_i16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x6a,0x04,0x02,0x00]
-
-v_add_nc_i16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x6b,0x04,0x02,0x00]
-
-v_add_nc_i16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x7c,0x04,0x02,0x00]
-
-v_add_nc_i16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x7e,0x04,0x02,0x00]
-
-v_add_nc_i16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x7f,0x04,0x02,0x00]
-
-v_add_nc_i16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x80,0x04,0x02,0x00]
-
-v_add_nc_i16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0xc1,0x04,0x02,0x00]
-
-v_add_nc_i16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_add_nc_i16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_add_nc_i16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x03,0x00]
-
-v_add_nc_i16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x05,0x00,0x00]
-
-v_add_nc_i16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xcb,0x00,0x00]
-
-v_add_nc_i16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xd5,0x00,0x00]
-
-v_add_nc_i16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xd7,0x00,0x00]
-
-v_add_nc_i16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xf9,0x00,0x00]
-
-v_add_nc_i16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xfd,0x00,0x00]
-
-v_add_nc_i16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x00,0x00]
-
-v_add_nc_i16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x01,0x01,0x00]
-
-v_add_nc_i16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x83,0x01,0x00]
-
-v_add_nc_i16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_add_nc_i16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x05,0x02,0x00]
-
-v_sub_nc_i16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x0e,0xd7,0x01,0x05,0x02,0x00]
-
-v_sub_nc_i16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0xff,0x05,0x02,0x00]
-
-v_sub_nc_i16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x04,0x02,0x00]
-
-v_sub_nc_i16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x65,0x04,0x02,0x00]
-
-v_sub_nc_i16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x6a,0x04,0x02,0x00]
-
-v_sub_nc_i16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x6b,0x04,0x02,0x00]
-
-v_sub_nc_i16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x7c,0x04,0x02,0x00]
-
-v_sub_nc_i16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x7e,0x04,0x02,0x00]
-
-v_sub_nc_i16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x7f,0x04,0x02,0x00]
-
-v_sub_nc_i16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x80,0x04,0x02,0x00]
-
-v_sub_nc_i16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0xc1,0x04,0x02,0x00]
-
-v_sub_nc_i16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_sub_nc_i16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xff,0x03,0x00]
-
-v_sub_nc_i16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x05,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xcb,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xd5,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xd7,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xf9,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xfd,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xff,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x01,0x01,0x00]
-
-v_sub_nc_i16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x83,0x01,0x00]
-
-v_sub_nc_i16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_sub_nc_i16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0xff,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x65,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x6a,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x6b,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x7c,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x7e,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x7f,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x80,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0xc1,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0xf0,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0xf7,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xff,0x03,0x00]
-
-v_pack_b32_f16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xcb,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xd5,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xd7,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xf9,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xfd,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xff,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x01,0x01,0x00]
-
-v_pack_b32_f16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x83,0x01,0x00]
-
-v_pack_b32_f16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xe1,0x01,0x00]
-
-v_pack_b32_f16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xef,0x01,0x00]
-
-v_pack_b32_f16 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x20]
-
-v_pack_b32_f16 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x40]
-
-v_pack_b32_f16 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x60]
-
-v_pack_b32_f16 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,0]
-// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[1,0,0]
-// GFX10: encoding: [0x05,0x08,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[0,1,0]
-// GFX10: encoding: [0x05,0x10,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,1]
-// GFX10: encoding: [0x05,0x40,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[1,1,1]
-// GFX10: encoding: [0x05,0x58,0x11,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x65,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xcb,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_i16_f16 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_i16_f16 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_i16_f16 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_i16_f16 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,0]
-// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,0,0]
-// GFX10: encoding: [0x05,0x08,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,1,0]
-// GFX10: encoding: [0x05,0x10,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,1]
-// GFX10: encoding: [0x05,0x40,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,1,1]
-// GFX10: encoding: [0x05,0x58,0x12,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x65,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xcb,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_u16_f16 v5, -v1, v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_u16_f16 v5, v1, -v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_u16_f16 v5, -v1, -v2
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_u16_f16 v5, |v1|, v2
-// GFX10: encoding: [0x05,0x01,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, |v2|
-// GFX10: encoding: [0x05,0x02,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, |v1|, |v2|
-// GFX10: encoding: [0x05,0x03,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,0]
-// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,0,0]
-// GFX10: encoding: [0x05,0x08,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,1,0]
-// GFX10: encoding: [0x05,0x10,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,1]
-// GFX10: encoding: [0x05,0x40,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1]
-// GFX10: encoding: [0x05,0x58,0x13,0xd7,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b16 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b16 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x14,0xd7,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b16 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b16 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b16 v5, s101, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x65,0x04,0x02,0x00]
-
-v_lshlrev_b16 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b16 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b16 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b16 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b16 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b16 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b16 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b16 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_lshlrev_b16 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x03,0x00]
-
-v_lshlrev_b16 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x05,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, s101
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xcb,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xd7,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xf9,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b16 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b16 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_mad_u16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd7,0x80,0x04,0x0e,0x04]
-
-v_mad_u16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x40,0xd7,0x01,0x83,0x0d,0x04]
-
-v_mad_u16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x40,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
-
-v_mad_u16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x40,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x40,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x40,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x40,0xd7,0x01,0x05,0x0e,0x04]
-
-v_interp_p1ll_f16 v5, v2, attr31.x
-// GFX10: encoding: [0x05,0x00,0x42,0xd7,0x1f,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.w
-// GFX10: encoding: [0x05,0x00,0x42,0xd7,0xc0,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, -v2, attr0.x
-// GFX10: encoding: [0x05,0x00,0x42,0xd7,0x00,0x04,0x02,0x40]
-
-v_interp_p1ll_f16 v5, |v2|, attr0.x
-// GFX10: encoding: [0x05,0x02,0x42,0xd7,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x high
-// GFX10: encoding: [0x05,0x00,0x42,0xd7,0x00,0x05,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x clamp
-// GFX10: encoding: [0x05,0x80,0x42,0xd7,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x mul:4
-// GFX10: encoding: [0x05,0x00,0x42,0xd7,0x00,0x04,0x02,0x10]
-
-v_interp_p1lv_f16 v5, v2, attr1.x, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x01,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.z, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x80,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, -v2, attr0.x, v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x04,0x0e,0x44]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, -v3
-// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x04,0x0e,0x84]
-
-v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
-// GFX10: encoding: [0x05,0x02,0x43,0xd7,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
-// GFX10: encoding: [0x05,0x04,0x43,0xd7,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
-// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x05,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x43,0xd7,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
-// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x04,0x0e,0x0c]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
-// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x04,0x0e,0x1c]
-
-v_perm_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x0e,0x04]
-
-v_perm_b32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x44,0xd7,0x01,0x05,0x0e,0x04]
-
-v_perm_b32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0xff,0x05,0x0e,0x04]
-
-v_perm_b32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x04,0x0e,0x04]
-
-v_perm_b32 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x65,0x04,0x0e,0x04]
-
-v_perm_b32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_perm_b32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_perm_b32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_perm_b32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_perm_b32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_perm_b32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x80,0x04,0x0e,0x04]
-
-v_perm_b32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_perm_b32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_perm_b32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_perm_b32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xff,0x0f,0x04]
-
-v_perm_b32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x0c,0x04]
-
-v_perm_b32 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_perm_b32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_perm_b32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_perm_b32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_perm_b32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_perm_b32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xff,0x0c,0x04]
-
-v_perm_b32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x01,0x0d,0x04]
-
-v_perm_b32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x83,0x0d,0x04]
-
-v_perm_b32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_perm_b32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xef,0x0d,0x04]
-
-v_perm_b32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xfe,0x07]
-
-v_perm_b32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x0e,0x00]
-
-v_perm_b32 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x96,0x01]
-
-v_perm_b32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xaa,0x01]
-
-v_perm_b32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xae,0x01]
-
-v_perm_b32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xf2,0x01]
-
-v_perm_b32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xfa,0x01]
-
-v_perm_b32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xfe,0x01]
-
-v_perm_b32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x02,0x02]
-
-v_perm_b32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x06,0x03]
-
-v_perm_b32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xc2,0x03]
-
-v_perm_b32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xde,0x03]
-
-v_xad_u32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x0e,0x04]
-
-v_xad_u32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x45,0xd7,0x01,0x05,0x0e,0x04]
-
-v_xad_u32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0xff,0x05,0x0e,0x04]
-
-v_xad_u32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x04,0x0e,0x04]
-
-v_xad_u32 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x65,0x04,0x0e,0x04]
-
-v_xad_u32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_xad_u32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_xad_u32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_xad_u32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_xad_u32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_xad_u32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x80,0x04,0x0e,0x04]
-
-v_xad_u32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_xad_u32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_xad_u32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_xad_u32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xff,0x0f,0x04]
-
-v_xad_u32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x0c,0x04]
-
-v_xad_u32 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_xad_u32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_xad_u32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_xad_u32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_xad_u32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_xad_u32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xff,0x0c,0x04]
-
-v_xad_u32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x01,0x0d,0x04]
-
-v_xad_u32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x83,0x0d,0x04]
-
-v_xad_u32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_xad_u32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xef,0x0d,0x04]
-
-v_xad_u32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xfe,0x07]
-
-v_xad_u32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x0e,0x00]
-
-v_xad_u32 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x96,0x01]
-
-v_xad_u32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xaa,0x01]
-
-v_xad_u32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xae,0x01]
-
-v_xad_u32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xf2,0x01]
-
-v_xad_u32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xfa,0x01]
-
-v_xad_u32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xfe,0x01]
-
-v_xad_u32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x02,0x02]
-
-v_xad_u32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x06,0x03]
-
-v_xad_u32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xc2,0x03]
-
-v_xad_u32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xde,0x03]
-
-v_lshl_add_u32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x0e,0x04]
-
-v_lshl_add_u32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x46,0xd7,0x01,0x05,0x0e,0x04]
-
-v_lshl_add_u32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0xff,0x05,0x0e,0x04]
-
-v_lshl_add_u32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x65,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x80,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xff,0x0f,0x04]
-
-v_lshl_add_u32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xff,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x01,0x0d,0x04]
-
-v_lshl_add_u32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x83,0x0d,0x04]
-
-v_lshl_add_u32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_lshl_add_u32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xef,0x0d,0x04]
-
-v_lshl_add_u32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xfe,0x07]
-
-v_lshl_add_u32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x0e,0x00]
-
-v_lshl_add_u32 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x96,0x01]
-
-v_lshl_add_u32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xaa,0x01]
-
-v_lshl_add_u32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xae,0x01]
-
-v_lshl_add_u32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xf2,0x01]
-
-v_lshl_add_u32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xfa,0x01]
-
-v_lshl_add_u32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xfe,0x01]
-
-v_lshl_add_u32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x02,0x02]
-
-v_lshl_add_u32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x06,0x03]
-
-v_lshl_add_u32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xc2,0x03]
-
-v_lshl_add_u32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xde,0x03]
-
-v_add_lshl_u32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x0e,0x04]
-
-v_add_lshl_u32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x47,0xd7,0x01,0x05,0x0e,0x04]
-
-v_add_lshl_u32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0xff,0x05,0x0e,0x04]
-
-v_add_lshl_u32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x65,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x80,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xff,0x0f,0x04]
-
-v_add_lshl_u32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xff,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x01,0x0d,0x04]
-
-v_add_lshl_u32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x83,0x0d,0x04]
-
-v_add_lshl_u32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_add_lshl_u32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xef,0x0d,0x04]
-
-v_add_lshl_u32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xfe,0x07]
-
-v_add_lshl_u32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x0e,0x00]
-
-v_add_lshl_u32 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x96,0x01]
-
-v_add_lshl_u32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xaa,0x01]
-
-v_add_lshl_u32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xae,0x01]
-
-v_add_lshl_u32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xf2,0x01]
-
-v_add_lshl_u32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xfa,0x01]
-
-v_add_lshl_u32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xfe,0x01]
-
-v_add_lshl_u32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x02,0x02]
-
-v_add_lshl_u32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x06,0x03]
-
-v_add_lshl_u32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xc2,0x03]
-
-v_add_lshl_u32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xde,0x03]
-
-v_fma_f16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd7,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x4b,0xd7,0x01,0x05,0x0e,0x44]
-
-v_fma_f16 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x4b,0xd7,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x4b,0xd7,0x01,0x05,0x0e,0x04]
-
-// FIXME-GFX10-V_FMA_F16: See "FIXME-GFX10-V_FMA_F16" in VOP3Instructions.td.
-// v_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// FIXME-GFX10-V_FMA_F16: encoding: [0x05,0x08,0x4b,0xd7,0x01,0x05,0x0e,0x04]
-
-// v_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// FIXME-GFX10-V_FMA_F16: encoding: [0x05,0x10,0x4b,0xd7,0x01,0x05,0x0e,0x04]
-
-// v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// FIXME-GFX10-V_FMA_F16: encoding: [0x05,0x78,0x4b,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0xff,0x05,0x0e,0x04]
-
-v_min3_f16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x04,0x0e,0x04]
-
-v_min3_f16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x65,0x04,0x0e,0x04]
-
-v_min3_f16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_min3_f16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_min3_f16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_min3_f16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_min3_f16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_min3_f16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x80,0x04,0x0e,0x04]
-
-v_min3_f16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_min3_f16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_min3_f16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_min3_f16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xff,0x0f,0x04]
-
-v_min3_f16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0c,0x04]
-
-v_min3_f16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_min3_f16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_min3_f16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_min3_f16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_min3_f16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_min3_f16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xff,0x0c,0x04]
-
-v_min3_f16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x01,0x0d,0x04]
-
-v_min3_f16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x83,0x0d,0x04]
-
-v_min3_f16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_min3_f16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xef,0x0d,0x04]
-
-v_min3_f16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xfe,0x07]
-
-v_min3_f16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x00]
-
-v_min3_f16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x96,0x01]
-
-v_min3_f16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xaa,0x01]
-
-v_min3_f16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xae,0x01]
-
-v_min3_f16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xf2,0x01]
-
-v_min3_f16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xfa,0x01]
-
-v_min3_f16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xfe,0x01]
-
-v_min3_f16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x02,0x02]
-
-v_min3_f16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x06,0x03]
-
-v_min3_f16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xc2,0x03]
-
-v_min3_f16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xde,0x03]
-
-v_min3_f16 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x24]
-
-v_min3_f16 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x44]
-
-v_min3_f16 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x84]
-
-v_min3_f16 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0xe4]
-
-v_min3_f16 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x51,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x52,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0xff,0x05,0x0e,0x04]
-
-v_min3_i16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x04,0x0e,0x04]
-
-v_min3_i16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x65,0x04,0x0e,0x04]
-
-v_min3_i16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_min3_i16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_min3_i16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_min3_i16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_min3_i16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_min3_i16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x80,0x04,0x0e,0x04]
-
-v_min3_i16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_min3_i16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
-
-v_min3_i16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
-
-v_min3_i16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0f,0x04]
-
-v_min3_i16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x0c,0x04]
-
-v_min3_i16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_min3_i16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_min3_i16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_min3_i16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_min3_i16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_min3_i16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0c,0x04]
-
-v_min3_i16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x01,0x0d,0x04]
-
-v_min3_i16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x83,0x0d,0x04]
-
-v_min3_i16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
-
-v_min3_i16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
-
-v_min3_i16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x07]
-
-v_min3_i16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x0e,0x00]
-
-v_min3_i16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x96,0x01]
-
-v_min3_i16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xaa,0x01]
-
-v_min3_i16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xae,0x01]
-
-v_min3_i16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xf2,0x01]
-
-v_min3_i16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfa,0x01]
-
-v_min3_i16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x01]
-
-v_min3_i16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x02,0x02]
-
-v_min3_i16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x06,0x03]
-
-v_min3_i16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
-
-v_min3_i16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x52,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x52,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x52,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x52,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x52,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x52,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x53,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0xff,0x05,0x0e,0x04]
-
-v_min3_u16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x04,0x0e,0x04]
-
-v_min3_u16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x65,0x04,0x0e,0x04]
-
-v_min3_u16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_min3_u16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_min3_u16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_min3_u16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_min3_u16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_min3_u16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x80,0x04,0x0e,0x04]
-
-v_min3_u16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_min3_u16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
-
-v_min3_u16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
-
-v_min3_u16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xff,0x0f,0x04]
-
-v_min3_u16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x0c,0x04]
-
-v_min3_u16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_min3_u16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_min3_u16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_min3_u16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_min3_u16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_min3_u16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xff,0x0c,0x04]
-
-v_min3_u16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x01,0x0d,0x04]
-
-v_min3_u16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x83,0x0d,0x04]
-
-v_min3_u16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
-
-v_min3_u16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
-
-v_min3_u16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfe,0x07]
-
-v_min3_u16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x0e,0x00]
-
-v_min3_u16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x96,0x01]
-
-v_min3_u16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xaa,0x01]
-
-v_min3_u16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xae,0x01]
-
-v_min3_u16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xf2,0x01]
-
-v_min3_u16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfa,0x01]
-
-v_min3_u16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfe,0x01]
-
-v_min3_u16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x02,0x02]
-
-v_min3_u16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x06,0x03]
-
-v_min3_u16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
-
-v_min3_u16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x53,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x53,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x53,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x53,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x53,0xd7,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x53,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0xff,0x05,0x0e,0x04]
-
-v_max3_f16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x04,0x0e,0x04]
-
-v_max3_f16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x65,0x04,0x0e,0x04]
-
-v_max3_f16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_max3_f16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_max3_f16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_max3_f16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_max3_f16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_max3_f16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x80,0x04,0x0e,0x04]
-
-v_max3_f16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_max3_f16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_max3_f16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_max3_f16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xff,0x0f,0x04]
-
-v_max3_f16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0c,0x04]
-
-v_max3_f16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_max3_f16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_max3_f16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_max3_f16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_max3_f16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_max3_f16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xff,0x0c,0x04]
-
-v_max3_f16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x01,0x0d,0x04]
-
-v_max3_f16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x83,0x0d,0x04]
-
-v_max3_f16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_max3_f16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xef,0x0d,0x04]
-
-v_max3_f16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xfe,0x07]
-
-v_max3_f16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x00]
-
-v_max3_f16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x96,0x01]
-
-v_max3_f16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xaa,0x01]
-
-v_max3_f16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xae,0x01]
-
-v_max3_f16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xf2,0x01]
-
-v_max3_f16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xfa,0x01]
-
-v_max3_f16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xfe,0x01]
-
-v_max3_f16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x02,0x02]
-
-v_max3_f16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x06,0x03]
-
-v_max3_f16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xc2,0x03]
-
-v_max3_f16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xde,0x03]
-
-v_max3_f16 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x24]
-
-v_max3_f16 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x44]
-
-v_max3_f16 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x84]
-
-v_max3_f16 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0xe4]
-
-v_max3_f16 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x54,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x55,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0xff,0x05,0x0e,0x04]
-
-v_max3_i16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x04,0x0e,0x04]
-
-v_max3_i16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x65,0x04,0x0e,0x04]
-
-v_max3_i16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_max3_i16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_max3_i16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_max3_i16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_max3_i16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_max3_i16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x80,0x04,0x0e,0x04]
-
-v_max3_i16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_max3_i16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
-
-v_max3_i16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
-
-v_max3_i16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xff,0x0f,0x04]
-
-v_max3_i16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x0c,0x04]
-
-v_max3_i16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_max3_i16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_max3_i16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_max3_i16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_max3_i16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_max3_i16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xff,0x0c,0x04]
-
-v_max3_i16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x01,0x0d,0x04]
-
-v_max3_i16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x83,0x0d,0x04]
-
-v_max3_i16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
-
-v_max3_i16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
-
-v_max3_i16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfe,0x07]
-
-v_max3_i16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x0e,0x00]
-
-v_max3_i16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x96,0x01]
-
-v_max3_i16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xaa,0x01]
-
-v_max3_i16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xae,0x01]
-
-v_max3_i16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xf2,0x01]
-
-v_max3_i16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfa,0x01]
-
-v_max3_i16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfe,0x01]
-
-v_max3_i16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x02,0x02]
-
-v_max3_i16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x06,0x03]
-
-v_max3_i16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
-
-v_max3_i16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x55,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x55,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x55,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x55,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x55,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x55,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x56,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0xff,0x05,0x0e,0x04]
-
-v_max3_u16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x04,0x0e,0x04]
-
-v_max3_u16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x65,0x04,0x0e,0x04]
-
-v_max3_u16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_max3_u16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_max3_u16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_max3_u16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_max3_u16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_max3_u16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x80,0x04,0x0e,0x04]
-
-v_max3_u16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_max3_u16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
-
-v_max3_u16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
-
-v_max3_u16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xff,0x0f,0x04]
-
-v_max3_u16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x0c,0x04]
-
-v_max3_u16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_max3_u16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_max3_u16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_max3_u16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_max3_u16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_max3_u16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xff,0x0c,0x04]
-
-v_max3_u16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x01,0x0d,0x04]
-
-v_max3_u16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x83,0x0d,0x04]
-
-v_max3_u16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
-
-v_max3_u16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
-
-v_max3_u16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfe,0x07]
-
-v_max3_u16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x0e,0x00]
-
-v_max3_u16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x96,0x01]
-
-v_max3_u16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xaa,0x01]
-
-v_max3_u16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xae,0x01]
-
-v_max3_u16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xf2,0x01]
-
-v_max3_u16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfa,0x01]
-
-v_max3_u16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfe,0x01]
-
-v_max3_u16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x02,0x02]
-
-v_max3_u16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x06,0x03]
-
-v_max3_u16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
-
-v_max3_u16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x56,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x56,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x56,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x56,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x56,0xd7,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x56,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0xff,0x05,0x0e,0x04]
-
-v_med3_f16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x04,0x0e,0x04]
-
-v_med3_f16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x65,0x04,0x0e,0x04]
-
-v_med3_f16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_med3_f16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_med3_f16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_med3_f16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_med3_f16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_med3_f16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x80,0x04,0x0e,0x04]
-
-v_med3_f16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_med3_f16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_med3_f16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_med3_f16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xff,0x0f,0x04]
-
-v_med3_f16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0c,0x04]
-
-v_med3_f16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_med3_f16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_med3_f16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_med3_f16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_med3_f16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_med3_f16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xff,0x0c,0x04]
-
-v_med3_f16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x01,0x0d,0x04]
-
-v_med3_f16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x83,0x0d,0x04]
-
-v_med3_f16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_med3_f16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xef,0x0d,0x04]
-
-v_med3_f16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xfe,0x07]
-
-v_med3_f16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x00]
-
-v_med3_f16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x96,0x01]
-
-v_med3_f16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xaa,0x01]
-
-v_med3_f16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xae,0x01]
-
-v_med3_f16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xf2,0x01]
-
-v_med3_f16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xfa,0x01]
-
-v_med3_f16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xfe,0x01]
-
-v_med3_f16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x02,0x02]
-
-v_med3_f16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x06,0x03]
-
-v_med3_f16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xc2,0x03]
-
-v_med3_f16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xde,0x03]
-
-v_med3_f16 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x24]
-
-v_med3_f16 v5, v1, -v2, v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x44]
-
-v_med3_f16 v5, v1, v2, -v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x84]
-
-v_med3_f16 v5, -v1, -v2, -v3
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0xe4]
-
-v_med3_f16 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, |v2|, v3
-// GFX10: encoding: [0x05,0x02,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, |v3|
-// GFX10: encoding: [0x05,0x04,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, |v1|, |v2|, |v3|
-// GFX10: encoding: [0x05,0x07,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x57,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x58,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0xff,0x05,0x0e,0x04]
-
-v_med3_i16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x04,0x0e,0x04]
-
-v_med3_i16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x65,0x04,0x0e,0x04]
-
-v_med3_i16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_med3_i16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_med3_i16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_med3_i16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_med3_i16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_med3_i16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x80,0x04,0x0e,0x04]
-
-v_med3_i16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_med3_i16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
-
-v_med3_i16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
-
-v_med3_i16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xff,0x0f,0x04]
-
-v_med3_i16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x0c,0x04]
-
-v_med3_i16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_med3_i16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_med3_i16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_med3_i16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_med3_i16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_med3_i16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xff,0x0c,0x04]
-
-v_med3_i16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x01,0x0d,0x04]
-
-v_med3_i16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x83,0x0d,0x04]
-
-v_med3_i16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
-
-v_med3_i16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
-
-v_med3_i16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfe,0x07]
-
-v_med3_i16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x0e,0x00]
-
-v_med3_i16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x96,0x01]
-
-v_med3_i16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xaa,0x01]
-
-v_med3_i16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xae,0x01]
-
-v_med3_i16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xf2,0x01]
-
-v_med3_i16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfa,0x01]
-
-v_med3_i16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfe,0x01]
-
-v_med3_i16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x02,0x02]
-
-v_med3_i16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x06,0x03]
-
-v_med3_i16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
-
-v_med3_i16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x58,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x58,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x58,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x58,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x58,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x58,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x59,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0xff,0x05,0x0e,0x04]
-
-v_med3_u16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x04,0x0e,0x04]
-
-v_med3_u16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x65,0x04,0x0e,0x04]
-
-v_med3_u16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_med3_u16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_med3_u16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_med3_u16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_med3_u16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_med3_u16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x80,0x04,0x0e,0x04]
-
-v_med3_u16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_med3_u16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
-
-v_med3_u16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
-
-v_med3_u16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xff,0x0f,0x04]
-
-v_med3_u16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x0c,0x04]
-
-v_med3_u16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_med3_u16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_med3_u16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_med3_u16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_med3_u16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_med3_u16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xff,0x0c,0x04]
-
-v_med3_u16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x01,0x0d,0x04]
-
-v_med3_u16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x83,0x0d,0x04]
-
-v_med3_u16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
-
-v_med3_u16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
-
-v_med3_u16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfe,0x07]
-
-v_med3_u16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x0e,0x00]
-
-v_med3_u16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x96,0x01]
-
-v_med3_u16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xaa,0x01]
-
-v_med3_u16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xae,0x01]
-
-v_med3_u16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xf2,0x01]
-
-v_med3_u16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfa,0x01]
-
-v_med3_u16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfe,0x01]
-
-v_med3_u16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x02,0x02]
-
-v_med3_u16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x06,0x03]
-
-v_med3_u16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
-
-v_med3_u16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x59,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x59,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x59,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x59,0xd7,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x59,0xd7,0x01,0x05,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd7,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, -v2, attr0.x, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd7,0x00,0x04,0x0e,0x44]
-
-v_interp_p2_f16 v5, v2, attr0.x, |v3|
-// GFX10: encoding: [0x05,0x04,0x5a,0xd7,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.w, v3
-// GFX10: encoding: [0x05,0x00,0x5a,0xd7,0xc0,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v3 high
-// GFX10: encoding: [0x05,0x00,0x5a,0xd7,0x00,0x05,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x5a,0xd7,0x00,0x04,0x0e,0x04]
-
-v_mad_i16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd7,0x80,0x04,0x0e,0x04]
-
-v_mad_i16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x5e,0xd7,0x01,0x83,0x0d,0x04]
-
-v_mad_i16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x5e,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
-
-v_mad_i16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x5e,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x5e,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x5e,0xd7,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x5f,0xd7,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f16 v5, -v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x5f,0xd7,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f16 v5, |v1|, v2, v3
-// GFX10: encoding: [0x05,0x01,0x5f,0xd7,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x5f,0xd7,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x5f,0xd7,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x5f,0xd7,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x5f,0xd7,0x01,0x05,0x0e,0x04]
-
-v_add3_u32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x0e,0x04]
-
-v_add3_u32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x6d,0xd7,0x01,0x05,0x0e,0x04]
-
-v_add3_u32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0xff,0x05,0x0e,0x04]
-
-v_add3_u32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x04,0x0e,0x04]
-
-v_add3_u32 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x65,0x04,0x0e,0x04]
-
-v_add3_u32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_add3_u32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_add3_u32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_add3_u32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_add3_u32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_add3_u32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x80,0x04,0x0e,0x04]
-
-v_add3_u32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_add3_u32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_add3_u32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_add3_u32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xff,0x0f,0x04]
-
-v_add3_u32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x0c,0x04]
-
-v_add3_u32 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_add3_u32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_add3_u32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_add3_u32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_add3_u32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_add3_u32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xff,0x0c,0x04]
-
-v_add3_u32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x01,0x0d,0x04]
-
-v_add3_u32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x83,0x0d,0x04]
-
-v_add3_u32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_add3_u32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xef,0x0d,0x04]
-
-v_add3_u32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xfe,0x07]
-
-v_add3_u32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x0e,0x00]
-
-v_add3_u32 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x96,0x01]
-
-v_add3_u32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xaa,0x01]
-
-v_add3_u32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xae,0x01]
-
-v_add3_u32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xf2,0x01]
-
-v_add3_u32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xfa,0x01]
-
-v_add3_u32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xfe,0x01]
-
-v_add3_u32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x02,0x02]
-
-v_add3_u32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x06,0x03]
-
-v_add3_u32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xc2,0x03]
-
-v_add3_u32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xde,0x03]
-
-v_lshl_or_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x0e,0x04]
-
-v_lshl_or_b32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x6f,0xd7,0x01,0x05,0x0e,0x04]
-
-v_lshl_or_b32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0xff,0x05,0x0e,0x04]
-
-v_lshl_or_b32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x65,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x80,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xff,0x0f,0x04]
-
-v_lshl_or_b32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xff,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x01,0x0d,0x04]
-
-v_lshl_or_b32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x83,0x0d,0x04]
-
-v_lshl_or_b32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_lshl_or_b32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xef,0x0d,0x04]
-
-v_lshl_or_b32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xfe,0x07]
-
-v_lshl_or_b32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x0e,0x00]
-
-v_lshl_or_b32 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x96,0x01]
-
-v_lshl_or_b32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xaa,0x01]
-
-v_lshl_or_b32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xae,0x01]
-
-v_lshl_or_b32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xf2,0x01]
-
-v_lshl_or_b32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xfa,0x01]
-
-v_lshl_or_b32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xfe,0x01]
-
-v_lshl_or_b32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x02,0x02]
-
-v_lshl_or_b32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x06,0x03]
-
-v_lshl_or_b32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xc2,0x03]
-
-v_lshl_or_b32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xde,0x03]
-
-v_and_or_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x0e,0x04]
-
-v_and_or_b32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x71,0xd7,0x01,0x05,0x0e,0x04]
-
-v_and_or_b32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0xff,0x05,0x0e,0x04]
-
-v_and_or_b32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x65,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x80,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xff,0x0f,0x04]
-
-v_and_or_b32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x0c,0x04]
-
-v_and_or_b32 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_and_or_b32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_and_or_b32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_and_or_b32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_and_or_b32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_and_or_b32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xff,0x0c,0x04]
-
-v_and_or_b32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x01,0x0d,0x04]
-
-v_and_or_b32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x83,0x0d,0x04]
-
-v_and_or_b32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_and_or_b32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xef,0x0d,0x04]
-
-v_and_or_b32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xfe,0x07]
-
-v_and_or_b32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x0e,0x00]
-
-v_and_or_b32 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x96,0x01]
-
-v_and_or_b32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xaa,0x01]
-
-v_and_or_b32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xae,0x01]
-
-v_and_or_b32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xf2,0x01]
-
-v_and_or_b32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xfa,0x01]
-
-v_and_or_b32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xfe,0x01]
-
-v_and_or_b32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x02,0x02]
-
-v_and_or_b32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x06,0x03]
-
-v_and_or_b32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xc2,0x03]
-
-v_and_or_b32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xde,0x03]
-
-v_or3_b32 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x0e,0x04]
-
-v_or3_b32 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x72,0xd7,0x01,0x05,0x0e,0x04]
-
-v_or3_b32 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0xff,0x05,0x0e,0x04]
-
-v_or3_b32 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x04,0x0e,0x04]
-
-v_or3_b32 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x65,0x04,0x0e,0x04]
-
-v_or3_b32 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_or3_b32 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_or3_b32 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_or3_b32 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_or3_b32 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_or3_b32 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x80,0x04,0x0e,0x04]
-
-v_or3_b32 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_or3_b32 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0xf0,0x04,0x0e,0x04]
-
-v_or3_b32 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0xf7,0x04,0x0e,0x04]
-
-v_or3_b32 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xff,0x0f,0x04]
-
-v_or3_b32 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x0c,0x04]
-
-v_or3_b32 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_or3_b32 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_or3_b32 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_or3_b32 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_or3_b32 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_or3_b32 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xff,0x0c,0x04]
-
-v_or3_b32 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x01,0x0d,0x04]
-
-v_or3_b32 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x83,0x0d,0x04]
-
-v_or3_b32 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xe1,0x0d,0x04]
-
-v_or3_b32 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xef,0x0d,0x04]
-
-v_or3_b32 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xfe,0x07]
-
-v_or3_b32 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x0e,0x00]
-
-v_or3_b32 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x96,0x01]
-
-v_or3_b32 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xaa,0x01]
-
-v_or3_b32 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xae,0x01]
-
-v_or3_b32 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xf2,0x01]
-
-v_or3_b32 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xfa,0x01]
-
-v_or3_b32 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xfe,0x01]
-
-v_or3_b32 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x02,0x02]
-
-v_or3_b32 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x06,0x03]
-
-v_or3_b32 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xc2,0x03]
-
-v_or3_b32 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xde,0x03]
-
-v_mad_u32_u16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x73,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0xff,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x65,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x80,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
-
-v_mad_u32_u16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
-
-v_mad_u32_u16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xff,0x0f,0x04]
-
-v_mad_u32_u16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xff,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x01,0x0d,0x04]
-
-v_mad_u32_u16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x83,0x0d,0x04]
-
-v_mad_u32_u16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
-
-v_mad_u32_u16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
-
-v_mad_u32_u16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xfe,0x07]
-
-v_mad_u32_u16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x0e,0x00]
-
-v_mad_u32_u16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x96,0x01]
-
-v_mad_u32_u16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xaa,0x01]
-
-v_mad_u32_u16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xae,0x01]
-
-v_mad_u32_u16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xf2,0x01]
-
-v_mad_u32_u16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xfa,0x01]
-
-v_mad_u32_u16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xfe,0x01]
-
-v_mad_u32_u16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x02,0x02]
-
-v_mad_u32_u16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x06,0x03]
-
-v_mad_u32_u16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xc2,0x03]
-
-v_mad_u32_u16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xde,0x03]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x73,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x73,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x73,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x73,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x73,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x73,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v255, v1, v2, v3
-// GFX10: encoding: [0xff,0x00,0x75,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v255, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0xff,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, s1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, s101, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x65,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, vcc_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x6a,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, vcc_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x6b,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, m0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x7c,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, exec_lo, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x7e,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, exec_hi, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x7f,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, 0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x80,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, -1, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0xc1,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, 0.5, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
-
-v_mad_i32_i16 v5, -4.0, v2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
-
-v_mad_i32_i16 v5, v1, v255, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xff,0x0f,0x04]
-
-v_mad_i32_i16 v5, v1, s2, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, s101, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xcb,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, vcc_lo, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xd5,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, vcc_hi, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xd7,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, m0, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xf9,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, exec_lo, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xfd,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, exec_hi, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xff,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, 0, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x01,0x0d,0x04]
-
-v_mad_i32_i16 v5, v1, -1, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x83,0x0d,0x04]
-
-v_mad_i32_i16 v5, v1, 0.5, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
-
-v_mad_i32_i16 v5, v1, -4.0, v3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
-
-v_mad_i32_i16 v5, v1, v2, v255
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xfe,0x07]
-
-v_mad_i32_i16 v5, v1, v2, s3
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x0e,0x00]
-
-v_mad_i32_i16 v5, v1, v2, s101
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x96,0x01]
-
-v_mad_i32_i16 v5, v1, v2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xaa,0x01]
-
-v_mad_i32_i16 v5, v1, v2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xae,0x01]
-
-v_mad_i32_i16 v5, v1, v2, m0
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xf2,0x01]
-
-v_mad_i32_i16 v5, v1, v2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xfa,0x01]
-
-v_mad_i32_i16 v5, v1, v2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xfe,0x01]
-
-v_mad_i32_i16 v5, v1, v2, 0
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x02,0x02]
-
-v_mad_i32_i16 v5, v1, v2, -1
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x06,0x03]
-
-v_mad_i32_i16 v5, v1, v2, 0.5
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xc2,0x03]
-
-v_mad_i32_i16 v5, v1, v2, -4.0
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xde,0x03]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// GFX10: encoding: [0x05,0x08,0x75,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// GFX10: encoding: [0x05,0x10,0x75,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// GFX10: encoding: [0x05,0x20,0x75,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// GFX10: encoding: [0x05,0x40,0x75,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// GFX10: encoding: [0x05,0x78,0x75,0xd7,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 clamp
-// GFX10: encoding: [0x05,0x80,0x75,0xd7,0x01,0x05,0x0e,0x04]
-
-v_sub_nc_i32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x05,0x02,0x00]
-
-v_sub_nc_i32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x76,0xd7,0x01,0x05,0x02,0x00]
-
-v_sub_nc_i32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0xff,0x05,0x02,0x00]
-
-v_sub_nc_i32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x67,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x6b,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x77,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x7c,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x7e,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x7f,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x80,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0xc1,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0xf0,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0xf7,0x04,0x02,0x00]
-
-v_sub_nc_i32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xff,0x03,0x00]
-
-v_sub_nc_i32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x05,0x00,0x00]
-
-v_sub_nc_i32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xcf,0x00,0x00]
-
-v_sub_nc_i32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xd5,0x00,0x00]
-
-v_sub_nc_i32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xd7,0x00,0x00]
-
-v_sub_nc_i32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xef,0x00,0x00]
-
-v_sub_nc_i32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xf9,0x00,0x00]
-
-v_sub_nc_i32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xfd,0x00,0x00]
-
-v_sub_nc_i32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xff,0x00,0x00]
-
-v_sub_nc_i32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x01,0x01,0x00]
-
-v_sub_nc_i32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x83,0x01,0x00]
-
-v_sub_nc_i32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xe1,0x01,0x00]
-
-v_sub_nc_i32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xef,0x01,0x00]
-
-v_sub_nc_i32 v5, v1, -4.0 clamp
-// GFX10: v_sub_nc_i32 v5, v1, -4.0 clamp ; encoding: [0x05,0x80,0x76,0xd7,0x01,0xef,0x01,0x00]
-
-v_permlane16_b32 v5, v1, v2, v3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlane16_b32 v5, v1, v2, s3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlane16_b32 v5, v1, s2, v3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlane16_b32 v5, s1, s2, s3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlane16_b32 v5, 0, s2, s3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlane16_b32 v5, v1, s2, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlane16_b32 v255, v1, s2, s3
-// GFX10: encoding: [0xff,0x00,0x77,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlane16_b32 v5, v255, s2, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0xff,0x05,0x0c,0x00]
-
-v_permlane16_b32 v5, v103, s2, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x67,0x05,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, vcc_lo, s2
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xd5,0x08,0x00]
-
-v_permlane16_b32 v5, v1, vcc_hi, s2
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xd7,0x08,0x00]
-
-v_permlane16_b32 v5, v1, ttmp11, s2
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xef,0x08,0x00]
-
-v_permlane16_b32 v5, v1, m0, s2
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xf9,0x08,0x00]
-
-v_permlane16_b32 v5, v1, exec_lo, s2
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xfd,0x08,0x00]
-
-v_permlane16_b32 v5, v1, exec_hi, s2
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xff,0x08,0x00]
-
-v_permlane16_b32 v5, v1, s103, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xcf,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, vcc_lo, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xd5,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, vcc_hi, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xd7,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, ttmp11, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xef,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, m0, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xf9,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, exec_lo, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xfd,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, exec_hi, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xff,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, 0, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x01,0x0d,0x00]
-
-v_permlane16_b32 v5, v1, -1, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x83,0x0d,0x00]
-
-v_permlane16_b32 v5, v1, 0.5, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xe1,0x0d,0x00]
-
-v_permlane16_b32 v5, v1, -4.0, s3
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xef,0x0d,0x00]
-
-v_permlane16_b32 v5, v1, s2, s103
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x9c,0x01]
-
-v_permlane16_b32 v5, v1, s2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xa8,0x01]
-
-v_permlane16_b32 v5, v1, s2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xac,0x01]
-
-v_permlane16_b32 v5, v1, s2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x01]
-
-v_permlane16_b32 v5, v1, s2, m0
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xf0,0x01]
-
-v_permlane16_b32 v5, v1, s2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xf8,0x01]
-
-v_permlane16_b32 v5, v1, s2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xfc,0x01]
-
-v_permlane16_b32 v5, v1, s2, 0
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x00,0x02]
-
-v_permlane16_b32 v5, v1, s2, -1
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x04,0x03]
-
-v_permlane16_b32 v5, v1, s2, 0.5
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xc0,0x03]
-
-v_permlane16_b32 v5, v1, s2, -4.0
-// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x03]
-
-v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,0]
-// GFX10: encoding: [0x05,0x08,0x77,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,1]
-// GFX10: encoding: [0x05,0x18,0x77,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, s2, s3 op_sel:[0,1]
-// GFX10: encoding: [0x05,0x10,0x77,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
-
-v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 1, 0]
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
-
-v_permlanex16_b32 v5, v1, v2, v3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlanex16_b32 v5, v1, v2, s3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlanex16_b32 v5, v1, s2, v3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlanex16_b32 v5, s1, s2, s3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlanex16_b32 v5, 0, s2, s3
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_permlanex16_b32 v5, v1, s2, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlanex16_b32 v255, v1, s2, s3
-// GFX10: encoding: [0xff,0x00,0x78,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlanex16_b32 v5, v255, s2, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0xff,0x05,0x0c,0x00]
-
-v_permlanex16_b32 v5, v103, s2, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x67,0x05,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, vcc_lo, s2
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xd5,0x08,0x00]
-
-v_permlanex16_b32 v5, v1, vcc_hi, s2
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xd7,0x08,0x00]
-
-v_permlanex16_b32 v5, v1, ttmp11, s2
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xef,0x08,0x00]
-
-v_permlanex16_b32 v5, v1, m0, s2
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xf9,0x08,0x00]
-
-v_permlanex16_b32 v5, v1, exec_lo, s2
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xfd,0x08,0x00]
-
-v_permlanex16_b32 v5, v1, exec_hi, s2
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xff,0x08,0x00]
-
-v_permlanex16_b32 v5, v1, s103, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xcf,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, vcc_lo, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xd5,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, vcc_hi, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xd7,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, ttmp11, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xef,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, m0, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xf9,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, exec_lo, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xfd,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, exec_hi, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xff,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, 0, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x01,0x0d,0x00]
-
-v_permlanex16_b32 v5, v1, -1, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x83,0x0d,0x00]
-
-v_permlanex16_b32 v5, v1, 0.5, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xe1,0x0d,0x00]
-
-v_permlanex16_b32 v5, v1, -4.0, s3
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xef,0x0d,0x00]
-
-v_permlanex16_b32 v5, v1, s2, s103
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x9c,0x01]
-
-v_permlanex16_b32 v5, v1, s2, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xa8,0x01]
-
-v_permlanex16_b32 v5, v1, s2, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xac,0x01]
-
-v_permlanex16_b32 v5, v1, s2, ttmp11
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x01]
-
-v_permlanex16_b32 v5, v1, s2, m0
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xf0,0x01]
-
-v_permlanex16_b32 v5, v1, s2, exec_lo
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xf8,0x01]
-
-v_permlanex16_b32 v5, v1, s2, exec_hi
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xfc,0x01]
-
-v_permlanex16_b32 v5, v1, s2, 0
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x00,0x02]
-
-v_permlanex16_b32 v5, v1, s2, -1
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x04,0x03]
-
-v_permlanex16_b32 v5, v1, s2, 0.5
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xc0,0x03]
-
-v_permlanex16_b32 v5, v1, s2, -4.0
-// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x03]
-
-v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,0]
-// GFX10: encoding: [0x05,0x08,0x78,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,1]
-// GFX10: encoding: [0x05,0x18,0x78,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0,1]
-// GFX10: encoding: [0x05,0x10,0x78,0xd7,0x01,0x05,0x0c,0x00]
-
-v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
-
-v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0, 0, 1, 0]
-// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
-
-v_add_nc_i32 v5, v1, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x05,0x02,0x00]
-
-v_add_nc_i32 v255, v1, v2
-// GFX10: encoding: [0xff,0x00,0x7f,0xd7,0x01,0x05,0x02,0x00]
-
-v_add_nc_i32 v5, v255, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0xff,0x05,0x02,0x00]
-
-v_add_nc_i32 v5, s1, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, s103, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x67,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, vcc_lo, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, vcc_hi, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x6b,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, ttmp11, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x77,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, m0, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x7c,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, exec_lo, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x7e,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, exec_hi, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x7f,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, 0, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x80,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, -1, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0xc1,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, 0.5, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0xf0,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, -4.0, v2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0xf7,0x04,0x02,0x00]
-
-v_add_nc_i32 v5, v1, v255
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xff,0x03,0x00]
-
-v_add_nc_i32 v5, v1, s2
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x05,0x00,0x00]
-
-v_add_nc_i32 v5, v1, s103
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xcf,0x00,0x00]
-
-v_add_nc_i32 v5, v1, vcc_lo
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xd5,0x00,0x00]
-
-v_add_nc_i32 v5, v1, vcc_hi
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xd7,0x00,0x00]
-
-v_add_nc_i32 v5, v1, ttmp11
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xef,0x00,0x00]
-
-v_add_nc_i32 v5, v1, m0
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xf9,0x00,0x00]
-
-v_add_nc_i32 v5, v1, exec_lo
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xfd,0x00,0x00]
-
-v_add_nc_i32 v5, v1, exec_hi
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xff,0x00,0x00]
-
-v_add_nc_i32 v5, v1, 0
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x01,0x01,0x00]
-
-v_add_nc_i32 v5, v1, -1
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x83,0x01,0x00]
-
-v_add_nc_i32 v5, v1, 0.5
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xe1,0x01,0x00]
-
-v_add_nc_i32 v5, v1, -4.0
-// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xef,0x01,0x00]
-
-v_add_nc_i32 v5, v1, -4.0 clamp
-// GFX10: v_add_nc_i32 v5, v1, -4.0 clamp ; encoding: [0x05,0x80,0x7f,0xd7,0x01,0xef,0x01,0x00]
-
-v_pk_fmac_f16 v5, v1, v2
-// GFX10: encoding: [0x01,0x05,0x0a,0x78]
-
-v_pk_fmac_f16 v255, v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x79]
-
-v_pk_fmac_f16 v5, v255, v2
-// GFX10: encoding: [0xff,0x05,0x0a,0x78]
-
-v_pk_fmac_f16 v5, s1, v2
-// GFX10: encoding: [0x01,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, s103, v2
-// GFX10: encoding: [0x67,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, ttmp11, v2
-// GFX10: encoding: [0x77,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, m0, v2
-// GFX10: encoding: [0x7c,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, 0, v2
-// GFX10: encoding: [0x80,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, -1, v2
-// GFX10: encoding: [0xc1,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x0a,0x78]
-
-v_pk_fmac_f16 v5, v1, v255
-// GFX10: encoding: [0x01,0xff,0x0b,0x78]
-
-//===----------------------------------------------------------------------===//
-// ENC_VOPC.
-//===----------------------------------------------------------------------===//
-
-v_cmp_f_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x00,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x00,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x00,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x01,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x01,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x00,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x00,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x00,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x01,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x00,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x01,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x02,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x02,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x02,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x03,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x03,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x02,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x02,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x02,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x03,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x01,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x03,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x04,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x04,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x04,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x05,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x05,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x04,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x04,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x04,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x05,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x02,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x05,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x06,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x06,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x06,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x07,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x07,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x06,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x06,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x06,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x07,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x03,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x07,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x08,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x08,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x08,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x09,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x09,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x08,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x08,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x08,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x09,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x04,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x09,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x0a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x0a,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x0a,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x0b,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x0b,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x0a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x0a,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x0a,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x0b,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x05,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x0b,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x0c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x0c,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x0c,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x0d,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x0d,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x0c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x0c,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x0c,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x0d,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x06,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x0d,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x0e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x0e,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x0e,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x0f,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x0f,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x0e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x0e,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x0e,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x0f,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x07,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x0f,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x10,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x10,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x10,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x11,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x11,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x10,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x10,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x10,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x11,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x08,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x11,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x12,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x12,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x12,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x13,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x13,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x12,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x12,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x12,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x13,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x09,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x13,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x14,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x14,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x14,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x15,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x15,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x14,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x14,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x14,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x15,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x0a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x15,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x16,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x16,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x16,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x17,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x17,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x16,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x16,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x16,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x17,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x0b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x17,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x18,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x18,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x18,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x19,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x19,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x18,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x18,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x18,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x19,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x0c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x19,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x1a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x1a,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x1a,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x1b,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x1b,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x1a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x1a,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x1a,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x1b,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x0d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x1b,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x1c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x1c,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x1c,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x1d,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x1d,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x1c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x1c,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x1c,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x1d,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x0e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x1d,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x1e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x1e,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x1e,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x1f,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x1f,0x7c,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x1e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x1e,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x1e,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x1f,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0x0f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x1f,0x7c,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmpx_f_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x20,0x7c]
-
-v_cmpx_f_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x20,0x7c]
-
-v_cmpx_f_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x20,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x20,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x21,0x7c]
-
-v_cmpx_f_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x22,0x7c]
-
-v_cmpx_lt_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x22,0x7c]
-
-v_cmpx_lt_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x22,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x22,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x23,0x7c]
-
-v_cmpx_lt_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x24,0x7c]
-
-v_cmpx_eq_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x24,0x7c]
-
-v_cmpx_eq_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x24,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x24,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x25,0x7c]
-
-v_cmpx_eq_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x26,0x7c]
-
-v_cmpx_le_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x26,0x7c]
-
-v_cmpx_le_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x26,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x26,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x27,0x7c]
-
-v_cmpx_le_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x28,0x7c]
-
-v_cmpx_gt_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x28,0x7c]
-
-v_cmpx_gt_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x28,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x28,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x29,0x7c]
-
-v_cmpx_gt_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x2a,0x7c]
-
-v_cmpx_lg_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x2a,0x7c]
-
-v_cmpx_lg_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x2a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lg_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x2a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lg_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x2b,0x7c]
-
-v_cmpx_lg_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_lg_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_lg_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lg_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lg_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lg_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_lg_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x2c,0x7c]
-
-v_cmpx_ge_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x2c,0x7c]
-
-v_cmpx_ge_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x2c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x2c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x2d,0x7c]
-
-v_cmpx_ge_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x2e,0x7c]
-
-v_cmpx_o_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x2e,0x7c]
-
-v_cmpx_o_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x2e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_o_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x2e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_o_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x2f,0x7c]
-
-v_cmpx_o_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_o_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_o_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_o_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_o_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_o_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_o_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x30,0x7c]
-
-v_cmpx_u_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x30,0x7c]
-
-v_cmpx_u_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x30,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_u_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x30,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_u_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x31,0x7c]
-
-v_cmpx_u_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_u_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_u_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_u_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_u_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_u_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_u_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x32,0x7c]
-
-v_cmpx_nge_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x32,0x7c]
-
-v_cmpx_nge_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x32,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nge_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x32,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nge_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x33,0x7c]
-
-v_cmpx_nge_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_nge_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_nge_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nge_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nge_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nge_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_nge_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x34,0x7c]
-
-v_cmpx_nlg_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x34,0x7c]
-
-v_cmpx_nlg_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x34,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlg_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x34,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlg_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x35,0x7c]
-
-v_cmpx_nlg_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlg_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x36,0x7c]
-
-v_cmpx_ngt_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x36,0x7c]
-
-v_cmpx_ngt_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x36,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ngt_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x36,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ngt_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x37,0x7c]
-
-v_cmpx_ngt_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ngt_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x38,0x7c]
-
-v_cmpx_nle_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x38,0x7c]
-
-v_cmpx_nle_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x38,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nle_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x38,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nle_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x39,0x7c]
-
-v_cmpx_nle_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_nle_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_nle_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nle_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nle_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nle_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_nle_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x3a,0x7c]
-
-v_cmpx_neq_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x3a,0x7c]
-
-v_cmpx_neq_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x3a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_neq_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x3a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_neq_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x3b,0x7c]
-
-v_cmpx_neq_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_neq_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_neq_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_neq_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_neq_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_neq_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_neq_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x3c,0x7c]
-
-v_cmpx_nlt_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x3c,0x7c]
-
-v_cmpx_nlt_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x3c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlt_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x3c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlt_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x3d,0x7c]
-
-v_cmpx_nlt_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlt_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x3e,0x7c]
-
-v_cmpx_tru_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x3e,0x7c]
-
-v_cmpx_tru_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x3e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_tru_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x3e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_tru_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x3f,0x7c]
-
-v_cmpx_tru_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_tru_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_tru_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_tru_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_tru_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_tru_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_tru_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f32_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f32_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_f_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_f_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_f_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_f_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_f_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_f_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x21,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_f_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_f_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x23,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_lt_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_lt_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x25,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_eq_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_eq_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_le_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_le_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_le_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_le_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_le_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_le_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x27,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_le_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_le_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x29,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_gt_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_gt_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x2b,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_lg_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_lg_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_lg_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_lg_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x2d,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_ge_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_ge_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_o_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_o_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_o_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_o_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_o_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_o_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_o_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x2f,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_o_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_o_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_o_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_o_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_u_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_u_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_u_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_u_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_u_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_u_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_u_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x31,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_u_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_u_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_u_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_u_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x33,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nge_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nge_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nge_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nge_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x35,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nlg_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nlg_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nlg_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nlg_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x37,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_ngt_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_ngt_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_ngt_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_ngt_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x39,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nle_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nle_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nle_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nle_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x3b,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_neq_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_neq_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_neq_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_neq_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x3d,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nlt_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nlt_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nlt_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nlt_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x65,0x00,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x6a,0x00,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x6b,0x00,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x7c,0x00,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x7e,0x00,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x7f,0x00,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x3f,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_tru_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_tru_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_tru_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_tru_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_f_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x40,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x40,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x40,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x41,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x40,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x40,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x40,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x41,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x20,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x42,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x42,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x42,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x43,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x42,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x42,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x42,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x43,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x21,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x44,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x44,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x44,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x45,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x44,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x44,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x44,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x45,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x22,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x46,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x46,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x46,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x47,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x46,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x46,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x46,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x47,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x23,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x48,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x48,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x48,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x49,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x48,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x48,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x48,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x49,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x24,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x4a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x4a,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x4b,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x4a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x4a,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x4b,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x25,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x4c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x4c,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x4d,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x4c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x4c,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x4d,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x26,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x4e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x4e,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x4f,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x4e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x4e,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x4f,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x27,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x50,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x50,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x50,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x51,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x50,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x50,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x50,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x51,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x28,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x52,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x52,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x52,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x53,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x52,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x52,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x52,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x53,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x29,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x54,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x54,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x54,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x55,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x54,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x54,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x54,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x55,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x2a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x56,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x56,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x56,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x57,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x56,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x56,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x56,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x57,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x2b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x58,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x58,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x58,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x59,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x58,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x58,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x58,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x59,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x2c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x5a,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x5a,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x5b,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x5a,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x5a,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x5b,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x2d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x5c,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x5c,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x5d,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x5c,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x5c,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x5d,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x2e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x5e,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x5e,0x7c,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x5f,0x7c]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// W64: encoding: [0x0a,0x80,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x5e,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x5e,0x7c,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x5f,0x7c]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, -v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, -v[1:2], -v[2:3]
-// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f64_e64 s10, v[1:2], v[2:3] clamp
-// W32: encoding: [0x0a,0x80,0x2f,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmpx_f_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x60,0x7c]
-
-v_cmpx_f_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x60,0x7c]
-
-v_cmpx_f_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x60,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x60,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x61,0x7c]
-
-v_cmpx_f_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_f_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x62,0x7c]
-
-v_cmpx_lt_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x62,0x7c]
-
-v_cmpx_lt_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x62,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x62,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x63,0x7c]
-
-v_cmpx_lt_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x64,0x7c]
-
-v_cmpx_eq_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x64,0x7c]
-
-v_cmpx_eq_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x64,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x64,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x65,0x7c]
-
-v_cmpx_eq_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_eq_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x66,0x7c]
-
-v_cmpx_le_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x66,0x7c]
-
-v_cmpx_le_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x66,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x66,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x67,0x7c]
-
-v_cmpx_le_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_le_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x68,0x7c]
-
-v_cmpx_gt_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x68,0x7c]
-
-v_cmpx_gt_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x68,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x68,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x69,0x7c]
-
-v_cmpx_gt_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_gt_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x6a,0x7c]
-
-v_cmpx_lg_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x6a,0x7c]
-
-v_cmpx_lg_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lg_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lg_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x6b,0x7c]
-
-v_cmpx_lg_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_lg_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x6c,0x7c]
-
-v_cmpx_ge_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x6c,0x7c]
-
-v_cmpx_ge_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x6d,0x7c]
-
-v_cmpx_ge_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_ge_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x6e,0x7c]
-
-v_cmpx_o_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x6e,0x7c]
-
-v_cmpx_o_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_o_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_o_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x6f,0x7c]
-
-v_cmpx_o_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_o_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x70,0x7c]
-
-v_cmpx_u_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x70,0x7c]
-
-v_cmpx_u_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x70,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_u_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x70,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_u_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x71,0x7c]
-
-v_cmpx_u_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_u_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x72,0x7c]
-
-v_cmpx_nge_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x72,0x7c]
-
-v_cmpx_nge_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x72,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nge_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x72,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nge_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x73,0x7c]
-
-v_cmpx_nge_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_nge_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x74,0x7c]
-
-v_cmpx_nlg_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x74,0x7c]
-
-v_cmpx_nlg_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x74,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlg_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x74,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlg_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x75,0x7c]
-
-v_cmpx_nlg_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x76,0x7c]
-
-v_cmpx_ngt_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x76,0x7c]
-
-v_cmpx_ngt_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x76,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ngt_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x76,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ngt_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x77,0x7c]
-
-v_cmpx_ngt_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x78,0x7c]
-
-v_cmpx_nle_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x78,0x7c]
-
-v_cmpx_nle_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x78,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nle_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x78,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nle_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x79,0x7c]
-
-v_cmpx_nle_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_nle_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x7a,0x7c]
-
-v_cmpx_neq_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x7a,0x7c]
-
-v_cmpx_neq_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x7a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_neq_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x7a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_neq_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x7b,0x7c]
-
-v_cmpx_neq_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_neq_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x7c,0x7c]
-
-v_cmpx_nlt_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x7c,0x7c]
-
-v_cmpx_nlt_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x7c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlt_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x7c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlt_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x7d,0x7c]
-
-v_cmpx_nlt_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x7e,0x7c]
-
-v_cmpx_tru_f64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x7e,0x7c]
-
-v_cmpx_tru_f64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x7e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_tru_f64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x7e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_tru_f64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x7f,0x7c]
-
-v_cmpx_tru_f64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 exec, v[1:2]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x7e,0x02,0x02,0x00]
-
-v_cmpx_tru_f64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f64_e64 -v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f64_e64 v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f64_e64 -v[1:2], -v[2:3]
-// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmp_f_i32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x00,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x00,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x00,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x01,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x02,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x02,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x02,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x03,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x04,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x04,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x04,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x05,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x06,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x06,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x06,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x07,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x08,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x08,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x08,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x09,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x0a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x0a,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x0a,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x0b,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x0c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x0c,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x0c,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x0d,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x0e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x0e,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x0e,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x0f,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x01,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x03,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x05,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x07,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x09,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x0b,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x0d,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x0f,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x00,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x00,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x00,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x01,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x02,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x02,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x02,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x03,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x04,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x04,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x04,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x05,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x06,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x06,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x06,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x07,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x08,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x08,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x08,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x09,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x0a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x0a,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x0a,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x0b,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x0c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x0c,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x0c,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x0d,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x0e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x0e,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x0e,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x0f,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x01,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x03,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x05,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x07,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x09,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x0b,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x0d,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x0f,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x10,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x10,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x10,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x11,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x11,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x10,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x10,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x10,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x11,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x11,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x12,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x12,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x12,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x12,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x12,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x13,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x14,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x14,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x14,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x14,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x14,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x15,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x16,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x16,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x16,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x16,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x16,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x17,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x18,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x18,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x18,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x18,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x18,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x19,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x1a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x1a,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x1a,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x1a,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x1a,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x1b,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x1c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x1c,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x1c,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x1c,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x1c,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x1d,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x13,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x15,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x17,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x19,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x1b,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x1d,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x12,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x12,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x12,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x12,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x12,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x13,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x14,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x14,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x14,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x14,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x14,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x15,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x16,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x16,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x16,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x16,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x16,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x17,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x18,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x18,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x18,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x18,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x18,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x19,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x1a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x1a,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x1a,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x1a,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x1a,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x1b,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x1c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x1c,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x1c,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x1c,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x1c,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x1d,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x13,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x15,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x17,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x19,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x1b,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x1d,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x1e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x1e,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x1e,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x1f,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0x8f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0x8f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0x8f,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x1f,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmpx_f_i32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x20,0x7d]
-
-v_cmpx_f_i32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x20,0x7d]
-
-v_cmpx_f_i32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 0, v2
-// GFX10: encoding: [0x80,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x20,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_i32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x20,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_i32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x21,0x7d]
-
-v_cmpx_f_i32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_i32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_i32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_i32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_i32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_i32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_i32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_i32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_i32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x22,0x7d]
-
-v_cmpx_lt_i32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x22,0x7d]
-
-v_cmpx_lt_i32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 0, v2
-// GFX10: encoding: [0x80,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x22,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_i32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x22,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_i32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x23,0x7d]
-
-v_cmpx_lt_i32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_i32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_i32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_i32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_i32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_i32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_i32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_i32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_i32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x24,0x7d]
-
-v_cmpx_eq_i32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x24,0x7d]
-
-v_cmpx_eq_i32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 0, v2
-// GFX10: encoding: [0x80,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x24,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_i32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x24,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_i32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x25,0x7d]
-
-v_cmpx_eq_i32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_i32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_i32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_i32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_i32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_i32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_i32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_i32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_i32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x26,0x7d]
-
-v_cmpx_le_i32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x26,0x7d]
-
-v_cmpx_le_i32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 0, v2
-// GFX10: encoding: [0x80,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x26,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_i32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x26,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_i32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x27,0x7d]
-
-v_cmpx_le_i32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_i32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_i32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_i32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_i32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_i32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_i32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_i32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_i32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x28,0x7d]
-
-v_cmpx_gt_i32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x28,0x7d]
-
-v_cmpx_gt_i32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 0, v2
-// GFX10: encoding: [0x80,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x28,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_i32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x28,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_i32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x29,0x7d]
-
-v_cmpx_gt_i32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_i32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_i32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_i32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_i32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_i32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_i32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_i32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_i32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x2a,0x7d]
-
-v_cmpx_ne_i32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x2a,0x7d]
-
-v_cmpx_ne_i32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 0, v2
-// GFX10: encoding: [0x80,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x2a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_i32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x2a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_i32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x2b,0x7d]
-
-v_cmpx_ne_i32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_i32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_i32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_i32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_i32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_i32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_i32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_i32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_i32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x2c,0x7d]
-
-v_cmpx_ge_i32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x2c,0x7d]
-
-v_cmpx_ge_i32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 0, v2
-// GFX10: encoding: [0x80,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x2c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_i32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x2c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_i32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x2d,0x7d]
-
-v_cmpx_ge_i32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_i32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_i32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_i32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_i32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_i32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_i32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_i32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_i32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x2e,0x7d]
-
-v_cmpx_t_i32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x2e,0x7d]
-
-v_cmpx_t_i32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 0, v2
-// GFX10: encoding: [0x80,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x2e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_i32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x2e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_i32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x2f,0x7d]
-
-v_cmpx_t_i32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_i32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_i32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_i32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_i32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_i32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_i32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_i32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f32 v1, v2
-// GFX10: encoding: [0x01,0x05,0x30,0x7d]
-
-v_cmpx_class_f32 v255, v2
-// GFX10: encoding: [0xff,0x05,0x30,0x7d]
-
-v_cmpx_class_f32 s1, v2
-// GFX10: encoding: [0x01,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 s101, v2
-// GFX10: encoding: [0x65,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 0, v2
-// GFX10: encoding: [0x80,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x30,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_class_f32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x30,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_class_f32 v1, v255
-// GFX10: encoding: [0x01,0xff,0x31,0x7d]
-
-v_cmpx_class_f32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_class_f32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f32_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_i16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x32,0x7d]
-
-v_cmpx_lt_i16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x32,0x7d]
-
-v_cmpx_lt_i16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x32,0x7d]
-
-v_cmpx_lt_i16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x32,0x7d]
-
-v_cmpx_lt_i16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x32,0x7d]
-
-v_cmpx_lt_i16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x32,0x7d]
-
-v_cmpx_lt_i16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x32,0x7d]
-
-v_cmpx_lt_i16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x32,0x7d]
-
-v_cmpx_lt_i16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x32,0x7d]
-
-v_cmpx_lt_i16 0, v2
-// GFX10: encoding: [0x80,0x04,0x32,0x7d]
-
-v_cmpx_lt_i16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x32,0x7d]
-
-v_cmpx_lt_i16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x32,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_i16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x32,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_lt_i16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x32,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lt_i16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x32,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_lt_i16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x33,0x7d]
-
-v_cmpx_lt_i16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_i16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_lt_i16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_i16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_i16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_i16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_i16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_i16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_i16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_i16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_i16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x34,0x7d]
-
-v_cmpx_eq_i16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x34,0x7d]
-
-v_cmpx_eq_i16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x34,0x7d]
-
-v_cmpx_eq_i16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x34,0x7d]
-
-v_cmpx_eq_i16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x34,0x7d]
-
-v_cmpx_eq_i16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x34,0x7d]
-
-v_cmpx_eq_i16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x34,0x7d]
-
-v_cmpx_eq_i16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x34,0x7d]
-
-v_cmpx_eq_i16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x34,0x7d]
-
-v_cmpx_eq_i16 0, v2
-// GFX10: encoding: [0x80,0x04,0x34,0x7d]
-
-v_cmpx_eq_i16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x34,0x7d]
-
-v_cmpx_eq_i16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x34,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_i16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x34,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_i16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x34,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_eq_i16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x34,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_eq_i16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x35,0x7d]
-
-v_cmpx_eq_i16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_i16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_i16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_i16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_i16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_i16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_i16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_i16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_i16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_i16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_i16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x36,0x7d]
-
-v_cmpx_le_i16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x36,0x7d]
-
-v_cmpx_le_i16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x36,0x7d]
-
-v_cmpx_le_i16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x36,0x7d]
-
-v_cmpx_le_i16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x36,0x7d]
-
-v_cmpx_le_i16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x36,0x7d]
-
-v_cmpx_le_i16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x36,0x7d]
-
-v_cmpx_le_i16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x36,0x7d]
-
-v_cmpx_le_i16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x36,0x7d]
-
-v_cmpx_le_i16 0, v2
-// GFX10: encoding: [0x80,0x04,0x36,0x7d]
-
-v_cmpx_le_i16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x36,0x7d]
-
-v_cmpx_le_i16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x36,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_i16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x36,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_i16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x36,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_le_i16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x36,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_le_i16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x37,0x7d]
-
-v_cmpx_le_i16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_i16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_i16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_i16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_i16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_i16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_i16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_i16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_i16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_i16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_i16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x38,0x7d]
-
-v_cmpx_gt_i16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x38,0x7d]
-
-v_cmpx_gt_i16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x38,0x7d]
-
-v_cmpx_gt_i16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x38,0x7d]
-
-v_cmpx_gt_i16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x38,0x7d]
-
-v_cmpx_gt_i16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x38,0x7d]
-
-v_cmpx_gt_i16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x38,0x7d]
-
-v_cmpx_gt_i16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x38,0x7d]
-
-v_cmpx_gt_i16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x38,0x7d]
-
-v_cmpx_gt_i16 0, v2
-// GFX10: encoding: [0x80,0x04,0x38,0x7d]
-
-v_cmpx_gt_i16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x38,0x7d]
-
-v_cmpx_gt_i16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x38,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_i16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x38,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_i16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x38,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_gt_i16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x38,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_gt_i16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x39,0x7d]
-
-v_cmpx_gt_i16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_i16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_i16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_i16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_i16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_i16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_i16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_i16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_i16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_i16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_i16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x3a,0x7d]
-
-v_cmpx_ne_i16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x3a,0x7d]
-
-v_cmpx_ne_i16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x3a,0x7d]
-
-v_cmpx_ne_i16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x3a,0x7d]
-
-v_cmpx_ne_i16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x3a,0x7d]
-
-v_cmpx_ne_i16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x3a,0x7d]
-
-v_cmpx_ne_i16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x3a,0x7d]
-
-v_cmpx_ne_i16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x3a,0x7d]
-
-v_cmpx_ne_i16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x3a,0x7d]
-
-v_cmpx_ne_i16 0, v2
-// GFX10: encoding: [0x80,0x04,0x3a,0x7d]
-
-v_cmpx_ne_i16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x3a,0x7d]
-
-v_cmpx_ne_i16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x3a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_i16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x3a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_i16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x3a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ne_i16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x3a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ne_i16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x3b,0x7d]
-
-v_cmpx_ne_i16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_i16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_i16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_i16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_i16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_i16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_i16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_i16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_i16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_i16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_i16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x3c,0x7d]
-
-v_cmpx_ge_i16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x3c,0x7d]
-
-v_cmpx_ge_i16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x3c,0x7d]
-
-v_cmpx_ge_i16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x3c,0x7d]
-
-v_cmpx_ge_i16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x3c,0x7d]
-
-v_cmpx_ge_i16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x3c,0x7d]
-
-v_cmpx_ge_i16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x3c,0x7d]
-
-v_cmpx_ge_i16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x3c,0x7d]
-
-v_cmpx_ge_i16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x3c,0x7d]
-
-v_cmpx_ge_i16 0, v2
-// GFX10: encoding: [0x80,0x04,0x3c,0x7d]
-
-v_cmpx_ge_i16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x3c,0x7d]
-
-v_cmpx_ge_i16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x3c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_i16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x3c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_i16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x3c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ge_i16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x3c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ge_i16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x3d,0x7d]
-
-v_cmpx_ge_i16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_i16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_i16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_i16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_i16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_i16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_i16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_i16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_i16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_i16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_class_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x3e,0x7d]
-
-v_cmpx_class_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x3e,0x7d]
-
-v_cmpx_class_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x3e,0x7d]
-
-v_cmpx_class_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x3e,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_class_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x3e,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_class_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x3f,0x7d]
-
-v_cmpx_class_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_class_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_i64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x60,0x7d]
-
-v_cmpx_f_i64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x60,0x7d]
-
-v_cmpx_f_i64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x60,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_i64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x60,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_i64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x61,0x7d]
-
-v_cmpx_f_i64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_i64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_i64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x62,0x7d]
-
-v_cmpx_lt_i64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x62,0x7d]
-
-v_cmpx_lt_i64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x62,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_i64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x62,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_i64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x63,0x7d]
-
-v_cmpx_lt_i64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_i64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_i64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x64,0x7d]
-
-v_cmpx_eq_i64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x64,0x7d]
-
-v_cmpx_eq_i64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x64,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_i64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x64,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_i64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x65,0x7d]
-
-v_cmpx_eq_i64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_i64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_i64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x66,0x7d]
-
-v_cmpx_le_i64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x66,0x7d]
-
-v_cmpx_le_i64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x66,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_i64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x66,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_i64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x67,0x7d]
-
-v_cmpx_le_i64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_i64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_i64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x68,0x7d]
-
-v_cmpx_gt_i64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x68,0x7d]
-
-v_cmpx_gt_i64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x68,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_i64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x68,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_i64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x69,0x7d]
-
-v_cmpx_gt_i64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_i64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_i64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x6a,0x7d]
-
-v_cmpx_ne_i64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x6a,0x7d]
-
-v_cmpx_ne_i64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_i64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_i64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x6b,0x7d]
-
-v_cmpx_ne_i64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_i64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_i64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x6c,0x7d]
-
-v_cmpx_ge_i64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x6c,0x7d]
-
-v_cmpx_ge_i64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_i64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_i64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x6d,0x7d]
-
-v_cmpx_ge_i64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_i64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_i64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0x6e,0x7d]
-
-v_cmpx_t_i64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0x6e,0x7d]
-
-v_cmpx_t_i64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_i64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0x6e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_i64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0x6f,0x7d]
-
-v_cmpx_t_i64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_i64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f64 v[1:2], v2
-// GFX10: encoding: [0x01,0x05,0x70,0x7d]
-
-v_cmpx_class_f64 v[254:255], v2
-// GFX10: encoding: [0xfe,0x05,0x70,0x7d]
-
-v_cmpx_class_f64 s[2:3], v2
-// GFX10: encoding: [0x02,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 s[4:5], v2
-// GFX10: encoding: [0x04,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 s[100:101], v2
-// GFX10: encoding: [0x64,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, v2
-// GFX10: encoding: [0x6a,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 exec, v2
-// GFX10: encoding: [0x7e,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 0, v2
-// GFX10: encoding: [0x80,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0x70,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_class_f64 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0x70,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_class_f64 v[1:2], v255
-// GFX10: encoding: [0x01,0xff,0x71,0x7d]
-
-v_cmpx_class_f64_e64 v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 v[254:255], v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[2:3], v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[4:5], v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 vcc, v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], v255
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], s2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], s101
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], vcc_lo
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], vcc_hi
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], m0
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], exec_lo
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], exec_hi
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f64_e64 -v[1:2], v2
-// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_u16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x72,0x7d]
-
-v_cmpx_lt_u16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x72,0x7d]
-
-v_cmpx_lt_u16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 0, v2
-// GFX10: encoding: [0x80,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x72,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_u16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x72,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_lt_u16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x72,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lt_u16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x72,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_lt_u16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x73,0x7d]
-
-v_cmpx_lt_u16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_u16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_lt_u16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_u16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_u16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_u16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_u16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_u16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_u16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_u16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_u16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x74,0x7d]
-
-v_cmpx_eq_u16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x74,0x7d]
-
-v_cmpx_eq_u16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 0, v2
-// GFX10: encoding: [0x80,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x74,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_u16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x74,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_u16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x74,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_eq_u16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x74,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_eq_u16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x75,0x7d]
-
-v_cmpx_eq_u16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_u16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_u16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_u16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_u16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_u16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_u16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_u16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_u16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_u16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_u16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x76,0x7d]
-
-v_cmpx_le_u16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x76,0x7d]
-
-v_cmpx_le_u16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 0, v2
-// GFX10: encoding: [0x80,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x76,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_u16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x76,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_u16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x76,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_le_u16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x76,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_le_u16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x77,0x7d]
-
-v_cmpx_le_u16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_u16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_u16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_u16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_u16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_u16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_u16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_u16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_u16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_u16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_u16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x78,0x7d]
-
-v_cmpx_gt_u16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x78,0x7d]
-
-v_cmpx_gt_u16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 0, v2
-// GFX10: encoding: [0x80,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x78,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_u16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x78,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_u16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x78,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_gt_u16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x78,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_gt_u16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x79,0x7d]
-
-v_cmpx_gt_u16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_u16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_u16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_u16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_u16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_u16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_u16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_u16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_u16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_u16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_u16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x7a,0x7d]
-
-v_cmpx_ne_u16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x7a,0x7d]
-
-v_cmpx_ne_u16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 0, v2
-// GFX10: encoding: [0x80,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x7a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_u16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x7a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_u16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x7a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ne_u16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x7a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ne_u16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x7b,0x7d]
-
-v_cmpx_ne_u16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_u16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_u16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_u16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_u16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_u16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_u16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_u16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_u16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_u16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_u16 v1, v2
-// GFX10: encoding: [0x01,0x05,0x7c,0x7d]
-
-v_cmpx_ge_u16 v255, v2
-// GFX10: encoding: [0xff,0x05,0x7c,0x7d]
-
-v_cmpx_ge_u16 s1, v2
-// GFX10: encoding: [0x01,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 s101, v2
-// GFX10: encoding: [0x65,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 0, v2
-// GFX10: encoding: [0x80,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 0.5, v2
-// GFX10: encoding: [0xff,0x04,0x7c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_u16 -4.0, v2
-// GFX10: encoding: [0xff,0x04,0x7c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_u16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0x7c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ge_u16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0x7c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ge_u16 v1, v255
-// GFX10: encoding: [0x01,0xff,0x7d,0x7d]
-
-v_cmpx_ge_u16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_u16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_u16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_u16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_u16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_u16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_u16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_u16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_u16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_u16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-
-v_cmpx_f_u32 v1, v2
-// GFX10: encoding: [0x01,0x05,0xa0,0x7d]
-
-v_cmpx_f_u32 v255, v2
-// GFX10: encoding: [0xff,0x05,0xa0,0x7d]
-
-v_cmpx_f_u32 s1, v2
-// GFX10: encoding: [0x01,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 s101, v2
-// GFX10: encoding: [0x65,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 0, v2
-// GFX10: encoding: [0x80,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0xa0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_u32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0xa0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_u32 v1, v255
-// GFX10: encoding: [0x01,0xff,0xa1,0x7d]
-
-v_cmpx_f_u32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_u32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_u32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_u32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_u32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_u32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_u32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_u32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_u32 v1, v2
-// GFX10: encoding: [0x01,0x05,0xa2,0x7d]
-
-v_cmpx_lt_u32 v255, v2
-// GFX10: encoding: [0xff,0x05,0xa2,0x7d]
-
-v_cmpx_lt_u32 s1, v2
-// GFX10: encoding: [0x01,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 s101, v2
-// GFX10: encoding: [0x65,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 0, v2
-// GFX10: encoding: [0x80,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0xa2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_u32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0xa2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_u32 v1, v255
-// GFX10: encoding: [0x01,0xff,0xa3,0x7d]
-
-v_cmpx_lt_u32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_u32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_u32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_u32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_u32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_u32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_u32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_u32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_u32 v1, v2
-// GFX10: encoding: [0x01,0x05,0xa4,0x7d]
-
-v_cmpx_eq_u32 v255, v2
-// GFX10: encoding: [0xff,0x05,0xa4,0x7d]
-
-v_cmpx_eq_u32 s1, v2
-// GFX10: encoding: [0x01,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 s101, v2
-// GFX10: encoding: [0x65,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 0, v2
-// GFX10: encoding: [0x80,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0xa4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_u32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0xa4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_u32 v1, v255
-// GFX10: encoding: [0x01,0xff,0xa5,0x7d]
-
-v_cmpx_eq_u32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_u32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_u32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_u32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_u32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_u32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_u32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_u32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_u32 v1, v2
-// GFX10: encoding: [0x01,0x05,0xa6,0x7d]
-
-v_cmpx_le_u32 v255, v2
-// GFX10: encoding: [0xff,0x05,0xa6,0x7d]
-
-v_cmpx_le_u32 s1, v2
-// GFX10: encoding: [0x01,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 s101, v2
-// GFX10: encoding: [0x65,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 0, v2
-// GFX10: encoding: [0x80,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0xa6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_u32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0xa6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_u32 v1, v255
-// GFX10: encoding: [0x01,0xff,0xa7,0x7d]
-
-v_cmpx_le_u32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_u32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_u32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_u32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_u32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_u32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_u32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_u32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_u32 v1, v2
-// GFX10: encoding: [0x01,0x05,0xa8,0x7d]
-
-v_cmpx_gt_u32 v255, v2
-// GFX10: encoding: [0xff,0x05,0xa8,0x7d]
-
-v_cmpx_gt_u32 s1, v2
-// GFX10: encoding: [0x01,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 s101, v2
-// GFX10: encoding: [0x65,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 0, v2
-// GFX10: encoding: [0x80,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0xa8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_u32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0xa8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_u32 v1, v255
-// GFX10: encoding: [0x01,0xff,0xa9,0x7d]
-
-v_cmpx_gt_u32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_u32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_u32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_u32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_u32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_u32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_u32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_u32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_u32 v1, v2
-// GFX10: encoding: [0x01,0x05,0xaa,0x7d]
-
-v_cmpx_ne_u32 v255, v2
-// GFX10: encoding: [0xff,0x05,0xaa,0x7d]
-
-v_cmpx_ne_u32 s1, v2
-// GFX10: encoding: [0x01,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 s101, v2
-// GFX10: encoding: [0x65,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 0, v2
-// GFX10: encoding: [0x80,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0xaa,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_u32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0xaa,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_u32 v1, v255
-// GFX10: encoding: [0x01,0xff,0xab,0x7d]
-
-v_cmpx_ne_u32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_u32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_u32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_u32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_u32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_u32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_u32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_u32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_u32 v1, v2
-// GFX10: encoding: [0x01,0x05,0xac,0x7d]
-
-v_cmpx_ge_u32 v255, v2
-// GFX10: encoding: [0xff,0x05,0xac,0x7d]
-
-v_cmpx_ge_u32 s1, v2
-// GFX10: encoding: [0x01,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 s101, v2
-// GFX10: encoding: [0x65,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 0, v2
-// GFX10: encoding: [0x80,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0xac,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_u32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0xac,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_u32 v1, v255
-// GFX10: encoding: [0x01,0xff,0xad,0x7d]
-
-v_cmpx_ge_u32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_u32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_u32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_u32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_u32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_u32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_u32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_u32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_u32 v1, v2
-// GFX10: encoding: [0x01,0x05,0xae,0x7d]
-
-v_cmpx_t_u32 v255, v2
-// GFX10: encoding: [0xff,0x05,0xae,0x7d]
-
-v_cmpx_t_u32 s1, v2
-// GFX10: encoding: [0x01,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 s101, v2
-// GFX10: encoding: [0x65,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 0, v2
-// GFX10: encoding: [0x80,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 0xaf123456, v2
-// GFX10: encoding: [0xff,0x04,0xae,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_u32 0x3f717273, v2
-// GFX10: encoding: [0xff,0x04,0xae,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_u32 v1, v255
-// GFX10: encoding: [0x01,0xff,0xaf,0x7d]
-
-v_cmpx_t_u32_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_u32_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_u32_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_u32_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u32_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_u32_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_u32_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u32_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_u32_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u32_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u32_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_u32_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xb0,0x7d]
-
-v_cmpx_f_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xb0,0x7d]
-
-v_cmpx_f_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xb0,0x7d]
-
-v_cmpx_f_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xb0,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_f_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xb0,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_f_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xb1,0x7d]
-
-v_cmpx_f_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xb2,0x7d]
-
-v_cmpx_lt_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xb2,0x7d]
-
-v_cmpx_lt_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xb2,0x7d]
-
-v_cmpx_lt_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xb2,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lt_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xb2,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_lt_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xb3,0x7d]
-
-v_cmpx_lt_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xb4,0x7d]
-
-v_cmpx_eq_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xb4,0x7d]
-
-v_cmpx_eq_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xb4,0x7d]
-
-v_cmpx_eq_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xb4,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_eq_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xb4,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_eq_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xb5,0x7d]
-
-v_cmpx_eq_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xb6,0x7d]
-
-v_cmpx_le_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xb6,0x7d]
-
-v_cmpx_le_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xb6,0x7d]
-
-v_cmpx_le_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xb6,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_le_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xb6,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_le_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xb7,0x7d]
-
-v_cmpx_le_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xb8,0x7d]
-
-v_cmpx_gt_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xb8,0x7d]
-
-v_cmpx_gt_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xb8,0x7d]
-
-v_cmpx_gt_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xb8,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_gt_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xb8,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_gt_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xb9,0x7d]
-
-v_cmpx_gt_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xba,0x7d]
-
-v_cmpx_lg_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xba,0x7d]
-
-v_cmpx_lg_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xba,0x7d]
-
-v_cmpx_lg_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xba,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lg_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xba,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_lg_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xbb,0x7d]
-
-v_cmpx_lg_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_lg_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_lg_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lg_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lg_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lg_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_lg_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xbc,0x7d]
-
-v_cmpx_ge_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xbc,0x7d]
-
-v_cmpx_ge_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xbc,0x7d]
-
-v_cmpx_ge_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xbc,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ge_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xbc,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ge_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xbd,0x7d]
-
-v_cmpx_ge_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xbe,0x7d]
-
-v_cmpx_o_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xbe,0x7d]
-
-v_cmpx_o_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xbe,0x7d]
-
-v_cmpx_o_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xbe,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_o_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xbe,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_o_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xbf,0x7d]
-
-v_cmpx_o_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_o_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_o_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_o_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_o_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_o_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_o_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_u64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0xe0,0x7d]
-
-v_cmpx_f_u64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0xe0,0x7d]
-
-v_cmpx_f_u64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_u64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_u64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0xe1,0x7d]
-
-v_cmpx_f_u64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_u64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_u64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0xe2,0x7d]
-
-v_cmpx_lt_u64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0xe2,0x7d]
-
-v_cmpx_lt_u64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_u64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_u64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0xe3,0x7d]
-
-v_cmpx_lt_u64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_u64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_u64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0xe4,0x7d]
-
-v_cmpx_eq_u64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0xe4,0x7d]
-
-v_cmpx_eq_u64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_u64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_u64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0xe5,0x7d]
-
-v_cmpx_eq_u64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_u64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_u64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0xe6,0x7d]
-
-v_cmpx_le_u64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0xe6,0x7d]
-
-v_cmpx_le_u64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_u64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_u64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0xe7,0x7d]
-
-v_cmpx_le_u64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_u64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_u64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0xe8,0x7d]
-
-v_cmpx_gt_u64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0xe8,0x7d]
-
-v_cmpx_gt_u64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_u64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xe8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_u64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0xe9,0x7d]
-
-v_cmpx_gt_u64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_u64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_u64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0xea,0x7d]
-
-v_cmpx_ne_u64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0xea,0x7d]
-
-v_cmpx_ne_u64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xea,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_u64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xea,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_u64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0xeb,0x7d]
-
-v_cmpx_ne_u64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_u64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_u64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0xec,0x7d]
-
-v_cmpx_ge_u64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0xec,0x7d]
-
-v_cmpx_ge_u64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xec,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_u64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xec,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_u64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0xed,0x7d]
-
-v_cmpx_ge_u64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_u64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_u64 v[1:2], v[2:3]
-// GFX10: encoding: [0x01,0x05,0xee,0x7d]
-
-v_cmpx_t_u64 v[254:255], v[2:3]
-// GFX10: encoding: [0xfe,0x05,0xee,0x7d]
-
-v_cmpx_t_u64 s[2:3], v[2:3]
-// GFX10: encoding: [0x02,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 s[4:5], v[2:3]
-// GFX10: encoding: [0x04,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 s[100:101], v[2:3]
-// GFX10: encoding: [0x64,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, v[2:3]
-// GFX10: encoding: [0x6a,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 exec, v[2:3]
-// GFX10: encoding: [0x7e,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 0, v[2:3]
-// GFX10: encoding: [0x80,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 -1, v[2:3]
-// GFX10: encoding: [0xc1,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 0.5, v[2:3]
-// GFX10: encoding: [0xf0,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 -4.0, v[2:3]
-// GFX10: encoding: [0xf7,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 0xaf123456, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xee,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_u64 0x3f717273, v[2:3]
-// GFX10: encoding: [0xff,0x04,0xee,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_u64 v[1:2], v[254:255]
-// GFX10: encoding: [0x01,0xfd,0xef,0x7d]
-
-v_cmpx_t_u64_e64 v[1:2], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 v[254:255], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0xfe,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[2:3], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x02,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[4:5], v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x04,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 vcc, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 -1, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 0.5, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 -4.0, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], v[254:255]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xfd,0x03,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], s[4:5]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x09,0x00,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], s[6:7]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x0d,0x00,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], s[100:101]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xc9,0x00,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], vcc
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], exec
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], 0
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], -1
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], 0.5
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_u64_e64 v[1:2], -4.0
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xf0,0x7d]
-
-v_cmpx_u_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xf0,0x7d]
-
-v_cmpx_u_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xf0,0x7d]
-
-v_cmpx_u_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xf0,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_u_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xf0,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_u_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xf1,0x7d]
-
-v_cmpx_u_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_u_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_u_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_u_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_u_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_u_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_u_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xf2,0x7d]
-
-v_cmpx_nge_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xf2,0x7d]
-
-v_cmpx_nge_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xf2,0x7d]
-
-v_cmpx_nge_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xf2,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nge_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xf2,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_nge_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xf3,0x7d]
-
-v_cmpx_nge_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_nge_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_nge_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nge_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nge_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nge_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_nge_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xf4,0x7d]
-
-v_cmpx_nlg_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xf4,0x7d]
-
-v_cmpx_nlg_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xf4,0x7d]
-
-v_cmpx_nlg_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xf4,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nlg_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xf4,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_nlg_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xf5,0x7d]
-
-v_cmpx_nlg_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlg_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xf6,0x7d]
-
-v_cmpx_ngt_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xf6,0x7d]
-
-v_cmpx_ngt_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xf6,0x7d]
-
-v_cmpx_ngt_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xf6,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ngt_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xf6,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ngt_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xf7,0x7d]
-
-v_cmpx_ngt_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_ngt_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xf8,0x7d]
-
-v_cmpx_nle_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xf8,0x7d]
-
-v_cmpx_nle_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xf8,0x7d]
-
-v_cmpx_nle_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xf8,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nle_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xf8,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_nle_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xf9,0x7d]
-
-v_cmpx_nle_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_nle_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_nle_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nle_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nle_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nle_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_nle_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xfa,0x7d]
-
-v_cmpx_neq_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xfa,0x7d]
-
-v_cmpx_neq_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xfa,0x7d]
-
-v_cmpx_neq_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_neq_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xfa,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_neq_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xfb,0x7d]
-
-v_cmpx_neq_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_neq_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_neq_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_neq_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_neq_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_neq_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_neq_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xfc,0x7d]
-
-v_cmpx_nlt_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xfc,0x7d]
-
-v_cmpx_nlt_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xfc,0x7d]
-
-v_cmpx_nlt_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xfc,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nlt_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xfc,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_nlt_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xfd,0x7d]
-
-v_cmpx_nlt_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlt_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f16 v1, v2
-// GFX10: encoding: [0x01,0x05,0xfe,0x7d]
-
-v_cmpx_tru_f16 v255, v2
-// GFX10: encoding: [0xff,0x05,0xfe,0x7d]
-
-v_cmpx_tru_f16 s1, v2
-// GFX10: encoding: [0x01,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 s101, v2
-// GFX10: encoding: [0x65,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 vcc_lo, v2
-// GFX10: encoding: [0x6a,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 vcc_hi, v2
-// GFX10: encoding: [0x6b,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 m0, v2
-// GFX10: encoding: [0x7c,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 exec_lo, v2
-// GFX10: encoding: [0x7e,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 exec_hi, v2
-// GFX10: encoding: [0x7f,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 0, v2
-// GFX10: encoding: [0x80,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 -1, v2
-// GFX10: encoding: [0xc1,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 0.5, v2
-// GFX10: encoding: [0xf0,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 -4.0, v2
-// GFX10: encoding: [0xf7,0x04,0xfe,0x7d]
-
-v_cmpx_tru_f16 0xfe0b, v2
-// GFX10: encoding: [0xff,0x04,0xfe,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_tru_f16 0x3456, v2
-// GFX10: encoding: [0xff,0x04,0xfe,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_tru_f16 v1, v255
-// GFX10: encoding: [0x01,0xff,0xff,0x7d]
-
-v_cmpx_tru_f16_e64 v1, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 v255, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0xff,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s1, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s101, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x65,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 vcc_lo, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 vcc_hi, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x6b,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 m0, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x7c,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 exec_lo, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 exec_hi, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x7f,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 0, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 -1, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 0.5, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 -4.0, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 v1, v255
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xff,0x03,0x00]
-
-v_cmpx_tru_f16_e64 v1, s2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x00,0x00]
-
-v_cmpx_tru_f16_e64 v1, s101
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xcb,0x00,0x00]
-
-v_cmpx_tru_f16_e64 v1, vcc_lo
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f16_e64 v1, vcc_hi
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xd7,0x00,0x00]
-
-v_cmpx_tru_f16_e64 v1, m0
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xf9,0x00,0x00]
-
-v_cmpx_tru_f16_e64 v1, exec_lo
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f16_e64 v1, exec_hi
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xff,0x00,0x00]
-
-v_cmpx_tru_f16_e64 v1, 0
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f16_e64 v1, -1
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f16_e64 v1, 0.5
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f16_e64 v1, -4.0
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f16_e64 -v1, v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f16_e64 v1, -v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f16_e64 -v1, -v2
-// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_f_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_f_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_f_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_f_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_f_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_f_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x21,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x23,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x25,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_le_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_le_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_le_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_le_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_le_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_le_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x27,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x29,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x2b,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ne_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ne_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x2d,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_t_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_t_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_t_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_t_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_t_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_t_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_t_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x2f,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_t_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_t_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x33,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x35,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_le_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_le_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_le_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_le_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_le_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_le_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x37,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x39,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x3b,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ne_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ne_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x3d,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x73,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x75,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_le_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_le_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_le_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_le_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_le_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_le_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x77,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x79,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x7b,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ne_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ne_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0x7d,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_f_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_f_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_f_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_f_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_f_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_f_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xa1,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xa3,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xa5,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_le_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_le_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_le_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_le_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_le_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_le_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xa7,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xa9,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xab,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ne_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ne_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xad,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_t_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_t_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_t_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_t_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_t_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_t_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_t_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xaf,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_t_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_t_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_f_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_f_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_f_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_f_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_f_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_f_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xb1,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_f_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_f_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xb3,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_lt_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_lt_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xb5,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_eq_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_eq_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_le_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_le_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_le_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_le_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_le_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_le_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xb7,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_le_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_le_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xb9,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_gt_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_gt_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xbb,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lg_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_lg_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lg_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_lg_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xbd,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_ge_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_ge_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_o_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_o_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_o_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_o_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_o_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_o_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_o_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xbf,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_o_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_o_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_o_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_o_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_u_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_u_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_u_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_u_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_u_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_u_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_u_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xf1,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_u_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_u_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_u_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_u_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xf3,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_nge_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_nge_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_nge_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_nge_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xf5,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_nlg_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_nlg_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_nlg_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_nlg_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xf7,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ngt_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_ngt_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ngt_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_ngt_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xf9,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_nle_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_nle_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_nle_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_nle_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xfb,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_neq_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_neq_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_neq_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_neq_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xfd,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_nlt_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_nlt_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_nlt_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_nlt_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x65,0x00,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x6a,0x00,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x6b,0x00,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x7c,0x00,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x7e,0x00,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x7f,0x00,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0xfe,0xff,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_tru_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x16,0x06]
-
-v_cmpx_tru_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x26,0x06]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_tru_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x16]
-
-v_cmpx_tru_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x26]
-
-v_cmp_f_i64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x40,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x40,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x40,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x41,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x42,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x42,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x42,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x43,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x44,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x44,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x44,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x45,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x46,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x46,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x46,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x47,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x48,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x48,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x48,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x49,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x4a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x4a,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x4b,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x4c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x4c,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x4d,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0x4e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0x4e,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0x4f,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64 vcc, v[1:2], v2
-// W64: encoding: [0x01,0x05,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, v[254:255], v2
-// W64: encoding: [0xfe,0x05,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, s[2:3], v2
-// W64: encoding: [0x02,0x04,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, s[4:5], v2
-// W64: encoding: [0x04,0x04,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, s[100:101], v2
-// W64: encoding: [0x64,0x04,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, vcc, v2
-// W64: encoding: [0x6a,0x04,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, exec, v2
-// W64: encoding: [0x7e,0x04,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x50,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x50,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x50,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc, v[1:2], v255
-// W64: encoding: [0x01,0xff,0x51,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[12:13], v[1:2], v2
-// W64: encoding: [0x0c,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[100:101], v[1:2], v2
-// W64: encoding: [0x64,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 vcc, v[1:2], v2
-// W64: encoding: [0x6a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[254:255], v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], s[2:3], v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], s[4:5], v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], s[100:101], v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], vcc, v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], exec, v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], v255
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], s2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], s101
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_lo
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_hi
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], m0
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], exec_lo
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], exec_hi
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s[10:11], -v[1:2], v2
-// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0xc0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0xc1,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0xc2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0xc3,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0xc4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0xc5,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0xc6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0xc7,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0xc8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0xc9,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0xca,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0xcb,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0xcc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0xcd,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x01,0x05,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, v[254:255], v[2:3]
-// W64: encoding: [0xfe,0x05,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, s[2:3], v[2:3]
-// W64: encoding: [0x02,0x04,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, s[4:5], v[2:3]
-// W64: encoding: [0x04,0x04,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, s[100:101], v[2:3]
-// W64: encoding: [0x64,0x04,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, vcc, v[2:3]
-// W64: encoding: [0x6a,0x04,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, exec, v[2:3]
-// W64: encoding: [0x7e,0x04,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, 0, v[2:3]
-// W64: encoding: [0x80,0x04,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, -1, v[2:3]
-// W64: encoding: [0xc1,0x04,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, 0.5, v[2:3]
-// W64: encoding: [0xf0,0x04,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, -4.0, v[2:3]
-// W64: encoding: [0xf7,0x04,0xce,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, 0xaf123456, v[2:3]
-// W64: encoding: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, 0x3f717273, v[2:3]
-// W64: encoding: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc, v[1:2], v[254:255]
-// W64: encoding: [0x01,0xfd,0xcf,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[12:13], v[1:2], v[2:3]
-// W64: encoding: [0x0c,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[100:101], v[1:2], v[2:3]
-// W64: encoding: [0x64,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 vcc, v[1:2], v[2:3]
-// W64: encoding: [0x6a,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[254:255], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0xfe,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], s[2:3], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x02,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], s[4:5], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x04,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], s[100:101], v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x64,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], vcc, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], exec, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], 0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], -1, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], 0.5, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], -4.0, v[2:3]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], v[254:255]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xfd,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[4:5]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x09,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[6:7]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x0d,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[100:101]
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xc9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], vcc
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], exec
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], 0
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], -1
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], 0.5
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], -4.0
-// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x40,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x40,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x40,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x41,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_i64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_i64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x42,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x42,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x42,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x43,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_i64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_i64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x44,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x44,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x44,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x45,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_i64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_i64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x46,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x46,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x46,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x47,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_i64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_i64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x48,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x48,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x48,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x49,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_i64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_i64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x4a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x4a,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x4b,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_i64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_i64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x4c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x4c,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x4d,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_i64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_i64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0x4e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0x4e,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0x4f,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_i64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_i64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64 vcc_lo, v[1:2], v2
-// W32: encoding: [0x01,0x05,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, v[254:255], v2
-// W32: encoding: [0xfe,0x05,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, s[2:3], v2
-// W32: encoding: [0x02,0x04,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, s[4:5], v2
-// W32: encoding: [0x04,0x04,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, s[100:101], v2
-// W32: encoding: [0x64,0x04,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, vcc, v2
-// W32: encoding: [0x6a,0x04,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, exec, v2
-// W32: encoding: [0x7e,0x04,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x50,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x50,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x50,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64 vcc_lo, v[1:2], v255
-// W32: encoding: [0x01,0xff,0x51,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_class_f64_e64 s10, v[1:2], v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s12, v[1:2], v2
-// W32: encoding: [0x0c,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s100, v[1:2], v2
-// W32: encoding: [0x64,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 vcc_lo, v[1:2], v2
-// W32: encoding: [0x6a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[254:255], v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, s[2:3], v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, s[4:5], v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, s[100:101], v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, vcc, v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, exec, v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], v255
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], s2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], s101
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], vcc_lo
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], vcc_hi
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], m0
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], exec_lo
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], exec_hi
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_class_f64_e64 s10, -v[1:2], v2
-// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0xc0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0xc1,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0xc2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0xc3,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0xc4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0xc5,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0xc6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0xc7,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0xc8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0xc9,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0xca,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0xcb,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0xcc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0xcd,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x01,0x05,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, v[254:255], v[2:3]
-// W32: encoding: [0xfe,0x05,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, s[2:3], v[2:3]
-// W32: encoding: [0x02,0x04,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, s[4:5], v[2:3]
-// W32: encoding: [0x04,0x04,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, s[100:101], v[2:3]
-// W32: encoding: [0x64,0x04,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, vcc, v[2:3]
-// W32: encoding: [0x6a,0x04,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, exec, v[2:3]
-// W32: encoding: [0x7e,0x04,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, 0, v[2:3]
-// W32: encoding: [0x80,0x04,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, -1, v[2:3]
-// W32: encoding: [0xc1,0x04,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, 0.5, v[2:3]
-// W32: encoding: [0xf0,0x04,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, -4.0, v[2:3]
-// W32: encoding: [0xf7,0x04,0xce,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, 0xaf123456, v[2:3]
-// W32: encoding: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, 0x3f717273, v[2:3]
-// W32: encoding: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64 vcc_lo, v[1:2], v[254:255]
-// W32: encoding: [0x01,0xfd,0xcf,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u64_e64 s10, v[1:2], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s12, v[1:2], v[2:3]
-// W32: encoding: [0x0c,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s100, v[1:2], v[2:3]
-// W32: encoding: [0x64,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 vcc_lo, v[1:2], v[2:3]
-// W32: encoding: [0x6a,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[254:255], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0xfe,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, s[2:3], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x02,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, s[4:5], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x04,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, s[100:101], v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x64,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, vcc, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, exec, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, 0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, -1, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, 0.5, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, -4.0, v[2:3]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], v[254:255]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xfd,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], s[4:5]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x09,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], s[6:7]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x0d,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], s[100:101]
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xc9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], vcc
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], exec
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], 0
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], -1
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], 0.5
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u64_e64 s10, v[1:2], -4.0
-// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmpx_f_u64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 exec, v[2:3]
-// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_u16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x52,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x52,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x52,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x52,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x52,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x53,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x54,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x54,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x54,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x54,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x54,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x55,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x56,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x56,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x56,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x56,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x56,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x57,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x58,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x58,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x58,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x58,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x58,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x59,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x5a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x5a,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x5a,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x5a,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x5a,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x5b,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x5c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, 0.5, v2
-// W64: encoding: [0xff,0x04,0x5c,0x7d,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, -4.0, v2
-// W64: encoding: [0xff,0x04,0x5c,0x7d,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x5c,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x5c,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x5d,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x80,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x81,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x82,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x83,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x84,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x85,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x86,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x87,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x88,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x89,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x8a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x8b,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x8c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x8d,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x8e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, 0xaf123456, v2
-// W64: encoding: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, 0x3f717273, v2
-// W64: encoding: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x8f,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x90,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x90,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x90,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x91,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x92,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x92,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x92,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x93,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x94,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x94,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x94,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x95,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x96,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x96,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x96,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x97,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x98,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x98,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x98,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x99,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x9a,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x9a,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x9a,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x9b,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x9c,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x9c,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x9c,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x9d,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0x9e,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0x9e,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0x9e,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0x9f,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0xd0,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0xd0,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0xd0,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0xd1,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0xd2,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0xd2,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0xd2,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0xd3,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0xd4,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0xd4,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0xd4,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0xd5,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0xd6,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0xd6,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0xd6,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0xd7,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0xd8,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0xd8,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0xd8,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0xd9,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0xda,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0xda,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0xda,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0xdb,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0xdc,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0xdc,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0xdc,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0xdd,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16 vcc, v1, v2
-// W64: encoding: [0x01,0x05,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, v255, v2
-// W64: encoding: [0xff,0x05,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, s1, v2
-// W64: encoding: [0x01,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, s101, v2
-// W64: encoding: [0x65,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, vcc_lo, v2
-// W64: encoding: [0x6a,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, vcc_hi, v2
-// W64: encoding: [0x6b,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, m0, v2
-// W64: encoding: [0x7c,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, exec_lo, v2
-// W64: encoding: [0x7e,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, exec_hi, v2
-// W64: encoding: [0x7f,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, 0, v2
-// W64: encoding: [0x80,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, -1, v2
-// W64: encoding: [0xc1,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, 0.5, v2
-// W64: encoding: [0xf0,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, -4.0, v2
-// W64: encoding: [0xf7,0x04,0xde,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, 0xfe0b, v2
-// W64: encoding: [0xff,0x04,0xde,0x7d,0x0b,0xfe,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, 0x3456, v2
-// W64: encoding: [0xff,0x04,0xde,0x7d,0x56,0x34,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc, v1, v255
-// W64: encoding: [0x01,0xff,0xdf,0x7d]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16_e64 s[10:11], v1, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[12:13], v1, v2
-// W64: encoding: [0x0c,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[100:101], v1, v2
-// W64: encoding: [0x64,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 vcc, v1, v2
-// W64: encoding: [0x6a,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v255, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0xff,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], s1, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], s101, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x65,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], vcc_lo, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x6a,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], vcc_hi, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x6b,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], m0, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x7c,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], exec_lo, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x7e,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], exec_hi, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x7f,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], 0, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x80,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], -1, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0xc1,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], 0.5, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0xf0,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], -4.0, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0xf7,0x04,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, v255
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xff,0x03,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, s2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, s101
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xcb,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, vcc_lo
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xd5,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, vcc_hi
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xd7,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, m0
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xf9,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, exec_lo
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xfd,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, exec_hi
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xff,0x00,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, 0
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x01,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, -1
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x83,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, 0.5
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xe1,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, -4.0
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xef,0x01,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], -v1, v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x20]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, -v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x40]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], -v1, -v2
-// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x60]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s[10:11], v1, v2 clamp
-// W64: encoding: [0x0a,0x80,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x52,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x52,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x52,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x52,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x52,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x53,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x54,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x54,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x54,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x54,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x54,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x55,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x56,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x56,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x56,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x56,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x56,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x57,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x58,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x58,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x58,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x58,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x58,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x59,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x5a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x5a,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x5a,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x5a,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x5a,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x5b,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x5c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, 0.5, v2
-// W32: encoding: [0xff,0x04,0x5c,0x7d,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, -4.0, v2
-// W32: encoding: [0xff,0x04,0x5c,0x7d,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x5c,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x5c,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x5d,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x80,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x81,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x82,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x83,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x84,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x85,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x86,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x87,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x88,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x89,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x8a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x8b,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x8c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x8d,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x8e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, 0xaf123456, v2
-// W32: encoding: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, 0x3f717273, v2
-// W32: encoding: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x8f,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x90,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x90,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x90,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x91,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xc8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x92,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x92,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x92,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x93,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xc9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x94,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x94,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x94,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x95,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xca,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x96,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x96,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x96,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x97,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xcb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x98,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x98,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x98,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x99,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xcc,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x9a,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x9a,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x9a,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x9b,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xcd,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x9c,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x9c,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x9c,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x9d,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xce,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0x9e,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0x9e,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0x9e,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0x9f,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xcf,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0xd0,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0xd0,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0xd0,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0xd1,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xe8,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0xd2,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0xd2,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0xd2,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0xd3,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xe9,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0xd4,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0xd4,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0xd4,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0xd5,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xea,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0xd6,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0xd6,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0xd6,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0xd7,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xeb,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0xd8,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0xd8,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0xd8,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0xd9,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xec,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0xda,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0xda,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0xda,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0xdb,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xed,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0xdc,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0xdc,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0xdc,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0xdd,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xee,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16 vcc_lo, v1, v2
-// W32: encoding: [0x01,0x05,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, v255, v2
-// W32: encoding: [0xff,0x05,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, s1, v2
-// W32: encoding: [0x01,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, s101, v2
-// W32: encoding: [0x65,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, vcc_lo, v2
-// W32: encoding: [0x6a,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, vcc_hi, v2
-// W32: encoding: [0x6b,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, m0, v2
-// W32: encoding: [0x7c,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, exec_lo, v2
-// W32: encoding: [0x7e,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, exec_hi, v2
-// W32: encoding: [0x7f,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, 0, v2
-// W32: encoding: [0x80,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, -1, v2
-// W32: encoding: [0xc1,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, 0.5, v2
-// W32: encoding: [0xf0,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, -4.0, v2
-// W32: encoding: [0xf7,0x04,0xde,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, 0xfe0b, v2
-// W32: encoding: [0xff,0x04,0xde,0x7d,0x0b,0xfe,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, 0x3456, v2
-// W32: encoding: [0xff,0x04,0xde,0x7d,0x56,0x34,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16 vcc_lo, v1, v255
-// W32: encoding: [0x01,0xff,0xdf,0x7d]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16_e64 s10, v1, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s12, v1, v2
-// W32: encoding: [0x0c,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s100, v1, v2
-// W32: encoding: [0x64,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 vcc_lo, v1, v2
-// W32: encoding: [0x6a,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v255, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0xff,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, s1, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, s101, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x65,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, vcc_lo, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x6a,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, vcc_hi, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x6b,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, m0, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x7c,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, exec_lo, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x7e,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, exec_hi, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x7f,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, 0, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x80,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, -1, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0xc1,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, 0.5, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0xf0,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, -4.0, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0xf7,0x04,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, v255
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xff,0x03,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, s2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, s101
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xcb,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, vcc_lo
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xd5,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, vcc_hi
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xd7,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, m0
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xf9,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, exec_lo
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xfd,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, exec_hi
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xff,0x00,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, 0
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x01,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, -1
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x83,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, 0.5
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xe1,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, -4.0
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xef,0x01,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, -v1, v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x20]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, -v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x40]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, -v1, -v2
-// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x60]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_e64 s10, v1, v2 clamp
-// W32: encoding: [0x0a,0x80,0xef,0xd4,0x01,0x05,0x02,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x53,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x55,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x57,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x59,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x5b,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x5d,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x81,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x83,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x85,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x87,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x89,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ne_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x8b,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x8d,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_t_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x8f,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x0e,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x0e]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_f_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x91,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x93,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_eq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x95,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_le_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x97,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_gt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x99,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_lg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x9b,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x9d,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_o_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0x9f,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_u_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0xd1,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0xd3,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0xd5,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_ngt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0xd7,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nle_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0xd9,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_neq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0xdb,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_nlt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0xdd,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x88,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0xe4,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x00,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
-
-v_cmp_tru_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0xff,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x65,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x6a,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x6b,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x7c,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x7e,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x7f,0x86,0x86,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0xfe,0xdf,0x7d,0x01,0x86,0x06,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x00,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x01,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x02,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x03,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x04,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x05,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x16,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x26,0x06]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x00]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x01]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x02]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x03]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x04]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x05]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x16]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x26]
-// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x53,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x55,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x57,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x59,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x5b,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x5d,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x81,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x83,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x85,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x87,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x89,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x8b,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ne_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x8d,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x8f,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x0e,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_t_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x0e]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x91,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_f_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x93,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lt_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x95,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_eq_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x97,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_le_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x99,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_gt_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x9b,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_lg_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x9d,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ge_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0x9f,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_o_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0xd1,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_u_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0xd3,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nge_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0xd5,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlg_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0xd7,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_ngt_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0xd9,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nle_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0xdb,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_neq_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0xdd,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_nlt_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x88,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0xe4,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x00,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0xff,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x65,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x6a,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x6b,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x7c,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x7e,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x7f,0x86,0x86,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0xfe,0xdf,0x7d,0x01,0x86,0x06,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x00,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x01,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x02,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x03,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x04,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x05,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x16,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x26,0x06]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x00]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x01]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x02]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x03]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x04]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x05]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x16]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_cmp_tru_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x26]
-// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
-
-v_interp_p1_f32_e64 v5, v2, attr0.x
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v255, v2, attr0.x
-// GFX10: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr1.x
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x00,0xd6,0x01,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr31.x
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x00,0xd6,0x1f,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr32.x
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x00,0xd6,0x20,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v255, attr0.x
-// GFX10: v_interp_p1_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0xfe,0x03,0x00]
-
-v_interp_p1_f32_e64 v5, -v2, attr0.x
-// GFX10: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x40]
-
-v_interp_p1_f32_e64 v5, |v2|, attr0.x
-// GFX10: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x00,0xd6,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.y
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x00,0xd6,0x40,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.z
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x00,0xd6,0x80,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.w
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x00,0xd6,0xc0,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x clamp
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x00,0xd6,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x08]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x mul:4
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x10]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x div:2
-// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x18]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v255, v2, attr0.x
-// GFX10: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr1.x
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x01,0xd6,0x01,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr31.x
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x01,0xd6,0x1f,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr32.x
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x01,0xd6,0x20,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v255, attr0.x
-// GFX10: v_interp_p2_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0xfe,0x03,0x00]
-
-v_interp_p2_f32_e64 v5, -v2, attr0.x
-// GFX10: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x40]
-
-v_interp_p2_f32_e64 v5, |v2|, attr0.x
-// GFX10: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x01,0xd6,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.y
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x01,0xd6,0x40,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.z
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x01,0xd6,0x80,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.w
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x01,0xd6,0xc0,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x clamp
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x01,0xd6,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x mul:2
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x08]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x mul:4
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x10]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x div:2
-// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x18]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v255, p10, attr0.x
-// GFX10: v_interp_mov_f32_e64 v255, p10, attr0.x ; encoding: [0xff,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr1.x
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr1.x ; encoding: [0x05,0x00,0x02,0xd6,0x01,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr31.x
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr31.x ; encoding: [0x05,0x00,0x02,0xd6,0x1f,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr32.x
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x02,0xd6,0x20,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p20, attr0.x
-// GFX10: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x02,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p0, attr0.x
-// GFX10: v_interp_mov_f32_e64 v5, p0, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x04,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.y
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.y ; encoding: [0x05,0x00,0x02,0xd6,0x40,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.z
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.z ; encoding: [0x05,0x00,0x02,0xd6,0x80,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.w
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x02,0xd6,0xc0,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x clamp
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x02,0xd6,0x00,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x08]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x10]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x div:2
-// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x18]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_ds.s b/llvm/test/MC/AMDGPU/gfx10_asm_ds.s
new file mode 100644
index 0000000000000..fd56d5c527ebc
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_ds.s
@@ -0,0 +1,6987 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+
+//===----------------------------------------------------------------------===//
+// ENC_DS.
+//===----------------------------------------------------------------------===//
+
+ds_add_u32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x00,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_u32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x00,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_u32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x00,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_u32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x00,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_u32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x00,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_u32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x00,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_u32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x00,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_u32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x00,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_u32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x00,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_u32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x00,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_u32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x00,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_u32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x00,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_u32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_u32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_u32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_u32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_u32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x02,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_u32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x02,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_u32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x02,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_u32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x02,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_u32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x02,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_u32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x02,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_u32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x02,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_u32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x02,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_u32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x02,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_u32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x02,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_u32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x02,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_u32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x02,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_u32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x02,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_u32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x02,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_u32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x02,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_u32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x02,0xd8,0xff,0x01,0x00,0x00]
+
+ds_sub_u32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x04,0xd8,0x00,0x01,0x00,0x00]
+
+ds_sub_u32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x04,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_sub_u32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x04,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_sub_u32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x04,0xd8,0xff,0x01,0x00,0x00]
+
+ds_sub_u32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x04,0xd8,0x00,0x01,0x00,0x00]
+
+ds_sub_u32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x04,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_sub_u32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x04,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_sub_u32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x04,0xd8,0xff,0x01,0x00,0x00]
+
+ds_sub_u32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x04,0xd8,0x00,0x01,0x00,0x00]
+
+ds_sub_u32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x04,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_sub_u32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x04,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_sub_u32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x04,0xd8,0xff,0x01,0x00,0x00]
+
+ds_sub_u32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xd8,0x00,0x01,0x00,0x00]
+
+ds_sub_u32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_sub_u32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_sub_u32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xd8,0xff,0x01,0x00,0x00]
+
+ds_sub_u32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x06,0xd8,0x00,0x01,0x00,0x00]
+
+ds_sub_u32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x06,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_sub_u32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x06,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_sub_u32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x06,0xd8,0xff,0x01,0x00,0x00]
+
+ds_sub_u32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x06,0xd8,0x00,0x01,0x00,0x00]
+
+ds_sub_u32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x06,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_sub_u32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x06,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_sub_u32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x06,0xd8,0xff,0x01,0x00,0x00]
+
+ds_sub_u32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x06,0xd8,0x00,0x01,0x00,0x00]
+
+ds_sub_u32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x06,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_sub_u32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x06,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_sub_u32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x06,0xd8,0xff,0x01,0x00,0x00]
+
+ds_sub_u32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x06,0xd8,0x00,0x01,0x00,0x00]
+
+ds_sub_u32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x06,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_sub_u32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x06,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_sub_u32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x06,0xd8,0xff,0x01,0x00,0x00]
+
+ds_rsub_u32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x08,0xd8,0x00,0x01,0x00,0x00]
+
+ds_rsub_u32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x08,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_rsub_u32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x08,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_rsub_u32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x08,0xd8,0xff,0x01,0x00,0x00]
+
+ds_rsub_u32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x08,0xd8,0x00,0x01,0x00,0x00]
+
+ds_rsub_u32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x08,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_rsub_u32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x08,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_rsub_u32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x08,0xd8,0xff,0x01,0x00,0x00]
+
+ds_rsub_u32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x08,0xd8,0x00,0x01,0x00,0x00]
+
+ds_rsub_u32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x08,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_rsub_u32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x08,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_rsub_u32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x08,0xd8,0xff,0x01,0x00,0x00]
+
+ds_rsub_u32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xd8,0x00,0x01,0x00,0x00]
+
+ds_rsub_u32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_rsub_u32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_rsub_u32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xd8,0xff,0x01,0x00,0x00]
+
+ds_rsub_u32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_rsub_u32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_rsub_u32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_rsub_u32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_rsub_u32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_rsub_u32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_rsub_u32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_rsub_u32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x0a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_rsub_u32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x0a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_rsub_u32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x0a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_rsub_u32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x0a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_rsub_u32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x0a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_rsub_u32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_rsub_u32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_rsub_u32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_rsub_u32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_inc_u32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_inc_u32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_inc_u32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_inc_u32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_inc_u32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_inc_u32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_inc_u32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_inc_u32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x0c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_inc_u32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x0c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_inc_u32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x0c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_inc_u32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x0c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_inc_u32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x0c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_inc_u32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_inc_u32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_inc_u32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_inc_u32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_inc_u32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_inc_u32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_inc_u32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_inc_u32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_inc_u32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_inc_u32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_inc_u32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_inc_u32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x0e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_inc_u32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x0e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_inc_u32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x0e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_inc_u32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x0e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_inc_u32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x0e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_inc_u32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_inc_u32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_inc_u32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_inc_u32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_dec_u32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x10,0xd8,0x00,0x01,0x00,0x00]
+
+ds_dec_u32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x10,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_dec_u32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x10,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_dec_u32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x10,0xd8,0xff,0x01,0x00,0x00]
+
+ds_dec_u32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x10,0xd8,0x00,0x01,0x00,0x00]
+
+ds_dec_u32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x10,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_dec_u32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x10,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_dec_u32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x10,0xd8,0xff,0x01,0x00,0x00]
+
+ds_dec_u32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x10,0xd8,0x00,0x01,0x00,0x00]
+
+ds_dec_u32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x10,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_dec_u32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x10,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_dec_u32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x10,0xd8,0xff,0x01,0x00,0x00]
+
+ds_dec_u32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xd8,0x00,0x01,0x00,0x00]
+
+ds_dec_u32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_dec_u32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_dec_u32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xd8,0xff,0x01,0x00,0x00]
+
+ds_dec_u32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x12,0xd8,0x00,0x01,0x00,0x00]
+
+ds_dec_u32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x12,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_dec_u32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x12,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_dec_u32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x12,0xd8,0xff,0x01,0x00,0x00]
+
+ds_dec_u32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x12,0xd8,0x00,0x01,0x00,0x00]
+
+ds_dec_u32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x12,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_dec_u32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x12,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_dec_u32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x12,0xd8,0xff,0x01,0x00,0x00]
+
+ds_dec_u32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x12,0xd8,0x00,0x01,0x00,0x00]
+
+ds_dec_u32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x12,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_dec_u32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x12,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_dec_u32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x12,0xd8,0xff,0x01,0x00,0x00]
+
+ds_dec_u32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x12,0xd8,0x00,0x01,0x00,0x00]
+
+ds_dec_u32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x12,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_dec_u32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x12,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_dec_u32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x12,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_i32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x14,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_i32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x14,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_i32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x14,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_i32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x14,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_i32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x14,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_i32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x14,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_i32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x14,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_i32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x14,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_i32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x14,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_i32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x14,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_i32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x14,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_i32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x14,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_i32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_i32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_i32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_i32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_i32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x16,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_i32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x16,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_i32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x16,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_i32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x16,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_i32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x16,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_i32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x16,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_i32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x16,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_i32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x16,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_i32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x16,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_i32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x16,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_i32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x16,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_i32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x16,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_i32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x16,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_i32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x16,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_i32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x16,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_i32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x16,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_i32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x18,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_i32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x18,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_i32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x18,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_i32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x18,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_i32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x18,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_i32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x18,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_i32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x18,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_i32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x18,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_i32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x18,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_i32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x18,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_i32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x18,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_i32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x18,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_i32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_i32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_i32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_i32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_i32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_i32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_i32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_i32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_i32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_i32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_i32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_i32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x1a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_i32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x1a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_i32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x1a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_i32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x1a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_i32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x1a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_i32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_i32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_i32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_i32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_u32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_u32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_u32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_u32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_u32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_u32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_u32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_u32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x1c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_u32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x1c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_u32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x1c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_u32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x1c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_u32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x1c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_u32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_u32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_u32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_u32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_u32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_u32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_u32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_u32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_u32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_u32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_u32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_u32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x1e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_u32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x1e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_u32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x1e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_u32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x1e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_u32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x1e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_u32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_u32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_u32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_u32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_u32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x20,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_u32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x20,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_u32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x20,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_u32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x20,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_u32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x20,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_u32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x20,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_u32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x20,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_u32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x20,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_u32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x20,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_u32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x20,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_u32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x20,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_u32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x20,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_u32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_u32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_u32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_u32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_u32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x22,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_u32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x22,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_u32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x22,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_u32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x22,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_u32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x22,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_u32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x22,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_u32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x22,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_u32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x22,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_u32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x22,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_u32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x22,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_u32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x22,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_u32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x22,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_u32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x22,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_u32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x22,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_u32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x22,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_u32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x22,0xd8,0xff,0x01,0x00,0x00]
+
+ds_and_b32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x24,0xd8,0x00,0x01,0x00,0x00]
+
+ds_and_b32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x24,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_and_b32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x24,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_and_b32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x24,0xd8,0xff,0x01,0x00,0x00]
+
+ds_and_b32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x24,0xd8,0x00,0x01,0x00,0x00]
+
+ds_and_b32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x24,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_and_b32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x24,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_and_b32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x24,0xd8,0xff,0x01,0x00,0x00]
+
+ds_and_b32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x24,0xd8,0x00,0x01,0x00,0x00]
+
+ds_and_b32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x24,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_and_b32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x24,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_and_b32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x24,0xd8,0xff,0x01,0x00,0x00]
+
+ds_and_b32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xd8,0x00,0x01,0x00,0x00]
+
+ds_and_b32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_and_b32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_and_b32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xd8,0xff,0x01,0x00,0x00]
+
+ds_and_b32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x26,0xd8,0x00,0x01,0x00,0x00]
+
+ds_and_b32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x26,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_and_b32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x26,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_and_b32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x26,0xd8,0xff,0x01,0x00,0x00]
+
+ds_and_b32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x26,0xd8,0x00,0x01,0x00,0x00]
+
+ds_and_b32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x26,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_and_b32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x26,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_and_b32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x26,0xd8,0xff,0x01,0x00,0x00]
+
+ds_and_b32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x26,0xd8,0x00,0x01,0x00,0x00]
+
+ds_and_b32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x26,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_and_b32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x26,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_and_b32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x26,0xd8,0xff,0x01,0x00,0x00]
+
+ds_and_b32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x26,0xd8,0x00,0x01,0x00,0x00]
+
+ds_and_b32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x26,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_and_b32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x26,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_and_b32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x26,0xd8,0xff,0x01,0x00,0x00]
+
+ds_or_b32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x28,0xd8,0x00,0x01,0x00,0x00]
+
+ds_or_b32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x28,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_or_b32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x28,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_or_b32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x28,0xd8,0xff,0x01,0x00,0x00]
+
+ds_or_b32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x28,0xd8,0x00,0x01,0x00,0x00]
+
+ds_or_b32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x28,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_or_b32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x28,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_or_b32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x28,0xd8,0xff,0x01,0x00,0x00]
+
+ds_or_b32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x28,0xd8,0x00,0x01,0x00,0x00]
+
+ds_or_b32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x28,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_or_b32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x28,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_or_b32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x28,0xd8,0xff,0x01,0x00,0x00]
+
+ds_or_b32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xd8,0x00,0x01,0x00,0x00]
+
+ds_or_b32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_or_b32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_or_b32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xd8,0xff,0x01,0x00,0x00]
+
+ds_or_b32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_or_b32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_or_b32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_or_b32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_or_b32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_or_b32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_or_b32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_or_b32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x2a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_or_b32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x2a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_or_b32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x2a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_or_b32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x2a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_or_b32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x2a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_or_b32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_or_b32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_or_b32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_or_b32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_xor_b32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_xor_b32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_xor_b32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_xor_b32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_xor_b32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_xor_b32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_xor_b32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_xor_b32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x2c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_xor_b32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x2c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_xor_b32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x2c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_xor_b32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x2c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_xor_b32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x2c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_xor_b32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_xor_b32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_xor_b32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_xor_b32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_xor_b32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_xor_b32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_xor_b32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_xor_b32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_xor_b32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_xor_b32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_xor_b32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_xor_b32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x2e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_xor_b32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x2e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_xor_b32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x2e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_xor_b32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x2e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_xor_b32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x2e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_xor_b32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_xor_b32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_xor_b32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_xor_b32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_mskor_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0x00,0x01,0x02,0x00]
+
+ds_mskor_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_mskor_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_mskor_b32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0x00,0x01,0x02,0x00]
+
+ds_mskor_b32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_mskor_b32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x30,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_mskor_b32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x30,0xd8,0x00,0x01,0x02,0x00]
+
+ds_mskor_b32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x30,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x30,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x30,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_mskor_b32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x30,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_mskor_b32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x30,0xd8,0x00,0x01,0x02,0x00]
+
+ds_mskor_b32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x30,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x30,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x30,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_mskor_b32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x30,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_mskor_b32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0x00,0x01,0x02,0x00]
+
+ds_mskor_b32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_mskor_b32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_mskor_b32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0x00,0x01,0x02,0x00]
+
+ds_mskor_b32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_mskor_b32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x32,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_mskor_b32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x32,0xd8,0x00,0x01,0x02,0x00]
+
+ds_mskor_b32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x32,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x32,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x32,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_mskor_b32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x32,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_mskor_b32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x32,0xd8,0x00,0x01,0x02,0x00]
+
+ds_mskor_b32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x32,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x32,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_mskor_b32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x32,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_mskor_b32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x32,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write_b32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x34,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x34,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x34,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x34,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x34,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x34,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x34,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x34,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x34,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x34,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x34,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x34,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x36,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x36,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x36,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x36,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x36,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x36,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x36,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x36,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x36,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x36,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x36,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x36,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x36,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x36,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x36,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x36,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write2_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x38,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x38,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x38,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x38,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x38,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x38,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x38,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x38,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x38,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x38,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x38,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x38,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x38,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x38,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x38,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x38,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x38,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x38,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x38,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x38,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x38,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x38,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x38,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x38,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x3a,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3a,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3a,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3a,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3a,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3a,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3a,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2_b32 v0, v1, v2 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2_b32 v255, v254, v253 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2_b32 v0, v254, v253 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2_b32 v255, v1, v253 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2_b32 v255, v254, v2 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3a,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x3c,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:0 offset1:123
+// GFX10: encoding: [0x00,0x7b,0x3c,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:123 offset1:0
+// GFX10: encoding: [0x7b,0x00,0x3c,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:64 offset1:123
+// GFX10: encoding: [0x40,0x7b,0x3c,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:123 offset1:64
+// GFX10: encoding: [0x7b,0x40,0x3c,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:64 offset1:255
+// GFX10: encoding: [0x40,0xff,0x3c,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:255 offset1:64
+// GFX10: encoding: [0xff,0x40,0x3c,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:255 offset1:255
+// GFX10: encoding: [0xff,0xff,0x3c,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x3e,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:0 offset1:123 gds
+// GFX10: encoding: [0x00,0x7b,0x3e,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:123 offset1:0 gds
+// GFX10: encoding: [0x7b,0x00,0x3e,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:64 offset1:123 gds
+// GFX10: encoding: [0x40,0x7b,0x3e,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:123 offset1:64 gds
+// GFX10: encoding: [0x7b,0x40,0x3e,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:64 offset1:255 gds
+// GFX10: encoding: [0x40,0xff,0x3e,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:255 offset1:64 gds
+// GFX10: encoding: [0xff,0x40,0x3e,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_write2st64_b32 v0, v1, v2 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0x00,0x01,0x02,0x00]
+
+ds_write2st64_b32 v255, v254, v253 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v0, v254, v253 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_write2st64_b32 v255, v1, v253 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_write2st64_b32 v255, v254, v2 offset0:255 offset1:255 gds
+// GFX10: encoding: [0xff,0xff,0x3e,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_b32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_b32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_b32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x40,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_b32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x40,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_b32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x40,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x40,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x40,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_b32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x40,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_b32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x40,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_b32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x40,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x40,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x40,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_b32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x40,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_b32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_b32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_b32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_b32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_b32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_b32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x42,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_b32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x42,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_b32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x42,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x42,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x42,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_b32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x42,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_b32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x42,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_b32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x42,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x42,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_b32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x42,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_b32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x42,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_f32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_f32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_f32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_f32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_f32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_f32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x44,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_f32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x44,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_f32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x44,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x44,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x44,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_f32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x44,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_f32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x44,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_f32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x44,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x44,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x44,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_f32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x44,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_f32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_f32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_f32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_f32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_f32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_f32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x46,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_f32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x46,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_f32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x46,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x46,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x46,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_f32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x46,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_cmpst_f32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x46,0xd8,0x00,0x01,0x02,0x00]
+
+ds_cmpst_f32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x46,0xd8,0xff,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x46,0xd8,0x00,0xfe,0xfd,0x00]
+
+ds_cmpst_f32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x46,0xd8,0xff,0x01,0xfd,0x00]
+
+ds_cmpst_f32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x46,0xd8,0xff,0xfe,0x02,0x00]
+
+ds_min_f32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x48,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_f32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x48,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_f32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x48,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_f32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x48,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_f32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x48,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_f32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x48,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_f32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x48,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_f32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x48,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_f32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x48,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_f32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x48,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_f32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x48,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_f32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x48,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_f32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_f32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_f32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_f32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_f32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_f32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_f32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_f32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_f32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_f32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_f32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_f32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x4a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_f32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x4a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_f32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x4a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_f32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x4a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_f32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x4a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_min_f32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_min_f32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_min_f32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_min_f32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_f32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_f32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_f32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_f32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_f32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_f32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_f32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_f32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x4c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_f32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x4c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_f32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x4c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_f32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x4c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_f32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x4c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_f32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_f32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_f32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_f32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_f32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_f32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_f32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_f32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_f32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_f32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_f32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_f32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x4e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_f32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x4e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_f32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x4e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_f32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x4e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_f32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x4e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_max_f32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_max_f32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_max_f32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_max_f32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_nop
+// GFX10: encoding: [0x00,0x00,0x50,0xd8,0x00,0x00,0x00,0x00]
+
+ds_add_f32 v0, v1
+// GFX10: encoding: [0x00,0x00,0x54,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_f32 v255, v254
+// GFX10: encoding: [0x00,0x00,0x54,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_f32 v0, v254
+// GFX10: encoding: [0x00,0x00,0x54,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_f32 v255, v1
+// GFX10: encoding: [0x00,0x00,0x54,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_f32 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_f32 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_f32 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_f32 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_f32 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x54,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_f32 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x54,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_f32 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x54,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_f32 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x54,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_f32 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_f32 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_f32 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_f32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_f32 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_f32 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_f32 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_f32 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_f32 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_f32 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_f32 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_f32 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_f32 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x56,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_f32 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x56,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_f32 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x56,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_f32 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x56,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_f32 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xd8,0x00,0x01,0x00,0x00]
+
+ds_add_f32 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_add_f32 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_add_f32 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xd8,0xff,0x01,0x00,0x00]
+
+ds_gws_sema_release_all gds
+// GFX10: encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x62,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_init v0 gds
+// GFX10: encoding: [0x00,0x00,0x66,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_init v255 gds
+// GFX10: encoding: [0x00,0x00,0x66,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_init v0 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x66,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_init v255 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x66,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_init v0 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x66,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_init v255 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x66,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_init v0 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x66,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_init v255 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x66,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_sema_v gds
+// GFX10: encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x6a,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x6a,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_br v0 gds
+// GFX10: encoding: [0x00,0x00,0x6e,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_br v255 gds
+// GFX10: encoding: [0x00,0x00,0x6e,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_sema_br v0 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x6e,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_br v255 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x6e,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_sema_br v0 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x6e,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_br v255 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x6e,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_sema_br v0 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x6e,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_br v255 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_sema_p gds
+// GFX10: encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x72,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_barrier v0 gds
+// GFX10: encoding: [0x00,0x00,0x76,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_barrier v255 gds
+// GFX10: encoding: [0x00,0x00,0x76,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_barrier v0 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x76,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_barrier v255 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x76,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_barrier v0 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x76,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_barrier v255 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x76,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_barrier v0 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x76,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_barrier v255 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x76,0xd8,0xff,0x00,0x00,0x00]
+
+ds_write_b8 v0, v1
+// GFX10: encoding: [0x00,0x00,0x78,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b8 v255, v254
+// GFX10: encoding: [0x00,0x00,0x78,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b8 v0, v254
+// GFX10: encoding: [0x00,0x00,0x78,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b8 v255, v1
+// GFX10: encoding: [0x00,0x00,0x78,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b8 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x78,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b8 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x78,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b8 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x78,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b8 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x78,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b8 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x78,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b8 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x78,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b8 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x78,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b8 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x78,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b8 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x78,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b8 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x78,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b8 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x78,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b8 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x78,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b8 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b8 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b8 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b8 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b8 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b8 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b8 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b8 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x7a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b8 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x7a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b8 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x7a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b8 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x7a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b8 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x7a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b8 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b8 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7a,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b8 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7a,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b8 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7a,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b16 v0, v1
+// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b16 v255, v254
+// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b16 v0, v254
+// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b16 v255, v1
+// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b16 v0, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b16 v255, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b16 v0, v254 offset:0
+// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b16 v255, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x7c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b16 v0, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x7c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b16 v255, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x7c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b16 v0, v254 offset:4660
+// GFX10: encoding: [0x34,0x12,0x7c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b16 v255, v1 offset:4660
+// GFX10: encoding: [0x34,0x12,0x7c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b16 v0, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x7c,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b16 v255, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x7c,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b16 v0, v254 offset:65535
+// GFX10: encoding: [0xff,0xff,0x7c,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b16 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x7c,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b16 v0, v1 gds
+// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b16 v255, v254 gds
+// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b16 v0, v254 gds
+// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b16 v255, v1 gds
+// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b16 v0, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b16 v255, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b16 v0, v254 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b16 v255, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x7e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b16 v0, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x7e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b16 v255, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x7e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b16 v0, v254 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x7e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b16 v255, v1 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x7e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_write_b16 v0, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7e,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b16 v255, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7e,0xd8,0xff,0xfe,0x00,0x00]
+
+ds_write_b16 v0, v254 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7e,0xd8,0x00,0xfe,0x00,0x00]
+
+ds_write_b16 v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7e,0xd8,0xff,0x01,0x00,0x00]
+
+ds_add_rtn_u32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_u32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_u32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x80,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x80,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x80,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_u32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x80,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x80,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_u32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_u32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_u32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x82,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x82,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x82,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_u32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x82,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x82,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x82,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x82,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_u32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x82,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_u32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x82,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x84,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x84,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x84,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x84,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x84,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x86,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x86,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x86,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x86,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x86,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x86,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x86,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_sub_rtn_u32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x86,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_sub_rtn_u32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x86,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x88,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x88,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x88,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x88,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x88,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8a,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8a,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_rsub_rtn_u32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_rsub_rtn_u32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8a,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x8c,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x8c,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x8e,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x8e,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_inc_rtn_u32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_inc_rtn_u32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8e,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x90,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x90,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x90,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x90,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x90,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x92,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x92,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x92,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x92,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x92,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x92,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x92,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_dec_rtn_u32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x92,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_dec_rtn_u32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x92,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_i32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_i32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_i32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_i32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x94,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_i32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x94,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x94,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_i32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x94,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x94,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_i32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_i32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_i32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_i32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_i32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_i32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x96,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_i32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x96,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x96,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_i32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x96,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x96,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_i32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x96,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x96,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_i32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x96,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_i32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x96,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_i32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_i32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_i32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_i32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x98,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x98,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_i32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x98,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x98,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_i32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x98,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x98,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_i32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_i32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_i32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_i32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_i32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_i32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9a,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_i32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_i32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9a,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_i32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_i32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_i32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9a,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_u32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_u32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_u32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_u32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x9c,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_u32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_u32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x9c,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_u32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_u32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_u32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_u32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_u32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_u32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x9e,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_u32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_u32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x9e,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_rtn_u32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_min_rtn_u32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_min_rtn_u32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9e,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_u32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_u32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_u32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_u32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xa0,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_u32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_u32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa0,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_u32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_u32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa0,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_u32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_u32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_u32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_u32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa2,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_u32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_u32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa2,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_rtn_u32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_max_rtn_u32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_max_rtn_u32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa2,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_rtn_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_and_rtn_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_rtn_b32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_and_rtn_b32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xa4,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_rtn_b32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_and_rtn_b32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa4,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_rtn_b32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_and_rtn_b32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa4,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_rtn_b32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_and_rtn_b32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_rtn_b32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_and_rtn_b32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xa6,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_rtn_b32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_and_rtn_b32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xa6,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_rtn_b32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_and_rtn_b32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_and_rtn_b32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa6,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_rtn_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_or_rtn_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_rtn_b32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_or_rtn_b32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xa8,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_rtn_b32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_or_rtn_b32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xa8,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_rtn_b32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_or_rtn_b32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xa8,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_rtn_b32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_or_rtn_b32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_rtn_b32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_or_rtn_b32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xaa,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_rtn_b32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_or_rtn_b32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xaa,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_rtn_b32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_or_rtn_b32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_or_rtn_b32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xaa,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xac,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xac,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xac,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xac,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xac,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xac,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xac,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xac,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xac,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xac,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xac,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xae,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xae,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xae,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xae,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xae,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xae,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xae,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xae,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xae,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_xor_rtn_b32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xae,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_xor_rtn_b32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xae,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_mskor_rtn_b32 v0, v1, v2, v3
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_rtn_b32 v255, v254, v253, v252
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v0, v254, v253, v252
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0xfc,0x00]
+
+ds_mskor_rtn_b32 v255, v1, v253, v252
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0x01,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v2, v252
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0x02,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v253, v3
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0x03,0xff]
+
+ds_mskor_rtn_b32 v0, v1, v2, v3 offset:0
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_rtn_b32 v255, v254, v253, v252 offset:0
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v0, v254, v253, v252 offset:0
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0xfc,0x00]
+
+ds_mskor_rtn_b32 v255, v1, v253, v252 offset:0
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0x01,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v2, v252 offset:0
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0x02,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v253, v3 offset:0
+// GFX10: encoding: [0x00,0x00,0xb0,0xd8,0xfe,0xfd,0x03,0xff]
+
+ds_mskor_rtn_b32 v0, v1, v2, v3 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_rtn_b32 v255, v254, v253, v252 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0xfe,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v0, v254, v253, v252 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0xfe,0xfd,0xfc,0x00]
+
+ds_mskor_rtn_b32 v255, v1, v253, v252 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0x01,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v2, v252 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0xfe,0x02,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v253, v3 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb0,0xd8,0xfe,0xfd,0x03,0xff]
+
+ds_mskor_rtn_b32 v0, v1, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_rtn_b32 v255, v254, v253, v252 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0xfe,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v0, v254, v253, v252 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0xfe,0xfd,0xfc,0x00]
+
+ds_mskor_rtn_b32 v255, v1, v253, v252 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0x01,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v2, v252 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0xfe,0x02,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v253, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd8,0xfe,0xfd,0x03,0xff]
+
+ds_mskor_rtn_b32 v0, v1, v2, v3 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_rtn_b32 v255, v254, v253, v252 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v0, v254, v253, v252 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0xfc,0x00]
+
+ds_mskor_rtn_b32 v255, v1, v253, v252 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0x01,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v2, v252 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0x02,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v253, v3 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0x03,0xff]
+
+ds_mskor_rtn_b32 v0, v1, v2, v3 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_rtn_b32 v255, v254, v253, v252 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v0, v254, v253, v252 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0xfc,0x00]
+
+ds_mskor_rtn_b32 v255, v1, v253, v252 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0x01,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v2, v252 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0x02,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v253, v3 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb2,0xd8,0xfe,0xfd,0x03,0xff]
+
+ds_mskor_rtn_b32 v0, v1, v2, v3 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_rtn_b32 v255, v254, v253, v252 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0xfe,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v0, v254, v253, v252 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0xfe,0xfd,0xfc,0x00]
+
+ds_mskor_rtn_b32 v255, v1, v253, v252 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0x01,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v2, v252 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0xfe,0x02,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v253, v3 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb2,0xd8,0xfe,0xfd,0x03,0xff]
+
+ds_mskor_rtn_b32 v0, v1, v2, v3 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_rtn_b32 v255, v254, v253, v252 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0xfe,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v0, v254, v253, v252 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0xfe,0xfd,0xfc,0x00]
+
+ds_mskor_rtn_b32 v255, v1, v253, v252 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0x01,0xfd,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v2, v252 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0xfe,0x02,0xfc,0xff]
+
+ds_mskor_rtn_b32 v255, v254, v253, v3 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb2,0xd8,0xfe,0xfd,0x03,0xff]
+
+ds_wrxchg_rtn_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xb4,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xb4,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xb4,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xb6,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0xb6,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0xfe,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0xfe,0xfd,0x00,0x00]
+
+ds_wrxchg_rtn_b32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0x01,0xfd,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb6,0xd8,0xfe,0x02,0x00,0xff]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_wrxchg2_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset1:255
+// GFX10: encoding: [0x00,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127
+// GFX10: encoding: [0x7f,0x00,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0xba,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset1:255
+// GFX10: encoding: [0x00,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127
+// GFX10: encoding: [0x7f,0x00,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0xbe,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v255, v1, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x03,0xff]
+
+ds_cmpst_rtn_b32 v5, v255, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v255, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0x01,0xff,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd8,0x01,0x02,0xff,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:0
+// GFX10: encoding: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:4
+// GFX10: encoding: [0x04,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v255, v1, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x03,0xff]
+
+ds_cmpst_rtn_f32 v5, v255, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v255, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0x01,0xff,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd8,0x01,0x02,0xff,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:0
+// GFX10: encoding: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:4
+// GFX10: encoding: [0x04,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x03,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v255, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_f32 v5, v255, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2
+// GFX10: encoding: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:4
+// GFX10: encoding: [0x04,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v255, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_f32 v5, v255, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2
+// GFX10: encoding: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:4
+// GFX10: encoding: [0x04,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
+
+ds_wrap_rtn_b32 v5, v255, v2, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v255, v3 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd0,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:0
+// GFX10: encoding: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:4
+// GFX10: encoding: [0x04,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_swizzle_b32 v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
+
+ds_swizzle_b32 v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1
+// GFX10: encoding: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd8,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_b32 v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd8,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1
+// GFX10: encoding: [0x00,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xda,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xdc,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read2_b32 v[5:6], v255 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xdc,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset1:255
+// GFX10: encoding: [0x00,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127
+// GFX10: encoding: [0x7f,0x00,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0xde,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xe0,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read2st64_b32 v[5:6], v255 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xe0,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset1:255
+// GFX10: encoding: [0x00,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127
+// GFX10: encoding: [0x7f,0x00,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0xe2,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xe4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xe4,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i8 v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xe4,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1
+// GFX10: encoding: [0x00,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xe6,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xe8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xe8,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u8 v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xe8,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1
+// GFX10: encoding: [0x00,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xea,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i16 v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xec,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1
+// GFX10: encoding: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf0,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u16 v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf0,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1
+// GFX10: encoding: [0x00,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xf2,0xd8,0x01,0x00,0x00,0x05]
+
+ds_consume v5 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf4,0xd8,0x00,0x00,0x00,0x05]
+
+ds_consume v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf4,0xd8,0x00,0x00,0x00,0xff]
+
+ds_consume v5
+// GFX10: encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:0
+// GFX10: encoding: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:4
+// GFX10: encoding: [0x04,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xf6,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf8,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf8,0xd8,0x00,0x00,0x00,0xff]
+
+ds_append v5
+// GFX10: encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:0
+// GFX10: encoding: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:4
+// GFX10: encoding: [0x04,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xfa,0xd8,0x00,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xfe,0xd8,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v255, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xfe,0xd8,0x01,0x00,0x00,0xff]
+
+ds_ordered_count v5, v255 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xfe,0xd8,0xff,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 gds
+// GFX10: encoding: [0x00,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:4 gds
+// GFX10: encoding: [0x04,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
+
+ds_add_u64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xd9,0xff,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_add_u64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x02,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x06,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xd9,0xff,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0a,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xd9,0xff,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0e,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xd9,0xff,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x12,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xd9,0xff,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_min_i64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x16,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xd9,0xff,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_max_i64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1a,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xd9,0xff,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_min_u64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1e,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xd9,0xff,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_max_u64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x22,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xd9,0xff,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_and_b64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x26,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xd9,0xff,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_or_b64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2a,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xd9,0xff,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2e,0xd9,0x01,0x02,0x00,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x30,0xd9,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v255, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x30,0xd9,0xff,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[254:255], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x30,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x30,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4]
+// GFX10: encoding: [0x00,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:0
+// GFX10: encoding: [0x00,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:4
+// GFX10: encoding: [0x04,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x32,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write_b64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xd9,0xff,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_write_b64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x36,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0x38,0xd9,0xff,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0x38,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0x38,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
+// GFX10: encoding: [0x00,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
+// GFX10: encoding: [0x7f,0x00,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0x3a,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0x3c,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0x3c,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset1:255
+// GFX10: encoding: [0x00,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127
+// GFX10: encoding: [0x7f,0x00,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0x3e,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x40,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v255, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x40,0xd9,0xff,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[254:255], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x40,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x40,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4]
+// GFX10: encoding: [0x00,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:0
+// GFX10: encoding: [0x00,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:4
+// GFX10: encoding: [0x04,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x42,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x44,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v255, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x44,0xd9,0xff,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[254:255], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x44,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x44,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4]
+// GFX10: encoding: [0x00,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:0
+// GFX10: encoding: [0x00,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:4
+// GFX10: encoding: [0x04,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x46,0xd9,0x01,0x02,0x03,0x00]
+
+ds_min_f64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xd9,0xff,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_min_f64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4a,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xd9,0xff,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_max_f64 v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4e,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_f32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_f32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_f32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_f32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_f32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_f32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xd9,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_f32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x54,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_f32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x54,0xd9,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x54,0xd9,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_f32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0x54,0xd9,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0x54,0xd9,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_f32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_f32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xd9,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xd9,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_f32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xd9,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xd9,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_f32 v0, v1, v2 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_f32 v255, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v0, v254, v253 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_f32 v255, v1, v253 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v255, v254, v2 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_f32 v0, v1, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_f32 v255, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v0, v254, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_f32 v255, v1, v253 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v255, v254, v2 offset:0 gds
+// GFX10: encoding: [0x00,0x00,0x56,0xd9,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_f32 v0, v1, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x56,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_f32 v255, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x56,0xd9,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v0, v254, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x56,0xd9,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_f32 v255, v1, v253 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x56,0xd9,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v255, v254, v2 offset:4660 gds
+// GFX10: encoding: [0x34,0x12,0x56,0xd9,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_f32 v0, v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_f32 v255, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xd9,0xfe,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v0, v254, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xd9,0xfe,0xfd,0x00,0x00]
+
+ds_add_rtn_f32 v255, v1, v253 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xd9,0x01,0xfd,0x00,0xff]
+
+ds_add_rtn_f32 v255, v254, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xd9,0xfe,0x02,0x00,0xff]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xd9,0xff,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x82,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_sub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xd9,0xff,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x86,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_rsub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xd9,0xff,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8a,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_inc_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xd9,0xff,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8e,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_dec_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xd9,0xff,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x92,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_i64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xd9,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x96,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_i64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xd9,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9a,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xd9,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9e,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa0,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa0,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa0,0xd9,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa0,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa2,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa4,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_and_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa4,0xd9,0xff,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa4,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xa6,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa8,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_or_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa8,0xd9,0xff,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xa8,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xaa,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xac,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xac,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_xor_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xac,0xd9,0xff,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xac,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xae,0xd9,0x01,0x02,0x00,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0x01,0x02,0x03,0xfe]
+
+ds_mskor_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0xff,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xb0,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// GFX10: encoding: [0x00,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// GFX10: encoding: [0x04,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb2,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xb4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xb4,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_wrxchg_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xb4,0xd9,0xff,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xb4,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xb6,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0x03,0xfc]
+
+ds_wrxchg2_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
+// GFX10: encoding: [0x00,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
+// GFX10: encoding: [0x7f,0x00,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0xba,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0x03,0xfc]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
+// GFX10: encoding: [0x00,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
+// GFX10: encoding: [0x7f,0x00,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0xbe,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0x01,0x02,0x03,0xfe]
+
+ds_cmpst_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
+// GFX10: encoding: [0x00,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// GFX10: encoding: [0x00,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// GFX10: encoding: [0x04,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xc2,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0x01,0x02,0x03,0xfe]
+
+ds_cmpst_rtn_f64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4]
+// GFX10: encoding: [0x00,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// GFX10: encoding: [0x00,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// GFX10: encoding: [0x04,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xc6,0xd9,0x01,0x02,0x03,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_f64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xd9,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xca,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_f64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xd9,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xce,0xd9,0x01,0x02,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd8,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[254:255], v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd8,0xd9,0x01,0x00,0x00,0xfe]
+
+ds_read_b64 v[5:6], v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xd8,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1
+// GFX10: encoding: [0x00,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:0
+// GFX10: encoding: [0x00,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:4
+// GFX10: encoding: [0x04,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xda,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xdc,0xd9,0x01,0x00,0x00,0xfc]
+
+ds_read2_b64 v[5:8], v255 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xdc,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset1:255
+// GFX10: encoding: [0x00,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127
+// GFX10: encoding: [0x7f,0x00,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0xde,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xe0,0xd9,0x01,0x00,0x00,0xfc]
+
+ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255
+// GFX10: encoding: [0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset1:255
+// GFX10: encoding: [0x00,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:0 offset1:255
+// GFX10: encoding: [0x00,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:16 offset1:255
+// GFX10: encoding: [0x10,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127
+// GFX10: encoding: [0x7f,0x00,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:0
+// GFX10: encoding: [0x7f,0x00,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:1
+// GFX10: encoding: [0x7f,0x01,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255 gds
+// GFX10: encoding: [0x7f,0xff,0xe2,0xd9,0x01,0x00,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xf8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xf8,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_condxchg32_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// GFX10: encoding: [0xff,0xff,0xf8,0xd9,0xff,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0xf8,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// GFX10: encoding: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// GFX10: encoding: [0x04,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xfa,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_src2_u32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xda,0xff,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1
+// GFX10: encoding: [0x00,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x02,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xda,0xff,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1
+// GFX10: encoding: [0x00,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x06,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xda,0xff,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1
+// GFX10: encoding: [0x00,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0a,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xda,0xff,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1
+// GFX10: encoding: [0x00,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0e,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xda,0xff,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1
+// GFX10: encoding: [0x00,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x12,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xda,0xff,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1
+// GFX10: encoding: [0x00,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x16,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xda,0xff,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1
+// GFX10: encoding: [0x00,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1a,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xda,0xff,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1
+// GFX10: encoding: [0x00,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1e,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xda,0xff,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1
+// GFX10: encoding: [0x00,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x22,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xda,0xff,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1
+// GFX10: encoding: [0x00,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x26,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xda,0xff,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1
+// GFX10: encoding: [0x00,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2a,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xda,0xff,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1
+// GFX10: encoding: [0x00,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2e,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xda,0xff,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1
+// GFX10: encoding: [0x00,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x36,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xda,0xff,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1
+// GFX10: encoding: [0x00,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4a,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xda,0xff,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1
+// GFX10: encoding: [0x00,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4e,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x54,0xda,0xff,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1
+// GFX10: encoding: [0x00,0x00,0x54,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x54,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x54,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x56,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xda,0x01,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v255, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xda,0xff,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x80,0xda,0x01,0xff,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2
+// GFX10: encoding: [0x00,0x00,0x80,0xda,0x01,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x80,0xda,0x01,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2 offset:4
+// GFX10: encoding: [0x04,0x00,0x80,0xda,0x01,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x82,0xda,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xda,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v255, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xda,0xff,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x84,0xda,0x01,0xff,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2
+// GFX10: encoding: [0x00,0x00,0x84,0xda,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0x84,0xda,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2 offset:4
+// GFX10: encoding: [0x04,0x00,0x84,0xda,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x86,0xda,0x01,0x02,0x00,0x00]
+
+ds_read_u8_d16 v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xda,0x01,0x00,0x00,0xff]
+
+ds_read_u8_d16 v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x88,0xda,0xff,0x00,0x00,0x05]
+
+ds_read_u8_d16 v5, v1
+// GFX10: encoding: [0x00,0x00,0x88,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16 v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x88,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16 v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x88,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16 v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8a,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xda,0x01,0x00,0x00,0xff]
+
+ds_read_u8_d16_hi v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x8c,0xda,0xff,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1
+// GFX10: encoding: [0x00,0x00,0x8c,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x8c,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x8c,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x8e,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xda,0x01,0x00,0x00,0xff]
+
+ds_read_i8_d16 v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x90,0xda,0xff,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1
+// GFX10: encoding: [0x00,0x00,0x90,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x90,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x90,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x92,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xda,0x01,0x00,0x00,0xff]
+
+ds_read_i8_d16_hi v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x94,0xda,0xff,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1
+// GFX10: encoding: [0x00,0x00,0x94,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x94,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x94,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x96,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xda,0x01,0x00,0x00,0xff]
+
+ds_read_u16_d16 v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x98,0xda,0xff,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1
+// GFX10: encoding: [0x00,0x00,0x98,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x98,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x98,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9a,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v255, v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xda,0x01,0x00,0x00,0xff]
+
+ds_read_u16_d16_hi v5, v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x9c,0xda,0xff,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1
+// GFX10: encoding: [0x00,0x00,0x9c,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x9c,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x9c,0xda,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x9e,0xda,0x01,0x00,0x00,0x05]
+
+ds_write_addtid_b32 v5 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0x05,0x00,0x00]
+
+ds_write_addtid_b32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc0,0xda,0x00,0xff,0x00,0x00]
+
+ds_write_addtid_b32 v5
+// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
+
+ds_write_addtid_b32 v5 offset:0
+// GFX10: encoding: [0x00,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
+
+ds_write_addtid_b32 v5 offset:4
+// GFX10: encoding: [0x04,0x00,0xc0,0xda,0x00,0x05,0x00,0x00]
+
+ds_write_addtid_b32 v5 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xc2,0xda,0x00,0x05,0x00,0x00]
+
+ds_read_addtid_b32 v5 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0x05]
+
+ds_read_addtid_b32 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc4,0xda,0x00,0x00,0x00,0xff]
+
+ds_read_addtid_b32 v5
+// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
+
+ds_read_addtid_b32 v5 offset:0
+// GFX10: encoding: [0x00,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
+
+ds_read_addtid_b32 v5 offset:4
+// GFX10: encoding: [0x04,0x00,0xc4,0xda,0x00,0x00,0x00,0x05]
+
+ds_read_addtid_b32 v5 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xc6,0xda,0x00,0x00,0x00,0x05]
+
+ds_permute_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0x02,0x00,0x00]
+
+ds_permute_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0xfd,0x00,0xff]
+
+ds_permute_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0xfd,0x00,0x00]
+
+ds_permute_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0xfd,0x00,0xff]
+
+ds_permute_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0x02,0x00,0xff]
+
+ds_permute_b32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0x02,0x00,0x00]
+
+ds_permute_b32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0xfd,0x00,0xff]
+
+ds_permute_b32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0xfd,0x00,0x00]
+
+ds_permute_b32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0x01,0xfd,0x00,0xff]
+
+ds_permute_b32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xc8,0xda,0xfe,0x02,0x00,0xff]
+
+ds_permute_b32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xc8,0xda,0x01,0x02,0x00,0x00]
+
+ds_permute_b32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xc8,0xda,0xfe,0xfd,0x00,0xff]
+
+ds_permute_b32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xc8,0xda,0xfe,0xfd,0x00,0x00]
+
+ds_permute_b32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xc8,0xda,0x01,0xfd,0x00,0xff]
+
+ds_permute_b32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xc8,0xda,0xfe,0x02,0x00,0xff]
+
+ds_permute_b32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xda,0x01,0x02,0x00,0x00]
+
+ds_permute_b32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xda,0xfe,0xfd,0x00,0xff]
+
+ds_permute_b32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xda,0xfe,0xfd,0x00,0x00]
+
+ds_permute_b32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xda,0x01,0xfd,0x00,0xff]
+
+ds_permute_b32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xc8,0xda,0xfe,0x02,0x00,0xff]
+
+ds_bpermute_b32 v0, v1, v2
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0x01,0x02,0x00,0x00]
+
+ds_bpermute_b32 v255, v254, v253
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0xfd,0x00,0xff]
+
+ds_bpermute_b32 v0, v254, v253
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0xfd,0x00,0x00]
+
+ds_bpermute_b32 v255, v1, v253
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0x01,0xfd,0x00,0xff]
+
+ds_bpermute_b32 v255, v254, v2
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0x02,0x00,0xff]
+
+ds_bpermute_b32 v0, v1, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0x01,0x02,0x00,0x00]
+
+ds_bpermute_b32 v255, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0xfd,0x00,0xff]
+
+ds_bpermute_b32 v0, v254, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0xfd,0x00,0x00]
+
+ds_bpermute_b32 v255, v1, v253 offset:0
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0x01,0xfd,0x00,0xff]
+
+ds_bpermute_b32 v255, v254, v2 offset:0
+// GFX10: encoding: [0x00,0x00,0xcc,0xda,0xfe,0x02,0x00,0xff]
+
+ds_bpermute_b32 v0, v1, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xcc,0xda,0x01,0x02,0x00,0x00]
+
+ds_bpermute_b32 v255, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xcc,0xda,0xfe,0xfd,0x00,0xff]
+
+ds_bpermute_b32 v0, v254, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xcc,0xda,0xfe,0xfd,0x00,0x00]
+
+ds_bpermute_b32 v255, v1, v253 offset:4660
+// GFX10: encoding: [0x34,0x12,0xcc,0xda,0x01,0xfd,0x00,0xff]
+
+ds_bpermute_b32 v255, v254, v2 offset:4660
+// GFX10: encoding: [0x34,0x12,0xcc,0xda,0xfe,0x02,0x00,0xff]
+
+ds_bpermute_b32 v0, v1, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xda,0x01,0x02,0x00,0x00]
+
+ds_bpermute_b32 v255, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xda,0xfe,0xfd,0x00,0xff]
+
+ds_bpermute_b32 v0, v254, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xda,0xfe,0xfd,0x00,0x00]
+
+ds_bpermute_b32 v255, v1, v253 offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xda,0x01,0xfd,0x00,0xff]
+
+ds_bpermute_b32 v255, v254, v2 offset:65535
+// GFX10: encoding: [0xff,0xff,0xcc,0xda,0xfe,0x02,0x00,0xff]
+
+ds_add_src2_u64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xdb,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x00,0xdb,0xff,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1
+// GFX10: encoding: [0x00,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x02,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x04,0xdb,0xff,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1
+// GFX10: encoding: [0x00,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x06,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x08,0xdb,0xff,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1
+// GFX10: encoding: [0x00,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0a,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x0c,0xdb,0xff,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1
+// GFX10: encoding: [0x00,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x0e,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x10,0xdb,0xff,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1
+// GFX10: encoding: [0x00,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x12,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x14,0xdb,0xff,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1
+// GFX10: encoding: [0x00,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x16,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x18,0xdb,0xff,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1
+// GFX10: encoding: [0x00,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1a,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x1c,0xdb,0xff,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1
+// GFX10: encoding: [0x00,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x1e,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x20,0xdb,0xff,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1
+// GFX10: encoding: [0x00,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x22,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x24,0xdb,0xff,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1
+// GFX10: encoding: [0x00,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x26,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x28,0xdb,0xff,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1
+// GFX10: encoding: [0x00,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2a,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x2c,0xdb,0xff,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1
+// GFX10: encoding: [0x00,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x2e,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x34,0xdb,0xff,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1
+// GFX10: encoding: [0x00,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x36,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x48,0xdb,0xff,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1
+// GFX10: encoding: [0x00,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4a,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0x4c,0xdb,0xff,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1
+// GFX10: encoding: [0x00,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:0
+// GFX10: encoding: [0x00,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:4
+// GFX10: encoding: [0x04,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x4e,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x78,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v255, v[2:4] offset:65535
+// GFX10: encoding: [0xff,0xff,0x78,0xdb,0xff,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[253:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x78,0xdb,0x01,0xfd,0x00,0x00]
+
+ds_write_b96 v1, v[2:4]
+// GFX10: encoding: [0x00,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:0
+// GFX10: encoding: [0x00,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:4
+// GFX10: encoding: [0x04,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7a,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:65535
+// GFX10: encoding: [0xff,0xff,0x7c,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v255, v[2:5] offset:65535
+// GFX10: encoding: [0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[252:255] offset:65535
+// GFX10: encoding: [0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00]
+
+ds_write_b128 v1, v[2:5]
+// GFX10: encoding: [0x00,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:0
+// GFX10: encoding: [0x00,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:4
+// GFX10: encoding: [0x04,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0x7e,0xdb,0x01,0x02,0x00,0x00]
+
+ds_read_b96 v[5:7], v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf8,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[253:255], v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf8,0xdb,0x01,0x00,0x00,0xfd]
+
+ds_read_b96 v[5:7], v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xf8,0xdb,0xff,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1
+// GFX10: encoding: [0x00,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:0
+// GFX10: encoding: [0x00,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:4
+// GFX10: encoding: [0x04,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xfa,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[252:255], v1 offset:65535
+// GFX10: encoding: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc]
+
+ds_read_b128 v[5:8], v255 offset:65535
+// GFX10: encoding: [0xff,0xff,0xfc,0xdb,0xff,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1
+// GFX10: encoding: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:0
+// GFX10: encoding: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:4
+// GFX10: encoding: [0x04,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:65535 gds
+// GFX10: encoding: [0xff,0xff,0xfe,0xdb,0x01,0x00,0x00,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_flat.s b/llvm/test/MC/AMDGPU/gfx10_asm_flat.s
new file mode 100644
index 0000000000000..7f3d9a04b9aa3
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_flat.s
@@ -0,0 +1,128 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+
+//===----------------------------------------------------------------------===//
+// ENC_FLAT.
+//===----------------------------------------------------------------------===//
+
+flat_load_ubyte v5, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x20,0xdc,0x01,0x00,0x7d,0x05]
+
+flat_load_sbyte v5, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x24,0xdc,0x01,0x00,0x7d,0x05]
+
+flat_load_ushort v5, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x28,0xdc,0x01,0x00,0x7d,0x05]
+
+flat_load_sshort v5, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x2c,0xdc,0x01,0x00,0x7d,0x05]
+
+flat_load_dword v5, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x30,0xdc,0x01,0x00,0x7d,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2]
+// GFX10: encoding: [0x00,0x00,0x34,0xdc,0x01,0x00,0x7d,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2]
+// GFX10: encoding: [0x00,0x00,0x3c,0xdc,0x01,0x00,0x7d,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2]
+// GFX10: encoding: [0x00,0x00,0x38,0xdc,0x01,0x00,0x7d,0x05]
+
+flat_store_byte v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0x60,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_store_short v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0x68,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_store_dword v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0x70,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x74,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4]
+// GFX10: encoding: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5]
+// GFX10: encoding: [0x00,0x00,0x78,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_swap v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xc0,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xc4,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_add v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xc8,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_sub v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xcc,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_smin v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_umin v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_smax v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_umax v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xe0,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_and v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xe4,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_or v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xe8,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_xor v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xec,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_inc v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xf0,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_dec v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xf4,0xdc,0x01,0x02,0x7d,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x40,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5]
+// GFX10: encoding: [0x00,0x00,0x44,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x48,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x4c,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x54,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x58,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x5c,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x60,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x64,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x68,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x6c,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x70,0xdd,0x01,0x02,0x7d,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x74,0xdd,0x01,0x02,0x7d,0x00]
+
+// Also see flat-gfx10.s, flat-global.s, flat-scratch-instructions.s.
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
new file mode 100644
index 0000000000000..8b6d85c55f28c
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mubuf.s
@@ -0,0 +1,2289 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+
+//===----------------------------------------------------------------------===//
+// ENC_MUBUF.
+//===----------------------------------------------------------------------===//
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_format_x v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_x v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_x v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_x v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_x v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x00,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xy v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x04,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0xfd,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x08,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0xfc,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x0c,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v255, off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_format_x v1, off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_x v1, off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_x v1, off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_x v1, off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_x v1, off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x10,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xy v[1:2], off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x14,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0xfd,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x18,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0xfc,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x1c,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ubyte v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_ubyte v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ubyte v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ubyte v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ubyte v5, off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ubyte v5, off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ubyte v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x20,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sbyte v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_sbyte v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sbyte v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sbyte v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sbyte v5, off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sbyte v5, off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sbyte v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x24,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ushort v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ushort v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_ushort v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ushort v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ushort v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ushort v5, off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ushort v5, off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x28,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sshort v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sshort v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_sshort v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sshort v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sshort v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sshort v5, off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sshort v5, off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sshort v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x2c,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_dword v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dword v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dword v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dword v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dword v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dword v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dword v5, off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dword v5, off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dword v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x30,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x34,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[253:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0xfd,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x3c,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[252:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0xfc,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x38,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v255, off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_byte v1, off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_byte v1, off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_byte v1, off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_byte v1, off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_byte v1, off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_byte v1, off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_byte v1, off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_byte v1, off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_byte v1, v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x60,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v255, off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_short v1, off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_short v1, off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_short v1, off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_short v1, off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_short v1, off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_short v1, off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_short v1, off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_short v1, off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_short v1, v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x68,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v255, off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_dword v1, off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dword v1, off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dword v1, off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dword v1, off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dword v1, off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dword v1, off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dword v1, off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dword v1, off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dword v1, v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x70,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[254:255], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x74,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[253:255], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0xfd,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x7c,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[252:255], off, s[12:15], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0xfc,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[16:19], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[96:99], s4 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], 0.5 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], -4.0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4
+// GFX10: encoding: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:7
+// GFX10: encoding: [0x07,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 dlc
+// GFX10: encoding: [0xff,0x8f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc slc dlc
+// GFX10: encoding: [0xff,0xcf,0x78,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_swap v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_swap v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_swap v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_swap v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_swap v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xc0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xc0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xc0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xc0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xc0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xc0,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xc4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xc4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xc4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xc4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xc4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xc4,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_add v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_add v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_add v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_add v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_add v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_add v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xc8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xc8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xc8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xc8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xc8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xc8,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_sub v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_sub v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_sub v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_sub v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_sub v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xcc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xcc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xcc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xcc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xcc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xcc,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smin v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smin v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smin v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smin v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smin v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xd4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xd4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xd4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xd4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xd4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xd4,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umin v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umin v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umin v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umin v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umin v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xd8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xd8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xd8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xd8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xd8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xd8,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smax v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smax v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smax v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smax v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smax v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xdc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xdc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xdc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xdc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xdc,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xdc,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umax v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umax v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umax v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umax v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umax v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xe0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xe0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xe0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xe0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xe0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xe0,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_and v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_and v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_and v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_and v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_and v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_and v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xe4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xe4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xe4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xe4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xe4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xe4,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_or v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_or v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_or v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_or v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_or v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_or v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xe8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xe8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xe8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xe8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xe8,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xe8,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_xor v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_xor v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_xor v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_xor v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_xor v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xec,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xec,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xec,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xec,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xec,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xec,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_inc v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_inc v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_inc v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_inc v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_inc v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xf0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xf0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xf0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xf0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xf0,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xf0,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v255, off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_atomic_dec v5, off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_atomic_dec v5, off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_dec v5, off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_atomic_dec v5, off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_dec v5, v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0xf4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0xf4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0xf4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0xf4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0xf4,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0xf4,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x40,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x40,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x40,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x40,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x40,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x40,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[252:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0xfc,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x44,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x44,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x44,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x44,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x44,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x44,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x48,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x48,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x48,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x48,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x48,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x48,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x4c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x4c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x4c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x4c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x4c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x4c,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x54,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x54,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x54,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x54,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x54,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x54,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x58,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x58,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x58,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x58,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x58,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x58,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x5c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x5c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x5c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x5c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x5c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x5c,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x60,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x60,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x60,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x60,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x60,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x60,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x64,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x64,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x64,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x64,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x64,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x64,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x68,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x68,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x68,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x68,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x68,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x68,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x6c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x6c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x6c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x6c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x6c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x6c,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x70,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x70,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x70,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x70,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x70,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x70,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[254:255], off, s[8:11], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[12:15], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[96:99], s3 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s101 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], m0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], -1 offset:4095
+// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// GFX10: encoding: [0xff,0x2f,0x74,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// GFX10: encoding: [0xff,0x1f,0x74,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3
+// GFX10: encoding: [0x00,0x00,0x74,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:7
+// GFX10: encoding: [0x07,0x00,0x74,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// GFX10: encoding: [0xff,0x4f,0x74,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// GFX10: encoding: [0xff,0x0f,0x74,0xe1,0x00,0x05,0x42,0x03]
+
+buffer_gl0_inv
+// GFX10: encoding: [0x00,0x00,0xc4,0xe1,0x00,0x00,0x00,0x00]
+
+buffer_gl1_inv
+// GFX10: encoding: [0x00,0x00,0xc8,0xe1,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_smem.s b/llvm/test/MC/AMDGPU/gfx10_asm_smem.s
new file mode 100644
index 0000000000000..edf70e7f4c47d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_smem.s
@@ -0,0 +1,1194 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+
+//===----------------------------------------------------------------------===//
+// ENC_SMEM.
+//===----------------------------------------------------------------------===//
+
+s_load_dword s5, s[2:3], s0
+// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword s101, s[2:3], s0
+// GFX10: encoding: [0x41,0x19,0x00,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword vcc_lo, s[2:3], s0
+// GFX10: encoding: [0x81,0x1a,0x00,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword vcc_hi, s[2:3], s0
+// GFX10: encoding: [0xc1,0x1a,0x00,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[4:5], s0
+// GFX10: encoding: [0x42,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[100:101], s0
+// GFX10: encoding: [0x72,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, vcc, s0
+// GFX10: encoding: [0x75,0x01,0x00,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xca]
+
+s_load_dword s5, s[2:3], vcc_lo
+// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xd4]
+
+s_load_dword s5, s[2:3], vcc_hi
+// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xd6]
+
+s_load_dword s5, s[2:3], m0
+// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xf8]
+
+s_load_dword s5, s[2:3], 0x0
+// GFX10: encoding: [0x41,0x01,0x00,0xf4,0x00,0x00,0x00,0xfa]
+
+s_load_dword s5, s[2:3], s0 glc
+// GFX10: encoding: [0x41,0x01,0x01,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], s0 dlc
+// GFX10: encoding: [0x41,0x41,0x00,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], s0 glc dlc
+// GFX10: encoding: [0x41,0x41,0x01,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], 0x1234 glc dlc
+// GFX10: encoding: [0x41,0x41,0x01,0xf4,0x34,0x12,0x00,0xfa]
+
+s_load_dwordx2 s[10:11], s[2:3], s0
+// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[12:13], s[2:3], s0
+// GFX10: encoding: [0x01,0x03,0x04,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[100:101], s[2:3], s0
+// GFX10: encoding: [0x01,0x19,0x04,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 vcc, s[2:3], s0
+// GFX10: encoding: [0x81,0x1a,0x04,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[4:5], s0
+// GFX10: encoding: [0x82,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[100:101], s0
+// GFX10: encoding: [0xb2,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], vcc, s0
+// GFX10: encoding: [0xb5,0x02,0x04,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], s101
+// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xca]
+
+s_load_dwordx2 s[10:11], s[2:3], vcc_lo
+// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xd4]
+
+s_load_dwordx2 s[10:11], s[2:3], vcc_hi
+// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xd6]
+
+s_load_dwordx2 s[10:11], s[2:3], m0
+// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xf8]
+
+s_load_dwordx2 s[10:11], s[2:3], 0x0
+// GFX10: encoding: [0x81,0x02,0x04,0xf4,0x00,0x00,0x00,0xfa]
+
+s_load_dwordx2 s[10:11], s[2:3], s0 glc
+// GFX10: encoding: [0x81,0x02,0x05,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], s0 dlc
+// GFX10: encoding: [0x81,0x42,0x04,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], s0 glc dlc
+// GFX10: encoding: [0x81,0x42,0x05,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], 0x1234 glc dlc
+// GFX10: encoding: [0x81,0x42,0x05,0xf4,0x34,0x12,0x00,0xfa]
+
+s_load_dwordx4 s[20:23], s[2:3], s0
+// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[24:27], s[2:3], s0
+// GFX10: encoding: [0x01,0x06,0x08,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[96:99], s[2:3], s0
+// GFX10: encoding: [0x01,0x18,0x08,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[4:5], s0
+// GFX10: encoding: [0x02,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[100:101], s0
+// GFX10: encoding: [0x32,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], vcc, s0
+// GFX10: encoding: [0x35,0x05,0x08,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], s101
+// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xca]
+
+s_load_dwordx4 s[20:23], s[2:3], vcc_lo
+// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xd4]
+
+s_load_dwordx4 s[20:23], s[2:3], vcc_hi
+// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xd6]
+
+s_load_dwordx4 s[20:23], s[2:3], m0
+// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xf8]
+
+s_load_dwordx4 s[20:23], s[2:3], 0x0
+// GFX10: encoding: [0x01,0x05,0x08,0xf4,0x00,0x00,0x00,0xfa]
+
+s_load_dwordx4 s[20:23], s[2:3], s0 glc
+// GFX10: encoding: [0x01,0x05,0x09,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], s0 dlc
+// GFX10: encoding: [0x01,0x45,0x08,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], s0 glc dlc
+// GFX10: encoding: [0x01,0x45,0x09,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], 0x1234 glc dlc
+// GFX10: encoding: [0x01,0x45,0x09,0xf4,0x34,0x12,0x00,0xfa]
+
+s_load_dwordx8 s[20:27], s[2:3], s0
+// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[24:31], s[2:3], s0
+// GFX10: encoding: [0x01,0x06,0x0c,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[92:99], s[2:3], s0
+// GFX10: encoding: [0x01,0x17,0x0c,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[4:5], s0
+// GFX10: encoding: [0x02,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[100:101], s0
+// GFX10: encoding: [0x32,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], vcc, s0
+// GFX10: encoding: [0x35,0x05,0x0c,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], s101
+// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xca]
+
+s_load_dwordx8 s[20:27], s[2:3], vcc_lo
+// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xd4]
+
+s_load_dwordx8 s[20:27], s[2:3], vcc_hi
+// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xd6]
+
+s_load_dwordx8 s[20:27], s[2:3], m0
+// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xf8]
+
+s_load_dwordx8 s[20:27], s[2:3], 0x0
+// GFX10: encoding: [0x01,0x05,0x0c,0xf4,0x00,0x00,0x00,0xfa]
+
+s_load_dwordx8 s[20:27], s[2:3], s0 glc
+// GFX10: encoding: [0x01,0x05,0x0d,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], s0 dlc
+// GFX10: encoding: [0x01,0x45,0x0c,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], s0 glc dlc
+// GFX10: encoding: [0x01,0x45,0x0d,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], 0x1234 glc dlc
+// GFX10: encoding: [0x01,0x45,0x0d,0xf4,0x34,0x12,0x00,0xfa]
+
+s_load_dwordx16 s[20:35], s[2:3], s0
+// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[24:39], s[2:3], s0
+// GFX10: encoding: [0x01,0x06,0x10,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[84:99], s[2:3], s0
+// GFX10: encoding: [0x01,0x15,0x10,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[4:5], s0
+// GFX10: encoding: [0x02,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[100:101], s0
+// GFX10: encoding: [0x32,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], vcc, s0
+// GFX10: encoding: [0x35,0x05,0x10,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], s101
+// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xca]
+
+s_load_dwordx16 s[20:35], s[2:3], vcc_lo
+// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xd4]
+
+s_load_dwordx16 s[20:35], s[2:3], vcc_hi
+// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xd6]
+
+s_load_dwordx16 s[20:35], s[2:3], m0
+// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xf8]
+
+s_load_dwordx16 s[20:35], s[2:3], 0x0
+// GFX10: encoding: [0x01,0x05,0x10,0xf4,0x00,0x00,0x00,0xfa]
+
+s_load_dwordx16 s[20:35], s[2:3], s0 glc
+// GFX10: encoding: [0x01,0x05,0x11,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], s0 dlc
+// GFX10: encoding: [0x01,0x45,0x10,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], s0 glc dlc
+// GFX10: encoding: [0x01,0x45,0x11,0xf4,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], 0x1234 glc dlc
+// GFX10: encoding: [0x01,0x45,0x11,0xf4,0x34,0x12,0x00,0xfa]
+
+s_buffer_load_dword s5, s[4:7], s0
+// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s101, s[4:7], s0
+// GFX10: encoding: [0x42,0x19,0x20,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword vcc_lo, s[4:7], s0
+// GFX10: encoding: [0x82,0x1a,0x20,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword vcc_hi, s[4:7], s0
+// GFX10: encoding: [0xc2,0x1a,0x20,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[8:11], s0
+// GFX10: encoding: [0x44,0x01,0x20,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[96:99], s0
+// GFX10: encoding: [0x70,0x01,0x20,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], s101
+// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xca]
+
+s_buffer_load_dword s5, s[4:7], vcc_lo
+// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xd4]
+
+s_buffer_load_dword s5, s[4:7], vcc_hi
+// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xd6]
+
+s_buffer_load_dword s5, s[4:7], m0
+// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xf8]
+
+s_buffer_load_dword s5, s[4:7], 0x0
+// GFX10: encoding: [0x42,0x01,0x20,0xf4,0x00,0x00,0x00,0xfa]
+
+s_buffer_load_dword s5, s[4:7], s0 glc
+// GFX10: encoding: [0x42,0x01,0x21,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], s0 dlc
+// GFX10: encoding: [0x42,0x41,0x20,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], s0 glc dlc
+// GFX10: encoding: [0x42,0x41,0x21,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], 0x1234 glc dlc
+// GFX10: encoding: [0x42,0x41,0x21,0xf4,0x34,0x12,0x00,0xfa]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s0
+// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[12:13], s[4:7], s0
+// GFX10: encoding: [0x02,0x03,0x24,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[100:101], s[4:7], s0
+// GFX10: encoding: [0x02,0x19,0x24,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 vcc, s[4:7], s0
+// GFX10: encoding: [0x82,0x1a,0x24,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[8:11], s0
+// GFX10: encoding: [0x84,0x02,0x24,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[96:99], s0
+// GFX10: encoding: [0xb0,0x02,0x24,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s101
+// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xca]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_lo
+// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xd4]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
+// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xd6]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], m0
+// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xf8]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], 0x0
+// GFX10: encoding: [0x82,0x02,0x24,0xf4,0x00,0x00,0x00,0xfa]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc
+// GFX10: encoding: [0x82,0x02,0x25,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s0 dlc
+// GFX10: encoding: [0x82,0x42,0x24,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc dlc
+// GFX10: encoding: [0x82,0x42,0x25,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], 0x1234 glc dlc
+// GFX10: encoding: [0x82,0x42,0x25,0xf4,0x34,0x12,0x00,0xfa]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s0
+// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[24:27], s[4:7], s0
+// GFX10: encoding: [0x02,0x06,0x28,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[96:99], s[4:7], s0
+// GFX10: encoding: [0x02,0x18,0x28,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[8:11], s0
+// GFX10: encoding: [0x04,0x05,0x28,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[96:99], s0
+// GFX10: encoding: [0x30,0x05,0x28,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s101
+// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xca]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_lo
+// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xd4]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
+// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xd6]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], m0
+// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xf8]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], 0x0
+// GFX10: encoding: [0x02,0x05,0x28,0xf4,0x00,0x00,0x00,0xfa]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc
+// GFX10: encoding: [0x02,0x05,0x29,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s0 dlc
+// GFX10: encoding: [0x02,0x45,0x28,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc dlc
+// GFX10: encoding: [0x02,0x45,0x29,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], 0x1234 glc dlc
+// GFX10: encoding: [0x02,0x45,0x29,0xf4,0x34,0x12,0x00,0xfa]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s0
+// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[24:31], s[4:7], s0
+// GFX10: encoding: [0x02,0x06,0x2c,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[92:99], s[4:7], s0
+// GFX10: encoding: [0x02,0x17,0x2c,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[8:11], s0
+// GFX10: encoding: [0x04,0x05,0x2c,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[96:99], s0
+// GFX10: encoding: [0x30,0x05,0x2c,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s101
+// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xca]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_lo
+// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xd4]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
+// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xd6]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], m0
+// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xf8]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], 0x0
+// GFX10: encoding: [0x02,0x05,0x2c,0xf4,0x00,0x00,0x00,0xfa]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc
+// GFX10: encoding: [0x02,0x05,0x2d,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s0 dlc
+// GFX10: encoding: [0x02,0x45,0x2c,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc dlc
+// GFX10: encoding: [0x02,0x45,0x2d,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], 0x1234 glc dlc
+// GFX10: encoding: [0x02,0x45,0x2d,0xf4,0x34,0x12,0x00,0xfa]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s0
+// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[24:39], s[4:7], s0
+// GFX10: encoding: [0x02,0x06,0x30,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[84:99], s[4:7], s0
+// GFX10: encoding: [0x02,0x15,0x30,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[8:11], s0
+// GFX10: encoding: [0x04,0x05,0x30,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[96:99], s0
+// GFX10: encoding: [0x30,0x05,0x30,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s101
+// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xca]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_lo
+// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xd4]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
+// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xd6]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], m0
+// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xf8]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], 0x0
+// GFX10: encoding: [0x02,0x05,0x30,0xf4,0x00,0x00,0x00,0xfa]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc
+// GFX10: encoding: [0x02,0x05,0x31,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s0 dlc
+// GFX10: encoding: [0x02,0x45,0x30,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc dlc
+// GFX10: encoding: [0x02,0x45,0x31,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], 0x1234 glc dlc
+// GFX10: encoding: [0x02,0x45,0x31,0xf4,0x34,0x12,0x00,0xfa]
+
+s_store_dword s1, s[4:5], s0
+// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword s101, s[4:5], s0
+// GFX10: encoding: [0x42,0x19,0x40,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword vcc_lo, s[4:5], s0
+// GFX10: encoding: [0x82,0x1a,0x40,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword vcc_hi, s[4:5], s0
+// GFX10: encoding: [0xc2,0x1a,0x40,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[6:7], s0
+// GFX10: encoding: [0x43,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[100:101], s0
+// GFX10: encoding: [0x72,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, vcc, s0
+// GFX10: encoding: [0x75,0x00,0x40,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], s101
+// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xca]
+
+s_store_dword s1, s[4:5], vcc_lo
+// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xd4]
+
+s_store_dword s1, s[4:5], vcc_hi
+// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xd6]
+
+s_store_dword s1, s[4:5], m0
+// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xf8]
+
+s_store_dword s1, s[4:5], 0x0
+// GFX10: encoding: [0x42,0x00,0x40,0xf4,0x00,0x00,0x00,0xfa]
+
+s_store_dword s1, s[4:5], s0 glc
+// GFX10: encoding: [0x42,0x00,0x41,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], s0 dlc
+// GFX10: encoding: [0x42,0x40,0x40,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], s0 glc dlc
+// GFX10: encoding: [0x42,0x40,0x41,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], 0x1234 glc dlc
+// GFX10: encoding: [0x42,0x40,0x41,0xf4,0x34,0x12,0x00,0xfa]
+
+s_store_dwordx2 s[2:3], s[4:5], s0
+// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[4:5], s[4:5], s0
+// GFX10: encoding: [0x02,0x01,0x44,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[100:101], s[4:5], s0
+// GFX10: encoding: [0x02,0x19,0x44,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 vcc, s[4:5], s0
+// GFX10: encoding: [0x82,0x1a,0x44,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[6:7], s0
+// GFX10: encoding: [0x83,0x00,0x44,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[100:101], s0
+// GFX10: encoding: [0xb2,0x00,0x44,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], vcc, s0
+// GFX10: encoding: [0xb5,0x00,0x44,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], s101
+// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xca]
+
+s_store_dwordx2 s[2:3], s[4:5], vcc_lo
+// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xd4]
+
+s_store_dwordx2 s[2:3], s[4:5], vcc_hi
+// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xd6]
+
+s_store_dwordx2 s[2:3], s[4:5], m0
+// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xf8]
+
+s_store_dwordx2 s[2:3], s[4:5], 0x0
+// GFX10: encoding: [0x82,0x00,0x44,0xf4,0x00,0x00,0x00,0xfa]
+
+s_store_dwordx2 s[2:3], s[4:5], s0 glc
+// GFX10: encoding: [0x82,0x00,0x45,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], s0 dlc
+// GFX10: encoding: [0x82,0x40,0x44,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], s0 glc dlc
+// GFX10: encoding: [0x82,0x40,0x45,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], 0x1234 glc dlc
+// GFX10: encoding: [0x82,0x40,0x45,0xf4,0x34,0x12,0x00,0xfa]
+
+s_store_dwordx4 s[4:7], s[4:5], s0
+// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[8:11], s[4:5], s0
+// GFX10: encoding: [0x02,0x02,0x48,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[96:99], s[4:5], s0
+// GFX10: encoding: [0x02,0x18,0x48,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[6:7], s0
+// GFX10: encoding: [0x03,0x01,0x48,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[100:101], s0
+// GFX10: encoding: [0x32,0x01,0x48,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], vcc, s0
+// GFX10: encoding: [0x35,0x01,0x48,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], s101
+// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xca]
+
+s_store_dwordx4 s[4:7], s[4:5], vcc_lo
+// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xd4]
+
+s_store_dwordx4 s[4:7], s[4:5], vcc_hi
+// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xd6]
+
+s_store_dwordx4 s[4:7], s[4:5], m0
+// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xf8]
+
+s_store_dwordx4 s[4:7], s[4:5], 0x0
+// GFX10: encoding: [0x02,0x01,0x48,0xf4,0x00,0x00,0x00,0xfa]
+
+s_store_dwordx4 s[4:7], s[4:5], s0 glc
+// GFX10: encoding: [0x02,0x01,0x49,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], s0 dlc
+// GFX10: encoding: [0x02,0x41,0x48,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], s0 glc dlc
+// GFX10: encoding: [0x02,0x41,0x49,0xf4,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], 0x1234 glc dlc
+// GFX10: encoding: [0x02,0x41,0x49,0xf4,0x34,0x12,0x00,0xfa]
+
+s_buffer_store_dword s1, s[8:11], s0
+// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s101, s[8:11], s0
+// GFX10: encoding: [0x44,0x19,0x60,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword vcc_lo, s[8:11], s0
+// GFX10: encoding: [0x84,0x1a,0x60,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword vcc_hi, s[8:11], s0
+// GFX10: encoding: [0xc4,0x1a,0x60,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[12:15], s0
+// GFX10: encoding: [0x46,0x00,0x60,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[96:99], s0
+// GFX10: encoding: [0x70,0x00,0x60,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], s101
+// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xca]
+
+s_buffer_store_dword s1, s[8:11], vcc_lo
+// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xd4]
+
+s_buffer_store_dword s1, s[8:11], vcc_hi
+// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xd6]
+
+s_buffer_store_dword s1, s[8:11], m0
+// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xf8]
+
+s_buffer_store_dword s1, s[8:11], 0x0
+// GFX10: encoding: [0x44,0x00,0x60,0xf4,0x00,0x00,0x00,0xfa]
+
+s_buffer_store_dword s1, s[8:11], s0 glc
+// GFX10: encoding: [0x44,0x00,0x61,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], s0 dlc
+// GFX10: encoding: [0x44,0x40,0x60,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], s0 glc dlc
+// GFX10: encoding: [0x44,0x40,0x61,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], 0x1234 glc dlc
+// GFX10: encoding: [0x44,0x40,0x61,0xf4,0x34,0x12,0x00,0xfa]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], s0
+// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[4:5], s[8:11], s0
+// GFX10: encoding: [0x04,0x01,0x64,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[100:101], s[8:11], s0
+// GFX10: encoding: [0x04,0x19,0x64,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 vcc, s[8:11], s0
+// GFX10: encoding: [0x84,0x1a,0x64,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[12:15], s0
+// GFX10: encoding: [0x86,0x00,0x64,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[96:99], s0
+// GFX10: encoding: [0xb0,0x00,0x64,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], s101
+// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xca]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], vcc_lo
+// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xd4]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], vcc_hi
+// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xd6]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], m0
+// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xf8]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], 0x0
+// GFX10: encoding: [0x84,0x00,0x64,0xf4,0x00,0x00,0x00,0xfa]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], s0 glc
+// GFX10: encoding: [0x84,0x00,0x65,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], s0 dlc
+// GFX10: encoding: [0x84,0x40,0x64,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], s0 glc dlc
+// GFX10: encoding: [0x84,0x40,0x65,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], 0x1234 glc dlc
+// GFX10: encoding: [0x84,0x40,0x65,0xf4,0x34,0x12,0x00,0xfa]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], s0
+// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[8:11], s[8:11], s0
+// GFX10: encoding: [0x04,0x02,0x68,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[96:99], s[8:11], s0
+// GFX10: encoding: [0x04,0x18,0x68,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[12:15], s0
+// GFX10: encoding: [0x06,0x01,0x68,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[96:99], s0
+// GFX10: encoding: [0x30,0x01,0x68,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], s101
+// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xca]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], vcc_lo
+// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xd4]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], vcc_hi
+// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xd6]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], m0
+// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xf8]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], 0x0
+// GFX10: encoding: [0x04,0x01,0x68,0xf4,0x00,0x00,0x00,0xfa]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], s0 glc
+// GFX10: encoding: [0x04,0x01,0x69,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], s0 dlc
+// GFX10: encoding: [0x04,0x41,0x68,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], s0 glc dlc
+// GFX10: encoding: [0x04,0x41,0x69,0xf4,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], 0x1234 glc dlc
+// GFX10: encoding: [0x04,0x41,0x69,0xf4,0x34,0x12,0x00,0xfa]
+
+s_memrealtime s[10:11]
+// GFX10: encoding: [0x80,0x02,0x94,0xf4,0x00,0x00,0x00,0x00]
+
+s_memrealtime s[12:13]
+// GFX10: encoding: [0x00,0x03,0x94,0xf4,0x00,0x00,0x00,0x00]
+
+s_memrealtime s[100:101]
+// GFX10: encoding: [0x00,0x19,0x94,0xf4,0x00,0x00,0x00,0x00]
+
+s_memrealtime vcc
+// GFX10: encoding: [0x80,0x1a,0x94,0xf4,0x00,0x00,0x00,0x00]
+
+s_memtime s[10:11]
+// GFX10: encoding: [0x80,0x02,0x90,0xf4,0x00,0x00,0x00,0x00]
+
+s_memtime s[12:13]
+// GFX10: encoding: [0x00,0x03,0x90,0xf4,0x00,0x00,0x00,0x00]
+
+s_memtime s[100:101]
+// GFX10: encoding: [0x00,0x19,0x90,0xf4,0x00,0x00,0x00,0x00]
+
+s_memtime vcc
+// GFX10: encoding: [0x80,0x1a,0x90,0xf4,0x00,0x00,0x00,0x00]
+
+s_dcache_inv
+// GFX10: encoding: [0x00,0x00,0x80,0xf4,0x00,0x00,0x00,0x00]
+
+s_gl1_inv
+// GFX10: encoding: [0x00,0x00,0x7c,0xf4,0x00,0x00,0x00,0x00]
+
+s_dcache_wb
+// GFX10: encoding: [0x00,0x00,0x84,0xf4,0x00,0x00,0x00,0x00]
+
+s_get_waveid_in_workgroup s0
+// GFX10: encoding: [0x00,0x00,0xa8,0xf4,0x00,0x00,0x00,0x00]
+
+s_get_waveid_in_workgroup vcc_lo
+// GFX10: encoding: [0x80,0x1a,0xa8,0xf4,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x14,0xf4,0x00,0x00,0x00,0xca]
+
+s_scratch_load_dword s5, s[2:3], s0 glc
+// GFX10: encoding: [0x41,0x01,0x15,0xf4,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[100:101], s[2:3], s0
+// GFX10: encoding: [0x01,0x19,0x18,0xf4,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], 0x1 glc
+// GFX10: encoding: [0x81,0x02,0x19,0xf4,0x01,0x00,0x00,0xfa]
+
+s_scratch_load_dwordx4 s[20:23], s[4:5], s0
+// GFX10: encoding: [0x02,0x05,0x1c,0xf4,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s101, s[4:5], s0
+// GFX10: encoding: [0x42,0x19,0x54,0xf4,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], 0x123 glc
+// GFX10: encoding: [0x42,0x00,0x55,0xf4,0x23,0x01,0x00,0xfa]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], s101 glc
+// GFX10: encoding: [0x82,0x00,0x59,0xf4,0x00,0x00,0x00,0xca]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], s0 glc
+// GFX10: encoding: [0x02,0x01,0x5d,0xf4,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x7, s[4:5], s2
+// GFX10: s_atc_probe 7, s[4:5], s2 ; encoding: [0xc2,0x01,0x98,0xf4,0x00,0x00,0x00,0x04]
+
+s_atc_probe 0x7, s[4:5], 100
+// GFX10: s_atc_probe 7, s[4:5], 0x64 ; encoding: [0xc2,0x01,0x98,0xf4,0x64,0x00,0x00,0xfa]
+
+s_atc_probe_buffer 0x7, s[8:11], s2
+// GFX10: s_atc_probe_buffer 7, s[8:11], s2 ; encoding: [0xc4,0x01,0x9c,0xf4,0x00,0x00,0x00,0x04]
+
+s_atc_probe_buffer 0x7, s[8:11], 100
+// GFX10: s_atc_probe_buffer 7, s[8:11], 0x64 ; encoding: [0xc4,0x01,0x9c,0xf4,0x64,0x00,0x00,0xfa]
+
+s_dcache_discard s[2:3], s2
+// GFX10: s_dcache_discard s[2:3], s2 ; encoding: [0x01,0x00,0xa0,0xf4,0x00,0x00,0x00,0x04]
+
+s_dcache_discard s[2:3], 100
+// GFX10: s_dcache_discard s[2:3], 0x64 ; encoding: [0x01,0x00,0xa0,0xf4,0x64,0x00,0x00,0xfa]
+
+s_dcache_discard_x2 s[2:3], s2
+// GFX10: s_dcache_discard_x2 s[2:3], s2 ; encoding: [0x01,0x00,0xa4,0xf4,0x00,0x00,0x00,0x04]
+
+s_dcache_discard_x2 s[2:3], 100
+// GFX10: s_dcache_discard_x2 s[2:3], 0x64 ; encoding: [0x01,0x00,0xa4,0xf4,0x64,0x00,0x00,0xfa]
+
+s_atomic_add s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x08,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_add s5, s[2:3], 0x64
+// GFX10: encoding: [0x41,0x01,0x08,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_add_x2 s[10:11], s[2:3], s101
+// GFX10: encoding: [0x81,0x02,0x88,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_and s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x20,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_and_x2 s[10:11], s[2:3], 0x64
+// GFX10: encoding: [0x81,0x02,0xa0,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_cmpswap s[10:11], s[2:3], s101
+// GFX10: encoding: [0x81,0x02,0x04,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_cmpswap s[10:11], s[2:3], 0x64
+// GFX10: encoding: [0x81,0x02,0x04,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], s101
+// GFX10: encoding: [0x01,0x05,0x84,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], 0x64
+// GFX10: encoding: [0x01,0x05,0x84,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_dec_x2 s[10:11], s[2:3], s101
+// GFX10: encoding: [0x81,0x02,0xb0,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_inc_x2 s[10:11], s[2:3], s101
+// GFX10: encoding: [0x81,0x02,0xac,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_or s5, s[2:3], 0x64
+// GFX10: encoding: [0x41,0x01,0x24,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_smax s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x18,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_smin s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x10,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_sub s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x0c,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_swap s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x00,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_umax_x2 s[10:11], s[2:3], s101
+// GFX10: encoding: [0x81,0x02,0x9c,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_umin s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x14,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_xor s5, s[2:3], s101
+// GFX10: encoding: [0x41,0x01,0x28,0xf6,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_add s5, s[4:7], s101
+// GFX10: encoding: [0x42,0x01,0x08,0xf5,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_add s5, s[4:7], 0x64
+// GFX10: encoding: [0x42,0x01,0x08,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], s2
+// GFX10: encoding: [0x82,0x02,0x88,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_and s101, s[4:7], s2
+// GFX10: encoding: [0x42,0x19,0x20,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_and_x2 s[10:11], s[8:11], s2
+// GFX10: encoding: [0x84,0x02,0xa0,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], s2
+// GFX10: encoding: [0x82,0x02,0x04,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], 0x64
+// GFX10: encoding: [0x82,0x02,0x04,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], s101
+// GFX10: encoding: [0x02,0x05,0x84,0xf5,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], 0x64
+// GFX10: encoding: [0x02,0x05,0x84,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_dec s5, s[4:7], s2
+// GFX10: encoding: [0x42,0x01,0x30,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_inc s101, s[4:7], s2
+// GFX10: encoding: [0x42,0x19,0x2c,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], 0x64
+// GFX10: encoding: [0x82,0x02,0xac,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_or s5, s[8:11], s2
+// GFX10: encoding: [0x44,0x01,0x24,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_or_x2 s[10:11], s[96:99], s2
+// GFX10: encoding: [0xb0,0x02,0xa4,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_smax s5, s[4:7], s101
+// GFX10: encoding: [0x42,0x01,0x18,0xf5,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_smax_x2 s[100:101], s[4:7], s2
+// GFX10: encoding: [0x02,0x19,0x98,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_smin s5, s[4:7], 0x64
+// GFX10: encoding: [0x42,0x01,0x10,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_smin_x2 s[12:13], s[4:7], s2
+// GFX10: encoding: [0x02,0x03,0x90,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], s2
+// GFX10: encoding: [0x82,0x02,0x8c,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_swap s5, s[4:7], s2
+// GFX10: encoding: [0x42,0x01,0x00,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_umax s5, s[4:7], s2
+// GFX10: encoding: [0x42,0x01,0x1c,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_umin s5, s[4:7], s2
+// GFX10: encoding: [0x42,0x01,0x14,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_xor s5, s[4:7], s2
+// GFX10: encoding: [0x42,0x01,0x28,0xf5,0x00,0x00,0x00,0x04]
+
+s_atomic_add s5, s[2:3], s101 glc
+// GFX10: encoding: [0x41,0x01,0x09,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_add s5, s[2:3], 0x64 glc
+// GFX10: encoding: [0x41,0x01,0x09,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_add_x2 s[10:11], s[2:3], s101 glc
+// GFX10: encoding: [0x81,0x02,0x89,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_and s5, s[2:3], s101 glc
+// GFX10: encoding: [0x41,0x01,0x21,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_and_x2 s[10:11], s[2:3], 0x64 glc
+// GFX10: encoding: [0x81,0x02,0xa1,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_cmpswap s[10:11], s[2:3], s101 glc
+// GFX10: encoding: [0x81,0x02,0x05,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_cmpswap s[10:11], s[2:3], 0x64 glc
+// GFX10: encoding: [0x81,0x02,0x05,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], s101 glc
+// GFX10: encoding: [0x01,0x05,0x85,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], 0x64 glc
+// GFX10: encoding: [0x01,0x05,0x85,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_dec_x2 s[10:11], s[2:3], s101 glc
+// GFX10: encoding: [0x81,0x02,0xb1,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_inc_x2 s[10:11], s[2:3], s101 glc
+// GFX10: encoding: [0x81,0x02,0xad,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_or s5, s[2:3], 0x64 glc
+// GFX10: encoding: [0x41,0x01,0x25,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_smax s5, s[2:3], s101 glc
+// GFX10: encoding: [0x41,0x01,0x19,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_smin s5, s[2:3], s101 glc
+// GFX10: encoding: [0x41,0x01,0x11,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_sub s5, s[2:3], s101 glc
+// GFX10: encoding: [0x41,0x01,0x0d,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_swap s5, s[2:3], s101 glc
+// GFX10: encoding: [0x41,0x01,0x01,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_umax_x2 s[10:11], s[2:3], s101 glc
+// GFX10: encoding: [0x81,0x02,0x9d,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_umin s5, s[2:3], s101 glc
+// GFX10: encoding: [0x41,0x01,0x15,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_xor s5, s[2:3], s101 glc
+// GFX10: encoding: [0x41,0x01,0x29,0xf6,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_add s5, s[4:7], s101 glc
+// GFX10: encoding: [0x42,0x01,0x09,0xf5,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_add s5, s[4:7], 0x64 glc
+// GFX10: encoding: [0x42,0x01,0x09,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], s2 glc
+// GFX10: encoding: [0x82,0x02,0x89,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_and s101, s[4:7], s2 glc
+// GFX10: encoding: [0x42,0x19,0x21,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_and_x2 s[10:11], s[8:11], s2 glc
+// GFX10: encoding: [0x84,0x02,0xa1,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], s2 glc
+// GFX10: encoding: [0x82,0x02,0x05,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], 0x64 glc
+// GFX10: encoding: [0x82,0x02,0x05,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], s101 glc
+// GFX10: encoding: [0x02,0x05,0x85,0xf5,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], 0x64 glc
+// GFX10: encoding: [0x02,0x05,0x85,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_dec s5, s[4:7], s2 glc
+// GFX10: encoding: [0x42,0x01,0x31,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_inc s101, s[4:7], s2 glc
+// GFX10: encoding: [0x42,0x19,0x2d,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], 0x64 glc
+// GFX10: encoding: [0x82,0x02,0xad,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_or s5, s[8:11], s2 glc
+// GFX10: encoding: [0x44,0x01,0x25,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_or_x2 s[10:11], s[96:99], s2 glc
+// GFX10: encoding: [0xb0,0x02,0xa5,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_smax s5, s[4:7], s101 glc
+// GFX10: encoding: [0x42,0x01,0x19,0xf5,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_smax_x2 s[100:101], s[4:7], s2 glc
+// GFX10: encoding: [0x02,0x19,0x99,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_smin s5, s[4:7], 0x64 glc
+// GFX10: encoding: [0x42,0x01,0x11,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_smin_x2 s[12:13], s[4:7], s2 glc
+// GFX10: encoding: [0x02,0x03,0x91,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], s2 glc
+// GFX10: encoding: [0x82,0x02,0x8d,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_swap s5, s[4:7], s2 glc
+// GFX10: encoding: [0x42,0x01,0x01,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_umax s5, s[4:7], s2 glc
+// GFX10: encoding: [0x42,0x01,0x1d,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_umin s5, s[4:7], s2 glc
+// GFX10: encoding: [0x42,0x01,0x15,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_xor s5, s[4:7], s2 glc
+// GFX10: encoding: [0x42,0x01,0x29,0xf5,0x00,0x00,0x00,0x04]
+
+s_atomic_add s5, s[2:3], s101 dlc
+// GFX10: encoding: [0x41,0x41,0x08,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_add s5, s[2:3], 0x64 dlc
+// GFX10: encoding: [0x41,0x41,0x08,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_add_x2 s[10:11], s[2:3], s101 dlc
+// GFX10: encoding: [0x81,0x42,0x88,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_and s5, s[2:3], s101 dlc
+// GFX10: encoding: [0x41,0x41,0x20,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_and_x2 s[10:11], s[2:3], 0x64 dlc
+// GFX10: encoding: [0x81,0x42,0xa0,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_cmpswap s[10:11], s[2:3], s101 dlc
+// GFX10: encoding: [0x81,0x42,0x04,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_cmpswap s[10:11], s[2:3], 0x64 dlc
+// GFX10: encoding: [0x81,0x42,0x04,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], s101 dlc
+// GFX10: encoding: [0x01,0x45,0x84,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], 0x64 dlc
+// GFX10: encoding: [0x01,0x45,0x84,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_dec_x2 s[10:11], s[2:3], s101 dlc
+// GFX10: encoding: [0x81,0x42,0xb0,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_inc_x2 s[10:11], s[2:3], s101 dlc
+// GFX10: encoding: [0x81,0x42,0xac,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_or s5, s[2:3], 0x64 dlc
+// GFX10: encoding: [0x41,0x41,0x24,0xf6,0x64,0x00,0x00,0xfa]
+
+s_atomic_smax s5, s[2:3], s101 dlc
+// GFX10: encoding: [0x41,0x41,0x18,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_smin s5, s[2:3], s101 dlc
+// GFX10: encoding: [0x41,0x41,0x10,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_sub s5, s[2:3], s101 dlc
+// GFX10: encoding: [0x41,0x41,0x0c,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_swap s5, s[2:3], s101 dlc
+// GFX10: encoding: [0x41,0x41,0x00,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_umax_x2 s[10:11], s[2:3], s101 dlc
+// GFX10: encoding: [0x81,0x42,0x9c,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_umin s5, s[2:3], s101 dlc
+// GFX10: encoding: [0x41,0x41,0x14,0xf6,0x00,0x00,0x00,0xca]
+
+s_atomic_xor s5, s[2:3], s101 dlc
+// GFX10: encoding: [0x41,0x41,0x28,0xf6,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_add s5, s[4:7], s101 dlc
+// GFX10: encoding: [0x42,0x41,0x08,0xf5,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_add s5, s[4:7], 0x64 dlc
+// GFX10: encoding: [0x42,0x41,0x08,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], s2 dlc
+// GFX10: encoding: [0x82,0x42,0x88,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_and s101, s[4:7], s2 dlc
+// GFX10: encoding: [0x42,0x59,0x20,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_and_x2 s[10:11], s[8:11], s2 dlc
+// GFX10: encoding: [0x84,0x42,0xa0,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], s2 dlc
+// GFX10: encoding: [0x82,0x42,0x04,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], 0x64 dlc
+// GFX10: encoding: [0x82,0x42,0x04,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], s101 dlc
+// GFX10: encoding: [0x02,0x45,0x84,0xf5,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], 0x64 dlc
+// GFX10: encoding: [0x02,0x45,0x84,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_dec s5, s[4:7], s2 dlc
+// GFX10: encoding: [0x42,0x41,0x30,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_inc s101, s[4:7], s2 dlc
+// GFX10: encoding: [0x42,0x59,0x2c,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], 0x64 dlc
+// GFX10: encoding: [0x82,0x42,0xac,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_or s5, s[8:11], s2 dlc
+// GFX10: encoding: [0x44,0x41,0x24,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_or_x2 s[10:11], s[96:99], s2 dlc
+// GFX10: encoding: [0xb0,0x42,0xa4,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_smax s5, s[4:7], s101 dlc
+// GFX10: encoding: [0x42,0x41,0x18,0xf5,0x00,0x00,0x00,0xca]
+
+s_buffer_atomic_smax_x2 s[100:101], s[4:7], s2 dlc
+// GFX10: encoding: [0x02,0x59,0x98,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_smin s5, s[4:7], 0x64 dlc
+// GFX10: encoding: [0x42,0x41,0x10,0xf5,0x64,0x00,0x00,0xfa]
+
+s_buffer_atomic_smin_x2 s[12:13], s[4:7], s2 dlc
+// GFX10: encoding: [0x02,0x43,0x90,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], s2 dlc
+// GFX10: encoding: [0x82,0x42,0x8c,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_swap s5, s[4:7], s2 dlc
+// GFX10: encoding: [0x42,0x41,0x00,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_umax s5, s[4:7], s2 dlc
+// GFX10: encoding: [0x42,0x41,0x1c,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_umin s5, s[4:7], s2 dlc
+// GFX10: encoding: [0x42,0x41,0x14,0xf5,0x00,0x00,0x00,0x04]
+
+s_buffer_atomic_xor s5, s[4:7], s2 dlc
+// GFX10: encoding: [0x42,0x41,0x28,0xf5,0x00,0x00,0x00,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_sop.s b/llvm/test/MC/AMDGPU/gfx10_asm_sop.s
new file mode 100644
index 0000000000000..5401aa49e3b4d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_sop.s
@@ -0,0 +1,10072 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+
+//===----------------------------------------------------------------------===//
+// ENC_SOP1.
+//===----------------------------------------------------------------------===//
+
+s_mov_b32 s0, s1
+// GFX10: encoding: [0x01,0x03,0x80,0xbe]
+
+s_mov_b32 s105, s104
+// GFX10: encoding: [0x68,0x03,0xe9,0xbe]
+
+s_mov_b32 s0, s104
+// GFX10: encoding: [0x68,0x03,0x80,0xbe]
+
+s_mov_b32 s105, s1
+// GFX10: encoding: [0x01,0x03,0xe9,0xbe]
+
+s_mov_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x03,0xfe,0xbe]
+
+s_mov_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x03,0xff,0xbe]
+
+s_mov_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x03,0xea,0xbe]
+
+s_mov_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x03,0xeb,0xbe]
+
+s_mov_b32 m0, s1
+// GFX10: encoding: [0x01,0x03,0xfc,0xbe]
+
+s_mov_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x03,0x80,0xbe]
+
+s_mov_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x03,0x80,0xbe]
+
+s_mov_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x03,0x80,0xbe]
+
+s_mov_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x03,0x80,0xbe]
+
+s_mov_b32 s0, m0
+// GFX10: encoding: [0x7c,0x03,0x80,0xbe]
+
+s_mov_b32 s0, 0
+// GFX10: encoding: [0x80,0x03,0x80,0xbe]
+
+s_mov_b32 s0, -1
+// GFX10: encoding: [0xc1,0x03,0x80,0xbe]
+
+s_mov_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x03,0x80,0xbe]
+
+s_mov_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x03,0x80,0xbe]
+
+s_mov_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x03,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_mov_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x03,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_mov_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x04,0x80,0xbe]
+
+s_mov_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x04,0xe8,0xbe]
+
+s_mov_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x04,0x80,0xbe]
+
+s_mov_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x04,0xe8,0xbe]
+
+s_mov_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x04,0xfe,0xbe]
+
+s_mov_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x04,0xea,0xbe]
+
+s_mov_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x04,0x80,0xbe]
+
+s_mov_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x04,0x80,0xbe]
+
+s_mov_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x04,0x80,0xbe]
+
+s_mov_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x04,0x80,0xbe]
+
+s_mov_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x04,0x80,0xbe]
+
+s_mov_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x04,0x80,0xbe]
+
+s_mov_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x04,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_mov_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x04,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_cmov_b32 s0, s1
+// GFX10: encoding: [0x01,0x05,0x80,0xbe]
+
+s_cmov_b32 s105, s104
+// GFX10: encoding: [0x68,0x05,0xe9,0xbe]
+
+s_cmov_b32 s0, s104
+// GFX10: encoding: [0x68,0x05,0x80,0xbe]
+
+s_cmov_b32 s105, s1
+// GFX10: encoding: [0x01,0x05,0xe9,0xbe]
+
+s_cmov_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x05,0xfe,0xbe]
+
+s_cmov_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x05,0xff,0xbe]
+
+s_cmov_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x05,0xea,0xbe]
+
+s_cmov_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x05,0xeb,0xbe]
+
+s_cmov_b32 m0, s1
+// GFX10: encoding: [0x01,0x05,0xfc,0xbe]
+
+s_cmov_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x05,0x80,0xbe]
+
+s_cmov_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x05,0x80,0xbe]
+
+s_cmov_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x05,0x80,0xbe]
+
+s_cmov_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x05,0x80,0xbe]
+
+s_cmov_b32 s0, m0
+// GFX10: encoding: [0x7c,0x05,0x80,0xbe]
+
+s_cmov_b32 s0, 0
+// GFX10: encoding: [0x80,0x05,0x80,0xbe]
+
+s_cmov_b32 s0, -1
+// GFX10: encoding: [0xc1,0x05,0x80,0xbe]
+
+s_cmov_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x05,0x80,0xbe]
+
+s_cmov_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x05,0x80,0xbe]
+
+s_cmov_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x05,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cmov_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x05,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_cmov_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x06,0x80,0xbe]
+
+s_cmov_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x06,0xe8,0xbe]
+
+s_cmov_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x06,0x80,0xbe]
+
+s_cmov_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x06,0xe8,0xbe]
+
+s_cmov_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x06,0xfe,0xbe]
+
+s_cmov_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x06,0xea,0xbe]
+
+s_cmov_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x06,0x80,0xbe]
+
+s_cmov_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x06,0x80,0xbe]
+
+s_cmov_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x06,0x80,0xbe]
+
+s_cmov_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x06,0x80,0xbe]
+
+s_cmov_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x06,0x80,0xbe]
+
+s_cmov_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x06,0x80,0xbe]
+
+s_cmov_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x06,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cmov_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x06,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_not_b32 s0, s1
+// GFX10: encoding: [0x01,0x07,0x80,0xbe]
+
+s_not_b32 s105, s104
+// GFX10: encoding: [0x68,0x07,0xe9,0xbe]
+
+s_not_b32 s0, s104
+// GFX10: encoding: [0x68,0x07,0x80,0xbe]
+
+s_not_b32 s105, s1
+// GFX10: encoding: [0x01,0x07,0xe9,0xbe]
+
+s_not_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x07,0xfe,0xbe]
+
+s_not_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x07,0xff,0xbe]
+
+s_not_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x07,0xea,0xbe]
+
+s_not_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x07,0xeb,0xbe]
+
+s_not_b32 m0, s1
+// GFX10: encoding: [0x01,0x07,0xfc,0xbe]
+
+s_not_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x07,0x80,0xbe]
+
+s_not_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x07,0x80,0xbe]
+
+s_not_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x07,0x80,0xbe]
+
+s_not_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x07,0x80,0xbe]
+
+s_not_b32 s0, m0
+// GFX10: encoding: [0x7c,0x07,0x80,0xbe]
+
+s_not_b32 s0, 0
+// GFX10: encoding: [0x80,0x07,0x80,0xbe]
+
+s_not_b32 s0, -1
+// GFX10: encoding: [0xc1,0x07,0x80,0xbe]
+
+s_not_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x07,0x80,0xbe]
+
+s_not_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x07,0x80,0xbe]
+
+s_not_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x07,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_not_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x07,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_not_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x08,0x80,0xbe]
+
+s_not_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x08,0xe8,0xbe]
+
+s_not_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x08,0x80,0xbe]
+
+s_not_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x08,0xe8,0xbe]
+
+s_not_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x08,0xfe,0xbe]
+
+s_not_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x08,0xea,0xbe]
+
+s_not_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x08,0x80,0xbe]
+
+s_not_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x08,0x80,0xbe]
+
+s_not_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x08,0x80,0xbe]
+
+s_not_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x08,0x80,0xbe]
+
+s_not_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x08,0x80,0xbe]
+
+s_not_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x08,0x80,0xbe]
+
+s_not_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x08,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_not_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x08,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_wqm_b32 s0, s1
+// GFX10: encoding: [0x01,0x09,0x80,0xbe]
+
+s_wqm_b32 s105, s104
+// GFX10: encoding: [0x68,0x09,0xe9,0xbe]
+
+s_wqm_b32 s0, s104
+// GFX10: encoding: [0x68,0x09,0x80,0xbe]
+
+s_wqm_b32 s105, s1
+// GFX10: encoding: [0x01,0x09,0xe9,0xbe]
+
+s_wqm_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x09,0xfe,0xbe]
+
+s_wqm_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x09,0xff,0xbe]
+
+s_wqm_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x09,0xea,0xbe]
+
+s_wqm_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x09,0xeb,0xbe]
+
+s_wqm_b32 m0, s1
+// GFX10: encoding: [0x01,0x09,0xfc,0xbe]
+
+s_wqm_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x09,0x80,0xbe]
+
+s_wqm_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x09,0x80,0xbe]
+
+s_wqm_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x09,0x80,0xbe]
+
+s_wqm_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x09,0x80,0xbe]
+
+s_wqm_b32 s0, m0
+// GFX10: encoding: [0x7c,0x09,0x80,0xbe]
+
+s_wqm_b32 s0, 0
+// GFX10: encoding: [0x80,0x09,0x80,0xbe]
+
+s_wqm_b32 s0, -1
+// GFX10: encoding: [0xc1,0x09,0x80,0xbe]
+
+s_wqm_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x09,0x80,0xbe]
+
+s_wqm_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x09,0x80,0xbe]
+
+s_wqm_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x09,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_wqm_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x09,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_wqm_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x0a,0x80,0xbe]
+
+s_wqm_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x0a,0xe8,0xbe]
+
+s_wqm_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x0a,0x80,0xbe]
+
+s_wqm_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x0a,0xe8,0xbe]
+
+s_wqm_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x0a,0xfe,0xbe]
+
+s_wqm_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x0a,0xea,0xbe]
+
+s_wqm_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x0a,0x80,0xbe]
+
+s_wqm_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x0a,0x80,0xbe]
+
+s_wqm_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x0a,0x80,0xbe]
+
+s_wqm_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x0a,0x80,0xbe]
+
+s_wqm_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x0a,0x80,0xbe]
+
+s_wqm_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x0a,0x80,0xbe]
+
+s_wqm_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x0a,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_wqm_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x0a,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_brev_b32 s0, s1
+// GFX10: encoding: [0x01,0x0b,0x80,0xbe]
+
+s_brev_b32 s105, s104
+// GFX10: encoding: [0x68,0x0b,0xe9,0xbe]
+
+s_brev_b32 s0, s104
+// GFX10: encoding: [0x68,0x0b,0x80,0xbe]
+
+s_brev_b32 s105, s1
+// GFX10: encoding: [0x01,0x0b,0xe9,0xbe]
+
+s_brev_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x0b,0xfe,0xbe]
+
+s_brev_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x0b,0xff,0xbe]
+
+s_brev_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x0b,0xea,0xbe]
+
+s_brev_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x0b,0xeb,0xbe]
+
+s_brev_b32 m0, s1
+// GFX10: encoding: [0x01,0x0b,0xfc,0xbe]
+
+s_brev_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x0b,0x80,0xbe]
+
+s_brev_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x0b,0x80,0xbe]
+
+s_brev_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x0b,0x80,0xbe]
+
+s_brev_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x0b,0x80,0xbe]
+
+s_brev_b32 s0, m0
+// GFX10: encoding: [0x7c,0x0b,0x80,0xbe]
+
+s_brev_b32 s0, 0
+// GFX10: encoding: [0x80,0x0b,0x80,0xbe]
+
+s_brev_b32 s0, -1
+// GFX10: encoding: [0xc1,0x0b,0x80,0xbe]
+
+s_brev_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x0b,0x80,0xbe]
+
+s_brev_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x0b,0x80,0xbe]
+
+s_brev_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x0b,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_brev_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x0b,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_brev_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x0c,0x80,0xbe]
+
+s_brev_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x0c,0xe8,0xbe]
+
+s_brev_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x0c,0x80,0xbe]
+
+s_brev_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x0c,0xe8,0xbe]
+
+s_brev_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x0c,0xfe,0xbe]
+
+s_brev_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x0c,0xea,0xbe]
+
+s_brev_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x0c,0x80,0xbe]
+
+s_brev_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x0c,0x80,0xbe]
+
+s_brev_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x0c,0x80,0xbe]
+
+s_brev_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x0c,0x80,0xbe]
+
+s_brev_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x0c,0x80,0xbe]
+
+s_brev_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x0c,0x80,0xbe]
+
+s_brev_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x0c,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_brev_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x0c,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt0_i32_b32 s0, s1
+// GFX10: encoding: [0x01,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s105, s104
+// GFX10: encoding: [0x68,0x0d,0xe9,0xbe]
+
+s_bcnt0_i32_b32 s0, s104
+// GFX10: encoding: [0x68,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s105, s1
+// GFX10: encoding: [0x01,0x0d,0xe9,0xbe]
+
+s_bcnt0_i32_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x0d,0xfe,0xbe]
+
+s_bcnt0_i32_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x0d,0xff,0xbe]
+
+s_bcnt0_i32_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x0d,0xea,0xbe]
+
+s_bcnt0_i32_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x0d,0xeb,0xbe]
+
+s_bcnt0_i32_b32 m0, s1
+// GFX10: encoding: [0x01,0x0d,0xfc,0xbe]
+
+s_bcnt0_i32_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s0, m0
+// GFX10: encoding: [0x7c,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s0, 0
+// GFX10: encoding: [0x80,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s0, -1
+// GFX10: encoding: [0xc1,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x0d,0x80,0xbe]
+
+s_bcnt0_i32_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x0d,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt0_i32_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x0d,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt0_i32_b64 s0, s[2:3]
+// GFX10: encoding: [0x02,0x0e,0x80,0xbe]
+
+s_bcnt0_i32_b64 s105, s[102:103]
+// GFX10: encoding: [0x66,0x0e,0xe9,0xbe]
+
+s_bcnt0_i32_b64 s0, s[102:103]
+// GFX10: encoding: [0x66,0x0e,0x80,0xbe]
+
+s_bcnt0_i32_b64 s105, s[2:3]
+// GFX10: encoding: [0x02,0x0e,0xe9,0xbe]
+
+s_bcnt0_i32_b64 exec_lo, s[2:3]
+// GFX10: encoding: [0x02,0x0e,0xfe,0xbe]
+
+s_bcnt0_i32_b64 exec_hi, s[2:3]
+// GFX10: encoding: [0x02,0x0e,0xff,0xbe]
+
+s_bcnt0_i32_b64 vcc_lo, s[2:3]
+// GFX10: encoding: [0x02,0x0e,0xea,0xbe]
+
+s_bcnt0_i32_b64 vcc_hi, s[2:3]
+// GFX10: encoding: [0x02,0x0e,0xeb,0xbe]
+
+s_bcnt0_i32_b64 m0, s[2:3]
+// GFX10: encoding: [0x02,0x0e,0xfc,0xbe]
+
+s_bcnt0_i32_b64 s0, exec
+// GFX10: encoding: [0x7e,0x0e,0x80,0xbe]
+
+s_bcnt0_i32_b64 s0, vcc
+// GFX10: encoding: [0x6a,0x0e,0x80,0xbe]
+
+s_bcnt0_i32_b64 s0, 0
+// GFX10: encoding: [0x80,0x0e,0x80,0xbe]
+
+s_bcnt0_i32_b64 s0, -1
+// GFX10: encoding: [0xc1,0x0e,0x80,0xbe]
+
+s_bcnt0_i32_b64 s0, 0.5
+// GFX10: encoding: [0xf0,0x0e,0x80,0xbe]
+
+s_bcnt0_i32_b64 s0, -4.0
+// GFX10: encoding: [0xf7,0x0e,0x80,0xbe]
+
+s_bcnt0_i32_b64 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x0e,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt0_i32_b64 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x0e,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt1_i32_b32 s0, s1
+// GFX10: encoding: [0x01,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s105, s104
+// GFX10: encoding: [0x68,0x0f,0xe9,0xbe]
+
+s_bcnt1_i32_b32 s0, s104
+// GFX10: encoding: [0x68,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s105, s1
+// GFX10: encoding: [0x01,0x0f,0xe9,0xbe]
+
+s_bcnt1_i32_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x0f,0xfe,0xbe]
+
+s_bcnt1_i32_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x0f,0xff,0xbe]
+
+s_bcnt1_i32_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x0f,0xea,0xbe]
+
+s_bcnt1_i32_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x0f,0xeb,0xbe]
+
+s_bcnt1_i32_b32 m0, s1
+// GFX10: encoding: [0x01,0x0f,0xfc,0xbe]
+
+s_bcnt1_i32_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s0, m0
+// GFX10: encoding: [0x7c,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s0, 0
+// GFX10: encoding: [0x80,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s0, -1
+// GFX10: encoding: [0xc1,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x0f,0x80,0xbe]
+
+s_bcnt1_i32_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x0f,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt1_i32_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x0f,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt1_i32_b64 s0, s[2:3]
+// GFX10: encoding: [0x02,0x10,0x80,0xbe]
+
+s_bcnt1_i32_b64 s105, s[102:103]
+// GFX10: encoding: [0x66,0x10,0xe9,0xbe]
+
+s_bcnt1_i32_b64 s0, s[102:103]
+// GFX10: encoding: [0x66,0x10,0x80,0xbe]
+
+s_bcnt1_i32_b64 s105, s[2:3]
+// GFX10: encoding: [0x02,0x10,0xe9,0xbe]
+
+s_bcnt1_i32_b64 exec_lo, s[2:3]
+// GFX10: encoding: [0x02,0x10,0xfe,0xbe]
+
+s_bcnt1_i32_b64 exec_hi, s[2:3]
+// GFX10: encoding: [0x02,0x10,0xff,0xbe]
+
+s_bcnt1_i32_b64 vcc_lo, s[2:3]
+// GFX10: encoding: [0x02,0x10,0xea,0xbe]
+
+s_bcnt1_i32_b64 vcc_hi, s[2:3]
+// GFX10: encoding: [0x02,0x10,0xeb,0xbe]
+
+s_bcnt1_i32_b64 m0, s[2:3]
+// GFX10: encoding: [0x02,0x10,0xfc,0xbe]
+
+s_bcnt1_i32_b64 s0, exec
+// GFX10: encoding: [0x7e,0x10,0x80,0xbe]
+
+s_bcnt1_i32_b64 s0, vcc
+// GFX10: encoding: [0x6a,0x10,0x80,0xbe]
+
+s_bcnt1_i32_b64 s0, 0
+// GFX10: encoding: [0x80,0x10,0x80,0xbe]
+
+s_bcnt1_i32_b64 s0, -1
+// GFX10: encoding: [0xc1,0x10,0x80,0xbe]
+
+s_bcnt1_i32_b64 s0, 0.5
+// GFX10: encoding: [0xf0,0x10,0x80,0xbe]
+
+s_bcnt1_i32_b64 s0, -4.0
+// GFX10: encoding: [0xf7,0x10,0x80,0xbe]
+
+s_bcnt1_i32_b64 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x10,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt1_i32_b64 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x10,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff0_i32_b32 s0, s1
+// GFX10: encoding: [0x01,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s105, s104
+// GFX10: encoding: [0x68,0x11,0xe9,0xbe]
+
+s_ff0_i32_b32 s0, s104
+// GFX10: encoding: [0x68,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s105, s1
+// GFX10: encoding: [0x01,0x11,0xe9,0xbe]
+
+s_ff0_i32_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x11,0xfe,0xbe]
+
+s_ff0_i32_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x11,0xff,0xbe]
+
+s_ff0_i32_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x11,0xea,0xbe]
+
+s_ff0_i32_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x11,0xeb,0xbe]
+
+s_ff0_i32_b32 m0, s1
+// GFX10: encoding: [0x01,0x11,0xfc,0xbe]
+
+s_ff0_i32_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s0, m0
+// GFX10: encoding: [0x7c,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s0, 0
+// GFX10: encoding: [0x80,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s0, -1
+// GFX10: encoding: [0xc1,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x11,0x80,0xbe]
+
+s_ff0_i32_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x11,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff0_i32_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x11,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff0_i32_b64 s0, s[2:3]
+// GFX10: encoding: [0x02,0x12,0x80,0xbe]
+
+s_ff0_i32_b64 s105, s[102:103]
+// GFX10: encoding: [0x66,0x12,0xe9,0xbe]
+
+s_ff0_i32_b64 s0, s[102:103]
+// GFX10: encoding: [0x66,0x12,0x80,0xbe]
+
+s_ff0_i32_b64 s105, s[2:3]
+// GFX10: encoding: [0x02,0x12,0xe9,0xbe]
+
+s_ff0_i32_b64 exec_lo, s[2:3]
+// GFX10: encoding: [0x02,0x12,0xfe,0xbe]
+
+s_ff0_i32_b64 exec_hi, s[2:3]
+// GFX10: encoding: [0x02,0x12,0xff,0xbe]
+
+s_ff0_i32_b64 vcc_lo, s[2:3]
+// GFX10: encoding: [0x02,0x12,0xea,0xbe]
+
+s_ff0_i32_b64 vcc_hi, s[2:3]
+// GFX10: encoding: [0x02,0x12,0xeb,0xbe]
+
+s_ff0_i32_b64 m0, s[2:3]
+// GFX10: encoding: [0x02,0x12,0xfc,0xbe]
+
+s_ff0_i32_b64 s0, exec
+// GFX10: encoding: [0x7e,0x12,0x80,0xbe]
+
+s_ff0_i32_b64 s0, vcc
+// GFX10: encoding: [0x6a,0x12,0x80,0xbe]
+
+s_ff0_i32_b64 s0, 0
+// GFX10: encoding: [0x80,0x12,0x80,0xbe]
+
+s_ff0_i32_b64 s0, -1
+// GFX10: encoding: [0xc1,0x12,0x80,0xbe]
+
+s_ff0_i32_b64 s0, 0.5
+// GFX10: encoding: [0xf0,0x12,0x80,0xbe]
+
+s_ff0_i32_b64 s0, -4.0
+// GFX10: encoding: [0xf7,0x12,0x80,0xbe]
+
+s_ff0_i32_b64 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x12,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff0_i32_b64 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x12,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff1_i32_b32 s0, s1
+// GFX10: encoding: [0x01,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s105, s104
+// GFX10: encoding: [0x68,0x13,0xe9,0xbe]
+
+s_ff1_i32_b32 s0, s104
+// GFX10: encoding: [0x68,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s105, s1
+// GFX10: encoding: [0x01,0x13,0xe9,0xbe]
+
+s_ff1_i32_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x13,0xfe,0xbe]
+
+s_ff1_i32_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x13,0xff,0xbe]
+
+s_ff1_i32_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x13,0xea,0xbe]
+
+s_ff1_i32_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x13,0xeb,0xbe]
+
+s_ff1_i32_b32 m0, s1
+// GFX10: encoding: [0x01,0x13,0xfc,0xbe]
+
+s_ff1_i32_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s0, m0
+// GFX10: encoding: [0x7c,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s0, 0
+// GFX10: encoding: [0x80,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s0, -1
+// GFX10: encoding: [0xc1,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x13,0x80,0xbe]
+
+s_ff1_i32_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x13,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff1_i32_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x13,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff1_i32_b64 s0, s[2:3]
+// GFX10: encoding: [0x02,0x14,0x80,0xbe]
+
+s_ff1_i32_b64 s105, s[102:103]
+// GFX10: encoding: [0x66,0x14,0xe9,0xbe]
+
+s_ff1_i32_b64 s0, s[102:103]
+// GFX10: encoding: [0x66,0x14,0x80,0xbe]
+
+s_ff1_i32_b64 s105, s[2:3]
+// GFX10: encoding: [0x02,0x14,0xe9,0xbe]
+
+s_ff1_i32_b64 exec_lo, s[2:3]
+// GFX10: encoding: [0x02,0x14,0xfe,0xbe]
+
+s_ff1_i32_b64 exec_hi, s[2:3]
+// GFX10: encoding: [0x02,0x14,0xff,0xbe]
+
+s_ff1_i32_b64 vcc_lo, s[2:3]
+// GFX10: encoding: [0x02,0x14,0xea,0xbe]
+
+s_ff1_i32_b64 vcc_hi, s[2:3]
+// GFX10: encoding: [0x02,0x14,0xeb,0xbe]
+
+s_ff1_i32_b64 m0, s[2:3]
+// GFX10: encoding: [0x02,0x14,0xfc,0xbe]
+
+s_ff1_i32_b64 s0, exec
+// GFX10: encoding: [0x7e,0x14,0x80,0xbe]
+
+s_ff1_i32_b64 s0, vcc
+// GFX10: encoding: [0x6a,0x14,0x80,0xbe]
+
+s_ff1_i32_b64 s0, 0
+// GFX10: encoding: [0x80,0x14,0x80,0xbe]
+
+s_ff1_i32_b64 s0, -1
+// GFX10: encoding: [0xc1,0x14,0x80,0xbe]
+
+s_ff1_i32_b64 s0, 0.5
+// GFX10: encoding: [0xf0,0x14,0x80,0xbe]
+
+s_ff1_i32_b64 s0, -4.0
+// GFX10: encoding: [0xf7,0x14,0x80,0xbe]
+
+s_ff1_i32_b64 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x14,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff1_i32_b64 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x14,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_b32 s0, s1
+// GFX10: encoding: [0x01,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s105, s104
+// GFX10: encoding: [0x68,0x15,0xe9,0xbe]
+
+s_flbit_i32_b32 s0, s104
+// GFX10: encoding: [0x68,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s105, s1
+// GFX10: encoding: [0x01,0x15,0xe9,0xbe]
+
+s_flbit_i32_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x15,0xfe,0xbe]
+
+s_flbit_i32_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x15,0xff,0xbe]
+
+s_flbit_i32_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x15,0xea,0xbe]
+
+s_flbit_i32_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x15,0xeb,0xbe]
+
+s_flbit_i32_b32 m0, s1
+// GFX10: encoding: [0x01,0x15,0xfc,0xbe]
+
+s_flbit_i32_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s0, m0
+// GFX10: encoding: [0x7c,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s0, 0
+// GFX10: encoding: [0x80,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s0, -1
+// GFX10: encoding: [0xc1,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x15,0x80,0xbe]
+
+s_flbit_i32_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x15,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x15,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_b64 s0, s[2:3]
+// GFX10: encoding: [0x02,0x16,0x80,0xbe]
+
+s_flbit_i32_b64 s105, s[102:103]
+// GFX10: encoding: [0x66,0x16,0xe9,0xbe]
+
+s_flbit_i32_b64 s0, s[102:103]
+// GFX10: encoding: [0x66,0x16,0x80,0xbe]
+
+s_flbit_i32_b64 s105, s[2:3]
+// GFX10: encoding: [0x02,0x16,0xe9,0xbe]
+
+s_flbit_i32_b64 exec_lo, s[2:3]
+// GFX10: encoding: [0x02,0x16,0xfe,0xbe]
+
+s_flbit_i32_b64 exec_hi, s[2:3]
+// GFX10: encoding: [0x02,0x16,0xff,0xbe]
+
+s_flbit_i32_b64 vcc_lo, s[2:3]
+// GFX10: encoding: [0x02,0x16,0xea,0xbe]
+
+s_flbit_i32_b64 vcc_hi, s[2:3]
+// GFX10: encoding: [0x02,0x16,0xeb,0xbe]
+
+s_flbit_i32_b64 m0, s[2:3]
+// GFX10: encoding: [0x02,0x16,0xfc,0xbe]
+
+s_flbit_i32_b64 s0, exec
+// GFX10: encoding: [0x7e,0x16,0x80,0xbe]
+
+s_flbit_i32_b64 s0, vcc
+// GFX10: encoding: [0x6a,0x16,0x80,0xbe]
+
+s_flbit_i32_b64 s0, 0
+// GFX10: encoding: [0x80,0x16,0x80,0xbe]
+
+s_flbit_i32_b64 s0, -1
+// GFX10: encoding: [0xc1,0x16,0x80,0xbe]
+
+s_flbit_i32_b64 s0, 0.5
+// GFX10: encoding: [0xf0,0x16,0x80,0xbe]
+
+s_flbit_i32_b64 s0, -4.0
+// GFX10: encoding: [0xf7,0x16,0x80,0xbe]
+
+s_flbit_i32_b64 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x16,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_b64 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x16,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32 s0, s1
+// GFX10: encoding: [0x01,0x17,0x80,0xbe]
+
+s_flbit_i32 s105, s104
+// GFX10: encoding: [0x68,0x17,0xe9,0xbe]
+
+s_flbit_i32 s0, s104
+// GFX10: encoding: [0x68,0x17,0x80,0xbe]
+
+s_flbit_i32 s105, s1
+// GFX10: encoding: [0x01,0x17,0xe9,0xbe]
+
+s_flbit_i32 exec_lo, s1
+// GFX10: encoding: [0x01,0x17,0xfe,0xbe]
+
+s_flbit_i32 exec_hi, s1
+// GFX10: encoding: [0x01,0x17,0xff,0xbe]
+
+s_flbit_i32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x17,0xea,0xbe]
+
+s_flbit_i32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x17,0xeb,0xbe]
+
+s_flbit_i32 m0, s1
+// GFX10: encoding: [0x01,0x17,0xfc,0xbe]
+
+s_flbit_i32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x17,0x80,0xbe]
+
+s_flbit_i32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x17,0x80,0xbe]
+
+s_flbit_i32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x17,0x80,0xbe]
+
+s_flbit_i32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x17,0x80,0xbe]
+
+s_flbit_i32 s0, m0
+// GFX10: encoding: [0x7c,0x17,0x80,0xbe]
+
+s_flbit_i32 s0, 0
+// GFX10: encoding: [0x80,0x17,0x80,0xbe]
+
+s_flbit_i32 s0, -1
+// GFX10: encoding: [0xc1,0x17,0x80,0xbe]
+
+s_flbit_i32 s0, 0.5
+// GFX10: encoding: [0xf0,0x17,0x80,0xbe]
+
+s_flbit_i32 s0, -4.0
+// GFX10: encoding: [0xf7,0x17,0x80,0xbe]
+
+s_flbit_i32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x17,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x17,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_i64 s0, s[2:3]
+// GFX10: encoding: [0x02,0x18,0x80,0xbe]
+
+s_flbit_i32_i64 s105, s[102:103]
+// GFX10: encoding: [0x66,0x18,0xe9,0xbe]
+
+s_flbit_i32_i64 s0, s[102:103]
+// GFX10: encoding: [0x66,0x18,0x80,0xbe]
+
+s_flbit_i32_i64 s105, s[2:3]
+// GFX10: encoding: [0x02,0x18,0xe9,0xbe]
+
+s_flbit_i32_i64 exec_lo, s[2:3]
+// GFX10: encoding: [0x02,0x18,0xfe,0xbe]
+
+s_flbit_i32_i64 exec_hi, s[2:3]
+// GFX10: encoding: [0x02,0x18,0xff,0xbe]
+
+s_flbit_i32_i64 vcc_lo, s[2:3]
+// GFX10: encoding: [0x02,0x18,0xea,0xbe]
+
+s_flbit_i32_i64 vcc_hi, s[2:3]
+// GFX10: encoding: [0x02,0x18,0xeb,0xbe]
+
+s_flbit_i32_i64 m0, s[2:3]
+// GFX10: encoding: [0x02,0x18,0xfc,0xbe]
+
+s_flbit_i32_i64 s0, exec
+// GFX10: encoding: [0x7e,0x18,0x80,0xbe]
+
+s_flbit_i32_i64 s0, vcc
+// GFX10: encoding: [0x6a,0x18,0x80,0xbe]
+
+s_flbit_i32_i64 s0, 0
+// GFX10: encoding: [0x80,0x18,0x80,0xbe]
+
+s_flbit_i32_i64 s0, -1
+// GFX10: encoding: [0xc1,0x18,0x80,0xbe]
+
+s_flbit_i32_i64 s0, 0.5
+// GFX10: encoding: [0xf0,0x18,0x80,0xbe]
+
+s_flbit_i32_i64 s0, -4.0
+// GFX10: encoding: [0xf7,0x18,0x80,0xbe]
+
+s_flbit_i32_i64 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x18,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_i64 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x18,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_sext_i32_i8 s0, s1
+// GFX10: encoding: [0x01,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s105, s104
+// GFX10: encoding: [0x68,0x19,0xe9,0xbe]
+
+s_sext_i32_i8 s0, s104
+// GFX10: encoding: [0x68,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s105, s1
+// GFX10: encoding: [0x01,0x19,0xe9,0xbe]
+
+s_sext_i32_i8 exec_lo, s1
+// GFX10: encoding: [0x01,0x19,0xfe,0xbe]
+
+s_sext_i32_i8 exec_hi, s1
+// GFX10: encoding: [0x01,0x19,0xff,0xbe]
+
+s_sext_i32_i8 vcc_lo, s1
+// GFX10: encoding: [0x01,0x19,0xea,0xbe]
+
+s_sext_i32_i8 vcc_hi, s1
+// GFX10: encoding: [0x01,0x19,0xeb,0xbe]
+
+s_sext_i32_i8 m0, s1
+// GFX10: encoding: [0x01,0x19,0xfc,0xbe]
+
+s_sext_i32_i8 s0, exec_lo
+// GFX10: encoding: [0x7e,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s0, exec_hi
+// GFX10: encoding: [0x7f,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s0, m0
+// GFX10: encoding: [0x7c,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s0, 0
+// GFX10: encoding: [0x80,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s0, -1
+// GFX10: encoding: [0xc1,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s0, 0.5
+// GFX10: encoding: [0xf0,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s0, -4.0
+// GFX10: encoding: [0xf7,0x19,0x80,0xbe]
+
+s_sext_i32_i8 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x19,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_sext_i32_i8 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x19,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_sext_i32_i16 s0, s1
+// GFX10: encoding: [0x01,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s105, s104
+// GFX10: encoding: [0x68,0x1a,0xe9,0xbe]
+
+s_sext_i32_i16 s0, s104
+// GFX10: encoding: [0x68,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s105, s1
+// GFX10: encoding: [0x01,0x1a,0xe9,0xbe]
+
+s_sext_i32_i16 exec_lo, s1
+// GFX10: encoding: [0x01,0x1a,0xfe,0xbe]
+
+s_sext_i32_i16 exec_hi, s1
+// GFX10: encoding: [0x01,0x1a,0xff,0xbe]
+
+s_sext_i32_i16 vcc_lo, s1
+// GFX10: encoding: [0x01,0x1a,0xea,0xbe]
+
+s_sext_i32_i16 vcc_hi, s1
+// GFX10: encoding: [0x01,0x1a,0xeb,0xbe]
+
+s_sext_i32_i16 m0, s1
+// GFX10: encoding: [0x01,0x1a,0xfc,0xbe]
+
+s_sext_i32_i16 s0, exec_lo
+// GFX10: encoding: [0x7e,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s0, exec_hi
+// GFX10: encoding: [0x7f,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s0, m0
+// GFX10: encoding: [0x7c,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s0, 0
+// GFX10: encoding: [0x80,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s0, -1
+// GFX10: encoding: [0xc1,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s0, 0.5
+// GFX10: encoding: [0xf0,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s0, -4.0
+// GFX10: encoding: [0xf7,0x1a,0x80,0xbe]
+
+s_sext_i32_i16 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x1a,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_sext_i32_i16 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x1a,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset0_b32 s0, s1
+// GFX10: encoding: [0x01,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s105, s104
+// GFX10: encoding: [0x68,0x1b,0xe9,0xbe]
+
+s_bitset0_b32 s0, s104
+// GFX10: encoding: [0x68,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s105, s1
+// GFX10: encoding: [0x01,0x1b,0xe9,0xbe]
+
+s_bitset0_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x1b,0xfe,0xbe]
+
+s_bitset0_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x1b,0xff,0xbe]
+
+s_bitset0_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x1b,0xea,0xbe]
+
+s_bitset0_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x1b,0xeb,0xbe]
+
+s_bitset0_b32 m0, s1
+// GFX10: encoding: [0x01,0x1b,0xfc,0xbe]
+
+s_bitset0_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s0, m0
+// GFX10: encoding: [0x7c,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s0, 0
+// GFX10: encoding: [0x80,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s0, -1
+// GFX10: encoding: [0xc1,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x1b,0x80,0xbe]
+
+s_bitset0_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x1b,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset0_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x1b,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset0_b64 s[0:1], s2
+// GFX10: encoding: [0x02,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[104:105], s102
+// GFX10: encoding: [0x66,0x1c,0xe8,0xbe]
+
+s_bitset0_b64 s[0:1], s102
+// GFX10: encoding: [0x66,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[104:105], s2
+// GFX10: encoding: [0x02,0x1c,0xe8,0xbe]
+
+s_bitset0_b64 exec, s2
+// GFX10: encoding: [0x02,0x1c,0xfe,0xbe]
+
+s_bitset0_b64 vcc, s2
+// GFX10: encoding: [0x02,0x1c,0xea,0xbe]
+
+s_bitset0_b64 s[0:1], exec_lo
+// GFX10: encoding: [0x7e,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[0:1], exec_hi
+// GFX10: encoding: [0x7f,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[0:1], vcc_lo
+// GFX10: encoding: [0x6a,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[0:1], vcc_hi
+// GFX10: encoding: [0x6b,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[0:1], m0
+// GFX10: encoding: [0x7c,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x1c,0x80,0xbe]
+
+s_bitset0_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x1c,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset0_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x1c,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset1_b32 s0, s1
+// GFX10: encoding: [0x01,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s105, s104
+// GFX10: encoding: [0x68,0x1d,0xe9,0xbe]
+
+s_bitset1_b32 s0, s104
+// GFX10: encoding: [0x68,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s105, s1
+// GFX10: encoding: [0x01,0x1d,0xe9,0xbe]
+
+s_bitset1_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x1d,0xfe,0xbe]
+
+s_bitset1_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x1d,0xff,0xbe]
+
+s_bitset1_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x1d,0xea,0xbe]
+
+s_bitset1_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x1d,0xeb,0xbe]
+
+s_bitset1_b32 m0, s1
+// GFX10: encoding: [0x01,0x1d,0xfc,0xbe]
+
+s_bitset1_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s0, m0
+// GFX10: encoding: [0x7c,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s0, 0
+// GFX10: encoding: [0x80,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s0, -1
+// GFX10: encoding: [0xc1,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x1d,0x80,0xbe]
+
+s_bitset1_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x1d,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset1_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x1d,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset1_b64 s[0:1], s2
+// GFX10: encoding: [0x02,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[104:105], s102
+// GFX10: encoding: [0x66,0x1e,0xe8,0xbe]
+
+s_bitset1_b64 s[0:1], s102
+// GFX10: encoding: [0x66,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[104:105], s2
+// GFX10: encoding: [0x02,0x1e,0xe8,0xbe]
+
+s_bitset1_b64 exec, s2
+// GFX10: encoding: [0x02,0x1e,0xfe,0xbe]
+
+s_bitset1_b64 vcc, s2
+// GFX10: encoding: [0x02,0x1e,0xea,0xbe]
+
+s_bitset1_b64 s[0:1], exec_lo
+// GFX10: encoding: [0x7e,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[0:1], exec_hi
+// GFX10: encoding: [0x7f,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[0:1], vcc_lo
+// GFX10: encoding: [0x6a,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[0:1], vcc_hi
+// GFX10: encoding: [0x6b,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[0:1], m0
+// GFX10: encoding: [0x7c,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x1e,0x80,0xbe]
+
+s_bitset1_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x1e,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset1_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x1e,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_getpc_b64 s[0:1]
+// GFX10: encoding: [0x00,0x1f,0x80,0xbe]
+
+s_getpc_b64 s[104:105]
+// GFX10: encoding: [0x00,0x1f,0xe8,0xbe]
+
+s_getpc_b64 exec
+// GFX10: encoding: [0x00,0x1f,0xfe,0xbe]
+
+s_getpc_b64 vcc
+// GFX10: encoding: [0x00,0x1f,0xea,0xbe]
+
+s_setpc_b64 s[0:1]
+// GFX10: encoding: [0x00,0x20,0x80,0xbe]
+
+s_setpc_b64 s[104:105]
+// GFX10: encoding: [0x68,0x20,0x80,0xbe]
+
+s_setpc_b64 vcc
+// GFX10: encoding: [0x6a,0x20,0x80,0xbe]
+
+s_swappc_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x21,0x80,0xbe]
+
+s_swappc_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x21,0xe8,0xbe]
+
+s_swappc_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x21,0x80,0xbe]
+
+s_swappc_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x21,0xe8,0xbe]
+
+s_swappc_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x21,0xea,0xbe]
+
+s_swappc_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x21,0x80,0xbe]
+
+s_rfe_b64 s[0:1]
+// GFX10: encoding: [0x00,0x22,0x80,0xbe]
+
+s_rfe_b64 s[104:105]
+// GFX10: encoding: [0x68,0x22,0x80,0xbe]
+
+s_rfe_b64 vcc
+// GFX10: encoding: [0x6a,0x22,0x80,0xbe]
+
+s_and_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x24,0x80,0xbe]
+
+s_and_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x24,0xe8,0xbe]
+
+s_and_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x24,0x80,0xbe]
+
+s_and_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x24,0xe8,0xbe]
+
+s_and_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x24,0xfe,0xbe]
+
+s_and_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x24,0xea,0xbe]
+
+s_and_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x24,0x80,0xbe]
+
+s_and_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x24,0x80,0xbe]
+
+s_and_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x24,0x80,0xbe]
+
+s_and_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x24,0x80,0xbe]
+
+s_and_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x24,0x80,0xbe]
+
+s_and_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x24,0x80,0xbe]
+
+s_and_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x24,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_and_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x24,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_or_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x25,0x80,0xbe]
+
+s_or_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x25,0xe8,0xbe]
+
+s_or_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x25,0x80,0xbe]
+
+s_or_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x25,0xe8,0xbe]
+
+s_or_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x25,0xfe,0xbe]
+
+s_or_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x25,0xea,0xbe]
+
+s_or_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x25,0x80,0xbe]
+
+s_or_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x25,0x80,0xbe]
+
+s_or_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x25,0x80,0xbe]
+
+s_or_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x25,0x80,0xbe]
+
+s_or_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x25,0x80,0xbe]
+
+s_or_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x25,0x80,0xbe]
+
+s_or_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x25,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_or_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x25,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xor_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x26,0x80,0xbe]
+
+s_xor_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x26,0xe8,0xbe]
+
+s_xor_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x26,0x80,0xbe]
+
+s_xor_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x26,0xe8,0xbe]
+
+s_xor_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x26,0xfe,0xbe]
+
+s_xor_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x26,0xea,0xbe]
+
+s_xor_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x26,0x80,0xbe]
+
+s_xor_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x26,0x80,0xbe]
+
+s_xor_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x26,0x80,0xbe]
+
+s_xor_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x26,0x80,0xbe]
+
+s_xor_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x26,0x80,0xbe]
+
+s_xor_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x26,0x80,0xbe]
+
+s_xor_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x26,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xor_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x26,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn2_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x27,0x80,0xbe]
+
+s_andn2_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x27,0xe8,0xbe]
+
+s_andn2_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x27,0x80,0xbe]
+
+s_andn2_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x27,0xe8,0xbe]
+
+s_andn2_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x27,0xfe,0xbe]
+
+s_andn2_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x27,0xea,0xbe]
+
+s_andn2_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x27,0x80,0xbe]
+
+s_andn2_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x27,0x80,0xbe]
+
+s_andn2_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x27,0x80,0xbe]
+
+s_andn2_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x27,0x80,0xbe]
+
+s_andn2_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x27,0x80,0xbe]
+
+s_andn2_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x27,0x80,0xbe]
+
+s_andn2_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x27,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn2_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x27,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_orn2_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x28,0x80,0xbe]
+
+s_orn2_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x28,0xe8,0xbe]
+
+s_orn2_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x28,0x80,0xbe]
+
+s_orn2_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x28,0xe8,0xbe]
+
+s_orn2_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x28,0xfe,0xbe]
+
+s_orn2_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x28,0xea,0xbe]
+
+s_orn2_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x28,0x80,0xbe]
+
+s_orn2_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x28,0x80,0xbe]
+
+s_orn2_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x28,0x80,0xbe]
+
+s_orn2_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x28,0x80,0xbe]
+
+s_orn2_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x28,0x80,0xbe]
+
+s_orn2_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x28,0x80,0xbe]
+
+s_orn2_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x28,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_orn2_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x28,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nand_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x29,0x80,0xbe]
+
+s_nand_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x29,0xe8,0xbe]
+
+s_nand_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x29,0x80,0xbe]
+
+s_nand_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x29,0xe8,0xbe]
+
+s_nand_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x29,0xfe,0xbe]
+
+s_nand_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x29,0xea,0xbe]
+
+s_nand_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x29,0x80,0xbe]
+
+s_nand_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x29,0x80,0xbe]
+
+s_nand_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x29,0x80,0xbe]
+
+s_nand_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x29,0x80,0xbe]
+
+s_nand_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x29,0x80,0xbe]
+
+s_nand_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x29,0x80,0xbe]
+
+s_nand_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x29,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nand_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x29,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nor_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x2a,0x80,0xbe]
+
+s_nor_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x2a,0xe8,0xbe]
+
+s_nor_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x2a,0x80,0xbe]
+
+s_nor_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x2a,0xe8,0xbe]
+
+s_nor_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x2a,0xfe,0xbe]
+
+s_nor_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x2a,0xea,0xbe]
+
+s_nor_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x2a,0x80,0xbe]
+
+s_nor_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x2a,0x80,0xbe]
+
+s_nor_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x2a,0x80,0xbe]
+
+s_nor_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x2a,0x80,0xbe]
+
+s_nor_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x2a,0x80,0xbe]
+
+s_nor_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x2a,0x80,0xbe]
+
+s_nor_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x2a,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nor_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x2a,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xnor_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x2b,0x80,0xbe]
+
+s_xnor_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x2b,0xe8,0xbe]
+
+s_xnor_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x2b,0x80,0xbe]
+
+s_xnor_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x2b,0xe8,0xbe]
+
+s_xnor_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x2b,0xfe,0xbe]
+
+s_xnor_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x2b,0xea,0xbe]
+
+s_xnor_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x2b,0x80,0xbe]
+
+s_xnor_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x2b,0x80,0xbe]
+
+s_xnor_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x2b,0x80,0xbe]
+
+s_xnor_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x2b,0x80,0xbe]
+
+s_xnor_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x2b,0x80,0xbe]
+
+s_xnor_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x2b,0x80,0xbe]
+
+s_xnor_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x2b,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xnor_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x2b,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_quadmask_b32 s0, s1
+// GFX10: encoding: [0x01,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s105, s104
+// GFX10: encoding: [0x68,0x2c,0xe9,0xbe]
+
+s_quadmask_b32 s0, s104
+// GFX10: encoding: [0x68,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s105, s1
+// GFX10: encoding: [0x01,0x2c,0xe9,0xbe]
+
+s_quadmask_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x2c,0xfe,0xbe]
+
+s_quadmask_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x2c,0xff,0xbe]
+
+s_quadmask_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x2c,0xea,0xbe]
+
+s_quadmask_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x2c,0xeb,0xbe]
+
+s_quadmask_b32 m0, s1
+// GFX10: encoding: [0x01,0x2c,0xfc,0xbe]
+
+s_quadmask_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s0, m0
+// GFX10: encoding: [0x7c,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s0, 0
+// GFX10: encoding: [0x80,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s0, -1
+// GFX10: encoding: [0xc1,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x2c,0x80,0xbe]
+
+s_quadmask_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x2c,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_quadmask_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x2c,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_quadmask_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x2d,0x80,0xbe]
+
+s_quadmask_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x2d,0xe8,0xbe]
+
+s_quadmask_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x2d,0x80,0xbe]
+
+s_quadmask_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x2d,0xe8,0xbe]
+
+s_quadmask_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x2d,0xfe,0xbe]
+
+s_quadmask_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x2d,0xea,0xbe]
+
+s_quadmask_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x2d,0x80,0xbe]
+
+s_quadmask_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x2d,0x80,0xbe]
+
+s_quadmask_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x2d,0x80,0xbe]
+
+s_quadmask_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x2d,0x80,0xbe]
+
+s_quadmask_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x2d,0x80,0xbe]
+
+s_quadmask_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x2d,0x80,0xbe]
+
+s_quadmask_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x2d,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_quadmask_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x2d,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_movrels_b32 s0, s1
+// GFX10: encoding: [0x01,0x2e,0x80,0xbe]
+
+s_movrels_b32 s105, s104
+// GFX10: encoding: [0x68,0x2e,0xe9,0xbe]
+
+s_movrels_b32 s0, s104
+// GFX10: encoding: [0x68,0x2e,0x80,0xbe]
+
+s_movrels_b32 s105, s1
+// GFX10: encoding: [0x01,0x2e,0xe9,0xbe]
+
+s_movrels_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x2e,0xfe,0xbe]
+
+s_movrels_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x2e,0xff,0xbe]
+
+s_movrels_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x2e,0xea,0xbe]
+
+s_movrels_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x2e,0xeb,0xbe]
+
+s_movrels_b32 m0, s1
+// GFX10: encoding: [0x01,0x2e,0xfc,0xbe]
+
+s_movrels_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x2e,0x80,0xbe]
+
+s_movrels_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x2e,0x80,0xbe]
+
+s_movrels_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x2f,0x80,0xbe]
+
+s_movrels_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x2f,0xe8,0xbe]
+
+s_movrels_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x2f,0x80,0xbe]
+
+s_movrels_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x2f,0xe8,0xbe]
+
+s_movrels_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x2f,0xfe,0xbe]
+
+s_movrels_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x2f,0xea,0xbe]
+
+s_movrels_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x2f,0x80,0xbe]
+
+s_movreld_b32 s0, s1
+// GFX10: encoding: [0x01,0x30,0x80,0xbe]
+
+s_movreld_b32 s105, s104
+// GFX10: encoding: [0x68,0x30,0xe9,0xbe]
+
+s_movreld_b32 s0, s104
+// GFX10: encoding: [0x68,0x30,0x80,0xbe]
+
+s_movreld_b32 s105, s1
+// GFX10: encoding: [0x01,0x30,0xe9,0xbe]
+
+s_movreld_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x30,0xea,0xbe]
+
+s_movreld_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x30,0xeb,0xbe]
+
+s_movreld_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x30,0x80,0xbe]
+
+s_movreld_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x30,0x80,0xbe]
+
+s_movreld_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x30,0x80,0xbe]
+
+s_movreld_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x30,0x80,0xbe]
+
+s_movreld_b32 s0, m0
+// GFX10: encoding: [0x7c,0x30,0x80,0xbe]
+
+s_movreld_b32 s0, 0
+// GFX10: encoding: [0x80,0x30,0x80,0xbe]
+
+s_movreld_b32 s0, -1
+// GFX10: encoding: [0xc1,0x30,0x80,0xbe]
+
+s_movreld_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x30,0x80,0xbe]
+
+s_movreld_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x30,0x80,0xbe]
+
+s_movreld_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x30,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_movreld_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x30,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_movreld_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x31,0x80,0xbe]
+
+s_movreld_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x31,0xe8,0xbe]
+
+s_movreld_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x31,0x80,0xbe]
+
+s_movreld_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x31,0xe8,0xbe]
+
+s_movreld_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x31,0xea,0xbe]
+
+s_movreld_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x31,0x80,0xbe]
+
+s_movreld_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x31,0x80,0xbe]
+
+s_movreld_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x31,0x80,0xbe]
+
+s_movreld_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x31,0x80,0xbe]
+
+s_movreld_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x31,0x80,0xbe]
+
+s_movreld_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x31,0x80,0xbe]
+
+s_movreld_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x31,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_movreld_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x31,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_abs_i32 s0, s1
+// GFX10: encoding: [0x01,0x34,0x80,0xbe]
+
+s_abs_i32 s105, s104
+// GFX10: encoding: [0x68,0x34,0xe9,0xbe]
+
+s_abs_i32 s0, s104
+// GFX10: encoding: [0x68,0x34,0x80,0xbe]
+
+s_abs_i32 s105, s1
+// GFX10: encoding: [0x01,0x34,0xe9,0xbe]
+
+s_abs_i32 exec_lo, s1
+// GFX10: encoding: [0x01,0x34,0xfe,0xbe]
+
+s_abs_i32 exec_hi, s1
+// GFX10: encoding: [0x01,0x34,0xff,0xbe]
+
+s_abs_i32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x34,0xea,0xbe]
+
+s_abs_i32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x34,0xeb,0xbe]
+
+s_abs_i32 m0, s1
+// GFX10: encoding: [0x01,0x34,0xfc,0xbe]
+
+s_abs_i32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x34,0x80,0xbe]
+
+s_abs_i32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x34,0x80,0xbe]
+
+s_abs_i32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x34,0x80,0xbe]
+
+s_abs_i32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x34,0x80,0xbe]
+
+s_abs_i32 s0, m0
+// GFX10: encoding: [0x7c,0x34,0x80,0xbe]
+
+s_abs_i32 s0, 0
+// GFX10: encoding: [0x80,0x34,0x80,0xbe]
+
+s_abs_i32 s0, -1
+// GFX10: encoding: [0xc1,0x34,0x80,0xbe]
+
+s_abs_i32 s0, 0.5
+// GFX10: encoding: [0xf0,0x34,0x80,0xbe]
+
+s_abs_i32 s0, -4.0
+// GFX10: encoding: [0xf7,0x34,0x80,0xbe]
+
+s_abs_i32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x34,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_abs_i32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x34,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn1_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x37,0x80,0xbe]
+
+s_andn1_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x37,0xe8,0xbe]
+
+s_andn1_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x37,0x80,0xbe]
+
+s_andn1_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x37,0xe8,0xbe]
+
+s_andn1_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x37,0xfe,0xbe]
+
+s_andn1_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x37,0xea,0xbe]
+
+s_andn1_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x37,0x80,0xbe]
+
+s_andn1_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x37,0x80,0xbe]
+
+s_andn1_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x37,0x80,0xbe]
+
+s_andn1_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x37,0x80,0xbe]
+
+s_andn1_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x37,0x80,0xbe]
+
+s_andn1_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x37,0x80,0xbe]
+
+s_andn1_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x37,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn1_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x37,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_orn1_saveexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x38,0x80,0xbe]
+
+s_orn1_saveexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x38,0xe8,0xbe]
+
+s_orn1_saveexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x38,0x80,0xbe]
+
+s_orn1_saveexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x38,0xe8,0xbe]
+
+s_orn1_saveexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x38,0xfe,0xbe]
+
+s_orn1_saveexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x38,0xea,0xbe]
+
+s_orn1_saveexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x38,0x80,0xbe]
+
+s_orn1_saveexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x38,0x80,0xbe]
+
+s_orn1_saveexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x38,0x80,0xbe]
+
+s_orn1_saveexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x38,0x80,0xbe]
+
+s_orn1_saveexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x38,0x80,0xbe]
+
+s_orn1_saveexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x38,0x80,0xbe]
+
+s_orn1_saveexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x38,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_orn1_saveexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x38,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn1_wrexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x39,0x80,0xbe]
+
+s_andn1_wrexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x39,0xe8,0xbe]
+
+s_andn1_wrexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x39,0x80,0xbe]
+
+s_andn1_wrexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x39,0xe8,0xbe]
+
+s_andn1_wrexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x39,0xfe,0xbe]
+
+s_andn1_wrexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x39,0xea,0xbe]
+
+s_andn1_wrexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x39,0x80,0xbe]
+
+s_andn1_wrexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x39,0x80,0xbe]
+
+s_andn1_wrexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x39,0x80,0xbe]
+
+s_andn1_wrexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x39,0x80,0xbe]
+
+s_andn1_wrexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x39,0x80,0xbe]
+
+s_andn1_wrexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x39,0x80,0xbe]
+
+s_andn1_wrexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x39,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn1_wrexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x39,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn2_wrexec_b64 s[0:1], s[2:3]
+// GFX10: encoding: [0x02,0x3a,0x80,0xbe]
+
+s_andn2_wrexec_b64 s[104:105], s[102:103]
+// GFX10: encoding: [0x66,0x3a,0xe8,0xbe]
+
+s_andn2_wrexec_b64 s[0:1], s[102:103]
+// GFX10: encoding: [0x66,0x3a,0x80,0xbe]
+
+s_andn2_wrexec_b64 s[104:105], s[2:3]
+// GFX10: encoding: [0x02,0x3a,0xe8,0xbe]
+
+s_andn2_wrexec_b64 exec, s[2:3]
+// GFX10: encoding: [0x02,0x3a,0xfe,0xbe]
+
+s_andn2_wrexec_b64 vcc, s[2:3]
+// GFX10: encoding: [0x02,0x3a,0xea,0xbe]
+
+s_andn2_wrexec_b64 s[0:1], exec
+// GFX10: encoding: [0x7e,0x3a,0x80,0xbe]
+
+s_andn2_wrexec_b64 s[0:1], vcc
+// GFX10: encoding: [0x6a,0x3a,0x80,0xbe]
+
+s_andn2_wrexec_b64 s[0:1], 0
+// GFX10: encoding: [0x80,0x3a,0x80,0xbe]
+
+s_andn2_wrexec_b64 s[0:1], -1
+// GFX10: encoding: [0xc1,0x3a,0x80,0xbe]
+
+s_andn2_wrexec_b64 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x3a,0x80,0xbe]
+
+s_andn2_wrexec_b64 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x3a,0x80,0xbe]
+
+s_andn2_wrexec_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x3a,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn2_wrexec_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x3a,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitreplicate_b64_b32 s[0:1], s2
+// GFX10: encoding: [0x02,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[104:105], s102
+// GFX10: encoding: [0x66,0x3b,0xe8,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], s102
+// GFX10: encoding: [0x66,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[104:105], s2
+// GFX10: encoding: [0x02,0x3b,0xe8,0xbe]
+
+s_bitreplicate_b64_b32 exec, s2
+// GFX10: encoding: [0x02,0x3b,0xfe,0xbe]
+
+s_bitreplicate_b64_b32 vcc, s2
+// GFX10: encoding: [0x02,0x3b,0xea,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], exec_lo
+// GFX10: encoding: [0x7e,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], exec_hi
+// GFX10: encoding: [0x7f,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], vcc_lo
+// GFX10: encoding: [0x6a,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], vcc_hi
+// GFX10: encoding: [0x6b,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], m0
+// GFX10: encoding: [0x7c,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], 0
+// GFX10: encoding: [0x80,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], -1
+// GFX10: encoding: [0xc1,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], 0.5
+// GFX10: encoding: [0xf0,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], -4.0
+// GFX10: encoding: [0xf7,0x3b,0x80,0xbe]
+
+s_bitreplicate_b64_b32 s[0:1], 0x3f717273
+// GFX10: encoding: [0xff,0x3b,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitreplicate_b64_b32 s[0:1], 0xaf123456
+// GFX10: encoding: [0xff,0x3b,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_and_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x3c,0xe9,0xbe]
+
+s_and_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x3c,0xe9,0xbe]
+
+s_and_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x3c,0xfe,0xbe]
+
+s_and_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x3c,0xff,0xbe]
+
+s_and_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x3c,0xea,0xbe]
+
+s_and_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x3c,0xeb,0xbe]
+
+s_and_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x3c,0xfc,0xbe]
+
+s_and_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x3c,0x80,0xbe]
+
+s_and_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x3c,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_and_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x3c,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_or_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x3d,0xe9,0xbe]
+
+s_or_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x3d,0xe9,0xbe]
+
+s_or_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x3d,0xfe,0xbe]
+
+s_or_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x3d,0xff,0xbe]
+
+s_or_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x3d,0xea,0xbe]
+
+s_or_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x3d,0xeb,0xbe]
+
+s_or_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x3d,0xfc,0xbe]
+
+s_or_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x3d,0x80,0xbe]
+
+s_or_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x3d,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_or_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x3d,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xor_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x3e,0xe9,0xbe]
+
+s_xor_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x3e,0xe9,0xbe]
+
+s_xor_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x3e,0xfe,0xbe]
+
+s_xor_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x3e,0xff,0xbe]
+
+s_xor_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x3e,0xea,0xbe]
+
+s_xor_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x3e,0xeb,0xbe]
+
+s_xor_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x3e,0xfc,0xbe]
+
+s_xor_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x3e,0x80,0xbe]
+
+s_xor_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x3e,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xor_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x3e,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn2_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x3f,0xe9,0xbe]
+
+s_andn2_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x3f,0xe9,0xbe]
+
+s_andn2_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x3f,0xfe,0xbe]
+
+s_andn2_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x3f,0xff,0xbe]
+
+s_andn2_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x3f,0xea,0xbe]
+
+s_andn2_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x3f,0xeb,0xbe]
+
+s_andn2_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x3f,0xfc,0xbe]
+
+s_andn2_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x3f,0x80,0xbe]
+
+s_andn2_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x3f,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn2_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x3f,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_orn2_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x40,0xe9,0xbe]
+
+s_orn2_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x40,0xe9,0xbe]
+
+s_orn2_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x40,0xfe,0xbe]
+
+s_orn2_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x40,0xff,0xbe]
+
+s_orn2_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x40,0xea,0xbe]
+
+s_orn2_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x40,0xeb,0xbe]
+
+s_orn2_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x40,0xfc,0xbe]
+
+s_orn2_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x40,0x80,0xbe]
+
+s_orn2_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x40,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_orn2_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x40,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nand_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x41,0xe9,0xbe]
+
+s_nand_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x41,0xe9,0xbe]
+
+s_nand_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x41,0xfe,0xbe]
+
+s_nand_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x41,0xff,0xbe]
+
+s_nand_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x41,0xea,0xbe]
+
+s_nand_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x41,0xeb,0xbe]
+
+s_nand_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x41,0xfc,0xbe]
+
+s_nand_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x41,0x80,0xbe]
+
+s_nand_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x41,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nand_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x41,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nor_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x42,0xe9,0xbe]
+
+s_nor_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x42,0xe9,0xbe]
+
+s_nor_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x42,0xfe,0xbe]
+
+s_nor_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x42,0xff,0xbe]
+
+s_nor_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x42,0xea,0xbe]
+
+s_nor_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x42,0xeb,0xbe]
+
+s_nor_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x42,0xfc,0xbe]
+
+s_nor_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x42,0x80,0xbe]
+
+s_nor_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x42,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nor_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x42,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xnor_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x43,0xe9,0xbe]
+
+s_xnor_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x43,0xe9,0xbe]
+
+s_xnor_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x43,0xfe,0xbe]
+
+s_xnor_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x43,0xff,0xbe]
+
+s_xnor_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x43,0xea,0xbe]
+
+s_xnor_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x43,0xeb,0xbe]
+
+s_xnor_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x43,0xfc,0xbe]
+
+s_xnor_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x43,0x80,0xbe]
+
+s_xnor_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x43,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xnor_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x43,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn1_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x44,0xe9,0xbe]
+
+s_andn1_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x44,0xe9,0xbe]
+
+s_andn1_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x44,0xfe,0xbe]
+
+s_andn1_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x44,0xff,0xbe]
+
+s_andn1_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x44,0xea,0xbe]
+
+s_andn1_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x44,0xeb,0xbe]
+
+s_andn1_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x44,0xfc,0xbe]
+
+s_andn1_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x44,0x80,0xbe]
+
+s_andn1_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x44,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn1_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x44,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_orn1_saveexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x45,0xe9,0xbe]
+
+s_orn1_saveexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x45,0xe9,0xbe]
+
+s_orn1_saveexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x45,0xfe,0xbe]
+
+s_orn1_saveexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x45,0xff,0xbe]
+
+s_orn1_saveexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x45,0xea,0xbe]
+
+s_orn1_saveexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x45,0xeb,0xbe]
+
+s_orn1_saveexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x45,0xfc,0xbe]
+
+s_orn1_saveexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x45,0x80,0xbe]
+
+s_orn1_saveexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x45,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_orn1_saveexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x45,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn1_wrexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x46,0xe9,0xbe]
+
+s_andn1_wrexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x46,0xe9,0xbe]
+
+s_andn1_wrexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x46,0xfe,0xbe]
+
+s_andn1_wrexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x46,0xff,0xbe]
+
+s_andn1_wrexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x46,0xea,0xbe]
+
+s_andn1_wrexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x46,0xeb,0xbe]
+
+s_andn1_wrexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x46,0xfc,0xbe]
+
+s_andn1_wrexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x46,0x80,0xbe]
+
+s_andn1_wrexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x46,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn1_wrexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x46,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn2_wrexec_b32 s0, s1
+// GFX10: encoding: [0x01,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s105, s104
+// GFX10: encoding: [0x68,0x47,0xe9,0xbe]
+
+s_andn2_wrexec_b32 s0, s104
+// GFX10: encoding: [0x68,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s105, s1
+// GFX10: encoding: [0x01,0x47,0xe9,0xbe]
+
+s_andn2_wrexec_b32 exec_lo, s1
+// GFX10: encoding: [0x01,0x47,0xfe,0xbe]
+
+s_andn2_wrexec_b32 exec_hi, s1
+// GFX10: encoding: [0x01,0x47,0xff,0xbe]
+
+s_andn2_wrexec_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x47,0xea,0xbe]
+
+s_andn2_wrexec_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x47,0xeb,0xbe]
+
+s_andn2_wrexec_b32 m0, s1
+// GFX10: encoding: [0x01,0x47,0xfc,0xbe]
+
+s_andn2_wrexec_b32 s0, exec_lo
+// GFX10: encoding: [0x7e,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s0, exec_hi
+// GFX10: encoding: [0x7f,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s0, m0
+// GFX10: encoding: [0x7c,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s0, 0
+// GFX10: encoding: [0x80,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s0, -1
+// GFX10: encoding: [0xc1,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s0, 0.5
+// GFX10: encoding: [0xf0,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s0, -4.0
+// GFX10: encoding: [0xf7,0x47,0x80,0xbe]
+
+s_andn2_wrexec_b32 s0, 0x3f717273
+// GFX10: encoding: [0xff,0x47,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn2_wrexec_b32 s0, 0xaf123456
+// GFX10: encoding: [0xff,0x47,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_movrelsd_2_b32 s0, s1
+// GFX10: encoding: [0x01,0x49,0x80,0xbe]
+
+s_movrelsd_2_b32 s105, s104
+// GFX10: encoding: [0x68,0x49,0xe9,0xbe]
+
+s_movrelsd_2_b32 s0, s104
+// GFX10: encoding: [0x68,0x49,0x80,0xbe]
+
+s_movrelsd_2_b32 s105, s1
+// GFX10: encoding: [0x01,0x49,0xe9,0xbe]
+
+s_movrelsd_2_b32 vcc_lo, s1
+// GFX10: encoding: [0x01,0x49,0xea,0xbe]
+
+s_movrelsd_2_b32 vcc_hi, s1
+// GFX10: encoding: [0x01,0x49,0xeb,0xbe]
+
+s_movrelsd_2_b32 s0, vcc_lo
+// GFX10: encoding: [0x6a,0x49,0x80,0xbe]
+
+s_movrelsd_2_b32 s0, vcc_hi
+// GFX10: encoding: [0x6b,0x49,0x80,0xbe]
+
+//===----------------------------------------------------------------------===//
+// ENC_SOP2.
+//===----------------------------------------------------------------------===//
+
+s_add_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x80]
+
+s_add_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x80]
+
+s_add_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x80]
+
+s_add_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x80]
+
+s_add_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x80]
+
+s_add_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x80]
+
+s_add_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x80]
+
+s_add_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x80]
+
+s_add_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x80]
+
+s_add_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x80]
+
+s_add_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x80]
+
+s_add_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x80]
+
+s_add_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x80]
+
+s_add_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x80]
+
+s_add_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x80]
+
+s_add_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x80]
+
+s_add_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x80]
+
+s_add_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x80]
+
+s_add_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x80]
+
+s_add_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x80]
+
+s_add_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x80]
+
+s_add_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x80]
+
+s_add_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x80,0x73,0x72,0x71,0x3f]
+
+s_add_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x80,0x56,0x34,0x12,0xaf]
+
+s_add_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x80]
+
+s_add_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x80]
+
+s_add_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x80]
+
+s_add_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x80]
+
+s_add_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x80]
+
+s_add_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x80]
+
+s_add_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x80]
+
+s_add_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x80]
+
+s_add_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x80]
+
+s_add_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x80,0x73,0x72,0x71,0x3f]
+
+s_add_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x80,0x56,0x34,0x12,0xaf]
+
+s_sub_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x80]
+
+s_sub_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x80]
+
+s_sub_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x80]
+
+s_sub_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x80]
+
+s_sub_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x80]
+
+s_sub_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x80]
+
+s_sub_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x80]
+
+s_sub_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x80]
+
+s_sub_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x80]
+
+s_sub_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x80]
+
+s_sub_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x80]
+
+s_sub_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x80]
+
+s_sub_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x80]
+
+s_sub_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x80]
+
+s_sub_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x80]
+
+s_sub_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x80]
+
+s_sub_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x80]
+
+s_sub_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x80]
+
+s_sub_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x80]
+
+s_sub_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x80]
+
+s_sub_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x80]
+
+s_sub_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x80]
+
+s_sub_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x80,0x73,0x72,0x71,0x3f]
+
+s_sub_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x80,0x56,0x34,0x12,0xaf]
+
+s_sub_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x80]
+
+s_sub_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x80]
+
+s_sub_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x80]
+
+s_sub_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x80]
+
+s_sub_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x80]
+
+s_sub_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x80]
+
+s_sub_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x80]
+
+s_sub_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x80]
+
+s_sub_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x80]
+
+s_sub_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x80,0x73,0x72,0x71,0x3f]
+
+s_sub_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x80,0x56,0x34,0x12,0xaf]
+
+s_add_i32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x81]
+
+s_add_i32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x81]
+
+s_add_i32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x81]
+
+s_add_i32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x81]
+
+s_add_i32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x81]
+
+s_add_i32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x81]
+
+s_add_i32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x81]
+
+s_add_i32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x81]
+
+s_add_i32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x81]
+
+s_add_i32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x81]
+
+s_add_i32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x81]
+
+s_add_i32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x81]
+
+s_add_i32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x81]
+
+s_add_i32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x81]
+
+s_add_i32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x81]
+
+s_add_i32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x81]
+
+s_add_i32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x81]
+
+s_add_i32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x81]
+
+s_add_i32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x81]
+
+s_add_i32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x81]
+
+s_add_i32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x81]
+
+s_add_i32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x81]
+
+s_add_i32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x81,0x73,0x72,0x71,0x3f]
+
+s_add_i32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x81,0x56,0x34,0x12,0xaf]
+
+s_add_i32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x81]
+
+s_add_i32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x81]
+
+s_add_i32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x81]
+
+s_add_i32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x81]
+
+s_add_i32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x81]
+
+s_add_i32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x81]
+
+s_add_i32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x81]
+
+s_add_i32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x81]
+
+s_add_i32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x81]
+
+s_add_i32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x81,0x73,0x72,0x71,0x3f]
+
+s_add_i32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x81,0x56,0x34,0x12,0xaf]
+
+s_sub_i32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x81]
+
+s_sub_i32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x81]
+
+s_sub_i32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x81]
+
+s_sub_i32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x81]
+
+s_sub_i32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x81]
+
+s_sub_i32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x81]
+
+s_sub_i32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x81]
+
+s_sub_i32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x81]
+
+s_sub_i32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x81]
+
+s_sub_i32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x81]
+
+s_sub_i32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x81]
+
+s_sub_i32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x81]
+
+s_sub_i32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x81]
+
+s_sub_i32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x81]
+
+s_sub_i32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x81]
+
+s_sub_i32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x81]
+
+s_sub_i32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x81]
+
+s_sub_i32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x81]
+
+s_sub_i32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x81]
+
+s_sub_i32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x81]
+
+s_sub_i32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x81]
+
+s_sub_i32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x81]
+
+s_sub_i32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x81,0x73,0x72,0x71,0x3f]
+
+s_sub_i32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x81,0x56,0x34,0x12,0xaf]
+
+s_sub_i32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x81]
+
+s_sub_i32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x81]
+
+s_sub_i32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x81]
+
+s_sub_i32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x81]
+
+s_sub_i32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x81]
+
+s_sub_i32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x81]
+
+s_sub_i32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x81]
+
+s_sub_i32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x81]
+
+s_sub_i32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x81]
+
+s_sub_i32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x81,0x73,0x72,0x71,0x3f]
+
+s_sub_i32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x81,0x56,0x34,0x12,0xaf]
+
+s_addc_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x82]
+
+s_addc_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x82]
+
+s_addc_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x82]
+
+s_addc_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x82]
+
+s_addc_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x82]
+
+s_addc_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x82]
+
+s_addc_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x82]
+
+s_addc_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x82]
+
+s_addc_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x82]
+
+s_addc_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x82]
+
+s_addc_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x82]
+
+s_addc_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x82]
+
+s_addc_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x82]
+
+s_addc_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x82]
+
+s_addc_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x82]
+
+s_addc_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x82]
+
+s_addc_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x82]
+
+s_addc_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x82]
+
+s_addc_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x82]
+
+s_addc_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x82]
+
+s_addc_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x82]
+
+s_addc_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x82]
+
+s_addc_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x82,0x73,0x72,0x71,0x3f]
+
+s_addc_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x82,0x56,0x34,0x12,0xaf]
+
+s_addc_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x82]
+
+s_addc_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x82]
+
+s_addc_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x82]
+
+s_addc_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x82]
+
+s_addc_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x82]
+
+s_addc_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x82]
+
+s_addc_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x82]
+
+s_addc_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x82]
+
+s_addc_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x82]
+
+s_addc_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x82,0x73,0x72,0x71,0x3f]
+
+s_addc_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x82,0x56,0x34,0x12,0xaf]
+
+s_subb_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x82]
+
+s_subb_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x82]
+
+s_subb_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x82]
+
+s_subb_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x82]
+
+s_subb_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x82]
+
+s_subb_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x82]
+
+s_subb_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x82]
+
+s_subb_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x82]
+
+s_subb_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x82]
+
+s_subb_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x82]
+
+s_subb_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x82]
+
+s_subb_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x82]
+
+s_subb_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x82]
+
+s_subb_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x82]
+
+s_subb_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x82]
+
+s_subb_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x82]
+
+s_subb_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x82]
+
+s_subb_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x82]
+
+s_subb_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x82]
+
+s_subb_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x82]
+
+s_subb_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x82]
+
+s_subb_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x82]
+
+s_subb_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x82,0x73,0x72,0x71,0x3f]
+
+s_subb_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x82,0x56,0x34,0x12,0xaf]
+
+s_subb_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x82]
+
+s_subb_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x82]
+
+s_subb_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x82]
+
+s_subb_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x82]
+
+s_subb_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x82]
+
+s_subb_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x82]
+
+s_subb_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x82]
+
+s_subb_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x82]
+
+s_subb_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x82]
+
+s_subb_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x82,0x73,0x72,0x71,0x3f]
+
+s_subb_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x82,0x56,0x34,0x12,0xaf]
+
+s_min_i32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x83]
+
+s_min_i32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x83]
+
+s_min_i32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x83]
+
+s_min_i32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x83]
+
+s_min_i32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x83]
+
+s_min_i32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x83]
+
+s_min_i32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x83]
+
+s_min_i32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x83]
+
+s_min_i32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x83]
+
+s_min_i32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x83]
+
+s_min_i32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x83]
+
+s_min_i32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x83]
+
+s_min_i32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x83]
+
+s_min_i32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x83]
+
+s_min_i32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x83]
+
+s_min_i32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x83]
+
+s_min_i32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x83]
+
+s_min_i32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x83]
+
+s_min_i32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x83]
+
+s_min_i32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x83]
+
+s_min_i32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x83]
+
+s_min_i32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x83]
+
+s_min_i32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_i32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_i32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x83]
+
+s_min_i32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x83]
+
+s_min_i32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x83]
+
+s_min_i32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x83]
+
+s_min_i32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x83]
+
+s_min_i32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x83]
+
+s_min_i32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x83]
+
+s_min_i32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x83]
+
+s_min_i32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x83]
+
+s_min_i32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_i32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x83]
+
+s_min_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x83]
+
+s_min_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x83]
+
+s_min_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x83]
+
+s_min_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x83]
+
+s_min_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x83]
+
+s_min_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x83]
+
+s_min_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x83]
+
+s_min_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x83]
+
+s_min_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x83]
+
+s_min_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x83]
+
+s_min_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x83]
+
+s_min_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x83]
+
+s_min_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x83]
+
+s_min_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x83]
+
+s_min_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x83]
+
+s_min_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x83]
+
+s_min_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x83]
+
+s_min_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x83]
+
+s_min_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x83]
+
+s_min_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x83]
+
+s_min_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x83]
+
+s_min_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x83]
+
+s_min_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x83]
+
+s_min_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x83]
+
+s_min_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x83]
+
+s_min_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x83]
+
+s_min_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x83]
+
+s_min_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x83]
+
+s_min_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x83]
+
+s_min_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x83]
+
+s_min_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x83,0x56,0x34,0x12,0xaf]
+
+s_max_i32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x84]
+
+s_max_i32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x84]
+
+s_max_i32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x84]
+
+s_max_i32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x84]
+
+s_max_i32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x84]
+
+s_max_i32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x84]
+
+s_max_i32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x84]
+
+s_max_i32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x84]
+
+s_max_i32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x84]
+
+s_max_i32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x84]
+
+s_max_i32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x84]
+
+s_max_i32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x84]
+
+s_max_i32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x84]
+
+s_max_i32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x84]
+
+s_max_i32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x84]
+
+s_max_i32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x84]
+
+s_max_i32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x84]
+
+s_max_i32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x84]
+
+s_max_i32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x84]
+
+s_max_i32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x84]
+
+s_max_i32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x84]
+
+s_max_i32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x84]
+
+s_max_i32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_i32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_i32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x84]
+
+s_max_i32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x84]
+
+s_max_i32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x84]
+
+s_max_i32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x84]
+
+s_max_i32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x84]
+
+s_max_i32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x84]
+
+s_max_i32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x84]
+
+s_max_i32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x84]
+
+s_max_i32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x84]
+
+s_max_i32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_i32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x84]
+
+s_max_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x84]
+
+s_max_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x84]
+
+s_max_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x84]
+
+s_max_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x84]
+
+s_max_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x84]
+
+s_max_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x84]
+
+s_max_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x84]
+
+s_max_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x84]
+
+s_max_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x84]
+
+s_max_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x84]
+
+s_max_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x84]
+
+s_max_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x84]
+
+s_max_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x84]
+
+s_max_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x84]
+
+s_max_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x84]
+
+s_max_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x84]
+
+s_max_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x84]
+
+s_max_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x84]
+
+s_max_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x84]
+
+s_max_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x84]
+
+s_max_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x84]
+
+s_max_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x84]
+
+s_max_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x84]
+
+s_max_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x84]
+
+s_max_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x84]
+
+s_max_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x84]
+
+s_max_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x84]
+
+s_max_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x84]
+
+s_max_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x84]
+
+s_max_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x84]
+
+s_max_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x84,0x56,0x34,0x12,0xaf]
+
+s_cselect_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x85]
+
+s_cselect_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x85]
+
+s_cselect_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x85]
+
+s_cselect_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x85]
+
+s_cselect_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x85]
+
+s_cselect_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x85]
+
+s_cselect_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x85]
+
+s_cselect_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x85]
+
+s_cselect_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x85]
+
+s_cselect_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x85]
+
+s_cselect_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x85]
+
+s_cselect_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x85]
+
+s_cselect_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x85]
+
+s_cselect_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x85]
+
+s_cselect_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x85]
+
+s_cselect_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x85]
+
+s_cselect_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x85]
+
+s_cselect_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x85]
+
+s_cselect_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x85]
+
+s_cselect_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x85]
+
+s_cselect_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x85]
+
+s_cselect_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x85]
+
+s_cselect_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x85]
+
+s_cselect_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x85]
+
+s_cselect_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x85]
+
+s_cselect_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x85]
+
+s_cselect_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x85]
+
+s_cselect_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x85]
+
+s_cselect_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x85]
+
+s_cselect_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x85]
+
+s_cselect_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x85]
+
+s_cselect_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b64 s[0:1], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0x80,0x85]
+
+s_cselect_b64 s[104:105], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0xe8,0x85]
+
+s_cselect_b64 s[0:1], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0x80,0x85]
+
+s_cselect_b64 s[104:105], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0xe8,0x85]
+
+s_cselect_b64 s[104:105], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0xe8,0x85]
+
+s_cselect_b64 s[104:105], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xe8,0x85]
+
+s_cselect_b64 s[0:1], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0x80,0x85]
+
+s_cselect_b64 s[0:1], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0x80,0x85]
+
+s_cselect_b64 exec, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xfe,0x85]
+
+s_cselect_b64 vcc, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xea,0x85]
+
+s_cselect_b64 s[0:1], exec, s[4:5]
+// GFX10: encoding: [0x7e,0x04,0x80,0x85]
+
+s_cselect_b64 s[0:1], vcc, s[4:5]
+// GFX10: encoding: [0x6a,0x04,0x80,0x85]
+
+s_cselect_b64 s[0:1], 0, s[4:5]
+// GFX10: encoding: [0x80,0x04,0x80,0x85]
+
+s_cselect_b64 s[0:1], -1, s[4:5]
+// GFX10: encoding: [0xc1,0x04,0x80,0x85]
+
+s_cselect_b64 s[0:1], 0.5, s[4:5]
+// GFX10: encoding: [0xf0,0x04,0x80,0x85]
+
+s_cselect_b64 s[0:1], -4.0, s[4:5]
+// GFX10: encoding: [0xf7,0x04,0x80,0x85]
+
+s_cselect_b64 s[0:1], 0x3f717273, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b64 s[0:1], 0xaf123456, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b64 s[0:1], s[2:3], exec
+// GFX10: encoding: [0x02,0x7e,0x80,0x85]
+
+s_cselect_b64 s[0:1], s[2:3], vcc
+// GFX10: encoding: [0x02,0x6a,0x80,0x85]
+
+s_cselect_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x85]
+
+s_cselect_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x85]
+
+s_cselect_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x85]
+
+s_cselect_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x85]
+
+s_cselect_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x85,0x56,0x34,0x12,0xaf]
+
+s_and_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x87]
+
+s_and_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x87]
+
+s_and_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x87]
+
+s_and_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x87]
+
+s_and_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x87]
+
+s_and_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x87]
+
+s_and_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x87]
+
+s_and_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x87]
+
+s_and_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x87]
+
+s_and_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x87]
+
+s_and_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x87]
+
+s_and_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x87]
+
+s_and_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x87]
+
+s_and_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x87]
+
+s_and_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x87]
+
+s_and_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x87]
+
+s_and_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x87]
+
+s_and_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x87]
+
+s_and_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x87]
+
+s_and_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x87]
+
+s_and_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x87]
+
+s_and_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x87]
+
+s_and_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x87,0x73,0x72,0x71,0x3f]
+
+s_and_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x87,0x56,0x34,0x12,0xaf]
+
+s_and_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x87]
+
+s_and_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x87]
+
+s_and_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x87]
+
+s_and_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x87]
+
+s_and_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x87]
+
+s_and_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x87]
+
+s_and_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x87]
+
+s_and_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x87]
+
+s_and_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x87]
+
+s_and_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x87,0x73,0x72,0x71,0x3f]
+
+s_and_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x87,0x56,0x34,0x12,0xaf]
+
+s_and_b64 s[0:1], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0x80,0x87]
+
+s_and_b64 s[104:105], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0xe8,0x87]
+
+s_and_b64 s[0:1], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0x80,0x87]
+
+s_and_b64 s[104:105], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0xe8,0x87]
+
+s_and_b64 s[104:105], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0xe8,0x87]
+
+s_and_b64 s[104:105], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xe8,0x87]
+
+s_and_b64 s[0:1], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0x80,0x87]
+
+s_and_b64 s[0:1], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0x80,0x87]
+
+s_and_b64 exec, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xfe,0x87]
+
+s_and_b64 vcc, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xea,0x87]
+
+s_and_b64 s[0:1], exec, s[4:5]
+// GFX10: encoding: [0x7e,0x04,0x80,0x87]
+
+s_and_b64 s[0:1], vcc, s[4:5]
+// GFX10: encoding: [0x6a,0x04,0x80,0x87]
+
+s_and_b64 s[0:1], 0, s[4:5]
+// GFX10: encoding: [0x80,0x04,0x80,0x87]
+
+s_and_b64 s[0:1], -1, s[4:5]
+// GFX10: encoding: [0xc1,0x04,0x80,0x87]
+
+s_and_b64 s[0:1], 0.5, s[4:5]
+// GFX10: encoding: [0xf0,0x04,0x80,0x87]
+
+s_and_b64 s[0:1], -4.0, s[4:5]
+// GFX10: encoding: [0xf7,0x04,0x80,0x87]
+
+s_and_b64 s[0:1], 0x3f717273, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x87,0x73,0x72,0x71,0x3f]
+
+s_and_b64 s[0:1], 0xaf123456, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x87,0x56,0x34,0x12,0xaf]
+
+s_and_b64 s[0:1], s[2:3], exec
+// GFX10: encoding: [0x02,0x7e,0x80,0x87]
+
+s_and_b64 s[0:1], s[2:3], vcc
+// GFX10: encoding: [0x02,0x6a,0x80,0x87]
+
+s_and_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x87]
+
+s_and_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x87]
+
+s_and_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x87]
+
+s_and_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x87]
+
+s_and_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x87,0x73,0x72,0x71,0x3f]
+
+s_and_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x87,0x56,0x34,0x12,0xaf]
+
+s_or_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x88]
+
+s_or_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x88]
+
+s_or_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x88]
+
+s_or_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x88]
+
+s_or_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x88]
+
+s_or_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x88]
+
+s_or_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x88]
+
+s_or_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x88]
+
+s_or_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x88]
+
+s_or_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x88]
+
+s_or_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x88]
+
+s_or_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x88]
+
+s_or_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x88]
+
+s_or_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x88]
+
+s_or_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x88]
+
+s_or_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x88]
+
+s_or_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x88]
+
+s_or_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x88]
+
+s_or_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x88]
+
+s_or_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x88]
+
+s_or_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x88]
+
+s_or_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x88]
+
+s_or_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x88,0x73,0x72,0x71,0x3f]
+
+s_or_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x88,0x56,0x34,0x12,0xaf]
+
+s_or_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x88]
+
+s_or_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x88]
+
+s_or_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x88]
+
+s_or_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x88]
+
+s_or_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x88]
+
+s_or_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x88]
+
+s_or_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x88]
+
+s_or_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x88]
+
+s_or_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x88]
+
+s_or_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x88,0x73,0x72,0x71,0x3f]
+
+s_or_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x88,0x56,0x34,0x12,0xaf]
+
+s_or_b64 s[0:1], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0x80,0x88]
+
+s_or_b64 s[104:105], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0xe8,0x88]
+
+s_or_b64 s[0:1], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0x80,0x88]
+
+s_or_b64 s[104:105], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0xe8,0x88]
+
+s_or_b64 s[104:105], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0xe8,0x88]
+
+s_or_b64 s[104:105], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xe8,0x88]
+
+s_or_b64 s[0:1], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0x80,0x88]
+
+s_or_b64 s[0:1], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0x80,0x88]
+
+s_or_b64 exec, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xfe,0x88]
+
+s_or_b64 vcc, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xea,0x88]
+
+s_or_b64 s[0:1], exec, s[4:5]
+// GFX10: encoding: [0x7e,0x04,0x80,0x88]
+
+s_or_b64 s[0:1], vcc, s[4:5]
+// GFX10: encoding: [0x6a,0x04,0x80,0x88]
+
+s_or_b64 s[0:1], 0, s[4:5]
+// GFX10: encoding: [0x80,0x04,0x80,0x88]
+
+s_or_b64 s[0:1], -1, s[4:5]
+// GFX10: encoding: [0xc1,0x04,0x80,0x88]
+
+s_or_b64 s[0:1], 0.5, s[4:5]
+// GFX10: encoding: [0xf0,0x04,0x80,0x88]
+
+s_or_b64 s[0:1], -4.0, s[4:5]
+// GFX10: encoding: [0xf7,0x04,0x80,0x88]
+
+s_or_b64 s[0:1], 0x3f717273, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x88,0x73,0x72,0x71,0x3f]
+
+s_or_b64 s[0:1], 0xaf123456, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x88,0x56,0x34,0x12,0xaf]
+
+s_or_b64 s[0:1], s[2:3], exec
+// GFX10: encoding: [0x02,0x7e,0x80,0x88]
+
+s_or_b64 s[0:1], s[2:3], vcc
+// GFX10: encoding: [0x02,0x6a,0x80,0x88]
+
+s_or_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x88]
+
+s_or_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x88]
+
+s_or_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x88]
+
+s_or_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x88]
+
+s_or_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x88,0x73,0x72,0x71,0x3f]
+
+s_or_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x88,0x56,0x34,0x12,0xaf]
+
+s_xor_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x89]
+
+s_xor_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x89]
+
+s_xor_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x89]
+
+s_xor_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x89]
+
+s_xor_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x89]
+
+s_xor_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x89]
+
+s_xor_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x89]
+
+s_xor_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x89]
+
+s_xor_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x89]
+
+s_xor_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x89]
+
+s_xor_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x89]
+
+s_xor_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x89]
+
+s_xor_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x89]
+
+s_xor_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x89]
+
+s_xor_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x89]
+
+s_xor_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x89]
+
+s_xor_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x89]
+
+s_xor_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x89]
+
+s_xor_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x89]
+
+s_xor_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x89]
+
+s_xor_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x89]
+
+s_xor_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x89]
+
+s_xor_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x89,0x73,0x72,0x71,0x3f]
+
+s_xor_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x89,0x56,0x34,0x12,0xaf]
+
+s_xor_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x89]
+
+s_xor_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x89]
+
+s_xor_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x89]
+
+s_xor_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x89]
+
+s_xor_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x89]
+
+s_xor_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x89]
+
+s_xor_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x89]
+
+s_xor_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x89]
+
+s_xor_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x89]
+
+s_xor_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x89,0x73,0x72,0x71,0x3f]
+
+s_xor_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x89,0x56,0x34,0x12,0xaf]
+
+s_xor_b64 s[0:1], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0x80,0x89]
+
+s_xor_b64 s[104:105], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0xe8,0x89]
+
+s_xor_b64 s[0:1], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0x80,0x89]
+
+s_xor_b64 s[104:105], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0xe8,0x89]
+
+s_xor_b64 s[104:105], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0xe8,0x89]
+
+s_xor_b64 s[104:105], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xe8,0x89]
+
+s_xor_b64 s[0:1], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0x80,0x89]
+
+s_xor_b64 s[0:1], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0x80,0x89]
+
+s_xor_b64 exec, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xfe,0x89]
+
+s_xor_b64 vcc, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xea,0x89]
+
+s_xor_b64 s[0:1], exec, s[4:5]
+// GFX10: encoding: [0x7e,0x04,0x80,0x89]
+
+s_xor_b64 s[0:1], vcc, s[4:5]
+// GFX10: encoding: [0x6a,0x04,0x80,0x89]
+
+s_xor_b64 s[0:1], 0, s[4:5]
+// GFX10: encoding: [0x80,0x04,0x80,0x89]
+
+s_xor_b64 s[0:1], -1, s[4:5]
+// GFX10: encoding: [0xc1,0x04,0x80,0x89]
+
+s_xor_b64 s[0:1], 0.5, s[4:5]
+// GFX10: encoding: [0xf0,0x04,0x80,0x89]
+
+s_xor_b64 s[0:1], -4.0, s[4:5]
+// GFX10: encoding: [0xf7,0x04,0x80,0x89]
+
+s_xor_b64 s[0:1], 0x3f717273, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x89,0x73,0x72,0x71,0x3f]
+
+s_xor_b64 s[0:1], 0xaf123456, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x89,0x56,0x34,0x12,0xaf]
+
+s_xor_b64 s[0:1], s[2:3], exec
+// GFX10: encoding: [0x02,0x7e,0x80,0x89]
+
+s_xor_b64 s[0:1], s[2:3], vcc
+// GFX10: encoding: [0x02,0x6a,0x80,0x89]
+
+s_xor_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x89]
+
+s_xor_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x89]
+
+s_xor_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x89]
+
+s_xor_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x89]
+
+s_xor_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x89,0x73,0x72,0x71,0x3f]
+
+s_xor_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x89,0x56,0x34,0x12,0xaf]
+
+s_andn2_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x8a]
+
+s_andn2_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x8a]
+
+s_andn2_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x8a]
+
+s_andn2_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x8a]
+
+s_andn2_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x8a]
+
+s_andn2_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x8a]
+
+s_andn2_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x8a]
+
+s_andn2_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x8a]
+
+s_andn2_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x8a]
+
+s_andn2_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x8a]
+
+s_andn2_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x8a]
+
+s_andn2_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x8a]
+
+s_andn2_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x8a]
+
+s_andn2_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8a,0x73,0x72,0x71,0x3f]
+
+s_andn2_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8a,0x56,0x34,0x12,0xaf]
+
+s_andn2_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x8a]
+
+s_andn2_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x8a]
+
+s_andn2_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x8a]
+
+s_andn2_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x8a]
+
+s_andn2_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x8a]
+
+s_andn2_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x8a]
+
+s_andn2_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x8a]
+
+s_andn2_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x8a]
+
+s_andn2_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x8a]
+
+s_andn2_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x8a,0x73,0x72,0x71,0x3f]
+
+s_andn2_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x8a,0x56,0x34,0x12,0xaf]
+
+s_andn2_b64 s[0:1], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0x80,0x8a]
+
+s_andn2_b64 s[104:105], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0xe8,0x8a]
+
+s_andn2_b64 s[0:1], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0x80,0x8a]
+
+s_andn2_b64 s[104:105], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0xe8,0x8a]
+
+s_andn2_b64 s[104:105], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0xe8,0x8a]
+
+s_andn2_b64 s[104:105], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xe8,0x8a]
+
+s_andn2_b64 s[0:1], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0x80,0x8a]
+
+s_andn2_b64 s[0:1], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0x80,0x8a]
+
+s_andn2_b64 exec, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xfe,0x8a]
+
+s_andn2_b64 vcc, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xea,0x8a]
+
+s_andn2_b64 s[0:1], exec, s[4:5]
+// GFX10: encoding: [0x7e,0x04,0x80,0x8a]
+
+s_andn2_b64 s[0:1], vcc, s[4:5]
+// GFX10: encoding: [0x6a,0x04,0x80,0x8a]
+
+s_andn2_b64 s[0:1], 0, s[4:5]
+// GFX10: encoding: [0x80,0x04,0x80,0x8a]
+
+s_andn2_b64 s[0:1], -1, s[4:5]
+// GFX10: encoding: [0xc1,0x04,0x80,0x8a]
+
+s_andn2_b64 s[0:1], 0.5, s[4:5]
+// GFX10: encoding: [0xf0,0x04,0x80,0x8a]
+
+s_andn2_b64 s[0:1], -4.0, s[4:5]
+// GFX10: encoding: [0xf7,0x04,0x80,0x8a]
+
+s_andn2_b64 s[0:1], 0x3f717273, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8a,0x73,0x72,0x71,0x3f]
+
+s_andn2_b64 s[0:1], 0xaf123456, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8a,0x56,0x34,0x12,0xaf]
+
+s_andn2_b64 s[0:1], s[2:3], exec
+// GFX10: encoding: [0x02,0x7e,0x80,0x8a]
+
+s_andn2_b64 s[0:1], s[2:3], vcc
+// GFX10: encoding: [0x02,0x6a,0x80,0x8a]
+
+s_andn2_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x8a]
+
+s_andn2_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x8a]
+
+s_andn2_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x8a]
+
+s_andn2_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x8a]
+
+s_andn2_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x8a,0x73,0x72,0x71,0x3f]
+
+s_andn2_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x8a,0x56,0x34,0x12,0xaf]
+
+s_orn2_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x8b]
+
+s_orn2_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x8b]
+
+s_orn2_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x8b]
+
+s_orn2_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x8b]
+
+s_orn2_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x8b]
+
+s_orn2_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x8b]
+
+s_orn2_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x8b]
+
+s_orn2_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x8b]
+
+s_orn2_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x8b]
+
+s_orn2_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x8b]
+
+s_orn2_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x8b]
+
+s_orn2_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x8b]
+
+s_orn2_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x8b]
+
+s_orn2_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8b,0x73,0x72,0x71,0x3f]
+
+s_orn2_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8b,0x56,0x34,0x12,0xaf]
+
+s_orn2_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x8b]
+
+s_orn2_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x8b]
+
+s_orn2_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x8b]
+
+s_orn2_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x8b]
+
+s_orn2_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x8b]
+
+s_orn2_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x8b]
+
+s_orn2_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x8b]
+
+s_orn2_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x8b]
+
+s_orn2_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x8b]
+
+s_orn2_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x8b,0x73,0x72,0x71,0x3f]
+
+s_orn2_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x8b,0x56,0x34,0x12,0xaf]
+
+s_orn2_b64 s[0:1], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0x80,0x8b]
+
+s_orn2_b64 s[104:105], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0xe8,0x8b]
+
+s_orn2_b64 s[0:1], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0x80,0x8b]
+
+s_orn2_b64 s[104:105], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0xe8,0x8b]
+
+s_orn2_b64 s[104:105], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0xe8,0x8b]
+
+s_orn2_b64 s[104:105], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xe8,0x8b]
+
+s_orn2_b64 s[0:1], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0x80,0x8b]
+
+s_orn2_b64 s[0:1], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0x80,0x8b]
+
+s_orn2_b64 exec, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xfe,0x8b]
+
+s_orn2_b64 vcc, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xea,0x8b]
+
+s_orn2_b64 s[0:1], exec, s[4:5]
+// GFX10: encoding: [0x7e,0x04,0x80,0x8b]
+
+s_orn2_b64 s[0:1], vcc, s[4:5]
+// GFX10: encoding: [0x6a,0x04,0x80,0x8b]
+
+s_orn2_b64 s[0:1], 0, s[4:5]
+// GFX10: encoding: [0x80,0x04,0x80,0x8b]
+
+s_orn2_b64 s[0:1], -1, s[4:5]
+// GFX10: encoding: [0xc1,0x04,0x80,0x8b]
+
+s_orn2_b64 s[0:1], 0.5, s[4:5]
+// GFX10: encoding: [0xf0,0x04,0x80,0x8b]
+
+s_orn2_b64 s[0:1], -4.0, s[4:5]
+// GFX10: encoding: [0xf7,0x04,0x80,0x8b]
+
+s_orn2_b64 s[0:1], 0x3f717273, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8b,0x73,0x72,0x71,0x3f]
+
+s_orn2_b64 s[0:1], 0xaf123456, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8b,0x56,0x34,0x12,0xaf]
+
+s_orn2_b64 s[0:1], s[2:3], exec
+// GFX10: encoding: [0x02,0x7e,0x80,0x8b]
+
+s_orn2_b64 s[0:1], s[2:3], vcc
+// GFX10: encoding: [0x02,0x6a,0x80,0x8b]
+
+s_orn2_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x8b]
+
+s_orn2_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x8b]
+
+s_orn2_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x8b]
+
+s_orn2_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x8b]
+
+s_orn2_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x8b,0x73,0x72,0x71,0x3f]
+
+s_orn2_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x8b,0x56,0x34,0x12,0xaf]
+
+s_nand_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x8c]
+
+s_nand_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x8c]
+
+s_nand_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x8c]
+
+s_nand_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x8c]
+
+s_nand_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x8c]
+
+s_nand_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x8c]
+
+s_nand_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x8c]
+
+s_nand_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x8c]
+
+s_nand_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x8c]
+
+s_nand_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x8c]
+
+s_nand_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x8c]
+
+s_nand_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x8c]
+
+s_nand_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x8c]
+
+s_nand_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x8c]
+
+s_nand_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x8c]
+
+s_nand_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x8c]
+
+s_nand_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x8c]
+
+s_nand_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x8c]
+
+s_nand_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x8c]
+
+s_nand_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x8c]
+
+s_nand_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x8c]
+
+s_nand_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x8c]
+
+s_nand_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nand_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nand_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x8c]
+
+s_nand_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x8c]
+
+s_nand_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x8c]
+
+s_nand_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x8c]
+
+s_nand_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x8c]
+
+s_nand_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x8c]
+
+s_nand_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x8c]
+
+s_nand_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x8c]
+
+s_nand_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x8c]
+
+s_nand_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nand_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nand_b64 s[0:1], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0x80,0x8c]
+
+s_nand_b64 s[104:105], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0xe8,0x8c]
+
+s_nand_b64 s[0:1], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0x80,0x8c]
+
+s_nand_b64 s[104:105], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0xe8,0x8c]
+
+s_nand_b64 s[104:105], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0xe8,0x8c]
+
+s_nand_b64 s[104:105], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xe8,0x8c]
+
+s_nand_b64 s[0:1], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0x80,0x8c]
+
+s_nand_b64 s[0:1], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0x80,0x8c]
+
+s_nand_b64 exec, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xfe,0x8c]
+
+s_nand_b64 vcc, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xea,0x8c]
+
+s_nand_b64 s[0:1], exec, s[4:5]
+// GFX10: encoding: [0x7e,0x04,0x80,0x8c]
+
+s_nand_b64 s[0:1], vcc, s[4:5]
+// GFX10: encoding: [0x6a,0x04,0x80,0x8c]
+
+s_nand_b64 s[0:1], 0, s[4:5]
+// GFX10: encoding: [0x80,0x04,0x80,0x8c]
+
+s_nand_b64 s[0:1], -1, s[4:5]
+// GFX10: encoding: [0xc1,0x04,0x80,0x8c]
+
+s_nand_b64 s[0:1], 0.5, s[4:5]
+// GFX10: encoding: [0xf0,0x04,0x80,0x8c]
+
+s_nand_b64 s[0:1], -4.0, s[4:5]
+// GFX10: encoding: [0xf7,0x04,0x80,0x8c]
+
+s_nand_b64 s[0:1], 0x3f717273, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nand_b64 s[0:1], 0xaf123456, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nand_b64 s[0:1], s[2:3], exec
+// GFX10: encoding: [0x02,0x7e,0x80,0x8c]
+
+s_nand_b64 s[0:1], s[2:3], vcc
+// GFX10: encoding: [0x02,0x6a,0x80,0x8c]
+
+s_nand_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x8c]
+
+s_nand_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x8c]
+
+s_nand_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x8c]
+
+s_nand_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x8c]
+
+s_nand_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nand_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nor_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x8d]
+
+s_nor_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x8d]
+
+s_nor_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x8d]
+
+s_nor_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x8d]
+
+s_nor_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x8d]
+
+s_nor_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x8d]
+
+s_nor_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x8d]
+
+s_nor_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x8d]
+
+s_nor_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x8d]
+
+s_nor_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x8d]
+
+s_nor_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x8d]
+
+s_nor_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x8d]
+
+s_nor_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x8d]
+
+s_nor_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x8d]
+
+s_nor_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x8d]
+
+s_nor_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x8d]
+
+s_nor_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x8d]
+
+s_nor_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x8d]
+
+s_nor_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x8d]
+
+s_nor_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x8d]
+
+s_nor_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x8d]
+
+s_nor_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x8d]
+
+s_nor_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8d,0x73,0x72,0x71,0x3f]
+
+s_nor_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8d,0x56,0x34,0x12,0xaf]
+
+s_nor_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x8d]
+
+s_nor_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x8d]
+
+s_nor_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x8d]
+
+s_nor_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x8d]
+
+s_nor_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x8d]
+
+s_nor_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x8d]
+
+s_nor_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x8d]
+
+s_nor_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x8d]
+
+s_nor_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x8d]
+
+s_nor_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x8d,0x73,0x72,0x71,0x3f]
+
+s_nor_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x8d,0x56,0x34,0x12,0xaf]
+
+s_nor_b64 s[0:1], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0x80,0x8d]
+
+s_nor_b64 s[104:105], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0xe8,0x8d]
+
+s_nor_b64 s[0:1], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0x80,0x8d]
+
+s_nor_b64 s[104:105], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0xe8,0x8d]
+
+s_nor_b64 s[104:105], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0xe8,0x8d]
+
+s_nor_b64 s[104:105], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xe8,0x8d]
+
+s_nor_b64 s[0:1], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0x80,0x8d]
+
+s_nor_b64 s[0:1], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0x80,0x8d]
+
+s_nor_b64 exec, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xfe,0x8d]
+
+s_nor_b64 vcc, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xea,0x8d]
+
+s_nor_b64 s[0:1], exec, s[4:5]
+// GFX10: encoding: [0x7e,0x04,0x80,0x8d]
+
+s_nor_b64 s[0:1], vcc, s[4:5]
+// GFX10: encoding: [0x6a,0x04,0x80,0x8d]
+
+s_nor_b64 s[0:1], 0, s[4:5]
+// GFX10: encoding: [0x80,0x04,0x80,0x8d]
+
+s_nor_b64 s[0:1], -1, s[4:5]
+// GFX10: encoding: [0xc1,0x04,0x80,0x8d]
+
+s_nor_b64 s[0:1], 0.5, s[4:5]
+// GFX10: encoding: [0xf0,0x04,0x80,0x8d]
+
+s_nor_b64 s[0:1], -4.0, s[4:5]
+// GFX10: encoding: [0xf7,0x04,0x80,0x8d]
+
+s_nor_b64 s[0:1], 0x3f717273, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8d,0x73,0x72,0x71,0x3f]
+
+s_nor_b64 s[0:1], 0xaf123456, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8d,0x56,0x34,0x12,0xaf]
+
+s_nor_b64 s[0:1], s[2:3], exec
+// GFX10: encoding: [0x02,0x7e,0x80,0x8d]
+
+s_nor_b64 s[0:1], s[2:3], vcc
+// GFX10: encoding: [0x02,0x6a,0x80,0x8d]
+
+s_nor_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x8d]
+
+s_nor_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x8d]
+
+s_nor_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x8d]
+
+s_nor_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x8d]
+
+s_nor_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x8d,0x73,0x72,0x71,0x3f]
+
+s_nor_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x8d,0x56,0x34,0x12,0xaf]
+
+s_xnor_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x8e]
+
+s_xnor_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x8e]
+
+s_xnor_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x8e]
+
+s_xnor_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x8e]
+
+s_xnor_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x8e]
+
+s_xnor_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x8e]
+
+s_xnor_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x8e]
+
+s_xnor_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x8e]
+
+s_xnor_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x8e]
+
+s_xnor_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x8e]
+
+s_xnor_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x8e]
+
+s_xnor_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x8e]
+
+s_xnor_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x8e]
+
+s_xnor_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8e,0x73,0x72,0x71,0x3f]
+
+s_xnor_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8e,0x56,0x34,0x12,0xaf]
+
+s_xnor_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x8e]
+
+s_xnor_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x8e]
+
+s_xnor_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x8e]
+
+s_xnor_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x8e]
+
+s_xnor_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x8e]
+
+s_xnor_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x8e]
+
+s_xnor_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x8e]
+
+s_xnor_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x8e]
+
+s_xnor_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x8e]
+
+s_xnor_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x8e,0x73,0x72,0x71,0x3f]
+
+s_xnor_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x8e,0x56,0x34,0x12,0xaf]
+
+s_xnor_b64 s[0:1], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0x80,0x8e]
+
+s_xnor_b64 s[104:105], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0xe8,0x8e]
+
+s_xnor_b64 s[0:1], s[102:103], s[100:101]
+// GFX10: encoding: [0x66,0x64,0x80,0x8e]
+
+s_xnor_b64 s[104:105], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0xe8,0x8e]
+
+s_xnor_b64 s[104:105], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0xe8,0x8e]
+
+s_xnor_b64 s[104:105], s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xe8,0x8e]
+
+s_xnor_b64 s[0:1], s[102:103], s[4:5]
+// GFX10: encoding: [0x66,0x04,0x80,0x8e]
+
+s_xnor_b64 s[0:1], s[2:3], s[100:101]
+// GFX10: encoding: [0x02,0x64,0x80,0x8e]
+
+s_xnor_b64 exec, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xfe,0x8e]
+
+s_xnor_b64 vcc, s[2:3], s[4:5]
+// GFX10: encoding: [0x02,0x04,0xea,0x8e]
+
+s_xnor_b64 s[0:1], exec, s[4:5]
+// GFX10: encoding: [0x7e,0x04,0x80,0x8e]
+
+s_xnor_b64 s[0:1], vcc, s[4:5]
+// GFX10: encoding: [0x6a,0x04,0x80,0x8e]
+
+s_xnor_b64 s[0:1], 0, s[4:5]
+// GFX10: encoding: [0x80,0x04,0x80,0x8e]
+
+s_xnor_b64 s[0:1], -1, s[4:5]
+// GFX10: encoding: [0xc1,0x04,0x80,0x8e]
+
+s_xnor_b64 s[0:1], 0.5, s[4:5]
+// GFX10: encoding: [0xf0,0x04,0x80,0x8e]
+
+s_xnor_b64 s[0:1], -4.0, s[4:5]
+// GFX10: encoding: [0xf7,0x04,0x80,0x8e]
+
+s_xnor_b64 s[0:1], 0x3f717273, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8e,0x73,0x72,0x71,0x3f]
+
+s_xnor_b64 s[0:1], 0xaf123456, s[4:5]
+// GFX10: encoding: [0xff,0x04,0x80,0x8e,0x56,0x34,0x12,0xaf]
+
+s_xnor_b64 s[0:1], s[2:3], exec
+// GFX10: encoding: [0x02,0x7e,0x80,0x8e]
+
+s_xnor_b64 s[0:1], s[2:3], vcc
+// GFX10: encoding: [0x02,0x6a,0x80,0x8e]
+
+s_xnor_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x8e]
+
+s_xnor_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x8e]
+
+s_xnor_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x8e]
+
+s_xnor_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x8e]
+
+s_xnor_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x8e,0x73,0x72,0x71,0x3f]
+
+s_xnor_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x8e,0x56,0x34,0x12,0xaf]
+
+s_lshl_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x8f]
+
+s_lshl_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x8f]
+
+s_lshl_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x8f]
+
+s_lshl_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x8f]
+
+s_lshl_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x8f]
+
+s_lshl_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x8f]
+
+s_lshl_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x8f]
+
+s_lshl_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x8f]
+
+s_lshl_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x8f]
+
+s_lshl_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x8f]
+
+s_lshl_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x8f]
+
+s_lshl_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x8f]
+
+s_lshl_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x8f]
+
+s_lshl_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshl_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshl_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x8f]
+
+s_lshl_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x8f]
+
+s_lshl_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x8f]
+
+s_lshl_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x8f]
+
+s_lshl_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x8f]
+
+s_lshl_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x8f]
+
+s_lshl_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x8f]
+
+s_lshl_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x8f]
+
+s_lshl_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x8f]
+
+s_lshl_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshl_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshl_b64 s[0:1], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0x80,0x8f]
+
+s_lshl_b64 s[104:105], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0xe8,0x8f]
+
+s_lshl_b64 s[0:1], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0x80,0x8f]
+
+s_lshl_b64 s[104:105], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0xe8,0x8f]
+
+s_lshl_b64 s[104:105], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0xe8,0x8f]
+
+s_lshl_b64 s[104:105], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xe8,0x8f]
+
+s_lshl_b64 s[0:1], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0x80,0x8f]
+
+s_lshl_b64 s[0:1], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0x80,0x8f]
+
+s_lshl_b64 exec, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xfe,0x8f]
+
+s_lshl_b64 vcc, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xea,0x8f]
+
+s_lshl_b64 s[0:1], exec, s4
+// GFX10: encoding: [0x7e,0x04,0x80,0x8f]
+
+s_lshl_b64 s[0:1], vcc, s4
+// GFX10: encoding: [0x6a,0x04,0x80,0x8f]
+
+s_lshl_b64 s[0:1], 0, s4
+// GFX10: encoding: [0x80,0x04,0x80,0x8f]
+
+s_lshl_b64 s[0:1], -1, s4
+// GFX10: encoding: [0xc1,0x04,0x80,0x8f]
+
+s_lshl_b64 s[0:1], 0.5, s4
+// GFX10: encoding: [0xf0,0x04,0x80,0x8f]
+
+s_lshl_b64 s[0:1], -4.0, s4
+// GFX10: encoding: [0xf7,0x04,0x80,0x8f]
+
+s_lshl_b64 s[0:1], 0x3f717273, s4
+// GFX10: encoding: [0xff,0x04,0x80,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshl_b64 s[0:1], 0xaf123456, s4
+// GFX10: encoding: [0xff,0x04,0x80,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshl_b64 s[0:1], s[2:3], exec_lo
+// GFX10: encoding: [0x02,0x7e,0x80,0x8f]
+
+s_lshl_b64 s[0:1], s[2:3], vcc_lo
+// GFX10: encoding: [0x02,0x6a,0x80,0x8f]
+
+s_lshl_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x8f]
+
+s_lshl_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x8f]
+
+s_lshl_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x8f]
+
+s_lshl_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x8f]
+
+s_lshl_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshl_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshr_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x90]
+
+s_lshr_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x90]
+
+s_lshr_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x90]
+
+s_lshr_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x90]
+
+s_lshr_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x90]
+
+s_lshr_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x90]
+
+s_lshr_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x90]
+
+s_lshr_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x90]
+
+s_lshr_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x90]
+
+s_lshr_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x90]
+
+s_lshr_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x90]
+
+s_lshr_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x90]
+
+s_lshr_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x90]
+
+s_lshr_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x90]
+
+s_lshr_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x90]
+
+s_lshr_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x90]
+
+s_lshr_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x90]
+
+s_lshr_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x90]
+
+s_lshr_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x90]
+
+s_lshr_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x90]
+
+s_lshr_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x90]
+
+s_lshr_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x90]
+
+s_lshr_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x90,0x73,0x72,0x71,0x3f]
+
+s_lshr_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x90,0x56,0x34,0x12,0xaf]
+
+s_lshr_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x90]
+
+s_lshr_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x90]
+
+s_lshr_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x90]
+
+s_lshr_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x90]
+
+s_lshr_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x90]
+
+s_lshr_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x90]
+
+s_lshr_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x90]
+
+s_lshr_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x90]
+
+s_lshr_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x90]
+
+s_lshr_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x90,0x73,0x72,0x71,0x3f]
+
+s_lshr_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x90,0x56,0x34,0x12,0xaf]
+
+s_lshr_b64 s[0:1], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0x80,0x90]
+
+s_lshr_b64 s[104:105], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0xe8,0x90]
+
+s_lshr_b64 s[0:1], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0x80,0x90]
+
+s_lshr_b64 s[104:105], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0xe8,0x90]
+
+s_lshr_b64 s[104:105], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0xe8,0x90]
+
+s_lshr_b64 s[104:105], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xe8,0x90]
+
+s_lshr_b64 s[0:1], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0x80,0x90]
+
+s_lshr_b64 s[0:1], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0x80,0x90]
+
+s_lshr_b64 exec, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xfe,0x90]
+
+s_lshr_b64 vcc, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xea,0x90]
+
+s_lshr_b64 s[0:1], exec, s4
+// GFX10: encoding: [0x7e,0x04,0x80,0x90]
+
+s_lshr_b64 s[0:1], vcc, s4
+// GFX10: encoding: [0x6a,0x04,0x80,0x90]
+
+s_lshr_b64 s[0:1], 0, s4
+// GFX10: encoding: [0x80,0x04,0x80,0x90]
+
+s_lshr_b64 s[0:1], -1, s4
+// GFX10: encoding: [0xc1,0x04,0x80,0x90]
+
+s_lshr_b64 s[0:1], 0.5, s4
+// GFX10: encoding: [0xf0,0x04,0x80,0x90]
+
+s_lshr_b64 s[0:1], -4.0, s4
+// GFX10: encoding: [0xf7,0x04,0x80,0x90]
+
+s_lshr_b64 s[0:1], 0x3f717273, s4
+// GFX10: encoding: [0xff,0x04,0x80,0x90,0x73,0x72,0x71,0x3f]
+
+s_lshr_b64 s[0:1], 0xaf123456, s4
+// GFX10: encoding: [0xff,0x04,0x80,0x90,0x56,0x34,0x12,0xaf]
+
+s_lshr_b64 s[0:1], s[2:3], exec_lo
+// GFX10: encoding: [0x02,0x7e,0x80,0x90]
+
+s_lshr_b64 s[0:1], s[2:3], vcc_lo
+// GFX10: encoding: [0x02,0x6a,0x80,0x90]
+
+s_lshr_b64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x90]
+
+s_lshr_b64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x90]
+
+s_lshr_b64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x90]
+
+s_lshr_b64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x90]
+
+s_lshr_b64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x90,0x73,0x72,0x71,0x3f]
+
+s_lshr_b64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x90,0x56,0x34,0x12,0xaf]
+
+s_ashr_i32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x91]
+
+s_ashr_i32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x91]
+
+s_ashr_i32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x91]
+
+s_ashr_i32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x91]
+
+s_ashr_i32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x91]
+
+s_ashr_i32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x91]
+
+s_ashr_i32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x91]
+
+s_ashr_i32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x91]
+
+s_ashr_i32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x91]
+
+s_ashr_i32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x91]
+
+s_ashr_i32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x91]
+
+s_ashr_i32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x91]
+
+s_ashr_i32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x91]
+
+s_ashr_i32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x91]
+
+s_ashr_i32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x91]
+
+s_ashr_i32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x91]
+
+s_ashr_i32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x91]
+
+s_ashr_i32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x91]
+
+s_ashr_i32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x91]
+
+s_ashr_i32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x91]
+
+s_ashr_i32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x91]
+
+s_ashr_i32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x91]
+
+s_ashr_i32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x91,0x73,0x72,0x71,0x3f]
+
+s_ashr_i32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x91,0x56,0x34,0x12,0xaf]
+
+s_ashr_i32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x91]
+
+s_ashr_i32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x91]
+
+s_ashr_i32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x91]
+
+s_ashr_i32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x91]
+
+s_ashr_i32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x91]
+
+s_ashr_i32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x91]
+
+s_ashr_i32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x91]
+
+s_ashr_i32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x91]
+
+s_ashr_i32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x91]
+
+s_ashr_i32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x91,0x73,0x72,0x71,0x3f]
+
+s_ashr_i32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x91,0x56,0x34,0x12,0xaf]
+
+s_ashr_i64 s[0:1], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0x80,0x91]
+
+s_ashr_i64 s[104:105], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0xe8,0x91]
+
+s_ashr_i64 s[0:1], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0x80,0x91]
+
+s_ashr_i64 s[104:105], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0xe8,0x91]
+
+s_ashr_i64 s[104:105], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0xe8,0x91]
+
+s_ashr_i64 s[104:105], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xe8,0x91]
+
+s_ashr_i64 s[0:1], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0x80,0x91]
+
+s_ashr_i64 s[0:1], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0x80,0x91]
+
+s_ashr_i64 exec, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xfe,0x91]
+
+s_ashr_i64 vcc, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xea,0x91]
+
+s_ashr_i64 s[0:1], exec, s4
+// GFX10: encoding: [0x7e,0x04,0x80,0x91]
+
+s_ashr_i64 s[0:1], vcc, s4
+// GFX10: encoding: [0x6a,0x04,0x80,0x91]
+
+s_ashr_i64 s[0:1], 0, s4
+// GFX10: encoding: [0x80,0x04,0x80,0x91]
+
+s_ashr_i64 s[0:1], -1, s4
+// GFX10: encoding: [0xc1,0x04,0x80,0x91]
+
+s_ashr_i64 s[0:1], 0.5, s4
+// GFX10: encoding: [0xf0,0x04,0x80,0x91]
+
+s_ashr_i64 s[0:1], -4.0, s4
+// GFX10: encoding: [0xf7,0x04,0x80,0x91]
+
+s_ashr_i64 s[0:1], 0x3f717273, s4
+// GFX10: encoding: [0xff,0x04,0x80,0x91,0x73,0x72,0x71,0x3f]
+
+s_ashr_i64 s[0:1], 0xaf123456, s4
+// GFX10: encoding: [0xff,0x04,0x80,0x91,0x56,0x34,0x12,0xaf]
+
+s_ashr_i64 s[0:1], s[2:3], exec_lo
+// GFX10: encoding: [0x02,0x7e,0x80,0x91]
+
+s_ashr_i64 s[0:1], s[2:3], vcc_lo
+// GFX10: encoding: [0x02,0x6a,0x80,0x91]
+
+s_ashr_i64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x91]
+
+s_ashr_i64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x91]
+
+s_ashr_i64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x91]
+
+s_ashr_i64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x91]
+
+s_ashr_i64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x91,0x73,0x72,0x71,0x3f]
+
+s_ashr_i64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x91,0x56,0x34,0x12,0xaf]
+
+s_bfm_b32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x92]
+
+s_bfm_b32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x92]
+
+s_bfm_b32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x92]
+
+s_bfm_b32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x92]
+
+s_bfm_b32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x92]
+
+s_bfm_b32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x92]
+
+s_bfm_b32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x92]
+
+s_bfm_b32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x92]
+
+s_bfm_b32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x92]
+
+s_bfm_b32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x92]
+
+s_bfm_b32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x92]
+
+s_bfm_b32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x92]
+
+s_bfm_b32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x92]
+
+s_bfm_b32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x92]
+
+s_bfm_b32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x92]
+
+s_bfm_b32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x92]
+
+s_bfm_b32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x92]
+
+s_bfm_b32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x92]
+
+s_bfm_b32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x92]
+
+s_bfm_b32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x92]
+
+s_bfm_b32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x92]
+
+s_bfm_b32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x92]
+
+s_bfm_b32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfm_b32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfm_b32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x92]
+
+s_bfm_b32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x92]
+
+s_bfm_b32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x92]
+
+s_bfm_b32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x92]
+
+s_bfm_b32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x92]
+
+s_bfm_b32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x92]
+
+s_bfm_b32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x92]
+
+s_bfm_b32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x92]
+
+s_bfm_b32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x92]
+
+s_bfm_b32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfm_b32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfm_b64 s[0:1], s2, s3
+// GFX10: encoding: [0x02,0x03,0x80,0x92]
+
+s_bfm_b64 s[104:105], s103, s102
+// GFX10: encoding: [0x67,0x66,0xe8,0x92]
+
+s_bfm_b64 s[0:1], s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x92]
+
+s_bfm_b64 s[104:105], s2, s103
+// GFX10: encoding: [0x02,0x67,0xe8,0x92]
+
+s_bfm_b64 s[104:105], s104, s3
+// GFX10: encoding: [0x68,0x03,0xe8,0x92]
+
+s_bfm_b64 s[104:105], s2, s3
+// GFX10: encoding: [0x02,0x03,0xe8,0x92]
+
+s_bfm_b64 s[0:1], s104, s3
+// GFX10: encoding: [0x68,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, s103
+// GFX10: encoding: [0x02,0x67,0x80,0x92]
+
+s_bfm_b64 exec, s2, s3
+// GFX10: encoding: [0x02,0x03,0xfe,0x92]
+
+s_bfm_b64 vcc, s2, s3
+// GFX10: encoding: [0x02,0x03,0xea,0x92]
+
+s_bfm_b64 s[0:1], exec_lo, s3
+// GFX10: encoding: [0x7e,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], exec_hi, s3
+// GFX10: encoding: [0x7f,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], vcc_lo, s3
+// GFX10: encoding: [0x6a,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], vcc_hi, s3
+// GFX10: encoding: [0x6b,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], m0, s3
+// GFX10: encoding: [0x7c,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], 0, s3
+// GFX10: encoding: [0x80,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], -1, s3
+// GFX10: encoding: [0xc1,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], 0.5, s3
+// GFX10: encoding: [0xf0,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], -4.0, s3
+// GFX10: encoding: [0xf7,0x03,0x80,0x92]
+
+s_bfm_b64 s[0:1], 0x3f717273, s3
+// GFX10: encoding: [0xff,0x03,0x80,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfm_b64 s[0:1], 0xaf123456, s3
+// GFX10: encoding: [0xff,0x03,0x80,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfm_b64 s[0:1], s2, exec_lo
+// GFX10: encoding: [0x02,0x7e,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, exec_hi
+// GFX10: encoding: [0x02,0x7f,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, vcc_lo
+// GFX10: encoding: [0x02,0x6a,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, vcc_hi
+// GFX10: encoding: [0x02,0x6b,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, m0
+// GFX10: encoding: [0x02,0x7c,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, 0
+// GFX10: encoding: [0x02,0x80,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x92]
+
+s_bfm_b64 s[0:1], s2, 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfm_b64 s[0:1], s2, 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x92,0x56,0x34,0x12,0xaf]
+
+s_mul_i32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x93]
+
+s_mul_i32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x93]
+
+s_mul_i32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x93]
+
+s_mul_i32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x93]
+
+s_mul_i32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x93]
+
+s_mul_i32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x93]
+
+s_mul_i32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x93]
+
+s_mul_i32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x93]
+
+s_mul_i32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x93]
+
+s_mul_i32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x93]
+
+s_mul_i32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x93]
+
+s_mul_i32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x93]
+
+s_mul_i32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x93]
+
+s_mul_i32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x93]
+
+s_mul_i32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x93]
+
+s_mul_i32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x93]
+
+s_mul_i32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x93]
+
+s_mul_i32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x93]
+
+s_mul_i32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x93]
+
+s_mul_i32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x93]
+
+s_mul_i32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x93]
+
+s_mul_i32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x93]
+
+s_mul_i32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x93,0x73,0x72,0x71,0x3f]
+
+s_mul_i32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x93,0x56,0x34,0x12,0xaf]
+
+s_mul_i32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x93]
+
+s_mul_i32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x93]
+
+s_mul_i32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x93]
+
+s_mul_i32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x93]
+
+s_mul_i32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x93]
+
+s_mul_i32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x93]
+
+s_mul_i32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x93]
+
+s_mul_i32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x93]
+
+s_mul_i32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x93]
+
+s_mul_i32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x93,0x73,0x72,0x71,0x3f]
+
+s_mul_i32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x93]
+
+s_bfe_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x93]
+
+s_bfe_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x93]
+
+s_bfe_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x93]
+
+s_bfe_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x93]
+
+s_bfe_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x93]
+
+s_bfe_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x93]
+
+s_bfe_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x93]
+
+s_bfe_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x93]
+
+s_bfe_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x93]
+
+s_bfe_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x93]
+
+s_bfe_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x93]
+
+s_bfe_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x93]
+
+s_bfe_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x93]
+
+s_bfe_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x93]
+
+s_bfe_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x93]
+
+s_bfe_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x93]
+
+s_bfe_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x93]
+
+s_bfe_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x93]
+
+s_bfe_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x93]
+
+s_bfe_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x93]
+
+s_bfe_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x93]
+
+s_bfe_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x93]
+
+s_bfe_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x93]
+
+s_bfe_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x93]
+
+s_bfe_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x93]
+
+s_bfe_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x93]
+
+s_bfe_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x93]
+
+s_bfe_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x93]
+
+s_bfe_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x93]
+
+s_bfe_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x93]
+
+s_bfe_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_i32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x94]
+
+s_bfe_i32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x94]
+
+s_bfe_i32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x94]
+
+s_bfe_i32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x94]
+
+s_bfe_i32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x94]
+
+s_bfe_i32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x94]
+
+s_bfe_i32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x94]
+
+s_bfe_i32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x94]
+
+s_bfe_i32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x94]
+
+s_bfe_i32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x94]
+
+s_bfe_i32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x94]
+
+s_bfe_i32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x94]
+
+s_bfe_i32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x94]
+
+s_bfe_i32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x94]
+
+s_bfe_i32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x94]
+
+s_bfe_i32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x94]
+
+s_bfe_i32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x94]
+
+s_bfe_i32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x94]
+
+s_bfe_i32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x94]
+
+s_bfe_i32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x94]
+
+s_bfe_i32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x94]
+
+s_bfe_i32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x94]
+
+s_bfe_i32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_i32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_i32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x94]
+
+s_bfe_i32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x94]
+
+s_bfe_i32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x94]
+
+s_bfe_i32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x94]
+
+s_bfe_i32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x94]
+
+s_bfe_i32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x94]
+
+s_bfe_i32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x94]
+
+s_bfe_i32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x94]
+
+s_bfe_i32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x94]
+
+s_bfe_i32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_i32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_u64 s[0:1], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0x80,0x94]
+
+s_bfe_u64 s[104:105], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0xe8,0x94]
+
+s_bfe_u64 s[0:1], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0x80,0x94]
+
+s_bfe_u64 s[104:105], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0xe8,0x94]
+
+s_bfe_u64 s[104:105], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0xe8,0x94]
+
+s_bfe_u64 s[104:105], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xe8,0x94]
+
+s_bfe_u64 s[0:1], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0x80,0x94]
+
+s_bfe_u64 s[0:1], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0x80,0x94]
+
+s_bfe_u64 exec, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xfe,0x94]
+
+s_bfe_u64 vcc, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0xea,0x94]
+
+s_bfe_u64 s[0:1], exec, s4
+// GFX10: encoding: [0x7e,0x04,0x80,0x94]
+
+s_bfe_u64 s[0:1], vcc, s4
+// GFX10: encoding: [0x6a,0x04,0x80,0x94]
+
+s_bfe_u64 s[0:1], 0, s4
+// GFX10: encoding: [0x80,0x04,0x80,0x94]
+
+s_bfe_u64 s[0:1], -1, s4
+// GFX10: encoding: [0xc1,0x04,0x80,0x94]
+
+s_bfe_u64 s[0:1], 0.5, s4
+// GFX10: encoding: [0xf0,0x04,0x80,0x94]
+
+s_bfe_u64 s[0:1], -4.0, s4
+// GFX10: encoding: [0xf7,0x04,0x80,0x94]
+
+s_bfe_u64 s[0:1], 0x3f717273, s4
+// GFX10: encoding: [0xff,0x04,0x80,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_u64 s[0:1], 0xaf123456, s4
+// GFX10: encoding: [0xff,0x04,0x80,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_u64 s[0:1], s[2:3], exec_lo
+// GFX10: encoding: [0x02,0x7e,0x80,0x94]
+
+s_bfe_u64 s[0:1], s[2:3], vcc_lo
+// GFX10: encoding: [0x02,0x6a,0x80,0x94]
+
+s_bfe_u64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x80,0x94]
+
+s_bfe_u64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x80,0x94]
+
+s_bfe_u64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x80,0x94]
+
+s_bfe_u64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x80,0x94]
+
+s_bfe_u64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x80,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_u64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x80,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_i64 s[0:1], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0x00,0x95]
+
+s_bfe_i64 s[104:105], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0x68,0x95]
+
+s_bfe_i64 s[0:1], s[102:103], s100
+// GFX10: encoding: [0x66,0x64,0x00,0x95]
+
+s_bfe_i64 s[104:105], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0x68,0x95]
+
+s_bfe_i64 s[104:105], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0x68,0x95]
+
+s_bfe_i64 s[104:105], s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0x68,0x95]
+
+s_bfe_i64 s[0:1], s[102:103], s4
+// GFX10: encoding: [0x66,0x04,0x00,0x95]
+
+s_bfe_i64 s[0:1], s[2:3], s100
+// GFX10: encoding: [0x02,0x64,0x00,0x95]
+
+s_bfe_i64 exec, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0x7e,0x95]
+
+s_bfe_i64 vcc, s[2:3], s4
+// GFX10: encoding: [0x02,0x04,0x6a,0x95]
+
+s_bfe_i64 s[0:1], exec, s4
+// GFX10: encoding: [0x7e,0x04,0x00,0x95]
+
+s_bfe_i64 s[0:1], vcc, s4
+// GFX10: encoding: [0x6a,0x04,0x00,0x95]
+
+s_bfe_i64 s[0:1], 0, s4
+// GFX10: encoding: [0x80,0x04,0x00,0x95]
+
+s_bfe_i64 s[0:1], -1, s4
+// GFX10: encoding: [0xc1,0x04,0x00,0x95]
+
+s_bfe_i64 s[0:1], 0.5, s4
+// GFX10: encoding: [0xf0,0x04,0x00,0x95]
+
+s_bfe_i64 s[0:1], -4.0, s4
+// GFX10: encoding: [0xf7,0x04,0x00,0x95]
+
+s_bfe_i64 s[0:1], 0x3f717273, s4
+// GFX10: encoding: [0xff,0x04,0x00,0x95,0x73,0x72,0x71,0x3f]
+
+s_bfe_i64 s[0:1], 0xaf123456, s4
+// GFX10: encoding: [0xff,0x04,0x00,0x95,0x56,0x34,0x12,0xaf]
+
+s_bfe_i64 s[0:1], s[2:3], exec_lo
+// GFX10: encoding: [0x02,0x7e,0x00,0x95]
+
+s_bfe_i64 s[0:1], s[2:3], vcc_lo
+// GFX10: encoding: [0x02,0x6a,0x00,0x95]
+
+s_bfe_i64 s[0:1], s[2:3], 0
+// GFX10: encoding: [0x02,0x80,0x00,0x95]
+
+s_bfe_i64 s[0:1], s[2:3], -1
+// GFX10: encoding: [0x02,0xc1,0x00,0x95]
+
+s_bfe_i64 s[0:1], s[2:3], 0.5
+// GFX10: encoding: [0x02,0xf0,0x00,0x95]
+
+s_bfe_i64 s[0:1], s[2:3], -4.0
+// GFX10: encoding: [0x02,0xf7,0x00,0x95]
+
+s_bfe_i64 s[0:1], s[2:3], 0x3f717273
+// GFX10: encoding: [0x02,0xff,0x00,0x95,0x73,0x72,0x71,0x3f]
+
+s_bfe_i64 s[0:1], s[2:3], 0xaf123456
+// GFX10: encoding: [0x02,0xff,0x00,0x95,0x56,0x34,0x12,0xaf]
+
+s_absdiff_i32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x96]
+
+s_absdiff_i32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x96]
+
+s_absdiff_i32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x96]
+
+s_absdiff_i32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x96]
+
+s_absdiff_i32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x96]
+
+s_absdiff_i32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x96]
+
+s_absdiff_i32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x96]
+
+s_absdiff_i32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x96]
+
+s_absdiff_i32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x96]
+
+s_absdiff_i32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x96]
+
+s_absdiff_i32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x96]
+
+s_absdiff_i32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x96]
+
+s_absdiff_i32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x96]
+
+s_absdiff_i32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x96,0x73,0x72,0x71,0x3f]
+
+s_absdiff_i32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x96,0x56,0x34,0x12,0xaf]
+
+s_absdiff_i32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x96]
+
+s_absdiff_i32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x96]
+
+s_absdiff_i32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x96]
+
+s_absdiff_i32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x96]
+
+s_absdiff_i32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x96]
+
+s_absdiff_i32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x96]
+
+s_absdiff_i32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x96]
+
+s_absdiff_i32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x96]
+
+s_absdiff_i32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x96]
+
+s_absdiff_i32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x96,0x73,0x72,0x71,0x3f]
+
+s_absdiff_i32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x96,0x56,0x34,0x12,0xaf]
+
+s_lshl1_add_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x97]
+
+s_lshl1_add_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x97]
+
+s_lshl1_add_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x97]
+
+s_lshl1_add_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x97]
+
+s_lshl1_add_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x97]
+
+s_lshl1_add_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x97]
+
+s_lshl1_add_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x97]
+
+s_lshl1_add_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x97]
+
+s_lshl1_add_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x97]
+
+s_lshl1_add_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x97]
+
+s_lshl1_add_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x97]
+
+s_lshl1_add_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x97]
+
+s_lshl1_add_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x97,0x73,0x72,0x71,0x3f]
+
+s_lshl1_add_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x97,0x56,0x34,0x12,0xaf]
+
+s_lshl1_add_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x97]
+
+s_lshl1_add_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x97,0x73,0x72,0x71,0x3f]
+
+s_lshl1_add_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x97,0x56,0x34,0x12,0xaf]
+
+s_lshl2_add_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x97]
+
+s_lshl2_add_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x97]
+
+s_lshl2_add_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x97]
+
+s_lshl2_add_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x97]
+
+s_lshl2_add_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x97]
+
+s_lshl2_add_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x97]
+
+s_lshl2_add_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x97]
+
+s_lshl2_add_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x97]
+
+s_lshl2_add_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x97]
+
+s_lshl2_add_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x97]
+
+s_lshl2_add_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x97]
+
+s_lshl2_add_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x97]
+
+s_lshl2_add_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x97,0x73,0x72,0x71,0x3f]
+
+s_lshl2_add_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x97,0x56,0x34,0x12,0xaf]
+
+s_lshl2_add_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x97]
+
+s_lshl2_add_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x97,0x73,0x72,0x71,0x3f]
+
+s_lshl2_add_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x97,0x56,0x34,0x12,0xaf]
+
+s_lshl3_add_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x98]
+
+s_lshl3_add_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x98]
+
+s_lshl3_add_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x98]
+
+s_lshl3_add_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x98]
+
+s_lshl3_add_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x98]
+
+s_lshl3_add_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x98]
+
+s_lshl3_add_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x98]
+
+s_lshl3_add_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x98]
+
+s_lshl3_add_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x98]
+
+s_lshl3_add_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x98]
+
+s_lshl3_add_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x98]
+
+s_lshl3_add_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x98]
+
+s_lshl3_add_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x98,0x73,0x72,0x71,0x3f]
+
+s_lshl3_add_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x98,0x56,0x34,0x12,0xaf]
+
+s_lshl3_add_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x98]
+
+s_lshl3_add_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x98,0x73,0x72,0x71,0x3f]
+
+s_lshl3_add_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x98,0x56,0x34,0x12,0xaf]
+
+s_lshl4_add_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x98]
+
+s_lshl4_add_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x98]
+
+s_lshl4_add_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x98]
+
+s_lshl4_add_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x98]
+
+s_lshl4_add_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x98]
+
+s_lshl4_add_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x98]
+
+s_lshl4_add_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x98]
+
+s_lshl4_add_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x98]
+
+s_lshl4_add_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x98]
+
+s_lshl4_add_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x98]
+
+s_lshl4_add_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x98]
+
+s_lshl4_add_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x98]
+
+s_lshl4_add_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x98,0x73,0x72,0x71,0x3f]
+
+s_lshl4_add_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x98,0x56,0x34,0x12,0xaf]
+
+s_lshl4_add_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x98]
+
+s_lshl4_add_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x98,0x73,0x72,0x71,0x3f]
+
+s_lshl4_add_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x98,0x56,0x34,0x12,0xaf]
+
+s_pack_ll_b32_b16 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x99]
+
+s_pack_ll_b32_b16 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x99]
+
+s_pack_ll_b32_b16 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x99]
+
+s_pack_ll_b32_b16 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x99]
+
+s_pack_ll_b32_b16 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x99]
+
+s_pack_ll_b32_b16 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x99]
+
+s_pack_ll_b32_b16 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x99]
+
+s_pack_ll_b32_b16 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x99]
+
+s_pack_ll_b32_b16 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x99]
+
+s_pack_ll_b32_b16 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x99]
+
+s_pack_ll_b32_b16 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x99]
+
+s_pack_ll_b32_b16 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x99,0x73,0x72,0x71,0x3f]
+
+s_pack_ll_b32_b16 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x99,0x56,0x34,0x12,0xaf]
+
+s_pack_ll_b32_b16 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x99]
+
+s_pack_ll_b32_b16 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x99,0x73,0x72,0x71,0x3f]
+
+s_pack_ll_b32_b16 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x99,0x56,0x34,0x12,0xaf]
+
+s_pack_lh_b32_b16 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x99]
+
+s_pack_lh_b32_b16 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x99]
+
+s_pack_lh_b32_b16 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x99]
+
+s_pack_lh_b32_b16 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x99]
+
+s_pack_lh_b32_b16 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x99]
+
+s_pack_lh_b32_b16 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x99]
+
+s_pack_lh_b32_b16 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x99]
+
+s_pack_lh_b32_b16 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x99]
+
+s_pack_lh_b32_b16 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x99]
+
+s_pack_lh_b32_b16 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x99]
+
+s_pack_lh_b32_b16 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x99]
+
+s_pack_lh_b32_b16 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x99,0x73,0x72,0x71,0x3f]
+
+s_pack_lh_b32_b16 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x99,0x56,0x34,0x12,0xaf]
+
+s_pack_lh_b32_b16 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x99]
+
+s_pack_lh_b32_b16 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x99,0x73,0x72,0x71,0x3f]
+
+s_pack_lh_b32_b16 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x99,0x56,0x34,0x12,0xaf]
+
+s_pack_hh_b32_b16 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x9a]
+
+s_pack_hh_b32_b16 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x9a]
+
+s_pack_hh_b32_b16 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x9a]
+
+s_pack_hh_b32_b16 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x9a]
+
+s_pack_hh_b32_b16 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x9a]
+
+s_pack_hh_b32_b16 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x9a]
+
+s_pack_hh_b32_b16 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x9a]
+
+s_pack_hh_b32_b16 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x9a]
+
+s_pack_hh_b32_b16 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x9a]
+
+s_pack_hh_b32_b16 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x9a]
+
+s_pack_hh_b32_b16 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x9a]
+
+s_pack_hh_b32_b16 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x9a,0x73,0x72,0x71,0x3f]
+
+s_pack_hh_b32_b16 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x9a,0x56,0x34,0x12,0xaf]
+
+s_pack_hh_b32_b16 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x9a]
+
+s_pack_hh_b32_b16 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x9a,0x73,0x72,0x71,0x3f]
+
+s_pack_hh_b32_b16 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x9a,0x56,0x34,0x12,0xaf]
+
+s_mul_hi_u32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0xe9,0x9a]
+
+s_mul_hi_u32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x80,0x9a]
+
+s_mul_hi_u32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0xe9,0x9a]
+
+s_mul_hi_u32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0xe9,0x9a]
+
+s_mul_hi_u32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0xe9,0x9a]
+
+s_mul_hi_u32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x80,0x9a]
+
+s_mul_hi_u32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfe,0x9a]
+
+s_mul_hi_u32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xff,0x9a]
+
+s_mul_hi_u32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0xea,0x9a]
+
+s_mul_hi_u32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0xeb,0x9a]
+
+s_mul_hi_u32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0xfc,0x9a]
+
+s_mul_hi_u32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x80,0x9a]
+
+s_mul_hi_u32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x9a,0x73,0x72,0x71,0x3f]
+
+s_mul_hi_u32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x80,0x9a,0x56,0x34,0x12,0xaf]
+
+s_mul_hi_u32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x80,0x9a]
+
+s_mul_hi_u32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x80,0x9a,0x73,0x72,0x71,0x3f]
+
+s_mul_hi_u32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x80,0x9a,0x56,0x34,0x12,0xaf]
+
+s_mul_hi_i32 s0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s105, s104, s103
+// GFX10: encoding: [0x68,0x67,0x69,0x9b]
+
+s_mul_hi_i32 s0, s104, s103
+// GFX10: encoding: [0x68,0x67,0x00,0x9b]
+
+s_mul_hi_i32 s105, s1, s103
+// GFX10: encoding: [0x01,0x67,0x69,0x9b]
+
+s_mul_hi_i32 s105, s104, s2
+// GFX10: encoding: [0x68,0x02,0x69,0x9b]
+
+s_mul_hi_i32 s105, s1, s2
+// GFX10: encoding: [0x01,0x02,0x69,0x9b]
+
+s_mul_hi_i32 s0, s104, s2
+// GFX10: encoding: [0x68,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, s103
+// GFX10: encoding: [0x01,0x67,0x00,0x9b]
+
+s_mul_hi_i32 exec_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7e,0x9b]
+
+s_mul_hi_i32 exec_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7f,0x9b]
+
+s_mul_hi_i32 vcc_lo, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6a,0x9b]
+
+s_mul_hi_i32 vcc_hi, s1, s2
+// GFX10: encoding: [0x01,0x02,0x6b,0x9b]
+
+s_mul_hi_i32 m0, s1, s2
+// GFX10: encoding: [0x01,0x02,0x7c,0x9b]
+
+s_mul_hi_i32 s0, exec_lo, s2
+// GFX10: encoding: [0x7e,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, exec_hi, s2
+// GFX10: encoding: [0x7f,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, vcc_lo, s2
+// GFX10: encoding: [0x6a,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, vcc_hi, s2
+// GFX10: encoding: [0x6b,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, m0, s2
+// GFX10: encoding: [0x7c,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, 0, s2
+// GFX10: encoding: [0x80,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, -1, s2
+// GFX10: encoding: [0xc1,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, 0.5, s2
+// GFX10: encoding: [0xf0,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, -4.0, s2
+// GFX10: encoding: [0xf7,0x02,0x00,0x9b]
+
+s_mul_hi_i32 s0, 0x3f717273, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x9b,0x73,0x72,0x71,0x3f]
+
+s_mul_hi_i32 s0, 0xaf123456, s2
+// GFX10: encoding: [0xff,0x02,0x00,0x9b,0x56,0x34,0x12,0xaf]
+
+s_mul_hi_i32 s0, s1, exec_lo
+// GFX10: encoding: [0x01,0x7e,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, exec_hi
+// GFX10: encoding: [0x01,0x7f,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, vcc_lo
+// GFX10: encoding: [0x01,0x6a,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, vcc_hi
+// GFX10: encoding: [0x01,0x6b,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, m0
+// GFX10: encoding: [0x01,0x7c,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, 0
+// GFX10: encoding: [0x01,0x80,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, -1
+// GFX10: encoding: [0x01,0xc1,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, 0.5
+// GFX10: encoding: [0x01,0xf0,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, -4.0
+// GFX10: encoding: [0x01,0xf7,0x00,0x9b]
+
+s_mul_hi_i32 s0, s1, 0x3f717273
+// GFX10: encoding: [0x01,0xff,0x00,0x9b,0x73,0x72,0x71,0x3f]
+
+s_mul_hi_i32 s0, s1, 0xaf123456
+// GFX10: encoding: [0x01,0xff,0x00,0x9b,0x56,0x34,0x12,0xaf]
+
+//===----------------------------------------------------------------------===//
+// ENC_SOPC.
+//===----------------------------------------------------------------------===//
+
+s_cmp_eq_i32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x00,0xbf]
+
+s_cmp_eq_i32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x00,0xbf]
+
+s_cmp_eq_i32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x00,0xbf]
+
+s_cmp_eq_i32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x00,0xbf]
+
+s_cmp_eq_i32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x00,0xbf]
+
+s_cmp_eq_i32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x00,0xbf]
+
+s_cmp_eq_i32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x00,0xbf]
+
+s_cmp_eq_i32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x00,0xbf]
+
+s_cmp_eq_i32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x00,0xbf]
+
+s_cmp_eq_i32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x00,0xbf]
+
+s_cmp_eq_i32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x00,0xbf]
+
+s_cmp_eq_i32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x00,0xbf]
+
+s_cmp_eq_i32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x00,0xbf]
+
+s_cmp_eq_i32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x00,0xbf]
+
+s_cmp_eq_i32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x00,0xbf]
+
+s_cmp_eq_i32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x00,0xbf]
+
+s_cmp_eq_i32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x00,0xbf]
+
+s_cmp_eq_i32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x00,0xbf]
+
+s_cmp_eq_i32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_i32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_i32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x01,0xbf]
+
+s_cmp_lg_i32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x01,0xbf]
+
+s_cmp_lg_i32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x01,0xbf]
+
+s_cmp_lg_i32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x01,0xbf]
+
+s_cmp_lg_i32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x01,0xbf]
+
+s_cmp_lg_i32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x01,0xbf]
+
+s_cmp_lg_i32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x01,0xbf]
+
+s_cmp_lg_i32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x01,0xbf]
+
+s_cmp_lg_i32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x01,0xbf]
+
+s_cmp_lg_i32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x01,0xbf]
+
+s_cmp_lg_i32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x01,0xbf]
+
+s_cmp_lg_i32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x01,0xbf]
+
+s_cmp_lg_i32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x01,0xbf]
+
+s_cmp_lg_i32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x01,0xbf]
+
+s_cmp_lg_i32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x01,0xbf]
+
+s_cmp_lg_i32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x01,0xbf]
+
+s_cmp_lg_i32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x01,0xbf]
+
+s_cmp_lg_i32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x01,0xbf]
+
+s_cmp_lg_i32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_i32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_i32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x02,0xbf]
+
+s_cmp_gt_i32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x02,0xbf]
+
+s_cmp_gt_i32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x02,0xbf]
+
+s_cmp_gt_i32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x02,0xbf]
+
+s_cmp_gt_i32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x02,0xbf]
+
+s_cmp_gt_i32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x02,0xbf]
+
+s_cmp_gt_i32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x02,0xbf]
+
+s_cmp_gt_i32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x02,0xbf]
+
+s_cmp_gt_i32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x02,0xbf]
+
+s_cmp_gt_i32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x02,0xbf]
+
+s_cmp_gt_i32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x02,0xbf]
+
+s_cmp_gt_i32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x02,0xbf]
+
+s_cmp_gt_i32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x02,0xbf]
+
+s_cmp_gt_i32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x02,0xbf]
+
+s_cmp_gt_i32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x02,0xbf]
+
+s_cmp_gt_i32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x02,0xbf]
+
+s_cmp_gt_i32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x02,0xbf]
+
+s_cmp_gt_i32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x02,0xbf]
+
+s_cmp_gt_i32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_i32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_i32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x03,0xbf]
+
+s_cmp_ge_i32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x03,0xbf]
+
+s_cmp_ge_i32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x03,0xbf]
+
+s_cmp_ge_i32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x03,0xbf]
+
+s_cmp_ge_i32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x03,0xbf]
+
+s_cmp_ge_i32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x03,0xbf]
+
+s_cmp_ge_i32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x03,0xbf]
+
+s_cmp_ge_i32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x03,0xbf]
+
+s_cmp_ge_i32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x03,0xbf]
+
+s_cmp_ge_i32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x03,0xbf]
+
+s_cmp_ge_i32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x03,0xbf]
+
+s_cmp_ge_i32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x03,0xbf]
+
+s_cmp_ge_i32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x03,0xbf]
+
+s_cmp_ge_i32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x03,0xbf]
+
+s_cmp_ge_i32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x03,0xbf]
+
+s_cmp_ge_i32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x03,0xbf]
+
+s_cmp_ge_i32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x03,0xbf]
+
+s_cmp_ge_i32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x03,0xbf]
+
+s_cmp_ge_i32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_i32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_i32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x04,0xbf]
+
+s_cmp_lt_i32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x04,0xbf]
+
+s_cmp_lt_i32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x04,0xbf]
+
+s_cmp_lt_i32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x04,0xbf]
+
+s_cmp_lt_i32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x04,0xbf]
+
+s_cmp_lt_i32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x04,0xbf]
+
+s_cmp_lt_i32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x04,0xbf]
+
+s_cmp_lt_i32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x04,0xbf]
+
+s_cmp_lt_i32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x04,0xbf]
+
+s_cmp_lt_i32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x04,0xbf]
+
+s_cmp_lt_i32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x04,0xbf]
+
+s_cmp_lt_i32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x04,0xbf]
+
+s_cmp_lt_i32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x04,0xbf]
+
+s_cmp_lt_i32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x04,0xbf]
+
+s_cmp_lt_i32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x04,0xbf]
+
+s_cmp_lt_i32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x04,0xbf]
+
+s_cmp_lt_i32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x04,0xbf]
+
+s_cmp_lt_i32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x04,0xbf]
+
+s_cmp_lt_i32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_i32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_i32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x05,0xbf]
+
+s_cmp_le_i32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x05,0xbf]
+
+s_cmp_le_i32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x05,0xbf]
+
+s_cmp_le_i32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x05,0xbf]
+
+s_cmp_le_i32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x05,0xbf]
+
+s_cmp_le_i32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x05,0xbf]
+
+s_cmp_le_i32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x05,0xbf]
+
+s_cmp_le_i32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x05,0xbf]
+
+s_cmp_le_i32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x05,0xbf]
+
+s_cmp_le_i32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x05,0xbf]
+
+s_cmp_le_i32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x05,0xbf]
+
+s_cmp_le_i32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x05,0xbf]
+
+s_cmp_le_i32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x05,0xbf]
+
+s_cmp_le_i32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x05,0xbf]
+
+s_cmp_le_i32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x05,0xbf]
+
+s_cmp_le_i32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x05,0xbf]
+
+s_cmp_le_i32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x05,0xbf]
+
+s_cmp_le_i32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x05,0xbf]
+
+s_cmp_le_i32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_i32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x06,0xbf]
+
+s_cmp_eq_u32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x06,0xbf]
+
+s_cmp_eq_u32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x06,0xbf]
+
+s_cmp_eq_u32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x06,0xbf]
+
+s_cmp_eq_u32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x06,0xbf]
+
+s_cmp_eq_u32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x06,0xbf]
+
+s_cmp_eq_u32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x06,0xbf]
+
+s_cmp_eq_u32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x06,0xbf]
+
+s_cmp_eq_u32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x06,0xbf]
+
+s_cmp_eq_u32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x06,0xbf]
+
+s_cmp_eq_u32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x06,0xbf]
+
+s_cmp_eq_u32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x06,0xbf]
+
+s_cmp_eq_u32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x06,0xbf]
+
+s_cmp_eq_u32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x06,0xbf]
+
+s_cmp_eq_u32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x06,0xbf]
+
+s_cmp_eq_u32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x06,0xbf]
+
+s_cmp_eq_u32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x06,0xbf]
+
+s_cmp_eq_u32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x06,0xbf]
+
+s_cmp_eq_u32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x07,0xbf]
+
+s_cmp_lg_u32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x07,0xbf]
+
+s_cmp_lg_u32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x07,0xbf]
+
+s_cmp_lg_u32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x07,0xbf]
+
+s_cmp_lg_u32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x07,0xbf]
+
+s_cmp_lg_u32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x07,0xbf]
+
+s_cmp_lg_u32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x07,0xbf]
+
+s_cmp_lg_u32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x07,0xbf]
+
+s_cmp_lg_u32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x07,0xbf]
+
+s_cmp_lg_u32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x07,0xbf]
+
+s_cmp_lg_u32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x07,0xbf]
+
+s_cmp_lg_u32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x07,0xbf]
+
+s_cmp_lg_u32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x07,0xbf]
+
+s_cmp_lg_u32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x07,0xbf]
+
+s_cmp_lg_u32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x07,0xbf]
+
+s_cmp_lg_u32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x07,0xbf]
+
+s_cmp_lg_u32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x07,0xbf]
+
+s_cmp_lg_u32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x07,0xbf]
+
+s_cmp_lg_u32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_u32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x08,0xbf]
+
+s_cmp_gt_u32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x08,0xbf]
+
+s_cmp_gt_u32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x08,0xbf]
+
+s_cmp_gt_u32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x08,0xbf]
+
+s_cmp_gt_u32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x08,0xbf]
+
+s_cmp_gt_u32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x08,0xbf]
+
+s_cmp_gt_u32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x08,0xbf]
+
+s_cmp_gt_u32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x08,0xbf]
+
+s_cmp_gt_u32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x08,0xbf]
+
+s_cmp_gt_u32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x08,0xbf]
+
+s_cmp_gt_u32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x08,0xbf]
+
+s_cmp_gt_u32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x08,0xbf]
+
+s_cmp_gt_u32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x08,0xbf]
+
+s_cmp_gt_u32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x08,0xbf]
+
+s_cmp_gt_u32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x08,0xbf]
+
+s_cmp_gt_u32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x08,0xbf]
+
+s_cmp_gt_u32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x08,0xbf]
+
+s_cmp_gt_u32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x08,0xbf]
+
+s_cmp_gt_u32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_u32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_u32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x09,0xbf]
+
+s_cmp_ge_u32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x09,0xbf]
+
+s_cmp_ge_u32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x09,0xbf]
+
+s_cmp_ge_u32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x09,0xbf]
+
+s_cmp_ge_u32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x09,0xbf]
+
+s_cmp_ge_u32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x09,0xbf]
+
+s_cmp_ge_u32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x09,0xbf]
+
+s_cmp_ge_u32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x09,0xbf]
+
+s_cmp_ge_u32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x09,0xbf]
+
+s_cmp_ge_u32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x09,0xbf]
+
+s_cmp_ge_u32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x09,0xbf]
+
+s_cmp_ge_u32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x09,0xbf]
+
+s_cmp_ge_u32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x09,0xbf]
+
+s_cmp_ge_u32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x09,0xbf]
+
+s_cmp_ge_u32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x09,0xbf]
+
+s_cmp_ge_u32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x09,0xbf]
+
+s_cmp_ge_u32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x09,0xbf]
+
+s_cmp_ge_u32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x09,0xbf]
+
+s_cmp_ge_u32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_u32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_u32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x0a,0xbf]
+
+s_cmp_lt_u32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x0a,0xbf]
+
+s_cmp_lt_u32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x0a,0xbf]
+
+s_cmp_lt_u32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x0a,0xbf]
+
+s_cmp_lt_u32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x0a,0xbf]
+
+s_cmp_lt_u32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x0a,0xbf]
+
+s_cmp_lt_u32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x0a,0xbf]
+
+s_cmp_lt_u32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x0a,0xbf]
+
+s_cmp_lt_u32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_u32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_u32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x0b,0xbf]
+
+s_cmp_le_u32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x0b,0xbf]
+
+s_cmp_le_u32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x0b,0xbf]
+
+s_cmp_le_u32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x0b,0xbf]
+
+s_cmp_le_u32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x0b,0xbf]
+
+s_cmp_le_u32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x0b,0xbf]
+
+s_cmp_le_u32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x0b,0xbf]
+
+s_cmp_le_u32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x0b,0xbf]
+
+s_cmp_le_u32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x0b,0xbf]
+
+s_cmp_le_u32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x0b,0xbf]
+
+s_cmp_le_u32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x0b,0xbf]
+
+s_cmp_le_u32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x0b,0xbf]
+
+s_cmp_le_u32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x0b,0xbf]
+
+s_cmp_le_u32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x0b,0xbf]
+
+s_cmp_le_u32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x0b,0xbf]
+
+s_cmp_le_u32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x0b,0xbf]
+
+s_cmp_le_u32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x0b,0xbf]
+
+s_cmp_le_u32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x0b,0xbf]
+
+s_cmp_le_u32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_u32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x0c,0xbf]
+
+s_bitcmp0_b32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x0c,0xbf]
+
+s_bitcmp0_b32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x0c,0xbf]
+
+s_bitcmp0_b32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x0c,0xbf]
+
+s_bitcmp0_b32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x0c,0xbf]
+
+s_bitcmp0_b32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x0c,0xbf]
+
+s_bitcmp0_b32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x0c,0xbf]
+
+s_bitcmp0_b32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x0c,0xbf]
+
+s_bitcmp0_b32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b32 s0, s1
+// GFX10: encoding: [0x00,0x01,0x0d,0xbf]
+
+s_bitcmp1_b32 s105, s104
+// GFX10: encoding: [0x69,0x68,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, s104
+// GFX10: encoding: [0x00,0x68,0x0d,0xbf]
+
+s_bitcmp1_b32 s105, s1
+// GFX10: encoding: [0x69,0x01,0x0d,0xbf]
+
+s_bitcmp1_b32 exec_lo, s1
+// GFX10: encoding: [0x7e,0x01,0x0d,0xbf]
+
+s_bitcmp1_b32 exec_hi, s1
+// GFX10: encoding: [0x7f,0x01,0x0d,0xbf]
+
+s_bitcmp1_b32 vcc_lo, s1
+// GFX10: encoding: [0x6a,0x01,0x0d,0xbf]
+
+s_bitcmp1_b32 vcc_hi, s1
+// GFX10: encoding: [0x6b,0x01,0x0d,0xbf]
+
+s_bitcmp1_b32 m0, s1
+// GFX10: encoding: [0x7c,0x01,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, exec_lo
+// GFX10: encoding: [0x00,0x7e,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, exec_hi
+// GFX10: encoding: [0x00,0x7f,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, m0
+// GFX10: encoding: [0x00,0x7c,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, 0
+// GFX10: encoding: [0x00,0x80,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, -1
+// GFX10: encoding: [0x00,0xc1,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, 0.5
+// GFX10: encoding: [0x00,0xf0,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, -4.0
+// GFX10: encoding: [0x00,0xf7,0x0d,0xbf]
+
+s_bitcmp1_b32 s0, 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b32 s0, 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b64 s[0:1], s2
+// GFX10: encoding: [0x00,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 s[104:105], s102
+// GFX10: encoding: [0x68,0x66,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], s102
+// GFX10: encoding: [0x00,0x66,0x0e,0xbf]
+
+s_bitcmp0_b64 s[104:105], s2
+// GFX10: encoding: [0x68,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 exec, s2
+// GFX10: encoding: [0x7e,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 vcc, s2
+// GFX10: encoding: [0x6a,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], exec_lo
+// GFX10: encoding: [0x00,0x7e,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], exec_hi
+// GFX10: encoding: [0x00,0x7f,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], m0
+// GFX10: encoding: [0x00,0x7c,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], 0
+// GFX10: encoding: [0x00,0x80,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], -1
+// GFX10: encoding: [0x00,0xc1,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], 0.5
+// GFX10: encoding: [0x00,0xf0,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], -4.0
+// GFX10: encoding: [0x00,0xf7,0x0e,0xbf]
+
+s_bitcmp0_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b64 s[0:1], s2
+// GFX10: encoding: [0x00,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 s[104:105], s102
+// GFX10: encoding: [0x68,0x66,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], s102
+// GFX10: encoding: [0x00,0x66,0x0f,0xbf]
+
+s_bitcmp1_b64 s[104:105], s2
+// GFX10: encoding: [0x68,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 exec, s2
+// GFX10: encoding: [0x7e,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 vcc, s2
+// GFX10: encoding: [0x6a,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], exec_lo
+// GFX10: encoding: [0x00,0x7e,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], exec_hi
+// GFX10: encoding: [0x00,0x7f,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], vcc_lo
+// GFX10: encoding: [0x00,0x6a,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], vcc_hi
+// GFX10: encoding: [0x00,0x6b,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], m0
+// GFX10: encoding: [0x00,0x7c,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], 0
+// GFX10: encoding: [0x00,0x80,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], -1
+// GFX10: encoding: [0x00,0xc1,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], 0.5
+// GFX10: encoding: [0x00,0xf0,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], -4.0
+// GFX10: encoding: [0x00,0xf7,0x0f,0xbf]
+
+s_bitcmp1_b64 s[0:1], 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b64 s[0:1], 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u64 s[0:1], s[2:3]
+// GFX10: encoding: [0x00,0x02,0x12,0xbf]
+
+s_cmp_eq_u64 s[104:105], s[102:103]
+// GFX10: encoding: [0x68,0x66,0x12,0xbf]
+
+s_cmp_eq_u64 s[0:1], s[102:103]
+// GFX10: encoding: [0x00,0x66,0x12,0xbf]
+
+s_cmp_eq_u64 s[104:105], s[2:3]
+// GFX10: encoding: [0x68,0x02,0x12,0xbf]
+
+s_cmp_eq_u64 exec, s[2:3]
+// GFX10: encoding: [0x7e,0x02,0x12,0xbf]
+
+s_cmp_eq_u64 vcc, s[2:3]
+// GFX10: encoding: [0x6a,0x02,0x12,0xbf]
+
+s_cmp_eq_u64 s[0:1], exec
+// GFX10: encoding: [0x00,0x7e,0x12,0xbf]
+
+s_cmp_eq_u64 s[0:1], vcc
+// GFX10: encoding: [0x00,0x6a,0x12,0xbf]
+
+s_cmp_eq_u64 s[0:1], 0
+// GFX10: encoding: [0x00,0x80,0x12,0xbf]
+
+s_cmp_eq_u64 s[0:1], -1
+// GFX10: encoding: [0x00,0xc1,0x12,0xbf]
+
+s_cmp_eq_u64 s[0:1], 0.5
+// GFX10: encoding: [0x00,0xf0,0x12,0xbf]
+
+s_cmp_eq_u64 s[0:1], -4.0
+// GFX10: encoding: [0x00,0xf7,0x12,0xbf]
+
+s_cmp_eq_u64 s[0:1], 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x12,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u64 s[0:1], 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x12,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u64 s[0:1], s[2:3]
+// GFX10: encoding: [0x00,0x02,0x13,0xbf]
+
+s_cmp_lg_u64 s[104:105], s[102:103]
+// GFX10: encoding: [0x68,0x66,0x13,0xbf]
+
+s_cmp_lg_u64 s[0:1], s[102:103]
+// GFX10: encoding: [0x00,0x66,0x13,0xbf]
+
+s_cmp_lg_u64 s[104:105], s[2:3]
+// GFX10: encoding: [0x68,0x02,0x13,0xbf]
+
+s_cmp_lg_u64 exec, s[2:3]
+// GFX10: encoding: [0x7e,0x02,0x13,0xbf]
+
+s_cmp_lg_u64 vcc, s[2:3]
+// GFX10: encoding: [0x6a,0x02,0x13,0xbf]
+
+s_cmp_lg_u64 s[0:1], exec
+// GFX10: encoding: [0x00,0x7e,0x13,0xbf]
+
+s_cmp_lg_u64 s[0:1], vcc
+// GFX10: encoding: [0x00,0x6a,0x13,0xbf]
+
+s_cmp_lg_u64 s[0:1], 0
+// GFX10: encoding: [0x00,0x80,0x13,0xbf]
+
+s_cmp_lg_u64 s[0:1], -1
+// GFX10: encoding: [0x00,0xc1,0x13,0xbf]
+
+s_cmp_lg_u64 s[0:1], 0.5
+// GFX10: encoding: [0x00,0xf0,0x13,0xbf]
+
+s_cmp_lg_u64 s[0:1], -4.0
+// GFX10: encoding: [0x00,0xf7,0x13,0xbf]
+
+s_cmp_lg_u64 s[0:1], 0x3f717273
+// GFX10: encoding: [0x00,0xff,0x13,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u64 s[0:1], 0xaf123456
+// GFX10: encoding: [0x00,0xff,0x13,0xbf,0x56,0x34,0x12,0xaf]
+
+//===----------------------------------------------------------------------===//
+// ENC_SOPK.
+//===----------------------------------------------------------------------===//
+
+s_movk_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb0]
+
+s_movk_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb0]
+
+s_movk_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb0]
+
+s_movk_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb0]
+
+s_movk_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb0]
+
+s_movk_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb0]
+
+s_movk_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb0]
+
+s_movk_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb0]
+
+s_version 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xb0]
+
+s_version 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xb0]
+
+s_cmovk_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb1]
+
+s_cmovk_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb1]
+
+s_cmovk_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb1]
+
+s_cmovk_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb1]
+
+s_cmovk_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb1]
+
+s_cmovk_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb1]
+
+s_cmovk_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb1]
+
+s_cmovk_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb1]
+
+s_cmpk_eq_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xb1]
+
+s_cmpk_eq_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xb1]
+
+s_cmpk_eq_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xb1]
+
+s_cmpk_eq_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xb1]
+
+s_cmpk_eq_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xb1]
+
+s_cmpk_eq_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xb1]
+
+s_cmpk_eq_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xb1]
+
+s_cmpk_eq_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xb1]
+
+s_cmpk_lg_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb2]
+
+s_cmpk_lg_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb2]
+
+s_cmpk_lg_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb2]
+
+s_cmpk_lg_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb2]
+
+s_cmpk_lg_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb2]
+
+s_cmpk_lg_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb2]
+
+s_cmpk_lg_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb2]
+
+s_cmpk_lg_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb2]
+
+s_cmpk_gt_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xb2]
+
+s_cmpk_gt_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xb2]
+
+s_cmpk_gt_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xb2]
+
+s_cmpk_gt_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xb2]
+
+s_cmpk_gt_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xb2]
+
+s_cmpk_gt_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xb2]
+
+s_cmpk_gt_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xb2]
+
+s_cmpk_gt_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xb2]
+
+s_cmpk_ge_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb3]
+
+s_cmpk_ge_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb3]
+
+s_cmpk_ge_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb3]
+
+s_cmpk_ge_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb3]
+
+s_cmpk_ge_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb3]
+
+s_cmpk_ge_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb3]
+
+s_cmpk_ge_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb3]
+
+s_cmpk_ge_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb3]
+
+s_cmpk_lt_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xb3]
+
+s_cmpk_lt_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xb3]
+
+s_cmpk_lt_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xb3]
+
+s_cmpk_lt_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xb3]
+
+s_cmpk_lt_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xb3]
+
+s_cmpk_lt_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xb3]
+
+s_cmpk_lt_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xb3]
+
+s_cmpk_lt_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xb3]
+
+s_cmpk_le_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb4]
+
+s_cmpk_le_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb4]
+
+s_cmpk_le_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb4]
+
+s_cmpk_le_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb4]
+
+s_cmpk_le_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb4]
+
+s_cmpk_le_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb4]
+
+s_cmpk_le_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb4]
+
+s_cmpk_le_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb4]
+
+s_cmpk_eq_u32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xb4]
+
+s_cmpk_eq_u32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xb4]
+
+s_cmpk_eq_u32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xb4]
+
+s_cmpk_eq_u32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xb4]
+
+s_cmpk_eq_u32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xb4]
+
+s_cmpk_eq_u32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xb4]
+
+s_cmpk_eq_u32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xb4]
+
+s_cmpk_eq_u32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xb4]
+
+s_cmpk_lg_u32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb5]
+
+s_cmpk_lg_u32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb5]
+
+s_cmpk_lg_u32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb5]
+
+s_cmpk_lg_u32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb5]
+
+s_cmpk_lg_u32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb5]
+
+s_cmpk_lg_u32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb5]
+
+s_cmpk_lg_u32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb5]
+
+s_cmpk_lg_u32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb5]
+
+s_cmpk_gt_u32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xb5]
+
+s_cmpk_gt_u32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xb5]
+
+s_cmpk_gt_u32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xb5]
+
+s_cmpk_gt_u32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xb5]
+
+s_cmpk_gt_u32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xb5]
+
+s_cmpk_gt_u32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xb5]
+
+s_cmpk_gt_u32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xb5]
+
+s_cmpk_gt_u32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xb5]
+
+s_cmpk_ge_u32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb6]
+
+s_cmpk_ge_u32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb6]
+
+s_cmpk_ge_u32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb6]
+
+s_cmpk_ge_u32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb6]
+
+s_cmpk_ge_u32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb6]
+
+s_cmpk_ge_u32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb6]
+
+s_cmpk_ge_u32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb6]
+
+s_cmpk_ge_u32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb6]
+
+s_cmpk_lt_u32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xb6]
+
+s_cmpk_lt_u32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xb6]
+
+s_cmpk_lt_u32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xb6]
+
+s_cmpk_lt_u32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xb6]
+
+s_cmpk_lt_u32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xb6]
+
+s_cmpk_lt_u32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xb6]
+
+s_cmpk_lt_u32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xb6]
+
+s_cmpk_lt_u32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xb6]
+
+s_cmpk_le_u32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb7]
+
+s_cmpk_le_u32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb7]
+
+s_cmpk_le_u32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb7]
+
+s_cmpk_le_u32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb7]
+
+s_cmpk_le_u32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb7]
+
+s_cmpk_le_u32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb7]
+
+s_cmpk_le_u32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb7]
+
+s_cmpk_le_u32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb7]
+
+s_addk_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xb7]
+
+s_addk_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xb7]
+
+s_addk_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xb7]
+
+s_addk_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xb7]
+
+s_addk_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xb7]
+
+s_addk_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xb7]
+
+s_addk_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xb7]
+
+s_addk_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xb7]
+
+s_mulk_i32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb8]
+
+s_mulk_i32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb8]
+
+s_mulk_i32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb8]
+
+s_mulk_i32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb8]
+
+s_mulk_i32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb8]
+
+s_mulk_i32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb8]
+
+s_mulk_i32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb8]
+
+s_mulk_i32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb8]
+
+s_getreg_b32 s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xb9]
+
+s_getreg_b32 s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xb9]
+
+s_getreg_b32 s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xb9]
+
+s_getreg_b32 exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xb9]
+
+s_getreg_b32 exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xb9]
+
+s_getreg_b32 vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xb9]
+
+s_getreg_b32 vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xb9]
+
+s_getreg_b32 m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xb9]
+
+s_setreg_b32 0x1234, s0
+// GFX10: encoding: [0x34,0x12,0x80,0xb9]
+
+s_setreg_b32 0xc1d1, s0
+// GFX10: encoding: [0xd1,0xc1,0x80,0xb9]
+
+s_setreg_b32 0x1234, s105
+// GFX10: encoding: [0x34,0x12,0xe9,0xb9]
+
+s_setreg_b32 0x1234, exec_lo
+// GFX10: encoding: [0x34,0x12,0xfe,0xb9]
+
+s_setreg_b32 0x1234, exec_hi
+// GFX10: encoding: [0x34,0x12,0xff,0xb9]
+
+s_setreg_b32 0x1234, vcc_lo
+// GFX10: encoding: [0x34,0x12,0xea,0xb9]
+
+s_setreg_b32 0x1234, vcc_hi
+// GFX10: encoding: [0x34,0x12,0xeb,0xb9]
+
+s_setreg_b32 0x1234, m0
+// GFX10: encoding: [0x34,0x12,0xfc,0xb9]
+
+s_setreg_imm32_b32 0x1234, 0x11213141
+// GFX10: encoding: [0x34,0x12,0x80,0xba,0x41,0x31,0x21,0x11]
+
+s_setreg_imm32_b32 0xc1d1, 0x11213141
+// GFX10: encoding: [0xd1,0xc1,0x80,0xba,0x41,0x31,0x21,0x11]
+
+s_setreg_imm32_b32 0x1234, 0xa1b1c1d1
+// GFX10: encoding: [0x34,0x12,0x80,0xba,0xd1,0xc1,0xb1,0xa1]
+
+s_setreg_imm32_b32 0xc1d1, 0xa1b1c1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xba,0xd1,0xc1,0xb1,0xa1]
+
+s_call_b64 s[0:1], 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xbb]
+
+s_call_b64 s[0:1], 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xbb]
+
+s_call_b64 s[104:105], 0x1234
+// GFX10: encoding: [0x34,0x12,0x68,0xbb]
+
+s_call_b64 exec, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xbb]
+
+s_call_b64 vcc, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xbb]
+
+s_waitcnt_vscnt s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xbb]
+
+s_waitcnt_vscnt s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xbb]
+
+s_waitcnt_vscnt s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xbb]
+
+s_waitcnt_vscnt exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xbb]
+
+s_waitcnt_vscnt exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xbb]
+
+s_waitcnt_vscnt vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xbb]
+
+s_waitcnt_vscnt vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xbb]
+
+s_waitcnt_vscnt m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xbb]
+
+s_waitcnt_vmcnt s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xbc]
+
+s_waitcnt_vmcnt s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xbc]
+
+s_waitcnt_vmcnt s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xbc]
+
+s_waitcnt_vmcnt exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xbc]
+
+s_waitcnt_vmcnt exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xbc]
+
+s_waitcnt_vmcnt vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xbc]
+
+s_waitcnt_vmcnt vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xbc]
+
+s_waitcnt_vmcnt m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xbc]
+
+s_waitcnt_expcnt s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xbc]
+
+s_waitcnt_expcnt s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xbc]
+
+s_waitcnt_expcnt s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xbc]
+
+s_waitcnt_expcnt exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xbc]
+
+s_waitcnt_expcnt exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xbc]
+
+s_waitcnt_expcnt vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xbc]
+
+s_waitcnt_expcnt vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xbc]
+
+s_waitcnt_expcnt m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xbc]
+
+s_waitcnt_lgkmcnt s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xbd]
+
+s_waitcnt_lgkmcnt s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xbd]
+
+s_waitcnt_lgkmcnt s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xbd]
+
+s_waitcnt_lgkmcnt exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xbd]
+
+s_waitcnt_lgkmcnt exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xbd]
+
+s_waitcnt_lgkmcnt vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xbd]
+
+s_waitcnt_lgkmcnt vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xbd]
+
+s_waitcnt_lgkmcnt m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xbd]
+
+s_waitcnt_depctr 0xfffe
+// GFX10: encoding: [0xfe,0xff,0xa3,0xbf]
+
+s_waitcnt_depctr 0
+// GFX10: encoding: [0x00,0x00,0xa3,0xbf]
+
+s_wait_idle
+// GFX10: encoding: [0x00,0x00,0xa2,0xbf]
+
+s_subvector_loop_begin s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xbd]
+
+s_subvector_loop_begin s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xbd]
+
+s_subvector_loop_begin s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0xe9,0xbd]
+
+s_subvector_loop_begin exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfe,0xbd]
+
+s_subvector_loop_begin exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xff,0xbd]
+
+s_subvector_loop_begin vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0xea,0xbd]
+
+s_subvector_loop_begin vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0xeb,0xbd]
+
+s_subvector_loop_begin m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0xfc,0xbd]
+
+s_subvector_loop_end s0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x00,0xbe]
+
+s_subvector_loop_end s0, 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x00,0xbe]
+
+s_subvector_loop_end s105, 0x1234
+// GFX10: encoding: [0x34,0x12,0x69,0xbe]
+
+s_subvector_loop_end exec_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7e,0xbe]
+
+s_subvector_loop_end exec_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7f,0xbe]
+
+s_subvector_loop_end vcc_lo, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6a,0xbe]
+
+s_subvector_loop_end vcc_hi, 0x1234
+// GFX10: encoding: [0x34,0x12,0x6b,0xbe]
+
+s_subvector_loop_end m0, 0x1234
+// GFX10: encoding: [0x34,0x12,0x7c,0xbe]
+
+//===----------------------------------------------------------------------===//
+// ENC_SOPP.
+//===----------------------------------------------------------------------===//
+
+s_nop 0x0
+// GFX10: encoding: [0x00,0x00,0x80,0xbf]
+
+s_nop 0x1234
+// GFX10: encoding: [0x34,0x12,0x80,0xbf]
+
+s_nop 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x80,0xbf]
+
+s_endpgm
+// GFX10: encoding: [0x00,0x00,0x81,0xbf]
+
+s_branch 0x0
+// GFX10: encoding: [0x00,0x00,0x82,0xbf]
+
+s_branch 0x1234
+// GFX10: encoding: [0x34,0x12,0x82,0xbf]
+
+s_branch 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x82,0xbf]
+
+s_wakeup
+// GFX10: encoding: [0x00,0x00,0x83,0xbf]
+
+s_cbranch_scc0 0x0
+// GFX10: encoding: [0x00,0x00,0x84,0xbf]
+
+s_cbranch_scc0 0x1234
+// GFX10: encoding: [0x34,0x12,0x84,0xbf]
+
+s_cbranch_scc0 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x84,0xbf]
+
+s_cbranch_scc1 0x0
+// GFX10: encoding: [0x00,0x00,0x85,0xbf]
+
+s_cbranch_scc1 0x1234
+// GFX10: encoding: [0x34,0x12,0x85,0xbf]
+
+s_cbranch_scc1 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x85,0xbf]
+
+s_cbranch_vccz 0x0
+// GFX10: encoding: [0x00,0x00,0x86,0xbf]
+
+s_cbranch_vccz 0x1234
+// GFX10: encoding: [0x34,0x12,0x86,0xbf]
+
+s_cbranch_vccz 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x86,0xbf]
+
+s_cbranch_vccnz 0x0
+// GFX10: encoding: [0x00,0x00,0x87,0xbf]
+
+s_cbranch_vccnz 0x1234
+// GFX10: encoding: [0x34,0x12,0x87,0xbf]
+
+s_cbranch_vccnz 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x87,0xbf]
+
+s_cbranch_execz 0x0
+// GFX10: encoding: [0x00,0x00,0x88,0xbf]
+
+s_cbranch_execz 0x1234
+// GFX10: encoding: [0x34,0x12,0x88,0xbf]
+
+s_cbranch_execz 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x88,0xbf]
+
+s_cbranch_execnz 0x0
+// GFX10: encoding: [0x00,0x00,0x89,0xbf]
+
+s_cbranch_execnz 0x1234
+// GFX10: encoding: [0x34,0x12,0x89,0xbf]
+
+s_cbranch_execnz 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x89,0xbf]
+
+s_barrier
+// GFX10: encoding: [0x00,0x00,0x8a,0xbf]
+
+s_setkill 0x0
+// GFX10: encoding: [0x00,0x00,0x8b,0xbf]
+
+s_setkill 0x1234
+// GFX10: encoding: [0x34,0x12,0x8b,0xbf]
+
+s_setkill 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x8b,0xbf]
+
+s_waitcnt 0x0
+// GFX10: encoding: [0x00,0x00,0x8c,0xbf]
+
+s_waitcnt 0x1234
+// GFX10: encoding: [0x34,0x12,0x8c,0xbf]
+
+s_waitcnt 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x8c,0xbf]
+
+s_sethalt 0x0
+// GFX10: encoding: [0x00,0x00,0x8d,0xbf]
+
+s_sethalt 0x1234
+// GFX10: encoding: [0x34,0x12,0x8d,0xbf]
+
+s_sethalt 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x8d,0xbf]
+
+s_sleep 0x0
+// GFX10: encoding: [0x00,0x00,0x8e,0xbf]
+
+s_sleep 0x1234
+// GFX10: encoding: [0x34,0x12,0x8e,0xbf]
+
+s_sleep 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x8e,0xbf]
+
+s_setprio 0x0
+// GFX10: encoding: [0x00,0x00,0x8f,0xbf]
+
+s_setprio 0x1234
+// GFX10: encoding: [0x34,0x12,0x8f,0xbf]
+
+s_setprio 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x8f,0xbf]
+
+s_sendmsg 0x0
+// GFX10: encoding: [0x00,0x00,0x90,0xbf]
+
+s_sendmsg 0x1234
+// GFX10: encoding: [0x34,0x12,0x90,0xbf]
+
+s_sendmsg 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x90,0xbf]
+
+s_sendmsghalt 0x0
+// GFX10: encoding: [0x00,0x00,0x91,0xbf]
+
+s_sendmsghalt 0x1234
+// GFX10: encoding: [0x34,0x12,0x91,0xbf]
+
+s_sendmsghalt 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x91,0xbf]
+
+s_trap 0x0
+// GFX10: encoding: [0x00,0x00,0x92,0xbf]
+
+s_trap 0x1234
+// GFX10: encoding: [0x34,0x12,0x92,0xbf]
+
+s_trap 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x92,0xbf]
+
+s_icache_inv
+// GFX10: encoding: [0x00,0x00,0x93,0xbf]
+
+s_incperflevel 0x0
+// GFX10: encoding: [0x00,0x00,0x94,0xbf]
+
+s_incperflevel 0x1234
+// GFX10: encoding: [0x34,0x12,0x94,0xbf]
+
+s_incperflevel 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x94,0xbf]
+
+s_decperflevel 0x0
+// GFX10: encoding: [0x00,0x00,0x95,0xbf]
+
+s_decperflevel 0x1234
+// GFX10: encoding: [0x34,0x12,0x95,0xbf]
+
+s_decperflevel 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x95,0xbf]
+
+s_ttracedata
+// GFX10: encoding: [0x00,0x00,0x96,0xbf]
+
+s_cbranch_cdbgsys 0x0
+// GFX10: encoding: [0x00,0x00,0x97,0xbf]
+
+s_cbranch_cdbgsys 0x1234
+// GFX10: encoding: [0x34,0x12,0x97,0xbf]
+
+s_cbranch_cdbgsys 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x97,0xbf]
+
+s_cbranch_cdbguser 0x0
+// GFX10: encoding: [0x00,0x00,0x98,0xbf]
+
+s_cbranch_cdbguser 0x1234
+// GFX10: encoding: [0x34,0x12,0x98,0xbf]
+
+s_cbranch_cdbguser 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x98,0xbf]
+
+s_cbranch_cdbgsys_or_user 0x0
+// GFX10: encoding: [0x00,0x00,0x99,0xbf]
+
+s_cbranch_cdbgsys_or_user 0x1234
+// GFX10: encoding: [0x34,0x12,0x99,0xbf]
+
+s_cbranch_cdbgsys_or_user 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x99,0xbf]
+
+s_cbranch_cdbgsys_and_user 0x0
+// GFX10: encoding: [0x00,0x00,0x9a,0xbf]
+
+s_cbranch_cdbgsys_and_user 0x1234
+// GFX10: encoding: [0x34,0x12,0x9a,0xbf]
+
+s_cbranch_cdbgsys_and_user 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0x9a,0xbf]
+
+s_endpgm_saved
+// GFX10: encoding: [0x00,0x00,0x9b,0xbf]
+
+s_endpgm_ordered_ps_done
+// GFX10: encoding: [0x00,0x00,0x9e,0xbf]
+
+s_code_end
+// GFX10: encoding: [0x00,0x00,0x9f,0xbf]
+
+s_inst_prefetch 0x0
+// GFX10: encoding: [0x00,0x00,0xa0,0xbf]
+
+s_inst_prefetch 0x1234
+// GFX10: encoding: [0x34,0x12,0xa0,0xbf]
+
+s_inst_prefetch 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0xa0,0xbf]
+
+s_clause 0x0
+// GFX10: encoding: [0x00,0x00,0xa1,0xbf]
+
+s_clause 0x1234
+// GFX10: encoding: [0x34,0x12,0xa1,0xbf]
+
+s_clause 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0xa1,0xbf]
+
+s_round_mode 0x0
+// GFX10: encoding: [0x00,0x00,0xa4,0xbf]
+
+s_round_mode 0x1234
+// GFX10: encoding: [0x34,0x12,0xa4,0xbf]
+
+s_round_mode 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0xa4,0xbf]
+
+s_denorm_mode 0x0
+// GFX10: encoding: [0x00,0x00,0xa5,0xbf]
+
+s_denorm_mode 0x1234
+// GFX10: encoding: [0x34,0x12,0xa5,0xbf]
+
+s_denorm_mode 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0xa5,0xbf]
+
+s_ttracedata_imm 0x0
+// GFX10: encoding: [0x00,0x00,0xa8,0xbf]
+
+s_ttracedata_imm 0x1234
+// GFX10: encoding: [0x34,0x12,0xa8,0xbf]
+
+s_ttracedata_imm 0xc1d1
+// GFX10: encoding: [0xd1,0xc1,0xa8,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
new file mode 100644
index 0000000000000..205e7c1471ca4
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop1.s
@@ -0,0 +1,16229 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W64-ERR --implicit-check-not=error: %s
+
+//===----------------------------------------------------------------------===//
+// ENC_VOP1.
+//===----------------------------------------------------------------------===//
+
+v_nop_e32
+// GFX10: encoding: [0x00,0x00,0x00,0x7e]
+
+v_nop_e64
+// GFX10: encoding: [0x00,0x00,0x80,0xd5,0x00,0x00,0x00,0x00]
+
+v_mov_b32_e32 v5, v1
+// GFX10: encoding: [0x01,0x03,0x0a,0x7e]
+
+v_mov_b32_e32 v255, v1
+// GFX10: encoding: [0x01,0x03,0xfe,0x7f]
+
+v_mov_b32_e32 v5, v255
+// GFX10: encoding: [0xff,0x03,0x0a,0x7e]
+
+v_mov_b32_e32 v5, s1
+// GFX10: encoding: [0x01,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, s103
+// GFX10: encoding: [0x67,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, ttmp11
+// GFX10: encoding: [0x77,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, m0
+// GFX10: encoding: [0x7c,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, 0
+// GFX10: encoding: [0x80,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, -1
+// GFX10: encoding: [0xc1,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0x02,0x0a,0x7e]
+
+v_mov_b32_e32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x02,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_mov_b32_e32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x02,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_mov_b32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x01,0x01,0x00,0x00]
+
+v_mov_b32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x81,0xd5,0x01,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0xff,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x01,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x65,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x6a,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x6b,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x7c,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x7e,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x7f,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0x80,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0xc1,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0xf0,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x81,0xd5,0xf7,0x00,0x00,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_mov_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_mov_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_mov_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_mov_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_mov_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x02,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_readfirstlane_b32 s5, v1
+// GFX10: encoding: [0x01,0x05,0x0a,0x7e]
+
+v_readfirstlane_b32 s103, v1
+// GFX10: encoding: [0x01,0x05,0xce,0x7e]
+
+v_readfirstlane_b32 ttmp11, v1
+// GFX10: encoding: [0x01,0x05,0xee,0x7e]
+
+v_readfirstlane_b32 s5, v255
+// GFX10: encoding: [0xff,0x05,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, v[1:2]
+// GFX10: encoding: [0x01,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v255, v[1:2]
+// GFX10: encoding: [0x01,0x07,0xfe,0x7f]
+
+v_cvt_i32_f64_e32 v5, v[254:255]
+// GFX10: encoding: [0xfe,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, s[2:3]
+// GFX10: encoding: [0x02,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, s[4:5]
+// GFX10: encoding: [0x04,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, s[102:103]
+// GFX10: encoding: [0x66,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, vcc
+// GFX10: encoding: [0x6a,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, ttmp[10:11]
+// GFX10: encoding: [0x76,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, exec
+// GFX10: encoding: [0x7e,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, 0
+// GFX10: encoding: [0x80,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, -1
+// GFX10: encoding: [0xc1,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64_e32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x06,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f64_e32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x06,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_i32_f64_e64 v5, v[1:2]
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v255, v[1:2]
+// GFX10: encoding: [0xff,0x00,0x83,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[254:255]
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0xfe,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[2:3]
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x02,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[4:5]
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x04,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[100:101]
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x64,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, vcc
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, exec
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -v[1:2]
+// GFX10: encoding: [0x05,0x00,0x83,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_i32_f64_e64 v5, |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0x83,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0x83,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e32 v[5:6], v1
+// GFX10: encoding: [0x01,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[254:255], v1
+// GFX10: encoding: [0x01,0x09,0xfc,0x7f]
+
+v_cvt_f64_i32_e32 v[5:6], v255
+// GFX10: encoding: [0xff,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], s1
+// GFX10: encoding: [0x01,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], s103
+// GFX10: encoding: [0x67,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], vcc_lo
+// GFX10: encoding: [0x6a,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], vcc_hi
+// GFX10: encoding: [0x6b,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], ttmp11
+// GFX10: encoding: [0x77,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], m0
+// GFX10: encoding: [0x7c,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], exec_lo
+// GFX10: encoding: [0x7e,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], exec_hi
+// GFX10: encoding: [0x7f,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], 0
+// GFX10: encoding: [0x80,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], -1
+// GFX10: encoding: [0xc1,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32_e32 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x08,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_i32_e32 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x08,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_i32_e64 v[5:6], v1
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[254:255], v1
+// GFX10: encoding: [0xfe,0x00,0x84,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v255
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s1
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s101
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_lo
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_hi
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], m0
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_lo
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_hi
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1 clamp
+// GFX10: encoding: [0x05,0x80,0x84,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_i32_e64 v[5:6], v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_i32_e64 v[5:6], v1 div:2
+// GFX10: encoding: [0x05,0x00,0x84,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_i32_e32 v5, v1
+// GFX10: encoding: [0x01,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v255, v1
+// GFX10: encoding: [0x01,0x0b,0xfe,0x7f]
+
+v_cvt_f32_i32_e32 v5, v255
+// GFX10: encoding: [0xff,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, s1
+// GFX10: encoding: [0x01,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, s103
+// GFX10: encoding: [0x67,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, ttmp11
+// GFX10: encoding: [0x77,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, m0
+// GFX10: encoding: [0x7c,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, 0
+// GFX10: encoding: [0x80,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, -1
+// GFX10: encoding: [0xc1,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32_e32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x0a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_i32_e32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x0a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_i32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x85,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x85,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_i32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_i32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0x85,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0a,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_f32_u32_e32 v5, v1
+// GFX10: encoding: [0x01,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v255, v1
+// GFX10: encoding: [0x01,0x0d,0xfe,0x7f]
+
+v_cvt_f32_u32_e32 v5, v255
+// GFX10: encoding: [0xff,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, s1
+// GFX10: encoding: [0x01,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, s103
+// GFX10: encoding: [0x67,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, ttmp11
+// GFX10: encoding: [0x77,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, m0
+// GFX10: encoding: [0x7c,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, 0
+// GFX10: encoding: [0x80,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, -1
+// GFX10: encoding: [0xc1,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32_e32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x0c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_u32_e32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x0c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_u32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x86,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x86,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_u32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_u32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0x86,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0c,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_u32_f32_e32 v5, v1
+// GFX10: encoding: [0x01,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v255, v1
+// GFX10: encoding: [0x01,0x0f,0xfe,0x7f]
+
+v_cvt_u32_f32_e32 v5, v255
+// GFX10: encoding: [0xff,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, s1
+// GFX10: encoding: [0x01,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, s103
+// GFX10: encoding: [0x67,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, ttmp11
+// GFX10: encoding: [0x77,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, m0
+// GFX10: encoding: [0x7c,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, 0
+// GFX10: encoding: [0x80,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, -1
+// GFX10: encoding: [0xc1,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32_e32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x0e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f32_e32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x0e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_u32_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x87,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0x87,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_u32_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0x87,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x87,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_u32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_u32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_u32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_u32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x0e,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_i32_f32_e32 v5, v1
+// GFX10: encoding: [0x01,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v255, v1
+// GFX10: encoding: [0x01,0x11,0xfe,0x7f]
+
+v_cvt_i32_f32_e32 v5, v255
+// GFX10: encoding: [0xff,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, s1
+// GFX10: encoding: [0x01,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, s103
+// GFX10: encoding: [0x67,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, ttmp11
+// GFX10: encoding: [0x77,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, m0
+// GFX10: encoding: [0x7c,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, 0
+// GFX10: encoding: [0x80,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, -1
+// GFX10: encoding: [0xc1,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32_e32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x10,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f32_e32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x10,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_i32_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x88,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0x88,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_i32_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0x88,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x88,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x10,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_f16_f32 v5, v1
+// GFX10: encoding: [0x01,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v255, v1
+// GFX10: encoding: [0x01,0x15,0xfe,0x7f]
+
+v_cvt_f16_f32 v5, v255
+// GFX10: encoding: [0xff,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s1
+// GFX10: encoding: [0x01,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s103
+// GFX10: encoding: [0x67,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, m0
+// GFX10: encoding: [0x7c,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0
+// GFX10: encoding: [0x80,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, -1
+// GFX10: encoding: [0xc1,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x14,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f16_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x14,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f16_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x8a,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_f16_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0x8a,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x8a,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f16_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f16_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0x8a,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f16_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_f16_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x14,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_f32_f16 v5, v1
+// GFX10: encoding: [0x01,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v255, v1
+// GFX10: encoding: [0x01,0x17,0xfe,0x7f]
+
+v_cvt_f32_f16 v5, v255
+// GFX10: encoding: [0xff,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s1
+// GFX10: encoding: [0x01,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s103
+// GFX10: encoding: [0x67,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, ttmp11
+// GFX10: encoding: [0x77,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, m0
+// GFX10: encoding: [0x7c,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_lo
+// GFX10: encoding: [0x7e,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_hi
+// GFX10: encoding: [0x7f,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, 0
+// GFX10: encoding: [0x80,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, -1
+// GFX10: encoding: [0xc1,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x8b,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_f32_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0x8b,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x8b,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_f16_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_f16_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0x8b,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_f32_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x16,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_rpi_i32_f32 v5, v1
+// GFX10: encoding: [0x01,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v255, v1
+// GFX10: encoding: [0x01,0x19,0xfe,0x7f]
+
+v_cvt_rpi_i32_f32 v5, v255
+// GFX10: encoding: [0xff,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s1
+// GFX10: encoding: [0x01,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s103
+// GFX10: encoding: [0x67,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, m0
+// GFX10: encoding: [0x7c,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0
+// GFX10: encoding: [0x80,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, -1
+// GFX10: encoding: [0xc1,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x18,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_rpi_i32_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x18,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_rpi_i32_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x8c,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0x8c,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_rpi_i32_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0x8c,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x8c,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x18,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_flr_i32_f32 v5, v1
+// GFX10: encoding: [0x01,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v255, v1
+// GFX10: encoding: [0x01,0x1b,0xfe,0x7f]
+
+v_cvt_flr_i32_f32 v5, v255
+// GFX10: encoding: [0xff,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s1
+// GFX10: encoding: [0x01,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s103
+// GFX10: encoding: [0x67,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, m0
+// GFX10: encoding: [0x7c,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0
+// GFX10: encoding: [0x80,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, -1
+// GFX10: encoding: [0xc1,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x1a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_flr_i32_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x1a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_flr_i32_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x8d,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0x8d,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_flr_i32_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0x8d,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x8d,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1a,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_off_f32_i4 v5, v1
+// GFX10: encoding: [0x01,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v255, v1
+// GFX10: encoding: [0x01,0x1d,0xfe,0x7f]
+
+v_cvt_off_f32_i4 v5, v255
+// GFX10: encoding: [0xff,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s1
+// GFX10: encoding: [0x01,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s103
+// GFX10: encoding: [0x67,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, ttmp11
+// GFX10: encoding: [0x77,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, m0
+// GFX10: encoding: [0x7c,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_lo
+// GFX10: encoding: [0x7e,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_hi
+// GFX10: encoding: [0x7f,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0
+// GFX10: encoding: [0x80,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, -1
+// GFX10: encoding: [0xc1,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0.5
+// GFX10: encoding: [0xf0,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, -4.0
+// GFX10: encoding: [0xf7,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0x4f
+// GFX10: encoding: [0xff,0x1c,0x0a,0x7e,0x4f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4 v5, 0x41
+// GFX10: encoding: [0xff,0x1c,0x0a,0x7e,0x41,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x8e,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x8e,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_off_f32_i4_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_off_f32_i4_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0x8e,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x1c,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_f32_f64 v5, v[1:2]
+// GFX10: encoding: [0x01,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v255, v[1:2]
+// GFX10: encoding: [0x01,0x1f,0xfe,0x7f]
+
+v_cvt_f32_f64 v5, v[254:255]
+// GFX10: encoding: [0xfe,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[2:3]
+// GFX10: encoding: [0x02,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[4:5]
+// GFX10: encoding: [0x04,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[102:103]
+// GFX10: encoding: [0x66,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, vcc
+// GFX10: encoding: [0x6a,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, ttmp[10:11]
+// GFX10: encoding: [0x76,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, exec
+// GFX10: encoding: [0x7e,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0
+// GFX10: encoding: [0x80,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, -1
+// GFX10: encoding: [0xc1,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0.5
+// GFX10: encoding: [0xf0,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, -4.0
+// GFX10: encoding: [0xf7,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x1e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_f64 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x1e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_f64_e64 v5, v[1:2]
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v255, v[1:2]
+// GFX10: encoding: [0xff,0x00,0x8f,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[254:255]
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0xfe,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[2:3]
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x02,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[4:5]
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x04,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[100:101]
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x64,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, vcc
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, exec
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -v[1:2]
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_f32_f64_e64 v5, |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0x8f,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0x8f,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_f64_e64 v5, v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_f64_e64 v5, v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0x8f,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f64_f32 v[5:6], v1
+// GFX10: encoding: [0x01,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[254:255], v1
+// GFX10: encoding: [0x01,0x21,0xfc,0x7f]
+
+v_cvt_f64_f32 v[5:6], v255
+// GFX10: encoding: [0xff,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s1
+// GFX10: encoding: [0x01,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s103
+// GFX10: encoding: [0x67,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_lo
+// GFX10: encoding: [0x6a,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_hi
+// GFX10: encoding: [0x6b,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], ttmp11
+// GFX10: encoding: [0x77,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], m0
+// GFX10: encoding: [0x7c,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_lo
+// GFX10: encoding: [0x7e,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_hi
+// GFX10: encoding: [0x7f,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0
+// GFX10: encoding: [0x80,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], -1
+// GFX10: encoding: [0xc1,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x20,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_f32 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x20,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_f32_e64 v[5:6], v1
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[254:255], v1
+// GFX10: encoding: [0xfe,0x00,0x90,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v255
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s1
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s101
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_lo
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_hi
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], m0
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_lo
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_hi
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -v1
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_f64_f32_e64 v[5:6], |v1|
+// GFX10: encoding: [0x05,0x01,0x90,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v1 clamp
+// GFX10: encoding: [0x05,0x80,0x90,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_f32_e64 v[5:6], v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_f32_e64 v[5:6], v1 div:2
+// GFX10: encoding: [0x05,0x00,0x90,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte0 v5, v1
+// GFX10: encoding: [0x01,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v255, v1
+// GFX10: encoding: [0x01,0x23,0xfe,0x7f]
+
+v_cvt_f32_ubyte0 v5, v255
+// GFX10: encoding: [0xff,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s1
+// GFX10: encoding: [0x01,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s103
+// GFX10: encoding: [0x67,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, ttmp11
+// GFX10: encoding: [0x77,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, m0
+// GFX10: encoding: [0x7c,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_lo
+// GFX10: encoding: [0x7e,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_hi
+// GFX10: encoding: [0x7f,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0
+// GFX10: encoding: [0x80,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, -1
+// GFX10: encoding: [0xc1,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0.5
+// GFX10: encoding: [0xf0,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, -4.0
+// GFX10: encoding: [0xf7,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x22,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte0 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x22,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte0_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x91,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x91,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte0_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte0_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0x91,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x22,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_f32_ubyte1 v5, v1
+// GFX10: encoding: [0x01,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v255, v1
+// GFX10: encoding: [0x01,0x25,0xfe,0x7f]
+
+v_cvt_f32_ubyte1 v5, v255
+// GFX10: encoding: [0xff,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s1
+// GFX10: encoding: [0x01,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s103
+// GFX10: encoding: [0x67,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, ttmp11
+// GFX10: encoding: [0x77,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, m0
+// GFX10: encoding: [0x7c,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_lo
+// GFX10: encoding: [0x7e,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_hi
+// GFX10: encoding: [0x7f,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0
+// GFX10: encoding: [0x80,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, -1
+// GFX10: encoding: [0xc1,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0.5
+// GFX10: encoding: [0xf0,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, -4.0
+// GFX10: encoding: [0xf7,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x24,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte1 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x24,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte1_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x92,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x92,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte1_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte1_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0x92,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x24,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_f32_ubyte2 v5, v1
+// GFX10: encoding: [0x01,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v255, v1
+// GFX10: encoding: [0x01,0x27,0xfe,0x7f]
+
+v_cvt_f32_ubyte2 v5, v255
+// GFX10: encoding: [0xff,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s1
+// GFX10: encoding: [0x01,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s103
+// GFX10: encoding: [0x67,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, ttmp11
+// GFX10: encoding: [0x77,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, m0
+// GFX10: encoding: [0x7c,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_lo
+// GFX10: encoding: [0x7e,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_hi
+// GFX10: encoding: [0x7f,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0
+// GFX10: encoding: [0x80,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, -1
+// GFX10: encoding: [0xc1,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0.5
+// GFX10: encoding: [0xf0,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, -4.0
+// GFX10: encoding: [0xf7,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x26,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte2 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x26,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte2_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x93,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x93,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte2_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte2_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0x93,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x26,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_f32_ubyte3 v5, v1
+// GFX10: encoding: [0x01,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v255, v1
+// GFX10: encoding: [0x01,0x29,0xfe,0x7f]
+
+v_cvt_f32_ubyte3 v5, v255
+// GFX10: encoding: [0xff,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s1
+// GFX10: encoding: [0x01,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s103
+// GFX10: encoding: [0x67,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, ttmp11
+// GFX10: encoding: [0x77,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, m0
+// GFX10: encoding: [0x7c,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_lo
+// GFX10: encoding: [0x7e,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_hi
+// GFX10: encoding: [0x7f,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0
+// GFX10: encoding: [0x80,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, -1
+// GFX10: encoding: [0xc1,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0.5
+// GFX10: encoding: [0xf0,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, -4.0
+// GFX10: encoding: [0xf7,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x28,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte3 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x28,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte3_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0x94,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0x94,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte3_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte3_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0x94,0xd5,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x28,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_u32_f64 v5, v[1:2]
+// GFX10: encoding: [0x01,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v255, v[1:2]
+// GFX10: encoding: [0x01,0x2b,0xfe,0x7f]
+
+v_cvt_u32_f64 v5, v[254:255]
+// GFX10: encoding: [0xfe,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[2:3]
+// GFX10: encoding: [0x02,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[4:5]
+// GFX10: encoding: [0x04,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[102:103]
+// GFX10: encoding: [0x66,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, vcc
+// GFX10: encoding: [0x6a,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, ttmp[10:11]
+// GFX10: encoding: [0x76,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, exec
+// GFX10: encoding: [0x7e,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0
+// GFX10: encoding: [0x80,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, -1
+// GFX10: encoding: [0xc1,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0.5
+// GFX10: encoding: [0xf0,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, -4.0
+// GFX10: encoding: [0xf7,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x2a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f64 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x2a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_u32_f64_e64 v5, v[1:2]
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v255, v[1:2]
+// GFX10: encoding: [0xff,0x00,0x95,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, v[254:255]
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0xfe,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[2:3]
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x02,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[4:5]
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x04,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[100:101]
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x64,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, vcc
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, exec
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -v[1:2]
+// GFX10: encoding: [0x05,0x00,0x95,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_u32_f64_e64 v5, |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0x95,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0x95,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32 v[5:6], v1
+// GFX10: encoding: [0x01,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[254:255], v1
+// GFX10: encoding: [0x01,0x2d,0xfc,0x7f]
+
+v_cvt_f64_u32 v[5:6], v255
+// GFX10: encoding: [0xff,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s1
+// GFX10: encoding: [0x01,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s103
+// GFX10: encoding: [0x67,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_lo
+// GFX10: encoding: [0x6a,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_hi
+// GFX10: encoding: [0x6b,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], ttmp11
+// GFX10: encoding: [0x77,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], m0
+// GFX10: encoding: [0x7c,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_lo
+// GFX10: encoding: [0x7e,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_hi
+// GFX10: encoding: [0x7f,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0
+// GFX10: encoding: [0x80,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], -1
+// GFX10: encoding: [0xc1,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x2c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_u32 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x2c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_u32_e64 v[5:6], v1
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[254:255], v1
+// GFX10: encoding: [0xfe,0x00,0x96,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v255
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s1
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s101
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_lo
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_hi
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], m0
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_lo
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_hi
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1 clamp
+// GFX10: encoding: [0x05,0x80,0x96,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1 mul:2
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_u32_e64 v[5:6], v1 mul:4
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_u32_e64 v[5:6], v1 div:2
+// GFX10: encoding: [0x05,0x00,0x96,0xd5,0x01,0x01,0x00,0x18]
+
+v_trunc_f64 v[5:6], v[1:2]
+// GFX10: encoding: [0x01,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[254:255], v[1:2]
+// GFX10: encoding: [0x01,0x2f,0xfc,0x7f]
+
+v_trunc_f64 v[5:6], v[254:255]
+// GFX10: encoding: [0xfe,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[2:3]
+// GFX10: encoding: [0x02,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[4:5]
+// GFX10: encoding: [0x04,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[102:103]
+// GFX10: encoding: [0x66,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], vcc
+// GFX10: encoding: [0x6a,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], ttmp[10:11]
+// GFX10: encoding: [0x76,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], exec
+// GFX10: encoding: [0x7e,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0
+// GFX10: encoding: [0x80,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], -1
+// GFX10: encoding: [0xc1,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x2e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_trunc_f64 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x2e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_trunc_f64_e64 v[5:6], v[1:2]
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[254:255], v[1:2]
+// GFX10: encoding: [0xfe,0x00,0x97,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0xfe,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[2:3]
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x02,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[4:5]
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x04,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[100:101]
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x64,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], vcc
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x6a,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], exec
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x7e,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x80,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0xc1,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0xf0,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0xf7,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -v[1:2]
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x20]
+
+v_trunc_f64_e64 v[5:6], |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0x97,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0x97,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x08]
+
+v_trunc_f64_e64 v[5:6], v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x10]
+
+v_trunc_f64_e64 v[5:6], v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0x97,0xd5,0x01,0x01,0x00,0x18]
+
+v_ceil_f64 v[5:6], v[1:2]
+// GFX10: encoding: [0x01,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[254:255], v[1:2]
+// GFX10: encoding: [0x01,0x31,0xfc,0x7f]
+
+v_ceil_f64 v[5:6], v[254:255]
+// GFX10: encoding: [0xfe,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[2:3]
+// GFX10: encoding: [0x02,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[4:5]
+// GFX10: encoding: [0x04,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[102:103]
+// GFX10: encoding: [0x66,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], vcc
+// GFX10: encoding: [0x6a,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], ttmp[10:11]
+// GFX10: encoding: [0x76,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], exec
+// GFX10: encoding: [0x7e,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0
+// GFX10: encoding: [0x80,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], -1
+// GFX10: encoding: [0xc1,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x30,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ceil_f64 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x30,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ceil_f64_e64 v[5:6], v[1:2]
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[254:255], v[1:2]
+// GFX10: encoding: [0xfe,0x00,0x98,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0xfe,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[2:3]
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x02,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[4:5]
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x04,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[100:101]
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x64,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], vcc
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], exec
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x80,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0xf7,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -v[1:2]
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x20]
+
+v_ceil_f64_e64 v[5:6], |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0x98,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0x98,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x08]
+
+v_ceil_f64_e64 v[5:6], v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x10]
+
+v_ceil_f64_e64 v[5:6], v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0x98,0xd5,0x01,0x01,0x00,0x18]
+
+v_rndne_f64 v[5:6], v[1:2]
+// GFX10: encoding: [0x01,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[254:255], v[1:2]
+// GFX10: encoding: [0x01,0x33,0xfc,0x7f]
+
+v_rndne_f64 v[5:6], v[254:255]
+// GFX10: encoding: [0xfe,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[2:3]
+// GFX10: encoding: [0x02,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[4:5]
+// GFX10: encoding: [0x04,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[102:103]
+// GFX10: encoding: [0x66,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], vcc
+// GFX10: encoding: [0x6a,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], ttmp[10:11]
+// GFX10: encoding: [0x76,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], exec
+// GFX10: encoding: [0x7e,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0
+// GFX10: encoding: [0x80,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], -1
+// GFX10: encoding: [0xc1,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x32,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rndne_f64 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x32,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rndne_f64_e64 v[5:6], v[1:2]
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[254:255], v[1:2]
+// GFX10: encoding: [0xfe,0x00,0x99,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0xfe,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[2:3]
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x02,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[4:5]
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x04,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[100:101]
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x64,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], vcc
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], exec
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x80,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -v[1:2]
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x20]
+
+v_rndne_f64_e64 v[5:6], v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0x99,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x08]
+
+v_rndne_f64_e64 v[5:6], v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x10]
+
+v_rndne_f64_e64 v[5:6], v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0x99,0xd5,0x01,0x01,0x00,0x18]
+
+v_floor_f64 v[5:6], v[1:2]
+// GFX10: encoding: [0x01,0x35,0x0a,0x7e]
+
+v_floor_f64 v[254:255], v[1:2]
+// GFX10: encoding: [0x01,0x35,0xfc,0x7f]
+
+v_floor_f64 v[5:6], v[254:255]
+// GFX10: encoding: [0xfe,0x35,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[2:3]
+// GFX10: encoding: [0x02,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[4:5]
+// GFX10: encoding: [0x04,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[102:103]
+// GFX10: encoding: [0x66,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], vcc
+// GFX10: encoding: [0x6a,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], ttmp[10:11]
+// GFX10: encoding: [0x76,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], exec
+// GFX10: encoding: [0x7e,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0
+// GFX10: encoding: [0x80,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], -1
+// GFX10: encoding: [0xc1,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x34,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_floor_f64 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x34,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_floor_f64_e64 v[5:6], v[1:2]
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[254:255], v[1:2]
+// GFX10: encoding: [0xfe,0x00,0x9a,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0xfe,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[2:3]
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x02,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[4:5]
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x04,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[100:101]
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x64,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], vcc
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x6a,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], exec
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x7e,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x80,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0xc1,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0xf0,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0xf7,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -v[1:2]
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x20]
+
+v_floor_f64_e64 v[5:6], v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0x9a,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x08]
+
+v_floor_f64_e64 v[5:6], v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x10]
+
+v_floor_f64_e64 v[5:6], v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0x9a,0xd5,0x01,0x01,0x00,0x18]
+
+v_pipeflush
+// GFX10: encoding: [0x00,0x36,0x00,0x7e]
+
+v_pipeflush_e64
+// GFX10: encoding: [0x00,0x00,0x9b,0xd5,0x00,0x00,0x00,0x00]
+
+v_fract_f32 v5, v1
+// GFX10: encoding: [0x01,0x41,0x0a,0x7e]
+
+v_fract_f32 v255, v1
+// GFX10: encoding: [0x01,0x41,0xfe,0x7f]
+
+v_fract_f32 v5, v255
+// GFX10: encoding: [0xff,0x41,0x0a,0x7e]
+
+v_fract_f32 v5, s1
+// GFX10: encoding: [0x01,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, s103
+// GFX10: encoding: [0x67,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, m0
+// GFX10: encoding: [0x7c,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, 0
+// GFX10: encoding: [0x80,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, -1
+// GFX10: encoding: [0xc1,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x40,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_fract_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x40,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_fract_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xa0,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0xff,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x65,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x6a,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x6b,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x7c,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x7e,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x7f,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x80,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0xc1,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0xf0,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0xf7,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x20]
+
+v_fract_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xa0,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x08]
+
+v_fract_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x10]
+
+v_fract_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xa0,0xd5,0x01,0x01,0x00,0x18]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_fract_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_fract_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_fract_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_fract_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_fract_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_fract_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x40,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_trunc_f32 v5, v1
+// GFX10: encoding: [0x01,0x43,0x0a,0x7e]
+
+v_trunc_f32 v255, v1
+// GFX10: encoding: [0x01,0x43,0xfe,0x7f]
+
+v_trunc_f32 v5, v255
+// GFX10: encoding: [0xff,0x43,0x0a,0x7e]
+
+v_trunc_f32 v5, s1
+// GFX10: encoding: [0x01,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, s103
+// GFX10: encoding: [0x67,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, m0
+// GFX10: encoding: [0x7c,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, 0
+// GFX10: encoding: [0x80,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, -1
+// GFX10: encoding: [0xc1,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x42,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_trunc_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x42,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_trunc_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xa1,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0xff,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x65,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x6a,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x6b,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x7c,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x7e,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x7f,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x80,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0xc1,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0xf0,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0xf7,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x20]
+
+v_trunc_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xa1,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x08]
+
+v_trunc_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x10]
+
+v_trunc_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xa1,0xd5,0x01,0x01,0x00,0x18]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_trunc_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_trunc_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_trunc_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_trunc_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_trunc_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_trunc_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x42,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_ceil_f32 v5, v1
+// GFX10: encoding: [0x01,0x45,0x0a,0x7e]
+
+v_ceil_f32 v255, v1
+// GFX10: encoding: [0x01,0x45,0xfe,0x7f]
+
+v_ceil_f32 v5, v255
+// GFX10: encoding: [0xff,0x45,0x0a,0x7e]
+
+v_ceil_f32 v5, s1
+// GFX10: encoding: [0x01,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, s103
+// GFX10: encoding: [0x67,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, m0
+// GFX10: encoding: [0x7c,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, 0
+// GFX10: encoding: [0x80,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, -1
+// GFX10: encoding: [0xc1,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x44,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ceil_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x44,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ceil_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xa2,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0xff,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x65,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x80,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0xf7,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x20]
+
+v_ceil_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xa2,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x08]
+
+v_ceil_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x10]
+
+v_ceil_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xa2,0xd5,0x01,0x01,0x00,0x18]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ceil_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_ceil_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ceil_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ceil_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ceil_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ceil_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x44,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_rndne_f32 v5, v1
+// GFX10: encoding: [0x01,0x47,0x0a,0x7e]
+
+v_rndne_f32 v255, v1
+// GFX10: encoding: [0x01,0x47,0xfe,0x7f]
+
+v_rndne_f32 v5, v255
+// GFX10: encoding: [0xff,0x47,0x0a,0x7e]
+
+v_rndne_f32 v5, s1
+// GFX10: encoding: [0x01,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, s103
+// GFX10: encoding: [0x67,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, m0
+// GFX10: encoding: [0x7c,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, 0
+// GFX10: encoding: [0x80,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, -1
+// GFX10: encoding: [0xc1,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x46,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rndne_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x46,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rndne_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xa3,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0xff,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x65,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x80,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x20]
+
+v_rndne_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xa3,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x08]
+
+v_rndne_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x10]
+
+v_rndne_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xa3,0xd5,0x01,0x01,0x00,0x18]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rndne_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rndne_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rndne_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rndne_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rndne_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rndne_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x46,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_floor_f32 v5, v1
+// GFX10: encoding: [0x01,0x49,0x0a,0x7e]
+
+v_floor_f32 v255, v1
+// GFX10: encoding: [0x01,0x49,0xfe,0x7f]
+
+v_floor_f32 v5, v255
+// GFX10: encoding: [0xff,0x49,0x0a,0x7e]
+
+v_floor_f32 v5, s1
+// GFX10: encoding: [0x01,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, s103
+// GFX10: encoding: [0x67,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, m0
+// GFX10: encoding: [0x7c,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, 0
+// GFX10: encoding: [0x80,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, -1
+// GFX10: encoding: [0xc1,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x48,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_floor_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x48,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_floor_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xa4,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0xff,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x65,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x6a,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x6b,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x7c,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x7e,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x7f,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x80,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0xc1,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0xf0,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0xf7,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x20]
+
+v_floor_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xa4,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xa4,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x08]
+
+v_floor_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x10]
+
+v_floor_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xa4,0xd5,0x01,0x01,0x00,0x18]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_floor_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_floor_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_floor_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_floor_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_floor_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_floor_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x48,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_exp_f32 v5, v1
+// GFX10: encoding: [0x01,0x4b,0x0a,0x7e]
+
+v_exp_f32 v255, v1
+// GFX10: encoding: [0x01,0x4b,0xfe,0x7f]
+
+v_exp_f32 v5, v255
+// GFX10: encoding: [0xff,0x4b,0x0a,0x7e]
+
+v_exp_f32 v5, s1
+// GFX10: encoding: [0x01,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, s103
+// GFX10: encoding: [0x67,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, m0
+// GFX10: encoding: [0x7c,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, 0
+// GFX10: encoding: [0x80,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, -1
+// GFX10: encoding: [0xc1,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x4a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_exp_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x4a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_exp_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xa5,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0xff,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x65,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x6a,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x6b,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x7c,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x7e,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x7f,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x80,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0xc1,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0xf0,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0xf7,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x20]
+
+v_exp_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xa5,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xa5,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x08]
+
+v_exp_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x10]
+
+v_exp_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xa5,0xd5,0x01,0x01,0x00,0x18]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_exp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_exp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_exp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_exp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_exp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_exp_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4a,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_log_f32 v5, v1
+// GFX10: encoding: [0x01,0x4f,0x0a,0x7e]
+
+v_log_f32 v255, v1
+// GFX10: encoding: [0x01,0x4f,0xfe,0x7f]
+
+v_log_f32 v5, v255
+// GFX10: encoding: [0xff,0x4f,0x0a,0x7e]
+
+v_log_f32 v5, s1
+// GFX10: encoding: [0x01,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, s103
+// GFX10: encoding: [0x67,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, m0
+// GFX10: encoding: [0x7c,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, 0
+// GFX10: encoding: [0x80,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, -1
+// GFX10: encoding: [0xc1,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x4e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_log_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x4e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_log_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xa7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0xff,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x65,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x6a,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x6b,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x7c,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x7e,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x7f,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x80,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0xc1,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0xf0,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0xf7,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x20]
+
+v_log_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xa7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xa7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x08]
+
+v_log_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x10]
+
+v_log_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xa7,0xd5,0x01,0x01,0x00,0x18]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_log_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_log_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_log_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_log_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_log_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_log_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x4e,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_rcp_f32 v5, v1
+// GFX10: encoding: [0x01,0x55,0x0a,0x7e]
+
+v_rcp_f32 v255, v1
+// GFX10: encoding: [0x01,0x55,0xfe,0x7f]
+
+v_rcp_f32 v5, v255
+// GFX10: encoding: [0xff,0x55,0x0a,0x7e]
+
+v_rcp_f32 v5, s1
+// GFX10: encoding: [0x01,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, s103
+// GFX10: encoding: [0x67,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, m0
+// GFX10: encoding: [0x7c,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, 0
+// GFX10: encoding: [0x80,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, -1
+// GFX10: encoding: [0xc1,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x54,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x54,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xaa,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0xff,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x65,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x80,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x20]
+
+v_rcp_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xaa,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xaa,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x08]
+
+v_rcp_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x10]
+
+v_rcp_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xaa,0xd5,0x01,0x01,0x00,0x18]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rcp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rcp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rcp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rcp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rcp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rcp_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x54,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_rcp_iflag_f32 v5, v1
+// GFX10: encoding: [0x01,0x57,0x0a,0x7e]
+
+v_rcp_iflag_f32 v255, v1
+// GFX10: encoding: [0x01,0x57,0xfe,0x7f]
+
+v_rcp_iflag_f32 v5, v255
+// GFX10: encoding: [0xff,0x57,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s1
+// GFX10: encoding: [0x01,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s103
+// GFX10: encoding: [0x67,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, m0
+// GFX10: encoding: [0x7c,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0
+// GFX10: encoding: [0x80,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, -1
+// GFX10: encoding: [0xc1,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x56,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_iflag_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x56,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_iflag_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xab,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0xff,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x65,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x80,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x20]
+
+v_rcp_iflag_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xab,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xab,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x08]
+
+v_rcp_iflag_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x10]
+
+v_rcp_iflag_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xab,0xd5,0x01,0x01,0x00,0x18]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rcp_iflag_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rcp_iflag_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x56,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_rsq_f32 v5, v1
+// GFX10: encoding: [0x01,0x5d,0x0a,0x7e]
+
+v_rsq_f32 v255, v1
+// GFX10: encoding: [0x01,0x5d,0xfe,0x7f]
+
+v_rsq_f32 v5, v255
+// GFX10: encoding: [0xff,0x5d,0x0a,0x7e]
+
+v_rsq_f32 v5, s1
+// GFX10: encoding: [0x01,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, s103
+// GFX10: encoding: [0x67,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, m0
+// GFX10: encoding: [0x7c,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, 0
+// GFX10: encoding: [0x80,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, -1
+// GFX10: encoding: [0xc1,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x5c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x5c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xae,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0xff,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x65,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x80,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x20]
+
+v_rsq_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xae,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xae,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x08]
+
+v_rsq_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x10]
+
+v_rsq_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xae,0xd5,0x01,0x01,0x00,0x18]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rsq_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rsq_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rsq_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rsq_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rsq_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rsq_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x5c,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_rcp_f64 v[5:6], v[1:2]
+// GFX10: encoding: [0x01,0x5f,0x0a,0x7e]
+
+v_rcp_f64 v[254:255], v[1:2]
+// GFX10: encoding: [0x01,0x5f,0xfc,0x7f]
+
+v_rcp_f64 v[5:6], v[254:255]
+// GFX10: encoding: [0xfe,0x5f,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[2:3]
+// GFX10: encoding: [0x02,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[4:5]
+// GFX10: encoding: [0x04,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[102:103]
+// GFX10: encoding: [0x66,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], vcc
+// GFX10: encoding: [0x6a,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], ttmp[10:11]
+// GFX10: encoding: [0x76,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], exec
+// GFX10: encoding: [0x7e,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0
+// GFX10: encoding: [0x80,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], -1
+// GFX10: encoding: [0xc1,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x5e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_f64 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x5e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_f64_e64 v[5:6], v[1:2]
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[254:255], v[1:2]
+// GFX10: encoding: [0xfe,0x00,0xaf,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[254:255]
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0xfe,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[2:3]
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x02,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[4:5]
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x04,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[100:101]
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x64,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], vcc
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], exec
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x80,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -v[1:2]
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x20]
+
+v_rcp_f64_e64 v[5:6], |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0xaf,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0xaf,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x08]
+
+v_rcp_f64_e64 v[5:6], v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x10]
+
+v_rcp_f64_e64 v[5:6], v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0xaf,0xd5,0x01,0x01,0x00,0x18]
+
+v_rsq_f64 v[5:6], v[1:2]
+// GFX10: encoding: [0x01,0x63,0x0a,0x7e]
+
+v_rsq_f64 v[254:255], v[1:2]
+// GFX10: encoding: [0x01,0x63,0xfc,0x7f]
+
+v_rsq_f64 v[5:6], v[254:255]
+// GFX10: encoding: [0xfe,0x63,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[2:3]
+// GFX10: encoding: [0x02,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[4:5]
+// GFX10: encoding: [0x04,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[102:103]
+// GFX10: encoding: [0x66,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], vcc
+// GFX10: encoding: [0x6a,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], ttmp[10:11]
+// GFX10: encoding: [0x76,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], exec
+// GFX10: encoding: [0x7e,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0
+// GFX10: encoding: [0x80,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], -1
+// GFX10: encoding: [0xc1,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x62,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_f64 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x62,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_f64_e64 v[5:6], v[1:2]
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[254:255], v[1:2]
+// GFX10: encoding: [0xfe,0x00,0xb1,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[254:255]
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0xfe,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[2:3]
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x02,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[4:5]
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x04,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[100:101]
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x64,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], vcc
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], exec
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x80,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -v[1:2]
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x20]
+
+v_rsq_f64_e64 v[5:6], |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0xb1,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0xb1,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x08]
+
+v_rsq_f64_e64 v[5:6], v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x10]
+
+v_rsq_f64_e64 v[5:6], v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0xb1,0xd5,0x01,0x01,0x00,0x18]
+
+v_sqrt_f32 v5, v1
+// GFX10: encoding: [0x01,0x67,0x0a,0x7e]
+
+v_sqrt_f32 v255, v1
+// GFX10: encoding: [0x01,0x67,0xfe,0x7f]
+
+v_sqrt_f32 v5, v255
+// GFX10: encoding: [0xff,0x67,0x0a,0x7e]
+
+v_sqrt_f32 v5, s1
+// GFX10: encoding: [0x01,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, s103
+// GFX10: encoding: [0x67,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, m0
+// GFX10: encoding: [0x7c,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0
+// GFX10: encoding: [0x80,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, -1
+// GFX10: encoding: [0xc1,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x66,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x66,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sqrt_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xb3,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0xff,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x65,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x6b,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x80,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x20]
+
+v_sqrt_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xb3,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xb3,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x08]
+
+v_sqrt_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x10]
+
+v_sqrt_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xb3,0xd5,0x01,0x01,0x00,0x18]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sqrt_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sqrt_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x66,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_sqrt_f64 v[5:6], v[1:2]
+// GFX10: encoding: [0x01,0x69,0x0a,0x7e]
+
+v_sqrt_f64 v[254:255], v[1:2]
+// GFX10: encoding: [0x01,0x69,0xfc,0x7f]
+
+v_sqrt_f64 v[5:6], v[254:255]
+// GFX10: encoding: [0xfe,0x69,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[2:3]
+// GFX10: encoding: [0x02,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[4:5]
+// GFX10: encoding: [0x04,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[102:103]
+// GFX10: encoding: [0x66,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], vcc
+// GFX10: encoding: [0x6a,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], ttmp[10:11]
+// GFX10: encoding: [0x76,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], exec
+// GFX10: encoding: [0x7e,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0
+// GFX10: encoding: [0x80,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], -1
+// GFX10: encoding: [0xc1,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x68,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f64 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x68,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sqrt_f64_e64 v[5:6], v[1:2]
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[254:255], v[1:2]
+// GFX10: encoding: [0xfe,0x00,0xb4,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[254:255]
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0xfe,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[2:3]
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x02,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[4:5]
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x04,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[100:101]
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x64,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], vcc
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], exec
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x80,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -v[1:2]
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x20]
+
+v_sqrt_f64_e64 v[5:6], |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0xb4,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0xb4,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x08]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x10]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0xb4,0xd5,0x01,0x01,0x00,0x18]
+
+v_sin_f32 v5, v1
+// GFX10: encoding: [0x01,0x6b,0x0a,0x7e]
+
+v_sin_f32 v255, v1
+// GFX10: encoding: [0x01,0x6b,0xfe,0x7f]
+
+v_sin_f32 v5, v255
+// GFX10: encoding: [0xff,0x6b,0x0a,0x7e]
+
+v_sin_f32 v5, s1
+// GFX10: encoding: [0x01,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, s103
+// GFX10: encoding: [0x67,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, m0
+// GFX10: encoding: [0x7c,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, 0
+// GFX10: encoding: [0x80,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, -1
+// GFX10: encoding: [0xc1,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x6a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sin_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x6a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sin_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xb5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0xff,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x65,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x6b,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x7f,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x80,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0xf0,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0xf7,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x20]
+
+v_sin_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xb5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xb5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x08]
+
+v_sin_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x10]
+
+v_sin_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xb5,0xd5,0x01,0x01,0x00,0x18]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sin_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sin_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sin_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sin_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sin_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sin_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6a,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cos_f32 v5, v1
+// GFX10: encoding: [0x01,0x6d,0x0a,0x7e]
+
+v_cos_f32 v255, v1
+// GFX10: encoding: [0x01,0x6d,0xfe,0x7f]
+
+v_cos_f32 v5, v255
+// GFX10: encoding: [0xff,0x6d,0x0a,0x7e]
+
+v_cos_f32 v5, s1
+// GFX10: encoding: [0x01,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, s103
+// GFX10: encoding: [0x67,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, m0
+// GFX10: encoding: [0x7c,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, 0
+// GFX10: encoding: [0x80,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, -1
+// GFX10: encoding: [0xc1,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x6c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cos_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x6c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cos_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xb6,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0xff,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x65,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x80,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x20]
+
+v_cos_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xb6,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xb6,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x08]
+
+v_cos_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x10]
+
+v_cos_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xb6,0xd5,0x01,0x01,0x00,0x18]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cos_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cos_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6c,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cos_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cos_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cos_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cos_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6c,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_not_b32 v5, v1
+// GFX10: encoding: [0x01,0x6f,0x0a,0x7e]
+
+v_not_b32 v255, v1
+// GFX10: encoding: [0x01,0x6f,0xfe,0x7f]
+
+v_not_b32 v5, v255
+// GFX10: encoding: [0xff,0x6f,0x0a,0x7e]
+
+v_not_b32 v5, s1
+// GFX10: encoding: [0x01,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, s103
+// GFX10: encoding: [0x67,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, ttmp11
+// GFX10: encoding: [0x77,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, m0
+// GFX10: encoding: [0x7c,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, 0
+// GFX10: encoding: [0x80,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, -1
+// GFX10: encoding: [0xc1,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, 0.5
+// GFX10: encoding: [0xf0,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, -4.0
+// GFX10: encoding: [0xf7,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x6e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_not_b32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_not_b32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x01,0x01,0x00,0x00]
+
+v_not_b32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xb7,0xd5,0x01,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0xff,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x01,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x65,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x6a,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x6b,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x7c,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x7e,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x7f,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0x80,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0xc1,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0xf0,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xb7,0xd5,0xf7,0x00,0x00,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_not_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_not_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_not_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_not_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_not_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x6e,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_bfrev_b32 v5, v1
+// GFX10: encoding: [0x01,0x71,0x0a,0x7e]
+
+v_bfrev_b32 v255, v1
+// GFX10: encoding: [0x01,0x71,0xfe,0x7f]
+
+v_bfrev_b32 v5, v255
+// GFX10: encoding: [0xff,0x71,0x0a,0x7e]
+
+v_bfrev_b32 v5, s1
+// GFX10: encoding: [0x01,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, s103
+// GFX10: encoding: [0x67,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, ttmp11
+// GFX10: encoding: [0x77,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, m0
+// GFX10: encoding: [0x7c,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0
+// GFX10: encoding: [0x80,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, -1
+// GFX10: encoding: [0xc1,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0.5
+// GFX10: encoding: [0xf0,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, -4.0
+// GFX10: encoding: [0xf7,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x70,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_bfrev_b32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x70,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_bfrev_b32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xb8,0xd5,0x01,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0xff,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x01,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x65,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x6a,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x6b,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x7c,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x7e,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x7f,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0x80,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0xc1,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0xf0,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xb8,0xd5,0xf7,0x00,0x00,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_bfrev_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x70,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_bfrev_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_bfrev_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x70,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_ffbh_u32 v5, v1
+// GFX10: encoding: [0x01,0x73,0x0a,0x7e]
+
+v_ffbh_u32 v255, v1
+// GFX10: encoding: [0x01,0x73,0xfe,0x7f]
+
+v_ffbh_u32 v5, v255
+// GFX10: encoding: [0xff,0x73,0x0a,0x7e]
+
+v_ffbh_u32 v5, s1
+// GFX10: encoding: [0x01,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, s103
+// GFX10: encoding: [0x67,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, ttmp11
+// GFX10: encoding: [0x77,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, m0
+// GFX10: encoding: [0x7c,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0
+// GFX10: encoding: [0x80,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, -1
+// GFX10: encoding: [0xc1,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0.5
+// GFX10: encoding: [0xf0,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, -4.0
+// GFX10: encoding: [0xf7,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x72,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbh_u32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x72,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbh_u32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x01,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xb9,0xd5,0x01,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0xff,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x01,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x65,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0x80,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xb9,0xd5,0xf7,0x00,0x00,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ffbh_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ffbh_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ffbh_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x72,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_ffbl_b32 v5, v1
+// GFX10: encoding: [0x01,0x75,0x0a,0x7e]
+
+v_ffbl_b32 v255, v1
+// GFX10: encoding: [0x01,0x75,0xfe,0x7f]
+
+v_ffbl_b32 v5, v255
+// GFX10: encoding: [0xff,0x75,0x0a,0x7e]
+
+v_ffbl_b32 v5, s1
+// GFX10: encoding: [0x01,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, s103
+// GFX10: encoding: [0x67,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, ttmp11
+// GFX10: encoding: [0x77,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, m0
+// GFX10: encoding: [0x7c,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0
+// GFX10: encoding: [0x80,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, -1
+// GFX10: encoding: [0xc1,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0.5
+// GFX10: encoding: [0xf0,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, -4.0
+// GFX10: encoding: [0xf7,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x74,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbl_b32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x74,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbl_b32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x01,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xba,0xd5,0x01,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0xff,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x01,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x65,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0x80,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xba,0xd5,0xf7,0x00,0x00,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ffbl_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ffbl_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ffbl_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x74,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_ffbh_i32 v5, v1
+// GFX10: encoding: [0x01,0x77,0x0a,0x7e]
+
+v_ffbh_i32 v255, v1
+// GFX10: encoding: [0x01,0x77,0xfe,0x7f]
+
+v_ffbh_i32 v5, v255
+// GFX10: encoding: [0xff,0x77,0x0a,0x7e]
+
+v_ffbh_i32 v5, s1
+// GFX10: encoding: [0x01,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, s103
+// GFX10: encoding: [0x67,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, ttmp11
+// GFX10: encoding: [0x77,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, m0
+// GFX10: encoding: [0x7c,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0
+// GFX10: encoding: [0x80,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, -1
+// GFX10: encoding: [0xc1,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0.5
+// GFX10: encoding: [0xf0,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, -4.0
+// GFX10: encoding: [0xf7,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x76,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbh_i32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x76,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbh_i32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x01,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xbb,0xd5,0x01,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0xff,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x01,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x65,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0x80,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xbb,0xd5,0xf7,0x00,0x00,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ffbh_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ffbh_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ffbh_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x76,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_frexp_exp_i32_f64 v5, v[1:2]
+// GFX10: encoding: [0x01,0x79,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v255, v[1:2]
+// GFX10: encoding: [0x01,0x79,0xfe,0x7f]
+
+v_frexp_exp_i32_f64 v5, v[254:255]
+// GFX10: encoding: [0xfe,0x79,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[2:3]
+// GFX10: encoding: [0x02,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[4:5]
+// GFX10: encoding: [0x04,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[102:103]
+// GFX10: encoding: [0x66,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, vcc
+// GFX10: encoding: [0x6a,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, ttmp[10:11]
+// GFX10: encoding: [0x76,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, exec
+// GFX10: encoding: [0x7e,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0
+// GFX10: encoding: [0x80,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, -1
+// GFX10: encoding: [0xc1,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0.5
+// GFX10: encoding: [0xf0,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, -4.0
+// GFX10: encoding: [0xf7,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x78,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f64 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x78,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_exp_i32_f64_e64 v5, v[1:2]
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v255, v[1:2]
+// GFX10: encoding: [0xff,0x00,0xbc,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, v[254:255]
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0xfe,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[2:3]
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x02,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[4:5]
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x04,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[100:101]
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x64,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, vcc
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, exec
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -v[1:2]
+// GFX10: encoding: [0x05,0x00,0xbc,0xd5,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0xbc,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0xbc,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64 v[5:6], v[1:2]
+// GFX10: encoding: [0x01,0x7b,0x0a,0x7e]
+
+v_frexp_mant_f64 v[254:255], v[1:2]
+// GFX10: encoding: [0x01,0x7b,0xfc,0x7f]
+
+v_frexp_mant_f64 v[5:6], v[254:255]
+// GFX10: encoding: [0xfe,0x7b,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[2:3]
+// GFX10: encoding: [0x02,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[4:5]
+// GFX10: encoding: [0x04,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[102:103]
+// GFX10: encoding: [0x66,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], vcc
+// GFX10: encoding: [0x6a,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], ttmp[10:11]
+// GFX10: encoding: [0x76,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], exec
+// GFX10: encoding: [0x7e,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0
+// GFX10: encoding: [0x80,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], -1
+// GFX10: encoding: [0xc1,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x7a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f64 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x7a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2]
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[254:255], v[1:2]
+// GFX10: encoding: [0xfe,0x00,0xbd,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[254:255]
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0xfe,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[2:3]
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x02,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[4:5]
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x04,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[100:101]
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x64,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], vcc
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], exec
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -v[1:2]
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f64_e64 v[5:6], |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0xbd,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0xbd,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x08]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x10]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0xbd,0xd5,0x01,0x01,0x00,0x18]
+
+v_fract_f64 v[5:6], v[1:2]
+// GFX10: encoding: [0x01,0x7d,0x0a,0x7e]
+
+v_fract_f64 v[254:255], v[1:2]
+// GFX10: encoding: [0x01,0x7d,0xfc,0x7f]
+
+v_fract_f64 v[5:6], v[254:255]
+// GFX10: encoding: [0xfe,0x7d,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[2:3]
+// GFX10: encoding: [0x02,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[4:5]
+// GFX10: encoding: [0x04,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[102:103]
+// GFX10: encoding: [0x66,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], vcc
+// GFX10: encoding: [0x6a,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], ttmp[10:11]
+// GFX10: encoding: [0x76,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], exec
+// GFX10: encoding: [0x7e,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0
+// GFX10: encoding: [0x80,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], -1
+// GFX10: encoding: [0xc1,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0.5
+// GFX10: encoding: [0xf0,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], -4.0
+// GFX10: encoding: [0xf7,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0xaf123456
+// GFX10: encoding: [0xff,0x7c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_fract_f64 v[5:6], 0x3f717273
+// GFX10: encoding: [0xff,0x7c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_fract_f64_e64 v[5:6], v[1:2]
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[254:255], v[1:2]
+// GFX10: encoding: [0xfe,0x00,0xbe,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[254:255]
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0xfe,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[2:3]
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x02,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[4:5]
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x04,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[100:101]
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x64,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], vcc
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x6a,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], exec
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x7e,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], 0
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x80,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -1
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0xc1,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], 0.5
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0xf0,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -4.0
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0xf7,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -v[1:2]
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x20]
+
+v_fract_f64_e64 v[5:6], |v[1:2]|
+// GFX10: encoding: [0x05,0x01,0xbe,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[1:2] clamp
+// GFX10: encoding: [0x05,0x80,0xbe,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[1:2] mul:2
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x08]
+
+v_fract_f64_e64 v[5:6], v[1:2] mul:4
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x10]
+
+v_fract_f64_e64 v[5:6], v[1:2] div:2
+// GFX10: encoding: [0x05,0x00,0xbe,0xd5,0x01,0x01,0x00,0x18]
+
+v_frexp_exp_i32_f32 v5, v1
+// GFX10: encoding: [0x01,0x7f,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v255, v1
+// GFX10: encoding: [0x01,0x7f,0xfe,0x7f]
+
+v_frexp_exp_i32_f32 v5, v255
+// GFX10: encoding: [0xff,0x7f,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s1
+// GFX10: encoding: [0x01,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s103
+// GFX10: encoding: [0x67,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, m0
+// GFX10: encoding: [0x7c,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0
+// GFX10: encoding: [0x80,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, -1
+// GFX10: encoding: [0xc1,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x7e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x7e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_exp_i32_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xbf,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0xff,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x01,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x65,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x6b,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xbf,0xd5,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i32_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xbf,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xbf,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x7e,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_frexp_mant_f32 v5, v1
+// GFX10: encoding: [0x01,0x81,0x0a,0x7e]
+
+v_frexp_mant_f32 v255, v1
+// GFX10: encoding: [0x01,0x81,0xfe,0x7f]
+
+v_frexp_mant_f32 v5, v255
+// GFX10: encoding: [0xff,0x81,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s1
+// GFX10: encoding: [0x01,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s103
+// GFX10: encoding: [0x67,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, ttmp11
+// GFX10: encoding: [0x77,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, m0
+// GFX10: encoding: [0x7c,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_lo
+// GFX10: encoding: [0x7e,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_hi
+// GFX10: encoding: [0x7f,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0
+// GFX10: encoding: [0x80,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, -1
+// GFX10: encoding: [0xc1,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0.5
+// GFX10: encoding: [0xf0,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, -4.0
+// GFX10: encoding: [0xf7,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0xaf123456
+// GFX10: encoding: [0xff,0x80,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f32 v5, 0x3f717273
+// GFX10: encoding: [0xff,0x80,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_mant_f32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xc0,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0xff,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x65,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x6b,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f32_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xc0,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xc0,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1 mul:2
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x08]
+
+v_frexp_mant_f32_e64 v5, v1 mul:4
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x10]
+
+v_frexp_mant_f32_e64 v5, v1 div:2
+// GFX10: encoding: [0x05,0x00,0xc0,0xd5,0x01,0x01,0x00,0x18]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_mant_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_mant_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x80,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_clrexcp_e32
+// GFX10: encoding: [0x00,0x82,0x00,0x7e]
+
+v_clrexcp_e64
+// GFX10: encoding: [0x00,0x00,0xc1,0xd5,0x00,0x00,0x00,0x00]
+
+v_movreld_b32 v5, v1
+// GFX10: encoding: [0x01,0x85,0x0a,0x7e]
+
+v_movreld_b32 v255, v1
+// GFX10: encoding: [0x01,0x85,0xfe,0x7f]
+
+v_movreld_b32 v5, v255
+// GFX10: encoding: [0xff,0x85,0x0a,0x7e]
+
+v_movreld_b32 v5, m0
+// GFX10: encoding: [0x7c,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, 0
+// GFX10: encoding: [0x80,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, -1
+// GFX10: encoding: [0xc1,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, 0.5
+// GFX10: encoding: [0xf0,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, -4.0
+// GFX10: encoding: [0xf7,0x84,0x0a,0x7e]
+
+v_movreld_b32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0x01,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xc2,0xd5,0x01,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0x7c,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0x80,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xc1,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xf0,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xf7,0x00,0x00,0x00]
+
+v_movreld_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movreld_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00]
+
+v_movreld_b32_sdwa v0, 64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00]
+
+v_movreld_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrels_b32 v5, v1
+// GFX10: encoding: [0x01,0x87,0x0a,0x7e]
+
+v_movrels_b32 v255, v1
+// GFX10: encoding: [0x01,0x87,0xfe,0x7f]
+
+v_movrels_b32 v5, v255
+// GFX10: encoding: [0xff,0x87,0x0a,0x7e]
+
+v_movrels_b32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xc3,0xd5,0x01,0x01,0x00,0x00]
+
+v_movrels_b32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xc3,0xd5,0x01,0x01,0x00,0x00]
+
+v_movrels_b32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
+
+v_movrels_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movrels_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrels_b32_e32 v5, s1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrels_b32_e32 v5, 1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrels_b32_e64 v5, s1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrels_b32_e64 v5, 1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrels_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
+
+v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
+
+v_movrelsd_b32 v5, v1
+// GFX10: encoding: [0x01,0x89,0x0a,0x7e]
+
+v_movrelsd_b32 v255, v1
+// GFX10: encoding: [0x01,0x89,0xfe,0x7f]
+
+v_movrelsd_b32 v5, v255
+// GFX10: encoding: [0xff,0x89,0x0a,0x7e]
+
+v_movrelsd_b32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xc4,0xd5,0x01,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
+
+v_movrelsd_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movrelsd_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00]
+
+v_movrelsd_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrelsd_b32_e32 v5, s1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrelsd_b32_e32 v5, 1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrelsd_b32_e64 v5, s1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrelsd_b32_e64 v5, 1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrelsd_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
+
+v_movrelsd_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
+
+v_movrelsd_2_b32 v5, v1
+// GFX10: encoding: [0x01,0x91,0x0a,0x7e]
+
+v_movrelsd_2_b32 v255, v1
+// GFX10: encoding: [0x01,0x91,0xfe,0x7f]
+
+v_movrelsd_2_b32 v5, v255
+// GFX10: encoding: [0xff,0x91,0x0a,0x7e]
+
+v_movrelsd_2_b32_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00]
+
+v_movrelsd_2_b32_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00]
+
+v_movrelsd_2_b32_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
+
+v_movrelsd_2_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00]
+
+v_movrelsd_2_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00]
+
+v_movrelsd_2_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00]
+
+v_movrelsd_2_b32_e32 v5, s1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrelsd_2_b32_e32 v5, 1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrelsd_2_b32_e64 v5, s1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrelsd_2_b32_e64 v5, 1
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_movrelsd_2_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
+
+v_movrelsd_2_b32_sdwa v0, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
+
+v_movrelsd_2_b32_sdwa v0, null dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: source operand must be a VGPR
+
+v_cvt_f16_u16_e32 v5, v1
+// GFX10: encoding: [0x01,0xa1,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v255, v1
+// GFX10: encoding: [0x01,0xa1,0xfe,0x7f]
+
+v_cvt_f16_u16_e32 v5, v255
+// GFX10: encoding: [0xff,0xa1,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, s1
+// GFX10: encoding: [0x01,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, s101
+// GFX10: encoding: [0x65,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, 0
+// GFX10: encoding: [0x80,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xa0,0x0a,0x7e]
+
+v_cvt_f16_u16_e32 v5, 0.5
+// GFX10: encoding: [0xff,0xa0,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_u16_e32 v5, -4.0
+// GFX10: encoding: [0xff,0xa0,0x0a,0x7e,0x00,0xc4,0x00,0x00]
+
+v_cvt_f16_u16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xa0,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f16_u16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xa0,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd0,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0xff,0x00,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd0,0xd5,0xff,0x00,0x00,0x00,0x00,0xc4,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd0,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f16_u16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa0,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_u16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_u16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa0,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_f16_i16_e32 v5, v1
+// GFX10: encoding: [0x01,0xa3,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v255, v1
+// GFX10: encoding: [0x01,0xa3,0xfe,0x7f]
+
+v_cvt_f16_i16_e32 v5, v255
+// GFX10: encoding: [0xff,0xa3,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, s1
+// GFX10: encoding: [0x01,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, s101
+// GFX10: encoding: [0x65,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, 0
+// GFX10: encoding: [0x80,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xa2,0x0a,0x7e]
+
+v_cvt_f16_i16_e32 v5, 0.5
+// GFX10: encoding: [0xff,0xa2,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_i16_e32 v5, -4.0
+// GFX10: encoding: [0xff,0xa2,0x0a,0x7e,0x00,0xc4,0x00,0x00]
+
+v_cvt_f16_i16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xa2,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f16_i16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xa2,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd1,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0xff,0x00,0x00,0x00,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd1,0xd5,0xff,0x00,0x00,0x00,0x00,0xc4,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd1,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f16_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa2,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_i16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_i16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa2,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_u16_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xa5,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xa5,0xfe,0x7f]
+
+v_cvt_u16_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xa5,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xa4,0x0a,0x7e]
+
+v_cvt_u16_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xa4,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_u16_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xa4,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd2,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xd2,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_u16_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xd2,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd2,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_u16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_u16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa4,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_u16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa4,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_i16_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xa7,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xa7,0xfe,0x7f]
+
+v_cvt_i16_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xa7,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xa6,0x0a,0x7e]
+
+v_cvt_i16_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xa6,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_i16_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xa6,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xd3,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_i16_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xd3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa6,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa6,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_rcp_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xa9,0x0a,0x7e]
+
+v_rcp_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xa9,0xfe,0x7f]
+
+v_rcp_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xa9,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xa8,0x0a,0x7e]
+
+v_rcp_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xa8,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rcp_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xa8,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_rcp_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd4,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0xff,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x01,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x65,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x80,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xd4,0xd5,0x01,0x01,0x00,0x20]
+
+v_rcp_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xd4,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd4,0xd5,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rcp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rcp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xa8,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rcp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rcp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rcp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rcp_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xa8,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_sqrt_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xab,0x0a,0x7e]
+
+v_sqrt_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xab,0xfe,0x7f]
+
+v_sqrt_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xab,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xaa,0x0a,0x7e]
+
+v_sqrt_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xaa,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sqrt_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xaa,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0xff,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x01,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x65,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x6b,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x80,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xd5,0xd5,0x01,0x01,0x00,0x20]
+
+v_sqrt_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xd5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd5,0xd5,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sqrt_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sqrt_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xaa,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xaa,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_rsq_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xad,0x0a,0x7e]
+
+v_rsq_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xad,0xfe,0x7f]
+
+v_rsq_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xad,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xac,0x0a,0x7e]
+
+v_rsq_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xac,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rsq_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xac,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_rsq_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd6,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0xff,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x01,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x65,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x80,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xd6,0xd5,0x01,0x01,0x00,0x20]
+
+v_rsq_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xd6,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd6,0xd5,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rsq_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rsq_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xac,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rsq_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rsq_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rsq_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rsq_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xac,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_log_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xaf,0x0a,0x7e]
+
+v_log_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xaf,0xfe,0x7f]
+
+v_log_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xaf,0x0a,0x7e]
+
+v_log_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xae,0x0a,0x7e]
+
+v_log_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xae,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_log_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xae,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_log_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0xff,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x01,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x65,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x6a,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x6b,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x7c,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x7e,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x7f,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x80,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0xc1,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0xf0,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0xf7,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xd7,0xd5,0x01,0x01,0x00,0x20]
+
+v_log_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xd7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd7,0xd5,0x01,0x01,0x00,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_log_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_log_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xae,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_log_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_log_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_log_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_log_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xae,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_exp_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xb1,0x0a,0x7e]
+
+v_exp_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xb1,0xfe,0x7f]
+
+v_exp_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xb1,0x0a,0x7e]
+
+v_exp_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xb0,0x0a,0x7e]
+
+v_exp_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xb0,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_exp_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xb0,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_exp_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd8,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0xff,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x01,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x65,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x6a,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x6b,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x7c,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x7e,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x7f,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x80,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0xc1,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0xf0,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0xf7,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xd8,0xd5,0x01,0x01,0x00,0x20]
+
+v_exp_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xd8,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd8,0xd5,0x01,0x01,0x00,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_exp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_exp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb0,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_exp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_exp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_exp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_exp_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb0,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_frexp_mant_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xb3,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xb3,0xfe,0x7f]
+
+v_frexp_mant_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xb3,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xb2,0x0a,0x7e]
+
+v_frexp_mant_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xb2,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_frexp_mant_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xb2,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xd9,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0xff,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x01,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x65,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x6b,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xd9,0xd5,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xd9,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xd9,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_mant_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_mant_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb2,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb2,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_frexp_exp_i16_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xb5,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xb5,0xfe,0x7f]
+
+v_frexp_exp_i16_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xb5,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xb4,0x0a,0x7e]
+
+v_frexp_exp_i16_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xb4,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_frexp_exp_i16_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xb4,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xda,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0xff,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x01,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x65,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x6b,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xda,0xd5,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i16_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xda,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xda,0xd5,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb4,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb4,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_floor_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xb7,0x0a,0x7e]
+
+v_floor_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xb7,0xfe,0x7f]
+
+v_floor_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xb7,0x0a,0x7e]
+
+v_floor_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xb6,0x0a,0x7e]
+
+v_floor_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xb6,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_floor_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xb6,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_floor_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xdb,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0xff,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x01,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x65,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x6a,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x6b,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x7c,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x7e,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x7f,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x80,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0xc1,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0xf0,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0xf7,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xdb,0xd5,0x01,0x01,0x00,0x20]
+
+v_floor_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xdb,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xdb,0xd5,0x01,0x01,0x00,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_floor_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_floor_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb6,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_floor_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_floor_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_floor_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_floor_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb6,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_ceil_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xb9,0x0a,0x7e]
+
+v_ceil_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xb9,0xfe,0x7f]
+
+v_ceil_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xb9,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xb8,0x0a,0x7e]
+
+v_ceil_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xb8,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_ceil_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xb8,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_ceil_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0xff,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x01,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x65,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x6a,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x6b,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x7c,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x7e,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x7f,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x80,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0xc1,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0xf0,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0xf7,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x20]
+
+v_ceil_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xdc,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xdc,0xd5,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ceil_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_ceil_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xb8,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ceil_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ceil_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ceil_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ceil_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xb8,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_trunc_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xbb,0x0a,0x7e]
+
+v_trunc_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xbb,0xfe,0x7f]
+
+v_trunc_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xbb,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xba,0x0a,0x7e]
+
+v_trunc_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xba,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_trunc_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xba,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_trunc_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xdd,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0xff,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x01,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x65,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x6a,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x6b,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x7c,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x7e,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x7f,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x80,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0xc1,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0xf0,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0xf7,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xdd,0xd5,0x01,0x01,0x00,0x20]
+
+v_trunc_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xdd,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xdd,0xd5,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_trunc_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_trunc_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xba,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_trunc_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xba,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_rndne_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xbd,0x0a,0x7e]
+
+v_rndne_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xbd,0xfe,0x7f]
+
+v_rndne_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xbd,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xbc,0x0a,0x7e]
+
+v_rndne_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xbc,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rndne_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xbc,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_rndne_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xde,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0xff,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x01,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x65,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x6a,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x6b,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x7c,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x7e,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x7f,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x80,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0xc1,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0xf0,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0xf7,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xde,0xd5,0x01,0x01,0x00,0x20]
+
+v_rndne_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xde,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xde,0xd5,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rndne_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rndne_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbc,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rndne_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rndne_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rndne_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rndne_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbc,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_fract_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xbf,0x0a,0x7e]
+
+v_fract_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xbf,0xfe,0x7f]
+
+v_fract_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xbf,0x0a,0x7e]
+
+v_fract_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xbe,0x0a,0x7e]
+
+v_fract_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xbe,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_fract_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xbe,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_fract_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xdf,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0xff,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x01,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x65,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x6a,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x6b,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x7c,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x7e,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x7f,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x80,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0xc1,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0xf0,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0xf7,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xdf,0xd5,0x01,0x01,0x00,0x20]
+
+v_fract_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xdf,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xdf,0xd5,0x01,0x01,0x00,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_fract_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_fract_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xbe,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_fract_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_fract_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_fract_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_fract_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xbe,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_sin_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xc1,0x0a,0x7e]
+
+v_sin_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xc1,0xfe,0x7f]
+
+v_sin_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xc1,0x0a,0x7e]
+
+v_sin_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xc0,0x0a,0x7e]
+
+v_sin_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xc0,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sin_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xc0,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_sin_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xe0,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0xff,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x01,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x65,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x6a,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x6b,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x7c,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x7e,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x7f,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x80,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0xc1,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0xf0,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0xf7,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xe0,0xd5,0x01,0x01,0x00,0x20]
+
+v_sin_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xe0,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xe0,0xd5,0x01,0x01,0x00,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sin_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sin_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc0,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sin_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sin_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sin_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sin_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc0,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cos_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xc3,0x0a,0x7e]
+
+v_cos_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xc3,0xfe,0x7f]
+
+v_cos_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xc3,0x0a,0x7e]
+
+v_cos_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xc2,0x0a,0x7e]
+
+v_cos_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xc2,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cos_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xc2,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cos_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xe1,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0xff,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x01,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x65,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x80,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xe1,0xd5,0x01,0x01,0x00,0x20]
+
+v_cos_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xe1,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xe1,0xd5,0x01,0x01,0x00,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cos_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cos_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc2,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cos_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cos_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cos_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cos_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc2,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_norm_i16_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xc7,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xc7,0xfe,0x7f]
+
+v_cvt_norm_i16_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xc7,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xc6,0x0a,0x7e]
+
+v_cvt_norm_i16_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xc6,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_norm_i16_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xc6,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xe3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xe3,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_norm_i16_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xe3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xe3,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc6,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_norm_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc6,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_cvt_norm_u16_f16_e32 v5, v1
+// GFX10: encoding: [0x01,0xc9,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v255, v1
+// GFX10: encoding: [0x01,0xc9,0xfe,0x7f]
+
+v_cvt_norm_u16_f16_e32 v5, v255
+// GFX10: encoding: [0xff,0xc9,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, s1
+// GFX10: encoding: [0x01,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, s101
+// GFX10: encoding: [0x65,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, vcc_lo
+// GFX10: encoding: [0x6a,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, vcc_hi
+// GFX10: encoding: [0x6b,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, m0
+// GFX10: encoding: [0x7c,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, exec_lo
+// GFX10: encoding: [0x7e,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, exec_hi
+// GFX10: encoding: [0x7f,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, 0
+// GFX10: encoding: [0x80,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, -1
+// GFX10: encoding: [0xc1,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, 0.5
+// GFX10: encoding: [0xf0,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, -4.0
+// GFX10: encoding: [0xf7,0xc8,0x0a,0x7e]
+
+v_cvt_norm_u16_f16_e32 v5, 0xfe0b
+// GFX10: encoding: [0xff,0xc8,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_norm_u16_f16_e32 v5, 0x3456
+// GFX10: encoding: [0xff,0xc8,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, v1
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v255, v1
+// GFX10: encoding: [0xff,0x00,0xe4,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, v255
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0xff,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, s1
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x01,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, s101
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x65,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, vcc_lo
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x6a,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, vcc_hi
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x6b,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, m0
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x7c,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, exec_lo
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x7e,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, exec_hi
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x7f,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, 0
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x80,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, -1
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0xc1,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, 0.5
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0xf0,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, -4.0
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0xf7,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, -v1
+// GFX10: encoding: [0x05,0x00,0xe4,0xd5,0x01,0x01,0x00,0x20]
+
+v_cvt_norm_u16_f16_e64 v5, |v1|
+// GFX10: encoding: [0x05,0x01,0xe4,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, v1 clamp
+// GFX10: encoding: [0x05,0x80,0xe4,0xd5,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0xc8,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_norm_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x51,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x5f,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x61,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xc8,0x0a,0x7e,0x01,0x6f,0x01,0x00]
+
+v_swap_b32 v5, v1
+// GFX10: encoding: [0x01,0xcb,0x0a,0x7e]
+
+v_swap_b32 v255, v1
+// GFX10: encoding: [0x01,0xcb,0xfe,0x7f]
+
+v_swap_b32 v5, v255
+// GFX10: encoding: [0xff,0xcb,0x0a,0x7e]
+
+v_swaprel_b32 v5, v1
+// GFX10: encoding: [0x01,0xd1,0x0a,0x7e]
+
+v_swaprel_b32 v255, v1
+// GFX10: encoding: [0x01,0xd1,0xfe,0x7f]
+
+v_swaprel_b32 v5, v255
+// GFX10: encoding: [0xff,0xd1,0x0a,0x7e]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
new file mode 100644
index 0000000000000..40cb3aadc2503
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop2.s
@@ -0,0 +1,13092 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W64-ERR --implicit-check-not=error: %s
+
+//===----------------------------------------------------------------------===//
+// ENC_VOP2.
+//===----------------------------------------------------------------------===//
+
+v_cndmask_b32_e32 v5, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v255, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0xfe,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, v255, v2, vcc
+// W64: encoding: [0xff,0x05,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, 0, v2, vcc
+// W64: encoding: [0x80,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, -1, v2, vcc
+// W64: encoding: [0xc1,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, 0.5, v2, vcc
+// W64: encoding: [0xf0,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, -4.0, v2, vcc
+// W64: encoding: [0xf7,0x04,0x0a,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, v1, v255, vcc
+// W64: encoding: [0x01,0xff,0x0b,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e64 v5, v1, v2, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v255, v1, v2, s[6:7]
+// W64: encoding: [0xff,0x00,0x01,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v255, v2, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, 0, v2, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x80,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, -1, v2, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0xc1,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, 0.5, v2, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0xf0,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, -4.0, v2, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0xf7,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, v255, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, 0, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x01,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, -1, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x83,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, 0.5, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0xe1,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, -4.0, s[6:7]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0xef,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, v2, s[8:9]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x22,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, v2, s[100:101]
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x92,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, v2, vcc
+// W64: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v255, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0xfe,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, v255, v2, vcc_lo
+// W32: encoding: [0xff,0x05,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, 0, v2, vcc_lo
+// W32: encoding: [0x80,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, -1, v2, vcc_lo
+// W32: encoding: [0xc1,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, 0.5, v2, vcc_lo
+// W32: encoding: [0xf0,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, -4.0, v2, vcc_lo
+// W32: encoding: [0xf7,0x04,0x0a,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e32 v5, v1, v255, vcc_lo
+// W32: encoding: [0x01,0xff,0x0b,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cndmask_b32_e64 v5, v1, v2, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v255, v1, v2, s6
+// W32: encoding: [0xff,0x00,0x01,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v255, v2, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0xff,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, 0, v2, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x80,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, -1, v2, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0xc1,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, 0.5, v2, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0xf0,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, -4.0, v2, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0xf7,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, v255, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0xff,0x1b,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, 0, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x01,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, -1, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x83,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, 0.5, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0xe1,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, -4.0, s6
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0xef,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, v2, s8
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x22,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, v2, s100
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0x92,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cndmask_b32_e64 v5, v1, v2, vcc_lo
+// W32: encoding: [0x05,0x00,0x01,0xd5,0x01,0x05,0xaa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x06]
+
+v_add_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x07]
+
+v_add_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x06]
+
+v_add_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x06]
+
+v_add_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x06,0x56,0x34,0x12,0xaf]
+
+v_add_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x06,0x73,0x72,0x71,0x3f]
+
+v_add_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x06]
+
+v_add_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x03,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0xff,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x65,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x6a,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x6b,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x7c,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x7e,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x7f,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x80,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0xc1,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0xf0,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0xf7,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xff,0x03,0x00]
+
+v_add_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x00,0x00]
+
+v_add_f32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xcb,0x00,0x00]
+
+v_add_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xd5,0x00,0x00]
+
+v_add_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xd7,0x00,0x00]
+
+v_add_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xf9,0x00,0x00]
+
+v_add_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xfd,0x00,0x00]
+
+v_add_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xff,0x00,0x00]
+
+v_add_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x01,0x01,0x00]
+
+v_add_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x83,0x01,0x00]
+
+v_add_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xe1,0x01,0x00]
+
+v_add_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0xef,0x01,0x00]
+
+v_add_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x20]
+
+v_add_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x40]
+
+v_add_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x60]
+
+v_add_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x03,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x03,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x03,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x03,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x08]
+
+v_add_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x10]
+
+v_add_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x03,0xd5,0x01,0x05,0x02,0x18]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x07,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0xff,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x65,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x6a,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x6b,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x7c,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x7e,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x7f,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x06,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x26,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x46,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x86,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0xc6,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x00,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x01,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x02,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x03,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x04,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x05,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x0e,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x00,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x01,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x02,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x03,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x04,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x05,0x06]
+
+v_add_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x16,0x06]
+
+v_add_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x26,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x00]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x01]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x02]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x03]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x04]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x05]
+
+v_add_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x16]
+
+v_add_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x26]
+
+v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x00]
+
+v_add_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0x00]
+
+v_add_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0xff,0xe4,0x00,0x00]
+
+v_add_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x06,0x01,0xe4,0x00,0x00]
+
+v_add_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x10]
+
+v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x30]
+
+v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
+
+v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01]
+
+v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
+
+v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
+
+v_add_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
+
+v_add_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00]
+
+v_add_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00]
+
+v_add_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x40,0x00]
+
+v_add_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x80,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x51,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x5f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x61,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x06,0x01,0x6f,0x01,0x00]
+
+v_sub_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x08]
+
+v_sub_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x09]
+
+v_sub_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x08]
+
+v_sub_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x08]
+
+v_sub_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x08,0x56,0x34,0x12,0xaf]
+
+v_sub_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x08,0x73,0x72,0x71,0x3f]
+
+v_sub_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x08]
+
+v_sub_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x04,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0xff,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x65,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x6a,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x6b,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x7c,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x7e,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x7f,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x80,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0xc1,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0xf0,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0xf7,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xff,0x03,0x00]
+
+v_sub_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xcb,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xd5,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xd7,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xf9,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xfd,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xff,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x01,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x83,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xe1,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0xef,0x01,0x00]
+
+v_sub_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x20]
+
+v_sub_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x40]
+
+v_sub_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x60]
+
+v_sub_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x04,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x04,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x04,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x04,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x08]
+
+v_sub_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x10]
+
+v_sub_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x04,0xd5,0x01,0x05,0x02,0x18]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x09,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0xff,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x65,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x6a,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x6b,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x7c,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x7e,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x7f,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x08,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x26,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x46,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x86,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0xc6,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x00,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x01,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x02,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x03,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x04,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x05,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x0e,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x00,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x01,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x02,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x03,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x04,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x05,0x06]
+
+v_sub_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x16,0x06]
+
+v_sub_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x26,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x00]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x01]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x02]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x03]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x04]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x05]
+
+v_sub_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x16]
+
+v_sub_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x26]
+
+v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x09,0x01,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0xff,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x08,0x01,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x10]
+
+v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x30]
+
+v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
+
+v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01]
+
+v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
+
+v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
+
+v_sub_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
+
+v_sub_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00]
+
+v_sub_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00]
+
+v_sub_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x40,0x00]
+
+v_sub_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x80,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x51,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x5f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x61,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x08,0x01,0x6f,0x01,0x00]
+
+v_subrev_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x0a]
+
+v_subrev_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x0b]
+
+v_subrev_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x0a]
+
+v_subrev_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x0a,0x56,0x34,0x12,0xaf]
+
+v_subrev_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x0a,0x73,0x72,0x71,0x3f]
+
+v_subrev_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x0a]
+
+v_subrev_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x05,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0xff,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x65,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x6a,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x6b,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x7c,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x7e,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x7f,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x80,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0xc1,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0xf0,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0xf7,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xff,0x03,0x00]
+
+v_subrev_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xcb,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xd5,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xd7,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xf9,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xfd,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xff,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x01,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x83,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xe1,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0xef,0x01,0x00]
+
+v_subrev_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x20]
+
+v_subrev_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x40]
+
+v_subrev_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x60]
+
+v_subrev_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x05,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x05,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x05,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x05,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x08]
+
+v_subrev_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x10]
+
+v_subrev_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x05,0xd5,0x01,0x05,0x02,0x18]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x0b,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0xff,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x65,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x6a,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x6b,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x7c,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x7e,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x7f,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x0a,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x26,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x46,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x86,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0xc6,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x00,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x01,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x02,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x03,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x04,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x05,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x0e,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x00,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x01,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x02,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x03,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x04,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x05,0x06]
+
+v_subrev_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x16,0x06]
+
+v_subrev_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x26,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x00]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x01]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x02]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x03]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x04]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x05]
+
+v_subrev_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x16]
+
+v_subrev_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x26]
+
+v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x0b,0x01,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0xff,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x0a,0x01,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x10]
+
+v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x30]
+
+v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01]
+
+v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
+
+v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
+
+v_subrev_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00]
+
+v_subrev_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00]
+
+v_subrev_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x40,0x00]
+
+v_subrev_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x80,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x51,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x5f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x61,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0a,0x01,0x6f,0x01,0x00]
+
+v_mac_legacy_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x0d]
+
+v_mac_legacy_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x0c,0x56,0x34,0x12,0xaf]
+
+v_mac_legacy_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x0c,0x73,0x72,0x71,0x3f]
+
+v_mac_legacy_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x0c]
+
+v_mac_legacy_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x06,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0xff,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x67,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x77,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x80,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xff,0x03,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xcf,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xef,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xff,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x01,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x83,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0xef,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x20]
+
+v_mac_legacy_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x40]
+
+v_mac_legacy_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x60]
+
+v_mac_legacy_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x06,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x06,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x06,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x06,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x08]
+
+v_mac_legacy_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x10]
+
+v_mac_legacy_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x06,0xd5,0x01,0x05,0x02,0x18]
+
+v_mul_legacy_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x0f]
+
+v_mul_legacy_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x0e,0x56,0x34,0x12,0xaf]
+
+v_mul_legacy_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x0e,0x73,0x72,0x71,0x3f]
+
+v_mul_legacy_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x0e]
+
+v_mul_legacy_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x07,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x65,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xcb,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x20]
+
+v_mul_legacy_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x40]
+
+v_mul_legacy_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x60]
+
+v_mul_legacy_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x07,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x07,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x07,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x07,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x08]
+
+v_mul_legacy_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x10]
+
+v_mul_legacy_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x07,0xd5,0x01,0x05,0x02,0x18]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0xff,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x65,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x6a,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x6b,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x7c,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x7e,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x7f,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x26,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x46,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x86,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0xc6,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x00,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x01,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x02,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x03,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x04,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x05,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x0e,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x00,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x01,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x02,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x03,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x04,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x05,0x06]
+
+v_mul_legacy_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x16,0x06]
+
+v_mul_legacy_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x26,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x00]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x01]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x02]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x03]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x04]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x05]
+
+v_mul_legacy_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x16]
+
+v_mul_legacy_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x26]
+
+v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x0f,0x01,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0xff,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x0e,0x01,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x10]
+
+v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x30]
+
+v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
+
+v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01]
+
+v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
+
+v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
+
+v_mul_legacy_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
+
+v_mul_legacy_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x10,0x00]
+
+v_mul_legacy_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x20,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x40,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x80,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x51,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x5f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x61,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x0e,0x01,0x6f,0x01,0x00]
+
+v_mul_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x10]
+
+v_mul_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x11]
+
+v_mul_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x10]
+
+v_mul_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x10]
+
+v_mul_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x10,0x56,0x34,0x12,0xaf]
+
+v_mul_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x10,0x73,0x72,0x71,0x3f]
+
+v_mul_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x10]
+
+v_mul_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x08,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x65,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xcb,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x20]
+
+v_mul_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x40]
+
+v_mul_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x60]
+
+v_mul_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x08,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x08,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x08,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x08,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x08]
+
+v_mul_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x10]
+
+v_mul_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x08,0xd5,0x01,0x05,0x02,0x18]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0xff,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x65,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x6a,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x6b,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x7c,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x7e,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x7f,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x26,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x46,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x86,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0xc6,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x00,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x01,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x02,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x03,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x04,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x05,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x0e,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x00,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x01,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x02,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x03,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x04,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x05,0x06]
+
+v_mul_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x16,0x06]
+
+v_mul_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x26,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x00]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x01]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x02]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x03]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x04]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x05]
+
+v_mul_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x16]
+
+v_mul_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x26]
+
+v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x11,0x01,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0xff,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x10,0x01,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x10]
+
+v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x30]
+
+v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
+
+v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01]
+
+v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
+
+v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
+
+v_mul_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
+
+v_mul_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x10,0x00]
+
+v_mul_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x20,0x00]
+
+v_mul_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x40,0x00]
+
+v_mul_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x80,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x51,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x5f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x61,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x10,0x01,0x6f,0x01,0x00]
+
+v_mul_i32_i24_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x12]
+
+v_mul_i32_i24_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x13]
+
+v_mul_i32_i24_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x12]
+
+v_mul_i32_i24_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0xaf]
+
+v_mul_i32_i24_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x3f]
+
+v_mul_i32_i24_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x12]
+
+v_mul_i32_i24_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x09,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x65,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_i32_i24_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xcb,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x09,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, -4.0 clamp
+// GFX10: encoding: [0x05,0x80,0x09,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0xff,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x65,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x6a,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x6b,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x7c,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x7e,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x7f,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x26,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x00,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x01,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x02,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x03,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x04,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x05,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x0e,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x00,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x01,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x02,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x03,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x04,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x05,0x06]
+
+v_mul_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x0e,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x00]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x01]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x02]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x03]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x04]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x05]
+
+v_mul_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x0e]
+
+v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x13,0x01,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0xff,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x12,0x01,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x10]
+
+v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x30]
+
+v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
+
+v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01]
+
+v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
+
+v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
+
+v_mul_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x51,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x5f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x61,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x12,0x01,0x6f,0x01,0x00]
+
+v_mul_hi_i32_i24_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x15]
+
+v_mul_hi_i32_i24_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x14,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_i32_i24_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x14,0x73,0x72,0x71,0x3f]
+
+v_mul_hi_i32_i24_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x14]
+
+v_mul_hi_i32_i24_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x0a,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x65,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x0a,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0xff,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x65,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x6a,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x6b,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x7c,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x7e,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x7f,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x14,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x26,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x00,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x01,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x02,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x03,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x04,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x05,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x0e,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x00,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x01,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x02,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x03,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x04,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x05,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x0e,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x00]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x01]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x02]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x03]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x04]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x05]
+
+v_mul_hi_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x0e]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x15,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0xff,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x14,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x10]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x30]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x51,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x5f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x61,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x14,0x01,0x6f,0x01,0x00]
+
+v_mul_u32_u24_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x16]
+
+v_mul_u32_u24_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x17]
+
+v_mul_u32_u24_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x16]
+
+v_mul_u32_u24_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x16,0x56,0x34,0x12,0xaf]
+
+v_mul_u32_u24_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x16,0x73,0x72,0x71,0x3f]
+
+v_mul_u32_u24_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x16]
+
+v_mul_u32_u24_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x0b,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x65,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_u32_u24_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xcb,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x0b,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, -4.0 clamp
+// GFX10: encoding: [0x05,0x80,0x0b,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0xff,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x65,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x6a,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x6b,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x7c,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x7e,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x7f,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x16,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x26,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x00,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x01,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x02,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x03,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x04,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x05,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x0e,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x00,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x01,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x02,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x03,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x04,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x05,0x06]
+
+v_mul_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x0e,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x00]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x01]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x02]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x03]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x04]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x05]
+
+v_mul_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x0e]
+
+v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x17,0x01,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0xff,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x16,0x01,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x10]
+
+v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x30]
+
+v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
+
+v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01]
+
+v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
+
+v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
+
+v_mul_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x51,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x5f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x61,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x16,0x01,0x6f,0x01,0x00]
+
+v_mul_hi_u32_u24_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x19]
+
+v_mul_hi_u32_u24_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x18,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_u32_u24_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x18,0x73,0x72,0x71,0x3f]
+
+v_mul_hi_u32_u24_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x18]
+
+v_mul_hi_u32_u24_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x0c,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x65,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x0c,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x19,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0xff,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x65,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x6a,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x6b,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x7c,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x7e,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x7f,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x18,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x26,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x00,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x01,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x02,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x03,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x04,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x05,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x0e,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x00,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x01,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x02,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x03,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x04,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x05,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x0e,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x00]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x01]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x02]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x03]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x04]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x05]
+
+v_mul_hi_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x0e]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x19,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0xff,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x18,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x10]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x30]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x51,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x5f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x61,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x18,0x01,0x6f,0x01,0x00]
+
+v_min_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x1e]
+
+v_min_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x1f]
+
+v_min_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x1e]
+
+v_min_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x1e]
+
+v_min_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x1e,0x56,0x34,0x12,0xaf]
+
+v_min_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x1e,0x73,0x72,0x71,0x3f]
+
+v_min_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x1e]
+
+v_min_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x0f,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0xff,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x65,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x6a,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x6b,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x7c,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x7e,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x7f,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x80,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0xc1,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0xf0,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0xf7,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xff,0x03,0x00]
+
+v_min_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x00,0x00]
+
+v_min_f32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xcb,0x00,0x00]
+
+v_min_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xd5,0x00,0x00]
+
+v_min_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xd7,0x00,0x00]
+
+v_min_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xf9,0x00,0x00]
+
+v_min_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xfd,0x00,0x00]
+
+v_min_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xff,0x00,0x00]
+
+v_min_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x01,0x01,0x00]
+
+v_min_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x83,0x01,0x00]
+
+v_min_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xe1,0x01,0x00]
+
+v_min_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0xef,0x01,0x00]
+
+v_min_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x20]
+
+v_min_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x40]
+
+v_min_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x60]
+
+v_min_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x0f,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x0f,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x0f,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x0f,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x08]
+
+v_min_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x10]
+
+v_min_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x0f,0xd5,0x01,0x05,0x02,0x18]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0xff,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x65,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x6a,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x6b,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x7c,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x7e,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x7f,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x1e,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x26,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x46,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x86,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0xc6,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x00,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x01,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x02,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x03,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x04,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x05,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x0e,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x00,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x01,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x02,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x03,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x04,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x05,0x06]
+
+v_min_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x16,0x06]
+
+v_min_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x26,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x00]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x01]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x02]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x03]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x04]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x05]
+
+v_min_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x16]
+
+v_min_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x26]
+
+v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x00]
+
+v_min_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x1f,0x01,0xe4,0x00,0x00]
+
+v_min_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0xff,0xe4,0x00,0x00]
+
+v_min_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x1e,0x01,0xe4,0x00,0x00]
+
+v_min_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x10]
+
+v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x30]
+
+v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
+
+v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01]
+
+v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
+
+v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
+
+v_min_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
+
+v_min_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x10,0x00]
+
+v_min_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x20,0x00]
+
+v_min_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x40,0x00]
+
+v_min_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x80,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x51,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x5f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x61,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x1e,0x01,0x6f,0x01,0x00]
+
+v_max_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x20]
+
+v_max_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x21]
+
+v_max_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x20]
+
+v_max_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x20]
+
+v_max_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x20,0x56,0x34,0x12,0xaf]
+
+v_max_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x20,0x73,0x72,0x71,0x3f]
+
+v_max_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x20]
+
+v_max_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x10,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0xff,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x65,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x6a,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x6b,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x7c,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x7e,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x7f,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x80,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0xc1,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0xf0,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0xf7,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xff,0x03,0x00]
+
+v_max_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x00,0x00]
+
+v_max_f32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xcb,0x00,0x00]
+
+v_max_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xd5,0x00,0x00]
+
+v_max_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xd7,0x00,0x00]
+
+v_max_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xf9,0x00,0x00]
+
+v_max_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xfd,0x00,0x00]
+
+v_max_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xff,0x00,0x00]
+
+v_max_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x01,0x01,0x00]
+
+v_max_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x83,0x01,0x00]
+
+v_max_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xe1,0x01,0x00]
+
+v_max_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0xef,0x01,0x00]
+
+v_max_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x20]
+
+v_max_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x40]
+
+v_max_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x60]
+
+v_max_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x10,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x10,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x10,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x10,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x08]
+
+v_max_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x10]
+
+v_max_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x10,0xd5,0x01,0x05,0x02,0x18]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0xff,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x65,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x6a,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x6b,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x7c,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x7e,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x7f,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x20,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x26,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x46,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x86,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0xc6,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x00,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x01,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x02,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x03,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x04,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x05,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x0e,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x00,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x01,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x02,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x03,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x04,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x05,0x06]
+
+v_max_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x16,0x06]
+
+v_max_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x26,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x00]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x01]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x02]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x03]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x04]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x05]
+
+v_max_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x16]
+
+v_max_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x26]
+
+v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x00]
+
+v_max_f32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x21,0x01,0xe4,0x00,0x00]
+
+v_max_f32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0xff,0xe4,0x00,0x00]
+
+v_max_f32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x20,0x01,0xe4,0x00,0x00]
+
+v_max_f32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x10]
+
+v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x30]
+
+v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
+
+v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01]
+
+v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
+
+v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
+
+v_max_f32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
+
+v_max_f32_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x10,0x00]
+
+v_max_f32_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x20,0x00]
+
+v_max_f32_dpp v5, v1, -v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x40,0x00]
+
+v_max_f32_dpp v5, v1, |v2|  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x80,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x51,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x5f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x61,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x20,0x01,0x6f,0x01,0x00]
+
+v_min_i32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x22]
+
+v_min_i32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x23]
+
+v_min_i32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x22]
+
+v_min_i32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x22]
+
+v_min_i32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x22,0x56,0x34,0x12,0xaf]
+
+v_min_i32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x22,0x73,0x72,0x71,0x3f]
+
+v_min_i32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x22]
+
+v_min_i32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_i32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x11,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_i32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0xff,0x05,0x02,0x00]
+
+v_min_i32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x65,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x6a,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x6b,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x7c,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x7e,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x7f,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x80,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0xc1,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0xf0,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0xf7,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xff,0x03,0x00]
+
+v_min_i32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x05,0x00,0x00]
+
+v_min_i32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xcb,0x00,0x00]
+
+v_min_i32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xd5,0x00,0x00]
+
+v_min_i32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xd7,0x00,0x00]
+
+v_min_i32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xf9,0x00,0x00]
+
+v_min_i32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xfd,0x00,0x00]
+
+v_min_i32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xff,0x00,0x00]
+
+v_min_i32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x01,0x01,0x00]
+
+v_min_i32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0x83,0x01,0x00]
+
+v_min_i32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xe1,0x01,0x00]
+
+v_min_i32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x11,0xd5,0x01,0xef,0x01,0x00]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0xff,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x65,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x6a,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x6b,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x7c,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x7e,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x7f,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x22,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x26,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x00,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x01,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x02,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x03,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x04,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x05,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x0e,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x00,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x01,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x02,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x03,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x04,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x05,0x06]
+
+v_min_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x0e,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x00]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x01]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x02]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x03]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x04]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x05]
+
+v_min_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x0e]
+
+v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00]
+
+v_min_i32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00]
+
+v_min_i32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0xff,0xe4,0x00,0x00]
+
+v_min_i32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x22,0x01,0xe4,0x00,0x00]
+
+v_min_i32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x10]
+
+v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x30]
+
+v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
+
+v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01]
+
+v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
+
+v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
+
+v_min_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x51,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x5f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x61,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x22,0x01,0x6f,0x01,0x00]
+
+v_max_i32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x24]
+
+v_max_i32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x25]
+
+v_max_i32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x24]
+
+v_max_i32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x24]
+
+v_max_i32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x24,0x56,0x34,0x12,0xaf]
+
+v_max_i32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x24,0x73,0x72,0x71,0x3f]
+
+v_max_i32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x24]
+
+v_max_i32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_i32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x12,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_i32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0xff,0x05,0x02,0x00]
+
+v_max_i32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x65,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x6a,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x6b,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x7c,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x7e,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x7f,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x80,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0xc1,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0xf0,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0xf7,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xff,0x03,0x00]
+
+v_max_i32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x05,0x00,0x00]
+
+v_max_i32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xcb,0x00,0x00]
+
+v_max_i32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xd5,0x00,0x00]
+
+v_max_i32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xd7,0x00,0x00]
+
+v_max_i32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xf9,0x00,0x00]
+
+v_max_i32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xfd,0x00,0x00]
+
+v_max_i32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xff,0x00,0x00]
+
+v_max_i32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x01,0x01,0x00]
+
+v_max_i32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0x83,0x01,0x00]
+
+v_max_i32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xe1,0x01,0x00]
+
+v_max_i32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x12,0xd5,0x01,0xef,0x01,0x00]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0xff,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x65,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x6a,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x6b,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x7c,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x7e,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x7f,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x24,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x26,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x00,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x01,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x02,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x03,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x04,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x05,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x0e,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x00,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x01,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x02,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x03,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x04,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x05,0x06]
+
+v_max_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x0e,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x00]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x01]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x02]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x03]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x04]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x05]
+
+v_max_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x0e]
+
+v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00]
+
+v_max_i32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00]
+
+v_max_i32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0xff,0xe4,0x00,0x00]
+
+v_max_i32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x24,0x01,0xe4,0x00,0x00]
+
+v_max_i32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x10]
+
+v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x30]
+
+v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
+
+v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01]
+
+v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
+
+v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
+
+v_max_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x51,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x5f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x61,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x24,0x01,0x6f,0x01,0x00]
+
+v_min_u32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x26]
+
+v_min_u32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x27]
+
+v_min_u32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x26]
+
+v_min_u32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x26]
+
+v_min_u32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x26,0x56,0x34,0x12,0xaf]
+
+v_min_u32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x26,0x73,0x72,0x71,0x3f]
+
+v_min_u32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x26]
+
+v_min_u32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_u32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x13,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_u32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0xff,0x05,0x02,0x00]
+
+v_min_u32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x65,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x6a,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x6b,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x7c,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x7e,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x7f,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x80,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0xc1,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0xf0,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0xf7,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xff,0x03,0x00]
+
+v_min_u32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x05,0x00,0x00]
+
+v_min_u32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xcb,0x00,0x00]
+
+v_min_u32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xd5,0x00,0x00]
+
+v_min_u32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xd7,0x00,0x00]
+
+v_min_u32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xf9,0x00,0x00]
+
+v_min_u32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xfd,0x00,0x00]
+
+v_min_u32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xff,0x00,0x00]
+
+v_min_u32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x01,0x01,0x00]
+
+v_min_u32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0x83,0x01,0x00]
+
+v_min_u32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xe1,0x01,0x00]
+
+v_min_u32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x13,0xd5,0x01,0xef,0x01,0x00]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0xff,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x65,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x6a,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x6b,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x7c,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x7e,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x7f,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x26,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x26,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x00,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x01,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x02,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x03,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x04,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x05,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x0e,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x00,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x01,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x02,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x03,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x04,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x05,0x06]
+
+v_min_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x0e,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x00]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x01]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x02]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x03]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x04]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x05]
+
+v_min_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x0e]
+
+v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00]
+
+v_min_u32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00]
+
+v_min_u32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0xff,0xe4,0x00,0x00]
+
+v_min_u32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x26,0x01,0xe4,0x00,0x00]
+
+v_min_u32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x10]
+
+v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x30]
+
+v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
+
+v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01]
+
+v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
+
+v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
+
+v_min_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x51,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x5f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x61,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x26,0x01,0x6f,0x01,0x00]
+
+v_max_u32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x28]
+
+v_max_u32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x29]
+
+v_max_u32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x28]
+
+v_max_u32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x28]
+
+v_max_u32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x28,0x56,0x34,0x12,0xaf]
+
+v_max_u32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x28,0x73,0x72,0x71,0x3f]
+
+v_max_u32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x28]
+
+v_max_u32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_u32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x14,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_u32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0xff,0x05,0x02,0x00]
+
+v_max_u32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x65,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x6a,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x6b,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x7c,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x7e,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x7f,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x80,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0xc1,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0xf0,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0xf7,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xff,0x03,0x00]
+
+v_max_u32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x05,0x00,0x00]
+
+v_max_u32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xcb,0x00,0x00]
+
+v_max_u32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xd5,0x00,0x00]
+
+v_max_u32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xd7,0x00,0x00]
+
+v_max_u32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xf9,0x00,0x00]
+
+v_max_u32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xfd,0x00,0x00]
+
+v_max_u32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xff,0x00,0x00]
+
+v_max_u32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x01,0x01,0x00]
+
+v_max_u32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0x83,0x01,0x00]
+
+v_max_u32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xe1,0x01,0x00]
+
+v_max_u32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x14,0xd5,0x01,0xef,0x01,0x00]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0xff,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x65,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x6a,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x6b,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x7c,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x7e,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x7f,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x28,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x26,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x00,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x01,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x02,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x03,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x04,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x05,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x0e,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x00,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x01,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x02,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x03,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x04,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x05,0x06]
+
+v_max_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x0e,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x00]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x01]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x02]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x03]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x04]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x05]
+
+v_max_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x0e]
+
+v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00]
+
+v_max_u32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00]
+
+v_max_u32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0xff,0xe4,0x00,0x00]
+
+v_max_u32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x28,0x01,0xe4,0x00,0x00]
+
+v_max_u32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x10]
+
+v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x30]
+
+v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
+
+v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01]
+
+v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
+
+v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
+
+v_max_u32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x51,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x5f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x61,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x28,0x01,0x6f,0x01,0x00]
+
+v_lshrrev_b32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x2d]
+
+v_lshrrev_b32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x2c]
+
+v_lshrrev_b32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x2c,0x56,0x34,0x12,0xaf]
+
+v_lshrrev_b32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x2c,0x73,0x72,0x71,0x3f]
+
+v_lshrrev_b32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x2c]
+
+v_lshrrev_b32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x16,0xd5,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x65,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0xf0,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0xf7,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xff,0x03,0x00]
+
+v_lshrrev_b32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x05,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xcb,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xd7,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xf9,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xff,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xe1,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x16,0xd5,0x01,0xef,0x01,0x00]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x2d,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0xff,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x65,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x6a,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x6b,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x7c,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x7e,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x7f,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x2c,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x00,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x01,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x02,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x03,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x04,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x05,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x0e,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x00,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x01,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x02,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x03,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x04,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x05,0x06]
+
+v_lshrrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x0e,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x00]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x01]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x02]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x03]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x04]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x05]
+
+v_lshrrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x0e]
+
+v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0xff,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x2c,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x10]
+
+v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x30]
+
+v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
+
+v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01]
+
+v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
+
+v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
+
+v_lshrrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x51,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x5f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x61,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x2c,0x01,0x6f,0x01,0x00]
+
+v_ashrrev_i32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x30]
+
+v_ashrrev_i32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x31]
+
+v_ashrrev_i32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x30]
+
+v_ashrrev_i32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x30,0x56,0x34,0x12,0xaf]
+
+v_ashrrev_i32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x30,0x73,0x72,0x71,0x3f]
+
+v_ashrrev_i32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x30]
+
+v_ashrrev_i32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x18,0xd5,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x65,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0xf0,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0xf7,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xff,0x03,0x00]
+
+v_ashrrev_i32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x05,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xcb,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xd7,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xf9,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xff,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xe1,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x18,0xd5,0x01,0xef,0x01,0x00]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x31,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0xff,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x65,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x6a,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x6b,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x7c,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x7e,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x7f,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x30,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x00,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x01,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x02,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x03,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x04,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x05,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x0e,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x00,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x01,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x02,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x03,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x04,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x05,0x06]
+
+v_ashrrev_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x0e,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x00]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x01]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x02]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x03]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x04]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x05]
+
+v_ashrrev_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x30,0x01,0x06,0x06,0x0e]
+
+v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x31,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0xff,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x30,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x40,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x41,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x0f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x11,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x1f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x21,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x2f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x10]
+
+v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x30]
+
+v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0xf0]
+
+v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x01]
+
+v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x03]
+
+v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x0f]
+
+v_ashrrev_i32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x08,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x51,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x5f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x61,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x30,0x01,0x6f,0x01,0x00]
+
+v_lshlrev_b32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x34]
+
+v_lshlrev_b32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x35]
+
+v_lshlrev_b32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x34]
+
+v_lshlrev_b32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x34,0x56,0x34,0x12,0xaf]
+
+v_lshlrev_b32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x34,0x73,0x72,0x71,0x3f]
+
+v_lshlrev_b32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x34]
+
+v_lshlrev_b32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x1a,0xd5,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x65,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0xf0,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0xf7,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xff,0x03,0x00]
+
+v_lshlrev_b32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x05,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xcb,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xd7,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xf9,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xff,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xe1,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x1a,0xd5,0x01,0xef,0x01,0x00]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0xff,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x65,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x6a,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x6b,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x7c,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x7e,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x7f,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x34,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x00,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x01,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x02,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x03,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x04,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x05,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x0e,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x00,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x01,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x02,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x03,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x04,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x05,0x06]
+
+v_lshlrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x0e,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x00]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x01]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x02]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x03]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x04]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x05]
+
+v_lshlrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x0e]
+
+v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0xff,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x34,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x10]
+
+v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x30]
+
+v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
+
+v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01]
+
+v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
+
+v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
+
+v_lshlrev_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x51,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x5f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x61,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x34,0x01,0x6f,0x01,0x00]
+
+v_and_b32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x36]
+
+v_and_b32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x37]
+
+v_and_b32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x36]
+
+v_and_b32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x36]
+
+v_and_b32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x36,0x56,0x34,0x12,0xaf]
+
+v_and_b32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x36,0x73,0x72,0x71,0x3f]
+
+v_and_b32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x36]
+
+v_and_b32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x05,0x02,0x00]
+
+v_and_b32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x1b,0xd5,0x01,0x05,0x02,0x00]
+
+v_and_b32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0xff,0x05,0x02,0x00]
+
+v_and_b32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x65,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x6a,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x6b,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x7c,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x7e,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x7f,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x80,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0xc1,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0xf0,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0xf7,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xff,0x03,0x00]
+
+v_and_b32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x05,0x00,0x00]
+
+v_and_b32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xcb,0x00,0x00]
+
+v_and_b32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xd5,0x00,0x00]
+
+v_and_b32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xd7,0x00,0x00]
+
+v_and_b32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xf9,0x00,0x00]
+
+v_and_b32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xfd,0x00,0x00]
+
+v_and_b32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xff,0x00,0x00]
+
+v_and_b32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x01,0x01,0x00]
+
+v_and_b32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0x83,0x01,0x00]
+
+v_and_b32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xe1,0x01,0x00]
+
+v_and_b32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x1b,0xd5,0x01,0xef,0x01,0x00]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0xff,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x65,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x6a,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x6b,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x7c,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x7e,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x7f,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x36,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x00,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x01,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x02,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x03,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x04,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x05,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x0e,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x00,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x01,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x02,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x03,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x04,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x05,0x06]
+
+v_and_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x0e,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x00]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x01]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x02]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x03]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x04]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x05]
+
+v_and_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x0e]
+
+v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x00]
+
+v_and_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x37,0x01,0xe4,0x00,0x00]
+
+v_and_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0xff,0xe4,0x00,0x00]
+
+v_and_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x36,0x01,0xe4,0x00,0x00]
+
+v_and_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x10]
+
+v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x30]
+
+v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
+
+v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01]
+
+v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
+
+v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
+
+v_and_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x51,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x5f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x61,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x36,0x01,0x6f,0x01,0x00]
+
+v_or_b32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x38]
+
+v_or_b32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x39]
+
+v_or_b32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x38]
+
+v_or_b32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x38]
+
+v_or_b32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x38,0x56,0x34,0x12,0xaf]
+
+v_or_b32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x38,0x73,0x72,0x71,0x3f]
+
+v_or_b32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x38]
+
+v_or_b32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x05,0x02,0x00]
+
+v_or_b32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x1c,0xd5,0x01,0x05,0x02,0x00]
+
+v_or_b32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0xff,0x05,0x02,0x00]
+
+v_or_b32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x65,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x6a,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x6b,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x7c,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x7e,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x7f,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x80,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0xc1,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0xf0,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0xf7,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xff,0x03,0x00]
+
+v_or_b32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x05,0x00,0x00]
+
+v_or_b32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xcb,0x00,0x00]
+
+v_or_b32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xd5,0x00,0x00]
+
+v_or_b32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xd7,0x00,0x00]
+
+v_or_b32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xf9,0x00,0x00]
+
+v_or_b32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xfd,0x00,0x00]
+
+v_or_b32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xff,0x00,0x00]
+
+v_or_b32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x01,0x01,0x00]
+
+v_or_b32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0x83,0x01,0x00]
+
+v_or_b32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xe1,0x01,0x00]
+
+v_or_b32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x1c,0xd5,0x01,0xef,0x01,0x00]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0xff,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x65,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x6a,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x6b,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x7c,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x7e,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x7f,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x38,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x00,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x01,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x02,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x03,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x04,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x05,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x0e,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x00,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x01,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x02,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x03,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x04,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x05,0x06]
+
+v_or_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x0e,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x00]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x01]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x02]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x03]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x04]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x05]
+
+v_or_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x0e]
+
+v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x00]
+
+v_or_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x39,0x01,0xe4,0x00,0x00]
+
+v_or_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0xff,0xe4,0x00,0x00]
+
+v_or_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x38,0x01,0xe4,0x00,0x00]
+
+v_or_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x10]
+
+v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x30]
+
+v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
+
+v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01]
+
+v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
+
+v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
+
+v_or_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x51,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x5f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x61,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x38,0x01,0x6f,0x01,0x00]
+
+v_xor_b32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x3a]
+
+v_xor_b32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x3b]
+
+v_xor_b32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x3a]
+
+v_xor_b32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x3a]
+
+v_xor_b32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x3a,0x56,0x34,0x12,0xaf]
+
+v_xor_b32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x3a,0x73,0x72,0x71,0x3f]
+
+v_xor_b32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x3a]
+
+v_xor_b32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x05,0x02,0x00]
+
+v_xor_b32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x1d,0xd5,0x01,0x05,0x02,0x00]
+
+v_xor_b32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0xff,0x05,0x02,0x00]
+
+v_xor_b32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x65,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x6a,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x6b,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x7c,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x7e,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x7f,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x80,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0xc1,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0xf0,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0xf7,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xff,0x03,0x00]
+
+v_xor_b32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x05,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xcb,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xd5,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xd7,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xf9,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xfd,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xff,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x01,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x83,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xe1,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x1d,0xd5,0x01,0xef,0x01,0x00]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0xff,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x65,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x6a,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x6b,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x7c,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x7e,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x7f,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x3a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x00,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x01,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x02,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x03,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x04,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x05,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x0e,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x00,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x01,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x02,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x03,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x04,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x05,0x06]
+
+v_xor_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x0e,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x00]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x01]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x02]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x03]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x04]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x05]
+
+v_xor_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x0e]
+
+v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x3b,0x01,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0xff,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x3a,0x01,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x10]
+
+v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x30]
+
+v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
+
+v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01]
+
+v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
+
+v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
+
+v_xor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x51,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x5f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x61,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3a,0x01,0x6f,0x01,0x00]
+
+v_xnor_b32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x3c]
+
+v_xnor_b32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x3d]
+
+v_xnor_b32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x3c]
+
+v_xnor_b32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x3c,0x56,0x34,0x12,0xaf]
+
+v_xnor_b32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x3c,0x73,0x72,0x71,0x3f]
+
+v_xnor_b32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x3c]
+
+v_xnor_b32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x05,0x02,0x00]
+
+v_xnor_b32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x1e,0xd5,0x01,0x05,0x02,0x00]
+
+v_xnor_b32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0xff,0x05,0x02,0x00]
+
+v_xnor_b32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x65,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x6a,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x6b,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x7c,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x7e,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x7f,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x80,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0xc1,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0xf0,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0xf7,0x04,0x02,0x00]
+
+v_xnor_b32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xff,0x03,0x00]
+
+v_xnor_b32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x05,0x00,0x00]
+
+v_xnor_b32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xcb,0x00,0x00]
+
+v_xnor_b32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xd5,0x00,0x00]
+
+v_xnor_b32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xd7,0x00,0x00]
+
+v_xnor_b32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xf9,0x00,0x00]
+
+v_xnor_b32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xfd,0x00,0x00]
+
+v_xnor_b32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xff,0x00,0x00]
+
+v_xnor_b32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x01,0x01,0x00]
+
+v_xnor_b32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0x83,0x01,0x00]
+
+v_xnor_b32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xe1,0x01,0x00]
+
+v_xnor_b32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x1e,0xd5,0x01,0xef,0x01,0x00]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_xnor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0xff,0x06,0x06,0x06]
+
+v_xnor_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x86,0x06]
+
+v_xnor_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x65,0x06,0x86,0x06]
+
+v_xnor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x6a,0x06,0x86,0x06]
+
+v_xnor_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x6b,0x06,0x86,0x06]
+
+v_xnor_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x7c,0x06,0x86,0x06]
+
+v_xnor_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x7e,0x06,0x86,0x06]
+
+v_xnor_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x7f,0x06,0x86,0x06]
+
+v_xnor_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x3c,0x01,0x06,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x00,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x01,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x02,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x03,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x04,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x05,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x0e,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x00,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x01,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x02,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x03,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x04,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x05,0x06]
+
+v_xnor_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x0e,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x00]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x01]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x02]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x03]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x04]
+
+v_xnor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x05]
+
+v_xnor_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x0e]
+
+v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x00]
+
+v_xnor_b32_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x3d,0x01,0xe4,0x00,0x00]
+
+v_xnor_b32_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0xff,0xe4,0x00,0x00]
+
+v_xnor_b32_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x3c,0x01,0xe4,0x00,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x10]
+
+v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x30]
+
+v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
+
+v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01]
+
+v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
+
+v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
+
+v_xnor_b32_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x51,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x5f,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x61,0x01,0x00]
+
+v_xnor_b32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x3c,0x01,0x6f,0x01,0x00]
+
+v_mac_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x3e]
+
+v_mac_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x3f]
+
+v_mac_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x3e]
+
+v_mac_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x3e]
+
+v_mac_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x3e,0x56,0x34,0x12,0xaf]
+
+v_mac_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x3e,0x73,0x72,0x71,0x3f]
+
+v_mac_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x3e]
+
+v_mac_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x1f,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0xff,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x65,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x80,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xff,0x03,0x00]
+
+v_mac_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xcb,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xff,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x01,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x83,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0xef,0x01,0x00]
+
+v_mac_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x20]
+
+v_mac_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x40]
+
+v_mac_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x60]
+
+v_mac_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x1f,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x1f,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x1f,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x1f,0xd5,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x08]
+
+v_mac_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x10]
+
+v_mac_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x1f,0xd5,0x01,0x05,0x02,0x18]
+
+v_madmk_f32 v5, v1, 0x11213141, v3
+// GFX10: encoding: [0x01,0x07,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v255, v1, 0x11213141, v3
+// GFX10: encoding: [0x01,0x07,0xfe,0x41,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, v255, 0x11213141, v3
+// GFX10: encoding: [0xff,0x07,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, 0, 0x11213141, v3
+// GFX10: encoding: [0x80,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, -1, 0x11213141, v3
+// GFX10: encoding: [0xc1,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, 0.5, 0x11213141, v3
+// GFX10: encoding: [0xf0,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, -4.0, 0x11213141, v3
+// GFX10: encoding: [0xf7,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, v1, 0xa1b1c1d1, v3
+// GFX10: encoding: [0x01,0x07,0x0a,0x40,0xd1,0xc1,0xb1,0xa1]
+
+v_madmk_f32 v5, v1, 0x11213141, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x40,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v2, 0x11213141
+// GFX10: encoding: [0x01,0x05,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v255, v1, v2, 0x11213141
+// GFX10: encoding: [0x01,0x05,0xfe,0x43,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v255, v2, 0x11213141
+// GFX10: encoding: [0xff,0x05,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, 0, v2, 0x11213141
+// GFX10: encoding: [0x80,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, -1, v2, 0x11213141
+// GFX10: encoding: [0xc1,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, 0.5, v2, 0x11213141
+// GFX10: encoding: [0xf0,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, -4.0, v2, 0x11213141
+// GFX10: encoding: [0xf7,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v255, 0x11213141
+// GFX10: encoding: [0x01,0xff,0x0b,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v2, 0xa1b1c1d1
+// GFX10: encoding: [0x01,0x05,0x0a,0x42,0xd1,0xc1,0xb1,0xa1]
+
+v_add_nc_u32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x4a]
+
+v_add_nc_u32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x4b]
+
+v_add_nc_u32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x4a]
+
+v_add_nc_u32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x4a,0x56,0x34,0x12,0xaf]
+
+v_add_nc_u32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x4a,0x73,0x72,0x71,0x3f]
+
+v_add_nc_u32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x4a]
+
+v_add_nc_u32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_nc_u32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x25,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_nc_u32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0xff,0x05,0x02,0x00]
+
+v_add_nc_u32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x65,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x6a,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x6b,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x7c,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x7e,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x7f,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x80,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0xc1,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0xf0,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0xf7,0x04,0x02,0x00]
+
+v_add_nc_u32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xff,0x03,0x00]
+
+v_add_nc_u32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x05,0x00,0x00]
+
+v_add_nc_u32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xcb,0x00,0x00]
+
+v_add_nc_u32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xd5,0x00,0x00]
+
+v_add_nc_u32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xd7,0x00,0x00]
+
+v_add_nc_u32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xf9,0x00,0x00]
+
+v_add_nc_u32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xfd,0x00,0x00]
+
+v_add_nc_u32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xff,0x00,0x00]
+
+v_add_nc_u32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x01,0x01,0x00]
+
+v_add_nc_u32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0x83,0x01,0x00]
+
+v_add_nc_u32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xe1,0x01,0x00]
+
+v_add_nc_u32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x25,0xd5,0x01,0xef,0x01,0x00]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x06]
+
+v_add_nc_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x4b,0x01,0x06,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0xff,0x06,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x86,0x06]
+
+v_add_nc_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x65,0x06,0x86,0x06]
+
+v_add_nc_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x6a,0x06,0x86,0x06]
+
+v_add_nc_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x6b,0x06,0x86,0x06]
+
+v_add_nc_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x7c,0x06,0x86,0x06]
+
+v_add_nc_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x7e,0x06,0x86,0x06]
+
+v_add_nc_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x7f,0x06,0x86,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x4a,0x01,0x06,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x26,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x00,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x01,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x02,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x03,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x04,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x05,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x0e,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x16,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x16,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x00,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x01,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x02,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x03,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x04,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x05,0x06]
+
+v_add_nc_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x0e,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x06]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x00]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x01]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x02]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x03]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x04]
+
+v_add_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x05]
+
+v_add_nc_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4a,0x01,0x06,0x06,0x0e]
+
+v_sub_nc_u32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x4d]
+
+v_sub_nc_u32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x4c]
+
+v_sub_nc_u32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x4c,0x56,0x34,0x12,0xaf]
+
+v_sub_nc_u32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x4c,0x73,0x72,0x71,0x3f]
+
+v_sub_nc_u32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x4c]
+
+v_sub_nc_u32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x26,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0xff,0x05,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x65,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x6a,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x6b,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x7c,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x7e,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x7f,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x80,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0xc1,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0xf0,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0xf7,0x04,0x02,0x00]
+
+v_sub_nc_u32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xff,0x03,0x00]
+
+v_sub_nc_u32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x05,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xcb,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xd5,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xd7,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xf9,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xfd,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xff,0x00,0x00]
+
+v_sub_nc_u32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x01,0x01,0x00]
+
+v_sub_nc_u32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0x83,0x01,0x00]
+
+v_sub_nc_u32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xe1,0x01,0x00]
+
+v_sub_nc_u32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x26,0xd5,0x01,0xef,0x01,0x00]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_sub_nc_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x4d,0x01,0x06,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0xff,0x06,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x86,0x06]
+
+v_sub_nc_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x65,0x06,0x86,0x06]
+
+v_sub_nc_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x6a,0x06,0x86,0x06]
+
+v_sub_nc_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x6b,0x06,0x86,0x06]
+
+v_sub_nc_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x7c,0x06,0x86,0x06]
+
+v_sub_nc_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x7e,0x06,0x86,0x06]
+
+v_sub_nc_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x7f,0x06,0x86,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x4c,0x01,0x06,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x26,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x00,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x01,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x02,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x03,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x04,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x05,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x0e,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x00,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x01,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x02,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x03,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x04,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x05,0x06]
+
+v_sub_nc_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x0e,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x00]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x01]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x02]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x03]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x04]
+
+v_sub_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x05]
+
+v_sub_nc_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x0e]
+
+v_subrev_nc_u32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x4f]
+
+v_subrev_nc_u32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x4e]
+
+v_subrev_nc_u32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x4e,0x56,0x34,0x12,0xaf]
+
+v_subrev_nc_u32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x4e,0x73,0x72,0x71,0x3f]
+
+v_subrev_nc_u32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x4e]
+
+v_subrev_nc_u32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_nc_u32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x27,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0xff,0x05,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x65,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x6a,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x6b,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x7c,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x7e,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x7f,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x80,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0xc1,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0xf0,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0xf7,0x04,0x02,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xff,0x03,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x05,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xcb,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xd5,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xd7,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xf9,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xfd,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xff,0x00,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x01,0x01,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0x83,0x01,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xe1,0x01,0x00]
+
+v_subrev_nc_u32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x27,0xd5,0x01,0xef,0x01,0x00]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0xff,0x06,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x86,0x06]
+
+v_subrev_nc_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x65,0x06,0x86,0x06]
+
+v_subrev_nc_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x6a,0x06,0x86,0x06]
+
+v_subrev_nc_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x6b,0x06,0x86,0x06]
+
+v_subrev_nc_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x7c,0x06,0x86,0x06]
+
+v_subrev_nc_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x7e,0x06,0x86,0x06]
+
+v_subrev_nc_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x7f,0x06,0x86,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x4e,0x01,0x06,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x26,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x00,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x01,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x02,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x03,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x04,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x05,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x0e,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x00,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x01,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x02,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x03,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x04,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x05,0x06]
+
+v_subrev_nc_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x0e,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x00]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x01]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x02]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x03]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x04]
+
+v_subrev_nc_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x05]
+
+v_subrev_nc_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x0e]
+
+v_add_co_ci_u32_e32 v5, vcc, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0x0a,0x50]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v255, vcc, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0xfe,0x51]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc, v255, v2, vcc
+// W64: encoding: [0xff,0x05,0x0a,0x50]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc, 0, v2, vcc
+// W64: encoding: [0x80,0x04,0x0a,0x50]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc, -1, v2, vcc
+// W64: encoding: [0xc1,0x04,0x0a,0x50]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc
+// W64: encoding: [0xf0,0x04,0x0a,0x50]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc, -4.0, v2, vcc
+// W64: encoding: [0xf7,0x04,0x0a,0x50]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc, v1, v255, vcc
+// W64: encoding: [0x01,0xff,0x0b,0x50]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// W64: encoding: [0xff,0x0c,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x0e,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[102:103], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x66,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, vcc, v1, v2, s[6:7]
+// W64: encoding: [0x05,0x6a,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0xff,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x80,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0xc1,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0xf0,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0xf7,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xff,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x01,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x83,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xe1,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xef,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x22,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, v2, s[102:103]
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x9a,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s[12:13], v1, v2, vcc
+// W64: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0xaa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0x0a,0x50]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v255, vcc_lo, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0xfe,0x51]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo
+// W32: encoding: [0xff,0x05,0x0a,0x50]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
+// W32: encoding: [0x80,0x04,0x0a,0x50]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo
+// W32: encoding: [0xc1,0x04,0x0a,0x50]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo
+// W32: encoding: [0xf0,0x04,0x0a,0x50]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc_lo, -4.0, v2, vcc_lo
+// W32: encoding: [0xf7,0x04,0x0a,0x50]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e32 v5, vcc_lo, v1, v255, vcc_lo
+// W32: encoding: [0x01,0xff,0x0b,0x50]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_e64 v5, s12, v1, v2, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v255, s12, v1, v2, s6
+// W32: encoding: [0xff,0x0c,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s14, v1, v2, s6
+// W32: encoding: [0x05,0x0e,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s102, v1, v2, s6
+// W32: encoding: [0x05,0x66,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, vcc_lo, v1, v2, s6
+// W32: encoding: [0x05,0x6a,0x28,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, v255, v2, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0xff,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, 0, v2, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x80,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, -1, v2, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0xc1,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, 0.5, v2, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0xf0,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, -4.0, v2, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0xf7,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, v1, v255, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xff,0x1b,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, v1, 0, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x01,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, v1, -1, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x83,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, v1, 0.5, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xe1,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, v1, -4.0, s6
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0xef,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, v1, v2, s8
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x22,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, v1, v2, s102
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0x9a,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_e64 v5, s12, v1, v2, vcc_lo
+// W32: encoding: [0x05,0x0c,0x28,0xd5,0x01,0x05,0xaa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x26,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x01,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x02,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x03,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x04,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x05,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x0e,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v255, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v255, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v255, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x26,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x01,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x02,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x03,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x04,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x05,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x0e,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, sext(v1), v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_add_co_ci_u32_sdwa v5, vcc_lo, v1, sext(v2), vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0x0a,0x52]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v255, vcc, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0xfe,0x53]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc, v255, v2, vcc
+// W64: encoding: [0xff,0x05,0x0a,0x52]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc, 0, v2, vcc
+// W64: encoding: [0x80,0x04,0x0a,0x52]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc, -1, v2, vcc
+// W64: encoding: [0xc1,0x04,0x0a,0x52]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc
+// W64: encoding: [0xf0,0x04,0x0a,0x52]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc, -4.0, v2, vcc
+// W64: encoding: [0xf7,0x04,0x0a,0x52]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc, v1, v255, vcc
+// W64: encoding: [0x01,0xff,0x0b,0x52]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// W64: encoding: [0xff,0x0c,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x0e,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[102:103], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x66,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, vcc, v1, v2, s[6:7]
+// W64: encoding: [0x05,0x6a,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0xff,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x80,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0xc1,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0xf0,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0xf7,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xff,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x01,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x83,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xe1,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xef,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x22,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, v2, s[102:103]
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x9a,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s[12:13], v1, v2, vcc
+// W64: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0xaa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0x0a,0x52]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v255, vcc_lo, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0xfe,0x53]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo
+// W32: encoding: [0xff,0x05,0x0a,0x52]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
+// W32: encoding: [0x80,0x04,0x0a,0x52]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo
+// W32: encoding: [0xc1,0x04,0x0a,0x52]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo
+// W32: encoding: [0xf0,0x04,0x0a,0x52]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc_lo, -4.0, v2, vcc_lo
+// W32: encoding: [0xf7,0x04,0x0a,0x52]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v255, vcc_lo
+// W32: encoding: [0x01,0xff,0x0b,0x52]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_e64 v5, s12, v1, v2, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v255, s12, v1, v2, s6
+// W32: encoding: [0xff,0x0c,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s14, v1, v2, s6
+// W32: encoding: [0x05,0x0e,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s102, v1, v2, s6
+// W32: encoding: [0x05,0x66,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, vcc_lo, v1, v2, s6
+// W32: encoding: [0x05,0x6a,0x29,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, v255, v2, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0xff,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, 0, v2, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x80,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, -1, v2, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0xc1,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, 0.5, v2, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0xf0,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, -4.0, v2, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0xf7,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, v1, v255, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xff,0x1b,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, v1, 0, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x01,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, v1, -1, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x83,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, v1, 0.5, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xe1,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, v1, -4.0, s6
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0xef,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, v1, v2, s8
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x22,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, v1, v2, s102
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0x9a,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_e64 v5, s12, v1, v2, vcc_lo
+// W32: encoding: [0x05,0x0c,0x29,0xd5,0x01,0x05,0xaa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x26,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x01,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x02,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x03,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x04,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x05,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x0e,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v255, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v255, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v255, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x26,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x01,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x02,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x03,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x04,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x05,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x0e,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, sext(v1), v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, sext(v2), vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0x0a,0x54]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v255, vcc, v1, v2, vcc
+// W64: encoding: [0x01,0x05,0xfe,0x55]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc, v255, v2, vcc
+// W64: encoding: [0xff,0x05,0x0a,0x54]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc, 0, v2, vcc
+// W64: encoding: [0x80,0x04,0x0a,0x54]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc, -1, v2, vcc
+// W64: encoding: [0xc1,0x04,0x0a,0x54]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc, 0.5, v2, vcc
+// W64: encoding: [0xf0,0x04,0x0a,0x54]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc, -4.0, v2, vcc
+// W64: encoding: [0xf7,0x04,0x0a,0x54]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc, v1, v255, vcc
+// W64: encoding: [0x01,0xff,0x0b,0x54]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// W64: encoding: [0xff,0x0c,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x0e,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[102:103], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x66,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, vcc, v1, v2, s[6:7]
+// W64: encoding: [0x05,0x6a,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0xff,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x80,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0xc1,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0xf0,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0xf7,0x04,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xff,0x1b,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x01,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x83,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xe1,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xef,0x19,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x22,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v2, s[102:103]
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x9a,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s[12:13], v1, v2, vcc
+// W64: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0xaa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e32 v5, vcc_lo, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0x0a,0x54]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v255, vcc_lo, v1, v2, vcc_lo
+// W32: encoding: [0x01,0x05,0xfe,0x55]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc_lo, v255, v2, vcc_lo
+// W32: encoding: [0xff,0x05,0x0a,0x54]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v2, vcc_lo
+// W32: encoding: [0x80,0x04,0x0a,0x54]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc_lo, -1, v2, vcc_lo
+// W32: encoding: [0xc1,0x04,0x0a,0x54]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc_lo, 0.5, v2, vcc_lo
+// W32: encoding: [0xf0,0x04,0x0a,0x54]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc_lo, -4.0, v2, vcc_lo
+// W32: encoding: [0xf7,0x04,0x0a,0x54]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e32 v5, vcc_lo, v1, v255, vcc_lo
+// W32: encoding: [0x01,0xff,0x0b,0x54]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_e64 v5, s12, v1, v2, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v255, s12, v1, v2, s6
+// W32: encoding: [0xff,0x0c,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s14, v1, v2, s6
+// W32: encoding: [0x05,0x0e,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s102, v1, v2, s6
+// W32: encoding: [0x05,0x66,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, vcc_lo, v1, v2, s6
+// W32: encoding: [0x05,0x6a,0x2a,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, v255, v2, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0xff,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, 0, v2, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x80,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, -1, v2, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0xc1,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, 0.5, v2, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0xf0,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, -4.0, v2, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0xf7,0x04,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, v1, v255, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xff,0x1b,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, v1, 0, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x01,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, v1, -1, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x83,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, v1, 0.5, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xe1,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, v1, -4.0, s6
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0xef,0x19,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, v1, v2, s8
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x22,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, v1, v2, s102
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0x9a,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_e64 v5, s12, v1, v2, vcc_lo
+// W32: encoding: [0x05,0x0c,0x2a,0xd5,0x01,0x05,0xaa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x26,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x01,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x02,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x03,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x04,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x05,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x0e,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v255, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v255, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v255, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x26,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x01,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x02,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x03,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x04,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x05,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x0e,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, sext(v1), v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, sext(v2), vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_fmac_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x56]
+
+v_fmac_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x57]
+
+v_fmac_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x56]
+
+v_fmac_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x56]
+
+v_fmac_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x56,0x56,0x34,0x12,0xaf]
+
+v_fmac_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x56,0x73,0x72,0x71,0x3f]
+
+v_fmac_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x56]
+
+v_fmac_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x2b,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0xff,0x05,0x02,0x00]
+
+v_fmac_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x65,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x6a,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x6b,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x7c,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x7e,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x7f,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x80,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0xc1,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0xf0,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0xf7,0x04,0x02,0x00]
+
+v_fmac_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xff,0x03,0x00]
+
+v_fmac_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x00,0x00]
+
+v_fmac_f32_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xcb,0x00,0x00]
+
+v_fmac_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xd5,0x00,0x00]
+
+v_fmac_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xd7,0x00,0x00]
+
+v_fmac_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xf9,0x00,0x00]
+
+v_fmac_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xfd,0x00,0x00]
+
+v_fmac_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xff,0x00,0x00]
+
+v_fmac_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x01,0x01,0x00]
+
+v_fmac_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x83,0x01,0x00]
+
+v_fmac_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xe1,0x01,0x00]
+
+v_fmac_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0xef,0x01,0x00]
+
+v_fmac_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x20]
+
+v_fmac_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x40]
+
+v_fmac_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x60]
+
+v_fmac_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x2b,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x2b,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x2b,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f32_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x2b,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f32_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x08]
+
+v_fmac_f32_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x10]
+
+v_fmac_f32_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x2b,0xd5,0x01,0x05,0x02,0x18]
+
+v_fmamk_f32 v5, v1, 0x11213141, v3
+// GFX10: encoding: [0x01,0x07,0x0a,0x58,0x41,0x31,0x21,0x11]
+
+v_fmamk_f32 v255, v1, 0x11213141, v3
+// GFX10: encoding: [0x01,0x07,0xfe,0x59,0x41,0x31,0x21,0x11]
+
+v_fmamk_f32 v5, v255, 0x11213141, v3
+// GFX10: encoding: [0xff,0x07,0x0a,0x58,0x41,0x31,0x21,0x11]
+
+v_fmamk_f32 v5, 0, 0x11213141, v3
+// GFX10: encoding: [0x80,0x06,0x0a,0x58,0x41,0x31,0x21,0x11]
+
+v_fmamk_f32 v5, -1, 0x11213141, v3
+// GFX10: encoding: [0xc1,0x06,0x0a,0x58,0x41,0x31,0x21,0x11]
+
+v_fmamk_f32 v5, 0.5, 0x11213141, v3
+// GFX10: encoding: [0xf0,0x06,0x0a,0x58,0x41,0x31,0x21,0x11]
+
+v_fmamk_f32 v5, -4.0, 0x11213141, v3
+// GFX10: encoding: [0xf7,0x06,0x0a,0x58,0x41,0x31,0x21,0x11]
+
+v_fmamk_f32 v5, v1, 0xa1b1c1d1, v3
+// GFX10: encoding: [0x01,0x07,0x0a,0x58,0xd1,0xc1,0xb1,0xa1]
+
+v_fmamk_f32 v5, v1, 0x11213141, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x58,0x41,0x31,0x21,0x11]
+
+v_fmaak_f32 v5, v1, v2, 0x11213141
+// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0x41,0x31,0x21,0x11]
+
+v_fmaak_f32 v255, v1, v2, 0x11213141
+// GFX10: encoding: [0x01,0x05,0xfe,0x5b,0x41,0x31,0x21,0x11]
+
+v_fmaak_f32 v5, v255, v2, 0x11213141
+// GFX10: encoding: [0xff,0x05,0x0a,0x5a,0x41,0x31,0x21,0x11]
+
+v_fmaak_f32 v5, 0, v2, 0x11213141
+// GFX10: encoding: [0x80,0x04,0x0a,0x5a,0x41,0x31,0x21,0x11]
+
+v_fmaak_f32 v5, -1, v2, 0x11213141
+// GFX10: encoding: [0xc1,0x04,0x0a,0x5a,0x41,0x31,0x21,0x11]
+
+v_fmaak_f32 v5, 0.5, v2, 0x11213141
+// GFX10: encoding: [0xf0,0x04,0x0a,0x5a,0x41,0x31,0x21,0x11]
+
+v_fmaak_f32 v5, -4.0, v2, 0x11213141
+// GFX10: encoding: [0xf7,0x04,0x0a,0x5a,0x41,0x31,0x21,0x11]
+
+v_fmaak_f32 v5, v1, v255, 0x11213141
+// GFX10: encoding: [0x01,0xff,0x0b,0x5a,0x41,0x31,0x21,0x11]
+
+v_fmaak_f32 v5, v1, v2, 0xa1b1c1d1
+// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xd1,0xc1,0xb1,0xa1]
+
+v_cvt_pkrtz_f16_f32_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x5f]
+
+v_cvt_pkrtz_f16_f32_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32_e32 v5, 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x5e,0x56,0x34,0x12,0xaf]
+
+v_cvt_pkrtz_f16_f32_e32 v5, 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x5e,0x73,0x72,0x71,0x3f]
+
+v_cvt_pkrtz_f16_f32_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x5e]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x2f,0xd5,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0xff,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x67,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x6a,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x6b,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x77,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x7c,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x7e,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x7f,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x80,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0xc1,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0xf0,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0xf7,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xff,0x03,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xcf,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xd5,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xd7,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xef,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xf9,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xfd,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xff,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x01,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x83,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xe1,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0xef,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x20]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x40]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x2f,0xd5,0x01,0x05,0x02,0x60]
+
+v_cvt_pkrtz_f16_f32_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x2f,0xd5,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x2f,0xd5,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x2f,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f16_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x64]
+
+v_add_f16_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x65]
+
+v_add_f16_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x64]
+
+v_add_f16_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x64]
+
+v_add_f16_e32 v5, 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x64,0x0b,0xfe,0x00,0x00]
+
+v_add_f16_e32 v5, 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x64,0x56,0x34,0x00,0x00]
+
+v_add_f16_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x64]
+
+v_add_f16_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x32,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0xff,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x65,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x6a,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x6b,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x7c,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x7e,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x7f,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x80,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0xc1,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0xf0,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0xf7,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xff,0x03,0x00]
+
+v_add_f16_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x00,0x00]
+
+v_add_f16_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xcb,0x00,0x00]
+
+v_add_f16_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xd5,0x00,0x00]
+
+v_add_f16_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xd7,0x00,0x00]
+
+v_add_f16_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xf9,0x00,0x00]
+
+v_add_f16_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xfd,0x00,0x00]
+
+v_add_f16_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xff,0x00,0x00]
+
+v_add_f16_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x01,0x01,0x00]
+
+v_add_f16_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x83,0x01,0x00]
+
+v_add_f16_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xe1,0x01,0x00]
+
+v_add_f16_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0xef,0x01,0x00]
+
+v_add_f16_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x20]
+
+v_add_f16_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x40]
+
+v_add_f16_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x32,0xd5,0x01,0x05,0x02,0x60]
+
+v_add_f16_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x32,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x32,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x32,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x32,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0xff,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x65,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x6a,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x6b,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x7c,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x7e,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x7f,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x64,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x26,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x00,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x01,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x02,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x03,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x04,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x05,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x0e,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x00,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x01,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x02,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x03,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x04,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x05,0x06]
+
+v_add_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x16,0x06]
+
+v_add_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x26,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x00]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x01]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x02]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x03]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x04]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x05]
+
+v_add_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x16]
+
+v_add_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x26]
+
+v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x00]
+
+v_add_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00]
+
+v_add_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0xff,0xe4,0x00,0x00]
+
+v_add_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x64,0x01,0xe4,0x00,0x00]
+
+v_add_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x10]
+
+v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x30]
+
+v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
+
+v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01]
+
+v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
+
+v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
+
+v_add_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
+
+v_add_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x10,0x00]
+
+v_add_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x20,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x51,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x5f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x61,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x64,0x01,0x6f,0x01,0x00]
+
+v_sub_f16_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x66]
+
+v_sub_f16_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x67]
+
+v_sub_f16_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x66]
+
+v_sub_f16_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x66]
+
+v_sub_f16_e32 v5, 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x66,0x0b,0xfe,0x00,0x00]
+
+v_sub_f16_e32 v5, 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x66,0x56,0x34,0x00,0x00]
+
+v_sub_f16_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x66]
+
+v_sub_f16_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x33,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0xff,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x65,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x6a,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x6b,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x7c,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x7e,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x7f,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x80,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0xc1,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0xf0,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0xf7,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xff,0x03,0x00]
+
+v_sub_f16_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xcb,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xd5,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xd7,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xf9,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xfd,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xff,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x01,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x83,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xe1,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0xef,0x01,0x00]
+
+v_sub_f16_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x20]
+
+v_sub_f16_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x40]
+
+v_sub_f16_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x33,0xd5,0x01,0x05,0x02,0x60]
+
+v_sub_f16_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x33,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x33,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x33,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x33,0xd5,0x01,0x05,0x02,0x00]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0xff,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x65,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x6a,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x6b,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x7c,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x7e,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x7f,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x66,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x26,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x00,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x01,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x02,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x03,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x04,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x05,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x0e,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x00,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x01,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x02,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x03,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x04,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x05,0x06]
+
+v_sub_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x16,0x06]
+
+v_sub_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x26,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x00]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x01]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x02]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x03]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x04]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x05]
+
+v_sub_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x16]
+
+v_sub_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x26]
+
+v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0xff,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x66,0x01,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x10]
+
+v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x30]
+
+v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
+
+v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01]
+
+v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
+
+v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
+
+v_sub_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
+
+v_sub_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
+
+v_sub_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x51,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x5f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x61,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x66,0x01,0x6f,0x01,0x00]
+
+v_subrev_f16_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x68]
+
+v_subrev_f16_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x69]
+
+v_subrev_f16_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x68]
+
+v_subrev_f16_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x68]
+
+v_subrev_f16_e32 v5, 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x68,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f16_e32 v5, 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x68,0x56,0x34,0x00,0x00]
+
+v_subrev_f16_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x68]
+
+v_subrev_f16_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x34,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0xff,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x65,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x6a,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x6b,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x7c,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x7e,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x7f,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x80,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0xc1,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0xf0,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0xf7,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x03,0x00]
+
+v_subrev_f16_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xcb,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xd5,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xd7,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xf9,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xfd,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xff,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x01,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x83,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xe1,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0xef,0x01,0x00]
+
+v_subrev_f16_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x20]
+
+v_subrev_f16_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x40]
+
+v_subrev_f16_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x34,0xd5,0x01,0x05,0x02,0x60]
+
+v_subrev_f16_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x34,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x34,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x34,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x34,0xd5,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x69,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0xff,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x65,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x6a,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x6b,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x7c,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x7e,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x7f,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x68,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x26,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x00,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x01,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x02,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x03,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x04,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x05,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x0e,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x16,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x16,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x00,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x01,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x02,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x03,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x04,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x05,0x06]
+
+v_subrev_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x16,0x06]
+
+v_subrev_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x26,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x00]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x01]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x02]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x03]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x04]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x05]
+
+v_subrev_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x16]
+
+v_subrev_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x26]
+
+v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x69,0x01,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0xff,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x68,0x01,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x10]
+
+v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x30]
+
+v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x01]
+
+v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x03]
+
+v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00]
+
+v_subrev_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x10,0x00]
+
+v_subrev_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x20,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x51,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x5f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x61,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x68,0x01,0x6f,0x01,0x00]
+
+v_mul_f16_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x6a]
+
+v_mul_f16_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x6b]
+
+v_mul_f16_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x6a]
+
+v_mul_f16_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x6a]
+
+v_mul_f16_e32 v5, 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x6a,0x0b,0xfe,0x00,0x00]
+
+v_mul_f16_e32 v5, 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x6a,0x56,0x34,0x00,0x00]
+
+v_mul_f16_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x6a]
+
+v_mul_f16_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x35,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x65,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_f16_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xcb,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_f16_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x20]
+
+v_mul_f16_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x40]
+
+v_mul_f16_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x35,0xd5,0x01,0x05,0x02,0x60]
+
+v_mul_f16_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x35,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x35,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x35,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x35,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x6b,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0xff,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x65,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x6a,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x6b,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x7c,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x7e,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x7f,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x6a,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x26,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x00,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x01,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x02,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x03,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x04,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x05,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x0e,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x16,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x16,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x00,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x01,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x02,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x03,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x04,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x05,0x06]
+
+v_mul_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x16,0x06]
+
+v_mul_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x26,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x00]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x01]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x02]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x03]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x04]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x05]
+
+v_mul_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x16]
+
+v_mul_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x26]
+
+v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x6b,0x01,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0xff,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x6a,0x01,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x10]
+
+v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x30]
+
+v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xf0]
+
+v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x01]
+
+v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x03]
+
+v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x0f]
+
+v_mul_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00]
+
+v_mul_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x10,0x00]
+
+v_mul_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x20,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x51,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x5f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x61,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x6a,0x01,0x6f,0x01,0x00]
+
+v_fmac_f16_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x6c]
+
+v_fmac_f16_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x6d]
+
+v_fmac_f16_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x6c]
+
+v_fmac_f16_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x6c]
+
+v_fmac_f16 v5, 0x1234, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x6c,0x34,0x12,0x00,0x00]
+
+v_fmac_f16_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x6c]
+
+v_fmac_f16_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f16_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x36,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f16_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0xff,0x05,0x02,0x00]
+
+v_fmac_f16_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x65,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x6a,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x6b,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x7c,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x7e,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x7f,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x80,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0xc1,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0xf0,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0xf7,0x04,0x02,0x00]
+
+v_fmac_f16_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xff,0x03,0x00]
+
+v_fmac_f16_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x00,0x00]
+
+v_fmac_f16_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xcb,0x00,0x00]
+
+v_fmac_f16_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xd5,0x00,0x00]
+
+v_fmac_f16_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xd7,0x00,0x00]
+
+v_fmac_f16_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xf9,0x00,0x00]
+
+v_fmac_f16_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xfd,0x00,0x00]
+
+v_fmac_f16_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xff,0x00,0x00]
+
+v_fmac_f16_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x01,0x01,0x00]
+
+v_fmac_f16_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x83,0x01,0x00]
+
+v_fmac_f16_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xe1,0x01,0x00]
+
+v_fmac_f16_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0xef,0x01,0x00]
+
+v_fmac_f16_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x20]
+
+v_fmac_f16_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x40]
+
+v_fmac_f16_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x60]
+
+v_fmac_f16_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x36,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f16_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x36,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f16_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x36,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f16_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x36,0xd5,0x01,0x05,0x02,0x00]
+
+v_fmac_f16_e64 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x08]
+
+v_fmac_f16_e64 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x10]
+
+v_fmac_f16_e64 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x36,0xd5,0x01,0x05,0x02,0x18]
+
+v_fmamk_f32 v5, v1, 0x1121, v3
+// GFX10: encoding: [0x01,0x07,0x0a,0x58,0x21,0x11,0x00,0x00]
+
+v_fmamk_f32 v255, v1, 0x1121, v3
+// GFX10: encoding: [0x01,0x07,0xfe,0x59,0x21,0x11,0x00,0x00]
+
+v_fmamk_f32 v5, v255, 0x1121, v3
+// GFX10: encoding: [0xff,0x07,0x0a,0x58,0x21,0x11,0x00,0x00]
+
+v_fmamk_f32 v5, 0, 0x1121, v3
+// GFX10: encoding: [0x80,0x06,0x0a,0x58,0x21,0x11,0x00,0x00]
+
+v_fmamk_f32 v5, -1, 0x1121, v3
+// GFX10: encoding: [0xc1,0x06,0x0a,0x58,0x21,0x11,0x00,0x00]
+
+v_fmamk_f32 v5, 0.5, 0x1121, v3
+// GFX10: encoding: [0xf0,0x06,0x0a,0x58,0x21,0x11,0x00,0x00]
+
+v_fmamk_f32 v5, -4.0, 0x1121, v3
+// GFX10: encoding: [0xf7,0x06,0x0a,0x58,0x21,0x11,0x00,0x00]
+
+v_fmamk_f32 v5, v1, 0xa1b1, v3
+// GFX10: encoding: [0x01,0x07,0x0a,0x58,0xb1,0xa1,0x00,0x00]
+
+v_fmamk_f32 v5, v1, 0x1121, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x58,0x21,0x11,0x00,0x00]
+
+v_fmaak_f32 v5, v1, v2, 0x1121
+// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0x21,0x11,0x00,0x00]
+
+v_fmaak_f32 v255, v1, v2, 0x1121
+// GFX10: encoding: [0x01,0x05,0xfe,0x5b,0x21,0x11,0x00,0x00]
+
+v_fmaak_f32 v5, v255, v2, 0x1121
+// GFX10: encoding: [0xff,0x05,0x0a,0x5a,0x21,0x11,0x00,0x00]
+
+v_fmaak_f32 v5, 0, v2, 0x1121
+// GFX10: encoding: [0x80,0x04,0x0a,0x5a,0x21,0x11,0x00,0x00]
+
+v_fmaak_f32 v5, -1, v2, 0x1121
+// GFX10: encoding: [0xc1,0x04,0x0a,0x5a,0x21,0x11,0x00,0x00]
+
+v_fmaak_f32 v5, 0.5, v2, 0x1121
+// GFX10: encoding: [0xf0,0x04,0x0a,0x5a,0x21,0x11,0x00,0x00]
+
+v_fmaak_f32 v5, -4.0, v2, 0x1121
+// GFX10: encoding: [0xf7,0x04,0x0a,0x5a,0x21,0x11,0x00,0x00]
+
+v_fmaak_f32 v5, v1, v255, 0x1121
+// GFX10: encoding: [0x01,0xff,0x0b,0x5a,0x21,0x11,0x00,0x00]
+
+v_fmaak_f32 v5, v1, v2, 0xa1b1
+// GFX10: encoding: [0x01,0x05,0x0a,0x5a,0xb1,0xa1,0x00,0x00]
+
+v_max_f16_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x72]
+
+v_max_f16_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x73]
+
+v_max_f16_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x72]
+
+v_max_f16_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x72]
+
+v_max_f16_e32 v5, 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x72,0x0b,0xfe,0x00,0x00]
+
+v_max_f16_e32 v5, 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x72,0x56,0x34,0x00,0x00]
+
+v_max_f16_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x72]
+
+v_max_f16_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x39,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0xff,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x65,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x6a,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x6b,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x7c,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x7e,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x7f,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x80,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0xc1,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0xf0,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0xf7,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xff,0x03,0x00]
+
+v_max_f16_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x00,0x00]
+
+v_max_f16_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xcb,0x00,0x00]
+
+v_max_f16_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xd5,0x00,0x00]
+
+v_max_f16_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xd7,0x00,0x00]
+
+v_max_f16_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xf9,0x00,0x00]
+
+v_max_f16_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xfd,0x00,0x00]
+
+v_max_f16_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xff,0x00,0x00]
+
+v_max_f16_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x01,0x01,0x00]
+
+v_max_f16_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x83,0x01,0x00]
+
+v_max_f16_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xe1,0x01,0x00]
+
+v_max_f16_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0xef,0x01,0x00]
+
+v_max_f16_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x02,0x20]
+
+v_max_f16_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x02,0x40]
+
+v_max_f16_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x39,0xd5,0x01,0x05,0x02,0x60]
+
+v_max_f16_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x39,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x39,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x39,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x39,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x73,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0xff,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x65,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x6a,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x6b,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x7c,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x7e,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x7f,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x72,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x26,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x00,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x01,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x02,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x03,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x04,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x05,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x0e,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x16,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x16,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x00,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x01,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x02,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x03,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x04,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x05,0x06]
+
+v_max_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x16,0x06]
+
+v_max_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x26,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x00]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x01]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x02]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x03]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x04]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x05]
+
+v_max_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x16]
+
+v_max_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x72,0x01,0x06,0x06,0x26]
+
+v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x00]
+
+v_max_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x73,0x01,0xe4,0x00,0x00]
+
+v_max_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0xff,0xe4,0x00,0x00]
+
+v_max_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x72,0x01,0xe4,0x00,0x00]
+
+v_max_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x40,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x41,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x01,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x0f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x11,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x1f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x21,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x2f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x10]
+
+v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x30]
+
+v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0xf0]
+
+v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x01]
+
+v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x03]
+
+v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x00,0x0f]
+
+v_max_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x08,0x00]
+
+v_max_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x10,0x00]
+
+v_max_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0xe4,0x20,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x51,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x5f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x61,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x72,0x01,0x6f,0x01,0x00]
+
+v_min_f16_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x74]
+
+v_min_f16_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x75]
+
+v_min_f16_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x74]
+
+v_min_f16_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x74]
+
+v_min_f16_e32 v5, 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x74,0x0b,0xfe,0x00,0x00]
+
+v_min_f16_e32 v5, 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x74,0x56,0x34,0x00,0x00]
+
+v_min_f16_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x74]
+
+v_min_f16_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x3a,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0xff,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x65,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x6a,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x6b,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x7c,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x7e,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x7f,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x80,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0xc1,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0xf0,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0xf7,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xff,0x03,0x00]
+
+v_min_f16_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x00,0x00]
+
+v_min_f16_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xcb,0x00,0x00]
+
+v_min_f16_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xd5,0x00,0x00]
+
+v_min_f16_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xd7,0x00,0x00]
+
+v_min_f16_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xf9,0x00,0x00]
+
+v_min_f16_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xfd,0x00,0x00]
+
+v_min_f16_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xff,0x00,0x00]
+
+v_min_f16_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x01,0x01,0x00]
+
+v_min_f16_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x83,0x01,0x00]
+
+v_min_f16_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xe1,0x01,0x00]
+
+v_min_f16_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0xef,0x01,0x00]
+
+v_min_f16_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x02,0x20]
+
+v_min_f16_e64 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x02,0x40]
+
+v_min_f16_e64 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x3a,0xd5,0x01,0x05,0x02,0x60]
+
+v_min_f16_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x3a,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x3a,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x3a,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x3a,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x75,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0xff,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x65,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x6a,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x6b,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x7c,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x7e,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x7f,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x74,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x26,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x00,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x01,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x02,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x03,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x04,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x05,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x0e,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x16,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x16,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x00,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x01,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x02,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x03,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x04,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x05,0x06]
+
+v_min_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x16,0x06]
+
+v_min_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x26,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x00]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x01]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x02]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x03]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x04]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x05]
+
+v_min_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x16]
+
+v_min_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x74,0x01,0x06,0x06,0x26]
+
+v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x00]
+
+v_min_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x75,0x01,0xe4,0x00,0x00]
+
+v_min_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0xff,0xe4,0x00,0x00]
+
+v_min_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x74,0x01,0xe4,0x00,0x00]
+
+v_min_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x40,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x41,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x01,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x0f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x11,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x1f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x21,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x2f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x10]
+
+v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x30]
+
+v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0xf0]
+
+v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x01]
+
+v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x03]
+
+v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x00,0x0f]
+
+v_min_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x08,0x00]
+
+v_min_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x10,0x00]
+
+v_min_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0xe4,0x20,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x51,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x5f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x61,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x74,0x01,0x6f,0x01,0x00]
+
+v_ldexp_f16_e32 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x76]
+
+v_ldexp_f16_e32 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x77]
+
+v_ldexp_f16_e32 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, s101, v2
+// GFX10: encoding: [0x65,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x76]
+
+v_ldexp_f16_e32 v5, 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x76,0x0b,0xfe,0x00,0x00]
+
+v_ldexp_f16_e32 v5, 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x0a,0x76,0x56,0x34,0x00,0x00]
+
+v_ldexp_f16_e32 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x76]
+
+v_ldexp_f16_e64 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x3b,0xd5,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0xff,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x65,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x6b,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x7c,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x7f,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x80,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xff,0x03,0x00]
+
+v_ldexp_f16_e64 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x05,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xcb,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xff,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x01,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x83,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0xef,0x01,0x00]
+
+v_ldexp_f16_e64 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x3b,0xd5,0x01,0x05,0x02,0x20]
+
+v_ldexp_f16_e64 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x3b,0xd5,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x3b,0xd5,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x77,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0xff,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x65,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x6a,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x6b,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x7c,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x7e,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x7f,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x0b,0x76,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x26,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x00,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x01,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x02,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x03,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x04,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x05,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x0e,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x16,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x16,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x00,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x01,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x02,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x03,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x04,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x05,0x06]
+
+v_ldexp_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x16,0x06]
+
+v_ldexp_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x26,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x00]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x01]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x02]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x03]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x04]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x06,0x05]
+
+v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v255, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0xfe,0x77,0x01,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v255, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0xff,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v1, v255  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0xfe,0x0b,0x76,0x01,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x40,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_half_mirror row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x41,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_shl:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x01,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_shl:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x0f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_shr:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x11,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_shr:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x1f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_ror:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x21,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_ror:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x2f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x10]
+
+v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x30]
+
+v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0xf0]
+
+v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x01]
+
+v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x03]
+
+v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x00,0x0f]
+
+v_ldexp_f16_dpp v5, v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x08,0x00]
+
+v_ldexp_f16_dpp v5, -v1, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x10,0x00]
+
+v_ldexp_f16_dpp v5, |v1|, v2  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0xe4,0x20,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_share:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x51,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2  row_share:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x5f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_xmask:1 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x61,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
+// GFX10: encoding: [0xfa,0x04,0x0a,0x76,0x01,0x6f,0x01,0x00]
+
+v_pk_fmac_f16 v5, v1, v2
+// GFX10: encoding: [0x01,0x05,0x0a,0x78]
+
+v_pk_fmac_f16 v255, v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x79]
+
+v_pk_fmac_f16 v5, v255, v2
+// GFX10: encoding: [0xff,0x05,0x0a,0x78]
+
+v_pk_fmac_f16 v5, s1, v2
+// GFX10: encoding: [0x01,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, s103, v2
+// GFX10: encoding: [0x67,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, ttmp11, v2
+// GFX10: encoding: [0x77,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, m0, v2
+// GFX10: encoding: [0x7c,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, 0, v2
+// GFX10: encoding: [0x80,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, -1, v2
+// GFX10: encoding: [0xc1,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x0a,0x78]
+
+v_pk_fmac_f16 v5, v1, v255
+// GFX10: encoding: [0x01,0xff,0x0b,0x78]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
new file mode 100644
index 0000000000000..a4f77a4bbaad9
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vop3.s
@@ -0,0 +1,13141 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W64-ERR --implicit-check-not=error: %s
+
+//===----------------------------------------------------------------------===//
+// ENC_VOP3.
+//===----------------------------------------------------------------------===//
+
+v_readlane_b32 s5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 s101, v1, s2
+// GFX10: encoding: [0x65,0x00,0x60,0xd7,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 s5, v255, s2
+// GFX10: encoding: [0x05,0x00,0x60,0xd7,0xff,0x05,0x00,0x00]
+
+v_readlane_b32 s5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0xcb,0x00,0x00]
+
+v_readlane_b32 s5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0xd5,0x00,0x00]
+
+v_readlane_b32 s5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0xd7,0x00,0x00]
+
+v_readlane_b32 s5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0xf9,0x00,0x00]
+
+v_readlane_b32 s5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x60,0xd7,0x01,0x01,0x01,0x00]
+
+v_writelane_b32 v5, 0, s2
+// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
+
+v_writelane_b32 v255, 0, s2
+// GFX10: encoding: [0xff,0x00,0x61,0xd7,0x80,0x04,0x00,0x00]
+
+v_writelane_b32 v5, -1, s2
+// GFX10: encoding: [0x05,0x00,0x61,0xd7,0xc1,0x04,0x00,0x00]
+
+v_writelane_b32 v5, 0.5, s2
+// GFX10: encoding: [0x05,0x00,0x61,0xd7,0xf0,0x04,0x00,0x00]
+
+v_writelane_b32 v5, -4.0, s2
+// GFX10: encoding: [0x05,0x00,0x61,0xd7,0xf7,0x04,0x00,0x00]
+
+v_writelane_b32 v5, 0, s101
+// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0xca,0x00,0x00]
+
+v_writelane_b32 v5, 0, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0xd4,0x00,0x00]
+
+v_writelane_b32 v5, 0, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0xd6,0x00,0x00]
+
+v_writelane_b32 v5, 0, m0
+// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0xf8,0x00,0x00]
+
+v_writelane_b32 v5, 0, 0
+// GFX10: encoding: [0x05,0x00,0x61,0xd7,0x80,0x00,0x01,0x00]
+
+v_bfm_b32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
+
+v_bfm_b32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
+
+v_bfm_b32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0xff,0x05,0x02,0x00]
+
+v_bfm_b32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x04,0x02,0x00]
+
+v_bfm_b32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x67,0x04,0x02,0x00]
+
+v_bfm_b32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x6a,0x04,0x02,0x00]
+
+v_bfm_b32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x6b,0x04,0x02,0x00]
+
+v_bfm_b32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x77,0x04,0x02,0x00]
+
+v_bfm_b32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x7c,0x04,0x02,0x00]
+
+v_bfm_b32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x7e,0x04,0x02,0x00]
+
+v_bfm_b32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x7f,0x04,0x02,0x00]
+
+v_bfm_b32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x80,0x04,0x02,0x00]
+
+v_bfm_b32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0xc1,0x04,0x02,0x00]
+
+v_bfm_b32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0xf0,0x04,0x02,0x00]
+
+v_bfm_b32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0xf7,0x04,0x02,0x00]
+
+v_bfm_b32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xff,0x03,0x00]
+
+v_bfm_b32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x00,0x00]
+
+v_bfm_b32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xcf,0x00,0x00]
+
+v_bfm_b32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xd5,0x00,0x00]
+
+v_bfm_b32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xd7,0x00,0x00]
+
+v_bfm_b32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xef,0x00,0x00]
+
+v_bfm_b32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xf9,0x00,0x00]
+
+v_bfm_b32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xfd,0x00,0x00]
+
+v_bfm_b32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xff,0x00,0x00]
+
+v_bfm_b32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x01,0x01,0x00]
+
+v_bfm_b32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0x83,0x01,0x00]
+
+v_bfm_b32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xe1,0x01,0x00]
+
+v_bfm_b32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x63,0xd7,0x01,0xef,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0xff,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x67,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x6a,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x6b,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x77,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x7c,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x7e,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x7f,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x80,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0xc1,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0xf0,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0xf7,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xff,0x03,0x00]
+
+v_bcnt_u32_b32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xcf,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xd5,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xd7,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xef,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xf9,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xfd,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xff,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x01,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0x83,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xe1,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x64,0xd7,0x01,0xef,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x65,0xd7,0x01,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0xff,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x67,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x6a,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x6b,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x77,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x7c,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x7e,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x7f,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x80,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0xc1,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0xf0,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0xf7,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xff,0x03,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xcf,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xd5,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xd7,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xef,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xf9,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xfd,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xff,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x01,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0x83,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xe1,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x65,0xd7,0x01,0xef,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x66,0xd7,0x01,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0xff,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x67,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x6a,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x6b,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x77,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x7c,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x7e,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x7f,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x80,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0xc1,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0xf0,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0xf7,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xff,0x03,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xcf,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xd5,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xd7,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xef,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xf9,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xfd,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xff,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x01,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0x83,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xe1,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x66,0xd7,0x01,0xef,0x01,0x00]
+
+v_add_co_u32 v5, s0, v1, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v255, s0, v1, v2
+// W32: encoding: [0xff,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v255, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, s1, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, s103, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x67,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, vcc_lo, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, vcc_hi, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, ttmp11, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x77,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, m0, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, exec_lo, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, exec_hi, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, 0, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, -1, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, 0.5, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, -4.0, v2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, v255
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, s2
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, s103
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xcf,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, vcc_lo
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, vcc_hi
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, ttmp11
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, m0
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, exec_lo
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, exec_hi
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, 0
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, -1
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, 0.5
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s0, v1, -4.0
+// W32: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v255, s[0:1], v1, v2
+// W64: encoding: [0xff,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v255, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], s1, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], s103, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x67,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], vcc_lo, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], vcc_hi, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], ttmp11, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x77,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], m0, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], exec_lo, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], exec_hi, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], 0, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], -1, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], 0.5, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], -4.0, v2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, v255
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, s2
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, s103
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xcf,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, vcc_lo
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, vcc_hi
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, ttmp11
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, m0
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, exec_lo
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, exec_hi
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, 0
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, -1
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, 0.5
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_add_co_u32 v5, s[0:1], v1, -4.0
+// W64: encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v255, s0, v1, v2
+// W32: encoding: [0xff,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v255, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, s1, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, s103, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x67,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, vcc_lo, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, vcc_hi, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, ttmp11, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x77,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, m0, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, exec_lo, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, exec_hi, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, 0, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, -1, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, 0.5, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, -4.0, v2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, v255
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, s2
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, s103
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xcf,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, vcc_lo
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, vcc_hi
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, ttmp11
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, m0
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, exec_lo
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, exec_hi
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, 0
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, -1
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, 0.5
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s0, v1, -4.0
+// W32: encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v255, s[0:1], v1, v2
+// W64: encoding: [0xff,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v255, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], s1, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], s103, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x67,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], vcc_lo, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], vcc_hi, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], ttmp11, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x77,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], m0, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], exec_lo, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], exec_hi, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], 0, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], -1, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], 0.5, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], -4.0, v2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, v255
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, s2
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, s103
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xcf,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, vcc_lo
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, vcc_hi
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, ttmp11
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, m0
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, exec_lo
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, exec_hi
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, 0
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, -1
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, 0.5
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_sub_co_u32 v5, s[0:1], v1, -4.0
+// W64: encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v255, s0, v1, v2
+// W32: encoding: [0xff,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v255, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, s1, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, s103, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x67,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, vcc_lo, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, vcc_hi, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, ttmp11, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x77,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, m0, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, exec_lo, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, exec_hi, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, 0, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, -1, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, 0.5, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, -4.0, v2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, v255
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, s2
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, s103
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xcf,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, vcc_lo
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, vcc_hi
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, ttmp11
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, m0
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, exec_lo
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, exec_hi
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, 0
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, -1
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, 0.5
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s0, v1, -4.0
+// W32: encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v255, s[0:1], v1, v2
+// W64: encoding: [0xff,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v255, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], s1, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], s103, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x67,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], vcc_lo, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], vcc_hi, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], ttmp11, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x77,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], m0, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], exec_lo, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], exec_hi, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], 0, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], -1, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], 0.5, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], -4.0, v2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, v255
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, s2
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, s103
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xcf,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, vcc_lo
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, vcc_hi
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, ttmp11
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, m0
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, exec_lo
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, exec_hi
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, 0
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, -1
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, 0.5
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_subrev_co_u32 v5, s[0:1], v1, -4.0
+// W64: encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_ldexp_f32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0xff,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x67,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x6b,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x77,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x7c,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x7f,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x80,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xff,0x03,0x00]
+
+v_ldexp_f32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x00,0x00]
+
+v_ldexp_f32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xef,0x00,0x00]
+
+v_ldexp_f32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xff,0x00,0x00]
+
+v_ldexp_f32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x01,0x01,0x00]
+
+v_ldexp_f32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x83,0x01,0x00]
+
+v_ldexp_f32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0xef,0x01,0x00]
+
+v_ldexp_f32 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x20]
+
+v_ldexp_f32 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x62,0xd7,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x62,0xd7,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v1, v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x08]
+
+v_ldexp_f32 v5, v1, v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x10]
+
+v_ldexp_f32 v5, v1, v2 div:2
+// GFX10: encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x18]
+
+v_cvt_pknorm_i16_f32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x68,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x77,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xef,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_i16_f32 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_i16_f32 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_i16_f32 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x68,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x68,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x68,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x68,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x69,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x77,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xef,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_u16_f32 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_u16_f32 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_u16_f32 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x69,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x69,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x69,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, v2 clamp
+// GFX10: encoding: [0x05,0x80,0x69,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0xff,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x67,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x6a,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x6b,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x77,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x7c,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x7e,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x7f,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x80,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0xc1,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0xf0,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0xf7,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xff,0x03,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x05,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xcf,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xd5,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xd7,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xef,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xf9,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xfd,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xff,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x01,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0x83,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xe1,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x6a,0xd7,0x01,0xef,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0xff,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x67,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x6a,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x6b,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x77,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x7c,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x7e,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x7f,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x80,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0xc1,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0xf0,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0xf7,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xff,0x03,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x05,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xcf,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xd5,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xd7,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xef,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xf9,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xfd,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xff,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x01,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0x83,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xe1,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x6b,0xd7,0x01,0xef,0x01,0x00]
+
+v_mad_legacy_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x40,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0xff,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x67,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x77,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xff,0x0f,0x04]
+
+v_mad_legacy_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xef,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xff,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x01,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0xef,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xfe,0x07]
+
+v_mad_legacy_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x00]
+
+v_mad_legacy_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x9e,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xaa,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xae,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xde,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xf2,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xfa,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xfe,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x02,0x02]
+
+v_mad_legacy_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x06,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xc2,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0xde,0x03]
+
+v_mad_legacy_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x24]
+
+v_mad_legacy_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x44]
+
+v_mad_legacy_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x84]
+
+v_mad_legacy_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_mad_legacy_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x40,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x40,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x40,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x40,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x40,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_mad_legacy_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x14]
+
+v_mad_legacy_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x40,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_mad_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x41,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0xff,0x05,0x0e,0x04]
+
+v_mad_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x04,0x0e,0x04]
+
+v_mad_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x67,0x04,0x0e,0x04]
+
+v_mad_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_mad_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_mad_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x77,0x04,0x0e,0x04]
+
+v_mad_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_mad_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_mad_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_mad_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x80,0x04,0x0e,0x04]
+
+v_mad_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_mad_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_mad_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_mad_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xff,0x0f,0x04]
+
+v_mad_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0c,0x04]
+
+v_mad_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_mad_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_mad_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_mad_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xef,0x0c,0x04]
+
+v_mad_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_mad_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_mad_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xff,0x0c,0x04]
+
+v_mad_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x01,0x0d,0x04]
+
+v_mad_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x83,0x0d,0x04]
+
+v_mad_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_mad_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0xef,0x0d,0x04]
+
+v_mad_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xfe,0x07]
+
+v_mad_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x00]
+
+v_mad_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x9e,0x01]
+
+v_mad_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xaa,0x01]
+
+v_mad_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xae,0x01]
+
+v_mad_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xde,0x01]
+
+v_mad_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xf2,0x01]
+
+v_mad_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xfa,0x01]
+
+v_mad_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xfe,0x01]
+
+v_mad_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x02,0x02]
+
+v_mad_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x06,0x03]
+
+v_mad_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xc2,0x03]
+
+v_mad_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0xde,0x03]
+
+v_mad_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x24]
+
+v_mad_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x44]
+
+v_mad_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x84]
+
+v_mad_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_mad_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x41,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x41,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x41,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x41,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x41,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_mad_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x14]
+
+v_mad_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x41,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_mad_i32_i24 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x42,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0xff,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x67,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x77,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x80,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xff,0x0f,0x04]
+
+v_mad_i32_i24 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xef,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xff,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x01,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x83,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0xef,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xfe,0x07]
+
+v_mad_i32_i24 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x0e,0x00]
+
+v_mad_i32_i24 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x9e,0x01]
+
+v_mad_i32_i24 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xaa,0x01]
+
+v_mad_i32_i24 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xae,0x01]
+
+v_mad_i32_i24 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xde,0x01]
+
+v_mad_i32_i24 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xf2,0x01]
+
+v_mad_i32_i24 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xfa,0x01]
+
+v_mad_i32_i24 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xfe,0x01]
+
+v_mad_i32_i24 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x02,0x02]
+
+v_mad_i32_i24 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0x06,0x03]
+
+v_mad_i32_i24 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xc2,0x03]
+
+v_mad_i32_i24 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x42,0xd5,0x01,0x05,0xde,0x03]
+
+v_mad_u32_u24 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x43,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0xff,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x67,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x77,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x80,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xff,0x0f,0x04]
+
+v_mad_u32_u24 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xef,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xff,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x01,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x83,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0xef,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xfe,0x07]
+
+v_mad_u32_u24 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x0e,0x00]
+
+v_mad_u32_u24 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x9e,0x01]
+
+v_mad_u32_u24 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xaa,0x01]
+
+v_mad_u32_u24 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xae,0x01]
+
+v_mad_u32_u24 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xde,0x01]
+
+v_mad_u32_u24 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xf2,0x01]
+
+v_mad_u32_u24 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xfa,0x01]
+
+v_mad_u32_u24 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xfe,0x01]
+
+v_mad_u32_u24 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x02,0x02]
+
+v_mad_u32_u24 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0x06,0x03]
+
+v_mad_u32_u24 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xc2,0x03]
+
+v_mad_u32_u24 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x43,0xd5,0x01,0x05,0xde,0x03]
+
+v_cubeid_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x44,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0xff,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x67,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x77,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x80,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xff,0x0f,0x04]
+
+v_cubeid_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xef,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xff,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x01,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x83,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0xef,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xfe,0x07]
+
+v_cubeid_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x00]
+
+v_cubeid_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x9e,0x01]
+
+v_cubeid_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xaa,0x01]
+
+v_cubeid_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xae,0x01]
+
+v_cubeid_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xde,0x01]
+
+v_cubeid_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xf2,0x01]
+
+v_cubeid_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xfa,0x01]
+
+v_cubeid_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xfe,0x01]
+
+v_cubeid_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x02,0x02]
+
+v_cubeid_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x06,0x03]
+
+v_cubeid_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xc2,0x03]
+
+v_cubeid_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0xde,0x03]
+
+v_cubeid_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x24]
+
+v_cubeid_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x44]
+
+v_cubeid_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x84]
+
+v_cubeid_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_cubeid_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x44,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x44,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x44,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x44,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x44,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_cubeid_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x14]
+
+v_cubeid_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x44,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_cubesc_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x45,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0xff,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x67,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x77,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x80,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xff,0x0f,0x04]
+
+v_cubesc_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xef,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xff,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x01,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x83,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0xef,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xfe,0x07]
+
+v_cubesc_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x00]
+
+v_cubesc_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x9e,0x01]
+
+v_cubesc_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xaa,0x01]
+
+v_cubesc_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xae,0x01]
+
+v_cubesc_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xde,0x01]
+
+v_cubesc_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xf2,0x01]
+
+v_cubesc_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xfa,0x01]
+
+v_cubesc_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xfe,0x01]
+
+v_cubesc_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x02,0x02]
+
+v_cubesc_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x06,0x03]
+
+v_cubesc_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xc2,0x03]
+
+v_cubesc_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0xde,0x03]
+
+v_cubesc_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x24]
+
+v_cubesc_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x44]
+
+v_cubesc_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x84]
+
+v_cubesc_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_cubesc_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x45,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x45,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x45,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x45,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x45,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_cubesc_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x14]
+
+v_cubesc_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x45,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_cubetc_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x46,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0xff,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x67,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x77,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x80,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xff,0x0f,0x04]
+
+v_cubetc_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xef,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xff,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x01,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x83,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0xef,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xfe,0x07]
+
+v_cubetc_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x00]
+
+v_cubetc_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x9e,0x01]
+
+v_cubetc_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xaa,0x01]
+
+v_cubetc_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xae,0x01]
+
+v_cubetc_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xde,0x01]
+
+v_cubetc_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xf2,0x01]
+
+v_cubetc_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xfa,0x01]
+
+v_cubetc_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xfe,0x01]
+
+v_cubetc_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x02,0x02]
+
+v_cubetc_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x06,0x03]
+
+v_cubetc_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xc2,0x03]
+
+v_cubetc_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0xde,0x03]
+
+v_cubetc_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x24]
+
+v_cubetc_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x44]
+
+v_cubetc_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x84]
+
+v_cubetc_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_cubetc_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x46,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x46,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x46,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x46,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x46,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_cubetc_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x14]
+
+v_cubetc_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x46,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_cubema_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x47,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0xff,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x67,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x77,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x80,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xff,0x0f,0x04]
+
+v_cubema_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0c,0x04]
+
+v_cubema_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_cubema_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_cubema_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_cubema_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xef,0x0c,0x04]
+
+v_cubema_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_cubema_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_cubema_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xff,0x0c,0x04]
+
+v_cubema_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x01,0x0d,0x04]
+
+v_cubema_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x83,0x0d,0x04]
+
+v_cubema_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_cubema_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0xef,0x0d,0x04]
+
+v_cubema_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xfe,0x07]
+
+v_cubema_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x00]
+
+v_cubema_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x9e,0x01]
+
+v_cubema_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xaa,0x01]
+
+v_cubema_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xae,0x01]
+
+v_cubema_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xde,0x01]
+
+v_cubema_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xf2,0x01]
+
+v_cubema_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xfa,0x01]
+
+v_cubema_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xfe,0x01]
+
+v_cubema_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x02,0x02]
+
+v_cubema_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x06,0x03]
+
+v_cubema_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xc2,0x03]
+
+v_cubema_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0xde,0x03]
+
+v_cubema_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x24]
+
+v_cubema_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x44]
+
+v_cubema_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x84]
+
+v_cubema_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_cubema_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x47,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x47,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x47,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x47,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x47,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_cubema_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x14]
+
+v_cubema_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x47,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_bfe_u32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x0e,0x04]
+
+v_bfe_u32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x48,0xd5,0x01,0x05,0x0e,0x04]
+
+v_bfe_u32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0xff,0x05,0x0e,0x04]
+
+v_bfe_u32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x67,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x77,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x80,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xff,0x0f,0x04]
+
+v_bfe_u32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x0c,0x04]
+
+v_bfe_u32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_bfe_u32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_bfe_u32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_bfe_u32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xef,0x0c,0x04]
+
+v_bfe_u32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_bfe_u32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_bfe_u32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xff,0x0c,0x04]
+
+v_bfe_u32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x01,0x0d,0x04]
+
+v_bfe_u32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x83,0x0d,0x04]
+
+v_bfe_u32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_bfe_u32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0xef,0x0d,0x04]
+
+v_bfe_u32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xfe,0x07]
+
+v_bfe_u32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x0e,0x00]
+
+v_bfe_u32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x9e,0x01]
+
+v_bfe_u32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xaa,0x01]
+
+v_bfe_u32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xae,0x01]
+
+v_bfe_u32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xde,0x01]
+
+v_bfe_u32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xf2,0x01]
+
+v_bfe_u32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xfa,0x01]
+
+v_bfe_u32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xfe,0x01]
+
+v_bfe_u32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x02,0x02]
+
+v_bfe_u32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0x06,0x03]
+
+v_bfe_u32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xc2,0x03]
+
+v_bfe_u32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x48,0xd5,0x01,0x05,0xde,0x03]
+
+v_bfe_i32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x0e,0x04]
+
+v_bfe_i32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x49,0xd5,0x01,0x05,0x0e,0x04]
+
+v_bfe_i32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0xff,0x05,0x0e,0x04]
+
+v_bfe_i32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x67,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x77,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x80,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xff,0x0f,0x04]
+
+v_bfe_i32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x0c,0x04]
+
+v_bfe_i32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_bfe_i32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_bfe_i32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_bfe_i32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xef,0x0c,0x04]
+
+v_bfe_i32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_bfe_i32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_bfe_i32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xff,0x0c,0x04]
+
+v_bfe_i32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x01,0x0d,0x04]
+
+v_bfe_i32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x83,0x0d,0x04]
+
+v_bfe_i32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_bfe_i32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0xef,0x0d,0x04]
+
+v_bfe_i32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xfe,0x07]
+
+v_bfe_i32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x0e,0x00]
+
+v_bfe_i32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x9e,0x01]
+
+v_bfe_i32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xaa,0x01]
+
+v_bfe_i32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xae,0x01]
+
+v_bfe_i32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xde,0x01]
+
+v_bfe_i32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xf2,0x01]
+
+v_bfe_i32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xfa,0x01]
+
+v_bfe_i32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xfe,0x01]
+
+v_bfe_i32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x02,0x02]
+
+v_bfe_i32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0x06,0x03]
+
+v_bfe_i32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xc2,0x03]
+
+v_bfe_i32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x49,0xd5,0x01,0x05,0xde,0x03]
+
+v_bfi_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x0e,0x04]
+
+v_bfi_b32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x4a,0xd5,0x01,0x05,0x0e,0x04]
+
+v_bfi_b32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0xff,0x05,0x0e,0x04]
+
+v_bfi_b32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x67,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x77,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x80,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xff,0x0f,0x04]
+
+v_bfi_b32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x0c,0x04]
+
+v_bfi_b32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_bfi_b32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_bfi_b32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_bfi_b32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xef,0x0c,0x04]
+
+v_bfi_b32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_bfi_b32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_bfi_b32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xff,0x0c,0x04]
+
+v_bfi_b32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x01,0x0d,0x04]
+
+v_bfi_b32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x83,0x0d,0x04]
+
+v_bfi_b32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_bfi_b32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0xef,0x0d,0x04]
+
+v_bfi_b32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xfe,0x07]
+
+v_bfi_b32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x0e,0x00]
+
+v_bfi_b32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x9e,0x01]
+
+v_bfi_b32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xaa,0x01]
+
+v_bfi_b32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xae,0x01]
+
+v_bfi_b32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xde,0x01]
+
+v_bfi_b32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xf2,0x01]
+
+v_bfi_b32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xfa,0x01]
+
+v_bfi_b32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xfe,0x01]
+
+v_bfi_b32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x02,0x02]
+
+v_bfi_b32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0x06,0x03]
+
+v_bfi_b32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xc2,0x03]
+
+v_bfi_b32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x4a,0xd5,0x01,0x05,0xde,0x03]
+
+v_fma_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0xff,0x05,0x0e,0x04]
+
+v_fma_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x04,0x0e,0x04]
+
+v_fma_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x67,0x04,0x0e,0x04]
+
+v_fma_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_fma_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_fma_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x77,0x04,0x0e,0x04]
+
+v_fma_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_fma_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_fma_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_fma_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x80,0x04,0x0e,0x04]
+
+v_fma_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_fma_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_fma_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_fma_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xff,0x0f,0x04]
+
+v_fma_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0c,0x04]
+
+v_fma_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_fma_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_fma_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_fma_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xef,0x0c,0x04]
+
+v_fma_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_fma_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_fma_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xff,0x0c,0x04]
+
+v_fma_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x01,0x0d,0x04]
+
+v_fma_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x83,0x0d,0x04]
+
+v_fma_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_fma_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0xef,0x0d,0x04]
+
+v_fma_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xfe,0x07]
+
+v_fma_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x00]
+
+v_fma_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x9e,0x01]
+
+v_fma_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xaa,0x01]
+
+v_fma_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xae,0x01]
+
+v_fma_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xde,0x01]
+
+v_fma_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xf2,0x01]
+
+v_fma_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xfa,0x01]
+
+v_fma_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xfe,0x01]
+
+v_fma_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x02,0x02]
+
+v_fma_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x06,0x03]
+
+v_fma_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xc2,0x03]
+
+v_fma_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0xde,0x03]
+
+v_fma_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x24]
+
+v_fma_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x44]
+
+v_fma_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x84]
+
+v_fma_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_fma_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x4b,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x4b,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x4b,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x4b,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x4b,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_fma_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x14]
+
+v_fma_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x4b,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// GFX10: encoding: [0xfe,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0xfe,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[2:3], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x02,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[4:5], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x04,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[102:103], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x66,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], vcc, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x76,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], exec, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], 0, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x80,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], -1, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xfd,0x0f,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[4:5], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x09,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[6:7], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x0d,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[102:103], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xcd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], vcc, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xed,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], exec, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], 0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x01,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], -1, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x83,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0xef,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xfa,0x07]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[6:7]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x1a,0x00]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[8:9]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x22,0x00]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[102:103]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x9a,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], vcc
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xaa,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xda,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], exec
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xfa,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], 0
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x02,0x02]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -1
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x06,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], 0.5
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xc2,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -4.0
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0xde,0x03]
+
+v_fma_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x24]
+
+v_fma_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x44]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x84]
+
+v_fma_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_fma_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x01,0x4c,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// GFX10: encoding: [0x05,0x02,0x4c,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// GFX10: encoding: [0x05,0x04,0x4c,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// GFX10: encoding: [0x05,0x07,0x4c,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// GFX10: encoding: [0x05,0x80,0x4c,0xd5,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x14]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// GFX10: encoding: [0x05,0x00,0x4c,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_lerp_u8 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x0e,0x04]
+
+v_lerp_u8 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x4d,0xd5,0x01,0x05,0x0e,0x04]
+
+v_lerp_u8 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0xff,0x05,0x0e,0x04]
+
+v_lerp_u8 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x67,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x77,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x80,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xff,0x0f,0x04]
+
+v_lerp_u8 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x0c,0x04]
+
+v_lerp_u8 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_lerp_u8 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_lerp_u8 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_lerp_u8 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xef,0x0c,0x04]
+
+v_lerp_u8 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_lerp_u8 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_lerp_u8 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xff,0x0c,0x04]
+
+v_lerp_u8 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x01,0x0d,0x04]
+
+v_lerp_u8 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x83,0x0d,0x04]
+
+v_lerp_u8 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_lerp_u8 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0xef,0x0d,0x04]
+
+v_lerp_u8 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xfe,0x07]
+
+v_lerp_u8 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x0e,0x00]
+
+v_lerp_u8 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x9e,0x01]
+
+v_lerp_u8 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xaa,0x01]
+
+v_lerp_u8 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xae,0x01]
+
+v_lerp_u8 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xde,0x01]
+
+v_lerp_u8 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xf2,0x01]
+
+v_lerp_u8 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xfa,0x01]
+
+v_lerp_u8 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xfe,0x01]
+
+v_lerp_u8 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x02,0x02]
+
+v_lerp_u8 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0x06,0x03]
+
+v_lerp_u8 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xc2,0x03]
+
+v_lerp_u8 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x4d,0xd5,0x01,0x05,0xde,0x03]
+
+v_alignbit_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0x0e,0x04]
+
+v_alignbit_b32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x4e,0xd5,0x01,0x05,0x0e,0x04]
+
+v_alignbit_b32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0xff,0x05,0x0e,0x04]
+
+v_alignbit_b32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x67,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x77,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xff,0x0f,0x04]
+
+v_alignbit_b32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xef,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0xff,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xfe,0x07]
+
+v_alignbit_b32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0x0e,0x00]
+
+v_alignbit_b32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0x9e,0x01]
+
+v_alignbit_b32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xaa,0x01]
+
+v_alignbit_b32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xae,0x01]
+
+v_alignbit_b32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xde,0x01]
+
+v_alignbit_b32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xf2,0x01]
+
+v_alignbit_b32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xfa,0x01]
+
+v_alignbit_b32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x4e,0xd5,0x01,0x05,0xfe,0x01]
+
+v_alignbyte_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0xff,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x67,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x77,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xff,0x0f,0x04]
+
+v_alignbyte_b32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xef,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0xff,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xfe,0x07]
+
+v_alignbyte_b32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x0e,0x00]
+
+v_alignbyte_b32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0x9e,0x01]
+
+v_alignbyte_b32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xaa,0x01]
+
+v_alignbyte_b32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xae,0x01]
+
+v_alignbyte_b32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xde,0x01]
+
+v_alignbyte_b32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xf2,0x01]
+
+v_alignbyte_b32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xfa,0x01]
+
+v_alignbyte_b32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x4f,0xd5,0x01,0x05,0xfe,0x01]
+
+v_mullit_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x50,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0xff,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x67,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x77,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x80,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xff,0x0f,0x04]
+
+v_mullit_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0c,0x04]
+
+v_mullit_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_mullit_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_mullit_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_mullit_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xef,0x0c,0x04]
+
+v_mullit_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_mullit_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_mullit_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xff,0x0c,0x04]
+
+v_mullit_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x01,0x0d,0x04]
+
+v_mullit_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x83,0x0d,0x04]
+
+v_mullit_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_mullit_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0xef,0x0d,0x04]
+
+v_mullit_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xfe,0x07]
+
+v_mullit_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x00]
+
+v_mullit_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x9e,0x01]
+
+v_mullit_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xaa,0x01]
+
+v_mullit_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xae,0x01]
+
+v_mullit_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xde,0x01]
+
+v_mullit_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xf2,0x01]
+
+v_mullit_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xfa,0x01]
+
+v_mullit_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xfe,0x01]
+
+v_mullit_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x02,0x02]
+
+v_mullit_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x06,0x03]
+
+v_mullit_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xc2,0x03]
+
+v_mullit_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0xde,0x03]
+
+v_mullit_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x24]
+
+v_mullit_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x44]
+
+v_mullit_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x84]
+
+v_mullit_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_mullit_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x50,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x50,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x50,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x50,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x50,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_mullit_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x14]
+
+v_mullit_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x50,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_min3_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x51,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0xff,0x05,0x0e,0x04]
+
+v_min3_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x04,0x0e,0x04]
+
+v_min3_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x67,0x04,0x0e,0x04]
+
+v_min3_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_min3_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_min3_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x77,0x04,0x0e,0x04]
+
+v_min3_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_min3_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_min3_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_min3_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x80,0x04,0x0e,0x04]
+
+v_min3_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_min3_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_min3_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_min3_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xff,0x0f,0x04]
+
+v_min3_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0c,0x04]
+
+v_min3_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_min3_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_min3_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_min3_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xef,0x0c,0x04]
+
+v_min3_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_min3_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_min3_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xff,0x0c,0x04]
+
+v_min3_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x01,0x0d,0x04]
+
+v_min3_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x83,0x0d,0x04]
+
+v_min3_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_min3_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0xef,0x0d,0x04]
+
+v_min3_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xfe,0x07]
+
+v_min3_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x00]
+
+v_min3_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x9e,0x01]
+
+v_min3_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xaa,0x01]
+
+v_min3_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xae,0x01]
+
+v_min3_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xde,0x01]
+
+v_min3_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xf2,0x01]
+
+v_min3_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xfa,0x01]
+
+v_min3_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xfe,0x01]
+
+v_min3_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x02,0x02]
+
+v_min3_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x06,0x03]
+
+v_min3_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xc2,0x03]
+
+v_min3_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0xde,0x03]
+
+v_min3_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x24]
+
+v_min3_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x44]
+
+v_min3_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x84]
+
+v_min3_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_min3_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x51,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x51,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x51,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x51,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x51,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_min3_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x14]
+
+v_min3_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x51,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_min3_i32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_i32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x52,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_i32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0xff,0x05,0x0e,0x04]
+
+v_min3_i32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x04,0x0e,0x04]
+
+v_min3_i32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x67,0x04,0x0e,0x04]
+
+v_min3_i32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_min3_i32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_min3_i32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x77,0x04,0x0e,0x04]
+
+v_min3_i32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_min3_i32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_min3_i32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_min3_i32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x80,0x04,0x0e,0x04]
+
+v_min3_i32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_min3_i32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_min3_i32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_min3_i32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xff,0x0f,0x04]
+
+v_min3_i32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x0c,0x04]
+
+v_min3_i32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_min3_i32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_min3_i32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_min3_i32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xef,0x0c,0x04]
+
+v_min3_i32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_min3_i32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_min3_i32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xff,0x0c,0x04]
+
+v_min3_i32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x01,0x0d,0x04]
+
+v_min3_i32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x83,0x0d,0x04]
+
+v_min3_i32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_min3_i32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0xef,0x0d,0x04]
+
+v_min3_i32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xfe,0x07]
+
+v_min3_i32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x0e,0x00]
+
+v_min3_i32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x9e,0x01]
+
+v_min3_i32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xaa,0x01]
+
+v_min3_i32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xae,0x01]
+
+v_min3_i32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xde,0x01]
+
+v_min3_i32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xf2,0x01]
+
+v_min3_i32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xfa,0x01]
+
+v_min3_i32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xfe,0x01]
+
+v_min3_i32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x02,0x02]
+
+v_min3_i32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0x06,0x03]
+
+v_min3_i32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xc2,0x03]
+
+v_min3_i32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x52,0xd5,0x01,0x05,0xde,0x03]
+
+v_min3_u32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_u32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x53,0xd5,0x01,0x05,0x0e,0x04]
+
+v_min3_u32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0xff,0x05,0x0e,0x04]
+
+v_min3_u32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x04,0x0e,0x04]
+
+v_min3_u32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x67,0x04,0x0e,0x04]
+
+v_min3_u32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_min3_u32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_min3_u32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x77,0x04,0x0e,0x04]
+
+v_min3_u32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_min3_u32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_min3_u32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_min3_u32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x80,0x04,0x0e,0x04]
+
+v_min3_u32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_min3_u32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_min3_u32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_min3_u32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xff,0x0f,0x04]
+
+v_min3_u32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x0c,0x04]
+
+v_min3_u32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_min3_u32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_min3_u32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_min3_u32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xef,0x0c,0x04]
+
+v_min3_u32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_min3_u32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_min3_u32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xff,0x0c,0x04]
+
+v_min3_u32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x01,0x0d,0x04]
+
+v_min3_u32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x83,0x0d,0x04]
+
+v_min3_u32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_min3_u32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0xef,0x0d,0x04]
+
+v_min3_u32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xfe,0x07]
+
+v_min3_u32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x0e,0x00]
+
+v_min3_u32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x9e,0x01]
+
+v_min3_u32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xaa,0x01]
+
+v_min3_u32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xae,0x01]
+
+v_min3_u32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xde,0x01]
+
+v_min3_u32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xf2,0x01]
+
+v_min3_u32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xfa,0x01]
+
+v_min3_u32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xfe,0x01]
+
+v_min3_u32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x02,0x02]
+
+v_min3_u32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0x06,0x03]
+
+v_min3_u32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xc2,0x03]
+
+v_min3_u32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x53,0xd5,0x01,0x05,0xde,0x03]
+
+v_max3_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x54,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0xff,0x05,0x0e,0x04]
+
+v_max3_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x04,0x0e,0x04]
+
+v_max3_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x67,0x04,0x0e,0x04]
+
+v_max3_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_max3_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_max3_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x77,0x04,0x0e,0x04]
+
+v_max3_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_max3_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_max3_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_max3_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x80,0x04,0x0e,0x04]
+
+v_max3_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_max3_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_max3_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_max3_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xff,0x0f,0x04]
+
+v_max3_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0c,0x04]
+
+v_max3_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_max3_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_max3_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_max3_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xef,0x0c,0x04]
+
+v_max3_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_max3_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_max3_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xff,0x0c,0x04]
+
+v_max3_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x01,0x0d,0x04]
+
+v_max3_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x83,0x0d,0x04]
+
+v_max3_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_max3_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0xef,0x0d,0x04]
+
+v_max3_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xfe,0x07]
+
+v_max3_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x00]
+
+v_max3_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x9e,0x01]
+
+v_max3_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xaa,0x01]
+
+v_max3_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xae,0x01]
+
+v_max3_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xde,0x01]
+
+v_max3_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xf2,0x01]
+
+v_max3_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xfa,0x01]
+
+v_max3_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xfe,0x01]
+
+v_max3_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x02,0x02]
+
+v_max3_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x06,0x03]
+
+v_max3_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xc2,0x03]
+
+v_max3_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0xde,0x03]
+
+v_max3_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x24]
+
+v_max3_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x44]
+
+v_max3_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x84]
+
+v_max3_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_max3_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x54,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x54,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x54,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x54,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x54,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_max3_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x14]
+
+v_max3_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x54,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_max3_i32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_i32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x55,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_i32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0xff,0x05,0x0e,0x04]
+
+v_max3_i32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x04,0x0e,0x04]
+
+v_max3_i32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x67,0x04,0x0e,0x04]
+
+v_max3_i32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_max3_i32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_max3_i32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x77,0x04,0x0e,0x04]
+
+v_max3_i32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_max3_i32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_max3_i32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_max3_i32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x80,0x04,0x0e,0x04]
+
+v_max3_i32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_max3_i32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_max3_i32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_max3_i32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xff,0x0f,0x04]
+
+v_max3_i32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x0c,0x04]
+
+v_max3_i32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_max3_i32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_max3_i32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_max3_i32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xef,0x0c,0x04]
+
+v_max3_i32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_max3_i32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_max3_i32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xff,0x0c,0x04]
+
+v_max3_i32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x01,0x0d,0x04]
+
+v_max3_i32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x83,0x0d,0x04]
+
+v_max3_i32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_max3_i32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0xef,0x0d,0x04]
+
+v_max3_i32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xfe,0x07]
+
+v_max3_i32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x0e,0x00]
+
+v_max3_i32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x9e,0x01]
+
+v_max3_i32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xaa,0x01]
+
+v_max3_i32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xae,0x01]
+
+v_max3_i32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xde,0x01]
+
+v_max3_i32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xf2,0x01]
+
+v_max3_i32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xfa,0x01]
+
+v_max3_i32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xfe,0x01]
+
+v_max3_i32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x02,0x02]
+
+v_max3_i32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0x06,0x03]
+
+v_max3_i32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xc2,0x03]
+
+v_max3_i32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x55,0xd5,0x01,0x05,0xde,0x03]
+
+v_max3_u32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_u32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x56,0xd5,0x01,0x05,0x0e,0x04]
+
+v_max3_u32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0xff,0x05,0x0e,0x04]
+
+v_max3_u32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x04,0x0e,0x04]
+
+v_max3_u32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x67,0x04,0x0e,0x04]
+
+v_max3_u32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_max3_u32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_max3_u32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x77,0x04,0x0e,0x04]
+
+v_max3_u32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_max3_u32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_max3_u32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_max3_u32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x80,0x04,0x0e,0x04]
+
+v_max3_u32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_max3_u32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_max3_u32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_max3_u32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xff,0x0f,0x04]
+
+v_max3_u32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x0c,0x04]
+
+v_max3_u32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_max3_u32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_max3_u32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_max3_u32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xef,0x0c,0x04]
+
+v_max3_u32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_max3_u32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_max3_u32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xff,0x0c,0x04]
+
+v_max3_u32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x01,0x0d,0x04]
+
+v_max3_u32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x83,0x0d,0x04]
+
+v_max3_u32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_max3_u32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0xef,0x0d,0x04]
+
+v_max3_u32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xfe,0x07]
+
+v_max3_u32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x0e,0x00]
+
+v_max3_u32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x9e,0x01]
+
+v_max3_u32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xaa,0x01]
+
+v_max3_u32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xae,0x01]
+
+v_max3_u32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xde,0x01]
+
+v_max3_u32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xf2,0x01]
+
+v_max3_u32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xfa,0x01]
+
+v_max3_u32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xfe,0x01]
+
+v_max3_u32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x02,0x02]
+
+v_max3_u32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0x06,0x03]
+
+v_max3_u32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xc2,0x03]
+
+v_max3_u32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x56,0xd5,0x01,0x05,0xde,0x03]
+
+v_med3_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x57,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0xff,0x05,0x0e,0x04]
+
+v_med3_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x04,0x0e,0x04]
+
+v_med3_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x67,0x04,0x0e,0x04]
+
+v_med3_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_med3_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_med3_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x77,0x04,0x0e,0x04]
+
+v_med3_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_med3_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_med3_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_med3_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x80,0x04,0x0e,0x04]
+
+v_med3_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_med3_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_med3_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_med3_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xff,0x0f,0x04]
+
+v_med3_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0c,0x04]
+
+v_med3_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_med3_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_med3_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_med3_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xef,0x0c,0x04]
+
+v_med3_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_med3_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_med3_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xff,0x0c,0x04]
+
+v_med3_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x01,0x0d,0x04]
+
+v_med3_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x83,0x0d,0x04]
+
+v_med3_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_med3_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0xef,0x0d,0x04]
+
+v_med3_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xfe,0x07]
+
+v_med3_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x00]
+
+v_med3_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x9e,0x01]
+
+v_med3_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xaa,0x01]
+
+v_med3_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xae,0x01]
+
+v_med3_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xde,0x01]
+
+v_med3_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xf2,0x01]
+
+v_med3_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xfa,0x01]
+
+v_med3_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xfe,0x01]
+
+v_med3_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x02,0x02]
+
+v_med3_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x06,0x03]
+
+v_med3_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xc2,0x03]
+
+v_med3_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0xde,0x03]
+
+v_med3_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x24]
+
+v_med3_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x44]
+
+v_med3_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x84]
+
+v_med3_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_med3_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x57,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x57,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x57,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x57,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x57,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_med3_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x14]
+
+v_med3_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x57,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_med3_i32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_i32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x58,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_i32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0xff,0x05,0x0e,0x04]
+
+v_med3_i32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x04,0x0e,0x04]
+
+v_med3_i32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x67,0x04,0x0e,0x04]
+
+v_med3_i32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_med3_i32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_med3_i32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x77,0x04,0x0e,0x04]
+
+v_med3_i32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_med3_i32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_med3_i32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_med3_i32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x80,0x04,0x0e,0x04]
+
+v_med3_i32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_med3_i32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_med3_i32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_med3_i32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xff,0x0f,0x04]
+
+v_med3_i32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x0c,0x04]
+
+v_med3_i32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_med3_i32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_med3_i32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_med3_i32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xef,0x0c,0x04]
+
+v_med3_i32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_med3_i32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_med3_i32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xff,0x0c,0x04]
+
+v_med3_i32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x01,0x0d,0x04]
+
+v_med3_i32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x83,0x0d,0x04]
+
+v_med3_i32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_med3_i32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0xef,0x0d,0x04]
+
+v_med3_i32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xfe,0x07]
+
+v_med3_i32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x0e,0x00]
+
+v_med3_i32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x9e,0x01]
+
+v_med3_i32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xaa,0x01]
+
+v_med3_i32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xae,0x01]
+
+v_med3_i32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xde,0x01]
+
+v_med3_i32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xf2,0x01]
+
+v_med3_i32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xfa,0x01]
+
+v_med3_i32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xfe,0x01]
+
+v_med3_i32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x02,0x02]
+
+v_med3_i32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0x06,0x03]
+
+v_med3_i32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xc2,0x03]
+
+v_med3_i32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x58,0xd5,0x01,0x05,0xde,0x03]
+
+v_med3_u32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_u32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x59,0xd5,0x01,0x05,0x0e,0x04]
+
+v_med3_u32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0xff,0x05,0x0e,0x04]
+
+v_med3_u32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x04,0x0e,0x04]
+
+v_med3_u32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x67,0x04,0x0e,0x04]
+
+v_med3_u32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_med3_u32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_med3_u32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x77,0x04,0x0e,0x04]
+
+v_med3_u32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_med3_u32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_med3_u32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_med3_u32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x80,0x04,0x0e,0x04]
+
+v_med3_u32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_med3_u32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_med3_u32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_med3_u32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xff,0x0f,0x04]
+
+v_med3_u32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x0c,0x04]
+
+v_med3_u32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_med3_u32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_med3_u32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_med3_u32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xef,0x0c,0x04]
+
+v_med3_u32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_med3_u32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_med3_u32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xff,0x0c,0x04]
+
+v_med3_u32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x01,0x0d,0x04]
+
+v_med3_u32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x83,0x0d,0x04]
+
+v_med3_u32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_med3_u32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0xef,0x0d,0x04]
+
+v_med3_u32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xfe,0x07]
+
+v_med3_u32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x0e,0x00]
+
+v_med3_u32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x9e,0x01]
+
+v_med3_u32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xaa,0x01]
+
+v_med3_u32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xae,0x01]
+
+v_med3_u32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xde,0x01]
+
+v_med3_u32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xf2,0x01]
+
+v_med3_u32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xfa,0x01]
+
+v_med3_u32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xfe,0x01]
+
+v_med3_u32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x02,0x02]
+
+v_med3_u32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0x06,0x03]
+
+v_med3_u32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xc2,0x03]
+
+v_med3_u32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x59,0xd5,0x01,0x05,0xde,0x03]
+
+v_sad_u8 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x0e,0x04]
+
+v_sad_u8 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x5a,0xd5,0x01,0x05,0x0e,0x04]
+
+v_sad_u8 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0xff,0x05,0x0e,0x04]
+
+v_sad_u8 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x04,0x0e,0x04]
+
+v_sad_u8 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x67,0x04,0x0e,0x04]
+
+v_sad_u8 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_sad_u8 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_sad_u8 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x77,0x04,0x0e,0x04]
+
+v_sad_u8 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_sad_u8 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_sad_u8 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_sad_u8 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x80,0x04,0x0e,0x04]
+
+v_sad_u8 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_sad_u8 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_sad_u8 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_sad_u8 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xff,0x0f,0x04]
+
+v_sad_u8 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x0c,0x04]
+
+v_sad_u8 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_sad_u8 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_sad_u8 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_sad_u8 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xef,0x0c,0x04]
+
+v_sad_u8 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_sad_u8 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_sad_u8 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xff,0x0c,0x04]
+
+v_sad_u8 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x01,0x0d,0x04]
+
+v_sad_u8 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x83,0x0d,0x04]
+
+v_sad_u8 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_sad_u8 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0xef,0x0d,0x04]
+
+v_sad_u8 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xfe,0x07]
+
+v_sad_u8 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x0e,0x00]
+
+v_sad_u8 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x9e,0x01]
+
+v_sad_u8 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xaa,0x01]
+
+v_sad_u8 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xae,0x01]
+
+v_sad_u8 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xde,0x01]
+
+v_sad_u8 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xf2,0x01]
+
+v_sad_u8 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xfa,0x01]
+
+v_sad_u8 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xfe,0x01]
+
+v_sad_u8 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x02,0x02]
+
+v_sad_u8 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0x06,0x03]
+
+v_sad_u8 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xc2,0x03]
+
+v_sad_u8 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x5a,0xd5,0x01,0x05,0xde,0x03]
+
+v_sad_hi_u8 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x5b,0xd5,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0xff,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x67,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x77,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x80,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xff,0x0f,0x04]
+
+v_sad_hi_u8 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xef,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xff,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x01,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x83,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0xef,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xfe,0x07]
+
+v_sad_hi_u8 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x0e,0x00]
+
+v_sad_hi_u8 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x9e,0x01]
+
+v_sad_hi_u8 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xaa,0x01]
+
+v_sad_hi_u8 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xae,0x01]
+
+v_sad_hi_u8 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xde,0x01]
+
+v_sad_hi_u8 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xf2,0x01]
+
+v_sad_hi_u8 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xfa,0x01]
+
+v_sad_hi_u8 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xfe,0x01]
+
+v_sad_hi_u8 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x02,0x02]
+
+v_sad_hi_u8 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0x06,0x03]
+
+v_sad_hi_u8 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xc2,0x03]
+
+v_sad_hi_u8 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x5b,0xd5,0x01,0x05,0xde,0x03]
+
+v_sad_u16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x5c,0xd5,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0xff,0x05,0x0e,0x04]
+
+v_sad_u16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x04,0x0e,0x04]
+
+v_sad_u16 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x67,0x04,0x0e,0x04]
+
+v_sad_u16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_sad_u16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_sad_u16 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x77,0x04,0x0e,0x04]
+
+v_sad_u16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_sad_u16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_sad_u16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_sad_u16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x80,0x04,0x0e,0x04]
+
+v_sad_u16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_sad_u16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_sad_u16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_sad_u16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xff,0x0f,0x04]
+
+v_sad_u16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x0c,0x04]
+
+v_sad_u16 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_sad_u16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_sad_u16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_sad_u16 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xef,0x0c,0x04]
+
+v_sad_u16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_sad_u16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_sad_u16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xff,0x0c,0x04]
+
+v_sad_u16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x01,0x0d,0x04]
+
+v_sad_u16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x83,0x0d,0x04]
+
+v_sad_u16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_sad_u16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0xef,0x0d,0x04]
+
+v_sad_u16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xfe,0x07]
+
+v_sad_u16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x0e,0x00]
+
+v_sad_u16 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x9e,0x01]
+
+v_sad_u16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xaa,0x01]
+
+v_sad_u16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xae,0x01]
+
+v_sad_u16 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xde,0x01]
+
+v_sad_u16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xf2,0x01]
+
+v_sad_u16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xfa,0x01]
+
+v_sad_u16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xfe,0x01]
+
+v_sad_u16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x02,0x02]
+
+v_sad_u16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0x06,0x03]
+
+v_sad_u16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xc2,0x03]
+
+v_sad_u16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x5c,0xd5,0x01,0x05,0xde,0x03]
+
+v_sad_u32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x5d,0xd5,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0xff,0x05,0x0e,0x04]
+
+v_sad_u32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x04,0x0e,0x04]
+
+v_sad_u32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x67,0x04,0x0e,0x04]
+
+v_sad_u32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_sad_u32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_sad_u32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x77,0x04,0x0e,0x04]
+
+v_sad_u32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_sad_u32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_sad_u32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_sad_u32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x80,0x04,0x0e,0x04]
+
+v_sad_u32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_sad_u32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_sad_u32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_sad_u32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xff,0x0f,0x04]
+
+v_sad_u32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x0c,0x04]
+
+v_sad_u32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_sad_u32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_sad_u32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_sad_u32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xef,0x0c,0x04]
+
+v_sad_u32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_sad_u32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_sad_u32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xff,0x0c,0x04]
+
+v_sad_u32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x01,0x0d,0x04]
+
+v_sad_u32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x83,0x0d,0x04]
+
+v_sad_u32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_sad_u32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0xef,0x0d,0x04]
+
+v_sad_u32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xfe,0x07]
+
+v_sad_u32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x0e,0x00]
+
+v_sad_u32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x9e,0x01]
+
+v_sad_u32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xaa,0x01]
+
+v_sad_u32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xae,0x01]
+
+v_sad_u32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xde,0x01]
+
+v_sad_u32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xf2,0x01]
+
+v_sad_u32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xfa,0x01]
+
+v_sad_u32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xfe,0x01]
+
+v_sad_u32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x02,0x02]
+
+v_sad_u32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0x06,0x03]
+
+v_sad_u32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xc2,0x03]
+
+v_sad_u32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x5d,0xd5,0x01,0x05,0xde,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0xff,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x67,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x77,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x80,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xff,0x0f,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xef,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xff,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x01,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x83,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0xef,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xfe,0x07]
+
+v_cvt_pk_u8_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x00]
+
+v_cvt_pk_u8_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x9e,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xaa,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xae,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xde,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xf2,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xfa,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xfe,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x02,0x02]
+
+v_cvt_pk_u8_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x06,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xc2,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0xde,0x03]
+
+v_cvt_pk_u8_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x24]
+
+v_cvt_pk_u8_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x5e,0xd5,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x5e,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0xff,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x67,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x77,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xff,0x0f,0x04]
+
+v_div_fixup_f32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xef,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xff,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xfe,0x07]
+
+v_div_fixup_f32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x00]
+
+v_div_fixup_f32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x9e,0x01]
+
+v_div_fixup_f32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xae,0x01]
+
+v_div_fixup_f32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xde,0x01]
+
+v_div_fixup_f32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xf2,0x01]
+
+v_div_fixup_f32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xfe,0x01]
+
+v_div_fixup_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x5f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x5f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x5f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x5f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x5f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_div_fixup_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x14]
+
+v_div_fixup_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x5f,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// GFX10: encoding: [0xfe,0x00,0x60,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0xfe,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[2:3], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x02,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[4:5], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x04,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[102:103], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x66,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], vcc, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x76,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], exec, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], 0, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], -1, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xfd,0x0f,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[4:5], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x09,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[6:7], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x0d,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[102:103], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xcd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], vcc, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xed,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], exec, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], 0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], -1, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xfa,0x07]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[6:7]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x1a,0x00]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[8:9]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x22,0x00]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[102:103]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x9a,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], vcc
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xda,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], exec
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -1
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0.5
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -4.0
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x01,0x60,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// GFX10: encoding: [0x05,0x02,0x60,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// GFX10: encoding: [0x05,0x04,0x60,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// GFX10: encoding: [0x05,0x07,0x60,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// GFX10: encoding: [0x05,0x80,0x60,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x14]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// GFX10: encoding: [0x05,0x00,0x60,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_add_f64 v[5:6], v[1:2], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[254:255], v[1:2], v[2:3]
+// GFX10: encoding: [0xfe,0x00,0x64,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[254:255], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0xfe,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], s[2:3], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x02,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], s[4:5], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x04,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], s[102:103], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x66,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], vcc, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x6a,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], ttmp[10:11], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x76,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], exec, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x7e,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], 0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x80,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], -1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0xc1,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], 0.5, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0xf0,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], -4.0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0xf7,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xfd,0x03,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[4:5]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x09,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[6:7]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x0d,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[102:103]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xcd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], vcc
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xd5,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], ttmp[10:11]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xed,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], exec
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xfd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], 0
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x01,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], -1
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x83,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], 0.5
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xe1,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], -4.0
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0xef,0x01,0x00]
+
+v_add_f64 v[5:6], -v[1:2], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x20]
+
+v_add_f64 v[5:6], v[1:2], -v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x40]
+
+v_add_f64 v[5:6], -v[1:2], -v[2:3]
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x60]
+
+v_add_f64 v[5:6], |v[1:2]|, v[2:3]
+// GFX10: encoding: [0x05,0x01,0x64,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], |v[2:3]|
+// GFX10: encoding: [0x05,0x02,0x64,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// GFX10: encoding: [0x05,0x03,0x64,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] clamp
+// GFX10: encoding: [0x05,0x80,0x64,0xd5,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] mul:2
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x08]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] mul:4
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x10]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] div:2
+// GFX10: encoding: [0x05,0x00,0x64,0xd5,0x01,0x05,0x02,0x18]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[254:255], v[1:2], v[2:3]
+// GFX10: encoding: [0xfe,0x00,0x65,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[254:255], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0xfe,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], s[2:3], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x02,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], s[4:5], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x04,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], s[102:103], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x66,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], vcc, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], ttmp[10:11], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x76,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], exec, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], 0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], -1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], 0.5, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], -4.0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xfd,0x03,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[4:5]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x09,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[6:7]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x0d,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[102:103]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xcd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], vcc
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], ttmp[10:11]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xed,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], exec
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], 0
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], -1
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], 0.5
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], -4.0
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_f64 v[5:6], -v[1:2], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x20]
+
+v_mul_f64 v[5:6], v[1:2], -v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x40]
+
+v_mul_f64 v[5:6], -v[1:2], -v[2:3]
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x60]
+
+v_mul_f64 v[5:6], |v[1:2]|, v[2:3]
+// GFX10: encoding: [0x05,0x01,0x65,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], |v[2:3]|
+// GFX10: encoding: [0x05,0x02,0x65,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// GFX10: encoding: [0x05,0x03,0x65,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] clamp
+// GFX10: encoding: [0x05,0x80,0x65,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] mul:2
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x08]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] mul:4
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x10]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] div:2
+// GFX10: encoding: [0x05,0x00,0x65,0xd5,0x01,0x05,0x02,0x18]
+
+v_min_f64 v[5:6], v[1:2], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[254:255], v[1:2], v[2:3]
+// GFX10: encoding: [0xfe,0x00,0x66,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[254:255], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0xfe,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], s[2:3], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x02,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], s[4:5], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x04,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], s[102:103], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x66,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], vcc, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x6a,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], ttmp[10:11], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x76,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], exec, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x7e,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], 0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x80,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], -1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0xc1,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], 0.5, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0xf0,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], -4.0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0xf7,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xfd,0x03,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[4:5]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x09,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[6:7]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x0d,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[102:103]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xcd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], vcc
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xd5,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], ttmp[10:11]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xed,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], exec
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xfd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], 0
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x01,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], -1
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x83,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], 0.5
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xe1,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], -4.0
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0xef,0x01,0x00]
+
+v_min_f64 v[5:6], -v[1:2], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x20]
+
+v_min_f64 v[5:6], v[1:2], -v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x40]
+
+v_min_f64 v[5:6], -v[1:2], -v[2:3]
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x60]
+
+v_min_f64 v[5:6], |v[1:2]|, v[2:3]
+// GFX10: encoding: [0x05,0x01,0x66,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], |v[2:3]|
+// GFX10: encoding: [0x05,0x02,0x66,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// GFX10: encoding: [0x05,0x03,0x66,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] clamp
+// GFX10: encoding: [0x05,0x80,0x66,0xd5,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] mul:2
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x08]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] mul:4
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x10]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] div:2
+// GFX10: encoding: [0x05,0x00,0x66,0xd5,0x01,0x05,0x02,0x18]
+
+v_max_f64 v[5:6], v[1:2], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[254:255], v[1:2], v[2:3]
+// GFX10: encoding: [0xfe,0x00,0x67,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[254:255], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0xfe,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], s[2:3], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x02,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], s[4:5], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x04,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], s[102:103], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x66,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], vcc, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x6a,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], ttmp[10:11], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x76,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], exec, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x7e,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], 0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x80,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], -1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0xc1,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], 0.5, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0xf0,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], -4.0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0xf7,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xfd,0x03,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[4:5]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x09,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[6:7]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x0d,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[102:103]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xcd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], vcc
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xd5,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], ttmp[10:11]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xed,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], exec
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xfd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], 0
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x01,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], -1
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x83,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], 0.5
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xe1,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], -4.0
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0xef,0x01,0x00]
+
+v_max_f64 v[5:6], -v[1:2], v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x20]
+
+v_max_f64 v[5:6], v[1:2], -v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x40]
+
+v_max_f64 v[5:6], -v[1:2], -v[2:3]
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x60]
+
+v_max_f64 v[5:6], |v[1:2]|, v[2:3]
+// GFX10: encoding: [0x05,0x01,0x67,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], |v[2:3]|
+// GFX10: encoding: [0x05,0x02,0x67,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// GFX10: encoding: [0x05,0x03,0x67,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] clamp
+// GFX10: encoding: [0x05,0x80,0x67,0xd5,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] mul:2
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x08]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] mul:4
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x10]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] div:2
+// GFX10: encoding: [0x05,0x00,0x67,0xd5,0x01,0x05,0x02,0x18]
+
+v_ldexp_f64 v[5:6], v[1:2], v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[254:255], v[1:2], v2
+// GFX10: encoding: [0xfe,0x00,0x68,0xd5,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[254:255], v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0xfe,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[2:3], v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x02,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[4:5], v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x04,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[102:103], v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x66,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], vcc, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], ttmp[10:11], v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x76,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], exec, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], 0, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x80,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], -1, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v255
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xff,0x03,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s103
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], vcc_lo
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], vcc_hi
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], ttmp11
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xef,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], m0
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], exec_lo
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], exec_hi
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xff,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], 0
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x01,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], -1
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x83,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], 0.5
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], -4.0
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0xef,0x01,0x00]
+
+v_ldexp_f64 v[5:6], -v[1:2], v2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x20]
+
+v_ldexp_f64 v[5:6], |v[1:2]|, v2
+// GFX10: encoding: [0x05,0x01,0x68,0xd5,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 clamp
+// GFX10: encoding: [0x05,0x80,0x68,0xd5,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x08]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x10]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 div:2
+// GFX10: encoding: [0x05,0x00,0x68,0xd5,0x01,0x05,0x02,0x18]
+
+v_mul_lo_u32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x69,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_lo_u32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x67,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x77,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_lo_u32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xcf,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xef,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x69,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x6a,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_hi_u32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x67,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x77,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_hi_u32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xef,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x6a,0xd5,0x01,0xef,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x6c,0xd5,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0xff,0x05,0x02,0x00]
+
+v_mul_hi_i32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x67,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x77,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x80,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xff,0x03,0x00]
+
+v_mul_hi_i32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x05,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xef,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xff,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0x83,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x6c,0xd5,0x01,0xef,0x01,0x00]
+
+v_div_scale_f32 v5, s0, v1, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v255, s0, v1, v2, v3
+// W32: encoding: [0xff,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v255, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0xff,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, s1, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, s103, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x67,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, vcc_lo, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x6a,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, vcc_hi, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x6b,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, ttmp11, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x77,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, m0, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x7c,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, exec_lo, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x7e,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, exec_hi, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x7f,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, 0, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x80,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, -1, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0xc1,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, 0.5, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0xf0,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, -4.0, v2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0xf7,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v255, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xff,0x0f,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, s2, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, s103, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xcf,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, vcc_lo, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xd5,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, vcc_hi, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xd7,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, ttmp11, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xef,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, m0, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xf9,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, exec_lo, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xfd,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, exec_hi, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xff,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, 0, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x01,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, -1, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x83,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, 0.5, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xe1,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, -4.0, v3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xef,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, v255
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfe,0x07]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, s3
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, s103
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x9e,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, vcc_lo
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xaa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, vcc_hi
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xae,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, ttmp11
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xde,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, m0
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xf2,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, exec_lo
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, exec_hi
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfe,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, 0
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x02,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, -1
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, 0.5
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xc2,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s0, v1, v2, -4.0
+// W32: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xde,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v255, s[0:1], v1, v2, v3
+// W64: encoding: [0xff,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v255, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0xff,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], s1, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], s103, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x67,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], vcc_lo, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x6a,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], vcc_hi, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x6b,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], ttmp11, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x77,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], m0, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x7c,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], exec_lo, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x7e,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], exec_hi, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x7f,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], 0, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x80,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], -1, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0xc1,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], 0.5, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0xf0,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], -4.0, v2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0xf7,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v255, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xff,0x0f,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, s2, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, s103, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xcf,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, vcc_lo, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xd5,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, vcc_hi, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xd7,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, ttmp11, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xef,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, m0, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xf9,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, exec_lo, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xfd,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, exec_hi, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xff,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, 0, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x01,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, -1, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x83,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, 0.5, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xe1,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, -4.0, v3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0xef,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, v255
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfe,0x07]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, s3
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x0e,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, s103
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x9e,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, vcc_lo
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xaa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, vcc_hi
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xae,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, ttmp11
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xde,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, m0
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xf2,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, exec_lo
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, exec_hi
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xfe,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, 0
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x02,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, -1
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, 0.5
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xc2,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_scale_f32 v5, s[0:1], v1, v2, -4.0
+// W64: encoding: [0x05,0x00,0x6d,0xd5,0x01,0x05,0xde,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_div_fmas_f32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0xff,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x80,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0xff,0x0f,0x04]
+
+v_div_fmas_f32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x01,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x83,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0xef,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0xfe,0x07]
+
+v_div_fmas_f32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x02,0x02]
+
+v_div_fmas_f32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x06,0x03]
+
+v_div_fmas_f32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0xc2,0x03]
+
+v_div_fmas_f32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0xde,0x03]
+
+v_div_fmas_f32 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x24]
+
+v_div_fmas_f32 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x44]
+
+v_div_fmas_f32 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x84]
+
+v_div_fmas_f32 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_div_fmas_f32 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x6f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x6f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x6f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x6f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x6f,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_div_fmas_f32 v5, v1, v2, v3 mul:4
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x14]
+
+v_div_fmas_f32 v5, v1, v2, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x6f,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// GFX10: encoding: [0xfe,0x00,0x70,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0xfe,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], 0, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x80,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], -1, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0xfd,0x0f,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], 0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x01,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], -1, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x83,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0xef,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0xfa,0x07]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x02,0x02]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -1
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x06,0x03]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0.5
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0xc2,0x03]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -4.0
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0xde,0x03]
+
+v_div_fmas_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x24]
+
+v_div_fmas_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x44]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x84]
+
+v_div_fmas_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0xe4]
+
+v_div_fmas_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// GFX10: encoding: [0x05,0x01,0x70,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// GFX10: encoding: [0x05,0x02,0x70,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// GFX10: encoding: [0x05,0x04,0x70,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// GFX10: encoding: [0x05,0x07,0x70,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// GFX10: encoding: [0x05,0x80,0x70,0xd5,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x0c]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x14]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// GFX10: encoding: [0x05,0x00,0x70,0xd5,0x01,0x05,0x0e,0x1c]
+
+v_msad_u8 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x0e,0x04]
+
+v_msad_u8 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x71,0xd5,0x01,0x05,0x0e,0x04]
+
+v_msad_u8 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0xff,0x05,0x0e,0x04]
+
+v_msad_u8 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x04,0x0e,0x04]
+
+v_msad_u8 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x67,0x04,0x0e,0x04]
+
+v_msad_u8 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_msad_u8 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_msad_u8 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x77,0x04,0x0e,0x04]
+
+v_msad_u8 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_msad_u8 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_msad_u8 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_msad_u8 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x80,0x04,0x0e,0x04]
+
+v_msad_u8 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_msad_u8 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_msad_u8 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_msad_u8 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xff,0x0f,0x04]
+
+v_msad_u8 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x0c,0x04]
+
+v_msad_u8 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_msad_u8 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_msad_u8 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_msad_u8 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xef,0x0c,0x04]
+
+v_msad_u8 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_msad_u8 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_msad_u8 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xff,0x0c,0x04]
+
+v_msad_u8 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x01,0x0d,0x04]
+
+v_msad_u8 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x83,0x0d,0x04]
+
+v_msad_u8 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_msad_u8 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0xef,0x0d,0x04]
+
+v_msad_u8 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xfe,0x07]
+
+v_msad_u8 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x0e,0x00]
+
+v_msad_u8 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x9e,0x01]
+
+v_msad_u8 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xaa,0x01]
+
+v_msad_u8 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xae,0x01]
+
+v_msad_u8 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xde,0x01]
+
+v_msad_u8 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xf2,0x01]
+
+v_msad_u8 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xfa,0x01]
+
+v_msad_u8 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xfe,0x01]
+
+v_msad_u8 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x02,0x02]
+
+v_msad_u8 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0x06,0x03]
+
+v_msad_u8 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xc2,0x03]
+
+v_msad_u8 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x71,0xd5,0x01,0x05,0xde,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
+// GFX10: encoding: [0xfe,0x00,0x72,0xd5,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0xfe,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x02,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x04,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[102:103], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x66,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x76,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x80,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xff,0x0f,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s103, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xef,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0xff,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x01,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x83,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0xfa,0x07]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x1a,0x00]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x22,0x00]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[102:103]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x9a,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0xaa,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0xda,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0xfa,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x02,0x02]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
+// GFX10: encoding: [0x05,0x00,0x72,0xd5,0x01,0x05,0x06,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
+// GFX10: encoding: [0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0xfe,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x02,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x04,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[102:103], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x66,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x76,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x80,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xff,0x0f,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s103, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xef,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0xff,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x01,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x83,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0xfa,0x07]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x1a,0x00]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x22,0x00]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[102:103]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x9a,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0xaa,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0xda,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0xfa,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x02,0x02]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
+// GFX10: encoding: [0x05,0x00,0x73,0xd5,0x01,0x05,0x06,0x03]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[254:255], v[1:2], v2
+// GFX10: encoding: [0xfe,0x00,0x74,0xd5,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[254:255], v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0xfe,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[2:3], v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x02,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[4:5], v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x04,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[102:103], v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x66,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], vcc, v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x6a,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], ttmp[10:11], v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x76,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], exec, v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x7e,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], 0, v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x80,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], -1, v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0xc1,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0xf0,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0xf7,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v255
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xff,0x03,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s103
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xcf,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], vcc_lo
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xd5,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], vcc_hi
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xd7,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], ttmp11
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xef,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], m0
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xf9,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], exec_lo
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xfd,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], exec_hi
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xff,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], 0
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x01,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], -1
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x83,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], 0.5
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xe1,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], -4.0
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0xef,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], -v[1:2], v2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x20]
+
+v_trig_preop_f64 v[5:6], |v[1:2]|, v2
+// GFX10: encoding: [0x05,0x01,0x74,0xd5,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 clamp
+// GFX10: encoding: [0x05,0x80,0x74,0xd5,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 mul:2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x08]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 mul:4
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x10]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 div:2
+// GFX10: encoding: [0x05,0x00,0x74,0xd5,0x01,0x05,0x02,0x18]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0x05,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[2:3], v2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x02,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[4:5], v2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x04,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[102:103], v2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x66,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], vcc, v2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], ttmp[10:11], v2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x76,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], exec, v2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], 0, v2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x80,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], -1, v2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], s2, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0x05,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], s103, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], vcc_lo, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], vcc_hi, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], ttmp11, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xef,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], m0, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], exec_lo, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], exec_hi, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0xff,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], 0, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0x01,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], -1, v[3:6]
+// GFX10: encoding: [0xfc,0x00,0x75,0xd5,0x01,0x83,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[254:255], s12, v1, v2, v[3:4]
+// W32: encoding: [0xfe,0x0c,0x76,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s14, v1, v2, v[3:4]
+// W32: encoding: [0x05,0x0e,0x76,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s100, v1, v2, v[3:4]
+// W32: encoding: [0x05,0x64,0x76,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v255, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0xff,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, s1, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, s101, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x65,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, vcc_lo, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x6a,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, vcc_hi, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x6b,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, m0, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x7c,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, exec_lo, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x7e,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, exec_hi, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x7f,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, 0, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x80,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, -1, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0xc1,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, 0.5, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0xf0,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, -4.0, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0xf7,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v255, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xff,0x0f,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, s2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, s101, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xcb,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, vcc_lo, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xd5,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, vcc_hi, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xd7,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, m0, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xf9,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, exec_lo, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xfd,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, exec_hi, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xff,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, 0, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x01,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, -1, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x83,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, 0.5, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xe1,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, -4.0, v[3:4]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xef,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, v[254:255]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xfa,0x07]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, s[6:7]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, s[8:9]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x22,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, s[100:101]
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x92,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, vcc
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xaa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, exec
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xfa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, 0
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x02,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, -1
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, 0.5
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xc2,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s12, v1, v2, -4.0
+// W32: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xde,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[254:255], s[12:13], v1, v2, v[3:4]
+// W64: encoding: [0xfe,0x0c,0x76,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[14:15], v1, v2, v[3:4]
+// W64: encoding: [0x05,0x0e,0x76,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[100:101], v1, v2, v[3:4]
+// W64: encoding: [0x05,0x64,0x76,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v255, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0xff,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], s1, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], s101, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x65,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x6a,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x6b,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], m0, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x7c,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x7e,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x7f,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], 0, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x80,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], -1, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0xc1,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], 0.5, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0xf0,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], -4.0, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0xf7,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v255, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xff,0x0f,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, s2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, s101, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xcb,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xd5,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xd7,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, m0, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xf9,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xfd,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xff,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, 0, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x01,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, -1, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x83,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, 0.5, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xe1,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, -4.0, v[3:4]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0xef,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[254:255]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xfa,0x07]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[8:9]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x22,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[100:101]
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x92,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, vcc
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xaa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, exec
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xfa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x02,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -1
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0.5
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xc2,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -4.0
+// W64: encoding: [0x05,0x0c,0x76,0xd5,0x01,0x05,0xde,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[254:255], s12, v1, v2, v[3:4]
+// W32: encoding: [0xfe,0x0c,0x77,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s14, v1, v2, v[3:4]
+// W32: encoding: [0x05,0x0e,0x77,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s100, v1, v2, v[3:4]
+// W32: encoding: [0x05,0x64,0x77,0xd5,0x01,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v255, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0xff,0x05,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, s1, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, s101, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x65,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, vcc_lo, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x6a,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, vcc_hi, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x6b,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, m0, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x7c,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, exec_lo, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x7e,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, exec_hi, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x7f,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, 0, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x80,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, -1, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0xc1,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, 0.5, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0xf0,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, -4.0, v2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0xf7,0x04,0x0e,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v255, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xff,0x0f,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, s2, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, s101, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xcb,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, vcc_lo, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xd5,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, vcc_hi, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xd7,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, m0, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xf9,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, exec_lo, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xfd,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, exec_hi, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xff,0x0c,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, 0, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x01,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, -1, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x83,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, 0.5, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xe1,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, -4.0, v[3:4]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xef,0x0d,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, v[254:255]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xfa,0x07]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, s[6:7]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x1a,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, s[8:9]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x22,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, s[100:101]
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x92,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, vcc
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xaa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, exec
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xfa,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, 0
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x02,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, -1
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, 0.5
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xc2,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s12, v1, v2, -4.0
+// W32: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xde,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[254:255], s[12:13], v1, v2, v[3:4]
+// W64: encoding: [0xfe,0x0c,0x77,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[14:15], v1, v2, v[3:4]
+// W64: encoding: [0x05,0x0e,0x77,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[100:101], v1, v2, v[3:4]
+// W64: encoding: [0x05,0x64,0x77,0xd5,0x01,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v255, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0xff,0x05,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], s1, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], s101, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x65,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x6a,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x6b,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], m0, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x7c,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x7e,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x7f,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], 0, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x80,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], -1, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0xc1,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], 0.5, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0xf0,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], -4.0, v2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0xf7,0x04,0x0e,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v255, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xff,0x0f,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, s2, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, s101, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xcb,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xd5,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xd7,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, m0, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xf9,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xfd,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xff,0x0c,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, 0, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x01,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, -1, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x83,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, 0.5, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xe1,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, -4.0, v[3:4]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0xef,0x0d,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[254:255]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xfa,0x07]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[6:7]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x1a,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[8:9]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x22,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[100:101]
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x92,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, vcc
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xaa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, exec
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xfa,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x02,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -1
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0.5
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xc2,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -4.0
+// W64: encoding: [0x05,0x0c,0x77,0xd5,0x01,0x05,0xde,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_xor3_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x0e,0x04]
+
+v_xor3_b32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x78,0xd5,0x01,0x05,0x0e,0x04]
+
+v_xor3_b32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0xff,0x05,0x0e,0x04]
+
+v_xor3_b32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, s103, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x67,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x6a,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x6b,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, ttmp11, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x77,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x7c,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x7e,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x7f,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x80,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0xc1,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0xf0,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0xf7,0x04,0x0e,0x04]
+
+v_xor3_b32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xff,0x0f,0x04]
+
+v_xor3_b32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x0c,0x04]
+
+v_xor3_b32 v5, v1, s103, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xcf,0x0c,0x04]
+
+v_xor3_b32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xd5,0x0c,0x04]
+
+v_xor3_b32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xd7,0x0c,0x04]
+
+v_xor3_b32 v5, v1, ttmp11, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xef,0x0c,0x04]
+
+v_xor3_b32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xf9,0x0c,0x04]
+
+v_xor3_b32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xfd,0x0c,0x04]
+
+v_xor3_b32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xff,0x0c,0x04]
+
+v_xor3_b32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x01,0x0d,0x04]
+
+v_xor3_b32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x83,0x0d,0x04]
+
+v_xor3_b32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xe1,0x0d,0x04]
+
+v_xor3_b32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0xef,0x0d,0x04]
+
+v_xor3_b32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xfe,0x07]
+
+v_xor3_b32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x0e,0x00]
+
+v_xor3_b32 v5, v1, v2, s103
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x9e,0x01]
+
+v_xor3_b32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xaa,0x01]
+
+v_xor3_b32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xae,0x01]
+
+v_xor3_b32 v5, v1, v2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xde,0x01]
+
+v_xor3_b32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xf2,0x01]
+
+v_xor3_b32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xfa,0x01]
+
+v_xor3_b32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xfe,0x01]
+
+v_xor3_b32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x02,0x02]
+
+v_xor3_b32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0x06,0x03]
+
+v_xor3_b32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xc2,0x03]
+
+v_xor3_b32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x78,0xd5,0x01,0x05,0xde,0x03]
+
+v_lshlrev_b64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b64 v[254:255], v1, v[2:3]
+// GFX10: encoding: [0xfe,0x00,0xff,0xd6,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], v255, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], s1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], s101, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x65,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], vcc_lo, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], vcc_hi, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], m0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], exec_lo, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], exec_hi, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], 0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], -1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], 0.5, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0xf0,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], -4.0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0xf7,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], v1, v[254:255]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xfd,0x03,0x00]
+
+v_lshlrev_b64 v[5:6], v1, s[4:5]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x09,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, s[6:7]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x0d,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, s[100:101]
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xc9,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, vcc
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, exec
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, 0
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, -1
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, 0.5
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xe1,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, -4.0
+// GFX10: encoding: [0x05,0x00,0xff,0xd6,0x01,0xef,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b64 v[254:255], v1, v[2:3]
+// GFX10: encoding: [0xfe,0x00,0x00,0xd7,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], v255, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], s1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], s101, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x65,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], vcc_lo, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], vcc_hi, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], m0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], exec_lo, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], exec_hi, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], 0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], -1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], 0.5, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0xf0,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], -4.0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0xf7,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], v1, v[254:255]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xfd,0x03,0x00]
+
+v_lshrrev_b64 v[5:6], v1, s[4:5]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x09,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, s[6:7]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x0d,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, s[100:101]
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xc9,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, vcc
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, exec
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, 0
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, -1
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xe1,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x00,0xd7,0x01,0xef,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i64 v[254:255], v1, v[2:3]
+// GFX10: encoding: [0xfe,0x00,0x01,0xd7,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], v255, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], s1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], s101, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x65,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], vcc_lo, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], vcc_hi, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], m0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], exec_lo, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], exec_hi, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], 0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], -1, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], 0.5, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0xf0,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], -4.0, v[2:3]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0xf7,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], v1, v[254:255]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xfd,0x03,0x00]
+
+v_ashrrev_i64 v[5:6], v1, s[4:5]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x09,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, s[6:7]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x0d,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, s[100:101]
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xc9,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, vcc
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, exec
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, 0
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, -1
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xe1,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x01,0xd7,0x01,0xef,0x01,0x00]
+
+v_add_nc_u16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_u16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_u16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0xff,0x05,0x02,0x00]
+
+v_add_nc_u16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x04,0x02,0x00]
+
+v_add_nc_u16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x65,0x04,0x02,0x00]
+
+v_add_nc_u16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00]
+
+v_add_nc_u16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00]
+
+v_add_nc_u16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x7c,0x04,0x02,0x00]
+
+v_add_nc_u16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x7e,0x04,0x02,0x00]
+
+v_add_nc_u16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x7f,0x04,0x02,0x00]
+
+v_add_nc_u16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x80,0x04,0x02,0x00]
+
+v_add_nc_u16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0xc1,0x04,0x02,0x00]
+
+v_add_nc_u16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_add_nc_u16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_add_nc_u16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x03,0x00]
+
+v_add_nc_u16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x00,0x00]
+
+v_add_nc_u16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xcb,0x00,0x00]
+
+v_add_nc_u16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xd5,0x00,0x00]
+
+v_add_nc_u16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xd7,0x00,0x00]
+
+v_add_nc_u16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xf9,0x00,0x00]
+
+v_add_nc_u16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xfd,0x00,0x00]
+
+v_add_nc_u16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x00,0x00]
+
+v_add_nc_u16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x01,0x01,0x00]
+
+v_add_nc_u16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0x83,0x01,0x00]
+
+v_add_nc_u16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_add_nc_u16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_add_nc_u16 v5, v1, -4.0 clamp
+// GFX10: encoding: [0x05,0x80,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_u16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00]
+
+v_sub_nc_u16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x04,0x02,0x00]
+
+v_sub_nc_u16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x65,0x04,0x02,0x00]
+
+v_sub_nc_u16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00]
+
+v_sub_nc_u16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00]
+
+v_sub_nc_u16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x7c,0x04,0x02,0x00]
+
+v_sub_nc_u16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x7e,0x04,0x02,0x00]
+
+v_sub_nc_u16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x7f,0x04,0x02,0x00]
+
+v_sub_nc_u16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x80,0x04,0x02,0x00]
+
+v_sub_nc_u16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0xc1,0x04,0x02,0x00]
+
+v_sub_nc_u16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_sub_nc_u16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x03,0x00]
+
+v_sub_nc_u16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xcb,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xd5,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xd7,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xf9,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xfd,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x01,0x01,0x00]
+
+v_sub_nc_u16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0x83,0x01,0x00]
+
+v_sub_nc_u16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_sub_nc_u16 v5, v1, -4.0 clamp
+// GFX10: encoding: [0x05,0x80,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0xff,0x05,0x02,0x00]
+
+v_mul_lo_u16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x04,0x02,0x00]
+
+v_mul_lo_u16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x65,0x04,0x02,0x00]
+
+v_mul_lo_u16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_u16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_u16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x7c,0x04,0x02,0x00]
+
+v_mul_lo_u16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x7e,0x04,0x02,0x00]
+
+v_mul_lo_u16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x7f,0x04,0x02,0x00]
+
+v_mul_lo_u16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x80,0x04,0x02,0x00]
+
+v_mul_lo_u16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0xc1,0x04,0x02,0x00]
+
+v_mul_lo_u16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_mul_lo_u16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x03,0x00]
+
+v_mul_lo_u16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xcb,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xd5,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xd7,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xf9,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xfd,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x01,0x01,0x00]
+
+v_mul_lo_u16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0x83,0x01,0x00]
+
+v_mul_lo_u16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x65,0x04,0x02,0x00]
+
+v_lshrrev_b16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_lshrrev_b16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x03,0x00]
+
+v_lshrrev_b16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xcb,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xd7,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xf9,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x08,0xd7,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x65,0x04,0x02,0x00]
+
+v_ashrrev_i16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_ashrrev_i16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x03,0x00]
+
+v_ashrrev_i16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x05,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xcb,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xd7,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xf9,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_max_u16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
+
+v_max_u16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
+
+v_max_u16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0xff,0x05,0x02,0x00]
+
+v_max_u16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x04,0x02,0x00]
+
+v_max_u16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x65,0x04,0x02,0x00]
+
+v_max_u16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x6a,0x04,0x02,0x00]
+
+v_max_u16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x6b,0x04,0x02,0x00]
+
+v_max_u16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x7c,0x04,0x02,0x00]
+
+v_max_u16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x7e,0x04,0x02,0x00]
+
+v_max_u16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x7f,0x04,0x02,0x00]
+
+v_max_u16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x80,0x04,0x02,0x00]
+
+v_max_u16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0xc1,0x04,0x02,0x00]
+
+v_max_u16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_max_u16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_max_u16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x03,0x00]
+
+v_max_u16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x00,0x00]
+
+v_max_u16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xcb,0x00,0x00]
+
+v_max_u16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xd5,0x00,0x00]
+
+v_max_u16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xd7,0x00,0x00]
+
+v_max_u16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xf9,0x00,0x00]
+
+v_max_u16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xfd,0x00,0x00]
+
+v_max_u16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x00,0x00]
+
+v_max_u16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x01,0x01,0x00]
+
+v_max_u16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0x83,0x01,0x00]
+
+v_max_u16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_max_u16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_max_i16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
+
+v_max_i16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
+
+v_max_i16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0xff,0x05,0x02,0x00]
+
+v_max_i16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x04,0x02,0x00]
+
+v_max_i16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x65,0x04,0x02,0x00]
+
+v_max_i16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x6a,0x04,0x02,0x00]
+
+v_max_i16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x6b,0x04,0x02,0x00]
+
+v_max_i16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x7c,0x04,0x02,0x00]
+
+v_max_i16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x7e,0x04,0x02,0x00]
+
+v_max_i16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x7f,0x04,0x02,0x00]
+
+v_max_i16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x80,0x04,0x02,0x00]
+
+v_max_i16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0xc1,0x04,0x02,0x00]
+
+v_max_i16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_max_i16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_max_i16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x03,0x00]
+
+v_max_i16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x00,0x00]
+
+v_max_i16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xcb,0x00,0x00]
+
+v_max_i16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xd5,0x00,0x00]
+
+v_max_i16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xd7,0x00,0x00]
+
+v_max_i16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xf9,0x00,0x00]
+
+v_max_i16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xfd,0x00,0x00]
+
+v_max_i16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x00,0x00]
+
+v_max_i16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x01,0x01,0x00]
+
+v_max_i16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0x83,0x01,0x00]
+
+v_max_i16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_max_i16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_min_u16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
+
+v_min_u16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
+
+v_min_u16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0xff,0x05,0x02,0x00]
+
+v_min_u16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x04,0x02,0x00]
+
+v_min_u16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x65,0x04,0x02,0x00]
+
+v_min_u16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x6a,0x04,0x02,0x00]
+
+v_min_u16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x6b,0x04,0x02,0x00]
+
+v_min_u16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x7c,0x04,0x02,0x00]
+
+v_min_u16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x7e,0x04,0x02,0x00]
+
+v_min_u16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x7f,0x04,0x02,0x00]
+
+v_min_u16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x80,0x04,0x02,0x00]
+
+v_min_u16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0xc1,0x04,0x02,0x00]
+
+v_min_u16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_min_u16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_min_u16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x03,0x00]
+
+v_min_u16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x00,0x00]
+
+v_min_u16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xcb,0x00,0x00]
+
+v_min_u16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xd5,0x00,0x00]
+
+v_min_u16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xd7,0x00,0x00]
+
+v_min_u16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xf9,0x00,0x00]
+
+v_min_u16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xfd,0x00,0x00]
+
+v_min_u16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x00,0x00]
+
+v_min_u16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x01,0x01,0x00]
+
+v_min_u16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0x83,0x01,0x00]
+
+v_min_u16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_min_u16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_min_i16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
+
+v_min_i16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
+
+v_min_i16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0xff,0x05,0x02,0x00]
+
+v_min_i16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x04,0x02,0x00]
+
+v_min_i16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x65,0x04,0x02,0x00]
+
+v_min_i16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x6a,0x04,0x02,0x00]
+
+v_min_i16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x6b,0x04,0x02,0x00]
+
+v_min_i16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x7c,0x04,0x02,0x00]
+
+v_min_i16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x7e,0x04,0x02,0x00]
+
+v_min_i16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x7f,0x04,0x02,0x00]
+
+v_min_i16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x80,0x04,0x02,0x00]
+
+v_min_i16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0xc1,0x04,0x02,0x00]
+
+v_min_i16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_min_i16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_min_i16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x03,0x00]
+
+v_min_i16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x00,0x00]
+
+v_min_i16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xcb,0x00,0x00]
+
+v_min_i16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xd5,0x00,0x00]
+
+v_min_i16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xd7,0x00,0x00]
+
+v_min_i16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xf9,0x00,0x00]
+
+v_min_i16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xfd,0x00,0x00]
+
+v_min_i16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x00,0x00]
+
+v_min_i16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x01,0x01,0x00]
+
+v_min_i16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0x83,0x01,0x00]
+
+v_min_i16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_min_i16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_add_nc_i16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_i16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x0d,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_i16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0xff,0x05,0x02,0x00]
+
+v_add_nc_i16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x04,0x02,0x00]
+
+v_add_nc_i16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x65,0x04,0x02,0x00]
+
+v_add_nc_i16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x6a,0x04,0x02,0x00]
+
+v_add_nc_i16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x6b,0x04,0x02,0x00]
+
+v_add_nc_i16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x7c,0x04,0x02,0x00]
+
+v_add_nc_i16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x7e,0x04,0x02,0x00]
+
+v_add_nc_i16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x7f,0x04,0x02,0x00]
+
+v_add_nc_i16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x80,0x04,0x02,0x00]
+
+v_add_nc_i16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0xc1,0x04,0x02,0x00]
+
+v_add_nc_i16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_add_nc_i16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_add_nc_i16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x03,0x00]
+
+v_add_nc_i16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x05,0x00,0x00]
+
+v_add_nc_i16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xcb,0x00,0x00]
+
+v_add_nc_i16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xd5,0x00,0x00]
+
+v_add_nc_i16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xd7,0x00,0x00]
+
+v_add_nc_i16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xf9,0x00,0x00]
+
+v_add_nc_i16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xfd,0x00,0x00]
+
+v_add_nc_i16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x00,0x00]
+
+v_add_nc_i16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x01,0x01,0x00]
+
+v_add_nc_i16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0x83,0x01,0x00]
+
+v_add_nc_i16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_add_nc_i16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_i16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x0e,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_i16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0xff,0x05,0x02,0x00]
+
+v_sub_nc_i16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x04,0x02,0x00]
+
+v_sub_nc_i16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x65,0x04,0x02,0x00]
+
+v_sub_nc_i16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x6a,0x04,0x02,0x00]
+
+v_sub_nc_i16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x6b,0x04,0x02,0x00]
+
+v_sub_nc_i16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x7c,0x04,0x02,0x00]
+
+v_sub_nc_i16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x7e,0x04,0x02,0x00]
+
+v_sub_nc_i16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x7f,0x04,0x02,0x00]
+
+v_sub_nc_i16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x80,0x04,0x02,0x00]
+
+v_sub_nc_i16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0xc1,0x04,0x02,0x00]
+
+v_sub_nc_i16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_sub_nc_i16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xff,0x03,0x00]
+
+v_sub_nc_i16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x05,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xcb,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xd5,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xd7,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xf9,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xfd,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xff,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x01,0x01,0x00]
+
+v_sub_nc_i16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0x83,0x01,0x00]
+
+v_sub_nc_i16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_sub_nc_i16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x0e,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0xff,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x65,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x6a,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x6b,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x7c,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x7e,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x7f,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x80,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0xc1,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0xf0,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0xf7,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xff,0x03,0x00]
+
+v_pack_b32_f16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xcb,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xd5,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xd7,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xf9,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xfd,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xff,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x01,0x01,0x00]
+
+v_pack_b32_f16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x83,0x01,0x00]
+
+v_pack_b32_f16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xe1,0x01,0x00]
+
+v_pack_b32_f16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0xef,0x01,0x00]
+
+v_pack_b32_f16 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x20]
+
+v_pack_b32_f16 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x40]
+
+v_pack_b32_f16 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x60]
+
+v_pack_b32_f16 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,0]
+// GFX10: encoding: [0x05,0x00,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[1,0,0]
+// GFX10: encoding: [0x05,0x08,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[0,1,0]
+// GFX10: encoding: [0x05,0x10,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,1]
+// GFX10: encoding: [0x05,0x40,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[1,1,1]
+// GFX10: encoding: [0x05,0x58,0x11,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x65,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xcb,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_i16_f16 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_i16_f16 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_i16_f16 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,0]
+// GFX10: encoding: [0x05,0x00,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,0,0]
+// GFX10: encoding: [0x05,0x08,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,1,0]
+// GFX10: encoding: [0x05,0x10,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,1]
+// GFX10: encoding: [0x05,0x40,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,1,1]
+// GFX10: encoding: [0x05,0x58,0x12,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x65,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xcb,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, -v1, v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_u16_f16 v5, v1, -v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_u16_f16 v5, -v1, -v2
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_u16_f16 v5, |v1|, v2
+// GFX10: encoding: [0x05,0x01,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, |v2|
+// GFX10: encoding: [0x05,0x02,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, |v1|, |v2|
+// GFX10: encoding: [0x05,0x03,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,0]
+// GFX10: encoding: [0x05,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,0,0]
+// GFX10: encoding: [0x05,0x08,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,1,0]
+// GFX10: encoding: [0x05,0x10,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,1]
+// GFX10: encoding: [0x05,0x40,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1]
+// GFX10: encoding: [0x05,0x58,0x13,0xd7,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b16 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b16 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x14,0xd7,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b16 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b16 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b16 v5, s101, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x65,0x04,0x02,0x00]
+
+v_lshlrev_b16 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b16 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b16 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b16 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b16 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b16 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b16 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b16 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_lshlrev_b16 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x03,0x00]
+
+v_lshlrev_b16 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x05,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, s101
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xcb,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xd7,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xf9,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b16 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b16 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_mad_u16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd7,0x80,0x04,0x0e,0x04]
+
+v_mad_u16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x40,0xd7,0x01,0x83,0x0d,0x04]
+
+v_mad_u16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x40,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
+
+v_mad_u16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x40,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x40,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x40,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x40,0xd7,0x01,0x05,0x0e,0x04]
+
+v_interp_p1ll_f16 v5, v2, attr31.x
+// GFX10: encoding: [0x05,0x00,0x42,0xd7,0x1f,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.w
+// GFX10: encoding: [0x05,0x00,0x42,0xd7,0xc0,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, -v2, attr0.x
+// GFX10: encoding: [0x05,0x00,0x42,0xd7,0x00,0x04,0x02,0x40]
+
+v_interp_p1ll_f16 v5, |v2|, attr0.x
+// GFX10: encoding: [0x05,0x02,0x42,0xd7,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x high
+// GFX10: encoding: [0x05,0x00,0x42,0xd7,0x00,0x05,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x clamp
+// GFX10: encoding: [0x05,0x80,0x42,0xd7,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x mul:4
+// GFX10: encoding: [0x05,0x00,0x42,0xd7,0x00,0x04,0x02,0x10]
+
+v_interp_p1lv_f16 v5, v2, attr1.x, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x01,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.z, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x80,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, -v2, attr0.x, v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x04,0x0e,0x44]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, -v3
+// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x04,0x0e,0x84]
+
+v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
+// GFX10: encoding: [0x05,0x02,0x43,0xd7,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
+// GFX10: encoding: [0x05,0x04,0x43,0xd7,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
+// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x05,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x43,0xd7,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
+// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x04,0x0e,0x0c]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
+// GFX10: encoding: [0x05,0x00,0x43,0xd7,0x00,0x04,0x0e,0x1c]
+
+v_perm_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x0e,0x04]
+
+v_perm_b32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x44,0xd7,0x01,0x05,0x0e,0x04]
+
+v_perm_b32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0xff,0x05,0x0e,0x04]
+
+v_perm_b32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x04,0x0e,0x04]
+
+v_perm_b32 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x65,0x04,0x0e,0x04]
+
+v_perm_b32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_perm_b32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_perm_b32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_perm_b32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_perm_b32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_perm_b32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x80,0x04,0x0e,0x04]
+
+v_perm_b32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_perm_b32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_perm_b32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_perm_b32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xff,0x0f,0x04]
+
+v_perm_b32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x0c,0x04]
+
+v_perm_b32 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_perm_b32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_perm_b32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_perm_b32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_perm_b32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_perm_b32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xff,0x0c,0x04]
+
+v_perm_b32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x01,0x0d,0x04]
+
+v_perm_b32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x83,0x0d,0x04]
+
+v_perm_b32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_perm_b32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0xef,0x0d,0x04]
+
+v_perm_b32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xfe,0x07]
+
+v_perm_b32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x0e,0x00]
+
+v_perm_b32 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x96,0x01]
+
+v_perm_b32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xaa,0x01]
+
+v_perm_b32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xae,0x01]
+
+v_perm_b32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xf2,0x01]
+
+v_perm_b32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xfa,0x01]
+
+v_perm_b32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xfe,0x01]
+
+v_perm_b32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x02,0x02]
+
+v_perm_b32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0x06,0x03]
+
+v_perm_b32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xc2,0x03]
+
+v_perm_b32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x44,0xd7,0x01,0x05,0xde,0x03]
+
+v_xad_u32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x0e,0x04]
+
+v_xad_u32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x45,0xd7,0x01,0x05,0x0e,0x04]
+
+v_xad_u32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0xff,0x05,0x0e,0x04]
+
+v_xad_u32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x04,0x0e,0x04]
+
+v_xad_u32 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x65,0x04,0x0e,0x04]
+
+v_xad_u32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_xad_u32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_xad_u32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_xad_u32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_xad_u32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_xad_u32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x80,0x04,0x0e,0x04]
+
+v_xad_u32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_xad_u32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_xad_u32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_xad_u32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xff,0x0f,0x04]
+
+v_xad_u32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x0c,0x04]
+
+v_xad_u32 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_xad_u32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_xad_u32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_xad_u32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_xad_u32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_xad_u32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xff,0x0c,0x04]
+
+v_xad_u32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x01,0x0d,0x04]
+
+v_xad_u32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x83,0x0d,0x04]
+
+v_xad_u32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_xad_u32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0xef,0x0d,0x04]
+
+v_xad_u32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xfe,0x07]
+
+v_xad_u32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x0e,0x00]
+
+v_xad_u32 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x96,0x01]
+
+v_xad_u32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xaa,0x01]
+
+v_xad_u32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xae,0x01]
+
+v_xad_u32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xf2,0x01]
+
+v_xad_u32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xfa,0x01]
+
+v_xad_u32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xfe,0x01]
+
+v_xad_u32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x02,0x02]
+
+v_xad_u32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0x06,0x03]
+
+v_xad_u32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xc2,0x03]
+
+v_xad_u32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x45,0xd7,0x01,0x05,0xde,0x03]
+
+v_lshl_add_u32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x0e,0x04]
+
+v_lshl_add_u32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x46,0xd7,0x01,0x05,0x0e,0x04]
+
+v_lshl_add_u32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0xff,0x05,0x0e,0x04]
+
+v_lshl_add_u32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x65,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x80,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xff,0x0f,0x04]
+
+v_lshl_add_u32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xff,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x01,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x83,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0xef,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xfe,0x07]
+
+v_lshl_add_u32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x0e,0x00]
+
+v_lshl_add_u32 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x96,0x01]
+
+v_lshl_add_u32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xaa,0x01]
+
+v_lshl_add_u32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xae,0x01]
+
+v_lshl_add_u32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xf2,0x01]
+
+v_lshl_add_u32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xfa,0x01]
+
+v_lshl_add_u32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xfe,0x01]
+
+v_lshl_add_u32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x02,0x02]
+
+v_lshl_add_u32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0x06,0x03]
+
+v_lshl_add_u32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xc2,0x03]
+
+v_lshl_add_u32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x46,0xd7,0x01,0x05,0xde,0x03]
+
+v_add_lshl_u32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x0e,0x04]
+
+v_add_lshl_u32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x47,0xd7,0x01,0x05,0x0e,0x04]
+
+v_add_lshl_u32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0xff,0x05,0x0e,0x04]
+
+v_add_lshl_u32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x65,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x80,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xff,0x0f,0x04]
+
+v_add_lshl_u32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xff,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x01,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x83,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0xef,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xfe,0x07]
+
+v_add_lshl_u32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x0e,0x00]
+
+v_add_lshl_u32 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x96,0x01]
+
+v_add_lshl_u32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xaa,0x01]
+
+v_add_lshl_u32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xae,0x01]
+
+v_add_lshl_u32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xf2,0x01]
+
+v_add_lshl_u32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xfa,0x01]
+
+v_add_lshl_u32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xfe,0x01]
+
+v_add_lshl_u32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x02,0x02]
+
+v_add_lshl_u32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0x06,0x03]
+
+v_add_lshl_u32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xc2,0x03]
+
+v_add_lshl_u32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x47,0xd7,0x01,0x05,0xde,0x03]
+
+v_fma_f16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd7,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x4b,0xd7,0x01,0x05,0x0e,0x44]
+
+v_fma_f16 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x4b,0xd7,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x4b,0xd7,0x01,0x05,0x0e,0x04]
+
+// FIXME-GFX10-V_FMA_F16: See "FIXME-GFX10-V_FMA_F16" in VOP3Instructions.td.
+// v_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// FIXME-GFX10-V_FMA_F16: encoding: [0x05,0x08,0x4b,0xd7,0x01,0x05,0x0e,0x04]
+
+// v_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// FIXME-GFX10-V_FMA_F16: encoding: [0x05,0x10,0x4b,0xd7,0x01,0x05,0x0e,0x04]
+
+// v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// FIXME-GFX10-V_FMA_F16: encoding: [0x05,0x78,0x4b,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0xff,0x05,0x0e,0x04]
+
+v_min3_f16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x04,0x0e,0x04]
+
+v_min3_f16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x65,0x04,0x0e,0x04]
+
+v_min3_f16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_min3_f16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_min3_f16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_min3_f16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_min3_f16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_min3_f16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x80,0x04,0x0e,0x04]
+
+v_min3_f16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_min3_f16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_min3_f16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_min3_f16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xff,0x0f,0x04]
+
+v_min3_f16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0c,0x04]
+
+v_min3_f16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_min3_f16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_min3_f16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_min3_f16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_min3_f16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_min3_f16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xff,0x0c,0x04]
+
+v_min3_f16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x01,0x0d,0x04]
+
+v_min3_f16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x83,0x0d,0x04]
+
+v_min3_f16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_min3_f16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0xef,0x0d,0x04]
+
+v_min3_f16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xfe,0x07]
+
+v_min3_f16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x00]
+
+v_min3_f16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x96,0x01]
+
+v_min3_f16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xaa,0x01]
+
+v_min3_f16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xae,0x01]
+
+v_min3_f16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xf2,0x01]
+
+v_min3_f16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xfa,0x01]
+
+v_min3_f16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xfe,0x01]
+
+v_min3_f16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x02,0x02]
+
+v_min3_f16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x06,0x03]
+
+v_min3_f16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xc2,0x03]
+
+v_min3_f16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0xde,0x03]
+
+v_min3_f16 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x24]
+
+v_min3_f16 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x44]
+
+v_min3_f16 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x84]
+
+v_min3_f16 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0xe4]
+
+v_min3_f16 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x51,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x52,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0xff,0x05,0x0e,0x04]
+
+v_min3_i16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x04,0x0e,0x04]
+
+v_min3_i16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x65,0x04,0x0e,0x04]
+
+v_min3_i16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_min3_i16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_min3_i16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_min3_i16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_min3_i16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_min3_i16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x80,0x04,0x0e,0x04]
+
+v_min3_i16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_min3_i16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
+
+v_min3_i16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
+
+v_min3_i16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0f,0x04]
+
+v_min3_i16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x0c,0x04]
+
+v_min3_i16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_min3_i16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_min3_i16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_min3_i16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_min3_i16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_min3_i16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0c,0x04]
+
+v_min3_i16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x01,0x0d,0x04]
+
+v_min3_i16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x83,0x0d,0x04]
+
+v_min3_i16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
+
+v_min3_i16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
+
+v_min3_i16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x07]
+
+v_min3_i16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x0e,0x00]
+
+v_min3_i16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x96,0x01]
+
+v_min3_i16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xaa,0x01]
+
+v_min3_i16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xae,0x01]
+
+v_min3_i16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xf2,0x01]
+
+v_min3_i16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfa,0x01]
+
+v_min3_i16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x01]
+
+v_min3_i16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x02,0x02]
+
+v_min3_i16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x06,0x03]
+
+v_min3_i16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
+
+v_min3_i16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x52,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x52,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x52,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x52,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x52,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x52,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x52,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x53,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0xff,0x05,0x0e,0x04]
+
+v_min3_u16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x04,0x0e,0x04]
+
+v_min3_u16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x65,0x04,0x0e,0x04]
+
+v_min3_u16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_min3_u16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_min3_u16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_min3_u16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_min3_u16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_min3_u16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x80,0x04,0x0e,0x04]
+
+v_min3_u16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_min3_u16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
+
+v_min3_u16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
+
+v_min3_u16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xff,0x0f,0x04]
+
+v_min3_u16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x0c,0x04]
+
+v_min3_u16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_min3_u16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_min3_u16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_min3_u16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_min3_u16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_min3_u16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xff,0x0c,0x04]
+
+v_min3_u16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x01,0x0d,0x04]
+
+v_min3_u16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x83,0x0d,0x04]
+
+v_min3_u16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
+
+v_min3_u16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
+
+v_min3_u16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfe,0x07]
+
+v_min3_u16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x0e,0x00]
+
+v_min3_u16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x96,0x01]
+
+v_min3_u16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xaa,0x01]
+
+v_min3_u16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xae,0x01]
+
+v_min3_u16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xf2,0x01]
+
+v_min3_u16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfa,0x01]
+
+v_min3_u16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfe,0x01]
+
+v_min3_u16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x02,0x02]
+
+v_min3_u16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x06,0x03]
+
+v_min3_u16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
+
+v_min3_u16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x53,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x53,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x53,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x53,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x53,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x53,0xd7,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x53,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0xff,0x05,0x0e,0x04]
+
+v_max3_f16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x04,0x0e,0x04]
+
+v_max3_f16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x65,0x04,0x0e,0x04]
+
+v_max3_f16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_max3_f16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_max3_f16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_max3_f16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_max3_f16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_max3_f16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x80,0x04,0x0e,0x04]
+
+v_max3_f16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_max3_f16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_max3_f16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_max3_f16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xff,0x0f,0x04]
+
+v_max3_f16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0c,0x04]
+
+v_max3_f16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_max3_f16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_max3_f16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_max3_f16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_max3_f16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_max3_f16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xff,0x0c,0x04]
+
+v_max3_f16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x01,0x0d,0x04]
+
+v_max3_f16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x83,0x0d,0x04]
+
+v_max3_f16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_max3_f16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0xef,0x0d,0x04]
+
+v_max3_f16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xfe,0x07]
+
+v_max3_f16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x00]
+
+v_max3_f16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x96,0x01]
+
+v_max3_f16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xaa,0x01]
+
+v_max3_f16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xae,0x01]
+
+v_max3_f16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xf2,0x01]
+
+v_max3_f16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xfa,0x01]
+
+v_max3_f16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xfe,0x01]
+
+v_max3_f16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x02,0x02]
+
+v_max3_f16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x06,0x03]
+
+v_max3_f16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xc2,0x03]
+
+v_max3_f16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0xde,0x03]
+
+v_max3_f16 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x24]
+
+v_max3_f16 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x44]
+
+v_max3_f16 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x84]
+
+v_max3_f16 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0xe4]
+
+v_max3_f16 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x54,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x55,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0xff,0x05,0x0e,0x04]
+
+v_max3_i16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x04,0x0e,0x04]
+
+v_max3_i16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x65,0x04,0x0e,0x04]
+
+v_max3_i16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_max3_i16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_max3_i16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_max3_i16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_max3_i16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_max3_i16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x80,0x04,0x0e,0x04]
+
+v_max3_i16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_max3_i16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
+
+v_max3_i16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
+
+v_max3_i16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xff,0x0f,0x04]
+
+v_max3_i16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x0c,0x04]
+
+v_max3_i16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_max3_i16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_max3_i16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_max3_i16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_max3_i16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_max3_i16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xff,0x0c,0x04]
+
+v_max3_i16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x01,0x0d,0x04]
+
+v_max3_i16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x83,0x0d,0x04]
+
+v_max3_i16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
+
+v_max3_i16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
+
+v_max3_i16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfe,0x07]
+
+v_max3_i16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x0e,0x00]
+
+v_max3_i16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x96,0x01]
+
+v_max3_i16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xaa,0x01]
+
+v_max3_i16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xae,0x01]
+
+v_max3_i16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xf2,0x01]
+
+v_max3_i16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfa,0x01]
+
+v_max3_i16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfe,0x01]
+
+v_max3_i16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x02,0x02]
+
+v_max3_i16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x06,0x03]
+
+v_max3_i16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
+
+v_max3_i16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x55,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x55,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x55,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x55,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x55,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x55,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x55,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x56,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0xff,0x05,0x0e,0x04]
+
+v_max3_u16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x04,0x0e,0x04]
+
+v_max3_u16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x65,0x04,0x0e,0x04]
+
+v_max3_u16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_max3_u16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_max3_u16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_max3_u16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_max3_u16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_max3_u16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x80,0x04,0x0e,0x04]
+
+v_max3_u16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_max3_u16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
+
+v_max3_u16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
+
+v_max3_u16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xff,0x0f,0x04]
+
+v_max3_u16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x0c,0x04]
+
+v_max3_u16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_max3_u16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_max3_u16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_max3_u16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_max3_u16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_max3_u16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xff,0x0c,0x04]
+
+v_max3_u16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x01,0x0d,0x04]
+
+v_max3_u16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x83,0x0d,0x04]
+
+v_max3_u16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
+
+v_max3_u16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
+
+v_max3_u16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfe,0x07]
+
+v_max3_u16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x0e,0x00]
+
+v_max3_u16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x96,0x01]
+
+v_max3_u16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xaa,0x01]
+
+v_max3_u16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xae,0x01]
+
+v_max3_u16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xf2,0x01]
+
+v_max3_u16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfa,0x01]
+
+v_max3_u16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfe,0x01]
+
+v_max3_u16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x02,0x02]
+
+v_max3_u16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x06,0x03]
+
+v_max3_u16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
+
+v_max3_u16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x56,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x56,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x56,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x56,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x56,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x56,0xd7,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x56,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0xff,0x05,0x0e,0x04]
+
+v_med3_f16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x04,0x0e,0x04]
+
+v_med3_f16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x65,0x04,0x0e,0x04]
+
+v_med3_f16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_med3_f16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_med3_f16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_med3_f16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_med3_f16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_med3_f16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x80,0x04,0x0e,0x04]
+
+v_med3_f16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_med3_f16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_med3_f16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_med3_f16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xff,0x0f,0x04]
+
+v_med3_f16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0c,0x04]
+
+v_med3_f16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_med3_f16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_med3_f16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_med3_f16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_med3_f16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_med3_f16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xff,0x0c,0x04]
+
+v_med3_f16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x01,0x0d,0x04]
+
+v_med3_f16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x83,0x0d,0x04]
+
+v_med3_f16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_med3_f16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0xef,0x0d,0x04]
+
+v_med3_f16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xfe,0x07]
+
+v_med3_f16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x00]
+
+v_med3_f16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x96,0x01]
+
+v_med3_f16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xaa,0x01]
+
+v_med3_f16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xae,0x01]
+
+v_med3_f16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xf2,0x01]
+
+v_med3_f16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xfa,0x01]
+
+v_med3_f16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xfe,0x01]
+
+v_med3_f16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x02,0x02]
+
+v_med3_f16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x06,0x03]
+
+v_med3_f16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xc2,0x03]
+
+v_med3_f16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0xde,0x03]
+
+v_med3_f16 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x24]
+
+v_med3_f16 v5, v1, -v2, v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x44]
+
+v_med3_f16 v5, v1, v2, -v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x84]
+
+v_med3_f16 v5, -v1, -v2, -v3
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0xe4]
+
+v_med3_f16 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, |v2|, v3
+// GFX10: encoding: [0x05,0x02,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, |v3|
+// GFX10: encoding: [0x05,0x04,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, |v1|, |v2|, |v3|
+// GFX10: encoding: [0x05,0x07,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x57,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x58,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0xff,0x05,0x0e,0x04]
+
+v_med3_i16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x04,0x0e,0x04]
+
+v_med3_i16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x65,0x04,0x0e,0x04]
+
+v_med3_i16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_med3_i16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_med3_i16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_med3_i16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_med3_i16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_med3_i16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x80,0x04,0x0e,0x04]
+
+v_med3_i16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_med3_i16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
+
+v_med3_i16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
+
+v_med3_i16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xff,0x0f,0x04]
+
+v_med3_i16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x0c,0x04]
+
+v_med3_i16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_med3_i16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_med3_i16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_med3_i16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_med3_i16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_med3_i16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xff,0x0c,0x04]
+
+v_med3_i16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x01,0x0d,0x04]
+
+v_med3_i16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x83,0x0d,0x04]
+
+v_med3_i16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
+
+v_med3_i16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
+
+v_med3_i16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfe,0x07]
+
+v_med3_i16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x0e,0x00]
+
+v_med3_i16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x96,0x01]
+
+v_med3_i16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xaa,0x01]
+
+v_med3_i16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xae,0x01]
+
+v_med3_i16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xf2,0x01]
+
+v_med3_i16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfa,0x01]
+
+v_med3_i16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfe,0x01]
+
+v_med3_i16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x02,0x02]
+
+v_med3_i16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x06,0x03]
+
+v_med3_i16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
+
+v_med3_i16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x58,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x58,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x58,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x58,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x58,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x58,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x58,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x59,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0xff,0x05,0x0e,0x04]
+
+v_med3_u16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x04,0x0e,0x04]
+
+v_med3_u16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x65,0x04,0x0e,0x04]
+
+v_med3_u16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_med3_u16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_med3_u16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_med3_u16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_med3_u16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_med3_u16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x80,0x04,0x0e,0x04]
+
+v_med3_u16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_med3_u16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
+
+v_med3_u16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
+
+v_med3_u16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xff,0x0f,0x04]
+
+v_med3_u16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x0c,0x04]
+
+v_med3_u16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_med3_u16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_med3_u16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_med3_u16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_med3_u16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_med3_u16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xff,0x0c,0x04]
+
+v_med3_u16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x01,0x0d,0x04]
+
+v_med3_u16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x83,0x0d,0x04]
+
+v_med3_u16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
+
+v_med3_u16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
+
+v_med3_u16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfe,0x07]
+
+v_med3_u16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x0e,0x00]
+
+v_med3_u16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x96,0x01]
+
+v_med3_u16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xaa,0x01]
+
+v_med3_u16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xae,0x01]
+
+v_med3_u16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xf2,0x01]
+
+v_med3_u16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfa,0x01]
+
+v_med3_u16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfe,0x01]
+
+v_med3_u16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x02,0x02]
+
+v_med3_u16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x06,0x03]
+
+v_med3_u16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfe,0x03,0x00,0x38,0x00,0x00]
+
+v_med3_u16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x59,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x59,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x59,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x59,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x59,0xd7,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x59,0xd7,0x01,0x05,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd7,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, -v2, attr0.x, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd7,0x00,0x04,0x0e,0x44]
+
+v_interp_p2_f16 v5, v2, attr0.x, |v3|
+// GFX10: encoding: [0x05,0x04,0x5a,0xd7,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.w, v3
+// GFX10: encoding: [0x05,0x00,0x5a,0xd7,0xc0,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 high
+// GFX10: encoding: [0x05,0x00,0x5a,0xd7,0x00,0x05,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x5a,0xd7,0x00,0x04,0x0e,0x04]
+
+v_mad_i16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd7,0x80,0x04,0x0e,0x04]
+
+v_mad_i16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x5e,0xd7,0x01,0x83,0x0d,0x04]
+
+v_mad_i16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x5e,0xd7,0x01,0x05,0xfe,0x03,0x00,0xc4,0x00,0x00]
+
+v_mad_i16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x5e,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x5e,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x5e,0xd7,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x5f,0xd7,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f16 v5, -v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x5f,0xd7,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f16 v5, |v1|, v2, v3
+// GFX10: encoding: [0x05,0x01,0x5f,0xd7,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x5f,0xd7,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x5f,0xd7,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x5f,0xd7,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x5f,0xd7,0x01,0x05,0x0e,0x04]
+
+v_add3_u32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x0e,0x04]
+
+v_add3_u32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x6d,0xd7,0x01,0x05,0x0e,0x04]
+
+v_add3_u32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0xff,0x05,0x0e,0x04]
+
+v_add3_u32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x04,0x0e,0x04]
+
+v_add3_u32 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x65,0x04,0x0e,0x04]
+
+v_add3_u32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_add3_u32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_add3_u32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_add3_u32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_add3_u32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_add3_u32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x80,0x04,0x0e,0x04]
+
+v_add3_u32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_add3_u32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_add3_u32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_add3_u32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xff,0x0f,0x04]
+
+v_add3_u32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x0c,0x04]
+
+v_add3_u32 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_add3_u32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_add3_u32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_add3_u32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_add3_u32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_add3_u32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xff,0x0c,0x04]
+
+v_add3_u32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x01,0x0d,0x04]
+
+v_add3_u32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x83,0x0d,0x04]
+
+v_add3_u32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_add3_u32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0xef,0x0d,0x04]
+
+v_add3_u32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xfe,0x07]
+
+v_add3_u32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x0e,0x00]
+
+v_add3_u32 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x96,0x01]
+
+v_add3_u32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xaa,0x01]
+
+v_add3_u32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xae,0x01]
+
+v_add3_u32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xf2,0x01]
+
+v_add3_u32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xfa,0x01]
+
+v_add3_u32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xfe,0x01]
+
+v_add3_u32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x02,0x02]
+
+v_add3_u32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0x06,0x03]
+
+v_add3_u32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xc2,0x03]
+
+v_add3_u32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x6d,0xd7,0x01,0x05,0xde,0x03]
+
+v_lshl_or_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x0e,0x04]
+
+v_lshl_or_b32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x6f,0xd7,0x01,0x05,0x0e,0x04]
+
+v_lshl_or_b32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0xff,0x05,0x0e,0x04]
+
+v_lshl_or_b32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x65,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x80,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xff,0x0f,0x04]
+
+v_lshl_or_b32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xff,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x01,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x83,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0xef,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xfe,0x07]
+
+v_lshl_or_b32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x0e,0x00]
+
+v_lshl_or_b32 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x96,0x01]
+
+v_lshl_or_b32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xaa,0x01]
+
+v_lshl_or_b32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xae,0x01]
+
+v_lshl_or_b32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xf2,0x01]
+
+v_lshl_or_b32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xfa,0x01]
+
+v_lshl_or_b32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xfe,0x01]
+
+v_lshl_or_b32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x02,0x02]
+
+v_lshl_or_b32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0x06,0x03]
+
+v_lshl_or_b32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xc2,0x03]
+
+v_lshl_or_b32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x6f,0xd7,0x01,0x05,0xde,0x03]
+
+v_and_or_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x0e,0x04]
+
+v_and_or_b32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x71,0xd7,0x01,0x05,0x0e,0x04]
+
+v_and_or_b32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0xff,0x05,0x0e,0x04]
+
+v_and_or_b32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x65,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x80,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xff,0x0f,0x04]
+
+v_and_or_b32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x0c,0x04]
+
+v_and_or_b32 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_and_or_b32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_and_or_b32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_and_or_b32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_and_or_b32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_and_or_b32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xff,0x0c,0x04]
+
+v_and_or_b32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x01,0x0d,0x04]
+
+v_and_or_b32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x83,0x0d,0x04]
+
+v_and_or_b32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_and_or_b32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0xef,0x0d,0x04]
+
+v_and_or_b32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xfe,0x07]
+
+v_and_or_b32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x0e,0x00]
+
+v_and_or_b32 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x96,0x01]
+
+v_and_or_b32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xaa,0x01]
+
+v_and_or_b32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xae,0x01]
+
+v_and_or_b32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xf2,0x01]
+
+v_and_or_b32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xfa,0x01]
+
+v_and_or_b32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xfe,0x01]
+
+v_and_or_b32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x02,0x02]
+
+v_and_or_b32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0x06,0x03]
+
+v_and_or_b32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xc2,0x03]
+
+v_and_or_b32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x71,0xd7,0x01,0x05,0xde,0x03]
+
+v_or3_b32 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x0e,0x04]
+
+v_or3_b32 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x72,0xd7,0x01,0x05,0x0e,0x04]
+
+v_or3_b32 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0xff,0x05,0x0e,0x04]
+
+v_or3_b32 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x04,0x0e,0x04]
+
+v_or3_b32 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x65,0x04,0x0e,0x04]
+
+v_or3_b32 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_or3_b32 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_or3_b32 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_or3_b32 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_or3_b32 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_or3_b32 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x80,0x04,0x0e,0x04]
+
+v_or3_b32 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_or3_b32 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0xf0,0x04,0x0e,0x04]
+
+v_or3_b32 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0xf7,0x04,0x0e,0x04]
+
+v_or3_b32 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xff,0x0f,0x04]
+
+v_or3_b32 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x0c,0x04]
+
+v_or3_b32 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_or3_b32 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_or3_b32 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_or3_b32 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_or3_b32 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_or3_b32 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xff,0x0c,0x04]
+
+v_or3_b32 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x01,0x0d,0x04]
+
+v_or3_b32 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x83,0x0d,0x04]
+
+v_or3_b32 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xe1,0x0d,0x04]
+
+v_or3_b32 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0xef,0x0d,0x04]
+
+v_or3_b32 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xfe,0x07]
+
+v_or3_b32 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x0e,0x00]
+
+v_or3_b32 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x96,0x01]
+
+v_or3_b32 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xaa,0x01]
+
+v_or3_b32 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xae,0x01]
+
+v_or3_b32 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xf2,0x01]
+
+v_or3_b32 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xfa,0x01]
+
+v_or3_b32 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xfe,0x01]
+
+v_or3_b32 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x02,0x02]
+
+v_or3_b32 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0x06,0x03]
+
+v_or3_b32 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xc2,0x03]
+
+v_or3_b32 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x72,0xd7,0x01,0x05,0xde,0x03]
+
+v_mad_u32_u16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x73,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0xff,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x65,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x80,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
+
+v_mad_u32_u16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
+
+v_mad_u32_u16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xff,0x0f,0x04]
+
+v_mad_u32_u16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xff,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x01,0x0d,0x04]
+
+v_mad_u32_u16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x83,0x0d,0x04]
+
+v_mad_u32_u16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
+
+v_mad_u32_u16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
+
+v_mad_u32_u16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xfe,0x07]
+
+v_mad_u32_u16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x0e,0x00]
+
+v_mad_u32_u16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x96,0x01]
+
+v_mad_u32_u16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xaa,0x01]
+
+v_mad_u32_u16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xae,0x01]
+
+v_mad_u32_u16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xf2,0x01]
+
+v_mad_u32_u16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xfa,0x01]
+
+v_mad_u32_u16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xfe,0x01]
+
+v_mad_u32_u16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x02,0x02]
+
+v_mad_u32_u16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x06,0x03]
+
+v_mad_u32_u16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xc2,0x03]
+
+v_mad_u32_u16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0xde,0x03]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x73,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x73,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x73,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x73,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x73,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x73,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x73,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v255, v1, v2, v3
+// GFX10: encoding: [0xff,0x00,0x75,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v255, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0xff,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, s1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, s101, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x65,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, vcc_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x6a,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, vcc_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x6b,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, m0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x7c,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, exec_lo, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x7e,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, exec_hi, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x7f,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, 0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x80,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, -1, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0xc1,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, 0.5, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0xff,0x04,0x0e,0x04,0x00,0x38,0x00,0x00]
+
+v_mad_i32_i16 v5, -4.0, v2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0xff,0x04,0x0e,0x04,0x00,0xc4,0x00,0x00]
+
+v_mad_i32_i16 v5, v1, v255, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xff,0x0f,0x04]
+
+v_mad_i32_i16 v5, v1, s2, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, s101, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xcb,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, vcc_lo, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xd5,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, vcc_hi, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xd7,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, m0, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xf9,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, exec_lo, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xfd,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, exec_hi, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xff,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, 0, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x01,0x0d,0x04]
+
+v_mad_i32_i16 v5, v1, -1, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x83,0x0d,0x04]
+
+v_mad_i32_i16 v5, v1, 0.5, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xff,0x0d,0x04,0x00,0x38,0x00,0x00]
+
+v_mad_i32_i16 v5, v1, -4.0, v3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0xff,0x0d,0x04,0x00,0xc4,0x00,0x00]
+
+v_mad_i32_i16 v5, v1, v2, v255
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xfe,0x07]
+
+v_mad_i32_i16 v5, v1, v2, s3
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x0e,0x00]
+
+v_mad_i32_i16 v5, v1, v2, s101
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x96,0x01]
+
+v_mad_i32_i16 v5, v1, v2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xaa,0x01]
+
+v_mad_i32_i16 v5, v1, v2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xae,0x01]
+
+v_mad_i32_i16 v5, v1, v2, m0
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xf2,0x01]
+
+v_mad_i32_i16 v5, v1, v2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xfa,0x01]
+
+v_mad_i32_i16 v5, v1, v2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xfe,0x01]
+
+v_mad_i32_i16 v5, v1, v2, 0
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x02,0x02]
+
+v_mad_i32_i16 v5, v1, v2, -1
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x06,0x03]
+
+v_mad_i32_i16 v5, v1, v2, 0.5
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xc2,0x03]
+
+v_mad_i32_i16 v5, v1, v2, -4.0
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0xde,0x03]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// GFX10: encoding: [0x05,0x00,0x75,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// GFX10: encoding: [0x05,0x08,0x75,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// GFX10: encoding: [0x05,0x10,0x75,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// GFX10: encoding: [0x05,0x20,0x75,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// GFX10: encoding: [0x05,0x40,0x75,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// GFX10: encoding: [0x05,0x78,0x75,0xd7,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 clamp
+// GFX10: encoding: [0x05,0x80,0x75,0xd7,0x01,0x05,0x0e,0x04]
+
+v_sub_nc_i32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_i32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x76,0xd7,0x01,0x05,0x02,0x00]
+
+v_sub_nc_i32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0xff,0x05,0x02,0x00]
+
+v_sub_nc_i32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x67,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x6b,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x77,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x7c,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x7e,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x7f,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x80,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0xc1,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0xf0,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0xf7,0x04,0x02,0x00]
+
+v_sub_nc_i32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xff,0x03,0x00]
+
+v_sub_nc_i32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x05,0x00,0x00]
+
+v_sub_nc_i32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xcf,0x00,0x00]
+
+v_sub_nc_i32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xd5,0x00,0x00]
+
+v_sub_nc_i32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xd7,0x00,0x00]
+
+v_sub_nc_i32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xef,0x00,0x00]
+
+v_sub_nc_i32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xf9,0x00,0x00]
+
+v_sub_nc_i32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xfd,0x00,0x00]
+
+v_sub_nc_i32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xff,0x00,0x00]
+
+v_sub_nc_i32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x01,0x01,0x00]
+
+v_sub_nc_i32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0x83,0x01,0x00]
+
+v_sub_nc_i32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xe1,0x01,0x00]
+
+v_sub_nc_i32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x76,0xd7,0x01,0xef,0x01,0x00]
+
+v_sub_nc_i32 v5, v1, -4.0 clamp
+// GFX10: v_sub_nc_i32 v5, v1, -4.0 clamp ; encoding: [0x05,0x80,0x76,0xd7,0x01,0xef,0x01,0x00]
+
+v_permlane16_b32 v5, v1, v2, v3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlane16_b32 v5, v1, v2, s3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlane16_b32 v5, v1, s2, v3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlane16_b32 v5, s1, s2, s3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlane16_b32 v5, 0, s2, s3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlane16_b32 v5, v1, s2, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlane16_b32 v255, v1, s2, s3
+// GFX10: encoding: [0xff,0x00,0x77,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlane16_b32 v5, v255, s2, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0xff,0x05,0x0c,0x00]
+
+v_permlane16_b32 v5, v103, s2, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x67,0x05,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, vcc_lo, s2
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xd5,0x08,0x00]
+
+v_permlane16_b32 v5, v1, vcc_hi, s2
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xd7,0x08,0x00]
+
+v_permlane16_b32 v5, v1, ttmp11, s2
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xef,0x08,0x00]
+
+v_permlane16_b32 v5, v1, m0, s2
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xf9,0x08,0x00]
+
+v_permlane16_b32 v5, v1, exec_lo, s2
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xfd,0x08,0x00]
+
+v_permlane16_b32 v5, v1, exec_hi, s2
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xff,0x08,0x00]
+
+v_permlane16_b32 v5, v1, s103, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xcf,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, vcc_lo, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xd5,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, vcc_hi, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xd7,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, ttmp11, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xef,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, m0, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xf9,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, exec_lo, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xfd,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, exec_hi, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xff,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, 0, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x01,0x0d,0x00]
+
+v_permlane16_b32 v5, v1, -1, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x83,0x0d,0x00]
+
+v_permlane16_b32 v5, v1, 0.5, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xe1,0x0d,0x00]
+
+v_permlane16_b32 v5, v1, -4.0, s3
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0xef,0x0d,0x00]
+
+v_permlane16_b32 v5, v1, s2, s103
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x9c,0x01]
+
+v_permlane16_b32 v5, v1, s2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xa8,0x01]
+
+v_permlane16_b32 v5, v1, s2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xac,0x01]
+
+v_permlane16_b32 v5, v1, s2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x01]
+
+v_permlane16_b32 v5, v1, s2, m0
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xf0,0x01]
+
+v_permlane16_b32 v5, v1, s2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xf8,0x01]
+
+v_permlane16_b32 v5, v1, s2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xfc,0x01]
+
+v_permlane16_b32 v5, v1, s2, 0
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x00,0x02]
+
+v_permlane16_b32 v5, v1, s2, -1
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0x04,0x03]
+
+v_permlane16_b32 v5, v1, s2, 0.5
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xc0,0x03]
+
+v_permlane16_b32 v5, v1, s2, -4.0
+// GFX10: encoding: [0x05,0x00,0x77,0xd7,0x01,0x05,0xdc,0x03]
+
+v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,0]
+// GFX10: encoding: [0x05,0x08,0x77,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, s2, s3 op_sel:[1,1]
+// GFX10: encoding: [0x05,0x18,0x77,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, s2, s3 op_sel:[0,1]
+// GFX10: encoding: [0x05,0x10,0x77,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 1, 0]
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_permlanex16_b32 v5, v1, v2, v3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlanex16_b32 v5, v1, v2, s3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlanex16_b32 v5, v1, s2, v3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlanex16_b32 v5, s1, s2, s3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlanex16_b32 v5, 0, s2, s3
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_permlanex16_b32 v5, v1, s2, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlanex16_b32 v255, v1, s2, s3
+// GFX10: encoding: [0xff,0x00,0x78,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlanex16_b32 v5, v255, s2, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0xff,0x05,0x0c,0x00]
+
+v_permlanex16_b32 v5, v103, s2, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x67,0x05,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, vcc_lo, s2
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xd5,0x08,0x00]
+
+v_permlanex16_b32 v5, v1, vcc_hi, s2
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xd7,0x08,0x00]
+
+v_permlanex16_b32 v5, v1, ttmp11, s2
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xef,0x08,0x00]
+
+v_permlanex16_b32 v5, v1, m0, s2
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xf9,0x08,0x00]
+
+v_permlanex16_b32 v5, v1, exec_lo, s2
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xfd,0x08,0x00]
+
+v_permlanex16_b32 v5, v1, exec_hi, s2
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xff,0x08,0x00]
+
+v_permlanex16_b32 v5, v1, s103, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xcf,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, vcc_lo, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xd5,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, vcc_hi, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xd7,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, ttmp11, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xef,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, m0, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xf9,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, exec_lo, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xfd,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, exec_hi, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xff,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, 0, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x01,0x0d,0x00]
+
+v_permlanex16_b32 v5, v1, -1, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x83,0x0d,0x00]
+
+v_permlanex16_b32 v5, v1, 0.5, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xe1,0x0d,0x00]
+
+v_permlanex16_b32 v5, v1, -4.0, s3
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0xef,0x0d,0x00]
+
+v_permlanex16_b32 v5, v1, s2, s103
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x9c,0x01]
+
+v_permlanex16_b32 v5, v1, s2, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xa8,0x01]
+
+v_permlanex16_b32 v5, v1, s2, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xac,0x01]
+
+v_permlanex16_b32 v5, v1, s2, ttmp11
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x01]
+
+v_permlanex16_b32 v5, v1, s2, m0
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xf0,0x01]
+
+v_permlanex16_b32 v5, v1, s2, exec_lo
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xf8,0x01]
+
+v_permlanex16_b32 v5, v1, s2, exec_hi
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xfc,0x01]
+
+v_permlanex16_b32 v5, v1, s2, 0
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x00,0x02]
+
+v_permlanex16_b32 v5, v1, s2, -1
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0x04,0x03]
+
+v_permlanex16_b32 v5, v1, s2, 0.5
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xc0,0x03]
+
+v_permlanex16_b32 v5, v1, s2, -4.0
+// GFX10: encoding: [0x05,0x00,0x78,0xd7,0x01,0x05,0xdc,0x03]
+
+v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,0]
+// GFX10: encoding: [0x05,0x08,0x78,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, s2, s3 op_sel:[1,1]
+// GFX10: encoding: [0x05,0x18,0x78,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0,1]
+// GFX10: encoding: [0x05,0x10,0x78,0xd7,0x01,0x05,0x0c,0x00]
+
+v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_permlanex16_b32 v5, v1, s2, s3 op_sel:[0, 0, 1, 0]
+// GFX10-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid op_sel operand
+
+v_add_nc_i32 v5, v1, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_i32 v255, v1, v2
+// GFX10: encoding: [0xff,0x00,0x7f,0xd7,0x01,0x05,0x02,0x00]
+
+v_add_nc_i32 v5, v255, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0xff,0x05,0x02,0x00]
+
+v_add_nc_i32 v5, s1, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, s103, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x67,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, vcc_lo, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, vcc_hi, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x6b,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, ttmp11, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x77,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, m0, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x7c,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, exec_lo, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x7e,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, exec_hi, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x7f,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, 0, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x80,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, -1, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0xc1,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, 0.5, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0xf0,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, -4.0, v2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0xf7,0x04,0x02,0x00]
+
+v_add_nc_i32 v5, v1, v255
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xff,0x03,0x00]
+
+v_add_nc_i32 v5, v1, s2
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x05,0x00,0x00]
+
+v_add_nc_i32 v5, v1, s103
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xcf,0x00,0x00]
+
+v_add_nc_i32 v5, v1, vcc_lo
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xd5,0x00,0x00]
+
+v_add_nc_i32 v5, v1, vcc_hi
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xd7,0x00,0x00]
+
+v_add_nc_i32 v5, v1, ttmp11
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xef,0x00,0x00]
+
+v_add_nc_i32 v5, v1, m0
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xf9,0x00,0x00]
+
+v_add_nc_i32 v5, v1, exec_lo
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xfd,0x00,0x00]
+
+v_add_nc_i32 v5, v1, exec_hi
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xff,0x00,0x00]
+
+v_add_nc_i32 v5, v1, 0
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x01,0x01,0x00]
+
+v_add_nc_i32 v5, v1, -1
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0x83,0x01,0x00]
+
+v_add_nc_i32 v5, v1, 0.5
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xe1,0x01,0x00]
+
+v_add_nc_i32 v5, v1, -4.0
+// GFX10: encoding: [0x05,0x00,0x7f,0xd7,0x01,0xef,0x01,0x00]
+
+v_add_nc_i32 v5, v1, -4.0 clamp
+// GFX10: v_add_nc_i32 v5, v1, -4.0 clamp ; encoding: [0x05,0x80,0x7f,0xd7,0x01,0xef,0x01,0x00]
+
+//===----------------------------------------------------------------------===//
+// ENC_VOP3 INTERP.
+//===----------------------------------------------------------------------===//
+
+v_interp_p1_f32_e64 v5, v2, attr0.x
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v255, v2, attr0.x
+// GFX10: v_interp_p1_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x00,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr1.x
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x00,0xd6,0x01,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr31.x
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x00,0xd6,0x1f,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr32.x
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x00,0xd6,0x20,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v255, attr0.x
+// GFX10: v_interp_p1_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0xfe,0x03,0x00]
+
+v_interp_p1_f32_e64 v5, -v2, attr0.x
+// GFX10: v_interp_p1_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x40]
+
+v_interp_p1_f32_e64 v5, |v2|, attr0.x
+// GFX10: v_interp_p1_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x00,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.y
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x00,0xd6,0x40,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.z
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x00,0xd6,0x80,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.w
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x00,0xd6,0xc0,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x clamp
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x00,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x08]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:4
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x10]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x div:2
+// GFX10: v_interp_p1_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x00,0xd6,0x00,0x04,0x02,0x18]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v255, v2, attr0.x
+// GFX10: v_interp_p2_f32_e64 v255, v2, attr0.x ; encoding: [0xff,0x00,0x01,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr1.x
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr1.x ; encoding: [0x05,0x00,0x01,0xd6,0x01,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr31.x
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr31.x ; encoding: [0x05,0x00,0x01,0xd6,0x1f,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr32.x
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr32.x ; encoding: [0x05,0x00,0x01,0xd6,0x20,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v255, attr0.x
+// GFX10: v_interp_p2_f32_e64 v5, v255, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0xfe,0x03,0x00]
+
+v_interp_p2_f32_e64 v5, -v2, attr0.x
+// GFX10: v_interp_p2_f32_e64 v5, -v2, attr0.x ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x40]
+
+v_interp_p2_f32_e64 v5, |v2|, attr0.x
+// GFX10: v_interp_p2_f32_e64 v5, |v2|, attr0.x ; encoding: [0x05,0x02,0x01,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.y
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.y ; encoding: [0x05,0x00,0x01,0xd6,0x40,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.z
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.z ; encoding: [0x05,0x00,0x01,0xd6,0x80,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.w
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.w ; encoding: [0x05,0x00,0x01,0xd6,0xc0,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x clamp
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x clamp ; encoding: [0x05,0x80,0x01,0xd6,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x mul:2
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x08]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x mul:4
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x mul:4 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x10]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x div:2
+// GFX10: v_interp_p2_f32_e64 v5, v2, attr0.x div:2 ; encoding: [0x05,0x00,0x01,0xd6,0x00,0x04,0x02,0x18]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v255, p10, attr0.x
+// GFX10: v_interp_mov_f32_e64 v255, p10, attr0.x ; encoding: [0xff,0x00,0x02,0xd6,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr1.x
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr1.x ; encoding: [0x05,0x00,0x02,0xd6,0x01,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr31.x
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr31.x ; encoding: [0x05,0x00,0x02,0xd6,0x1f,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr32.x
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr32.x ; encoding: [0x05,0x00,0x02,0xd6,0x20,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p20, attr0.x
+// GFX10: v_interp_mov_f32_e64 v5, p20, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x02,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p0, attr0.x
+// GFX10: v_interp_mov_f32_e64 v5, p0, attr0.x ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x04,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.y
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.y ; encoding: [0x05,0x00,0x02,0xd6,0x40,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.z
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.z ; encoding: [0x05,0x00,0x02,0xd6,0x80,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.w
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.w ; encoding: [0x05,0x00,0x02,0xd6,0xc0,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x clamp
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x clamp ; encoding: [0x05,0x80,0x02,0xd6,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x08]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x mul:4 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x10]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x div:2
+// GFX10: v_interp_mov_f32_e64 v5, p10, attr0.x div:2 ; encoding: [0x05,0x00,0x02,0xd6,0x00,0x00,0x00,0x18]
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx10_asm_vopc.s
new file mode 100644
index 0000000000000..ef13457e79e45
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vopc.s
@@ -0,0 +1,11576 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W64-ERR --implicit-check-not=error: %s
+
+//===----------------------------------------------------------------------===//
+// ENC_VOPC - v_cmp_* opcodes.
+//===----------------------------------------------------------------------===//
+
+v_cmp_f_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x00,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x00,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x00,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x01,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x00,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x00,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x00,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x01,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x02,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x02,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x02,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x03,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x02,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x02,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x02,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x03,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x04,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x04,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x04,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x05,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x04,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x04,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x04,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x05,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x06,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x06,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x06,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x07,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x06,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x06,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x06,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x07,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x08,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x08,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x08,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x09,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x08,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x08,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x08,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x09,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x0a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x0a,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x0a,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x0b,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x0a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x0a,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x0a,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x0b,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x0c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x0c,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x0c,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x0d,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x0c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x0c,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x0c,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x0d,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x0e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x0e,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x0e,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x0f,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x0e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x0e,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x0e,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x0f,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x10,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x10,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x10,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x11,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x10,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x10,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x10,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x11,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x12,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x12,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x12,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x13,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x12,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x12,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x12,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x13,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x14,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x14,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x14,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x15,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x14,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x14,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x14,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x15,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x16,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x16,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x16,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x17,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x16,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x16,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x16,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x17,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x18,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x18,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x18,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x19,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x18,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x18,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x18,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x19,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x1a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x1a,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x1a,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x1b,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x1a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x1a,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x1a,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x1b,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x1c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x1c,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x1c,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x1d,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x1c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x1c,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x1c,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x1d,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x1e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x1e,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x1e,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x1f,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x1e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x1e,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x1e,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x1f,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x40,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x40,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x40,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x41,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x40,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x40,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x40,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x41,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x42,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x42,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x42,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x43,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x42,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x42,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x42,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x43,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x44,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x44,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x44,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x45,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x44,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x44,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x44,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x45,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x46,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x46,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x46,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x47,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x46,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x46,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x46,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x47,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x48,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x48,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x48,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x49,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x48,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x48,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x48,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x49,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x4a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x4a,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x4b,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x4a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x4a,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x4b,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x4c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x4c,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x4d,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x4c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x4c,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x4d,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x4e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x4e,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x4f,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x4e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x4e,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x4f,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x50,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x50,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x50,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x51,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x50,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x50,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x50,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x51,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x52,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x52,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x52,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x53,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x52,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x52,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x52,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x53,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x54,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x54,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x54,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x55,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x54,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x54,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x54,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x55,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x56,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x56,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x56,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x57,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x56,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x56,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x56,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x57,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x58,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x58,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x58,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x59,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x58,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x58,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x58,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x59,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x5a,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x5a,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x5b,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x5a,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x5a,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x5b,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x5c,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x5c,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x5d,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x5c,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x5c,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x5d,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x5e,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x5e,0x7c,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x5f,0x7c]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x5e,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x5e,0x7c,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x5f,0x7c]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x00,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x00,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x00,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x01,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x02,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x02,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x02,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x03,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x04,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x04,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x04,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x05,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x06,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x06,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x06,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x07,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x08,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x08,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x08,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x09,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x0a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x0a,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x0a,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x0b,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x0c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x0c,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x0c,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x0d,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x0e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x0e,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x0e,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x0f,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x00,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x00,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x00,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x01,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x02,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x02,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x02,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x03,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x04,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x04,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x04,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x05,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x06,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x06,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x06,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x07,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x08,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x08,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x08,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x09,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x0a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x0a,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x0a,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x0b,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x0c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x0c,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x0c,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x0d,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x0e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x0e,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x0e,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x0f,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x10,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x10,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x10,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x11,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x10,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x10,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x10,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x11,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x12,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x12,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x12,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x12,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x12,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x13,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x14,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x14,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x14,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x14,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x14,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x15,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x16,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x16,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x16,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x16,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x16,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x17,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x18,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x18,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x18,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x18,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x18,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x19,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x1a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x1a,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x1a,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x1a,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x1a,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x1b,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x1c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x1c,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x1c,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x1c,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x1c,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x1d,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x12,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x12,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x12,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x12,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x12,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x13,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x14,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x14,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x14,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x14,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x14,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x15,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x16,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x16,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x16,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x16,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x16,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x17,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x18,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x18,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x18,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x18,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x18,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x19,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x1a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x1a,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x1a,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x1a,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x1a,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x1b,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x1c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x1c,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x1c,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x1c,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x1c,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x1d,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x1e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x1e,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x1e,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x1f,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x40,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x40,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x40,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x41,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x42,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x42,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x42,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x43,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x44,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x44,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x44,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x45,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x46,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x46,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x46,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x47,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x48,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x48,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x48,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x49,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x4a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x4a,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x4b,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x4c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x4c,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x4d,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0x4e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0x4e,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0x4f,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, v[1:2], v2
+// W64: encoding: [0x01,0x05,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, v[254:255], v2
+// W64: encoding: [0xfe,0x05,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, s[2:3], v2
+// W64: encoding: [0x02,0x04,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, s[4:5], v2
+// W64: encoding: [0x04,0x04,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, s[100:101], v2
+// W64: encoding: [0x64,0x04,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, vcc, v2
+// W64: encoding: [0x6a,0x04,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, exec, v2
+// W64: encoding: [0x7e,0x04,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x50,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x50,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x50,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc, v[1:2], v255
+// W64: encoding: [0x01,0xff,0x51,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0xc0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0xc1,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0xc2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0xc3,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0xc4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0xc5,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0xc6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0xc7,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0xc8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0xc9,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0xca,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0xcb,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0xcc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0xcd,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x01,0x05,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, v[254:255], v[2:3]
+// W64: encoding: [0xfe,0x05,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, s[2:3], v[2:3]
+// W64: encoding: [0x02,0x04,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, s[4:5], v[2:3]
+// W64: encoding: [0x04,0x04,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, s[100:101], v[2:3]
+// W64: encoding: [0x64,0x04,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, vcc, v[2:3]
+// W64: encoding: [0x6a,0x04,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, exec, v[2:3]
+// W64: encoding: [0x7e,0x04,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, 0, v[2:3]
+// W64: encoding: [0x80,0x04,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, -1, v[2:3]
+// W64: encoding: [0xc1,0x04,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, 0.5, v[2:3]
+// W64: encoding: [0xf0,0x04,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, -4.0, v[2:3]
+// W64: encoding: [0xf7,0x04,0xce,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, 0xaf123456, v[2:3]
+// W64: encoding: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, 0x3f717273, v[2:3]
+// W64: encoding: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc, v[1:2], v[254:255]
+// W64: encoding: [0x01,0xfd,0xcf,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x40,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x40,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x40,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x41,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x42,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x42,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x42,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x43,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x44,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x44,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x44,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x45,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x46,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x46,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x46,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x47,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x48,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x48,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x48,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x49,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x4a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x4a,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x4b,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x4c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x4c,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x4d,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0x4e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0x4e,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0x4f,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, v[1:2], v2
+// W32: encoding: [0x01,0x05,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, v[254:255], v2
+// W32: encoding: [0xfe,0x05,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, s[2:3], v2
+// W32: encoding: [0x02,0x04,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, s[4:5], v2
+// W32: encoding: [0x04,0x04,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, s[100:101], v2
+// W32: encoding: [0x64,0x04,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, vcc, v2
+// W32: encoding: [0x6a,0x04,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, exec, v2
+// W32: encoding: [0x7e,0x04,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x50,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x50,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x50,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f64 vcc_lo, v[1:2], v255
+// W32: encoding: [0x01,0xff,0x51,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0xc0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0xc1,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0xc2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0xc3,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0xc4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0xc5,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0xc6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0xc7,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0xc8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0xc9,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0xca,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0xcb,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0xcc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0xcd,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x01,0x05,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, v[254:255], v[2:3]
+// W32: encoding: [0xfe,0x05,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, s[2:3], v[2:3]
+// W32: encoding: [0x02,0x04,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, s[4:5], v[2:3]
+// W32: encoding: [0x04,0x04,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, s[100:101], v[2:3]
+// W32: encoding: [0x64,0x04,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, vcc, v[2:3]
+// W32: encoding: [0x6a,0x04,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, exec, v[2:3]
+// W32: encoding: [0x7e,0x04,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, 0, v[2:3]
+// W32: encoding: [0x80,0x04,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, -1, v[2:3]
+// W32: encoding: [0xc1,0x04,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, 0.5, v[2:3]
+// W32: encoding: [0xf0,0x04,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, -4.0, v[2:3]
+// W32: encoding: [0xf7,0x04,0xce,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, 0xaf123456, v[2:3]
+// W32: encoding: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, 0x3f717273, v[2:3]
+// W32: encoding: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u64 vcc_lo, v[1:2], v[254:255]
+// W32: encoding: [0x01,0xfd,0xcf,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x52,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x52,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x52,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x52,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x52,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x53,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x54,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x54,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x54,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x54,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x54,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x55,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x56,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x56,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x56,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x56,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x56,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x57,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x58,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x58,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x58,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x58,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x58,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x59,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x5a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x5a,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x5a,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x5a,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x5a,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x5b,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x5c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, 0.5, v2
+// W64: encoding: [0xff,0x04,0x5c,0x7d,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, -4.0, v2
+// W64: encoding: [0xff,0x04,0x5c,0x7d,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x5c,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x5c,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x5d,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x80,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x81,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x82,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x83,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x84,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x85,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x86,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x87,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x88,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x89,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x8a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x8b,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x8c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x8d,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x8e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, 0xaf123456, v2
+// W64: encoding: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, 0x3f717273, v2
+// W64: encoding: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x8f,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x90,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x90,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x90,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x91,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x92,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x92,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x92,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x93,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x94,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x94,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x94,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x95,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x96,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x96,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x96,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x97,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x98,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x98,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x98,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x99,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x9a,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x9a,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x9a,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x9b,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x9c,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x9c,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x9c,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x9d,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0x9e,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0x9e,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0x9e,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0x9f,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0xd0,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0xd0,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0xd0,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0xd1,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0xd2,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0xd2,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0xd2,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0xd3,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0xd4,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0xd4,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0xd4,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0xd5,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0xd6,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0xd6,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0xd6,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0xd7,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0xd8,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0xd8,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0xd8,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0xd9,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0xda,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0xda,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0xda,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0xdb,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0xdc,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0xdc,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0xdc,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0xdd,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, v1, v2
+// W64: encoding: [0x01,0x05,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, v255, v2
+// W64: encoding: [0xff,0x05,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, s1, v2
+// W64: encoding: [0x01,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, s101, v2
+// W64: encoding: [0x65,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, vcc_lo, v2
+// W64: encoding: [0x6a,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, vcc_hi, v2
+// W64: encoding: [0x6b,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, m0, v2
+// W64: encoding: [0x7c,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, exec_lo, v2
+// W64: encoding: [0x7e,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, exec_hi, v2
+// W64: encoding: [0x7f,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, 0, v2
+// W64: encoding: [0x80,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, -1, v2
+// W64: encoding: [0xc1,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, 0.5, v2
+// W64: encoding: [0xf0,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, -4.0, v2
+// W64: encoding: [0xf7,0x04,0xde,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, 0xfe0b, v2
+// W64: encoding: [0xff,0x04,0xde,0x7d,0x0b,0xfe,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, 0x3456, v2
+// W64: encoding: [0xff,0x04,0xde,0x7d,0x56,0x34,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc, v1, v255
+// W64: encoding: [0x01,0xff,0xdf,0x7d]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x52,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x52,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x52,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x52,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x52,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x53,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x54,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x54,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x54,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x54,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x54,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x55,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x56,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x56,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x56,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x56,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x56,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x57,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x58,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x58,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x58,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x58,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x58,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x59,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x5a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x5a,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x5a,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x5a,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x5a,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x5b,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x5c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, 0.5, v2
+// W32: encoding: [0xff,0x04,0x5c,0x7d,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, -4.0, v2
+// W32: encoding: [0xff,0x04,0x5c,0x7d,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x5c,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x5c,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x5d,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x80,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x81,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x82,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x83,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x84,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x85,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x86,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x87,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x88,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x89,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x8a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x8b,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x8c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x8d,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x8e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, 0xaf123456, v2
+// W32: encoding: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, 0x3f717273, v2
+// W32: encoding: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x8f,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x90,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x90,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x90,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x91,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x92,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x92,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x92,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x93,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x94,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x94,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x94,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x95,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x96,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x96,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x96,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x97,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x98,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x98,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x98,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x99,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x9a,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x9a,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x9a,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x9b,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x9c,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x9c,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x9c,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x9d,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0x9e,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0x9e,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0x9e,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0x9f,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0xd0,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0xd0,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0xd0,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0xd1,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0xd2,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0xd2,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0xd2,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0xd3,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0xd4,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0xd4,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0xd4,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0xd5,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0xd6,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0xd6,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0xd6,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0xd7,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0xd8,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0xd8,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0xd8,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0xd9,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0xda,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0xda,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0xda,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0xdb,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0xdc,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0xdc,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0xdc,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0xdd,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, v1, v2
+// W32: encoding: [0x01,0x05,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, v255, v2
+// W32: encoding: [0xff,0x05,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, s1, v2
+// W32: encoding: [0x01,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, s101, v2
+// W32: encoding: [0x65,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, vcc_lo, v2
+// W32: encoding: [0x6a,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, vcc_hi, v2
+// W32: encoding: [0x6b,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, m0, v2
+// W32: encoding: [0x7c,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, exec_lo, v2
+// W32: encoding: [0x7e,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, exec_hi, v2
+// W32: encoding: [0x7f,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, 0, v2
+// W32: encoding: [0x80,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, -1, v2
+// W32: encoding: [0xc1,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, 0.5, v2
+// W32: encoding: [0xf0,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, -4.0, v2
+// W32: encoding: [0xf7,0x04,0xde,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, 0xfe0b, v2
+// W32: encoding: [0xff,0x04,0xde,0x7d,0x0b,0xfe,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, 0x3456, v2
+// W32: encoding: [0xff,0x04,0xde,0x7d,0x56,0x34,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16 vcc_lo, v1, v255
+// W32: encoding: [0x01,0xff,0xdf,0x7d]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s b/llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
new file mode 100644
index 0000000000000..c2940be07c824
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vopc_e64.s
@@ -0,0 +1,21692 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W64-ERR --implicit-check-not=error: %s
+
+//===----------------------------------------------------------------------===//
+// ENC_VOPC, VOP3 variant.
+//===----------------------------------------------------------------------===//
+
+v_cmp_f_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x00,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x00,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x01,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x01,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x02,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x02,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x03,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x03,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x04,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x04,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x05,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x05,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x06,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x06,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x07,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x07,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x08,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x08,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x09,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x09,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x0a,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x0a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x0b,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x0b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x0c,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x0c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x0d,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x0d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x0e,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x0e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0x0f,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0x0f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x20,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x20,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x21,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x21,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x22,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x22,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x23,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x23,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x24,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x24,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x25,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x25,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x26,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x26,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x27,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x27,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x28,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x28,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x29,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x29,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2a,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x2a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2b,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x2b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2c,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x2c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2d,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x2d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2e,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x2e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// W64: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// W64: encoding: [0x0a,0x80,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, -v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, -v[1:2], -v[2:3]
+// W32: encoding: [0x0a,0x00,0x2f,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f64_e64 s10, v[1:2], v[2:3] clamp
+// W32: encoding: [0x0a,0x80,0x2f,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x80,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x80,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x81,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x81,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x82,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x82,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x83,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x83,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x84,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x84,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x85,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x85,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x86,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x86,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x87,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x87,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x88,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0x88,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x89,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x89,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x8a,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x8a,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x8b,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x8b,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x8c,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x8c,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x8d,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x8d,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0x8e,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0x8e,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0x8f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0x8f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0x8f,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0x8f,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[12:13], v[1:2], v2
+// W64: encoding: [0x0c,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[100:101], v[1:2], v2
+// W64: encoding: [0x64,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 vcc, v[1:2], v2
+// W64: encoding: [0x6a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[254:255], v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], s[2:3], v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], s[4:5], v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], s[100:101], v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], vcc, v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], exec, v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v255
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s101
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_lo
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_hi
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], m0
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], exec_lo
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], exec_hi
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s[10:11], -v[1:2], v2
+// W64: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[12:13], v[1:2], v[2:3]
+// W64: encoding: [0x0c,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[100:101], v[1:2], v[2:3]
+// W64: encoding: [0x64,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 vcc, v[1:2], v[2:3]
+// W64: encoding: [0x6a,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[254:255], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0xfe,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], s[2:3], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x02,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], s[4:5], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x04,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], s[100:101], v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x64,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], vcc, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], exec, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], 0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], -1, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], 0.5, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], -4.0, v[2:3]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], v[254:255]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xfd,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[4:5]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x09,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[6:7]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x0d,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[100:101]
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xc9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], vcc
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], exec
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], 0
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], -1
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], 0.5
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], -4.0
+// W64: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xa0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xa0,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xa1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xa1,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xa2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xa2,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xa3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xa3,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xa4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xa4,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xa5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xa5,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xa6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xa6,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xa7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xa7,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s12, v[1:2], v2
+// W32: encoding: [0x0c,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s100, v[1:2], v2
+// W32: encoding: [0x64,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 vcc_lo, v[1:2], v2
+// W32: encoding: [0x6a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[254:255], v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, s[2:3], v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, s[4:5], v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, s[100:101], v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, vcc, v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, exec, v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], v255
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], s2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], s101
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], vcc_lo
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], vcc_hi
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], m0
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], exec_lo
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], exec_hi
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f64_e64 s10, -v[1:2], v2
+// W32: encoding: [0x0a,0x00,0xa8,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xe0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xe0,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xe1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xe1,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xe2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xe2,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xe3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xe3,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xe4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xe4,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xe5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xe5,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xe6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xe6,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s12, v[1:2], v[2:3]
+// W32: encoding: [0x0c,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s100, v[1:2], v[2:3]
+// W32: encoding: [0x64,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 vcc_lo, v[1:2], v[2:3]
+// W32: encoding: [0x6a,0x00,0xe7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[254:255], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0xfe,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, s[2:3], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x02,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, s[4:5], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x04,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, s[100:101], v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x64,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, vcc, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, exec, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, 0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, -1, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, 0.5, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, -4.0, v[2:3]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], v[254:255]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xfd,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], s[4:5]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x09,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], s[6:7]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x0d,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], s[100:101]
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xc9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], vcc
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], exec
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], 0
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], -1
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], 0.5
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u64_e64 s10, v[1:2], -4.0
+// W32: encoding: [0x0a,0x00,0xe7,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[12:13], v1, v2
+// W64: encoding: [0x0c,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[100:101], v1, v2
+// W64: encoding: [0x64,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 vcc, v1, v2
+// W64: encoding: [0x6a,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v255, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0xff,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], s1, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], s101, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x65,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], vcc_lo, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x6a,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], vcc_hi, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x6b,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], m0, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x7c,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], exec_lo, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x7e,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], exec_hi, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x7f,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], 0, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x80,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], -1, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0xc1,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], 0.5, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0xf0,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], -4.0, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0xf7,0x04,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, v255
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xff,0x03,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, s2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, s101
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xcb,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, vcc_lo
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xd5,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, vcc_hi
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xd7,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, m0
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xf9,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, exec_lo
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xfd,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, exec_hi
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xff,0x00,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, 0
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x01,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, -1
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x83,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, 0.5
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xe1,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, -4.0
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xef,0x01,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], -v1, v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x20]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, -v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x40]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], -v1, -v2
+// W64: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x60]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s[10:11], v1, v2 clamp
+// W64: encoding: [0x0a,0x80,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xa9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xa9,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xaa,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xaa,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xab,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xab,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xac,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xac,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xad,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xad,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xae,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xae,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc0,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc0,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc1,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc1,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc2,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc2,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc3,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc3,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc4,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc4,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc5,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc5,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc6,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc6,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc7,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc7,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xc8,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xc8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xc9,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xc9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xca,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xca,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xcb,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xcb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xcc,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xcc,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xcd,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xcd,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xce,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xce,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xcf,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xcf,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xe8,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xe8,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xe9,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xe9,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xea,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xea,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xeb,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xeb,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xec,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xec,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xed,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xed,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xee,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xee,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s12, v1, v2
+// W32: encoding: [0x0c,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s100, v1, v2
+// W32: encoding: [0x64,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 vcc_lo, v1, v2
+// W32: encoding: [0x6a,0x00,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v255, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0xff,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, s1, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, s101, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x65,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, vcc_lo, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x6a,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, vcc_hi, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x6b,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, m0, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x7c,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, exec_lo, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x7e,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, exec_hi, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x7f,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, 0, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x80,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, -1, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0xc1,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, 0.5, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0xf0,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, -4.0, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0xf7,0x04,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, v255
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xff,0x03,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, s2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, s101
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xcb,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, vcc_lo
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xd5,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, vcc_hi
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xd7,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, m0
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xf9,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, exec_lo
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xfd,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, exec_hi
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xff,0x00,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, 0
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x01,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, -1
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x83,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, 0.5
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xe1,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, -4.0
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0xef,0x01,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, -v1, v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x20]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, -v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x40]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, -v1, -v2
+// W32: encoding: [0x0a,0x00,0xef,0xd4,0x01,0x05,0x02,0x60]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_e64 s10, v1, v2 clamp
+// W32: encoding: [0x0a,0x80,0xef,0xd4,0x01,0x05,0x02,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s b/llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s
new file mode 100644
index 0000000000000..75f130968d447
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vopc_sdwa.s
@@ -0,0 +1,13816 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GFX10-ERR,W64-ERR --implicit-check-not=error: %s
+
+//===----------------------------------------------------------------------===//
+// ENC_VOPC, SDWA variant.
+//===----------------------------------------------------------------------===//
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x01,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x01,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x03,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x03,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x05,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x05,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x07,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x07,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x09,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x09,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x0b,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x0b,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x0d,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x0d,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x0f,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x0f,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x11,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x11,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x13,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x13,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x15,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x15,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x17,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x17,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x19,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x19,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x1b,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x1b,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x1d,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x1d,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x1f,0x7c,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x1f,0x7c,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f32_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1e,0x7c,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x01,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x03,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x05,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x07,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x09,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x0b,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x0d,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x0f,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x01,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x00,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x03,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x02,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x05,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x04,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x07,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x06,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x09,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x08,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x0b,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0a,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x0d,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0c,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x0f,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_i32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x0e,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x11,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x11,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x10,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x13,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x15,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x17,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x19,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x1b,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x1d,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x13,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x12,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x15,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x14,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x17,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x16,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x19,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x18,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x1b,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1a,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x1d,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_i16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x1c,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_class_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x1f,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_class_f16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x53,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x55,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x57,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x59,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x5b,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x5d,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x81,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x83,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x85,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x87,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x89,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ne_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x8b,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x8d,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_t_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x8f,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x0e,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x0e]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_f_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x91,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x93,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_eq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x95,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_le_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x97,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_gt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x99,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_lg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x9b,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x9d,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_o_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0x9f,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_u_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0xd1,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0xd3,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0xd5,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_ngt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0xd7,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nle_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0xd9,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_neq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0xdb,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_nlt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0xdd,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x88,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0xe4,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x00,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
+
+v_cmp_tru_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0xff,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x65,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x6a,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x6b,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x7c,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x7e,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x7f,0x86,0x86,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0xfe,0xdf,0x7d,0x01,0x86,0x06,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x00,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x01,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x02,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x03,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x04,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x05,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x16,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x26,0x06]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x00]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x01]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x02]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x03]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x04]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x05]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x16]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W64: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x26]
+// W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x53,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x55,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x57,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x59,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x5b,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x5d,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u16_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x81,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x83,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x85,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x87,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x89,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x8b,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ne_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x8d,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x8f,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x0e,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_t_u32_sdwa s6, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x0e]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x91,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_f_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x93,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lt_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x95,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_eq_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x97,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_le_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x99,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_gt_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x9b,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_lg_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x9d,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ge_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0x9f,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_o_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0xd1,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_u_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd0,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0xd3,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nge_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd2,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0xd5,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlg_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd4,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0xd7,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_ngt_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd6,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0xd9,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nle_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xd8,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0xdb,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_neq_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xda,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0xdd,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_nlt_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xdc,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s8, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x88,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s100, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0xe4,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x00,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0xff,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, s1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, s101, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x65,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x6a,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x6b,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, m0, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x7c,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x7e,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x7f,0x86,0x86,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0xfe,0xdf,0x7d,0x01,0x86,0x06,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x00,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x01,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x02,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x03,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x04,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x05,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x16,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x26,0x06]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x00]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x01]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x02]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x03]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x04]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x05]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x16]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
+
+v_cmp_tru_f16_sdwa s6, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// W32: encoding: [0xf9,0x04,0xde,0x7d,0x01,0x86,0x06,0x26]
+// W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s b/llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s
new file mode 100644
index 0000000000000..54baa79d08ff5
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_vopcx.s
@@ -0,0 +1,15975 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
+
+//===----------------------------------------------------------------------===//
+// ENC_VOPC - v_cmpx_* opcodes.
+//===----------------------------------------------------------------------===//
+
+v_cmpx_f_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x20,0x7c]
+
+v_cmpx_f_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x20,0x7c]
+
+v_cmpx_f_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x20,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x20,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x21,0x7c]
+
+v_cmpx_f_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x10,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x22,0x7c]
+
+v_cmpx_lt_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x22,0x7c]
+
+v_cmpx_lt_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x22,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x22,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x23,0x7c]
+
+v_cmpx_lt_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x11,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x24,0x7c]
+
+v_cmpx_eq_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x24,0x7c]
+
+v_cmpx_eq_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x24,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x24,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x25,0x7c]
+
+v_cmpx_eq_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x12,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x26,0x7c]
+
+v_cmpx_le_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x26,0x7c]
+
+v_cmpx_le_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x26,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x26,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x27,0x7c]
+
+v_cmpx_le_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x13,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x28,0x7c]
+
+v_cmpx_gt_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x28,0x7c]
+
+v_cmpx_gt_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x28,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x28,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x29,0x7c]
+
+v_cmpx_gt_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x14,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x2a,0x7c]
+
+v_cmpx_lg_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x2a,0x7c]
+
+v_cmpx_lg_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x2a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x2a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lg_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x2b,0x7c]
+
+v_cmpx_lg_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_lg_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_lg_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lg_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lg_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lg_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_lg_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x15,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x2c,0x7c]
+
+v_cmpx_ge_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x2c,0x7c]
+
+v_cmpx_ge_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x2c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x2c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x2d,0x7c]
+
+v_cmpx_ge_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x16,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x2e,0x7c]
+
+v_cmpx_o_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x2e,0x7c]
+
+v_cmpx_o_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x2e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x2e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_o_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x2f,0x7c]
+
+v_cmpx_o_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_o_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_o_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_o_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_o_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_o_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_o_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x17,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x30,0x7c]
+
+v_cmpx_u_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x30,0x7c]
+
+v_cmpx_u_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x30,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x30,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_u_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x31,0x7c]
+
+v_cmpx_u_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_u_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_u_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_u_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_u_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_u_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_u_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x18,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x32,0x7c]
+
+v_cmpx_nge_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x32,0x7c]
+
+v_cmpx_nge_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x32,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x32,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nge_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x33,0x7c]
+
+v_cmpx_nge_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_nge_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_nge_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nge_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nge_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nge_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_nge_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x19,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x34,0x7c]
+
+v_cmpx_nlg_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x34,0x7c]
+
+v_cmpx_nlg_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x34,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x34,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlg_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x35,0x7c]
+
+v_cmpx_nlg_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlg_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1a,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x36,0x7c]
+
+v_cmpx_ngt_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x36,0x7c]
+
+v_cmpx_ngt_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x36,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x36,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ngt_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x37,0x7c]
+
+v_cmpx_ngt_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ngt_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1b,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x38,0x7c]
+
+v_cmpx_nle_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x38,0x7c]
+
+v_cmpx_nle_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x38,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x38,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nle_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x39,0x7c]
+
+v_cmpx_nle_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_nle_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_nle_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nle_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nle_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nle_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_nle_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1c,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x3a,0x7c]
+
+v_cmpx_neq_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x3a,0x7c]
+
+v_cmpx_neq_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x3a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x3a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_neq_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x3b,0x7c]
+
+v_cmpx_neq_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_neq_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_neq_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_neq_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_neq_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_neq_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_neq_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1d,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x3c,0x7c]
+
+v_cmpx_nlt_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x3c,0x7c]
+
+v_cmpx_nlt_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x3c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x3c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlt_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x3d,0x7c]
+
+v_cmpx_nlt_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlt_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1e,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x3e,0x7c]
+
+v_cmpx_tru_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x3e,0x7c]
+
+v_cmpx_tru_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x3e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_tru_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x3e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_tru_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x3f,0x7c]
+
+v_cmpx_tru_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_tru_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_tru_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_tru_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_tru_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_tru_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_tru_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f32_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f32_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0x1f,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_f_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_f_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_f_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_f_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_f_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_f_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x21,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_f_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_f_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x23,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_lt_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_lt_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x25,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_eq_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_eq_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_le_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_le_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_le_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_le_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_le_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_le_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x27,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_le_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_le_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x29,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_gt_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_gt_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x2b,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_lg_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_lg_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_lg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_lg_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_lg_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x2d,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_ge_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_ge_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_o_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_o_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_o_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_o_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_o_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_o_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_o_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x2f,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_o_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_o_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_o_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_o_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_o_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_u_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_u_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_u_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_u_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_u_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_u_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_u_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x31,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_u_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_u_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_u_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_u_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_u_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x30,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x33,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nge_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nge_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nge_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nge_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nge_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x35,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nlg_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nlg_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nlg_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nlg_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nlg_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x37,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_ngt_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_ngt_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_ngt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_ngt_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_ngt_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x39,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nle_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nle_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nle_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nle_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nle_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x3b,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_neq_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_neq_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_neq_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_neq_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_neq_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x3d,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nlt_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nlt_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nlt_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nlt_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nlt_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x65,0x00,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x6a,0x00,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x6b,0x00,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x7c,0x00,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x7e,0x00,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x7f,0x00,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x3f,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_tru_f32_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_tru_f32_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_tru_f32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_tru_f32_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_tru_f32_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3e,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_f_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x60,0x7c]
+
+v_cmpx_f_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x60,0x7c]
+
+v_cmpx_f_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x60,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x60,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x61,0x7c]
+
+v_cmpx_f_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_f_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x30,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x62,0x7c]
+
+v_cmpx_lt_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x62,0x7c]
+
+v_cmpx_lt_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x62,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x62,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x63,0x7c]
+
+v_cmpx_lt_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x31,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x64,0x7c]
+
+v_cmpx_eq_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x64,0x7c]
+
+v_cmpx_eq_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x64,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x64,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x65,0x7c]
+
+v_cmpx_eq_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_eq_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x32,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x66,0x7c]
+
+v_cmpx_le_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x66,0x7c]
+
+v_cmpx_le_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x66,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x66,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x67,0x7c]
+
+v_cmpx_le_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_le_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x33,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x68,0x7c]
+
+v_cmpx_gt_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x68,0x7c]
+
+v_cmpx_gt_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x68,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x68,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x69,0x7c]
+
+v_cmpx_gt_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_gt_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x34,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x6a,0x7c]
+
+v_cmpx_lg_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x6a,0x7c]
+
+v_cmpx_lg_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lg_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x6b,0x7c]
+
+v_cmpx_lg_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_lg_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x35,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x6c,0x7c]
+
+v_cmpx_ge_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x6c,0x7c]
+
+v_cmpx_ge_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x6d,0x7c]
+
+v_cmpx_ge_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_ge_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x36,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x6e,0x7c]
+
+v_cmpx_o_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x6e,0x7c]
+
+v_cmpx_o_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_o_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x6f,0x7c]
+
+v_cmpx_o_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_o_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x37,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x70,0x7c]
+
+v_cmpx_u_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x70,0x7c]
+
+v_cmpx_u_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x70,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x70,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_u_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x71,0x7c]
+
+v_cmpx_u_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_u_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x38,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x72,0x7c]
+
+v_cmpx_nge_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x72,0x7c]
+
+v_cmpx_nge_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x72,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x72,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nge_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x73,0x7c]
+
+v_cmpx_nge_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_nge_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x39,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x74,0x7c]
+
+v_cmpx_nlg_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x74,0x7c]
+
+v_cmpx_nlg_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x74,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x74,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlg_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x75,0x7c]
+
+v_cmpx_nlg_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3a,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x76,0x7c]
+
+v_cmpx_ngt_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x76,0x7c]
+
+v_cmpx_ngt_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x76,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x76,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ngt_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x77,0x7c]
+
+v_cmpx_ngt_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3b,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x78,0x7c]
+
+v_cmpx_nle_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x78,0x7c]
+
+v_cmpx_nle_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x78,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x78,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nle_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x79,0x7c]
+
+v_cmpx_nle_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_nle_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3c,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x7a,0x7c]
+
+v_cmpx_neq_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x7a,0x7c]
+
+v_cmpx_neq_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x7a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x7a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_neq_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x7b,0x7c]
+
+v_cmpx_neq_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_neq_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3d,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x7c,0x7c]
+
+v_cmpx_nlt_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x7c,0x7c]
+
+v_cmpx_nlt_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x7c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x7c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlt_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x7d,0x7c]
+
+v_cmpx_nlt_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3e,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x7e,0x7c]
+
+v_cmpx_tru_f64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x7e,0x7c]
+
+v_cmpx_tru_f64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x7e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_tru_f64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x7e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_tru_f64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x7f,0x7c]
+
+v_cmpx_tru_f64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 exec, v[1:2]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x7e,0x02,0x02,0x00]
+
+v_cmpx_tru_f64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f64_e64 -v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f64_e64 v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f64_e64 -v[1:2], -v[2:3]
+// GFX10: encoding: [0x00,0x00,0x3f,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_i32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x20,0x7d]
+
+v_cmpx_f_i32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x20,0x7d]
+
+v_cmpx_f_i32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 0, v2
+// GFX10: encoding: [0x80,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x20,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_i32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x20,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_i32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x21,0x7d]
+
+v_cmpx_f_i32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_i32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_i32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_i32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_i32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_i32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_i32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_i32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x90,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_i32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x22,0x7d]
+
+v_cmpx_lt_i32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x22,0x7d]
+
+v_cmpx_lt_i32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 0, v2
+// GFX10: encoding: [0x80,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x22,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x22,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_i32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x23,0x7d]
+
+v_cmpx_lt_i32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_i32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_i32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_i32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_i32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_i32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_i32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_i32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x91,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_i32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x24,0x7d]
+
+v_cmpx_eq_i32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x24,0x7d]
+
+v_cmpx_eq_i32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 0, v2
+// GFX10: encoding: [0x80,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x24,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x24,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_i32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x25,0x7d]
+
+v_cmpx_eq_i32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_i32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_i32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_i32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_i32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_i32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_i32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_i32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x92,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_i32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x26,0x7d]
+
+v_cmpx_le_i32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x26,0x7d]
+
+v_cmpx_le_i32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 0, v2
+// GFX10: encoding: [0x80,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x26,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x26,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_i32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x27,0x7d]
+
+v_cmpx_le_i32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_i32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_i32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_i32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_i32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_i32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_i32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_i32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x93,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_i32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x28,0x7d]
+
+v_cmpx_gt_i32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x28,0x7d]
+
+v_cmpx_gt_i32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 0, v2
+// GFX10: encoding: [0x80,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x28,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x28,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_i32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x29,0x7d]
+
+v_cmpx_gt_i32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_i32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_i32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_i32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_i32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_i32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_i32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_i32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x94,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_i32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x2a,0x7d]
+
+v_cmpx_ne_i32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x2a,0x7d]
+
+v_cmpx_ne_i32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 0, v2
+// GFX10: encoding: [0x80,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x2a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x2a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_i32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x2b,0x7d]
+
+v_cmpx_ne_i32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_i32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_i32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_i32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_i32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_i32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_i32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_i32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x95,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_i32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x2c,0x7d]
+
+v_cmpx_ge_i32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x2c,0x7d]
+
+v_cmpx_ge_i32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 0, v2
+// GFX10: encoding: [0x80,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x2c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x2c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_i32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x2d,0x7d]
+
+v_cmpx_ge_i32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_i32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_i32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_i32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_i32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_i32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_i32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_i32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x96,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_i32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x2e,0x7d]
+
+v_cmpx_t_i32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x2e,0x7d]
+
+v_cmpx_t_i32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 0, v2
+// GFX10: encoding: [0x80,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x2e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_i32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x2e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_i32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x2f,0x7d]
+
+v_cmpx_t_i32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_i32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_i32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_i32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_i32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_i32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_i32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_i32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x97,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f32 v1, v2
+// GFX10: encoding: [0x01,0x05,0x30,0x7d]
+
+v_cmpx_class_f32 v255, v2
+// GFX10: encoding: [0xff,0x05,0x30,0x7d]
+
+v_cmpx_class_f32 s1, v2
+// GFX10: encoding: [0x01,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 s101, v2
+// GFX10: encoding: [0x65,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 0, v2
+// GFX10: encoding: [0x80,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x30,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x30,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_class_f32 v1, v255
+// GFX10: encoding: [0x01,0xff,0x31,0x7d]
+
+v_cmpx_class_f32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_class_f32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f32_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x98,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_i16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x32,0x7d]
+
+v_cmpx_lt_i16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x32,0x7d]
+
+v_cmpx_lt_i16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x32,0x7d]
+
+v_cmpx_lt_i16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x32,0x7d]
+
+v_cmpx_lt_i16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x32,0x7d]
+
+v_cmpx_lt_i16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x32,0x7d]
+
+v_cmpx_lt_i16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x32,0x7d]
+
+v_cmpx_lt_i16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x32,0x7d]
+
+v_cmpx_lt_i16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x32,0x7d]
+
+v_cmpx_lt_i16 0, v2
+// GFX10: encoding: [0x80,0x04,0x32,0x7d]
+
+v_cmpx_lt_i16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x32,0x7d]
+
+v_cmpx_lt_i16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x32,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_i16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x32,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_lt_i16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x32,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_i16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x32,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_i16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x33,0x7d]
+
+v_cmpx_lt_i16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_i16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_lt_i16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_i16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_i16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_i16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_i16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_i16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_i16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_i16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x99,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_i16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x34,0x7d]
+
+v_cmpx_eq_i16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x34,0x7d]
+
+v_cmpx_eq_i16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x34,0x7d]
+
+v_cmpx_eq_i16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x34,0x7d]
+
+v_cmpx_eq_i16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x34,0x7d]
+
+v_cmpx_eq_i16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x34,0x7d]
+
+v_cmpx_eq_i16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x34,0x7d]
+
+v_cmpx_eq_i16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x34,0x7d]
+
+v_cmpx_eq_i16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x34,0x7d]
+
+v_cmpx_eq_i16 0, v2
+// GFX10: encoding: [0x80,0x04,0x34,0x7d]
+
+v_cmpx_eq_i16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x34,0x7d]
+
+v_cmpx_eq_i16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x34,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_i16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x34,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_i16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x34,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_i16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x34,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_eq_i16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x35,0x7d]
+
+v_cmpx_eq_i16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_i16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_i16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_i16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_i16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_i16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_i16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_i16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_i16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_i16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x9a,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_i16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x36,0x7d]
+
+v_cmpx_le_i16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x36,0x7d]
+
+v_cmpx_le_i16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x36,0x7d]
+
+v_cmpx_le_i16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x36,0x7d]
+
+v_cmpx_le_i16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x36,0x7d]
+
+v_cmpx_le_i16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x36,0x7d]
+
+v_cmpx_le_i16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x36,0x7d]
+
+v_cmpx_le_i16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x36,0x7d]
+
+v_cmpx_le_i16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x36,0x7d]
+
+v_cmpx_le_i16 0, v2
+// GFX10: encoding: [0x80,0x04,0x36,0x7d]
+
+v_cmpx_le_i16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x36,0x7d]
+
+v_cmpx_le_i16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x36,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_i16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x36,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_i16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x36,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_i16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x36,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_le_i16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x37,0x7d]
+
+v_cmpx_le_i16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_i16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_i16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_i16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_i16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_i16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_i16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_i16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_i16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_i16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x9b,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_i16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x38,0x7d]
+
+v_cmpx_gt_i16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x38,0x7d]
+
+v_cmpx_gt_i16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x38,0x7d]
+
+v_cmpx_gt_i16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x38,0x7d]
+
+v_cmpx_gt_i16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x38,0x7d]
+
+v_cmpx_gt_i16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x38,0x7d]
+
+v_cmpx_gt_i16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x38,0x7d]
+
+v_cmpx_gt_i16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x38,0x7d]
+
+v_cmpx_gt_i16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x38,0x7d]
+
+v_cmpx_gt_i16 0, v2
+// GFX10: encoding: [0x80,0x04,0x38,0x7d]
+
+v_cmpx_gt_i16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x38,0x7d]
+
+v_cmpx_gt_i16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x38,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_i16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x38,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_i16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x38,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_i16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x38,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_gt_i16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x39,0x7d]
+
+v_cmpx_gt_i16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_i16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_i16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_i16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_i16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_i16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_i16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_i16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_i16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_i16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x9c,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_i16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x3a,0x7d]
+
+v_cmpx_ne_i16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x3a,0x7d]
+
+v_cmpx_ne_i16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x3a,0x7d]
+
+v_cmpx_ne_i16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x3a,0x7d]
+
+v_cmpx_ne_i16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x3a,0x7d]
+
+v_cmpx_ne_i16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x3a,0x7d]
+
+v_cmpx_ne_i16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x3a,0x7d]
+
+v_cmpx_ne_i16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x3a,0x7d]
+
+v_cmpx_ne_i16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x3a,0x7d]
+
+v_cmpx_ne_i16 0, v2
+// GFX10: encoding: [0x80,0x04,0x3a,0x7d]
+
+v_cmpx_ne_i16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x3a,0x7d]
+
+v_cmpx_ne_i16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x3a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_i16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x3a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_i16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x3a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_i16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x3a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ne_i16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x3b,0x7d]
+
+v_cmpx_ne_i16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_i16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_i16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_i16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_i16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_i16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_i16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_i16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_i16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_i16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x9d,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_i16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x3c,0x7d]
+
+v_cmpx_ge_i16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x3c,0x7d]
+
+v_cmpx_ge_i16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x3c,0x7d]
+
+v_cmpx_ge_i16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x3c,0x7d]
+
+v_cmpx_ge_i16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x3c,0x7d]
+
+v_cmpx_ge_i16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x3c,0x7d]
+
+v_cmpx_ge_i16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x3c,0x7d]
+
+v_cmpx_ge_i16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x3c,0x7d]
+
+v_cmpx_ge_i16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x3c,0x7d]
+
+v_cmpx_ge_i16 0, v2
+// GFX10: encoding: [0x80,0x04,0x3c,0x7d]
+
+v_cmpx_ge_i16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x3c,0x7d]
+
+v_cmpx_ge_i16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x3c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_i16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x3c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_i16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x3c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_i16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x3c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ge_i16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x3d,0x7d]
+
+v_cmpx_ge_i16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_i16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_i16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_i16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_i16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_i16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_i16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_i16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_i16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_i16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x9e,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_class_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x3e,0x7d]
+
+v_cmpx_class_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x3e,0x7d]
+
+v_cmpx_class_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x3e,0x7d]
+
+v_cmpx_class_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x3e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_class_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x3e,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_class_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x3f,0x7d]
+
+v_cmpx_class_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_class_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0x9f,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_i64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x60,0x7d]
+
+v_cmpx_f_i64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x60,0x7d]
+
+v_cmpx_f_i64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x60,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_i64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x60,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_i64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x61,0x7d]
+
+v_cmpx_f_i64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_i64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xb0,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_i64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x62,0x7d]
+
+v_cmpx_lt_i64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x62,0x7d]
+
+v_cmpx_lt_i64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x62,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x62,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_i64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x63,0x7d]
+
+v_cmpx_lt_i64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_i64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xb1,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_i64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x64,0x7d]
+
+v_cmpx_eq_i64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x64,0x7d]
+
+v_cmpx_eq_i64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x64,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x64,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_i64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x65,0x7d]
+
+v_cmpx_eq_i64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_i64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xb2,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_i64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x66,0x7d]
+
+v_cmpx_le_i64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x66,0x7d]
+
+v_cmpx_le_i64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x66,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x66,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_i64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x67,0x7d]
+
+v_cmpx_le_i64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_i64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xb3,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_i64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x68,0x7d]
+
+v_cmpx_gt_i64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x68,0x7d]
+
+v_cmpx_gt_i64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x68,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x68,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_i64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x69,0x7d]
+
+v_cmpx_gt_i64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_i64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xb4,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_i64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_i64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x6b,0x7d]
+
+v_cmpx_ne_i64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_i64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xb5,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_i64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_i64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x6d,0x7d]
+
+v_cmpx_ge_i64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_i64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xb6,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_i64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0x6e,0x7d]
+
+v_cmpx_t_i64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0x6e,0x7d]
+
+v_cmpx_t_i64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_i64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0x6e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_i64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0x6f,0x7d]
+
+v_cmpx_t_i64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_i64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xb7,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f64 v[1:2], v2
+// GFX10: encoding: [0x01,0x05,0x70,0x7d]
+
+v_cmpx_class_f64 v[254:255], v2
+// GFX10: encoding: [0xfe,0x05,0x70,0x7d]
+
+v_cmpx_class_f64 s[2:3], v2
+// GFX10: encoding: [0x02,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 s[4:5], v2
+// GFX10: encoding: [0x04,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 s[100:101], v2
+// GFX10: encoding: [0x64,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, v2
+// GFX10: encoding: [0x6a,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 exec, v2
+// GFX10: encoding: [0x7e,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 0, v2
+// GFX10: encoding: [0x80,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0x70,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f64 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0x70,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_class_f64 v[1:2], v255
+// GFX10: encoding: [0x01,0xff,0x71,0x7d]
+
+v_cmpx_class_f64_e64 v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 v[254:255], v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[2:3], v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[4:5], v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 vcc, v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], v255
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], s2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], s101
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], vcc_lo
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], vcc_hi
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], m0
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], exec_lo
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], exec_hi
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f64_e64 -v[1:2], v2
+// GFX10: encoding: [0x00,0x00,0xb8,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_u16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x72,0x7d]
+
+v_cmpx_lt_u16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x72,0x7d]
+
+v_cmpx_lt_u16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 0, v2
+// GFX10: encoding: [0x80,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x72,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_u16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x72,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_lt_u16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x72,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_u16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x72,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_u16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x73,0x7d]
+
+v_cmpx_lt_u16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_u16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_lt_u16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_u16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_u16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_u16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_u16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_u16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_u16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_u16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xb9,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_u16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x74,0x7d]
+
+v_cmpx_eq_u16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x74,0x7d]
+
+v_cmpx_eq_u16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 0, v2
+// GFX10: encoding: [0x80,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x74,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_u16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x74,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_u16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x74,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_u16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x74,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_eq_u16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x75,0x7d]
+
+v_cmpx_eq_u16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_u16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_u16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_u16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_u16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_u16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_u16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_u16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_u16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_u16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xba,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_u16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x76,0x7d]
+
+v_cmpx_le_u16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x76,0x7d]
+
+v_cmpx_le_u16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 0, v2
+// GFX10: encoding: [0x80,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x76,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_u16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x76,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_u16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x76,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_u16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x76,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_le_u16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x77,0x7d]
+
+v_cmpx_le_u16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_u16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_u16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_u16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_u16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_u16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_u16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_u16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_u16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_u16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xbb,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_u16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x78,0x7d]
+
+v_cmpx_gt_u16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x78,0x7d]
+
+v_cmpx_gt_u16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 0, v2
+// GFX10: encoding: [0x80,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x78,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_u16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x78,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_u16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x78,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_u16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x78,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_gt_u16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x79,0x7d]
+
+v_cmpx_gt_u16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_u16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_u16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_u16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_u16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_u16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_u16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_u16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_u16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_u16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xbc,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_u16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x7a,0x7d]
+
+v_cmpx_ne_u16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x7a,0x7d]
+
+v_cmpx_ne_u16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 0, v2
+// GFX10: encoding: [0x80,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x7a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_u16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x7a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_u16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x7a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_u16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x7a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ne_u16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x7b,0x7d]
+
+v_cmpx_ne_u16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_u16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_u16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_u16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_u16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_u16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_u16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_u16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_u16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_u16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xbd,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_u16 v1, v2
+// GFX10: encoding: [0x01,0x05,0x7c,0x7d]
+
+v_cmpx_ge_u16 v255, v2
+// GFX10: encoding: [0xff,0x05,0x7c,0x7d]
+
+v_cmpx_ge_u16 s1, v2
+// GFX10: encoding: [0x01,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 s101, v2
+// GFX10: encoding: [0x65,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 0, v2
+// GFX10: encoding: [0x80,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 0.5, v2
+// GFX10: encoding: [0xff,0x04,0x7c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_u16 -4.0, v2
+// GFX10: encoding: [0xff,0x04,0x7c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_u16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0x7c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_u16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0x7c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ge_u16 v1, v255
+// GFX10: encoding: [0x01,0xff,0x7d,0x7d]
+
+v_cmpx_ge_u16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_u16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_u16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_u16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_u16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_u16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_u16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_u16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_u16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_u16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xbe,0xd4,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+
+v_cmpx_f_u32 v1, v2
+// GFX10: encoding: [0x01,0x05,0xa0,0x7d]
+
+v_cmpx_f_u32 v255, v2
+// GFX10: encoding: [0xff,0x05,0xa0,0x7d]
+
+v_cmpx_f_u32 s1, v2
+// GFX10: encoding: [0x01,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 s101, v2
+// GFX10: encoding: [0x65,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 0, v2
+// GFX10: encoding: [0x80,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0xa0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_u32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0xa0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_u32 v1, v255
+// GFX10: encoding: [0x01,0xff,0xa1,0x7d]
+
+v_cmpx_f_u32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_u32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_u32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_u32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_u32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_u32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_u32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_u32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd0,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_u32 v1, v2
+// GFX10: encoding: [0x01,0x05,0xa2,0x7d]
+
+v_cmpx_lt_u32 v255, v2
+// GFX10: encoding: [0xff,0x05,0xa2,0x7d]
+
+v_cmpx_lt_u32 s1, v2
+// GFX10: encoding: [0x01,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 s101, v2
+// GFX10: encoding: [0x65,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 0, v2
+// GFX10: encoding: [0x80,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0xa2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0xa2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_u32 v1, v255
+// GFX10: encoding: [0x01,0xff,0xa3,0x7d]
+
+v_cmpx_lt_u32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_u32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_u32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_u32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_u32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_u32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_u32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_u32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd1,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_u32 v1, v2
+// GFX10: encoding: [0x01,0x05,0xa4,0x7d]
+
+v_cmpx_eq_u32 v255, v2
+// GFX10: encoding: [0xff,0x05,0xa4,0x7d]
+
+v_cmpx_eq_u32 s1, v2
+// GFX10: encoding: [0x01,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 s101, v2
+// GFX10: encoding: [0x65,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 0, v2
+// GFX10: encoding: [0x80,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0xa4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0xa4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_u32 v1, v255
+// GFX10: encoding: [0x01,0xff,0xa5,0x7d]
+
+v_cmpx_eq_u32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_u32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_u32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_u32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_u32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_u32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_u32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_u32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd2,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_u32 v1, v2
+// GFX10: encoding: [0x01,0x05,0xa6,0x7d]
+
+v_cmpx_le_u32 v255, v2
+// GFX10: encoding: [0xff,0x05,0xa6,0x7d]
+
+v_cmpx_le_u32 s1, v2
+// GFX10: encoding: [0x01,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 s101, v2
+// GFX10: encoding: [0x65,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 0, v2
+// GFX10: encoding: [0x80,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0xa6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0xa6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_u32 v1, v255
+// GFX10: encoding: [0x01,0xff,0xa7,0x7d]
+
+v_cmpx_le_u32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_u32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_u32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_u32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_u32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_u32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_u32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_u32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd3,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_u32 v1, v2
+// GFX10: encoding: [0x01,0x05,0xa8,0x7d]
+
+v_cmpx_gt_u32 v255, v2
+// GFX10: encoding: [0xff,0x05,0xa8,0x7d]
+
+v_cmpx_gt_u32 s1, v2
+// GFX10: encoding: [0x01,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 s101, v2
+// GFX10: encoding: [0x65,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 0, v2
+// GFX10: encoding: [0x80,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0xa8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0xa8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_u32 v1, v255
+// GFX10: encoding: [0x01,0xff,0xa9,0x7d]
+
+v_cmpx_gt_u32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_u32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_u32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_u32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_u32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_u32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_u32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_u32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd4,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_u32 v1, v2
+// GFX10: encoding: [0x01,0x05,0xaa,0x7d]
+
+v_cmpx_ne_u32 v255, v2
+// GFX10: encoding: [0xff,0x05,0xaa,0x7d]
+
+v_cmpx_ne_u32 s1, v2
+// GFX10: encoding: [0x01,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 s101, v2
+// GFX10: encoding: [0x65,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 0, v2
+// GFX10: encoding: [0x80,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0xaa,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0xaa,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_u32 v1, v255
+// GFX10: encoding: [0x01,0xff,0xab,0x7d]
+
+v_cmpx_ne_u32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_u32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_u32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_u32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_u32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_u32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_u32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_u32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd5,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_u32 v1, v2
+// GFX10: encoding: [0x01,0x05,0xac,0x7d]
+
+v_cmpx_ge_u32 v255, v2
+// GFX10: encoding: [0xff,0x05,0xac,0x7d]
+
+v_cmpx_ge_u32 s1, v2
+// GFX10: encoding: [0x01,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 s101, v2
+// GFX10: encoding: [0x65,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 0, v2
+// GFX10: encoding: [0x80,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0xac,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0xac,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_u32 v1, v255
+// GFX10: encoding: [0x01,0xff,0xad,0x7d]
+
+v_cmpx_ge_u32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_u32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_u32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_u32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_u32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_u32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_u32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_u32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd6,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_u32 v1, v2
+// GFX10: encoding: [0x01,0x05,0xae,0x7d]
+
+v_cmpx_t_u32 v255, v2
+// GFX10: encoding: [0xff,0x05,0xae,0x7d]
+
+v_cmpx_t_u32 s1, v2
+// GFX10: encoding: [0x01,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 s101, v2
+// GFX10: encoding: [0x65,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 0, v2
+// GFX10: encoding: [0x80,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 0xaf123456, v2
+// GFX10: encoding: [0xff,0x04,0xae,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_u32 0x3f717273, v2
+// GFX10: encoding: [0xff,0x04,0xae,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_u32 v1, v255
+// GFX10: encoding: [0x01,0xff,0xaf,0x7d]
+
+v_cmpx_t_u32_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_u32_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_u32_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_u32_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u32_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_u32_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_u32_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u32_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_u32_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u32_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u32_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_u32_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd7,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xb0,0x7d]
+
+v_cmpx_f_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xb0,0x7d]
+
+v_cmpx_f_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xb0,0x7d]
+
+v_cmpx_f_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xb0,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_f_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xb0,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_f_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xb1,0x7d]
+
+v_cmpx_f_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xd8,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xb2,0x7d]
+
+v_cmpx_lt_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xb2,0x7d]
+
+v_cmpx_lt_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xb2,0x7d]
+
+v_cmpx_lt_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xb2,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xb2,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xb3,0x7d]
+
+v_cmpx_lt_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xd9,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xb4,0x7d]
+
+v_cmpx_eq_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xb4,0x7d]
+
+v_cmpx_eq_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xb4,0x7d]
+
+v_cmpx_eq_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xb4,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xb4,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_eq_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xb5,0x7d]
+
+v_cmpx_eq_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xda,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xb6,0x7d]
+
+v_cmpx_le_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xb6,0x7d]
+
+v_cmpx_le_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xb6,0x7d]
+
+v_cmpx_le_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xb6,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xb6,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_le_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xb7,0x7d]
+
+v_cmpx_le_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xdb,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xb8,0x7d]
+
+v_cmpx_gt_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xb8,0x7d]
+
+v_cmpx_gt_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xb8,0x7d]
+
+v_cmpx_gt_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xb8,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xb8,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_gt_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xb9,0x7d]
+
+v_cmpx_gt_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xdc,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xba,0x7d]
+
+v_cmpx_lg_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xba,0x7d]
+
+v_cmpx_lg_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xba,0x7d]
+
+v_cmpx_lg_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xba,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lg_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xba,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_lg_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xbb,0x7d]
+
+v_cmpx_lg_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_lg_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_lg_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lg_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lg_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lg_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_lg_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xdd,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xbc,0x7d]
+
+v_cmpx_ge_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xbc,0x7d]
+
+v_cmpx_ge_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xbc,0x7d]
+
+v_cmpx_ge_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xbc,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xbc,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ge_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xbd,0x7d]
+
+v_cmpx_ge_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xde,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xbe,0x7d]
+
+v_cmpx_o_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xbe,0x7d]
+
+v_cmpx_o_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xbe,0x7d]
+
+v_cmpx_o_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xbe,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_o_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xbe,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_o_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xbf,0x7d]
+
+v_cmpx_o_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_o_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_o_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_o_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_o_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_o_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_o_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xdf,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_u64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0xe0,0x7d]
+
+v_cmpx_f_u64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0xe0,0x7d]
+
+v_cmpx_f_u64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_u64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_u64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0xe1,0x7d]
+
+v_cmpx_f_u64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_u64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_u64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0xe2,0x7d]
+
+v_cmpx_lt_u64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0xe2,0x7d]
+
+v_cmpx_lt_u64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_u64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0xe3,0x7d]
+
+v_cmpx_lt_u64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_u64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_u64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0xe4,0x7d]
+
+v_cmpx_eq_u64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0xe4,0x7d]
+
+v_cmpx_eq_u64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_u64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0xe5,0x7d]
+
+v_cmpx_eq_u64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_u64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_u64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0xe6,0x7d]
+
+v_cmpx_le_u64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0xe6,0x7d]
+
+v_cmpx_le_u64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_u64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0xe7,0x7d]
+
+v_cmpx_le_u64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_u64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_u64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0xe8,0x7d]
+
+v_cmpx_gt_u64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0xe8,0x7d]
+
+v_cmpx_gt_u64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xe8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_u64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0xe9,0x7d]
+
+v_cmpx_gt_u64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_u64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_u64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0xea,0x7d]
+
+v_cmpx_ne_u64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0xea,0x7d]
+
+v_cmpx_ne_u64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xea,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xea,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_u64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0xeb,0x7d]
+
+v_cmpx_ne_u64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_u64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_u64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0xec,0x7d]
+
+v_cmpx_ge_u64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0xec,0x7d]
+
+v_cmpx_ge_u64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xec,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xec,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_u64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0xed,0x7d]
+
+v_cmpx_ge_u64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_u64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_u64 v[1:2], v[2:3]
+// GFX10: encoding: [0x01,0x05,0xee,0x7d]
+
+v_cmpx_t_u64 v[254:255], v[2:3]
+// GFX10: encoding: [0xfe,0x05,0xee,0x7d]
+
+v_cmpx_t_u64 s[2:3], v[2:3]
+// GFX10: encoding: [0x02,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 s[4:5], v[2:3]
+// GFX10: encoding: [0x04,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 s[100:101], v[2:3]
+// GFX10: encoding: [0x64,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, v[2:3]
+// GFX10: encoding: [0x6a,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 exec, v[2:3]
+// GFX10: encoding: [0x7e,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 0, v[2:3]
+// GFX10: encoding: [0x80,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 -1, v[2:3]
+// GFX10: encoding: [0xc1,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 0.5, v[2:3]
+// GFX10: encoding: [0xf0,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 -4.0, v[2:3]
+// GFX10: encoding: [0xf7,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 0xaf123456, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xee,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_u64 0x3f717273, v[2:3]
+// GFX10: encoding: [0xff,0x04,0xee,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_u64 v[1:2], v[254:255]
+// GFX10: encoding: [0x01,0xfd,0xef,0x7d]
+
+v_cmpx_t_u64_e64 v[1:2], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 v[254:255], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0xfe,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[2:3], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x02,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[4:5], v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x04,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 vcc, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 -1, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 0.5, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 -4.0, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], v[254:255]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xfd,0x03,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], s[4:5]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x09,0x00,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], s[6:7]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x0d,0x00,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], s[100:101]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xc9,0x00,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], vcc
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], exec
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], 0
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], -1
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], 0.5
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_u64_e64 v[1:2], -4.0
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xf0,0x7d]
+
+v_cmpx_u_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xf0,0x7d]
+
+v_cmpx_u_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xf0,0x7d]
+
+v_cmpx_u_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xf0,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_u_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xf0,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_u_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xf1,0x7d]
+
+v_cmpx_u_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_u_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_u_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_u_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_u_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_u_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_u_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xf8,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xf2,0x7d]
+
+v_cmpx_nge_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xf2,0x7d]
+
+v_cmpx_nge_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xf2,0x7d]
+
+v_cmpx_nge_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xf2,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nge_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xf2,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_nge_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xf3,0x7d]
+
+v_cmpx_nge_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_nge_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_nge_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nge_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nge_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nge_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_nge_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xf9,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xf4,0x7d]
+
+v_cmpx_nlg_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xf4,0x7d]
+
+v_cmpx_nlg_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xf4,0x7d]
+
+v_cmpx_nlg_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xf4,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlg_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xf4,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_nlg_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xf5,0x7d]
+
+v_cmpx_nlg_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlg_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfa,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xf6,0x7d]
+
+v_cmpx_ngt_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xf6,0x7d]
+
+v_cmpx_ngt_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xf6,0x7d]
+
+v_cmpx_ngt_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xf6,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ngt_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xf6,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ngt_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xf7,0x7d]
+
+v_cmpx_ngt_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_ngt_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfb,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xf8,0x7d]
+
+v_cmpx_nle_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xf8,0x7d]
+
+v_cmpx_nle_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xf8,0x7d]
+
+v_cmpx_nle_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xf8,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nle_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xf8,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_nle_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xf9,0x7d]
+
+v_cmpx_nle_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_nle_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_nle_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nle_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nle_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nle_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_nle_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfc,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xfa,0x7d]
+
+v_cmpx_neq_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xfa,0x7d]
+
+v_cmpx_neq_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xfa,0x7d]
+
+v_cmpx_neq_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xfa,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_neq_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xfa,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_neq_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xfb,0x7d]
+
+v_cmpx_neq_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_neq_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_neq_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_neq_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_neq_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_neq_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_neq_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfd,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xfc,0x7d]
+
+v_cmpx_nlt_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xfc,0x7d]
+
+v_cmpx_nlt_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xfc,0x7d]
+
+v_cmpx_nlt_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xfc,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlt_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xfc,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_nlt_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xfd,0x7d]
+
+v_cmpx_nlt_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlt_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xfe,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f16 v1, v2
+// GFX10: encoding: [0x01,0x05,0xfe,0x7d]
+
+v_cmpx_tru_f16 v255, v2
+// GFX10: encoding: [0xff,0x05,0xfe,0x7d]
+
+v_cmpx_tru_f16 s1, v2
+// GFX10: encoding: [0x01,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 s101, v2
+// GFX10: encoding: [0x65,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 vcc_lo, v2
+// GFX10: encoding: [0x6a,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 vcc_hi, v2
+// GFX10: encoding: [0x6b,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 m0, v2
+// GFX10: encoding: [0x7c,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 exec_lo, v2
+// GFX10: encoding: [0x7e,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 exec_hi, v2
+// GFX10: encoding: [0x7f,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 0, v2
+// GFX10: encoding: [0x80,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 -1, v2
+// GFX10: encoding: [0xc1,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 0.5, v2
+// GFX10: encoding: [0xf0,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 -4.0, v2
+// GFX10: encoding: [0xf7,0x04,0xfe,0x7d]
+
+v_cmpx_tru_f16 0xfe0b, v2
+// GFX10: encoding: [0xff,0x04,0xfe,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_tru_f16 0x3456, v2
+// GFX10: encoding: [0xff,0x04,0xfe,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_tru_f16 v1, v255
+// GFX10: encoding: [0x01,0xff,0xff,0x7d]
+
+v_cmpx_tru_f16_e64 v1, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 v255, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0xff,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s1, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s101, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x65,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 vcc_lo, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 vcc_hi, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x6b,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 m0, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x7c,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 exec_lo, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 exec_hi, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x7f,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 0, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 -1, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 0.5, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 -4.0, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 v1, v255
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xff,0x03,0x00]
+
+v_cmpx_tru_f16_e64 v1, s2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x00,0x00]
+
+v_cmpx_tru_f16_e64 v1, s101
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xcb,0x00,0x00]
+
+v_cmpx_tru_f16_e64 v1, vcc_lo
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f16_e64 v1, vcc_hi
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xd7,0x00,0x00]
+
+v_cmpx_tru_f16_e64 v1, m0
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xf9,0x00,0x00]
+
+v_cmpx_tru_f16_e64 v1, exec_lo
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f16_e64 v1, exec_hi
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xff,0x00,0x00]
+
+v_cmpx_tru_f16_e64 v1, 0
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f16_e64 v1, -1
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f16_e64 v1, 0.5
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f16_e64 v1, -4.0
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f16_e64 -v1, v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f16_e64 v1, -v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f16_e64 -v1, -v2
+// GFX10: encoding: [0x00,0x00,0xff,0xd4,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_f_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_f_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_f_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_f_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_f_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_f_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x21,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x20,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x23,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x22,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x25,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x24,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_le_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_le_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_le_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_le_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_le_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_le_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x27,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x26,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x29,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x28,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x2b,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ne_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ne_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ne_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2a,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x2d,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2c,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_t_i32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_t_i32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_t_i32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_t_i32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_t_i32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_t_i32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_t_i32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x2f,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_t_i32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_t_i32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_t_i32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x2e,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x33,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x32,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x35,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x34,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_le_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_le_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_le_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_le_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_le_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_le_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x37,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x36,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x39,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x38,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x3b,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ne_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ne_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ne_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3a,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x3d,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_i16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_i16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_i16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x3c,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x73,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x75,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_le_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_le_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_le_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_le_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_le_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_le_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x77,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x79,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x7b,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ne_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ne_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ne_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0x7d,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_u16_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_u16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_u16_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_f_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_f_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_f_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_f_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_f_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_f_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xa1,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xa3,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xa5,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_le_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_le_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_le_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_le_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_le_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_le_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xa7,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xa9,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xab,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ne_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ne_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ne_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xad,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u32_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_t_u32_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_t_u32_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_t_u32_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_t_u32_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_t_u32_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_t_u32_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_t_u32_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xaf,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_t_u32_sdwa sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_t_u32_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_t_u32_sdwa v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_f_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_f_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_f_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_f_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_f_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_f_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xb1,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_f_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_f_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xb3,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_lt_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_lt_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xb5,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_eq_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_eq_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_le_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_le_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_le_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_le_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_le_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_le_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xb7,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_le_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_le_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xb9,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_gt_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_gt_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xbb,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lg_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_lg_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lg_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_lg_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xbd,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_ge_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_ge_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_o_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_o_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_o_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_o_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_o_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_o_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_o_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xbf,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_o_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_o_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_o_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_o_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_o_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_u_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_u_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_u_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_u_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_u_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_u_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_u_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xf1,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_u_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_u_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_u_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_u_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_u_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf0,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xf3,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_nge_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_nge_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_nge_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_nge_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_nge_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf2,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xf5,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_nlg_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_nlg_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_nlg_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_nlg_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_nlg_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf4,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xf7,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ngt_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_ngt_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ngt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ngt_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_ngt_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf6,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xf9,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_nle_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_nle_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_nle_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_nle_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_nle_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xf8,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xfb,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_neq_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_neq_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_neq_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_neq_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_neq_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfa,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xfd,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_nlt_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_nlt_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_nlt_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_nlt_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_nlt_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfc,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa v255, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa s1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s101, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x65,0x00,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x6a,0x00,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x6b,0x00,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa m0, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x7c,0x00,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x7e,0x00,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x7f,0x00,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa v1, v255 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0xfe,0xff,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_tru_f16_sdwa -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x16,0x06]
+
+v_cmpx_tru_f16_sdwa |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x26,0x06]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_tru_f16_sdwa v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_tru_f16_sdwa v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x16]
+
+v_cmpx_tru_f16_sdwa v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// GFX10: encoding: [0xf9,0x04,0xfe,0x7d,0x01,0x00,0x06,0x26]
+
+v_cmpx_f_u64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf0,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf1,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf2,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf3,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf4,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf5,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf6,0xd4,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 exec, v[2:3]
+// GFX10: encoding: [0x00,0x00,0xf7,0xd4,0x7e,0x04,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx10_err_pos.s b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
index 013dba6410012..7f77a0da2a78c 100644
--- a/llvm/test/MC/AMDGPU/gfx10_err_pos.s
+++ b/llvm/test/MC/AMDGPU/gfx10_err_pos.s
@@ -443,21 +443,6 @@ v_ceil_f16 v0, abs(neg(1))
 // CHECK-NEXT:{{^}}v_ceil_f16 v0, abs(neg(1))
 // CHECK-NEXT:{{^}}                   ^
 
-v_interp_mov_f32 v11, invalid_param_3, attr0.y
-// CHECK: error: failed parsing operand.
-// CHECK-NEXT:{{^}}v_interp_mov_f32 v11, invalid_param_3, attr0.y
-// CHECK-NEXT:{{^}}                      ^
-
-v_interp_mov_f32 v8, foo, attr0.x
-// CHECK: error: failed parsing operand.
-// CHECK-NEXT:{{^}}v_interp_mov_f32 v8, foo, attr0.x
-// CHECK-NEXT:{{^}}                     ^
-
-v_interp_p2_f32 v0, v1, attr
-// CHECK: error: failed parsing operand.
-// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, attr
-// CHECK-NEXT:{{^}}                        ^
-
 //==============================================================================
 // first register index should not exceed second index
 
@@ -588,6 +573,22 @@ v_dot_f32_f16 v0, v1, v2
 // CHECK-NEXT:{{^}}v_dot_f32_f16 v0, v1, v2
 // CHECK-NEXT:{{^}}^
 
+//==============================================================================
+// invalid interpolation attribute
+
+v_interp_p2_f32 v0, v1, att
+// CHECK: error: invalid interpolation attribute
+// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, att
+// CHECK-NEXT:{{^}}                        ^
+
+//==============================================================================
+// invalid interpolation slot
+
+v_interp_mov_f32 v8, p1, attr0.x
+// CHECK: error: invalid interpolation slot
+// CHECK-NEXT:{{^}}v_interp_mov_f32 v8, p1, attr0.x
+// CHECK-NEXT:{{^}}                     ^
+
 //==============================================================================
 // invalid mask
 
@@ -625,6 +626,22 @@ v_cvt_f64_i32 v[5:6], s1 mul:3
 // CHECK-NEXT:{{^}}v_cvt_f64_i32 v[5:6], s1 mul:3
 // CHECK-NEXT:{{^}}                         ^
 
+//==============================================================================
+// invalid or missing interpolation attribute channel
+
+v_interp_p2_f32 v0, v1, attr0.q
+// CHECK: error: invalid or missing interpolation attribute channel
+// CHECK-NEXT:{{^}}v_interp_p2_f32 v0, v1, attr0.q
+// CHECK-NEXT:{{^}}                        ^
+
+//==============================================================================
+// invalid or missing interpolation attribute number
+
+v_interp_p2_f32 v7, v1, attr.x
+// CHECK: error: invalid or missing interpolation attribute number
+// CHECK-NEXT:{{^}}v_interp_p2_f32 v7, v1, attr.x
+// CHECK-NEXT:{{^}}                        ^
+
 //==============================================================================
 // invalid op_sel operand
 
@@ -870,10 +887,10 @@ v_bfe_u32 v0, v2, undef, 123
 // CHECK-NEXT:{{^}}                         ^
 
 //==============================================================================
-// out of bounds attr
+// out of bounds interpolation attribute number
 
 v_interp_p1_f32 v0, v1, attr64.w
-// CHECK: error: out of bounds attr
+// CHECK: error: out of bounds interpolation attribute number
 // CHECK-NEXT:{{^}}v_interp_p1_f32 v0, v1, attr64.w
 // CHECK-NEXT:{{^}}                        ^
 
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_all.s b/llvm/test/MC/AMDGPU/gfx7_asm_all.s
deleted file mode 100644
index 73247d17aed1a..0000000000000
--- a/llvm/test/MC/AMDGPU/gfx7_asm_all.s
+++ /dev/null
@@ -1,86860 +0,0 @@
-// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
-
-ds_add_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd8,0xff,0x02,0x00,0x00]
-
-ds_add_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd8,0x01,0xff,0x00,0x00]
-
-ds_add_u32 v1, v2
-// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x02,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd8,0xff,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd8,0x01,0xff,0x00,0x00]
-
-ds_sub_u32 v1, v2
-// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x06,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
-
-ds_rsub_u32 v1, v2
-// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0xff,0x00,0x00]
-
-ds_inc_u32 v1, v2
-// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd8,0xff,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd8,0x01,0xff,0x00,0x00]
-
-ds_dec_u32 v1, v2
-// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x12,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_i32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd8,0x01,0xff,0x00,0x00]
-
-ds_min_i32 v1, v2
-// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x16,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_i32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0x01,0xff,0x00,0x00]
-
-ds_max_i32 v1, v2
-// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x18,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x1c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x1c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x1c,0xd8,0x01,0xff,0x00,0x00]
-
-ds_min_u32 v1, v2
-// CHECK: [0x00,0x00,0x1c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x1c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x1c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x1e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0x01,0xff,0x00,0x00]
-
-ds_max_u32 v1, v2
-// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x20,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd8,0xff,0x02,0x00,0x00]
-
-ds_and_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd8,0x01,0xff,0x00,0x00]
-
-ds_and_b32 v1, v2
-// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x26,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x28,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x28,0xd8,0xff,0x02,0x00,0x00]
-
-ds_or_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x28,0xd8,0x01,0xff,0x00,0x00]
-
-ds_or_b32 v1, v2
-// CHECK: [0x00,0x00,0x28,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x28,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x28,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x2c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x2c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x2c,0xd8,0x01,0xff,0x00,0x00]
-
-ds_xor_b32 v1, v2
-// CHECK: [0x00,0x00,0x2c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x2c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x2c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x2e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x30,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x30,0xd8,0xff,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x30,0xd8,0x01,0xff,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x30,0xd8,0x01,0x02,0xff,0x00]
-
-ds_mskor_b32 v1, v2, v3
-// CHECK: [0x00,0x00,0x30,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x30,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x30,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x32,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x34,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x34,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x34,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b32 v1, v2
-// CHECK: [0x00,0x00,0x34,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x34,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x34,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x36,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x38,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x38,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x38,0xd8,0x01,0xff,0x03,0x00]
-
-ds_write2_b32 v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x38,0xd8,0x01,0x02,0xff,0x00]
-
-ds_write2_b32 v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x38,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x38,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x38,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x38,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x38,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x38,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x3a,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x3c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x3c,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x3c,0xd8,0x01,0xff,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x3c,0xd8,0x01,0x02,0xff,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x3c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x3c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x3c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x3c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x3c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x3c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x3e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0x01,0xff,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0xff,0x00]
-
-ds_cmpst_b32 v1, v2, v3
-// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x40,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0x01,0xff,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0xff,0x00]
-
-ds_cmpst_f32 v1, v2, v3
-// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x44,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x03,0x00]
-
-ds_min_f32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_f32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0x01,0xff,0x00,0x00]
-
-ds_min_f32 v1, v2
-// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x48,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_f32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0xff,0x00,0x00]
-
-ds_max_f32 v1, v2
-// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x4c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_nop
-// CHECK: [0x00,0x00,0x50,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:65535 gds
-// CHECK: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all gds
-// CHECK: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:0 gds
-// CHECK: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:4 gds
-// CHECK: [0x04,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_init v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_init v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x66,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_init v1 gds
-// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_init v1 offset:0 gds
-// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_init v1 offset:4 gds
-// CHECK: [0x04,0x00,0x66,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:65535 gds
-// CHECK: [0xff,0xff,0x6a,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v gds
-// CHECK: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:0 gds
-// CHECK: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:4 gds
-// CHECK: [0x04,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x6e,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_br v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 gds
-// CHECK: [0x00,0x00,0x6e,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 offset:0 gds
-// CHECK: [0x00,0x00,0x6e,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 offset:4 gds
-// CHECK: [0x04,0x00,0x6e,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:65535 gds
-// CHECK: [0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p gds
-// CHECK: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:0 gds
-// CHECK: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:4 gds
-// CHECK: [0x04,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
-
-ds_gws_barrier v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_barrier v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x76,0xd8,0xff,0x00,0x00,0x00]
-
-ds_gws_barrier v1 gds
-// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_barrier v1 offset:0 gds
-// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x00]
-
-ds_gws_barrier v1 offset:4 gds
-// CHECK: [0x04,0x00,0x76,0xd8,0x01,0x00,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x78,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b8 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x78,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b8 v1, v2
-// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x78,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b16 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b16 v1, v2
-// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x7c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0xff,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0x01,0xff,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x80,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x82,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0xff,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0x01,0xff,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x84,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x86,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0xff,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0x01,0xff,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x88,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0xff,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0xff,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x8c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0xff,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0x01,0xff,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x90,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x92,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2
-// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x94,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x96,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2
-// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x98,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x9c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x9c,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x9c,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x9c,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x9c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x9c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x9c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x9e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0xa0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0xff,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0xff,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0xa4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd8,0xff,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0xff,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0xa8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0xaa,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xac,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xac,0xd8,0x01,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0xac,0xd8,0xff,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0xac,0xd8,0x01,0xff,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0xac,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0xac,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0xac,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0xae,0xd8,0x01,0x02,0x00,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x02,0x03,0xff]
-
-ds_mskor_rtn_b32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd8,0xff,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0xff,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x02,0xff,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0xb0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0xb0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0xb0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0xb2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd8,0xff,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0xff,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0xb4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0xb4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0xb4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0xb6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_wrxchg2_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xb8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xba,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xbc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xbe,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x03,0xff]
-
-ds_cmpst_rtn_b32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0xff,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0xff,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x03,0xff]
-
-ds_cmpst_rtn_f32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0xff,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0xff,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x03,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_f32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2
-// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_f32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2
-// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
-
-ds_wrap_rtn_b32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_swizzle_b32 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
-
-ds_swizzle_b32 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1
-// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:0
-// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:4
-// CHECK: [0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_b32 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1
-// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:0
-// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:4
-// CHECK: [0x04,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read2_b32 v[5:6], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset1:255
-// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127
-// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xdc,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xe0,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read2st64_b32 v[5:6], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xe0,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset1:255
-// CHECK: [0x00,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127
-// CHECK: [0x7f,0x00,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xe0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xe2,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i8 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1
-// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:0
-// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:4
-// CHECK: [0x04,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xe8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xe8,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u8 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xe8,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1
-// CHECK: [0x00,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:0
-// CHECK: [0x00,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:4
-// CHECK: [0x04,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xea,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i16 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xec,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1
-// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:0
-// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:4
-// CHECK: [0x04,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xf0,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u16 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xf0,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1
-// CHECK: [0x00,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:0
-// CHECK: [0x00,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:4
-// CHECK: [0x04,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xf2,0xd8,0x01,0x00,0x00,0x05]
-
-ds_consume v5 offset:65535
-// CHECK: [0xff,0xff,0xf4,0xd8,0x00,0x00,0x00,0x05]
-
-ds_consume v255 offset:65535
-// CHECK: [0xff,0xff,0xf4,0xd8,0x00,0x00,0x00,0xff]
-
-ds_consume v5
-// CHECK: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:0
-// CHECK: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:4
-// CHECK: [0x04,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:65535 gds
-// CHECK: [0xff,0xff,0xf6,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:65535
-// CHECK: [0xff,0xff,0xf8,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v255 offset:65535
-// CHECK: [0xff,0xff,0xf8,0xd8,0x00,0x00,0x00,0xff]
-
-ds_append v5
-// CHECK: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:0
-// CHECK: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:4
-// CHECK: [0x04,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:65535 gds
-// CHECK: [0xff,0xff,0xfa,0xd8,0x00,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xfe,0xd8,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v255, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xfe,0xd8,0x01,0x00,0x00,0xff]
-
-ds_ordered_count v5, v255 offset:65535 gds
-// CHECK: [0xff,0xff,0xfe,0xd8,0xff,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 gds
-// CHECK: [0x00,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:0 gds
-// CHECK: [0x00,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:4 gds
-// CHECK: [0x04,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
-
-ds_add_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x00,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x00,0xd9,0xff,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x00,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_add_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x02,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x04,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x04,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x06,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x08,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x08,0xd9,0xff,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x08,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x0a,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd9,0xff,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x0e,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x10,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x10,0xd9,0xff,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x10,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x12,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x14,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x14,0xd9,0xff,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x14,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_min_i64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x16,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x18,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x18,0xd9,0xff,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x18,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_max_i64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x1a,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x1c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x1c,0xd9,0xff,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x1c,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_min_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x1e,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x20,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x20,0xd9,0xff,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x20,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_max_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x22,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x24,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x24,0xd9,0xff,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x24,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_and_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x26,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x28,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x28,0xd9,0xff,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x28,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_or_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x2a,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x2c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x2c,0xd9,0xff,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x2c,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x2e,0xd9,0x01,0x02,0x00,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x30,0xd9,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x30,0xd9,0xff,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x30,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x30,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0x32,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x34,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x34,0xd9,0xff,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x34,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_write_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x36,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x38,0xd9,0xff,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x38,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x38,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x38,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x3a,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x3c,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x3c,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x3c,0xd9,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x3e,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x40,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x40,0xd9,0xff,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x40,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x40,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0x42,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x44,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x44,0xd9,0xff,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x44,0xd9,0x01,0xfe,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x44,0xd9,0x01,0x02,0xfe,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0x46,0xd9,0x01,0x02,0x03,0x00]
-
-ds_min_f64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x48,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x48,0xd9,0xff,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x48,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_min_f64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x4a,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd9,0xff,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd9,0x01,0xfe,0x00,0x00]
-
-ds_max_f64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x4e,0xd9,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd9,0xff,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x82,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_sub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd9,0xff,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x86,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_rsub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd9,0xff,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x8a,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_inc_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd9,0xff,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x8e,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_dec_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd9,0xff,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x92,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_i64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd9,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x96,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_i64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd9,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x9a,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x9c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x9c,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x9c,0xd9,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x9c,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x9e,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd9,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xa2,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_and_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd9,0xff,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xa6,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_or_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd9,0xff,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xaa,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xac,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xac,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_xor_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xac,0xd9,0xff,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xac,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xae,0xd9,0x01,0x02,0x00,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd9,0x01,0x02,0x03,0xfe]
-
-ds_mskor_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd9,0xff,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xb2,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_wrxchg_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd9,0xff,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xb6,0xd9,0x01,0x02,0x00,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0x03,0xfc]
-
-ds_wrxchg2_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd9,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xb8,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xba,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0x03,0xfc]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd9,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xbc,0xd9,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xbe,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd9,0x01,0x02,0x03,0xfe]
-
-ds_cmpst_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd9,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xc2,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd9,0x01,0x02,0x03,0xfe]
-
-ds_cmpst_rtn_f64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd9,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd9,0x01,0xfe,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd9,0x01,0x02,0xfe,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xc6,0xd9,0x01,0x02,0x03,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_f64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd9,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xca,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_f64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd9,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xce,0xd9,0x01,0x02,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[254:255], v1 offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd9,0x01,0x00,0x00,0xfe]
-
-ds_read_b64 v[5:6], v255 offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1
-// CHECK: [0x00,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:0
-// CHECK: [0x00,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:4
-// CHECK: [0x04,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xda,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd9,0x01,0x00,0x00,0xfc]
-
-ds_read2_b64 v[5:8], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset1:255
-// CHECK: [0x00,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127
-// CHECK: [0x7f,0x00,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xdc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xde,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xe0,0xd9,0x01,0x00,0x00,0xfc]
-
-ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset1:255
-// CHECK: [0x00,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127
-// CHECK: [0x7f,0x00,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xe0,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xe2,0xd9,0x01,0x00,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xf8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xf8,0xd9,0x01,0x02,0x00,0xfe]
-
-ds_condxchg32_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xf8,0xd9,0xff,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xf8,0xd9,0x01,0xfe,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xfa,0xd9,0x01,0x02,0x00,0x05]
-
-ds_add_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x00,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x00,0xda,0xff,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1
-// CHECK: [0x00,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x02,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x04,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x04,0xda,0xff,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1
-// CHECK: [0x00,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x06,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x08,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x08,0xda,0xff,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1
-// CHECK: [0x00,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0a,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xda,0xff,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1
-// CHECK: [0x00,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0e,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x10,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x10,0xda,0xff,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1
-// CHECK: [0x00,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x12,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:65535
-// CHECK: [0xff,0xff,0x14,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v255 offset:65535
-// CHECK: [0xff,0xff,0x14,0xda,0xff,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1
-// CHECK: [0x00,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:0
-// CHECK: [0x00,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:4
-// CHECK: [0x04,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x16,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:65535
-// CHECK: [0xff,0xff,0x18,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v255 offset:65535
-// CHECK: [0xff,0xff,0x18,0xda,0xff,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1
-// CHECK: [0x00,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:0
-// CHECK: [0x00,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:4
-// CHECK: [0x04,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x1a,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x1c,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x1c,0xda,0xff,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1
-// CHECK: [0x00,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x1e,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x20,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x20,0xda,0xff,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1
-// CHECK: [0x00,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x22,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x24,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x24,0xda,0xff,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1
-// CHECK: [0x00,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x26,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x28,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x28,0xda,0xff,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1
-// CHECK: [0x00,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x2a,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x2c,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x2c,0xda,0xff,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1
-// CHECK: [0x00,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x2e,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x34,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x34,0xda,0xff,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1
-// CHECK: [0x00,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x36,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:65535
-// CHECK: [0xff,0xff,0x48,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v255 offset:65535
-// CHECK: [0xff,0xff,0x48,0xda,0xff,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1
-// CHECK: [0x00,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:0
-// CHECK: [0x00,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:4
-// CHECK: [0x04,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x4a,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v255 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xda,0xff,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1
-// CHECK: [0x00,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:0
-// CHECK: [0x00,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:4
-// CHECK: [0x04,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x4e,0xda,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x00,0xdb,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x00,0xdb,0xff,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1
-// CHECK: [0x00,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x02,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x04,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x04,0xdb,0xff,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1
-// CHECK: [0x00,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x06,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x08,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x08,0xdb,0xff,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1
-// CHECK: [0x00,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0a,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xdb,0xff,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1
-// CHECK: [0x00,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0e,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x10,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x10,0xdb,0xff,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1
-// CHECK: [0x00,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x12,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:65535
-// CHECK: [0xff,0xff,0x14,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v255 offset:65535
-// CHECK: [0xff,0xff,0x14,0xdb,0xff,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1
-// CHECK: [0x00,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:0
-// CHECK: [0x00,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:4
-// CHECK: [0x04,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x16,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:65535
-// CHECK: [0xff,0xff,0x18,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v255 offset:65535
-// CHECK: [0xff,0xff,0x18,0xdb,0xff,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1
-// CHECK: [0x00,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:0
-// CHECK: [0x00,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:4
-// CHECK: [0x04,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x1a,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x1c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x1c,0xdb,0xff,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1
-// CHECK: [0x00,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x1e,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x20,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x20,0xdb,0xff,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1
-// CHECK: [0x00,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x22,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x24,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x24,0xdb,0xff,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1
-// CHECK: [0x00,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x26,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x28,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x28,0xdb,0xff,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1
-// CHECK: [0x00,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x2a,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x2c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x2c,0xdb,0xff,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1
-// CHECK: [0x00,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x2e,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x34,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x34,0xdb,0xff,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1
-// CHECK: [0x00,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x36,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:65535
-// CHECK: [0xff,0xff,0x48,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v255 offset:65535
-// CHECK: [0xff,0xff,0x48,0xdb,0xff,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1
-// CHECK: [0x00,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:0
-// CHECK: [0x00,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:4
-// CHECK: [0x04,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x4a,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v255 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xdb,0xff,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1
-// CHECK: [0x00,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:0
-// CHECK: [0x00,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:4
-// CHECK: [0x04,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x4e,0xdb,0x01,0x00,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:65535
-// CHECK: [0xff,0xff,0x78,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v255, v[2:4] offset:65535
-// CHECK: [0xff,0xff,0x78,0xdb,0xff,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[253:255] offset:65535
-// CHECK: [0xff,0xff,0x78,0xdb,0x01,0xfd,0x00,0x00]
-
-ds_write_b96 v1, v[2:4]
-// CHECK: [0x00,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:0
-// CHECK: [0x00,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:4
-// CHECK: [0x04,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:65535 gds
-// CHECK: [0xff,0xff,0x7a,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:65535
-// CHECK: [0xff,0xff,0x7c,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v255, v[2:5] offset:65535
-// CHECK: [0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[252:255] offset:65535
-// CHECK: [0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00]
-
-ds_write_b128 v1, v[2:5]
-// CHECK: [0x00,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:0
-// CHECK: [0x00,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:4
-// CHECK: [0x04,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:65535 gds
-// CHECK: [0xff,0xff,0x7e,0xdb,0x01,0x02,0x00,0x00]
-
-ds_read_b96 v[5:7], v1 offset:65535
-// CHECK: [0xff,0xff,0xf8,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[253:255], v1 offset:65535
-// CHECK: [0xff,0xff,0xf8,0xdb,0x01,0x00,0x00,0xfd]
-
-ds_read_b96 v[5:7], v255 offset:65535
-// CHECK: [0xff,0xff,0xf8,0xdb,0xff,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1
-// CHECK: [0x00,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:0
-// CHECK: [0x00,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:4
-// CHECK: [0x04,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xfa,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:65535
-// CHECK: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[252:255], v1 offset:65535
-// CHECK: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc]
-
-ds_read_b128 v[5:8], v255 offset:65535
-// CHECK: [0xff,0xff,0xfc,0xdb,0xff,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1
-// CHECK: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:0
-// CHECK: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:4
-// CHECK: [0x04,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xfe,0xdb,0x01,0x00,0x00,0x05]
-
-exp mrt0 v0, v0, v0, v0
-// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrtz v0, v0, v0, v0
-// CHECK: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp null v0, v0, v0, v0
-// CHECK: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp pos0 v0, v0, v0, v0
-// CHECK: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp param0 v0, v0, v0, v0
-// CHECK: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v255, v0, v0, v0
-// CHECK: [0x0f,0x00,0x00,0xf8,0xff,0x00,0x00,0x00]
-
-exp mrt0 v0, v255, v0, v0
-// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0xff,0x00,0x00]
-
-exp mrt0 v0, v0, v255, v0
-// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0xff,0x00]
-
-exp mrt0 v0, v0, v0, v255
-// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0xff]
-
-exp mrt0 v0, off, off, off
-// CHECK: [0x01,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, off, off
-// CHECK: [0x02,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, off, off
-// CHECK: [0x03,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, v0, off
-// CHECK: [0x04,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, off, v0, off
-// CHECK: [0x05,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, v0, off
-// CHECK: [0x06,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, off
-// CHECK: [0x07,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, off, v0
-// CHECK: [0x08,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, off, off, v0
-// CHECK: [0x09,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, off, v0
-// CHECK: [0x0a,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, off, v0
-// CHECK: [0x0b,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, v0, v0
-// CHECK: [0x0c,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, off, v0, v0
-// CHECK: [0x0d,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, v0, v0
-// CHECK: [0x0e,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, off, off
-// CHECK: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, v0 done
-// CHECK: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, v0 compr
-// CHECK: [0x0f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, v0 vm
-// CHECK: [0x0f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00]
-
-flat_load_ubyte v5, v[1:2]
-// CHECK: [0x00,0x00,0x20,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte v255, v[1:2]
-// CHECK: [0x00,0x00,0x20,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_ubyte v5, v[254:255]
-// CHECK: [0x00,0x00,0x20,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_ubyte v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x21,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x22,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2]
-// CHECK: [0x00,0x00,0x24,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v255, v[1:2]
-// CHECK: [0x00,0x00,0x24,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_sbyte v5, v[254:255]
-// CHECK: [0x00,0x00,0x24,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x25,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x26,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2]
-// CHECK: [0x00,0x00,0x28,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v255, v[1:2]
-// CHECK: [0x00,0x00,0x28,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_ushort v5, v[254:255]
-// CHECK: [0x00,0x00,0x28,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x29,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x2a,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2]
-// CHECK: [0x00,0x00,0x2c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v255, v[1:2]
-// CHECK: [0x00,0x00,0x2c,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_sshort v5, v[254:255]
-// CHECK: [0x00,0x00,0x2c,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x2d,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x2e,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2]
-// CHECK: [0x00,0x00,0x30,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v255, v[1:2]
-// CHECK: [0x00,0x00,0x30,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_dword v5, v[254:255]
-// CHECK: [0x00,0x00,0x30,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x31,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x32,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2]
-// CHECK: [0x00,0x00,0x34,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[254:255], v[1:2]
-// CHECK: [0x00,0x00,0x34,0xdc,0x01,0x00,0x00,0xfe]
-
-flat_load_dwordx2 v[5:6], v[254:255]
-// CHECK: [0x00,0x00,0x34,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2] glc
-// CHECK: [0x00,0x00,0x35,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2] slc
-// CHECK: [0x00,0x00,0x36,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2]
-// CHECK: [0x00,0x00,0x38,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[252:255], v[1:2]
-// CHECK: [0x00,0x00,0x38,0xdc,0x01,0x00,0x00,0xfc]
-
-flat_load_dwordx4 v[5:8], v[254:255]
-// CHECK: [0x00,0x00,0x38,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2] glc
-// CHECK: [0x00,0x00,0x39,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2] slc
-// CHECK: [0x00,0x00,0x3a,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2]
-// CHECK: [0x00,0x00,0x3c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[253:255], v[1:2]
-// CHECK: [0x00,0x00,0x3c,0xdc,0x01,0x00,0x00,0xfd]
-
-flat_load_dwordx3 v[5:7], v[254:255]
-// CHECK: [0x00,0x00,0x3c,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2] glc
-// CHECK: [0x00,0x00,0x3d,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2] slc
-// CHECK: [0x00,0x00,0x3e,0xdc,0x01,0x00,0x00,0x05]
-
-flat_store_byte v[1:2], v2
-// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte v[254:255], v2
-// CHECK: [0x00,0x00,0x60,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_byte v[1:2], v255
-// CHECK: [0x00,0x00,0x60,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_byte v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x61,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x62,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v2
-// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[254:255], v2
-// CHECK: [0x00,0x00,0x68,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v255
-// CHECK: [0x00,0x00,0x68,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_short v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x69,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x6a,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v2
-// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[254:255], v2
-// CHECK: [0x00,0x00,0x70,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v255
-// CHECK: [0x00,0x00,0x70,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_dword v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x71,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x72,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x74,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x74,0xdc,0x01,0xfe,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x75,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x76,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5]
-// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[254:255], v[2:5]
-// CHECK: [0x00,0x00,0x78,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[252:255]
-// CHECK: [0x00,0x00,0x78,0xdc,0x01,0xfc,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5] glc
-// CHECK: [0x00,0x00,0x79,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5] slc
-// CHECK: [0x00,0x00,0x7a,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4]
-// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[254:255], v[2:4]
-// CHECK: [0x00,0x00,0x7c,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[253:255]
-// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0xfd,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4] glc
-// CHECK: [0x00,0x00,0x7d,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4] slc
-// CHECK: [0x00,0x00,0x7e,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v2
-// CHECK: [0x00,0x00,0xc0,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[254:255], v2
-// CHECK: [0x00,0x00,0xc0,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v255
-// CHECK: [0x00,0x00,0xc0,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_swap v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xc1,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xc2,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xc4,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0xc4,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0xc4,0xdc,0x01,0xfe,0x00,0x00]
-
-flat_atomic_cmpswap v0, v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0xc5,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0xc6,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v2
-// CHECK: [0x00,0x00,0xc8,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[254:255], v2
-// CHECK: [0x00,0x00,0xc8,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v255
-// CHECK: [0x00,0x00,0xc8,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_add v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xc9,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xca,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v2
-// CHECK: [0x00,0x00,0xcc,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[254:255], v2
-// CHECK: [0x00,0x00,0xcc,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v255
-// CHECK: [0x00,0x00,0xcc,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_sub v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xcd,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xce,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v2
-// CHECK: [0x00,0x00,0xd4,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[254:255], v2
-// CHECK: [0x00,0x00,0xd4,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v255
-// CHECK: [0x00,0x00,0xd4,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_smin v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xd5,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xd6,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v2
-// CHECK: [0x00,0x00,0xd8,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[254:255], v2
-// CHECK: [0x00,0x00,0xd8,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v255
-// CHECK: [0x00,0x00,0xd8,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_umin v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xd9,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xda,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v2
-// CHECK: [0x00,0x00,0xdc,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[254:255], v2
-// CHECK: [0x00,0x00,0xdc,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v255
-// CHECK: [0x00,0x00,0xdc,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_smax v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xdd,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xde,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v2
-// CHECK: [0x00,0x00,0xe0,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[254:255], v2
-// CHECK: [0x00,0x00,0xe0,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v255
-// CHECK: [0x00,0x00,0xe0,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_umax v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xe1,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xe2,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v2
-// CHECK: [0x00,0x00,0xe4,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[254:255], v2
-// CHECK: [0x00,0x00,0xe4,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v255
-// CHECK: [0x00,0x00,0xe4,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_and v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xe5,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xe6,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v2
-// CHECK: [0x00,0x00,0xe8,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[254:255], v2
-// CHECK: [0x00,0x00,0xe8,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v255
-// CHECK: [0x00,0x00,0xe8,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_or v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xe9,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xea,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v2
-// CHECK: [0x00,0x00,0xec,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[254:255], v2
-// CHECK: [0x00,0x00,0xec,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v255
-// CHECK: [0x00,0x00,0xec,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_xor v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xed,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xee,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v2
-// CHECK: [0x00,0x00,0xf0,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[254:255], v2
-// CHECK: [0x00,0x00,0xf0,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v255
-// CHECK: [0x00,0x00,0xf0,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_inc v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xf1,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xf2,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v2
-// CHECK: [0x00,0x00,0xf4,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[254:255], v2
-// CHECK: [0x00,0x00,0xf4,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v255
-// CHECK: [0x00,0x00,0xf4,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_dec v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xf5,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xf6,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_fcmpswap v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xf8,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_fcmpswap v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0xf8,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_fcmpswap v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0xf8,0xdc,0x01,0xfe,0x00,0x00]
-
-flat_atomic_fcmpswap v0, v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0xf9,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_fcmpswap v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0xfa,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmin v[1:2], v2
-// CHECK: [0x00,0x00,0xfc,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmin v[254:255], v2
-// CHECK: [0x00,0x00,0xfc,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_atomic_fmin v[1:2], v255
-// CHECK: [0x00,0x00,0xfc,0xdc,0x01,0xff,0x00,0x00]
-
-flat_atomic_fmin v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0xfd,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmin v[1:2], v2 slc
-// CHECK: [0x00,0x00,0xfe,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmax v[1:2], v2
-// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmax v[254:255], v2
-// CHECK: [0x00,0x00,0x00,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_fmax v[1:2], v255
-// CHECK: [0x00,0x00,0x00,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_fmax v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x01,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmax v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x02,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x40,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x40,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x40,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_swap_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x41,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x42,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5]
-// CHECK: [0x00,0x00,0x44,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[254:255], v[2:5]
-// CHECK: [0x00,0x00,0x44,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[252:255]
-// CHECK: [0x00,0x00,0x44,0xdd,0x01,0xfc,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[0:1], v[1:2], v[2:5] glc
-// CHECK: [0x00,0x00,0x45,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5] slc
-// CHECK: [0x00,0x00,0x46,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x48,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x48,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x48,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_add_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x49,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x4a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x4c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x4c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x4c,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_sub_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x4d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x4e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x54,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x54,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x54,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_smin_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x55,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x56,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x58,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x58,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x58,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_umin_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x59,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x5a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x5c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x5c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x5c,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_smax_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x5d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x5e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x60,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x60,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x60,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_umax_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x61,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x62,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x64,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x64,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x64,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_and_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x65,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x66,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x68,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x68,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x68,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_or_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x69,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x6a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x6c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x6c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x6c,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_xor_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x6d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x6e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x70,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x70,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x70,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_inc_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x71,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x72,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x74,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x74,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x74,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_dec_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x75,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x76,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fcmpswap_x2 v[1:2], v[2:5]
-// CHECK: [0x00,0x00,0x78,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fcmpswap_x2 v[254:255], v[2:5]
-// CHECK: [0x00,0x00,0x78,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_fcmpswap_x2 v[1:2], v[252:255]
-// CHECK: [0x00,0x00,0x78,0xdd,0x01,0xfc,0x00,0x00]
-
-flat_atomic_fcmpswap_x2 v[0:1], v[1:2], v[2:5] glc
-// CHECK: [0x00,0x00,0x79,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fcmpswap_x2 v[1:2], v[2:5] slc
-// CHECK: [0x00,0x00,0x7a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmin_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x7c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmin_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x7c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_fmin_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x7c,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_fmin_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x7d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmin_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x7e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmax_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmax_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x80,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_fmax_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x80,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_fmax_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x81,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_fmax_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x82,0xdd,0x01,0x02,0x00,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v252, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0xfc,0x02,0x00]
-
-image_load v5, v[252:255], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0xfc,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[12:19] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x03,0x00]
-
-image_load v5, v[1:4], s[96:103] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x18,0x00]
-
-image_load v5, v[1:4], ttmp[4:11] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x1d,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x2
-// CHECK: [0x00,0x02,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x3
-// CHECK: [0x00,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x4
-// CHECK: [0x00,0x04,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x5
-// CHECK: [0x00,0x05,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x6
-// CHECK: [0x00,0x06,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0x7
-// CHECK: [0x00,0x07,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x8
-// CHECK: [0x00,0x08,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x9
-// CHECK: [0x00,0x09,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x0
-// CHECK: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x02,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v252, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0xfc,0x02,0x00]
-
-image_load_mip v5, v[252:255], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0xfc,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[12:19] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x03,0x00]
-
-image_load_mip v5, v[1:4], s[96:103] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x18,0x00]
-
-image_load_mip v5, v[1:4], ttmp[4:11] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x1d,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x2
-// CHECK: [0x00,0x02,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x3
-// CHECK: [0x00,0x03,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x4
-// CHECK: [0x00,0x04,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x5
-// CHECK: [0x00,0x05,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x6
-// CHECK: [0x00,0x06,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0x7
-// CHECK: [0x00,0x07,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x8
-// CHECK: [0x00,0x08,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x9
-// CHECK: [0x00,0x09,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x0
-// CHECK: [0x00,0x00,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x06,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v252, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0xfc,0x03,0x00]
-
-image_store v1, v[252:255], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0xfc,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x04,0x00]
-
-image_store v1, v[2:5], s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x18,0x00]
-
-image_store v1, v[2:5], ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x1d,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x2 unorm
-// CHECK: [0x00,0x12,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x4 unorm
-// CHECK: [0x00,0x14,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x5 unorm
-// CHECK: [0x00,0x15,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x6 unorm
-// CHECK: [0x00,0x16,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0x7 unorm
-// CHECK: [0x00,0x17,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x8 unorm
-// CHECK: [0x00,0x18,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x9 unorm
-// CHECK: [0x00,0x19,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0xa unorm
-// CHECK: [0x00,0x1a,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0xb unorm
-// CHECK: [0x00,0x1b,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0xc unorm
-// CHECK: [0x00,0x1c,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0xd unorm
-// CHECK: [0x00,0x1d,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0xe unorm
-// CHECK: [0x00,0x1e,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:4], v[2:5], s[12:19] dmask:0xf unorm
-// CHECK: [0x00,0x1f,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x0 unorm
-// CHECK: [0x00,0x10,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x20,0xf2,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x22,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v252, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0xfc,0x03,0x00]
-
-image_store_mip v1, v[252:255], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0xfc,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x04,0x00]
-
-image_store_mip v1, v[2:5], s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x18,0x00]
-
-image_store_mip v1, v[2:5], ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x1d,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x2 unorm
-// CHECK: [0x00,0x12,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x4 unorm
-// CHECK: [0x00,0x14,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x5 unorm
-// CHECK: [0x00,0x15,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x6 unorm
-// CHECK: [0x00,0x16,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0x7 unorm
-// CHECK: [0x00,0x17,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x8 unorm
-// CHECK: [0x00,0x18,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x9 unorm
-// CHECK: [0x00,0x19,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0xa unorm
-// CHECK: [0x00,0x1a,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0xb unorm
-// CHECK: [0x00,0x1b,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0xc unorm
-// CHECK: [0x00,0x1c,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0xd unorm
-// CHECK: [0x00,0x1d,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0xe unorm
-// CHECK: [0x00,0x1e,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:4], v[2:5], s[12:19] dmask:0xf unorm
-// CHECK: [0x00,0x1f,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x0 unorm
-// CHECK: [0x00,0x10,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x24,0xf2,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x26,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v252, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0xfc,0x02,0x00]
-
-image_get_resinfo v5, v[252:255], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0xfc,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[12:19] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x03,0x00]
-
-image_get_resinfo v5, v[1:4], s[96:103] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x18,0x00]
-
-image_get_resinfo v5, v[1:4], ttmp[4:11] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x1d,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x2
-// CHECK: [0x00,0x02,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x3
-// CHECK: [0x00,0x03,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x4
-// CHECK: [0x00,0x04,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x5
-// CHECK: [0x00,0x05,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x6
-// CHECK: [0x00,0x06,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v[1:4], s[8:15] dmask:0x7
-// CHECK: [0x00,0x07,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x8
-// CHECK: [0x00,0x08,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x9
-// CHECK: [0x00,0x09,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v[1:4], s[8:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v[1:4], s[8:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v[1:4], s[8:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x0
-// CHECK: [0x00,0x00,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x3a,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_swap v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_swap v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x3c,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_swap v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_swap v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_swap v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_swap v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x3c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x3c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x3c,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x3e,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x3c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_cmpswap v[252:253], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x40,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_cmpswap v[1:2], v255, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x40,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_cmpswap v[1:2], v2, s[16:23] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_cmpswap v[1:2], v2, s[96:103] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_cmpswap v[1:2], v2, ttmp[4:11] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_cmpswap v[1:4], v2, s[12:19] dmask:0xf unorm
-// CHECK: [0x00,0x1f,0x40,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm glc
-// CHECK: [0x00,0x33,0x40,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm slc
-// CHECK: [0x00,0x13,0x40,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm lwe
-// CHECK: [0x00,0x13,0x42,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm da
-// CHECK: [0x00,0x53,0x40,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_add v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x44,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_add v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x44,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_add v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_add v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_add v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_add v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x44,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x44,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x46,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x44,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_sub v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_sub v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_sub v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_sub v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_sub v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_sub v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x48,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x48,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x48,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x4a,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x48,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smin v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_smin v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_smin v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_smin v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_smin v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_smin v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x50,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x50,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x50,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x52,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x50,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umin v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_umin v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_umin v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_umin v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_umin v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_umin v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x54,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x54,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x54,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x56,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x54,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smax v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_smax v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_smax v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_smax v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_smax v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_smax v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x58,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x58,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x58,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x5a,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x58,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umax v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_umax v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_umax v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_umax v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_umax v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_umax v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x5c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x5c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x5c,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x5e,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x5c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_and v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_and v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_and v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_and v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_and v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_and v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x60,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x60,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x60,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x62,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x60,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_or v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_or v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_or v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_or v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_or v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_or v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x64,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x64,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x64,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x66,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x64,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_xor v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_xor v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_xor v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_xor v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_xor v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_xor v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x68,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x68,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x68,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x6a,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x68,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_inc v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_inc v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_inc v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_inc v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_inc v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_inc v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x6c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x6c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x6c,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x6e,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x6c,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_dec v252, v2, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x02,0xfc,0x03,0x00]
-
-image_atomic_dec v1, v255, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0xff,0x01,0x03,0x00]
-
-image_atomic_dec v1, v2, s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x04,0x00]
-
-image_atomic_dec v1, v2, s[96:103] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x18,0x00]
-
-image_atomic_dec v1, v2, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x1d,0x00]
-
-image_atomic_dec v[1:2], v2, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x70,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x70,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x70,0xf2,0x02,0x01,0x03,0x00]
-
-image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x72,0xf0,0x02,0x01,0x03,0x00]
-
-image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x70,0xf0,0x02,0x01,0x03,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x80,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x81,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x82,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_cl v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x86,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_l v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_l v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_l v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_l v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x92,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_b v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_b v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_b v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_b v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x96,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_b_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_b_cl v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_b_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_b_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x98,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x99,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x9a,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_lz v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_lz v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_lz v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_lz v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x9c,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x9d,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x9e,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_c v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_c v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xa2,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_cl v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_c_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_c_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xa4,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xa5,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xa6,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_d v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_d v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_c_d v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_c_d v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xa8,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xa9,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xaa,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xa8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_l v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_l v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_c_l v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_c_l v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xb0,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xb1,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xb2,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_b v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_b v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_c_b v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_c_b v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xb4,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xb5,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xb6,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_b_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_c_b_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xb8,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xb9,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xba,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_lz v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_lz v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x78,0x00]
-
-image_sample_c_lz v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x22,0x03]
-
-image_sample_c_lz v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xbe,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[252:255], v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4 v[5:8], v255, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0xff,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4 v[5:8], v1, s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4 v[5:8], v1, ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4 v[5:8], v1, s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x00,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x02,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_cl v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x04,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x06,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_l v[5:8], v255, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0xff,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_l v[5:8], v1, ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x10,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x12,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_b v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_b v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x14,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x16,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x18,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x1a,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[252:255], v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_lz v[5:8], v255, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0xff,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_lz v[5:8], v1, s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_lz v[5:8], v1, ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_lz v[5:8], v1, s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x1c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x1e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x20,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x22,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x24,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x26,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x30,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x32,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x34,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x36,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x38,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x3a,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x3c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x3e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_o v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x40,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x42,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x44,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x46,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x50,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x52,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x54,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x56,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x58,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x5a,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x5c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x5e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x60,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x62,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x64,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x66,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x70,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x72,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x74,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x76,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[248:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0xf8,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x78,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x7a,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x78,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x22,0x03]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x7c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x7e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v252, v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0xfc,0x62,0x00]
-
-image_get_lod v5, v255, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0xff,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x63,0x00]
-
-image_get_lod v5, v1, s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x78,0x00]
-
-image_get_lod v5, v1, ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x7d,0x00]
-
-image_get_lod v5, v1, s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x82,0x00]
-
-image_get_lod v5, v1, s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x22,0x03]
-
-image_get_lod v5, v1, s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0xc2,0x03]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x80,0xf3,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x81,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x82,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0xfc,0x62,0x00]
-
-image_sample_c_cd v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf1,0xfc,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x63,0x00]
-
-image_sample_c_cd v5, v[1:4], s[96:103], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x78,0x00]
-
-image_sample_c_cd v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x7d,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x82,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[100:103] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x22,0x03]
-
-image_sample_c_cd v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0xc2,0x03]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xa8,0xf3,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xa9,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xaa,0xf1,0x01,0x05,0x62,0x00]
-
-image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xa8,0xf1,0x01,0x05,0x62,0x00]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_format_x v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_x v5, off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_format_x v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_format_x v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_x v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_x v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xy v[5:6], off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_format_xy v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0xfd,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_format_xyz v[5:7], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0xfc,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_format_xyzw v[5:8], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_format_x v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_x v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_format_x v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_format_x v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_x v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_x v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xy v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_format_xy v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0xfd,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_format_xyz v[1:3], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0xfc,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_format_xyzw v[1:4], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ubyte v5, off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_ubyte v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_ubyte v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ubyte v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ubyte v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ubyte v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ubyte v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ubyte v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x21,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sbyte v5, off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_sbyte v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_sbyte v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sbyte v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sbyte v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sbyte v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sbyte v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sbyte v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x25,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ushort v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ushort v5, off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_ushort v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_ushort v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ushort v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ushort v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ushort v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ushort v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x29,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sshort v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sshort v5, off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_sshort v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_sshort v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sshort v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sshort v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sshort v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sshort v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sshort v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x2d,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_dword v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dword v5, off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_dword v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_dword v5, off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_dword v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dword v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dword v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dword v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dword v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dword v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x30,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x31,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_dwordx2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x34,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[252:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0xfc,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_dwordx4 v[5:8], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x38,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[253:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0xfd,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[100:103], s3 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x19,0x03]
-
-buffer_load_dwordx3 v[5:7], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s103 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x67]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], v[0:1], s[8:11], s3 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x3c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x42,0x03]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_byte v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_byte v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_byte v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_byte v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_byte v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_byte v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_byte v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_byte v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_byte v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_byte v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_short v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_short v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_short v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_short v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_short v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_short v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_short v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_short v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_short v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_short v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_dword v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dword v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_dword v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_dword v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_dword v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dword v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dword v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dword v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dword v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dword v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_dwordx2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[252:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0xfc,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_dwordx4 v[1:4], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[253:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0xfd,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_store_dwordx3 v[1:3], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_swap v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_swap v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_swap v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_swap v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_swap v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_swap v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_swap v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_swap v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_swap v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xc0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xc0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xc0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xc0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xc0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xc0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xc0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_cmpswap v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xc4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xc4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xc4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0xc4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xc4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xc4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xc4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_add v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_add v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_add v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_add v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_add v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_add v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_add v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_add v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_add v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xc8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xc8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xc8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xc8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xc8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xc8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xc8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_sub v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_sub v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_sub v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_sub v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_sub v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_sub v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_sub v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_sub v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_sub v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xcc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xcc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xcc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xcc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xcc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xcc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xcc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_smin v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_smin v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_smin v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_smin v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_smin v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_smin v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_smin v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_smin v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_smin v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xd4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xd4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xd4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xd4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xd4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xd4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xd4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_umin v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_umin v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_umin v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_umin v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_umin v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_umin v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_umin v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_umin v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_umin v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xd8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xd8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xd8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xd8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xd8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xd8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xd8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_smax v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_smax v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_smax v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_smax v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_smax v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_smax v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_smax v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_smax v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_smax v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xdc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xdc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xdc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xdc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xdc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xdc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xdc,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_umax v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_umax v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_umax v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_umax v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_umax v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_umax v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_umax v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_umax v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_umax v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xe0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xe0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xe0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xe0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xe0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xe0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xe0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_and v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_and v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_and v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_and v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_and v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_and v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_and v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_and v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_and v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xe4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xe4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xe4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xe4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xe4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xe4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xe4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_or v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_or v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_or v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_or v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_or v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_or v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_or v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_or v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_or v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xe8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xe8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xe8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xe8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xe8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xe8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xe8,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_xor v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_xor v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_xor v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_xor v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_xor v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_xor v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_xor v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_xor v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_xor v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xec,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xec,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xec,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xec,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xec,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xec,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xec,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_inc v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_inc v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_inc v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_inc v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_inc v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_inc v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_inc v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_inc v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_inc v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xf0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xf0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xf0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xf0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xf0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xf0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xf0,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_dec v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_atomic_dec v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_atomic_dec v1, off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x19,0x04]
-
-buffer_atomic_dec v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_dec v1, off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x67]
-
-buffer_atomic_dec v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_dec v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_atomic_dec v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_dec v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0xf4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0xf4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec v1, v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0xf4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0xf4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0xf4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0xf4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0xf4,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x43,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_swap_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x40,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x40,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x40,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x40,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x40,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x40,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x40,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap_x2 v[252:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0xfc,0x03,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_cmpswap_x2 v[1:4], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x44,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x44,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x44,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x44,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x44,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x44,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x44,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_add_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x48,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x48,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x48,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x48,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x48,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x48,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x48,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_sub_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x4c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x4c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x4c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x4c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x4c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x4c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x4c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_smin_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x54,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x54,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x54,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x54,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x54,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x54,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x54,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_umin_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x58,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x58,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x58,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x58,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x58,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x58,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x58,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_smax_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x5c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x5c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x5c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x5c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x5c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x5c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x5c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_umax_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x60,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x60,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x60,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x60,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x60,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x60,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x60,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_and_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x64,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x64,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x64,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x64,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x64,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x64,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x64,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_or_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x68,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x68,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x68,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x68,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x68,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x68,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x68,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_xor_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x6c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x6c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x6c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x6c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x6c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x6c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x6c,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_inc_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x70,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x70,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x70,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x70,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x70,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x70,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x70,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec_x2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0xfe,0x03,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x04,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, s[100:103], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x19,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x1e,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], s103 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x67]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x7c]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x80]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0xc1]
-
-buffer_atomic_dec_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x74,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x74,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
-// CHECK: [0xff,0x8f,0x74,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x74,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x74,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x74,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x74,0xe1,0x00,0x01,0x03,0x04]
-
-buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x43,0x04]
-
-buffer_wbinvl1_vol
-// CHECK: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00]
-
-buffer_wbinvl1
-// CHECK: [0x00,0x00,0xc4,0xe1,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], s2
-// CHECK: [0x02,0x82,0x02,0xc0]
-
-s_load_dword s103, s[2:3], s2
-// CHECK: [0x02,0x82,0x33,0xc0]
-
-s_load_dword vcc_lo, s[2:3], s2
-// CHECK: [0x02,0x02,0x35,0xc0]
-
-s_load_dword vcc_hi, s[2:3], s2
-// CHECK: [0x02,0x82,0x35,0xc0]
-
-s_load_dword s5, s[4:5], s2
-// CHECK: [0x02,0x84,0x02,0xc0]
-
-s_load_dword s5, s[102:103], s2
-// CHECK: [0x02,0xe6,0x02,0xc0]
-
-s_load_dword s5, flat_scratch, s2
-// CHECK: [0x02,0xe8,0x02,0xc0]
-
-s_load_dword s5, vcc, s2
-// CHECK: [0x02,0xea,0x02,0xc0]
-
-s_load_dword s5, tba, s2
-// CHECK: [0x02,0xec,0x02,0xc0]
-
-s_load_dword s5, tma, s2
-// CHECK: [0x02,0xee,0x02,0xc0]
-
-s_load_dword s5, ttmp[10:11], s2
-// CHECK: [0x02,0xfa,0x02,0xc0]
-
-s_load_dword s5, s[2:3], s103
-// CHECK: [0x67,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], flat_scratch_lo
-// CHECK: [0x68,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], flat_scratch_hi
-// CHECK: [0x69,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], vcc_lo
-// CHECK: [0x6a,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], vcc_hi
-// CHECK: [0x6b,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], tba_lo
-// CHECK: [0x6c,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], tba_hi
-// CHECK: [0x6d,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], tma_lo
-// CHECK: [0x6e,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], tma_hi
-// CHECK: [0x6f,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], ttmp11
-// CHECK: [0x7b,0x82,0x02,0xc0]
-
-s_load_dword s5, s[2:3], 0xaf123456
-// CHECK: [0xff,0x82,0x02,0xc0,0x56,0x34,0x12,0xaf]
-
-s_load_dword s5, s[2:3], 0x3f717273
-// CHECK: [0xff,0x82,0x02,0xc0,0x73,0x72,0x71,0x3f]
-
-s_load_dword s5, s[2:3], 0x7f
-// CHECK: [0x7f,0x83,0x02,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x46,0xc0]
-
-s_load_dwordx2 s[102:103], s[2:3], s2
-// CHECK: [0x02,0x02,0x73,0xc0]
-
-s_load_dwordx2 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0x75,0xc0]
-
-s_load_dwordx2 s[10:11], s[4:5], s2
-// CHECK: [0x02,0x04,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[102:103], s2
-// CHECK: [0x02,0x66,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], flat_scratch, s2
-// CHECK: [0x02,0x68,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], vcc, s2
-// CHECK: [0x02,0x6a,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], tba, s2
-// CHECK: [0x02,0x6c,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], tma, s2
-// CHECK: [0x02,0x6e,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], ttmp[10:11], s2
-// CHECK: [0x02,0x7a,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], s103
-// CHECK: [0x67,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x68,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x69,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x6a,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x6b,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], tba_lo
-// CHECK: [0x6c,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], tba_hi
-// CHECK: [0x6d,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], tma_lo
-// CHECK: [0x6e,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], tma_hi
-// CHECK: [0x6f,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], ttmp11
-// CHECK: [0x7b,0x02,0x45,0xc0]
-
-s_load_dwordx2 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0xff,0x02,0x45,0xc0,0x56,0x34,0x12,0xaf]
-
-s_load_dwordx2 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0xff,0x02,0x45,0xc0,0x73,0x72,0x71,0x3f]
-
-s_load_dwordx2 s[10:11], s[2:3], 0x7f
-// CHECK: [0x7f,0x03,0x45,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[24:27], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0xc0]
-
-s_load_dwordx4 s[100:103], s[2:3], s2
-// CHECK: [0x02,0x02,0xb2,0xc0]
-
-s_load_dwordx4 s[20:23], s[4:5], s2
-// CHECK: [0x02,0x04,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[102:103], s2
-// CHECK: [0x02,0x66,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], flat_scratch, s2
-// CHECK: [0x02,0x68,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], vcc, s2
-// CHECK: [0x02,0x6a,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], tba, s2
-// CHECK: [0x02,0x6c,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], tma, s2
-// CHECK: [0x02,0x6e,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], ttmp[10:11], s2
-// CHECK: [0x02,0x7a,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], s103
-// CHECK: [0x67,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], flat_scratch_lo
-// CHECK: [0x68,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], flat_scratch_hi
-// CHECK: [0x69,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], vcc_lo
-// CHECK: [0x6a,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], vcc_hi
-// CHECK: [0x6b,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], tba_lo
-// CHECK: [0x6c,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], tba_hi
-// CHECK: [0x6d,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], tma_lo
-// CHECK: [0x6e,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], tma_hi
-// CHECK: [0x6f,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], ttmp11
-// CHECK: [0x7b,0x02,0x8a,0xc0]
-
-s_load_dwordx4 s[20:23], s[2:3], 0xaf123456
-// CHECK: [0xff,0x02,0x8a,0xc0,0x56,0x34,0x12,0xaf]
-
-s_load_dwordx4 s[20:23], s[2:3], 0x3f717273
-// CHECK: [0xff,0x02,0x8a,0xc0,0x73,0x72,0x71,0x3f]
-
-s_load_dwordx4 s[20:23], s[2:3], 0x7f
-// CHECK: [0x7f,0x03,0x8a,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], s2
-// CHECK: [0x02,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[24:31], s[2:3], s2
-// CHECK: [0x02,0x02,0xcc,0xc0]
-
-s_load_dwordx8 s[96:103], s[2:3], s2
-// CHECK: [0x02,0x02,0xf0,0xc0]
-
-s_load_dwordx8 s[20:27], s[4:5], s2
-// CHECK: [0x02,0x04,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[102:103], s2
-// CHECK: [0x02,0x66,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], flat_scratch, s2
-// CHECK: [0x02,0x68,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], vcc, s2
-// CHECK: [0x02,0x6a,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], tba, s2
-// CHECK: [0x02,0x6c,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], tma, s2
-// CHECK: [0x02,0x6e,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], ttmp[10:11], s2
-// CHECK: [0x02,0x7a,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], s103
-// CHECK: [0x67,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], flat_scratch_lo
-// CHECK: [0x68,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], flat_scratch_hi
-// CHECK: [0x69,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], vcc_lo
-// CHECK: [0x6a,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], vcc_hi
-// CHECK: [0x6b,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], tba_lo
-// CHECK: [0x6c,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], tba_hi
-// CHECK: [0x6d,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], tma_lo
-// CHECK: [0x6e,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], tma_hi
-// CHECK: [0x6f,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], ttmp11
-// CHECK: [0x7b,0x02,0xca,0xc0]
-
-s_load_dwordx8 s[20:27], s[2:3], 0xaf123456
-// CHECK: [0xff,0x02,0xca,0xc0,0x56,0x34,0x12,0xaf]
-
-s_load_dwordx8 s[20:27], s[2:3], 0x3f717273
-// CHECK: [0xff,0x02,0xca,0xc0,0x73,0x72,0x71,0x3f]
-
-s_load_dwordx8 s[20:27], s[2:3], 0x7f
-// CHECK: [0x7f,0x03,0xca,0xc0]
-
-s_load_dwordx16 s[20:35], s[2:3], s2
-// CHECK: [0x02,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[24:39], s[2:3], s2
-// CHECK: [0x02,0x02,0x0c,0xc1]
-
-s_load_dwordx16 s[88:103], s[2:3], s2
-// CHECK: [0x02,0x02,0x2c,0xc1]
-
-s_load_dwordx16 s[20:35], s[4:5], s2
-// CHECK: [0x02,0x04,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[102:103], s2
-// CHECK: [0x02,0x66,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], flat_scratch, s2
-// CHECK: [0x02,0x68,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], vcc, s2
-// CHECK: [0x02,0x6a,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], tba, s2
-// CHECK: [0x02,0x6c,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], tma, s2
-// CHECK: [0x02,0x6e,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], ttmp[10:11], s2
-// CHECK: [0x02,0x7a,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], s103
-// CHECK: [0x67,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], flat_scratch_lo
-// CHECK: [0x68,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], flat_scratch_hi
-// CHECK: [0x69,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], vcc_lo
-// CHECK: [0x6a,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], vcc_hi
-// CHECK: [0x6b,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], tba_lo
-// CHECK: [0x6c,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], tba_hi
-// CHECK: [0x6d,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], tma_lo
-// CHECK: [0x6e,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], tma_hi
-// CHECK: [0x6f,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], ttmp11
-// CHECK: [0x7b,0x02,0x0a,0xc1]
-
-s_load_dwordx16 s[20:35], s[2:3], 0xaf123456
-// CHECK: [0xff,0x02,0x0a,0xc1,0x56,0x34,0x12,0xaf]
-
-s_load_dwordx16 s[20:35], s[2:3], 0x3f717273
-// CHECK: [0xff,0x02,0x0a,0xc1,0x73,0x72,0x71,0x3f]
-
-s_load_dwordx16 s[20:35], s[2:3], 0x7f
-// CHECK: [0x7f,0x03,0x0a,0xc1]
-
-s_buffer_load_dword s5, s[4:7], s2
-// CHECK: [0x02,0x84,0x02,0xc2]
-
-s_buffer_load_dword s103, s[4:7], s2
-// CHECK: [0x02,0x84,0x33,0xc2]
-
-s_buffer_load_dword vcc_lo, s[4:7], s2
-// CHECK: [0x02,0x04,0x35,0xc2]
-
-s_buffer_load_dword vcc_hi, s[4:7], s2
-// CHECK: [0x02,0x84,0x35,0xc2]
-
-s_buffer_load_dword s5, s[8:11], s2
-// CHECK: [0x02,0x88,0x02,0xc2]
-
-s_buffer_load_dword s5, s[100:103], s2
-// CHECK: [0x02,0xe4,0x02,0xc2]
-
-s_buffer_load_dword s5, ttmp[8:11], s2
-// CHECK: [0x02,0xf8,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], s103
-// CHECK: [0x67,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], flat_scratch_lo
-// CHECK: [0x68,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], flat_scratch_hi
-// CHECK: [0x69,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], vcc_lo
-// CHECK: [0x6a,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], vcc_hi
-// CHECK: [0x6b,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], tba_lo
-// CHECK: [0x6c,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], tba_hi
-// CHECK: [0x6d,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], tma_lo
-// CHECK: [0x6e,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], tma_hi
-// CHECK: [0x6f,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], ttmp11
-// CHECK: [0x7b,0x84,0x02,0xc2]
-
-s_buffer_load_dword s5, s[4:7], 0xaf123456
-// CHECK: [0xff,0x84,0x02,0xc2,0x56,0x34,0x12,0xaf]
-
-s_buffer_load_dword s5, s[4:7], 0x3f717273
-// CHECK: [0xff,0x84,0x02,0xc2,0x73,0x72,0x71,0x3f]
-
-s_buffer_load_dword s5, s[4:7], 0x7f
-// CHECK: [0x7f,0x85,0x02,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s2
-// CHECK: [0x02,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[12:13], s[4:7], s2
-// CHECK: [0x02,0x04,0x46,0xc2]
-
-s_buffer_load_dwordx2 s[102:103], s[4:7], s2
-// CHECK: [0x02,0x04,0x73,0xc2]
-
-s_buffer_load_dwordx2 vcc, s[4:7], s2
-// CHECK: [0x02,0x04,0x75,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[8:11], s2
-// CHECK: [0x02,0x08,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[100:103], s2
-// CHECK: [0x02,0x64,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], ttmp[8:11], s2
-// CHECK: [0x02,0x78,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s103
-// CHECK: [0x67,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_lo
-// CHECK: [0x68,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_hi
-// CHECK: [0x69,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_lo
-// CHECK: [0x6a,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
-// CHECK: [0x6b,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], tba_lo
-// CHECK: [0x6c,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], tba_hi
-// CHECK: [0x6d,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], tma_lo
-// CHECK: [0x6e,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], tma_hi
-// CHECK: [0x6f,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], ttmp11
-// CHECK: [0x7b,0x04,0x45,0xc2]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], 0xaf123456
-// CHECK: [0xff,0x04,0x45,0xc2,0x56,0x34,0x12,0xaf]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], 0x3f717273
-// CHECK: [0xff,0x04,0x45,0xc2,0x73,0x72,0x71,0x3f]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], 0x7f
-// CHECK: [0x7f,0x05,0x45,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s2
-// CHECK: [0x02,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[24:27], s[4:7], s2
-// CHECK: [0x02,0x04,0x8c,0xc2]
-
-s_buffer_load_dwordx4 s[100:103], s[4:7], s2
-// CHECK: [0x02,0x04,0xb2,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[8:11], s2
-// CHECK: [0x02,0x08,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[100:103], s2
-// CHECK: [0x02,0x64,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], ttmp[8:11], s2
-// CHECK: [0x02,0x78,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s103
-// CHECK: [0x67,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_lo
-// CHECK: [0x68,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_hi
-// CHECK: [0x69,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_lo
-// CHECK: [0x6a,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
-// CHECK: [0x6b,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], tba_lo
-// CHECK: [0x6c,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], tba_hi
-// CHECK: [0x6d,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], tma_lo
-// CHECK: [0x6e,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], tma_hi
-// CHECK: [0x6f,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], ttmp11
-// CHECK: [0x7b,0x04,0x8a,0xc2]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], 0xaf123456
-// CHECK: [0xff,0x04,0x8a,0xc2,0x56,0x34,0x12,0xaf]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], 0x3f717273
-// CHECK: [0xff,0x04,0x8a,0xc2,0x73,0x72,0x71,0x3f]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], 0x7f
-// CHECK: [0x7f,0x05,0x8a,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s2
-// CHECK: [0x02,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[24:31], s[4:7], s2
-// CHECK: [0x02,0x04,0xcc,0xc2]
-
-s_buffer_load_dwordx8 s[96:103], s[4:7], s2
-// CHECK: [0x02,0x04,0xf0,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[8:11], s2
-// CHECK: [0x02,0x08,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[100:103], s2
-// CHECK: [0x02,0x64,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], ttmp[8:11], s2
-// CHECK: [0x02,0x78,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s103
-// CHECK: [0x67,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_lo
-// CHECK: [0x68,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_hi
-// CHECK: [0x69,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_lo
-// CHECK: [0x6a,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
-// CHECK: [0x6b,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], tba_lo
-// CHECK: [0x6c,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], tba_hi
-// CHECK: [0x6d,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], tma_lo
-// CHECK: [0x6e,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], tma_hi
-// CHECK: [0x6f,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], ttmp11
-// CHECK: [0x7b,0x04,0xca,0xc2]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], 0xaf123456
-// CHECK: [0xff,0x04,0xca,0xc2,0x56,0x34,0x12,0xaf]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], 0x3f717273
-// CHECK: [0xff,0x04,0xca,0xc2,0x73,0x72,0x71,0x3f]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], 0x7f
-// CHECK: [0x7f,0x05,0xca,0xc2]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s2
-// CHECK: [0x02,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[24:39], s[4:7], s2
-// CHECK: [0x02,0x04,0x0c,0xc3]
-
-s_buffer_load_dwordx16 s[88:103], s[4:7], s2
-// CHECK: [0x02,0x04,0x2c,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[8:11], s2
-// CHECK: [0x02,0x08,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[100:103], s2
-// CHECK: [0x02,0x64,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], ttmp[8:11], s2
-// CHECK: [0x02,0x78,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s103
-// CHECK: [0x67,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_lo
-// CHECK: [0x68,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_hi
-// CHECK: [0x69,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_lo
-// CHECK: [0x6a,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
-// CHECK: [0x6b,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], tba_lo
-// CHECK: [0x6c,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], tba_hi
-// CHECK: [0x6d,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], tma_lo
-// CHECK: [0x6e,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], tma_hi
-// CHECK: [0x6f,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], ttmp11
-// CHECK: [0x7b,0x04,0x0a,0xc3]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], 0xaf123456
-// CHECK: [0xff,0x04,0x0a,0xc3,0x56,0x34,0x12,0xaf]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], 0x3f717273
-// CHECK: [0xff,0x04,0x0a,0xc3,0x73,0x72,0x71,0x3f]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], 0x7f
-// CHECK: [0x7f,0x05,0x0a,0xc3]
-
-s_dcache_inv_vol
-// CHECK: [0x00,0x00,0x40,0xc7]
-
-s_memtime s[10:11]
-// CHECK: [0x00,0x00,0x85,0xc7]
-
-s_memtime s[12:13]
-// CHECK: [0x00,0x00,0x86,0xc7]
-
-s_memtime s[102:103]
-// CHECK: [0x00,0x00,0xb3,0xc7]
-
-s_memtime vcc
-// CHECK: [0x00,0x00,0xb5,0xc7]
-
-s_dcache_inv
-// CHECK: [0x00,0x00,0xc0,0xc7]
-
-s_mov_b32 s5, s1
-// CHECK: [0x01,0x03,0x85,0xbe]
-
-s_mov_b32 s103, s1
-// CHECK: [0x01,0x03,0xe7,0xbe]
-
-s_mov_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x03,0xe8,0xbe]
-
-s_mov_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x03,0xe9,0xbe]
-
-s_mov_b32 vcc_lo, s1
-// CHECK: [0x01,0x03,0xea,0xbe]
-
-s_mov_b32 vcc_hi, s1
-// CHECK: [0x01,0x03,0xeb,0xbe]
-
-s_mov_b32 tba_lo, s1
-// CHECK: [0x01,0x03,0xec,0xbe]
-
-s_mov_b32 tba_hi, s1
-// CHECK: [0x01,0x03,0xed,0xbe]
-
-s_mov_b32 tma_lo, s1
-// CHECK: [0x01,0x03,0xee,0xbe]
-
-s_mov_b32 tma_hi, s1
-// CHECK: [0x01,0x03,0xef,0xbe]
-
-s_mov_b32 ttmp11, s1
-// CHECK: [0x01,0x03,0xfb,0xbe]
-
-s_mov_b32 m0, s1
-// CHECK: [0x01,0x03,0xfc,0xbe]
-
-s_mov_b32 exec_lo, s1
-// CHECK: [0x01,0x03,0xfe,0xbe]
-
-s_mov_b32 exec_hi, s1
-// CHECK: [0x01,0x03,0xff,0xbe]
-
-s_mov_b32 s5, s103
-// CHECK: [0x67,0x03,0x85,0xbe]
-
-s_mov_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x03,0x85,0xbe]
-
-s_mov_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x03,0x85,0xbe]
-
-s_mov_b32 s5, vcc_lo
-// CHECK: [0x6a,0x03,0x85,0xbe]
-
-s_mov_b32 s5, vcc_hi
-// CHECK: [0x6b,0x03,0x85,0xbe]
-
-s_mov_b32 s5, tba_lo
-// CHECK: [0x6c,0x03,0x85,0xbe]
-
-s_mov_b32 s5, tba_hi
-// CHECK: [0x6d,0x03,0x85,0xbe]
-
-s_mov_b32 s5, tma_lo
-// CHECK: [0x6e,0x03,0x85,0xbe]
-
-s_mov_b32 s5, tma_hi
-// CHECK: [0x6f,0x03,0x85,0xbe]
-
-s_mov_b32 s5, ttmp11
-// CHECK: [0x7b,0x03,0x85,0xbe]
-
-s_mov_b32 s5, m0
-// CHECK: [0x7c,0x03,0x85,0xbe]
-
-s_mov_b32 s5, exec_lo
-// CHECK: [0x7e,0x03,0x85,0xbe]
-
-s_mov_b32 s5, exec_hi
-// CHECK: [0x7f,0x03,0x85,0xbe]
-
-s_mov_b32 s5, 0
-// CHECK: [0x80,0x03,0x85,0xbe]
-
-s_mov_b32 s5, -1
-// CHECK: [0xc1,0x03,0x85,0xbe]
-
-s_mov_b32 s5, 0.5
-// CHECK: [0xf0,0x03,0x85,0xbe]
-
-s_mov_b32 s5, -4.0
-// CHECK: [0xf7,0x03,0x85,0xbe]
-
-s_mov_b32 s5, 0xaf123456
-// CHECK: [0xff,0x03,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_mov_b32 s5, 0x3f717273
-// CHECK: [0xff,0x03,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_mov_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x04,0x8a,0xbe]
-
-s_mov_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x04,0x8c,0xbe]
-
-s_mov_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x04,0xe6,0xbe]
-
-s_mov_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x04,0xe8,0xbe]
-
-s_mov_b64 vcc, s[2:3]
-// CHECK: [0x02,0x04,0xea,0xbe]
-
-s_mov_b64 tba, s[2:3]
-// CHECK: [0x02,0x04,0xec,0xbe]
-
-s_mov_b64 tma, s[2:3]
-// CHECK: [0x02,0x04,0xee,0xbe]
-
-s_mov_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x04,0xfa,0xbe]
-
-s_mov_b64 exec, s[2:3]
-// CHECK: [0x02,0x04,0xfe,0xbe]
-
-s_mov_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], vcc
-// CHECK: [0x6a,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], tba
-// CHECK: [0x6c,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], tma
-// CHECK: [0x6e,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], exec
-// CHECK: [0x7e,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], 0
-// CHECK: [0x80,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], -1
-// CHECK: [0xc1,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x04,0x8a,0xbe]
-
-s_mov_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x04,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_mov_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x04,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cmov_b32 s5, s1
-// CHECK: [0x01,0x05,0x85,0xbe]
-
-s_cmov_b32 s103, s1
-// CHECK: [0x01,0x05,0xe7,0xbe]
-
-s_cmov_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x05,0xe8,0xbe]
-
-s_cmov_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x05,0xe9,0xbe]
-
-s_cmov_b32 vcc_lo, s1
-// CHECK: [0x01,0x05,0xea,0xbe]
-
-s_cmov_b32 vcc_hi, s1
-// CHECK: [0x01,0x05,0xeb,0xbe]
-
-s_cmov_b32 tba_lo, s1
-// CHECK: [0x01,0x05,0xec,0xbe]
-
-s_cmov_b32 tba_hi, s1
-// CHECK: [0x01,0x05,0xed,0xbe]
-
-s_cmov_b32 tma_lo, s1
-// CHECK: [0x01,0x05,0xee,0xbe]
-
-s_cmov_b32 tma_hi, s1
-// CHECK: [0x01,0x05,0xef,0xbe]
-
-s_cmov_b32 ttmp11, s1
-// CHECK: [0x01,0x05,0xfb,0xbe]
-
-s_cmov_b32 m0, s1
-// CHECK: [0x01,0x05,0xfc,0xbe]
-
-s_cmov_b32 exec_lo, s1
-// CHECK: [0x01,0x05,0xfe,0xbe]
-
-s_cmov_b32 exec_hi, s1
-// CHECK: [0x01,0x05,0xff,0xbe]
-
-s_cmov_b32 s5, s103
-// CHECK: [0x67,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, vcc_lo
-// CHECK: [0x6a,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, vcc_hi
-// CHECK: [0x6b,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, tba_lo
-// CHECK: [0x6c,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, tba_hi
-// CHECK: [0x6d,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, tma_lo
-// CHECK: [0x6e,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, tma_hi
-// CHECK: [0x6f,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, ttmp11
-// CHECK: [0x7b,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, m0
-// CHECK: [0x7c,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, exec_lo
-// CHECK: [0x7e,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, exec_hi
-// CHECK: [0x7f,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, 0
-// CHECK: [0x80,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, -1
-// CHECK: [0xc1,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, 0.5
-// CHECK: [0xf0,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, -4.0
-// CHECK: [0xf7,0x05,0x85,0xbe]
-
-s_cmov_b32 s5, 0xaf123456
-// CHECK: [0xff,0x05,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_cmov_b32 s5, 0x3f717273
-// CHECK: [0xff,0x05,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cmov_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x06,0x8c,0xbe]
-
-s_cmov_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x06,0xe6,0xbe]
-
-s_cmov_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x06,0xe8,0xbe]
-
-s_cmov_b64 vcc, s[2:3]
-// CHECK: [0x02,0x06,0xea,0xbe]
-
-s_cmov_b64 tba, s[2:3]
-// CHECK: [0x02,0x06,0xec,0xbe]
-
-s_cmov_b64 tma, s[2:3]
-// CHECK: [0x02,0x06,0xee,0xbe]
-
-s_cmov_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x06,0xfa,0xbe]
-
-s_cmov_b64 exec, s[2:3]
-// CHECK: [0x02,0x06,0xfe,0xbe]
-
-s_cmov_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], vcc
-// CHECK: [0x6a,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], tba
-// CHECK: [0x6c,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], tma
-// CHECK: [0x6e,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], exec
-// CHECK: [0x7e,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], 0
-// CHECK: [0x80,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], -1
-// CHECK: [0xc1,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x06,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x06,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_cmov_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x06,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_not_b32 s5, s1
-// CHECK: [0x01,0x07,0x85,0xbe]
-
-s_not_b32 s103, s1
-// CHECK: [0x01,0x07,0xe7,0xbe]
-
-s_not_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x07,0xe8,0xbe]
-
-s_not_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x07,0xe9,0xbe]
-
-s_not_b32 vcc_lo, s1
-// CHECK: [0x01,0x07,0xea,0xbe]
-
-s_not_b32 vcc_hi, s1
-// CHECK: [0x01,0x07,0xeb,0xbe]
-
-s_not_b32 tba_lo, s1
-// CHECK: [0x01,0x07,0xec,0xbe]
-
-s_not_b32 tba_hi, s1
-// CHECK: [0x01,0x07,0xed,0xbe]
-
-s_not_b32 tma_lo, s1
-// CHECK: [0x01,0x07,0xee,0xbe]
-
-s_not_b32 tma_hi, s1
-// CHECK: [0x01,0x07,0xef,0xbe]
-
-s_not_b32 ttmp11, s1
-// CHECK: [0x01,0x07,0xfb,0xbe]
-
-s_not_b32 m0, s1
-// CHECK: [0x01,0x07,0xfc,0xbe]
-
-s_not_b32 exec_lo, s1
-// CHECK: [0x01,0x07,0xfe,0xbe]
-
-s_not_b32 exec_hi, s1
-// CHECK: [0x01,0x07,0xff,0xbe]
-
-s_not_b32 s5, s103
-// CHECK: [0x67,0x07,0x85,0xbe]
-
-s_not_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x07,0x85,0xbe]
-
-s_not_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x07,0x85,0xbe]
-
-s_not_b32 s5, vcc_lo
-// CHECK: [0x6a,0x07,0x85,0xbe]
-
-s_not_b32 s5, vcc_hi
-// CHECK: [0x6b,0x07,0x85,0xbe]
-
-s_not_b32 s5, tba_lo
-// CHECK: [0x6c,0x07,0x85,0xbe]
-
-s_not_b32 s5, tba_hi
-// CHECK: [0x6d,0x07,0x85,0xbe]
-
-s_not_b32 s5, tma_lo
-// CHECK: [0x6e,0x07,0x85,0xbe]
-
-s_not_b32 s5, tma_hi
-// CHECK: [0x6f,0x07,0x85,0xbe]
-
-s_not_b32 s5, ttmp11
-// CHECK: [0x7b,0x07,0x85,0xbe]
-
-s_not_b32 s5, m0
-// CHECK: [0x7c,0x07,0x85,0xbe]
-
-s_not_b32 s5, exec_lo
-// CHECK: [0x7e,0x07,0x85,0xbe]
-
-s_not_b32 s5, exec_hi
-// CHECK: [0x7f,0x07,0x85,0xbe]
-
-s_not_b32 s5, 0
-// CHECK: [0x80,0x07,0x85,0xbe]
-
-s_not_b32 s5, -1
-// CHECK: [0xc1,0x07,0x85,0xbe]
-
-s_not_b32 s5, 0.5
-// CHECK: [0xf0,0x07,0x85,0xbe]
-
-s_not_b32 s5, -4.0
-// CHECK: [0xf7,0x07,0x85,0xbe]
-
-s_not_b32 s5, 0xaf123456
-// CHECK: [0xff,0x07,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_not_b32 s5, 0x3f717273
-// CHECK: [0xff,0x07,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_not_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x08,0x8a,0xbe]
-
-s_not_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x08,0x8c,0xbe]
-
-s_not_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x08,0xe6,0xbe]
-
-s_not_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x08,0xe8,0xbe]
-
-s_not_b64 vcc, s[2:3]
-// CHECK: [0x02,0x08,0xea,0xbe]
-
-s_not_b64 tba, s[2:3]
-// CHECK: [0x02,0x08,0xec,0xbe]
-
-s_not_b64 tma, s[2:3]
-// CHECK: [0x02,0x08,0xee,0xbe]
-
-s_not_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x08,0xfa,0xbe]
-
-s_not_b64 exec, s[2:3]
-// CHECK: [0x02,0x08,0xfe,0xbe]
-
-s_not_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], vcc
-// CHECK: [0x6a,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], tba
-// CHECK: [0x6c,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], tma
-// CHECK: [0x6e,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], exec
-// CHECK: [0x7e,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], 0
-// CHECK: [0x80,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], -1
-// CHECK: [0xc1,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x08,0x8a,0xbe]
-
-s_not_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x08,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_not_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x08,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_wqm_b32 s5, s1
-// CHECK: [0x01,0x09,0x85,0xbe]
-
-s_wqm_b32 s103, s1
-// CHECK: [0x01,0x09,0xe7,0xbe]
-
-s_wqm_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x09,0xe8,0xbe]
-
-s_wqm_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x09,0xe9,0xbe]
-
-s_wqm_b32 vcc_lo, s1
-// CHECK: [0x01,0x09,0xea,0xbe]
-
-s_wqm_b32 vcc_hi, s1
-// CHECK: [0x01,0x09,0xeb,0xbe]
-
-s_wqm_b32 tba_lo, s1
-// CHECK: [0x01,0x09,0xec,0xbe]
-
-s_wqm_b32 tba_hi, s1
-// CHECK: [0x01,0x09,0xed,0xbe]
-
-s_wqm_b32 tma_lo, s1
-// CHECK: [0x01,0x09,0xee,0xbe]
-
-s_wqm_b32 tma_hi, s1
-// CHECK: [0x01,0x09,0xef,0xbe]
-
-s_wqm_b32 ttmp11, s1
-// CHECK: [0x01,0x09,0xfb,0xbe]
-
-s_wqm_b32 m0, s1
-// CHECK: [0x01,0x09,0xfc,0xbe]
-
-s_wqm_b32 exec_lo, s1
-// CHECK: [0x01,0x09,0xfe,0xbe]
-
-s_wqm_b32 exec_hi, s1
-// CHECK: [0x01,0x09,0xff,0xbe]
-
-s_wqm_b32 s5, s103
-// CHECK: [0x67,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, vcc_lo
-// CHECK: [0x6a,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, vcc_hi
-// CHECK: [0x6b,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, tba_lo
-// CHECK: [0x6c,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, tba_hi
-// CHECK: [0x6d,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, tma_lo
-// CHECK: [0x6e,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, tma_hi
-// CHECK: [0x6f,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, ttmp11
-// CHECK: [0x7b,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, m0
-// CHECK: [0x7c,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, exec_lo
-// CHECK: [0x7e,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, exec_hi
-// CHECK: [0x7f,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, 0
-// CHECK: [0x80,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, -1
-// CHECK: [0xc1,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, 0.5
-// CHECK: [0xf0,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, -4.0
-// CHECK: [0xf7,0x09,0x85,0xbe]
-
-s_wqm_b32 s5, 0xaf123456
-// CHECK: [0xff,0x09,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_wqm_b32 s5, 0x3f717273
-// CHECK: [0xff,0x09,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_wqm_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x0a,0x8c,0xbe]
-
-s_wqm_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x0a,0xe6,0xbe]
-
-s_wqm_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x0a,0xe8,0xbe]
-
-s_wqm_b64 vcc, s[2:3]
-// CHECK: [0x02,0x0a,0xea,0xbe]
-
-s_wqm_b64 tba, s[2:3]
-// CHECK: [0x02,0x0a,0xec,0xbe]
-
-s_wqm_b64 tma, s[2:3]
-// CHECK: [0x02,0x0a,0xee,0xbe]
-
-s_wqm_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x0a,0xfa,0xbe]
-
-s_wqm_b64 exec, s[2:3]
-// CHECK: [0x02,0x0a,0xfe,0xbe]
-
-s_wqm_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], vcc
-// CHECK: [0x6a,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], tba
-// CHECK: [0x6c,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], tma
-// CHECK: [0x6e,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], exec
-// CHECK: [0x7e,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], 0
-// CHECK: [0x80,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], -1
-// CHECK: [0xc1,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x0a,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x0a,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_wqm_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x0a,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_brev_b32 s5, s1
-// CHECK: [0x01,0x0b,0x85,0xbe]
-
-s_brev_b32 s103, s1
-// CHECK: [0x01,0x0b,0xe7,0xbe]
-
-s_brev_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x0b,0xe8,0xbe]
-
-s_brev_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x0b,0xe9,0xbe]
-
-s_brev_b32 vcc_lo, s1
-// CHECK: [0x01,0x0b,0xea,0xbe]
-
-s_brev_b32 vcc_hi, s1
-// CHECK: [0x01,0x0b,0xeb,0xbe]
-
-s_brev_b32 tba_lo, s1
-// CHECK: [0x01,0x0b,0xec,0xbe]
-
-s_brev_b32 tba_hi, s1
-// CHECK: [0x01,0x0b,0xed,0xbe]
-
-s_brev_b32 tma_lo, s1
-// CHECK: [0x01,0x0b,0xee,0xbe]
-
-s_brev_b32 tma_hi, s1
-// CHECK: [0x01,0x0b,0xef,0xbe]
-
-s_brev_b32 ttmp11, s1
-// CHECK: [0x01,0x0b,0xfb,0xbe]
-
-s_brev_b32 m0, s1
-// CHECK: [0x01,0x0b,0xfc,0xbe]
-
-s_brev_b32 exec_lo, s1
-// CHECK: [0x01,0x0b,0xfe,0xbe]
-
-s_brev_b32 exec_hi, s1
-// CHECK: [0x01,0x0b,0xff,0xbe]
-
-s_brev_b32 s5, s103
-// CHECK: [0x67,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, vcc_lo
-// CHECK: [0x6a,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, vcc_hi
-// CHECK: [0x6b,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, tba_lo
-// CHECK: [0x6c,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, tba_hi
-// CHECK: [0x6d,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, tma_lo
-// CHECK: [0x6e,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, tma_hi
-// CHECK: [0x6f,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, ttmp11
-// CHECK: [0x7b,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, m0
-// CHECK: [0x7c,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, exec_lo
-// CHECK: [0x7e,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, exec_hi
-// CHECK: [0x7f,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, 0
-// CHECK: [0x80,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, -1
-// CHECK: [0xc1,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, 0.5
-// CHECK: [0xf0,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, -4.0
-// CHECK: [0xf7,0x0b,0x85,0xbe]
-
-s_brev_b32 s5, 0xaf123456
-// CHECK: [0xff,0x0b,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_brev_b32 s5, 0x3f717273
-// CHECK: [0xff,0x0b,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_brev_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x0c,0x8c,0xbe]
-
-s_brev_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x0c,0xe6,0xbe]
-
-s_brev_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x0c,0xe8,0xbe]
-
-s_brev_b64 vcc, s[2:3]
-// CHECK: [0x02,0x0c,0xea,0xbe]
-
-s_brev_b64 tba, s[2:3]
-// CHECK: [0x02,0x0c,0xec,0xbe]
-
-s_brev_b64 tma, s[2:3]
-// CHECK: [0x02,0x0c,0xee,0xbe]
-
-s_brev_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x0c,0xfa,0xbe]
-
-s_brev_b64 exec, s[2:3]
-// CHECK: [0x02,0x0c,0xfe,0xbe]
-
-s_brev_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], vcc
-// CHECK: [0x6a,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], tba
-// CHECK: [0x6c,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], tma
-// CHECK: [0x6e,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], exec
-// CHECK: [0x7e,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], 0
-// CHECK: [0x80,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], -1
-// CHECK: [0xc1,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x0c,0x8a,0xbe]
-
-s_brev_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x0c,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_brev_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x0c,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt0_i32_b32 s5, s1
-// CHECK: [0x01,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s103, s1
-// CHECK: [0x01,0x0d,0xe7,0xbe]
-
-s_bcnt0_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x0d,0xe8,0xbe]
-
-s_bcnt0_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x0d,0xe9,0xbe]
-
-s_bcnt0_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x0d,0xea,0xbe]
-
-s_bcnt0_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x0d,0xeb,0xbe]
-
-s_bcnt0_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x0d,0xec,0xbe]
-
-s_bcnt0_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x0d,0xed,0xbe]
-
-s_bcnt0_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x0d,0xee,0xbe]
-
-s_bcnt0_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x0d,0xef,0xbe]
-
-s_bcnt0_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x0d,0xfb,0xbe]
-
-s_bcnt0_i32_b32 m0, s1
-// CHECK: [0x01,0x0d,0xfc,0xbe]
-
-s_bcnt0_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x0d,0xfe,0xbe]
-
-s_bcnt0_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x0d,0xff,0xbe]
-
-s_bcnt0_i32_b32 s5, s103
-// CHECK: [0x67,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, m0
-// CHECK: [0x7c,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, 0
-// CHECK: [0x80,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, -1
-// CHECK: [0xc1,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x0d,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x0d,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt0_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x0d,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt0_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s103, s[2:3]
-// CHECK: [0x02,0x0e,0xe7,0xbe]
-
-s_bcnt0_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x0e,0xe8,0xbe]
-
-s_bcnt0_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x0e,0xe9,0xbe]
-
-s_bcnt0_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x0e,0xea,0xbe]
-
-s_bcnt0_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x0e,0xeb,0xbe]
-
-s_bcnt0_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x0e,0xec,0xbe]
-
-s_bcnt0_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x0e,0xed,0xbe]
-
-s_bcnt0_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x0e,0xee,0xbe]
-
-s_bcnt0_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x0e,0xef,0xbe]
-
-s_bcnt0_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x0e,0xfb,0xbe]
-
-s_bcnt0_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x0e,0xfc,0xbe]
-
-s_bcnt0_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x0e,0xfe,0xbe]
-
-s_bcnt0_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x0e,0xff,0xbe]
-
-s_bcnt0_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, s[102:103]
-// CHECK: [0x66,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, flat_scratch
-// CHECK: [0x68,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, vcc
-// CHECK: [0x6a,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, tba
-// CHECK: [0x6c,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, tma
-// CHECK: [0x6e,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, exec
-// CHECK: [0x7e,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, 0
-// CHECK: [0x80,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, -1
-// CHECK: [0xc1,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x0e,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x0e,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt0_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x0e,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt1_i32_b32 s5, s1
-// CHECK: [0x01,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s103, s1
-// CHECK: [0x01,0x0f,0xe7,0xbe]
-
-s_bcnt1_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x0f,0xe8,0xbe]
-
-s_bcnt1_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x0f,0xe9,0xbe]
-
-s_bcnt1_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x0f,0xea,0xbe]
-
-s_bcnt1_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x0f,0xeb,0xbe]
-
-s_bcnt1_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x0f,0xec,0xbe]
-
-s_bcnt1_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x0f,0xed,0xbe]
-
-s_bcnt1_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x0f,0xee,0xbe]
-
-s_bcnt1_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x0f,0xef,0xbe]
-
-s_bcnt1_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x0f,0xfb,0xbe]
-
-s_bcnt1_i32_b32 m0, s1
-// CHECK: [0x01,0x0f,0xfc,0xbe]
-
-s_bcnt1_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x0f,0xfe,0xbe]
-
-s_bcnt1_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x0f,0xff,0xbe]
-
-s_bcnt1_i32_b32 s5, s103
-// CHECK: [0x67,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, m0
-// CHECK: [0x7c,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, 0
-// CHECK: [0x80,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, -1
-// CHECK: [0xc1,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x0f,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x0f,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt1_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x0f,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt1_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s103, s[2:3]
-// CHECK: [0x02,0x10,0xe7,0xbe]
-
-s_bcnt1_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x10,0xe8,0xbe]
-
-s_bcnt1_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x10,0xe9,0xbe]
-
-s_bcnt1_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x10,0xea,0xbe]
-
-s_bcnt1_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x10,0xeb,0xbe]
-
-s_bcnt1_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x10,0xec,0xbe]
-
-s_bcnt1_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x10,0xed,0xbe]
-
-s_bcnt1_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x10,0xee,0xbe]
-
-s_bcnt1_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x10,0xef,0xbe]
-
-s_bcnt1_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x10,0xfb,0xbe]
-
-s_bcnt1_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x10,0xfc,0xbe]
-
-s_bcnt1_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x10,0xfe,0xbe]
-
-s_bcnt1_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x10,0xff,0xbe]
-
-s_bcnt1_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, s[102:103]
-// CHECK: [0x66,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, flat_scratch
-// CHECK: [0x68,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, vcc
-// CHECK: [0x6a,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, tba
-// CHECK: [0x6c,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, tma
-// CHECK: [0x6e,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, exec
-// CHECK: [0x7e,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, 0
-// CHECK: [0x80,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, -1
-// CHECK: [0xc1,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x10,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x10,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt1_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x10,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff0_i32_b32 s5, s1
-// CHECK: [0x01,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s103, s1
-// CHECK: [0x01,0x11,0xe7,0xbe]
-
-s_ff0_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x11,0xe8,0xbe]
-
-s_ff0_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x11,0xe9,0xbe]
-
-s_ff0_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x11,0xea,0xbe]
-
-s_ff0_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x11,0xeb,0xbe]
-
-s_ff0_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x11,0xec,0xbe]
-
-s_ff0_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x11,0xed,0xbe]
-
-s_ff0_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x11,0xee,0xbe]
-
-s_ff0_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x11,0xef,0xbe]
-
-s_ff0_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x11,0xfb,0xbe]
-
-s_ff0_i32_b32 m0, s1
-// CHECK: [0x01,0x11,0xfc,0xbe]
-
-s_ff0_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x11,0xfe,0xbe]
-
-s_ff0_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x11,0xff,0xbe]
-
-s_ff0_i32_b32 s5, s103
-// CHECK: [0x67,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, m0
-// CHECK: [0x7c,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, 0
-// CHECK: [0x80,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, -1
-// CHECK: [0xc1,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x11,0x85,0xbe]
-
-s_ff0_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x11,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff0_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x11,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff0_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s103, s[2:3]
-// CHECK: [0x02,0x12,0xe7,0xbe]
-
-s_ff0_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x12,0xe8,0xbe]
-
-s_ff0_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x12,0xe9,0xbe]
-
-s_ff0_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x12,0xea,0xbe]
-
-s_ff0_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x12,0xeb,0xbe]
-
-s_ff0_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x12,0xec,0xbe]
-
-s_ff0_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x12,0xed,0xbe]
-
-s_ff0_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x12,0xee,0xbe]
-
-s_ff0_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x12,0xef,0xbe]
-
-s_ff0_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x12,0xfb,0xbe]
-
-s_ff0_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x12,0xfc,0xbe]
-
-s_ff0_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x12,0xfe,0xbe]
-
-s_ff0_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x12,0xff,0xbe]
-
-s_ff0_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, s[102:103]
-// CHECK: [0x66,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, flat_scratch
-// CHECK: [0x68,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, vcc
-// CHECK: [0x6a,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, tba
-// CHECK: [0x6c,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, tma
-// CHECK: [0x6e,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, exec
-// CHECK: [0x7e,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, 0
-// CHECK: [0x80,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, -1
-// CHECK: [0xc1,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x12,0x85,0xbe]
-
-s_ff0_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x12,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff0_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x12,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff1_i32_b32 s5, s1
-// CHECK: [0x01,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s103, s1
-// CHECK: [0x01,0x13,0xe7,0xbe]
-
-s_ff1_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x13,0xe8,0xbe]
-
-s_ff1_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x13,0xe9,0xbe]
-
-s_ff1_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x13,0xea,0xbe]
-
-s_ff1_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x13,0xeb,0xbe]
-
-s_ff1_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x13,0xec,0xbe]
-
-s_ff1_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x13,0xed,0xbe]
-
-s_ff1_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x13,0xee,0xbe]
-
-s_ff1_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x13,0xef,0xbe]
-
-s_ff1_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x13,0xfb,0xbe]
-
-s_ff1_i32_b32 m0, s1
-// CHECK: [0x01,0x13,0xfc,0xbe]
-
-s_ff1_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x13,0xfe,0xbe]
-
-s_ff1_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x13,0xff,0xbe]
-
-s_ff1_i32_b32 s5, s103
-// CHECK: [0x67,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, m0
-// CHECK: [0x7c,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, 0
-// CHECK: [0x80,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, -1
-// CHECK: [0xc1,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x13,0x85,0xbe]
-
-s_ff1_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x13,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff1_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x13,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff1_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s103, s[2:3]
-// CHECK: [0x02,0x14,0xe7,0xbe]
-
-s_ff1_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x14,0xe8,0xbe]
-
-s_ff1_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x14,0xe9,0xbe]
-
-s_ff1_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x14,0xea,0xbe]
-
-s_ff1_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x14,0xeb,0xbe]
-
-s_ff1_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x14,0xec,0xbe]
-
-s_ff1_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x14,0xed,0xbe]
-
-s_ff1_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x14,0xee,0xbe]
-
-s_ff1_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x14,0xef,0xbe]
-
-s_ff1_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x14,0xfb,0xbe]
-
-s_ff1_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x14,0xfc,0xbe]
-
-s_ff1_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x14,0xfe,0xbe]
-
-s_ff1_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x14,0xff,0xbe]
-
-s_ff1_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, s[102:103]
-// CHECK: [0x66,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, flat_scratch
-// CHECK: [0x68,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, vcc
-// CHECK: [0x6a,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, tba
-// CHECK: [0x6c,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, tma
-// CHECK: [0x6e,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, exec
-// CHECK: [0x7e,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, 0
-// CHECK: [0x80,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, -1
-// CHECK: [0xc1,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x14,0x85,0xbe]
-
-s_ff1_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x14,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff1_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x14,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_b32 s5, s1
-// CHECK: [0x01,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s103, s1
-// CHECK: [0x01,0x15,0xe7,0xbe]
-
-s_flbit_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x15,0xe8,0xbe]
-
-s_flbit_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x15,0xe9,0xbe]
-
-s_flbit_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x15,0xea,0xbe]
-
-s_flbit_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x15,0xeb,0xbe]
-
-s_flbit_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x15,0xec,0xbe]
-
-s_flbit_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x15,0xed,0xbe]
-
-s_flbit_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x15,0xee,0xbe]
-
-s_flbit_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x15,0xef,0xbe]
-
-s_flbit_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x15,0xfb,0xbe]
-
-s_flbit_i32_b32 m0, s1
-// CHECK: [0x01,0x15,0xfc,0xbe]
-
-s_flbit_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x15,0xfe,0xbe]
-
-s_flbit_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x15,0xff,0xbe]
-
-s_flbit_i32_b32 s5, s103
-// CHECK: [0x67,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, m0
-// CHECK: [0x7c,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, 0
-// CHECK: [0x80,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, -1
-// CHECK: [0xc1,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x15,0x85,0xbe]
-
-s_flbit_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x15,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x15,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s103, s[2:3]
-// CHECK: [0x02,0x16,0xe7,0xbe]
-
-s_flbit_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x16,0xe8,0xbe]
-
-s_flbit_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x16,0xe9,0xbe]
-
-s_flbit_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x16,0xea,0xbe]
-
-s_flbit_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x16,0xeb,0xbe]
-
-s_flbit_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x16,0xec,0xbe]
-
-s_flbit_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x16,0xed,0xbe]
-
-s_flbit_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x16,0xee,0xbe]
-
-s_flbit_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x16,0xef,0xbe]
-
-s_flbit_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x16,0xfb,0xbe]
-
-s_flbit_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x16,0xfc,0xbe]
-
-s_flbit_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x16,0xfe,0xbe]
-
-s_flbit_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x16,0xff,0xbe]
-
-s_flbit_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, s[102:103]
-// CHECK: [0x66,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, flat_scratch
-// CHECK: [0x68,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, vcc
-// CHECK: [0x6a,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, tba
-// CHECK: [0x6c,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, tma
-// CHECK: [0x6e,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, exec
-// CHECK: [0x7e,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, 0
-// CHECK: [0x80,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, -1
-// CHECK: [0xc1,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x16,0x85,0xbe]
-
-s_flbit_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x16,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x16,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32 s5, s1
-// CHECK: [0x01,0x17,0x85,0xbe]
-
-s_flbit_i32 s103, s1
-// CHECK: [0x01,0x17,0xe7,0xbe]
-
-s_flbit_i32 flat_scratch_lo, s1
-// CHECK: [0x01,0x17,0xe8,0xbe]
-
-s_flbit_i32 flat_scratch_hi, s1
-// CHECK: [0x01,0x17,0xe9,0xbe]
-
-s_flbit_i32 vcc_lo, s1
-// CHECK: [0x01,0x17,0xea,0xbe]
-
-s_flbit_i32 vcc_hi, s1
-// CHECK: [0x01,0x17,0xeb,0xbe]
-
-s_flbit_i32 tba_lo, s1
-// CHECK: [0x01,0x17,0xec,0xbe]
-
-s_flbit_i32 tba_hi, s1
-// CHECK: [0x01,0x17,0xed,0xbe]
-
-s_flbit_i32 tma_lo, s1
-// CHECK: [0x01,0x17,0xee,0xbe]
-
-s_flbit_i32 tma_hi, s1
-// CHECK: [0x01,0x17,0xef,0xbe]
-
-s_flbit_i32 ttmp11, s1
-// CHECK: [0x01,0x17,0xfb,0xbe]
-
-s_flbit_i32 m0, s1
-// CHECK: [0x01,0x17,0xfc,0xbe]
-
-s_flbit_i32 exec_lo, s1
-// CHECK: [0x01,0x17,0xfe,0xbe]
-
-s_flbit_i32 exec_hi, s1
-// CHECK: [0x01,0x17,0xff,0xbe]
-
-s_flbit_i32 s5, s103
-// CHECK: [0x67,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, flat_scratch_lo
-// CHECK: [0x68,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, flat_scratch_hi
-// CHECK: [0x69,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, vcc_lo
-// CHECK: [0x6a,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, vcc_hi
-// CHECK: [0x6b,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, tba_lo
-// CHECK: [0x6c,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, tba_hi
-// CHECK: [0x6d,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, tma_lo
-// CHECK: [0x6e,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, tma_hi
-// CHECK: [0x6f,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, ttmp11
-// CHECK: [0x7b,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, m0
-// CHECK: [0x7c,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, exec_lo
-// CHECK: [0x7e,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, exec_hi
-// CHECK: [0x7f,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, 0
-// CHECK: [0x80,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, -1
-// CHECK: [0xc1,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, 0.5
-// CHECK: [0xf0,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, -4.0
-// CHECK: [0xf7,0x17,0x85,0xbe]
-
-s_flbit_i32 s5, 0xaf123456
-// CHECK: [0xff,0x17,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32 s5, 0x3f717273
-// CHECK: [0xff,0x17,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_i64 s5, s[2:3]
-// CHECK: [0x02,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s103, s[2:3]
-// CHECK: [0x02,0x18,0xe7,0xbe]
-
-s_flbit_i32_i64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x18,0xe8,0xbe]
-
-s_flbit_i32_i64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x18,0xe9,0xbe]
-
-s_flbit_i32_i64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x18,0xea,0xbe]
-
-s_flbit_i32_i64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x18,0xeb,0xbe]
-
-s_flbit_i32_i64 tba_lo, s[2:3]
-// CHECK: [0x02,0x18,0xec,0xbe]
-
-s_flbit_i32_i64 tba_hi, s[2:3]
-// CHECK: [0x02,0x18,0xed,0xbe]
-
-s_flbit_i32_i64 tma_lo, s[2:3]
-// CHECK: [0x02,0x18,0xee,0xbe]
-
-s_flbit_i32_i64 tma_hi, s[2:3]
-// CHECK: [0x02,0x18,0xef,0xbe]
-
-s_flbit_i32_i64 ttmp11, s[2:3]
-// CHECK: [0x02,0x18,0xfb,0xbe]
-
-s_flbit_i32_i64 m0, s[2:3]
-// CHECK: [0x02,0x18,0xfc,0xbe]
-
-s_flbit_i32_i64 exec_lo, s[2:3]
-// CHECK: [0x02,0x18,0xfe,0xbe]
-
-s_flbit_i32_i64 exec_hi, s[2:3]
-// CHECK: [0x02,0x18,0xff,0xbe]
-
-s_flbit_i32_i64 s5, s[4:5]
-// CHECK: [0x04,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, s[102:103]
-// CHECK: [0x66,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, flat_scratch
-// CHECK: [0x68,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, vcc
-// CHECK: [0x6a,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, tba
-// CHECK: [0x6c,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, tma
-// CHECK: [0x6e,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, exec
-// CHECK: [0x7e,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, 0
-// CHECK: [0x80,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, -1
-// CHECK: [0xc1,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, 0.5
-// CHECK: [0xf0,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, -4.0
-// CHECK: [0xf7,0x18,0x85,0xbe]
-
-s_flbit_i32_i64 s5, 0xaf123456
-// CHECK: [0xff,0x18,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_i64 s5, 0x3f717273
-// CHECK: [0xff,0x18,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_sext_i32_i8 s5, s1
-// CHECK: [0x01,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s103, s1
-// CHECK: [0x01,0x19,0xe7,0xbe]
-
-s_sext_i32_i8 flat_scratch_lo, s1
-// CHECK: [0x01,0x19,0xe8,0xbe]
-
-s_sext_i32_i8 flat_scratch_hi, s1
-// CHECK: [0x01,0x19,0xe9,0xbe]
-
-s_sext_i32_i8 vcc_lo, s1
-// CHECK: [0x01,0x19,0xea,0xbe]
-
-s_sext_i32_i8 vcc_hi, s1
-// CHECK: [0x01,0x19,0xeb,0xbe]
-
-s_sext_i32_i8 tba_lo, s1
-// CHECK: [0x01,0x19,0xec,0xbe]
-
-s_sext_i32_i8 tba_hi, s1
-// CHECK: [0x01,0x19,0xed,0xbe]
-
-s_sext_i32_i8 tma_lo, s1
-// CHECK: [0x01,0x19,0xee,0xbe]
-
-s_sext_i32_i8 tma_hi, s1
-// CHECK: [0x01,0x19,0xef,0xbe]
-
-s_sext_i32_i8 ttmp11, s1
-// CHECK: [0x01,0x19,0xfb,0xbe]
-
-s_sext_i32_i8 m0, s1
-// CHECK: [0x01,0x19,0xfc,0xbe]
-
-s_sext_i32_i8 exec_lo, s1
-// CHECK: [0x01,0x19,0xfe,0xbe]
-
-s_sext_i32_i8 exec_hi, s1
-// CHECK: [0x01,0x19,0xff,0xbe]
-
-s_sext_i32_i8 s5, s103
-// CHECK: [0x67,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, flat_scratch_lo
-// CHECK: [0x68,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, flat_scratch_hi
-// CHECK: [0x69,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, vcc_lo
-// CHECK: [0x6a,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, vcc_hi
-// CHECK: [0x6b,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, tba_lo
-// CHECK: [0x6c,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, tba_hi
-// CHECK: [0x6d,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, tma_lo
-// CHECK: [0x6e,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, tma_hi
-// CHECK: [0x6f,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, ttmp11
-// CHECK: [0x7b,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, m0
-// CHECK: [0x7c,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, exec_lo
-// CHECK: [0x7e,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, exec_hi
-// CHECK: [0x7f,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, 0
-// CHECK: [0x80,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, -1
-// CHECK: [0xc1,0x19,0x85,0xbe]
-
-s_sext_i32_i8 s5, 0x71
-// CHECK: [0xff,0x19,0x85,0xbe,0x71,0x00,0x00,0x00]
-
-s_sext_i32_i8 s5, 0xf0
-// CHECK: [0xff,0x19,0x85,0xbe,0xf0,0x00,0x00,0x00]
-
-s_sext_i32_i16 s5, s1
-// CHECK: [0x01,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s103, s1
-// CHECK: [0x01,0x1a,0xe7,0xbe]
-
-s_sext_i32_i16 flat_scratch_lo, s1
-// CHECK: [0x01,0x1a,0xe8,0xbe]
-
-s_sext_i32_i16 flat_scratch_hi, s1
-// CHECK: [0x01,0x1a,0xe9,0xbe]
-
-s_sext_i32_i16 vcc_lo, s1
-// CHECK: [0x01,0x1a,0xea,0xbe]
-
-s_sext_i32_i16 vcc_hi, s1
-// CHECK: [0x01,0x1a,0xeb,0xbe]
-
-s_sext_i32_i16 tba_lo, s1
-// CHECK: [0x01,0x1a,0xec,0xbe]
-
-s_sext_i32_i16 tba_hi, s1
-// CHECK: [0x01,0x1a,0xed,0xbe]
-
-s_sext_i32_i16 tma_lo, s1
-// CHECK: [0x01,0x1a,0xee,0xbe]
-
-s_sext_i32_i16 tma_hi, s1
-// CHECK: [0x01,0x1a,0xef,0xbe]
-
-s_sext_i32_i16 ttmp11, s1
-// CHECK: [0x01,0x1a,0xfb,0xbe]
-
-s_sext_i32_i16 m0, s1
-// CHECK: [0x01,0x1a,0xfc,0xbe]
-
-s_sext_i32_i16 exec_lo, s1
-// CHECK: [0x01,0x1a,0xfe,0xbe]
-
-s_sext_i32_i16 exec_hi, s1
-// CHECK: [0x01,0x1a,0xff,0xbe]
-
-s_sext_i32_i16 s5, s103
-// CHECK: [0x67,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, flat_scratch_lo
-// CHECK: [0x68,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, flat_scratch_hi
-// CHECK: [0x69,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, vcc_lo
-// CHECK: [0x6a,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, vcc_hi
-// CHECK: [0x6b,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, tba_lo
-// CHECK: [0x6c,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, tba_hi
-// CHECK: [0x6d,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, tma_lo
-// CHECK: [0x6e,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, tma_hi
-// CHECK: [0x6f,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, ttmp11
-// CHECK: [0x7b,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, m0
-// CHECK: [0x7c,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, exec_lo
-// CHECK: [0x7e,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, exec_hi
-// CHECK: [0x7f,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, 0
-// CHECK: [0x80,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, -1
-// CHECK: [0xc1,0x1a,0x85,0xbe]
-
-s_sext_i32_i16 s5, 0xfe0b
-// CHECK: [0xff,0x1a,0x85,0xbe,0x0b,0xfe,0x00,0x00]
-
-s_sext_i32_i16 s5, 0x3456
-// CHECK: [0xff,0x1a,0x85,0xbe,0x56,0x34,0x00,0x00]
-
-s_bitset0_b32 s5, s1
-// CHECK: [0x01,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s103, s1
-// CHECK: [0x01,0x1b,0xe7,0xbe]
-
-s_bitset0_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x1b,0xe8,0xbe]
-
-s_bitset0_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x1b,0xe9,0xbe]
-
-s_bitset0_b32 vcc_lo, s1
-// CHECK: [0x01,0x1b,0xea,0xbe]
-
-s_bitset0_b32 vcc_hi, s1
-// CHECK: [0x01,0x1b,0xeb,0xbe]
-
-s_bitset0_b32 tba_lo, s1
-// CHECK: [0x01,0x1b,0xec,0xbe]
-
-s_bitset0_b32 tba_hi, s1
-// CHECK: [0x01,0x1b,0xed,0xbe]
-
-s_bitset0_b32 tma_lo, s1
-// CHECK: [0x01,0x1b,0xee,0xbe]
-
-s_bitset0_b32 tma_hi, s1
-// CHECK: [0x01,0x1b,0xef,0xbe]
-
-s_bitset0_b32 ttmp11, s1
-// CHECK: [0x01,0x1b,0xfb,0xbe]
-
-s_bitset0_b32 m0, s1
-// CHECK: [0x01,0x1b,0xfc,0xbe]
-
-s_bitset0_b32 exec_lo, s1
-// CHECK: [0x01,0x1b,0xfe,0xbe]
-
-s_bitset0_b32 exec_hi, s1
-// CHECK: [0x01,0x1b,0xff,0xbe]
-
-s_bitset0_b32 s5, s103
-// CHECK: [0x67,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, vcc_lo
-// CHECK: [0x6a,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, vcc_hi
-// CHECK: [0x6b,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, tba_lo
-// CHECK: [0x6c,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, tba_hi
-// CHECK: [0x6d,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, tma_lo
-// CHECK: [0x6e,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, tma_hi
-// CHECK: [0x6f,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, ttmp11
-// CHECK: [0x7b,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, m0
-// CHECK: [0x7c,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, exec_lo
-// CHECK: [0x7e,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, exec_hi
-// CHECK: [0x7f,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, 0
-// CHECK: [0x80,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, -1
-// CHECK: [0xc1,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, 0.5
-// CHECK: [0xf0,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, -4.0
-// CHECK: [0xf7,0x1b,0x85,0xbe]
-
-s_bitset0_b32 s5, 0xaf123456
-// CHECK: [0xff,0x1b,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset0_b32 s5, 0x3f717273
-// CHECK: [0xff,0x1b,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset0_b64 s[10:11], s1
-// CHECK: [0x01,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[12:13], s1
-// CHECK: [0x01,0x1c,0x8c,0xbe]
-
-s_bitset0_b64 s[102:103], s1
-// CHECK: [0x01,0x1c,0xe6,0xbe]
-
-s_bitset0_b64 flat_scratch, s1
-// CHECK: [0x01,0x1c,0xe8,0xbe]
-
-s_bitset0_b64 vcc, s1
-// CHECK: [0x01,0x1c,0xea,0xbe]
-
-s_bitset0_b64 tba, s1
-// CHECK: [0x01,0x1c,0xec,0xbe]
-
-s_bitset0_b64 tma, s1
-// CHECK: [0x01,0x1c,0xee,0xbe]
-
-s_bitset0_b64 ttmp[10:11], s1
-// CHECK: [0x01,0x1c,0xfa,0xbe]
-
-s_bitset0_b64 exec, s1
-// CHECK: [0x01,0x1c,0xfe,0xbe]
-
-s_bitset0_b64 s[10:11], s103
-// CHECK: [0x67,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], flat_scratch_lo
-// CHECK: [0x68,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], flat_scratch_hi
-// CHECK: [0x69,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], vcc_lo
-// CHECK: [0x6a,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], vcc_hi
-// CHECK: [0x6b,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], tba_lo
-// CHECK: [0x6c,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], tba_hi
-// CHECK: [0x6d,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], tma_lo
-// CHECK: [0x6e,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], tma_hi
-// CHECK: [0x6f,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], ttmp11
-// CHECK: [0x7b,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], m0
-// CHECK: [0x7c,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], exec_lo
-// CHECK: [0x7e,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], exec_hi
-// CHECK: [0x7f,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], 0
-// CHECK: [0x80,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], -1
-// CHECK: [0xc1,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x1c,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x1c,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset0_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x1c,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset1_b32 s5, s1
-// CHECK: [0x01,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s103, s1
-// CHECK: [0x01,0x1d,0xe7,0xbe]
-
-s_bitset1_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x1d,0xe8,0xbe]
-
-s_bitset1_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x1d,0xe9,0xbe]
-
-s_bitset1_b32 vcc_lo, s1
-// CHECK: [0x01,0x1d,0xea,0xbe]
-
-s_bitset1_b32 vcc_hi, s1
-// CHECK: [0x01,0x1d,0xeb,0xbe]
-
-s_bitset1_b32 tba_lo, s1
-// CHECK: [0x01,0x1d,0xec,0xbe]
-
-s_bitset1_b32 tba_hi, s1
-// CHECK: [0x01,0x1d,0xed,0xbe]
-
-s_bitset1_b32 tma_lo, s1
-// CHECK: [0x01,0x1d,0xee,0xbe]
-
-s_bitset1_b32 tma_hi, s1
-// CHECK: [0x01,0x1d,0xef,0xbe]
-
-s_bitset1_b32 ttmp11, s1
-// CHECK: [0x01,0x1d,0xfb,0xbe]
-
-s_bitset1_b32 m0, s1
-// CHECK: [0x01,0x1d,0xfc,0xbe]
-
-s_bitset1_b32 exec_lo, s1
-// CHECK: [0x01,0x1d,0xfe,0xbe]
-
-s_bitset1_b32 exec_hi, s1
-// CHECK: [0x01,0x1d,0xff,0xbe]
-
-s_bitset1_b32 s5, s103
-// CHECK: [0x67,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, vcc_lo
-// CHECK: [0x6a,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, vcc_hi
-// CHECK: [0x6b,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, tba_lo
-// CHECK: [0x6c,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, tba_hi
-// CHECK: [0x6d,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, tma_lo
-// CHECK: [0x6e,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, tma_hi
-// CHECK: [0x6f,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, ttmp11
-// CHECK: [0x7b,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, m0
-// CHECK: [0x7c,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, exec_lo
-// CHECK: [0x7e,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, exec_hi
-// CHECK: [0x7f,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, 0
-// CHECK: [0x80,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, -1
-// CHECK: [0xc1,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, 0.5
-// CHECK: [0xf0,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, -4.0
-// CHECK: [0xf7,0x1d,0x85,0xbe]
-
-s_bitset1_b32 s5, 0xaf123456
-// CHECK: [0xff,0x1d,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset1_b32 s5, 0x3f717273
-// CHECK: [0xff,0x1d,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset1_b64 s[10:11], s1
-// CHECK: [0x01,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[12:13], s1
-// CHECK: [0x01,0x1e,0x8c,0xbe]
-
-s_bitset1_b64 s[102:103], s1
-// CHECK: [0x01,0x1e,0xe6,0xbe]
-
-s_bitset1_b64 flat_scratch, s1
-// CHECK: [0x01,0x1e,0xe8,0xbe]
-
-s_bitset1_b64 vcc, s1
-// CHECK: [0x01,0x1e,0xea,0xbe]
-
-s_bitset1_b64 tba, s1
-// CHECK: [0x01,0x1e,0xec,0xbe]
-
-s_bitset1_b64 tma, s1
-// CHECK: [0x01,0x1e,0xee,0xbe]
-
-s_bitset1_b64 ttmp[10:11], s1
-// CHECK: [0x01,0x1e,0xfa,0xbe]
-
-s_bitset1_b64 exec, s1
-// CHECK: [0x01,0x1e,0xfe,0xbe]
-
-s_bitset1_b64 s[10:11], s103
-// CHECK: [0x67,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], flat_scratch_lo
-// CHECK: [0x68,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], flat_scratch_hi
-// CHECK: [0x69,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], vcc_lo
-// CHECK: [0x6a,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], vcc_hi
-// CHECK: [0x6b,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], tba_lo
-// CHECK: [0x6c,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], tba_hi
-// CHECK: [0x6d,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], tma_lo
-// CHECK: [0x6e,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], tma_hi
-// CHECK: [0x6f,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], ttmp11
-// CHECK: [0x7b,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], m0
-// CHECK: [0x7c,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], exec_lo
-// CHECK: [0x7e,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], exec_hi
-// CHECK: [0x7f,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], 0
-// CHECK: [0x80,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], -1
-// CHECK: [0xc1,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x1e,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x1e,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset1_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x1e,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_getpc_b64 s[10:11]
-// CHECK: [0x00,0x1f,0x8a,0xbe]
-
-s_getpc_b64 s[12:13]
-// CHECK: [0x00,0x1f,0x8c,0xbe]
-
-s_getpc_b64 s[102:103]
-// CHECK: [0x00,0x1f,0xe6,0xbe]
-
-s_getpc_b64 flat_scratch
-// CHECK: [0x00,0x1f,0xe8,0xbe]
-
-s_getpc_b64 vcc
-// CHECK: [0x00,0x1f,0xea,0xbe]
-
-s_getpc_b64 tba
-// CHECK: [0x00,0x1f,0xec,0xbe]
-
-s_getpc_b64 tma
-// CHECK: [0x00,0x1f,0xee,0xbe]
-
-s_getpc_b64 ttmp[10:11]
-// CHECK: [0x00,0x1f,0xfa,0xbe]
-
-s_getpc_b64 exec
-// CHECK: [0x00,0x1f,0xfe,0xbe]
-
-s_setpc_b64 s[2:3]
-// CHECK: [0x02,0x20,0x80,0xbe]
-
-s_setpc_b64 s[4:5]
-// CHECK: [0x04,0x20,0x80,0xbe]
-
-s_setpc_b64 s[102:103]
-// CHECK: [0x66,0x20,0x80,0xbe]
-
-s_setpc_b64 flat_scratch
-// CHECK: [0x68,0x20,0x80,0xbe]
-
-s_setpc_b64 vcc
-// CHECK: [0x6a,0x20,0x80,0xbe]
-
-s_setpc_b64 tba
-// CHECK: [0x6c,0x20,0x80,0xbe]
-
-s_setpc_b64 tma
-// CHECK: [0x6e,0x20,0x80,0xbe]
-
-s_setpc_b64 ttmp[10:11]
-// CHECK: [0x7a,0x20,0x80,0xbe]
-
-s_swappc_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x21,0x8a,0xbe]
-
-s_swappc_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x21,0x8c,0xbe]
-
-s_swappc_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x21,0xe6,0xbe]
-
-s_swappc_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x21,0xe8,0xbe]
-
-s_swappc_b64 vcc, s[2:3]
-// CHECK: [0x02,0x21,0xea,0xbe]
-
-s_swappc_b64 tba, s[2:3]
-// CHECK: [0x02,0x21,0xec,0xbe]
-
-s_swappc_b64 tma, s[2:3]
-// CHECK: [0x02,0x21,0xee,0xbe]
-
-s_swappc_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x21,0xfa,0xbe]
-
-s_swappc_b64 exec, s[2:3]
-// CHECK: [0x02,0x21,0xfe,0xbe]
-
-s_swappc_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x21,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x21,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x21,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], vcc
-// CHECK: [0x6a,0x21,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], tba
-// CHECK: [0x6c,0x21,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], tma
-// CHECK: [0x6e,0x21,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x21,0x8a,0xbe]
-
-s_rfe_b64 s[2:3]
-// CHECK: [0x02,0x22,0x80,0xbe]
-
-s_rfe_b64 s[4:5]
-// CHECK: [0x04,0x22,0x80,0xbe]
-
-s_rfe_b64 s[102:103]
-// CHECK: [0x66,0x22,0x80,0xbe]
-
-s_rfe_b64 flat_scratch
-// CHECK: [0x68,0x22,0x80,0xbe]
-
-s_rfe_b64 vcc
-// CHECK: [0x6a,0x22,0x80,0xbe]
-
-s_rfe_b64 tba
-// CHECK: [0x6c,0x22,0x80,0xbe]
-
-s_rfe_b64 tma
-// CHECK: [0x6e,0x22,0x80,0xbe]
-
-s_rfe_b64 ttmp[10:11]
-// CHECK: [0x7a,0x22,0x80,0xbe]
-
-s_and_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x24,0x8c,0xbe]
-
-s_and_saveexec_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x24,0xe6,0xbe]
-
-s_and_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x24,0xe8,0xbe]
-
-s_and_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x24,0xea,0xbe]
-
-s_and_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x24,0xec,0xbe]
-
-s_and_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x24,0xee,0xbe]
-
-s_and_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x24,0xfa,0xbe]
-
-s_and_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x24,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x24,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_and_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x24,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_or_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x25,0x8c,0xbe]
-
-s_or_saveexec_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x25,0xe6,0xbe]
-
-s_or_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x25,0xe8,0xbe]
-
-s_or_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x25,0xea,0xbe]
-
-s_or_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x25,0xec,0xbe]
-
-s_or_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x25,0xee,0xbe]
-
-s_or_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x25,0xfa,0xbe]
-
-s_or_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x25,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x25,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_or_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x25,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xor_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x26,0x8c,0xbe]
-
-s_xor_saveexec_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x26,0xe6,0xbe]
-
-s_xor_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x26,0xe8,0xbe]
-
-s_xor_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x26,0xea,0xbe]
-
-s_xor_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x26,0xec,0xbe]
-
-s_xor_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x26,0xee,0xbe]
-
-s_xor_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x26,0xfa,0xbe]
-
-s_xor_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x26,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x26,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xor_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x26,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn2_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x27,0x8c,0xbe]
-
-s_andn2_saveexec_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x27,0xe6,0xbe]
-
-s_andn2_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x27,0xe8,0xbe]
-
-s_andn2_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x27,0xea,0xbe]
-
-s_andn2_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x27,0xec,0xbe]
-
-s_andn2_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x27,0xee,0xbe]
-
-s_andn2_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x27,0xfa,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x27,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x27,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn2_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x27,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_orn2_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x28,0x8c,0xbe]
-
-s_orn2_saveexec_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x28,0xe6,0xbe]
-
-s_orn2_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x28,0xe8,0xbe]
-
-s_orn2_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x28,0xea,0xbe]
-
-s_orn2_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x28,0xec,0xbe]
-
-s_orn2_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x28,0xee,0xbe]
-
-s_orn2_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x28,0xfa,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x28,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x28,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_orn2_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x28,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nand_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x29,0x8c,0xbe]
-
-s_nand_saveexec_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x29,0xe6,0xbe]
-
-s_nand_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x29,0xe8,0xbe]
-
-s_nand_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x29,0xea,0xbe]
-
-s_nand_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x29,0xec,0xbe]
-
-s_nand_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x29,0xee,0xbe]
-
-s_nand_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x29,0xfa,0xbe]
-
-s_nand_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x29,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x29,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nand_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x29,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nor_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x2a,0x8c,0xbe]
-
-s_nor_saveexec_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x2a,0xe6,0xbe]
-
-s_nor_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x2a,0xe8,0xbe]
-
-s_nor_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x2a,0xea,0xbe]
-
-s_nor_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x2a,0xec,0xbe]
-
-s_nor_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x2a,0xee,0xbe]
-
-s_nor_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x2a,0xfa,0xbe]
-
-s_nor_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x2a,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x2a,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nor_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x2a,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xnor_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x2b,0x8c,0xbe]
-
-s_xnor_saveexec_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x2b,0xe6,0xbe]
-
-s_xnor_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x2b,0xe8,0xbe]
-
-s_xnor_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x2b,0xea,0xbe]
-
-s_xnor_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x2b,0xec,0xbe]
-
-s_xnor_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x2b,0xee,0xbe]
-
-s_xnor_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x2b,0xfa,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x2b,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x2b,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xnor_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x2b,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_quadmask_b32 s5, s1
-// CHECK: [0x01,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s103, s1
-// CHECK: [0x01,0x2c,0xe7,0xbe]
-
-s_quadmask_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x2c,0xe8,0xbe]
-
-s_quadmask_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x2c,0xe9,0xbe]
-
-s_quadmask_b32 vcc_lo, s1
-// CHECK: [0x01,0x2c,0xea,0xbe]
-
-s_quadmask_b32 vcc_hi, s1
-// CHECK: [0x01,0x2c,0xeb,0xbe]
-
-s_quadmask_b32 tba_lo, s1
-// CHECK: [0x01,0x2c,0xec,0xbe]
-
-s_quadmask_b32 tba_hi, s1
-// CHECK: [0x01,0x2c,0xed,0xbe]
-
-s_quadmask_b32 tma_lo, s1
-// CHECK: [0x01,0x2c,0xee,0xbe]
-
-s_quadmask_b32 tma_hi, s1
-// CHECK: [0x01,0x2c,0xef,0xbe]
-
-s_quadmask_b32 ttmp11, s1
-// CHECK: [0x01,0x2c,0xfb,0xbe]
-
-s_quadmask_b32 m0, s1
-// CHECK: [0x01,0x2c,0xfc,0xbe]
-
-s_quadmask_b32 exec_lo, s1
-// CHECK: [0x01,0x2c,0xfe,0xbe]
-
-s_quadmask_b32 exec_hi, s1
-// CHECK: [0x01,0x2c,0xff,0xbe]
-
-s_quadmask_b32 s5, s103
-// CHECK: [0x67,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, vcc_lo
-// CHECK: [0x6a,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, vcc_hi
-// CHECK: [0x6b,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, tba_lo
-// CHECK: [0x6c,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, tba_hi
-// CHECK: [0x6d,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, tma_lo
-// CHECK: [0x6e,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, tma_hi
-// CHECK: [0x6f,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, ttmp11
-// CHECK: [0x7b,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, m0
-// CHECK: [0x7c,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, exec_lo
-// CHECK: [0x7e,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, exec_hi
-// CHECK: [0x7f,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, 0
-// CHECK: [0x80,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, -1
-// CHECK: [0xc1,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, 0.5
-// CHECK: [0xf0,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, -4.0
-// CHECK: [0xf7,0x2c,0x85,0xbe]
-
-s_quadmask_b32 s5, 0xaf123456
-// CHECK: [0xff,0x2c,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_quadmask_b32 s5, 0x3f717273
-// CHECK: [0xff,0x2c,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_quadmask_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x2d,0x8c,0xbe]
-
-s_quadmask_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x2d,0xe6,0xbe]
-
-s_quadmask_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x2d,0xe8,0xbe]
-
-s_quadmask_b64 vcc, s[2:3]
-// CHECK: [0x02,0x2d,0xea,0xbe]
-
-s_quadmask_b64 tba, s[2:3]
-// CHECK: [0x02,0x2d,0xec,0xbe]
-
-s_quadmask_b64 tma, s[2:3]
-// CHECK: [0x02,0x2d,0xee,0xbe]
-
-s_quadmask_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x2d,0xfa,0xbe]
-
-s_quadmask_b64 exec, s[2:3]
-// CHECK: [0x02,0x2d,0xfe,0xbe]
-
-s_quadmask_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], vcc
-// CHECK: [0x6a,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], tba
-// CHECK: [0x6c,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], tma
-// CHECK: [0x6e,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], exec
-// CHECK: [0x7e,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], 0
-// CHECK: [0x80,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], -1
-// CHECK: [0xc1,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x2d,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x2d,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_quadmask_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x2d,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_movrels_b32 s5, s1
-// CHECK: [0x01,0x2e,0x85,0xbe]
-
-s_movrels_b32 s103, s1
-// CHECK: [0x01,0x2e,0xe7,0xbe]
-
-s_movrels_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x2e,0xe8,0xbe]
-
-s_movrels_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x2e,0xe9,0xbe]
-
-s_movrels_b32 vcc_lo, s1
-// CHECK: [0x01,0x2e,0xea,0xbe]
-
-s_movrels_b32 vcc_hi, s1
-// CHECK: [0x01,0x2e,0xeb,0xbe]
-
-s_movrels_b32 tba_lo, s1
-// CHECK: [0x01,0x2e,0xec,0xbe]
-
-s_movrels_b32 tba_hi, s1
-// CHECK: [0x01,0x2e,0xed,0xbe]
-
-s_movrels_b32 tma_lo, s1
-// CHECK: [0x01,0x2e,0xee,0xbe]
-
-s_movrels_b32 tma_hi, s1
-// CHECK: [0x01,0x2e,0xef,0xbe]
-
-s_movrels_b32 ttmp11, s1
-// CHECK: [0x01,0x2e,0xfb,0xbe]
-
-s_movrels_b32 m0, s1
-// CHECK: [0x01,0x2e,0xfc,0xbe]
-
-s_movrels_b32 exec_lo, s1
-// CHECK: [0x01,0x2e,0xfe,0xbe]
-
-s_movrels_b32 exec_hi, s1
-// CHECK: [0x01,0x2e,0xff,0xbe]
-
-s_movrels_b32 s5, s103
-// CHECK: [0x67,0x2e,0x85,0xbe]
-
-s_movrels_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x2e,0x85,0xbe]
-
-s_movrels_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x2e,0x85,0xbe]
-
-s_movrels_b32 s5, vcc_lo
-// CHECK: [0x6a,0x2e,0x85,0xbe]
-
-s_movrels_b32 s5, vcc_hi
-// CHECK: [0x6b,0x2e,0x85,0xbe]
-
-s_movrels_b32 s5, tba_lo
-// CHECK: [0x6c,0x2e,0x85,0xbe]
-
-s_movrels_b32 s5, tba_hi
-// CHECK: [0x6d,0x2e,0x85,0xbe]
-
-s_movrels_b32 s5, tma_lo
-// CHECK: [0x6e,0x2e,0x85,0xbe]
-
-s_movrels_b32 s5, tma_hi
-// CHECK: [0x6f,0x2e,0x85,0xbe]
-
-s_movrels_b32 s5, ttmp11
-// CHECK: [0x7b,0x2e,0x85,0xbe]
-
-s_movrels_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x2f,0x8a,0xbe]
-
-s_movrels_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x2f,0x8c,0xbe]
-
-s_movrels_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x2f,0xe6,0xbe]
-
-s_movrels_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x2f,0xe8,0xbe]
-
-s_movrels_b64 vcc, s[2:3]
-// CHECK: [0x02,0x2f,0xea,0xbe]
-
-s_movrels_b64 tba, s[2:3]
-// CHECK: [0x02,0x2f,0xec,0xbe]
-
-s_movrels_b64 tma, s[2:3]
-// CHECK: [0x02,0x2f,0xee,0xbe]
-
-s_movrels_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x2f,0xfa,0xbe]
-
-s_movrels_b64 exec, s[2:3]
-// CHECK: [0x02,0x2f,0xfe,0xbe]
-
-s_movrels_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x2f,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x2f,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x2f,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], vcc
-// CHECK: [0x6a,0x2f,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], tba
-// CHECK: [0x6c,0x2f,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], tma
-// CHECK: [0x6e,0x2f,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x2f,0x8a,0xbe]
-
-s_movreld_b32 s5, s1
-// CHECK: [0x01,0x30,0x85,0xbe]
-
-s_movreld_b32 s103, s1
-// CHECK: [0x01,0x30,0xe7,0xbe]
-
-s_movreld_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x30,0xe8,0xbe]
-
-s_movreld_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x30,0xe9,0xbe]
-
-s_movreld_b32 vcc_lo, s1
-// CHECK: [0x01,0x30,0xea,0xbe]
-
-s_movreld_b32 vcc_hi, s1
-// CHECK: [0x01,0x30,0xeb,0xbe]
-
-s_movreld_b32 tba_lo, s1
-// CHECK: [0x01,0x30,0xec,0xbe]
-
-s_movreld_b32 tba_hi, s1
-// CHECK: [0x01,0x30,0xed,0xbe]
-
-s_movreld_b32 tma_lo, s1
-// CHECK: [0x01,0x30,0xee,0xbe]
-
-s_movreld_b32 tma_hi, s1
-// CHECK: [0x01,0x30,0xef,0xbe]
-
-s_movreld_b32 ttmp11, s1
-// CHECK: [0x01,0x30,0xfb,0xbe]
-
-s_movreld_b32 s5, s103
-// CHECK: [0x67,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, flat_scratch_lo
-// CHECK: [0x68,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, flat_scratch_hi
-// CHECK: [0x69,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, vcc_lo
-// CHECK: [0x6a,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, vcc_hi
-// CHECK: [0x6b,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, tba_lo
-// CHECK: [0x6c,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, tba_hi
-// CHECK: [0x6d,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, tma_lo
-// CHECK: [0x6e,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, tma_hi
-// CHECK: [0x6f,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, ttmp11
-// CHECK: [0x7b,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, m0
-// CHECK: [0x7c,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, 0
-// CHECK: [0x80,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, -1
-// CHECK: [0xc1,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, 0.5
-// CHECK: [0xf0,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, -4.0
-// CHECK: [0xf7,0x30,0x85,0xbe]
-
-s_movreld_b32 s5, 0xaf123456
-// CHECK: [0xff,0x30,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_movreld_b32 s5, 0x3f717273
-// CHECK: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_movreld_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x31,0x8c,0xbe]
-
-s_movreld_b64 s[102:103], s[2:3]
-// CHECK: [0x02,0x31,0xe6,0xbe]
-
-s_movreld_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x31,0xe8,0xbe]
-
-s_movreld_b64 vcc, s[2:3]
-// CHECK: [0x02,0x31,0xea,0xbe]
-
-s_movreld_b64 tba, s[2:3]
-// CHECK: [0x02,0x31,0xec,0xbe]
-
-s_movreld_b64 tma, s[2:3]
-// CHECK: [0x02,0x31,0xee,0xbe]
-
-s_movreld_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x31,0xfa,0xbe]
-
-s_movreld_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], s[102:103]
-// CHECK: [0x66,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], flat_scratch
-// CHECK: [0x68,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], vcc
-// CHECK: [0x6a,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], tba
-// CHECK: [0x6c,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], tma
-// CHECK: [0x6e,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], 0
-// CHECK: [0x80,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], -1
-// CHECK: [0xc1,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x31,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x31,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_movreld_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x31,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cbranch_join s1
-// CHECK: [0x01,0x32,0x80,0xbe]
-
-s_cbranch_join s103
-// CHECK: [0x67,0x32,0x80,0xbe]
-
-s_cbranch_join flat_scratch_lo
-// CHECK: [0x68,0x32,0x80,0xbe]
-
-s_cbranch_join flat_scratch_hi
-// CHECK: [0x69,0x32,0x80,0xbe]
-
-s_cbranch_join vcc_lo
-// CHECK: [0x6a,0x32,0x80,0xbe]
-
-s_cbranch_join vcc_hi
-// CHECK: [0x6b,0x32,0x80,0xbe]
-
-s_cbranch_join tba_lo
-// CHECK: [0x6c,0x32,0x80,0xbe]
-
-s_cbranch_join tba_hi
-// CHECK: [0x6d,0x32,0x80,0xbe]
-
-s_cbranch_join tma_lo
-// CHECK: [0x6e,0x32,0x80,0xbe]
-
-s_cbranch_join tma_hi
-// CHECK: [0x6f,0x32,0x80,0xbe]
-
-s_cbranch_join ttmp11
-// CHECK: [0x7b,0x32,0x80,0xbe]
-
-s_cbranch_join m0
-// CHECK: [0x7c,0x32,0x80,0xbe]
-
-s_cbranch_join exec_lo
-// CHECK: [0x7e,0x32,0x80,0xbe]
-
-s_cbranch_join exec_hi
-// CHECK: [0x7f,0x32,0x80,0xbe]
-
-s_abs_i32 s5, s1
-// CHECK: [0x01,0x34,0x85,0xbe]
-
-s_abs_i32 s103, s1
-// CHECK: [0x01,0x34,0xe7,0xbe]
-
-s_abs_i32 flat_scratch_lo, s1
-// CHECK: [0x01,0x34,0xe8,0xbe]
-
-s_abs_i32 flat_scratch_hi, s1
-// CHECK: [0x01,0x34,0xe9,0xbe]
-
-s_abs_i32 vcc_lo, s1
-// CHECK: [0x01,0x34,0xea,0xbe]
-
-s_abs_i32 vcc_hi, s1
-// CHECK: [0x01,0x34,0xeb,0xbe]
-
-s_abs_i32 tba_lo, s1
-// CHECK: [0x01,0x34,0xec,0xbe]
-
-s_abs_i32 tba_hi, s1
-// CHECK: [0x01,0x34,0xed,0xbe]
-
-s_abs_i32 tma_lo, s1
-// CHECK: [0x01,0x34,0xee,0xbe]
-
-s_abs_i32 tma_hi, s1
-// CHECK: [0x01,0x34,0xef,0xbe]
-
-s_abs_i32 ttmp11, s1
-// CHECK: [0x01,0x34,0xfb,0xbe]
-
-s_abs_i32 m0, s1
-// CHECK: [0x01,0x34,0xfc,0xbe]
-
-s_abs_i32 exec_lo, s1
-// CHECK: [0x01,0x34,0xfe,0xbe]
-
-s_abs_i32 exec_hi, s1
-// CHECK: [0x01,0x34,0xff,0xbe]
-
-s_abs_i32 s5, s103
-// CHECK: [0x67,0x34,0x85,0xbe]
-
-s_abs_i32 s5, flat_scratch_lo
-// CHECK: [0x68,0x34,0x85,0xbe]
-
-s_abs_i32 s5, flat_scratch_hi
-// CHECK: [0x69,0x34,0x85,0xbe]
-
-s_abs_i32 s5, vcc_lo
-// CHECK: [0x6a,0x34,0x85,0xbe]
-
-s_abs_i32 s5, vcc_hi
-// CHECK: [0x6b,0x34,0x85,0xbe]
-
-s_abs_i32 s5, tba_lo
-// CHECK: [0x6c,0x34,0x85,0xbe]
-
-s_abs_i32 s5, tba_hi
-// CHECK: [0x6d,0x34,0x85,0xbe]
-
-s_abs_i32 s5, tma_lo
-// CHECK: [0x6e,0x34,0x85,0xbe]
-
-s_abs_i32 s5, tma_hi
-// CHECK: [0x6f,0x34,0x85,0xbe]
-
-s_abs_i32 s5, ttmp11
-// CHECK: [0x7b,0x34,0x85,0xbe]
-
-s_abs_i32 s5, m0
-// CHECK: [0x7c,0x34,0x85,0xbe]
-
-s_abs_i32 s5, exec_lo
-// CHECK: [0x7e,0x34,0x85,0xbe]
-
-s_abs_i32 s5, exec_hi
-// CHECK: [0x7f,0x34,0x85,0xbe]
-
-s_abs_i32 s5, 0
-// CHECK: [0x80,0x34,0x85,0xbe]
-
-s_abs_i32 s5, -1
-// CHECK: [0xc1,0x34,0x85,0xbe]
-
-s_abs_i32 s5, 0.5
-// CHECK: [0xf0,0x34,0x85,0xbe]
-
-s_abs_i32 s5, -4.0
-// CHECK: [0xf7,0x34,0x85,0xbe]
-
-s_abs_i32 s5, 0xaf123456
-// CHECK: [0xff,0x34,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_abs_i32 s5, 0x3f717273
-// CHECK: [0xff,0x34,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_add_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x80]
-
-s_add_u32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x80]
-
-s_add_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x80]
-
-s_add_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x80]
-
-s_add_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x80]
-
-s_add_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x80]
-
-s_add_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x80]
-
-s_add_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x80]
-
-s_add_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x80]
-
-s_add_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x80]
-
-s_add_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x80]
-
-s_add_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x80]
-
-s_add_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x80]
-
-s_add_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x80]
-
-s_add_u32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x80]
-
-s_add_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x80]
-
-s_add_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x80]
-
-s_add_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x80]
-
-s_add_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x80]
-
-s_add_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x80]
-
-s_add_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x80]
-
-s_add_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x80]
-
-s_add_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x80]
-
-s_add_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x80]
-
-s_add_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x80]
-
-s_add_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x80]
-
-s_add_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x80]
-
-s_add_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x80]
-
-s_add_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x80]
-
-s_add_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x80]
-
-s_add_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x80]
-
-s_add_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x80,0x56,0x34,0x12,0xaf]
-
-s_add_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x80,0x73,0x72,0x71,0x3f]
-
-s_add_u32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x80]
-
-s_add_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x80]
-
-s_add_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x80]
-
-s_add_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x80]
-
-s_add_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x80]
-
-s_add_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x80]
-
-s_add_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x80]
-
-s_add_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x80]
-
-s_add_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x80]
-
-s_add_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x80]
-
-s_add_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x80]
-
-s_add_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x80]
-
-s_add_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x80]
-
-s_add_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x80]
-
-s_add_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x80]
-
-s_add_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x80]
-
-s_add_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x80]
-
-s_add_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x80,0x56,0x34,0x12,0xaf]
-
-s_add_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x80,0x73,0x72,0x71,0x3f]
-
-s_sub_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x80]
-
-s_sub_u32 s103, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x80]
-
-s_sub_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe8,0x80]
-
-s_sub_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe9,0x80]
-
-s_sub_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x80]
-
-s_sub_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x80]
-
-s_sub_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x80]
-
-s_sub_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x80]
-
-s_sub_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x80]
-
-s_sub_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x80]
-
-s_sub_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x80]
-
-s_sub_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x80]
-
-s_sub_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x80]
-
-s_sub_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x80]
-
-s_sub_u32 s5, s103, s2
-// CHECK: [0x67,0x02,0x85,0x80]
-
-s_sub_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x85,0x80]
-
-s_sub_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x85,0x80]
-
-s_sub_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x80]
-
-s_sub_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x80]
-
-s_sub_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x80]
-
-s_sub_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x80]
-
-s_sub_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x80]
-
-s_sub_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x80]
-
-s_sub_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x80]
-
-s_sub_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x80]
-
-s_sub_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x80]
-
-s_sub_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x80]
-
-s_sub_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x80]
-
-s_sub_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x80]
-
-s_sub_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x80]
-
-s_sub_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x80]
-
-s_sub_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x80,0x56,0x34,0x12,0xaf]
-
-s_sub_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x80,0x73,0x72,0x71,0x3f]
-
-s_sub_u32 s5, s1, s103
-// CHECK: [0x01,0x67,0x85,0x80]
-
-s_sub_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x85,0x80]
-
-s_sub_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x85,0x80]
-
-s_sub_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x80]
-
-s_sub_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x80]
-
-s_sub_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x80]
-
-s_sub_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x80]
-
-s_sub_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x80]
-
-s_sub_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x80]
-
-s_sub_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x80]
-
-s_sub_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x80]
-
-s_sub_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x80]
-
-s_sub_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x80]
-
-s_sub_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x80]
-
-s_sub_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x80]
-
-s_sub_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x80]
-
-s_sub_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x80]
-
-s_sub_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x80,0x56,0x34,0x12,0xaf]
-
-s_sub_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x80,0x73,0x72,0x71,0x3f]
-
-s_add_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x81]
-
-s_add_i32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x81]
-
-s_add_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x81]
-
-s_add_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x81]
-
-s_add_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x81]
-
-s_add_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x81]
-
-s_add_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x81]
-
-s_add_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x81]
-
-s_add_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x81]
-
-s_add_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x81]
-
-s_add_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x81]
-
-s_add_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x81]
-
-s_add_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x81]
-
-s_add_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x81]
-
-s_add_i32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x81]
-
-s_add_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x81]
-
-s_add_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x81]
-
-s_add_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x81]
-
-s_add_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x81]
-
-s_add_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x81]
-
-s_add_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x81]
-
-s_add_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x81]
-
-s_add_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x81]
-
-s_add_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x81]
-
-s_add_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x81]
-
-s_add_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x81]
-
-s_add_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x81]
-
-s_add_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x81]
-
-s_add_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x81]
-
-s_add_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x81]
-
-s_add_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x81]
-
-s_add_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x81,0x56,0x34,0x12,0xaf]
-
-s_add_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x81,0x73,0x72,0x71,0x3f]
-
-s_add_i32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x81]
-
-s_add_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x81]
-
-s_add_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x81]
-
-s_add_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x81]
-
-s_add_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x81]
-
-s_add_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x81]
-
-s_add_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x81]
-
-s_add_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x81]
-
-s_add_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x81]
-
-s_add_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x81]
-
-s_add_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x81]
-
-s_add_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x81]
-
-s_add_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x81]
-
-s_add_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x81]
-
-s_add_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x81]
-
-s_add_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x81]
-
-s_add_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x81]
-
-s_add_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x81,0x56,0x34,0x12,0xaf]
-
-s_add_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x81,0x73,0x72,0x71,0x3f]
-
-s_sub_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x81]
-
-s_sub_i32 s103, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x81]
-
-s_sub_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe8,0x81]
-
-s_sub_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe9,0x81]
-
-s_sub_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x81]
-
-s_sub_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x81]
-
-s_sub_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x81]
-
-s_sub_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x81]
-
-s_sub_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x81]
-
-s_sub_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x81]
-
-s_sub_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x81]
-
-s_sub_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x81]
-
-s_sub_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x81]
-
-s_sub_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x81]
-
-s_sub_i32 s5, s103, s2
-// CHECK: [0x67,0x02,0x85,0x81]
-
-s_sub_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x85,0x81]
-
-s_sub_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x85,0x81]
-
-s_sub_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x81]
-
-s_sub_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x81]
-
-s_sub_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x81]
-
-s_sub_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x81]
-
-s_sub_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x81]
-
-s_sub_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x81]
-
-s_sub_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x81]
-
-s_sub_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x81]
-
-s_sub_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x81]
-
-s_sub_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x81]
-
-s_sub_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x81]
-
-s_sub_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x81]
-
-s_sub_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x81]
-
-s_sub_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x81]
-
-s_sub_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x81,0x56,0x34,0x12,0xaf]
-
-s_sub_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x81,0x73,0x72,0x71,0x3f]
-
-s_sub_i32 s5, s1, s103
-// CHECK: [0x01,0x67,0x85,0x81]
-
-s_sub_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x85,0x81]
-
-s_sub_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x85,0x81]
-
-s_sub_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x81]
-
-s_sub_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x81]
-
-s_sub_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x81]
-
-s_sub_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x81]
-
-s_sub_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x81]
-
-s_sub_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x81]
-
-s_sub_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x81]
-
-s_sub_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x81]
-
-s_sub_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x81]
-
-s_sub_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x81]
-
-s_sub_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x81]
-
-s_sub_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x81]
-
-s_sub_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x81]
-
-s_sub_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x81]
-
-s_sub_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x81,0x56,0x34,0x12,0xaf]
-
-s_sub_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x81,0x73,0x72,0x71,0x3f]
-
-s_addc_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x82]
-
-s_addc_u32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x82]
-
-s_addc_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x82]
-
-s_addc_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x82]
-
-s_addc_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x82]
-
-s_addc_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x82]
-
-s_addc_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x82]
-
-s_addc_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x82]
-
-s_addc_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x82]
-
-s_addc_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x82]
-
-s_addc_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x82]
-
-s_addc_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x82]
-
-s_addc_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x82]
-
-s_addc_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x82]
-
-s_addc_u32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x82]
-
-s_addc_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x82]
-
-s_addc_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x82]
-
-s_addc_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x82]
-
-s_addc_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x82]
-
-s_addc_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x82]
-
-s_addc_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x82]
-
-s_addc_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x82]
-
-s_addc_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x82]
-
-s_addc_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x82]
-
-s_addc_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x82]
-
-s_addc_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x82]
-
-s_addc_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x82]
-
-s_addc_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x82]
-
-s_addc_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x82]
-
-s_addc_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x82]
-
-s_addc_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x82]
-
-s_addc_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x82,0x56,0x34,0x12,0xaf]
-
-s_addc_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x82,0x73,0x72,0x71,0x3f]
-
-s_addc_u32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x82]
-
-s_addc_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x82]
-
-s_addc_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x82]
-
-s_addc_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x82]
-
-s_addc_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x82]
-
-s_addc_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x82]
-
-s_addc_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x82]
-
-s_addc_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x82]
-
-s_addc_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x82]
-
-s_addc_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x82]
-
-s_addc_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x82]
-
-s_addc_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x82]
-
-s_addc_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x82]
-
-s_addc_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x82]
-
-s_addc_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x82]
-
-s_addc_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x82]
-
-s_addc_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x82]
-
-s_addc_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x82,0x56,0x34,0x12,0xaf]
-
-s_addc_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x82,0x73,0x72,0x71,0x3f]
-
-s_subb_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x82]
-
-s_subb_u32 s103, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x82]
-
-s_subb_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe8,0x82]
-
-s_subb_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe9,0x82]
-
-s_subb_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x82]
-
-s_subb_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x82]
-
-s_subb_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x82]
-
-s_subb_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x82]
-
-s_subb_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x82]
-
-s_subb_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x82]
-
-s_subb_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x82]
-
-s_subb_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x82]
-
-s_subb_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x82]
-
-s_subb_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x82]
-
-s_subb_u32 s5, s103, s2
-// CHECK: [0x67,0x02,0x85,0x82]
-
-s_subb_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x85,0x82]
-
-s_subb_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x85,0x82]
-
-s_subb_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x82]
-
-s_subb_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x82]
-
-s_subb_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x82]
-
-s_subb_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x82]
-
-s_subb_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x82]
-
-s_subb_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x82]
-
-s_subb_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x82]
-
-s_subb_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x82]
-
-s_subb_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x82]
-
-s_subb_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x82]
-
-s_subb_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x82]
-
-s_subb_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x82]
-
-s_subb_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x82]
-
-s_subb_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x82]
-
-s_subb_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x82,0x56,0x34,0x12,0xaf]
-
-s_subb_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x82,0x73,0x72,0x71,0x3f]
-
-s_subb_u32 s5, s1, s103
-// CHECK: [0x01,0x67,0x85,0x82]
-
-s_subb_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x85,0x82]
-
-s_subb_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x85,0x82]
-
-s_subb_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x82]
-
-s_subb_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x82]
-
-s_subb_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x82]
-
-s_subb_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x82]
-
-s_subb_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x82]
-
-s_subb_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x82]
-
-s_subb_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x82]
-
-s_subb_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x82]
-
-s_subb_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x82]
-
-s_subb_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x82]
-
-s_subb_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x82]
-
-s_subb_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x82]
-
-s_subb_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x82]
-
-s_subb_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x82]
-
-s_subb_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x82,0x56,0x34,0x12,0xaf]
-
-s_subb_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x82,0x73,0x72,0x71,0x3f]
-
-s_min_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x83]
-
-s_min_i32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x83]
-
-s_min_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x83]
-
-s_min_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x83]
-
-s_min_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x83]
-
-s_min_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x83]
-
-s_min_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x83]
-
-s_min_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x83]
-
-s_min_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x83]
-
-s_min_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x83]
-
-s_min_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x83]
-
-s_min_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x83]
-
-s_min_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x83]
-
-s_min_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x83]
-
-s_min_i32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x83]
-
-s_min_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x83]
-
-s_min_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x83]
-
-s_min_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x83]
-
-s_min_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x83]
-
-s_min_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x83]
-
-s_min_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x83]
-
-s_min_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x83]
-
-s_min_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x83]
-
-s_min_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x83]
-
-s_min_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x83]
-
-s_min_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x83]
-
-s_min_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x83]
-
-s_min_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x83]
-
-s_min_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x83]
-
-s_min_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x83]
-
-s_min_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x83]
-
-s_min_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_i32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x83]
-
-s_min_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x83]
-
-s_min_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x83]
-
-s_min_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x83]
-
-s_min_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x83]
-
-s_min_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x83]
-
-s_min_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x83]
-
-s_min_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x83]
-
-s_min_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x83]
-
-s_min_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x83]
-
-s_min_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x83]
-
-s_min_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x83]
-
-s_min_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x83]
-
-s_min_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x83]
-
-s_min_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x83]
-
-s_min_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x83]
-
-s_min_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x83]
-
-s_min_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x83]
-
-s_min_u32 s103, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x83]
-
-s_min_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe8,0x83]
-
-s_min_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe9,0x83]
-
-s_min_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x83]
-
-s_min_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x83]
-
-s_min_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x83]
-
-s_min_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x83]
-
-s_min_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x83]
-
-s_min_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x83]
-
-s_min_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x83]
-
-s_min_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x83]
-
-s_min_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x83]
-
-s_min_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x83]
-
-s_min_u32 s5, s103, s2
-// CHECK: [0x67,0x02,0x85,0x83]
-
-s_min_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x85,0x83]
-
-s_min_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x85,0x83]
-
-s_min_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x83]
-
-s_min_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x83]
-
-s_min_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x83]
-
-s_min_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x83]
-
-s_min_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x83]
-
-s_min_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x83]
-
-s_min_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x83]
-
-s_min_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x83]
-
-s_min_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x83]
-
-s_min_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x83]
-
-s_min_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x83]
-
-s_min_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x83]
-
-s_min_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x83]
-
-s_min_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x83]
-
-s_min_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_u32 s5, s1, s103
-// CHECK: [0x01,0x67,0x85,0x83]
-
-s_min_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x85,0x83]
-
-s_min_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x85,0x83]
-
-s_min_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x83]
-
-s_min_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x83]
-
-s_min_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x83]
-
-s_min_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x83]
-
-s_min_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x83]
-
-s_min_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x83]
-
-s_min_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x83]
-
-s_min_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x83]
-
-s_min_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x83]
-
-s_min_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x83]
-
-s_min_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x83]
-
-s_min_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x83]
-
-s_min_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x83]
-
-s_min_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x83]
-
-s_min_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x83,0x73,0x72,0x71,0x3f]
-
-s_max_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x84]
-
-s_max_i32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x84]
-
-s_max_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x84]
-
-s_max_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x84]
-
-s_max_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x84]
-
-s_max_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x84]
-
-s_max_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x84]
-
-s_max_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x84]
-
-s_max_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x84]
-
-s_max_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x84]
-
-s_max_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x84]
-
-s_max_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x84]
-
-s_max_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x84]
-
-s_max_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x84]
-
-s_max_i32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x84]
-
-s_max_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x84]
-
-s_max_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x84]
-
-s_max_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x84]
-
-s_max_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x84]
-
-s_max_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x84]
-
-s_max_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x84]
-
-s_max_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x84]
-
-s_max_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x84]
-
-s_max_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x84]
-
-s_max_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x84]
-
-s_max_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x84]
-
-s_max_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x84]
-
-s_max_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x84]
-
-s_max_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x84]
-
-s_max_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x84]
-
-s_max_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x84]
-
-s_max_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_i32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x84]
-
-s_max_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x84]
-
-s_max_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x84]
-
-s_max_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x84]
-
-s_max_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x84]
-
-s_max_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x84]
-
-s_max_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x84]
-
-s_max_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x84]
-
-s_max_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x84]
-
-s_max_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x84]
-
-s_max_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x84]
-
-s_max_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x84]
-
-s_max_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x84]
-
-s_max_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x84]
-
-s_max_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x84]
-
-s_max_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x84]
-
-s_max_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x84]
-
-s_max_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x84]
-
-s_max_u32 s103, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x84]
-
-s_max_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe8,0x84]
-
-s_max_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe9,0x84]
-
-s_max_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x84]
-
-s_max_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x84]
-
-s_max_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x84]
-
-s_max_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x84]
-
-s_max_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x84]
-
-s_max_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x84]
-
-s_max_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x84]
-
-s_max_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x84]
-
-s_max_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x84]
-
-s_max_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x84]
-
-s_max_u32 s5, s103, s2
-// CHECK: [0x67,0x02,0x85,0x84]
-
-s_max_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x85,0x84]
-
-s_max_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x85,0x84]
-
-s_max_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x84]
-
-s_max_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x84]
-
-s_max_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x84]
-
-s_max_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x84]
-
-s_max_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x84]
-
-s_max_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x84]
-
-s_max_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x84]
-
-s_max_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x84]
-
-s_max_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x84]
-
-s_max_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x84]
-
-s_max_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x84]
-
-s_max_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x84]
-
-s_max_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x84]
-
-s_max_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x84]
-
-s_max_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_u32 s5, s1, s103
-// CHECK: [0x01,0x67,0x85,0x84]
-
-s_max_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x85,0x84]
-
-s_max_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x85,0x84]
-
-s_max_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x84]
-
-s_max_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x84]
-
-s_max_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x84]
-
-s_max_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x84]
-
-s_max_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x84]
-
-s_max_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x84]
-
-s_max_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x84]
-
-s_max_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x84]
-
-s_max_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x84]
-
-s_max_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x84]
-
-s_max_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x84]
-
-s_max_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x84]
-
-s_max_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x84]
-
-s_max_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x84]
-
-s_max_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x84,0x73,0x72,0x71,0x3f]
-
-s_cselect_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x85]
-
-s_cselect_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x85]
-
-s_cselect_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x85]
-
-s_cselect_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x85]
-
-s_cselect_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x85]
-
-s_cselect_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x85]
-
-s_cselect_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x85]
-
-s_cselect_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x85]
-
-s_cselect_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x85]
-
-s_cselect_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x85]
-
-s_cselect_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x85]
-
-s_cselect_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x85]
-
-s_cselect_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x85]
-
-s_cselect_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x85]
-
-s_cselect_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x85]
-
-s_cselect_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x85]
-
-s_cselect_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x85]
-
-s_cselect_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x85]
-
-s_cselect_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x85]
-
-s_cselect_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x85]
-
-s_cselect_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x85]
-
-s_cselect_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x85]
-
-s_cselect_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x85]
-
-s_cselect_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x85]
-
-s_cselect_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x85]
-
-s_cselect_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x85]
-
-s_cselect_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x85]
-
-s_cselect_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x85]
-
-s_cselect_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x85]
-
-s_cselect_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x85]
-
-s_cselect_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x85]
-
-s_cselect_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x85]
-
-s_cselect_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x85]
-
-s_cselect_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x85]
-
-s_cselect_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x85]
-
-s_cselect_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x85]
-
-s_cselect_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x85]
-
-s_cselect_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x85]
-
-s_cselect_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x85]
-
-s_cselect_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x85]
-
-s_cselect_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x85]
-
-s_cselect_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x85]
-
-s_cselect_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x85]
-
-s_cselect_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x85]
-
-s_cselect_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x85]
-
-s_cselect_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x85]
-
-s_cselect_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x85]
-
-s_cselect_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x85]
-
-s_cselect_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x85]
-
-s_cselect_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x85]
-
-s_cselect_b64 s[102:103], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x85]
-
-s_cselect_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe8,0x85]
-
-s_cselect_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x85]
-
-s_cselect_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x85]
-
-s_cselect_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x85]
-
-s_cselect_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x85]
-
-s_cselect_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x85]
-
-s_cselect_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x85,0x73,0x72,0x71,0x3f]
-
-s_and_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x87]
-
-s_and_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x87]
-
-s_and_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x87]
-
-s_and_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x87]
-
-s_and_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x87]
-
-s_and_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x87]
-
-s_and_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x87]
-
-s_and_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x87]
-
-s_and_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x87]
-
-s_and_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x87]
-
-s_and_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x87]
-
-s_and_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x87]
-
-s_and_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x87]
-
-s_and_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x87]
-
-s_and_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x87]
-
-s_and_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x87]
-
-s_and_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x87]
-
-s_and_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x87]
-
-s_and_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x87]
-
-s_and_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x87]
-
-s_and_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x87]
-
-s_and_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x87]
-
-s_and_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x87]
-
-s_and_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x87]
-
-s_and_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x87]
-
-s_and_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x87]
-
-s_and_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x87]
-
-s_and_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x87]
-
-s_and_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x87]
-
-s_and_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x87]
-
-s_and_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x87]
-
-s_and_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x87,0x56,0x34,0x12,0xaf]
-
-s_and_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x87,0x73,0x72,0x71,0x3f]
-
-s_and_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x87]
-
-s_and_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x87]
-
-s_and_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x87]
-
-s_and_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x87]
-
-s_and_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x87]
-
-s_and_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x87]
-
-s_and_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x87]
-
-s_and_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x87]
-
-s_and_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x87]
-
-s_and_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x87]
-
-s_and_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x87]
-
-s_and_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x87]
-
-s_and_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x87]
-
-s_and_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x87]
-
-s_and_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x87]
-
-s_and_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x87]
-
-s_and_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x87]
-
-s_and_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x87,0x56,0x34,0x12,0xaf]
-
-s_and_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x87,0x73,0x72,0x71,0x3f]
-
-s_and_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x87]
-
-s_and_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x87]
-
-s_and_b64 s[102:103], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x87]
-
-s_and_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe8,0x87]
-
-s_and_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x87]
-
-s_and_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x87]
-
-s_and_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x87]
-
-s_and_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x87]
-
-s_and_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x87]
-
-s_and_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x87]
-
-s_and_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x87,0x56,0x34,0x12,0xaf]
-
-s_and_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x87,0x73,0x72,0x71,0x3f]
-
-s_and_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x87]
-
-s_and_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x87,0x56,0x34,0x12,0xaf]
-
-s_and_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x87,0x73,0x72,0x71,0x3f]
-
-s_or_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x88]
-
-s_or_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x88]
-
-s_or_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x88]
-
-s_or_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x88]
-
-s_or_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x88]
-
-s_or_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x88]
-
-s_or_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x88]
-
-s_or_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x88]
-
-s_or_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x88]
-
-s_or_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x88]
-
-s_or_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x88]
-
-s_or_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x88]
-
-s_or_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x88]
-
-s_or_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x88]
-
-s_or_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x88]
-
-s_or_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x88]
-
-s_or_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x88]
-
-s_or_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x88]
-
-s_or_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x88]
-
-s_or_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x88]
-
-s_or_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x88]
-
-s_or_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x88]
-
-s_or_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x88]
-
-s_or_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x88]
-
-s_or_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x88]
-
-s_or_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x88]
-
-s_or_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x88]
-
-s_or_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x88]
-
-s_or_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x88]
-
-s_or_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x88]
-
-s_or_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x88]
-
-s_or_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x88,0x56,0x34,0x12,0xaf]
-
-s_or_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x88,0x73,0x72,0x71,0x3f]
-
-s_or_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x88]
-
-s_or_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x88]
-
-s_or_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x88]
-
-s_or_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x88]
-
-s_or_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x88]
-
-s_or_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x88]
-
-s_or_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x88]
-
-s_or_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x88]
-
-s_or_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x88]
-
-s_or_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x88]
-
-s_or_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x88]
-
-s_or_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x88]
-
-s_or_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x88]
-
-s_or_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x88]
-
-s_or_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x88]
-
-s_or_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x88]
-
-s_or_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x88]
-
-s_or_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x88,0x56,0x34,0x12,0xaf]
-
-s_or_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x88,0x73,0x72,0x71,0x3f]
-
-s_or_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x88]
-
-s_or_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x88]
-
-s_or_b64 s[102:103], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x88]
-
-s_or_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe8,0x88]
-
-s_or_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x88]
-
-s_or_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x88]
-
-s_or_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x88]
-
-s_or_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x88]
-
-s_or_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x88]
-
-s_or_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x88]
-
-s_or_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x88,0x56,0x34,0x12,0xaf]
-
-s_or_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x88,0x73,0x72,0x71,0x3f]
-
-s_or_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x88]
-
-s_or_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x88,0x56,0x34,0x12,0xaf]
-
-s_or_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x88,0x73,0x72,0x71,0x3f]
-
-s_xor_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x89]
-
-s_xor_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x89]
-
-s_xor_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x89]
-
-s_xor_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x89]
-
-s_xor_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x89]
-
-s_xor_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x89]
-
-s_xor_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x89]
-
-s_xor_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x89]
-
-s_xor_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x89]
-
-s_xor_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x89]
-
-s_xor_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x89]
-
-s_xor_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x89]
-
-s_xor_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x89]
-
-s_xor_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x89]
-
-s_xor_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x89]
-
-s_xor_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x89]
-
-s_xor_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x89]
-
-s_xor_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x89]
-
-s_xor_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x89]
-
-s_xor_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x89]
-
-s_xor_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x89]
-
-s_xor_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x89]
-
-s_xor_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x89]
-
-s_xor_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x89]
-
-s_xor_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x89]
-
-s_xor_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x89]
-
-s_xor_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x89]
-
-s_xor_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x89]
-
-s_xor_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x89]
-
-s_xor_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x89]
-
-s_xor_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x89]
-
-s_xor_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x89,0x56,0x34,0x12,0xaf]
-
-s_xor_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x89,0x73,0x72,0x71,0x3f]
-
-s_xor_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x89]
-
-s_xor_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x89]
-
-s_xor_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x89]
-
-s_xor_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x89]
-
-s_xor_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x89]
-
-s_xor_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x89]
-
-s_xor_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x89]
-
-s_xor_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x89]
-
-s_xor_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x89]
-
-s_xor_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x89]
-
-s_xor_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x89]
-
-s_xor_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x89]
-
-s_xor_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x89]
-
-s_xor_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x89]
-
-s_xor_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x89]
-
-s_xor_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x89]
-
-s_xor_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x89]
-
-s_xor_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x89,0x56,0x34,0x12,0xaf]
-
-s_xor_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x89,0x73,0x72,0x71,0x3f]
-
-s_xor_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x89]
-
-s_xor_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x89]
-
-s_xor_b64 s[102:103], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x89]
-
-s_xor_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe8,0x89]
-
-s_xor_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x89]
-
-s_xor_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x89]
-
-s_xor_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x89]
-
-s_xor_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x89]
-
-s_xor_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x89]
-
-s_xor_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x89]
-
-s_xor_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x89,0x56,0x34,0x12,0xaf]
-
-s_xor_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x89,0x73,0x72,0x71,0x3f]
-
-s_xor_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x89]
-
-s_xor_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x89,0x56,0x34,0x12,0xaf]
-
-s_xor_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x89,0x73,0x72,0x71,0x3f]
-
-s_andn2_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8a]
-
-s_andn2_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8a]
-
-s_andn2_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x8a]
-
-s_andn2_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x8a]
-
-s_andn2_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8a]
-
-s_andn2_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8a]
-
-s_andn2_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8a]
-
-s_andn2_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8a]
-
-s_andn2_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8a]
-
-s_andn2_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8a]
-
-s_andn2_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8a]
-
-s_andn2_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8a]
-
-s_andn2_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8a]
-
-s_andn2_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8a]
-
-s_andn2_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8a]
-
-s_andn2_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8a,0x56,0x34,0x12,0xaf]
-
-s_andn2_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8a,0x73,0x72,0x71,0x3f]
-
-s_andn2_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x8a]
-
-s_andn2_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x8a]
-
-s_andn2_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x8a]
-
-s_andn2_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8a]
-
-s_andn2_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8a]
-
-s_andn2_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8a]
-
-s_andn2_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8a]
-
-s_andn2_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8a]
-
-s_andn2_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8a]
-
-s_andn2_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8a]
-
-s_andn2_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8a]
-
-s_andn2_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8a]
-
-s_andn2_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8a]
-
-s_andn2_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8a]
-
-s_andn2_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8a]
-
-s_andn2_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8a]
-
-s_andn2_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8a]
-
-s_andn2_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8a,0x56,0x34,0x12,0xaf]
-
-s_andn2_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8a,0x73,0x72,0x71,0x3f]
-
-s_andn2_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8a]
-
-s_andn2_b64 s[102:103], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8a]
-
-s_andn2_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe8,0x8a]
-
-s_andn2_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8a]
-
-s_andn2_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x8a]
-
-s_andn2_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x8a]
-
-s_andn2_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x8a]
-
-s_andn2_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8a]
-
-s_andn2_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8a,0x56,0x34,0x12,0xaf]
-
-s_andn2_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8a,0x73,0x72,0x71,0x3f]
-
-s_andn2_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8a]
-
-s_andn2_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8a,0x56,0x34,0x12,0xaf]
-
-s_andn2_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8a,0x73,0x72,0x71,0x3f]
-
-s_orn2_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8b]
-
-s_orn2_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8b]
-
-s_orn2_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x8b]
-
-s_orn2_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x8b]
-
-s_orn2_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8b]
-
-s_orn2_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8b]
-
-s_orn2_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8b]
-
-s_orn2_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8b]
-
-s_orn2_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8b]
-
-s_orn2_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8b]
-
-s_orn2_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8b]
-
-s_orn2_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8b]
-
-s_orn2_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8b]
-
-s_orn2_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8b]
-
-s_orn2_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8b]
-
-s_orn2_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8b,0x56,0x34,0x12,0xaf]
-
-s_orn2_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8b,0x73,0x72,0x71,0x3f]
-
-s_orn2_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x8b]
-
-s_orn2_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x8b]
-
-s_orn2_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x8b]
-
-s_orn2_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8b]
-
-s_orn2_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8b]
-
-s_orn2_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8b]
-
-s_orn2_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8b]
-
-s_orn2_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8b]
-
-s_orn2_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8b]
-
-s_orn2_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8b]
-
-s_orn2_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8b]
-
-s_orn2_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8b]
-
-s_orn2_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8b]
-
-s_orn2_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8b]
-
-s_orn2_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8b]
-
-s_orn2_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8b]
-
-s_orn2_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8b]
-
-s_orn2_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8b,0x56,0x34,0x12,0xaf]
-
-s_orn2_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8b,0x73,0x72,0x71,0x3f]
-
-s_orn2_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8b]
-
-s_orn2_b64 s[102:103], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8b]
-
-s_orn2_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe8,0x8b]
-
-s_orn2_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8b]
-
-s_orn2_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x8b]
-
-s_orn2_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x8b]
-
-s_orn2_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x8b]
-
-s_orn2_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8b]
-
-s_orn2_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8b,0x56,0x34,0x12,0xaf]
-
-s_orn2_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8b,0x73,0x72,0x71,0x3f]
-
-s_orn2_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8b]
-
-s_orn2_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8b,0x56,0x34,0x12,0xaf]
-
-s_orn2_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8b,0x73,0x72,0x71,0x3f]
-
-s_nand_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8c]
-
-s_nand_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8c]
-
-s_nand_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x8c]
-
-s_nand_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x8c]
-
-s_nand_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8c]
-
-s_nand_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8c]
-
-s_nand_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8c]
-
-s_nand_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8c]
-
-s_nand_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8c]
-
-s_nand_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8c]
-
-s_nand_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8c]
-
-s_nand_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8c]
-
-s_nand_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8c]
-
-s_nand_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8c]
-
-s_nand_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x8c]
-
-s_nand_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x8c]
-
-s_nand_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x8c]
-
-s_nand_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8c]
-
-s_nand_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8c]
-
-s_nand_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8c]
-
-s_nand_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8c]
-
-s_nand_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8c]
-
-s_nand_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8c]
-
-s_nand_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8c]
-
-s_nand_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8c]
-
-s_nand_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8c]
-
-s_nand_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8c]
-
-s_nand_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8c]
-
-s_nand_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8c]
-
-s_nand_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8c]
-
-s_nand_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8c]
-
-s_nand_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nand_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nand_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x8c]
-
-s_nand_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x8c]
-
-s_nand_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x8c]
-
-s_nand_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8c]
-
-s_nand_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8c]
-
-s_nand_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8c]
-
-s_nand_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8c]
-
-s_nand_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8c]
-
-s_nand_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8c]
-
-s_nand_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8c]
-
-s_nand_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8c]
-
-s_nand_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8c]
-
-s_nand_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8c]
-
-s_nand_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8c]
-
-s_nand_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8c]
-
-s_nand_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8c]
-
-s_nand_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8c]
-
-s_nand_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nand_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nand_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8c]
-
-s_nand_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8c]
-
-s_nand_b64 s[102:103], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8c]
-
-s_nand_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe8,0x8c]
-
-s_nand_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8c]
-
-s_nand_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x8c]
-
-s_nand_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x8c]
-
-s_nand_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x8c]
-
-s_nand_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8c]
-
-s_nand_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8c]
-
-s_nand_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nand_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nand_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8c]
-
-s_nand_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nand_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nor_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8d]
-
-s_nor_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8d]
-
-s_nor_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x8d]
-
-s_nor_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x8d]
-
-s_nor_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8d]
-
-s_nor_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8d]
-
-s_nor_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8d]
-
-s_nor_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8d]
-
-s_nor_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8d]
-
-s_nor_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8d]
-
-s_nor_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8d]
-
-s_nor_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8d]
-
-s_nor_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8d]
-
-s_nor_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8d]
-
-s_nor_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x8d]
-
-s_nor_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x8d]
-
-s_nor_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x8d]
-
-s_nor_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8d]
-
-s_nor_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8d]
-
-s_nor_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8d]
-
-s_nor_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8d]
-
-s_nor_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8d]
-
-s_nor_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8d]
-
-s_nor_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8d]
-
-s_nor_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8d]
-
-s_nor_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8d]
-
-s_nor_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8d]
-
-s_nor_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8d]
-
-s_nor_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8d]
-
-s_nor_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8d]
-
-s_nor_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8d]
-
-s_nor_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8d,0x56,0x34,0x12,0xaf]
-
-s_nor_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8d,0x73,0x72,0x71,0x3f]
-
-s_nor_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x8d]
-
-s_nor_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x8d]
-
-s_nor_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x8d]
-
-s_nor_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8d]
-
-s_nor_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8d]
-
-s_nor_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8d]
-
-s_nor_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8d]
-
-s_nor_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8d]
-
-s_nor_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8d]
-
-s_nor_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8d]
-
-s_nor_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8d]
-
-s_nor_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8d]
-
-s_nor_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8d]
-
-s_nor_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8d]
-
-s_nor_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8d]
-
-s_nor_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8d]
-
-s_nor_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8d]
-
-s_nor_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8d,0x56,0x34,0x12,0xaf]
-
-s_nor_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8d,0x73,0x72,0x71,0x3f]
-
-s_nor_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8d]
-
-s_nor_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8d]
-
-s_nor_b64 s[102:103], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8d]
-
-s_nor_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe8,0x8d]
-
-s_nor_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8d]
-
-s_nor_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x8d]
-
-s_nor_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x8d]
-
-s_nor_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x8d]
-
-s_nor_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8d]
-
-s_nor_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8d]
-
-s_nor_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8d,0x56,0x34,0x12,0xaf]
-
-s_nor_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8d,0x73,0x72,0x71,0x3f]
-
-s_nor_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8d]
-
-s_nor_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8d,0x56,0x34,0x12,0xaf]
-
-s_nor_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8d,0x73,0x72,0x71,0x3f]
-
-s_xnor_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8e]
-
-s_xnor_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8e]
-
-s_xnor_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x8e]
-
-s_xnor_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x8e]
-
-s_xnor_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8e]
-
-s_xnor_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8e]
-
-s_xnor_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8e]
-
-s_xnor_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8e]
-
-s_xnor_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8e]
-
-s_xnor_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8e]
-
-s_xnor_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8e]
-
-s_xnor_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8e]
-
-s_xnor_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8e]
-
-s_xnor_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8e]
-
-s_xnor_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8e]
-
-s_xnor_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8e,0x56,0x34,0x12,0xaf]
-
-s_xnor_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8e,0x73,0x72,0x71,0x3f]
-
-s_xnor_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x8e]
-
-s_xnor_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x8e]
-
-s_xnor_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x8e]
-
-s_xnor_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8e]
-
-s_xnor_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8e]
-
-s_xnor_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8e]
-
-s_xnor_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8e]
-
-s_xnor_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8e]
-
-s_xnor_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8e]
-
-s_xnor_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8e]
-
-s_xnor_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8e]
-
-s_xnor_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8e]
-
-s_xnor_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8e]
-
-s_xnor_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8e]
-
-s_xnor_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8e]
-
-s_xnor_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8e]
-
-s_xnor_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8e]
-
-s_xnor_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8e,0x56,0x34,0x12,0xaf]
-
-s_xnor_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8e,0x73,0x72,0x71,0x3f]
-
-s_xnor_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8e]
-
-s_xnor_b64 s[102:103], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8e]
-
-s_xnor_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe8,0x8e]
-
-s_xnor_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8e]
-
-s_xnor_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x8e]
-
-s_xnor_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x8e]
-
-s_xnor_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x8e]
-
-s_xnor_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8e]
-
-s_xnor_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8e,0x56,0x34,0x12,0xaf]
-
-s_xnor_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8e,0x73,0x72,0x71,0x3f]
-
-s_xnor_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8e]
-
-s_xnor_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8e,0x56,0x34,0x12,0xaf]
-
-s_xnor_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8e,0x73,0x72,0x71,0x3f]
-
-s_lshl_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8f]
-
-s_lshl_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8f]
-
-s_lshl_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x8f]
-
-s_lshl_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x8f]
-
-s_lshl_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8f]
-
-s_lshl_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8f]
-
-s_lshl_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8f]
-
-s_lshl_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8f]
-
-s_lshl_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8f]
-
-s_lshl_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8f]
-
-s_lshl_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8f]
-
-s_lshl_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8f]
-
-s_lshl_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8f]
-
-s_lshl_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8f]
-
-s_lshl_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8f]
-
-s_lshl_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshl_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshl_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x8f]
-
-s_lshl_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x8f]
-
-s_lshl_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x8f]
-
-s_lshl_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8f]
-
-s_lshl_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8f]
-
-s_lshl_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8f]
-
-s_lshl_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8f]
-
-s_lshl_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8f]
-
-s_lshl_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8f]
-
-s_lshl_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8f]
-
-s_lshl_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8f]
-
-s_lshl_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8f]
-
-s_lshl_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8f]
-
-s_lshl_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8f]
-
-s_lshl_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8f]
-
-s_lshl_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8f]
-
-s_lshl_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8f]
-
-s_lshl_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshl_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshl_b64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x8f]
-
-s_lshl_b64 s[102:103], s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x8f]
-
-s_lshl_b64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe8,0x8f]
-
-s_lshl_b64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x8f]
-
-s_lshl_b64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0xec,0x8f]
-
-s_lshl_b64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0xee,0x8f]
-
-s_lshl_b64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0xfa,0x8f]
-
-s_lshl_b64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x8f]
-
-s_lshl_b64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[102:103], s2
-// CHECK: [0x66,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], flat_scratch, s2
-// CHECK: [0x68,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshl_b64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshl_b64 s[10:11], s[2:3], s103
-// CHECK: [0x02,0x67,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x68,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x69,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8f]
-
-s_lshl_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshl_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshr_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x90]
-
-s_lshr_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x90]
-
-s_lshr_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x90]
-
-s_lshr_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x90]
-
-s_lshr_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x90]
-
-s_lshr_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x90]
-
-s_lshr_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x90]
-
-s_lshr_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x90]
-
-s_lshr_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x90]
-
-s_lshr_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x90]
-
-s_lshr_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x90]
-
-s_lshr_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x90]
-
-s_lshr_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x90]
-
-s_lshr_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x90]
-
-s_lshr_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x90]
-
-s_lshr_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x90]
-
-s_lshr_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x90]
-
-s_lshr_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x90]
-
-s_lshr_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x90]
-
-s_lshr_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x90]
-
-s_lshr_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x90]
-
-s_lshr_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x90]
-
-s_lshr_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x90]
-
-s_lshr_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x90]
-
-s_lshr_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x90]
-
-s_lshr_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x90]
-
-s_lshr_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x90]
-
-s_lshr_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x90]
-
-s_lshr_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x90]
-
-s_lshr_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x90]
-
-s_lshr_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x90]
-
-s_lshr_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x90,0x56,0x34,0x12,0xaf]
-
-s_lshr_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x90,0x73,0x72,0x71,0x3f]
-
-s_lshr_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x90]
-
-s_lshr_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x90]
-
-s_lshr_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x90]
-
-s_lshr_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x90]
-
-s_lshr_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x90]
-
-s_lshr_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x90]
-
-s_lshr_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x90]
-
-s_lshr_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x90]
-
-s_lshr_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x90]
-
-s_lshr_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x90]
-
-s_lshr_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x90]
-
-s_lshr_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x90]
-
-s_lshr_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x90]
-
-s_lshr_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x90]
-
-s_lshr_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x90]
-
-s_lshr_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x90]
-
-s_lshr_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x90]
-
-s_lshr_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x90,0x56,0x34,0x12,0xaf]
-
-s_lshr_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x90,0x73,0x72,0x71,0x3f]
-
-s_lshr_b64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x90]
-
-s_lshr_b64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x90]
-
-s_lshr_b64 s[102:103], s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x90]
-
-s_lshr_b64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe8,0x90]
-
-s_lshr_b64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x90]
-
-s_lshr_b64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0xec,0x90]
-
-s_lshr_b64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0xee,0x90]
-
-s_lshr_b64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0xfa,0x90]
-
-s_lshr_b64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x90]
-
-s_lshr_b64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[102:103], s2
-// CHECK: [0x66,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], flat_scratch, s2
-// CHECK: [0x68,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x90]
-
-s_lshr_b64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x90,0x56,0x34,0x12,0xaf]
-
-s_lshr_b64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x90,0x73,0x72,0x71,0x3f]
-
-s_lshr_b64 s[10:11], s[2:3], s103
-// CHECK: [0x02,0x67,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x68,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x69,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x90]
-
-s_lshr_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x90,0x56,0x34,0x12,0xaf]
-
-s_lshr_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x90,0x73,0x72,0x71,0x3f]
-
-s_ashr_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x91]
-
-s_ashr_i32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x91]
-
-s_ashr_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x91]
-
-s_ashr_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x91]
-
-s_ashr_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x91]
-
-s_ashr_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x91]
-
-s_ashr_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x91]
-
-s_ashr_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x91]
-
-s_ashr_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x91]
-
-s_ashr_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x91]
-
-s_ashr_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x91]
-
-s_ashr_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x91]
-
-s_ashr_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x91]
-
-s_ashr_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x91]
-
-s_ashr_i32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x91]
-
-s_ashr_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x91]
-
-s_ashr_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x91]
-
-s_ashr_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x91]
-
-s_ashr_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x91]
-
-s_ashr_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x91]
-
-s_ashr_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x91]
-
-s_ashr_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x91]
-
-s_ashr_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x91]
-
-s_ashr_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x91]
-
-s_ashr_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x91]
-
-s_ashr_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x91]
-
-s_ashr_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x91]
-
-s_ashr_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x91]
-
-s_ashr_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x91]
-
-s_ashr_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x91]
-
-s_ashr_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x91]
-
-s_ashr_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x91,0x56,0x34,0x12,0xaf]
-
-s_ashr_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x91,0x73,0x72,0x71,0x3f]
-
-s_ashr_i32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x91]
-
-s_ashr_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x91]
-
-s_ashr_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x91]
-
-s_ashr_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x91]
-
-s_ashr_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x91]
-
-s_ashr_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x91]
-
-s_ashr_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x91]
-
-s_ashr_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x91]
-
-s_ashr_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x91]
-
-s_ashr_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x91]
-
-s_ashr_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x91]
-
-s_ashr_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x91]
-
-s_ashr_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x91]
-
-s_ashr_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x91]
-
-s_ashr_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x91]
-
-s_ashr_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x91]
-
-s_ashr_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x91]
-
-s_ashr_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x91,0x56,0x34,0x12,0xaf]
-
-s_ashr_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x91,0x73,0x72,0x71,0x3f]
-
-s_ashr_i64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x91]
-
-s_ashr_i64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x91]
-
-s_ashr_i64 s[102:103], s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x91]
-
-s_ashr_i64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe8,0x91]
-
-s_ashr_i64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x91]
-
-s_ashr_i64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0xec,0x91]
-
-s_ashr_i64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0xee,0x91]
-
-s_ashr_i64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0xfa,0x91]
-
-s_ashr_i64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x91]
-
-s_ashr_i64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[102:103], s2
-// CHECK: [0x66,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], flat_scratch, s2
-// CHECK: [0x68,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x91]
-
-s_ashr_i64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x91,0x56,0x34,0x12,0xaf]
-
-s_ashr_i64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x91,0x73,0x72,0x71,0x3f]
-
-s_ashr_i64 s[10:11], s[2:3], s103
-// CHECK: [0x02,0x67,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x68,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x69,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x91]
-
-s_ashr_i64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x91,0x56,0x34,0x12,0xaf]
-
-s_ashr_i64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x91,0x73,0x72,0x71,0x3f]
-
-s_bfm_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x92]
-
-s_bfm_b32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x92]
-
-s_bfm_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x92]
-
-s_bfm_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x92]
-
-s_bfm_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x92]
-
-s_bfm_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x92]
-
-s_bfm_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x92]
-
-s_bfm_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x92]
-
-s_bfm_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x92]
-
-s_bfm_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x92]
-
-s_bfm_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x92]
-
-s_bfm_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x92]
-
-s_bfm_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x92]
-
-s_bfm_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x92]
-
-s_bfm_b32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x92]
-
-s_bfm_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x92]
-
-s_bfm_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x92]
-
-s_bfm_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x92]
-
-s_bfm_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x92]
-
-s_bfm_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x92]
-
-s_bfm_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x92]
-
-s_bfm_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x92]
-
-s_bfm_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x92]
-
-s_bfm_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x92]
-
-s_bfm_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x92]
-
-s_bfm_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x92]
-
-s_bfm_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x92]
-
-s_bfm_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x92]
-
-s_bfm_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x92]
-
-s_bfm_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x92]
-
-s_bfm_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x92]
-
-s_bfm_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfm_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfm_b32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x92]
-
-s_bfm_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x92]
-
-s_bfm_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x92]
-
-s_bfm_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x92]
-
-s_bfm_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x92]
-
-s_bfm_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x92]
-
-s_bfm_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x92]
-
-s_bfm_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x92]
-
-s_bfm_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x92]
-
-s_bfm_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x92]
-
-s_bfm_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x92]
-
-s_bfm_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x92]
-
-s_bfm_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x92]
-
-s_bfm_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x92]
-
-s_bfm_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x92]
-
-s_bfm_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x92]
-
-s_bfm_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x92]
-
-s_bfm_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfm_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfm_b64 s[10:11], s1, s2
-// CHECK: [0x01,0x02,0x8a,0x92]
-
-s_bfm_b64 s[12:13], s1, s2
-// CHECK: [0x01,0x02,0x8c,0x92]
-
-s_bfm_b64 s[102:103], s1, s2
-// CHECK: [0x01,0x02,0xe6,0x92]
-
-s_bfm_b64 flat_scratch, s1, s2
-// CHECK: [0x01,0x02,0xe8,0x92]
-
-s_bfm_b64 vcc, s1, s2
-// CHECK: [0x01,0x02,0xea,0x92]
-
-s_bfm_b64 tba, s1, s2
-// CHECK: [0x01,0x02,0xec,0x92]
-
-s_bfm_b64 tma, s1, s2
-// CHECK: [0x01,0x02,0xee,0x92]
-
-s_bfm_b64 ttmp[10:11], s1, s2
-// CHECK: [0x01,0x02,0xfa,0x92]
-
-s_bfm_b64 exec, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x92]
-
-s_bfm_b64 s[10:11], s103, s2
-// CHECK: [0x67,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], vcc_lo, s2
-// CHECK: [0x6a,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], vcc_hi, s2
-// CHECK: [0x6b,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], tba_lo, s2
-// CHECK: [0x6c,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], tba_hi, s2
-// CHECK: [0x6d,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], tma_lo, s2
-// CHECK: [0x6e,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], tma_hi, s2
-// CHECK: [0x6f,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], ttmp11, s2
-// CHECK: [0x7b,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], m0, s2
-// CHECK: [0x7c,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], exec_lo, s2
-// CHECK: [0x7e,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], exec_hi, s2
-// CHECK: [0x7f,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x92]
-
-s_bfm_b64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfm_b64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfm_b64 s[10:11], s1, s103
-// CHECK: [0x01,0x67,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, vcc_lo
-// CHECK: [0x01,0x6a,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, vcc_hi
-// CHECK: [0x01,0x6b,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, tba_lo
-// CHECK: [0x01,0x6c,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, tba_hi
-// CHECK: [0x01,0x6d,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, tma_lo
-// CHECK: [0x01,0x6e,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, tma_hi
-// CHECK: [0x01,0x6f,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, ttmp11
-// CHECK: [0x01,0x7b,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, m0
-// CHECK: [0x01,0x7c,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, exec_lo
-// CHECK: [0x01,0x7e,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, exec_hi
-// CHECK: [0x01,0x7f,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, 0
-// CHECK: [0x01,0x80,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, -1
-// CHECK: [0x01,0xc1,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, 0.5
-// CHECK: [0x01,0xf0,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, -4.0
-// CHECK: [0x01,0xf7,0x8a,0x92]
-
-s_bfm_b64 s[10:11], s1, 0xaf123456
-// CHECK: [0x01,0xff,0x8a,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfm_b64 s[10:11], s1, 0x3f717273
-// CHECK: [0x01,0xff,0x8a,0x92,0x73,0x72,0x71,0x3f]
-
-s_mul_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x93]
-
-s_mul_i32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x93]
-
-s_mul_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x93]
-
-s_mul_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x93]
-
-s_mul_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x93]
-
-s_mul_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x93]
-
-s_mul_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x93]
-
-s_mul_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x93]
-
-s_mul_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x93]
-
-s_mul_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x93]
-
-s_mul_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x93]
-
-s_mul_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x93]
-
-s_mul_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x93]
-
-s_mul_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x93]
-
-s_mul_i32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x93]
-
-s_mul_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x93]
-
-s_mul_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x93]
-
-s_mul_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x93]
-
-s_mul_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x93]
-
-s_mul_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x93]
-
-s_mul_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x93]
-
-s_mul_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x93]
-
-s_mul_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x93]
-
-s_mul_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x93]
-
-s_mul_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x93]
-
-s_mul_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x93]
-
-s_mul_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x93]
-
-s_mul_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x93]
-
-s_mul_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x93]
-
-s_mul_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x93]
-
-s_mul_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x93]
-
-s_mul_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x93,0x56,0x34,0x12,0xaf]
-
-s_mul_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x93,0x73,0x72,0x71,0x3f]
-
-s_mul_i32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x93]
-
-s_mul_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x93]
-
-s_mul_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x93]
-
-s_mul_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x93]
-
-s_mul_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x93]
-
-s_mul_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x93]
-
-s_mul_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x93]
-
-s_mul_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x93]
-
-s_mul_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x93]
-
-s_mul_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x93]
-
-s_mul_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x93]
-
-s_mul_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x93]
-
-s_mul_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x93]
-
-s_mul_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x93]
-
-s_mul_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x93]
-
-s_mul_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x93]
-
-s_mul_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x93]
-
-s_mul_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x93,0x56,0x34,0x12,0xaf]
-
-s_mul_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x93]
-
-s_bfe_u32 s103, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x93]
-
-s_bfe_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe8,0x93]
-
-s_bfe_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe9,0x93]
-
-s_bfe_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x93]
-
-s_bfe_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x93]
-
-s_bfe_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x93]
-
-s_bfe_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x93]
-
-s_bfe_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x93]
-
-s_bfe_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x93]
-
-s_bfe_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x93]
-
-s_bfe_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x93]
-
-s_bfe_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x93]
-
-s_bfe_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x93]
-
-s_bfe_u32 s5, s103, s2
-// CHECK: [0x67,0x02,0x85,0x93]
-
-s_bfe_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x85,0x93]
-
-s_bfe_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x85,0x93]
-
-s_bfe_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x93]
-
-s_bfe_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x93]
-
-s_bfe_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x93]
-
-s_bfe_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x93]
-
-s_bfe_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x93]
-
-s_bfe_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x93]
-
-s_bfe_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x93]
-
-s_bfe_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x93]
-
-s_bfe_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x93]
-
-s_bfe_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x93]
-
-s_bfe_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x93]
-
-s_bfe_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x93]
-
-s_bfe_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x93]
-
-s_bfe_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x93]
-
-s_bfe_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_u32 s5, s1, s103
-// CHECK: [0x01,0x67,0x85,0x93]
-
-s_bfe_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x85,0x93]
-
-s_bfe_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x85,0x93]
-
-s_bfe_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x93]
-
-s_bfe_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x93]
-
-s_bfe_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x93]
-
-s_bfe_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x93]
-
-s_bfe_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x93]
-
-s_bfe_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x93]
-
-s_bfe_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x93]
-
-s_bfe_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x93]
-
-s_bfe_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x93]
-
-s_bfe_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x93]
-
-s_bfe_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x93]
-
-s_bfe_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x93]
-
-s_bfe_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x93]
-
-s_bfe_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x93]
-
-s_bfe_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x94]
-
-s_bfe_i32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x94]
-
-s_bfe_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x94]
-
-s_bfe_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x94]
-
-s_bfe_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x94]
-
-s_bfe_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x94]
-
-s_bfe_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x94]
-
-s_bfe_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x94]
-
-s_bfe_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x94]
-
-s_bfe_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x94]
-
-s_bfe_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x94]
-
-s_bfe_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x94]
-
-s_bfe_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x94]
-
-s_bfe_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x94]
-
-s_bfe_i32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x94]
-
-s_bfe_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x94]
-
-s_bfe_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x94]
-
-s_bfe_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x94]
-
-s_bfe_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x94]
-
-s_bfe_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x94]
-
-s_bfe_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x94]
-
-s_bfe_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x94]
-
-s_bfe_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x94]
-
-s_bfe_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x94]
-
-s_bfe_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x94]
-
-s_bfe_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x94]
-
-s_bfe_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x94]
-
-s_bfe_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x94]
-
-s_bfe_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x94]
-
-s_bfe_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x94]
-
-s_bfe_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x94]
-
-s_bfe_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_i32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x94]
-
-s_bfe_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x94]
-
-s_bfe_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x94]
-
-s_bfe_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x94]
-
-s_bfe_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x94]
-
-s_bfe_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x94]
-
-s_bfe_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x94]
-
-s_bfe_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x94]
-
-s_bfe_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x94]
-
-s_bfe_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x94]
-
-s_bfe_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x94]
-
-s_bfe_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x94]
-
-s_bfe_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x94]
-
-s_bfe_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x94]
-
-s_bfe_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x94]
-
-s_bfe_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x94]
-
-s_bfe_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x94]
-
-s_bfe_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_u64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x94]
-
-s_bfe_u64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x94]
-
-s_bfe_u64 s[102:103], s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x94]
-
-s_bfe_u64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe8,0x94]
-
-s_bfe_u64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x94]
-
-s_bfe_u64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0xec,0x94]
-
-s_bfe_u64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0xee,0x94]
-
-s_bfe_u64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0xfa,0x94]
-
-s_bfe_u64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x94]
-
-s_bfe_u64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[102:103], s2
-// CHECK: [0x66,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], flat_scratch, s2
-// CHECK: [0x68,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x94]
-
-s_bfe_u64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_u64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_u64 s[10:11], s[2:3], s103
-// CHECK: [0x02,0x67,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x68,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x69,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x94]
-
-s_bfe_u64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_u64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_i64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x0a,0x95]
-
-s_bfe_i64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x0c,0x95]
-
-s_bfe_i64 s[102:103], s[2:3], s2
-// CHECK: [0x02,0x02,0x66,0x95]
-
-s_bfe_i64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0x68,0x95]
-
-s_bfe_i64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0x6a,0x95]
-
-s_bfe_i64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0x6c,0x95]
-
-s_bfe_i64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0x6e,0x95]
-
-s_bfe_i64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x7a,0x95]
-
-s_bfe_i64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0x7e,0x95]
-
-s_bfe_i64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[102:103], s2
-// CHECK: [0x66,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], flat_scratch, s2
-// CHECK: [0x68,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x0a,0x95]
-
-s_bfe_i64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0a,0x95,0x56,0x34,0x12,0xaf]
-
-s_bfe_i64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0a,0x95,0x73,0x72,0x71,0x3f]
-
-s_bfe_i64 s[10:11], s[2:3], s103
-// CHECK: [0x02,0x67,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x68,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x69,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x0a,0x95]
-
-s_bfe_i64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x0a,0x95,0x56,0x34,0x12,0xaf]
-
-s_bfe_i64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x0a,0x95,0x73,0x72,0x71,0x3f]
-
-s_cbranch_g_fork s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x80,0x95]
-
-s_cbranch_g_fork s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x80,0x95]
-
-s_cbranch_g_fork s[102:103], s[4:5]
-// CHECK: [0x66,0x04,0x80,0x95]
-
-s_cbranch_g_fork flat_scratch, s[4:5]
-// CHECK: [0x68,0x04,0x80,0x95]
-
-s_cbranch_g_fork vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x80,0x95]
-
-s_cbranch_g_fork tba, s[4:5]
-// CHECK: [0x6c,0x04,0x80,0x95]
-
-s_cbranch_g_fork tma, s[4:5]
-// CHECK: [0x6e,0x04,0x80,0x95]
-
-s_cbranch_g_fork ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x80,0x95]
-
-s_cbranch_g_fork exec, s[4:5]
-// CHECK: [0x7e,0x04,0x80,0x95]
-
-s_cbranch_g_fork 0, s[4:5]
-// CHECK: [0x80,0x04,0x80,0x95]
-
-s_cbranch_g_fork -1, s[4:5]
-// CHECK: [0xc1,0x04,0x80,0x95]
-
-s_cbranch_g_fork 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x80,0x95]
-
-s_cbranch_g_fork -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], s[102:103]
-// CHECK: [0x02,0x66,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], flat_scratch
-// CHECK: [0x02,0x68,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], vcc
-// CHECK: [0x02,0x6a,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], tba
-// CHECK: [0x02,0x6c,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], tma
-// CHECK: [0x02,0x6e,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], exec
-// CHECK: [0x02,0x7e,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], 0
-// CHECK: [0x02,0x80,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], -1
-// CHECK: [0x02,0xc1,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x80,0x95]
-
-s_cbranch_g_fork s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x80,0x95]
-
-s_absdiff_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x96]
-
-s_absdiff_i32 s103, s1, s2
-// CHECK: [0x01,0x02,0x67,0x96]
-
-s_absdiff_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x68,0x96]
-
-s_absdiff_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x69,0x96]
-
-s_absdiff_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x96]
-
-s_absdiff_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x96]
-
-s_absdiff_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x96]
-
-s_absdiff_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x96]
-
-s_absdiff_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x96]
-
-s_absdiff_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x96]
-
-s_absdiff_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x96]
-
-s_absdiff_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x96]
-
-s_absdiff_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x96]
-
-s_absdiff_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x96]
-
-s_absdiff_i32 s5, s103, s2
-// CHECK: [0x67,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x96]
-
-s_absdiff_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x96,0x56,0x34,0x12,0xaf]
-
-s_absdiff_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x96,0x73,0x72,0x71,0x3f]
-
-s_absdiff_i32 s5, s1, s103
-// CHECK: [0x01,0x67,0x05,0x96]
-
-s_absdiff_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0x96]
-
-s_absdiff_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0x96]
-
-s_absdiff_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x96]
-
-s_absdiff_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x96]
-
-s_absdiff_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x96]
-
-s_absdiff_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x96]
-
-s_absdiff_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x96]
-
-s_absdiff_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x96]
-
-s_absdiff_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x96]
-
-s_absdiff_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x96]
-
-s_absdiff_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x96]
-
-s_absdiff_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x96]
-
-s_absdiff_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x96]
-
-s_absdiff_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x96]
-
-s_absdiff_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x96]
-
-s_absdiff_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x96]
-
-s_absdiff_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x96,0x56,0x34,0x12,0xaf]
-
-s_absdiff_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x96,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_i32 s1, s2
-// CHECK: [0x01,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 s103, s2
-// CHECK: [0x67,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 m0, s2
-// CHECK: [0x7c,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 0, s2
-// CHECK: [0x80,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 -1, s2
-// CHECK: [0xc1,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x00,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x00,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_i32 s1, s103
-// CHECK: [0x01,0x67,0x00,0xbf]
-
-s_cmp_eq_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x00,0xbf]
-
-s_cmp_eq_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x00,0xbf]
-
-s_cmp_eq_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x00,0xbf]
-
-s_cmp_eq_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x00,0xbf]
-
-s_cmp_eq_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x00,0xbf]
-
-s_cmp_eq_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x00,0xbf]
-
-s_cmp_eq_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x00,0xbf]
-
-s_cmp_eq_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x00,0xbf]
-
-s_cmp_eq_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x00,0xbf]
-
-s_cmp_eq_i32 s1, m0
-// CHECK: [0x01,0x7c,0x00,0xbf]
-
-s_cmp_eq_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x00,0xbf]
-
-s_cmp_eq_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x00,0xbf]
-
-s_cmp_eq_i32 s1, 0
-// CHECK: [0x01,0x80,0x00,0xbf]
-
-s_cmp_eq_i32 s1, -1
-// CHECK: [0x01,0xc1,0x00,0xbf]
-
-s_cmp_eq_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x00,0xbf]
-
-s_cmp_eq_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x00,0xbf]
-
-s_cmp_eq_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_i32 s1, s2
-// CHECK: [0x01,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 s103, s2
-// CHECK: [0x67,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 m0, s2
-// CHECK: [0x7c,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 0, s2
-// CHECK: [0x80,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 -1, s2
-// CHECK: [0xc1,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x01,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x01,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_i32 s1, s103
-// CHECK: [0x01,0x67,0x01,0xbf]
-
-s_cmp_lg_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x01,0xbf]
-
-s_cmp_lg_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x01,0xbf]
-
-s_cmp_lg_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x01,0xbf]
-
-s_cmp_lg_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x01,0xbf]
-
-s_cmp_lg_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x01,0xbf]
-
-s_cmp_lg_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x01,0xbf]
-
-s_cmp_lg_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x01,0xbf]
-
-s_cmp_lg_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x01,0xbf]
-
-s_cmp_lg_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x01,0xbf]
-
-s_cmp_lg_i32 s1, m0
-// CHECK: [0x01,0x7c,0x01,0xbf]
-
-s_cmp_lg_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x01,0xbf]
-
-s_cmp_lg_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x01,0xbf]
-
-s_cmp_lg_i32 s1, 0
-// CHECK: [0x01,0x80,0x01,0xbf]
-
-s_cmp_lg_i32 s1, -1
-// CHECK: [0x01,0xc1,0x01,0xbf]
-
-s_cmp_lg_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x01,0xbf]
-
-s_cmp_lg_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x01,0xbf]
-
-s_cmp_lg_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_i32 s1, s2
-// CHECK: [0x01,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 s103, s2
-// CHECK: [0x67,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 m0, s2
-// CHECK: [0x7c,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 0, s2
-// CHECK: [0x80,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 -1, s2
-// CHECK: [0xc1,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x02,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x02,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_i32 s1, s103
-// CHECK: [0x01,0x67,0x02,0xbf]
-
-s_cmp_gt_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x02,0xbf]
-
-s_cmp_gt_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x02,0xbf]
-
-s_cmp_gt_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x02,0xbf]
-
-s_cmp_gt_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x02,0xbf]
-
-s_cmp_gt_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x02,0xbf]
-
-s_cmp_gt_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x02,0xbf]
-
-s_cmp_gt_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x02,0xbf]
-
-s_cmp_gt_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x02,0xbf]
-
-s_cmp_gt_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x02,0xbf]
-
-s_cmp_gt_i32 s1, m0
-// CHECK: [0x01,0x7c,0x02,0xbf]
-
-s_cmp_gt_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x02,0xbf]
-
-s_cmp_gt_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x02,0xbf]
-
-s_cmp_gt_i32 s1, 0
-// CHECK: [0x01,0x80,0x02,0xbf]
-
-s_cmp_gt_i32 s1, -1
-// CHECK: [0x01,0xc1,0x02,0xbf]
-
-s_cmp_gt_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x02,0xbf]
-
-s_cmp_gt_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x02,0xbf]
-
-s_cmp_gt_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_i32 s1, s2
-// CHECK: [0x01,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 s103, s2
-// CHECK: [0x67,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 m0, s2
-// CHECK: [0x7c,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 0, s2
-// CHECK: [0x80,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 -1, s2
-// CHECK: [0xc1,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x03,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x03,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_i32 s1, s103
-// CHECK: [0x01,0x67,0x03,0xbf]
-
-s_cmp_ge_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x03,0xbf]
-
-s_cmp_ge_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x03,0xbf]
-
-s_cmp_ge_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x03,0xbf]
-
-s_cmp_ge_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x03,0xbf]
-
-s_cmp_ge_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x03,0xbf]
-
-s_cmp_ge_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x03,0xbf]
-
-s_cmp_ge_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x03,0xbf]
-
-s_cmp_ge_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x03,0xbf]
-
-s_cmp_ge_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x03,0xbf]
-
-s_cmp_ge_i32 s1, m0
-// CHECK: [0x01,0x7c,0x03,0xbf]
-
-s_cmp_ge_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x03,0xbf]
-
-s_cmp_ge_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x03,0xbf]
-
-s_cmp_ge_i32 s1, 0
-// CHECK: [0x01,0x80,0x03,0xbf]
-
-s_cmp_ge_i32 s1, -1
-// CHECK: [0x01,0xc1,0x03,0xbf]
-
-s_cmp_ge_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x03,0xbf]
-
-s_cmp_ge_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x03,0xbf]
-
-s_cmp_ge_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_i32 s1, s2
-// CHECK: [0x01,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 s103, s2
-// CHECK: [0x67,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 m0, s2
-// CHECK: [0x7c,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 0, s2
-// CHECK: [0x80,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 -1, s2
-// CHECK: [0xc1,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x04,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x04,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_i32 s1, s103
-// CHECK: [0x01,0x67,0x04,0xbf]
-
-s_cmp_lt_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x04,0xbf]
-
-s_cmp_lt_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x04,0xbf]
-
-s_cmp_lt_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x04,0xbf]
-
-s_cmp_lt_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x04,0xbf]
-
-s_cmp_lt_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x04,0xbf]
-
-s_cmp_lt_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x04,0xbf]
-
-s_cmp_lt_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x04,0xbf]
-
-s_cmp_lt_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x04,0xbf]
-
-s_cmp_lt_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x04,0xbf]
-
-s_cmp_lt_i32 s1, m0
-// CHECK: [0x01,0x7c,0x04,0xbf]
-
-s_cmp_lt_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x04,0xbf]
-
-s_cmp_lt_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x04,0xbf]
-
-s_cmp_lt_i32 s1, 0
-// CHECK: [0x01,0x80,0x04,0xbf]
-
-s_cmp_lt_i32 s1, -1
-// CHECK: [0x01,0xc1,0x04,0xbf]
-
-s_cmp_lt_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x04,0xbf]
-
-s_cmp_lt_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x04,0xbf]
-
-s_cmp_lt_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_i32 s1, s2
-// CHECK: [0x01,0x02,0x05,0xbf]
-
-s_cmp_le_i32 s103, s2
-// CHECK: [0x67,0x02,0x05,0xbf]
-
-s_cmp_le_i32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x05,0xbf]
-
-s_cmp_le_i32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x05,0xbf]
-
-s_cmp_le_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0xbf]
-
-s_cmp_le_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0xbf]
-
-s_cmp_le_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0xbf]
-
-s_cmp_le_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0xbf]
-
-s_cmp_le_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0xbf]
-
-s_cmp_le_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0xbf]
-
-s_cmp_le_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0xbf]
-
-s_cmp_le_i32 m0, s2
-// CHECK: [0x7c,0x02,0x05,0xbf]
-
-s_cmp_le_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0xbf]
-
-s_cmp_le_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0xbf]
-
-s_cmp_le_i32 0, s2
-// CHECK: [0x80,0x02,0x05,0xbf]
-
-s_cmp_le_i32 -1, s2
-// CHECK: [0xc1,0x02,0x05,0xbf]
-
-s_cmp_le_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0xbf]
-
-s_cmp_le_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0xbf]
-
-s_cmp_le_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_i32 s1, s103
-// CHECK: [0x01,0x67,0x05,0xbf]
-
-s_cmp_le_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x05,0xbf]
-
-s_cmp_le_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x05,0xbf]
-
-s_cmp_le_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0xbf]
-
-s_cmp_le_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0xbf]
-
-s_cmp_le_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0xbf]
-
-s_cmp_le_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0xbf]
-
-s_cmp_le_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0xbf]
-
-s_cmp_le_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0xbf]
-
-s_cmp_le_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0xbf]
-
-s_cmp_le_i32 s1, m0
-// CHECK: [0x01,0x7c,0x05,0xbf]
-
-s_cmp_le_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0xbf]
-
-s_cmp_le_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0xbf]
-
-s_cmp_le_i32 s1, 0
-// CHECK: [0x01,0x80,0x05,0xbf]
-
-s_cmp_le_i32 s1, -1
-// CHECK: [0x01,0xc1,0x05,0xbf]
-
-s_cmp_le_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0xbf]
-
-s_cmp_le_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0xbf]
-
-s_cmp_le_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u32 s1, s2
-// CHECK: [0x01,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 s103, s2
-// CHECK: [0x67,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 m0, s2
-// CHECK: [0x7c,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 0, s2
-// CHECK: [0x80,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 -1, s2
-// CHECK: [0xc1,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x06,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x06,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u32 s1, s103
-// CHECK: [0x01,0x67,0x06,0xbf]
-
-s_cmp_eq_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x06,0xbf]
-
-s_cmp_eq_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x06,0xbf]
-
-s_cmp_eq_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x06,0xbf]
-
-s_cmp_eq_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x06,0xbf]
-
-s_cmp_eq_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x06,0xbf]
-
-s_cmp_eq_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x06,0xbf]
-
-s_cmp_eq_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x06,0xbf]
-
-s_cmp_eq_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x06,0xbf]
-
-s_cmp_eq_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x06,0xbf]
-
-s_cmp_eq_u32 s1, m0
-// CHECK: [0x01,0x7c,0x06,0xbf]
-
-s_cmp_eq_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x06,0xbf]
-
-s_cmp_eq_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x06,0xbf]
-
-s_cmp_eq_u32 s1, 0
-// CHECK: [0x01,0x80,0x06,0xbf]
-
-s_cmp_eq_u32 s1, -1
-// CHECK: [0x01,0xc1,0x06,0xbf]
-
-s_cmp_eq_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x06,0xbf]
-
-s_cmp_eq_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x06,0xbf]
-
-s_cmp_eq_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u32 s1, s2
-// CHECK: [0x01,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 s103, s2
-// CHECK: [0x67,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 m0, s2
-// CHECK: [0x7c,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 0, s2
-// CHECK: [0x80,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 -1, s2
-// CHECK: [0xc1,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x07,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x07,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u32 s1, s103
-// CHECK: [0x01,0x67,0x07,0xbf]
-
-s_cmp_lg_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x07,0xbf]
-
-s_cmp_lg_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x07,0xbf]
-
-s_cmp_lg_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x07,0xbf]
-
-s_cmp_lg_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x07,0xbf]
-
-s_cmp_lg_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x07,0xbf]
-
-s_cmp_lg_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x07,0xbf]
-
-s_cmp_lg_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x07,0xbf]
-
-s_cmp_lg_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x07,0xbf]
-
-s_cmp_lg_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x07,0xbf]
-
-s_cmp_lg_u32 s1, m0
-// CHECK: [0x01,0x7c,0x07,0xbf]
-
-s_cmp_lg_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x07,0xbf]
-
-s_cmp_lg_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x07,0xbf]
-
-s_cmp_lg_u32 s1, 0
-// CHECK: [0x01,0x80,0x07,0xbf]
-
-s_cmp_lg_u32 s1, -1
-// CHECK: [0x01,0xc1,0x07,0xbf]
-
-s_cmp_lg_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x07,0xbf]
-
-s_cmp_lg_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x07,0xbf]
-
-s_cmp_lg_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_u32 s1, s2
-// CHECK: [0x01,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 s103, s2
-// CHECK: [0x67,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 m0, s2
-// CHECK: [0x7c,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 0, s2
-// CHECK: [0x80,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 -1, s2
-// CHECK: [0xc1,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x08,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x08,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_u32 s1, s103
-// CHECK: [0x01,0x67,0x08,0xbf]
-
-s_cmp_gt_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x08,0xbf]
-
-s_cmp_gt_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x08,0xbf]
-
-s_cmp_gt_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x08,0xbf]
-
-s_cmp_gt_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x08,0xbf]
-
-s_cmp_gt_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x08,0xbf]
-
-s_cmp_gt_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x08,0xbf]
-
-s_cmp_gt_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x08,0xbf]
-
-s_cmp_gt_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x08,0xbf]
-
-s_cmp_gt_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x08,0xbf]
-
-s_cmp_gt_u32 s1, m0
-// CHECK: [0x01,0x7c,0x08,0xbf]
-
-s_cmp_gt_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x08,0xbf]
-
-s_cmp_gt_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x08,0xbf]
-
-s_cmp_gt_u32 s1, 0
-// CHECK: [0x01,0x80,0x08,0xbf]
-
-s_cmp_gt_u32 s1, -1
-// CHECK: [0x01,0xc1,0x08,0xbf]
-
-s_cmp_gt_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x08,0xbf]
-
-s_cmp_gt_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x08,0xbf]
-
-s_cmp_gt_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_u32 s1, s2
-// CHECK: [0x01,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 s103, s2
-// CHECK: [0x67,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 m0, s2
-// CHECK: [0x7c,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 0, s2
-// CHECK: [0x80,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 -1, s2
-// CHECK: [0xc1,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x09,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x09,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_u32 s1, s103
-// CHECK: [0x01,0x67,0x09,0xbf]
-
-s_cmp_ge_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x09,0xbf]
-
-s_cmp_ge_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x09,0xbf]
-
-s_cmp_ge_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x09,0xbf]
-
-s_cmp_ge_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x09,0xbf]
-
-s_cmp_ge_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x09,0xbf]
-
-s_cmp_ge_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x09,0xbf]
-
-s_cmp_ge_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x09,0xbf]
-
-s_cmp_ge_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x09,0xbf]
-
-s_cmp_ge_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x09,0xbf]
-
-s_cmp_ge_u32 s1, m0
-// CHECK: [0x01,0x7c,0x09,0xbf]
-
-s_cmp_ge_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x09,0xbf]
-
-s_cmp_ge_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x09,0xbf]
-
-s_cmp_ge_u32 s1, 0
-// CHECK: [0x01,0x80,0x09,0xbf]
-
-s_cmp_ge_u32 s1, -1
-// CHECK: [0x01,0xc1,0x09,0xbf]
-
-s_cmp_ge_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x09,0xbf]
-
-s_cmp_ge_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x09,0xbf]
-
-s_cmp_ge_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_u32 s1, s2
-// CHECK: [0x01,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 s103, s2
-// CHECK: [0x67,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 m0, s2
-// CHECK: [0x7c,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 0, s2
-// CHECK: [0x80,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 -1, s2
-// CHECK: [0xc1,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0a,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0a,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_u32 s1, s103
-// CHECK: [0x01,0x67,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, m0
-// CHECK: [0x01,0x7c,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, 0
-// CHECK: [0x01,0x80,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, -1
-// CHECK: [0x01,0xc1,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_u32 s1, s2
-// CHECK: [0x01,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 s103, s2
-// CHECK: [0x67,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 m0, s2
-// CHECK: [0x7c,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 0, s2
-// CHECK: [0x80,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 -1, s2
-// CHECK: [0xc1,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0b,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0b,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_u32 s1, s103
-// CHECK: [0x01,0x67,0x0b,0xbf]
-
-s_cmp_le_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x0b,0xbf]
-
-s_cmp_le_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x0b,0xbf]
-
-s_cmp_le_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0b,0xbf]
-
-s_cmp_le_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0b,0xbf]
-
-s_cmp_le_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x0b,0xbf]
-
-s_cmp_le_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x0b,0xbf]
-
-s_cmp_le_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x0b,0xbf]
-
-s_cmp_le_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x0b,0xbf]
-
-s_cmp_le_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x0b,0xbf]
-
-s_cmp_le_u32 s1, m0
-// CHECK: [0x01,0x7c,0x0b,0xbf]
-
-s_cmp_le_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0b,0xbf]
-
-s_cmp_le_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0b,0xbf]
-
-s_cmp_le_u32 s1, 0
-// CHECK: [0x01,0x80,0x0b,0xbf]
-
-s_cmp_le_u32 s1, -1
-// CHECK: [0x01,0xc1,0x0b,0xbf]
-
-s_cmp_le_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0b,0xbf]
-
-s_cmp_le_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0b,0xbf]
-
-s_cmp_le_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b32 s1, s2
-// CHECK: [0x01,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 s103, s2
-// CHECK: [0x67,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 m0, s2
-// CHECK: [0x7c,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 0, s2
-// CHECK: [0x80,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 -1, s2
-// CHECK: [0xc1,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 0.5, s2
-// CHECK: [0xf0,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0c,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0c,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b32 s1, s103
-// CHECK: [0x01,0x67,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, m0
-// CHECK: [0x01,0x7c,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, 0
-// CHECK: [0x01,0x80,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, -1
-// CHECK: [0x01,0xc1,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b32 s1, s2
-// CHECK: [0x01,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 s103, s2
-// CHECK: [0x67,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 m0, s2
-// CHECK: [0x7c,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 0, s2
-// CHECK: [0x80,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 -1, s2
-// CHECK: [0xc1,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 0.5, s2
-// CHECK: [0xf0,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0d,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0d,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b32 s1, s103
-// CHECK: [0x01,0x67,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, m0
-// CHECK: [0x01,0x7c,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, 0
-// CHECK: [0x01,0x80,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, -1
-// CHECK: [0x01,0xc1,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b64 s[2:3], s2
-// CHECK: [0x02,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 s[4:5], s2
-// CHECK: [0x04,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 s[102:103], s2
-// CHECK: [0x66,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 flat_scratch, s2
-// CHECK: [0x68,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 vcc, s2
-// CHECK: [0x6a,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 tba, s2
-// CHECK: [0x6c,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 tma, s2
-// CHECK: [0x6e,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 exec, s2
-// CHECK: [0x7e,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 0, s2
-// CHECK: [0x80,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 -1, s2
-// CHECK: [0xc1,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 0.5, s2
-// CHECK: [0xf0,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 -4.0, s2
-// CHECK: [0xf7,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0e,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b64 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0e,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b64 s[2:3], s103
-// CHECK: [0x02,0x67,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x68,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x69,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], m0
-// CHECK: [0x02,0x7c,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], 0
-// CHECK: [0x02,0x80,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b64 s[2:3], s2
-// CHECK: [0x02,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 s[4:5], s2
-// CHECK: [0x04,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 s[102:103], s2
-// CHECK: [0x66,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 flat_scratch, s2
-// CHECK: [0x68,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 vcc, s2
-// CHECK: [0x6a,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 tba, s2
-// CHECK: [0x6c,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 tma, s2
-// CHECK: [0x6e,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 exec, s2
-// CHECK: [0x7e,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 0, s2
-// CHECK: [0x80,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 -1, s2
-// CHECK: [0xc1,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 0.5, s2
-// CHECK: [0xf0,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 -4.0, s2
-// CHECK: [0xf7,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0f,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b64 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0f,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b64 s[2:3], s103
-// CHECK: [0x02,0x67,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x68,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x69,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], m0
-// CHECK: [0x02,0x7c,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], 0
-// CHECK: [0x02,0x80,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f]
-
-s_setvskip s1, s2
-// CHECK: [0x01,0x02,0x10,0xbf]
-
-s_setvskip s103, s2
-// CHECK: [0x67,0x02,0x10,0xbf]
-
-s_setvskip flat_scratch_lo, s2
-// CHECK: [0x68,0x02,0x10,0xbf]
-
-s_setvskip flat_scratch_hi, s2
-// CHECK: [0x69,0x02,0x10,0xbf]
-
-s_setvskip vcc_lo, s2
-// CHECK: [0x6a,0x02,0x10,0xbf]
-
-s_setvskip vcc_hi, s2
-// CHECK: [0x6b,0x02,0x10,0xbf]
-
-s_setvskip tba_lo, s2
-// CHECK: [0x6c,0x02,0x10,0xbf]
-
-s_setvskip tba_hi, s2
-// CHECK: [0x6d,0x02,0x10,0xbf]
-
-s_setvskip tma_lo, s2
-// CHECK: [0x6e,0x02,0x10,0xbf]
-
-s_setvskip tma_hi, s2
-// CHECK: [0x6f,0x02,0x10,0xbf]
-
-s_setvskip ttmp11, s2
-// CHECK: [0x7b,0x02,0x10,0xbf]
-
-s_setvskip m0, s2
-// CHECK: [0x7c,0x02,0x10,0xbf]
-
-s_setvskip exec_lo, s2
-// CHECK: [0x7e,0x02,0x10,0xbf]
-
-s_setvskip exec_hi, s2
-// CHECK: [0x7f,0x02,0x10,0xbf]
-
-s_setvskip 0, s2
-// CHECK: [0x80,0x02,0x10,0xbf]
-
-s_setvskip -1, s2
-// CHECK: [0xc1,0x02,0x10,0xbf]
-
-s_setvskip 0.5, s2
-// CHECK: [0xf0,0x02,0x10,0xbf]
-
-s_setvskip -4.0, s2
-// CHECK: [0xf7,0x02,0x10,0xbf]
-
-s_setvskip 0xaf123456, s2
-// CHECK: [0xff,0x02,0x10,0xbf,0x56,0x34,0x12,0xaf]
-
-s_setvskip 0x3f717273, s2
-// CHECK: [0xff,0x02,0x10,0xbf,0x73,0x72,0x71,0x3f]
-
-s_setvskip s1, s103
-// CHECK: [0x01,0x67,0x10,0xbf]
-
-s_setvskip s1, flat_scratch_lo
-// CHECK: [0x01,0x68,0x10,0xbf]
-
-s_setvskip s1, flat_scratch_hi
-// CHECK: [0x01,0x69,0x10,0xbf]
-
-s_setvskip s1, vcc_lo
-// CHECK: [0x01,0x6a,0x10,0xbf]
-
-s_setvskip s1, vcc_hi
-// CHECK: [0x01,0x6b,0x10,0xbf]
-
-s_setvskip s1, tba_lo
-// CHECK: [0x01,0x6c,0x10,0xbf]
-
-s_setvskip s1, tba_hi
-// CHECK: [0x01,0x6d,0x10,0xbf]
-
-s_setvskip s1, tma_lo
-// CHECK: [0x01,0x6e,0x10,0xbf]
-
-s_setvskip s1, tma_hi
-// CHECK: [0x01,0x6f,0x10,0xbf]
-
-s_setvskip s1, ttmp11
-// CHECK: [0x01,0x7b,0x10,0xbf]
-
-s_setvskip s1, m0
-// CHECK: [0x01,0x7c,0x10,0xbf]
-
-s_setvskip s1, exec_lo
-// CHECK: [0x01,0x7e,0x10,0xbf]
-
-s_setvskip s1, exec_hi
-// CHECK: [0x01,0x7f,0x10,0xbf]
-
-s_setvskip s1, 0
-// CHECK: [0x01,0x80,0x10,0xbf]
-
-s_setvskip s1, -1
-// CHECK: [0x01,0xc1,0x10,0xbf]
-
-s_setvskip s1, 0.5
-// CHECK: [0x01,0xf0,0x10,0xbf]
-
-s_setvskip s1, -4.0
-// CHECK: [0x01,0xf7,0x10,0xbf]
-
-s_setvskip s1, 0xaf123456
-// CHECK: [0x01,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf]
-
-s_setvskip s1, 0x3f717273
-// CHECK: [0x01,0xff,0x10,0xbf,0x73,0x72,0x71,0x3f]
-
-s_movk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x05,0xb0]
-
-s_movk_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb0]
-
-s_movk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb0]
-
-s_movk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb0]
-
-s_movk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb0]
-
-s_movk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb0]
-
-s_movk_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb0]
-
-s_movk_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb0]
-
-s_movk_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb0]
-
-s_movk_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb0]
-
-s_movk_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb0]
-
-s_movk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb0]
-
-s_movk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb0]
-
-s_movk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb0]
-
-s_movk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x05,0xb0]
-
-s_cmovk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x05,0xb1]
-
-s_cmovk_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb1]
-
-s_cmovk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb1]
-
-s_cmovk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb1]
-
-s_cmovk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb1]
-
-s_cmovk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb1]
-
-s_cmovk_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb1]
-
-s_cmovk_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb1]
-
-s_cmovk_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb1]
-
-s_cmovk_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb1]
-
-s_cmovk_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb1]
-
-s_cmovk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb1]
-
-s_cmovk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb1]
-
-s_cmovk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb1]
-
-s_cmovk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x05,0xb1]
-
-s_cmpk_eq_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb1]
-
-s_cmpk_eq_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb1]
-
-s_cmpk_eq_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe8,0xb1]
-
-s_cmpk_eq_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe9,0xb1]
-
-s_cmpk_eq_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb1]
-
-s_cmpk_eq_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb1]
-
-s_cmpk_eq_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb1]
-
-s_cmpk_eq_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb1]
-
-s_cmpk_eq_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb1]
-
-s_cmpk_eq_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb1]
-
-s_cmpk_eq_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb1]
-
-s_cmpk_eq_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb1]
-
-s_cmpk_eq_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb1]
-
-s_cmpk_eq_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb1]
-
-s_cmpk_eq_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb1]
-
-s_cmpk_lg_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb2]
-
-s_cmpk_lg_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb2]
-
-s_cmpk_lg_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb2]
-
-s_cmpk_lg_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb2]
-
-s_cmpk_lg_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb2]
-
-s_cmpk_lg_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb2]
-
-s_cmpk_lg_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb2]
-
-s_cmpk_lg_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb2]
-
-s_cmpk_lg_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb2]
-
-s_cmpk_lg_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb2]
-
-s_cmpk_lg_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb2]
-
-s_cmpk_lg_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb2]
-
-s_cmpk_lg_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb2]
-
-s_cmpk_lg_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb2]
-
-s_cmpk_lg_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb2]
-
-s_cmpk_gt_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb2]
-
-s_cmpk_gt_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb2]
-
-s_cmpk_gt_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe8,0xb2]
-
-s_cmpk_gt_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe9,0xb2]
-
-s_cmpk_gt_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb2]
-
-s_cmpk_gt_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb2]
-
-s_cmpk_gt_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb2]
-
-s_cmpk_gt_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb2]
-
-s_cmpk_gt_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb2]
-
-s_cmpk_gt_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb2]
-
-s_cmpk_gt_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb2]
-
-s_cmpk_gt_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb2]
-
-s_cmpk_gt_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb2]
-
-s_cmpk_gt_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb2]
-
-s_cmpk_gt_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb2]
-
-s_cmpk_ge_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb3]
-
-s_cmpk_ge_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb3]
-
-s_cmpk_ge_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb3]
-
-s_cmpk_ge_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb3]
-
-s_cmpk_ge_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb3]
-
-s_cmpk_ge_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb3]
-
-s_cmpk_ge_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb3]
-
-s_cmpk_ge_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb3]
-
-s_cmpk_ge_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb3]
-
-s_cmpk_ge_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb3]
-
-s_cmpk_ge_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb3]
-
-s_cmpk_ge_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb3]
-
-s_cmpk_ge_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb3]
-
-s_cmpk_ge_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb3]
-
-s_cmpk_ge_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb3]
-
-s_cmpk_lt_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb3]
-
-s_cmpk_lt_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb3]
-
-s_cmpk_lt_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe8,0xb3]
-
-s_cmpk_lt_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe9,0xb3]
-
-s_cmpk_lt_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb3]
-
-s_cmpk_lt_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb3]
-
-s_cmpk_lt_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb3]
-
-s_cmpk_lt_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb3]
-
-s_cmpk_lt_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb3]
-
-s_cmpk_lt_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb3]
-
-s_cmpk_lt_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb3]
-
-s_cmpk_lt_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb3]
-
-s_cmpk_lt_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb3]
-
-s_cmpk_lt_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb3]
-
-s_cmpk_lt_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb3]
-
-s_cmpk_le_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb4]
-
-s_cmpk_le_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb4]
-
-s_cmpk_le_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb4]
-
-s_cmpk_le_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb4]
-
-s_cmpk_le_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb4]
-
-s_cmpk_le_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb4]
-
-s_cmpk_le_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb4]
-
-s_cmpk_le_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb4]
-
-s_cmpk_le_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb4]
-
-s_cmpk_le_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb4]
-
-s_cmpk_le_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb4]
-
-s_cmpk_le_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb4]
-
-s_cmpk_le_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb4]
-
-s_cmpk_le_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb4]
-
-s_cmpk_le_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb4]
-
-s_cmpk_eq_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb4]
-
-s_cmpk_eq_u32 s103, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb4]
-
-s_cmpk_eq_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe8,0xb4]
-
-s_cmpk_eq_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe9,0xb4]
-
-s_cmpk_eq_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb4]
-
-s_cmpk_eq_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb4]
-
-s_cmpk_eq_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb4]
-
-s_cmpk_eq_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb4]
-
-s_cmpk_eq_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb4]
-
-s_cmpk_eq_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb4]
-
-s_cmpk_eq_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb4]
-
-s_cmpk_eq_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb4]
-
-s_cmpk_eq_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb4]
-
-s_cmpk_eq_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb4]
-
-s_cmpk_eq_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb4]
-
-s_cmpk_lg_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb5]
-
-s_cmpk_lg_u32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb5]
-
-s_cmpk_lg_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb5]
-
-s_cmpk_lg_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb5]
-
-s_cmpk_lg_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb5]
-
-s_cmpk_lg_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb5]
-
-s_cmpk_lg_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb5]
-
-s_cmpk_lg_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb5]
-
-s_cmpk_lg_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb5]
-
-s_cmpk_lg_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb5]
-
-s_cmpk_lg_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb5]
-
-s_cmpk_lg_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb5]
-
-s_cmpk_lg_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb5]
-
-s_cmpk_lg_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb5]
-
-s_cmpk_lg_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb5]
-
-s_cmpk_gt_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb5]
-
-s_cmpk_gt_u32 s103, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb5]
-
-s_cmpk_gt_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe8,0xb5]
-
-s_cmpk_gt_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe9,0xb5]
-
-s_cmpk_gt_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb5]
-
-s_cmpk_gt_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb5]
-
-s_cmpk_gt_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb5]
-
-s_cmpk_gt_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb5]
-
-s_cmpk_gt_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb5]
-
-s_cmpk_gt_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb5]
-
-s_cmpk_gt_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb5]
-
-s_cmpk_gt_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb5]
-
-s_cmpk_gt_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb5]
-
-s_cmpk_gt_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb5]
-
-s_cmpk_gt_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb5]
-
-s_cmpk_ge_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb6]
-
-s_cmpk_ge_u32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb6]
-
-s_cmpk_ge_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb6]
-
-s_cmpk_ge_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb6]
-
-s_cmpk_ge_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb6]
-
-s_cmpk_ge_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb6]
-
-s_cmpk_ge_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb6]
-
-s_cmpk_ge_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb6]
-
-s_cmpk_ge_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb6]
-
-s_cmpk_ge_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb6]
-
-s_cmpk_ge_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb6]
-
-s_cmpk_ge_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb6]
-
-s_cmpk_ge_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb6]
-
-s_cmpk_ge_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb6]
-
-s_cmpk_ge_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb6]
-
-s_cmpk_lt_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb6]
-
-s_cmpk_lt_u32 s103, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb6]
-
-s_cmpk_lt_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe8,0xb6]
-
-s_cmpk_lt_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe9,0xb6]
-
-s_cmpk_lt_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb6]
-
-s_cmpk_lt_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb6]
-
-s_cmpk_lt_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb6]
-
-s_cmpk_lt_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb6]
-
-s_cmpk_lt_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb6]
-
-s_cmpk_lt_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb6]
-
-s_cmpk_lt_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb6]
-
-s_cmpk_lt_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb6]
-
-s_cmpk_lt_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb6]
-
-s_cmpk_lt_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb6]
-
-s_cmpk_lt_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb6]
-
-s_cmpk_le_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb7]
-
-s_cmpk_le_u32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb7]
-
-s_cmpk_le_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb7]
-
-s_cmpk_le_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb7]
-
-s_cmpk_le_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb7]
-
-s_cmpk_le_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb7]
-
-s_cmpk_le_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb7]
-
-s_cmpk_le_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb7]
-
-s_cmpk_le_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb7]
-
-s_cmpk_le_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb7]
-
-s_cmpk_le_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb7]
-
-s_cmpk_le_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb7]
-
-s_cmpk_le_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb7]
-
-s_cmpk_le_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb7]
-
-s_cmpk_le_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb7]
-
-s_addk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x85,0xb7]
-
-s_addk_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb7]
-
-s_addk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe8,0xb7]
-
-s_addk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe9,0xb7]
-
-s_addk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb7]
-
-s_addk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb7]
-
-s_addk_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb7]
-
-s_addk_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb7]
-
-s_addk_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb7]
-
-s_addk_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb7]
-
-s_addk_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb7]
-
-s_addk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb7]
-
-s_addk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb7]
-
-s_addk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb7]
-
-s_addk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x85,0xb7]
-
-s_mulk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x05,0xb8]
-
-s_mulk_i32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb8]
-
-s_mulk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb8]
-
-s_mulk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb8]
-
-s_mulk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb8]
-
-s_mulk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb8]
-
-s_mulk_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb8]
-
-s_mulk_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb8]
-
-s_mulk_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb8]
-
-s_mulk_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb8]
-
-s_mulk_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb8]
-
-s_mulk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb8]
-
-s_mulk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb8]
-
-s_mulk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb8]
-
-s_mulk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x05,0xb8]
-
-s_cbranch_i_fork s[2:3], 12609
-// CHECK: [0x41,0x31,0x82,0xb8]
-
-s_cbranch_i_fork s[4:5], 12609
-// CHECK: [0x41,0x31,0x84,0xb8]
-
-s_cbranch_i_fork s[102:103], 12609
-// CHECK: [0x41,0x31,0xe6,0xb8]
-
-s_cbranch_i_fork flat_scratch, 12609
-// CHECK: [0x41,0x31,0xe8,0xb8]
-
-s_cbranch_i_fork vcc, 12609
-// CHECK: [0x41,0x31,0xea,0xb8]
-
-s_cbranch_i_fork tba, 12609
-// CHECK: [0x41,0x31,0xec,0xb8]
-
-s_cbranch_i_fork tma, 12609
-// CHECK: [0x41,0x31,0xee,0xb8]
-
-s_cbranch_i_fork ttmp[10:11], 12609
-// CHECK: [0x41,0x31,0xfa,0xb8]
-
-s_cbranch_i_fork exec, 12609
-// CHECK: [0x41,0x31,0xfe,0xb8]
-
-s_cbranch_i_fork s[2:3], 49617
-// CHECK: [0xd1,0xc1,0x82,0xb8]
-
-s_getreg_b32 s5, 0x3141
-// CHECK: [0x41,0x31,0x05,0xb9]
-
-s_getreg_b32 s103, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb9]
-
-s_getreg_b32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x68,0xb9]
-
-s_getreg_b32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x69,0xb9]
-
-s_getreg_b32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb9]
-
-s_getreg_b32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb9]
-
-s_getreg_b32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb9]
-
-s_getreg_b32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb9]
-
-s_getreg_b32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb9]
-
-s_getreg_b32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb9]
-
-s_getreg_b32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb9]
-
-s_getreg_b32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb9]
-
-s_getreg_b32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb9]
-
-s_getreg_b32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb9]
-
-s_getreg_b32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x05,0xb9]
-
-s_setreg_b32 0x3141, s1
-// CHECK: [0x41,0x31,0x81,0xb9]
-
-s_setreg_b32 0xc1d1, s1
-// CHECK: [0xd1,0xc1,0x81,0xb9]
-
-s_setreg_b32 0x3141, s103
-// CHECK: [0x41,0x31,0xe7,0xb9]
-
-s_setreg_b32 0x3141, flat_scratch_lo
-// CHECK: [0x41,0x31,0xe8,0xb9]
-
-s_setreg_b32 0x3141, flat_scratch_hi
-// CHECK: [0x41,0x31,0xe9,0xb9]
-
-s_setreg_b32 0x3141, vcc_lo
-// CHECK: [0x41,0x31,0xea,0xb9]
-
-s_setreg_b32 0x3141, vcc_hi
-// CHECK: [0x41,0x31,0xeb,0xb9]
-
-s_setreg_b32 0x3141, tba_lo
-// CHECK: [0x41,0x31,0xec,0xb9]
-
-s_setreg_b32 0x3141, tba_hi
-// CHECK: [0x41,0x31,0xed,0xb9]
-
-s_setreg_b32 0x3141, tma_lo
-// CHECK: [0x41,0x31,0xee,0xb9]
-
-s_setreg_b32 0x3141, tma_hi
-// CHECK: [0x41,0x31,0xef,0xb9]
-
-s_setreg_b32 0x3141, ttmp11
-// CHECK: [0x41,0x31,0xfb,0xb9]
-
-s_setreg_b32 0x3141, m0
-// CHECK: [0x41,0x31,0xfc,0xb9]
-
-s_setreg_b32 0x3141, exec_lo
-// CHECK: [0x41,0x31,0xfe,0xb9]
-
-s_setreg_b32 0x3141, exec_hi
-// CHECK: [0x41,0x31,0xff,0xb9]
-
-s_setreg_imm32_b32 0x3141, 0x11213141
-// CHECK: [0x41,0x31,0x80,0xba,0x41,0x31,0x21,0x11]
-
-s_setreg_imm32_b32 0xc1d1, 0x11213141
-// CHECK: [0xd1,0xc1,0x80,0xba,0x41,0x31,0x21,0x11]
-
-s_setreg_imm32_b32 0x3141, 0xa1b1c1d1
-// CHECK: [0x41,0x31,0x80,0xba,0xd1,0xc1,0xb1,0xa1]
-
-s_nop 0x3141
-// CHECK: [0x41,0x31,0x80,0xbf]
-
-s_nop 0xc1d1
-// CHECK: [0xd1,0xc1,0x80,0xbf]
-
-s_endpgm
-// CHECK: [0x00,0x00,0x81,0xbf]
-
-s_branch 12609
-// CHECK: [0x41,0x31,0x82,0xbf]
-
-s_branch 49617
-// CHECK: [0xd1,0xc1,0x82,0xbf]
-
-s_cbranch_scc0 12609
-// CHECK: [0x41,0x31,0x84,0xbf]
-
-s_cbranch_scc0 49617
-// CHECK: [0xd1,0xc1,0x84,0xbf]
-
-s_cbranch_scc1 12609
-// CHECK: [0x41,0x31,0x85,0xbf]
-
-s_cbranch_scc1 49617
-// CHECK: [0xd1,0xc1,0x85,0xbf]
-
-s_cbranch_vccz 12609
-// CHECK: [0x41,0x31,0x86,0xbf]
-
-s_cbranch_vccz 49617
-// CHECK: [0xd1,0xc1,0x86,0xbf]
-
-s_cbranch_vccnz 12609
-// CHECK: [0x41,0x31,0x87,0xbf]
-
-s_cbranch_vccnz 49617
-// CHECK: [0xd1,0xc1,0x87,0xbf]
-
-s_cbranch_execz 12609
-// CHECK: [0x41,0x31,0x88,0xbf]
-
-s_cbranch_execz 49617
-// CHECK: [0xd1,0xc1,0x88,0xbf]
-
-s_cbranch_execnz 12609
-// CHECK: [0x41,0x31,0x89,0xbf]
-
-s_cbranch_execnz 49617
-// CHECK: [0xd1,0xc1,0x89,0xbf]
-
-s_barrier
-// CHECK: [0x00,0x00,0x8a,0xbf]
-
-s_setkill 0x3141
-// CHECK: [0x41,0x31,0x8b,0xbf]
-
-s_setkill 0xc1d1
-// CHECK: [0xd1,0xc1,0x8b,0xbf]
-
-s_waitcnt 0x3141
-// CHECK: [0x41,0x31,0x8c,0xbf]
-
-s_waitcnt 0xc1d1
-// CHECK: [0xd1,0xc1,0x8c,0xbf]
-
-s_sethalt 0x3141
-// CHECK: [0x41,0x31,0x8d,0xbf]
-
-s_sethalt 0xc1d1
-// CHECK: [0xd1,0xc1,0x8d,0xbf]
-
-s_sleep 0x3141
-// CHECK: [0x41,0x31,0x8e,0xbf]
-
-s_sleep 0xc1d1
-// CHECK: [0xd1,0xc1,0x8e,0xbf]
-
-s_setprio 0x3141
-// CHECK: [0x41,0x31,0x8f,0xbf]
-
-s_setprio 0xc1d1
-// CHECK: [0xd1,0xc1,0x8f,0xbf]
-
-s_sendmsg 0x3141
-// CHECK: [0x41,0x31,0x90,0xbf]
-
-s_sendmsg 0xc1d1
-// CHECK: [0xd1,0xc1,0x90,0xbf]
-
-s_sendmsghalt 0x3141
-// CHECK: [0x41,0x31,0x91,0xbf]
-
-s_sendmsghalt 0xc1d1
-// CHECK: [0xd1,0xc1,0x91,0xbf]
-
-s_trap 0x3141
-// CHECK: [0x41,0x31,0x92,0xbf]
-
-s_trap 0xc1d1
-// CHECK: [0xd1,0xc1,0x92,0xbf]
-
-s_icache_inv
-// CHECK: [0x00,0x00,0x93,0xbf]
-
-s_incperflevel 0x3141
-// CHECK: [0x41,0x31,0x94,0xbf]
-
-s_incperflevel 0xc1d1
-// CHECK: [0xd1,0xc1,0x94,0xbf]
-
-s_decperflevel 0x3141
-// CHECK: [0x41,0x31,0x95,0xbf]
-
-s_decperflevel 0xc1d1
-// CHECK: [0xd1,0xc1,0x95,0xbf]
-
-s_ttracedata
-// CHECK: [0x00,0x00,0x96,0xbf]
-
-s_cbranch_cdbgsys 12609
-// CHECK: [0x41,0x31,0x97,0xbf]
-
-s_cbranch_cdbgsys 49617
-// CHECK: [0xd1,0xc1,0x97,0xbf]
-
-s_cbranch_cdbguser 12609
-// CHECK: [0x41,0x31,0x98,0xbf]
-
-s_cbranch_cdbguser 49617
-// CHECK: [0xd1,0xc1,0x98,0xbf]
-
-s_cbranch_cdbgsys_or_user 12609
-// CHECK: [0x41,0x31,0x99,0xbf]
-
-s_cbranch_cdbgsys_or_user 49617
-// CHECK: [0xd1,0xc1,0x99,0xbf]
-
-s_cbranch_cdbgsys_and_user 12609
-// CHECK: [0x41,0x31,0x9a,0xbf]
-
-s_cbranch_cdbgsys_and_user 49617
-// CHECK: [0xd1,0xc1,0x9a,0xbf]
-
-v_interp_p1_f32 v5, v1, attr0.x
-// CHECK: [0x01,0x00,0x14,0xc8]
-
-v_interp_p1_f32 v255, v1, attr0.x
-// CHECK: [0x01,0x00,0xfc,0xcb]
-
-v_interp_p1_f32 v5, v255, attr0.x
-// CHECK: [0xff,0x00,0x14,0xc8]
-
-v_interp_p1_f32 v5, v1, attr1.x
-// CHECK: [0x01,0x04,0x14,0xc8]
-
-v_interp_p1_f32 v5, v1, attr31.x
-// CHECK: [0x01,0x7c,0x14,0xc8]
-
-v_interp_p1_f32 v5, v1, attr32.x
-// CHECK: [0x01,0x80,0x14,0xc8]
-
-v_interp_p1_f32 v5, v1, attr0.y
-// CHECK: [0x01,0x01,0x14,0xc8]
-
-v_interp_p1_f32 v5, v1, attr0.z
-// CHECK: [0x01,0x02,0x14,0xc8]
-
-v_interp_p1_f32 v5, v1, attr0.w
-// CHECK: [0x01,0x03,0x14,0xc8]
-
-v_interp_p2_f32 v5, v1, attr0.x
-// CHECK: [0x01,0x00,0x15,0xc8]
-
-v_interp_p2_f32 v255, v1, attr0.x
-// CHECK: [0x01,0x00,0xfd,0xcb]
-
-v_interp_p2_f32 v5, v255, attr0.x
-// CHECK: [0xff,0x00,0x15,0xc8]
-
-v_interp_p2_f32 v5, v1, attr1.x
-// CHECK: [0x01,0x04,0x15,0xc8]
-
-v_interp_p2_f32 v5, v1, attr31.x
-// CHECK: [0x01,0x7c,0x15,0xc8]
-
-v_interp_p2_f32 v5, v1, attr32.x
-// CHECK: [0x01,0x80,0x15,0xc8]
-
-v_interp_p2_f32 v5, v1, attr0.y
-// CHECK: [0x01,0x01,0x15,0xc8]
-
-v_interp_p2_f32 v5, v1, attr0.z
-// CHECK: [0x01,0x02,0x15,0xc8]
-
-v_interp_p2_f32 v5, v1, attr0.w
-// CHECK: [0x01,0x03,0x15,0xc8]
-
-v_interp_mov_f32 v5, p10, attr0.x
-// CHECK: [0x00,0x00,0x16,0xc8]
-
-v_interp_mov_f32 v255, p10, attr0.x
-// CHECK: [0x00,0x00,0xfe,0xcb]
-
-v_interp_mov_f32 v5, p20, attr0.x
-// CHECK: [0x01,0x00,0x16,0xc8]
-
-v_interp_mov_f32 v5, p0, attr0.x
-// CHECK: [0x02,0x00,0x16,0xc8]
-
-v_interp_mov_f32 v5, p10, attr1.x
-// CHECK: [0x00,0x04,0x16,0xc8]
-
-v_interp_mov_f32 v5, p10, attr31.x
-// CHECK: [0x00,0x7c,0x16,0xc8]
-
-v_interp_mov_f32 v5, p10, attr32.x
-// CHECK: [0x00,0x80,0x16,0xc8]
-
-v_interp_mov_f32 v5, p10, attr0.y
-// CHECK: [0x00,0x01,0x16,0xc8]
-
-v_interp_mov_f32 v5, p10, attr0.z
-// CHECK: [0x00,0x02,0x16,0xc8]
-
-v_interp_mov_f32 v5, p10, attr0.w
-// CHECK: [0x00,0x03,0x16,0xc8]
-
-v_nop
-// CHECK: [0x00,0x00,0x00,0x7e]
-
-v_nop_e64
-// CHECK: [0x00,0x00,0x00,0xd3,0x00,0x00,0x00,0x00]
-
-v_mov_b32 v5, v1
-// CHECK: [0x01,0x03,0x0a,0x7e]
-
-v_mov_b32 v255, v1
-// CHECK: [0x01,0x03,0xfe,0x7f]
-
-v_mov_b32 v5, v255
-// CHECK: [0xff,0x03,0x0a,0x7e]
-
-v_mov_b32 v5, s1
-// CHECK: [0x01,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, s103
-// CHECK: [0x67,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, flat_scratch_lo
-// CHECK: [0x68,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, flat_scratch_hi
-// CHECK: [0x69,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, vcc_lo
-// CHECK: [0x6a,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, vcc_hi
-// CHECK: [0x6b,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, tba_lo
-// CHECK: [0x6c,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, tba_hi
-// CHECK: [0x6d,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, tma_lo
-// CHECK: [0x6e,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, tma_hi
-// CHECK: [0x6f,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, ttmp11
-// CHECK: [0x7b,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, m0
-// CHECK: [0x7c,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, exec_lo
-// CHECK: [0x7e,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, exec_hi
-// CHECK: [0x7f,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, 0
-// CHECK: [0x80,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, -1
-// CHECK: [0xc1,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, 0.5
-// CHECK: [0xf0,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, -4.0
-// CHECK: [0xf7,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, 0xaf123456
-// CHECK: [0xff,0x02,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_mov_b32 v5, 0x3f717273
-// CHECK: [0xff,0x02,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_mov_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x02,0xd3,0x01,0x01,0x00,0x00]
-
-v_mov_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x02,0xd3,0x01,0x01,0x00,0x00]
-
-v_mov_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x02,0xd3,0xff,0x01,0x00,0x00]
-
-v_mov_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x02,0xd3,0x01,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, s103
-// CHECK: [0x05,0x00,0x02,0xd3,0x67,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x02,0xd3,0x68,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x02,0xd3,0x69,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x02,0xd3,0x6a,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x02,0xd3,0x6b,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x02,0xd3,0x6c,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x02,0xd3,0x6d,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x02,0xd3,0x6e,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x02,0xd3,0x6f,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x02,0xd3,0x7b,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x02,0xd3,0x7c,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x02,0xd3,0x7e,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x02,0xd3,0x7f,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x02,0xd3,0x80,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x02,0xd3,0xc1,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x02,0xd3,0xf0,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x02,0xd3,0xf7,0x00,0x00,0x00]
-
-v_readfirstlane_b32 s5, v1
-// CHECK: [0x01,0x05,0x0a,0x7e]
-
-v_readfirstlane_b32 s103, v1
-// CHECK: [0x01,0x05,0xce,0x7e]
-
-v_readfirstlane_b32 tba_lo, v1
-// CHECK: [0x01,0x05,0xd8,0x7e]
-
-v_readfirstlane_b32 tba_hi, v1
-// CHECK: [0x01,0x05,0xda,0x7e]
-
-v_readfirstlane_b32 tma_lo, v1
-// CHECK: [0x01,0x05,0xdc,0x7e]
-
-v_readfirstlane_b32 tma_hi, v1
-// CHECK: [0x01,0x05,0xde,0x7e]
-
-v_readfirstlane_b32 ttmp11, v1
-// CHECK: [0x01,0x05,0xf6,0x7e]
-
-v_readfirstlane_b32 s5, v255
-// CHECK: [0xff,0x05,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, v[1:2]
-// CHECK: [0x01,0x07,0x0a,0x7e]
-
-v_cvt_i32_f64 v255, v[1:2]
-// CHECK: [0x01,0x07,0xfe,0x7f]
-
-v_cvt_i32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x07,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, s[2:3]
-// CHECK: [0x02,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, s[4:5]
-// CHECK: [0x04,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, s[102:103]
-// CHECK: [0x66,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, flat_scratch
-// CHECK: [0x68,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, vcc
-// CHECK: [0x6a,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, tba
-// CHECK: [0x6c,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, tma
-// CHECK: [0x6e,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, ttmp[10:11]
-// CHECK: [0x7a,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, exec
-// CHECK: [0x7e,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, 0
-// CHECK: [0x80,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, -1
-// CHECK: [0xc1,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, 0.5
-// CHECK: [0xf0,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, -4.0
-// CHECK: [0xf7,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x06,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_i32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x06,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_i32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x06,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x06,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x06,0xd3,0xfe,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x06,0xd3,0x02,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x06,0xd3,0x04,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[102:103]
-// CHECK: [0x05,0x00,0x06,0xd3,0x66,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x06,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x06,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, tba
-// CHECK: [0x05,0x00,0x06,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, tma
-// CHECK: [0x05,0x00,0x06,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, ttmp[10:11]
-// CHECK: [0x05,0x00,0x06,0xd3,0x7a,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x06,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x06,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x06,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x06,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x06,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x06,0xd3,0x01,0x01,0x00,0x20]
-
-v_cvt_i32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x06,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32 v[5:6], v1
-// CHECK: [0x01,0x09,0x0a,0x7e]
-
-v_cvt_f64_i32 v[254:255], v1
-// CHECK: [0x01,0x09,0xfc,0x7f]
-
-v_cvt_f64_i32 v[5:6], v255
-// CHECK: [0xff,0x09,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], s1
-// CHECK: [0x01,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], s103
-// CHECK: [0x67,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], flat_scratch_lo
-// CHECK: [0x68,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], flat_scratch_hi
-// CHECK: [0x69,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], vcc_lo
-// CHECK: [0x6a,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], vcc_hi
-// CHECK: [0x6b,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], tba_lo
-// CHECK: [0x6c,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], tba_hi
-// CHECK: [0x6d,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], tma_lo
-// CHECK: [0x6e,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], tma_hi
-// CHECK: [0x6f,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], ttmp11
-// CHECK: [0x7b,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], m0
-// CHECK: [0x7c,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], exec_lo
-// CHECK: [0x7e,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], exec_hi
-// CHECK: [0x7f,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], 0
-// CHECK: [0x80,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], -1
-// CHECK: [0xc1,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], 0.5
-// CHECK: [0xf0,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], -4.0
-// CHECK: [0xf7,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], 0xaf123456
-// CHECK: [0xff,0x08,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_i32 v[5:6], 0x3f717273
-// CHECK: [0xff,0x08,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_i32_e64 v[5:6], v1
-// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[254:255], v1
-// CHECK: [0xfe,0x00,0x08,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v255
-// CHECK: [0x05,0x00,0x08,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], s1
-// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], s103
-// CHECK: [0x05,0x00,0x08,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], flat_scratch_lo
-// CHECK: [0x05,0x00,0x08,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], flat_scratch_hi
-// CHECK: [0x05,0x00,0x08,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], vcc_lo
-// CHECK: [0x05,0x00,0x08,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], vcc_hi
-// CHECK: [0x05,0x00,0x08,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], tba_lo
-// CHECK: [0x05,0x00,0x08,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], tba_hi
-// CHECK: [0x05,0x00,0x08,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], tma_lo
-// CHECK: [0x05,0x00,0x08,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], tma_hi
-// CHECK: [0x05,0x00,0x08,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], ttmp11
-// CHECK: [0x05,0x00,0x08,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], m0
-// CHECK: [0x05,0x00,0x08,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], exec_lo
-// CHECK: [0x05,0x00,0x08,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], exec_hi
-// CHECK: [0x05,0x00,0x08,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x08,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x08,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x08,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x08,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v1 clamp
-// CHECK: [0x05,0x08,0x08,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v1 mul:2
-// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_i32_e64 v[5:6], v1 mul:4
-// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_i32_e64 v[5:6], v1 div:2
-// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_i32 v5, v1
-// CHECK: [0x01,0x0b,0x0a,0x7e]
-
-v_cvt_f32_i32 v255, v1
-// CHECK: [0x01,0x0b,0xfe,0x7f]
-
-v_cvt_f32_i32 v5, v255
-// CHECK: [0xff,0x0b,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, s1
-// CHECK: [0x01,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, s103
-// CHECK: [0x67,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, flat_scratch_lo
-// CHECK: [0x68,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, flat_scratch_hi
-// CHECK: [0x69,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, vcc_lo
-// CHECK: [0x6a,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, vcc_hi
-// CHECK: [0x6b,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, tba_lo
-// CHECK: [0x6c,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, tba_hi
-// CHECK: [0x6d,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, tma_lo
-// CHECK: [0x6e,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, tma_hi
-// CHECK: [0x6f,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, ttmp11
-// CHECK: [0x7b,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, m0
-// CHECK: [0x7c,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, exec_lo
-// CHECK: [0x7e,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, exec_hi
-// CHECK: [0x7f,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, 0
-// CHECK: [0x80,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, -1
-// CHECK: [0xc1,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, 0.5
-// CHECK: [0xf0,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, -4.0
-// CHECK: [0xf7,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, 0xaf123456
-// CHECK: [0xff,0x0a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_i32 v5, 0x3f717273
-// CHECK: [0xff,0x0a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_i32_e64 v5, v1
-// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v255, v1
-// CHECK: [0xff,0x00,0x0a,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v255
-// CHECK: [0x05,0x00,0x0a,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, s1
-// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, s103
-// CHECK: [0x05,0x00,0x0a,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0a,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0a,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x0a,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x0a,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x0a,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x0a,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x0a,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x0a,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x0a,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, m0
-// CHECK: [0x05,0x00,0x0a,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x0a,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x0a,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, 0
-// CHECK: [0x05,0x00,0x0a,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, -1
-// CHECK: [0x05,0x00,0x0a,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x0a,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x0a,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x0a,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_i32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_i32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_u32 v5, v1
-// CHECK: [0x01,0x0d,0x0a,0x7e]
-
-v_cvt_f32_u32 v255, v1
-// CHECK: [0x01,0x0d,0xfe,0x7f]
-
-v_cvt_f32_u32 v5, v255
-// CHECK: [0xff,0x0d,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, s1
-// CHECK: [0x01,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, s103
-// CHECK: [0x67,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, flat_scratch_lo
-// CHECK: [0x68,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, flat_scratch_hi
-// CHECK: [0x69,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, vcc_lo
-// CHECK: [0x6a,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, vcc_hi
-// CHECK: [0x6b,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, tba_lo
-// CHECK: [0x6c,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, tba_hi
-// CHECK: [0x6d,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, tma_lo
-// CHECK: [0x6e,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, tma_hi
-// CHECK: [0x6f,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, ttmp11
-// CHECK: [0x7b,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, m0
-// CHECK: [0x7c,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, exec_lo
-// CHECK: [0x7e,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, exec_hi
-// CHECK: [0x7f,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, 0
-// CHECK: [0x80,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, -1
-// CHECK: [0xc1,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, 0.5
-// CHECK: [0xf0,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, -4.0
-// CHECK: [0xf7,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, 0xaf123456
-// CHECK: [0xff,0x0c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_u32 v5, 0x3f717273
-// CHECK: [0xff,0x0c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_u32_e64 v5, v1
-// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v255, v1
-// CHECK: [0xff,0x00,0x0c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v255
-// CHECK: [0x05,0x00,0x0c,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, s1
-// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, s103
-// CHECK: [0x05,0x00,0x0c,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0c,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0c,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x0c,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x0c,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x0c,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x0c,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x0c,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x0c,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x0c,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, m0
-// CHECK: [0x05,0x00,0x0c,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x0c,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x0c,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, 0
-// CHECK: [0x05,0x00,0x0c,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, -1
-// CHECK: [0x05,0x00,0x0c,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x0c,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x0c,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x0c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_u32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_u32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x01,0x00,0x18]
-
-v_cvt_u32_f32 v5, v1
-// CHECK: [0x01,0x0f,0x0a,0x7e]
-
-v_cvt_u32_f32 v255, v1
-// CHECK: [0x01,0x0f,0xfe,0x7f]
-
-v_cvt_u32_f32 v5, v255
-// CHECK: [0xff,0x0f,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, s1
-// CHECK: [0x01,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, s103
-// CHECK: [0x67,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, tba_lo
-// CHECK: [0x6c,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, tba_hi
-// CHECK: [0x6d,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, tma_lo
-// CHECK: [0x6e,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, tma_hi
-// CHECK: [0x6f,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, ttmp11
-// CHECK: [0x7b,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, m0
-// CHECK: [0x7c,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, exec_lo
-// CHECK: [0x7e,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, exec_hi
-// CHECK: [0x7f,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, 0
-// CHECK: [0x80,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, -1
-// CHECK: [0xc1,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, 0.5
-// CHECK: [0xf0,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, -4.0
-// CHECK: [0xf7,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x0e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_u32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x0e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_u32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x0e,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x0e,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x0e,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x0e,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x0e,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0e,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0e,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x0e,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x0e,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x0e,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x0e,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x0e,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x0e,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x0e,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x0e,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x0e,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x0e,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x0e,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x0e,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x0e,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x0e,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x0e,0xd3,0x01,0x01,0x00,0x20]
-
-v_cvt_u32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x0e,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32 v5, v1
-// CHECK: [0x01,0x11,0x0a,0x7e]
-
-v_cvt_i32_f32 v255, v1
-// CHECK: [0x01,0x11,0xfe,0x7f]
-
-v_cvt_i32_f32 v5, v255
-// CHECK: [0xff,0x11,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, s1
-// CHECK: [0x01,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, s103
-// CHECK: [0x67,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, tba_lo
-// CHECK: [0x6c,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, tba_hi
-// CHECK: [0x6d,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, tma_lo
-// CHECK: [0x6e,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, tma_hi
-// CHECK: [0x6f,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, ttmp11
-// CHECK: [0x7b,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, m0
-// CHECK: [0x7c,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, 0
-// CHECK: [0x80,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, -1
-// CHECK: [0xc1,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x10,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x10,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x10,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x10,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x10,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x10,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x10,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x10,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x10,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x10,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x10,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x10,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x10,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x10,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x10,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x10,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x10,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x10,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x10,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x10,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x10,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x10,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x10,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x10,0xd3,0x01,0x01,0x00,0x20]
-
-v_cvt_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x10,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32 v5, v1
-// CHECK: [0x01,0x15,0x0a,0x7e]
-
-v_cvt_f16_f32 v255, v1
-// CHECK: [0x01,0x15,0xfe,0x7f]
-
-v_cvt_f16_f32 v5, v255
-// CHECK: [0xff,0x15,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, s1
-// CHECK: [0x01,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, s103
-// CHECK: [0x67,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, vcc_lo
-// CHECK: [0x6a,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, vcc_hi
-// CHECK: [0x6b,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, tba_lo
-// CHECK: [0x6c,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, tba_hi
-// CHECK: [0x6d,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, tma_lo
-// CHECK: [0x6e,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, tma_hi
-// CHECK: [0x6f,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, ttmp11
-// CHECK: [0x7b,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, m0
-// CHECK: [0x7c,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, exec_lo
-// CHECK: [0x7e,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, exec_hi
-// CHECK: [0x7f,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0
-// CHECK: [0x80,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, -1
-// CHECK: [0xc1,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0.5
-// CHECK: [0xf0,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, -4.0
-// CHECK: [0xf7,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0xaf123456
-// CHECK: [0xff,0x14,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f16_f32 v5, 0x3f717273
-// CHECK: [0xff,0x14,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f16_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x14,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x14,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x14,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x14,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x14,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x14,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x14,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x14,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x14,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x14,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x14,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x14,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x14,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x14,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x14,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x14,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x14,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x14,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x14,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x14,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x14,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x14,0xd3,0x01,0x01,0x00,0x20]
-
-v_cvt_f16_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x14,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16 v5, v1
-// CHECK: [0x01,0x17,0x0a,0x7e]
-
-v_cvt_f32_f16 v255, v1
-// CHECK: [0x01,0x17,0xfe,0x7f]
-
-v_cvt_f32_f16 v5, v255
-// CHECK: [0xff,0x17,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, s1
-// CHECK: [0x01,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, s103
-// CHECK: [0x67,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, flat_scratch_lo
-// CHECK: [0x68,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, flat_scratch_hi
-// CHECK: [0x69,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, vcc_lo
-// CHECK: [0x6a,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, vcc_hi
-// CHECK: [0x6b,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, tba_lo
-// CHECK: [0x6c,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, tba_hi
-// CHECK: [0x6d,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, tma_lo
-// CHECK: [0x6e,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, tma_hi
-// CHECK: [0x6f,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, ttmp11
-// CHECK: [0x7b,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, m0
-// CHECK: [0x7c,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, exec_lo
-// CHECK: [0x7e,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, exec_hi
-// CHECK: [0x7f,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, 0
-// CHECK: [0x80,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, -1
-// CHECK: [0xc1,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x16,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x16,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, s103
-// CHECK: [0x05,0x00,0x16,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x16,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x16,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x16,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x16,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x16,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x16,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x16,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x16,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x16,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x16,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x16,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x16,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x16,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_f16_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_f16_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x01,0x00,0x18]
-
-v_cvt_rpi_i32_f32 v5, v1
-// CHECK: [0x01,0x19,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v255, v1
-// CHECK: [0x01,0x19,0xfe,0x7f]
-
-v_cvt_rpi_i32_f32 v5, v255
-// CHECK: [0xff,0x19,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, s1
-// CHECK: [0x01,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, s103
-// CHECK: [0x67,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, tba_lo
-// CHECK: [0x6c,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, tba_hi
-// CHECK: [0x6d,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, tma_lo
-// CHECK: [0x6e,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, tma_hi
-// CHECK: [0x6f,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, ttmp11
-// CHECK: [0x7b,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, m0
-// CHECK: [0x7c,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0
-// CHECK: [0x80,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, -1
-// CHECK: [0xc1,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x18,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_rpi_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x18,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_rpi_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x18,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x18,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x18,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x18,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x18,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x18,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x18,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x18,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x18,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x18,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x18,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x18,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x18,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x18,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x18,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x18,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x18,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x18,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x18,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x18,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x18,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x18,0xd3,0x01,0x01,0x00,0x20]
-
-v_cvt_rpi_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x18,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32 v5, v1
-// CHECK: [0x01,0x1b,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v255, v1
-// CHECK: [0x01,0x1b,0xfe,0x7f]
-
-v_cvt_flr_i32_f32 v5, v255
-// CHECK: [0xff,0x1b,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, s1
-// CHECK: [0x01,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, s103
-// CHECK: [0x67,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, tba_lo
-// CHECK: [0x6c,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, tba_hi
-// CHECK: [0x6d,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, tma_lo
-// CHECK: [0x6e,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, tma_hi
-// CHECK: [0x6f,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, ttmp11
-// CHECK: [0x7b,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, m0
-// CHECK: [0x7c,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0
-// CHECK: [0x80,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, -1
-// CHECK: [0xc1,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x1a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_flr_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x1a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_flr_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x1a,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x1a,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x1a,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x1a,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x1a,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x1a,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x1a,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x1a,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x1a,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x1a,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x1a,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x1a,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x1a,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x1a,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x1a,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x1a,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x1a,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x1a,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x1a,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x1a,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x1a,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x1a,0xd3,0x01,0x01,0x00,0x20]
-
-v_cvt_flr_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x1a,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4 v5, v1
-// CHECK: [0x01,0x1d,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v255, v1
-// CHECK: [0x01,0x1d,0xfe,0x7f]
-
-v_cvt_off_f32_i4 v5, v255
-// CHECK: [0xff,0x1d,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, s1
-// CHECK: [0x01,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, s103
-// CHECK: [0x67,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, flat_scratch_lo
-// CHECK: [0x68,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, flat_scratch_hi
-// CHECK: [0x69,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, vcc_lo
-// CHECK: [0x6a,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, vcc_hi
-// CHECK: [0x6b,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, tba_lo
-// CHECK: [0x6c,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, tba_hi
-// CHECK: [0x6d,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, tma_lo
-// CHECK: [0x6e,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, tma_hi
-// CHECK: [0x6f,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, ttmp11
-// CHECK: [0x7b,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, m0
-// CHECK: [0x7c,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, exec_lo
-// CHECK: [0x7e,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, exec_hi
-// CHECK: [0x7f,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0
-// CHECK: [0x80,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, -1
-// CHECK: [0xc1,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0.5
-// CHECK: [0xf0,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, -4.0
-// CHECK: [0xf7,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0x4f
-// CHECK: [0xff,0x1c,0x0a,0x7e,0x4f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4 v5, 0x41
-// CHECK: [0xff,0x1c,0x0a,0x7e,0x41,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1
-// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v255, v1
-// CHECK: [0xff,0x00,0x1c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v255
-// CHECK: [0x05,0x00,0x1c,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, s1
-// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, s103
-// CHECK: [0x05,0x00,0x1c,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x1c,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x1c,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x1c,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x1c,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x1c,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x1c,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x1c,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x1c,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x1c,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, m0
-// CHECK: [0x05,0x00,0x1c,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x1c,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x1c,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, 0
-// CHECK: [0x05,0x00,0x1c,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, -1
-// CHECK: [0x05,0x00,0x1c,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x1c,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x1c,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x1c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x01,0x00,0x08]
-
-v_cvt_off_f32_i4_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x01,0x00,0x10]
-
-v_cvt_off_f32_i4_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_f64 v5, v[1:2]
-// CHECK: [0x01,0x1f,0x0a,0x7e]
-
-v_cvt_f32_f64 v255, v[1:2]
-// CHECK: [0x01,0x1f,0xfe,0x7f]
-
-v_cvt_f32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x1f,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[2:3]
-// CHECK: [0x02,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[4:5]
-// CHECK: [0x04,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[102:103]
-// CHECK: [0x66,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, flat_scratch
-// CHECK: [0x68,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, vcc
-// CHECK: [0x6a,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, tba
-// CHECK: [0x6c,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, tma
-// CHECK: [0x6e,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, ttmp[10:11]
-// CHECK: [0x7a,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, exec
-// CHECK: [0x7e,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0
-// CHECK: [0x80,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, -1
-// CHECK: [0xc1,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0.5
-// CHECK: [0xf0,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, -4.0
-// CHECK: [0xf7,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x1e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x1e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x1e,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x1e,0xd3,0xfe,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x1e,0xd3,0x02,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x1e,0xd3,0x04,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[102:103]
-// CHECK: [0x05,0x00,0x1e,0xd3,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x1e,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x1e,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, tba
-// CHECK: [0x05,0x00,0x1e,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, tma
-// CHECK: [0x05,0x00,0x1e,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, ttmp[10:11]
-// CHECK: [0x05,0x00,0x1e,0xd3,0x7a,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x1e,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x1e,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x1e,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x1e,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x1e,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x20]
-
-v_cvt_f32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x1e,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[1:2] clamp
-// CHECK: [0x05,0x08,0x1e,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[1:2] mul:2
-// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_f64_e64 v5, v[1:2] mul:4
-// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_f64_e64 v5, v[1:2] div:2
-// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x18]
-
-v_cvt_f64_f32 v[5:6], v1
-// CHECK: [0x01,0x21,0x0a,0x7e]
-
-v_cvt_f64_f32 v[254:255], v1
-// CHECK: [0x01,0x21,0xfc,0x7f]
-
-v_cvt_f64_f32 v[5:6], v255
-// CHECK: [0xff,0x21,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], s1
-// CHECK: [0x01,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], s103
-// CHECK: [0x67,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], flat_scratch_lo
-// CHECK: [0x68,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], flat_scratch_hi
-// CHECK: [0x69,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], vcc_lo
-// CHECK: [0x6a,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], vcc_hi
-// CHECK: [0x6b,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], tba_lo
-// CHECK: [0x6c,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], tba_hi
-// CHECK: [0x6d,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], tma_lo
-// CHECK: [0x6e,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], tma_hi
-// CHECK: [0x6f,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], ttmp11
-// CHECK: [0x7b,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], m0
-// CHECK: [0x7c,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], exec_lo
-// CHECK: [0x7e,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], exec_hi
-// CHECK: [0x7f,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0
-// CHECK: [0x80,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], -1
-// CHECK: [0xc1,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0.5
-// CHECK: [0xf0,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], -4.0
-// CHECK: [0xf7,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0xaf123456
-// CHECK: [0xff,0x20,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_f32 v[5:6], 0x3f717273
-// CHECK: [0xff,0x20,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_f32_e64 v[5:6], v1
-// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[254:255], v1
-// CHECK: [0xfe,0x00,0x20,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v255
-// CHECK: [0x05,0x00,0x20,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], s1
-// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], s103
-// CHECK: [0x05,0x00,0x20,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], flat_scratch_lo
-// CHECK: [0x05,0x00,0x20,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], flat_scratch_hi
-// CHECK: [0x05,0x00,0x20,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], vcc_lo
-// CHECK: [0x05,0x00,0x20,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], vcc_hi
-// CHECK: [0x05,0x00,0x20,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], tba_lo
-// CHECK: [0x05,0x00,0x20,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], tba_hi
-// CHECK: [0x05,0x00,0x20,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], tma_lo
-// CHECK: [0x05,0x00,0x20,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], tma_hi
-// CHECK: [0x05,0x00,0x20,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], ttmp11
-// CHECK: [0x05,0x00,0x20,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], m0
-// CHECK: [0x05,0x00,0x20,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], exec_lo
-// CHECK: [0x05,0x00,0x20,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], exec_hi
-// CHECK: [0x05,0x00,0x20,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x20,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x20,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x20,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x20,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -v1
-// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x20]
-
-v_cvt_f64_f32_e64 v[5:6], |v1|
-// CHECK: [0x05,0x01,0x20,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v1 clamp
-// CHECK: [0x05,0x08,0x20,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v1 mul:2
-// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_f32_e64 v[5:6], v1 mul:4
-// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_f32_e64 v[5:6], v1 div:2
-// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte0 v5, v1
-// CHECK: [0x01,0x23,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v255, v1
-// CHECK: [0x01,0x23,0xfe,0x7f]
-
-v_cvt_f32_ubyte0 v5, v255
-// CHECK: [0xff,0x23,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, s1
-// CHECK: [0x01,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, s103
-// CHECK: [0x67,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, flat_scratch_lo
-// CHECK: [0x68,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, flat_scratch_hi
-// CHECK: [0x69,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, vcc_lo
-// CHECK: [0x6a,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, vcc_hi
-// CHECK: [0x6b,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, tba_lo
-// CHECK: [0x6c,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, tba_hi
-// CHECK: [0x6d,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, tma_lo
-// CHECK: [0x6e,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, tma_hi
-// CHECK: [0x6f,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, ttmp11
-// CHECK: [0x7b,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, m0
-// CHECK: [0x7c,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, exec_lo
-// CHECK: [0x7e,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, exec_hi
-// CHECK: [0x7f,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0
-// CHECK: [0x80,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, -1
-// CHECK: [0xc1,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0.5
-// CHECK: [0xf0,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, -4.0
-// CHECK: [0xf7,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0xaf123456
-// CHECK: [0xff,0x22,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte0 v5, 0x3f717273
-// CHECK: [0xff,0x22,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte0_e64 v5, v1
-// CHECK: [0x05,0x00,0x22,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v255, v1
-// CHECK: [0xff,0x00,0x22,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v255
-// CHECK: [0x05,0x00,0x22,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, s1
-// CHECK: [0x05,0x00,0x22,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, s103
-// CHECK: [0x05,0x00,0x22,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x22,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x22,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x22,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x22,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x22,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x22,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x22,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x22,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x22,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, m0
-// CHECK: [0x05,0x00,0x22,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x22,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x22,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, 0
-// CHECK: [0x05,0x00,0x22,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, -1
-// CHECK: [0x05,0x00,0x22,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x22,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x22,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1 v5, v1
-// CHECK: [0x01,0x25,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v255, v1
-// CHECK: [0x01,0x25,0xfe,0x7f]
-
-v_cvt_f32_ubyte1 v5, v255
-// CHECK: [0xff,0x25,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, s1
-// CHECK: [0x01,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, s103
-// CHECK: [0x67,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, flat_scratch_lo
-// CHECK: [0x68,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, flat_scratch_hi
-// CHECK: [0x69,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, vcc_lo
-// CHECK: [0x6a,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, vcc_hi
-// CHECK: [0x6b,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, tba_lo
-// CHECK: [0x6c,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, tba_hi
-// CHECK: [0x6d,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, tma_lo
-// CHECK: [0x6e,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, tma_hi
-// CHECK: [0x6f,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, ttmp11
-// CHECK: [0x7b,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, m0
-// CHECK: [0x7c,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, exec_lo
-// CHECK: [0x7e,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, exec_hi
-// CHECK: [0x7f,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0
-// CHECK: [0x80,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, -1
-// CHECK: [0xc1,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0.5
-// CHECK: [0xf0,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, -4.0
-// CHECK: [0xf7,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0xaf123456
-// CHECK: [0xff,0x24,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte1 v5, 0x3f717273
-// CHECK: [0xff,0x24,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte1_e64 v5, v1
-// CHECK: [0x05,0x00,0x24,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v255, v1
-// CHECK: [0xff,0x00,0x24,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v255
-// CHECK: [0x05,0x00,0x24,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, s1
-// CHECK: [0x05,0x00,0x24,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, s103
-// CHECK: [0x05,0x00,0x24,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x24,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x24,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x24,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x24,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x24,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x24,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x24,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x24,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x24,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, m0
-// CHECK: [0x05,0x00,0x24,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x24,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x24,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, 0
-// CHECK: [0x05,0x00,0x24,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, -1
-// CHECK: [0x05,0x00,0x24,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x24,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x24,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2 v5, v1
-// CHECK: [0x01,0x27,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v255, v1
-// CHECK: [0x01,0x27,0xfe,0x7f]
-
-v_cvt_f32_ubyte2 v5, v255
-// CHECK: [0xff,0x27,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, s1
-// CHECK: [0x01,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, s103
-// CHECK: [0x67,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, flat_scratch_lo
-// CHECK: [0x68,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, flat_scratch_hi
-// CHECK: [0x69,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, vcc_lo
-// CHECK: [0x6a,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, vcc_hi
-// CHECK: [0x6b,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, tba_lo
-// CHECK: [0x6c,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, tba_hi
-// CHECK: [0x6d,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, tma_lo
-// CHECK: [0x6e,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, tma_hi
-// CHECK: [0x6f,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, ttmp11
-// CHECK: [0x7b,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, m0
-// CHECK: [0x7c,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, exec_lo
-// CHECK: [0x7e,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, exec_hi
-// CHECK: [0x7f,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0
-// CHECK: [0x80,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, -1
-// CHECK: [0xc1,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0.5
-// CHECK: [0xf0,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, -4.0
-// CHECK: [0xf7,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0xaf123456
-// CHECK: [0xff,0x26,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte2 v5, 0x3f717273
-// CHECK: [0xff,0x26,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte2_e64 v5, v1
-// CHECK: [0x05,0x00,0x26,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v255, v1
-// CHECK: [0xff,0x00,0x26,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v255
-// CHECK: [0x05,0x00,0x26,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, s1
-// CHECK: [0x05,0x00,0x26,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, s103
-// CHECK: [0x05,0x00,0x26,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x26,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x26,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x26,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x26,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x26,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x26,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x26,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x26,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x26,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, m0
-// CHECK: [0x05,0x00,0x26,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x26,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x26,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, 0
-// CHECK: [0x05,0x00,0x26,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, -1
-// CHECK: [0x05,0x00,0x26,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x26,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x26,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3 v5, v1
-// CHECK: [0x01,0x29,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v255, v1
-// CHECK: [0x01,0x29,0xfe,0x7f]
-
-v_cvt_f32_ubyte3 v5, v255
-// CHECK: [0xff,0x29,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, s1
-// CHECK: [0x01,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, s103
-// CHECK: [0x67,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, flat_scratch_lo
-// CHECK: [0x68,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, flat_scratch_hi
-// CHECK: [0x69,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, vcc_lo
-// CHECK: [0x6a,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, vcc_hi
-// CHECK: [0x6b,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, tba_lo
-// CHECK: [0x6c,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, tba_hi
-// CHECK: [0x6d,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, tma_lo
-// CHECK: [0x6e,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, tma_hi
-// CHECK: [0x6f,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, ttmp11
-// CHECK: [0x7b,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, m0
-// CHECK: [0x7c,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, exec_lo
-// CHECK: [0x7e,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, exec_hi
-// CHECK: [0x7f,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0
-// CHECK: [0x80,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, -1
-// CHECK: [0xc1,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0.5
-// CHECK: [0xf0,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, -4.0
-// CHECK: [0xf7,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0xaf123456
-// CHECK: [0xff,0x28,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte3 v5, 0x3f717273
-// CHECK: [0xff,0x28,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte3_e64 v5, v1
-// CHECK: [0x05,0x00,0x28,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v255, v1
-// CHECK: [0xff,0x00,0x28,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v255
-// CHECK: [0x05,0x00,0x28,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, s1
-// CHECK: [0x05,0x00,0x28,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, s103
-// CHECK: [0x05,0x00,0x28,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x28,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x28,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x28,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x28,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x28,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x28,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x28,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x28,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x28,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, m0
-// CHECK: [0x05,0x00,0x28,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x28,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x28,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, 0
-// CHECK: [0x05,0x00,0x28,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, -1
-// CHECK: [0x05,0x00,0x28,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x28,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x28,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_u32_f64 v5, v[1:2]
-// CHECK: [0x01,0x2b,0x0a,0x7e]
-
-v_cvt_u32_f64 v255, v[1:2]
-// CHECK: [0x01,0x2b,0xfe,0x7f]
-
-v_cvt_u32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x2b,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[2:3]
-// CHECK: [0x02,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[4:5]
-// CHECK: [0x04,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[102:103]
-// CHECK: [0x66,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, flat_scratch
-// CHECK: [0x68,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, vcc
-// CHECK: [0x6a,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, tba
-// CHECK: [0x6c,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, tma
-// CHECK: [0x6e,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, ttmp[10:11]
-// CHECK: [0x7a,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, exec
-// CHECK: [0x7e,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0
-// CHECK: [0x80,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, -1
-// CHECK: [0xc1,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0.5
-// CHECK: [0xf0,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, -4.0
-// CHECK: [0xf7,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x2a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_u32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x2a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_u32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x2a,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x2a,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x2a,0xd3,0xfe,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x2a,0xd3,0x02,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x2a,0xd3,0x04,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[102:103]
-// CHECK: [0x05,0x00,0x2a,0xd3,0x66,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x2a,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x2a,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, tba
-// CHECK: [0x05,0x00,0x2a,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, tma
-// CHECK: [0x05,0x00,0x2a,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, ttmp[10:11]
-// CHECK: [0x05,0x00,0x2a,0xd3,0x7a,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x2a,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x2a,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x2a,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x2a,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x2a,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x2a,0xd3,0x01,0x01,0x00,0x20]
-
-v_cvt_u32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x2a,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32 v[5:6], v1
-// CHECK: [0x01,0x2d,0x0a,0x7e]
-
-v_cvt_f64_u32 v[254:255], v1
-// CHECK: [0x01,0x2d,0xfc,0x7f]
-
-v_cvt_f64_u32 v[5:6], v255
-// CHECK: [0xff,0x2d,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], s1
-// CHECK: [0x01,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], s103
-// CHECK: [0x67,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], flat_scratch_lo
-// CHECK: [0x68,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], flat_scratch_hi
-// CHECK: [0x69,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], vcc_lo
-// CHECK: [0x6a,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], vcc_hi
-// CHECK: [0x6b,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], tba_lo
-// CHECK: [0x6c,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], tba_hi
-// CHECK: [0x6d,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], tma_lo
-// CHECK: [0x6e,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], tma_hi
-// CHECK: [0x6f,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], ttmp11
-// CHECK: [0x7b,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], m0
-// CHECK: [0x7c,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], exec_lo
-// CHECK: [0x7e,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], exec_hi
-// CHECK: [0x7f,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0
-// CHECK: [0x80,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], -1
-// CHECK: [0xc1,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0.5
-// CHECK: [0xf0,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], -4.0
-// CHECK: [0xf7,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0xaf123456
-// CHECK: [0xff,0x2c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_u32 v[5:6], 0x3f717273
-// CHECK: [0xff,0x2c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_u32_e64 v[5:6], v1
-// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[254:255], v1
-// CHECK: [0xfe,0x00,0x2c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v255
-// CHECK: [0x05,0x00,0x2c,0xd3,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], s1
-// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], s103
-// CHECK: [0x05,0x00,0x2c,0xd3,0x67,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], flat_scratch_lo
-// CHECK: [0x05,0x00,0x2c,0xd3,0x68,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], flat_scratch_hi
-// CHECK: [0x05,0x00,0x2c,0xd3,0x69,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], vcc_lo
-// CHECK: [0x05,0x00,0x2c,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], vcc_hi
-// CHECK: [0x05,0x00,0x2c,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], tba_lo
-// CHECK: [0x05,0x00,0x2c,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], tba_hi
-// CHECK: [0x05,0x00,0x2c,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], tma_lo
-// CHECK: [0x05,0x00,0x2c,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], tma_hi
-// CHECK: [0x05,0x00,0x2c,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], ttmp11
-// CHECK: [0x05,0x00,0x2c,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], m0
-// CHECK: [0x05,0x00,0x2c,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], exec_lo
-// CHECK: [0x05,0x00,0x2c,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], exec_hi
-// CHECK: [0x05,0x00,0x2c,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x2c,0xd3,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x2c,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x2c,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x2c,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v1 clamp
-// CHECK: [0x05,0x08,0x2c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v1 mul:2
-// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_u32_e64 v[5:6], v1 mul:4
-// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_u32_e64 v[5:6], v1 div:2
-// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x01,0x00,0x18]
-
-v_trunc_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x2f,0x0a,0x7e]
-
-v_trunc_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x2f,0xfc,0x7f]
-
-v_trunc_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x2f,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], vcc
-// CHECK: [0x6a,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], tba
-// CHECK: [0x6c,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], tma
-// CHECK: [0x6e,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], exec
-// CHECK: [0x7e,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0
-// CHECK: [0x80,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], -1
-// CHECK: [0xc1,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x2e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_trunc_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x2e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_trunc_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x2e,0xd3,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x2e,0xd3,0xfe,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x2e,0xd3,0x02,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x2e,0xd3,0x04,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x2e,0xd3,0x66,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x2e,0xd3,0x68,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x2e,0xd3,0x6a,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x2e,0xd3,0x6c,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x2e,0xd3,0x6e,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x2e,0xd3,0x7a,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x2e,0xd3,0x7e,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x2e,0xd3,0x80,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x2e,0xd3,0xc1,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x2e,0xd3,0xf0,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x2e,0xd3,0xf7,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x20]
-
-v_trunc_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x2e,0xd3,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x2e,0xd3,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x08]
-
-v_trunc_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x10]
-
-v_trunc_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x18]
-
-v_ceil_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x31,0x0a,0x7e]
-
-v_ceil_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x31,0xfc,0x7f]
-
-v_ceil_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x31,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], vcc
-// CHECK: [0x6a,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], tba
-// CHECK: [0x6c,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], tma
-// CHECK: [0x6e,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], exec
-// CHECK: [0x7e,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0
-// CHECK: [0x80,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], -1
-// CHECK: [0xc1,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x30,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ceil_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x30,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ceil_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x30,0xd3,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x30,0xd3,0xfe,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x30,0xd3,0x02,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x30,0xd3,0x04,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x30,0xd3,0x66,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x30,0xd3,0x68,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x30,0xd3,0x6a,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x30,0xd3,0x6c,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x30,0xd3,0x6e,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x30,0xd3,0x7a,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x30,0xd3,0x7e,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x30,0xd3,0x80,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x30,0xd3,0xc1,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x30,0xd3,0xf0,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x30,0xd3,0xf7,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x20]
-
-v_ceil_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x30,0xd3,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x30,0xd3,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x08]
-
-v_ceil_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x10]
-
-v_ceil_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x18]
-
-v_rndne_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x33,0x0a,0x7e]
-
-v_rndne_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x33,0xfc,0x7f]
-
-v_rndne_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x33,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], vcc
-// CHECK: [0x6a,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], tba
-// CHECK: [0x6c,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], tma
-// CHECK: [0x6e,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], exec
-// CHECK: [0x7e,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0
-// CHECK: [0x80,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], -1
-// CHECK: [0xc1,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x32,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rndne_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x32,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rndne_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x32,0xd3,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x32,0xd3,0xfe,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x32,0xd3,0x02,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x32,0xd3,0x04,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x32,0xd3,0x66,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x32,0xd3,0x68,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x32,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x32,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x32,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x32,0xd3,0x7a,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x32,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x32,0xd3,0x80,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x32,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x32,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x32,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x20]
-
-v_rndne_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x32,0xd3,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x32,0xd3,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x08]
-
-v_rndne_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x10]
-
-v_rndne_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x18]
-
-v_floor_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x35,0x0a,0x7e]
-
-v_floor_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x35,0xfc,0x7f]
-
-v_floor_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x35,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], vcc
-// CHECK: [0x6a,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], tba
-// CHECK: [0x6c,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], tma
-// CHECK: [0x6e,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], exec
-// CHECK: [0x7e,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0
-// CHECK: [0x80,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], -1
-// CHECK: [0xc1,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x34,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_floor_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x34,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_floor_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x34,0xd3,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x34,0xd3,0xfe,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x34,0xd3,0x02,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x34,0xd3,0x04,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x34,0xd3,0x66,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x34,0xd3,0x68,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x34,0xd3,0x6a,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x34,0xd3,0x6c,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x34,0xd3,0x6e,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x34,0xd3,0x7a,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x34,0xd3,0x7e,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x34,0xd3,0x80,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x34,0xd3,0xc1,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x34,0xd3,0xf0,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x34,0xd3,0xf7,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x20]
-
-v_floor_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x34,0xd3,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x34,0xd3,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x08]
-
-v_floor_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x10]
-
-v_floor_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x18]
-
-v_fract_f32 v5, v1
-// CHECK: [0x01,0x41,0x0a,0x7e]
-
-v_fract_f32 v255, v1
-// CHECK: [0x01,0x41,0xfe,0x7f]
-
-v_fract_f32 v5, v255
-// CHECK: [0xff,0x41,0x0a,0x7e]
-
-v_fract_f32 v5, s1
-// CHECK: [0x01,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, s103
-// CHECK: [0x67,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, vcc_lo
-// CHECK: [0x6a,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, vcc_hi
-// CHECK: [0x6b,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, tba_lo
-// CHECK: [0x6c,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, tba_hi
-// CHECK: [0x6d,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, tma_lo
-// CHECK: [0x6e,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, tma_hi
-// CHECK: [0x6f,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, ttmp11
-// CHECK: [0x7b,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, m0
-// CHECK: [0x7c,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, exec_lo
-// CHECK: [0x7e,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, exec_hi
-// CHECK: [0x7f,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, 0
-// CHECK: [0x80,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, -1
-// CHECK: [0xc1,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, 0.5
-// CHECK: [0xf0,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, -4.0
-// CHECK: [0xf7,0x40,0x0a,0x7e]
-
-v_fract_f32 v5, 0xaf123456
-// CHECK: [0xff,0x40,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_fract_f32 v5, 0x3f717273
-// CHECK: [0xff,0x40,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_fract_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x40,0xd3,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x40,0xd3,0xff,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x40,0xd3,0x67,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x40,0xd3,0x68,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x40,0xd3,0x69,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x40,0xd3,0x6a,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x40,0xd3,0x6b,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x40,0xd3,0x6c,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x40,0xd3,0x6d,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x40,0xd3,0x6e,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x40,0xd3,0x6f,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x40,0xd3,0x7b,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x40,0xd3,0x7c,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x40,0xd3,0x7e,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x40,0xd3,0x7f,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x40,0xd3,0x80,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x40,0xd3,0xc1,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x40,0xd3,0xf0,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x40,0xd3,0xf7,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x20]
-
-v_fract_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x40,0xd3,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x40,0xd3,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x08]
-
-v_fract_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x10]
-
-v_fract_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x18]
-
-v_trunc_f32 v5, v1
-// CHECK: [0x01,0x43,0x0a,0x7e]
-
-v_trunc_f32 v255, v1
-// CHECK: [0x01,0x43,0xfe,0x7f]
-
-v_trunc_f32 v5, v255
-// CHECK: [0xff,0x43,0x0a,0x7e]
-
-v_trunc_f32 v5, s1
-// CHECK: [0x01,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, s103
-// CHECK: [0x67,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, vcc_lo
-// CHECK: [0x6a,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, vcc_hi
-// CHECK: [0x6b,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, tba_lo
-// CHECK: [0x6c,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, tba_hi
-// CHECK: [0x6d,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, tma_lo
-// CHECK: [0x6e,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, tma_hi
-// CHECK: [0x6f,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, ttmp11
-// CHECK: [0x7b,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, m0
-// CHECK: [0x7c,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, exec_lo
-// CHECK: [0x7e,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, exec_hi
-// CHECK: [0x7f,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, 0
-// CHECK: [0x80,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, -1
-// CHECK: [0xc1,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, 0.5
-// CHECK: [0xf0,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, -4.0
-// CHECK: [0xf7,0x42,0x0a,0x7e]
-
-v_trunc_f32 v5, 0xaf123456
-// CHECK: [0xff,0x42,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_trunc_f32 v5, 0x3f717273
-// CHECK: [0xff,0x42,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_trunc_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x42,0xd3,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x42,0xd3,0xff,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x42,0xd3,0x67,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x42,0xd3,0x68,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x42,0xd3,0x69,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x42,0xd3,0x6a,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x42,0xd3,0x6b,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x42,0xd3,0x6c,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x42,0xd3,0x6d,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x42,0xd3,0x6e,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x42,0xd3,0x6f,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x42,0xd3,0x7b,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x42,0xd3,0x7c,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x42,0xd3,0x7e,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x42,0xd3,0x7f,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x42,0xd3,0x80,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x42,0xd3,0xc1,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x42,0xd3,0xf0,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x42,0xd3,0xf7,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x20]
-
-v_trunc_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x42,0xd3,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x42,0xd3,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x08]
-
-v_trunc_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x10]
-
-v_trunc_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x18]
-
-v_ceil_f32 v5, v1
-// CHECK: [0x01,0x45,0x0a,0x7e]
-
-v_ceil_f32 v255, v1
-// CHECK: [0x01,0x45,0xfe,0x7f]
-
-v_ceil_f32 v5, v255
-// CHECK: [0xff,0x45,0x0a,0x7e]
-
-v_ceil_f32 v5, s1
-// CHECK: [0x01,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, s103
-// CHECK: [0x67,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, vcc_lo
-// CHECK: [0x6a,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, vcc_hi
-// CHECK: [0x6b,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, tba_lo
-// CHECK: [0x6c,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, tba_hi
-// CHECK: [0x6d,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, tma_lo
-// CHECK: [0x6e,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, tma_hi
-// CHECK: [0x6f,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, ttmp11
-// CHECK: [0x7b,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, m0
-// CHECK: [0x7c,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, exec_lo
-// CHECK: [0x7e,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, exec_hi
-// CHECK: [0x7f,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, 0
-// CHECK: [0x80,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, -1
-// CHECK: [0xc1,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, 0.5
-// CHECK: [0xf0,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, -4.0
-// CHECK: [0xf7,0x44,0x0a,0x7e]
-
-v_ceil_f32 v5, 0xaf123456
-// CHECK: [0xff,0x44,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ceil_f32 v5, 0x3f717273
-// CHECK: [0xff,0x44,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ceil_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x44,0xd3,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x44,0xd3,0xff,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x44,0xd3,0x67,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x44,0xd3,0x68,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x44,0xd3,0x69,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x44,0xd3,0x6a,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x44,0xd3,0x6b,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x44,0xd3,0x6c,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x44,0xd3,0x6d,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x44,0xd3,0x6e,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x44,0xd3,0x6f,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x44,0xd3,0x7b,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x44,0xd3,0x7c,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x44,0xd3,0x7e,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x44,0xd3,0x7f,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x44,0xd3,0x80,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x44,0xd3,0xc1,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x44,0xd3,0xf0,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x44,0xd3,0xf7,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x20]
-
-v_ceil_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x44,0xd3,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x44,0xd3,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x08]
-
-v_ceil_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x10]
-
-v_ceil_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x18]
-
-v_rndne_f32 v5, v1
-// CHECK: [0x01,0x47,0x0a,0x7e]
-
-v_rndne_f32 v255, v1
-// CHECK: [0x01,0x47,0xfe,0x7f]
-
-v_rndne_f32 v5, v255
-// CHECK: [0xff,0x47,0x0a,0x7e]
-
-v_rndne_f32 v5, s1
-// CHECK: [0x01,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, s103
-// CHECK: [0x67,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, vcc_lo
-// CHECK: [0x6a,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, vcc_hi
-// CHECK: [0x6b,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, tba_lo
-// CHECK: [0x6c,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, tba_hi
-// CHECK: [0x6d,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, tma_lo
-// CHECK: [0x6e,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, tma_hi
-// CHECK: [0x6f,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, ttmp11
-// CHECK: [0x7b,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, m0
-// CHECK: [0x7c,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, exec_lo
-// CHECK: [0x7e,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, exec_hi
-// CHECK: [0x7f,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, 0
-// CHECK: [0x80,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, -1
-// CHECK: [0xc1,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, 0.5
-// CHECK: [0xf0,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, -4.0
-// CHECK: [0xf7,0x46,0x0a,0x7e]
-
-v_rndne_f32 v5, 0xaf123456
-// CHECK: [0xff,0x46,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rndne_f32 v5, 0x3f717273
-// CHECK: [0xff,0x46,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rndne_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x46,0xd3,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x46,0xd3,0xff,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x46,0xd3,0x67,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x46,0xd3,0x68,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x46,0xd3,0x69,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x46,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x46,0xd3,0x6b,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x46,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x46,0xd3,0x6d,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x46,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x46,0xd3,0x6f,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x46,0xd3,0x7b,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x46,0xd3,0x7c,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x46,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x46,0xd3,0x7f,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x46,0xd3,0x80,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x46,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x46,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x46,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x20]
-
-v_rndne_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x46,0xd3,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x46,0xd3,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x08]
-
-v_rndne_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x10]
-
-v_rndne_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x18]
-
-v_floor_f32 v5, v1
-// CHECK: [0x01,0x49,0x0a,0x7e]
-
-v_floor_f32 v255, v1
-// CHECK: [0x01,0x49,0xfe,0x7f]
-
-v_floor_f32 v5, v255
-// CHECK: [0xff,0x49,0x0a,0x7e]
-
-v_floor_f32 v5, s1
-// CHECK: [0x01,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, s103
-// CHECK: [0x67,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, vcc_lo
-// CHECK: [0x6a,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, vcc_hi
-// CHECK: [0x6b,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, tba_lo
-// CHECK: [0x6c,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, tba_hi
-// CHECK: [0x6d,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, tma_lo
-// CHECK: [0x6e,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, tma_hi
-// CHECK: [0x6f,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, ttmp11
-// CHECK: [0x7b,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, m0
-// CHECK: [0x7c,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, exec_lo
-// CHECK: [0x7e,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, exec_hi
-// CHECK: [0x7f,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, 0
-// CHECK: [0x80,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, -1
-// CHECK: [0xc1,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, 0.5
-// CHECK: [0xf0,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, -4.0
-// CHECK: [0xf7,0x48,0x0a,0x7e]
-
-v_floor_f32 v5, 0xaf123456
-// CHECK: [0xff,0x48,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_floor_f32 v5, 0x3f717273
-// CHECK: [0xff,0x48,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_floor_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x48,0xd3,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x48,0xd3,0xff,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x48,0xd3,0x67,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x48,0xd3,0x68,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x48,0xd3,0x69,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x48,0xd3,0x6a,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x48,0xd3,0x6b,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x48,0xd3,0x6c,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x48,0xd3,0x6d,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x48,0xd3,0x6e,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x48,0xd3,0x6f,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x48,0xd3,0x7b,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x48,0xd3,0x7c,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x48,0xd3,0x7e,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x48,0xd3,0x7f,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x48,0xd3,0x80,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x48,0xd3,0xc1,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x48,0xd3,0xf0,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x48,0xd3,0xf7,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x20]
-
-v_floor_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x48,0xd3,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x48,0xd3,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x08]
-
-v_floor_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x10]
-
-v_floor_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x18]
-
-v_exp_f32 v5, v1
-// CHECK: [0x01,0x4b,0x0a,0x7e]
-
-v_exp_f32 v255, v1
-// CHECK: [0x01,0x4b,0xfe,0x7f]
-
-v_exp_f32 v5, v255
-// CHECK: [0xff,0x4b,0x0a,0x7e]
-
-v_exp_f32 v5, s1
-// CHECK: [0x01,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, s103
-// CHECK: [0x67,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, vcc_lo
-// CHECK: [0x6a,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, vcc_hi
-// CHECK: [0x6b,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, tba_lo
-// CHECK: [0x6c,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, tba_hi
-// CHECK: [0x6d,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, tma_lo
-// CHECK: [0x6e,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, tma_hi
-// CHECK: [0x6f,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, ttmp11
-// CHECK: [0x7b,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, m0
-// CHECK: [0x7c,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, exec_lo
-// CHECK: [0x7e,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, exec_hi
-// CHECK: [0x7f,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, 0
-// CHECK: [0x80,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, -1
-// CHECK: [0xc1,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, 0.5
-// CHECK: [0xf0,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, -4.0
-// CHECK: [0xf7,0x4a,0x0a,0x7e]
-
-v_exp_f32 v5, 0xaf123456
-// CHECK: [0xff,0x4a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_exp_f32 v5, 0x3f717273
-// CHECK: [0xff,0x4a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_exp_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x4a,0xd3,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x4a,0xd3,0xff,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x4a,0xd3,0x67,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4a,0xd3,0x68,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4a,0xd3,0x69,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4a,0xd3,0x6a,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4a,0xd3,0x6b,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x4a,0xd3,0x6c,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x4a,0xd3,0x6d,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x4a,0xd3,0x6e,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x4a,0xd3,0x6f,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x4a,0xd3,0x7b,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x4a,0xd3,0x7c,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4a,0xd3,0x7e,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4a,0xd3,0x7f,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x4a,0xd3,0x80,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x4a,0xd3,0xc1,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4a,0xd3,0xf0,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4a,0xd3,0xf7,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x20]
-
-v_exp_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x08]
-
-v_exp_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x10]
-
-v_exp_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x18]
-
-v_log_clamp_f32 v5, v1
-// CHECK: [0x01,0x4d,0x0a,0x7e]
-
-v_log_clamp_f32 v255, v1
-// CHECK: [0x01,0x4d,0xfe,0x7f]
-
-v_log_clamp_f32 v5, v255
-// CHECK: [0xff,0x4d,0x0a,0x7e]
-
-v_log_clamp_f32 v5, s1
-// CHECK: [0x01,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, s103
-// CHECK: [0x67,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, vcc_lo
-// CHECK: [0x6a,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, vcc_hi
-// CHECK: [0x6b,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, tba_lo
-// CHECK: [0x6c,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, tba_hi
-// CHECK: [0x6d,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, tma_lo
-// CHECK: [0x6e,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, tma_hi
-// CHECK: [0x6f,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, ttmp11
-// CHECK: [0x7b,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, m0
-// CHECK: [0x7c,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, exec_lo
-// CHECK: [0x7e,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, exec_hi
-// CHECK: [0x7f,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, 0
-// CHECK: [0x80,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, -1
-// CHECK: [0xc1,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, 0.5
-// CHECK: [0xf0,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, -4.0
-// CHECK: [0xf7,0x4c,0x0a,0x7e]
-
-v_log_clamp_f32 v5, 0xaf123456
-// CHECK: [0xff,0x4c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_log_clamp_f32 v5, 0x3f717273
-// CHECK: [0xff,0x4c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_log_clamp_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x00]
-
-v_log_clamp_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x4c,0xd3,0x01,0x01,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x4c,0xd3,0xff,0x01,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x4c,0xd3,0x67,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4c,0xd3,0x68,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4c,0xd3,0x69,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4c,0xd3,0x6a,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4c,0xd3,0x6b,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x4c,0xd3,0x6c,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x4c,0xd3,0x6d,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x4c,0xd3,0x6e,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x4c,0xd3,0x6f,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x4c,0xd3,0x7b,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x4c,0xd3,0x7c,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4c,0xd3,0x7e,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4c,0xd3,0x7f,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x4c,0xd3,0x80,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x4c,0xd3,0xc1,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4c,0xd3,0xf0,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4c,0xd3,0xf7,0x00,0x00,0x00]
-
-v_log_clamp_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x20]
-
-v_log_clamp_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x08]
-
-v_log_clamp_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x10]
-
-v_log_clamp_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x18]
-
-v_log_f32 v5, v1
-// CHECK: [0x01,0x4f,0x0a,0x7e]
-
-v_log_f32 v255, v1
-// CHECK: [0x01,0x4f,0xfe,0x7f]
-
-v_log_f32 v5, v255
-// CHECK: [0xff,0x4f,0x0a,0x7e]
-
-v_log_f32 v5, s1
-// CHECK: [0x01,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, s103
-// CHECK: [0x67,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, vcc_lo
-// CHECK: [0x6a,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, vcc_hi
-// CHECK: [0x6b,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, tba_lo
-// CHECK: [0x6c,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, tba_hi
-// CHECK: [0x6d,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, tma_lo
-// CHECK: [0x6e,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, tma_hi
-// CHECK: [0x6f,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, ttmp11
-// CHECK: [0x7b,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, m0
-// CHECK: [0x7c,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, exec_lo
-// CHECK: [0x7e,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, exec_hi
-// CHECK: [0x7f,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, 0
-// CHECK: [0x80,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, -1
-// CHECK: [0xc1,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, 0.5
-// CHECK: [0xf0,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, -4.0
-// CHECK: [0xf7,0x4e,0x0a,0x7e]
-
-v_log_f32 v5, 0xaf123456
-// CHECK: [0xff,0x4e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_log_f32 v5, 0x3f717273
-// CHECK: [0xff,0x4e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_log_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x4e,0xd3,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x4e,0xd3,0xff,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x4e,0xd3,0x67,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4e,0xd3,0x68,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4e,0xd3,0x69,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4e,0xd3,0x6a,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4e,0xd3,0x6b,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x4e,0xd3,0x6c,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x4e,0xd3,0x6d,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x4e,0xd3,0x6e,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x4e,0xd3,0x6f,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x4e,0xd3,0x7b,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x4e,0xd3,0x7c,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4e,0xd3,0x7e,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4e,0xd3,0x7f,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x4e,0xd3,0x80,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x4e,0xd3,0xc1,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4e,0xd3,0xf0,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4e,0xd3,0xf7,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x20]
-
-v_log_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x08]
-
-v_log_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x10]
-
-v_log_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x18]
-
-v_rcp_clamp_f32 v5, v1
-// CHECK: [0x01,0x51,0x0a,0x7e]
-
-v_rcp_clamp_f32 v255, v1
-// CHECK: [0x01,0x51,0xfe,0x7f]
-
-v_rcp_clamp_f32 v5, v255
-// CHECK: [0xff,0x51,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, s1
-// CHECK: [0x01,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, s103
-// CHECK: [0x67,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, vcc_lo
-// CHECK: [0x6a,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, vcc_hi
-// CHECK: [0x6b,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, tba_lo
-// CHECK: [0x6c,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, tba_hi
-// CHECK: [0x6d,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, tma_lo
-// CHECK: [0x6e,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, tma_hi
-// CHECK: [0x6f,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, ttmp11
-// CHECK: [0x7b,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, m0
-// CHECK: [0x7c,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, exec_lo
-// CHECK: [0x7e,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, exec_hi
-// CHECK: [0x7f,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, 0
-// CHECK: [0x80,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, -1
-// CHECK: [0xc1,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, 0.5
-// CHECK: [0xf0,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, -4.0
-// CHECK: [0xf7,0x50,0x0a,0x7e]
-
-v_rcp_clamp_f32 v5, 0xaf123456
-// CHECK: [0xff,0x50,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_clamp_f32 v5, 0x3f717273
-// CHECK: [0xff,0x50,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_clamp_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x50,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x50,0xd3,0xff,0x01,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x50,0xd3,0x67,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x50,0xd3,0x68,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x50,0xd3,0x69,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x50,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x50,0xd3,0x6b,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x50,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x50,0xd3,0x6d,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x50,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x50,0xd3,0x6f,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x50,0xd3,0x7b,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x50,0xd3,0x7c,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x50,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x50,0xd3,0x7f,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x50,0xd3,0x80,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x50,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x50,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x50,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rcp_clamp_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x20]
-
-v_rcp_clamp_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x08]
-
-v_rcp_clamp_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x10]
-
-v_rcp_clamp_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x18]
-
-v_rcp_legacy_f32 v5, v1
-// CHECK: [0x01,0x53,0x0a,0x7e]
-
-v_rcp_legacy_f32 v255, v1
-// CHECK: [0x01,0x53,0xfe,0x7f]
-
-v_rcp_legacy_f32 v5, v255
-// CHECK: [0xff,0x53,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, s1
-// CHECK: [0x01,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, s103
-// CHECK: [0x67,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, vcc_lo
-// CHECK: [0x6a,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, vcc_hi
-// CHECK: [0x6b,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, tba_lo
-// CHECK: [0x6c,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, tba_hi
-// CHECK: [0x6d,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, tma_lo
-// CHECK: [0x6e,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, tma_hi
-// CHECK: [0x6f,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, ttmp11
-// CHECK: [0x7b,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, m0
-// CHECK: [0x7c,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, exec_lo
-// CHECK: [0x7e,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, exec_hi
-// CHECK: [0x7f,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, 0
-// CHECK: [0x80,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, -1
-// CHECK: [0xc1,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, 0.5
-// CHECK: [0xf0,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, -4.0
-// CHECK: [0xf7,0x52,0x0a,0x7e]
-
-v_rcp_legacy_f32 v5, 0xaf123456
-// CHECK: [0xff,0x52,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_legacy_f32 v5, 0x3f717273
-// CHECK: [0xff,0x52,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_legacy_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x52,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x52,0xd3,0xff,0x01,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x52,0xd3,0x67,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x52,0xd3,0x68,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x52,0xd3,0x69,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x52,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x52,0xd3,0x6b,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x52,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x52,0xd3,0x6d,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x52,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x52,0xd3,0x6f,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x52,0xd3,0x7b,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x52,0xd3,0x7c,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x52,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x52,0xd3,0x7f,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x52,0xd3,0x80,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x52,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x52,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x52,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rcp_legacy_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x20]
-
-v_rcp_legacy_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x08]
-
-v_rcp_legacy_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x10]
-
-v_rcp_legacy_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x18]
-
-v_rcp_f32 v5, v1
-// CHECK: [0x01,0x55,0x0a,0x7e]
-
-v_rcp_f32 v255, v1
-// CHECK: [0x01,0x55,0xfe,0x7f]
-
-v_rcp_f32 v5, v255
-// CHECK: [0xff,0x55,0x0a,0x7e]
-
-v_rcp_f32 v5, s1
-// CHECK: [0x01,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, s103
-// CHECK: [0x67,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, vcc_lo
-// CHECK: [0x6a,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, vcc_hi
-// CHECK: [0x6b,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, tba_lo
-// CHECK: [0x6c,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, tba_hi
-// CHECK: [0x6d,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, tma_lo
-// CHECK: [0x6e,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, tma_hi
-// CHECK: [0x6f,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, ttmp11
-// CHECK: [0x7b,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, m0
-// CHECK: [0x7c,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, exec_lo
-// CHECK: [0x7e,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, exec_hi
-// CHECK: [0x7f,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, 0
-// CHECK: [0x80,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, -1
-// CHECK: [0xc1,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, 0.5
-// CHECK: [0xf0,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, -4.0
-// CHECK: [0xf7,0x54,0x0a,0x7e]
-
-v_rcp_f32 v5, 0xaf123456
-// CHECK: [0xff,0x54,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_f32 v5, 0x3f717273
-// CHECK: [0xff,0x54,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x54,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x54,0xd3,0xff,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x54,0xd3,0x67,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x54,0xd3,0x68,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x54,0xd3,0x69,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x54,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x54,0xd3,0x6b,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x54,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x54,0xd3,0x6d,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x54,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x54,0xd3,0x6f,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x54,0xd3,0x7b,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x54,0xd3,0x7c,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x54,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x54,0xd3,0x7f,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x54,0xd3,0x80,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x54,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x54,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x54,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x20]
-
-v_rcp_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x08]
-
-v_rcp_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x10]
-
-v_rcp_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x18]
-
-v_rcp_iflag_f32 v5, v1
-// CHECK: [0x01,0x57,0x0a,0x7e]
-
-v_rcp_iflag_f32 v255, v1
-// CHECK: [0x01,0x57,0xfe,0x7f]
-
-v_rcp_iflag_f32 v5, v255
-// CHECK: [0xff,0x57,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, s1
-// CHECK: [0x01,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, s103
-// CHECK: [0x67,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, vcc_lo
-// CHECK: [0x6a,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, vcc_hi
-// CHECK: [0x6b,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, tba_lo
-// CHECK: [0x6c,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, tba_hi
-// CHECK: [0x6d,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, tma_lo
-// CHECK: [0x6e,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, tma_hi
-// CHECK: [0x6f,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, ttmp11
-// CHECK: [0x7b,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, m0
-// CHECK: [0x7c,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, exec_lo
-// CHECK: [0x7e,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, exec_hi
-// CHECK: [0x7f,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0
-// CHECK: [0x80,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, -1
-// CHECK: [0xc1,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0.5
-// CHECK: [0xf0,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, -4.0
-// CHECK: [0xf7,0x56,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0xaf123456
-// CHECK: [0xff,0x56,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_iflag_f32 v5, 0x3f717273
-// CHECK: [0xff,0x56,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_iflag_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x56,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x56,0xd3,0xff,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x56,0xd3,0x67,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x56,0xd3,0x68,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x56,0xd3,0x69,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x56,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x56,0xd3,0x6b,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x56,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x56,0xd3,0x6d,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x56,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x56,0xd3,0x6f,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x56,0xd3,0x7b,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x56,0xd3,0x7c,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x56,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x56,0xd3,0x7f,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x56,0xd3,0x80,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x56,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x56,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x56,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x20]
-
-v_rcp_iflag_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x56,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x56,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x08]
-
-v_rcp_iflag_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x10]
-
-v_rcp_iflag_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x18]
-
-v_rsq_clamp_f32 v5, v1
-// CHECK: [0x01,0x59,0x0a,0x7e]
-
-v_rsq_clamp_f32 v255, v1
-// CHECK: [0x01,0x59,0xfe,0x7f]
-
-v_rsq_clamp_f32 v5, v255
-// CHECK: [0xff,0x59,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, s1
-// CHECK: [0x01,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, s103
-// CHECK: [0x67,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, vcc_lo
-// CHECK: [0x6a,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, vcc_hi
-// CHECK: [0x6b,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, tba_lo
-// CHECK: [0x6c,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, tba_hi
-// CHECK: [0x6d,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, tma_lo
-// CHECK: [0x6e,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, tma_hi
-// CHECK: [0x6f,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, ttmp11
-// CHECK: [0x7b,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, m0
-// CHECK: [0x7c,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, exec_lo
-// CHECK: [0x7e,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, exec_hi
-// CHECK: [0x7f,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, 0
-// CHECK: [0x80,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, -1
-// CHECK: [0xc1,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, 0.5
-// CHECK: [0xf0,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, -4.0
-// CHECK: [0xf7,0x58,0x0a,0x7e]
-
-v_rsq_clamp_f32 v5, 0xaf123456
-// CHECK: [0xff,0x58,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_clamp_f32 v5, 0x3f717273
-// CHECK: [0xff,0x58,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_clamp_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x58,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x58,0xd3,0xff,0x01,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x58,0xd3,0x67,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x58,0xd3,0x68,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x58,0xd3,0x69,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x58,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x58,0xd3,0x6b,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x58,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x58,0xd3,0x6d,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x58,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x58,0xd3,0x6f,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x58,0xd3,0x7b,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x58,0xd3,0x7c,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x58,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x58,0xd3,0x7f,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x58,0xd3,0x80,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x58,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x58,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x58,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x20]
-
-v_rsq_clamp_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x58,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x58,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_clamp_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x08]
-
-v_rsq_clamp_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x10]
-
-v_rsq_clamp_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x18]
-
-v_rsq_legacy_f32 v5, v1
-// CHECK: [0x01,0x5b,0x0a,0x7e]
-
-v_rsq_legacy_f32 v255, v1
-// CHECK: [0x01,0x5b,0xfe,0x7f]
-
-v_rsq_legacy_f32 v5, v255
-// CHECK: [0xff,0x5b,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, s1
-// CHECK: [0x01,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, s103
-// CHECK: [0x67,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, vcc_lo
-// CHECK: [0x6a,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, vcc_hi
-// CHECK: [0x6b,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, tba_lo
-// CHECK: [0x6c,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, tba_hi
-// CHECK: [0x6d,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, tma_lo
-// CHECK: [0x6e,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, tma_hi
-// CHECK: [0x6f,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, ttmp11
-// CHECK: [0x7b,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, m0
-// CHECK: [0x7c,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, exec_lo
-// CHECK: [0x7e,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, exec_hi
-// CHECK: [0x7f,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, 0
-// CHECK: [0x80,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, -1
-// CHECK: [0xc1,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, 0.5
-// CHECK: [0xf0,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, -4.0
-// CHECK: [0xf7,0x5a,0x0a,0x7e]
-
-v_rsq_legacy_f32 v5, 0xaf123456
-// CHECK: [0xff,0x5a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_legacy_f32 v5, 0x3f717273
-// CHECK: [0xff,0x5a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_legacy_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5a,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5a,0xd3,0xff,0x01,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x5a,0xd3,0x67,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5a,0xd3,0x68,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5a,0xd3,0x69,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5a,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5a,0xd3,0x6b,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x5a,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x5a,0xd3,0x6d,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x5a,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x5a,0xd3,0x6f,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x5a,0xd3,0x7b,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5a,0xd3,0x7c,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5a,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5a,0xd3,0x7f,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5a,0xd3,0x80,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5a,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5a,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5a,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x20]
-
-v_rsq_legacy_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x5a,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x5a,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_legacy_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x08]
-
-v_rsq_legacy_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x10]
-
-v_rsq_legacy_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x18]
-
-v_rsq_f32 v5, v1
-// CHECK: [0x01,0x5d,0x0a,0x7e]
-
-v_rsq_f32 v255, v1
-// CHECK: [0x01,0x5d,0xfe,0x7f]
-
-v_rsq_f32 v5, v255
-// CHECK: [0xff,0x5d,0x0a,0x7e]
-
-v_rsq_f32 v5, s1
-// CHECK: [0x01,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, s103
-// CHECK: [0x67,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, vcc_lo
-// CHECK: [0x6a,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, vcc_hi
-// CHECK: [0x6b,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, tba_lo
-// CHECK: [0x6c,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, tba_hi
-// CHECK: [0x6d,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, tma_lo
-// CHECK: [0x6e,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, tma_hi
-// CHECK: [0x6f,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, ttmp11
-// CHECK: [0x7b,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, m0
-// CHECK: [0x7c,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, exec_lo
-// CHECK: [0x7e,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, exec_hi
-// CHECK: [0x7f,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, 0
-// CHECK: [0x80,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, -1
-// CHECK: [0xc1,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, 0.5
-// CHECK: [0xf0,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, -4.0
-// CHECK: [0xf7,0x5c,0x0a,0x7e]
-
-v_rsq_f32 v5, 0xaf123456
-// CHECK: [0xff,0x5c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_f32 v5, 0x3f717273
-// CHECK: [0xff,0x5c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5c,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5c,0xd3,0xff,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x5c,0xd3,0x67,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5c,0xd3,0x68,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5c,0xd3,0x69,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5c,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5c,0xd3,0x6b,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x5c,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x5c,0xd3,0x6d,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x5c,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x5c,0xd3,0x6f,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x5c,0xd3,0x7b,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5c,0xd3,0x7c,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5c,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5c,0xd3,0x7f,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5c,0xd3,0x80,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5c,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5c,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5c,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x20]
-
-v_rsq_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x5c,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x5c,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x08]
-
-v_rsq_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x10]
-
-v_rsq_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x18]
-
-v_rcp_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x5f,0x0a,0x7e]
-
-v_rcp_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x5f,0xfc,0x7f]
-
-v_rcp_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x5f,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], vcc
-// CHECK: [0x6a,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], tba
-// CHECK: [0x6c,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], tma
-// CHECK: [0x6e,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], exec
-// CHECK: [0x7e,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0
-// CHECK: [0x80,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], -1
-// CHECK: [0xc1,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x5e,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x5e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x5e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x5e,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x5e,0xd3,0xfe,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x5e,0xd3,0x02,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x5e,0xd3,0x04,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x5e,0xd3,0x66,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x5e,0xd3,0x68,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x5e,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x5e,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x5e,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x5e,0xd3,0x7a,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x5e,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x5e,0xd3,0x80,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x5e,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x5e,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x5e,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x20]
-
-v_rcp_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x5e,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x5e,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x08]
-
-v_rcp_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x10]
-
-v_rcp_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x18]
-
-v_rcp_clamp_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x61,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x61,0xfc,0x7f]
-
-v_rcp_clamp_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x61,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], vcc
-// CHECK: [0x6a,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], tba
-// CHECK: [0x6c,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], tma
-// CHECK: [0x6e,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], exec
-// CHECK: [0x7e,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], 0
-// CHECK: [0x80,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], -1
-// CHECK: [0xc1,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x60,0x0a,0x7e]
-
-v_rcp_clamp_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x60,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_clamp_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x60,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_clamp_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x60,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x60,0xd3,0xfe,0x01,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x60,0xd3,0x02,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x60,0xd3,0x04,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x60,0xd3,0x66,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x60,0xd3,0x68,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x60,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x60,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x60,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x60,0xd3,0x7a,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x60,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x60,0xd3,0x80,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x60,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x60,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x60,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x20]
-
-v_rcp_clamp_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x60,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x60,0xd3,0x01,0x01,0x00,0x00]
-
-v_rcp_clamp_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x08]
-
-v_rcp_clamp_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x10]
-
-v_rcp_clamp_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x18]
-
-v_rsq_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x63,0x0a,0x7e]
-
-v_rsq_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x63,0xfc,0x7f]
-
-v_rsq_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x63,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], vcc
-// CHECK: [0x6a,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], tba
-// CHECK: [0x6c,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], tma
-// CHECK: [0x6e,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], exec
-// CHECK: [0x7e,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0
-// CHECK: [0x80,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], -1
-// CHECK: [0xc1,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x62,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x62,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x62,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x62,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x62,0xd3,0xfe,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x62,0xd3,0x02,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x62,0xd3,0x04,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x62,0xd3,0x66,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x62,0xd3,0x68,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x62,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x62,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x62,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x62,0xd3,0x7a,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x62,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x62,0xd3,0x80,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x62,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x62,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x62,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x20]
-
-v_rsq_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x62,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x62,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x08]
-
-v_rsq_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x10]
-
-v_rsq_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x18]
-
-v_rsq_clamp_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x65,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x65,0xfc,0x7f]
-
-v_rsq_clamp_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x65,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], vcc
-// CHECK: [0x6a,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], tba
-// CHECK: [0x6c,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], tma
-// CHECK: [0x6e,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], exec
-// CHECK: [0x7e,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], 0
-// CHECK: [0x80,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], -1
-// CHECK: [0xc1,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x64,0x0a,0x7e]
-
-v_rsq_clamp_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x64,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_clamp_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x64,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_clamp_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x64,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x64,0xd3,0xfe,0x01,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x64,0xd3,0x02,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x64,0xd3,0x04,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x64,0xd3,0x66,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x64,0xd3,0x68,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x64,0xd3,0x6a,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x64,0xd3,0x6c,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x64,0xd3,0x6e,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x64,0xd3,0x7a,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x64,0xd3,0x7e,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x64,0xd3,0x80,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x64,0xd3,0xc1,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x64,0xd3,0xf0,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x64,0xd3,0xf7,0x00,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x20]
-
-v_rsq_clamp_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x64,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x64,0xd3,0x01,0x01,0x00,0x00]
-
-v_rsq_clamp_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x08]
-
-v_rsq_clamp_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x10]
-
-v_rsq_clamp_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x18]
-
-v_sqrt_f32 v5, v1
-// CHECK: [0x01,0x67,0x0a,0x7e]
-
-v_sqrt_f32 v255, v1
-// CHECK: [0x01,0x67,0xfe,0x7f]
-
-v_sqrt_f32 v5, v255
-// CHECK: [0xff,0x67,0x0a,0x7e]
-
-v_sqrt_f32 v5, s1
-// CHECK: [0x01,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, s103
-// CHECK: [0x67,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, vcc_lo
-// CHECK: [0x6a,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, vcc_hi
-// CHECK: [0x6b,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, tba_lo
-// CHECK: [0x6c,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, tba_hi
-// CHECK: [0x6d,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, tma_lo
-// CHECK: [0x6e,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, tma_hi
-// CHECK: [0x6f,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, ttmp11
-// CHECK: [0x7b,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, m0
-// CHECK: [0x7c,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, exec_lo
-// CHECK: [0x7e,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, exec_hi
-// CHECK: [0x7f,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0
-// CHECK: [0x80,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, -1
-// CHECK: [0xc1,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0.5
-// CHECK: [0xf0,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, -4.0
-// CHECK: [0xf7,0x66,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0xaf123456
-// CHECK: [0xff,0x66,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sqrt_f32 v5, 0x3f717273
-// CHECK: [0xff,0x66,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sqrt_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x66,0xd3,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x66,0xd3,0xff,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x66,0xd3,0x67,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x66,0xd3,0x68,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x66,0xd3,0x69,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x66,0xd3,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x66,0xd3,0x6b,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x66,0xd3,0x6c,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x66,0xd3,0x6d,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x66,0xd3,0x6e,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x66,0xd3,0x6f,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x66,0xd3,0x7b,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x66,0xd3,0x7c,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x66,0xd3,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x66,0xd3,0x7f,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x66,0xd3,0x80,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x66,0xd3,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x66,0xd3,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x66,0xd3,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x20]
-
-v_sqrt_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x66,0xd3,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x66,0xd3,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x08]
-
-v_sqrt_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x10]
-
-v_sqrt_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x18]
-
-v_sqrt_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x69,0x0a,0x7e]
-
-v_sqrt_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x69,0xfc,0x7f]
-
-v_sqrt_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x69,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], vcc
-// CHECK: [0x6a,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], tba
-// CHECK: [0x6c,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], tma
-// CHECK: [0x6e,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], exec
-// CHECK: [0x7e,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0
-// CHECK: [0x80,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], -1
-// CHECK: [0xc1,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x68,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x68,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sqrt_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x68,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sqrt_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x68,0xd3,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x68,0xd3,0xfe,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x68,0xd3,0x02,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x68,0xd3,0x04,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x68,0xd3,0x66,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x68,0xd3,0x68,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x68,0xd3,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x68,0xd3,0x6c,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x68,0xd3,0x6e,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x68,0xd3,0x7a,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x68,0xd3,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x68,0xd3,0x80,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x68,0xd3,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x68,0xd3,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x68,0xd3,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x20]
-
-v_sqrt_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x68,0xd3,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x68,0xd3,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x08]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x10]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x18]
-
-v_sin_f32 v5, v1
-// CHECK: [0x01,0x6b,0x0a,0x7e]
-
-v_sin_f32 v255, v1
-// CHECK: [0x01,0x6b,0xfe,0x7f]
-
-v_sin_f32 v5, v255
-// CHECK: [0xff,0x6b,0x0a,0x7e]
-
-v_sin_f32 v5, s1
-// CHECK: [0x01,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, s103
-// CHECK: [0x67,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, vcc_lo
-// CHECK: [0x6a,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, vcc_hi
-// CHECK: [0x6b,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, tba_lo
-// CHECK: [0x6c,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, tba_hi
-// CHECK: [0x6d,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, tma_lo
-// CHECK: [0x6e,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, tma_hi
-// CHECK: [0x6f,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, ttmp11
-// CHECK: [0x7b,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, m0
-// CHECK: [0x7c,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, exec_lo
-// CHECK: [0x7e,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, exec_hi
-// CHECK: [0x7f,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, 0
-// CHECK: [0x80,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, -1
-// CHECK: [0xc1,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, 0.5
-// CHECK: [0xf0,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, -4.0
-// CHECK: [0xf7,0x6a,0x0a,0x7e]
-
-v_sin_f32 v5, 0xaf123456
-// CHECK: [0xff,0x6a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sin_f32 v5, 0x3f717273
-// CHECK: [0xff,0x6a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sin_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6a,0xd3,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6a,0xd3,0xff,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x6a,0xd3,0x67,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6a,0xd3,0x68,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6a,0xd3,0x69,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6a,0xd3,0x6a,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6a,0xd3,0x6b,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x6a,0xd3,0x6c,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x6a,0xd3,0x6d,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x6a,0xd3,0x6e,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x6a,0xd3,0x6f,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x6a,0xd3,0x7b,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6a,0xd3,0x7c,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6a,0xd3,0x7e,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6a,0xd3,0x7f,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6a,0xd3,0x80,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6a,0xd3,0xc1,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6a,0xd3,0xf0,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6a,0xd3,0xf7,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x20]
-
-v_sin_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x6a,0xd3,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x6a,0xd3,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x08]
-
-v_sin_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x10]
-
-v_sin_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x18]
-
-v_cos_f32 v5, v1
-// CHECK: [0x01,0x6d,0x0a,0x7e]
-
-v_cos_f32 v255, v1
-// CHECK: [0x01,0x6d,0xfe,0x7f]
-
-v_cos_f32 v5, v255
-// CHECK: [0xff,0x6d,0x0a,0x7e]
-
-v_cos_f32 v5, s1
-// CHECK: [0x01,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, s103
-// CHECK: [0x67,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, vcc_lo
-// CHECK: [0x6a,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, vcc_hi
-// CHECK: [0x6b,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, tba_lo
-// CHECK: [0x6c,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, tba_hi
-// CHECK: [0x6d,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, tma_lo
-// CHECK: [0x6e,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, tma_hi
-// CHECK: [0x6f,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, ttmp11
-// CHECK: [0x7b,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, m0
-// CHECK: [0x7c,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, exec_lo
-// CHECK: [0x7e,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, exec_hi
-// CHECK: [0x7f,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, 0
-// CHECK: [0x80,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, -1
-// CHECK: [0xc1,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, 0.5
-// CHECK: [0xf0,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, -4.0
-// CHECK: [0xf7,0x6c,0x0a,0x7e]
-
-v_cos_f32 v5, 0xaf123456
-// CHECK: [0xff,0x6c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cos_f32 v5, 0x3f717273
-// CHECK: [0xff,0x6c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cos_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6c,0xd3,0xff,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x6c,0xd3,0x67,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6c,0xd3,0x68,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6c,0xd3,0x69,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6c,0xd3,0x6a,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6c,0xd3,0x6b,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x6c,0xd3,0x6c,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x6c,0xd3,0x6d,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x6c,0xd3,0x6e,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x6c,0xd3,0x6f,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x6c,0xd3,0x7b,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6c,0xd3,0x7c,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6c,0xd3,0x7e,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6c,0xd3,0x7f,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6c,0xd3,0x80,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6c,0xd3,0xc1,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6c,0xd3,0xf0,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6c,0xd3,0xf7,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x20]
-
-v_cos_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x6c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x6c,0xd3,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x08]
-
-v_cos_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x10]
-
-v_cos_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x18]
-
-v_not_b32 v5, v1
-// CHECK: [0x01,0x6f,0x0a,0x7e]
-
-v_not_b32 v255, v1
-// CHECK: [0x01,0x6f,0xfe,0x7f]
-
-v_not_b32 v5, v255
-// CHECK: [0xff,0x6f,0x0a,0x7e]
-
-v_not_b32 v5, s1
-// CHECK: [0x01,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, s103
-// CHECK: [0x67,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, flat_scratch_lo
-// CHECK: [0x68,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, flat_scratch_hi
-// CHECK: [0x69,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, vcc_lo
-// CHECK: [0x6a,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, vcc_hi
-// CHECK: [0x6b,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, tba_lo
-// CHECK: [0x6c,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, tba_hi
-// CHECK: [0x6d,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, tma_lo
-// CHECK: [0x6e,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, tma_hi
-// CHECK: [0x6f,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, ttmp11
-// CHECK: [0x7b,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, m0
-// CHECK: [0x7c,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, exec_lo
-// CHECK: [0x7e,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, exec_hi
-// CHECK: [0x7f,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, 0
-// CHECK: [0x80,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, -1
-// CHECK: [0xc1,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, 0.5
-// CHECK: [0xf0,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, -4.0
-// CHECK: [0xf7,0x6e,0x0a,0x7e]
-
-v_not_b32 v5, 0xaf123456
-// CHECK: [0xff,0x6e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_not_b32 v5, 0x3f717273
-// CHECK: [0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_not_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6e,0xd3,0x01,0x01,0x00,0x00]
-
-v_not_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6e,0xd3,0x01,0x01,0x00,0x00]
-
-v_not_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6e,0xd3,0xff,0x01,0x00,0x00]
-
-v_not_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6e,0xd3,0x01,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, s103
-// CHECK: [0x05,0x00,0x6e,0xd3,0x67,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6e,0xd3,0x68,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6e,0xd3,0x69,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6e,0xd3,0x6a,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6e,0xd3,0x6b,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x6e,0xd3,0x6c,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x6e,0xd3,0x6d,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x6e,0xd3,0x6e,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x6e,0xd3,0x6f,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x6e,0xd3,0x7b,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6e,0xd3,0x7c,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6e,0xd3,0x7e,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6e,0xd3,0x7f,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6e,0xd3,0x80,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6e,0xd3,0xc1,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6e,0xd3,0xf0,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6e,0xd3,0xf7,0x00,0x00,0x00]
-
-v_bfrev_b32 v5, v1
-// CHECK: [0x01,0x71,0x0a,0x7e]
-
-v_bfrev_b32 v255, v1
-// CHECK: [0x01,0x71,0xfe,0x7f]
-
-v_bfrev_b32 v5, v255
-// CHECK: [0xff,0x71,0x0a,0x7e]
-
-v_bfrev_b32 v5, s1
-// CHECK: [0x01,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, s103
-// CHECK: [0x67,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, flat_scratch_lo
-// CHECK: [0x68,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, flat_scratch_hi
-// CHECK: [0x69,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, vcc_lo
-// CHECK: [0x6a,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, vcc_hi
-// CHECK: [0x6b,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, tba_lo
-// CHECK: [0x6c,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, tba_hi
-// CHECK: [0x6d,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, tma_lo
-// CHECK: [0x6e,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, tma_hi
-// CHECK: [0x6f,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, ttmp11
-// CHECK: [0x7b,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, m0
-// CHECK: [0x7c,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, exec_lo
-// CHECK: [0x7e,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, exec_hi
-// CHECK: [0x7f,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0
-// CHECK: [0x80,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, -1
-// CHECK: [0xc1,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0.5
-// CHECK: [0xf0,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, -4.0
-// CHECK: [0xf7,0x70,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0xaf123456
-// CHECK: [0xff,0x70,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_bfrev_b32 v5, 0x3f717273
-// CHECK: [0xff,0x70,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_bfrev_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x70,0xd3,0x01,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x70,0xd3,0x01,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x70,0xd3,0xff,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x70,0xd3,0x01,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, s103
-// CHECK: [0x05,0x00,0x70,0xd3,0x67,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x70,0xd3,0x68,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x70,0xd3,0x69,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x70,0xd3,0x6a,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x70,0xd3,0x6b,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x70,0xd3,0x6c,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x70,0xd3,0x6d,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x70,0xd3,0x6e,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x70,0xd3,0x6f,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x70,0xd3,0x7b,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x70,0xd3,0x7c,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x70,0xd3,0x7e,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x70,0xd3,0x7f,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x70,0xd3,0x80,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x70,0xd3,0xc1,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x70,0xd3,0xf0,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x70,0xd3,0xf7,0x00,0x00,0x00]
-
-v_ffbh_u32 v5, v1
-// CHECK: [0x01,0x73,0x0a,0x7e]
-
-v_ffbh_u32 v255, v1
-// CHECK: [0x01,0x73,0xfe,0x7f]
-
-v_ffbh_u32 v5, v255
-// CHECK: [0xff,0x73,0x0a,0x7e]
-
-v_ffbh_u32 v5, s1
-// CHECK: [0x01,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, s103
-// CHECK: [0x67,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, flat_scratch_lo
-// CHECK: [0x68,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, flat_scratch_hi
-// CHECK: [0x69,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, vcc_lo
-// CHECK: [0x6a,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, vcc_hi
-// CHECK: [0x6b,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, tba_lo
-// CHECK: [0x6c,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, tba_hi
-// CHECK: [0x6d,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, tma_lo
-// CHECK: [0x6e,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, tma_hi
-// CHECK: [0x6f,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, ttmp11
-// CHECK: [0x7b,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, m0
-// CHECK: [0x7c,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, exec_lo
-// CHECK: [0x7e,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, exec_hi
-// CHECK: [0x7f,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0
-// CHECK: [0x80,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, -1
-// CHECK: [0xc1,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0.5
-// CHECK: [0xf0,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, -4.0
-// CHECK: [0xf7,0x72,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0xaf123456
-// CHECK: [0xff,0x72,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbh_u32 v5, 0x3f717273
-// CHECK: [0xff,0x72,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbh_u32_e64 v5, v1
-// CHECK: [0x05,0x00,0x72,0xd3,0x01,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v255, v1
-// CHECK: [0xff,0x00,0x72,0xd3,0x01,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v5, v255
-// CHECK: [0x05,0x00,0x72,0xd3,0xff,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v5, s1
-// CHECK: [0x05,0x00,0x72,0xd3,0x01,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, s103
-// CHECK: [0x05,0x00,0x72,0xd3,0x67,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x72,0xd3,0x68,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x72,0xd3,0x69,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x72,0xd3,0x6a,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x72,0xd3,0x6b,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x72,0xd3,0x6c,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x72,0xd3,0x6d,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x72,0xd3,0x6e,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x72,0xd3,0x6f,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x72,0xd3,0x7b,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, m0
-// CHECK: [0x05,0x00,0x72,0xd3,0x7c,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x72,0xd3,0x7e,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x72,0xd3,0x7f,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, 0
-// CHECK: [0x05,0x00,0x72,0xd3,0x80,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, -1
-// CHECK: [0x05,0x00,0x72,0xd3,0xc1,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x72,0xd3,0xf0,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x72,0xd3,0xf7,0x00,0x00,0x00]
-
-v_ffbl_b32 v5, v1
-// CHECK: [0x01,0x75,0x0a,0x7e]
-
-v_ffbl_b32 v255, v1
-// CHECK: [0x01,0x75,0xfe,0x7f]
-
-v_ffbl_b32 v5, v255
-// CHECK: [0xff,0x75,0x0a,0x7e]
-
-v_ffbl_b32 v5, s1
-// CHECK: [0x01,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, s103
-// CHECK: [0x67,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, flat_scratch_lo
-// CHECK: [0x68,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, flat_scratch_hi
-// CHECK: [0x69,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, vcc_lo
-// CHECK: [0x6a,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, vcc_hi
-// CHECK: [0x6b,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, tba_lo
-// CHECK: [0x6c,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, tba_hi
-// CHECK: [0x6d,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, tma_lo
-// CHECK: [0x6e,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, tma_hi
-// CHECK: [0x6f,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, ttmp11
-// CHECK: [0x7b,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, m0
-// CHECK: [0x7c,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, exec_lo
-// CHECK: [0x7e,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, exec_hi
-// CHECK: [0x7f,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0
-// CHECK: [0x80,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, -1
-// CHECK: [0xc1,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0.5
-// CHECK: [0xf0,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, -4.0
-// CHECK: [0xf7,0x74,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0xaf123456
-// CHECK: [0xff,0x74,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbl_b32 v5, 0x3f717273
-// CHECK: [0xff,0x74,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbl_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x74,0xd3,0x01,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x74,0xd3,0x01,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x74,0xd3,0xff,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x74,0xd3,0x01,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, s103
-// CHECK: [0x05,0x00,0x74,0xd3,0x67,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x74,0xd3,0x68,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x74,0xd3,0x69,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x74,0xd3,0x6a,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x74,0xd3,0x6b,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x74,0xd3,0x6c,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x74,0xd3,0x6d,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x74,0xd3,0x6e,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x74,0xd3,0x6f,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x74,0xd3,0x7b,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x74,0xd3,0x7c,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x74,0xd3,0x7e,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x74,0xd3,0x7f,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x74,0xd3,0x80,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x74,0xd3,0xc1,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x74,0xd3,0xf0,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x74,0xd3,0xf7,0x00,0x00,0x00]
-
-v_ffbh_i32 v5, v1
-// CHECK: [0x01,0x77,0x0a,0x7e]
-
-v_ffbh_i32 v255, v1
-// CHECK: [0x01,0x77,0xfe,0x7f]
-
-v_ffbh_i32 v5, v255
-// CHECK: [0xff,0x77,0x0a,0x7e]
-
-v_ffbh_i32 v5, s1
-// CHECK: [0x01,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, s103
-// CHECK: [0x67,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, flat_scratch_lo
-// CHECK: [0x68,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, flat_scratch_hi
-// CHECK: [0x69,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, vcc_lo
-// CHECK: [0x6a,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, vcc_hi
-// CHECK: [0x6b,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, tba_lo
-// CHECK: [0x6c,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, tba_hi
-// CHECK: [0x6d,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, tma_lo
-// CHECK: [0x6e,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, tma_hi
-// CHECK: [0x6f,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, ttmp11
-// CHECK: [0x7b,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, m0
-// CHECK: [0x7c,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, exec_lo
-// CHECK: [0x7e,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, exec_hi
-// CHECK: [0x7f,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0
-// CHECK: [0x80,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, -1
-// CHECK: [0xc1,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0.5
-// CHECK: [0xf0,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, -4.0
-// CHECK: [0xf7,0x76,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0xaf123456
-// CHECK: [0xff,0x76,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbh_i32 v5, 0x3f717273
-// CHECK: [0xff,0x76,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbh_i32_e64 v5, v1
-// CHECK: [0x05,0x00,0x76,0xd3,0x01,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v255, v1
-// CHECK: [0xff,0x00,0x76,0xd3,0x01,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v5, v255
-// CHECK: [0x05,0x00,0x76,0xd3,0xff,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v5, s1
-// CHECK: [0x05,0x00,0x76,0xd3,0x01,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, s103
-// CHECK: [0x05,0x00,0x76,0xd3,0x67,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x76,0xd3,0x68,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x76,0xd3,0x69,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x76,0xd3,0x6a,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x76,0xd3,0x6b,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x76,0xd3,0x6c,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x76,0xd3,0x6d,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x76,0xd3,0x6e,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x76,0xd3,0x6f,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x76,0xd3,0x7b,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, m0
-// CHECK: [0x05,0x00,0x76,0xd3,0x7c,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x76,0xd3,0x7e,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x76,0xd3,0x7f,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, 0
-// CHECK: [0x05,0x00,0x76,0xd3,0x80,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, -1
-// CHECK: [0x05,0x00,0x76,0xd3,0xc1,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x76,0xd3,0xf0,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x76,0xd3,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64 v5, v[1:2]
-// CHECK: [0x01,0x79,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v255, v[1:2]
-// CHECK: [0x01,0x79,0xfe,0x7f]
-
-v_frexp_exp_i32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x79,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[2:3]
-// CHECK: [0x02,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[4:5]
-// CHECK: [0x04,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[102:103]
-// CHECK: [0x66,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, flat_scratch
-// CHECK: [0x68,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, vcc
-// CHECK: [0x6a,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, tba
-// CHECK: [0x6c,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, tma
-// CHECK: [0x6e,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, ttmp[10:11]
-// CHECK: [0x7a,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, exec
-// CHECK: [0x7e,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0
-// CHECK: [0x80,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, -1
-// CHECK: [0xc1,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0.5
-// CHECK: [0xf0,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, -4.0
-// CHECK: [0xf7,0x78,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x78,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_exp_i32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x78,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_exp_i32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x78,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x78,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x78,0xd3,0xfe,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x78,0xd3,0x02,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x78,0xd3,0x04,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[102:103]
-// CHECK: [0x05,0x00,0x78,0xd3,0x66,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x78,0xd3,0x68,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x78,0xd3,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, tba
-// CHECK: [0x05,0x00,0x78,0xd3,0x6c,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, tma
-// CHECK: [0x05,0x00,0x78,0xd3,0x6e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, ttmp[10:11]
-// CHECK: [0x05,0x00,0x78,0xd3,0x7a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x78,0xd3,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x78,0xd3,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x78,0xd3,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x78,0xd3,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x78,0xd3,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x78,0xd3,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x78,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x7b,0x0a,0x7e]
-
-v_frexp_mant_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x7b,0xfc,0x7f]
-
-v_frexp_mant_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x7b,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], vcc
-// CHECK: [0x6a,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], tba
-// CHECK: [0x6c,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], tma
-// CHECK: [0x6e,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], exec
-// CHECK: [0x7e,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0
-// CHECK: [0x80,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], -1
-// CHECK: [0xc1,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x7a,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x7a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_mant_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x7a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x7a,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x7a,0xd3,0xfe,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x7a,0xd3,0x02,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x7a,0xd3,0x04,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x7a,0xd3,0x66,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x7a,0xd3,0x68,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x7a,0xd3,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x7a,0xd3,0x6c,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x7a,0xd3,0x6e,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x7a,0xd3,0x7a,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x7a,0xd3,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x7a,0xd3,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x7a,0xd3,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x7a,0xd3,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x7a,0xd3,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x7a,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x7a,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x08]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x10]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x18]
-
-v_fract_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x7d,0x0a,0x7e]
-
-v_fract_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x7d,0xfc,0x7f]
-
-v_fract_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x7d,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[102:103]
-// CHECK: [0x66,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], flat_scratch
-// CHECK: [0x68,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], vcc
-// CHECK: [0x6a,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], tba
-// CHECK: [0x6c,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], tma
-// CHECK: [0x6e,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], exec
-// CHECK: [0x7e,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0
-// CHECK: [0x80,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], -1
-// CHECK: [0xc1,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x7c,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x7c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_fract_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x7c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_fract_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x7c,0xd3,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x7c,0xd3,0xfe,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x7c,0xd3,0x02,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x7c,0xd3,0x04,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[102:103]
-// CHECK: [0x05,0x00,0x7c,0xd3,0x66,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x7c,0xd3,0x68,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x7c,0xd3,0x6a,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x7c,0xd3,0x6c,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x7c,0xd3,0x6e,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x7c,0xd3,0x7a,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x7c,0xd3,0x7e,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x7c,0xd3,0x80,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x7c,0xd3,0xc1,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x7c,0xd3,0xf0,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x7c,0xd3,0xf7,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x20]
-
-v_fract_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x7c,0xd3,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x08,0x7c,0xd3,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x08]
-
-v_fract_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x10]
-
-v_fract_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x18]
-
-v_frexp_exp_i32_f32 v5, v1
-// CHECK: [0x01,0x7f,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v255, v1
-// CHECK: [0x01,0x7f,0xfe,0x7f]
-
-v_frexp_exp_i32_f32 v5, v255
-// CHECK: [0xff,0x7f,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, s1
-// CHECK: [0x01,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, s103
-// CHECK: [0x67,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, tba_lo
-// CHECK: [0x6c,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, tba_hi
-// CHECK: [0x6d,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, tma_lo
-// CHECK: [0x6e,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, tma_hi
-// CHECK: [0x6f,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, ttmp11
-// CHECK: [0x7b,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, m0
-// CHECK: [0x7c,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0
-// CHECK: [0x80,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, -1
-// CHECK: [0xc1,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x7e,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x7e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_exp_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x7e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_exp_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x7e,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x7e,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x7e,0xd3,0xff,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x7e,0xd3,0x01,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x7e,0xd3,0x67,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7e,0xd3,0x68,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7e,0xd3,0x69,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7e,0xd3,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7e,0xd3,0x6b,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x7e,0xd3,0x6c,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x7e,0xd3,0x6d,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x7e,0xd3,0x6e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x7e,0xd3,0x6f,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x7e,0xd3,0x7b,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x7e,0xd3,0x7c,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7e,0xd3,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7e,0xd3,0x7f,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x7e,0xd3,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x7e,0xd3,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7e,0xd3,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7e,0xd3,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f32 v5, v1
-// CHECK: [0x01,0x81,0x0a,0x7e]
-
-v_frexp_mant_f32 v255, v1
-// CHECK: [0x01,0x81,0xfe,0x7f]
-
-v_frexp_mant_f32 v5, v255
-// CHECK: [0xff,0x81,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, s1
-// CHECK: [0x01,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, s103
-// CHECK: [0x67,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, vcc_lo
-// CHECK: [0x6a,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, vcc_hi
-// CHECK: [0x6b,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, tba_lo
-// CHECK: [0x6c,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, tba_hi
-// CHECK: [0x6d,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, tma_lo
-// CHECK: [0x6e,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, tma_hi
-// CHECK: [0x6f,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, ttmp11
-// CHECK: [0x7b,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, m0
-// CHECK: [0x7c,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, exec_lo
-// CHECK: [0x7e,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, exec_hi
-// CHECK: [0x7f,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0
-// CHECK: [0x80,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, -1
-// CHECK: [0xc1,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0.5
-// CHECK: [0xf0,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, -4.0
-// CHECK: [0xf7,0x80,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0xaf123456
-// CHECK: [0xff,0x80,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_mant_f32 v5, 0x3f717273
-// CHECK: [0xff,0x80,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_mant_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x80,0xd3,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x80,0xd3,0xff,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x80,0xd3,0x67,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x80,0xd3,0x68,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x80,0xd3,0x69,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x80,0xd3,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x80,0xd3,0x6b,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x80,0xd3,0x6c,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x80,0xd3,0x6d,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x80,0xd3,0x6e,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x80,0xd3,0x6f,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x80,0xd3,0x7b,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x80,0xd3,0x7c,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x80,0xd3,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x80,0xd3,0x7f,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x80,0xd3,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x80,0xd3,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x80,0xd3,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x80,0xd3,0xf7,0x00,0x00,0x00]
-
-v_clrexcp
-// CHECK: [0x00,0x82,0x00,0x7e]
-
-v_clrexcp_e64
-// CHECK: [0x00,0x00,0x82,0xd3,0x00,0x00,0x00,0x00]
-
-v_movreld_b32 v5, v1
-// CHECK: [0x01,0x85,0x0a,0x7e]
-
-v_movreld_b32 v255, v1
-// CHECK: [0x01,0x85,0xfe,0x7f]
-
-v_movreld_b32 v5, v255
-// CHECK: [0xff,0x85,0x0a,0x7e]
-
-v_movreld_b32 v5, m0
-// CHECK: [0x7c,0x84,0x0a,0x7e]
-
-v_movreld_b32 v5, 0
-// CHECK: [0x80,0x84,0x0a,0x7e]
-
-v_movreld_b32 v5, -1
-// CHECK: [0xc1,0x84,0x0a,0x7e]
-
-v_movreld_b32 v5, 0.5
-// CHECK: [0xf0,0x84,0x0a,0x7e]
-
-v_movreld_b32 v5, -4.0
-// CHECK: [0xf7,0x84,0x0a,0x7e]
-
-v_movreld_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x01,0x00,0x00]
-
-v_movreld_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x84,0xd3,0x01,0x01,0x00,0x00]
-
-v_movreld_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x84,0xd3,0xff,0x01,0x00,0x00]
-
-v_movreld_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x84,0xd3,0x7c,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x84,0xd3,0x80,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x84,0xd3,0xc1,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x84,0xd3,0xf0,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x84,0xd3,0xf7,0x00,0x00,0x00]
-
-v_movrels_b32 v5, v1
-// CHECK: [0x01,0x87,0x0a,0x7e]
-
-v_movrels_b32 v255, v1
-// CHECK: [0x01,0x87,0xfe,0x7f]
-
-v_movrels_b32 v5, v255
-// CHECK: [0xff,0x87,0x0a,0x7e]
-
-v_movrels_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x01,0x00,0x00]
-
-v_movrels_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x86,0xd3,0x01,0x01,0x00,0x00]
-
-v_movrels_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x86,0xd3,0xff,0x01,0x00,0x00]
-
-v_movrelsd_b32 v5, v1
-// CHECK: [0x01,0x89,0x0a,0x7e]
-
-v_movrelsd_b32 v255, v1
-// CHECK: [0x01,0x89,0xfe,0x7f]
-
-v_movrelsd_b32 v5, v255
-// CHECK: [0xff,0x89,0x0a,0x7e]
-
-v_movrelsd_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x01,0x00,0x00]
-
-v_movrelsd_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x88,0xd3,0x01,0x01,0x00,0x00]
-
-v_movrelsd_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x88,0xd3,0xff,0x01,0x00,0x00]
-
-v_log_legacy_f32 v5, v1
-// CHECK: [0x01,0x8b,0x0a,0x7e]
-
-v_log_legacy_f32 v255, v1
-// CHECK: [0x01,0x8b,0xfe,0x7f]
-
-v_log_legacy_f32 v5, v255
-// CHECK: [0xff,0x8b,0x0a,0x7e]
-
-v_log_legacy_f32 v5, s1
-// CHECK: [0x01,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, s103
-// CHECK: [0x67,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, vcc_lo
-// CHECK: [0x6a,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, vcc_hi
-// CHECK: [0x6b,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, tba_lo
-// CHECK: [0x6c,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, tba_hi
-// CHECK: [0x6d,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, tma_lo
-// CHECK: [0x6e,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, tma_hi
-// CHECK: [0x6f,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, ttmp11
-// CHECK: [0x7b,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, m0
-// CHECK: [0x7c,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, exec_lo
-// CHECK: [0x7e,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, exec_hi
-// CHECK: [0x7f,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, 0
-// CHECK: [0x80,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, -1
-// CHECK: [0xc1,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, 0.5
-// CHECK: [0xf0,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, -4.0
-// CHECK: [0xf7,0x8a,0x0a,0x7e]
-
-v_log_legacy_f32 v5, 0xaf123456
-// CHECK: [0xff,0x8a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_log_legacy_f32 v5, 0x3f717273
-// CHECK: [0xff,0x8a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_log_legacy_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x8a,0xd3,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x8a,0xd3,0xff,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x8a,0xd3,0x67,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8a,0xd3,0x68,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8a,0xd3,0x69,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x8a,0xd3,0x6a,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x8a,0xd3,0x6b,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x8a,0xd3,0x6c,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x8a,0xd3,0x6d,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x8a,0xd3,0x6e,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x8a,0xd3,0x6f,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x8a,0xd3,0x7b,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x8a,0xd3,0x7c,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x8a,0xd3,0x7e,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x8a,0xd3,0x7f,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x8a,0xd3,0x80,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x8a,0xd3,0xc1,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x8a,0xd3,0xf0,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x8a,0xd3,0xf7,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x20]
-
-v_log_legacy_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x8a,0xd3,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x8a,0xd3,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x08]
-
-v_log_legacy_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x10]
-
-v_log_legacy_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x18]
-
-v_exp_legacy_f32 v5, v1
-// CHECK: [0x01,0x8d,0x0a,0x7e]
-
-v_exp_legacy_f32 v255, v1
-// CHECK: [0x01,0x8d,0xfe,0x7f]
-
-v_exp_legacy_f32 v5, v255
-// CHECK: [0xff,0x8d,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, s1
-// CHECK: [0x01,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, s103
-// CHECK: [0x67,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, flat_scratch_lo
-// CHECK: [0x68,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, flat_scratch_hi
-// CHECK: [0x69,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, vcc_lo
-// CHECK: [0x6a,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, vcc_hi
-// CHECK: [0x6b,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, tba_lo
-// CHECK: [0x6c,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, tba_hi
-// CHECK: [0x6d,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, tma_lo
-// CHECK: [0x6e,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, tma_hi
-// CHECK: [0x6f,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, ttmp11
-// CHECK: [0x7b,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, m0
-// CHECK: [0x7c,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, exec_lo
-// CHECK: [0x7e,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, exec_hi
-// CHECK: [0x7f,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, 0
-// CHECK: [0x80,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, -1
-// CHECK: [0xc1,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, 0.5
-// CHECK: [0xf0,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, -4.0
-// CHECK: [0xf7,0x8c,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, 0xaf123456
-// CHECK: [0xff,0x8c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_exp_legacy_f32 v5, 0x3f717273
-// CHECK: [0xff,0x8c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_exp_legacy_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x8c,0xd3,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x8c,0xd3,0xff,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, s103
-// CHECK: [0x05,0x00,0x8c,0xd3,0x67,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8c,0xd3,0x68,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8c,0xd3,0x69,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x8c,0xd3,0x6a,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x8c,0xd3,0x6b,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x8c,0xd3,0x6c,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x8c,0xd3,0x6d,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x8c,0xd3,0x6e,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x8c,0xd3,0x6f,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x8c,0xd3,0x7b,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x8c,0xd3,0x7c,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x8c,0xd3,0x7e,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x8c,0xd3,0x7f,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x8c,0xd3,0x80,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x8c,0xd3,0xc1,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x8c,0xd3,0xf0,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x8c,0xd3,0xf7,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x20]
-
-v_exp_legacy_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x8c,0xd3,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x08,0x8c,0xd3,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x08]
-
-v_exp_legacy_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x10]
-
-v_exp_legacy_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x18]
-
-v_cndmask_b32 v5, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x00]
-
-v_cndmask_b32 v255, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x01]
-
-v_cndmask_b32 v5, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x00]
-
-v_cndmask_b32 v5, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x00]
-
-v_cndmask_b32_e64 v5, v1, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x1a,0x00]
-
-v_cndmask_b32_e64 v255, v1, v2, s[6:7]
-// CHECK: [0xff,0x00,0x00,0xd2,0x01,0x05,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, v255, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0xff,0x05,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, 0, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0x80,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, -1, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0xc1,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, 0.5, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0xf0,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, -4.0, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0xf7,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, v1, v255, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xff,0x1b,0x00]
-
-v_cndmask_b32_e64 v5, v1, 0, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x01,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, -1, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x83,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, 0.5, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xe1,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, -4.0, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xef,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, v2, s[8:9]
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x22,0x00]
-
-v_cndmask_b32_e64 v5, v1, v2, s[102:103]
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x9a,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, flat_scratch
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xa2,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, vcc
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xaa,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, tba
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xb2,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, tma
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xba,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xea,0x01]
-
-v_readlane_b32 s5, v1, s2
-// CHECK: [0x01,0x05,0x0a,0x02]
-
-v_readlane_b32 s103, v1, s2
-// CHECK: [0x01,0x05,0xce,0x02]
-
-v_readlane_b32 tba_lo, v1, s2
-// CHECK: [0x01,0x05,0xd8,0x02]
-
-v_readlane_b32 tba_hi, v1, s2
-// CHECK: [0x01,0x05,0xda,0x02]
-
-v_readlane_b32 tma_lo, v1, s2
-// CHECK: [0x01,0x05,0xdc,0x02]
-
-v_readlane_b32 tma_hi, v1, s2
-// CHECK: [0x01,0x05,0xde,0x02]
-
-v_readlane_b32 ttmp11, v1, s2
-// CHECK: [0x01,0x05,0xf6,0x02]
-
-v_readlane_b32 s5, v255, s2
-// CHECK: [0xff,0x05,0x0a,0x02]
-
-v_readlane_b32 s5, v1, s103
-// CHECK: [0x01,0xcf,0x0a,0x02]
-
-v_readlane_b32 s5, v1, flat_scratch_lo
-// CHECK: [0x01,0xd1,0x0a,0x02]
-
-v_readlane_b32 s5, v1, flat_scratch_hi
-// CHECK: [0x01,0xd3,0x0a,0x02]
-
-v_readlane_b32 s5, v1, vcc_lo
-// CHECK: [0x01,0xd5,0x0a,0x02]
-
-v_readlane_b32 s5, v1, vcc_hi
-// CHECK: [0x01,0xd7,0x0a,0x02]
-
-v_readlane_b32 s5, v1, tba_lo
-// CHECK: [0x01,0xd9,0x0a,0x02]
-
-v_readlane_b32 s5, v1, tba_hi
-// CHECK: [0x01,0xdb,0x0a,0x02]
-
-v_readlane_b32 s5, v1, tma_lo
-// CHECK: [0x01,0xdd,0x0a,0x02]
-
-v_readlane_b32 s5, v1, tma_hi
-// CHECK: [0x01,0xdf,0x0a,0x02]
-
-v_readlane_b32 s5, v1, ttmp11
-// CHECK: [0x01,0xf7,0x0a,0x02]
-
-v_readlane_b32 s5, v1, m0
-// CHECK: [0x01,0xf9,0x0a,0x02]
-
-v_readlane_b32 s5, v1, 0
-// CHECK: [0x01,0x01,0x0b,0x02]
-
-v_writelane_b32 v5, 0, s2
-// CHECK: [0x80,0x04,0x0a,0x04]
-
-v_writelane_b32 v255, 0, s2
-// CHECK: [0x80,0x04,0xfe,0x05]
-
-v_writelane_b32 v5, -1, s2
-// CHECK: [0xc1,0x04,0x0a,0x04]
-
-v_writelane_b32 v5, 0.5, s2
-// CHECK: [0xf0,0x04,0x0a,0x04]
-
-v_writelane_b32 v5, -4.0, s2
-// CHECK: [0xf7,0x04,0x0a,0x04]
-
-v_writelane_b32 v5, 0, s103
-// CHECK: [0x80,0xce,0x0a,0x04]
-
-v_writelane_b32 v5, 0, flat_scratch_lo
-// CHECK: [0x80,0xd0,0x0a,0x04]
-
-v_writelane_b32 v5, 0, flat_scratch_hi
-// CHECK: [0x80,0xd2,0x0a,0x04]
-
-v_writelane_b32 v5, 0, vcc_lo
-// CHECK: [0x80,0xd4,0x0a,0x04]
-
-v_writelane_b32 v5, 0, vcc_hi
-// CHECK: [0x80,0xd6,0x0a,0x04]
-
-v_writelane_b32 v5, 0, tba_lo
-// CHECK: [0x80,0xd8,0x0a,0x04]
-
-v_writelane_b32 v5, 0, tba_hi
-// CHECK: [0x80,0xda,0x0a,0x04]
-
-v_writelane_b32 v5, 0, tma_lo
-// CHECK: [0x80,0xdc,0x0a,0x04]
-
-v_writelane_b32 v5, 0, tma_hi
-// CHECK: [0x80,0xde,0x0a,0x04]
-
-v_writelane_b32 v5, 0, ttmp11
-// CHECK: [0x80,0xf6,0x0a,0x04]
-
-v_writelane_b32 v5, 0, m0
-// CHECK: [0x80,0xf8,0x0a,0x04]
-
-v_writelane_b32 v5, 0, 0
-// CHECK: [0x80,0x00,0x0b,0x04]
-
-v_add_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x06]
-
-v_add_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x07]
-
-v_add_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x06]
-
-v_add_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x06]
-
-v_add_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x06]
-
-v_add_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x06]
-
-v_add_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x06]
-
-v_add_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x06]
-
-v_add_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x06]
-
-v_add_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x06]
-
-v_add_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x06]
-
-v_add_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x06]
-
-v_add_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x06]
-
-v_add_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x06]
-
-v_add_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x06]
-
-v_add_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x06]
-
-v_add_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x06]
-
-v_add_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x06]
-
-v_add_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x06]
-
-v_add_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x06]
-
-v_add_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x06]
-
-v_add_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x06,0x56,0x34,0x12,0xaf]
-
-v_add_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x06,0x73,0x72,0x71,0x3f]
-
-v_add_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x06]
-
-v_add_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x06,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0xff,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x67,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x68,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x69,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x6a,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x6b,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x6c,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x6d,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x6e,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x6f,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x7b,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x7c,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x7e,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x7f,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x80,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0xc1,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0xf0,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0xf7,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xff,0x03,0x00]
-
-v_add_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x00,0x00]
-
-v_add_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xcf,0x00,0x00]
-
-v_add_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd1,0x00,0x00]
-
-v_add_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd3,0x00,0x00]
-
-v_add_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd5,0x00,0x00]
-
-v_add_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd7,0x00,0x00]
-
-v_add_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd9,0x00,0x00]
-
-v_add_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xdb,0x00,0x00]
-
-v_add_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xdd,0x00,0x00]
-
-v_add_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xdf,0x00,0x00]
-
-v_add_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf7,0x00,0x00]
-
-v_add_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf9,0x00,0x00]
-
-v_add_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xfd,0x00,0x00]
-
-v_add_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xff,0x00,0x00]
-
-v_add_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x01,0x01,0x00]
-
-v_add_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x83,0x01,0x00]
-
-v_add_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xe1,0x01,0x00]
-
-v_add_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xef,0x01,0x00]
-
-v_add_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x20]
-
-v_add_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x40]
-
-v_add_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x60]
-
-v_add_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x06,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x06,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x06,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x06,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x08]
-
-v_add_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x10]
-
-v_add_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x18]
-
-v_sub_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x08]
-
-v_sub_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x09]
-
-v_sub_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x08]
-
-v_sub_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x08]
-
-v_sub_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x08]
-
-v_sub_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x08]
-
-v_sub_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x08]
-
-v_sub_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x08]
-
-v_sub_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x08]
-
-v_sub_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x08]
-
-v_sub_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x08]
-
-v_sub_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x08]
-
-v_sub_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x08]
-
-v_sub_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x08]
-
-v_sub_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x08]
-
-v_sub_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x08]
-
-v_sub_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x08]
-
-v_sub_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x08]
-
-v_sub_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x08]
-
-v_sub_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x08]
-
-v_sub_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x08]
-
-v_sub_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x08,0x56,0x34,0x12,0xaf]
-
-v_sub_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x08,0x73,0x72,0x71,0x3f]
-
-v_sub_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x08]
-
-v_sub_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x08,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0xff,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x67,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x68,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x69,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x6a,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x6b,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x6c,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x6d,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x6e,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x6f,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x7b,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x7c,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x7e,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x7f,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x80,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0xc1,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0xf0,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0xf7,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xff,0x03,0x00]
-
-v_sub_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xcf,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd1,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd3,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd5,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd7,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd9,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xdb,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xdd,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xdf,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xf7,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xf9,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xfd,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xff,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x01,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x83,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xe1,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xef,0x01,0x00]
-
-v_sub_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x20]
-
-v_sub_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x40]
-
-v_sub_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x60]
-
-v_sub_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x08,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x08,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x08,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x08,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x08]
-
-v_sub_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x10]
-
-v_sub_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x18]
-
-v_subrev_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x0a]
-
-v_subrev_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x0b]
-
-v_subrev_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x0a]
-
-v_subrev_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x0a]
-
-v_subrev_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x0a,0x56,0x34,0x12,0xaf]
-
-v_subrev_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x0a,0x73,0x72,0x71,0x3f]
-
-v_subrev_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x0a]
-
-v_subrev_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0a,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0xff,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x67,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x68,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x69,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x6a,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x6b,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x6c,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x6d,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x6e,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x6f,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x7b,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x7c,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x7e,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x7f,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x80,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0xc1,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0xf0,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0xf7,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xff,0x03,0x00]
-
-v_subrev_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xcf,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd1,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd3,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd5,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd7,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd9,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xdb,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xdd,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xdf,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xf7,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xf9,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xfd,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xff,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x01,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x83,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xe1,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xef,0x01,0x00]
-
-v_subrev_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x20]
-
-v_subrev_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x40]
-
-v_subrev_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x60]
-
-v_subrev_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x0a,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x0a,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x0a,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x0a,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x08]
-
-v_subrev_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x10]
-
-v_subrev_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x18]
-
-v_mac_legacy_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x0c]
-
-v_mac_legacy_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x0d]
-
-v_mac_legacy_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x0c]
-
-v_mac_legacy_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x0c,0x56,0x34,0x12,0xaf]
-
-v_mac_legacy_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x0c,0x73,0x72,0x71,0x3f]
-
-v_mac_legacy_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x0c]
-
-v_mac_legacy_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0xff,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x67,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x68,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x69,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x80,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xff,0x03,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xff,0x00,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x01,0x01,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x83,0x01,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xef,0x01,0x00]
-
-v_mac_legacy_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x20]
-
-v_mac_legacy_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x40]
-
-v_mac_legacy_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x60]
-
-v_mac_legacy_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x0c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x0c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x0c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x0c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_legacy_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x08]
-
-v_mac_legacy_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x10]
-
-v_mac_legacy_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x18]
-
-v_mul_legacy_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x0e]
-
-v_mul_legacy_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x0f]
-
-v_mul_legacy_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x0e]
-
-v_mul_legacy_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x0e,0x56,0x34,0x12,0xaf]
-
-v_mul_legacy_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x0e,0x73,0x72,0x71,0x3f]
-
-v_mul_legacy_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x0e]
-
-v_mul_legacy_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x20]
-
-v_mul_legacy_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x40]
-
-v_mul_legacy_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x60]
-
-v_mul_legacy_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x0e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x0e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x0e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x0e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x08]
-
-v_mul_legacy_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x10]
-
-v_mul_legacy_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x18]
-
-v_mul_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x10]
-
-v_mul_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x11]
-
-v_mul_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x10]
-
-v_mul_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x10]
-
-v_mul_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x10]
-
-v_mul_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x10]
-
-v_mul_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x10]
-
-v_mul_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x10]
-
-v_mul_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x10]
-
-v_mul_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x10]
-
-v_mul_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x10]
-
-v_mul_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x10]
-
-v_mul_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x10]
-
-v_mul_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x10]
-
-v_mul_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x10]
-
-v_mul_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x10]
-
-v_mul_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x10]
-
-v_mul_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x10]
-
-v_mul_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x10]
-
-v_mul_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x10]
-
-v_mul_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x10]
-
-v_mul_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x10,0x56,0x34,0x12,0xaf]
-
-v_mul_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x10,0x73,0x72,0x71,0x3f]
-
-v_mul_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x10]
-
-v_mul_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x10,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x20]
-
-v_mul_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x40]
-
-v_mul_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x60]
-
-v_mul_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x10,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x10,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x10,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x10,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x08]
-
-v_mul_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x10]
-
-v_mul_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x18]
-
-v_mul_i32_i24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x12]
-
-v_mul_i32_i24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x13]
-
-v_mul_i32_i24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x12]
-
-v_mul_i32_i24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x12]
-
-v_mul_i32_i24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0xaf]
-
-v_mul_i32_i24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x3f]
-
-v_mul_i32_i24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x12]
-
-v_mul_i32_i24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x12,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x12,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_i32_i24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_hi_i32_i24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x14]
-
-v_mul_hi_i32_i24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x15]
-
-v_mul_hi_i32_i24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x14]
-
-v_mul_hi_i32_i24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x14,0x56,0x34,0x12,0xaf]
-
-v_mul_hi_i32_i24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x14,0x73,0x72,0x71,0x3f]
-
-v_mul_hi_i32_i24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x14]
-
-v_mul_hi_i32_i24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x14,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x14,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_u32_u24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x16]
-
-v_mul_u32_u24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x17]
-
-v_mul_u32_u24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x16]
-
-v_mul_u32_u24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x16]
-
-v_mul_u32_u24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x16,0x56,0x34,0x12,0xaf]
-
-v_mul_u32_u24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x16,0x73,0x72,0x71,0x3f]
-
-v_mul_u32_u24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x16]
-
-v_mul_u32_u24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x16,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x16,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_u32_u24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_hi_u32_u24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x18]
-
-v_mul_hi_u32_u24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x19]
-
-v_mul_hi_u32_u24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x18]
-
-v_mul_hi_u32_u24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x18,0x56,0x34,0x12,0xaf]
-
-v_mul_hi_u32_u24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x18,0x73,0x72,0x71,0x3f]
-
-v_mul_hi_u32_u24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x18]
-
-v_mul_hi_u32_u24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x18,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x18,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xef,0x01,0x00]
-
-v_min_legacy_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x1a]
-
-v_min_legacy_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x1b]
-
-v_min_legacy_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x1a]
-
-v_min_legacy_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x1a]
-
-v_min_legacy_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x1a,0x56,0x34,0x12,0xaf]
-
-v_min_legacy_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x1a,0x73,0x72,0x71,0x3f]
-
-v_min_legacy_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x1a]
-
-v_min_legacy_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_legacy_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x1a,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0xff,0x05,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x67,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x68,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x69,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x6a,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x6b,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x6c,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x6d,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x6e,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x6f,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x7b,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x7c,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x7e,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x7f,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x80,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0xc1,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0xf0,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0xf7,0x04,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xff,0x03,0x00]
-
-v_min_legacy_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xcf,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd1,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd3,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd5,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd7,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd9,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xdb,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xdd,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xdf,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xf7,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xf9,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xfd,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xff,0x00,0x00]
-
-v_min_legacy_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x01,0x01,0x00]
-
-v_min_legacy_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x83,0x01,0x00]
-
-v_min_legacy_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xe1,0x01,0x00]
-
-v_min_legacy_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xef,0x01,0x00]
-
-v_min_legacy_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x20]
-
-v_min_legacy_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x40]
-
-v_min_legacy_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x60]
-
-v_min_legacy_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x1a,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x1a,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x1a,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x1a,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_legacy_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x08]
-
-v_min_legacy_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x10]
-
-v_min_legacy_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x18]
-
-v_max_legacy_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x1c]
-
-v_max_legacy_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x1d]
-
-v_max_legacy_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x1c]
-
-v_max_legacy_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x1c]
-
-v_max_legacy_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x1c,0x56,0x34,0x12,0xaf]
-
-v_max_legacy_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x1c,0x73,0x72,0x71,0x3f]
-
-v_max_legacy_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x1c]
-
-v_max_legacy_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_legacy_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x1c,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0xff,0x05,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x67,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x68,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x69,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x6a,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x6b,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x6c,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x6d,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x6e,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x6f,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x7b,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x7c,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x7e,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x7f,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x80,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0xc1,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0xf0,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0xf7,0x04,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xff,0x03,0x00]
-
-v_max_legacy_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xcf,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd1,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd3,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd5,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd7,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd9,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xdb,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xdd,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xdf,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xf7,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xf9,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xfd,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xff,0x00,0x00]
-
-v_max_legacy_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x01,0x01,0x00]
-
-v_max_legacy_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x83,0x01,0x00]
-
-v_max_legacy_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xe1,0x01,0x00]
-
-v_max_legacy_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xef,0x01,0x00]
-
-v_max_legacy_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x20]
-
-v_max_legacy_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x40]
-
-v_max_legacy_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x60]
-
-v_max_legacy_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x1c,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x1c,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x1c,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x1c,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_legacy_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x08]
-
-v_max_legacy_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x10]
-
-v_max_legacy_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x18]
-
-v_min_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x1e]
-
-v_min_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x1f]
-
-v_min_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x1e]
-
-v_min_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x1e]
-
-v_min_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x1e]
-
-v_min_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x1e]
-
-v_min_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x1e]
-
-v_min_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x1e]
-
-v_min_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x1e]
-
-v_min_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x1e]
-
-v_min_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x1e]
-
-v_min_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x1e]
-
-v_min_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x1e]
-
-v_min_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x1e]
-
-v_min_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x1e]
-
-v_min_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x1e]
-
-v_min_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x1e]
-
-v_min_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x1e]
-
-v_min_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x1e]
-
-v_min_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x1e]
-
-v_min_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x1e]
-
-v_min_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x1e,0x56,0x34,0x12,0xaf]
-
-v_min_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x1e,0x73,0x72,0x71,0x3f]
-
-v_min_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x1e]
-
-v_min_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x1e,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0xff,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x67,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x68,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x69,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x6a,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x6b,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x6c,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x6d,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x6e,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x6f,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x7b,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x7c,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x7e,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x7f,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x80,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0xc1,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0xf0,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0xf7,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xff,0x03,0x00]
-
-v_min_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x00,0x00]
-
-v_min_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xcf,0x00,0x00]
-
-v_min_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd1,0x00,0x00]
-
-v_min_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd3,0x00,0x00]
-
-v_min_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd5,0x00,0x00]
-
-v_min_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd7,0x00,0x00]
-
-v_min_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd9,0x00,0x00]
-
-v_min_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xdb,0x00,0x00]
-
-v_min_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xdd,0x00,0x00]
-
-v_min_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xdf,0x00,0x00]
-
-v_min_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xf7,0x00,0x00]
-
-v_min_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xf9,0x00,0x00]
-
-v_min_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xfd,0x00,0x00]
-
-v_min_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xff,0x00,0x00]
-
-v_min_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x01,0x01,0x00]
-
-v_min_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x83,0x01,0x00]
-
-v_min_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xe1,0x01,0x00]
-
-v_min_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xef,0x01,0x00]
-
-v_min_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x20]
-
-v_min_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x40]
-
-v_min_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x60]
-
-v_min_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x1e,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x1e,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x1e,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x1e,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x08]
-
-v_min_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x10]
-
-v_min_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x18]
-
-v_max_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x20]
-
-v_max_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x21]
-
-v_max_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x20]
-
-v_max_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x20]
-
-v_max_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x20]
-
-v_max_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x20]
-
-v_max_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x20]
-
-v_max_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x20]
-
-v_max_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x20]
-
-v_max_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x20]
-
-v_max_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x20]
-
-v_max_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x20]
-
-v_max_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x20]
-
-v_max_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x20]
-
-v_max_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x20]
-
-v_max_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x20]
-
-v_max_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x20]
-
-v_max_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x20]
-
-v_max_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x20]
-
-v_max_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x20]
-
-v_max_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x20]
-
-v_max_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x20,0x56,0x34,0x12,0xaf]
-
-v_max_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x20,0x73,0x72,0x71,0x3f]
-
-v_max_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x20]
-
-v_max_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x20,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0xff,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x67,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x68,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x69,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x6a,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x6b,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x6c,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x6d,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x6e,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x6f,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x7b,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x7c,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x7e,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x7f,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x80,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0xc1,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0xf0,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0xf7,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xff,0x03,0x00]
-
-v_max_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x00,0x00]
-
-v_max_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xcf,0x00,0x00]
-
-v_max_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd1,0x00,0x00]
-
-v_max_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd3,0x00,0x00]
-
-v_max_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd5,0x00,0x00]
-
-v_max_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd7,0x00,0x00]
-
-v_max_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd9,0x00,0x00]
-
-v_max_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xdb,0x00,0x00]
-
-v_max_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xdd,0x00,0x00]
-
-v_max_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xdf,0x00,0x00]
-
-v_max_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xf7,0x00,0x00]
-
-v_max_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xf9,0x00,0x00]
-
-v_max_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xfd,0x00,0x00]
-
-v_max_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xff,0x00,0x00]
-
-v_max_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x01,0x01,0x00]
-
-v_max_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x83,0x01,0x00]
-
-v_max_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xe1,0x01,0x00]
-
-v_max_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xef,0x01,0x00]
-
-v_max_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x20]
-
-v_max_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x40]
-
-v_max_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x60]
-
-v_max_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x20,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x20,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x20,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x20,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x08]
-
-v_max_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x10]
-
-v_max_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x18]
-
-v_min_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x22]
-
-v_min_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x23]
-
-v_min_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x22]
-
-v_min_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x22]
-
-v_min_i32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x22]
-
-v_min_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x22]
-
-v_min_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x22]
-
-v_min_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x22]
-
-v_min_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x22]
-
-v_min_i32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x22]
-
-v_min_i32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x22]
-
-v_min_i32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x22]
-
-v_min_i32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x22]
-
-v_min_i32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x22]
-
-v_min_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x22]
-
-v_min_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x22]
-
-v_min_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x22]
-
-v_min_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x22]
-
-v_min_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x22]
-
-v_min_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x22]
-
-v_min_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x22]
-
-v_min_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x22,0x56,0x34,0x12,0xaf]
-
-v_min_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x22,0x73,0x72,0x71,0x3f]
-
-v_min_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x22]
-
-v_min_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x22,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0xff,0x05,0x02,0x00]
-
-v_min_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x67,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x68,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x69,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x6a,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x6b,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x6c,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x6d,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x6e,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x6f,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x7b,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x7c,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x7e,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x7f,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0x80,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0xc1,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0xf0,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x22,0xd2,0xf7,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xff,0x03,0x00]
-
-v_min_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x05,0x00,0x00]
-
-v_min_i32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xcf,0x00,0x00]
-
-v_min_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd1,0x00,0x00]
-
-v_min_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd3,0x00,0x00]
-
-v_min_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd5,0x00,0x00]
-
-v_min_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd7,0x00,0x00]
-
-v_min_i32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd9,0x00,0x00]
-
-v_min_i32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xdb,0x00,0x00]
-
-v_min_i32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xdd,0x00,0x00]
-
-v_min_i32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xdf,0x00,0x00]
-
-v_min_i32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xf7,0x00,0x00]
-
-v_min_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xf9,0x00,0x00]
-
-v_min_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xfd,0x00,0x00]
-
-v_min_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xff,0x00,0x00]
-
-v_min_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x01,0x01,0x00]
-
-v_min_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x83,0x01,0x00]
-
-v_min_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xe1,0x01,0x00]
-
-v_min_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xef,0x01,0x00]
-
-v_max_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x24]
-
-v_max_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x25]
-
-v_max_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x24]
-
-v_max_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x24]
-
-v_max_i32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x24]
-
-v_max_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x24]
-
-v_max_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x24]
-
-v_max_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x24]
-
-v_max_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x24]
-
-v_max_i32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x24]
-
-v_max_i32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x24]
-
-v_max_i32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x24]
-
-v_max_i32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x24]
-
-v_max_i32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x24]
-
-v_max_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x24]
-
-v_max_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x24]
-
-v_max_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x24]
-
-v_max_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x24]
-
-v_max_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x24]
-
-v_max_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x24]
-
-v_max_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x24]
-
-v_max_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x24,0x56,0x34,0x12,0xaf]
-
-v_max_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x24,0x73,0x72,0x71,0x3f]
-
-v_max_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x24]
-
-v_max_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x24,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0xff,0x05,0x02,0x00]
-
-v_max_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x67,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x68,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x69,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x6a,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x6b,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x6c,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x6d,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x6e,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x6f,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x7b,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x7c,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x7e,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x7f,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0x80,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0xc1,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0xf0,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x24,0xd2,0xf7,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xff,0x03,0x00]
-
-v_max_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x05,0x00,0x00]
-
-v_max_i32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xcf,0x00,0x00]
-
-v_max_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd1,0x00,0x00]
-
-v_max_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd3,0x00,0x00]
-
-v_max_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd5,0x00,0x00]
-
-v_max_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd7,0x00,0x00]
-
-v_max_i32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd9,0x00,0x00]
-
-v_max_i32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xdb,0x00,0x00]
-
-v_max_i32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xdd,0x00,0x00]
-
-v_max_i32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xdf,0x00,0x00]
-
-v_max_i32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xf7,0x00,0x00]
-
-v_max_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xf9,0x00,0x00]
-
-v_max_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xfd,0x00,0x00]
-
-v_max_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xff,0x00,0x00]
-
-v_max_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x01,0x01,0x00]
-
-v_max_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x83,0x01,0x00]
-
-v_max_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xe1,0x01,0x00]
-
-v_max_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xef,0x01,0x00]
-
-v_min_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x26]
-
-v_min_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x27]
-
-v_min_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x26]
-
-v_min_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x26]
-
-v_min_u32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x26]
-
-v_min_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x26]
-
-v_min_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x26]
-
-v_min_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x26]
-
-v_min_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x26]
-
-v_min_u32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x26]
-
-v_min_u32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x26]
-
-v_min_u32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x26]
-
-v_min_u32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x26]
-
-v_min_u32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x26]
-
-v_min_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x26]
-
-v_min_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x26]
-
-v_min_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x26]
-
-v_min_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x26]
-
-v_min_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x26]
-
-v_min_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x26]
-
-v_min_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x26]
-
-v_min_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x26,0x56,0x34,0x12,0xaf]
-
-v_min_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x26,0x73,0x72,0x71,0x3f]
-
-v_min_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x26]
-
-v_min_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x26,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0xff,0x05,0x02,0x00]
-
-v_min_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x67,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x68,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x69,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x6a,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x6b,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x6c,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x6d,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x6e,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x6f,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x7b,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x7c,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x7e,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x7f,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0x80,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0xc1,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0xf0,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x26,0xd2,0xf7,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xff,0x03,0x00]
-
-v_min_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x05,0x00,0x00]
-
-v_min_u32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xcf,0x00,0x00]
-
-v_min_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd1,0x00,0x00]
-
-v_min_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd3,0x00,0x00]
-
-v_min_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd5,0x00,0x00]
-
-v_min_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd7,0x00,0x00]
-
-v_min_u32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd9,0x00,0x00]
-
-v_min_u32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xdb,0x00,0x00]
-
-v_min_u32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xdd,0x00,0x00]
-
-v_min_u32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xdf,0x00,0x00]
-
-v_min_u32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xf7,0x00,0x00]
-
-v_min_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xf9,0x00,0x00]
-
-v_min_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xfd,0x00,0x00]
-
-v_min_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xff,0x00,0x00]
-
-v_min_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x01,0x01,0x00]
-
-v_min_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x83,0x01,0x00]
-
-v_min_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xe1,0x01,0x00]
-
-v_min_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xef,0x01,0x00]
-
-v_max_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x28]
-
-v_max_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x29]
-
-v_max_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x28]
-
-v_max_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x28]
-
-v_max_u32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x28]
-
-v_max_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x28]
-
-v_max_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x28]
-
-v_max_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x28]
-
-v_max_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x28]
-
-v_max_u32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x28]
-
-v_max_u32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x28]
-
-v_max_u32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x28]
-
-v_max_u32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x28]
-
-v_max_u32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x28]
-
-v_max_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x28]
-
-v_max_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x28]
-
-v_max_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x28]
-
-v_max_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x28]
-
-v_max_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x28]
-
-v_max_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x28]
-
-v_max_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x28]
-
-v_max_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x28,0x56,0x34,0x12,0xaf]
-
-v_max_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x28,0x73,0x72,0x71,0x3f]
-
-v_max_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x28]
-
-v_max_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x28,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0xff,0x05,0x02,0x00]
-
-v_max_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x67,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x68,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x69,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x6a,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x6b,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x6c,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x6d,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x6e,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x6f,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x7b,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x7c,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x7e,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x7f,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0x80,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0xc1,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0xf0,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x28,0xd2,0xf7,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xff,0x03,0x00]
-
-v_max_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x05,0x00,0x00]
-
-v_max_u32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xcf,0x00,0x00]
-
-v_max_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd1,0x00,0x00]
-
-v_max_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd3,0x00,0x00]
-
-v_max_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd5,0x00,0x00]
-
-v_max_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd7,0x00,0x00]
-
-v_max_u32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd9,0x00,0x00]
-
-v_max_u32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xdb,0x00,0x00]
-
-v_max_u32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xdd,0x00,0x00]
-
-v_max_u32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xdf,0x00,0x00]
-
-v_max_u32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xf7,0x00,0x00]
-
-v_max_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xf9,0x00,0x00]
-
-v_max_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xfd,0x00,0x00]
-
-v_max_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xff,0x00,0x00]
-
-v_max_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x01,0x01,0x00]
-
-v_max_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x83,0x01,0x00]
-
-v_max_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xe1,0x01,0x00]
-
-v_max_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xef,0x01,0x00]
-
-v_lshr_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x2a]
-
-v_lshr_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x2b]
-
-v_lshr_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x2a]
-
-v_lshr_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x2a]
-
-v_lshr_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x2a,0x56,0x34,0x12,0xaf]
-
-v_lshr_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x2a,0x73,0x72,0x71,0x3f]
-
-v_lshr_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x2a]
-
-v_lshr_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshr_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2a,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshr_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0xff,0x05,0x02,0x00]
-
-v_lshr_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x67,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x68,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x69,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x6b,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x6c,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x6d,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x6e,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x6f,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x7b,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x7c,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x7f,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x2a,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshr_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xff,0x03,0x00]
-
-v_lshr_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x05,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xcf,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd1,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd3,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd7,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd9,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xdb,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xdd,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xdf,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xf7,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xf9,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xff,0x00,0x00]
-
-v_lshr_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshr_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshr_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshr_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xef,0x01,0x00]
-
-v_lshrrev_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x2c]
-
-v_lshrrev_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x2d]
-
-v_lshrrev_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x2c]
-
-v_lshrrev_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x2c]
-
-v_lshrrev_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x2c,0x56,0x34,0x12,0xaf]
-
-v_lshrrev_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x2c,0x73,0x72,0x71,0x3f]
-
-v_lshrrev_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x2c]
-
-v_lshrrev_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2c,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x67,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x68,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x69,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x6c,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x6d,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x6e,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x6f,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x7b,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x2c,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xff,0x03,0x00]
-
-v_lshrrev_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x05,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xcf,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd1,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd3,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd7,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd9,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xdb,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xdd,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xdf,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xf7,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xf9,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xff,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xef,0x01,0x00]
-
-v_ashr_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x2e]
-
-v_ashr_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x2f]
-
-v_ashr_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x2e]
-
-v_ashr_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x2e]
-
-v_ashr_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x2e,0x56,0x34,0x12,0xaf]
-
-v_ashr_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x2e,0x73,0x72,0x71,0x3f]
-
-v_ashr_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x2e]
-
-v_ashr_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashr_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2e,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashr_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0xff,0x05,0x02,0x00]
-
-v_ashr_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x67,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x68,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x69,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x6b,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x6c,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x6d,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x6e,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x6f,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x7b,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x7c,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x7f,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x80,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x2e,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ashr_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xff,0x03,0x00]
-
-v_ashr_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x05,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xcf,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd1,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd3,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd7,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd9,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xdb,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xdd,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xdf,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xf7,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xf9,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xff,0x00,0x00]
-
-v_ashr_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x01,0x01,0x00]
-
-v_ashr_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x83,0x01,0x00]
-
-v_ashr_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ashr_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xef,0x01,0x00]
-
-v_ashrrev_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x30]
-
-v_ashrrev_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x31]
-
-v_ashrrev_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x30]
-
-v_ashrrev_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x30]
-
-v_ashrrev_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x30,0x56,0x34,0x12,0xaf]
-
-v_ashrrev_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x30,0x73,0x72,0x71,0x3f]
-
-v_ashrrev_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x30]
-
-v_ashrrev_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x30,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x67,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x68,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x69,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x6c,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x6d,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x6e,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x6f,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x7b,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x30,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xff,0x03,0x00]
-
-v_ashrrev_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x05,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xcf,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd1,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd3,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd7,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd9,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xdb,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xdd,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xdf,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xf7,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xf9,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xff,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xef,0x01,0x00]
-
-v_lshl_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x32]
-
-v_lshl_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x33]
-
-v_lshl_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x32]
-
-v_lshl_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x32]
-
-v_lshl_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x32,0x56,0x34,0x12,0xaf]
-
-v_lshl_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x32,0x73,0x72,0x71,0x3f]
-
-v_lshl_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x32]
-
-v_lshl_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshl_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x32,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshl_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0xff,0x05,0x02,0x00]
-
-v_lshl_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x67,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x68,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x69,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x6b,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x6c,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x6d,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x6e,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x6f,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x7b,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x7c,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x7f,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x32,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshl_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xff,0x03,0x00]
-
-v_lshl_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x05,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xcf,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd1,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd3,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd7,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd9,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xdb,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xdd,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xdf,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xf7,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xf9,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xff,0x00,0x00]
-
-v_lshl_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshl_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshl_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshl_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xef,0x01,0x00]
-
-v_lshlrev_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x34]
-
-v_lshlrev_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x35]
-
-v_lshlrev_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x34]
-
-v_lshlrev_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x34]
-
-v_lshlrev_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x34,0x56,0x34,0x12,0xaf]
-
-v_lshlrev_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x34,0x73,0x72,0x71,0x3f]
-
-v_lshlrev_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x34]
-
-v_lshlrev_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x34,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x67,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x68,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x69,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x6c,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x6d,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x6e,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x6f,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x7b,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x34,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xff,0x03,0x00]
-
-v_lshlrev_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x05,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xcf,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd1,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd3,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd7,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd9,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xdb,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xdd,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xdf,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xf7,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xf9,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xff,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xef,0x01,0x00]
-
-v_and_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x36]
-
-v_and_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x37]
-
-v_and_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x36]
-
-v_and_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x36]
-
-v_and_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x36]
-
-v_and_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x36]
-
-v_and_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x36]
-
-v_and_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x36]
-
-v_and_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x36]
-
-v_and_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x36]
-
-v_and_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x36]
-
-v_and_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x36]
-
-v_and_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x36]
-
-v_and_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x36]
-
-v_and_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x36]
-
-v_and_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x36]
-
-v_and_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x36]
-
-v_and_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x36]
-
-v_and_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x36]
-
-v_and_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x36]
-
-v_and_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x36]
-
-v_and_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x36,0x56,0x34,0x12,0xaf]
-
-v_and_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x36,0x73,0x72,0x71,0x3f]
-
-v_and_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x36]
-
-v_and_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x05,0x02,0x00]
-
-v_and_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x36,0xd2,0x01,0x05,0x02,0x00]
-
-v_and_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0xff,0x05,0x02,0x00]
-
-v_and_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x67,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x68,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x69,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x6a,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x6b,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x6c,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x6d,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x6e,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x6f,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x7b,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x7c,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x7e,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x7f,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0x80,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0xc1,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0xf0,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x36,0xd2,0xf7,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xff,0x03,0x00]
-
-v_and_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x05,0x00,0x00]
-
-v_and_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xcf,0x00,0x00]
-
-v_and_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd1,0x00,0x00]
-
-v_and_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd3,0x00,0x00]
-
-v_and_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd5,0x00,0x00]
-
-v_and_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd7,0x00,0x00]
-
-v_and_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd9,0x00,0x00]
-
-v_and_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xdb,0x00,0x00]
-
-v_and_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xdd,0x00,0x00]
-
-v_and_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xdf,0x00,0x00]
-
-v_and_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xf7,0x00,0x00]
-
-v_and_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xf9,0x00,0x00]
-
-v_and_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xfd,0x00,0x00]
-
-v_and_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xff,0x00,0x00]
-
-v_and_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x01,0x01,0x00]
-
-v_and_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x83,0x01,0x00]
-
-v_and_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xe1,0x01,0x00]
-
-v_and_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xef,0x01,0x00]
-
-v_or_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x38]
-
-v_or_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x39]
-
-v_or_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x38]
-
-v_or_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x38]
-
-v_or_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x38]
-
-v_or_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x38]
-
-v_or_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x38]
-
-v_or_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x38]
-
-v_or_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x38]
-
-v_or_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x38]
-
-v_or_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x38]
-
-v_or_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x38]
-
-v_or_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x38]
-
-v_or_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x38]
-
-v_or_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x38]
-
-v_or_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x38]
-
-v_or_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x38]
-
-v_or_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x38]
-
-v_or_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x38]
-
-v_or_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x38]
-
-v_or_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x38]
-
-v_or_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x38,0x56,0x34,0x12,0xaf]
-
-v_or_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x38,0x73,0x72,0x71,0x3f]
-
-v_or_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x38]
-
-v_or_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x05,0x02,0x00]
-
-v_or_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x38,0xd2,0x01,0x05,0x02,0x00]
-
-v_or_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0xff,0x05,0x02,0x00]
-
-v_or_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x67,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x68,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x69,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x6a,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x6b,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x6c,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x6d,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x6e,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x6f,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x7b,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x7c,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x7e,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x7f,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0x80,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0xc1,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0xf0,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x38,0xd2,0xf7,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xff,0x03,0x00]
-
-v_or_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x05,0x00,0x00]
-
-v_or_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xcf,0x00,0x00]
-
-v_or_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd1,0x00,0x00]
-
-v_or_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd3,0x00,0x00]
-
-v_or_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd5,0x00,0x00]
-
-v_or_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd7,0x00,0x00]
-
-v_or_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd9,0x00,0x00]
-
-v_or_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xdb,0x00,0x00]
-
-v_or_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xdd,0x00,0x00]
-
-v_or_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xdf,0x00,0x00]
-
-v_or_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xf7,0x00,0x00]
-
-v_or_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xf9,0x00,0x00]
-
-v_or_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xfd,0x00,0x00]
-
-v_or_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xff,0x00,0x00]
-
-v_or_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x01,0x01,0x00]
-
-v_or_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x83,0x01,0x00]
-
-v_or_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xe1,0x01,0x00]
-
-v_or_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xef,0x01,0x00]
-
-v_xor_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x3a]
-
-v_xor_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x3b]
-
-v_xor_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x3a]
-
-v_xor_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x3a]
-
-v_xor_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x3a,0x56,0x34,0x12,0xaf]
-
-v_xor_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x3a,0x73,0x72,0x71,0x3f]
-
-v_xor_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x3a]
-
-v_xor_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x05,0x02,0x00]
-
-v_xor_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x3a,0xd2,0x01,0x05,0x02,0x00]
-
-v_xor_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0xff,0x05,0x02,0x00]
-
-v_xor_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x67,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x68,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x69,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x6a,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x6b,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x6c,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x6d,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x6e,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x6f,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x7b,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x7c,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x7e,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x7f,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x80,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0xc1,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0xf0,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x3a,0xd2,0xf7,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xff,0x03,0x00]
-
-v_xor_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x05,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xcf,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd1,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd3,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd5,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd7,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd9,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xdb,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xdd,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xdf,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xf7,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xf9,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xfd,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xff,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x01,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x83,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xe1,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xef,0x01,0x00]
-
-v_bfm_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x3c]
-
-v_bfm_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x3d]
-
-v_bfm_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x3c]
-
-v_bfm_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x3c]
-
-v_bfm_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x3c,0x56,0x34,0x12,0xaf]
-
-v_bfm_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x3c,0x73,0x72,0x71,0x3f]
-
-v_bfm_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x3c]
-
-v_bfm_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x05,0x02,0x00]
-
-v_bfm_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x3c,0xd2,0x01,0x05,0x02,0x00]
-
-v_bfm_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0xff,0x05,0x02,0x00]
-
-v_bfm_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x67,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x68,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x69,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x6a,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x6b,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x6c,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x6d,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x6e,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x6f,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x7b,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x7c,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x7e,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x7f,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x80,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0xc1,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0xf0,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x3c,0xd2,0xf7,0x04,0x02,0x00]
-
-v_bfm_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xff,0x03,0x00]
-
-v_bfm_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x05,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xcf,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd1,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd3,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd5,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd7,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd9,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xdb,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xdd,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xdf,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xf7,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xf9,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xfd,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xff,0x00,0x00]
-
-v_bfm_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x01,0x01,0x00]
-
-v_bfm_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x83,0x01,0x00]
-
-v_bfm_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xe1,0x01,0x00]
-
-v_bfm_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xef,0x01,0x00]
-
-v_mac_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x3e]
-
-v_mac_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x3f]
-
-v_mac_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x3e]
-
-v_mac_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x3e]
-
-v_mac_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x3e,0x56,0x34,0x12,0xaf]
-
-v_mac_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x3e,0x73,0x72,0x71,0x3f]
-
-v_mac_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x3e]
-
-v_mac_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x3e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0xff,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x67,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x68,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x69,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x80,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xff,0x03,0x00]
-
-v_mac_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xff,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x01,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x83,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xef,0x01,0x00]
-
-v_mac_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x20]
-
-v_mac_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x40]
-
-v_mac_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x60]
-
-v_mac_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x3e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x3e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x3e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x08,0x3e,0xd2,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x08]
-
-v_mac_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x10]
-
-v_mac_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x18]
-
-v_madmk_f32 v5, v1, 0x11213141, v3
-// CHECK: [0x01,0x07,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v255, v1, 0x11213141, v3
-// CHECK: [0x01,0x07,0xfe,0x41,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, v255, 0x11213141, v3
-// CHECK: [0xff,0x07,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, 0, 0x11213141, v3
-// CHECK: [0x80,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, -1, 0x11213141, v3
-// CHECK: [0xc1,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, 0.5, 0x11213141, v3
-// CHECK: [0xf0,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, -4.0, 0x11213141, v3
-// CHECK: [0xf7,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, v1, 0xa1b1c1d1, v3
-// CHECK: [0x01,0x07,0x0a,0x40,0xd1,0xc1,0xb1,0xa1]
-
-v_madmk_f32 v5, v1, 0x11213141, v255
-// CHECK: [0x01,0xff,0x0b,0x40,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v2, 0x11213141
-// CHECK: [0x01,0x05,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v255, v1, v2, 0x11213141
-// CHECK: [0x01,0x05,0xfe,0x43,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v255, v2, 0x11213141
-// CHECK: [0xff,0x05,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, 0, v2, 0x11213141
-// CHECK: [0x80,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, -1, v2, 0x11213141
-// CHECK: [0xc1,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, 0.5, v2, 0x11213141
-// CHECK: [0xf0,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, -4.0, v2, 0x11213141
-// CHECK: [0xf7,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v255, 0x11213141
-// CHECK: [0x01,0xff,0x0b,0x42,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v2, 0xa1b1c1d1
-// CHECK: [0x01,0x05,0x0a,0x42,0xd1,0xc1,0xb1,0xa1]
-
-v_bcnt_u32_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x44]
-
-v_bcnt_u32_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x45]
-
-v_bcnt_u32_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x44]
-
-v_bcnt_u32_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x44,0x56,0x34,0x12,0xaf]
-
-v_bcnt_u32_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x44,0x73,0x72,0x71,0x3f]
-
-v_bcnt_u32_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x44]
-
-v_bcnt_u32_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x05,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x44,0xd2,0x01,0x05,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0xff,0x05,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x67,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x68,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x69,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x6a,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x6b,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x6c,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x6d,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x6e,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x6f,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x7b,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x7c,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x7e,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x7f,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0x80,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0xc1,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0xf0,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x44,0xd2,0xf7,0x04,0x02,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xff,0x03,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x05,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xcf,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd1,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd3,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd5,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd7,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd9,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xdb,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xdd,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xdf,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xf7,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xf9,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xfd,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xff,0x00,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x01,0x01,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x83,0x01,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xe1,0x01,0x00]
-
-v_bcnt_u32_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xef,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x47]
-
-v_mbcnt_lo_u32_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x46]
-
-v_mbcnt_lo_u32_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x46,0x56,0x34,0x12,0xaf]
-
-v_mbcnt_lo_u32_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x46,0x73,0x72,0x71,0x3f]
-
-v_mbcnt_lo_u32_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x46]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x46,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0xff,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x67,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x68,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x69,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0x80,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x46,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xff,0x03,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x05,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xff,0x00,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x01,0x01,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x83,0x01,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mbcnt_lo_u32_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xef,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x49]
-
-v_mbcnt_hi_u32_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x48]
-
-v_mbcnt_hi_u32_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x48,0x56,0x34,0x12,0xaf]
-
-v_mbcnt_hi_u32_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x48,0x73,0x72,0x71,0x3f]
-
-v_mbcnt_hi_u32_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x48]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x48,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0xff,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x67,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x68,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x69,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0x80,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x48,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xff,0x03,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x05,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xff,0x00,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x01,0x01,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x83,0x01,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mbcnt_hi_u32_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xef,0x01,0x00]
-
-v_add_i32 v5, vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x4a]
-
-v_add_i32 v255, vcc, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x4b]
-
-v_add_i32 v5, vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x4a]
-
-v_add_i32 v5, vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x4a]
-
-v_add_i32 v5, vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x4a,0x56,0x34,0x12,0xaf]
-
-v_add_i32 v5, vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x4a,0x73,0x72,0x71,0x3f]
-
-v_add_i32 v5, vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x4a]
-
-v_add_i32_e64 v5, s[12:13], v1, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32_e64 v255, s[12:13], v1, v2
-// CHECK: [0xff,0x0c,0x4a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32_e64 v5, s[14:15], v1, v2
-// CHECK: [0x05,0x0e,0x4a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32_e64 v5, s[102:103], v1, v2
-// CHECK: [0x05,0x66,0x4a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32_e64 v5, flat_scratch, v1, v2
-// CHECK: [0x05,0x68,0x4a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32_e64 v5, vcc, v1, v2
-// CHECK: [0x05,0x6a,0x4a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32_e64 v5, tba, v1, v2
-// CHECK: [0x05,0x6c,0x4a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32_e64 v5, tma, v1, v2
-// CHECK: [0x05,0x6e,0x4a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32_e64 v5, ttmp[10:11], v1, v2
-// CHECK: [0x05,0x7a,0x4a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], v255, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0xff,0x05,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], s1, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], s103, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x67,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], flat_scratch_lo, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x68,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], flat_scratch_hi, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x69,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], vcc_lo, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x6a,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], vcc_hi, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x6b,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], tba_lo, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x6c,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], tba_hi, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x6d,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], tma_lo, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x6e,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], tma_hi, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x6f,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], ttmp11, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x7b,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], m0, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x7c,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], exec_lo, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x7e,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], exec_hi, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x7f,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], 0, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x80,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], -1, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0xc1,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], 0.5, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0xf0,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], -4.0, v2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0xf7,0x04,0x02,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, v255
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xff,0x03,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, s2
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x05,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, s103
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xcf,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, flat_scratch_lo
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd1,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, flat_scratch_hi
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd3,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, vcc_lo
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd5,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, vcc_hi
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd7,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, tba_lo
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd9,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, tba_hi
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xdb,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, tma_lo
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xdd,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, tma_hi
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xdf,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, ttmp11
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xf7,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, m0
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xf9,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, exec_lo
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xfd,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, exec_hi
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xff,0x00,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, 0
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x01,0x01,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, -1
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x83,0x01,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, 0.5
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xe1,0x01,0x00]
-
-v_add_i32_e64 v5, s[12:13], v1, -4.0
-// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xef,0x01,0x00]
-
-v_sub_i32 v5, vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x4c]
-
-v_sub_i32 v255, vcc, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x4d]
-
-v_sub_i32 v5, vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x4c]
-
-v_sub_i32 v5, vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x4c,0x56,0x34,0x12,0xaf]
-
-v_sub_i32 v5, vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x4c,0x73,0x72,0x71,0x3f]
-
-v_sub_i32 v5, vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x4c]
-
-v_sub_i32_e64 v5, s[12:13], v1, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32_e64 v255, s[12:13], v1, v2
-// CHECK: [0xff,0x0c,0x4c,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32_e64 v5, s[14:15], v1, v2
-// CHECK: [0x05,0x0e,0x4c,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32_e64 v5, s[102:103], v1, v2
-// CHECK: [0x05,0x66,0x4c,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32_e64 v5, flat_scratch, v1, v2
-// CHECK: [0x05,0x68,0x4c,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32_e64 v5, vcc, v1, v2
-// CHECK: [0x05,0x6a,0x4c,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32_e64 v5, tba, v1, v2
-// CHECK: [0x05,0x6c,0x4c,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32_e64 v5, tma, v1, v2
-// CHECK: [0x05,0x6e,0x4c,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32_e64 v5, ttmp[10:11], v1, v2
-// CHECK: [0x05,0x7a,0x4c,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v255, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0xff,0x05,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], s1, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], s103, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x67,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], flat_scratch_lo, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x68,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], flat_scratch_hi, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x69,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], vcc_lo, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x6a,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], vcc_hi, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x6b,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], tba_lo, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x6c,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], tba_hi, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x6d,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], tma_lo, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x6e,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], tma_hi, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x6f,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], ttmp11, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x7b,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], m0, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x7c,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], exec_lo, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x7e,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], exec_hi, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x7f,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], 0, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x80,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], -1, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0xc1,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], 0.5, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0xf0,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], -4.0, v2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0xf7,0x04,0x02,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, v255
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xff,0x03,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, s2
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x05,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, s103
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xcf,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, flat_scratch_lo
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd1,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, flat_scratch_hi
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd3,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, vcc_lo
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd5,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, vcc_hi
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd7,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, tba_lo
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd9,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, tba_hi
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xdb,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, tma_lo
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xdd,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, tma_hi
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xdf,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, ttmp11
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xf7,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, m0
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xf9,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, exec_lo
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xfd,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, exec_hi
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xff,0x00,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, 0
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x01,0x01,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, -1
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x83,0x01,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, 0.5
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xe1,0x01,0x00]
-
-v_sub_i32_e64 v5, s[12:13], v1, -4.0
-// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xef,0x01,0x00]
-
-v_subrev_i32 v5, vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x4e]
-
-v_subrev_i32 v255, vcc, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x4f]
-
-v_subrev_i32 v5, vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x4e]
-
-v_subrev_i32 v5, vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x4e,0x56,0x34,0x12,0xaf]
-
-v_subrev_i32 v5, vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x4e,0x73,0x72,0x71,0x3f]
-
-v_subrev_i32 v5, vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x4e]
-
-v_subrev_i32_e64 v5, s[12:13], v1, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v255, s[12:13], v1, v2
-// CHECK: [0xff,0x0c,0x4e,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[14:15], v1, v2
-// CHECK: [0x05,0x0e,0x4e,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[102:103], v1, v2
-// CHECK: [0x05,0x66,0x4e,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v5, flat_scratch, v1, v2
-// CHECK: [0x05,0x68,0x4e,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v5, vcc, v1, v2
-// CHECK: [0x05,0x6a,0x4e,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v5, tba, v1, v2
-// CHECK: [0x05,0x6c,0x4e,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v5, tma, v1, v2
-// CHECK: [0x05,0x6e,0x4e,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v5, ttmp[10:11], v1, v2
-// CHECK: [0x05,0x7a,0x4e,0xd2,0x01,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v255, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0xff,0x05,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], s1, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], s103, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x67,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], flat_scratch_lo, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x68,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], flat_scratch_hi, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x69,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], vcc_lo, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x6a,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], vcc_hi, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x6b,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], tba_lo, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x6c,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], tba_hi, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x6d,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], tma_lo, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x6e,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], tma_hi, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x6f,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], ttmp11, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x7b,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], m0, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x7c,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], exec_lo, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x7e,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], exec_hi, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x7f,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], 0, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x80,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], -1, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0xc1,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], 0.5, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0xf0,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], -4.0, v2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0xf7,0x04,0x02,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, v255
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xff,0x03,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, s2
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x05,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, s103
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xcf,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, flat_scratch_lo
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd1,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, flat_scratch_hi
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd3,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, vcc_lo
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd5,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, vcc_hi
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd7,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, tba_lo
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd9,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, tba_hi
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xdb,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, tma_lo
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xdd,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, tma_hi
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xdf,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, ttmp11
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xf7,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, m0
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xf9,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, exec_lo
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xfd,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, exec_hi
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xff,0x00,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, 0
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x01,0x01,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, -1
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x83,0x01,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, 0.5
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xe1,0x01,0x00]
-
-v_subrev_i32_e64 v5, s[12:13], v1, -4.0
-// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xef,0x01,0x00]
-
-v_addc_u32 v5, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x50]
-
-v_addc_u32 v255, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x51]
-
-v_addc_u32 v5, vcc, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x50]
-
-v_addc_u32 v5, vcc, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x50]
-
-v_addc_u32 v5, vcc, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x50]
-
-v_addc_u32 v5, vcc, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x50]
-
-v_addc_u32 v5, vcc, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x50]
-
-v_addc_u32 v5, vcc, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x50]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: [0xff,0x0c,0x50,0xd2,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// CHECK: [0x05,0x0e,0x50,0xd2,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[102:103], v1, v2, s[6:7]
-// CHECK: [0x05,0x66,0x50,0xd2,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
-// CHECK: [0x05,0x68,0x50,0xd2,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, vcc, v1, v2, s[6:7]
-// CHECK: [0x05,0x6a,0x50,0xd2,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, tba, v1, v2, s[6:7]
-// CHECK: [0x05,0x6c,0x50,0xd2,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, tma, v1, v2, s[6:7]
-// CHECK: [0x05,0x6e,0x50,0xd2,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
-// CHECK: [0x05,0x7a,0x50,0xd2,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0xff,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x80,0x04,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0xc1,0x04,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0xf0,0x04,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0xf7,0x04,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0xff,0x1b,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x01,0x19,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x83,0x19,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0xe1,0x19,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0xef,0x19,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0x22,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, s[102:103]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0x9a,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xa2,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xaa,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xb2,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xba,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xea,0x01]
-
-v_subb_u32 v5, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x52]
-
-v_subb_u32 v255, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x53]
-
-v_subb_u32 v5, vcc, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x52]
-
-v_subb_u32 v5, vcc, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x52]
-
-v_subb_u32 v5, vcc, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x52]
-
-v_subb_u32 v5, vcc, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x52]
-
-v_subb_u32 v5, vcc, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x52]
-
-v_subb_u32 v5, vcc, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x52]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: [0xff,0x0c,0x52,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// CHECK: [0x05,0x0e,0x52,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[102:103], v1, v2, s[6:7]
-// CHECK: [0x05,0x66,0x52,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
-// CHECK: [0x05,0x68,0x52,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, vcc, v1, v2, s[6:7]
-// CHECK: [0x05,0x6a,0x52,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, tba, v1, v2, s[6:7]
-// CHECK: [0x05,0x6c,0x52,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, tma, v1, v2, s[6:7]
-// CHECK: [0x05,0x6e,0x52,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
-// CHECK: [0x05,0x7a,0x52,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0xff,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x80,0x04,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0xc1,0x04,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0xf0,0x04,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0xf7,0x04,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0xff,0x1b,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x01,0x19,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x83,0x19,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0xe1,0x19,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0xef,0x19,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0x22,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, s[102:103]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0x9a,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xa2,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xaa,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xb2,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xba,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xea,0x01]
-
-v_subbrev_u32 v5, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x54]
-
-v_subbrev_u32 v255, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x55]
-
-v_subbrev_u32 v5, vcc, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x54]
-
-v_subbrev_u32 v5, vcc, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x54]
-
-v_subbrev_u32 v5, vcc, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x54]
-
-v_subbrev_u32 v5, vcc, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x54]
-
-v_subbrev_u32 v5, vcc, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x54]
-
-v_subbrev_u32 v5, vcc, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x54]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: [0xff,0x0c,0x54,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// CHECK: [0x05,0x0e,0x54,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[102:103], v1, v2, s[6:7]
-// CHECK: [0x05,0x66,0x54,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
-// CHECK: [0x05,0x68,0x54,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, vcc, v1, v2, s[6:7]
-// CHECK: [0x05,0x6a,0x54,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, tba, v1, v2, s[6:7]
-// CHECK: [0x05,0x6c,0x54,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, tma, v1, v2, s[6:7]
-// CHECK: [0x05,0x6e,0x54,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
-// CHECK: [0x05,0x7a,0x54,0xd2,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0xff,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x80,0x04,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0xc1,0x04,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0xf0,0x04,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0xf7,0x04,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0xff,0x1b,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x01,0x19,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x83,0x19,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0xe1,0x19,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0xef,0x19,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0x22,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[102:103]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0x9a,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xa2,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xaa,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xb2,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xba,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xea,0x01]
-
-v_ldexp_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x56]
-
-v_ldexp_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x57]
-
-v_ldexp_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x56]
-
-v_ldexp_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x56]
-
-v_ldexp_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x56,0x56,0x34,0x12,0xaf]
-
-v_ldexp_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x56,0x73,0x72,0x71,0x3f]
-
-v_ldexp_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x56]
-
-v_ldexp_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x56,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0xff,0x05,0x02,0x00]
-
-v_ldexp_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x67,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x68,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x69,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x6b,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x6c,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x6d,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x6e,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x6f,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x7b,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x7c,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x7f,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0x80,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x56,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xff,0x03,0x00]
-
-v_ldexp_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x05,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd1,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd3,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd9,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xdb,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xdd,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xdf,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xf7,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xff,0x00,0x00]
-
-v_ldexp_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x01,0x01,0x00]
-
-v_ldexp_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x83,0x01,0x00]
-
-v_ldexp_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x59]
-
-v_cvt_pkaccum_u8_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x58]
-
-v_cvt_pkaccum_u8_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x58,0x56,0x34,0x12,0xaf]
-
-v_cvt_pkaccum_u8_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x58,0x73,0x72,0x71,0x3f]
-
-v_cvt_pkaccum_u8_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x58]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x58,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x68,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x69,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd1,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd3,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pkaccum_u8_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x58,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x5b]
-
-v_cvt_pknorm_i16_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x5a]
-
-v_cvt_pknorm_i16_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
-
-v_cvt_pknorm_i16_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x5a,0x73,0x72,0x71,0x3f]
-
-v_cvt_pknorm_i16_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x5a]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x5a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x68,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x69,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd1,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd3,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_i16_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_i16_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x5a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x5a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x5a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x5d]
-
-v_cvt_pknorm_u16_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x5c]
-
-v_cvt_pknorm_u16_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x5c,0x56,0x34,0x12,0xaf]
-
-v_cvt_pknorm_u16_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x5c,0x73,0x72,0x71,0x3f]
-
-v_cvt_pknorm_u16_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x5c]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x5c,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x68,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x69,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd1,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd3,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_u16_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_u16_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x5c,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x5c,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x5c,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x5f]
-
-v_cvt_pkrtz_f16_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x5e]
-
-v_cvt_pkrtz_f16_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x5e,0x56,0x34,0x12,0xaf]
-
-v_cvt_pkrtz_f16_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x5e,0x73,0x72,0x71,0x3f]
-
-v_cvt_pkrtz_f16_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x5e]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x5e,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x68,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x69,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd1,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd3,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pkrtz_f16_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pkrtz_f16_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x5e,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x5e,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x5e,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x61]
-
-v_cvt_pk_u16_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x60]
-
-v_cvt_pk_u16_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x60,0x56,0x34,0x12,0xaf]
-
-v_cvt_pk_u16_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x60,0x73,0x72,0x71,0x3f]
-
-v_cvt_pk_u16_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x60]
-
-v_cvt_pk_u16_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x60,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x68,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x69,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x60,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd1,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd3,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pk_u16_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x63]
-
-v_cvt_pk_i16_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x62]
-
-v_cvt_pk_i16_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x62,0x56,0x34,0x12,0xaf]
-
-v_cvt_pk_i16_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x62,0x73,0x72,0x71,0x3f]
-
-v_cvt_pk_i16_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x62]
-
-v_cvt_pk_i16_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x62,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, s103, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x68,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x69,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x62,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, s103
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd1,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd3,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pk_i16_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xef,0x01,0x00]
-
-v_mad_legacy_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x80,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x68,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x69,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mad_legacy_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xef,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xfe,0x07]
-
-v_mad_legacy_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x00]
-
-v_mad_legacy_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x9e,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xa2,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xa6,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xae,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xb2,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xb6,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xba,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xbe,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xee,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xf2,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xfe,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x02]
-
-v_mad_legacy_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x06,0x03]
-
-v_mad_legacy_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xc2,0x03]
-
-v_mad_legacy_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xde,0x03]
-
-v_mad_legacy_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x24]
-
-v_mad_legacy_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x44]
-
-v_mad_legacy_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x84]
-
-v_mad_legacy_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_mad_legacy_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x80,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x80,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x80,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x80,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0x80,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_mad_legacy_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x14]
-
-v_mad_legacy_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_mad_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x82,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mad_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mad_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mad_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x68,0x04,0x0e,0x04]
-
-v_mad_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x69,0x04,0x0e,0x04]
-
-v_mad_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mad_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mad_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_mad_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_mad_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_mad_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_mad_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_mad_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mad_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mad_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mad_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mad_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mad_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_mad_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_mad_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mad_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mad_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mad_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_mad_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_mad_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mad_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mad_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_mad_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_mad_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_mad_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_mad_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_mad_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mad_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mad_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mad_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mad_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_mad_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xef,0x0d,0x04]
-
-v_mad_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xfe,0x07]
-
-v_mad_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x00]
-
-v_mad_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x9e,0x01]
-
-v_mad_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xa2,0x01]
-
-v_mad_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xa6,0x01]
-
-v_mad_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mad_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xae,0x01]
-
-v_mad_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xb2,0x01]
-
-v_mad_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xb6,0x01]
-
-v_mad_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xba,0x01]
-
-v_mad_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xbe,0x01]
-
-v_mad_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xee,0x01]
-
-v_mad_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xf2,0x01]
-
-v_mad_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mad_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xfe,0x01]
-
-v_mad_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x02]
-
-v_mad_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x06,0x03]
-
-v_mad_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xc2,0x03]
-
-v_mad_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xde,0x03]
-
-v_mad_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x24]
-
-v_mad_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x44]
-
-v_mad_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x84]
-
-v_mad_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_mad_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x82,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x82,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x82,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x82,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0x82,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_mad_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x14]
-
-v_mad_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_mad_i32_i24 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x84,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x68,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x69,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mad_i32_i24 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xef,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xfe,0x07]
-
-v_mad_i32_i24 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x0e,0x00]
-
-v_mad_i32_i24 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x9e,0x01]
-
-v_mad_i32_i24 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xa2,0x01]
-
-v_mad_i32_i24 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xa6,0x01]
-
-v_mad_i32_i24 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mad_i32_i24 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xae,0x01]
-
-v_mad_i32_i24 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xb2,0x01]
-
-v_mad_i32_i24 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xb6,0x01]
-
-v_mad_i32_i24 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xba,0x01]
-
-v_mad_i32_i24 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xbe,0x01]
-
-v_mad_i32_i24 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xee,0x01]
-
-v_mad_i32_i24 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xf2,0x01]
-
-v_mad_i32_i24 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mad_i32_i24 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xfe,0x01]
-
-v_mad_i32_i24 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x02]
-
-v_mad_i32_i24 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x06,0x03]
-
-v_mad_i32_i24 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xc2,0x03]
-
-v_mad_i32_i24 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xde,0x03]
-
-v_mad_u32_u24 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x86,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x68,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x69,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mad_u32_u24 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xef,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xfe,0x07]
-
-v_mad_u32_u24 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x0e,0x00]
-
-v_mad_u32_u24 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x9e,0x01]
-
-v_mad_u32_u24 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xa2,0x01]
-
-v_mad_u32_u24 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xa6,0x01]
-
-v_mad_u32_u24 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mad_u32_u24 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xae,0x01]
-
-v_mad_u32_u24 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xb2,0x01]
-
-v_mad_u32_u24 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xb6,0x01]
-
-v_mad_u32_u24 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xba,0x01]
-
-v_mad_u32_u24 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xbe,0x01]
-
-v_mad_u32_u24 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xee,0x01]
-
-v_mad_u32_u24 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xf2,0x01]
-
-v_mad_u32_u24 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mad_u32_u24 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xfe,0x01]
-
-v_mad_u32_u24 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x02,0x02]
-
-v_mad_u32_u24 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x06,0x03]
-
-v_mad_u32_u24 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xc2,0x03]
-
-v_mad_u32_u24 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xde,0x03]
-
-v_cubeid_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x88,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0xff,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x67,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x68,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x69,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x80,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x0f,0x04]
-
-v_cubeid_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x01,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x83,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xef,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xfe,0x07]
-
-v_cubeid_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x00]
-
-v_cubeid_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x9e,0x01]
-
-v_cubeid_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xa2,0x01]
-
-v_cubeid_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xa6,0x01]
-
-v_cubeid_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xaa,0x01]
-
-v_cubeid_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xae,0x01]
-
-v_cubeid_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xb2,0x01]
-
-v_cubeid_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xb6,0x01]
-
-v_cubeid_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xba,0x01]
-
-v_cubeid_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xbe,0x01]
-
-v_cubeid_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xee,0x01]
-
-v_cubeid_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xf2,0x01]
-
-v_cubeid_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xfa,0x01]
-
-v_cubeid_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xfe,0x01]
-
-v_cubeid_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x02]
-
-v_cubeid_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x06,0x03]
-
-v_cubeid_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xc2,0x03]
-
-v_cubeid_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xde,0x03]
-
-v_cubeid_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x24]
-
-v_cubeid_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x44]
-
-v_cubeid_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x84]
-
-v_cubeid_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_cubeid_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x88,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x88,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x88,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x88,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0x88,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_cubeid_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x14]
-
-v_cubeid_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_cubesc_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0xff,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x67,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x68,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x69,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xff,0x0f,0x04]
-
-v_cubesc_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xff,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x01,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x83,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xef,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xfe,0x07]
-
-v_cubesc_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x00]
-
-v_cubesc_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x9e,0x01]
-
-v_cubesc_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xa2,0x01]
-
-v_cubesc_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xa6,0x01]
-
-v_cubesc_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xaa,0x01]
-
-v_cubesc_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xae,0x01]
-
-v_cubesc_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xb2,0x01]
-
-v_cubesc_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xb6,0x01]
-
-v_cubesc_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xba,0x01]
-
-v_cubesc_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xbe,0x01]
-
-v_cubesc_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xee,0x01]
-
-v_cubesc_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xf2,0x01]
-
-v_cubesc_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xfa,0x01]
-
-v_cubesc_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xfe,0x01]
-
-v_cubesc_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x02,0x02]
-
-v_cubesc_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x06,0x03]
-
-v_cubesc_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xc2,0x03]
-
-v_cubesc_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xde,0x03]
-
-v_cubesc_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x24]
-
-v_cubesc_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x44]
-
-v_cubesc_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x84]
-
-v_cubesc_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_cubesc_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x8a,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x8a,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x8a,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x8a,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0x8a,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_cubesc_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x14]
-
-v_cubesc_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_cubetc_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0xff,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x67,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x68,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x69,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x80,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x0f,0x04]
-
-v_cubetc_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x01,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x83,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xef,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xfe,0x07]
-
-v_cubetc_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x00]
-
-v_cubetc_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x9e,0x01]
-
-v_cubetc_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xa2,0x01]
-
-v_cubetc_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xa6,0x01]
-
-v_cubetc_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xaa,0x01]
-
-v_cubetc_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xae,0x01]
-
-v_cubetc_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xb2,0x01]
-
-v_cubetc_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xb6,0x01]
-
-v_cubetc_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xba,0x01]
-
-v_cubetc_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xbe,0x01]
-
-v_cubetc_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xee,0x01]
-
-v_cubetc_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xf2,0x01]
-
-v_cubetc_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xfa,0x01]
-
-v_cubetc_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xfe,0x01]
-
-v_cubetc_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x02,0x02]
-
-v_cubetc_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x06,0x03]
-
-v_cubetc_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xc2,0x03]
-
-v_cubetc_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xde,0x03]
-
-v_cubetc_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x24]
-
-v_cubetc_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x44]
-
-v_cubetc_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x84]
-
-v_cubetc_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_cubetc_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x8c,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x8c,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x8c,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x8c,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0x8c,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_cubetc_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x14]
-
-v_cubetc_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_cubema_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0xff,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x67,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x68,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x69,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x80,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xff,0x0f,0x04]
-
-v_cubema_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0c,0x04]
-
-v_cubema_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_cubema_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_cubema_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_cubema_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_cubema_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_cubema_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_cubema_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_cubema_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_cubema_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_cubema_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_cubema_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_cubema_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_cubema_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xff,0x0c,0x04]
-
-v_cubema_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x01,0x0d,0x04]
-
-v_cubema_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x83,0x0d,0x04]
-
-v_cubema_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_cubema_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xef,0x0d,0x04]
-
-v_cubema_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xfe,0x07]
-
-v_cubema_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x00]
-
-v_cubema_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x9e,0x01]
-
-v_cubema_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xa2,0x01]
-
-v_cubema_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xa6,0x01]
-
-v_cubema_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xaa,0x01]
-
-v_cubema_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xae,0x01]
-
-v_cubema_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xb2,0x01]
-
-v_cubema_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xb6,0x01]
-
-v_cubema_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xba,0x01]
-
-v_cubema_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xbe,0x01]
-
-v_cubema_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xee,0x01]
-
-v_cubema_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xf2,0x01]
-
-v_cubema_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xfa,0x01]
-
-v_cubema_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xfe,0x01]
-
-v_cubema_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x02,0x02]
-
-v_cubema_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x06,0x03]
-
-v_cubema_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xc2,0x03]
-
-v_cubema_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xde,0x03]
-
-v_cubema_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x24]
-
-v_cubema_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x44]
-
-v_cubema_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x84]
-
-v_cubema_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_cubema_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x8e,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x8e,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x8e,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x8e,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0x8e,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_cubema_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x14]
-
-v_cubema_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_bfe_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x0e,0x04]
-
-v_bfe_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x90,0xd2,0x01,0x05,0x0e,0x04]
-
-v_bfe_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0xff,0x05,0x0e,0x04]
-
-v_bfe_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x67,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x68,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x69,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x80,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xff,0x0f,0x04]
-
-v_bfe_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x0c,0x04]
-
-v_bfe_u32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_bfe_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_bfe_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_bfe_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_bfe_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_bfe_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_bfe_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_bfe_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_bfe_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_bfe_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_bfe_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_bfe_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_bfe_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xff,0x0c,0x04]
-
-v_bfe_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x01,0x0d,0x04]
-
-v_bfe_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x83,0x0d,0x04]
-
-v_bfe_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_bfe_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xef,0x0d,0x04]
-
-v_bfe_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xfe,0x07]
-
-v_bfe_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x0e,0x00]
-
-v_bfe_u32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x9e,0x01]
-
-v_bfe_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xa2,0x01]
-
-v_bfe_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xa6,0x01]
-
-v_bfe_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xaa,0x01]
-
-v_bfe_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xae,0x01]
-
-v_bfe_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xb2,0x01]
-
-v_bfe_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xb6,0x01]
-
-v_bfe_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xba,0x01]
-
-v_bfe_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xbe,0x01]
-
-v_bfe_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xee,0x01]
-
-v_bfe_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xf2,0x01]
-
-v_bfe_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xfa,0x01]
-
-v_bfe_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xfe,0x01]
-
-v_bfe_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x02,0x02]
-
-v_bfe_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x06,0x03]
-
-v_bfe_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xc2,0x03]
-
-v_bfe_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xde,0x03]
-
-v_bfe_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x0e,0x04]
-
-v_bfe_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x92,0xd2,0x01,0x05,0x0e,0x04]
-
-v_bfe_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0xff,0x05,0x0e,0x04]
-
-v_bfe_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x67,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x68,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x69,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x80,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x0f,0x04]
-
-v_bfe_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x0c,0x04]
-
-v_bfe_i32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_bfe_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_bfe_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_bfe_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_bfe_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_bfe_i32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_bfe_i32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_bfe_i32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_bfe_i32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_bfe_i32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_bfe_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_bfe_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_bfe_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x0c,0x04]
-
-v_bfe_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x01,0x0d,0x04]
-
-v_bfe_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x83,0x0d,0x04]
-
-v_bfe_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_bfe_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xef,0x0d,0x04]
-
-v_bfe_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xfe,0x07]
-
-v_bfe_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x0e,0x00]
-
-v_bfe_i32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x9e,0x01]
-
-v_bfe_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xa2,0x01]
-
-v_bfe_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xa6,0x01]
-
-v_bfe_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xaa,0x01]
-
-v_bfe_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xae,0x01]
-
-v_bfe_i32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xb2,0x01]
-
-v_bfe_i32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xb6,0x01]
-
-v_bfe_i32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xba,0x01]
-
-v_bfe_i32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xbe,0x01]
-
-v_bfe_i32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xee,0x01]
-
-v_bfe_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xf2,0x01]
-
-v_bfe_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xfa,0x01]
-
-v_bfe_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xfe,0x01]
-
-v_bfe_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x02]
-
-v_bfe_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x06,0x03]
-
-v_bfe_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xc2,0x03]
-
-v_bfe_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xde,0x03]
-
-v_bfi_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x0e,0x04]
-
-v_bfi_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x94,0xd2,0x01,0x05,0x0e,0x04]
-
-v_bfi_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0xff,0x05,0x0e,0x04]
-
-v_bfi_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x67,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x68,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x69,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x80,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x0f,0x04]
-
-v_bfi_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x0c,0x04]
-
-v_bfi_b32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_bfi_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_bfi_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_bfi_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_bfi_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_bfi_b32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_bfi_b32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_bfi_b32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_bfi_b32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_bfi_b32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_bfi_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_bfi_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_bfi_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x0c,0x04]
-
-v_bfi_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x01,0x0d,0x04]
-
-v_bfi_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x83,0x0d,0x04]
-
-v_bfi_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_bfi_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xef,0x0d,0x04]
-
-v_bfi_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xfe,0x07]
-
-v_bfi_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x0e,0x00]
-
-v_bfi_b32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x9e,0x01]
-
-v_bfi_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xa2,0x01]
-
-v_bfi_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xa6,0x01]
-
-v_bfi_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xaa,0x01]
-
-v_bfi_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xae,0x01]
-
-v_bfi_b32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xb2,0x01]
-
-v_bfi_b32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xb6,0x01]
-
-v_bfi_b32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xba,0x01]
-
-v_bfi_b32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xbe,0x01]
-
-v_bfi_b32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xee,0x01]
-
-v_bfi_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xf2,0x01]
-
-v_bfi_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xfa,0x01]
-
-v_bfi_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xfe,0x01]
-
-v_bfi_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x02]
-
-v_bfi_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x06,0x03]
-
-v_bfi_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xc2,0x03]
-
-v_bfi_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xde,0x03]
-
-v_fma_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x96,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0xff,0x05,0x0e,0x04]
-
-v_fma_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x04,0x0e,0x04]
-
-v_fma_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x67,0x04,0x0e,0x04]
-
-v_fma_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x68,0x04,0x0e,0x04]
-
-v_fma_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x69,0x04,0x0e,0x04]
-
-v_fma_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_fma_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_fma_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_fma_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_fma_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_fma_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_fma_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_fma_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_fma_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_fma_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_fma_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x80,0x04,0x0e,0x04]
-
-v_fma_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_fma_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_fma_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_fma_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x0f,0x04]
-
-v_fma_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0c,0x04]
-
-v_fma_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_fma_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_fma_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_fma_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_fma_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_fma_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_fma_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_fma_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_fma_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_fma_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_fma_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_fma_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_fma_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x0c,0x04]
-
-v_fma_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x01,0x0d,0x04]
-
-v_fma_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x83,0x0d,0x04]
-
-v_fma_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_fma_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xef,0x0d,0x04]
-
-v_fma_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xfe,0x07]
-
-v_fma_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x00]
-
-v_fma_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x9e,0x01]
-
-v_fma_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xa2,0x01]
-
-v_fma_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xa6,0x01]
-
-v_fma_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xaa,0x01]
-
-v_fma_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xae,0x01]
-
-v_fma_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xb2,0x01]
-
-v_fma_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xb6,0x01]
-
-v_fma_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xba,0x01]
-
-v_fma_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xbe,0x01]
-
-v_fma_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xee,0x01]
-
-v_fma_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xf2,0x01]
-
-v_fma_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xfa,0x01]
-
-v_fma_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xfe,0x01]
-
-v_fma_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x02]
-
-v_fma_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x06,0x03]
-
-v_fma_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xc2,0x03]
-
-v_fma_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xde,0x03]
-
-v_fma_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x24]
-
-v_fma_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x44]
-
-v_fma_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x84]
-
-v_fma_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_fma_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x96,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x96,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x96,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x96,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0x96,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_fma_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x14]
-
-v_fma_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x00,0x98,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0xfe,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[2:3], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x02,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[4:5], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x04,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[102:103], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x66,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x68,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], tba, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], tma, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x7a,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], exec, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x80,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfd,0x0f,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[4:5], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x09,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[6:7], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x0d,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[102:103], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], tba, v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], tma, v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf5,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], exec, v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x01,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x83,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xef,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xfa,0x07]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[6:7]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x1a,0x00]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[8:9]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x22,0x00]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[102:103]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x9a,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], flat_scratch
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xa2,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xaa,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], tba
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xb2,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], tma
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xba,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xea,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], exec
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xfa,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], 0
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x02,0x02]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -1
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x06,0x03]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xc2,0x03]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xde,0x03]
-
-v_fma_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x24]
-
-v_fma_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x44]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x84]
-
-v_fma_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_fma_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// CHECK: [0x05,0x01,0x98,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// CHECK: [0x05,0x02,0x98,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// CHECK: [0x05,0x04,0x98,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// CHECK: [0x05,0x07,0x98,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// CHECK: [0x05,0x08,0x98,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x14]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_lerp_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x0e,0x04]
-
-v_lerp_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x9a,0xd2,0x01,0x05,0x0e,0x04]
-
-v_lerp_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0xff,0x05,0x0e,0x04]
-
-v_lerp_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x67,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x68,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x69,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x80,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xff,0x0f,0x04]
-
-v_lerp_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x0c,0x04]
-
-v_lerp_u8 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_lerp_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_lerp_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_lerp_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_lerp_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_lerp_u8 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_lerp_u8 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_lerp_u8 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_lerp_u8 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_lerp_u8 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_lerp_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_lerp_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_lerp_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xff,0x0c,0x04]
-
-v_lerp_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x01,0x0d,0x04]
-
-v_lerp_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x83,0x0d,0x04]
-
-v_lerp_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xfe,0x07]
-
-v_lerp_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x0e,0x00]
-
-v_lerp_u8 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x9e,0x01]
-
-v_lerp_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xa2,0x01]
-
-v_lerp_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xa6,0x01]
-
-v_lerp_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xaa,0x01]
-
-v_lerp_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xae,0x01]
-
-v_lerp_u8 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xb2,0x01]
-
-v_lerp_u8 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xb6,0x01]
-
-v_lerp_u8 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xba,0x01]
-
-v_lerp_u8 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xbe,0x01]
-
-v_lerp_u8 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xee,0x01]
-
-v_lerp_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xf2,0x01]
-
-v_lerp_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xfa,0x01]
-
-v_lerp_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xfe,0x01]
-
-v_lerp_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x02]
-
-v_lerp_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x06,0x03]
-
-v_alignbit_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x0e,0x04]
-
-v_alignbit_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x9c,0xd2,0x01,0x05,0x0e,0x04]
-
-v_alignbit_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0xff,0x05,0x0e,0x04]
-
-v_alignbit_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x67,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x68,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x69,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x80,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xff,0x0f,0x04]
-
-v_alignbit_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xff,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x01,0x0d,0x04]
-
-v_alignbit_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x83,0x0d,0x04]
-
-v_alignbit_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_alignbit_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xef,0x0d,0x04]
-
-v_alignbit_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xfe,0x07]
-
-v_alignbit_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x0e,0x00]
-
-v_alignbit_b32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x9e,0x01]
-
-v_alignbit_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xa2,0x01]
-
-v_alignbit_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xa6,0x01]
-
-v_alignbit_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xaa,0x01]
-
-v_alignbit_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xae,0x01]
-
-v_alignbit_b32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xb2,0x01]
-
-v_alignbit_b32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xb6,0x01]
-
-v_alignbit_b32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xba,0x01]
-
-v_alignbit_b32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xbe,0x01]
-
-v_alignbit_b32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xee,0x01]
-
-v_alignbit_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xf2,0x01]
-
-v_alignbit_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xfa,0x01]
-
-v_alignbit_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xfe,0x01]
-
-v_alignbit_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x02,0x02]
-
-v_alignbit_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x06,0x03]
-
-v_alignbit_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xc2,0x03]
-
-v_alignbit_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xde,0x03]
-
-v_alignbyte_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x9e,0xd2,0x01,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0xff,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x67,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x68,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x69,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x80,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xff,0x0f,0x04]
-
-v_alignbyte_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xff,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x01,0x0d,0x04]
-
-v_alignbyte_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x83,0x0d,0x04]
-
-v_alignbyte_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_alignbyte_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xef,0x0d,0x04]
-
-v_alignbyte_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xfe,0x07]
-
-v_alignbyte_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x0e,0x00]
-
-v_alignbyte_b32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x9e,0x01]
-
-v_alignbyte_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xa2,0x01]
-
-v_alignbyte_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xa6,0x01]
-
-v_alignbyte_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xaa,0x01]
-
-v_alignbyte_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xae,0x01]
-
-v_alignbyte_b32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xb2,0x01]
-
-v_alignbyte_b32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xb6,0x01]
-
-v_alignbyte_b32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xba,0x01]
-
-v_alignbyte_b32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xbe,0x01]
-
-v_alignbyte_b32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xee,0x01]
-
-v_alignbyte_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xf2,0x01]
-
-v_alignbyte_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xfa,0x01]
-
-v_alignbyte_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xfe,0x01]
-
-v_alignbyte_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x02,0x02]
-
-v_alignbyte_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x06,0x03]
-
-v_alignbyte_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xc2,0x03]
-
-v_alignbyte_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xde,0x03]
-
-v_mullit_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x68,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x69,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_mullit_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mullit_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mullit_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mullit_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_mullit_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_mullit_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mullit_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mullit_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_mullit_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_mullit_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_mullit_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_mullit_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_mullit_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mullit_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mullit_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mullit_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mullit_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mullit_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_mullit_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xef,0x0d,0x04]
-
-v_mullit_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xfe,0x07]
-
-v_mullit_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x00]
-
-v_mullit_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x9e,0x01]
-
-v_mullit_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xa2,0x01]
-
-v_mullit_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xa6,0x01]
-
-v_mullit_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mullit_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xae,0x01]
-
-v_mullit_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xb2,0x01]
-
-v_mullit_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xb6,0x01]
-
-v_mullit_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xba,0x01]
-
-v_mullit_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xbe,0x01]
-
-v_mullit_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xee,0x01]
-
-v_mullit_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xf2,0x01]
-
-v_mullit_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mullit_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xfe,0x01]
-
-v_mullit_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x02]
-
-v_mullit_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x06,0x03]
-
-v_mullit_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xc2,0x03]
-
-v_mullit_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xde,0x03]
-
-v_mullit_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x24]
-
-v_mullit_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x44]
-
-v_mullit_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x84]
-
-v_mullit_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_mullit_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xa0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xa0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xa0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xa0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0xa0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mullit_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_mullit_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x14]
-
-v_mullit_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_min3_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0xff,0x05,0x0e,0x04]
-
-v_min3_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x04,0x0e,0x04]
-
-v_min3_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x67,0x04,0x0e,0x04]
-
-v_min3_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x68,0x04,0x0e,0x04]
-
-v_min3_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x69,0x04,0x0e,0x04]
-
-v_min3_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_min3_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_min3_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_min3_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_min3_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_min3_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_min3_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_min3_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_min3_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_min3_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_min3_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x80,0x04,0x0e,0x04]
-
-v_min3_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_min3_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_min3_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_min3_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xff,0x0f,0x04]
-
-v_min3_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0c,0x04]
-
-v_min3_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_min3_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_min3_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_min3_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_min3_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_min3_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_min3_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_min3_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_min3_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_min3_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_min3_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_min3_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_min3_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xff,0x0c,0x04]
-
-v_min3_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x01,0x0d,0x04]
-
-v_min3_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x83,0x0d,0x04]
-
-v_min3_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_min3_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xef,0x0d,0x04]
-
-v_min3_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xfe,0x07]
-
-v_min3_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x00]
-
-v_min3_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x9e,0x01]
-
-v_min3_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xa2,0x01]
-
-v_min3_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xa6,0x01]
-
-v_min3_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xaa,0x01]
-
-v_min3_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xae,0x01]
-
-v_min3_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xb2,0x01]
-
-v_min3_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xb6,0x01]
-
-v_min3_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xba,0x01]
-
-v_min3_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xbe,0x01]
-
-v_min3_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xee,0x01]
-
-v_min3_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xf2,0x01]
-
-v_min3_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xfa,0x01]
-
-v_min3_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xfe,0x01]
-
-v_min3_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x02,0x02]
-
-v_min3_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x06,0x03]
-
-v_min3_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xc2,0x03]
-
-v_min3_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xde,0x03]
-
-v_min3_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x24]
-
-v_min3_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x44]
-
-v_min3_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x84]
-
-v_min3_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_min3_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xa2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xa2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xa2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xa2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0xa2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_min3_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x14]
-
-v_min3_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_min3_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xa4,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0xff,0x05,0x0e,0x04]
-
-v_min3_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x04,0x0e,0x04]
-
-v_min3_i32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x67,0x04,0x0e,0x04]
-
-v_min3_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x68,0x04,0x0e,0x04]
-
-v_min3_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x69,0x04,0x0e,0x04]
-
-v_min3_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_min3_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_min3_i32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_min3_i32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_min3_i32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_min3_i32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_min3_i32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_min3_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_min3_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_min3_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_min3_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x80,0x04,0x0e,0x04]
-
-v_min3_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_min3_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_min3_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_min3_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xff,0x0f,0x04]
-
-v_min3_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x0c,0x04]
-
-v_min3_i32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_min3_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_min3_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_min3_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_min3_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_min3_i32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_min3_i32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_min3_i32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_min3_i32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_min3_i32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_min3_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_min3_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_min3_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xff,0x0c,0x04]
-
-v_min3_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x01,0x0d,0x04]
-
-v_min3_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x83,0x0d,0x04]
-
-v_min3_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_min3_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xef,0x0d,0x04]
-
-v_min3_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xfe,0x07]
-
-v_min3_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x0e,0x00]
-
-v_min3_i32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x9e,0x01]
-
-v_min3_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xa2,0x01]
-
-v_min3_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xa6,0x01]
-
-v_min3_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xaa,0x01]
-
-v_min3_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xae,0x01]
-
-v_min3_i32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xb2,0x01]
-
-v_min3_i32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xb6,0x01]
-
-v_min3_i32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xba,0x01]
-
-v_min3_i32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xbe,0x01]
-
-v_min3_i32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xee,0x01]
-
-v_min3_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xf2,0x01]
-
-v_min3_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xfa,0x01]
-
-v_min3_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xfe,0x01]
-
-v_min3_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x02,0x02]
-
-v_min3_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x06,0x03]
-
-v_min3_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xc2,0x03]
-
-v_min3_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xde,0x03]
-
-v_min3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xa6,0xd2,0x01,0x05,0x0e,0x04]
-
-v_min3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0xff,0x05,0x0e,0x04]
-
-v_min3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x04,0x0e,0x04]
-
-v_min3_u32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x67,0x04,0x0e,0x04]
-
-v_min3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x68,0x04,0x0e,0x04]
-
-v_min3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x69,0x04,0x0e,0x04]
-
-v_min3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_min3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_min3_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_min3_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_min3_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_min3_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_min3_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_min3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_min3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_min3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_min3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x80,0x04,0x0e,0x04]
-
-v_min3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_min3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_min3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_min3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xff,0x0f,0x04]
-
-v_min3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x0c,0x04]
-
-v_min3_u32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_min3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_min3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_min3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_min3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_min3_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_min3_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_min3_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_min3_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_min3_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_min3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_min3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_min3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xff,0x0c,0x04]
-
-v_min3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x01,0x0d,0x04]
-
-v_min3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x83,0x0d,0x04]
-
-v_min3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_min3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xef,0x0d,0x04]
-
-v_min3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xfe,0x07]
-
-v_min3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x0e,0x00]
-
-v_min3_u32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x9e,0x01]
-
-v_min3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xa2,0x01]
-
-v_min3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xa6,0x01]
-
-v_min3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xaa,0x01]
-
-v_min3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xae,0x01]
-
-v_min3_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xb2,0x01]
-
-v_min3_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xb6,0x01]
-
-v_min3_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xba,0x01]
-
-v_min3_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xbe,0x01]
-
-v_min3_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xee,0x01]
-
-v_min3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xf2,0x01]
-
-v_min3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xfa,0x01]
-
-v_min3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xfe,0x01]
-
-v_min3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x02,0x02]
-
-v_min3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x06,0x03]
-
-v_min3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xc2,0x03]
-
-v_min3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xde,0x03]
-
-v_max3_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0xff,0x05,0x0e,0x04]
-
-v_max3_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x04,0x0e,0x04]
-
-v_max3_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x67,0x04,0x0e,0x04]
-
-v_max3_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x68,0x04,0x0e,0x04]
-
-v_max3_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x69,0x04,0x0e,0x04]
-
-v_max3_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_max3_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_max3_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_max3_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_max3_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_max3_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_max3_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_max3_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_max3_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_max3_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_max3_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x80,0x04,0x0e,0x04]
-
-v_max3_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_max3_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_max3_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_max3_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xff,0x0f,0x04]
-
-v_max3_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0c,0x04]
-
-v_max3_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_max3_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_max3_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_max3_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_max3_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_max3_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_max3_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_max3_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_max3_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_max3_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_max3_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_max3_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_max3_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xff,0x0c,0x04]
-
-v_max3_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x01,0x0d,0x04]
-
-v_max3_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x83,0x0d,0x04]
-
-v_max3_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_max3_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xef,0x0d,0x04]
-
-v_max3_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xfe,0x07]
-
-v_max3_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x00]
-
-v_max3_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x9e,0x01]
-
-v_max3_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xa2,0x01]
-
-v_max3_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xa6,0x01]
-
-v_max3_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xaa,0x01]
-
-v_max3_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xae,0x01]
-
-v_max3_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xb2,0x01]
-
-v_max3_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xb6,0x01]
-
-v_max3_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xba,0x01]
-
-v_max3_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xbe,0x01]
-
-v_max3_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xee,0x01]
-
-v_max3_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xf2,0x01]
-
-v_max3_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xfa,0x01]
-
-v_max3_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xfe,0x01]
-
-v_max3_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x02,0x02]
-
-v_max3_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x06,0x03]
-
-v_max3_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xc2,0x03]
-
-v_max3_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xde,0x03]
-
-v_max3_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x24]
-
-v_max3_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x44]
-
-v_max3_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x84]
-
-v_max3_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_max3_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xa8,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xa8,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xa8,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xa8,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0xa8,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_max3_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x14]
-
-v_max3_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_max3_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xaa,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0xff,0x05,0x0e,0x04]
-
-v_max3_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x04,0x0e,0x04]
-
-v_max3_i32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x67,0x04,0x0e,0x04]
-
-v_max3_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x68,0x04,0x0e,0x04]
-
-v_max3_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x69,0x04,0x0e,0x04]
-
-v_max3_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_max3_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_max3_i32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_max3_i32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_max3_i32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_max3_i32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_max3_i32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_max3_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_max3_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_max3_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_max3_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x80,0x04,0x0e,0x04]
-
-v_max3_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_max3_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_max3_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_max3_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xff,0x0f,0x04]
-
-v_max3_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x0c,0x04]
-
-v_max3_i32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_max3_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_max3_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_max3_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_max3_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_max3_i32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_max3_i32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_max3_i32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_max3_i32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_max3_i32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_max3_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_max3_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_max3_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xff,0x0c,0x04]
-
-v_max3_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x01,0x0d,0x04]
-
-v_max3_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x83,0x0d,0x04]
-
-v_max3_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_max3_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xef,0x0d,0x04]
-
-v_max3_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xfe,0x07]
-
-v_max3_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x0e,0x00]
-
-v_max3_i32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x9e,0x01]
-
-v_max3_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xa2,0x01]
-
-v_max3_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xa6,0x01]
-
-v_max3_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xaa,0x01]
-
-v_max3_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xae,0x01]
-
-v_max3_i32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xb2,0x01]
-
-v_max3_i32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xb6,0x01]
-
-v_max3_i32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xba,0x01]
-
-v_max3_i32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xbe,0x01]
-
-v_max3_i32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xee,0x01]
-
-v_max3_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xf2,0x01]
-
-v_max3_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xfa,0x01]
-
-v_max3_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xfe,0x01]
-
-v_max3_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x02,0x02]
-
-v_max3_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x06,0x03]
-
-v_max3_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xc2,0x03]
-
-v_max3_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xde,0x03]
-
-v_max3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xac,0xd2,0x01,0x05,0x0e,0x04]
-
-v_max3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0xff,0x05,0x0e,0x04]
-
-v_max3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x04,0x0e,0x04]
-
-v_max3_u32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x67,0x04,0x0e,0x04]
-
-v_max3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x68,0x04,0x0e,0x04]
-
-v_max3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x69,0x04,0x0e,0x04]
-
-v_max3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_max3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_max3_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_max3_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_max3_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_max3_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_max3_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_max3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_max3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_max3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_max3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x80,0x04,0x0e,0x04]
-
-v_max3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_max3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_max3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_max3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xff,0x0f,0x04]
-
-v_max3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x0c,0x04]
-
-v_max3_u32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_max3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_max3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_max3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_max3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_max3_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_max3_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_max3_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_max3_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_max3_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_max3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_max3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_max3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xff,0x0c,0x04]
-
-v_max3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x01,0x0d,0x04]
-
-v_max3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x83,0x0d,0x04]
-
-v_max3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_max3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xef,0x0d,0x04]
-
-v_max3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xfe,0x07]
-
-v_max3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x0e,0x00]
-
-v_max3_u32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x9e,0x01]
-
-v_max3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xa2,0x01]
-
-v_max3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xa6,0x01]
-
-v_max3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xaa,0x01]
-
-v_max3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xae,0x01]
-
-v_max3_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xb2,0x01]
-
-v_max3_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xb6,0x01]
-
-v_max3_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xba,0x01]
-
-v_max3_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xbe,0x01]
-
-v_max3_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xee,0x01]
-
-v_max3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xf2,0x01]
-
-v_max3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xfa,0x01]
-
-v_max3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xfe,0x01]
-
-v_max3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x02,0x02]
-
-v_max3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x06,0x03]
-
-v_max3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xc2,0x03]
-
-v_max3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xde,0x03]
-
-v_med3_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xae,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0xff,0x05,0x0e,0x04]
-
-v_med3_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x04,0x0e,0x04]
-
-v_med3_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x67,0x04,0x0e,0x04]
-
-v_med3_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x68,0x04,0x0e,0x04]
-
-v_med3_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x69,0x04,0x0e,0x04]
-
-v_med3_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_med3_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_med3_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_med3_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_med3_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_med3_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_med3_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_med3_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_med3_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_med3_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_med3_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x80,0x04,0x0e,0x04]
-
-v_med3_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_med3_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_med3_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_med3_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xff,0x0f,0x04]
-
-v_med3_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0c,0x04]
-
-v_med3_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_med3_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_med3_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_med3_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_med3_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_med3_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_med3_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_med3_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_med3_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_med3_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_med3_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_med3_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_med3_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xff,0x0c,0x04]
-
-v_med3_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x01,0x0d,0x04]
-
-v_med3_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x83,0x0d,0x04]
-
-v_med3_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_med3_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xef,0x0d,0x04]
-
-v_med3_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xfe,0x07]
-
-v_med3_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x00]
-
-v_med3_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x9e,0x01]
-
-v_med3_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xa2,0x01]
-
-v_med3_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xa6,0x01]
-
-v_med3_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xaa,0x01]
-
-v_med3_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xae,0x01]
-
-v_med3_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xb2,0x01]
-
-v_med3_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xb6,0x01]
-
-v_med3_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xba,0x01]
-
-v_med3_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xbe,0x01]
-
-v_med3_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xee,0x01]
-
-v_med3_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xf2,0x01]
-
-v_med3_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xfa,0x01]
-
-v_med3_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xfe,0x01]
-
-v_med3_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x02,0x02]
-
-v_med3_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x06,0x03]
-
-v_med3_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xc2,0x03]
-
-v_med3_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xde,0x03]
-
-v_med3_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x24]
-
-v_med3_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x44]
-
-v_med3_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x84]
-
-v_med3_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_med3_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xae,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xae,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xae,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xae,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0xae,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_med3_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x14]
-
-v_med3_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_med3_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xb0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0xff,0x05,0x0e,0x04]
-
-v_med3_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x04,0x0e,0x04]
-
-v_med3_i32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x67,0x04,0x0e,0x04]
-
-v_med3_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x68,0x04,0x0e,0x04]
-
-v_med3_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x69,0x04,0x0e,0x04]
-
-v_med3_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_med3_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_med3_i32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_med3_i32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_med3_i32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_med3_i32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_med3_i32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_med3_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_med3_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_med3_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_med3_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x80,0x04,0x0e,0x04]
-
-v_med3_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_med3_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_med3_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_med3_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xff,0x0f,0x04]
-
-v_med3_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x0c,0x04]
-
-v_med3_i32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_med3_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_med3_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_med3_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_med3_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_med3_i32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_med3_i32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_med3_i32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_med3_i32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_med3_i32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_med3_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_med3_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_med3_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xff,0x0c,0x04]
-
-v_med3_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x01,0x0d,0x04]
-
-v_med3_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x83,0x0d,0x04]
-
-v_med3_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_med3_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xef,0x0d,0x04]
-
-v_med3_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xfe,0x07]
-
-v_med3_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x0e,0x00]
-
-v_med3_i32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x9e,0x01]
-
-v_med3_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xa2,0x01]
-
-v_med3_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xa6,0x01]
-
-v_med3_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xaa,0x01]
-
-v_med3_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xae,0x01]
-
-v_med3_i32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xb2,0x01]
-
-v_med3_i32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xb6,0x01]
-
-v_med3_i32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xba,0x01]
-
-v_med3_i32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xbe,0x01]
-
-v_med3_i32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xee,0x01]
-
-v_med3_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xf2,0x01]
-
-v_med3_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xfa,0x01]
-
-v_med3_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xfe,0x01]
-
-v_med3_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x02,0x02]
-
-v_med3_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x06,0x03]
-
-v_med3_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xc2,0x03]
-
-v_med3_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xde,0x03]
-
-v_med3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xb2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_med3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0xff,0x05,0x0e,0x04]
-
-v_med3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x04,0x0e,0x04]
-
-v_med3_u32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x67,0x04,0x0e,0x04]
-
-v_med3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x68,0x04,0x0e,0x04]
-
-v_med3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x69,0x04,0x0e,0x04]
-
-v_med3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_med3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_med3_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_med3_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_med3_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_med3_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_med3_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_med3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_med3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_med3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_med3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x80,0x04,0x0e,0x04]
-
-v_med3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_med3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_med3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_med3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xff,0x0f,0x04]
-
-v_med3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x0c,0x04]
-
-v_med3_u32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_med3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_med3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_med3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_med3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_med3_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_med3_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_med3_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_med3_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_med3_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_med3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_med3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_med3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xff,0x0c,0x04]
-
-v_med3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x01,0x0d,0x04]
-
-v_med3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x83,0x0d,0x04]
-
-v_med3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_med3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xef,0x0d,0x04]
-
-v_med3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xfe,0x07]
-
-v_med3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x0e,0x00]
-
-v_med3_u32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x9e,0x01]
-
-v_med3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xa2,0x01]
-
-v_med3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xa6,0x01]
-
-v_med3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xaa,0x01]
-
-v_med3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xae,0x01]
-
-v_med3_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xb2,0x01]
-
-v_med3_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xb6,0x01]
-
-v_med3_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xba,0x01]
-
-v_med3_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xbe,0x01]
-
-v_med3_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xee,0x01]
-
-v_med3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xf2,0x01]
-
-v_med3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xfa,0x01]
-
-v_med3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xfe,0x01]
-
-v_med3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x02,0x02]
-
-v_med3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x06,0x03]
-
-v_med3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xc2,0x03]
-
-v_med3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xde,0x03]
-
-v_sad_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x0e,0x04]
-
-v_sad_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xb4,0xd2,0x01,0x05,0x0e,0x04]
-
-v_sad_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0xff,0x05,0x0e,0x04]
-
-v_sad_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x04,0x0e,0x04]
-
-v_sad_u8 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x67,0x04,0x0e,0x04]
-
-v_sad_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x68,0x04,0x0e,0x04]
-
-v_sad_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x69,0x04,0x0e,0x04]
-
-v_sad_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_sad_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_sad_u8 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_sad_u8 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_sad_u8 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_sad_u8 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_sad_u8 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_sad_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_sad_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_sad_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_sad_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x80,0x04,0x0e,0x04]
-
-v_sad_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_sad_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xff,0x0f,0x04]
-
-v_sad_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x0c,0x04]
-
-v_sad_u8 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_sad_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_sad_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_sad_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_sad_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_sad_u8 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_sad_u8 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_sad_u8 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_sad_u8 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_sad_u8 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_sad_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_sad_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_sad_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xff,0x0c,0x04]
-
-v_sad_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x01,0x0d,0x04]
-
-v_sad_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x83,0x0d,0x04]
-
-v_sad_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xfe,0x07]
-
-v_sad_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x0e,0x00]
-
-v_sad_u8 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x9e,0x01]
-
-v_sad_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xa2,0x01]
-
-v_sad_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xa6,0x01]
-
-v_sad_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xaa,0x01]
-
-v_sad_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xae,0x01]
-
-v_sad_u8 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xb2,0x01]
-
-v_sad_u8 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xb6,0x01]
-
-v_sad_u8 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xba,0x01]
-
-v_sad_u8 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xbe,0x01]
-
-v_sad_u8 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xee,0x01]
-
-v_sad_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xf2,0x01]
-
-v_sad_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xfa,0x01]
-
-v_sad_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xfe,0x01]
-
-v_sad_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x02,0x02]
-
-v_sad_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x06,0x03]
-
-v_sad_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xc2,0x03]
-
-v_sad_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xde,0x03]
-
-v_sad_hi_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xb6,0xd2,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0xff,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x67,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x68,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x69,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x80,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xff,0x0f,0x04]
-
-v_sad_hi_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xff,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x01,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x83,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xfe,0x07]
-
-v_sad_hi_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x0e,0x00]
-
-v_sad_hi_u8 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x9e,0x01]
-
-v_sad_hi_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xa2,0x01]
-
-v_sad_hi_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xa6,0x01]
-
-v_sad_hi_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xaa,0x01]
-
-v_sad_hi_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xae,0x01]
-
-v_sad_hi_u8 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xb2,0x01]
-
-v_sad_hi_u8 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xb6,0x01]
-
-v_sad_hi_u8 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xba,0x01]
-
-v_sad_hi_u8 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xbe,0x01]
-
-v_sad_hi_u8 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xee,0x01]
-
-v_sad_hi_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xf2,0x01]
-
-v_sad_hi_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xfa,0x01]
-
-v_sad_hi_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xfe,0x01]
-
-v_sad_hi_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x02,0x02]
-
-v_sad_hi_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x06,0x03]
-
-v_sad_hi_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xc2,0x03]
-
-v_sad_hi_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xde,0x03]
-
-v_sad_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xb8,0xd2,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0xff,0x05,0x0e,0x04]
-
-v_sad_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x04,0x0e,0x04]
-
-v_sad_u16 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x67,0x04,0x0e,0x04]
-
-v_sad_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x68,0x04,0x0e,0x04]
-
-v_sad_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x69,0x04,0x0e,0x04]
-
-v_sad_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_sad_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_sad_u16 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_sad_u16 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_sad_u16 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_sad_u16 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_sad_u16 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_sad_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_sad_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_sad_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_sad_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x80,0x04,0x0e,0x04]
-
-v_sad_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_sad_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xff,0x0f,0x04]
-
-v_sad_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x0c,0x04]
-
-v_sad_u16 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_sad_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_sad_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_sad_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_sad_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_sad_u16 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_sad_u16 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_sad_u16 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_sad_u16 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_sad_u16 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_sad_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_sad_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_sad_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xff,0x0c,0x04]
-
-v_sad_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x01,0x0d,0x04]
-
-v_sad_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x83,0x0d,0x04]
-
-v_sad_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xfe,0x07]
-
-v_sad_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x0e,0x00]
-
-v_sad_u16 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x9e,0x01]
-
-v_sad_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xa2,0x01]
-
-v_sad_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xa6,0x01]
-
-v_sad_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xaa,0x01]
-
-v_sad_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xae,0x01]
-
-v_sad_u16 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xb2,0x01]
-
-v_sad_u16 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xb6,0x01]
-
-v_sad_u16 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xba,0x01]
-
-v_sad_u16 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xbe,0x01]
-
-v_sad_u16 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xee,0x01]
-
-v_sad_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xf2,0x01]
-
-v_sad_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xfa,0x01]
-
-v_sad_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xfe,0x01]
-
-v_sad_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x02,0x02]
-
-v_sad_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x06,0x03]
-
-v_sad_u16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xc2,0x03]
-
-v_sad_u16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xde,0x03]
-
-v_sad_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xba,0xd2,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0xff,0x05,0x0e,0x04]
-
-v_sad_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x04,0x0e,0x04]
-
-v_sad_u32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x67,0x04,0x0e,0x04]
-
-v_sad_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x68,0x04,0x0e,0x04]
-
-v_sad_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x69,0x04,0x0e,0x04]
-
-v_sad_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_sad_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_sad_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_sad_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_sad_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_sad_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_sad_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_sad_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_sad_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_sad_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_sad_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x80,0x04,0x0e,0x04]
-
-v_sad_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_sad_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_sad_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_sad_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xff,0x0f,0x04]
-
-v_sad_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x0c,0x04]
-
-v_sad_u32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_sad_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_sad_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_sad_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_sad_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_sad_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_sad_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_sad_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_sad_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_sad_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_sad_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_sad_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_sad_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xff,0x0c,0x04]
-
-v_sad_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x01,0x0d,0x04]
-
-v_sad_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x83,0x0d,0x04]
-
-v_sad_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_sad_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xef,0x0d,0x04]
-
-v_sad_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xfe,0x07]
-
-v_sad_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x0e,0x00]
-
-v_sad_u32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x9e,0x01]
-
-v_sad_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xa2,0x01]
-
-v_sad_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xa6,0x01]
-
-v_sad_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xaa,0x01]
-
-v_sad_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xae,0x01]
-
-v_sad_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xb2,0x01]
-
-v_sad_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xb6,0x01]
-
-v_sad_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xba,0x01]
-
-v_sad_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xbe,0x01]
-
-v_sad_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xee,0x01]
-
-v_sad_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xf2,0x01]
-
-v_sad_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xfa,0x01]
-
-v_sad_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xfe,0x01]
-
-v_sad_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x02,0x02]
-
-v_sad_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x06,0x03]
-
-v_sad_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xc2,0x03]
-
-v_sad_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xde,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xbc,0xd2,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0xff,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x67,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x68,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x69,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x80,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xff,0x0f,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xff,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x01,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x83,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xef,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xfe,0x07]
-
-v_cvt_pk_u8_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x0e,0x00]
-
-v_cvt_pk_u8_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x9e,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xa2,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xa6,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xaa,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xae,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xb2,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xb6,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xba,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xbe,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xee,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xf2,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xfa,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xfe,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x02,0x02]
-
-v_cvt_pk_u8_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x06,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xc2,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0xff,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x67,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x68,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x69,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xff,0x0f,0x04]
-
-v_div_fixup_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xff,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xfe,0x07]
-
-v_div_fixup_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x00]
-
-v_div_fixup_f32 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x9e,0x01]
-
-v_div_fixup_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xa2,0x01]
-
-v_div_fixup_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xa6,0x01]
-
-v_div_fixup_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xae,0x01]
-
-v_div_fixup_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xb2,0x01]
-
-v_div_fixup_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xb6,0x01]
-
-v_div_fixup_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xba,0x01]
-
-v_div_fixup_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xbe,0x01]
-
-v_div_fixup_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xee,0x01]
-
-v_div_fixup_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xf2,0x01]
-
-v_div_fixup_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xfe,0x01]
-
-v_div_fixup_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xbe,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xbe,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xbe,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xbe,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0xbe,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_div_fixup_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x14]
-
-v_div_fixup_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0xfe,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[2:3], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x02,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[4:5], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x04,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[102:103], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x66,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x68,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], tba, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], tma, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x7a,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], exec, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xfd,0x0f,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[4:5], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x09,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[6:7], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x0d,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[102:103], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], tba, v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], tma, v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xf5,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], exec, v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xfa,0x07]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[6:7]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x1a,0x00]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[8:9]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x22,0x00]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[102:103]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x9a,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], flat_scratch
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xa2,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], tba
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xb2,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], tma
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xba,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xea,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], exec
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -1
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// CHECK: [0x05,0x01,0xc0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// CHECK: [0x05,0x02,0xc0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// CHECK: [0x05,0x04,0xc0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// CHECK: [0x05,0x07,0xc0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// CHECK: [0x05,0x08,0xc0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x14]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_lshl_b64 v[5:6], v[1:2], v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshl_b64 v[254:255], v[1:2], v2
-// CHECK: [0xfe,0x00,0xc2,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshl_b64 v[5:6], v[254:255], v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0xfe,0x05,0x02,0x00]
-
-v_lshl_b64 v[5:6], s[2:3], v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x02,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], s[4:5], v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x04,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], s[102:103], v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x66,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], flat_scratch, v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x68,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], vcc, v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], tba, v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x6c,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], tma, v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x6e,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], ttmp[10:11], v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x7a,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], exec, v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], 0, v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], -1, v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], 0.5, v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], -4.0, v2
-// CHECK: [0x05,0x00,0xc2,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], v255
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xff,0x03,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], s2
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0x05,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], s103
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xcf,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], flat_scratch_lo
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd1,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], flat_scratch_hi
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd3,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], vcc_lo
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], vcc_hi
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd7,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], tba_lo
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd9,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], tba_hi
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xdb,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], tma_lo
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xdd,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], tma_hi
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xdf,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], ttmp11
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xf7,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], m0
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xf9,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], exec_lo
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], exec_hi
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xff,0x00,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshl_b64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xef,0x01,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshr_b64 v[254:255], v[1:2], v2
-// CHECK: [0xfe,0x00,0xc4,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshr_b64 v[5:6], v[254:255], v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0xfe,0x05,0x02,0x00]
-
-v_lshr_b64 v[5:6], s[2:3], v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x02,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], s[4:5], v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x04,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], s[102:103], v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x66,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], flat_scratch, v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x68,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], vcc, v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], tba, v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x6c,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], tma, v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x6e,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], ttmp[10:11], v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x7a,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], exec, v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], 0, v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], -1, v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], 0.5, v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], -4.0, v2
-// CHECK: [0x05,0x00,0xc4,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], v255
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xff,0x03,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], s2
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0x05,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], s103
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xcf,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], flat_scratch_lo
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd1,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], flat_scratch_hi
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd3,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], vcc_lo
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], vcc_hi
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd7,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], tba_lo
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd9,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], tba_hi
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xdb,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], tma_lo
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xdd,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], tma_hi
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xdf,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], ttmp11
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xf7,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], m0
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xf9,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], exec_lo
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], exec_hi
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xff,0x00,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshr_b64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xef,0x01,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashr_i64 v[254:255], v[1:2], v2
-// CHECK: [0xfe,0x00,0xc6,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashr_i64 v[5:6], v[254:255], v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0xfe,0x05,0x02,0x00]
-
-v_ashr_i64 v[5:6], s[2:3], v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x02,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], s[4:5], v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x04,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], s[102:103], v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x66,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], flat_scratch, v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x68,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], vcc, v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], tba, v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x6c,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], tma, v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x6e,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], ttmp[10:11], v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x7a,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], exec, v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], 0, v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x80,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], -1, v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], 0.5, v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], -4.0, v2
-// CHECK: [0x05,0x00,0xc6,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], v255
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xff,0x03,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], s2
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0x05,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], s103
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xcf,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], flat_scratch_lo
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd1,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], flat_scratch_hi
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd3,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], vcc_lo
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], vcc_hi
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd7,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], tba_lo
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd9,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], tba_hi
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xdb,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], tma_lo
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xdd,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], tma_hi
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xdf,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], ttmp11
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xf7,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], m0
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xf9,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], exec_lo
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], exec_hi
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xff,0x00,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0x01,0x01,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0x83,0x01,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ashr_i64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xef,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0xc8,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0xfe,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x02,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x04,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], s[102:103], v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x66,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x68,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x6a,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], tba, v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x6c,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], tma, v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x6e,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], ttmp[10:11], v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x7a,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x7e,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x80,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0xc1,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0xf0,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0xf7,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xfd,0x03,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x09,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x0d,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[102:103]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xcd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xd1,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xd5,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], tba
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xd9,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], tma
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xdd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], ttmp[10:11]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xf5,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xfd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x01,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x83,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xe1,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xef,0x01,0x00]
-
-v_add_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x20]
-
-v_add_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x40]
-
-v_add_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x60]
-
-v_add_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0xc8,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0xc8,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0xc8,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x08,0xc8,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x08]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x10]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x18]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0xca,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0xfe,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x02,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x04,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], s[102:103], v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x66,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], tba, v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], tma, v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], ttmp[10:11], v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x7a,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xfd,0x03,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x09,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x0d,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[102:103]
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], tba
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], tma
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], ttmp[10:11]
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xf5,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x20]
-
-v_mul_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x40]
-
-v_mul_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x60]
-
-v_mul_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0xca,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0xca,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0xca,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x08,0xca,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x08]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x10]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x18]
-
-v_min_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0xcc,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0xfe,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x02,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x04,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], s[102:103], v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x66,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x68,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x6a,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], tba, v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x6c,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], tma, v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x6e,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], ttmp[10:11], v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x7a,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x7e,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x80,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0xc1,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0xf0,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0xf7,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xfd,0x03,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x09,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x0d,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[102:103]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xcd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xd1,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xd5,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], tba
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xd9,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], tma
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xdd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], ttmp[10:11]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xf5,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xfd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x01,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x83,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xe1,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xef,0x01,0x00]
-
-v_min_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x20]
-
-v_min_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x40]
-
-v_min_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x60]
-
-v_min_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0xcc,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0xcc,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0xcc,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x08,0xcc,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x08]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x10]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x18]
-
-v_max_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0xce,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0xfe,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x02,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x04,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], s[102:103], v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x66,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x68,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x6a,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], tba, v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x6c,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], tma, v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x6e,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], ttmp[10:11], v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x7a,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x7e,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x80,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0xc1,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0xf0,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0xf7,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xfd,0x03,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x09,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x0d,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[102:103]
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xcd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xd1,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xd5,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], tba
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xd9,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], tma
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xdd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], ttmp[10:11]
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xf5,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xfd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x01,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x83,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xe1,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xef,0x01,0x00]
-
-v_max_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x20]
-
-v_max_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x40]
-
-v_max_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x60]
-
-v_max_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0xce,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0xce,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0xce,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x08,0xce,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x08]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x10]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x18]
-
-v_ldexp_f64 v[5:6], v[1:2], v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[254:255], v[1:2], v2
-// CHECK: [0xfe,0x00,0xd0,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[254:255], v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0xfe,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[2:3], v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x02,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[4:5], v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x04,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[102:103], v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x66,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], flat_scratch, v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x68,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], vcc, v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], tba, v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x6c,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], tma, v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x6e,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], ttmp[10:11], v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x7a,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], exec, v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], 0, v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x80,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], -1, v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], 0.5, v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], -4.0, v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v255
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xff,0x03,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], s2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], s103
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], flat_scratch_lo
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd1,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], flat_scratch_hi
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd3,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], vcc_lo
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], vcc_hi
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], tba_lo
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd9,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], tba_hi
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xdb,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], tma_lo
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xdd,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], tma_hi
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xdf,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], ttmp11
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xf7,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], m0
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], exec_lo
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], exec_hi
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xff,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x01,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x83,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xef,0x01,0x00]
-
-v_ldexp_f64 v[5:6], -v[1:2], v2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x20]
-
-v_ldexp_f64 v[5:6], |v[1:2]|, v2
-// CHECK: [0x05,0x01,0xd0,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 clamp
-// CHECK: [0x05,0x08,0xd0,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 mul:2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x08]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 mul:4
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x10]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 div:2
-// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x18]
-
-v_mul_lo_u32 v5, v1, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u32 v255, v1, v2
-// CHECK: [0xff,0x00,0xd2,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u32 v5, v255, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_lo_u32 v5, s1, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, s103, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, m0, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, 0, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, -1, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0xd2,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, v1, v255
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_lo_u32 v5, v1, s2
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, s103
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, m0
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, 0
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, -1
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32 v255, v1, v2
-// CHECK: [0xff,0x00,0xd4,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32 v5, v255, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_hi_u32 v5, s1, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, s103, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, m0, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, 0, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, -1, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0xd4,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, v1, v255
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_hi_u32 v5, v1, s2
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, s103
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, m0
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, 0
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, -1
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_lo_i32 v5, v1, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_lo_i32 v255, v1, v2
-// CHECK: [0xff,0x00,0xd6,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_lo_i32 v5, v255, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_lo_i32 v5, s1, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, s103, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, m0, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, 0, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, -1, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0xd6,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_lo_i32 v5, v1, v255
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_lo_i32 v5, v1, s2
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, s103
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, m0
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_lo_i32 v5, v1, 0
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_lo_i32 v5, v1, -1
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_lo_i32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_lo_i32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32 v255, v1, v2
-// CHECK: [0xff,0x00,0xd8,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32 v5, v255, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_hi_i32 v5, s1, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, s103, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x68,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x69,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, m0, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, 0, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, -1, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0xd8,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, v1, v255
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_hi_i32 v5, v1, s2
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, s103
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd1,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd3,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, m0
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, 0
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, -1
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xef,0x01,0x00]
-
-v_div_scale_f32 v5, vcc, v1, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f32 v255, vcc, v1, v2, v3
-// CHECK: [0xff,0x6a,0xda,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, v255, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0xff,0x05,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, s1, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, s103, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x67,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x68,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x69,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, vcc_lo, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, vcc_hi, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, tba_lo, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, tba_hi, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, tma_lo, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, tma_hi, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, ttmp11, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, m0, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, exec_lo, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, exec_hi, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, 0, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x80,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, -1, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, 0.5, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, -4.0, v2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, v1, v255, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xff,0x0f,0x04]
-
-v_div_scale_f32 v5, vcc, v1, s2, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, s103, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, vcc_lo, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, vcc_hi, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, tba_lo, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, tba_hi, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, tma_lo, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, tma_hi, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, ttmp11, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, m0, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, exec_lo, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, exec_hi, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xff,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, 0, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x01,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, -1, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x83,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, 0.5, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, -4.0, v3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xef,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, v2, v255
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xfe,0x07]
-
-v_div_scale_f32 v5, vcc, v1, v2, s3
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x0e,0x00]
-
-v_div_scale_f32 v5, vcc, v1, v2, s103
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x9e,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xa2,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xa6,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, vcc_lo
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xaa,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, vcc_hi
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xae,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, tba_lo
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xb2,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, tba_hi
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xb6,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, tma_lo
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xba,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, tma_hi
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xbe,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, ttmp11
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xee,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, m0
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xf2,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, exec_lo
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xfa,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, exec_hi
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xfe,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, 0
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x02,0x02]
-
-v_div_scale_f32 v5, vcc, v1, v2, -1
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x06,0x03]
-
-v_div_scale_f32 v5, vcc, v1, v2, 0.5
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xc2,0x03]
-
-v_div_scale_f32 v5, vcc, v1, v2, -4.0
-// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xde,0x03]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f64 v[254:255], vcc, v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x6a,0xdc,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0xfe,0x05,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, s[2:3], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x02,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, s[4:5], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x04,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, s[102:103], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x66,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, flat_scratch, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x68,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, tba, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, tma, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, ttmp[10:11], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x7a,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, exec, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x80,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xfd,0x0f,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], s[4:5], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x09,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], s[6:7], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x0d,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], s[102:103], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], flat_scratch, v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], tba, v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], tma, v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], ttmp[10:11], v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xf5,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], exec, v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x01,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x83,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xef,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xfa,0x07]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[6:7]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x1a,0x00]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[8:9]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x22,0x00]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[102:103]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x9a,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], flat_scratch
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xa2,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xaa,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], tba
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xb2,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], tma
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xba,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], ttmp[10:11]
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xea,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], exec
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xfa,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x02,0x02]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -1
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x06,0x03]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xc2,0x03]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xde,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0xff,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x80,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0xff,0x0f,0x04]
-
-v_div_fmas_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x01,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x83,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0xef,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0xfe,0x07]
-
-v_div_fmas_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x02,0x02]
-
-v_div_fmas_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x06,0x03]
-
-v_div_fmas_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0xc2,0x03]
-
-v_div_fmas_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x24]
-
-v_div_fmas_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x44]
-
-v_div_fmas_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x84]
-
-v_div_fmas_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_div_fmas_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xde,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xde,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xde,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xde,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x08,0xde,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_div_fmas_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x14]
-
-v_div_fmas_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0xfe,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x80,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0xfd,0x0f,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x01,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x83,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0xef,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0xfa,0x07]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0xaa,0x01]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x02,0x02]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -1
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x06,0x03]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0xc2,0x03]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x24]
-
-v_div_fmas_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x44]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x84]
-
-v_div_fmas_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_div_fmas_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// CHECK: [0x05,0x01,0xe0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// CHECK: [0x05,0x02,0xe0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// CHECK: [0x05,0x04,0xe0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// CHECK: [0x05,0x07,0xe0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// CHECK: [0x05,0x08,0xe0,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x0c]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x14]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x1c]
-
-v_msad_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_msad_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xe2,0xd2,0x01,0x05,0x0e,0x04]
-
-v_msad_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0xff,0x05,0x0e,0x04]
-
-v_msad_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x04,0x0e,0x04]
-
-v_msad_u8 v5, s103, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x67,0x04,0x0e,0x04]
-
-v_msad_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x68,0x04,0x0e,0x04]
-
-v_msad_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x69,0x04,0x0e,0x04]
-
-v_msad_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_msad_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_msad_u8 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_msad_u8 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_msad_u8 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_msad_u8 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_msad_u8 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_msad_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_msad_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_msad_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_msad_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x80,0x04,0x0e,0x04]
-
-v_msad_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_msad_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xff,0x0f,0x04]
-
-v_msad_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x0c,0x04]
-
-v_msad_u8 v5, v1, s103, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_msad_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_msad_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_msad_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_msad_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_msad_u8 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_msad_u8 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_msad_u8 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_msad_u8 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_msad_u8 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_msad_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_msad_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_msad_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xff,0x0c,0x04]
-
-v_msad_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x01,0x0d,0x04]
-
-v_msad_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x83,0x0d,0x04]
-
-v_msad_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xfe,0x07]
-
-v_msad_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x0e,0x00]
-
-v_msad_u8 v5, v1, v2, s103
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x9e,0x01]
-
-v_msad_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xa2,0x01]
-
-v_msad_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xa6,0x01]
-
-v_msad_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xaa,0x01]
-
-v_msad_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xae,0x01]
-
-v_msad_u8 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xb2,0x01]
-
-v_msad_u8 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xb6,0x01]
-
-v_msad_u8 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xba,0x01]
-
-v_msad_u8 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xbe,0x01]
-
-v_msad_u8 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xee,0x01]
-
-v_msad_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xf2,0x01]
-
-v_msad_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xfa,0x01]
-
-v_msad_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xfe,0x01]
-
-v_msad_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x02,0x02]
-
-v_msad_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x06,0x03]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
-// CHECK: [0xfe,0x00,0xe4,0xd2,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0xfe,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x02,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x04,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[102:103], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x66,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x68,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], tba, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], tma, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x7a,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x80,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xff,0x0f,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], s103, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], tba_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], tba_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], tma_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], tma_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xff,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x01,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x83,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xfa,0x07]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x1a,0x00]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x22,0x00]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[102:103]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x9a,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xa2,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xaa,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, tba
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xb2,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, tma
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xba,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xea,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xfa,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x02,0x02]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
-// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x06,0x03]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
-// CHECK: [0xfe,0x00,0xe6,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0xfe,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x02,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x04,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[102:103], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x66,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x68,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], tba, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], tma, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x7a,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], s103, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], tba_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], tba_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], tma_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], tma_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xfa,0x07]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x1a,0x00]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x22,0x00]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[102:103]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x9a,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xa2,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, tba
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xb2,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, tma
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xba,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xea,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x02,0x02]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
-// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x06,0x03]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[254:255], v[1:2], v2
-// CHECK: [0xfe,0x00,0xe8,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[254:255], v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0xfe,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[2:3], v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x02,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[4:5], v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x04,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[102:103], v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x66,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], flat_scratch, v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x68,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], vcc, v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x6a,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], tba, v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x6c,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], tma, v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x6e,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], ttmp[10:11], v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x7a,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], exec, v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x7e,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], 0, v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x80,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], -1, v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0xc1,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], 0.5, v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0xf0,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], -4.0, v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0xf7,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v255
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xff,0x03,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], s2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], s103
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xcf,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_lo
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd1,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_hi
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd3,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], vcc_lo
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd5,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], vcc_hi
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd7,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], tba_lo
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd9,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], tba_hi
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xdb,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], tma_lo
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xdd,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], tma_hi
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xdf,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], ttmp11
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xf7,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], m0
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xf9,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], exec_lo
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xfd,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], exec_hi
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xff,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x01,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x83,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xe1,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xef,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], -v[1:2], v2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x20]
-
-v_trig_preop_f64 v[5:6], |v[1:2]|, v2
-// CHECK: [0x05,0x01,0xe8,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 clamp
-// CHECK: [0x05,0x08,0xe8,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 mul:2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x08]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 mul:4
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x10]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 div:2
-// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x18]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[2:3], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x02,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[4:5], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x04,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[102:103], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x66,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], flat_scratch, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x68,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], vcc, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], tba, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], tma, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], ttmp[10:11], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x7a,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], exec, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], 0, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], -1, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], s2, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], s103, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], vcc_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], vcc_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], tba_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], tba_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], tma_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], tma_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], ttmp11, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], m0, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], exec_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], exec_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], 0, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], -1, v[3:6]
-// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[254:255], s[12:13], v1, v2, v[3:4]
-// CHECK: [0xfe,0x0c,0xec,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[14:15], v1, v2, v[3:4]
-// CHECK: [0x05,0x0e,0xec,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[102:103], v1, v2, v[3:4]
-// CHECK: [0x05,0x66,0xec,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], flat_scratch, v1, v2, v[3:4]
-// CHECK: [0x05,0x68,0xec,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], vcc, v1, v2, v[3:4]
-// CHECK: [0x05,0x6a,0xec,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], tba, v1, v2, v[3:4]
-// CHECK: [0x05,0x6c,0xec,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], tma, v1, v2, v[3:4]
-// CHECK: [0x05,0x6e,0xec,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], ttmp[10:11], v1, v2, v[3:4]
-// CHECK: [0x05,0x7a,0xec,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v255, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], s1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], s103, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x68,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x69,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], tba_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], tba_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], tma_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], tma_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], ttmp11, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], m0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], 0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], -1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v255, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, s2, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, s103, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, tba_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, tba_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, tma_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, tma_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, ttmp11, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, m0, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, 0, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, -1, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, 0.5, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, -4.0, v[3:4]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xef,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[254:255]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xfa,0x07]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x1a,0x00]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x22,0x00]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[102:103]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x9a,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xa2,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xb2,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xba,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xea,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, exec
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x02,0x02]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -1
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x06,0x03]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0.5
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xc2,0x03]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -4.0
-// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xde,0x03]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[254:255], s[12:13], v1, v2, v[3:4]
-// CHECK: [0xfe,0x0c,0xee,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[14:15], v1, v2, v[3:4]
-// CHECK: [0x05,0x0e,0xee,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[102:103], v1, v2, v[3:4]
-// CHECK: [0x05,0x66,0xee,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], flat_scratch, v1, v2, v[3:4]
-// CHECK: [0x05,0x68,0xee,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], vcc, v1, v2, v[3:4]
-// CHECK: [0x05,0x6a,0xee,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], tba, v1, v2, v[3:4]
-// CHECK: [0x05,0x6c,0xee,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], tma, v1, v2, v[3:4]
-// CHECK: [0x05,0x6e,0xee,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], ttmp[10:11], v1, v2, v[3:4]
-// CHECK: [0x05,0x7a,0xee,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v255, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], s1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], s103, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x68,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x69,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], tba_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x6c,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], tba_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x6d,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], tma_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x6e,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], tma_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x6f,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], ttmp11, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x7b,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], m0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], 0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], -1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v255, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, s2, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, s103, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd1,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd3,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, tba_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd9,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, tba_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xdb,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, tma_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xdd,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, tma_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xdf,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, ttmp11, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xf7,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, m0, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, 0, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, -1, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, 0.5, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, -4.0, v[3:4]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xef,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[254:255]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xfa,0x07]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x1a,0x00]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x22,0x00]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[102:103]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x9a,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xa2,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xb2,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xba,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xea,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, exec
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x02,0x02]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -1
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x06,0x03]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0.5
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xc2,0x03]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -4.0
-// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xde,0x03]
-
-v_cmp_f_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x00,0x7c]
-
-v_cmp_f_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x00,0x7c]
-
-v_cmp_f_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x00,0x7c]
-
-v_cmp_f_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x00,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x00,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x01,0x7c]
-
-v_cmp_f_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_f_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x02,0x7c]
-
-v_cmp_lt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x02,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x02,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x03,0x7c]
-
-v_cmp_lt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_eq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x04,0x7c]
-
-v_cmp_eq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x04,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x04,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x05,0x7c]
-
-v_cmp_eq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_eq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_eq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_le_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x06,0x7c]
-
-v_cmp_le_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x06,0x7c]
-
-v_cmp_le_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x06,0x7c]
-
-v_cmp_le_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x06,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x06,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x07,0x7c]
-
-v_cmp_le_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_le_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_le_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_gt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x08,0x7c]
-
-v_cmp_gt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x08,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x08,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x09,0x7c]
-
-v_cmp_gt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_gt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_gt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x7c]
-
-v_cmp_lg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x7c]
-
-v_cmp_lg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0c,0x7c]
-
-v_cmp_ge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x0d,0x7c]
-
-v_cmp_ge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_o_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0e,0x7c]
-
-v_cmp_o_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_o_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_o_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x0f,0x7c]
-
-v_cmp_o_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_o_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_o_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_u_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x10,0x7c]
-
-v_cmp_u_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x10,0x7c]
-
-v_cmp_u_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x10,0x7c]
-
-v_cmp_u_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x10,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_u_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x10,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_u_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x11,0x7c]
-
-v_cmp_u_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_u_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_u_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x12,0x7c]
-
-v_cmp_nge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x12,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x12,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x13,0x7c]
-
-v_cmp_nge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x14,0x7c]
-
-v_cmp_nlg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x14,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x14,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x15,0x7c]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ngt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x16,0x7c]
-
-v_cmp_ngt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x16,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ngt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x16,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ngt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x17,0x7c]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ngt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nle_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x18,0x7c]
-
-v_cmp_nle_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x18,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nle_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x18,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nle_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x19,0x7c]
-
-v_cmp_nle_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nle_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nle_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_neq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x1a,0x7c]
-
-v_cmp_neq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x1a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_neq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x1a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_neq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x1b,0x7c]
-
-v_cmp_neq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_neq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_neq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x1c,0x7c]
-
-v_cmp_nlt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x1c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x1c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x1d,0x7c]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_tru_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x1e,0x7c]
-
-v_cmp_tru_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x1e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_tru_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x1e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_tru_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x1f,0x7c]
-
-v_cmp_tru_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_tru_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_tru_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x20,0x7c]
-
-v_cmpx_f_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x20,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x20,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x21,0x7c]
-
-v_cmpx_f_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x22,0x7c]
-
-v_cmpx_lt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x22,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x22,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x23,0x7c]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x24,0x7c]
-
-v_cmpx_eq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x24,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x24,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x25,0x7c]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x26,0x7c]
-
-v_cmpx_le_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x26,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x26,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x27,0x7c]
-
-v_cmpx_le_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x28,0x7c]
-
-v_cmpx_gt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x28,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x28,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x29,0x7c]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x2a,0x7c]
-
-v_cmpx_lg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x2a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x2a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x2b,0x7c]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x2c,0x7c]
-
-v_cmpx_ge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x2c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x2c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x2d,0x7c]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x2e,0x7c]
-
-v_cmpx_o_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x2e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_o_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x2e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_o_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x2f,0x7c]
-
-v_cmpx_o_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x30,0x7c]
-
-v_cmpx_u_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x30,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_u_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x30,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_u_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x31,0x7c]
-
-v_cmpx_u_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x32,0x7c]
-
-v_cmpx_nge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x32,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x32,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x33,0x7c]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x34,0x7c]
-
-v_cmpx_nlg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x34,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x34,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x35,0x7c]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x36,0x7c]
-
-v_cmpx_ngt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x36,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ngt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x36,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ngt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x37,0x7c]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x38,0x7c]
-
-v_cmpx_nle_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x38,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nle_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x38,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nle_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x39,0x7c]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x3a,0x7c]
-
-v_cmpx_neq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x3a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_neq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x3a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_neq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x3b,0x7c]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x3c,0x7c]
-
-v_cmpx_nlt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x3c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x3c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x3d,0x7c]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x3e,0x7c]
-
-v_cmpx_tru_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x3e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_tru_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x3e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_tru_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x3f,0x7c]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_f_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x40,0x7c]
-
-v_cmp_f_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x40,0x7c]
-
-v_cmp_f_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x40,0x7c]
-
-v_cmp_f_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x40,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x40,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x41,0x7c]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x42,0x7c]
-
-v_cmp_lt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x42,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x42,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x43,0x7c]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_eq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x44,0x7c]
-
-v_cmp_eq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x44,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x44,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x45,0x7c]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_le_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x46,0x7c]
-
-v_cmp_le_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x46,0x7c]
-
-v_cmp_le_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x46,0x7c]
-
-v_cmp_le_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x46,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x46,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x47,0x7c]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_gt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x48,0x7c]
-
-v_cmp_gt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x48,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x48,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x49,0x7c]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x4a,0x7c]
-
-v_cmp_lg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x4a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x4b,0x7c]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x4c,0x7c]
-
-v_cmp_ge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x4c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x4d,0x7c]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_o_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x4e,0x7c]
-
-v_cmp_o_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_o_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x4e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_o_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x4f,0x7c]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_u_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x50,0x7c]
-
-v_cmp_u_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x50,0x7c]
-
-v_cmp_u_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x50,0x7c]
-
-v_cmp_u_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x50,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_u_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x50,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_u_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x51,0x7c]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x52,0x7c]
-
-v_cmp_nge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x52,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x52,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x53,0x7c]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x54,0x7c]
-
-v_cmp_nlg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x54,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x54,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x55,0x7c]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ngt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x56,0x7c]
-
-v_cmp_ngt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x56,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ngt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x56,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ngt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x57,0x7c]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nle_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x58,0x7c]
-
-v_cmp_nle_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x58,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nle_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x58,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nle_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x59,0x7c]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_neq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x5a,0x7c]
-
-v_cmp_neq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_neq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x5a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_neq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x5b,0x7c]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x5c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x5d,0x7c]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_tru_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x5e,0x7c]
-
-v_cmp_tru_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_tru_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x5e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_tru_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x5f,0x7c]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x60,0x7c]
-
-v_cmpx_f_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x60,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x60,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x61,0x7c]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x62,0x7c]
-
-v_cmpx_lt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x62,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x62,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x63,0x7c]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x64,0x7c]
-
-v_cmpx_eq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x64,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x64,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x65,0x7c]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x66,0x7c]
-
-v_cmpx_le_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x66,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x66,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x67,0x7c]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x68,0x7c]
-
-v_cmpx_gt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x68,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x68,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x69,0x7c]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x6a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x6a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x6b,0x7c]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x6c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x6c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x6d,0x7c]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x6e,0x7c]
-
-v_cmpx_o_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x6e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_o_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x6e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_o_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x6f,0x7c]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x70,0x7c]
-
-v_cmpx_u_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x70,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_u_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x70,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_u_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x71,0x7c]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x72,0x7c]
-
-v_cmpx_nge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x72,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x72,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x73,0x7c]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x74,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x74,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x75,0x7c]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x76,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ngt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x76,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ngt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x77,0x7c]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x78,0x7c]
-
-v_cmpx_nle_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x78,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nle_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x78,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nle_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x79,0x7c]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x7a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_neq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x7a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_neq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x7b,0x7c]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x7c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x7c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x7d,0x7c]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x7e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_tru_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x7e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_tru_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x7f,0x7c]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_f_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x80,0x7c]
-
-v_cmps_f_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x80,0x7c]
-
-v_cmps_f_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x80,0x7c]
-
-v_cmps_f_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x80,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_f_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x80,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_f_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x81,0x7c]
-
-v_cmps_f_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_f_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_f_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_f_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_f_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_lt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x82,0x7c]
-
-v_cmps_lt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x82,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_lt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x82,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_lt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x83,0x7c]
-
-v_cmps_lt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_lt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_lt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_lt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_eq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x84,0x7c]
-
-v_cmps_eq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x84,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_eq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x84,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_eq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x85,0x7c]
-
-v_cmps_eq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_eq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_eq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_eq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_le_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x86,0x7c]
-
-v_cmps_le_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x86,0x7c]
-
-v_cmps_le_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x86,0x7c]
-
-v_cmps_le_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x86,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_le_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x86,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_le_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x87,0x7c]
-
-v_cmps_le_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_le_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_le_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_le_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_le_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_gt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x88,0x7c]
-
-v_cmps_gt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x88,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_gt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x88,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_gt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x89,0x7c]
-
-v_cmps_gt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_gt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_gt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_gt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_lg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8a,0x7c]
-
-v_cmps_lg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_lg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_lg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8b,0x7c]
-
-v_cmps_lg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_lg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_lg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_lg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_ge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8c,0x7c]
-
-v_cmps_ge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_ge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_ge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8d,0x7c]
-
-v_cmps_ge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_ge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_ge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_ge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_o_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8e,0x7c]
-
-v_cmps_o_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_o_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_o_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8f,0x7c]
-
-v_cmps_o_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_o_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_o_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_o_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_o_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_u_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x90,0x7c]
-
-v_cmps_u_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x90,0x7c]
-
-v_cmps_u_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x90,0x7c]
-
-v_cmps_u_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x90,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_u_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x90,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_u_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x91,0x7c]
-
-v_cmps_u_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_u_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_u_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_u_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_u_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_nge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x92,0x7c]
-
-v_cmps_nge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x92,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_nge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x92,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_nge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x93,0x7c]
-
-v_cmps_nge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_nge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_nge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_nge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_nlg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x94,0x7c]
-
-v_cmps_nlg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x94,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_nlg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x94,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_nlg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x95,0x7c]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_nlg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_nlg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_nlg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_ngt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x96,0x7c]
-
-v_cmps_ngt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x96,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_ngt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x96,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_ngt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x97,0x7c]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_ngt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_ngt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_ngt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_nle_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x98,0x7c]
-
-v_cmps_nle_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x98,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_nle_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x98,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_nle_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x99,0x7c]
-
-v_cmps_nle_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_nle_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_nle_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_nle_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_neq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9a,0x7c]
-
-v_cmps_neq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_neq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_neq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9b,0x7c]
-
-v_cmps_neq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_neq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_neq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_neq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_nlt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9c,0x7c]
-
-v_cmps_nlt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_nlt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_nlt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9d,0x7c]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_nlt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_nlt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_nlt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_tru_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9e,0x7c]
-
-v_cmps_tru_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_tru_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_tru_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9f,0x7c]
-
-v_cmps_tru_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_tru_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_tru_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_tru_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_f_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa0,0x7c]
-
-v_cmpsx_f_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_f_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_f_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa1,0x7c]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_f_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_f_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_f_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_lt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa2,0x7c]
-
-v_cmpsx_lt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_lt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_lt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa3,0x7c]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_lt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_lt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_lt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_eq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa4,0x7c]
-
-v_cmpsx_eq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_eq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_eq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa5,0x7c]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_eq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_eq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_eq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_le_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa6,0x7c]
-
-v_cmpsx_le_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_le_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_le_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa7,0x7c]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_le_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_le_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_le_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_gt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa8,0x7c]
-
-v_cmpsx_gt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_gt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_gt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa9,0x7c]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_gt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_gt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_gt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_lg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xaa,0x7c]
-
-v_cmpsx_lg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xaa,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_lg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xaa,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_lg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xab,0x7c]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_lg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_lg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_lg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_ge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xac,0x7c]
-
-v_cmpsx_ge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xac,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_ge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xac,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_ge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xad,0x7c]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_ge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_ge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_ge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_o_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xae,0x7c]
-
-v_cmpsx_o_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xae,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_o_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xae,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_o_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xaf,0x7c]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_o_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_o_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_o_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_u_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb0,0x7c]
-
-v_cmpsx_u_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_u_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_u_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb1,0x7c]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_u_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_u_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_u_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_nge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb2,0x7c]
-
-v_cmpsx_nge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_nge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_nge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb3,0x7c]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_nge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_nge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_nge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_nlg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb4,0x7c]
-
-v_cmpsx_nlg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_nlg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_nlg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb5,0x7c]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_nlg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_nlg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_nlg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_ngt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb6,0x7c]
-
-v_cmpsx_ngt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_ngt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_ngt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb7,0x7c]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_ngt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_ngt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_ngt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_nle_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb8,0x7c]
-
-v_cmpsx_nle_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_nle_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_nle_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb9,0x7c]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_nle_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_nle_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_nle_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_neq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xba,0x7c]
-
-v_cmpsx_neq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xba,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_neq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xba,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_neq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbb,0x7c]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_neq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_neq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_neq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_nlt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbc,0x7c]
-
-v_cmpsx_nlt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_nlt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_nlt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbd,0x7c]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_nlt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_nlt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_nlt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_tru_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbe,0x7c]
-
-v_cmpsx_tru_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbe,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_tru_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbe,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_tru_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbf,0x7c]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x69,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd3,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_tru_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_tru_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_tru_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_f_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc0,0x7c]
-
-v_cmps_f_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_f_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_f_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc1,0x7c]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_f_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_f_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_lt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc2,0x7c]
-
-v_cmps_lt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_lt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_lt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc3,0x7c]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_eq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc4,0x7c]
-
-v_cmps_eq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_eq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_eq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc5,0x7c]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_le_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc6,0x7c]
-
-v_cmps_le_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_le_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_le_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc7,0x7c]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_le_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_le_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_gt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc8,0x7c]
-
-v_cmps_gt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_gt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_gt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc9,0x7c]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_lg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xca,0x7c]
-
-v_cmps_lg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_lg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_lg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcb,0x7c]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_ge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xcc,0x7c]
-
-v_cmps_ge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_ge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_ge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcd,0x7c]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_o_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xce,0x7c]
-
-v_cmps_o_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xce,0x7c]
-
-v_cmps_o_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xce,0x7c]
-
-v_cmps_o_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_o_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_o_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcf,0x7c]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_o_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_o_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_u_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd0,0x7c]
-
-v_cmps_u_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_u_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_u_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd1,0x7c]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_u_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_u_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_nge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd2,0x7c]
-
-v_cmps_nge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_nge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_nge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd3,0x7c]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_nlg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd4,0x7c]
-
-v_cmps_nlg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_nlg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_nlg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd5,0x7c]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_ngt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd6,0x7c]
-
-v_cmps_ngt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_ngt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_ngt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd7,0x7c]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_nle_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd8,0x7c]
-
-v_cmps_nle_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_nle_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_nle_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd9,0x7c]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_neq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xda,0x7c]
-
-v_cmps_neq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_neq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_neq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdb,0x7c]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_nlt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xdc,0x7c]
-
-v_cmps_nlt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_nlt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_nlt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdd,0x7c]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmps_tru_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xde,0x7c]
-
-v_cmps_tru_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmps_tru_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmps_tru_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdf,0x7c]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmps_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmps_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmps_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_f_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe0,0x7c]
-
-v_cmpsx_f_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_f_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_f_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe1,0x7c]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_f_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_f_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_lt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe2,0x7c]
-
-v_cmpsx_lt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_lt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_lt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe3,0x7c]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_eq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe4,0x7c]
-
-v_cmpsx_eq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_eq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_eq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe5,0x7c]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_le_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe6,0x7c]
-
-v_cmpsx_le_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_le_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_le_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe7,0x7c]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_le_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_le_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_gt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe8,0x7c]
-
-v_cmpsx_gt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_gt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_gt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe9,0x7c]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_lg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xea,0x7c]
-
-v_cmpsx_lg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_lg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_lg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xeb,0x7c]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_ge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xec,0x7c]
-
-v_cmpsx_ge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_ge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_ge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xed,0x7c]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_o_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xee,0x7c]
-
-v_cmpsx_o_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_o_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_o_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xef,0x7c]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_o_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_o_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_u_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf0,0x7c]
-
-v_cmpsx_u_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_u_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_u_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf1,0x7c]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_u_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_u_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_nge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf2,0x7c]
-
-v_cmpsx_nge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_nge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_nge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf3,0x7c]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_nlg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf4,0x7c]
-
-v_cmpsx_nlg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_nlg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_nlg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf5,0x7c]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_ngt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf6,0x7c]
-
-v_cmpsx_ngt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_ngt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_ngt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf7,0x7c]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_nle_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf8,0x7c]
-
-v_cmpsx_nle_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_nle_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_nle_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf9,0x7c]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_neq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfa,0x7c]
-
-v_cmpsx_neq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_neq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_neq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfb,0x7c]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_nlt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfc,0x7c]
-
-v_cmpsx_nlt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_nlt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_nlt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfd,0x7c]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpsx_tru_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfe,0x7c]
-
-v_cmpsx_tru_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpsx_tru_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpsx_tru_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xff,0x7c]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x68,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd1,0x00,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpsx_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpsx_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpsx_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_f_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x00,0x7d]
-
-v_cmp_f_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x00,0x7d]
-
-v_cmp_f_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x00,0x7d]
-
-v_cmp_f_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x00,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x00,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x01,0x7d]
-
-v_cmp_f_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x00,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x02,0x7d]
-
-v_cmp_lt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x02,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x02,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x03,0x7d]
-
-v_cmp_lt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x02,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x04,0x7d]
-
-v_cmp_eq_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x04,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x04,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x05,0x7d]
-
-v_cmp_eq_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x04,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_le_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x06,0x7d]
-
-v_cmp_le_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x06,0x7d]
-
-v_cmp_le_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x06,0x7d]
-
-v_cmp_le_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x06,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x06,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x07,0x7d]
-
-v_cmp_le_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x06,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x08,0x7d]
-
-v_cmp_gt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x08,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x08,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x09,0x7d]
-
-v_cmp_gt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x08,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x7d]
-
-v_cmp_ne_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x7d]
-
-v_cmp_ne_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0c,0x7d]
-
-v_cmp_ge_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x0d,0x7d]
-
-v_cmp_ge_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_t_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0e,0x7d]
-
-v_cmp_t_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x0f,0x7d]
-
-v_cmp_t_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x20,0x7d]
-
-v_cmpx_f_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x20,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x20,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x21,0x7d]
-
-v_cmpx_f_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x20,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x22,0x7d]
-
-v_cmpx_lt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x22,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x22,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x23,0x7d]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x22,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x24,0x7d]
-
-v_cmpx_eq_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x24,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x24,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x25,0x7d]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x24,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x26,0x7d]
-
-v_cmpx_le_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x26,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x26,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x27,0x7d]
-
-v_cmpx_le_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x26,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x28,0x7d]
-
-v_cmpx_gt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x28,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x28,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x29,0x7d]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x28,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x2a,0x7d]
-
-v_cmpx_ne_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x2a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x2a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x2b,0x7d]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x2c,0x7d]
-
-v_cmpx_ge_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x2c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x2c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x2d,0x7d]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x2e,0x7d]
-
-v_cmpx_t_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x2e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x2e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x2f,0x7d]
-
-v_cmpx_t_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_f_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x40,0x7d]
-
-v_cmp_f_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x40,0x7d]
-
-v_cmp_f_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x40,0x7d]
-
-v_cmp_f_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x40,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x40,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x41,0x7d]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x40,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x42,0x7d]
-
-v_cmp_lt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x42,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x42,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x43,0x7d]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x42,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x44,0x7d]
-
-v_cmp_eq_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x44,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x44,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x45,0x7d]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x44,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_le_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x46,0x7d]
-
-v_cmp_le_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x46,0x7d]
-
-v_cmp_le_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x46,0x7d]
-
-v_cmp_le_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x46,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x46,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x47,0x7d]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x46,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x48,0x7d]
-
-v_cmp_gt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x48,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x48,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x49,0x7d]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x48,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x4a,0x7d]
-
-v_cmp_ne_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x4a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x4b,0x7d]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x4c,0x7d]
-
-v_cmp_ge_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x4c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x4d,0x7d]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_t_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x4e,0x7d]
-
-v_cmp_t_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x4e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x4f,0x7d]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x60,0x7d]
-
-v_cmpx_f_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x60,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x60,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x61,0x7d]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x62,0x7d]
-
-v_cmpx_lt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x62,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x62,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x63,0x7d]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x64,0x7d]
-
-v_cmpx_eq_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x64,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x64,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x65,0x7d]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x66,0x7d]
-
-v_cmpx_le_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x66,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x66,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x67,0x7d]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x68,0x7d]
-
-v_cmpx_gt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x68,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x68,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x69,0x7d]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x6a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x6a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x6b,0x7d]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x6c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x6c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x6d,0x7d]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0x6e,0x7d]
-
-v_cmpx_t_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0x6e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0x6e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0x6f,0x7d]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_f_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x80,0x7d]
-
-v_cmp_f_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x80,0x7d]
-
-v_cmp_f_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x80,0x7d]
-
-v_cmp_f_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x81,0x7d]
-
-v_cmp_f_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x80,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x82,0x7d]
-
-v_cmp_lt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x83,0x7d]
-
-v_cmp_lt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x82,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x84,0x7d]
-
-v_cmp_eq_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x85,0x7d]
-
-v_cmp_eq_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x84,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_le_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x86,0x7d]
-
-v_cmp_le_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x86,0x7d]
-
-v_cmp_le_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x86,0x7d]
-
-v_cmp_le_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x87,0x7d]
-
-v_cmp_le_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x86,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x88,0x7d]
-
-v_cmp_gt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x89,0x7d]
-
-v_cmp_gt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x88,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8a,0x7d]
-
-v_cmp_ne_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8b,0x7d]
-
-v_cmp_ne_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8c,0x7d]
-
-v_cmp_ge_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8d,0x7d]
-
-v_cmp_ge_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_t_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8e,0x7d]
-
-v_cmp_t_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8f,0x7d]
-
-v_cmp_t_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa0,0x7d]
-
-v_cmpx_f_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa1,0x7d]
-
-v_cmpx_f_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa2,0x7d]
-
-v_cmpx_lt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa3,0x7d]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa4,0x7d]
-
-v_cmpx_eq_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa5,0x7d]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa6,0x7d]
-
-v_cmpx_le_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa7,0x7d]
-
-v_cmpx_le_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa8,0x7d]
-
-v_cmpx_gt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa9,0x7d]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xaa,0x7d]
-
-v_cmpx_ne_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xaa,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xaa,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xab,0x7d]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xac,0x7d]
-
-v_cmpx_ge_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xac,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xac,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xad,0x7d]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xac,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, s103, v2
-// CHECK: [0x67,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xae,0x7d]
-
-v_cmpx_t_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xae,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xae,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xaf,0x7d]
-
-v_cmpx_t_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xae,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_f_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc0,0x7d]
-
-v_cmp_f_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc1,0x7d]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc2,0x7d]
-
-v_cmp_lt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc3,0x7d]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc4,0x7d]
-
-v_cmp_eq_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc5,0x7d]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_le_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc6,0x7d]
-
-v_cmp_le_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc7,0x7d]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc8,0x7d]
-
-v_cmp_gt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc9,0x7d]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xca,0x7d]
-
-v_cmp_ne_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcb,0x7d]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xca,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xcc,0x7d]
-
-v_cmp_ge_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcd,0x7d]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_t_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xce,0x7d]
-
-v_cmp_t_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xce,0x7d]
-
-v_cmp_t_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xce,0x7d]
-
-v_cmp_t_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcf,0x7d]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xce,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe0,0x7d]
-
-v_cmpx_f_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe1,0x7d]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe2,0x7d]
-
-v_cmpx_lt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe3,0x7d]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe4,0x7d]
-
-v_cmpx_eq_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe5,0x7d]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe6,0x7d]
-
-v_cmpx_le_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe7,0x7d]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe8,0x7d]
-
-v_cmpx_gt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe9,0x7d]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xea,0x7d]
-
-v_cmpx_ne_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xeb,0x7d]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xec,0x7d]
-
-v_cmpx_ge_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xed,0x7d]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, s[102:103], v[2:3]
-// CHECK: [0x66,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x68,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xee,0x7d]
-
-v_cmpx_t_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xef,0x7d]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[102:103], v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x68,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], s[102:103], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xfd,0x03,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x09,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x0d,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], s[102:103]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xf5,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x10,0x7d]
-
-v_cmp_class_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x10,0x7d]
-
-v_cmp_class_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x10,0x7d]
-
-v_cmp_class_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x10,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_class_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x10,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_class_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x11,0x7d]
-
-v_cmp_class_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x05,0x02,0x20]
-
-v_cmpx_class_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, s103, v2
-// CHECK: [0x67,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x68,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x69,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x30,0x7d]
-
-v_cmpx_class_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x30,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_class_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x30,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_class_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x31,0x7d]
-
-v_cmpx_class_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[102:103], v1, v2
-// CHECK: [0x66,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x68,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0xff,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], s103, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x67,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x69,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, s103
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x05,0x02,0x20]
-
-v_cmp_class_f64 vcc, v[1:2], v2
-// CHECK: [0x01,0x05,0x50,0x7d]
-
-v_cmp_class_f64 vcc, v[254:255], v2
-// CHECK: [0xfe,0x05,0x50,0x7d]
-
-v_cmp_class_f64 vcc, s[2:3], v2
-// CHECK: [0x02,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, s[4:5], v2
-// CHECK: [0x04,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, s[102:103], v2
-// CHECK: [0x66,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, flat_scratch, v2
-// CHECK: [0x68,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, vcc, v2
-// CHECK: [0x6a,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, tba, v2
-// CHECK: [0x6c,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, tma, v2
-// CHECK: [0x6e,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, ttmp[10:11], v2
-// CHECK: [0x7a,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, exec, v2
-// CHECK: [0x7e,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, 0, v2
-// CHECK: [0x80,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x50,0x7d]
-
-v_cmp_class_f64 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x50,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_class_f64 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x50,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_class_f64 vcc, v[1:2], v255
-// CHECK: [0x01,0xff,0x51,0x7d]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[12:13], v[1:2], v2
-// CHECK: [0x0c,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[102:103], v[1:2], v2
-// CHECK: [0x66,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 flat_scratch, v[1:2], v2
-// CHECK: [0x68,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 vcc, v[1:2], v2
-// CHECK: [0x6a,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 tba, v[1:2], v2
-// CHECK: [0x6c,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 tma, v[1:2], v2
-// CHECK: [0x6e,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 ttmp[10:11], v[1:2], v2
-// CHECK: [0x7a,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[254:255], v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], s[2:3], v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], s[4:5], v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], s[102:103], v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], flat_scratch, v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], vcc, v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], tba, v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], tma, v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], ttmp[10:11], v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], exec, v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], v255
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], s2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], s103
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_lo
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_hi
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], tba_lo
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], tba_hi
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], tma_lo
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], tma_hi
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], ttmp11
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], m0
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], exec_lo
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], exec_hi
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], -v[1:2], v2
-// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x05,0x02,0x20]
-
-v_cmpx_class_f64 vcc, v[1:2], v2
-// CHECK: [0x01,0x05,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, v[254:255], v2
-// CHECK: [0xfe,0x05,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, s[2:3], v2
-// CHECK: [0x02,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, s[4:5], v2
-// CHECK: [0x04,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, s[102:103], v2
-// CHECK: [0x66,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, flat_scratch, v2
-// CHECK: [0x68,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, vcc, v2
-// CHECK: [0x6a,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, tba, v2
-// CHECK: [0x6c,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, tma, v2
-// CHECK: [0x6e,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, ttmp[10:11], v2
-// CHECK: [0x7a,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, exec, v2
-// CHECK: [0x7e,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, 0, v2
-// CHECK: [0x80,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x70,0x7d]
-
-v_cmpx_class_f64 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x70,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_class_f64 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x70,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_class_f64 vcc, v[1:2], v255
-// CHECK: [0x01,0xff,0x71,0x7d]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[12:13], v[1:2], v2
-// CHECK: [0x0c,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[102:103], v[1:2], v2
-// CHECK: [0x66,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 flat_scratch, v[1:2], v2
-// CHECK: [0x68,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 vcc, v[1:2], v2
-// CHECK: [0x6a,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 tba, v[1:2], v2
-// CHECK: [0x6c,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 tma, v[1:2], v2
-// CHECK: [0x6e,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 ttmp[10:11], v[1:2], v2
-// CHECK: [0x7a,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[254:255], v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0xfe,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], s[2:3], v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x02,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], s[4:5], v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x04,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], s[102:103], v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x66,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], flat_scratch, v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x68,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], vcc, v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], tba, v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], tma, v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], ttmp[10:11], v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x7a,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], exec, v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], v255
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], s2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], s103
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd1,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd3,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_lo
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_hi
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], tba_lo
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], tba_hi
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], tma_lo
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], tma_hi
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], ttmp11
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], m0
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_lo
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_hi
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], -v[1:2], v2
-// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x05,0x02,0x20]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_ds.s b/llvm/test/MC/AMDGPU/gfx7_asm_ds.s
new file mode 100644
index 0000000000000..6861970293c27
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_ds.s
@@ -0,0 +1,3055 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+ds_add_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd8,0xff,0x02,0x00,0x00]
+
+ds_add_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd8,0x01,0xff,0x00,0x00]
+
+ds_add_u32 v1, v2
+// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x02,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd8,0xff,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd8,0x01,0xff,0x00,0x00]
+
+ds_sub_u32 v1, v2
+// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x06,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
+
+ds_rsub_u32 v1, v2
+// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0xff,0x00,0x00]
+
+ds_inc_u32 v1, v2
+// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd8,0xff,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd8,0x01,0xff,0x00,0x00]
+
+ds_dec_u32 v1, v2
+// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x12,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_i32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd8,0x01,0xff,0x00,0x00]
+
+ds_min_i32 v1, v2
+// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x16,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_i32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0x01,0xff,0x00,0x00]
+
+ds_max_i32 v1, v2
+// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x18,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x1c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x1c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x1c,0xd8,0x01,0xff,0x00,0x00]
+
+ds_min_u32 v1, v2
+// CHECK: [0x00,0x00,0x1c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x1c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x1c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x1e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0x01,0xff,0x00,0x00]
+
+ds_max_u32 v1, v2
+// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x20,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd8,0xff,0x02,0x00,0x00]
+
+ds_and_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd8,0x01,0xff,0x00,0x00]
+
+ds_and_b32 v1, v2
+// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x26,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x28,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x28,0xd8,0xff,0x02,0x00,0x00]
+
+ds_or_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x28,0xd8,0x01,0xff,0x00,0x00]
+
+ds_or_b32 v1, v2
+// CHECK: [0x00,0x00,0x28,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x28,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x28,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x2c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x2c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x2c,0xd8,0x01,0xff,0x00,0x00]
+
+ds_xor_b32 v1, v2
+// CHECK: [0x00,0x00,0x2c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x2c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x2c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x2e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x30,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x30,0xd8,0xff,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x30,0xd8,0x01,0xff,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x30,0xd8,0x01,0x02,0xff,0x00]
+
+ds_mskor_b32 v1, v2, v3
+// CHECK: [0x00,0x00,0x30,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x30,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x30,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x32,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x34,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x34,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x34,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b32 v1, v2
+// CHECK: [0x00,0x00,0x34,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x34,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x34,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x36,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x38,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x38,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x38,0xd8,0x01,0xff,0x03,0x00]
+
+ds_write2_b32 v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x38,0xd8,0x01,0x02,0xff,0x00]
+
+ds_write2_b32 v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x38,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x38,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x38,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x38,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x38,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x38,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x3a,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x3c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x3c,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x3c,0xd8,0x01,0xff,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x3c,0xd8,0x01,0x02,0xff,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x3c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x3c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x3c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x3c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x3c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x3c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x3e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0x01,0xff,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0xff,0x00]
+
+ds_cmpst_b32 v1, v2, v3
+// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x40,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0x01,0xff,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0xff,0x00]
+
+ds_cmpst_f32 v1, v2, v3
+// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x44,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x03,0x00]
+
+ds_min_f32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_f32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0x01,0xff,0x00,0x00]
+
+ds_min_f32 v1, v2
+// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x48,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_f32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0xff,0x00,0x00]
+
+ds_max_f32 v1, v2
+// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x4c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_nop
+// CHECK: [0x00,0x00,0x50,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:65535 gds
+// CHECK: [0xff,0xff,0x62,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all gds
+// CHECK: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:0 gds
+// CHECK: [0x00,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:4 gds
+// CHECK: [0x04,0x00,0x62,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_init v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_init v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x66,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_init v1 gds
+// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_init v1 offset:0 gds
+// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_init v1 offset:4 gds
+// CHECK: [0x04,0x00,0x66,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:65535 gds
+// CHECK: [0xff,0xff,0x6a,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v gds
+// CHECK: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:0 gds
+// CHECK: [0x00,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:4 gds
+// CHECK: [0x04,0x00,0x6a,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x6e,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_br v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x6e,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 gds
+// CHECK: [0x00,0x00,0x6e,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 offset:0 gds
+// CHECK: [0x00,0x00,0x6e,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 offset:4 gds
+// CHECK: [0x04,0x00,0x6e,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:65535 gds
+// CHECK: [0xff,0xff,0x72,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p gds
+// CHECK: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:0 gds
+// CHECK: [0x00,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:4 gds
+// CHECK: [0x04,0x00,0x72,0xd8,0x00,0x00,0x00,0x00]
+
+ds_gws_barrier v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_barrier v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x76,0xd8,0xff,0x00,0x00,0x00]
+
+ds_gws_barrier v1 gds
+// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_barrier v1 offset:0 gds
+// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x00]
+
+ds_gws_barrier v1 offset:4 gds
+// CHECK: [0x04,0x00,0x76,0xd8,0x01,0x00,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x78,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b8 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x78,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b8 v1, v2
+// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x78,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b16 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b16 v1, v2
+// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x7c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0xff,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0x01,0xff,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x80,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x82,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0xff,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0x01,0xff,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x84,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x86,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0xff,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0x01,0xff,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x88,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0xff,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0xff,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x8c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0xff,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0x01,0xff,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x90,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x92,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2
+// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x94,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x96,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2
+// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x98,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x9c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x9c,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x9c,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x9c,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x9c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x9c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x9c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x9e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0xa0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0xff,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0xff,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0xa4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd8,0xff,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0xff,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0xa8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0xaa,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xac,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xac,0xd8,0x01,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0xac,0xd8,0xff,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0xac,0xd8,0x01,0xff,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0xac,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0xac,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0xac,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0xae,0xd8,0x01,0x02,0x00,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x02,0x03,0xff]
+
+ds_mskor_rtn_b32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd8,0xff,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0xff,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x02,0xff,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0xb0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0xb0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0xb0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0xb2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd8,0xff,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0xff,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0xb4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0xb4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0xb4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0xb6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_wrxchg2_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xb8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xba,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xbc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xbe,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x03,0xff]
+
+ds_cmpst_rtn_b32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0xff,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0xff,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0xc0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x03,0xff]
+
+ds_cmpst_rtn_f32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0xff,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0xff,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0xc4,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x03,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_f32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2
+// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_f32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2
+// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x03,0xff]
+
+ds_wrap_rtn_b32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0xd0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_swizzle_b32 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x00,0x00,0xff]
+
+ds_swizzle_b32 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0xff,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1
+// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:0
+// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:4
+// CHECK: [0x04,0x00,0xd4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_b32 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1
+// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:0
+// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:4
+// CHECK: [0x04,0x00,0xd8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read2_b32 v[5:6], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset1:255
+// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127
+// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xdc,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xe0,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read2st64_b32 v[5:6], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xe0,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset1:255
+// CHECK: [0x00,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127
+// CHECK: [0x7f,0x00,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xe0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xe2,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i8 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1
+// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:0
+// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:4
+// CHECK: [0x04,0x00,0xe4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xe8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xe8,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u8 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xe8,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1
+// CHECK: [0x00,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:0
+// CHECK: [0x00,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:4
+// CHECK: [0x04,0x00,0xe8,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xea,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i16 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xec,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1
+// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:0
+// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:4
+// CHECK: [0x04,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xf0,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u16 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xf0,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1
+// CHECK: [0x00,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:0
+// CHECK: [0x00,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:4
+// CHECK: [0x04,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xf2,0xd8,0x01,0x00,0x00,0x05]
+
+ds_consume v5 offset:65535
+// CHECK: [0xff,0xff,0xf4,0xd8,0x00,0x00,0x00,0x05]
+
+ds_consume v255 offset:65535
+// CHECK: [0xff,0xff,0xf4,0xd8,0x00,0x00,0x00,0xff]
+
+ds_consume v5
+// CHECK: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:0
+// CHECK: [0x00,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:4
+// CHECK: [0x04,0x00,0xf4,0xd8,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:65535 gds
+// CHECK: [0xff,0xff,0xf6,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:65535
+// CHECK: [0xff,0xff,0xf8,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v255 offset:65535
+// CHECK: [0xff,0xff,0xf8,0xd8,0x00,0x00,0x00,0xff]
+
+ds_append v5
+// CHECK: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:0
+// CHECK: [0x00,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:4
+// CHECK: [0x04,0x00,0xf8,0xd8,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:65535 gds
+// CHECK: [0xff,0xff,0xfa,0xd8,0x00,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xfe,0xd8,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v255, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xfe,0xd8,0x01,0x00,0x00,0xff]
+
+ds_ordered_count v5, v255 offset:65535 gds
+// CHECK: [0xff,0xff,0xfe,0xd8,0xff,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 gds
+// CHECK: [0x00,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:0 gds
+// CHECK: [0x00,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:4 gds
+// CHECK: [0x04,0x00,0xfe,0xd8,0x01,0x00,0x00,0x05]
+
+ds_add_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x00,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x00,0xd9,0xff,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x00,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_add_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x00,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x02,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x04,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x04,0xd9,0xff,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x04,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x04,0xd9,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x06,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x08,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x08,0xd9,0xff,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x08,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x08,0xd9,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x0a,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd9,0xff,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x0c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x0e,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x10,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x10,0xd9,0xff,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x10,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x10,0xd9,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x12,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x14,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x14,0xd9,0xff,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x14,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_min_i64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x14,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x16,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x18,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x18,0xd9,0xff,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x18,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_max_i64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x18,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x1a,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x1c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x1c,0xd9,0xff,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x1c,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_min_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x1c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x1e,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x20,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x20,0xd9,0xff,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x20,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_max_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x20,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x22,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x24,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x24,0xd9,0xff,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x24,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_and_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x24,0xd9,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x26,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x28,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x28,0xd9,0xff,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x28,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_or_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x28,0xd9,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x2a,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x2c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x2c,0xd9,0xff,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x2c,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x2c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x2e,0xd9,0x01,0x02,0x00,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x30,0xd9,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x30,0xd9,0xff,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x30,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x30,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0x30,0xd9,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0x32,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x34,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x34,0xd9,0xff,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x34,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_write_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x34,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x36,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x38,0xd9,0xff,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x38,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x38,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x38,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x3a,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x3c,0xd9,0xff,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x3c,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x3c,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x3c,0xd9,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x3e,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x40,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x40,0xd9,0xff,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x40,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x40,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0x40,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0x42,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x44,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x44,0xd9,0xff,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x44,0xd9,0x01,0xfe,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x44,0xd9,0x01,0x02,0xfe,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0x44,0xd9,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0x46,0xd9,0x01,0x02,0x03,0x00]
+
+ds_min_f64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x48,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x48,0xd9,0xff,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x48,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_min_f64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x48,0xd9,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x4a,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd9,0xff,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd9,0x01,0xfe,0x00,0x00]
+
+ds_max_f64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x4c,0xd9,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x4e,0xd9,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd9,0xff,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x80,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x82,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_sub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd9,0xff,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x84,0xd9,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x86,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_rsub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd9,0xff,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x88,0xd9,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x8a,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_inc_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd9,0xff,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x8c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x8e,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_dec_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd9,0xff,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x90,0xd9,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x92,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_i64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd9,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x94,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x96,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_i64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd9,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x98,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x9a,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x9c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x9c,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x9c,0xd9,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x9c,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x9c,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x9e,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd9,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xa0,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xa2,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_and_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd9,0xff,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xa4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xa6,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_or_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd9,0xff,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xa8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xaa,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xac,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xac,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_xor_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xac,0xd9,0xff,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xac,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xac,0xd9,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xae,0xd9,0x01,0x02,0x00,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd9,0x01,0x02,0x03,0xfe]
+
+ds_mskor_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd9,0xff,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xb0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xb2,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_wrxchg_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd9,0xff,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xb4,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xb6,0xd9,0x01,0x02,0x00,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0x03,0xfc]
+
+ds_wrxchg2_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd9,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xb8,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xb8,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xba,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0x03,0xfc]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd9,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xbc,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xbc,0xd9,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xbe,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd9,0x01,0x02,0x03,0xfe]
+
+ds_cmpst_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd9,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xc0,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xc2,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd9,0x01,0x02,0x03,0xfe]
+
+ds_cmpst_rtn_f64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd9,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd9,0x01,0xfe,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd9,0x01,0x02,0xfe,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xc4,0xd9,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xc6,0xd9,0x01,0x02,0x03,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_f64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd9,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xca,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_f64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd9,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xcc,0xd9,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xce,0xd9,0x01,0x02,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[254:255], v1 offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd9,0x01,0x00,0x00,0xfe]
+
+ds_read_b64 v[5:6], v255 offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1
+// CHECK: [0x00,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:0
+// CHECK: [0x00,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:4
+// CHECK: [0x04,0x00,0xd8,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xda,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd9,0x01,0x00,0x00,0xfc]
+
+ds_read2_b64 v[5:8], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset1:255
+// CHECK: [0x00,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127
+// CHECK: [0x7f,0x00,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xdc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xde,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xe0,0xd9,0x01,0x00,0x00,0xfc]
+
+ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xe0,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset1:255
+// CHECK: [0x00,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127
+// CHECK: [0x7f,0x00,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xe0,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xe2,0xd9,0x01,0x00,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xf8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xf8,0xd9,0x01,0x02,0x00,0xfe]
+
+ds_condxchg32_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xf8,0xd9,0xff,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xf8,0xd9,0x01,0xfe,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xf8,0xd9,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xfa,0xd9,0x01,0x02,0x00,0x05]
+
+ds_add_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x00,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x00,0xda,0xff,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1
+// CHECK: [0x00,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x00,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x02,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x04,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x04,0xda,0xff,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1
+// CHECK: [0x00,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x04,0xda,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x06,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x08,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x08,0xda,0xff,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1
+// CHECK: [0x00,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x08,0xda,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0a,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xda,0xff,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1
+// CHECK: [0x00,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x0c,0xda,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0e,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x10,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x10,0xda,0xff,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1
+// CHECK: [0x00,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x10,0xda,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x12,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:65535
+// CHECK: [0xff,0xff,0x14,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v255 offset:65535
+// CHECK: [0xff,0xff,0x14,0xda,0xff,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1
+// CHECK: [0x00,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:0
+// CHECK: [0x00,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:4
+// CHECK: [0x04,0x00,0x14,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x16,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:65535
+// CHECK: [0xff,0xff,0x18,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v255 offset:65535
+// CHECK: [0xff,0xff,0x18,0xda,0xff,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1
+// CHECK: [0x00,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:0
+// CHECK: [0x00,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:4
+// CHECK: [0x04,0x00,0x18,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x1a,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x1c,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x1c,0xda,0xff,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1
+// CHECK: [0x00,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x1c,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x1e,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x20,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x20,0xda,0xff,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1
+// CHECK: [0x00,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x20,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x22,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x24,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x24,0xda,0xff,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1
+// CHECK: [0x00,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x24,0xda,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x26,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x28,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x28,0xda,0xff,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1
+// CHECK: [0x00,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x28,0xda,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x2a,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x2c,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x2c,0xda,0xff,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1
+// CHECK: [0x00,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x2c,0xda,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x2e,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x34,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x34,0xda,0xff,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1
+// CHECK: [0x00,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x34,0xda,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x36,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:65535
+// CHECK: [0xff,0xff,0x48,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v255 offset:65535
+// CHECK: [0xff,0xff,0x48,0xda,0xff,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1
+// CHECK: [0x00,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:0
+// CHECK: [0x00,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:4
+// CHECK: [0x04,0x00,0x48,0xda,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x4a,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v255 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xda,0xff,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1
+// CHECK: [0x00,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:0
+// CHECK: [0x00,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:4
+// CHECK: [0x04,0x00,0x4c,0xda,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x4e,0xda,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x00,0xdb,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x00,0xdb,0xff,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1
+// CHECK: [0x00,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x00,0xdb,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x02,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x04,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x04,0xdb,0xff,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1
+// CHECK: [0x00,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x04,0xdb,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x06,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x08,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x08,0xdb,0xff,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1
+// CHECK: [0x00,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x08,0xdb,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0a,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xdb,0xff,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1
+// CHECK: [0x00,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x0c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0e,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x10,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x10,0xdb,0xff,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1
+// CHECK: [0x00,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x10,0xdb,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x12,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:65535
+// CHECK: [0xff,0xff,0x14,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v255 offset:65535
+// CHECK: [0xff,0xff,0x14,0xdb,0xff,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1
+// CHECK: [0x00,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:0
+// CHECK: [0x00,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:4
+// CHECK: [0x04,0x00,0x14,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x16,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:65535
+// CHECK: [0xff,0xff,0x18,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v255 offset:65535
+// CHECK: [0xff,0xff,0x18,0xdb,0xff,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1
+// CHECK: [0x00,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:0
+// CHECK: [0x00,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:4
+// CHECK: [0x04,0x00,0x18,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x1a,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x1c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x1c,0xdb,0xff,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1
+// CHECK: [0x00,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x1c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x1e,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x20,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x20,0xdb,0xff,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1
+// CHECK: [0x00,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x20,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x22,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x24,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x24,0xdb,0xff,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1
+// CHECK: [0x00,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x24,0xdb,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x26,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x28,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x28,0xdb,0xff,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1
+// CHECK: [0x00,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x28,0xdb,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x2a,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x2c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x2c,0xdb,0xff,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1
+// CHECK: [0x00,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x2c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x2e,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x34,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x34,0xdb,0xff,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1
+// CHECK: [0x00,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x34,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x36,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:65535
+// CHECK: [0xff,0xff,0x48,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v255 offset:65535
+// CHECK: [0xff,0xff,0x48,0xdb,0xff,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1
+// CHECK: [0x00,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:0
+// CHECK: [0x00,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:4
+// CHECK: [0x04,0x00,0x48,0xdb,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x4a,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v255 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xdb,0xff,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1
+// CHECK: [0x00,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:0
+// CHECK: [0x00,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:4
+// CHECK: [0x04,0x00,0x4c,0xdb,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x4e,0xdb,0x01,0x00,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:65535
+// CHECK: [0xff,0xff,0x78,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v255, v[2:4] offset:65535
+// CHECK: [0xff,0xff,0x78,0xdb,0xff,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[253:255] offset:65535
+// CHECK: [0xff,0xff,0x78,0xdb,0x01,0xfd,0x00,0x00]
+
+ds_write_b96 v1, v[2:4]
+// CHECK: [0x00,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:0
+// CHECK: [0x00,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:4
+// CHECK: [0x04,0x00,0x78,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:65535 gds
+// CHECK: [0xff,0xff,0x7a,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:65535
+// CHECK: [0xff,0xff,0x7c,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v255, v[2:5] offset:65535
+// CHECK: [0xff,0xff,0x7c,0xdb,0xff,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[252:255] offset:65535
+// CHECK: [0xff,0xff,0x7c,0xdb,0x01,0xfc,0x00,0x00]
+
+ds_write_b128 v1, v[2:5]
+// CHECK: [0x00,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:0
+// CHECK: [0x00,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:4
+// CHECK: [0x04,0x00,0x7c,0xdb,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:65535 gds
+// CHECK: [0xff,0xff,0x7e,0xdb,0x01,0x02,0x00,0x00]
+
+ds_read_b96 v[5:7], v1 offset:65535
+// CHECK: [0xff,0xff,0xf8,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[253:255], v1 offset:65535
+// CHECK: [0xff,0xff,0xf8,0xdb,0x01,0x00,0x00,0xfd]
+
+ds_read_b96 v[5:7], v255 offset:65535
+// CHECK: [0xff,0xff,0xf8,0xdb,0xff,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1
+// CHECK: [0x00,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:0
+// CHECK: [0x00,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:4
+// CHECK: [0x04,0x00,0xf8,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xfa,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:65535
+// CHECK: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[252:255], v1 offset:65535
+// CHECK: [0xff,0xff,0xfc,0xdb,0x01,0x00,0x00,0xfc]
+
+ds_read_b128 v[5:8], v255 offset:65535
+// CHECK: [0xff,0xff,0xfc,0xdb,0xff,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1
+// CHECK: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:0
+// CHECK: [0x00,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:4
+// CHECK: [0x04,0x00,0xfc,0xdb,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xfe,0xdb,0x01,0x00,0x00,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_exp.s b/llvm/test/MC/AMDGPU/gfx7_asm_exp.s
new file mode 100644
index 0000000000000..8c5fafa405642
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_exp.s
@@ -0,0 +1,82 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+exp mrt0 v0, v0, v0, v0
+// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrtz v0, v0, v0, v0
+// CHECK: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp null v0, v0, v0, v0
+// CHECK: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp pos0 v0, v0, v0, v0
+// CHECK: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp param0 v0, v0, v0, v0
+// CHECK: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v255, v0, v0, v0
+// CHECK: [0x0f,0x00,0x00,0xf8,0xff,0x00,0x00,0x00]
+
+exp mrt0 v0, v255, v0, v0
+// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0xff,0x00,0x00]
+
+exp mrt0 v0, v0, v255, v0
+// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0xff,0x00]
+
+exp mrt0 v0, v0, v0, v255
+// CHECK: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0xff]
+
+exp mrt0 v0, off, off, off
+// CHECK: [0x01,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, off, off
+// CHECK: [0x02,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, off, off
+// CHECK: [0x03,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, v0, off
+// CHECK: [0x04,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, off, v0, off
+// CHECK: [0x05,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, v0, off
+// CHECK: [0x06,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, off
+// CHECK: [0x07,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, off, v0
+// CHECK: [0x08,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, off, off, v0
+// CHECK: [0x09,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, off, v0
+// CHECK: [0x0a,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, off, v0
+// CHECK: [0x0b,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, v0, v0
+// CHECK: [0x0c,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, off, v0, v0
+// CHECK: [0x0d,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, v0, v0
+// CHECK: [0x0e,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, off, off
+// CHECK: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, v0 done
+// CHECK: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, v0 compr
+// CHECK: [0x0f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, v0 vm
+// CHECK: [0x0f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_flat.s b/llvm/test/MC/AMDGPU/gfx7_asm_flat.s
new file mode 100644
index 0000000000000..c240b263b967a
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_flat.s
@@ -0,0 +1,691 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+flat_load_ubyte v5, v[1:2]
+// CHECK: [0x00,0x00,0x20,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte v255, v[1:2]
+// CHECK: [0x00,0x00,0x20,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_ubyte v5, v[254:255]
+// CHECK: [0x00,0x00,0x20,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_ubyte v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x21,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x22,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2]
+// CHECK: [0x00,0x00,0x24,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v255, v[1:2]
+// CHECK: [0x00,0x00,0x24,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_sbyte v5, v[254:255]
+// CHECK: [0x00,0x00,0x24,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x25,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x26,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2]
+// CHECK: [0x00,0x00,0x28,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v255, v[1:2]
+// CHECK: [0x00,0x00,0x28,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_ushort v5, v[254:255]
+// CHECK: [0x00,0x00,0x28,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x29,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x2a,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2]
+// CHECK: [0x00,0x00,0x2c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v255, v[1:2]
+// CHECK: [0x00,0x00,0x2c,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_sshort v5, v[254:255]
+// CHECK: [0x00,0x00,0x2c,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x2d,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x2e,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2]
+// CHECK: [0x00,0x00,0x30,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v255, v[1:2]
+// CHECK: [0x00,0x00,0x30,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_dword v5, v[254:255]
+// CHECK: [0x00,0x00,0x30,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x31,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x32,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2]
+// CHECK: [0x00,0x00,0x34,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[254:255], v[1:2]
+// CHECK: [0x00,0x00,0x34,0xdc,0x01,0x00,0x00,0xfe]
+
+flat_load_dwordx2 v[5:6], v[254:255]
+// CHECK: [0x00,0x00,0x34,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2] glc
+// CHECK: [0x00,0x00,0x35,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2] slc
+// CHECK: [0x00,0x00,0x36,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2]
+// CHECK: [0x00,0x00,0x38,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[252:255], v[1:2]
+// CHECK: [0x00,0x00,0x38,0xdc,0x01,0x00,0x00,0xfc]
+
+flat_load_dwordx4 v[5:8], v[254:255]
+// CHECK: [0x00,0x00,0x38,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2] glc
+// CHECK: [0x00,0x00,0x39,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2] slc
+// CHECK: [0x00,0x00,0x3a,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2]
+// CHECK: [0x00,0x00,0x3c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[253:255], v[1:2]
+// CHECK: [0x00,0x00,0x3c,0xdc,0x01,0x00,0x00,0xfd]
+
+flat_load_dwordx3 v[5:7], v[254:255]
+// CHECK: [0x00,0x00,0x3c,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2] glc
+// CHECK: [0x00,0x00,0x3d,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2] slc
+// CHECK: [0x00,0x00,0x3e,0xdc,0x01,0x00,0x00,0x05]
+
+flat_store_byte v[1:2], v2
+// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte v[254:255], v2
+// CHECK: [0x00,0x00,0x60,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_byte v[1:2], v255
+// CHECK: [0x00,0x00,0x60,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_byte v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x61,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x62,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v2
+// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[254:255], v2
+// CHECK: [0x00,0x00,0x68,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v255
+// CHECK: [0x00,0x00,0x68,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_short v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x69,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x6a,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v2
+// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[254:255], v2
+// CHECK: [0x00,0x00,0x70,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v255
+// CHECK: [0x00,0x00,0x70,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_dword v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x71,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x72,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x74,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x74,0xdc,0x01,0xfe,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x75,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x76,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5]
+// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[254:255], v[2:5]
+// CHECK: [0x00,0x00,0x78,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[252:255]
+// CHECK: [0x00,0x00,0x78,0xdc,0x01,0xfc,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5] glc
+// CHECK: [0x00,0x00,0x79,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5] slc
+// CHECK: [0x00,0x00,0x7a,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4]
+// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[254:255], v[2:4]
+// CHECK: [0x00,0x00,0x7c,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[253:255]
+// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0xfd,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4] glc
+// CHECK: [0x00,0x00,0x7d,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4] slc
+// CHECK: [0x00,0x00,0x7e,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v2
+// CHECK: [0x00,0x00,0xc0,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[254:255], v2
+// CHECK: [0x00,0x00,0xc0,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v255
+// CHECK: [0x00,0x00,0xc0,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_swap v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xc1,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xc2,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xc4,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0xc4,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0xc4,0xdc,0x01,0xfe,0x00,0x00]
+
+flat_atomic_cmpswap v0, v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0xc5,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0xc6,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v2
+// CHECK: [0x00,0x00,0xc8,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[254:255], v2
+// CHECK: [0x00,0x00,0xc8,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v255
+// CHECK: [0x00,0x00,0xc8,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_add v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xc9,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xca,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v2
+// CHECK: [0x00,0x00,0xcc,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[254:255], v2
+// CHECK: [0x00,0x00,0xcc,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v255
+// CHECK: [0x00,0x00,0xcc,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_sub v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xcd,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xce,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v2
+// CHECK: [0x00,0x00,0xd4,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[254:255], v2
+// CHECK: [0x00,0x00,0xd4,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v255
+// CHECK: [0x00,0x00,0xd4,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_smin v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xd5,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xd6,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v2
+// CHECK: [0x00,0x00,0xd8,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[254:255], v2
+// CHECK: [0x00,0x00,0xd8,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v255
+// CHECK: [0x00,0x00,0xd8,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_umin v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xd9,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xda,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v2
+// CHECK: [0x00,0x00,0xdc,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[254:255], v2
+// CHECK: [0x00,0x00,0xdc,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v255
+// CHECK: [0x00,0x00,0xdc,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_smax v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xdd,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xde,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v2
+// CHECK: [0x00,0x00,0xe0,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[254:255], v2
+// CHECK: [0x00,0x00,0xe0,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v255
+// CHECK: [0x00,0x00,0xe0,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_umax v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xe1,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xe2,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v2
+// CHECK: [0x00,0x00,0xe4,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[254:255], v2
+// CHECK: [0x00,0x00,0xe4,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v255
+// CHECK: [0x00,0x00,0xe4,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_and v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xe5,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xe6,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v2
+// CHECK: [0x00,0x00,0xe8,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[254:255], v2
+// CHECK: [0x00,0x00,0xe8,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v255
+// CHECK: [0x00,0x00,0xe8,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_or v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xe9,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xea,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v2
+// CHECK: [0x00,0x00,0xec,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[254:255], v2
+// CHECK: [0x00,0x00,0xec,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v255
+// CHECK: [0x00,0x00,0xec,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_xor v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xed,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xee,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v2
+// CHECK: [0x00,0x00,0xf0,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[254:255], v2
+// CHECK: [0x00,0x00,0xf0,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v255
+// CHECK: [0x00,0x00,0xf0,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_inc v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xf1,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xf2,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v2
+// CHECK: [0x00,0x00,0xf4,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[254:255], v2
+// CHECK: [0x00,0x00,0xf4,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v255
+// CHECK: [0x00,0x00,0xf4,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_dec v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xf5,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xf6,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_fcmpswap v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xf8,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_fcmpswap v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0xf8,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_fcmpswap v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0xf8,0xdc,0x01,0xfe,0x00,0x00]
+
+flat_atomic_fcmpswap v0, v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0xf9,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_fcmpswap v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0xfa,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmin v[1:2], v2
+// CHECK: [0x00,0x00,0xfc,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmin v[254:255], v2
+// CHECK: [0x00,0x00,0xfc,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_atomic_fmin v[1:2], v255
+// CHECK: [0x00,0x00,0xfc,0xdc,0x01,0xff,0x00,0x00]
+
+flat_atomic_fmin v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0xfd,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmin v[1:2], v2 slc
+// CHECK: [0x00,0x00,0xfe,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmax v[1:2], v2
+// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmax v[254:255], v2
+// CHECK: [0x00,0x00,0x00,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_fmax v[1:2], v255
+// CHECK: [0x00,0x00,0x00,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_fmax v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x01,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmax v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x02,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x40,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x40,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x40,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_swap_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x41,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x42,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5]
+// CHECK: [0x00,0x00,0x44,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[254:255], v[2:5]
+// CHECK: [0x00,0x00,0x44,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[252:255]
+// CHECK: [0x00,0x00,0x44,0xdd,0x01,0xfc,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[0:1], v[1:2], v[2:5] glc
+// CHECK: [0x00,0x00,0x45,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5] slc
+// CHECK: [0x00,0x00,0x46,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x48,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x48,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x48,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_add_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x49,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x4a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x4c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x4c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x4c,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_sub_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x4d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x4e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x54,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x54,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x54,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_smin_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x55,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x56,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x58,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x58,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x58,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_umin_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x59,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x5a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x5c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x5c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x5c,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_smax_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x5d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x5e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x60,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x60,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x60,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_umax_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x61,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x62,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x64,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x64,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x64,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_and_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x65,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x66,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x68,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x68,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x68,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_or_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x69,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x6a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x6c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x6c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x6c,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_xor_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x6d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x6e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x70,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x70,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x70,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_inc_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x71,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x72,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x74,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x74,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x74,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_dec_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x75,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x76,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fcmpswap_x2 v[1:2], v[2:5]
+// CHECK: [0x00,0x00,0x78,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fcmpswap_x2 v[254:255], v[2:5]
+// CHECK: [0x00,0x00,0x78,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_fcmpswap_x2 v[1:2], v[252:255]
+// CHECK: [0x00,0x00,0x78,0xdd,0x01,0xfc,0x00,0x00]
+
+flat_atomic_fcmpswap_x2 v[0:1], v[1:2], v[2:5] glc
+// CHECK: [0x00,0x00,0x79,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fcmpswap_x2 v[1:2], v[2:5] slc
+// CHECK: [0x00,0x00,0x7a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmin_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x7c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmin_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x7c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_fmin_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x7c,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_fmin_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x7d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmin_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x7e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmax_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmax_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x80,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_fmax_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x80,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_fmax_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x81,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_fmax_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x82,0xdd,0x01,0x02,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
new file mode 100644
index 0000000000000..10c9363d74ad2
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
@@ -0,0 +1,6661 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+image_load v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x03,0x00]
+
+image_load v5, v1, s[96:103] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x18,0x00]
+
+image_load v5, v1, ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x02,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v252, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_mip v5, v[252:253], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_mip v5, v[1:2], s[96:103] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x18,0x00]
+
+image_load_mip v5, v[1:2], ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:8], v[1:2], s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x06,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_pck v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_pck v5, v1, s[96:103] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x18,0x00]
+
+image_load_pck v5, v1, ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x08,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x09,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x0a,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_pck_sgn v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_pck_sgn v5, v1, s[96:103] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x18,0x00]
+
+image_load_pck_sgn v5, v1, ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x0c,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x0d,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x0e,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v252, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_mip_pck v5, v[252:253], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_mip_pck v5, v[1:2], s[96:103] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x18,0x00]
+
+image_load_mip_pck v5, v[1:2], ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:8], v[1:2], s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x10,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x11,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x12,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v252, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[252:253], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[96:103] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x18,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:8], v[1:2], s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x14,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x15,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x16,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store v1, v252, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x04,0x00]
+
+image_store v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x18,0x00]
+
+image_store v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:4], v2, s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x20,0xf2,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x22,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v252, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_mip v1, v[252:253], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x04,0x00]
+
+image_store_mip v1, v[2:3], s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x18,0x00]
+
+image_store_mip v1, v[2:3], ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:4], v[2:3], s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x24,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x26,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_pck v1, v252, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x04,0x00]
+
+image_store_pck v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x18,0x00]
+
+image_store_pck v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:4], v2, s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x28,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x2a,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_mip_pck v1, v[252:253], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x04,0x00]
+
+image_store_mip_pck v1, v[2:3], s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x18,0x00]
+
+image_store_mip_pck v1, v[2:3], ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:4], v[2:3], s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x2c,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x2e,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0xfc,0x02,0x00]
+
+image_get_resinfo v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0xfc,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x03,0x00]
+
+image_get_resinfo v5, v1, s[96:103] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x18,0x00]
+
+image_get_resinfo v5, v1, ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x1d,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x3a,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_swap v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_swap v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_swap v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_swap v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_swap v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_swap v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x3c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_swap v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_swap v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_swap v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x3c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x3c,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x3e,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_swap v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x3c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[252:253], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v255, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v2, s[16:23] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_cmpswap v[1:2], v2, s[96:103] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_cmpswap v[1:2], v2, ttmp[4:11] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_cmpswap v[1:4], v2, s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x40,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v[2:5], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm glc
+// CHECK: [0x00,0x33,0x40,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm slc
+// CHECK: [0x00,0x13,0x40,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm lwe
+// CHECK: [0x00,0x13,0x42,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm da
+// CHECK: [0x00,0x53,0x40,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_add v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_add v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_add v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_add v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_add v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_add v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_add v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_add v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_add v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x44,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x44,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x46,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x44,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_sub v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_sub v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_sub v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_sub v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_sub v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_sub v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x48,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_sub v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_sub v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_sub v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x48,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x48,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x4a,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_sub v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x48,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smin v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_smin v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_smin v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_smin v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_smin v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_smin v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x50,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smin v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smin v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smin v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x50,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x50,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x52,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smin v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x50,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umin v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_umin v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_umin v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_umin v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_umin v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_umin v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x54,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umin v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umin v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umin v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x54,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x54,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x56,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umin v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x54,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smax v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_smax v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_smax v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_smax v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_smax v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_smax v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x58,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smax v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smax v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smax v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x58,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x58,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x5a,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_smax v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x58,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umax v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_umax v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_umax v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_umax v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_umax v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_umax v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x5c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umax v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umax v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umax v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x5c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x5c,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x5e,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_umax v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x5c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_and v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_and v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_and v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_and v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_and v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_and v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x60,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_and v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_and v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_and v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x60,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x60,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x62,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_and v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x60,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_or v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_or v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_or v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_or v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_or v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_or v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x64,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_or v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_or v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_or v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x64,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x64,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x66,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_or v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x64,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_xor v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_xor v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_xor v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_xor v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_xor v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_xor v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x68,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_xor v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_xor v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_xor v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x68,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x68,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x6a,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_xor v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x68,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_inc v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_inc v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_inc v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_inc v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_inc v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_inc v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x6c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_inc v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_inc v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_inc v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x6c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x6c,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x6e,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_inc v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x6c,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_dec v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_dec v1, v255, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_dec v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x04,0x00]
+
+image_atomic_dec v1, v2, s[96:103] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_dec v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_dec v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x70,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_dec v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_dec v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_dec v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x70,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x70,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x72,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_dec v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x70,0xf0,0x02,0x01,0x03,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v252, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample v5, v252, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample v5, v1, s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample v5, v1, s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample v5, v1, ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample v5, v1, s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample v5, v1, s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample v5, v1, s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:8], v1, s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x80,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x81,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x82,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_cl v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_cl v5, v[1:2], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_cl v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_cl v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x86,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d v5, v[246:248], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_d v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_d v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x88,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x89,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x8a,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d_cl v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d_cl v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_d_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_d_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x8c,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x8d,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x8e,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_l v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_l v5, v[1:2], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_l v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_l v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x92,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b v5, v[1:2], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_b v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_b v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x96,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b_cl v5, v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b_cl v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_b_cl v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_b_cl v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x98,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x99,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x9a,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v252, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_lz v5, v252, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_lz v5, v1, s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_lz v5, v1, ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_lz v5, v1, s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:8], v1, s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x9c,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x9d,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x9e,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c v5, v[1:2], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cl v5, v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_cl v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_cl v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_cl v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d v5, v[252:255], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_d v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_d v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xaa,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d_cl v5, v[246:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_d_cl v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xac,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xad,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xae,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_l v5, v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_l v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_l v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_l v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b v5, v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_b v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_b v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_b_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xba,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_lz v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_lz v5, v[1:2], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_lz v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_lz v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xbe,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_o v5, v[251:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_o v5, v[1:2], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_o v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_o v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xc0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xc1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xc2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_cl_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_cl_o v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_cl_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_cl_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xc4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xc5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xc6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d_o v5, v[245:248], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d_o v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_d_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_d_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xc8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xc9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xca,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_d_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xcc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xcd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xce,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_l_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_l_o v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_l_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_l_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xd0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xd1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xd2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b_o v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_b_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_b_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xd4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xd5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xd6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b_cl_o v5, v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_b_cl_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xd8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xd9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xda,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_lz_o v5, v[251:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_lz_o v5, v[1:2], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_lz_o v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_lz_o v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xdc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xdd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xde,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_o v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xe0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xe1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xe2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cl_o v5, v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_cl_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xe4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xe5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xe6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_d_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xe8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xe9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xea,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xec,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xed,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xee,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_l_o v5, v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_l_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xf0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xf1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xf2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b_o v5, v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_b_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xf4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xf5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xf6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xf8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xf9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xfa,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_lz_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x78,0x00]
+
+image_sample_c_lz_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x22,0x03]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xfc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xfd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xfe,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[252:255], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4 v[5:8], v[1:2], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4 v[5:8], v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4 v[5:8], v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x00,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:9], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x01,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x02,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_cl v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x04,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x05,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x06,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_l v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x10,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x11,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x12,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_b v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x14,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x15,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x16,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x18,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x19,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x1a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[252:255], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_lz v[5:8], v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x1c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:9], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x1d,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x1e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x20,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x21,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x22,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x24,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x25,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x26,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x30,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x31,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x32,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x34,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x35,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x36,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x38,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x39,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x3a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x3c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x3d,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x3e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_o v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x40,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x41,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x42,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x44,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x45,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x46,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x50,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x51,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x52,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x54,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x55,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x56,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x58,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x59,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x5a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x5c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x5d,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x5e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x60,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x61,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x62,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x64,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x65,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x66,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x70,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x71,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x72,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x74,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x75,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x76,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x78,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x79,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x7a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x78,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x22,0x03]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x7c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x7d,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x7e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v252, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0xfc,0x62,0x00]
+
+image_get_lod v5, v255, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0xff,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x63,0x00]
+
+image_get_lod v5, v1, s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x78,0x00]
+
+image_get_lod v5, v1, ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x7d,0x00]
+
+image_get_lod v5, v1, s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x82,0x00]
+
+image_get_lod v5, v1, s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x22,0x03]
+
+image_get_lod v5, v1, s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0xc2,0x03]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:8], v1, s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x80,0xf3,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x81,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x82,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd v5, v[246:248], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd v5, v[1:3], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x78,0x00]
+
+image_sample_cd v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x22,0x03]
+
+image_sample_cd v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa0,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa1,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa2,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd_cl v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x78,0x00]
+
+image_sample_cd_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x22,0x03]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa4,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa5,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa6,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd v5, v[252:255], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0xfc,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x78,0x00]
+
+image_sample_c_cd v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x22,0x03]
+
+image_sample_c_cd v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa8,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa9,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xaa,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[246:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x78,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x22,0x03]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xac,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xad,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xae,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd_o v5, v[245:248], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd_o v5, v[1:4], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x78,0x00]
+
+image_sample_cd_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x22,0x03]
+
+image_sample_cd_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb0,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb1,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb2,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x78,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x22,0x03]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb4,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb5,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb6,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x78,0x00]
+
+image_sample_c_cd_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x22,0x03]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb8,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb9,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xba,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[96:103], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x78,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[100:103] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x22,0x03]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xbc,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xbd,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xbe,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xbc,0xf1,0x01,0x05,0x62,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s b/llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s
new file mode 100644
index 0000000000000..61d180b753195
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_mtbuf.s
@@ -0,0 +1,1369 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0xff,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_x v5, off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x19,0x03]
+
+tbuffer_load_format_x v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x68]
+
+tbuffer_load_format_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x69]
+
+tbuffer_load_format_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_x v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_x v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_x v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_x v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_x v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM_OGL] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0xfe,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x19,0x03]
+
+tbuffer_load_format_xy v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x68]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x69]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x11,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x19,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x21,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x29,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x31,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x39,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x41,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x49,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x51,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x59,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x61,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x69,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x71,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x79,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x01,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM_OGL] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0xfd,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x19,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x68]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x69]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x12,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x22,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x32,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x42,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x52,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x62,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x72,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x02,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM_OGL] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0a,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0xfc,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x19,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x68]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x69]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x13,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x23,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x33,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x43,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x53,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x63,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x73,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x03,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM_OGL] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0b,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0xff,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_x v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x19,0x04]
+
+tbuffer_store_format_x v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x68]
+
+tbuffer_store_format_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x69]
+
+tbuffer_store_format_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_x v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_x v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_x v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_x v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_x v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM_OGL] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0c,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0xfe,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x19,0x04]
+
+tbuffer_store_format_xy v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x68]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x69]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x15,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x25,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x35,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x45,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x55,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x65,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x75,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x05,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM_OGL] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0d,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0xfd,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x19,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x68]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x69]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x16,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x26,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x36,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x46,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x56,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x66,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x76,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x06,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM_OGL] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0xfc,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x19,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x68]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x69]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x17,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x27,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x37,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x47,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x57,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x67,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x77,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x07,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM_OGL] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x43,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
new file mode 100644
index 0000000000000..f6ae2d5ede97b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_mubuf.s
@@ -0,0 +1,5371 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_format_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_x v5, off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_format_x v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_format_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_format_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_x v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_x v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_x v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_x v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_x v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xy v[5:6], off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_format_xy v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_format_xy v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_xy v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_xy v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_xy v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_xy v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_xy v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_xy v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xy v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_xy v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xy v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_xy v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_xy v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0xfd,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_format_xyz v[5:7], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0xfc,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_format_xyzw v[5:8], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_format_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_x v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_format_x v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_format_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_format_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_x v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_x v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_x v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_x v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_x v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xy v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_format_xy v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_format_xy v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_xy v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_xy v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_xy v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_xy v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_xy v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_xy v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xy v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_xy v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xy v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_xy v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_xy v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0xfd,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_format_xyz v[1:3], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0xfc,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_format_xyzw v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ubyte v5, off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_ubyte v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_ubyte v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_ubyte v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_ubyte v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_ubyte v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_ubyte v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_ubyte v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_ubyte v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_ubyte v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_ubyte v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_ubyte v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ubyte v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_ubyte v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_ubyte v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ubyte v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ubyte v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ubyte v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ubyte v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_ubyte v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_ubyte v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_ubyte v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x21,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sbyte v5, off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_sbyte v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_sbyte v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_sbyte v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_sbyte v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_sbyte v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_sbyte v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_sbyte v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_sbyte v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_sbyte v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_sbyte v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_sbyte v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sbyte v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_sbyte v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_sbyte v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sbyte v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sbyte v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sbyte v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sbyte v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_sbyte v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_sbyte v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_sbyte v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x25,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ushort v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ushort v5, off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_ushort v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_ushort v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_ushort v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_ushort v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_ushort v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_ushort v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_ushort v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_ushort v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_ushort v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_ushort v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_ushort v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ushort v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_ushort v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_ushort v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ushort v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ushort v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ushort v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ushort v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_ushort v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_ushort v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x29,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sshort v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sshort v5, off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_sshort v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_sshort v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_sshort v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_sshort v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_sshort v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_sshort v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_sshort v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_sshort v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_sshort v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_sshort v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_sshort v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sshort v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_sshort v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_sshort v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sshort v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sshort v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sshort v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sshort v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_sshort v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_sshort v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_sshort v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x2d,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_dword v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dword v5, off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_dword v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dword v5, off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dword v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_dword v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_dword v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dword v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dword v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_dword v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_dword v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_dword v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_dword v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dword v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dword v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dword v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dword v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dword v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dword v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dword v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dword v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dword v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dword v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dword v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x30,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x31,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_dwordx2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x34,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0xfc,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_dwordx4 v[5:8], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x38,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0xfd,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[100:103], s3 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x19,0x03]
+
+buffer_load_dwordx3 v[5:7], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s103 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x68]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x69]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], v[0:1], s[8:11], s3 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x3c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x05,0x42,0x03]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_byte v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_byte v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_byte v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_byte v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_byte v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_byte v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_byte v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_byte v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_byte v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_byte v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_byte v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_byte v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_byte v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_byte v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_byte v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_byte v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_byte v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_byte v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_byte v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_byte v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_byte v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_byte v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_byte v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_byte v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_short v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_short v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_short v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_short v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_short v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_short v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_short v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_short v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_short v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_short v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_short v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_short v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_short v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_short v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_short v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_short v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_short v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_short v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_short v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_short v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_short v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_short v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_short v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_short v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_dword v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dword v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_dword v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dword v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dword v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_dword v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_dword v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dword v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dword v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_dword v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_dword v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_dword v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_dword v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dword v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dword v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dword v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dword v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dword v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dword v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dword v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dword v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dword v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dword v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dword v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_dwordx2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0xfc,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_dwordx4 v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0xfd,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_store_dwordx3 v[1:3], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_swap v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_swap v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_swap v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_swap v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_swap v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_swap v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_swap v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_swap v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_swap v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_swap v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_swap v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_swap v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_swap v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_swap v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_swap v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_swap v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_swap v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_swap v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_swap v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_swap v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_swap v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_swap v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_swap v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_swap v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_swap v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xc0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xc0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xc0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xc0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xc0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xc0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xc0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xc0,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_cmpswap v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xc4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xc4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xc4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0xc4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xc4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xc4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xc4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xc4,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_add v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_add v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_add v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_add v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_add v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_add v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_add v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_add v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_add v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_add v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_add v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_add v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_add v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_add v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_add v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_add v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_add v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_add v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_add v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_add v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_add v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_add v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_add v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_add v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_add v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xc8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xc8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xc8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xc8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xc8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xc8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xc8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xc8,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_sub v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_sub v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_sub v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_sub v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_sub v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_sub v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_sub v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_sub v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_sub v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_sub v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_sub v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_sub v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_sub v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_sub v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_sub v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_sub v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_sub v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_sub v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_sub v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_sub v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_sub v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_sub v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_sub v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_sub v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_sub v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xcc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xcc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xcc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xcc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xcc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xcc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xcc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xcc,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_smin v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_smin v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_smin v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_smin v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_smin v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_smin v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_smin v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_smin v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_smin v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_smin v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_smin v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_smin v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_smin v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_smin v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_smin v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_smin v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_smin v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_smin v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_smin v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_smin v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_smin v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_smin v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_smin v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_smin v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_smin v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xd4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xd4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xd4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xd4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xd4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xd4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xd4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xd4,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_umin v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_umin v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_umin v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_umin v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_umin v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_umin v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_umin v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_umin v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_umin v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_umin v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_umin v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_umin v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_umin v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_umin v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_umin v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_umin v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_umin v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_umin v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_umin v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_umin v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_umin v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_umin v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_umin v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_umin v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_umin v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xd8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xd8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xd8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xd8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xd8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xd8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xd8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xd8,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_smax v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_smax v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_smax v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_smax v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_smax v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_smax v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_smax v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_smax v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_smax v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_smax v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_smax v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_smax v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_smax v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_smax v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_smax v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_smax v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_smax v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_smax v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_smax v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_smax v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_smax v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_smax v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_smax v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_smax v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_smax v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xdc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xdc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xdc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xdc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xdc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xdc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xdc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xdc,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_umax v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_umax v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_umax v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_umax v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_umax v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_umax v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_umax v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_umax v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_umax v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_umax v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_umax v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_umax v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_umax v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_umax v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_umax v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_umax v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_umax v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_umax v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_umax v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_umax v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_umax v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_umax v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_umax v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_umax v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_umax v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xe0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xe0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xe0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xe0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xe0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xe0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xe0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xe0,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_and v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_and v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_and v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_and v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_and v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_and v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_and v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_and v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_and v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_and v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_and v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_and v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_and v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_and v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_and v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_and v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_and v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_and v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_and v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_and v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_and v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_and v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_and v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_and v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_and v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xe4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xe4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xe4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xe4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xe4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xe4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xe4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xe4,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_or v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_or v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_or v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_or v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_or v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_or v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_or v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_or v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_or v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_or v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_or v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_or v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_or v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_or v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_or v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_or v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_or v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_or v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_or v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_or v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_or v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_or v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_or v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_or v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_or v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xe8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xe8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xe8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xe8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xe8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xe8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xe8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xe8,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_xor v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_xor v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_xor v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_xor v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_xor v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_xor v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_xor v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_xor v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_xor v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_xor v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_xor v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_xor v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_xor v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_xor v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_xor v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_xor v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_xor v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_xor v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_xor v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_xor v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_xor v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_xor v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_xor v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_xor v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_xor v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xec,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xec,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xec,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xec,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xec,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xec,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xec,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xec,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_inc v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_inc v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_inc v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_inc v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_inc v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_inc v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_inc v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_inc v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_inc v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_inc v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_inc v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_inc v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_inc v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_inc v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_inc v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_inc v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_inc v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_inc v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_inc v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_inc v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_inc v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_inc v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_inc v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_inc v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_inc v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xf0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xf0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xf0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xf0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xf0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xf0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xf0,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xf0,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_dec v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_dec v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_dec v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_dec v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_dec v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_dec v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_dec v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_dec v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_dec v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_dec v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_dec v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_dec v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_dec v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_dec v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_dec v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_dec v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_dec v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_dec v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_dec v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_dec v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_dec v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_dec v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_dec v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_dec v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_dec v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xf4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xf4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xf4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xf4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xf4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xf4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xf4,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xf4,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_fcmpswap v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xf8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xf8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xf8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0xf8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xf8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xf8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xf8,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xf8,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_fmin v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_atomic_fmin v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_atomic_fmin v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x19,0x04]
+
+buffer_atomic_fmin v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_fmin v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_atomic_fmin v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x68]
+
+buffer_atomic_fmin v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x69]
+
+buffer_atomic_fmin v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_fmin v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_fmin v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_fmin v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_fmin v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_fmin v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_fmin v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_fmin v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_fmin v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_fmin v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_fmin v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_atomic_fmin v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_fmin v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_fmin v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_fmin v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_fmin v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_fmin v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_fmin v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0xfc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0xfc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0xfc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0xfc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0xfc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0xfc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0xfc,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0xfc,0xe0,0x00,0x01,0x43,0x04]
+
+buffer_atomic_fmax v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0xff,0x03,0x04]
+
+buffer_atomic_fmax v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_fmax v1, off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_fmax v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_fmax v1, off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_fmax v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_fmax v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_fmax v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_fmax v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_fmax v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_fmax v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_fmax v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_fmax v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_fmax v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_fmax v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_fmax v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_fmax v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_fmax v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_fmax v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_fmax v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_fmax v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_fmax v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_fmax v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_fmax v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_fmax v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x00,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x00,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax v1, v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x00,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x00,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x00,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_swap_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x40,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x40,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x40,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x40,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x40,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x40,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x40,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_swap_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x40,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap_x2 v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0xfc,0x03,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_cmpswap_x2 v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x44,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x44,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x44,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x44,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x44,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x44,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x44,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_cmpswap_x2 v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x44,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_add_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x48,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x48,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x48,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x48,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x48,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x48,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x48,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_add_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x48,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_sub_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x4c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x4c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x4c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x4c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x4c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x4c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x4c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_sub_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x4c,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_smin_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x54,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x54,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x54,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x54,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x54,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x54,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x54,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smin_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x54,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_umin_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x58,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x58,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x58,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x58,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x58,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x58,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x58,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umin_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x58,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_smax_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x5c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x5c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x5c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x5c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x5c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x5c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x5c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_smax_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x5c,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_umax_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x60,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x60,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x60,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x60,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x60,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x60,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x60,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_umax_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x60,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_and_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x64,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x64,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x64,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x64,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x64,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x64,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x64,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_and_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x64,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_or_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x68,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x68,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x68,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x68,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x68,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x68,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x68,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_or_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x68,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_xor_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x6c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x6c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x6c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x6c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x6c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x6c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x6c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_xor_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x6c,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_inc_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x70,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x70,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x70,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x70,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x70,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x70,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x70,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_inc_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x70,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_dec_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x74,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x74,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x74,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x74,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x74,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x74,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x74,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_dec_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x74,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap_x2 v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0xfc,0x03,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_fcmpswap_x2 v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x78,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x78,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x78,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x78,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x78,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x78,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x78,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fcmpswap_x2 v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x78,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_fmin_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x7c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x7c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x7c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x7c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x7c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x7c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x7c,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmin_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x7c,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax_x2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0xfe,0x03,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x04,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[100:103], s4 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x19,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x1e,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], s103 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x67]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x68]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x69]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x6a]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x6b]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x6c]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x6d]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x6e]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x6f]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x7b]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x7c]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x7e]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x7f]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0x80]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0xc1]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0xf0]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0xf7]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0xfb]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0xfc]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x03,0xfd]
+
+buffer_atomic_fmax_x2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x80,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x80,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], v[0:1], s[12:15], s4 addr64 offset:4095
+// CHECK: [0xff,0x8f,0x80,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x80,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x80,0xe1,0x00,0x01,0x03,0x04]
+
+buffer_atomic_fmax_x2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x01,0x43,0x04]
+
+buffer_wbinvl1_vol
+// CHECK: [0x00,0x00,0xc0,0xe1,0x00,0x00,0x00,0x00]
+
+buffer_wbinvl1
+// CHECK: [0x00,0x00,0xc4,0xe1,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_smrd.s b/llvm/test/MC/AMDGPU/gfx7_asm_smrd.s
new file mode 100644
index 0000000000000..2b44cdc851acb
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_smrd.s
@@ -0,0 +1,751 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+s_load_dword s5, s[2:3], s2
+// CHECK: [0x02,0x82,0x02,0xc0]
+
+s_load_dword s103, s[2:3], s2
+// CHECK: [0x02,0x82,0x33,0xc0]
+
+s_load_dword flat_scratch_lo, s[2:3], s2
+// CHECK: [0x02,0x02,0x34,0xc0]
+
+s_load_dword flat_scratch_hi, s[2:3], s2
+// CHECK: [0x02,0x82,0x34,0xc0]
+
+s_load_dword vcc_lo, s[2:3], s2
+// CHECK: [0x02,0x02,0x35,0xc0]
+
+s_load_dword vcc_hi, s[2:3], s2
+// CHECK: [0x02,0x82,0x35,0xc0]
+
+s_load_dword tba_lo, s[2:3], s2
+// CHECK: [0x02,0x02,0x36,0xc0]
+
+s_load_dword tba_hi, s[2:3], s2
+// CHECK: [0x02,0x82,0x36,0xc0]
+
+s_load_dword tma_lo, s[2:3], s2
+// CHECK: [0x02,0x02,0x37,0xc0]
+
+s_load_dword tma_hi, s[2:3], s2
+// CHECK: [0x02,0x82,0x37,0xc0]
+
+s_load_dword ttmp11, s[2:3], s2
+// CHECK: [0x02,0x82,0x3d,0xc0]
+
+s_load_dword s5, s[4:5], s2
+// CHECK: [0x02,0x84,0x02,0xc0]
+
+s_load_dword s5, s[102:103], s2
+// CHECK: [0x02,0xe6,0x02,0xc0]
+
+s_load_dword s5, flat_scratch, s2
+// CHECK: [0x02,0xe8,0x02,0xc0]
+
+s_load_dword s5, vcc, s2
+// CHECK: [0x02,0xea,0x02,0xc0]
+
+s_load_dword s5, tba, s2
+// CHECK: [0x02,0xec,0x02,0xc0]
+
+s_load_dword s5, tma, s2
+// CHECK: [0x02,0xee,0x02,0xc0]
+
+s_load_dword s5, ttmp[10:11], s2
+// CHECK: [0x02,0xfa,0x02,0xc0]
+
+s_load_dword s5, s[2:3], s103
+// CHECK: [0x67,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], flat_scratch_lo
+// CHECK: [0x68,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], flat_scratch_hi
+// CHECK: [0x69,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], vcc_lo
+// CHECK: [0x6a,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], vcc_hi
+// CHECK: [0x6b,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], tba_lo
+// CHECK: [0x6c,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], tba_hi
+// CHECK: [0x6d,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], tma_lo
+// CHECK: [0x6e,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], tma_hi
+// CHECK: [0x6f,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], ttmp11
+// CHECK: [0x7b,0x82,0x02,0xc0]
+
+s_load_dword s5, s[2:3], 0xaf123456
+// CHECK: [0xff,0x82,0x02,0xc0,0x56,0x34,0x12,0xaf]
+
+s_load_dword s5, s[2:3], 0x3f717273
+// CHECK: [0xff,0x82,0x02,0xc0,0x73,0x72,0x71,0x3f]
+
+s_load_dword s5, s[2:3], 0x7f
+// CHECK: [0x7f,0x83,0x02,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x46,0xc0]
+
+s_load_dwordx2 s[102:103], s[2:3], s2
+// CHECK: [0x02,0x02,0x73,0xc0]
+
+s_load_dwordx2 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0x74,0xc0]
+
+s_load_dwordx2 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0x75,0xc0]
+
+s_load_dwordx2 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0x76,0xc0]
+
+s_load_dwordx2 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0x77,0xc0]
+
+s_load_dwordx2 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x7d,0xc0]
+
+s_load_dwordx2 s[10:11], s[4:5], s2
+// CHECK: [0x02,0x04,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[102:103], s2
+// CHECK: [0x02,0x66,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], flat_scratch, s2
+// CHECK: [0x02,0x68,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], vcc, s2
+// CHECK: [0x02,0x6a,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], tba, s2
+// CHECK: [0x02,0x6c,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], tma, s2
+// CHECK: [0x02,0x6e,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], ttmp[10:11], s2
+// CHECK: [0x02,0x7a,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], s103
+// CHECK: [0x67,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x68,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x69,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x6a,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x6b,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], tba_lo
+// CHECK: [0x6c,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], tba_hi
+// CHECK: [0x6d,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], tma_lo
+// CHECK: [0x6e,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], tma_hi
+// CHECK: [0x6f,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], ttmp11
+// CHECK: [0x7b,0x02,0x45,0xc0]
+
+s_load_dwordx2 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0xff,0x02,0x45,0xc0,0x56,0x34,0x12,0xaf]
+
+s_load_dwordx2 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0xff,0x02,0x45,0xc0,0x73,0x72,0x71,0x3f]
+
+s_load_dwordx2 s[10:11], s[2:3], 0x7f
+// CHECK: [0x7f,0x03,0x45,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[24:27], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0xc0]
+
+s_load_dwordx4 s[100:103], s[2:3], s2
+// CHECK: [0x02,0x02,0xb2,0xc0]
+
+s_load_dwordx4 ttmp[8:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xbc,0xc0]
+
+s_load_dwordx4 s[20:23], s[4:5], s2
+// CHECK: [0x02,0x04,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[102:103], s2
+// CHECK: [0x02,0x66,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], flat_scratch, s2
+// CHECK: [0x02,0x68,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], vcc, s2
+// CHECK: [0x02,0x6a,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], tba, s2
+// CHECK: [0x02,0x6c,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], tma, s2
+// CHECK: [0x02,0x6e,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], ttmp[10:11], s2
+// CHECK: [0x02,0x7a,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], s103
+// CHECK: [0x67,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], flat_scratch_lo
+// CHECK: [0x68,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], flat_scratch_hi
+// CHECK: [0x69,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], vcc_lo
+// CHECK: [0x6a,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], vcc_hi
+// CHECK: [0x6b,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], tba_lo
+// CHECK: [0x6c,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], tba_hi
+// CHECK: [0x6d,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], tma_lo
+// CHECK: [0x6e,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], tma_hi
+// CHECK: [0x6f,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], ttmp11
+// CHECK: [0x7b,0x02,0x8a,0xc0]
+
+s_load_dwordx4 s[20:23], s[2:3], 0xaf123456
+// CHECK: [0xff,0x02,0x8a,0xc0,0x56,0x34,0x12,0xaf]
+
+s_load_dwordx4 s[20:23], s[2:3], 0x3f717273
+// CHECK: [0xff,0x02,0x8a,0xc0,0x73,0x72,0x71,0x3f]
+
+s_load_dwordx4 s[20:23], s[2:3], 0x7f
+// CHECK: [0x7f,0x03,0x8a,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], s2
+// CHECK: [0x02,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[24:31], s[2:3], s2
+// CHECK: [0x02,0x02,0xcc,0xc0]
+
+s_load_dwordx8 s[96:103], s[2:3], s2
+// CHECK: [0x02,0x02,0xf0,0xc0]
+
+s_load_dwordx8 ttmp[4:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0xc0]
+
+s_load_dwordx8 s[20:27], s[4:5], s2
+// CHECK: [0x02,0x04,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[102:103], s2
+// CHECK: [0x02,0x66,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], flat_scratch, s2
+// CHECK: [0x02,0x68,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], vcc, s2
+// CHECK: [0x02,0x6a,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], tba, s2
+// CHECK: [0x02,0x6c,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], tma, s2
+// CHECK: [0x02,0x6e,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], ttmp[10:11], s2
+// CHECK: [0x02,0x7a,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], s103
+// CHECK: [0x67,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], flat_scratch_lo
+// CHECK: [0x68,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], flat_scratch_hi
+// CHECK: [0x69,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], vcc_lo
+// CHECK: [0x6a,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], vcc_hi
+// CHECK: [0x6b,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], tba_lo
+// CHECK: [0x6c,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], tba_hi
+// CHECK: [0x6d,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], tma_lo
+// CHECK: [0x6e,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], tma_hi
+// CHECK: [0x6f,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], ttmp11
+// CHECK: [0x7b,0x02,0xca,0xc0]
+
+s_load_dwordx8 s[20:27], s[2:3], 0xaf123456
+// CHECK: [0xff,0x02,0xca,0xc0,0x56,0x34,0x12,0xaf]
+
+s_load_dwordx8 s[20:27], s[2:3], 0x3f717273
+// CHECK: [0xff,0x02,0xca,0xc0,0x73,0x72,0x71,0x3f]
+
+s_load_dwordx8 s[20:27], s[2:3], 0x7f
+// CHECK: [0x7f,0x03,0xca,0xc0]
+
+s_load_dwordx16 s[20:35], s[2:3], s2
+// CHECK: [0x02,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[24:39], s[2:3], s2
+// CHECK: [0x02,0x02,0x0c,0xc1]
+
+s_load_dwordx16 s[88:103], s[2:3], s2
+// CHECK: [0x02,0x02,0x2c,0xc1]
+
+s_load_dwordx16 s[20:35], s[4:5], s2
+// CHECK: [0x02,0x04,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[102:103], s2
+// CHECK: [0x02,0x66,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], flat_scratch, s2
+// CHECK: [0x02,0x68,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], vcc, s2
+// CHECK: [0x02,0x6a,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], tba, s2
+// CHECK: [0x02,0x6c,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], tma, s2
+// CHECK: [0x02,0x6e,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], ttmp[10:11], s2
+// CHECK: [0x02,0x7a,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], s103
+// CHECK: [0x67,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], flat_scratch_lo
+// CHECK: [0x68,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], flat_scratch_hi
+// CHECK: [0x69,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], vcc_lo
+// CHECK: [0x6a,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], vcc_hi
+// CHECK: [0x6b,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], tba_lo
+// CHECK: [0x6c,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], tba_hi
+// CHECK: [0x6d,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], tma_lo
+// CHECK: [0x6e,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], tma_hi
+// CHECK: [0x6f,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], ttmp11
+// CHECK: [0x7b,0x02,0x0a,0xc1]
+
+s_load_dwordx16 s[20:35], s[2:3], 0xaf123456
+// CHECK: [0xff,0x02,0x0a,0xc1,0x56,0x34,0x12,0xaf]
+
+s_load_dwordx16 s[20:35], s[2:3], 0x3f717273
+// CHECK: [0xff,0x02,0x0a,0xc1,0x73,0x72,0x71,0x3f]
+
+s_load_dwordx16 s[20:35], s[2:3], 0x7f
+// CHECK: [0x7f,0x03,0x0a,0xc1]
+
+s_buffer_load_dword s5, s[4:7], s2
+// CHECK: [0x02,0x84,0x02,0xc2]
+
+s_buffer_load_dword s103, s[4:7], s2
+// CHECK: [0x02,0x84,0x33,0xc2]
+
+s_buffer_load_dword flat_scratch_lo, s[4:7], s2
+// CHECK: [0x02,0x04,0x34,0xc2]
+
+s_buffer_load_dword flat_scratch_hi, s[4:7], s2
+// CHECK: [0x02,0x84,0x34,0xc2]
+
+s_buffer_load_dword vcc_lo, s[4:7], s2
+// CHECK: [0x02,0x04,0x35,0xc2]
+
+s_buffer_load_dword vcc_hi, s[4:7], s2
+// CHECK: [0x02,0x84,0x35,0xc2]
+
+s_buffer_load_dword tba_lo, s[4:7], s2
+// CHECK: [0x02,0x04,0x36,0xc2]
+
+s_buffer_load_dword tba_hi, s[4:7], s2
+// CHECK: [0x02,0x84,0x36,0xc2]
+
+s_buffer_load_dword tma_lo, s[4:7], s2
+// CHECK: [0x02,0x04,0x37,0xc2]
+
+s_buffer_load_dword tma_hi, s[4:7], s2
+// CHECK: [0x02,0x84,0x37,0xc2]
+
+s_buffer_load_dword ttmp11, s[4:7], s2
+// CHECK: [0x02,0x84,0x3d,0xc2]
+
+s_buffer_load_dword s5, s[8:11], s2
+// CHECK: [0x02,0x88,0x02,0xc2]
+
+s_buffer_load_dword s5, s[100:103], s2
+// CHECK: [0x02,0xe4,0x02,0xc2]
+
+s_buffer_load_dword s5, ttmp[8:11], s2
+// CHECK: [0x02,0xf8,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], s103
+// CHECK: [0x67,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], flat_scratch_lo
+// CHECK: [0x68,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], flat_scratch_hi
+// CHECK: [0x69,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], vcc_lo
+// CHECK: [0x6a,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], vcc_hi
+// CHECK: [0x6b,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], tba_lo
+// CHECK: [0x6c,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], tba_hi
+// CHECK: [0x6d,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], tma_lo
+// CHECK: [0x6e,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], tma_hi
+// CHECK: [0x6f,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], ttmp11
+// CHECK: [0x7b,0x84,0x02,0xc2]
+
+s_buffer_load_dword s5, s[4:7], 0xaf123456
+// CHECK: [0xff,0x84,0x02,0xc2,0x56,0x34,0x12,0xaf]
+
+s_buffer_load_dword s5, s[4:7], 0x3f717273
+// CHECK: [0xff,0x84,0x02,0xc2,0x73,0x72,0x71,0x3f]
+
+s_buffer_load_dword s5, s[4:7], 0x7f
+// CHECK: [0x7f,0x85,0x02,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s2
+// CHECK: [0x02,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[12:13], s[4:7], s2
+// CHECK: [0x02,0x04,0x46,0xc2]
+
+s_buffer_load_dwordx2 s[102:103], s[4:7], s2
+// CHECK: [0x02,0x04,0x73,0xc2]
+
+s_buffer_load_dwordx2 flat_scratch, s[4:7], s2
+// CHECK: [0x02,0x04,0x74,0xc2]
+
+s_buffer_load_dwordx2 vcc, s[4:7], s2
+// CHECK: [0x02,0x04,0x75,0xc2]
+
+s_buffer_load_dwordx2 tba, s[4:7], s2
+// CHECK: [0x02,0x04,0x76,0xc2]
+
+s_buffer_load_dwordx2 tma, s[4:7], s2
+// CHECK: [0x02,0x04,0x77,0xc2]
+
+s_buffer_load_dwordx2 ttmp[10:11], s[4:7], s2
+// CHECK: [0x02,0x04,0x7d,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[8:11], s2
+// CHECK: [0x02,0x08,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[100:103], s2
+// CHECK: [0x02,0x64,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], ttmp[8:11], s2
+// CHECK: [0x02,0x78,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s103
+// CHECK: [0x67,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x68,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x69,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x6a,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x6b,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], tba_lo
+// CHECK: [0x6c,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], tba_hi
+// CHECK: [0x6d,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], tma_lo
+// CHECK: [0x6e,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], tma_hi
+// CHECK: [0x6f,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], ttmp11
+// CHECK: [0x7b,0x04,0x45,0xc2]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], 0xaf123456
+// CHECK: [0xff,0x04,0x45,0xc2,0x56,0x34,0x12,0xaf]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], 0x3f717273
+// CHECK: [0xff,0x04,0x45,0xc2,0x73,0x72,0x71,0x3f]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], 0x7f
+// CHECK: [0x7f,0x05,0x45,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s2
+// CHECK: [0x02,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[24:27], s[4:7], s2
+// CHECK: [0x02,0x04,0x8c,0xc2]
+
+s_buffer_load_dwordx4 s[100:103], s[4:7], s2
+// CHECK: [0x02,0x04,0xb2,0xc2]
+
+s_buffer_load_dwordx4 ttmp[8:11], s[4:7], s2
+// CHECK: [0x02,0x04,0xbc,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[8:11], s2
+// CHECK: [0x02,0x08,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[100:103], s2
+// CHECK: [0x02,0x64,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], ttmp[8:11], s2
+// CHECK: [0x02,0x78,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s103
+// CHECK: [0x67,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_lo
+// CHECK: [0x68,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_hi
+// CHECK: [0x69,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_lo
+// CHECK: [0x6a,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
+// CHECK: [0x6b,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], tba_lo
+// CHECK: [0x6c,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], tba_hi
+// CHECK: [0x6d,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], tma_lo
+// CHECK: [0x6e,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], tma_hi
+// CHECK: [0x6f,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], ttmp11
+// CHECK: [0x7b,0x04,0x8a,0xc2]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], 0xaf123456
+// CHECK: [0xff,0x04,0x8a,0xc2,0x56,0x34,0x12,0xaf]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], 0x3f717273
+// CHECK: [0xff,0x04,0x8a,0xc2,0x73,0x72,0x71,0x3f]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], 0x7f
+// CHECK: [0x7f,0x05,0x8a,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s2
+// CHECK: [0x02,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[24:31], s[4:7], s2
+// CHECK: [0x02,0x04,0xcc,0xc2]
+
+s_buffer_load_dwordx8 s[96:103], s[4:7], s2
+// CHECK: [0x02,0x04,0xf0,0xc2]
+
+s_buffer_load_dwordx8 ttmp[4:11], s[4:7], s2
+// CHECK: [0x02,0x04,0xfa,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[8:11], s2
+// CHECK: [0x02,0x08,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[100:103], s2
+// CHECK: [0x02,0x64,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], ttmp[8:11], s2
+// CHECK: [0x02,0x78,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s103
+// CHECK: [0x67,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_lo
+// CHECK: [0x68,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_hi
+// CHECK: [0x69,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_lo
+// CHECK: [0x6a,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
+// CHECK: [0x6b,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], tba_lo
+// CHECK: [0x6c,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], tba_hi
+// CHECK: [0x6d,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], tma_lo
+// CHECK: [0x6e,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], tma_hi
+// CHECK: [0x6f,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], ttmp11
+// CHECK: [0x7b,0x04,0xca,0xc2]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], 0xaf123456
+// CHECK: [0xff,0x04,0xca,0xc2,0x56,0x34,0x12,0xaf]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], 0x3f717273
+// CHECK: [0xff,0x04,0xca,0xc2,0x73,0x72,0x71,0x3f]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], 0x7f
+// CHECK: [0x7f,0x05,0xca,0xc2]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s2
+// CHECK: [0x02,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[24:39], s[4:7], s2
+// CHECK: [0x02,0x04,0x0c,0xc3]
+
+s_buffer_load_dwordx16 s[88:103], s[4:7], s2
+// CHECK: [0x02,0x04,0x2c,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[8:11], s2
+// CHECK: [0x02,0x08,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[100:103], s2
+// CHECK: [0x02,0x64,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], ttmp[8:11], s2
+// CHECK: [0x02,0x78,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s103
+// CHECK: [0x67,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_lo
+// CHECK: [0x68,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_hi
+// CHECK: [0x69,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_lo
+// CHECK: [0x6a,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
+// CHECK: [0x6b,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], tba_lo
+// CHECK: [0x6c,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], tba_hi
+// CHECK: [0x6d,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], tma_lo
+// CHECK: [0x6e,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], tma_hi
+// CHECK: [0x6f,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], ttmp11
+// CHECK: [0x7b,0x04,0x0a,0xc3]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], 0xaf123456
+// CHECK: [0xff,0x04,0x0a,0xc3,0x56,0x34,0x12,0xaf]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], 0x3f717273
+// CHECK: [0xff,0x04,0x0a,0xc3,0x73,0x72,0x71,0x3f]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], 0x7f
+// CHECK: [0x7f,0x05,0x0a,0xc3]
+
+s_dcache_inv_vol
+// CHECK: [0x00,0x00,0x40,0xc7]
+
+s_memtime s[10:11]
+// CHECK: [0x00,0x00,0x85,0xc7]
+
+s_memtime s[12:13]
+// CHECK: [0x00,0x00,0x86,0xc7]
+
+s_memtime s[102:103]
+// CHECK: [0x00,0x00,0xb3,0xc7]
+
+s_memtime flat_scratch
+// CHECK: [0x00,0x00,0xb4,0xc7]
+
+s_memtime vcc
+// CHECK: [0x00,0x00,0xb5,0xc7]
+
+s_memtime tba
+// CHECK: [0x00,0x00,0xb6,0xc7]
+
+s_memtime tma
+// CHECK: [0x00,0x00,0xb7,0xc7]
+
+s_memtime ttmp[10:11]
+// CHECK: [0x00,0x00,0xbd,0xc7]
+
+s_dcache_inv
+// CHECK: [0x00,0x00,0xc0,0xc7]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx7_asm_sop1.s
new file mode 100644
index 0000000000000..ecff976fe54ee
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sop1.s
@@ -0,0 +1,4096 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+s_mov_b32 s5, s1
+// CHECK: [0x01,0x03,0x85,0xbe]
+
+s_mov_b32 s103, s1
+// CHECK: [0x01,0x03,0xe7,0xbe]
+
+s_mov_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x03,0xe8,0xbe]
+
+s_mov_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x03,0xe9,0xbe]
+
+s_mov_b32 vcc_lo, s1
+// CHECK: [0x01,0x03,0xea,0xbe]
+
+s_mov_b32 vcc_hi, s1
+// CHECK: [0x01,0x03,0xeb,0xbe]
+
+s_mov_b32 tba_lo, s1
+// CHECK: [0x01,0x03,0xec,0xbe]
+
+s_mov_b32 tba_hi, s1
+// CHECK: [0x01,0x03,0xed,0xbe]
+
+s_mov_b32 tma_lo, s1
+// CHECK: [0x01,0x03,0xee,0xbe]
+
+s_mov_b32 tma_hi, s1
+// CHECK: [0x01,0x03,0xef,0xbe]
+
+s_mov_b32 ttmp11, s1
+// CHECK: [0x01,0x03,0xfb,0xbe]
+
+s_mov_b32 m0, s1
+// CHECK: [0x01,0x03,0xfc,0xbe]
+
+s_mov_b32 exec_lo, s1
+// CHECK: [0x01,0x03,0xfe,0xbe]
+
+s_mov_b32 exec_hi, s1
+// CHECK: [0x01,0x03,0xff,0xbe]
+
+s_mov_b32 s5, s103
+// CHECK: [0x67,0x03,0x85,0xbe]
+
+s_mov_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x03,0x85,0xbe]
+
+s_mov_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x03,0x85,0xbe]
+
+s_mov_b32 s5, vcc_lo
+// CHECK: [0x6a,0x03,0x85,0xbe]
+
+s_mov_b32 s5, vcc_hi
+// CHECK: [0x6b,0x03,0x85,0xbe]
+
+s_mov_b32 s5, tba_lo
+// CHECK: [0x6c,0x03,0x85,0xbe]
+
+s_mov_b32 s5, tba_hi
+// CHECK: [0x6d,0x03,0x85,0xbe]
+
+s_mov_b32 s5, tma_lo
+// CHECK: [0x6e,0x03,0x85,0xbe]
+
+s_mov_b32 s5, tma_hi
+// CHECK: [0x6f,0x03,0x85,0xbe]
+
+s_mov_b32 s5, ttmp11
+// CHECK: [0x7b,0x03,0x85,0xbe]
+
+s_mov_b32 s5, m0
+// CHECK: [0x7c,0x03,0x85,0xbe]
+
+s_mov_b32 s5, exec_lo
+// CHECK: [0x7e,0x03,0x85,0xbe]
+
+s_mov_b32 s5, exec_hi
+// CHECK: [0x7f,0x03,0x85,0xbe]
+
+s_mov_b32 s5, 0
+// CHECK: [0x80,0x03,0x85,0xbe]
+
+s_mov_b32 s5, -1
+// CHECK: [0xc1,0x03,0x85,0xbe]
+
+s_mov_b32 s5, 0.5
+// CHECK: [0xf0,0x03,0x85,0xbe]
+
+s_mov_b32 s5, -4.0
+// CHECK: [0xf7,0x03,0x85,0xbe]
+
+s_mov_b32 s5, src_vccz
+// CHECK: [0xfb,0x03,0x85,0xbe]
+
+s_mov_b32 s5, src_execz
+// CHECK: [0xfc,0x03,0x85,0xbe]
+
+s_mov_b32 s5, src_scc
+// CHECK: [0xfd,0x03,0x85,0xbe]
+
+s_mov_b32 s5, 0xaf123456
+// CHECK: [0xff,0x03,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_mov_b32 s5, 0x3f717273
+// CHECK: [0xff,0x03,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_mov_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x04,0x8a,0xbe]
+
+s_mov_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x04,0x8c,0xbe]
+
+s_mov_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x04,0xe6,0xbe]
+
+s_mov_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x04,0xe8,0xbe]
+
+s_mov_b64 vcc, s[2:3]
+// CHECK: [0x02,0x04,0xea,0xbe]
+
+s_mov_b64 tba, s[2:3]
+// CHECK: [0x02,0x04,0xec,0xbe]
+
+s_mov_b64 tma, s[2:3]
+// CHECK: [0x02,0x04,0xee,0xbe]
+
+s_mov_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x04,0xfa,0xbe]
+
+s_mov_b64 exec, s[2:3]
+// CHECK: [0x02,0x04,0xfe,0xbe]
+
+s_mov_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], vcc
+// CHECK: [0x6a,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], tba
+// CHECK: [0x6c,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], tma
+// CHECK: [0x6e,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], exec
+// CHECK: [0x7e,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], 0
+// CHECK: [0x80,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], -1
+// CHECK: [0xc1,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x04,0x8a,0xbe]
+
+s_mov_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x04,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_mov_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x04,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cmov_b32 s5, s1
+// CHECK: [0x01,0x05,0x85,0xbe]
+
+s_cmov_b32 s103, s1
+// CHECK: [0x01,0x05,0xe7,0xbe]
+
+s_cmov_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x05,0xe8,0xbe]
+
+s_cmov_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x05,0xe9,0xbe]
+
+s_cmov_b32 vcc_lo, s1
+// CHECK: [0x01,0x05,0xea,0xbe]
+
+s_cmov_b32 vcc_hi, s1
+// CHECK: [0x01,0x05,0xeb,0xbe]
+
+s_cmov_b32 tba_lo, s1
+// CHECK: [0x01,0x05,0xec,0xbe]
+
+s_cmov_b32 tba_hi, s1
+// CHECK: [0x01,0x05,0xed,0xbe]
+
+s_cmov_b32 tma_lo, s1
+// CHECK: [0x01,0x05,0xee,0xbe]
+
+s_cmov_b32 tma_hi, s1
+// CHECK: [0x01,0x05,0xef,0xbe]
+
+s_cmov_b32 ttmp11, s1
+// CHECK: [0x01,0x05,0xfb,0xbe]
+
+s_cmov_b32 m0, s1
+// CHECK: [0x01,0x05,0xfc,0xbe]
+
+s_cmov_b32 exec_lo, s1
+// CHECK: [0x01,0x05,0xfe,0xbe]
+
+s_cmov_b32 exec_hi, s1
+// CHECK: [0x01,0x05,0xff,0xbe]
+
+s_cmov_b32 s5, s103
+// CHECK: [0x67,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, vcc_lo
+// CHECK: [0x6a,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, vcc_hi
+// CHECK: [0x6b,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, tba_lo
+// CHECK: [0x6c,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, tba_hi
+// CHECK: [0x6d,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, tma_lo
+// CHECK: [0x6e,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, tma_hi
+// CHECK: [0x6f,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, ttmp11
+// CHECK: [0x7b,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, m0
+// CHECK: [0x7c,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, exec_lo
+// CHECK: [0x7e,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, exec_hi
+// CHECK: [0x7f,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, 0
+// CHECK: [0x80,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, -1
+// CHECK: [0xc1,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, 0.5
+// CHECK: [0xf0,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, -4.0
+// CHECK: [0xf7,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, src_vccz
+// CHECK: [0xfb,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, src_execz
+// CHECK: [0xfc,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, src_scc
+// CHECK: [0xfd,0x05,0x85,0xbe]
+
+s_cmov_b32 s5, 0xaf123456
+// CHECK: [0xff,0x05,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_cmov_b32 s5, 0x3f717273
+// CHECK: [0xff,0x05,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cmov_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x06,0x8c,0xbe]
+
+s_cmov_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x06,0xe6,0xbe]
+
+s_cmov_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x06,0xe8,0xbe]
+
+s_cmov_b64 vcc, s[2:3]
+// CHECK: [0x02,0x06,0xea,0xbe]
+
+s_cmov_b64 tba, s[2:3]
+// CHECK: [0x02,0x06,0xec,0xbe]
+
+s_cmov_b64 tma, s[2:3]
+// CHECK: [0x02,0x06,0xee,0xbe]
+
+s_cmov_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x06,0xfa,0xbe]
+
+s_cmov_b64 exec, s[2:3]
+// CHECK: [0x02,0x06,0xfe,0xbe]
+
+s_cmov_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], vcc
+// CHECK: [0x6a,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], tba
+// CHECK: [0x6c,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], tma
+// CHECK: [0x6e,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], exec
+// CHECK: [0x7e,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], 0
+// CHECK: [0x80,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], -1
+// CHECK: [0xc1,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x06,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x06,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_cmov_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x06,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_not_b32 s5, s1
+// CHECK: [0x01,0x07,0x85,0xbe]
+
+s_not_b32 s103, s1
+// CHECK: [0x01,0x07,0xe7,0xbe]
+
+s_not_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x07,0xe8,0xbe]
+
+s_not_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x07,0xe9,0xbe]
+
+s_not_b32 vcc_lo, s1
+// CHECK: [0x01,0x07,0xea,0xbe]
+
+s_not_b32 vcc_hi, s1
+// CHECK: [0x01,0x07,0xeb,0xbe]
+
+s_not_b32 tba_lo, s1
+// CHECK: [0x01,0x07,0xec,0xbe]
+
+s_not_b32 tba_hi, s1
+// CHECK: [0x01,0x07,0xed,0xbe]
+
+s_not_b32 tma_lo, s1
+// CHECK: [0x01,0x07,0xee,0xbe]
+
+s_not_b32 tma_hi, s1
+// CHECK: [0x01,0x07,0xef,0xbe]
+
+s_not_b32 ttmp11, s1
+// CHECK: [0x01,0x07,0xfb,0xbe]
+
+s_not_b32 m0, s1
+// CHECK: [0x01,0x07,0xfc,0xbe]
+
+s_not_b32 exec_lo, s1
+// CHECK: [0x01,0x07,0xfe,0xbe]
+
+s_not_b32 exec_hi, s1
+// CHECK: [0x01,0x07,0xff,0xbe]
+
+s_not_b32 s5, s103
+// CHECK: [0x67,0x07,0x85,0xbe]
+
+s_not_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x07,0x85,0xbe]
+
+s_not_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x07,0x85,0xbe]
+
+s_not_b32 s5, vcc_lo
+// CHECK: [0x6a,0x07,0x85,0xbe]
+
+s_not_b32 s5, vcc_hi
+// CHECK: [0x6b,0x07,0x85,0xbe]
+
+s_not_b32 s5, tba_lo
+// CHECK: [0x6c,0x07,0x85,0xbe]
+
+s_not_b32 s5, tba_hi
+// CHECK: [0x6d,0x07,0x85,0xbe]
+
+s_not_b32 s5, tma_lo
+// CHECK: [0x6e,0x07,0x85,0xbe]
+
+s_not_b32 s5, tma_hi
+// CHECK: [0x6f,0x07,0x85,0xbe]
+
+s_not_b32 s5, ttmp11
+// CHECK: [0x7b,0x07,0x85,0xbe]
+
+s_not_b32 s5, m0
+// CHECK: [0x7c,0x07,0x85,0xbe]
+
+s_not_b32 s5, exec_lo
+// CHECK: [0x7e,0x07,0x85,0xbe]
+
+s_not_b32 s5, exec_hi
+// CHECK: [0x7f,0x07,0x85,0xbe]
+
+s_not_b32 s5, 0
+// CHECK: [0x80,0x07,0x85,0xbe]
+
+s_not_b32 s5, -1
+// CHECK: [0xc1,0x07,0x85,0xbe]
+
+s_not_b32 s5, 0.5
+// CHECK: [0xf0,0x07,0x85,0xbe]
+
+s_not_b32 s5, -4.0
+// CHECK: [0xf7,0x07,0x85,0xbe]
+
+s_not_b32 s5, src_vccz
+// CHECK: [0xfb,0x07,0x85,0xbe]
+
+s_not_b32 s5, src_execz
+// CHECK: [0xfc,0x07,0x85,0xbe]
+
+s_not_b32 s5, src_scc
+// CHECK: [0xfd,0x07,0x85,0xbe]
+
+s_not_b32 s5, 0xaf123456
+// CHECK: [0xff,0x07,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_not_b32 s5, 0x3f717273
+// CHECK: [0xff,0x07,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_not_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x08,0x8a,0xbe]
+
+s_not_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x08,0x8c,0xbe]
+
+s_not_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x08,0xe6,0xbe]
+
+s_not_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x08,0xe8,0xbe]
+
+s_not_b64 vcc, s[2:3]
+// CHECK: [0x02,0x08,0xea,0xbe]
+
+s_not_b64 tba, s[2:3]
+// CHECK: [0x02,0x08,0xec,0xbe]
+
+s_not_b64 tma, s[2:3]
+// CHECK: [0x02,0x08,0xee,0xbe]
+
+s_not_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x08,0xfa,0xbe]
+
+s_not_b64 exec, s[2:3]
+// CHECK: [0x02,0x08,0xfe,0xbe]
+
+s_not_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], vcc
+// CHECK: [0x6a,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], tba
+// CHECK: [0x6c,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], tma
+// CHECK: [0x6e,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], exec
+// CHECK: [0x7e,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], 0
+// CHECK: [0x80,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], -1
+// CHECK: [0xc1,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x08,0x8a,0xbe]
+
+s_not_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x08,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_not_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x08,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_wqm_b32 s5, s1
+// CHECK: [0x01,0x09,0x85,0xbe]
+
+s_wqm_b32 s103, s1
+// CHECK: [0x01,0x09,0xe7,0xbe]
+
+s_wqm_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x09,0xe8,0xbe]
+
+s_wqm_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x09,0xe9,0xbe]
+
+s_wqm_b32 vcc_lo, s1
+// CHECK: [0x01,0x09,0xea,0xbe]
+
+s_wqm_b32 vcc_hi, s1
+// CHECK: [0x01,0x09,0xeb,0xbe]
+
+s_wqm_b32 tba_lo, s1
+// CHECK: [0x01,0x09,0xec,0xbe]
+
+s_wqm_b32 tba_hi, s1
+// CHECK: [0x01,0x09,0xed,0xbe]
+
+s_wqm_b32 tma_lo, s1
+// CHECK: [0x01,0x09,0xee,0xbe]
+
+s_wqm_b32 tma_hi, s1
+// CHECK: [0x01,0x09,0xef,0xbe]
+
+s_wqm_b32 ttmp11, s1
+// CHECK: [0x01,0x09,0xfb,0xbe]
+
+s_wqm_b32 m0, s1
+// CHECK: [0x01,0x09,0xfc,0xbe]
+
+s_wqm_b32 exec_lo, s1
+// CHECK: [0x01,0x09,0xfe,0xbe]
+
+s_wqm_b32 exec_hi, s1
+// CHECK: [0x01,0x09,0xff,0xbe]
+
+s_wqm_b32 s5, s103
+// CHECK: [0x67,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, vcc_lo
+// CHECK: [0x6a,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, vcc_hi
+// CHECK: [0x6b,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, tba_lo
+// CHECK: [0x6c,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, tba_hi
+// CHECK: [0x6d,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, tma_lo
+// CHECK: [0x6e,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, tma_hi
+// CHECK: [0x6f,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, ttmp11
+// CHECK: [0x7b,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, m0
+// CHECK: [0x7c,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, exec_lo
+// CHECK: [0x7e,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, exec_hi
+// CHECK: [0x7f,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, 0
+// CHECK: [0x80,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, -1
+// CHECK: [0xc1,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, 0.5
+// CHECK: [0xf0,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, -4.0
+// CHECK: [0xf7,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, src_vccz
+// CHECK: [0xfb,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, src_execz
+// CHECK: [0xfc,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, src_scc
+// CHECK: [0xfd,0x09,0x85,0xbe]
+
+s_wqm_b32 s5, 0xaf123456
+// CHECK: [0xff,0x09,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_wqm_b32 s5, 0x3f717273
+// CHECK: [0xff,0x09,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_wqm_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x0a,0x8c,0xbe]
+
+s_wqm_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x0a,0xe6,0xbe]
+
+s_wqm_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x0a,0xe8,0xbe]
+
+s_wqm_b64 vcc, s[2:3]
+// CHECK: [0x02,0x0a,0xea,0xbe]
+
+s_wqm_b64 tba, s[2:3]
+// CHECK: [0x02,0x0a,0xec,0xbe]
+
+s_wqm_b64 tma, s[2:3]
+// CHECK: [0x02,0x0a,0xee,0xbe]
+
+s_wqm_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x0a,0xfa,0xbe]
+
+s_wqm_b64 exec, s[2:3]
+// CHECK: [0x02,0x0a,0xfe,0xbe]
+
+s_wqm_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], vcc
+// CHECK: [0x6a,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], tba
+// CHECK: [0x6c,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], tma
+// CHECK: [0x6e,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], exec
+// CHECK: [0x7e,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], 0
+// CHECK: [0x80,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], -1
+// CHECK: [0xc1,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x0a,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x0a,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_wqm_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x0a,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_brev_b32 s5, s1
+// CHECK: [0x01,0x0b,0x85,0xbe]
+
+s_brev_b32 s103, s1
+// CHECK: [0x01,0x0b,0xe7,0xbe]
+
+s_brev_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x0b,0xe8,0xbe]
+
+s_brev_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x0b,0xe9,0xbe]
+
+s_brev_b32 vcc_lo, s1
+// CHECK: [0x01,0x0b,0xea,0xbe]
+
+s_brev_b32 vcc_hi, s1
+// CHECK: [0x01,0x0b,0xeb,0xbe]
+
+s_brev_b32 tba_lo, s1
+// CHECK: [0x01,0x0b,0xec,0xbe]
+
+s_brev_b32 tba_hi, s1
+// CHECK: [0x01,0x0b,0xed,0xbe]
+
+s_brev_b32 tma_lo, s1
+// CHECK: [0x01,0x0b,0xee,0xbe]
+
+s_brev_b32 tma_hi, s1
+// CHECK: [0x01,0x0b,0xef,0xbe]
+
+s_brev_b32 ttmp11, s1
+// CHECK: [0x01,0x0b,0xfb,0xbe]
+
+s_brev_b32 m0, s1
+// CHECK: [0x01,0x0b,0xfc,0xbe]
+
+s_brev_b32 exec_lo, s1
+// CHECK: [0x01,0x0b,0xfe,0xbe]
+
+s_brev_b32 exec_hi, s1
+// CHECK: [0x01,0x0b,0xff,0xbe]
+
+s_brev_b32 s5, s103
+// CHECK: [0x67,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, vcc_lo
+// CHECK: [0x6a,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, vcc_hi
+// CHECK: [0x6b,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, tba_lo
+// CHECK: [0x6c,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, tba_hi
+// CHECK: [0x6d,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, tma_lo
+// CHECK: [0x6e,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, tma_hi
+// CHECK: [0x6f,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, ttmp11
+// CHECK: [0x7b,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, m0
+// CHECK: [0x7c,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, exec_lo
+// CHECK: [0x7e,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, exec_hi
+// CHECK: [0x7f,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, 0
+// CHECK: [0x80,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, -1
+// CHECK: [0xc1,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, 0.5
+// CHECK: [0xf0,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, -4.0
+// CHECK: [0xf7,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, src_vccz
+// CHECK: [0xfb,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, src_execz
+// CHECK: [0xfc,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, src_scc
+// CHECK: [0xfd,0x0b,0x85,0xbe]
+
+s_brev_b32 s5, 0xaf123456
+// CHECK: [0xff,0x0b,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_brev_b32 s5, 0x3f717273
+// CHECK: [0xff,0x0b,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_brev_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x0c,0x8c,0xbe]
+
+s_brev_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x0c,0xe6,0xbe]
+
+s_brev_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x0c,0xe8,0xbe]
+
+s_brev_b64 vcc, s[2:3]
+// CHECK: [0x02,0x0c,0xea,0xbe]
+
+s_brev_b64 tba, s[2:3]
+// CHECK: [0x02,0x0c,0xec,0xbe]
+
+s_brev_b64 tma, s[2:3]
+// CHECK: [0x02,0x0c,0xee,0xbe]
+
+s_brev_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x0c,0xfa,0xbe]
+
+s_brev_b64 exec, s[2:3]
+// CHECK: [0x02,0x0c,0xfe,0xbe]
+
+s_brev_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], vcc
+// CHECK: [0x6a,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], tba
+// CHECK: [0x6c,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], tma
+// CHECK: [0x6e,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], exec
+// CHECK: [0x7e,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], 0
+// CHECK: [0x80,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], -1
+// CHECK: [0xc1,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x0c,0x8a,0xbe]
+
+s_brev_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x0c,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_brev_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x0c,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt0_i32_b32 s5, s1
+// CHECK: [0x01,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s103, s1
+// CHECK: [0x01,0x0d,0xe7,0xbe]
+
+s_bcnt0_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x0d,0xe8,0xbe]
+
+s_bcnt0_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x0d,0xe9,0xbe]
+
+s_bcnt0_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x0d,0xea,0xbe]
+
+s_bcnt0_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x0d,0xeb,0xbe]
+
+s_bcnt0_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x0d,0xec,0xbe]
+
+s_bcnt0_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x0d,0xed,0xbe]
+
+s_bcnt0_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x0d,0xee,0xbe]
+
+s_bcnt0_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x0d,0xef,0xbe]
+
+s_bcnt0_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x0d,0xfb,0xbe]
+
+s_bcnt0_i32_b32 m0, s1
+// CHECK: [0x01,0x0d,0xfc,0xbe]
+
+s_bcnt0_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x0d,0xfe,0xbe]
+
+s_bcnt0_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x0d,0xff,0xbe]
+
+s_bcnt0_i32_b32 s5, s103
+// CHECK: [0x67,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, m0
+// CHECK: [0x7c,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, 0
+// CHECK: [0x80,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, -1
+// CHECK: [0xc1,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x0d,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x0d,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt0_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x0d,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt0_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s103, s[2:3]
+// CHECK: [0x02,0x0e,0xe7,0xbe]
+
+s_bcnt0_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x0e,0xe8,0xbe]
+
+s_bcnt0_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x0e,0xe9,0xbe]
+
+s_bcnt0_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x0e,0xea,0xbe]
+
+s_bcnt0_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x0e,0xeb,0xbe]
+
+s_bcnt0_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x0e,0xec,0xbe]
+
+s_bcnt0_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x0e,0xed,0xbe]
+
+s_bcnt0_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x0e,0xee,0xbe]
+
+s_bcnt0_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x0e,0xef,0xbe]
+
+s_bcnt0_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x0e,0xfb,0xbe]
+
+s_bcnt0_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x0e,0xfc,0xbe]
+
+s_bcnt0_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x0e,0xfe,0xbe]
+
+s_bcnt0_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x0e,0xff,0xbe]
+
+s_bcnt0_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, s[102:103]
+// CHECK: [0x66,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, flat_scratch
+// CHECK: [0x68,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, vcc
+// CHECK: [0x6a,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, tba
+// CHECK: [0x6c,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, tma
+// CHECK: [0x6e,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, exec
+// CHECK: [0x7e,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, 0
+// CHECK: [0x80,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, -1
+// CHECK: [0xc1,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x0e,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x0e,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt0_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x0e,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt1_i32_b32 s5, s1
+// CHECK: [0x01,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s103, s1
+// CHECK: [0x01,0x0f,0xe7,0xbe]
+
+s_bcnt1_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x0f,0xe8,0xbe]
+
+s_bcnt1_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x0f,0xe9,0xbe]
+
+s_bcnt1_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x0f,0xea,0xbe]
+
+s_bcnt1_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x0f,0xeb,0xbe]
+
+s_bcnt1_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x0f,0xec,0xbe]
+
+s_bcnt1_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x0f,0xed,0xbe]
+
+s_bcnt1_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x0f,0xee,0xbe]
+
+s_bcnt1_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x0f,0xef,0xbe]
+
+s_bcnt1_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x0f,0xfb,0xbe]
+
+s_bcnt1_i32_b32 m0, s1
+// CHECK: [0x01,0x0f,0xfc,0xbe]
+
+s_bcnt1_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x0f,0xfe,0xbe]
+
+s_bcnt1_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x0f,0xff,0xbe]
+
+s_bcnt1_i32_b32 s5, s103
+// CHECK: [0x67,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, m0
+// CHECK: [0x7c,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, 0
+// CHECK: [0x80,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, -1
+// CHECK: [0xc1,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x0f,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x0f,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt1_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x0f,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt1_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s103, s[2:3]
+// CHECK: [0x02,0x10,0xe7,0xbe]
+
+s_bcnt1_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x10,0xe8,0xbe]
+
+s_bcnt1_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x10,0xe9,0xbe]
+
+s_bcnt1_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x10,0xea,0xbe]
+
+s_bcnt1_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x10,0xeb,0xbe]
+
+s_bcnt1_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x10,0xec,0xbe]
+
+s_bcnt1_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x10,0xed,0xbe]
+
+s_bcnt1_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x10,0xee,0xbe]
+
+s_bcnt1_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x10,0xef,0xbe]
+
+s_bcnt1_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x10,0xfb,0xbe]
+
+s_bcnt1_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x10,0xfc,0xbe]
+
+s_bcnt1_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x10,0xfe,0xbe]
+
+s_bcnt1_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x10,0xff,0xbe]
+
+s_bcnt1_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, s[102:103]
+// CHECK: [0x66,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, flat_scratch
+// CHECK: [0x68,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, vcc
+// CHECK: [0x6a,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, tba
+// CHECK: [0x6c,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, tma
+// CHECK: [0x6e,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, exec
+// CHECK: [0x7e,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, 0
+// CHECK: [0x80,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, -1
+// CHECK: [0xc1,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x10,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x10,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt1_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x10,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff0_i32_b32 s5, s1
+// CHECK: [0x01,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s103, s1
+// CHECK: [0x01,0x11,0xe7,0xbe]
+
+s_ff0_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x11,0xe8,0xbe]
+
+s_ff0_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x11,0xe9,0xbe]
+
+s_ff0_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x11,0xea,0xbe]
+
+s_ff0_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x11,0xeb,0xbe]
+
+s_ff0_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x11,0xec,0xbe]
+
+s_ff0_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x11,0xed,0xbe]
+
+s_ff0_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x11,0xee,0xbe]
+
+s_ff0_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x11,0xef,0xbe]
+
+s_ff0_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x11,0xfb,0xbe]
+
+s_ff0_i32_b32 m0, s1
+// CHECK: [0x01,0x11,0xfc,0xbe]
+
+s_ff0_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x11,0xfe,0xbe]
+
+s_ff0_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x11,0xff,0xbe]
+
+s_ff0_i32_b32 s5, s103
+// CHECK: [0x67,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, m0
+// CHECK: [0x7c,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, 0
+// CHECK: [0x80,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, -1
+// CHECK: [0xc1,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x11,0x85,0xbe]
+
+s_ff0_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x11,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff0_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x11,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff0_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s103, s[2:3]
+// CHECK: [0x02,0x12,0xe7,0xbe]
+
+s_ff0_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x12,0xe8,0xbe]
+
+s_ff0_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x12,0xe9,0xbe]
+
+s_ff0_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x12,0xea,0xbe]
+
+s_ff0_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x12,0xeb,0xbe]
+
+s_ff0_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x12,0xec,0xbe]
+
+s_ff0_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x12,0xed,0xbe]
+
+s_ff0_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x12,0xee,0xbe]
+
+s_ff0_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x12,0xef,0xbe]
+
+s_ff0_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x12,0xfb,0xbe]
+
+s_ff0_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x12,0xfc,0xbe]
+
+s_ff0_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x12,0xfe,0xbe]
+
+s_ff0_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x12,0xff,0xbe]
+
+s_ff0_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, s[102:103]
+// CHECK: [0x66,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, flat_scratch
+// CHECK: [0x68,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, vcc
+// CHECK: [0x6a,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, tba
+// CHECK: [0x6c,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, tma
+// CHECK: [0x6e,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, exec
+// CHECK: [0x7e,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, 0
+// CHECK: [0x80,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, -1
+// CHECK: [0xc1,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x12,0x85,0xbe]
+
+s_ff0_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x12,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff0_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x12,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff1_i32_b32 s5, s1
+// CHECK: [0x01,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s103, s1
+// CHECK: [0x01,0x13,0xe7,0xbe]
+
+s_ff1_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x13,0xe8,0xbe]
+
+s_ff1_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x13,0xe9,0xbe]
+
+s_ff1_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x13,0xea,0xbe]
+
+s_ff1_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x13,0xeb,0xbe]
+
+s_ff1_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x13,0xec,0xbe]
+
+s_ff1_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x13,0xed,0xbe]
+
+s_ff1_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x13,0xee,0xbe]
+
+s_ff1_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x13,0xef,0xbe]
+
+s_ff1_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x13,0xfb,0xbe]
+
+s_ff1_i32_b32 m0, s1
+// CHECK: [0x01,0x13,0xfc,0xbe]
+
+s_ff1_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x13,0xfe,0xbe]
+
+s_ff1_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x13,0xff,0xbe]
+
+s_ff1_i32_b32 s5, s103
+// CHECK: [0x67,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, m0
+// CHECK: [0x7c,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, 0
+// CHECK: [0x80,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, -1
+// CHECK: [0xc1,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x13,0x85,0xbe]
+
+s_ff1_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x13,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff1_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x13,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff1_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s103, s[2:3]
+// CHECK: [0x02,0x14,0xe7,0xbe]
+
+s_ff1_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x14,0xe8,0xbe]
+
+s_ff1_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x14,0xe9,0xbe]
+
+s_ff1_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x14,0xea,0xbe]
+
+s_ff1_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x14,0xeb,0xbe]
+
+s_ff1_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x14,0xec,0xbe]
+
+s_ff1_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x14,0xed,0xbe]
+
+s_ff1_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x14,0xee,0xbe]
+
+s_ff1_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x14,0xef,0xbe]
+
+s_ff1_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x14,0xfb,0xbe]
+
+s_ff1_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x14,0xfc,0xbe]
+
+s_ff1_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x14,0xfe,0xbe]
+
+s_ff1_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x14,0xff,0xbe]
+
+s_ff1_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, s[102:103]
+// CHECK: [0x66,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, flat_scratch
+// CHECK: [0x68,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, vcc
+// CHECK: [0x6a,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, tba
+// CHECK: [0x6c,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, tma
+// CHECK: [0x6e,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, exec
+// CHECK: [0x7e,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, 0
+// CHECK: [0x80,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, -1
+// CHECK: [0xc1,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x14,0x85,0xbe]
+
+s_ff1_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x14,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff1_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x14,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_b32 s5, s1
+// CHECK: [0x01,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s103, s1
+// CHECK: [0x01,0x15,0xe7,0xbe]
+
+s_flbit_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x15,0xe8,0xbe]
+
+s_flbit_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x15,0xe9,0xbe]
+
+s_flbit_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x15,0xea,0xbe]
+
+s_flbit_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x15,0xeb,0xbe]
+
+s_flbit_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x15,0xec,0xbe]
+
+s_flbit_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x15,0xed,0xbe]
+
+s_flbit_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x15,0xee,0xbe]
+
+s_flbit_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x15,0xef,0xbe]
+
+s_flbit_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x15,0xfb,0xbe]
+
+s_flbit_i32_b32 m0, s1
+// CHECK: [0x01,0x15,0xfc,0xbe]
+
+s_flbit_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x15,0xfe,0xbe]
+
+s_flbit_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x15,0xff,0xbe]
+
+s_flbit_i32_b32 s5, s103
+// CHECK: [0x67,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, m0
+// CHECK: [0x7c,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, 0
+// CHECK: [0x80,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, -1
+// CHECK: [0xc1,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x15,0x85,0xbe]
+
+s_flbit_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x15,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x15,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s103, s[2:3]
+// CHECK: [0x02,0x16,0xe7,0xbe]
+
+s_flbit_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x16,0xe8,0xbe]
+
+s_flbit_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x16,0xe9,0xbe]
+
+s_flbit_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x16,0xea,0xbe]
+
+s_flbit_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x16,0xeb,0xbe]
+
+s_flbit_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x16,0xec,0xbe]
+
+s_flbit_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x16,0xed,0xbe]
+
+s_flbit_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x16,0xee,0xbe]
+
+s_flbit_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x16,0xef,0xbe]
+
+s_flbit_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x16,0xfb,0xbe]
+
+s_flbit_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x16,0xfc,0xbe]
+
+s_flbit_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x16,0xfe,0xbe]
+
+s_flbit_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x16,0xff,0xbe]
+
+s_flbit_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, s[102:103]
+// CHECK: [0x66,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, flat_scratch
+// CHECK: [0x68,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, vcc
+// CHECK: [0x6a,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, tba
+// CHECK: [0x6c,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, tma
+// CHECK: [0x6e,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, exec
+// CHECK: [0x7e,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, 0
+// CHECK: [0x80,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, -1
+// CHECK: [0xc1,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x16,0x85,0xbe]
+
+s_flbit_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x16,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x16,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32 s5, s1
+// CHECK: [0x01,0x17,0x85,0xbe]
+
+s_flbit_i32 s103, s1
+// CHECK: [0x01,0x17,0xe7,0xbe]
+
+s_flbit_i32 flat_scratch_lo, s1
+// CHECK: [0x01,0x17,0xe8,0xbe]
+
+s_flbit_i32 flat_scratch_hi, s1
+// CHECK: [0x01,0x17,0xe9,0xbe]
+
+s_flbit_i32 vcc_lo, s1
+// CHECK: [0x01,0x17,0xea,0xbe]
+
+s_flbit_i32 vcc_hi, s1
+// CHECK: [0x01,0x17,0xeb,0xbe]
+
+s_flbit_i32 tba_lo, s1
+// CHECK: [0x01,0x17,0xec,0xbe]
+
+s_flbit_i32 tba_hi, s1
+// CHECK: [0x01,0x17,0xed,0xbe]
+
+s_flbit_i32 tma_lo, s1
+// CHECK: [0x01,0x17,0xee,0xbe]
+
+s_flbit_i32 tma_hi, s1
+// CHECK: [0x01,0x17,0xef,0xbe]
+
+s_flbit_i32 ttmp11, s1
+// CHECK: [0x01,0x17,0xfb,0xbe]
+
+s_flbit_i32 m0, s1
+// CHECK: [0x01,0x17,0xfc,0xbe]
+
+s_flbit_i32 exec_lo, s1
+// CHECK: [0x01,0x17,0xfe,0xbe]
+
+s_flbit_i32 exec_hi, s1
+// CHECK: [0x01,0x17,0xff,0xbe]
+
+s_flbit_i32 s5, s103
+// CHECK: [0x67,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, flat_scratch_lo
+// CHECK: [0x68,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, flat_scratch_hi
+// CHECK: [0x69,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, vcc_lo
+// CHECK: [0x6a,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, vcc_hi
+// CHECK: [0x6b,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, tba_lo
+// CHECK: [0x6c,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, tba_hi
+// CHECK: [0x6d,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, tma_lo
+// CHECK: [0x6e,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, tma_hi
+// CHECK: [0x6f,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, ttmp11
+// CHECK: [0x7b,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, m0
+// CHECK: [0x7c,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, exec_lo
+// CHECK: [0x7e,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, exec_hi
+// CHECK: [0x7f,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, 0
+// CHECK: [0x80,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, -1
+// CHECK: [0xc1,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, 0.5
+// CHECK: [0xf0,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, -4.0
+// CHECK: [0xf7,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, src_vccz
+// CHECK: [0xfb,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, src_execz
+// CHECK: [0xfc,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, src_scc
+// CHECK: [0xfd,0x17,0x85,0xbe]
+
+s_flbit_i32 s5, 0xaf123456
+// CHECK: [0xff,0x17,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32 s5, 0x3f717273
+// CHECK: [0xff,0x17,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_i64 s5, s[2:3]
+// CHECK: [0x02,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s103, s[2:3]
+// CHECK: [0x02,0x18,0xe7,0xbe]
+
+s_flbit_i32_i64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x18,0xe8,0xbe]
+
+s_flbit_i32_i64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x18,0xe9,0xbe]
+
+s_flbit_i32_i64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x18,0xea,0xbe]
+
+s_flbit_i32_i64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x18,0xeb,0xbe]
+
+s_flbit_i32_i64 tba_lo, s[2:3]
+// CHECK: [0x02,0x18,0xec,0xbe]
+
+s_flbit_i32_i64 tba_hi, s[2:3]
+// CHECK: [0x02,0x18,0xed,0xbe]
+
+s_flbit_i32_i64 tma_lo, s[2:3]
+// CHECK: [0x02,0x18,0xee,0xbe]
+
+s_flbit_i32_i64 tma_hi, s[2:3]
+// CHECK: [0x02,0x18,0xef,0xbe]
+
+s_flbit_i32_i64 ttmp11, s[2:3]
+// CHECK: [0x02,0x18,0xfb,0xbe]
+
+s_flbit_i32_i64 m0, s[2:3]
+// CHECK: [0x02,0x18,0xfc,0xbe]
+
+s_flbit_i32_i64 exec_lo, s[2:3]
+// CHECK: [0x02,0x18,0xfe,0xbe]
+
+s_flbit_i32_i64 exec_hi, s[2:3]
+// CHECK: [0x02,0x18,0xff,0xbe]
+
+s_flbit_i32_i64 s5, s[4:5]
+// CHECK: [0x04,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, s[102:103]
+// CHECK: [0x66,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, flat_scratch
+// CHECK: [0x68,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, vcc
+// CHECK: [0x6a,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, tba
+// CHECK: [0x6c,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, tma
+// CHECK: [0x6e,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, exec
+// CHECK: [0x7e,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, 0
+// CHECK: [0x80,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, -1
+// CHECK: [0xc1,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, 0.5
+// CHECK: [0xf0,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, -4.0
+// CHECK: [0xf7,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, src_vccz
+// CHECK: [0xfb,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, src_execz
+// CHECK: [0xfc,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, src_scc
+// CHECK: [0xfd,0x18,0x85,0xbe]
+
+s_flbit_i32_i64 s5, 0xaf123456
+// CHECK: [0xff,0x18,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_i64 s5, 0x3f717273
+// CHECK: [0xff,0x18,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_sext_i32_i8 s5, s1
+// CHECK: [0x01,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s103, s1
+// CHECK: [0x01,0x19,0xe7,0xbe]
+
+s_sext_i32_i8 flat_scratch_lo, s1
+// CHECK: [0x01,0x19,0xe8,0xbe]
+
+s_sext_i32_i8 flat_scratch_hi, s1
+// CHECK: [0x01,0x19,0xe9,0xbe]
+
+s_sext_i32_i8 vcc_lo, s1
+// CHECK: [0x01,0x19,0xea,0xbe]
+
+s_sext_i32_i8 vcc_hi, s1
+// CHECK: [0x01,0x19,0xeb,0xbe]
+
+s_sext_i32_i8 tba_lo, s1
+// CHECK: [0x01,0x19,0xec,0xbe]
+
+s_sext_i32_i8 tba_hi, s1
+// CHECK: [0x01,0x19,0xed,0xbe]
+
+s_sext_i32_i8 tma_lo, s1
+// CHECK: [0x01,0x19,0xee,0xbe]
+
+s_sext_i32_i8 tma_hi, s1
+// CHECK: [0x01,0x19,0xef,0xbe]
+
+s_sext_i32_i8 ttmp11, s1
+// CHECK: [0x01,0x19,0xfb,0xbe]
+
+s_sext_i32_i8 m0, s1
+// CHECK: [0x01,0x19,0xfc,0xbe]
+
+s_sext_i32_i8 exec_lo, s1
+// CHECK: [0x01,0x19,0xfe,0xbe]
+
+s_sext_i32_i8 exec_hi, s1
+// CHECK: [0x01,0x19,0xff,0xbe]
+
+s_sext_i32_i8 s5, s103
+// CHECK: [0x67,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, flat_scratch_lo
+// CHECK: [0x68,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, flat_scratch_hi
+// CHECK: [0x69,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, vcc_lo
+// CHECK: [0x6a,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, vcc_hi
+// CHECK: [0x6b,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, tba_lo
+// CHECK: [0x6c,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, tba_hi
+// CHECK: [0x6d,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, tma_lo
+// CHECK: [0x6e,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, tma_hi
+// CHECK: [0x6f,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, ttmp11
+// CHECK: [0x7b,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, m0
+// CHECK: [0x7c,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, exec_lo
+// CHECK: [0x7e,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, exec_hi
+// CHECK: [0x7f,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, 0
+// CHECK: [0x80,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, -1
+// CHECK: [0xc1,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, src_vccz
+// CHECK: [0xfb,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, src_execz
+// CHECK: [0xfc,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, src_scc
+// CHECK: [0xfd,0x19,0x85,0xbe]
+
+s_sext_i32_i8 s5, 0x71
+// CHECK: [0xff,0x19,0x85,0xbe,0x71,0x00,0x00,0x00]
+
+s_sext_i32_i8 s5, 0xf0
+// CHECK: [0xff,0x19,0x85,0xbe,0xf0,0x00,0x00,0x00]
+
+s_sext_i32_i16 s5, s1
+// CHECK: [0x01,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s103, s1
+// CHECK: [0x01,0x1a,0xe7,0xbe]
+
+s_sext_i32_i16 flat_scratch_lo, s1
+// CHECK: [0x01,0x1a,0xe8,0xbe]
+
+s_sext_i32_i16 flat_scratch_hi, s1
+// CHECK: [0x01,0x1a,0xe9,0xbe]
+
+s_sext_i32_i16 vcc_lo, s1
+// CHECK: [0x01,0x1a,0xea,0xbe]
+
+s_sext_i32_i16 vcc_hi, s1
+// CHECK: [0x01,0x1a,0xeb,0xbe]
+
+s_sext_i32_i16 tba_lo, s1
+// CHECK: [0x01,0x1a,0xec,0xbe]
+
+s_sext_i32_i16 tba_hi, s1
+// CHECK: [0x01,0x1a,0xed,0xbe]
+
+s_sext_i32_i16 tma_lo, s1
+// CHECK: [0x01,0x1a,0xee,0xbe]
+
+s_sext_i32_i16 tma_hi, s1
+// CHECK: [0x01,0x1a,0xef,0xbe]
+
+s_sext_i32_i16 ttmp11, s1
+// CHECK: [0x01,0x1a,0xfb,0xbe]
+
+s_sext_i32_i16 m0, s1
+// CHECK: [0x01,0x1a,0xfc,0xbe]
+
+s_sext_i32_i16 exec_lo, s1
+// CHECK: [0x01,0x1a,0xfe,0xbe]
+
+s_sext_i32_i16 exec_hi, s1
+// CHECK: [0x01,0x1a,0xff,0xbe]
+
+s_sext_i32_i16 s5, s103
+// CHECK: [0x67,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, flat_scratch_lo
+// CHECK: [0x68,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, flat_scratch_hi
+// CHECK: [0x69,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, vcc_lo
+// CHECK: [0x6a,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, vcc_hi
+// CHECK: [0x6b,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, tba_lo
+// CHECK: [0x6c,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, tba_hi
+// CHECK: [0x6d,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, tma_lo
+// CHECK: [0x6e,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, tma_hi
+// CHECK: [0x6f,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, ttmp11
+// CHECK: [0x7b,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, m0
+// CHECK: [0x7c,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, exec_lo
+// CHECK: [0x7e,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, exec_hi
+// CHECK: [0x7f,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, 0
+// CHECK: [0x80,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, -1
+// CHECK: [0xc1,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, src_vccz
+// CHECK: [0xfb,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, src_execz
+// CHECK: [0xfc,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, src_scc
+// CHECK: [0xfd,0x1a,0x85,0xbe]
+
+s_sext_i32_i16 s5, 0xfe0b
+// CHECK: [0xff,0x1a,0x85,0xbe,0x0b,0xfe,0x00,0x00]
+
+s_sext_i32_i16 s5, 0x3456
+// CHECK: [0xff,0x1a,0x85,0xbe,0x56,0x34,0x00,0x00]
+
+s_bitset0_b32 s5, s1
+// CHECK: [0x01,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s103, s1
+// CHECK: [0x01,0x1b,0xe7,0xbe]
+
+s_bitset0_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x1b,0xe8,0xbe]
+
+s_bitset0_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x1b,0xe9,0xbe]
+
+s_bitset0_b32 vcc_lo, s1
+// CHECK: [0x01,0x1b,0xea,0xbe]
+
+s_bitset0_b32 vcc_hi, s1
+// CHECK: [0x01,0x1b,0xeb,0xbe]
+
+s_bitset0_b32 tba_lo, s1
+// CHECK: [0x01,0x1b,0xec,0xbe]
+
+s_bitset0_b32 tba_hi, s1
+// CHECK: [0x01,0x1b,0xed,0xbe]
+
+s_bitset0_b32 tma_lo, s1
+// CHECK: [0x01,0x1b,0xee,0xbe]
+
+s_bitset0_b32 tma_hi, s1
+// CHECK: [0x01,0x1b,0xef,0xbe]
+
+s_bitset0_b32 ttmp11, s1
+// CHECK: [0x01,0x1b,0xfb,0xbe]
+
+s_bitset0_b32 m0, s1
+// CHECK: [0x01,0x1b,0xfc,0xbe]
+
+s_bitset0_b32 exec_lo, s1
+// CHECK: [0x01,0x1b,0xfe,0xbe]
+
+s_bitset0_b32 exec_hi, s1
+// CHECK: [0x01,0x1b,0xff,0xbe]
+
+s_bitset0_b32 s5, s103
+// CHECK: [0x67,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, vcc_lo
+// CHECK: [0x6a,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, vcc_hi
+// CHECK: [0x6b,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, tba_lo
+// CHECK: [0x6c,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, tba_hi
+// CHECK: [0x6d,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, tma_lo
+// CHECK: [0x6e,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, tma_hi
+// CHECK: [0x6f,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, ttmp11
+// CHECK: [0x7b,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, m0
+// CHECK: [0x7c,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, exec_lo
+// CHECK: [0x7e,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, exec_hi
+// CHECK: [0x7f,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, 0
+// CHECK: [0x80,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, -1
+// CHECK: [0xc1,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, 0.5
+// CHECK: [0xf0,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, -4.0
+// CHECK: [0xf7,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, src_vccz
+// CHECK: [0xfb,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, src_execz
+// CHECK: [0xfc,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, src_scc
+// CHECK: [0xfd,0x1b,0x85,0xbe]
+
+s_bitset0_b32 s5, 0xaf123456
+// CHECK: [0xff,0x1b,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset0_b32 s5, 0x3f717273
+// CHECK: [0xff,0x1b,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset0_b64 s[10:11], s1
+// CHECK: [0x01,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[12:13], s1
+// CHECK: [0x01,0x1c,0x8c,0xbe]
+
+s_bitset0_b64 s[102:103], s1
+// CHECK: [0x01,0x1c,0xe6,0xbe]
+
+s_bitset0_b64 flat_scratch, s1
+// CHECK: [0x01,0x1c,0xe8,0xbe]
+
+s_bitset0_b64 vcc, s1
+// CHECK: [0x01,0x1c,0xea,0xbe]
+
+s_bitset0_b64 tba, s1
+// CHECK: [0x01,0x1c,0xec,0xbe]
+
+s_bitset0_b64 tma, s1
+// CHECK: [0x01,0x1c,0xee,0xbe]
+
+s_bitset0_b64 ttmp[10:11], s1
+// CHECK: [0x01,0x1c,0xfa,0xbe]
+
+s_bitset0_b64 exec, s1
+// CHECK: [0x01,0x1c,0xfe,0xbe]
+
+s_bitset0_b64 s[10:11], s103
+// CHECK: [0x67,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], flat_scratch_lo
+// CHECK: [0x68,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], flat_scratch_hi
+// CHECK: [0x69,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], vcc_lo
+// CHECK: [0x6a,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], vcc_hi
+// CHECK: [0x6b,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], tba_lo
+// CHECK: [0x6c,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], tba_hi
+// CHECK: [0x6d,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], tma_lo
+// CHECK: [0x6e,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], tma_hi
+// CHECK: [0x6f,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], ttmp11
+// CHECK: [0x7b,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], m0
+// CHECK: [0x7c,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], exec_lo
+// CHECK: [0x7e,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], exec_hi
+// CHECK: [0x7f,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], 0
+// CHECK: [0x80,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], -1
+// CHECK: [0xc1,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x1c,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x1c,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset0_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x1c,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset1_b32 s5, s1
+// CHECK: [0x01,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s103, s1
+// CHECK: [0x01,0x1d,0xe7,0xbe]
+
+s_bitset1_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x1d,0xe8,0xbe]
+
+s_bitset1_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x1d,0xe9,0xbe]
+
+s_bitset1_b32 vcc_lo, s1
+// CHECK: [0x01,0x1d,0xea,0xbe]
+
+s_bitset1_b32 vcc_hi, s1
+// CHECK: [0x01,0x1d,0xeb,0xbe]
+
+s_bitset1_b32 tba_lo, s1
+// CHECK: [0x01,0x1d,0xec,0xbe]
+
+s_bitset1_b32 tba_hi, s1
+// CHECK: [0x01,0x1d,0xed,0xbe]
+
+s_bitset1_b32 tma_lo, s1
+// CHECK: [0x01,0x1d,0xee,0xbe]
+
+s_bitset1_b32 tma_hi, s1
+// CHECK: [0x01,0x1d,0xef,0xbe]
+
+s_bitset1_b32 ttmp11, s1
+// CHECK: [0x01,0x1d,0xfb,0xbe]
+
+s_bitset1_b32 m0, s1
+// CHECK: [0x01,0x1d,0xfc,0xbe]
+
+s_bitset1_b32 exec_lo, s1
+// CHECK: [0x01,0x1d,0xfe,0xbe]
+
+s_bitset1_b32 exec_hi, s1
+// CHECK: [0x01,0x1d,0xff,0xbe]
+
+s_bitset1_b32 s5, s103
+// CHECK: [0x67,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, vcc_lo
+// CHECK: [0x6a,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, vcc_hi
+// CHECK: [0x6b,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, tba_lo
+// CHECK: [0x6c,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, tba_hi
+// CHECK: [0x6d,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, tma_lo
+// CHECK: [0x6e,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, tma_hi
+// CHECK: [0x6f,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, ttmp11
+// CHECK: [0x7b,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, m0
+// CHECK: [0x7c,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, exec_lo
+// CHECK: [0x7e,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, exec_hi
+// CHECK: [0x7f,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, 0
+// CHECK: [0x80,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, -1
+// CHECK: [0xc1,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, 0.5
+// CHECK: [0xf0,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, -4.0
+// CHECK: [0xf7,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, src_vccz
+// CHECK: [0xfb,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, src_execz
+// CHECK: [0xfc,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, src_scc
+// CHECK: [0xfd,0x1d,0x85,0xbe]
+
+s_bitset1_b32 s5, 0xaf123456
+// CHECK: [0xff,0x1d,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset1_b32 s5, 0x3f717273
+// CHECK: [0xff,0x1d,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset1_b64 s[10:11], s1
+// CHECK: [0x01,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[12:13], s1
+// CHECK: [0x01,0x1e,0x8c,0xbe]
+
+s_bitset1_b64 s[102:103], s1
+// CHECK: [0x01,0x1e,0xe6,0xbe]
+
+s_bitset1_b64 flat_scratch, s1
+// CHECK: [0x01,0x1e,0xe8,0xbe]
+
+s_bitset1_b64 vcc, s1
+// CHECK: [0x01,0x1e,0xea,0xbe]
+
+s_bitset1_b64 tba, s1
+// CHECK: [0x01,0x1e,0xec,0xbe]
+
+s_bitset1_b64 tma, s1
+// CHECK: [0x01,0x1e,0xee,0xbe]
+
+s_bitset1_b64 ttmp[10:11], s1
+// CHECK: [0x01,0x1e,0xfa,0xbe]
+
+s_bitset1_b64 exec, s1
+// CHECK: [0x01,0x1e,0xfe,0xbe]
+
+s_bitset1_b64 s[10:11], s103
+// CHECK: [0x67,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], flat_scratch_lo
+// CHECK: [0x68,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], flat_scratch_hi
+// CHECK: [0x69,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], vcc_lo
+// CHECK: [0x6a,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], vcc_hi
+// CHECK: [0x6b,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], tba_lo
+// CHECK: [0x6c,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], tba_hi
+// CHECK: [0x6d,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], tma_lo
+// CHECK: [0x6e,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], tma_hi
+// CHECK: [0x6f,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], ttmp11
+// CHECK: [0x7b,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], m0
+// CHECK: [0x7c,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], exec_lo
+// CHECK: [0x7e,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], exec_hi
+// CHECK: [0x7f,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], 0
+// CHECK: [0x80,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], -1
+// CHECK: [0xc1,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x1e,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x1e,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset1_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x1e,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_getpc_b64 s[10:11]
+// CHECK: [0x00,0x1f,0x8a,0xbe]
+
+s_getpc_b64 s[12:13]
+// CHECK: [0x00,0x1f,0x8c,0xbe]
+
+s_getpc_b64 s[102:103]
+// CHECK: [0x00,0x1f,0xe6,0xbe]
+
+s_getpc_b64 flat_scratch
+// CHECK: [0x00,0x1f,0xe8,0xbe]
+
+s_getpc_b64 vcc
+// CHECK: [0x00,0x1f,0xea,0xbe]
+
+s_getpc_b64 tba
+// CHECK: [0x00,0x1f,0xec,0xbe]
+
+s_getpc_b64 tma
+// CHECK: [0x00,0x1f,0xee,0xbe]
+
+s_getpc_b64 ttmp[10:11]
+// CHECK: [0x00,0x1f,0xfa,0xbe]
+
+s_getpc_b64 exec
+// CHECK: [0x00,0x1f,0xfe,0xbe]
+
+s_setpc_b64 s[2:3]
+// CHECK: [0x02,0x20,0x80,0xbe]
+
+s_setpc_b64 s[4:5]
+// CHECK: [0x04,0x20,0x80,0xbe]
+
+s_setpc_b64 s[102:103]
+// CHECK: [0x66,0x20,0x80,0xbe]
+
+s_setpc_b64 flat_scratch
+// CHECK: [0x68,0x20,0x80,0xbe]
+
+s_setpc_b64 vcc
+// CHECK: [0x6a,0x20,0x80,0xbe]
+
+s_setpc_b64 tba
+// CHECK: [0x6c,0x20,0x80,0xbe]
+
+s_setpc_b64 tma
+// CHECK: [0x6e,0x20,0x80,0xbe]
+
+s_setpc_b64 ttmp[10:11]
+// CHECK: [0x7a,0x20,0x80,0xbe]
+
+s_swappc_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x21,0x8a,0xbe]
+
+s_swappc_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x21,0x8c,0xbe]
+
+s_swappc_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x21,0xe6,0xbe]
+
+s_swappc_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x21,0xe8,0xbe]
+
+s_swappc_b64 vcc, s[2:3]
+// CHECK: [0x02,0x21,0xea,0xbe]
+
+s_swappc_b64 tba, s[2:3]
+// CHECK: [0x02,0x21,0xec,0xbe]
+
+s_swappc_b64 tma, s[2:3]
+// CHECK: [0x02,0x21,0xee,0xbe]
+
+s_swappc_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x21,0xfa,0xbe]
+
+s_swappc_b64 exec, s[2:3]
+// CHECK: [0x02,0x21,0xfe,0xbe]
+
+s_swappc_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x21,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x21,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x21,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], vcc
+// CHECK: [0x6a,0x21,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], tba
+// CHECK: [0x6c,0x21,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], tma
+// CHECK: [0x6e,0x21,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x21,0x8a,0xbe]
+
+s_rfe_b64 s[2:3]
+// CHECK: [0x02,0x22,0x80,0xbe]
+
+s_rfe_b64 s[4:5]
+// CHECK: [0x04,0x22,0x80,0xbe]
+
+s_rfe_b64 s[102:103]
+// CHECK: [0x66,0x22,0x80,0xbe]
+
+s_rfe_b64 flat_scratch
+// CHECK: [0x68,0x22,0x80,0xbe]
+
+s_rfe_b64 vcc
+// CHECK: [0x6a,0x22,0x80,0xbe]
+
+s_rfe_b64 tba
+// CHECK: [0x6c,0x22,0x80,0xbe]
+
+s_rfe_b64 tma
+// CHECK: [0x6e,0x22,0x80,0xbe]
+
+s_rfe_b64 ttmp[10:11]
+// CHECK: [0x7a,0x22,0x80,0xbe]
+
+s_and_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x24,0x8c,0xbe]
+
+s_and_saveexec_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x24,0xe6,0xbe]
+
+s_and_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x24,0xe8,0xbe]
+
+s_and_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x24,0xea,0xbe]
+
+s_and_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x24,0xec,0xbe]
+
+s_and_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x24,0xee,0xbe]
+
+s_and_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x24,0xfa,0xbe]
+
+s_and_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x24,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x24,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_and_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x24,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_or_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x25,0x8c,0xbe]
+
+s_or_saveexec_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x25,0xe6,0xbe]
+
+s_or_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x25,0xe8,0xbe]
+
+s_or_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x25,0xea,0xbe]
+
+s_or_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x25,0xec,0xbe]
+
+s_or_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x25,0xee,0xbe]
+
+s_or_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x25,0xfa,0xbe]
+
+s_or_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x25,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x25,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_or_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x25,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xor_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x26,0x8c,0xbe]
+
+s_xor_saveexec_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x26,0xe6,0xbe]
+
+s_xor_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x26,0xe8,0xbe]
+
+s_xor_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x26,0xea,0xbe]
+
+s_xor_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x26,0xec,0xbe]
+
+s_xor_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x26,0xee,0xbe]
+
+s_xor_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x26,0xfa,0xbe]
+
+s_xor_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x26,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x26,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xor_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x26,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn2_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x27,0x8c,0xbe]
+
+s_andn2_saveexec_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x27,0xe6,0xbe]
+
+s_andn2_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x27,0xe8,0xbe]
+
+s_andn2_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x27,0xea,0xbe]
+
+s_andn2_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x27,0xec,0xbe]
+
+s_andn2_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x27,0xee,0xbe]
+
+s_andn2_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x27,0xfa,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x27,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x27,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn2_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x27,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_orn2_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x28,0x8c,0xbe]
+
+s_orn2_saveexec_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x28,0xe6,0xbe]
+
+s_orn2_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x28,0xe8,0xbe]
+
+s_orn2_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x28,0xea,0xbe]
+
+s_orn2_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x28,0xec,0xbe]
+
+s_orn2_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x28,0xee,0xbe]
+
+s_orn2_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x28,0xfa,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x28,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x28,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_orn2_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x28,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nand_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x29,0x8c,0xbe]
+
+s_nand_saveexec_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x29,0xe6,0xbe]
+
+s_nand_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x29,0xe8,0xbe]
+
+s_nand_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x29,0xea,0xbe]
+
+s_nand_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x29,0xec,0xbe]
+
+s_nand_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x29,0xee,0xbe]
+
+s_nand_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x29,0xfa,0xbe]
+
+s_nand_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x29,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x29,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nand_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x29,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nor_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x2a,0x8c,0xbe]
+
+s_nor_saveexec_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x2a,0xe6,0xbe]
+
+s_nor_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x2a,0xe8,0xbe]
+
+s_nor_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x2a,0xea,0xbe]
+
+s_nor_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x2a,0xec,0xbe]
+
+s_nor_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x2a,0xee,0xbe]
+
+s_nor_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x2a,0xfa,0xbe]
+
+s_nor_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x2a,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x2a,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nor_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x2a,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xnor_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x2b,0x8c,0xbe]
+
+s_xnor_saveexec_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x2b,0xe6,0xbe]
+
+s_xnor_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x2b,0xe8,0xbe]
+
+s_xnor_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x2b,0xea,0xbe]
+
+s_xnor_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x2b,0xec,0xbe]
+
+s_xnor_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x2b,0xee,0xbe]
+
+s_xnor_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x2b,0xfa,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x2b,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x2b,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xnor_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x2b,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_quadmask_b32 s5, s1
+// CHECK: [0x01,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s103, s1
+// CHECK: [0x01,0x2c,0xe7,0xbe]
+
+s_quadmask_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x2c,0xe8,0xbe]
+
+s_quadmask_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x2c,0xe9,0xbe]
+
+s_quadmask_b32 vcc_lo, s1
+// CHECK: [0x01,0x2c,0xea,0xbe]
+
+s_quadmask_b32 vcc_hi, s1
+// CHECK: [0x01,0x2c,0xeb,0xbe]
+
+s_quadmask_b32 tba_lo, s1
+// CHECK: [0x01,0x2c,0xec,0xbe]
+
+s_quadmask_b32 tba_hi, s1
+// CHECK: [0x01,0x2c,0xed,0xbe]
+
+s_quadmask_b32 tma_lo, s1
+// CHECK: [0x01,0x2c,0xee,0xbe]
+
+s_quadmask_b32 tma_hi, s1
+// CHECK: [0x01,0x2c,0xef,0xbe]
+
+s_quadmask_b32 ttmp11, s1
+// CHECK: [0x01,0x2c,0xfb,0xbe]
+
+s_quadmask_b32 m0, s1
+// CHECK: [0x01,0x2c,0xfc,0xbe]
+
+s_quadmask_b32 exec_lo, s1
+// CHECK: [0x01,0x2c,0xfe,0xbe]
+
+s_quadmask_b32 exec_hi, s1
+// CHECK: [0x01,0x2c,0xff,0xbe]
+
+s_quadmask_b32 s5, s103
+// CHECK: [0x67,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, vcc_lo
+// CHECK: [0x6a,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, vcc_hi
+// CHECK: [0x6b,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, tba_lo
+// CHECK: [0x6c,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, tba_hi
+// CHECK: [0x6d,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, tma_lo
+// CHECK: [0x6e,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, tma_hi
+// CHECK: [0x6f,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, ttmp11
+// CHECK: [0x7b,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, m0
+// CHECK: [0x7c,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, exec_lo
+// CHECK: [0x7e,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, exec_hi
+// CHECK: [0x7f,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, 0
+// CHECK: [0x80,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, -1
+// CHECK: [0xc1,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, 0.5
+// CHECK: [0xf0,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, -4.0
+// CHECK: [0xf7,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, src_vccz
+// CHECK: [0xfb,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, src_execz
+// CHECK: [0xfc,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, src_scc
+// CHECK: [0xfd,0x2c,0x85,0xbe]
+
+s_quadmask_b32 s5, 0xaf123456
+// CHECK: [0xff,0x2c,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_quadmask_b32 s5, 0x3f717273
+// CHECK: [0xff,0x2c,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_quadmask_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x2d,0x8c,0xbe]
+
+s_quadmask_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x2d,0xe6,0xbe]
+
+s_quadmask_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x2d,0xe8,0xbe]
+
+s_quadmask_b64 vcc, s[2:3]
+// CHECK: [0x02,0x2d,0xea,0xbe]
+
+s_quadmask_b64 tba, s[2:3]
+// CHECK: [0x02,0x2d,0xec,0xbe]
+
+s_quadmask_b64 tma, s[2:3]
+// CHECK: [0x02,0x2d,0xee,0xbe]
+
+s_quadmask_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x2d,0xfa,0xbe]
+
+s_quadmask_b64 exec, s[2:3]
+// CHECK: [0x02,0x2d,0xfe,0xbe]
+
+s_quadmask_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], vcc
+// CHECK: [0x6a,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], tba
+// CHECK: [0x6c,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], tma
+// CHECK: [0x6e,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], exec
+// CHECK: [0x7e,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], 0
+// CHECK: [0x80,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], -1
+// CHECK: [0xc1,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x2d,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x2d,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_quadmask_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x2d,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_movrels_b32 s5, s1
+// CHECK: [0x01,0x2e,0x85,0xbe]
+
+s_movrels_b32 s103, s1
+// CHECK: [0x01,0x2e,0xe7,0xbe]
+
+s_movrels_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x2e,0xe8,0xbe]
+
+s_movrels_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x2e,0xe9,0xbe]
+
+s_movrels_b32 vcc_lo, s1
+// CHECK: [0x01,0x2e,0xea,0xbe]
+
+s_movrels_b32 vcc_hi, s1
+// CHECK: [0x01,0x2e,0xeb,0xbe]
+
+s_movrels_b32 tba_lo, s1
+// CHECK: [0x01,0x2e,0xec,0xbe]
+
+s_movrels_b32 tba_hi, s1
+// CHECK: [0x01,0x2e,0xed,0xbe]
+
+s_movrels_b32 tma_lo, s1
+// CHECK: [0x01,0x2e,0xee,0xbe]
+
+s_movrels_b32 tma_hi, s1
+// CHECK: [0x01,0x2e,0xef,0xbe]
+
+s_movrels_b32 ttmp11, s1
+// CHECK: [0x01,0x2e,0xfb,0xbe]
+
+s_movrels_b32 m0, s1
+// CHECK: [0x01,0x2e,0xfc,0xbe]
+
+s_movrels_b32 exec_lo, s1
+// CHECK: [0x01,0x2e,0xfe,0xbe]
+
+s_movrels_b32 exec_hi, s1
+// CHECK: [0x01,0x2e,0xff,0xbe]
+
+s_movrels_b32 s5, s103
+// CHECK: [0x67,0x2e,0x85,0xbe]
+
+s_movrels_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x2e,0x85,0xbe]
+
+s_movrels_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x2e,0x85,0xbe]
+
+s_movrels_b32 s5, vcc_lo
+// CHECK: [0x6a,0x2e,0x85,0xbe]
+
+s_movrels_b32 s5, vcc_hi
+// CHECK: [0x6b,0x2e,0x85,0xbe]
+
+s_movrels_b32 s5, tba_lo
+// CHECK: [0x6c,0x2e,0x85,0xbe]
+
+s_movrels_b32 s5, tba_hi
+// CHECK: [0x6d,0x2e,0x85,0xbe]
+
+s_movrels_b32 s5, tma_lo
+// CHECK: [0x6e,0x2e,0x85,0xbe]
+
+s_movrels_b32 s5, tma_hi
+// CHECK: [0x6f,0x2e,0x85,0xbe]
+
+s_movrels_b32 s5, ttmp11
+// CHECK: [0x7b,0x2e,0x85,0xbe]
+
+s_movrels_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x2f,0x8a,0xbe]
+
+s_movrels_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x2f,0x8c,0xbe]
+
+s_movrels_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x2f,0xe6,0xbe]
+
+s_movrels_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x2f,0xe8,0xbe]
+
+s_movrels_b64 vcc, s[2:3]
+// CHECK: [0x02,0x2f,0xea,0xbe]
+
+s_movrels_b64 tba, s[2:3]
+// CHECK: [0x02,0x2f,0xec,0xbe]
+
+s_movrels_b64 tma, s[2:3]
+// CHECK: [0x02,0x2f,0xee,0xbe]
+
+s_movrels_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x2f,0xfa,0xbe]
+
+s_movrels_b64 exec, s[2:3]
+// CHECK: [0x02,0x2f,0xfe,0xbe]
+
+s_movrels_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x2f,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x2f,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x2f,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], vcc
+// CHECK: [0x6a,0x2f,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], tba
+// CHECK: [0x6c,0x2f,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], tma
+// CHECK: [0x6e,0x2f,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x2f,0x8a,0xbe]
+
+s_movreld_b32 s5, s1
+// CHECK: [0x01,0x30,0x85,0xbe]
+
+s_movreld_b32 s103, s1
+// CHECK: [0x01,0x30,0xe7,0xbe]
+
+s_movreld_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x30,0xe8,0xbe]
+
+s_movreld_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x30,0xe9,0xbe]
+
+s_movreld_b32 vcc_lo, s1
+// CHECK: [0x01,0x30,0xea,0xbe]
+
+s_movreld_b32 vcc_hi, s1
+// CHECK: [0x01,0x30,0xeb,0xbe]
+
+s_movreld_b32 tba_lo, s1
+// CHECK: [0x01,0x30,0xec,0xbe]
+
+s_movreld_b32 tba_hi, s1
+// CHECK: [0x01,0x30,0xed,0xbe]
+
+s_movreld_b32 tma_lo, s1
+// CHECK: [0x01,0x30,0xee,0xbe]
+
+s_movreld_b32 tma_hi, s1
+// CHECK: [0x01,0x30,0xef,0xbe]
+
+s_movreld_b32 ttmp11, s1
+// CHECK: [0x01,0x30,0xfb,0xbe]
+
+s_movreld_b32 s5, s103
+// CHECK: [0x67,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, flat_scratch_lo
+// CHECK: [0x68,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, flat_scratch_hi
+// CHECK: [0x69,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, vcc_lo
+// CHECK: [0x6a,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, vcc_hi
+// CHECK: [0x6b,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, tba_lo
+// CHECK: [0x6c,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, tba_hi
+// CHECK: [0x6d,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, tma_lo
+// CHECK: [0x6e,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, tma_hi
+// CHECK: [0x6f,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, ttmp11
+// CHECK: [0x7b,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, m0
+// CHECK: [0x7c,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, 0
+// CHECK: [0x80,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, -1
+// CHECK: [0xc1,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, 0.5
+// CHECK: [0xf0,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, -4.0
+// CHECK: [0xf7,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, src_vccz
+// CHECK: [0xfb,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, src_execz
+// CHECK: [0xfc,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, src_scc
+// CHECK: [0xfd,0x30,0x85,0xbe]
+
+s_movreld_b32 s5, 0xaf123456
+// CHECK: [0xff,0x30,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_movreld_b32 s5, 0x3f717273
+// CHECK: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_movreld_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x31,0x8c,0xbe]
+
+s_movreld_b64 s[102:103], s[2:3]
+// CHECK: [0x02,0x31,0xe6,0xbe]
+
+s_movreld_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x31,0xe8,0xbe]
+
+s_movreld_b64 vcc, s[2:3]
+// CHECK: [0x02,0x31,0xea,0xbe]
+
+s_movreld_b64 tba, s[2:3]
+// CHECK: [0x02,0x31,0xec,0xbe]
+
+s_movreld_b64 tma, s[2:3]
+// CHECK: [0x02,0x31,0xee,0xbe]
+
+s_movreld_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x31,0xfa,0xbe]
+
+s_movreld_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], s[102:103]
+// CHECK: [0x66,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], flat_scratch
+// CHECK: [0x68,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], vcc
+// CHECK: [0x6a,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], tba
+// CHECK: [0x6c,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], tma
+// CHECK: [0x6e,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], 0
+// CHECK: [0x80,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], -1
+// CHECK: [0xc1,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x31,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x31,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_movreld_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x31,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cbranch_join s1
+// CHECK: [0x01,0x32,0x80,0xbe]
+
+s_cbranch_join s103
+// CHECK: [0x67,0x32,0x80,0xbe]
+
+s_cbranch_join flat_scratch_lo
+// CHECK: [0x68,0x32,0x80,0xbe]
+
+s_cbranch_join flat_scratch_hi
+// CHECK: [0x69,0x32,0x80,0xbe]
+
+s_cbranch_join vcc_lo
+// CHECK: [0x6a,0x32,0x80,0xbe]
+
+s_cbranch_join vcc_hi
+// CHECK: [0x6b,0x32,0x80,0xbe]
+
+s_cbranch_join tba_lo
+// CHECK: [0x6c,0x32,0x80,0xbe]
+
+s_cbranch_join tba_hi
+// CHECK: [0x6d,0x32,0x80,0xbe]
+
+s_cbranch_join tma_lo
+// CHECK: [0x6e,0x32,0x80,0xbe]
+
+s_cbranch_join tma_hi
+// CHECK: [0x6f,0x32,0x80,0xbe]
+
+s_cbranch_join ttmp11
+// CHECK: [0x7b,0x32,0x80,0xbe]
+
+s_cbranch_join m0
+// CHECK: [0x7c,0x32,0x80,0xbe]
+
+s_cbranch_join exec_lo
+// CHECK: [0x7e,0x32,0x80,0xbe]
+
+s_cbranch_join exec_hi
+// CHECK: [0x7f,0x32,0x80,0xbe]
+
+s_cbranch_join src_vccz
+// CHECK: [0xfb,0x32,0x80,0xbe]
+
+s_cbranch_join src_execz
+// CHECK: [0xfc,0x32,0x80,0xbe]
+
+s_cbranch_join src_scc
+// CHECK: [0xfd,0x32,0x80,0xbe]
+
+s_abs_i32 s5, s1
+// CHECK: [0x01,0x34,0x85,0xbe]
+
+s_abs_i32 s103, s1
+// CHECK: [0x01,0x34,0xe7,0xbe]
+
+s_abs_i32 flat_scratch_lo, s1
+// CHECK: [0x01,0x34,0xe8,0xbe]
+
+s_abs_i32 flat_scratch_hi, s1
+// CHECK: [0x01,0x34,0xe9,0xbe]
+
+s_abs_i32 vcc_lo, s1
+// CHECK: [0x01,0x34,0xea,0xbe]
+
+s_abs_i32 vcc_hi, s1
+// CHECK: [0x01,0x34,0xeb,0xbe]
+
+s_abs_i32 tba_lo, s1
+// CHECK: [0x01,0x34,0xec,0xbe]
+
+s_abs_i32 tba_hi, s1
+// CHECK: [0x01,0x34,0xed,0xbe]
+
+s_abs_i32 tma_lo, s1
+// CHECK: [0x01,0x34,0xee,0xbe]
+
+s_abs_i32 tma_hi, s1
+// CHECK: [0x01,0x34,0xef,0xbe]
+
+s_abs_i32 ttmp11, s1
+// CHECK: [0x01,0x34,0xfb,0xbe]
+
+s_abs_i32 m0, s1
+// CHECK: [0x01,0x34,0xfc,0xbe]
+
+s_abs_i32 exec_lo, s1
+// CHECK: [0x01,0x34,0xfe,0xbe]
+
+s_abs_i32 exec_hi, s1
+// CHECK: [0x01,0x34,0xff,0xbe]
+
+s_abs_i32 s5, s103
+// CHECK: [0x67,0x34,0x85,0xbe]
+
+s_abs_i32 s5, flat_scratch_lo
+// CHECK: [0x68,0x34,0x85,0xbe]
+
+s_abs_i32 s5, flat_scratch_hi
+// CHECK: [0x69,0x34,0x85,0xbe]
+
+s_abs_i32 s5, vcc_lo
+// CHECK: [0x6a,0x34,0x85,0xbe]
+
+s_abs_i32 s5, vcc_hi
+// CHECK: [0x6b,0x34,0x85,0xbe]
+
+s_abs_i32 s5, tba_lo
+// CHECK: [0x6c,0x34,0x85,0xbe]
+
+s_abs_i32 s5, tba_hi
+// CHECK: [0x6d,0x34,0x85,0xbe]
+
+s_abs_i32 s5, tma_lo
+// CHECK: [0x6e,0x34,0x85,0xbe]
+
+s_abs_i32 s5, tma_hi
+// CHECK: [0x6f,0x34,0x85,0xbe]
+
+s_abs_i32 s5, ttmp11
+// CHECK: [0x7b,0x34,0x85,0xbe]
+
+s_abs_i32 s5, m0
+// CHECK: [0x7c,0x34,0x85,0xbe]
+
+s_abs_i32 s5, exec_lo
+// CHECK: [0x7e,0x34,0x85,0xbe]
+
+s_abs_i32 s5, exec_hi
+// CHECK: [0x7f,0x34,0x85,0xbe]
+
+s_abs_i32 s5, 0
+// CHECK: [0x80,0x34,0x85,0xbe]
+
+s_abs_i32 s5, -1
+// CHECK: [0xc1,0x34,0x85,0xbe]
+
+s_abs_i32 s5, 0.5
+// CHECK: [0xf0,0x34,0x85,0xbe]
+
+s_abs_i32 s5, -4.0
+// CHECK: [0xf7,0x34,0x85,0xbe]
+
+s_abs_i32 s5, src_vccz
+// CHECK: [0xfb,0x34,0x85,0xbe]
+
+s_abs_i32 s5, src_execz
+// CHECK: [0xfc,0x34,0x85,0xbe]
+
+s_abs_i32 s5, src_scc
+// CHECK: [0xfd,0x34,0x85,0xbe]
+
+s_abs_i32 s5, 0xaf123456
+// CHECK: [0xff,0x34,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_abs_i32 s5, 0x3f717273
+// CHECK: [0xff,0x34,0x85,0xbe,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx7_asm_sop2.s
new file mode 100644
index 0000000000000..aa9caaf69f8e8
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sop2.s
@@ -0,0 +1,6832 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+s_add_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x80]
+
+s_add_u32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x80]
+
+s_add_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x80]
+
+s_add_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x80]
+
+s_add_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x80]
+
+s_add_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x80]
+
+s_add_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x80]
+
+s_add_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x80]
+
+s_add_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x80]
+
+s_add_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x80]
+
+s_add_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x80]
+
+s_add_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x80]
+
+s_add_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x80]
+
+s_add_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x80]
+
+s_add_u32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x80]
+
+s_add_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x80]
+
+s_add_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x80]
+
+s_add_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x80]
+
+s_add_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x80]
+
+s_add_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x80]
+
+s_add_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x80]
+
+s_add_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x80]
+
+s_add_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x80]
+
+s_add_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x80]
+
+s_add_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x80]
+
+s_add_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x80]
+
+s_add_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x80]
+
+s_add_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x80]
+
+s_add_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x80]
+
+s_add_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x80]
+
+s_add_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x80]
+
+s_add_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x80]
+
+s_add_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x80]
+
+s_add_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x80]
+
+s_add_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x80,0x56,0x34,0x12,0xaf]
+
+s_add_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x80,0x73,0x72,0x71,0x3f]
+
+s_add_u32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x80]
+
+s_add_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x80]
+
+s_add_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x80]
+
+s_add_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x80]
+
+s_add_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x80]
+
+s_add_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x80]
+
+s_add_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x80]
+
+s_add_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x80]
+
+s_add_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x80]
+
+s_add_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x80]
+
+s_add_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x80]
+
+s_add_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x80]
+
+s_add_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x80]
+
+s_add_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x80]
+
+s_add_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x80]
+
+s_add_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x80]
+
+s_add_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x80]
+
+s_add_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x80]
+
+s_add_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x80]
+
+s_add_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x80]
+
+s_add_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x80,0x56,0x34,0x12,0xaf]
+
+s_add_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x80,0x73,0x72,0x71,0x3f]
+
+s_sub_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x80]
+
+s_sub_u32 s103, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x80]
+
+s_sub_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe8,0x80]
+
+s_sub_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe9,0x80]
+
+s_sub_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x80]
+
+s_sub_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x80]
+
+s_sub_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x80]
+
+s_sub_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x80]
+
+s_sub_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x80]
+
+s_sub_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x80]
+
+s_sub_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x80]
+
+s_sub_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x80]
+
+s_sub_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x80]
+
+s_sub_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x80]
+
+s_sub_u32 s5, s103, s2
+// CHECK: [0x67,0x02,0x85,0x80]
+
+s_sub_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x85,0x80]
+
+s_sub_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x85,0x80]
+
+s_sub_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x80]
+
+s_sub_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x80]
+
+s_sub_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x80]
+
+s_sub_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x80]
+
+s_sub_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x80]
+
+s_sub_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x80]
+
+s_sub_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x80]
+
+s_sub_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x80]
+
+s_sub_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x80]
+
+s_sub_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x80]
+
+s_sub_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x80]
+
+s_sub_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x80]
+
+s_sub_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x80]
+
+s_sub_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x80]
+
+s_sub_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x80]
+
+s_sub_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x80]
+
+s_sub_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x80]
+
+s_sub_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x80,0x56,0x34,0x12,0xaf]
+
+s_sub_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x80,0x73,0x72,0x71,0x3f]
+
+s_sub_u32 s5, s1, s103
+// CHECK: [0x01,0x67,0x85,0x80]
+
+s_sub_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x85,0x80]
+
+s_sub_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x85,0x80]
+
+s_sub_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x80]
+
+s_sub_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x80]
+
+s_sub_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x80]
+
+s_sub_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x80]
+
+s_sub_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x80]
+
+s_sub_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x80]
+
+s_sub_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x80]
+
+s_sub_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x80]
+
+s_sub_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x80]
+
+s_sub_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x80]
+
+s_sub_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x80]
+
+s_sub_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x80]
+
+s_sub_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x80]
+
+s_sub_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x80]
+
+s_sub_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x80]
+
+s_sub_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x80]
+
+s_sub_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x80]
+
+s_sub_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x80,0x56,0x34,0x12,0xaf]
+
+s_sub_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x80,0x73,0x72,0x71,0x3f]
+
+s_add_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x81]
+
+s_add_i32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x81]
+
+s_add_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x81]
+
+s_add_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x81]
+
+s_add_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x81]
+
+s_add_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x81]
+
+s_add_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x81]
+
+s_add_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x81]
+
+s_add_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x81]
+
+s_add_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x81]
+
+s_add_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x81]
+
+s_add_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x81]
+
+s_add_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x81]
+
+s_add_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x81]
+
+s_add_i32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x81]
+
+s_add_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x81]
+
+s_add_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x81]
+
+s_add_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x81]
+
+s_add_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x81]
+
+s_add_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x81]
+
+s_add_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x81]
+
+s_add_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x81]
+
+s_add_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x81]
+
+s_add_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x81]
+
+s_add_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x81]
+
+s_add_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x81]
+
+s_add_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x81]
+
+s_add_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x81]
+
+s_add_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x81]
+
+s_add_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x81]
+
+s_add_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x81]
+
+s_add_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x81]
+
+s_add_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x81]
+
+s_add_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x81]
+
+s_add_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x81,0x56,0x34,0x12,0xaf]
+
+s_add_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x81,0x73,0x72,0x71,0x3f]
+
+s_add_i32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x81]
+
+s_add_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x81]
+
+s_add_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x81]
+
+s_add_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x81]
+
+s_add_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x81]
+
+s_add_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x81]
+
+s_add_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x81]
+
+s_add_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x81]
+
+s_add_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x81]
+
+s_add_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x81]
+
+s_add_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x81]
+
+s_add_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x81]
+
+s_add_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x81]
+
+s_add_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x81]
+
+s_add_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x81]
+
+s_add_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x81]
+
+s_add_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x81]
+
+s_add_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x81]
+
+s_add_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x81]
+
+s_add_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x81]
+
+s_add_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x81,0x56,0x34,0x12,0xaf]
+
+s_add_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x81,0x73,0x72,0x71,0x3f]
+
+s_sub_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x81]
+
+s_sub_i32 s103, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x81]
+
+s_sub_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe8,0x81]
+
+s_sub_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe9,0x81]
+
+s_sub_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x81]
+
+s_sub_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x81]
+
+s_sub_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x81]
+
+s_sub_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x81]
+
+s_sub_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x81]
+
+s_sub_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x81]
+
+s_sub_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x81]
+
+s_sub_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x81]
+
+s_sub_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x81]
+
+s_sub_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x81]
+
+s_sub_i32 s5, s103, s2
+// CHECK: [0x67,0x02,0x85,0x81]
+
+s_sub_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x85,0x81]
+
+s_sub_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x85,0x81]
+
+s_sub_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x81]
+
+s_sub_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x81]
+
+s_sub_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x81]
+
+s_sub_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x81]
+
+s_sub_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x81]
+
+s_sub_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x81]
+
+s_sub_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x81]
+
+s_sub_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x81]
+
+s_sub_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x81]
+
+s_sub_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x81]
+
+s_sub_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x81]
+
+s_sub_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x81]
+
+s_sub_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x81]
+
+s_sub_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x81]
+
+s_sub_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x81]
+
+s_sub_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x81]
+
+s_sub_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x81]
+
+s_sub_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x81,0x56,0x34,0x12,0xaf]
+
+s_sub_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x81,0x73,0x72,0x71,0x3f]
+
+s_sub_i32 s5, s1, s103
+// CHECK: [0x01,0x67,0x85,0x81]
+
+s_sub_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x85,0x81]
+
+s_sub_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x85,0x81]
+
+s_sub_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x81]
+
+s_sub_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x81]
+
+s_sub_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x81]
+
+s_sub_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x81]
+
+s_sub_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x81]
+
+s_sub_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x81]
+
+s_sub_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x81]
+
+s_sub_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x81]
+
+s_sub_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x81]
+
+s_sub_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x81]
+
+s_sub_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x81]
+
+s_sub_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x81]
+
+s_sub_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x81]
+
+s_sub_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x81]
+
+s_sub_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x81]
+
+s_sub_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x81]
+
+s_sub_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x81]
+
+s_sub_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x81,0x56,0x34,0x12,0xaf]
+
+s_sub_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x81,0x73,0x72,0x71,0x3f]
+
+s_addc_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x82]
+
+s_addc_u32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x82]
+
+s_addc_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x82]
+
+s_addc_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x82]
+
+s_addc_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x82]
+
+s_addc_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x82]
+
+s_addc_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x82]
+
+s_addc_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x82]
+
+s_addc_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x82]
+
+s_addc_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x82]
+
+s_addc_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x82]
+
+s_addc_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x82]
+
+s_addc_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x82]
+
+s_addc_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x82]
+
+s_addc_u32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x82]
+
+s_addc_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x82]
+
+s_addc_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x82]
+
+s_addc_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x82]
+
+s_addc_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x82]
+
+s_addc_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x82]
+
+s_addc_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x82]
+
+s_addc_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x82]
+
+s_addc_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x82]
+
+s_addc_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x82]
+
+s_addc_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x82]
+
+s_addc_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x82]
+
+s_addc_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x82]
+
+s_addc_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x82]
+
+s_addc_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x82]
+
+s_addc_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x82]
+
+s_addc_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x82]
+
+s_addc_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x82]
+
+s_addc_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x82]
+
+s_addc_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x82]
+
+s_addc_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x82,0x56,0x34,0x12,0xaf]
+
+s_addc_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x82,0x73,0x72,0x71,0x3f]
+
+s_addc_u32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x82]
+
+s_addc_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x82]
+
+s_addc_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x82]
+
+s_addc_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x82]
+
+s_addc_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x82]
+
+s_addc_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x82]
+
+s_addc_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x82]
+
+s_addc_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x82]
+
+s_addc_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x82]
+
+s_addc_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x82]
+
+s_addc_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x82]
+
+s_addc_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x82]
+
+s_addc_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x82]
+
+s_addc_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x82]
+
+s_addc_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x82]
+
+s_addc_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x82]
+
+s_addc_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x82]
+
+s_addc_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x82]
+
+s_addc_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x82]
+
+s_addc_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x82]
+
+s_addc_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x82,0x56,0x34,0x12,0xaf]
+
+s_addc_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x82,0x73,0x72,0x71,0x3f]
+
+s_subb_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x82]
+
+s_subb_u32 s103, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x82]
+
+s_subb_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe8,0x82]
+
+s_subb_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe9,0x82]
+
+s_subb_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x82]
+
+s_subb_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x82]
+
+s_subb_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x82]
+
+s_subb_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x82]
+
+s_subb_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x82]
+
+s_subb_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x82]
+
+s_subb_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x82]
+
+s_subb_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x82]
+
+s_subb_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x82]
+
+s_subb_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x82]
+
+s_subb_u32 s5, s103, s2
+// CHECK: [0x67,0x02,0x85,0x82]
+
+s_subb_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x85,0x82]
+
+s_subb_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x85,0x82]
+
+s_subb_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x82]
+
+s_subb_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x82]
+
+s_subb_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x82]
+
+s_subb_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x82]
+
+s_subb_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x82]
+
+s_subb_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x82]
+
+s_subb_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x82]
+
+s_subb_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x82]
+
+s_subb_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x82]
+
+s_subb_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x82]
+
+s_subb_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x82]
+
+s_subb_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x82]
+
+s_subb_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x82]
+
+s_subb_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x82]
+
+s_subb_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x82]
+
+s_subb_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x82]
+
+s_subb_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x82]
+
+s_subb_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x82,0x56,0x34,0x12,0xaf]
+
+s_subb_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x82,0x73,0x72,0x71,0x3f]
+
+s_subb_u32 s5, s1, s103
+// CHECK: [0x01,0x67,0x85,0x82]
+
+s_subb_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x85,0x82]
+
+s_subb_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x85,0x82]
+
+s_subb_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x82]
+
+s_subb_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x82]
+
+s_subb_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x82]
+
+s_subb_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x82]
+
+s_subb_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x82]
+
+s_subb_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x82]
+
+s_subb_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x82]
+
+s_subb_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x82]
+
+s_subb_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x82]
+
+s_subb_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x82]
+
+s_subb_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x82]
+
+s_subb_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x82]
+
+s_subb_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x82]
+
+s_subb_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x82]
+
+s_subb_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x82]
+
+s_subb_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x82]
+
+s_subb_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x82]
+
+s_subb_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x82,0x56,0x34,0x12,0xaf]
+
+s_subb_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x82,0x73,0x72,0x71,0x3f]
+
+s_min_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x83]
+
+s_min_i32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x83]
+
+s_min_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x83]
+
+s_min_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x83]
+
+s_min_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x83]
+
+s_min_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x83]
+
+s_min_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x83]
+
+s_min_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x83]
+
+s_min_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x83]
+
+s_min_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x83]
+
+s_min_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x83]
+
+s_min_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x83]
+
+s_min_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x83]
+
+s_min_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x83]
+
+s_min_i32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x83]
+
+s_min_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x83]
+
+s_min_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x83]
+
+s_min_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x83]
+
+s_min_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x83]
+
+s_min_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x83]
+
+s_min_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x83]
+
+s_min_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x83]
+
+s_min_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x83]
+
+s_min_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x83]
+
+s_min_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x83]
+
+s_min_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x83]
+
+s_min_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x83]
+
+s_min_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x83]
+
+s_min_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x83]
+
+s_min_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x83]
+
+s_min_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x83]
+
+s_min_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x83]
+
+s_min_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x83]
+
+s_min_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x83]
+
+s_min_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_i32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x83]
+
+s_min_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x83]
+
+s_min_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x83]
+
+s_min_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x83]
+
+s_min_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x83]
+
+s_min_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x83]
+
+s_min_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x83]
+
+s_min_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x83]
+
+s_min_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x83]
+
+s_min_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x83]
+
+s_min_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x83]
+
+s_min_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x83]
+
+s_min_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x83]
+
+s_min_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x83]
+
+s_min_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x83]
+
+s_min_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x83]
+
+s_min_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x83]
+
+s_min_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x83]
+
+s_min_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x83]
+
+s_min_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x83]
+
+s_min_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x83]
+
+s_min_u32 s103, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x83]
+
+s_min_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe8,0x83]
+
+s_min_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe9,0x83]
+
+s_min_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x83]
+
+s_min_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x83]
+
+s_min_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x83]
+
+s_min_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x83]
+
+s_min_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x83]
+
+s_min_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x83]
+
+s_min_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x83]
+
+s_min_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x83]
+
+s_min_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x83]
+
+s_min_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x83]
+
+s_min_u32 s5, s103, s2
+// CHECK: [0x67,0x02,0x85,0x83]
+
+s_min_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x85,0x83]
+
+s_min_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x85,0x83]
+
+s_min_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x83]
+
+s_min_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x83]
+
+s_min_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x83]
+
+s_min_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x83]
+
+s_min_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x83]
+
+s_min_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x83]
+
+s_min_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x83]
+
+s_min_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x83]
+
+s_min_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x83]
+
+s_min_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x83]
+
+s_min_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x83]
+
+s_min_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x83]
+
+s_min_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x83]
+
+s_min_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x83]
+
+s_min_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x83]
+
+s_min_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x83]
+
+s_min_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x83]
+
+s_min_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_u32 s5, s1, s103
+// CHECK: [0x01,0x67,0x85,0x83]
+
+s_min_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x85,0x83]
+
+s_min_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x85,0x83]
+
+s_min_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x83]
+
+s_min_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x83]
+
+s_min_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x83]
+
+s_min_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x83]
+
+s_min_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x83]
+
+s_min_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x83]
+
+s_min_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x83]
+
+s_min_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x83]
+
+s_min_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x83]
+
+s_min_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x83]
+
+s_min_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x83]
+
+s_min_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x83]
+
+s_min_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x83]
+
+s_min_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x83]
+
+s_min_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x83]
+
+s_min_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x83]
+
+s_min_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x83]
+
+s_min_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x83,0x73,0x72,0x71,0x3f]
+
+s_max_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x84]
+
+s_max_i32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x84]
+
+s_max_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x84]
+
+s_max_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x84]
+
+s_max_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x84]
+
+s_max_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x84]
+
+s_max_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x84]
+
+s_max_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x84]
+
+s_max_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x84]
+
+s_max_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x84]
+
+s_max_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x84]
+
+s_max_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x84]
+
+s_max_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x84]
+
+s_max_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x84]
+
+s_max_i32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x84]
+
+s_max_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x84]
+
+s_max_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x84]
+
+s_max_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x84]
+
+s_max_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x84]
+
+s_max_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x84]
+
+s_max_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x84]
+
+s_max_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x84]
+
+s_max_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x84]
+
+s_max_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x84]
+
+s_max_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x84]
+
+s_max_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x84]
+
+s_max_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x84]
+
+s_max_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x84]
+
+s_max_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x84]
+
+s_max_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x84]
+
+s_max_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x84]
+
+s_max_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x84]
+
+s_max_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x84]
+
+s_max_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x84]
+
+s_max_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_i32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x84]
+
+s_max_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x84]
+
+s_max_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x84]
+
+s_max_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x84]
+
+s_max_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x84]
+
+s_max_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x84]
+
+s_max_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x84]
+
+s_max_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x84]
+
+s_max_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x84]
+
+s_max_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x84]
+
+s_max_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x84]
+
+s_max_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x84]
+
+s_max_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x84]
+
+s_max_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x84]
+
+s_max_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x84]
+
+s_max_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x84]
+
+s_max_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x84]
+
+s_max_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x84]
+
+s_max_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x84]
+
+s_max_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x84]
+
+s_max_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x84]
+
+s_max_u32 s103, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x84]
+
+s_max_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe8,0x84]
+
+s_max_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe9,0x84]
+
+s_max_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x84]
+
+s_max_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x84]
+
+s_max_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x84]
+
+s_max_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x84]
+
+s_max_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x84]
+
+s_max_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x84]
+
+s_max_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x84]
+
+s_max_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x84]
+
+s_max_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x84]
+
+s_max_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x84]
+
+s_max_u32 s5, s103, s2
+// CHECK: [0x67,0x02,0x85,0x84]
+
+s_max_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x85,0x84]
+
+s_max_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x85,0x84]
+
+s_max_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x84]
+
+s_max_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x84]
+
+s_max_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x84]
+
+s_max_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x84]
+
+s_max_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x84]
+
+s_max_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x84]
+
+s_max_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x84]
+
+s_max_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x84]
+
+s_max_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x84]
+
+s_max_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x84]
+
+s_max_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x84]
+
+s_max_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x84]
+
+s_max_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x84]
+
+s_max_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x84]
+
+s_max_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x84]
+
+s_max_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x84]
+
+s_max_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x84]
+
+s_max_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_u32 s5, s1, s103
+// CHECK: [0x01,0x67,0x85,0x84]
+
+s_max_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x85,0x84]
+
+s_max_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x85,0x84]
+
+s_max_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x84]
+
+s_max_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x84]
+
+s_max_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x84]
+
+s_max_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x84]
+
+s_max_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x84]
+
+s_max_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x84]
+
+s_max_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x84]
+
+s_max_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x84]
+
+s_max_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x84]
+
+s_max_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x84]
+
+s_max_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x84]
+
+s_max_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x84]
+
+s_max_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x84]
+
+s_max_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x84]
+
+s_max_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x84]
+
+s_max_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x84]
+
+s_max_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x84]
+
+s_max_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x84,0x73,0x72,0x71,0x3f]
+
+s_cselect_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x85]
+
+s_cselect_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x85]
+
+s_cselect_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x85]
+
+s_cselect_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x85]
+
+s_cselect_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x85]
+
+s_cselect_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x85]
+
+s_cselect_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x85]
+
+s_cselect_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x85]
+
+s_cselect_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x85]
+
+s_cselect_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x85]
+
+s_cselect_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x85]
+
+s_cselect_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x85]
+
+s_cselect_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x85]
+
+s_cselect_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x85]
+
+s_cselect_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x85]
+
+s_cselect_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x85]
+
+s_cselect_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x85]
+
+s_cselect_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x85]
+
+s_cselect_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x85]
+
+s_cselect_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x85]
+
+s_cselect_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x85]
+
+s_cselect_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x85]
+
+s_cselect_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x85]
+
+s_cselect_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x85]
+
+s_cselect_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x85]
+
+s_cselect_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x85]
+
+s_cselect_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x85]
+
+s_cselect_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x85]
+
+s_cselect_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x85]
+
+s_cselect_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x85]
+
+s_cselect_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x85]
+
+s_cselect_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x85]
+
+s_cselect_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x85]
+
+s_cselect_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x85]
+
+s_cselect_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x85]
+
+s_cselect_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x85]
+
+s_cselect_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x85]
+
+s_cselect_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x85]
+
+s_cselect_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x85]
+
+s_cselect_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x85]
+
+s_cselect_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x85]
+
+s_cselect_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x85]
+
+s_cselect_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x85]
+
+s_cselect_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x85]
+
+s_cselect_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x85]
+
+s_cselect_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x85]
+
+s_cselect_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x85]
+
+s_cselect_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x85]
+
+s_cselect_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x85]
+
+s_cselect_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x85]
+
+s_cselect_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x85]
+
+s_cselect_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x85]
+
+s_cselect_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x85]
+
+s_cselect_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x85]
+
+s_cselect_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x85]
+
+s_cselect_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x85]
+
+s_cselect_b64 s[102:103], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x85]
+
+s_cselect_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe8,0x85]
+
+s_cselect_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x85]
+
+s_cselect_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x85]
+
+s_cselect_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x85]
+
+s_cselect_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x85]
+
+s_cselect_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x85]
+
+s_cselect_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x85,0x73,0x72,0x71,0x3f]
+
+s_and_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x87]
+
+s_and_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x87]
+
+s_and_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x87]
+
+s_and_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x87]
+
+s_and_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x87]
+
+s_and_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x87]
+
+s_and_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x87]
+
+s_and_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x87]
+
+s_and_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x87]
+
+s_and_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x87]
+
+s_and_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x87]
+
+s_and_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x87]
+
+s_and_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x87]
+
+s_and_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x87]
+
+s_and_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x87]
+
+s_and_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x87]
+
+s_and_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x87]
+
+s_and_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x87]
+
+s_and_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x87]
+
+s_and_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x87]
+
+s_and_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x87]
+
+s_and_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x87]
+
+s_and_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x87]
+
+s_and_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x87]
+
+s_and_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x87]
+
+s_and_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x87]
+
+s_and_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x87]
+
+s_and_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x87]
+
+s_and_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x87]
+
+s_and_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x87]
+
+s_and_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x87]
+
+s_and_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x87]
+
+s_and_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x87]
+
+s_and_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x87]
+
+s_and_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x87,0x56,0x34,0x12,0xaf]
+
+s_and_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x87,0x73,0x72,0x71,0x3f]
+
+s_and_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x87]
+
+s_and_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x87]
+
+s_and_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x87]
+
+s_and_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x87]
+
+s_and_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x87]
+
+s_and_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x87]
+
+s_and_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x87]
+
+s_and_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x87]
+
+s_and_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x87]
+
+s_and_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x87]
+
+s_and_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x87]
+
+s_and_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x87]
+
+s_and_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x87]
+
+s_and_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x87]
+
+s_and_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x87]
+
+s_and_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x87]
+
+s_and_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x87]
+
+s_and_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x87]
+
+s_and_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x87]
+
+s_and_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x87]
+
+s_and_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x87,0x56,0x34,0x12,0xaf]
+
+s_and_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x87,0x73,0x72,0x71,0x3f]
+
+s_and_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x87]
+
+s_and_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x87]
+
+s_and_b64 s[102:103], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x87]
+
+s_and_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe8,0x87]
+
+s_and_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x87]
+
+s_and_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x87]
+
+s_and_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x87]
+
+s_and_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x87]
+
+s_and_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x87]
+
+s_and_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x87]
+
+s_and_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x87,0x56,0x34,0x12,0xaf]
+
+s_and_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x87,0x73,0x72,0x71,0x3f]
+
+s_and_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x87]
+
+s_and_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x87,0x56,0x34,0x12,0xaf]
+
+s_and_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x87,0x73,0x72,0x71,0x3f]
+
+s_or_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x88]
+
+s_or_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x88]
+
+s_or_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x88]
+
+s_or_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x88]
+
+s_or_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x88]
+
+s_or_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x88]
+
+s_or_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x88]
+
+s_or_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x88]
+
+s_or_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x88]
+
+s_or_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x88]
+
+s_or_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x88]
+
+s_or_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x88]
+
+s_or_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x88]
+
+s_or_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x88]
+
+s_or_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x88]
+
+s_or_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x88]
+
+s_or_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x88]
+
+s_or_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x88]
+
+s_or_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x88]
+
+s_or_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x88]
+
+s_or_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x88]
+
+s_or_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x88]
+
+s_or_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x88]
+
+s_or_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x88]
+
+s_or_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x88]
+
+s_or_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x88]
+
+s_or_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x88]
+
+s_or_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x88]
+
+s_or_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x88]
+
+s_or_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x88]
+
+s_or_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x88]
+
+s_or_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x88]
+
+s_or_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x88]
+
+s_or_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x88]
+
+s_or_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x88,0x56,0x34,0x12,0xaf]
+
+s_or_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x88,0x73,0x72,0x71,0x3f]
+
+s_or_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x88]
+
+s_or_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x88]
+
+s_or_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x88]
+
+s_or_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x88]
+
+s_or_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x88]
+
+s_or_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x88]
+
+s_or_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x88]
+
+s_or_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x88]
+
+s_or_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x88]
+
+s_or_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x88]
+
+s_or_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x88]
+
+s_or_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x88]
+
+s_or_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x88]
+
+s_or_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x88]
+
+s_or_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x88]
+
+s_or_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x88]
+
+s_or_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x88]
+
+s_or_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x88]
+
+s_or_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x88]
+
+s_or_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x88]
+
+s_or_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x88,0x56,0x34,0x12,0xaf]
+
+s_or_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x88,0x73,0x72,0x71,0x3f]
+
+s_or_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x88]
+
+s_or_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x88]
+
+s_or_b64 s[102:103], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x88]
+
+s_or_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe8,0x88]
+
+s_or_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x88]
+
+s_or_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x88]
+
+s_or_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x88]
+
+s_or_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x88]
+
+s_or_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x88]
+
+s_or_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x88]
+
+s_or_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x88,0x56,0x34,0x12,0xaf]
+
+s_or_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x88,0x73,0x72,0x71,0x3f]
+
+s_or_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x88]
+
+s_or_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x88,0x56,0x34,0x12,0xaf]
+
+s_or_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x88,0x73,0x72,0x71,0x3f]
+
+s_xor_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x89]
+
+s_xor_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x89]
+
+s_xor_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x89]
+
+s_xor_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x89]
+
+s_xor_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x89]
+
+s_xor_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x89]
+
+s_xor_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x89]
+
+s_xor_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x89]
+
+s_xor_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x89]
+
+s_xor_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x89]
+
+s_xor_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x89]
+
+s_xor_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x89]
+
+s_xor_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x89]
+
+s_xor_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x89]
+
+s_xor_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x89]
+
+s_xor_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x89]
+
+s_xor_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x89]
+
+s_xor_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x89]
+
+s_xor_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x89]
+
+s_xor_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x89]
+
+s_xor_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x89]
+
+s_xor_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x89]
+
+s_xor_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x89]
+
+s_xor_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x89]
+
+s_xor_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x89]
+
+s_xor_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x89]
+
+s_xor_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x89]
+
+s_xor_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x89]
+
+s_xor_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x89]
+
+s_xor_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x89]
+
+s_xor_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x89]
+
+s_xor_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x89]
+
+s_xor_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x89]
+
+s_xor_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x89]
+
+s_xor_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x89,0x56,0x34,0x12,0xaf]
+
+s_xor_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x89,0x73,0x72,0x71,0x3f]
+
+s_xor_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x89]
+
+s_xor_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x89]
+
+s_xor_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x89]
+
+s_xor_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x89]
+
+s_xor_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x89]
+
+s_xor_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x89]
+
+s_xor_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x89]
+
+s_xor_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x89]
+
+s_xor_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x89]
+
+s_xor_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x89]
+
+s_xor_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x89]
+
+s_xor_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x89]
+
+s_xor_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x89]
+
+s_xor_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x89]
+
+s_xor_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x89]
+
+s_xor_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x89]
+
+s_xor_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x89]
+
+s_xor_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x89]
+
+s_xor_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x89]
+
+s_xor_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x89]
+
+s_xor_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x89,0x56,0x34,0x12,0xaf]
+
+s_xor_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x89,0x73,0x72,0x71,0x3f]
+
+s_xor_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x89]
+
+s_xor_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x89]
+
+s_xor_b64 s[102:103], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x89]
+
+s_xor_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe8,0x89]
+
+s_xor_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x89]
+
+s_xor_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x89]
+
+s_xor_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x89]
+
+s_xor_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x89]
+
+s_xor_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x89]
+
+s_xor_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x89]
+
+s_xor_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x89,0x56,0x34,0x12,0xaf]
+
+s_xor_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x89,0x73,0x72,0x71,0x3f]
+
+s_xor_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x89]
+
+s_xor_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x89,0x56,0x34,0x12,0xaf]
+
+s_xor_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x89,0x73,0x72,0x71,0x3f]
+
+s_andn2_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8a]
+
+s_andn2_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8a]
+
+s_andn2_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x8a]
+
+s_andn2_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x8a]
+
+s_andn2_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8a]
+
+s_andn2_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8a]
+
+s_andn2_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8a]
+
+s_andn2_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8a]
+
+s_andn2_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8a]
+
+s_andn2_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8a]
+
+s_andn2_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8a]
+
+s_andn2_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8a]
+
+s_andn2_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8a]
+
+s_andn2_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8a]
+
+s_andn2_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8a]
+
+s_andn2_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8a,0x56,0x34,0x12,0xaf]
+
+s_andn2_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8a,0x73,0x72,0x71,0x3f]
+
+s_andn2_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x8a]
+
+s_andn2_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x8a]
+
+s_andn2_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x8a]
+
+s_andn2_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8a]
+
+s_andn2_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8a]
+
+s_andn2_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8a]
+
+s_andn2_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8a]
+
+s_andn2_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8a]
+
+s_andn2_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8a]
+
+s_andn2_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8a]
+
+s_andn2_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8a]
+
+s_andn2_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8a]
+
+s_andn2_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8a]
+
+s_andn2_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8a]
+
+s_andn2_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8a]
+
+s_andn2_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8a]
+
+s_andn2_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8a]
+
+s_andn2_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8a]
+
+s_andn2_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8a]
+
+s_andn2_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8a]
+
+s_andn2_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8a,0x56,0x34,0x12,0xaf]
+
+s_andn2_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8a,0x73,0x72,0x71,0x3f]
+
+s_andn2_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8a]
+
+s_andn2_b64 s[102:103], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8a]
+
+s_andn2_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe8,0x8a]
+
+s_andn2_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8a]
+
+s_andn2_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x8a]
+
+s_andn2_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x8a]
+
+s_andn2_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8a]
+
+s_andn2_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8a]
+
+s_andn2_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8a,0x56,0x34,0x12,0xaf]
+
+s_andn2_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8a,0x73,0x72,0x71,0x3f]
+
+s_andn2_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8a]
+
+s_andn2_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8a,0x56,0x34,0x12,0xaf]
+
+s_andn2_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8a,0x73,0x72,0x71,0x3f]
+
+s_orn2_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8b]
+
+s_orn2_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8b]
+
+s_orn2_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x8b]
+
+s_orn2_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x8b]
+
+s_orn2_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8b]
+
+s_orn2_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8b]
+
+s_orn2_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8b]
+
+s_orn2_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8b]
+
+s_orn2_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8b]
+
+s_orn2_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8b]
+
+s_orn2_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8b]
+
+s_orn2_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8b]
+
+s_orn2_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8b]
+
+s_orn2_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8b]
+
+s_orn2_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8b]
+
+s_orn2_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8b,0x56,0x34,0x12,0xaf]
+
+s_orn2_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8b,0x73,0x72,0x71,0x3f]
+
+s_orn2_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x8b]
+
+s_orn2_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x8b]
+
+s_orn2_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x8b]
+
+s_orn2_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8b]
+
+s_orn2_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8b]
+
+s_orn2_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8b]
+
+s_orn2_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8b]
+
+s_orn2_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8b]
+
+s_orn2_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8b]
+
+s_orn2_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8b]
+
+s_orn2_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8b]
+
+s_orn2_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8b]
+
+s_orn2_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8b]
+
+s_orn2_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8b]
+
+s_orn2_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8b]
+
+s_orn2_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8b]
+
+s_orn2_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8b]
+
+s_orn2_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8b]
+
+s_orn2_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8b]
+
+s_orn2_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8b]
+
+s_orn2_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8b,0x56,0x34,0x12,0xaf]
+
+s_orn2_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8b,0x73,0x72,0x71,0x3f]
+
+s_orn2_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8b]
+
+s_orn2_b64 s[102:103], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8b]
+
+s_orn2_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe8,0x8b]
+
+s_orn2_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8b]
+
+s_orn2_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x8b]
+
+s_orn2_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x8b]
+
+s_orn2_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8b]
+
+s_orn2_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8b]
+
+s_orn2_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8b,0x56,0x34,0x12,0xaf]
+
+s_orn2_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8b,0x73,0x72,0x71,0x3f]
+
+s_orn2_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8b]
+
+s_orn2_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8b,0x56,0x34,0x12,0xaf]
+
+s_orn2_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8b,0x73,0x72,0x71,0x3f]
+
+s_nand_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8c]
+
+s_nand_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8c]
+
+s_nand_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x8c]
+
+s_nand_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x8c]
+
+s_nand_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8c]
+
+s_nand_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8c]
+
+s_nand_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8c]
+
+s_nand_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8c]
+
+s_nand_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8c]
+
+s_nand_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8c]
+
+s_nand_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8c]
+
+s_nand_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8c]
+
+s_nand_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8c]
+
+s_nand_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8c]
+
+s_nand_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x8c]
+
+s_nand_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x8c]
+
+s_nand_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x8c]
+
+s_nand_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8c]
+
+s_nand_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8c]
+
+s_nand_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8c]
+
+s_nand_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8c]
+
+s_nand_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8c]
+
+s_nand_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8c]
+
+s_nand_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8c]
+
+s_nand_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8c]
+
+s_nand_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8c]
+
+s_nand_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8c]
+
+s_nand_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8c]
+
+s_nand_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8c]
+
+s_nand_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8c]
+
+s_nand_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8c]
+
+s_nand_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8c]
+
+s_nand_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8c]
+
+s_nand_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8c]
+
+s_nand_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nand_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nand_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x8c]
+
+s_nand_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x8c]
+
+s_nand_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x8c]
+
+s_nand_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8c]
+
+s_nand_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8c]
+
+s_nand_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8c]
+
+s_nand_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8c]
+
+s_nand_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8c]
+
+s_nand_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8c]
+
+s_nand_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8c]
+
+s_nand_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8c]
+
+s_nand_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8c]
+
+s_nand_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8c]
+
+s_nand_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8c]
+
+s_nand_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8c]
+
+s_nand_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8c]
+
+s_nand_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8c]
+
+s_nand_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8c]
+
+s_nand_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8c]
+
+s_nand_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8c]
+
+s_nand_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nand_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nand_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8c]
+
+s_nand_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8c]
+
+s_nand_b64 s[102:103], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8c]
+
+s_nand_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe8,0x8c]
+
+s_nand_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8c]
+
+s_nand_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x8c]
+
+s_nand_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x8c]
+
+s_nand_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8c]
+
+s_nand_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8c]
+
+s_nand_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8c]
+
+s_nand_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nand_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nand_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8c]
+
+s_nand_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nand_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nor_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8d]
+
+s_nor_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8d]
+
+s_nor_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x8d]
+
+s_nor_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x8d]
+
+s_nor_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8d]
+
+s_nor_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8d]
+
+s_nor_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8d]
+
+s_nor_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8d]
+
+s_nor_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8d]
+
+s_nor_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8d]
+
+s_nor_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8d]
+
+s_nor_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8d]
+
+s_nor_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8d]
+
+s_nor_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8d]
+
+s_nor_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x8d]
+
+s_nor_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x8d]
+
+s_nor_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x8d]
+
+s_nor_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8d]
+
+s_nor_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8d]
+
+s_nor_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8d]
+
+s_nor_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8d]
+
+s_nor_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8d]
+
+s_nor_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8d]
+
+s_nor_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8d]
+
+s_nor_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8d]
+
+s_nor_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8d]
+
+s_nor_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8d]
+
+s_nor_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8d]
+
+s_nor_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8d]
+
+s_nor_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8d]
+
+s_nor_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8d]
+
+s_nor_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8d]
+
+s_nor_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8d]
+
+s_nor_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8d]
+
+s_nor_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8d,0x56,0x34,0x12,0xaf]
+
+s_nor_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8d,0x73,0x72,0x71,0x3f]
+
+s_nor_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x8d]
+
+s_nor_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x8d]
+
+s_nor_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x8d]
+
+s_nor_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8d]
+
+s_nor_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8d]
+
+s_nor_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8d]
+
+s_nor_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8d]
+
+s_nor_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8d]
+
+s_nor_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8d]
+
+s_nor_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8d]
+
+s_nor_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8d]
+
+s_nor_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8d]
+
+s_nor_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8d]
+
+s_nor_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8d]
+
+s_nor_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8d]
+
+s_nor_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8d]
+
+s_nor_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8d]
+
+s_nor_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8d]
+
+s_nor_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8d]
+
+s_nor_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8d]
+
+s_nor_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8d,0x56,0x34,0x12,0xaf]
+
+s_nor_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8d,0x73,0x72,0x71,0x3f]
+
+s_nor_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8d]
+
+s_nor_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8d]
+
+s_nor_b64 s[102:103], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8d]
+
+s_nor_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe8,0x8d]
+
+s_nor_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8d]
+
+s_nor_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x8d]
+
+s_nor_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x8d]
+
+s_nor_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8d]
+
+s_nor_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8d]
+
+s_nor_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8d]
+
+s_nor_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8d,0x56,0x34,0x12,0xaf]
+
+s_nor_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8d,0x73,0x72,0x71,0x3f]
+
+s_nor_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8d]
+
+s_nor_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8d,0x56,0x34,0x12,0xaf]
+
+s_nor_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8d,0x73,0x72,0x71,0x3f]
+
+s_xnor_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8e]
+
+s_xnor_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8e]
+
+s_xnor_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x8e]
+
+s_xnor_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x8e]
+
+s_xnor_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8e]
+
+s_xnor_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8e]
+
+s_xnor_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8e]
+
+s_xnor_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8e]
+
+s_xnor_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8e]
+
+s_xnor_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8e]
+
+s_xnor_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8e]
+
+s_xnor_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8e]
+
+s_xnor_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8e]
+
+s_xnor_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8e]
+
+s_xnor_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8e]
+
+s_xnor_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8e,0x56,0x34,0x12,0xaf]
+
+s_xnor_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8e,0x73,0x72,0x71,0x3f]
+
+s_xnor_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x8e]
+
+s_xnor_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x8e]
+
+s_xnor_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x8e]
+
+s_xnor_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8e]
+
+s_xnor_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8e]
+
+s_xnor_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8e]
+
+s_xnor_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8e]
+
+s_xnor_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8e]
+
+s_xnor_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8e]
+
+s_xnor_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8e]
+
+s_xnor_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8e]
+
+s_xnor_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8e]
+
+s_xnor_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8e]
+
+s_xnor_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8e]
+
+s_xnor_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8e]
+
+s_xnor_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8e]
+
+s_xnor_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8e]
+
+s_xnor_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8e]
+
+s_xnor_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8e]
+
+s_xnor_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8e]
+
+s_xnor_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8e,0x56,0x34,0x12,0xaf]
+
+s_xnor_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8e,0x73,0x72,0x71,0x3f]
+
+s_xnor_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8e]
+
+s_xnor_b64 s[102:103], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8e]
+
+s_xnor_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe8,0x8e]
+
+s_xnor_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8e]
+
+s_xnor_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x8e]
+
+s_xnor_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x8e]
+
+s_xnor_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8e]
+
+s_xnor_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8e]
+
+s_xnor_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8e,0x56,0x34,0x12,0xaf]
+
+s_xnor_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8e,0x73,0x72,0x71,0x3f]
+
+s_xnor_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8e]
+
+s_xnor_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8e,0x56,0x34,0x12,0xaf]
+
+s_xnor_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8e,0x73,0x72,0x71,0x3f]
+
+s_lshl_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8f]
+
+s_lshl_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8f]
+
+s_lshl_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x8f]
+
+s_lshl_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x8f]
+
+s_lshl_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8f]
+
+s_lshl_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8f]
+
+s_lshl_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8f]
+
+s_lshl_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8f]
+
+s_lshl_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8f]
+
+s_lshl_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8f]
+
+s_lshl_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8f]
+
+s_lshl_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8f]
+
+s_lshl_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8f]
+
+s_lshl_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8f]
+
+s_lshl_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8f]
+
+s_lshl_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshl_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshl_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x8f]
+
+s_lshl_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x8f]
+
+s_lshl_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x8f]
+
+s_lshl_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8f]
+
+s_lshl_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8f]
+
+s_lshl_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8f]
+
+s_lshl_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8f]
+
+s_lshl_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8f]
+
+s_lshl_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8f]
+
+s_lshl_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8f]
+
+s_lshl_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8f]
+
+s_lshl_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8f]
+
+s_lshl_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8f]
+
+s_lshl_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8f]
+
+s_lshl_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8f]
+
+s_lshl_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8f]
+
+s_lshl_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8f]
+
+s_lshl_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8f]
+
+s_lshl_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8f]
+
+s_lshl_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8f]
+
+s_lshl_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshl_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshl_b64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x8f]
+
+s_lshl_b64 s[102:103], s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x8f]
+
+s_lshl_b64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe8,0x8f]
+
+s_lshl_b64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x8f]
+
+s_lshl_b64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0xec,0x8f]
+
+s_lshl_b64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0xee,0x8f]
+
+s_lshl_b64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x8f]
+
+s_lshl_b64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x8f]
+
+s_lshl_b64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[102:103], s2
+// CHECK: [0x66,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], flat_scratch, s2
+// CHECK: [0x68,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshl_b64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshl_b64 s[10:11], s[2:3], s103
+// CHECK: [0x02,0x67,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x68,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x69,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8f]
+
+s_lshl_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshl_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshr_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x90]
+
+s_lshr_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x90]
+
+s_lshr_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x90]
+
+s_lshr_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x90]
+
+s_lshr_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x90]
+
+s_lshr_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x90]
+
+s_lshr_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x90]
+
+s_lshr_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x90]
+
+s_lshr_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x90]
+
+s_lshr_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x90]
+
+s_lshr_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x90]
+
+s_lshr_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x90]
+
+s_lshr_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x90]
+
+s_lshr_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x90]
+
+s_lshr_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x90]
+
+s_lshr_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x90]
+
+s_lshr_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x90]
+
+s_lshr_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x90]
+
+s_lshr_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x90]
+
+s_lshr_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x90]
+
+s_lshr_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x90]
+
+s_lshr_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x90]
+
+s_lshr_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x90]
+
+s_lshr_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x90]
+
+s_lshr_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x90]
+
+s_lshr_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x90]
+
+s_lshr_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x90]
+
+s_lshr_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x90]
+
+s_lshr_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x90]
+
+s_lshr_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x90]
+
+s_lshr_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x90]
+
+s_lshr_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x90]
+
+s_lshr_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x90]
+
+s_lshr_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x90]
+
+s_lshr_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x90,0x56,0x34,0x12,0xaf]
+
+s_lshr_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x90,0x73,0x72,0x71,0x3f]
+
+s_lshr_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x90]
+
+s_lshr_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x90]
+
+s_lshr_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x90]
+
+s_lshr_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x90]
+
+s_lshr_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x90]
+
+s_lshr_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x90]
+
+s_lshr_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x90]
+
+s_lshr_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x90]
+
+s_lshr_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x90]
+
+s_lshr_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x90]
+
+s_lshr_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x90]
+
+s_lshr_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x90]
+
+s_lshr_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x90]
+
+s_lshr_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x90]
+
+s_lshr_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x90]
+
+s_lshr_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x90]
+
+s_lshr_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x90]
+
+s_lshr_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x90]
+
+s_lshr_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x90]
+
+s_lshr_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x90]
+
+s_lshr_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x90,0x56,0x34,0x12,0xaf]
+
+s_lshr_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x90,0x73,0x72,0x71,0x3f]
+
+s_lshr_b64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x90]
+
+s_lshr_b64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x90]
+
+s_lshr_b64 s[102:103], s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x90]
+
+s_lshr_b64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe8,0x90]
+
+s_lshr_b64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x90]
+
+s_lshr_b64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0xec,0x90]
+
+s_lshr_b64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0xee,0x90]
+
+s_lshr_b64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x90]
+
+s_lshr_b64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x90]
+
+s_lshr_b64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[102:103], s2
+// CHECK: [0x66,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], flat_scratch, s2
+// CHECK: [0x68,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x90]
+
+s_lshr_b64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x90,0x56,0x34,0x12,0xaf]
+
+s_lshr_b64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x90,0x73,0x72,0x71,0x3f]
+
+s_lshr_b64 s[10:11], s[2:3], s103
+// CHECK: [0x02,0x67,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x68,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x69,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x90]
+
+s_lshr_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x90,0x56,0x34,0x12,0xaf]
+
+s_lshr_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x90,0x73,0x72,0x71,0x3f]
+
+s_ashr_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x91]
+
+s_ashr_i32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x91]
+
+s_ashr_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x91]
+
+s_ashr_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x91]
+
+s_ashr_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x91]
+
+s_ashr_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x91]
+
+s_ashr_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x91]
+
+s_ashr_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x91]
+
+s_ashr_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x91]
+
+s_ashr_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x91]
+
+s_ashr_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x91]
+
+s_ashr_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x91]
+
+s_ashr_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x91]
+
+s_ashr_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x91]
+
+s_ashr_i32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x91]
+
+s_ashr_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x91]
+
+s_ashr_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x91]
+
+s_ashr_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x91]
+
+s_ashr_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x91]
+
+s_ashr_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x91]
+
+s_ashr_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x91]
+
+s_ashr_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x91]
+
+s_ashr_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x91]
+
+s_ashr_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x91]
+
+s_ashr_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x91]
+
+s_ashr_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x91]
+
+s_ashr_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x91]
+
+s_ashr_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x91]
+
+s_ashr_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x91]
+
+s_ashr_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x91]
+
+s_ashr_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x91]
+
+s_ashr_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x91]
+
+s_ashr_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x91]
+
+s_ashr_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x91]
+
+s_ashr_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x91,0x56,0x34,0x12,0xaf]
+
+s_ashr_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x91,0x73,0x72,0x71,0x3f]
+
+s_ashr_i32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x91]
+
+s_ashr_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x91]
+
+s_ashr_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x91]
+
+s_ashr_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x91]
+
+s_ashr_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x91]
+
+s_ashr_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x91]
+
+s_ashr_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x91]
+
+s_ashr_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x91]
+
+s_ashr_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x91]
+
+s_ashr_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x91]
+
+s_ashr_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x91]
+
+s_ashr_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x91]
+
+s_ashr_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x91]
+
+s_ashr_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x91]
+
+s_ashr_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x91]
+
+s_ashr_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x91]
+
+s_ashr_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x91]
+
+s_ashr_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x91]
+
+s_ashr_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x91]
+
+s_ashr_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x91]
+
+s_ashr_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x91,0x56,0x34,0x12,0xaf]
+
+s_ashr_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x91,0x73,0x72,0x71,0x3f]
+
+s_ashr_i64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x91]
+
+s_ashr_i64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x91]
+
+s_ashr_i64 s[102:103], s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x91]
+
+s_ashr_i64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe8,0x91]
+
+s_ashr_i64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x91]
+
+s_ashr_i64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0xec,0x91]
+
+s_ashr_i64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0xee,0x91]
+
+s_ashr_i64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x91]
+
+s_ashr_i64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x91]
+
+s_ashr_i64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[102:103], s2
+// CHECK: [0x66,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], flat_scratch, s2
+// CHECK: [0x68,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x91]
+
+s_ashr_i64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x91,0x56,0x34,0x12,0xaf]
+
+s_ashr_i64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x91,0x73,0x72,0x71,0x3f]
+
+s_ashr_i64 s[10:11], s[2:3], s103
+// CHECK: [0x02,0x67,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x68,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x69,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x91]
+
+s_ashr_i64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x91,0x56,0x34,0x12,0xaf]
+
+s_ashr_i64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x91,0x73,0x72,0x71,0x3f]
+
+s_bfm_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x92]
+
+s_bfm_b32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x92]
+
+s_bfm_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x92]
+
+s_bfm_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x92]
+
+s_bfm_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x92]
+
+s_bfm_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x92]
+
+s_bfm_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x92]
+
+s_bfm_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x92]
+
+s_bfm_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x92]
+
+s_bfm_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x92]
+
+s_bfm_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x92]
+
+s_bfm_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x92]
+
+s_bfm_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x92]
+
+s_bfm_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x92]
+
+s_bfm_b32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x92]
+
+s_bfm_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x92]
+
+s_bfm_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x92]
+
+s_bfm_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x92]
+
+s_bfm_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x92]
+
+s_bfm_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x92]
+
+s_bfm_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x92]
+
+s_bfm_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x92]
+
+s_bfm_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x92]
+
+s_bfm_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x92]
+
+s_bfm_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x92]
+
+s_bfm_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x92]
+
+s_bfm_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x92]
+
+s_bfm_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x92]
+
+s_bfm_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x92]
+
+s_bfm_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x92]
+
+s_bfm_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x92]
+
+s_bfm_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x92]
+
+s_bfm_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x92]
+
+s_bfm_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x92]
+
+s_bfm_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfm_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfm_b32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x92]
+
+s_bfm_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x92]
+
+s_bfm_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x92]
+
+s_bfm_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x92]
+
+s_bfm_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x92]
+
+s_bfm_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x92]
+
+s_bfm_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x92]
+
+s_bfm_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x92]
+
+s_bfm_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x92]
+
+s_bfm_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x92]
+
+s_bfm_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x92]
+
+s_bfm_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x92]
+
+s_bfm_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x92]
+
+s_bfm_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x92]
+
+s_bfm_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x92]
+
+s_bfm_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x92]
+
+s_bfm_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x92]
+
+s_bfm_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x92]
+
+s_bfm_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x92]
+
+s_bfm_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x92]
+
+s_bfm_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfm_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfm_b64 s[10:11], s1, s2
+// CHECK: [0x01,0x02,0x8a,0x92]
+
+s_bfm_b64 s[12:13], s1, s2
+// CHECK: [0x01,0x02,0x8c,0x92]
+
+s_bfm_b64 s[102:103], s1, s2
+// CHECK: [0x01,0x02,0xe6,0x92]
+
+s_bfm_b64 flat_scratch, s1, s2
+// CHECK: [0x01,0x02,0xe8,0x92]
+
+s_bfm_b64 vcc, s1, s2
+// CHECK: [0x01,0x02,0xea,0x92]
+
+s_bfm_b64 tba, s1, s2
+// CHECK: [0x01,0x02,0xec,0x92]
+
+s_bfm_b64 tma, s1, s2
+// CHECK: [0x01,0x02,0xee,0x92]
+
+s_bfm_b64 ttmp[10:11], s1, s2
+// CHECK: [0x01,0x02,0xfa,0x92]
+
+s_bfm_b64 exec, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x92]
+
+s_bfm_b64 s[10:11], s103, s2
+// CHECK: [0x67,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], vcc_lo, s2
+// CHECK: [0x6a,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], vcc_hi, s2
+// CHECK: [0x6b,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], tba_lo, s2
+// CHECK: [0x6c,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], tba_hi, s2
+// CHECK: [0x6d,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], tma_lo, s2
+// CHECK: [0x6e,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], tma_hi, s2
+// CHECK: [0x6f,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], ttmp11, s2
+// CHECK: [0x7b,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], m0, s2
+// CHECK: [0x7c,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], exec_lo, s2
+// CHECK: [0x7e,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], exec_hi, s2
+// CHECK: [0x7f,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x92]
+
+s_bfm_b64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfm_b64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfm_b64 s[10:11], s1, s103
+// CHECK: [0x01,0x67,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, vcc_lo
+// CHECK: [0x01,0x6a,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, vcc_hi
+// CHECK: [0x01,0x6b,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, tba_lo
+// CHECK: [0x01,0x6c,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, tba_hi
+// CHECK: [0x01,0x6d,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, tma_lo
+// CHECK: [0x01,0x6e,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, tma_hi
+// CHECK: [0x01,0x6f,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, ttmp11
+// CHECK: [0x01,0x7b,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, m0
+// CHECK: [0x01,0x7c,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, exec_lo
+// CHECK: [0x01,0x7e,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, exec_hi
+// CHECK: [0x01,0x7f,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, 0
+// CHECK: [0x01,0x80,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, -1
+// CHECK: [0x01,0xc1,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, 0.5
+// CHECK: [0x01,0xf0,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, -4.0
+// CHECK: [0x01,0xf7,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, src_vccz
+// CHECK: [0x01,0xfb,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, src_execz
+// CHECK: [0x01,0xfc,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, src_scc
+// CHECK: [0x01,0xfd,0x8a,0x92]
+
+s_bfm_b64 s[10:11], s1, 0xaf123456
+// CHECK: [0x01,0xff,0x8a,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfm_b64 s[10:11], s1, 0x3f717273
+// CHECK: [0x01,0xff,0x8a,0x92,0x73,0x72,0x71,0x3f]
+
+s_mul_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x93]
+
+s_mul_i32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x93]
+
+s_mul_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x93]
+
+s_mul_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x93]
+
+s_mul_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x93]
+
+s_mul_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x93]
+
+s_mul_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x93]
+
+s_mul_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x93]
+
+s_mul_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x93]
+
+s_mul_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x93]
+
+s_mul_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x93]
+
+s_mul_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x93]
+
+s_mul_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x93]
+
+s_mul_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x93]
+
+s_mul_i32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x93]
+
+s_mul_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x93]
+
+s_mul_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x93]
+
+s_mul_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x93]
+
+s_mul_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x93]
+
+s_mul_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x93]
+
+s_mul_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x93]
+
+s_mul_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x93]
+
+s_mul_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x93]
+
+s_mul_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x93]
+
+s_mul_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x93]
+
+s_mul_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x93]
+
+s_mul_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x93]
+
+s_mul_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x93]
+
+s_mul_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x93]
+
+s_mul_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x93]
+
+s_mul_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x93]
+
+s_mul_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x93]
+
+s_mul_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x93]
+
+s_mul_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x93]
+
+s_mul_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x93,0x56,0x34,0x12,0xaf]
+
+s_mul_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x93,0x73,0x72,0x71,0x3f]
+
+s_mul_i32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x93]
+
+s_mul_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x93]
+
+s_mul_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x93]
+
+s_mul_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x93]
+
+s_mul_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x93]
+
+s_mul_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x93]
+
+s_mul_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x93]
+
+s_mul_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x93]
+
+s_mul_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x93]
+
+s_mul_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x93]
+
+s_mul_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x93]
+
+s_mul_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x93]
+
+s_mul_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x93]
+
+s_mul_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x93]
+
+s_mul_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x93]
+
+s_mul_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x93]
+
+s_mul_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x93]
+
+s_mul_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x93]
+
+s_mul_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x93]
+
+s_mul_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x93]
+
+s_mul_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x93,0x56,0x34,0x12,0xaf]
+
+s_mul_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x93]
+
+s_bfe_u32 s103, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x93]
+
+s_bfe_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe8,0x93]
+
+s_bfe_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe9,0x93]
+
+s_bfe_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x93]
+
+s_bfe_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x93]
+
+s_bfe_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x93]
+
+s_bfe_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x93]
+
+s_bfe_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x93]
+
+s_bfe_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x93]
+
+s_bfe_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x93]
+
+s_bfe_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x93]
+
+s_bfe_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x93]
+
+s_bfe_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x93]
+
+s_bfe_u32 s5, s103, s2
+// CHECK: [0x67,0x02,0x85,0x93]
+
+s_bfe_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x85,0x93]
+
+s_bfe_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x85,0x93]
+
+s_bfe_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x93]
+
+s_bfe_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x93]
+
+s_bfe_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x93]
+
+s_bfe_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x93]
+
+s_bfe_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x93]
+
+s_bfe_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x93]
+
+s_bfe_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x93]
+
+s_bfe_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x93]
+
+s_bfe_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x93]
+
+s_bfe_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x93]
+
+s_bfe_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x93]
+
+s_bfe_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x93]
+
+s_bfe_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x93]
+
+s_bfe_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x93]
+
+s_bfe_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x93]
+
+s_bfe_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x93]
+
+s_bfe_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x93]
+
+s_bfe_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_u32 s5, s1, s103
+// CHECK: [0x01,0x67,0x85,0x93]
+
+s_bfe_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x85,0x93]
+
+s_bfe_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x85,0x93]
+
+s_bfe_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x93]
+
+s_bfe_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x93]
+
+s_bfe_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x93]
+
+s_bfe_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x93]
+
+s_bfe_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x93]
+
+s_bfe_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x93]
+
+s_bfe_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x93]
+
+s_bfe_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x93]
+
+s_bfe_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x93]
+
+s_bfe_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x93]
+
+s_bfe_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x93]
+
+s_bfe_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x93]
+
+s_bfe_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x93]
+
+s_bfe_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x93]
+
+s_bfe_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x93]
+
+s_bfe_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x93]
+
+s_bfe_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x93]
+
+s_bfe_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x94]
+
+s_bfe_i32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x94]
+
+s_bfe_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x94]
+
+s_bfe_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x94]
+
+s_bfe_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x94]
+
+s_bfe_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x94]
+
+s_bfe_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x94]
+
+s_bfe_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x94]
+
+s_bfe_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x94]
+
+s_bfe_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x94]
+
+s_bfe_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x94]
+
+s_bfe_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x94]
+
+s_bfe_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x94]
+
+s_bfe_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x94]
+
+s_bfe_i32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x94]
+
+s_bfe_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x94]
+
+s_bfe_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x94]
+
+s_bfe_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x94]
+
+s_bfe_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x94]
+
+s_bfe_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x94]
+
+s_bfe_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x94]
+
+s_bfe_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x94]
+
+s_bfe_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x94]
+
+s_bfe_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x94]
+
+s_bfe_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x94]
+
+s_bfe_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x94]
+
+s_bfe_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x94]
+
+s_bfe_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x94]
+
+s_bfe_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x94]
+
+s_bfe_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x94]
+
+s_bfe_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x94]
+
+s_bfe_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x94]
+
+s_bfe_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x94]
+
+s_bfe_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x94]
+
+s_bfe_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_i32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x94]
+
+s_bfe_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x94]
+
+s_bfe_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x94]
+
+s_bfe_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x94]
+
+s_bfe_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x94]
+
+s_bfe_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x94]
+
+s_bfe_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x94]
+
+s_bfe_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x94]
+
+s_bfe_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x94]
+
+s_bfe_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x94]
+
+s_bfe_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x94]
+
+s_bfe_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x94]
+
+s_bfe_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x94]
+
+s_bfe_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x94]
+
+s_bfe_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x94]
+
+s_bfe_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x94]
+
+s_bfe_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x94]
+
+s_bfe_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x94]
+
+s_bfe_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x94]
+
+s_bfe_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x94]
+
+s_bfe_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_u64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x94]
+
+s_bfe_u64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x94]
+
+s_bfe_u64 s[102:103], s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x94]
+
+s_bfe_u64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe8,0x94]
+
+s_bfe_u64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x94]
+
+s_bfe_u64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0xec,0x94]
+
+s_bfe_u64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0xee,0x94]
+
+s_bfe_u64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x94]
+
+s_bfe_u64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x94]
+
+s_bfe_u64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[102:103], s2
+// CHECK: [0x66,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], flat_scratch, s2
+// CHECK: [0x68,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x94]
+
+s_bfe_u64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_u64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_u64 s[10:11], s[2:3], s103
+// CHECK: [0x02,0x67,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x68,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x69,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x94]
+
+s_bfe_u64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_u64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_i64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x0a,0x95]
+
+s_bfe_i64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x0c,0x95]
+
+s_bfe_i64 s[102:103], s[2:3], s2
+// CHECK: [0x02,0x02,0x66,0x95]
+
+s_bfe_i64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0x68,0x95]
+
+s_bfe_i64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0x6a,0x95]
+
+s_bfe_i64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0x6c,0x95]
+
+s_bfe_i64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0x6e,0x95]
+
+s_bfe_i64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x7a,0x95]
+
+s_bfe_i64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0x7e,0x95]
+
+s_bfe_i64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[102:103], s2
+// CHECK: [0x66,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], flat_scratch, s2
+// CHECK: [0x68,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x0a,0x95]
+
+s_bfe_i64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0a,0x95,0x56,0x34,0x12,0xaf]
+
+s_bfe_i64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0a,0x95,0x73,0x72,0x71,0x3f]
+
+s_bfe_i64 s[10:11], s[2:3], s103
+// CHECK: [0x02,0x67,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x68,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x69,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x0a,0x95]
+
+s_bfe_i64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x0a,0x95,0x56,0x34,0x12,0xaf]
+
+s_bfe_i64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x0a,0x95,0x73,0x72,0x71,0x3f]
+
+s_cbranch_g_fork s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x80,0x95]
+
+s_cbranch_g_fork s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x80,0x95]
+
+s_cbranch_g_fork s[102:103], s[4:5]
+// CHECK: [0x66,0x04,0x80,0x95]
+
+s_cbranch_g_fork flat_scratch, s[4:5]
+// CHECK: [0x68,0x04,0x80,0x95]
+
+s_cbranch_g_fork vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x80,0x95]
+
+s_cbranch_g_fork tba, s[4:5]
+// CHECK: [0x6c,0x04,0x80,0x95]
+
+s_cbranch_g_fork tma, s[4:5]
+// CHECK: [0x6e,0x04,0x80,0x95]
+
+s_cbranch_g_fork ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x80,0x95]
+
+s_cbranch_g_fork exec, s[4:5]
+// CHECK: [0x7e,0x04,0x80,0x95]
+
+s_cbranch_g_fork 0, s[4:5]
+// CHECK: [0x80,0x04,0x80,0x95]
+
+s_cbranch_g_fork -1, s[4:5]
+// CHECK: [0xc1,0x04,0x80,0x95]
+
+s_cbranch_g_fork 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x80,0x95]
+
+s_cbranch_g_fork -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x80,0x95]
+
+s_cbranch_g_fork src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x80,0x95]
+
+s_cbranch_g_fork src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x80,0x95]
+
+s_cbranch_g_fork src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], s[102:103]
+// CHECK: [0x02,0x66,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], flat_scratch
+// CHECK: [0x02,0x68,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], vcc
+// CHECK: [0x02,0x6a,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], tba
+// CHECK: [0x02,0x6c,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], tma
+// CHECK: [0x02,0x6e,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], exec
+// CHECK: [0x02,0x7e,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], 0
+// CHECK: [0x02,0x80,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], -1
+// CHECK: [0x02,0xc1,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x80,0x95]
+
+s_cbranch_g_fork s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x80,0x95]
+
+s_absdiff_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x96]
+
+s_absdiff_i32 s103, s1, s2
+// CHECK: [0x01,0x02,0x67,0x96]
+
+s_absdiff_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x68,0x96]
+
+s_absdiff_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x69,0x96]
+
+s_absdiff_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x96]
+
+s_absdiff_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x96]
+
+s_absdiff_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x96]
+
+s_absdiff_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x96]
+
+s_absdiff_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x96]
+
+s_absdiff_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x96]
+
+s_absdiff_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x96]
+
+s_absdiff_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x96]
+
+s_absdiff_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x96]
+
+s_absdiff_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x96]
+
+s_absdiff_i32 s5, s103, s2
+// CHECK: [0x67,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x96]
+
+s_absdiff_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x96,0x56,0x34,0x12,0xaf]
+
+s_absdiff_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x96,0x73,0x72,0x71,0x3f]
+
+s_absdiff_i32 s5, s1, s103
+// CHECK: [0x01,0x67,0x05,0x96]
+
+s_absdiff_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0x96]
+
+s_absdiff_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0x96]
+
+s_absdiff_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x96]
+
+s_absdiff_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x96]
+
+s_absdiff_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x96]
+
+s_absdiff_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x96]
+
+s_absdiff_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x96]
+
+s_absdiff_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x96]
+
+s_absdiff_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x96]
+
+s_absdiff_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x96]
+
+s_absdiff_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x96]
+
+s_absdiff_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x96]
+
+s_absdiff_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x96]
+
+s_absdiff_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x96]
+
+s_absdiff_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x96]
+
+s_absdiff_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x96]
+
+s_absdiff_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x96]
+
+s_absdiff_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x96]
+
+s_absdiff_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x96]
+
+s_absdiff_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x96,0x56,0x34,0x12,0xaf]
+
+s_absdiff_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x96,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx7_asm_sopc.s
new file mode 100644
index 0000000000000..ec0f43b90ed07
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sopc.s
@@ -0,0 +1,2266 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+s_cmp_eq_i32 s1, s2
+// CHECK: [0x01,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 s103, s2
+// CHECK: [0x67,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 m0, s2
+// CHECK: [0x7c,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 0, s2
+// CHECK: [0x80,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 -1, s2
+// CHECK: [0xc1,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x00,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x00,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_i32 s1, s103
+// CHECK: [0x01,0x67,0x00,0xbf]
+
+s_cmp_eq_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x00,0xbf]
+
+s_cmp_eq_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x00,0xbf]
+
+s_cmp_eq_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x00,0xbf]
+
+s_cmp_eq_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x00,0xbf]
+
+s_cmp_eq_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x00,0xbf]
+
+s_cmp_eq_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x00,0xbf]
+
+s_cmp_eq_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x00,0xbf]
+
+s_cmp_eq_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x00,0xbf]
+
+s_cmp_eq_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x00,0xbf]
+
+s_cmp_eq_i32 s1, m0
+// CHECK: [0x01,0x7c,0x00,0xbf]
+
+s_cmp_eq_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x00,0xbf]
+
+s_cmp_eq_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x00,0xbf]
+
+s_cmp_eq_i32 s1, 0
+// CHECK: [0x01,0x80,0x00,0xbf]
+
+s_cmp_eq_i32 s1, -1
+// CHECK: [0x01,0xc1,0x00,0xbf]
+
+s_cmp_eq_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x00,0xbf]
+
+s_cmp_eq_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x00,0xbf]
+
+s_cmp_eq_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x00,0xbf]
+
+s_cmp_eq_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x00,0xbf]
+
+s_cmp_eq_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x00,0xbf]
+
+s_cmp_eq_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_i32 s1, s2
+// CHECK: [0x01,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 s103, s2
+// CHECK: [0x67,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 m0, s2
+// CHECK: [0x7c,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 0, s2
+// CHECK: [0x80,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 -1, s2
+// CHECK: [0xc1,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x01,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x01,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_i32 s1, s103
+// CHECK: [0x01,0x67,0x01,0xbf]
+
+s_cmp_lg_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x01,0xbf]
+
+s_cmp_lg_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x01,0xbf]
+
+s_cmp_lg_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x01,0xbf]
+
+s_cmp_lg_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x01,0xbf]
+
+s_cmp_lg_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x01,0xbf]
+
+s_cmp_lg_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x01,0xbf]
+
+s_cmp_lg_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x01,0xbf]
+
+s_cmp_lg_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x01,0xbf]
+
+s_cmp_lg_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x01,0xbf]
+
+s_cmp_lg_i32 s1, m0
+// CHECK: [0x01,0x7c,0x01,0xbf]
+
+s_cmp_lg_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x01,0xbf]
+
+s_cmp_lg_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x01,0xbf]
+
+s_cmp_lg_i32 s1, 0
+// CHECK: [0x01,0x80,0x01,0xbf]
+
+s_cmp_lg_i32 s1, -1
+// CHECK: [0x01,0xc1,0x01,0xbf]
+
+s_cmp_lg_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x01,0xbf]
+
+s_cmp_lg_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x01,0xbf]
+
+s_cmp_lg_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x01,0xbf]
+
+s_cmp_lg_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x01,0xbf]
+
+s_cmp_lg_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x01,0xbf]
+
+s_cmp_lg_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_i32 s1, s2
+// CHECK: [0x01,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 s103, s2
+// CHECK: [0x67,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 m0, s2
+// CHECK: [0x7c,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 0, s2
+// CHECK: [0x80,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 -1, s2
+// CHECK: [0xc1,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x02,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x02,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_i32 s1, s103
+// CHECK: [0x01,0x67,0x02,0xbf]
+
+s_cmp_gt_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x02,0xbf]
+
+s_cmp_gt_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x02,0xbf]
+
+s_cmp_gt_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x02,0xbf]
+
+s_cmp_gt_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x02,0xbf]
+
+s_cmp_gt_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x02,0xbf]
+
+s_cmp_gt_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x02,0xbf]
+
+s_cmp_gt_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x02,0xbf]
+
+s_cmp_gt_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x02,0xbf]
+
+s_cmp_gt_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x02,0xbf]
+
+s_cmp_gt_i32 s1, m0
+// CHECK: [0x01,0x7c,0x02,0xbf]
+
+s_cmp_gt_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x02,0xbf]
+
+s_cmp_gt_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x02,0xbf]
+
+s_cmp_gt_i32 s1, 0
+// CHECK: [0x01,0x80,0x02,0xbf]
+
+s_cmp_gt_i32 s1, -1
+// CHECK: [0x01,0xc1,0x02,0xbf]
+
+s_cmp_gt_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x02,0xbf]
+
+s_cmp_gt_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x02,0xbf]
+
+s_cmp_gt_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x02,0xbf]
+
+s_cmp_gt_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x02,0xbf]
+
+s_cmp_gt_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x02,0xbf]
+
+s_cmp_gt_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_i32 s1, s2
+// CHECK: [0x01,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 s103, s2
+// CHECK: [0x67,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 m0, s2
+// CHECK: [0x7c,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 0, s2
+// CHECK: [0x80,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 -1, s2
+// CHECK: [0xc1,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x03,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x03,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_i32 s1, s103
+// CHECK: [0x01,0x67,0x03,0xbf]
+
+s_cmp_ge_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x03,0xbf]
+
+s_cmp_ge_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x03,0xbf]
+
+s_cmp_ge_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x03,0xbf]
+
+s_cmp_ge_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x03,0xbf]
+
+s_cmp_ge_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x03,0xbf]
+
+s_cmp_ge_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x03,0xbf]
+
+s_cmp_ge_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x03,0xbf]
+
+s_cmp_ge_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x03,0xbf]
+
+s_cmp_ge_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x03,0xbf]
+
+s_cmp_ge_i32 s1, m0
+// CHECK: [0x01,0x7c,0x03,0xbf]
+
+s_cmp_ge_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x03,0xbf]
+
+s_cmp_ge_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x03,0xbf]
+
+s_cmp_ge_i32 s1, 0
+// CHECK: [0x01,0x80,0x03,0xbf]
+
+s_cmp_ge_i32 s1, -1
+// CHECK: [0x01,0xc1,0x03,0xbf]
+
+s_cmp_ge_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x03,0xbf]
+
+s_cmp_ge_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x03,0xbf]
+
+s_cmp_ge_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x03,0xbf]
+
+s_cmp_ge_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x03,0xbf]
+
+s_cmp_ge_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x03,0xbf]
+
+s_cmp_ge_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_i32 s1, s2
+// CHECK: [0x01,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 s103, s2
+// CHECK: [0x67,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 m0, s2
+// CHECK: [0x7c,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 0, s2
+// CHECK: [0x80,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 -1, s2
+// CHECK: [0xc1,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x04,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x04,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_i32 s1, s103
+// CHECK: [0x01,0x67,0x04,0xbf]
+
+s_cmp_lt_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x04,0xbf]
+
+s_cmp_lt_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x04,0xbf]
+
+s_cmp_lt_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x04,0xbf]
+
+s_cmp_lt_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x04,0xbf]
+
+s_cmp_lt_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x04,0xbf]
+
+s_cmp_lt_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x04,0xbf]
+
+s_cmp_lt_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x04,0xbf]
+
+s_cmp_lt_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x04,0xbf]
+
+s_cmp_lt_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x04,0xbf]
+
+s_cmp_lt_i32 s1, m0
+// CHECK: [0x01,0x7c,0x04,0xbf]
+
+s_cmp_lt_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x04,0xbf]
+
+s_cmp_lt_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x04,0xbf]
+
+s_cmp_lt_i32 s1, 0
+// CHECK: [0x01,0x80,0x04,0xbf]
+
+s_cmp_lt_i32 s1, -1
+// CHECK: [0x01,0xc1,0x04,0xbf]
+
+s_cmp_lt_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x04,0xbf]
+
+s_cmp_lt_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x04,0xbf]
+
+s_cmp_lt_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x04,0xbf]
+
+s_cmp_lt_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x04,0xbf]
+
+s_cmp_lt_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x04,0xbf]
+
+s_cmp_lt_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_i32 s1, s2
+// CHECK: [0x01,0x02,0x05,0xbf]
+
+s_cmp_le_i32 s103, s2
+// CHECK: [0x67,0x02,0x05,0xbf]
+
+s_cmp_le_i32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x05,0xbf]
+
+s_cmp_le_i32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x05,0xbf]
+
+s_cmp_le_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0xbf]
+
+s_cmp_le_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0xbf]
+
+s_cmp_le_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0xbf]
+
+s_cmp_le_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0xbf]
+
+s_cmp_le_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0xbf]
+
+s_cmp_le_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0xbf]
+
+s_cmp_le_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0xbf]
+
+s_cmp_le_i32 m0, s2
+// CHECK: [0x7c,0x02,0x05,0xbf]
+
+s_cmp_le_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0xbf]
+
+s_cmp_le_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0xbf]
+
+s_cmp_le_i32 0, s2
+// CHECK: [0x80,0x02,0x05,0xbf]
+
+s_cmp_le_i32 -1, s2
+// CHECK: [0xc1,0x02,0x05,0xbf]
+
+s_cmp_le_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0xbf]
+
+s_cmp_le_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0xbf]
+
+s_cmp_le_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0xbf]
+
+s_cmp_le_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0xbf]
+
+s_cmp_le_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0xbf]
+
+s_cmp_le_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_i32 s1, s103
+// CHECK: [0x01,0x67,0x05,0xbf]
+
+s_cmp_le_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x05,0xbf]
+
+s_cmp_le_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x05,0xbf]
+
+s_cmp_le_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0xbf]
+
+s_cmp_le_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0xbf]
+
+s_cmp_le_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0xbf]
+
+s_cmp_le_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0xbf]
+
+s_cmp_le_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0xbf]
+
+s_cmp_le_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0xbf]
+
+s_cmp_le_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0xbf]
+
+s_cmp_le_i32 s1, m0
+// CHECK: [0x01,0x7c,0x05,0xbf]
+
+s_cmp_le_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0xbf]
+
+s_cmp_le_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0xbf]
+
+s_cmp_le_i32 s1, 0
+// CHECK: [0x01,0x80,0x05,0xbf]
+
+s_cmp_le_i32 s1, -1
+// CHECK: [0x01,0xc1,0x05,0xbf]
+
+s_cmp_le_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0xbf]
+
+s_cmp_le_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0xbf]
+
+s_cmp_le_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0xbf]
+
+s_cmp_le_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0xbf]
+
+s_cmp_le_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0xbf]
+
+s_cmp_le_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u32 s1, s2
+// CHECK: [0x01,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 s103, s2
+// CHECK: [0x67,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 m0, s2
+// CHECK: [0x7c,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 0, s2
+// CHECK: [0x80,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 -1, s2
+// CHECK: [0xc1,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x06,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x06,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u32 s1, s103
+// CHECK: [0x01,0x67,0x06,0xbf]
+
+s_cmp_eq_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x06,0xbf]
+
+s_cmp_eq_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x06,0xbf]
+
+s_cmp_eq_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x06,0xbf]
+
+s_cmp_eq_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x06,0xbf]
+
+s_cmp_eq_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x06,0xbf]
+
+s_cmp_eq_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x06,0xbf]
+
+s_cmp_eq_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x06,0xbf]
+
+s_cmp_eq_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x06,0xbf]
+
+s_cmp_eq_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x06,0xbf]
+
+s_cmp_eq_u32 s1, m0
+// CHECK: [0x01,0x7c,0x06,0xbf]
+
+s_cmp_eq_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x06,0xbf]
+
+s_cmp_eq_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x06,0xbf]
+
+s_cmp_eq_u32 s1, 0
+// CHECK: [0x01,0x80,0x06,0xbf]
+
+s_cmp_eq_u32 s1, -1
+// CHECK: [0x01,0xc1,0x06,0xbf]
+
+s_cmp_eq_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x06,0xbf]
+
+s_cmp_eq_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x06,0xbf]
+
+s_cmp_eq_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x06,0xbf]
+
+s_cmp_eq_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x06,0xbf]
+
+s_cmp_eq_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x06,0xbf]
+
+s_cmp_eq_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u32 s1, s2
+// CHECK: [0x01,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 s103, s2
+// CHECK: [0x67,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 m0, s2
+// CHECK: [0x7c,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 0, s2
+// CHECK: [0x80,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 -1, s2
+// CHECK: [0xc1,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x07,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x07,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u32 s1, s103
+// CHECK: [0x01,0x67,0x07,0xbf]
+
+s_cmp_lg_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x07,0xbf]
+
+s_cmp_lg_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x07,0xbf]
+
+s_cmp_lg_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x07,0xbf]
+
+s_cmp_lg_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x07,0xbf]
+
+s_cmp_lg_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x07,0xbf]
+
+s_cmp_lg_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x07,0xbf]
+
+s_cmp_lg_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x07,0xbf]
+
+s_cmp_lg_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x07,0xbf]
+
+s_cmp_lg_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x07,0xbf]
+
+s_cmp_lg_u32 s1, m0
+// CHECK: [0x01,0x7c,0x07,0xbf]
+
+s_cmp_lg_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x07,0xbf]
+
+s_cmp_lg_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x07,0xbf]
+
+s_cmp_lg_u32 s1, 0
+// CHECK: [0x01,0x80,0x07,0xbf]
+
+s_cmp_lg_u32 s1, -1
+// CHECK: [0x01,0xc1,0x07,0xbf]
+
+s_cmp_lg_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x07,0xbf]
+
+s_cmp_lg_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x07,0xbf]
+
+s_cmp_lg_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x07,0xbf]
+
+s_cmp_lg_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x07,0xbf]
+
+s_cmp_lg_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x07,0xbf]
+
+s_cmp_lg_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_u32 s1, s2
+// CHECK: [0x01,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 s103, s2
+// CHECK: [0x67,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 m0, s2
+// CHECK: [0x7c,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 0, s2
+// CHECK: [0x80,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 -1, s2
+// CHECK: [0xc1,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x08,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x08,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_u32 s1, s103
+// CHECK: [0x01,0x67,0x08,0xbf]
+
+s_cmp_gt_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x08,0xbf]
+
+s_cmp_gt_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x08,0xbf]
+
+s_cmp_gt_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x08,0xbf]
+
+s_cmp_gt_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x08,0xbf]
+
+s_cmp_gt_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x08,0xbf]
+
+s_cmp_gt_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x08,0xbf]
+
+s_cmp_gt_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x08,0xbf]
+
+s_cmp_gt_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x08,0xbf]
+
+s_cmp_gt_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x08,0xbf]
+
+s_cmp_gt_u32 s1, m0
+// CHECK: [0x01,0x7c,0x08,0xbf]
+
+s_cmp_gt_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x08,0xbf]
+
+s_cmp_gt_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x08,0xbf]
+
+s_cmp_gt_u32 s1, 0
+// CHECK: [0x01,0x80,0x08,0xbf]
+
+s_cmp_gt_u32 s1, -1
+// CHECK: [0x01,0xc1,0x08,0xbf]
+
+s_cmp_gt_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x08,0xbf]
+
+s_cmp_gt_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x08,0xbf]
+
+s_cmp_gt_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x08,0xbf]
+
+s_cmp_gt_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x08,0xbf]
+
+s_cmp_gt_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x08,0xbf]
+
+s_cmp_gt_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_u32 s1, s2
+// CHECK: [0x01,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 s103, s2
+// CHECK: [0x67,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 m0, s2
+// CHECK: [0x7c,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 0, s2
+// CHECK: [0x80,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 -1, s2
+// CHECK: [0xc1,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x09,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x09,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_u32 s1, s103
+// CHECK: [0x01,0x67,0x09,0xbf]
+
+s_cmp_ge_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x09,0xbf]
+
+s_cmp_ge_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x09,0xbf]
+
+s_cmp_ge_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x09,0xbf]
+
+s_cmp_ge_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x09,0xbf]
+
+s_cmp_ge_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x09,0xbf]
+
+s_cmp_ge_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x09,0xbf]
+
+s_cmp_ge_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x09,0xbf]
+
+s_cmp_ge_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x09,0xbf]
+
+s_cmp_ge_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x09,0xbf]
+
+s_cmp_ge_u32 s1, m0
+// CHECK: [0x01,0x7c,0x09,0xbf]
+
+s_cmp_ge_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x09,0xbf]
+
+s_cmp_ge_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x09,0xbf]
+
+s_cmp_ge_u32 s1, 0
+// CHECK: [0x01,0x80,0x09,0xbf]
+
+s_cmp_ge_u32 s1, -1
+// CHECK: [0x01,0xc1,0x09,0xbf]
+
+s_cmp_ge_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x09,0xbf]
+
+s_cmp_ge_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x09,0xbf]
+
+s_cmp_ge_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x09,0xbf]
+
+s_cmp_ge_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x09,0xbf]
+
+s_cmp_ge_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x09,0xbf]
+
+s_cmp_ge_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_u32 s1, s2
+// CHECK: [0x01,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 s103, s2
+// CHECK: [0x67,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 m0, s2
+// CHECK: [0x7c,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 0, s2
+// CHECK: [0x80,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 -1, s2
+// CHECK: [0xc1,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0a,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0a,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_u32 s1, s103
+// CHECK: [0x01,0x67,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, m0
+// CHECK: [0x01,0x7c,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, 0
+// CHECK: [0x01,0x80,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, -1
+// CHECK: [0x01,0xc1,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_u32 s1, s2
+// CHECK: [0x01,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 s103, s2
+// CHECK: [0x67,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 m0, s2
+// CHECK: [0x7c,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 0, s2
+// CHECK: [0x80,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 -1, s2
+// CHECK: [0xc1,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0b,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0b,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_u32 s1, s103
+// CHECK: [0x01,0x67,0x0b,0xbf]
+
+s_cmp_le_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x0b,0xbf]
+
+s_cmp_le_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x0b,0xbf]
+
+s_cmp_le_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0b,0xbf]
+
+s_cmp_le_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0b,0xbf]
+
+s_cmp_le_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x0b,0xbf]
+
+s_cmp_le_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x0b,0xbf]
+
+s_cmp_le_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x0b,0xbf]
+
+s_cmp_le_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x0b,0xbf]
+
+s_cmp_le_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x0b,0xbf]
+
+s_cmp_le_u32 s1, m0
+// CHECK: [0x01,0x7c,0x0b,0xbf]
+
+s_cmp_le_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0b,0xbf]
+
+s_cmp_le_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0b,0xbf]
+
+s_cmp_le_u32 s1, 0
+// CHECK: [0x01,0x80,0x0b,0xbf]
+
+s_cmp_le_u32 s1, -1
+// CHECK: [0x01,0xc1,0x0b,0xbf]
+
+s_cmp_le_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0b,0xbf]
+
+s_cmp_le_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0b,0xbf]
+
+s_cmp_le_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0b,0xbf]
+
+s_cmp_le_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0b,0xbf]
+
+s_cmp_le_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0b,0xbf]
+
+s_cmp_le_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b32 s1, s2
+// CHECK: [0x01,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 s103, s2
+// CHECK: [0x67,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 m0, s2
+// CHECK: [0x7c,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 0, s2
+// CHECK: [0x80,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 -1, s2
+// CHECK: [0xc1,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 0.5, s2
+// CHECK: [0xf0,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0c,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0c,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b32 s1, s103
+// CHECK: [0x01,0x67,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, m0
+// CHECK: [0x01,0x7c,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, 0
+// CHECK: [0x01,0x80,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, -1
+// CHECK: [0x01,0xc1,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b32 s1, s2
+// CHECK: [0x01,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 s103, s2
+// CHECK: [0x67,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 m0, s2
+// CHECK: [0x7c,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 0, s2
+// CHECK: [0x80,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 -1, s2
+// CHECK: [0xc1,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 0.5, s2
+// CHECK: [0xf0,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0d,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0d,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b32 s1, s103
+// CHECK: [0x01,0x67,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, m0
+// CHECK: [0x01,0x7c,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, 0
+// CHECK: [0x01,0x80,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, -1
+// CHECK: [0x01,0xc1,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b64 s[2:3], s2
+// CHECK: [0x02,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 s[4:5], s2
+// CHECK: [0x04,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 s[102:103], s2
+// CHECK: [0x66,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 flat_scratch, s2
+// CHECK: [0x68,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 vcc, s2
+// CHECK: [0x6a,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 tba, s2
+// CHECK: [0x6c,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 tma, s2
+// CHECK: [0x6e,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 exec, s2
+// CHECK: [0x7e,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 0, s2
+// CHECK: [0x80,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 -1, s2
+// CHECK: [0xc1,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 0.5, s2
+// CHECK: [0xf0,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 -4.0, s2
+// CHECK: [0xf7,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 src_execz, s2
+// CHECK: [0xfc,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 src_scc, s2
+// CHECK: [0xfd,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0e,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b64 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0e,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b64 s[2:3], s103
+// CHECK: [0x02,0x67,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x68,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x69,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], m0
+// CHECK: [0x02,0x7c,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], 0
+// CHECK: [0x02,0x80,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b64 s[2:3], s2
+// CHECK: [0x02,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 s[4:5], s2
+// CHECK: [0x04,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 s[102:103], s2
+// CHECK: [0x66,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 flat_scratch, s2
+// CHECK: [0x68,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 vcc, s2
+// CHECK: [0x6a,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 tba, s2
+// CHECK: [0x6c,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 tma, s2
+// CHECK: [0x6e,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 exec, s2
+// CHECK: [0x7e,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 0, s2
+// CHECK: [0x80,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 -1, s2
+// CHECK: [0xc1,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 0.5, s2
+// CHECK: [0xf0,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 -4.0, s2
+// CHECK: [0xf7,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 src_execz, s2
+// CHECK: [0xfc,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 src_scc, s2
+// CHECK: [0xfd,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0f,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b64 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0f,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b64 s[2:3], s103
+// CHECK: [0x02,0x67,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x68,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x69,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], m0
+// CHECK: [0x02,0x7c,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], 0
+// CHECK: [0x02,0x80,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f]
+
+s_setvskip s1, s2
+// CHECK: [0x01,0x02,0x10,0xbf]
+
+s_setvskip s103, s2
+// CHECK: [0x67,0x02,0x10,0xbf]
+
+s_setvskip flat_scratch_lo, s2
+// CHECK: [0x68,0x02,0x10,0xbf]
+
+s_setvskip flat_scratch_hi, s2
+// CHECK: [0x69,0x02,0x10,0xbf]
+
+s_setvskip vcc_lo, s2
+// CHECK: [0x6a,0x02,0x10,0xbf]
+
+s_setvskip vcc_hi, s2
+// CHECK: [0x6b,0x02,0x10,0xbf]
+
+s_setvskip tba_lo, s2
+// CHECK: [0x6c,0x02,0x10,0xbf]
+
+s_setvskip tba_hi, s2
+// CHECK: [0x6d,0x02,0x10,0xbf]
+
+s_setvskip tma_lo, s2
+// CHECK: [0x6e,0x02,0x10,0xbf]
+
+s_setvskip tma_hi, s2
+// CHECK: [0x6f,0x02,0x10,0xbf]
+
+s_setvskip ttmp11, s2
+// CHECK: [0x7b,0x02,0x10,0xbf]
+
+s_setvskip m0, s2
+// CHECK: [0x7c,0x02,0x10,0xbf]
+
+s_setvskip exec_lo, s2
+// CHECK: [0x7e,0x02,0x10,0xbf]
+
+s_setvskip exec_hi, s2
+// CHECK: [0x7f,0x02,0x10,0xbf]
+
+s_setvskip 0, s2
+// CHECK: [0x80,0x02,0x10,0xbf]
+
+s_setvskip -1, s2
+// CHECK: [0xc1,0x02,0x10,0xbf]
+
+s_setvskip 0.5, s2
+// CHECK: [0xf0,0x02,0x10,0xbf]
+
+s_setvskip -4.0, s2
+// CHECK: [0xf7,0x02,0x10,0xbf]
+
+s_setvskip src_vccz, s2
+// CHECK: [0xfb,0x02,0x10,0xbf]
+
+s_setvskip src_execz, s2
+// CHECK: [0xfc,0x02,0x10,0xbf]
+
+s_setvskip src_scc, s2
+// CHECK: [0xfd,0x02,0x10,0xbf]
+
+s_setvskip 0xaf123456, s2
+// CHECK: [0xff,0x02,0x10,0xbf,0x56,0x34,0x12,0xaf]
+
+s_setvskip 0x3f717273, s2
+// CHECK: [0xff,0x02,0x10,0xbf,0x73,0x72,0x71,0x3f]
+
+s_setvskip s1, s103
+// CHECK: [0x01,0x67,0x10,0xbf]
+
+s_setvskip s1, flat_scratch_lo
+// CHECK: [0x01,0x68,0x10,0xbf]
+
+s_setvskip s1, flat_scratch_hi
+// CHECK: [0x01,0x69,0x10,0xbf]
+
+s_setvskip s1, vcc_lo
+// CHECK: [0x01,0x6a,0x10,0xbf]
+
+s_setvskip s1, vcc_hi
+// CHECK: [0x01,0x6b,0x10,0xbf]
+
+s_setvskip s1, tba_lo
+// CHECK: [0x01,0x6c,0x10,0xbf]
+
+s_setvskip s1, tba_hi
+// CHECK: [0x01,0x6d,0x10,0xbf]
+
+s_setvskip s1, tma_lo
+// CHECK: [0x01,0x6e,0x10,0xbf]
+
+s_setvskip s1, tma_hi
+// CHECK: [0x01,0x6f,0x10,0xbf]
+
+s_setvskip s1, ttmp11
+// CHECK: [0x01,0x7b,0x10,0xbf]
+
+s_setvskip s1, m0
+// CHECK: [0x01,0x7c,0x10,0xbf]
+
+s_setvskip s1, exec_lo
+// CHECK: [0x01,0x7e,0x10,0xbf]
+
+s_setvskip s1, exec_hi
+// CHECK: [0x01,0x7f,0x10,0xbf]
+
+s_setvskip s1, 0
+// CHECK: [0x01,0x80,0x10,0xbf]
+
+s_setvskip s1, -1
+// CHECK: [0x01,0xc1,0x10,0xbf]
+
+s_setvskip s1, 0.5
+// CHECK: [0x01,0xf0,0x10,0xbf]
+
+s_setvskip s1, -4.0
+// CHECK: [0x01,0xf7,0x10,0xbf]
+
+s_setvskip s1, src_vccz
+// CHECK: [0x01,0xfb,0x10,0xbf]
+
+s_setvskip s1, src_execz
+// CHECK: [0x01,0xfc,0x10,0xbf]
+
+s_setvskip s1, src_scc
+// CHECK: [0x01,0xfd,0x10,0xbf]
+
+s_setvskip s1, 0xaf123456
+// CHECK: [0x01,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf]
+
+s_setvskip s1, 0x3f717273
+// CHECK: [0x01,0xff,0x10,0xbf,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx7_asm_sopk.s
new file mode 100644
index 0000000000000..c3283dec6ba6b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sopk.s
@@ -0,0 +1,850 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+s_movk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x05,0xb0]
+
+s_movk_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb0]
+
+s_movk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb0]
+
+s_movk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb0]
+
+s_movk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb0]
+
+s_movk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb0]
+
+s_movk_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb0]
+
+s_movk_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb0]
+
+s_movk_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb0]
+
+s_movk_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb0]
+
+s_movk_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb0]
+
+s_movk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb0]
+
+s_movk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb0]
+
+s_movk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb0]
+
+s_movk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x05,0xb0]
+
+s_cmovk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x05,0xb1]
+
+s_cmovk_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb1]
+
+s_cmovk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb1]
+
+s_cmovk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb1]
+
+s_cmovk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb1]
+
+s_cmovk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb1]
+
+s_cmovk_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb1]
+
+s_cmovk_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb1]
+
+s_cmovk_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb1]
+
+s_cmovk_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb1]
+
+s_cmovk_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb1]
+
+s_cmovk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb1]
+
+s_cmovk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb1]
+
+s_cmovk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb1]
+
+s_cmovk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x05,0xb1]
+
+s_cmpk_eq_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb1]
+
+s_cmpk_eq_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb1]
+
+s_cmpk_eq_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe8,0xb1]
+
+s_cmpk_eq_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe9,0xb1]
+
+s_cmpk_eq_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb1]
+
+s_cmpk_eq_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb1]
+
+s_cmpk_eq_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb1]
+
+s_cmpk_eq_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb1]
+
+s_cmpk_eq_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb1]
+
+s_cmpk_eq_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb1]
+
+s_cmpk_eq_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb1]
+
+s_cmpk_eq_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb1]
+
+s_cmpk_eq_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb1]
+
+s_cmpk_eq_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb1]
+
+s_cmpk_eq_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb1]
+
+s_cmpk_lg_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb2]
+
+s_cmpk_lg_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb2]
+
+s_cmpk_lg_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb2]
+
+s_cmpk_lg_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb2]
+
+s_cmpk_lg_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb2]
+
+s_cmpk_lg_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb2]
+
+s_cmpk_lg_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb2]
+
+s_cmpk_lg_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb2]
+
+s_cmpk_lg_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb2]
+
+s_cmpk_lg_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb2]
+
+s_cmpk_lg_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb2]
+
+s_cmpk_lg_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb2]
+
+s_cmpk_lg_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb2]
+
+s_cmpk_lg_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb2]
+
+s_cmpk_lg_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb2]
+
+s_cmpk_gt_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb2]
+
+s_cmpk_gt_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb2]
+
+s_cmpk_gt_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe8,0xb2]
+
+s_cmpk_gt_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe9,0xb2]
+
+s_cmpk_gt_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb2]
+
+s_cmpk_gt_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb2]
+
+s_cmpk_gt_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb2]
+
+s_cmpk_gt_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb2]
+
+s_cmpk_gt_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb2]
+
+s_cmpk_gt_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb2]
+
+s_cmpk_gt_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb2]
+
+s_cmpk_gt_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb2]
+
+s_cmpk_gt_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb2]
+
+s_cmpk_gt_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb2]
+
+s_cmpk_gt_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb2]
+
+s_cmpk_ge_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb3]
+
+s_cmpk_ge_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb3]
+
+s_cmpk_ge_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb3]
+
+s_cmpk_ge_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb3]
+
+s_cmpk_ge_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb3]
+
+s_cmpk_ge_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb3]
+
+s_cmpk_ge_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb3]
+
+s_cmpk_ge_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb3]
+
+s_cmpk_ge_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb3]
+
+s_cmpk_ge_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb3]
+
+s_cmpk_ge_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb3]
+
+s_cmpk_ge_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb3]
+
+s_cmpk_ge_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb3]
+
+s_cmpk_ge_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb3]
+
+s_cmpk_ge_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb3]
+
+s_cmpk_lt_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb3]
+
+s_cmpk_lt_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb3]
+
+s_cmpk_lt_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe8,0xb3]
+
+s_cmpk_lt_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe9,0xb3]
+
+s_cmpk_lt_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb3]
+
+s_cmpk_lt_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb3]
+
+s_cmpk_lt_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb3]
+
+s_cmpk_lt_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb3]
+
+s_cmpk_lt_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb3]
+
+s_cmpk_lt_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb3]
+
+s_cmpk_lt_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb3]
+
+s_cmpk_lt_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb3]
+
+s_cmpk_lt_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb3]
+
+s_cmpk_lt_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb3]
+
+s_cmpk_lt_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb3]
+
+s_cmpk_le_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb4]
+
+s_cmpk_le_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb4]
+
+s_cmpk_le_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb4]
+
+s_cmpk_le_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb4]
+
+s_cmpk_le_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb4]
+
+s_cmpk_le_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb4]
+
+s_cmpk_le_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb4]
+
+s_cmpk_le_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb4]
+
+s_cmpk_le_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb4]
+
+s_cmpk_le_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb4]
+
+s_cmpk_le_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb4]
+
+s_cmpk_le_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb4]
+
+s_cmpk_le_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb4]
+
+s_cmpk_le_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb4]
+
+s_cmpk_le_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb4]
+
+s_cmpk_eq_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb4]
+
+s_cmpk_eq_u32 s103, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb4]
+
+s_cmpk_eq_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe8,0xb4]
+
+s_cmpk_eq_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe9,0xb4]
+
+s_cmpk_eq_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb4]
+
+s_cmpk_eq_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb4]
+
+s_cmpk_eq_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb4]
+
+s_cmpk_eq_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb4]
+
+s_cmpk_eq_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb4]
+
+s_cmpk_eq_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb4]
+
+s_cmpk_eq_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb4]
+
+s_cmpk_eq_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb4]
+
+s_cmpk_eq_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb4]
+
+s_cmpk_eq_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb4]
+
+s_cmpk_eq_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb4]
+
+s_cmpk_lg_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb5]
+
+s_cmpk_lg_u32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb5]
+
+s_cmpk_lg_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb5]
+
+s_cmpk_lg_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb5]
+
+s_cmpk_lg_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb5]
+
+s_cmpk_lg_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb5]
+
+s_cmpk_lg_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb5]
+
+s_cmpk_lg_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb5]
+
+s_cmpk_lg_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb5]
+
+s_cmpk_lg_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb5]
+
+s_cmpk_lg_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb5]
+
+s_cmpk_lg_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb5]
+
+s_cmpk_lg_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb5]
+
+s_cmpk_lg_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb5]
+
+s_cmpk_lg_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb5]
+
+s_cmpk_gt_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb5]
+
+s_cmpk_gt_u32 s103, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb5]
+
+s_cmpk_gt_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe8,0xb5]
+
+s_cmpk_gt_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe9,0xb5]
+
+s_cmpk_gt_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb5]
+
+s_cmpk_gt_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb5]
+
+s_cmpk_gt_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb5]
+
+s_cmpk_gt_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb5]
+
+s_cmpk_gt_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb5]
+
+s_cmpk_gt_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb5]
+
+s_cmpk_gt_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb5]
+
+s_cmpk_gt_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb5]
+
+s_cmpk_gt_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb5]
+
+s_cmpk_gt_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb5]
+
+s_cmpk_gt_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb5]
+
+s_cmpk_ge_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb6]
+
+s_cmpk_ge_u32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb6]
+
+s_cmpk_ge_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb6]
+
+s_cmpk_ge_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb6]
+
+s_cmpk_ge_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb6]
+
+s_cmpk_ge_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb6]
+
+s_cmpk_ge_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb6]
+
+s_cmpk_ge_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb6]
+
+s_cmpk_ge_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb6]
+
+s_cmpk_ge_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb6]
+
+s_cmpk_ge_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb6]
+
+s_cmpk_ge_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb6]
+
+s_cmpk_ge_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb6]
+
+s_cmpk_ge_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb6]
+
+s_cmpk_ge_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb6]
+
+s_cmpk_lt_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb6]
+
+s_cmpk_lt_u32 s103, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb6]
+
+s_cmpk_lt_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe8,0xb6]
+
+s_cmpk_lt_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe9,0xb6]
+
+s_cmpk_lt_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb6]
+
+s_cmpk_lt_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb6]
+
+s_cmpk_lt_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb6]
+
+s_cmpk_lt_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb6]
+
+s_cmpk_lt_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb6]
+
+s_cmpk_lt_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb6]
+
+s_cmpk_lt_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb6]
+
+s_cmpk_lt_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb6]
+
+s_cmpk_lt_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb6]
+
+s_cmpk_lt_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb6]
+
+s_cmpk_lt_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb6]
+
+s_cmpk_le_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb7]
+
+s_cmpk_le_u32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb7]
+
+s_cmpk_le_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb7]
+
+s_cmpk_le_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb7]
+
+s_cmpk_le_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb7]
+
+s_cmpk_le_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb7]
+
+s_cmpk_le_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb7]
+
+s_cmpk_le_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb7]
+
+s_cmpk_le_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb7]
+
+s_cmpk_le_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb7]
+
+s_cmpk_le_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb7]
+
+s_cmpk_le_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb7]
+
+s_cmpk_le_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb7]
+
+s_cmpk_le_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb7]
+
+s_cmpk_le_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb7]
+
+s_addk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x85,0xb7]
+
+s_addk_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb7]
+
+s_addk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe8,0xb7]
+
+s_addk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe9,0xb7]
+
+s_addk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb7]
+
+s_addk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb7]
+
+s_addk_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb7]
+
+s_addk_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb7]
+
+s_addk_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb7]
+
+s_addk_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb7]
+
+s_addk_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb7]
+
+s_addk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb7]
+
+s_addk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb7]
+
+s_addk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb7]
+
+s_addk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x85,0xb7]
+
+s_mulk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x05,0xb8]
+
+s_mulk_i32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb8]
+
+s_mulk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb8]
+
+s_mulk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb8]
+
+s_mulk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb8]
+
+s_mulk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb8]
+
+s_mulk_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb8]
+
+s_mulk_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb8]
+
+s_mulk_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb8]
+
+s_mulk_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb8]
+
+s_mulk_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb8]
+
+s_mulk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb8]
+
+s_mulk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb8]
+
+s_mulk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb8]
+
+s_mulk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x05,0xb8]
+
+s_cbranch_i_fork s[2:3], 12609
+// CHECK: [0x41,0x31,0x82,0xb8]
+
+s_cbranch_i_fork s[4:5], 12609
+// CHECK: [0x41,0x31,0x84,0xb8]
+
+s_cbranch_i_fork s[102:103], 12609
+// CHECK: [0x41,0x31,0xe6,0xb8]
+
+s_cbranch_i_fork flat_scratch, 12609
+// CHECK: [0x41,0x31,0xe8,0xb8]
+
+s_cbranch_i_fork vcc, 12609
+// CHECK: [0x41,0x31,0xea,0xb8]
+
+s_cbranch_i_fork tba, 12609
+// CHECK: [0x41,0x31,0xec,0xb8]
+
+s_cbranch_i_fork tma, 12609
+// CHECK: [0x41,0x31,0xee,0xb8]
+
+s_cbranch_i_fork ttmp[10:11], 12609
+// CHECK: [0x41,0x31,0xfa,0xb8]
+
+s_cbranch_i_fork exec, 12609
+// CHECK: [0x41,0x31,0xfe,0xb8]
+
+s_cbranch_i_fork s[2:3], 49617
+// CHECK: [0xd1,0xc1,0x82,0xb8]
+
+s_getreg_b32 s5, 0x3141
+// CHECK: [0x41,0x31,0x05,0xb9]
+
+s_getreg_b32 s103, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb9]
+
+s_getreg_b32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x68,0xb9]
+
+s_getreg_b32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x69,0xb9]
+
+s_getreg_b32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb9]
+
+s_getreg_b32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb9]
+
+s_getreg_b32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb9]
+
+s_getreg_b32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb9]
+
+s_getreg_b32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb9]
+
+s_getreg_b32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb9]
+
+s_getreg_b32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb9]
+
+s_getreg_b32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb9]
+
+s_getreg_b32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb9]
+
+s_getreg_b32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb9]
+
+s_getreg_b32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x05,0xb9]
+
+s_setreg_b32 0x3141, s1
+// CHECK: [0x41,0x31,0x81,0xb9]
+
+s_setreg_b32 0xc1d1, s1
+// CHECK: [0xd1,0xc1,0x81,0xb9]
+
+s_setreg_b32 0x3141, s103
+// CHECK: [0x41,0x31,0xe7,0xb9]
+
+s_setreg_b32 0x3141, flat_scratch_lo
+// CHECK: [0x41,0x31,0xe8,0xb9]
+
+s_setreg_b32 0x3141, flat_scratch_hi
+// CHECK: [0x41,0x31,0xe9,0xb9]
+
+s_setreg_b32 0x3141, vcc_lo
+// CHECK: [0x41,0x31,0xea,0xb9]
+
+s_setreg_b32 0x3141, vcc_hi
+// CHECK: [0x41,0x31,0xeb,0xb9]
+
+s_setreg_b32 0x3141, tba_lo
+// CHECK: [0x41,0x31,0xec,0xb9]
+
+s_setreg_b32 0x3141, tba_hi
+// CHECK: [0x41,0x31,0xed,0xb9]
+
+s_setreg_b32 0x3141, tma_lo
+// CHECK: [0x41,0x31,0xee,0xb9]
+
+s_setreg_b32 0x3141, tma_hi
+// CHECK: [0x41,0x31,0xef,0xb9]
+
+s_setreg_b32 0x3141, ttmp11
+// CHECK: [0x41,0x31,0xfb,0xb9]
+
+s_setreg_b32 0x3141, m0
+// CHECK: [0x41,0x31,0xfc,0xb9]
+
+s_setreg_b32 0x3141, exec_lo
+// CHECK: [0x41,0x31,0xfe,0xb9]
+
+s_setreg_b32 0x3141, exec_hi
+// CHECK: [0x41,0x31,0xff,0xb9]
+
+s_setreg_imm32_b32 0x3141, 0x11213141
+// CHECK: [0x41,0x31,0x80,0xba,0x41,0x31,0x21,0x11]
+
+s_setreg_imm32_b32 0xc1d1, 0x11213141
+// CHECK: [0xd1,0xc1,0x80,0xba,0x41,0x31,0x21,0x11]
+
+s_setreg_imm32_b32 0x3141, 0xa1b1c1d1
+// CHECK: [0x41,0x31,0x80,0xba,0xd1,0xc1,0xb1,0xa1]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx7_asm_sopp.s
new file mode 100644
index 0000000000000..7e66c0cfeadb3
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_sopp.s
@@ -0,0 +1,145 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+s_nop 0x3141
+// CHECK: [0x41,0x31,0x80,0xbf]
+
+s_nop 0xc1d1
+// CHECK: [0xd1,0xc1,0x80,0xbf]
+
+s_endpgm
+// CHECK: [0x00,0x00,0x81,0xbf]
+
+s_branch 12609
+// CHECK: [0x41,0x31,0x82,0xbf]
+
+s_branch 49617
+// CHECK: [0xd1,0xc1,0x82,0xbf]
+
+s_cbranch_scc0 12609
+// CHECK: [0x41,0x31,0x84,0xbf]
+
+s_cbranch_scc0 49617
+// CHECK: [0xd1,0xc1,0x84,0xbf]
+
+s_cbranch_scc1 12609
+// CHECK: [0x41,0x31,0x85,0xbf]
+
+s_cbranch_scc1 49617
+// CHECK: [0xd1,0xc1,0x85,0xbf]
+
+s_cbranch_vccz 12609
+// CHECK: [0x41,0x31,0x86,0xbf]
+
+s_cbranch_vccz 49617
+// CHECK: [0xd1,0xc1,0x86,0xbf]
+
+s_cbranch_vccnz 12609
+// CHECK: [0x41,0x31,0x87,0xbf]
+
+s_cbranch_vccnz 49617
+// CHECK: [0xd1,0xc1,0x87,0xbf]
+
+s_cbranch_execz 12609
+// CHECK: [0x41,0x31,0x88,0xbf]
+
+s_cbranch_execz 49617
+// CHECK: [0xd1,0xc1,0x88,0xbf]
+
+s_cbranch_execnz 12609
+// CHECK: [0x41,0x31,0x89,0xbf]
+
+s_cbranch_execnz 49617
+// CHECK: [0xd1,0xc1,0x89,0xbf]
+
+s_barrier
+// CHECK: [0x00,0x00,0x8a,0xbf]
+
+s_setkill 0x3141
+// CHECK: [0x41,0x31,0x8b,0xbf]
+
+s_setkill 0xc1d1
+// CHECK: [0xd1,0xc1,0x8b,0xbf]
+
+s_waitcnt 0x3141
+// CHECK: [0x41,0x31,0x8c,0xbf]
+
+s_waitcnt 0xc1d1
+// CHECK: [0xd1,0xc1,0x8c,0xbf]
+
+s_sethalt 0x3141
+// CHECK: [0x41,0x31,0x8d,0xbf]
+
+s_sethalt 0xc1d1
+// CHECK: [0xd1,0xc1,0x8d,0xbf]
+
+s_sleep 0x3141
+// CHECK: [0x41,0x31,0x8e,0xbf]
+
+s_sleep 0xc1d1
+// CHECK: [0xd1,0xc1,0x8e,0xbf]
+
+s_setprio 0x3141
+// CHECK: [0x41,0x31,0x8f,0xbf]
+
+s_setprio 0xc1d1
+// CHECK: [0xd1,0xc1,0x8f,0xbf]
+
+s_sendmsg 0x3141
+// CHECK: [0x41,0x31,0x90,0xbf]
+
+s_sendmsg 0xc1d1
+// CHECK: [0xd1,0xc1,0x90,0xbf]
+
+s_sendmsghalt 0x3141
+// CHECK: [0x41,0x31,0x91,0xbf]
+
+s_sendmsghalt 0xc1d1
+// CHECK: [0xd1,0xc1,0x91,0xbf]
+
+s_trap 0x3141
+// CHECK: [0x41,0x31,0x92,0xbf]
+
+s_trap 0xc1d1
+// CHECK: [0xd1,0xc1,0x92,0xbf]
+
+s_icache_inv
+// CHECK: [0x00,0x00,0x93,0xbf]
+
+s_incperflevel 0x3141
+// CHECK: [0x41,0x31,0x94,0xbf]
+
+s_incperflevel 0xc1d1
+// CHECK: [0xd1,0xc1,0x94,0xbf]
+
+s_decperflevel 0x3141
+// CHECK: [0x41,0x31,0x95,0xbf]
+
+s_decperflevel 0xc1d1
+// CHECK: [0xd1,0xc1,0x95,0xbf]
+
+s_ttracedata
+// CHECK: [0x00,0x00,0x96,0xbf]
+
+s_cbranch_cdbgsys 12609
+// CHECK: [0x41,0x31,0x97,0xbf]
+
+s_cbranch_cdbgsys 49617
+// CHECK: [0xd1,0xc1,0x97,0xbf]
+
+s_cbranch_cdbguser 12609
+// CHECK: [0x41,0x31,0x98,0xbf]
+
+s_cbranch_cdbguser 49617
+// CHECK: [0xd1,0xc1,0x98,0xbf]
+
+s_cbranch_cdbgsys_or_user 12609
+// CHECK: [0x41,0x31,0x99,0xbf]
+
+s_cbranch_cdbgsys_or_user 49617
+// CHECK: [0xd1,0xc1,0x99,0xbf]
+
+s_cbranch_cdbgsys_and_user 12609
+// CHECK: [0x41,0x31,0x9a,0xbf]
+
+s_cbranch_cdbgsys_and_user 49617
+// CHECK: [0xd1,0xc1,0x9a,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s b/llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s
new file mode 100644
index 0000000000000..4dfa9e05e6586
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vintrp.s
@@ -0,0 +1,85 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+v_interp_p1_f32 v5, v1, attr0.x
+// CHECK: [0x01,0x00,0x14,0xc8]
+
+v_interp_p1_f32 v255, v1, attr0.x
+// CHECK: [0x01,0x00,0xfc,0xcb]
+
+v_interp_p1_f32 v5, v255, attr0.x
+// CHECK: [0xff,0x00,0x14,0xc8]
+
+v_interp_p1_f32 v5, v1, attr1.x
+// CHECK: [0x01,0x04,0x14,0xc8]
+
+v_interp_p1_f32 v5, v1, attr31.x
+// CHECK: [0x01,0x7c,0x14,0xc8]
+
+v_interp_p1_f32 v5, v1, attr32.x
+// CHECK: [0x01,0x80,0x14,0xc8]
+
+v_interp_p1_f32 v5, v1, attr0.y
+// CHECK: [0x01,0x01,0x14,0xc8]
+
+v_interp_p1_f32 v5, v1, attr0.z
+// CHECK: [0x01,0x02,0x14,0xc8]
+
+v_interp_p1_f32 v5, v1, attr0.w
+// CHECK: [0x01,0x03,0x14,0xc8]
+
+v_interp_p2_f32 v5, v1, attr0.x
+// CHECK: [0x01,0x00,0x15,0xc8]
+
+v_interp_p2_f32 v255, v1, attr0.x
+// CHECK: [0x01,0x00,0xfd,0xcb]
+
+v_interp_p2_f32 v5, v255, attr0.x
+// CHECK: [0xff,0x00,0x15,0xc8]
+
+v_interp_p2_f32 v5, v1, attr1.x
+// CHECK: [0x01,0x04,0x15,0xc8]
+
+v_interp_p2_f32 v5, v1, attr31.x
+// CHECK: [0x01,0x7c,0x15,0xc8]
+
+v_interp_p2_f32 v5, v1, attr32.x
+// CHECK: [0x01,0x80,0x15,0xc8]
+
+v_interp_p2_f32 v5, v1, attr0.y
+// CHECK: [0x01,0x01,0x15,0xc8]
+
+v_interp_p2_f32 v5, v1, attr0.z
+// CHECK: [0x01,0x02,0x15,0xc8]
+
+v_interp_p2_f32 v5, v1, attr0.w
+// CHECK: [0x01,0x03,0x15,0xc8]
+
+v_interp_mov_f32 v5, p10, attr0.x
+// CHECK: [0x00,0x00,0x16,0xc8]
+
+v_interp_mov_f32 v255, p10, attr0.x
+// CHECK: [0x00,0x00,0xfe,0xcb]
+
+v_interp_mov_f32 v5, p20, attr0.x
+// CHECK: [0x01,0x00,0x16,0xc8]
+
+v_interp_mov_f32 v5, p0, attr0.x
+// CHECK: [0x02,0x00,0x16,0xc8]
+
+v_interp_mov_f32 v5, p10, attr1.x
+// CHECK: [0x00,0x04,0x16,0xc8]
+
+v_interp_mov_f32 v5, p10, attr31.x
+// CHECK: [0x00,0x7c,0x16,0xc8]
+
+v_interp_mov_f32 v5, p10, attr32.x
+// CHECK: [0x00,0x80,0x16,0xc8]
+
+v_interp_mov_f32 v5, p10, attr0.y
+// CHECK: [0x00,0x01,0x16,0xc8]
+
+v_interp_mov_f32 v5, p10, attr0.z
+// CHECK: [0x00,0x02,0x16,0xc8]
+
+v_interp_mov_f32 v5, p10, attr0.w
+// CHECK: [0x00,0x03,0x16,0xc8]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx7_asm_vop1.s
new file mode 100644
index 0000000000000..d42bfb1c021ce
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vop1.s
@@ -0,0 +1,4576 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+v_nop
+// CHECK: [0x00,0x00,0x00,0x7e]
+
+v_mov_b32 v5, v1
+// CHECK: [0x01,0x03,0x0a,0x7e]
+
+v_mov_b32 v255, v1
+// CHECK: [0x01,0x03,0xfe,0x7f]
+
+v_mov_b32 v5, v255
+// CHECK: [0xff,0x03,0x0a,0x7e]
+
+v_mov_b32 v5, s1
+// CHECK: [0x01,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, s103
+// CHECK: [0x67,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, flat_scratch_lo
+// CHECK: [0x68,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, flat_scratch_hi
+// CHECK: [0x69,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, vcc_lo
+// CHECK: [0x6a,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, vcc_hi
+// CHECK: [0x6b,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, tba_lo
+// CHECK: [0x6c,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, tba_hi
+// CHECK: [0x6d,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, tma_lo
+// CHECK: [0x6e,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, tma_hi
+// CHECK: [0x6f,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, ttmp11
+// CHECK: [0x7b,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, m0
+// CHECK: [0x7c,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, exec_lo
+// CHECK: [0x7e,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, exec_hi
+// CHECK: [0x7f,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0
+// CHECK: [0x80,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, -1
+// CHECK: [0xc1,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0.5
+// CHECK: [0xf0,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, -4.0
+// CHECK: [0xf7,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_vccz
+// CHECK: [0xfb,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_execz
+// CHECK: [0xfc,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_scc
+// CHECK: [0xfd,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0xaf123456
+// CHECK: [0xff,0x02,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_mov_b32 v5, 0x3f717273
+// CHECK: [0xff,0x02,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_readfirstlane_b32 s5, v1
+// CHECK: [0x01,0x05,0x0a,0x7e]
+
+v_readfirstlane_b32 s103, v1
+// CHECK: [0x01,0x05,0xce,0x7e]
+
+v_readfirstlane_b32 tba_lo, v1
+// CHECK: [0x01,0x05,0xd8,0x7e]
+
+v_readfirstlane_b32 tba_hi, v1
+// CHECK: [0x01,0x05,0xda,0x7e]
+
+v_readfirstlane_b32 tma_lo, v1
+// CHECK: [0x01,0x05,0xdc,0x7e]
+
+v_readfirstlane_b32 tma_hi, v1
+// CHECK: [0x01,0x05,0xde,0x7e]
+
+v_readfirstlane_b32 ttmp11, v1
+// CHECK: [0x01,0x05,0xf6,0x7e]
+
+v_readfirstlane_b32 s5, v255
+// CHECK: [0xff,0x05,0x0a,0x7e]
+
+v_readfirstlane_b32 s5, src_lds_direct
+// CHECK: [0xfe,0x04,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, v[1:2]
+// CHECK: [0x01,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64 v255, v[1:2]
+// CHECK: [0x01,0x07,0xfe,0x7f]
+
+v_cvt_i32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[2:3]
+// CHECK: [0x02,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[4:5]
+// CHECK: [0x04,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[102:103]
+// CHECK: [0x66,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, flat_scratch
+// CHECK: [0x68,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, vcc
+// CHECK: [0x6a,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, tba
+// CHECK: [0x6c,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, tma
+// CHECK: [0x6e,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, ttmp[10:11]
+// CHECK: [0x7a,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, exec
+// CHECK: [0x7e,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0
+// CHECK: [0x80,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, -1
+// CHECK: [0xc1,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0.5
+// CHECK: [0xf0,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, -4.0
+// CHECK: [0xf7,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_vccz
+// CHECK: [0xfb,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_execz
+// CHECK: [0xfc,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_scc
+// CHECK: [0xfd,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x06,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x06,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_i32 v[5:6], v1
+// CHECK: [0x01,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32 v[254:255], v1
+// CHECK: [0x01,0x09,0xfc,0x7f]
+
+v_cvt_f64_i32 v[5:6], v255
+// CHECK: [0xff,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], s1
+// CHECK: [0x01,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], s103
+// CHECK: [0x67,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], flat_scratch_lo
+// CHECK: [0x68,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], flat_scratch_hi
+// CHECK: [0x69,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], vcc_lo
+// CHECK: [0x6a,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], vcc_hi
+// CHECK: [0x6b,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], tba_lo
+// CHECK: [0x6c,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], tba_hi
+// CHECK: [0x6d,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], tma_lo
+// CHECK: [0x6e,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], tma_hi
+// CHECK: [0x6f,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], ttmp11
+// CHECK: [0x7b,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], m0
+// CHECK: [0x7c,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], exec_lo
+// CHECK: [0x7e,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], exec_hi
+// CHECK: [0x7f,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0
+// CHECK: [0x80,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], -1
+// CHECK: [0xc1,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0.5
+// CHECK: [0xf0,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], -4.0
+// CHECK: [0xf7,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_vccz
+// CHECK: [0xfb,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_execz
+// CHECK: [0xfc,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_scc
+// CHECK: [0xfd,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_lds_direct
+// CHECK: [0xfe,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0xaf123456
+// CHECK: [0xff,0x08,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_i32 v[5:6], 0x3f717273
+// CHECK: [0xff,0x08,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_i32 v5, v1
+// CHECK: [0x01,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32 v255, v1
+// CHECK: [0x01,0x0b,0xfe,0x7f]
+
+v_cvt_f32_i32 v5, v255
+// CHECK: [0xff,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, s1
+// CHECK: [0x01,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, s103
+// CHECK: [0x67,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, flat_scratch_lo
+// CHECK: [0x68,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, flat_scratch_hi
+// CHECK: [0x69,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, vcc_lo
+// CHECK: [0x6a,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, vcc_hi
+// CHECK: [0x6b,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, tba_lo
+// CHECK: [0x6c,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, tba_hi
+// CHECK: [0x6d,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, tma_lo
+// CHECK: [0x6e,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, tma_hi
+// CHECK: [0x6f,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, ttmp11
+// CHECK: [0x7b,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, m0
+// CHECK: [0x7c,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, exec_lo
+// CHECK: [0x7e,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, exec_hi
+// CHECK: [0x7f,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0
+// CHECK: [0x80,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, -1
+// CHECK: [0xc1,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0.5
+// CHECK: [0xf0,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, -4.0
+// CHECK: [0xf7,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_vccz
+// CHECK: [0xfb,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_execz
+// CHECK: [0xfc,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_scc
+// CHECK: [0xfd,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_lds_direct
+// CHECK: [0xfe,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0xaf123456
+// CHECK: [0xff,0x0a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_i32 v5, 0x3f717273
+// CHECK: [0xff,0x0a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_u32 v5, v1
+// CHECK: [0x01,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32 v255, v1
+// CHECK: [0x01,0x0d,0xfe,0x7f]
+
+v_cvt_f32_u32 v5, v255
+// CHECK: [0xff,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, s1
+// CHECK: [0x01,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, s103
+// CHECK: [0x67,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, flat_scratch_lo
+// CHECK: [0x68,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, flat_scratch_hi
+// CHECK: [0x69,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, vcc_lo
+// CHECK: [0x6a,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, vcc_hi
+// CHECK: [0x6b,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, tba_lo
+// CHECK: [0x6c,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, tba_hi
+// CHECK: [0x6d,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, tma_lo
+// CHECK: [0x6e,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, tma_hi
+// CHECK: [0x6f,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, ttmp11
+// CHECK: [0x7b,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, m0
+// CHECK: [0x7c,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, exec_lo
+// CHECK: [0x7e,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, exec_hi
+// CHECK: [0x7f,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0
+// CHECK: [0x80,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, -1
+// CHECK: [0xc1,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0.5
+// CHECK: [0xf0,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, -4.0
+// CHECK: [0xf7,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_vccz
+// CHECK: [0xfb,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_execz
+// CHECK: [0xfc,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_scc
+// CHECK: [0xfd,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_lds_direct
+// CHECK: [0xfe,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0xaf123456
+// CHECK: [0xff,0x0c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_u32 v5, 0x3f717273
+// CHECK: [0xff,0x0c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_u32_f32 v5, v1
+// CHECK: [0x01,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32 v255, v1
+// CHECK: [0x01,0x0f,0xfe,0x7f]
+
+v_cvt_u32_f32 v5, v255
+// CHECK: [0xff,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, s1
+// CHECK: [0x01,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, s103
+// CHECK: [0x67,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, tba_lo
+// CHECK: [0x6c,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, tba_hi
+// CHECK: [0x6d,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, tma_lo
+// CHECK: [0x6e,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, tma_hi
+// CHECK: [0x6f,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, ttmp11
+// CHECK: [0x7b,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, m0
+// CHECK: [0x7c,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, exec_lo
+// CHECK: [0x7e,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, exec_hi
+// CHECK: [0x7f,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0
+// CHECK: [0x80,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, -1
+// CHECK: [0xc1,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0.5
+// CHECK: [0xf0,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, -4.0
+// CHECK: [0xf7,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_vccz
+// CHECK: [0xfb,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_execz
+// CHECK: [0xfc,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_scc
+// CHECK: [0xfd,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x0e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x0e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_i32_f32 v5, v1
+// CHECK: [0x01,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32 v255, v1
+// CHECK: [0x01,0x11,0xfe,0x7f]
+
+v_cvt_i32_f32 v5, v255
+// CHECK: [0xff,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, s1
+// CHECK: [0x01,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, s103
+// CHECK: [0x67,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, tba_lo
+// CHECK: [0x6c,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, tba_hi
+// CHECK: [0x6d,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, tma_lo
+// CHECK: [0x6e,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, tma_hi
+// CHECK: [0x6f,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, ttmp11
+// CHECK: [0x7b,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, m0
+// CHECK: [0x7c,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0
+// CHECK: [0x80,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, -1
+// CHECK: [0xc1,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x10,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x10,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f16_f32 v5, v1
+// CHECK: [0x01,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v255, v1
+// CHECK: [0x01,0x15,0xfe,0x7f]
+
+v_cvt_f16_f32 v5, v255
+// CHECK: [0xff,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s1
+// CHECK: [0x01,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s103
+// CHECK: [0x67,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_lo
+// CHECK: [0x6a,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_hi
+// CHECK: [0x6b,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, tba_lo
+// CHECK: [0x6c,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, tba_hi
+// CHECK: [0x6d,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, tma_lo
+// CHECK: [0x6e,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, tma_hi
+// CHECK: [0x6f,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, ttmp11
+// CHECK: [0x7b,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, m0
+// CHECK: [0x7c,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_lo
+// CHECK: [0x7e,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_hi
+// CHECK: [0x7f,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0
+// CHECK: [0x80,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, -1
+// CHECK: [0xc1,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0.5
+// CHECK: [0xf0,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, -4.0
+// CHECK: [0xf7,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_vccz
+// CHECK: [0xfb,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_execz
+// CHECK: [0xfc,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_scc
+// CHECK: [0xfd,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0xaf123456
+// CHECK: [0xff,0x14,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f16_f32 v5, 0x3f717273
+// CHECK: [0xff,0x14,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_f16 v5, v1
+// CHECK: [0x01,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v255, v1
+// CHECK: [0x01,0x17,0xfe,0x7f]
+
+v_cvt_f32_f16 v5, v255
+// CHECK: [0xff,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s1
+// CHECK: [0x01,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s103
+// CHECK: [0x67,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, flat_scratch_lo
+// CHECK: [0x68,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, flat_scratch_hi
+// CHECK: [0x69,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_lo
+// CHECK: [0x6a,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_hi
+// CHECK: [0x6b,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, tba_lo
+// CHECK: [0x6c,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, tba_hi
+// CHECK: [0x6d,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, tma_lo
+// CHECK: [0x6e,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, tma_hi
+// CHECK: [0x6f,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, ttmp11
+// CHECK: [0x7b,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, m0
+// CHECK: [0x7c,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_lo
+// CHECK: [0x7e,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_hi
+// CHECK: [0x7f,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, 0
+// CHECK: [0x80,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, -1
+// CHECK: [0xc1,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_vccz
+// CHECK: [0xfb,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_execz
+// CHECK: [0xfc,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_scc
+// CHECK: [0xfd,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x16,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, v1
+// CHECK: [0x01,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v255, v1
+// CHECK: [0x01,0x19,0xfe,0x7f]
+
+v_cvt_rpi_i32_f32 v5, v255
+// CHECK: [0xff,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s1
+// CHECK: [0x01,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s103
+// CHECK: [0x67,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, tba_lo
+// CHECK: [0x6c,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, tba_hi
+// CHECK: [0x6d,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, tma_lo
+// CHECK: [0x6e,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, tma_hi
+// CHECK: [0x6f,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, ttmp11
+// CHECK: [0x7b,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, m0
+// CHECK: [0x7c,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0
+// CHECK: [0x80,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, -1
+// CHECK: [0xc1,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x18,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_rpi_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x18,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_flr_i32_f32 v5, v1
+// CHECK: [0x01,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v255, v1
+// CHECK: [0x01,0x1b,0xfe,0x7f]
+
+v_cvt_flr_i32_f32 v5, v255
+// CHECK: [0xff,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s1
+// CHECK: [0x01,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s103
+// CHECK: [0x67,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, tba_lo
+// CHECK: [0x6c,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, tba_hi
+// CHECK: [0x6d,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, tma_lo
+// CHECK: [0x6e,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, tma_hi
+// CHECK: [0x6f,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, ttmp11
+// CHECK: [0x7b,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, m0
+// CHECK: [0x7c,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0
+// CHECK: [0x80,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, -1
+// CHECK: [0xc1,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x1a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_flr_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x1a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_off_f32_i4 v5, v1
+// CHECK: [0x01,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v255, v1
+// CHECK: [0x01,0x1d,0xfe,0x7f]
+
+v_cvt_off_f32_i4 v5, v255
+// CHECK: [0xff,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s1
+// CHECK: [0x01,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s103
+// CHECK: [0x67,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, flat_scratch_lo
+// CHECK: [0x68,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, flat_scratch_hi
+// CHECK: [0x69,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_lo
+// CHECK: [0x6a,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_hi
+// CHECK: [0x6b,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, tba_lo
+// CHECK: [0x6c,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, tba_hi
+// CHECK: [0x6d,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, tma_lo
+// CHECK: [0x6e,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, tma_hi
+// CHECK: [0x6f,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, ttmp11
+// CHECK: [0x7b,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, m0
+// CHECK: [0x7c,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_lo
+// CHECK: [0x7e,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_hi
+// CHECK: [0x7f,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0
+// CHECK: [0x80,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, -1
+// CHECK: [0xc1,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0.5
+// CHECK: [0xf0,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, -4.0
+// CHECK: [0xf7,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_vccz
+// CHECK: [0xfb,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_execz
+// CHECK: [0xfc,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_scc
+// CHECK: [0xfd,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_lds_direct
+// CHECK: [0xfe,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0x4f
+// CHECK: [0xff,0x1c,0x0a,0x7e,0x4f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4 v5, 0x41
+// CHECK: [0xff,0x1c,0x0a,0x7e,0x41,0x00,0x00,0x00]
+
+v_cvt_f32_f64 v5, v[1:2]
+// CHECK: [0x01,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v255, v[1:2]
+// CHECK: [0x01,0x1f,0xfe,0x7f]
+
+v_cvt_f32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[2:3]
+// CHECK: [0x02,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[4:5]
+// CHECK: [0x04,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[102:103]
+// CHECK: [0x66,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, flat_scratch
+// CHECK: [0x68,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, vcc
+// CHECK: [0x6a,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, tba
+// CHECK: [0x6c,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, tma
+// CHECK: [0x6e,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, ttmp[10:11]
+// CHECK: [0x7a,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, exec
+// CHECK: [0x7e,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0
+// CHECK: [0x80,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, -1
+// CHECK: [0xc1,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0.5
+// CHECK: [0xf0,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, -4.0
+// CHECK: [0xf7,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_vccz
+// CHECK: [0xfb,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_execz
+// CHECK: [0xfc,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_scc
+// CHECK: [0xfd,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x1e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x1e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_f32 v[5:6], v1
+// CHECK: [0x01,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[254:255], v1
+// CHECK: [0x01,0x21,0xfc,0x7f]
+
+v_cvt_f64_f32 v[5:6], v255
+// CHECK: [0xff,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s1
+// CHECK: [0x01,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s103
+// CHECK: [0x67,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], flat_scratch_lo
+// CHECK: [0x68,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], flat_scratch_hi
+// CHECK: [0x69,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_lo
+// CHECK: [0x6a,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_hi
+// CHECK: [0x6b,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], tba_lo
+// CHECK: [0x6c,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], tba_hi
+// CHECK: [0x6d,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], tma_lo
+// CHECK: [0x6e,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], tma_hi
+// CHECK: [0x6f,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], ttmp11
+// CHECK: [0x7b,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], m0
+// CHECK: [0x7c,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_lo
+// CHECK: [0x7e,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_hi
+// CHECK: [0x7f,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0
+// CHECK: [0x80,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], -1
+// CHECK: [0xc1,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0.5
+// CHECK: [0xf0,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], -4.0
+// CHECK: [0xf7,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_vccz
+// CHECK: [0xfb,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_execz
+// CHECK: [0xfc,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_scc
+// CHECK: [0xfd,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_lds_direct
+// CHECK: [0xfe,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0xaf123456
+// CHECK: [0xff,0x20,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_f32 v[5:6], 0x3f717273
+// CHECK: [0xff,0x20,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte0 v5, v1
+// CHECK: [0x01,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v255, v1
+// CHECK: [0x01,0x23,0xfe,0x7f]
+
+v_cvt_f32_ubyte0 v5, v255
+// CHECK: [0xff,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s1
+// CHECK: [0x01,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s103
+// CHECK: [0x67,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, flat_scratch_lo
+// CHECK: [0x68,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, flat_scratch_hi
+// CHECK: [0x69,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_lo
+// CHECK: [0x6a,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_hi
+// CHECK: [0x6b,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, tba_lo
+// CHECK: [0x6c,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, tba_hi
+// CHECK: [0x6d,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, tma_lo
+// CHECK: [0x6e,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, tma_hi
+// CHECK: [0x6f,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, ttmp11
+// CHECK: [0x7b,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, m0
+// CHECK: [0x7c,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_lo
+// CHECK: [0x7e,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_hi
+// CHECK: [0x7f,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0
+// CHECK: [0x80,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, -1
+// CHECK: [0xc1,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0.5
+// CHECK: [0xf0,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, -4.0
+// CHECK: [0xf7,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_vccz
+// CHECK: [0xfb,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_execz
+// CHECK: [0xfc,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_scc
+// CHECK: [0xfd,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_lds_direct
+// CHECK: [0xfe,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0xaf123456
+// CHECK: [0xff,0x22,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte0 v5, 0x3f717273
+// CHECK: [0xff,0x22,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte1 v5, v1
+// CHECK: [0x01,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v255, v1
+// CHECK: [0x01,0x25,0xfe,0x7f]
+
+v_cvt_f32_ubyte1 v5, v255
+// CHECK: [0xff,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s1
+// CHECK: [0x01,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s103
+// CHECK: [0x67,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, flat_scratch_lo
+// CHECK: [0x68,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, flat_scratch_hi
+// CHECK: [0x69,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_lo
+// CHECK: [0x6a,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_hi
+// CHECK: [0x6b,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, tba_lo
+// CHECK: [0x6c,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, tba_hi
+// CHECK: [0x6d,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, tma_lo
+// CHECK: [0x6e,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, tma_hi
+// CHECK: [0x6f,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, ttmp11
+// CHECK: [0x7b,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, m0
+// CHECK: [0x7c,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_lo
+// CHECK: [0x7e,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_hi
+// CHECK: [0x7f,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0
+// CHECK: [0x80,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, -1
+// CHECK: [0xc1,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0.5
+// CHECK: [0xf0,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, -4.0
+// CHECK: [0xf7,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_vccz
+// CHECK: [0xfb,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_execz
+// CHECK: [0xfc,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_scc
+// CHECK: [0xfd,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_lds_direct
+// CHECK: [0xfe,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0xaf123456
+// CHECK: [0xff,0x24,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte1 v5, 0x3f717273
+// CHECK: [0xff,0x24,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte2 v5, v1
+// CHECK: [0x01,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v255, v1
+// CHECK: [0x01,0x27,0xfe,0x7f]
+
+v_cvt_f32_ubyte2 v5, v255
+// CHECK: [0xff,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s1
+// CHECK: [0x01,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s103
+// CHECK: [0x67,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, flat_scratch_lo
+// CHECK: [0x68,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, flat_scratch_hi
+// CHECK: [0x69,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_lo
+// CHECK: [0x6a,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_hi
+// CHECK: [0x6b,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, tba_lo
+// CHECK: [0x6c,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, tba_hi
+// CHECK: [0x6d,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, tma_lo
+// CHECK: [0x6e,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, tma_hi
+// CHECK: [0x6f,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, ttmp11
+// CHECK: [0x7b,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, m0
+// CHECK: [0x7c,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_lo
+// CHECK: [0x7e,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_hi
+// CHECK: [0x7f,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0
+// CHECK: [0x80,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, -1
+// CHECK: [0xc1,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0.5
+// CHECK: [0xf0,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, -4.0
+// CHECK: [0xf7,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_vccz
+// CHECK: [0xfb,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_execz
+// CHECK: [0xfc,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_scc
+// CHECK: [0xfd,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_lds_direct
+// CHECK: [0xfe,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0xaf123456
+// CHECK: [0xff,0x26,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte2 v5, 0x3f717273
+// CHECK: [0xff,0x26,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte3 v5, v1
+// CHECK: [0x01,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v255, v1
+// CHECK: [0x01,0x29,0xfe,0x7f]
+
+v_cvt_f32_ubyte3 v5, v255
+// CHECK: [0xff,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s1
+// CHECK: [0x01,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s103
+// CHECK: [0x67,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, flat_scratch_lo
+// CHECK: [0x68,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, flat_scratch_hi
+// CHECK: [0x69,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_lo
+// CHECK: [0x6a,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_hi
+// CHECK: [0x6b,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, tba_lo
+// CHECK: [0x6c,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, tba_hi
+// CHECK: [0x6d,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, tma_lo
+// CHECK: [0x6e,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, tma_hi
+// CHECK: [0x6f,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, ttmp11
+// CHECK: [0x7b,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, m0
+// CHECK: [0x7c,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_lo
+// CHECK: [0x7e,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_hi
+// CHECK: [0x7f,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0
+// CHECK: [0x80,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, -1
+// CHECK: [0xc1,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0.5
+// CHECK: [0xf0,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, -4.0
+// CHECK: [0xf7,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_vccz
+// CHECK: [0xfb,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_execz
+// CHECK: [0xfc,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_scc
+// CHECK: [0xfd,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_lds_direct
+// CHECK: [0xfe,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0xaf123456
+// CHECK: [0xff,0x28,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte3 v5, 0x3f717273
+// CHECK: [0xff,0x28,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_u32_f64 v5, v[1:2]
+// CHECK: [0x01,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v255, v[1:2]
+// CHECK: [0x01,0x2b,0xfe,0x7f]
+
+v_cvt_u32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[2:3]
+// CHECK: [0x02,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[4:5]
+// CHECK: [0x04,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[102:103]
+// CHECK: [0x66,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, flat_scratch
+// CHECK: [0x68,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, vcc
+// CHECK: [0x6a,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, tba
+// CHECK: [0x6c,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, tma
+// CHECK: [0x6e,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, ttmp[10:11]
+// CHECK: [0x7a,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, exec
+// CHECK: [0x7e,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0
+// CHECK: [0x80,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, -1
+// CHECK: [0xc1,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0.5
+// CHECK: [0xf0,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, -4.0
+// CHECK: [0xf7,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_vccz
+// CHECK: [0xfb,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_execz
+// CHECK: [0xfc,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_scc
+// CHECK: [0xfd,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x2a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x2a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_u32 v[5:6], v1
+// CHECK: [0x01,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[254:255], v1
+// CHECK: [0x01,0x2d,0xfc,0x7f]
+
+v_cvt_f64_u32 v[5:6], v255
+// CHECK: [0xff,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s1
+// CHECK: [0x01,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s103
+// CHECK: [0x67,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], flat_scratch_lo
+// CHECK: [0x68,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], flat_scratch_hi
+// CHECK: [0x69,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_lo
+// CHECK: [0x6a,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_hi
+// CHECK: [0x6b,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], tba_lo
+// CHECK: [0x6c,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], tba_hi
+// CHECK: [0x6d,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], tma_lo
+// CHECK: [0x6e,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], tma_hi
+// CHECK: [0x6f,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], ttmp11
+// CHECK: [0x7b,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], m0
+// CHECK: [0x7c,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_lo
+// CHECK: [0x7e,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_hi
+// CHECK: [0x7f,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0
+// CHECK: [0x80,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], -1
+// CHECK: [0xc1,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0.5
+// CHECK: [0xf0,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], -4.0
+// CHECK: [0xf7,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_vccz
+// CHECK: [0xfb,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_execz
+// CHECK: [0xfc,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_scc
+// CHECK: [0xfd,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_lds_direct
+// CHECK: [0xfe,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0xaf123456
+// CHECK: [0xff,0x2c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_u32 v[5:6], 0x3f717273
+// CHECK: [0xff,0x2c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_trunc_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x2f,0xfc,0x7f]
+
+v_trunc_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], vcc
+// CHECK: [0x6a,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], tba
+// CHECK: [0x6c,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], tma
+// CHECK: [0x6e,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], exec
+// CHECK: [0x7e,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0
+// CHECK: [0x80,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], -1
+// CHECK: [0xc1,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x2e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_trunc_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x2e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ceil_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x31,0xfc,0x7f]
+
+v_ceil_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], vcc
+// CHECK: [0x6a,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], tba
+// CHECK: [0x6c,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], tma
+// CHECK: [0x6e,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], exec
+// CHECK: [0x7e,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0
+// CHECK: [0x80,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], -1
+// CHECK: [0xc1,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x30,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ceil_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x30,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rndne_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x33,0xfc,0x7f]
+
+v_rndne_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], vcc
+// CHECK: [0x6a,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], tba
+// CHECK: [0x6c,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], tma
+// CHECK: [0x6e,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], exec
+// CHECK: [0x7e,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0
+// CHECK: [0x80,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], -1
+// CHECK: [0xc1,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x32,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rndne_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x32,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_floor_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x35,0x0a,0x7e]
+
+v_floor_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x35,0xfc,0x7f]
+
+v_floor_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x35,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], vcc
+// CHECK: [0x6a,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], tba
+// CHECK: [0x6c,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], tma
+// CHECK: [0x6e,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], exec
+// CHECK: [0x7e,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0
+// CHECK: [0x80,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], -1
+// CHECK: [0xc1,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x34,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_floor_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x34,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_fract_f32 v5, v1
+// CHECK: [0x01,0x41,0x0a,0x7e]
+
+v_fract_f32 v255, v1
+// CHECK: [0x01,0x41,0xfe,0x7f]
+
+v_fract_f32 v5, v255
+// CHECK: [0xff,0x41,0x0a,0x7e]
+
+v_fract_f32 v5, s1
+// CHECK: [0x01,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, s103
+// CHECK: [0x67,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_lo
+// CHECK: [0x6a,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_hi
+// CHECK: [0x6b,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, tba_lo
+// CHECK: [0x6c,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, tba_hi
+// CHECK: [0x6d,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, tma_lo
+// CHECK: [0x6e,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, tma_hi
+// CHECK: [0x6f,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, ttmp11
+// CHECK: [0x7b,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, m0
+// CHECK: [0x7c,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, exec_lo
+// CHECK: [0x7e,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, exec_hi
+// CHECK: [0x7f,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, 0
+// CHECK: [0x80,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, -1
+// CHECK: [0xc1,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, 0.5
+// CHECK: [0xf0,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, -4.0
+// CHECK: [0xf7,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, src_vccz
+// CHECK: [0xfb,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, src_execz
+// CHECK: [0xfc,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, src_scc
+// CHECK: [0xfd,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x40,0x0a,0x7e]
+
+v_fract_f32 v5, 0xaf123456
+// CHECK: [0xff,0x40,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_fract_f32 v5, 0x3f717273
+// CHECK: [0xff,0x40,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_trunc_f32 v5, v1
+// CHECK: [0x01,0x43,0x0a,0x7e]
+
+v_trunc_f32 v255, v1
+// CHECK: [0x01,0x43,0xfe,0x7f]
+
+v_trunc_f32 v5, v255
+// CHECK: [0xff,0x43,0x0a,0x7e]
+
+v_trunc_f32 v5, s1
+// CHECK: [0x01,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, s103
+// CHECK: [0x67,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_lo
+// CHECK: [0x6a,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_hi
+// CHECK: [0x6b,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, tba_lo
+// CHECK: [0x6c,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, tba_hi
+// CHECK: [0x6d,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, tma_lo
+// CHECK: [0x6e,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, tma_hi
+// CHECK: [0x6f,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, ttmp11
+// CHECK: [0x7b,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, m0
+// CHECK: [0x7c,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_lo
+// CHECK: [0x7e,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_hi
+// CHECK: [0x7f,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, 0
+// CHECK: [0x80,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, -1
+// CHECK: [0xc1,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, 0.5
+// CHECK: [0xf0,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, -4.0
+// CHECK: [0xf7,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, src_vccz
+// CHECK: [0xfb,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, src_execz
+// CHECK: [0xfc,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, src_scc
+// CHECK: [0xfd,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x42,0x0a,0x7e]
+
+v_trunc_f32 v5, 0xaf123456
+// CHECK: [0xff,0x42,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_trunc_f32 v5, 0x3f717273
+// CHECK: [0xff,0x42,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ceil_f32 v5, v1
+// CHECK: [0x01,0x45,0x0a,0x7e]
+
+v_ceil_f32 v255, v1
+// CHECK: [0x01,0x45,0xfe,0x7f]
+
+v_ceil_f32 v5, v255
+// CHECK: [0xff,0x45,0x0a,0x7e]
+
+v_ceil_f32 v5, s1
+// CHECK: [0x01,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, s103
+// CHECK: [0x67,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_lo
+// CHECK: [0x6a,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_hi
+// CHECK: [0x6b,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, tba_lo
+// CHECK: [0x6c,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, tba_hi
+// CHECK: [0x6d,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, tma_lo
+// CHECK: [0x6e,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, tma_hi
+// CHECK: [0x6f,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, ttmp11
+// CHECK: [0x7b,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, m0
+// CHECK: [0x7c,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_lo
+// CHECK: [0x7e,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_hi
+// CHECK: [0x7f,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, 0
+// CHECK: [0x80,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, -1
+// CHECK: [0xc1,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, 0.5
+// CHECK: [0xf0,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, -4.0
+// CHECK: [0xf7,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, src_vccz
+// CHECK: [0xfb,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, src_execz
+// CHECK: [0xfc,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, src_scc
+// CHECK: [0xfd,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x44,0x0a,0x7e]
+
+v_ceil_f32 v5, 0xaf123456
+// CHECK: [0xff,0x44,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ceil_f32 v5, 0x3f717273
+// CHECK: [0xff,0x44,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rndne_f32 v5, v1
+// CHECK: [0x01,0x47,0x0a,0x7e]
+
+v_rndne_f32 v255, v1
+// CHECK: [0x01,0x47,0xfe,0x7f]
+
+v_rndne_f32 v5, v255
+// CHECK: [0xff,0x47,0x0a,0x7e]
+
+v_rndne_f32 v5, s1
+// CHECK: [0x01,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, s103
+// CHECK: [0x67,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_lo
+// CHECK: [0x6a,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_hi
+// CHECK: [0x6b,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, tba_lo
+// CHECK: [0x6c,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, tba_hi
+// CHECK: [0x6d,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, tma_lo
+// CHECK: [0x6e,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, tma_hi
+// CHECK: [0x6f,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, ttmp11
+// CHECK: [0x7b,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, m0
+// CHECK: [0x7c,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_lo
+// CHECK: [0x7e,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_hi
+// CHECK: [0x7f,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, 0
+// CHECK: [0x80,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, -1
+// CHECK: [0xc1,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, 0.5
+// CHECK: [0xf0,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, -4.0
+// CHECK: [0xf7,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, src_vccz
+// CHECK: [0xfb,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, src_execz
+// CHECK: [0xfc,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, src_scc
+// CHECK: [0xfd,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x46,0x0a,0x7e]
+
+v_rndne_f32 v5, 0xaf123456
+// CHECK: [0xff,0x46,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rndne_f32 v5, 0x3f717273
+// CHECK: [0xff,0x46,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_floor_f32 v5, v1
+// CHECK: [0x01,0x49,0x0a,0x7e]
+
+v_floor_f32 v255, v1
+// CHECK: [0x01,0x49,0xfe,0x7f]
+
+v_floor_f32 v5, v255
+// CHECK: [0xff,0x49,0x0a,0x7e]
+
+v_floor_f32 v5, s1
+// CHECK: [0x01,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, s103
+// CHECK: [0x67,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_lo
+// CHECK: [0x6a,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_hi
+// CHECK: [0x6b,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, tba_lo
+// CHECK: [0x6c,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, tba_hi
+// CHECK: [0x6d,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, tma_lo
+// CHECK: [0x6e,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, tma_hi
+// CHECK: [0x6f,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, ttmp11
+// CHECK: [0x7b,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, m0
+// CHECK: [0x7c,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, exec_lo
+// CHECK: [0x7e,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, exec_hi
+// CHECK: [0x7f,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, 0
+// CHECK: [0x80,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, -1
+// CHECK: [0xc1,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, 0.5
+// CHECK: [0xf0,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, -4.0
+// CHECK: [0xf7,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, src_vccz
+// CHECK: [0xfb,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, src_execz
+// CHECK: [0xfc,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, src_scc
+// CHECK: [0xfd,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x48,0x0a,0x7e]
+
+v_floor_f32 v5, 0xaf123456
+// CHECK: [0xff,0x48,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_floor_f32 v5, 0x3f717273
+// CHECK: [0xff,0x48,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_exp_f32 v5, v1
+// CHECK: [0x01,0x4b,0x0a,0x7e]
+
+v_exp_f32 v255, v1
+// CHECK: [0x01,0x4b,0xfe,0x7f]
+
+v_exp_f32 v5, v255
+// CHECK: [0xff,0x4b,0x0a,0x7e]
+
+v_exp_f32 v5, s1
+// CHECK: [0x01,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, s103
+// CHECK: [0x67,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_lo
+// CHECK: [0x6a,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_hi
+// CHECK: [0x6b,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, tba_lo
+// CHECK: [0x6c,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, tba_hi
+// CHECK: [0x6d,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, tma_lo
+// CHECK: [0x6e,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, tma_hi
+// CHECK: [0x6f,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, ttmp11
+// CHECK: [0x7b,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, m0
+// CHECK: [0x7c,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, exec_lo
+// CHECK: [0x7e,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, exec_hi
+// CHECK: [0x7f,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, 0
+// CHECK: [0x80,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, -1
+// CHECK: [0xc1,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, 0.5
+// CHECK: [0xf0,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, -4.0
+// CHECK: [0xf7,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, src_vccz
+// CHECK: [0xfb,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, src_execz
+// CHECK: [0xfc,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, src_scc
+// CHECK: [0xfd,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x4a,0x0a,0x7e]
+
+v_exp_f32 v5, 0xaf123456
+// CHECK: [0xff,0x4a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_exp_f32 v5, 0x3f717273
+// CHECK: [0xff,0x4a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_log_clamp_f32 v5, v1
+// CHECK: [0x01,0x4d,0x0a,0x7e]
+
+v_log_clamp_f32 v255, v1
+// CHECK: [0x01,0x4d,0xfe,0x7f]
+
+v_log_clamp_f32 v5, v255
+// CHECK: [0xff,0x4d,0x0a,0x7e]
+
+v_log_clamp_f32 v5, s1
+// CHECK: [0x01,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, s103
+// CHECK: [0x67,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, vcc_lo
+// CHECK: [0x6a,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, vcc_hi
+// CHECK: [0x6b,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, tba_lo
+// CHECK: [0x6c,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, tba_hi
+// CHECK: [0x6d,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, tma_lo
+// CHECK: [0x6e,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, tma_hi
+// CHECK: [0x6f,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, ttmp11
+// CHECK: [0x7b,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, m0
+// CHECK: [0x7c,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, exec_lo
+// CHECK: [0x7e,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, exec_hi
+// CHECK: [0x7f,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, 0
+// CHECK: [0x80,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, -1
+// CHECK: [0xc1,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, 0.5
+// CHECK: [0xf0,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, -4.0
+// CHECK: [0xf7,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, src_vccz
+// CHECK: [0xfb,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, src_execz
+// CHECK: [0xfc,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, src_scc
+// CHECK: [0xfd,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x4c,0x0a,0x7e]
+
+v_log_clamp_f32 v5, 0xaf123456
+// CHECK: [0xff,0x4c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_log_clamp_f32 v5, 0x3f717273
+// CHECK: [0xff,0x4c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_log_f32 v5, v1
+// CHECK: [0x01,0x4f,0x0a,0x7e]
+
+v_log_f32 v255, v1
+// CHECK: [0x01,0x4f,0xfe,0x7f]
+
+v_log_f32 v5, v255
+// CHECK: [0xff,0x4f,0x0a,0x7e]
+
+v_log_f32 v5, s1
+// CHECK: [0x01,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, s103
+// CHECK: [0x67,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, vcc_lo
+// CHECK: [0x6a,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, vcc_hi
+// CHECK: [0x6b,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, tba_lo
+// CHECK: [0x6c,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, tba_hi
+// CHECK: [0x6d,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, tma_lo
+// CHECK: [0x6e,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, tma_hi
+// CHECK: [0x6f,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, ttmp11
+// CHECK: [0x7b,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, m0
+// CHECK: [0x7c,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, exec_lo
+// CHECK: [0x7e,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, exec_hi
+// CHECK: [0x7f,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, 0
+// CHECK: [0x80,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, -1
+// CHECK: [0xc1,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, 0.5
+// CHECK: [0xf0,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, -4.0
+// CHECK: [0xf7,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, src_vccz
+// CHECK: [0xfb,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, src_execz
+// CHECK: [0xfc,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, src_scc
+// CHECK: [0xfd,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x4e,0x0a,0x7e]
+
+v_log_f32 v5, 0xaf123456
+// CHECK: [0xff,0x4e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_log_f32 v5, 0x3f717273
+// CHECK: [0xff,0x4e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_clamp_f32 v5, v1
+// CHECK: [0x01,0x51,0x0a,0x7e]
+
+v_rcp_clamp_f32 v255, v1
+// CHECK: [0x01,0x51,0xfe,0x7f]
+
+v_rcp_clamp_f32 v5, v255
+// CHECK: [0xff,0x51,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, s1
+// CHECK: [0x01,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, s103
+// CHECK: [0x67,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, vcc_lo
+// CHECK: [0x6a,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, vcc_hi
+// CHECK: [0x6b,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, tba_lo
+// CHECK: [0x6c,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, tba_hi
+// CHECK: [0x6d,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, tma_lo
+// CHECK: [0x6e,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, tma_hi
+// CHECK: [0x6f,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, ttmp11
+// CHECK: [0x7b,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, m0
+// CHECK: [0x7c,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, exec_lo
+// CHECK: [0x7e,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, exec_hi
+// CHECK: [0x7f,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, 0
+// CHECK: [0x80,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, -1
+// CHECK: [0xc1,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, 0.5
+// CHECK: [0xf0,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, -4.0
+// CHECK: [0xf7,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, src_vccz
+// CHECK: [0xfb,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, src_execz
+// CHECK: [0xfc,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, src_scc
+// CHECK: [0xfd,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x50,0x0a,0x7e]
+
+v_rcp_clamp_f32 v5, 0xaf123456
+// CHECK: [0xff,0x50,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_clamp_f32 v5, 0x3f717273
+// CHECK: [0xff,0x50,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_legacy_f32 v5, v1
+// CHECK: [0x01,0x53,0x0a,0x7e]
+
+v_rcp_legacy_f32 v255, v1
+// CHECK: [0x01,0x53,0xfe,0x7f]
+
+v_rcp_legacy_f32 v5, v255
+// CHECK: [0xff,0x53,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, s1
+// CHECK: [0x01,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, s103
+// CHECK: [0x67,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, vcc_lo
+// CHECK: [0x6a,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, vcc_hi
+// CHECK: [0x6b,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, tba_lo
+// CHECK: [0x6c,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, tba_hi
+// CHECK: [0x6d,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, tma_lo
+// CHECK: [0x6e,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, tma_hi
+// CHECK: [0x6f,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, ttmp11
+// CHECK: [0x7b,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, m0
+// CHECK: [0x7c,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, exec_lo
+// CHECK: [0x7e,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, exec_hi
+// CHECK: [0x7f,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, 0
+// CHECK: [0x80,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, -1
+// CHECK: [0xc1,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, 0.5
+// CHECK: [0xf0,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, -4.0
+// CHECK: [0xf7,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, src_vccz
+// CHECK: [0xfb,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, src_execz
+// CHECK: [0xfc,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, src_scc
+// CHECK: [0xfd,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x52,0x0a,0x7e]
+
+v_rcp_legacy_f32 v5, 0xaf123456
+// CHECK: [0xff,0x52,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_legacy_f32 v5, 0x3f717273
+// CHECK: [0xff,0x52,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_f32 v5, v1
+// CHECK: [0x01,0x55,0x0a,0x7e]
+
+v_rcp_f32 v255, v1
+// CHECK: [0x01,0x55,0xfe,0x7f]
+
+v_rcp_f32 v5, v255
+// CHECK: [0xff,0x55,0x0a,0x7e]
+
+v_rcp_f32 v5, s1
+// CHECK: [0x01,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, s103
+// CHECK: [0x67,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_lo
+// CHECK: [0x6a,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_hi
+// CHECK: [0x6b,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, tba_lo
+// CHECK: [0x6c,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, tba_hi
+// CHECK: [0x6d,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, tma_lo
+// CHECK: [0x6e,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, tma_hi
+// CHECK: [0x6f,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, ttmp11
+// CHECK: [0x7b,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, m0
+// CHECK: [0x7c,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_lo
+// CHECK: [0x7e,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_hi
+// CHECK: [0x7f,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, 0
+// CHECK: [0x80,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, -1
+// CHECK: [0xc1,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, 0.5
+// CHECK: [0xf0,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, -4.0
+// CHECK: [0xf7,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, src_vccz
+// CHECK: [0xfb,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, src_execz
+// CHECK: [0xfc,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, src_scc
+// CHECK: [0xfd,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x54,0x0a,0x7e]
+
+v_rcp_f32 v5, 0xaf123456
+// CHECK: [0xff,0x54,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_f32 v5, 0x3f717273
+// CHECK: [0xff,0x54,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_iflag_f32 v5, v1
+// CHECK: [0x01,0x57,0x0a,0x7e]
+
+v_rcp_iflag_f32 v255, v1
+// CHECK: [0x01,0x57,0xfe,0x7f]
+
+v_rcp_iflag_f32 v5, v255
+// CHECK: [0xff,0x57,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s1
+// CHECK: [0x01,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s103
+// CHECK: [0x67,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_lo
+// CHECK: [0x6a,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_hi
+// CHECK: [0x6b,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, tba_lo
+// CHECK: [0x6c,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, tba_hi
+// CHECK: [0x6d,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, tma_lo
+// CHECK: [0x6e,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, tma_hi
+// CHECK: [0x6f,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, ttmp11
+// CHECK: [0x7b,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, m0
+// CHECK: [0x7c,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_lo
+// CHECK: [0x7e,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_hi
+// CHECK: [0x7f,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0
+// CHECK: [0x80,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, -1
+// CHECK: [0xc1,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0.5
+// CHECK: [0xf0,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, -4.0
+// CHECK: [0xf7,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_vccz
+// CHECK: [0xfb,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_execz
+// CHECK: [0xfc,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_scc
+// CHECK: [0xfd,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x56,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0xaf123456
+// CHECK: [0xff,0x56,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_iflag_f32 v5, 0x3f717273
+// CHECK: [0xff,0x56,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_clamp_f32 v5, v1
+// CHECK: [0x01,0x59,0x0a,0x7e]
+
+v_rsq_clamp_f32 v255, v1
+// CHECK: [0x01,0x59,0xfe,0x7f]
+
+v_rsq_clamp_f32 v5, v255
+// CHECK: [0xff,0x59,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, s1
+// CHECK: [0x01,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, s103
+// CHECK: [0x67,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, vcc_lo
+// CHECK: [0x6a,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, vcc_hi
+// CHECK: [0x6b,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, tba_lo
+// CHECK: [0x6c,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, tba_hi
+// CHECK: [0x6d,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, tma_lo
+// CHECK: [0x6e,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, tma_hi
+// CHECK: [0x6f,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, ttmp11
+// CHECK: [0x7b,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, m0
+// CHECK: [0x7c,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, exec_lo
+// CHECK: [0x7e,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, exec_hi
+// CHECK: [0x7f,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, 0
+// CHECK: [0x80,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, -1
+// CHECK: [0xc1,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, 0.5
+// CHECK: [0xf0,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, -4.0
+// CHECK: [0xf7,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, src_vccz
+// CHECK: [0xfb,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, src_execz
+// CHECK: [0xfc,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, src_scc
+// CHECK: [0xfd,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x58,0x0a,0x7e]
+
+v_rsq_clamp_f32 v5, 0xaf123456
+// CHECK: [0xff,0x58,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_clamp_f32 v5, 0x3f717273
+// CHECK: [0xff,0x58,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_legacy_f32 v5, v1
+// CHECK: [0x01,0x5b,0x0a,0x7e]
+
+v_rsq_legacy_f32 v255, v1
+// CHECK: [0x01,0x5b,0xfe,0x7f]
+
+v_rsq_legacy_f32 v5, v255
+// CHECK: [0xff,0x5b,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, s1
+// CHECK: [0x01,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, s103
+// CHECK: [0x67,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, vcc_lo
+// CHECK: [0x6a,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, vcc_hi
+// CHECK: [0x6b,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, tba_lo
+// CHECK: [0x6c,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, tba_hi
+// CHECK: [0x6d,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, tma_lo
+// CHECK: [0x6e,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, tma_hi
+// CHECK: [0x6f,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, ttmp11
+// CHECK: [0x7b,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, m0
+// CHECK: [0x7c,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, exec_lo
+// CHECK: [0x7e,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, exec_hi
+// CHECK: [0x7f,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, 0
+// CHECK: [0x80,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, -1
+// CHECK: [0xc1,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, 0.5
+// CHECK: [0xf0,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, -4.0
+// CHECK: [0xf7,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, src_vccz
+// CHECK: [0xfb,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, src_execz
+// CHECK: [0xfc,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, src_scc
+// CHECK: [0xfd,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x5a,0x0a,0x7e]
+
+v_rsq_legacy_f32 v5, 0xaf123456
+// CHECK: [0xff,0x5a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_legacy_f32 v5, 0x3f717273
+// CHECK: [0xff,0x5a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_f32 v5, v1
+// CHECK: [0x01,0x5d,0x0a,0x7e]
+
+v_rsq_f32 v255, v1
+// CHECK: [0x01,0x5d,0xfe,0x7f]
+
+v_rsq_f32 v5, v255
+// CHECK: [0xff,0x5d,0x0a,0x7e]
+
+v_rsq_f32 v5, s1
+// CHECK: [0x01,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, s103
+// CHECK: [0x67,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_lo
+// CHECK: [0x6a,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_hi
+// CHECK: [0x6b,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, tba_lo
+// CHECK: [0x6c,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, tba_hi
+// CHECK: [0x6d,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, tma_lo
+// CHECK: [0x6e,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, tma_hi
+// CHECK: [0x6f,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, ttmp11
+// CHECK: [0x7b,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, m0
+// CHECK: [0x7c,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_lo
+// CHECK: [0x7e,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_hi
+// CHECK: [0x7f,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, 0
+// CHECK: [0x80,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, -1
+// CHECK: [0xc1,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, 0.5
+// CHECK: [0xf0,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, -4.0
+// CHECK: [0xf7,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, src_vccz
+// CHECK: [0xfb,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, src_execz
+// CHECK: [0xfc,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, src_scc
+// CHECK: [0xfd,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x5c,0x0a,0x7e]
+
+v_rsq_f32 v5, 0xaf123456
+// CHECK: [0xff,0x5c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_f32 v5, 0x3f717273
+// CHECK: [0xff,0x5c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x5f,0x0a,0x7e]
+
+v_rcp_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x5f,0xfc,0x7f]
+
+v_rcp_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x5f,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], vcc
+// CHECK: [0x6a,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], tba
+// CHECK: [0x6c,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], tma
+// CHECK: [0x6e,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], exec
+// CHECK: [0x7e,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0
+// CHECK: [0x80,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], -1
+// CHECK: [0xc1,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x5e,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x5e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x5e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_clamp_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x61,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x61,0xfc,0x7f]
+
+v_rcp_clamp_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x61,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], vcc
+// CHECK: [0x6a,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], tba
+// CHECK: [0x6c,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], tma
+// CHECK: [0x6e,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], exec
+// CHECK: [0x7e,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], 0
+// CHECK: [0x80,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], -1
+// CHECK: [0xc1,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x60,0x0a,0x7e]
+
+v_rcp_clamp_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x60,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_clamp_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x60,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x63,0x0a,0x7e]
+
+v_rsq_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x63,0xfc,0x7f]
+
+v_rsq_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x63,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], vcc
+// CHECK: [0x6a,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], tba
+// CHECK: [0x6c,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], tma
+// CHECK: [0x6e,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], exec
+// CHECK: [0x7e,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0
+// CHECK: [0x80,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], -1
+// CHECK: [0xc1,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x62,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x62,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x62,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_clamp_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x65,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x65,0xfc,0x7f]
+
+v_rsq_clamp_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x65,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], vcc
+// CHECK: [0x6a,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], tba
+// CHECK: [0x6c,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], tma
+// CHECK: [0x6e,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], exec
+// CHECK: [0x7e,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], 0
+// CHECK: [0x80,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], -1
+// CHECK: [0xc1,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x64,0x0a,0x7e]
+
+v_rsq_clamp_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x64,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_clamp_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x64,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sqrt_f32 v5, v1
+// CHECK: [0x01,0x67,0x0a,0x7e]
+
+v_sqrt_f32 v255, v1
+// CHECK: [0x01,0x67,0xfe,0x7f]
+
+v_sqrt_f32 v5, v255
+// CHECK: [0xff,0x67,0x0a,0x7e]
+
+v_sqrt_f32 v5, s1
+// CHECK: [0x01,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, s103
+// CHECK: [0x67,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_lo
+// CHECK: [0x6a,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_hi
+// CHECK: [0x6b,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, tba_lo
+// CHECK: [0x6c,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, tba_hi
+// CHECK: [0x6d,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, tma_lo
+// CHECK: [0x6e,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, tma_hi
+// CHECK: [0x6f,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, ttmp11
+// CHECK: [0x7b,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, m0
+// CHECK: [0x7c,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_lo
+// CHECK: [0x7e,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_hi
+// CHECK: [0x7f,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0
+// CHECK: [0x80,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, -1
+// CHECK: [0xc1,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0.5
+// CHECK: [0xf0,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, -4.0
+// CHECK: [0xf7,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_vccz
+// CHECK: [0xfb,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_execz
+// CHECK: [0xfc,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_scc
+// CHECK: [0xfd,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x66,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0xaf123456
+// CHECK: [0xff,0x66,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f32 v5, 0x3f717273
+// CHECK: [0xff,0x66,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sqrt_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x69,0x0a,0x7e]
+
+v_sqrt_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x69,0xfc,0x7f]
+
+v_sqrt_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x69,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], vcc
+// CHECK: [0x6a,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], tba
+// CHECK: [0x6c,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], tma
+// CHECK: [0x6e,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], exec
+// CHECK: [0x7e,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0
+// CHECK: [0x80,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], -1
+// CHECK: [0xc1,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x68,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x68,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x68,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sin_f32 v5, v1
+// CHECK: [0x01,0x6b,0x0a,0x7e]
+
+v_sin_f32 v255, v1
+// CHECK: [0x01,0x6b,0xfe,0x7f]
+
+v_sin_f32 v5, v255
+// CHECK: [0xff,0x6b,0x0a,0x7e]
+
+v_sin_f32 v5, s1
+// CHECK: [0x01,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, s103
+// CHECK: [0x67,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_lo
+// CHECK: [0x6a,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_hi
+// CHECK: [0x6b,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, tba_lo
+// CHECK: [0x6c,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, tba_hi
+// CHECK: [0x6d,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, tma_lo
+// CHECK: [0x6e,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, tma_hi
+// CHECK: [0x6f,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, ttmp11
+// CHECK: [0x7b,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, m0
+// CHECK: [0x7c,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, exec_lo
+// CHECK: [0x7e,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, exec_hi
+// CHECK: [0x7f,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, 0
+// CHECK: [0x80,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, -1
+// CHECK: [0xc1,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, 0.5
+// CHECK: [0xf0,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, -4.0
+// CHECK: [0xf7,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, src_vccz
+// CHECK: [0xfb,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, src_execz
+// CHECK: [0xfc,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, src_scc
+// CHECK: [0xfd,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x6a,0x0a,0x7e]
+
+v_sin_f32 v5, 0xaf123456
+// CHECK: [0xff,0x6a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sin_f32 v5, 0x3f717273
+// CHECK: [0xff,0x6a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cos_f32 v5, v1
+// CHECK: [0x01,0x6d,0x0a,0x7e]
+
+v_cos_f32 v255, v1
+// CHECK: [0x01,0x6d,0xfe,0x7f]
+
+v_cos_f32 v5, v255
+// CHECK: [0xff,0x6d,0x0a,0x7e]
+
+v_cos_f32 v5, s1
+// CHECK: [0x01,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, s103
+// CHECK: [0x67,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_lo
+// CHECK: [0x6a,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_hi
+// CHECK: [0x6b,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, tba_lo
+// CHECK: [0x6c,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, tba_hi
+// CHECK: [0x6d,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, tma_lo
+// CHECK: [0x6e,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, tma_hi
+// CHECK: [0x6f,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, ttmp11
+// CHECK: [0x7b,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, m0
+// CHECK: [0x7c,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, exec_lo
+// CHECK: [0x7e,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, exec_hi
+// CHECK: [0x7f,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, 0
+// CHECK: [0x80,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, -1
+// CHECK: [0xc1,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, 0.5
+// CHECK: [0xf0,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, -4.0
+// CHECK: [0xf7,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, src_vccz
+// CHECK: [0xfb,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, src_execz
+// CHECK: [0xfc,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, src_scc
+// CHECK: [0xfd,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x6c,0x0a,0x7e]
+
+v_cos_f32 v5, 0xaf123456
+// CHECK: [0xff,0x6c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cos_f32 v5, 0x3f717273
+// CHECK: [0xff,0x6c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_not_b32 v5, v1
+// CHECK: [0x01,0x6f,0x0a,0x7e]
+
+v_not_b32 v255, v1
+// CHECK: [0x01,0x6f,0xfe,0x7f]
+
+v_not_b32 v5, v255
+// CHECK: [0xff,0x6f,0x0a,0x7e]
+
+v_not_b32 v5, s1
+// CHECK: [0x01,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, s103
+// CHECK: [0x67,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, flat_scratch_lo
+// CHECK: [0x68,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, flat_scratch_hi
+// CHECK: [0x69,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, vcc_lo
+// CHECK: [0x6a,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, vcc_hi
+// CHECK: [0x6b,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, tba_lo
+// CHECK: [0x6c,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, tba_hi
+// CHECK: [0x6d,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, tma_lo
+// CHECK: [0x6e,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, tma_hi
+// CHECK: [0x6f,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, ttmp11
+// CHECK: [0x7b,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, m0
+// CHECK: [0x7c,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, exec_lo
+// CHECK: [0x7e,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, exec_hi
+// CHECK: [0x7f,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, 0
+// CHECK: [0x80,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, -1
+// CHECK: [0xc1,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, 0.5
+// CHECK: [0xf0,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, -4.0
+// CHECK: [0xf7,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, src_vccz
+// CHECK: [0xfb,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, src_execz
+// CHECK: [0xfc,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, src_scc
+// CHECK: [0xfd,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x6e,0x0a,0x7e]
+
+v_not_b32 v5, 0xaf123456
+// CHECK: [0xff,0x6e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_not_b32 v5, 0x3f717273
+// CHECK: [0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_bfrev_b32 v5, v1
+// CHECK: [0x01,0x71,0x0a,0x7e]
+
+v_bfrev_b32 v255, v1
+// CHECK: [0x01,0x71,0xfe,0x7f]
+
+v_bfrev_b32 v5, v255
+// CHECK: [0xff,0x71,0x0a,0x7e]
+
+v_bfrev_b32 v5, s1
+// CHECK: [0x01,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, s103
+// CHECK: [0x67,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, flat_scratch_lo
+// CHECK: [0x68,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, flat_scratch_hi
+// CHECK: [0x69,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_lo
+// CHECK: [0x6a,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_hi
+// CHECK: [0x6b,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, tba_lo
+// CHECK: [0x6c,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, tba_hi
+// CHECK: [0x6d,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, tma_lo
+// CHECK: [0x6e,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, tma_hi
+// CHECK: [0x6f,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, ttmp11
+// CHECK: [0x7b,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, m0
+// CHECK: [0x7c,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_lo
+// CHECK: [0x7e,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_hi
+// CHECK: [0x7f,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0
+// CHECK: [0x80,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, -1
+// CHECK: [0xc1,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0.5
+// CHECK: [0xf0,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, -4.0
+// CHECK: [0xf7,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_vccz
+// CHECK: [0xfb,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_execz
+// CHECK: [0xfc,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_scc
+// CHECK: [0xfd,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x70,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0xaf123456
+// CHECK: [0xff,0x70,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_bfrev_b32 v5, 0x3f717273
+// CHECK: [0xff,0x70,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbh_u32 v5, v1
+// CHECK: [0x01,0x73,0x0a,0x7e]
+
+v_ffbh_u32 v255, v1
+// CHECK: [0x01,0x73,0xfe,0x7f]
+
+v_ffbh_u32 v5, v255
+// CHECK: [0xff,0x73,0x0a,0x7e]
+
+v_ffbh_u32 v5, s1
+// CHECK: [0x01,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, s103
+// CHECK: [0x67,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, flat_scratch_lo
+// CHECK: [0x68,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, flat_scratch_hi
+// CHECK: [0x69,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_lo
+// CHECK: [0x6a,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_hi
+// CHECK: [0x6b,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, tba_lo
+// CHECK: [0x6c,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, tba_hi
+// CHECK: [0x6d,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, tma_lo
+// CHECK: [0x6e,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, tma_hi
+// CHECK: [0x6f,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, ttmp11
+// CHECK: [0x7b,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, m0
+// CHECK: [0x7c,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_lo
+// CHECK: [0x7e,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_hi
+// CHECK: [0x7f,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0
+// CHECK: [0x80,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, -1
+// CHECK: [0xc1,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0.5
+// CHECK: [0xf0,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, -4.0
+// CHECK: [0xf7,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_vccz
+// CHECK: [0xfb,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_execz
+// CHECK: [0xfc,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_scc
+// CHECK: [0xfd,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_lds_direct
+// CHECK: [0xfe,0x72,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0xaf123456
+// CHECK: [0xff,0x72,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbh_u32 v5, 0x3f717273
+// CHECK: [0xff,0x72,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbl_b32 v5, v1
+// CHECK: [0x01,0x75,0x0a,0x7e]
+
+v_ffbl_b32 v255, v1
+// CHECK: [0x01,0x75,0xfe,0x7f]
+
+v_ffbl_b32 v5, v255
+// CHECK: [0xff,0x75,0x0a,0x7e]
+
+v_ffbl_b32 v5, s1
+// CHECK: [0x01,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, s103
+// CHECK: [0x67,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, flat_scratch_lo
+// CHECK: [0x68,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, flat_scratch_hi
+// CHECK: [0x69,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_lo
+// CHECK: [0x6a,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_hi
+// CHECK: [0x6b,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, tba_lo
+// CHECK: [0x6c,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, tba_hi
+// CHECK: [0x6d,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, tma_lo
+// CHECK: [0x6e,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, tma_hi
+// CHECK: [0x6f,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, ttmp11
+// CHECK: [0x7b,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, m0
+// CHECK: [0x7c,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_lo
+// CHECK: [0x7e,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_hi
+// CHECK: [0x7f,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0
+// CHECK: [0x80,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, -1
+// CHECK: [0xc1,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0.5
+// CHECK: [0xf0,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, -4.0
+// CHECK: [0xf7,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_vccz
+// CHECK: [0xfb,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_execz
+// CHECK: [0xfc,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_scc
+// CHECK: [0xfd,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x74,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0xaf123456
+// CHECK: [0xff,0x74,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbl_b32 v5, 0x3f717273
+// CHECK: [0xff,0x74,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbh_i32 v5, v1
+// CHECK: [0x01,0x77,0x0a,0x7e]
+
+v_ffbh_i32 v255, v1
+// CHECK: [0x01,0x77,0xfe,0x7f]
+
+v_ffbh_i32 v5, v255
+// CHECK: [0xff,0x77,0x0a,0x7e]
+
+v_ffbh_i32 v5, s1
+// CHECK: [0x01,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, s103
+// CHECK: [0x67,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, flat_scratch_lo
+// CHECK: [0x68,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, flat_scratch_hi
+// CHECK: [0x69,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_lo
+// CHECK: [0x6a,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_hi
+// CHECK: [0x6b,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, tba_lo
+// CHECK: [0x6c,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, tba_hi
+// CHECK: [0x6d,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, tma_lo
+// CHECK: [0x6e,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, tma_hi
+// CHECK: [0x6f,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, ttmp11
+// CHECK: [0x7b,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, m0
+// CHECK: [0x7c,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_lo
+// CHECK: [0x7e,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_hi
+// CHECK: [0x7f,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0
+// CHECK: [0x80,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, -1
+// CHECK: [0xc1,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0.5
+// CHECK: [0xf0,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, -4.0
+// CHECK: [0xf7,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_vccz
+// CHECK: [0xfb,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_execz
+// CHECK: [0xfc,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_scc
+// CHECK: [0xfd,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_lds_direct
+// CHECK: [0xfe,0x76,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0xaf123456
+// CHECK: [0xff,0x76,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbh_i32 v5, 0x3f717273
+// CHECK: [0xff,0x76,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_exp_i32_f64 v5, v[1:2]
+// CHECK: [0x01,0x79,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v255, v[1:2]
+// CHECK: [0x01,0x79,0xfe,0x7f]
+
+v_frexp_exp_i32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x79,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[2:3]
+// CHECK: [0x02,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[4:5]
+// CHECK: [0x04,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[102:103]
+// CHECK: [0x66,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, flat_scratch
+// CHECK: [0x68,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, vcc
+// CHECK: [0x6a,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, tba
+// CHECK: [0x6c,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, tma
+// CHECK: [0x6e,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, ttmp[10:11]
+// CHECK: [0x7a,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, exec
+// CHECK: [0x7e,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0
+// CHECK: [0x80,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, -1
+// CHECK: [0xc1,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0.5
+// CHECK: [0xf0,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, -4.0
+// CHECK: [0xf7,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_vccz
+// CHECK: [0xfb,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_execz
+// CHECK: [0xfc,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_scc
+// CHECK: [0xfd,0x78,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x78,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x78,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_mant_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x7b,0x0a,0x7e]
+
+v_frexp_mant_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x7b,0xfc,0x7f]
+
+v_frexp_mant_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x7b,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], vcc
+// CHECK: [0x6a,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], tba
+// CHECK: [0x6c,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], tma
+// CHECK: [0x6e,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], exec
+// CHECK: [0x7e,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0
+// CHECK: [0x80,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], -1
+// CHECK: [0xc1,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x7a,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x7a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x7a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_fract_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x7d,0x0a,0x7e]
+
+v_fract_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x7d,0xfc,0x7f]
+
+v_fract_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x7d,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[102:103]
+// CHECK: [0x66,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], flat_scratch
+// CHECK: [0x68,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], vcc
+// CHECK: [0x6a,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], tba
+// CHECK: [0x6c,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], tma
+// CHECK: [0x6e,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], exec
+// CHECK: [0x7e,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0
+// CHECK: [0x80,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], -1
+// CHECK: [0xc1,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x7c,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x7c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_fract_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x7c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_exp_i32_f32 v5, v1
+// CHECK: [0x01,0x7f,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v255, v1
+// CHECK: [0x01,0x7f,0xfe,0x7f]
+
+v_frexp_exp_i32_f32 v5, v255
+// CHECK: [0xff,0x7f,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s1
+// CHECK: [0x01,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s103
+// CHECK: [0x67,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, tba_lo
+// CHECK: [0x6c,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, tba_hi
+// CHECK: [0x6d,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, tma_lo
+// CHECK: [0x6e,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, tma_hi
+// CHECK: [0x6f,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, ttmp11
+// CHECK: [0x7b,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, m0
+// CHECK: [0x7c,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0
+// CHECK: [0x80,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, -1
+// CHECK: [0xc1,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x7e,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x7e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x7e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_mant_f32 v5, v1
+// CHECK: [0x01,0x81,0x0a,0x7e]
+
+v_frexp_mant_f32 v255, v1
+// CHECK: [0x01,0x81,0xfe,0x7f]
+
+v_frexp_mant_f32 v5, v255
+// CHECK: [0xff,0x81,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s1
+// CHECK: [0x01,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s103
+// CHECK: [0x67,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_lo
+// CHECK: [0x6a,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_hi
+// CHECK: [0x6b,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, tba_lo
+// CHECK: [0x6c,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, tba_hi
+// CHECK: [0x6d,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, tma_lo
+// CHECK: [0x6e,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, tma_hi
+// CHECK: [0x6f,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, ttmp11
+// CHECK: [0x7b,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, m0
+// CHECK: [0x7c,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_lo
+// CHECK: [0x7e,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_hi
+// CHECK: [0x7f,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0
+// CHECK: [0x80,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, -1
+// CHECK: [0xc1,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0.5
+// CHECK: [0xf0,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, -4.0
+// CHECK: [0xf7,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_vccz
+// CHECK: [0xfb,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_execz
+// CHECK: [0xfc,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_scc
+// CHECK: [0xfd,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x80,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0xaf123456
+// CHECK: [0xff,0x80,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f32 v5, 0x3f717273
+// CHECK: [0xff,0x80,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_clrexcp
+// CHECK: [0x00,0x82,0x00,0x7e]
+
+v_movreld_b32 v5, v1
+// CHECK: [0x01,0x85,0x0a,0x7e]
+
+v_movreld_b32 v255, v1
+// CHECK: [0x01,0x85,0xfe,0x7f]
+
+v_movreld_b32 v5, v255
+// CHECK: [0xff,0x85,0x0a,0x7e]
+
+v_movreld_b32 v5, m0
+// CHECK: [0x7c,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, 0
+// CHECK: [0x80,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, -1
+// CHECK: [0xc1,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, 0.5
+// CHECK: [0xf0,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, -4.0
+// CHECK: [0xf7,0x84,0x0a,0x7e]
+
+v_movreld_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x84,0x0a,0x7e]
+
+v_movrels_b32 v5, v1
+// CHECK: [0x01,0x87,0x0a,0x7e]
+
+v_movrels_b32 v255, v1
+// CHECK: [0x01,0x87,0xfe,0x7f]
+
+v_movrels_b32 v5, v255
+// CHECK: [0xff,0x87,0x0a,0x7e]
+
+v_movrelsd_b32 v5, v1
+// CHECK: [0x01,0x89,0x0a,0x7e]
+
+v_movrelsd_b32 v255, v1
+// CHECK: [0x01,0x89,0xfe,0x7f]
+
+v_movrelsd_b32 v5, v255
+// CHECK: [0xff,0x89,0x0a,0x7e]
+
+v_log_legacy_f32 v5, v1
+// CHECK: [0x01,0x8b,0x0a,0x7e]
+
+v_log_legacy_f32 v255, v1
+// CHECK: [0x01,0x8b,0xfe,0x7f]
+
+v_log_legacy_f32 v5, v255
+// CHECK: [0xff,0x8b,0x0a,0x7e]
+
+v_log_legacy_f32 v5, s1
+// CHECK: [0x01,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, s103
+// CHECK: [0x67,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, vcc_lo
+// CHECK: [0x6a,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, vcc_hi
+// CHECK: [0x6b,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, tba_lo
+// CHECK: [0x6c,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, tba_hi
+// CHECK: [0x6d,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, tma_lo
+// CHECK: [0x6e,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, tma_hi
+// CHECK: [0x6f,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, ttmp11
+// CHECK: [0x7b,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, m0
+// CHECK: [0x7c,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, exec_lo
+// CHECK: [0x7e,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, exec_hi
+// CHECK: [0x7f,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, 0
+// CHECK: [0x80,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, -1
+// CHECK: [0xc1,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, 0.5
+// CHECK: [0xf0,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, -4.0
+// CHECK: [0xf7,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_vccz
+// CHECK: [0xfb,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_execz
+// CHECK: [0xfc,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_scc
+// CHECK: [0xfd,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x8a,0x0a,0x7e]
+
+v_log_legacy_f32 v5, 0xaf123456
+// CHECK: [0xff,0x8a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_log_legacy_f32 v5, 0x3f717273
+// CHECK: [0xff,0x8a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_exp_legacy_f32 v5, v1
+// CHECK: [0x01,0x8d,0x0a,0x7e]
+
+v_exp_legacy_f32 v255, v1
+// CHECK: [0x01,0x8d,0xfe,0x7f]
+
+v_exp_legacy_f32 v5, v255
+// CHECK: [0xff,0x8d,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, s1
+// CHECK: [0x01,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, s103
+// CHECK: [0x67,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, flat_scratch_lo
+// CHECK: [0x68,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, flat_scratch_hi
+// CHECK: [0x69,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, vcc_lo
+// CHECK: [0x6a,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, vcc_hi
+// CHECK: [0x6b,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, tba_lo
+// CHECK: [0x6c,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, tba_hi
+// CHECK: [0x6d,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, tma_lo
+// CHECK: [0x6e,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, tma_hi
+// CHECK: [0x6f,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, ttmp11
+// CHECK: [0x7b,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, m0
+// CHECK: [0x7c,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, exec_lo
+// CHECK: [0x7e,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, exec_hi
+// CHECK: [0x7f,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, 0
+// CHECK: [0x80,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, -1
+// CHECK: [0xc1,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, 0.5
+// CHECK: [0xf0,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, -4.0
+// CHECK: [0xf7,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_vccz
+// CHECK: [0xfb,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_execz
+// CHECK: [0xfc,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_scc
+// CHECK: [0xfd,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x8c,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, 0xaf123456
+// CHECK: [0xff,0x8c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_exp_legacy_f32 v5, 0x3f717273
+// CHECK: [0xff,0x8c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx7_asm_vop2.s
new file mode 100644
index 0000000000000..fe71cba45d3ee
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vop2.s
@@ -0,0 +1,3796 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+v_cndmask_b32 v5, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x00]
+
+v_cndmask_b32 v255, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x01]
+
+v_cndmask_b32 v5, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x00]
+
+v_cndmask_b32 v5, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, src_lds_direct, v2, vcc
+// CHECK: [0xfe,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x00]
+
+v_readlane_b32 s5, v1, s2
+// CHECK: [0x01,0x05,0x0a,0x02]
+
+v_readlane_b32 s103, v1, s2
+// CHECK: [0x01,0x05,0xce,0x02]
+
+v_readlane_b32 tba_lo, v1, s2
+// CHECK: [0x01,0x05,0xd8,0x02]
+
+v_readlane_b32 tba_hi, v1, s2
+// CHECK: [0x01,0x05,0xda,0x02]
+
+v_readlane_b32 tma_lo, v1, s2
+// CHECK: [0x01,0x05,0xdc,0x02]
+
+v_readlane_b32 tma_hi, v1, s2
+// CHECK: [0x01,0x05,0xde,0x02]
+
+v_readlane_b32 ttmp11, v1, s2
+// CHECK: [0x01,0x05,0xf6,0x02]
+
+v_readlane_b32 s5, v255, s2
+// CHECK: [0xff,0x05,0x0a,0x02]
+
+v_readlane_b32 s5, src_lds_direct, s2
+// CHECK: [0xfe,0x04,0x0a,0x02]
+
+v_readlane_b32 s5, v1, s103
+// CHECK: [0x01,0xcf,0x0a,0x02]
+
+v_readlane_b32 s5, v1, flat_scratch_lo
+// CHECK: [0x01,0xd1,0x0a,0x02]
+
+v_readlane_b32 s5, v1, flat_scratch_hi
+// CHECK: [0x01,0xd3,0x0a,0x02]
+
+v_readlane_b32 s5, v1, vcc_lo
+// CHECK: [0x01,0xd5,0x0a,0x02]
+
+v_readlane_b32 s5, v1, vcc_hi
+// CHECK: [0x01,0xd7,0x0a,0x02]
+
+v_readlane_b32 s5, v1, tba_lo
+// CHECK: [0x01,0xd9,0x0a,0x02]
+
+v_readlane_b32 s5, v1, tba_hi
+// CHECK: [0x01,0xdb,0x0a,0x02]
+
+v_readlane_b32 s5, v1, tma_lo
+// CHECK: [0x01,0xdd,0x0a,0x02]
+
+v_readlane_b32 s5, v1, tma_hi
+// CHECK: [0x01,0xdf,0x0a,0x02]
+
+v_readlane_b32 s5, v1, ttmp11
+// CHECK: [0x01,0xf7,0x0a,0x02]
+
+v_readlane_b32 s5, v1, m0
+// CHECK: [0x01,0xf9,0x0a,0x02]
+
+v_readlane_b32 s5, v1, 0
+// CHECK: [0x01,0x01,0x0b,0x02]
+
+v_writelane_b32 v5, 0, s2
+// CHECK: [0x80,0x04,0x0a,0x04]
+
+v_writelane_b32 v255, 0, s2
+// CHECK: [0x80,0x04,0xfe,0x05]
+
+v_writelane_b32 v5, -1, s2
+// CHECK: [0xc1,0x04,0x0a,0x04]
+
+v_writelane_b32 v5, 0.5, s2
+// CHECK: [0xf0,0x04,0x0a,0x04]
+
+v_writelane_b32 v5, -4.0, s2
+// CHECK: [0xf7,0x04,0x0a,0x04]
+
+v_writelane_b32 v5, src_lds_direct, s2
+// CHECK: [0xfe,0x04,0x0a,0x04]
+
+v_writelane_b32 v5, 0, s103
+// CHECK: [0x80,0xce,0x0a,0x04]
+
+v_writelane_b32 v5, 0, flat_scratch_lo
+// CHECK: [0x80,0xd0,0x0a,0x04]
+
+v_writelane_b32 v5, 0, flat_scratch_hi
+// CHECK: [0x80,0xd2,0x0a,0x04]
+
+v_writelane_b32 v5, 0, vcc_lo
+// CHECK: [0x80,0xd4,0x0a,0x04]
+
+v_writelane_b32 v5, 0, vcc_hi
+// CHECK: [0x80,0xd6,0x0a,0x04]
+
+v_writelane_b32 v5, 0, tba_lo
+// CHECK: [0x80,0xd8,0x0a,0x04]
+
+v_writelane_b32 v5, 0, tba_hi
+// CHECK: [0x80,0xda,0x0a,0x04]
+
+v_writelane_b32 v5, 0, tma_lo
+// CHECK: [0x80,0xdc,0x0a,0x04]
+
+v_writelane_b32 v5, 0, tma_hi
+// CHECK: [0x80,0xde,0x0a,0x04]
+
+v_writelane_b32 v5, 0, ttmp11
+// CHECK: [0x80,0xf6,0x0a,0x04]
+
+v_writelane_b32 v5, 0, m0
+// CHECK: [0x80,0xf8,0x0a,0x04]
+
+v_writelane_b32 v5, 0, 0
+// CHECK: [0x80,0x00,0x0b,0x04]
+
+v_add_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x06]
+
+v_add_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x07]
+
+v_add_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x06]
+
+v_add_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x06]
+
+v_add_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x06]
+
+v_add_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x06]
+
+v_add_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x06]
+
+v_add_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x06]
+
+v_add_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x06]
+
+v_add_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x06]
+
+v_add_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x06]
+
+v_add_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x06]
+
+v_add_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x06]
+
+v_add_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x06]
+
+v_add_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x06]
+
+v_add_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x06]
+
+v_add_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x06]
+
+v_add_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x06]
+
+v_add_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x06]
+
+v_add_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x06]
+
+v_add_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x06]
+
+v_add_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x06]
+
+v_add_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x06]
+
+v_add_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x06]
+
+v_add_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x06]
+
+v_add_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x06,0x56,0x34,0x12,0xaf]
+
+v_add_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x06,0x73,0x72,0x71,0x3f]
+
+v_add_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x06]
+
+v_sub_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x08]
+
+v_sub_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x09]
+
+v_sub_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x08]
+
+v_sub_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x08]
+
+v_sub_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x08]
+
+v_sub_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x08]
+
+v_sub_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x08]
+
+v_sub_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x08]
+
+v_sub_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x08]
+
+v_sub_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x08]
+
+v_sub_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x08]
+
+v_sub_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x08]
+
+v_sub_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x08]
+
+v_sub_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x08]
+
+v_sub_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x08]
+
+v_sub_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x08]
+
+v_sub_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x08]
+
+v_sub_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x08]
+
+v_sub_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x08]
+
+v_sub_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x08]
+
+v_sub_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x08]
+
+v_sub_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x08]
+
+v_sub_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x08]
+
+v_sub_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x08]
+
+v_sub_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x08]
+
+v_sub_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x08,0x56,0x34,0x12,0xaf]
+
+v_sub_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x08,0x73,0x72,0x71,0x3f]
+
+v_sub_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x08]
+
+v_subrev_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x0a]
+
+v_subrev_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x0b]
+
+v_subrev_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x0a]
+
+v_subrev_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x0a]
+
+v_subrev_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x0a,0x56,0x34,0x12,0xaf]
+
+v_subrev_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x0a,0x73,0x72,0x71,0x3f]
+
+v_subrev_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x0a]
+
+v_mac_legacy_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x0c]
+
+v_mac_legacy_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x0d]
+
+v_mac_legacy_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x0c]
+
+v_mac_legacy_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x0c,0x56,0x34,0x12,0xaf]
+
+v_mac_legacy_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x0c,0x73,0x72,0x71,0x3f]
+
+v_mac_legacy_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x0c]
+
+v_mul_legacy_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x0e]
+
+v_mul_legacy_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x0f]
+
+v_mul_legacy_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x0e]
+
+v_mul_legacy_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x0e,0x56,0x34,0x12,0xaf]
+
+v_mul_legacy_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x0e,0x73,0x72,0x71,0x3f]
+
+v_mul_legacy_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x0e]
+
+v_mul_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x10]
+
+v_mul_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x11]
+
+v_mul_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x10]
+
+v_mul_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x10]
+
+v_mul_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x10]
+
+v_mul_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x10]
+
+v_mul_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x10]
+
+v_mul_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x10]
+
+v_mul_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x10]
+
+v_mul_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x10]
+
+v_mul_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x10]
+
+v_mul_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x10]
+
+v_mul_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x10]
+
+v_mul_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x10]
+
+v_mul_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x10]
+
+v_mul_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x10]
+
+v_mul_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x10]
+
+v_mul_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x10]
+
+v_mul_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x10]
+
+v_mul_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x10]
+
+v_mul_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x10]
+
+v_mul_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x10]
+
+v_mul_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x10]
+
+v_mul_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x10]
+
+v_mul_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x10]
+
+v_mul_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x10,0x56,0x34,0x12,0xaf]
+
+v_mul_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x10,0x73,0x72,0x71,0x3f]
+
+v_mul_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x10]
+
+v_mul_i32_i24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x12]
+
+v_mul_i32_i24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x13]
+
+v_mul_i32_i24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x12]
+
+v_mul_i32_i24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x12]
+
+v_mul_i32_i24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0xaf]
+
+v_mul_i32_i24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x3f]
+
+v_mul_i32_i24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x12]
+
+v_mul_hi_i32_i24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x14]
+
+v_mul_hi_i32_i24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x15]
+
+v_mul_hi_i32_i24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x14]
+
+v_mul_hi_i32_i24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x14,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_i32_i24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x14,0x73,0x72,0x71,0x3f]
+
+v_mul_hi_i32_i24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x14]
+
+v_mul_u32_u24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x16]
+
+v_mul_u32_u24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x17]
+
+v_mul_u32_u24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x16]
+
+v_mul_u32_u24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x16]
+
+v_mul_u32_u24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x16,0x56,0x34,0x12,0xaf]
+
+v_mul_u32_u24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x16,0x73,0x72,0x71,0x3f]
+
+v_mul_u32_u24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x16]
+
+v_mul_hi_u32_u24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x18]
+
+v_mul_hi_u32_u24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x19]
+
+v_mul_hi_u32_u24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x18]
+
+v_mul_hi_u32_u24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x18,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_u32_u24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x18,0x73,0x72,0x71,0x3f]
+
+v_mul_hi_u32_u24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x18]
+
+v_min_legacy_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x1a]
+
+v_min_legacy_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x1b]
+
+v_min_legacy_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x1a]
+
+v_min_legacy_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x1a]
+
+v_min_legacy_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x1a,0x56,0x34,0x12,0xaf]
+
+v_min_legacy_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x1a,0x73,0x72,0x71,0x3f]
+
+v_min_legacy_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x1a]
+
+v_max_legacy_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x1c]
+
+v_max_legacy_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x1d]
+
+v_max_legacy_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x1c]
+
+v_max_legacy_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x1c]
+
+v_max_legacy_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x1c,0x56,0x34,0x12,0xaf]
+
+v_max_legacy_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x1c,0x73,0x72,0x71,0x3f]
+
+v_max_legacy_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x1c]
+
+v_min_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x1e]
+
+v_min_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x1f]
+
+v_min_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x1e]
+
+v_min_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x1e]
+
+v_min_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x1e]
+
+v_min_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x1e]
+
+v_min_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x1e]
+
+v_min_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x1e]
+
+v_min_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x1e]
+
+v_min_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x1e]
+
+v_min_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x1e]
+
+v_min_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x1e]
+
+v_min_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x1e]
+
+v_min_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x1e]
+
+v_min_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x1e]
+
+v_min_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x1e]
+
+v_min_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x1e]
+
+v_min_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x1e]
+
+v_min_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x1e]
+
+v_min_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x1e]
+
+v_min_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x1e]
+
+v_min_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x1e]
+
+v_min_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x1e]
+
+v_min_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x1e]
+
+v_min_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x1e]
+
+v_min_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x1e,0x56,0x34,0x12,0xaf]
+
+v_min_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x1e,0x73,0x72,0x71,0x3f]
+
+v_min_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x1e]
+
+v_max_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x20]
+
+v_max_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x21]
+
+v_max_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x20]
+
+v_max_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x20]
+
+v_max_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x20]
+
+v_max_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x20]
+
+v_max_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x20]
+
+v_max_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x20]
+
+v_max_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x20]
+
+v_max_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x20]
+
+v_max_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x20]
+
+v_max_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x20]
+
+v_max_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x20]
+
+v_max_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x20]
+
+v_max_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x20]
+
+v_max_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x20]
+
+v_max_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x20]
+
+v_max_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x20]
+
+v_max_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x20]
+
+v_max_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x20]
+
+v_max_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x20]
+
+v_max_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x20]
+
+v_max_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x20]
+
+v_max_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x20]
+
+v_max_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x20]
+
+v_max_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x20,0x56,0x34,0x12,0xaf]
+
+v_max_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x20,0x73,0x72,0x71,0x3f]
+
+v_max_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x20]
+
+v_min_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x22]
+
+v_min_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x23]
+
+v_min_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x22]
+
+v_min_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x22]
+
+v_min_i32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x22]
+
+v_min_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x22]
+
+v_min_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x22]
+
+v_min_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x22]
+
+v_min_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x22]
+
+v_min_i32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x22]
+
+v_min_i32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x22]
+
+v_min_i32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x22]
+
+v_min_i32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x22]
+
+v_min_i32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x22]
+
+v_min_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x22]
+
+v_min_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x22]
+
+v_min_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x22]
+
+v_min_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x22]
+
+v_min_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x22]
+
+v_min_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x22]
+
+v_min_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x22]
+
+v_min_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x22]
+
+v_min_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x22]
+
+v_min_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x22]
+
+v_min_i32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x22]
+
+v_min_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x22,0x56,0x34,0x12,0xaf]
+
+v_min_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x22,0x73,0x72,0x71,0x3f]
+
+v_min_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x22]
+
+v_max_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x24]
+
+v_max_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x25]
+
+v_max_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x24]
+
+v_max_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x24]
+
+v_max_i32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x24]
+
+v_max_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x24]
+
+v_max_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x24]
+
+v_max_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x24]
+
+v_max_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x24]
+
+v_max_i32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x24]
+
+v_max_i32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x24]
+
+v_max_i32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x24]
+
+v_max_i32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x24]
+
+v_max_i32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x24]
+
+v_max_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x24]
+
+v_max_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x24]
+
+v_max_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x24]
+
+v_max_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x24]
+
+v_max_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x24]
+
+v_max_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x24]
+
+v_max_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x24]
+
+v_max_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x24]
+
+v_max_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x24]
+
+v_max_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x24]
+
+v_max_i32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x24]
+
+v_max_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x24,0x56,0x34,0x12,0xaf]
+
+v_max_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x24,0x73,0x72,0x71,0x3f]
+
+v_max_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x24]
+
+v_min_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x26]
+
+v_min_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x27]
+
+v_min_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x26]
+
+v_min_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x26]
+
+v_min_u32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x26]
+
+v_min_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x26]
+
+v_min_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x26]
+
+v_min_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x26]
+
+v_min_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x26]
+
+v_min_u32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x26]
+
+v_min_u32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x26]
+
+v_min_u32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x26]
+
+v_min_u32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x26]
+
+v_min_u32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x26]
+
+v_min_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x26]
+
+v_min_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x26]
+
+v_min_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x26]
+
+v_min_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x26]
+
+v_min_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x26]
+
+v_min_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x26]
+
+v_min_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x26]
+
+v_min_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x26]
+
+v_min_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x26]
+
+v_min_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x26]
+
+v_min_u32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x26]
+
+v_min_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x26,0x56,0x34,0x12,0xaf]
+
+v_min_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x26,0x73,0x72,0x71,0x3f]
+
+v_min_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x26]
+
+v_max_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x28]
+
+v_max_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x29]
+
+v_max_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x28]
+
+v_max_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x28]
+
+v_max_u32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x28]
+
+v_max_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x28]
+
+v_max_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x28]
+
+v_max_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x28]
+
+v_max_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x28]
+
+v_max_u32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x28]
+
+v_max_u32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x28]
+
+v_max_u32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x28]
+
+v_max_u32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x28]
+
+v_max_u32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x28]
+
+v_max_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x28]
+
+v_max_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x28]
+
+v_max_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x28]
+
+v_max_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x28]
+
+v_max_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x28]
+
+v_max_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x28]
+
+v_max_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x28]
+
+v_max_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x28]
+
+v_max_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x28]
+
+v_max_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x28]
+
+v_max_u32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x28]
+
+v_max_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x28,0x56,0x34,0x12,0xaf]
+
+v_max_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x28,0x73,0x72,0x71,0x3f]
+
+v_max_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x28]
+
+v_lshr_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x2a]
+
+v_lshr_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x2b]
+
+v_lshr_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x2a]
+
+v_lshr_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x2a]
+
+v_lshr_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x2a,0x56,0x34,0x12,0xaf]
+
+v_lshr_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x2a,0x73,0x72,0x71,0x3f]
+
+v_lshr_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x2a]
+
+v_lshrrev_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x2c]
+
+v_lshrrev_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x2d]
+
+v_lshrrev_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x2c]
+
+v_lshrrev_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x2c]
+
+v_lshrrev_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x2c,0x56,0x34,0x12,0xaf]
+
+v_lshrrev_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x2c,0x73,0x72,0x71,0x3f]
+
+v_lshrrev_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x2c]
+
+v_ashr_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x2e]
+
+v_ashr_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x2f]
+
+v_ashr_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x2e]
+
+v_ashr_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x2e]
+
+v_ashr_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x2e,0x56,0x34,0x12,0xaf]
+
+v_ashr_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x2e,0x73,0x72,0x71,0x3f]
+
+v_ashr_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x2e]
+
+v_ashrrev_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x30]
+
+v_ashrrev_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x31]
+
+v_ashrrev_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x30]
+
+v_ashrrev_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x30]
+
+v_ashrrev_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x30,0x56,0x34,0x12,0xaf]
+
+v_ashrrev_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x30,0x73,0x72,0x71,0x3f]
+
+v_ashrrev_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x30]
+
+v_lshl_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x32]
+
+v_lshl_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x33]
+
+v_lshl_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x32]
+
+v_lshl_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x32]
+
+v_lshl_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x32,0x56,0x34,0x12,0xaf]
+
+v_lshl_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x32,0x73,0x72,0x71,0x3f]
+
+v_lshl_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x32]
+
+v_lshlrev_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x34]
+
+v_lshlrev_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x35]
+
+v_lshlrev_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x34]
+
+v_lshlrev_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x34]
+
+v_lshlrev_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x34,0x56,0x34,0x12,0xaf]
+
+v_lshlrev_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x34,0x73,0x72,0x71,0x3f]
+
+v_lshlrev_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x34]
+
+v_and_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x36]
+
+v_and_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x37]
+
+v_and_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x36]
+
+v_and_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x36]
+
+v_and_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x36]
+
+v_and_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x36]
+
+v_and_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x36]
+
+v_and_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x36]
+
+v_and_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x36]
+
+v_and_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x36]
+
+v_and_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x36]
+
+v_and_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x36]
+
+v_and_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x36]
+
+v_and_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x36]
+
+v_and_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x36]
+
+v_and_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x36]
+
+v_and_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x36]
+
+v_and_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x36]
+
+v_and_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x36]
+
+v_and_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x36]
+
+v_and_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x36]
+
+v_and_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x36]
+
+v_and_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x36]
+
+v_and_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x36]
+
+v_and_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x36]
+
+v_and_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x36,0x56,0x34,0x12,0xaf]
+
+v_and_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x36,0x73,0x72,0x71,0x3f]
+
+v_and_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x36]
+
+v_or_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x38]
+
+v_or_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x39]
+
+v_or_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x38]
+
+v_or_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x38]
+
+v_or_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x38]
+
+v_or_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x38]
+
+v_or_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x38]
+
+v_or_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x38]
+
+v_or_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x38]
+
+v_or_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x38]
+
+v_or_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x38]
+
+v_or_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x38]
+
+v_or_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x38]
+
+v_or_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x38]
+
+v_or_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x38]
+
+v_or_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x38]
+
+v_or_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x38]
+
+v_or_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x38]
+
+v_or_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x38]
+
+v_or_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x38]
+
+v_or_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x38]
+
+v_or_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x38]
+
+v_or_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x38]
+
+v_or_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x38]
+
+v_or_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x38]
+
+v_or_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x38,0x56,0x34,0x12,0xaf]
+
+v_or_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x38,0x73,0x72,0x71,0x3f]
+
+v_or_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x38]
+
+v_xor_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x3a]
+
+v_xor_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x3b]
+
+v_xor_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x3a]
+
+v_xor_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x3a]
+
+v_xor_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x3a,0x56,0x34,0x12,0xaf]
+
+v_xor_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x3a,0x73,0x72,0x71,0x3f]
+
+v_xor_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x3a]
+
+v_bfm_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x3c]
+
+v_bfm_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x3d]
+
+v_bfm_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x3c]
+
+v_bfm_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x3c]
+
+v_bfm_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x3c,0x56,0x34,0x12,0xaf]
+
+v_bfm_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x3c,0x73,0x72,0x71,0x3f]
+
+v_bfm_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x3c]
+
+v_mac_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x3e]
+
+v_mac_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x3f]
+
+v_mac_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x3e]
+
+v_mac_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x3e]
+
+v_mac_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x3e,0x56,0x34,0x12,0xaf]
+
+v_mac_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x3e,0x73,0x72,0x71,0x3f]
+
+v_mac_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x3e]
+
+v_madmk_f32 v5, v1, 0x11213141, v3
+// CHECK: [0x01,0x07,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v255, v1, 0x11213141, v3
+// CHECK: [0x01,0x07,0xfe,0x41,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, v255, 0x11213141, v3
+// CHECK: [0xff,0x07,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, 0, 0x11213141, v3
+// CHECK: [0x80,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, -1, 0x11213141, v3
+// CHECK: [0xc1,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, 0.5, 0x11213141, v3
+// CHECK: [0xf0,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, -4.0, 0x11213141, v3
+// CHECK: [0xf7,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, src_lds_direct, 0x11213141, v3
+// CHECK: [0xfe,0x06,0x0a,0x40,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, v1, 0xa1b1c1d1, v3
+// CHECK: [0x01,0x07,0x0a,0x40,0xd1,0xc1,0xb1,0xa1]
+
+v_madmk_f32 v5, v1, 0x11213141, v255
+// CHECK: [0x01,0xff,0x0b,0x40,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v2, 0x11213141
+// CHECK: [0x01,0x05,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v255, v1, v2, 0x11213141
+// CHECK: [0x01,0x05,0xfe,0x43,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v255, v2, 0x11213141
+// CHECK: [0xff,0x05,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, 0, v2, 0x11213141
+// CHECK: [0x80,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, -1, v2, 0x11213141
+// CHECK: [0xc1,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, 0.5, v2, 0x11213141
+// CHECK: [0xf0,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, -4.0, v2, 0x11213141
+// CHECK: [0xf7,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, src_lds_direct, v2, 0x11213141
+// CHECK: [0xfe,0x04,0x0a,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v255, 0x11213141
+// CHECK: [0x01,0xff,0x0b,0x42,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v2, 0xa1b1c1d1
+// CHECK: [0x01,0x05,0x0a,0x42,0xd1,0xc1,0xb1,0xa1]
+
+v_bcnt_u32_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x44]
+
+v_bcnt_u32_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x45]
+
+v_bcnt_u32_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x44]
+
+v_bcnt_u32_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x44,0x56,0x34,0x12,0xaf]
+
+v_bcnt_u32_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x44,0x73,0x72,0x71,0x3f]
+
+v_bcnt_u32_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x44]
+
+v_mbcnt_lo_u32_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x47]
+
+v_mbcnt_lo_u32_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x46]
+
+v_mbcnt_lo_u32_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x46,0x56,0x34,0x12,0xaf]
+
+v_mbcnt_lo_u32_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x46,0x73,0x72,0x71,0x3f]
+
+v_mbcnt_lo_u32_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x46]
+
+v_mbcnt_hi_u32_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x49]
+
+v_mbcnt_hi_u32_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x48]
+
+v_mbcnt_hi_u32_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x48,0x56,0x34,0x12,0xaf]
+
+v_mbcnt_hi_u32_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x48,0x73,0x72,0x71,0x3f]
+
+v_mbcnt_hi_u32_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x48]
+
+v_add_i32 v5, vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x4a]
+
+v_add_i32 v255, vcc, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x4b]
+
+v_add_i32 v5, vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x4a]
+
+v_add_i32 v5, vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x4a]
+
+v_add_i32 v5, vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x4a,0x56,0x34,0x12,0xaf]
+
+v_add_i32 v5, vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x4a,0x73,0x72,0x71,0x3f]
+
+v_add_i32 v5, vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x4a]
+
+v_sub_i32 v5, vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x4c]
+
+v_sub_i32 v255, vcc, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x4d]
+
+v_sub_i32 v5, vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x4c]
+
+v_sub_i32 v5, vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x56,0x34,0x12,0xaf]
+
+v_sub_i32 v5, vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x73,0x72,0x71,0x3f]
+
+v_sub_i32 v5, vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x4c]
+
+v_subrev_i32 v5, vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x4e]
+
+v_subrev_i32 v255, vcc, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x4f]
+
+v_subrev_i32 v5, vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x4e]
+
+v_subrev_i32 v5, vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x56,0x34,0x12,0xaf]
+
+v_subrev_i32 v5, vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x73,0x72,0x71,0x3f]
+
+v_subrev_i32 v5, vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x4e]
+
+v_addc_u32 v5, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x50]
+
+v_addc_u32 v255, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x51]
+
+v_addc_u32 v5, vcc, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x50]
+
+v_addc_u32 v5, vcc, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x50]
+
+v_addc_u32 v5, vcc, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x50]
+
+v_addc_u32 v5, vcc, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x50]
+
+v_addc_u32 v5, vcc, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x50]
+
+v_addc_u32 v5, vcc, src_lds_direct, v2, vcc
+// CHECK: [0xfe,0x04,0x0a,0x50]
+
+v_addc_u32 v5, vcc, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x50]
+
+v_subb_u32 v5, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x52]
+
+v_subb_u32 v255, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x53]
+
+v_subb_u32 v5, vcc, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x52]
+
+v_subb_u32 v5, vcc, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x52]
+
+v_subb_u32 v5, vcc, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x52]
+
+v_subb_u32 v5, vcc, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x52]
+
+v_subb_u32 v5, vcc, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x52]
+
+v_subb_u32 v5, vcc, src_lds_direct, v2, vcc
+// CHECK: [0xfe,0x04,0x0a,0x52]
+
+v_subb_u32 v5, vcc, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x52]
+
+v_subbrev_u32 v5, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x54]
+
+v_subbrev_u32 v255, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x55]
+
+v_subbrev_u32 v5, vcc, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x54]
+
+v_subbrev_u32 v5, vcc, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x54]
+
+v_subbrev_u32 v5, vcc, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x54]
+
+v_subbrev_u32 v5, vcc, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x54]
+
+v_subbrev_u32 v5, vcc, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x54]
+
+v_subbrev_u32 v5, vcc, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x54]
+
+v_ldexp_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x56]
+
+v_ldexp_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x57]
+
+v_ldexp_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x56]
+
+v_ldexp_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x56]
+
+v_ldexp_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x56,0x34,0x12,0xaf]
+
+v_ldexp_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x73,0x72,0x71,0x3f]
+
+v_ldexp_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x56]
+
+v_cvt_pkaccum_u8_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x59]
+
+v_cvt_pkaccum_u8_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x58]
+
+v_cvt_pkaccum_u8_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x56,0x34,0x12,0xaf]
+
+v_cvt_pkaccum_u8_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x73,0x72,0x71,0x3f]
+
+v_cvt_pkaccum_u8_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x58]
+
+v_cvt_pknorm_i16_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x5b]
+
+v_cvt_pknorm_i16_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x5a]
+
+v_cvt_pknorm_i16_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x5a,0x56,0x34,0x12,0xaf]
+
+v_cvt_pknorm_i16_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x5a,0x73,0x72,0x71,0x3f]
+
+v_cvt_pknorm_i16_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x5a]
+
+v_cvt_pknorm_u16_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x5d]
+
+v_cvt_pknorm_u16_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x5c]
+
+v_cvt_pknorm_u16_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x5c,0x56,0x34,0x12,0xaf]
+
+v_cvt_pknorm_u16_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x5c,0x73,0x72,0x71,0x3f]
+
+v_cvt_pknorm_u16_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x5c]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x5f]
+
+v_cvt_pkrtz_f16_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x5e]
+
+v_cvt_pkrtz_f16_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x56,0x34,0x12,0xaf]
+
+v_cvt_pkrtz_f16_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x73,0x72,0x71,0x3f]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x5e]
+
+v_cvt_pk_u16_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x61]
+
+v_cvt_pk_u16_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x60]
+
+v_cvt_pk_u16_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_u16_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x73,0x72,0x71,0x3f]
+
+v_cvt_pk_u16_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x60]
+
+v_cvt_pk_i16_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x63]
+
+v_cvt_pk_i16_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x62]
+
+v_cvt_pk_i16_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x56,0x34,0x12,0xaf]
+
+v_cvt_pk_i16_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x73,0x72,0x71,0x3f]
+
+v_cvt_pk_i16_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x62]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
new file mode 100644
index 0000000000000..143fc658ec829
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vop3.s
@@ -0,0 +1,41875 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+v_nop_e64
+// CHECK: [0x00,0x00,0x00,0xd3,0x00,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x02,0xd3,0x01,0x01,0x00,0x00]
+
+v_mov_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x02,0xd3,0x01,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x02,0xd3,0xff,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x02,0xd3,0x01,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, s103
+// CHECK: [0x05,0x00,0x02,0xd3,0x67,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x02,0xd3,0x68,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x02,0xd3,0x69,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x02,0xd3,0x6a,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x02,0xd3,0x6b,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x02,0xd3,0x6c,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x02,0xd3,0x6d,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x02,0xd3,0x6e,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x02,0xd3,0x6f,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x02,0xd3,0x7b,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x02,0xd3,0x7c,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x02,0xd3,0x7e,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x02,0xd3,0x7f,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x02,0xd3,0x80,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x02,0xd3,0xc1,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x02,0xd3,0xf0,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x02,0xd3,0xf7,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x02,0xd3,0xfb,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x02,0xd3,0xfc,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x02,0xd3,0xfd,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x02,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x06,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x06,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x06,0xd3,0xfe,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x06,0xd3,0x02,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x06,0xd3,0x04,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[102:103]
+// CHECK: [0x05,0x00,0x06,0xd3,0x66,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x06,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x06,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, tba
+// CHECK: [0x05,0x00,0x06,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, tma
+// CHECK: [0x05,0x00,0x06,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, ttmp[10:11]
+// CHECK: [0x05,0x00,0x06,0xd3,0x7a,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x06,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x06,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x06,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x06,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x06,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x06,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x06,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x06,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x06,0xd3,0x01,0x01,0x00,0x20]
+
+v_cvt_i32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x06,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1
+// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[254:255], v1
+// CHECK: [0xfe,0x00,0x08,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v255
+// CHECK: [0x05,0x00,0x08,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s1
+// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s103
+// CHECK: [0x05,0x00,0x08,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], flat_scratch_lo
+// CHECK: [0x05,0x00,0x08,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], flat_scratch_hi
+// CHECK: [0x05,0x00,0x08,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_lo
+// CHECK: [0x05,0x00,0x08,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_hi
+// CHECK: [0x05,0x00,0x08,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], tba_lo
+// CHECK: [0x05,0x00,0x08,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], tba_hi
+// CHECK: [0x05,0x00,0x08,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], tma_lo
+// CHECK: [0x05,0x00,0x08,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], tma_hi
+// CHECK: [0x05,0x00,0x08,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], ttmp11
+// CHECK: [0x05,0x00,0x08,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], m0
+// CHECK: [0x05,0x00,0x08,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_lo
+// CHECK: [0x05,0x00,0x08,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_hi
+// CHECK: [0x05,0x00,0x08,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x08,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x08,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x08,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x08,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x08,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x08,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x08,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_lds_direct
+// CHECK: [0x05,0x00,0x08,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1 clamp
+// CHECK: [0x05,0x08,0x08,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1 mul:2
+// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_i32_e64 v[5:6], v1 mul:4
+// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_i32_e64 v[5:6], v1 div:2
+// CHECK: [0x05,0x00,0x08,0xd3,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_i32_e64 v5, v1
+// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v255, v1
+// CHECK: [0xff,0x00,0x0a,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v255
+// CHECK: [0x05,0x00,0x0a,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s1
+// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s103
+// CHECK: [0x05,0x00,0x0a,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0a,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0a,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x0a,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x0a,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x0a,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x0a,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x0a,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x0a,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x0a,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, m0
+// CHECK: [0x05,0x00,0x0a,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x0a,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x0a,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, 0
+// CHECK: [0x05,0x00,0x0a,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, -1
+// CHECK: [0x05,0x00,0x0a,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x0a,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x0a,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x0a,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x0a,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x0a,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x0a,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x0a,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_i32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_i32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x0a,0xd3,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_u32_e64 v5, v1
+// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v255, v1
+// CHECK: [0xff,0x00,0x0c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v255
+// CHECK: [0x05,0x00,0x0c,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s1
+// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s103
+// CHECK: [0x05,0x00,0x0c,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0c,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0c,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x0c,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x0c,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x0c,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x0c,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x0c,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x0c,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x0c,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, m0
+// CHECK: [0x05,0x00,0x0c,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x0c,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x0c,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, 0
+// CHECK: [0x05,0x00,0x0c,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, -1
+// CHECK: [0x05,0x00,0x0c,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x0c,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x0c,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x0c,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x0c,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x0c,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x0c,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x0c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_u32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_u32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x0c,0xd3,0x01,0x01,0x00,0x18]
+
+v_cvt_u32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x0e,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x0e,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x0e,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x0e,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x0e,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0e,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0e,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x0e,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x0e,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x0e,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x0e,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x0e,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x0e,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x0e,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x0e,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x0e,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x0e,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x0e,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x0e,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x0e,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x0e,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x0e,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x0e,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x0e,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x0e,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x0e,0xd3,0x01,0x01,0x00,0x20]
+
+v_cvt_u32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x0e,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x10,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x10,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x10,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x10,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x10,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x10,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x10,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x10,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x10,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x10,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x10,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x10,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x10,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x10,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x10,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x10,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x10,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x10,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x10,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x10,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x10,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x10,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x10,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x10,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x10,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x10,0xd3,0x01,0x01,0x00,0x20]
+
+v_cvt_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x10,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x14,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x14,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x14,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x14,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x14,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x14,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x14,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x14,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x14,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x14,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x14,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x14,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x14,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x14,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x14,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x14,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x14,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x14,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x14,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x14,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x14,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x14,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x14,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x14,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x14,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x14,0xd3,0x01,0x01,0x00,0x20]
+
+v_cvt_f16_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x14,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x16,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x16,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s103
+// CHECK: [0x05,0x00,0x16,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x16,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x16,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x16,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x16,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x16,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x16,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x16,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x16,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x16,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x16,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x16,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x16,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x16,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x16,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x16,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x16,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x16,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_f16_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_f16_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x16,0xd3,0x01,0x01,0x00,0x18]
+
+v_cvt_rpi_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x18,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x18,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x18,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x18,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x18,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x18,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x18,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x18,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x18,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x18,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x18,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x18,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x18,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x18,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x18,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x18,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x18,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x18,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x18,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x18,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x18,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x18,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x18,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x18,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x18,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x18,0xd3,0x01,0x01,0x00,0x20]
+
+v_cvt_rpi_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x18,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x1a,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x1a,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x1a,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x1a,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x1a,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x1a,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x1a,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x1a,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x1a,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x1a,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x1a,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x1a,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x1a,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x1a,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x1a,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x1a,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x1a,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x1a,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x1a,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x1a,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x1a,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x1a,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x1a,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x1a,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x1a,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x1a,0xd3,0x01,0x01,0x00,0x20]
+
+v_cvt_flr_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x1a,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1
+// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v255, v1
+// CHECK: [0xff,0x00,0x1c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v255
+// CHECK: [0x05,0x00,0x1c,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s1
+// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s103
+// CHECK: [0x05,0x00,0x1c,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x1c,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x1c,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x1c,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x1c,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x1c,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x1c,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x1c,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x1c,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x1c,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, m0
+// CHECK: [0x05,0x00,0x1c,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x1c,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x1c,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, 0
+// CHECK: [0x05,0x00,0x1c,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, -1
+// CHECK: [0x05,0x00,0x1c,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x1c,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x1c,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x1c,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x1c,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x1c,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x1c,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x1c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x01,0x00,0x08]
+
+v_cvt_off_f32_i4_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x01,0x00,0x10]
+
+v_cvt_off_f32_i4_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x1c,0xd3,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x1e,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x1e,0xd3,0xfe,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x1e,0xd3,0x02,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x1e,0xd3,0x04,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[102:103]
+// CHECK: [0x05,0x00,0x1e,0xd3,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x1e,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x1e,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, tba
+// CHECK: [0x05,0x00,0x1e,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, tma
+// CHECK: [0x05,0x00,0x1e,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, ttmp[10:11]
+// CHECK: [0x05,0x00,0x1e,0xd3,0x7a,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x1e,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x1e,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x1e,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x1e,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x1e,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x1e,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x1e,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x1e,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x20]
+
+v_cvt_f32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x1e,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[1:2] clamp
+// CHECK: [0x05,0x08,0x1e,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[1:2] mul:2
+// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_f64_e64 v5, v[1:2] mul:4
+// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_f64_e64 v5, v[1:2] div:2
+// CHECK: [0x05,0x00,0x1e,0xd3,0x01,0x01,0x00,0x18]
+
+v_cvt_f64_f32_e64 v[5:6], v1
+// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[254:255], v1
+// CHECK: [0xfe,0x00,0x20,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v255
+// CHECK: [0x05,0x00,0x20,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s1
+// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s103
+// CHECK: [0x05,0x00,0x20,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], flat_scratch_lo
+// CHECK: [0x05,0x00,0x20,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], flat_scratch_hi
+// CHECK: [0x05,0x00,0x20,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_lo
+// CHECK: [0x05,0x00,0x20,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_hi
+// CHECK: [0x05,0x00,0x20,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], tba_lo
+// CHECK: [0x05,0x00,0x20,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], tba_hi
+// CHECK: [0x05,0x00,0x20,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], tma_lo
+// CHECK: [0x05,0x00,0x20,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], tma_hi
+// CHECK: [0x05,0x00,0x20,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], ttmp11
+// CHECK: [0x05,0x00,0x20,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], m0
+// CHECK: [0x05,0x00,0x20,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_lo
+// CHECK: [0x05,0x00,0x20,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_hi
+// CHECK: [0x05,0x00,0x20,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x20,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x20,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x20,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x20,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x20,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x20,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x20,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_lds_direct
+// CHECK: [0x05,0x00,0x20,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -v1
+// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x20]
+
+v_cvt_f64_f32_e64 v[5:6], |v1|
+// CHECK: [0x05,0x01,0x20,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v1 clamp
+// CHECK: [0x05,0x08,0x20,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v1 mul:2
+// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_f32_e64 v[5:6], v1 mul:4
+// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_f32_e64 v[5:6], v1 div:2
+// CHECK: [0x05,0x00,0x20,0xd3,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte0_e64 v5, v1
+// CHECK: [0x05,0x00,0x22,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v255, v1
+// CHECK: [0xff,0x00,0x22,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v255
+// CHECK: [0x05,0x00,0x22,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s1
+// CHECK: [0x05,0x00,0x22,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s103
+// CHECK: [0x05,0x00,0x22,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x22,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x22,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x22,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x22,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x22,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x22,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x22,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x22,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x22,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, m0
+// CHECK: [0x05,0x00,0x22,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x22,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x22,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, 0
+// CHECK: [0x05,0x00,0x22,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, -1
+// CHECK: [0x05,0x00,0x22,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x22,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x22,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x22,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x22,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x22,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x22,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v1
+// CHECK: [0x05,0x00,0x24,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v255, v1
+// CHECK: [0xff,0x00,0x24,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v255
+// CHECK: [0x05,0x00,0x24,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s1
+// CHECK: [0x05,0x00,0x24,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s103
+// CHECK: [0x05,0x00,0x24,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x24,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x24,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x24,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x24,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x24,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x24,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x24,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x24,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x24,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, m0
+// CHECK: [0x05,0x00,0x24,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x24,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x24,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, 0
+// CHECK: [0x05,0x00,0x24,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, -1
+// CHECK: [0x05,0x00,0x24,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x24,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x24,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x24,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x24,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x24,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x24,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v1
+// CHECK: [0x05,0x00,0x26,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v255, v1
+// CHECK: [0xff,0x00,0x26,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v255
+// CHECK: [0x05,0x00,0x26,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s1
+// CHECK: [0x05,0x00,0x26,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s103
+// CHECK: [0x05,0x00,0x26,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x26,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x26,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x26,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x26,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x26,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x26,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x26,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x26,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x26,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, m0
+// CHECK: [0x05,0x00,0x26,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x26,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x26,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, 0
+// CHECK: [0x05,0x00,0x26,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, -1
+// CHECK: [0x05,0x00,0x26,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x26,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x26,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x26,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x26,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x26,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x26,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v1
+// CHECK: [0x05,0x00,0x28,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v255, v1
+// CHECK: [0xff,0x00,0x28,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v255
+// CHECK: [0x05,0x00,0x28,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s1
+// CHECK: [0x05,0x00,0x28,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s103
+// CHECK: [0x05,0x00,0x28,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x28,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x28,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x28,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x28,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x28,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x28,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x28,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x28,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x28,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, m0
+// CHECK: [0x05,0x00,0x28,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x28,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x28,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, 0
+// CHECK: [0x05,0x00,0x28,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, -1
+// CHECK: [0x05,0x00,0x28,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x28,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x28,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x28,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x28,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x28,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x28,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x2a,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x2a,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x2a,0xd3,0xfe,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x2a,0xd3,0x02,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x2a,0xd3,0x04,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[102:103]
+// CHECK: [0x05,0x00,0x2a,0xd3,0x66,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x2a,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x2a,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, tba
+// CHECK: [0x05,0x00,0x2a,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, tma
+// CHECK: [0x05,0x00,0x2a,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, ttmp[10:11]
+// CHECK: [0x05,0x00,0x2a,0xd3,0x7a,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x2a,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x2a,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x2a,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x2a,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x2a,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x2a,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x2a,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x2a,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x2a,0xd3,0x01,0x01,0x00,0x20]
+
+v_cvt_u32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x2a,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1
+// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[254:255], v1
+// CHECK: [0xfe,0x00,0x2c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v255
+// CHECK: [0x05,0x00,0x2c,0xd3,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s1
+// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s103
+// CHECK: [0x05,0x00,0x2c,0xd3,0x67,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], flat_scratch_lo
+// CHECK: [0x05,0x00,0x2c,0xd3,0x68,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], flat_scratch_hi
+// CHECK: [0x05,0x00,0x2c,0xd3,0x69,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_lo
+// CHECK: [0x05,0x00,0x2c,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_hi
+// CHECK: [0x05,0x00,0x2c,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], tba_lo
+// CHECK: [0x05,0x00,0x2c,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], tba_hi
+// CHECK: [0x05,0x00,0x2c,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], tma_lo
+// CHECK: [0x05,0x00,0x2c,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], tma_hi
+// CHECK: [0x05,0x00,0x2c,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], ttmp11
+// CHECK: [0x05,0x00,0x2c,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], m0
+// CHECK: [0x05,0x00,0x2c,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_lo
+// CHECK: [0x05,0x00,0x2c,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_hi
+// CHECK: [0x05,0x00,0x2c,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x2c,0xd3,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x2c,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x2c,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x2c,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x2c,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x2c,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x2c,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_lds_direct
+// CHECK: [0x05,0x00,0x2c,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1 clamp
+// CHECK: [0x05,0x08,0x2c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1 mul:2
+// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_u32_e64 v[5:6], v1 mul:4
+// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_u32_e64 v[5:6], v1 div:2
+// CHECK: [0x05,0x00,0x2c,0xd3,0x01,0x01,0x00,0x18]
+
+v_trunc_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x2e,0xd3,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x2e,0xd3,0xfe,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x2e,0xd3,0x02,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x2e,0xd3,0x04,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x2e,0xd3,0x66,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x2e,0xd3,0x68,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x2e,0xd3,0x6a,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x2e,0xd3,0x6c,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x2e,0xd3,0x6e,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x2e,0xd3,0x7a,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x2e,0xd3,0x7e,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x2e,0xd3,0x80,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x2e,0xd3,0xc1,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x2e,0xd3,0xf0,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x2e,0xd3,0xf7,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x2e,0xd3,0xfb,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x2e,0xd3,0xfc,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x2e,0xd3,0xfd,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x20]
+
+v_trunc_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x2e,0xd3,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x2e,0xd3,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x08]
+
+v_trunc_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x10]
+
+v_trunc_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x2e,0xd3,0x01,0x01,0x00,0x18]
+
+v_ceil_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x30,0xd3,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x30,0xd3,0xfe,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x30,0xd3,0x02,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x30,0xd3,0x04,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x30,0xd3,0x66,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x30,0xd3,0x68,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x30,0xd3,0x6a,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x30,0xd3,0x6c,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x30,0xd3,0x6e,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x30,0xd3,0x7a,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x30,0xd3,0x7e,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x30,0xd3,0x80,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x30,0xd3,0xc1,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x30,0xd3,0xf0,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x30,0xd3,0xf7,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x30,0xd3,0xfb,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x30,0xd3,0xfc,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x30,0xd3,0xfd,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x20]
+
+v_ceil_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x30,0xd3,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x30,0xd3,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x08]
+
+v_ceil_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x10]
+
+v_ceil_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x30,0xd3,0x01,0x01,0x00,0x18]
+
+v_rndne_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x32,0xd3,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x32,0xd3,0xfe,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x32,0xd3,0x02,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x32,0xd3,0x04,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x32,0xd3,0x66,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x32,0xd3,0x68,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x32,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x32,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x32,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x32,0xd3,0x7a,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x32,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x32,0xd3,0x80,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x32,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x32,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x32,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x32,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x32,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x32,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x20]
+
+v_rndne_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x32,0xd3,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x32,0xd3,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x08]
+
+v_rndne_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x10]
+
+v_rndne_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x32,0xd3,0x01,0x01,0x00,0x18]
+
+v_floor_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x34,0xd3,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x34,0xd3,0xfe,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x34,0xd3,0x02,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x34,0xd3,0x04,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x34,0xd3,0x66,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x34,0xd3,0x68,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x34,0xd3,0x6a,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x34,0xd3,0x6c,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x34,0xd3,0x6e,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x34,0xd3,0x7a,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x34,0xd3,0x7e,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x34,0xd3,0x80,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x34,0xd3,0xc1,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x34,0xd3,0xf0,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x34,0xd3,0xf7,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x34,0xd3,0xfb,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x34,0xd3,0xfc,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x34,0xd3,0xfd,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x20]
+
+v_floor_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x34,0xd3,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x34,0xd3,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x08]
+
+v_floor_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x10]
+
+v_floor_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x34,0xd3,0x01,0x01,0x00,0x18]
+
+v_fract_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x40,0xd3,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x40,0xd3,0xff,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x40,0xd3,0x67,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x40,0xd3,0x68,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x40,0xd3,0x69,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x40,0xd3,0x6a,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x40,0xd3,0x6b,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x40,0xd3,0x6c,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x40,0xd3,0x6d,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x40,0xd3,0x6e,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x40,0xd3,0x6f,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x40,0xd3,0x7b,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x40,0xd3,0x7c,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x40,0xd3,0x7e,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x40,0xd3,0x7f,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x40,0xd3,0x80,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x40,0xd3,0xc1,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x40,0xd3,0xf0,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x40,0xd3,0xf7,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x40,0xd3,0xfb,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x40,0xd3,0xfc,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x40,0xd3,0xfd,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x40,0xd3,0xfe,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x20]
+
+v_fract_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x40,0xd3,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x40,0xd3,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x08]
+
+v_fract_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x10]
+
+v_fract_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x40,0xd3,0x01,0x01,0x00,0x18]
+
+v_trunc_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x42,0xd3,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x42,0xd3,0xff,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x42,0xd3,0x67,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x42,0xd3,0x68,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x42,0xd3,0x69,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x42,0xd3,0x6a,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x42,0xd3,0x6b,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x42,0xd3,0x6c,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x42,0xd3,0x6d,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x42,0xd3,0x6e,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x42,0xd3,0x6f,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x42,0xd3,0x7b,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x42,0xd3,0x7c,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x42,0xd3,0x7e,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x42,0xd3,0x7f,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x42,0xd3,0x80,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x42,0xd3,0xc1,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x42,0xd3,0xf0,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x42,0xd3,0xf7,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x42,0xd3,0xfb,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x42,0xd3,0xfc,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x42,0xd3,0xfd,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x42,0xd3,0xfe,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x20]
+
+v_trunc_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x42,0xd3,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x42,0xd3,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x08]
+
+v_trunc_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x10]
+
+v_trunc_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x42,0xd3,0x01,0x01,0x00,0x18]
+
+v_ceil_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x44,0xd3,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x44,0xd3,0xff,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x44,0xd3,0x67,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x44,0xd3,0x68,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x44,0xd3,0x69,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x44,0xd3,0x6a,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x44,0xd3,0x6b,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x44,0xd3,0x6c,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x44,0xd3,0x6d,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x44,0xd3,0x6e,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x44,0xd3,0x6f,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x44,0xd3,0x7b,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x44,0xd3,0x7c,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x44,0xd3,0x7e,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x44,0xd3,0x7f,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x44,0xd3,0x80,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x44,0xd3,0xc1,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x44,0xd3,0xf0,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x44,0xd3,0xf7,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x44,0xd3,0xfb,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x44,0xd3,0xfc,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x44,0xd3,0xfd,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x44,0xd3,0xfe,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x20]
+
+v_ceil_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x44,0xd3,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x44,0xd3,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x08]
+
+v_ceil_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x10]
+
+v_ceil_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x44,0xd3,0x01,0x01,0x00,0x18]
+
+v_rndne_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x46,0xd3,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x46,0xd3,0xff,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x46,0xd3,0x67,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x46,0xd3,0x68,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x46,0xd3,0x69,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x46,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x46,0xd3,0x6b,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x46,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x46,0xd3,0x6d,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x46,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x46,0xd3,0x6f,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x46,0xd3,0x7b,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x46,0xd3,0x7c,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x46,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x46,0xd3,0x7f,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x46,0xd3,0x80,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x46,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x46,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x46,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x46,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x46,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x46,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x46,0xd3,0xfe,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x20]
+
+v_rndne_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x46,0xd3,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x46,0xd3,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x08]
+
+v_rndne_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x10]
+
+v_rndne_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x46,0xd3,0x01,0x01,0x00,0x18]
+
+v_floor_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x48,0xd3,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x48,0xd3,0xff,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x48,0xd3,0x67,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x48,0xd3,0x68,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x48,0xd3,0x69,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x48,0xd3,0x6a,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x48,0xd3,0x6b,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x48,0xd3,0x6c,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x48,0xd3,0x6d,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x48,0xd3,0x6e,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x48,0xd3,0x6f,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x48,0xd3,0x7b,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x48,0xd3,0x7c,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x48,0xd3,0x7e,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x48,0xd3,0x7f,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x48,0xd3,0x80,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x48,0xd3,0xc1,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x48,0xd3,0xf0,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x48,0xd3,0xf7,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x48,0xd3,0xfb,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x48,0xd3,0xfc,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x48,0xd3,0xfd,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x48,0xd3,0xfe,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x20]
+
+v_floor_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x48,0xd3,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x48,0xd3,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x08]
+
+v_floor_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x10]
+
+v_floor_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x48,0xd3,0x01,0x01,0x00,0x18]
+
+v_exp_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x4a,0xd3,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x4a,0xd3,0xff,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x4a,0xd3,0x67,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4a,0xd3,0x68,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4a,0xd3,0x69,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4a,0xd3,0x6a,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4a,0xd3,0x6b,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x4a,0xd3,0x6c,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x4a,0xd3,0x6d,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x4a,0xd3,0x6e,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x4a,0xd3,0x6f,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x4a,0xd3,0x7b,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x4a,0xd3,0x7c,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4a,0xd3,0x7e,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4a,0xd3,0x7f,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x4a,0xd3,0x80,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x4a,0xd3,0xc1,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4a,0xd3,0xf0,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4a,0xd3,0xf7,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4a,0xd3,0xfb,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4a,0xd3,0xfc,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4a,0xd3,0xfd,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4a,0xd3,0xfe,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x20]
+
+v_exp_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4a,0xd3,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x4a,0xd3,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x08]
+
+v_exp_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x10]
+
+v_exp_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x4a,0xd3,0x01,0x01,0x00,0x18]
+
+v_log_clamp_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_clamp_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x4c,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x4c,0xd3,0xff,0x01,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x4c,0xd3,0x67,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4c,0xd3,0x68,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4c,0xd3,0x69,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4c,0xd3,0x6a,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4c,0xd3,0x6b,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x4c,0xd3,0x6c,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x4c,0xd3,0x6d,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x4c,0xd3,0x6e,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x4c,0xd3,0x6f,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x4c,0xd3,0x7b,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x4c,0xd3,0x7c,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4c,0xd3,0x7e,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4c,0xd3,0x7f,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x4c,0xd3,0x80,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x4c,0xd3,0xc1,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4c,0xd3,0xf0,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4c,0xd3,0xf7,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4c,0xd3,0xfb,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4c,0xd3,0xfc,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4c,0xd3,0xfd,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4c,0xd3,0xfe,0x00,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x20]
+
+v_log_clamp_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4c,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x4c,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_clamp_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x08]
+
+v_log_clamp_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x10]
+
+v_log_clamp_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x4c,0xd3,0x01,0x01,0x00,0x18]
+
+v_log_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x4e,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x4e,0xd3,0xff,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x4e,0xd3,0x67,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4e,0xd3,0x68,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4e,0xd3,0x69,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4e,0xd3,0x6a,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4e,0xd3,0x6b,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x4e,0xd3,0x6c,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x4e,0xd3,0x6d,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x4e,0xd3,0x6e,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x4e,0xd3,0x6f,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x4e,0xd3,0x7b,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x4e,0xd3,0x7c,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4e,0xd3,0x7e,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4e,0xd3,0x7f,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x4e,0xd3,0x80,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x4e,0xd3,0xc1,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4e,0xd3,0xf0,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4e,0xd3,0xf7,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4e,0xd3,0xfb,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4e,0xd3,0xfc,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4e,0xd3,0xfd,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4e,0xd3,0xfe,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x20]
+
+v_log_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4e,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x4e,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x08]
+
+v_log_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x10]
+
+v_log_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x4e,0xd3,0x01,0x01,0x00,0x18]
+
+v_rcp_clamp_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x50,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x50,0xd3,0xff,0x01,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x50,0xd3,0x67,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x50,0xd3,0x68,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x50,0xd3,0x69,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x50,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x50,0xd3,0x6b,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x50,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x50,0xd3,0x6d,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x50,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x50,0xd3,0x6f,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x50,0xd3,0x7b,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x50,0xd3,0x7c,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x50,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x50,0xd3,0x7f,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x50,0xd3,0x80,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x50,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x50,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x50,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x50,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x50,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x50,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x50,0xd3,0xfe,0x00,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x20]
+
+v_rcp_clamp_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x50,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x50,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_clamp_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x08]
+
+v_rcp_clamp_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x10]
+
+v_rcp_clamp_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x50,0xd3,0x01,0x01,0x00,0x18]
+
+v_rcp_legacy_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x52,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x52,0xd3,0xff,0x01,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x52,0xd3,0x67,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x52,0xd3,0x68,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x52,0xd3,0x69,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x52,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x52,0xd3,0x6b,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x52,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x52,0xd3,0x6d,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x52,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x52,0xd3,0x6f,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x52,0xd3,0x7b,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x52,0xd3,0x7c,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x52,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x52,0xd3,0x7f,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x52,0xd3,0x80,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x52,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x52,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x52,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x52,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x52,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x52,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x52,0xd3,0xfe,0x00,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x20]
+
+v_rcp_legacy_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x52,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x52,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_legacy_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x08]
+
+v_rcp_legacy_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x10]
+
+v_rcp_legacy_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x52,0xd3,0x01,0x01,0x00,0x18]
+
+v_rcp_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x54,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x54,0xd3,0xff,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x54,0xd3,0x67,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x54,0xd3,0x68,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x54,0xd3,0x69,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x54,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x54,0xd3,0x6b,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x54,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x54,0xd3,0x6d,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x54,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x54,0xd3,0x6f,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x54,0xd3,0x7b,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x54,0xd3,0x7c,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x54,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x54,0xd3,0x7f,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x54,0xd3,0x80,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x54,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x54,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x54,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x54,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x54,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x54,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x54,0xd3,0xfe,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x20]
+
+v_rcp_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x54,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x54,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x08]
+
+v_rcp_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x10]
+
+v_rcp_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x54,0xd3,0x01,0x01,0x00,0x18]
+
+v_rcp_iflag_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x56,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x56,0xd3,0xff,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x56,0xd3,0x67,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x56,0xd3,0x68,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x56,0xd3,0x69,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x56,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x56,0xd3,0x6b,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x56,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x56,0xd3,0x6d,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x56,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x56,0xd3,0x6f,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x56,0xd3,0x7b,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x56,0xd3,0x7c,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x56,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x56,0xd3,0x7f,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x56,0xd3,0x80,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x56,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x56,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x56,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x56,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x56,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x56,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x56,0xd3,0xfe,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x20]
+
+v_rcp_iflag_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x56,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x56,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x08]
+
+v_rcp_iflag_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x10]
+
+v_rcp_iflag_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x56,0xd3,0x01,0x01,0x00,0x18]
+
+v_rsq_clamp_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x58,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x58,0xd3,0xff,0x01,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x58,0xd3,0x67,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x58,0xd3,0x68,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x58,0xd3,0x69,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x58,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x58,0xd3,0x6b,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x58,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x58,0xd3,0x6d,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x58,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x58,0xd3,0x6f,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x58,0xd3,0x7b,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x58,0xd3,0x7c,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x58,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x58,0xd3,0x7f,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x58,0xd3,0x80,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x58,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x58,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x58,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x58,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x58,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x58,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x58,0xd3,0xfe,0x00,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x20]
+
+v_rsq_clamp_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x58,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x58,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_clamp_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x08]
+
+v_rsq_clamp_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x10]
+
+v_rsq_clamp_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x58,0xd3,0x01,0x01,0x00,0x18]
+
+v_rsq_legacy_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5a,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5a,0xd3,0xff,0x01,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x5a,0xd3,0x67,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5a,0xd3,0x68,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5a,0xd3,0x69,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5a,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5a,0xd3,0x6b,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x5a,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x5a,0xd3,0x6d,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x5a,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x5a,0xd3,0x6f,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x5a,0xd3,0x7b,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5a,0xd3,0x7c,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5a,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5a,0xd3,0x7f,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5a,0xd3,0x80,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5a,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5a,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5a,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5a,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5a,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5a,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5a,0xd3,0xfe,0x00,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x20]
+
+v_rsq_legacy_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5a,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x5a,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_legacy_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x08]
+
+v_rsq_legacy_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x10]
+
+v_rsq_legacy_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5a,0xd3,0x01,0x01,0x00,0x18]
+
+v_rsq_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5c,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5c,0xd3,0xff,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x5c,0xd3,0x67,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5c,0xd3,0x68,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5c,0xd3,0x69,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5c,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5c,0xd3,0x6b,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x5c,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x5c,0xd3,0x6d,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x5c,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x5c,0xd3,0x6f,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x5c,0xd3,0x7b,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5c,0xd3,0x7c,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5c,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5c,0xd3,0x7f,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5c,0xd3,0x80,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5c,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5c,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5c,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5c,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5c,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5c,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5c,0xd3,0xfe,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x20]
+
+v_rsq_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5c,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x5c,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x08]
+
+v_rsq_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x10]
+
+v_rsq_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5c,0xd3,0x01,0x01,0x00,0x18]
+
+v_rcp_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x5e,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x5e,0xd3,0xfe,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x5e,0xd3,0x02,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x5e,0xd3,0x04,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x5e,0xd3,0x66,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x5e,0xd3,0x68,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x5e,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x5e,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x5e,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x5e,0xd3,0x7a,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x5e,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x5e,0xd3,0x80,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x5e,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x5e,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x5e,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x5e,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x5e,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x5e,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x20]
+
+v_rcp_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x5e,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x5e,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x08]
+
+v_rcp_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x10]
+
+v_rcp_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x5e,0xd3,0x01,0x01,0x00,0x18]
+
+v_rcp_clamp_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x60,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x60,0xd3,0xfe,0x01,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x60,0xd3,0x02,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x60,0xd3,0x04,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x60,0xd3,0x66,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x60,0xd3,0x68,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x60,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x60,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x60,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x60,0xd3,0x7a,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x60,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x60,0xd3,0x80,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x60,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x60,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x60,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x60,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x60,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x60,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x20]
+
+v_rcp_clamp_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x60,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x60,0xd3,0x01,0x01,0x00,0x00]
+
+v_rcp_clamp_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x08]
+
+v_rcp_clamp_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x10]
+
+v_rcp_clamp_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x60,0xd3,0x01,0x01,0x00,0x18]
+
+v_rsq_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x62,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x62,0xd3,0xfe,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x62,0xd3,0x02,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x62,0xd3,0x04,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x62,0xd3,0x66,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x62,0xd3,0x68,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x62,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x62,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x62,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x62,0xd3,0x7a,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x62,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x62,0xd3,0x80,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x62,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x62,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x62,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x62,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x62,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x62,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x20]
+
+v_rsq_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x62,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x62,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x08]
+
+v_rsq_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x10]
+
+v_rsq_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x62,0xd3,0x01,0x01,0x00,0x18]
+
+v_rsq_clamp_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x64,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x64,0xd3,0xfe,0x01,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x64,0xd3,0x02,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x64,0xd3,0x04,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x64,0xd3,0x66,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x64,0xd3,0x68,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x64,0xd3,0x6a,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x64,0xd3,0x6c,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x64,0xd3,0x6e,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x64,0xd3,0x7a,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x64,0xd3,0x7e,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x64,0xd3,0x80,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x64,0xd3,0xc1,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x64,0xd3,0xf0,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x64,0xd3,0xf7,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x64,0xd3,0xfb,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x64,0xd3,0xfc,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x64,0xd3,0xfd,0x00,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x20]
+
+v_rsq_clamp_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x64,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x64,0xd3,0x01,0x01,0x00,0x00]
+
+v_rsq_clamp_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x08]
+
+v_rsq_clamp_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x10]
+
+v_rsq_clamp_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x64,0xd3,0x01,0x01,0x00,0x18]
+
+v_sqrt_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x66,0xd3,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x66,0xd3,0xff,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x66,0xd3,0x67,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x66,0xd3,0x68,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x66,0xd3,0x69,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x66,0xd3,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x66,0xd3,0x6b,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x66,0xd3,0x6c,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x66,0xd3,0x6d,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x66,0xd3,0x6e,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x66,0xd3,0x6f,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x66,0xd3,0x7b,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x66,0xd3,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x66,0xd3,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x66,0xd3,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x66,0xd3,0x80,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x66,0xd3,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x66,0xd3,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x66,0xd3,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x66,0xd3,0xfb,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x66,0xd3,0xfc,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x66,0xd3,0xfd,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x66,0xd3,0xfe,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x20]
+
+v_sqrt_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x66,0xd3,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x66,0xd3,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x08]
+
+v_sqrt_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x10]
+
+v_sqrt_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x66,0xd3,0x01,0x01,0x00,0x18]
+
+v_sqrt_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x68,0xd3,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x68,0xd3,0xfe,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x68,0xd3,0x02,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x68,0xd3,0x04,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x68,0xd3,0x66,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x68,0xd3,0x68,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x68,0xd3,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x68,0xd3,0x6c,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x68,0xd3,0x6e,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x68,0xd3,0x7a,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x68,0xd3,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x68,0xd3,0x80,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x68,0xd3,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x68,0xd3,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x68,0xd3,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x68,0xd3,0xfb,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x68,0xd3,0xfc,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x68,0xd3,0xfd,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x20]
+
+v_sqrt_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x68,0xd3,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x68,0xd3,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x08]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x10]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x68,0xd3,0x01,0x01,0x00,0x18]
+
+v_sin_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6a,0xd3,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6a,0xd3,0xff,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x6a,0xd3,0x67,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6a,0xd3,0x68,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6a,0xd3,0x69,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6a,0xd3,0x6a,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6a,0xd3,0x6b,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x6a,0xd3,0x6c,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x6a,0xd3,0x6d,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x6a,0xd3,0x6e,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x6a,0xd3,0x6f,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x6a,0xd3,0x7b,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6a,0xd3,0x7c,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6a,0xd3,0x7e,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6a,0xd3,0x7f,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6a,0xd3,0x80,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6a,0xd3,0xc1,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6a,0xd3,0xf0,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6a,0xd3,0xf7,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6a,0xd3,0xfb,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6a,0xd3,0xfc,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6a,0xd3,0xfd,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6a,0xd3,0xfe,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x20]
+
+v_sin_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x6a,0xd3,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x6a,0xd3,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x08]
+
+v_sin_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x10]
+
+v_sin_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x6a,0xd3,0x01,0x01,0x00,0x18]
+
+v_cos_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6c,0xd3,0xff,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x6c,0xd3,0x67,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6c,0xd3,0x68,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6c,0xd3,0x69,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6c,0xd3,0x6a,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6c,0xd3,0x6b,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x6c,0xd3,0x6c,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x6c,0xd3,0x6d,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x6c,0xd3,0x6e,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x6c,0xd3,0x6f,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x6c,0xd3,0x7b,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6c,0xd3,0x7c,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6c,0xd3,0x7e,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6c,0xd3,0x7f,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6c,0xd3,0x80,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6c,0xd3,0xc1,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6c,0xd3,0xf0,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6c,0xd3,0xf7,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6c,0xd3,0xfb,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6c,0xd3,0xfc,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6c,0xd3,0xfd,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6c,0xd3,0xfe,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x20]
+
+v_cos_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x6c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x6c,0xd3,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x08]
+
+v_cos_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x10]
+
+v_cos_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x6c,0xd3,0x01,0x01,0x00,0x18]
+
+v_not_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6e,0xd3,0x01,0x01,0x00,0x00]
+
+v_not_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6e,0xd3,0x01,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6e,0xd3,0xff,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6e,0xd3,0x01,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, s103
+// CHECK: [0x05,0x00,0x6e,0xd3,0x67,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6e,0xd3,0x68,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6e,0xd3,0x69,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6e,0xd3,0x6a,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6e,0xd3,0x6b,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x6e,0xd3,0x6c,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x6e,0xd3,0x6d,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x6e,0xd3,0x6e,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x6e,0xd3,0x6f,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x6e,0xd3,0x7b,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6e,0xd3,0x7c,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6e,0xd3,0x7e,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6e,0xd3,0x7f,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6e,0xd3,0x80,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6e,0xd3,0xc1,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6e,0xd3,0xf0,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6e,0xd3,0xf7,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6e,0xd3,0xfb,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6e,0xd3,0xfc,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6e,0xd3,0xfd,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6e,0xd3,0xfe,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x70,0xd3,0x01,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x70,0xd3,0x01,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x70,0xd3,0xff,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x70,0xd3,0x01,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s103
+// CHECK: [0x05,0x00,0x70,0xd3,0x67,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x70,0xd3,0x68,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x70,0xd3,0x69,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x70,0xd3,0x6a,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x70,0xd3,0x6b,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x70,0xd3,0x6c,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x70,0xd3,0x6d,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x70,0xd3,0x6e,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x70,0xd3,0x6f,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x70,0xd3,0x7b,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x70,0xd3,0x7c,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x70,0xd3,0x7e,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x70,0xd3,0x7f,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x70,0xd3,0x80,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x70,0xd3,0xc1,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x70,0xd3,0xf0,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x70,0xd3,0xf7,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x70,0xd3,0xfb,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x70,0xd3,0xfc,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x70,0xd3,0xfd,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x70,0xd3,0xfe,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, v1
+// CHECK: [0x05,0x00,0x72,0xd3,0x01,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v255, v1
+// CHECK: [0xff,0x00,0x72,0xd3,0x01,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, v255
+// CHECK: [0x05,0x00,0x72,0xd3,0xff,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s1
+// CHECK: [0x05,0x00,0x72,0xd3,0x01,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s103
+// CHECK: [0x05,0x00,0x72,0xd3,0x67,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x72,0xd3,0x68,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x72,0xd3,0x69,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x72,0xd3,0x6a,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x72,0xd3,0x6b,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x72,0xd3,0x6c,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x72,0xd3,0x6d,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x72,0xd3,0x6e,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x72,0xd3,0x6f,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x72,0xd3,0x7b,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, m0
+// CHECK: [0x05,0x00,0x72,0xd3,0x7c,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x72,0xd3,0x7e,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x72,0xd3,0x7f,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, 0
+// CHECK: [0x05,0x00,0x72,0xd3,0x80,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, -1
+// CHECK: [0x05,0x00,0x72,0xd3,0xc1,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x72,0xd3,0xf0,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x72,0xd3,0xf7,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x72,0xd3,0xfb,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x72,0xd3,0xfc,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x72,0xd3,0xfd,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x72,0xd3,0xfe,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x74,0xd3,0x01,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x74,0xd3,0x01,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x74,0xd3,0xff,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x74,0xd3,0x01,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s103
+// CHECK: [0x05,0x00,0x74,0xd3,0x67,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x74,0xd3,0x68,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x74,0xd3,0x69,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x74,0xd3,0x6a,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x74,0xd3,0x6b,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x74,0xd3,0x6c,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x74,0xd3,0x6d,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x74,0xd3,0x6e,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x74,0xd3,0x6f,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x74,0xd3,0x7b,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x74,0xd3,0x7c,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x74,0xd3,0x7e,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x74,0xd3,0x7f,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x74,0xd3,0x80,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x74,0xd3,0xc1,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x74,0xd3,0xf0,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x74,0xd3,0xf7,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x74,0xd3,0xfb,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x74,0xd3,0xfc,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x74,0xd3,0xfd,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x74,0xd3,0xfe,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, v1
+// CHECK: [0x05,0x00,0x76,0xd3,0x01,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v255, v1
+// CHECK: [0xff,0x00,0x76,0xd3,0x01,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, v255
+// CHECK: [0x05,0x00,0x76,0xd3,0xff,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s1
+// CHECK: [0x05,0x00,0x76,0xd3,0x01,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s103
+// CHECK: [0x05,0x00,0x76,0xd3,0x67,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x76,0xd3,0x68,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x76,0xd3,0x69,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x76,0xd3,0x6a,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x76,0xd3,0x6b,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x76,0xd3,0x6c,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x76,0xd3,0x6d,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x76,0xd3,0x6e,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x76,0xd3,0x6f,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x76,0xd3,0x7b,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, m0
+// CHECK: [0x05,0x00,0x76,0xd3,0x7c,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x76,0xd3,0x7e,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x76,0xd3,0x7f,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, 0
+// CHECK: [0x05,0x00,0x76,0xd3,0x80,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, -1
+// CHECK: [0x05,0x00,0x76,0xd3,0xc1,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x76,0xd3,0xf0,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x76,0xd3,0xf7,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x76,0xd3,0xfb,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x76,0xd3,0xfc,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x76,0xd3,0xfd,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x76,0xd3,0xfe,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x78,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x78,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x78,0xd3,0xfe,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x78,0xd3,0x02,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x78,0xd3,0x04,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[102:103]
+// CHECK: [0x05,0x00,0x78,0xd3,0x66,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x78,0xd3,0x68,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x78,0xd3,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, tba
+// CHECK: [0x05,0x00,0x78,0xd3,0x6c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, tma
+// CHECK: [0x05,0x00,0x78,0xd3,0x6e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, ttmp[10:11]
+// CHECK: [0x05,0x00,0x78,0xd3,0x7a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x78,0xd3,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x78,0xd3,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x78,0xd3,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x78,0xd3,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x78,0xd3,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x78,0xd3,0xfb,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x78,0xd3,0xfc,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x78,0xd3,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x78,0xd3,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x78,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x7a,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x7a,0xd3,0xfe,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x7a,0xd3,0x02,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x7a,0xd3,0x04,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x7a,0xd3,0x66,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x7a,0xd3,0x68,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x7a,0xd3,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x7a,0xd3,0x6c,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x7a,0xd3,0x6e,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x7a,0xd3,0x7a,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x7a,0xd3,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x7a,0xd3,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x7a,0xd3,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x7a,0xd3,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x7a,0xd3,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x7a,0xd3,0xfb,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x7a,0xd3,0xfc,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x7a,0xd3,0xfd,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x7a,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x7a,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x08]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x10]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x7a,0xd3,0x01,0x01,0x00,0x18]
+
+v_fract_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x7c,0xd3,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x7c,0xd3,0xfe,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x7c,0xd3,0x02,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x7c,0xd3,0x04,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[102:103]
+// CHECK: [0x05,0x00,0x7c,0xd3,0x66,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x7c,0xd3,0x68,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x7c,0xd3,0x6a,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x7c,0xd3,0x6c,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x7c,0xd3,0x6e,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x7c,0xd3,0x7a,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x7c,0xd3,0x7e,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x7c,0xd3,0x80,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x7c,0xd3,0xc1,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x7c,0xd3,0xf0,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x7c,0xd3,0xf7,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x7c,0xd3,0xfb,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x7c,0xd3,0xfc,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x7c,0xd3,0xfd,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x20]
+
+v_fract_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x7c,0xd3,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x08,0x7c,0xd3,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x08]
+
+v_fract_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x10]
+
+v_fract_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x7c,0xd3,0x01,0x01,0x00,0x18]
+
+v_frexp_exp_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x7e,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x7e,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x7e,0xd3,0xff,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x7e,0xd3,0x01,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x7e,0xd3,0x67,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7e,0xd3,0x68,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7e,0xd3,0x69,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7e,0xd3,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7e,0xd3,0x6b,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x7e,0xd3,0x6c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x7e,0xd3,0x6d,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x7e,0xd3,0x6e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x7e,0xd3,0x6f,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x7e,0xd3,0x7b,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x7e,0xd3,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7e,0xd3,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7e,0xd3,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x7e,0xd3,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x7e,0xd3,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7e,0xd3,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7e,0xd3,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7e,0xd3,0xfb,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7e,0xd3,0xfc,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7e,0xd3,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7e,0xd3,0xfe,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x80,0xd3,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x80,0xd3,0xff,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x80,0xd3,0x67,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x80,0xd3,0x68,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x80,0xd3,0x69,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x80,0xd3,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x80,0xd3,0x6b,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x80,0xd3,0x6c,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x80,0xd3,0x6d,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x80,0xd3,0x6e,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x80,0xd3,0x6f,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x80,0xd3,0x7b,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x80,0xd3,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x80,0xd3,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x80,0xd3,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x80,0xd3,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x80,0xd3,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x80,0xd3,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x80,0xd3,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x80,0xd3,0xfb,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x80,0xd3,0xfc,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x80,0xd3,0xfd,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x80,0xd3,0xfe,0x00,0x00,0x00]
+
+v_clrexcp_e64
+// CHECK: [0x00,0x00,0x82,0xd3,0x00,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x84,0xd3,0x01,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x84,0xd3,0xff,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x84,0xd3,0x7c,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x84,0xd3,0x80,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x84,0xd3,0xc1,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x84,0xd3,0xf0,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x84,0xd3,0xf7,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x84,0xd3,0xfe,0x00,0x00,0x00]
+
+v_movrels_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x01,0x00,0x00]
+
+v_movrels_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x86,0xd3,0x01,0x01,0x00,0x00]
+
+v_movrels_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x86,0xd3,0xff,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x88,0xd3,0x01,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x88,0xd3,0xff,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x8a,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x8a,0xd3,0xff,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x8a,0xd3,0x67,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8a,0xd3,0x68,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8a,0xd3,0x69,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8a,0xd3,0x6a,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8a,0xd3,0x6b,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x8a,0xd3,0x6c,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x8a,0xd3,0x6d,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x8a,0xd3,0x6e,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x8a,0xd3,0x6f,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x8a,0xd3,0x7b,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x8a,0xd3,0x7c,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8a,0xd3,0x7e,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8a,0xd3,0x7f,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x8a,0xd3,0x80,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x8a,0xd3,0xc1,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8a,0xd3,0xf0,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8a,0xd3,0xf7,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8a,0xd3,0xfb,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8a,0xd3,0xfc,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8a,0xd3,0xfd,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8a,0xd3,0xfe,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x20]
+
+v_log_legacy_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8a,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x8a,0xd3,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x08]
+
+v_log_legacy_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x10]
+
+v_log_legacy_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x00,0x18]
+
+v_exp_legacy_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x8c,0xd3,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x8c,0xd3,0xff,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, s103
+// CHECK: [0x05,0x00,0x8c,0xd3,0x67,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8c,0xd3,0x68,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8c,0xd3,0x69,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8c,0xd3,0x6a,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8c,0xd3,0x6b,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x8c,0xd3,0x6c,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x8c,0xd3,0x6d,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x8c,0xd3,0x6e,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x8c,0xd3,0x6f,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x8c,0xd3,0x7b,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x8c,0xd3,0x7c,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8c,0xd3,0x7e,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8c,0xd3,0x7f,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x8c,0xd3,0x80,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x8c,0xd3,0xc1,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8c,0xd3,0xf0,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8c,0xd3,0xf7,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8c,0xd3,0xfb,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8c,0xd3,0xfc,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8c,0xd3,0xfd,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8c,0xd3,0xfe,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x20]
+
+v_exp_legacy_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8c,0xd3,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x08,0x8c,0xd3,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x08]
+
+v_exp_legacy_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x10]
+
+v_exp_legacy_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x00,0x18]
+
+v_cndmask_b32_e64 v5, v1, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x1a,0x00]
+
+v_cndmask_b32_e64 v255, v1, v2, s[6:7]
+// CHECK: [0xff,0x00,0x00,0xd2,0x01,0x05,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, v255, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0xff,0x05,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, 0, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0x80,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, -1, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0xc1,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, 0.5, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0xf0,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, -4.0, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0xf7,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, src_lds_direct, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0xfe,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, v1, v255, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xff,0x1b,0x00]
+
+v_cndmask_b32_e64 v5, v1, 0, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x01,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, -1, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x83,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, 0.5, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xe1,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, -4.0, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xef,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, v2, s[8:9]
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x22,0x00]
+
+v_cndmask_b32_e64 v5, v1, v2, s[102:103]
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x9a,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, flat_scratch
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xa2,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, vcc
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xaa,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, tba
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xb2,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, tma
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xba,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xea,0x01]
+
+v_add_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x06,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0xff,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x67,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x68,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x69,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x6a,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x6b,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x6c,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x6d,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x6e,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x6f,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x7b,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x7c,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x7e,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x7f,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x80,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0xc1,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0xf0,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0xf7,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0xfb,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0xfc,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0xfd,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0xfe,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xff,0x03,0x00]
+
+v_add_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x00,0x00]
+
+v_add_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xcf,0x00,0x00]
+
+v_add_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd1,0x00,0x00]
+
+v_add_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd3,0x00,0x00]
+
+v_add_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd5,0x00,0x00]
+
+v_add_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd7,0x00,0x00]
+
+v_add_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd9,0x00,0x00]
+
+v_add_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xdb,0x00,0x00]
+
+v_add_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xdd,0x00,0x00]
+
+v_add_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xdf,0x00,0x00]
+
+v_add_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf7,0x00,0x00]
+
+v_add_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf9,0x00,0x00]
+
+v_add_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xfd,0x00,0x00]
+
+v_add_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xff,0x00,0x00]
+
+v_add_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x01,0x01,0x00]
+
+v_add_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x83,0x01,0x00]
+
+v_add_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xe1,0x01,0x00]
+
+v_add_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xef,0x01,0x00]
+
+v_add_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf7,0x01,0x00]
+
+v_add_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf9,0x01,0x00]
+
+v_add_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xfb,0x01,0x00]
+
+v_add_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x20]
+
+v_add_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x40]
+
+v_add_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x60]
+
+v_add_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x06,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x06,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x06,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x06,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x08]
+
+v_add_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x10]
+
+v_add_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x18]
+
+v_sub_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x08,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0xff,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x67,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x68,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x69,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x6a,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x6b,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x6c,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x6d,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x6e,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x6f,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x7b,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x7c,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x7e,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x7f,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x80,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0xc1,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0xf0,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0xf7,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0xfb,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0xfc,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0xfd,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0xfe,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xff,0x03,0x00]
+
+v_sub_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xcf,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd1,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd3,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd5,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd7,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xd9,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xdb,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xdd,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xdf,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xf7,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xf9,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xfd,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xff,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x01,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x83,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xe1,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xef,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xf7,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xf9,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0xfb,0x01,0x00]
+
+v_sub_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x20]
+
+v_sub_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x40]
+
+v_sub_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x60]
+
+v_sub_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x08,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x08,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x08,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x08,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x08]
+
+v_sub_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x10]
+
+v_sub_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x08,0xd2,0x01,0x05,0x02,0x18]
+
+v_subrev_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0a,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0xff,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x67,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x68,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x69,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x6a,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x6b,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x6c,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x6d,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x6e,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x6f,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x7b,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x7c,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x7e,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x7f,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x80,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0xc1,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0xf0,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0xf7,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0xfb,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0xfc,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0xfd,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xff,0x03,0x00]
+
+v_subrev_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xcf,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd1,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd3,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd5,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd7,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xd9,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xdb,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xdd,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xdf,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xf7,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xf9,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xfd,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xff,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x01,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x83,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xe1,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xef,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xf7,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xf9,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0xfb,0x01,0x00]
+
+v_subrev_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x20]
+
+v_subrev_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x40]
+
+v_subrev_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x60]
+
+v_subrev_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x0a,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x0a,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x0a,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x0a,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x08]
+
+v_subrev_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x10]
+
+v_subrev_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x0a,0xd2,0x01,0x05,0x02,0x18]
+
+v_mac_legacy_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0xff,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x67,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x68,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x69,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x80,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xff,0x03,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xff,0x00,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x01,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x83,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xef,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mac_legacy_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x20]
+
+v_mac_legacy_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x40]
+
+v_mac_legacy_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x60]
+
+v_mac_legacy_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x0c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x0c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x0c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x0c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_legacy_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x08]
+
+v_mac_legacy_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x10]
+
+v_mac_legacy_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x0c,0xd2,0x01,0x05,0x02,0x18]
+
+v_mul_legacy_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x20]
+
+v_mul_legacy_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x40]
+
+v_mul_legacy_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x60]
+
+v_mul_legacy_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x0e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x0e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x0e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x0e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x08]
+
+v_mul_legacy_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x10]
+
+v_mul_legacy_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x0e,0xd2,0x01,0x05,0x02,0x18]
+
+v_mul_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x10,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x20]
+
+v_mul_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x40]
+
+v_mul_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x60]
+
+v_mul_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x10,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x10,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x10,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x10,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x08]
+
+v_mul_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x10]
+
+v_mul_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x10,0xd2,0x01,0x05,0x02,0x18]
+
+v_mul_i32_i24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x12,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x12,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_i32_i24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x12,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x14,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x14,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x14,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x16,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x16,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_u32_u24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x16,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x18,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x18,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x18,0xd2,0x01,0xfb,0x01,0x00]
+
+v_min_legacy_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_legacy_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x1a,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0xff,0x05,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x67,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x68,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x69,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x6a,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x6b,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x6c,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x6d,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x6e,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x6f,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x7b,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x7c,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x7e,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x7f,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x80,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0xc1,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0xf0,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0xf7,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0xfb,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0xfc,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0xfd,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0xfe,0x04,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xff,0x03,0x00]
+
+v_min_legacy_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xcf,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd1,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd3,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd5,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd7,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xd9,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xdb,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xdd,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xdf,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xf7,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xf9,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xfd,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xff,0x00,0x00]
+
+v_min_legacy_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x01,0x01,0x00]
+
+v_min_legacy_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x83,0x01,0x00]
+
+v_min_legacy_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xe1,0x01,0x00]
+
+v_min_legacy_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xef,0x01,0x00]
+
+v_min_legacy_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xf7,0x01,0x00]
+
+v_min_legacy_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xf9,0x01,0x00]
+
+v_min_legacy_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0xfb,0x01,0x00]
+
+v_min_legacy_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x20]
+
+v_min_legacy_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x40]
+
+v_min_legacy_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x60]
+
+v_min_legacy_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x1a,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x1a,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x1a,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x1a,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_legacy_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x08]
+
+v_min_legacy_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x10]
+
+v_min_legacy_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x1a,0xd2,0x01,0x05,0x02,0x18]
+
+v_max_legacy_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_legacy_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x1c,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0xff,0x05,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x67,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x68,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x69,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x6a,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x6b,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x6c,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x6d,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x6e,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x6f,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x7b,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x7c,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x7e,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x7f,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x80,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0xc1,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0xf0,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0xf7,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0xfb,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0xfc,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0xfd,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0xfe,0x04,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xff,0x03,0x00]
+
+v_max_legacy_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xcf,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd1,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd3,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd5,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd7,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xd9,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xdb,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xdd,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xdf,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xf7,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xf9,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xfd,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xff,0x00,0x00]
+
+v_max_legacy_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x01,0x01,0x00]
+
+v_max_legacy_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x83,0x01,0x00]
+
+v_max_legacy_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xe1,0x01,0x00]
+
+v_max_legacy_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xef,0x01,0x00]
+
+v_max_legacy_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xf7,0x01,0x00]
+
+v_max_legacy_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xf9,0x01,0x00]
+
+v_max_legacy_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0xfb,0x01,0x00]
+
+v_max_legacy_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x20]
+
+v_max_legacy_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x40]
+
+v_max_legacy_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x60]
+
+v_max_legacy_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x1c,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x1c,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x1c,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x1c,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_legacy_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x08]
+
+v_max_legacy_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x10]
+
+v_max_legacy_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x1c,0xd2,0x01,0x05,0x02,0x18]
+
+v_min_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x1e,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0xff,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x67,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x68,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x69,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x6a,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x6b,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x6c,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x6d,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x6e,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x6f,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x7b,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x7c,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x7e,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x7f,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x80,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0xc1,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0xf0,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0xf7,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0xfb,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0xfc,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0xfd,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0xfe,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xff,0x03,0x00]
+
+v_min_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x00,0x00]
+
+v_min_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xcf,0x00,0x00]
+
+v_min_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd1,0x00,0x00]
+
+v_min_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd3,0x00,0x00]
+
+v_min_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd5,0x00,0x00]
+
+v_min_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd7,0x00,0x00]
+
+v_min_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xd9,0x00,0x00]
+
+v_min_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xdb,0x00,0x00]
+
+v_min_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xdd,0x00,0x00]
+
+v_min_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xdf,0x00,0x00]
+
+v_min_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xf7,0x00,0x00]
+
+v_min_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xf9,0x00,0x00]
+
+v_min_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xfd,0x00,0x00]
+
+v_min_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xff,0x00,0x00]
+
+v_min_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x01,0x01,0x00]
+
+v_min_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x83,0x01,0x00]
+
+v_min_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xe1,0x01,0x00]
+
+v_min_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xef,0x01,0x00]
+
+v_min_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xf7,0x01,0x00]
+
+v_min_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xf9,0x01,0x00]
+
+v_min_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0xfb,0x01,0x00]
+
+v_min_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x20]
+
+v_min_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x40]
+
+v_min_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x60]
+
+v_min_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x1e,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x1e,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x1e,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x1e,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x08]
+
+v_min_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x10]
+
+v_min_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x1e,0xd2,0x01,0x05,0x02,0x18]
+
+v_max_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x20,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0xff,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x67,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x68,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x69,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x6a,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x6b,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x6c,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x6d,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x6e,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x6f,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x7b,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x7c,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x7e,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x7f,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x80,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0xc1,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0xf0,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0xf7,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0xfb,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0xfc,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0xfd,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0xfe,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xff,0x03,0x00]
+
+v_max_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x00,0x00]
+
+v_max_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xcf,0x00,0x00]
+
+v_max_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd1,0x00,0x00]
+
+v_max_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd3,0x00,0x00]
+
+v_max_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd5,0x00,0x00]
+
+v_max_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd7,0x00,0x00]
+
+v_max_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xd9,0x00,0x00]
+
+v_max_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xdb,0x00,0x00]
+
+v_max_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xdd,0x00,0x00]
+
+v_max_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xdf,0x00,0x00]
+
+v_max_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xf7,0x00,0x00]
+
+v_max_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xf9,0x00,0x00]
+
+v_max_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xfd,0x00,0x00]
+
+v_max_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xff,0x00,0x00]
+
+v_max_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x01,0x01,0x00]
+
+v_max_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x83,0x01,0x00]
+
+v_max_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xe1,0x01,0x00]
+
+v_max_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xef,0x01,0x00]
+
+v_max_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xf7,0x01,0x00]
+
+v_max_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xf9,0x01,0x00]
+
+v_max_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0xfb,0x01,0x00]
+
+v_max_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x20]
+
+v_max_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x40]
+
+v_max_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x60]
+
+v_max_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x20,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x20,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x20,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x20,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x08]
+
+v_max_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x10]
+
+v_max_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x20,0xd2,0x01,0x05,0x02,0x18]
+
+v_min_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x22,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0xff,0x05,0x02,0x00]
+
+v_min_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x67,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x68,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x69,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x6a,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x6b,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x6c,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x6d,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x6e,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x6f,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x7b,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x7c,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x7e,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x7f,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0x80,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0xc1,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0xf0,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0xf7,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0xfb,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0xfc,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0xfd,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x22,0xd2,0xfe,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xff,0x03,0x00]
+
+v_min_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x05,0x00,0x00]
+
+v_min_i32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xcf,0x00,0x00]
+
+v_min_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd1,0x00,0x00]
+
+v_min_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd3,0x00,0x00]
+
+v_min_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd5,0x00,0x00]
+
+v_min_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd7,0x00,0x00]
+
+v_min_i32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xd9,0x00,0x00]
+
+v_min_i32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xdb,0x00,0x00]
+
+v_min_i32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xdd,0x00,0x00]
+
+v_min_i32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xdf,0x00,0x00]
+
+v_min_i32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xf7,0x00,0x00]
+
+v_min_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xf9,0x00,0x00]
+
+v_min_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xfd,0x00,0x00]
+
+v_min_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xff,0x00,0x00]
+
+v_min_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x01,0x01,0x00]
+
+v_min_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0x83,0x01,0x00]
+
+v_min_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xe1,0x01,0x00]
+
+v_min_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xef,0x01,0x00]
+
+v_min_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xf7,0x01,0x00]
+
+v_min_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xf9,0x01,0x00]
+
+v_min_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x22,0xd2,0x01,0xfb,0x01,0x00]
+
+v_max_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x24,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0xff,0x05,0x02,0x00]
+
+v_max_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x67,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x68,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x69,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x6a,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x6b,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x6c,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x6d,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x6e,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x6f,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x7b,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x7c,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x7e,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x7f,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0x80,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0xc1,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0xf0,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0xf7,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0xfb,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0xfc,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0xfd,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x24,0xd2,0xfe,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xff,0x03,0x00]
+
+v_max_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x05,0x00,0x00]
+
+v_max_i32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xcf,0x00,0x00]
+
+v_max_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd1,0x00,0x00]
+
+v_max_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd3,0x00,0x00]
+
+v_max_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd5,0x00,0x00]
+
+v_max_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd7,0x00,0x00]
+
+v_max_i32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xd9,0x00,0x00]
+
+v_max_i32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xdb,0x00,0x00]
+
+v_max_i32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xdd,0x00,0x00]
+
+v_max_i32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xdf,0x00,0x00]
+
+v_max_i32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xf7,0x00,0x00]
+
+v_max_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xf9,0x00,0x00]
+
+v_max_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xfd,0x00,0x00]
+
+v_max_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xff,0x00,0x00]
+
+v_max_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x01,0x01,0x00]
+
+v_max_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0x83,0x01,0x00]
+
+v_max_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xe1,0x01,0x00]
+
+v_max_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xef,0x01,0x00]
+
+v_max_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xf7,0x01,0x00]
+
+v_max_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xf9,0x01,0x00]
+
+v_max_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x24,0xd2,0x01,0xfb,0x01,0x00]
+
+v_min_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x26,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0xff,0x05,0x02,0x00]
+
+v_min_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x67,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x68,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x69,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x6a,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x6b,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x6c,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x6d,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x6e,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x6f,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x7b,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x7c,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x7e,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x7f,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0x80,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0xc1,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0xf0,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0xf7,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0xfb,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0xfc,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0xfd,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x26,0xd2,0xfe,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xff,0x03,0x00]
+
+v_min_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x05,0x00,0x00]
+
+v_min_u32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xcf,0x00,0x00]
+
+v_min_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd1,0x00,0x00]
+
+v_min_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd3,0x00,0x00]
+
+v_min_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd5,0x00,0x00]
+
+v_min_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd7,0x00,0x00]
+
+v_min_u32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xd9,0x00,0x00]
+
+v_min_u32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xdb,0x00,0x00]
+
+v_min_u32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xdd,0x00,0x00]
+
+v_min_u32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xdf,0x00,0x00]
+
+v_min_u32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xf7,0x00,0x00]
+
+v_min_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xf9,0x00,0x00]
+
+v_min_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xfd,0x00,0x00]
+
+v_min_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xff,0x00,0x00]
+
+v_min_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x01,0x01,0x00]
+
+v_min_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0x83,0x01,0x00]
+
+v_min_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xe1,0x01,0x00]
+
+v_min_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xef,0x01,0x00]
+
+v_min_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xf7,0x01,0x00]
+
+v_min_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xf9,0x01,0x00]
+
+v_min_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x26,0xd2,0x01,0xfb,0x01,0x00]
+
+v_max_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x28,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0xff,0x05,0x02,0x00]
+
+v_max_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x67,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x68,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x69,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x6a,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x6b,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x6c,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x6d,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x6e,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x6f,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x7b,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x7c,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x7e,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x7f,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0x80,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0xc1,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0xf0,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0xf7,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0xfb,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0xfc,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0xfd,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x28,0xd2,0xfe,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xff,0x03,0x00]
+
+v_max_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x05,0x00,0x00]
+
+v_max_u32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xcf,0x00,0x00]
+
+v_max_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd1,0x00,0x00]
+
+v_max_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd3,0x00,0x00]
+
+v_max_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd5,0x00,0x00]
+
+v_max_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd7,0x00,0x00]
+
+v_max_u32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xd9,0x00,0x00]
+
+v_max_u32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xdb,0x00,0x00]
+
+v_max_u32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xdd,0x00,0x00]
+
+v_max_u32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xdf,0x00,0x00]
+
+v_max_u32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xf7,0x00,0x00]
+
+v_max_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xf9,0x00,0x00]
+
+v_max_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xfd,0x00,0x00]
+
+v_max_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xff,0x00,0x00]
+
+v_max_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x01,0x01,0x00]
+
+v_max_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0x83,0x01,0x00]
+
+v_max_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xe1,0x01,0x00]
+
+v_max_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xef,0x01,0x00]
+
+v_max_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xf7,0x01,0x00]
+
+v_max_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xf9,0x01,0x00]
+
+v_max_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x28,0xd2,0x01,0xfb,0x01,0x00]
+
+v_lshr_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshr_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2a,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshr_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0xff,0x05,0x02,0x00]
+
+v_lshr_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x67,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x68,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x69,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x6b,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x6c,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x6d,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x6e,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x6f,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x7b,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x7c,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x7f,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x2a,0xd2,0xfe,0x04,0x02,0x00]
+
+v_lshr_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xff,0x03,0x00]
+
+v_lshr_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x05,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xcf,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd1,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd3,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd7,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xd9,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xdb,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xdd,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xdf,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xf7,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xf9,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xff,0x00,0x00]
+
+v_lshr_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshr_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshr_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshr_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshr_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshr_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshr_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2a,0xd2,0x01,0xfb,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2c,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x67,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x68,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x69,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x6c,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x6d,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x6e,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x6f,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x7b,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2c,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xff,0x03,0x00]
+
+v_lshrrev_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x05,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xcf,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd1,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd3,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd7,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xd9,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xdb,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xdd,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xdf,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xf7,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xf9,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xff,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2c,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ashr_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashr_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2e,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashr_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0xff,0x05,0x02,0x00]
+
+v_ashr_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x67,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x68,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x69,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x6b,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x6c,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x6d,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x6e,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x6f,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x7b,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x7c,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x7f,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x80,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x2e,0xd2,0xfe,0x04,0x02,0x00]
+
+v_ashr_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xff,0x03,0x00]
+
+v_ashr_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x05,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xcf,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd1,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd3,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd7,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xd9,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xdb,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xdd,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xdf,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xf7,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xf9,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xff,0x00,0x00]
+
+v_ashr_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x01,0x01,0x00]
+
+v_ashr_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0x83,0x01,0x00]
+
+v_ashr_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ashr_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xef,0x01,0x00]
+
+v_ashr_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ashr_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ashr_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2e,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x30,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x67,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x68,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x69,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x6c,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x6d,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x6e,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x6f,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x7b,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x30,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xff,0x03,0x00]
+
+v_ashrrev_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x05,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xcf,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd1,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd3,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd7,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xd9,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xdb,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xdd,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xdf,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xf7,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xf9,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xff,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xef,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x30,0xd2,0x01,0xfb,0x01,0x00]
+
+v_lshl_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshl_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x32,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshl_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0xff,0x05,0x02,0x00]
+
+v_lshl_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x67,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x68,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x69,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x6b,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x6c,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x6d,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x6e,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x6f,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x7b,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x7c,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x7f,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x32,0xd2,0xfe,0x04,0x02,0x00]
+
+v_lshl_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xff,0x03,0x00]
+
+v_lshl_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x05,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xcf,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd1,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd3,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd7,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xd9,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xdb,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xdd,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xdf,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xf7,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xf9,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xff,0x00,0x00]
+
+v_lshl_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshl_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshl_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshl_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshl_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshl_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshl_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x32,0xd2,0x01,0xfb,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x34,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x67,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x68,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x69,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x6c,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x6d,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x6e,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x6f,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x7b,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x34,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xff,0x03,0x00]
+
+v_lshlrev_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x05,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xcf,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd1,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd3,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd7,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xd9,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xdb,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xdd,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xdf,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xf7,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xf9,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xff,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x34,0xd2,0x01,0xfb,0x01,0x00]
+
+v_and_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x05,0x02,0x00]
+
+v_and_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x36,0xd2,0x01,0x05,0x02,0x00]
+
+v_and_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0xff,0x05,0x02,0x00]
+
+v_and_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x67,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x68,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x69,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x6a,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x6b,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x6c,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x6d,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x6e,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x6f,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x7b,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x7c,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x7e,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x7f,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0x80,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0xc1,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0xf0,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0xf7,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0xfb,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0xfc,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0xfd,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x36,0xd2,0xfe,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xff,0x03,0x00]
+
+v_and_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x05,0x00,0x00]
+
+v_and_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xcf,0x00,0x00]
+
+v_and_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd1,0x00,0x00]
+
+v_and_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd3,0x00,0x00]
+
+v_and_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd5,0x00,0x00]
+
+v_and_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd7,0x00,0x00]
+
+v_and_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xd9,0x00,0x00]
+
+v_and_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xdb,0x00,0x00]
+
+v_and_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xdd,0x00,0x00]
+
+v_and_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xdf,0x00,0x00]
+
+v_and_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xf7,0x00,0x00]
+
+v_and_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xf9,0x00,0x00]
+
+v_and_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xfd,0x00,0x00]
+
+v_and_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xff,0x00,0x00]
+
+v_and_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x01,0x01,0x00]
+
+v_and_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0x83,0x01,0x00]
+
+v_and_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xe1,0x01,0x00]
+
+v_and_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xef,0x01,0x00]
+
+v_and_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xf7,0x01,0x00]
+
+v_and_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xf9,0x01,0x00]
+
+v_and_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x36,0xd2,0x01,0xfb,0x01,0x00]
+
+v_or_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x05,0x02,0x00]
+
+v_or_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x38,0xd2,0x01,0x05,0x02,0x00]
+
+v_or_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0xff,0x05,0x02,0x00]
+
+v_or_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x67,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x68,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x69,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x6a,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x6b,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x6c,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x6d,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x6e,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x6f,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x7b,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x7c,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x7e,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x7f,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0x80,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0xc1,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0xf0,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0xf7,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0xfb,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0xfc,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0xfd,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x38,0xd2,0xfe,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xff,0x03,0x00]
+
+v_or_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x05,0x00,0x00]
+
+v_or_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xcf,0x00,0x00]
+
+v_or_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd1,0x00,0x00]
+
+v_or_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd3,0x00,0x00]
+
+v_or_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd5,0x00,0x00]
+
+v_or_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd7,0x00,0x00]
+
+v_or_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xd9,0x00,0x00]
+
+v_or_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xdb,0x00,0x00]
+
+v_or_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xdd,0x00,0x00]
+
+v_or_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xdf,0x00,0x00]
+
+v_or_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xf7,0x00,0x00]
+
+v_or_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xf9,0x00,0x00]
+
+v_or_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xfd,0x00,0x00]
+
+v_or_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xff,0x00,0x00]
+
+v_or_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x01,0x01,0x00]
+
+v_or_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0x83,0x01,0x00]
+
+v_or_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xe1,0x01,0x00]
+
+v_or_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xef,0x01,0x00]
+
+v_or_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xf7,0x01,0x00]
+
+v_or_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xf9,0x01,0x00]
+
+v_or_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x38,0xd2,0x01,0xfb,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x05,0x02,0x00]
+
+v_xor_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x3a,0xd2,0x01,0x05,0x02,0x00]
+
+v_xor_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0xff,0x05,0x02,0x00]
+
+v_xor_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x67,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x68,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x69,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x6a,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x6b,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x6c,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x6d,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x6e,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x6f,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x7b,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x7c,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x7e,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x7f,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x80,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0xc1,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0xf0,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0xf7,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0xfb,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0xfc,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0xfd,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x3a,0xd2,0xfe,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xff,0x03,0x00]
+
+v_xor_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x05,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xcf,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd1,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd3,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd5,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd7,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xd9,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xdb,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xdd,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xdf,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xf7,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xf9,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xfd,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xff,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x01,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0x83,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xe1,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xef,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xf7,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xf9,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x3a,0xd2,0x01,0xfb,0x01,0x00]
+
+v_bfm_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x05,0x02,0x00]
+
+v_bfm_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x3c,0xd2,0x01,0x05,0x02,0x00]
+
+v_bfm_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0xff,0x05,0x02,0x00]
+
+v_bfm_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x67,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x68,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x69,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x6a,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x6b,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x6c,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x6d,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x6e,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x6f,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x7b,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x7c,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x7e,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x7f,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x80,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0xc1,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0xf0,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0xf7,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0xfb,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0xfc,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0xfd,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x3c,0xd2,0xfe,0x04,0x02,0x00]
+
+v_bfm_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xff,0x03,0x00]
+
+v_bfm_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x05,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xcf,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd1,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd3,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd5,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd7,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xd9,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xdb,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xdd,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xdf,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xf7,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xf9,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xfd,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xff,0x00,0x00]
+
+v_bfm_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x01,0x01,0x00]
+
+v_bfm_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0x83,0x01,0x00]
+
+v_bfm_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xe1,0x01,0x00]
+
+v_bfm_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xef,0x01,0x00]
+
+v_bfm_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xf7,0x01,0x00]
+
+v_bfm_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xf9,0x01,0x00]
+
+v_bfm_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x3c,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x3e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0xff,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x67,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x68,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x69,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x80,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xff,0x03,0x00]
+
+v_mac_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xff,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x01,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x83,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xef,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mac_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x20]
+
+v_mac_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x40]
+
+v_mac_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x60]
+
+v_mac_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x3e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x3e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x3e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x3e,0xd2,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x08]
+
+v_mac_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x10]
+
+v_mac_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x3e,0xd2,0x01,0x05,0x02,0x18]
+
+v_bcnt_u32_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x05,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x44,0xd2,0x01,0x05,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0xff,0x05,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x67,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x68,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x69,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x6a,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x6b,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x6c,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x6d,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x6e,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x6f,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x7b,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x7c,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x7e,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x7f,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0x80,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0xc1,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0xf0,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0xf7,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0xfb,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0xfc,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0xfd,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x44,0xd2,0xfe,0x04,0x02,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xff,0x03,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x05,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xcf,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd1,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd3,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd5,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd7,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xd9,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xdb,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xdd,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xdf,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xf7,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xf9,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xfd,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xff,0x00,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x01,0x01,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0x83,0x01,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xe1,0x01,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xef,0x01,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xf7,0x01,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xf9,0x01,0x00]
+
+v_bcnt_u32_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x44,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x46,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0xff,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x67,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x68,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x69,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0x80,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x46,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xff,0x03,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x05,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xff,0x00,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x01,0x01,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0x83,0x01,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xef,0x01,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mbcnt_lo_u32_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x46,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x48,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0xff,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x67,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x68,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x69,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0x80,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x48,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xff,0x03,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x05,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xff,0x00,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x01,0x01,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0x83,0x01,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xef,0x01,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mbcnt_hi_u32_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x48,0xd2,0x01,0xfb,0x01,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32_e64 v255, s[12:13], v1, v2
+// CHECK: [0xff,0x0c,0x4a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32_e64 v5, s[14:15], v1, v2
+// CHECK: [0x05,0x0e,0x4a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32_e64 v5, s[102:103], v1, v2
+// CHECK: [0x05,0x66,0x4a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32_e64 v5, flat_scratch, v1, v2
+// CHECK: [0x05,0x68,0x4a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32_e64 v5, vcc, v1, v2
+// CHECK: [0x05,0x6a,0x4a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32_e64 v5, tba, v1, v2
+// CHECK: [0x05,0x6c,0x4a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32_e64 v5, tma, v1, v2
+// CHECK: [0x05,0x6e,0x4a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32_e64 v5, ttmp[10:11], v1, v2
+// CHECK: [0x05,0x7a,0x4a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], v255, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0xff,0x05,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], s1, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], s103, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x67,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], flat_scratch_lo, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x68,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], flat_scratch_hi, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x69,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], vcc_lo, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x6a,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], vcc_hi, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x6b,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], tba_lo, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x6c,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], tba_hi, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x6d,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], tma_lo, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x6e,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], tma_hi, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x6f,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], ttmp11, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x7b,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], m0, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x7c,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], exec_lo, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x7e,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], exec_hi, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x7f,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], 0, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x80,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], -1, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0xc1,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], 0.5, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0xf0,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], -4.0, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0xf7,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], src_vccz, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0xfb,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], src_execz, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0xfc,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], src_scc, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0xfd,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], src_lds_direct, v2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0xfe,0x04,0x02,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, v255
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xff,0x03,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, s2
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x05,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, s103
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xcf,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, flat_scratch_lo
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd1,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, flat_scratch_hi
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd3,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, vcc_lo
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd5,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, vcc_hi
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd7,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, tba_lo
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xd9,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, tba_hi
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xdb,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, tma_lo
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xdd,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, tma_hi
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xdf,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, ttmp11
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xf7,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, m0
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xf9,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, exec_lo
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xfd,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, exec_hi
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xff,0x00,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, 0
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x01,0x01,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, -1
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0x83,0x01,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, 0.5
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xe1,0x01,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, -4.0
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xef,0x01,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, src_vccz
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xf7,0x01,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, src_execz
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xf9,0x01,0x00]
+
+v_add_i32_e64 v5, s[12:13], v1, src_scc
+// CHECK: [0x05,0x0c,0x4a,0xd2,0x01,0xfb,0x01,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32_e64 v255, s[12:13], v1, v2
+// CHECK: [0xff,0x0c,0x4c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32_e64 v5, s[14:15], v1, v2
+// CHECK: [0x05,0x0e,0x4c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32_e64 v5, s[102:103], v1, v2
+// CHECK: [0x05,0x66,0x4c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32_e64 v5, flat_scratch, v1, v2
+// CHECK: [0x05,0x68,0x4c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32_e64 v5, vcc, v1, v2
+// CHECK: [0x05,0x6a,0x4c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32_e64 v5, tba, v1, v2
+// CHECK: [0x05,0x6c,0x4c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32_e64 v5, tma, v1, v2
+// CHECK: [0x05,0x6e,0x4c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32_e64 v5, ttmp[10:11], v1, v2
+// CHECK: [0x05,0x7a,0x4c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v255, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0xff,0x05,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], s1, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], s103, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x67,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], flat_scratch_lo, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x68,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], flat_scratch_hi, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x69,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], vcc_lo, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x6a,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], vcc_hi, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x6b,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], tba_lo, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x6c,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], tba_hi, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x6d,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], tma_lo, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x6e,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], tma_hi, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x6f,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], ttmp11, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x7b,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], m0, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x7c,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], exec_lo, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x7e,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], exec_hi, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x7f,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], 0, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x80,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], -1, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0xc1,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], 0.5, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0xf0,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], -4.0, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0xf7,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], src_vccz, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0xfb,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], src_execz, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0xfc,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], src_scc, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0xfd,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], src_lds_direct, v2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0xfe,0x04,0x02,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, v255
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xff,0x03,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, s2
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x05,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, s103
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xcf,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, flat_scratch_lo
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd1,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, flat_scratch_hi
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd3,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, vcc_lo
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd5,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, vcc_hi
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd7,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, tba_lo
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xd9,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, tba_hi
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xdb,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, tma_lo
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xdd,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, tma_hi
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xdf,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, ttmp11
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xf7,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, m0
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xf9,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, exec_lo
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xfd,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, exec_hi
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xff,0x00,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, 0
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x01,0x01,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, -1
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0x83,0x01,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, 0.5
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xe1,0x01,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, -4.0
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xef,0x01,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, src_vccz
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xf7,0x01,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, src_execz
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xf9,0x01,0x00]
+
+v_sub_i32_e64 v5, s[12:13], v1, src_scc
+// CHECK: [0x05,0x0c,0x4c,0xd2,0x01,0xfb,0x01,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v255, s[12:13], v1, v2
+// CHECK: [0xff,0x0c,0x4e,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[14:15], v1, v2
+// CHECK: [0x05,0x0e,0x4e,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[102:103], v1, v2
+// CHECK: [0x05,0x66,0x4e,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v5, flat_scratch, v1, v2
+// CHECK: [0x05,0x68,0x4e,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v5, vcc, v1, v2
+// CHECK: [0x05,0x6a,0x4e,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v5, tba, v1, v2
+// CHECK: [0x05,0x6c,0x4e,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v5, tma, v1, v2
+// CHECK: [0x05,0x6e,0x4e,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v5, ttmp[10:11], v1, v2
+// CHECK: [0x05,0x7a,0x4e,0xd2,0x01,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v255, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0xff,0x05,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], s1, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], s103, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x67,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], flat_scratch_lo, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x68,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], flat_scratch_hi, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x69,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], vcc_lo, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x6a,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], vcc_hi, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x6b,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], tba_lo, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x6c,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], tba_hi, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x6d,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], tma_lo, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x6e,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], tma_hi, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x6f,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], ttmp11, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x7b,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], m0, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x7c,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], exec_lo, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x7e,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], exec_hi, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x7f,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], 0, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x80,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], -1, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0xc1,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], 0.5, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0xf0,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], -4.0, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0xf7,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], src_vccz, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0xfb,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], src_execz, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0xfc,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], src_scc, v2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0xfd,0x04,0x02,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, v255
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xff,0x03,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, s2
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x05,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, s103
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xcf,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, flat_scratch_lo
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd1,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, flat_scratch_hi
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd3,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, vcc_lo
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd5,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, vcc_hi
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd7,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, tba_lo
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xd9,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, tba_hi
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xdb,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, tma_lo
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xdd,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, tma_hi
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xdf,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, ttmp11
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xf7,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, m0
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xf9,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, exec_lo
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xfd,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, exec_hi
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xff,0x00,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, 0
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x01,0x01,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, -1
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0x83,0x01,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, 0.5
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xe1,0x01,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, -4.0
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xef,0x01,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, src_vccz
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xf7,0x01,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, src_execz
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xf9,0x01,0x00]
+
+v_subrev_i32_e64 v5, s[12:13], v1, src_scc
+// CHECK: [0x05,0x0c,0x4e,0xd2,0x01,0xfb,0x01,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// CHECK: [0xff,0x0c,0x50,0xd2,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x0e,0x50,0xd2,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[102:103], v1, v2, s[6:7]
+// CHECK: [0x05,0x66,0x50,0xd2,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
+// CHECK: [0x05,0x68,0x50,0xd2,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, vcc, v1, v2, s[6:7]
+// CHECK: [0x05,0x6a,0x50,0xd2,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, tba, v1, v2, s[6:7]
+// CHECK: [0x05,0x6c,0x50,0xd2,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, tma, v1, v2, s[6:7]
+// CHECK: [0x05,0x6e,0x50,0xd2,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
+// CHECK: [0x05,0x7a,0x50,0xd2,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0xff,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x80,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0xc1,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0xf0,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0xf7,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], src_lds_direct, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0xfe,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0xff,0x1b,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x01,0x19,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x83,0x19,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0xe1,0x19,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0xef,0x19,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0x22,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, s[102:103]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0x9a,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xa2,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xaa,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xb2,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xba,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0x50,0xd2,0x01,0x05,0xea,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// CHECK: [0xff,0x0c,0x52,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x0e,0x52,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[102:103], v1, v2, s[6:7]
+// CHECK: [0x05,0x66,0x52,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
+// CHECK: [0x05,0x68,0x52,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, vcc, v1, v2, s[6:7]
+// CHECK: [0x05,0x6a,0x52,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, tba, v1, v2, s[6:7]
+// CHECK: [0x05,0x6c,0x52,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, tma, v1, v2, s[6:7]
+// CHECK: [0x05,0x6e,0x52,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
+// CHECK: [0x05,0x7a,0x52,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0xff,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x80,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0xc1,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0xf0,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0xf7,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], src_lds_direct, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0xfe,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0xff,0x1b,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x01,0x19,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x83,0x19,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0xe1,0x19,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0xef,0x19,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0x22,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, s[102:103]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0x9a,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xa2,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xaa,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xb2,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xba,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0x52,0xd2,0x01,0x05,0xea,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// CHECK: [0xff,0x0c,0x54,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x0e,0x54,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[102:103], v1, v2, s[6:7]
+// CHECK: [0x05,0x66,0x54,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
+// CHECK: [0x05,0x68,0x54,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, vcc, v1, v2, s[6:7]
+// CHECK: [0x05,0x6a,0x54,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, tba, v1, v2, s[6:7]
+// CHECK: [0x05,0x6c,0x54,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, tma, v1, v2, s[6:7]
+// CHECK: [0x05,0x6e,0x54,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
+// CHECK: [0x05,0x7a,0x54,0xd2,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0xff,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x80,0x04,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0xc1,0x04,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0xf0,0x04,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0xf7,0x04,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0xff,0x1b,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x01,0x19,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x83,0x19,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0xe1,0x19,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0xef,0x19,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0x22,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[102:103]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0x9a,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xa2,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xaa,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xb2,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xba,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0x54,0xd2,0x01,0x05,0xea,0x01]
+
+v_ldexp_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x56,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0xff,0x05,0x02,0x00]
+
+v_ldexp_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x67,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x68,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x69,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x6b,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x6c,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x6d,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x6e,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x6f,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x7b,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x7c,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x7f,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x80,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0xfe,0x04,0x02,0x00]
+
+v_ldexp_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xff,0x03,0x00]
+
+v_ldexp_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x05,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd1,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd3,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xd9,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xdb,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xdd,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xdf,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xf7,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xff,0x00,0x00]
+
+v_ldexp_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x01,0x01,0x00]
+
+v_ldexp_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x83,0x01,0x00]
+
+v_ldexp_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xef,0x01,0x00]
+
+v_ldexp_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ldexp_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ldexp_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x05,0x02,0x20]
+
+v_ldexp_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x56,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x08,0x56,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x05,0x02,0x08]
+
+v_ldexp_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x05,0x02,0x10]
+
+v_ldexp_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x56,0xd2,0x01,0x05,0x02,0x18]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x58,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x68,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x69,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd1,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd3,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x58,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pkaccum_u8_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x58,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x5a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x68,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x69,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd1,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd3,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_i16_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x5a,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_i16_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x5a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x5a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x5a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x5c,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x68,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x69,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd1,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd3,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_u16_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x5c,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_u16_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x5c,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x5c,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x5c,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x5e,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x68,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x69,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd1,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd3,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pkrtz_f16_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x5e,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pkrtz_f16_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x5e,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x5e,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x5e,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x60,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x68,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x69,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x60,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd1,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd3,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pk_u16_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x60,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x62,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, s103, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x68,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x69,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x62,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, s103
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd1,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd3,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pk_i16_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x62,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_f_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_f_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x00,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_f_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x00,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x02,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x02,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_eq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_eq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x04,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_eq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x04,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_le_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_le_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x06,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_le_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x06,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_gt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_gt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x08,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_gt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x08,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x0a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x0a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x0c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x0c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_o_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_o_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x0e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_o_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x0e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_u_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_u_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_u_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ngt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x16,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ngt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x16,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nle_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nle_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x18,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nle_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x18,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_neq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_neq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x1a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_neq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x1a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x1c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x1c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_tru_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_tru_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x1e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_tru_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x1e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_f_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_eq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_le_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_gt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_o_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_u_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ngt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nle_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_neq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_tru_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_f_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_f_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_f_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x80,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_f_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x80,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_lt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_lt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x82,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_lt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x82,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_eq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_eq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x84,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_eq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x84,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_le_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_le_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_le_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x86,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_le_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x86,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_gt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_gt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x88,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_gt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x88,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_lg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_lg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x8a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_lg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x8a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_ge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_ge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x8c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_ge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x8c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_o_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_o_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_o_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x8e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_o_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x8e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_u_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_u_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_u_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x90,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_u_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x90,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_nge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_nge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x92,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_nge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x92,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_nlg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x94,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_nlg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x94,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_ngt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x96,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_ngt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x96,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_nle_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_nle_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x98,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_nle_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x98,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_neq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_neq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x9a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_neq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x9a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_nlt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x9c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_nlt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x9c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_tru_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_tru_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x9e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_tru_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x9e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_f_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_f_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_lt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_lt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_eq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_eq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_le_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_le_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_gt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_gt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_lg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_lg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_ge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_ge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_o_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_o_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_u_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_u_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_nge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_nge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_nlg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_nlg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_ngt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_ngt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_nle_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_nle_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_neq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_neq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_nlt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_nlt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x69,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd3,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_tru_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_tru_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_f_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_f_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_f_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_lt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_eq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_eq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_le_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_le_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_le_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_gt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_gt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_lg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_lg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_ge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_o_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_o_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_o_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_u_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_u_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_u_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_nge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_nlg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_ngt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_ngt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_nle_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nle_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_neq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_neq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_nlt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_nlt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmps_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmps_tru_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmps_tru_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_f_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_f_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_lt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_eq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_eq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_le_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_le_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_gt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_gt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_lg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_lg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_ge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_o_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_o_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_u_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_u_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_nge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_nlg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_ngt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_ngt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_nle_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nle_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_neq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_neq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_nlt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_nlt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x68,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd1,0x00,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpsx_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpsx_tru_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpsx_tru_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x00,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x00,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x00,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x02,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x02,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x04,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x04,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x06,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x06,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x08,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x08,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x0a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x0c,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x0e,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x20,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x20,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x22,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x22,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x24,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x24,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x24,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x26,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x26,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x28,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x28,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2c,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2e,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x40,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x40,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x40,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x42,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x42,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x42,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x44,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x44,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x44,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x46,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x46,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x46,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x48,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x48,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x48,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x4a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x4a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x4c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x4c,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x4e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x4e,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x60,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x60,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x62,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x62,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x64,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x64,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x66,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x66,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x68,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x68,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6c,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6e,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x80,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x80,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x80,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x82,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x82,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x82,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x84,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x84,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x84,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x86,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x86,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x86,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x88,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x88,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x88,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x8a,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x8a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x8c,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x8c,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x8e,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x8e,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa0,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa2,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa4,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa6,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa8,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xaa,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xaa,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xac,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xac,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xac,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xae,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xae,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xae,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc0,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc2,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc4,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc6,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xc8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xc8,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xca,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xca,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xca,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xcc,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xcc,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xce,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xce,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xce,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe0,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe2,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe2,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe4,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe4,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe6,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe6,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe8,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe8,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xea,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xea,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xec,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xec,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[102:103], v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x68,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xee,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], s[102:103], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xfd,0x03,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x09,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x0d,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], s[102:103]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xf5,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xee,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x10,0xd1,0x01,0x05,0x02,0x20]
+
+v_cmp_class_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[102:103], v1, v2
+// CHECK: [0x66,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x68,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], s103, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x67,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x69,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, s103
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x30,0xd1,0x01,0x05,0x02,0x20]
+
+v_cmpx_class_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[12:13], v[1:2], v2
+// CHECK: [0x0c,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[102:103], v[1:2], v2
+// CHECK: [0x66,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 flat_scratch, v[1:2], v2
+// CHECK: [0x68,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 vcc, v[1:2], v2
+// CHECK: [0x6a,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 tba, v[1:2], v2
+// CHECK: [0x6c,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 tma, v[1:2], v2
+// CHECK: [0x6e,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 ttmp[10:11], v[1:2], v2
+// CHECK: [0x7a,0x00,0x50,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[254:255], v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], s[2:3], v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], s[4:5], v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], s[102:103], v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], flat_scratch, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], vcc, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], tba, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], tma, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], ttmp[10:11], v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], exec, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v255
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s103
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_lo
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_hi
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], tba_lo
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], tba_hi
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], tma_lo
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], tma_hi
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], ttmp11
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], m0
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], exec_lo
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], exec_hi
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], -v[1:2], v2
+// CHECK: [0x0a,0x00,0x50,0xd1,0x01,0x05,0x02,0x20]
+
+v_cmp_class_f64_e64 s[10:11], |v[1:2]|, v2
+// CHECK: [0x0a,0x01,0x50,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[12:13], v[1:2], v2
+// CHECK: [0x0c,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[102:103], v[1:2], v2
+// CHECK: [0x66,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 flat_scratch, v[1:2], v2
+// CHECK: [0x68,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 vcc, v[1:2], v2
+// CHECK: [0x6a,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 tba, v[1:2], v2
+// CHECK: [0x6c,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 tma, v[1:2], v2
+// CHECK: [0x6e,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 ttmp[10:11], v[1:2], v2
+// CHECK: [0x7a,0x00,0x70,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[254:255], v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0xfe,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], s[2:3], v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x02,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], s[4:5], v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x04,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], s[102:103], v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x66,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], flat_scratch, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x68,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], vcc, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], tba, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], tma, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], ttmp[10:11], v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x7a,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], exec, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], v255
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], s2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], s103
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd1,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd3,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_lo
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_hi
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], tba_lo
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], tba_hi
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], tma_lo
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], tma_hi
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], ttmp11
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], m0
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_lo
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_hi
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], -v[1:2], v2
+// CHECK: [0x0a,0x00,0x70,0xd1,0x01,0x05,0x02,0x20]
+
+v_cmpx_class_f64_e64 s[10:11], |v[1:2]|, v2
+// CHECK: [0x0a,0x01,0x70,0xd1,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s b/llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s
new file mode 100644
index 0000000000000..422412b4595e1
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vop3_e64.s
@@ -0,0 +1,10534 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+v_mad_legacy_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x80,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x68,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x69,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mad_legacy_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xef,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xfe,0x07]
+
+v_mad_legacy_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x00]
+
+v_mad_legacy_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x9e,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xa2,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xa6,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xae,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xb2,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xb6,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xba,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xbe,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xee,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xf2,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xfe,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x02]
+
+v_mad_legacy_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x06,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xee,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mad_legacy_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x24]
+
+v_mad_legacy_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x44]
+
+v_mad_legacy_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x84]
+
+v_mad_legacy_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_mad_legacy_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x80,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x80,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x80,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x80,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0x80,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_mad_legacy_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x14]
+
+v_mad_legacy_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_mad_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x82,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mad_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mad_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mad_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x68,0x04,0x0e,0x04]
+
+v_mad_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x69,0x04,0x0e,0x04]
+
+v_mad_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mad_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mad_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_mad_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_mad_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_mad_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_mad_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mad_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mad_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mad_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mad_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mad_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mad_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mad_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mad_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mad_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mad_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_mad_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_mad_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mad_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mad_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_mad_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_mad_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_mad_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_mad_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mad_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mad_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mad_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mad_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mad_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mad_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xef,0x0d,0x04]
+
+v_mad_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mad_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mad_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xfe,0x07]
+
+v_mad_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x00]
+
+v_mad_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x9e,0x01]
+
+v_mad_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xa2,0x01]
+
+v_mad_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xa6,0x01]
+
+v_mad_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mad_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xae,0x01]
+
+v_mad_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xb2,0x01]
+
+v_mad_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xb6,0x01]
+
+v_mad_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xba,0x01]
+
+v_mad_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xbe,0x01]
+
+v_mad_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xee,0x01]
+
+v_mad_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xf2,0x01]
+
+v_mad_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mad_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xfe,0x01]
+
+v_mad_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x02]
+
+v_mad_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x06,0x03]
+
+v_mad_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mad_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xee,0x03]
+
+v_mad_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mad_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mad_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x24]
+
+v_mad_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x44]
+
+v_mad_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x84]
+
+v_mad_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_mad_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x82,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x82,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x82,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x82,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0x82,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_mad_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x14]
+
+v_mad_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_mad_i32_i24 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x84,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x68,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x69,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mad_i32_i24 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xef,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xfe,0x07]
+
+v_mad_i32_i24 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x0e,0x00]
+
+v_mad_i32_i24 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x9e,0x01]
+
+v_mad_i32_i24 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xa2,0x01]
+
+v_mad_i32_i24 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xa6,0x01]
+
+v_mad_i32_i24 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mad_i32_i24 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xae,0x01]
+
+v_mad_i32_i24 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xb2,0x01]
+
+v_mad_i32_i24 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xb6,0x01]
+
+v_mad_i32_i24 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xba,0x01]
+
+v_mad_i32_i24 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xbe,0x01]
+
+v_mad_i32_i24 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xee,0x01]
+
+v_mad_i32_i24 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xf2,0x01]
+
+v_mad_i32_i24 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mad_i32_i24 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xfe,0x01]
+
+v_mad_i32_i24 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x02]
+
+v_mad_i32_i24 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x06,0x03]
+
+v_mad_i32_i24 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mad_i32_i24 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_i32_i24 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xee,0x03]
+
+v_mad_i32_i24 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mad_i32_i24 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mad_u32_u24 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x86,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x68,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x69,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mad_u32_u24 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xef,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xfe,0x07]
+
+v_mad_u32_u24 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x0e,0x00]
+
+v_mad_u32_u24 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x9e,0x01]
+
+v_mad_u32_u24 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xa2,0x01]
+
+v_mad_u32_u24 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xa6,0x01]
+
+v_mad_u32_u24 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mad_u32_u24 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xae,0x01]
+
+v_mad_u32_u24 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xb2,0x01]
+
+v_mad_u32_u24 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xb6,0x01]
+
+v_mad_u32_u24 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xba,0x01]
+
+v_mad_u32_u24 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xbe,0x01]
+
+v_mad_u32_u24 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xee,0x01]
+
+v_mad_u32_u24 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xf2,0x01]
+
+v_mad_u32_u24 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mad_u32_u24 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xfe,0x01]
+
+v_mad_u32_u24 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x02,0x02]
+
+v_mad_u32_u24 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x06,0x03]
+
+v_mad_u32_u24 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mad_u32_u24 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_u32_u24 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xee,0x03]
+
+v_mad_u32_u24 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mad_u32_u24 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0xf6,0x03]
+
+v_cubeid_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x88,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0xff,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x67,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x68,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x69,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x80,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x0f,0x04]
+
+v_cubeid_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x01,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x83,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xef,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xfe,0x07]
+
+v_cubeid_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x00]
+
+v_cubeid_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x9e,0x01]
+
+v_cubeid_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xa2,0x01]
+
+v_cubeid_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xa6,0x01]
+
+v_cubeid_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xaa,0x01]
+
+v_cubeid_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xae,0x01]
+
+v_cubeid_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xb2,0x01]
+
+v_cubeid_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xb6,0x01]
+
+v_cubeid_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xba,0x01]
+
+v_cubeid_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xbe,0x01]
+
+v_cubeid_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xee,0x01]
+
+v_cubeid_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xf2,0x01]
+
+v_cubeid_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xfa,0x01]
+
+v_cubeid_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xfe,0x01]
+
+v_cubeid_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x02]
+
+v_cubeid_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x06,0x03]
+
+v_cubeid_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xc2,0x03]
+
+v_cubeid_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xde,0x03]
+
+v_cubeid_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xee,0x03]
+
+v_cubeid_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xf2,0x03]
+
+v_cubeid_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0xf6,0x03]
+
+v_cubeid_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x24]
+
+v_cubeid_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x44]
+
+v_cubeid_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x84]
+
+v_cubeid_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_cubeid_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x88,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x88,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x88,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x88,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0x88,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_cubeid_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x14]
+
+v_cubeid_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_cubesc_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0xff,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x67,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x68,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x69,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xff,0x0f,0x04]
+
+v_cubesc_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xff,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x01,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x83,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xef,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xfe,0x07]
+
+v_cubesc_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x00]
+
+v_cubesc_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x9e,0x01]
+
+v_cubesc_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xa2,0x01]
+
+v_cubesc_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xa6,0x01]
+
+v_cubesc_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xaa,0x01]
+
+v_cubesc_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xae,0x01]
+
+v_cubesc_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xb2,0x01]
+
+v_cubesc_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xb6,0x01]
+
+v_cubesc_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xba,0x01]
+
+v_cubesc_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xbe,0x01]
+
+v_cubesc_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xee,0x01]
+
+v_cubesc_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xf2,0x01]
+
+v_cubesc_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xfa,0x01]
+
+v_cubesc_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xfe,0x01]
+
+v_cubesc_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x02,0x02]
+
+v_cubesc_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x06,0x03]
+
+v_cubesc_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xc2,0x03]
+
+v_cubesc_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xde,0x03]
+
+v_cubesc_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xee,0x03]
+
+v_cubesc_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xf2,0x03]
+
+v_cubesc_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0xf6,0x03]
+
+v_cubesc_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x24]
+
+v_cubesc_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x44]
+
+v_cubesc_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x84]
+
+v_cubesc_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_cubesc_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x8a,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x8a,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x8a,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x8a,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0x8a,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_cubesc_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x14]
+
+v_cubesc_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0x8a,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_cubetc_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0xff,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x67,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x68,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x69,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x80,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x0f,0x04]
+
+v_cubetc_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x01,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x83,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xef,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xfe,0x07]
+
+v_cubetc_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x00]
+
+v_cubetc_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x9e,0x01]
+
+v_cubetc_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xa2,0x01]
+
+v_cubetc_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xa6,0x01]
+
+v_cubetc_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xaa,0x01]
+
+v_cubetc_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xae,0x01]
+
+v_cubetc_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xb2,0x01]
+
+v_cubetc_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xb6,0x01]
+
+v_cubetc_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xba,0x01]
+
+v_cubetc_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xbe,0x01]
+
+v_cubetc_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xee,0x01]
+
+v_cubetc_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xf2,0x01]
+
+v_cubetc_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xfa,0x01]
+
+v_cubetc_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xfe,0x01]
+
+v_cubetc_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x02,0x02]
+
+v_cubetc_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x06,0x03]
+
+v_cubetc_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xc2,0x03]
+
+v_cubetc_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xde,0x03]
+
+v_cubetc_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xee,0x03]
+
+v_cubetc_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xf2,0x03]
+
+v_cubetc_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0xf6,0x03]
+
+v_cubetc_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x24]
+
+v_cubetc_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x44]
+
+v_cubetc_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x84]
+
+v_cubetc_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_cubetc_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x8c,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x8c,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x8c,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x8c,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0x8c,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_cubetc_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x14]
+
+v_cubetc_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_cubema_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0xff,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x67,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x68,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x69,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x80,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xff,0x0f,0x04]
+
+v_cubema_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0c,0x04]
+
+v_cubema_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_cubema_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_cubema_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_cubema_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_cubema_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_cubema_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_cubema_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_cubema_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_cubema_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_cubema_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_cubema_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_cubema_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_cubema_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xff,0x0c,0x04]
+
+v_cubema_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x01,0x0d,0x04]
+
+v_cubema_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x83,0x0d,0x04]
+
+v_cubema_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_cubema_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xef,0x0d,0x04]
+
+v_cubema_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_cubema_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_cubema_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_cubema_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xfe,0x07]
+
+v_cubema_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x00]
+
+v_cubema_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x9e,0x01]
+
+v_cubema_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xa2,0x01]
+
+v_cubema_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xa6,0x01]
+
+v_cubema_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xaa,0x01]
+
+v_cubema_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xae,0x01]
+
+v_cubema_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xb2,0x01]
+
+v_cubema_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xb6,0x01]
+
+v_cubema_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xba,0x01]
+
+v_cubema_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xbe,0x01]
+
+v_cubema_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xee,0x01]
+
+v_cubema_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xf2,0x01]
+
+v_cubema_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xfa,0x01]
+
+v_cubema_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xfe,0x01]
+
+v_cubema_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x02,0x02]
+
+v_cubema_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x06,0x03]
+
+v_cubema_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xc2,0x03]
+
+v_cubema_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xde,0x03]
+
+v_cubema_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xee,0x03]
+
+v_cubema_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xf2,0x03]
+
+v_cubema_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0xf6,0x03]
+
+v_cubema_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x24]
+
+v_cubema_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x44]
+
+v_cubema_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x84]
+
+v_cubema_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_cubema_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x8e,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x8e,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x8e,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x8e,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0x8e,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_cubema_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x14]
+
+v_cubema_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0x8e,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_bfe_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x0e,0x04]
+
+v_bfe_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x90,0xd2,0x01,0x05,0x0e,0x04]
+
+v_bfe_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0xff,0x05,0x0e,0x04]
+
+v_bfe_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x67,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x68,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x69,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x80,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xff,0x0f,0x04]
+
+v_bfe_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x0c,0x04]
+
+v_bfe_u32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_bfe_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_bfe_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_bfe_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_bfe_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_bfe_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_bfe_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_bfe_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_bfe_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_bfe_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_bfe_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_bfe_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_bfe_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xff,0x0c,0x04]
+
+v_bfe_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x01,0x0d,0x04]
+
+v_bfe_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x83,0x0d,0x04]
+
+v_bfe_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_bfe_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xef,0x0d,0x04]
+
+v_bfe_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_bfe_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_bfe_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_bfe_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xfe,0x07]
+
+v_bfe_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x0e,0x00]
+
+v_bfe_u32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x9e,0x01]
+
+v_bfe_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xa2,0x01]
+
+v_bfe_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xa6,0x01]
+
+v_bfe_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xaa,0x01]
+
+v_bfe_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xae,0x01]
+
+v_bfe_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xb2,0x01]
+
+v_bfe_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xb6,0x01]
+
+v_bfe_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xba,0x01]
+
+v_bfe_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xbe,0x01]
+
+v_bfe_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xee,0x01]
+
+v_bfe_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xf2,0x01]
+
+v_bfe_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xfa,0x01]
+
+v_bfe_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xfe,0x01]
+
+v_bfe_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x02,0x02]
+
+v_bfe_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x06,0x03]
+
+v_bfe_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xc2,0x03]
+
+v_bfe_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xde,0x03]
+
+v_bfe_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xee,0x03]
+
+v_bfe_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xf2,0x03]
+
+v_bfe_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0xf6,0x03]
+
+v_bfe_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x0e,0x04]
+
+v_bfe_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x92,0xd2,0x01,0x05,0x0e,0x04]
+
+v_bfe_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0xff,0x05,0x0e,0x04]
+
+v_bfe_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x67,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x68,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x69,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x80,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x0f,0x04]
+
+v_bfe_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x0c,0x04]
+
+v_bfe_i32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_bfe_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_bfe_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_bfe_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_bfe_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_bfe_i32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_bfe_i32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_bfe_i32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_bfe_i32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_bfe_i32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_bfe_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_bfe_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_bfe_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x0c,0x04]
+
+v_bfe_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x01,0x0d,0x04]
+
+v_bfe_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x83,0x0d,0x04]
+
+v_bfe_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_bfe_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xef,0x0d,0x04]
+
+v_bfe_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_bfe_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_bfe_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_bfe_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xfe,0x07]
+
+v_bfe_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x0e,0x00]
+
+v_bfe_i32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x9e,0x01]
+
+v_bfe_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xa2,0x01]
+
+v_bfe_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xa6,0x01]
+
+v_bfe_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xaa,0x01]
+
+v_bfe_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xae,0x01]
+
+v_bfe_i32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xb2,0x01]
+
+v_bfe_i32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xb6,0x01]
+
+v_bfe_i32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xba,0x01]
+
+v_bfe_i32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xbe,0x01]
+
+v_bfe_i32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xee,0x01]
+
+v_bfe_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xf2,0x01]
+
+v_bfe_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xfa,0x01]
+
+v_bfe_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xfe,0x01]
+
+v_bfe_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x02]
+
+v_bfe_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x06,0x03]
+
+v_bfe_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xc2,0x03]
+
+v_bfe_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xde,0x03]
+
+v_bfe_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xee,0x03]
+
+v_bfe_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xf2,0x03]
+
+v_bfe_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0xf6,0x03]
+
+v_bfi_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x0e,0x04]
+
+v_bfi_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x94,0xd2,0x01,0x05,0x0e,0x04]
+
+v_bfi_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0xff,0x05,0x0e,0x04]
+
+v_bfi_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x67,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x68,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x69,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x80,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x0f,0x04]
+
+v_bfi_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x0c,0x04]
+
+v_bfi_b32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_bfi_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_bfi_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_bfi_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_bfi_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_bfi_b32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_bfi_b32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_bfi_b32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_bfi_b32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_bfi_b32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_bfi_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_bfi_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_bfi_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x0c,0x04]
+
+v_bfi_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x01,0x0d,0x04]
+
+v_bfi_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x83,0x0d,0x04]
+
+v_bfi_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_bfi_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xef,0x0d,0x04]
+
+v_bfi_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_bfi_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_bfi_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_bfi_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xfe,0x07]
+
+v_bfi_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x0e,0x00]
+
+v_bfi_b32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x9e,0x01]
+
+v_bfi_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xa2,0x01]
+
+v_bfi_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xa6,0x01]
+
+v_bfi_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xaa,0x01]
+
+v_bfi_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xae,0x01]
+
+v_bfi_b32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xb2,0x01]
+
+v_bfi_b32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xb6,0x01]
+
+v_bfi_b32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xba,0x01]
+
+v_bfi_b32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xbe,0x01]
+
+v_bfi_b32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xee,0x01]
+
+v_bfi_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xf2,0x01]
+
+v_bfi_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xfa,0x01]
+
+v_bfi_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xfe,0x01]
+
+v_bfi_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x02]
+
+v_bfi_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x06,0x03]
+
+v_bfi_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xc2,0x03]
+
+v_bfi_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xde,0x03]
+
+v_bfi_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xee,0x03]
+
+v_bfi_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xf2,0x03]
+
+v_bfi_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0xf6,0x03]
+
+v_fma_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x96,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0xff,0x05,0x0e,0x04]
+
+v_fma_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x04,0x0e,0x04]
+
+v_fma_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x67,0x04,0x0e,0x04]
+
+v_fma_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x68,0x04,0x0e,0x04]
+
+v_fma_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x69,0x04,0x0e,0x04]
+
+v_fma_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_fma_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_fma_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_fma_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_fma_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_fma_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_fma_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_fma_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_fma_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_fma_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_fma_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x80,0x04,0x0e,0x04]
+
+v_fma_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_fma_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_fma_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_fma_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x0f,0x04]
+
+v_fma_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0c,0x04]
+
+v_fma_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_fma_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_fma_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_fma_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_fma_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_fma_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_fma_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_fma_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_fma_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_fma_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_fma_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_fma_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_fma_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x0c,0x04]
+
+v_fma_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x01,0x0d,0x04]
+
+v_fma_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x83,0x0d,0x04]
+
+v_fma_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_fma_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xef,0x0d,0x04]
+
+v_fma_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_fma_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_fma_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_fma_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xfe,0x07]
+
+v_fma_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x00]
+
+v_fma_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x9e,0x01]
+
+v_fma_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xa2,0x01]
+
+v_fma_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xa6,0x01]
+
+v_fma_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xaa,0x01]
+
+v_fma_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xae,0x01]
+
+v_fma_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xb2,0x01]
+
+v_fma_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xb6,0x01]
+
+v_fma_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xba,0x01]
+
+v_fma_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xbe,0x01]
+
+v_fma_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xee,0x01]
+
+v_fma_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xf2,0x01]
+
+v_fma_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xfa,0x01]
+
+v_fma_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xfe,0x01]
+
+v_fma_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x02]
+
+v_fma_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x06,0x03]
+
+v_fma_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xc2,0x03]
+
+v_fma_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xde,0x03]
+
+v_fma_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xee,0x03]
+
+v_fma_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xf2,0x03]
+
+v_fma_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0xf6,0x03]
+
+v_fma_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x24]
+
+v_fma_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x44]
+
+v_fma_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x84]
+
+v_fma_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_fma_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x96,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x96,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x96,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x96,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0x96,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_fma_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x14]
+
+v_fma_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x00,0x98,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0xfe,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[2:3], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x02,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[4:5], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x04,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[102:103], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x66,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x68,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], tba, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], tma, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x7a,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], exec, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x80,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], src_vccz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], src_execz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], src_scc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfd,0x0f,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[4:5], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x09,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[6:7], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x0d,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[102:103], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], tba, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], tma, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf5,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], exec, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x01,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x83,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xef,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xfa,0x07]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[6:7]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x1a,0x00]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[8:9]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x22,0x00]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[102:103]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x9a,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], flat_scratch
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xa2,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xaa,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], tba
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xb2,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], tma
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xba,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xea,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], exec
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xfa,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], 0
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x02,0x02]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -1
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x06,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xc2,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xde,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], src_vccz
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xee,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], src_execz
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xf2,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], src_scc
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0xf6,0x03]
+
+v_fma_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x24]
+
+v_fma_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x44]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x84]
+
+v_fma_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_fma_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// CHECK: [0x05,0x01,0x98,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// CHECK: [0x05,0x02,0x98,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// CHECK: [0x05,0x04,0x98,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// CHECK: [0x05,0x07,0x98,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// CHECK: [0x05,0x08,0x98,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x14]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_lerp_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x0e,0x04]
+
+v_lerp_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x9a,0xd2,0x01,0x05,0x0e,0x04]
+
+v_lerp_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0xff,0x05,0x0e,0x04]
+
+v_lerp_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x67,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x68,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x69,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x80,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xff,0x0f,0x04]
+
+v_lerp_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x0c,0x04]
+
+v_lerp_u8 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_lerp_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_lerp_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_lerp_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_lerp_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_lerp_u8 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_lerp_u8 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_lerp_u8 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_lerp_u8 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_lerp_u8 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_lerp_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_lerp_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_lerp_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xff,0x0c,0x04]
+
+v_lerp_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x01,0x0d,0x04]
+
+v_lerp_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x83,0x0d,0x04]
+
+v_lerp_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_lerp_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_lerp_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_lerp_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xfe,0x07]
+
+v_lerp_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x0e,0x00]
+
+v_lerp_u8 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x9e,0x01]
+
+v_lerp_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xa2,0x01]
+
+v_lerp_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xa6,0x01]
+
+v_lerp_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xaa,0x01]
+
+v_lerp_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xae,0x01]
+
+v_lerp_u8 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xb2,0x01]
+
+v_lerp_u8 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xb6,0x01]
+
+v_lerp_u8 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xba,0x01]
+
+v_lerp_u8 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xbe,0x01]
+
+v_lerp_u8 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xee,0x01]
+
+v_lerp_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xf2,0x01]
+
+v_lerp_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xfa,0x01]
+
+v_lerp_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xfe,0x01]
+
+v_lerp_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x02]
+
+v_lerp_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x06,0x03]
+
+v_lerp_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xee,0x03]
+
+v_lerp_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xf2,0x03]
+
+v_lerp_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0xf6,0x03]
+
+v_alignbit_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x0e,0x04]
+
+v_alignbit_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x9c,0xd2,0x01,0x05,0x0e,0x04]
+
+v_alignbit_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0xff,0x05,0x0e,0x04]
+
+v_alignbit_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x67,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x68,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x69,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x80,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xff,0x0f,0x04]
+
+v_alignbit_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xff,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x01,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x83,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xef,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xfe,0x07]
+
+v_alignbit_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x0e,0x00]
+
+v_alignbit_b32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x9e,0x01]
+
+v_alignbit_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xa2,0x01]
+
+v_alignbit_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xa6,0x01]
+
+v_alignbit_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xaa,0x01]
+
+v_alignbit_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xae,0x01]
+
+v_alignbit_b32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xb2,0x01]
+
+v_alignbit_b32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xb6,0x01]
+
+v_alignbit_b32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xba,0x01]
+
+v_alignbit_b32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xbe,0x01]
+
+v_alignbit_b32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xee,0x01]
+
+v_alignbit_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xf2,0x01]
+
+v_alignbit_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xfa,0x01]
+
+v_alignbit_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xfe,0x01]
+
+v_alignbit_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x02,0x02]
+
+v_alignbit_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x06,0x03]
+
+v_alignbit_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xc2,0x03]
+
+v_alignbit_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xde,0x03]
+
+v_alignbit_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xee,0x03]
+
+v_alignbit_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xf2,0x03]
+
+v_alignbit_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0xf6,0x03]
+
+v_alignbyte_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x9e,0xd2,0x01,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0xff,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x67,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x68,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x69,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x80,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xff,0x0f,0x04]
+
+v_alignbyte_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xff,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x01,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x83,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xef,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xfe,0x07]
+
+v_alignbyte_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x0e,0x00]
+
+v_alignbyte_b32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x9e,0x01]
+
+v_alignbyte_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xa2,0x01]
+
+v_alignbyte_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xa6,0x01]
+
+v_alignbyte_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xaa,0x01]
+
+v_alignbyte_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xae,0x01]
+
+v_alignbyte_b32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xb2,0x01]
+
+v_alignbyte_b32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xb6,0x01]
+
+v_alignbyte_b32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xba,0x01]
+
+v_alignbyte_b32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xbe,0x01]
+
+v_alignbyte_b32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xee,0x01]
+
+v_alignbyte_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xf2,0x01]
+
+v_alignbyte_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xfa,0x01]
+
+v_alignbyte_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xfe,0x01]
+
+v_alignbyte_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x02,0x02]
+
+v_alignbyte_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x06,0x03]
+
+v_alignbyte_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xc2,0x03]
+
+v_alignbyte_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xde,0x03]
+
+v_alignbyte_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xee,0x03]
+
+v_alignbyte_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xf2,0x03]
+
+v_alignbyte_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mullit_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x68,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x69,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mullit_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mullit_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mullit_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mullit_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_mullit_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_mullit_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mullit_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mullit_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_mullit_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_mullit_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_mullit_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_mullit_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mullit_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mullit_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mullit_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mullit_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mullit_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mullit_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mullit_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xef,0x0d,0x04]
+
+v_mullit_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mullit_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mullit_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mullit_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xfe,0x07]
+
+v_mullit_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x00]
+
+v_mullit_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x9e,0x01]
+
+v_mullit_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xa2,0x01]
+
+v_mullit_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xa6,0x01]
+
+v_mullit_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mullit_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xae,0x01]
+
+v_mullit_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xb2,0x01]
+
+v_mullit_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xb6,0x01]
+
+v_mullit_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xba,0x01]
+
+v_mullit_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xbe,0x01]
+
+v_mullit_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xee,0x01]
+
+v_mullit_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xf2,0x01]
+
+v_mullit_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mullit_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xfe,0x01]
+
+v_mullit_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x02]
+
+v_mullit_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x06,0x03]
+
+v_mullit_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mullit_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xde,0x03]
+
+v_mullit_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xee,0x03]
+
+v_mullit_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mullit_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mullit_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x24]
+
+v_mullit_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x44]
+
+v_mullit_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x84]
+
+v_mullit_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_mullit_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xa0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xa0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xa0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xa0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0xa0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mullit_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_mullit_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x14]
+
+v_mullit_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_min3_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0xff,0x05,0x0e,0x04]
+
+v_min3_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x04,0x0e,0x04]
+
+v_min3_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x67,0x04,0x0e,0x04]
+
+v_min3_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x68,0x04,0x0e,0x04]
+
+v_min3_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x69,0x04,0x0e,0x04]
+
+v_min3_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_min3_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_min3_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_min3_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_min3_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_min3_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_min3_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_min3_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_min3_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_min3_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_min3_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x80,0x04,0x0e,0x04]
+
+v_min3_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_min3_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_min3_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_min3_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xff,0x0f,0x04]
+
+v_min3_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0c,0x04]
+
+v_min3_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_min3_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_min3_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_min3_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_min3_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_min3_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_min3_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_min3_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_min3_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_min3_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_min3_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_min3_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_min3_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xff,0x0c,0x04]
+
+v_min3_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x01,0x0d,0x04]
+
+v_min3_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x83,0x0d,0x04]
+
+v_min3_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_min3_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xef,0x0d,0x04]
+
+v_min3_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_min3_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_min3_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_min3_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xfe,0x07]
+
+v_min3_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x00]
+
+v_min3_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x9e,0x01]
+
+v_min3_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xa2,0x01]
+
+v_min3_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xa6,0x01]
+
+v_min3_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xaa,0x01]
+
+v_min3_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xae,0x01]
+
+v_min3_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xb2,0x01]
+
+v_min3_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xb6,0x01]
+
+v_min3_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xba,0x01]
+
+v_min3_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xbe,0x01]
+
+v_min3_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xee,0x01]
+
+v_min3_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xf2,0x01]
+
+v_min3_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xfa,0x01]
+
+v_min3_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xfe,0x01]
+
+v_min3_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x02,0x02]
+
+v_min3_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x06,0x03]
+
+v_min3_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xc2,0x03]
+
+v_min3_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xde,0x03]
+
+v_min3_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xee,0x03]
+
+v_min3_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xf2,0x03]
+
+v_min3_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0xf6,0x03]
+
+v_min3_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x24]
+
+v_min3_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x44]
+
+v_min3_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x84]
+
+v_min3_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_min3_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xa2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xa2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xa2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xa2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0xa2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_min3_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x14]
+
+v_min3_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xa2,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_min3_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xa4,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0xff,0x05,0x0e,0x04]
+
+v_min3_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x04,0x0e,0x04]
+
+v_min3_i32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x67,0x04,0x0e,0x04]
+
+v_min3_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x68,0x04,0x0e,0x04]
+
+v_min3_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x69,0x04,0x0e,0x04]
+
+v_min3_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_min3_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_min3_i32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_min3_i32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_min3_i32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_min3_i32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_min3_i32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_min3_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_min3_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_min3_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_min3_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x80,0x04,0x0e,0x04]
+
+v_min3_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_min3_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_min3_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_min3_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xff,0x0f,0x04]
+
+v_min3_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x0c,0x04]
+
+v_min3_i32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_min3_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_min3_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_min3_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_min3_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_min3_i32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_min3_i32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_min3_i32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_min3_i32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_min3_i32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_min3_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_min3_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_min3_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xff,0x0c,0x04]
+
+v_min3_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x01,0x0d,0x04]
+
+v_min3_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x83,0x0d,0x04]
+
+v_min3_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_min3_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xef,0x0d,0x04]
+
+v_min3_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_min3_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_min3_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_min3_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xfe,0x07]
+
+v_min3_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x0e,0x00]
+
+v_min3_i32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x9e,0x01]
+
+v_min3_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xa2,0x01]
+
+v_min3_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xa6,0x01]
+
+v_min3_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xaa,0x01]
+
+v_min3_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xae,0x01]
+
+v_min3_i32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xb2,0x01]
+
+v_min3_i32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xb6,0x01]
+
+v_min3_i32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xba,0x01]
+
+v_min3_i32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xbe,0x01]
+
+v_min3_i32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xee,0x01]
+
+v_min3_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xf2,0x01]
+
+v_min3_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xfa,0x01]
+
+v_min3_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xfe,0x01]
+
+v_min3_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x02,0x02]
+
+v_min3_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0x06,0x03]
+
+v_min3_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xc2,0x03]
+
+v_min3_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xde,0x03]
+
+v_min3_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xee,0x03]
+
+v_min3_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xf2,0x03]
+
+v_min3_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xa4,0xd2,0x01,0x05,0xf6,0x03]
+
+v_min3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xa6,0xd2,0x01,0x05,0x0e,0x04]
+
+v_min3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0xff,0x05,0x0e,0x04]
+
+v_min3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x04,0x0e,0x04]
+
+v_min3_u32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x67,0x04,0x0e,0x04]
+
+v_min3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x68,0x04,0x0e,0x04]
+
+v_min3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x69,0x04,0x0e,0x04]
+
+v_min3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_min3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_min3_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_min3_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_min3_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_min3_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_min3_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_min3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_min3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_min3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_min3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x80,0x04,0x0e,0x04]
+
+v_min3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_min3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_min3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_min3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xff,0x0f,0x04]
+
+v_min3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x0c,0x04]
+
+v_min3_u32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_min3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_min3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_min3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_min3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_min3_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_min3_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_min3_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_min3_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_min3_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_min3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_min3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_min3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xff,0x0c,0x04]
+
+v_min3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x01,0x0d,0x04]
+
+v_min3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x83,0x0d,0x04]
+
+v_min3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_min3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xef,0x0d,0x04]
+
+v_min3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_min3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_min3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_min3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xfe,0x07]
+
+v_min3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x0e,0x00]
+
+v_min3_u32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x9e,0x01]
+
+v_min3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xa2,0x01]
+
+v_min3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xa6,0x01]
+
+v_min3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xaa,0x01]
+
+v_min3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xae,0x01]
+
+v_min3_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xb2,0x01]
+
+v_min3_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xb6,0x01]
+
+v_min3_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xba,0x01]
+
+v_min3_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xbe,0x01]
+
+v_min3_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xee,0x01]
+
+v_min3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xf2,0x01]
+
+v_min3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xfa,0x01]
+
+v_min3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xfe,0x01]
+
+v_min3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x02,0x02]
+
+v_min3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0x06,0x03]
+
+v_min3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xc2,0x03]
+
+v_min3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xde,0x03]
+
+v_min3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xee,0x03]
+
+v_min3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xf2,0x03]
+
+v_min3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xa6,0xd2,0x01,0x05,0xf6,0x03]
+
+v_max3_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0xff,0x05,0x0e,0x04]
+
+v_max3_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x04,0x0e,0x04]
+
+v_max3_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x67,0x04,0x0e,0x04]
+
+v_max3_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x68,0x04,0x0e,0x04]
+
+v_max3_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x69,0x04,0x0e,0x04]
+
+v_max3_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_max3_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_max3_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_max3_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_max3_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_max3_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_max3_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_max3_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_max3_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_max3_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_max3_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x80,0x04,0x0e,0x04]
+
+v_max3_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_max3_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_max3_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_max3_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xff,0x0f,0x04]
+
+v_max3_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0c,0x04]
+
+v_max3_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_max3_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_max3_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_max3_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_max3_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_max3_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_max3_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_max3_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_max3_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_max3_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_max3_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_max3_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_max3_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xff,0x0c,0x04]
+
+v_max3_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x01,0x0d,0x04]
+
+v_max3_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x83,0x0d,0x04]
+
+v_max3_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_max3_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xef,0x0d,0x04]
+
+v_max3_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_max3_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_max3_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_max3_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xfe,0x07]
+
+v_max3_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x00]
+
+v_max3_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x9e,0x01]
+
+v_max3_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xa2,0x01]
+
+v_max3_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xa6,0x01]
+
+v_max3_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xaa,0x01]
+
+v_max3_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xae,0x01]
+
+v_max3_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xb2,0x01]
+
+v_max3_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xb6,0x01]
+
+v_max3_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xba,0x01]
+
+v_max3_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xbe,0x01]
+
+v_max3_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xee,0x01]
+
+v_max3_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xf2,0x01]
+
+v_max3_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xfa,0x01]
+
+v_max3_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xfe,0x01]
+
+v_max3_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x02,0x02]
+
+v_max3_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x06,0x03]
+
+v_max3_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xc2,0x03]
+
+v_max3_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xde,0x03]
+
+v_max3_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xee,0x03]
+
+v_max3_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xf2,0x03]
+
+v_max3_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0xf6,0x03]
+
+v_max3_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x24]
+
+v_max3_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x44]
+
+v_max3_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x84]
+
+v_max3_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_max3_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xa8,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xa8,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xa8,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xa8,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0xa8,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_max3_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x14]
+
+v_max3_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xa8,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_max3_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xaa,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0xff,0x05,0x0e,0x04]
+
+v_max3_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x04,0x0e,0x04]
+
+v_max3_i32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x67,0x04,0x0e,0x04]
+
+v_max3_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x68,0x04,0x0e,0x04]
+
+v_max3_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x69,0x04,0x0e,0x04]
+
+v_max3_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_max3_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_max3_i32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_max3_i32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_max3_i32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_max3_i32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_max3_i32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_max3_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_max3_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_max3_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_max3_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x80,0x04,0x0e,0x04]
+
+v_max3_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_max3_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_max3_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_max3_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xff,0x0f,0x04]
+
+v_max3_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x0c,0x04]
+
+v_max3_i32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_max3_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_max3_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_max3_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_max3_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_max3_i32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_max3_i32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_max3_i32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_max3_i32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_max3_i32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_max3_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_max3_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_max3_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xff,0x0c,0x04]
+
+v_max3_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x01,0x0d,0x04]
+
+v_max3_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x83,0x0d,0x04]
+
+v_max3_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_max3_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xef,0x0d,0x04]
+
+v_max3_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_max3_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_max3_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_max3_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xfe,0x07]
+
+v_max3_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x0e,0x00]
+
+v_max3_i32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x9e,0x01]
+
+v_max3_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xa2,0x01]
+
+v_max3_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xa6,0x01]
+
+v_max3_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xaa,0x01]
+
+v_max3_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xae,0x01]
+
+v_max3_i32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xb2,0x01]
+
+v_max3_i32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xb6,0x01]
+
+v_max3_i32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xba,0x01]
+
+v_max3_i32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xbe,0x01]
+
+v_max3_i32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xee,0x01]
+
+v_max3_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xf2,0x01]
+
+v_max3_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xfa,0x01]
+
+v_max3_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xfe,0x01]
+
+v_max3_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x02,0x02]
+
+v_max3_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0x06,0x03]
+
+v_max3_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xc2,0x03]
+
+v_max3_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xde,0x03]
+
+v_max3_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xee,0x03]
+
+v_max3_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xf2,0x03]
+
+v_max3_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xaa,0xd2,0x01,0x05,0xf6,0x03]
+
+v_max3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xac,0xd2,0x01,0x05,0x0e,0x04]
+
+v_max3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0xff,0x05,0x0e,0x04]
+
+v_max3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x04,0x0e,0x04]
+
+v_max3_u32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x67,0x04,0x0e,0x04]
+
+v_max3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x68,0x04,0x0e,0x04]
+
+v_max3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x69,0x04,0x0e,0x04]
+
+v_max3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_max3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_max3_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_max3_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_max3_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_max3_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_max3_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_max3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_max3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_max3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_max3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x80,0x04,0x0e,0x04]
+
+v_max3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_max3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_max3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_max3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xff,0x0f,0x04]
+
+v_max3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x0c,0x04]
+
+v_max3_u32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_max3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_max3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_max3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_max3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_max3_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_max3_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_max3_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_max3_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_max3_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_max3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_max3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_max3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xff,0x0c,0x04]
+
+v_max3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x01,0x0d,0x04]
+
+v_max3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x83,0x0d,0x04]
+
+v_max3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_max3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xef,0x0d,0x04]
+
+v_max3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_max3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_max3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_max3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xfe,0x07]
+
+v_max3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x0e,0x00]
+
+v_max3_u32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x9e,0x01]
+
+v_max3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xa2,0x01]
+
+v_max3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xa6,0x01]
+
+v_max3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xaa,0x01]
+
+v_max3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xae,0x01]
+
+v_max3_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xb2,0x01]
+
+v_max3_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xb6,0x01]
+
+v_max3_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xba,0x01]
+
+v_max3_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xbe,0x01]
+
+v_max3_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xee,0x01]
+
+v_max3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xf2,0x01]
+
+v_max3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xfa,0x01]
+
+v_max3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xfe,0x01]
+
+v_max3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x02,0x02]
+
+v_max3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0x06,0x03]
+
+v_max3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xc2,0x03]
+
+v_max3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xde,0x03]
+
+v_max3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xee,0x03]
+
+v_max3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xf2,0x03]
+
+v_max3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xac,0xd2,0x01,0x05,0xf6,0x03]
+
+v_med3_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xae,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0xff,0x05,0x0e,0x04]
+
+v_med3_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x04,0x0e,0x04]
+
+v_med3_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x67,0x04,0x0e,0x04]
+
+v_med3_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x68,0x04,0x0e,0x04]
+
+v_med3_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x69,0x04,0x0e,0x04]
+
+v_med3_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_med3_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_med3_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_med3_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_med3_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_med3_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_med3_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_med3_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_med3_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_med3_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_med3_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x80,0x04,0x0e,0x04]
+
+v_med3_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_med3_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_med3_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_med3_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xff,0x0f,0x04]
+
+v_med3_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0c,0x04]
+
+v_med3_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_med3_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_med3_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_med3_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_med3_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_med3_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_med3_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_med3_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_med3_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_med3_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_med3_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_med3_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_med3_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xff,0x0c,0x04]
+
+v_med3_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x01,0x0d,0x04]
+
+v_med3_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x83,0x0d,0x04]
+
+v_med3_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_med3_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xef,0x0d,0x04]
+
+v_med3_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_med3_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_med3_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_med3_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xfe,0x07]
+
+v_med3_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x00]
+
+v_med3_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x9e,0x01]
+
+v_med3_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xa2,0x01]
+
+v_med3_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xa6,0x01]
+
+v_med3_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xaa,0x01]
+
+v_med3_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xae,0x01]
+
+v_med3_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xb2,0x01]
+
+v_med3_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xb6,0x01]
+
+v_med3_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xba,0x01]
+
+v_med3_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xbe,0x01]
+
+v_med3_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xee,0x01]
+
+v_med3_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xf2,0x01]
+
+v_med3_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xfa,0x01]
+
+v_med3_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xfe,0x01]
+
+v_med3_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x02,0x02]
+
+v_med3_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x06,0x03]
+
+v_med3_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xc2,0x03]
+
+v_med3_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xde,0x03]
+
+v_med3_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xee,0x03]
+
+v_med3_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xf2,0x03]
+
+v_med3_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0xf6,0x03]
+
+v_med3_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x24]
+
+v_med3_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x44]
+
+v_med3_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x84]
+
+v_med3_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_med3_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xae,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xae,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xae,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xae,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0xae,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_med3_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x14]
+
+v_med3_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xae,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_med3_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xb0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0xff,0x05,0x0e,0x04]
+
+v_med3_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x04,0x0e,0x04]
+
+v_med3_i32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x67,0x04,0x0e,0x04]
+
+v_med3_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x68,0x04,0x0e,0x04]
+
+v_med3_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x69,0x04,0x0e,0x04]
+
+v_med3_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_med3_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_med3_i32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_med3_i32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_med3_i32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_med3_i32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_med3_i32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_med3_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_med3_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_med3_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_med3_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x80,0x04,0x0e,0x04]
+
+v_med3_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_med3_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_med3_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_med3_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xff,0x0f,0x04]
+
+v_med3_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x0c,0x04]
+
+v_med3_i32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_med3_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_med3_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_med3_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_med3_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_med3_i32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_med3_i32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_med3_i32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_med3_i32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_med3_i32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_med3_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_med3_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_med3_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xff,0x0c,0x04]
+
+v_med3_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x01,0x0d,0x04]
+
+v_med3_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x83,0x0d,0x04]
+
+v_med3_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_med3_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xef,0x0d,0x04]
+
+v_med3_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_med3_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_med3_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_med3_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xfe,0x07]
+
+v_med3_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x0e,0x00]
+
+v_med3_i32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x9e,0x01]
+
+v_med3_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xa2,0x01]
+
+v_med3_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xa6,0x01]
+
+v_med3_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xaa,0x01]
+
+v_med3_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xae,0x01]
+
+v_med3_i32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xb2,0x01]
+
+v_med3_i32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xb6,0x01]
+
+v_med3_i32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xba,0x01]
+
+v_med3_i32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xbe,0x01]
+
+v_med3_i32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xee,0x01]
+
+v_med3_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xf2,0x01]
+
+v_med3_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xfa,0x01]
+
+v_med3_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xfe,0x01]
+
+v_med3_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x02,0x02]
+
+v_med3_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0x06,0x03]
+
+v_med3_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xc2,0x03]
+
+v_med3_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xde,0x03]
+
+v_med3_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xee,0x03]
+
+v_med3_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xf2,0x03]
+
+v_med3_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xb0,0xd2,0x01,0x05,0xf6,0x03]
+
+v_med3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xb2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_med3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0xff,0x05,0x0e,0x04]
+
+v_med3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x04,0x0e,0x04]
+
+v_med3_u32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x67,0x04,0x0e,0x04]
+
+v_med3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x68,0x04,0x0e,0x04]
+
+v_med3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x69,0x04,0x0e,0x04]
+
+v_med3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_med3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_med3_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_med3_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_med3_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_med3_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_med3_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_med3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_med3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_med3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_med3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x80,0x04,0x0e,0x04]
+
+v_med3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_med3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_med3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_med3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xff,0x0f,0x04]
+
+v_med3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x0c,0x04]
+
+v_med3_u32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_med3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_med3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_med3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_med3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_med3_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_med3_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_med3_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_med3_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_med3_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_med3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_med3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_med3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xff,0x0c,0x04]
+
+v_med3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x01,0x0d,0x04]
+
+v_med3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x83,0x0d,0x04]
+
+v_med3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_med3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xef,0x0d,0x04]
+
+v_med3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_med3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_med3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_med3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xfe,0x07]
+
+v_med3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x0e,0x00]
+
+v_med3_u32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x9e,0x01]
+
+v_med3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xa2,0x01]
+
+v_med3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xa6,0x01]
+
+v_med3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xaa,0x01]
+
+v_med3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xae,0x01]
+
+v_med3_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xb2,0x01]
+
+v_med3_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xb6,0x01]
+
+v_med3_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xba,0x01]
+
+v_med3_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xbe,0x01]
+
+v_med3_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xee,0x01]
+
+v_med3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xf2,0x01]
+
+v_med3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xfa,0x01]
+
+v_med3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xfe,0x01]
+
+v_med3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x02,0x02]
+
+v_med3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0x06,0x03]
+
+v_med3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xc2,0x03]
+
+v_med3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xde,0x03]
+
+v_med3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xee,0x03]
+
+v_med3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xf2,0x03]
+
+v_med3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xb2,0xd2,0x01,0x05,0xf6,0x03]
+
+v_sad_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x0e,0x04]
+
+v_sad_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xb4,0xd2,0x01,0x05,0x0e,0x04]
+
+v_sad_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0xff,0x05,0x0e,0x04]
+
+v_sad_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x04,0x0e,0x04]
+
+v_sad_u8 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x67,0x04,0x0e,0x04]
+
+v_sad_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x68,0x04,0x0e,0x04]
+
+v_sad_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x69,0x04,0x0e,0x04]
+
+v_sad_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_sad_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_sad_u8 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_sad_u8 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_sad_u8 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_sad_u8 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_sad_u8 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_sad_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_sad_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_sad_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_sad_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x80,0x04,0x0e,0x04]
+
+v_sad_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_sad_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xff,0x0f,0x04]
+
+v_sad_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x0c,0x04]
+
+v_sad_u8 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_sad_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_sad_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_sad_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_sad_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_sad_u8 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_sad_u8 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_sad_u8 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_sad_u8 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_sad_u8 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_sad_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_sad_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_sad_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xff,0x0c,0x04]
+
+v_sad_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x01,0x0d,0x04]
+
+v_sad_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x83,0x0d,0x04]
+
+v_sad_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_sad_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_sad_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_sad_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xfe,0x07]
+
+v_sad_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x0e,0x00]
+
+v_sad_u8 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x9e,0x01]
+
+v_sad_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xa2,0x01]
+
+v_sad_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xa6,0x01]
+
+v_sad_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xaa,0x01]
+
+v_sad_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xae,0x01]
+
+v_sad_u8 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xb2,0x01]
+
+v_sad_u8 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xb6,0x01]
+
+v_sad_u8 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xba,0x01]
+
+v_sad_u8 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xbe,0x01]
+
+v_sad_u8 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xee,0x01]
+
+v_sad_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xf2,0x01]
+
+v_sad_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xfa,0x01]
+
+v_sad_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xfe,0x01]
+
+v_sad_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x02,0x02]
+
+v_sad_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0x06,0x03]
+
+v_sad_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xc2,0x03]
+
+v_sad_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xde,0x03]
+
+v_sad_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xee,0x03]
+
+v_sad_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xf2,0x03]
+
+v_sad_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xb4,0xd2,0x01,0x05,0xf6,0x03]
+
+v_sad_hi_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xb6,0xd2,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0xff,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x67,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x68,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x69,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x80,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xff,0x0f,0x04]
+
+v_sad_hi_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xff,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x01,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x83,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xfe,0x07]
+
+v_sad_hi_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x0e,0x00]
+
+v_sad_hi_u8 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x9e,0x01]
+
+v_sad_hi_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xa2,0x01]
+
+v_sad_hi_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xa6,0x01]
+
+v_sad_hi_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xaa,0x01]
+
+v_sad_hi_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xae,0x01]
+
+v_sad_hi_u8 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xb2,0x01]
+
+v_sad_hi_u8 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xb6,0x01]
+
+v_sad_hi_u8 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xba,0x01]
+
+v_sad_hi_u8 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xbe,0x01]
+
+v_sad_hi_u8 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xee,0x01]
+
+v_sad_hi_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xf2,0x01]
+
+v_sad_hi_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xfa,0x01]
+
+v_sad_hi_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xfe,0x01]
+
+v_sad_hi_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x02,0x02]
+
+v_sad_hi_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0x06,0x03]
+
+v_sad_hi_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xc2,0x03]
+
+v_sad_hi_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xde,0x03]
+
+v_sad_hi_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xee,0x03]
+
+v_sad_hi_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xf2,0x03]
+
+v_sad_hi_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xb6,0xd2,0x01,0x05,0xf6,0x03]
+
+v_sad_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xb8,0xd2,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0xff,0x05,0x0e,0x04]
+
+v_sad_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x04,0x0e,0x04]
+
+v_sad_u16 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x67,0x04,0x0e,0x04]
+
+v_sad_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x68,0x04,0x0e,0x04]
+
+v_sad_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x69,0x04,0x0e,0x04]
+
+v_sad_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_sad_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_sad_u16 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_sad_u16 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_sad_u16 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_sad_u16 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_sad_u16 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_sad_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_sad_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_sad_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_sad_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x80,0x04,0x0e,0x04]
+
+v_sad_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_sad_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xff,0x0f,0x04]
+
+v_sad_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x0c,0x04]
+
+v_sad_u16 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_sad_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_sad_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_sad_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_sad_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_sad_u16 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_sad_u16 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_sad_u16 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_sad_u16 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_sad_u16 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_sad_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_sad_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_sad_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xff,0x0c,0x04]
+
+v_sad_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x01,0x0d,0x04]
+
+v_sad_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x83,0x0d,0x04]
+
+v_sad_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_sad_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_sad_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_sad_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xfe,0x07]
+
+v_sad_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x0e,0x00]
+
+v_sad_u16 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x9e,0x01]
+
+v_sad_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xa2,0x01]
+
+v_sad_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xa6,0x01]
+
+v_sad_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xaa,0x01]
+
+v_sad_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xae,0x01]
+
+v_sad_u16 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xb2,0x01]
+
+v_sad_u16 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xb6,0x01]
+
+v_sad_u16 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xba,0x01]
+
+v_sad_u16 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xbe,0x01]
+
+v_sad_u16 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xee,0x01]
+
+v_sad_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xf2,0x01]
+
+v_sad_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xfa,0x01]
+
+v_sad_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xfe,0x01]
+
+v_sad_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x02,0x02]
+
+v_sad_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0x06,0x03]
+
+v_sad_u16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xc2,0x03]
+
+v_sad_u16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xde,0x03]
+
+v_sad_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xee,0x03]
+
+v_sad_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xf2,0x03]
+
+v_sad_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xb8,0xd2,0x01,0x05,0xf6,0x03]
+
+v_sad_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xba,0xd2,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0xff,0x05,0x0e,0x04]
+
+v_sad_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x04,0x0e,0x04]
+
+v_sad_u32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x67,0x04,0x0e,0x04]
+
+v_sad_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x68,0x04,0x0e,0x04]
+
+v_sad_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x69,0x04,0x0e,0x04]
+
+v_sad_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_sad_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_sad_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_sad_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_sad_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_sad_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_sad_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_sad_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_sad_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_sad_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_sad_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x80,0x04,0x0e,0x04]
+
+v_sad_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_sad_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_sad_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_sad_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xff,0x0f,0x04]
+
+v_sad_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x0c,0x04]
+
+v_sad_u32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_sad_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_sad_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_sad_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_sad_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_sad_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_sad_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_sad_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_sad_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_sad_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_sad_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_sad_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_sad_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xff,0x0c,0x04]
+
+v_sad_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x01,0x0d,0x04]
+
+v_sad_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x83,0x0d,0x04]
+
+v_sad_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_sad_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xef,0x0d,0x04]
+
+v_sad_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_sad_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_sad_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_sad_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xfe,0x07]
+
+v_sad_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x0e,0x00]
+
+v_sad_u32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x9e,0x01]
+
+v_sad_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xa2,0x01]
+
+v_sad_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xa6,0x01]
+
+v_sad_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xaa,0x01]
+
+v_sad_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xae,0x01]
+
+v_sad_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xb2,0x01]
+
+v_sad_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xb6,0x01]
+
+v_sad_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xba,0x01]
+
+v_sad_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xbe,0x01]
+
+v_sad_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xee,0x01]
+
+v_sad_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xf2,0x01]
+
+v_sad_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xfa,0x01]
+
+v_sad_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xfe,0x01]
+
+v_sad_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x02,0x02]
+
+v_sad_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0x06,0x03]
+
+v_sad_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xc2,0x03]
+
+v_sad_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xde,0x03]
+
+v_sad_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xee,0x03]
+
+v_sad_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xf2,0x03]
+
+v_sad_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xba,0xd2,0x01,0x05,0xf6,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xbc,0xd2,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0xff,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x67,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x68,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x69,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x80,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xff,0x0f,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xff,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x01,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x83,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xef,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xfe,0x07]
+
+v_cvt_pk_u8_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x0e,0x00]
+
+v_cvt_pk_u8_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x9e,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xa2,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xa6,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xaa,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xae,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xb2,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xb6,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xba,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xbe,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xee,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xf2,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xfa,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xfe,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x02,0x02]
+
+v_cvt_pk_u8_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0x06,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xc2,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xde,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xee,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xf2,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xbc,0xd2,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0xff,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x67,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x68,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x69,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xff,0x0f,0x04]
+
+v_div_fixup_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xff,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xfe,0x07]
+
+v_div_fixup_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x00]
+
+v_div_fixup_f32 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x9e,0x01]
+
+v_div_fixup_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xa2,0x01]
+
+v_div_fixup_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xa6,0x01]
+
+v_div_fixup_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xae,0x01]
+
+v_div_fixup_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xb2,0x01]
+
+v_div_fixup_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xb6,0x01]
+
+v_div_fixup_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xba,0x01]
+
+v_div_fixup_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xbe,0x01]
+
+v_div_fixup_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xee,0x01]
+
+v_div_fixup_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xf2,0x01]
+
+v_div_fixup_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xfe,0x01]
+
+v_div_fixup_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xee,0x03]
+
+v_div_fixup_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xf2,0x03]
+
+v_div_fixup_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xbe,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xbe,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xbe,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xbe,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0xbe,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_div_fixup_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x14]
+
+v_div_fixup_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xbe,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0xfe,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[2:3], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x02,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[4:5], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x04,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[102:103], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x66,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x68,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], tba, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], tma, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x7a,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], exec, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], src_vccz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], src_execz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], src_scc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xfd,0x0f,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[4:5], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x09,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[6:7], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x0d,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[102:103], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], tba, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], tma, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xf5,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], exec, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xfa,0x07]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[6:7]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x1a,0x00]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[8:9]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x22,0x00]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[102:103]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x9a,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], flat_scratch
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xa2,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], tba
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xb2,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], tma
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xba,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xea,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], exec
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -1
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], src_vccz
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xee,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], src_execz
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xf2,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], src_scc
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// CHECK: [0x05,0x01,0xc0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// CHECK: [0x05,0x02,0xc0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// CHECK: [0x05,0x04,0xc0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// CHECK: [0x05,0x07,0xc0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// CHECK: [0x05,0x08,0xc0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x14]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// CHECK: [0x05,0x00,0xc0,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_lshl_b64 v[5:6], v[1:2], v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshl_b64 v[254:255], v[1:2], v2
+// CHECK: [0xfe,0x00,0xc2,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshl_b64 v[5:6], v[254:255], v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0xfe,0x05,0x02,0x00]
+
+v_lshl_b64 v[5:6], s[2:3], v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x02,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], s[4:5], v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x04,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], s[102:103], v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x66,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], flat_scratch, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x68,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], vcc, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], tba, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x6c,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], tma, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x6e,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], ttmp[10:11], v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x7a,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], exec, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], 0, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], -1, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], 0.5, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], -4.0, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], src_vccz, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], src_execz, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], src_scc, v2
+// CHECK: [0x05,0x00,0xc2,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], v255
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xff,0x03,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], s2
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0x05,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], s103
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xcf,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], flat_scratch_lo
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd1,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], flat_scratch_hi
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd3,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], vcc_lo
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], vcc_hi
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd7,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], tba_lo
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xd9,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], tba_hi
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xdb,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], tma_lo
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xdd,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], tma_hi
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xdf,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], ttmp11
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xf7,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], m0
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xf9,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], exec_lo
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], exec_hi
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xff,0x00,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshl_b64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0xc2,0xd2,0x01,0xfb,0x01,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshr_b64 v[254:255], v[1:2], v2
+// CHECK: [0xfe,0x00,0xc4,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshr_b64 v[5:6], v[254:255], v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0xfe,0x05,0x02,0x00]
+
+v_lshr_b64 v[5:6], s[2:3], v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x02,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], s[4:5], v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x04,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], s[102:103], v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x66,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], flat_scratch, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x68,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], vcc, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], tba, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x6c,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], tma, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x6e,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], ttmp[10:11], v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x7a,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], exec, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], 0, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], -1, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], 0.5, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], -4.0, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], src_vccz, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], src_execz, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], src_scc, v2
+// CHECK: [0x05,0x00,0xc4,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], v255
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xff,0x03,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], s2
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0x05,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], s103
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xcf,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], flat_scratch_lo
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd1,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], flat_scratch_hi
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd3,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], vcc_lo
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], vcc_hi
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd7,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], tba_lo
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xd9,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], tba_hi
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xdb,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], tma_lo
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xdd,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], tma_hi
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xdf,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], ttmp11
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xf7,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], m0
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xf9,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], exec_lo
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], exec_hi
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xff,0x00,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshr_b64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0xc4,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashr_i64 v[254:255], v[1:2], v2
+// CHECK: [0xfe,0x00,0xc6,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashr_i64 v[5:6], v[254:255], v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0xfe,0x05,0x02,0x00]
+
+v_ashr_i64 v[5:6], s[2:3], v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x02,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], s[4:5], v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x04,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], s[102:103], v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x66,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], flat_scratch, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x68,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], vcc, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], tba, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x6c,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], tma, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x6e,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], ttmp[10:11], v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x7a,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], exec, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], 0, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x80,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], -1, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], 0.5, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], -4.0, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], src_vccz, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], src_execz, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], src_scc, v2
+// CHECK: [0x05,0x00,0xc6,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], v255
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xff,0x03,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], s2
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0x05,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], s103
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xcf,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], flat_scratch_lo
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd1,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], flat_scratch_hi
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd3,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], vcc_lo
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], vcc_hi
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd7,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], tba_lo
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xd9,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], tba_hi
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xdb,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], tma_lo
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xdd,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], tma_hi
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xdf,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], ttmp11
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xf7,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], m0
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xf9,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], exec_lo
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], exec_hi
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xff,0x00,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0x01,0x01,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0x83,0x01,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xef,0x01,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ashr_i64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0xc6,0xd2,0x01,0xfb,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0xc8,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0xfe,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x02,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x04,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], s[102:103], v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x66,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x68,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x6a,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], tba, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x6c,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], tma, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x6e,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], ttmp[10:11], v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x7a,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x7e,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x80,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0xc1,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0xf0,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0xf7,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0xfb,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0xfc,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0xfd,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xfd,0x03,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x09,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x0d,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[102:103]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xcd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xd1,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xd5,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], tba
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xd9,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], tma
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xdd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], ttmp[10:11]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xf5,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xfd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x01,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x83,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xe1,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xef,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xf7,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xf9,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0xfb,0x01,0x00]
+
+v_add_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x20]
+
+v_add_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x40]
+
+v_add_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x60]
+
+v_add_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0xc8,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0xc8,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0xc8,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x08,0xc8,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x08]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x10]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0xc8,0xd2,0x01,0x05,0x02,0x18]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0xca,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0xfe,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x02,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x04,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], s[102:103], v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x66,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], tba, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], tma, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], ttmp[10:11], v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x7a,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xfd,0x03,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x09,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x0d,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[102:103]
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], tba
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], tma
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], ttmp[10:11]
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xf5,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x20]
+
+v_mul_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x40]
+
+v_mul_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x60]
+
+v_mul_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0xca,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0xca,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0xca,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x08,0xca,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x08]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x10]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0xca,0xd2,0x01,0x05,0x02,0x18]
+
+v_min_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0xcc,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0xfe,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x02,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x04,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], s[102:103], v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x66,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x68,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x6a,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], tba, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x6c,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], tma, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x6e,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], ttmp[10:11], v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x7a,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x7e,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x80,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0xc1,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0xf0,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0xf7,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0xfb,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0xfc,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0xfd,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xfd,0x03,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x09,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x0d,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[102:103]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xcd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xd1,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xd5,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], tba
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xd9,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], tma
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xdd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], ttmp[10:11]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xf5,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xfd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x01,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x83,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xe1,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xef,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xf7,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xf9,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0xfb,0x01,0x00]
+
+v_min_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x20]
+
+v_min_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x40]
+
+v_min_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x60]
+
+v_min_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0xcc,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0xcc,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0xcc,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x08,0xcc,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x08]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x10]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0xcc,0xd2,0x01,0x05,0x02,0x18]
+
+v_max_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0xce,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0xfe,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x02,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x04,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], s[102:103], v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x66,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x68,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x6a,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], tba, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x6c,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], tma, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x6e,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], ttmp[10:11], v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x7a,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x7e,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x80,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0xc1,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0xf0,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0xf7,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0xfb,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0xfc,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0xfd,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xfd,0x03,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x09,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x0d,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[102:103]
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xcd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xd1,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xd5,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], tba
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xd9,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], tma
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xdd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], ttmp[10:11]
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xf5,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xfd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x01,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x83,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xe1,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xef,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xf7,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xf9,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0xfb,0x01,0x00]
+
+v_max_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x20]
+
+v_max_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x40]
+
+v_max_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x60]
+
+v_max_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0xce,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0xce,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0xce,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x08,0xce,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x08]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x10]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0xce,0xd2,0x01,0x05,0x02,0x18]
+
+v_ldexp_f64 v[5:6], v[1:2], v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[254:255], v[1:2], v2
+// CHECK: [0xfe,0x00,0xd0,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[254:255], v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0xfe,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[2:3], v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x02,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[4:5], v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x04,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[102:103], v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x66,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], flat_scratch, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x68,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], vcc, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], tba, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x6c,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], tma, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x6e,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], ttmp[10:11], v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x7a,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], exec, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], 0, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x80,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], -1, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], 0.5, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], -4.0, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], src_vccz, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], src_execz, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], src_scc, v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v255
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xff,0x03,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s103
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], flat_scratch_lo
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd1,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], flat_scratch_hi
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd3,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], vcc_lo
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], vcc_hi
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], tba_lo
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xd9,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], tba_hi
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xdb,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], tma_lo
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xdd,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], tma_hi
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xdf,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], ttmp11
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xf7,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], m0
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], exec_lo
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], exec_hi
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xff,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x01,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x83,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xef,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f64 v[5:6], -v[1:2], v2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x20]
+
+v_ldexp_f64 v[5:6], |v[1:2]|, v2
+// CHECK: [0x05,0x01,0xd0,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 clamp
+// CHECK: [0x05,0x08,0xd0,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 mul:2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x08]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 mul:4
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x10]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 div:2
+// CHECK: [0x05,0x00,0xd0,0xd2,0x01,0x05,0x02,0x18]
+
+v_mul_lo_u32 v5, v1, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u32 v255, v1, v2
+// CHECK: [0xff,0x00,0xd2,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u32 v5, v255, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_lo_u32 v5, s1, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, s103, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, m0, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, 0, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, -1, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0xd2,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, v1, v255
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_lo_u32 v5, v1, s2
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, s103
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, m0
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, 0
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, -1
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0xd2,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32 v255, v1, v2
+// CHECK: [0xff,0x00,0xd4,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32 v5, v255, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_hi_u32 v5, s1, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, s103, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, m0, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, 0, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, -1, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0xd4,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, v1, v255
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_hi_u32 v5, v1, s2
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, s103
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, m0
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, 0
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, -1
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0xd4,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_lo_i32 v5, v1, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v255, v1, v2
+// CHECK: [0xff,0x00,0xd6,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, v255, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_lo_i32 v5, s1, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, s103, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, m0, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, 0, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, -1, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0xd6,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_lo_i32 v5, v1, v255
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_lo_i32 v5, v1, s2
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, s103
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, m0
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_lo_i32 v5, v1, 0
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_lo_i32 v5, v1, -1
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_lo_i32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_lo_i32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_lo_i32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_lo_i32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_lo_i32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0xd6,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32 v255, v1, v2
+// CHECK: [0xff,0x00,0xd8,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32 v5, v255, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_hi_i32 v5, s1, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, s103, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x68,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x69,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, m0, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, 0, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, -1, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0xd8,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, v1, v255
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_hi_i32 v5, v1, s2
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, s103
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd1,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd3,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, m0
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, 0
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, -1
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0xd8,0xd2,0x01,0xfb,0x01,0x00]
+
+v_div_scale_f32 v5, vcc, v1, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f32 v255, vcc, v1, v2, v3
+// CHECK: [0xff,0x6a,0xda,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, v255, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0xff,0x05,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, s1, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, s103, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x67,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x68,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x69,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, vcc_lo, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, vcc_hi, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, tba_lo, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, tba_hi, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, tma_lo, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, tma_hi, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, ttmp11, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, m0, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, exec_lo, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, exec_hi, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, 0, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x80,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, -1, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, 0.5, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, -4.0, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_vccz, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_execz, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_scc, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_lds_direct, v2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, v1, v255, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xff,0x0f,0x04]
+
+v_div_scale_f32 v5, vcc, v1, s2, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, s103, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, vcc_lo, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, vcc_hi, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, tba_lo, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, tba_hi, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, tma_lo, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, tma_hi, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, ttmp11, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, m0, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, exec_lo, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, exec_hi, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xff,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, 0, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x01,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, -1, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x83,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, 0.5, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, -4.0, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xef,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, src_vccz, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, src_execz, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, src_scc, v3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, v2, v255
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xfe,0x07]
+
+v_div_scale_f32 v5, vcc, v1, v2, s3
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x0e,0x00]
+
+v_div_scale_f32 v5, vcc, v1, v2, s103
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x9e,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xa2,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xa6,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, vcc_lo
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xaa,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, vcc_hi
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xae,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, tba_lo
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xb2,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, tba_hi
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xb6,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, tma_lo
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xba,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, tma_hi
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xbe,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, ttmp11
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xee,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, m0
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xf2,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, exec_lo
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xfa,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, exec_hi
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xfe,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, 0
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x02,0x02]
+
+v_div_scale_f32 v5, vcc, v1, v2, -1
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0x06,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, 0.5
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xc2,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, -4.0
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xde,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, src_vccz
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xee,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, src_execz
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xf2,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, src_scc
+// CHECK: [0x05,0x6a,0xda,0xd2,0x01,0x05,0xf6,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f64 v[254:255], vcc, v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x6a,0xdc,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0xfe,0x05,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, s[2:3], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x02,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, s[4:5], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x04,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, s[102:103], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x66,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, flat_scratch, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x68,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, tba, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, tma, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, ttmp[10:11], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x7a,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, exec, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x80,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, src_vccz, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, src_execz, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, src_scc, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xfd,0x0f,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], s[4:5], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x09,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], s[6:7], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x0d,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], s[102:103], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], flat_scratch, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], tba, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], tma, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], ttmp[10:11], v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xf5,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], exec, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x01,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x83,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xef,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xfa,0x07]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[6:7]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x1a,0x00]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[8:9]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x22,0x00]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[102:103]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x9a,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], flat_scratch
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xa2,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xaa,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], tba
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xb2,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], tma
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xba,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], ttmp[10:11]
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xea,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], exec
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xfa,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x02,0x02]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -1
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0x06,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xc2,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xde,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], src_vccz
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xee,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], src_execz
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xf2,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], src_scc
+// CHECK: [0x05,0x6a,0xdc,0xd2,0x01,0x05,0xf6,0x03]
+
+v_div_fmas_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xde,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0xff,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x80,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0xff,0x0f,0x04]
+
+v_div_fmas_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x01,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x83,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0xef,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0xfe,0x07]
+
+v_div_fmas_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x02,0x02]
+
+v_div_fmas_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x06,0x03]
+
+v_div_fmas_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0xc2,0x03]
+
+v_div_fmas_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0xde,0x03]
+
+v_div_fmas_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x24]
+
+v_div_fmas_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x44]
+
+v_div_fmas_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x84]
+
+v_div_fmas_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_div_fmas_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xde,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xde,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xde,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xde,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x08,0xde,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_div_fmas_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x14]
+
+v_div_fmas_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xde,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0xfe,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x80,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0xfd,0x0f,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x01,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x83,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0xef,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0xfa,0x07]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0xaa,0x01]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x02,0x02]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -1
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x06,0x03]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0xc2,0x03]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0xde,0x03]
+
+v_div_fmas_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x24]
+
+v_div_fmas_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x44]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x84]
+
+v_div_fmas_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_div_fmas_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// CHECK: [0x05,0x01,0xe0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// CHECK: [0x05,0x02,0xe0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// CHECK: [0x05,0x04,0xe0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// CHECK: [0x05,0x07,0xe0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// CHECK: [0x05,0x08,0xe0,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x0c]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x14]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// CHECK: [0x05,0x00,0xe0,0xd2,0x01,0x05,0x0e,0x1c]
+
+v_msad_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_msad_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xe2,0xd2,0x01,0x05,0x0e,0x04]
+
+v_msad_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0xff,0x05,0x0e,0x04]
+
+v_msad_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x04,0x0e,0x04]
+
+v_msad_u8 v5, s103, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x67,0x04,0x0e,0x04]
+
+v_msad_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x68,0x04,0x0e,0x04]
+
+v_msad_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x69,0x04,0x0e,0x04]
+
+v_msad_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_msad_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_msad_u8 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_msad_u8 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_msad_u8 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_msad_u8 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_msad_u8 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_msad_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_msad_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_msad_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_msad_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x80,0x04,0x0e,0x04]
+
+v_msad_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_msad_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xff,0x0f,0x04]
+
+v_msad_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x0c,0x04]
+
+v_msad_u8 v5, v1, s103, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_msad_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_msad_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_msad_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_msad_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_msad_u8 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_msad_u8 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_msad_u8 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_msad_u8 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_msad_u8 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_msad_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_msad_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_msad_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xff,0x0c,0x04]
+
+v_msad_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x01,0x0d,0x04]
+
+v_msad_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x83,0x0d,0x04]
+
+v_msad_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_msad_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_msad_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_msad_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xfe,0x07]
+
+v_msad_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x0e,0x00]
+
+v_msad_u8 v5, v1, v2, s103
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x9e,0x01]
+
+v_msad_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xa2,0x01]
+
+v_msad_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xa6,0x01]
+
+v_msad_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xaa,0x01]
+
+v_msad_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xae,0x01]
+
+v_msad_u8 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xb2,0x01]
+
+v_msad_u8 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xb6,0x01]
+
+v_msad_u8 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xba,0x01]
+
+v_msad_u8 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xbe,0x01]
+
+v_msad_u8 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xee,0x01]
+
+v_msad_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xf2,0x01]
+
+v_msad_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xfa,0x01]
+
+v_msad_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xfe,0x01]
+
+v_msad_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x02,0x02]
+
+v_msad_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0x06,0x03]
+
+v_msad_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xee,0x03]
+
+v_msad_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xf2,0x03]
+
+v_msad_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xe2,0xd2,0x01,0x05,0xf6,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
+// CHECK: [0xfe,0x00,0xe4,0xd2,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0xfe,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x02,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x04,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[102:103], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x66,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x68,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], tba, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], tma, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x7a,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x80,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xff,0x0f,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s103, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], tba_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], tba_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], tma_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], tma_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xff,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x01,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x83,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xfa,0x07]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x1a,0x00]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x22,0x00]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[102:103]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x9a,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xa2,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xaa,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, tba
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xb2,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, tma
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xba,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xea,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xfa,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x02,0x02]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0x06,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, src_vccz
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xee,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, src_execz
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xf2,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, src_scc
+// CHECK: [0x05,0x00,0xe4,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
+// CHECK: [0xfe,0x00,0xe6,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0xfe,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x02,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x04,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[102:103], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x66,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x68,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], tba, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], tma, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x7a,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s103, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], tba_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], tba_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], tma_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], tma_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xfa,0x07]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x1a,0x00]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x22,0x00]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[102:103]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x9a,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xa2,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, tba
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xb2,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, tma
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xba,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xea,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x02,0x02]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0x06,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, src_vccz
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xee,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, src_execz
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, src_scc
+// CHECK: [0x05,0x00,0xe6,0xd2,0x01,0x05,0xf6,0x03]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[254:255], v[1:2], v2
+// CHECK: [0xfe,0x00,0xe8,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[254:255], v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0xfe,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[2:3], v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x02,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[4:5], v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x04,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[102:103], v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x66,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], flat_scratch, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x68,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], vcc, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x6a,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], tba, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x6c,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], tma, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x6e,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], ttmp[10:11], v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x7a,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], exec, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x7e,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], 0, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x80,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], -1, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0xc1,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], 0.5, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0xf0,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], -4.0, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0xf7,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], src_vccz, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0xfb,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], src_execz, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0xfc,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], src_scc, v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0xfd,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v255
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xff,0x03,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s103
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xcf,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_lo
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd1,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_hi
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd3,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], vcc_lo
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd5,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], vcc_hi
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd7,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], tba_lo
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xd9,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], tba_hi
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xdb,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], tma_lo
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xdd,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], tma_hi
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xdf,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], ttmp11
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xf7,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], m0
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xf9,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], exec_lo
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xfd,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], exec_hi
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xff,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x01,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x83,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xe1,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xef,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xf7,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xf9,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0xfb,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], -v[1:2], v2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x20]
+
+v_trig_preop_f64 v[5:6], |v[1:2]|, v2
+// CHECK: [0x05,0x01,0xe8,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 clamp
+// CHECK: [0x05,0x08,0xe8,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 mul:2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x08]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 mul:4
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x10]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 div:2
+// CHECK: [0x05,0x00,0xe8,0xd2,0x01,0x05,0x02,0x18]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[2:3], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x02,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[4:5], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x04,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[102:103], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x66,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], flat_scratch, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x68,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], vcc, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], tba, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], tma, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], ttmp[10:11], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x7a,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], exec, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], 0, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], -1, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], src_vccz, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], src_execz, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], src_scc, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], s2, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], s103, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], vcc_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], vcc_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], tba_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], tba_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], tma_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], tma_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], ttmp11, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], m0, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], exec_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], exec_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], 0, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], -1, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], src_vccz, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], src_execz, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], src_scc, v[3:6]
+// CHECK: [0xfc,0x00,0xea,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[254:255], s[12:13], v1, v2, v[3:4]
+// CHECK: [0xfe,0x0c,0xec,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[14:15], v1, v2, v[3:4]
+// CHECK: [0x05,0x0e,0xec,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[102:103], v1, v2, v[3:4]
+// CHECK: [0x05,0x66,0xec,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], flat_scratch, v1, v2, v[3:4]
+// CHECK: [0x05,0x68,0xec,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], vcc, v1, v2, v[3:4]
+// CHECK: [0x05,0x6a,0xec,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], tba, v1, v2, v[3:4]
+// CHECK: [0x05,0x6c,0xec,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], tma, v1, v2, v[3:4]
+// CHECK: [0x05,0x6e,0xec,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], ttmp[10:11], v1, v2, v[3:4]
+// CHECK: [0x05,0x7a,0xec,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v255, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], s1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], s103, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x68,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x69,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], tba_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], tba_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], tma_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], tma_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], ttmp11, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], m0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], 0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], -1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_lds_direct, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v255, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, s2, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, s103, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, tba_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, tba_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, tma_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, tma_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, ttmp11, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, m0, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, 0, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, -1, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, 0.5, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, -4.0, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xef,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, src_vccz, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, src_execz, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, src_scc, v[3:4]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[254:255]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xfa,0x07]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x1a,0x00]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x22,0x00]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[102:103]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x9a,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xa2,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xb2,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xba,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xea,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, exec
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x02,0x02]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -1
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0x06,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0.5
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -4.0
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, src_vccz
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xee,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, src_execz
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, src_scc
+// CHECK: [0x05,0x0c,0xec,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[254:255], s[12:13], v1, v2, v[3:4]
+// CHECK: [0xfe,0x0c,0xee,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[14:15], v1, v2, v[3:4]
+// CHECK: [0x05,0x0e,0xee,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[102:103], v1, v2, v[3:4]
+// CHECK: [0x05,0x66,0xee,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], flat_scratch, v1, v2, v[3:4]
+// CHECK: [0x05,0x68,0xee,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], vcc, v1, v2, v[3:4]
+// CHECK: [0x05,0x6a,0xee,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], tba, v1, v2, v[3:4]
+// CHECK: [0x05,0x6c,0xee,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], tma, v1, v2, v[3:4]
+// CHECK: [0x05,0x6e,0xee,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], ttmp[10:11], v1, v2, v[3:4]
+// CHECK: [0x05,0x7a,0xee,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v255, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], s1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], s103, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x68,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x69,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], tba_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x6c,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], tba_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x6d,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], tma_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x6e,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], tma_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x6f,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], ttmp11, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], m0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], 0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], -1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_lds_direct, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v255, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, s2, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, s103, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd1,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd3,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, tba_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xd9,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, tba_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xdb,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, tma_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xdd,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, tma_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xdf,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, ttmp11, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, m0, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, 0, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, -1, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, 0.5, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, -4.0, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xef,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, src_vccz, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, src_execz, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, src_scc, v[3:4]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[254:255]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xfa,0x07]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x1a,0x00]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x22,0x00]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[102:103]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x9a,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xa2,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xb2,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xba,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xea,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, exec
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x02,0x02]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -1
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0x06,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0.5
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -4.0
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, src_vccz
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xee,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, src_execz
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, src_scc
+// CHECK: [0x05,0x0c,0xee,0xd2,0x01,0x05,0xf6,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx7_asm_vopc.s
new file mode 100644
index 0000000000000..1cb63dcd3f4b1
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_vopc.s
@@ -0,0 +1,14113 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s
+
+v_cmp_f_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x00,0x7c]
+
+v_cmp_f_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x00,0x7c]
+
+v_cmp_f_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x00,0x7c]
+
+v_cmp_f_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x00,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x00,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x01,0x7c]
+
+v_cmp_lt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x02,0x7c]
+
+v_cmp_lt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x02,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x02,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x03,0x7c]
+
+v_cmp_eq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x04,0x7c]
+
+v_cmp_eq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x04,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x04,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x05,0x7c]
+
+v_cmp_le_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x06,0x7c]
+
+v_cmp_le_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x06,0x7c]
+
+v_cmp_le_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x06,0x7c]
+
+v_cmp_le_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x06,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x06,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x07,0x7c]
+
+v_cmp_gt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x08,0x7c]
+
+v_cmp_gt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x08,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x08,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x09,0x7c]
+
+v_cmp_lg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x7c]
+
+v_cmp_lg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x7c]
+
+v_cmp_ge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0c,0x7c]
+
+v_cmp_ge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x0d,0x7c]
+
+v_cmp_o_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0e,0x7c]
+
+v_cmp_o_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_o_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_o_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x0f,0x7c]
+
+v_cmp_u_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x10,0x7c]
+
+v_cmp_u_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x10,0x7c]
+
+v_cmp_u_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x10,0x7c]
+
+v_cmp_u_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x10,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_u_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x10,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_u_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x11,0x7c]
+
+v_cmp_nge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x12,0x7c]
+
+v_cmp_nge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x12,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x12,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x13,0x7c]
+
+v_cmp_nlg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x14,0x7c]
+
+v_cmp_nlg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x14,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x14,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x15,0x7c]
+
+v_cmp_ngt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x16,0x7c]
+
+v_cmp_ngt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x16,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ngt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x16,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ngt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x17,0x7c]
+
+v_cmp_nle_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x18,0x7c]
+
+v_cmp_nle_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x18,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nle_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x18,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nle_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x19,0x7c]
+
+v_cmp_neq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x1a,0x7c]
+
+v_cmp_neq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x1a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_neq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x1a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_neq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x1b,0x7c]
+
+v_cmp_nlt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x1c,0x7c]
+
+v_cmp_nlt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x1c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x1c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x1d,0x7c]
+
+v_cmp_tru_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x1e,0x7c]
+
+v_cmp_tru_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x1e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_tru_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x1e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_tru_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x1f,0x7c]
+
+v_cmpx_f_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x20,0x7c]
+
+v_cmpx_f_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x20,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x20,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x21,0x7c]
+
+v_cmpx_lt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x22,0x7c]
+
+v_cmpx_lt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x22,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x22,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x23,0x7c]
+
+v_cmpx_eq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x24,0x7c]
+
+v_cmpx_eq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x24,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x24,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x25,0x7c]
+
+v_cmpx_le_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x26,0x7c]
+
+v_cmpx_le_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x26,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x26,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x27,0x7c]
+
+v_cmpx_gt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x28,0x7c]
+
+v_cmpx_gt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x28,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x28,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x29,0x7c]
+
+v_cmpx_lg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x2a,0x7c]
+
+v_cmpx_lg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x2a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x2a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x2b,0x7c]
+
+v_cmpx_ge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x2c,0x7c]
+
+v_cmpx_ge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x2c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x2c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x2d,0x7c]
+
+v_cmpx_o_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x2e,0x7c]
+
+v_cmpx_o_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x2e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x2e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_o_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x2f,0x7c]
+
+v_cmpx_u_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x30,0x7c]
+
+v_cmpx_u_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x30,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x30,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_u_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x31,0x7c]
+
+v_cmpx_nge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x32,0x7c]
+
+v_cmpx_nge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x32,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x32,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x33,0x7c]
+
+v_cmpx_nlg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x34,0x7c]
+
+v_cmpx_nlg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x34,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x34,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x35,0x7c]
+
+v_cmpx_ngt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x36,0x7c]
+
+v_cmpx_ngt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x36,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x36,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ngt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x37,0x7c]
+
+v_cmpx_nle_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x38,0x7c]
+
+v_cmpx_nle_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x38,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x38,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nle_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x39,0x7c]
+
+v_cmpx_neq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x3a,0x7c]
+
+v_cmpx_neq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x3a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x3a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_neq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x3b,0x7c]
+
+v_cmpx_nlt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x3c,0x7c]
+
+v_cmpx_nlt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x3c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x3c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x3d,0x7c]
+
+v_cmpx_tru_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x3e,0x7c]
+
+v_cmpx_tru_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x3e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_tru_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x3e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_tru_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x3f,0x7c]
+
+v_cmp_f_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x40,0x7c]
+
+v_cmp_f_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x40,0x7c]
+
+v_cmp_f_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x40,0x7c]
+
+v_cmp_f_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x40,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x40,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x41,0x7c]
+
+v_cmp_lt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x42,0x7c]
+
+v_cmp_lt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x42,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x42,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x43,0x7c]
+
+v_cmp_eq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x44,0x7c]
+
+v_cmp_eq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x44,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x44,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x45,0x7c]
+
+v_cmp_le_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x46,0x7c]
+
+v_cmp_le_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x46,0x7c]
+
+v_cmp_le_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x46,0x7c]
+
+v_cmp_le_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x46,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x46,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x47,0x7c]
+
+v_cmp_gt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x48,0x7c]
+
+v_cmp_gt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x48,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x48,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x49,0x7c]
+
+v_cmp_lg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x4a,0x7c]
+
+v_cmp_lg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x4a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x4b,0x7c]
+
+v_cmp_ge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x4c,0x7c]
+
+v_cmp_ge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x4c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x4d,0x7c]
+
+v_cmp_o_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x4e,0x7c]
+
+v_cmp_o_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_o_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x4e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_o_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x4f,0x7c]
+
+v_cmp_u_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x50,0x7c]
+
+v_cmp_u_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x50,0x7c]
+
+v_cmp_u_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x50,0x7c]
+
+v_cmp_u_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x50,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_u_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x50,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_u_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x51,0x7c]
+
+v_cmp_nge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x52,0x7c]
+
+v_cmp_nge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x52,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x52,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x53,0x7c]
+
+v_cmp_nlg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x54,0x7c]
+
+v_cmp_nlg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x54,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x54,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x55,0x7c]
+
+v_cmp_ngt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x56,0x7c]
+
+v_cmp_ngt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x56,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ngt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x56,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ngt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x57,0x7c]
+
+v_cmp_nle_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x58,0x7c]
+
+v_cmp_nle_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x58,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nle_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x58,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nle_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x59,0x7c]
+
+v_cmp_neq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x5a,0x7c]
+
+v_cmp_neq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_neq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x5a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_neq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x5b,0x7c]
+
+v_cmp_nlt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x5c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x5d,0x7c]
+
+v_cmp_tru_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x5e,0x7c]
+
+v_cmp_tru_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_tru_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x5e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_tru_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x5f,0x7c]
+
+v_cmpx_f_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x60,0x7c]
+
+v_cmpx_f_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x60,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x60,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x61,0x7c]
+
+v_cmpx_lt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x62,0x7c]
+
+v_cmpx_lt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x62,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x62,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x63,0x7c]
+
+v_cmpx_eq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x64,0x7c]
+
+v_cmpx_eq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x64,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x64,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x65,0x7c]
+
+v_cmpx_le_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x66,0x7c]
+
+v_cmpx_le_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x66,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x66,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x67,0x7c]
+
+v_cmpx_gt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x68,0x7c]
+
+v_cmpx_gt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x68,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x68,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x69,0x7c]
+
+v_cmpx_lg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x6a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x6a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x6b,0x7c]
+
+v_cmpx_ge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x6c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x6c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x6d,0x7c]
+
+v_cmpx_o_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x6e,0x7c]
+
+v_cmpx_o_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x6e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x6e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_o_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x6f,0x7c]
+
+v_cmpx_u_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x70,0x7c]
+
+v_cmpx_u_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x70,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x70,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_u_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x71,0x7c]
+
+v_cmpx_nge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x72,0x7c]
+
+v_cmpx_nge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x72,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x72,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x73,0x7c]
+
+v_cmpx_nlg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x74,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x74,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x75,0x7c]
+
+v_cmpx_ngt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x76,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x76,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ngt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x77,0x7c]
+
+v_cmpx_nle_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x78,0x7c]
+
+v_cmpx_nle_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x78,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x78,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nle_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x79,0x7c]
+
+v_cmpx_neq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x7a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x7a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_neq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x7b,0x7c]
+
+v_cmpx_nlt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x7c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x7c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x7d,0x7c]
+
+v_cmpx_tru_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x7e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_tru_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x7e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_tru_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x7f,0x7c]
+
+v_cmps_f_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x80,0x7c]
+
+v_cmps_f_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x80,0x7c]
+
+v_cmps_f_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x80,0x7c]
+
+v_cmps_f_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x80,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_f_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x80,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_f_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x81,0x7c]
+
+v_cmps_lt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x82,0x7c]
+
+v_cmps_lt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x82,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_lt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x82,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_lt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x83,0x7c]
+
+v_cmps_eq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x84,0x7c]
+
+v_cmps_eq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x84,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_eq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x84,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_eq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x85,0x7c]
+
+v_cmps_le_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x86,0x7c]
+
+v_cmps_le_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x86,0x7c]
+
+v_cmps_le_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x86,0x7c]
+
+v_cmps_le_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x86,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_le_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x86,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_le_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x87,0x7c]
+
+v_cmps_gt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x88,0x7c]
+
+v_cmps_gt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x88,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_gt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x88,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_gt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x89,0x7c]
+
+v_cmps_lg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8a,0x7c]
+
+v_cmps_lg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_lg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_lg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8b,0x7c]
+
+v_cmps_ge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8c,0x7c]
+
+v_cmps_ge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_ge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_ge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8d,0x7c]
+
+v_cmps_o_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8e,0x7c]
+
+v_cmps_o_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_o_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_o_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8f,0x7c]
+
+v_cmps_u_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x90,0x7c]
+
+v_cmps_u_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x90,0x7c]
+
+v_cmps_u_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x90,0x7c]
+
+v_cmps_u_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x90,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_u_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x90,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_u_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x91,0x7c]
+
+v_cmps_nge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x92,0x7c]
+
+v_cmps_nge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x92,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_nge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x92,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_nge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x93,0x7c]
+
+v_cmps_nlg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x94,0x7c]
+
+v_cmps_nlg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x94,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_nlg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x94,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_nlg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x95,0x7c]
+
+v_cmps_ngt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x96,0x7c]
+
+v_cmps_ngt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x96,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_ngt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x96,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_ngt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x97,0x7c]
+
+v_cmps_nle_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x98,0x7c]
+
+v_cmps_nle_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x98,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_nle_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x98,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_nle_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x99,0x7c]
+
+v_cmps_neq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9a,0x7c]
+
+v_cmps_neq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_neq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_neq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9b,0x7c]
+
+v_cmps_nlt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9c,0x7c]
+
+v_cmps_nlt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_nlt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_nlt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9d,0x7c]
+
+v_cmps_tru_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9e,0x7c]
+
+v_cmps_tru_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_tru_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_tru_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9f,0x7c]
+
+v_cmpsx_f_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa0,0x7c]
+
+v_cmpsx_f_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_f_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_f_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa1,0x7c]
+
+v_cmpsx_lt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa2,0x7c]
+
+v_cmpsx_lt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_lt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_lt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa3,0x7c]
+
+v_cmpsx_eq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa4,0x7c]
+
+v_cmpsx_eq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_eq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_eq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa5,0x7c]
+
+v_cmpsx_le_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa6,0x7c]
+
+v_cmpsx_le_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_le_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_le_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa7,0x7c]
+
+v_cmpsx_gt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa8,0x7c]
+
+v_cmpsx_gt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_gt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_gt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa9,0x7c]
+
+v_cmpsx_lg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xaa,0x7c]
+
+v_cmpsx_lg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xaa,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_lg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xaa,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_lg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xab,0x7c]
+
+v_cmpsx_ge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xac,0x7c]
+
+v_cmpsx_ge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xac,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_ge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xac,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_ge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xad,0x7c]
+
+v_cmpsx_o_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xae,0x7c]
+
+v_cmpsx_o_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xae,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_o_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xae,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_o_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xaf,0x7c]
+
+v_cmpsx_u_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb0,0x7c]
+
+v_cmpsx_u_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_u_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_u_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb1,0x7c]
+
+v_cmpsx_nge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb2,0x7c]
+
+v_cmpsx_nge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_nge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_nge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb3,0x7c]
+
+v_cmpsx_nlg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb4,0x7c]
+
+v_cmpsx_nlg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_nlg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_nlg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb5,0x7c]
+
+v_cmpsx_ngt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb6,0x7c]
+
+v_cmpsx_ngt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_ngt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_ngt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb7,0x7c]
+
+v_cmpsx_nle_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb8,0x7c]
+
+v_cmpsx_nle_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_nle_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_nle_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb9,0x7c]
+
+v_cmpsx_neq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xba,0x7c]
+
+v_cmpsx_neq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xba,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_neq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xba,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_neq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbb,0x7c]
+
+v_cmpsx_nlt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbc,0x7c]
+
+v_cmpsx_nlt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_nlt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_nlt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbd,0x7c]
+
+v_cmpsx_tru_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbe,0x7c]
+
+v_cmpsx_tru_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbe,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_tru_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbe,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_tru_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbf,0x7c]
+
+v_cmps_f_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc0,0x7c]
+
+v_cmps_f_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_f_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_f_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc1,0x7c]
+
+v_cmps_lt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc2,0x7c]
+
+v_cmps_lt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_lt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_lt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc3,0x7c]
+
+v_cmps_eq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc4,0x7c]
+
+v_cmps_eq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_eq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_eq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc5,0x7c]
+
+v_cmps_le_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc6,0x7c]
+
+v_cmps_le_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_le_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_le_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc7,0x7c]
+
+v_cmps_gt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc8,0x7c]
+
+v_cmps_gt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_gt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_gt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc9,0x7c]
+
+v_cmps_lg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xca,0x7c]
+
+v_cmps_lg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_lg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_lg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcb,0x7c]
+
+v_cmps_ge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xcc,0x7c]
+
+v_cmps_ge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_ge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_ge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcd,0x7c]
+
+v_cmps_o_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xce,0x7c]
+
+v_cmps_o_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xce,0x7c]
+
+v_cmps_o_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xce,0x7c]
+
+v_cmps_o_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_o_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_o_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcf,0x7c]
+
+v_cmps_u_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd0,0x7c]
+
+v_cmps_u_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_u_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_u_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd1,0x7c]
+
+v_cmps_nge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd2,0x7c]
+
+v_cmps_nge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_nge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_nge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd3,0x7c]
+
+v_cmps_nlg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd4,0x7c]
+
+v_cmps_nlg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_nlg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_nlg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd5,0x7c]
+
+v_cmps_ngt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd6,0x7c]
+
+v_cmps_ngt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_ngt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_ngt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd7,0x7c]
+
+v_cmps_nle_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd8,0x7c]
+
+v_cmps_nle_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_nle_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_nle_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd9,0x7c]
+
+v_cmps_neq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xda,0x7c]
+
+v_cmps_neq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_neq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_neq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdb,0x7c]
+
+v_cmps_nlt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xdc,0x7c]
+
+v_cmps_nlt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_nlt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_nlt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdd,0x7c]
+
+v_cmps_tru_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xde,0x7c]
+
+v_cmps_tru_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmps_tru_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmps_tru_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdf,0x7c]
+
+v_cmpsx_f_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe0,0x7c]
+
+v_cmpsx_f_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_f_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_f_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe1,0x7c]
+
+v_cmpsx_lt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe2,0x7c]
+
+v_cmpsx_lt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_lt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_lt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe3,0x7c]
+
+v_cmpsx_eq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe4,0x7c]
+
+v_cmpsx_eq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_eq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_eq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe5,0x7c]
+
+v_cmpsx_le_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe6,0x7c]
+
+v_cmpsx_le_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_le_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_le_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe7,0x7c]
+
+v_cmpsx_gt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe8,0x7c]
+
+v_cmpsx_gt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_gt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_gt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe9,0x7c]
+
+v_cmpsx_lg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xea,0x7c]
+
+v_cmpsx_lg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_lg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_lg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xeb,0x7c]
+
+v_cmpsx_ge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xec,0x7c]
+
+v_cmpsx_ge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_ge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_ge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xed,0x7c]
+
+v_cmpsx_o_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xee,0x7c]
+
+v_cmpsx_o_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_o_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_o_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xef,0x7c]
+
+v_cmpsx_u_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf0,0x7c]
+
+v_cmpsx_u_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_u_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_u_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf1,0x7c]
+
+v_cmpsx_nge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf2,0x7c]
+
+v_cmpsx_nge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_nge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_nge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf3,0x7c]
+
+v_cmpsx_nlg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf4,0x7c]
+
+v_cmpsx_nlg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_nlg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_nlg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf5,0x7c]
+
+v_cmpsx_ngt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf6,0x7c]
+
+v_cmpsx_ngt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_ngt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_ngt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf7,0x7c]
+
+v_cmpsx_nle_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf8,0x7c]
+
+v_cmpsx_nle_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_nle_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_nle_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf9,0x7c]
+
+v_cmpsx_neq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfa,0x7c]
+
+v_cmpsx_neq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_neq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_neq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfb,0x7c]
+
+v_cmpsx_nlt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfc,0x7c]
+
+v_cmpsx_nlt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_nlt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_nlt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfd,0x7c]
+
+v_cmpsx_tru_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfe,0x7c]
+
+v_cmpsx_tru_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpsx_tru_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpsx_tru_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xff,0x7c]
+
+v_cmp_f_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x00,0x7d]
+
+v_cmp_f_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x00,0x7d]
+
+v_cmp_f_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x00,0x7d]
+
+v_cmp_f_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x00,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x00,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x01,0x7d]
+
+v_cmp_lt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x02,0x7d]
+
+v_cmp_lt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x02,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x02,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x03,0x7d]
+
+v_cmp_eq_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x04,0x7d]
+
+v_cmp_eq_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x04,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x04,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x05,0x7d]
+
+v_cmp_le_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x06,0x7d]
+
+v_cmp_le_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x06,0x7d]
+
+v_cmp_le_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x06,0x7d]
+
+v_cmp_le_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x06,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x06,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x07,0x7d]
+
+v_cmp_gt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x08,0x7d]
+
+v_cmp_gt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x08,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x08,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x09,0x7d]
+
+v_cmp_ne_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x7d]
+
+v_cmp_ne_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x7d]
+
+v_cmp_ge_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0c,0x7d]
+
+v_cmp_ge_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x0d,0x7d]
+
+v_cmp_t_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0e,0x7d]
+
+v_cmp_t_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x0f,0x7d]
+
+v_cmpx_f_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x20,0x7d]
+
+v_cmpx_f_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x20,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x20,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x21,0x7d]
+
+v_cmpx_lt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x22,0x7d]
+
+v_cmpx_lt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x22,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x22,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x23,0x7d]
+
+v_cmpx_eq_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x24,0x7d]
+
+v_cmpx_eq_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x24,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x24,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x25,0x7d]
+
+v_cmpx_le_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x26,0x7d]
+
+v_cmpx_le_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x26,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x26,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x27,0x7d]
+
+v_cmpx_gt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x28,0x7d]
+
+v_cmpx_gt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x28,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x28,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x29,0x7d]
+
+v_cmpx_ne_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x2a,0x7d]
+
+v_cmpx_ne_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x2a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x2a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x2b,0x7d]
+
+v_cmpx_ge_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x2c,0x7d]
+
+v_cmpx_ge_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x2c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x2c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x2d,0x7d]
+
+v_cmpx_t_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x2e,0x7d]
+
+v_cmpx_t_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x2e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x2e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x2f,0x7d]
+
+v_cmp_f_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x40,0x7d]
+
+v_cmp_f_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x40,0x7d]
+
+v_cmp_f_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x40,0x7d]
+
+v_cmp_f_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x40,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x40,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x41,0x7d]
+
+v_cmp_lt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x42,0x7d]
+
+v_cmp_lt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x42,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x42,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x43,0x7d]
+
+v_cmp_eq_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x44,0x7d]
+
+v_cmp_eq_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x44,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x44,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x45,0x7d]
+
+v_cmp_le_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x46,0x7d]
+
+v_cmp_le_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x46,0x7d]
+
+v_cmp_le_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x46,0x7d]
+
+v_cmp_le_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x46,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x46,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x47,0x7d]
+
+v_cmp_gt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x48,0x7d]
+
+v_cmp_gt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x48,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x48,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x49,0x7d]
+
+v_cmp_ne_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x4a,0x7d]
+
+v_cmp_ne_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x4a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x4b,0x7d]
+
+v_cmp_ge_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x4c,0x7d]
+
+v_cmp_ge_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x4c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x4d,0x7d]
+
+v_cmp_t_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x4e,0x7d]
+
+v_cmp_t_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x4e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x4f,0x7d]
+
+v_cmpx_f_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x60,0x7d]
+
+v_cmpx_f_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x60,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x60,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x61,0x7d]
+
+v_cmpx_lt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x62,0x7d]
+
+v_cmpx_lt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x62,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x62,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x63,0x7d]
+
+v_cmpx_eq_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x64,0x7d]
+
+v_cmpx_eq_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x64,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x64,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x65,0x7d]
+
+v_cmpx_le_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x66,0x7d]
+
+v_cmpx_le_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x66,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x66,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x67,0x7d]
+
+v_cmpx_gt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x68,0x7d]
+
+v_cmpx_gt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x68,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x68,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x69,0x7d]
+
+v_cmpx_ne_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x6a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x6a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x6b,0x7d]
+
+v_cmpx_ge_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x6c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x6c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x6d,0x7d]
+
+v_cmpx_t_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0x6e,0x7d]
+
+v_cmpx_t_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0x6e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0x6e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0x6f,0x7d]
+
+v_cmp_f_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x80,0x7d]
+
+v_cmp_f_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x80,0x7d]
+
+v_cmp_f_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x80,0x7d]
+
+v_cmp_f_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x81,0x7d]
+
+v_cmp_lt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x82,0x7d]
+
+v_cmp_lt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x83,0x7d]
+
+v_cmp_eq_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x84,0x7d]
+
+v_cmp_eq_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x85,0x7d]
+
+v_cmp_le_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x86,0x7d]
+
+v_cmp_le_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x86,0x7d]
+
+v_cmp_le_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x86,0x7d]
+
+v_cmp_le_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x87,0x7d]
+
+v_cmp_gt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x88,0x7d]
+
+v_cmp_gt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x89,0x7d]
+
+v_cmp_ne_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8a,0x7d]
+
+v_cmp_ne_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8b,0x7d]
+
+v_cmp_ge_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8c,0x7d]
+
+v_cmp_ge_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8d,0x7d]
+
+v_cmp_t_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8e,0x7d]
+
+v_cmp_t_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8f,0x7d]
+
+v_cmpx_f_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa0,0x7d]
+
+v_cmpx_f_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa1,0x7d]
+
+v_cmpx_lt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa2,0x7d]
+
+v_cmpx_lt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa3,0x7d]
+
+v_cmpx_eq_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa4,0x7d]
+
+v_cmpx_eq_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa5,0x7d]
+
+v_cmpx_le_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa6,0x7d]
+
+v_cmpx_le_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa7,0x7d]
+
+v_cmpx_gt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa8,0x7d]
+
+v_cmpx_gt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa9,0x7d]
+
+v_cmpx_ne_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xaa,0x7d]
+
+v_cmpx_ne_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xaa,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xaa,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xab,0x7d]
+
+v_cmpx_ge_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xac,0x7d]
+
+v_cmpx_ge_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xac,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xac,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xad,0x7d]
+
+v_cmpx_t_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, s103, v2
+// CHECK: [0x67,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xae,0x7d]
+
+v_cmpx_t_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xae,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xae,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xaf,0x7d]
+
+v_cmp_f_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc0,0x7d]
+
+v_cmp_f_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc1,0x7d]
+
+v_cmp_lt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc2,0x7d]
+
+v_cmp_lt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc3,0x7d]
+
+v_cmp_eq_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc4,0x7d]
+
+v_cmp_eq_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc5,0x7d]
+
+v_cmp_le_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc6,0x7d]
+
+v_cmp_le_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc7,0x7d]
+
+v_cmp_gt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc8,0x7d]
+
+v_cmp_gt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc9,0x7d]
+
+v_cmp_ne_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xca,0x7d]
+
+v_cmp_ne_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcb,0x7d]
+
+v_cmp_ge_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xcc,0x7d]
+
+v_cmp_ge_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcd,0x7d]
+
+v_cmp_t_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xce,0x7d]
+
+v_cmp_t_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xce,0x7d]
+
+v_cmp_t_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xce,0x7d]
+
+v_cmp_t_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcf,0x7d]
+
+v_cmpx_f_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe0,0x7d]
+
+v_cmpx_f_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe1,0x7d]
+
+v_cmpx_lt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe2,0x7d]
+
+v_cmpx_lt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe3,0x7d]
+
+v_cmpx_eq_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe4,0x7d]
+
+v_cmpx_eq_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe5,0x7d]
+
+v_cmpx_le_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe6,0x7d]
+
+v_cmpx_le_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe7,0x7d]
+
+v_cmpx_gt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe8,0x7d]
+
+v_cmpx_gt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe9,0x7d]
+
+v_cmpx_ne_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xea,0x7d]
+
+v_cmpx_ne_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xeb,0x7d]
+
+v_cmpx_ge_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xec,0x7d]
+
+v_cmpx_ge_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xed,0x7d]
+
+v_cmpx_t_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, s[102:103], v[2:3]
+// CHECK: [0x66,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x68,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xee,0x7d]
+
+v_cmpx_t_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xef,0x7d]
+
+v_cmp_class_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x10,0x7d]
+
+v_cmp_class_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x10,0x7d]
+
+v_cmp_class_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x10,0x7d]
+
+v_cmp_class_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x10,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_class_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x10,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_class_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x11,0x7d]
+
+v_cmpx_class_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, s103, v2
+// CHECK: [0x67,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x68,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x69,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x30,0x7d]
+
+v_cmpx_class_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x30,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x30,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_class_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x31,0x7d]
+
+v_cmp_class_f64 vcc, v[1:2], v2
+// CHECK: [0x01,0x05,0x50,0x7d]
+
+v_cmp_class_f64 vcc, v[254:255], v2
+// CHECK: [0xfe,0x05,0x50,0x7d]
+
+v_cmp_class_f64 vcc, s[2:3], v2
+// CHECK: [0x02,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, s[4:5], v2
+// CHECK: [0x04,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, s[102:103], v2
+// CHECK: [0x66,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, flat_scratch, v2
+// CHECK: [0x68,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, vcc, v2
+// CHECK: [0x6a,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, tba, v2
+// CHECK: [0x6c,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, tma, v2
+// CHECK: [0x6e,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, ttmp[10:11], v2
+// CHECK: [0x7a,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, exec, v2
+// CHECK: [0x7e,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, 0, v2
+// CHECK: [0x80,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x50,0x7d]
+
+v_cmp_class_f64 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_class_f64 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_class_f64 vcc, v[1:2], v255
+// CHECK: [0x01,0xff,0x51,0x7d]
+
+v_cmpx_class_f64 vcc, v[1:2], v2
+// CHECK: [0x01,0x05,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, v[254:255], v2
+// CHECK: [0xfe,0x05,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, s[2:3], v2
+// CHECK: [0x02,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, s[4:5], v2
+// CHECK: [0x04,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, s[102:103], v2
+// CHECK: [0x66,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, flat_scratch, v2
+// CHECK: [0x68,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, vcc, v2
+// CHECK: [0x6a,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, tba, v2
+// CHECK: [0x6c,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, tma, v2
+// CHECK: [0x6e,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, ttmp[10:11], v2
+// CHECK: [0x7a,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, exec, v2
+// CHECK: [0x7e,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, 0, v2
+// CHECK: [0x80,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x70,0x7d]
+
+v_cmpx_class_f64 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f64 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_class_f64 vcc, v[1:2], v255
+// CHECK: [0x01,0xff,0x71,0x7d]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_all.s b/llvm/test/MC/AMDGPU/gfx8_asm_all.s
deleted file mode 100644
index d4142d922993d..0000000000000
--- a/llvm/test/MC/AMDGPU/gfx8_asm_all.s
+++ /dev/null
@@ -1,119543 +0,0 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=CHECK-ERR --implicit-check-not=error: %s
-
-ds_add_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd8,0xff,0x02,0x00,0x00]
-
-ds_add_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd8,0x01,0xff,0x00,0x00]
-
-ds_add_u32 v1, v2
-// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x01,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd8,0xff,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd8,0x01,0xff,0x00,0x00]
-
-ds_sub_u32 v1, v2
-// CHECK: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x03,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd8,0xff,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd8,0x01,0xff,0x00,0x00]
-
-ds_rsub_u32 v1, v2
-// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x05,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd8,0xff,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd8,0x01,0xff,0x00,0x00]
-
-ds_inc_u32 v1, v2
-// CHECK: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x07,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
-
-ds_dec_u32 v1, v2
-// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x09,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_i32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0xff,0x00,0x00]
-
-ds_min_i32 v1, v2
-// CHECK: [0x00,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x0b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_i32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0xff,0x00,0x00]
-
-ds_max_i32 v1, v2
-// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x0d,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0xff,0x00,0x00]
-
-ds_min_u32 v1, v2
-// CHECK: [0x00,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x0f,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd8,0x01,0xff,0x00,0x00]
-
-ds_max_u32 v1, v2
-// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x11,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd8,0xff,0x02,0x00,0x00]
-
-ds_and_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd8,0x01,0xff,0x00,0x00]
-
-ds_and_b32 v1, v2
-// CHECK: [0x00,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x13,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd8,0xff,0x02,0x00,0x00]
-
-ds_or_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd8,0x01,0xff,0x00,0x00]
-
-ds_or_b32 v1, v2
-// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x15,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd8,0xff,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd8,0x01,0xff,0x00,0x00]
-
-ds_xor_b32 v1, v2
-// CHECK: [0x00,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x17,0xd8,0x01,0x02,0x00,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0xff,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0x01,0xff,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0xff,0x00]
-
-ds_mskor_b32 v1, v2, v3
-// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x19,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b32 v1, v2
-// CHECK: [0x00,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x1b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1c,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0xff,0x03,0x00]
-
-ds_write2_b32 v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0x02,0xff,0x00]
-
-ds_write2_b32 v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x1d,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1e,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0xff,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0x02,0xff,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x1f,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0x01,0xff,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0xff,0x00]
-
-ds_cmpst_b32 v1, v2, v3
-// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x21,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x22,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x22,0xd8,0x01,0xff,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0xff,0x00]
-
-ds_cmpst_f32 v1, v2, v3
-// CHECK: [0x00,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x23,0xd8,0x01,0x02,0x03,0x00]
-
-ds_min_f32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_f32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd8,0x01,0xff,0x00,0x00]
-
-ds_min_f32 v1, v2
-// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x25,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_f32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd8,0x01,0xff,0x00,0x00]
-
-ds_max_f32 v1, v2
-// CHECK: [0x00,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x27,0xd8,0x01,0x02,0x00,0x00]
-
-ds_nop
-// CHECK: [0x00,0x00,0x28,0xd8,0x00,0x00,0x00,0x00]
-
-ds_add_f32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_f32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x2a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_add_f32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0xff,0x00,0x00]
-
-ds_add_f32 v1, v2
-// CHECK: [0x00,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_f32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_f32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_f32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x2b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x3c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x3c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b8 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x3c,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b8 v1, v2
-// CHECK: [0x00,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x3d,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x3e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x3e,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b16 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x3e,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b16 v1, v2
-// CHECK: [0x00,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x3f,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0xff,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0x01,0xff,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x41,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x42,0xd8,0xff,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x42,0xd8,0x01,0xff,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x43,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0xff,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0x01,0xff,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x45,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x46,0xd8,0xff,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x46,0xd8,0x01,0xff,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x47,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0xff,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0x01,0xff,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x49,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x4a,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2
-// CHECK: [0x00,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x4b,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2
-// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x4d,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x4e,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x4f,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x50,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x50,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x50,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x50,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x51,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x52,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x52,0xd8,0x01,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x52,0xd8,0xff,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x52,0xd8,0x01,0xff,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x53,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x54,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x54,0xd8,0x01,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x54,0xd8,0xff,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x54,0xd8,0x01,0xff,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x55,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x56,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x56,0xd8,0x01,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x56,0xd8,0xff,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x56,0xd8,0x01,0xff,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x57,0xd8,0x01,0x02,0x00,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0x03,0xff]
-
-ds_mskor_rtn_b32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0xff,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0x01,0xff,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0xff,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x59,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x5a,0xd8,0xff,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0xff,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x5b,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_wrxchg2_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x5d,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x5f,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0x03,0xff]
-
-ds_cmpst_rtn_b32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0x01,0xff,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0xff,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x61,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0x03,0xff]
-
-ds_cmpst_rtn_f32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0x01,0xff,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0xff,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x63,0xd8,0x01,0x02,0x03,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x64,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x64,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_f32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x64,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x64,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2
-// CHECK: [0x00,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x65,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_f32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x66,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x66,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2
-// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x67,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0x03,0xff]
-
-ds_wrap_rtn_b32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x69,0xd8,0x01,0x02,0x03,0x05]
-
-ds_add_rtn_f32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0x02,0x00,0xff]
-
-ds_add_rtn_f32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x6a,0xd8,0xff,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0xff,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v2
-// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x6b,0xd8,0x01,0x02,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x6c,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x6c,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_b32 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x6c,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1
-// CHECK: [0x00,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x6d,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x6e,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read2_b32 v[5:6], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x6e,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset1:255
-// CHECK: [0x00,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127
-// CHECK: [0x7f,0x00,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x6f,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x70,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read2st64_b32 v[5:6], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x70,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset1:255
-// CHECK: [0x00,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127
-// CHECK: [0x7f,0x00,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x71,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x72,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x72,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i8 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x72,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1
-// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x73,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x74,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x74,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u8 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x74,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1
-// CHECK: [0x00,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x75,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i16 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x76,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1
-// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x77,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u16 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x78,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1
-// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x79,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0xff]
-
-ds_swizzle_b32 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd8,0xff,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1
-// CHECK: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05]
-
-ds_permute_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_permute_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0xff]
-
-ds_permute_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0xff,0x02,0x00,0x05]
-
-ds_permute_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0xff,0x00,0x05]
-
-ds_permute_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_permute_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_permute_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_bpermute_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0xff]
-
-ds_bpermute_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x7e,0xd8,0xff,0x02,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0xff,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0xff,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_add_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x81,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x82,0xd8,0xff,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x82,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x83,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0xff,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x85,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x86,0xd8,0xff,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x86,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x87,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0xff,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x89,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_min_i64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x8b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_max_i64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x8d,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_min_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x8f,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_max_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x91,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x92,0xd8,0xff,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x92,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_and_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x93,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0xff,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_or_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x95,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x96,0xd8,0xff,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x96,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x97,0xd8,0x01,0x02,0x00,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0xff,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0x99,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_write_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x9b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9c,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x9d,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9e,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x9f,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xa1,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa2,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xa3,0xd8,0x01,0x02,0x03,0x00]
-
-ds_min_f64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_min_f64 v1, v[2:3]
-// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xa5,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_max_f64 v1, v[2:3]
-// CHECK: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xa7,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0xff,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc1,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_sub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc2,0xd8,0xff,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc3,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_rsub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0xff,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc5,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_inc_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc6,0xd8,0xff,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc7,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_dec_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0xff,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc9,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_i64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xca,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xca,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xcb,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_i64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xcd,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xce,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xce,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xcf,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xd1,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_and_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd2,0xd8,0xff,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xd3,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_or_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0xff,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xd5,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_xor_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd6,0xd8,0xff,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xd7,0xd8,0x01,0x02,0x00,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_mskor_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0xff,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xd9,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_wrxchg_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xda,0xd8,0xff,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xda,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xdb,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0x03,0xfc]
-
-ds_wrxchg2_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xdd,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0x03,0xfc]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xdf,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_cmpst_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xe1,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_cmpst_rtn_f64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xe3,0xd8,0x01,0x02,0x03,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_f64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xe5,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_f64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe6,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xe7,0xd8,0x01,0x02,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:65535
-// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[254:255], v1 offset:65535
-// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read_b64 v[5:6], v255 offset:65535
-// CHECK: [0xff,0xff,0xec,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1
-// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:0
-// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:4
-// CHECK: [0x04,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xed,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xee,0xd8,0x01,0x00,0x00,0xfc]
-
-ds_read2_b64 v[5:8], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xee,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset1:255
-// CHECK: [0x00,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127
-// CHECK: [0x7f,0x00,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xef,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xf0,0xd8,0x01,0x00,0x00,0xfc]
-
-ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xf0,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset1:255
-// CHECK: [0x00,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127
-// CHECK: [0x7f,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xf1,0xd8,0x01,0x00,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_condxchg32_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd8,0xff,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xfd,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd9,0xff,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1
-// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x01,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd9,0xff,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1
-// CHECK: [0x00,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x03,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd9,0xff,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1
-// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x05,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd9,0xff,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1
-// CHECK: [0x00,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x07,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd9,0xff,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1
-// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x09,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v255 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1
-// CHECK: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:0
-// CHECK: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:4
-// CHECK: [0x04,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v255 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1
-// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:0
-// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:4
-// CHECK: [0x04,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0d,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1
-// CHECK: [0x00,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0f,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1
-// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x11,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd9,0xff,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1
-// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x13,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd9,0xff,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1
-// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x15,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd9,0xff,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1
-// CHECK: [0x00,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x17,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd9,0xff,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1
-// CHECK: [0x00,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x1b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v255 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1
-// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:0
-// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:4
-// CHECK: [0x04,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x25,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v255 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1
-// CHECK: [0x00,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:0
-// CHECK: [0x00,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:4
-// CHECK: [0x04,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x27,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:65535 gds
-// CHECK: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all gds
-// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:0 gds
-// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:4 gds
-// CHECK: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_init v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x33,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_init v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x33,0xd9,0xff,0x00,0x00,0x00]
-
-ds_gws_init v1 gds
-// CHECK: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_init v1 offset:0 gds
-// CHECK: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_init v1 offset:4 gds
-// CHECK: [0x04,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:65535 gds
-// CHECK: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v gds
-// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:0 gds
-// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:4 gds
-// CHECK: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x37,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_br v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x37,0xd9,0xff,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 gds
-// CHECK: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 offset:0 gds
-// CHECK: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 offset:4 gds
-// CHECK: [0x04,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:65535 gds
-// CHECK: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p gds
-// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:0 gds
-// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:4 gds
-// CHECK: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_barrier v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x3b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_barrier v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x3b,0xd9,0xff,0x00,0x00,0x00]
-
-ds_gws_barrier v1 gds
-// CHECK: [0x00,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_barrier v1 offset:0 gds
-// CHECK: [0x00,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_barrier v1 offset:4 gds
-// CHECK: [0x04,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_consume v5 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0x05]
-
-ds_consume v255 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0xff]
-
-ds_consume v5
-// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:0
-// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:4
-// CHECK: [0x04,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:65535 gds
-// CHECK: [0xff,0xff,0x7b,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v255 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0xff]
-
-ds_append v5
-// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:0
-// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:4
-// CHECK: [0x04,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:65535 gds
-// CHECK: [0xff,0xff,0x7d,0xd9,0x00,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x7f,0xd9,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v255, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x7f,0xd9,0x01,0x00,0x00,0xff]
-
-ds_ordered_count v5, v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x7f,0xd9,0xff,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 gds
-// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:0 gds
-// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:4 gds
-// CHECK: [0x04,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
-
-ds_add_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x80,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x80,0xd9,0xff,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1
-// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x81,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x82,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x82,0xd9,0xff,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1
-// CHECK: [0x00,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x83,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x84,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x84,0xd9,0xff,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1
-// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x85,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x86,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x86,0xd9,0xff,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1
-// CHECK: [0x00,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x87,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x88,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x88,0xd9,0xff,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1
-// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x89,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v255 offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1
-// CHECK: [0x00,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:0
-// CHECK: [0x00,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:4
-// CHECK: [0x04,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x8b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v255 offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1
-// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:0
-// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:4
-// CHECK: [0x04,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x8d,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1
-// CHECK: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x8f,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x90,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x90,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1
-// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x91,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x92,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x92,0xd9,0xff,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1
-// CHECK: [0x00,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x93,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x94,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x94,0xd9,0xff,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1
-// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x95,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x96,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x96,0xd9,0xff,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1
-// CHECK: [0x00,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x97,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd9,0xff,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1
-// CHECK: [0x00,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x9b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v255 offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1
-// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:0
-// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:4
-// CHECK: [0x04,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xa5,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v255 offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1
-// CHECK: [0x00,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:0
-// CHECK: [0x00,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:4
-// CHECK: [0x04,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xa7,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:65535
-// CHECK: [0xff,0xff,0xbc,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v255, v[2:4] offset:65535
-// CHECK: [0xff,0xff,0xbc,0xd9,0xff,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[253:255] offset:65535
-// CHECK: [0xff,0xff,0xbc,0xd9,0x01,0xfd,0x00,0x00]
-
-ds_write_b96 v1, v[2:4]
-// CHECK: [0x00,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:0
-// CHECK: [0x00,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:4
-// CHECK: [0x04,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xbd,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:65535
-// CHECK: [0xff,0xff,0xbe,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v255, v[2:5] offset:65535
-// CHECK: [0xff,0xff,0xbe,0xd9,0xff,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[252:255] offset:65535
-// CHECK: [0xff,0xff,0xbe,0xd9,0x01,0xfc,0x00,0x00]
-
-ds_write_b128 v1, v[2:5]
-// CHECK: [0x00,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:0
-// CHECK: [0x00,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:4
-// CHECK: [0x04,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:65535 gds
-// CHECK: [0xff,0xff,0xbf,0xd9,0x01,0x02,0x00,0x00]
-
-ds_read_b96 v[5:7], v1 offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[253:255], v1 offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd9,0x01,0x00,0x00,0xfd]
-
-ds_read_b96 v[5:7], v255 offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1
-// CHECK: [0x00,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:0
-// CHECK: [0x00,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:4
-// CHECK: [0x04,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xfd,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:65535
-// CHECK: [0xff,0xff,0xfe,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[252:255], v1 offset:65535
-// CHECK: [0xff,0xff,0xfe,0xd9,0x01,0x00,0x00,0xfc]
-
-ds_read_b128 v[5:8], v255 offset:65535
-// CHECK: [0xff,0xff,0xfe,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1
-// CHECK: [0x00,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:0
-// CHECK: [0x00,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:4
-// CHECK: [0x04,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xff,0xd9,0x01,0x00,0x00,0x05]
-
-exp mrt0 v0, v0, v0, v0
-// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrtz v0, v0, v0, v0
-// CHECK: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp null v0, v0, v0, v0
-// CHECK: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp pos0 v0, v0, v0, v0
-// CHECK: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp param0 v0, v0, v0, v0
-// CHECK: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v255, v0, v0, v0
-// CHECK: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00]
-
-exp mrt0 v0, v255, v0, v0
-// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00]
-
-exp mrt0 v0, v0, v255, v0
-// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00]
-
-exp mrt0 v0, v0, v0, v255
-// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff]
-
-exp mrt0 v0, off, off, off
-// CHECK: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, off, off
-// CHECK: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, off, off
-// CHECK: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, v0, off
-// CHECK: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, off, v0, off
-// CHECK: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, v0, off
-// CHECK: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, off
-// CHECK: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, off, v0
-// CHECK: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, off, off, v0
-// CHECK: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, off, v0
-// CHECK: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, off, v0
-// CHECK: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, v0, v0
-// CHECK: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, off, v0, v0
-// CHECK: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, v0, v0
-// CHECK: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, off, off
-// CHECK: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, v0 done
-// CHECK: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, v0 compr
-// CHECK: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, v0 vm
-// CHECK: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-flat_load_ubyte v5, v[1:2]
-// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte v255, v[1:2]
-// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_ubyte v5, v[254:255]
-// CHECK: [0x00,0x00,0x40,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_ubyte v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x41,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x42,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2]
-// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v255, v[1:2]
-// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_sbyte v5, v[254:255]
-// CHECK: [0x00,0x00,0x44,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x45,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x46,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2]
-// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v255, v[1:2]
-// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_ushort v5, v[254:255]
-// CHECK: [0x00,0x00,0x48,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x49,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x4a,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2]
-// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v255, v[1:2]
-// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_sshort v5, v[254:255]
-// CHECK: [0x00,0x00,0x4c,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x4d,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x4e,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2]
-// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v255, v[1:2]
-// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_dword v5, v[254:255]
-// CHECK: [0x00,0x00,0x50,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2] glc
-// CHECK: [0x00,0x00,0x51,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2] slc
-// CHECK: [0x00,0x00,0x52,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2]
-// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[254:255], v[1:2]
-// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0xfe]
-
-flat_load_dwordx2 v[5:6], v[254:255]
-// CHECK: [0x00,0x00,0x54,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2] glc
-// CHECK: [0x00,0x00,0x55,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2] slc
-// CHECK: [0x00,0x00,0x56,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2]
-// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[253:255], v[1:2]
-// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0xfd]
-
-flat_load_dwordx3 v[5:7], v[254:255]
-// CHECK: [0x00,0x00,0x58,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2] glc
-// CHECK: [0x00,0x00,0x59,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2] slc
-// CHECK: [0x00,0x00,0x5a,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2]
-// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[252:255], v[1:2]
-// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0xfc]
-
-flat_load_dwordx4 v[5:8], v[254:255]
-// CHECK: [0x00,0x00,0x5c,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2] glc
-// CHECK: [0x00,0x00,0x5d,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2] slc
-// CHECK: [0x00,0x00,0x5e,0xdc,0x01,0x00,0x00,0x05]
-
-flat_store_byte v[1:2], v2
-// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte v[254:255], v2
-// CHECK: [0x00,0x00,0x60,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_byte v[1:2], v255
-// CHECK: [0x00,0x00,0x60,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_byte v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x61,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x62,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v2
-// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[254:255], v2
-// CHECK: [0x00,0x00,0x68,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v255
-// CHECK: [0x00,0x00,0x68,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_short v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x69,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x6a,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v2
-// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[254:255], v2
-// CHECK: [0x00,0x00,0x70,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v255
-// CHECK: [0x00,0x00,0x70,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_dword v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x71,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x72,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x74,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x74,0xdc,0x01,0xfe,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x75,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x76,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4]
-// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[254:255], v[2:4]
-// CHECK: [0x00,0x00,0x78,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[253:255]
-// CHECK: [0x00,0x00,0x78,0xdc,0x01,0xfd,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4] glc
-// CHECK: [0x00,0x00,0x79,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4] slc
-// CHECK: [0x00,0x00,0x7a,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5]
-// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[254:255], v[2:5]
-// CHECK: [0x00,0x00,0x7c,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[252:255]
-// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0xfc,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5] glc
-// CHECK: [0x00,0x00,0x7d,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5] slc
-// CHECK: [0x00,0x00,0x7e,0xdc,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v2
-// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[254:255], v2
-// CHECK: [0x00,0x00,0x00,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v255
-// CHECK: [0x00,0x00,0x00,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_swap v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x01,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x02,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x04,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x04,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x04,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_cmpswap v0, v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x05,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x06,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v2
-// CHECK: [0x00,0x00,0x08,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[254:255], v2
-// CHECK: [0x00,0x00,0x08,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v255
-// CHECK: [0x00,0x00,0x08,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_add v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x09,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x0a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v2
-// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[254:255], v2
-// CHECK: [0x00,0x00,0x0c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v255
-// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_sub v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x0d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x0e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v2
-// CHECK: [0x00,0x00,0x10,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[254:255], v2
-// CHECK: [0x00,0x00,0x10,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v255
-// CHECK: [0x00,0x00,0x10,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_smin v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x11,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x12,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v2
-// CHECK: [0x00,0x00,0x14,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[254:255], v2
-// CHECK: [0x00,0x00,0x14,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v255
-// CHECK: [0x00,0x00,0x14,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_umin v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x15,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x16,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v2
-// CHECK: [0x00,0x00,0x18,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[254:255], v2
-// CHECK: [0x00,0x00,0x18,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v255
-// CHECK: [0x00,0x00,0x18,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_smax v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x19,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x1a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v2
-// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[254:255], v2
-// CHECK: [0x00,0x00,0x1c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v255
-// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_umax v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x1d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x1e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v2
-// CHECK: [0x00,0x00,0x20,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[254:255], v2
-// CHECK: [0x00,0x00,0x20,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v255
-// CHECK: [0x00,0x00,0x20,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_and v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x21,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x22,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v2
-// CHECK: [0x00,0x00,0x24,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[254:255], v2
-// CHECK: [0x00,0x00,0x24,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v255
-// CHECK: [0x00,0x00,0x24,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_or v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x25,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x26,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v2
-// CHECK: [0x00,0x00,0x28,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[254:255], v2
-// CHECK: [0x00,0x00,0x28,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v255
-// CHECK: [0x00,0x00,0x28,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_xor v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x29,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x2a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v2
-// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[254:255], v2
-// CHECK: [0x00,0x00,0x2c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v255
-// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_inc v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x2d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x2e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v2
-// CHECK: [0x00,0x00,0x30,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[254:255], v2
-// CHECK: [0x00,0x00,0x30,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v255
-// CHECK: [0x00,0x00,0x30,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_dec v0, v[1:2], v2 glc
-// CHECK: [0x00,0x00,0x31,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v2 slc
-// CHECK: [0x00,0x00,0x32,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x80,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x80,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_swap_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x81,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x82,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5]
-// CHECK: [0x00,0x00,0x84,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[254:255], v[2:5]
-// CHECK: [0x00,0x00,0x84,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[252:255]
-// CHECK: [0x00,0x00,0x84,0xdd,0x01,0xfc,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[0:1], v[1:2], v[2:5] glc
-// CHECK: [0x00,0x00,0x85,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5] slc
-// CHECK: [0x00,0x00,0x86,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x88,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x88,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x88,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_add_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x89,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x8a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x8c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_sub_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x8d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x8e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x90,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x90,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x90,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_smin_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x91,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x92,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x94,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x94,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x94,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_umin_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x95,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x96,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x98,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x98,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x98,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_smax_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x99,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x9a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0x9c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_umax_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0x9d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0x9e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0xa0,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_and_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0xa1,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0xa2,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0xa4,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_or_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0xa5,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0xa6,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0xa8,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_xor_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0xa9,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0xaa,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xac,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0xac,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0xac,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_inc_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0xad,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0xae,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[254:255], v[2:3]
-// CHECK: [0x00,0x00,0xb0,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[254:255]
-// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_dec_x2 v[0:1], v[1:2], v[2:3] glc
-// CHECK: [0x00,0x00,0xb1,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3] slc
-// CHECK: [0x00,0x00,0xb2,0xdd,0x01,0x02,0x00,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v252, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0xfc,0x02,0x00]
-
-image_load v5, v[252:255], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0xfc,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[12:19] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x03,0x00]
-
-image_load v5, v[1:4], s[92:99] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x17,0x00]
-
-image_load v5, v[1:4], ttmp[4:11] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x1d,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x2
-// CHECK: [0x00,0x02,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x3
-// CHECK: [0x00,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x4
-// CHECK: [0x00,0x04,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x5
-// CHECK: [0x00,0x05,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x6
-// CHECK: [0x00,0x06,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0x7
-// CHECK: [0x00,0x07,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x8
-// CHECK: [0x00,0x08,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x9
-// CHECK: [0x00,0x09,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x0
-// CHECK: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x02,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x80]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v252, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0xfc,0x02,0x00]
-
-image_load_mip v5, v[252:255], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0xfc,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[12:19] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x03,0x00]
-
-image_load_mip v5, v[1:4], s[92:99] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x17,0x00]
-
-image_load_mip v5, v[1:4], ttmp[4:11] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x1d,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x2
-// CHECK: [0x00,0x02,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x3
-// CHECK: [0x00,0x03,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x4
-// CHECK: [0x00,0x04,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x5
-// CHECK: [0x00,0x05,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x6
-// CHECK: [0x00,0x06,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0x7
-// CHECK: [0x00,0x07,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x8
-// CHECK: [0x00,0x08,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x9
-// CHECK: [0x00,0x09,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x0
-// CHECK: [0x00,0x00,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x06,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x80]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v252, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0xfc,0x03,0x00]
-
-image_store v1, v[252:255], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0xfc,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x04,0x00]
-
-image_store v1, v[2:5], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x17,0x00]
-
-image_store v1, v[2:5], ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x1d,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x2 unorm
-// CHECK: [0x00,0x12,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x4 unorm
-// CHECK: [0x00,0x14,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x5 unorm
-// CHECK: [0x00,0x15,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x6 unorm
-// CHECK: [0x00,0x16,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0x7 unorm
-// CHECK: [0x00,0x17,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x8 unorm
-// CHECK: [0x00,0x18,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x9 unorm
-// CHECK: [0x00,0x19,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0xa unorm
-// CHECK: [0x00,0x1a,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0xb unorm
-// CHECK: [0x00,0x1b,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0xc unorm
-// CHECK: [0x00,0x1c,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0xd unorm
-// CHECK: [0x00,0x1d,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0xe unorm
-// CHECK: [0x00,0x1e,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:4], v[2:5], s[12:19] dmask:0xf unorm
-// CHECK: [0x00,0x1f,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x0 unorm
-// CHECK: [0x00,0x10,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x20,0xf2,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x22,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm d16
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x80]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v252, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0xfc,0x03,0x00]
-
-image_store_mip v1, v[252:255], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0xfc,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x04,0x00]
-
-image_store_mip v1, v[2:5], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x17,0x00]
-
-image_store_mip v1, v[2:5], ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x1d,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x2 unorm
-// CHECK: [0x00,0x12,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x4 unorm
-// CHECK: [0x00,0x14,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x5 unorm
-// CHECK: [0x00,0x15,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x6 unorm
-// CHECK: [0x00,0x16,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0x7 unorm
-// CHECK: [0x00,0x17,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x8 unorm
-// CHECK: [0x00,0x18,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x9 unorm
-// CHECK: [0x00,0x19,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0xa unorm
-// CHECK: [0x00,0x1a,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0xb unorm
-// CHECK: [0x00,0x1b,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0xc unorm
-// CHECK: [0x00,0x1c,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0xd unorm
-// CHECK: [0x00,0x1d,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0xe unorm
-// CHECK: [0x00,0x1e,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:4], v[2:5], s[12:19] dmask:0xf unorm
-// CHECK: [0x00,0x1f,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x0 unorm
-// CHECK: [0x00,0x10,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x24,0xf2,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x26,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm d16
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x80]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v252, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0xfc,0x02,0x00]
-
-image_get_resinfo v5, v[252:255], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0xfc,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[12:19] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x03,0x00]
-
-image_get_resinfo v5, v[1:4], s[92:99] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x17,0x00]
-
-image_get_resinfo v5, v[1:4], ttmp[4:11] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x1d,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x2
-// CHECK: [0x00,0x02,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x3
-// CHECK: [0x00,0x03,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x4
-// CHECK: [0x00,0x04,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x5
-// CHECK: [0x00,0x05,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x6
-// CHECK: [0x00,0x06,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v[1:4], s[8:15] dmask:0x7
-// CHECK: [0x00,0x07,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x8
-// CHECK: [0x00,0x08,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x9
-// CHECK: [0x00,0x09,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v[1:4], s[8:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v[1:4], s[8:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v[1:4], s[8:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x0
-// CHECK: [0x00,0x00,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v[1:4], s[8:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x3a,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v[1:4], s[8:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_swap v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_swap v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_swap v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_swap v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_swap v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x40,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x40,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x40,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x42,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x40,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[252:253], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v255, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v1, s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_cmpswap v[5:6], v1, s[92:99] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_cmpswap v[5:6], v1, ttmp[4:11] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_cmpswap v[5:8], v1, s[8:15] dmask:0xf unorm
-// CHECK: [0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm glc
-// CHECK: [0x00,0x33,0x44,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm slc
-// CHECK: [0x00,0x13,0x44,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm lwe
-// CHECK: [0x00,0x13,0x46,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm da
-// CHECK: [0x00,0x53,0x44,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_add v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_add v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_add v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_add v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_add v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x48,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x48,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x4a,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x48,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_sub v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_sub v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_sub v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_sub v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_sub v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x4c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x4c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x4c,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x4e,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x4c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_smin v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_smin v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_smin v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_smin v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_smin v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x50,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x50,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x50,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x52,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x50,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_umin v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_umin v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_umin v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_umin v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_umin v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x54,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x54,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x54,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x56,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x54,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_smax v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_smax v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_smax v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_smax v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_smax v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x58,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x58,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x58,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x5a,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x58,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_umax v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_umax v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_umax v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_umax v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_umax v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x5c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x5c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x5c,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x5e,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x5c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_and v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_and v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_and v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_and v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_and v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x60,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x60,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x60,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x62,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x60,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_or v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_or v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_or v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_or v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_or v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x64,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x64,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x64,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x66,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x64,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_xor v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_xor v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_xor v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_xor v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_xor v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x68,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x68,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x68,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x6a,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x68,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_inc v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_inc v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_inc v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_inc v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_inc v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x6c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x6c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x6c,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x6e,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x6c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v252, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_dec v5, v255, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0xff,0x05,0x02,0x00]
-
-image_atomic_dec v5, v1, s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_dec v5, v1, s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_dec v5, v1, ttmp[4:11] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x1d,0x00]
-
-image_atomic_dec v[5:6], v1, s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x70,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x70,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x70,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x72,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x70,0xf0,0x01,0x05,0x02,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x80,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x81,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x82,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x80,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x86,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_l v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_l v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_l v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_l v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x92,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_b v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_b v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_b v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_b v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x96,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_b_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_b_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_b_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_b_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x98,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x99,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x9a,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x98,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_lz v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_lz v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_lz v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_lz v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x9c,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x9d,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x9e,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x9c,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_c v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_c v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xa2,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_c_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_c_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xa4,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xa5,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xa6,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xa4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_l v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_l v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_c_l v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_c_l v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xb0,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xb1,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xb2,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xb0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_b v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_b v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_c_b v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_c_b v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xb4,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xb5,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xb6,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xb4,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_b_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_c_b_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xb8,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xb9,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xba,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xb8,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_lz v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_lz v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_c_lz v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x7d,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_c_lz v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0xc2,0x03]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xbe,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x80]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[252:255], v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4 v[5:8], v255, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0xff,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4 v[5:8], v1, s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4 v[5:8], v1, ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4 v[5:8], v1, s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x00,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x02,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x00,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_cl v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x04,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x06,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_l v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_l v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x10,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x12,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_b v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_b v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x14,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x16,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x18,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x1a,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x18,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[252:255], v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_lz v[5:8], v255, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0xff,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_lz v[5:8], v1, s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_lz v[5:8], v1, ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_lz v[5:8], v1, s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x1c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x1e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x1c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x20,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x22,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x24,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x26,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x24,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x30,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x32,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x30,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x34,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x36,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x34,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x38,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x3a,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x38,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x3c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x3e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_o v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x40,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x42,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x44,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x46,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x44,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x50,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x52,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x50,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x54,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x56,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x54,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x58,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x5a,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x58,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[254:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0xfe,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x5c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x5e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x60,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x62,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x60,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x64,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x66,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x64,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x70,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x72,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x70,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x74,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x76,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x74,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[248:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0xf8,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x78,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x7a,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x78,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[253:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0xfd,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x7d,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0xc2,0x03]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x7c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x7e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x7c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x80]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v252, v1, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0xfc,0x62,0x00]
-
-image_get_lod v5, v255, s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0xff,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x63,0x00]
-
-image_get_lod v5, v1, s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x77,0x00]
-
-image_get_lod v5, v1, ttmp[4:11], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x7d,0x00]
-
-image_get_lod v5, v1, s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x82,0x00]
-
-image_get_lod v5, v1, s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x02,0x03]
-
-image_get_lod v5, v1, s[8:15], ttmp[8:11] dmask:0x1
-// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0xc2,0x03]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:8], v1, s[8:15], s[12:15] dmask:0xf
-// CHECK: [0x00,0x0f,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x80,0xf3,0x01,0x05,0x62,0x00]
-
-image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x81,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x82,0xf1,0x01,0x05,0x62,0x00]
-
-image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x80,0xf1,0x01,0x05,0x62,0x00]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_format_x v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_x v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_x v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_x v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_x v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_x v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xy v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_xy v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x06,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0xfd,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_xyz v[5:7], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0a,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0xfc,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_xyzw v[5:8], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0e,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_format_x v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_x v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_x v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_x v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_x v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_x v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x12,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xy v[1:2], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_xy v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x16,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0xfd,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_xyz v[1:3], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1a,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0xfc,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_xyzw v[1:4], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1e,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_d16_x v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_d16_x v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_d16_x v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_d16_x v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_d16_x v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_d16_x v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_d16_x v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_d16_x v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x22,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_d16_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x26,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[253:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0xfd,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_d16_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2a,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[252:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0xfc,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_d16_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2e,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_d16_x v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_d16_x v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_d16_x v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_d16_x v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_d16_x v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_d16_x v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_d16_x v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_d16_x v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x32,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_d16_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x36,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[253:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0xfd,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_d16_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x3a,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[252:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0xfc,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_d16_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x3e,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ubyte v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_ubyte v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_ubyte v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ubyte v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ubyte v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ubyte v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ubyte v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ubyte v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sbyte v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_sbyte v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_sbyte v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sbyte v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sbyte v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sbyte v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sbyte v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sbyte v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ushort v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ushort v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_ushort v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_ushort v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ushort v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ushort v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ushort v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ushort v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sshort v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sshort v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_sshort v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_sshort v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sshort v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sshort v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sshort v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sshort v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sshort v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_dword v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dword v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dword v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_dword v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dword v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dword v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dword v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dword v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dword v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dword v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dwordx2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x56,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[253:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0xfd,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dwordx3 v[5:7], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x5a,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[252:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0xfc,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dwordx4 v[5:8], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x1e,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x5e,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_byte v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_byte v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_byte v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_byte v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_byte v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_byte v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_byte v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_byte v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_byte v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_byte v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x62,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_short v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_short v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_short v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_short v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_short v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_short v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_short v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_short v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_short v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_short v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x6a,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_dword v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dword v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dword v1, off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_dword v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dword v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dword v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dword v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dword v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dword v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dword v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x72,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dwordx2 v[1:2], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x76,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[253:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0xfd,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dwordx3 v[1:3], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x7a,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[252:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0xfc,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dwordx4 v[1:4], off, ttmp[8:11], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x1e,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x7e,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_wbinvl1
-// CHECK: [0x00,0x00,0xf8,0xe0,0x00,0x00,0x00,0x00]
-
-buffer_wbinvl1_vol
-// CHECK: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_swap v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_swap v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_swap v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_swap v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_swap v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_swap v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_swap v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_swap v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x02,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x06,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_add v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_add v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_add v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_add v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_add v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_add v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_add v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_add v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_sub v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_sub v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_sub v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_sub v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_sub v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_sub v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_sub v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_sub v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smin v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smin v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smin v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smin v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smin v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smin v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_smin v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_smin v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x12,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umin v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umin v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umin v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umin v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umin v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umin v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_umin v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_umin v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x16,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smax v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smax v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smax v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smax v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smax v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smax v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_smax v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_smax v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umax v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umax v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umax v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umax v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umax v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umax v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_umax v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_umax v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_and v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_and v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_and v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_and v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_and v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_and v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_and v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_and v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_and v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x22,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_or v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_or v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_or v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_or v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_or v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_or v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_or v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_or v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_or v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x26,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_xor v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_xor v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_xor v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_xor v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_xor v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_xor v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_xor v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_xor v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_inc v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_inc v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_inc v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_inc v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_inc v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_inc v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_inc v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_inc v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_dec v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_dec v5, off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_dec v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_dec v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_dec v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_dec v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_dec v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_dec v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x32,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x82,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[252:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0xfc,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x86,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x8a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x8e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x92,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x96,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x9a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x9e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xa2,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xa6,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xaa,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xae,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x1e,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xb2,0xe1,0x00,0x05,0x02,0x03]
-
-s_load_dword s5, s[2:3], s2
-// CHECK: [0x41,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword s101, s[2:3], s2
-// CHECK: [0x41,0x19,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword flat_scratch_lo, s[2:3], s2
-// CHECK: [0x81,0x19,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword flat_scratch_hi, s[2:3], s2
-// CHECK: [0xc1,0x19,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword vcc_lo, s[2:3], s2
-// CHECK: [0x81,0x1a,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword vcc_hi, s[2:3], s2
-// CHECK: [0xc1,0x1a,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword tba_lo, s[2:3], s2
-// CHECK: [0x01,0x1b,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword tba_hi, s[2:3], s2
-// CHECK: [0x41,0x1b,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword tma_lo, s[2:3], s2
-// CHECK: [0x81,0x1b,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword tma_hi, s[2:3], s2
-// CHECK: [0xc1,0x1b,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword ttmp11, s[2:3], s2
-// CHECK: [0xc1,0x1e,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword s5, s[4:5], s2
-// CHECK: [0x42,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword s5, s[100:101], s2
-// CHECK: [0x72,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword s5, flat_scratch, s2
-// CHECK: [0x73,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword s5, vcc, s2
-// CHECK: [0x75,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword s5, tba, s2
-// CHECK: [0x76,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword s5, tma, s2
-// CHECK: [0x77,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword s5, ttmp[10:11], s2
-// CHECK: [0x7d,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], s101
-// CHECK: [0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], flat_scratch_lo
-// CHECK: [0x41,0x01,0x00,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], flat_scratch_hi
-// CHECK: [0x41,0x01,0x00,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], vcc_lo
-// CHECK: [0x41,0x01,0x00,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], vcc_hi
-// CHECK: [0x41,0x01,0x00,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], tba_lo
-// CHECK: [0x41,0x01,0x00,0xc0,0x6c,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], tba_hi
-// CHECK: [0x41,0x01,0x00,0xc0,0x6d,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], tma_lo
-// CHECK: [0x41,0x01,0x00,0xc0,0x6e,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], tma_hi
-// CHECK: [0x41,0x01,0x00,0xc0,0x6f,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], ttmp11
-// CHECK: [0x41,0x01,0x00,0xc0,0x7b,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], m0
-// CHECK: [0x41,0x01,0x00,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], 0x7ffff
-// CHECK: [0x41,0x01,0x02,0xc0,0xff,0xff,0x07,0x00]
-
-s_load_dword s5, s[2:3], s2 glc
-// CHECK: [0x41,0x01,0x01,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], s2
-// CHECK: [0x81,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[12:13], s[2:3], s2
-// CHECK: [0x01,0x03,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[100:101], s[2:3], s2
-// CHECK: [0x01,0x19,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 flat_scratch, s[2:3], s2
-// CHECK: [0x81,0x19,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 vcc, s[2:3], s2
-// CHECK: [0x81,0x1a,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 tba, s[2:3], s2
-// CHECK: [0x01,0x1b,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 tma, s[2:3], s2
-// CHECK: [0x81,0x1b,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 ttmp[10:11], s[2:3], s2
-// CHECK: [0x81,0x1e,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[4:5], s2
-// CHECK: [0x82,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[100:101], s2
-// CHECK: [0xb2,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], flat_scratch, s2
-// CHECK: [0xb3,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], vcc, s2
-// CHECK: [0xb5,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], tba, s2
-// CHECK: [0xb6,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], tma, s2
-// CHECK: [0xb7,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], ttmp[10:11], s2
-// CHECK: [0xbd,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], s101
-// CHECK: [0x81,0x02,0x04,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x81,0x02,0x04,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x81,0x02,0x04,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x81,0x02,0x04,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x81,0x02,0x04,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], tba_lo
-// CHECK: [0x81,0x02,0x04,0xc0,0x6c,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], tba_hi
-// CHECK: [0x81,0x02,0x04,0xc0,0x6d,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], tma_lo
-// CHECK: [0x81,0x02,0x04,0xc0,0x6e,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], tma_hi
-// CHECK: [0x81,0x02,0x04,0xc0,0x6f,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], ttmp11
-// CHECK: [0x81,0x02,0x04,0xc0,0x7b,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], m0
-// CHECK: [0x81,0x02,0x04,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], 0x7ffff
-// CHECK: [0x81,0x02,0x06,0xc0,0xff,0xff,0x07,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], s2 glc
-// CHECK: [0x81,0x02,0x05,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], s2
-// CHECK: [0x01,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[24:27], s[2:3], s2
-// CHECK: [0x01,0x06,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[96:99], s[2:3], s2
-// CHECK: [0x01,0x18,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 ttmp[8:11], s[2:3], s2
-// CHECK: [0x01,0x1e,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[4:5], s2
-// CHECK: [0x02,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[100:101], s2
-// CHECK: [0x32,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], flat_scratch, s2
-// CHECK: [0x33,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], vcc, s2
-// CHECK: [0x35,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], tba, s2
-// CHECK: [0x36,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], tma, s2
-// CHECK: [0x37,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], ttmp[10:11], s2
-// CHECK: [0x3d,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], s101
-// CHECK: [0x01,0x05,0x08,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], flat_scratch_lo
-// CHECK: [0x01,0x05,0x08,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], flat_scratch_hi
-// CHECK: [0x01,0x05,0x08,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], vcc_lo
-// CHECK: [0x01,0x05,0x08,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], vcc_hi
-// CHECK: [0x01,0x05,0x08,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], tba_lo
-// CHECK: [0x01,0x05,0x08,0xc0,0x6c,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], tba_hi
-// CHECK: [0x01,0x05,0x08,0xc0,0x6d,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], tma_lo
-// CHECK: [0x01,0x05,0x08,0xc0,0x6e,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], tma_hi
-// CHECK: [0x01,0x05,0x08,0xc0,0x6f,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], ttmp11
-// CHECK: [0x01,0x05,0x08,0xc0,0x7b,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], m0
-// CHECK: [0x01,0x05,0x08,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], 0x7ffff
-// CHECK: [0x01,0x05,0x0a,0xc0,0xff,0xff,0x07,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], s2 glc
-// CHECK: [0x01,0x05,0x09,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], s2
-// CHECK: [0x01,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[24:31], s[2:3], s2
-// CHECK: [0x01,0x06,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[92:99], s[2:3], s2
-// CHECK: [0x01,0x17,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 ttmp[4:11], s[2:3], s2
-// CHECK: [0x01,0x1d,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[4:5], s2
-// CHECK: [0x02,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[100:101], s2
-// CHECK: [0x32,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], flat_scratch, s2
-// CHECK: [0x33,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], vcc, s2
-// CHECK: [0x35,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], tba, s2
-// CHECK: [0x36,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], tma, s2
-// CHECK: [0x37,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], ttmp[10:11], s2
-// CHECK: [0x3d,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], s101
-// CHECK: [0x01,0x05,0x0c,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], flat_scratch_lo
-// CHECK: [0x01,0x05,0x0c,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], flat_scratch_hi
-// CHECK: [0x01,0x05,0x0c,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], vcc_lo
-// CHECK: [0x01,0x05,0x0c,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], vcc_hi
-// CHECK: [0x01,0x05,0x0c,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], tba_lo
-// CHECK: [0x01,0x05,0x0c,0xc0,0x6c,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], tba_hi
-// CHECK: [0x01,0x05,0x0c,0xc0,0x6d,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], tma_lo
-// CHECK: [0x01,0x05,0x0c,0xc0,0x6e,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], tma_hi
-// CHECK: [0x01,0x05,0x0c,0xc0,0x6f,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], ttmp11
-// CHECK: [0x01,0x05,0x0c,0xc0,0x7b,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], m0
-// CHECK: [0x01,0x05,0x0c,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], 0x7ffff
-// CHECK: [0x01,0x05,0x0e,0xc0,0xff,0xff,0x07,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], s2 glc
-// CHECK: [0x01,0x05,0x0d,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], s2
-// CHECK: [0x01,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[24:39], s[2:3], s2
-// CHECK: [0x01,0x06,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[84:99], s[2:3], s2
-// CHECK: [0x01,0x15,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[4:5], s2
-// CHECK: [0x02,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[100:101], s2
-// CHECK: [0x32,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], flat_scratch, s2
-// CHECK: [0x33,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], vcc, s2
-// CHECK: [0x35,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], tba, s2
-// CHECK: [0x36,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], tma, s2
-// CHECK: [0x37,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], ttmp[10:11], s2
-// CHECK: [0x3d,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], s101
-// CHECK: [0x01,0x05,0x10,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], flat_scratch_lo
-// CHECK: [0x01,0x05,0x10,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], flat_scratch_hi
-// CHECK: [0x01,0x05,0x10,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], vcc_lo
-// CHECK: [0x01,0x05,0x10,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], vcc_hi
-// CHECK: [0x01,0x05,0x10,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], tba_lo
-// CHECK: [0x01,0x05,0x10,0xc0,0x6c,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], tba_hi
-// CHECK: [0x01,0x05,0x10,0xc0,0x6d,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], tma_lo
-// CHECK: [0x01,0x05,0x10,0xc0,0x6e,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], tma_hi
-// CHECK: [0x01,0x05,0x10,0xc0,0x6f,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], ttmp11
-// CHECK: [0x01,0x05,0x10,0xc0,0x7b,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], m0
-// CHECK: [0x01,0x05,0x10,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], 0x7ffff
-// CHECK: [0x01,0x05,0x12,0xc0,0xff,0xff,0x07,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], s2 glc
-// CHECK: [0x01,0x05,0x11,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], s2
-// CHECK: [0x42,0x01,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword s101, s[4:7], s2
-// CHECK: [0x42,0x19,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword flat_scratch_lo, s[4:7], s2
-// CHECK: [0x82,0x19,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword flat_scratch_hi, s[4:7], s2
-// CHECK: [0xc2,0x19,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword vcc_lo, s[4:7], s2
-// CHECK: [0x82,0x1a,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword vcc_hi, s[4:7], s2
-// CHECK: [0xc2,0x1a,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword tba_lo, s[4:7], s2
-// CHECK: [0x02,0x1b,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword tba_hi, s[4:7], s2
-// CHECK: [0x42,0x1b,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword tma_lo, s[4:7], s2
-// CHECK: [0x82,0x1b,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword tma_hi, s[4:7], s2
-// CHECK: [0xc2,0x1b,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword ttmp11, s[4:7], s2
-// CHECK: [0xc2,0x1e,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[8:11], s2
-// CHECK: [0x44,0x01,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[96:99], s2
-// CHECK: [0x70,0x01,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, ttmp[8:11], s2
-// CHECK: [0x7c,0x01,0x20,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], s101
-// CHECK: [0x42,0x01,0x20,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], flat_scratch_lo
-// CHECK: [0x42,0x01,0x20,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], flat_scratch_hi
-// CHECK: [0x42,0x01,0x20,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], vcc_lo
-// CHECK: [0x42,0x01,0x20,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], vcc_hi
-// CHECK: [0x42,0x01,0x20,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], tba_lo
-// CHECK: [0x42,0x01,0x20,0xc0,0x6c,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], tba_hi
-// CHECK: [0x42,0x01,0x20,0xc0,0x6d,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], tma_lo
-// CHECK: [0x42,0x01,0x20,0xc0,0x6e,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], tma_hi
-// CHECK: [0x42,0x01,0x20,0xc0,0x6f,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], ttmp11
-// CHECK: [0x42,0x01,0x20,0xc0,0x7b,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], m0
-// CHECK: [0x42,0x01,0x20,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], 0x7ffff
-// CHECK: [0x42,0x01,0x22,0xc0,0xff,0xff,0x07,0x00]
-
-s_buffer_load_dword s5, s[4:7], s2 glc
-// CHECK: [0x42,0x01,0x21,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s2
-// CHECK: [0x82,0x02,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[12:13], s[4:7], s2
-// CHECK: [0x02,0x03,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[100:101], s[4:7], s2
-// CHECK: [0x02,0x19,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 flat_scratch, s[4:7], s2
-// CHECK: [0x82,0x19,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 vcc, s[4:7], s2
-// CHECK: [0x82,0x1a,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 tba, s[4:7], s2
-// CHECK: [0x02,0x1b,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 tma, s[4:7], s2
-// CHECK: [0x82,0x1b,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 ttmp[10:11], s[4:7], s2
-// CHECK: [0x82,0x1e,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[8:11], s2
-// CHECK: [0x84,0x02,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[96:99], s2
-// CHECK: [0xb0,0x02,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], ttmp[8:11], s2
-// CHECK: [0xbc,0x02,0x24,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s101
-// CHECK: [0x82,0x02,0x24,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_lo
-// CHECK: [0x82,0x02,0x24,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_hi
-// CHECK: [0x82,0x02,0x24,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_lo
-// CHECK: [0x82,0x02,0x24,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
-// CHECK: [0x82,0x02,0x24,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], tba_lo
-// CHECK: [0x82,0x02,0x24,0xc0,0x6c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], tba_hi
-// CHECK: [0x82,0x02,0x24,0xc0,0x6d,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], tma_lo
-// CHECK: [0x82,0x02,0x24,0xc0,0x6e,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], tma_hi
-// CHECK: [0x82,0x02,0x24,0xc0,0x6f,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], ttmp11
-// CHECK: [0x82,0x02,0x24,0xc0,0x7b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], m0
-// CHECK: [0x82,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], 0x7ffff
-// CHECK: [0x82,0x02,0x26,0xc0,0xff,0xff,0x07,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s2 glc
-// CHECK: [0x82,0x02,0x25,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s2
-// CHECK: [0x02,0x05,0x28,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[24:27], s[4:7], s2
-// CHECK: [0x02,0x06,0x28,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[96:99], s[4:7], s2
-// CHECK: [0x02,0x18,0x28,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 ttmp[8:11], s[4:7], s2
-// CHECK: [0x02,0x1e,0x28,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[8:11], s2
-// CHECK: [0x04,0x05,0x28,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[96:99], s2
-// CHECK: [0x30,0x05,0x28,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], ttmp[8:11], s2
-// CHECK: [0x3c,0x05,0x28,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s101
-// CHECK: [0x02,0x05,0x28,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_lo
-// CHECK: [0x02,0x05,0x28,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_hi
-// CHECK: [0x02,0x05,0x28,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_lo
-// CHECK: [0x02,0x05,0x28,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
-// CHECK: [0x02,0x05,0x28,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], tba_lo
-// CHECK: [0x02,0x05,0x28,0xc0,0x6c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], tba_hi
-// CHECK: [0x02,0x05,0x28,0xc0,0x6d,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], tma_lo
-// CHECK: [0x02,0x05,0x28,0xc0,0x6e,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], tma_hi
-// CHECK: [0x02,0x05,0x28,0xc0,0x6f,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], ttmp11
-// CHECK: [0x02,0x05,0x28,0xc0,0x7b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], m0
-// CHECK: [0x02,0x05,0x28,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], 0x7ffff
-// CHECK: [0x02,0x05,0x2a,0xc0,0xff,0xff,0x07,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s2 glc
-// CHECK: [0x02,0x05,0x29,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s2
-// CHECK: [0x02,0x05,0x2c,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[24:31], s[4:7], s2
-// CHECK: [0x02,0x06,0x2c,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[92:99], s[4:7], s2
-// CHECK: [0x02,0x17,0x2c,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 ttmp[4:11], s[4:7], s2
-// CHECK: [0x02,0x1d,0x2c,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[8:11], s2
-// CHECK: [0x04,0x05,0x2c,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[96:99], s2
-// CHECK: [0x30,0x05,0x2c,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], ttmp[8:11], s2
-// CHECK: [0x3c,0x05,0x2c,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s101
-// CHECK: [0x02,0x05,0x2c,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_lo
-// CHECK: [0x02,0x05,0x2c,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_hi
-// CHECK: [0x02,0x05,0x2c,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_lo
-// CHECK: [0x02,0x05,0x2c,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
-// CHECK: [0x02,0x05,0x2c,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], tba_lo
-// CHECK: [0x02,0x05,0x2c,0xc0,0x6c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], tba_hi
-// CHECK: [0x02,0x05,0x2c,0xc0,0x6d,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], tma_lo
-// CHECK: [0x02,0x05,0x2c,0xc0,0x6e,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], tma_hi
-// CHECK: [0x02,0x05,0x2c,0xc0,0x6f,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], ttmp11
-// CHECK: [0x02,0x05,0x2c,0xc0,0x7b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], m0
-// CHECK: [0x02,0x05,0x2c,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], 0x7ffff
-// CHECK: [0x02,0x05,0x2e,0xc0,0xff,0xff,0x07,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s2 glc
-// CHECK: [0x02,0x05,0x2d,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s2
-// CHECK: [0x02,0x05,0x30,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[24:39], s[4:7], s2
-// CHECK: [0x02,0x06,0x30,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[84:99], s[4:7], s2
-// CHECK: [0x02,0x15,0x30,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[8:11], s2
-// CHECK: [0x04,0x05,0x30,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[96:99], s2
-// CHECK: [0x30,0x05,0x30,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], ttmp[8:11], s2
-// CHECK: [0x3c,0x05,0x30,0xc0,0x02,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s101
-// CHECK: [0x02,0x05,0x30,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_lo
-// CHECK: [0x02,0x05,0x30,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_hi
-// CHECK: [0x02,0x05,0x30,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_lo
-// CHECK: [0x02,0x05,0x30,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
-// CHECK: [0x02,0x05,0x30,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], tba_lo
-// CHECK: [0x02,0x05,0x30,0xc0,0x6c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], tba_hi
-// CHECK: [0x02,0x05,0x30,0xc0,0x6d,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], tma_lo
-// CHECK: [0x02,0x05,0x30,0xc0,0x6e,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], tma_hi
-// CHECK: [0x02,0x05,0x30,0xc0,0x6f,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], ttmp11
-// CHECK: [0x02,0x05,0x30,0xc0,0x7b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], m0
-// CHECK: [0x02,0x05,0x30,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], 0x7ffff
-// CHECK: [0x02,0x05,0x32,0xc0,0xff,0xff,0x07,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s2 glc
-// CHECK: [0x02,0x05,0x31,0xc0,0x02,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], m0
-// CHECK: [0x42,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s101, s[4:5], m0
-// CHECK: [0x42,0x19,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword flat_scratch_lo, s[4:5], m0
-// CHECK: [0x82,0x19,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword flat_scratch_hi, s[4:5], m0
-// CHECK: [0xc2,0x19,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword vcc_lo, s[4:5], m0
-// CHECK: [0x82,0x1a,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword vcc_hi, s[4:5], m0
-// CHECK: [0xc2,0x1a,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword tba_lo, s[4:5], m0
-// CHECK: [0x02,0x1b,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword tba_hi, s[4:5], m0
-// CHECK: [0x42,0x1b,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword tma_lo, s[4:5], m0
-// CHECK: [0x82,0x1b,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword tma_hi, s[4:5], m0
-// CHECK: [0xc2,0x1b,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword ttmp11, s[4:5], m0
-// CHECK: [0xc2,0x1e,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s1, s[6:7], m0
-// CHECK: [0x43,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s1, s[100:101], m0
-// CHECK: [0x72,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s1, flat_scratch, m0
-// CHECK: [0x73,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s1, vcc, m0
-// CHECK: [0x75,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s1, tba, m0
-// CHECK: [0x76,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s1, tma, m0
-// CHECK: [0x77,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s1, ttmp[10:11], m0
-// CHECK: [0x7d,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], 0x7ffff
-// CHECK: [0x42,0x00,0x42,0xc0,0xff,0xff,0x07,0x00]
-
-s_store_dword s1, s[4:5], m0 glc
-// CHECK: [0x42,0x00,0x41,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], m0
-// CHECK: [0x82,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[4:5], s[4:5], m0
-// CHECK: [0x02,0x01,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[100:101], s[4:5], m0
-// CHECK: [0x02,0x19,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 flat_scratch, s[4:5], m0
-// CHECK: [0x82,0x19,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 vcc, s[4:5], m0
-// CHECK: [0x82,0x1a,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 tba, s[4:5], m0
-// CHECK: [0x02,0x1b,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 tma, s[4:5], m0
-// CHECK: [0x82,0x1b,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 ttmp[10:11], s[4:5], m0
-// CHECK: [0x82,0x1e,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[6:7], m0
-// CHECK: [0x83,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[100:101], m0
-// CHECK: [0xb2,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], flat_scratch, m0
-// CHECK: [0xb3,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], vcc, m0
-// CHECK: [0xb5,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], tba, m0
-// CHECK: [0xb6,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], tma, m0
-// CHECK: [0xb7,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], ttmp[10:11], m0
-// CHECK: [0xbd,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], 0x7ffff
-// CHECK: [0x82,0x00,0x46,0xc0,0xff,0xff,0x07,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], m0 glc
-// CHECK: [0x82,0x00,0x45,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], m0
-// CHECK: [0x02,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[8:11], s[4:5], m0
-// CHECK: [0x02,0x02,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[96:99], s[4:5], m0
-// CHECK: [0x02,0x18,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 ttmp[8:11], s[4:5], m0
-// CHECK: [0x02,0x1e,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[6:7], m0
-// CHECK: [0x03,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[100:101], m0
-// CHECK: [0x32,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], flat_scratch, m0
-// CHECK: [0x33,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], vcc, m0
-// CHECK: [0x35,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], tba, m0
-// CHECK: [0x36,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], tma, m0
-// CHECK: [0x37,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], ttmp[10:11], m0
-// CHECK: [0x3d,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], 0x7ffff
-// CHECK: [0x02,0x01,0x4a,0xc0,0xff,0xff,0x07,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], m0 glc
-// CHECK: [0x02,0x01,0x49,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], m0
-// CHECK: [0x44,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword s101, s[8:11], m0
-// CHECK: [0x44,0x19,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword flat_scratch_lo, s[8:11], m0
-// CHECK: [0x84,0x19,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword flat_scratch_hi, s[8:11], m0
-// CHECK: [0xc4,0x19,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword vcc_lo, s[8:11], m0
-// CHECK: [0x84,0x1a,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword vcc_hi, s[8:11], m0
-// CHECK: [0xc4,0x1a,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword tba_lo, s[8:11], m0
-// CHECK: [0x04,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword tba_hi, s[8:11], m0
-// CHECK: [0x44,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword tma_lo, s[8:11], m0
-// CHECK: [0x84,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword tma_hi, s[8:11], m0
-// CHECK: [0xc4,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword ttmp11, s[8:11], m0
-// CHECK: [0xc4,0x1e,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[12:15], m0
-// CHECK: [0x46,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[96:99], m0
-// CHECK: [0x70,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, ttmp[8:11], m0
-// CHECK: [0x7c,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], 0x7ffff
-// CHECK: [0x44,0x00,0x62,0xc0,0xff,0xff,0x07,0x00]
-
-s_buffer_store_dword s1, s[8:11], m0 glc
-// CHECK: [0x44,0x00,0x61,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], m0
-// CHECK: [0x84,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[4:5], s[8:11], m0
-// CHECK: [0x04,0x01,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[100:101], s[8:11], m0
-// CHECK: [0x04,0x19,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 flat_scratch, s[8:11], m0
-// CHECK: [0x84,0x19,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 vcc, s[8:11], m0
-// CHECK: [0x84,0x1a,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 tba, s[8:11], m0
-// CHECK: [0x04,0x1b,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 tma, s[8:11], m0
-// CHECK: [0x84,0x1b,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 ttmp[10:11], s[8:11], m0
-// CHECK: [0x84,0x1e,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[12:15], m0
-// CHECK: [0x86,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[96:99], m0
-// CHECK: [0xb0,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], ttmp[8:11], m0
-// CHECK: [0xbc,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], 0x7ffff
-// CHECK: [0x84,0x00,0x66,0xc0,0xff,0xff,0x07,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], m0 glc
-// CHECK: [0x84,0x00,0x65,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], m0
-// CHECK: [0x04,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[8:11], s[8:11], m0
-// CHECK: [0x04,0x02,0x68,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[96:99], s[8:11], m0
-// CHECK: [0x04,0x18,0x68,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 ttmp[8:11], s[8:11], m0
-// CHECK: [0x04,0x1e,0x68,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[12:15], m0
-// CHECK: [0x06,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[96:99], m0
-// CHECK: [0x30,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], ttmp[8:11], m0
-// CHECK: [0x3c,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], 0x7ffff
-// CHECK: [0x04,0x01,0x6a,0xc0,0xff,0xff,0x07,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], m0 glc
-// CHECK: [0x04,0x01,0x69,0xc0,0x7c,0x00,0x00,0x00]
-
-s_dcache_inv
-// CHECK: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
-
-s_dcache_wb
-// CHECK: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
-
-s_dcache_inv_vol
-// CHECK: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
-
-s_dcache_wb_vol
-// CHECK: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime s[10:11]
-// CHECK: [0x80,0x02,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime s[12:13]
-// CHECK: [0x00,0x03,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime s[100:101]
-// CHECK: [0x00,0x19,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime flat_scratch
-// CHECK: [0x80,0x19,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime vcc
-// CHECK: [0x80,0x1a,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime tba
-// CHECK: [0x00,0x1b,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime tma
-// CHECK: [0x80,0x1b,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime ttmp[10:11]
-// CHECK: [0x80,0x1e,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime s[10:11]
-// CHECK: [0x80,0x02,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime s[12:13]
-// CHECK: [0x00,0x03,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime s[100:101]
-// CHECK: [0x00,0x19,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime flat_scratch
-// CHECK: [0x80,0x19,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime vcc
-// CHECK: [0x80,0x1a,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime tba
-// CHECK: [0x00,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime tma
-// CHECK: [0x80,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime ttmp[10:11]
-// CHECK: [0x80,0x1e,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_mov_b32 s5, s1
-// CHECK: [0x01,0x00,0x85,0xbe]
-
-s_mov_b32 s101, s1
-// CHECK: [0x01,0x00,0xe5,0xbe]
-
-s_mov_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x00,0xe6,0xbe]
-
-s_mov_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x00,0xe7,0xbe]
-
-s_mov_b32 vcc_lo, s1
-// CHECK: [0x01,0x00,0xea,0xbe]
-
-s_mov_b32 vcc_hi, s1
-// CHECK: [0x01,0x00,0xeb,0xbe]
-
-s_mov_b32 tba_lo, s1
-// CHECK: [0x01,0x00,0xec,0xbe]
-
-s_mov_b32 tba_hi, s1
-// CHECK: [0x01,0x00,0xed,0xbe]
-
-s_mov_b32 tma_lo, s1
-// CHECK: [0x01,0x00,0xee,0xbe]
-
-s_mov_b32 tma_hi, s1
-// CHECK: [0x01,0x00,0xef,0xbe]
-
-s_mov_b32 ttmp11, s1
-// CHECK: [0x01,0x00,0xfb,0xbe]
-
-s_mov_b32 m0, s1
-// CHECK: [0x01,0x00,0xfc,0xbe]
-
-s_mov_b32 exec_lo, s1
-// CHECK: [0x01,0x00,0xfe,0xbe]
-
-s_mov_b32 exec_hi, s1
-// CHECK: [0x01,0x00,0xff,0xbe]
-
-s_mov_b32 s5, s101
-// CHECK: [0x65,0x00,0x85,0xbe]
-
-s_mov_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x00,0x85,0xbe]
-
-s_mov_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x00,0x85,0xbe]
-
-s_mov_b32 s5, vcc_lo
-// CHECK: [0x6a,0x00,0x85,0xbe]
-
-s_mov_b32 s5, vcc_hi
-// CHECK: [0x6b,0x00,0x85,0xbe]
-
-s_mov_b32 s5, tba_lo
-// CHECK: [0x6c,0x00,0x85,0xbe]
-
-s_mov_b32 s5, tba_hi
-// CHECK: [0x6d,0x00,0x85,0xbe]
-
-s_mov_b32 s5, tma_lo
-// CHECK: [0x6e,0x00,0x85,0xbe]
-
-s_mov_b32 s5, tma_hi
-// CHECK: [0x6f,0x00,0x85,0xbe]
-
-s_mov_b32 s5, ttmp11
-// CHECK: [0x7b,0x00,0x85,0xbe]
-
-s_mov_b32 s5, m0
-// CHECK: [0x7c,0x00,0x85,0xbe]
-
-s_mov_b32 s5, exec_lo
-// CHECK: [0x7e,0x00,0x85,0xbe]
-
-s_mov_b32 s5, exec_hi
-// CHECK: [0x7f,0x00,0x85,0xbe]
-
-s_mov_b32 s5, 0
-// CHECK: [0x80,0x00,0x85,0xbe]
-
-s_mov_b32 s5, -1
-// CHECK: [0xc1,0x00,0x85,0xbe]
-
-s_mov_b32 s5, 0.5
-// CHECK: [0xf0,0x00,0x85,0xbe]
-
-s_mov_b32 s5, -4.0
-// CHECK: [0xf7,0x00,0x85,0xbe]
-
-s_mov_b32 s5, 0xaf123456
-// CHECK: [0xff,0x00,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_mov_b32 s5, 0x3f717273
-// CHECK: [0xff,0x00,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_mov_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x01,0x8a,0xbe]
-
-s_mov_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x01,0x8c,0xbe]
-
-s_mov_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x01,0xe4,0xbe]
-
-s_mov_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x01,0xe6,0xbe]
-
-s_mov_b64 vcc, s[2:3]
-// CHECK: [0x02,0x01,0xea,0xbe]
-
-s_mov_b64 tba, s[2:3]
-// CHECK: [0x02,0x01,0xec,0xbe]
-
-s_mov_b64 tma, s[2:3]
-// CHECK: [0x02,0x01,0xee,0xbe]
-
-s_mov_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x01,0xfa,0xbe]
-
-s_mov_b64 exec, s[2:3]
-// CHECK: [0x02,0x01,0xfe,0xbe]
-
-s_mov_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], vcc
-// CHECK: [0x6a,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], tba
-// CHECK: [0x6c,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], tma
-// CHECK: [0x6e,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], exec
-// CHECK: [0x7e,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], 0
-// CHECK: [0x80,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], -1
-// CHECK: [0xc1,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x01,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_mov_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x01,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cmov_b32 s5, s1
-// CHECK: [0x01,0x02,0x85,0xbe]
-
-s_cmov_b32 s101, s1
-// CHECK: [0x01,0x02,0xe5,0xbe]
-
-s_cmov_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x02,0xe6,0xbe]
-
-s_cmov_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x02,0xe7,0xbe]
-
-s_cmov_b32 vcc_lo, s1
-// CHECK: [0x01,0x02,0xea,0xbe]
-
-s_cmov_b32 vcc_hi, s1
-// CHECK: [0x01,0x02,0xeb,0xbe]
-
-s_cmov_b32 tba_lo, s1
-// CHECK: [0x01,0x02,0xec,0xbe]
-
-s_cmov_b32 tba_hi, s1
-// CHECK: [0x01,0x02,0xed,0xbe]
-
-s_cmov_b32 tma_lo, s1
-// CHECK: [0x01,0x02,0xee,0xbe]
-
-s_cmov_b32 tma_hi, s1
-// CHECK: [0x01,0x02,0xef,0xbe]
-
-s_cmov_b32 ttmp11, s1
-// CHECK: [0x01,0x02,0xfb,0xbe]
-
-s_cmov_b32 m0, s1
-// CHECK: [0x01,0x02,0xfc,0xbe]
-
-s_cmov_b32 exec_lo, s1
-// CHECK: [0x01,0x02,0xfe,0xbe]
-
-s_cmov_b32 exec_hi, s1
-// CHECK: [0x01,0x02,0xff,0xbe]
-
-s_cmov_b32 s5, s101
-// CHECK: [0x65,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, vcc_lo
-// CHECK: [0x6a,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, vcc_hi
-// CHECK: [0x6b,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, tba_lo
-// CHECK: [0x6c,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, tba_hi
-// CHECK: [0x6d,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, tma_lo
-// CHECK: [0x6e,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, tma_hi
-// CHECK: [0x6f,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, ttmp11
-// CHECK: [0x7b,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, m0
-// CHECK: [0x7c,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, exec_lo
-// CHECK: [0x7e,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, exec_hi
-// CHECK: [0x7f,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, 0
-// CHECK: [0x80,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, -1
-// CHECK: [0xc1,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, 0.5
-// CHECK: [0xf0,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, -4.0
-// CHECK: [0xf7,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, 0xaf123456
-// CHECK: [0xff,0x02,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_cmov_b32 s5, 0x3f717273
-// CHECK: [0xff,0x02,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cmov_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x03,0x8c,0xbe]
-
-s_cmov_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x03,0xe4,0xbe]
-
-s_cmov_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x03,0xe6,0xbe]
-
-s_cmov_b64 vcc, s[2:3]
-// CHECK: [0x02,0x03,0xea,0xbe]
-
-s_cmov_b64 tba, s[2:3]
-// CHECK: [0x02,0x03,0xec,0xbe]
-
-s_cmov_b64 tma, s[2:3]
-// CHECK: [0x02,0x03,0xee,0xbe]
-
-s_cmov_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x03,0xfa,0xbe]
-
-s_cmov_b64 exec, s[2:3]
-// CHECK: [0x02,0x03,0xfe,0xbe]
-
-s_cmov_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], vcc
-// CHECK: [0x6a,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], tba
-// CHECK: [0x6c,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], tma
-// CHECK: [0x6e,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], exec
-// CHECK: [0x7e,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], 0
-// CHECK: [0x80,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], -1
-// CHECK: [0xc1,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x03,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_cmov_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x03,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_not_b32 s5, s1
-// CHECK: [0x01,0x04,0x85,0xbe]
-
-s_not_b32 s101, s1
-// CHECK: [0x01,0x04,0xe5,0xbe]
-
-s_not_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x04,0xe6,0xbe]
-
-s_not_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x04,0xe7,0xbe]
-
-s_not_b32 vcc_lo, s1
-// CHECK: [0x01,0x04,0xea,0xbe]
-
-s_not_b32 vcc_hi, s1
-// CHECK: [0x01,0x04,0xeb,0xbe]
-
-s_not_b32 tba_lo, s1
-// CHECK: [0x01,0x04,0xec,0xbe]
-
-s_not_b32 tba_hi, s1
-// CHECK: [0x01,0x04,0xed,0xbe]
-
-s_not_b32 tma_lo, s1
-// CHECK: [0x01,0x04,0xee,0xbe]
-
-s_not_b32 tma_hi, s1
-// CHECK: [0x01,0x04,0xef,0xbe]
-
-s_not_b32 ttmp11, s1
-// CHECK: [0x01,0x04,0xfb,0xbe]
-
-s_not_b32 m0, s1
-// CHECK: [0x01,0x04,0xfc,0xbe]
-
-s_not_b32 exec_lo, s1
-// CHECK: [0x01,0x04,0xfe,0xbe]
-
-s_not_b32 exec_hi, s1
-// CHECK: [0x01,0x04,0xff,0xbe]
-
-s_not_b32 s5, s101
-// CHECK: [0x65,0x04,0x85,0xbe]
-
-s_not_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x04,0x85,0xbe]
-
-s_not_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x04,0x85,0xbe]
-
-s_not_b32 s5, vcc_lo
-// CHECK: [0x6a,0x04,0x85,0xbe]
-
-s_not_b32 s5, vcc_hi
-// CHECK: [0x6b,0x04,0x85,0xbe]
-
-s_not_b32 s5, tba_lo
-// CHECK: [0x6c,0x04,0x85,0xbe]
-
-s_not_b32 s5, tba_hi
-// CHECK: [0x6d,0x04,0x85,0xbe]
-
-s_not_b32 s5, tma_lo
-// CHECK: [0x6e,0x04,0x85,0xbe]
-
-s_not_b32 s5, tma_hi
-// CHECK: [0x6f,0x04,0x85,0xbe]
-
-s_not_b32 s5, ttmp11
-// CHECK: [0x7b,0x04,0x85,0xbe]
-
-s_not_b32 s5, m0
-// CHECK: [0x7c,0x04,0x85,0xbe]
-
-s_not_b32 s5, exec_lo
-// CHECK: [0x7e,0x04,0x85,0xbe]
-
-s_not_b32 s5, exec_hi
-// CHECK: [0x7f,0x04,0x85,0xbe]
-
-s_not_b32 s5, 0
-// CHECK: [0x80,0x04,0x85,0xbe]
-
-s_not_b32 s5, -1
-// CHECK: [0xc1,0x04,0x85,0xbe]
-
-s_not_b32 s5, 0.5
-// CHECK: [0xf0,0x04,0x85,0xbe]
-
-s_not_b32 s5, -4.0
-// CHECK: [0xf7,0x04,0x85,0xbe]
-
-s_not_b32 s5, 0xaf123456
-// CHECK: [0xff,0x04,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_not_b32 s5, 0x3f717273
-// CHECK: [0xff,0x04,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_not_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x05,0x8a,0xbe]
-
-s_not_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x05,0x8c,0xbe]
-
-s_not_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x05,0xe4,0xbe]
-
-s_not_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x05,0xe6,0xbe]
-
-s_not_b64 vcc, s[2:3]
-// CHECK: [0x02,0x05,0xea,0xbe]
-
-s_not_b64 tba, s[2:3]
-// CHECK: [0x02,0x05,0xec,0xbe]
-
-s_not_b64 tma, s[2:3]
-// CHECK: [0x02,0x05,0xee,0xbe]
-
-s_not_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x05,0xfa,0xbe]
-
-s_not_b64 exec, s[2:3]
-// CHECK: [0x02,0x05,0xfe,0xbe]
-
-s_not_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], vcc
-// CHECK: [0x6a,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], tba
-// CHECK: [0x6c,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], tma
-// CHECK: [0x6e,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], exec
-// CHECK: [0x7e,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], 0
-// CHECK: [0x80,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], -1
-// CHECK: [0xc1,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x05,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_not_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x05,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_wqm_b32 s5, s1
-// CHECK: [0x01,0x06,0x85,0xbe]
-
-s_wqm_b32 s101, s1
-// CHECK: [0x01,0x06,0xe5,0xbe]
-
-s_wqm_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x06,0xe6,0xbe]
-
-s_wqm_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x06,0xe7,0xbe]
-
-s_wqm_b32 vcc_lo, s1
-// CHECK: [0x01,0x06,0xea,0xbe]
-
-s_wqm_b32 vcc_hi, s1
-// CHECK: [0x01,0x06,0xeb,0xbe]
-
-s_wqm_b32 tba_lo, s1
-// CHECK: [0x01,0x06,0xec,0xbe]
-
-s_wqm_b32 tba_hi, s1
-// CHECK: [0x01,0x06,0xed,0xbe]
-
-s_wqm_b32 tma_lo, s1
-// CHECK: [0x01,0x06,0xee,0xbe]
-
-s_wqm_b32 tma_hi, s1
-// CHECK: [0x01,0x06,0xef,0xbe]
-
-s_wqm_b32 ttmp11, s1
-// CHECK: [0x01,0x06,0xfb,0xbe]
-
-s_wqm_b32 m0, s1
-// CHECK: [0x01,0x06,0xfc,0xbe]
-
-s_wqm_b32 exec_lo, s1
-// CHECK: [0x01,0x06,0xfe,0xbe]
-
-s_wqm_b32 exec_hi, s1
-// CHECK: [0x01,0x06,0xff,0xbe]
-
-s_wqm_b32 s5, s101
-// CHECK: [0x65,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, vcc_lo
-// CHECK: [0x6a,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, vcc_hi
-// CHECK: [0x6b,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, tba_lo
-// CHECK: [0x6c,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, tba_hi
-// CHECK: [0x6d,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, tma_lo
-// CHECK: [0x6e,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, tma_hi
-// CHECK: [0x6f,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, ttmp11
-// CHECK: [0x7b,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, m0
-// CHECK: [0x7c,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, exec_lo
-// CHECK: [0x7e,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, exec_hi
-// CHECK: [0x7f,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, 0
-// CHECK: [0x80,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, -1
-// CHECK: [0xc1,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, 0.5
-// CHECK: [0xf0,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, -4.0
-// CHECK: [0xf7,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, 0xaf123456
-// CHECK: [0xff,0x06,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_wqm_b32 s5, 0x3f717273
-// CHECK: [0xff,0x06,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_wqm_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x07,0x8c,0xbe]
-
-s_wqm_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x07,0xe4,0xbe]
-
-s_wqm_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x07,0xe6,0xbe]
-
-s_wqm_b64 vcc, s[2:3]
-// CHECK: [0x02,0x07,0xea,0xbe]
-
-s_wqm_b64 tba, s[2:3]
-// CHECK: [0x02,0x07,0xec,0xbe]
-
-s_wqm_b64 tma, s[2:3]
-// CHECK: [0x02,0x07,0xee,0xbe]
-
-s_wqm_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x07,0xfa,0xbe]
-
-s_wqm_b64 exec, s[2:3]
-// CHECK: [0x02,0x07,0xfe,0xbe]
-
-s_wqm_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], vcc
-// CHECK: [0x6a,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], tba
-// CHECK: [0x6c,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], tma
-// CHECK: [0x6e,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], exec
-// CHECK: [0x7e,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], 0
-// CHECK: [0x80,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], -1
-// CHECK: [0xc1,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x07,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_wqm_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x07,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_brev_b32 s5, s1
-// CHECK: [0x01,0x08,0x85,0xbe]
-
-s_brev_b32 s101, s1
-// CHECK: [0x01,0x08,0xe5,0xbe]
-
-s_brev_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x08,0xe6,0xbe]
-
-s_brev_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x08,0xe7,0xbe]
-
-s_brev_b32 vcc_lo, s1
-// CHECK: [0x01,0x08,0xea,0xbe]
-
-s_brev_b32 vcc_hi, s1
-// CHECK: [0x01,0x08,0xeb,0xbe]
-
-s_brev_b32 tba_lo, s1
-// CHECK: [0x01,0x08,0xec,0xbe]
-
-s_brev_b32 tba_hi, s1
-// CHECK: [0x01,0x08,0xed,0xbe]
-
-s_brev_b32 tma_lo, s1
-// CHECK: [0x01,0x08,0xee,0xbe]
-
-s_brev_b32 tma_hi, s1
-// CHECK: [0x01,0x08,0xef,0xbe]
-
-s_brev_b32 ttmp11, s1
-// CHECK: [0x01,0x08,0xfb,0xbe]
-
-s_brev_b32 m0, s1
-// CHECK: [0x01,0x08,0xfc,0xbe]
-
-s_brev_b32 exec_lo, s1
-// CHECK: [0x01,0x08,0xfe,0xbe]
-
-s_brev_b32 exec_hi, s1
-// CHECK: [0x01,0x08,0xff,0xbe]
-
-s_brev_b32 s5, s101
-// CHECK: [0x65,0x08,0x85,0xbe]
-
-s_brev_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x08,0x85,0xbe]
-
-s_brev_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x08,0x85,0xbe]
-
-s_brev_b32 s5, vcc_lo
-// CHECK: [0x6a,0x08,0x85,0xbe]
-
-s_brev_b32 s5, vcc_hi
-// CHECK: [0x6b,0x08,0x85,0xbe]
-
-s_brev_b32 s5, tba_lo
-// CHECK: [0x6c,0x08,0x85,0xbe]
-
-s_brev_b32 s5, tba_hi
-// CHECK: [0x6d,0x08,0x85,0xbe]
-
-s_brev_b32 s5, tma_lo
-// CHECK: [0x6e,0x08,0x85,0xbe]
-
-s_brev_b32 s5, tma_hi
-// CHECK: [0x6f,0x08,0x85,0xbe]
-
-s_brev_b32 s5, ttmp11
-// CHECK: [0x7b,0x08,0x85,0xbe]
-
-s_brev_b32 s5, m0
-// CHECK: [0x7c,0x08,0x85,0xbe]
-
-s_brev_b32 s5, exec_lo
-// CHECK: [0x7e,0x08,0x85,0xbe]
-
-s_brev_b32 s5, exec_hi
-// CHECK: [0x7f,0x08,0x85,0xbe]
-
-s_brev_b32 s5, 0
-// CHECK: [0x80,0x08,0x85,0xbe]
-
-s_brev_b32 s5, -1
-// CHECK: [0xc1,0x08,0x85,0xbe]
-
-s_brev_b32 s5, 0.5
-// CHECK: [0xf0,0x08,0x85,0xbe]
-
-s_brev_b32 s5, -4.0
-// CHECK: [0xf7,0x08,0x85,0xbe]
-
-s_brev_b32 s5, 0xaf123456
-// CHECK: [0xff,0x08,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_brev_b32 s5, 0x3f717273
-// CHECK: [0xff,0x08,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_brev_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x09,0x8a,0xbe]
-
-s_brev_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x09,0x8c,0xbe]
-
-s_brev_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x09,0xe4,0xbe]
-
-s_brev_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x09,0xe6,0xbe]
-
-s_brev_b64 vcc, s[2:3]
-// CHECK: [0x02,0x09,0xea,0xbe]
-
-s_brev_b64 tba, s[2:3]
-// CHECK: [0x02,0x09,0xec,0xbe]
-
-s_brev_b64 tma, s[2:3]
-// CHECK: [0x02,0x09,0xee,0xbe]
-
-s_brev_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x09,0xfa,0xbe]
-
-s_brev_b64 exec, s[2:3]
-// CHECK: [0x02,0x09,0xfe,0xbe]
-
-s_brev_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], vcc
-// CHECK: [0x6a,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], tba
-// CHECK: [0x6c,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], tma
-// CHECK: [0x6e,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], exec
-// CHECK: [0x7e,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], 0
-// CHECK: [0x80,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], -1
-// CHECK: [0xc1,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x09,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_brev_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x09,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt0_i32_b32 s5, s1
-// CHECK: [0x01,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s101, s1
-// CHECK: [0x01,0x0a,0xe5,0xbe]
-
-s_bcnt0_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x0a,0xe6,0xbe]
-
-s_bcnt0_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x0a,0xe7,0xbe]
-
-s_bcnt0_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x0a,0xea,0xbe]
-
-s_bcnt0_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x0a,0xeb,0xbe]
-
-s_bcnt0_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x0a,0xec,0xbe]
-
-s_bcnt0_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x0a,0xed,0xbe]
-
-s_bcnt0_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x0a,0xee,0xbe]
-
-s_bcnt0_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x0a,0xef,0xbe]
-
-s_bcnt0_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x0a,0xfb,0xbe]
-
-s_bcnt0_i32_b32 m0, s1
-// CHECK: [0x01,0x0a,0xfc,0xbe]
-
-s_bcnt0_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x0a,0xfe,0xbe]
-
-s_bcnt0_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x0a,0xff,0xbe]
-
-s_bcnt0_i32_b32 s5, s101
-// CHECK: [0x65,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, m0
-// CHECK: [0x7c,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, 0
-// CHECK: [0x80,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, -1
-// CHECK: [0xc1,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x0a,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt0_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x0a,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt0_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x0b,0xe5,0xbe]
-
-s_bcnt0_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x0b,0xe6,0xbe]
-
-s_bcnt0_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x0b,0xe7,0xbe]
-
-s_bcnt0_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x0b,0xea,0xbe]
-
-s_bcnt0_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x0b,0xeb,0xbe]
-
-s_bcnt0_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x0b,0xec,0xbe]
-
-s_bcnt0_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x0b,0xed,0xbe]
-
-s_bcnt0_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x0b,0xee,0xbe]
-
-s_bcnt0_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x0b,0xef,0xbe]
-
-s_bcnt0_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x0b,0xfb,0xbe]
-
-s_bcnt0_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x0b,0xfc,0xbe]
-
-s_bcnt0_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x0b,0xfe,0xbe]
-
-s_bcnt0_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x0b,0xff,0xbe]
-
-s_bcnt0_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, vcc
-// CHECK: [0x6a,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, tba
-// CHECK: [0x6c,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, tma
-// CHECK: [0x6e,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, exec
-// CHECK: [0x7e,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, 0
-// CHECK: [0x80,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, -1
-// CHECK: [0xc1,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x0b,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt0_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x0b,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt1_i32_b32 s5, s1
-// CHECK: [0x01,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s101, s1
-// CHECK: [0x01,0x0c,0xe5,0xbe]
-
-s_bcnt1_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x0c,0xe6,0xbe]
-
-s_bcnt1_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x0c,0xe7,0xbe]
-
-s_bcnt1_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x0c,0xea,0xbe]
-
-s_bcnt1_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x0c,0xeb,0xbe]
-
-s_bcnt1_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x0c,0xec,0xbe]
-
-s_bcnt1_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x0c,0xed,0xbe]
-
-s_bcnt1_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x0c,0xee,0xbe]
-
-s_bcnt1_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x0c,0xef,0xbe]
-
-s_bcnt1_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x0c,0xfb,0xbe]
-
-s_bcnt1_i32_b32 m0, s1
-// CHECK: [0x01,0x0c,0xfc,0xbe]
-
-s_bcnt1_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x0c,0xfe,0xbe]
-
-s_bcnt1_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x0c,0xff,0xbe]
-
-s_bcnt1_i32_b32 s5, s101
-// CHECK: [0x65,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, m0
-// CHECK: [0x7c,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, 0
-// CHECK: [0x80,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, -1
-// CHECK: [0xc1,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x0c,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt1_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x0c,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt1_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x0d,0xe5,0xbe]
-
-s_bcnt1_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x0d,0xe6,0xbe]
-
-s_bcnt1_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x0d,0xe7,0xbe]
-
-s_bcnt1_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x0d,0xea,0xbe]
-
-s_bcnt1_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x0d,0xeb,0xbe]
-
-s_bcnt1_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x0d,0xec,0xbe]
-
-s_bcnt1_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x0d,0xed,0xbe]
-
-s_bcnt1_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x0d,0xee,0xbe]
-
-s_bcnt1_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x0d,0xef,0xbe]
-
-s_bcnt1_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x0d,0xfb,0xbe]
-
-s_bcnt1_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x0d,0xfc,0xbe]
-
-s_bcnt1_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x0d,0xfe,0xbe]
-
-s_bcnt1_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x0d,0xff,0xbe]
-
-s_bcnt1_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, vcc
-// CHECK: [0x6a,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, tba
-// CHECK: [0x6c,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, tma
-// CHECK: [0x6e,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, exec
-// CHECK: [0x7e,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, 0
-// CHECK: [0x80,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, -1
-// CHECK: [0xc1,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x0d,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt1_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x0d,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff0_i32_b32 s5, s1
-// CHECK: [0x01,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s101, s1
-// CHECK: [0x01,0x0e,0xe5,0xbe]
-
-s_ff0_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x0e,0xe6,0xbe]
-
-s_ff0_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x0e,0xe7,0xbe]
-
-s_ff0_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x0e,0xea,0xbe]
-
-s_ff0_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x0e,0xeb,0xbe]
-
-s_ff0_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x0e,0xec,0xbe]
-
-s_ff0_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x0e,0xed,0xbe]
-
-s_ff0_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x0e,0xee,0xbe]
-
-s_ff0_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x0e,0xef,0xbe]
-
-s_ff0_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x0e,0xfb,0xbe]
-
-s_ff0_i32_b32 m0, s1
-// CHECK: [0x01,0x0e,0xfc,0xbe]
-
-s_ff0_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x0e,0xfe,0xbe]
-
-s_ff0_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x0e,0xff,0xbe]
-
-s_ff0_i32_b32 s5, s101
-// CHECK: [0x65,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, m0
-// CHECK: [0x7c,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, 0
-// CHECK: [0x80,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, -1
-// CHECK: [0xc1,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x0e,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff0_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x0e,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff0_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x0f,0xe5,0xbe]
-
-s_ff0_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x0f,0xe6,0xbe]
-
-s_ff0_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x0f,0xe7,0xbe]
-
-s_ff0_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x0f,0xea,0xbe]
-
-s_ff0_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x0f,0xeb,0xbe]
-
-s_ff0_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x0f,0xec,0xbe]
-
-s_ff0_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x0f,0xed,0xbe]
-
-s_ff0_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x0f,0xee,0xbe]
-
-s_ff0_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x0f,0xef,0xbe]
-
-s_ff0_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x0f,0xfb,0xbe]
-
-s_ff0_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x0f,0xfc,0xbe]
-
-s_ff0_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x0f,0xfe,0xbe]
-
-s_ff0_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x0f,0xff,0xbe]
-
-s_ff0_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, vcc
-// CHECK: [0x6a,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, tba
-// CHECK: [0x6c,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, tma
-// CHECK: [0x6e,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, exec
-// CHECK: [0x7e,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, 0
-// CHECK: [0x80,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, -1
-// CHECK: [0xc1,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x0f,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff0_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x0f,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff1_i32_b32 s5, s1
-// CHECK: [0x01,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s101, s1
-// CHECK: [0x01,0x10,0xe5,0xbe]
-
-s_ff1_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x10,0xe6,0xbe]
-
-s_ff1_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x10,0xe7,0xbe]
-
-s_ff1_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x10,0xea,0xbe]
-
-s_ff1_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x10,0xeb,0xbe]
-
-s_ff1_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x10,0xec,0xbe]
-
-s_ff1_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x10,0xed,0xbe]
-
-s_ff1_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x10,0xee,0xbe]
-
-s_ff1_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x10,0xef,0xbe]
-
-s_ff1_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x10,0xfb,0xbe]
-
-s_ff1_i32_b32 m0, s1
-// CHECK: [0x01,0x10,0xfc,0xbe]
-
-s_ff1_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x10,0xfe,0xbe]
-
-s_ff1_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x10,0xff,0xbe]
-
-s_ff1_i32_b32 s5, s101
-// CHECK: [0x65,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, m0
-// CHECK: [0x7c,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, 0
-// CHECK: [0x80,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, -1
-// CHECK: [0xc1,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x10,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff1_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x10,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff1_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x11,0xe5,0xbe]
-
-s_ff1_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x11,0xe6,0xbe]
-
-s_ff1_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x11,0xe7,0xbe]
-
-s_ff1_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x11,0xea,0xbe]
-
-s_ff1_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x11,0xeb,0xbe]
-
-s_ff1_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x11,0xec,0xbe]
-
-s_ff1_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x11,0xed,0xbe]
-
-s_ff1_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x11,0xee,0xbe]
-
-s_ff1_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x11,0xef,0xbe]
-
-s_ff1_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x11,0xfb,0xbe]
-
-s_ff1_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x11,0xfc,0xbe]
-
-s_ff1_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x11,0xfe,0xbe]
-
-s_ff1_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x11,0xff,0xbe]
-
-s_ff1_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, vcc
-// CHECK: [0x6a,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, tba
-// CHECK: [0x6c,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, tma
-// CHECK: [0x6e,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, exec
-// CHECK: [0x7e,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, 0
-// CHECK: [0x80,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, -1
-// CHECK: [0xc1,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x11,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff1_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x11,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_b32 s5, s1
-// CHECK: [0x01,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s101, s1
-// CHECK: [0x01,0x12,0xe5,0xbe]
-
-s_flbit_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x12,0xe6,0xbe]
-
-s_flbit_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x12,0xe7,0xbe]
-
-s_flbit_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x12,0xea,0xbe]
-
-s_flbit_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x12,0xeb,0xbe]
-
-s_flbit_i32_b32 tba_lo, s1
-// CHECK: [0x01,0x12,0xec,0xbe]
-
-s_flbit_i32_b32 tba_hi, s1
-// CHECK: [0x01,0x12,0xed,0xbe]
-
-s_flbit_i32_b32 tma_lo, s1
-// CHECK: [0x01,0x12,0xee,0xbe]
-
-s_flbit_i32_b32 tma_hi, s1
-// CHECK: [0x01,0x12,0xef,0xbe]
-
-s_flbit_i32_b32 ttmp11, s1
-// CHECK: [0x01,0x12,0xfb,0xbe]
-
-s_flbit_i32_b32 m0, s1
-// CHECK: [0x01,0x12,0xfc,0xbe]
-
-s_flbit_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x12,0xfe,0xbe]
-
-s_flbit_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x12,0xff,0xbe]
-
-s_flbit_i32_b32 s5, s101
-// CHECK: [0x65,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, tba_lo
-// CHECK: [0x6c,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, tba_hi
-// CHECK: [0x6d,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, tma_lo
-// CHECK: [0x6e,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, tma_hi
-// CHECK: [0x6f,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, ttmp11
-// CHECK: [0x7b,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, m0
-// CHECK: [0x7c,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, 0
-// CHECK: [0x80,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, -1
-// CHECK: [0xc1,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x12,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x12,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x13,0xe5,0xbe]
-
-s_flbit_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x13,0xe6,0xbe]
-
-s_flbit_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x13,0xe7,0xbe]
-
-s_flbit_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x13,0xea,0xbe]
-
-s_flbit_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x13,0xeb,0xbe]
-
-s_flbit_i32_b64 tba_lo, s[2:3]
-// CHECK: [0x02,0x13,0xec,0xbe]
-
-s_flbit_i32_b64 tba_hi, s[2:3]
-// CHECK: [0x02,0x13,0xed,0xbe]
-
-s_flbit_i32_b64 tma_lo, s[2:3]
-// CHECK: [0x02,0x13,0xee,0xbe]
-
-s_flbit_i32_b64 tma_hi, s[2:3]
-// CHECK: [0x02,0x13,0xef,0xbe]
-
-s_flbit_i32_b64 ttmp11, s[2:3]
-// CHECK: [0x02,0x13,0xfb,0xbe]
-
-s_flbit_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x13,0xfc,0xbe]
-
-s_flbit_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x13,0xfe,0xbe]
-
-s_flbit_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x13,0xff,0xbe]
-
-s_flbit_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, vcc
-// CHECK: [0x6a,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, tba
-// CHECK: [0x6c,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, tma
-// CHECK: [0x6e,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, exec
-// CHECK: [0x7e,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, 0
-// CHECK: [0x80,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, -1
-// CHECK: [0xc1,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x13,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x13,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32 s5, s1
-// CHECK: [0x01,0x14,0x85,0xbe]
-
-s_flbit_i32 s101, s1
-// CHECK: [0x01,0x14,0xe5,0xbe]
-
-s_flbit_i32 flat_scratch_lo, s1
-// CHECK: [0x01,0x14,0xe6,0xbe]
-
-s_flbit_i32 flat_scratch_hi, s1
-// CHECK: [0x01,0x14,0xe7,0xbe]
-
-s_flbit_i32 vcc_lo, s1
-// CHECK: [0x01,0x14,0xea,0xbe]
-
-s_flbit_i32 vcc_hi, s1
-// CHECK: [0x01,0x14,0xeb,0xbe]
-
-s_flbit_i32 tba_lo, s1
-// CHECK: [0x01,0x14,0xec,0xbe]
-
-s_flbit_i32 tba_hi, s1
-// CHECK: [0x01,0x14,0xed,0xbe]
-
-s_flbit_i32 tma_lo, s1
-// CHECK: [0x01,0x14,0xee,0xbe]
-
-s_flbit_i32 tma_hi, s1
-// CHECK: [0x01,0x14,0xef,0xbe]
-
-s_flbit_i32 ttmp11, s1
-// CHECK: [0x01,0x14,0xfb,0xbe]
-
-s_flbit_i32 m0, s1
-// CHECK: [0x01,0x14,0xfc,0xbe]
-
-s_flbit_i32 exec_lo, s1
-// CHECK: [0x01,0x14,0xfe,0xbe]
-
-s_flbit_i32 exec_hi, s1
-// CHECK: [0x01,0x14,0xff,0xbe]
-
-s_flbit_i32 s5, s101
-// CHECK: [0x65,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, flat_scratch_lo
-// CHECK: [0x66,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, flat_scratch_hi
-// CHECK: [0x67,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, vcc_lo
-// CHECK: [0x6a,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, vcc_hi
-// CHECK: [0x6b,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, tba_lo
-// CHECK: [0x6c,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, tba_hi
-// CHECK: [0x6d,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, tma_lo
-// CHECK: [0x6e,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, tma_hi
-// CHECK: [0x6f,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, ttmp11
-// CHECK: [0x7b,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, m0
-// CHECK: [0x7c,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, exec_lo
-// CHECK: [0x7e,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, exec_hi
-// CHECK: [0x7f,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, 0
-// CHECK: [0x80,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, -1
-// CHECK: [0xc1,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, 0.5
-// CHECK: [0xf0,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, -4.0
-// CHECK: [0xf7,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, 0xaf123456
-// CHECK: [0xff,0x14,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32 s5, 0x3f717273
-// CHECK: [0xff,0x14,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_i64 s5, s[2:3]
-// CHECK: [0x02,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s101, s[2:3]
-// CHECK: [0x02,0x15,0xe5,0xbe]
-
-s_flbit_i32_i64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x15,0xe6,0xbe]
-
-s_flbit_i32_i64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x15,0xe7,0xbe]
-
-s_flbit_i32_i64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x15,0xea,0xbe]
-
-s_flbit_i32_i64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x15,0xeb,0xbe]
-
-s_flbit_i32_i64 tba_lo, s[2:3]
-// CHECK: [0x02,0x15,0xec,0xbe]
-
-s_flbit_i32_i64 tba_hi, s[2:3]
-// CHECK: [0x02,0x15,0xed,0xbe]
-
-s_flbit_i32_i64 tma_lo, s[2:3]
-// CHECK: [0x02,0x15,0xee,0xbe]
-
-s_flbit_i32_i64 tma_hi, s[2:3]
-// CHECK: [0x02,0x15,0xef,0xbe]
-
-s_flbit_i32_i64 ttmp11, s[2:3]
-// CHECK: [0x02,0x15,0xfb,0xbe]
-
-s_flbit_i32_i64 m0, s[2:3]
-// CHECK: [0x02,0x15,0xfc,0xbe]
-
-s_flbit_i32_i64 exec_lo, s[2:3]
-// CHECK: [0x02,0x15,0xfe,0xbe]
-
-s_flbit_i32_i64 exec_hi, s[2:3]
-// CHECK: [0x02,0x15,0xff,0xbe]
-
-s_flbit_i32_i64 s5, s[4:5]
-// CHECK: [0x04,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, s[100:101]
-// CHECK: [0x64,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, flat_scratch
-// CHECK: [0x66,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, vcc
-// CHECK: [0x6a,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, tba
-// CHECK: [0x6c,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, tma
-// CHECK: [0x6e,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, ttmp[10:11]
-// CHECK: [0x7a,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, exec
-// CHECK: [0x7e,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, 0
-// CHECK: [0x80,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, -1
-// CHECK: [0xc1,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, 0.5
-// CHECK: [0xf0,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, -4.0
-// CHECK: [0xf7,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, 0xaf123456
-// CHECK: [0xff,0x15,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_i64 s5, 0x3f717273
-// CHECK: [0xff,0x15,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_sext_i32_i8 s5, s1
-// CHECK: [0x01,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s101, s1
-// CHECK: [0x01,0x16,0xe5,0xbe]
-
-s_sext_i32_i8 flat_scratch_lo, s1
-// CHECK: [0x01,0x16,0xe6,0xbe]
-
-s_sext_i32_i8 flat_scratch_hi, s1
-// CHECK: [0x01,0x16,0xe7,0xbe]
-
-s_sext_i32_i8 vcc_lo, s1
-// CHECK: [0x01,0x16,0xea,0xbe]
-
-s_sext_i32_i8 vcc_hi, s1
-// CHECK: [0x01,0x16,0xeb,0xbe]
-
-s_sext_i32_i8 tba_lo, s1
-// CHECK: [0x01,0x16,0xec,0xbe]
-
-s_sext_i32_i8 tba_hi, s1
-// CHECK: [0x01,0x16,0xed,0xbe]
-
-s_sext_i32_i8 tma_lo, s1
-// CHECK: [0x01,0x16,0xee,0xbe]
-
-s_sext_i32_i8 tma_hi, s1
-// CHECK: [0x01,0x16,0xef,0xbe]
-
-s_sext_i32_i8 ttmp11, s1
-// CHECK: [0x01,0x16,0xfb,0xbe]
-
-s_sext_i32_i8 m0, s1
-// CHECK: [0x01,0x16,0xfc,0xbe]
-
-s_sext_i32_i8 exec_lo, s1
-// CHECK: [0x01,0x16,0xfe,0xbe]
-
-s_sext_i32_i8 exec_hi, s1
-// CHECK: [0x01,0x16,0xff,0xbe]
-
-s_sext_i32_i8 s5, s101
-// CHECK: [0x65,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, flat_scratch_lo
-// CHECK: [0x66,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, flat_scratch_hi
-// CHECK: [0x67,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, vcc_lo
-// CHECK: [0x6a,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, vcc_hi
-// CHECK: [0x6b,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, tba_lo
-// CHECK: [0x6c,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, tba_hi
-// CHECK: [0x6d,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, tma_lo
-// CHECK: [0x6e,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, tma_hi
-// CHECK: [0x6f,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, ttmp11
-// CHECK: [0x7b,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, m0
-// CHECK: [0x7c,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, exec_lo
-// CHECK: [0x7e,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, exec_hi
-// CHECK: [0x7f,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, 0
-// CHECK: [0x80,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, -1
-// CHECK: [0xc1,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, 0.5
-// CHECK: [0xf0,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, -4.0
-// CHECK: [0xf7,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, 0x71
-// CHECK: [0xff,0x16,0x85,0xbe,0x71,0x00,0x00,0x00]
-
-s_sext_i32_i8 s5, 0xf0
-// CHECK: [0xff,0x16,0x85,0xbe,0xf0,0x00,0x00,0x00]
-
-s_sext_i32_i16 s5, s1
-// CHECK: [0x01,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s101, s1
-// CHECK: [0x01,0x17,0xe5,0xbe]
-
-s_sext_i32_i16 flat_scratch_lo, s1
-// CHECK: [0x01,0x17,0xe6,0xbe]
-
-s_sext_i32_i16 flat_scratch_hi, s1
-// CHECK: [0x01,0x17,0xe7,0xbe]
-
-s_sext_i32_i16 vcc_lo, s1
-// CHECK: [0x01,0x17,0xea,0xbe]
-
-s_sext_i32_i16 vcc_hi, s1
-// CHECK: [0x01,0x17,0xeb,0xbe]
-
-s_sext_i32_i16 tba_lo, s1
-// CHECK: [0x01,0x17,0xec,0xbe]
-
-s_sext_i32_i16 tba_hi, s1
-// CHECK: [0x01,0x17,0xed,0xbe]
-
-s_sext_i32_i16 tma_lo, s1
-// CHECK: [0x01,0x17,0xee,0xbe]
-
-s_sext_i32_i16 tma_hi, s1
-// CHECK: [0x01,0x17,0xef,0xbe]
-
-s_sext_i32_i16 ttmp11, s1
-// CHECK: [0x01,0x17,0xfb,0xbe]
-
-s_sext_i32_i16 m0, s1
-// CHECK: [0x01,0x17,0xfc,0xbe]
-
-s_sext_i32_i16 exec_lo, s1
-// CHECK: [0x01,0x17,0xfe,0xbe]
-
-s_sext_i32_i16 exec_hi, s1
-// CHECK: [0x01,0x17,0xff,0xbe]
-
-s_sext_i32_i16 s5, s101
-// CHECK: [0x65,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, flat_scratch_lo
-// CHECK: [0x66,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, flat_scratch_hi
-// CHECK: [0x67,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, vcc_lo
-// CHECK: [0x6a,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, vcc_hi
-// CHECK: [0x6b,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, tba_lo
-// CHECK: [0x6c,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, tba_hi
-// CHECK: [0x6d,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, tma_lo
-// CHECK: [0x6e,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, tma_hi
-// CHECK: [0x6f,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, ttmp11
-// CHECK: [0x7b,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, m0
-// CHECK: [0x7c,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, exec_lo
-// CHECK: [0x7e,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, exec_hi
-// CHECK: [0x7f,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, 0
-// CHECK: [0x80,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, -1
-// CHECK: [0xc1,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, 0.5
-// CHECK: [0xf0,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, -4.0
-// CHECK: [0xf7,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, 0xaf123456
-// CHECK: [0xff,0x17,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_sext_i32_i16 s5, 0x3f717273
-// CHECK: [0xff,0x17,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset0_b32 s5, s1
-// CHECK: [0x01,0x18,0x85,0xbe]
-
-s_bitset0_b32 s101, s1
-// CHECK: [0x01,0x18,0xe5,0xbe]
-
-s_bitset0_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x18,0xe6,0xbe]
-
-s_bitset0_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x18,0xe7,0xbe]
-
-s_bitset0_b32 vcc_lo, s1
-// CHECK: [0x01,0x18,0xea,0xbe]
-
-s_bitset0_b32 vcc_hi, s1
-// CHECK: [0x01,0x18,0xeb,0xbe]
-
-s_bitset0_b32 tba_lo, s1
-// CHECK: [0x01,0x18,0xec,0xbe]
-
-s_bitset0_b32 tba_hi, s1
-// CHECK: [0x01,0x18,0xed,0xbe]
-
-s_bitset0_b32 tma_lo, s1
-// CHECK: [0x01,0x18,0xee,0xbe]
-
-s_bitset0_b32 tma_hi, s1
-// CHECK: [0x01,0x18,0xef,0xbe]
-
-s_bitset0_b32 ttmp11, s1
-// CHECK: [0x01,0x18,0xfb,0xbe]
-
-s_bitset0_b32 m0, s1
-// CHECK: [0x01,0x18,0xfc,0xbe]
-
-s_bitset0_b32 exec_lo, s1
-// CHECK: [0x01,0x18,0xfe,0xbe]
-
-s_bitset0_b32 exec_hi, s1
-// CHECK: [0x01,0x18,0xff,0xbe]
-
-s_bitset0_b32 s5, s101
-// CHECK: [0x65,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, vcc_lo
-// CHECK: [0x6a,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, vcc_hi
-// CHECK: [0x6b,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, tba_lo
-// CHECK: [0x6c,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, tba_hi
-// CHECK: [0x6d,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, tma_lo
-// CHECK: [0x6e,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, tma_hi
-// CHECK: [0x6f,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, ttmp11
-// CHECK: [0x7b,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, m0
-// CHECK: [0x7c,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, exec_lo
-// CHECK: [0x7e,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, exec_hi
-// CHECK: [0x7f,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, 0
-// CHECK: [0x80,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, -1
-// CHECK: [0xc1,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, 0.5
-// CHECK: [0xf0,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, -4.0
-// CHECK: [0xf7,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, 0xaf123456
-// CHECK: [0xff,0x18,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset0_b32 s5, 0x3f717273
-// CHECK: [0xff,0x18,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset0_b64 s[10:11], s1
-// CHECK: [0x01,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[12:13], s1
-// CHECK: [0x01,0x19,0x8c,0xbe]
-
-s_bitset0_b64 s[100:101], s1
-// CHECK: [0x01,0x19,0xe4,0xbe]
-
-s_bitset0_b64 flat_scratch, s1
-// CHECK: [0x01,0x19,0xe6,0xbe]
-
-s_bitset0_b64 vcc, s1
-// CHECK: [0x01,0x19,0xea,0xbe]
-
-s_bitset0_b64 tba, s1
-// CHECK: [0x01,0x19,0xec,0xbe]
-
-s_bitset0_b64 tma, s1
-// CHECK: [0x01,0x19,0xee,0xbe]
-
-s_bitset0_b64 ttmp[10:11], s1
-// CHECK: [0x01,0x19,0xfa,0xbe]
-
-s_bitset0_b64 exec, s1
-// CHECK: [0x01,0x19,0xfe,0xbe]
-
-s_bitset0_b64 s[10:11], s101
-// CHECK: [0x65,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], flat_scratch_lo
-// CHECK: [0x66,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], flat_scratch_hi
-// CHECK: [0x67,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], vcc_lo
-// CHECK: [0x6a,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], vcc_hi
-// CHECK: [0x6b,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], tba_lo
-// CHECK: [0x6c,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], tba_hi
-// CHECK: [0x6d,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], tma_lo
-// CHECK: [0x6e,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], tma_hi
-// CHECK: [0x6f,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], ttmp11
-// CHECK: [0x7b,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], m0
-// CHECK: [0x7c,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], exec_lo
-// CHECK: [0x7e,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], exec_hi
-// CHECK: [0x7f,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], 0
-// CHECK: [0x80,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], -1
-// CHECK: [0xc1,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x19,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset0_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x19,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset1_b32 s5, s1
-// CHECK: [0x01,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s101, s1
-// CHECK: [0x01,0x1a,0xe5,0xbe]
-
-s_bitset1_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x1a,0xe6,0xbe]
-
-s_bitset1_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x1a,0xe7,0xbe]
-
-s_bitset1_b32 vcc_lo, s1
-// CHECK: [0x01,0x1a,0xea,0xbe]
-
-s_bitset1_b32 vcc_hi, s1
-// CHECK: [0x01,0x1a,0xeb,0xbe]
-
-s_bitset1_b32 tba_lo, s1
-// CHECK: [0x01,0x1a,0xec,0xbe]
-
-s_bitset1_b32 tba_hi, s1
-// CHECK: [0x01,0x1a,0xed,0xbe]
-
-s_bitset1_b32 tma_lo, s1
-// CHECK: [0x01,0x1a,0xee,0xbe]
-
-s_bitset1_b32 tma_hi, s1
-// CHECK: [0x01,0x1a,0xef,0xbe]
-
-s_bitset1_b32 ttmp11, s1
-// CHECK: [0x01,0x1a,0xfb,0xbe]
-
-s_bitset1_b32 m0, s1
-// CHECK: [0x01,0x1a,0xfc,0xbe]
-
-s_bitset1_b32 exec_lo, s1
-// CHECK: [0x01,0x1a,0xfe,0xbe]
-
-s_bitset1_b32 exec_hi, s1
-// CHECK: [0x01,0x1a,0xff,0xbe]
-
-s_bitset1_b32 s5, s101
-// CHECK: [0x65,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, vcc_lo
-// CHECK: [0x6a,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, vcc_hi
-// CHECK: [0x6b,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, tba_lo
-// CHECK: [0x6c,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, tba_hi
-// CHECK: [0x6d,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, tma_lo
-// CHECK: [0x6e,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, tma_hi
-// CHECK: [0x6f,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, ttmp11
-// CHECK: [0x7b,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, m0
-// CHECK: [0x7c,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, exec_lo
-// CHECK: [0x7e,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, exec_hi
-// CHECK: [0x7f,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, 0
-// CHECK: [0x80,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, -1
-// CHECK: [0xc1,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, 0.5
-// CHECK: [0xf0,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, -4.0
-// CHECK: [0xf7,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, 0xaf123456
-// CHECK: [0xff,0x1a,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset1_b32 s5, 0x3f717273
-// CHECK: [0xff,0x1a,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset1_b64 s[10:11], s1
-// CHECK: [0x01,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[12:13], s1
-// CHECK: [0x01,0x1b,0x8c,0xbe]
-
-s_bitset1_b64 s[100:101], s1
-// CHECK: [0x01,0x1b,0xe4,0xbe]
-
-s_bitset1_b64 flat_scratch, s1
-// CHECK: [0x01,0x1b,0xe6,0xbe]
-
-s_bitset1_b64 vcc, s1
-// CHECK: [0x01,0x1b,0xea,0xbe]
-
-s_bitset1_b64 tba, s1
-// CHECK: [0x01,0x1b,0xec,0xbe]
-
-s_bitset1_b64 tma, s1
-// CHECK: [0x01,0x1b,0xee,0xbe]
-
-s_bitset1_b64 ttmp[10:11], s1
-// CHECK: [0x01,0x1b,0xfa,0xbe]
-
-s_bitset1_b64 exec, s1
-// CHECK: [0x01,0x1b,0xfe,0xbe]
-
-s_bitset1_b64 s[10:11], s101
-// CHECK: [0x65,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], flat_scratch_lo
-// CHECK: [0x66,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], flat_scratch_hi
-// CHECK: [0x67,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], vcc_lo
-// CHECK: [0x6a,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], vcc_hi
-// CHECK: [0x6b,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], tba_lo
-// CHECK: [0x6c,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], tba_hi
-// CHECK: [0x6d,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], tma_lo
-// CHECK: [0x6e,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], tma_hi
-// CHECK: [0x6f,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], ttmp11
-// CHECK: [0x7b,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], m0
-// CHECK: [0x7c,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], exec_lo
-// CHECK: [0x7e,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], exec_hi
-// CHECK: [0x7f,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], 0
-// CHECK: [0x80,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], -1
-// CHECK: [0xc1,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x1b,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset1_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x1b,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_getpc_b64 s[10:11]
-// CHECK: [0x00,0x1c,0x8a,0xbe]
-
-s_getpc_b64 s[12:13]
-// CHECK: [0x00,0x1c,0x8c,0xbe]
-
-s_getpc_b64 s[100:101]
-// CHECK: [0x00,0x1c,0xe4,0xbe]
-
-s_getpc_b64 flat_scratch
-// CHECK: [0x00,0x1c,0xe6,0xbe]
-
-s_getpc_b64 vcc
-// CHECK: [0x00,0x1c,0xea,0xbe]
-
-s_getpc_b64 tba
-// CHECK: [0x00,0x1c,0xec,0xbe]
-
-s_getpc_b64 tma
-// CHECK: [0x00,0x1c,0xee,0xbe]
-
-s_getpc_b64 ttmp[10:11]
-// CHECK: [0x00,0x1c,0xfa,0xbe]
-
-s_getpc_b64 exec
-// CHECK: [0x00,0x1c,0xfe,0xbe]
-
-s_setpc_b64 s[2:3]
-// CHECK: [0x02,0x1d,0x80,0xbe]
-
-s_setpc_b64 s[4:5]
-// CHECK: [0x04,0x1d,0x80,0xbe]
-
-s_setpc_b64 s[100:101]
-// CHECK: [0x64,0x1d,0x80,0xbe]
-
-s_setpc_b64 flat_scratch
-// CHECK: [0x66,0x1d,0x80,0xbe]
-
-s_setpc_b64 vcc
-// CHECK: [0x6a,0x1d,0x80,0xbe]
-
-s_setpc_b64 tba
-// CHECK: [0x6c,0x1d,0x80,0xbe]
-
-s_setpc_b64 tma
-// CHECK: [0x6e,0x1d,0x80,0xbe]
-
-s_setpc_b64 ttmp[10:11]
-// CHECK: [0x7a,0x1d,0x80,0xbe]
-
-s_swappc_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x1e,0x8c,0xbe]
-
-s_swappc_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x1e,0xe4,0xbe]
-
-s_swappc_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x1e,0xe6,0xbe]
-
-s_swappc_b64 vcc, s[2:3]
-// CHECK: [0x02,0x1e,0xea,0xbe]
-
-s_swappc_b64 tba, s[2:3]
-// CHECK: [0x02,0x1e,0xec,0xbe]
-
-s_swappc_b64 tma, s[2:3]
-// CHECK: [0x02,0x1e,0xee,0xbe]
-
-s_swappc_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x1e,0xfa,0xbe]
-
-s_swappc_b64 exec, s[2:3]
-// CHECK: [0x02,0x1e,0xfe,0xbe]
-
-s_swappc_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], vcc
-// CHECK: [0x6a,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], tba
-// CHECK: [0x6c,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], tma
-// CHECK: [0x6e,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x1e,0x8a,0xbe]
-
-s_rfe_b64 s[2:3]
-// CHECK: [0x02,0x1f,0x80,0xbe]
-
-s_rfe_b64 s[4:5]
-// CHECK: [0x04,0x1f,0x80,0xbe]
-
-s_rfe_b64 s[100:101]
-// CHECK: [0x64,0x1f,0x80,0xbe]
-
-s_rfe_b64 flat_scratch
-// CHECK: [0x66,0x1f,0x80,0xbe]
-
-s_rfe_b64 vcc
-// CHECK: [0x6a,0x1f,0x80,0xbe]
-
-s_rfe_b64 tba
-// CHECK: [0x6c,0x1f,0x80,0xbe]
-
-s_rfe_b64 tma
-// CHECK: [0x6e,0x1f,0x80,0xbe]
-
-s_rfe_b64 ttmp[10:11]
-// CHECK: [0x7a,0x1f,0x80,0xbe]
-
-s_and_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x20,0x8c,0xbe]
-
-s_and_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x20,0xe4,0xbe]
-
-s_and_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x20,0xe6,0xbe]
-
-s_and_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x20,0xea,0xbe]
-
-s_and_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x20,0xec,0xbe]
-
-s_and_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x20,0xee,0xbe]
-
-s_and_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x20,0xfa,0xbe]
-
-s_and_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x20,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_and_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x20,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_or_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x21,0x8c,0xbe]
-
-s_or_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x21,0xe4,0xbe]
-
-s_or_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x21,0xe6,0xbe]
-
-s_or_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x21,0xea,0xbe]
-
-s_or_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x21,0xec,0xbe]
-
-s_or_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x21,0xee,0xbe]
-
-s_or_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x21,0xfa,0xbe]
-
-s_or_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x21,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_or_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x21,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xor_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x22,0x8c,0xbe]
-
-s_xor_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x22,0xe4,0xbe]
-
-s_xor_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x22,0xe6,0xbe]
-
-s_xor_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x22,0xea,0xbe]
-
-s_xor_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x22,0xec,0xbe]
-
-s_xor_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x22,0xee,0xbe]
-
-s_xor_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x22,0xfa,0xbe]
-
-s_xor_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x22,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xor_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x22,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn2_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x23,0x8c,0xbe]
-
-s_andn2_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x23,0xe4,0xbe]
-
-s_andn2_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x23,0xe6,0xbe]
-
-s_andn2_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x23,0xea,0xbe]
-
-s_andn2_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x23,0xec,0xbe]
-
-s_andn2_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x23,0xee,0xbe]
-
-s_andn2_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x23,0xfa,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x23,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn2_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x23,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_orn2_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x24,0x8c,0xbe]
-
-s_orn2_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x24,0xe4,0xbe]
-
-s_orn2_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x24,0xe6,0xbe]
-
-s_orn2_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x24,0xea,0xbe]
-
-s_orn2_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x24,0xec,0xbe]
-
-s_orn2_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x24,0xee,0xbe]
-
-s_orn2_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x24,0xfa,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x24,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_orn2_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x24,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nand_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x25,0x8c,0xbe]
-
-s_nand_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x25,0xe4,0xbe]
-
-s_nand_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x25,0xe6,0xbe]
-
-s_nand_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x25,0xea,0xbe]
-
-s_nand_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x25,0xec,0xbe]
-
-s_nand_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x25,0xee,0xbe]
-
-s_nand_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x25,0xfa,0xbe]
-
-s_nand_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x25,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nand_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x25,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nor_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x26,0x8c,0xbe]
-
-s_nor_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x26,0xe4,0xbe]
-
-s_nor_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x26,0xe6,0xbe]
-
-s_nor_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x26,0xea,0xbe]
-
-s_nor_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x26,0xec,0xbe]
-
-s_nor_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x26,0xee,0xbe]
-
-s_nor_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x26,0xfa,0xbe]
-
-s_nor_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x26,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nor_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x26,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xnor_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x27,0x8c,0xbe]
-
-s_xnor_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x27,0xe4,0xbe]
-
-s_xnor_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x27,0xe6,0xbe]
-
-s_xnor_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x27,0xea,0xbe]
-
-s_xnor_saveexec_b64 tba, s[2:3]
-// CHECK: [0x02,0x27,0xec,0xbe]
-
-s_xnor_saveexec_b64 tma, s[2:3]
-// CHECK: [0x02,0x27,0xee,0xbe]
-
-s_xnor_saveexec_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x27,0xfa,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], tba
-// CHECK: [0x6c,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], tma
-// CHECK: [0x6e,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x27,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xnor_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x27,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_quadmask_b32 s5, s1
-// CHECK: [0x01,0x28,0x85,0xbe]
-
-s_quadmask_b32 s101, s1
-// CHECK: [0x01,0x28,0xe5,0xbe]
-
-s_quadmask_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x28,0xe6,0xbe]
-
-s_quadmask_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x28,0xe7,0xbe]
-
-s_quadmask_b32 vcc_lo, s1
-// CHECK: [0x01,0x28,0xea,0xbe]
-
-s_quadmask_b32 vcc_hi, s1
-// CHECK: [0x01,0x28,0xeb,0xbe]
-
-s_quadmask_b32 tba_lo, s1
-// CHECK: [0x01,0x28,0xec,0xbe]
-
-s_quadmask_b32 tba_hi, s1
-// CHECK: [0x01,0x28,0xed,0xbe]
-
-s_quadmask_b32 tma_lo, s1
-// CHECK: [0x01,0x28,0xee,0xbe]
-
-s_quadmask_b32 tma_hi, s1
-// CHECK: [0x01,0x28,0xef,0xbe]
-
-s_quadmask_b32 ttmp11, s1
-// CHECK: [0x01,0x28,0xfb,0xbe]
-
-s_quadmask_b32 m0, s1
-// CHECK: [0x01,0x28,0xfc,0xbe]
-
-s_quadmask_b32 exec_lo, s1
-// CHECK: [0x01,0x28,0xfe,0xbe]
-
-s_quadmask_b32 exec_hi, s1
-// CHECK: [0x01,0x28,0xff,0xbe]
-
-s_quadmask_b32 s5, s101
-// CHECK: [0x65,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, vcc_lo
-// CHECK: [0x6a,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, vcc_hi
-// CHECK: [0x6b,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, tba_lo
-// CHECK: [0x6c,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, tba_hi
-// CHECK: [0x6d,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, tma_lo
-// CHECK: [0x6e,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, tma_hi
-// CHECK: [0x6f,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, ttmp11
-// CHECK: [0x7b,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, m0
-// CHECK: [0x7c,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, exec_lo
-// CHECK: [0x7e,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, exec_hi
-// CHECK: [0x7f,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, 0
-// CHECK: [0x80,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, -1
-// CHECK: [0xc1,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, 0.5
-// CHECK: [0xf0,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, -4.0
-// CHECK: [0xf7,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, 0xaf123456
-// CHECK: [0xff,0x28,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_quadmask_b32 s5, 0x3f717273
-// CHECK: [0xff,0x28,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_quadmask_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x29,0x8c,0xbe]
-
-s_quadmask_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x29,0xe4,0xbe]
-
-s_quadmask_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x29,0xe6,0xbe]
-
-s_quadmask_b64 vcc, s[2:3]
-// CHECK: [0x02,0x29,0xea,0xbe]
-
-s_quadmask_b64 tba, s[2:3]
-// CHECK: [0x02,0x29,0xec,0xbe]
-
-s_quadmask_b64 tma, s[2:3]
-// CHECK: [0x02,0x29,0xee,0xbe]
-
-s_quadmask_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x29,0xfa,0xbe]
-
-s_quadmask_b64 exec, s[2:3]
-// CHECK: [0x02,0x29,0xfe,0xbe]
-
-s_quadmask_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], vcc
-// CHECK: [0x6a,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], tba
-// CHECK: [0x6c,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], tma
-// CHECK: [0x6e,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], exec
-// CHECK: [0x7e,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], 0
-// CHECK: [0x80,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], -1
-// CHECK: [0xc1,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x29,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_quadmask_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x29,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_movrels_b32 s5, s1
-// CHECK: [0x01,0x2a,0x85,0xbe]
-
-s_movrels_b32 s101, s1
-// CHECK: [0x01,0x2a,0xe5,0xbe]
-
-s_movrels_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x2a,0xe6,0xbe]
-
-s_movrels_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x2a,0xe7,0xbe]
-
-s_movrels_b32 vcc_lo, s1
-// CHECK: [0x01,0x2a,0xea,0xbe]
-
-s_movrels_b32 vcc_hi, s1
-// CHECK: [0x01,0x2a,0xeb,0xbe]
-
-s_movrels_b32 tba_lo, s1
-// CHECK: [0x01,0x2a,0xec,0xbe]
-
-s_movrels_b32 tba_hi, s1
-// CHECK: [0x01,0x2a,0xed,0xbe]
-
-s_movrels_b32 tma_lo, s1
-// CHECK: [0x01,0x2a,0xee,0xbe]
-
-s_movrels_b32 tma_hi, s1
-// CHECK: [0x01,0x2a,0xef,0xbe]
-
-s_movrels_b32 ttmp11, s1
-// CHECK: [0x01,0x2a,0xfb,0xbe]
-
-s_movrels_b32 m0, s1
-// CHECK: [0x01,0x2a,0xfc,0xbe]
-
-s_movrels_b32 exec_lo, s1
-// CHECK: [0x01,0x2a,0xfe,0xbe]
-
-s_movrels_b32 exec_hi, s1
-// CHECK: [0x01,0x2a,0xff,0xbe]
-
-s_movrels_b32 s5, s101
-// CHECK: [0x65,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, vcc_lo
-// CHECK: [0x6a,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, vcc_hi
-// CHECK: [0x6b,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, tba_lo
-// CHECK: [0x6c,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, tba_hi
-// CHECK: [0x6d,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, tma_lo
-// CHECK: [0x6e,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, tma_hi
-// CHECK: [0x6f,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, ttmp11
-// CHECK: [0x7b,0x2a,0x85,0xbe]
-
-s_movrels_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x2b,0x8c,0xbe]
-
-s_movrels_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x2b,0xe4,0xbe]
-
-s_movrels_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x2b,0xe6,0xbe]
-
-s_movrels_b64 vcc, s[2:3]
-// CHECK: [0x02,0x2b,0xea,0xbe]
-
-s_movrels_b64 tba, s[2:3]
-// CHECK: [0x02,0x2b,0xec,0xbe]
-
-s_movrels_b64 tma, s[2:3]
-// CHECK: [0x02,0x2b,0xee,0xbe]
-
-s_movrels_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x2b,0xfa,0xbe]
-
-s_movrels_b64 exec, s[2:3]
-// CHECK: [0x02,0x2b,0xfe,0xbe]
-
-s_movrels_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], vcc
-// CHECK: [0x6a,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], tba
-// CHECK: [0x6c,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], tma
-// CHECK: [0x6e,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x2b,0x8a,0xbe]
-
-s_movreld_b32 s5, s1
-// CHECK: [0x01,0x2c,0x85,0xbe]
-
-s_movreld_b32 s101, s1
-// CHECK: [0x01,0x2c,0xe5,0xbe]
-
-s_movreld_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x2c,0xe6,0xbe]
-
-s_movreld_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x2c,0xe7,0xbe]
-
-s_movreld_b32 vcc_lo, s1
-// CHECK: [0x01,0x2c,0xea,0xbe]
-
-s_movreld_b32 vcc_hi, s1
-// CHECK: [0x01,0x2c,0xeb,0xbe]
-
-s_movreld_b32 tba_lo, s1
-// CHECK: [0x01,0x2c,0xec,0xbe]
-
-s_movreld_b32 tba_hi, s1
-// CHECK: [0x01,0x2c,0xed,0xbe]
-
-s_movreld_b32 tma_lo, s1
-// CHECK: [0x01,0x2c,0xee,0xbe]
-
-s_movreld_b32 tma_hi, s1
-// CHECK: [0x01,0x2c,0xef,0xbe]
-
-s_movreld_b32 ttmp11, s1
-// CHECK: [0x01,0x2c,0xfb,0xbe]
-
-s_movreld_b32 s5, s101
-// CHECK: [0x65,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, vcc_lo
-// CHECK: [0x6a,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, vcc_hi
-// CHECK: [0x6b,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, tba_lo
-// CHECK: [0x6c,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, tba_hi
-// CHECK: [0x6d,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, tma_lo
-// CHECK: [0x6e,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, tma_hi
-// CHECK: [0x6f,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, ttmp11
-// CHECK: [0x7b,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, m0
-// CHECK: [0x7c,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, 0
-// CHECK: [0x80,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, -1
-// CHECK: [0xc1,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, 0.5
-// CHECK: [0xf0,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, -4.0
-// CHECK: [0xf7,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, 0xaf123456
-// CHECK: [0xff,0x2c,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_movreld_b32 s5, 0x3f717273
-// CHECK: [0xff,0x2c,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_movreld_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x2d,0x8c,0xbe]
-
-s_movreld_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x2d,0xe4,0xbe]
-
-s_movreld_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x2d,0xe6,0xbe]
-
-s_movreld_b64 vcc, s[2:3]
-// CHECK: [0x02,0x2d,0xea,0xbe]
-
-s_movreld_b64 tba, s[2:3]
-// CHECK: [0x02,0x2d,0xec,0xbe]
-
-s_movreld_b64 tma, s[2:3]
-// CHECK: [0x02,0x2d,0xee,0xbe]
-
-s_movreld_b64 ttmp[10:11], s[2:3]
-// CHECK: [0x02,0x2d,0xfa,0xbe]
-
-s_movreld_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], vcc
-// CHECK: [0x6a,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], tba
-// CHECK: [0x6c,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], tma
-// CHECK: [0x6e,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], ttmp[10:11]
-// CHECK: [0x7a,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], 0
-// CHECK: [0x80,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], -1
-// CHECK: [0xc1,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x2d,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_movreld_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x2d,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cbranch_join s1
-// CHECK: [0x01,0x2e,0x80,0xbe]
-
-s_cbranch_join s101
-// CHECK: [0x65,0x2e,0x80,0xbe]
-
-s_cbranch_join flat_scratch_lo
-// CHECK: [0x66,0x2e,0x80,0xbe]
-
-s_cbranch_join flat_scratch_hi
-// CHECK: [0x67,0x2e,0x80,0xbe]
-
-s_cbranch_join vcc_lo
-// CHECK: [0x6a,0x2e,0x80,0xbe]
-
-s_cbranch_join vcc_hi
-// CHECK: [0x6b,0x2e,0x80,0xbe]
-
-s_cbranch_join tba_lo
-// CHECK: [0x6c,0x2e,0x80,0xbe]
-
-s_cbranch_join tba_hi
-// CHECK: [0x6d,0x2e,0x80,0xbe]
-
-s_cbranch_join tma_lo
-// CHECK: [0x6e,0x2e,0x80,0xbe]
-
-s_cbranch_join tma_hi
-// CHECK: [0x6f,0x2e,0x80,0xbe]
-
-s_cbranch_join ttmp11
-// CHECK: [0x7b,0x2e,0x80,0xbe]
-
-s_abs_i32 s5, s1
-// CHECK: [0x01,0x30,0x85,0xbe]
-
-s_abs_i32 s101, s1
-// CHECK: [0x01,0x30,0xe5,0xbe]
-
-s_abs_i32 flat_scratch_lo, s1
-// CHECK: [0x01,0x30,0xe6,0xbe]
-
-s_abs_i32 flat_scratch_hi, s1
-// CHECK: [0x01,0x30,0xe7,0xbe]
-
-s_abs_i32 vcc_lo, s1
-// CHECK: [0x01,0x30,0xea,0xbe]
-
-s_abs_i32 vcc_hi, s1
-// CHECK: [0x01,0x30,0xeb,0xbe]
-
-s_abs_i32 tba_lo, s1
-// CHECK: [0x01,0x30,0xec,0xbe]
-
-s_abs_i32 tba_hi, s1
-// CHECK: [0x01,0x30,0xed,0xbe]
-
-s_abs_i32 tma_lo, s1
-// CHECK: [0x01,0x30,0xee,0xbe]
-
-s_abs_i32 tma_hi, s1
-// CHECK: [0x01,0x30,0xef,0xbe]
-
-s_abs_i32 ttmp11, s1
-// CHECK: [0x01,0x30,0xfb,0xbe]
-
-s_abs_i32 m0, s1
-// CHECK: [0x01,0x30,0xfc,0xbe]
-
-s_abs_i32 exec_lo, s1
-// CHECK: [0x01,0x30,0xfe,0xbe]
-
-s_abs_i32 exec_hi, s1
-// CHECK: [0x01,0x30,0xff,0xbe]
-
-s_abs_i32 s5, s101
-// CHECK: [0x65,0x30,0x85,0xbe]
-
-s_abs_i32 s5, flat_scratch_lo
-// CHECK: [0x66,0x30,0x85,0xbe]
-
-s_abs_i32 s5, flat_scratch_hi
-// CHECK: [0x67,0x30,0x85,0xbe]
-
-s_abs_i32 s5, vcc_lo
-// CHECK: [0x6a,0x30,0x85,0xbe]
-
-s_abs_i32 s5, vcc_hi
-// CHECK: [0x6b,0x30,0x85,0xbe]
-
-s_abs_i32 s5, tba_lo
-// CHECK: [0x6c,0x30,0x85,0xbe]
-
-s_abs_i32 s5, tba_hi
-// CHECK: [0x6d,0x30,0x85,0xbe]
-
-s_abs_i32 s5, tma_lo
-// CHECK: [0x6e,0x30,0x85,0xbe]
-
-s_abs_i32 s5, tma_hi
-// CHECK: [0x6f,0x30,0x85,0xbe]
-
-s_abs_i32 s5, ttmp11
-// CHECK: [0x7b,0x30,0x85,0xbe]
-
-s_abs_i32 s5, m0
-// CHECK: [0x7c,0x30,0x85,0xbe]
-
-s_abs_i32 s5, exec_lo
-// CHECK: [0x7e,0x30,0x85,0xbe]
-
-s_abs_i32 s5, exec_hi
-// CHECK: [0x7f,0x30,0x85,0xbe]
-
-s_abs_i32 s5, 0
-// CHECK: [0x80,0x30,0x85,0xbe]
-
-s_abs_i32 s5, -1
-// CHECK: [0xc1,0x30,0x85,0xbe]
-
-s_abs_i32 s5, 0.5
-// CHECK: [0xf0,0x30,0x85,0xbe]
-
-s_abs_i32 s5, -4.0
-// CHECK: [0xf7,0x30,0x85,0xbe]
-
-s_abs_i32 s5, 0xaf123456
-// CHECK: [0xff,0x30,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_abs_i32 s5, 0x3f717273
-// CHECK: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_set_gpr_idx_idx s1
-// CHECK: [0x01,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx s101
-// CHECK: [0x65,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx flat_scratch_lo
-// CHECK: [0x66,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx flat_scratch_hi
-// CHECK: [0x67,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx vcc_lo
-// CHECK: [0x6a,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx vcc_hi
-// CHECK: [0x6b,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx tba_lo
-// CHECK: [0x6c,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx tba_hi
-// CHECK: [0x6d,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx tma_lo
-// CHECK: [0x6e,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx tma_hi
-// CHECK: [0x6f,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx ttmp11
-// CHECK: [0x7b,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx m0
-// CHECK: [0x7c,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx 0
-// CHECK: [0x80,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx -1
-// CHECK: [0xc1,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx 0.5
-// CHECK: [0xf0,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx -4.0
-// CHECK: [0xf7,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx 0xaf123456
-// CHECK: [0xff,0x32,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_set_gpr_idx_idx 0x3f717273
-// CHECK: [0xff,0x32,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_add_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x80]
-
-s_add_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x80]
-
-s_add_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x80]
-
-s_add_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x80]
-
-s_add_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x80]
-
-s_add_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x80]
-
-s_add_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x80]
-
-s_add_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x80]
-
-s_add_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x80]
-
-s_add_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x80]
-
-s_add_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x80]
-
-s_add_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x80]
-
-s_add_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x80]
-
-s_add_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x80]
-
-s_add_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x80]
-
-s_add_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x80]
-
-s_add_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x80]
-
-s_add_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x80]
-
-s_add_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x80]
-
-s_add_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x80]
-
-s_add_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x80]
-
-s_add_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x80]
-
-s_add_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x80]
-
-s_add_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x80]
-
-s_add_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x80]
-
-s_add_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x80]
-
-s_add_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x80]
-
-s_add_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x80]
-
-s_add_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x80]
-
-s_add_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x80]
-
-s_add_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x80]
-
-s_add_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x80,0x56,0x34,0x12,0xaf]
-
-s_add_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x80,0x73,0x72,0x71,0x3f]
-
-s_add_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x80]
-
-s_add_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x80]
-
-s_add_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x80]
-
-s_add_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x80]
-
-s_add_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x80]
-
-s_add_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x80]
-
-s_add_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x80]
-
-s_add_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x80]
-
-s_add_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x80]
-
-s_add_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x80]
-
-s_add_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x80]
-
-s_add_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x80]
-
-s_add_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x80]
-
-s_add_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x80]
-
-s_add_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x80]
-
-s_add_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x80]
-
-s_add_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x80]
-
-s_add_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x80,0x56,0x34,0x12,0xaf]
-
-s_add_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x80,0x73,0x72,0x71,0x3f]
-
-s_sub_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x80]
-
-s_sub_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x80]
-
-s_sub_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x80]
-
-s_sub_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x80]
-
-s_sub_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x80]
-
-s_sub_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x80]
-
-s_sub_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x80]
-
-s_sub_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x80]
-
-s_sub_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x80]
-
-s_sub_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x80]
-
-s_sub_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x80]
-
-s_sub_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x80]
-
-s_sub_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x80]
-
-s_sub_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x80]
-
-s_sub_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x80]
-
-s_sub_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x80]
-
-s_sub_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x80]
-
-s_sub_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x80]
-
-s_sub_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x80]
-
-s_sub_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x80]
-
-s_sub_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x80]
-
-s_sub_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x80]
-
-s_sub_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x80]
-
-s_sub_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x80]
-
-s_sub_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x80]
-
-s_sub_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x80]
-
-s_sub_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x80]
-
-s_sub_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x80]
-
-s_sub_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x80]
-
-s_sub_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x80]
-
-s_sub_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x80]
-
-s_sub_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x80,0x56,0x34,0x12,0xaf]
-
-s_sub_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x80,0x73,0x72,0x71,0x3f]
-
-s_sub_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x80]
-
-s_sub_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x80]
-
-s_sub_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x80]
-
-s_sub_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x80]
-
-s_sub_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x80]
-
-s_sub_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x80]
-
-s_sub_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x80]
-
-s_sub_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x80]
-
-s_sub_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x80]
-
-s_sub_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x80]
-
-s_sub_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x80]
-
-s_sub_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x80]
-
-s_sub_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x80]
-
-s_sub_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x80]
-
-s_sub_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x80]
-
-s_sub_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x80]
-
-s_sub_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x80]
-
-s_sub_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x80,0x56,0x34,0x12,0xaf]
-
-s_sub_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x80,0x73,0x72,0x71,0x3f]
-
-s_add_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x81]
-
-s_add_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x81]
-
-s_add_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x81]
-
-s_add_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x81]
-
-s_add_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x81]
-
-s_add_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x81]
-
-s_add_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x81]
-
-s_add_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x81]
-
-s_add_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x81]
-
-s_add_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x81]
-
-s_add_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x81]
-
-s_add_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x81]
-
-s_add_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x81]
-
-s_add_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x81]
-
-s_add_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x81]
-
-s_add_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x81]
-
-s_add_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x81]
-
-s_add_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x81]
-
-s_add_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x81]
-
-s_add_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x81]
-
-s_add_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x81]
-
-s_add_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x81]
-
-s_add_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x81]
-
-s_add_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x81]
-
-s_add_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x81]
-
-s_add_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x81]
-
-s_add_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x81]
-
-s_add_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x81]
-
-s_add_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x81]
-
-s_add_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x81]
-
-s_add_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x81]
-
-s_add_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x81,0x56,0x34,0x12,0xaf]
-
-s_add_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x81,0x73,0x72,0x71,0x3f]
-
-s_add_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x81]
-
-s_add_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x81]
-
-s_add_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x81]
-
-s_add_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x81]
-
-s_add_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x81]
-
-s_add_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x81]
-
-s_add_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x81]
-
-s_add_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x81]
-
-s_add_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x81]
-
-s_add_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x81]
-
-s_add_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x81]
-
-s_add_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x81]
-
-s_add_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x81]
-
-s_add_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x81]
-
-s_add_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x81]
-
-s_add_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x81]
-
-s_add_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x81]
-
-s_add_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x81,0x56,0x34,0x12,0xaf]
-
-s_add_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x81,0x73,0x72,0x71,0x3f]
-
-s_sub_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x81]
-
-s_sub_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x81]
-
-s_sub_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x81]
-
-s_sub_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x81]
-
-s_sub_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x81]
-
-s_sub_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x81]
-
-s_sub_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x81]
-
-s_sub_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x81]
-
-s_sub_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x81]
-
-s_sub_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x81]
-
-s_sub_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x81]
-
-s_sub_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x81]
-
-s_sub_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x81]
-
-s_sub_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x81]
-
-s_sub_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x81]
-
-s_sub_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x81]
-
-s_sub_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x81]
-
-s_sub_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x81]
-
-s_sub_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x81]
-
-s_sub_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x81]
-
-s_sub_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x81]
-
-s_sub_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x81]
-
-s_sub_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x81]
-
-s_sub_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x81]
-
-s_sub_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x81]
-
-s_sub_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x81]
-
-s_sub_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x81]
-
-s_sub_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x81]
-
-s_sub_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x81]
-
-s_sub_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x81]
-
-s_sub_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x81]
-
-s_sub_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x81,0x56,0x34,0x12,0xaf]
-
-s_sub_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x81,0x73,0x72,0x71,0x3f]
-
-s_sub_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x81]
-
-s_sub_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x81]
-
-s_sub_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x81]
-
-s_sub_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x81]
-
-s_sub_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x81]
-
-s_sub_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x81]
-
-s_sub_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x81]
-
-s_sub_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x81]
-
-s_sub_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x81]
-
-s_sub_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x81]
-
-s_sub_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x81]
-
-s_sub_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x81]
-
-s_sub_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x81]
-
-s_sub_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x81]
-
-s_sub_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x81]
-
-s_sub_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x81]
-
-s_sub_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x81]
-
-s_sub_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x81,0x56,0x34,0x12,0xaf]
-
-s_sub_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x81,0x73,0x72,0x71,0x3f]
-
-s_addc_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x82]
-
-s_addc_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x82]
-
-s_addc_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x82]
-
-s_addc_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x82]
-
-s_addc_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x82]
-
-s_addc_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x82]
-
-s_addc_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x82]
-
-s_addc_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x82]
-
-s_addc_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x82]
-
-s_addc_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x82]
-
-s_addc_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x82]
-
-s_addc_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x82]
-
-s_addc_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x82]
-
-s_addc_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x82]
-
-s_addc_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x82]
-
-s_addc_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x82]
-
-s_addc_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x82]
-
-s_addc_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x82]
-
-s_addc_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x82]
-
-s_addc_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x82]
-
-s_addc_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x82]
-
-s_addc_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x82]
-
-s_addc_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x82]
-
-s_addc_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x82]
-
-s_addc_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x82]
-
-s_addc_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x82]
-
-s_addc_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x82]
-
-s_addc_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x82]
-
-s_addc_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x82]
-
-s_addc_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x82]
-
-s_addc_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x82]
-
-s_addc_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x82,0x56,0x34,0x12,0xaf]
-
-s_addc_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x82,0x73,0x72,0x71,0x3f]
-
-s_addc_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x82]
-
-s_addc_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x82]
-
-s_addc_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x82]
-
-s_addc_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x82]
-
-s_addc_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x82]
-
-s_addc_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x82]
-
-s_addc_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x82]
-
-s_addc_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x82]
-
-s_addc_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x82]
-
-s_addc_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x82]
-
-s_addc_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x82]
-
-s_addc_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x82]
-
-s_addc_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x82]
-
-s_addc_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x82]
-
-s_addc_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x82]
-
-s_addc_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x82]
-
-s_addc_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x82]
-
-s_addc_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x82,0x56,0x34,0x12,0xaf]
-
-s_addc_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x82,0x73,0x72,0x71,0x3f]
-
-s_subb_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x82]
-
-s_subb_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x82]
-
-s_subb_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x82]
-
-s_subb_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x82]
-
-s_subb_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x82]
-
-s_subb_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x82]
-
-s_subb_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x82]
-
-s_subb_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x82]
-
-s_subb_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x82]
-
-s_subb_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x82]
-
-s_subb_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x82]
-
-s_subb_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x82]
-
-s_subb_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x82]
-
-s_subb_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x82]
-
-s_subb_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x82]
-
-s_subb_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x82]
-
-s_subb_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x82]
-
-s_subb_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x82]
-
-s_subb_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x82]
-
-s_subb_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x82]
-
-s_subb_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x82]
-
-s_subb_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x82]
-
-s_subb_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x82]
-
-s_subb_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x82]
-
-s_subb_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x82]
-
-s_subb_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x82]
-
-s_subb_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x82]
-
-s_subb_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x82]
-
-s_subb_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x82]
-
-s_subb_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x82]
-
-s_subb_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x82]
-
-s_subb_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x82,0x56,0x34,0x12,0xaf]
-
-s_subb_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x82,0x73,0x72,0x71,0x3f]
-
-s_subb_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x82]
-
-s_subb_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x82]
-
-s_subb_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x82]
-
-s_subb_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x82]
-
-s_subb_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x82]
-
-s_subb_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x82]
-
-s_subb_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x82]
-
-s_subb_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x82]
-
-s_subb_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x82]
-
-s_subb_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x82]
-
-s_subb_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x82]
-
-s_subb_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x82]
-
-s_subb_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x82]
-
-s_subb_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x82]
-
-s_subb_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x82]
-
-s_subb_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x82]
-
-s_subb_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x82]
-
-s_subb_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x82,0x56,0x34,0x12,0xaf]
-
-s_subb_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x82,0x73,0x72,0x71,0x3f]
-
-s_min_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x83]
-
-s_min_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x83]
-
-s_min_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x83]
-
-s_min_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x83]
-
-s_min_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x83]
-
-s_min_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x83]
-
-s_min_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x83]
-
-s_min_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x83]
-
-s_min_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x83]
-
-s_min_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x83]
-
-s_min_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x83]
-
-s_min_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x83]
-
-s_min_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x83]
-
-s_min_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x83]
-
-s_min_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x83]
-
-s_min_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x83]
-
-s_min_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x83]
-
-s_min_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x83]
-
-s_min_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x83]
-
-s_min_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x83]
-
-s_min_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x83]
-
-s_min_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x83]
-
-s_min_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x83]
-
-s_min_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x83]
-
-s_min_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x83]
-
-s_min_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x83]
-
-s_min_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x83]
-
-s_min_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x83]
-
-s_min_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x83]
-
-s_min_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x83]
-
-s_min_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x83]
-
-s_min_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x83]
-
-s_min_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x83]
-
-s_min_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x83]
-
-s_min_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x83]
-
-s_min_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x83]
-
-s_min_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x83]
-
-s_min_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x83]
-
-s_min_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x83]
-
-s_min_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x83]
-
-s_min_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x83]
-
-s_min_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x83]
-
-s_min_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x83]
-
-s_min_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x83]
-
-s_min_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x83]
-
-s_min_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x83]
-
-s_min_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x83]
-
-s_min_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x83]
-
-s_min_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x83]
-
-s_min_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x83]
-
-s_min_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x83]
-
-s_min_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x83]
-
-s_min_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x83]
-
-s_min_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x83]
-
-s_min_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x83]
-
-s_min_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x83]
-
-s_min_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x83]
-
-s_min_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x83]
-
-s_min_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x83]
-
-s_min_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x83]
-
-s_min_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x83]
-
-s_min_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x83]
-
-s_min_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x83]
-
-s_min_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x83]
-
-s_min_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x83]
-
-s_min_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x83]
-
-s_min_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x83]
-
-s_min_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x83]
-
-s_min_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x83]
-
-s_min_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x83]
-
-s_min_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x83]
-
-s_min_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x83]
-
-s_min_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x83]
-
-s_min_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x83]
-
-s_min_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x83]
-
-s_min_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x83]
-
-s_min_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x83]
-
-s_min_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x83]
-
-s_min_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x83]
-
-s_min_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x83]
-
-s_min_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x83]
-
-s_min_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x83]
-
-s_min_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x83]
-
-s_min_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x83]
-
-s_min_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x83]
-
-s_min_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x83]
-
-s_min_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x83]
-
-s_min_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x83]
-
-s_min_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x83]
-
-s_min_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x83]
-
-s_min_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x83]
-
-s_min_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x83]
-
-s_min_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x83]
-
-s_min_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x83]
-
-s_min_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x83]
-
-s_min_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x83]
-
-s_min_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x83,0x73,0x72,0x71,0x3f]
-
-s_max_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x84]
-
-s_max_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x84]
-
-s_max_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x84]
-
-s_max_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x84]
-
-s_max_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x84]
-
-s_max_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x84]
-
-s_max_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x84]
-
-s_max_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x84]
-
-s_max_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x84]
-
-s_max_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x84]
-
-s_max_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x84]
-
-s_max_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x84]
-
-s_max_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x84]
-
-s_max_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x84]
-
-s_max_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x84]
-
-s_max_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x84]
-
-s_max_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x84]
-
-s_max_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x84]
-
-s_max_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x84]
-
-s_max_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x84]
-
-s_max_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x84]
-
-s_max_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x84]
-
-s_max_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x84]
-
-s_max_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x84]
-
-s_max_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x84]
-
-s_max_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x84]
-
-s_max_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x84]
-
-s_max_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x84]
-
-s_max_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x84]
-
-s_max_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x84]
-
-s_max_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x84]
-
-s_max_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x84]
-
-s_max_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x84]
-
-s_max_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x84]
-
-s_max_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x84]
-
-s_max_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x84]
-
-s_max_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x84]
-
-s_max_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x84]
-
-s_max_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x84]
-
-s_max_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x84]
-
-s_max_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x84]
-
-s_max_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x84]
-
-s_max_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x84]
-
-s_max_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x84]
-
-s_max_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x84]
-
-s_max_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x84]
-
-s_max_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x84]
-
-s_max_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x84]
-
-s_max_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x84]
-
-s_max_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x84]
-
-s_max_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x84]
-
-s_max_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x84]
-
-s_max_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x84]
-
-s_max_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x84]
-
-s_max_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x84]
-
-s_max_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x84]
-
-s_max_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x84]
-
-s_max_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x84]
-
-s_max_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x84]
-
-s_max_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x84]
-
-s_max_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x84]
-
-s_max_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x84]
-
-s_max_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x84]
-
-s_max_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x84]
-
-s_max_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x84]
-
-s_max_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x84]
-
-s_max_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x84]
-
-s_max_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x84]
-
-s_max_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x84]
-
-s_max_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x84]
-
-s_max_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x84]
-
-s_max_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x84]
-
-s_max_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x84]
-
-s_max_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x84]
-
-s_max_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x84]
-
-s_max_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x84]
-
-s_max_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x84]
-
-s_max_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x84]
-
-s_max_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x84]
-
-s_max_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x84]
-
-s_max_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x84]
-
-s_max_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x84]
-
-s_max_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x84]
-
-s_max_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x84]
-
-s_max_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x84]
-
-s_max_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x84]
-
-s_max_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x84]
-
-s_max_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x84]
-
-s_max_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x84]
-
-s_max_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x84]
-
-s_max_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x84]
-
-s_max_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x84]
-
-s_max_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x84]
-
-s_max_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x84]
-
-s_max_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x84]
-
-s_max_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x84]
-
-s_max_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x84,0x73,0x72,0x71,0x3f]
-
-s_cselect_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x85]
-
-s_cselect_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x85]
-
-s_cselect_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x85]
-
-s_cselect_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x85]
-
-s_cselect_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x85]
-
-s_cselect_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x85]
-
-s_cselect_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x85]
-
-s_cselect_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x85]
-
-s_cselect_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x85]
-
-s_cselect_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x85]
-
-s_cselect_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x85]
-
-s_cselect_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x85]
-
-s_cselect_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x85]
-
-s_cselect_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x85]
-
-s_cselect_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x85]
-
-s_cselect_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x85]
-
-s_cselect_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x85]
-
-s_cselect_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x85]
-
-s_cselect_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x85]
-
-s_cselect_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x85]
-
-s_cselect_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x85]
-
-s_cselect_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x85]
-
-s_cselect_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x85]
-
-s_cselect_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x85]
-
-s_cselect_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x85]
-
-s_cselect_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x85]
-
-s_cselect_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x85]
-
-s_cselect_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x85]
-
-s_cselect_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x85]
-
-s_cselect_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x85]
-
-s_cselect_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x85]
-
-s_cselect_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x85]
-
-s_cselect_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x85]
-
-s_cselect_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x85]
-
-s_cselect_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x85]
-
-s_cselect_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x85]
-
-s_cselect_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x85]
-
-s_cselect_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x85]
-
-s_cselect_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x85]
-
-s_cselect_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x85]
-
-s_cselect_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x85]
-
-s_cselect_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x85]
-
-s_cselect_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x85]
-
-s_cselect_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x85]
-
-s_cselect_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x85]
-
-s_cselect_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x85]
-
-s_cselect_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x85]
-
-s_cselect_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x85]
-
-s_cselect_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x85]
-
-s_cselect_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x85]
-
-s_cselect_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x85]
-
-s_cselect_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x85]
-
-s_cselect_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x85]
-
-s_cselect_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x85]
-
-s_cselect_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x85]
-
-s_cselect_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x85]
-
-s_cselect_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x85]
-
-s_cselect_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x85,0x73,0x72,0x71,0x3f]
-
-s_and_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x86]
-
-s_and_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x86]
-
-s_and_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x86]
-
-s_and_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x86]
-
-s_and_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x86]
-
-s_and_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x86]
-
-s_and_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x86]
-
-s_and_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x86]
-
-s_and_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x86]
-
-s_and_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x86]
-
-s_and_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x86]
-
-s_and_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x86]
-
-s_and_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x86]
-
-s_and_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x86]
-
-s_and_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x86]
-
-s_and_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x86]
-
-s_and_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x86]
-
-s_and_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x86]
-
-s_and_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x86]
-
-s_and_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x86]
-
-s_and_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x86]
-
-s_and_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x86]
-
-s_and_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x86]
-
-s_and_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x86]
-
-s_and_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x86]
-
-s_and_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x86]
-
-s_and_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x86]
-
-s_and_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x86]
-
-s_and_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x86]
-
-s_and_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x86]
-
-s_and_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x86]
-
-s_and_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x86,0x56,0x34,0x12,0xaf]
-
-s_and_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x86,0x73,0x72,0x71,0x3f]
-
-s_and_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x86]
-
-s_and_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x86]
-
-s_and_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x86]
-
-s_and_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x86]
-
-s_and_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x86]
-
-s_and_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x86]
-
-s_and_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x86]
-
-s_and_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x86]
-
-s_and_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x86]
-
-s_and_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x86]
-
-s_and_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x86]
-
-s_and_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x86]
-
-s_and_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x86]
-
-s_and_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x86]
-
-s_and_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x86]
-
-s_and_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x86]
-
-s_and_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x86]
-
-s_and_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x86,0x56,0x34,0x12,0xaf]
-
-s_and_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x86,0x73,0x72,0x71,0x3f]
-
-s_and_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x86]
-
-s_and_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x86]
-
-s_and_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x86]
-
-s_and_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x86]
-
-s_and_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x86]
-
-s_and_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x86]
-
-s_and_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x86]
-
-s_and_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x86]
-
-s_and_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x86]
-
-s_and_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x86,0x56,0x34,0x12,0xaf]
-
-s_and_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x86,0x73,0x72,0x71,0x3f]
-
-s_and_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x86,0x56,0x34,0x12,0xaf]
-
-s_and_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x86,0x73,0x72,0x71,0x3f]
-
-s_or_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x87]
-
-s_or_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x87]
-
-s_or_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x87]
-
-s_or_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x87]
-
-s_or_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x87]
-
-s_or_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x87]
-
-s_or_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x87]
-
-s_or_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x87]
-
-s_or_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x87]
-
-s_or_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x87]
-
-s_or_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x87]
-
-s_or_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x87]
-
-s_or_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x87]
-
-s_or_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x87]
-
-s_or_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x87]
-
-s_or_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x87]
-
-s_or_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x87]
-
-s_or_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x87]
-
-s_or_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x87]
-
-s_or_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x87]
-
-s_or_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x87]
-
-s_or_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x87]
-
-s_or_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x87]
-
-s_or_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x87]
-
-s_or_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x87]
-
-s_or_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x87]
-
-s_or_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x87]
-
-s_or_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x87]
-
-s_or_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x87]
-
-s_or_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x87]
-
-s_or_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x87]
-
-s_or_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x87,0x56,0x34,0x12,0xaf]
-
-s_or_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x87,0x73,0x72,0x71,0x3f]
-
-s_or_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x87]
-
-s_or_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x87]
-
-s_or_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x87]
-
-s_or_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x87]
-
-s_or_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x87]
-
-s_or_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x87]
-
-s_or_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x87]
-
-s_or_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x87]
-
-s_or_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x87]
-
-s_or_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x87]
-
-s_or_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x87]
-
-s_or_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x87]
-
-s_or_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x87]
-
-s_or_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x87]
-
-s_or_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x87]
-
-s_or_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x87]
-
-s_or_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x87]
-
-s_or_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x87,0x56,0x34,0x12,0xaf]
-
-s_or_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x87,0x73,0x72,0x71,0x3f]
-
-s_or_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x87]
-
-s_or_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x87]
-
-s_or_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x87]
-
-s_or_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x87]
-
-s_or_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x87]
-
-s_or_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x87]
-
-s_or_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x87]
-
-s_or_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x87]
-
-s_or_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x87]
-
-s_or_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x87,0x56,0x34,0x12,0xaf]
-
-s_or_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x87,0x73,0x72,0x71,0x3f]
-
-s_or_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x87,0x56,0x34,0x12,0xaf]
-
-s_or_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x87,0x73,0x72,0x71,0x3f]
-
-s_xor_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x88]
-
-s_xor_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x88]
-
-s_xor_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x88]
-
-s_xor_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x88]
-
-s_xor_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x88]
-
-s_xor_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x88]
-
-s_xor_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x88]
-
-s_xor_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x88]
-
-s_xor_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x88]
-
-s_xor_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x88]
-
-s_xor_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x88]
-
-s_xor_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x88]
-
-s_xor_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x88]
-
-s_xor_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x88]
-
-s_xor_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x88]
-
-s_xor_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x88]
-
-s_xor_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x88]
-
-s_xor_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x88]
-
-s_xor_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x88]
-
-s_xor_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x88]
-
-s_xor_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x88]
-
-s_xor_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x88]
-
-s_xor_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x88]
-
-s_xor_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x88]
-
-s_xor_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x88]
-
-s_xor_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x88]
-
-s_xor_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x88]
-
-s_xor_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x88]
-
-s_xor_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x88]
-
-s_xor_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x88]
-
-s_xor_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x88]
-
-s_xor_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x88,0x56,0x34,0x12,0xaf]
-
-s_xor_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x88,0x73,0x72,0x71,0x3f]
-
-s_xor_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x88]
-
-s_xor_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x88]
-
-s_xor_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x88]
-
-s_xor_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x88]
-
-s_xor_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x88]
-
-s_xor_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x88]
-
-s_xor_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x88]
-
-s_xor_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x88]
-
-s_xor_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x88]
-
-s_xor_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x88]
-
-s_xor_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x88]
-
-s_xor_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x88]
-
-s_xor_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x88]
-
-s_xor_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x88]
-
-s_xor_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x88]
-
-s_xor_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x88]
-
-s_xor_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x88]
-
-s_xor_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x88,0x56,0x34,0x12,0xaf]
-
-s_xor_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x88,0x73,0x72,0x71,0x3f]
-
-s_xor_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x88]
-
-s_xor_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x88]
-
-s_xor_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x88]
-
-s_xor_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x88]
-
-s_xor_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x88]
-
-s_xor_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x88]
-
-s_xor_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x88]
-
-s_xor_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x88]
-
-s_xor_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x88]
-
-s_xor_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x88,0x56,0x34,0x12,0xaf]
-
-s_xor_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x88,0x73,0x72,0x71,0x3f]
-
-s_xor_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x88,0x56,0x34,0x12,0xaf]
-
-s_xor_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x88,0x73,0x72,0x71,0x3f]
-
-s_andn2_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x89]
-
-s_andn2_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x89]
-
-s_andn2_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x89]
-
-s_andn2_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x89]
-
-s_andn2_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x89]
-
-s_andn2_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x89]
-
-s_andn2_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x89]
-
-s_andn2_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x89]
-
-s_andn2_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x89]
-
-s_andn2_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x89]
-
-s_andn2_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x89]
-
-s_andn2_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x89]
-
-s_andn2_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x89]
-
-s_andn2_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x89]
-
-s_andn2_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x89]
-
-s_andn2_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x89]
-
-s_andn2_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x89]
-
-s_andn2_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x89]
-
-s_andn2_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x89]
-
-s_andn2_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x89]
-
-s_andn2_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x89]
-
-s_andn2_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x89]
-
-s_andn2_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x89]
-
-s_andn2_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x89]
-
-s_andn2_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x89]
-
-s_andn2_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x89]
-
-s_andn2_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x89]
-
-s_andn2_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x89]
-
-s_andn2_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x89]
-
-s_andn2_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x89]
-
-s_andn2_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x89]
-
-s_andn2_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x89,0x56,0x34,0x12,0xaf]
-
-s_andn2_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x89,0x73,0x72,0x71,0x3f]
-
-s_andn2_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x89]
-
-s_andn2_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x89]
-
-s_andn2_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x89]
-
-s_andn2_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x89]
-
-s_andn2_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x89]
-
-s_andn2_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x89]
-
-s_andn2_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x89]
-
-s_andn2_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x89]
-
-s_andn2_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x89]
-
-s_andn2_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x89]
-
-s_andn2_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x89]
-
-s_andn2_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x89]
-
-s_andn2_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x89]
-
-s_andn2_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x89]
-
-s_andn2_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x89]
-
-s_andn2_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x89]
-
-s_andn2_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x89]
-
-s_andn2_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x89,0x56,0x34,0x12,0xaf]
-
-s_andn2_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x89,0x73,0x72,0x71,0x3f]
-
-s_andn2_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x89]
-
-s_andn2_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x89]
-
-s_andn2_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x89]
-
-s_andn2_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x89]
-
-s_andn2_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x89]
-
-s_andn2_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x89]
-
-s_andn2_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x89]
-
-s_andn2_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x89]
-
-s_andn2_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x89]
-
-s_andn2_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x89,0x56,0x34,0x12,0xaf]
-
-s_andn2_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x89,0x73,0x72,0x71,0x3f]
-
-s_andn2_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x89,0x56,0x34,0x12,0xaf]
-
-s_andn2_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x89,0x73,0x72,0x71,0x3f]
-
-s_orn2_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8a]
-
-s_orn2_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8a]
-
-s_orn2_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8a]
-
-s_orn2_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8a]
-
-s_orn2_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8a]
-
-s_orn2_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8a]
-
-s_orn2_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8a]
-
-s_orn2_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8a]
-
-s_orn2_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8a]
-
-s_orn2_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8a]
-
-s_orn2_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8a]
-
-s_orn2_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8a]
-
-s_orn2_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8a]
-
-s_orn2_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8a]
-
-s_orn2_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8a,0x56,0x34,0x12,0xaf]
-
-s_orn2_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8a,0x73,0x72,0x71,0x3f]
-
-s_orn2_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8a]
-
-s_orn2_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8a]
-
-s_orn2_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8a]
-
-s_orn2_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8a]
-
-s_orn2_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8a]
-
-s_orn2_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8a]
-
-s_orn2_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8a]
-
-s_orn2_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8a]
-
-s_orn2_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8a]
-
-s_orn2_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8a]
-
-s_orn2_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8a]
-
-s_orn2_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8a]
-
-s_orn2_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8a]
-
-s_orn2_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8a]
-
-s_orn2_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8a]
-
-s_orn2_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8a]
-
-s_orn2_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8a]
-
-s_orn2_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8a,0x56,0x34,0x12,0xaf]
-
-s_orn2_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8a,0x73,0x72,0x71,0x3f]
-
-s_orn2_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8a]
-
-s_orn2_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x8a]
-
-s_orn2_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8a]
-
-s_orn2_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8a]
-
-s_orn2_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x8a]
-
-s_orn2_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x8a]
-
-s_orn2_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x8a]
-
-s_orn2_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8a]
-
-s_orn2_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8a,0x56,0x34,0x12,0xaf]
-
-s_orn2_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8a,0x73,0x72,0x71,0x3f]
-
-s_orn2_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8a,0x56,0x34,0x12,0xaf]
-
-s_orn2_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8a,0x73,0x72,0x71,0x3f]
-
-s_nand_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8b]
-
-s_nand_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8b]
-
-s_nand_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8b]
-
-s_nand_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8b]
-
-s_nand_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8b]
-
-s_nand_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8b]
-
-s_nand_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8b]
-
-s_nand_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8b]
-
-s_nand_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8b]
-
-s_nand_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8b]
-
-s_nand_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8b]
-
-s_nand_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8b]
-
-s_nand_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8b]
-
-s_nand_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8b]
-
-s_nand_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8b]
-
-s_nand_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8b]
-
-s_nand_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8b]
-
-s_nand_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8b]
-
-s_nand_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8b]
-
-s_nand_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8b]
-
-s_nand_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8b]
-
-s_nand_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8b]
-
-s_nand_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8b]
-
-s_nand_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8b]
-
-s_nand_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8b]
-
-s_nand_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8b]
-
-s_nand_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8b]
-
-s_nand_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8b]
-
-s_nand_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8b]
-
-s_nand_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8b]
-
-s_nand_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8b]
-
-s_nand_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8b,0x56,0x34,0x12,0xaf]
-
-s_nand_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8b,0x73,0x72,0x71,0x3f]
-
-s_nand_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8b]
-
-s_nand_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8b]
-
-s_nand_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8b]
-
-s_nand_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8b]
-
-s_nand_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8b]
-
-s_nand_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8b]
-
-s_nand_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8b]
-
-s_nand_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8b]
-
-s_nand_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8b]
-
-s_nand_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8b]
-
-s_nand_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8b]
-
-s_nand_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8b]
-
-s_nand_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8b]
-
-s_nand_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8b]
-
-s_nand_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8b]
-
-s_nand_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8b]
-
-s_nand_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8b]
-
-s_nand_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8b,0x56,0x34,0x12,0xaf]
-
-s_nand_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8b,0x73,0x72,0x71,0x3f]
-
-s_nand_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8b]
-
-s_nand_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8b]
-
-s_nand_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x8b]
-
-s_nand_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8b]
-
-s_nand_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8b]
-
-s_nand_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x8b]
-
-s_nand_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x8b]
-
-s_nand_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x8b]
-
-s_nand_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8b]
-
-s_nand_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8b,0x56,0x34,0x12,0xaf]
-
-s_nand_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8b,0x73,0x72,0x71,0x3f]
-
-s_nand_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8b,0x56,0x34,0x12,0xaf]
-
-s_nand_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8b,0x73,0x72,0x71,0x3f]
-
-s_nor_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8c]
-
-s_nor_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8c]
-
-s_nor_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8c]
-
-s_nor_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8c]
-
-s_nor_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8c]
-
-s_nor_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8c]
-
-s_nor_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8c]
-
-s_nor_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8c]
-
-s_nor_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8c]
-
-s_nor_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8c]
-
-s_nor_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8c]
-
-s_nor_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8c]
-
-s_nor_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8c]
-
-s_nor_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8c]
-
-s_nor_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8c]
-
-s_nor_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8c]
-
-s_nor_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8c]
-
-s_nor_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8c]
-
-s_nor_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8c]
-
-s_nor_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8c]
-
-s_nor_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8c]
-
-s_nor_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8c]
-
-s_nor_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8c]
-
-s_nor_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8c]
-
-s_nor_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8c]
-
-s_nor_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8c]
-
-s_nor_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8c]
-
-s_nor_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8c]
-
-s_nor_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8c]
-
-s_nor_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8c]
-
-s_nor_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8c]
-
-s_nor_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nor_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nor_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8c]
-
-s_nor_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8c]
-
-s_nor_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8c]
-
-s_nor_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8c]
-
-s_nor_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8c]
-
-s_nor_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8c]
-
-s_nor_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8c]
-
-s_nor_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8c]
-
-s_nor_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8c]
-
-s_nor_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8c]
-
-s_nor_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8c]
-
-s_nor_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8c]
-
-s_nor_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8c]
-
-s_nor_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8c]
-
-s_nor_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8c]
-
-s_nor_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8c]
-
-s_nor_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8c]
-
-s_nor_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nor_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nor_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8c]
-
-s_nor_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8c]
-
-s_nor_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x8c]
-
-s_nor_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8c]
-
-s_nor_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8c]
-
-s_nor_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x8c]
-
-s_nor_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x8c]
-
-s_nor_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x8c]
-
-s_nor_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8c]
-
-s_nor_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nor_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nor_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nor_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8c,0x73,0x72,0x71,0x3f]
-
-s_xnor_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8d]
-
-s_xnor_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8d]
-
-s_xnor_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8d]
-
-s_xnor_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8d]
-
-s_xnor_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8d]
-
-s_xnor_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8d]
-
-s_xnor_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8d]
-
-s_xnor_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8d]
-
-s_xnor_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8d]
-
-s_xnor_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8d]
-
-s_xnor_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8d]
-
-s_xnor_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8d]
-
-s_xnor_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8d]
-
-s_xnor_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8d]
-
-s_xnor_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8d,0x56,0x34,0x12,0xaf]
-
-s_xnor_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8d,0x73,0x72,0x71,0x3f]
-
-s_xnor_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8d]
-
-s_xnor_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8d]
-
-s_xnor_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8d]
-
-s_xnor_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8d]
-
-s_xnor_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8d]
-
-s_xnor_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8d]
-
-s_xnor_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8d]
-
-s_xnor_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8d]
-
-s_xnor_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8d]
-
-s_xnor_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8d]
-
-s_xnor_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8d]
-
-s_xnor_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8d]
-
-s_xnor_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8d]
-
-s_xnor_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8d]
-
-s_xnor_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8d]
-
-s_xnor_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8d]
-
-s_xnor_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8d]
-
-s_xnor_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8d,0x56,0x34,0x12,0xaf]
-
-s_xnor_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8d,0x73,0x72,0x71,0x3f]
-
-s_xnor_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8d]
-
-s_xnor_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x8d]
-
-s_xnor_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8d]
-
-s_xnor_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8d]
-
-s_xnor_b64 tba, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xec,0x8d]
-
-s_xnor_b64 tma, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xee,0x8d]
-
-s_xnor_b64 ttmp[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfa,0x8d]
-
-s_xnor_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8d]
-
-s_xnor_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], tba, s[4:5]
-// CHECK: [0x6c,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], tma, s[4:5]
-// CHECK: [0x6e,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8d,0x56,0x34,0x12,0xaf]
-
-s_xnor_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8d,0x73,0x72,0x71,0x3f]
-
-s_xnor_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], tba
-// CHECK: [0x02,0x6c,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], tma
-// CHECK: [0x02,0x6e,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8d,0x56,0x34,0x12,0xaf]
-
-s_xnor_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8d,0x73,0x72,0x71,0x3f]
-
-s_lshl_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8e]
-
-s_lshl_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8e]
-
-s_lshl_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8e]
-
-s_lshl_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8e]
-
-s_lshl_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8e]
-
-s_lshl_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8e]
-
-s_lshl_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8e]
-
-s_lshl_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8e]
-
-s_lshl_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8e]
-
-s_lshl_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8e]
-
-s_lshl_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8e]
-
-s_lshl_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8e]
-
-s_lshl_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8e]
-
-s_lshl_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8e]
-
-s_lshl_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8e,0x56,0x34,0x12,0xaf]
-
-s_lshl_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8e,0x73,0x72,0x71,0x3f]
-
-s_lshl_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8e]
-
-s_lshl_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8e]
-
-s_lshl_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8e]
-
-s_lshl_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8e]
-
-s_lshl_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8e]
-
-s_lshl_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8e]
-
-s_lshl_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8e]
-
-s_lshl_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8e]
-
-s_lshl_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8e]
-
-s_lshl_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8e]
-
-s_lshl_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8e]
-
-s_lshl_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8e]
-
-s_lshl_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8e]
-
-s_lshl_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8e]
-
-s_lshl_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8e]
-
-s_lshl_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8e]
-
-s_lshl_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8e]
-
-s_lshl_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8e,0x56,0x34,0x12,0xaf]
-
-s_lshl_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8e,0x73,0x72,0x71,0x3f]
-
-s_lshl_b64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x8e]
-
-s_lshl_b64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0xe4,0x8e]
-
-s_lshl_b64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x8e]
-
-s_lshl_b64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x8e]
-
-s_lshl_b64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0xec,0x8e]
-
-s_lshl_b64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0xee,0x8e]
-
-s_lshl_b64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0xfa,0x8e]
-
-s_lshl_b64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x8e]
-
-s_lshl_b64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x8e,0x56,0x34,0x12,0xaf]
-
-s_lshl_b64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x8e,0x73,0x72,0x71,0x3f]
-
-s_lshl_b64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8e,0x56,0x34,0x12,0xaf]
-
-s_lshl_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8e,0x73,0x72,0x71,0x3f]
-
-s_lshr_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8f]
-
-s_lshr_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8f]
-
-s_lshr_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8f]
-
-s_lshr_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8f]
-
-s_lshr_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8f]
-
-s_lshr_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8f]
-
-s_lshr_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x8f]
-
-s_lshr_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x8f]
-
-s_lshr_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x8f]
-
-s_lshr_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x8f]
-
-s_lshr_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x8f]
-
-s_lshr_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8f]
-
-s_lshr_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8f]
-
-s_lshr_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8f]
-
-s_lshr_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshr_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshr_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8f]
-
-s_lshr_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8f]
-
-s_lshr_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8f]
-
-s_lshr_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8f]
-
-s_lshr_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8f]
-
-s_lshr_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x8f]
-
-s_lshr_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x8f]
-
-s_lshr_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x8f]
-
-s_lshr_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x8f]
-
-s_lshr_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x8f]
-
-s_lshr_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8f]
-
-s_lshr_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8f]
-
-s_lshr_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8f]
-
-s_lshr_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8f]
-
-s_lshr_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8f]
-
-s_lshr_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8f]
-
-s_lshr_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8f]
-
-s_lshr_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshr_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshr_b64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x8f]
-
-s_lshr_b64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0xe4,0x8f]
-
-s_lshr_b64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x8f]
-
-s_lshr_b64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x8f]
-
-s_lshr_b64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0xec,0x8f]
-
-s_lshr_b64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0xee,0x8f]
-
-s_lshr_b64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0xfa,0x8f]
-
-s_lshr_b64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x8f]
-
-s_lshr_b64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshr_b64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshr_b64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshr_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8f,0x73,0x72,0x71,0x3f]
-
-s_ashr_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x90]
-
-s_ashr_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x90]
-
-s_ashr_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x90]
-
-s_ashr_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x90]
-
-s_ashr_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x90]
-
-s_ashr_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x90]
-
-s_ashr_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x90]
-
-s_ashr_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x90]
-
-s_ashr_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x90]
-
-s_ashr_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x90]
-
-s_ashr_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x90]
-
-s_ashr_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x90]
-
-s_ashr_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x90]
-
-s_ashr_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x90]
-
-s_ashr_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x90]
-
-s_ashr_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x90]
-
-s_ashr_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x90]
-
-s_ashr_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x90]
-
-s_ashr_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x90]
-
-s_ashr_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x90]
-
-s_ashr_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x90]
-
-s_ashr_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x90]
-
-s_ashr_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x90]
-
-s_ashr_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x90]
-
-s_ashr_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x90]
-
-s_ashr_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x90]
-
-s_ashr_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x90]
-
-s_ashr_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x90]
-
-s_ashr_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x90]
-
-s_ashr_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x90]
-
-s_ashr_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x90]
-
-s_ashr_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x90,0x56,0x34,0x12,0xaf]
-
-s_ashr_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x90,0x73,0x72,0x71,0x3f]
-
-s_ashr_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x90]
-
-s_ashr_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x90]
-
-s_ashr_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x90]
-
-s_ashr_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x90]
-
-s_ashr_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x90]
-
-s_ashr_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x90]
-
-s_ashr_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x90]
-
-s_ashr_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x90]
-
-s_ashr_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x90]
-
-s_ashr_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x90]
-
-s_ashr_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x90]
-
-s_ashr_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x90]
-
-s_ashr_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x90]
-
-s_ashr_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x90]
-
-s_ashr_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x90]
-
-s_ashr_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x90]
-
-s_ashr_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x90]
-
-s_ashr_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x90,0x56,0x34,0x12,0xaf]
-
-s_ashr_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x90,0x73,0x72,0x71,0x3f]
-
-s_ashr_i64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x90]
-
-s_ashr_i64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x90]
-
-s_ashr_i64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0xe4,0x90]
-
-s_ashr_i64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x90]
-
-s_ashr_i64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x90]
-
-s_ashr_i64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0xec,0x90]
-
-s_ashr_i64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0xee,0x90]
-
-s_ashr_i64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0xfa,0x90]
-
-s_ashr_i64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x90]
-
-s_ashr_i64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x90,0x56,0x34,0x12,0xaf]
-
-s_ashr_i64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x90,0x73,0x72,0x71,0x3f]
-
-s_ashr_i64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x90,0x56,0x34,0x12,0xaf]
-
-s_ashr_i64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x90,0x73,0x72,0x71,0x3f]
-
-s_bfm_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x91]
-
-s_bfm_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x91]
-
-s_bfm_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x91]
-
-s_bfm_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x91]
-
-s_bfm_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x91]
-
-s_bfm_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x91]
-
-s_bfm_b32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x91]
-
-s_bfm_b32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x91]
-
-s_bfm_b32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x91]
-
-s_bfm_b32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x91]
-
-s_bfm_b32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x91]
-
-s_bfm_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x91]
-
-s_bfm_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x91]
-
-s_bfm_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x91]
-
-s_bfm_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x91]
-
-s_bfm_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x91]
-
-s_bfm_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x91]
-
-s_bfm_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x91]
-
-s_bfm_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x91]
-
-s_bfm_b32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x91]
-
-s_bfm_b32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x91]
-
-s_bfm_b32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x91]
-
-s_bfm_b32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x91]
-
-s_bfm_b32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x91]
-
-s_bfm_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x91]
-
-s_bfm_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x91]
-
-s_bfm_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x91]
-
-s_bfm_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x91]
-
-s_bfm_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x91]
-
-s_bfm_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x91]
-
-s_bfm_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x91]
-
-s_bfm_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x91,0x56,0x34,0x12,0xaf]
-
-s_bfm_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x91,0x73,0x72,0x71,0x3f]
-
-s_bfm_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x91]
-
-s_bfm_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x91]
-
-s_bfm_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x91]
-
-s_bfm_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x91]
-
-s_bfm_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x91]
-
-s_bfm_b32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x91]
-
-s_bfm_b32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x91]
-
-s_bfm_b32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x91]
-
-s_bfm_b32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x91]
-
-s_bfm_b32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x91]
-
-s_bfm_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x91]
-
-s_bfm_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x91]
-
-s_bfm_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x91]
-
-s_bfm_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x91]
-
-s_bfm_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x91]
-
-s_bfm_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x91]
-
-s_bfm_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x91]
-
-s_bfm_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x91,0x56,0x34,0x12,0xaf]
-
-s_bfm_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x91,0x73,0x72,0x71,0x3f]
-
-s_bfm_b64 s[10:11], s1, s2
-// CHECK: [0x01,0x02,0x8a,0x91]
-
-s_bfm_b64 s[12:13], s1, s2
-// CHECK: [0x01,0x02,0x8c,0x91]
-
-s_bfm_b64 s[100:101], s1, s2
-// CHECK: [0x01,0x02,0xe4,0x91]
-
-s_bfm_b64 flat_scratch, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x91]
-
-s_bfm_b64 vcc, s1, s2
-// CHECK: [0x01,0x02,0xea,0x91]
-
-s_bfm_b64 tba, s1, s2
-// CHECK: [0x01,0x02,0xec,0x91]
-
-s_bfm_b64 tma, s1, s2
-// CHECK: [0x01,0x02,0xee,0x91]
-
-s_bfm_b64 ttmp[10:11], s1, s2
-// CHECK: [0x01,0x02,0xfa,0x91]
-
-s_bfm_b64 exec, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x91]
-
-s_bfm_b64 s[10:11], s101, s2
-// CHECK: [0x65,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], vcc_lo, s2
-// CHECK: [0x6a,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], vcc_hi, s2
-// CHECK: [0x6b,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], tba_lo, s2
-// CHECK: [0x6c,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], tba_hi, s2
-// CHECK: [0x6d,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], tma_lo, s2
-// CHECK: [0x6e,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], tma_hi, s2
-// CHECK: [0x6f,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], ttmp11, s2
-// CHECK: [0x7b,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], m0, s2
-// CHECK: [0x7c,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], exec_lo, s2
-// CHECK: [0x7e,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], exec_hi, s2
-// CHECK: [0x7f,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x91,0x56,0x34,0x12,0xaf]
-
-s_bfm_b64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x91,0x73,0x72,0x71,0x3f]
-
-s_bfm_b64 s[10:11], s1, s101
-// CHECK: [0x01,0x65,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, vcc_lo
-// CHECK: [0x01,0x6a,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, vcc_hi
-// CHECK: [0x01,0x6b,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, tba_lo
-// CHECK: [0x01,0x6c,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, tba_hi
-// CHECK: [0x01,0x6d,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, tma_lo
-// CHECK: [0x01,0x6e,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, tma_hi
-// CHECK: [0x01,0x6f,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, ttmp11
-// CHECK: [0x01,0x7b,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, m0
-// CHECK: [0x01,0x7c,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, exec_lo
-// CHECK: [0x01,0x7e,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, exec_hi
-// CHECK: [0x01,0x7f,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, 0
-// CHECK: [0x01,0x80,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, -1
-// CHECK: [0x01,0xc1,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, 0.5
-// CHECK: [0x01,0xf0,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, -4.0
-// CHECK: [0x01,0xf7,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, 0xaf123456
-// CHECK: [0x01,0xff,0x8a,0x91,0x56,0x34,0x12,0xaf]
-
-s_bfm_b64 s[10:11], s1, 0x3f717273
-// CHECK: [0x01,0xff,0x8a,0x91,0x73,0x72,0x71,0x3f]
-
-s_mul_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x92]
-
-s_mul_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x92]
-
-s_mul_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x92]
-
-s_mul_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x92]
-
-s_mul_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x92]
-
-s_mul_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x92]
-
-s_mul_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x92]
-
-s_mul_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x92]
-
-s_mul_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x92]
-
-s_mul_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x92]
-
-s_mul_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x92]
-
-s_mul_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x92]
-
-s_mul_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x92]
-
-s_mul_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x92]
-
-s_mul_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x92]
-
-s_mul_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x92]
-
-s_mul_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x92]
-
-s_mul_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x92]
-
-s_mul_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x92]
-
-s_mul_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x92]
-
-s_mul_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x92]
-
-s_mul_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x92]
-
-s_mul_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x92]
-
-s_mul_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x92]
-
-s_mul_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x92]
-
-s_mul_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x92]
-
-s_mul_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x92]
-
-s_mul_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x92]
-
-s_mul_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x92]
-
-s_mul_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x92]
-
-s_mul_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x92]
-
-s_mul_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x92,0x56,0x34,0x12,0xaf]
-
-s_mul_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x92,0x73,0x72,0x71,0x3f]
-
-s_mul_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x92]
-
-s_mul_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x92]
-
-s_mul_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x92]
-
-s_mul_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x92]
-
-s_mul_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x92]
-
-s_mul_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x92]
-
-s_mul_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x92]
-
-s_mul_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x92]
-
-s_mul_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x92]
-
-s_mul_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x92]
-
-s_mul_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x92]
-
-s_mul_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x92]
-
-s_mul_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x92]
-
-s_mul_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x92]
-
-s_mul_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x92]
-
-s_mul_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x92]
-
-s_mul_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x92]
-
-s_mul_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x92,0x56,0x34,0x12,0xaf]
-
-s_mul_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfe_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x92]
-
-s_bfe_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x92]
-
-s_bfe_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x92]
-
-s_bfe_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x92]
-
-s_bfe_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x92]
-
-s_bfe_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x92]
-
-s_bfe_u32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0xec,0x92]
-
-s_bfe_u32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0xed,0x92]
-
-s_bfe_u32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0xee,0x92]
-
-s_bfe_u32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0xef,0x92]
-
-s_bfe_u32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0xfb,0x92]
-
-s_bfe_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x92]
-
-s_bfe_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x92]
-
-s_bfe_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x92]
-
-s_bfe_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x92]
-
-s_bfe_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x92]
-
-s_bfe_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x92]
-
-s_bfe_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x92]
-
-s_bfe_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x92]
-
-s_bfe_u32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x85,0x92]
-
-s_bfe_u32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x85,0x92]
-
-s_bfe_u32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x85,0x92]
-
-s_bfe_u32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x85,0x92]
-
-s_bfe_u32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x85,0x92]
-
-s_bfe_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x92]
-
-s_bfe_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x92]
-
-s_bfe_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x92]
-
-s_bfe_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x92]
-
-s_bfe_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x92]
-
-s_bfe_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x92]
-
-s_bfe_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x92]
-
-s_bfe_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfe_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfe_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x92]
-
-s_bfe_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x92]
-
-s_bfe_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x92]
-
-s_bfe_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x92]
-
-s_bfe_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x92]
-
-s_bfe_u32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x85,0x92]
-
-s_bfe_u32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x85,0x92]
-
-s_bfe_u32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x85,0x92]
-
-s_bfe_u32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x85,0x92]
-
-s_bfe_u32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x85,0x92]
-
-s_bfe_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x92]
-
-s_bfe_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x92]
-
-s_bfe_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x92]
-
-s_bfe_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x92]
-
-s_bfe_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x92]
-
-s_bfe_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x92]
-
-s_bfe_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x92]
-
-s_bfe_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfe_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfe_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x93]
-
-s_bfe_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x93]
-
-s_bfe_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x93]
-
-s_bfe_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x93]
-
-s_bfe_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x93]
-
-s_bfe_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x93]
-
-s_bfe_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x93]
-
-s_bfe_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x93]
-
-s_bfe_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x93]
-
-s_bfe_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x93]
-
-s_bfe_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x93]
-
-s_bfe_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x93]
-
-s_bfe_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x93]
-
-s_bfe_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x93]
-
-s_bfe_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x93]
-
-s_bfe_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x93]
-
-s_bfe_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x93]
-
-s_bfe_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x93]
-
-s_bfe_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x93]
-
-s_bfe_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x93]
-
-s_bfe_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x93]
-
-s_bfe_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x93]
-
-s_bfe_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x93]
-
-s_bfe_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x93]
-
-s_bfe_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x93]
-
-s_bfe_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x93]
-
-s_bfe_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x93]
-
-s_bfe_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x93]
-
-s_bfe_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x93]
-
-s_bfe_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x93]
-
-s_bfe_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x93]
-
-s_bfe_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x93]
-
-s_bfe_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x93]
-
-s_bfe_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x93]
-
-s_bfe_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x93]
-
-s_bfe_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x93]
-
-s_bfe_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x93]
-
-s_bfe_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x93]
-
-s_bfe_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x93]
-
-s_bfe_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x93]
-
-s_bfe_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x93]
-
-s_bfe_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x93]
-
-s_bfe_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x93]
-
-s_bfe_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x93]
-
-s_bfe_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x93]
-
-s_bfe_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x93]
-
-s_bfe_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x93]
-
-s_bfe_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x93]
-
-s_bfe_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_u64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x93]
-
-s_bfe_u64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x93]
-
-s_bfe_u64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0xe4,0x93]
-
-s_bfe_u64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x93]
-
-s_bfe_u64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x93]
-
-s_bfe_u64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0xec,0x93]
-
-s_bfe_u64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0xee,0x93]
-
-s_bfe_u64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0xfa,0x93]
-
-s_bfe_u64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x93]
-
-s_bfe_u64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_u64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_u64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_u64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_i64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x0a,0x94]
-
-s_bfe_i64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x0c,0x94]
-
-s_bfe_i64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0x64,0x94]
-
-s_bfe_i64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0x66,0x94]
-
-s_bfe_i64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0x6a,0x94]
-
-s_bfe_i64 tba, s[2:3], s2
-// CHECK: [0x02,0x02,0x6c,0x94]
-
-s_bfe_i64 tma, s[2:3], s2
-// CHECK: [0x02,0x02,0x6e,0x94]
-
-s_bfe_i64 ttmp[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x7a,0x94]
-
-s_bfe_i64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0x7e,0x94]
-
-s_bfe_i64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], tba, s2
-// CHECK: [0x6c,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], tma, s2
-// CHECK: [0x6e,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0a,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_i64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0a,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_i64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x0a,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_i64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x0a,0x94,0x73,0x72,0x71,0x3f]
-
-s_cbranch_g_fork s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x80,0x94]
-
-s_cbranch_g_fork s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x80,0x94]
-
-s_cbranch_g_fork s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x80,0x94]
-
-s_cbranch_g_fork flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x80,0x94]
-
-s_cbranch_g_fork vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x80,0x94]
-
-s_cbranch_g_fork tba, s[4:5]
-// CHECK: [0x6c,0x04,0x80,0x94]
-
-s_cbranch_g_fork tma, s[4:5]
-// CHECK: [0x6e,0x04,0x80,0x94]
-
-s_cbranch_g_fork ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x80,0x94]
-
-s_cbranch_g_fork exec, s[4:5]
-// CHECK: [0x7e,0x04,0x80,0x94]
-
-s_cbranch_g_fork 0, s[4:5]
-// CHECK: [0x80,0x04,0x80,0x94]
-
-s_cbranch_g_fork -1, s[4:5]
-// CHECK: [0xc1,0x04,0x80,0x94]
-
-s_cbranch_g_fork 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x80,0x94]
-
-s_cbranch_g_fork -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], vcc
-// CHECK: [0x02,0x6a,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], tba
-// CHECK: [0x02,0x6c,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], tma
-// CHECK: [0x02,0x6e,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], exec
-// CHECK: [0x02,0x7e,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], 0
-// CHECK: [0x02,0x80,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], -1
-// CHECK: [0x02,0xc1,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x80,0x94]
-
-s_absdiff_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x95]
-
-s_absdiff_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x95]
-
-s_absdiff_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x95]
-
-s_absdiff_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x95]
-
-s_absdiff_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x95]
-
-s_absdiff_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x95]
-
-s_absdiff_i32 tba_lo, s1, s2
-// CHECK: [0x01,0x02,0x6c,0x95]
-
-s_absdiff_i32 tba_hi, s1, s2
-// CHECK: [0x01,0x02,0x6d,0x95]
-
-s_absdiff_i32 tma_lo, s1, s2
-// CHECK: [0x01,0x02,0x6e,0x95]
-
-s_absdiff_i32 tma_hi, s1, s2
-// CHECK: [0x01,0x02,0x6f,0x95]
-
-s_absdiff_i32 ttmp11, s1, s2
-// CHECK: [0x01,0x02,0x7b,0x95]
-
-s_absdiff_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x95]
-
-s_absdiff_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x95]
-
-s_absdiff_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x95]
-
-s_absdiff_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x95,0x56,0x34,0x12,0xaf]
-
-s_absdiff_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x95,0x73,0x72,0x71,0x3f]
-
-s_absdiff_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x95]
-
-s_absdiff_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x95]
-
-s_absdiff_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x95]
-
-s_absdiff_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x95]
-
-s_absdiff_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x95]
-
-s_absdiff_i32 s5, s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0x95]
-
-s_absdiff_i32 s5, s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0x95]
-
-s_absdiff_i32 s5, s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0x95]
-
-s_absdiff_i32 s5, s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0x95]
-
-s_absdiff_i32 s5, s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0x95]
-
-s_absdiff_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x95]
-
-s_absdiff_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x95]
-
-s_absdiff_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x95]
-
-s_absdiff_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x95]
-
-s_absdiff_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x95]
-
-s_absdiff_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x95]
-
-s_absdiff_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x95]
-
-s_absdiff_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x95,0x56,0x34,0x12,0xaf]
-
-s_absdiff_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x95,0x73,0x72,0x71,0x3f]
-
-s_rfe_restore_b64 s[2:3], s2
-// CHECK: [0x02,0x02,0x80,0x95]
-
-s_rfe_restore_b64 s[4:5], s2
-// CHECK: [0x04,0x02,0x80,0x95]
-
-s_rfe_restore_b64 s[100:101], s2
-// CHECK: [0x64,0x02,0x80,0x95]
-
-s_rfe_restore_b64 flat_scratch, s2
-// CHECK: [0x66,0x02,0x80,0x95]
-
-s_rfe_restore_b64 vcc, s2
-// CHECK: [0x6a,0x02,0x80,0x95]
-
-s_rfe_restore_b64 tba, s2
-// CHECK: [0x6c,0x02,0x80,0x95]
-
-s_rfe_restore_b64 tma, s2
-// CHECK: [0x6e,0x02,0x80,0x95]
-
-s_rfe_restore_b64 ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x80,0x95]
-
-s_rfe_restore_b64 exec, s2
-// CHECK: [0x7e,0x02,0x80,0x95]
-
-s_rfe_restore_b64 0, s2
-// CHECK: [0x80,0x02,0x80,0x95]
-
-s_rfe_restore_b64 -1, s2
-// CHECK: [0xc1,0x02,0x80,0x95]
-
-s_rfe_restore_b64 0.5, s2
-// CHECK: [0xf0,0x02,0x80,0x95]
-
-s_rfe_restore_b64 -4.0, s2
-// CHECK: [0xf7,0x02,0x80,0x95]
-
-s_rfe_restore_b64 0xaf123456, s2
-// CHECK: [0xff,0x02,0x80,0x95,0x56,0x34,0x12,0xaf]
-
-s_rfe_restore_b64 0x3f717273, s2
-// CHECK: [0xff,0x02,0x80,0x95,0x73,0x72,0x71,0x3f]
-
-s_rfe_restore_b64 s[2:3], s101
-// CHECK: [0x02,0x65,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], m0
-// CHECK: [0x02,0x7c,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], 0
-// CHECK: [0x02,0x80,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x80,0x95,0x56,0x34,0x12,0xaf]
-
-s_rfe_restore_b64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x80,0x95,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_i32 s1, s2
-// CHECK: [0x01,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 s101, s2
-// CHECK: [0x65,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 m0, s2
-// CHECK: [0x7c,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 0, s2
-// CHECK: [0x80,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 -1, s2
-// CHECK: [0xc1,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x00,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x00,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_i32 s1, s101
-// CHECK: [0x01,0x65,0x00,0xbf]
-
-s_cmp_eq_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x00,0xbf]
-
-s_cmp_eq_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x00,0xbf]
-
-s_cmp_eq_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x00,0xbf]
-
-s_cmp_eq_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x00,0xbf]
-
-s_cmp_eq_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x00,0xbf]
-
-s_cmp_eq_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x00,0xbf]
-
-s_cmp_eq_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x00,0xbf]
-
-s_cmp_eq_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x00,0xbf]
-
-s_cmp_eq_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x00,0xbf]
-
-s_cmp_eq_i32 s1, m0
-// CHECK: [0x01,0x7c,0x00,0xbf]
-
-s_cmp_eq_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x00,0xbf]
-
-s_cmp_eq_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x00,0xbf]
-
-s_cmp_eq_i32 s1, 0
-// CHECK: [0x01,0x80,0x00,0xbf]
-
-s_cmp_eq_i32 s1, -1
-// CHECK: [0x01,0xc1,0x00,0xbf]
-
-s_cmp_eq_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x00,0xbf]
-
-s_cmp_eq_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x00,0xbf]
-
-s_cmp_eq_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_i32 s1, s2
-// CHECK: [0x01,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 s101, s2
-// CHECK: [0x65,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 m0, s2
-// CHECK: [0x7c,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 0, s2
-// CHECK: [0x80,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 -1, s2
-// CHECK: [0xc1,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x01,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x01,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_i32 s1, s101
-// CHECK: [0x01,0x65,0x01,0xbf]
-
-s_cmp_lg_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x01,0xbf]
-
-s_cmp_lg_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x01,0xbf]
-
-s_cmp_lg_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x01,0xbf]
-
-s_cmp_lg_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x01,0xbf]
-
-s_cmp_lg_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x01,0xbf]
-
-s_cmp_lg_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x01,0xbf]
-
-s_cmp_lg_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x01,0xbf]
-
-s_cmp_lg_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x01,0xbf]
-
-s_cmp_lg_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x01,0xbf]
-
-s_cmp_lg_i32 s1, m0
-// CHECK: [0x01,0x7c,0x01,0xbf]
-
-s_cmp_lg_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x01,0xbf]
-
-s_cmp_lg_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x01,0xbf]
-
-s_cmp_lg_i32 s1, 0
-// CHECK: [0x01,0x80,0x01,0xbf]
-
-s_cmp_lg_i32 s1, -1
-// CHECK: [0x01,0xc1,0x01,0xbf]
-
-s_cmp_lg_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x01,0xbf]
-
-s_cmp_lg_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x01,0xbf]
-
-s_cmp_lg_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_i32 s1, s2
-// CHECK: [0x01,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 s101, s2
-// CHECK: [0x65,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 m0, s2
-// CHECK: [0x7c,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 0, s2
-// CHECK: [0x80,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 -1, s2
-// CHECK: [0xc1,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x02,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x02,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_i32 s1, s101
-// CHECK: [0x01,0x65,0x02,0xbf]
-
-s_cmp_gt_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x02,0xbf]
-
-s_cmp_gt_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x02,0xbf]
-
-s_cmp_gt_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x02,0xbf]
-
-s_cmp_gt_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x02,0xbf]
-
-s_cmp_gt_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x02,0xbf]
-
-s_cmp_gt_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x02,0xbf]
-
-s_cmp_gt_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x02,0xbf]
-
-s_cmp_gt_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x02,0xbf]
-
-s_cmp_gt_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x02,0xbf]
-
-s_cmp_gt_i32 s1, m0
-// CHECK: [0x01,0x7c,0x02,0xbf]
-
-s_cmp_gt_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x02,0xbf]
-
-s_cmp_gt_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x02,0xbf]
-
-s_cmp_gt_i32 s1, 0
-// CHECK: [0x01,0x80,0x02,0xbf]
-
-s_cmp_gt_i32 s1, -1
-// CHECK: [0x01,0xc1,0x02,0xbf]
-
-s_cmp_gt_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x02,0xbf]
-
-s_cmp_gt_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x02,0xbf]
-
-s_cmp_gt_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_i32 s1, s2
-// CHECK: [0x01,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 s101, s2
-// CHECK: [0x65,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 m0, s2
-// CHECK: [0x7c,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 0, s2
-// CHECK: [0x80,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 -1, s2
-// CHECK: [0xc1,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x03,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x03,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_i32 s1, s101
-// CHECK: [0x01,0x65,0x03,0xbf]
-
-s_cmp_ge_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x03,0xbf]
-
-s_cmp_ge_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x03,0xbf]
-
-s_cmp_ge_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x03,0xbf]
-
-s_cmp_ge_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x03,0xbf]
-
-s_cmp_ge_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x03,0xbf]
-
-s_cmp_ge_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x03,0xbf]
-
-s_cmp_ge_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x03,0xbf]
-
-s_cmp_ge_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x03,0xbf]
-
-s_cmp_ge_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x03,0xbf]
-
-s_cmp_ge_i32 s1, m0
-// CHECK: [0x01,0x7c,0x03,0xbf]
-
-s_cmp_ge_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x03,0xbf]
-
-s_cmp_ge_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x03,0xbf]
-
-s_cmp_ge_i32 s1, 0
-// CHECK: [0x01,0x80,0x03,0xbf]
-
-s_cmp_ge_i32 s1, -1
-// CHECK: [0x01,0xc1,0x03,0xbf]
-
-s_cmp_ge_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x03,0xbf]
-
-s_cmp_ge_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x03,0xbf]
-
-s_cmp_ge_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_i32 s1, s2
-// CHECK: [0x01,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 s101, s2
-// CHECK: [0x65,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 m0, s2
-// CHECK: [0x7c,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 0, s2
-// CHECK: [0x80,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 -1, s2
-// CHECK: [0xc1,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x04,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x04,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_i32 s1, s101
-// CHECK: [0x01,0x65,0x04,0xbf]
-
-s_cmp_lt_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x04,0xbf]
-
-s_cmp_lt_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x04,0xbf]
-
-s_cmp_lt_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x04,0xbf]
-
-s_cmp_lt_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x04,0xbf]
-
-s_cmp_lt_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x04,0xbf]
-
-s_cmp_lt_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x04,0xbf]
-
-s_cmp_lt_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x04,0xbf]
-
-s_cmp_lt_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x04,0xbf]
-
-s_cmp_lt_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x04,0xbf]
-
-s_cmp_lt_i32 s1, m0
-// CHECK: [0x01,0x7c,0x04,0xbf]
-
-s_cmp_lt_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x04,0xbf]
-
-s_cmp_lt_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x04,0xbf]
-
-s_cmp_lt_i32 s1, 0
-// CHECK: [0x01,0x80,0x04,0xbf]
-
-s_cmp_lt_i32 s1, -1
-// CHECK: [0x01,0xc1,0x04,0xbf]
-
-s_cmp_lt_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x04,0xbf]
-
-s_cmp_lt_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x04,0xbf]
-
-s_cmp_lt_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_i32 s1, s2
-// CHECK: [0x01,0x02,0x05,0xbf]
-
-s_cmp_le_i32 s101, s2
-// CHECK: [0x65,0x02,0x05,0xbf]
-
-s_cmp_le_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0xbf]
-
-s_cmp_le_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0xbf]
-
-s_cmp_le_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0xbf]
-
-s_cmp_le_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0xbf]
-
-s_cmp_le_i32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x05,0xbf]
-
-s_cmp_le_i32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x05,0xbf]
-
-s_cmp_le_i32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x05,0xbf]
-
-s_cmp_le_i32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x05,0xbf]
-
-s_cmp_le_i32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x05,0xbf]
-
-s_cmp_le_i32 m0, s2
-// CHECK: [0x7c,0x02,0x05,0xbf]
-
-s_cmp_le_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0xbf]
-
-s_cmp_le_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0xbf]
-
-s_cmp_le_i32 0, s2
-// CHECK: [0x80,0x02,0x05,0xbf]
-
-s_cmp_le_i32 -1, s2
-// CHECK: [0xc1,0x02,0x05,0xbf]
-
-s_cmp_le_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0xbf]
-
-s_cmp_le_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0xbf]
-
-s_cmp_le_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_i32 s1, s101
-// CHECK: [0x01,0x65,0x05,0xbf]
-
-s_cmp_le_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0xbf]
-
-s_cmp_le_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0xbf]
-
-s_cmp_le_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0xbf]
-
-s_cmp_le_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0xbf]
-
-s_cmp_le_i32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x05,0xbf]
-
-s_cmp_le_i32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x05,0xbf]
-
-s_cmp_le_i32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x05,0xbf]
-
-s_cmp_le_i32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x05,0xbf]
-
-s_cmp_le_i32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x05,0xbf]
-
-s_cmp_le_i32 s1, m0
-// CHECK: [0x01,0x7c,0x05,0xbf]
-
-s_cmp_le_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0xbf]
-
-s_cmp_le_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0xbf]
-
-s_cmp_le_i32 s1, 0
-// CHECK: [0x01,0x80,0x05,0xbf]
-
-s_cmp_le_i32 s1, -1
-// CHECK: [0x01,0xc1,0x05,0xbf]
-
-s_cmp_le_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0xbf]
-
-s_cmp_le_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0xbf]
-
-s_cmp_le_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u32 s1, s2
-// CHECK: [0x01,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 s101, s2
-// CHECK: [0x65,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 m0, s2
-// CHECK: [0x7c,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 0, s2
-// CHECK: [0x80,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 -1, s2
-// CHECK: [0xc1,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x06,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x06,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u32 s1, s101
-// CHECK: [0x01,0x65,0x06,0xbf]
-
-s_cmp_eq_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x06,0xbf]
-
-s_cmp_eq_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x06,0xbf]
-
-s_cmp_eq_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x06,0xbf]
-
-s_cmp_eq_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x06,0xbf]
-
-s_cmp_eq_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x06,0xbf]
-
-s_cmp_eq_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x06,0xbf]
-
-s_cmp_eq_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x06,0xbf]
-
-s_cmp_eq_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x06,0xbf]
-
-s_cmp_eq_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x06,0xbf]
-
-s_cmp_eq_u32 s1, m0
-// CHECK: [0x01,0x7c,0x06,0xbf]
-
-s_cmp_eq_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x06,0xbf]
-
-s_cmp_eq_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x06,0xbf]
-
-s_cmp_eq_u32 s1, 0
-// CHECK: [0x01,0x80,0x06,0xbf]
-
-s_cmp_eq_u32 s1, -1
-// CHECK: [0x01,0xc1,0x06,0xbf]
-
-s_cmp_eq_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x06,0xbf]
-
-s_cmp_eq_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x06,0xbf]
-
-s_cmp_eq_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u32 s1, s2
-// CHECK: [0x01,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 s101, s2
-// CHECK: [0x65,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 m0, s2
-// CHECK: [0x7c,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 0, s2
-// CHECK: [0x80,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 -1, s2
-// CHECK: [0xc1,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x07,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x07,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u32 s1, s101
-// CHECK: [0x01,0x65,0x07,0xbf]
-
-s_cmp_lg_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x07,0xbf]
-
-s_cmp_lg_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x07,0xbf]
-
-s_cmp_lg_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x07,0xbf]
-
-s_cmp_lg_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x07,0xbf]
-
-s_cmp_lg_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x07,0xbf]
-
-s_cmp_lg_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x07,0xbf]
-
-s_cmp_lg_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x07,0xbf]
-
-s_cmp_lg_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x07,0xbf]
-
-s_cmp_lg_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x07,0xbf]
-
-s_cmp_lg_u32 s1, m0
-// CHECK: [0x01,0x7c,0x07,0xbf]
-
-s_cmp_lg_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x07,0xbf]
-
-s_cmp_lg_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x07,0xbf]
-
-s_cmp_lg_u32 s1, 0
-// CHECK: [0x01,0x80,0x07,0xbf]
-
-s_cmp_lg_u32 s1, -1
-// CHECK: [0x01,0xc1,0x07,0xbf]
-
-s_cmp_lg_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x07,0xbf]
-
-s_cmp_lg_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x07,0xbf]
-
-s_cmp_lg_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_u32 s1, s2
-// CHECK: [0x01,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 s101, s2
-// CHECK: [0x65,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 m0, s2
-// CHECK: [0x7c,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 0, s2
-// CHECK: [0x80,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 -1, s2
-// CHECK: [0xc1,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x08,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x08,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_u32 s1, s101
-// CHECK: [0x01,0x65,0x08,0xbf]
-
-s_cmp_gt_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x08,0xbf]
-
-s_cmp_gt_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x08,0xbf]
-
-s_cmp_gt_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x08,0xbf]
-
-s_cmp_gt_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x08,0xbf]
-
-s_cmp_gt_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x08,0xbf]
-
-s_cmp_gt_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x08,0xbf]
-
-s_cmp_gt_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x08,0xbf]
-
-s_cmp_gt_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x08,0xbf]
-
-s_cmp_gt_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x08,0xbf]
-
-s_cmp_gt_u32 s1, m0
-// CHECK: [0x01,0x7c,0x08,0xbf]
-
-s_cmp_gt_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x08,0xbf]
-
-s_cmp_gt_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x08,0xbf]
-
-s_cmp_gt_u32 s1, 0
-// CHECK: [0x01,0x80,0x08,0xbf]
-
-s_cmp_gt_u32 s1, -1
-// CHECK: [0x01,0xc1,0x08,0xbf]
-
-s_cmp_gt_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x08,0xbf]
-
-s_cmp_gt_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x08,0xbf]
-
-s_cmp_gt_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_u32 s1, s2
-// CHECK: [0x01,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 s101, s2
-// CHECK: [0x65,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 m0, s2
-// CHECK: [0x7c,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 0, s2
-// CHECK: [0x80,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 -1, s2
-// CHECK: [0xc1,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x09,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x09,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_u32 s1, s101
-// CHECK: [0x01,0x65,0x09,0xbf]
-
-s_cmp_ge_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x09,0xbf]
-
-s_cmp_ge_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x09,0xbf]
-
-s_cmp_ge_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x09,0xbf]
-
-s_cmp_ge_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x09,0xbf]
-
-s_cmp_ge_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x09,0xbf]
-
-s_cmp_ge_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x09,0xbf]
-
-s_cmp_ge_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x09,0xbf]
-
-s_cmp_ge_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x09,0xbf]
-
-s_cmp_ge_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x09,0xbf]
-
-s_cmp_ge_u32 s1, m0
-// CHECK: [0x01,0x7c,0x09,0xbf]
-
-s_cmp_ge_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x09,0xbf]
-
-s_cmp_ge_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x09,0xbf]
-
-s_cmp_ge_u32 s1, 0
-// CHECK: [0x01,0x80,0x09,0xbf]
-
-s_cmp_ge_u32 s1, -1
-// CHECK: [0x01,0xc1,0x09,0xbf]
-
-s_cmp_ge_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x09,0xbf]
-
-s_cmp_ge_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x09,0xbf]
-
-s_cmp_ge_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_u32 s1, s2
-// CHECK: [0x01,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 s101, s2
-// CHECK: [0x65,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 m0, s2
-// CHECK: [0x7c,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 0, s2
-// CHECK: [0x80,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 -1, s2
-// CHECK: [0xc1,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0a,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0a,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_u32 s1, s101
-// CHECK: [0x01,0x65,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, m0
-// CHECK: [0x01,0x7c,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, 0
-// CHECK: [0x01,0x80,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, -1
-// CHECK: [0x01,0xc1,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_u32 s1, s2
-// CHECK: [0x01,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 s101, s2
-// CHECK: [0x65,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 m0, s2
-// CHECK: [0x7c,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 0, s2
-// CHECK: [0x80,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 -1, s2
-// CHECK: [0xc1,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0b,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0b,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_u32 s1, s101
-// CHECK: [0x01,0x65,0x0b,0xbf]
-
-s_cmp_le_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x0b,0xbf]
-
-s_cmp_le_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x0b,0xbf]
-
-s_cmp_le_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0b,0xbf]
-
-s_cmp_le_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0b,0xbf]
-
-s_cmp_le_u32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x0b,0xbf]
-
-s_cmp_le_u32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x0b,0xbf]
-
-s_cmp_le_u32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x0b,0xbf]
-
-s_cmp_le_u32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x0b,0xbf]
-
-s_cmp_le_u32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x0b,0xbf]
-
-s_cmp_le_u32 s1, m0
-// CHECK: [0x01,0x7c,0x0b,0xbf]
-
-s_cmp_le_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0b,0xbf]
-
-s_cmp_le_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0b,0xbf]
-
-s_cmp_le_u32 s1, 0
-// CHECK: [0x01,0x80,0x0b,0xbf]
-
-s_cmp_le_u32 s1, -1
-// CHECK: [0x01,0xc1,0x0b,0xbf]
-
-s_cmp_le_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0b,0xbf]
-
-s_cmp_le_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0b,0xbf]
-
-s_cmp_le_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b32 s1, s2
-// CHECK: [0x01,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 s101, s2
-// CHECK: [0x65,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 m0, s2
-// CHECK: [0x7c,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 0, s2
-// CHECK: [0x80,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 -1, s2
-// CHECK: [0xc1,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 0.5, s2
-// CHECK: [0xf0,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0c,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0c,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b32 s1, s101
-// CHECK: [0x01,0x65,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, m0
-// CHECK: [0x01,0x7c,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, 0
-// CHECK: [0x01,0x80,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, -1
-// CHECK: [0x01,0xc1,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b32 s1, s2
-// CHECK: [0x01,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 s101, s2
-// CHECK: [0x65,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 tba_lo, s2
-// CHECK: [0x6c,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 tba_hi, s2
-// CHECK: [0x6d,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 tma_lo, s2
-// CHECK: [0x6e,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 tma_hi, s2
-// CHECK: [0x6f,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 ttmp11, s2
-// CHECK: [0x7b,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 m0, s2
-// CHECK: [0x7c,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 0, s2
-// CHECK: [0x80,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 -1, s2
-// CHECK: [0xc1,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 0.5, s2
-// CHECK: [0xf0,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0d,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0d,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b32 s1, s101
-// CHECK: [0x01,0x65,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, tba_lo
-// CHECK: [0x01,0x6c,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, tba_hi
-// CHECK: [0x01,0x6d,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, tma_lo
-// CHECK: [0x01,0x6e,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, tma_hi
-// CHECK: [0x01,0x6f,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, ttmp11
-// CHECK: [0x01,0x7b,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, m0
-// CHECK: [0x01,0x7c,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, 0
-// CHECK: [0x01,0x80,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, -1
-// CHECK: [0x01,0xc1,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b64 s[2:3], s2
-// CHECK: [0x02,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 s[4:5], s2
-// CHECK: [0x04,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 s[100:101], s2
-// CHECK: [0x64,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 flat_scratch, s2
-// CHECK: [0x66,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 vcc, s2
-// CHECK: [0x6a,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 tba, s2
-// CHECK: [0x6c,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 tma, s2
-// CHECK: [0x6e,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 exec, s2
-// CHECK: [0x7e,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 0, s2
-// CHECK: [0x80,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 -1, s2
-// CHECK: [0xc1,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 0.5, s2
-// CHECK: [0xf0,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 -4.0, s2
-// CHECK: [0xf7,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0e,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b64 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0e,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b64 s[2:3], s101
-// CHECK: [0x02,0x65,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], m0
-// CHECK: [0x02,0x7c,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], 0
-// CHECK: [0x02,0x80,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b64 s[2:3], s2
-// CHECK: [0x02,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 s[4:5], s2
-// CHECK: [0x04,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 s[100:101], s2
-// CHECK: [0x64,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 flat_scratch, s2
-// CHECK: [0x66,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 vcc, s2
-// CHECK: [0x6a,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 tba, s2
-// CHECK: [0x6c,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 tma, s2
-// CHECK: [0x6e,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 ttmp[10:11], s2
-// CHECK: [0x7a,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 exec, s2
-// CHECK: [0x7e,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 0, s2
-// CHECK: [0x80,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 -1, s2
-// CHECK: [0xc1,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 0.5, s2
-// CHECK: [0xf0,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 -4.0, s2
-// CHECK: [0xf7,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0f,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b64 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0f,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b64 s[2:3], s101
-// CHECK: [0x02,0x65,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], tba_lo
-// CHECK: [0x02,0x6c,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], tba_hi
-// CHECK: [0x02,0x6d,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], tma_lo
-// CHECK: [0x02,0x6e,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], tma_hi
-// CHECK: [0x02,0x6f,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], ttmp11
-// CHECK: [0x02,0x7b,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], m0
-// CHECK: [0x02,0x7c,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], 0
-// CHECK: [0x02,0x80,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f]
-
-s_setvskip s1, s2
-// CHECK: [0x01,0x02,0x10,0xbf]
-
-s_setvskip s101, s2
-// CHECK: [0x65,0x02,0x10,0xbf]
-
-s_setvskip flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x10,0xbf]
-
-s_setvskip flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x10,0xbf]
-
-s_setvskip vcc_lo, s2
-// CHECK: [0x6a,0x02,0x10,0xbf]
-
-s_setvskip vcc_hi, s2
-// CHECK: [0x6b,0x02,0x10,0xbf]
-
-s_setvskip tba_lo, s2
-// CHECK: [0x6c,0x02,0x10,0xbf]
-
-s_setvskip tba_hi, s2
-// CHECK: [0x6d,0x02,0x10,0xbf]
-
-s_setvskip tma_lo, s2
-// CHECK: [0x6e,0x02,0x10,0xbf]
-
-s_setvskip tma_hi, s2
-// CHECK: [0x6f,0x02,0x10,0xbf]
-
-s_setvskip ttmp11, s2
-// CHECK: [0x7b,0x02,0x10,0xbf]
-
-s_setvskip m0, s2
-// CHECK: [0x7c,0x02,0x10,0xbf]
-
-s_setvskip exec_lo, s2
-// CHECK: [0x7e,0x02,0x10,0xbf]
-
-s_setvskip exec_hi, s2
-// CHECK: [0x7f,0x02,0x10,0xbf]
-
-s_setvskip 0, s2
-// CHECK: [0x80,0x02,0x10,0xbf]
-
-s_setvskip -1, s2
-// CHECK: [0xc1,0x02,0x10,0xbf]
-
-s_setvskip 0.5, s2
-// CHECK: [0xf0,0x02,0x10,0xbf]
-
-s_setvskip -4.0, s2
-// CHECK: [0xf7,0x02,0x10,0xbf]
-
-s_setvskip 0xaf123456, s2
-// CHECK: [0xff,0x02,0x10,0xbf,0x56,0x34,0x12,0xaf]
-
-s_setvskip 0x3f717273, s2
-// CHECK: [0xff,0x02,0x10,0xbf,0x73,0x72,0x71,0x3f]
-
-s_setvskip s1, s101
-// CHECK: [0x01,0x65,0x10,0xbf]
-
-s_setvskip s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x10,0xbf]
-
-s_setvskip s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x10,0xbf]
-
-s_setvskip s1, vcc_lo
-// CHECK: [0x01,0x6a,0x10,0xbf]
-
-s_setvskip s1, vcc_hi
-// CHECK: [0x01,0x6b,0x10,0xbf]
-
-s_setvskip s1, tba_lo
-// CHECK: [0x01,0x6c,0x10,0xbf]
-
-s_setvskip s1, tba_hi
-// CHECK: [0x01,0x6d,0x10,0xbf]
-
-s_setvskip s1, tma_lo
-// CHECK: [0x01,0x6e,0x10,0xbf]
-
-s_setvskip s1, tma_hi
-// CHECK: [0x01,0x6f,0x10,0xbf]
-
-s_setvskip s1, ttmp11
-// CHECK: [0x01,0x7b,0x10,0xbf]
-
-s_setvskip s1, m0
-// CHECK: [0x01,0x7c,0x10,0xbf]
-
-s_setvskip s1, exec_lo
-// CHECK: [0x01,0x7e,0x10,0xbf]
-
-s_setvskip s1, exec_hi
-// CHECK: [0x01,0x7f,0x10,0xbf]
-
-s_setvskip s1, 0
-// CHECK: [0x01,0x80,0x10,0xbf]
-
-s_setvskip s1, -1
-// CHECK: [0x01,0xc1,0x10,0xbf]
-
-s_setvskip s1, 0.5
-// CHECK: [0x01,0xf0,0x10,0xbf]
-
-s_setvskip s1, -4.0
-// CHECK: [0x01,0xf7,0x10,0xbf]
-
-s_setvskip s1, 0xaf123456
-// CHECK: [0x01,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf]
-
-s_setvskip s1, 0x3f717273
-// CHECK: [0x01,0xff,0x10,0xbf,0x73,0x72,0x71,0x3f]
-
-s_set_gpr_idx_on s1, 0x0
-// CHECK: [0x01,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on s101, 0x0
-// CHECK: [0x65,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on flat_scratch_lo, 0x0
-// CHECK: [0x66,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on flat_scratch_hi, 0x0
-// CHECK: [0x67,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on vcc_lo, 0x0
-// CHECK: [0x6a,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on vcc_hi, 0x0
-// CHECK: [0x6b,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on tba_lo, 0x0
-// CHECK: [0x6c,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on tba_hi, 0x0
-// CHECK: [0x6d,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on tma_lo, 0x0
-// CHECK: [0x6e,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on tma_hi, 0x0
-// CHECK: [0x6f,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on ttmp11, 0x0
-// CHECK: [0x7b,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on m0, 0x0
-// CHECK: [0x7c,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on 0, 0x0
-// CHECK: [0x80,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on -1, 0x0
-// CHECK: [0xc1,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on 0.5, 0x0
-// CHECK: [0xf0,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on -4.0, 0x0
-// CHECK: [0xf7,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on 0xaf123456, 0x0
-// CHECK: [0xff,0x00,0x11,0xbf,0x56,0x34,0x12,0xaf]
-
-s_set_gpr_idx_on 0x3f717273, 0x0
-// CHECK: [0xff,0x00,0x11,0xbf,0x73,0x72,0x71,0x3f]
-
-s_set_gpr_idx_on s1, 0x1
-// CHECK: [0x01,0x01,0x11,0xbf]
-
-s_set_gpr_idx_on s1, 0xF
-// CHECK: [0x01,0x0f,0x11,0xbf]
-
-s_cmp_eq_u64 s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 tba, s[4:5]
-// CHECK: [0x6c,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 tma, s[4:5]
-// CHECK: [0x6e,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 exec, s[4:5]
-// CHECK: [0x7e,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 0, s[4:5]
-// CHECK: [0x80,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 -1, s[4:5]
-// CHECK: [0xc1,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x12,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u64 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x12,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u64 s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], vcc
-// CHECK: [0x02,0x6a,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], tba
-// CHECK: [0x02,0x6c,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], tma
-// CHECK: [0x02,0x6e,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], exec
-// CHECK: [0x02,0x7e,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], 0
-// CHECK: [0x02,0x80,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x12,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x12,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u64 s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 tba, s[4:5]
-// CHECK: [0x6c,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 tma, s[4:5]
-// CHECK: [0x6e,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 ttmp[10:11], s[4:5]
-// CHECK: [0x7a,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 exec, s[4:5]
-// CHECK: [0x7e,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 0, s[4:5]
-// CHECK: [0x80,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 -1, s[4:5]
-// CHECK: [0xc1,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x13,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u64 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x13,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u64 s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], vcc
-// CHECK: [0x02,0x6a,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], tba
-// CHECK: [0x02,0x6c,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], tma
-// CHECK: [0x02,0x6e,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], ttmp[10:11]
-// CHECK: [0x02,0x7a,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], exec
-// CHECK: [0x02,0x7e,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], 0
-// CHECK: [0x02,0x80,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x13,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x13,0xbf,0x73,0x72,0x71,0x3f]
-
-s_movk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x05,0xb0]
-
-s_movk_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb0]
-
-s_movk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb0]
-
-s_movk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb0]
-
-s_movk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb0]
-
-s_movk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb0]
-
-s_movk_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb0]
-
-s_movk_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb0]
-
-s_movk_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb0]
-
-s_movk_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb0]
-
-s_movk_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb0]
-
-s_movk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb0]
-
-s_movk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb0]
-
-s_movk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb0]
-
-s_movk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x05,0xb0]
-
-s_cmovk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x85,0xb0]
-
-s_cmovk_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb0]
-
-s_cmovk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb0]
-
-s_cmovk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb0]
-
-s_cmovk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb0]
-
-s_cmovk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb0]
-
-s_cmovk_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb0]
-
-s_cmovk_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb0]
-
-s_cmovk_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb0]
-
-s_cmovk_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb0]
-
-s_cmovk_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb0]
-
-s_cmovk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb0]
-
-s_cmovk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb0]
-
-s_cmovk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb0]
-
-s_cmovk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x85,0xb0]
-
-s_cmpk_eq_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb1]
-
-s_cmpk_eq_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb1]
-
-s_cmpk_eq_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb1]
-
-s_cmpk_eq_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb1]
-
-s_cmpk_eq_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb1]
-
-s_cmpk_eq_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb1]
-
-s_cmpk_eq_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb1]
-
-s_cmpk_eq_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb1]
-
-s_cmpk_eq_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb1]
-
-s_cmpk_eq_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb1]
-
-s_cmpk_eq_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb1]
-
-s_cmpk_eq_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb1]
-
-s_cmpk_eq_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb1]
-
-s_cmpk_eq_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb1]
-
-s_cmpk_eq_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb1]
-
-s_cmpk_lg_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb1]
-
-s_cmpk_lg_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb1]
-
-s_cmpk_lg_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb1]
-
-s_cmpk_lg_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb1]
-
-s_cmpk_lg_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb1]
-
-s_cmpk_lg_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb1]
-
-s_cmpk_lg_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb1]
-
-s_cmpk_lg_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb1]
-
-s_cmpk_lg_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb1]
-
-s_cmpk_lg_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb1]
-
-s_cmpk_lg_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb1]
-
-s_cmpk_lg_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb1]
-
-s_cmpk_lg_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb1]
-
-s_cmpk_lg_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb1]
-
-s_cmpk_lg_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb1]
-
-s_cmpk_gt_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb2]
-
-s_cmpk_gt_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb2]
-
-s_cmpk_gt_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb2]
-
-s_cmpk_gt_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb2]
-
-s_cmpk_gt_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb2]
-
-s_cmpk_gt_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb2]
-
-s_cmpk_gt_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb2]
-
-s_cmpk_gt_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb2]
-
-s_cmpk_gt_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb2]
-
-s_cmpk_gt_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb2]
-
-s_cmpk_gt_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb2]
-
-s_cmpk_gt_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb2]
-
-s_cmpk_gt_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb2]
-
-s_cmpk_gt_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb2]
-
-s_cmpk_gt_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb2]
-
-s_cmpk_ge_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb2]
-
-s_cmpk_ge_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb2]
-
-s_cmpk_ge_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb2]
-
-s_cmpk_ge_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb2]
-
-s_cmpk_ge_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb2]
-
-s_cmpk_ge_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb2]
-
-s_cmpk_ge_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb2]
-
-s_cmpk_ge_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb2]
-
-s_cmpk_ge_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb2]
-
-s_cmpk_ge_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb2]
-
-s_cmpk_ge_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb2]
-
-s_cmpk_ge_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb2]
-
-s_cmpk_ge_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb2]
-
-s_cmpk_ge_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb2]
-
-s_cmpk_ge_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb2]
-
-s_cmpk_lt_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb3]
-
-s_cmpk_lt_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb3]
-
-s_cmpk_lt_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb3]
-
-s_cmpk_lt_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb3]
-
-s_cmpk_lt_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb3]
-
-s_cmpk_lt_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb3]
-
-s_cmpk_lt_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb3]
-
-s_cmpk_lt_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb3]
-
-s_cmpk_lt_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb3]
-
-s_cmpk_lt_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb3]
-
-s_cmpk_lt_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb3]
-
-s_cmpk_lt_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb3]
-
-s_cmpk_lt_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb3]
-
-s_cmpk_lt_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb3]
-
-s_cmpk_lt_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb3]
-
-s_cmpk_le_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb3]
-
-s_cmpk_le_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb3]
-
-s_cmpk_le_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb3]
-
-s_cmpk_le_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb3]
-
-s_cmpk_le_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb3]
-
-s_cmpk_le_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb3]
-
-s_cmpk_le_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb3]
-
-s_cmpk_le_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb3]
-
-s_cmpk_le_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb3]
-
-s_cmpk_le_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb3]
-
-s_cmpk_le_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb3]
-
-s_cmpk_le_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb3]
-
-s_cmpk_le_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb3]
-
-s_cmpk_le_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb3]
-
-s_cmpk_le_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb3]
-
-s_cmpk_eq_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb4]
-
-s_cmpk_eq_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb4]
-
-s_cmpk_eq_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb4]
-
-s_cmpk_eq_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb4]
-
-s_cmpk_eq_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb4]
-
-s_cmpk_eq_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb4]
-
-s_cmpk_eq_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb4]
-
-s_cmpk_eq_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb4]
-
-s_cmpk_eq_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb4]
-
-s_cmpk_eq_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb4]
-
-s_cmpk_eq_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb4]
-
-s_cmpk_eq_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb4]
-
-s_cmpk_eq_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb4]
-
-s_cmpk_eq_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb4]
-
-s_cmpk_eq_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb4]
-
-s_cmpk_lg_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb4]
-
-s_cmpk_lg_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb4]
-
-s_cmpk_lg_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb4]
-
-s_cmpk_lg_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb4]
-
-s_cmpk_lg_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb4]
-
-s_cmpk_lg_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb4]
-
-s_cmpk_lg_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb4]
-
-s_cmpk_lg_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb4]
-
-s_cmpk_lg_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb4]
-
-s_cmpk_lg_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb4]
-
-s_cmpk_lg_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb4]
-
-s_cmpk_lg_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb4]
-
-s_cmpk_lg_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb4]
-
-s_cmpk_lg_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb4]
-
-s_cmpk_lg_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb4]
-
-s_cmpk_gt_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb5]
-
-s_cmpk_gt_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb5]
-
-s_cmpk_gt_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb5]
-
-s_cmpk_gt_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb5]
-
-s_cmpk_gt_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb5]
-
-s_cmpk_gt_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb5]
-
-s_cmpk_gt_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb5]
-
-s_cmpk_gt_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb5]
-
-s_cmpk_gt_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb5]
-
-s_cmpk_gt_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb5]
-
-s_cmpk_gt_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb5]
-
-s_cmpk_gt_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb5]
-
-s_cmpk_gt_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb5]
-
-s_cmpk_gt_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb5]
-
-s_cmpk_gt_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb5]
-
-s_cmpk_ge_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb5]
-
-s_cmpk_ge_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb5]
-
-s_cmpk_ge_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb5]
-
-s_cmpk_ge_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb5]
-
-s_cmpk_ge_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb5]
-
-s_cmpk_ge_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb5]
-
-s_cmpk_ge_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb5]
-
-s_cmpk_ge_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb5]
-
-s_cmpk_ge_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb5]
-
-s_cmpk_ge_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb5]
-
-s_cmpk_ge_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb5]
-
-s_cmpk_ge_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb5]
-
-s_cmpk_ge_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb5]
-
-s_cmpk_ge_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb5]
-
-s_cmpk_ge_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb5]
-
-s_cmpk_lt_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb6]
-
-s_cmpk_lt_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb6]
-
-s_cmpk_lt_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb6]
-
-s_cmpk_lt_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb6]
-
-s_cmpk_lt_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb6]
-
-s_cmpk_lt_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb6]
-
-s_cmpk_lt_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb6]
-
-s_cmpk_lt_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb6]
-
-s_cmpk_lt_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb6]
-
-s_cmpk_lt_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb6]
-
-s_cmpk_lt_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb6]
-
-s_cmpk_lt_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb6]
-
-s_cmpk_lt_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb6]
-
-s_cmpk_lt_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb6]
-
-s_cmpk_lt_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb6]
-
-s_cmpk_le_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb6]
-
-s_cmpk_le_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb6]
-
-s_cmpk_le_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb6]
-
-s_cmpk_le_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb6]
-
-s_cmpk_le_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb6]
-
-s_cmpk_le_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb6]
-
-s_cmpk_le_u32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb6]
-
-s_cmpk_le_u32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb6]
-
-s_cmpk_le_u32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb6]
-
-s_cmpk_le_u32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb6]
-
-s_cmpk_le_u32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb6]
-
-s_cmpk_le_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb6]
-
-s_cmpk_le_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb6]
-
-s_cmpk_le_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb6]
-
-s_cmpk_le_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb6]
-
-s_addk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x05,0xb7]
-
-s_addk_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb7]
-
-s_addk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb7]
-
-s_addk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb7]
-
-s_addk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb7]
-
-s_addk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb7]
-
-s_addk_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0x6c,0xb7]
-
-s_addk_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0x6d,0xb7]
-
-s_addk_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0x6e,0xb7]
-
-s_addk_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0x6f,0xb7]
-
-s_addk_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0x7b,0xb7]
-
-s_addk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb7]
-
-s_addk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb7]
-
-s_addk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb7]
-
-s_addk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x05,0xb7]
-
-s_mulk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x85,0xb7]
-
-s_mulk_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb7]
-
-s_mulk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb7]
-
-s_mulk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb7]
-
-s_mulk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb7]
-
-s_mulk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb7]
-
-s_mulk_i32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb7]
-
-s_mulk_i32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb7]
-
-s_mulk_i32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb7]
-
-s_mulk_i32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb7]
-
-s_mulk_i32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb7]
-
-s_mulk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb7]
-
-s_mulk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb7]
-
-s_mulk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb7]
-
-s_mulk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x85,0xb7]
-
-s_cbranch_i_fork s[2:3], 12609
-// CHECK: [0x41,0x31,0x02,0xb8]
-
-s_cbranch_i_fork s[4:5], 12609
-// CHECK: [0x41,0x31,0x04,0xb8]
-
-s_cbranch_i_fork s[100:101], 12609
-// CHECK: [0x41,0x31,0x64,0xb8]
-
-s_cbranch_i_fork flat_scratch, 12609
-// CHECK: [0x41,0x31,0x66,0xb8]
-
-s_cbranch_i_fork vcc, 12609
-// CHECK: [0x41,0x31,0x6a,0xb8]
-
-s_cbranch_i_fork tba, 12609
-// CHECK: [0x41,0x31,0x6c,0xb8]
-
-s_cbranch_i_fork tma, 12609
-// CHECK: [0x41,0x31,0x6e,0xb8]
-
-s_cbranch_i_fork ttmp[10:11], 12609
-// CHECK: [0x41,0x31,0x7a,0xb8]
-
-s_cbranch_i_fork exec, 12609
-// CHECK: [0x41,0x31,0x7e,0xb8]
-
-s_cbranch_i_fork s[2:3], 49617
-// CHECK: [0xd1,0xc1,0x02,0xb8]
-
-s_getreg_b32 s5, 0x3141
-// CHECK: [0x41,0x31,0x85,0xb8]
-
-s_getreg_b32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb8]
-
-s_getreg_b32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb8]
-
-s_getreg_b32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb8]
-
-s_getreg_b32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb8]
-
-s_getreg_b32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb8]
-
-s_getreg_b32 tba_lo, 0x3141
-// CHECK: [0x41,0x31,0xec,0xb8]
-
-s_getreg_b32 tba_hi, 0x3141
-// CHECK: [0x41,0x31,0xed,0xb8]
-
-s_getreg_b32 tma_lo, 0x3141
-// CHECK: [0x41,0x31,0xee,0xb8]
-
-s_getreg_b32 tma_hi, 0x3141
-// CHECK: [0x41,0x31,0xef,0xb8]
-
-s_getreg_b32 ttmp11, 0x3141
-// CHECK: [0x41,0x31,0xfb,0xb8]
-
-s_getreg_b32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb8]
-
-s_getreg_b32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb8]
-
-s_getreg_b32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb8]
-
-s_getreg_b32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x85,0xb8]
-
-s_setreg_b32 0x3141, s1
-// CHECK: [0x41,0x31,0x01,0xb9]
-
-s_setreg_b32 0xc1d1, s1
-// CHECK: [0xd1,0xc1,0x01,0xb9]
-
-s_setreg_b32 0x3141, s101
-// CHECK: [0x41,0x31,0x65,0xb9]
-
-s_setreg_b32 0x3141, flat_scratch_lo
-// CHECK: [0x41,0x31,0x66,0xb9]
-
-s_setreg_b32 0x3141, flat_scratch_hi
-// CHECK: [0x41,0x31,0x67,0xb9]
-
-s_setreg_b32 0x3141, vcc_lo
-// CHECK: [0x41,0x31,0x6a,0xb9]
-
-s_setreg_b32 0x3141, vcc_hi
-// CHECK: [0x41,0x31,0x6b,0xb9]
-
-s_setreg_b32 0x3141, tba_lo
-// CHECK: [0x41,0x31,0x6c,0xb9]
-
-s_setreg_b32 0x3141, tba_hi
-// CHECK: [0x41,0x31,0x6d,0xb9]
-
-s_setreg_b32 0x3141, tma_lo
-// CHECK: [0x41,0x31,0x6e,0xb9]
-
-s_setreg_b32 0x3141, tma_hi
-// CHECK: [0x41,0x31,0x6f,0xb9]
-
-s_setreg_b32 0x3141, ttmp11
-// CHECK: [0x41,0x31,0x7b,0xb9]
-
-s_setreg_b32 0x3141, m0
-// CHECK: [0x41,0x31,0x7c,0xb9]
-
-s_setreg_b32 0x3141, exec_lo
-// CHECK: [0x41,0x31,0x7e,0xb9]
-
-s_setreg_b32 0x3141, exec_hi
-// CHECK: [0x41,0x31,0x7f,0xb9]
-
-s_setreg_imm32_b32 0x3141, 0x11213141
-// CHECK: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
-
-s_setreg_imm32_b32 0xc1d1, 0x11213141
-// CHECK: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
-
-s_setreg_imm32_b32 0x3141, 0xa1b1c1d1
-// CHECK: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]
-
-s_nop 0x3141
-// CHECK: [0x41,0x31,0x80,0xbf]
-
-s_nop 0xc1d1
-// CHECK: [0xd1,0xc1,0x80,0xbf]
-
-s_endpgm
-// CHECK: [0x00,0x00,0x81,0xbf]
-
-s_branch 12609
-// CHECK: [0x41,0x31,0x82,0xbf]
-
-s_branch 49617
-// CHECK: [0xd1,0xc1,0x82,0xbf]
-
-s_wakeup
-// CHECK: [0x00,0x00,0x83,0xbf]
-
-s_cbranch_scc0 12609
-// CHECK: [0x41,0x31,0x84,0xbf]
-
-s_cbranch_scc0 49617
-// CHECK: [0xd1,0xc1,0x84,0xbf]
-
-s_cbranch_scc1 12609
-// CHECK: [0x41,0x31,0x85,0xbf]
-
-s_cbranch_scc1 49617
-// CHECK: [0xd1,0xc1,0x85,0xbf]
-
-s_cbranch_vccz 12609
-// CHECK: [0x41,0x31,0x86,0xbf]
-
-s_cbranch_vccz 49617
-// CHECK: [0xd1,0xc1,0x86,0xbf]
-
-s_cbranch_vccnz 12609
-// CHECK: [0x41,0x31,0x87,0xbf]
-
-s_cbranch_vccnz 49617
-// CHECK: [0xd1,0xc1,0x87,0xbf]
-
-s_cbranch_execz 12609
-// CHECK: [0x41,0x31,0x88,0xbf]
-
-s_cbranch_execz 49617
-// CHECK: [0xd1,0xc1,0x88,0xbf]
-
-s_cbranch_execnz 12609
-// CHECK: [0x41,0x31,0x89,0xbf]
-
-s_cbranch_execnz 49617
-// CHECK: [0xd1,0xc1,0x89,0xbf]
-
-s_barrier
-// CHECK: [0x00,0x00,0x8a,0xbf]
-
-s_setkill 0x3141
-// CHECK: [0x41,0x31,0x8b,0xbf]
-
-s_setkill 0xc1d1
-// CHECK: [0xd1,0xc1,0x8b,0xbf]
-
-s_waitcnt 0x3141
-// CHECK: [0x41,0x31,0x8c,0xbf]
-
-s_waitcnt 0xc1d1
-// CHECK: [0xd1,0xc1,0x8c,0xbf]
-
-s_sethalt 0x3141
-// CHECK: [0x41,0x31,0x8d,0xbf]
-
-s_sethalt 0xc1d1
-// CHECK: [0xd1,0xc1,0x8d,0xbf]
-
-s_sleep 0x3141
-// CHECK: [0x41,0x31,0x8e,0xbf]
-
-s_sleep 0xc1d1
-// CHECK: [0xd1,0xc1,0x8e,0xbf]
-
-s_setprio 0x3141
-// CHECK: [0x41,0x31,0x8f,0xbf]
-
-s_setprio 0xc1d1
-// CHECK: [0xd1,0xc1,0x8f,0xbf]
-
-s_sendmsg 0x3141
-// CHECK: [0x41,0x31,0x90,0xbf]
-
-s_sendmsg 0xc1d1
-// CHECK: [0xd1,0xc1,0x90,0xbf]
-
-s_sendmsghalt 0x3141
-// CHECK: [0x41,0x31,0x91,0xbf]
-
-s_sendmsghalt 0xc1d1
-// CHECK: [0xd1,0xc1,0x91,0xbf]
-
-s_trap 0x3141
-// CHECK: [0x41,0x31,0x92,0xbf]
-
-s_trap 0xc1d1
-// CHECK: [0xd1,0xc1,0x92,0xbf]
-
-s_icache_inv
-// CHECK: [0x00,0x00,0x93,0xbf]
-
-s_incperflevel 0x3141
-// CHECK: [0x41,0x31,0x94,0xbf]
-
-s_incperflevel 0xc1d1
-// CHECK: [0xd1,0xc1,0x94,0xbf]
-
-s_decperflevel 0x3141
-// CHECK: [0x41,0x31,0x95,0xbf]
-
-s_decperflevel 0xc1d1
-// CHECK: [0xd1,0xc1,0x95,0xbf]
-
-s_ttracedata
-// CHECK: [0x00,0x00,0x96,0xbf]
-
-s_cbranch_cdbgsys 12609
-// CHECK: [0x41,0x31,0x97,0xbf]
-
-s_cbranch_cdbgsys 49617
-// CHECK: [0xd1,0xc1,0x97,0xbf]
-
-s_cbranch_cdbguser 12609
-// CHECK: [0x41,0x31,0x98,0xbf]
-
-s_cbranch_cdbguser 49617
-// CHECK: [0xd1,0xc1,0x98,0xbf]
-
-s_cbranch_cdbgsys_or_user 12609
-// CHECK: [0x41,0x31,0x99,0xbf]
-
-s_cbranch_cdbgsys_or_user 49617
-// CHECK: [0xd1,0xc1,0x99,0xbf]
-
-s_cbranch_cdbgsys_and_user 12609
-// CHECK: [0x41,0x31,0x9a,0xbf]
-
-s_cbranch_cdbgsys_and_user 49617
-// CHECK: [0xd1,0xc1,0x9a,0xbf]
-
-s_endpgm_saved
-// CHECK: [0x00,0x00,0x9b,0xbf]
-
-s_set_gpr_idx_off
-// CHECK: [0x00,0x00,0x9c,0xbf]
-
-s_set_gpr_idx_mode 0x0
-// CHECK: [0x00,0x00,0x9d,0xbf]
-
-s_set_gpr_idx_mode 0x1
-// CHECK: [0x01,0x00,0x9d,0xbf]
-
-s_set_gpr_idx_mode 0xF
-// CHECK: [0x0f,0x00,0x9d,0xbf]
-
-v_interp_p1_f32 v5, v1, attr0.x
-// CHECK: [0x01,0x00,0x14,0xd4]
-
-v_interp_p1_f32 v255, v1, attr0.x
-// CHECK: [0x01,0x00,0xfc,0xd7]
-
-v_interp_p1_f32 v5, v255, attr0.x
-// CHECK: [0xff,0x00,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr1.x
-// CHECK: [0x01,0x04,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr31.x
-// CHECK: [0x01,0x7c,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr32.x
-// CHECK: [0x01,0x80,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr0.y
-// CHECK: [0x01,0x01,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr0.z
-// CHECK: [0x01,0x02,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr0.w
-// CHECK: [0x01,0x03,0x14,0xd4]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v255, v2, attr0.x
-// CHECK: [0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr1.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr31.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x1f,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr32.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x20,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v255, attr0.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0xfe,0x03,0x00]
-
-v_interp_p1_f32_e64 v5, -v2, attr0.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
-
-v_interp_p1_f32_e64 v5, |v2|, attr0.x
-// CHECK: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.y
-// CHECK: [0x05,0x00,0x70,0xd2,0x40,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.z
-// CHECK: [0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.w
-// CHECK: [0x05,0x00,0x70,0xd2,0xc0,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x clamp
-// CHECK: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x mul:4
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x10]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x div:2
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x18]
-
-v_interp_p2_f32 v5, v1, attr0.x
-// CHECK: [0x01,0x00,0x15,0xd4]
-
-v_interp_p2_f32 v255, v1, attr0.x
-// CHECK: [0x01,0x00,0xfd,0xd7]
-
-v_interp_p2_f32 v5, v255, attr0.x
-// CHECK: [0xff,0x00,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr1.x
-// CHECK: [0x01,0x04,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr31.x
-// CHECK: [0x01,0x7c,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr32.x
-// CHECK: [0x01,0x80,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr0.y
-// CHECK: [0x01,0x01,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr0.z
-// CHECK: [0x01,0x02,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr0.w
-// CHECK: [0x01,0x03,0x15,0xd4]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v255, v2, attr0.x
-// CHECK: [0xff,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr1.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x01,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr31.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr32.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x20,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v255, attr0.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0xfe,0x03,0x00]
-
-v_interp_p2_f32_e64 v5, -v2, attr0.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
-
-v_interp_p2_f32_e64 v5, |v2|, attr0.x
-// CHECK: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.y
-// CHECK: [0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.z
-// CHECK: [0x05,0x00,0x71,0xd2,0x80,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.w
-// CHECK: [0x05,0x00,0x71,0xd2,0xc0,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x clamp
-// CHECK: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x mul:2
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x08]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x mul:4
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x div:2
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x18]
-
-v_interp_mov_f32 v5, p10, attr0.x
-// CHECK: [0x00,0x00,0x16,0xd4]
-
-v_interp_mov_f32 v255, p10, attr0.x
-// CHECK: [0x00,0x00,0xfe,0xd7]
-
-v_interp_mov_f32 v5, p20, attr0.x
-// CHECK: [0x01,0x00,0x16,0xd4]
-
-v_interp_mov_f32 v5, p0, attr0.x
-// CHECK: [0x02,0x00,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr1.x
-// CHECK: [0x00,0x04,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr31.x
-// CHECK: [0x00,0x7c,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr32.x
-// CHECK: [0x00,0x80,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr0.y
-// CHECK: [0x00,0x01,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr0.z
-// CHECK: [0x00,0x02,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr0.w
-// CHECK: [0x00,0x03,0x16,0xd4]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v255, p10, attr0.x
-// CHECK: [0xff,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr1.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x01,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr31.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x1f,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr32.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p20, attr0.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p0, attr0.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x04,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.y
-// CHECK: [0x05,0x00,0x72,0xd2,0x40,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.z
-// CHECK: [0x05,0x00,0x72,0xd2,0x80,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.w
-// CHECK: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x clamp
-// CHECK: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x div:2
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
-
-v_nop
-// CHECK: [0x00,0x00,0x00,0x7e]
-
-v_nop_e64
-// CHECK: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
-
-v_mov_b32 v5, v1
-// CHECK: [0x01,0x03,0x0a,0x7e]
-
-v_mov_b32 v255, v1
-// CHECK: [0x01,0x03,0xfe,0x7f]
-
-v_mov_b32 v5, v255
-// CHECK: [0xff,0x03,0x0a,0x7e]
-
-v_mov_b32 v5, s1
-// CHECK: [0x01,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, s101
-// CHECK: [0x65,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, flat_scratch_lo
-// CHECK: [0x66,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, flat_scratch_hi
-// CHECK: [0x67,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, vcc_lo
-// CHECK: [0x6a,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, vcc_hi
-// CHECK: [0x6b,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, tba_lo
-// CHECK: [0x6c,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, tba_hi
-// CHECK: [0x6d,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, tma_lo
-// CHECK: [0x6e,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, tma_hi
-// CHECK: [0x6f,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, ttmp11
-// CHECK: [0x7b,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, m0
-// CHECK: [0x7c,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, exec_lo
-// CHECK: [0x7e,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, exec_hi
-// CHECK: [0x7f,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, 0
-// CHECK: [0x80,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, -1
-// CHECK: [0xc1,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, 0.5
-// CHECK: [0xf0,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, -4.0
-// CHECK: [0xf7,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, 0xaf123456
-// CHECK: [0xff,0x02,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_mov_b32 v5, 0x3f717273
-// CHECK: [0xff,0x02,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_mov_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x41,0xd1,0x01,0x01,0x00,0x00]
-
-v_mov_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x41,0xd1,0x01,0x01,0x00,0x00]
-
-v_mov_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x41,0xd1,0xff,0x01,0x00,0x00]
-
-v_mov_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x41,0xd1,0x01,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, s101
-// CHECK: [0x05,0x00,0x41,0xd1,0x65,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x41,0xd1,0x66,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x41,0xd1,0x67,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x41,0xd1,0x6a,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x41,0xd1,0x6b,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x41,0xd1,0x6c,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x41,0xd1,0x6d,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x41,0xd1,0x6e,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x41,0xd1,0x6f,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x41,0xd1,0x7b,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x41,0xd1,0x7c,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x41,0xd1,0x7e,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x41,0xd1,0x7f,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x41,0xd1,0x80,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x41,0xd1,0xc1,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x41,0xd1,0xf0,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x41,0xd1,0xf7,0x00,0x00,0x00]
-
-v_readfirstlane_b32 s5, v1
-// CHECK: [0x01,0x05,0x0a,0x7e]
-
-v_readfirstlane_b32 s101, v1
-// CHECK: [0x01,0x05,0xca,0x7e]
-
-v_readfirstlane_b32 flat_scratch_lo, v1
-// CHECK: [0x01,0x05,0xcc,0x7e]
-
-v_readfirstlane_b32 flat_scratch_hi, v1
-// CHECK: [0x01,0x05,0xce,0x7e]
-
-v_readfirstlane_b32 tba_lo, v1
-// CHECK: [0x01,0x05,0xd8,0x7e]
-
-v_readfirstlane_b32 tba_hi, v1
-// CHECK: [0x01,0x05,0xda,0x7e]
-
-v_readfirstlane_b32 tma_lo, v1
-// CHECK: [0x01,0x05,0xdc,0x7e]
-
-v_readfirstlane_b32 tma_hi, v1
-// CHECK: [0x01,0x05,0xde,0x7e]
-
-v_readfirstlane_b32 ttmp11, v1
-// CHECK: [0x01,0x05,0xf6,0x7e]
-
-v_readfirstlane_b32 s5, v255
-// CHECK: [0xff,0x05,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, v[1:2]
-// CHECK: [0x01,0x07,0x0a,0x7e]
-
-v_cvt_i32_f64 v255, v[1:2]
-// CHECK: [0x01,0x07,0xfe,0x7f]
-
-v_cvt_i32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x07,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, s[2:3]
-// CHECK: [0x02,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, s[4:5]
-// CHECK: [0x04,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, s[100:101]
-// CHECK: [0x64,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, flat_scratch
-// CHECK: [0x66,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, vcc
-// CHECK: [0x6a,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, tba
-// CHECK: [0x6c,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, tma
-// CHECK: [0x6e,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, ttmp[10:11]
-// CHECK: [0x7a,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, exec
-// CHECK: [0x7e,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, 0
-// CHECK: [0x80,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, -1
-// CHECK: [0xc1,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, 0.5
-// CHECK: [0xf0,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, -4.0
-// CHECK: [0xf7,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x06,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_i32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x06,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_i32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x43,0xd1,0x02,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x43,0xd1,0x04,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[100:101]
-// CHECK: [0x05,0x00,0x43,0xd1,0x64,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x43,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x43,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, tba
-// CHECK: [0x05,0x00,0x43,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, tma
-// CHECK: [0x05,0x00,0x43,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, ttmp[10:11]
-// CHECK: [0x05,0x00,0x43,0xd1,0x7a,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x43,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x43,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x43,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x43,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x43,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_i32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x43,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32 v[5:6], v1
-// CHECK: [0x01,0x09,0x0a,0x7e]
-
-v_cvt_f64_i32 v[254:255], v1
-// CHECK: [0x01,0x09,0xfc,0x7f]
-
-v_cvt_f64_i32 v[5:6], v255
-// CHECK: [0xff,0x09,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], s1
-// CHECK: [0x01,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], s101
-// CHECK: [0x65,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], flat_scratch_lo
-// CHECK: [0x66,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], flat_scratch_hi
-// CHECK: [0x67,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], vcc_lo
-// CHECK: [0x6a,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], vcc_hi
-// CHECK: [0x6b,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], tba_lo
-// CHECK: [0x6c,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], tba_hi
-// CHECK: [0x6d,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], tma_lo
-// CHECK: [0x6e,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], tma_hi
-// CHECK: [0x6f,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], ttmp11
-// CHECK: [0x7b,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], m0
-// CHECK: [0x7c,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], exec_lo
-// CHECK: [0x7e,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], exec_hi
-// CHECK: [0x7f,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], 0
-// CHECK: [0x80,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], -1
-// CHECK: [0xc1,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], 0.5
-// CHECK: [0xf0,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], -4.0
-// CHECK: [0xf7,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], 0xaf123456
-// CHECK: [0xff,0x08,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_i32 v[5:6], 0x3f717273
-// CHECK: [0xff,0x08,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_i32_e64 v[5:6], v1
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[254:255], v1
-// CHECK: [0xfe,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v255
-// CHECK: [0x05,0x00,0x44,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], s1
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], s101
-// CHECK: [0x05,0x00,0x44,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], flat_scratch_lo
-// CHECK: [0x05,0x00,0x44,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], flat_scratch_hi
-// CHECK: [0x05,0x00,0x44,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], vcc_lo
-// CHECK: [0x05,0x00,0x44,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], vcc_hi
-// CHECK: [0x05,0x00,0x44,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], tba_lo
-// CHECK: [0x05,0x00,0x44,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], tba_hi
-// CHECK: [0x05,0x00,0x44,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], tma_lo
-// CHECK: [0x05,0x00,0x44,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], tma_hi
-// CHECK: [0x05,0x00,0x44,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], ttmp11
-// CHECK: [0x05,0x00,0x44,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], m0
-// CHECK: [0x05,0x00,0x44,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], exec_lo
-// CHECK: [0x05,0x00,0x44,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], exec_hi
-// CHECK: [0x05,0x00,0x44,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x44,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x44,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x44,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x44,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v1 clamp
-// CHECK: [0x05,0x80,0x44,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v1 mul:2
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_i32_e64 v[5:6], v1 mul:4
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_i32_e64 v[5:6], v1 div:2
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_i32 v5, v1
-// CHECK: [0x01,0x0b,0x0a,0x7e]
-
-v_cvt_f32_i32 v255, v1
-// CHECK: [0x01,0x0b,0xfe,0x7f]
-
-v_cvt_f32_i32 v5, v255
-// CHECK: [0xff,0x0b,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, s1
-// CHECK: [0x01,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, s101
-// CHECK: [0x65,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, flat_scratch_lo
-// CHECK: [0x66,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, flat_scratch_hi
-// CHECK: [0x67,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, vcc_lo
-// CHECK: [0x6a,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, vcc_hi
-// CHECK: [0x6b,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, tba_lo
-// CHECK: [0x6c,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, tba_hi
-// CHECK: [0x6d,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, tma_lo
-// CHECK: [0x6e,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, tma_hi
-// CHECK: [0x6f,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, ttmp11
-// CHECK: [0x7b,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, m0
-// CHECK: [0x7c,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, exec_lo
-// CHECK: [0x7e,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, exec_hi
-// CHECK: [0x7f,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, 0
-// CHECK: [0x80,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, -1
-// CHECK: [0xc1,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, 0.5
-// CHECK: [0xf0,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, -4.0
-// CHECK: [0xf7,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, 0xaf123456
-// CHECK: [0xff,0x0a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_i32 v5, 0x3f717273
-// CHECK: [0xff,0x0a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_i32_e64 v5, v1
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v255, v1
-// CHECK: [0xff,0x00,0x45,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v255
-// CHECK: [0x05,0x00,0x45,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, s1
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, s101
-// CHECK: [0x05,0x00,0x45,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x45,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x45,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x45,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x45,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x45,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x45,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x45,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x45,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x45,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, m0
-// CHECK: [0x05,0x00,0x45,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x45,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x45,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, 0
-// CHECK: [0x05,0x00,0x45,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, -1
-// CHECK: [0x05,0x00,0x45,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x45,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x45,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x45,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_i32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_i32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_u32 v5, v1
-// CHECK: [0x01,0x0d,0x0a,0x7e]
-
-v_cvt_f32_u32 v255, v1
-// CHECK: [0x01,0x0d,0xfe,0x7f]
-
-v_cvt_f32_u32 v5, v255
-// CHECK: [0xff,0x0d,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, s1
-// CHECK: [0x01,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, s101
-// CHECK: [0x65,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, flat_scratch_lo
-// CHECK: [0x66,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, flat_scratch_hi
-// CHECK: [0x67,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, vcc_lo
-// CHECK: [0x6a,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, vcc_hi
-// CHECK: [0x6b,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, tba_lo
-// CHECK: [0x6c,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, tba_hi
-// CHECK: [0x6d,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, tma_lo
-// CHECK: [0x6e,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, tma_hi
-// CHECK: [0x6f,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, ttmp11
-// CHECK: [0x7b,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, m0
-// CHECK: [0x7c,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, exec_lo
-// CHECK: [0x7e,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, exec_hi
-// CHECK: [0x7f,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, 0
-// CHECK: [0x80,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, -1
-// CHECK: [0xc1,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, 0.5
-// CHECK: [0xf0,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, -4.0
-// CHECK: [0xf7,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, 0xaf123456
-// CHECK: [0xff,0x0c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_u32 v5, 0x3f717273
-// CHECK: [0xff,0x0c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_u32_e64 v5, v1
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v255, v1
-// CHECK: [0xff,0x00,0x46,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v255
-// CHECK: [0x05,0x00,0x46,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, s1
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, s101
-// CHECK: [0x05,0x00,0x46,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x46,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x46,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x46,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x46,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x46,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x46,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x46,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x46,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x46,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, m0
-// CHECK: [0x05,0x00,0x46,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x46,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x46,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, 0
-// CHECK: [0x05,0x00,0x46,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, -1
-// CHECK: [0x05,0x00,0x46,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x46,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x46,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x46,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_u32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_u32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_u32_f32 v5, v1
-// CHECK: [0x01,0x0f,0x0a,0x7e]
-
-v_cvt_u32_f32 v255, v1
-// CHECK: [0x01,0x0f,0xfe,0x7f]
-
-v_cvt_u32_f32 v5, v255
-// CHECK: [0xff,0x0f,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, s1
-// CHECK: [0x01,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, s101
-// CHECK: [0x65,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, tba_lo
-// CHECK: [0x6c,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, tba_hi
-// CHECK: [0x6d,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, tma_lo
-// CHECK: [0x6e,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, tma_hi
-// CHECK: [0x6f,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, ttmp11
-// CHECK: [0x7b,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, m0
-// CHECK: [0x7c,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, exec_lo
-// CHECK: [0x7e,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, exec_hi
-// CHECK: [0x7f,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, 0
-// CHECK: [0x80,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, -1
-// CHECK: [0xc1,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, 0.5
-// CHECK: [0xf0,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, -4.0
-// CHECK: [0xf7,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x0e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_u32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x0e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_u32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x47,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x47,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x47,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x47,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x47,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x47,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x47,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x47,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x47,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x47,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x47,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x47,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x47,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x47,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x47,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x47,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x47,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x47,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x47,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_u32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x47,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32 v5, v1
-// CHECK: [0x01,0x11,0x0a,0x7e]
-
-v_cvt_i32_f32 v255, v1
-// CHECK: [0x01,0x11,0xfe,0x7f]
-
-v_cvt_i32_f32 v5, v255
-// CHECK: [0xff,0x11,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, s1
-// CHECK: [0x01,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, s101
-// CHECK: [0x65,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, tba_lo
-// CHECK: [0x6c,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, tba_hi
-// CHECK: [0x6d,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, tma_lo
-// CHECK: [0x6e,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, tma_hi
-// CHECK: [0x6f,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, ttmp11
-// CHECK: [0x7b,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, m0
-// CHECK: [0x7c,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, 0
-// CHECK: [0x80,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, -1
-// CHECK: [0xc1,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x10,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x10,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x48,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x48,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x48,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x48,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x48,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x48,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x48,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x48,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x48,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x48,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x48,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x48,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x48,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x48,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x48,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x48,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x48,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x48,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x48,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32 v5, v1
-// CHECK: [0x01,0x15,0x0a,0x7e]
-
-v_cvt_f16_f32 v255, v1
-// CHECK: [0x01,0x15,0xfe,0x7f]
-
-v_cvt_f16_f32 v5, v255
-// CHECK: [0xff,0x15,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, s1
-// CHECK: [0x01,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, s101
-// CHECK: [0x65,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, vcc_lo
-// CHECK: [0x6a,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, vcc_hi
-// CHECK: [0x6b,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, tba_lo
-// CHECK: [0x6c,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, tba_hi
-// CHECK: [0x6d,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, tma_lo
-// CHECK: [0x6e,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, tma_hi
-// CHECK: [0x6f,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, ttmp11
-// CHECK: [0x7b,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, m0
-// CHECK: [0x7c,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, exec_lo
-// CHECK: [0x7e,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, exec_hi
-// CHECK: [0x7f,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0
-// CHECK: [0x80,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, -1
-// CHECK: [0xc1,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0.5
-// CHECK: [0xf0,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, -4.0
-// CHECK: [0xf7,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0xaf123456
-// CHECK: [0xff,0x14,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f16_f32 v5, 0x3f717273
-// CHECK: [0xff,0x14,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f16_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x4a,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x4a,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4a,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4a,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4a,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x4a,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x4a,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x4a,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x4a,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x4a,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x4a,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4a,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x4a,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x4a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4a,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4a,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_f16_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x4a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x4a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f16_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f16_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_f16 v5, v1
-// CHECK: [0x01,0x17,0x0a,0x7e]
-
-v_cvt_f32_f16 v255, v1
-// CHECK: [0x01,0x17,0xfe,0x7f]
-
-v_cvt_f32_f16 v5, v255
-// CHECK: [0xff,0x17,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, s1
-// CHECK: [0x01,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, s101
-// CHECK: [0x65,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, vcc_lo
-// CHECK: [0x6a,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, vcc_hi
-// CHECK: [0x6b,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, tba_lo
-// CHECK: [0x6c,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, tba_hi
-// CHECK: [0x6d,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, tma_lo
-// CHECK: [0x6e,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, tma_hi
-// CHECK: [0x6f,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, ttmp11
-// CHECK: [0x7b,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, m0
-// CHECK: [0x7c,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, exec_lo
-// CHECK: [0x7e,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, exec_hi
-// CHECK: [0x7f,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, 0
-// CHECK: [0x80,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, -1
-// CHECK: [0xc1,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, 0.5
-// CHECK: [0xf0,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, -4.0
-// CHECK: [0xf7,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, 0xfe0b
-// CHECK: [0xff,0x16,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_f32_f16 v5, 0x3456
-// CHECK: [0xff,0x16,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x4b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x4b,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x4b,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4b,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4b,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x4b,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x4b,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x4b,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x4b,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x4b,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x4b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x4b,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x4b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_f32_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x4b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x4b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_f16_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_f16_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_rpi_i32_f32 v5, v1
-// CHECK: [0x01,0x19,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v255, v1
-// CHECK: [0x01,0x19,0xfe,0x7f]
-
-v_cvt_rpi_i32_f32 v5, v255
-// CHECK: [0xff,0x19,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, s1
-// CHECK: [0x01,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, s101
-// CHECK: [0x65,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, tba_lo
-// CHECK: [0x6c,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, tba_hi
-// CHECK: [0x6d,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, tma_lo
-// CHECK: [0x6e,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, tma_hi
-// CHECK: [0x6f,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, ttmp11
-// CHECK: [0x7b,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, m0
-// CHECK: [0x7c,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0
-// CHECK: [0x80,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, -1
-// CHECK: [0xc1,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x18,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_rpi_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x18,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_rpi_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x4c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x4c,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x4c,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4c,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4c,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x4c,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x4c,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x4c,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x4c,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x4c,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x4c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x4c,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x4c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_rpi_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x4c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32 v5, v1
-// CHECK: [0x01,0x1b,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v255, v1
-// CHECK: [0x01,0x1b,0xfe,0x7f]
-
-v_cvt_flr_i32_f32 v5, v255
-// CHECK: [0xff,0x1b,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, s1
-// CHECK: [0x01,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, s101
-// CHECK: [0x65,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, tba_lo
-// CHECK: [0x6c,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, tba_hi
-// CHECK: [0x6d,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, tma_lo
-// CHECK: [0x6e,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, tma_hi
-// CHECK: [0x6f,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, ttmp11
-// CHECK: [0x7b,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, m0
-// CHECK: [0x7c,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0
-// CHECK: [0x80,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, -1
-// CHECK: [0xc1,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x1a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_flr_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x1a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_flr_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x4d,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x4d,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x4d,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4d,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4d,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4d,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4d,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x4d,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x4d,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x4d,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x4d,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x4d,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x4d,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4d,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4d,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x4d,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x4d,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4d,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4d,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_flr_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x4d,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4 v5, v1
-// CHECK: [0x01,0x1d,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v255, v1
-// CHECK: [0x01,0x1d,0xfe,0x7f]
-
-v_cvt_off_f32_i4 v5, v255
-// CHECK: [0xff,0x1d,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, s1
-// CHECK: [0x01,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, s101
-// CHECK: [0x65,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, flat_scratch_lo
-// CHECK: [0x66,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, flat_scratch_hi
-// CHECK: [0x67,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, vcc_lo
-// CHECK: [0x6a,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, vcc_hi
-// CHECK: [0x6b,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, tba_lo
-// CHECK: [0x6c,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, tba_hi
-// CHECK: [0x6d,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, tma_lo
-// CHECK: [0x6e,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, tma_hi
-// CHECK: [0x6f,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, ttmp11
-// CHECK: [0x7b,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, m0
-// CHECK: [0x7c,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, exec_lo
-// CHECK: [0x7e,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, exec_hi
-// CHECK: [0x7f,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0
-// CHECK: [0x80,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, -1
-// CHECK: [0xc1,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0.5
-// CHECK: [0xf0,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, -4.0
-// CHECK: [0xf7,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0x4f
-// CHECK: [0xff,0x1c,0x0a,0x7e,0x4f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4 v5, 0x41
-// CHECK: [0xff,0x1c,0x0a,0x7e,0x41,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v255, v1
-// CHECK: [0xff,0x00,0x4e,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v255
-// CHECK: [0x05,0x00,0x4e,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, s1
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, s101
-// CHECK: [0x05,0x00,0x4e,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4e,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4e,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4e,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4e,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x4e,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x4e,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x4e,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x4e,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x4e,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, m0
-// CHECK: [0x05,0x00,0x4e,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4e,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4e,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, 0
-// CHECK: [0x05,0x00,0x4e,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, -1
-// CHECK: [0x05,0x00,0x4e,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4e,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4e,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x4e,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_off_f32_i4_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_off_f32_i4_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_f64 v5, v[1:2]
-// CHECK: [0x01,0x1f,0x0a,0x7e]
-
-v_cvt_f32_f64 v255, v[1:2]
-// CHECK: [0x01,0x1f,0xfe,0x7f]
-
-v_cvt_f32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x1f,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[2:3]
-// CHECK: [0x02,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[4:5]
-// CHECK: [0x04,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[100:101]
-// CHECK: [0x64,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, flat_scratch
-// CHECK: [0x66,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, vcc
-// CHECK: [0x6a,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, tba
-// CHECK: [0x6c,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, tma
-// CHECK: [0x6e,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, ttmp[10:11]
-// CHECK: [0x7a,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, exec
-// CHECK: [0x7e,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0
-// CHECK: [0x80,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, -1
-// CHECK: [0xc1,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0.5
-// CHECK: [0xf0,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, -4.0
-// CHECK: [0xf7,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x1e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x1e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x4f,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x4f,0xd1,0xfe,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x02,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x04,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[100:101]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x64,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x4f,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x4f,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, tba
-// CHECK: [0x05,0x00,0x4f,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, tma
-// CHECK: [0x05,0x00,0x4f,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, ttmp[10:11]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x7a,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x4f,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x4f,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x4f,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4f,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4f,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_f32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x4f,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[1:2] clamp
-// CHECK: [0x05,0x80,0x4f,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[1:2] mul:2
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_f64_e64 v5, v[1:2] mul:4
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_f64_e64 v5, v[1:2] div:2
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f64_f32 v[5:6], v1
-// CHECK: [0x01,0x21,0x0a,0x7e]
-
-v_cvt_f64_f32 v[254:255], v1
-// CHECK: [0x01,0x21,0xfc,0x7f]
-
-v_cvt_f64_f32 v[5:6], v255
-// CHECK: [0xff,0x21,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], s1
-// CHECK: [0x01,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], s101
-// CHECK: [0x65,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], flat_scratch_lo
-// CHECK: [0x66,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], flat_scratch_hi
-// CHECK: [0x67,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], vcc_lo
-// CHECK: [0x6a,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], vcc_hi
-// CHECK: [0x6b,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], tba_lo
-// CHECK: [0x6c,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], tba_hi
-// CHECK: [0x6d,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], tma_lo
-// CHECK: [0x6e,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], tma_hi
-// CHECK: [0x6f,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], ttmp11
-// CHECK: [0x7b,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], m0
-// CHECK: [0x7c,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], exec_lo
-// CHECK: [0x7e,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], exec_hi
-// CHECK: [0x7f,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0
-// CHECK: [0x80,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], -1
-// CHECK: [0xc1,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0.5
-// CHECK: [0xf0,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], -4.0
-// CHECK: [0xf7,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0xaf123456
-// CHECK: [0xff,0x20,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_f32 v[5:6], 0x3f717273
-// CHECK: [0xff,0x20,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_f32_e64 v[5:6], v1
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[254:255], v1
-// CHECK: [0xfe,0x00,0x50,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v255
-// CHECK: [0x05,0x00,0x50,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], s1
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], s101
-// CHECK: [0x05,0x00,0x50,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], flat_scratch_lo
-// CHECK: [0x05,0x00,0x50,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], flat_scratch_hi
-// CHECK: [0x05,0x00,0x50,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], vcc_lo
-// CHECK: [0x05,0x00,0x50,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], vcc_hi
-// CHECK: [0x05,0x00,0x50,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], tba_lo
-// CHECK: [0x05,0x00,0x50,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], tba_hi
-// CHECK: [0x05,0x00,0x50,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], tma_lo
-// CHECK: [0x05,0x00,0x50,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], tma_hi
-// CHECK: [0x05,0x00,0x50,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], ttmp11
-// CHECK: [0x05,0x00,0x50,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], m0
-// CHECK: [0x05,0x00,0x50,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], exec_lo
-// CHECK: [0x05,0x00,0x50,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], exec_hi
-// CHECK: [0x05,0x00,0x50,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x50,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x50,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x50,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x50,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -v1
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_f64_f32_e64 v[5:6], |v1|
-// CHECK: [0x05,0x01,0x50,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v1 clamp
-// CHECK: [0x05,0x80,0x50,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v1 mul:2
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_f32_e64 v[5:6], v1 mul:4
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_f32_e64 v[5:6], v1 div:2
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte0 v5, v1
-// CHECK: [0x01,0x23,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v255, v1
-// CHECK: [0x01,0x23,0xfe,0x7f]
-
-v_cvt_f32_ubyte0 v5, v255
-// CHECK: [0xff,0x23,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, s1
-// CHECK: [0x01,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, s101
-// CHECK: [0x65,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, flat_scratch_lo
-// CHECK: [0x66,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, flat_scratch_hi
-// CHECK: [0x67,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, vcc_lo
-// CHECK: [0x6a,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, vcc_hi
-// CHECK: [0x6b,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, tba_lo
-// CHECK: [0x6c,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, tba_hi
-// CHECK: [0x6d,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, tma_lo
-// CHECK: [0x6e,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, tma_hi
-// CHECK: [0x6f,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, ttmp11
-// CHECK: [0x7b,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, m0
-// CHECK: [0x7c,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, exec_lo
-// CHECK: [0x7e,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, exec_hi
-// CHECK: [0x7f,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0
-// CHECK: [0x80,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, -1
-// CHECK: [0xc1,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0.5
-// CHECK: [0xf0,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, -4.0
-// CHECK: [0xf7,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0xaf123456
-// CHECK: [0xff,0x22,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte0 v5, 0x3f717273
-// CHECK: [0xff,0x22,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte0_e64 v5, v1
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v255, v1
-// CHECK: [0xff,0x00,0x51,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v255
-// CHECK: [0x05,0x00,0x51,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, s1
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, s101
-// CHECK: [0x05,0x00,0x51,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x51,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x51,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x51,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x51,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x51,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x51,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x51,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x51,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x51,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, m0
-// CHECK: [0x05,0x00,0x51,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x51,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x51,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, 0
-// CHECK: [0x05,0x00,0x51,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, -1
-// CHECK: [0x05,0x00,0x51,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x51,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x51,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x51,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte0_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte0_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte1 v5, v1
-// CHECK: [0x01,0x25,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v255, v1
-// CHECK: [0x01,0x25,0xfe,0x7f]
-
-v_cvt_f32_ubyte1 v5, v255
-// CHECK: [0xff,0x25,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, s1
-// CHECK: [0x01,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, s101
-// CHECK: [0x65,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, flat_scratch_lo
-// CHECK: [0x66,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, flat_scratch_hi
-// CHECK: [0x67,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, vcc_lo
-// CHECK: [0x6a,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, vcc_hi
-// CHECK: [0x6b,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, tba_lo
-// CHECK: [0x6c,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, tba_hi
-// CHECK: [0x6d,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, tma_lo
-// CHECK: [0x6e,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, tma_hi
-// CHECK: [0x6f,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, ttmp11
-// CHECK: [0x7b,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, m0
-// CHECK: [0x7c,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, exec_lo
-// CHECK: [0x7e,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, exec_hi
-// CHECK: [0x7f,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0
-// CHECK: [0x80,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, -1
-// CHECK: [0xc1,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0.5
-// CHECK: [0xf0,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, -4.0
-// CHECK: [0xf7,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0xaf123456
-// CHECK: [0xff,0x24,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte1 v5, 0x3f717273
-// CHECK: [0xff,0x24,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte1_e64 v5, v1
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v255, v1
-// CHECK: [0xff,0x00,0x52,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v255
-// CHECK: [0x05,0x00,0x52,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, s1
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, s101
-// CHECK: [0x05,0x00,0x52,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x52,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x52,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x52,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x52,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x52,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x52,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x52,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x52,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x52,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, m0
-// CHECK: [0x05,0x00,0x52,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x52,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x52,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, 0
-// CHECK: [0x05,0x00,0x52,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, -1
-// CHECK: [0x05,0x00,0x52,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x52,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x52,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x52,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte1_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte1_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte2 v5, v1
-// CHECK: [0x01,0x27,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v255, v1
-// CHECK: [0x01,0x27,0xfe,0x7f]
-
-v_cvt_f32_ubyte2 v5, v255
-// CHECK: [0xff,0x27,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, s1
-// CHECK: [0x01,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, s101
-// CHECK: [0x65,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, flat_scratch_lo
-// CHECK: [0x66,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, flat_scratch_hi
-// CHECK: [0x67,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, vcc_lo
-// CHECK: [0x6a,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, vcc_hi
-// CHECK: [0x6b,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, tba_lo
-// CHECK: [0x6c,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, tba_hi
-// CHECK: [0x6d,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, tma_lo
-// CHECK: [0x6e,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, tma_hi
-// CHECK: [0x6f,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, ttmp11
-// CHECK: [0x7b,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, m0
-// CHECK: [0x7c,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, exec_lo
-// CHECK: [0x7e,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, exec_hi
-// CHECK: [0x7f,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0
-// CHECK: [0x80,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, -1
-// CHECK: [0xc1,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0.5
-// CHECK: [0xf0,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, -4.0
-// CHECK: [0xf7,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0xaf123456
-// CHECK: [0xff,0x26,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte2 v5, 0x3f717273
-// CHECK: [0xff,0x26,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte2_e64 v5, v1
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v255, v1
-// CHECK: [0xff,0x00,0x53,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v255
-// CHECK: [0x05,0x00,0x53,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, s1
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, s101
-// CHECK: [0x05,0x00,0x53,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x53,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x53,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x53,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x53,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x53,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x53,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x53,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x53,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x53,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, m0
-// CHECK: [0x05,0x00,0x53,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x53,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x53,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, 0
-// CHECK: [0x05,0x00,0x53,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, -1
-// CHECK: [0x05,0x00,0x53,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x53,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x53,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x53,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte2_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte2_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte3 v5, v1
-// CHECK: [0x01,0x29,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v255, v1
-// CHECK: [0x01,0x29,0xfe,0x7f]
-
-v_cvt_f32_ubyte3 v5, v255
-// CHECK: [0xff,0x29,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, s1
-// CHECK: [0x01,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, s101
-// CHECK: [0x65,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, flat_scratch_lo
-// CHECK: [0x66,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, flat_scratch_hi
-// CHECK: [0x67,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, vcc_lo
-// CHECK: [0x6a,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, vcc_hi
-// CHECK: [0x6b,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, tba_lo
-// CHECK: [0x6c,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, tba_hi
-// CHECK: [0x6d,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, tma_lo
-// CHECK: [0x6e,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, tma_hi
-// CHECK: [0x6f,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, ttmp11
-// CHECK: [0x7b,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, m0
-// CHECK: [0x7c,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, exec_lo
-// CHECK: [0x7e,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, exec_hi
-// CHECK: [0x7f,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0
-// CHECK: [0x80,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, -1
-// CHECK: [0xc1,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0.5
-// CHECK: [0xf0,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, -4.0
-// CHECK: [0xf7,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0xaf123456
-// CHECK: [0xff,0x28,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte3 v5, 0x3f717273
-// CHECK: [0xff,0x28,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte3_e64 v5, v1
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v255, v1
-// CHECK: [0xff,0x00,0x54,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v255
-// CHECK: [0x05,0x00,0x54,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, s1
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, s101
-// CHECK: [0x05,0x00,0x54,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x54,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x54,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x54,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x54,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x54,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x54,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x54,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x54,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x54,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, m0
-// CHECK: [0x05,0x00,0x54,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x54,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x54,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, 0
-// CHECK: [0x05,0x00,0x54,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, -1
-// CHECK: [0x05,0x00,0x54,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x54,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x54,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x54,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte3_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte3_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_u32_f64 v5, v[1:2]
-// CHECK: [0x01,0x2b,0x0a,0x7e]
-
-v_cvt_u32_f64 v255, v[1:2]
-// CHECK: [0x01,0x2b,0xfe,0x7f]
-
-v_cvt_u32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x2b,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[2:3]
-// CHECK: [0x02,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[4:5]
-// CHECK: [0x04,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[100:101]
-// CHECK: [0x64,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, flat_scratch
-// CHECK: [0x66,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, vcc
-// CHECK: [0x6a,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, tba
-// CHECK: [0x6c,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, tma
-// CHECK: [0x6e,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, ttmp[10:11]
-// CHECK: [0x7a,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, exec
-// CHECK: [0x7e,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0
-// CHECK: [0x80,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, -1
-// CHECK: [0xc1,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0.5
-// CHECK: [0xf0,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, -4.0
-// CHECK: [0xf7,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x2a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_u32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x2a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_u32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x55,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x55,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x55,0xd1,0xfe,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x55,0xd1,0x02,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x55,0xd1,0x04,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[100:101]
-// CHECK: [0x05,0x00,0x55,0xd1,0x64,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x55,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x55,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, tba
-// CHECK: [0x05,0x00,0x55,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, tma
-// CHECK: [0x05,0x00,0x55,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, ttmp[10:11]
-// CHECK: [0x05,0x00,0x55,0xd1,0x7a,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x55,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x55,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x55,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x55,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x55,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x55,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_u32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x55,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32 v[5:6], v1
-// CHECK: [0x01,0x2d,0x0a,0x7e]
-
-v_cvt_f64_u32 v[254:255], v1
-// CHECK: [0x01,0x2d,0xfc,0x7f]
-
-v_cvt_f64_u32 v[5:6], v255
-// CHECK: [0xff,0x2d,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], s1
-// CHECK: [0x01,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], s101
-// CHECK: [0x65,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], flat_scratch_lo
-// CHECK: [0x66,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], flat_scratch_hi
-// CHECK: [0x67,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], vcc_lo
-// CHECK: [0x6a,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], vcc_hi
-// CHECK: [0x6b,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], tba_lo
-// CHECK: [0x6c,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], tba_hi
-// CHECK: [0x6d,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], tma_lo
-// CHECK: [0x6e,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], tma_hi
-// CHECK: [0x6f,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], ttmp11
-// CHECK: [0x7b,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], m0
-// CHECK: [0x7c,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], exec_lo
-// CHECK: [0x7e,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], exec_hi
-// CHECK: [0x7f,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0
-// CHECK: [0x80,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], -1
-// CHECK: [0xc1,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0.5
-// CHECK: [0xf0,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], -4.0
-// CHECK: [0xf7,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0xaf123456
-// CHECK: [0xff,0x2c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_u32 v[5:6], 0x3f717273
-// CHECK: [0xff,0x2c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_u32_e64 v[5:6], v1
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[254:255], v1
-// CHECK: [0xfe,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v255
-// CHECK: [0x05,0x00,0x56,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], s1
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], s101
-// CHECK: [0x05,0x00,0x56,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], flat_scratch_lo
-// CHECK: [0x05,0x00,0x56,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], flat_scratch_hi
-// CHECK: [0x05,0x00,0x56,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], vcc_lo
-// CHECK: [0x05,0x00,0x56,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], vcc_hi
-// CHECK: [0x05,0x00,0x56,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], tba_lo
-// CHECK: [0x05,0x00,0x56,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], tba_hi
-// CHECK: [0x05,0x00,0x56,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], tma_lo
-// CHECK: [0x05,0x00,0x56,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], tma_hi
-// CHECK: [0x05,0x00,0x56,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], ttmp11
-// CHECK: [0x05,0x00,0x56,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], m0
-// CHECK: [0x05,0x00,0x56,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], exec_lo
-// CHECK: [0x05,0x00,0x56,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], exec_hi
-// CHECK: [0x05,0x00,0x56,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x56,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x56,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x56,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x56,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v1 clamp
-// CHECK: [0x05,0x80,0x56,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v1 mul:2
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_u32_e64 v[5:6], v1 mul:4
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_u32_e64 v[5:6], v1 div:2
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x18]
-
-v_trunc_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x2f,0x0a,0x7e]
-
-v_trunc_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x2f,0xfc,0x7f]
-
-v_trunc_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x2f,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], vcc
-// CHECK: [0x6a,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], tba
-// CHECK: [0x6c,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], tma
-// CHECK: [0x6e,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], exec
-// CHECK: [0x7e,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0
-// CHECK: [0x80,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], -1
-// CHECK: [0xc1,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x2e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_trunc_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x2e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_trunc_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x57,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x57,0xd1,0xfe,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x57,0xd1,0x02,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x57,0xd1,0x04,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x57,0xd1,0x64,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x57,0xd1,0x66,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x57,0xd1,0x6a,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x57,0xd1,0x6c,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x57,0xd1,0x6e,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x57,0xd1,0x7a,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x57,0xd1,0x7e,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x57,0xd1,0x80,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x57,0xd1,0xc1,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x57,0xd1,0xf0,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x57,0xd1,0xf7,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x20]
-
-v_trunc_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x57,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x57,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x08]
-
-v_trunc_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x10]
-
-v_trunc_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x18]
-
-v_ceil_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x31,0x0a,0x7e]
-
-v_ceil_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x31,0xfc,0x7f]
-
-v_ceil_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x31,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], vcc
-// CHECK: [0x6a,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], tba
-// CHECK: [0x6c,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], tma
-// CHECK: [0x6e,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], exec
-// CHECK: [0x7e,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0
-// CHECK: [0x80,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], -1
-// CHECK: [0xc1,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x30,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ceil_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x30,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ceil_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x58,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x58,0xd1,0xfe,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x58,0xd1,0x02,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x58,0xd1,0x04,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x58,0xd1,0x64,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x58,0xd1,0x66,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x58,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x58,0xd1,0x6c,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x58,0xd1,0x6e,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x58,0xd1,0x7a,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x58,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x58,0xd1,0x80,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x58,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x58,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x58,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x20]
-
-v_ceil_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x58,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x58,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x08]
-
-v_ceil_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x10]
-
-v_ceil_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x18]
-
-v_rndne_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x33,0x0a,0x7e]
-
-v_rndne_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x33,0xfc,0x7f]
-
-v_rndne_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x33,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], vcc
-// CHECK: [0x6a,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], tba
-// CHECK: [0x6c,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], tma
-// CHECK: [0x6e,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], exec
-// CHECK: [0x7e,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0
-// CHECK: [0x80,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], -1
-// CHECK: [0xc1,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x32,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rndne_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x32,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rndne_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x59,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x59,0xd1,0xfe,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x59,0xd1,0x02,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x59,0xd1,0x04,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x59,0xd1,0x64,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x59,0xd1,0x66,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x59,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x59,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x59,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x59,0xd1,0x7a,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x59,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x59,0xd1,0x80,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x59,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x59,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x59,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x20]
-
-v_rndne_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x59,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x08]
-
-v_rndne_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x10]
-
-v_rndne_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x18]
-
-v_floor_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x35,0x0a,0x7e]
-
-v_floor_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x35,0xfc,0x7f]
-
-v_floor_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x35,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], vcc
-// CHECK: [0x6a,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], tba
-// CHECK: [0x6c,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], tma
-// CHECK: [0x6e,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], exec
-// CHECK: [0x7e,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0
-// CHECK: [0x80,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], -1
-// CHECK: [0xc1,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x34,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_floor_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x34,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_floor_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x5a,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x5a,0xd1,0xfe,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x02,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x04,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x64,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x5a,0xd1,0x66,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x5a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x5a,0xd1,0x6c,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x5a,0xd1,0x6e,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x7a,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x5a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x5a,0xd1,0x80,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x5a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x5a,0xd1,0xf0,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x5a,0xd1,0xf7,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x20]
-
-v_floor_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x5a,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x08]
-
-v_floor_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x10]
-
-v_floor_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x18]
-
-v_fract_f32 v5, v1
-// CHECK: [0x01,0x37,0x0a,0x7e]
-
-v_fract_f32 v255, v1
-// CHECK: [0x01,0x37,0xfe,0x7f]
-
-v_fract_f32 v5, v255
-// CHECK: [0xff,0x37,0x0a,0x7e]
-
-v_fract_f32 v5, s1
-// CHECK: [0x01,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, s101
-// CHECK: [0x65,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, vcc_lo
-// CHECK: [0x6a,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, vcc_hi
-// CHECK: [0x6b,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, tba_lo
-// CHECK: [0x6c,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, tba_hi
-// CHECK: [0x6d,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, tma_lo
-// CHECK: [0x6e,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, tma_hi
-// CHECK: [0x6f,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, ttmp11
-// CHECK: [0x7b,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, m0
-// CHECK: [0x7c,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, exec_lo
-// CHECK: [0x7e,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, exec_hi
-// CHECK: [0x7f,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, 0
-// CHECK: [0x80,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, -1
-// CHECK: [0xc1,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, 0.5
-// CHECK: [0xf0,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, -4.0
-// CHECK: [0xf7,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, 0xaf123456
-// CHECK: [0xff,0x36,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_fract_f32 v5, 0x3f717273
-// CHECK: [0xff,0x36,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_fract_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5b,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5b,0xd1,0xff,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5b,0xd1,0x65,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5b,0xd1,0x66,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5b,0xd1,0x67,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x5b,0xd1,0x6c,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x5b,0xd1,0x6d,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x5b,0xd1,0x6e,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x5b,0xd1,0x6f,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x5b,0xd1,0x7b,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5b,0xd1,0x80,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x20]
-
-v_fract_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5b,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x08]
-
-v_fract_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x10]
-
-v_fract_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x18]
-
-v_trunc_f32 v5, v1
-// CHECK: [0x01,0x39,0x0a,0x7e]
-
-v_trunc_f32 v255, v1
-// CHECK: [0x01,0x39,0xfe,0x7f]
-
-v_trunc_f32 v5, v255
-// CHECK: [0xff,0x39,0x0a,0x7e]
-
-v_trunc_f32 v5, s1
-// CHECK: [0x01,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, s101
-// CHECK: [0x65,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, vcc_lo
-// CHECK: [0x6a,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, vcc_hi
-// CHECK: [0x6b,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, tba_lo
-// CHECK: [0x6c,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, tba_hi
-// CHECK: [0x6d,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, tma_lo
-// CHECK: [0x6e,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, tma_hi
-// CHECK: [0x6f,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, ttmp11
-// CHECK: [0x7b,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, m0
-// CHECK: [0x7c,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, exec_lo
-// CHECK: [0x7e,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, exec_hi
-// CHECK: [0x7f,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, 0
-// CHECK: [0x80,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, -1
-// CHECK: [0xc1,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, 0.5
-// CHECK: [0xf0,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, -4.0
-// CHECK: [0xf7,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, 0xaf123456
-// CHECK: [0xff,0x38,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_trunc_f32 v5, 0x3f717273
-// CHECK: [0xff,0x38,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_trunc_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5c,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5c,0xd1,0xff,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5c,0xd1,0x65,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5c,0xd1,0x66,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5c,0xd1,0x67,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x5c,0xd1,0x6c,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x5c,0xd1,0x6d,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x5c,0xd1,0x6e,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x5c,0xd1,0x6f,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x5c,0xd1,0x7b,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5c,0xd1,0x80,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x20]
-
-v_trunc_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5c,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x08]
-
-v_trunc_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x10]
-
-v_trunc_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x18]
-
-v_ceil_f32 v5, v1
-// CHECK: [0x01,0x3b,0x0a,0x7e]
-
-v_ceil_f32 v255, v1
-// CHECK: [0x01,0x3b,0xfe,0x7f]
-
-v_ceil_f32 v5, v255
-// CHECK: [0xff,0x3b,0x0a,0x7e]
-
-v_ceil_f32 v5, s1
-// CHECK: [0x01,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, s101
-// CHECK: [0x65,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, vcc_lo
-// CHECK: [0x6a,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, vcc_hi
-// CHECK: [0x6b,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, tba_lo
-// CHECK: [0x6c,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, tba_hi
-// CHECK: [0x6d,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, tma_lo
-// CHECK: [0x6e,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, tma_hi
-// CHECK: [0x6f,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, ttmp11
-// CHECK: [0x7b,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, m0
-// CHECK: [0x7c,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, exec_lo
-// CHECK: [0x7e,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, exec_hi
-// CHECK: [0x7f,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, 0
-// CHECK: [0x80,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, -1
-// CHECK: [0xc1,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, 0.5
-// CHECK: [0xf0,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, -4.0
-// CHECK: [0xf7,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, 0xaf123456
-// CHECK: [0xff,0x3a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ceil_f32 v5, 0x3f717273
-// CHECK: [0xff,0x3a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ceil_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5d,0xd1,0xff,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5d,0xd1,0x65,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5d,0xd1,0x66,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5d,0xd1,0x67,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5d,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5d,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x5d,0xd1,0x6c,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x5d,0xd1,0x6d,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x5d,0xd1,0x6e,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x5d,0xd1,0x6f,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x5d,0xd1,0x7b,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5d,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5d,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5d,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5d,0xd1,0x80,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5d,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5d,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x20]
-
-v_ceil_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x08]
-
-v_ceil_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x10]
-
-v_ceil_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x18]
-
-v_rndne_f32 v5, v1
-// CHECK: [0x01,0x3d,0x0a,0x7e]
-
-v_rndne_f32 v255, v1
-// CHECK: [0x01,0x3d,0xfe,0x7f]
-
-v_rndne_f32 v5, v255
-// CHECK: [0xff,0x3d,0x0a,0x7e]
-
-v_rndne_f32 v5, s1
-// CHECK: [0x01,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, s101
-// CHECK: [0x65,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, vcc_lo
-// CHECK: [0x6a,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, vcc_hi
-// CHECK: [0x6b,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, tba_lo
-// CHECK: [0x6c,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, tba_hi
-// CHECK: [0x6d,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, tma_lo
-// CHECK: [0x6e,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, tma_hi
-// CHECK: [0x6f,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, ttmp11
-// CHECK: [0x7b,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, m0
-// CHECK: [0x7c,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, exec_lo
-// CHECK: [0x7e,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, exec_hi
-// CHECK: [0x7f,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, 0
-// CHECK: [0x80,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, -1
-// CHECK: [0xc1,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, 0.5
-// CHECK: [0xf0,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, -4.0
-// CHECK: [0xf7,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, 0xaf123456
-// CHECK: [0xff,0x3c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rndne_f32 v5, 0x3f717273
-// CHECK: [0xff,0x3c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rndne_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5e,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5e,0xd1,0xff,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5e,0xd1,0x65,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5e,0xd1,0x66,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5e,0xd1,0x67,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5e,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5e,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x5e,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x5e,0xd1,0x6d,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x5e,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x5e,0xd1,0x6f,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x5e,0xd1,0x7b,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5e,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5e,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5e,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5e,0xd1,0x80,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5e,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5e,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5e,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x20]
-
-v_rndne_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5e,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x08]
-
-v_rndne_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x10]
-
-v_rndne_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x18]
-
-v_floor_f32 v5, v1
-// CHECK: [0x01,0x3f,0x0a,0x7e]
-
-v_floor_f32 v255, v1
-// CHECK: [0x01,0x3f,0xfe,0x7f]
-
-v_floor_f32 v5, v255
-// CHECK: [0xff,0x3f,0x0a,0x7e]
-
-v_floor_f32 v5, s1
-// CHECK: [0x01,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, s101
-// CHECK: [0x65,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, vcc_lo
-// CHECK: [0x6a,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, vcc_hi
-// CHECK: [0x6b,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, tba_lo
-// CHECK: [0x6c,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, tba_hi
-// CHECK: [0x6d,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, tma_lo
-// CHECK: [0x6e,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, tma_hi
-// CHECK: [0x6f,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, ttmp11
-// CHECK: [0x7b,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, m0
-// CHECK: [0x7c,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, exec_lo
-// CHECK: [0x7e,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, exec_hi
-// CHECK: [0x7f,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, 0
-// CHECK: [0x80,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, -1
-// CHECK: [0xc1,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, 0.5
-// CHECK: [0xf0,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, -4.0
-// CHECK: [0xf7,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, 0xaf123456
-// CHECK: [0xff,0x3e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_floor_f32 v5, 0x3f717273
-// CHECK: [0xff,0x3e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_floor_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5f,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5f,0xd1,0xff,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5f,0xd1,0x65,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5f,0xd1,0x66,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5f,0xd1,0x67,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5f,0xd1,0x6a,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5f,0xd1,0x6b,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x5f,0xd1,0x6c,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x5f,0xd1,0x6d,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x5f,0xd1,0x6e,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x5f,0xd1,0x6f,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x5f,0xd1,0x7b,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5f,0xd1,0x7c,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5f,0xd1,0x7e,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5f,0xd1,0x7f,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5f,0xd1,0x80,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5f,0xd1,0xc1,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5f,0xd1,0xf0,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5f,0xd1,0xf7,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x20]
-
-v_floor_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x5f,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5f,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x08]
-
-v_floor_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x10]
-
-v_floor_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x18]
-
-v_exp_f32 v5, v1
-// CHECK: [0x01,0x41,0x0a,0x7e]
-
-v_exp_f32 v255, v1
-// CHECK: [0x01,0x41,0xfe,0x7f]
-
-v_exp_f32 v5, v255
-// CHECK: [0xff,0x41,0x0a,0x7e]
-
-v_exp_f32 v5, s1
-// CHECK: [0x01,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, s101
-// CHECK: [0x65,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, vcc_lo
-// CHECK: [0x6a,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, vcc_hi
-// CHECK: [0x6b,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, tba_lo
-// CHECK: [0x6c,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, tba_hi
-// CHECK: [0x6d,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, tma_lo
-// CHECK: [0x6e,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, tma_hi
-// CHECK: [0x6f,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, ttmp11
-// CHECK: [0x7b,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, m0
-// CHECK: [0x7c,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, exec_lo
-// CHECK: [0x7e,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, exec_hi
-// CHECK: [0x7f,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, 0
-// CHECK: [0x80,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, -1
-// CHECK: [0xc1,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, 0.5
-// CHECK: [0xf0,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, -4.0
-// CHECK: [0xf7,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, 0xaf123456
-// CHECK: [0xff,0x40,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_exp_f32 v5, 0x3f717273
-// CHECK: [0xff,0x40,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_exp_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x60,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x60,0xd1,0xff,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x60,0xd1,0x65,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x60,0xd1,0x66,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x60,0xd1,0x67,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x60,0xd1,0x6a,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x60,0xd1,0x6b,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x60,0xd1,0x6c,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x60,0xd1,0x6d,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x60,0xd1,0x6e,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x60,0xd1,0x6f,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x60,0xd1,0x7b,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x60,0xd1,0x7c,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x60,0xd1,0x7e,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x60,0xd1,0x7f,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x60,0xd1,0x80,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x60,0xd1,0xc1,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x60,0xd1,0xf0,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x60,0xd1,0xf7,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x20]
-
-v_exp_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x60,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x60,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x08]
-
-v_exp_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x10]
-
-v_exp_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x18]
-
-v_log_f32 v5, v1
-// CHECK: [0x01,0x43,0x0a,0x7e]
-
-v_log_f32 v255, v1
-// CHECK: [0x01,0x43,0xfe,0x7f]
-
-v_log_f32 v5, v255
-// CHECK: [0xff,0x43,0x0a,0x7e]
-
-v_log_f32 v5, s1
-// CHECK: [0x01,0x42,0x0a,0x7e]
-
-v_log_f32 v5, s101
-// CHECK: [0x65,0x42,0x0a,0x7e]
-
-v_log_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x42,0x0a,0x7e]
-
-v_log_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x42,0x0a,0x7e]
-
-v_log_f32 v5, vcc_lo
-// CHECK: [0x6a,0x42,0x0a,0x7e]
-
-v_log_f32 v5, vcc_hi
-// CHECK: [0x6b,0x42,0x0a,0x7e]
-
-v_log_f32 v5, tba_lo
-// CHECK: [0x6c,0x42,0x0a,0x7e]
-
-v_log_f32 v5, tba_hi
-// CHECK: [0x6d,0x42,0x0a,0x7e]
-
-v_log_f32 v5, tma_lo
-// CHECK: [0x6e,0x42,0x0a,0x7e]
-
-v_log_f32 v5, tma_hi
-// CHECK: [0x6f,0x42,0x0a,0x7e]
-
-v_log_f32 v5, ttmp11
-// CHECK: [0x7b,0x42,0x0a,0x7e]
-
-v_log_f32 v5, m0
-// CHECK: [0x7c,0x42,0x0a,0x7e]
-
-v_log_f32 v5, exec_lo
-// CHECK: [0x7e,0x42,0x0a,0x7e]
-
-v_log_f32 v5, exec_hi
-// CHECK: [0x7f,0x42,0x0a,0x7e]
-
-v_log_f32 v5, 0
-// CHECK: [0x80,0x42,0x0a,0x7e]
-
-v_log_f32 v5, -1
-// CHECK: [0xc1,0x42,0x0a,0x7e]
-
-v_log_f32 v5, 0.5
-// CHECK: [0xf0,0x42,0x0a,0x7e]
-
-v_log_f32 v5, -4.0
-// CHECK: [0xf7,0x42,0x0a,0x7e]
-
-v_log_f32 v5, 0xaf123456
-// CHECK: [0xff,0x42,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_log_f32 v5, 0x3f717273
-// CHECK: [0xff,0x42,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_log_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x61,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x61,0xd1,0xff,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x61,0xd1,0x65,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x61,0xd1,0x66,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x61,0xd1,0x67,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x61,0xd1,0x6a,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x61,0xd1,0x6b,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x61,0xd1,0x6c,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x61,0xd1,0x6d,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x61,0xd1,0x6e,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x61,0xd1,0x6f,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x61,0xd1,0x7b,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x61,0xd1,0x7c,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x61,0xd1,0x7e,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x61,0xd1,0x7f,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x61,0xd1,0x80,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x61,0xd1,0xc1,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x61,0xd1,0xf0,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x61,0xd1,0xf7,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x20]
-
-v_log_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x61,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x61,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x08]
-
-v_log_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x10]
-
-v_log_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x18]
-
-v_rcp_f32 v5, v1
-// CHECK: [0x01,0x45,0x0a,0x7e]
-
-v_rcp_f32 v255, v1
-// CHECK: [0x01,0x45,0xfe,0x7f]
-
-v_rcp_f32 v5, v255
-// CHECK: [0xff,0x45,0x0a,0x7e]
-
-v_rcp_f32 v5, s1
-// CHECK: [0x01,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, s101
-// CHECK: [0x65,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, vcc_lo
-// CHECK: [0x6a,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, vcc_hi
-// CHECK: [0x6b,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, tba_lo
-// CHECK: [0x6c,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, tba_hi
-// CHECK: [0x6d,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, tma_lo
-// CHECK: [0x6e,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, tma_hi
-// CHECK: [0x6f,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, ttmp11
-// CHECK: [0x7b,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, m0
-// CHECK: [0x7c,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, exec_lo
-// CHECK: [0x7e,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, exec_hi
-// CHECK: [0x7f,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, 0
-// CHECK: [0x80,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, -1
-// CHECK: [0xc1,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, 0.5
-// CHECK: [0xf0,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, -4.0
-// CHECK: [0xf7,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, 0xaf123456
-// CHECK: [0xff,0x44,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_f32 v5, 0x3f717273
-// CHECK: [0xff,0x44,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x62,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x62,0xd1,0xff,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x62,0xd1,0x65,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x62,0xd1,0x66,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x62,0xd1,0x67,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x62,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x62,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x62,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x62,0xd1,0x6d,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x62,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x62,0xd1,0x6f,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x62,0xd1,0x7b,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x62,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x62,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x62,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x62,0xd1,0x80,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x62,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x62,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x62,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x20]
-
-v_rcp_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x62,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x62,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x08]
-
-v_rcp_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x10]
-
-v_rcp_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x18]
-
-v_rcp_iflag_f32 v5, v1
-// CHECK: [0x01,0x47,0x0a,0x7e]
-
-v_rcp_iflag_f32 v255, v1
-// CHECK: [0x01,0x47,0xfe,0x7f]
-
-v_rcp_iflag_f32 v5, v255
-// CHECK: [0xff,0x47,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, s1
-// CHECK: [0x01,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, s101
-// CHECK: [0x65,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, vcc_lo
-// CHECK: [0x6a,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, vcc_hi
-// CHECK: [0x6b,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, tba_lo
-// CHECK: [0x6c,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, tba_hi
-// CHECK: [0x6d,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, tma_lo
-// CHECK: [0x6e,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, tma_hi
-// CHECK: [0x6f,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, ttmp11
-// CHECK: [0x7b,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, m0
-// CHECK: [0x7c,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, exec_lo
-// CHECK: [0x7e,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, exec_hi
-// CHECK: [0x7f,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0
-// CHECK: [0x80,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, -1
-// CHECK: [0xc1,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0.5
-// CHECK: [0xf0,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, -4.0
-// CHECK: [0xf7,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0xaf123456
-// CHECK: [0xff,0x46,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_iflag_f32 v5, 0x3f717273
-// CHECK: [0xff,0x46,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_iflag_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x63,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x63,0xd1,0xff,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x63,0xd1,0x65,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x63,0xd1,0x66,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x63,0xd1,0x67,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x63,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x63,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x63,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x63,0xd1,0x6d,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x63,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x63,0xd1,0x6f,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x63,0xd1,0x7b,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x63,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x63,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x63,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x63,0xd1,0x80,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x63,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x63,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x63,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x20]
-
-v_rcp_iflag_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x63,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x63,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x08]
-
-v_rcp_iflag_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x10]
-
-v_rcp_iflag_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x18]
-
-v_rsq_f32 v5, v1
-// CHECK: [0x01,0x49,0x0a,0x7e]
-
-v_rsq_f32 v255, v1
-// CHECK: [0x01,0x49,0xfe,0x7f]
-
-v_rsq_f32 v5, v255
-// CHECK: [0xff,0x49,0x0a,0x7e]
-
-v_rsq_f32 v5, s1
-// CHECK: [0x01,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, s101
-// CHECK: [0x65,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, vcc_lo
-// CHECK: [0x6a,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, vcc_hi
-// CHECK: [0x6b,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, tba_lo
-// CHECK: [0x6c,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, tba_hi
-// CHECK: [0x6d,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, tma_lo
-// CHECK: [0x6e,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, tma_hi
-// CHECK: [0x6f,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, ttmp11
-// CHECK: [0x7b,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, m0
-// CHECK: [0x7c,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, exec_lo
-// CHECK: [0x7e,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, exec_hi
-// CHECK: [0x7f,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, 0
-// CHECK: [0x80,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, -1
-// CHECK: [0xc1,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, 0.5
-// CHECK: [0xf0,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, -4.0
-// CHECK: [0xf7,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, 0xaf123456
-// CHECK: [0xff,0x48,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_f32 v5, 0x3f717273
-// CHECK: [0xff,0x48,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x64,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x64,0xd1,0xff,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x64,0xd1,0x65,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x64,0xd1,0x66,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x64,0xd1,0x67,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x64,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x64,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x64,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x64,0xd1,0x6d,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x64,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x64,0xd1,0x6f,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x64,0xd1,0x7b,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x64,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x64,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x64,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x64,0xd1,0x80,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x64,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x64,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x64,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x20]
-
-v_rsq_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x64,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x64,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x08]
-
-v_rsq_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x10]
-
-v_rsq_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x18]
-
-v_rcp_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x4b,0x0a,0x7e]
-
-v_rcp_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x4b,0xfc,0x7f]
-
-v_rcp_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x4b,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], vcc
-// CHECK: [0x6a,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], tba
-// CHECK: [0x6c,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], tma
-// CHECK: [0x6e,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], exec
-// CHECK: [0x7e,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0
-// CHECK: [0x80,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], -1
-// CHECK: [0xc1,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x4a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x4a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x65,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x65,0xd1,0xfe,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x65,0xd1,0x02,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x65,0xd1,0x04,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x65,0xd1,0x64,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x65,0xd1,0x66,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x65,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x65,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x65,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x65,0xd1,0x7a,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x65,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x65,0xd1,0x80,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x65,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x65,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x65,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x20]
-
-v_rcp_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x65,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x65,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x08]
-
-v_rcp_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x10]
-
-v_rcp_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x18]
-
-v_rsq_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x4d,0x0a,0x7e]
-
-v_rsq_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x4d,0xfc,0x7f]
-
-v_rsq_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x4d,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], vcc
-// CHECK: [0x6a,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], tba
-// CHECK: [0x6c,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], tma
-// CHECK: [0x6e,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], exec
-// CHECK: [0x7e,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0
-// CHECK: [0x80,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], -1
-// CHECK: [0xc1,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x4c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x4c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x66,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x66,0xd1,0xfe,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x66,0xd1,0x02,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x66,0xd1,0x04,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x66,0xd1,0x64,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x66,0xd1,0x66,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x66,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x66,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x66,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x66,0xd1,0x7a,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x66,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x66,0xd1,0x80,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x66,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x66,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x66,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x20]
-
-v_rsq_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x66,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x66,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x08]
-
-v_rsq_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x10]
-
-v_rsq_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x18]
-
-v_sqrt_f32 v5, v1
-// CHECK: [0x01,0x4f,0x0a,0x7e]
-
-v_sqrt_f32 v255, v1
-// CHECK: [0x01,0x4f,0xfe,0x7f]
-
-v_sqrt_f32 v5, v255
-// CHECK: [0xff,0x4f,0x0a,0x7e]
-
-v_sqrt_f32 v5, s1
-// CHECK: [0x01,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, s101
-// CHECK: [0x65,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, vcc_lo
-// CHECK: [0x6a,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, vcc_hi
-// CHECK: [0x6b,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, tba_lo
-// CHECK: [0x6c,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, tba_hi
-// CHECK: [0x6d,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, tma_lo
-// CHECK: [0x6e,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, tma_hi
-// CHECK: [0x6f,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, ttmp11
-// CHECK: [0x7b,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, m0
-// CHECK: [0x7c,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, exec_lo
-// CHECK: [0x7e,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, exec_hi
-// CHECK: [0x7f,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0
-// CHECK: [0x80,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, -1
-// CHECK: [0xc1,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0.5
-// CHECK: [0xf0,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, -4.0
-// CHECK: [0xf7,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0xaf123456
-// CHECK: [0xff,0x4e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sqrt_f32 v5, 0x3f717273
-// CHECK: [0xff,0x4e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sqrt_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x67,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x67,0xd1,0xff,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x67,0xd1,0x65,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x67,0xd1,0x66,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x67,0xd1,0x67,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x67,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x67,0xd1,0x6b,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x67,0xd1,0x6c,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x67,0xd1,0x6d,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x67,0xd1,0x6e,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x67,0xd1,0x6f,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x67,0xd1,0x7b,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x67,0xd1,0x7c,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x67,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x67,0xd1,0x7f,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x67,0xd1,0x80,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x67,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x67,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x67,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x20]
-
-v_sqrt_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x67,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x67,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x08]
-
-v_sqrt_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x10]
-
-v_sqrt_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x18]
-
-v_sqrt_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x51,0x0a,0x7e]
-
-v_sqrt_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x51,0xfc,0x7f]
-
-v_sqrt_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x51,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], vcc
-// CHECK: [0x6a,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], tba
-// CHECK: [0x6c,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], tma
-// CHECK: [0x6e,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], exec
-// CHECK: [0x7e,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0
-// CHECK: [0x80,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], -1
-// CHECK: [0xc1,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x50,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sqrt_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x50,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sqrt_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x68,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x68,0xd1,0xfe,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x68,0xd1,0x02,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x68,0xd1,0x04,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x68,0xd1,0x64,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x68,0xd1,0x66,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x68,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x68,0xd1,0x6c,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x68,0xd1,0x6e,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x68,0xd1,0x7a,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x68,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x68,0xd1,0x80,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x68,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x68,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x68,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x20]
-
-v_sqrt_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x68,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x68,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x08]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x10]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x18]
-
-v_sin_f32 v5, v1
-// CHECK: [0x01,0x53,0x0a,0x7e]
-
-v_sin_f32 v255, v1
-// CHECK: [0x01,0x53,0xfe,0x7f]
-
-v_sin_f32 v5, v255
-// CHECK: [0xff,0x53,0x0a,0x7e]
-
-v_sin_f32 v5, s1
-// CHECK: [0x01,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, s101
-// CHECK: [0x65,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, vcc_lo
-// CHECK: [0x6a,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, vcc_hi
-// CHECK: [0x6b,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, tba_lo
-// CHECK: [0x6c,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, tba_hi
-// CHECK: [0x6d,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, tma_lo
-// CHECK: [0x6e,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, tma_hi
-// CHECK: [0x6f,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, ttmp11
-// CHECK: [0x7b,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, m0
-// CHECK: [0x7c,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, exec_lo
-// CHECK: [0x7e,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, exec_hi
-// CHECK: [0x7f,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, 0
-// CHECK: [0x80,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, -1
-// CHECK: [0xc1,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, 0.5
-// CHECK: [0xf0,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, -4.0
-// CHECK: [0xf7,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, 0xaf123456
-// CHECK: [0xff,0x52,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sin_f32 v5, 0x3f717273
-// CHECK: [0xff,0x52,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sin_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x69,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x69,0xd1,0xff,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x69,0xd1,0x65,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x69,0xd1,0x66,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x69,0xd1,0x67,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x69,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x69,0xd1,0x6b,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x69,0xd1,0x6c,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x69,0xd1,0x6d,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x69,0xd1,0x6e,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x69,0xd1,0x6f,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x69,0xd1,0x7b,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x69,0xd1,0x7c,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x69,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x69,0xd1,0x7f,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x69,0xd1,0x80,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x69,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x69,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x69,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x20]
-
-v_sin_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x69,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x69,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x08]
-
-v_sin_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x10]
-
-v_sin_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x18]
-
-v_cos_f32 v5, v1
-// CHECK: [0x01,0x55,0x0a,0x7e]
-
-v_cos_f32 v255, v1
-// CHECK: [0x01,0x55,0xfe,0x7f]
-
-v_cos_f32 v5, v255
-// CHECK: [0xff,0x55,0x0a,0x7e]
-
-v_cos_f32 v5, s1
-// CHECK: [0x01,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, s101
-// CHECK: [0x65,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, vcc_lo
-// CHECK: [0x6a,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, vcc_hi
-// CHECK: [0x6b,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, tba_lo
-// CHECK: [0x6c,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, tba_hi
-// CHECK: [0x6d,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, tma_lo
-// CHECK: [0x6e,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, tma_hi
-// CHECK: [0x6f,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, ttmp11
-// CHECK: [0x7b,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, m0
-// CHECK: [0x7c,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, exec_lo
-// CHECK: [0x7e,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, exec_hi
-// CHECK: [0x7f,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, 0
-// CHECK: [0x80,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, -1
-// CHECK: [0xc1,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, 0.5
-// CHECK: [0xf0,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, -4.0
-// CHECK: [0xf7,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, 0xaf123456
-// CHECK: [0xff,0x54,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cos_f32 v5, 0x3f717273
-// CHECK: [0xff,0x54,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cos_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6a,0xd1,0xff,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6a,0xd1,0x65,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6a,0xd1,0x66,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6a,0xd1,0x67,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6a,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x6a,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x6a,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x6a,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x6a,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x6a,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6a,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6a,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6a,0xd1,0x80,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6a,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6a,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x20]
-
-v_cos_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x6a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x6a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x08]
-
-v_cos_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x10]
-
-v_cos_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x18]
-
-v_not_b32 v5, v1
-// CHECK: [0x01,0x57,0x0a,0x7e]
-
-v_not_b32 v255, v1
-// CHECK: [0x01,0x57,0xfe,0x7f]
-
-v_not_b32 v5, v255
-// CHECK: [0xff,0x57,0x0a,0x7e]
-
-v_not_b32 v5, s1
-// CHECK: [0x01,0x56,0x0a,0x7e]
-
-v_not_b32 v5, s101
-// CHECK: [0x65,0x56,0x0a,0x7e]
-
-v_not_b32 v5, flat_scratch_lo
-// CHECK: [0x66,0x56,0x0a,0x7e]
-
-v_not_b32 v5, flat_scratch_hi
-// CHECK: [0x67,0x56,0x0a,0x7e]
-
-v_not_b32 v5, vcc_lo
-// CHECK: [0x6a,0x56,0x0a,0x7e]
-
-v_not_b32 v5, vcc_hi
-// CHECK: [0x6b,0x56,0x0a,0x7e]
-
-v_not_b32 v5, tba_lo
-// CHECK: [0x6c,0x56,0x0a,0x7e]
-
-v_not_b32 v5, tba_hi
-// CHECK: [0x6d,0x56,0x0a,0x7e]
-
-v_not_b32 v5, tma_lo
-// CHECK: [0x6e,0x56,0x0a,0x7e]
-
-v_not_b32 v5, tma_hi
-// CHECK: [0x6f,0x56,0x0a,0x7e]
-
-v_not_b32 v5, ttmp11
-// CHECK: [0x7b,0x56,0x0a,0x7e]
-
-v_not_b32 v5, m0
-// CHECK: [0x7c,0x56,0x0a,0x7e]
-
-v_not_b32 v5, exec_lo
-// CHECK: [0x7e,0x56,0x0a,0x7e]
-
-v_not_b32 v5, exec_hi
-// CHECK: [0x7f,0x56,0x0a,0x7e]
-
-v_not_b32 v5, 0
-// CHECK: [0x80,0x56,0x0a,0x7e]
-
-v_not_b32 v5, -1
-// CHECK: [0xc1,0x56,0x0a,0x7e]
-
-v_not_b32 v5, 0.5
-// CHECK: [0xf0,0x56,0x0a,0x7e]
-
-v_not_b32 v5, -4.0
-// CHECK: [0xf7,0x56,0x0a,0x7e]
-
-v_not_b32 v5, 0xaf123456
-// CHECK: [0xff,0x56,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_not_b32 v5, 0x3f717273
-// CHECK: [0xff,0x56,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_not_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
-
-v_not_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
-
-v_not_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6b,0xd1,0xff,0x01,0x00,0x00]
-
-v_not_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6b,0xd1,0x01,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6b,0xd1,0x65,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6b,0xd1,0x66,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6b,0xd1,0x67,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x6b,0xd1,0x6c,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x6b,0xd1,0x6d,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x6b,0xd1,0x6e,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x6b,0xd1,0x6f,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x6b,0xd1,0x7b,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6b,0xd1,0x80,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_bfrev_b32 v5, v1
-// CHECK: [0x01,0x59,0x0a,0x7e]
-
-v_bfrev_b32 v255, v1
-// CHECK: [0x01,0x59,0xfe,0x7f]
-
-v_bfrev_b32 v5, v255
-// CHECK: [0xff,0x59,0x0a,0x7e]
-
-v_bfrev_b32 v5, s1
-// CHECK: [0x01,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, s101
-// CHECK: [0x65,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, flat_scratch_lo
-// CHECK: [0x66,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, flat_scratch_hi
-// CHECK: [0x67,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, vcc_lo
-// CHECK: [0x6a,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, vcc_hi
-// CHECK: [0x6b,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, tba_lo
-// CHECK: [0x6c,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, tba_hi
-// CHECK: [0x6d,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, tma_lo
-// CHECK: [0x6e,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, tma_hi
-// CHECK: [0x6f,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, ttmp11
-// CHECK: [0x7b,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, m0
-// CHECK: [0x7c,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, exec_lo
-// CHECK: [0x7e,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, exec_hi
-// CHECK: [0x7f,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0
-// CHECK: [0x80,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, -1
-// CHECK: [0xc1,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0.5
-// CHECK: [0xf0,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, -4.0
-// CHECK: [0xf7,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0xaf123456
-// CHECK: [0xff,0x58,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_bfrev_b32 v5, 0x3f717273
-// CHECK: [0xff,0x58,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_bfrev_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6c,0xd1,0x01,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6c,0xd1,0x01,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6c,0xd1,0xff,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6c,0xd1,0x01,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6c,0xd1,0x65,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6c,0xd1,0x66,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6c,0xd1,0x67,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x6c,0xd1,0x6c,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x6c,0xd1,0x6d,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x6c,0xd1,0x6e,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x6c,0xd1,0x6f,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x6c,0xd1,0x7b,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6c,0xd1,0x80,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ffbh_u32 v5, v1
-// CHECK: [0x01,0x5b,0x0a,0x7e]
-
-v_ffbh_u32 v255, v1
-// CHECK: [0x01,0x5b,0xfe,0x7f]
-
-v_ffbh_u32 v5, v255
-// CHECK: [0xff,0x5b,0x0a,0x7e]
-
-v_ffbh_u32 v5, s1
-// CHECK: [0x01,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, s101
-// CHECK: [0x65,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, flat_scratch_lo
-// CHECK: [0x66,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, flat_scratch_hi
-// CHECK: [0x67,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, vcc_lo
-// CHECK: [0x6a,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, vcc_hi
-// CHECK: [0x6b,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, tba_lo
-// CHECK: [0x6c,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, tba_hi
-// CHECK: [0x6d,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, tma_lo
-// CHECK: [0x6e,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, tma_hi
-// CHECK: [0x6f,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, ttmp11
-// CHECK: [0x7b,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, m0
-// CHECK: [0x7c,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, exec_lo
-// CHECK: [0x7e,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, exec_hi
-// CHECK: [0x7f,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0
-// CHECK: [0x80,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, -1
-// CHECK: [0xc1,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0.5
-// CHECK: [0xf0,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, -4.0
-// CHECK: [0xf7,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0xaf123456
-// CHECK: [0xff,0x5a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbh_u32 v5, 0x3f717273
-// CHECK: [0xff,0x5a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbh_u32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6d,0xd1,0xff,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6d,0xd1,0x01,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6d,0xd1,0x65,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6d,0xd1,0x66,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6d,0xd1,0x67,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6d,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6d,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x6d,0xd1,0x6c,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x6d,0xd1,0x6d,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x6d,0xd1,0x6e,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x6d,0xd1,0x6f,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x6d,0xd1,0x7b,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6d,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6d,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6d,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6d,0xd1,0x80,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6d,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6d,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6d,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ffbl_b32 v5, v1
-// CHECK: [0x01,0x5d,0x0a,0x7e]
-
-v_ffbl_b32 v255, v1
-// CHECK: [0x01,0x5d,0xfe,0x7f]
-
-v_ffbl_b32 v5, v255
-// CHECK: [0xff,0x5d,0x0a,0x7e]
-
-v_ffbl_b32 v5, s1
-// CHECK: [0x01,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, s101
-// CHECK: [0x65,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, flat_scratch_lo
-// CHECK: [0x66,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, flat_scratch_hi
-// CHECK: [0x67,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, vcc_lo
-// CHECK: [0x6a,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, vcc_hi
-// CHECK: [0x6b,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, tba_lo
-// CHECK: [0x6c,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, tba_hi
-// CHECK: [0x6d,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, tma_lo
-// CHECK: [0x6e,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, tma_hi
-// CHECK: [0x6f,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, ttmp11
-// CHECK: [0x7b,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, m0
-// CHECK: [0x7c,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, exec_lo
-// CHECK: [0x7e,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, exec_hi
-// CHECK: [0x7f,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0
-// CHECK: [0x80,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, -1
-// CHECK: [0xc1,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0.5
-// CHECK: [0xf0,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, -4.0
-// CHECK: [0xf7,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0xaf123456
-// CHECK: [0xff,0x5c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbl_b32 v5, 0x3f717273
-// CHECK: [0xff,0x5c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbl_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6e,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6e,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6e,0xd1,0xff,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6e,0xd1,0x01,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6e,0xd1,0x65,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6e,0xd1,0x66,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6e,0xd1,0x67,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6e,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6e,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x6e,0xd1,0x6c,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x6e,0xd1,0x6d,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x6e,0xd1,0x6e,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x6e,0xd1,0x6f,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x6e,0xd1,0x7b,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6e,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6e,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6e,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6e,0xd1,0x80,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6e,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6e,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6e,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ffbh_i32 v5, v1
-// CHECK: [0x01,0x5f,0x0a,0x7e]
-
-v_ffbh_i32 v255, v1
-// CHECK: [0x01,0x5f,0xfe,0x7f]
-
-v_ffbh_i32 v5, v255
-// CHECK: [0xff,0x5f,0x0a,0x7e]
-
-v_ffbh_i32 v5, s1
-// CHECK: [0x01,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, s101
-// CHECK: [0x65,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, flat_scratch_lo
-// CHECK: [0x66,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, flat_scratch_hi
-// CHECK: [0x67,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, vcc_lo
-// CHECK: [0x6a,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, vcc_hi
-// CHECK: [0x6b,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, tba_lo
-// CHECK: [0x6c,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, tba_hi
-// CHECK: [0x6d,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, tma_lo
-// CHECK: [0x6e,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, tma_hi
-// CHECK: [0x6f,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, ttmp11
-// CHECK: [0x7b,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, m0
-// CHECK: [0x7c,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, exec_lo
-// CHECK: [0x7e,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, exec_hi
-// CHECK: [0x7f,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0
-// CHECK: [0x80,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, -1
-// CHECK: [0xc1,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0.5
-// CHECK: [0xf0,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, -4.0
-// CHECK: [0xf7,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0xaf123456
-// CHECK: [0xff,0x5e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbh_i32 v5, 0x3f717273
-// CHECK: [0xff,0x5e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbh_i32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6f,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6f,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6f,0xd1,0xff,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6f,0xd1,0x01,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6f,0xd1,0x65,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6f,0xd1,0x66,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6f,0xd1,0x67,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6f,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6f,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x6f,0xd1,0x6c,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x6f,0xd1,0x6d,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x6f,0xd1,0x6e,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x6f,0xd1,0x6f,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x6f,0xd1,0x7b,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6f,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6f,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6f,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6f,0xd1,0x80,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6f,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6f,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6f,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64 v5, v[1:2]
-// CHECK: [0x01,0x61,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v255, v[1:2]
-// CHECK: [0x01,0x61,0xfe,0x7f]
-
-v_frexp_exp_i32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x61,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[2:3]
-// CHECK: [0x02,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[4:5]
-// CHECK: [0x04,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[100:101]
-// CHECK: [0x64,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, flat_scratch
-// CHECK: [0x66,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, vcc
-// CHECK: [0x6a,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, tba
-// CHECK: [0x6c,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, tma
-// CHECK: [0x6e,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, ttmp[10:11]
-// CHECK: [0x7a,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, exec
-// CHECK: [0x7e,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0
-// CHECK: [0x80,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, -1
-// CHECK: [0xc1,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0.5
-// CHECK: [0xf0,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, -4.0
-// CHECK: [0xf7,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x60,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_exp_i32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x60,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_exp_i32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x70,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x70,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x70,0xd1,0xfe,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x70,0xd1,0x02,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x70,0xd1,0x04,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[100:101]
-// CHECK: [0x05,0x00,0x70,0xd1,0x64,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x70,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x70,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, tba
-// CHECK: [0x05,0x00,0x70,0xd1,0x6c,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, tma
-// CHECK: [0x05,0x00,0x70,0xd1,0x6e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, ttmp[10:11]
-// CHECK: [0x05,0x00,0x70,0xd1,0x7a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x70,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x70,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x70,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x70,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x70,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x70,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x70,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x63,0x0a,0x7e]
-
-v_frexp_mant_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x63,0xfc,0x7f]
-
-v_frexp_mant_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x63,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], vcc
-// CHECK: [0x6a,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], tba
-// CHECK: [0x6c,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], tma
-// CHECK: [0x6e,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], exec
-// CHECK: [0x7e,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0
-// CHECK: [0x80,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], -1
-// CHECK: [0xc1,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x62,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_mant_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x62,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x71,0xd1,0xfe,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x71,0xd1,0x02,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x71,0xd1,0x04,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x71,0xd1,0x64,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x71,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x71,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x71,0xd1,0x6c,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x71,0xd1,0x6e,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x71,0xd1,0x7a,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x71,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x71,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x71,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x71,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x71,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x71,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x71,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x08]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x10]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x18]
-
-v_fract_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x65,0x0a,0x7e]
-
-v_fract_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x65,0xfc,0x7f]
-
-v_fract_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x65,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], vcc
-// CHECK: [0x6a,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], tba
-// CHECK: [0x6c,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], tma
-// CHECK: [0x6e,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], ttmp[10:11]
-// CHECK: [0x7a,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], exec
-// CHECK: [0x7e,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0
-// CHECK: [0x80,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], -1
-// CHECK: [0xc1,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x64,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_fract_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x64,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_fract_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x72,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x72,0xd1,0xfe,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x72,0xd1,0x04,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x72,0xd1,0x64,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x72,0xd1,0x66,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x72,0xd1,0x6a,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], tba
-// CHECK: [0x05,0x00,0x72,0xd1,0x6c,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], tma
-// CHECK: [0x05,0x00,0x72,0xd1,0x6e,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], ttmp[10:11]
-// CHECK: [0x05,0x00,0x72,0xd1,0x7a,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x72,0xd1,0x7e,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x72,0xd1,0x80,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x72,0xd1,0xc1,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x72,0xd1,0xf0,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x72,0xd1,0xf7,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x20]
-
-v_fract_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x72,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x72,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x08]
-
-v_fract_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x10]
-
-v_fract_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x18]
-
-v_frexp_exp_i32_f32 v5, v1
-// CHECK: [0x01,0x67,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v255, v1
-// CHECK: [0x01,0x67,0xfe,0x7f]
-
-v_frexp_exp_i32_f32 v5, v255
-// CHECK: [0xff,0x67,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, s1
-// CHECK: [0x01,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, s101
-// CHECK: [0x65,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, tba_lo
-// CHECK: [0x6c,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, tba_hi
-// CHECK: [0x6d,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, tma_lo
-// CHECK: [0x6e,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, tma_hi
-// CHECK: [0x6f,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, ttmp11
-// CHECK: [0x7b,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, m0
-// CHECK: [0x7c,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0
-// CHECK: [0x80,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, -1
-// CHECK: [0xc1,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x66,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_exp_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x66,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_exp_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x73,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x73,0xd1,0xff,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x73,0xd1,0x65,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x73,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x73,0xd1,0x67,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x73,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x73,0xd1,0x6b,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x73,0xd1,0x6c,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x73,0xd1,0x6d,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x73,0xd1,0x6e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x73,0xd1,0x6f,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x73,0xd1,0x7b,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x73,0xd1,0x7c,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x73,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x73,0xd1,0x7f,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x73,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x73,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x73,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x73,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x73,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32 v5, v1
-// CHECK: [0x01,0x69,0x0a,0x7e]
-
-v_frexp_mant_f32 v255, v1
-// CHECK: [0x01,0x69,0xfe,0x7f]
-
-v_frexp_mant_f32 v5, v255
-// CHECK: [0xff,0x69,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, s1
-// CHECK: [0x01,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, s101
-// CHECK: [0x65,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, vcc_lo
-// CHECK: [0x6a,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, vcc_hi
-// CHECK: [0x6b,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, tba_lo
-// CHECK: [0x6c,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, tba_hi
-// CHECK: [0x6d,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, tma_lo
-// CHECK: [0x6e,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, tma_hi
-// CHECK: [0x6f,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, ttmp11
-// CHECK: [0x7b,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, m0
-// CHECK: [0x7c,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, exec_lo
-// CHECK: [0x7e,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, exec_hi
-// CHECK: [0x7f,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0
-// CHECK: [0x80,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, -1
-// CHECK: [0xc1,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0.5
-// CHECK: [0xf0,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, -4.0
-// CHECK: [0xf7,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0xaf123456
-// CHECK: [0xff,0x68,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_mant_f32 v5, 0x3f717273
-// CHECK: [0xff,0x68,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_mant_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x74,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x74,0xd1,0xff,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x74,0xd1,0x65,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x74,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x74,0xd1,0x67,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x74,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x74,0xd1,0x6b,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x74,0xd1,0x6c,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x74,0xd1,0x6d,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x74,0xd1,0x6e,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x74,0xd1,0x6f,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x74,0xd1,0x7b,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x74,0xd1,0x7c,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x74,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x74,0xd1,0x7f,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x74,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x74,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x74,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x74,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x74,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x74,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x08]
-
-v_frexp_mant_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x10]
-
-v_frexp_mant_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x18]
-
-v_clrexcp
-// CHECK: [0x00,0x6a,0x00,0x7e]
-
-v_clrexcp_e64
-// CHECK: [0x00,0x00,0x75,0xd1,0x00,0x00,0x00,0x00]
-
-v_movreld_b32 v5, v1
-// CHECK: [0x01,0x6d,0x0a,0x7e]
-
-v_movreld_b32 v255, v1
-// CHECK: [0x01,0x6d,0xfe,0x7f]
-
-v_movreld_b32 v5, v255
-// CHECK: [0xff,0x6d,0x0a,0x7e]
-
-v_movreld_b32 v5, m0
-// CHECK: [0x7c,0x6c,0x0a,0x7e]
-
-v_movreld_b32 v5, 0
-// CHECK: [0x80,0x6c,0x0a,0x7e]
-
-v_movreld_b32 v5, -1
-// CHECK: [0xc1,0x6c,0x0a,0x7e]
-
-v_movreld_b32 v5, 0.5
-// CHECK: [0xf0,0x6c,0x0a,0x7e]
-
-v_movreld_b32 v5, -4.0
-// CHECK: [0xf7,0x6c,0x0a,0x7e]
-
-v_movreld_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x76,0xd1,0x01,0x01,0x00,0x00]
-
-v_movreld_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x76,0xd1,0x01,0x01,0x00,0x00]
-
-v_movreld_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x76,0xd1,0xff,0x01,0x00,0x00]
-
-v_movreld_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x76,0xd1,0x7c,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x76,0xd1,0x80,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x76,0xd1,0xc1,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x76,0xd1,0xf0,0x00,0x00,0x00]
-
-v_movreld_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x76,0xd1,0xf7,0x00,0x00,0x00]
-
-v_movrels_b32 v5, v1
-// CHECK: [0x01,0x6f,0x0a,0x7e]
-
-v_movrels_b32 v255, v1
-// CHECK: [0x01,0x6f,0xfe,0x7f]
-
-v_movrels_b32 v5, v255
-// CHECK: [0xff,0x6f,0x0a,0x7e]
-
-v_movrels_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
-
-v_movrels_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
-
-v_movrels_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x77,0xd1,0xff,0x01,0x00,0x00]
-
-v_movrelsd_b32 v5, v1
-// CHECK: [0x01,0x71,0x0a,0x7e]
-
-v_movrelsd_b32 v255, v1
-// CHECK: [0x01,0x71,0xfe,0x7f]
-
-v_movrelsd_b32 v5, v255
-// CHECK: [0xff,0x71,0x0a,0x7e]
-
-v_movrelsd_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x78,0xd1,0x01,0x01,0x00,0x00]
-
-v_movrelsd_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x78,0xd1,0x01,0x01,0x00,0x00]
-
-v_movrelsd_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x78,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_u16 v5, v1
-// CHECK: [0x01,0x73,0x0a,0x7e]
-
-v_cvt_f16_u16 v255, v1
-// CHECK: [0x01,0x73,0xfe,0x7f]
-
-v_cvt_f16_u16 v5, v255
-// CHECK: [0xff,0x73,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, s1
-// CHECK: [0x01,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, s101
-// CHECK: [0x65,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, flat_scratch_lo
-// CHECK: [0x66,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, flat_scratch_hi
-// CHECK: [0x67,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, vcc_lo
-// CHECK: [0x6a,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, vcc_hi
-// CHECK: [0x6b,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, tba_lo
-// CHECK: [0x6c,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, tba_hi
-// CHECK: [0x6d,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, tma_lo
-// CHECK: [0x6e,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, tma_hi
-// CHECK: [0x6f,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, ttmp11
-// CHECK: [0x7b,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, m0
-// CHECK: [0x7c,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, exec_lo
-// CHECK: [0x7e,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, exec_hi
-// CHECK: [0x7f,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, 0
-// CHECK: [0x80,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, -1
-// CHECK: [0xc1,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, 0.5
-// CHECK: encoding: [0xff,0x72,0x0a,0x7e,0x00,0x38,0x00,0x00]
-
-v_cvt_f16_u16 v5, -4.0
-// CHECK: encoding: [0xff,0x72,0x0a,0x7e,0x00,0xc4,0x00,0x00]
-
-v_cvt_f16_u16 v5, 0xfe0b
-// CHECK: [0xff,0x72,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_f16_u16 v5, 0x3456
-// CHECK: [0xff,0x72,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, v1
-// CHECK: [0x05,0x00,0x79,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_u16_e64 v255, v1
-// CHECK: [0xff,0x00,0x79,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, v255
-// CHECK: [0x05,0x00,0x79,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, s1
-// CHECK: [0x05,0x00,0x79,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, s101
-// CHECK: [0x05,0x00,0x79,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x79,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x79,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x79,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x79,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x79,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x79,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x79,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x79,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x79,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, m0
-// CHECK: [0x05,0x00,0x79,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x79,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x79,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, 0
-// CHECK: [0x05,0x00,0x79,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, -1
-// CHECK: [0x05,0x00,0x79,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cvt_f16_u16_e64 v5, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cvt_f16_u16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x79,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_i16 v5, v1
-// CHECK: [0x01,0x75,0x0a,0x7e]
-
-v_cvt_f16_i16 v255, v1
-// CHECK: [0x01,0x75,0xfe,0x7f]
-
-v_cvt_f16_i16 v5, v255
-// CHECK: [0xff,0x75,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, s1
-// CHECK: [0x01,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, s101
-// CHECK: [0x65,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, flat_scratch_lo
-// CHECK: [0x66,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, flat_scratch_hi
-// CHECK: [0x67,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, vcc_lo
-// CHECK: [0x6a,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, vcc_hi
-// CHECK: [0x6b,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, tba_lo
-// CHECK: [0x6c,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, tba_hi
-// CHECK: [0x6d,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, tma_lo
-// CHECK: [0x6e,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, tma_hi
-// CHECK: [0x6f,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, ttmp11
-// CHECK: [0x7b,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, m0
-// CHECK: [0x7c,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, exec_lo
-// CHECK: [0x7e,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, exec_hi
-// CHECK: [0x7f,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, 0
-// CHECK: [0x80,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, -1
-// CHECK: [0xc1,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, 0.5
-// CHECK: encoding: [0xff,0x74,0x0a,0x7e,0x00,0x38,0x00,0x00]
-
-v_cvt_f16_i16 v5, -4.0
-// CHECK: encoding: [0xff,0x74,0x0a,0x7e,0x00,0xc4,0x00,0x00]
-
-v_cvt_f16_i16 v5, 0xfe0b
-// CHECK: [0xff,0x74,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_f16_i16 v5, 0x3456
-// CHECK: [0xff,0x74,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_i16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7a,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7a,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7a,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7a,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7a,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7a,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x7a,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x7a,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x7a,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x7a,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x7a,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7a,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7a,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7a,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cvt_f16_i16_e64 v5, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cvt_f16_i16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16 v5, v1
-// CHECK: [0x01,0x77,0x0a,0x7e]
-
-v_cvt_u16_f16 v255, v1
-// CHECK: [0x01,0x77,0xfe,0x7f]
-
-v_cvt_u16_f16 v5, v255
-// CHECK: [0xff,0x77,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, s1
-// CHECK: [0x01,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, s101
-// CHECK: [0x65,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, vcc_lo
-// CHECK: [0x6a,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, vcc_hi
-// CHECK: [0x6b,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, tba_lo
-// CHECK: [0x6c,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, tba_hi
-// CHECK: [0x6d,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, tma_lo
-// CHECK: [0x6e,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, tma_hi
-// CHECK: [0x6f,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, ttmp11
-// CHECK: [0x7b,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, m0
-// CHECK: [0x7c,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, exec_lo
-// CHECK: [0x7e,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, exec_hi
-// CHECK: [0x7f,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, 0
-// CHECK: [0x80,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, -1
-// CHECK: [0xc1,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, 0.5
-// CHECK: [0xf0,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, -4.0
-// CHECK: [0xf7,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, 0xfe0b
-// CHECK: [0xff,0x76,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_u16_f16 v5, 0x3456
-// CHECK: [0xff,0x76,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7b,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7b,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7b,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7b,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x7b,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x7b,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x7b,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x7b,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x7b,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7b,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_u16_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16 v5, v1
-// CHECK: [0x01,0x79,0x0a,0x7e]
-
-v_cvt_i16_f16 v255, v1
-// CHECK: [0x01,0x79,0xfe,0x7f]
-
-v_cvt_i16_f16 v5, v255
-// CHECK: [0xff,0x79,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, s1
-// CHECK: [0x01,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, s101
-// CHECK: [0x65,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, vcc_lo
-// CHECK: [0x6a,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, vcc_hi
-// CHECK: [0x6b,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, tba_lo
-// CHECK: [0x6c,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, tba_hi
-// CHECK: [0x6d,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, tma_lo
-// CHECK: [0x6e,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, tma_hi
-// CHECK: [0x6f,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, ttmp11
-// CHECK: [0x7b,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, m0
-// CHECK: [0x7c,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, exec_lo
-// CHECK: [0x7e,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, exec_hi
-// CHECK: [0x7f,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, 0
-// CHECK: [0x80,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, -1
-// CHECK: [0xc1,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, 0.5
-// CHECK: [0xf0,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, -4.0
-// CHECK: [0xf7,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, 0xfe0b
-// CHECK: [0xff,0x78,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_i16_f16 v5, 0x3456
-// CHECK: [0xff,0x78,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7c,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7c,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7c,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7c,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x7c,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x7c,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x7c,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x7c,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x7c,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7c,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_i16_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7c,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f16 v5, v1
-// CHECK: [0x01,0x7b,0x0a,0x7e]
-
-v_rcp_f16 v255, v1
-// CHECK: [0x01,0x7b,0xfe,0x7f]
-
-v_rcp_f16 v5, v255
-// CHECK: [0xff,0x7b,0x0a,0x7e]
-
-v_rcp_f16 v5, s1
-// CHECK: [0x01,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, s101
-// CHECK: [0x65,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, vcc_lo
-// CHECK: [0x6a,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, vcc_hi
-// CHECK: [0x6b,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, tba_lo
-// CHECK: [0x6c,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, tba_hi
-// CHECK: [0x6d,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, tma_lo
-// CHECK: [0x6e,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, tma_hi
-// CHECK: [0x6f,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, ttmp11
-// CHECK: [0x7b,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, m0
-// CHECK: [0x7c,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, exec_lo
-// CHECK: [0x7e,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, exec_hi
-// CHECK: [0x7f,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, 0
-// CHECK: [0x80,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, -1
-// CHECK: [0xc1,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, 0.5
-// CHECK: [0xf0,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, -4.0
-// CHECK: [0xf7,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, 0xfe0b
-// CHECK: [0xff,0x7a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_rcp_f16 v5, 0x3456
-// CHECK: [0xff,0x7a,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_rcp_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7d,0xd1,0xff,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7d,0xd1,0x65,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7d,0xd1,0x66,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7d,0xd1,0x67,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7d,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7d,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x7d,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x7d,0xd1,0x6d,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x7d,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x7d,0xd1,0x6f,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x7d,0xd1,0x7b,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7d,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7d,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7d,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7d,0xd1,0x80,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7d,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7d,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7d,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x20]
-
-v_rcp_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7d,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7d,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16 v5, v1
-// CHECK: [0x01,0x7d,0x0a,0x7e]
-
-v_sqrt_f16 v255, v1
-// CHECK: [0x01,0x7d,0xfe,0x7f]
-
-v_sqrt_f16 v5, v255
-// CHECK: [0xff,0x7d,0x0a,0x7e]
-
-v_sqrt_f16 v5, s1
-// CHECK: [0x01,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, s101
-// CHECK: [0x65,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, vcc_lo
-// CHECK: [0x6a,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, vcc_hi
-// CHECK: [0x6b,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, tba_lo
-// CHECK: [0x6c,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, tba_hi
-// CHECK: [0x6d,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, tma_lo
-// CHECK: [0x6e,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, tma_hi
-// CHECK: [0x6f,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, ttmp11
-// CHECK: [0x7b,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, m0
-// CHECK: [0x7c,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, exec_lo
-// CHECK: [0x7e,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, exec_hi
-// CHECK: [0x7f,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, 0
-// CHECK: [0x80,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, -1
-// CHECK: [0xc1,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, 0.5
-// CHECK: [0xf0,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, -4.0
-// CHECK: [0xf7,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, 0xfe0b
-// CHECK: [0xff,0x7c,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_sqrt_f16 v5, 0x3456
-// CHECK: [0xff,0x7c,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_sqrt_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7e,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7e,0xd1,0xff,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7e,0xd1,0x65,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7e,0xd1,0x66,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7e,0xd1,0x67,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7e,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7e,0xd1,0x6b,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x7e,0xd1,0x6c,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x7e,0xd1,0x6d,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x7e,0xd1,0x6e,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x7e,0xd1,0x6f,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x7e,0xd1,0x7b,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7e,0xd1,0x7c,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7e,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7e,0xd1,0x7f,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7e,0xd1,0x80,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7e,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7e,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7e,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x01,0x00,0x20]
-
-v_sqrt_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7e,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7e,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f16 v5, v1
-// CHECK: [0x01,0x7f,0x0a,0x7e]
-
-v_rsq_f16 v255, v1
-// CHECK: [0x01,0x7f,0xfe,0x7f]
-
-v_rsq_f16 v5, v255
-// CHECK: [0xff,0x7f,0x0a,0x7e]
-
-v_rsq_f16 v5, s1
-// CHECK: [0x01,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, s101
-// CHECK: [0x65,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, vcc_lo
-// CHECK: [0x6a,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, vcc_hi
-// CHECK: [0x6b,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, tba_lo
-// CHECK: [0x6c,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, tba_hi
-// CHECK: [0x6d,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, tma_lo
-// CHECK: [0x6e,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, tma_hi
-// CHECK: [0x6f,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, ttmp11
-// CHECK: [0x7b,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, m0
-// CHECK: [0x7c,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, exec_lo
-// CHECK: [0x7e,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, exec_hi
-// CHECK: [0x7f,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, 0
-// CHECK: [0x80,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, -1
-// CHECK: [0xc1,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, 0.5
-// CHECK: [0xf0,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, -4.0
-// CHECK: [0xf7,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, 0xfe0b
-// CHECK: [0xff,0x7e,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_rsq_f16 v5, 0x3456
-// CHECK: [0xff,0x7e,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_rsq_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7f,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7f,0xd1,0xff,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7f,0xd1,0x65,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7f,0xd1,0x66,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7f,0xd1,0x67,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7f,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7f,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x7f,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x7f,0xd1,0x6d,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x7f,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x7f,0xd1,0x6f,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x7f,0xd1,0x7b,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7f,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7f,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7f,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7f,0xd1,0x80,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7f,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7f,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7f,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x01,0x00,0x20]
-
-v_rsq_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7f,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7f,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f16 v5, v1
-// CHECK: [0x01,0x81,0x0a,0x7e]
-
-v_log_f16 v255, v1
-// CHECK: [0x01,0x81,0xfe,0x7f]
-
-v_log_f16 v5, v255
-// CHECK: [0xff,0x81,0x0a,0x7e]
-
-v_log_f16 v5, s1
-// CHECK: [0x01,0x80,0x0a,0x7e]
-
-v_log_f16 v5, s101
-// CHECK: [0x65,0x80,0x0a,0x7e]
-
-v_log_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x80,0x0a,0x7e]
-
-v_log_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x80,0x0a,0x7e]
-
-v_log_f16 v5, vcc_lo
-// CHECK: [0x6a,0x80,0x0a,0x7e]
-
-v_log_f16 v5, vcc_hi
-// CHECK: [0x6b,0x80,0x0a,0x7e]
-
-v_log_f16 v5, tba_lo
-// CHECK: [0x6c,0x80,0x0a,0x7e]
-
-v_log_f16 v5, tba_hi
-// CHECK: [0x6d,0x80,0x0a,0x7e]
-
-v_log_f16 v5, tma_lo
-// CHECK: [0x6e,0x80,0x0a,0x7e]
-
-v_log_f16 v5, tma_hi
-// CHECK: [0x6f,0x80,0x0a,0x7e]
-
-v_log_f16 v5, ttmp11
-// CHECK: [0x7b,0x80,0x0a,0x7e]
-
-v_log_f16 v5, m0
-// CHECK: [0x7c,0x80,0x0a,0x7e]
-
-v_log_f16 v5, exec_lo
-// CHECK: [0x7e,0x80,0x0a,0x7e]
-
-v_log_f16 v5, exec_hi
-// CHECK: [0x7f,0x80,0x0a,0x7e]
-
-v_log_f16 v5, 0
-// CHECK: [0x80,0x80,0x0a,0x7e]
-
-v_log_f16 v5, -1
-// CHECK: [0xc1,0x80,0x0a,0x7e]
-
-v_log_f16 v5, 0.5
-// CHECK: [0xf0,0x80,0x0a,0x7e]
-
-v_log_f16 v5, -4.0
-// CHECK: [0xf7,0x80,0x0a,0x7e]
-
-v_log_f16 v5, 0xfe0b
-// CHECK: [0xff,0x80,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_log_f16 v5, 0x3456
-// CHECK: [0xff,0x80,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_log_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x80,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x80,0xd1,0xff,0x01,0x00,0x00]
-
-v_log_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x80,0xd1,0x65,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x80,0xd1,0x66,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x80,0xd1,0x67,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x80,0xd1,0x6a,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x80,0xd1,0x6b,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x80,0xd1,0x6c,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x80,0xd1,0x6d,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x80,0xd1,0x6e,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x80,0xd1,0x6f,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x80,0xd1,0x7b,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x80,0xd1,0x7c,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x80,0xd1,0x7e,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x80,0xd1,0x7f,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x80,0xd1,0x80,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x80,0xd1,0xc1,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x80,0xd1,0xf0,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x80,0xd1,0xf7,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x01,0x00,0x20]
-
-v_log_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x80,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x80,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f16 v5, v1
-// CHECK: [0x01,0x83,0x0a,0x7e]
-
-v_exp_f16 v255, v1
-// CHECK: [0x01,0x83,0xfe,0x7f]
-
-v_exp_f16 v5, v255
-// CHECK: [0xff,0x83,0x0a,0x7e]
-
-v_exp_f16 v5, s1
-// CHECK: [0x01,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, s101
-// CHECK: [0x65,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, vcc_lo
-// CHECK: [0x6a,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, vcc_hi
-// CHECK: [0x6b,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, tba_lo
-// CHECK: [0x6c,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, tba_hi
-// CHECK: [0x6d,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, tma_lo
-// CHECK: [0x6e,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, tma_hi
-// CHECK: [0x6f,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, ttmp11
-// CHECK: [0x7b,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, m0
-// CHECK: [0x7c,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, exec_lo
-// CHECK: [0x7e,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, exec_hi
-// CHECK: [0x7f,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, 0
-// CHECK: [0x80,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, -1
-// CHECK: [0xc1,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, 0.5
-// CHECK: [0xf0,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, -4.0
-// CHECK: [0xf7,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, 0xfe0b
-// CHECK: [0xff,0x82,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_exp_f16 v5, 0x3456
-// CHECK: [0xff,0x82,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_exp_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x81,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x81,0xd1,0xff,0x01,0x00,0x00]
-
-v_exp_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x81,0xd1,0x65,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x81,0xd1,0x66,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x81,0xd1,0x67,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x81,0xd1,0x6a,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x81,0xd1,0x6b,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x81,0xd1,0x6c,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x81,0xd1,0x6d,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x81,0xd1,0x6e,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x81,0xd1,0x6f,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x81,0xd1,0x7b,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x81,0xd1,0x7c,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x81,0xd1,0x7e,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x81,0xd1,0x7f,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x81,0xd1,0x80,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x81,0xd1,0xc1,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x81,0xd1,0xf0,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x81,0xd1,0xf7,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x01,0x00,0x20]
-
-v_exp_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x81,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x81,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16 v5, v1
-// CHECK: [0x01,0x85,0x0a,0x7e]
-
-v_frexp_mant_f16 v255, v1
-// CHECK: [0x01,0x85,0xfe,0x7f]
-
-v_frexp_mant_f16 v5, v255
-// CHECK: [0xff,0x85,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, s1
-// CHECK: [0x01,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, s101
-// CHECK: [0x65,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, vcc_lo
-// CHECK: [0x6a,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, vcc_hi
-// CHECK: [0x6b,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, tba_lo
-// CHECK: [0x6c,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, tba_hi
-// CHECK: [0x6d,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, tma_lo
-// CHECK: [0x6e,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, tma_hi
-// CHECK: [0x6f,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, ttmp11
-// CHECK: [0x7b,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, m0
-// CHECK: [0x7c,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, exec_lo
-// CHECK: [0x7e,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, exec_hi
-// CHECK: [0x7f,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, 0
-// CHECK: [0x80,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, -1
-// CHECK: [0xc1,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, 0.5
-// CHECK: [0xf0,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, -4.0
-// CHECK: [0xf7,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, 0xfe0b
-// CHECK: [0xff,0x84,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_frexp_mant_f16 v5, 0x3456
-// CHECK: [0xff,0x84,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x82,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x82,0xd1,0xff,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x82,0xd1,0x65,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x82,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x82,0xd1,0x67,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x82,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x82,0xd1,0x6b,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x82,0xd1,0x6c,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x82,0xd1,0x6d,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x82,0xd1,0x6e,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x82,0xd1,0x6f,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x82,0xd1,0x7b,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x82,0xd1,0x7c,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x82,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x82,0xd1,0x7f,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x82,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x82,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x82,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x82,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x82,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x82,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16 v5, v1
-// CHECK: [0x01,0x87,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v255, v1
-// CHECK: [0x01,0x87,0xfe,0x7f]
-
-v_frexp_exp_i16_f16 v5, v255
-// CHECK: [0xff,0x87,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, s1
-// CHECK: [0x01,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, s101
-// CHECK: [0x65,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, vcc_lo
-// CHECK: [0x6a,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, vcc_hi
-// CHECK: [0x6b,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, tba_lo
-// CHECK: [0x6c,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, tba_hi
-// CHECK: [0x6d,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, tma_lo
-// CHECK: [0x6e,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, tma_hi
-// CHECK: [0x6f,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, ttmp11
-// CHECK: [0x7b,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, m0
-// CHECK: [0x7c,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, exec_lo
-// CHECK: [0x7e,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, exec_hi
-// CHECK: [0x7f,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, 0
-// CHECK: [0x80,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, -1
-// CHECK: [0xc1,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, 0.5
-// CHECK: [0xf0,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, -4.0
-// CHECK: [0xf7,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, 0xfe0b
-// CHECK: [0xff,0x86,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_frexp_exp_i16_f16 v5, 0x3456
-// CHECK: [0xff,0x86,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x83,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x83,0xd1,0xff,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x83,0xd1,0x65,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x83,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x83,0xd1,0x67,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x83,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x83,0xd1,0x6b,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x83,0xd1,0x6c,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x83,0xd1,0x6d,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x83,0xd1,0x6e,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x83,0xd1,0x6f,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x83,0xd1,0x7b,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x83,0xd1,0x7c,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x83,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x83,0xd1,0x7f,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x83,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x83,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x83,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x83,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i16_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x83,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f16 v5, v1
-// CHECK: [0x01,0x89,0x0a,0x7e]
-
-v_floor_f16 v255, v1
-// CHECK: [0x01,0x89,0xfe,0x7f]
-
-v_floor_f16 v5, v255
-// CHECK: [0xff,0x89,0x0a,0x7e]
-
-v_floor_f16 v5, s1
-// CHECK: [0x01,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, s101
-// CHECK: [0x65,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, vcc_lo
-// CHECK: [0x6a,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, vcc_hi
-// CHECK: [0x6b,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, tba_lo
-// CHECK: [0x6c,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, tba_hi
-// CHECK: [0x6d,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, tma_lo
-// CHECK: [0x6e,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, tma_hi
-// CHECK: [0x6f,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, ttmp11
-// CHECK: [0x7b,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, m0
-// CHECK: [0x7c,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, exec_lo
-// CHECK: [0x7e,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, exec_hi
-// CHECK: [0x7f,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, 0
-// CHECK: [0x80,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, -1
-// CHECK: [0xc1,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, 0.5
-// CHECK: [0xf0,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, -4.0
-// CHECK: [0xf7,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, 0xfe0b
-// CHECK: [0xff,0x88,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_floor_f16 v5, 0x3456
-// CHECK: [0xff,0x88,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_floor_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x84,0xd1,0xff,0x01,0x00,0x00]
-
-v_floor_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x84,0xd1,0x65,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x84,0xd1,0x66,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x84,0xd1,0x67,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x84,0xd1,0x6a,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x84,0xd1,0x6b,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x84,0xd1,0x6c,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x84,0xd1,0x6d,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x84,0xd1,0x6e,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x84,0xd1,0x6f,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x84,0xd1,0x7b,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x84,0xd1,0x7c,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x84,0xd1,0x7e,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x84,0xd1,0x7f,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x84,0xd1,0x80,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x84,0xd1,0xc1,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x84,0xd1,0xf0,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x84,0xd1,0xf7,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x20]
-
-v_floor_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x84,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x84,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f16 v5, v1
-// CHECK: [0x01,0x8b,0x0a,0x7e]
-
-v_ceil_f16 v255, v1
-// CHECK: [0x01,0x8b,0xfe,0x7f]
-
-v_ceil_f16 v5, v255
-// CHECK: [0xff,0x8b,0x0a,0x7e]
-
-v_ceil_f16 v5, s1
-// CHECK: [0x01,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, s101
-// CHECK: [0x65,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, vcc_lo
-// CHECK: [0x6a,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, vcc_hi
-// CHECK: [0x6b,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, tba_lo
-// CHECK: [0x6c,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, tba_hi
-// CHECK: [0x6d,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, tma_lo
-// CHECK: [0x6e,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, tma_hi
-// CHECK: [0x6f,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, ttmp11
-// CHECK: [0x7b,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, m0
-// CHECK: [0x7c,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, exec_lo
-// CHECK: [0x7e,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, exec_hi
-// CHECK: [0x7f,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, 0
-// CHECK: [0x80,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, -1
-// CHECK: [0xc1,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, 0.5
-// CHECK: [0xf0,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, -4.0
-// CHECK: [0xf7,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, 0xfe0b
-// CHECK: [0xff,0x8a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_ceil_f16 v5, 0x3456
-// CHECK: [0xff,0x8a,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_ceil_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x85,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x85,0xd1,0xff,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x85,0xd1,0x65,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x85,0xd1,0x66,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x85,0xd1,0x67,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x85,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x85,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x85,0xd1,0x6c,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x85,0xd1,0x6d,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x85,0xd1,0x6e,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x85,0xd1,0x6f,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x85,0xd1,0x7b,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x85,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x85,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x85,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x85,0xd1,0x80,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x85,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x85,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x85,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x01,0x00,0x20]
-
-v_ceil_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x85,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x85,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f16 v5, v1
-// CHECK: [0x01,0x8d,0x0a,0x7e]
-
-v_trunc_f16 v255, v1
-// CHECK: [0x01,0x8d,0xfe,0x7f]
-
-v_trunc_f16 v5, v255
-// CHECK: [0xff,0x8d,0x0a,0x7e]
-
-v_trunc_f16 v5, s1
-// CHECK: [0x01,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, s101
-// CHECK: [0x65,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, vcc_lo
-// CHECK: [0x6a,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, vcc_hi
-// CHECK: [0x6b,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, tba_lo
-// CHECK: [0x6c,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, tba_hi
-// CHECK: [0x6d,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, tma_lo
-// CHECK: [0x6e,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, tma_hi
-// CHECK: [0x6f,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, ttmp11
-// CHECK: [0x7b,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, m0
-// CHECK: [0x7c,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, exec_lo
-// CHECK: [0x7e,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, exec_hi
-// CHECK: [0x7f,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, 0
-// CHECK: [0x80,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, -1
-// CHECK: [0xc1,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, 0.5
-// CHECK: [0xf0,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, -4.0
-// CHECK: [0xf7,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, 0xfe0b
-// CHECK: [0xff,0x8c,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_trunc_f16 v5, 0x3456
-// CHECK: [0xff,0x8c,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_trunc_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x86,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x86,0xd1,0xff,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x86,0xd1,0x65,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x86,0xd1,0x66,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x86,0xd1,0x67,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x86,0xd1,0x6a,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x86,0xd1,0x6b,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x86,0xd1,0x6c,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x86,0xd1,0x6d,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x86,0xd1,0x6e,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x86,0xd1,0x6f,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x86,0xd1,0x7b,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x86,0xd1,0x7c,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x86,0xd1,0x7e,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x86,0xd1,0x7f,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x86,0xd1,0x80,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x86,0xd1,0xc1,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x86,0xd1,0xf0,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x86,0xd1,0xf7,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x01,0x00,0x20]
-
-v_trunc_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x86,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x86,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f16 v5, v1
-// CHECK: [0x01,0x8f,0x0a,0x7e]
-
-v_rndne_f16 v255, v1
-// CHECK: [0x01,0x8f,0xfe,0x7f]
-
-v_rndne_f16 v5, v255
-// CHECK: [0xff,0x8f,0x0a,0x7e]
-
-v_rndne_f16 v5, s1
-// CHECK: [0x01,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, s101
-// CHECK: [0x65,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, vcc_lo
-// CHECK: [0x6a,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, vcc_hi
-// CHECK: [0x6b,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, tba_lo
-// CHECK: [0x6c,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, tba_hi
-// CHECK: [0x6d,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, tma_lo
-// CHECK: [0x6e,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, tma_hi
-// CHECK: [0x6f,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, ttmp11
-// CHECK: [0x7b,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, m0
-// CHECK: [0x7c,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, exec_lo
-// CHECK: [0x7e,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, exec_hi
-// CHECK: [0x7f,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, 0
-// CHECK: [0x80,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, -1
-// CHECK: [0xc1,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, 0.5
-// CHECK: [0xf0,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, -4.0
-// CHECK: [0xf7,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, 0xfe0b
-// CHECK: [0xff,0x8e,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_rndne_f16 v5, 0x3456
-// CHECK: [0xff,0x8e,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_rndne_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x87,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x87,0xd1,0xff,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x87,0xd1,0x65,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x87,0xd1,0x66,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x87,0xd1,0x67,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x87,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x87,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x87,0xd1,0x6c,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x87,0xd1,0x6d,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x87,0xd1,0x6e,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x87,0xd1,0x6f,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x87,0xd1,0x7b,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x87,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x87,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x87,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x87,0xd1,0x80,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x87,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x87,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x87,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x01,0x00,0x20]
-
-v_rndne_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x87,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x87,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f16 v5, v1
-// CHECK: [0x01,0x91,0x0a,0x7e]
-
-v_fract_f16 v255, v1
-// CHECK: [0x01,0x91,0xfe,0x7f]
-
-v_fract_f16 v5, v255
-// CHECK: [0xff,0x91,0x0a,0x7e]
-
-v_fract_f16 v5, s1
-// CHECK: [0x01,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, s101
-// CHECK: [0x65,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, vcc_lo
-// CHECK: [0x6a,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, vcc_hi
-// CHECK: [0x6b,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, tba_lo
-// CHECK: [0x6c,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, tba_hi
-// CHECK: [0x6d,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, tma_lo
-// CHECK: [0x6e,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, tma_hi
-// CHECK: [0x6f,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, ttmp11
-// CHECK: [0x7b,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, m0
-// CHECK: [0x7c,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, exec_lo
-// CHECK: [0x7e,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, exec_hi
-// CHECK: [0x7f,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, 0
-// CHECK: [0x80,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, -1
-// CHECK: [0xc1,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, 0.5
-// CHECK: [0xf0,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, -4.0
-// CHECK: [0xf7,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, 0xfe0b
-// CHECK: [0xff,0x90,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_fract_f16 v5, 0x3456
-// CHECK: [0xff,0x90,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_fract_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x88,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x88,0xd1,0xff,0x01,0x00,0x00]
-
-v_fract_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x88,0xd1,0x65,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x88,0xd1,0x66,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x88,0xd1,0x67,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x88,0xd1,0x6a,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x88,0xd1,0x6b,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x88,0xd1,0x6c,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x88,0xd1,0x6d,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x88,0xd1,0x6e,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x88,0xd1,0x6f,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x88,0xd1,0x7b,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x88,0xd1,0x7c,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x88,0xd1,0x7e,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x88,0xd1,0x7f,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x88,0xd1,0x80,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x88,0xd1,0xc1,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x88,0xd1,0xf0,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x88,0xd1,0xf7,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x01,0x00,0x20]
-
-v_fract_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x88,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x88,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f16 v5, v1
-// CHECK: [0x01,0x93,0x0a,0x7e]
-
-v_sin_f16 v255, v1
-// CHECK: [0x01,0x93,0xfe,0x7f]
-
-v_sin_f16 v5, v255
-// CHECK: [0xff,0x93,0x0a,0x7e]
-
-v_sin_f16 v5, s1
-// CHECK: [0x01,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, s101
-// CHECK: [0x65,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, vcc_lo
-// CHECK: [0x6a,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, vcc_hi
-// CHECK: [0x6b,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, tba_lo
-// CHECK: [0x6c,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, tba_hi
-// CHECK: [0x6d,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, tma_lo
-// CHECK: [0x6e,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, tma_hi
-// CHECK: [0x6f,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, ttmp11
-// CHECK: [0x7b,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, m0
-// CHECK: [0x7c,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, exec_lo
-// CHECK: [0x7e,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, exec_hi
-// CHECK: [0x7f,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, 0
-// CHECK: [0x80,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, -1
-// CHECK: [0xc1,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, 0.5
-// CHECK: [0xf0,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, -4.0
-// CHECK: [0xf7,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, 0xfe0b
-// CHECK: [0xff,0x92,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_sin_f16 v5, 0x3456
-// CHECK: [0xff,0x92,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_sin_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x89,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x89,0xd1,0xff,0x01,0x00,0x00]
-
-v_sin_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x89,0xd1,0x65,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x89,0xd1,0x66,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x89,0xd1,0x67,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x89,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x89,0xd1,0x6b,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x89,0xd1,0x6c,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x89,0xd1,0x6d,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x89,0xd1,0x6e,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x89,0xd1,0x6f,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x89,0xd1,0x7b,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x89,0xd1,0x7c,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x89,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x89,0xd1,0x7f,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x89,0xd1,0x80,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x89,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x89,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x89,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x01,0x00,0x20]
-
-v_sin_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x89,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x89,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f16 v5, v1
-// CHECK: [0x01,0x95,0x0a,0x7e]
-
-v_cos_f16 v255, v1
-// CHECK: [0x01,0x95,0xfe,0x7f]
-
-v_cos_f16 v5, v255
-// CHECK: [0xff,0x95,0x0a,0x7e]
-
-v_cos_f16 v5, s1
-// CHECK: [0x01,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, s101
-// CHECK: [0x65,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, vcc_lo
-// CHECK: [0x6a,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, vcc_hi
-// CHECK: [0x6b,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, tba_lo
-// CHECK: [0x6c,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, tba_hi
-// CHECK: [0x6d,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, tma_lo
-// CHECK: [0x6e,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, tma_hi
-// CHECK: [0x6f,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, ttmp11
-// CHECK: [0x7b,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, m0
-// CHECK: [0x7c,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, exec_lo
-// CHECK: [0x7e,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, exec_hi
-// CHECK: [0x7f,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, 0
-// CHECK: [0x80,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, -1
-// CHECK: [0xc1,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, 0.5
-// CHECK: [0xf0,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, -4.0
-// CHECK: [0xf7,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, 0xfe0b
-// CHECK: [0xff,0x94,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cos_f16 v5, 0x3456
-// CHECK: [0xff,0x94,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cos_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x8a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x8a,0xd1,0xff,0x01,0x00,0x00]
-
-v_cos_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x8a,0xd1,0x65,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8a,0xd1,0x66,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8a,0xd1,0x67,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x8a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x8a,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x8a,0xd1,0x6c,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x8a,0xd1,0x6d,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x8a,0xd1,0x6e,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x8a,0xd1,0x6f,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x8a,0xd1,0x7b,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x8a,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x8a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x8a,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x8a,0xd1,0x80,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x8a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x8a,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x8a,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x01,0x00,0x20]
-
-v_cos_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x8a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x8a,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32 v5, v1
-// CHECK: [0x01,0x97,0x0a,0x7e]
-
-v_exp_legacy_f32 v255, v1
-// CHECK: [0x01,0x97,0xfe,0x7f]
-
-v_exp_legacy_f32 v5, v255
-// CHECK: [0xff,0x97,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, s1
-// CHECK: [0x01,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, s101
-// CHECK: [0x65,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, vcc_lo
-// CHECK: [0x6a,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, vcc_hi
-// CHECK: [0x6b,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, tba_lo
-// CHECK: [0x6c,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, tba_hi
-// CHECK: [0x6d,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, tma_lo
-// CHECK: [0x6e,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, tma_hi
-// CHECK: [0x6f,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, ttmp11
-// CHECK: [0x7b,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, m0
-// CHECK: [0x7c,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, exec_lo
-// CHECK: [0x7e,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, exec_hi
-// CHECK: [0x7f,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, 0
-// CHECK: [0x80,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, -1
-// CHECK: [0xc1,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, 0.5
-// CHECK: [0xf0,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, -4.0
-// CHECK: [0xf7,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, 0xaf123456
-// CHECK: [0xff,0x96,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_exp_legacy_f32 v5, 0x3f717273
-// CHECK: [0xff,0x96,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_exp_legacy_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x8b,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x8b,0xd1,0xff,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x8b,0xd1,0x65,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8b,0xd1,0x66,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8b,0xd1,0x67,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x8b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x8b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x8b,0xd1,0x6c,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x8b,0xd1,0x6d,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x8b,0xd1,0x6e,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x8b,0xd1,0x6f,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x8b,0xd1,0x7b,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x8b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x8b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x8b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x8b,0xd1,0x80,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x8b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x8b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x8b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x20]
-
-v_exp_legacy_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x8b,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x8b,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x08]
-
-v_exp_legacy_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x10]
-
-v_exp_legacy_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x18]
-
-v_log_legacy_f32 v5, v1
-// CHECK: [0x01,0x99,0x0a,0x7e]
-
-v_log_legacy_f32 v255, v1
-// CHECK: [0x01,0x99,0xfe,0x7f]
-
-v_log_legacy_f32 v5, v255
-// CHECK: [0xff,0x99,0x0a,0x7e]
-
-v_log_legacy_f32 v5, s1
-// CHECK: [0x01,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, s101
-// CHECK: [0x65,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, vcc_lo
-// CHECK: [0x6a,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, vcc_hi
-// CHECK: [0x6b,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, tba_lo
-// CHECK: [0x6c,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, tba_hi
-// CHECK: [0x6d,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, tma_lo
-// CHECK: [0x6e,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, tma_hi
-// CHECK: [0x6f,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, ttmp11
-// CHECK: [0x7b,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, m0
-// CHECK: [0x7c,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, exec_lo
-// CHECK: [0x7e,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, exec_hi
-// CHECK: [0x7f,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, 0
-// CHECK: [0x80,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, -1
-// CHECK: [0xc1,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, 0.5
-// CHECK: [0xf0,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, -4.0
-// CHECK: [0xf7,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, 0xaf123456
-// CHECK: [0xff,0x98,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_log_legacy_f32 v5, 0x3f717273
-// CHECK: [0xff,0x98,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_log_legacy_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x8c,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x8c,0xd1,0xff,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x8c,0xd1,0x65,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8c,0xd1,0x66,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8c,0xd1,0x67,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x8c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x8c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, tba_lo
-// CHECK: [0x05,0x00,0x8c,0xd1,0x6c,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, tba_hi
-// CHECK: [0x05,0x00,0x8c,0xd1,0x6d,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, tma_lo
-// CHECK: [0x05,0x00,0x8c,0xd1,0x6e,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, tma_hi
-// CHECK: [0x05,0x00,0x8c,0xd1,0x6f,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, ttmp11
-// CHECK: [0x05,0x00,0x8c,0xd1,0x7b,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x8c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x8c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x8c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x8c,0xd1,0x80,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x8c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x8c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x8c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x20]
-
-v_log_legacy_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x8c,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x8c,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x08]
-
-v_log_legacy_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x10]
-
-v_log_legacy_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x18]
-
-v_cndmask_b32 v5, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x00]
-
-v_cndmask_b32 v255, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x01]
-
-v_cndmask_b32 v5, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x00]
-
-v_cndmask_b32 v5, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x00]
-
-v_cndmask_b32_e64 v5, v1, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x1a,0x00]
-
-v_cndmask_b32_e64 v255, v1, v2, s[6:7]
-// CHECK: [0xff,0x00,0x00,0xd1,0x01,0x05,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, v255, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0xff,0x05,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, 0, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x80,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, -1, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0xc1,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, 0.5, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0xf0,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, -4.0, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0xf7,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, v1, v255, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xff,0x1b,0x00]
-
-v_cndmask_b32_e64 v5, v1, 0, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x01,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, -1, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x83,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, 0.5, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xe1,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, -4.0, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xef,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, v2, s[8:9]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x22,0x00]
-
-v_cndmask_b32_e64 v5, v1, v2, s[100:101]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x92,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, flat_scratch
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, vcc
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, tba
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xb2,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, tma
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xba,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01]
-
-v_add_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x02]
-
-v_add_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x03]
-
-v_add_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x02]
-
-v_add_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x02]
-
-v_add_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x02]
-
-v_add_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x02]
-
-v_add_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x02]
-
-v_add_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x02]
-
-v_add_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x02]
-
-v_add_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x02]
-
-v_add_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x02]
-
-v_add_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x02]
-
-v_add_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x02]
-
-v_add_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x02]
-
-v_add_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x02]
-
-v_add_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x02]
-
-v_add_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x02]
-
-v_add_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x02]
-
-v_add_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x02]
-
-v_add_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x02]
-
-v_add_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x02]
-
-v_add_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x02,0x56,0x34,0x12,0xaf]
-
-v_add_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x02,0x73,0x72,0x71,0x3f]
-
-v_add_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x02]
-
-v_add_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x65,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x66,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x67,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x6a,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x6b,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x6c,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x6d,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x6e,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x6f,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x7b,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x7c,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x7e,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x7f,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x80,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0xc1,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0xf0,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0xf7,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xff,0x03,0x00]
-
-v_add_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x00,0x00]
-
-v_add_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcb,0x00,0x00]
-
-v_add_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcd,0x00,0x00]
-
-v_add_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcf,0x00,0x00]
-
-v_add_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd5,0x00,0x00]
-
-v_add_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd7,0x00,0x00]
-
-v_add_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd9,0x00,0x00]
-
-v_add_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xdb,0x00,0x00]
-
-v_add_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xdd,0x00,0x00]
-
-v_add_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xdf,0x00,0x00]
-
-v_add_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf7,0x00,0x00]
-
-v_add_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf9,0x00,0x00]
-
-v_add_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xfd,0x00,0x00]
-
-v_add_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xff,0x00,0x00]
-
-v_add_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x01,0x01,0x00]
-
-v_add_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x83,0x01,0x00]
-
-v_add_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xe1,0x01,0x00]
-
-v_add_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xef,0x01,0x00]
-
-v_add_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x20]
-
-v_add_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x40]
-
-v_add_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x60]
-
-v_add_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x08]
-
-v_add_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x10]
-
-v_add_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x18]
-
-v_sub_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x04]
-
-v_sub_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x05]
-
-v_sub_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x04]
-
-v_sub_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x04]
-
-v_sub_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x04]
-
-v_sub_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x04]
-
-v_sub_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x04]
-
-v_sub_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x04]
-
-v_sub_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x04]
-
-v_sub_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x04]
-
-v_sub_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x04]
-
-v_sub_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x04]
-
-v_sub_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x04]
-
-v_sub_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x04]
-
-v_sub_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x04]
-
-v_sub_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x04]
-
-v_sub_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x04]
-
-v_sub_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x04]
-
-v_sub_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x04]
-
-v_sub_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x04]
-
-v_sub_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x04]
-
-v_sub_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x04,0x56,0x34,0x12,0xaf]
-
-v_sub_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x04,0x73,0x72,0x71,0x3f]
-
-v_sub_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x04]
-
-v_sub_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0xff,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x65,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x66,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x67,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x6a,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x6b,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x6c,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x6d,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x6e,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x6f,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x7b,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x7c,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x7e,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x7f,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x80,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0xc1,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0xf0,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0xf7,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xff,0x03,0x00]
-
-v_sub_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcb,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcd,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcf,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd5,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd7,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd9,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xdb,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xdd,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xdf,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf7,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf9,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xfd,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xff,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x01,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xe1,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xef,0x01,0x00]
-
-v_sub_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x20]
-
-v_sub_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x40]
-
-v_sub_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x60]
-
-v_sub_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x08]
-
-v_sub_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x10]
-
-v_sub_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x18]
-
-v_subrev_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x06]
-
-v_subrev_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x07]
-
-v_subrev_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x06]
-
-v_subrev_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x06,0x56,0x34,0x12,0xaf]
-
-v_subrev_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x06,0x73,0x72,0x71,0x3f]
-
-v_subrev_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x06]
-
-v_subrev_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0xff,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x65,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x66,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x67,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x6a,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x6b,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x6c,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x6d,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x6e,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x6f,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x7b,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x7c,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x7e,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x7f,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x80,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0xc1,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0xf0,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0xf7,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xff,0x03,0x00]
-
-v_subrev_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcb,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcd,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcf,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd5,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd7,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd9,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xdb,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xdd,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xdf,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf7,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf9,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xfd,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xff,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x01,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x83,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xe1,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xef,0x01,0x00]
-
-v_subrev_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x20]
-
-v_subrev_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x40]
-
-v_subrev_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x60]
-
-v_subrev_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x08]
-
-v_subrev_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x10]
-
-v_subrev_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x18]
-
-v_mul_legacy_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x08]
-
-v_mul_legacy_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x09]
-
-v_mul_legacy_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x08]
-
-v_mul_legacy_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x08,0x56,0x34,0x12,0xaf]
-
-v_mul_legacy_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x08,0x73,0x72,0x71,0x3f]
-
-v_mul_legacy_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x08]
-
-v_mul_legacy_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x20]
-
-v_mul_legacy_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x40]
-
-v_mul_legacy_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x60]
-
-v_mul_legacy_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x08]
-
-v_mul_legacy_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x10]
-
-v_mul_legacy_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x18]
-
-v_mul_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x0a]
-
-v_mul_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x0b]
-
-v_mul_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x0a]
-
-v_mul_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x0a,0x56,0x34,0x12,0xaf]
-
-v_mul_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x0a,0x73,0x72,0x71,0x3f]
-
-v_mul_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x0a]
-
-v_mul_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x20]
-
-v_mul_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x40]
-
-v_mul_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x60]
-
-v_mul_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x08]
-
-v_mul_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x10]
-
-v_mul_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x18]
-
-v_mul_i32_i24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x0c]
-
-v_mul_i32_i24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x0d]
-
-v_mul_i32_i24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x0c]
-
-v_mul_i32_i24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x0c,0x56,0x34,0x12,0xaf]
-
-v_mul_i32_i24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x0c,0x73,0x72,0x71,0x3f]
-
-v_mul_i32_i24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x0c]
-
-v_mul_i32_i24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_i32_i24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_hi_i32_i24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x0f]
-
-v_mul_hi_i32_i24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x0e,0x56,0x34,0x12,0xaf]
-
-v_mul_hi_i32_i24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x0e,0x73,0x72,0x71,0x3f]
-
-v_mul_hi_i32_i24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x0e]
-
-v_mul_hi_i32_i24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x07,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_u32_u24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x10]
-
-v_mul_u32_u24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x11]
-
-v_mul_u32_u24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x10]
-
-v_mul_u32_u24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x10,0x56,0x34,0x12,0xaf]
-
-v_mul_u32_u24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x10,0x73,0x72,0x71,0x3f]
-
-v_mul_u32_u24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x10]
-
-v_mul_u32_u24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_u32_u24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_hi_u32_u24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x12]
-
-v_mul_hi_u32_u24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x13]
-
-v_mul_hi_u32_u24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0xaf]
-
-v_mul_hi_u32_u24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x3f]
-
-v_mul_hi_u32_u24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x12]
-
-v_mul_hi_u32_u24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x09,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xef,0x01,0x00]
-
-v_min_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x14]
-
-v_min_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x15]
-
-v_min_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x14]
-
-v_min_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x14]
-
-v_min_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x14]
-
-v_min_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x14]
-
-v_min_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x14]
-
-v_min_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x14]
-
-v_min_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x14]
-
-v_min_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x14]
-
-v_min_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x14]
-
-v_min_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x14]
-
-v_min_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x14]
-
-v_min_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x14]
-
-v_min_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x14]
-
-v_min_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x14]
-
-v_min_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x14]
-
-v_min_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x14]
-
-v_min_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x14]
-
-v_min_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x14]
-
-v_min_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x14]
-
-v_min_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x14,0x56,0x34,0x12,0xaf]
-
-v_min_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x14,0x73,0x72,0x71,0x3f]
-
-v_min_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x14]
-
-v_min_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x6c,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x6d,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x6e,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x6f,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x7b,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0xf0,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0xf7,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd9,0x00,0x00]
-
-v_min_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xdb,0x00,0x00]
-
-v_min_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xdd,0x00,0x00]
-
-v_min_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xdf,0x00,0x00]
-
-v_min_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf7,0x00,0x00]
-
-v_min_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xe1,0x01,0x00]
-
-v_min_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xef,0x01,0x00]
-
-v_min_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x20]
-
-v_min_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x40]
-
-v_min_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x60]
-
-v_min_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x08]
-
-v_min_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x10]
-
-v_min_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x18]
-
-v_max_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x16]
-
-v_max_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x17]
-
-v_max_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x16]
-
-v_max_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x16]
-
-v_max_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x16]
-
-v_max_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x16]
-
-v_max_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x16]
-
-v_max_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x16]
-
-v_max_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x16]
-
-v_max_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x16]
-
-v_max_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x16]
-
-v_max_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x16]
-
-v_max_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x16]
-
-v_max_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x16]
-
-v_max_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x16]
-
-v_max_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x16]
-
-v_max_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x16]
-
-v_max_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x16]
-
-v_max_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x16]
-
-v_max_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x16]
-
-v_max_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x16]
-
-v_max_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x16,0x56,0x34,0x12,0xaf]
-
-v_max_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x16,0x73,0x72,0x71,0x3f]
-
-v_max_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x16]
-
-v_max_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x6c,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x6d,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x6e,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x6f,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x7b,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0xf0,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0xf7,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd9,0x00,0x00]
-
-v_max_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xdb,0x00,0x00]
-
-v_max_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xdd,0x00,0x00]
-
-v_max_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xdf,0x00,0x00]
-
-v_max_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf7,0x00,0x00]
-
-v_max_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xe1,0x01,0x00]
-
-v_max_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xef,0x01,0x00]
-
-v_max_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x20]
-
-v_max_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x40]
-
-v_max_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x60]
-
-v_max_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x08]
-
-v_max_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x10]
-
-v_max_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x18]
-
-v_min_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x18]
-
-v_min_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x19]
-
-v_min_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x18]
-
-v_min_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x18]
-
-v_min_i32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x18]
-
-v_min_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x18]
-
-v_min_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x18]
-
-v_min_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x18]
-
-v_min_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x18]
-
-v_min_i32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x18]
-
-v_min_i32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x18]
-
-v_min_i32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x18]
-
-v_min_i32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x18]
-
-v_min_i32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x18]
-
-v_min_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x18]
-
-v_min_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x18]
-
-v_min_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x18]
-
-v_min_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x18]
-
-v_min_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x18]
-
-v_min_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x18]
-
-v_min_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x18]
-
-v_min_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x18,0x56,0x34,0x12,0xaf]
-
-v_min_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x18,0x73,0x72,0x71,0x3f]
-
-v_min_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x18]
-
-v_min_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x6c,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x6d,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x6e,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x6f,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x7b,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0xf0,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0xf7,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_i32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_i32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd9,0x00,0x00]
-
-v_min_i32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xdb,0x00,0x00]
-
-v_min_i32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xdd,0x00,0x00]
-
-v_min_i32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xdf,0x00,0x00]
-
-v_min_i32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf7,0x00,0x00]
-
-v_min_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xe1,0x01,0x00]
-
-v_min_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xef,0x01,0x00]
-
-v_max_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x1a]
-
-v_max_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x1b]
-
-v_max_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x1a]
-
-v_max_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x1a]
-
-v_max_i32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x1a]
-
-v_max_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x1a]
-
-v_max_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x1a]
-
-v_max_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x1a]
-
-v_max_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x1a]
-
-v_max_i32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x1a]
-
-v_max_i32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x1a]
-
-v_max_i32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x1a]
-
-v_max_i32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x1a]
-
-v_max_i32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x1a]
-
-v_max_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x1a]
-
-v_max_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x1a]
-
-v_max_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x1a]
-
-v_max_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x1a]
-
-v_max_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x1a]
-
-v_max_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x1a]
-
-v_max_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x1a]
-
-v_max_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x1a,0x56,0x34,0x12,0xaf]
-
-v_max_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x1a,0x73,0x72,0x71,0x3f]
-
-v_max_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x1a]
-
-v_max_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x6c,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x6d,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x6e,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x6f,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x7b,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0xf0,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0xf7,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_i32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_i32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd9,0x00,0x00]
-
-v_max_i32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xdb,0x00,0x00]
-
-v_max_i32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xdd,0x00,0x00]
-
-v_max_i32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xdf,0x00,0x00]
-
-v_max_i32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf7,0x00,0x00]
-
-v_max_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xe1,0x01,0x00]
-
-v_max_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xef,0x01,0x00]
-
-v_min_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x1c]
-
-v_min_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x1d]
-
-v_min_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x1c]
-
-v_min_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x1c]
-
-v_min_u32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x1c]
-
-v_min_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x1c]
-
-v_min_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x1c]
-
-v_min_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x1c]
-
-v_min_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x1c]
-
-v_min_u32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x1c]
-
-v_min_u32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x1c]
-
-v_min_u32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x1c]
-
-v_min_u32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x1c]
-
-v_min_u32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x1c]
-
-v_min_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x1c]
-
-v_min_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x1c]
-
-v_min_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x1c]
-
-v_min_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x1c]
-
-v_min_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x1c]
-
-v_min_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x1c]
-
-v_min_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x1c]
-
-v_min_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x1c,0x56,0x34,0x12,0xaf]
-
-v_min_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x1c,0x73,0x72,0x71,0x3f]
-
-v_min_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x1c]
-
-v_min_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x6c,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x6d,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x6e,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x6f,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x7b,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0xf0,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0xf7,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_u32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_u32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd9,0x00,0x00]
-
-v_min_u32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xdb,0x00,0x00]
-
-v_min_u32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xdd,0x00,0x00]
-
-v_min_u32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xdf,0x00,0x00]
-
-v_min_u32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf7,0x00,0x00]
-
-v_min_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xe1,0x01,0x00]
-
-v_min_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xef,0x01,0x00]
-
-v_max_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x1e]
-
-v_max_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x1f]
-
-v_max_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x1e]
-
-v_max_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x1e]
-
-v_max_u32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x1e]
-
-v_max_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x1e]
-
-v_max_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x1e]
-
-v_max_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x1e]
-
-v_max_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x1e]
-
-v_max_u32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x1e]
-
-v_max_u32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x1e]
-
-v_max_u32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x1e]
-
-v_max_u32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x1e]
-
-v_max_u32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x1e]
-
-v_max_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x1e]
-
-v_max_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x1e]
-
-v_max_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x1e]
-
-v_max_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x1e]
-
-v_max_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x1e]
-
-v_max_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x1e]
-
-v_max_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x1e]
-
-v_max_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x1e,0x56,0x34,0x12,0xaf]
-
-v_max_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x1e,0x73,0x72,0x71,0x3f]
-
-v_max_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x1e]
-
-v_max_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0f,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x6c,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x6d,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x6e,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x6f,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x7b,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0xf0,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0xf7,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_u32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_u32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd9,0x00,0x00]
-
-v_max_u32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xdb,0x00,0x00]
-
-v_max_u32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xdd,0x00,0x00]
-
-v_max_u32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xdf,0x00,0x00]
-
-v_max_u32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf7,0x00,0x00]
-
-v_max_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xe1,0x01,0x00]
-
-v_max_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xef,0x01,0x00]
-
-v_lshrrev_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x20]
-
-v_lshrrev_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x21]
-
-v_lshrrev_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x20]
-
-v_lshrrev_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x20,0x56,0x34,0x12,0xaf]
-
-v_lshrrev_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x20,0x73,0x72,0x71,0x3f]
-
-v_lshrrev_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x20]
-
-v_lshrrev_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x65,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x66,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x67,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x6c,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x6d,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x6e,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x6f,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x7b,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0xf0,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0xf7,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xff,0x03,0x00]
-
-v_lshrrev_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x05,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcb,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcd,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcf,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd7,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd9,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xdb,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xdd,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xdf,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf7,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf9,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xff,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xe1,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xef,0x01,0x00]
-
-v_ashrrev_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x22]
-
-v_ashrrev_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x23]
-
-v_ashrrev_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x22]
-
-v_ashrrev_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x22,0x56,0x34,0x12,0xaf]
-
-v_ashrrev_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x22,0x73,0x72,0x71,0x3f]
-
-v_ashrrev_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x22]
-
-v_ashrrev_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x11,0xd1,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x65,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x66,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x67,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x6c,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x6d,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x6e,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x6f,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x7b,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0xf0,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0xf7,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xff,0x03,0x00]
-
-v_ashrrev_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x05,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcb,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcd,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcf,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd7,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd9,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xdb,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xdd,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xdf,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf7,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf9,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xff,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xe1,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xef,0x01,0x00]
-
-v_lshlrev_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x24]
-
-v_lshlrev_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x25]
-
-v_lshlrev_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x24]
-
-v_lshlrev_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x24,0x56,0x34,0x12,0xaf]
-
-v_lshlrev_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x24,0x73,0x72,0x71,0x3f]
-
-v_lshlrev_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x24]
-
-v_lshlrev_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x12,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x65,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x66,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x67,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x6c,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x6d,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x6e,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x6f,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x7b,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0xf0,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0xf7,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xff,0x03,0x00]
-
-v_lshlrev_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x05,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcb,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcd,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcf,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd7,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd9,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xdb,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xdd,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xdf,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf7,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf9,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xff,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xe1,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xef,0x01,0x00]
-
-v_and_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x26]
-
-v_and_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x27]
-
-v_and_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x26]
-
-v_and_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x26]
-
-v_and_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x26]
-
-v_and_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x26]
-
-v_and_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x26]
-
-v_and_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x26]
-
-v_and_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x26]
-
-v_and_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x26]
-
-v_and_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x26]
-
-v_and_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x26]
-
-v_and_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x26]
-
-v_and_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x26]
-
-v_and_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x26]
-
-v_and_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x26]
-
-v_and_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x26]
-
-v_and_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x26]
-
-v_and_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x26]
-
-v_and_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x26]
-
-v_and_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x26]
-
-v_and_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x26,0x56,0x34,0x12,0xaf]
-
-v_and_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x26,0x73,0x72,0x71,0x3f]
-
-v_and_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x26]
-
-v_and_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x05,0x02,0x00]
-
-v_and_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x13,0xd1,0x01,0x05,0x02,0x00]
-
-v_and_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0xff,0x05,0x02,0x00]
-
-v_and_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x65,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x66,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x67,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x6a,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x6b,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x6c,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x6d,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x6e,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x6f,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x7b,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x7c,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x7e,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x7f,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x80,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0xc1,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0xf0,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0xf7,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xff,0x03,0x00]
-
-v_and_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x05,0x00,0x00]
-
-v_and_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcb,0x00,0x00]
-
-v_and_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcd,0x00,0x00]
-
-v_and_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcf,0x00,0x00]
-
-v_and_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd5,0x00,0x00]
-
-v_and_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd7,0x00,0x00]
-
-v_and_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd9,0x00,0x00]
-
-v_and_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xdb,0x00,0x00]
-
-v_and_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xdd,0x00,0x00]
-
-v_and_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xdf,0x00,0x00]
-
-v_and_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf7,0x00,0x00]
-
-v_and_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf9,0x00,0x00]
-
-v_and_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xfd,0x00,0x00]
-
-v_and_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xff,0x00,0x00]
-
-v_and_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x01,0x01,0x00]
-
-v_and_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x83,0x01,0x00]
-
-v_and_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xe1,0x01,0x00]
-
-v_and_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xef,0x01,0x00]
-
-v_or_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x28]
-
-v_or_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x29]
-
-v_or_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x28]
-
-v_or_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x28]
-
-v_or_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x28]
-
-v_or_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x28]
-
-v_or_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x28]
-
-v_or_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x28]
-
-v_or_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x28]
-
-v_or_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x28]
-
-v_or_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x28]
-
-v_or_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x28]
-
-v_or_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x28]
-
-v_or_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x28]
-
-v_or_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x28]
-
-v_or_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x28]
-
-v_or_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x28]
-
-v_or_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x28]
-
-v_or_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x28]
-
-v_or_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x28]
-
-v_or_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x28]
-
-v_or_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x28,0x56,0x34,0x12,0xaf]
-
-v_or_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x28,0x73,0x72,0x71,0x3f]
-
-v_or_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x28]
-
-v_or_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x05,0x02,0x00]
-
-v_or_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x14,0xd1,0x01,0x05,0x02,0x00]
-
-v_or_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0xff,0x05,0x02,0x00]
-
-v_or_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x65,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x66,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x67,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x6a,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x6b,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x6c,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x6d,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x6e,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x6f,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x7b,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x7c,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x7e,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x7f,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x80,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0xc1,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0xf0,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0xf7,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xff,0x03,0x00]
-
-v_or_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x05,0x00,0x00]
-
-v_or_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcb,0x00,0x00]
-
-v_or_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcd,0x00,0x00]
-
-v_or_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcf,0x00,0x00]
-
-v_or_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd5,0x00,0x00]
-
-v_or_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd7,0x00,0x00]
-
-v_or_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd9,0x00,0x00]
-
-v_or_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xdb,0x00,0x00]
-
-v_or_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xdd,0x00,0x00]
-
-v_or_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xdf,0x00,0x00]
-
-v_or_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf7,0x00,0x00]
-
-v_or_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf9,0x00,0x00]
-
-v_or_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xfd,0x00,0x00]
-
-v_or_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xff,0x00,0x00]
-
-v_or_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x01,0x01,0x00]
-
-v_or_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x83,0x01,0x00]
-
-v_or_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xe1,0x01,0x00]
-
-v_or_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xef,0x01,0x00]
-
-v_xor_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x2a]
-
-v_xor_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x2b]
-
-v_xor_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x2a]
-
-v_xor_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x2a,0x56,0x34,0x12,0xaf]
-
-v_xor_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x2a,0x73,0x72,0x71,0x3f]
-
-v_xor_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x2a]
-
-v_xor_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x05,0x02,0x00]
-
-v_xor_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x15,0xd1,0x01,0x05,0x02,0x00]
-
-v_xor_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0xff,0x05,0x02,0x00]
-
-v_xor_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x65,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x66,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x67,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x6a,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x6b,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x6c,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x6d,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x6e,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x6f,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x7b,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x7c,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x7e,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x7f,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x80,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0xc1,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0xf0,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0xf7,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xff,0x03,0x00]
-
-v_xor_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x05,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcb,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcd,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcf,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd5,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd7,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd9,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xdb,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xdd,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xdf,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf7,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf9,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xfd,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xff,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x01,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x83,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xe1,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xef,0x01,0x00]
-
-v_mac_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x2c]
-
-v_mac_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x2d]
-
-v_mac_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x2c]
-
-v_mac_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x2c,0x56,0x34,0x12,0xaf]
-
-v_mac_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x2c,0x73,0x72,0x71,0x3f]
-
-v_mac_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x2c]
-
-v_mac_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0xff,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x65,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x66,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x67,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x80,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xff,0x03,0x00]
-
-v_mac_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xff,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x01,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x83,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xef,0x01,0x00]
-
-v_mac_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x20]
-
-v_mac_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x40]
-
-v_mac_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x60]
-
-v_mac_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x08]
-
-v_mac_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x10]
-
-v_mac_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x18]
-
-v_madmk_f32 v5, v1, 0x11213141, v3
-// CHECK: [0x01,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v255, v1, 0x11213141, v3
-// CHECK: [0x01,0x07,0xfe,0x2f,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, v255, 0x11213141, v3
-// CHECK: [0xff,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, 0, 0x11213141, v3
-// CHECK: [0x80,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, -1, 0x11213141, v3
-// CHECK: [0xc1,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, 0.5, 0x11213141, v3
-// CHECK: [0xf0,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, -4.0, 0x11213141, v3
-// CHECK: [0xf7,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, v1, 0xa1b1c1d1, v3
-// CHECK: [0x01,0x07,0x0a,0x2e,0xd1,0xc1,0xb1,0xa1]
-
-v_madmk_f32 v5, v1, 0x11213141, v255
-// CHECK: [0x01,0xff,0x0b,0x2e,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v2, 0x11213141
-// CHECK: [0x01,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v255, v1, v2, 0x11213141
-// CHECK: [0x01,0x05,0xfe,0x31,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v255, v2, 0x11213141
-// CHECK: [0xff,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, 0, v2, 0x11213141
-// CHECK: [0x80,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, -1, v2, 0x11213141
-// CHECK: [0xc1,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, 0.5, v2, 0x11213141
-// CHECK: [0xf0,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, -4.0, v2, 0x11213141
-// CHECK: [0xf7,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v255, 0x11213141
-// CHECK: [0x01,0xff,0x0b,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v2, 0xa1b1c1d1
-// CHECK: [0x01,0x05,0x0a,0x30,0xd1,0xc1,0xb1,0xa1]
-
-v_add_u32 v5, vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x32]
-
-v_add_u32 v255, vcc, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x33]
-
-v_add_u32 v5, vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x32]
-
-v_add_u32 v5, vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x32]
-
-v_add_u32 v5, vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x32,0x56,0x34,0x12,0xaf]
-
-v_add_u32 v5, vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x32,0x73,0x72,0x71,0x3f]
-
-v_add_u32 v5, vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x32]
-
-v_add_u32_e64 v5, s[12:13], v1, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v255, s[12:13], v1, v2
-// CHECK: [0xff,0x0c,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, s[14:15], v1, v2
-// CHECK: [0x05,0x0e,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, s[100:101], v1, v2
-// CHECK: [0x05,0x64,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, flat_scratch, v1, v2
-// CHECK: [0x05,0x66,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, vcc, v1, v2
-// CHECK: [0x05,0x6a,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, tba, v1, v2
-// CHECK: [0x05,0x6c,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, tma, v1, v2
-// CHECK: [0x05,0x6e,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, ttmp[10:11], v1, v2
-// CHECK: [0x05,0x7a,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], v255, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0xff,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], s1, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], s101, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x65,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], flat_scratch_lo, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x66,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], flat_scratch_hi, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x67,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], vcc_lo, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x6a,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], vcc_hi, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x6b,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], tba_lo, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x6c,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], tba_hi, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x6d,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], tma_lo, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x6e,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], tma_hi, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x6f,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], ttmp11, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x7b,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], m0, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x7c,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], exec_lo, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x7e,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], exec_hi, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x7f,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], 0, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x80,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], -1, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0xc1,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], 0.5, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0xf0,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], -4.0, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0xf7,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, v255
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xff,0x03,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, s2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x05,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, s101
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcb,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, flat_scratch_lo
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcd,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, flat_scratch_hi
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcf,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, vcc_lo
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd5,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, vcc_hi
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd7,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, tba_lo
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd9,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, tba_hi
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xdb,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, tma_lo
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xdd,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, tma_hi
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xdf,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, ttmp11
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf7,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, m0
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf9,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, exec_lo
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xfd,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, exec_hi
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xff,0x00,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, 0
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x01,0x01,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, -1
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x83,0x01,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, 0.5
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xe1,0x01,0x00]
-
-v_add_u32_e64 v5, s[12:13], v1, -4.0
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xef,0x01,0x00]
-
-v_sub_u32 v5, vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x34]
-
-v_sub_u32 v255, vcc, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x35]
-
-v_sub_u32 v5, vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x34]
-
-v_sub_u32 v5, vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x34]
-
-v_sub_u32 v5, vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x34,0x56,0x34,0x12,0xaf]
-
-v_sub_u32 v5, vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x34,0x73,0x72,0x71,0x3f]
-
-v_sub_u32 v5, vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x34]
-
-v_sub_u32_e64 v5, s[12:13], v1, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v255, s[12:13], v1, v2
-// CHECK: [0xff,0x0c,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, s[14:15], v1, v2
-// CHECK: [0x05,0x0e,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, s[100:101], v1, v2
-// CHECK: [0x05,0x64,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, flat_scratch, v1, v2
-// CHECK: [0x05,0x66,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, vcc, v1, v2
-// CHECK: [0x05,0x6a,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, tba, v1, v2
-// CHECK: [0x05,0x6c,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, tma, v1, v2
-// CHECK: [0x05,0x6e,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, ttmp[10:11], v1, v2
-// CHECK: [0x05,0x7a,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v255, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0xff,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], s1, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], s101, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x65,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], flat_scratch_lo, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x66,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], flat_scratch_hi, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x67,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], vcc_lo, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], vcc_hi, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x6b,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], tba_lo, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x6c,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], tba_hi, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x6d,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], tma_lo, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x6e,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], tma_hi, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x6f,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], ttmp11, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x7b,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], m0, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x7c,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], exec_lo, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], exec_hi, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x7f,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], 0, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x80,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], -1, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], 0.5, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0xf0,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], -4.0, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0xf7,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, v255
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xff,0x03,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, s2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x05,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, s101
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcb,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, flat_scratch_lo
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcd,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, flat_scratch_hi
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcf,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, vcc_lo
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, vcc_hi
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd7,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, tba_lo
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd9,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, tba_hi
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xdb,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, tma_lo
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xdd,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, tma_hi
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xdf,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, ttmp11
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf7,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, m0
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf9,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, exec_lo
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, exec_hi
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xff,0x00,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, 0
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x01,0x01,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, -1
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, 0.5
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xe1,0x01,0x00]
-
-v_sub_u32_e64 v5, s[12:13], v1, -4.0
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xef,0x01,0x00]
-
-v_subrev_u32 v5, vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x36]
-
-v_subrev_u32 v255, vcc, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x37]
-
-v_subrev_u32 v5, vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x36]
-
-v_subrev_u32 v5, vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x36,0x56,0x34,0x12,0xaf]
-
-v_subrev_u32 v5, vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x36,0x73,0x72,0x71,0x3f]
-
-v_subrev_u32 v5, vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x36]
-
-v_subrev_u32_e64 v5, s[12:13], v1, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v255, s[12:13], v1, v2
-// CHECK: [0xff,0x0c,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[14:15], v1, v2
-// CHECK: [0x05,0x0e,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[100:101], v1, v2
-// CHECK: [0x05,0x64,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, flat_scratch, v1, v2
-// CHECK: [0x05,0x66,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, vcc, v1, v2
-// CHECK: [0x05,0x6a,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, tba, v1, v2
-// CHECK: [0x05,0x6c,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, tma, v1, v2
-// CHECK: [0x05,0x6e,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, ttmp[10:11], v1, v2
-// CHECK: [0x05,0x7a,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v255, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0xff,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], s1, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], s101, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x65,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], flat_scratch_lo, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x66,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], flat_scratch_hi, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x67,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], vcc_lo, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x6a,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], vcc_hi, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x6b,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], tba_lo, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x6c,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], tba_hi, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x6d,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], tma_lo, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x6e,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], tma_hi, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x6f,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], ttmp11, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x7b,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], m0, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x7c,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], exec_lo, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x7e,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], exec_hi, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x7f,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], 0, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x80,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], -1, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0xc1,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], 0.5, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0xf0,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], -4.0, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0xf7,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, v255
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xff,0x03,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, s2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x05,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, s101
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcb,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, flat_scratch_lo
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcd,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, flat_scratch_hi
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcf,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, vcc_lo
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd5,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, vcc_hi
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd7,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, tba_lo
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd9,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, tba_hi
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xdb,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, tma_lo
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xdd,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, tma_hi
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xdf,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, ttmp11
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf7,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, m0
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf9,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, exec_lo
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xfd,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, exec_hi
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xff,0x00,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, 0
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x01,0x01,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, -1
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x83,0x01,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, 0.5
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xe1,0x01,0x00]
-
-v_subrev_u32_e64 v5, s[12:13], v1, -4.0
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xef,0x01,0x00]
-
-v_addc_u32 v5, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x38]
-
-v_addc_u32 v255, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x39]
-
-v_addc_u32 v5, vcc, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x38]
-
-v_addc_u32 v5, vcc, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x38]
-
-v_addc_u32 v5, vcc, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x38]
-
-v_addc_u32 v5, vcc, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x38]
-
-v_addc_u32 v5, vcc, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x38]
-
-v_addc_u32 v5, vcc, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x38]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: [0xff,0x0c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// CHECK: [0x05,0x0e,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[100:101], v1, v2, s[6:7]
-// CHECK: [0x05,0x64,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
-// CHECK: [0x05,0x66,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, vcc, v1, v2, s[6:7]
-// CHECK: [0x05,0x6a,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, tba, v1, v2, s[6:7]
-// CHECK: [0x05,0x6c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, tma, v1, v2, s[6:7]
-// CHECK: [0x05,0x6e,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
-// CHECK: [0x05,0x7a,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0xff,0x05,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x80,0x04,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0xc1,0x04,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0xf0,0x04,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0xf7,0x04,0x1a,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xff,0x1b,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x01,0x19,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x83,0x19,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xe1,0x19,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xef,0x19,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x22,0x00]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x92,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x9a,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xaa,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xb2,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xba,0x01]
-
-v_addc_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xea,0x01]
-
-v_subb_u32 v5, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x3a]
-
-v_subb_u32 v255, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x3b]
-
-v_subb_u32 v5, vcc, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x3a]
-
-v_subb_u32 v5, vcc, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x3a]
-
-v_subb_u32 v5, vcc, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x3a]
-
-v_subb_u32 v5, vcc, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x3a]
-
-v_subb_u32 v5, vcc, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x3a]
-
-v_subb_u32 v5, vcc, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x3a]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: [0xff,0x0c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// CHECK: [0x05,0x0e,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[100:101], v1, v2, s[6:7]
-// CHECK: [0x05,0x64,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
-// CHECK: [0x05,0x66,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, vcc, v1, v2, s[6:7]
-// CHECK: [0x05,0x6a,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, tba, v1, v2, s[6:7]
-// CHECK: [0x05,0x6c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, tma, v1, v2, s[6:7]
-// CHECK: [0x05,0x6e,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
-// CHECK: [0x05,0x7a,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0xff,0x05,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x80,0x04,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0xc1,0x04,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0xf0,0x04,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0xf7,0x04,0x1a,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xff,0x1b,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x01,0x19,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x83,0x19,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xe1,0x19,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xef,0x19,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x22,0x00]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x92,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x9a,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xaa,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xb2,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xba,0x01]
-
-v_subb_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xea,0x01]
-
-v_subbrev_u32 v5, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x3c]
-
-v_subbrev_u32 v255, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x3d]
-
-v_subbrev_u32 v5, vcc, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x3c]
-
-v_subbrev_u32 v5, vcc, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x3c]
-
-v_subbrev_u32 v5, vcc, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x3c]
-
-v_subbrev_u32 v5, vcc, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x3c]
-
-v_subbrev_u32 v5, vcc, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x3c]
-
-v_subbrev_u32 v5, vcc, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x3c]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: [0xff,0x0c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// CHECK: [0x05,0x0e,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[100:101], v1, v2, s[6:7]
-// CHECK: [0x05,0x64,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
-// CHECK: [0x05,0x66,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, vcc, v1, v2, s[6:7]
-// CHECK: [0x05,0x6a,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, tba, v1, v2, s[6:7]
-// CHECK: [0x05,0x6c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, tma, v1, v2, s[6:7]
-// CHECK: [0x05,0x6e,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
-// CHECK: [0x05,0x7a,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0xff,0x05,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x80,0x04,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0xc1,0x04,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0xf0,0x04,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0xf7,0x04,0x1a,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xff,0x1b,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x01,0x19,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x83,0x19,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xe1,0x19,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xef,0x19,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x22,0x00]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x92,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x9a,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xaa,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xb2,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xba,0x01]
-
-v_subbrev_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xea,0x01]
-
-v_add_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x3e]
-
-v_add_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x3f]
-
-v_add_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x3e]
-
-v_add_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x3e]
-
-v_add_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x3e]
-
-v_add_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x3e]
-
-v_add_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x3e]
-
-v_add_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x3e]
-
-v_add_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x3e]
-
-v_add_f16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x3e]
-
-v_add_f16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x3e]
-
-v_add_f16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x3e]
-
-v_add_f16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x3e]
-
-v_add_f16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x3e]
-
-v_add_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x3e]
-
-v_add_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x3e]
-
-v_add_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x3e]
-
-v_add_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x3e]
-
-v_add_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x3e]
-
-v_add_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x3e]
-
-v_add_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x3e]
-
-v_add_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x3e,0x0b,0xfe,0x00,0x00]
-
-v_add_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x3e,0x56,0x34,0x00,0x00]
-
-v_add_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x3e]
-
-v_add_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0xff,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x65,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x66,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x67,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x6a,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x6b,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x6c,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x6d,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x6e,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x6f,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x7b,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x7c,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x7e,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x7f,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x80,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0xc1,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0xf0,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0xf7,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xff,0x03,0x00]
-
-v_add_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x00,0x00]
-
-v_add_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcb,0x00,0x00]
-
-v_add_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcd,0x00,0x00]
-
-v_add_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcf,0x00,0x00]
-
-v_add_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd5,0x00,0x00]
-
-v_add_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd7,0x00,0x00]
-
-v_add_f16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd9,0x00,0x00]
-
-v_add_f16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xdb,0x00,0x00]
-
-v_add_f16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xdd,0x00,0x00]
-
-v_add_f16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xdf,0x00,0x00]
-
-v_add_f16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf7,0x00,0x00]
-
-v_add_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf9,0x00,0x00]
-
-v_add_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xfd,0x00,0x00]
-
-v_add_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xff,0x00,0x00]
-
-v_add_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x01,0x01,0x00]
-
-v_add_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x83,0x01,0x00]
-
-v_add_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xe1,0x01,0x00]
-
-v_add_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xef,0x01,0x00]
-
-v_add_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x20]
-
-v_add_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x40]
-
-v_add_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x60]
-
-v_add_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x40]
-
-v_sub_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x41]
-
-v_sub_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x40]
-
-v_sub_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x40]
-
-v_sub_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x40]
-
-v_sub_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x40]
-
-v_sub_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x40]
-
-v_sub_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x40]
-
-v_sub_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x40]
-
-v_sub_f16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x40]
-
-v_sub_f16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x40]
-
-v_sub_f16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x40]
-
-v_sub_f16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x40]
-
-v_sub_f16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x40]
-
-v_sub_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x40]
-
-v_sub_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x40]
-
-v_sub_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x40]
-
-v_sub_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x40]
-
-v_sub_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x40]
-
-v_sub_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x40]
-
-v_sub_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x40]
-
-v_sub_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x40,0x0b,0xfe,0x00,0x00]
-
-v_sub_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x40,0x56,0x34,0x00,0x00]
-
-v_sub_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x40]
-
-v_sub_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0xff,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x65,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x66,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x67,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x6a,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x6b,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x6c,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x6d,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x6e,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x6f,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x7b,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x7c,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x7e,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x7f,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x80,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0xc1,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0xf0,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0xf7,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xff,0x03,0x00]
-
-v_sub_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcb,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcd,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcf,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd5,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd7,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd9,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xdb,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xdd,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xdf,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf7,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf9,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xfd,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xff,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x01,0x01,0x00]
-
-v_sub_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xe1,0x01,0x00]
-
-v_sub_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xef,0x01,0x00]
-
-v_sub_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x20]
-
-v_sub_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x40]
-
-v_sub_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x60]
-
-v_sub_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x42]
-
-v_subrev_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x43]
-
-v_subrev_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x42]
-
-v_subrev_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x42,0x0b,0xfe,0x00,0x00]
-
-v_subrev_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x42,0x56,0x34,0x00,0x00]
-
-v_subrev_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x42]
-
-v_subrev_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0xff,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x65,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x66,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x67,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x6a,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x6b,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x6c,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x6d,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x6e,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x6f,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x7b,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x7c,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x7e,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x7f,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x80,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0xc1,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0xf0,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0xf7,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xff,0x03,0x00]
-
-v_subrev_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcb,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcd,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcf,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd5,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd7,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd9,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xdb,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xdd,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xdf,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf7,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf9,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xfd,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xff,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x01,0x01,0x00]
-
-v_subrev_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x83,0x01,0x00]
-
-v_subrev_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xe1,0x01,0x00]
-
-v_subrev_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xef,0x01,0x00]
-
-v_subrev_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x20]
-
-v_subrev_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x40]
-
-v_subrev_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x60]
-
-v_subrev_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x44]
-
-v_mul_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x45]
-
-v_mul_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x44]
-
-v_mul_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x44]
-
-v_mul_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x44]
-
-v_mul_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x44]
-
-v_mul_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x44]
-
-v_mul_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x44]
-
-v_mul_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x44]
-
-v_mul_f16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x44]
-
-v_mul_f16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x44]
-
-v_mul_f16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x44]
-
-v_mul_f16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x44]
-
-v_mul_f16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x44]
-
-v_mul_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x44]
-
-v_mul_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x44]
-
-v_mul_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x44]
-
-v_mul_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x44]
-
-v_mul_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x44]
-
-v_mul_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x44]
-
-v_mul_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x44]
-
-v_mul_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x44,0x0b,0xfe,0x00,0x00]
-
-v_mul_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x44,0x56,0x34,0x00,0x00]
-
-v_mul_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x44]
-
-v_mul_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x20]
-
-v_mul_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x40]
-
-v_mul_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x60]
-
-v_mul_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x46]
-
-v_mac_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x47]
-
-v_mac_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x46]
-
-v_mac_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x46]
-
-v_mac_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x46]
-
-v_mac_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x46]
-
-v_mac_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x46]
-
-v_mac_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x46]
-
-v_mac_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x46]
-
-v_mac_f16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x46]
-
-v_mac_f16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x46]
-
-v_mac_f16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x46]
-
-v_mac_f16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x46]
-
-v_mac_f16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x46]
-
-v_mac_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x46]
-
-v_mac_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x46]
-
-v_mac_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x46]
-
-v_mac_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x46]
-
-v_mac_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x46]
-
-v_mac_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x46]
-
-v_mac_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x46]
-
-v_mac_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x46,0x0b,0xfe,0x00,0x00]
-
-v_mac_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x46,0x56,0x34,0x00,0x00]
-
-v_mac_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x46]
-
-v_mac_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0xff,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x65,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x66,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x67,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x80,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xff,0x03,0x00]
-
-v_mac_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xff,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x01,0x01,0x00]
-
-v_mac_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x83,0x01,0x00]
-
-v_mac_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mac_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xef,0x01,0x00]
-
-v_mac_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x20]
-
-v_mac_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x40]
-
-v_mac_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x60]
-
-v_mac_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_madmk_f16 v5, v1, 0x1121, v3
-// CHECK: [0x01,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v255, v1, 0x1121, v3
-// CHECK: [0x01,0x07,0xfe,0x49,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, v255, 0x1121, v3
-// CHECK: [0xff,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, 0, 0x1121, v3
-// CHECK: [0x80,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, -1, 0x1121, v3
-// CHECK: [0xc1,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, 0.5, 0x1121, v3
-// CHECK: [0xf0,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, -4.0, 0x1121, v3
-// CHECK: [0xf7,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, v1, 0xa1b1, v3
-// CHECK: [0x01,0x07,0x0a,0x48,0xb1,0xa1,0x00,0x00]
-
-v_madmk_f16 v5, v1, 0x1121, v255
-// CHECK: [0x01,0xff,0x0b,0x48,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, v1, v2, 0x1121
-// CHECK: [0x01,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v255, v1, v2, 0x1121
-// CHECK: [0x01,0x05,0xfe,0x4b,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, v255, v2, 0x1121
-// CHECK: [0xff,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, 0, v2, 0x1121
-// CHECK: [0x80,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, -1, v2, 0x1121
-// CHECK: [0xc1,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, 0.5, v2, 0x1121
-// CHECK: [0xf0,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, -4.0, v2, 0x1121
-// CHECK: [0xf7,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, v1, v255, 0x1121
-// CHECK: [0x01,0xff,0x0b,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, v1, v2, 0xa1b1
-// CHECK: [0x01,0x05,0x0a,0x4a,0xb1,0xa1,0x00,0x00]
-
-v_add_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x4c]
-
-v_add_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x4d]
-
-v_add_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x4c]
-
-v_add_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x4c]
-
-v_add_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x4c]
-
-v_add_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x4c]
-
-v_add_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x4c]
-
-v_add_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x4c]
-
-v_add_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x4c]
-
-v_add_u16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x4c]
-
-v_add_u16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x4c]
-
-v_add_u16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x4c]
-
-v_add_u16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x4c]
-
-v_add_u16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x4c]
-
-v_add_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x4c]
-
-v_add_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x4c]
-
-v_add_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x4c]
-
-v_add_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x4c]
-
-v_add_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x4c]
-
-v_add_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x4c,0x00,0x38,0x00,0x00]
-
-v_add_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x4c,0x00,0xc4,0x00,0x00]
-
-v_add_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x4c,0x0b,0xfe,0x00,0x00]
-
-v_add_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x4c,0x56,0x34,0x00,0x00]
-
-v_add_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x4c]
-
-v_add_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0xff,0x05,0x02,0x00]
-
-v_add_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x65,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x66,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x67,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x6a,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x6b,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x6c,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x6d,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x6e,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x6f,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x7b,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x7c,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x7e,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x7f,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x80,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0xc1,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_add_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_add_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xff,0x03,0x00]
-
-v_add_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x05,0x00,0x00]
-
-v_add_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcb,0x00,0x00]
-
-v_add_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcd,0x00,0x00]
-
-v_add_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcf,0x00,0x00]
-
-v_add_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd5,0x00,0x00]
-
-v_add_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd7,0x00,0x00]
-
-v_add_u16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd9,0x00,0x00]
-
-v_add_u16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xdb,0x00,0x00]
-
-v_add_u16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xdd,0x00,0x00]
-
-v_add_u16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xdf,0x00,0x00]
-
-v_add_u16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf7,0x00,0x00]
-
-v_add_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf9,0x00,0x00]
-
-v_add_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xfd,0x00,0x00]
-
-v_add_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xff,0x00,0x00]
-
-v_add_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x01,0x01,0x00]
-
-v_add_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x83,0x01,0x00]
-
-v_add_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_add_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x4e]
-
-v_sub_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x4f]
-
-v_sub_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x4e]
-
-v_sub_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x4e,0x00,0x38,0x00,0x00]
-
-v_sub_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x4e,0x00,0xc4,0x00,0x00]
-
-v_sub_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x4e,0x0b,0xfe,0x00,0x00]
-
-v_sub_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x4e,0x56,0x34,0x00,0x00]
-
-v_sub_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x4e]
-
-v_sub_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x27,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0xff,0x05,0x02,0x00]
-
-v_sub_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x65,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x66,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x67,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x6a,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x6b,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x6c,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x6d,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x6e,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x6f,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x7b,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x7c,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x7e,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x7f,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x80,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0xc1,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x03,0x00]
-
-v_sub_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x05,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcb,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcd,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcf,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd5,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd7,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd9,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xdb,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xdd,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xdf,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf7,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf9,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xfd,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x01,0x01,0x00]
-
-v_sub_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_subrev_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x50]
-
-v_subrev_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x51]
-
-v_subrev_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x50]
-
-v_subrev_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x50,0x00,0x38,0x00,0x00]
-
-v_subrev_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x50,0x00,0xc4,0x00,0x00]
-
-v_subrev_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x50,0x0b,0xfe,0x00,0x00]
-
-v_subrev_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x50,0x56,0x34,0x00,0x00]
-
-v_subrev_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x50]
-
-v_subrev_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0xff,0x05,0x02,0x00]
-
-v_subrev_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x65,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x66,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x67,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x6a,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x6b,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x6c,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x6d,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x6e,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x6f,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x7b,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x7c,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x7e,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x7f,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x80,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0xc1,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_subrev_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_subrev_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x03,0x00]
-
-v_subrev_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x05,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcb,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcd,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcf,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd5,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd7,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd9,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xdb,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xdd,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xdf,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf7,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf9,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xfd,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x01,0x01,0x00]
-
-v_subrev_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x83,0x01,0x00]
-
-v_subrev_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_subrev_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_mul_lo_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x52]
-
-v_mul_lo_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x53]
-
-v_mul_lo_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x52]
-
-v_mul_lo_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x52,0x00,0x38,0x00,0x00]
-
-v_mul_lo_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x52,0x00,0xc4,0x00,0x00]
-
-v_mul_lo_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x52,0x0b,0xfe,0x00,0x00]
-
-v_mul_lo_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x52,0x56,0x34,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x52]
-
-v_mul_lo_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x29,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x6c,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x6d,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x6e,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x6f,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x7b,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_mul_lo_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_mul_lo_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_lo_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd9,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xdb,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xdd,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xdf,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf7,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_lo_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_lo_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_mul_lo_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshlrev_b16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x54]
-
-v_lshlrev_b16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x55]
-
-v_lshlrev_b16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x54]
-
-v_lshlrev_b16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x54,0x00,0x38,0x00,0x00]
-
-v_lshlrev_b16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x54,0x00,0xc4,0x00,0x00]
-
-v_lshlrev_b16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x54,0x0b,0xfe,0x00,0x00]
-
-v_lshlrev_b16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x54,0x56,0x34,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x54]
-
-v_lshlrev_b16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x65,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x66,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x67,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x6c,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x6d,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x6e,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x6f,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x7b,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshlrev_b16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshlrev_b16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x03,0x00]
-
-v_lshlrev_b16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x05,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcb,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcd,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcf,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd7,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd9,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xdb,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xdd,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xdf,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf7,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf9,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshlrev_b16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshrrev_b16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x56]
-
-v_lshrrev_b16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x57]
-
-v_lshrrev_b16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x56]
-
-v_lshrrev_b16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x56,0x00,0x38,0x00,0x00]
-
-v_lshrrev_b16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x56,0x00,0xc4,0x00,0x00]
-
-v_lshrrev_b16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x56,0x0b,0xfe,0x00,0x00]
-
-v_lshrrev_b16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x56,0x56,0x34,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x56]
-
-v_lshrrev_b16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2b,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x65,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x66,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x67,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x6c,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x6d,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x6e,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x6f,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x7b,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshrrev_b16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshrrev_b16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x03,0x00]
-
-v_lshrrev_b16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x05,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcb,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcd,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcf,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd7,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd9,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xdb,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xdd,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xdf,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf7,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf9,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshrrev_b16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_ashrrev_i16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x58]
-
-v_ashrrev_i16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x59]
-
-v_ashrrev_i16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x58]
-
-v_ashrrev_i16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x58,0x00,0x38,0x00,0x00]
-
-v_ashrrev_i16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x58,0x00,0xc4,0x00,0x00]
-
-v_ashrrev_i16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x58,0x0b,0xfe,0x00,0x00]
-
-v_ashrrev_i16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x58,0x56,0x34,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x58]
-
-v_ashrrev_i16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x65,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x66,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x67,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x6c,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x6d,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x6e,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x6f,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x7b,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_ashrrev_i16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_ashrrev_i16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x03,0x00]
-
-v_ashrrev_i16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x05,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcb,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcd,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcf,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd7,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd9,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xdb,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xdd,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xdf,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf7,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf9,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_ashrrev_i16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x5a]
-
-v_max_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x5b]
-
-v_max_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x5a]
-
-v_max_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x5a]
-
-v_max_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x5a]
-
-v_max_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x5a]
-
-v_max_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x5a]
-
-v_max_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x5a]
-
-v_max_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x5a]
-
-v_max_f16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x5a]
-
-v_max_f16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x5a]
-
-v_max_f16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x5a]
-
-v_max_f16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x5a]
-
-v_max_f16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x5a]
-
-v_max_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x5a]
-
-v_max_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x5a]
-
-v_max_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x5a]
-
-v_max_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x5a]
-
-v_max_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x5a]
-
-v_max_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x5a]
-
-v_max_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x5a]
-
-v_max_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x5a,0x0b,0xfe,0x00,0x00]
-
-v_max_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x5a,0x56,0x34,0x00,0x00]
-
-v_max_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x5a]
-
-v_max_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x6c,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x6d,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x6e,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x6f,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x7b,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0xf0,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0xf7,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_f16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd9,0x00,0x00]
-
-v_max_f16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xdb,0x00,0x00]
-
-v_max_f16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xdd,0x00,0x00]
-
-v_max_f16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xdf,0x00,0x00]
-
-v_max_f16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf7,0x00,0x00]
-
-v_max_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xe1,0x01,0x00]
-
-v_max_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xef,0x01,0x00]
-
-v_max_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x20]
-
-v_max_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x40]
-
-v_max_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x60]
-
-v_max_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x5c]
-
-v_min_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x5d]
-
-v_min_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x5c]
-
-v_min_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x5c]
-
-v_min_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x5c]
-
-v_min_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x5c]
-
-v_min_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x5c]
-
-v_min_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x5c]
-
-v_min_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x5c]
-
-v_min_f16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x5c]
-
-v_min_f16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x5c]
-
-v_min_f16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x5c]
-
-v_min_f16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x5c]
-
-v_min_f16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x5c]
-
-v_min_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x5c]
-
-v_min_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x5c]
-
-v_min_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x5c]
-
-v_min_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x5c]
-
-v_min_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x5c]
-
-v_min_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x5c]
-
-v_min_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x5c]
-
-v_min_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x5c,0x0b,0xfe,0x00,0x00]
-
-v_min_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x5c,0x56,0x34,0x00,0x00]
-
-v_min_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x5c]
-
-v_min_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x6c,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x6d,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x6e,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x6f,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x7b,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0xf0,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0xf7,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_f16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd9,0x00,0x00]
-
-v_min_f16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xdb,0x00,0x00]
-
-v_min_f16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xdd,0x00,0x00]
-
-v_min_f16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xdf,0x00,0x00]
-
-v_min_f16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf7,0x00,0x00]
-
-v_min_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xe1,0x01,0x00]
-
-v_min_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xef,0x01,0x00]
-
-v_min_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x20]
-
-v_min_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x40]
-
-v_min_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x60]
-
-v_min_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x5e]
-
-v_max_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x5f]
-
-v_max_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x5e]
-
-v_max_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x5e]
-
-v_max_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x5e]
-
-v_max_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x5e]
-
-v_max_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x5e]
-
-v_max_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x5e]
-
-v_max_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x5e]
-
-v_max_u16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x5e]
-
-v_max_u16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x5e]
-
-v_max_u16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x5e]
-
-v_max_u16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x5e]
-
-v_max_u16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x5e]
-
-v_max_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x5e]
-
-v_max_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x5e]
-
-v_max_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x5e]
-
-v_max_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x5e]
-
-v_max_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x5e]
-
-v_max_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x5e,0x00,0x38,0x00,0x00]
-
-v_max_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x5e,0x00,0xc4,0x00,0x00]
-
-v_max_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x5e,0x0b,0xfe,0x00,0x00]
-
-v_max_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x5e,0x56,0x34,0x00,0x00]
-
-v_max_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x5e]
-
-v_max_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2f,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x6c,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x6d,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x6e,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x6f,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x7b,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_u16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd9,0x00,0x00]
-
-v_max_u16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xdb,0x00,0x00]
-
-v_max_u16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xdd,0x00,0x00]
-
-v_max_u16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xdf,0x00,0x00]
-
-v_max_u16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf7,0x00,0x00]
-
-v_max_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_i16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x60]
-
-v_max_i16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x61]
-
-v_max_i16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x60]
-
-v_max_i16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x60]
-
-v_max_i16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x60]
-
-v_max_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x60]
-
-v_max_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x60]
-
-v_max_i16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x60]
-
-v_max_i16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x60]
-
-v_max_i16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x60]
-
-v_max_i16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x60]
-
-v_max_i16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x60]
-
-v_max_i16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x60]
-
-v_max_i16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x60]
-
-v_max_i16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x60]
-
-v_max_i16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x60]
-
-v_max_i16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x60]
-
-v_max_i16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x60]
-
-v_max_i16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x60]
-
-v_max_i16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x60,0x00,0x38,0x00,0x00]
-
-v_max_i16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x60,0x00,0xc4,0x00,0x00]
-
-v_max_i16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x60,0x0b,0xfe,0x00,0x00]
-
-v_max_i16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x60,0x56,0x34,0x00,0x00]
-
-v_max_i16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x60]
-
-v_max_i16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_i16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_i16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_i16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x6c,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x6d,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x6e,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x6f,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x7b,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_i16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_i16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_i16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_i16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_i16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_i16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_i16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_i16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_i16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd9,0x00,0x00]
-
-v_max_i16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xdb,0x00,0x00]
-
-v_max_i16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xdd,0x00,0x00]
-
-v_max_i16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xdf,0x00,0x00]
-
-v_max_i16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf7,0x00,0x00]
-
-v_max_i16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_i16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_i16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_i16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_i16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_i16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_i16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x62]
-
-v_min_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x63]
-
-v_min_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x62]
-
-v_min_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x62]
-
-v_min_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x62]
-
-v_min_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x62]
-
-v_min_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x62]
-
-v_min_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x62]
-
-v_min_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x62]
-
-v_min_u16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x62]
-
-v_min_u16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x62]
-
-v_min_u16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x62]
-
-v_min_u16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x62]
-
-v_min_u16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x62]
-
-v_min_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x62]
-
-v_min_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x62]
-
-v_min_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x62]
-
-v_min_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x62]
-
-v_min_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x62]
-
-v_min_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x62,0x00,0x38,0x00,0x00]
-
-v_min_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x62,0x00,0xc4,0x00,0x00]
-
-v_min_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x62,0x0b,0xfe,0x00,0x00]
-
-v_min_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x62,0x56,0x34,0x00,0x00]
-
-v_min_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x62]
-
-v_min_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x31,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x6c,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x6d,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x6e,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x6f,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x7b,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_u16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd9,0x00,0x00]
-
-v_min_u16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xdb,0x00,0x00]
-
-v_min_u16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xdd,0x00,0x00]
-
-v_min_u16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xdf,0x00,0x00]
-
-v_min_u16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf7,0x00,0x00]
-
-v_min_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_i16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x64]
-
-v_min_i16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x65]
-
-v_min_i16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x64]
-
-v_min_i16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x64]
-
-v_min_i16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x64]
-
-v_min_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x64]
-
-v_min_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x64]
-
-v_min_i16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x64]
-
-v_min_i16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x64]
-
-v_min_i16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x64]
-
-v_min_i16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x64]
-
-v_min_i16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x64]
-
-v_min_i16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x64]
-
-v_min_i16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x64]
-
-v_min_i16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x64]
-
-v_min_i16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x64]
-
-v_min_i16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x64]
-
-v_min_i16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x64]
-
-v_min_i16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x64]
-
-v_min_i16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x64,0x00,0x38,0x00,0x00]
-
-v_min_i16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x64,0x00,0xc4,0x00,0x00]
-
-v_min_i16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x64,0x0b,0xfe,0x00,0x00]
-
-v_min_i16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x64,0x56,0x34,0x00,0x00]
-
-v_min_i16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x64]
-
-v_min_i16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_i16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x32,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_i16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_i16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x6c,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x6d,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x6e,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x6f,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x7b,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_i16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_i16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_i16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_i16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_i16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_i16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_i16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_i16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_i16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd9,0x00,0x00]
-
-v_min_i16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xdb,0x00,0x00]
-
-v_min_i16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xdd,0x00,0x00]
-
-v_min_i16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xdf,0x00,0x00]
-
-v_min_i16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf7,0x00,0x00]
-
-v_min_i16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_i16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_i16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_i16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_i16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_i16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_i16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_ldexp_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x66]
-
-v_ldexp_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x67]
-
-v_ldexp_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x66]
-
-v_ldexp_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, tba_lo, v2
-// CHECK: [0x6c,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, tba_hi, v2
-// CHECK: [0x6d,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, tma_lo, v2
-// CHECK: [0x6e,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, tma_hi, v2
-// CHECK: [0x6f,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, ttmp11, v2
-// CHECK: [0x7b,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x66,0x0b,0xfe,0x00,0x00]
-
-v_ldexp_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x66,0x56,0x34,0x00,0x00]
-
-v_ldexp_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x66]
-
-v_ldexp_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x33,0xd1,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0xff,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x65,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x66,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x67,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x6b,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x6c,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x6d,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x6e,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x6f,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x7b,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x7c,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x7f,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x80,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xff,0x03,0x00]
-
-v_ldexp_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcb,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcd,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd9,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xdb,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xdd,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xdf,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf7,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xff,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x01,0x01,0x00]
-
-v_ldexp_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x83,0x01,0x00]
-
-v_ldexp_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xef,0x01,0x00]
-
-v_ldexp_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x02,0x20]
-
-v_ldexp_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x33,0xd1,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x33,0xd1,0x01,0x05,0x02,0x00]
-
-v_mad_legacy_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_legacy_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_legacy_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_legacy_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xb6,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xba,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xbe,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xee,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_legacy_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_legacy_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_legacy_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_legacy_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x24]
-
-v_mad_legacy_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x44]
-
-v_mad_legacy_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x84]
-
-v_mad_legacy_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_mad_legacy_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_mad_legacy_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x14]
-
-v_mad_legacy_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_mad_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mad_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_mad_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mad_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_mad_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_mad_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mad_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mad_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mad_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mad_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mad_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mad_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xb6,0x01]
-
-v_mad_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xba,0x01]
-
-v_mad_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xbe,0x01]
-
-v_mad_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xee,0x01]
-
-v_mad_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x24]
-
-v_mad_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x44]
-
-v_mad_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x84]
-
-v_mad_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_mad_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_mad_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x14]
-
-v_mad_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_mad_i32_i24 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_i32_i24 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_i32_i24 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_i32_i24 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_i32_i24 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_i32_i24 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_i32_i24 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_i32_i24 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_i32_i24 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mad_i32_i24 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xb6,0x01]
-
-v_mad_i32_i24 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xba,0x01]
-
-v_mad_i32_i24 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xbe,0x01]
-
-v_mad_i32_i24 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xee,0x01]
-
-v_mad_i32_i24 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_i32_i24 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_i32_i24 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_i32_i24 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_i32_i24 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_i32_i24 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_i32_i24 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_i32_i24 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_u32_u24 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_u32_u24 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_u32_u24 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_u32_u24 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_u32_u24 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_u32_u24 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_u32_u24 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_u32_u24 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mad_u32_u24 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xb6,0x01]
-
-v_mad_u32_u24 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xba,0x01]
-
-v_mad_u32_u24 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xbe,0x01]
-
-v_mad_u32_u24 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xee,0x01]
-
-v_mad_u32_u24 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_u32_u24 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_u32_u24 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_u32_u24 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_u32_u24 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_u32_u24 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_u32_u24 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_u32_u24 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cubeid_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cubeid_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cubeid_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x96,0x01]
-
-v_cubeid_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cubeid_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cubeid_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cubeid_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xae,0x01]
-
-v_cubeid_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xb2,0x01]
-
-v_cubeid_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xb6,0x01]
-
-v_cubeid_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xba,0x01]
-
-v_cubeid_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xbe,0x01]
-
-v_cubeid_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xee,0x01]
-
-v_cubeid_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cubeid_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cubeid_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cubeid_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x02,0x02]
-
-v_cubeid_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x06,0x03]
-
-v_cubeid_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cubeid_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xde,0x03]
-
-v_cubeid_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cubeid_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x44]
-
-v_cubeid_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x84]
-
-v_cubeid_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_cubeid_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_cubeid_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x14]
-
-v_cubeid_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_cubesc_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cubesc_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cubesc_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cubesc_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x96,0x01]
-
-v_cubesc_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cubesc_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cubesc_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cubesc_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xae,0x01]
-
-v_cubesc_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xb2,0x01]
-
-v_cubesc_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xb6,0x01]
-
-v_cubesc_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xba,0x01]
-
-v_cubesc_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xbe,0x01]
-
-v_cubesc_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xee,0x01]
-
-v_cubesc_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cubesc_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cubesc_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cubesc_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x02,0x02]
-
-v_cubesc_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x06,0x03]
-
-v_cubesc_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cubesc_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xde,0x03]
-
-v_cubesc_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cubesc_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x44]
-
-v_cubesc_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x84]
-
-v_cubesc_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_cubesc_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_cubesc_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x14]
-
-v_cubesc_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_cubetc_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cubetc_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cubetc_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cubetc_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x96,0x01]
-
-v_cubetc_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cubetc_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cubetc_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cubetc_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xae,0x01]
-
-v_cubetc_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xb2,0x01]
-
-v_cubetc_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xb6,0x01]
-
-v_cubetc_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xba,0x01]
-
-v_cubetc_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xbe,0x01]
-
-v_cubetc_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xee,0x01]
-
-v_cubetc_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cubetc_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cubetc_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cubetc_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x02,0x02]
-
-v_cubetc_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x06,0x03]
-
-v_cubetc_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cubetc_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xde,0x03]
-
-v_cubetc_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cubetc_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x44]
-
-v_cubetc_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x84]
-
-v_cubetc_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_cubetc_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_cubetc_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x14]
-
-v_cubetc_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_cubema_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cubema_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cubema_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cubema_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cubema_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cubema_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cubema_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cubema_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_cubema_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_cubema_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_cubema_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_cubema_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_cubema_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cubema_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cubema_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cubema_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cubema_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cubema_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cubema_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cubema_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cubema_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cubema_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x96,0x01]
-
-v_cubema_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cubema_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cubema_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cubema_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xae,0x01]
-
-v_cubema_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xb2,0x01]
-
-v_cubema_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xb6,0x01]
-
-v_cubema_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xba,0x01]
-
-v_cubema_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xbe,0x01]
-
-v_cubema_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xee,0x01]
-
-v_cubema_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cubema_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cubema_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cubema_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x02,0x02]
-
-v_cubema_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x06,0x03]
-
-v_cubema_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cubema_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xde,0x03]
-
-v_cubema_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cubema_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x44]
-
-v_cubema_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x84]
-
-v_cubema_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_cubema_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_cubema_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x14]
-
-v_cubema_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_bfe_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfe_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfe_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0xff,0x05,0x0e,0x04]
-
-v_bfe_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x65,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x66,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x67,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x80,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xff,0x0f,0x04]
-
-v_bfe_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0c,0x04]
-
-v_bfe_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_bfe_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_bfe_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_bfe_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_bfe_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_bfe_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_bfe_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_bfe_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_bfe_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_bfe_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_bfe_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_bfe_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_bfe_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xff,0x0c,0x04]
-
-v_bfe_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x01,0x0d,0x04]
-
-v_bfe_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x83,0x0d,0x04]
-
-v_bfe_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_bfe_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xef,0x0d,0x04]
-
-v_bfe_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfe,0x07]
-
-v_bfe_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x00]
-
-v_bfe_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x96,0x01]
-
-v_bfe_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x9a,0x01]
-
-v_bfe_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x9e,0x01]
-
-v_bfe_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xaa,0x01]
-
-v_bfe_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xae,0x01]
-
-v_bfe_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xb2,0x01]
-
-v_bfe_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xb6,0x01]
-
-v_bfe_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xba,0x01]
-
-v_bfe_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xbe,0x01]
-
-v_bfe_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xee,0x01]
-
-v_bfe_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xf2,0x01]
-
-v_bfe_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfa,0x01]
-
-v_bfe_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfe,0x01]
-
-v_bfe_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x02,0x02]
-
-v_bfe_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x06,0x03]
-
-v_bfe_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xc2,0x03]
-
-v_bfe_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xde,0x03]
-
-v_bfe_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfe_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfe_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0xff,0x05,0x0e,0x04]
-
-v_bfe_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x65,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x66,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x67,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x80,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xff,0x0f,0x04]
-
-v_bfe_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0c,0x04]
-
-v_bfe_i32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_bfe_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_bfe_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_bfe_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_bfe_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_bfe_i32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_bfe_i32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_bfe_i32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_bfe_i32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_bfe_i32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_bfe_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_bfe_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_bfe_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xff,0x0c,0x04]
-
-v_bfe_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x01,0x0d,0x04]
-
-v_bfe_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x83,0x0d,0x04]
-
-v_bfe_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_bfe_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xef,0x0d,0x04]
-
-v_bfe_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfe,0x07]
-
-v_bfe_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x00]
-
-v_bfe_i32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x96,0x01]
-
-v_bfe_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x9a,0x01]
-
-v_bfe_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x9e,0x01]
-
-v_bfe_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xaa,0x01]
-
-v_bfe_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xae,0x01]
-
-v_bfe_i32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xb2,0x01]
-
-v_bfe_i32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xb6,0x01]
-
-v_bfe_i32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xba,0x01]
-
-v_bfe_i32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xbe,0x01]
-
-v_bfe_i32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xee,0x01]
-
-v_bfe_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xf2,0x01]
-
-v_bfe_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfa,0x01]
-
-v_bfe_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfe,0x01]
-
-v_bfe_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x02,0x02]
-
-v_bfe_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x06,0x03]
-
-v_bfe_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xc2,0x03]
-
-v_bfe_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xde,0x03]
-
-v_bfi_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfi_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xca,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfi_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0xff,0x05,0x0e,0x04]
-
-v_bfi_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x65,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x66,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x67,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x80,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xff,0x0f,0x04]
-
-v_bfi_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0c,0x04]
-
-v_bfi_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_bfi_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_bfi_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_bfi_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_bfi_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_bfi_b32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_bfi_b32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_bfi_b32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_bfi_b32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_bfi_b32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_bfi_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_bfi_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_bfi_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xff,0x0c,0x04]
-
-v_bfi_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x01,0x0d,0x04]
-
-v_bfi_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x83,0x0d,0x04]
-
-v_bfi_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_bfi_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xef,0x0d,0x04]
-
-v_bfi_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfe,0x07]
-
-v_bfi_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0e,0x00]
-
-v_bfi_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x96,0x01]
-
-v_bfi_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x9a,0x01]
-
-v_bfi_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x9e,0x01]
-
-v_bfi_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xaa,0x01]
-
-v_bfi_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xae,0x01]
-
-v_bfi_b32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xb2,0x01]
-
-v_bfi_b32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xb6,0x01]
-
-v_bfi_b32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xba,0x01]
-
-v_bfi_b32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xbe,0x01]
-
-v_bfi_b32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xee,0x01]
-
-v_bfi_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xf2,0x01]
-
-v_bfi_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfa,0x01]
-
-v_bfi_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfe,0x01]
-
-v_bfi_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x02,0x02]
-
-v_bfi_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x06,0x03]
-
-v_bfi_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xc2,0x03]
-
-v_bfi_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xde,0x03]
-
-v_fma_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0xff,0x05,0x0e,0x04]
-
-v_fma_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x04,0x0e,0x04]
-
-v_fma_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x65,0x04,0x0e,0x04]
-
-v_fma_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x66,0x04,0x0e,0x04]
-
-v_fma_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x67,0x04,0x0e,0x04]
-
-v_fma_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_fma_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_fma_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_fma_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_fma_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_fma_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_fma_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_fma_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_fma_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_fma_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_fma_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x80,0x04,0x0e,0x04]
-
-v_fma_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_fma_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_fma_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_fma_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xff,0x0f,0x04]
-
-v_fma_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0c,0x04]
-
-v_fma_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_fma_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_fma_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_fma_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_fma_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_fma_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_fma_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_fma_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_fma_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_fma_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_fma_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_fma_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_fma_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xff,0x0c,0x04]
-
-v_fma_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x01,0x0d,0x04]
-
-v_fma_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x83,0x0d,0x04]
-
-v_fma_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_fma_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xef,0x0d,0x04]
-
-v_fma_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfe,0x07]
-
-v_fma_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x00]
-
-v_fma_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x96,0x01]
-
-v_fma_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x9a,0x01]
-
-v_fma_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x9e,0x01]
-
-v_fma_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xaa,0x01]
-
-v_fma_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xae,0x01]
-
-v_fma_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xb2,0x01]
-
-v_fma_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xb6,0x01]
-
-v_fma_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xba,0x01]
-
-v_fma_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xbe,0x01]
-
-v_fma_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xee,0x01]
-
-v_fma_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xf2,0x01]
-
-v_fma_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfa,0x01]
-
-v_fma_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfe,0x01]
-
-v_fma_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x02,0x02]
-
-v_fma_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x06,0x03]
-
-v_fma_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xc2,0x03]
-
-v_fma_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xde,0x03]
-
-v_fma_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x24]
-
-v_fma_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x44]
-
-v_fma_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x84]
-
-v_fma_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_fma_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_fma_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x14]
-
-v_fma_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[2:3], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x02,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[4:5], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x04,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[100:101], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x64,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x66,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], tba, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], tma, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x7a,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], exec, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x80,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfd,0x0f,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[4:5], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x09,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[6:7], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x0d,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[100:101], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xc9,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], tba, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], tma, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xf5,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], exec, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x01,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x83,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xef,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xfa,0x07]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[6:7]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x1a,0x00]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[8:9]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x22,0x00]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[100:101]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x92,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], flat_scratch
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x9a,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xaa,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], tba
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xb2,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], tma
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xba,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xea,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], exec
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xfa,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], 0
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x02,0x02]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -1
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x06,0x03]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xc2,0x03]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xde,0x03]
-
-v_fma_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x24]
-
-v_fma_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x44]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x84]
-
-v_fma_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_fma_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// CHECK: [0x05,0x01,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// CHECK: [0x05,0x02,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// CHECK: [0x05,0x04,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// CHECK: [0x05,0x07,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// CHECK: [0x05,0x80,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x14]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_lerp_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_lerp_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_lerp_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0xff,0x05,0x0e,0x04]
-
-v_lerp_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x65,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x66,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x67,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x80,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xff,0x0f,0x04]
-
-v_lerp_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0c,0x04]
-
-v_lerp_u8 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_lerp_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_lerp_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_lerp_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_lerp_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_lerp_u8 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_lerp_u8 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_lerp_u8 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_lerp_u8 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_lerp_u8 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_lerp_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_lerp_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_lerp_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xff,0x0c,0x04]
-
-v_lerp_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x01,0x0d,0x04]
-
-v_lerp_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x83,0x0d,0x04]
-
-v_lerp_u8 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_lerp_u8 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xef,0x0d,0x04]
-
-v_lerp_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfe,0x07]
-
-v_lerp_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x00]
-
-v_lerp_u8 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x96,0x01]
-
-v_lerp_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x9a,0x01]
-
-v_lerp_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x9e,0x01]
-
-v_lerp_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xaa,0x01]
-
-v_lerp_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xae,0x01]
-
-v_lerp_u8 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xb2,0x01]
-
-v_lerp_u8 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xb6,0x01]
-
-v_lerp_u8 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xba,0x01]
-
-v_lerp_u8 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xbe,0x01]
-
-v_lerp_u8 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xee,0x01]
-
-v_lerp_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xf2,0x01]
-
-v_lerp_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfa,0x01]
-
-v_lerp_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfe,0x01]
-
-v_lerp_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x02,0x02]
-
-v_lerp_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x06,0x03]
-
-v_lerp_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xc2,0x03]
-
-v_lerp_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xde,0x03]
-
-v_alignbit_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0e,0x04]
-
-v_alignbit_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xce,0xd1,0x01,0x05,0x0e,0x04]
-
-v_alignbit_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0xff,0x05,0x0e,0x04]
-
-v_alignbit_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x65,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x66,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x67,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x80,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xff,0x0f,0x04]
-
-v_alignbit_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xff,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x01,0x0d,0x04]
-
-v_alignbit_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x83,0x0d,0x04]
-
-v_alignbit_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_alignbit_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xef,0x0d,0x04]
-
-v_alignbit_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x07]
-
-v_alignbit_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0e,0x00]
-
-v_alignbit_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x96,0x01]
-
-v_alignbit_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x9a,0x01]
-
-v_alignbit_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x9e,0x01]
-
-v_alignbit_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xaa,0x01]
-
-v_alignbit_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xae,0x01]
-
-v_alignbit_b32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xb2,0x01]
-
-v_alignbit_b32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xb6,0x01]
-
-v_alignbit_b32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xba,0x01]
-
-v_alignbit_b32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xbe,0x01]
-
-v_alignbit_b32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xee,0x01]
-
-v_alignbit_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xf2,0x01]
-
-v_alignbit_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfa,0x01]
-
-v_alignbit_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x01]
-
-v_alignbit_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x02,0x02]
-
-v_alignbit_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x06,0x03]
-
-v_alignbit_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xc2,0x03]
-
-v_alignbit_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xde,0x03]
-
-v_alignbyte_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0xff,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x65,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x66,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x67,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x80,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xff,0x0f,0x04]
-
-v_alignbyte_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xff,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x01,0x0d,0x04]
-
-v_alignbyte_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x83,0x0d,0x04]
-
-v_alignbyte_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_alignbyte_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xef,0x0d,0x04]
-
-v_alignbyte_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x07]
-
-v_alignbyte_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x00]
-
-v_alignbyte_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x96,0x01]
-
-v_alignbyte_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x9a,0x01]
-
-v_alignbyte_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x9e,0x01]
-
-v_alignbyte_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xaa,0x01]
-
-v_alignbyte_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xae,0x01]
-
-v_alignbyte_b32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xb2,0x01]
-
-v_alignbyte_b32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xb6,0x01]
-
-v_alignbyte_b32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xba,0x01]
-
-v_alignbyte_b32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xbe,0x01]
-
-v_alignbyte_b32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xee,0x01]
-
-v_alignbyte_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xf2,0x01]
-
-v_alignbyte_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfa,0x01]
-
-v_alignbyte_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x01]
-
-v_alignbyte_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x02,0x02]
-
-v_alignbyte_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x06,0x03]
-
-v_alignbyte_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xc2,0x03]
-
-v_alignbyte_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xde,0x03]
-
-v_min3_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0xff,0x05,0x0e,0x04]
-
-v_min3_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x04,0x0e,0x04]
-
-v_min3_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x65,0x04,0x0e,0x04]
-
-v_min3_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x66,0x04,0x0e,0x04]
-
-v_min3_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x67,0x04,0x0e,0x04]
-
-v_min3_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_min3_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_min3_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_min3_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_min3_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_min3_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_min3_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_min3_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_min3_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_min3_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_min3_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x80,0x04,0x0e,0x04]
-
-v_min3_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_min3_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_min3_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_min3_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xff,0x0f,0x04]
-
-v_min3_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0c,0x04]
-
-v_min3_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_min3_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_min3_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_min3_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_min3_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_min3_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_min3_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_min3_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_min3_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_min3_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_min3_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_min3_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_min3_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xff,0x0c,0x04]
-
-v_min3_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x01,0x0d,0x04]
-
-v_min3_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x83,0x0d,0x04]
-
-v_min3_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_min3_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xef,0x0d,0x04]
-
-v_min3_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfe,0x07]
-
-v_min3_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x00]
-
-v_min3_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x96,0x01]
-
-v_min3_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x9a,0x01]
-
-v_min3_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x9e,0x01]
-
-v_min3_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xaa,0x01]
-
-v_min3_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xae,0x01]
-
-v_min3_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xb2,0x01]
-
-v_min3_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xb6,0x01]
-
-v_min3_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xba,0x01]
-
-v_min3_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xbe,0x01]
-
-v_min3_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xee,0x01]
-
-v_min3_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xf2,0x01]
-
-v_min3_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfa,0x01]
-
-v_min3_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x02,0x02]
-
-v_min3_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x06,0x03]
-
-v_min3_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xc2,0x03]
-
-v_min3_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xde,0x03]
-
-v_min3_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x24]
-
-v_min3_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x44]
-
-v_min3_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x84]
-
-v_min3_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_min3_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_min3_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x14]
-
-v_min3_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_min3_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0xff,0x05,0x0e,0x04]
-
-v_min3_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x04,0x0e,0x04]
-
-v_min3_i32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x65,0x04,0x0e,0x04]
-
-v_min3_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x66,0x04,0x0e,0x04]
-
-v_min3_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x67,0x04,0x0e,0x04]
-
-v_min3_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_min3_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_min3_i32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_min3_i32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_min3_i32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_min3_i32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_min3_i32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_min3_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_min3_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_min3_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_min3_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x80,0x04,0x0e,0x04]
-
-v_min3_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_min3_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_min3_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_min3_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xff,0x0f,0x04]
-
-v_min3_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0c,0x04]
-
-v_min3_i32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_min3_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_min3_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_min3_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_min3_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_min3_i32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_min3_i32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_min3_i32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_min3_i32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_min3_i32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_min3_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_min3_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_min3_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xff,0x0c,0x04]
-
-v_min3_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x01,0x0d,0x04]
-
-v_min3_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x83,0x0d,0x04]
-
-v_min3_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_min3_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xef,0x0d,0x04]
-
-v_min3_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfe,0x07]
-
-v_min3_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x00]
-
-v_min3_i32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x96,0x01]
-
-v_min3_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x9a,0x01]
-
-v_min3_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x9e,0x01]
-
-v_min3_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xaa,0x01]
-
-v_min3_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xae,0x01]
-
-v_min3_i32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xb2,0x01]
-
-v_min3_i32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xb6,0x01]
-
-v_min3_i32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xba,0x01]
-
-v_min3_i32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xbe,0x01]
-
-v_min3_i32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xee,0x01]
-
-v_min3_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xf2,0x01]
-
-v_min3_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfa,0x01]
-
-v_min3_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x02,0x02]
-
-v_min3_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x06,0x03]
-
-v_min3_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xc2,0x03]
-
-v_min3_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xde,0x03]
-
-v_min3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0xff,0x05,0x0e,0x04]
-
-v_min3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x04,0x0e,0x04]
-
-v_min3_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x65,0x04,0x0e,0x04]
-
-v_min3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x66,0x04,0x0e,0x04]
-
-v_min3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x67,0x04,0x0e,0x04]
-
-v_min3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_min3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_min3_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_min3_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_min3_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_min3_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_min3_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_min3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_min3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_min3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_min3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x80,0x04,0x0e,0x04]
-
-v_min3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_min3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_min3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_min3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xff,0x0f,0x04]
-
-v_min3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0c,0x04]
-
-v_min3_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_min3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_min3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_min3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_min3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_min3_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_min3_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_min3_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_min3_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_min3_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_min3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_min3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_min3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xff,0x0c,0x04]
-
-v_min3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x01,0x0d,0x04]
-
-v_min3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x83,0x0d,0x04]
-
-v_min3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_min3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xef,0x0d,0x04]
-
-v_min3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfe,0x07]
-
-v_min3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x00]
-
-v_min3_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x96,0x01]
-
-v_min3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x9a,0x01]
-
-v_min3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x9e,0x01]
-
-v_min3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xaa,0x01]
-
-v_min3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xae,0x01]
-
-v_min3_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xb2,0x01]
-
-v_min3_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xb6,0x01]
-
-v_min3_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xba,0x01]
-
-v_min3_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xbe,0x01]
-
-v_min3_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xee,0x01]
-
-v_min3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xf2,0x01]
-
-v_min3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfa,0x01]
-
-v_min3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x02,0x02]
-
-v_min3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x06,0x03]
-
-v_min3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xc2,0x03]
-
-v_min3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xde,0x03]
-
-v_max3_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0xff,0x05,0x0e,0x04]
-
-v_max3_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x04,0x0e,0x04]
-
-v_max3_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x65,0x04,0x0e,0x04]
-
-v_max3_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x66,0x04,0x0e,0x04]
-
-v_max3_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x67,0x04,0x0e,0x04]
-
-v_max3_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_max3_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_max3_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_max3_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_max3_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_max3_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_max3_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_max3_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_max3_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_max3_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_max3_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x80,0x04,0x0e,0x04]
-
-v_max3_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_max3_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_max3_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_max3_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xff,0x0f,0x04]
-
-v_max3_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0c,0x04]
-
-v_max3_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_max3_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_max3_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_max3_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_max3_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_max3_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_max3_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_max3_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_max3_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_max3_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_max3_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_max3_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_max3_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xff,0x0c,0x04]
-
-v_max3_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x01,0x0d,0x04]
-
-v_max3_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x83,0x0d,0x04]
-
-v_max3_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_max3_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xef,0x0d,0x04]
-
-v_max3_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfe,0x07]
-
-v_max3_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x00]
-
-v_max3_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x96,0x01]
-
-v_max3_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x9a,0x01]
-
-v_max3_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x9e,0x01]
-
-v_max3_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xaa,0x01]
-
-v_max3_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xae,0x01]
-
-v_max3_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xb2,0x01]
-
-v_max3_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xb6,0x01]
-
-v_max3_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xba,0x01]
-
-v_max3_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xbe,0x01]
-
-v_max3_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xee,0x01]
-
-v_max3_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xf2,0x01]
-
-v_max3_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfa,0x01]
-
-v_max3_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfe,0x01]
-
-v_max3_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x02,0x02]
-
-v_max3_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x06,0x03]
-
-v_max3_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xc2,0x03]
-
-v_max3_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xde,0x03]
-
-v_max3_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x24]
-
-v_max3_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x44]
-
-v_max3_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x84]
-
-v_max3_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_max3_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_max3_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x14]
-
-v_max3_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_max3_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0xff,0x05,0x0e,0x04]
-
-v_max3_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x04,0x0e,0x04]
-
-v_max3_i32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x65,0x04,0x0e,0x04]
-
-v_max3_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x66,0x04,0x0e,0x04]
-
-v_max3_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x67,0x04,0x0e,0x04]
-
-v_max3_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_max3_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_max3_i32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_max3_i32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_max3_i32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_max3_i32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_max3_i32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_max3_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_max3_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_max3_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_max3_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x80,0x04,0x0e,0x04]
-
-v_max3_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_max3_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_max3_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_max3_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xff,0x0f,0x04]
-
-v_max3_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0c,0x04]
-
-v_max3_i32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_max3_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_max3_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_max3_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_max3_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_max3_i32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_max3_i32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_max3_i32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_max3_i32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_max3_i32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_max3_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_max3_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_max3_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xff,0x0c,0x04]
-
-v_max3_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x01,0x0d,0x04]
-
-v_max3_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x83,0x0d,0x04]
-
-v_max3_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_max3_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xef,0x0d,0x04]
-
-v_max3_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfe,0x07]
-
-v_max3_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x00]
-
-v_max3_i32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x96,0x01]
-
-v_max3_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x9a,0x01]
-
-v_max3_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x9e,0x01]
-
-v_max3_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xaa,0x01]
-
-v_max3_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xae,0x01]
-
-v_max3_i32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xb2,0x01]
-
-v_max3_i32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xb6,0x01]
-
-v_max3_i32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xba,0x01]
-
-v_max3_i32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xbe,0x01]
-
-v_max3_i32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xee,0x01]
-
-v_max3_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xf2,0x01]
-
-v_max3_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfa,0x01]
-
-v_max3_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfe,0x01]
-
-v_max3_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x02,0x02]
-
-v_max3_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x06,0x03]
-
-v_max3_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xc2,0x03]
-
-v_max3_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xde,0x03]
-
-v_max3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0xff,0x05,0x0e,0x04]
-
-v_max3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x04,0x0e,0x04]
-
-v_max3_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x65,0x04,0x0e,0x04]
-
-v_max3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x66,0x04,0x0e,0x04]
-
-v_max3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x67,0x04,0x0e,0x04]
-
-v_max3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_max3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_max3_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_max3_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_max3_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_max3_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_max3_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_max3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_max3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_max3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_max3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x80,0x04,0x0e,0x04]
-
-v_max3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_max3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_max3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_max3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xff,0x0f,0x04]
-
-v_max3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0c,0x04]
-
-v_max3_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_max3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_max3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_max3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_max3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_max3_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_max3_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_max3_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_max3_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_max3_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_max3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_max3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_max3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xff,0x0c,0x04]
-
-v_max3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x01,0x0d,0x04]
-
-v_max3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x83,0x0d,0x04]
-
-v_max3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_max3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xef,0x0d,0x04]
-
-v_max3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfe,0x07]
-
-v_max3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x00]
-
-v_max3_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x96,0x01]
-
-v_max3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x9a,0x01]
-
-v_max3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x9e,0x01]
-
-v_max3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xaa,0x01]
-
-v_max3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xae,0x01]
-
-v_max3_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xb2,0x01]
-
-v_max3_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xb6,0x01]
-
-v_max3_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xba,0x01]
-
-v_max3_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xbe,0x01]
-
-v_max3_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xee,0x01]
-
-v_max3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xf2,0x01]
-
-v_max3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfa,0x01]
-
-v_max3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfe,0x01]
-
-v_max3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x02,0x02]
-
-v_max3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x06,0x03]
-
-v_max3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xc2,0x03]
-
-v_max3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xde,0x03]
-
-v_med3_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0xff,0x05,0x0e,0x04]
-
-v_med3_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x04,0x0e,0x04]
-
-v_med3_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x65,0x04,0x0e,0x04]
-
-v_med3_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x66,0x04,0x0e,0x04]
-
-v_med3_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x67,0x04,0x0e,0x04]
-
-v_med3_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_med3_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_med3_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_med3_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_med3_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_med3_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_med3_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_med3_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_med3_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_med3_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_med3_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x80,0x04,0x0e,0x04]
-
-v_med3_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_med3_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_med3_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_med3_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xff,0x0f,0x04]
-
-v_med3_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0c,0x04]
-
-v_med3_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_med3_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_med3_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_med3_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_med3_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_med3_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_med3_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_med3_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_med3_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_med3_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_med3_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_med3_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_med3_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xff,0x0c,0x04]
-
-v_med3_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x01,0x0d,0x04]
-
-v_med3_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x83,0x0d,0x04]
-
-v_med3_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_med3_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xef,0x0d,0x04]
-
-v_med3_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfe,0x07]
-
-v_med3_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x00]
-
-v_med3_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x96,0x01]
-
-v_med3_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x9a,0x01]
-
-v_med3_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x9e,0x01]
-
-v_med3_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xaa,0x01]
-
-v_med3_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xae,0x01]
-
-v_med3_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xb2,0x01]
-
-v_med3_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xb6,0x01]
-
-v_med3_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xba,0x01]
-
-v_med3_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xbe,0x01]
-
-v_med3_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xee,0x01]
-
-v_med3_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xf2,0x01]
-
-v_med3_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfa,0x01]
-
-v_med3_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfe,0x01]
-
-v_med3_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x02,0x02]
-
-v_med3_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x06,0x03]
-
-v_med3_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xc2,0x03]
-
-v_med3_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xde,0x03]
-
-v_med3_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x24]
-
-v_med3_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x44]
-
-v_med3_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x84]
-
-v_med3_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_med3_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_med3_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x14]
-
-v_med3_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_med3_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0xff,0x05,0x0e,0x04]
-
-v_med3_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x04,0x0e,0x04]
-
-v_med3_i32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x65,0x04,0x0e,0x04]
-
-v_med3_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x66,0x04,0x0e,0x04]
-
-v_med3_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x67,0x04,0x0e,0x04]
-
-v_med3_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_med3_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_med3_i32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_med3_i32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_med3_i32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_med3_i32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_med3_i32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_med3_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_med3_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_med3_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_med3_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x80,0x04,0x0e,0x04]
-
-v_med3_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_med3_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_med3_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_med3_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xff,0x0f,0x04]
-
-v_med3_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0c,0x04]
-
-v_med3_i32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_med3_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_med3_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_med3_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_med3_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_med3_i32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_med3_i32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_med3_i32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_med3_i32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_med3_i32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_med3_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_med3_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_med3_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xff,0x0c,0x04]
-
-v_med3_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x01,0x0d,0x04]
-
-v_med3_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x83,0x0d,0x04]
-
-v_med3_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_med3_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xef,0x0d,0x04]
-
-v_med3_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfe,0x07]
-
-v_med3_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x00]
-
-v_med3_i32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x96,0x01]
-
-v_med3_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x9a,0x01]
-
-v_med3_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x9e,0x01]
-
-v_med3_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xaa,0x01]
-
-v_med3_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xae,0x01]
-
-v_med3_i32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xb2,0x01]
-
-v_med3_i32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xb6,0x01]
-
-v_med3_i32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xba,0x01]
-
-v_med3_i32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xbe,0x01]
-
-v_med3_i32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xee,0x01]
-
-v_med3_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xf2,0x01]
-
-v_med3_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfa,0x01]
-
-v_med3_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfe,0x01]
-
-v_med3_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x02,0x02]
-
-v_med3_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x06,0x03]
-
-v_med3_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xc2,0x03]
-
-v_med3_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xde,0x03]
-
-v_med3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0xff,0x05,0x0e,0x04]
-
-v_med3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x04,0x0e,0x04]
-
-v_med3_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x65,0x04,0x0e,0x04]
-
-v_med3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x66,0x04,0x0e,0x04]
-
-v_med3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x67,0x04,0x0e,0x04]
-
-v_med3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_med3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_med3_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_med3_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_med3_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_med3_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_med3_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_med3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_med3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_med3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_med3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x80,0x04,0x0e,0x04]
-
-v_med3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_med3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_med3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_med3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xff,0x0f,0x04]
-
-v_med3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0c,0x04]
-
-v_med3_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_med3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_med3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_med3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_med3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_med3_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_med3_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_med3_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_med3_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_med3_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_med3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_med3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_med3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xff,0x0c,0x04]
-
-v_med3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x01,0x0d,0x04]
-
-v_med3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x83,0x0d,0x04]
-
-v_med3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_med3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xef,0x0d,0x04]
-
-v_med3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfe,0x07]
-
-v_med3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x00]
-
-v_med3_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x96,0x01]
-
-v_med3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x9a,0x01]
-
-v_med3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x9e,0x01]
-
-v_med3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xaa,0x01]
-
-v_med3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xae,0x01]
-
-v_med3_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xb2,0x01]
-
-v_med3_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xb6,0x01]
-
-v_med3_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xba,0x01]
-
-v_med3_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xbe,0x01]
-
-v_med3_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xee,0x01]
-
-v_med3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xf2,0x01]
-
-v_med3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfa,0x01]
-
-v_med3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfe,0x01]
-
-v_med3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x02,0x02]
-
-v_med3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x06,0x03]
-
-v_med3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xc2,0x03]
-
-v_med3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0xff,0x05,0x0e,0x04]
-
-v_sad_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x04,0x0e,0x04]
-
-v_sad_u8 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x65,0x04,0x0e,0x04]
-
-v_sad_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x66,0x04,0x0e,0x04]
-
-v_sad_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x67,0x04,0x0e,0x04]
-
-v_sad_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_sad_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_sad_u8 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_sad_u8 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_sad_u8 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_sad_u8 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_sad_u8 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_sad_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_sad_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_sad_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_sad_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x80,0x04,0x0e,0x04]
-
-v_sad_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_sad_u8 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_sad_u8 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_sad_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xff,0x0f,0x04]
-
-v_sad_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0c,0x04]
-
-v_sad_u8 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_sad_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_sad_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_sad_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_sad_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_sad_u8 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_sad_u8 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_sad_u8 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_sad_u8 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_sad_u8 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_sad_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_sad_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_sad_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xff,0x0c,0x04]
-
-v_sad_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x01,0x0d,0x04]
-
-v_sad_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x83,0x0d,0x04]
-
-v_sad_u8 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_sad_u8 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xef,0x0d,0x04]
-
-v_sad_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfe,0x07]
-
-v_sad_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x00]
-
-v_sad_u8 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x96,0x01]
-
-v_sad_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x9a,0x01]
-
-v_sad_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x9e,0x01]
-
-v_sad_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xaa,0x01]
-
-v_sad_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xae,0x01]
-
-v_sad_u8 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xb2,0x01]
-
-v_sad_u8 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xb6,0x01]
-
-v_sad_u8 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xba,0x01]
-
-v_sad_u8 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xbe,0x01]
-
-v_sad_u8 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xee,0x01]
-
-v_sad_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xf2,0x01]
-
-v_sad_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfa,0x01]
-
-v_sad_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfe,0x01]
-
-v_sad_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x02,0x02]
-
-v_sad_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x06,0x03]
-
-v_sad_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xc2,0x03]
-
-v_sad_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_u8 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xd9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xda,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0xff,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x65,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x66,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x67,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x80,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xff,0x0f,0x04]
-
-v_sad_hi_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xff,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x01,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x83,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xef,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfe,0x07]
-
-v_sad_hi_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0e,0x00]
-
-v_sad_hi_u8 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x96,0x01]
-
-v_sad_hi_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x9a,0x01]
-
-v_sad_hi_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x9e,0x01]
-
-v_sad_hi_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xaa,0x01]
-
-v_sad_hi_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xae,0x01]
-
-v_sad_hi_u8 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xb2,0x01]
-
-v_sad_hi_u8 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xb6,0x01]
-
-v_sad_hi_u8 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xba,0x01]
-
-v_sad_hi_u8 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xbe,0x01]
-
-v_sad_hi_u8 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xee,0x01]
-
-v_sad_hi_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xf2,0x01]
-
-v_sad_hi_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfa,0x01]
-
-v_sad_hi_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfe,0x01]
-
-v_sad_hi_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x02,0x02]
-
-v_sad_hi_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x06,0x03]
-
-v_sad_hi_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xc2,0x03]
-
-v_sad_hi_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_hi_u8 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xda,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0xff,0x05,0x0e,0x04]
-
-v_sad_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x04,0x0e,0x04]
-
-v_sad_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x65,0x04,0x0e,0x04]
-
-v_sad_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x66,0x04,0x0e,0x04]
-
-v_sad_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x67,0x04,0x0e,0x04]
-
-v_sad_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_sad_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_sad_u16 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_sad_u16 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_sad_u16 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_sad_u16 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_sad_u16 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_sad_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_sad_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_sad_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_sad_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x80,0x04,0x0e,0x04]
-
-v_sad_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_sad_u16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_sad_u16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_sad_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xff,0x0f,0x04]
-
-v_sad_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0c,0x04]
-
-v_sad_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_sad_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_sad_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_sad_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_sad_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_sad_u16 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_sad_u16 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_sad_u16 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_sad_u16 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_sad_u16 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_sad_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_sad_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_sad_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xff,0x0c,0x04]
-
-v_sad_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x01,0x0d,0x04]
-
-v_sad_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x83,0x0d,0x04]
-
-v_sad_u16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_sad_u16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xef,0x0d,0x04]
-
-v_sad_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfe,0x07]
-
-v_sad_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x00]
-
-v_sad_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x96,0x01]
-
-v_sad_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x9a,0x01]
-
-v_sad_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x9e,0x01]
-
-v_sad_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xaa,0x01]
-
-v_sad_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xae,0x01]
-
-v_sad_u16 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xb2,0x01]
-
-v_sad_u16 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xb6,0x01]
-
-v_sad_u16 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xba,0x01]
-
-v_sad_u16 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xbe,0x01]
-
-v_sad_u16 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xee,0x01]
-
-v_sad_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xf2,0x01]
-
-v_sad_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfa,0x01]
-
-v_sad_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfe,0x01]
-
-v_sad_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x02,0x02]
-
-v_sad_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x06,0x03]
-
-v_sad_u16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xc2,0x03]
-
-v_sad_u16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_u16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xdb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0xff,0x05,0x0e,0x04]
-
-v_sad_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x04,0x0e,0x04]
-
-v_sad_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x65,0x04,0x0e,0x04]
-
-v_sad_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x66,0x04,0x0e,0x04]
-
-v_sad_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x67,0x04,0x0e,0x04]
-
-v_sad_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_sad_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_sad_u32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_sad_u32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_sad_u32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_sad_u32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_sad_u32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_sad_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_sad_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_sad_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_sad_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x80,0x04,0x0e,0x04]
-
-v_sad_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_sad_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_sad_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_sad_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xff,0x0f,0x04]
-
-v_sad_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0c,0x04]
-
-v_sad_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_sad_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_sad_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_sad_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_sad_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_sad_u32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_sad_u32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_sad_u32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_sad_u32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_sad_u32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_sad_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_sad_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_sad_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xff,0x0c,0x04]
-
-v_sad_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x01,0x0d,0x04]
-
-v_sad_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x83,0x0d,0x04]
-
-v_sad_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_sad_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xef,0x0d,0x04]
-
-v_sad_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfe,0x07]
-
-v_sad_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x00]
-
-v_sad_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x96,0x01]
-
-v_sad_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x9a,0x01]
-
-v_sad_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x9e,0x01]
-
-v_sad_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xaa,0x01]
-
-v_sad_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xae,0x01]
-
-v_sad_u32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xb2,0x01]
-
-v_sad_u32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xb6,0x01]
-
-v_sad_u32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xba,0x01]
-
-v_sad_u32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xbe,0x01]
-
-v_sad_u32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xee,0x01]
-
-v_sad_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xf2,0x01]
-
-v_sad_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfa,0x01]
-
-v_sad_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfe,0x01]
-
-v_sad_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x02,0x02]
-
-v_sad_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x06,0x03]
-
-v_sad_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xc2,0x03]
-
-v_sad_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_u32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xdc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cvt_pk_u8_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cvt_pk_u8_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x96,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xae,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xb2,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xb6,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xba,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xbe,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xee,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x02,0x02]
-
-v_cvt_pk_u8_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x06,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xde,0x03]
-
-v_cvt_pk_u8_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cvt_pk_u8_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xdd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0xff,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x65,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x67,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xff,0x0f,0x04]
-
-v_div_fixup_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xff,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfe,0x07]
-
-v_div_fixup_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x00]
-
-v_div_fixup_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x96,0x01]
-
-v_div_fixup_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_fixup_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x9e,0x01]
-
-v_div_fixup_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xae,0x01]
-
-v_div_fixup_f32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xb2,0x01]
-
-v_div_fixup_f32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xb6,0x01]
-
-v_div_fixup_f32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xba,0x01]
-
-v_div_fixup_f32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xbe,0x01]
-
-v_div_fixup_f32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xee,0x01]
-
-v_div_fixup_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xf2,0x01]
-
-v_div_fixup_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfe,0x01]
-
-v_div_fixup_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_div_fixup_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x14]
-
-v_div_fixup_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[2:3], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x02,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[4:5], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x04,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[100:101], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x64,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], tba, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], tma, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x7a,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], exec, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfd,0x0f,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[4:5], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x09,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[6:7], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x0d,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[100:101], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xc9,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], tba, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], tma, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xf5,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], exec, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xfa,0x07]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[6:7]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x1a,0x00]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[8:9]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x22,0x00]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[100:101]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x92,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], flat_scratch
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], tba
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xb2,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], tma
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xba,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xea,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], exec
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -1
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// CHECK: [0x05,0x01,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// CHECK: [0x05,0x02,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// CHECK: [0x05,0x04,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// CHECK: [0x05,0x07,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// CHECK: [0x05,0x80,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x14]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_div_scale_f32 v5, vcc, v1, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f32 v255, vcc, v1, v2, v3
-// CHECK: [0xff,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, v255, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0xff,0x05,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, s1, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, s101, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x65,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x67,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, vcc_lo, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, vcc_hi, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, tba_lo, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, tba_hi, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, tma_lo, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, tma_hi, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, ttmp11, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, m0, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, exec_lo, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, exec_hi, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, 0, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, -1, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, 0.5, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, -4.0, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, v1, v255, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xff,0x0f,0x04]
-
-v_div_scale_f32 v5, vcc, v1, s2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, s101, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, vcc_lo, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, vcc_hi, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, tba_lo, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, tba_hi, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, tma_lo, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, tma_hi, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, ttmp11, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, m0, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, exec_lo, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, exec_hi, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xff,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, 0, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, -1, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, 0.5, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, -4.0, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, v2, v255
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfe,0x07]
-
-v_div_scale_f32 v5, vcc, v1, v2, s3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x00]
-
-v_div_scale_f32 v5, vcc, v1, v2, s101
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x96,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x9e,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, vcc_lo
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, vcc_hi
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xae,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, tba_lo
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xb2,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, tba_hi
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xb6,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, tma_lo
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xba,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, tma_hi
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xbe,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, ttmp11
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xee,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, m0
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xf2,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, exec_lo
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, exec_hi
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfe,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, 0
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_scale_f32 v5, vcc, v1, v2, -1
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_scale_f32 v5, vcc, v1, v2, 0.5
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_scale_f32 v5, vcc, v1, v2, -4.0
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f64 v[254:255], vcc, v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x6a,0xe1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, s[2:3], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x02,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, s[4:5], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x04,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, s[100:101], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x64,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, flat_scratch, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, tba, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, tma, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, ttmp[10:11], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x7a,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, exec, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfd,0x0f,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], s[4:5], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x09,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], s[6:7], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x0d,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], s[100:101], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xc9,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], flat_scratch, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], tba, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], tma, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], ttmp[10:11], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xf5,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], exec, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xfa,0x07]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[6:7]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x1a,0x00]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[8:9]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x22,0x00]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[100:101]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x92,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], flat_scratch
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], tba
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xb2,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], tma
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xba,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], ttmp[10:11]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xea,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], exec
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -1
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0xff,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xff,0x0f,0x04]
-
-v_div_fmas_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xfe,0x07]
-
-v_div_fmas_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_fmas_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_fmas_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_fmas_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fmas_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fmas_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fmas_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fmas_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_div_fmas_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x14]
-
-v_div_fmas_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xfd,0x0f,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xfa,0x07]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -1
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fmas_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fmas_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fmas_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// CHECK: [0x05,0x01,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// CHECK: [0x05,0x02,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// CHECK: [0x05,0x04,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// CHECK: [0x05,0x07,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// CHECK: [0x05,0x80,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x14]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_msad_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_msad_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_msad_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0xff,0x05,0x0e,0x04]
-
-v_msad_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x04,0x0e,0x04]
-
-v_msad_u8 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x65,0x04,0x0e,0x04]
-
-v_msad_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x66,0x04,0x0e,0x04]
-
-v_msad_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x67,0x04,0x0e,0x04]
-
-v_msad_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_msad_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_msad_u8 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_msad_u8 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_msad_u8 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_msad_u8 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_msad_u8 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_msad_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_msad_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_msad_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_msad_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x80,0x04,0x0e,0x04]
-
-v_msad_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_msad_u8 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_msad_u8 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_msad_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xff,0x0f,0x04]
-
-v_msad_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0c,0x04]
-
-v_msad_u8 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_msad_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_msad_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_msad_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_msad_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_msad_u8 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_msad_u8 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_msad_u8 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_msad_u8 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_msad_u8 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_msad_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_msad_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_msad_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xff,0x0c,0x04]
-
-v_msad_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x01,0x0d,0x04]
-
-v_msad_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x83,0x0d,0x04]
-
-v_msad_u8 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_msad_u8 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xef,0x0d,0x04]
-
-v_msad_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfe,0x07]
-
-v_msad_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x00]
-
-v_msad_u8 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x96,0x01]
-
-v_msad_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x9a,0x01]
-
-v_msad_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x9e,0x01]
-
-v_msad_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xaa,0x01]
-
-v_msad_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xae,0x01]
-
-v_msad_u8 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xb2,0x01]
-
-v_msad_u8 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xb6,0x01]
-
-v_msad_u8 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xba,0x01]
-
-v_msad_u8 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xbe,0x01]
-
-v_msad_u8 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xee,0x01]
-
-v_msad_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xf2,0x01]
-
-v_msad_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfa,0x01]
-
-v_msad_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfe,0x01]
-
-v_msad_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x02,0x02]
-
-v_msad_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x06,0x03]
-
-v_msad_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xc2,0x03]
-
-v_msad_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xde,0x03]
-
-v_msad_u8 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xe4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
-// CHECK: [0xfe,0x00,0xe5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x02,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x04,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[100:101], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x64,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x66,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], tba, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], tma, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x7a,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x80,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xff,0x0f,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], s101, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], tba_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], tba_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], tma_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], tma_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xff,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x01,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x83,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xef,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xfa,0x07]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x1a,0x00]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x22,0x00]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[100:101]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x92,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x9a,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xaa,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, tba
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xb2,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, tma
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xba,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xea,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xfa,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x02,0x02]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x06,0x03]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0.5
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xc2,0x03]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -4.0
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xde,0x03]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
-// CHECK: [0x05,0x80,0xe5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
-// CHECK: [0xfe,0x00,0xe6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x02,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x04,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[100:101], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x64,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], tba, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], tma, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x7a,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], s101, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], tba_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], tba_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], tma_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], tma_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xfa,0x07]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x1a,0x00]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x22,0x00]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[100:101]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x92,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, tba
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, tma
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xba,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xea,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x02,0x02]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x06,0x03]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0.5
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -4.0
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xde,0x03]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
-// CHECK: [0x05,0x80,0xe6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[2:3], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x02,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[4:5], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x04,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[100:101], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x64,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], flat_scratch, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], vcc, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], tba, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], tma, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], ttmp[10:11], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x7a,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], exec, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], 0, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], -1, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], 0.5, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], -4.0, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], s2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], s101, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], vcc_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], vcc_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], tba_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], tba_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], tma_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], tma_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], ttmp11, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], m0, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], exec_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], exec_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], 0, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], -1, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], 0.5, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], -4.0, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6] clamp
-// CHECK: [0xfc,0x80,0xe7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[254:255], s[12:13], v1, v2, v[3:4]
-// CHECK: [0xfe,0x0c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[14:15], v1, v2, v[3:4]
-// CHECK: [0x05,0x0e,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[100:101], v1, v2, v[3:4]
-// CHECK: [0x05,0x64,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], flat_scratch, v1, v2, v[3:4]
-// CHECK: [0x05,0x66,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], vcc, v1, v2, v[3:4]
-// CHECK: [0x05,0x6a,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], tba, v1, v2, v[3:4]
-// CHECK: [0x05,0x6c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], tma, v1, v2, v[3:4]
-// CHECK: [0x05,0x6e,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], ttmp[10:11], v1, v2, v[3:4]
-// CHECK: [0x05,0x7a,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v255, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], s1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], s101, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], tba_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], tba_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], tma_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], tma_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], ttmp11, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], m0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], 0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], -1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v255, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, s2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, s101, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, tba_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, tba_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, tma_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, tma_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, ttmp11, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, m0, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, 0, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, -1, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, 0.5, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, -4.0, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[254:255]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xfa,0x07]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x1a,0x00]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x22,0x00]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x92,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xba,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xea,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, exec
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -1
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0.5
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -4.0
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4] clamp
-// CHECK: [0x05,0x8c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[254:255], s[12:13], v1, v2, v[3:4]
-// CHECK: [0xfe,0x0c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[14:15], v1, v2, v[3:4]
-// CHECK: [0x05,0x0e,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[100:101], v1, v2, v[3:4]
-// CHECK: [0x05,0x64,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], flat_scratch, v1, v2, v[3:4]
-// CHECK: [0x05,0x66,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], vcc, v1, v2, v[3:4]
-// CHECK: [0x05,0x6a,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], tba, v1, v2, v[3:4]
-// CHECK: [0x05,0x6c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], tma, v1, v2, v[3:4]
-// CHECK: [0x05,0x6e,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], ttmp[10:11], v1, v2, v[3:4]
-// CHECK: [0x05,0x7a,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v255, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], s1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], s101, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], tba_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], tba_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], tma_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], tma_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], ttmp11, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], m0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], 0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], -1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v255, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, s2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, s101, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, tba_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, tba_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, tma_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, tma_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, ttmp11, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, m0, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, 0, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, -1, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, 0.5, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, -4.0, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[254:255]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xfa,0x07]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x1a,0x00]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x22,0x00]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x92,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, tba
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, tma
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xba,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, ttmp[10:11]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xea,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, exec
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -1
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0.5
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -4.0
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4] clamp
-// CHECK: [0x05,0x8c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_f16 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mad_f16 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_mad_f16 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mad_f16 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_mad_f16 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_mad_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_f16 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mad_f16 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mad_f16 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mad_f16 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mad_f16 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mad_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_f16 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mad_f16 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xb6,0x01]
-
-v_mad_f16 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xba,0x01]
-
-v_mad_f16 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xbe,0x01]
-
-v_mad_f16 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xee,0x01]
-
-v_mad_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x24]
-
-v_mad_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
-
-v_mad_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x84]
-
-v_mad_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_mad_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_u16 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mad_u16 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_mad_u16 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mad_u16 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_mad_u16 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_mad_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_u16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_u16 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mad_u16 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mad_u16 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mad_u16 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mad_u16 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mad_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_u16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_u16 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mad_u16 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xb6,0x01]
-
-v_mad_u16 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xba,0x01]
-
-v_mad_u16 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xbe,0x01]
-
-v_mad_u16 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xee,0x01]
-
-v_mad_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_u16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xeb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xec,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_i16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_i16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_i16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_i16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_i16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_i16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_i16 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_mad_i16 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_mad_i16 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_mad_i16 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_mad_i16 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_mad_i16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_i16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_i16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_i16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_i16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_i16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_i16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_i16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_i16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_i16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_i16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_i16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_i16 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_mad_i16 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_mad_i16 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_mad_i16 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_mad_i16 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_mad_i16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_i16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_i16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_i16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_i16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_i16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_i16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_i16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_i16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_i16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_i16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_i16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_i16 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xb2,0x01]
-
-v_mad_i16 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xb6,0x01]
-
-v_mad_i16 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xba,0x01]
-
-v_mad_i16 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xbe,0x01]
-
-v_mad_i16 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xee,0x01]
-
-v_mad_i16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_i16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_i16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_i16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_i16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_i16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xec,0xd1,0x01,0x05,0x0e,0x04]
-
-v_perm_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0e,0x04]
-
-v_perm_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xed,0xd1,0x01,0x05,0x0e,0x04]
-
-v_perm_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0xff,0x05,0x0e,0x04]
-
-v_perm_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x04,0x0e,0x04]
-
-v_perm_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x65,0x04,0x0e,0x04]
-
-v_perm_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x66,0x04,0x0e,0x04]
-
-v_perm_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x67,0x04,0x0e,0x04]
-
-v_perm_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_perm_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_perm_b32 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_perm_b32 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_perm_b32 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_perm_b32 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_perm_b32 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_perm_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_perm_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_perm_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_perm_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x80,0x04,0x0e,0x04]
-
-v_perm_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_perm_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_perm_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_perm_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xff,0x0f,0x04]
-
-v_perm_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0c,0x04]
-
-v_perm_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_perm_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_perm_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_perm_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_perm_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_perm_b32 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_perm_b32 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_perm_b32 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_perm_b32 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_perm_b32 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_perm_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_perm_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_perm_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xff,0x0c,0x04]
-
-v_perm_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x01,0x0d,0x04]
-
-v_perm_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x83,0x0d,0x04]
-
-v_perm_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_perm_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xef,0x0d,0x04]
-
-v_perm_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfe,0x07]
-
-v_perm_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0e,0x00]
-
-v_perm_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x96,0x01]
-
-v_perm_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x9a,0x01]
-
-v_perm_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x9e,0x01]
-
-v_perm_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xaa,0x01]
-
-v_perm_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xae,0x01]
-
-v_perm_b32 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xb2,0x01]
-
-v_perm_b32 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xb6,0x01]
-
-v_perm_b32 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xba,0x01]
-
-v_perm_b32 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xbe,0x01]
-
-v_perm_b32 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xee,0x01]
-
-v_perm_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xf2,0x01]
-
-v_perm_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfa,0x01]
-
-v_perm_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfe,0x01]
-
-v_perm_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x02,0x02]
-
-v_perm_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x06,0x03]
-
-v_perm_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xc2,0x03]
-
-v_perm_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xde,0x03]
-
-v_fma_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0xff,0x05,0x0e,0x04]
-
-v_fma_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x04,0x0e,0x04]
-
-v_fma_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x65,0x04,0x0e,0x04]
-
-v_fma_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x66,0x04,0x0e,0x04]
-
-v_fma_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x67,0x04,0x0e,0x04]
-
-v_fma_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_fma_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_fma_f16 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_fma_f16 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_fma_f16 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_fma_f16 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_fma_f16 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_fma_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_fma_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_fma_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_fma_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x80,0x04,0x0e,0x04]
-
-v_fma_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_fma_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_fma_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_fma_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xff,0x0f,0x04]
-
-v_fma_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0c,0x04]
-
-v_fma_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_fma_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_fma_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_fma_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_fma_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_fma_f16 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_fma_f16 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_fma_f16 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_fma_f16 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_fma_f16 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_fma_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_fma_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_fma_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xff,0x0c,0x04]
-
-v_fma_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x01,0x0d,0x04]
-
-v_fma_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x83,0x0d,0x04]
-
-v_fma_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_fma_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xef,0x0d,0x04]
-
-v_fma_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfe,0x07]
-
-v_fma_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x00]
-
-v_fma_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x96,0x01]
-
-v_fma_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x9a,0x01]
-
-v_fma_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x9e,0x01]
-
-v_fma_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xaa,0x01]
-
-v_fma_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xae,0x01]
-
-v_fma_f16 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xb2,0x01]
-
-v_fma_f16 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xb6,0x01]
-
-v_fma_f16 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xba,0x01]
-
-v_fma_f16 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xbe,0x01]
-
-v_fma_f16 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xee,0x01]
-
-v_fma_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xf2,0x01]
-
-v_fma_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfa,0x01]
-
-v_fma_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfe,0x01]
-
-v_fma_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x02,0x02]
-
-v_fma_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x06,0x03]
-
-v_fma_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xc2,0x03]
-
-v_fma_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xde,0x03]
-
-v_fma_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x24]
-
-v_fma_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x44]
-
-v_fma_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
-
-v_fma_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_fma_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0xff,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x65,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x67,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, tba_lo, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x6c,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, tba_hi, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x6d,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, tma_lo, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x6e,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, tma_hi, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x6f,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, ttmp11, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x7b,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xff,0x0f,0x04]
-
-v_div_fixup_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, tba_lo, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd9,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, tba_hi, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xdb,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, tma_lo, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xdd,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, tma_hi, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xdf,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, ttmp11, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf7,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xff,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfe,0x07]
-
-v_div_fixup_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x00]
-
-v_div_fixup_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x96,0x01]
-
-v_div_fixup_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_fixup_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x9e,0x01]
-
-v_div_fixup_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xae,0x01]
-
-v_div_fixup_f16 v5, v1, v2, tba_lo
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xb2,0x01]
-
-v_div_fixup_f16 v5, v1, v2, tba_hi
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xb6,0x01]
-
-v_div_fixup_f16 v5, v1, v2, tma_lo
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xba,0x01]
-
-v_div_fixup_f16 v5, v1, v2, tma_hi
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xbe,0x01]
-
-v_div_fixup_f16 v5, v1, v2, ttmp11
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xee,0x01]
-
-v_div_fixup_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xf2,0x01]
-
-v_div_fixup_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfe,0x01]
-
-v_div_fixup_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cvt_pkaccum_u8_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0xf0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0xff,0x05,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x65,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x66,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x67,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x6c,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x6d,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x6e,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x6f,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x7b,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x80,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xff,0x03,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcb,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd9,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xdb,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xdd,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xdf,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf7,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xff,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x01,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x83,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xef,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x02,0x20]
-
-v_cvt_pkaccum_u8_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0xf0,0xd1,0x01,0x05,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v255, v2, attr0.x
-// CHECK: [0xff,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr1.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr31.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x1f,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr32.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x20,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v255, attr0.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0xfe,0x03,0x00]
-
-v_interp_p1ll_f16 v5, -v2, attr0.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
-
-v_interp_p1ll_f16 v5, |v2|, attr0.x
-// CHECK: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.y
-// CHECK: [0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.z
-// CHECK: [0x05,0x00,0x74,0xd2,0x80,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.w
-// CHECK: [0x05,0x00,0x74,0xd2,0xc0,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x high
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x clamp
-// CHECK: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x mul:2
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x08]
-
-v_interp_p1ll_f16 v5, v2, attr0.x mul:4
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x10]
-
-v_interp_p1ll_f16 v5, v2, attr0.x div:2
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v255, v2, attr0.x, v3
-// CHECK: [0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr1.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x01,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr31.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x1f,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr32.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v255, attr0.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0xfe,0x0f,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v255
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0xfe,0x07]
-
-v_interp_p1lv_f16 v5, -v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, -v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
-
-v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
-// CHECK: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
-// CHECK: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.y, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x40,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.z, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x80,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.w, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0xc0,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
-// CHECK: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x0c]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:4
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x1c]
-
-v_interp_p2_f16 v5, v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v255, v2, attr0.x, v3
-// CHECK: [0xff,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr1.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr31.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr32.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x20,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v255, attr0.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0xfe,0x0f,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v255
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0xfe,0x07]
-
-v_interp_p2_f16 v5, -v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
-
-v_interp_p2_f16 v5, v2, attr0.x, -v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
-
-v_interp_p2_f16 v5, |v2|, attr0.x, v3
-// CHECK: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, |v3|
-// CHECK: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.y, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x40,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.z, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x80,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.w, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v3 high
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
-// CHECK: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_add_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0xfe,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x02,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x04,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], s[100:101], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x64,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x66,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x6a,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], tba, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x6c,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], tma, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x6e,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], ttmp[10:11], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x7a,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x7e,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x80,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0xc1,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0xf0,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0xf7,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x03,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x09,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x0d,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[100:101]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xc9,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xcd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd5,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], tba
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd9,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], tma
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xdd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], ttmp[10:11]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf5,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x01,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x83,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xe1,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xef,0x01,0x00]
-
-v_add_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x20]
-
-v_add_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x40]
-
-v_add_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x60]
-
-v_add_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x80,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x08]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x10]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x18]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0xfe,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x02,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x04,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], s[100:101], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x64,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x66,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], tba, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], tma, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], ttmp[10:11], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x7a,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x03,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x09,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x0d,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[100:101]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xc9,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], tba
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], tma
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], ttmp[10:11]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xf5,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x20]
-
-v_mul_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x40]
-
-v_mul_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x60]
-
-v_mul_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x80,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x08]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x10]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x18]
-
-v_min_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0xfe,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x02,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x04,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], s[100:101], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x64,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x66,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x6a,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], tba, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x6c,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], tma, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x6e,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], ttmp[10:11], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x7a,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x7e,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x80,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0xc1,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0xf0,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0xf7,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x03,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x09,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x0d,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[100:101]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xc9,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xcd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd5,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], tba
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd9,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], tma
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xdd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], ttmp[10:11]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf5,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x01,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x83,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xe1,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xef,0x01,0x00]
-
-v_min_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x20]
-
-v_min_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x40]
-
-v_min_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x60]
-
-v_min_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x80,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x08]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x10]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x18]
-
-v_max_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0xfe,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x02,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x04,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], s[100:101], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x64,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x66,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x6a,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], tba, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x6c,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], tma, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x6e,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], ttmp[10:11], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x7a,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x7e,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x80,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0xc1,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0xf0,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0xf7,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x03,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x09,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x0d,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[100:101]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xc9,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xcd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xd5,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], tba
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xd9,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], tma
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xdd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], ttmp[10:11]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xf5,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x01,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x83,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xe1,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xef,0x01,0x00]
-
-v_max_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x20]
-
-v_max_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x40]
-
-v_max_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x60]
-
-v_max_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x80,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x08]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x10]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x18]
-
-v_ldexp_f64 v[5:6], v[1:2], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[254:255], v[1:2], v2
-// CHECK: [0xfe,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[254:255], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0xfe,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[2:3], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x02,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[4:5], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x04,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[100:101], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x64,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], flat_scratch, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x66,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], vcc, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], tba, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x6c,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], tma, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x6e,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], ttmp[10:11], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x7a,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], exec, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], 0, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x80,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], -1, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], 0.5, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], -4.0, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v255
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x03,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], s2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], s101
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcb,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], flat_scratch_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcd,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], flat_scratch_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], vcc_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], vcc_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], tba_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd9,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], tba_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdb,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], tma_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdd,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], tma_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdf,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], ttmp11
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf7,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], m0
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], exec_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], exec_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x01,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x83,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xef,0x01,0x00]
-
-v_ldexp_f64 v[5:6], -v[1:2], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x20]
-
-v_ldexp_f64 v[5:6], |v[1:2]|, v2
-// CHECK: [0x05,0x01,0x84,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 clamp
-// CHECK: [0x05,0x80,0x84,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 mul:2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x08]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 mul:4
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x10]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 div:2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x18]
-
-v_mul_lo_u32 v5, v1, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u32 v255, v1, v2
-// CHECK: [0xff,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u32 v5, v255, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_lo_u32 v5, s1, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, s101, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x65,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x66,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, m0, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, 0, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, -1, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, v1, v255
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_lo_u32 v5, v1, s2
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, s101
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, m0
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, 0
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, -1
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32 v255, v1, v2
-// CHECK: [0xff,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32 v5, v255, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_hi_u32 v5, s1, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, s101, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x65,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x66,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, m0, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, 0, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, -1, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, v1, v255
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_hi_u32 v5, v1, s2
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, s101
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, m0
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, 0
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, -1
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32 v255, v1, v2
-// CHECK: [0xff,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32 v5, v255, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_hi_i32 v5, s1, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, s101, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x65,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x66,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, m0, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, 0, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, -1, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, v1, v255
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_hi_i32 v5, v1, s2
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, s101
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, m0
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, 0
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, -1
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xef,0x01,0x00]
-
-v_ldexp_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0xff,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x65,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x66,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x67,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x6b,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x6c,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x6d,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x6e,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x6f,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x7b,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x7c,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x7f,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x80,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x03,0x00]
-
-v_ldexp_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x00,0x00]
-
-v_ldexp_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcb,0x00,0x00]
-
-v_ldexp_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcd,0x00,0x00]
-
-v_ldexp_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd9,0x00,0x00]
-
-v_ldexp_f32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdb,0x00,0x00]
-
-v_ldexp_f32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdd,0x00,0x00]
-
-v_ldexp_f32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdf,0x00,0x00]
-
-v_ldexp_f32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf7,0x00,0x00]
-
-v_ldexp_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x00,0x00]
-
-v_ldexp_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x01,0x01,0x00]
-
-v_ldexp_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x83,0x01,0x00]
-
-v_ldexp_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xef,0x01,0x00]
-
-v_ldexp_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x20]
-
-v_ldexp_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x88,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x88,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x08]
-
-v_ldexp_f32 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x10]
-
-v_ldexp_f32 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x18]
-
-v_readlane_b32 s5, v1, s2
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 s101, v1, s2
-// CHECK: [0x65,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 flat_scratch_lo, v1, s2
-// CHECK: [0x66,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 flat_scratch_hi, v1, s2
-// CHECK: [0x67,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 tba_lo, v1, s2
-// CHECK: [0x6c,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 tba_hi, v1, s2
-// CHECK: [0x6d,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 tma_lo, v1, s2
-// CHECK: [0x6e,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 tma_hi, v1, s2
-// CHECK: [0x6f,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 ttmp11, v1, s2
-// CHECK: [0x7b,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 s5, v255, s2
-// CHECK: [0x05,0x00,0x89,0xd2,0xff,0x05,0x00,0x00]
-
-v_readlane_b32 s5, v1, s101
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcb,0x00,0x00]
-
-v_readlane_b32 s5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcd,0x00,0x00]
-
-v_readlane_b32 s5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcf,0x00,0x00]
-
-v_readlane_b32 s5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd5,0x00,0x00]
-
-v_readlane_b32 s5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd7,0x00,0x00]
-
-v_readlane_b32 s5, v1, tba_lo
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd9,0x00,0x00]
-
-v_readlane_b32 s5, v1, tba_hi
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xdb,0x00,0x00]
-
-v_readlane_b32 s5, v1, tma_lo
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xdd,0x00,0x00]
-
-v_readlane_b32 s5, v1, tma_hi
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xdf,0x00,0x00]
-
-v_readlane_b32 s5, v1, ttmp11
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xf7,0x00,0x00]
-
-v_readlane_b32 s5, v1, m0
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xf9,0x00,0x00]
-
-v_readlane_b32 s5, v1, 0
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0x01,0x01,0x00]
-
-v_writelane_b32 v5, 0, s2
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
-
-v_writelane_b32 v255, 0, s2
-// CHECK: [0xff,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
-
-v_writelane_b32 v5, -1, s2
-// CHECK: [0x05,0x00,0x8a,0xd2,0xc1,0x04,0x00,0x00]
-
-v_writelane_b32 v5, 0.5, s2
-// CHECK: [0x05,0x00,0x8a,0xd2,0xf0,0x04,0x00,0x00]
-
-v_writelane_b32 v5, -4.0, s2
-// CHECK: [0x05,0x00,0x8a,0xd2,0xf7,0x04,0x00,0x00]
-
-v_writelane_b32 v5, 0, s101
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xca,0x00,0x00]
-
-v_writelane_b32 v5, 0, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xcc,0x00,0x00]
-
-v_writelane_b32 v5, 0, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xce,0x00,0x00]
-
-v_writelane_b32 v5, 0, vcc_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd4,0x00,0x00]
-
-v_writelane_b32 v5, 0, vcc_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd6,0x00,0x00]
-
-v_writelane_b32 v5, 0, tba_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd8,0x00,0x00]
-
-v_writelane_b32 v5, 0, tba_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xda,0x00,0x00]
-
-v_writelane_b32 v5, 0, tma_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xdc,0x00,0x00]
-
-v_writelane_b32 v5, 0, tma_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xde,0x00,0x00]
-
-v_writelane_b32 v5, 0, ttmp11
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xf6,0x00,0x00]
-
-v_writelane_b32 v5, 0, m0
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xf8,0x00,0x00]
-
-v_writelane_b32 v5, 0, 0
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x00,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
-
-v_bcnt_u32_b32 v255, v1, v2
-// CHECK: [0xff,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
-
-v_bcnt_u32_b32 v5, v255, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0xff,0x05,0x02,0x00]
-
-v_bcnt_u32_b32 v5, s1, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, s101, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x65,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x66,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x67,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x6a,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x6b,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x6c,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x6d,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x6e,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x6f,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x7b,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, m0, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x7c,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x7e,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x7f,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, 0, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x80,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, -1, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0xc1,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0xf0,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0xf7,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, v1, v255
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x03,0x00]
-
-v_bcnt_u32_b32 v5, v1, s2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, s101
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcb,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcd,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcf,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd5,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd7,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd9,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xdb,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xdd,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xdf,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf7,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, m0
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf9,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xfd,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, 0
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x01,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, -1
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x83,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xe1,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xef,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v255, v1, v2
-// CHECK: [0xff,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v255, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0xff,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, s1, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, s101, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x65,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x66,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x67,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, m0, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, 0, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x80,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, -1, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, v255
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x03,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, s2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, s101
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, m0
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, 0
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x01,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, -1
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x83,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xef,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v255, v1, v2
-// CHECK: [0xff,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v255, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0xff,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, s1, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, s101, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x65,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x66,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x67,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x6c,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x6d,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x6e,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x6f,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x7b,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, m0, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, 0, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x80,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, -1, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, v255
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x03,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, s2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, s101
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd9,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xdb,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xdd,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xdf,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf7,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, m0
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, 0
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x01,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, -1
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x83,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xef,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b64 v[254:255], v1, v[2:3]
-// CHECK: [0xfe,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], v255, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], s1, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], s101, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x65,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], flat_scratch_lo, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x66,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], flat_scratch_hi, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x67,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], vcc_lo, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], vcc_hi, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], tba_lo, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x6c,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], tba_hi, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x6d,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], tma_lo, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x6e,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], tma_hi, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x6f,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], ttmp11, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x7b,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], m0, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], exec_lo, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], exec_hi, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], v1, v[254:255]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x03,0x00]
-
-v_lshlrev_b64 v[5:6], v1, s[4:5]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x09,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, s[6:7]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x0d,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, s[100:101]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xc9,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, flat_scratch
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xcd,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, vcc
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, tba
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xd9,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, tma
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xdd,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, ttmp[10:11]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xf5,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, exec
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, 0
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, -1
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, 0.5
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, -4.0
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xef,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b64 v[254:255], v1, v[2:3]
-// CHECK: [0xfe,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], v255, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], s1, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], s101, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x65,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], flat_scratch_lo, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x66,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], flat_scratch_hi, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x67,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], vcc_lo, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], vcc_hi, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], tba_lo, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x6c,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], tba_hi, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x6d,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], tma_lo, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x6e,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], tma_hi, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x6f,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], ttmp11, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x7b,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], m0, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], exec_lo, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], exec_hi, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], v1, v[254:255]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x03,0x00]
-
-v_lshrrev_b64 v[5:6], v1, s[4:5]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x09,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, s[6:7]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x0d,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, s[100:101]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xc9,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, flat_scratch
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xcd,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, vcc
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, tba
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd9,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, tma
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xdd,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, ttmp[10:11]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf5,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, exec
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, 0
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, -1
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, 0.5
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, -4.0
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xef,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i64 v[254:255], v1, v[2:3]
-// CHECK: [0xfe,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], v255, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], s1, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], s101, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x65,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], flat_scratch_lo, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x66,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], flat_scratch_hi, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x67,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], vcc_lo, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], vcc_hi, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], tba_lo, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x6c,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], tba_hi, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x6d,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], tma_lo, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x6e,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], tma_hi, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x6f,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], ttmp11, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x7b,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], m0, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], exec_lo, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], exec_hi, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], v1, v[254:255]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x03,0x00]
-
-v_ashrrev_i64 v[5:6], v1, s[4:5]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x09,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, s[6:7]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x0d,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, s[100:101]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xc9,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, flat_scratch
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xcd,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, vcc
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, tba
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xd9,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, tma
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xdd,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, ttmp[10:11]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xf5,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, exec
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, 0
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, -1
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, 0.5
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, -4.0
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xef,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[254:255], v[1:2], v2
-// CHECK: [0xfe,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[254:255], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0xfe,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[2:3], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x02,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[4:5], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x04,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[100:101], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x64,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], flat_scratch, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x66,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], vcc, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x6a,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], tba, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x6c,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], tma, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x6e,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], ttmp[10:11], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x7a,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], exec, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x7e,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], 0, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x80,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], -1, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0xc1,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], 0.5, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0xf0,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], -4.0, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0xf7,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v255
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x03,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], s2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], s101
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcb,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcd,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcf,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], vcc_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd5,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], vcc_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd7,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], tba_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd9,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], tba_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdb,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], tma_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdd,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], tma_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdf,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], ttmp11
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf7,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], m0
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], exec_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfd,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], exec_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x01,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x83,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xe1,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xef,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], -v[1:2], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x20]
-
-v_trig_preop_f64 v[5:6], |v[1:2]|, v2
-// CHECK: [0x05,0x01,0x92,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 clamp
-// CHECK: [0x05,0x80,0x92,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 mul:2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x08]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 mul:4
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x10]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 div:2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x18]
-
-v_bfm_b32 v5, v1, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
-
-v_bfm_b32 v255, v1, v2
-// CHECK: [0xff,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
-
-v_bfm_b32 v5, v255, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0xff,0x05,0x02,0x00]
-
-v_bfm_b32 v5, s1, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x04,0x02,0x00]
-
-v_bfm_b32 v5, s101, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x65,0x04,0x02,0x00]
-
-v_bfm_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x66,0x04,0x02,0x00]
-
-v_bfm_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x67,0x04,0x02,0x00]
-
-v_bfm_b32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x6a,0x04,0x02,0x00]
-
-v_bfm_b32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x6b,0x04,0x02,0x00]
-
-v_bfm_b32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x6c,0x04,0x02,0x00]
-
-v_bfm_b32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x6d,0x04,0x02,0x00]
-
-v_bfm_b32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x6e,0x04,0x02,0x00]
-
-v_bfm_b32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x6f,0x04,0x02,0x00]
-
-v_bfm_b32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x7b,0x04,0x02,0x00]
-
-v_bfm_b32 v5, m0, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x7c,0x04,0x02,0x00]
-
-v_bfm_b32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x7e,0x04,0x02,0x00]
-
-v_bfm_b32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x7f,0x04,0x02,0x00]
-
-v_bfm_b32 v5, 0, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x80,0x04,0x02,0x00]
-
-v_bfm_b32 v5, -1, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0xc1,0x04,0x02,0x00]
-
-v_bfm_b32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0xf0,0x04,0x02,0x00]
-
-v_bfm_b32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0xf7,0x04,0x02,0x00]
-
-v_bfm_b32 v5, v1, v255
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x03,0x00]
-
-v_bfm_b32 v5, v1, s2
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x00,0x00]
-
-v_bfm_b32 v5, v1, s101
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcb,0x00,0x00]
-
-v_bfm_b32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcd,0x00,0x00]
-
-v_bfm_b32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcf,0x00,0x00]
-
-v_bfm_b32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd5,0x00,0x00]
-
-v_bfm_b32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd7,0x00,0x00]
-
-v_bfm_b32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd9,0x00,0x00]
-
-v_bfm_b32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xdb,0x00,0x00]
-
-v_bfm_b32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xdd,0x00,0x00]
-
-v_bfm_b32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xdf,0x00,0x00]
-
-v_bfm_b32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf7,0x00,0x00]
-
-v_bfm_b32 v5, v1, m0
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf9,0x00,0x00]
-
-v_bfm_b32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xfd,0x00,0x00]
-
-v_bfm_b32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x00,0x00]
-
-v_bfm_b32 v5, v1, 0
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x01,0x01,0x00]
-
-v_bfm_b32 v5, v1, -1
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x83,0x01,0x00]
-
-v_bfm_b32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xe1,0x01,0x00]
-
-v_bfm_b32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_i16_f32 v5, v1, -v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_i16_f32 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_i16_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_u16_f32 v5, v1, -v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_u16_f32 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_u16_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pkrtz_f16_f32 v5, v1, -v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pkrtz_f16_f32 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pkrtz_f16_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v255, v1, v2
-// CHECK: [0xff,0x00,0x97,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v255, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, s1, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, s101, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, m0, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, 0, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, -1, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, v255
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, s2
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, s101
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, m0
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, 0
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, -1
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32 v255, v1, v2
-// CHECK: [0xff,0x00,0x98,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, v255, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, s1, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, s101, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, tba_lo, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x6c,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, tba_hi, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x6d,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, tma_lo, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x6e,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, tma_hi, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x6f,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, ttmp11, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x7b,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, m0, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, 0, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, -1, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, v255
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, s2
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, s101
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, tba_lo
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd9,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, tba_hi
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xdb,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, tma_lo
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xdd,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, tma_hi
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xdf,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, ttmp11
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf7,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, m0
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, 0
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, -1
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x20,0x7c]
-
-v_cmp_class_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x20,0x7c]
-
-v_cmp_class_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x20,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_class_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x20,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_class_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x21,0x7c]
-
-v_cmp_class_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_class_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x22,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_class_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x22,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_class_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x23,0x7c]
-
-v_cmpx_class_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_class_f64 vcc, v[1:2], v2
-// CHECK: [0x01,0x05,0x24,0x7c]
-
-v_cmp_class_f64 vcc, v[254:255], v2
-// CHECK: [0xfe,0x05,0x24,0x7c]
-
-v_cmp_class_f64 vcc, s[2:3], v2
-// CHECK: [0x02,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, s[4:5], v2
-// CHECK: [0x04,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, s[100:101], v2
-// CHECK: [0x64,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, flat_scratch, v2
-// CHECK: [0x66,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, vcc, v2
-// CHECK: [0x6a,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, tba, v2
-// CHECK: [0x6c,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, tma, v2
-// CHECK: [0x6e,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, ttmp[10:11], v2
-// CHECK: [0x7a,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, exec, v2
-// CHECK: [0x7e,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, 0, v2
-// CHECK: [0x80,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x24,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_class_f64 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x24,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_class_f64 vcc, v[1:2], v255
-// CHECK: [0x01,0xff,0x25,0x7c]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[12:13], v[1:2], v2
-// CHECK: [0x0c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[100:101], v[1:2], v2
-// CHECK: [0x64,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 flat_scratch, v[1:2], v2
-// CHECK: [0x66,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 vcc, v[1:2], v2
-// CHECK: [0x6a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 tba, v[1:2], v2
-// CHECK: [0x6c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 tma, v[1:2], v2
-// CHECK: [0x6e,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 ttmp[10:11], v[1:2], v2
-// CHECK: [0x7a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[254:255], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], s[2:3], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], s[4:5], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], s[100:101], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], flat_scratch, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], vcc, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], tba, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], tma, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], ttmp[10:11], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], exec, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], v255
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], s2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], s101
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], tba_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], tba_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], tma_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], tma_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], ttmp11
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], m0
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], exec_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], exec_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], -v[1:2], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_class_f64 vcc, v[1:2], v2
-// CHECK: [0x01,0x05,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, v[254:255], v2
-// CHECK: [0xfe,0x05,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, s[2:3], v2
-// CHECK: [0x02,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, s[4:5], v2
-// CHECK: [0x04,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, s[100:101], v2
-// CHECK: [0x64,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, flat_scratch, v2
-// CHECK: [0x66,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, vcc, v2
-// CHECK: [0x6a,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, tba, v2
-// CHECK: [0x6c,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, tma, v2
-// CHECK: [0x6e,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, ttmp[10:11], v2
-// CHECK: [0x7a,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, exec, v2
-// CHECK: [0x7e,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, 0, v2
-// CHECK: [0x80,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x26,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_class_f64 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x26,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_class_f64 vcc, v[1:2], v255
-// CHECK: [0x01,0xff,0x27,0x7c]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[12:13], v[1:2], v2
-// CHECK: [0x0c,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[100:101], v[1:2], v2
-// CHECK: [0x64,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 flat_scratch, v[1:2], v2
-// CHECK: [0x66,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 vcc, v[1:2], v2
-// CHECK: [0x6a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 tba, v[1:2], v2
-// CHECK: [0x6c,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 tma, v[1:2], v2
-// CHECK: [0x6e,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 ttmp[10:11], v[1:2], v2
-// CHECK: [0x7a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[254:255], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], s[2:3], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], s[4:5], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], s[100:101], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], flat_scratch, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], vcc, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], tba, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], tma, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], ttmp[10:11], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], exec, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], v255
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], s2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], s101
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_lo
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_hi
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], tba_lo
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], tba_hi
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], tma_lo
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], tma_hi
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], ttmp11
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], m0
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_lo
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_hi
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], -v[1:2], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_class_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x28,0x7c]
-
-v_cmp_class_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x28,0x7c]
-
-v_cmp_class_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x28,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_class_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x28,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_class_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x29,0x7c]
-
-v_cmp_class_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_class_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x2a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_class_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x2a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_class_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x2b,0x7c]
-
-v_cmpx_class_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x40,0x7c]
-
-v_cmp_f_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x40,0x7c]
-
-v_cmp_f_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x40,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_f_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x40,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_f_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x41,0x7c]
-
-v_cmp_f_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_f_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_f_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x42,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_lt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x42,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_lt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x43,0x7c]
-
-v_cmp_lt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x44,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_eq_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x44,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_eq_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x45,0x7c]
-
-v_cmp_eq_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_eq_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_eq_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_eq_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x46,0x7c]
-
-v_cmp_le_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x46,0x7c]
-
-v_cmp_le_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x46,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_le_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x46,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_le_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x47,0x7c]
-
-v_cmp_le_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_le_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_le_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_le_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x48,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_gt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x48,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_gt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x49,0x7c]
-
-v_cmp_gt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_gt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_gt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_gt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_lg_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_lg_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4b,0x7c]
-
-v_cmp_lg_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lg_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lg_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lg_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4c,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ge_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_ge_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4d,0x7c]
-
-v_cmp_ge_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ge_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ge_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ge_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4e,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_o_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_o_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4f,0x7c]
-
-v_cmp_o_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_o_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_o_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_o_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_o_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x50,0x7c]
-
-v_cmp_u_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x50,0x7c]
-
-v_cmp_u_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x50,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_u_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x50,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_u_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x51,0x7c]
-
-v_cmp_u_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_u_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_u_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_u_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_u_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x52,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_nge_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x52,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_nge_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x53,0x7c]
-
-v_cmp_nge_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nge_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nge_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nge_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x54,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_nlg_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x54,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_nlg_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x55,0x7c]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlg_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x56,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ngt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x56,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_ngt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x57,0x7c]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ngt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x58,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_nle_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x58,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_nle_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x59,0x7c]
-
-v_cmp_nle_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nle_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nle_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nle_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_neq_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_neq_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5b,0x7c]
-
-v_cmp_neq_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_neq_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_neq_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_neq_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5c,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_nlt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_nlt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5d,0x7c]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5e,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_tru_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_tru_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5f,0x7c]
-
-v_cmp_tru_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_tru_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_tru_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_tru_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x60,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_f_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x60,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_f_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x61,0x7c]
-
-v_cmpx_f_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x62,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x62,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_lt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x63,0x7c]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x64,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_eq_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x64,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_eq_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x65,0x7c]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x66,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_le_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x66,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_le_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x67,0x7c]
-
-v_cmpx_le_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x68,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_gt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x68,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_gt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x69,0x7c]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lg_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_lg_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6b,0x7c]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6c,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ge_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6c,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_ge_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6d,0x7c]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6e,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_o_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6e,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_o_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6f,0x7c]
-
-v_cmpx_o_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x70,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_u_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x70,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_u_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x71,0x7c]
-
-v_cmpx_u_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x72,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nge_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x72,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_nge_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x73,0x7c]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x74,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nlg_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x74,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_nlg_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x75,0x7c]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x76,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ngt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x76,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_ngt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x77,0x7c]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x78,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nle_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x78,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_nle_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x79,0x7c]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_neq_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_neq_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7b,0x7c]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7c,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nlt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7c,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_nlt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7d,0x7c]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7e,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_tru_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7e,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_tru_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7f,0x7c]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x80,0x7c]
-
-v_cmp_f_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x80,0x7c]
-
-v_cmp_f_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x80,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x80,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x81,0x7c]
-
-v_cmp_f_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_f_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_f_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x82,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x82,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x83,0x7c]
-
-v_cmp_lt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x84,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x84,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x85,0x7c]
-
-v_cmp_eq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_eq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_eq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_eq_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x86,0x7c]
-
-v_cmp_le_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x86,0x7c]
-
-v_cmp_le_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x86,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x86,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x87,0x7c]
-
-v_cmp_le_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_le_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_le_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_le_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x88,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x88,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x89,0x7c]
-
-v_cmp_gt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_gt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_gt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_gt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8b,0x7c]
-
-v_cmp_lg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lg_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8d,0x7c]
-
-v_cmp_ge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ge_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_o_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_o_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8f,0x7c]
-
-v_cmp_o_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_o_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_o_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_o_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x90,0x7c]
-
-v_cmp_u_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x90,0x7c]
-
-v_cmp_u_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x90,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_u_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x90,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_u_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x91,0x7c]
-
-v_cmp_u_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_u_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_u_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_u_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x92,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x92,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x93,0x7c]
-
-v_cmp_nge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nge_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x94,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x94,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x95,0x7c]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x96,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ngt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x96,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ngt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x97,0x7c]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ngt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x98,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nle_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x98,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nle_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x99,0x7c]
-
-v_cmp_nle_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nle_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nle_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nle_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_neq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_neq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9b,0x7c]
-
-v_cmp_neq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_neq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_neq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_neq_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9d,0x7c]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_tru_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_tru_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9f,0x7c]
-
-v_cmp_tru_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_tru_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_tru_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_tru_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa1,0x7c]
-
-v_cmpx_f_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa3,0x7c]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa5,0x7c]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa7,0x7c]
-
-v_cmpx_le_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa9,0x7c]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xaa,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xaa,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xab,0x7c]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xac,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xac,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xad,0x7c]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xae,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_o_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xae,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_o_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xaf,0x7c]
-
-v_cmpx_o_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_u_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_u_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb1,0x7c]
-
-v_cmpx_u_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb3,0x7c]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb5,0x7c]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ngt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ngt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb7,0x7c]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nle_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nle_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb9,0x7c]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xba,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_neq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xba,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_neq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbb,0x7c]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbd,0x7c]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbe,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_tru_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbe,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_tru_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbf,0x7c]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc1,0x7c]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc3,0x7c]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc5,0x7c]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc7,0x7c]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc9,0x7c]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcb,0x7c]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcd,0x7c]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xce,0x7c]
-
-v_cmp_o_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xce,0x7c]
-
-v_cmp_o_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_o_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_o_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcf,0x7c]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_u_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_u_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd1,0x7c]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd3,0x7c]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd5,0x7c]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ngt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ngt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd7,0x7c]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nle_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nle_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd9,0x7c]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_neq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_neq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdb,0x7c]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdd,0x7c]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_tru_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_tru_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdf,0x7c]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe1,0x7c]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe3,0x7c]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe5,0x7c]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe7,0x7c]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe9,0x7c]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xeb,0x7c]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xed,0x7c]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_o_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_o_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xef,0x7c]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_u_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_u_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf1,0x7c]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf3,0x7c]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf5,0x7c]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ngt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ngt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf7,0x7c]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nle_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nle_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf9,0x7c]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_neq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_neq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfb,0x7c]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfd,0x7c]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_tru_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_tru_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xff,0x7c]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x40,0x7d]
-
-v_cmp_f_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x40,0x7d]
-
-v_cmp_f_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x40,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_f_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x40,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_f_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x40,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_f_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x40,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_f_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x41,0x7d]
-
-v_cmp_f_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x42,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_lt_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x42,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_lt_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x42,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_lt_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x42,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_lt_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x43,0x7d]
-
-v_cmp_lt_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x44,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_eq_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x44,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_eq_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x44,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_eq_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x44,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_eq_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x45,0x7d]
-
-v_cmp_eq_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x46,0x7d]
-
-v_cmp_le_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x46,0x7d]
-
-v_cmp_le_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x46,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_le_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x46,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_le_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x46,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_le_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x46,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_le_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x47,0x7d]
-
-v_cmp_le_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x48,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_gt_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x48,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_gt_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x48,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_gt_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x48,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_gt_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x49,0x7d]
-
-v_cmp_gt_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x4a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_ne_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x4a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_ne_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ne_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_ne_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4b,0x7d]
-
-v_cmp_ne_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x4c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_ge_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x4c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_ge_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ge_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_ge_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4d,0x7d]
-
-v_cmp_ge_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x4e,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_t_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x4e,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_t_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4e,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_t_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_t_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4f,0x7d]
-
-v_cmp_t_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x50,0x7d]
-
-v_cmp_f_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x50,0x7d]
-
-v_cmp_f_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x50,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_f_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x50,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_f_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x50,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_f_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x50,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_f_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x51,0x7d]
-
-v_cmp_f_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x52,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_lt_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x52,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_lt_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x52,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_lt_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x52,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_lt_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x53,0x7d]
-
-v_cmp_lt_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x54,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_eq_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x54,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_eq_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x54,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_eq_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x54,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_eq_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x55,0x7d]
-
-v_cmp_eq_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x56,0x7d]
-
-v_cmp_le_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x56,0x7d]
-
-v_cmp_le_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x56,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_le_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x56,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_le_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x56,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_le_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x56,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_le_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x57,0x7d]
-
-v_cmp_le_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x58,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_gt_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x58,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_gt_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x58,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_gt_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x58,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_gt_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x59,0x7d]
-
-v_cmp_gt_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x5a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_ne_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x5a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_ne_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ne_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_ne_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5b,0x7d]
-
-v_cmp_ne_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x5c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_ge_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x5c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_ge_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ge_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_ge_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5d,0x7d]
-
-v_cmp_ge_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x5e,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_t_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x5e,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_t_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5e,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_t_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5e,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_t_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5f,0x7d]
-
-v_cmp_t_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x60,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_f_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x60,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_f_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x60,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_f_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x60,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_f_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x61,0x7d]
-
-v_cmpx_f_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x62,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x62,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_lt_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x62,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lt_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x62,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_lt_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x63,0x7d]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x64,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x64,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x64,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_eq_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x64,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_eq_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x65,0x7d]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x66,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x66,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x66,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_le_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x66,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_le_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x67,0x7d]
-
-v_cmpx_le_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x68,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x68,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x68,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_gt_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x68,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_gt_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x69,0x7d]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x6a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x6a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ne_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ne_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6b,0x7d]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x6c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x6c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ge_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ge_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6d,0x7d]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x6e,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_t_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x6e,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_t_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6e,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_t_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6e,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_t_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6f,0x7d]
-
-v_cmpx_t_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x70,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_f_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x70,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_f_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x70,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_f_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x70,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_f_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x71,0x7d]
-
-v_cmpx_f_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x72,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x72,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_lt_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x72,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lt_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x72,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_lt_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x73,0x7d]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x74,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x74,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x74,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_eq_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x74,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_eq_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x75,0x7d]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x76,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x76,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x76,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_le_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x76,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_le_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x77,0x7d]
-
-v_cmpx_le_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x78,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x78,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x78,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_gt_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x78,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_gt_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x79,0x7d]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x7a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x7a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ne_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ne_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7b,0x7d]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x7c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x7c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ge_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ge_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7d,0x7d]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x7e,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_t_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x7e,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_t_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7e,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_t_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7e,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_t_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7f,0x7d]
-
-v_cmpx_t_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x80,0x7d]
-
-v_cmp_f_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x80,0x7d]
-
-v_cmp_f_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x81,0x7d]
-
-v_cmp_f_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x83,0x7d]
-
-v_cmp_lt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x85,0x7d]
-
-v_cmp_eq_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x86,0x7d]
-
-v_cmp_le_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x86,0x7d]
-
-v_cmp_le_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x87,0x7d]
-
-v_cmp_le_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x89,0x7d]
-
-v_cmp_gt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8b,0x7d]
-
-v_cmp_ne_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8d,0x7d]
-
-v_cmp_ge_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_t_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8f,0x7d]
-
-v_cmp_t_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x90,0x7d]
-
-v_cmp_f_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x90,0x7d]
-
-v_cmp_f_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x90,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x90,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x91,0x7d]
-
-v_cmp_f_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x92,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x92,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x93,0x7d]
-
-v_cmp_lt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x94,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x94,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x95,0x7d]
-
-v_cmp_eq_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x96,0x7d]
-
-v_cmp_le_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x96,0x7d]
-
-v_cmp_le_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x96,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x96,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x97,0x7d]
-
-v_cmp_le_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x98,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x98,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x99,0x7d]
-
-v_cmp_gt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9b,0x7d]
-
-v_cmp_ne_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9d,0x7d]
-
-v_cmp_ge_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_t_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9f,0x7d]
-
-v_cmp_t_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa1,0x7d]
-
-v_cmpx_f_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa3,0x7d]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa5,0x7d]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa7,0x7d]
-
-v_cmpx_le_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa9,0x7d]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xaa,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xaa,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xab,0x7d]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xac,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xac,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xad,0x7d]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xae,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xae,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xaf,0x7d]
-
-v_cmpx_t_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb1,0x7d]
-
-v_cmpx_f_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb3,0x7d]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb5,0x7d]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb7,0x7d]
-
-v_cmpx_le_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb9,0x7d]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xba,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xba,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbb,0x7d]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbc,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbc,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbd,0x7d]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, tba_lo, v2
-// CHECK: [0x6c,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, tba_hi, v2
-// CHECK: [0x6d,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, tma_lo, v2
-// CHECK: [0x6e,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, tma_hi, v2
-// CHECK: [0x6f,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, ttmp11, v2
-// CHECK: [0x7b,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbe,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbe,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbf,0x7d]
-
-v_cmpx_t_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 tba, v1, v2
-// CHECK: [0x6c,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 tma, v1, v2
-// CHECK: [0x6e,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 ttmp[10:11], v1, v2
-// CHECK: [0x7a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], tba_lo, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], tba_hi, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x6d,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], tma_lo, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], tma_hi, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x6f,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], ttmp11, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x7b,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, tba_lo
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, tba_hi
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xdb,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, tma_lo
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, tma_hi
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xdf,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, ttmp11
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf7,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc1,0x7d]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc3,0x7d]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc5,0x7d]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc7,0x7d]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc9,0x7d]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcb,0x7d]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcd,0x7d]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_t_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xce,0x7d]
-
-v_cmp_t_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xce,0x7d]
-
-v_cmp_t_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcf,0x7d]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd1,0x7d]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd3,0x7d]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd5,0x7d]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd7,0x7d]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd9,0x7d]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdb,0x7d]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdd,0x7d]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_t_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xde,0x7d]
-
-v_cmp_t_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xde,0x7d]
-
-v_cmp_t_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdf,0x7d]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe1,0x7d]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe3,0x7d]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe5,0x7d]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe7,0x7d]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe9,0x7d]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xeb,0x7d]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xed,0x7d]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xef,0x7d]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf1,0x7d]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf3,0x7d]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf5,0x7d]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf7,0x7d]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf9,0x7d]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfb,0x7d]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfd,0x7d]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, tba, v[2:3]
-// CHECK: [0x6c,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, tma, v[2:3]
-// CHECK: [0x6e,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, ttmp[10:11], v[2:3]
-// CHECK: [0x7a,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xff,0x7d]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 tba, v[1:2], v[2:3]
-// CHECK: [0x6c,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 tma, v[1:2], v[2:3]
-// CHECK: [0x6e,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 ttmp[10:11], v[1:2], v[2:3]
-// CHECK: [0x7a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], tba, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x6c,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], tma, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x6e,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], ttmp[10:11], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x7a,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], tba
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xd9,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], tma
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xdd,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], ttmp[10:11]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xf5,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xef,0x01,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_mov_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_mov_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_mov_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_mov_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_u32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_u32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_u32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_u32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_u32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f16_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_f16_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f16_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_f16_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_f32_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_f32_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_fract_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_fract_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_fract_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_fract_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_fract_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_fract_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_fract_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_trunc_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_trunc_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_trunc_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_trunc_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_trunc_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_trunc_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_trunc_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ceil_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_ceil_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ceil_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ceil_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ceil_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ceil_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_ceil_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rndne_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rndne_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rndne_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rndne_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rndne_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rndne_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rndne_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_floor_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_floor_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_floor_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_floor_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_floor_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_floor_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_floor_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_exp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_exp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_exp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_exp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_exp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_exp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_exp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_log_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_log_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_log_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_log_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_log_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_log_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_log_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_log_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_log_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_log_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_log_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rcp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rcp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rcp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rcp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rcp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rcp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rcp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rcp_iflag_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rcp_iflag_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rcp_iflag_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rcp_iflag_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rsq_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rsq_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rsq_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rsq_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rsq_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rsq_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rsq_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sqrt_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sqrt_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sqrt_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_sqrt_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sin_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sin_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sin_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sin_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sin_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sin_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_sin_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cos_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cos_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cos_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cos_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cos_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cos_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cos_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_not_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_not_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_not_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_not_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_not_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_not_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_not_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_not_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_bfrev_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_bfrev_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_bfrev_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ffbh_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ffbh_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ffbh_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ffbl_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ffbl_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ffbl_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ffbh_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ffbh_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ffbh_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_mant_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_mant_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_mant_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_frexp_mant_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f16_u16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_u16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_u16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f16_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_i16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_i16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_u16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_u16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_u16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_u16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rcp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rcp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rcp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rcp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rcp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rcp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rcp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sqrt_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sqrt_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sqrt_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_sqrt_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rsq_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rsq_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rsq_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rsq_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rsq_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rsq_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rsq_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_log_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_log_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_log_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_log_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_log_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_log_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_log_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_log_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_log_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_log_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_log_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_exp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_exp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_exp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_exp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_exp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_exp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_exp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_mant_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_mant_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_mant_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_frexp_mant_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_floor_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_floor_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_floor_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_floor_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_floor_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_floor_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_floor_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ceil_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_ceil_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ceil_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ceil_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ceil_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ceil_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_ceil_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_trunc_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_trunc_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_trunc_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_trunc_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rndne_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rndne_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rndne_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rndne_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rndne_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rndne_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rndne_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_fract_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_fract_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_fract_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_fract_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_fract_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_fract_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_fract_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sin_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sin_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sin_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sin_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sin_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sin_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_sin_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cos_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cos_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cos_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cos_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cos_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cos_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cos_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_exp_legacy_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_exp_legacy_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_exp_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_exp_legacy_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_exp_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_exp_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_log_legacy_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_log_legacy_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_log_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_log_legacy_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_log_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_log_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x03,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0xff,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x26,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x00,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x01,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x02,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x03,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x04,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x05,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x0e,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x00,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x01,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x02,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x03,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x04,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x05,0x06]
-
-v_add_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x16,0x06]
-
-v_add_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x00]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x01]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x02]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x03]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x04]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x05]
-
-v_add_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x16]
-
-v_add_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x26]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
-
-v_add_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x03,0x01,0xe4,0x00,0x00]
-
-v_add_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0xff,0xe4,0x00,0x00]
-
-v_add_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x02,0x01,0xe4,0x00,0x00]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x42,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x43,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x30,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x34,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x38,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x3c,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x10]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x30]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x01]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x03]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00]
-
-v_add_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x10,0x00]
-
-v_add_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x20,0x00]
-
-v_add_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x40,0x00]
-
-v_add_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x80,0x00]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x05,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0xff,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x26,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x00,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x01,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x02,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x03,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x04,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x05,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x0e,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x00,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x01,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x02,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x03,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x04,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x05,0x06]
-
-v_sub_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x16,0x06]
-
-v_sub_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x26,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x00]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x01]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x02]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x03]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x04]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x05]
-
-v_sub_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x16]
-
-v_sub_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x26]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x05,0x01,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0xff,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x04,0x01,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x42,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x43,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x30,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x34,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x38,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x3c,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x10]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x30]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
-
-v_sub_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
-
-v_sub_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
-
-v_sub_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x40,0x00]
-
-v_sub_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x80,0x00]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x07,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0xff,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x26,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x00,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x01,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x02,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x03,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x04,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x05,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x0e,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x00,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x01,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x02,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x03,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x04,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x05,0x06]
-
-v_subrev_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x16,0x06]
-
-v_subrev_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x26,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x00]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x01]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x02]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x03]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x04]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x05]
-
-v_subrev_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x16]
-
-v_subrev_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x26]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0xff,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x06,0x01,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x42,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x43,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x30,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x34,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x38,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x3c,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x10]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x30]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
-
-v_subrev_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00]
-
-v_subrev_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00]
-
-v_subrev_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x40,0x00]
-
-v_subrev_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x80,0x00]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x09,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0xff,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x26,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x00,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x01,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x02,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x03,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x04,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x05,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x0e,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x00,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x01,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x02,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x03,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x04,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x05,0x06]
-
-v_mul_legacy_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x16,0x06]
-
-v_mul_legacy_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x26,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x00]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x01]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x02]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x03]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x04]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x05]
-
-v_mul_legacy_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x16]
-
-v_mul_legacy_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x26]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x09,0x01,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0xff,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x08,0x01,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x42,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x43,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x30,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x34,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x38,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x3c,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x10]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x30]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
-
-v_mul_legacy_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00]
-
-v_mul_legacy_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x40,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x80,0x00]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x0b,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0xff,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x26,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x00,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x01,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x02,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x03,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x04,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x05,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x0e,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x00,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x01,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x02,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x03,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x04,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x05,0x06]
-
-v_mul_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x16,0x06]
-
-v_mul_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x26,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x00]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x01]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x02]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x03]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x04]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x05]
-
-v_mul_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x16]
-
-v_mul_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x26]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x0b,0x01,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0xff,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x0a,0x01,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x42,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x43,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x30,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x34,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x38,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x3c,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x10]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x30]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
-
-v_mul_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00]
-
-v_mul_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00]
-
-v_mul_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x40,0x00]
-
-v_mul_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x80,0x00]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x0d,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0xff,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x26,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x00,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x01,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x02,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x03,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x04,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x05,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x0e,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x00,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x01,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x02,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x03,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x04,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x05,0x06]
-
-v_mul_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x0e,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x00]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x01]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x02]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x03]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x04]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x05]
-
-v_mul_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x0e]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x0d,0x01,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0xff,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x0c,0x01,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1b,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x40,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x41,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x42,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x43,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x30,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x34,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x38,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x3c,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x01,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x0f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x11,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x21,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x2f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x10]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x30]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x01]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x03]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0xff,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x00,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x01,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x02,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x03,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x04,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x05,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x0e,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x00,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x01,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x02,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x03,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x04,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x05,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x0e,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x00]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x01]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x02]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x03]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x04]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x05]
-
-v_mul_hi_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x0e]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x0f,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0xff,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x0e,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x42,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x43,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x30,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x34,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x38,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x3c,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x10]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x30]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0xff,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x26,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x00,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x01,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x02,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x03,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x04,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x05,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x0e,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x00,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x01,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x02,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x03,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x04,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x05,0x06]
-
-v_mul_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x0e,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x00]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x01]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x02]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x03]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x04]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x05]
-
-v_mul_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x0e]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x11,0x01,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0xff,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x10,0x01,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x42,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x43,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x30,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x34,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x38,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x3c,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x10]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x30]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0xff,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x00,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x01,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x02,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x03,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x04,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x05,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x0e,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x00,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x01,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x02,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x03,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x04,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x05,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x0e,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x00]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x01]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x02]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x03]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x04]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x05]
-
-v_mul_hi_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x0e]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x13,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0xff,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x12,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x42,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x43,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x30,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x34,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x38,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x3c,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x10]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x30]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0xff,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x26,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x00,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x01,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x02,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x03,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x04,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x05,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x0e,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x00,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x01,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x02,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x03,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x04,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x05,0x06]
-
-v_min_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x16,0x06]
-
-v_min_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x26,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x00]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x01]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x02]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x03]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x04]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x05]
-
-v_min_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x16]
-
-v_min_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x26]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x00]
-
-v_min_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x15,0x01,0xe4,0x00,0x00]
-
-v_min_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0xff,0xe4,0x00,0x00]
-
-v_min_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x14,0x01,0xe4,0x00,0x00]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x42,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x43,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x30,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x34,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x38,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x3c,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x10]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x30]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
-
-v_min_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x10,0x00]
-
-v_min_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x20,0x00]
-
-v_min_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x40,0x00]
-
-v_min_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x80,0x00]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0xff,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x26,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x00,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x01,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x02,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x03,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x04,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x05,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x0e,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x00,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x01,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x02,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x03,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x04,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x05,0x06]
-
-v_max_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x16,0x06]
-
-v_max_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x26,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x00]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x01]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x02]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x03]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x04]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x05]
-
-v_max_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x16]
-
-v_max_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x26]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x00]
-
-v_max_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x17,0x01,0xe4,0x00,0x00]
-
-v_max_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0xff,0xe4,0x00,0x00]
-
-v_max_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x16,0x01,0xe4,0x00,0x00]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x42,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x43,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x30,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x34,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x38,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x3c,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x10]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x30]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
-
-v_max_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x10,0x00]
-
-v_max_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x20,0x00]
-
-v_max_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x40,0x00]
-
-v_max_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x80,0x00]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x19,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0xff,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x00,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x01,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x02,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x03,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x04,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x05,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x0e,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x00,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x01,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x02,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x03,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x04,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x05,0x06]
-
-v_min_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x0e,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x00]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x01]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x02]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x03]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x04]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x05]
-
-v_min_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x0e]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x00]
-
-v_min_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x19,0x01,0xe4,0x00,0x00]
-
-v_min_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0xff,0xe4,0x00,0x00]
-
-v_min_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x18,0x01,0xe4,0x00,0x00]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x42,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x43,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x30,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x34,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x38,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x3c,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x10]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x30]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x1b,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0xff,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x00,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x01,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x02,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x03,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x04,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x05,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x0e,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x00,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x01,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x02,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x03,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x04,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x05,0x06]
-
-v_max_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x0e,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x00]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x01]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x02]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x03]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x04]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x05]
-
-v_max_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x0e]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x00]
-
-v_max_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x1b,0x01,0xe4,0x00,0x00]
-
-v_max_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0xff,0xe4,0x00,0x00]
-
-v_max_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x1a,0x01,0xe4,0x00,0x00]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1b,0x00,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x40,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x41,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x42,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x43,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x30,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x34,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x38,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x3c,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x01,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x0f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x11,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x21,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x2f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x10]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x30]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x1d,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0xff,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x00,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x01,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x02,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x03,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x04,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x05,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x0e,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x00,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x01,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x02,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x03,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x04,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x05,0x06]
-
-v_min_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x0e,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x00]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x01]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x02]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x03]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x04]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x05]
-
-v_min_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x0e]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x00]
-
-v_min_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x1d,0x01,0xe4,0x00,0x00]
-
-v_min_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0xff,0xe4,0x00,0x00]
-
-v_min_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x1c,0x01,0xe4,0x00,0x00]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1b,0x00,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x40,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x41,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x42,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x43,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x30,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x34,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x38,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x3c,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x01,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x0f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x11,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x21,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x2f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x10]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x30]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x01]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x03]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0xff,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x00,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x01,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x02,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x03,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x04,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x05,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x0e,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x00,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x01,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x02,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x03,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x04,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x05,0x06]
-
-v_max_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x0e,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x00]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x01]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x02]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x03]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x04]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x05]
-
-v_max_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x0e]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x00]
-
-v_max_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x1f,0x01,0xe4,0x00,0x00]
-
-v_max_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0xff,0xe4,0x00,0x00]
-
-v_max_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x1e,0x01,0xe4,0x00,0x00]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x42,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x43,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x30,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x34,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x38,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x3c,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x10]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x30]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0xff,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x00,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x01,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x02,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x03,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x04,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x05,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x0e,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x00,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x01,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x02,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x03,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x04,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x05,0x06]
-
-v_lshrrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x0e,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x00]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x01]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x02]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x03]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x04]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x05]
-
-v_lshrrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x0e]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x21,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0xff,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x20,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x42,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x43,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x30,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x34,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x38,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x3c,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x10]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x30]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0xff,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x00,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x01,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x02,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x03,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x04,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x05,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x0e,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x00,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x01,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x02,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x03,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x04,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x05,0x06]
-
-v_ashrrev_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x0e,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x00]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x01]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x02]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x03]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x04]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x05]
-
-v_ashrrev_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x0e]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0xff,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x22,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x42,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x43,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x30,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x34,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x38,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x3c,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x10]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x30]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0xff,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x00,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x01,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x02,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x03,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x04,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x05,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x0e,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x00,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x01,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x02,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x03,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x04,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x05,0x06]
-
-v_lshlrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x0e,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x00]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x01]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x02]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x03]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x04]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x05]
-
-v_lshlrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x0e]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0xff,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x24,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x42,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x43,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x30,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x34,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x38,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x3c,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x10]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x30]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0xff,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x00,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x01,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x02,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x03,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x04,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x05,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x0e,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x00,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x01,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x02,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x03,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x04,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x05,0x06]
-
-v_and_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x0e,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x00]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x01]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x02]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x03]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x04]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x05]
-
-v_and_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x0e]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00]
-
-v_and_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00]
-
-v_and_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0xff,0xe4,0x00,0x00]
-
-v_and_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x26,0x01,0xe4,0x00,0x00]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x42,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x43,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x30,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x34,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x38,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x3c,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x10]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x30]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0xff,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x00,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x01,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x02,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x03,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x04,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x05,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x0e,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x00,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x01,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x02,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x03,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x04,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x05,0x06]
-
-v_or_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x0e,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x00]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x01]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x02]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x03]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x04]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x05]
-
-v_or_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x0e]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00]
-
-v_or_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00]
-
-v_or_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0xff,0xe4,0x00,0x00]
-
-v_or_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x28,0x01,0xe4,0x00,0x00]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x42,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x43,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x30,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x34,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x38,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x3c,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x10]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x30]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x2b,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0xff,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x00,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x01,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x02,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x03,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x04,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x05,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x0e,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x00,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x01,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x02,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x03,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x04,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x05,0x06]
-
-v_xor_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x0e,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x00]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x01]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x02]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x03]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x04]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x05]
-
-v_xor_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x0e]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x2b,0x01,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0xff,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x2a,0x01,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x42,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x43,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x30,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x34,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x38,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x3c,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x10]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x30]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x01]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x03]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
-
-v_mac_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x2d,0x01,0x06,0x06,0x06]
-
-v_mac_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0xff,0x06,0x06,0x06]
-
-v_mac_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x2c,0x01,0x06,0x06,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x26,0x06,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x0e,0x06,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x00,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x01,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x02,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x03,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x04,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x05,0x06]
-
-v_mac_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x16,0x06]
-
-v_mac_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x26,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x00]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x01]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x02]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x03]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x04]
-
-v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x05]
-
-v_mac_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x16]
-
-v_mac_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x26]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
-
-v_mac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
-
-v_mac_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0xff,0xe4,0x00,0x00]
-
-v_mac_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x2c,0x01,0xe4,0x00,0x00]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x42,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x43,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x30,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x34,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x38,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x3c,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x10]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x30]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
-
-v_mac_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x10,0x00]
-
-v_mac_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x20,0x00]
-
-v_mac_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x40,0x00]
-
-v_mac_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x80,0x00]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x33,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0xff,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x32,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x26,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x00,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x01,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x02,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x03,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x04,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x05,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x0e,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x00,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x01,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x02,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x03,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x04,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x05,0x06]
-
-v_add_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x0e,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x00]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x01]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x02]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x03]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x04]
-
-v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x05]
-
-v_add_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x0e]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x00]
-
-v_add_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x33,0x01,0xe4,0x00,0x00]
-
-v_add_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0xff,0xe4,0x00,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x32,0x01,0xe4,0x00,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x42,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x43,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x30,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x34,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x38,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x3c,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0x00]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x10]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x30]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x01]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x03]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
-
-v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0xff,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x26,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x00,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x01,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x02,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x03,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x04,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x05,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x0e,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x00,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x01,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x02,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x03,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x04,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x05,0x06]
-
-v_sub_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x0e,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x00]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x01]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x02]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x03]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x04]
-
-v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x05]
-
-v_sub_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x0e]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00]
-
-v_sub_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00]
-
-v_sub_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0xff,0xe4,0x00,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x34,0x01,0xe4,0x00,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x42,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x43,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x30,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x34,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x38,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x3c,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0x00]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x10]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x30]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
-
-v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0xff,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x26,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x00,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x01,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x02,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x03,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x04,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x05,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x0e,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x00,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x01,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x02,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x03,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x04,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x05,0x06]
-
-v_subrev_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x0e,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x00]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x01]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x02]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x03]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x04]
-
-v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x05]
-
-v_subrev_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x0e]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x00]
-
-v_subrev_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x37,0x01,0xe4,0x00,0x00]
-
-v_subrev_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0xff,0xe4,0x00,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x36,0x01,0xe4,0x00,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x42,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x43,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x30,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x34,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x38,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x3c,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0x00]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x10]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x30]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
-
-v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0xff,0x06,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x26,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x00,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x01,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x02,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x03,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x04,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x05,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x0e,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x00,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x01,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x02,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x03,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x04,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x05,0x06]
-
-v_addc_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x0e,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x00]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x01]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x02]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x03]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x04]
-
-v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x05]
-
-v_addc_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x0e]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x00]
-
-v_addc_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x39,0x01,0xe4,0x00,0x00]
-
-v_addc_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0xff,0xe4,0x00,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x38,0x01,0xe4,0x00,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x42,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x43,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x30,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x34,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x38,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x3c,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0x00]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x10]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x30]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
-
-v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0xff,0x06,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x26,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x00,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x01,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x02,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x03,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x04,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x05,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x0e,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x00,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x01,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x02,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x03,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x04,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x05,0x06]
-
-v_subb_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x0e,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x00]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x01]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x02]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x03]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x04]
-
-v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x05]
-
-v_subb_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x0e]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x00]
-
-v_subb_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x3b,0x01,0xe4,0x00,0x00]
-
-v_subb_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0xff,0xe4,0x00,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x3a,0x01,0xe4,0x00,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x42,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x43,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x30,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x34,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x38,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x3c,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0x00]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x10]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x30]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
-
-v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0xff,0x06,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x26,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x00,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x01,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x02,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x03,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x04,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x05,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x0e,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x00,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x01,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x02,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x03,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x04,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x05,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x0e,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x00]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x01]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x02]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x03]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x04]
-
-v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x05]
-
-v_subbrev_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x0e]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x00]
-
-v_subbrev_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x3d,0x01,0xe4,0x00,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0xff,0xe4,0x00,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x3c,0x01,0xe4,0x00,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x42,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x43,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x30,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x34,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x38,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x3c,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0x00]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x10]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x30]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
-
-v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x3f,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0xff,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x26,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x00,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x01,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x02,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x03,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x04,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x05,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x0e,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x00,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x01,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x02,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x03,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x04,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x05,0x06]
-
-v_add_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x16,0x06]
-
-v_add_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x26,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x00]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x01]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x02]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x03]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x04]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x05]
-
-v_add_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x16]
-
-v_add_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x26]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x00]
-
-v_add_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x3f,0x01,0xe4,0x00,0x00]
-
-v_add_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0xff,0xe4,0x00,0x00]
-
-v_add_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x3e,0x01,0xe4,0x00,0x00]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x00,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x40,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x41,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x42,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x43,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x30,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x34,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x38,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x3c,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x01,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x0f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x11,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x21,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x2f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x10]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x30]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x01]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x03]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00]
-
-v_add_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x10,0x00]
-
-v_add_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x20,0x00]
-
-v_add_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x40,0x00]
-
-v_add_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x80,0x00]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x41,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0xff,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x26,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x00,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x01,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x02,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x03,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x04,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x05,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x0e,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x00,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x01,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x02,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x03,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x04,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x05,0x06]
-
-v_sub_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x16,0x06]
-
-v_sub_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x26,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x00]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x01]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x02]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x03]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x04]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x05]
-
-v_sub_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x16]
-
-v_sub_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x26]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x41,0x01,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0xff,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x40,0x01,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x42,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x43,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x30,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x34,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x38,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x3c,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x10]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x30]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x01]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x03]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00]
-
-v_sub_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x10,0x00]
-
-v_sub_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x20,0x00]
-
-v_sub_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x40,0x00]
-
-v_sub_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x80,0x00]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x43,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0xff,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x26,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x00,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x01,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x02,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x03,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x04,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x05,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x0e,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x00,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x01,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x02,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x03,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x04,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x05,0x06]
-
-v_subrev_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x16,0x06]
-
-v_subrev_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x26,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x00]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x01]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x02]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x03]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x04]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x05]
-
-v_subrev_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x16]
-
-v_subrev_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x26]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x43,0x01,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0xff,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x42,0x01,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x42,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x43,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x30,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x34,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x38,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x3c,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x10]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x30]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x01]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x03]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00]
-
-v_subrev_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x10,0x00]
-
-v_subrev_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x20,0x00]
-
-v_subrev_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x40,0x00]
-
-v_subrev_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x80,0x00]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x45,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0xff,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x26,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x00,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x01,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x02,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x03,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x04,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x05,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x0e,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x00,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x01,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x02,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x03,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x04,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x05,0x06]
-
-v_mul_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x16,0x06]
-
-v_mul_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x26,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x00]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x01]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x02]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x03]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x04]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x05]
-
-v_mul_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x16]
-
-v_mul_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x26]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x45,0x01,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0xff,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x44,0x01,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x42,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x43,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x30,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x34,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x38,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x3c,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x10]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x30]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x01]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x03]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00]
-
-v_mul_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x10,0x00]
-
-v_mul_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x20,0x00]
-
-v_mul_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x40,0x00]
-
-v_mul_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x80,0x00]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
-
-v_mac_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x47,0x01,0x06,0x06,0x06]
-
-v_mac_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0xff,0x06,0x06,0x06]
-
-v_mac_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x46,0x01,0x06,0x06,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x26,0x06,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x0e,0x06,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x16,0x06,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x16,0x06,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x00,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x01,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x02,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x03,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x04,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x05,0x06]
-
-v_mac_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x16,0x06]
-
-v_mac_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x26,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x00]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x01]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x02]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x03]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x04]
-
-v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x05]
-
-v_mac_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x16]
-
-v_mac_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x26]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x00]
-
-v_mac_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x47,0x01,0xe4,0x00,0x00]
-
-v_mac_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0xff,0xe4,0x00,0x00]
-
-v_mac_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x46,0x01,0xe4,0x00,0x00]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1b,0x00,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x40,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x41,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x42,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x43,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x30,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x34,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x38,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x3c,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x01,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x0f,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x11,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1f,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x21,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x2f,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x10]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x30]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x01]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x03]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00]
-
-v_mac_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x10,0x00]
-
-v_mac_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x20,0x00]
-
-v_mac_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x40,0x00]
-
-v_mac_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x80,0x00]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x4d,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0xff,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x26,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x00,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x01,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x02,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x03,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x04,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x05,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x0e,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x00,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x01,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x02,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x03,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x04,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x05,0x06]
-
-v_add_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x0e,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x00]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x01]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x02]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x03]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x04]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x05]
-
-v_add_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x0e]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x00]
-
-v_add_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x4d,0x01,0xe4,0x00,0x00]
-
-v_add_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0xff,0xe4,0x00,0x00]
-
-v_add_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x4c,0x01,0xe4,0x00,0x00]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x42,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x43,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x30,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x34,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x38,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x3c,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x10]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x30]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x01]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x03]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0xff,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x26,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x00,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x01,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x02,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x03,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x04,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x05,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x0e,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x00,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x01,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x02,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x03,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x04,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x05,0x06]
-
-v_sub_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x0e,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x00]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x01]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x02]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x03]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x04]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x05]
-
-v_sub_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x0e]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x00]
-
-v_sub_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x4f,0x01,0xe4,0x00,0x00]
-
-v_sub_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0xff,0xe4,0x00,0x00]
-
-v_sub_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x4e,0x01,0xe4,0x00,0x00]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x42,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x43,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x30,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x34,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x38,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x3c,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x10]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x30]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x01]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x03]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x26,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x00,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x01,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x02,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x03,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x04,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x05,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x0e,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x00,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x01,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x02,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x03,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x04,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x05,0x06]
-
-v_subrev_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x0e,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x00]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x01]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x02]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x03]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x04]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x05]
-
-v_subrev_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x0e]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00]
-
-v_subrev_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x51,0x01,0xe4,0x00,0x00]
-
-v_subrev_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0xff,0xe4,0x00,0x00]
-
-v_subrev_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x50,0x01,0xe4,0x00,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x40,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x41,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x42,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x43,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x30,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x34,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x38,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x3c,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x01,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x0f,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x11,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1f,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x21,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x2f,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x10]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x30]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x01]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x03]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x00,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x01,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x02,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x03,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x04,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x05,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x0e,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x00,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x01,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x02,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x03,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x04,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x05,0x06]
-
-v_mul_lo_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x0e,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x00]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x01]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x02]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x03]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x04]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x05]
-
-v_mul_lo_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x0e]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x00]
-
-v_mul_lo_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x53,0x01,0xe4,0x00,0x00]
-
-v_mul_lo_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0xff,0xe4,0x00,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x52,0x01,0xe4,0x00,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x00,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x40,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x41,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x42,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x43,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x30,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x34,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x38,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x3c,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x01,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x0f,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x11,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1f,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x21,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x2f,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x10]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x30]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x01]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x03]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x00,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x01,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x02,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x03,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x04,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x05,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x0e,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x00,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x01,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x02,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x03,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x04,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x05,0x06]
-
-v_lshlrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x0e,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x00]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x01]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x02]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x03]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x04]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x05]
-
-v_lshlrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x0e]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x55,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0xff,0xe4,0x00,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x54,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x00,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x40,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x41,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x42,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x43,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x30,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x34,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x38,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x3c,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x0f,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x11,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1f,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x21,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x2f,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x10]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x30]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x01]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x03]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x57,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0xff,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x00,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x01,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x02,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x03,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x04,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x05,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x0e,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x00,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x01,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x02,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x03,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x04,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x05,0x06]
-
-v_lshrrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x0e,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x00]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x01]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x02]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x03]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x04]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x05]
-
-v_lshrrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x0e]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x57,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0xff,0xe4,0x00,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x56,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x42,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x43,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x30,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x34,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x38,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x3c,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x10]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x30]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x01]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x03]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x59,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0xff,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x00,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x01,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x02,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x03,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x04,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x05,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x0e,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x00,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x01,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x02,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x03,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x04,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x05,0x06]
-
-v_ashrrev_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x0e,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x00]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x01]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x02]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x03]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x04]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x05]
-
-v_ashrrev_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x0e]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x59,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0xff,0xe4,0x00,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x58,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1b,0x00,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x40,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x41,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x42,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x43,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x30,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x34,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x38,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x3c,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x0f,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x11,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1f,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x21,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x2f,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x10]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x30]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x01]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x03]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x5b,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0xff,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x26,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x00,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x01,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x02,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x03,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x04,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x05,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x0e,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x00,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x01,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x02,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x03,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x04,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x05,0x06]
-
-v_max_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x16,0x06]
-
-v_max_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x26,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x00]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x01]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x02]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x03]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x04]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x05]
-
-v_max_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x16]
-
-v_max_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x26]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x00]
-
-v_max_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x5b,0x01,0xe4,0x00,0x00]
-
-v_max_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0xff,0xe4,0x00,0x00]
-
-v_max_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x5a,0x01,0xe4,0x00,0x00]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1b,0x00,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x40,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x41,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x42,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x43,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x30,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x34,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x38,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x3c,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x01,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x0f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x11,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x21,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x2f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x10]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x30]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x01]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x03]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00]
-
-v_max_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x10,0x00]
-
-v_max_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x20,0x00]
-
-v_max_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x40,0x00]
-
-v_max_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x80,0x00]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x5d,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0xff,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x26,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x00,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x01,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x02,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x03,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x04,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x05,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x0e,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x00,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x01,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x02,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x03,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x04,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x05,0x06]
-
-v_min_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x16,0x06]
-
-v_min_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x26,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x00]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x01]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x02]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x03]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x04]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x05]
-
-v_min_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x16]
-
-v_min_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x26]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x00]
-
-v_min_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x5d,0x01,0xe4,0x00,0x00]
-
-v_min_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0xff,0xe4,0x00,0x00]
-
-v_min_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x5c,0x01,0xe4,0x00,0x00]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1b,0x00,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x40,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x41,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x42,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x43,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x30,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x34,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x38,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x3c,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x01,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x0f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x11,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x21,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x2f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x10]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x30]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x01]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x03]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00]
-
-v_min_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x10,0x00]
-
-v_min_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x20,0x00]
-
-v_min_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x40,0x00]
-
-v_min_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x80,0x00]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x5f,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0xff,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x00,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x01,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x02,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x03,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x04,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x05,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x0e,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x00,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x01,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x02,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x03,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x04,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x05,0x06]
-
-v_max_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x0e,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x00]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x01]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x02]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x03]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x04]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x05]
-
-v_max_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x0e]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x00]
-
-v_max_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x5f,0x01,0xe4,0x00,0x00]
-
-v_max_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0xff,0xe4,0x00,0x00]
-
-v_max_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x5e,0x01,0xe4,0x00,0x00]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x42,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x43,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x30,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x34,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x38,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x3c,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x10]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x30]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x01]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x03]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x61,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0xff,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x00,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x01,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x02,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x03,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x04,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x05,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x0e,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x00,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x01,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x02,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x03,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x04,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x05,0x06]
-
-v_max_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x0e,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x00]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x01]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x02]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x03]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x04]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x05]
-
-v_max_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x0e]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x00]
-
-v_max_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x61,0x01,0xe4,0x00,0x00]
-
-v_max_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0xff,0xe4,0x00,0x00]
-
-v_max_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x60,0x01,0xe4,0x00,0x00]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x42,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x43,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x30,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x34,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x38,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x3c,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x10]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x30]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x01]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x03]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x63,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0xff,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x00,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x01,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x02,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x03,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x04,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x05,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x0e,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x00,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x01,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x02,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x03,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x04,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x05,0x06]
-
-v_min_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x0e,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x00]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x01]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x02]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x03]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x04]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x05]
-
-v_min_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x0e]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x00]
-
-v_min_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x63,0x01,0xe4,0x00,0x00]
-
-v_min_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0xff,0xe4,0x00,0x00]
-
-v_min_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x62,0x01,0xe4,0x00,0x00]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x42,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x43,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x30,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x34,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x38,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x3c,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x10]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x30]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x01]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x03]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0xff,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x00,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x01,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x02,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x03,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x04,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x05,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x0e,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x00,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x01,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x02,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x03,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x04,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x05,0x06]
-
-v_min_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x0e,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x00]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x01]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x02]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x03]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x04]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x05]
-
-v_min_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x0e]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x00]
-
-v_min_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00]
-
-v_min_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0xff,0xe4,0x00,0x00]
-
-v_min_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x64,0x01,0xe4,0x00,0x00]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x42,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x43,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x30,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x34,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x38,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x3c,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x10]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x30]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0xff,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x26,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x00,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x01,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x02,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x03,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x04,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x05,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x0e,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x00,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x01,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x02,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x03,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x04,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x05,0x06]
-
-v_ldexp_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x16,0x06]
-
-v_ldexp_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x26,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x00]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x01]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x02]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x03]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x04]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x05]
-
-v_ldexp_f16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x0e]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0xff,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x66,0x01,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x42,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x43,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x30,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x34,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x38,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x3c,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x10]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x30]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
-
-v_ldexp_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
-
-v_ldexp_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x21,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_class_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_class_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_class_f32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x0e]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x23,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_class_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_class_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_class_f32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x0e]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x29,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_class_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_class_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_class_f16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x0e]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x2b,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_class_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_class_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_class_f16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x0e]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x41,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_f_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_f_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_f_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_f_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x43,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_lt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_lt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_lt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_lt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x45,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_eq_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_eq_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_eq_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_eq_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x47,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_le_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_le_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_le_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_le_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x49,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_gt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_gt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_gt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_gt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4b,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_lg_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_lg_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_lg_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_lg_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4d,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_ge_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_ge_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_ge_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_ge_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4f,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_o_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_o_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_o_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_o_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x51,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_u_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_u_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_u_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_u_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x53,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_nge_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_nge_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_nge_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_nge_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x55,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_nlg_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_nlg_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x57,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_ngt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_ngt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x59,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_nle_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_nle_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_nle_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_nle_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5b,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_neq_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_neq_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_neq_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_neq_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5d,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_nlt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_nlt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5f,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_tru_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_tru_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_tru_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_tru_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x61,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_f_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_f_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x63,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_lt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x65,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_eq_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x67,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_le_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_le_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x69,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_gt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6b,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_lg_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_lg_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6d,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_ge_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6f,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_o_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_o_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_o_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_o_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x71,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_u_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_u_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_u_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_u_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x73,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nge_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nge_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x75,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x77,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x79,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nle_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nle_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7b,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_neq_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_neq_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7d,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7f,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_tru_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_tru_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x81,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_f_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_f_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_f_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_f_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x83,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_lt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_lt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_lt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_lt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x85,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_eq_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_eq_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_eq_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_eq_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x87,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_le_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_le_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_le_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_le_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x89,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_gt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_gt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_gt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_gt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8b,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_lg_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_lg_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_lg_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_lg_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8d,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_ge_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_ge_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_ge_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_ge_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8f,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_o_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_o_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_o_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_o_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x91,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_u_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_u_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_u_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_u_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x93,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_nge_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_nge_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_nge_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_nge_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x95,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_nlg_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_nlg_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x97,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_ngt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_ngt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x99,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_nle_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_nle_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_nle_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_nle_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9b,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_neq_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_neq_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_neq_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_neq_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9d,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_nlt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_nlt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9f,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmp_tru_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmp_tru_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmp_tru_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmp_tru_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa1,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_f_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_f_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa3,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_lt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa5,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_eq_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa7,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_le_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_le_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa9,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_gt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xab,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_lg_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_lg_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xad,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_ge_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xaf,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_o_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_o_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_o_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_o_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb1,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_u_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_u_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_u_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_u_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb3,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nge_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nge_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb5,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb7,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb9,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nle_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nle_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbb,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_neq_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_neq_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbd,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0xff,0x00,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbf,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x20,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x00,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x01,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x02,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x03,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x04,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x05,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x16,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x26,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x00]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x01]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x02]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x03]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x04]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x05]
-
-v_cmpx_tru_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x16]
-
-v_cmpx_tru_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x26]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x41,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_f_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_f_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x43,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_lt_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_lt_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x45,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_eq_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_eq_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x47,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_le_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_le_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x49,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_gt_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_gt_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4b,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_ne_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_ne_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4d,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_ge_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_ge_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4f,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_t_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_t_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x51,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_f_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_f_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x53,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_lt_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_lt_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x55,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_eq_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_eq_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x57,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_le_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_le_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x59,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_gt_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_gt_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5b,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_ne_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_ne_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5d,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_ge_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_ge_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5f,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_t_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_t_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x61,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x63,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x65,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x67,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x69,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6b,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ne_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6d,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6f,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_t_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_t_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x71,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x73,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x75,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x77,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x79,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7b,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ne_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7d,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7f,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_t_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_t_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x81,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_f_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_f_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x83,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_lt_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_lt_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x85,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_eq_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_eq_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x87,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_le_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_le_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x89,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_gt_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_gt_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8b,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_ne_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_ne_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8d,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_ge_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_ge_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8f,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_t_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_t_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x91,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_f_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_f_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x93,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_lt_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_lt_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x95,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_eq_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_eq_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x97,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_le_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_le_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x99,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_gt_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_gt_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9b,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_ne_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_ne_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9d,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_ge_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_ge_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9f,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmp_t_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmp_t_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa1,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa3,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa5,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa7,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa9,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xab,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ne_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xad,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xaf,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_t_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_t_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb1,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_f_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_f_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb3,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_lt_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb5,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_eq_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb7,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_le_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_le_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb9,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_gt_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbb,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ne_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbd,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_ge_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x0e]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0xff,0x00,0x06,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbf,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x00,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x01,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x02,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x03,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x04,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x05,0x06]
-
-v_cmpx_t_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x0e,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x00]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x01]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x02]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x03]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x04]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x05]
-
-v_cmpx_t_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x0e]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_ds.s b/llvm/test/MC/AMDGPU/gfx8_asm_ds.s
new file mode 100644
index 0000000000000..da0297f7c3101
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_ds.s
@@ -0,0 +1,3160 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+ds_add_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd8,0xff,0x02,0x00,0x00]
+
+ds_add_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd8,0x01,0xff,0x00,0x00]
+
+ds_add_u32 v1, v2
+// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x01,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd8,0xff,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd8,0x01,0xff,0x00,0x00]
+
+ds_sub_u32 v1, v2
+// CHECK: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x03,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd8,0xff,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd8,0x01,0xff,0x00,0x00]
+
+ds_rsub_u32 v1, v2
+// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x05,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd8,0xff,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd8,0x01,0xff,0x00,0x00]
+
+ds_inc_u32 v1, v2
+// CHECK: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x07,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
+
+ds_dec_u32 v1, v2
+// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x09,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_i32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0xff,0x00,0x00]
+
+ds_min_i32 v1, v2
+// CHECK: [0x00,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x0b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_i32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0xff,0x00,0x00]
+
+ds_max_i32 v1, v2
+// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x0d,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0xff,0x00,0x00]
+
+ds_min_u32 v1, v2
+// CHECK: [0x00,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x0f,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd8,0x01,0xff,0x00,0x00]
+
+ds_max_u32 v1, v2
+// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x11,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd8,0xff,0x02,0x00,0x00]
+
+ds_and_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd8,0x01,0xff,0x00,0x00]
+
+ds_and_b32 v1, v2
+// CHECK: [0x00,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x13,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd8,0xff,0x02,0x00,0x00]
+
+ds_or_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd8,0x01,0xff,0x00,0x00]
+
+ds_or_b32 v1, v2
+// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x15,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd8,0xff,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd8,0x01,0xff,0x00,0x00]
+
+ds_xor_b32 v1, v2
+// CHECK: [0x00,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x17,0xd8,0x01,0x02,0x00,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0xff,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0x01,0xff,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0xff,0x00]
+
+ds_mskor_b32 v1, v2, v3
+// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x19,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b32 v1, v2
+// CHECK: [0x00,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x1b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1c,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0xff,0x03,0x00]
+
+ds_write2_b32 v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0x02,0xff,0x00]
+
+ds_write2_b32 v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x1d,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1e,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0xff,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0x02,0xff,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x1f,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0x01,0xff,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0xff,0x00]
+
+ds_cmpst_b32 v1, v2, v3
+// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x21,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x22,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x22,0xd8,0x01,0xff,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0xff,0x00]
+
+ds_cmpst_f32 v1, v2, v3
+// CHECK: [0x00,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x23,0xd8,0x01,0x02,0x03,0x00]
+
+ds_min_f32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_f32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd8,0x01,0xff,0x00,0x00]
+
+ds_min_f32 v1, v2
+// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x25,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_f32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd8,0x01,0xff,0x00,0x00]
+
+ds_max_f32 v1, v2
+// CHECK: [0x00,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x27,0xd8,0x01,0x02,0x00,0x00]
+
+ds_nop
+// CHECK: [0x00,0x00,0x28,0xd8,0x00,0x00,0x00,0x00]
+
+ds_add_f32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_f32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_add_f32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0xff,0x00,0x00]
+
+ds_add_f32 v1, v2
+// CHECK: [0x00,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_f32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_f32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_f32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x2b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x3c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x3c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b8 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x3c,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b8 v1, v2
+// CHECK: [0x00,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x3d,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x3e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x3e,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b16 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x3e,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b16 v1, v2
+// CHECK: [0x00,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x3f,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0xff,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0x01,0xff,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x41,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x42,0xd8,0xff,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x42,0xd8,0x01,0xff,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x43,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0xff,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0x01,0xff,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x45,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x46,0xd8,0xff,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x46,0xd8,0x01,0xff,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x47,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0xff,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0x01,0xff,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x49,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x4a,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2
+// CHECK: [0x00,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x4b,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2
+// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x4d,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x4e,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x4f,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x50,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x50,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x50,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x50,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x51,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x52,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x52,0xd8,0x01,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x52,0xd8,0xff,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x52,0xd8,0x01,0xff,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x53,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x54,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x54,0xd8,0x01,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x54,0xd8,0xff,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x54,0xd8,0x01,0xff,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x55,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x56,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x56,0xd8,0x01,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x56,0xd8,0xff,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x56,0xd8,0x01,0xff,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x57,0xd8,0x01,0x02,0x00,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0x03,0xff]
+
+ds_mskor_rtn_b32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0xff,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0x01,0xff,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0xff,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x59,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x5a,0xd8,0xff,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0xff,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x5b,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_wrxchg2_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x5d,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x5f,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0x03,0xff]
+
+ds_cmpst_rtn_b32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0x01,0xff,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0xff,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x61,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0x03,0xff]
+
+ds_cmpst_rtn_f32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0x01,0xff,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0xff,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x63,0xd8,0x01,0x02,0x03,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x64,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x64,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_f32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x64,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x64,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2
+// CHECK: [0x00,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x65,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_f32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x66,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x66,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2
+// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x67,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0x03,0xff]
+
+ds_wrap_rtn_b32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x69,0xd8,0x01,0x02,0x03,0x05]
+
+ds_add_rtn_f32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0x02,0x00,0xff]
+
+ds_add_rtn_f32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x6a,0xd8,0xff,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0xff,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v2
+// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x6b,0xd8,0x01,0x02,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x6c,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x6c,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_b32 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x6c,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1
+// CHECK: [0x00,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x6d,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x6e,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read2_b32 v[5:6], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x6e,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset1:255
+// CHECK: [0x00,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127
+// CHECK: [0x7f,0x00,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x6f,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x70,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read2st64_b32 v[5:6], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x70,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset1:255
+// CHECK: [0x00,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127
+// CHECK: [0x7f,0x00,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x71,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x72,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x72,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i8 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x72,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1
+// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x73,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x74,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x74,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u8 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x74,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1
+// CHECK: [0x00,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x75,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i16 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x76,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1
+// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x77,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u16 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x78,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1
+// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x79,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0xff]
+
+ds_swizzle_b32 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd8,0xff,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1
+// CHECK: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05]
+
+ds_permute_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_permute_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0xff]
+
+ds_permute_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0xff,0x02,0x00,0x05]
+
+ds_permute_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0xff,0x00,0x05]
+
+ds_permute_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_permute_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_permute_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_bpermute_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0xff]
+
+ds_bpermute_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x7e,0xd8,0xff,0x02,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0xff,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0xff,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_add_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x81,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x82,0xd8,0xff,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x82,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x83,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0xff,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x85,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x86,0xd8,0xff,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x86,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x87,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0xff,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x89,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_min_i64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x8b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_max_i64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x8d,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_min_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x8f,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_max_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x91,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x92,0xd8,0xff,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x92,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_and_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x93,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0xff,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_or_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x95,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x96,0xd8,0xff,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x96,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x97,0xd8,0x01,0x02,0x00,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0xff,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0x99,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_write_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x9b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9c,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x9d,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9e,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x9f,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xa1,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa2,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xa3,0xd8,0x01,0x02,0x03,0x00]
+
+ds_min_f64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_min_f64 v1, v[2:3]
+// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xa5,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_max_f64 v1, v[2:3]
+// CHECK: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xa7,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0xff,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc1,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_sub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc2,0xd8,0xff,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc3,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_rsub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0xff,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc5,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_inc_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc6,0xd8,0xff,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc7,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_dec_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0xff,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc9,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_i64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xca,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xca,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xcb,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_i64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xcd,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xce,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xce,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xcf,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xd1,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_and_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd2,0xd8,0xff,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xd3,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_or_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0xff,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xd5,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_xor_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd6,0xd8,0xff,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xd7,0xd8,0x01,0x02,0x00,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_mskor_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0xff,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xd9,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_wrxchg_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xda,0xd8,0xff,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xda,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xdb,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0x03,0xfc]
+
+ds_wrxchg2_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xdd,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0x03,0xfc]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xdf,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_cmpst_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xe1,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_cmpst_rtn_f64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xe3,0xd8,0x01,0x02,0x03,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_f64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xe5,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_f64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe6,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xe7,0xd8,0x01,0x02,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:65535
+// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[254:255], v1 offset:65535
+// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read_b64 v[5:6], v255 offset:65535
+// CHECK: [0xff,0xff,0xec,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1
+// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:0
+// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:4
+// CHECK: [0x04,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xed,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xee,0xd8,0x01,0x00,0x00,0xfc]
+
+ds_read2_b64 v[5:8], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xee,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset1:255
+// CHECK: [0x00,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127
+// CHECK: [0x7f,0x00,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xef,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xf0,0xd8,0x01,0x00,0x00,0xfc]
+
+ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xf0,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset1:255
+// CHECK: [0x00,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127
+// CHECK: [0x7f,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xf1,0xd8,0x01,0x00,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_condxchg32_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd8,0xff,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xfd,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd9,0xff,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1
+// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x01,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd9,0xff,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1
+// CHECK: [0x00,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x03,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd9,0xff,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1
+// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x05,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd9,0xff,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1
+// CHECK: [0x00,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x07,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd9,0xff,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1
+// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x09,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v255 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1
+// CHECK: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:0
+// CHECK: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:4
+// CHECK: [0x04,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v255 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1
+// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:0
+// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:4
+// CHECK: [0x04,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0d,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1
+// CHECK: [0x00,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0f,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1
+// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x11,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd9,0xff,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1
+// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x13,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd9,0xff,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1
+// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x15,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd9,0xff,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1
+// CHECK: [0x00,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x17,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1
+// CHECK: [0x00,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x1b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v255 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1
+// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:0
+// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:4
+// CHECK: [0x04,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x25,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v255 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1
+// CHECK: [0x00,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:0
+// CHECK: [0x00,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:4
+// CHECK: [0x04,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x27,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v255 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1
+// CHECK: [0x00,0x00,0x2a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:0
+// CHECK: [0x00,0x00,0x2a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:4
+// CHECK: [0x04,0x00,0x2a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x2b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:65535 gds
+// CHECK: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all gds
+// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:0 gds
+// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:4 gds
+// CHECK: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_init v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x33,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_init v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x33,0xd9,0xff,0x00,0x00,0x00]
+
+ds_gws_init v1 gds
+// CHECK: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_init v1 offset:0 gds
+// CHECK: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_init v1 offset:4 gds
+// CHECK: [0x04,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:65535 gds
+// CHECK: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v gds
+// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:0 gds
+// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:4 gds
+// CHECK: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x37,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_br v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x37,0xd9,0xff,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 gds
+// CHECK: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 offset:0 gds
+// CHECK: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 offset:4 gds
+// CHECK: [0x04,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:65535 gds
+// CHECK: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p gds
+// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:0 gds
+// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:4 gds
+// CHECK: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_barrier v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x3b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_barrier v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x3b,0xd9,0xff,0x00,0x00,0x00]
+
+ds_gws_barrier v1 gds
+// CHECK: [0x00,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_barrier v1 offset:0 gds
+// CHECK: [0x00,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_barrier v1 offset:4 gds
+// CHECK: [0x04,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_consume v5 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0x05]
+
+ds_consume v255 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0xff]
+
+ds_consume v5
+// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:0
+// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:4
+// CHECK: [0x04,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:65535 gds
+// CHECK: [0xff,0xff,0x7b,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v255 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0xff]
+
+ds_append v5
+// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:0
+// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:4
+// CHECK: [0x04,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:65535 gds
+// CHECK: [0xff,0xff,0x7d,0xd9,0x00,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x7f,0xd9,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v255, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x7f,0xd9,0x01,0x00,0x00,0xff]
+
+ds_ordered_count v5, v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x7f,0xd9,0xff,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 gds
+// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:0 gds
+// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:4 gds
+// CHECK: [0x04,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
+
+ds_add_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x80,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x80,0xd9,0xff,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1
+// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x81,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x82,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x82,0xd9,0xff,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1
+// CHECK: [0x00,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x83,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x84,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x84,0xd9,0xff,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1
+// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x85,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x86,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x86,0xd9,0xff,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1
+// CHECK: [0x00,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x87,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x88,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x88,0xd9,0xff,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1
+// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x89,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v255 offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1
+// CHECK: [0x00,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:0
+// CHECK: [0x00,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:4
+// CHECK: [0x04,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x8b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v255 offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1
+// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:0
+// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:4
+// CHECK: [0x04,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x8d,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1
+// CHECK: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x8f,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x90,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x90,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1
+// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x91,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x92,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x92,0xd9,0xff,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1
+// CHECK: [0x00,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x93,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x94,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x94,0xd9,0xff,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1
+// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x95,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x96,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x96,0xd9,0xff,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1
+// CHECK: [0x00,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x97,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1
+// CHECK: [0x00,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x9b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v255 offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1
+// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:0
+// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:4
+// CHECK: [0x04,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xa5,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v255 offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1
+// CHECK: [0x00,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:0
+// CHECK: [0x00,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:4
+// CHECK: [0x04,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xa7,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:65535
+// CHECK: [0xff,0xff,0xbc,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v255, v[2:4] offset:65535
+// CHECK: [0xff,0xff,0xbc,0xd9,0xff,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[253:255] offset:65535
+// CHECK: [0xff,0xff,0xbc,0xd9,0x01,0xfd,0x00,0x00]
+
+ds_write_b96 v1, v[2:4]
+// CHECK: [0x00,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:0
+// CHECK: [0x00,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:4
+// CHECK: [0x04,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xbd,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:65535
+// CHECK: [0xff,0xff,0xbe,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v255, v[2:5] offset:65535
+// CHECK: [0xff,0xff,0xbe,0xd9,0xff,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[252:255] offset:65535
+// CHECK: [0xff,0xff,0xbe,0xd9,0x01,0xfc,0x00,0x00]
+
+ds_write_b128 v1, v[2:5]
+// CHECK: [0x00,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:0
+// CHECK: [0x00,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:4
+// CHECK: [0x04,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:65535 gds
+// CHECK: [0xff,0xff,0xbf,0xd9,0x01,0x02,0x00,0x00]
+
+ds_read_b96 v[5:7], v1 offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[253:255], v1 offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd9,0x01,0x00,0x00,0xfd]
+
+ds_read_b96 v[5:7], v255 offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1
+// CHECK: [0x00,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:0
+// CHECK: [0x00,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:4
+// CHECK: [0x04,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xfd,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:65535
+// CHECK: [0xff,0xff,0xfe,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[252:255], v1 offset:65535
+// CHECK: [0xff,0xff,0xfe,0xd9,0x01,0x00,0x00,0xfc]
+
+ds_read_b128 v[5:8], v255 offset:65535
+// CHECK: [0xff,0xff,0xfe,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1
+// CHECK: [0x00,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:0
+// CHECK: [0x00,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:4
+// CHECK: [0x04,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xff,0xd9,0x01,0x00,0x00,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_exp.s b/llvm/test/MC/AMDGPU/gfx8_asm_exp.s
new file mode 100644
index 0000000000000..9e049d7f84d52
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_exp.s
@@ -0,0 +1,82 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+exp mrt0 v0, v0, v0, v0
+// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrtz v0, v0, v0, v0
+// CHECK: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp null v0, v0, v0, v0
+// CHECK: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp pos0 v0, v0, v0, v0
+// CHECK: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp param0 v0, v0, v0, v0
+// CHECK: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v255, v0, v0, v0
+// CHECK: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00]
+
+exp mrt0 v0, v255, v0, v0
+// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00]
+
+exp mrt0 v0, v0, v255, v0
+// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00]
+
+exp mrt0 v0, v0, v0, v255
+// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff]
+
+exp mrt0 v0, off, off, off
+// CHECK: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, off, off
+// CHECK: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, off, off
+// CHECK: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, v0, off
+// CHECK: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, off, v0, off
+// CHECK: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, v0, off
+// CHECK: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, off
+// CHECK: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, off, v0
+// CHECK: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, off, off, v0
+// CHECK: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, off, v0
+// CHECK: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, off, v0
+// CHECK: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, v0, v0
+// CHECK: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, off, v0, v0
+// CHECK: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, v0, v0
+// CHECK: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, off, off
+// CHECK: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, v0 done
+// CHECK: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, v0 compr
+// CHECK: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, v0 vm
+// CHECK: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_flat.s b/llvm/test/MC/AMDGPU/gfx8_asm_flat.s
new file mode 100644
index 0000000000000..4a62f04f4183e
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_flat.s
@@ -0,0 +1,601 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+flat_load_ubyte v5, v[1:2]
+// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte v255, v[1:2]
+// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_ubyte v5, v[254:255]
+// CHECK: [0x00,0x00,0x40,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_ubyte v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x41,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x42,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2]
+// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v255, v[1:2]
+// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_sbyte v5, v[254:255]
+// CHECK: [0x00,0x00,0x44,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x45,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x46,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2]
+// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v255, v[1:2]
+// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_ushort v5, v[254:255]
+// CHECK: [0x00,0x00,0x48,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x49,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x4a,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2]
+// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v255, v[1:2]
+// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_sshort v5, v[254:255]
+// CHECK: [0x00,0x00,0x4c,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x4d,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x4e,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2]
+// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v255, v[1:2]
+// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_dword v5, v[254:255]
+// CHECK: [0x00,0x00,0x50,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2] glc
+// CHECK: [0x00,0x00,0x51,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2] slc
+// CHECK: [0x00,0x00,0x52,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2]
+// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[254:255], v[1:2]
+// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0xfe]
+
+flat_load_dwordx2 v[5:6], v[254:255]
+// CHECK: [0x00,0x00,0x54,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2] glc
+// CHECK: [0x00,0x00,0x55,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2] slc
+// CHECK: [0x00,0x00,0x56,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2]
+// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[253:255], v[1:2]
+// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0xfd]
+
+flat_load_dwordx3 v[5:7], v[254:255]
+// CHECK: [0x00,0x00,0x58,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2] glc
+// CHECK: [0x00,0x00,0x59,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2] slc
+// CHECK: [0x00,0x00,0x5a,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2]
+// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[252:255], v[1:2]
+// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0xfc]
+
+flat_load_dwordx4 v[5:8], v[254:255]
+// CHECK: [0x00,0x00,0x5c,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2] glc
+// CHECK: [0x00,0x00,0x5d,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2] slc
+// CHECK: [0x00,0x00,0x5e,0xdc,0x01,0x00,0x00,0x05]
+
+flat_store_byte v[1:2], v2
+// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte v[254:255], v2
+// CHECK: [0x00,0x00,0x60,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_byte v[1:2], v255
+// CHECK: [0x00,0x00,0x60,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_byte v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x61,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x62,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v2
+// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[254:255], v2
+// CHECK: [0x00,0x00,0x68,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v255
+// CHECK: [0x00,0x00,0x68,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_short v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x69,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x6a,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v2
+// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[254:255], v2
+// CHECK: [0x00,0x00,0x70,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v255
+// CHECK: [0x00,0x00,0x70,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_dword v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x71,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x72,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x74,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x74,0xdc,0x01,0xfe,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x75,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x76,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4]
+// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[254:255], v[2:4]
+// CHECK: [0x00,0x00,0x78,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[253:255]
+// CHECK: [0x00,0x00,0x78,0xdc,0x01,0xfd,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4] glc
+// CHECK: [0x00,0x00,0x79,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4] slc
+// CHECK: [0x00,0x00,0x7a,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5]
+// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[254:255], v[2:5]
+// CHECK: [0x00,0x00,0x7c,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[252:255]
+// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0xfc,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5] glc
+// CHECK: [0x00,0x00,0x7d,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5] slc
+// CHECK: [0x00,0x00,0x7e,0xdc,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v2
+// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[254:255], v2
+// CHECK: [0x00,0x00,0x00,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v255
+// CHECK: [0x00,0x00,0x00,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_swap v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x01,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x02,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x04,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x04,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x04,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_cmpswap v0, v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x05,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x06,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v2
+// CHECK: [0x00,0x00,0x08,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[254:255], v2
+// CHECK: [0x00,0x00,0x08,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v255
+// CHECK: [0x00,0x00,0x08,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_add v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x09,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x0a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v2
+// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[254:255], v2
+// CHECK: [0x00,0x00,0x0c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v255
+// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_sub v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x0d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x0e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v2
+// CHECK: [0x00,0x00,0x10,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[254:255], v2
+// CHECK: [0x00,0x00,0x10,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v255
+// CHECK: [0x00,0x00,0x10,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_smin v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x11,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x12,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v2
+// CHECK: [0x00,0x00,0x14,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[254:255], v2
+// CHECK: [0x00,0x00,0x14,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v255
+// CHECK: [0x00,0x00,0x14,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_umin v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x15,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x16,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v2
+// CHECK: [0x00,0x00,0x18,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[254:255], v2
+// CHECK: [0x00,0x00,0x18,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v255
+// CHECK: [0x00,0x00,0x18,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_smax v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x19,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x1a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v2
+// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[254:255], v2
+// CHECK: [0x00,0x00,0x1c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v255
+// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_umax v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x1d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x1e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v2
+// CHECK: [0x00,0x00,0x20,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[254:255], v2
+// CHECK: [0x00,0x00,0x20,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v255
+// CHECK: [0x00,0x00,0x20,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_and v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x21,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x22,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v2
+// CHECK: [0x00,0x00,0x24,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[254:255], v2
+// CHECK: [0x00,0x00,0x24,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v255
+// CHECK: [0x00,0x00,0x24,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_or v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x25,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x26,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v2
+// CHECK: [0x00,0x00,0x28,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[254:255], v2
+// CHECK: [0x00,0x00,0x28,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v255
+// CHECK: [0x00,0x00,0x28,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_xor v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x29,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x2a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v2
+// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[254:255], v2
+// CHECK: [0x00,0x00,0x2c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v255
+// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_inc v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x2d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x2e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v2
+// CHECK: [0x00,0x00,0x30,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[254:255], v2
+// CHECK: [0x00,0x00,0x30,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v255
+// CHECK: [0x00,0x00,0x30,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_dec v0, v[1:2], v2 glc
+// CHECK: [0x00,0x00,0x31,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v2 slc
+// CHECK: [0x00,0x00,0x32,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x80,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x80,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_swap_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x81,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x82,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5]
+// CHECK: [0x00,0x00,0x84,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[254:255], v[2:5]
+// CHECK: [0x00,0x00,0x84,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[252:255]
+// CHECK: [0x00,0x00,0x84,0xdd,0x01,0xfc,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[0:1], v[1:2], v[2:5] glc
+// CHECK: [0x00,0x00,0x85,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5] slc
+// CHECK: [0x00,0x00,0x86,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x88,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x88,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x88,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_add_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x89,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x8a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x8c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_sub_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x8d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x8e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x90,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x90,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x90,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_smin_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x91,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x92,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x94,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x94,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x94,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_umin_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x95,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x96,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x98,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x98,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x98,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_smax_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x99,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x9a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0x9c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_umax_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0x9d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0x9e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0xa0,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_and_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0xa1,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0xa2,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0xa4,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_or_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0xa5,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0xa6,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0xa8,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_xor_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0xa9,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0xaa,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xac,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0xac,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0xac,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_inc_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0xad,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0xae,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[254:255], v[2:3]
+// CHECK: [0x00,0x00,0xb0,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[254:255]
+// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_dec_x2 v[0:1], v[1:2], v[2:3] glc
+// CHECK: [0x00,0x00,0xb1,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3] slc
+// CHECK: [0x00,0x00,0xb2,0xdd,0x01,0x02,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
new file mode 100644
index 0000000000000..e8f1f6ee04ac8
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mimg.s
@@ -0,0 +1,6865 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+image_load v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x03,0x00]
+
+image_load v5, v1, s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x17,0x00]
+
+image_load v5, v1, ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x02,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x80]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v252, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_mip v5, v[252:253], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_mip v5, v[1:2], s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_mip v5, v[1:2], ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:8], v[1:2], s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x06,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x80]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_pck v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_pck v5, v1, s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_pck v5, v1, ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x08,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x09,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x0a,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_pck_sgn v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_pck_sgn v5, v1, s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_pck_sgn v5, v1, ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x0c,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x0d,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x0e,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v252, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_mip_pck v5, v[252:253], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_mip_pck v5, v[1:2], s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_mip_pck v5, v[1:2], ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:8], v[1:2], s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x10,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x11,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x12,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v252, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[252:253], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:8], v[1:2], s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x14,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x15,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x16,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store v1, v252, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x04,0x00]
+
+image_store v1, v2, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x17,0x00]
+
+image_store v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:4], v2, s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x20,0xf2,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x22,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm d16
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x80]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v252, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_mip v1, v[252:253], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x04,0x00]
+
+image_store_mip v1, v[2:3], s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x17,0x00]
+
+image_store_mip v1, v[2:3], ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:4], v[2:3], s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x24,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x26,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm d16
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x80]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_pck v1, v252, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x04,0x00]
+
+image_store_pck v1, v2, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x17,0x00]
+
+image_store_pck v1, v2, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:4], v2, s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x28,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x2a,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_mip_pck v1, v[252:253], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x04,0x00]
+
+image_store_mip_pck v1, v[2:3], s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x17,0x00]
+
+image_store_mip_pck v1, v[2:3], ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:4], v[2:3], s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x2c,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x2e,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0xfc,0x02,0x00]
+
+image_get_resinfo v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0xfc,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x03,0x00]
+
+image_get_resinfo v5, v1, s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x17,0x00]
+
+image_get_resinfo v5, v1, ttmp[4:11] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x1d,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x3a,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_swap v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_swap v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_swap v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_swap v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x40,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x42,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[252:253], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v255, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[92:99] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_cmpswap v[5:6], v1, ttmp[4:11] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_cmpswap v[5:8], v1, s[8:15] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v[1:2], s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v[1:3], s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm glc
+// CHECK: [0x00,0x33,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm slc
+// CHECK: [0x00,0x13,0x44,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm lwe
+// CHECK: [0x00,0x13,0x46,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm da
+// CHECK: [0x00,0x53,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_add v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_add v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_add v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_add v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x48,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x4a,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_sub v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_sub v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_sub v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_sub v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x4c,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x4e,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_smin v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_smin v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_smin v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_smin v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x50,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x52,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_umin v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_umin v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_umin v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_umin v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x54,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x56,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_smax v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_smax v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_smax v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_smax v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x58,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x5a,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_umax v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_umax v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_umax v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_umax v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x5c,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x5e,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_and v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_and v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_and v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_and v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x60,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x62,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_or v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_or v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_or v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_or v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x64,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x66,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_xor v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_xor v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_xor v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_xor v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x68,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x6a,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_inc v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_inc v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_inc v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_inc v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x6c,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x6e,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_dec v5, v255, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0xff,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_dec v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_dec v5, v1, ttmp[4:11] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_dec v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x70,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x72,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v252, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample v5, v252, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample v5, v1, s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample v5, v1, s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample v5, v1, ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample v5, v1, s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample v5, v1, s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample v5, v1, s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:8], v1, s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x80,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x81,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x82,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_cl v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_cl v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_cl v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_cl v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x86,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d v5, v[246:248], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_d v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_d v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x88,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x89,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x8a,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d_cl v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_d_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_d_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x8c,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x8d,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x8e,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_l v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_l v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_l v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_l v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x92,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_b v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_b v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x96,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b_cl v5, v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b_cl v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_b_cl v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_b_cl v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x98,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x99,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x9a,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v252, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_lz v5, v252, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_lz v5, v1, s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_lz v5, v1, ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_lz v5, v1, s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:8], v1, s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x9c,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x9d,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x9e,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cl v5, v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_cl v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_cl v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_cl v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_d v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_d v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xaa,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d_cl v5, v[246:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_d_cl v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xac,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xad,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xae,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_l v5, v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_l v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_l v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_l v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b v5, v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_b v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_b v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_b_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xba,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_lz v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_lz v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_lz v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_lz v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xbe,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_o v5, v[251:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_o v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_o v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_o v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xc0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xc1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xc2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_cl_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_cl_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_cl_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_cl_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xc4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xc5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xc6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d_o v5, v[245:248], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_d_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_d_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xc8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xc9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xca,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_d_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xcc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xcd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xce,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_l_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_l_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_l_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_l_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xd0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xd1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xd2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_b_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_b_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xd4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xd5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xd6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b_cl_o v5, v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_b_cl_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xd8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xd9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xda,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_lz_o v5, v[251:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_lz_o v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_lz_o v5, v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_lz_o v5, v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xdc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xdd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xde,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xe0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xe1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xe2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cl_o v5, v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_cl_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xe4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xe5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xe6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_d_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xe8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xe9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xea,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xec,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xed,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xee,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_l_o v5, v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_l_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xf0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xf1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xf2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b_o v5, v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_b_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xf4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xf5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xf6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xf8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xf9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xfa,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_lz_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_lz_o v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xfc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xfd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xfe,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x80]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[252:255], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4 v[5:8], v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4 v[5:8], v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4 v[5:8], v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x00,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:9], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x01,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x02,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_cl v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x04,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x05,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x06,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_l v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x10,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x11,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x12,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_b v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x14,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x15,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x16,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x18,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x19,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x1a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[252:255], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_lz v[5:8], v[1:2], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x1c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:9], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x1d,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x1e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x20,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x21,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x22,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x24,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x25,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x26,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x30,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x31,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x32,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x34,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x35,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x36,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x38,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x39,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x3a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x3c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x3d,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x3e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_o v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x40,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x41,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x42,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x44,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x45,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x46,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x50,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x51,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x52,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x54,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x55,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x56,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x58,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x59,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x5a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x5c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:9], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x5d,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x5e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x60,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x61,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x62,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x64,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x65,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x66,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x70,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x71,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x72,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x74,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x75,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x76,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x78,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:9], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x79,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x7a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x7c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:9], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x7d,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x7e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x80]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v252, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0xfc,0x62,0x00]
+
+image_get_lod v5, v255, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0xff,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x63,0x00]
+
+image_get_lod v5, v1, s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x77,0x00]
+
+image_get_lod v5, v1, ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x7d,0x00]
+
+image_get_lod v5, v1, s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x82,0x00]
+
+image_get_lod v5, v1, s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x02,0x03]
+
+image_get_lod v5, v1, s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0xc2,0x03]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:8], v1, s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x80,0xf3,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x81,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x82,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd v5, v[246:248], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_cd v5, v[1:3], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_cd v5, v[1:3], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa0,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa1,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa2,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd_cl v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_cd_cl v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa4,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa5,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa6,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_c_cd v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_c_cd v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa8,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa9,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xaa,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[246:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xac,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xad,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xae,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd_o v5, v[245:248], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_cd_o v5, v[1:4], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_cd_o v5, v[1:4], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb0,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb1,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb2,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb4,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb5,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb6,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_c_cd_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb8,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb9,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xba,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], ttmp[4:11], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], ttmp[8:11] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xbc,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xbd,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xbe,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x62,0x80]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s b/llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s
new file mode 100644
index 0000000000000..d748885b67967
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mtbuf.s
@@ -0,0 +1,2689 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0xff,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_x v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_x v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_x v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_x v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_x v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_x v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_x v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0xfe,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_xy v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x10,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x18,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x20,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x28,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x30,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x38,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x40,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x48,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x50,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x58,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x60,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x68,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x70,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x78,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x00,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0xaf,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x9f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x80,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x80,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x80,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0xcf,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0xfd,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x11,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x19,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x21,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x29,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x31,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x39,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x41,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x49,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x51,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x59,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x61,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x69,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x71,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x79,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x01,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0xfc,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x11,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x19,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x21,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x29,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x31,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x39,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x41,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x49,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x51,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x59,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x61,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x69,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x71,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x79,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x01,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x89,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x89,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x89,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x89,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0xaf,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x9f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x80,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x80,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x80,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0xcf,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0xff,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_x v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_x v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_x v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_x v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_x v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_x v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_x v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x12,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x22,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x32,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x42,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x52,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x62,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x72,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x02,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0xfe,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_xy v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x12,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x22,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x32,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x42,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x52,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x62,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x72,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x02,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8a,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8a,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8a,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x9f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x80,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x80,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x80,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0xfd,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x13,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x23,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x33,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x43,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x53,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x63,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x73,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x03,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0xfc,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x13,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x23,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x33,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x43,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x53,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x63,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x73,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x03,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8b,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8b,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8b,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x9f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x80,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x80,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x80,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0xff,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_d16_x v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0xfe,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x14,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x24,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x34,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x44,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x54,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x64,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x74,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x04,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x9f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x80,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x80,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x80,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0xfd,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x15,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x25,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x35,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x45,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x55,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x65,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x75,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x05,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0xfc,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x6c]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x6d]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x6e]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x6f]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x15,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x25,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x35,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x45,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x55,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x65,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x75,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x05,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8d,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8d,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8d,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x9f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x80,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x80,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x80,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0xff,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_d16_x v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x16,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x26,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x36,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x46,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x56,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x66,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x76,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x06,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0xfe,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x16,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x26,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x36,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x46,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x56,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x66,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x76,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x06,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x9f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x80,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x80,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x80,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0xfd,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x17,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x27,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x37,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x47,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x57,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x67,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x77,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x07,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0xfc,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x6c]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x6d]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x6e]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x6f]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x17,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x27,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x37,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x47,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x57,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x67,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x77,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x07,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x9f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x80,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x80,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x80,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x43,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
new file mode 100644
index 0000000000000..9797942191ec7
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_mubuf.s
@@ -0,0 +1,5488 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_format_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_x v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_x v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_x v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_x v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_x v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_x v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_x v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xy v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_xy v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_xy v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_xy v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_xy v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_xy v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_xy v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_xy v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_xy v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xy v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_xy v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xy v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_xy v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_xy v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x06,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0xfd,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_xyz v[5:7], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0xfc,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_xyzw v[5:8], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0e,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_format_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_x v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_x v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_x v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_x v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_x v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_x v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_x v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x12,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xy v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_xy v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_xy v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_xy v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_xy v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_xy v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_xy v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_xy v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_xy v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xy v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_xy v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xy v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_xy v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_xy v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x16,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0xfd,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_xyz v[1:3], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1a,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0xfc,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_xyzw v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1e,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_d16_x v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_d16_x v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_d16_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_d16_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_d16_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_d16_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_d16_x v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_d16_x v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_d16_x v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_d16_x v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_d16_x v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_d16_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_d16_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_d16_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_d16_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_d16_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_d16_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_d16_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_d16_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_d16_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_d16_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_d16_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x22,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_d16_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x26,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0xfd,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_d16_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0xfc,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_d16_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2e,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_d16_x v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_d16_x v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_d16_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_d16_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_d16_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_d16_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_d16_x v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_d16_x v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_d16_x v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_d16_x v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_d16_x v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_d16_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_d16_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_d16_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_d16_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_d16_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_d16_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_d16_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_d16_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_d16_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_d16_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_d16_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x32,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_d16_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x36,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0xfd,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_d16_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x3a,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0xfc,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_d16_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x3e,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ubyte v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_ubyte v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_ubyte v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_ubyte v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_ubyte v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_ubyte v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_ubyte v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_ubyte v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_ubyte v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_ubyte v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_ubyte v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_ubyte v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ubyte v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_ubyte v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_ubyte v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ubyte v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ubyte v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ubyte v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ubyte v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_ubyte v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_ubyte v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_ubyte v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sbyte v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_sbyte v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_sbyte v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_sbyte v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_sbyte v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_sbyte v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_sbyte v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_sbyte v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_sbyte v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_sbyte v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_sbyte v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_sbyte v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sbyte v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_sbyte v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_sbyte v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sbyte v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sbyte v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sbyte v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sbyte v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_sbyte v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_sbyte v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_sbyte v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ushort v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ushort v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_ushort v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_ushort v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_ushort v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_ushort v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_ushort v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_ushort v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_ushort v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_ushort v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_ushort v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_ushort v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_ushort v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ushort v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_ushort v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_ushort v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ushort v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ushort v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ushort v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ushort v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_ushort v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_ushort v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sshort v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sshort v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_sshort v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_sshort v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_sshort v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_sshort v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_sshort v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_sshort v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_sshort v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_sshort v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_sshort v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_sshort v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_sshort v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sshort v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_sshort v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_sshort v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sshort v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sshort v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sshort v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sshort v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_sshort v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_sshort v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_sshort v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_dword v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dword v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dword v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dword v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dword v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_dword v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dword v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dword v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dword v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_dword v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_dword v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_dword v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_dword v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dword v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dword v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dword v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dword v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dword v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dword v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dword v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dword v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dword v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dword v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dword v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dwordx2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x56,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0xfd,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dwordx3 v[5:7], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x5a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0xfc,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dwordx4 v[5:8], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x6c]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x6d]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x6e]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x6f]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x5e,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_byte v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_byte v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_byte v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_byte v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_byte v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_byte v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_byte v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_byte v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_byte v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_byte v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_byte v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_byte v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_byte v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_byte v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_byte v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_byte v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_byte v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_byte v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_byte v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_byte v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_byte v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_byte v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_byte v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_byte v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x62,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_short v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_short v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_short v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_short v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_short v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_short v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_short v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_short v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_short v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_short v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_short v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_short v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_short v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_short v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_short v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_short v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_short v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_short v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_short v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_short v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_short v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_short v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_short v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_short v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x6a,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_dword v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dword v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dword v1, off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dword v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dword v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_dword v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dword v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dword v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dword v1, off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_dword v1, off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_dword v1, off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_dword v1, off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_dword v1, off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dword v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dword v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dword v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dword v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dword v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dword v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dword v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dword v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dword v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dword v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dword v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x72,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dwordx2 v[1:2], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x76,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0xfd,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dwordx3 v[1:3], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x7a,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0xfc,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dwordx4 v[1:4], off, ttmp[8:11], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6c]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6d]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6e]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6f]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x7e,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_lds_dword s[4:7], s0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[8:11], s0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x02,0x00]
+
+buffer_store_lds_dword s[96:99], s0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x18,0x00]
+
+buffer_store_lds_dword ttmp[8:11], s0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x1e,0x00]
+
+buffer_store_lds_dword s[4:7], s101 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x65]
+
+buffer_store_lds_dword s[4:7], flat_scratch_lo offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x66]
+
+buffer_store_lds_dword s[4:7], flat_scratch_hi offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x67]
+
+buffer_store_lds_dword s[4:7], vcc_lo offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x6a]
+
+buffer_store_lds_dword s[4:7], vcc_hi offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x6b]
+
+buffer_store_lds_dword s[4:7], tba_lo offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x6c]
+
+buffer_store_lds_dword s[4:7], tba_hi offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x6d]
+
+buffer_store_lds_dword s[4:7], tma_lo offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x6e]
+
+buffer_store_lds_dword s[4:7], tma_hi offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x6f]
+
+buffer_store_lds_dword s[4:7], ttmp11 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x7b]
+
+buffer_store_lds_dword s[4:7], m0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x7c]
+
+buffer_store_lds_dword s[4:7], exec_lo offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x7e]
+
+buffer_store_lds_dword s[4:7], exec_hi offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x7f]
+
+buffer_store_lds_dword s[4:7], 0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x80]
+
+buffer_store_lds_dword s[4:7], -1 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xc1]
+
+buffer_store_lds_dword s[4:7], 0.5 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xf0]
+
+buffer_store_lds_dword s[4:7], -4.0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xf7]
+
+buffer_store_lds_dword s[4:7], src_vccz offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xfb]
+
+buffer_store_lds_dword s[4:7], src_execz offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xfc]
+
+buffer_store_lds_dword s[4:7], src_scc offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xfd]
+
+buffer_store_lds_dword s[4:7], s0 lds
+// CHECK: [0x00,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[4:7], s0 offset:0 lds
+// CHECK: [0x00,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[4:7], s0 offset:7 lds
+// CHECK: [0x07,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[4:7], s0 offset:4095 lds glc
+// CHECK: [0xff,0x4f,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[4:7], s0 offset:4095 lds slc
+// CHECK: [0xff,0x0f,0xf7,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_wbinvl1
+// CHECK: [0x00,0x00,0xf8,0xe0,0x00,0x00,0x00,0x00]
+
+buffer_wbinvl1_vol
+// CHECK: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_swap v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_swap v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_swap v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_swap v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_swap v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_swap v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_swap v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_swap v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_swap v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_swap v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_swap v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_swap v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_swap v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_swap v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_swap v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_swap v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_swap v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_swap v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_swap v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_swap v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_swap v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_swap v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x02,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x06,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_add v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_add v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_add v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_add v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_add v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_add v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_add v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_add v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_add v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_add v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_add v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_add v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_add v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_add v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_add v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_add v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_add v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_add v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_add v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_add v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_add v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_add v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_sub v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_sub v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_sub v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_sub v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_sub v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_sub v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_sub v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_sub v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_sub v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_sub v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_sub v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_sub v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_sub v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_sub v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_sub v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_sub v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_sub v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_sub v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_sub v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_sub v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_sub v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_sub v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smin v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smin v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smin v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_smin v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_smin v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_smin v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_smin v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_smin v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_smin v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_smin v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_smin v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_smin v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smin v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_smin v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_smin v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smin v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smin v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_smin v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_smin v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_smin v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_smin v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_smin v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x12,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umin v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umin v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umin v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_umin v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_umin v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_umin v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_umin v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_umin v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_umin v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_umin v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_umin v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_umin v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umin v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_umin v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_umin v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umin v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umin v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_umin v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_umin v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_umin v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_umin v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_umin v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x16,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smax v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smax v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smax v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_smax v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_smax v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_smax v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_smax v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_smax v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_smax v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_smax v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_smax v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_smax v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smax v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_smax v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_smax v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smax v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smax v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_smax v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_smax v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_smax v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_smax v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_smax v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umax v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umax v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umax v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_umax v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_umax v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_umax v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_umax v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_umax v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_umax v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_umax v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_umax v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_umax v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umax v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_umax v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_umax v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umax v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umax v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_umax v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_umax v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_umax v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_umax v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_umax v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_and v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_and v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_and v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_and v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_and v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_and v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_and v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_and v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_and v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_and v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_and v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_and v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_and v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_and v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_and v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_and v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_and v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_and v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_and v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_and v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_and v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_and v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_and v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x22,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_or v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_or v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_or v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_or v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_or v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_or v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_or v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_or v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_or v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_or v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_or v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_or v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_or v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_or v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_or v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_or v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_or v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_or v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_or v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_or v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_or v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_or v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_or v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x26,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_xor v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_xor v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_xor v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_xor v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_xor v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_xor v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_xor v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_xor v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_xor v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_xor v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_xor v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_xor v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_xor v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_xor v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_xor v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_xor v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_xor v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_xor v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_xor v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_xor v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_xor v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_xor v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_inc v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_inc v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_inc v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_inc v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_inc v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_inc v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_inc v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_inc v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_inc v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_inc v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_inc v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_inc v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_inc v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_inc v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_inc v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_inc v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_inc v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_inc v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_inc v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_inc v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_inc v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_inc v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_dec v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_dec v5, off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_dec v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_dec v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_dec v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_dec v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_dec v5, off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_dec v5, off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_dec v5, off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_dec v5, off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_dec v5, off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_dec v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_dec v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_dec v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_dec v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_dec v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_dec v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_dec v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_dec v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_dec v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_dec v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_dec v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x32,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x82,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0xfc,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x86,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x8a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x8e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x92,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x96,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x9a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x9e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xa2,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xa6,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xaa,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xae,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, ttmp[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], tba_lo offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x6c]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], tba_hi offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x6d]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], tma_lo offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x6e]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], tma_hi offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x6f]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], ttmp11 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xb2,0xe1,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_smem.s b/llvm/test/MC/AMDGPU/gfx8_asm_smem.s
new file mode 100644
index 0000000000000..a39729b4b323d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_smem.s
@@ -0,0 +1,1165 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+s_load_dword s5, s[2:3], s2
+// CHECK: [0x41,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword s101, s[2:3], s2
+// CHECK: [0x41,0x19,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword flat_scratch_lo, s[2:3], s2
+// CHECK: [0x81,0x19,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword flat_scratch_hi, s[2:3], s2
+// CHECK: [0xc1,0x19,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword vcc_lo, s[2:3], s2
+// CHECK: [0x81,0x1a,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword vcc_hi, s[2:3], s2
+// CHECK: [0xc1,0x1a,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword tba_lo, s[2:3], s2
+// CHECK: [0x01,0x1b,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword tba_hi, s[2:3], s2
+// CHECK: [0x41,0x1b,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword tma_lo, s[2:3], s2
+// CHECK: [0x81,0x1b,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword tma_hi, s[2:3], s2
+// CHECK: [0xc1,0x1b,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword ttmp11, s[2:3], s2
+// CHECK: [0xc1,0x1e,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword s5, s[4:5], s2
+// CHECK: [0x42,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword s5, s[100:101], s2
+// CHECK: [0x72,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword s5, flat_scratch, s2
+// CHECK: [0x73,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword s5, vcc, s2
+// CHECK: [0x75,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword s5, tba, s2
+// CHECK: [0x76,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword s5, tma, s2
+// CHECK: [0x77,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword s5, ttmp[10:11], s2
+// CHECK: [0x7d,0x01,0x00,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x00,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x00,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x00,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x00,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], tba_lo
+// CHECK: [0x41,0x01,0x00,0xc0,0x6c,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], tba_hi
+// CHECK: [0x41,0x01,0x00,0xc0,0x6d,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], tma_lo
+// CHECK: [0x41,0x01,0x00,0xc0,0x6e,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], tma_hi
+// CHECK: [0x41,0x01,0x00,0xc0,0x6f,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], ttmp11
+// CHECK: [0x41,0x01,0x00,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x00,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], 0x7ffff
+// CHECK: [0x41,0x01,0x02,0xc0,0xff,0xff,0x07,0x00]
+
+s_load_dword s5, s[2:3], s2 glc
+// CHECK: [0x41,0x01,0x01,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], s2
+// CHECK: [0x81,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[12:13], s[2:3], s2
+// CHECK: [0x01,0x03,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[100:101], s[2:3], s2
+// CHECK: [0x01,0x19,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 flat_scratch, s[2:3], s2
+// CHECK: [0x81,0x19,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 vcc, s[2:3], s2
+// CHECK: [0x81,0x1a,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 tba, s[2:3], s2
+// CHECK: [0x01,0x1b,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 tma, s[2:3], s2
+// CHECK: [0x81,0x1b,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 ttmp[10:11], s[2:3], s2
+// CHECK: [0x81,0x1e,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[4:5], s2
+// CHECK: [0x82,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[100:101], s2
+// CHECK: [0xb2,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], flat_scratch, s2
+// CHECK: [0xb3,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], vcc, s2
+// CHECK: [0xb5,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], tba, s2
+// CHECK: [0xb6,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], tma, s2
+// CHECK: [0xb7,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], ttmp[10:11], s2
+// CHECK: [0xbd,0x02,0x04,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x04,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x04,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x04,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x04,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x04,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], tba_lo
+// CHECK: [0x81,0x02,0x04,0xc0,0x6c,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], tba_hi
+// CHECK: [0x81,0x02,0x04,0xc0,0x6d,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], tma_lo
+// CHECK: [0x81,0x02,0x04,0xc0,0x6e,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], tma_hi
+// CHECK: [0x81,0x02,0x04,0xc0,0x6f,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], ttmp11
+// CHECK: [0x81,0x02,0x04,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x04,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], 0x7ffff
+// CHECK: [0x81,0x02,0x06,0xc0,0xff,0xff,0x07,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], s2 glc
+// CHECK: [0x81,0x02,0x05,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], s2
+// CHECK: [0x01,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[24:27], s[2:3], s2
+// CHECK: [0x01,0x06,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[96:99], s[2:3], s2
+// CHECK: [0x01,0x18,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 ttmp[8:11], s[2:3], s2
+// CHECK: [0x01,0x1e,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[4:5], s2
+// CHECK: [0x02,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[100:101], s2
+// CHECK: [0x32,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], flat_scratch, s2
+// CHECK: [0x33,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], vcc, s2
+// CHECK: [0x35,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], tba, s2
+// CHECK: [0x36,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], tma, s2
+// CHECK: [0x37,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], ttmp[10:11], s2
+// CHECK: [0x3d,0x05,0x08,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], s101
+// CHECK: [0x01,0x05,0x08,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x05,0x08,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x05,0x08,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], vcc_lo
+// CHECK: [0x01,0x05,0x08,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], vcc_hi
+// CHECK: [0x01,0x05,0x08,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], tba_lo
+// CHECK: [0x01,0x05,0x08,0xc0,0x6c,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], tba_hi
+// CHECK: [0x01,0x05,0x08,0xc0,0x6d,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], tma_lo
+// CHECK: [0x01,0x05,0x08,0xc0,0x6e,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], tma_hi
+// CHECK: [0x01,0x05,0x08,0xc0,0x6f,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], ttmp11
+// CHECK: [0x01,0x05,0x08,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], m0
+// CHECK: [0x01,0x05,0x08,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], 0x7ffff
+// CHECK: [0x01,0x05,0x0a,0xc0,0xff,0xff,0x07,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], s2 glc
+// CHECK: [0x01,0x05,0x09,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], s2
+// CHECK: [0x01,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[24:31], s[2:3], s2
+// CHECK: [0x01,0x06,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[92:99], s[2:3], s2
+// CHECK: [0x01,0x17,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 ttmp[4:11], s[2:3], s2
+// CHECK: [0x01,0x1d,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[4:5], s2
+// CHECK: [0x02,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[100:101], s2
+// CHECK: [0x32,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], flat_scratch, s2
+// CHECK: [0x33,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], vcc, s2
+// CHECK: [0x35,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], tba, s2
+// CHECK: [0x36,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], tma, s2
+// CHECK: [0x37,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], ttmp[10:11], s2
+// CHECK: [0x3d,0x05,0x0c,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], s101
+// CHECK: [0x01,0x05,0x0c,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x05,0x0c,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x05,0x0c,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], vcc_lo
+// CHECK: [0x01,0x05,0x0c,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], vcc_hi
+// CHECK: [0x01,0x05,0x0c,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], tba_lo
+// CHECK: [0x01,0x05,0x0c,0xc0,0x6c,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], tba_hi
+// CHECK: [0x01,0x05,0x0c,0xc0,0x6d,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], tma_lo
+// CHECK: [0x01,0x05,0x0c,0xc0,0x6e,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], tma_hi
+// CHECK: [0x01,0x05,0x0c,0xc0,0x6f,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], ttmp11
+// CHECK: [0x01,0x05,0x0c,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], m0
+// CHECK: [0x01,0x05,0x0c,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], 0x7ffff
+// CHECK: [0x01,0x05,0x0e,0xc0,0xff,0xff,0x07,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], s2 glc
+// CHECK: [0x01,0x05,0x0d,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], s2
+// CHECK: [0x01,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[24:39], s[2:3], s2
+// CHECK: [0x01,0x06,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[84:99], s[2:3], s2
+// CHECK: [0x01,0x15,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[4:5], s2
+// CHECK: [0x02,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[100:101], s2
+// CHECK: [0x32,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], flat_scratch, s2
+// CHECK: [0x33,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], vcc, s2
+// CHECK: [0x35,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], tba, s2
+// CHECK: [0x36,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], tma, s2
+// CHECK: [0x37,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], ttmp[10:11], s2
+// CHECK: [0x3d,0x05,0x10,0xc0,0x02,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], s101
+// CHECK: [0x01,0x05,0x10,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x05,0x10,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x05,0x10,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], vcc_lo
+// CHECK: [0x01,0x05,0x10,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], vcc_hi
+// CHECK: [0x01,0x05,0x10,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], tba_lo
+// CHECK: [0x01,0x05,0x10,0xc0,0x6c,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], tba_hi
+// CHECK: [0x01,0x05,0x10,0xc0,0x6d,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], tma_lo
+// CHECK: [0x01,0x05,0x10,0xc0,0x6e,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], tma_hi
+// CHECK: [0x01,0x05,0x10,0xc0,0x6f,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], ttmp11
+// CHECK: [0x01,0x05,0x10,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], m0
+// CHECK: [0x01,0x05,0x10,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], 0x7ffff
+// CHECK: [0x01,0x05,0x12,0xc0,0xff,0xff,0x07,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], s2 glc
+// CHECK: [0x01,0x05,0x11,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], s2
+// CHECK: [0x42,0x01,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword s101, s[4:7], s2
+// CHECK: [0x42,0x19,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword flat_scratch_lo, s[4:7], s2
+// CHECK: [0x82,0x19,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword flat_scratch_hi, s[4:7], s2
+// CHECK: [0xc2,0x19,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword vcc_lo, s[4:7], s2
+// CHECK: [0x82,0x1a,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword vcc_hi, s[4:7], s2
+// CHECK: [0xc2,0x1a,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword tba_lo, s[4:7], s2
+// CHECK: [0x02,0x1b,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword tba_hi, s[4:7], s2
+// CHECK: [0x42,0x1b,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword tma_lo, s[4:7], s2
+// CHECK: [0x82,0x1b,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword tma_hi, s[4:7], s2
+// CHECK: [0xc2,0x1b,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword ttmp11, s[4:7], s2
+// CHECK: [0xc2,0x1e,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[8:11], s2
+// CHECK: [0x44,0x01,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[96:99], s2
+// CHECK: [0x70,0x01,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, ttmp[8:11], s2
+// CHECK: [0x7c,0x01,0x20,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x20,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x20,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x20,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x20,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x20,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], tba_lo
+// CHECK: [0x42,0x01,0x20,0xc0,0x6c,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], tba_hi
+// CHECK: [0x42,0x01,0x20,0xc0,0x6d,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], tma_lo
+// CHECK: [0x42,0x01,0x20,0xc0,0x6e,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], tma_hi
+// CHECK: [0x42,0x01,0x20,0xc0,0x6f,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], ttmp11
+// CHECK: [0x42,0x01,0x20,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x20,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], 0x7ffff
+// CHECK: [0x42,0x01,0x22,0xc0,0xff,0xff,0x07,0x00]
+
+s_buffer_load_dword s5, s[4:7], s2 glc
+// CHECK: [0x42,0x01,0x21,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s2
+// CHECK: [0x82,0x02,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[12:13], s[4:7], s2
+// CHECK: [0x02,0x03,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[100:101], s[4:7], s2
+// CHECK: [0x02,0x19,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 flat_scratch, s[4:7], s2
+// CHECK: [0x82,0x19,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 vcc, s[4:7], s2
+// CHECK: [0x82,0x1a,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 tba, s[4:7], s2
+// CHECK: [0x02,0x1b,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 tma, s[4:7], s2
+// CHECK: [0x82,0x1b,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 ttmp[10:11], s[4:7], s2
+// CHECK: [0x82,0x1e,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[8:11], s2
+// CHECK: [0x84,0x02,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[96:99], s2
+// CHECK: [0xb0,0x02,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], ttmp[8:11], s2
+// CHECK: [0xbc,0x02,0x24,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x24,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x24,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x24,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x24,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x24,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], tba_lo
+// CHECK: [0x82,0x02,0x24,0xc0,0x6c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], tba_hi
+// CHECK: [0x82,0x02,0x24,0xc0,0x6d,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], tma_lo
+// CHECK: [0x82,0x02,0x24,0xc0,0x6e,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], tma_hi
+// CHECK: [0x82,0x02,0x24,0xc0,0x6f,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], ttmp11
+// CHECK: [0x82,0x02,0x24,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], 0x7ffff
+// CHECK: [0x82,0x02,0x26,0xc0,0xff,0xff,0x07,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s2 glc
+// CHECK: [0x82,0x02,0x25,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s2
+// CHECK: [0x02,0x05,0x28,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[24:27], s[4:7], s2
+// CHECK: [0x02,0x06,0x28,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[96:99], s[4:7], s2
+// CHECK: [0x02,0x18,0x28,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 ttmp[8:11], s[4:7], s2
+// CHECK: [0x02,0x1e,0x28,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[8:11], s2
+// CHECK: [0x04,0x05,0x28,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[96:99], s2
+// CHECK: [0x30,0x05,0x28,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], ttmp[8:11], s2
+// CHECK: [0x3c,0x05,0x28,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s101
+// CHECK: [0x02,0x05,0x28,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_lo
+// CHECK: [0x02,0x05,0x28,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_hi
+// CHECK: [0x02,0x05,0x28,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_lo
+// CHECK: [0x02,0x05,0x28,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
+// CHECK: [0x02,0x05,0x28,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], tba_lo
+// CHECK: [0x02,0x05,0x28,0xc0,0x6c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], tba_hi
+// CHECK: [0x02,0x05,0x28,0xc0,0x6d,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], tma_lo
+// CHECK: [0x02,0x05,0x28,0xc0,0x6e,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], tma_hi
+// CHECK: [0x02,0x05,0x28,0xc0,0x6f,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], ttmp11
+// CHECK: [0x02,0x05,0x28,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], m0
+// CHECK: [0x02,0x05,0x28,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], 0x7ffff
+// CHECK: [0x02,0x05,0x2a,0xc0,0xff,0xff,0x07,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s2 glc
+// CHECK: [0x02,0x05,0x29,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s2
+// CHECK: [0x02,0x05,0x2c,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[24:31], s[4:7], s2
+// CHECK: [0x02,0x06,0x2c,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[92:99], s[4:7], s2
+// CHECK: [0x02,0x17,0x2c,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 ttmp[4:11], s[4:7], s2
+// CHECK: [0x02,0x1d,0x2c,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[8:11], s2
+// CHECK: [0x04,0x05,0x2c,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[96:99], s2
+// CHECK: [0x30,0x05,0x2c,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], ttmp[8:11], s2
+// CHECK: [0x3c,0x05,0x2c,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s101
+// CHECK: [0x02,0x05,0x2c,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_lo
+// CHECK: [0x02,0x05,0x2c,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_hi
+// CHECK: [0x02,0x05,0x2c,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_lo
+// CHECK: [0x02,0x05,0x2c,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
+// CHECK: [0x02,0x05,0x2c,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], tba_lo
+// CHECK: [0x02,0x05,0x2c,0xc0,0x6c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], tba_hi
+// CHECK: [0x02,0x05,0x2c,0xc0,0x6d,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], tma_lo
+// CHECK: [0x02,0x05,0x2c,0xc0,0x6e,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], tma_hi
+// CHECK: [0x02,0x05,0x2c,0xc0,0x6f,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], ttmp11
+// CHECK: [0x02,0x05,0x2c,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], m0
+// CHECK: [0x02,0x05,0x2c,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], 0x7ffff
+// CHECK: [0x02,0x05,0x2e,0xc0,0xff,0xff,0x07,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s2 glc
+// CHECK: [0x02,0x05,0x2d,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s2
+// CHECK: [0x02,0x05,0x30,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[24:39], s[4:7], s2
+// CHECK: [0x02,0x06,0x30,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[84:99], s[4:7], s2
+// CHECK: [0x02,0x15,0x30,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[8:11], s2
+// CHECK: [0x04,0x05,0x30,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[96:99], s2
+// CHECK: [0x30,0x05,0x30,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], ttmp[8:11], s2
+// CHECK: [0x3c,0x05,0x30,0xc0,0x02,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s101
+// CHECK: [0x02,0x05,0x30,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_lo
+// CHECK: [0x02,0x05,0x30,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_hi
+// CHECK: [0x02,0x05,0x30,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_lo
+// CHECK: [0x02,0x05,0x30,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
+// CHECK: [0x02,0x05,0x30,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], tba_lo
+// CHECK: [0x02,0x05,0x30,0xc0,0x6c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], tba_hi
+// CHECK: [0x02,0x05,0x30,0xc0,0x6d,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], tma_lo
+// CHECK: [0x02,0x05,0x30,0xc0,0x6e,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], tma_hi
+// CHECK: [0x02,0x05,0x30,0xc0,0x6f,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], ttmp11
+// CHECK: [0x02,0x05,0x30,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], m0
+// CHECK: [0x02,0x05,0x30,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], 0x7ffff
+// CHECK: [0x02,0x05,0x32,0xc0,0xff,0xff,0x07,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s2 glc
+// CHECK: [0x02,0x05,0x31,0xc0,0x02,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], m0
+// CHECK: [0x42,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s101, s[4:5], m0
+// CHECK: [0x42,0x19,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword flat_scratch_lo, s[4:5], m0
+// CHECK: [0x82,0x19,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword flat_scratch_hi, s[4:5], m0
+// CHECK: [0xc2,0x19,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword vcc_lo, s[4:5], m0
+// CHECK: [0x82,0x1a,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword vcc_hi, s[4:5], m0
+// CHECK: [0xc2,0x1a,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword tba_lo, s[4:5], m0
+// CHECK: [0x02,0x1b,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword tba_hi, s[4:5], m0
+// CHECK: [0x42,0x1b,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword tma_lo, s[4:5], m0
+// CHECK: [0x82,0x1b,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword tma_hi, s[4:5], m0
+// CHECK: [0xc2,0x1b,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword ttmp11, s[4:5], m0
+// CHECK: [0xc2,0x1e,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s1, s[6:7], m0
+// CHECK: [0x43,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s1, s[100:101], m0
+// CHECK: [0x72,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s1, flat_scratch, m0
+// CHECK: [0x73,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s1, vcc, m0
+// CHECK: [0x75,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s1, tba, m0
+// CHECK: [0x76,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s1, tma, m0
+// CHECK: [0x77,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s1, ttmp[10:11], m0
+// CHECK: [0x7d,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], 0x7ffff
+// CHECK: [0x42,0x00,0x42,0xc0,0xff,0xff,0x07,0x00]
+
+s_store_dword s1, s[4:5], m0 glc
+// CHECK: [0x42,0x00,0x41,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], m0
+// CHECK: [0x82,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[4:5], s[4:5], m0
+// CHECK: [0x02,0x01,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[100:101], s[4:5], m0
+// CHECK: [0x02,0x19,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 flat_scratch, s[4:5], m0
+// CHECK: [0x82,0x19,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 vcc, s[4:5], m0
+// CHECK: [0x82,0x1a,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 tba, s[4:5], m0
+// CHECK: [0x02,0x1b,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 tma, s[4:5], m0
+// CHECK: [0x82,0x1b,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 ttmp[10:11], s[4:5], m0
+// CHECK: [0x82,0x1e,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[6:7], m0
+// CHECK: [0x83,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[100:101], m0
+// CHECK: [0xb2,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], flat_scratch, m0
+// CHECK: [0xb3,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], vcc, m0
+// CHECK: [0xb5,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], tba, m0
+// CHECK: [0xb6,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], tma, m0
+// CHECK: [0xb7,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], ttmp[10:11], m0
+// CHECK: [0xbd,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], 0x7ffff
+// CHECK: [0x82,0x00,0x46,0xc0,0xff,0xff,0x07,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], m0 glc
+// CHECK: [0x82,0x00,0x45,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], m0
+// CHECK: [0x02,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[8:11], s[4:5], m0
+// CHECK: [0x02,0x02,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[96:99], s[4:5], m0
+// CHECK: [0x02,0x18,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 ttmp[8:11], s[4:5], m0
+// CHECK: [0x02,0x1e,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[6:7], m0
+// CHECK: [0x03,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[100:101], m0
+// CHECK: [0x32,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], flat_scratch, m0
+// CHECK: [0x33,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], vcc, m0
+// CHECK: [0x35,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], tba, m0
+// CHECK: [0x36,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], tma, m0
+// CHECK: [0x37,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], ttmp[10:11], m0
+// CHECK: [0x3d,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], 0x7ffff
+// CHECK: [0x02,0x01,0x4a,0xc0,0xff,0xff,0x07,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], m0 glc
+// CHECK: [0x02,0x01,0x49,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], m0
+// CHECK: [0x44,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword s101, s[8:11], m0
+// CHECK: [0x44,0x19,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword flat_scratch_lo, s[8:11], m0
+// CHECK: [0x84,0x19,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword flat_scratch_hi, s[8:11], m0
+// CHECK: [0xc4,0x19,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword vcc_lo, s[8:11], m0
+// CHECK: [0x84,0x1a,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword vcc_hi, s[8:11], m0
+// CHECK: [0xc4,0x1a,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword tba_lo, s[8:11], m0
+// CHECK: [0x04,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword tba_hi, s[8:11], m0
+// CHECK: [0x44,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword tma_lo, s[8:11], m0
+// CHECK: [0x84,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword tma_hi, s[8:11], m0
+// CHECK: [0xc4,0x1b,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword ttmp11, s[8:11], m0
+// CHECK: [0xc4,0x1e,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[12:15], m0
+// CHECK: [0x46,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[96:99], m0
+// CHECK: [0x70,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, ttmp[8:11], m0
+// CHECK: [0x7c,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], 0x7ffff
+// CHECK: [0x44,0x00,0x62,0xc0,0xff,0xff,0x07,0x00]
+
+s_buffer_store_dword s1, s[8:11], m0 glc
+// CHECK: [0x44,0x00,0x61,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], m0
+// CHECK: [0x84,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[4:5], s[8:11], m0
+// CHECK: [0x04,0x01,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[100:101], s[8:11], m0
+// CHECK: [0x04,0x19,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 flat_scratch, s[8:11], m0
+// CHECK: [0x84,0x19,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 vcc, s[8:11], m0
+// CHECK: [0x84,0x1a,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 tba, s[8:11], m0
+// CHECK: [0x04,0x1b,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 tma, s[8:11], m0
+// CHECK: [0x84,0x1b,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 ttmp[10:11], s[8:11], m0
+// CHECK: [0x84,0x1e,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[12:15], m0
+// CHECK: [0x86,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[96:99], m0
+// CHECK: [0xb0,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], ttmp[8:11], m0
+// CHECK: [0xbc,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], 0x7ffff
+// CHECK: [0x84,0x00,0x66,0xc0,0xff,0xff,0x07,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], m0 glc
+// CHECK: [0x84,0x00,0x65,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], m0
+// CHECK: [0x04,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[8:11], s[8:11], m0
+// CHECK: [0x04,0x02,0x68,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[96:99], s[8:11], m0
+// CHECK: [0x04,0x18,0x68,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 ttmp[8:11], s[8:11], m0
+// CHECK: [0x04,0x1e,0x68,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[12:15], m0
+// CHECK: [0x06,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[96:99], m0
+// CHECK: [0x30,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], ttmp[8:11], m0
+// CHECK: [0x3c,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], 0x7ffff
+// CHECK: [0x04,0x01,0x6a,0xc0,0xff,0xff,0x07,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], m0 glc
+// CHECK: [0x04,0x01,0x69,0xc0,0x7c,0x00,0x00,0x00]
+
+s_dcache_inv
+// CHECK: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_wb
+// CHECK: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_inv_vol
+// CHECK: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_wb_vol
+// CHECK: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime s[10:11]
+// CHECK: [0x80,0x02,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime s[12:13]
+// CHECK: [0x00,0x03,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime s[100:101]
+// CHECK: [0x00,0x19,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime flat_scratch
+// CHECK: [0x80,0x19,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime vcc
+// CHECK: [0x80,0x1a,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime tba
+// CHECK: [0x00,0x1b,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime tma
+// CHECK: [0x80,0x1b,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime ttmp[10:11]
+// CHECK: [0x80,0x1e,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime s[10:11]
+// CHECK: [0x80,0x02,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime s[12:13]
+// CHECK: [0x00,0x03,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime s[100:101]
+// CHECK: [0x00,0x19,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime flat_scratch
+// CHECK: [0x80,0x19,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime vcc
+// CHECK: [0x80,0x1a,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime tba
+// CHECK: [0x00,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime tma
+// CHECK: [0x80,0x1b,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime ttmp[10:11]
+// CHECK: [0x80,0x1e,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], s3
+// CHECK: [0x02,0x00,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x1, s[4:5], s3
+// CHECK: [0x42,0x00,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x7, s[4:5], s3
+// CHECK: [0xc2,0x01,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[6:7], s3
+// CHECK: [0x03,0x00,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[100:101], s3
+// CHECK: [0x32,0x00,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x0, flat_scratch, s3
+// CHECK: [0x33,0x00,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x0, vcc, s3
+// CHECK: [0x35,0x00,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x0, tba, s3
+// CHECK: [0x36,0x00,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x0, tma, s3
+// CHECK: [0x37,0x00,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x0, ttmp[10:11], s3
+// CHECK: [0x3d,0x00,0x98,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], s101
+// CHECK: [0x02,0x00,0x98,0xc0,0x65,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], flat_scratch_lo
+// CHECK: [0x02,0x00,0x98,0xc0,0x66,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], flat_scratch_hi
+// CHECK: [0x02,0x00,0x98,0xc0,0x67,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], vcc_lo
+// CHECK: [0x02,0x00,0x98,0xc0,0x6a,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], vcc_hi
+// CHECK: [0x02,0x00,0x98,0xc0,0x6b,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], tba_lo
+// CHECK: [0x02,0x00,0x98,0xc0,0x6c,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], tba_hi
+// CHECK: [0x02,0x00,0x98,0xc0,0x6d,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], tma_lo
+// CHECK: [0x02,0x00,0x98,0xc0,0x6e,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], tma_hi
+// CHECK: [0x02,0x00,0x98,0xc0,0x6f,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], ttmp11
+// CHECK: [0x02,0x00,0x98,0xc0,0x7b,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], m0
+// CHECK: [0x02,0x00,0x98,0xc0,0x7c,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], 0x7ffff
+// CHECK: [0x02,0x00,0x9a,0xc0,0xff,0xff,0x07,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], s3
+// CHECK: [0x04,0x00,0x9c,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x1, s[8:11], s3
+// CHECK: [0x44,0x00,0x9c,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x7, s[8:11], s3
+// CHECK: [0xc4,0x01,0x9c,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[12:15], s3
+// CHECK: [0x06,0x00,0x9c,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[96:99], s3
+// CHECK: [0x30,0x00,0x9c,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, ttmp[8:11], s3
+// CHECK: [0x3c,0x00,0x9c,0xc0,0x03,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], s101
+// CHECK: [0x04,0x00,0x9c,0xc0,0x65,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], flat_scratch_lo
+// CHECK: [0x04,0x00,0x9c,0xc0,0x66,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], flat_scratch_hi
+// CHECK: [0x04,0x00,0x9c,0xc0,0x67,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], vcc_lo
+// CHECK: [0x04,0x00,0x9c,0xc0,0x6a,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], vcc_hi
+// CHECK: [0x04,0x00,0x9c,0xc0,0x6b,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], tba_lo
+// CHECK: [0x04,0x00,0x9c,0xc0,0x6c,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], tba_hi
+// CHECK: [0x04,0x00,0x9c,0xc0,0x6d,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], tma_lo
+// CHECK: [0x04,0x00,0x9c,0xc0,0x6e,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], tma_hi
+// CHECK: [0x04,0x00,0x9c,0xc0,0x6f,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], ttmp11
+// CHECK: [0x04,0x00,0x9c,0xc0,0x7b,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], m0
+// CHECK: [0x04,0x00,0x9c,0xc0,0x7c,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], 0x7ffff
+// CHECK: [0x04,0x00,0x9e,0xc0,0xff,0xff,0x07,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx8_asm_sop1.s
new file mode 100644
index 0000000000000..f70a851239a43
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sop1.s
@@ -0,0 +1,4153 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+s_mov_b32 s5, s1
+// CHECK: [0x01,0x00,0x85,0xbe]
+
+s_mov_b32 s101, s1
+// CHECK: [0x01,0x00,0xe5,0xbe]
+
+s_mov_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x00,0xe6,0xbe]
+
+s_mov_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x00,0xe7,0xbe]
+
+s_mov_b32 vcc_lo, s1
+// CHECK: [0x01,0x00,0xea,0xbe]
+
+s_mov_b32 vcc_hi, s1
+// CHECK: [0x01,0x00,0xeb,0xbe]
+
+s_mov_b32 tba_lo, s1
+// CHECK: [0x01,0x00,0xec,0xbe]
+
+s_mov_b32 tba_hi, s1
+// CHECK: [0x01,0x00,0xed,0xbe]
+
+s_mov_b32 tma_lo, s1
+// CHECK: [0x01,0x00,0xee,0xbe]
+
+s_mov_b32 tma_hi, s1
+// CHECK: [0x01,0x00,0xef,0xbe]
+
+s_mov_b32 ttmp11, s1
+// CHECK: [0x01,0x00,0xfb,0xbe]
+
+s_mov_b32 m0, s1
+// CHECK: [0x01,0x00,0xfc,0xbe]
+
+s_mov_b32 exec_lo, s1
+// CHECK: [0x01,0x00,0xfe,0xbe]
+
+s_mov_b32 exec_hi, s1
+// CHECK: [0x01,0x00,0xff,0xbe]
+
+s_mov_b32 s5, s101
+// CHECK: [0x65,0x00,0x85,0xbe]
+
+s_mov_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x00,0x85,0xbe]
+
+s_mov_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x00,0x85,0xbe]
+
+s_mov_b32 s5, vcc_lo
+// CHECK: [0x6a,0x00,0x85,0xbe]
+
+s_mov_b32 s5, vcc_hi
+// CHECK: [0x6b,0x00,0x85,0xbe]
+
+s_mov_b32 s5, tba_lo
+// CHECK: [0x6c,0x00,0x85,0xbe]
+
+s_mov_b32 s5, tba_hi
+// CHECK: [0x6d,0x00,0x85,0xbe]
+
+s_mov_b32 s5, tma_lo
+// CHECK: [0x6e,0x00,0x85,0xbe]
+
+s_mov_b32 s5, tma_hi
+// CHECK: [0x6f,0x00,0x85,0xbe]
+
+s_mov_b32 s5, ttmp11
+// CHECK: [0x7b,0x00,0x85,0xbe]
+
+s_mov_b32 s5, m0
+// CHECK: [0x7c,0x00,0x85,0xbe]
+
+s_mov_b32 s5, exec_lo
+// CHECK: [0x7e,0x00,0x85,0xbe]
+
+s_mov_b32 s5, exec_hi
+// CHECK: [0x7f,0x00,0x85,0xbe]
+
+s_mov_b32 s5, 0
+// CHECK: [0x80,0x00,0x85,0xbe]
+
+s_mov_b32 s5, -1
+// CHECK: [0xc1,0x00,0x85,0xbe]
+
+s_mov_b32 s5, 0.5
+// CHECK: [0xf0,0x00,0x85,0xbe]
+
+s_mov_b32 s5, -4.0
+// CHECK: [0xf7,0x00,0x85,0xbe]
+
+s_mov_b32 s5, src_vccz
+// CHECK: [0xfb,0x00,0x85,0xbe]
+
+s_mov_b32 s5, src_execz
+// CHECK: [0xfc,0x00,0x85,0xbe]
+
+s_mov_b32 s5, src_scc
+// CHECK: [0xfd,0x00,0x85,0xbe]
+
+s_mov_b32 s5, 0xaf123456
+// CHECK: [0xff,0x00,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_mov_b32 s5, 0x3f717273
+// CHECK: [0xff,0x00,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_mov_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x01,0x8a,0xbe]
+
+s_mov_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x01,0x8c,0xbe]
+
+s_mov_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x01,0xe4,0xbe]
+
+s_mov_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x01,0xe6,0xbe]
+
+s_mov_b64 vcc, s[2:3]
+// CHECK: [0x02,0x01,0xea,0xbe]
+
+s_mov_b64 tba, s[2:3]
+// CHECK: [0x02,0x01,0xec,0xbe]
+
+s_mov_b64 tma, s[2:3]
+// CHECK: [0x02,0x01,0xee,0xbe]
+
+s_mov_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x01,0xfa,0xbe]
+
+s_mov_b64 exec, s[2:3]
+// CHECK: [0x02,0x01,0xfe,0xbe]
+
+s_mov_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], vcc
+// CHECK: [0x6a,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], tba
+// CHECK: [0x6c,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], tma
+// CHECK: [0x6e,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], exec
+// CHECK: [0x7e,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], 0
+// CHECK: [0x80,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], -1
+// CHECK: [0xc1,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x01,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_mov_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x01,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cmov_b32 s5, s1
+// CHECK: [0x01,0x02,0x85,0xbe]
+
+s_cmov_b32 s101, s1
+// CHECK: [0x01,0x02,0xe5,0xbe]
+
+s_cmov_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x02,0xe6,0xbe]
+
+s_cmov_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x02,0xe7,0xbe]
+
+s_cmov_b32 vcc_lo, s1
+// CHECK: [0x01,0x02,0xea,0xbe]
+
+s_cmov_b32 vcc_hi, s1
+// CHECK: [0x01,0x02,0xeb,0xbe]
+
+s_cmov_b32 tba_lo, s1
+// CHECK: [0x01,0x02,0xec,0xbe]
+
+s_cmov_b32 tba_hi, s1
+// CHECK: [0x01,0x02,0xed,0xbe]
+
+s_cmov_b32 tma_lo, s1
+// CHECK: [0x01,0x02,0xee,0xbe]
+
+s_cmov_b32 tma_hi, s1
+// CHECK: [0x01,0x02,0xef,0xbe]
+
+s_cmov_b32 ttmp11, s1
+// CHECK: [0x01,0x02,0xfb,0xbe]
+
+s_cmov_b32 m0, s1
+// CHECK: [0x01,0x02,0xfc,0xbe]
+
+s_cmov_b32 exec_lo, s1
+// CHECK: [0x01,0x02,0xfe,0xbe]
+
+s_cmov_b32 exec_hi, s1
+// CHECK: [0x01,0x02,0xff,0xbe]
+
+s_cmov_b32 s5, s101
+// CHECK: [0x65,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, vcc_lo
+// CHECK: [0x6a,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, vcc_hi
+// CHECK: [0x6b,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, tba_lo
+// CHECK: [0x6c,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, tba_hi
+// CHECK: [0x6d,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, tma_lo
+// CHECK: [0x6e,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, tma_hi
+// CHECK: [0x6f,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, ttmp11
+// CHECK: [0x7b,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, m0
+// CHECK: [0x7c,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, exec_lo
+// CHECK: [0x7e,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, exec_hi
+// CHECK: [0x7f,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, 0
+// CHECK: [0x80,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, -1
+// CHECK: [0xc1,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, 0.5
+// CHECK: [0xf0,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, -4.0
+// CHECK: [0xf7,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, src_vccz
+// CHECK: [0xfb,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, src_execz
+// CHECK: [0xfc,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, src_scc
+// CHECK: [0xfd,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, 0xaf123456
+// CHECK: [0xff,0x02,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_cmov_b32 s5, 0x3f717273
+// CHECK: [0xff,0x02,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cmov_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x03,0x8c,0xbe]
+
+s_cmov_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x03,0xe4,0xbe]
+
+s_cmov_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x03,0xe6,0xbe]
+
+s_cmov_b64 vcc, s[2:3]
+// CHECK: [0x02,0x03,0xea,0xbe]
+
+s_cmov_b64 tba, s[2:3]
+// CHECK: [0x02,0x03,0xec,0xbe]
+
+s_cmov_b64 tma, s[2:3]
+// CHECK: [0x02,0x03,0xee,0xbe]
+
+s_cmov_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x03,0xfa,0xbe]
+
+s_cmov_b64 exec, s[2:3]
+// CHECK: [0x02,0x03,0xfe,0xbe]
+
+s_cmov_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], vcc
+// CHECK: [0x6a,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], tba
+// CHECK: [0x6c,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], tma
+// CHECK: [0x6e,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], exec
+// CHECK: [0x7e,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], 0
+// CHECK: [0x80,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], -1
+// CHECK: [0xc1,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x03,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_cmov_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x03,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_not_b32 s5, s1
+// CHECK: [0x01,0x04,0x85,0xbe]
+
+s_not_b32 s101, s1
+// CHECK: [0x01,0x04,0xe5,0xbe]
+
+s_not_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x04,0xe6,0xbe]
+
+s_not_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x04,0xe7,0xbe]
+
+s_not_b32 vcc_lo, s1
+// CHECK: [0x01,0x04,0xea,0xbe]
+
+s_not_b32 vcc_hi, s1
+// CHECK: [0x01,0x04,0xeb,0xbe]
+
+s_not_b32 tba_lo, s1
+// CHECK: [0x01,0x04,0xec,0xbe]
+
+s_not_b32 tba_hi, s1
+// CHECK: [0x01,0x04,0xed,0xbe]
+
+s_not_b32 tma_lo, s1
+// CHECK: [0x01,0x04,0xee,0xbe]
+
+s_not_b32 tma_hi, s1
+// CHECK: [0x01,0x04,0xef,0xbe]
+
+s_not_b32 ttmp11, s1
+// CHECK: [0x01,0x04,0xfb,0xbe]
+
+s_not_b32 m0, s1
+// CHECK: [0x01,0x04,0xfc,0xbe]
+
+s_not_b32 exec_lo, s1
+// CHECK: [0x01,0x04,0xfe,0xbe]
+
+s_not_b32 exec_hi, s1
+// CHECK: [0x01,0x04,0xff,0xbe]
+
+s_not_b32 s5, s101
+// CHECK: [0x65,0x04,0x85,0xbe]
+
+s_not_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x04,0x85,0xbe]
+
+s_not_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x04,0x85,0xbe]
+
+s_not_b32 s5, vcc_lo
+// CHECK: [0x6a,0x04,0x85,0xbe]
+
+s_not_b32 s5, vcc_hi
+// CHECK: [0x6b,0x04,0x85,0xbe]
+
+s_not_b32 s5, tba_lo
+// CHECK: [0x6c,0x04,0x85,0xbe]
+
+s_not_b32 s5, tba_hi
+// CHECK: [0x6d,0x04,0x85,0xbe]
+
+s_not_b32 s5, tma_lo
+// CHECK: [0x6e,0x04,0x85,0xbe]
+
+s_not_b32 s5, tma_hi
+// CHECK: [0x6f,0x04,0x85,0xbe]
+
+s_not_b32 s5, ttmp11
+// CHECK: [0x7b,0x04,0x85,0xbe]
+
+s_not_b32 s5, m0
+// CHECK: [0x7c,0x04,0x85,0xbe]
+
+s_not_b32 s5, exec_lo
+// CHECK: [0x7e,0x04,0x85,0xbe]
+
+s_not_b32 s5, exec_hi
+// CHECK: [0x7f,0x04,0x85,0xbe]
+
+s_not_b32 s5, 0
+// CHECK: [0x80,0x04,0x85,0xbe]
+
+s_not_b32 s5, -1
+// CHECK: [0xc1,0x04,0x85,0xbe]
+
+s_not_b32 s5, 0.5
+// CHECK: [0xf0,0x04,0x85,0xbe]
+
+s_not_b32 s5, -4.0
+// CHECK: [0xf7,0x04,0x85,0xbe]
+
+s_not_b32 s5, src_vccz
+// CHECK: [0xfb,0x04,0x85,0xbe]
+
+s_not_b32 s5, src_execz
+// CHECK: [0xfc,0x04,0x85,0xbe]
+
+s_not_b32 s5, src_scc
+// CHECK: [0xfd,0x04,0x85,0xbe]
+
+s_not_b32 s5, 0xaf123456
+// CHECK: [0xff,0x04,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_not_b32 s5, 0x3f717273
+// CHECK: [0xff,0x04,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_not_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x05,0x8a,0xbe]
+
+s_not_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x05,0x8c,0xbe]
+
+s_not_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x05,0xe4,0xbe]
+
+s_not_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x05,0xe6,0xbe]
+
+s_not_b64 vcc, s[2:3]
+// CHECK: [0x02,0x05,0xea,0xbe]
+
+s_not_b64 tba, s[2:3]
+// CHECK: [0x02,0x05,0xec,0xbe]
+
+s_not_b64 tma, s[2:3]
+// CHECK: [0x02,0x05,0xee,0xbe]
+
+s_not_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x05,0xfa,0xbe]
+
+s_not_b64 exec, s[2:3]
+// CHECK: [0x02,0x05,0xfe,0xbe]
+
+s_not_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], vcc
+// CHECK: [0x6a,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], tba
+// CHECK: [0x6c,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], tma
+// CHECK: [0x6e,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], exec
+// CHECK: [0x7e,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], 0
+// CHECK: [0x80,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], -1
+// CHECK: [0xc1,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x05,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_not_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x05,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_wqm_b32 s5, s1
+// CHECK: [0x01,0x06,0x85,0xbe]
+
+s_wqm_b32 s101, s1
+// CHECK: [0x01,0x06,0xe5,0xbe]
+
+s_wqm_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x06,0xe6,0xbe]
+
+s_wqm_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x06,0xe7,0xbe]
+
+s_wqm_b32 vcc_lo, s1
+// CHECK: [0x01,0x06,0xea,0xbe]
+
+s_wqm_b32 vcc_hi, s1
+// CHECK: [0x01,0x06,0xeb,0xbe]
+
+s_wqm_b32 tba_lo, s1
+// CHECK: [0x01,0x06,0xec,0xbe]
+
+s_wqm_b32 tba_hi, s1
+// CHECK: [0x01,0x06,0xed,0xbe]
+
+s_wqm_b32 tma_lo, s1
+// CHECK: [0x01,0x06,0xee,0xbe]
+
+s_wqm_b32 tma_hi, s1
+// CHECK: [0x01,0x06,0xef,0xbe]
+
+s_wqm_b32 ttmp11, s1
+// CHECK: [0x01,0x06,0xfb,0xbe]
+
+s_wqm_b32 m0, s1
+// CHECK: [0x01,0x06,0xfc,0xbe]
+
+s_wqm_b32 exec_lo, s1
+// CHECK: [0x01,0x06,0xfe,0xbe]
+
+s_wqm_b32 exec_hi, s1
+// CHECK: [0x01,0x06,0xff,0xbe]
+
+s_wqm_b32 s5, s101
+// CHECK: [0x65,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, vcc_lo
+// CHECK: [0x6a,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, vcc_hi
+// CHECK: [0x6b,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, tba_lo
+// CHECK: [0x6c,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, tba_hi
+// CHECK: [0x6d,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, tma_lo
+// CHECK: [0x6e,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, tma_hi
+// CHECK: [0x6f,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, ttmp11
+// CHECK: [0x7b,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, m0
+// CHECK: [0x7c,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, exec_lo
+// CHECK: [0x7e,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, exec_hi
+// CHECK: [0x7f,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, 0
+// CHECK: [0x80,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, -1
+// CHECK: [0xc1,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, 0.5
+// CHECK: [0xf0,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, -4.0
+// CHECK: [0xf7,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, src_vccz
+// CHECK: [0xfb,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, src_execz
+// CHECK: [0xfc,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, src_scc
+// CHECK: [0xfd,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, 0xaf123456
+// CHECK: [0xff,0x06,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_wqm_b32 s5, 0x3f717273
+// CHECK: [0xff,0x06,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_wqm_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x07,0x8c,0xbe]
+
+s_wqm_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x07,0xe4,0xbe]
+
+s_wqm_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x07,0xe6,0xbe]
+
+s_wqm_b64 vcc, s[2:3]
+// CHECK: [0x02,0x07,0xea,0xbe]
+
+s_wqm_b64 tba, s[2:3]
+// CHECK: [0x02,0x07,0xec,0xbe]
+
+s_wqm_b64 tma, s[2:3]
+// CHECK: [0x02,0x07,0xee,0xbe]
+
+s_wqm_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x07,0xfa,0xbe]
+
+s_wqm_b64 exec, s[2:3]
+// CHECK: [0x02,0x07,0xfe,0xbe]
+
+s_wqm_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], vcc
+// CHECK: [0x6a,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], tba
+// CHECK: [0x6c,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], tma
+// CHECK: [0x6e,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], exec
+// CHECK: [0x7e,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], 0
+// CHECK: [0x80,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], -1
+// CHECK: [0xc1,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x07,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_wqm_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x07,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_brev_b32 s5, s1
+// CHECK: [0x01,0x08,0x85,0xbe]
+
+s_brev_b32 s101, s1
+// CHECK: [0x01,0x08,0xe5,0xbe]
+
+s_brev_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x08,0xe6,0xbe]
+
+s_brev_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x08,0xe7,0xbe]
+
+s_brev_b32 vcc_lo, s1
+// CHECK: [0x01,0x08,0xea,0xbe]
+
+s_brev_b32 vcc_hi, s1
+// CHECK: [0x01,0x08,0xeb,0xbe]
+
+s_brev_b32 tba_lo, s1
+// CHECK: [0x01,0x08,0xec,0xbe]
+
+s_brev_b32 tba_hi, s1
+// CHECK: [0x01,0x08,0xed,0xbe]
+
+s_brev_b32 tma_lo, s1
+// CHECK: [0x01,0x08,0xee,0xbe]
+
+s_brev_b32 tma_hi, s1
+// CHECK: [0x01,0x08,0xef,0xbe]
+
+s_brev_b32 ttmp11, s1
+// CHECK: [0x01,0x08,0xfb,0xbe]
+
+s_brev_b32 m0, s1
+// CHECK: [0x01,0x08,0xfc,0xbe]
+
+s_brev_b32 exec_lo, s1
+// CHECK: [0x01,0x08,0xfe,0xbe]
+
+s_brev_b32 exec_hi, s1
+// CHECK: [0x01,0x08,0xff,0xbe]
+
+s_brev_b32 s5, s101
+// CHECK: [0x65,0x08,0x85,0xbe]
+
+s_brev_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x08,0x85,0xbe]
+
+s_brev_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x08,0x85,0xbe]
+
+s_brev_b32 s5, vcc_lo
+// CHECK: [0x6a,0x08,0x85,0xbe]
+
+s_brev_b32 s5, vcc_hi
+// CHECK: [0x6b,0x08,0x85,0xbe]
+
+s_brev_b32 s5, tba_lo
+// CHECK: [0x6c,0x08,0x85,0xbe]
+
+s_brev_b32 s5, tba_hi
+// CHECK: [0x6d,0x08,0x85,0xbe]
+
+s_brev_b32 s5, tma_lo
+// CHECK: [0x6e,0x08,0x85,0xbe]
+
+s_brev_b32 s5, tma_hi
+// CHECK: [0x6f,0x08,0x85,0xbe]
+
+s_brev_b32 s5, ttmp11
+// CHECK: [0x7b,0x08,0x85,0xbe]
+
+s_brev_b32 s5, m0
+// CHECK: [0x7c,0x08,0x85,0xbe]
+
+s_brev_b32 s5, exec_lo
+// CHECK: [0x7e,0x08,0x85,0xbe]
+
+s_brev_b32 s5, exec_hi
+// CHECK: [0x7f,0x08,0x85,0xbe]
+
+s_brev_b32 s5, 0
+// CHECK: [0x80,0x08,0x85,0xbe]
+
+s_brev_b32 s5, -1
+// CHECK: [0xc1,0x08,0x85,0xbe]
+
+s_brev_b32 s5, 0.5
+// CHECK: [0xf0,0x08,0x85,0xbe]
+
+s_brev_b32 s5, -4.0
+// CHECK: [0xf7,0x08,0x85,0xbe]
+
+s_brev_b32 s5, src_vccz
+// CHECK: [0xfb,0x08,0x85,0xbe]
+
+s_brev_b32 s5, src_execz
+// CHECK: [0xfc,0x08,0x85,0xbe]
+
+s_brev_b32 s5, src_scc
+// CHECK: [0xfd,0x08,0x85,0xbe]
+
+s_brev_b32 s5, 0xaf123456
+// CHECK: [0xff,0x08,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_brev_b32 s5, 0x3f717273
+// CHECK: [0xff,0x08,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_brev_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x09,0x8a,0xbe]
+
+s_brev_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x09,0x8c,0xbe]
+
+s_brev_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x09,0xe4,0xbe]
+
+s_brev_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x09,0xe6,0xbe]
+
+s_brev_b64 vcc, s[2:3]
+// CHECK: [0x02,0x09,0xea,0xbe]
+
+s_brev_b64 tba, s[2:3]
+// CHECK: [0x02,0x09,0xec,0xbe]
+
+s_brev_b64 tma, s[2:3]
+// CHECK: [0x02,0x09,0xee,0xbe]
+
+s_brev_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x09,0xfa,0xbe]
+
+s_brev_b64 exec, s[2:3]
+// CHECK: [0x02,0x09,0xfe,0xbe]
+
+s_brev_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], vcc
+// CHECK: [0x6a,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], tba
+// CHECK: [0x6c,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], tma
+// CHECK: [0x6e,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], exec
+// CHECK: [0x7e,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], 0
+// CHECK: [0x80,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], -1
+// CHECK: [0xc1,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x09,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_brev_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x09,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt0_i32_b32 s5, s1
+// CHECK: [0x01,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s101, s1
+// CHECK: [0x01,0x0a,0xe5,0xbe]
+
+s_bcnt0_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x0a,0xe6,0xbe]
+
+s_bcnt0_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x0a,0xe7,0xbe]
+
+s_bcnt0_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x0a,0xea,0xbe]
+
+s_bcnt0_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x0a,0xeb,0xbe]
+
+s_bcnt0_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x0a,0xec,0xbe]
+
+s_bcnt0_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x0a,0xed,0xbe]
+
+s_bcnt0_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x0a,0xee,0xbe]
+
+s_bcnt0_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x0a,0xef,0xbe]
+
+s_bcnt0_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x0a,0xfb,0xbe]
+
+s_bcnt0_i32_b32 m0, s1
+// CHECK: [0x01,0x0a,0xfc,0xbe]
+
+s_bcnt0_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x0a,0xfe,0xbe]
+
+s_bcnt0_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x0a,0xff,0xbe]
+
+s_bcnt0_i32_b32 s5, s101
+// CHECK: [0x65,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, m0
+// CHECK: [0x7c,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, 0
+// CHECK: [0x80,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, -1
+// CHECK: [0xc1,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x0a,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt0_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x0a,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt0_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x0b,0xe5,0xbe]
+
+s_bcnt0_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x0b,0xe6,0xbe]
+
+s_bcnt0_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x0b,0xe7,0xbe]
+
+s_bcnt0_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x0b,0xea,0xbe]
+
+s_bcnt0_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x0b,0xeb,0xbe]
+
+s_bcnt0_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x0b,0xec,0xbe]
+
+s_bcnt0_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x0b,0xed,0xbe]
+
+s_bcnt0_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x0b,0xee,0xbe]
+
+s_bcnt0_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x0b,0xef,0xbe]
+
+s_bcnt0_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x0b,0xfb,0xbe]
+
+s_bcnt0_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x0b,0xfc,0xbe]
+
+s_bcnt0_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x0b,0xfe,0xbe]
+
+s_bcnt0_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x0b,0xff,0xbe]
+
+s_bcnt0_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, vcc
+// CHECK: [0x6a,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, tba
+// CHECK: [0x6c,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, tma
+// CHECK: [0x6e,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, exec
+// CHECK: [0x7e,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, 0
+// CHECK: [0x80,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, -1
+// CHECK: [0xc1,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x0b,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt0_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x0b,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt1_i32_b32 s5, s1
+// CHECK: [0x01,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s101, s1
+// CHECK: [0x01,0x0c,0xe5,0xbe]
+
+s_bcnt1_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x0c,0xe6,0xbe]
+
+s_bcnt1_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x0c,0xe7,0xbe]
+
+s_bcnt1_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x0c,0xea,0xbe]
+
+s_bcnt1_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x0c,0xeb,0xbe]
+
+s_bcnt1_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x0c,0xec,0xbe]
+
+s_bcnt1_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x0c,0xed,0xbe]
+
+s_bcnt1_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x0c,0xee,0xbe]
+
+s_bcnt1_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x0c,0xef,0xbe]
+
+s_bcnt1_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x0c,0xfb,0xbe]
+
+s_bcnt1_i32_b32 m0, s1
+// CHECK: [0x01,0x0c,0xfc,0xbe]
+
+s_bcnt1_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x0c,0xfe,0xbe]
+
+s_bcnt1_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x0c,0xff,0xbe]
+
+s_bcnt1_i32_b32 s5, s101
+// CHECK: [0x65,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, m0
+// CHECK: [0x7c,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, 0
+// CHECK: [0x80,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, -1
+// CHECK: [0xc1,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x0c,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt1_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x0c,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt1_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x0d,0xe5,0xbe]
+
+s_bcnt1_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x0d,0xe6,0xbe]
+
+s_bcnt1_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x0d,0xe7,0xbe]
+
+s_bcnt1_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x0d,0xea,0xbe]
+
+s_bcnt1_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x0d,0xeb,0xbe]
+
+s_bcnt1_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x0d,0xec,0xbe]
+
+s_bcnt1_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x0d,0xed,0xbe]
+
+s_bcnt1_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x0d,0xee,0xbe]
+
+s_bcnt1_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x0d,0xef,0xbe]
+
+s_bcnt1_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x0d,0xfb,0xbe]
+
+s_bcnt1_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x0d,0xfc,0xbe]
+
+s_bcnt1_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x0d,0xfe,0xbe]
+
+s_bcnt1_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x0d,0xff,0xbe]
+
+s_bcnt1_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, vcc
+// CHECK: [0x6a,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, tba
+// CHECK: [0x6c,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, tma
+// CHECK: [0x6e,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, exec
+// CHECK: [0x7e,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, 0
+// CHECK: [0x80,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, -1
+// CHECK: [0xc1,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x0d,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt1_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x0d,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff0_i32_b32 s5, s1
+// CHECK: [0x01,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s101, s1
+// CHECK: [0x01,0x0e,0xe5,0xbe]
+
+s_ff0_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x0e,0xe6,0xbe]
+
+s_ff0_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x0e,0xe7,0xbe]
+
+s_ff0_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x0e,0xea,0xbe]
+
+s_ff0_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x0e,0xeb,0xbe]
+
+s_ff0_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x0e,0xec,0xbe]
+
+s_ff0_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x0e,0xed,0xbe]
+
+s_ff0_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x0e,0xee,0xbe]
+
+s_ff0_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x0e,0xef,0xbe]
+
+s_ff0_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x0e,0xfb,0xbe]
+
+s_ff0_i32_b32 m0, s1
+// CHECK: [0x01,0x0e,0xfc,0xbe]
+
+s_ff0_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x0e,0xfe,0xbe]
+
+s_ff0_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x0e,0xff,0xbe]
+
+s_ff0_i32_b32 s5, s101
+// CHECK: [0x65,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, m0
+// CHECK: [0x7c,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, 0
+// CHECK: [0x80,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, -1
+// CHECK: [0xc1,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x0e,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff0_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x0e,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff0_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x0f,0xe5,0xbe]
+
+s_ff0_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x0f,0xe6,0xbe]
+
+s_ff0_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x0f,0xe7,0xbe]
+
+s_ff0_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x0f,0xea,0xbe]
+
+s_ff0_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x0f,0xeb,0xbe]
+
+s_ff0_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x0f,0xec,0xbe]
+
+s_ff0_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x0f,0xed,0xbe]
+
+s_ff0_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x0f,0xee,0xbe]
+
+s_ff0_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x0f,0xef,0xbe]
+
+s_ff0_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x0f,0xfb,0xbe]
+
+s_ff0_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x0f,0xfc,0xbe]
+
+s_ff0_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x0f,0xfe,0xbe]
+
+s_ff0_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x0f,0xff,0xbe]
+
+s_ff0_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, vcc
+// CHECK: [0x6a,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, tba
+// CHECK: [0x6c,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, tma
+// CHECK: [0x6e,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, exec
+// CHECK: [0x7e,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, 0
+// CHECK: [0x80,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, -1
+// CHECK: [0xc1,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x0f,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff0_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x0f,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff1_i32_b32 s5, s1
+// CHECK: [0x01,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s101, s1
+// CHECK: [0x01,0x10,0xe5,0xbe]
+
+s_ff1_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x10,0xe6,0xbe]
+
+s_ff1_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x10,0xe7,0xbe]
+
+s_ff1_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x10,0xea,0xbe]
+
+s_ff1_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x10,0xeb,0xbe]
+
+s_ff1_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x10,0xec,0xbe]
+
+s_ff1_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x10,0xed,0xbe]
+
+s_ff1_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x10,0xee,0xbe]
+
+s_ff1_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x10,0xef,0xbe]
+
+s_ff1_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x10,0xfb,0xbe]
+
+s_ff1_i32_b32 m0, s1
+// CHECK: [0x01,0x10,0xfc,0xbe]
+
+s_ff1_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x10,0xfe,0xbe]
+
+s_ff1_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x10,0xff,0xbe]
+
+s_ff1_i32_b32 s5, s101
+// CHECK: [0x65,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, m0
+// CHECK: [0x7c,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, 0
+// CHECK: [0x80,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, -1
+// CHECK: [0xc1,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x10,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff1_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x10,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff1_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x11,0xe5,0xbe]
+
+s_ff1_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x11,0xe6,0xbe]
+
+s_ff1_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x11,0xe7,0xbe]
+
+s_ff1_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x11,0xea,0xbe]
+
+s_ff1_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x11,0xeb,0xbe]
+
+s_ff1_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x11,0xec,0xbe]
+
+s_ff1_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x11,0xed,0xbe]
+
+s_ff1_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x11,0xee,0xbe]
+
+s_ff1_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x11,0xef,0xbe]
+
+s_ff1_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x11,0xfb,0xbe]
+
+s_ff1_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x11,0xfc,0xbe]
+
+s_ff1_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x11,0xfe,0xbe]
+
+s_ff1_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x11,0xff,0xbe]
+
+s_ff1_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, vcc
+// CHECK: [0x6a,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, tba
+// CHECK: [0x6c,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, tma
+// CHECK: [0x6e,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, exec
+// CHECK: [0x7e,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, 0
+// CHECK: [0x80,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, -1
+// CHECK: [0xc1,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x11,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff1_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x11,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_b32 s5, s1
+// CHECK: [0x01,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s101, s1
+// CHECK: [0x01,0x12,0xe5,0xbe]
+
+s_flbit_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x12,0xe6,0xbe]
+
+s_flbit_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x12,0xe7,0xbe]
+
+s_flbit_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x12,0xea,0xbe]
+
+s_flbit_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x12,0xeb,0xbe]
+
+s_flbit_i32_b32 tba_lo, s1
+// CHECK: [0x01,0x12,0xec,0xbe]
+
+s_flbit_i32_b32 tba_hi, s1
+// CHECK: [0x01,0x12,0xed,0xbe]
+
+s_flbit_i32_b32 tma_lo, s1
+// CHECK: [0x01,0x12,0xee,0xbe]
+
+s_flbit_i32_b32 tma_hi, s1
+// CHECK: [0x01,0x12,0xef,0xbe]
+
+s_flbit_i32_b32 ttmp11, s1
+// CHECK: [0x01,0x12,0xfb,0xbe]
+
+s_flbit_i32_b32 m0, s1
+// CHECK: [0x01,0x12,0xfc,0xbe]
+
+s_flbit_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x12,0xfe,0xbe]
+
+s_flbit_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x12,0xff,0xbe]
+
+s_flbit_i32_b32 s5, s101
+// CHECK: [0x65,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, tba_lo
+// CHECK: [0x6c,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, tba_hi
+// CHECK: [0x6d,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, tma_lo
+// CHECK: [0x6e,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, tma_hi
+// CHECK: [0x6f,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, ttmp11
+// CHECK: [0x7b,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, m0
+// CHECK: [0x7c,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, 0
+// CHECK: [0x80,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, -1
+// CHECK: [0xc1,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x12,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x12,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x13,0xe5,0xbe]
+
+s_flbit_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x13,0xe6,0xbe]
+
+s_flbit_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x13,0xe7,0xbe]
+
+s_flbit_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x13,0xea,0xbe]
+
+s_flbit_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x13,0xeb,0xbe]
+
+s_flbit_i32_b64 tba_lo, s[2:3]
+// CHECK: [0x02,0x13,0xec,0xbe]
+
+s_flbit_i32_b64 tba_hi, s[2:3]
+// CHECK: [0x02,0x13,0xed,0xbe]
+
+s_flbit_i32_b64 tma_lo, s[2:3]
+// CHECK: [0x02,0x13,0xee,0xbe]
+
+s_flbit_i32_b64 tma_hi, s[2:3]
+// CHECK: [0x02,0x13,0xef,0xbe]
+
+s_flbit_i32_b64 ttmp11, s[2:3]
+// CHECK: [0x02,0x13,0xfb,0xbe]
+
+s_flbit_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x13,0xfc,0xbe]
+
+s_flbit_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x13,0xfe,0xbe]
+
+s_flbit_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x13,0xff,0xbe]
+
+s_flbit_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, vcc
+// CHECK: [0x6a,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, tba
+// CHECK: [0x6c,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, tma
+// CHECK: [0x6e,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, exec
+// CHECK: [0x7e,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, 0
+// CHECK: [0x80,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, -1
+// CHECK: [0xc1,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x13,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x13,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32 s5, s1
+// CHECK: [0x01,0x14,0x85,0xbe]
+
+s_flbit_i32 s101, s1
+// CHECK: [0x01,0x14,0xe5,0xbe]
+
+s_flbit_i32 flat_scratch_lo, s1
+// CHECK: [0x01,0x14,0xe6,0xbe]
+
+s_flbit_i32 flat_scratch_hi, s1
+// CHECK: [0x01,0x14,0xe7,0xbe]
+
+s_flbit_i32 vcc_lo, s1
+// CHECK: [0x01,0x14,0xea,0xbe]
+
+s_flbit_i32 vcc_hi, s1
+// CHECK: [0x01,0x14,0xeb,0xbe]
+
+s_flbit_i32 tba_lo, s1
+// CHECK: [0x01,0x14,0xec,0xbe]
+
+s_flbit_i32 tba_hi, s1
+// CHECK: [0x01,0x14,0xed,0xbe]
+
+s_flbit_i32 tma_lo, s1
+// CHECK: [0x01,0x14,0xee,0xbe]
+
+s_flbit_i32 tma_hi, s1
+// CHECK: [0x01,0x14,0xef,0xbe]
+
+s_flbit_i32 ttmp11, s1
+// CHECK: [0x01,0x14,0xfb,0xbe]
+
+s_flbit_i32 m0, s1
+// CHECK: [0x01,0x14,0xfc,0xbe]
+
+s_flbit_i32 exec_lo, s1
+// CHECK: [0x01,0x14,0xfe,0xbe]
+
+s_flbit_i32 exec_hi, s1
+// CHECK: [0x01,0x14,0xff,0xbe]
+
+s_flbit_i32 s5, s101
+// CHECK: [0x65,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, flat_scratch_lo
+// CHECK: [0x66,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, flat_scratch_hi
+// CHECK: [0x67,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, vcc_lo
+// CHECK: [0x6a,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, vcc_hi
+// CHECK: [0x6b,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, tba_lo
+// CHECK: [0x6c,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, tba_hi
+// CHECK: [0x6d,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, tma_lo
+// CHECK: [0x6e,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, tma_hi
+// CHECK: [0x6f,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, ttmp11
+// CHECK: [0x7b,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, m0
+// CHECK: [0x7c,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, exec_lo
+// CHECK: [0x7e,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, exec_hi
+// CHECK: [0x7f,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, 0
+// CHECK: [0x80,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, -1
+// CHECK: [0xc1,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, 0.5
+// CHECK: [0xf0,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, -4.0
+// CHECK: [0xf7,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, src_vccz
+// CHECK: [0xfb,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, src_execz
+// CHECK: [0xfc,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, src_scc
+// CHECK: [0xfd,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, 0xaf123456
+// CHECK: [0xff,0x14,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32 s5, 0x3f717273
+// CHECK: [0xff,0x14,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_i64 s5, s[2:3]
+// CHECK: [0x02,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s101, s[2:3]
+// CHECK: [0x02,0x15,0xe5,0xbe]
+
+s_flbit_i32_i64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x15,0xe6,0xbe]
+
+s_flbit_i32_i64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x15,0xe7,0xbe]
+
+s_flbit_i32_i64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x15,0xea,0xbe]
+
+s_flbit_i32_i64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x15,0xeb,0xbe]
+
+s_flbit_i32_i64 tba_lo, s[2:3]
+// CHECK: [0x02,0x15,0xec,0xbe]
+
+s_flbit_i32_i64 tba_hi, s[2:3]
+// CHECK: [0x02,0x15,0xed,0xbe]
+
+s_flbit_i32_i64 tma_lo, s[2:3]
+// CHECK: [0x02,0x15,0xee,0xbe]
+
+s_flbit_i32_i64 tma_hi, s[2:3]
+// CHECK: [0x02,0x15,0xef,0xbe]
+
+s_flbit_i32_i64 ttmp11, s[2:3]
+// CHECK: [0x02,0x15,0xfb,0xbe]
+
+s_flbit_i32_i64 m0, s[2:3]
+// CHECK: [0x02,0x15,0xfc,0xbe]
+
+s_flbit_i32_i64 exec_lo, s[2:3]
+// CHECK: [0x02,0x15,0xfe,0xbe]
+
+s_flbit_i32_i64 exec_hi, s[2:3]
+// CHECK: [0x02,0x15,0xff,0xbe]
+
+s_flbit_i32_i64 s5, s[4:5]
+// CHECK: [0x04,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, s[100:101]
+// CHECK: [0x64,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, flat_scratch
+// CHECK: [0x66,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, vcc
+// CHECK: [0x6a,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, tba
+// CHECK: [0x6c,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, tma
+// CHECK: [0x6e,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, ttmp[10:11]
+// CHECK: [0x7a,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, exec
+// CHECK: [0x7e,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, 0
+// CHECK: [0x80,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, -1
+// CHECK: [0xc1,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, 0.5
+// CHECK: [0xf0,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, -4.0
+// CHECK: [0xf7,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, src_vccz
+// CHECK: [0xfb,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, src_execz
+// CHECK: [0xfc,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, src_scc
+// CHECK: [0xfd,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, 0xaf123456
+// CHECK: [0xff,0x15,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_i64 s5, 0x3f717273
+// CHECK: [0xff,0x15,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_sext_i32_i8 s5, s1
+// CHECK: [0x01,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s101, s1
+// CHECK: [0x01,0x16,0xe5,0xbe]
+
+s_sext_i32_i8 flat_scratch_lo, s1
+// CHECK: [0x01,0x16,0xe6,0xbe]
+
+s_sext_i32_i8 flat_scratch_hi, s1
+// CHECK: [0x01,0x16,0xe7,0xbe]
+
+s_sext_i32_i8 vcc_lo, s1
+// CHECK: [0x01,0x16,0xea,0xbe]
+
+s_sext_i32_i8 vcc_hi, s1
+// CHECK: [0x01,0x16,0xeb,0xbe]
+
+s_sext_i32_i8 tba_lo, s1
+// CHECK: [0x01,0x16,0xec,0xbe]
+
+s_sext_i32_i8 tba_hi, s1
+// CHECK: [0x01,0x16,0xed,0xbe]
+
+s_sext_i32_i8 tma_lo, s1
+// CHECK: [0x01,0x16,0xee,0xbe]
+
+s_sext_i32_i8 tma_hi, s1
+// CHECK: [0x01,0x16,0xef,0xbe]
+
+s_sext_i32_i8 ttmp11, s1
+// CHECK: [0x01,0x16,0xfb,0xbe]
+
+s_sext_i32_i8 m0, s1
+// CHECK: [0x01,0x16,0xfc,0xbe]
+
+s_sext_i32_i8 exec_lo, s1
+// CHECK: [0x01,0x16,0xfe,0xbe]
+
+s_sext_i32_i8 exec_hi, s1
+// CHECK: [0x01,0x16,0xff,0xbe]
+
+s_sext_i32_i8 s5, s101
+// CHECK: [0x65,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, flat_scratch_lo
+// CHECK: [0x66,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, flat_scratch_hi
+// CHECK: [0x67,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, vcc_lo
+// CHECK: [0x6a,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, vcc_hi
+// CHECK: [0x6b,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, tba_lo
+// CHECK: [0x6c,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, tba_hi
+// CHECK: [0x6d,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, tma_lo
+// CHECK: [0x6e,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, tma_hi
+// CHECK: [0x6f,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, ttmp11
+// CHECK: [0x7b,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, m0
+// CHECK: [0x7c,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, exec_lo
+// CHECK: [0x7e,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, exec_hi
+// CHECK: [0x7f,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, 0
+// CHECK: [0x80,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, -1
+// CHECK: [0xc1,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, 0.5
+// CHECK: [0xf0,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, -4.0
+// CHECK: [0xf7,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, src_vccz
+// CHECK: [0xfb,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, src_execz
+// CHECK: [0xfc,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, src_scc
+// CHECK: [0xfd,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, 0x71
+// CHECK: [0xff,0x16,0x85,0xbe,0x71,0x00,0x00,0x00]
+
+s_sext_i32_i8 s5, 0xf0
+// CHECK: [0xff,0x16,0x85,0xbe,0xf0,0x00,0x00,0x00]
+
+s_sext_i32_i16 s5, s1
+// CHECK: [0x01,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s101, s1
+// CHECK: [0x01,0x17,0xe5,0xbe]
+
+s_sext_i32_i16 flat_scratch_lo, s1
+// CHECK: [0x01,0x17,0xe6,0xbe]
+
+s_sext_i32_i16 flat_scratch_hi, s1
+// CHECK: [0x01,0x17,0xe7,0xbe]
+
+s_sext_i32_i16 vcc_lo, s1
+// CHECK: [0x01,0x17,0xea,0xbe]
+
+s_sext_i32_i16 vcc_hi, s1
+// CHECK: [0x01,0x17,0xeb,0xbe]
+
+s_sext_i32_i16 tba_lo, s1
+// CHECK: [0x01,0x17,0xec,0xbe]
+
+s_sext_i32_i16 tba_hi, s1
+// CHECK: [0x01,0x17,0xed,0xbe]
+
+s_sext_i32_i16 tma_lo, s1
+// CHECK: [0x01,0x17,0xee,0xbe]
+
+s_sext_i32_i16 tma_hi, s1
+// CHECK: [0x01,0x17,0xef,0xbe]
+
+s_sext_i32_i16 ttmp11, s1
+// CHECK: [0x01,0x17,0xfb,0xbe]
+
+s_sext_i32_i16 m0, s1
+// CHECK: [0x01,0x17,0xfc,0xbe]
+
+s_sext_i32_i16 exec_lo, s1
+// CHECK: [0x01,0x17,0xfe,0xbe]
+
+s_sext_i32_i16 exec_hi, s1
+// CHECK: [0x01,0x17,0xff,0xbe]
+
+s_sext_i32_i16 s5, s101
+// CHECK: [0x65,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, flat_scratch_lo
+// CHECK: [0x66,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, flat_scratch_hi
+// CHECK: [0x67,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, vcc_lo
+// CHECK: [0x6a,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, vcc_hi
+// CHECK: [0x6b,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, tba_lo
+// CHECK: [0x6c,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, tba_hi
+// CHECK: [0x6d,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, tma_lo
+// CHECK: [0x6e,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, tma_hi
+// CHECK: [0x6f,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, ttmp11
+// CHECK: [0x7b,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, m0
+// CHECK: [0x7c,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, exec_lo
+// CHECK: [0x7e,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, exec_hi
+// CHECK: [0x7f,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, 0
+// CHECK: [0x80,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, -1
+// CHECK: [0xc1,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, 0.5
+// CHECK: [0xf0,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, -4.0
+// CHECK: [0xf7,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, src_vccz
+// CHECK: [0xfb,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, src_execz
+// CHECK: [0xfc,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, src_scc
+// CHECK: [0xfd,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, 0xfe0b
+// CHECK: [0xff,0x17,0x85,0xbe,0x0b,0xfe,0x00,0x00]
+
+s_sext_i32_i16 s5, 0x3456
+// CHECK: [0xff,0x17,0x85,0xbe,0x56,0x34,0x00,0x00]
+
+s_bitset0_b32 s5, s1
+// CHECK: [0x01,0x18,0x85,0xbe]
+
+s_bitset0_b32 s101, s1
+// CHECK: [0x01,0x18,0xe5,0xbe]
+
+s_bitset0_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x18,0xe6,0xbe]
+
+s_bitset0_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x18,0xe7,0xbe]
+
+s_bitset0_b32 vcc_lo, s1
+// CHECK: [0x01,0x18,0xea,0xbe]
+
+s_bitset0_b32 vcc_hi, s1
+// CHECK: [0x01,0x18,0xeb,0xbe]
+
+s_bitset0_b32 tba_lo, s1
+// CHECK: [0x01,0x18,0xec,0xbe]
+
+s_bitset0_b32 tba_hi, s1
+// CHECK: [0x01,0x18,0xed,0xbe]
+
+s_bitset0_b32 tma_lo, s1
+// CHECK: [0x01,0x18,0xee,0xbe]
+
+s_bitset0_b32 tma_hi, s1
+// CHECK: [0x01,0x18,0xef,0xbe]
+
+s_bitset0_b32 ttmp11, s1
+// CHECK: [0x01,0x18,0xfb,0xbe]
+
+s_bitset0_b32 m0, s1
+// CHECK: [0x01,0x18,0xfc,0xbe]
+
+s_bitset0_b32 exec_lo, s1
+// CHECK: [0x01,0x18,0xfe,0xbe]
+
+s_bitset0_b32 exec_hi, s1
+// CHECK: [0x01,0x18,0xff,0xbe]
+
+s_bitset0_b32 s5, s101
+// CHECK: [0x65,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, vcc_lo
+// CHECK: [0x6a,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, vcc_hi
+// CHECK: [0x6b,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, tba_lo
+// CHECK: [0x6c,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, tba_hi
+// CHECK: [0x6d,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, tma_lo
+// CHECK: [0x6e,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, tma_hi
+// CHECK: [0x6f,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, ttmp11
+// CHECK: [0x7b,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, m0
+// CHECK: [0x7c,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, exec_lo
+// CHECK: [0x7e,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, exec_hi
+// CHECK: [0x7f,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, 0
+// CHECK: [0x80,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, -1
+// CHECK: [0xc1,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, 0.5
+// CHECK: [0xf0,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, -4.0
+// CHECK: [0xf7,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, src_vccz
+// CHECK: [0xfb,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, src_execz
+// CHECK: [0xfc,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, src_scc
+// CHECK: [0xfd,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, 0xaf123456
+// CHECK: [0xff,0x18,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset0_b32 s5, 0x3f717273
+// CHECK: [0xff,0x18,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset0_b64 s[10:11], s1
+// CHECK: [0x01,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[12:13], s1
+// CHECK: [0x01,0x19,0x8c,0xbe]
+
+s_bitset0_b64 s[100:101], s1
+// CHECK: [0x01,0x19,0xe4,0xbe]
+
+s_bitset0_b64 flat_scratch, s1
+// CHECK: [0x01,0x19,0xe6,0xbe]
+
+s_bitset0_b64 vcc, s1
+// CHECK: [0x01,0x19,0xea,0xbe]
+
+s_bitset0_b64 tba, s1
+// CHECK: [0x01,0x19,0xec,0xbe]
+
+s_bitset0_b64 tma, s1
+// CHECK: [0x01,0x19,0xee,0xbe]
+
+s_bitset0_b64 ttmp[10:11], s1
+// CHECK: [0x01,0x19,0xfa,0xbe]
+
+s_bitset0_b64 exec, s1
+// CHECK: [0x01,0x19,0xfe,0xbe]
+
+s_bitset0_b64 s[10:11], s101
+// CHECK: [0x65,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], flat_scratch_lo
+// CHECK: [0x66,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], flat_scratch_hi
+// CHECK: [0x67,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], vcc_lo
+// CHECK: [0x6a,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], vcc_hi
+// CHECK: [0x6b,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], tba_lo
+// CHECK: [0x6c,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], tba_hi
+// CHECK: [0x6d,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], tma_lo
+// CHECK: [0x6e,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], tma_hi
+// CHECK: [0x6f,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], ttmp11
+// CHECK: [0x7b,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], m0
+// CHECK: [0x7c,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], exec_lo
+// CHECK: [0x7e,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], exec_hi
+// CHECK: [0x7f,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], 0
+// CHECK: [0x80,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], -1
+// CHECK: [0xc1,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x19,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset0_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x19,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset1_b32 s5, s1
+// CHECK: [0x01,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s101, s1
+// CHECK: [0x01,0x1a,0xe5,0xbe]
+
+s_bitset1_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x1a,0xe6,0xbe]
+
+s_bitset1_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x1a,0xe7,0xbe]
+
+s_bitset1_b32 vcc_lo, s1
+// CHECK: [0x01,0x1a,0xea,0xbe]
+
+s_bitset1_b32 vcc_hi, s1
+// CHECK: [0x01,0x1a,0xeb,0xbe]
+
+s_bitset1_b32 tba_lo, s1
+// CHECK: [0x01,0x1a,0xec,0xbe]
+
+s_bitset1_b32 tba_hi, s1
+// CHECK: [0x01,0x1a,0xed,0xbe]
+
+s_bitset1_b32 tma_lo, s1
+// CHECK: [0x01,0x1a,0xee,0xbe]
+
+s_bitset1_b32 tma_hi, s1
+// CHECK: [0x01,0x1a,0xef,0xbe]
+
+s_bitset1_b32 ttmp11, s1
+// CHECK: [0x01,0x1a,0xfb,0xbe]
+
+s_bitset1_b32 m0, s1
+// CHECK: [0x01,0x1a,0xfc,0xbe]
+
+s_bitset1_b32 exec_lo, s1
+// CHECK: [0x01,0x1a,0xfe,0xbe]
+
+s_bitset1_b32 exec_hi, s1
+// CHECK: [0x01,0x1a,0xff,0xbe]
+
+s_bitset1_b32 s5, s101
+// CHECK: [0x65,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, vcc_lo
+// CHECK: [0x6a,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, vcc_hi
+// CHECK: [0x6b,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, tba_lo
+// CHECK: [0x6c,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, tba_hi
+// CHECK: [0x6d,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, tma_lo
+// CHECK: [0x6e,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, tma_hi
+// CHECK: [0x6f,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, ttmp11
+// CHECK: [0x7b,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, m0
+// CHECK: [0x7c,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, exec_lo
+// CHECK: [0x7e,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, exec_hi
+// CHECK: [0x7f,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, 0
+// CHECK: [0x80,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, -1
+// CHECK: [0xc1,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, 0.5
+// CHECK: [0xf0,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, -4.0
+// CHECK: [0xf7,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, src_vccz
+// CHECK: [0xfb,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, src_execz
+// CHECK: [0xfc,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, src_scc
+// CHECK: [0xfd,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, 0xaf123456
+// CHECK: [0xff,0x1a,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset1_b32 s5, 0x3f717273
+// CHECK: [0xff,0x1a,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset1_b64 s[10:11], s1
+// CHECK: [0x01,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[12:13], s1
+// CHECK: [0x01,0x1b,0x8c,0xbe]
+
+s_bitset1_b64 s[100:101], s1
+// CHECK: [0x01,0x1b,0xe4,0xbe]
+
+s_bitset1_b64 flat_scratch, s1
+// CHECK: [0x01,0x1b,0xe6,0xbe]
+
+s_bitset1_b64 vcc, s1
+// CHECK: [0x01,0x1b,0xea,0xbe]
+
+s_bitset1_b64 tba, s1
+// CHECK: [0x01,0x1b,0xec,0xbe]
+
+s_bitset1_b64 tma, s1
+// CHECK: [0x01,0x1b,0xee,0xbe]
+
+s_bitset1_b64 ttmp[10:11], s1
+// CHECK: [0x01,0x1b,0xfa,0xbe]
+
+s_bitset1_b64 exec, s1
+// CHECK: [0x01,0x1b,0xfe,0xbe]
+
+s_bitset1_b64 s[10:11], s101
+// CHECK: [0x65,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], flat_scratch_lo
+// CHECK: [0x66,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], flat_scratch_hi
+// CHECK: [0x67,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], vcc_lo
+// CHECK: [0x6a,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], vcc_hi
+// CHECK: [0x6b,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], tba_lo
+// CHECK: [0x6c,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], tba_hi
+// CHECK: [0x6d,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], tma_lo
+// CHECK: [0x6e,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], tma_hi
+// CHECK: [0x6f,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], ttmp11
+// CHECK: [0x7b,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], m0
+// CHECK: [0x7c,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], exec_lo
+// CHECK: [0x7e,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], exec_hi
+// CHECK: [0x7f,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], 0
+// CHECK: [0x80,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], -1
+// CHECK: [0xc1,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x1b,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset1_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x1b,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_getpc_b64 s[10:11]
+// CHECK: [0x00,0x1c,0x8a,0xbe]
+
+s_getpc_b64 s[12:13]
+// CHECK: [0x00,0x1c,0x8c,0xbe]
+
+s_getpc_b64 s[100:101]
+// CHECK: [0x00,0x1c,0xe4,0xbe]
+
+s_getpc_b64 flat_scratch
+// CHECK: [0x00,0x1c,0xe6,0xbe]
+
+s_getpc_b64 vcc
+// CHECK: [0x00,0x1c,0xea,0xbe]
+
+s_getpc_b64 tba
+// CHECK: [0x00,0x1c,0xec,0xbe]
+
+s_getpc_b64 tma
+// CHECK: [0x00,0x1c,0xee,0xbe]
+
+s_getpc_b64 ttmp[10:11]
+// CHECK: [0x00,0x1c,0xfa,0xbe]
+
+s_getpc_b64 exec
+// CHECK: [0x00,0x1c,0xfe,0xbe]
+
+s_setpc_b64 s[2:3]
+// CHECK: [0x02,0x1d,0x80,0xbe]
+
+s_setpc_b64 s[4:5]
+// CHECK: [0x04,0x1d,0x80,0xbe]
+
+s_setpc_b64 s[100:101]
+// CHECK: [0x64,0x1d,0x80,0xbe]
+
+s_setpc_b64 flat_scratch
+// CHECK: [0x66,0x1d,0x80,0xbe]
+
+s_setpc_b64 vcc
+// CHECK: [0x6a,0x1d,0x80,0xbe]
+
+s_setpc_b64 tba
+// CHECK: [0x6c,0x1d,0x80,0xbe]
+
+s_setpc_b64 tma
+// CHECK: [0x6e,0x1d,0x80,0xbe]
+
+s_setpc_b64 ttmp[10:11]
+// CHECK: [0x7a,0x1d,0x80,0xbe]
+
+s_swappc_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x1e,0x8c,0xbe]
+
+s_swappc_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x1e,0xe4,0xbe]
+
+s_swappc_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x1e,0xe6,0xbe]
+
+s_swappc_b64 vcc, s[2:3]
+// CHECK: [0x02,0x1e,0xea,0xbe]
+
+s_swappc_b64 tba, s[2:3]
+// CHECK: [0x02,0x1e,0xec,0xbe]
+
+s_swappc_b64 tma, s[2:3]
+// CHECK: [0x02,0x1e,0xee,0xbe]
+
+s_swappc_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x1e,0xfa,0xbe]
+
+s_swappc_b64 exec, s[2:3]
+// CHECK: [0x02,0x1e,0xfe,0xbe]
+
+s_swappc_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], vcc
+// CHECK: [0x6a,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], tba
+// CHECK: [0x6c,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], tma
+// CHECK: [0x6e,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x1e,0x8a,0xbe]
+
+s_rfe_b64 s[2:3]
+// CHECK: [0x02,0x1f,0x80,0xbe]
+
+s_rfe_b64 s[4:5]
+// CHECK: [0x04,0x1f,0x80,0xbe]
+
+s_rfe_b64 s[100:101]
+// CHECK: [0x64,0x1f,0x80,0xbe]
+
+s_rfe_b64 flat_scratch
+// CHECK: [0x66,0x1f,0x80,0xbe]
+
+s_rfe_b64 vcc
+// CHECK: [0x6a,0x1f,0x80,0xbe]
+
+s_rfe_b64 tba
+// CHECK: [0x6c,0x1f,0x80,0xbe]
+
+s_rfe_b64 tma
+// CHECK: [0x6e,0x1f,0x80,0xbe]
+
+s_rfe_b64 ttmp[10:11]
+// CHECK: [0x7a,0x1f,0x80,0xbe]
+
+s_and_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x20,0x8c,0xbe]
+
+s_and_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x20,0xe4,0xbe]
+
+s_and_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x20,0xe6,0xbe]
+
+s_and_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x20,0xea,0xbe]
+
+s_and_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x20,0xec,0xbe]
+
+s_and_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x20,0xee,0xbe]
+
+s_and_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x20,0xfa,0xbe]
+
+s_and_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x20,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_and_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x20,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_or_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x21,0x8c,0xbe]
+
+s_or_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x21,0xe4,0xbe]
+
+s_or_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x21,0xe6,0xbe]
+
+s_or_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x21,0xea,0xbe]
+
+s_or_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x21,0xec,0xbe]
+
+s_or_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x21,0xee,0xbe]
+
+s_or_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x21,0xfa,0xbe]
+
+s_or_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x21,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_or_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x21,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xor_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x22,0x8c,0xbe]
+
+s_xor_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x22,0xe4,0xbe]
+
+s_xor_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x22,0xe6,0xbe]
+
+s_xor_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x22,0xea,0xbe]
+
+s_xor_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x22,0xec,0xbe]
+
+s_xor_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x22,0xee,0xbe]
+
+s_xor_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x22,0xfa,0xbe]
+
+s_xor_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x22,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xor_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x22,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn2_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x23,0x8c,0xbe]
+
+s_andn2_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x23,0xe4,0xbe]
+
+s_andn2_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x23,0xe6,0xbe]
+
+s_andn2_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x23,0xea,0xbe]
+
+s_andn2_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x23,0xec,0xbe]
+
+s_andn2_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x23,0xee,0xbe]
+
+s_andn2_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x23,0xfa,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x23,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn2_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x23,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_orn2_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x24,0x8c,0xbe]
+
+s_orn2_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x24,0xe4,0xbe]
+
+s_orn2_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x24,0xe6,0xbe]
+
+s_orn2_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x24,0xea,0xbe]
+
+s_orn2_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x24,0xec,0xbe]
+
+s_orn2_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x24,0xee,0xbe]
+
+s_orn2_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x24,0xfa,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x24,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_orn2_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x24,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nand_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x25,0x8c,0xbe]
+
+s_nand_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x25,0xe4,0xbe]
+
+s_nand_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x25,0xe6,0xbe]
+
+s_nand_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x25,0xea,0xbe]
+
+s_nand_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x25,0xec,0xbe]
+
+s_nand_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x25,0xee,0xbe]
+
+s_nand_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x25,0xfa,0xbe]
+
+s_nand_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x25,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nand_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x25,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nor_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x26,0x8c,0xbe]
+
+s_nor_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x26,0xe4,0xbe]
+
+s_nor_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x26,0xe6,0xbe]
+
+s_nor_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x26,0xea,0xbe]
+
+s_nor_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x26,0xec,0xbe]
+
+s_nor_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x26,0xee,0xbe]
+
+s_nor_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x26,0xfa,0xbe]
+
+s_nor_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x26,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nor_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x26,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xnor_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x27,0x8c,0xbe]
+
+s_xnor_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x27,0xe4,0xbe]
+
+s_xnor_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x27,0xe6,0xbe]
+
+s_xnor_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x27,0xea,0xbe]
+
+s_xnor_saveexec_b64 tba, s[2:3]
+// CHECK: [0x02,0x27,0xec,0xbe]
+
+s_xnor_saveexec_b64 tma, s[2:3]
+// CHECK: [0x02,0x27,0xee,0xbe]
+
+s_xnor_saveexec_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x27,0xfa,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], tba
+// CHECK: [0x6c,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], tma
+// CHECK: [0x6e,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x27,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xnor_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x27,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_quadmask_b32 s5, s1
+// CHECK: [0x01,0x28,0x85,0xbe]
+
+s_quadmask_b32 s101, s1
+// CHECK: [0x01,0x28,0xe5,0xbe]
+
+s_quadmask_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x28,0xe6,0xbe]
+
+s_quadmask_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x28,0xe7,0xbe]
+
+s_quadmask_b32 vcc_lo, s1
+// CHECK: [0x01,0x28,0xea,0xbe]
+
+s_quadmask_b32 vcc_hi, s1
+// CHECK: [0x01,0x28,0xeb,0xbe]
+
+s_quadmask_b32 tba_lo, s1
+// CHECK: [0x01,0x28,0xec,0xbe]
+
+s_quadmask_b32 tba_hi, s1
+// CHECK: [0x01,0x28,0xed,0xbe]
+
+s_quadmask_b32 tma_lo, s1
+// CHECK: [0x01,0x28,0xee,0xbe]
+
+s_quadmask_b32 tma_hi, s1
+// CHECK: [0x01,0x28,0xef,0xbe]
+
+s_quadmask_b32 ttmp11, s1
+// CHECK: [0x01,0x28,0xfb,0xbe]
+
+s_quadmask_b32 m0, s1
+// CHECK: [0x01,0x28,0xfc,0xbe]
+
+s_quadmask_b32 exec_lo, s1
+// CHECK: [0x01,0x28,0xfe,0xbe]
+
+s_quadmask_b32 exec_hi, s1
+// CHECK: [0x01,0x28,0xff,0xbe]
+
+s_quadmask_b32 s5, s101
+// CHECK: [0x65,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, vcc_lo
+// CHECK: [0x6a,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, vcc_hi
+// CHECK: [0x6b,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, tba_lo
+// CHECK: [0x6c,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, tba_hi
+// CHECK: [0x6d,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, tma_lo
+// CHECK: [0x6e,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, tma_hi
+// CHECK: [0x6f,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, ttmp11
+// CHECK: [0x7b,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, m0
+// CHECK: [0x7c,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, exec_lo
+// CHECK: [0x7e,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, exec_hi
+// CHECK: [0x7f,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, 0
+// CHECK: [0x80,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, -1
+// CHECK: [0xc1,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, 0.5
+// CHECK: [0xf0,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, -4.0
+// CHECK: [0xf7,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, src_vccz
+// CHECK: [0xfb,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, src_execz
+// CHECK: [0xfc,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, src_scc
+// CHECK: [0xfd,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, 0xaf123456
+// CHECK: [0xff,0x28,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_quadmask_b32 s5, 0x3f717273
+// CHECK: [0xff,0x28,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_quadmask_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x29,0x8c,0xbe]
+
+s_quadmask_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x29,0xe4,0xbe]
+
+s_quadmask_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x29,0xe6,0xbe]
+
+s_quadmask_b64 vcc, s[2:3]
+// CHECK: [0x02,0x29,0xea,0xbe]
+
+s_quadmask_b64 tba, s[2:3]
+// CHECK: [0x02,0x29,0xec,0xbe]
+
+s_quadmask_b64 tma, s[2:3]
+// CHECK: [0x02,0x29,0xee,0xbe]
+
+s_quadmask_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x29,0xfa,0xbe]
+
+s_quadmask_b64 exec, s[2:3]
+// CHECK: [0x02,0x29,0xfe,0xbe]
+
+s_quadmask_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], vcc
+// CHECK: [0x6a,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], tba
+// CHECK: [0x6c,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], tma
+// CHECK: [0x6e,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], exec
+// CHECK: [0x7e,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], 0
+// CHECK: [0x80,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], -1
+// CHECK: [0xc1,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x29,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_quadmask_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x29,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_movrels_b32 s5, s1
+// CHECK: [0x01,0x2a,0x85,0xbe]
+
+s_movrels_b32 s101, s1
+// CHECK: [0x01,0x2a,0xe5,0xbe]
+
+s_movrels_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x2a,0xe6,0xbe]
+
+s_movrels_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x2a,0xe7,0xbe]
+
+s_movrels_b32 vcc_lo, s1
+// CHECK: [0x01,0x2a,0xea,0xbe]
+
+s_movrels_b32 vcc_hi, s1
+// CHECK: [0x01,0x2a,0xeb,0xbe]
+
+s_movrels_b32 tba_lo, s1
+// CHECK: [0x01,0x2a,0xec,0xbe]
+
+s_movrels_b32 tba_hi, s1
+// CHECK: [0x01,0x2a,0xed,0xbe]
+
+s_movrels_b32 tma_lo, s1
+// CHECK: [0x01,0x2a,0xee,0xbe]
+
+s_movrels_b32 tma_hi, s1
+// CHECK: [0x01,0x2a,0xef,0xbe]
+
+s_movrels_b32 ttmp11, s1
+// CHECK: [0x01,0x2a,0xfb,0xbe]
+
+s_movrels_b32 m0, s1
+// CHECK: [0x01,0x2a,0xfc,0xbe]
+
+s_movrels_b32 exec_lo, s1
+// CHECK: [0x01,0x2a,0xfe,0xbe]
+
+s_movrels_b32 exec_hi, s1
+// CHECK: [0x01,0x2a,0xff,0xbe]
+
+s_movrels_b32 s5, s101
+// CHECK: [0x65,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, vcc_lo
+// CHECK: [0x6a,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, vcc_hi
+// CHECK: [0x6b,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, tba_lo
+// CHECK: [0x6c,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, tba_hi
+// CHECK: [0x6d,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, tma_lo
+// CHECK: [0x6e,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, tma_hi
+// CHECK: [0x6f,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, ttmp11
+// CHECK: [0x7b,0x2a,0x85,0xbe]
+
+s_movrels_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x2b,0x8c,0xbe]
+
+s_movrels_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x2b,0xe4,0xbe]
+
+s_movrels_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x2b,0xe6,0xbe]
+
+s_movrels_b64 vcc, s[2:3]
+// CHECK: [0x02,0x2b,0xea,0xbe]
+
+s_movrels_b64 tba, s[2:3]
+// CHECK: [0x02,0x2b,0xec,0xbe]
+
+s_movrels_b64 tma, s[2:3]
+// CHECK: [0x02,0x2b,0xee,0xbe]
+
+s_movrels_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x2b,0xfa,0xbe]
+
+s_movrels_b64 exec, s[2:3]
+// CHECK: [0x02,0x2b,0xfe,0xbe]
+
+s_movrels_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], vcc
+// CHECK: [0x6a,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], tba
+// CHECK: [0x6c,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], tma
+// CHECK: [0x6e,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x2b,0x8a,0xbe]
+
+s_movreld_b32 s5, s1
+// CHECK: [0x01,0x2c,0x85,0xbe]
+
+s_movreld_b32 s101, s1
+// CHECK: [0x01,0x2c,0xe5,0xbe]
+
+s_movreld_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x2c,0xe6,0xbe]
+
+s_movreld_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x2c,0xe7,0xbe]
+
+s_movreld_b32 vcc_lo, s1
+// CHECK: [0x01,0x2c,0xea,0xbe]
+
+s_movreld_b32 vcc_hi, s1
+// CHECK: [0x01,0x2c,0xeb,0xbe]
+
+s_movreld_b32 tba_lo, s1
+// CHECK: [0x01,0x2c,0xec,0xbe]
+
+s_movreld_b32 tba_hi, s1
+// CHECK: [0x01,0x2c,0xed,0xbe]
+
+s_movreld_b32 tma_lo, s1
+// CHECK: [0x01,0x2c,0xee,0xbe]
+
+s_movreld_b32 tma_hi, s1
+// CHECK: [0x01,0x2c,0xef,0xbe]
+
+s_movreld_b32 ttmp11, s1
+// CHECK: [0x01,0x2c,0xfb,0xbe]
+
+s_movreld_b32 s5, s101
+// CHECK: [0x65,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, vcc_lo
+// CHECK: [0x6a,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, vcc_hi
+// CHECK: [0x6b,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, tba_lo
+// CHECK: [0x6c,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, tba_hi
+// CHECK: [0x6d,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, tma_lo
+// CHECK: [0x6e,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, tma_hi
+// CHECK: [0x6f,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, ttmp11
+// CHECK: [0x7b,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, m0
+// CHECK: [0x7c,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, 0
+// CHECK: [0x80,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, -1
+// CHECK: [0xc1,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, 0.5
+// CHECK: [0xf0,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, -4.0
+// CHECK: [0xf7,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, src_vccz
+// CHECK: [0xfb,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, src_execz
+// CHECK: [0xfc,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, src_scc
+// CHECK: [0xfd,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, 0xaf123456
+// CHECK: [0xff,0x2c,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_movreld_b32 s5, 0x3f717273
+// CHECK: [0xff,0x2c,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_movreld_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x2d,0x8c,0xbe]
+
+s_movreld_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x2d,0xe4,0xbe]
+
+s_movreld_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x2d,0xe6,0xbe]
+
+s_movreld_b64 vcc, s[2:3]
+// CHECK: [0x02,0x2d,0xea,0xbe]
+
+s_movreld_b64 tba, s[2:3]
+// CHECK: [0x02,0x2d,0xec,0xbe]
+
+s_movreld_b64 tma, s[2:3]
+// CHECK: [0x02,0x2d,0xee,0xbe]
+
+s_movreld_b64 ttmp[10:11], s[2:3]
+// CHECK: [0x02,0x2d,0xfa,0xbe]
+
+s_movreld_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], vcc
+// CHECK: [0x6a,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], tba
+// CHECK: [0x6c,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], tma
+// CHECK: [0x6e,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], ttmp[10:11]
+// CHECK: [0x7a,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], 0
+// CHECK: [0x80,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], -1
+// CHECK: [0xc1,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x2d,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_movreld_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x2d,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cbranch_join s1
+// CHECK: [0x01,0x2e,0x80,0xbe]
+
+s_cbranch_join s101
+// CHECK: [0x65,0x2e,0x80,0xbe]
+
+s_cbranch_join flat_scratch_lo
+// CHECK: [0x66,0x2e,0x80,0xbe]
+
+s_cbranch_join flat_scratch_hi
+// CHECK: [0x67,0x2e,0x80,0xbe]
+
+s_cbranch_join vcc_lo
+// CHECK: [0x6a,0x2e,0x80,0xbe]
+
+s_cbranch_join vcc_hi
+// CHECK: [0x6b,0x2e,0x80,0xbe]
+
+s_cbranch_join tba_lo
+// CHECK: [0x6c,0x2e,0x80,0xbe]
+
+s_cbranch_join tba_hi
+// CHECK: [0x6d,0x2e,0x80,0xbe]
+
+s_cbranch_join tma_lo
+// CHECK: [0x6e,0x2e,0x80,0xbe]
+
+s_cbranch_join tma_hi
+// CHECK: [0x6f,0x2e,0x80,0xbe]
+
+s_cbranch_join ttmp11
+// CHECK: [0x7b,0x2e,0x80,0xbe]
+
+s_abs_i32 s5, s1
+// CHECK: [0x01,0x30,0x85,0xbe]
+
+s_abs_i32 s101, s1
+// CHECK: [0x01,0x30,0xe5,0xbe]
+
+s_abs_i32 flat_scratch_lo, s1
+// CHECK: [0x01,0x30,0xe6,0xbe]
+
+s_abs_i32 flat_scratch_hi, s1
+// CHECK: [0x01,0x30,0xe7,0xbe]
+
+s_abs_i32 vcc_lo, s1
+// CHECK: [0x01,0x30,0xea,0xbe]
+
+s_abs_i32 vcc_hi, s1
+// CHECK: [0x01,0x30,0xeb,0xbe]
+
+s_abs_i32 tba_lo, s1
+// CHECK: [0x01,0x30,0xec,0xbe]
+
+s_abs_i32 tba_hi, s1
+// CHECK: [0x01,0x30,0xed,0xbe]
+
+s_abs_i32 tma_lo, s1
+// CHECK: [0x01,0x30,0xee,0xbe]
+
+s_abs_i32 tma_hi, s1
+// CHECK: [0x01,0x30,0xef,0xbe]
+
+s_abs_i32 ttmp11, s1
+// CHECK: [0x01,0x30,0xfb,0xbe]
+
+s_abs_i32 m0, s1
+// CHECK: [0x01,0x30,0xfc,0xbe]
+
+s_abs_i32 exec_lo, s1
+// CHECK: [0x01,0x30,0xfe,0xbe]
+
+s_abs_i32 exec_hi, s1
+// CHECK: [0x01,0x30,0xff,0xbe]
+
+s_abs_i32 s5, s101
+// CHECK: [0x65,0x30,0x85,0xbe]
+
+s_abs_i32 s5, flat_scratch_lo
+// CHECK: [0x66,0x30,0x85,0xbe]
+
+s_abs_i32 s5, flat_scratch_hi
+// CHECK: [0x67,0x30,0x85,0xbe]
+
+s_abs_i32 s5, vcc_lo
+// CHECK: [0x6a,0x30,0x85,0xbe]
+
+s_abs_i32 s5, vcc_hi
+// CHECK: [0x6b,0x30,0x85,0xbe]
+
+s_abs_i32 s5, tba_lo
+// CHECK: [0x6c,0x30,0x85,0xbe]
+
+s_abs_i32 s5, tba_hi
+// CHECK: [0x6d,0x30,0x85,0xbe]
+
+s_abs_i32 s5, tma_lo
+// CHECK: [0x6e,0x30,0x85,0xbe]
+
+s_abs_i32 s5, tma_hi
+// CHECK: [0x6f,0x30,0x85,0xbe]
+
+s_abs_i32 s5, ttmp11
+// CHECK: [0x7b,0x30,0x85,0xbe]
+
+s_abs_i32 s5, m0
+// CHECK: [0x7c,0x30,0x85,0xbe]
+
+s_abs_i32 s5, exec_lo
+// CHECK: [0x7e,0x30,0x85,0xbe]
+
+s_abs_i32 s5, exec_hi
+// CHECK: [0x7f,0x30,0x85,0xbe]
+
+s_abs_i32 s5, 0
+// CHECK: [0x80,0x30,0x85,0xbe]
+
+s_abs_i32 s5, -1
+// CHECK: [0xc1,0x30,0x85,0xbe]
+
+s_abs_i32 s5, 0.5
+// CHECK: [0xf0,0x30,0x85,0xbe]
+
+s_abs_i32 s5, -4.0
+// CHECK: [0xf7,0x30,0x85,0xbe]
+
+s_abs_i32 s5, src_vccz
+// CHECK: [0xfb,0x30,0x85,0xbe]
+
+s_abs_i32 s5, src_execz
+// CHECK: [0xfc,0x30,0x85,0xbe]
+
+s_abs_i32 s5, src_scc
+// CHECK: [0xfd,0x30,0x85,0xbe]
+
+s_abs_i32 s5, 0xaf123456
+// CHECK: [0xff,0x30,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_abs_i32 s5, 0x3f717273
+// CHECK: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_set_gpr_idx_idx s1
+// CHECK: [0x01,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx s101
+// CHECK: [0x65,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx flat_scratch_lo
+// CHECK: [0x66,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx flat_scratch_hi
+// CHECK: [0x67,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx vcc_lo
+// CHECK: [0x6a,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx vcc_hi
+// CHECK: [0x6b,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx tba_lo
+// CHECK: [0x6c,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx tba_hi
+// CHECK: [0x6d,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx tma_lo
+// CHECK: [0x6e,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx tma_hi
+// CHECK: [0x6f,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx ttmp11
+// CHECK: [0x7b,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx m0
+// CHECK: [0x7c,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx 0
+// CHECK: [0x80,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx -1
+// CHECK: [0xc1,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx 0.5
+// CHECK: [0xf0,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx -4.0
+// CHECK: [0xf7,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx src_vccz
+// CHECK: [0xfb,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx src_execz
+// CHECK: [0xfc,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx src_scc
+// CHECK: [0xfd,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx 0xaf123456
+// CHECK: [0xff,0x32,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_set_gpr_idx_idx 0x3f717273
+// CHECK: [0xff,0x32,0x80,0xbe,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx8_asm_sop2.s
new file mode 100644
index 0000000000000..121d0ad08fb9c
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sop2.s
@@ -0,0 +1,6952 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+s_add_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x80]
+
+s_add_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x80]
+
+s_add_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x80]
+
+s_add_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x80]
+
+s_add_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x80]
+
+s_add_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x80]
+
+s_add_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x80]
+
+s_add_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x80]
+
+s_add_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x80]
+
+s_add_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x80]
+
+s_add_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x80]
+
+s_add_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x80]
+
+s_add_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x80]
+
+s_add_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x80]
+
+s_add_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x80]
+
+s_add_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x80]
+
+s_add_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x80]
+
+s_add_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x80]
+
+s_add_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x80]
+
+s_add_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x80]
+
+s_add_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x80]
+
+s_add_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x80]
+
+s_add_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x80]
+
+s_add_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x80]
+
+s_add_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x80]
+
+s_add_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x80]
+
+s_add_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x80]
+
+s_add_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x80]
+
+s_add_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x80]
+
+s_add_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x80]
+
+s_add_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x80]
+
+s_add_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x80]
+
+s_add_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x80]
+
+s_add_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x80]
+
+s_add_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x80,0x56,0x34,0x12,0xaf]
+
+s_add_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x80,0x73,0x72,0x71,0x3f]
+
+s_add_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x80]
+
+s_add_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x80]
+
+s_add_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x80]
+
+s_add_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x80]
+
+s_add_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x80]
+
+s_add_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x80]
+
+s_add_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x80]
+
+s_add_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x80]
+
+s_add_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x80]
+
+s_add_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x80]
+
+s_add_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x80]
+
+s_add_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x80]
+
+s_add_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x80]
+
+s_add_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x80]
+
+s_add_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x80]
+
+s_add_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x80]
+
+s_add_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x80]
+
+s_add_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x80]
+
+s_add_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x80]
+
+s_add_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x80]
+
+s_add_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x80,0x56,0x34,0x12,0xaf]
+
+s_add_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x80,0x73,0x72,0x71,0x3f]
+
+s_sub_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x80]
+
+s_sub_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x80]
+
+s_sub_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x80]
+
+s_sub_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x80]
+
+s_sub_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x80]
+
+s_sub_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x80]
+
+s_sub_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x80]
+
+s_sub_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x80]
+
+s_sub_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x80]
+
+s_sub_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x80]
+
+s_sub_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x80]
+
+s_sub_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x80]
+
+s_sub_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x80]
+
+s_sub_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x80]
+
+s_sub_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x80]
+
+s_sub_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x80]
+
+s_sub_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x80]
+
+s_sub_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x80]
+
+s_sub_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x80]
+
+s_sub_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x80]
+
+s_sub_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x80]
+
+s_sub_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x80]
+
+s_sub_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x80]
+
+s_sub_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x80]
+
+s_sub_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x80]
+
+s_sub_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x80]
+
+s_sub_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x80]
+
+s_sub_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x80]
+
+s_sub_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x80]
+
+s_sub_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x80]
+
+s_sub_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x80]
+
+s_sub_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x80]
+
+s_sub_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x80]
+
+s_sub_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x80]
+
+s_sub_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x80,0x56,0x34,0x12,0xaf]
+
+s_sub_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x80,0x73,0x72,0x71,0x3f]
+
+s_sub_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x80]
+
+s_sub_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x80]
+
+s_sub_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x80]
+
+s_sub_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x80]
+
+s_sub_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x80]
+
+s_sub_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x80]
+
+s_sub_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x80]
+
+s_sub_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x80]
+
+s_sub_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x80]
+
+s_sub_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x80]
+
+s_sub_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x80]
+
+s_sub_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x80]
+
+s_sub_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x80]
+
+s_sub_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x80]
+
+s_sub_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x80]
+
+s_sub_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x80]
+
+s_sub_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x80]
+
+s_sub_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x80]
+
+s_sub_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x80]
+
+s_sub_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x80]
+
+s_sub_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x80,0x56,0x34,0x12,0xaf]
+
+s_sub_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x80,0x73,0x72,0x71,0x3f]
+
+s_add_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x81]
+
+s_add_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x81]
+
+s_add_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x81]
+
+s_add_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x81]
+
+s_add_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x81]
+
+s_add_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x81]
+
+s_add_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x81]
+
+s_add_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x81]
+
+s_add_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x81]
+
+s_add_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x81]
+
+s_add_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x81]
+
+s_add_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x81]
+
+s_add_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x81]
+
+s_add_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x81]
+
+s_add_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x81]
+
+s_add_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x81]
+
+s_add_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x81]
+
+s_add_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x81]
+
+s_add_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x81]
+
+s_add_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x81]
+
+s_add_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x81]
+
+s_add_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x81]
+
+s_add_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x81]
+
+s_add_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x81]
+
+s_add_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x81]
+
+s_add_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x81]
+
+s_add_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x81]
+
+s_add_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x81]
+
+s_add_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x81]
+
+s_add_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x81]
+
+s_add_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x81]
+
+s_add_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x81]
+
+s_add_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x81]
+
+s_add_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x81]
+
+s_add_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x81,0x56,0x34,0x12,0xaf]
+
+s_add_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x81,0x73,0x72,0x71,0x3f]
+
+s_add_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x81]
+
+s_add_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x81]
+
+s_add_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x81]
+
+s_add_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x81]
+
+s_add_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x81]
+
+s_add_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x81]
+
+s_add_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x81]
+
+s_add_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x81]
+
+s_add_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x81]
+
+s_add_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x81]
+
+s_add_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x81]
+
+s_add_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x81]
+
+s_add_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x81]
+
+s_add_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x81]
+
+s_add_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x81]
+
+s_add_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x81]
+
+s_add_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x81]
+
+s_add_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x81]
+
+s_add_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x81]
+
+s_add_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x81]
+
+s_add_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x81,0x56,0x34,0x12,0xaf]
+
+s_add_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x81,0x73,0x72,0x71,0x3f]
+
+s_sub_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x81]
+
+s_sub_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x81]
+
+s_sub_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x81]
+
+s_sub_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x81]
+
+s_sub_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x81]
+
+s_sub_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x81]
+
+s_sub_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x81]
+
+s_sub_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x81]
+
+s_sub_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x81]
+
+s_sub_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x81]
+
+s_sub_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x81]
+
+s_sub_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x81]
+
+s_sub_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x81]
+
+s_sub_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x81]
+
+s_sub_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x81]
+
+s_sub_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x81]
+
+s_sub_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x81]
+
+s_sub_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x81]
+
+s_sub_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x81]
+
+s_sub_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x81]
+
+s_sub_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x81]
+
+s_sub_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x81]
+
+s_sub_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x81]
+
+s_sub_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x81]
+
+s_sub_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x81]
+
+s_sub_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x81]
+
+s_sub_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x81]
+
+s_sub_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x81]
+
+s_sub_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x81]
+
+s_sub_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x81]
+
+s_sub_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x81]
+
+s_sub_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x81]
+
+s_sub_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x81]
+
+s_sub_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x81]
+
+s_sub_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x81,0x56,0x34,0x12,0xaf]
+
+s_sub_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x81,0x73,0x72,0x71,0x3f]
+
+s_sub_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x81]
+
+s_sub_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x81]
+
+s_sub_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x81]
+
+s_sub_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x81]
+
+s_sub_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x81]
+
+s_sub_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x81]
+
+s_sub_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x81]
+
+s_sub_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x81]
+
+s_sub_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x81]
+
+s_sub_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x81]
+
+s_sub_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x81]
+
+s_sub_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x81]
+
+s_sub_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x81]
+
+s_sub_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x81]
+
+s_sub_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x81]
+
+s_sub_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x81]
+
+s_sub_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x81]
+
+s_sub_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x81]
+
+s_sub_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x81]
+
+s_sub_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x81]
+
+s_sub_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x81,0x56,0x34,0x12,0xaf]
+
+s_sub_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x81,0x73,0x72,0x71,0x3f]
+
+s_addc_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x82]
+
+s_addc_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x82]
+
+s_addc_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x82]
+
+s_addc_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x82]
+
+s_addc_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x82]
+
+s_addc_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x82]
+
+s_addc_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x82]
+
+s_addc_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x82]
+
+s_addc_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x82]
+
+s_addc_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x82]
+
+s_addc_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x82]
+
+s_addc_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x82]
+
+s_addc_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x82]
+
+s_addc_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x82]
+
+s_addc_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x82]
+
+s_addc_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x82]
+
+s_addc_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x82]
+
+s_addc_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x82]
+
+s_addc_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x82]
+
+s_addc_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x82]
+
+s_addc_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x82]
+
+s_addc_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x82]
+
+s_addc_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x82]
+
+s_addc_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x82]
+
+s_addc_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x82]
+
+s_addc_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x82]
+
+s_addc_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x82]
+
+s_addc_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x82]
+
+s_addc_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x82]
+
+s_addc_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x82]
+
+s_addc_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x82]
+
+s_addc_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x82]
+
+s_addc_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x82]
+
+s_addc_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x82]
+
+s_addc_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x82,0x56,0x34,0x12,0xaf]
+
+s_addc_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x82,0x73,0x72,0x71,0x3f]
+
+s_addc_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x82]
+
+s_addc_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x82]
+
+s_addc_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x82]
+
+s_addc_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x82]
+
+s_addc_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x82]
+
+s_addc_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x82]
+
+s_addc_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x82]
+
+s_addc_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x82]
+
+s_addc_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x82]
+
+s_addc_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x82]
+
+s_addc_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x82]
+
+s_addc_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x82]
+
+s_addc_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x82]
+
+s_addc_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x82]
+
+s_addc_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x82]
+
+s_addc_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x82]
+
+s_addc_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x82]
+
+s_addc_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x82]
+
+s_addc_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x82]
+
+s_addc_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x82]
+
+s_addc_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x82,0x56,0x34,0x12,0xaf]
+
+s_addc_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x82,0x73,0x72,0x71,0x3f]
+
+s_subb_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x82]
+
+s_subb_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x82]
+
+s_subb_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x82]
+
+s_subb_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x82]
+
+s_subb_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x82]
+
+s_subb_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x82]
+
+s_subb_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x82]
+
+s_subb_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x82]
+
+s_subb_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x82]
+
+s_subb_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x82]
+
+s_subb_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x82]
+
+s_subb_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x82]
+
+s_subb_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x82]
+
+s_subb_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x82]
+
+s_subb_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x82]
+
+s_subb_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x82]
+
+s_subb_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x82]
+
+s_subb_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x82]
+
+s_subb_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x82]
+
+s_subb_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x82]
+
+s_subb_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x82]
+
+s_subb_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x82]
+
+s_subb_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x82]
+
+s_subb_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x82]
+
+s_subb_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x82]
+
+s_subb_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x82]
+
+s_subb_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x82]
+
+s_subb_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x82]
+
+s_subb_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x82]
+
+s_subb_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x82]
+
+s_subb_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x82]
+
+s_subb_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x82]
+
+s_subb_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x82]
+
+s_subb_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x82]
+
+s_subb_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x82,0x56,0x34,0x12,0xaf]
+
+s_subb_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x82,0x73,0x72,0x71,0x3f]
+
+s_subb_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x82]
+
+s_subb_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x82]
+
+s_subb_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x82]
+
+s_subb_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x82]
+
+s_subb_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x82]
+
+s_subb_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x82]
+
+s_subb_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x82]
+
+s_subb_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x82]
+
+s_subb_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x82]
+
+s_subb_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x82]
+
+s_subb_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x82]
+
+s_subb_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x82]
+
+s_subb_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x82]
+
+s_subb_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x82]
+
+s_subb_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x82]
+
+s_subb_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x82]
+
+s_subb_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x82]
+
+s_subb_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x82]
+
+s_subb_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x82]
+
+s_subb_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x82]
+
+s_subb_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x82,0x56,0x34,0x12,0xaf]
+
+s_subb_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x82,0x73,0x72,0x71,0x3f]
+
+s_min_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x83]
+
+s_min_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x83]
+
+s_min_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x83]
+
+s_min_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x83]
+
+s_min_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x83]
+
+s_min_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x83]
+
+s_min_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x83]
+
+s_min_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x83]
+
+s_min_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x83]
+
+s_min_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x83]
+
+s_min_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x83]
+
+s_min_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x83]
+
+s_min_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x83]
+
+s_min_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x83]
+
+s_min_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x83]
+
+s_min_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x83]
+
+s_min_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x83]
+
+s_min_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x83]
+
+s_min_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x83]
+
+s_min_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x83]
+
+s_min_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x83]
+
+s_min_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x83]
+
+s_min_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x83]
+
+s_min_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x83]
+
+s_min_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x83]
+
+s_min_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x83]
+
+s_min_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x83]
+
+s_min_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x83]
+
+s_min_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x83]
+
+s_min_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x83]
+
+s_min_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x83]
+
+s_min_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x83]
+
+s_min_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x83]
+
+s_min_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x83]
+
+s_min_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x83]
+
+s_min_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x83]
+
+s_min_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x83]
+
+s_min_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x83]
+
+s_min_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x83]
+
+s_min_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x83]
+
+s_min_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x83]
+
+s_min_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x83]
+
+s_min_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x83]
+
+s_min_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x83]
+
+s_min_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x83]
+
+s_min_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x83]
+
+s_min_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x83]
+
+s_min_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x83]
+
+s_min_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x83]
+
+s_min_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x83]
+
+s_min_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x83]
+
+s_min_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x83]
+
+s_min_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x83]
+
+s_min_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x83]
+
+s_min_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x83]
+
+s_min_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x83]
+
+s_min_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x83]
+
+s_min_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x83]
+
+s_min_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x83]
+
+s_min_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x83]
+
+s_min_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x83]
+
+s_min_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x83]
+
+s_min_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x83]
+
+s_min_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x83]
+
+s_min_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x83]
+
+s_min_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x83]
+
+s_min_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x83]
+
+s_min_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x83]
+
+s_min_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x83]
+
+s_min_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x83]
+
+s_min_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x83]
+
+s_min_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x83]
+
+s_min_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x83]
+
+s_min_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x83]
+
+s_min_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x83]
+
+s_min_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x83]
+
+s_min_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x83]
+
+s_min_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x83]
+
+s_min_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x83]
+
+s_min_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x83]
+
+s_min_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x83]
+
+s_min_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x83]
+
+s_min_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x83]
+
+s_min_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x83]
+
+s_min_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x83]
+
+s_min_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x83]
+
+s_min_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x83]
+
+s_min_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x83]
+
+s_min_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x83]
+
+s_min_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x83]
+
+s_min_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x83]
+
+s_min_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x83]
+
+s_min_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x83]
+
+s_min_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x83]
+
+s_min_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x83]
+
+s_min_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x83]
+
+s_min_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x83]
+
+s_min_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x83]
+
+s_min_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x83]
+
+s_min_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x83]
+
+s_min_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x83]
+
+s_min_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x83]
+
+s_min_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x83]
+
+s_min_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x83]
+
+s_min_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x83]
+
+s_min_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x83]
+
+s_min_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x83]
+
+s_min_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x83]
+
+s_min_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x83,0x73,0x72,0x71,0x3f]
+
+s_max_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x84]
+
+s_max_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x84]
+
+s_max_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x84]
+
+s_max_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x84]
+
+s_max_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x84]
+
+s_max_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x84]
+
+s_max_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x84]
+
+s_max_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x84]
+
+s_max_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x84]
+
+s_max_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x84]
+
+s_max_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x84]
+
+s_max_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x84]
+
+s_max_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x84]
+
+s_max_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x84]
+
+s_max_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x84]
+
+s_max_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x84]
+
+s_max_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x84]
+
+s_max_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x84]
+
+s_max_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x84]
+
+s_max_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x84]
+
+s_max_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x84]
+
+s_max_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x84]
+
+s_max_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x84]
+
+s_max_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x84]
+
+s_max_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x84]
+
+s_max_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x84]
+
+s_max_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x84]
+
+s_max_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x84]
+
+s_max_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x84]
+
+s_max_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x84]
+
+s_max_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x84]
+
+s_max_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x84]
+
+s_max_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x84]
+
+s_max_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x84]
+
+s_max_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x84]
+
+s_max_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x84]
+
+s_max_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x84]
+
+s_max_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x84]
+
+s_max_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x84]
+
+s_max_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x84]
+
+s_max_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x84]
+
+s_max_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x84]
+
+s_max_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x84]
+
+s_max_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x84]
+
+s_max_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x84]
+
+s_max_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x84]
+
+s_max_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x84]
+
+s_max_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x84]
+
+s_max_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x84]
+
+s_max_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x84]
+
+s_max_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x84]
+
+s_max_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x84]
+
+s_max_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x84]
+
+s_max_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x84]
+
+s_max_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x84]
+
+s_max_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x84]
+
+s_max_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x84]
+
+s_max_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x84]
+
+s_max_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x84]
+
+s_max_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x84]
+
+s_max_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x84]
+
+s_max_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x84]
+
+s_max_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x84]
+
+s_max_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x84]
+
+s_max_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x84]
+
+s_max_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x84]
+
+s_max_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x84]
+
+s_max_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x84]
+
+s_max_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x84]
+
+s_max_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x84]
+
+s_max_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x84]
+
+s_max_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x84]
+
+s_max_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x84]
+
+s_max_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x84]
+
+s_max_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x84]
+
+s_max_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x84]
+
+s_max_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x84]
+
+s_max_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x84]
+
+s_max_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x84]
+
+s_max_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x84]
+
+s_max_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x84]
+
+s_max_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x84]
+
+s_max_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x84]
+
+s_max_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x84]
+
+s_max_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x84]
+
+s_max_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x84]
+
+s_max_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x84]
+
+s_max_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x84]
+
+s_max_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x84]
+
+s_max_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x84]
+
+s_max_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x84]
+
+s_max_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x84]
+
+s_max_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x84]
+
+s_max_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x84]
+
+s_max_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x84]
+
+s_max_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x84]
+
+s_max_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x84]
+
+s_max_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x84]
+
+s_max_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x84]
+
+s_max_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x84]
+
+s_max_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x84]
+
+s_max_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x84]
+
+s_max_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x84]
+
+s_max_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x84]
+
+s_max_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x84]
+
+s_max_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x84]
+
+s_max_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x84]
+
+s_max_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x84]
+
+s_max_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x84,0x73,0x72,0x71,0x3f]
+
+s_cselect_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x85]
+
+s_cselect_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x85]
+
+s_cselect_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x85]
+
+s_cselect_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x85]
+
+s_cselect_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x85]
+
+s_cselect_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x85]
+
+s_cselect_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x85]
+
+s_cselect_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x85]
+
+s_cselect_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x85]
+
+s_cselect_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x85]
+
+s_cselect_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x85]
+
+s_cselect_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x85]
+
+s_cselect_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x85]
+
+s_cselect_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x85]
+
+s_cselect_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x85]
+
+s_cselect_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x85]
+
+s_cselect_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x85]
+
+s_cselect_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x85]
+
+s_cselect_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x85]
+
+s_cselect_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x85]
+
+s_cselect_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x85]
+
+s_cselect_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x85]
+
+s_cselect_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x85]
+
+s_cselect_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x85]
+
+s_cselect_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x85]
+
+s_cselect_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x85]
+
+s_cselect_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x85]
+
+s_cselect_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x85]
+
+s_cselect_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x85]
+
+s_cselect_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x85]
+
+s_cselect_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x85]
+
+s_cselect_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x85]
+
+s_cselect_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x85]
+
+s_cselect_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x85]
+
+s_cselect_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x85]
+
+s_cselect_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x85]
+
+s_cselect_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x85]
+
+s_cselect_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x85]
+
+s_cselect_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x85]
+
+s_cselect_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x85]
+
+s_cselect_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x85]
+
+s_cselect_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x85]
+
+s_cselect_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x85]
+
+s_cselect_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x85]
+
+s_cselect_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x85]
+
+s_cselect_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x85]
+
+s_cselect_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x85]
+
+s_cselect_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x85]
+
+s_cselect_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x85]
+
+s_cselect_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x85]
+
+s_cselect_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x85]
+
+s_cselect_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x85]
+
+s_cselect_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x85]
+
+s_cselect_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x85]
+
+s_cselect_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x85]
+
+s_cselect_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x85]
+
+s_cselect_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x85]
+
+s_cselect_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x85]
+
+s_cselect_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x85]
+
+s_cselect_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x85]
+
+s_cselect_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x85]
+
+s_cselect_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x85]
+
+s_cselect_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x85]
+
+s_cselect_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x85,0x73,0x72,0x71,0x3f]
+
+s_and_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x86]
+
+s_and_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x86]
+
+s_and_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x86]
+
+s_and_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x86]
+
+s_and_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x86]
+
+s_and_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x86]
+
+s_and_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x86]
+
+s_and_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x86]
+
+s_and_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x86]
+
+s_and_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x86]
+
+s_and_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x86]
+
+s_and_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x86]
+
+s_and_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x86]
+
+s_and_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x86]
+
+s_and_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x86]
+
+s_and_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x86]
+
+s_and_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x86]
+
+s_and_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x86]
+
+s_and_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x86]
+
+s_and_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x86]
+
+s_and_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x86]
+
+s_and_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x86]
+
+s_and_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x86]
+
+s_and_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x86]
+
+s_and_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x86]
+
+s_and_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x86]
+
+s_and_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x86]
+
+s_and_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x86]
+
+s_and_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x86]
+
+s_and_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x86]
+
+s_and_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x86]
+
+s_and_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x86]
+
+s_and_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x86]
+
+s_and_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x86]
+
+s_and_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x86,0x56,0x34,0x12,0xaf]
+
+s_and_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x86,0x73,0x72,0x71,0x3f]
+
+s_and_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x86]
+
+s_and_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x86]
+
+s_and_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x86]
+
+s_and_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x86]
+
+s_and_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x86]
+
+s_and_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x86]
+
+s_and_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x86]
+
+s_and_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x86]
+
+s_and_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x86]
+
+s_and_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x86]
+
+s_and_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x86]
+
+s_and_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x86]
+
+s_and_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x86]
+
+s_and_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x86]
+
+s_and_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x86]
+
+s_and_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x86]
+
+s_and_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x86]
+
+s_and_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x86]
+
+s_and_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x86]
+
+s_and_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x86]
+
+s_and_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x86,0x56,0x34,0x12,0xaf]
+
+s_and_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x86,0x73,0x72,0x71,0x3f]
+
+s_and_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x86]
+
+s_and_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x86]
+
+s_and_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x86]
+
+s_and_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x86]
+
+s_and_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x86]
+
+s_and_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x86]
+
+s_and_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x86]
+
+s_and_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x86]
+
+s_and_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x86]
+
+s_and_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x86,0x56,0x34,0x12,0xaf]
+
+s_and_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x86,0x73,0x72,0x71,0x3f]
+
+s_and_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x86,0x56,0x34,0x12,0xaf]
+
+s_and_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x86,0x73,0x72,0x71,0x3f]
+
+s_or_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x87]
+
+s_or_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x87]
+
+s_or_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x87]
+
+s_or_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x87]
+
+s_or_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x87]
+
+s_or_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x87]
+
+s_or_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x87]
+
+s_or_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x87]
+
+s_or_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x87]
+
+s_or_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x87]
+
+s_or_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x87]
+
+s_or_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x87]
+
+s_or_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x87]
+
+s_or_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x87]
+
+s_or_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x87]
+
+s_or_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x87]
+
+s_or_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x87]
+
+s_or_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x87]
+
+s_or_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x87]
+
+s_or_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x87]
+
+s_or_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x87]
+
+s_or_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x87]
+
+s_or_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x87]
+
+s_or_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x87]
+
+s_or_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x87]
+
+s_or_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x87]
+
+s_or_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x87]
+
+s_or_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x87]
+
+s_or_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x87]
+
+s_or_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x87]
+
+s_or_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x87]
+
+s_or_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x87]
+
+s_or_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x87]
+
+s_or_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x87]
+
+s_or_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x87,0x56,0x34,0x12,0xaf]
+
+s_or_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x87,0x73,0x72,0x71,0x3f]
+
+s_or_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x87]
+
+s_or_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x87]
+
+s_or_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x87]
+
+s_or_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x87]
+
+s_or_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x87]
+
+s_or_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x87]
+
+s_or_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x87]
+
+s_or_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x87]
+
+s_or_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x87]
+
+s_or_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x87]
+
+s_or_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x87]
+
+s_or_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x87]
+
+s_or_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x87]
+
+s_or_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x87]
+
+s_or_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x87]
+
+s_or_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x87]
+
+s_or_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x87]
+
+s_or_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x87]
+
+s_or_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x87]
+
+s_or_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x87]
+
+s_or_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x87,0x56,0x34,0x12,0xaf]
+
+s_or_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x87,0x73,0x72,0x71,0x3f]
+
+s_or_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x87]
+
+s_or_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x87]
+
+s_or_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x87]
+
+s_or_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x87]
+
+s_or_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x87]
+
+s_or_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x87]
+
+s_or_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x87]
+
+s_or_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x87]
+
+s_or_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x87]
+
+s_or_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x87,0x56,0x34,0x12,0xaf]
+
+s_or_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x87,0x73,0x72,0x71,0x3f]
+
+s_or_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x87,0x56,0x34,0x12,0xaf]
+
+s_or_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x87,0x73,0x72,0x71,0x3f]
+
+s_xor_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x88]
+
+s_xor_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x88]
+
+s_xor_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x88]
+
+s_xor_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x88]
+
+s_xor_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x88]
+
+s_xor_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x88]
+
+s_xor_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x88]
+
+s_xor_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x88]
+
+s_xor_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x88]
+
+s_xor_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x88]
+
+s_xor_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x88]
+
+s_xor_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x88]
+
+s_xor_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x88]
+
+s_xor_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x88]
+
+s_xor_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x88]
+
+s_xor_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x88]
+
+s_xor_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x88]
+
+s_xor_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x88]
+
+s_xor_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x88]
+
+s_xor_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x88]
+
+s_xor_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x88]
+
+s_xor_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x88]
+
+s_xor_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x88]
+
+s_xor_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x88]
+
+s_xor_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x88]
+
+s_xor_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x88]
+
+s_xor_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x88]
+
+s_xor_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x88]
+
+s_xor_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x88]
+
+s_xor_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x88]
+
+s_xor_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x88]
+
+s_xor_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x88]
+
+s_xor_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x88]
+
+s_xor_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x88]
+
+s_xor_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x88,0x56,0x34,0x12,0xaf]
+
+s_xor_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x88,0x73,0x72,0x71,0x3f]
+
+s_xor_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x88]
+
+s_xor_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x88]
+
+s_xor_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x88]
+
+s_xor_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x88]
+
+s_xor_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x88]
+
+s_xor_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x88]
+
+s_xor_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x88]
+
+s_xor_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x88]
+
+s_xor_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x88]
+
+s_xor_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x88]
+
+s_xor_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x88]
+
+s_xor_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x88]
+
+s_xor_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x88]
+
+s_xor_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x88]
+
+s_xor_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x88]
+
+s_xor_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x88]
+
+s_xor_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x88]
+
+s_xor_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x88]
+
+s_xor_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x88]
+
+s_xor_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x88]
+
+s_xor_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x88,0x56,0x34,0x12,0xaf]
+
+s_xor_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x88,0x73,0x72,0x71,0x3f]
+
+s_xor_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x88]
+
+s_xor_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x88]
+
+s_xor_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x88]
+
+s_xor_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x88]
+
+s_xor_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x88]
+
+s_xor_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x88]
+
+s_xor_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x88]
+
+s_xor_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x88]
+
+s_xor_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x88]
+
+s_xor_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x88,0x56,0x34,0x12,0xaf]
+
+s_xor_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x88,0x73,0x72,0x71,0x3f]
+
+s_xor_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x88,0x56,0x34,0x12,0xaf]
+
+s_xor_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x88,0x73,0x72,0x71,0x3f]
+
+s_andn2_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x89]
+
+s_andn2_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x89]
+
+s_andn2_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x89]
+
+s_andn2_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x89]
+
+s_andn2_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x89]
+
+s_andn2_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x89]
+
+s_andn2_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x89]
+
+s_andn2_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x89]
+
+s_andn2_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x89]
+
+s_andn2_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x89]
+
+s_andn2_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x89]
+
+s_andn2_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x89]
+
+s_andn2_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x89]
+
+s_andn2_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x89]
+
+s_andn2_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x89]
+
+s_andn2_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x89]
+
+s_andn2_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x89]
+
+s_andn2_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x89]
+
+s_andn2_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x89]
+
+s_andn2_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x89]
+
+s_andn2_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x89]
+
+s_andn2_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x89]
+
+s_andn2_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x89]
+
+s_andn2_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x89]
+
+s_andn2_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x89]
+
+s_andn2_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x89]
+
+s_andn2_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x89]
+
+s_andn2_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x89]
+
+s_andn2_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x89]
+
+s_andn2_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x89]
+
+s_andn2_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x89]
+
+s_andn2_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x89]
+
+s_andn2_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x89]
+
+s_andn2_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x89]
+
+s_andn2_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x89,0x56,0x34,0x12,0xaf]
+
+s_andn2_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x89,0x73,0x72,0x71,0x3f]
+
+s_andn2_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x89]
+
+s_andn2_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x89]
+
+s_andn2_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x89]
+
+s_andn2_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x89]
+
+s_andn2_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x89]
+
+s_andn2_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x89]
+
+s_andn2_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x89]
+
+s_andn2_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x89]
+
+s_andn2_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x89]
+
+s_andn2_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x89]
+
+s_andn2_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x89]
+
+s_andn2_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x89]
+
+s_andn2_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x89]
+
+s_andn2_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x89]
+
+s_andn2_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x89]
+
+s_andn2_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x89]
+
+s_andn2_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x89]
+
+s_andn2_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x89]
+
+s_andn2_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x89]
+
+s_andn2_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x89]
+
+s_andn2_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x89,0x56,0x34,0x12,0xaf]
+
+s_andn2_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x89,0x73,0x72,0x71,0x3f]
+
+s_andn2_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x89]
+
+s_andn2_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x89]
+
+s_andn2_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x89]
+
+s_andn2_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x89]
+
+s_andn2_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x89]
+
+s_andn2_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x89]
+
+s_andn2_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x89]
+
+s_andn2_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x89]
+
+s_andn2_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x89]
+
+s_andn2_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x89,0x56,0x34,0x12,0xaf]
+
+s_andn2_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x89,0x73,0x72,0x71,0x3f]
+
+s_andn2_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x89,0x56,0x34,0x12,0xaf]
+
+s_andn2_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x89,0x73,0x72,0x71,0x3f]
+
+s_orn2_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8a]
+
+s_orn2_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8a]
+
+s_orn2_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8a]
+
+s_orn2_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8a]
+
+s_orn2_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8a]
+
+s_orn2_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8a]
+
+s_orn2_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8a]
+
+s_orn2_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8a]
+
+s_orn2_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8a]
+
+s_orn2_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8a]
+
+s_orn2_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8a]
+
+s_orn2_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8a]
+
+s_orn2_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8a]
+
+s_orn2_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8a]
+
+s_orn2_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8a,0x56,0x34,0x12,0xaf]
+
+s_orn2_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8a,0x73,0x72,0x71,0x3f]
+
+s_orn2_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8a]
+
+s_orn2_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8a]
+
+s_orn2_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8a]
+
+s_orn2_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8a]
+
+s_orn2_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8a]
+
+s_orn2_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8a]
+
+s_orn2_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8a]
+
+s_orn2_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8a]
+
+s_orn2_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8a]
+
+s_orn2_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8a]
+
+s_orn2_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8a]
+
+s_orn2_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8a]
+
+s_orn2_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8a]
+
+s_orn2_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8a]
+
+s_orn2_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8a]
+
+s_orn2_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8a]
+
+s_orn2_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8a]
+
+s_orn2_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8a]
+
+s_orn2_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8a]
+
+s_orn2_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8a]
+
+s_orn2_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8a,0x56,0x34,0x12,0xaf]
+
+s_orn2_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8a,0x73,0x72,0x71,0x3f]
+
+s_orn2_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8a]
+
+s_orn2_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x8a]
+
+s_orn2_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8a]
+
+s_orn2_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8a]
+
+s_orn2_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x8a]
+
+s_orn2_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x8a]
+
+s_orn2_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8a]
+
+s_orn2_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8a]
+
+s_orn2_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8a,0x56,0x34,0x12,0xaf]
+
+s_orn2_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8a,0x73,0x72,0x71,0x3f]
+
+s_orn2_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8a,0x56,0x34,0x12,0xaf]
+
+s_orn2_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8a,0x73,0x72,0x71,0x3f]
+
+s_nand_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8b]
+
+s_nand_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8b]
+
+s_nand_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8b]
+
+s_nand_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8b]
+
+s_nand_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8b]
+
+s_nand_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8b]
+
+s_nand_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8b]
+
+s_nand_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8b]
+
+s_nand_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8b]
+
+s_nand_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8b]
+
+s_nand_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8b]
+
+s_nand_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8b]
+
+s_nand_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8b]
+
+s_nand_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8b]
+
+s_nand_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8b]
+
+s_nand_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8b]
+
+s_nand_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8b]
+
+s_nand_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8b]
+
+s_nand_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8b]
+
+s_nand_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8b]
+
+s_nand_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8b]
+
+s_nand_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8b]
+
+s_nand_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8b]
+
+s_nand_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8b]
+
+s_nand_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8b]
+
+s_nand_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8b]
+
+s_nand_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8b]
+
+s_nand_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8b]
+
+s_nand_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8b]
+
+s_nand_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8b]
+
+s_nand_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8b]
+
+s_nand_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8b]
+
+s_nand_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8b]
+
+s_nand_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8b]
+
+s_nand_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8b,0x56,0x34,0x12,0xaf]
+
+s_nand_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8b,0x73,0x72,0x71,0x3f]
+
+s_nand_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8b]
+
+s_nand_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8b]
+
+s_nand_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8b]
+
+s_nand_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8b]
+
+s_nand_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8b]
+
+s_nand_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8b]
+
+s_nand_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8b]
+
+s_nand_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8b]
+
+s_nand_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8b]
+
+s_nand_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8b]
+
+s_nand_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8b]
+
+s_nand_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8b]
+
+s_nand_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8b]
+
+s_nand_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8b]
+
+s_nand_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8b]
+
+s_nand_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8b]
+
+s_nand_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8b]
+
+s_nand_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8b]
+
+s_nand_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8b]
+
+s_nand_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8b]
+
+s_nand_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8b,0x56,0x34,0x12,0xaf]
+
+s_nand_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8b,0x73,0x72,0x71,0x3f]
+
+s_nand_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8b]
+
+s_nand_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8b]
+
+s_nand_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x8b]
+
+s_nand_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8b]
+
+s_nand_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8b]
+
+s_nand_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x8b]
+
+s_nand_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x8b]
+
+s_nand_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8b]
+
+s_nand_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8b]
+
+s_nand_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8b,0x56,0x34,0x12,0xaf]
+
+s_nand_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8b,0x73,0x72,0x71,0x3f]
+
+s_nand_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8b,0x56,0x34,0x12,0xaf]
+
+s_nand_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8b,0x73,0x72,0x71,0x3f]
+
+s_nor_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8c]
+
+s_nor_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8c]
+
+s_nor_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8c]
+
+s_nor_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8c]
+
+s_nor_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8c]
+
+s_nor_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8c]
+
+s_nor_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8c]
+
+s_nor_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8c]
+
+s_nor_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8c]
+
+s_nor_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8c]
+
+s_nor_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8c]
+
+s_nor_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8c]
+
+s_nor_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8c]
+
+s_nor_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8c]
+
+s_nor_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8c]
+
+s_nor_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8c]
+
+s_nor_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8c]
+
+s_nor_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8c]
+
+s_nor_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8c]
+
+s_nor_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8c]
+
+s_nor_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8c]
+
+s_nor_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8c]
+
+s_nor_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8c]
+
+s_nor_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8c]
+
+s_nor_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8c]
+
+s_nor_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8c]
+
+s_nor_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8c]
+
+s_nor_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8c]
+
+s_nor_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8c]
+
+s_nor_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8c]
+
+s_nor_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8c]
+
+s_nor_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8c]
+
+s_nor_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8c]
+
+s_nor_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8c]
+
+s_nor_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nor_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nor_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8c]
+
+s_nor_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8c]
+
+s_nor_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8c]
+
+s_nor_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8c]
+
+s_nor_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8c]
+
+s_nor_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8c]
+
+s_nor_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8c]
+
+s_nor_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8c]
+
+s_nor_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8c]
+
+s_nor_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8c]
+
+s_nor_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8c]
+
+s_nor_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8c]
+
+s_nor_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8c]
+
+s_nor_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8c]
+
+s_nor_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8c]
+
+s_nor_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8c]
+
+s_nor_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8c]
+
+s_nor_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8c]
+
+s_nor_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8c]
+
+s_nor_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8c]
+
+s_nor_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nor_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nor_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8c]
+
+s_nor_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8c]
+
+s_nor_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x8c]
+
+s_nor_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8c]
+
+s_nor_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8c]
+
+s_nor_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x8c]
+
+s_nor_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x8c]
+
+s_nor_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8c]
+
+s_nor_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8c]
+
+s_nor_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nor_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nor_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nor_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8c,0x73,0x72,0x71,0x3f]
+
+s_xnor_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8d]
+
+s_xnor_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8d]
+
+s_xnor_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8d]
+
+s_xnor_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8d]
+
+s_xnor_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8d]
+
+s_xnor_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8d]
+
+s_xnor_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8d]
+
+s_xnor_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8d]
+
+s_xnor_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8d]
+
+s_xnor_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8d]
+
+s_xnor_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8d]
+
+s_xnor_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8d]
+
+s_xnor_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8d]
+
+s_xnor_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8d]
+
+s_xnor_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8d,0x56,0x34,0x12,0xaf]
+
+s_xnor_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8d,0x73,0x72,0x71,0x3f]
+
+s_xnor_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8d]
+
+s_xnor_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8d]
+
+s_xnor_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8d]
+
+s_xnor_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8d]
+
+s_xnor_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8d]
+
+s_xnor_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8d]
+
+s_xnor_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8d]
+
+s_xnor_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8d]
+
+s_xnor_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8d]
+
+s_xnor_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8d]
+
+s_xnor_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8d]
+
+s_xnor_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8d]
+
+s_xnor_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8d]
+
+s_xnor_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8d]
+
+s_xnor_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8d]
+
+s_xnor_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8d]
+
+s_xnor_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8d]
+
+s_xnor_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8d]
+
+s_xnor_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8d]
+
+s_xnor_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8d]
+
+s_xnor_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8d,0x56,0x34,0x12,0xaf]
+
+s_xnor_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8d,0x73,0x72,0x71,0x3f]
+
+s_xnor_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8d]
+
+s_xnor_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x8d]
+
+s_xnor_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8d]
+
+s_xnor_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8d]
+
+s_xnor_b64 tba, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xec,0x8d]
+
+s_xnor_b64 tma, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xee,0x8d]
+
+s_xnor_b64 ttmp[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8d]
+
+s_xnor_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8d]
+
+s_xnor_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], tba, s[4:5]
+// CHECK: [0x6c,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], tma, s[4:5]
+// CHECK: [0x6e,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8d,0x56,0x34,0x12,0xaf]
+
+s_xnor_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8d,0x73,0x72,0x71,0x3f]
+
+s_xnor_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], tba
+// CHECK: [0x02,0x6c,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], tma
+// CHECK: [0x02,0x6e,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8d,0x56,0x34,0x12,0xaf]
+
+s_xnor_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8d,0x73,0x72,0x71,0x3f]
+
+s_lshl_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8e]
+
+s_lshl_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8e]
+
+s_lshl_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8e]
+
+s_lshl_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8e]
+
+s_lshl_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8e]
+
+s_lshl_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8e]
+
+s_lshl_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8e]
+
+s_lshl_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8e]
+
+s_lshl_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8e]
+
+s_lshl_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8e]
+
+s_lshl_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8e]
+
+s_lshl_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8e]
+
+s_lshl_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8e]
+
+s_lshl_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8e]
+
+s_lshl_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8e,0x56,0x34,0x12,0xaf]
+
+s_lshl_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8e,0x73,0x72,0x71,0x3f]
+
+s_lshl_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8e]
+
+s_lshl_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8e]
+
+s_lshl_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8e]
+
+s_lshl_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8e]
+
+s_lshl_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8e]
+
+s_lshl_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8e]
+
+s_lshl_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8e]
+
+s_lshl_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8e]
+
+s_lshl_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8e]
+
+s_lshl_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8e]
+
+s_lshl_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8e]
+
+s_lshl_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8e]
+
+s_lshl_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8e]
+
+s_lshl_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8e]
+
+s_lshl_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8e]
+
+s_lshl_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8e]
+
+s_lshl_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8e]
+
+s_lshl_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8e]
+
+s_lshl_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8e]
+
+s_lshl_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8e]
+
+s_lshl_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8e,0x56,0x34,0x12,0xaf]
+
+s_lshl_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8e,0x73,0x72,0x71,0x3f]
+
+s_lshl_b64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x8e]
+
+s_lshl_b64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0xe4,0x8e]
+
+s_lshl_b64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x8e]
+
+s_lshl_b64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x8e]
+
+s_lshl_b64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0xec,0x8e]
+
+s_lshl_b64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0xee,0x8e]
+
+s_lshl_b64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x8e]
+
+s_lshl_b64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x8e]
+
+s_lshl_b64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x8e,0x56,0x34,0x12,0xaf]
+
+s_lshl_b64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x8e,0x73,0x72,0x71,0x3f]
+
+s_lshl_b64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8e,0x56,0x34,0x12,0xaf]
+
+s_lshl_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8e,0x73,0x72,0x71,0x3f]
+
+s_lshr_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8f]
+
+s_lshr_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8f]
+
+s_lshr_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8f]
+
+s_lshr_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8f]
+
+s_lshr_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8f]
+
+s_lshr_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8f]
+
+s_lshr_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x8f]
+
+s_lshr_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x8f]
+
+s_lshr_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x8f]
+
+s_lshr_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x8f]
+
+s_lshr_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8f]
+
+s_lshr_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8f]
+
+s_lshr_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8f]
+
+s_lshr_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8f]
+
+s_lshr_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshr_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshr_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8f]
+
+s_lshr_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8f]
+
+s_lshr_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8f]
+
+s_lshr_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8f]
+
+s_lshr_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8f]
+
+s_lshr_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x8f]
+
+s_lshr_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x8f]
+
+s_lshr_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x8f]
+
+s_lshr_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x8f]
+
+s_lshr_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x8f]
+
+s_lshr_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8f]
+
+s_lshr_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8f]
+
+s_lshr_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8f]
+
+s_lshr_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8f]
+
+s_lshr_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8f]
+
+s_lshr_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8f]
+
+s_lshr_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8f]
+
+s_lshr_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8f]
+
+s_lshr_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8f]
+
+s_lshr_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8f]
+
+s_lshr_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshr_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshr_b64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x8f]
+
+s_lshr_b64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0xe4,0x8f]
+
+s_lshr_b64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x8f]
+
+s_lshr_b64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x8f]
+
+s_lshr_b64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0xec,0x8f]
+
+s_lshr_b64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0xee,0x8f]
+
+s_lshr_b64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x8f]
+
+s_lshr_b64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x8f]
+
+s_lshr_b64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshr_b64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshr_b64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshr_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8f,0x73,0x72,0x71,0x3f]
+
+s_ashr_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x90]
+
+s_ashr_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x90]
+
+s_ashr_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x90]
+
+s_ashr_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x90]
+
+s_ashr_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x90]
+
+s_ashr_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x90]
+
+s_ashr_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x90]
+
+s_ashr_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x90]
+
+s_ashr_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x90]
+
+s_ashr_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x90]
+
+s_ashr_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x90]
+
+s_ashr_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x90]
+
+s_ashr_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x90]
+
+s_ashr_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x90]
+
+s_ashr_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x90]
+
+s_ashr_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x90]
+
+s_ashr_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x90]
+
+s_ashr_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x90]
+
+s_ashr_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x90]
+
+s_ashr_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x90]
+
+s_ashr_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x90]
+
+s_ashr_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x90]
+
+s_ashr_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x90]
+
+s_ashr_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x90]
+
+s_ashr_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x90]
+
+s_ashr_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x90]
+
+s_ashr_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x90]
+
+s_ashr_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x90]
+
+s_ashr_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x90]
+
+s_ashr_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x90]
+
+s_ashr_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x90]
+
+s_ashr_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x90]
+
+s_ashr_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x90]
+
+s_ashr_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x90]
+
+s_ashr_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x90,0x56,0x34,0x12,0xaf]
+
+s_ashr_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x90,0x73,0x72,0x71,0x3f]
+
+s_ashr_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x90]
+
+s_ashr_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x90]
+
+s_ashr_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x90]
+
+s_ashr_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x90]
+
+s_ashr_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x90]
+
+s_ashr_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x90]
+
+s_ashr_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x90]
+
+s_ashr_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x90]
+
+s_ashr_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x90]
+
+s_ashr_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x90]
+
+s_ashr_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x90]
+
+s_ashr_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x90]
+
+s_ashr_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x90]
+
+s_ashr_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x90]
+
+s_ashr_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x90]
+
+s_ashr_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x90]
+
+s_ashr_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x90]
+
+s_ashr_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x90]
+
+s_ashr_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x90]
+
+s_ashr_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x90]
+
+s_ashr_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x90,0x56,0x34,0x12,0xaf]
+
+s_ashr_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x90,0x73,0x72,0x71,0x3f]
+
+s_ashr_i64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x90]
+
+s_ashr_i64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x90]
+
+s_ashr_i64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0xe4,0x90]
+
+s_ashr_i64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x90]
+
+s_ashr_i64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x90]
+
+s_ashr_i64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0xec,0x90]
+
+s_ashr_i64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0xee,0x90]
+
+s_ashr_i64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x90]
+
+s_ashr_i64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x90]
+
+s_ashr_i64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x90,0x56,0x34,0x12,0xaf]
+
+s_ashr_i64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x90,0x73,0x72,0x71,0x3f]
+
+s_ashr_i64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x90,0x56,0x34,0x12,0xaf]
+
+s_ashr_i64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x90,0x73,0x72,0x71,0x3f]
+
+s_bfm_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x91]
+
+s_bfm_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x91]
+
+s_bfm_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x91]
+
+s_bfm_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x91]
+
+s_bfm_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x91]
+
+s_bfm_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x91]
+
+s_bfm_b32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x91]
+
+s_bfm_b32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x91]
+
+s_bfm_b32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x91]
+
+s_bfm_b32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x91]
+
+s_bfm_b32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x91]
+
+s_bfm_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x91]
+
+s_bfm_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x91]
+
+s_bfm_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x91]
+
+s_bfm_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x91]
+
+s_bfm_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x91]
+
+s_bfm_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x91]
+
+s_bfm_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x91]
+
+s_bfm_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x91]
+
+s_bfm_b32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x91]
+
+s_bfm_b32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x91]
+
+s_bfm_b32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x91]
+
+s_bfm_b32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x91]
+
+s_bfm_b32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x91]
+
+s_bfm_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x91]
+
+s_bfm_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x91]
+
+s_bfm_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x91]
+
+s_bfm_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x91]
+
+s_bfm_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x91]
+
+s_bfm_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x91]
+
+s_bfm_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x91]
+
+s_bfm_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x91]
+
+s_bfm_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x91]
+
+s_bfm_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x91]
+
+s_bfm_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x91,0x56,0x34,0x12,0xaf]
+
+s_bfm_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x91,0x73,0x72,0x71,0x3f]
+
+s_bfm_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x91]
+
+s_bfm_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x91]
+
+s_bfm_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x91]
+
+s_bfm_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x91]
+
+s_bfm_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x91]
+
+s_bfm_b32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x91]
+
+s_bfm_b32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x91]
+
+s_bfm_b32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x91]
+
+s_bfm_b32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x91]
+
+s_bfm_b32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x91]
+
+s_bfm_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x91]
+
+s_bfm_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x91]
+
+s_bfm_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x91]
+
+s_bfm_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x91]
+
+s_bfm_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x91]
+
+s_bfm_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x91]
+
+s_bfm_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x91]
+
+s_bfm_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x91]
+
+s_bfm_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x91]
+
+s_bfm_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x91]
+
+s_bfm_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x91,0x56,0x34,0x12,0xaf]
+
+s_bfm_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x91,0x73,0x72,0x71,0x3f]
+
+s_bfm_b64 s[10:11], s1, s2
+// CHECK: [0x01,0x02,0x8a,0x91]
+
+s_bfm_b64 s[12:13], s1, s2
+// CHECK: [0x01,0x02,0x8c,0x91]
+
+s_bfm_b64 s[100:101], s1, s2
+// CHECK: [0x01,0x02,0xe4,0x91]
+
+s_bfm_b64 flat_scratch, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x91]
+
+s_bfm_b64 vcc, s1, s2
+// CHECK: [0x01,0x02,0xea,0x91]
+
+s_bfm_b64 tba, s1, s2
+// CHECK: [0x01,0x02,0xec,0x91]
+
+s_bfm_b64 tma, s1, s2
+// CHECK: [0x01,0x02,0xee,0x91]
+
+s_bfm_b64 ttmp[10:11], s1, s2
+// CHECK: [0x01,0x02,0xfa,0x91]
+
+s_bfm_b64 exec, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x91]
+
+s_bfm_b64 s[10:11], s101, s2
+// CHECK: [0x65,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], vcc_lo, s2
+// CHECK: [0x6a,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], vcc_hi, s2
+// CHECK: [0x6b,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], tba_lo, s2
+// CHECK: [0x6c,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], tba_hi, s2
+// CHECK: [0x6d,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], tma_lo, s2
+// CHECK: [0x6e,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], tma_hi, s2
+// CHECK: [0x6f,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], ttmp11, s2
+// CHECK: [0x7b,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], m0, s2
+// CHECK: [0x7c,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], exec_lo, s2
+// CHECK: [0x7e,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], exec_hi, s2
+// CHECK: [0x7f,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x91,0x56,0x34,0x12,0xaf]
+
+s_bfm_b64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x91,0x73,0x72,0x71,0x3f]
+
+s_bfm_b64 s[10:11], s1, s101
+// CHECK: [0x01,0x65,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, vcc_lo
+// CHECK: [0x01,0x6a,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, vcc_hi
+// CHECK: [0x01,0x6b,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, tba_lo
+// CHECK: [0x01,0x6c,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, tba_hi
+// CHECK: [0x01,0x6d,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, tma_lo
+// CHECK: [0x01,0x6e,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, tma_hi
+// CHECK: [0x01,0x6f,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, ttmp11
+// CHECK: [0x01,0x7b,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, m0
+// CHECK: [0x01,0x7c,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, exec_lo
+// CHECK: [0x01,0x7e,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, exec_hi
+// CHECK: [0x01,0x7f,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, 0
+// CHECK: [0x01,0x80,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, -1
+// CHECK: [0x01,0xc1,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, 0.5
+// CHECK: [0x01,0xf0,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, -4.0
+// CHECK: [0x01,0xf7,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, src_vccz
+// CHECK: [0x01,0xfb,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, src_execz
+// CHECK: [0x01,0xfc,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, src_scc
+// CHECK: [0x01,0xfd,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, 0xaf123456
+// CHECK: [0x01,0xff,0x8a,0x91,0x56,0x34,0x12,0xaf]
+
+s_bfm_b64 s[10:11], s1, 0x3f717273
+// CHECK: [0x01,0xff,0x8a,0x91,0x73,0x72,0x71,0x3f]
+
+s_mul_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x92]
+
+s_mul_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x92]
+
+s_mul_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x92]
+
+s_mul_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x92]
+
+s_mul_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x92]
+
+s_mul_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x92]
+
+s_mul_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x92]
+
+s_mul_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x92]
+
+s_mul_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x92]
+
+s_mul_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x92]
+
+s_mul_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x92]
+
+s_mul_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x92]
+
+s_mul_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x92]
+
+s_mul_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x92]
+
+s_mul_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x92]
+
+s_mul_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x92]
+
+s_mul_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x92]
+
+s_mul_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x92]
+
+s_mul_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x92]
+
+s_mul_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x92]
+
+s_mul_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x92]
+
+s_mul_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x92]
+
+s_mul_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x92]
+
+s_mul_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x92]
+
+s_mul_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x92]
+
+s_mul_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x92]
+
+s_mul_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x92]
+
+s_mul_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x92]
+
+s_mul_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x92]
+
+s_mul_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x92]
+
+s_mul_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x92]
+
+s_mul_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x92]
+
+s_mul_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x92]
+
+s_mul_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x92]
+
+s_mul_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x92,0x56,0x34,0x12,0xaf]
+
+s_mul_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x92,0x73,0x72,0x71,0x3f]
+
+s_mul_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x92]
+
+s_mul_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x92]
+
+s_mul_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x92]
+
+s_mul_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x92]
+
+s_mul_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x92]
+
+s_mul_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x92]
+
+s_mul_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x92]
+
+s_mul_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x92]
+
+s_mul_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x92]
+
+s_mul_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x92]
+
+s_mul_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x92]
+
+s_mul_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x92]
+
+s_mul_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x92]
+
+s_mul_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x92]
+
+s_mul_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x92]
+
+s_mul_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x92]
+
+s_mul_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x92]
+
+s_mul_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x92]
+
+s_mul_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x92]
+
+s_mul_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x92]
+
+s_mul_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x92,0x56,0x34,0x12,0xaf]
+
+s_mul_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfe_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x92]
+
+s_bfe_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x92]
+
+s_bfe_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x92]
+
+s_bfe_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x92]
+
+s_bfe_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x92]
+
+s_bfe_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x92]
+
+s_bfe_u32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0xec,0x92]
+
+s_bfe_u32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0xed,0x92]
+
+s_bfe_u32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0xee,0x92]
+
+s_bfe_u32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0xef,0x92]
+
+s_bfe_u32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x92]
+
+s_bfe_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x92]
+
+s_bfe_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x92]
+
+s_bfe_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x92]
+
+s_bfe_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x92]
+
+s_bfe_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x92]
+
+s_bfe_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x92]
+
+s_bfe_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x92]
+
+s_bfe_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x92]
+
+s_bfe_u32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x85,0x92]
+
+s_bfe_u32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x85,0x92]
+
+s_bfe_u32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x85,0x92]
+
+s_bfe_u32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x85,0x92]
+
+s_bfe_u32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x85,0x92]
+
+s_bfe_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x92]
+
+s_bfe_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x92]
+
+s_bfe_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x92]
+
+s_bfe_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x92]
+
+s_bfe_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x92]
+
+s_bfe_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x92]
+
+s_bfe_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x92]
+
+s_bfe_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x92]
+
+s_bfe_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x92]
+
+s_bfe_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x92]
+
+s_bfe_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfe_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfe_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x92]
+
+s_bfe_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x92]
+
+s_bfe_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x92]
+
+s_bfe_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x92]
+
+s_bfe_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x92]
+
+s_bfe_u32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x85,0x92]
+
+s_bfe_u32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x85,0x92]
+
+s_bfe_u32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x85,0x92]
+
+s_bfe_u32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x85,0x92]
+
+s_bfe_u32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x85,0x92]
+
+s_bfe_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x92]
+
+s_bfe_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x92]
+
+s_bfe_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x92]
+
+s_bfe_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x92]
+
+s_bfe_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x92]
+
+s_bfe_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x92]
+
+s_bfe_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x92]
+
+s_bfe_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x92]
+
+s_bfe_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x92]
+
+s_bfe_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x92]
+
+s_bfe_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfe_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfe_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x93]
+
+s_bfe_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x93]
+
+s_bfe_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x93]
+
+s_bfe_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x93]
+
+s_bfe_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x93]
+
+s_bfe_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x93]
+
+s_bfe_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x93]
+
+s_bfe_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x93]
+
+s_bfe_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x93]
+
+s_bfe_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x93]
+
+s_bfe_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x93]
+
+s_bfe_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x93]
+
+s_bfe_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x93]
+
+s_bfe_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x93]
+
+s_bfe_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x93]
+
+s_bfe_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x93]
+
+s_bfe_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x93]
+
+s_bfe_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x93]
+
+s_bfe_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x93]
+
+s_bfe_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x93]
+
+s_bfe_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x93]
+
+s_bfe_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x93]
+
+s_bfe_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x93]
+
+s_bfe_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x93]
+
+s_bfe_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x93]
+
+s_bfe_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x93]
+
+s_bfe_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x93]
+
+s_bfe_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x93]
+
+s_bfe_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x93]
+
+s_bfe_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x93]
+
+s_bfe_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x93]
+
+s_bfe_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x93]
+
+s_bfe_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x93]
+
+s_bfe_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x93]
+
+s_bfe_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x93]
+
+s_bfe_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x93]
+
+s_bfe_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x93]
+
+s_bfe_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x93]
+
+s_bfe_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x93]
+
+s_bfe_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x93]
+
+s_bfe_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x93]
+
+s_bfe_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x93]
+
+s_bfe_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x93]
+
+s_bfe_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x93]
+
+s_bfe_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x93]
+
+s_bfe_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x93]
+
+s_bfe_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x93]
+
+s_bfe_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x93]
+
+s_bfe_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x93]
+
+s_bfe_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x93]
+
+s_bfe_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x93]
+
+s_bfe_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x93]
+
+s_bfe_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x93]
+
+s_bfe_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x93]
+
+s_bfe_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_u64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x93]
+
+s_bfe_u64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x93]
+
+s_bfe_u64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0xe4,0x93]
+
+s_bfe_u64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x93]
+
+s_bfe_u64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x93]
+
+s_bfe_u64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0xec,0x93]
+
+s_bfe_u64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0xee,0x93]
+
+s_bfe_u64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x93]
+
+s_bfe_u64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x93]
+
+s_bfe_u64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_u64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_u64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_u64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_i64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x0a,0x94]
+
+s_bfe_i64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x0c,0x94]
+
+s_bfe_i64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0x64,0x94]
+
+s_bfe_i64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0x66,0x94]
+
+s_bfe_i64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0x6a,0x94]
+
+s_bfe_i64 tba, s[2:3], s2
+// CHECK: [0x02,0x02,0x6c,0x94]
+
+s_bfe_i64 tma, s[2:3], s2
+// CHECK: [0x02,0x02,0x6e,0x94]
+
+s_bfe_i64 ttmp[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x7a,0x94]
+
+s_bfe_i64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0x7e,0x94]
+
+s_bfe_i64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], tba, s2
+// CHECK: [0x6c,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], tma, s2
+// CHECK: [0x6e,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0a,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_i64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0a,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_i64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x0a,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_i64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x0a,0x94,0x73,0x72,0x71,0x3f]
+
+s_cbranch_g_fork s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x80,0x94]
+
+s_cbranch_g_fork s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x80,0x94]
+
+s_cbranch_g_fork s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x80,0x94]
+
+s_cbranch_g_fork flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x80,0x94]
+
+s_cbranch_g_fork vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x80,0x94]
+
+s_cbranch_g_fork tba, s[4:5]
+// CHECK: [0x6c,0x04,0x80,0x94]
+
+s_cbranch_g_fork tma, s[4:5]
+// CHECK: [0x6e,0x04,0x80,0x94]
+
+s_cbranch_g_fork ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x80,0x94]
+
+s_cbranch_g_fork exec, s[4:5]
+// CHECK: [0x7e,0x04,0x80,0x94]
+
+s_cbranch_g_fork 0, s[4:5]
+// CHECK: [0x80,0x04,0x80,0x94]
+
+s_cbranch_g_fork -1, s[4:5]
+// CHECK: [0xc1,0x04,0x80,0x94]
+
+s_cbranch_g_fork 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x80,0x94]
+
+s_cbranch_g_fork -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x80,0x94]
+
+s_cbranch_g_fork src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x80,0x94]
+
+s_cbranch_g_fork src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x80,0x94]
+
+s_cbranch_g_fork src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], vcc
+// CHECK: [0x02,0x6a,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], tba
+// CHECK: [0x02,0x6c,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], tma
+// CHECK: [0x02,0x6e,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], exec
+// CHECK: [0x02,0x7e,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], 0
+// CHECK: [0x02,0x80,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], -1
+// CHECK: [0x02,0xc1,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x80,0x94]
+
+s_absdiff_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x95]
+
+s_absdiff_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x95]
+
+s_absdiff_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x95]
+
+s_absdiff_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x95]
+
+s_absdiff_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x95]
+
+s_absdiff_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x95]
+
+s_absdiff_i32 tba_lo, s1, s2
+// CHECK: [0x01,0x02,0x6c,0x95]
+
+s_absdiff_i32 tba_hi, s1, s2
+// CHECK: [0x01,0x02,0x6d,0x95]
+
+s_absdiff_i32 tma_lo, s1, s2
+// CHECK: [0x01,0x02,0x6e,0x95]
+
+s_absdiff_i32 tma_hi, s1, s2
+// CHECK: [0x01,0x02,0x6f,0x95]
+
+s_absdiff_i32 ttmp11, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x95]
+
+s_absdiff_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x95]
+
+s_absdiff_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x95]
+
+s_absdiff_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x95]
+
+s_absdiff_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x95,0x56,0x34,0x12,0xaf]
+
+s_absdiff_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x95,0x73,0x72,0x71,0x3f]
+
+s_absdiff_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x95]
+
+s_absdiff_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x95]
+
+s_absdiff_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x95]
+
+s_absdiff_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x95]
+
+s_absdiff_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x95]
+
+s_absdiff_i32 s5, s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0x95]
+
+s_absdiff_i32 s5, s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0x95]
+
+s_absdiff_i32 s5, s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0x95]
+
+s_absdiff_i32 s5, s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0x95]
+
+s_absdiff_i32 s5, s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0x95]
+
+s_absdiff_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x95]
+
+s_absdiff_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x95]
+
+s_absdiff_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x95]
+
+s_absdiff_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x95]
+
+s_absdiff_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x95]
+
+s_absdiff_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x95]
+
+s_absdiff_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x95]
+
+s_absdiff_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x95]
+
+s_absdiff_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x95]
+
+s_absdiff_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x95]
+
+s_absdiff_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x95,0x56,0x34,0x12,0xaf]
+
+s_absdiff_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x95,0x73,0x72,0x71,0x3f]
+
+s_rfe_restore_b64 s[2:3], s2
+// CHECK: [0x02,0x02,0x80,0x95]
+
+s_rfe_restore_b64 s[4:5], s2
+// CHECK: [0x04,0x02,0x80,0x95]
+
+s_rfe_restore_b64 s[100:101], s2
+// CHECK: [0x64,0x02,0x80,0x95]
+
+s_rfe_restore_b64 flat_scratch, s2
+// CHECK: [0x66,0x02,0x80,0x95]
+
+s_rfe_restore_b64 vcc, s2
+// CHECK: [0x6a,0x02,0x80,0x95]
+
+s_rfe_restore_b64 tba, s2
+// CHECK: [0x6c,0x02,0x80,0x95]
+
+s_rfe_restore_b64 tma, s2
+// CHECK: [0x6e,0x02,0x80,0x95]
+
+s_rfe_restore_b64 ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x80,0x95]
+
+s_rfe_restore_b64 exec, s2
+// CHECK: [0x7e,0x02,0x80,0x95]
+
+s_rfe_restore_b64 0, s2
+// CHECK: [0x80,0x02,0x80,0x95]
+
+s_rfe_restore_b64 -1, s2
+// CHECK: [0xc1,0x02,0x80,0x95]
+
+s_rfe_restore_b64 0.5, s2
+// CHECK: [0xf0,0x02,0x80,0x95]
+
+s_rfe_restore_b64 -4.0, s2
+// CHECK: [0xf7,0x02,0x80,0x95]
+
+s_rfe_restore_b64 src_vccz, s2
+// CHECK: [0xfb,0x02,0x80,0x95]
+
+s_rfe_restore_b64 src_execz, s2
+// CHECK: [0xfc,0x02,0x80,0x95]
+
+s_rfe_restore_b64 src_scc, s2
+// CHECK: [0xfd,0x02,0x80,0x95]
+
+s_rfe_restore_b64 0xaf123456, s2
+// CHECK: [0xff,0x02,0x80,0x95,0x56,0x34,0x12,0xaf]
+
+s_rfe_restore_b64 0x3f717273, s2
+// CHECK: [0xff,0x02,0x80,0x95,0x73,0x72,0x71,0x3f]
+
+s_rfe_restore_b64 s[2:3], s101
+// CHECK: [0x02,0x65,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], m0
+// CHECK: [0x02,0x7c,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], 0
+// CHECK: [0x02,0x80,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x80,0x95,0x56,0x34,0x12,0xaf]
+
+s_rfe_restore_b64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x80,0x95,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx8_asm_sopc.s
new file mode 100644
index 0000000000000..c6a6a9bc8b9ed
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sopc.s
@@ -0,0 +1,2545 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+s_cmp_eq_i32 s1, s2
+// CHECK: [0x01,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 s101, s2
+// CHECK: [0x65,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 m0, s2
+// CHECK: [0x7c,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 0, s2
+// CHECK: [0x80,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 -1, s2
+// CHECK: [0xc1,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x00,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x00,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_i32 s1, s101
+// CHECK: [0x01,0x65,0x00,0xbf]
+
+s_cmp_eq_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x00,0xbf]
+
+s_cmp_eq_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x00,0xbf]
+
+s_cmp_eq_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x00,0xbf]
+
+s_cmp_eq_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x00,0xbf]
+
+s_cmp_eq_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x00,0xbf]
+
+s_cmp_eq_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x00,0xbf]
+
+s_cmp_eq_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x00,0xbf]
+
+s_cmp_eq_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x00,0xbf]
+
+s_cmp_eq_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x00,0xbf]
+
+s_cmp_eq_i32 s1, m0
+// CHECK: [0x01,0x7c,0x00,0xbf]
+
+s_cmp_eq_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x00,0xbf]
+
+s_cmp_eq_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x00,0xbf]
+
+s_cmp_eq_i32 s1, 0
+// CHECK: [0x01,0x80,0x00,0xbf]
+
+s_cmp_eq_i32 s1, -1
+// CHECK: [0x01,0xc1,0x00,0xbf]
+
+s_cmp_eq_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x00,0xbf]
+
+s_cmp_eq_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x00,0xbf]
+
+s_cmp_eq_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x00,0xbf]
+
+s_cmp_eq_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x00,0xbf]
+
+s_cmp_eq_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x00,0xbf]
+
+s_cmp_eq_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_i32 s1, s2
+// CHECK: [0x01,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 s101, s2
+// CHECK: [0x65,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 m0, s2
+// CHECK: [0x7c,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 0, s2
+// CHECK: [0x80,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 -1, s2
+// CHECK: [0xc1,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x01,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x01,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_i32 s1, s101
+// CHECK: [0x01,0x65,0x01,0xbf]
+
+s_cmp_lg_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x01,0xbf]
+
+s_cmp_lg_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x01,0xbf]
+
+s_cmp_lg_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x01,0xbf]
+
+s_cmp_lg_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x01,0xbf]
+
+s_cmp_lg_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x01,0xbf]
+
+s_cmp_lg_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x01,0xbf]
+
+s_cmp_lg_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x01,0xbf]
+
+s_cmp_lg_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x01,0xbf]
+
+s_cmp_lg_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x01,0xbf]
+
+s_cmp_lg_i32 s1, m0
+// CHECK: [0x01,0x7c,0x01,0xbf]
+
+s_cmp_lg_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x01,0xbf]
+
+s_cmp_lg_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x01,0xbf]
+
+s_cmp_lg_i32 s1, 0
+// CHECK: [0x01,0x80,0x01,0xbf]
+
+s_cmp_lg_i32 s1, -1
+// CHECK: [0x01,0xc1,0x01,0xbf]
+
+s_cmp_lg_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x01,0xbf]
+
+s_cmp_lg_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x01,0xbf]
+
+s_cmp_lg_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x01,0xbf]
+
+s_cmp_lg_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x01,0xbf]
+
+s_cmp_lg_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x01,0xbf]
+
+s_cmp_lg_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_i32 s1, s2
+// CHECK: [0x01,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 s101, s2
+// CHECK: [0x65,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 m0, s2
+// CHECK: [0x7c,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 0, s2
+// CHECK: [0x80,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 -1, s2
+// CHECK: [0xc1,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x02,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x02,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_i32 s1, s101
+// CHECK: [0x01,0x65,0x02,0xbf]
+
+s_cmp_gt_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x02,0xbf]
+
+s_cmp_gt_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x02,0xbf]
+
+s_cmp_gt_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x02,0xbf]
+
+s_cmp_gt_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x02,0xbf]
+
+s_cmp_gt_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x02,0xbf]
+
+s_cmp_gt_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x02,0xbf]
+
+s_cmp_gt_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x02,0xbf]
+
+s_cmp_gt_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x02,0xbf]
+
+s_cmp_gt_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x02,0xbf]
+
+s_cmp_gt_i32 s1, m0
+// CHECK: [0x01,0x7c,0x02,0xbf]
+
+s_cmp_gt_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x02,0xbf]
+
+s_cmp_gt_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x02,0xbf]
+
+s_cmp_gt_i32 s1, 0
+// CHECK: [0x01,0x80,0x02,0xbf]
+
+s_cmp_gt_i32 s1, -1
+// CHECK: [0x01,0xc1,0x02,0xbf]
+
+s_cmp_gt_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x02,0xbf]
+
+s_cmp_gt_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x02,0xbf]
+
+s_cmp_gt_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x02,0xbf]
+
+s_cmp_gt_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x02,0xbf]
+
+s_cmp_gt_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x02,0xbf]
+
+s_cmp_gt_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_i32 s1, s2
+// CHECK: [0x01,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 s101, s2
+// CHECK: [0x65,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 m0, s2
+// CHECK: [0x7c,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 0, s2
+// CHECK: [0x80,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 -1, s2
+// CHECK: [0xc1,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x03,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x03,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_i32 s1, s101
+// CHECK: [0x01,0x65,0x03,0xbf]
+
+s_cmp_ge_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x03,0xbf]
+
+s_cmp_ge_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x03,0xbf]
+
+s_cmp_ge_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x03,0xbf]
+
+s_cmp_ge_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x03,0xbf]
+
+s_cmp_ge_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x03,0xbf]
+
+s_cmp_ge_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x03,0xbf]
+
+s_cmp_ge_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x03,0xbf]
+
+s_cmp_ge_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x03,0xbf]
+
+s_cmp_ge_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x03,0xbf]
+
+s_cmp_ge_i32 s1, m0
+// CHECK: [0x01,0x7c,0x03,0xbf]
+
+s_cmp_ge_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x03,0xbf]
+
+s_cmp_ge_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x03,0xbf]
+
+s_cmp_ge_i32 s1, 0
+// CHECK: [0x01,0x80,0x03,0xbf]
+
+s_cmp_ge_i32 s1, -1
+// CHECK: [0x01,0xc1,0x03,0xbf]
+
+s_cmp_ge_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x03,0xbf]
+
+s_cmp_ge_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x03,0xbf]
+
+s_cmp_ge_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x03,0xbf]
+
+s_cmp_ge_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x03,0xbf]
+
+s_cmp_ge_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x03,0xbf]
+
+s_cmp_ge_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_i32 s1, s2
+// CHECK: [0x01,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 s101, s2
+// CHECK: [0x65,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 m0, s2
+// CHECK: [0x7c,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 0, s2
+// CHECK: [0x80,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 -1, s2
+// CHECK: [0xc1,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x04,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x04,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_i32 s1, s101
+// CHECK: [0x01,0x65,0x04,0xbf]
+
+s_cmp_lt_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x04,0xbf]
+
+s_cmp_lt_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x04,0xbf]
+
+s_cmp_lt_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x04,0xbf]
+
+s_cmp_lt_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x04,0xbf]
+
+s_cmp_lt_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x04,0xbf]
+
+s_cmp_lt_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x04,0xbf]
+
+s_cmp_lt_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x04,0xbf]
+
+s_cmp_lt_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x04,0xbf]
+
+s_cmp_lt_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x04,0xbf]
+
+s_cmp_lt_i32 s1, m0
+// CHECK: [0x01,0x7c,0x04,0xbf]
+
+s_cmp_lt_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x04,0xbf]
+
+s_cmp_lt_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x04,0xbf]
+
+s_cmp_lt_i32 s1, 0
+// CHECK: [0x01,0x80,0x04,0xbf]
+
+s_cmp_lt_i32 s1, -1
+// CHECK: [0x01,0xc1,0x04,0xbf]
+
+s_cmp_lt_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x04,0xbf]
+
+s_cmp_lt_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x04,0xbf]
+
+s_cmp_lt_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x04,0xbf]
+
+s_cmp_lt_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x04,0xbf]
+
+s_cmp_lt_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x04,0xbf]
+
+s_cmp_lt_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_i32 s1, s2
+// CHECK: [0x01,0x02,0x05,0xbf]
+
+s_cmp_le_i32 s101, s2
+// CHECK: [0x65,0x02,0x05,0xbf]
+
+s_cmp_le_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0xbf]
+
+s_cmp_le_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0xbf]
+
+s_cmp_le_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0xbf]
+
+s_cmp_le_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0xbf]
+
+s_cmp_le_i32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x05,0xbf]
+
+s_cmp_le_i32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x05,0xbf]
+
+s_cmp_le_i32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x05,0xbf]
+
+s_cmp_le_i32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x05,0xbf]
+
+s_cmp_le_i32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x05,0xbf]
+
+s_cmp_le_i32 m0, s2
+// CHECK: [0x7c,0x02,0x05,0xbf]
+
+s_cmp_le_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0xbf]
+
+s_cmp_le_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0xbf]
+
+s_cmp_le_i32 0, s2
+// CHECK: [0x80,0x02,0x05,0xbf]
+
+s_cmp_le_i32 -1, s2
+// CHECK: [0xc1,0x02,0x05,0xbf]
+
+s_cmp_le_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0xbf]
+
+s_cmp_le_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0xbf]
+
+s_cmp_le_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0xbf]
+
+s_cmp_le_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0xbf]
+
+s_cmp_le_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0xbf]
+
+s_cmp_le_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_i32 s1, s101
+// CHECK: [0x01,0x65,0x05,0xbf]
+
+s_cmp_le_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0xbf]
+
+s_cmp_le_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0xbf]
+
+s_cmp_le_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0xbf]
+
+s_cmp_le_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0xbf]
+
+s_cmp_le_i32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x05,0xbf]
+
+s_cmp_le_i32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x05,0xbf]
+
+s_cmp_le_i32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x05,0xbf]
+
+s_cmp_le_i32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x05,0xbf]
+
+s_cmp_le_i32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x05,0xbf]
+
+s_cmp_le_i32 s1, m0
+// CHECK: [0x01,0x7c,0x05,0xbf]
+
+s_cmp_le_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0xbf]
+
+s_cmp_le_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0xbf]
+
+s_cmp_le_i32 s1, 0
+// CHECK: [0x01,0x80,0x05,0xbf]
+
+s_cmp_le_i32 s1, -1
+// CHECK: [0x01,0xc1,0x05,0xbf]
+
+s_cmp_le_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0xbf]
+
+s_cmp_le_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0xbf]
+
+s_cmp_le_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0xbf]
+
+s_cmp_le_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0xbf]
+
+s_cmp_le_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0xbf]
+
+s_cmp_le_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u32 s1, s2
+// CHECK: [0x01,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 s101, s2
+// CHECK: [0x65,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 m0, s2
+// CHECK: [0x7c,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 0, s2
+// CHECK: [0x80,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 -1, s2
+// CHECK: [0xc1,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x06,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x06,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u32 s1, s101
+// CHECK: [0x01,0x65,0x06,0xbf]
+
+s_cmp_eq_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x06,0xbf]
+
+s_cmp_eq_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x06,0xbf]
+
+s_cmp_eq_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x06,0xbf]
+
+s_cmp_eq_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x06,0xbf]
+
+s_cmp_eq_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x06,0xbf]
+
+s_cmp_eq_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x06,0xbf]
+
+s_cmp_eq_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x06,0xbf]
+
+s_cmp_eq_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x06,0xbf]
+
+s_cmp_eq_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x06,0xbf]
+
+s_cmp_eq_u32 s1, m0
+// CHECK: [0x01,0x7c,0x06,0xbf]
+
+s_cmp_eq_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x06,0xbf]
+
+s_cmp_eq_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x06,0xbf]
+
+s_cmp_eq_u32 s1, 0
+// CHECK: [0x01,0x80,0x06,0xbf]
+
+s_cmp_eq_u32 s1, -1
+// CHECK: [0x01,0xc1,0x06,0xbf]
+
+s_cmp_eq_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x06,0xbf]
+
+s_cmp_eq_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x06,0xbf]
+
+s_cmp_eq_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x06,0xbf]
+
+s_cmp_eq_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x06,0xbf]
+
+s_cmp_eq_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x06,0xbf]
+
+s_cmp_eq_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u32 s1, s2
+// CHECK: [0x01,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 s101, s2
+// CHECK: [0x65,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 m0, s2
+// CHECK: [0x7c,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 0, s2
+// CHECK: [0x80,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 -1, s2
+// CHECK: [0xc1,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x07,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x07,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u32 s1, s101
+// CHECK: [0x01,0x65,0x07,0xbf]
+
+s_cmp_lg_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x07,0xbf]
+
+s_cmp_lg_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x07,0xbf]
+
+s_cmp_lg_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x07,0xbf]
+
+s_cmp_lg_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x07,0xbf]
+
+s_cmp_lg_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x07,0xbf]
+
+s_cmp_lg_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x07,0xbf]
+
+s_cmp_lg_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x07,0xbf]
+
+s_cmp_lg_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x07,0xbf]
+
+s_cmp_lg_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x07,0xbf]
+
+s_cmp_lg_u32 s1, m0
+// CHECK: [0x01,0x7c,0x07,0xbf]
+
+s_cmp_lg_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x07,0xbf]
+
+s_cmp_lg_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x07,0xbf]
+
+s_cmp_lg_u32 s1, 0
+// CHECK: [0x01,0x80,0x07,0xbf]
+
+s_cmp_lg_u32 s1, -1
+// CHECK: [0x01,0xc1,0x07,0xbf]
+
+s_cmp_lg_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x07,0xbf]
+
+s_cmp_lg_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x07,0xbf]
+
+s_cmp_lg_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x07,0xbf]
+
+s_cmp_lg_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x07,0xbf]
+
+s_cmp_lg_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x07,0xbf]
+
+s_cmp_lg_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_u32 s1, s2
+// CHECK: [0x01,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 s101, s2
+// CHECK: [0x65,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 m0, s2
+// CHECK: [0x7c,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 0, s2
+// CHECK: [0x80,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 -1, s2
+// CHECK: [0xc1,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x08,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x08,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_u32 s1, s101
+// CHECK: [0x01,0x65,0x08,0xbf]
+
+s_cmp_gt_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x08,0xbf]
+
+s_cmp_gt_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x08,0xbf]
+
+s_cmp_gt_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x08,0xbf]
+
+s_cmp_gt_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x08,0xbf]
+
+s_cmp_gt_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x08,0xbf]
+
+s_cmp_gt_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x08,0xbf]
+
+s_cmp_gt_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x08,0xbf]
+
+s_cmp_gt_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x08,0xbf]
+
+s_cmp_gt_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x08,0xbf]
+
+s_cmp_gt_u32 s1, m0
+// CHECK: [0x01,0x7c,0x08,0xbf]
+
+s_cmp_gt_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x08,0xbf]
+
+s_cmp_gt_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x08,0xbf]
+
+s_cmp_gt_u32 s1, 0
+// CHECK: [0x01,0x80,0x08,0xbf]
+
+s_cmp_gt_u32 s1, -1
+// CHECK: [0x01,0xc1,0x08,0xbf]
+
+s_cmp_gt_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x08,0xbf]
+
+s_cmp_gt_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x08,0xbf]
+
+s_cmp_gt_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x08,0xbf]
+
+s_cmp_gt_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x08,0xbf]
+
+s_cmp_gt_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x08,0xbf]
+
+s_cmp_gt_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_u32 s1, s2
+// CHECK: [0x01,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 s101, s2
+// CHECK: [0x65,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 m0, s2
+// CHECK: [0x7c,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 0, s2
+// CHECK: [0x80,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 -1, s2
+// CHECK: [0xc1,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x09,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x09,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_u32 s1, s101
+// CHECK: [0x01,0x65,0x09,0xbf]
+
+s_cmp_ge_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x09,0xbf]
+
+s_cmp_ge_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x09,0xbf]
+
+s_cmp_ge_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x09,0xbf]
+
+s_cmp_ge_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x09,0xbf]
+
+s_cmp_ge_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x09,0xbf]
+
+s_cmp_ge_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x09,0xbf]
+
+s_cmp_ge_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x09,0xbf]
+
+s_cmp_ge_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x09,0xbf]
+
+s_cmp_ge_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x09,0xbf]
+
+s_cmp_ge_u32 s1, m0
+// CHECK: [0x01,0x7c,0x09,0xbf]
+
+s_cmp_ge_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x09,0xbf]
+
+s_cmp_ge_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x09,0xbf]
+
+s_cmp_ge_u32 s1, 0
+// CHECK: [0x01,0x80,0x09,0xbf]
+
+s_cmp_ge_u32 s1, -1
+// CHECK: [0x01,0xc1,0x09,0xbf]
+
+s_cmp_ge_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x09,0xbf]
+
+s_cmp_ge_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x09,0xbf]
+
+s_cmp_ge_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x09,0xbf]
+
+s_cmp_ge_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x09,0xbf]
+
+s_cmp_ge_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x09,0xbf]
+
+s_cmp_ge_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_u32 s1, s2
+// CHECK: [0x01,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 s101, s2
+// CHECK: [0x65,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 m0, s2
+// CHECK: [0x7c,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 0, s2
+// CHECK: [0x80,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 -1, s2
+// CHECK: [0xc1,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0a,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0a,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_u32 s1, s101
+// CHECK: [0x01,0x65,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, m0
+// CHECK: [0x01,0x7c,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, 0
+// CHECK: [0x01,0x80,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, -1
+// CHECK: [0x01,0xc1,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_u32 s1, s2
+// CHECK: [0x01,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 s101, s2
+// CHECK: [0x65,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 m0, s2
+// CHECK: [0x7c,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 0, s2
+// CHECK: [0x80,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 -1, s2
+// CHECK: [0xc1,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0b,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0b,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_u32 s1, s101
+// CHECK: [0x01,0x65,0x0b,0xbf]
+
+s_cmp_le_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x0b,0xbf]
+
+s_cmp_le_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x0b,0xbf]
+
+s_cmp_le_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0b,0xbf]
+
+s_cmp_le_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0b,0xbf]
+
+s_cmp_le_u32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x0b,0xbf]
+
+s_cmp_le_u32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x0b,0xbf]
+
+s_cmp_le_u32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x0b,0xbf]
+
+s_cmp_le_u32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x0b,0xbf]
+
+s_cmp_le_u32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x0b,0xbf]
+
+s_cmp_le_u32 s1, m0
+// CHECK: [0x01,0x7c,0x0b,0xbf]
+
+s_cmp_le_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0b,0xbf]
+
+s_cmp_le_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0b,0xbf]
+
+s_cmp_le_u32 s1, 0
+// CHECK: [0x01,0x80,0x0b,0xbf]
+
+s_cmp_le_u32 s1, -1
+// CHECK: [0x01,0xc1,0x0b,0xbf]
+
+s_cmp_le_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0b,0xbf]
+
+s_cmp_le_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0b,0xbf]
+
+s_cmp_le_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0b,0xbf]
+
+s_cmp_le_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0b,0xbf]
+
+s_cmp_le_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0b,0xbf]
+
+s_cmp_le_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b32 s1, s2
+// CHECK: [0x01,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 s101, s2
+// CHECK: [0x65,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 m0, s2
+// CHECK: [0x7c,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 0, s2
+// CHECK: [0x80,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 -1, s2
+// CHECK: [0xc1,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 0.5, s2
+// CHECK: [0xf0,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0c,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0c,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b32 s1, s101
+// CHECK: [0x01,0x65,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, m0
+// CHECK: [0x01,0x7c,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, 0
+// CHECK: [0x01,0x80,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, -1
+// CHECK: [0x01,0xc1,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b32 s1, s2
+// CHECK: [0x01,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 s101, s2
+// CHECK: [0x65,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 tba_lo, s2
+// CHECK: [0x6c,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 tba_hi, s2
+// CHECK: [0x6d,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 tma_lo, s2
+// CHECK: [0x6e,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 tma_hi, s2
+// CHECK: [0x6f,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 ttmp11, s2
+// CHECK: [0x7b,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 m0, s2
+// CHECK: [0x7c,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 0, s2
+// CHECK: [0x80,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 -1, s2
+// CHECK: [0xc1,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 0.5, s2
+// CHECK: [0xf0,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0d,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0d,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b32 s1, s101
+// CHECK: [0x01,0x65,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, tba_lo
+// CHECK: [0x01,0x6c,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, tba_hi
+// CHECK: [0x01,0x6d,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, tma_lo
+// CHECK: [0x01,0x6e,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, tma_hi
+// CHECK: [0x01,0x6f,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, ttmp11
+// CHECK: [0x01,0x7b,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, m0
+// CHECK: [0x01,0x7c,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, 0
+// CHECK: [0x01,0x80,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, -1
+// CHECK: [0x01,0xc1,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b64 s[2:3], s2
+// CHECK: [0x02,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 s[4:5], s2
+// CHECK: [0x04,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 s[100:101], s2
+// CHECK: [0x64,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 flat_scratch, s2
+// CHECK: [0x66,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 vcc, s2
+// CHECK: [0x6a,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 tba, s2
+// CHECK: [0x6c,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 tma, s2
+// CHECK: [0x6e,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 exec, s2
+// CHECK: [0x7e,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 0, s2
+// CHECK: [0x80,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 -1, s2
+// CHECK: [0xc1,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 0.5, s2
+// CHECK: [0xf0,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 -4.0, s2
+// CHECK: [0xf7,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 src_execz, s2
+// CHECK: [0xfc,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 src_scc, s2
+// CHECK: [0xfd,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0e,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b64 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0e,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b64 s[2:3], s101
+// CHECK: [0x02,0x65,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], m0
+// CHECK: [0x02,0x7c,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], 0
+// CHECK: [0x02,0x80,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b64 s[2:3], s2
+// CHECK: [0x02,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 s[4:5], s2
+// CHECK: [0x04,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 s[100:101], s2
+// CHECK: [0x64,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 flat_scratch, s2
+// CHECK: [0x66,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 vcc, s2
+// CHECK: [0x6a,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 tba, s2
+// CHECK: [0x6c,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 tma, s2
+// CHECK: [0x6e,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 ttmp[10:11], s2
+// CHECK: [0x7a,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 exec, s2
+// CHECK: [0x7e,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 0, s2
+// CHECK: [0x80,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 -1, s2
+// CHECK: [0xc1,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 0.5, s2
+// CHECK: [0xf0,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 -4.0, s2
+// CHECK: [0xf7,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 src_execz, s2
+// CHECK: [0xfc,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 src_scc, s2
+// CHECK: [0xfd,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0f,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b64 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0f,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b64 s[2:3], s101
+// CHECK: [0x02,0x65,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], tba_lo
+// CHECK: [0x02,0x6c,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], tba_hi
+// CHECK: [0x02,0x6d,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], tma_lo
+// CHECK: [0x02,0x6e,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], tma_hi
+// CHECK: [0x02,0x6f,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], ttmp11
+// CHECK: [0x02,0x7b,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], m0
+// CHECK: [0x02,0x7c,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], 0
+// CHECK: [0x02,0x80,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f]
+
+s_setvskip s1, s2
+// CHECK: [0x01,0x02,0x10,0xbf]
+
+s_setvskip s101, s2
+// CHECK: [0x65,0x02,0x10,0xbf]
+
+s_setvskip flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x10,0xbf]
+
+s_setvskip flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x10,0xbf]
+
+s_setvskip vcc_lo, s2
+// CHECK: [0x6a,0x02,0x10,0xbf]
+
+s_setvskip vcc_hi, s2
+// CHECK: [0x6b,0x02,0x10,0xbf]
+
+s_setvskip tba_lo, s2
+// CHECK: [0x6c,0x02,0x10,0xbf]
+
+s_setvskip tba_hi, s2
+// CHECK: [0x6d,0x02,0x10,0xbf]
+
+s_setvskip tma_lo, s2
+// CHECK: [0x6e,0x02,0x10,0xbf]
+
+s_setvskip tma_hi, s2
+// CHECK: [0x6f,0x02,0x10,0xbf]
+
+s_setvskip ttmp11, s2
+// CHECK: [0x7b,0x02,0x10,0xbf]
+
+s_setvskip m0, s2
+// CHECK: [0x7c,0x02,0x10,0xbf]
+
+s_setvskip exec_lo, s2
+// CHECK: [0x7e,0x02,0x10,0xbf]
+
+s_setvskip exec_hi, s2
+// CHECK: [0x7f,0x02,0x10,0xbf]
+
+s_setvskip 0, s2
+// CHECK: [0x80,0x02,0x10,0xbf]
+
+s_setvskip -1, s2
+// CHECK: [0xc1,0x02,0x10,0xbf]
+
+s_setvskip 0.5, s2
+// CHECK: [0xf0,0x02,0x10,0xbf]
+
+s_setvskip -4.0, s2
+// CHECK: [0xf7,0x02,0x10,0xbf]
+
+s_setvskip src_vccz, s2
+// CHECK: [0xfb,0x02,0x10,0xbf]
+
+s_setvskip src_execz, s2
+// CHECK: [0xfc,0x02,0x10,0xbf]
+
+s_setvskip src_scc, s2
+// CHECK: [0xfd,0x02,0x10,0xbf]
+
+s_setvskip 0xaf123456, s2
+// CHECK: [0xff,0x02,0x10,0xbf,0x56,0x34,0x12,0xaf]
+
+s_setvskip 0x3f717273, s2
+// CHECK: [0xff,0x02,0x10,0xbf,0x73,0x72,0x71,0x3f]
+
+s_setvskip s1, s101
+// CHECK: [0x01,0x65,0x10,0xbf]
+
+s_setvskip s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x10,0xbf]
+
+s_setvskip s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x10,0xbf]
+
+s_setvskip s1, vcc_lo
+// CHECK: [0x01,0x6a,0x10,0xbf]
+
+s_setvskip s1, vcc_hi
+// CHECK: [0x01,0x6b,0x10,0xbf]
+
+s_setvskip s1, tba_lo
+// CHECK: [0x01,0x6c,0x10,0xbf]
+
+s_setvskip s1, tba_hi
+// CHECK: [0x01,0x6d,0x10,0xbf]
+
+s_setvskip s1, tma_lo
+// CHECK: [0x01,0x6e,0x10,0xbf]
+
+s_setvskip s1, tma_hi
+// CHECK: [0x01,0x6f,0x10,0xbf]
+
+s_setvskip s1, ttmp11
+// CHECK: [0x01,0x7b,0x10,0xbf]
+
+s_setvskip s1, m0
+// CHECK: [0x01,0x7c,0x10,0xbf]
+
+s_setvskip s1, exec_lo
+// CHECK: [0x01,0x7e,0x10,0xbf]
+
+s_setvskip s1, exec_hi
+// CHECK: [0x01,0x7f,0x10,0xbf]
+
+s_setvskip s1, 0
+// CHECK: [0x01,0x80,0x10,0xbf]
+
+s_setvskip s1, -1
+// CHECK: [0x01,0xc1,0x10,0xbf]
+
+s_setvskip s1, 0.5
+// CHECK: [0x01,0xf0,0x10,0xbf]
+
+s_setvskip s1, -4.0
+// CHECK: [0x01,0xf7,0x10,0xbf]
+
+s_setvskip s1, src_vccz
+// CHECK: [0x01,0xfb,0x10,0xbf]
+
+s_setvskip s1, src_execz
+// CHECK: [0x01,0xfc,0x10,0xbf]
+
+s_setvskip s1, src_scc
+// CHECK: [0x01,0xfd,0x10,0xbf]
+
+s_setvskip s1, 0xaf123456
+// CHECK: [0x01,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf]
+
+s_setvskip s1, 0x3f717273
+// CHECK: [0x01,0xff,0x10,0xbf,0x73,0x72,0x71,0x3f]
+
+s_set_gpr_idx_on s1, 0x0
+// CHECK: [0x01,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on s101, 0x0
+// CHECK: [0x65,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on flat_scratch_lo, 0x0
+// CHECK: [0x66,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on flat_scratch_hi, 0x0
+// CHECK: [0x67,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on vcc_lo, 0x0
+// CHECK: [0x6a,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on vcc_hi, 0x0
+// CHECK: [0x6b,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on tba_lo, 0x0
+// CHECK: [0x6c,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on tba_hi, 0x0
+// CHECK: [0x6d,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on tma_lo, 0x0
+// CHECK: [0x6e,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on tma_hi, 0x0
+// CHECK: [0x6f,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on ttmp11, 0x0
+// CHECK: [0x7b,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on m0, 0x0
+// CHECK: [0x7c,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on 0, 0x0
+// CHECK: [0x80,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on -1, 0x0
+// CHECK: [0xc1,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on 0.5, 0x0
+// CHECK: [0xf0,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on -4.0, 0x0
+// CHECK: [0xf7,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on src_vccz, 0x0
+// CHECK: [0xfb,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on src_execz, 0x0
+// CHECK: [0xfc,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on src_scc, 0x0
+// CHECK: [0xfd,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on 0xaf123456, 0x0
+// CHECK: [0xff,0x00,0x11,0xbf,0x56,0x34,0x12,0xaf]
+
+s_set_gpr_idx_on 0x3f717273, 0x0
+// CHECK: [0xff,0x00,0x11,0xbf,0x73,0x72,0x71,0x3f]
+
+s_set_gpr_idx_on s1, 0x1
+// CHECK: [0x01,0x01,0x11,0xbf]
+
+s_set_gpr_idx_on s1, 0xF
+// CHECK: [0x01,0x0f,0x11,0xbf]
+
+s_cmp_eq_u64 s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 tba, s[4:5]
+// CHECK: [0x6c,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 tma, s[4:5]
+// CHECK: [0x6e,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 exec, s[4:5]
+// CHECK: [0x7e,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 0, s[4:5]
+// CHECK: [0x80,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 -1, s[4:5]
+// CHECK: [0xc1,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x12,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u64 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x12,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u64 s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], vcc
+// CHECK: [0x02,0x6a,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], tba
+// CHECK: [0x02,0x6c,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], tma
+// CHECK: [0x02,0x6e,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], exec
+// CHECK: [0x02,0x7e,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], 0
+// CHECK: [0x02,0x80,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x12,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x12,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u64 s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 tba, s[4:5]
+// CHECK: [0x6c,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 tma, s[4:5]
+// CHECK: [0x6e,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 ttmp[10:11], s[4:5]
+// CHECK: [0x7a,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 exec, s[4:5]
+// CHECK: [0x7e,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 0, s[4:5]
+// CHECK: [0x80,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 -1, s[4:5]
+// CHECK: [0xc1,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x13,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u64 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x13,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u64 s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], vcc
+// CHECK: [0x02,0x6a,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], tba
+// CHECK: [0x02,0x6c,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], tma
+// CHECK: [0x02,0x6e,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], ttmp[10:11]
+// CHECK: [0x02,0x7a,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], exec
+// CHECK: [0x02,0x7e,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], 0
+// CHECK: [0x02,0x80,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x13,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x13,0xbf,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx8_asm_sopk.s
new file mode 100644
index 0000000000000..56a66243b96b4
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sopk.s
@@ -0,0 +1,850 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+s_movk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x05,0xb0]
+
+s_movk_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb0]
+
+s_movk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb0]
+
+s_movk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb0]
+
+s_movk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb0]
+
+s_movk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb0]
+
+s_movk_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb0]
+
+s_movk_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb0]
+
+s_movk_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb0]
+
+s_movk_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb0]
+
+s_movk_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb0]
+
+s_movk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb0]
+
+s_movk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb0]
+
+s_movk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb0]
+
+s_movk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x05,0xb0]
+
+s_cmovk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x85,0xb0]
+
+s_cmovk_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb0]
+
+s_cmovk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb0]
+
+s_cmovk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb0]
+
+s_cmovk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb0]
+
+s_cmovk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb0]
+
+s_cmovk_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb0]
+
+s_cmovk_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb0]
+
+s_cmovk_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb0]
+
+s_cmovk_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb0]
+
+s_cmovk_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb0]
+
+s_cmovk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb0]
+
+s_cmovk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb0]
+
+s_cmovk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb0]
+
+s_cmovk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x85,0xb0]
+
+s_cmpk_eq_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb1]
+
+s_cmpk_eq_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb1]
+
+s_cmpk_eq_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb1]
+
+s_cmpk_eq_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb1]
+
+s_cmpk_eq_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb1]
+
+s_cmpk_eq_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb1]
+
+s_cmpk_eq_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb1]
+
+s_cmpk_eq_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb1]
+
+s_cmpk_eq_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb1]
+
+s_cmpk_eq_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb1]
+
+s_cmpk_eq_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb1]
+
+s_cmpk_eq_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb1]
+
+s_cmpk_eq_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb1]
+
+s_cmpk_eq_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb1]
+
+s_cmpk_eq_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb1]
+
+s_cmpk_lg_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb1]
+
+s_cmpk_lg_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb1]
+
+s_cmpk_lg_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb1]
+
+s_cmpk_lg_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb1]
+
+s_cmpk_lg_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb1]
+
+s_cmpk_lg_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb1]
+
+s_cmpk_lg_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb1]
+
+s_cmpk_lg_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb1]
+
+s_cmpk_lg_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb1]
+
+s_cmpk_lg_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb1]
+
+s_cmpk_lg_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb1]
+
+s_cmpk_lg_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb1]
+
+s_cmpk_lg_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb1]
+
+s_cmpk_lg_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb1]
+
+s_cmpk_lg_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb1]
+
+s_cmpk_gt_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb2]
+
+s_cmpk_gt_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb2]
+
+s_cmpk_gt_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb2]
+
+s_cmpk_gt_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb2]
+
+s_cmpk_gt_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb2]
+
+s_cmpk_gt_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb2]
+
+s_cmpk_gt_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb2]
+
+s_cmpk_gt_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb2]
+
+s_cmpk_gt_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb2]
+
+s_cmpk_gt_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb2]
+
+s_cmpk_gt_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb2]
+
+s_cmpk_gt_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb2]
+
+s_cmpk_gt_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb2]
+
+s_cmpk_gt_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb2]
+
+s_cmpk_gt_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb2]
+
+s_cmpk_ge_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb2]
+
+s_cmpk_ge_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb2]
+
+s_cmpk_ge_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb2]
+
+s_cmpk_ge_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb2]
+
+s_cmpk_ge_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb2]
+
+s_cmpk_ge_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb2]
+
+s_cmpk_ge_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb2]
+
+s_cmpk_ge_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb2]
+
+s_cmpk_ge_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb2]
+
+s_cmpk_ge_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb2]
+
+s_cmpk_ge_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb2]
+
+s_cmpk_ge_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb2]
+
+s_cmpk_ge_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb2]
+
+s_cmpk_ge_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb2]
+
+s_cmpk_ge_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb2]
+
+s_cmpk_lt_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb3]
+
+s_cmpk_lt_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb3]
+
+s_cmpk_lt_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb3]
+
+s_cmpk_lt_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb3]
+
+s_cmpk_lt_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb3]
+
+s_cmpk_lt_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb3]
+
+s_cmpk_lt_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb3]
+
+s_cmpk_lt_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb3]
+
+s_cmpk_lt_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb3]
+
+s_cmpk_lt_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb3]
+
+s_cmpk_lt_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb3]
+
+s_cmpk_lt_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb3]
+
+s_cmpk_lt_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb3]
+
+s_cmpk_lt_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb3]
+
+s_cmpk_lt_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb3]
+
+s_cmpk_le_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb3]
+
+s_cmpk_le_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb3]
+
+s_cmpk_le_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb3]
+
+s_cmpk_le_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb3]
+
+s_cmpk_le_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb3]
+
+s_cmpk_le_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb3]
+
+s_cmpk_le_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb3]
+
+s_cmpk_le_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb3]
+
+s_cmpk_le_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb3]
+
+s_cmpk_le_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb3]
+
+s_cmpk_le_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb3]
+
+s_cmpk_le_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb3]
+
+s_cmpk_le_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb3]
+
+s_cmpk_le_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb3]
+
+s_cmpk_le_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb3]
+
+s_cmpk_eq_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb4]
+
+s_cmpk_eq_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb4]
+
+s_cmpk_eq_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb4]
+
+s_cmpk_eq_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb4]
+
+s_cmpk_eq_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb4]
+
+s_cmpk_eq_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb4]
+
+s_cmpk_eq_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb4]
+
+s_cmpk_eq_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb4]
+
+s_cmpk_eq_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb4]
+
+s_cmpk_eq_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb4]
+
+s_cmpk_eq_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb4]
+
+s_cmpk_eq_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb4]
+
+s_cmpk_eq_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb4]
+
+s_cmpk_eq_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb4]
+
+s_cmpk_eq_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb4]
+
+s_cmpk_lg_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb4]
+
+s_cmpk_lg_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb4]
+
+s_cmpk_lg_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb4]
+
+s_cmpk_lg_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb4]
+
+s_cmpk_lg_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb4]
+
+s_cmpk_lg_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb4]
+
+s_cmpk_lg_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb4]
+
+s_cmpk_lg_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb4]
+
+s_cmpk_lg_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb4]
+
+s_cmpk_lg_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb4]
+
+s_cmpk_lg_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb4]
+
+s_cmpk_lg_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb4]
+
+s_cmpk_lg_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb4]
+
+s_cmpk_lg_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb4]
+
+s_cmpk_lg_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb4]
+
+s_cmpk_gt_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb5]
+
+s_cmpk_gt_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb5]
+
+s_cmpk_gt_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb5]
+
+s_cmpk_gt_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb5]
+
+s_cmpk_gt_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb5]
+
+s_cmpk_gt_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb5]
+
+s_cmpk_gt_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb5]
+
+s_cmpk_gt_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb5]
+
+s_cmpk_gt_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb5]
+
+s_cmpk_gt_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb5]
+
+s_cmpk_gt_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb5]
+
+s_cmpk_gt_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb5]
+
+s_cmpk_gt_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb5]
+
+s_cmpk_gt_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb5]
+
+s_cmpk_gt_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb5]
+
+s_cmpk_ge_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb5]
+
+s_cmpk_ge_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb5]
+
+s_cmpk_ge_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb5]
+
+s_cmpk_ge_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb5]
+
+s_cmpk_ge_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb5]
+
+s_cmpk_ge_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb5]
+
+s_cmpk_ge_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb5]
+
+s_cmpk_ge_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb5]
+
+s_cmpk_ge_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb5]
+
+s_cmpk_ge_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb5]
+
+s_cmpk_ge_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb5]
+
+s_cmpk_ge_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb5]
+
+s_cmpk_ge_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb5]
+
+s_cmpk_ge_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb5]
+
+s_cmpk_ge_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb5]
+
+s_cmpk_lt_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb6]
+
+s_cmpk_lt_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb6]
+
+s_cmpk_lt_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb6]
+
+s_cmpk_lt_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb6]
+
+s_cmpk_lt_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb6]
+
+s_cmpk_lt_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb6]
+
+s_cmpk_lt_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb6]
+
+s_cmpk_lt_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb6]
+
+s_cmpk_lt_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb6]
+
+s_cmpk_lt_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb6]
+
+s_cmpk_lt_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb6]
+
+s_cmpk_lt_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb6]
+
+s_cmpk_lt_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb6]
+
+s_cmpk_lt_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb6]
+
+s_cmpk_lt_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb6]
+
+s_cmpk_le_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb6]
+
+s_cmpk_le_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb6]
+
+s_cmpk_le_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb6]
+
+s_cmpk_le_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb6]
+
+s_cmpk_le_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb6]
+
+s_cmpk_le_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb6]
+
+s_cmpk_le_u32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb6]
+
+s_cmpk_le_u32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb6]
+
+s_cmpk_le_u32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb6]
+
+s_cmpk_le_u32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb6]
+
+s_cmpk_le_u32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb6]
+
+s_cmpk_le_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb6]
+
+s_cmpk_le_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb6]
+
+s_cmpk_le_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb6]
+
+s_cmpk_le_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb6]
+
+s_addk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x05,0xb7]
+
+s_addk_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb7]
+
+s_addk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb7]
+
+s_addk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb7]
+
+s_addk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb7]
+
+s_addk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb7]
+
+s_addk_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0x6c,0xb7]
+
+s_addk_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0x6d,0xb7]
+
+s_addk_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0x6e,0xb7]
+
+s_addk_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0x6f,0xb7]
+
+s_addk_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb7]
+
+s_addk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb7]
+
+s_addk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb7]
+
+s_addk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb7]
+
+s_addk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x05,0xb7]
+
+s_mulk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x85,0xb7]
+
+s_mulk_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb7]
+
+s_mulk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb7]
+
+s_mulk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb7]
+
+s_mulk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb7]
+
+s_mulk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb7]
+
+s_mulk_i32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb7]
+
+s_mulk_i32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb7]
+
+s_mulk_i32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb7]
+
+s_mulk_i32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb7]
+
+s_mulk_i32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb7]
+
+s_mulk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb7]
+
+s_mulk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb7]
+
+s_mulk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb7]
+
+s_mulk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x85,0xb7]
+
+s_cbranch_i_fork s[2:3], 12609
+// CHECK: [0x41,0x31,0x02,0xb8]
+
+s_cbranch_i_fork s[4:5], 12609
+// CHECK: [0x41,0x31,0x04,0xb8]
+
+s_cbranch_i_fork s[100:101], 12609
+// CHECK: [0x41,0x31,0x64,0xb8]
+
+s_cbranch_i_fork flat_scratch, 12609
+// CHECK: [0x41,0x31,0x66,0xb8]
+
+s_cbranch_i_fork vcc, 12609
+// CHECK: [0x41,0x31,0x6a,0xb8]
+
+s_cbranch_i_fork tba, 12609
+// CHECK: [0x41,0x31,0x6c,0xb8]
+
+s_cbranch_i_fork tma, 12609
+// CHECK: [0x41,0x31,0x6e,0xb8]
+
+s_cbranch_i_fork ttmp[10:11], 12609
+// CHECK: [0x41,0x31,0x7a,0xb8]
+
+s_cbranch_i_fork exec, 12609
+// CHECK: [0x41,0x31,0x7e,0xb8]
+
+s_cbranch_i_fork s[2:3], 49617
+// CHECK: [0xd1,0xc1,0x02,0xb8]
+
+s_getreg_b32 s5, 0x3141
+// CHECK: [0x41,0x31,0x85,0xb8]
+
+s_getreg_b32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb8]
+
+s_getreg_b32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb8]
+
+s_getreg_b32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb8]
+
+s_getreg_b32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb8]
+
+s_getreg_b32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb8]
+
+s_getreg_b32 tba_lo, 0x3141
+// CHECK: [0x41,0x31,0xec,0xb8]
+
+s_getreg_b32 tba_hi, 0x3141
+// CHECK: [0x41,0x31,0xed,0xb8]
+
+s_getreg_b32 tma_lo, 0x3141
+// CHECK: [0x41,0x31,0xee,0xb8]
+
+s_getreg_b32 tma_hi, 0x3141
+// CHECK: [0x41,0x31,0xef,0xb8]
+
+s_getreg_b32 ttmp11, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb8]
+
+s_getreg_b32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb8]
+
+s_getreg_b32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb8]
+
+s_getreg_b32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb8]
+
+s_getreg_b32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x85,0xb8]
+
+s_setreg_b32 0x3141, s1
+// CHECK: [0x41,0x31,0x01,0xb9]
+
+s_setreg_b32 0xc1d1, s1
+// CHECK: [0xd1,0xc1,0x01,0xb9]
+
+s_setreg_b32 0x3141, s101
+// CHECK: [0x41,0x31,0x65,0xb9]
+
+s_setreg_b32 0x3141, flat_scratch_lo
+// CHECK: [0x41,0x31,0x66,0xb9]
+
+s_setreg_b32 0x3141, flat_scratch_hi
+// CHECK: [0x41,0x31,0x67,0xb9]
+
+s_setreg_b32 0x3141, vcc_lo
+// CHECK: [0x41,0x31,0x6a,0xb9]
+
+s_setreg_b32 0x3141, vcc_hi
+// CHECK: [0x41,0x31,0x6b,0xb9]
+
+s_setreg_b32 0x3141, tba_lo
+// CHECK: [0x41,0x31,0x6c,0xb9]
+
+s_setreg_b32 0x3141, tba_hi
+// CHECK: [0x41,0x31,0x6d,0xb9]
+
+s_setreg_b32 0x3141, tma_lo
+// CHECK: [0x41,0x31,0x6e,0xb9]
+
+s_setreg_b32 0x3141, tma_hi
+// CHECK: [0x41,0x31,0x6f,0xb9]
+
+s_setreg_b32 0x3141, ttmp11
+// CHECK: [0x41,0x31,0x7b,0xb9]
+
+s_setreg_b32 0x3141, m0
+// CHECK: [0x41,0x31,0x7c,0xb9]
+
+s_setreg_b32 0x3141, exec_lo
+// CHECK: [0x41,0x31,0x7e,0xb9]
+
+s_setreg_b32 0x3141, exec_hi
+// CHECK: [0x41,0x31,0x7f,0xb9]
+
+s_setreg_imm32_b32 0x3141, 0x11213141
+// CHECK: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
+
+s_setreg_imm32_b32 0xc1d1, 0x11213141
+// CHECK: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
+
+s_setreg_imm32_b32 0x3141, 0xa1b1c1d1
+// CHECK: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx8_asm_sopp.s
new file mode 100644
index 0000000000000..3aedcb08d0122
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_sopp.s
@@ -0,0 +1,163 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+s_nop 0x3141
+// CHECK: [0x41,0x31,0x80,0xbf]
+
+s_nop 0xc1d1
+// CHECK: [0xd1,0xc1,0x80,0xbf]
+
+s_endpgm
+// CHECK: [0x00,0x00,0x81,0xbf]
+
+s_branch 12609
+// CHECK: [0x41,0x31,0x82,0xbf]
+
+s_branch 49617
+// CHECK: [0xd1,0xc1,0x82,0xbf]
+
+s_wakeup
+// CHECK: [0x00,0x00,0x83,0xbf]
+
+s_cbranch_scc0 12609
+// CHECK: [0x41,0x31,0x84,0xbf]
+
+s_cbranch_scc0 49617
+// CHECK: [0xd1,0xc1,0x84,0xbf]
+
+s_cbranch_scc1 12609
+// CHECK: [0x41,0x31,0x85,0xbf]
+
+s_cbranch_scc1 49617
+// CHECK: [0xd1,0xc1,0x85,0xbf]
+
+s_cbranch_vccz 12609
+// CHECK: [0x41,0x31,0x86,0xbf]
+
+s_cbranch_vccz 49617
+// CHECK: [0xd1,0xc1,0x86,0xbf]
+
+s_cbranch_vccnz 12609
+// CHECK: [0x41,0x31,0x87,0xbf]
+
+s_cbranch_vccnz 49617
+// CHECK: [0xd1,0xc1,0x87,0xbf]
+
+s_cbranch_execz 12609
+// CHECK: [0x41,0x31,0x88,0xbf]
+
+s_cbranch_execz 49617
+// CHECK: [0xd1,0xc1,0x88,0xbf]
+
+s_cbranch_execnz 12609
+// CHECK: [0x41,0x31,0x89,0xbf]
+
+s_cbranch_execnz 49617
+// CHECK: [0xd1,0xc1,0x89,0xbf]
+
+s_barrier
+// CHECK: [0x00,0x00,0x8a,0xbf]
+
+s_setkill 0x3141
+// CHECK: [0x41,0x31,0x8b,0xbf]
+
+s_setkill 0xc1d1
+// CHECK: [0xd1,0xc1,0x8b,0xbf]
+
+s_waitcnt 0x3141
+// CHECK: [0x41,0x31,0x8c,0xbf]
+
+s_waitcnt 0xc1d1
+// CHECK: [0xd1,0xc1,0x8c,0xbf]
+
+s_sethalt 0x3141
+// CHECK: [0x41,0x31,0x8d,0xbf]
+
+s_sethalt 0xc1d1
+// CHECK: [0xd1,0xc1,0x8d,0xbf]
+
+s_sleep 0x3141
+// CHECK: [0x41,0x31,0x8e,0xbf]
+
+s_sleep 0xc1d1
+// CHECK: [0xd1,0xc1,0x8e,0xbf]
+
+s_setprio 0x3141
+// CHECK: [0x41,0x31,0x8f,0xbf]
+
+s_setprio 0xc1d1
+// CHECK: [0xd1,0xc1,0x8f,0xbf]
+
+s_sendmsg 0x3141
+// CHECK: [0x41,0x31,0x90,0xbf]
+
+s_sendmsg 0xc1d1
+// CHECK: [0xd1,0xc1,0x90,0xbf]
+
+s_sendmsghalt 0x3141
+// CHECK: [0x41,0x31,0x91,0xbf]
+
+s_sendmsghalt 0xc1d1
+// CHECK: [0xd1,0xc1,0x91,0xbf]
+
+s_trap 0x3141
+// CHECK: [0x41,0x31,0x92,0xbf]
+
+s_trap 0xc1d1
+// CHECK: [0xd1,0xc1,0x92,0xbf]
+
+s_icache_inv
+// CHECK: [0x00,0x00,0x93,0xbf]
+
+s_incperflevel 0x3141
+// CHECK: [0x41,0x31,0x94,0xbf]
+
+s_incperflevel 0xc1d1
+// CHECK: [0xd1,0xc1,0x94,0xbf]
+
+s_decperflevel 0x3141
+// CHECK: [0x41,0x31,0x95,0xbf]
+
+s_decperflevel 0xc1d1
+// CHECK: [0xd1,0xc1,0x95,0xbf]
+
+s_ttracedata
+// CHECK: [0x00,0x00,0x96,0xbf]
+
+s_cbranch_cdbgsys 12609
+// CHECK: [0x41,0x31,0x97,0xbf]
+
+s_cbranch_cdbgsys 49617
+// CHECK: [0xd1,0xc1,0x97,0xbf]
+
+s_cbranch_cdbguser 12609
+// CHECK: [0x41,0x31,0x98,0xbf]
+
+s_cbranch_cdbguser 49617
+// CHECK: [0xd1,0xc1,0x98,0xbf]
+
+s_cbranch_cdbgsys_or_user 12609
+// CHECK: [0x41,0x31,0x99,0xbf]
+
+s_cbranch_cdbgsys_or_user 49617
+// CHECK: [0xd1,0xc1,0x99,0xbf]
+
+s_cbranch_cdbgsys_and_user 12609
+// CHECK: [0x41,0x31,0x9a,0xbf]
+
+s_cbranch_cdbgsys_and_user 49617
+// CHECK: [0xd1,0xc1,0x9a,0xbf]
+
+s_endpgm_saved
+// CHECK: [0x00,0x00,0x9b,0xbf]
+
+s_set_gpr_idx_off
+// CHECK: [0x00,0x00,0x9c,0xbf]
+
+s_set_gpr_idx_mode 0x0
+// CHECK: [0x00,0x00,0x9d,0xbf]
+
+s_set_gpr_idx_mode 0x1
+// CHECK: [0x01,0x00,0x9d,0xbf]
+
+s_set_gpr_idx_mode 0xF
+// CHECK: [0x0f,0x00,0x9d,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s b/llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s
new file mode 100644
index 0000000000000..890cd728db9a4
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vintrp.s
@@ -0,0 +1,85 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+v_interp_p1_f32 v5, v1, attr0.x
+// CHECK: [0x01,0x00,0x14,0xd4]
+
+v_interp_p1_f32 v255, v1, attr0.x
+// CHECK: [0x01,0x00,0xfc,0xd7]
+
+v_interp_p1_f32 v5, v255, attr0.x
+// CHECK: [0xff,0x00,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr1.x
+// CHECK: [0x01,0x04,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr31.x
+// CHECK: [0x01,0x7c,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr32.x
+// CHECK: [0x01,0x80,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr0.y
+// CHECK: [0x01,0x01,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr0.z
+// CHECK: [0x01,0x02,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr0.w
+// CHECK: [0x01,0x03,0x14,0xd4]
+
+v_interp_p2_f32 v5, v1, attr0.x
+// CHECK: [0x01,0x00,0x15,0xd4]
+
+v_interp_p2_f32 v255, v1, attr0.x
+// CHECK: [0x01,0x00,0xfd,0xd7]
+
+v_interp_p2_f32 v5, v255, attr0.x
+// CHECK: [0xff,0x00,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr1.x
+// CHECK: [0x01,0x04,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr31.x
+// CHECK: [0x01,0x7c,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr32.x
+// CHECK: [0x01,0x80,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr0.y
+// CHECK: [0x01,0x01,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr0.z
+// CHECK: [0x01,0x02,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr0.w
+// CHECK: [0x01,0x03,0x15,0xd4]
+
+v_interp_mov_f32 v5, p10, attr0.x
+// CHECK: [0x00,0x00,0x16,0xd4]
+
+v_interp_mov_f32 v255, p10, attr0.x
+// CHECK: [0x00,0x00,0xfe,0xd7]
+
+v_interp_mov_f32 v5, p20, attr0.x
+// CHECK: [0x01,0x00,0x16,0xd4]
+
+v_interp_mov_f32 v5, p0, attr0.x
+// CHECK: [0x02,0x00,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr1.x
+// CHECK: [0x00,0x04,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr31.x
+// CHECK: [0x00,0x7c,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr32.x
+// CHECK: [0x00,0x80,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr0.y
+// CHECK: [0x00,0x01,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr0.z
+// CHECK: [0x00,0x02,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr0.w
+// CHECK: [0x00,0x03,0x16,0xd4]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop1.s
new file mode 100644
index 0000000000000..52f249b6f423b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop1.s
@@ -0,0 +1,13768 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+v_nop
+// CHECK: [0x00,0x00,0x00,0x7e]
+
+v_mov_b32 v5, v1
+// CHECK: [0x01,0x03,0x0a,0x7e]
+
+v_mov_b32 v255, v1
+// CHECK: [0x01,0x03,0xfe,0x7f]
+
+v_mov_b32 v5, v255
+// CHECK: [0xff,0x03,0x0a,0x7e]
+
+v_mov_b32 v5, s1
+// CHECK: [0x01,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, s101
+// CHECK: [0x65,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, flat_scratch_lo
+// CHECK: [0x66,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, flat_scratch_hi
+// CHECK: [0x67,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, vcc_lo
+// CHECK: [0x6a,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, vcc_hi
+// CHECK: [0x6b,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, tba_lo
+// CHECK: [0x6c,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, tba_hi
+// CHECK: [0x6d,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, tma_lo
+// CHECK: [0x6e,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, tma_hi
+// CHECK: [0x6f,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, ttmp11
+// CHECK: [0x7b,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, m0
+// CHECK: [0x7c,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, exec_lo
+// CHECK: [0x7e,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, exec_hi
+// CHECK: [0x7f,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0
+// CHECK: [0x80,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, -1
+// CHECK: [0xc1,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0.5
+// CHECK: [0xf0,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, -4.0
+// CHECK: [0xf7,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_vccz
+// CHECK: [0xfb,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_execz
+// CHECK: [0xfc,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_scc
+// CHECK: [0xfd,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0xaf123456
+// CHECK: [0xff,0x02,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_mov_b32 v5, 0x3f717273
+// CHECK: [0xff,0x02,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_readfirstlane_b32 s5, v1
+// CHECK: [0x01,0x05,0x0a,0x7e]
+
+v_readfirstlane_b32 s101, v1
+// CHECK: [0x01,0x05,0xca,0x7e]
+
+v_readfirstlane_b32 flat_scratch_lo, v1
+// CHECK: [0x01,0x05,0xcc,0x7e]
+
+v_readfirstlane_b32 flat_scratch_hi, v1
+// CHECK: [0x01,0x05,0xce,0x7e]
+
+v_readfirstlane_b32 tba_lo, v1
+// CHECK: [0x01,0x05,0xd8,0x7e]
+
+v_readfirstlane_b32 tba_hi, v1
+// CHECK: [0x01,0x05,0xda,0x7e]
+
+v_readfirstlane_b32 tma_lo, v1
+// CHECK: [0x01,0x05,0xdc,0x7e]
+
+v_readfirstlane_b32 tma_hi, v1
+// CHECK: [0x01,0x05,0xde,0x7e]
+
+v_readfirstlane_b32 ttmp11, v1
+// CHECK: [0x01,0x05,0xf6,0x7e]
+
+v_readfirstlane_b32 s5, v255
+// CHECK: [0xff,0x05,0x0a,0x7e]
+
+v_readfirstlane_b32 s5, src_lds_direct
+// CHECK: [0xfe,0x04,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, v[1:2]
+// CHECK: [0x01,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64 v255, v[1:2]
+// CHECK: [0x01,0x07,0xfe,0x7f]
+
+v_cvt_i32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[2:3]
+// CHECK: [0x02,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[4:5]
+// CHECK: [0x04,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[100:101]
+// CHECK: [0x64,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, flat_scratch
+// CHECK: [0x66,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, vcc
+// CHECK: [0x6a,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, tba
+// CHECK: [0x6c,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, tma
+// CHECK: [0x6e,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, ttmp[10:11]
+// CHECK: [0x7a,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, exec
+// CHECK: [0x7e,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0
+// CHECK: [0x80,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, -1
+// CHECK: [0xc1,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0.5
+// CHECK: [0xf0,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, -4.0
+// CHECK: [0xf7,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_vccz
+// CHECK: [0xfb,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_execz
+// CHECK: [0xfc,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_scc
+// CHECK: [0xfd,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x06,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x06,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_i32 v[5:6], v1
+// CHECK: [0x01,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32 v[254:255], v1
+// CHECK: [0x01,0x09,0xfc,0x7f]
+
+v_cvt_f64_i32 v[5:6], v255
+// CHECK: [0xff,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], s1
+// CHECK: [0x01,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], s101
+// CHECK: [0x65,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], flat_scratch_lo
+// CHECK: [0x66,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], flat_scratch_hi
+// CHECK: [0x67,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], vcc_lo
+// CHECK: [0x6a,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], vcc_hi
+// CHECK: [0x6b,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], tba_lo
+// CHECK: [0x6c,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], tba_hi
+// CHECK: [0x6d,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], tma_lo
+// CHECK: [0x6e,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], tma_hi
+// CHECK: [0x6f,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], ttmp11
+// CHECK: [0x7b,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], m0
+// CHECK: [0x7c,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], exec_lo
+// CHECK: [0x7e,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], exec_hi
+// CHECK: [0x7f,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0
+// CHECK: [0x80,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], -1
+// CHECK: [0xc1,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0.5
+// CHECK: [0xf0,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], -4.0
+// CHECK: [0xf7,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_vccz
+// CHECK: [0xfb,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_execz
+// CHECK: [0xfc,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_scc
+// CHECK: [0xfd,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_lds_direct
+// CHECK: [0xfe,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0xaf123456
+// CHECK: [0xff,0x08,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_i32 v[5:6], 0x3f717273
+// CHECK: [0xff,0x08,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_i32 v5, v1
+// CHECK: [0x01,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32 v255, v1
+// CHECK: [0x01,0x0b,0xfe,0x7f]
+
+v_cvt_f32_i32 v5, v255
+// CHECK: [0xff,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, s1
+// CHECK: [0x01,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, s101
+// CHECK: [0x65,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, flat_scratch_lo
+// CHECK: [0x66,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, flat_scratch_hi
+// CHECK: [0x67,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, vcc_lo
+// CHECK: [0x6a,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, vcc_hi
+// CHECK: [0x6b,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, tba_lo
+// CHECK: [0x6c,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, tba_hi
+// CHECK: [0x6d,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, tma_lo
+// CHECK: [0x6e,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, tma_hi
+// CHECK: [0x6f,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, ttmp11
+// CHECK: [0x7b,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, m0
+// CHECK: [0x7c,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, exec_lo
+// CHECK: [0x7e,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, exec_hi
+// CHECK: [0x7f,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0
+// CHECK: [0x80,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, -1
+// CHECK: [0xc1,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0.5
+// CHECK: [0xf0,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, -4.0
+// CHECK: [0xf7,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_vccz
+// CHECK: [0xfb,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_execz
+// CHECK: [0xfc,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_scc
+// CHECK: [0xfd,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_lds_direct
+// CHECK: [0xfe,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0xaf123456
+// CHECK: [0xff,0x0a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_i32 v5, 0x3f717273
+// CHECK: [0xff,0x0a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_u32 v5, v1
+// CHECK: [0x01,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32 v255, v1
+// CHECK: [0x01,0x0d,0xfe,0x7f]
+
+v_cvt_f32_u32 v5, v255
+// CHECK: [0xff,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, s1
+// CHECK: [0x01,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, s101
+// CHECK: [0x65,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, flat_scratch_lo
+// CHECK: [0x66,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, flat_scratch_hi
+// CHECK: [0x67,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, vcc_lo
+// CHECK: [0x6a,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, vcc_hi
+// CHECK: [0x6b,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, tba_lo
+// CHECK: [0x6c,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, tba_hi
+// CHECK: [0x6d,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, tma_lo
+// CHECK: [0x6e,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, tma_hi
+// CHECK: [0x6f,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, ttmp11
+// CHECK: [0x7b,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, m0
+// CHECK: [0x7c,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, exec_lo
+// CHECK: [0x7e,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, exec_hi
+// CHECK: [0x7f,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0
+// CHECK: [0x80,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, -1
+// CHECK: [0xc1,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0.5
+// CHECK: [0xf0,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, -4.0
+// CHECK: [0xf7,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_vccz
+// CHECK: [0xfb,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_execz
+// CHECK: [0xfc,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_scc
+// CHECK: [0xfd,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_lds_direct
+// CHECK: [0xfe,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0xaf123456
+// CHECK: [0xff,0x0c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_u32 v5, 0x3f717273
+// CHECK: [0xff,0x0c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_u32_f32 v5, v1
+// CHECK: [0x01,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32 v255, v1
+// CHECK: [0x01,0x0f,0xfe,0x7f]
+
+v_cvt_u32_f32 v5, v255
+// CHECK: [0xff,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, s1
+// CHECK: [0x01,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, s101
+// CHECK: [0x65,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, tba_lo
+// CHECK: [0x6c,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, tba_hi
+// CHECK: [0x6d,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, tma_lo
+// CHECK: [0x6e,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, tma_hi
+// CHECK: [0x6f,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, ttmp11
+// CHECK: [0x7b,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, m0
+// CHECK: [0x7c,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, exec_lo
+// CHECK: [0x7e,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, exec_hi
+// CHECK: [0x7f,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0
+// CHECK: [0x80,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, -1
+// CHECK: [0xc1,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0.5
+// CHECK: [0xf0,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, -4.0
+// CHECK: [0xf7,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_vccz
+// CHECK: [0xfb,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_execz
+// CHECK: [0xfc,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_scc
+// CHECK: [0xfd,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x0e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x0e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_i32_f32 v5, v1
+// CHECK: [0x01,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32 v255, v1
+// CHECK: [0x01,0x11,0xfe,0x7f]
+
+v_cvt_i32_f32 v5, v255
+// CHECK: [0xff,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, s1
+// CHECK: [0x01,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, s101
+// CHECK: [0x65,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, tba_lo
+// CHECK: [0x6c,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, tba_hi
+// CHECK: [0x6d,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, tma_lo
+// CHECK: [0x6e,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, tma_hi
+// CHECK: [0x6f,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, ttmp11
+// CHECK: [0x7b,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, m0
+// CHECK: [0x7c,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0
+// CHECK: [0x80,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, -1
+// CHECK: [0xc1,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x10,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x10,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f16_f32 v5, v1
+// CHECK: [0x01,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v255, v1
+// CHECK: [0x01,0x15,0xfe,0x7f]
+
+v_cvt_f16_f32 v5, v255
+// CHECK: [0xff,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s1
+// CHECK: [0x01,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s101
+// CHECK: [0x65,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_lo
+// CHECK: [0x6a,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_hi
+// CHECK: [0x6b,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, tba_lo
+// CHECK: [0x6c,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, tba_hi
+// CHECK: [0x6d,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, tma_lo
+// CHECK: [0x6e,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, tma_hi
+// CHECK: [0x6f,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, ttmp11
+// CHECK: [0x7b,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, m0
+// CHECK: [0x7c,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_lo
+// CHECK: [0x7e,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_hi
+// CHECK: [0x7f,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0
+// CHECK: [0x80,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, -1
+// CHECK: [0xc1,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0.5
+// CHECK: [0xf0,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, -4.0
+// CHECK: [0xf7,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_vccz
+// CHECK: [0xfb,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_execz
+// CHECK: [0xfc,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_scc
+// CHECK: [0xfd,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0xaf123456
+// CHECK: [0xff,0x14,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f16_f32 v5, 0x3f717273
+// CHECK: [0xff,0x14,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_f16 v5, v1
+// CHECK: [0x01,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v255, v1
+// CHECK: [0x01,0x17,0xfe,0x7f]
+
+v_cvt_f32_f16 v5, v255
+// CHECK: [0xff,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s1
+// CHECK: [0x01,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s101
+// CHECK: [0x65,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_lo
+// CHECK: [0x6a,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_hi
+// CHECK: [0x6b,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, tba_lo
+// CHECK: [0x6c,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, tba_hi
+// CHECK: [0x6d,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, tma_lo
+// CHECK: [0x6e,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, tma_hi
+// CHECK: [0x6f,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, ttmp11
+// CHECK: [0x7b,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, m0
+// CHECK: [0x7c,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_lo
+// CHECK: [0x7e,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_hi
+// CHECK: [0x7f,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, 0
+// CHECK: [0x80,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, -1
+// CHECK: [0xc1,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, 0.5
+// CHECK: [0xf0,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, -4.0
+// CHECK: [0xf7,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_vccz
+// CHECK: [0xfb,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_execz
+// CHECK: [0xfc,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_scc
+// CHECK: [0xfd,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, 0xfe0b
+// CHECK: [0xff,0x16,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f32_f16 v5, 0x3456
+// CHECK: [0xff,0x16,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_rpi_i32_f32 v5, v1
+// CHECK: [0x01,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v255, v1
+// CHECK: [0x01,0x19,0xfe,0x7f]
+
+v_cvt_rpi_i32_f32 v5, v255
+// CHECK: [0xff,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s1
+// CHECK: [0x01,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s101
+// CHECK: [0x65,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, tba_lo
+// CHECK: [0x6c,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, tba_hi
+// CHECK: [0x6d,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, tma_lo
+// CHECK: [0x6e,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, tma_hi
+// CHECK: [0x6f,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, ttmp11
+// CHECK: [0x7b,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, m0
+// CHECK: [0x7c,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0
+// CHECK: [0x80,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, -1
+// CHECK: [0xc1,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x18,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_rpi_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x18,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_flr_i32_f32 v5, v1
+// CHECK: [0x01,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v255, v1
+// CHECK: [0x01,0x1b,0xfe,0x7f]
+
+v_cvt_flr_i32_f32 v5, v255
+// CHECK: [0xff,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s1
+// CHECK: [0x01,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s101
+// CHECK: [0x65,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, tba_lo
+// CHECK: [0x6c,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, tba_hi
+// CHECK: [0x6d,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, tma_lo
+// CHECK: [0x6e,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, tma_hi
+// CHECK: [0x6f,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, ttmp11
+// CHECK: [0x7b,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, m0
+// CHECK: [0x7c,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0
+// CHECK: [0x80,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, -1
+// CHECK: [0xc1,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x1a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_flr_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x1a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_off_f32_i4 v5, v1
+// CHECK: [0x01,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v255, v1
+// CHECK: [0x01,0x1d,0xfe,0x7f]
+
+v_cvt_off_f32_i4 v5, v255
+// CHECK: [0xff,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s1
+// CHECK: [0x01,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s101
+// CHECK: [0x65,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, flat_scratch_lo
+// CHECK: [0x66,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, flat_scratch_hi
+// CHECK: [0x67,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_lo
+// CHECK: [0x6a,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_hi
+// CHECK: [0x6b,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, tba_lo
+// CHECK: [0x6c,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, tba_hi
+// CHECK: [0x6d,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, tma_lo
+// CHECK: [0x6e,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, tma_hi
+// CHECK: [0x6f,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, ttmp11
+// CHECK: [0x7b,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, m0
+// CHECK: [0x7c,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_lo
+// CHECK: [0x7e,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_hi
+// CHECK: [0x7f,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0
+// CHECK: [0x80,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, -1
+// CHECK: [0xc1,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0.5
+// CHECK: [0xf0,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, -4.0
+// CHECK: [0xf7,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_vccz
+// CHECK: [0xfb,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_execz
+// CHECK: [0xfc,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_scc
+// CHECK: [0xfd,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_lds_direct
+// CHECK: [0xfe,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0x4f
+// CHECK: [0xff,0x1c,0x0a,0x7e,0x4f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4 v5, 0x41
+// CHECK: [0xff,0x1c,0x0a,0x7e,0x41,0x00,0x00,0x00]
+
+v_cvt_f32_f64 v5, v[1:2]
+// CHECK: [0x01,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v255, v[1:2]
+// CHECK: [0x01,0x1f,0xfe,0x7f]
+
+v_cvt_f32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[2:3]
+// CHECK: [0x02,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[4:5]
+// CHECK: [0x04,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[100:101]
+// CHECK: [0x64,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, flat_scratch
+// CHECK: [0x66,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, vcc
+// CHECK: [0x6a,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, tba
+// CHECK: [0x6c,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, tma
+// CHECK: [0x6e,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, ttmp[10:11]
+// CHECK: [0x7a,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, exec
+// CHECK: [0x7e,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0
+// CHECK: [0x80,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, -1
+// CHECK: [0xc1,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0.5
+// CHECK: [0xf0,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, -4.0
+// CHECK: [0xf7,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_vccz
+// CHECK: [0xfb,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_execz
+// CHECK: [0xfc,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_scc
+// CHECK: [0xfd,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x1e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x1e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_f32 v[5:6], v1
+// CHECK: [0x01,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[254:255], v1
+// CHECK: [0x01,0x21,0xfc,0x7f]
+
+v_cvt_f64_f32 v[5:6], v255
+// CHECK: [0xff,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s1
+// CHECK: [0x01,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s101
+// CHECK: [0x65,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], flat_scratch_lo
+// CHECK: [0x66,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], flat_scratch_hi
+// CHECK: [0x67,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_lo
+// CHECK: [0x6a,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_hi
+// CHECK: [0x6b,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], tba_lo
+// CHECK: [0x6c,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], tba_hi
+// CHECK: [0x6d,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], tma_lo
+// CHECK: [0x6e,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], tma_hi
+// CHECK: [0x6f,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], ttmp11
+// CHECK: [0x7b,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], m0
+// CHECK: [0x7c,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_lo
+// CHECK: [0x7e,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_hi
+// CHECK: [0x7f,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0
+// CHECK: [0x80,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], -1
+// CHECK: [0xc1,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0.5
+// CHECK: [0xf0,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], -4.0
+// CHECK: [0xf7,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_vccz
+// CHECK: [0xfb,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_execz
+// CHECK: [0xfc,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_scc
+// CHECK: [0xfd,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_lds_direct
+// CHECK: [0xfe,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0xaf123456
+// CHECK: [0xff,0x20,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_f32 v[5:6], 0x3f717273
+// CHECK: [0xff,0x20,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte0 v5, v1
+// CHECK: [0x01,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v255, v1
+// CHECK: [0x01,0x23,0xfe,0x7f]
+
+v_cvt_f32_ubyte0 v5, v255
+// CHECK: [0xff,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s1
+// CHECK: [0x01,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s101
+// CHECK: [0x65,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, flat_scratch_lo
+// CHECK: [0x66,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, flat_scratch_hi
+// CHECK: [0x67,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_lo
+// CHECK: [0x6a,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_hi
+// CHECK: [0x6b,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, tba_lo
+// CHECK: [0x6c,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, tba_hi
+// CHECK: [0x6d,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, tma_lo
+// CHECK: [0x6e,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, tma_hi
+// CHECK: [0x6f,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, ttmp11
+// CHECK: [0x7b,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, m0
+// CHECK: [0x7c,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_lo
+// CHECK: [0x7e,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_hi
+// CHECK: [0x7f,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0
+// CHECK: [0x80,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, -1
+// CHECK: [0xc1,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0.5
+// CHECK: [0xf0,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, -4.0
+// CHECK: [0xf7,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_vccz
+// CHECK: [0xfb,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_execz
+// CHECK: [0xfc,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_scc
+// CHECK: [0xfd,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_lds_direct
+// CHECK: [0xfe,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0xaf123456
+// CHECK: [0xff,0x22,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte0 v5, 0x3f717273
+// CHECK: [0xff,0x22,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte1 v5, v1
+// CHECK: [0x01,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v255, v1
+// CHECK: [0x01,0x25,0xfe,0x7f]
+
+v_cvt_f32_ubyte1 v5, v255
+// CHECK: [0xff,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s1
+// CHECK: [0x01,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s101
+// CHECK: [0x65,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, flat_scratch_lo
+// CHECK: [0x66,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, flat_scratch_hi
+// CHECK: [0x67,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_lo
+// CHECK: [0x6a,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_hi
+// CHECK: [0x6b,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, tba_lo
+// CHECK: [0x6c,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, tba_hi
+// CHECK: [0x6d,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, tma_lo
+// CHECK: [0x6e,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, tma_hi
+// CHECK: [0x6f,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, ttmp11
+// CHECK: [0x7b,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, m0
+// CHECK: [0x7c,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_lo
+// CHECK: [0x7e,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_hi
+// CHECK: [0x7f,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0
+// CHECK: [0x80,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, -1
+// CHECK: [0xc1,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0.5
+// CHECK: [0xf0,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, -4.0
+// CHECK: [0xf7,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_vccz
+// CHECK: [0xfb,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_execz
+// CHECK: [0xfc,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_scc
+// CHECK: [0xfd,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_lds_direct
+// CHECK: [0xfe,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0xaf123456
+// CHECK: [0xff,0x24,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte1 v5, 0x3f717273
+// CHECK: [0xff,0x24,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte2 v5, v1
+// CHECK: [0x01,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v255, v1
+// CHECK: [0x01,0x27,0xfe,0x7f]
+
+v_cvt_f32_ubyte2 v5, v255
+// CHECK: [0xff,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s1
+// CHECK: [0x01,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s101
+// CHECK: [0x65,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, flat_scratch_lo
+// CHECK: [0x66,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, flat_scratch_hi
+// CHECK: [0x67,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_lo
+// CHECK: [0x6a,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_hi
+// CHECK: [0x6b,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, tba_lo
+// CHECK: [0x6c,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, tba_hi
+// CHECK: [0x6d,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, tma_lo
+// CHECK: [0x6e,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, tma_hi
+// CHECK: [0x6f,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, ttmp11
+// CHECK: [0x7b,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, m0
+// CHECK: [0x7c,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_lo
+// CHECK: [0x7e,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_hi
+// CHECK: [0x7f,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0
+// CHECK: [0x80,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, -1
+// CHECK: [0xc1,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0.5
+// CHECK: [0xf0,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, -4.0
+// CHECK: [0xf7,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_vccz
+// CHECK: [0xfb,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_execz
+// CHECK: [0xfc,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_scc
+// CHECK: [0xfd,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_lds_direct
+// CHECK: [0xfe,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0xaf123456
+// CHECK: [0xff,0x26,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte2 v5, 0x3f717273
+// CHECK: [0xff,0x26,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte3 v5, v1
+// CHECK: [0x01,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v255, v1
+// CHECK: [0x01,0x29,0xfe,0x7f]
+
+v_cvt_f32_ubyte3 v5, v255
+// CHECK: [0xff,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s1
+// CHECK: [0x01,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s101
+// CHECK: [0x65,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, flat_scratch_lo
+// CHECK: [0x66,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, flat_scratch_hi
+// CHECK: [0x67,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_lo
+// CHECK: [0x6a,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_hi
+// CHECK: [0x6b,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, tba_lo
+// CHECK: [0x6c,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, tba_hi
+// CHECK: [0x6d,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, tma_lo
+// CHECK: [0x6e,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, tma_hi
+// CHECK: [0x6f,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, ttmp11
+// CHECK: [0x7b,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, m0
+// CHECK: [0x7c,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_lo
+// CHECK: [0x7e,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_hi
+// CHECK: [0x7f,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0
+// CHECK: [0x80,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, -1
+// CHECK: [0xc1,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0.5
+// CHECK: [0xf0,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, -4.0
+// CHECK: [0xf7,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_vccz
+// CHECK: [0xfb,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_execz
+// CHECK: [0xfc,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_scc
+// CHECK: [0xfd,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_lds_direct
+// CHECK: [0xfe,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0xaf123456
+// CHECK: [0xff,0x28,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte3 v5, 0x3f717273
+// CHECK: [0xff,0x28,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_u32_f64 v5, v[1:2]
+// CHECK: [0x01,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v255, v[1:2]
+// CHECK: [0x01,0x2b,0xfe,0x7f]
+
+v_cvt_u32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[2:3]
+// CHECK: [0x02,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[4:5]
+// CHECK: [0x04,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[100:101]
+// CHECK: [0x64,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, flat_scratch
+// CHECK: [0x66,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, vcc
+// CHECK: [0x6a,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, tba
+// CHECK: [0x6c,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, tma
+// CHECK: [0x6e,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, ttmp[10:11]
+// CHECK: [0x7a,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, exec
+// CHECK: [0x7e,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0
+// CHECK: [0x80,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, -1
+// CHECK: [0xc1,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0.5
+// CHECK: [0xf0,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, -4.0
+// CHECK: [0xf7,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_vccz
+// CHECK: [0xfb,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_execz
+// CHECK: [0xfc,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_scc
+// CHECK: [0xfd,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x2a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x2a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_u32 v[5:6], v1
+// CHECK: [0x01,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[254:255], v1
+// CHECK: [0x01,0x2d,0xfc,0x7f]
+
+v_cvt_f64_u32 v[5:6], v255
+// CHECK: [0xff,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s1
+// CHECK: [0x01,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s101
+// CHECK: [0x65,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], flat_scratch_lo
+// CHECK: [0x66,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], flat_scratch_hi
+// CHECK: [0x67,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_lo
+// CHECK: [0x6a,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_hi
+// CHECK: [0x6b,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], tba_lo
+// CHECK: [0x6c,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], tba_hi
+// CHECK: [0x6d,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], tma_lo
+// CHECK: [0x6e,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], tma_hi
+// CHECK: [0x6f,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], ttmp11
+// CHECK: [0x7b,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], m0
+// CHECK: [0x7c,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_lo
+// CHECK: [0x7e,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_hi
+// CHECK: [0x7f,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0
+// CHECK: [0x80,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], -1
+// CHECK: [0xc1,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0.5
+// CHECK: [0xf0,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], -4.0
+// CHECK: [0xf7,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_vccz
+// CHECK: [0xfb,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_execz
+// CHECK: [0xfc,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_scc
+// CHECK: [0xfd,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_lds_direct
+// CHECK: [0xfe,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0xaf123456
+// CHECK: [0xff,0x2c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_u32 v[5:6], 0x3f717273
+// CHECK: [0xff,0x2c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_trunc_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x2f,0xfc,0x7f]
+
+v_trunc_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], vcc
+// CHECK: [0x6a,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], tba
+// CHECK: [0x6c,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], tma
+// CHECK: [0x6e,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], exec
+// CHECK: [0x7e,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0
+// CHECK: [0x80,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], -1
+// CHECK: [0xc1,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x2e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_trunc_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x2e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ceil_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x31,0xfc,0x7f]
+
+v_ceil_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], vcc
+// CHECK: [0x6a,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], tba
+// CHECK: [0x6c,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], tma
+// CHECK: [0x6e,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], exec
+// CHECK: [0x7e,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0
+// CHECK: [0x80,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], -1
+// CHECK: [0xc1,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x30,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ceil_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x30,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rndne_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x33,0xfc,0x7f]
+
+v_rndne_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], vcc
+// CHECK: [0x6a,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], tba
+// CHECK: [0x6c,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], tma
+// CHECK: [0x6e,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], exec
+// CHECK: [0x7e,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0
+// CHECK: [0x80,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], -1
+// CHECK: [0xc1,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x32,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rndne_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x32,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_floor_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x35,0x0a,0x7e]
+
+v_floor_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x35,0xfc,0x7f]
+
+v_floor_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x35,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], vcc
+// CHECK: [0x6a,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], tba
+// CHECK: [0x6c,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], tma
+// CHECK: [0x6e,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], exec
+// CHECK: [0x7e,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0
+// CHECK: [0x80,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], -1
+// CHECK: [0xc1,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x34,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_floor_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x34,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_fract_f32 v5, v1
+// CHECK: [0x01,0x37,0x0a,0x7e]
+
+v_fract_f32 v255, v1
+// CHECK: [0x01,0x37,0xfe,0x7f]
+
+v_fract_f32 v5, v255
+// CHECK: [0xff,0x37,0x0a,0x7e]
+
+v_fract_f32 v5, s1
+// CHECK: [0x01,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, s101
+// CHECK: [0x65,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_lo
+// CHECK: [0x6a,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_hi
+// CHECK: [0x6b,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, tba_lo
+// CHECK: [0x6c,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, tba_hi
+// CHECK: [0x6d,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, tma_lo
+// CHECK: [0x6e,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, tma_hi
+// CHECK: [0x6f,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, ttmp11
+// CHECK: [0x7b,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, m0
+// CHECK: [0x7c,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, exec_lo
+// CHECK: [0x7e,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, exec_hi
+// CHECK: [0x7f,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, 0
+// CHECK: [0x80,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, -1
+// CHECK: [0xc1,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, 0.5
+// CHECK: [0xf0,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, -4.0
+// CHECK: [0xf7,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, src_vccz
+// CHECK: [0xfb,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, src_execz
+// CHECK: [0xfc,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, src_scc
+// CHECK: [0xfd,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, 0xaf123456
+// CHECK: [0xff,0x36,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_fract_f32 v5, 0x3f717273
+// CHECK: [0xff,0x36,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_trunc_f32 v5, v1
+// CHECK: [0x01,0x39,0x0a,0x7e]
+
+v_trunc_f32 v255, v1
+// CHECK: [0x01,0x39,0xfe,0x7f]
+
+v_trunc_f32 v5, v255
+// CHECK: [0xff,0x39,0x0a,0x7e]
+
+v_trunc_f32 v5, s1
+// CHECK: [0x01,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, s101
+// CHECK: [0x65,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_lo
+// CHECK: [0x6a,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_hi
+// CHECK: [0x6b,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, tba_lo
+// CHECK: [0x6c,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, tba_hi
+// CHECK: [0x6d,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, tma_lo
+// CHECK: [0x6e,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, tma_hi
+// CHECK: [0x6f,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, ttmp11
+// CHECK: [0x7b,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, m0
+// CHECK: [0x7c,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_lo
+// CHECK: [0x7e,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_hi
+// CHECK: [0x7f,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, 0
+// CHECK: [0x80,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, -1
+// CHECK: [0xc1,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, 0.5
+// CHECK: [0xf0,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, -4.0
+// CHECK: [0xf7,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, src_vccz
+// CHECK: [0xfb,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, src_execz
+// CHECK: [0xfc,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, src_scc
+// CHECK: [0xfd,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, 0xaf123456
+// CHECK: [0xff,0x38,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_trunc_f32 v5, 0x3f717273
+// CHECK: [0xff,0x38,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ceil_f32 v5, v1
+// CHECK: [0x01,0x3b,0x0a,0x7e]
+
+v_ceil_f32 v255, v1
+// CHECK: [0x01,0x3b,0xfe,0x7f]
+
+v_ceil_f32 v5, v255
+// CHECK: [0xff,0x3b,0x0a,0x7e]
+
+v_ceil_f32 v5, s1
+// CHECK: [0x01,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, s101
+// CHECK: [0x65,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_lo
+// CHECK: [0x6a,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_hi
+// CHECK: [0x6b,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, tba_lo
+// CHECK: [0x6c,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, tba_hi
+// CHECK: [0x6d,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, tma_lo
+// CHECK: [0x6e,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, tma_hi
+// CHECK: [0x6f,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, ttmp11
+// CHECK: [0x7b,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, m0
+// CHECK: [0x7c,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_lo
+// CHECK: [0x7e,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_hi
+// CHECK: [0x7f,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, 0
+// CHECK: [0x80,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, -1
+// CHECK: [0xc1,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, 0.5
+// CHECK: [0xf0,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, -4.0
+// CHECK: [0xf7,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, src_vccz
+// CHECK: [0xfb,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, src_execz
+// CHECK: [0xfc,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, src_scc
+// CHECK: [0xfd,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, 0xaf123456
+// CHECK: [0xff,0x3a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ceil_f32 v5, 0x3f717273
+// CHECK: [0xff,0x3a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rndne_f32 v5, v1
+// CHECK: [0x01,0x3d,0x0a,0x7e]
+
+v_rndne_f32 v255, v1
+// CHECK: [0x01,0x3d,0xfe,0x7f]
+
+v_rndne_f32 v5, v255
+// CHECK: [0xff,0x3d,0x0a,0x7e]
+
+v_rndne_f32 v5, s1
+// CHECK: [0x01,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, s101
+// CHECK: [0x65,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_lo
+// CHECK: [0x6a,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_hi
+// CHECK: [0x6b,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, tba_lo
+// CHECK: [0x6c,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, tba_hi
+// CHECK: [0x6d,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, tma_lo
+// CHECK: [0x6e,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, tma_hi
+// CHECK: [0x6f,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, ttmp11
+// CHECK: [0x7b,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, m0
+// CHECK: [0x7c,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_lo
+// CHECK: [0x7e,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_hi
+// CHECK: [0x7f,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, 0
+// CHECK: [0x80,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, -1
+// CHECK: [0xc1,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, 0.5
+// CHECK: [0xf0,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, -4.0
+// CHECK: [0xf7,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, src_vccz
+// CHECK: [0xfb,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, src_execz
+// CHECK: [0xfc,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, src_scc
+// CHECK: [0xfd,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, 0xaf123456
+// CHECK: [0xff,0x3c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rndne_f32 v5, 0x3f717273
+// CHECK: [0xff,0x3c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_floor_f32 v5, v1
+// CHECK: [0x01,0x3f,0x0a,0x7e]
+
+v_floor_f32 v255, v1
+// CHECK: [0x01,0x3f,0xfe,0x7f]
+
+v_floor_f32 v5, v255
+// CHECK: [0xff,0x3f,0x0a,0x7e]
+
+v_floor_f32 v5, s1
+// CHECK: [0x01,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, s101
+// CHECK: [0x65,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_lo
+// CHECK: [0x6a,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_hi
+// CHECK: [0x6b,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, tba_lo
+// CHECK: [0x6c,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, tba_hi
+// CHECK: [0x6d,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, tma_lo
+// CHECK: [0x6e,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, tma_hi
+// CHECK: [0x6f,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, ttmp11
+// CHECK: [0x7b,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, m0
+// CHECK: [0x7c,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, exec_lo
+// CHECK: [0x7e,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, exec_hi
+// CHECK: [0x7f,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, 0
+// CHECK: [0x80,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, -1
+// CHECK: [0xc1,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, 0.5
+// CHECK: [0xf0,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, -4.0
+// CHECK: [0xf7,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, src_vccz
+// CHECK: [0xfb,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, src_execz
+// CHECK: [0xfc,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, src_scc
+// CHECK: [0xfd,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, 0xaf123456
+// CHECK: [0xff,0x3e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_floor_f32 v5, 0x3f717273
+// CHECK: [0xff,0x3e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_exp_f32 v5, v1
+// CHECK: [0x01,0x41,0x0a,0x7e]
+
+v_exp_f32 v255, v1
+// CHECK: [0x01,0x41,0xfe,0x7f]
+
+v_exp_f32 v5, v255
+// CHECK: [0xff,0x41,0x0a,0x7e]
+
+v_exp_f32 v5, s1
+// CHECK: [0x01,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, s101
+// CHECK: [0x65,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_lo
+// CHECK: [0x6a,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_hi
+// CHECK: [0x6b,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, tba_lo
+// CHECK: [0x6c,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, tba_hi
+// CHECK: [0x6d,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, tma_lo
+// CHECK: [0x6e,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, tma_hi
+// CHECK: [0x6f,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, ttmp11
+// CHECK: [0x7b,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, m0
+// CHECK: [0x7c,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, exec_lo
+// CHECK: [0x7e,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, exec_hi
+// CHECK: [0x7f,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, 0
+// CHECK: [0x80,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, -1
+// CHECK: [0xc1,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, 0.5
+// CHECK: [0xf0,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, -4.0
+// CHECK: [0xf7,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, src_vccz
+// CHECK: [0xfb,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, src_execz
+// CHECK: [0xfc,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, src_scc
+// CHECK: [0xfd,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, 0xaf123456
+// CHECK: [0xff,0x40,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_exp_f32 v5, 0x3f717273
+// CHECK: [0xff,0x40,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_log_f32 v5, v1
+// CHECK: [0x01,0x43,0x0a,0x7e]
+
+v_log_f32 v255, v1
+// CHECK: [0x01,0x43,0xfe,0x7f]
+
+v_log_f32 v5, v255
+// CHECK: [0xff,0x43,0x0a,0x7e]
+
+v_log_f32 v5, s1
+// CHECK: [0x01,0x42,0x0a,0x7e]
+
+v_log_f32 v5, s101
+// CHECK: [0x65,0x42,0x0a,0x7e]
+
+v_log_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x42,0x0a,0x7e]
+
+v_log_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x42,0x0a,0x7e]
+
+v_log_f32 v5, vcc_lo
+// CHECK: [0x6a,0x42,0x0a,0x7e]
+
+v_log_f32 v5, vcc_hi
+// CHECK: [0x6b,0x42,0x0a,0x7e]
+
+v_log_f32 v5, tba_lo
+// CHECK: [0x6c,0x42,0x0a,0x7e]
+
+v_log_f32 v5, tba_hi
+// CHECK: [0x6d,0x42,0x0a,0x7e]
+
+v_log_f32 v5, tma_lo
+// CHECK: [0x6e,0x42,0x0a,0x7e]
+
+v_log_f32 v5, tma_hi
+// CHECK: [0x6f,0x42,0x0a,0x7e]
+
+v_log_f32 v5, ttmp11
+// CHECK: [0x7b,0x42,0x0a,0x7e]
+
+v_log_f32 v5, m0
+// CHECK: [0x7c,0x42,0x0a,0x7e]
+
+v_log_f32 v5, exec_lo
+// CHECK: [0x7e,0x42,0x0a,0x7e]
+
+v_log_f32 v5, exec_hi
+// CHECK: [0x7f,0x42,0x0a,0x7e]
+
+v_log_f32 v5, 0
+// CHECK: [0x80,0x42,0x0a,0x7e]
+
+v_log_f32 v5, -1
+// CHECK: [0xc1,0x42,0x0a,0x7e]
+
+v_log_f32 v5, 0.5
+// CHECK: [0xf0,0x42,0x0a,0x7e]
+
+v_log_f32 v5, -4.0
+// CHECK: [0xf7,0x42,0x0a,0x7e]
+
+v_log_f32 v5, src_vccz
+// CHECK: [0xfb,0x42,0x0a,0x7e]
+
+v_log_f32 v5, src_execz
+// CHECK: [0xfc,0x42,0x0a,0x7e]
+
+v_log_f32 v5, src_scc
+// CHECK: [0xfd,0x42,0x0a,0x7e]
+
+v_log_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x42,0x0a,0x7e]
+
+v_log_f32 v5, 0xaf123456
+// CHECK: [0xff,0x42,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_log_f32 v5, 0x3f717273
+// CHECK: [0xff,0x42,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_f32 v5, v1
+// CHECK: [0x01,0x45,0x0a,0x7e]
+
+v_rcp_f32 v255, v1
+// CHECK: [0x01,0x45,0xfe,0x7f]
+
+v_rcp_f32 v5, v255
+// CHECK: [0xff,0x45,0x0a,0x7e]
+
+v_rcp_f32 v5, s1
+// CHECK: [0x01,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, s101
+// CHECK: [0x65,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_lo
+// CHECK: [0x6a,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_hi
+// CHECK: [0x6b,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, tba_lo
+// CHECK: [0x6c,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, tba_hi
+// CHECK: [0x6d,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, tma_lo
+// CHECK: [0x6e,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, tma_hi
+// CHECK: [0x6f,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, ttmp11
+// CHECK: [0x7b,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, m0
+// CHECK: [0x7c,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_lo
+// CHECK: [0x7e,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_hi
+// CHECK: [0x7f,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, 0
+// CHECK: [0x80,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, -1
+// CHECK: [0xc1,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, 0.5
+// CHECK: [0xf0,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, -4.0
+// CHECK: [0xf7,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, src_vccz
+// CHECK: [0xfb,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, src_execz
+// CHECK: [0xfc,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, src_scc
+// CHECK: [0xfd,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, 0xaf123456
+// CHECK: [0xff,0x44,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_f32 v5, 0x3f717273
+// CHECK: [0xff,0x44,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_iflag_f32 v5, v1
+// CHECK: [0x01,0x47,0x0a,0x7e]
+
+v_rcp_iflag_f32 v255, v1
+// CHECK: [0x01,0x47,0xfe,0x7f]
+
+v_rcp_iflag_f32 v5, v255
+// CHECK: [0xff,0x47,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s1
+// CHECK: [0x01,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s101
+// CHECK: [0x65,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_lo
+// CHECK: [0x6a,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_hi
+// CHECK: [0x6b,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, tba_lo
+// CHECK: [0x6c,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, tba_hi
+// CHECK: [0x6d,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, tma_lo
+// CHECK: [0x6e,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, tma_hi
+// CHECK: [0x6f,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, ttmp11
+// CHECK: [0x7b,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, m0
+// CHECK: [0x7c,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_lo
+// CHECK: [0x7e,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_hi
+// CHECK: [0x7f,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0
+// CHECK: [0x80,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, -1
+// CHECK: [0xc1,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0.5
+// CHECK: [0xf0,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, -4.0
+// CHECK: [0xf7,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_vccz
+// CHECK: [0xfb,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_execz
+// CHECK: [0xfc,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_scc
+// CHECK: [0xfd,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0xaf123456
+// CHECK: [0xff,0x46,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_iflag_f32 v5, 0x3f717273
+// CHECK: [0xff,0x46,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_f32 v5, v1
+// CHECK: [0x01,0x49,0x0a,0x7e]
+
+v_rsq_f32 v255, v1
+// CHECK: [0x01,0x49,0xfe,0x7f]
+
+v_rsq_f32 v5, v255
+// CHECK: [0xff,0x49,0x0a,0x7e]
+
+v_rsq_f32 v5, s1
+// CHECK: [0x01,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, s101
+// CHECK: [0x65,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_lo
+// CHECK: [0x6a,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_hi
+// CHECK: [0x6b,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, tba_lo
+// CHECK: [0x6c,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, tba_hi
+// CHECK: [0x6d,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, tma_lo
+// CHECK: [0x6e,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, tma_hi
+// CHECK: [0x6f,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, ttmp11
+// CHECK: [0x7b,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, m0
+// CHECK: [0x7c,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_lo
+// CHECK: [0x7e,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_hi
+// CHECK: [0x7f,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, 0
+// CHECK: [0x80,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, -1
+// CHECK: [0xc1,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, 0.5
+// CHECK: [0xf0,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, -4.0
+// CHECK: [0xf7,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, src_vccz
+// CHECK: [0xfb,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, src_execz
+// CHECK: [0xfc,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, src_scc
+// CHECK: [0xfd,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, 0xaf123456
+// CHECK: [0xff,0x48,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_f32 v5, 0x3f717273
+// CHECK: [0xff,0x48,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x4b,0x0a,0x7e]
+
+v_rcp_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x4b,0xfc,0x7f]
+
+v_rcp_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x4b,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], vcc
+// CHECK: [0x6a,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], tba
+// CHECK: [0x6c,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], tma
+// CHECK: [0x6e,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], exec
+// CHECK: [0x7e,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0
+// CHECK: [0x80,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], -1
+// CHECK: [0xc1,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x4a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x4a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x4d,0x0a,0x7e]
+
+v_rsq_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x4d,0xfc,0x7f]
+
+v_rsq_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x4d,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], vcc
+// CHECK: [0x6a,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], tba
+// CHECK: [0x6c,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], tma
+// CHECK: [0x6e,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], exec
+// CHECK: [0x7e,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0
+// CHECK: [0x80,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], -1
+// CHECK: [0xc1,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x4c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x4c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sqrt_f32 v5, v1
+// CHECK: [0x01,0x4f,0x0a,0x7e]
+
+v_sqrt_f32 v255, v1
+// CHECK: [0x01,0x4f,0xfe,0x7f]
+
+v_sqrt_f32 v5, v255
+// CHECK: [0xff,0x4f,0x0a,0x7e]
+
+v_sqrt_f32 v5, s1
+// CHECK: [0x01,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, s101
+// CHECK: [0x65,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_lo
+// CHECK: [0x6a,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_hi
+// CHECK: [0x6b,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, tba_lo
+// CHECK: [0x6c,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, tba_hi
+// CHECK: [0x6d,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, tma_lo
+// CHECK: [0x6e,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, tma_hi
+// CHECK: [0x6f,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, ttmp11
+// CHECK: [0x7b,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, m0
+// CHECK: [0x7c,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_lo
+// CHECK: [0x7e,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_hi
+// CHECK: [0x7f,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0
+// CHECK: [0x80,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, -1
+// CHECK: [0xc1,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0.5
+// CHECK: [0xf0,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, -4.0
+// CHECK: [0xf7,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_vccz
+// CHECK: [0xfb,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_execz
+// CHECK: [0xfc,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_scc
+// CHECK: [0xfd,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0xaf123456
+// CHECK: [0xff,0x4e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f32 v5, 0x3f717273
+// CHECK: [0xff,0x4e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sqrt_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x51,0x0a,0x7e]
+
+v_sqrt_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x51,0xfc,0x7f]
+
+v_sqrt_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x51,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], vcc
+// CHECK: [0x6a,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], tba
+// CHECK: [0x6c,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], tma
+// CHECK: [0x6e,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], exec
+// CHECK: [0x7e,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0
+// CHECK: [0x80,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], -1
+// CHECK: [0xc1,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x50,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x50,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sin_f32 v5, v1
+// CHECK: [0x01,0x53,0x0a,0x7e]
+
+v_sin_f32 v255, v1
+// CHECK: [0x01,0x53,0xfe,0x7f]
+
+v_sin_f32 v5, v255
+// CHECK: [0xff,0x53,0x0a,0x7e]
+
+v_sin_f32 v5, s1
+// CHECK: [0x01,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, s101
+// CHECK: [0x65,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_lo
+// CHECK: [0x6a,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_hi
+// CHECK: [0x6b,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, tba_lo
+// CHECK: [0x6c,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, tba_hi
+// CHECK: [0x6d,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, tma_lo
+// CHECK: [0x6e,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, tma_hi
+// CHECK: [0x6f,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, ttmp11
+// CHECK: [0x7b,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, m0
+// CHECK: [0x7c,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, exec_lo
+// CHECK: [0x7e,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, exec_hi
+// CHECK: [0x7f,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, 0
+// CHECK: [0x80,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, -1
+// CHECK: [0xc1,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, 0.5
+// CHECK: [0xf0,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, -4.0
+// CHECK: [0xf7,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, src_vccz
+// CHECK: [0xfb,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, src_execz
+// CHECK: [0xfc,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, src_scc
+// CHECK: [0xfd,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, 0xaf123456
+// CHECK: [0xff,0x52,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sin_f32 v5, 0x3f717273
+// CHECK: [0xff,0x52,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cos_f32 v5, v1
+// CHECK: [0x01,0x55,0x0a,0x7e]
+
+v_cos_f32 v255, v1
+// CHECK: [0x01,0x55,0xfe,0x7f]
+
+v_cos_f32 v5, v255
+// CHECK: [0xff,0x55,0x0a,0x7e]
+
+v_cos_f32 v5, s1
+// CHECK: [0x01,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, s101
+// CHECK: [0x65,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_lo
+// CHECK: [0x6a,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_hi
+// CHECK: [0x6b,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, tba_lo
+// CHECK: [0x6c,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, tba_hi
+// CHECK: [0x6d,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, tma_lo
+// CHECK: [0x6e,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, tma_hi
+// CHECK: [0x6f,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, ttmp11
+// CHECK: [0x7b,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, m0
+// CHECK: [0x7c,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, exec_lo
+// CHECK: [0x7e,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, exec_hi
+// CHECK: [0x7f,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, 0
+// CHECK: [0x80,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, -1
+// CHECK: [0xc1,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, 0.5
+// CHECK: [0xf0,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, -4.0
+// CHECK: [0xf7,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, src_vccz
+// CHECK: [0xfb,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, src_execz
+// CHECK: [0xfc,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, src_scc
+// CHECK: [0xfd,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, 0xaf123456
+// CHECK: [0xff,0x54,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cos_f32 v5, 0x3f717273
+// CHECK: [0xff,0x54,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_not_b32 v5, v1
+// CHECK: [0x01,0x57,0x0a,0x7e]
+
+v_not_b32 v255, v1
+// CHECK: [0x01,0x57,0xfe,0x7f]
+
+v_not_b32 v5, v255
+// CHECK: [0xff,0x57,0x0a,0x7e]
+
+v_not_b32 v5, s1
+// CHECK: [0x01,0x56,0x0a,0x7e]
+
+v_not_b32 v5, s101
+// CHECK: [0x65,0x56,0x0a,0x7e]
+
+v_not_b32 v5, flat_scratch_lo
+// CHECK: [0x66,0x56,0x0a,0x7e]
+
+v_not_b32 v5, flat_scratch_hi
+// CHECK: [0x67,0x56,0x0a,0x7e]
+
+v_not_b32 v5, vcc_lo
+// CHECK: [0x6a,0x56,0x0a,0x7e]
+
+v_not_b32 v5, vcc_hi
+// CHECK: [0x6b,0x56,0x0a,0x7e]
+
+v_not_b32 v5, tba_lo
+// CHECK: [0x6c,0x56,0x0a,0x7e]
+
+v_not_b32 v5, tba_hi
+// CHECK: [0x6d,0x56,0x0a,0x7e]
+
+v_not_b32 v5, tma_lo
+// CHECK: [0x6e,0x56,0x0a,0x7e]
+
+v_not_b32 v5, tma_hi
+// CHECK: [0x6f,0x56,0x0a,0x7e]
+
+v_not_b32 v5, ttmp11
+// CHECK: [0x7b,0x56,0x0a,0x7e]
+
+v_not_b32 v5, m0
+// CHECK: [0x7c,0x56,0x0a,0x7e]
+
+v_not_b32 v5, exec_lo
+// CHECK: [0x7e,0x56,0x0a,0x7e]
+
+v_not_b32 v5, exec_hi
+// CHECK: [0x7f,0x56,0x0a,0x7e]
+
+v_not_b32 v5, 0
+// CHECK: [0x80,0x56,0x0a,0x7e]
+
+v_not_b32 v5, -1
+// CHECK: [0xc1,0x56,0x0a,0x7e]
+
+v_not_b32 v5, 0.5
+// CHECK: [0xf0,0x56,0x0a,0x7e]
+
+v_not_b32 v5, -4.0
+// CHECK: [0xf7,0x56,0x0a,0x7e]
+
+v_not_b32 v5, src_vccz
+// CHECK: [0xfb,0x56,0x0a,0x7e]
+
+v_not_b32 v5, src_execz
+// CHECK: [0xfc,0x56,0x0a,0x7e]
+
+v_not_b32 v5, src_scc
+// CHECK: [0xfd,0x56,0x0a,0x7e]
+
+v_not_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x56,0x0a,0x7e]
+
+v_not_b32 v5, 0xaf123456
+// CHECK: [0xff,0x56,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_not_b32 v5, 0x3f717273
+// CHECK: [0xff,0x56,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_bfrev_b32 v5, v1
+// CHECK: [0x01,0x59,0x0a,0x7e]
+
+v_bfrev_b32 v255, v1
+// CHECK: [0x01,0x59,0xfe,0x7f]
+
+v_bfrev_b32 v5, v255
+// CHECK: [0xff,0x59,0x0a,0x7e]
+
+v_bfrev_b32 v5, s1
+// CHECK: [0x01,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, s101
+// CHECK: [0x65,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, flat_scratch_lo
+// CHECK: [0x66,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, flat_scratch_hi
+// CHECK: [0x67,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_lo
+// CHECK: [0x6a,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_hi
+// CHECK: [0x6b,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, tba_lo
+// CHECK: [0x6c,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, tba_hi
+// CHECK: [0x6d,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, tma_lo
+// CHECK: [0x6e,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, tma_hi
+// CHECK: [0x6f,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, ttmp11
+// CHECK: [0x7b,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, m0
+// CHECK: [0x7c,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_lo
+// CHECK: [0x7e,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_hi
+// CHECK: [0x7f,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0
+// CHECK: [0x80,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, -1
+// CHECK: [0xc1,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0.5
+// CHECK: [0xf0,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, -4.0
+// CHECK: [0xf7,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_vccz
+// CHECK: [0xfb,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_execz
+// CHECK: [0xfc,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_scc
+// CHECK: [0xfd,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0xaf123456
+// CHECK: [0xff,0x58,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_bfrev_b32 v5, 0x3f717273
+// CHECK: [0xff,0x58,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbh_u32 v5, v1
+// CHECK: [0x01,0x5b,0x0a,0x7e]
+
+v_ffbh_u32 v255, v1
+// CHECK: [0x01,0x5b,0xfe,0x7f]
+
+v_ffbh_u32 v5, v255
+// CHECK: [0xff,0x5b,0x0a,0x7e]
+
+v_ffbh_u32 v5, s1
+// CHECK: [0x01,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, s101
+// CHECK: [0x65,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, flat_scratch_lo
+// CHECK: [0x66,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, flat_scratch_hi
+// CHECK: [0x67,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_lo
+// CHECK: [0x6a,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_hi
+// CHECK: [0x6b,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, tba_lo
+// CHECK: [0x6c,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, tba_hi
+// CHECK: [0x6d,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, tma_lo
+// CHECK: [0x6e,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, tma_hi
+// CHECK: [0x6f,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, ttmp11
+// CHECK: [0x7b,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, m0
+// CHECK: [0x7c,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_lo
+// CHECK: [0x7e,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_hi
+// CHECK: [0x7f,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0
+// CHECK: [0x80,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, -1
+// CHECK: [0xc1,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0.5
+// CHECK: [0xf0,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, -4.0
+// CHECK: [0xf7,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_vccz
+// CHECK: [0xfb,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_execz
+// CHECK: [0xfc,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_scc
+// CHECK: [0xfd,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_lds_direct
+// CHECK: [0xfe,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0xaf123456
+// CHECK: [0xff,0x5a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbh_u32 v5, 0x3f717273
+// CHECK: [0xff,0x5a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbl_b32 v5, v1
+// CHECK: [0x01,0x5d,0x0a,0x7e]
+
+v_ffbl_b32 v255, v1
+// CHECK: [0x01,0x5d,0xfe,0x7f]
+
+v_ffbl_b32 v5, v255
+// CHECK: [0xff,0x5d,0x0a,0x7e]
+
+v_ffbl_b32 v5, s1
+// CHECK: [0x01,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, s101
+// CHECK: [0x65,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, flat_scratch_lo
+// CHECK: [0x66,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, flat_scratch_hi
+// CHECK: [0x67,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_lo
+// CHECK: [0x6a,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_hi
+// CHECK: [0x6b,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, tba_lo
+// CHECK: [0x6c,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, tba_hi
+// CHECK: [0x6d,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, tma_lo
+// CHECK: [0x6e,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, tma_hi
+// CHECK: [0x6f,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, ttmp11
+// CHECK: [0x7b,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, m0
+// CHECK: [0x7c,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_lo
+// CHECK: [0x7e,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_hi
+// CHECK: [0x7f,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0
+// CHECK: [0x80,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, -1
+// CHECK: [0xc1,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0.5
+// CHECK: [0xf0,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, -4.0
+// CHECK: [0xf7,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_vccz
+// CHECK: [0xfb,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_execz
+// CHECK: [0xfc,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_scc
+// CHECK: [0xfd,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0xaf123456
+// CHECK: [0xff,0x5c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbl_b32 v5, 0x3f717273
+// CHECK: [0xff,0x5c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbh_i32 v5, v1
+// CHECK: [0x01,0x5f,0x0a,0x7e]
+
+v_ffbh_i32 v255, v1
+// CHECK: [0x01,0x5f,0xfe,0x7f]
+
+v_ffbh_i32 v5, v255
+// CHECK: [0xff,0x5f,0x0a,0x7e]
+
+v_ffbh_i32 v5, s1
+// CHECK: [0x01,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, s101
+// CHECK: [0x65,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, flat_scratch_lo
+// CHECK: [0x66,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, flat_scratch_hi
+// CHECK: [0x67,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_lo
+// CHECK: [0x6a,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_hi
+// CHECK: [0x6b,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, tba_lo
+// CHECK: [0x6c,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, tba_hi
+// CHECK: [0x6d,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, tma_lo
+// CHECK: [0x6e,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, tma_hi
+// CHECK: [0x6f,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, ttmp11
+// CHECK: [0x7b,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, m0
+// CHECK: [0x7c,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_lo
+// CHECK: [0x7e,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_hi
+// CHECK: [0x7f,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0
+// CHECK: [0x80,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, -1
+// CHECK: [0xc1,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0.5
+// CHECK: [0xf0,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, -4.0
+// CHECK: [0xf7,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_vccz
+// CHECK: [0xfb,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_execz
+// CHECK: [0xfc,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_scc
+// CHECK: [0xfd,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_lds_direct
+// CHECK: [0xfe,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0xaf123456
+// CHECK: [0xff,0x5e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbh_i32 v5, 0x3f717273
+// CHECK: [0xff,0x5e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_exp_i32_f64 v5, v[1:2]
+// CHECK: [0x01,0x61,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v255, v[1:2]
+// CHECK: [0x01,0x61,0xfe,0x7f]
+
+v_frexp_exp_i32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x61,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[2:3]
+// CHECK: [0x02,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[4:5]
+// CHECK: [0x04,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[100:101]
+// CHECK: [0x64,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, flat_scratch
+// CHECK: [0x66,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, vcc
+// CHECK: [0x6a,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, tba
+// CHECK: [0x6c,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, tma
+// CHECK: [0x6e,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, ttmp[10:11]
+// CHECK: [0x7a,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, exec
+// CHECK: [0x7e,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0
+// CHECK: [0x80,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, -1
+// CHECK: [0xc1,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0.5
+// CHECK: [0xf0,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, -4.0
+// CHECK: [0xf7,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_vccz
+// CHECK: [0xfb,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_execz
+// CHECK: [0xfc,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_scc
+// CHECK: [0xfd,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x60,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x60,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_mant_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x63,0x0a,0x7e]
+
+v_frexp_mant_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x63,0xfc,0x7f]
+
+v_frexp_mant_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x63,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], vcc
+// CHECK: [0x6a,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], tba
+// CHECK: [0x6c,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], tma
+// CHECK: [0x6e,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], exec
+// CHECK: [0x7e,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0
+// CHECK: [0x80,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], -1
+// CHECK: [0xc1,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x62,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x62,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_fract_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x65,0x0a,0x7e]
+
+v_fract_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x65,0xfc,0x7f]
+
+v_fract_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x65,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], vcc
+// CHECK: [0x6a,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], tba
+// CHECK: [0x6c,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], tma
+// CHECK: [0x6e,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], ttmp[10:11]
+// CHECK: [0x7a,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], exec
+// CHECK: [0x7e,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0
+// CHECK: [0x80,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], -1
+// CHECK: [0xc1,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x64,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_fract_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x64,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_exp_i32_f32 v5, v1
+// CHECK: [0x01,0x67,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v255, v1
+// CHECK: [0x01,0x67,0xfe,0x7f]
+
+v_frexp_exp_i32_f32 v5, v255
+// CHECK: [0xff,0x67,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s1
+// CHECK: [0x01,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s101
+// CHECK: [0x65,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, tba_lo
+// CHECK: [0x6c,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, tba_hi
+// CHECK: [0x6d,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, tma_lo
+// CHECK: [0x6e,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, tma_hi
+// CHECK: [0x6f,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, ttmp11
+// CHECK: [0x7b,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, m0
+// CHECK: [0x7c,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0
+// CHECK: [0x80,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, -1
+// CHECK: [0xc1,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x66,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x66,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_mant_f32 v5, v1
+// CHECK: [0x01,0x69,0x0a,0x7e]
+
+v_frexp_mant_f32 v255, v1
+// CHECK: [0x01,0x69,0xfe,0x7f]
+
+v_frexp_mant_f32 v5, v255
+// CHECK: [0xff,0x69,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s1
+// CHECK: [0x01,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s101
+// CHECK: [0x65,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_lo
+// CHECK: [0x6a,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_hi
+// CHECK: [0x6b,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, tba_lo
+// CHECK: [0x6c,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, tba_hi
+// CHECK: [0x6d,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, tma_lo
+// CHECK: [0x6e,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, tma_hi
+// CHECK: [0x6f,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, ttmp11
+// CHECK: [0x7b,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, m0
+// CHECK: [0x7c,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_lo
+// CHECK: [0x7e,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_hi
+// CHECK: [0x7f,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0
+// CHECK: [0x80,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, -1
+// CHECK: [0xc1,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0.5
+// CHECK: [0xf0,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, -4.0
+// CHECK: [0xf7,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_vccz
+// CHECK: [0xfb,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_execz
+// CHECK: [0xfc,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_scc
+// CHECK: [0xfd,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0xaf123456
+// CHECK: [0xff,0x68,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f32 v5, 0x3f717273
+// CHECK: [0xff,0x68,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_clrexcp
+// CHECK: [0x00,0x6a,0x00,0x7e]
+
+v_movreld_b32 v5, v1
+// CHECK: [0x01,0x6d,0x0a,0x7e]
+
+v_movreld_b32 v255, v1
+// CHECK: [0x01,0x6d,0xfe,0x7f]
+
+v_movreld_b32 v5, v255
+// CHECK: [0xff,0x6d,0x0a,0x7e]
+
+v_movreld_b32 v5, m0
+// CHECK: [0x7c,0x6c,0x0a,0x7e]
+
+v_movreld_b32 v5, 0
+// CHECK: [0x80,0x6c,0x0a,0x7e]
+
+v_movreld_b32 v5, -1
+// CHECK: [0xc1,0x6c,0x0a,0x7e]
+
+v_movreld_b32 v5, 0.5
+// CHECK: [0xf0,0x6c,0x0a,0x7e]
+
+v_movreld_b32 v5, -4.0
+// CHECK: [0xf7,0x6c,0x0a,0x7e]
+
+v_movreld_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x6c,0x0a,0x7e]
+
+v_movrels_b32 v5, v1
+// CHECK: [0x01,0x6f,0x0a,0x7e]
+
+v_movrels_b32 v255, v1
+// CHECK: [0x01,0x6f,0xfe,0x7f]
+
+v_movrels_b32 v5, v255
+// CHECK: [0xff,0x6f,0x0a,0x7e]
+
+v_movrelsd_b32 v5, v1
+// CHECK: [0x01,0x71,0x0a,0x7e]
+
+v_movrelsd_b32 v255, v1
+// CHECK: [0x01,0x71,0xfe,0x7f]
+
+v_movrelsd_b32 v5, v255
+// CHECK: [0xff,0x71,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, v1
+// CHECK: [0x01,0x73,0x0a,0x7e]
+
+v_cvt_f16_u16 v255, v1
+// CHECK: [0x01,0x73,0xfe,0x7f]
+
+v_cvt_f16_u16 v5, v255
+// CHECK: [0xff,0x73,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, s1
+// CHECK: [0x01,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, s101
+// CHECK: [0x65,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, flat_scratch_lo
+// CHECK: [0x66,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, flat_scratch_hi
+// CHECK: [0x67,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, vcc_lo
+// CHECK: [0x6a,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, vcc_hi
+// CHECK: [0x6b,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, tba_lo
+// CHECK: [0x6c,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, tba_hi
+// CHECK: [0x6d,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, tma_lo
+// CHECK: [0x6e,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, tma_hi
+// CHECK: [0x6f,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, ttmp11
+// CHECK: [0x7b,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, m0
+// CHECK: [0x7c,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, exec_lo
+// CHECK: [0x7e,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, exec_hi
+// CHECK: [0x7f,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, 0
+// CHECK: [0x80,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, -1
+// CHECK: [0xc1,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, 0.5
+// CHECK: [0xff,0x72,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_u16 v5, -4.0
+// CHECK: [0xff,0x72,0x0a,0x7e,0x00,0xc4,0x00,0x00]
+
+v_cvt_f16_u16 v5, src_vccz
+// CHECK: [0xfb,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, src_execz
+// CHECK: [0xfc,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, src_scc
+// CHECK: [0xfd,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, src_lds_direct
+// CHECK: [0xfe,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, 0xfe0b
+// CHECK: [0xff,0x72,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f16_u16 v5, 0x3456
+// CHECK: [0xff,0x72,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_f16_i16 v5, v1
+// CHECK: [0x01,0x75,0x0a,0x7e]
+
+v_cvt_f16_i16 v255, v1
+// CHECK: [0x01,0x75,0xfe,0x7f]
+
+v_cvt_f16_i16 v5, v255
+// CHECK: [0xff,0x75,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, s1
+// CHECK: [0x01,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, s101
+// CHECK: [0x65,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, flat_scratch_lo
+// CHECK: [0x66,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, flat_scratch_hi
+// CHECK: [0x67,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, vcc_lo
+// CHECK: [0x6a,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, vcc_hi
+// CHECK: [0x6b,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, tba_lo
+// CHECK: [0x6c,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, tba_hi
+// CHECK: [0x6d,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, tma_lo
+// CHECK: [0x6e,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, tma_hi
+// CHECK: [0x6f,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, ttmp11
+// CHECK: [0x7b,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, m0
+// CHECK: [0x7c,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, exec_lo
+// CHECK: [0x7e,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, exec_hi
+// CHECK: [0x7f,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, 0
+// CHECK: [0x80,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, -1
+// CHECK: [0xc1,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, 0.5
+// CHECK: [0xff,0x74,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_i16 v5, -4.0
+// CHECK: [0xff,0x74,0x0a,0x7e,0x00,0xc4,0x00,0x00]
+
+v_cvt_f16_i16 v5, src_vccz
+// CHECK: [0xfb,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, src_execz
+// CHECK: [0xfc,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, src_scc
+// CHECK: [0xfd,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, src_lds_direct
+// CHECK: [0xfe,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, 0xfe0b
+// CHECK: [0xff,0x74,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f16_i16 v5, 0x3456
+// CHECK: [0xff,0x74,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_u16_f16 v5, v1
+// CHECK: [0x01,0x77,0x0a,0x7e]
+
+v_cvt_u16_f16 v255, v1
+// CHECK: [0x01,0x77,0xfe,0x7f]
+
+v_cvt_u16_f16 v5, v255
+// CHECK: [0xff,0x77,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, s1
+// CHECK: [0x01,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, s101
+// CHECK: [0x65,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, vcc_lo
+// CHECK: [0x6a,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, vcc_hi
+// CHECK: [0x6b,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, tba_lo
+// CHECK: [0x6c,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, tba_hi
+// CHECK: [0x6d,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, tma_lo
+// CHECK: [0x6e,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, tma_hi
+// CHECK: [0x6f,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, ttmp11
+// CHECK: [0x7b,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, m0
+// CHECK: [0x7c,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, exec_lo
+// CHECK: [0x7e,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, exec_hi
+// CHECK: [0x7f,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, 0
+// CHECK: [0x80,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, -1
+// CHECK: [0xc1,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, 0.5
+// CHECK: [0xf0,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, -4.0
+// CHECK: [0xf7,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, src_vccz
+// CHECK: [0xfb,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, src_execz
+// CHECK: [0xfc,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, src_scc
+// CHECK: [0xfd,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, 0xfe0b
+// CHECK: [0xff,0x76,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_u16_f16 v5, 0x3456
+// CHECK: [0xff,0x76,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_i16_f16 v5, v1
+// CHECK: [0x01,0x79,0x0a,0x7e]
+
+v_cvt_i16_f16 v255, v1
+// CHECK: [0x01,0x79,0xfe,0x7f]
+
+v_cvt_i16_f16 v5, v255
+// CHECK: [0xff,0x79,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, s1
+// CHECK: [0x01,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, s101
+// CHECK: [0x65,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, vcc_lo
+// CHECK: [0x6a,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, vcc_hi
+// CHECK: [0x6b,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, tba_lo
+// CHECK: [0x6c,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, tba_hi
+// CHECK: [0x6d,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, tma_lo
+// CHECK: [0x6e,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, tma_hi
+// CHECK: [0x6f,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, ttmp11
+// CHECK: [0x7b,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, m0
+// CHECK: [0x7c,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, exec_lo
+// CHECK: [0x7e,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, exec_hi
+// CHECK: [0x7f,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, 0
+// CHECK: [0x80,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, -1
+// CHECK: [0xc1,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, 0.5
+// CHECK: [0xf0,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, -4.0
+// CHECK: [0xf7,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, src_vccz
+// CHECK: [0xfb,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, src_execz
+// CHECK: [0xfc,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, src_scc
+// CHECK: [0xfd,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, 0xfe0b
+// CHECK: [0xff,0x78,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_i16_f16 v5, 0x3456
+// CHECK: [0xff,0x78,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_rcp_f16 v5, v1
+// CHECK: [0x01,0x7b,0x0a,0x7e]
+
+v_rcp_f16 v255, v1
+// CHECK: [0x01,0x7b,0xfe,0x7f]
+
+v_rcp_f16 v5, v255
+// CHECK: [0xff,0x7b,0x0a,0x7e]
+
+v_rcp_f16 v5, s1
+// CHECK: [0x01,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, s101
+// CHECK: [0x65,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, vcc_lo
+// CHECK: [0x6a,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, vcc_hi
+// CHECK: [0x6b,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, tba_lo
+// CHECK: [0x6c,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, tba_hi
+// CHECK: [0x6d,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, tma_lo
+// CHECK: [0x6e,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, tma_hi
+// CHECK: [0x6f,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, ttmp11
+// CHECK: [0x7b,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, m0
+// CHECK: [0x7c,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, exec_lo
+// CHECK: [0x7e,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, exec_hi
+// CHECK: [0x7f,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, 0
+// CHECK: [0x80,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, -1
+// CHECK: [0xc1,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, 0.5
+// CHECK: [0xf0,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, -4.0
+// CHECK: [0xf7,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, src_vccz
+// CHECK: [0xfb,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, src_execz
+// CHECK: [0xfc,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, src_scc
+// CHECK: [0xfd,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, 0xfe0b
+// CHECK: [0xff,0x7a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rcp_f16 v5, 0x3456
+// CHECK: [0xff,0x7a,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_sqrt_f16 v5, v1
+// CHECK: [0x01,0x7d,0x0a,0x7e]
+
+v_sqrt_f16 v255, v1
+// CHECK: [0x01,0x7d,0xfe,0x7f]
+
+v_sqrt_f16 v5, v255
+// CHECK: [0xff,0x7d,0x0a,0x7e]
+
+v_sqrt_f16 v5, s1
+// CHECK: [0x01,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, s101
+// CHECK: [0x65,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, vcc_lo
+// CHECK: [0x6a,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, vcc_hi
+// CHECK: [0x6b,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, tba_lo
+// CHECK: [0x6c,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, tba_hi
+// CHECK: [0x6d,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, tma_lo
+// CHECK: [0x6e,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, tma_hi
+// CHECK: [0x6f,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, ttmp11
+// CHECK: [0x7b,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, m0
+// CHECK: [0x7c,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, exec_lo
+// CHECK: [0x7e,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, exec_hi
+// CHECK: [0x7f,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, 0
+// CHECK: [0x80,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, -1
+// CHECK: [0xc1,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, 0.5
+// CHECK: [0xf0,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, -4.0
+// CHECK: [0xf7,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, src_vccz
+// CHECK: [0xfb,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, src_execz
+// CHECK: [0xfc,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, src_scc
+// CHECK: [0xfd,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, 0xfe0b
+// CHECK: [0xff,0x7c,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sqrt_f16 v5, 0x3456
+// CHECK: [0xff,0x7c,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_rsq_f16 v5, v1
+// CHECK: [0x01,0x7f,0x0a,0x7e]
+
+v_rsq_f16 v255, v1
+// CHECK: [0x01,0x7f,0xfe,0x7f]
+
+v_rsq_f16 v5, v255
+// CHECK: [0xff,0x7f,0x0a,0x7e]
+
+v_rsq_f16 v5, s1
+// CHECK: [0x01,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, s101
+// CHECK: [0x65,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, vcc_lo
+// CHECK: [0x6a,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, vcc_hi
+// CHECK: [0x6b,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, tba_lo
+// CHECK: [0x6c,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, tba_hi
+// CHECK: [0x6d,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, tma_lo
+// CHECK: [0x6e,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, tma_hi
+// CHECK: [0x6f,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, ttmp11
+// CHECK: [0x7b,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, m0
+// CHECK: [0x7c,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, exec_lo
+// CHECK: [0x7e,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, exec_hi
+// CHECK: [0x7f,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, 0
+// CHECK: [0x80,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, -1
+// CHECK: [0xc1,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, 0.5
+// CHECK: [0xf0,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, -4.0
+// CHECK: [0xf7,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, src_vccz
+// CHECK: [0xfb,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, src_execz
+// CHECK: [0xfc,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, src_scc
+// CHECK: [0xfd,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, 0xfe0b
+// CHECK: [0xff,0x7e,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rsq_f16 v5, 0x3456
+// CHECK: [0xff,0x7e,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_log_f16 v5, v1
+// CHECK: [0x01,0x81,0x0a,0x7e]
+
+v_log_f16 v255, v1
+// CHECK: [0x01,0x81,0xfe,0x7f]
+
+v_log_f16 v5, v255
+// CHECK: [0xff,0x81,0x0a,0x7e]
+
+v_log_f16 v5, s1
+// CHECK: [0x01,0x80,0x0a,0x7e]
+
+v_log_f16 v5, s101
+// CHECK: [0x65,0x80,0x0a,0x7e]
+
+v_log_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x80,0x0a,0x7e]
+
+v_log_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x80,0x0a,0x7e]
+
+v_log_f16 v5, vcc_lo
+// CHECK: [0x6a,0x80,0x0a,0x7e]
+
+v_log_f16 v5, vcc_hi
+// CHECK: [0x6b,0x80,0x0a,0x7e]
+
+v_log_f16 v5, tba_lo
+// CHECK: [0x6c,0x80,0x0a,0x7e]
+
+v_log_f16 v5, tba_hi
+// CHECK: [0x6d,0x80,0x0a,0x7e]
+
+v_log_f16 v5, tma_lo
+// CHECK: [0x6e,0x80,0x0a,0x7e]
+
+v_log_f16 v5, tma_hi
+// CHECK: [0x6f,0x80,0x0a,0x7e]
+
+v_log_f16 v5, ttmp11
+// CHECK: [0x7b,0x80,0x0a,0x7e]
+
+v_log_f16 v5, m0
+// CHECK: [0x7c,0x80,0x0a,0x7e]
+
+v_log_f16 v5, exec_lo
+// CHECK: [0x7e,0x80,0x0a,0x7e]
+
+v_log_f16 v5, exec_hi
+// CHECK: [0x7f,0x80,0x0a,0x7e]
+
+v_log_f16 v5, 0
+// CHECK: [0x80,0x80,0x0a,0x7e]
+
+v_log_f16 v5, -1
+// CHECK: [0xc1,0x80,0x0a,0x7e]
+
+v_log_f16 v5, 0.5
+// CHECK: [0xf0,0x80,0x0a,0x7e]
+
+v_log_f16 v5, -4.0
+// CHECK: [0xf7,0x80,0x0a,0x7e]
+
+v_log_f16 v5, src_vccz
+// CHECK: [0xfb,0x80,0x0a,0x7e]
+
+v_log_f16 v5, src_execz
+// CHECK: [0xfc,0x80,0x0a,0x7e]
+
+v_log_f16 v5, src_scc
+// CHECK: [0xfd,0x80,0x0a,0x7e]
+
+v_log_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x80,0x0a,0x7e]
+
+v_log_f16 v5, 0xfe0b
+// CHECK: [0xff,0x80,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_log_f16 v5, 0x3456
+// CHECK: [0xff,0x80,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_exp_f16 v5, v1
+// CHECK: [0x01,0x83,0x0a,0x7e]
+
+v_exp_f16 v255, v1
+// CHECK: [0x01,0x83,0xfe,0x7f]
+
+v_exp_f16 v5, v255
+// CHECK: [0xff,0x83,0x0a,0x7e]
+
+v_exp_f16 v5, s1
+// CHECK: [0x01,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, s101
+// CHECK: [0x65,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, vcc_lo
+// CHECK: [0x6a,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, vcc_hi
+// CHECK: [0x6b,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, tba_lo
+// CHECK: [0x6c,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, tba_hi
+// CHECK: [0x6d,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, tma_lo
+// CHECK: [0x6e,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, tma_hi
+// CHECK: [0x6f,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, ttmp11
+// CHECK: [0x7b,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, m0
+// CHECK: [0x7c,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, exec_lo
+// CHECK: [0x7e,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, exec_hi
+// CHECK: [0x7f,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, 0
+// CHECK: [0x80,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, -1
+// CHECK: [0xc1,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, 0.5
+// CHECK: [0xf0,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, -4.0
+// CHECK: [0xf7,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, src_vccz
+// CHECK: [0xfb,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, src_execz
+// CHECK: [0xfc,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, src_scc
+// CHECK: [0xfd,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, 0xfe0b
+// CHECK: [0xff,0x82,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_exp_f16 v5, 0x3456
+// CHECK: [0xff,0x82,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_frexp_mant_f16 v5, v1
+// CHECK: [0x01,0x85,0x0a,0x7e]
+
+v_frexp_mant_f16 v255, v1
+// CHECK: [0x01,0x85,0xfe,0x7f]
+
+v_frexp_mant_f16 v5, v255
+// CHECK: [0xff,0x85,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, s1
+// CHECK: [0x01,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, s101
+// CHECK: [0x65,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, vcc_lo
+// CHECK: [0x6a,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, vcc_hi
+// CHECK: [0x6b,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, tba_lo
+// CHECK: [0x6c,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, tba_hi
+// CHECK: [0x6d,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, tma_lo
+// CHECK: [0x6e,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, tma_hi
+// CHECK: [0x6f,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, ttmp11
+// CHECK: [0x7b,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, m0
+// CHECK: [0x7c,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, exec_lo
+// CHECK: [0x7e,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, exec_hi
+// CHECK: [0x7f,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, 0
+// CHECK: [0x80,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, -1
+// CHECK: [0xc1,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, 0.5
+// CHECK: [0xf0,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, -4.0
+// CHECK: [0xf7,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, src_vccz
+// CHECK: [0xfb,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, src_execz
+// CHECK: [0xfc,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, src_scc
+// CHECK: [0xfd,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, 0xfe0b
+// CHECK: [0xff,0x84,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_frexp_mant_f16 v5, 0x3456
+// CHECK: [0xff,0x84,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_frexp_exp_i16_f16 v5, v1
+// CHECK: [0x01,0x87,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v255, v1
+// CHECK: [0x01,0x87,0xfe,0x7f]
+
+v_frexp_exp_i16_f16 v5, v255
+// CHECK: [0xff,0x87,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, s1
+// CHECK: [0x01,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, s101
+// CHECK: [0x65,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, vcc_lo
+// CHECK: [0x6a,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, vcc_hi
+// CHECK: [0x6b,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, tba_lo
+// CHECK: [0x6c,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, tba_hi
+// CHECK: [0x6d,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, tma_lo
+// CHECK: [0x6e,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, tma_hi
+// CHECK: [0x6f,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, ttmp11
+// CHECK: [0x7b,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, m0
+// CHECK: [0x7c,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, exec_lo
+// CHECK: [0x7e,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, exec_hi
+// CHECK: [0x7f,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, 0
+// CHECK: [0x80,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, -1
+// CHECK: [0xc1,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, 0.5
+// CHECK: [0xf0,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, -4.0
+// CHECK: [0xf7,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, src_vccz
+// CHECK: [0xfb,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, src_execz
+// CHECK: [0xfc,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, src_scc
+// CHECK: [0xfd,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, 0xfe0b
+// CHECK: [0xff,0x86,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_frexp_exp_i16_f16 v5, 0x3456
+// CHECK: [0xff,0x86,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_floor_f16 v5, v1
+// CHECK: [0x01,0x89,0x0a,0x7e]
+
+v_floor_f16 v255, v1
+// CHECK: [0x01,0x89,0xfe,0x7f]
+
+v_floor_f16 v5, v255
+// CHECK: [0xff,0x89,0x0a,0x7e]
+
+v_floor_f16 v5, s1
+// CHECK: [0x01,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, s101
+// CHECK: [0x65,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, vcc_lo
+// CHECK: [0x6a,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, vcc_hi
+// CHECK: [0x6b,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, tba_lo
+// CHECK: [0x6c,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, tba_hi
+// CHECK: [0x6d,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, tma_lo
+// CHECK: [0x6e,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, tma_hi
+// CHECK: [0x6f,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, ttmp11
+// CHECK: [0x7b,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, m0
+// CHECK: [0x7c,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, exec_lo
+// CHECK: [0x7e,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, exec_hi
+// CHECK: [0x7f,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, 0
+// CHECK: [0x80,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, -1
+// CHECK: [0xc1,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, 0.5
+// CHECK: [0xf0,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, -4.0
+// CHECK: [0xf7,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, src_vccz
+// CHECK: [0xfb,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, src_execz
+// CHECK: [0xfc,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, src_scc
+// CHECK: [0xfd,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, 0xfe0b
+// CHECK: [0xff,0x88,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_floor_f16 v5, 0x3456
+// CHECK: [0xff,0x88,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_ceil_f16 v5, v1
+// CHECK: [0x01,0x8b,0x0a,0x7e]
+
+v_ceil_f16 v255, v1
+// CHECK: [0x01,0x8b,0xfe,0x7f]
+
+v_ceil_f16 v5, v255
+// CHECK: [0xff,0x8b,0x0a,0x7e]
+
+v_ceil_f16 v5, s1
+// CHECK: [0x01,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, s101
+// CHECK: [0x65,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, vcc_lo
+// CHECK: [0x6a,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, vcc_hi
+// CHECK: [0x6b,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, tba_lo
+// CHECK: [0x6c,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, tba_hi
+// CHECK: [0x6d,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, tma_lo
+// CHECK: [0x6e,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, tma_hi
+// CHECK: [0x6f,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, ttmp11
+// CHECK: [0x7b,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, m0
+// CHECK: [0x7c,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, exec_lo
+// CHECK: [0x7e,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, exec_hi
+// CHECK: [0x7f,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, 0
+// CHECK: [0x80,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, -1
+// CHECK: [0xc1,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, 0.5
+// CHECK: [0xf0,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, -4.0
+// CHECK: [0xf7,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, src_vccz
+// CHECK: [0xfb,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, src_execz
+// CHECK: [0xfc,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, src_scc
+// CHECK: [0xfd,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, 0xfe0b
+// CHECK: [0xff,0x8a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_ceil_f16 v5, 0x3456
+// CHECK: [0xff,0x8a,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_trunc_f16 v5, v1
+// CHECK: [0x01,0x8d,0x0a,0x7e]
+
+v_trunc_f16 v255, v1
+// CHECK: [0x01,0x8d,0xfe,0x7f]
+
+v_trunc_f16 v5, v255
+// CHECK: [0xff,0x8d,0x0a,0x7e]
+
+v_trunc_f16 v5, s1
+// CHECK: [0x01,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, s101
+// CHECK: [0x65,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, vcc_lo
+// CHECK: [0x6a,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, vcc_hi
+// CHECK: [0x6b,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, tba_lo
+// CHECK: [0x6c,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, tba_hi
+// CHECK: [0x6d,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, tma_lo
+// CHECK: [0x6e,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, tma_hi
+// CHECK: [0x6f,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, ttmp11
+// CHECK: [0x7b,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, m0
+// CHECK: [0x7c,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, exec_lo
+// CHECK: [0x7e,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, exec_hi
+// CHECK: [0x7f,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, 0
+// CHECK: [0x80,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, -1
+// CHECK: [0xc1,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, 0.5
+// CHECK: [0xf0,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, -4.0
+// CHECK: [0xf7,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, src_vccz
+// CHECK: [0xfb,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, src_execz
+// CHECK: [0xfc,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, src_scc
+// CHECK: [0xfd,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, 0xfe0b
+// CHECK: [0xff,0x8c,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_trunc_f16 v5, 0x3456
+// CHECK: [0xff,0x8c,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_rndne_f16 v5, v1
+// CHECK: [0x01,0x8f,0x0a,0x7e]
+
+v_rndne_f16 v255, v1
+// CHECK: [0x01,0x8f,0xfe,0x7f]
+
+v_rndne_f16 v5, v255
+// CHECK: [0xff,0x8f,0x0a,0x7e]
+
+v_rndne_f16 v5, s1
+// CHECK: [0x01,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, s101
+// CHECK: [0x65,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, vcc_lo
+// CHECK: [0x6a,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, vcc_hi
+// CHECK: [0x6b,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, tba_lo
+// CHECK: [0x6c,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, tba_hi
+// CHECK: [0x6d,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, tma_lo
+// CHECK: [0x6e,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, tma_hi
+// CHECK: [0x6f,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, ttmp11
+// CHECK: [0x7b,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, m0
+// CHECK: [0x7c,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, exec_lo
+// CHECK: [0x7e,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, exec_hi
+// CHECK: [0x7f,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, 0
+// CHECK: [0x80,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, -1
+// CHECK: [0xc1,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, 0.5
+// CHECK: [0xf0,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, -4.0
+// CHECK: [0xf7,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, src_vccz
+// CHECK: [0xfb,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, src_execz
+// CHECK: [0xfc,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, src_scc
+// CHECK: [0xfd,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, 0xfe0b
+// CHECK: [0xff,0x8e,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rndne_f16 v5, 0x3456
+// CHECK: [0xff,0x8e,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_fract_f16 v5, v1
+// CHECK: [0x01,0x91,0x0a,0x7e]
+
+v_fract_f16 v255, v1
+// CHECK: [0x01,0x91,0xfe,0x7f]
+
+v_fract_f16 v5, v255
+// CHECK: [0xff,0x91,0x0a,0x7e]
+
+v_fract_f16 v5, s1
+// CHECK: [0x01,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, s101
+// CHECK: [0x65,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, vcc_lo
+// CHECK: [0x6a,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, vcc_hi
+// CHECK: [0x6b,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, tba_lo
+// CHECK: [0x6c,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, tba_hi
+// CHECK: [0x6d,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, tma_lo
+// CHECK: [0x6e,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, tma_hi
+// CHECK: [0x6f,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, ttmp11
+// CHECK: [0x7b,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, m0
+// CHECK: [0x7c,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, exec_lo
+// CHECK: [0x7e,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, exec_hi
+// CHECK: [0x7f,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, 0
+// CHECK: [0x80,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, -1
+// CHECK: [0xc1,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, 0.5
+// CHECK: [0xf0,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, -4.0
+// CHECK: [0xf7,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, src_vccz
+// CHECK: [0xfb,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, src_execz
+// CHECK: [0xfc,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, src_scc
+// CHECK: [0xfd,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, 0xfe0b
+// CHECK: [0xff,0x90,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_fract_f16 v5, 0x3456
+// CHECK: [0xff,0x90,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_sin_f16 v5, v1
+// CHECK: [0x01,0x93,0x0a,0x7e]
+
+v_sin_f16 v255, v1
+// CHECK: [0x01,0x93,0xfe,0x7f]
+
+v_sin_f16 v5, v255
+// CHECK: [0xff,0x93,0x0a,0x7e]
+
+v_sin_f16 v5, s1
+// CHECK: [0x01,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, s101
+// CHECK: [0x65,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, vcc_lo
+// CHECK: [0x6a,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, vcc_hi
+// CHECK: [0x6b,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, tba_lo
+// CHECK: [0x6c,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, tba_hi
+// CHECK: [0x6d,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, tma_lo
+// CHECK: [0x6e,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, tma_hi
+// CHECK: [0x6f,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, ttmp11
+// CHECK: [0x7b,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, m0
+// CHECK: [0x7c,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, exec_lo
+// CHECK: [0x7e,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, exec_hi
+// CHECK: [0x7f,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, 0
+// CHECK: [0x80,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, -1
+// CHECK: [0xc1,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, 0.5
+// CHECK: [0xf0,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, -4.0
+// CHECK: [0xf7,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, src_vccz
+// CHECK: [0xfb,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, src_execz
+// CHECK: [0xfc,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, src_scc
+// CHECK: [0xfd,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, 0xfe0b
+// CHECK: [0xff,0x92,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sin_f16 v5, 0x3456
+// CHECK: [0xff,0x92,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cos_f16 v5, v1
+// CHECK: [0x01,0x95,0x0a,0x7e]
+
+v_cos_f16 v255, v1
+// CHECK: [0x01,0x95,0xfe,0x7f]
+
+v_cos_f16 v5, v255
+// CHECK: [0xff,0x95,0x0a,0x7e]
+
+v_cos_f16 v5, s1
+// CHECK: [0x01,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, s101
+// CHECK: [0x65,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, vcc_lo
+// CHECK: [0x6a,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, vcc_hi
+// CHECK: [0x6b,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, tba_lo
+// CHECK: [0x6c,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, tba_hi
+// CHECK: [0x6d,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, tma_lo
+// CHECK: [0x6e,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, tma_hi
+// CHECK: [0x6f,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, ttmp11
+// CHECK: [0x7b,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, m0
+// CHECK: [0x7c,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, exec_lo
+// CHECK: [0x7e,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, exec_hi
+// CHECK: [0x7f,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, 0
+// CHECK: [0x80,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, -1
+// CHECK: [0xc1,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, 0.5
+// CHECK: [0xf0,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, -4.0
+// CHECK: [0xf7,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, src_vccz
+// CHECK: [0xfb,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, src_execz
+// CHECK: [0xfc,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, src_scc
+// CHECK: [0xfd,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, 0xfe0b
+// CHECK: [0xff,0x94,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cos_f16 v5, 0x3456
+// CHECK: [0xff,0x94,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_exp_legacy_f32 v5, v1
+// CHECK: [0x01,0x97,0x0a,0x7e]
+
+v_exp_legacy_f32 v255, v1
+// CHECK: [0x01,0x97,0xfe,0x7f]
+
+v_exp_legacy_f32 v5, v255
+// CHECK: [0xff,0x97,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, s1
+// CHECK: [0x01,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, s101
+// CHECK: [0x65,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, vcc_lo
+// CHECK: [0x6a,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, vcc_hi
+// CHECK: [0x6b,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, tba_lo
+// CHECK: [0x6c,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, tba_hi
+// CHECK: [0x6d,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, tma_lo
+// CHECK: [0x6e,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, tma_hi
+// CHECK: [0x6f,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, ttmp11
+// CHECK: [0x7b,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, m0
+// CHECK: [0x7c,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, exec_lo
+// CHECK: [0x7e,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, exec_hi
+// CHECK: [0x7f,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, 0
+// CHECK: [0x80,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, -1
+// CHECK: [0xc1,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, 0.5
+// CHECK: [0xf0,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, -4.0
+// CHECK: [0xf7,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_vccz
+// CHECK: [0xfb,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_execz
+// CHECK: [0xfc,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_scc
+// CHECK: [0xfd,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, 0xaf123456
+// CHECK: [0xff,0x96,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_exp_legacy_f32 v5, 0x3f717273
+// CHECK: [0xff,0x96,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_log_legacy_f32 v5, v1
+// CHECK: [0x01,0x99,0x0a,0x7e]
+
+v_log_legacy_f32 v255, v1
+// CHECK: [0x01,0x99,0xfe,0x7f]
+
+v_log_legacy_f32 v5, v255
+// CHECK: [0xff,0x99,0x0a,0x7e]
+
+v_log_legacy_f32 v5, s1
+// CHECK: [0x01,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, s101
+// CHECK: [0x65,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, vcc_lo
+// CHECK: [0x6a,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, vcc_hi
+// CHECK: [0x6b,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, tba_lo
+// CHECK: [0x6c,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, tba_hi
+// CHECK: [0x6d,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, tma_lo
+// CHECK: [0x6e,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, tma_hi
+// CHECK: [0x6f,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, ttmp11
+// CHECK: [0x7b,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, m0
+// CHECK: [0x7c,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, exec_lo
+// CHECK: [0x7e,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, exec_hi
+// CHECK: [0x7f,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, 0
+// CHECK: [0x80,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, -1
+// CHECK: [0xc1,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, 0.5
+// CHECK: [0xf0,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, -4.0
+// CHECK: [0xf7,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_vccz
+// CHECK: [0xfb,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_execz
+// CHECK: [0xfc,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_scc
+// CHECK: [0xfd,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, 0xaf123456
+// CHECK: [0xff,0x98,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_log_legacy_f32 v5, 0x3f717273
+// CHECK: [0xff,0x98,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_mov_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_mov_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_mov_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_mov_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_u32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_u32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_u32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_u32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_u32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f16_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_f16_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f16_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_f16_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_f32_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_f32_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_fract_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_fract_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_fract_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_fract_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_fract_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_fract_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_fract_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_trunc_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_trunc_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_trunc_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_trunc_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_trunc_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_trunc_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_trunc_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ceil_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_ceil_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ceil_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ceil_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ceil_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ceil_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_ceil_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rndne_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rndne_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rndne_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rndne_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rndne_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rndne_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rndne_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_floor_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_floor_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_floor_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_floor_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_floor_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_floor_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_floor_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_exp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_exp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_exp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_exp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_exp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_exp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_exp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_log_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_log_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_log_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_log_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_log_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_log_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_log_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_log_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_log_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_log_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_log_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rcp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rcp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rcp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rcp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rcp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rcp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rcp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rcp_iflag_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rcp_iflag_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rcp_iflag_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rcp_iflag_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rsq_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rsq_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rsq_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rsq_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rsq_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rsq_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rsq_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sqrt_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sqrt_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sqrt_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_sqrt_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sin_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sin_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sin_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sin_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sin_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sin_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_sin_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cos_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cos_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cos_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cos_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cos_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cos_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cos_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_not_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_not_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_not_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_not_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_not_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_not_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_not_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_not_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_bfrev_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_bfrev_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_bfrev_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ffbh_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ffbh_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ffbh_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ffbl_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ffbl_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ffbl_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ffbh_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ffbh_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ffbh_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_mant_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_mant_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_mant_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_frexp_mant_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f16_u16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_u16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_u16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f16_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_i16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_i16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_u16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_u16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_u16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_u16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rcp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rcp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rcp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rcp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rcp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rcp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rcp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sqrt_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sqrt_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sqrt_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_sqrt_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rsq_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rsq_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rsq_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rsq_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rsq_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rsq_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rsq_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_log_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_log_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_log_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_log_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_log_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_log_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_log_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_log_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_log_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_log_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_log_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_exp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_exp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_exp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_exp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_exp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_exp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_exp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_mant_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_mant_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_mant_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_frexp_mant_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_floor_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_floor_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_floor_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_floor_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_floor_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_floor_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_floor_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ceil_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_ceil_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ceil_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ceil_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ceil_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ceil_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_ceil_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_trunc_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_trunc_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_trunc_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_trunc_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rndne_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rndne_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rndne_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rndne_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rndne_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rndne_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rndne_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_fract_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_fract_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_fract_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_fract_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_fract_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_fract_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_fract_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sin_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sin_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sin_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sin_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sin_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sin_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_sin_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cos_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cos_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cos_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cos_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cos_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cos_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cos_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_exp_legacy_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_exp_legacy_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_exp_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_exp_legacy_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_exp_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_exp_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_log_legacy_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_log_legacy_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_log_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_log_legacy_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_log_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_log_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x20,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s
new file mode 100644
index 0000000000000..1ee562300f5d3
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop2.s
@@ -0,0 +1,12568 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+v_cndmask_b32 v5, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x00]
+
+v_cndmask_b32 v255, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x01]
+
+v_cndmask_b32 v5, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x00]
+
+v_cndmask_b32 v5, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, src_lds_direct, v2, vcc
+// CHECK: [0xfe,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x00]
+
+v_add_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x02]
+
+v_add_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x03]
+
+v_add_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x02]
+
+v_add_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x02]
+
+v_add_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x02]
+
+v_add_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x02]
+
+v_add_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x02]
+
+v_add_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x02]
+
+v_add_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x02]
+
+v_add_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x02]
+
+v_add_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x02]
+
+v_add_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x02]
+
+v_add_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x02]
+
+v_add_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x02]
+
+v_add_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x02]
+
+v_add_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x02]
+
+v_add_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x02]
+
+v_add_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x02]
+
+v_add_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x02]
+
+v_add_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x02]
+
+v_add_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x02]
+
+v_add_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x02]
+
+v_add_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x02]
+
+v_add_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x02]
+
+v_add_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x02]
+
+v_add_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x02,0x56,0x34,0x12,0xaf]
+
+v_add_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x02,0x73,0x72,0x71,0x3f]
+
+v_add_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x02]
+
+v_sub_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x04]
+
+v_sub_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x05]
+
+v_sub_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x04]
+
+v_sub_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x04]
+
+v_sub_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x04]
+
+v_sub_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x04]
+
+v_sub_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x04]
+
+v_sub_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x04]
+
+v_sub_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x04]
+
+v_sub_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x04]
+
+v_sub_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x04]
+
+v_sub_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x04]
+
+v_sub_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x04]
+
+v_sub_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x04]
+
+v_sub_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x04]
+
+v_sub_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x04]
+
+v_sub_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x04]
+
+v_sub_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x04]
+
+v_sub_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x04]
+
+v_sub_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x04]
+
+v_sub_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x04]
+
+v_sub_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x04]
+
+v_sub_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x04]
+
+v_sub_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x04]
+
+v_sub_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x04]
+
+v_sub_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x04,0x56,0x34,0x12,0xaf]
+
+v_sub_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x04,0x73,0x72,0x71,0x3f]
+
+v_sub_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x04]
+
+v_subrev_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x06]
+
+v_subrev_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x07]
+
+v_subrev_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x06]
+
+v_subrev_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x06,0x56,0x34,0x12,0xaf]
+
+v_subrev_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x06,0x73,0x72,0x71,0x3f]
+
+v_subrev_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x06]
+
+v_mul_legacy_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x08]
+
+v_mul_legacy_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x09]
+
+v_mul_legacy_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x08]
+
+v_mul_legacy_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x08,0x56,0x34,0x12,0xaf]
+
+v_mul_legacy_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x08,0x73,0x72,0x71,0x3f]
+
+v_mul_legacy_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x08]
+
+v_mul_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x0a]
+
+v_mul_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x0b]
+
+v_mul_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x0a]
+
+v_mul_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x0a,0x56,0x34,0x12,0xaf]
+
+v_mul_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x0a,0x73,0x72,0x71,0x3f]
+
+v_mul_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x0a]
+
+v_mul_i32_i24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x0c]
+
+v_mul_i32_i24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x0d]
+
+v_mul_i32_i24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x0c]
+
+v_mul_i32_i24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x0c,0x56,0x34,0x12,0xaf]
+
+v_mul_i32_i24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x0c,0x73,0x72,0x71,0x3f]
+
+v_mul_i32_i24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x0c]
+
+v_mul_hi_i32_i24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x0f]
+
+v_mul_hi_i32_i24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x0e,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_i32_i24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x0e,0x73,0x72,0x71,0x3f]
+
+v_mul_hi_i32_i24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x0e]
+
+v_mul_u32_u24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x10]
+
+v_mul_u32_u24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x11]
+
+v_mul_u32_u24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x10]
+
+v_mul_u32_u24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x10,0x56,0x34,0x12,0xaf]
+
+v_mul_u32_u24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x10,0x73,0x72,0x71,0x3f]
+
+v_mul_u32_u24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x10]
+
+v_mul_hi_u32_u24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x12]
+
+v_mul_hi_u32_u24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x13]
+
+v_mul_hi_u32_u24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_u32_u24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x3f]
+
+v_mul_hi_u32_u24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x12]
+
+v_min_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x14]
+
+v_min_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x15]
+
+v_min_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x14]
+
+v_min_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x14]
+
+v_min_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x14]
+
+v_min_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x14]
+
+v_min_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x14]
+
+v_min_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x14]
+
+v_min_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x14]
+
+v_min_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x14]
+
+v_min_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x14]
+
+v_min_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x14]
+
+v_min_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x14]
+
+v_min_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x14]
+
+v_min_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x14]
+
+v_min_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x14]
+
+v_min_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x14]
+
+v_min_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x14]
+
+v_min_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x14]
+
+v_min_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x14]
+
+v_min_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x14]
+
+v_min_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x14]
+
+v_min_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x14]
+
+v_min_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x14]
+
+v_min_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x14]
+
+v_min_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x14,0x56,0x34,0x12,0xaf]
+
+v_min_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x14,0x73,0x72,0x71,0x3f]
+
+v_min_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x14]
+
+v_max_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x16]
+
+v_max_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x17]
+
+v_max_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x16]
+
+v_max_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x16]
+
+v_max_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x16]
+
+v_max_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x16]
+
+v_max_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x16]
+
+v_max_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x16]
+
+v_max_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x16]
+
+v_max_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x16]
+
+v_max_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x16]
+
+v_max_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x16]
+
+v_max_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x16]
+
+v_max_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x16]
+
+v_max_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x16]
+
+v_max_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x16]
+
+v_max_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x16]
+
+v_max_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x16]
+
+v_max_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x16]
+
+v_max_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x16]
+
+v_max_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x16]
+
+v_max_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x16]
+
+v_max_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x16]
+
+v_max_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x16]
+
+v_max_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x16]
+
+v_max_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x16,0x56,0x34,0x12,0xaf]
+
+v_max_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x16,0x73,0x72,0x71,0x3f]
+
+v_max_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x16]
+
+v_min_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x18]
+
+v_min_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x19]
+
+v_min_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x18]
+
+v_min_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x18]
+
+v_min_i32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x18]
+
+v_min_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x18]
+
+v_min_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x18]
+
+v_min_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x18]
+
+v_min_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x18]
+
+v_min_i32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x18]
+
+v_min_i32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x18]
+
+v_min_i32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x18]
+
+v_min_i32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x18]
+
+v_min_i32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x18]
+
+v_min_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x18]
+
+v_min_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x18]
+
+v_min_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x18]
+
+v_min_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x18]
+
+v_min_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x18]
+
+v_min_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x18]
+
+v_min_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x18]
+
+v_min_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x18]
+
+v_min_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x18]
+
+v_min_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x18]
+
+v_min_i32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x18]
+
+v_min_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x18,0x56,0x34,0x12,0xaf]
+
+v_min_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x18,0x73,0x72,0x71,0x3f]
+
+v_min_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x18]
+
+v_max_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x1a]
+
+v_max_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x1b]
+
+v_max_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x1a]
+
+v_max_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x1a]
+
+v_max_i32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x1a]
+
+v_max_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x1a]
+
+v_max_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x1a]
+
+v_max_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x1a]
+
+v_max_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x1a]
+
+v_max_i32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x1a]
+
+v_max_i32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x1a]
+
+v_max_i32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x1a]
+
+v_max_i32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x1a]
+
+v_max_i32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x1a]
+
+v_max_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x1a]
+
+v_max_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x1a]
+
+v_max_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x1a]
+
+v_max_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x1a]
+
+v_max_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x1a]
+
+v_max_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x1a]
+
+v_max_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x1a]
+
+v_max_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x1a]
+
+v_max_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x1a]
+
+v_max_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x1a]
+
+v_max_i32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x1a]
+
+v_max_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x1a,0x56,0x34,0x12,0xaf]
+
+v_max_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x1a,0x73,0x72,0x71,0x3f]
+
+v_max_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x1a]
+
+v_min_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x1c]
+
+v_min_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x1d]
+
+v_min_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x1c]
+
+v_min_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x1c]
+
+v_min_u32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x1c]
+
+v_min_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x1c]
+
+v_min_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x1c]
+
+v_min_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x1c]
+
+v_min_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x1c]
+
+v_min_u32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x1c]
+
+v_min_u32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x1c]
+
+v_min_u32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x1c]
+
+v_min_u32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x1c]
+
+v_min_u32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x1c]
+
+v_min_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x1c]
+
+v_min_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x1c]
+
+v_min_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x1c]
+
+v_min_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x1c]
+
+v_min_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x1c]
+
+v_min_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x1c]
+
+v_min_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x1c]
+
+v_min_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x1c]
+
+v_min_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x1c]
+
+v_min_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x1c]
+
+v_min_u32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x1c]
+
+v_min_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x1c,0x56,0x34,0x12,0xaf]
+
+v_min_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x1c,0x73,0x72,0x71,0x3f]
+
+v_min_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x1c]
+
+v_max_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x1e]
+
+v_max_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x1f]
+
+v_max_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x1e]
+
+v_max_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x1e]
+
+v_max_u32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x1e]
+
+v_max_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x1e]
+
+v_max_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x1e]
+
+v_max_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x1e]
+
+v_max_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x1e]
+
+v_max_u32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x1e]
+
+v_max_u32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x1e]
+
+v_max_u32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x1e]
+
+v_max_u32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x1e]
+
+v_max_u32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x1e]
+
+v_max_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x1e]
+
+v_max_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x1e]
+
+v_max_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x1e]
+
+v_max_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x1e]
+
+v_max_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x1e]
+
+v_max_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x1e]
+
+v_max_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x1e]
+
+v_max_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x1e]
+
+v_max_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x1e]
+
+v_max_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x1e]
+
+v_max_u32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x1e]
+
+v_max_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x1e,0x56,0x34,0x12,0xaf]
+
+v_max_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x1e,0x73,0x72,0x71,0x3f]
+
+v_max_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x1e]
+
+v_lshrrev_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x20]
+
+v_lshrrev_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x21]
+
+v_lshrrev_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x20]
+
+v_lshrrev_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x20,0x56,0x34,0x12,0xaf]
+
+v_lshrrev_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x20,0x73,0x72,0x71,0x3f]
+
+v_lshrrev_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x20]
+
+v_ashrrev_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x22]
+
+v_ashrrev_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x23]
+
+v_ashrrev_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x22]
+
+v_ashrrev_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x22,0x56,0x34,0x12,0xaf]
+
+v_ashrrev_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x22,0x73,0x72,0x71,0x3f]
+
+v_ashrrev_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x22]
+
+v_lshlrev_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x24]
+
+v_lshlrev_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x25]
+
+v_lshlrev_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x24]
+
+v_lshlrev_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x24,0x56,0x34,0x12,0xaf]
+
+v_lshlrev_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x24,0x73,0x72,0x71,0x3f]
+
+v_lshlrev_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x24]
+
+v_and_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x26]
+
+v_and_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x27]
+
+v_and_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x26]
+
+v_and_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x26]
+
+v_and_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x26]
+
+v_and_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x26]
+
+v_and_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x26]
+
+v_and_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x26]
+
+v_and_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x26]
+
+v_and_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x26]
+
+v_and_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x26]
+
+v_and_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x26]
+
+v_and_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x26]
+
+v_and_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x26]
+
+v_and_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x26]
+
+v_and_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x26]
+
+v_and_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x26]
+
+v_and_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x26]
+
+v_and_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x26]
+
+v_and_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x26]
+
+v_and_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x26]
+
+v_and_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x26]
+
+v_and_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x26]
+
+v_and_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x26]
+
+v_and_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x26]
+
+v_and_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x26,0x56,0x34,0x12,0xaf]
+
+v_and_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x26,0x73,0x72,0x71,0x3f]
+
+v_and_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x26]
+
+v_or_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x28]
+
+v_or_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x29]
+
+v_or_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x28]
+
+v_or_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x28]
+
+v_or_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x28]
+
+v_or_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x28]
+
+v_or_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x28]
+
+v_or_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x28]
+
+v_or_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x28]
+
+v_or_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x28]
+
+v_or_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x28]
+
+v_or_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x28]
+
+v_or_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x28]
+
+v_or_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x28]
+
+v_or_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x28]
+
+v_or_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x28]
+
+v_or_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x28]
+
+v_or_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x28]
+
+v_or_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x28]
+
+v_or_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x28]
+
+v_or_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x28]
+
+v_or_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x28]
+
+v_or_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x28]
+
+v_or_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x28]
+
+v_or_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x28]
+
+v_or_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x28,0x56,0x34,0x12,0xaf]
+
+v_or_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x28,0x73,0x72,0x71,0x3f]
+
+v_or_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x28]
+
+v_xor_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x2a]
+
+v_xor_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x2b]
+
+v_xor_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x2a]
+
+v_xor_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x2a,0x56,0x34,0x12,0xaf]
+
+v_xor_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x2a,0x73,0x72,0x71,0x3f]
+
+v_xor_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x2a]
+
+v_mac_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x2c]
+
+v_mac_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x2d]
+
+v_mac_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x2c]
+
+v_mac_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x2c,0x56,0x34,0x12,0xaf]
+
+v_mac_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x2c,0x73,0x72,0x71,0x3f]
+
+v_mac_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x2c]
+
+v_madmk_f32 v5, v1, 0x11213141, v3
+// CHECK: [0x01,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v255, v1, 0x11213141, v3
+// CHECK: [0x01,0x07,0xfe,0x2f,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, v255, 0x11213141, v3
+// CHECK: [0xff,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, 0, 0x11213141, v3
+// CHECK: [0x80,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, -1, 0x11213141, v3
+// CHECK: [0xc1,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, 0.5, 0x11213141, v3
+// CHECK: [0xf0,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, -4.0, 0x11213141, v3
+// CHECK: [0xf7,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, src_lds_direct, 0x11213141, v3
+// CHECK: [0xfe,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, v1, 0xa1b1c1d1, v3
+// CHECK: [0x01,0x07,0x0a,0x2e,0xd1,0xc1,0xb1,0xa1]
+
+v_madmk_f32 v5, v1, 0x11213141, v255
+// CHECK: [0x01,0xff,0x0b,0x2e,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v2, 0x11213141
+// CHECK: [0x01,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v255, v1, v2, 0x11213141
+// CHECK: [0x01,0x05,0xfe,0x31,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v255, v2, 0x11213141
+// CHECK: [0xff,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, 0, v2, 0x11213141
+// CHECK: [0x80,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, -1, v2, 0x11213141
+// CHECK: [0xc1,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, 0.5, v2, 0x11213141
+// CHECK: [0xf0,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, -4.0, v2, 0x11213141
+// CHECK: [0xf7,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, src_lds_direct, v2, 0x11213141
+// CHECK: [0xfe,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v255, 0x11213141
+// CHECK: [0x01,0xff,0x0b,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v2, 0xa1b1c1d1
+// CHECK: [0x01,0x05,0x0a,0x30,0xd1,0xc1,0xb1,0xa1]
+
+v_add_u32 v5, vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x32]
+
+v_add_u32 v255, vcc, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x33]
+
+v_add_u32 v5, vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x32]
+
+v_add_u32 v5, vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x32]
+
+v_add_u32 v5, vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x32,0x56,0x34,0x12,0xaf]
+
+v_add_u32 v5, vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x32,0x73,0x72,0x71,0x3f]
+
+v_add_u32 v5, vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x32]
+
+v_sub_u32 v5, vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x34]
+
+v_sub_u32 v255, vcc, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x35]
+
+v_sub_u32 v5, vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x34]
+
+v_sub_u32 v5, vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x34]
+
+v_sub_u32 v5, vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x34,0x56,0x34,0x12,0xaf]
+
+v_sub_u32 v5, vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x34,0x73,0x72,0x71,0x3f]
+
+v_sub_u32 v5, vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x34]
+
+v_subrev_u32 v5, vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x36]
+
+v_subrev_u32 v255, vcc, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x37]
+
+v_subrev_u32 v5, vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x36]
+
+v_subrev_u32 v5, vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x36,0x56,0x34,0x12,0xaf]
+
+v_subrev_u32 v5, vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x36,0x73,0x72,0x71,0x3f]
+
+v_subrev_u32 v5, vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x36]
+
+v_addc_u32 v5, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x38]
+
+v_addc_u32 v255, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x39]
+
+v_addc_u32 v5, vcc, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x38]
+
+v_addc_u32 v5, vcc, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x38]
+
+v_addc_u32 v5, vcc, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x38]
+
+v_addc_u32 v5, vcc, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x38]
+
+v_addc_u32 v5, vcc, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x38]
+
+v_addc_u32 v5, vcc, src_lds_direct, v2, vcc
+// CHECK: [0xfe,0x04,0x0a,0x38]
+
+v_addc_u32 v5, vcc, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x38]
+
+v_subb_u32 v5, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x3a]
+
+v_subb_u32 v255, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x3b]
+
+v_subb_u32 v5, vcc, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x3a]
+
+v_subb_u32 v5, vcc, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x3a]
+
+v_subb_u32 v5, vcc, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x3a]
+
+v_subb_u32 v5, vcc, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x3a]
+
+v_subb_u32 v5, vcc, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x3a]
+
+v_subb_u32 v5, vcc, src_lds_direct, v2, vcc
+// CHECK: [0xfe,0x04,0x0a,0x3a]
+
+v_subb_u32 v5, vcc, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x3a]
+
+v_subbrev_u32 v5, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x3c]
+
+v_subbrev_u32 v255, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x3d]
+
+v_subbrev_u32 v5, vcc, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x3c]
+
+v_subbrev_u32 v5, vcc, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x3c]
+
+v_subbrev_u32 v5, vcc, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x3c]
+
+v_subbrev_u32 v5, vcc, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x3c]
+
+v_subbrev_u32 v5, vcc, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x3c]
+
+v_subbrev_u32 v5, vcc, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x3c]
+
+v_add_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x3e]
+
+v_add_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x3f]
+
+v_add_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x3e]
+
+v_add_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x3e]
+
+v_add_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x3e]
+
+v_add_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x3e]
+
+v_add_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x3e]
+
+v_add_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x3e]
+
+v_add_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x3e]
+
+v_add_f16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x3e]
+
+v_add_f16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x3e]
+
+v_add_f16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x3e]
+
+v_add_f16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x3e]
+
+v_add_f16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x3e]
+
+v_add_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x3e]
+
+v_add_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x3e]
+
+v_add_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x3e]
+
+v_add_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x3e]
+
+v_add_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x3e]
+
+v_add_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x3e]
+
+v_add_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x3e]
+
+v_add_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x3e]
+
+v_add_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x3e]
+
+v_add_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x3e]
+
+v_add_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x3e]
+
+v_add_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x3e,0x0b,0xfe,0x00,0x00]
+
+v_add_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x3e,0x56,0x34,0x00,0x00]
+
+v_add_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x3e]
+
+v_sub_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x40]
+
+v_sub_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x41]
+
+v_sub_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x40]
+
+v_sub_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x40]
+
+v_sub_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x40]
+
+v_sub_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x40]
+
+v_sub_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x40]
+
+v_sub_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x40]
+
+v_sub_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x40]
+
+v_sub_f16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x40]
+
+v_sub_f16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x40]
+
+v_sub_f16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x40]
+
+v_sub_f16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x40]
+
+v_sub_f16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x40]
+
+v_sub_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x40]
+
+v_sub_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x40]
+
+v_sub_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x40]
+
+v_sub_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x40]
+
+v_sub_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x40]
+
+v_sub_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x40]
+
+v_sub_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x40]
+
+v_sub_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x40]
+
+v_sub_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x40]
+
+v_sub_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x40]
+
+v_sub_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x40]
+
+v_sub_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x40,0x0b,0xfe,0x00,0x00]
+
+v_sub_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x40,0x56,0x34,0x00,0x00]
+
+v_sub_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x40]
+
+v_subrev_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x42]
+
+v_subrev_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x43]
+
+v_subrev_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x42]
+
+v_subrev_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x42,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x42,0x56,0x34,0x00,0x00]
+
+v_subrev_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x42]
+
+v_mul_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x44]
+
+v_mul_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x45]
+
+v_mul_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x44]
+
+v_mul_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x44]
+
+v_mul_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x44]
+
+v_mul_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x44]
+
+v_mul_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x44]
+
+v_mul_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x44]
+
+v_mul_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x44]
+
+v_mul_f16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x44]
+
+v_mul_f16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x44]
+
+v_mul_f16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x44]
+
+v_mul_f16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x44]
+
+v_mul_f16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x44]
+
+v_mul_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x44]
+
+v_mul_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x44]
+
+v_mul_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x44]
+
+v_mul_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x44]
+
+v_mul_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x44]
+
+v_mul_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x44]
+
+v_mul_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x44]
+
+v_mul_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x44]
+
+v_mul_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x44]
+
+v_mul_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x44]
+
+v_mul_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x44]
+
+v_mul_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x44,0x0b,0xfe,0x00,0x00]
+
+v_mul_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x44,0x56,0x34,0x00,0x00]
+
+v_mul_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x44]
+
+v_mac_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x46]
+
+v_mac_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x47]
+
+v_mac_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x46]
+
+v_mac_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x46]
+
+v_mac_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x46]
+
+v_mac_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x46]
+
+v_mac_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x46]
+
+v_mac_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x46]
+
+v_mac_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x46]
+
+v_mac_f16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x46]
+
+v_mac_f16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x46]
+
+v_mac_f16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x46]
+
+v_mac_f16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x46]
+
+v_mac_f16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x46]
+
+v_mac_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x46]
+
+v_mac_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x46]
+
+v_mac_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x46]
+
+v_mac_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x46]
+
+v_mac_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x46]
+
+v_mac_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x46]
+
+v_mac_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x46]
+
+v_mac_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x46]
+
+v_mac_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x46]
+
+v_mac_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x46]
+
+v_mac_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x46]
+
+v_mac_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x46,0x0b,0xfe,0x00,0x00]
+
+v_mac_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x46,0x56,0x34,0x00,0x00]
+
+v_mac_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x46]
+
+v_madmk_f16 v5, v1, 0x1121, v3
+// CHECK: [0x01,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v255, v1, 0x1121, v3
+// CHECK: [0x01,0x07,0xfe,0x49,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, v255, 0x1121, v3
+// CHECK: [0xff,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, 0, 0x1121, v3
+// CHECK: [0x80,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, -1, 0x1121, v3
+// CHECK: [0xc1,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, 0.5, 0x1121, v3
+// CHECK: [0xf0,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, -4.0, 0x1121, v3
+// CHECK: [0xf7,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, src_lds_direct, 0x1121, v3
+// CHECK: [0xfe,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, v1, 0xa1b1, v3
+// CHECK: [0x01,0x07,0x0a,0x48,0xb1,0xa1,0x00,0x00]
+
+v_madmk_f16 v5, v1, 0x1121, v255
+// CHECK: [0x01,0xff,0x0b,0x48,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, v1, v2, 0x1121
+// CHECK: [0x01,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v255, v1, v2, 0x1121
+// CHECK: [0x01,0x05,0xfe,0x4b,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, v255, v2, 0x1121
+// CHECK: [0xff,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, 0, v2, 0x1121
+// CHECK: [0x80,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, -1, v2, 0x1121
+// CHECK: [0xc1,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, 0.5, v2, 0x1121
+// CHECK: [0xf0,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, -4.0, v2, 0x1121
+// CHECK: [0xf7,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, src_lds_direct, v2, 0x1121
+// CHECK: [0xfe,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, v1, v255, 0x1121
+// CHECK: [0x01,0xff,0x0b,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, v1, v2, 0xa1b1
+// CHECK: [0x01,0x05,0x0a,0x4a,0xb1,0xa1,0x00,0x00]
+
+v_add_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x4c]
+
+v_add_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x4d]
+
+v_add_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x4c]
+
+v_add_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x4c]
+
+v_add_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x4c]
+
+v_add_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x4c]
+
+v_add_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x4c]
+
+v_add_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x4c]
+
+v_add_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x4c]
+
+v_add_u16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x4c]
+
+v_add_u16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x4c]
+
+v_add_u16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x4c]
+
+v_add_u16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x4c]
+
+v_add_u16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x4c]
+
+v_add_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x4c]
+
+v_add_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x4c]
+
+v_add_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x4c]
+
+v_add_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x4c]
+
+v_add_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x4c]
+
+v_add_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x00,0x38,0x00,0x00]
+
+v_add_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x00,0xc4,0x00,0x00]
+
+v_add_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x4c]
+
+v_add_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x4c]
+
+v_add_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x4c]
+
+v_add_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x4c]
+
+v_add_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x0b,0xfe,0x00,0x00]
+
+v_add_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x56,0x34,0x00,0x00]
+
+v_add_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x4c]
+
+v_sub_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x4e]
+
+v_sub_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x4f]
+
+v_sub_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x4e]
+
+v_sub_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x00,0x38,0x00,0x00]
+
+v_sub_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x00,0xc4,0x00,0x00]
+
+v_sub_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x0b,0xfe,0x00,0x00]
+
+v_sub_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x56,0x34,0x00,0x00]
+
+v_sub_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x4e]
+
+v_subrev_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x50]
+
+v_subrev_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x51]
+
+v_subrev_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x50]
+
+v_subrev_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x50,0x00,0x38,0x00,0x00]
+
+v_subrev_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x50,0x00,0xc4,0x00,0x00]
+
+v_subrev_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x50,0x0b,0xfe,0x00,0x00]
+
+v_subrev_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x50,0x56,0x34,0x00,0x00]
+
+v_subrev_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x50]
+
+v_mul_lo_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x52]
+
+v_mul_lo_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x53]
+
+v_mul_lo_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x52]
+
+v_mul_lo_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x52,0x00,0x38,0x00,0x00]
+
+v_mul_lo_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x52,0x00,0xc4,0x00,0x00]
+
+v_mul_lo_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x52,0x0b,0xfe,0x00,0x00]
+
+v_mul_lo_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x52,0x56,0x34,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x52]
+
+v_lshlrev_b16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x54]
+
+v_lshlrev_b16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x55]
+
+v_lshlrev_b16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x54]
+
+v_lshlrev_b16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x54,0x00,0x38,0x00,0x00]
+
+v_lshlrev_b16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x54,0x00,0xc4,0x00,0x00]
+
+v_lshlrev_b16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x54,0x0b,0xfe,0x00,0x00]
+
+v_lshlrev_b16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x54,0x56,0x34,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x54]
+
+v_lshrrev_b16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x56]
+
+v_lshrrev_b16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x57]
+
+v_lshrrev_b16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x56]
+
+v_lshrrev_b16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x00,0x38,0x00,0x00]
+
+v_lshrrev_b16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x00,0xc4,0x00,0x00]
+
+v_lshrrev_b16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x0b,0xfe,0x00,0x00]
+
+v_lshrrev_b16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x56,0x34,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x56]
+
+v_ashrrev_i16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x58]
+
+v_ashrrev_i16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x59]
+
+v_ashrrev_i16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x58]
+
+v_ashrrev_i16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x00,0x38,0x00,0x00]
+
+v_ashrrev_i16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x00,0xc4,0x00,0x00]
+
+v_ashrrev_i16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x0b,0xfe,0x00,0x00]
+
+v_ashrrev_i16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x56,0x34,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x58]
+
+v_max_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x5a]
+
+v_max_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x5b]
+
+v_max_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x5a]
+
+v_max_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x5a]
+
+v_max_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x5a]
+
+v_max_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x5a]
+
+v_max_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x5a]
+
+v_max_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x5a]
+
+v_max_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x5a]
+
+v_max_f16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x5a]
+
+v_max_f16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x5a]
+
+v_max_f16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x5a]
+
+v_max_f16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x5a]
+
+v_max_f16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x5a]
+
+v_max_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x5a]
+
+v_max_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x5a]
+
+v_max_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x5a]
+
+v_max_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x5a]
+
+v_max_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x5a]
+
+v_max_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x5a]
+
+v_max_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x5a]
+
+v_max_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x5a]
+
+v_max_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x5a]
+
+v_max_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x5a]
+
+v_max_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x5a]
+
+v_max_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x5a,0x0b,0xfe,0x00,0x00]
+
+v_max_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x5a,0x56,0x34,0x00,0x00]
+
+v_max_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x5a]
+
+v_min_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x5c]
+
+v_min_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x5d]
+
+v_min_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x5c]
+
+v_min_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x5c]
+
+v_min_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x5c]
+
+v_min_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x5c]
+
+v_min_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x5c]
+
+v_min_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x5c]
+
+v_min_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x5c]
+
+v_min_f16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x5c]
+
+v_min_f16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x5c]
+
+v_min_f16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x5c]
+
+v_min_f16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x5c]
+
+v_min_f16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x5c]
+
+v_min_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x5c]
+
+v_min_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x5c]
+
+v_min_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x5c]
+
+v_min_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x5c]
+
+v_min_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x5c]
+
+v_min_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x5c]
+
+v_min_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x5c]
+
+v_min_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x5c]
+
+v_min_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x5c]
+
+v_min_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x5c]
+
+v_min_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x5c]
+
+v_min_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x5c,0x0b,0xfe,0x00,0x00]
+
+v_min_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x5c,0x56,0x34,0x00,0x00]
+
+v_min_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x5c]
+
+v_max_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x5e]
+
+v_max_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x5f]
+
+v_max_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x5e]
+
+v_max_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x5e]
+
+v_max_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x5e]
+
+v_max_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x5e]
+
+v_max_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x5e]
+
+v_max_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x5e]
+
+v_max_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x5e]
+
+v_max_u16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x5e]
+
+v_max_u16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x5e]
+
+v_max_u16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x5e]
+
+v_max_u16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x5e]
+
+v_max_u16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x5e]
+
+v_max_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x5e]
+
+v_max_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x5e]
+
+v_max_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x5e]
+
+v_max_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x5e]
+
+v_max_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x5e]
+
+v_max_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x00,0x38,0x00,0x00]
+
+v_max_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x00,0xc4,0x00,0x00]
+
+v_max_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x5e]
+
+v_max_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x5e]
+
+v_max_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x5e]
+
+v_max_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x5e]
+
+v_max_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x0b,0xfe,0x00,0x00]
+
+v_max_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x56,0x34,0x00,0x00]
+
+v_max_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x5e]
+
+v_max_i16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x60]
+
+v_max_i16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x61]
+
+v_max_i16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x60]
+
+v_max_i16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x60]
+
+v_max_i16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x60]
+
+v_max_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x60]
+
+v_max_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x60]
+
+v_max_i16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x60]
+
+v_max_i16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x60]
+
+v_max_i16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x60]
+
+v_max_i16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x60]
+
+v_max_i16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x60]
+
+v_max_i16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x60]
+
+v_max_i16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x60]
+
+v_max_i16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x60]
+
+v_max_i16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x60]
+
+v_max_i16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x60]
+
+v_max_i16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x60]
+
+v_max_i16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x60]
+
+v_max_i16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x00,0x38,0x00,0x00]
+
+v_max_i16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x00,0xc4,0x00,0x00]
+
+v_max_i16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x60]
+
+v_max_i16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x60]
+
+v_max_i16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x60]
+
+v_max_i16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x60]
+
+v_max_i16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x0b,0xfe,0x00,0x00]
+
+v_max_i16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x56,0x34,0x00,0x00]
+
+v_max_i16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x60]
+
+v_min_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x62]
+
+v_min_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x63]
+
+v_min_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x62]
+
+v_min_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x62]
+
+v_min_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x62]
+
+v_min_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x62]
+
+v_min_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x62]
+
+v_min_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x62]
+
+v_min_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x62]
+
+v_min_u16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x62]
+
+v_min_u16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x62]
+
+v_min_u16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x62]
+
+v_min_u16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x62]
+
+v_min_u16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x62]
+
+v_min_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x62]
+
+v_min_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x62]
+
+v_min_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x62]
+
+v_min_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x62]
+
+v_min_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x62]
+
+v_min_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x00,0x38,0x00,0x00]
+
+v_min_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x00,0xc4,0x00,0x00]
+
+v_min_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x62]
+
+v_min_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x62]
+
+v_min_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x62]
+
+v_min_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x62]
+
+v_min_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x0b,0xfe,0x00,0x00]
+
+v_min_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x56,0x34,0x00,0x00]
+
+v_min_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x62]
+
+v_min_i16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x64]
+
+v_min_i16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x65]
+
+v_min_i16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x64]
+
+v_min_i16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x64]
+
+v_min_i16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x64]
+
+v_min_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x64]
+
+v_min_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x64]
+
+v_min_i16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x64]
+
+v_min_i16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x64]
+
+v_min_i16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x64]
+
+v_min_i16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x64]
+
+v_min_i16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x64]
+
+v_min_i16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x64]
+
+v_min_i16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x64]
+
+v_min_i16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x64]
+
+v_min_i16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x64]
+
+v_min_i16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x64]
+
+v_min_i16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x64]
+
+v_min_i16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x64]
+
+v_min_i16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x64,0x00,0x38,0x00,0x00]
+
+v_min_i16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x64,0x00,0xc4,0x00,0x00]
+
+v_min_i16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x64]
+
+v_min_i16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x64]
+
+v_min_i16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x64]
+
+v_min_i16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x64]
+
+v_min_i16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x64,0x0b,0xfe,0x00,0x00]
+
+v_min_i16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x64,0x56,0x34,0x00,0x00]
+
+v_min_i16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x64]
+
+v_ldexp_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x66]
+
+v_ldexp_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x67]
+
+v_ldexp_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x66]
+
+v_ldexp_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, tba_lo, v2
+// CHECK: [0x6c,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, tba_hi, v2
+// CHECK: [0x6d,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, tma_lo, v2
+// CHECK: [0x6e,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, tma_hi, v2
+// CHECK: [0x6f,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, ttmp11, v2
+// CHECK: [0x7b,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x66,0x0b,0xfe,0x00,0x00]
+
+v_ldexp_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x66,0x56,0x34,0x00,0x00]
+
+v_ldexp_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x66]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v255, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x01,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0xff,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x01,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x02,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x03,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x04,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x05,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x0e,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x16,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x16,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x00,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x01,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x02,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x03,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x04,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x05,0x06]
+
+v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x0e,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x00]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x01]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x02]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x03]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x04]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x05]
+
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
+
+v_cndmask_b32_dpp v255, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x01,0x01,0xe4,0x00,0x00]
+
+v_cndmask_b32_dpp v5, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0xff,0xe4,0x00,0x00]
+
+v_cndmask_b32_dpp v5, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x00,0x01,0xe4,0x00,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x1b,0x00,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x40,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x41,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x42,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x43,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x30,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x34,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x38,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x3c,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x01,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x0f,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x11,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x1f,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x21,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x2f,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x10]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x30]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0xf0]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0xf0]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x01]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x03]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x08,0x00]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x03,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0xff,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x26,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x00,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x01,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x02,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x03,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x04,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x05,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x0e,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x00,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x01,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x02,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x03,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x04,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x05,0x06]
+
+v_add_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x16,0x06]
+
+v_add_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x00]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x01]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x02]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x03]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x04]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x05]
+
+v_add_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x16]
+
+v_add_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x26]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
+
+v_add_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x03,0x01,0xe4,0x00,0x00]
+
+v_add_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0xff,0xe4,0x00,0x00]
+
+v_add_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x02,0x01,0xe4,0x00,0x00]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x42,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x43,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x30,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x34,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x38,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x3c,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x10]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x30]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x01]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x03]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00]
+
+v_add_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x10,0x00]
+
+v_add_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x20,0x00]
+
+v_add_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x40,0x00]
+
+v_add_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x80,0x00]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x05,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0xff,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x26,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x00,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x01,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x02,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x03,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x04,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x05,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x0e,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x00,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x01,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x02,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x03,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x04,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x05,0x06]
+
+v_sub_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x16,0x06]
+
+v_sub_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x26,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x00]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x01]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x02]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x03]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x04]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x05]
+
+v_sub_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x16]
+
+v_sub_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x26]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x05,0x01,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0xff,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x04,0x01,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x42,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x43,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x30,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x34,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x38,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x3c,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x10]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x30]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
+
+v_sub_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
+
+v_sub_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
+
+v_sub_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x40,0x00]
+
+v_sub_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x80,0x00]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x07,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0xff,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x26,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x00,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x01,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x02,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x03,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x04,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x05,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x0e,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x00,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x01,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x02,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x03,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x04,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x05,0x06]
+
+v_subrev_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x16,0x06]
+
+v_subrev_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x26,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x00]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x01]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x02]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x03]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x04]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x05]
+
+v_subrev_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x16]
+
+v_subrev_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x26]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0xff,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x06,0x01,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x42,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x43,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x30,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x34,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x38,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x3c,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x10]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x30]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
+
+v_subrev_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00]
+
+v_subrev_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00]
+
+v_subrev_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x40,0x00]
+
+v_subrev_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x80,0x00]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x09,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0xff,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x26,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x00,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x01,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x02,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x03,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x04,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x05,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x0e,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x00,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x01,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x02,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x03,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x04,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x05,0x06]
+
+v_mul_legacy_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x16,0x06]
+
+v_mul_legacy_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x26,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x00]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x01]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x02]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x03]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x04]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x05]
+
+v_mul_legacy_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x16]
+
+v_mul_legacy_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x26]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x09,0x01,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0xff,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x08,0x01,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x42,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x43,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x30,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x34,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x38,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x3c,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x10]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x30]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
+
+v_mul_legacy_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00]
+
+v_mul_legacy_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x40,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x80,0x00]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x0b,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0xff,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x26,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x00,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x01,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x02,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x03,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x04,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x05,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x0e,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x00,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x01,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x02,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x03,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x04,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x05,0x06]
+
+v_mul_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x16,0x06]
+
+v_mul_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x26,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x00]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x01]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x02]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x03]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x04]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x05]
+
+v_mul_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x16]
+
+v_mul_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x26]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x0b,0x01,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0xff,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x0a,0x01,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x42,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x43,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x30,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x34,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x38,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x3c,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x10]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x30]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
+
+v_mul_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00]
+
+v_mul_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00]
+
+v_mul_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x40,0x00]
+
+v_mul_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x80,0x00]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x0d,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0xff,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x26,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x00,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x01,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x02,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x03,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x04,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x05,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x0e,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x00,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x01,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x02,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x03,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x04,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x05,0x06]
+
+v_mul_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x0e,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x00]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x01]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x02]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x03]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x04]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x05]
+
+v_mul_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x0e]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x0d,0x01,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0xff,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x0c,0x01,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1b,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x40,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x41,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x42,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x43,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x30,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x34,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x38,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x3c,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x01,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x0f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x11,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x21,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x2f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x10]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x30]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x01]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x03]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0xff,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x00,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x01,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x02,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x03,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x04,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x05,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x0e,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x00,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x01,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x02,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x03,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x04,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x05,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x0e,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x00]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x01]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x02]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x03]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x04]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x05]
+
+v_mul_hi_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x0e]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x0f,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0xff,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x0e,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x42,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x43,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x30,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x34,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x38,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x3c,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x10]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x30]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0xff,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x26,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x00,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x01,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x02,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x03,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x04,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x05,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x0e,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x00,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x01,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x02,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x03,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x04,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x05,0x06]
+
+v_mul_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x0e,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x00]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x01]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x02]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x03]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x04]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x05]
+
+v_mul_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x0e]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x11,0x01,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0xff,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x10,0x01,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x42,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x43,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x30,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x34,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x38,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x3c,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x10]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x30]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0xff,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x00,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x01,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x02,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x03,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x04,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x05,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x0e,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x00,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x01,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x02,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x03,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x04,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x05,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x0e,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x00]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x01]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x02]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x03]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x04]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x05]
+
+v_mul_hi_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x0e]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x13,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0xff,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x12,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x42,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x43,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x30,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x34,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x38,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x3c,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x10]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x30]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0xff,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x26,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x00,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x01,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x02,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x03,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x04,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x05,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x0e,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x00,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x01,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x02,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x03,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x04,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x05,0x06]
+
+v_min_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x16,0x06]
+
+v_min_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x26,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x00]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x01]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x02]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x03]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x04]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x05]
+
+v_min_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x16]
+
+v_min_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x26]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x00]
+
+v_min_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x15,0x01,0xe4,0x00,0x00]
+
+v_min_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0xff,0xe4,0x00,0x00]
+
+v_min_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x14,0x01,0xe4,0x00,0x00]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x42,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x43,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x30,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x34,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x38,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x3c,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x10]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x30]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
+
+v_min_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x10,0x00]
+
+v_min_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x20,0x00]
+
+v_min_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x40,0x00]
+
+v_min_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x80,0x00]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0xff,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x26,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x00,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x01,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x02,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x03,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x04,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x05,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x0e,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x00,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x01,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x02,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x03,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x04,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x05,0x06]
+
+v_max_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x16,0x06]
+
+v_max_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x26,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x00]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x01]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x02]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x03]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x04]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x05]
+
+v_max_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x16]
+
+v_max_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x26]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x00]
+
+v_max_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x17,0x01,0xe4,0x00,0x00]
+
+v_max_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0xff,0xe4,0x00,0x00]
+
+v_max_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x16,0x01,0xe4,0x00,0x00]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x42,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x43,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x30,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x34,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x38,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x3c,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x10]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x30]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
+
+v_max_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x10,0x00]
+
+v_max_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x20,0x00]
+
+v_max_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x40,0x00]
+
+v_max_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x80,0x00]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x19,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0xff,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x00,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x01,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x02,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x03,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x04,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x05,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x0e,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x00,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x01,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x02,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x03,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x04,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x05,0x06]
+
+v_min_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x0e,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x00]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x01]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x02]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x03]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x04]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x05]
+
+v_min_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x0e]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x00]
+
+v_min_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x19,0x01,0xe4,0x00,0x00]
+
+v_min_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0xff,0xe4,0x00,0x00]
+
+v_min_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x18,0x01,0xe4,0x00,0x00]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x42,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x43,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x30,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x34,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x38,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x3c,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x10]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x30]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x1b,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0xff,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x00,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x01,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x02,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x03,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x04,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x05,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x0e,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x00,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x01,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x02,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x03,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x04,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x05,0x06]
+
+v_max_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x0e,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x00]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x01]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x02]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x03]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x04]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x05]
+
+v_max_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x0e]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x00]
+
+v_max_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x1b,0x01,0xe4,0x00,0x00]
+
+v_max_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0xff,0xe4,0x00,0x00]
+
+v_max_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x1a,0x01,0xe4,0x00,0x00]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1b,0x00,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x40,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x41,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x42,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x43,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x30,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x34,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x38,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x3c,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x01,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x0f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x11,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x21,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x2f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x10]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x30]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x1d,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0xff,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x00,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x01,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x02,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x03,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x04,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x05,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x0e,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x00,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x01,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x02,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x03,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x04,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x05,0x06]
+
+v_min_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x0e,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x00]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x01]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x02]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x03]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x04]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x05]
+
+v_min_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x0e]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x00]
+
+v_min_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x1d,0x01,0xe4,0x00,0x00]
+
+v_min_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0xff,0xe4,0x00,0x00]
+
+v_min_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x1c,0x01,0xe4,0x00,0x00]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1b,0x00,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x40,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x41,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x42,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x43,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x30,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x34,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x38,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x3c,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x01,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x0f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x11,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x21,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x2f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x10]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x30]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x01]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x03]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0xff,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x00,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x01,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x02,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x03,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x04,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x05,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x0e,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x00,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x01,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x02,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x03,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x04,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x05,0x06]
+
+v_max_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x0e,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x00]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x01]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x02]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x03]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x04]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x05]
+
+v_max_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x0e]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x00]
+
+v_max_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x1f,0x01,0xe4,0x00,0x00]
+
+v_max_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0xff,0xe4,0x00,0x00]
+
+v_max_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x1e,0x01,0xe4,0x00,0x00]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x42,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x43,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x30,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x34,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x38,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x3c,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x10]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x30]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0xff,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x00,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x01,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x02,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x03,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x04,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x05,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x0e,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x00,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x01,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x02,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x03,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x04,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x05,0x06]
+
+v_lshrrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x0e,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x00]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x01]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x02]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x03]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x04]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x05]
+
+v_lshrrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x0e]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x21,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0xff,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x20,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x42,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x43,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x30,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x34,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x38,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x3c,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x10]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x30]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0xff,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x00,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x01,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x02,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x03,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x04,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x05,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x0e,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x00,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x01,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x02,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x03,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x04,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x05,0x06]
+
+v_ashrrev_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x0e,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x00]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x01]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x02]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x03]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x04]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x05]
+
+v_ashrrev_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x0e]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0xff,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x22,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x42,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x43,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x30,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x34,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x38,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x3c,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x10]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x30]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0xff,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x00,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x01,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x02,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x03,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x04,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x05,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x0e,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x00,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x01,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x02,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x03,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x04,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x05,0x06]
+
+v_lshlrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x0e,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x00]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x01]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x02]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x03]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x04]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x05]
+
+v_lshlrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x0e]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0xff,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x24,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x42,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x43,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x30,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x34,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x38,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x3c,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x10]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x30]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0xff,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x00,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x01,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x02,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x03,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x04,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x05,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x0e,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x00,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x01,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x02,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x03,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x04,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x05,0x06]
+
+v_and_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x0e,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x00]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x01]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x02]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x03]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x04]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x05]
+
+v_and_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x0e]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00]
+
+v_and_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00]
+
+v_and_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0xff,0xe4,0x00,0x00]
+
+v_and_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x26,0x01,0xe4,0x00,0x00]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x42,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x43,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x30,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x34,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x38,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x3c,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x10]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x30]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0xff,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x00,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x01,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x02,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x03,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x04,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x05,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x0e,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x00,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x01,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x02,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x03,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x04,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x05,0x06]
+
+v_or_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x0e,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x00]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x01]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x02]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x03]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x04]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x05]
+
+v_or_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x0e]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00]
+
+v_or_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00]
+
+v_or_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0xff,0xe4,0x00,0x00]
+
+v_or_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x28,0x01,0xe4,0x00,0x00]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x42,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x43,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x30,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x34,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x38,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x3c,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x10]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x30]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x2b,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0xff,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x00,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x01,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x02,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x03,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x04,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x05,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x0e,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x00,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x01,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x02,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x03,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x04,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x05,0x06]
+
+v_xor_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x0e,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x00]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x01]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x02]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x03]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x04]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x05]
+
+v_xor_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x0e]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x2b,0x01,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0xff,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x2a,0x01,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x42,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x43,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x30,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x34,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x38,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x3c,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x10]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x30]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x01]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x03]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
+
+v_mac_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x2d,0x01,0x06,0x06,0x06]
+
+v_mac_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0xff,0x06,0x06,0x06]
+
+v_mac_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x2c,0x01,0x06,0x06,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x26,0x06,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x0e,0x06,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x16,0x06,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x00,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x01,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x02,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x03,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x04,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x05,0x06]
+
+v_mac_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x16,0x06]
+
+v_mac_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x26,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x06]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x00]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x01]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x02]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x03]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x04]
+
+v_mac_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x05]
+
+v_mac_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x16]
+
+v_mac_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2c,0x01,0x06,0x06,0x26]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
+
+v_mac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
+
+v_mac_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0xff,0xe4,0x00,0x00]
+
+v_mac_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x2c,0x01,0xe4,0x00,0x00]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x42,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x43,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x30,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x34,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x38,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x3c,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x10]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x30]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
+
+v_mac_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x10,0x00]
+
+v_mac_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x20,0x00]
+
+v_mac_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x40,0x00]
+
+v_mac_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x80,0x00]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x33,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0xff,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x32,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x26,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x00,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x01,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x02,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x03,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x04,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x05,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x0e,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x00,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x01,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x02,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x03,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x04,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x05,0x06]
+
+v_add_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x0e,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x00]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x01]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x02]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x03]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x04]
+
+v_add_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x05]
+
+v_add_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x0e]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x00]
+
+v_add_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x33,0x01,0xe4,0x00,0x00]
+
+v_add_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0xff,0xe4,0x00,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x32,0x01,0xe4,0x00,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x42,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x43,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x30,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x34,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x38,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x3c,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0x00]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x10]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x30]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x01]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x03]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
+
+v_add_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0xff,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x26,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x00,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x01,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x02,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x03,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x04,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x05,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x0e,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x00,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x01,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x02,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x03,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x04,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x05,0x06]
+
+v_sub_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x0e,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x00]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x01]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x02]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x03]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x04]
+
+v_sub_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x05]
+
+v_sub_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x0e]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00]
+
+v_sub_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00]
+
+v_sub_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0xff,0xe4,0x00,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x34,0x01,0xe4,0x00,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x42,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x43,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x30,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x34,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x38,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x3c,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0x00]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x10]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x30]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
+
+v_sub_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0xff,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x26,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x00,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x01,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x02,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x03,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x04,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x05,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x0e,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x00,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x01,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x02,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x03,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x04,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x05,0x06]
+
+v_subrev_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x0e,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x00]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x01]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x02]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x03]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x04]
+
+v_subrev_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x05]
+
+v_subrev_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x0e]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x00]
+
+v_subrev_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x37,0x01,0xe4,0x00,0x00]
+
+v_subrev_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0xff,0xe4,0x00,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x36,0x01,0xe4,0x00,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x42,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x43,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x30,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x34,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x38,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x3c,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0x00]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x10]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x30]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
+
+v_subrev_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0xff,0x06,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x26,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x00,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x01,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x02,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x03,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x04,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x05,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x0e,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x00,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x01,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x02,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x03,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x04,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x05,0x06]
+
+v_addc_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x0e,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x00]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x01]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x02]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x03]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x04]
+
+v_addc_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x05]
+
+v_addc_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x0e]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x00]
+
+v_addc_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x39,0x01,0xe4,0x00,0x00]
+
+v_addc_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0xff,0xe4,0x00,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x38,0x01,0xe4,0x00,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x42,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x43,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x30,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x34,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x38,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x3c,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0x00]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x10]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x30]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
+
+v_addc_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0xff,0x06,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x26,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x00,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x01,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x02,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x03,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x04,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x05,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x0e,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x00,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x01,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x02,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x03,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x04,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x05,0x06]
+
+v_subb_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x0e,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x00]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x01]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x02]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x03]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x04]
+
+v_subb_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x05]
+
+v_subb_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x0e]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x00]
+
+v_subb_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x3b,0x01,0xe4,0x00,0x00]
+
+v_subb_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0xff,0xe4,0x00,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x3a,0x01,0xe4,0x00,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x42,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x43,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x30,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x34,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x38,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x3c,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0x00]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x10]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x30]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
+
+v_subb_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0xff,0x06,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x26,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x00,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x01,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x02,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x03,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x04,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x05,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x0e,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x00,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x01,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x02,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x03,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x04,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x05,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x0e,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x00]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x01]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x02]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x03]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x04]
+
+v_subbrev_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x05]
+
+v_subbrev_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x0e]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x00]
+
+v_subbrev_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x3d,0x01,0xe4,0x00,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0xff,0xe4,0x00,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x3c,0x01,0xe4,0x00,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x42,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x43,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x30,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x34,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x38,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x3c,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0x00]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x10]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x30]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
+
+v_subbrev_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x3f,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0xff,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x26,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x00,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x01,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x02,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x03,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x04,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x05,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x0e,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x00,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x01,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x02,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x03,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x04,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x05,0x06]
+
+v_add_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x16,0x06]
+
+v_add_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x26,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x00]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x01]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x02]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x03]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x04]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x05]
+
+v_add_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x16]
+
+v_add_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x26]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x00]
+
+v_add_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x3f,0x01,0xe4,0x00,0x00]
+
+v_add_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0xff,0xe4,0x00,0x00]
+
+v_add_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x3e,0x01,0xe4,0x00,0x00]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x00,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x40,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x41,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x42,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x43,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x30,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x34,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x38,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x3c,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x01,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x0f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x11,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x21,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x2f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x10]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x30]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x01]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x03]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00]
+
+v_add_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x10,0x00]
+
+v_add_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x20,0x00]
+
+v_add_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x40,0x00]
+
+v_add_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x80,0x00]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x41,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0xff,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x26,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x00,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x01,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x02,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x03,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x04,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x05,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x0e,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x00,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x01,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x02,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x03,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x04,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x05,0x06]
+
+v_sub_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x16,0x06]
+
+v_sub_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x26,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x00]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x01]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x02]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x03]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x04]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x05]
+
+v_sub_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x16]
+
+v_sub_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x26]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x41,0x01,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0xff,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x40,0x01,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x42,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x43,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x30,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x34,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x38,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x3c,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x10]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x30]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x01]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x03]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00]
+
+v_sub_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x10,0x00]
+
+v_sub_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x20,0x00]
+
+v_sub_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x40,0x00]
+
+v_sub_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x80,0x00]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x43,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0xff,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x26,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x00,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x01,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x02,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x03,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x04,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x05,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x0e,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x00,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x01,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x02,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x03,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x04,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x05,0x06]
+
+v_subrev_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x16,0x06]
+
+v_subrev_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x26,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x00]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x01]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x02]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x03]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x04]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x05]
+
+v_subrev_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x16]
+
+v_subrev_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x26]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x43,0x01,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0xff,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x42,0x01,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x42,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x43,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x30,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x34,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x38,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x3c,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x10]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x30]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x01]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x03]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00]
+
+v_subrev_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x10,0x00]
+
+v_subrev_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x20,0x00]
+
+v_subrev_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x40,0x00]
+
+v_subrev_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x80,0x00]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x45,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0xff,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x26,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x00,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x01,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x02,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x03,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x04,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x05,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x0e,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x00,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x01,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x02,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x03,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x04,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x05,0x06]
+
+v_mul_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x16,0x06]
+
+v_mul_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x26,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x00]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x01]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x02]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x03]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x04]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x05]
+
+v_mul_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x16]
+
+v_mul_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x26]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x45,0x01,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0xff,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x44,0x01,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x42,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x43,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x30,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x34,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x38,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x3c,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x10]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x30]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x01]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x03]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00]
+
+v_mul_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x10,0x00]
+
+v_mul_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x20,0x00]
+
+v_mul_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x40,0x00]
+
+v_mul_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x80,0x00]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
+
+v_mac_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x47,0x01,0x06,0x06,0x06]
+
+v_mac_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0xff,0x06,0x06,0x06]
+
+v_mac_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x46,0x01,0x06,0x06,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x26,0x06,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x0e,0x06,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x16,0x06,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x16,0x06,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x00,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x01,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x02,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x03,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x04,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x05,0x06]
+
+v_mac_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x16,0x06]
+
+v_mac_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x26,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x06]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x00]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x01]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x02]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x03]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x04]
+
+v_mac_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x05]
+
+v_mac_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x16]
+
+v_mac_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x46,0x01,0x06,0x06,0x26]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x00]
+
+v_mac_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x47,0x01,0xe4,0x00,0x00]
+
+v_mac_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0xff,0xe4,0x00,0x00]
+
+v_mac_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x46,0x01,0xe4,0x00,0x00]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1b,0x00,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x40,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x41,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x42,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x43,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x30,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x34,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x38,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x3c,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x01,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x0f,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x11,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1f,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x21,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x2f,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x10]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x30]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x01]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x03]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00]
+
+v_mac_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x10,0x00]
+
+v_mac_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x20,0x00]
+
+v_mac_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x40,0x00]
+
+v_mac_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x80,0x00]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x4d,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0xff,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x26,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x00,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x01,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x02,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x03,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x04,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x05,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x0e,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x00,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x01,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x02,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x03,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x04,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x05,0x06]
+
+v_add_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x0e,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x00]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x01]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x02]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x03]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x04]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x05]
+
+v_add_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x0e]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x00]
+
+v_add_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x4d,0x01,0xe4,0x00,0x00]
+
+v_add_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0xff,0xe4,0x00,0x00]
+
+v_add_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x4c,0x01,0xe4,0x00,0x00]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x42,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x43,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x30,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x34,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x38,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x3c,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x10]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x30]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x01]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x03]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0xff,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x26,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x00,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x01,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x02,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x03,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x04,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x05,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x0e,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x00,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x01,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x02,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x03,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x04,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x05,0x06]
+
+v_sub_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x0e,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x00]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x01]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x02]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x03]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x04]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x05]
+
+v_sub_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x0e]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x00]
+
+v_sub_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x4f,0x01,0xe4,0x00,0x00]
+
+v_sub_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0xff,0xe4,0x00,0x00]
+
+v_sub_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x4e,0x01,0xe4,0x00,0x00]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x42,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x43,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x30,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x34,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x38,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x3c,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x10]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x30]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x01]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x03]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x26,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x00,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x01,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x02,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x03,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x04,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x05,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x0e,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x00,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x01,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x02,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x03,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x04,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x05,0x06]
+
+v_subrev_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x0e,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x00]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x01]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x02]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x03]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x04]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x05]
+
+v_subrev_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x0e]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00]
+
+v_subrev_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x51,0x01,0xe4,0x00,0x00]
+
+v_subrev_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0xff,0xe4,0x00,0x00]
+
+v_subrev_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x50,0x01,0xe4,0x00,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x40,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x41,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x42,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x43,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x30,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x34,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x38,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x3c,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x01,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x0f,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x11,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1f,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x21,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x2f,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x10]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x30]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x01]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x03]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x00,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x01,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x02,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x03,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x04,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x05,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x0e,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x00,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x01,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x02,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x03,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x04,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x05,0x06]
+
+v_mul_lo_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x0e,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x00]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x01]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x02]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x03]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x04]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x05]
+
+v_mul_lo_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x0e]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x00]
+
+v_mul_lo_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x53,0x01,0xe4,0x00,0x00]
+
+v_mul_lo_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0xff,0xe4,0x00,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x52,0x01,0xe4,0x00,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x00,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x40,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x41,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x42,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x43,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x30,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x34,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x38,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x3c,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x01,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x0f,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x11,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1f,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x21,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x2f,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x10]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x30]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x01]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x03]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x00,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x01,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x02,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x03,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x04,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x05,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x0e,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x00,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x01,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x02,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x03,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x04,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x05,0x06]
+
+v_lshlrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x0e,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x00]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x01]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x02]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x03]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x04]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x05]
+
+v_lshlrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x0e]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x55,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0xff,0xe4,0x00,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x54,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x00,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x40,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x41,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x42,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x43,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x30,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x34,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x38,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x3c,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x0f,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x11,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1f,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x21,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x2f,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x10]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x30]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x01]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x03]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x57,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0xff,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x00,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x01,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x02,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x03,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x04,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x05,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x0e,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x00,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x01,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x02,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x03,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x04,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x05,0x06]
+
+v_lshrrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x0e,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x00]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x01]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x02]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x03]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x04]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x05]
+
+v_lshrrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x0e]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x57,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0xff,0xe4,0x00,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x56,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x42,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x43,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x30,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x34,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x38,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x3c,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x10]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x30]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x01]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x03]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x59,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0xff,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x00,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x01,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x02,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x03,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x04,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x05,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x0e,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x00,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x01,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x02,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x03,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x04,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x05,0x06]
+
+v_ashrrev_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x0e,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x00]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x01]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x02]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x03]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x04]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x05]
+
+v_ashrrev_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x0e]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x59,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0xff,0xe4,0x00,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x58,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1b,0x00,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x40,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x41,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x42,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x43,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x30,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x34,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x38,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x3c,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x0f,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x11,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1f,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x21,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x2f,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x10]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x30]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x01]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x03]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x5b,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0xff,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x26,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x00,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x01,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x02,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x03,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x04,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x05,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x0e,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x00,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x01,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x02,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x03,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x04,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x05,0x06]
+
+v_max_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x16,0x06]
+
+v_max_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x26,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x00]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x01]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x02]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x03]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x04]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x05]
+
+v_max_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x16]
+
+v_max_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x26]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x00]
+
+v_max_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x5b,0x01,0xe4,0x00,0x00]
+
+v_max_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0xff,0xe4,0x00,0x00]
+
+v_max_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x5a,0x01,0xe4,0x00,0x00]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1b,0x00,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x40,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x41,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x42,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x43,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x30,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x34,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x38,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x3c,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x01,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x0f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x11,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x21,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x2f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x10]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x30]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x01]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x03]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00]
+
+v_max_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x10,0x00]
+
+v_max_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x20,0x00]
+
+v_max_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x40,0x00]
+
+v_max_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x80,0x00]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x5d,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0xff,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x26,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x00,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x01,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x02,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x03,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x04,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x05,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x0e,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x00,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x01,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x02,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x03,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x04,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x05,0x06]
+
+v_min_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x16,0x06]
+
+v_min_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x26,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x00]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x01]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x02]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x03]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x04]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x05]
+
+v_min_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x16]
+
+v_min_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x26]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x00]
+
+v_min_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x5d,0x01,0xe4,0x00,0x00]
+
+v_min_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0xff,0xe4,0x00,0x00]
+
+v_min_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x5c,0x01,0xe4,0x00,0x00]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1b,0x00,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x40,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x41,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x42,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x43,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x30,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x34,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x38,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x3c,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x01,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x0f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x11,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x21,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x2f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x10]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x30]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x01]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x03]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00]
+
+v_min_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x10,0x00]
+
+v_min_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x20,0x00]
+
+v_min_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x40,0x00]
+
+v_min_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x80,0x00]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x5f,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0xff,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x00,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x01,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x02,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x03,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x04,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x05,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x0e,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x00,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x01,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x02,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x03,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x04,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x05,0x06]
+
+v_max_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x0e,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x00]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x01]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x02]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x03]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x04]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x05]
+
+v_max_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x0e]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x00]
+
+v_max_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x5f,0x01,0xe4,0x00,0x00]
+
+v_max_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0xff,0xe4,0x00,0x00]
+
+v_max_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x5e,0x01,0xe4,0x00,0x00]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x42,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x43,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x30,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x34,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x38,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x3c,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x10]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x30]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x01]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x03]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x61,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0xff,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x00,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x01,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x02,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x03,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x04,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x05,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x0e,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x00,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x01,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x02,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x03,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x04,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x05,0x06]
+
+v_max_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x0e,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x00]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x01]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x02]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x03]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x04]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x05]
+
+v_max_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x0e]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x00]
+
+v_max_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x61,0x01,0xe4,0x00,0x00]
+
+v_max_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0xff,0xe4,0x00,0x00]
+
+v_max_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x60,0x01,0xe4,0x00,0x00]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x42,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x43,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x30,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x34,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x38,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x3c,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x10]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x30]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x01]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x03]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x63,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0xff,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x00,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x01,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x02,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x03,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x04,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x05,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x0e,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x00,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x01,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x02,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x03,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x04,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x05,0x06]
+
+v_min_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x0e,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x00]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x01]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x02]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x03]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x04]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x05]
+
+v_min_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x0e]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x00]
+
+v_min_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x63,0x01,0xe4,0x00,0x00]
+
+v_min_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0xff,0xe4,0x00,0x00]
+
+v_min_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x62,0x01,0xe4,0x00,0x00]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x42,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x43,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x30,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x34,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x38,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x3c,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x10]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x30]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x01]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x03]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0xff,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x00,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x01,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x02,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x03,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x04,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x05,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x0e,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x00,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x01,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x02,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x03,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x04,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x05,0x06]
+
+v_min_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x0e,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x00]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x01]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x02]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x03]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x04]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x05]
+
+v_min_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x0e]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x00]
+
+v_min_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00]
+
+v_min_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0xff,0xe4,0x00,0x00]
+
+v_min_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x64,0x01,0xe4,0x00,0x00]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x42,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x43,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x30,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x34,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x38,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x3c,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x10]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x30]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0xff,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x26,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x00,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x01,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x02,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x03,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x04,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x05,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x0e,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x00,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x01,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x02,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x03,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x04,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x05,0x06]
+
+v_ldexp_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x16,0x06]
+
+v_ldexp_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x26,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x00]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x01]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x02]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x03]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x04]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x05]
+
+v_ldexp_f16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x0e]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0xff,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x66,0x01,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x42,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x43,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x30,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x34,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x38,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x3c,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x10]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x30]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
+
+v_ldexp_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
+
+v_ldexp_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
new file mode 100644
index 0000000000000..429133b3c1a40
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop3.s
@@ -0,0 +1,43843 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+v_interp_p1_f32_e64 v5, v2, attr0.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v255, v2, attr0.x
+// CHECK: [0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr1.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr31.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr32.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x20,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v255, attr0.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0xfe,0x03,0x00]
+
+v_interp_p1_f32_e64 v5, -v2, attr0.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p1_f32_e64 v5, |v2|, attr0.x
+// CHECK: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.y
+// CHECK: [0x05,0x00,0x70,0xd2,0x40,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.z
+// CHECK: [0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.w
+// CHECK: [0x05,0x00,0x70,0xd2,0xc0,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x clamp
+// CHECK: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:4
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x10]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x div:2
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x18]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v255, v2, attr0.x
+// CHECK: [0xff,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr1.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x01,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr31.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr32.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x20,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v255, attr0.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0xfe,0x03,0x00]
+
+v_interp_p2_f32_e64 v5, -v2, attr0.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p2_f32_e64 v5, |v2|, attr0.x
+// CHECK: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.y
+// CHECK: [0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.z
+// CHECK: [0x05,0x00,0x71,0xd2,0x80,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.w
+// CHECK: [0x05,0x00,0x71,0xd2,0xc0,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x clamp
+// CHECK: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x mul:2
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x08]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x mul:4
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x div:2
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x18]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v255, p10, attr0.x
+// CHECK: [0xff,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr1.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x01,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr31.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x1f,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr32.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p20, attr0.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p0, attr0.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x04,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.y
+// CHECK: [0x05,0x00,0x72,0xd2,0x40,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.z
+// CHECK: [0x05,0x00,0x72,0xd2,0x80,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.w
+// CHECK: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x clamp
+// CHECK: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x div:2
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
+
+v_nop_e64
+// CHECK: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x41,0xd1,0x01,0x01,0x00,0x00]
+
+v_mov_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x41,0xd1,0x01,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x41,0xd1,0xff,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x41,0xd1,0x01,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, s101
+// CHECK: [0x05,0x00,0x41,0xd1,0x65,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x41,0xd1,0x66,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x41,0xd1,0x67,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x41,0xd1,0x6a,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x41,0xd1,0x6b,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x41,0xd1,0x6c,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x41,0xd1,0x6d,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x41,0xd1,0x6e,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x41,0xd1,0x6f,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x41,0xd1,0x7b,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x41,0xd1,0x7c,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x41,0xd1,0x7e,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x41,0xd1,0x7f,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x41,0xd1,0x80,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x41,0xd1,0xc1,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x41,0xd1,0xf0,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x41,0xd1,0xf7,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x41,0xd1,0xfb,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x41,0xd1,0xfc,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x41,0xd1,0xfd,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x43,0xd1,0x02,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x43,0xd1,0x04,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[100:101]
+// CHECK: [0x05,0x00,0x43,0xd1,0x64,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x43,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x43,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, tba
+// CHECK: [0x05,0x00,0x43,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, tma
+// CHECK: [0x05,0x00,0x43,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, ttmp[10:11]
+// CHECK: [0x05,0x00,0x43,0xd1,0x7a,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x43,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x43,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x43,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x43,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x43,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x43,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x43,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x43,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_i32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x43,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[254:255], v1
+// CHECK: [0xfe,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v255
+// CHECK: [0x05,0x00,0x44,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s1
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s101
+// CHECK: [0x05,0x00,0x44,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], flat_scratch_lo
+// CHECK: [0x05,0x00,0x44,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], flat_scratch_hi
+// CHECK: [0x05,0x00,0x44,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_lo
+// CHECK: [0x05,0x00,0x44,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_hi
+// CHECK: [0x05,0x00,0x44,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], tba_lo
+// CHECK: [0x05,0x00,0x44,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], tba_hi
+// CHECK: [0x05,0x00,0x44,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], tma_lo
+// CHECK: [0x05,0x00,0x44,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], tma_hi
+// CHECK: [0x05,0x00,0x44,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], ttmp11
+// CHECK: [0x05,0x00,0x44,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], m0
+// CHECK: [0x05,0x00,0x44,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_lo
+// CHECK: [0x05,0x00,0x44,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_hi
+// CHECK: [0x05,0x00,0x44,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x44,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x44,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x44,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x44,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x44,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x44,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x44,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_lds_direct
+// CHECK: [0x05,0x00,0x44,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1 clamp
+// CHECK: [0x05,0x80,0x44,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1 mul:2
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_i32_e64 v[5:6], v1 mul:4
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_i32_e64 v[5:6], v1 div:2
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_i32_e64 v5, v1
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v255, v1
+// CHECK: [0xff,0x00,0x45,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v255
+// CHECK: [0x05,0x00,0x45,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s1
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s101
+// CHECK: [0x05,0x00,0x45,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x45,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x45,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x45,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x45,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x45,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x45,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x45,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x45,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x45,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, m0
+// CHECK: [0x05,0x00,0x45,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x45,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x45,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, 0
+// CHECK: [0x05,0x00,0x45,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, -1
+// CHECK: [0x05,0x00,0x45,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x45,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x45,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x45,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x45,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x45,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x45,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x45,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_i32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_i32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_u32_e64 v5, v1
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v255, v1
+// CHECK: [0xff,0x00,0x46,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v255
+// CHECK: [0x05,0x00,0x46,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s1
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s101
+// CHECK: [0x05,0x00,0x46,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x46,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x46,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x46,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x46,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x46,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x46,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x46,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x46,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x46,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, m0
+// CHECK: [0x05,0x00,0x46,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x46,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x46,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, 0
+// CHECK: [0x05,0x00,0x46,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, -1
+// CHECK: [0x05,0x00,0x46,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x46,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x46,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x46,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x46,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x46,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x46,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x46,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_u32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_u32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_u32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x47,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x47,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x47,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x47,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x47,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x47,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x47,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x47,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x47,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x47,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x47,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x47,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x47,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x47,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x47,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x47,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x47,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x47,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x47,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x47,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x47,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x47,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x47,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_u32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x47,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x48,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x48,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x48,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x48,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x48,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x48,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x48,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x48,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x48,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x48,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x48,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x48,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x48,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x48,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x48,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x48,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x48,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x48,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x48,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x48,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x48,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x48,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x48,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x4a,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x4a,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4a,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4a,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4a,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x4a,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x4a,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x4a,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x4a,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x4a,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x4a,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4a,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x4a,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x4a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4a,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4a,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4a,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_f16_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x4a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f16_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f16_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x4b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x4b,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x4b,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4b,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4b,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x4b,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x4b,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x4b,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x4b,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x4b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x4b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x4b,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x4b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_f32_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x4b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_f16_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_f16_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_rpi_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x4c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x4c,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x4c,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4c,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4c,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x4c,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x4c,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x4c,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x4c,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x4c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x4c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x4c,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x4c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_rpi_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x4d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x4d,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x4d,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4d,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4d,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4d,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4d,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x4d,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x4d,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x4d,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x4d,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x4d,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x4d,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4d,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4d,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x4d,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x4d,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4d,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4d,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4d,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4d,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4d,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4d,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_flr_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v255, v1
+// CHECK: [0xff,0x00,0x4e,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v255
+// CHECK: [0x05,0x00,0x4e,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s1
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s101
+// CHECK: [0x05,0x00,0x4e,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4e,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4e,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4e,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4e,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x4e,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x4e,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x4e,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x4e,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x4e,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, m0
+// CHECK: [0x05,0x00,0x4e,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4e,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4e,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, 0
+// CHECK: [0x05,0x00,0x4e,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, -1
+// CHECK: [0x05,0x00,0x4e,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4e,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4e,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4e,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4e,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4e,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4e,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x4e,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_off_f32_i4_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_off_f32_i4_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x4f,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x4f,0xd1,0xfe,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x02,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x04,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[100:101]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x64,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x4f,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x4f,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, tba
+// CHECK: [0x05,0x00,0x4f,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, tma
+// CHECK: [0x05,0x00,0x4f,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, ttmp[10:11]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x7a,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x4f,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x4f,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x4f,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4f,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4f,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4f,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4f,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4f,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_f32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x4f,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[1:2] clamp
+// CHECK: [0x05,0x80,0x4f,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[1:2] mul:2
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_f64_e64 v5, v[1:2] mul:4
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_f64_e64 v5, v[1:2] div:2
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f64_f32_e64 v[5:6], v1
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[254:255], v1
+// CHECK: [0xfe,0x00,0x50,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v255
+// CHECK: [0x05,0x00,0x50,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s1
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s101
+// CHECK: [0x05,0x00,0x50,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], flat_scratch_lo
+// CHECK: [0x05,0x00,0x50,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], flat_scratch_hi
+// CHECK: [0x05,0x00,0x50,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_lo
+// CHECK: [0x05,0x00,0x50,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_hi
+// CHECK: [0x05,0x00,0x50,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], tba_lo
+// CHECK: [0x05,0x00,0x50,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], tba_hi
+// CHECK: [0x05,0x00,0x50,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], tma_lo
+// CHECK: [0x05,0x00,0x50,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], tma_hi
+// CHECK: [0x05,0x00,0x50,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], ttmp11
+// CHECK: [0x05,0x00,0x50,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], m0
+// CHECK: [0x05,0x00,0x50,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_lo
+// CHECK: [0x05,0x00,0x50,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_hi
+// CHECK: [0x05,0x00,0x50,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x50,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x50,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x50,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x50,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x50,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x50,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x50,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_lds_direct
+// CHECK: [0x05,0x00,0x50,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -v1
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_f64_f32_e64 v[5:6], |v1|
+// CHECK: [0x05,0x01,0x50,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v1 clamp
+// CHECK: [0x05,0x80,0x50,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v1 mul:2
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_f32_e64 v[5:6], v1 mul:4
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_f32_e64 v[5:6], v1 div:2
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte0_e64 v5, v1
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v255, v1
+// CHECK: [0xff,0x00,0x51,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v255
+// CHECK: [0x05,0x00,0x51,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s1
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s101
+// CHECK: [0x05,0x00,0x51,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x51,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x51,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x51,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x51,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x51,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x51,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x51,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x51,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x51,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, m0
+// CHECK: [0x05,0x00,0x51,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x51,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x51,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, 0
+// CHECK: [0x05,0x00,0x51,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, -1
+// CHECK: [0x05,0x00,0x51,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x51,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x51,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x51,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x51,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x51,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x51,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x51,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte0_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte0_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte1_e64 v5, v1
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v255, v1
+// CHECK: [0xff,0x00,0x52,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v255
+// CHECK: [0x05,0x00,0x52,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s1
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s101
+// CHECK: [0x05,0x00,0x52,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x52,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x52,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x52,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x52,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x52,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x52,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x52,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x52,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x52,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, m0
+// CHECK: [0x05,0x00,0x52,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x52,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x52,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, 0
+// CHECK: [0x05,0x00,0x52,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, -1
+// CHECK: [0x05,0x00,0x52,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x52,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x52,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x52,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x52,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x52,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x52,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x52,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte1_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte1_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte2_e64 v5, v1
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v255, v1
+// CHECK: [0xff,0x00,0x53,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v255
+// CHECK: [0x05,0x00,0x53,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s1
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s101
+// CHECK: [0x05,0x00,0x53,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x53,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x53,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x53,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x53,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x53,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x53,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x53,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x53,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x53,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, m0
+// CHECK: [0x05,0x00,0x53,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x53,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x53,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, 0
+// CHECK: [0x05,0x00,0x53,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, -1
+// CHECK: [0x05,0x00,0x53,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x53,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x53,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x53,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x53,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x53,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x53,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x53,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte2_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte2_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte3_e64 v5, v1
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v255, v1
+// CHECK: [0xff,0x00,0x54,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v255
+// CHECK: [0x05,0x00,0x54,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s1
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s101
+// CHECK: [0x05,0x00,0x54,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x54,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x54,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x54,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x54,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x54,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x54,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x54,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x54,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x54,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, m0
+// CHECK: [0x05,0x00,0x54,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x54,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x54,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, 0
+// CHECK: [0x05,0x00,0x54,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, -1
+// CHECK: [0x05,0x00,0x54,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x54,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x54,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x54,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x54,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x54,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x54,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x54,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte3_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte3_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_u32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x55,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x55,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x55,0xd1,0xfe,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x55,0xd1,0x02,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x55,0xd1,0x04,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[100:101]
+// CHECK: [0x05,0x00,0x55,0xd1,0x64,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x55,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x55,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, tba
+// CHECK: [0x05,0x00,0x55,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, tma
+// CHECK: [0x05,0x00,0x55,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, ttmp[10:11]
+// CHECK: [0x05,0x00,0x55,0xd1,0x7a,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x55,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x55,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x55,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x55,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x55,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x55,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x55,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x55,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x55,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_u32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x55,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[254:255], v1
+// CHECK: [0xfe,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v255
+// CHECK: [0x05,0x00,0x56,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s1
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s101
+// CHECK: [0x05,0x00,0x56,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], flat_scratch_lo
+// CHECK: [0x05,0x00,0x56,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], flat_scratch_hi
+// CHECK: [0x05,0x00,0x56,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_lo
+// CHECK: [0x05,0x00,0x56,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_hi
+// CHECK: [0x05,0x00,0x56,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], tba_lo
+// CHECK: [0x05,0x00,0x56,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], tba_hi
+// CHECK: [0x05,0x00,0x56,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], tma_lo
+// CHECK: [0x05,0x00,0x56,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], tma_hi
+// CHECK: [0x05,0x00,0x56,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], ttmp11
+// CHECK: [0x05,0x00,0x56,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], m0
+// CHECK: [0x05,0x00,0x56,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_lo
+// CHECK: [0x05,0x00,0x56,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_hi
+// CHECK: [0x05,0x00,0x56,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x56,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x56,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x56,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x56,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x56,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x56,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x56,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_lds_direct
+// CHECK: [0x05,0x00,0x56,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1 clamp
+// CHECK: [0x05,0x80,0x56,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1 mul:2
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_u32_e64 v[5:6], v1 mul:4
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_u32_e64 v[5:6], v1 div:2
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x18]
+
+v_trunc_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x57,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x57,0xd1,0xfe,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x57,0xd1,0x02,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x57,0xd1,0x04,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x57,0xd1,0x64,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x57,0xd1,0x66,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x57,0xd1,0x6a,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x57,0xd1,0x6c,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x57,0xd1,0x6e,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x57,0xd1,0x7a,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x57,0xd1,0x7e,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x57,0xd1,0x80,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x57,0xd1,0xc1,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x57,0xd1,0xf0,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x57,0xd1,0xf7,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x57,0xd1,0xfb,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x57,0xd1,0xfc,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x57,0xd1,0xfd,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x20]
+
+v_trunc_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x57,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x57,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x08]
+
+v_trunc_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x10]
+
+v_trunc_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x18]
+
+v_ceil_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x58,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x58,0xd1,0xfe,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x58,0xd1,0x02,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x58,0xd1,0x04,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x58,0xd1,0x64,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x58,0xd1,0x66,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x58,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x58,0xd1,0x6c,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x58,0xd1,0x6e,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x58,0xd1,0x7a,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x58,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x58,0xd1,0x80,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x58,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x58,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x58,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x58,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x58,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x58,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x20]
+
+v_ceil_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x58,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x58,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x08]
+
+v_ceil_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x10]
+
+v_ceil_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x18]
+
+v_rndne_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x59,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x59,0xd1,0xfe,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x59,0xd1,0x02,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x59,0xd1,0x04,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x59,0xd1,0x64,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x59,0xd1,0x66,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x59,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x59,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x59,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x59,0xd1,0x7a,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x59,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x59,0xd1,0x80,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x59,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x59,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x59,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x59,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x59,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x59,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x20]
+
+v_rndne_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x59,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x59,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x08]
+
+v_rndne_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x10]
+
+v_rndne_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x18]
+
+v_floor_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x5a,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x5a,0xd1,0xfe,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x02,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x04,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x64,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x5a,0xd1,0x66,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x5a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x5a,0xd1,0x6c,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x5a,0xd1,0x6e,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x7a,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x5a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x5a,0xd1,0x80,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x5a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x5a,0xd1,0xf0,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x5a,0xd1,0xf7,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x5a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x5a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x5a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x20]
+
+v_floor_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x5a,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x5a,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x08]
+
+v_floor_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x10]
+
+v_floor_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x18]
+
+v_fract_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5b,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5b,0xd1,0xff,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5b,0xd1,0x65,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5b,0xd1,0x66,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5b,0xd1,0x67,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x5b,0xd1,0x6c,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x5b,0xd1,0x6d,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x5b,0xd1,0x6e,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x5b,0xd1,0x6f,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x5b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5b,0xd1,0x80,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x20]
+
+v_fract_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5b,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5b,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x08]
+
+v_fract_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x10]
+
+v_fract_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x18]
+
+v_trunc_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5c,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5c,0xd1,0xff,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5c,0xd1,0x65,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5c,0xd1,0x66,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5c,0xd1,0x67,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x5c,0xd1,0x6c,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x5c,0xd1,0x6d,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x5c,0xd1,0x6e,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x5c,0xd1,0x6f,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x5c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5c,0xd1,0x80,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x20]
+
+v_trunc_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5c,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5c,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x08]
+
+v_trunc_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x10]
+
+v_trunc_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x18]
+
+v_ceil_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5d,0xd1,0xff,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5d,0xd1,0x65,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5d,0xd1,0x66,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5d,0xd1,0x67,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5d,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5d,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x5d,0xd1,0x6c,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x5d,0xd1,0x6d,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x5d,0xd1,0x6e,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x5d,0xd1,0x6f,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x5d,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5d,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5d,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5d,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5d,0xd1,0x80,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5d,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5d,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5d,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5d,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5d,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5d,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x20]
+
+v_ceil_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x08]
+
+v_ceil_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x10]
+
+v_ceil_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x18]
+
+v_rndne_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5e,0xd1,0xff,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5e,0xd1,0x65,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5e,0xd1,0x66,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5e,0xd1,0x67,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5e,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5e,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x5e,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x5e,0xd1,0x6d,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x5e,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x5e,0xd1,0x6f,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x5e,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5e,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5e,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5e,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5e,0xd1,0x80,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5e,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5e,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5e,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5e,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5e,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5e,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5e,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x20]
+
+v_rndne_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x08]
+
+v_rndne_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x10]
+
+v_rndne_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x18]
+
+v_floor_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5f,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5f,0xd1,0xff,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5f,0xd1,0x65,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5f,0xd1,0x66,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5f,0xd1,0x67,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5f,0xd1,0x6a,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5f,0xd1,0x6b,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x5f,0xd1,0x6c,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x5f,0xd1,0x6d,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x5f,0xd1,0x6e,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x5f,0xd1,0x6f,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x5f,0xd1,0x7b,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5f,0xd1,0x7c,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5f,0xd1,0x7e,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5f,0xd1,0x7f,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5f,0xd1,0x80,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5f,0xd1,0xc1,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5f,0xd1,0xf0,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5f,0xd1,0xf7,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5f,0xd1,0xfb,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5f,0xd1,0xfc,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5f,0xd1,0xfd,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5f,0xd1,0xfe,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x20]
+
+v_floor_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5f,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5f,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x08]
+
+v_floor_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x10]
+
+v_floor_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x18]
+
+v_exp_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x60,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x60,0xd1,0xff,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x60,0xd1,0x65,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x60,0xd1,0x66,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x60,0xd1,0x67,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x60,0xd1,0x6a,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x60,0xd1,0x6b,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x60,0xd1,0x6c,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x60,0xd1,0x6d,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x60,0xd1,0x6e,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x60,0xd1,0x6f,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x60,0xd1,0x7b,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x60,0xd1,0x7c,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x60,0xd1,0x7e,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x60,0xd1,0x7f,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x60,0xd1,0x80,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x60,0xd1,0xc1,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x60,0xd1,0xf0,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x60,0xd1,0xf7,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x60,0xd1,0xfb,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x60,0xd1,0xfc,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x60,0xd1,0xfd,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x60,0xd1,0xfe,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x20]
+
+v_exp_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x60,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x60,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x08]
+
+v_exp_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x10]
+
+v_exp_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x18]
+
+v_log_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x61,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x61,0xd1,0xff,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x61,0xd1,0x65,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x61,0xd1,0x66,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x61,0xd1,0x67,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x61,0xd1,0x6a,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x61,0xd1,0x6b,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x61,0xd1,0x6c,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x61,0xd1,0x6d,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x61,0xd1,0x6e,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x61,0xd1,0x6f,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x61,0xd1,0x7b,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x61,0xd1,0x7c,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x61,0xd1,0x7e,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x61,0xd1,0x7f,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x61,0xd1,0x80,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x61,0xd1,0xc1,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x61,0xd1,0xf0,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x61,0xd1,0xf7,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x61,0xd1,0xfb,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x61,0xd1,0xfc,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x61,0xd1,0xfd,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x61,0xd1,0xfe,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x20]
+
+v_log_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x61,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x61,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x08]
+
+v_log_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x10]
+
+v_log_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x18]
+
+v_rcp_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x62,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x62,0xd1,0xff,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x62,0xd1,0x65,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x62,0xd1,0x66,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x62,0xd1,0x67,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x62,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x62,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x62,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x62,0xd1,0x6d,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x62,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x62,0xd1,0x6f,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x62,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x62,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x62,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x62,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x62,0xd1,0x80,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x62,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x62,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x62,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x62,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x62,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x62,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x62,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x20]
+
+v_rcp_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x62,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x62,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x08]
+
+v_rcp_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x10]
+
+v_rcp_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x18]
+
+v_rcp_iflag_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x63,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x63,0xd1,0xff,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x63,0xd1,0x65,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x63,0xd1,0x66,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x63,0xd1,0x67,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x63,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x63,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x63,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x63,0xd1,0x6d,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x63,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x63,0xd1,0x6f,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x63,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x63,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x63,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x63,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x63,0xd1,0x80,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x63,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x63,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x63,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x63,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x63,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x63,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x63,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x20]
+
+v_rcp_iflag_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x63,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x63,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x08]
+
+v_rcp_iflag_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x10]
+
+v_rcp_iflag_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x18]
+
+v_rsq_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x64,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x64,0xd1,0xff,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x64,0xd1,0x65,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x64,0xd1,0x66,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x64,0xd1,0x67,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x64,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x64,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x64,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x64,0xd1,0x6d,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x64,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x64,0xd1,0x6f,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x64,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x64,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x64,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x64,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x64,0xd1,0x80,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x64,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x64,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x64,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x64,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x64,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x64,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x64,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x20]
+
+v_rsq_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x64,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x64,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x08]
+
+v_rsq_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x10]
+
+v_rsq_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x18]
+
+v_rcp_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x65,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x65,0xd1,0xfe,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x65,0xd1,0x02,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x65,0xd1,0x04,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x65,0xd1,0x64,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x65,0xd1,0x66,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x65,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x65,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x65,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x65,0xd1,0x7a,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x65,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x65,0xd1,0x80,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x65,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x65,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x65,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x65,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x65,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x65,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x20]
+
+v_rcp_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x65,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x65,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x08]
+
+v_rcp_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x10]
+
+v_rcp_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x18]
+
+v_rsq_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x66,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x66,0xd1,0xfe,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x66,0xd1,0x02,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x66,0xd1,0x04,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x66,0xd1,0x64,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x66,0xd1,0x66,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x66,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x66,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x66,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x66,0xd1,0x7a,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x66,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x66,0xd1,0x80,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x66,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x66,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x66,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x66,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x66,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x66,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x20]
+
+v_rsq_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x66,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x66,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x08]
+
+v_rsq_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x10]
+
+v_rsq_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x18]
+
+v_sqrt_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x67,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x67,0xd1,0xff,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x67,0xd1,0x65,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x67,0xd1,0x66,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x67,0xd1,0x67,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x67,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x67,0xd1,0x6b,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x67,0xd1,0x6c,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x67,0xd1,0x6d,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x67,0xd1,0x6e,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x67,0xd1,0x6f,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x67,0xd1,0x7b,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x67,0xd1,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x67,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x67,0xd1,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x67,0xd1,0x80,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x67,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x67,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x67,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x67,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x67,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x67,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x67,0xd1,0xfe,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x20]
+
+v_sqrt_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x67,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x67,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x08]
+
+v_sqrt_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x10]
+
+v_sqrt_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x18]
+
+v_sqrt_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x68,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x68,0xd1,0xfe,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x68,0xd1,0x02,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x68,0xd1,0x04,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x68,0xd1,0x64,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x68,0xd1,0x66,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x68,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x68,0xd1,0x6c,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x68,0xd1,0x6e,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x68,0xd1,0x7a,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x68,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x68,0xd1,0x80,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x68,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x68,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x68,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x68,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x68,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x68,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x20]
+
+v_sqrt_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x68,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x68,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x08]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x10]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x18]
+
+v_sin_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x69,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x69,0xd1,0xff,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x69,0xd1,0x65,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x69,0xd1,0x66,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x69,0xd1,0x67,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x69,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x69,0xd1,0x6b,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x69,0xd1,0x6c,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x69,0xd1,0x6d,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x69,0xd1,0x6e,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x69,0xd1,0x6f,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x69,0xd1,0x7b,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x69,0xd1,0x7c,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x69,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x69,0xd1,0x7f,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x69,0xd1,0x80,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x69,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x69,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x69,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x69,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x69,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x69,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x69,0xd1,0xfe,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x20]
+
+v_sin_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x69,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x69,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x08]
+
+v_sin_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x10]
+
+v_sin_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x18]
+
+v_cos_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6a,0xd1,0xff,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6a,0xd1,0x65,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6a,0xd1,0x66,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6a,0xd1,0x67,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6a,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x6a,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x6a,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x6a,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x6a,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x6a,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6a,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6a,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6a,0xd1,0x80,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6a,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6a,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6a,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x20]
+
+v_cos_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x6a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x6a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x08]
+
+v_cos_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x10]
+
+v_cos_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x18]
+
+v_not_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
+
+v_not_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6b,0xd1,0xff,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6b,0xd1,0x01,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6b,0xd1,0x65,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6b,0xd1,0x66,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6b,0xd1,0x67,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x6b,0xd1,0x6c,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x6b,0xd1,0x6d,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x6b,0xd1,0x6e,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x6b,0xd1,0x6f,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x6b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6b,0xd1,0x80,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6c,0xd1,0x01,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6c,0xd1,0x01,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6c,0xd1,0xff,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6c,0xd1,0x01,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6c,0xd1,0x65,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6c,0xd1,0x66,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6c,0xd1,0x67,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x6c,0xd1,0x6c,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x6c,0xd1,0x6d,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x6c,0xd1,0x6e,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x6c,0xd1,0x6f,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x6c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6c,0xd1,0x80,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6d,0xd1,0xff,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6d,0xd1,0x01,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6d,0xd1,0x65,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6d,0xd1,0x66,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6d,0xd1,0x67,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6d,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6d,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x6d,0xd1,0x6c,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x6d,0xd1,0x6d,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x6d,0xd1,0x6e,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x6d,0xd1,0x6f,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x6d,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6d,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6d,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6d,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6d,0xd1,0x80,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6d,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6d,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6d,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6d,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6d,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6d,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6d,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6e,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6e,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6e,0xd1,0xff,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6e,0xd1,0x01,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6e,0xd1,0x65,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6e,0xd1,0x66,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6e,0xd1,0x67,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6e,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6e,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x6e,0xd1,0x6c,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x6e,0xd1,0x6d,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x6e,0xd1,0x6e,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x6e,0xd1,0x6f,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x6e,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6e,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6e,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6e,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6e,0xd1,0x80,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6e,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6e,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6e,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6e,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6e,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6e,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6e,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6f,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6f,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6f,0xd1,0xff,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6f,0xd1,0x01,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6f,0xd1,0x65,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6f,0xd1,0x66,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6f,0xd1,0x67,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6f,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6f,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x6f,0xd1,0x6c,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x6f,0xd1,0x6d,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x6f,0xd1,0x6e,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x6f,0xd1,0x6f,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x6f,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6f,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6f,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6f,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6f,0xd1,0x80,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6f,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6f,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6f,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6f,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6f,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6f,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6f,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x70,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x70,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x70,0xd1,0xfe,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x70,0xd1,0x02,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x70,0xd1,0x04,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[100:101]
+// CHECK: [0x05,0x00,0x70,0xd1,0x64,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x70,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x70,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, tba
+// CHECK: [0x05,0x00,0x70,0xd1,0x6c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, tma
+// CHECK: [0x05,0x00,0x70,0xd1,0x6e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, ttmp[10:11]
+// CHECK: [0x05,0x00,0x70,0xd1,0x7a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x70,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x70,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x70,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x70,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x70,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x70,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x70,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x70,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x70,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x70,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x71,0xd1,0xfe,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x71,0xd1,0x02,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x71,0xd1,0x04,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x71,0xd1,0x64,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x71,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x71,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x71,0xd1,0x6c,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x71,0xd1,0x6e,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x71,0xd1,0x7a,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x71,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x71,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x71,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x71,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x71,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x71,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x71,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x71,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x71,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x71,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x08]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x10]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x18]
+
+v_fract_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x72,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x72,0xd1,0xfe,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x72,0xd1,0x04,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x72,0xd1,0x64,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x72,0xd1,0x66,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x72,0xd1,0x6a,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], tba
+// CHECK: [0x05,0x00,0x72,0xd1,0x6c,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], tma
+// CHECK: [0x05,0x00,0x72,0xd1,0x6e,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], ttmp[10:11]
+// CHECK: [0x05,0x00,0x72,0xd1,0x7a,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x72,0xd1,0x7e,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x72,0xd1,0x80,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x72,0xd1,0xc1,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x72,0xd1,0xf0,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x72,0xd1,0xf7,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x72,0xd1,0xfb,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x72,0xd1,0xfc,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x72,0xd1,0xfd,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x20]
+
+v_fract_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x72,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x72,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x08]
+
+v_fract_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x10]
+
+v_fract_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x18]
+
+v_frexp_exp_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x73,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x73,0xd1,0xff,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x73,0xd1,0x65,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x73,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x73,0xd1,0x67,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x73,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x73,0xd1,0x6b,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x73,0xd1,0x6c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x73,0xd1,0x6d,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x73,0xd1,0x6e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x73,0xd1,0x6f,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x73,0xd1,0x7b,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x73,0xd1,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x73,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x73,0xd1,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x73,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x73,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x73,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x73,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x73,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x73,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x73,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x73,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x73,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x74,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x74,0xd1,0xff,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x74,0xd1,0x65,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x74,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x74,0xd1,0x67,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x74,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x74,0xd1,0x6b,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x74,0xd1,0x6c,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x74,0xd1,0x6d,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x74,0xd1,0x6e,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x74,0xd1,0x6f,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x74,0xd1,0x7b,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x74,0xd1,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x74,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x74,0xd1,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x74,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x74,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x74,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x74,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x74,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x74,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x74,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x74,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x74,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x74,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x08]
+
+v_frexp_mant_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x10]
+
+v_frexp_mant_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x18]
+
+v_clrexcp_e64
+// CHECK: [0x00,0x00,0x75,0xd1,0x00,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x76,0xd1,0x01,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x76,0xd1,0x01,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x76,0xd1,0xff,0x01,0x00,0x00]
+
+v_movreld_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x76,0xd1,0x7c,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x76,0xd1,0x80,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x76,0xd1,0xc1,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x76,0xd1,0xf0,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x76,0xd1,0xf7,0x00,0x00,0x00]
+
+v_movreld_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x76,0xd1,0xfe,0x00,0x00,0x00]
+
+v_movrels_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
+
+v_movrels_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
+
+v_movrels_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x77,0xd1,0xff,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x78,0xd1,0x01,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x78,0xd1,0x01,0x01,0x00,0x00]
+
+v_movrelsd_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x78,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v1
+// CHECK: [0x05,0x00,0x79,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v255, v1
+// CHECK: [0xff,0x00,0x79,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v255
+// CHECK: [0x05,0x00,0x79,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, s1
+// CHECK: [0x05,0x00,0x79,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, s101
+// CHECK: [0x05,0x00,0x79,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x79,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x79,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x79,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x79,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x79,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x79,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x79,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x79,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x79,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, m0
+// CHECK: [0x05,0x00,0x79,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x79,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x79,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, 0
+// CHECK: [0x05,0x00,0x79,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, -1
+// CHECK: [0x05,0x00,0x79,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x79,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x79,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x79,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x79,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x79,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7a,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7a,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7a,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7a,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7a,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7a,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x7a,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x7a,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x7a,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x7a,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x7a,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7a,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7a,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7a,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7a,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7b,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7b,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7b,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7b,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x7b,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x7b,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x7b,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x7b,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x7b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7b,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_u16_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7c,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7c,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7c,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7c,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x7c,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x7c,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x7c,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x7c,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x7c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7c,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_i16_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7c,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7d,0xd1,0xff,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7d,0xd1,0x65,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7d,0xd1,0x66,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7d,0xd1,0x67,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7d,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7d,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x7d,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x7d,0xd1,0x6d,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x7d,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x7d,0xd1,0x6f,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x7d,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7d,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7d,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7d,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7d,0xd1,0x80,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7d,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7d,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7d,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7d,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7d,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7d,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7d,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x20]
+
+v_rcp_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7d,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7d,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7e,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7e,0xd1,0xff,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7e,0xd1,0x65,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7e,0xd1,0x66,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7e,0xd1,0x67,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7e,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7e,0xd1,0x6b,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x7e,0xd1,0x6c,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x7e,0xd1,0x6d,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x7e,0xd1,0x6e,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x7e,0xd1,0x6f,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x7e,0xd1,0x7b,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7e,0xd1,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7e,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7e,0xd1,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7e,0xd1,0x80,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7e,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7e,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7e,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7e,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7e,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7e,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7e,0xd1,0xfe,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x01,0x00,0x20]
+
+v_sqrt_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7e,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7f,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7f,0xd1,0xff,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7f,0xd1,0x65,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7f,0xd1,0x66,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7f,0xd1,0x67,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7f,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7f,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x7f,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x7f,0xd1,0x6d,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x7f,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x7f,0xd1,0x6f,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x7f,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7f,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7f,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7f,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7f,0xd1,0x80,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7f,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7f,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7f,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7f,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7f,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7f,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7f,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x01,0x00,0x20]
+
+v_rsq_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7f,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7f,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x80,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x80,0xd1,0xff,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x80,0xd1,0x65,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x80,0xd1,0x66,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x80,0xd1,0x67,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x80,0xd1,0x6a,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x80,0xd1,0x6b,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x80,0xd1,0x6c,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x80,0xd1,0x6d,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x80,0xd1,0x6e,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x80,0xd1,0x6f,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x80,0xd1,0x7b,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x80,0xd1,0x7c,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x80,0xd1,0x7e,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x80,0xd1,0x7f,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x80,0xd1,0x80,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x80,0xd1,0xc1,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x80,0xd1,0xf0,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x80,0xd1,0xf7,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x80,0xd1,0xfb,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x80,0xd1,0xfc,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x80,0xd1,0xfd,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x80,0xd1,0xfe,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x01,0x00,0x20]
+
+v_log_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x80,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x80,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x81,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x81,0xd1,0xff,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x81,0xd1,0x65,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x81,0xd1,0x66,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x81,0xd1,0x67,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x81,0xd1,0x6a,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x81,0xd1,0x6b,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x81,0xd1,0x6c,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x81,0xd1,0x6d,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x81,0xd1,0x6e,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x81,0xd1,0x6f,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x81,0xd1,0x7b,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x81,0xd1,0x7c,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x81,0xd1,0x7e,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x81,0xd1,0x7f,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x81,0xd1,0x80,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x81,0xd1,0xc1,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x81,0xd1,0xf0,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x81,0xd1,0xf7,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x81,0xd1,0xfb,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x81,0xd1,0xfc,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x81,0xd1,0xfd,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x81,0xd1,0xfe,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x01,0x00,0x20]
+
+v_exp_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x81,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x81,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x82,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x82,0xd1,0xff,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x82,0xd1,0x65,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x82,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x82,0xd1,0x67,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x82,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x82,0xd1,0x6b,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x82,0xd1,0x6c,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x82,0xd1,0x6d,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x82,0xd1,0x6e,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x82,0xd1,0x6f,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x82,0xd1,0x7b,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x82,0xd1,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x82,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x82,0xd1,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x82,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x82,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x82,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x82,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x82,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x82,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x82,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x82,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x82,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x82,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x83,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x83,0xd1,0xff,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x83,0xd1,0x65,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x83,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x83,0xd1,0x67,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x83,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x83,0xd1,0x6b,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x83,0xd1,0x6c,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x83,0xd1,0x6d,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x83,0xd1,0x6e,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x83,0xd1,0x6f,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x83,0xd1,0x7b,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x83,0xd1,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x83,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x83,0xd1,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x83,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x83,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x83,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x83,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x83,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x83,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x83,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x83,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i16_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x83,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x84,0xd1,0xff,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x84,0xd1,0x65,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x84,0xd1,0x66,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x84,0xd1,0x67,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x84,0xd1,0x6a,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x84,0xd1,0x6b,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x84,0xd1,0x6c,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x84,0xd1,0x6d,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x84,0xd1,0x6e,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x84,0xd1,0x6f,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x84,0xd1,0x7b,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x84,0xd1,0x7c,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x84,0xd1,0x7e,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x84,0xd1,0x7f,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x84,0xd1,0x80,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x84,0xd1,0xc1,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x84,0xd1,0xf0,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x84,0xd1,0xf7,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x84,0xd1,0xfb,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x84,0xd1,0xfc,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x84,0xd1,0xfd,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x84,0xd1,0xfe,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x20]
+
+v_floor_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x84,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x84,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x85,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x85,0xd1,0xff,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x85,0xd1,0x65,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x85,0xd1,0x66,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x85,0xd1,0x67,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x85,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x85,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x85,0xd1,0x6c,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x85,0xd1,0x6d,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x85,0xd1,0x6e,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x85,0xd1,0x6f,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x85,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x85,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x85,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x85,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x85,0xd1,0x80,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x85,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x85,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x85,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x85,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x85,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x85,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x85,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x01,0x00,0x20]
+
+v_ceil_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x85,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x85,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x86,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x86,0xd1,0xff,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x86,0xd1,0x65,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x86,0xd1,0x66,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x86,0xd1,0x67,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x86,0xd1,0x6a,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x86,0xd1,0x6b,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x86,0xd1,0x6c,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x86,0xd1,0x6d,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x86,0xd1,0x6e,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x86,0xd1,0x6f,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x86,0xd1,0x7b,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x86,0xd1,0x7c,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x86,0xd1,0x7e,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x86,0xd1,0x7f,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x86,0xd1,0x80,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x86,0xd1,0xc1,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x86,0xd1,0xf0,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x86,0xd1,0xf7,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x86,0xd1,0xfb,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x86,0xd1,0xfc,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x86,0xd1,0xfd,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x86,0xd1,0xfe,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x01,0x00,0x20]
+
+v_trunc_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x86,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x86,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x87,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x87,0xd1,0xff,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x87,0xd1,0x65,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x87,0xd1,0x66,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x87,0xd1,0x67,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x87,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x87,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x87,0xd1,0x6c,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x87,0xd1,0x6d,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x87,0xd1,0x6e,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x87,0xd1,0x6f,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x87,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x87,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x87,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x87,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x87,0xd1,0x80,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x87,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x87,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x87,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x87,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x87,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x87,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x87,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x01,0x00,0x20]
+
+v_rndne_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x87,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x87,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x88,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x88,0xd1,0xff,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x88,0xd1,0x65,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x88,0xd1,0x66,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x88,0xd1,0x67,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x88,0xd1,0x6a,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x88,0xd1,0x6b,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x88,0xd1,0x6c,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x88,0xd1,0x6d,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x88,0xd1,0x6e,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x88,0xd1,0x6f,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x88,0xd1,0x7b,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x88,0xd1,0x7c,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x88,0xd1,0x7e,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x88,0xd1,0x7f,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x88,0xd1,0x80,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x88,0xd1,0xc1,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x88,0xd1,0xf0,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x88,0xd1,0xf7,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x88,0xd1,0xfb,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x88,0xd1,0xfc,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x88,0xd1,0xfd,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x88,0xd1,0xfe,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x01,0x00,0x20]
+
+v_fract_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x88,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x88,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x89,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x89,0xd1,0xff,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x89,0xd1,0x65,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x89,0xd1,0x66,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x89,0xd1,0x67,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x89,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x89,0xd1,0x6b,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x89,0xd1,0x6c,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x89,0xd1,0x6d,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x89,0xd1,0x6e,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x89,0xd1,0x6f,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x89,0xd1,0x7b,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x89,0xd1,0x7c,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x89,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x89,0xd1,0x7f,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x89,0xd1,0x80,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x89,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x89,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x89,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x89,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x89,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x89,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x89,0xd1,0xfe,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x01,0x00,0x20]
+
+v_sin_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x89,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x89,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x8a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x8a,0xd1,0xff,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x8a,0xd1,0x65,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8a,0xd1,0x66,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8a,0xd1,0x67,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8a,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x8a,0xd1,0x6c,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x8a,0xd1,0x6d,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x8a,0xd1,0x6e,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x8a,0xd1,0x6f,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x8a,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x8a,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8a,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x8a,0xd1,0x80,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x8a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8a,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8a,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8a,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x01,0x00,0x20]
+
+v_cos_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x8a,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x8b,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x8b,0xd1,0xff,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x8b,0xd1,0x65,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8b,0xd1,0x66,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8b,0xd1,0x67,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x8b,0xd1,0x6c,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x8b,0xd1,0x6d,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x8b,0xd1,0x6e,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x8b,0xd1,0x6f,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x8b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x8b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x8b,0xd1,0x80,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x8b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x20]
+
+v_exp_legacy_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8b,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x8b,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x08]
+
+v_exp_legacy_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x10]
+
+v_exp_legacy_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x18]
+
+v_log_legacy_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x8c,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x8c,0xd1,0xff,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x8c,0xd1,0x65,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8c,0xd1,0x66,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8c,0xd1,0x67,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, tba_lo
+// CHECK: [0x05,0x00,0x8c,0xd1,0x6c,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, tba_hi
+// CHECK: [0x05,0x00,0x8c,0xd1,0x6d,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, tma_lo
+// CHECK: [0x05,0x00,0x8c,0xd1,0x6e,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, tma_hi
+// CHECK: [0x05,0x00,0x8c,0xd1,0x6f,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, ttmp11
+// CHECK: [0x05,0x00,0x8c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x8c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x8c,0xd1,0x80,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x8c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x20]
+
+v_log_legacy_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8c,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x8c,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x08]
+
+v_log_legacy_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x10]
+
+v_log_legacy_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x18]
+
+v_cndmask_b32_e64 v5, v1, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x1a,0x00]
+
+v_cndmask_b32_e64 v255, v1, v2, s[6:7]
+// CHECK: [0xff,0x00,0x00,0xd1,0x01,0x05,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, v255, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xff,0x05,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, 0, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x80,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, -1, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xc1,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, 0.5, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xf0,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, -4.0, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xf7,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, src_lds_direct, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xfe,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, v1, v255, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xff,0x1b,0x00]
+
+v_cndmask_b32_e64 v5, v1, 0, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x01,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, -1, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x83,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, 0.5, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xe1,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, -4.0, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xef,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, v2, s[8:9]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x22,0x00]
+
+v_cndmask_b32_e64 v5, v1, v2, s[100:101]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x92,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, flat_scratch
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, vcc
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, tba
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xb2,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, tma
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xba,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01]
+
+v_add_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x65,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x66,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x67,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x6a,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x6b,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x6c,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x6d,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x6e,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x6f,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x7b,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x7c,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x7e,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x7f,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x80,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xc1,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xf0,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xf7,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xfb,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xfc,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xfd,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xfe,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xff,0x03,0x00]
+
+v_add_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x00,0x00]
+
+v_add_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcb,0x00,0x00]
+
+v_add_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcd,0x00,0x00]
+
+v_add_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcf,0x00,0x00]
+
+v_add_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd5,0x00,0x00]
+
+v_add_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd7,0x00,0x00]
+
+v_add_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd9,0x00,0x00]
+
+v_add_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xdb,0x00,0x00]
+
+v_add_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xdd,0x00,0x00]
+
+v_add_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xdf,0x00,0x00]
+
+v_add_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf7,0x00,0x00]
+
+v_add_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf9,0x00,0x00]
+
+v_add_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xfd,0x00,0x00]
+
+v_add_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xff,0x00,0x00]
+
+v_add_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x01,0x01,0x00]
+
+v_add_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x83,0x01,0x00]
+
+v_add_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xe1,0x01,0x00]
+
+v_add_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xef,0x01,0x00]
+
+v_add_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf7,0x01,0x00]
+
+v_add_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf9,0x01,0x00]
+
+v_add_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xfb,0x01,0x00]
+
+v_add_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x20]
+
+v_add_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x40]
+
+v_add_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x60]
+
+v_add_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x08]
+
+v_add_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x10]
+
+v_add_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x18]
+
+v_sub_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xff,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x65,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x66,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x67,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x6a,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x6b,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x6c,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x6d,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x6e,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x6f,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x7b,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x7c,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x7e,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x7f,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x80,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xc1,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xf0,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xf7,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xfb,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xfc,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xfd,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xfe,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xff,0x03,0x00]
+
+v_sub_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcb,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcd,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcf,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd5,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd7,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd9,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xdb,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xdd,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xdf,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf7,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf9,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xfd,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xff,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x01,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x83,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xe1,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xef,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf7,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf9,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xfb,0x01,0x00]
+
+v_sub_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x20]
+
+v_sub_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x40]
+
+v_sub_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x60]
+
+v_sub_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x08]
+
+v_sub_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x10]
+
+v_sub_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x18]
+
+v_subrev_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xff,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x65,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x66,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x67,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x6a,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x6b,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x6c,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x6d,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x6e,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x6f,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x7b,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x7c,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x7e,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x7f,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x80,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xc1,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xf0,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xf7,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xfb,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xfc,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xfd,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xff,0x03,0x00]
+
+v_subrev_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcb,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcd,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcf,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd5,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd7,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd9,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xdb,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xdd,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xdf,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf7,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf9,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xfd,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xff,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x01,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x83,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xe1,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xef,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf7,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf9,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xfb,0x01,0x00]
+
+v_subrev_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x20]
+
+v_subrev_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x40]
+
+v_subrev_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x60]
+
+v_subrev_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x08]
+
+v_subrev_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x10]
+
+v_subrev_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x18]
+
+v_mul_legacy_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x20]
+
+v_mul_legacy_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x40]
+
+v_mul_legacy_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x60]
+
+v_mul_legacy_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x08]
+
+v_mul_legacy_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x10]
+
+v_mul_legacy_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x18]
+
+v_mul_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x20]
+
+v_mul_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x40]
+
+v_mul_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x60]
+
+v_mul_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x08]
+
+v_mul_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x10]
+
+v_mul_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x18]
+
+v_mul_i32_i24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_i32_i24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x07,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_u32_u24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x09,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x6c,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x6d,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x6e,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x6f,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xf0,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xf7,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd9,0x00,0x00]
+
+v_min_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xdb,0x00,0x00]
+
+v_min_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xdd,0x00,0x00]
+
+v_min_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xdf,0x00,0x00]
+
+v_min_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xe1,0x01,0x00]
+
+v_min_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xef,0x01,0x00]
+
+v_min_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x20]
+
+v_min_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x40]
+
+v_min_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x60]
+
+v_min_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x08]
+
+v_min_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x10]
+
+v_min_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x18]
+
+v_max_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x6c,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x6d,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x6e,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x6f,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xf0,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xf7,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd9,0x00,0x00]
+
+v_max_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xdb,0x00,0x00]
+
+v_max_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xdd,0x00,0x00]
+
+v_max_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xdf,0x00,0x00]
+
+v_max_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xe1,0x01,0x00]
+
+v_max_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xef,0x01,0x00]
+
+v_max_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x20]
+
+v_max_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x40]
+
+v_max_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x60]
+
+v_max_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x08]
+
+v_max_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x10]
+
+v_max_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x18]
+
+v_min_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x6c,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x6d,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x6e,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x6f,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xf0,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xf7,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_i32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_i32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd9,0x00,0x00]
+
+v_min_i32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xdb,0x00,0x00]
+
+v_min_i32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xdd,0x00,0x00]
+
+v_min_i32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xdf,0x00,0x00]
+
+v_min_i32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xe1,0x01,0x00]
+
+v_min_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xef,0x01,0x00]
+
+v_min_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x6c,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x6d,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x6e,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x6f,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xf0,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xf7,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_i32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_i32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd9,0x00,0x00]
+
+v_max_i32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xdb,0x00,0x00]
+
+v_max_i32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xdd,0x00,0x00]
+
+v_max_i32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xdf,0x00,0x00]
+
+v_max_i32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xe1,0x01,0x00]
+
+v_max_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xef,0x01,0x00]
+
+v_max_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x6c,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x6d,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x6e,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x6f,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xf0,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xf7,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_u32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_u32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd9,0x00,0x00]
+
+v_min_u32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xdb,0x00,0x00]
+
+v_min_u32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xdd,0x00,0x00]
+
+v_min_u32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xdf,0x00,0x00]
+
+v_min_u32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xe1,0x01,0x00]
+
+v_min_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xef,0x01,0x00]
+
+v_min_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0f,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x6c,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x6d,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x6e,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x6f,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xf0,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xf7,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_u32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_u32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd9,0x00,0x00]
+
+v_max_u32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xdb,0x00,0x00]
+
+v_max_u32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xdd,0x00,0x00]
+
+v_max_u32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xdf,0x00,0x00]
+
+v_max_u32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xe1,0x01,0x00]
+
+v_max_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xef,0x01,0x00]
+
+v_max_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xfb,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x65,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x66,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x67,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x6c,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x6d,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x6e,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x6f,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x7b,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xf0,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xf7,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xfb,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xfc,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xfd,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xff,0x03,0x00]
+
+v_lshrrev_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x05,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcb,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcd,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcf,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd7,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd9,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xdb,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xdd,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xdf,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf7,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf9,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xff,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xe1,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xef,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf7,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf9,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xfb,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x11,0xd1,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x65,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x66,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x67,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x6c,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x6d,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x6e,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x6f,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x7b,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xf0,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xf7,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xfb,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xfc,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xfd,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xff,0x03,0x00]
+
+v_ashrrev_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x05,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcb,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcd,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcf,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd7,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd9,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xdb,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xdd,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xdf,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf7,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf9,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xff,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xe1,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xef,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf7,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf9,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xfb,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x12,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x65,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x66,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x67,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x6c,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x6d,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x6e,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x6f,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x7b,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xf0,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xf7,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xfb,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xfc,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xfd,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xff,0x03,0x00]
+
+v_lshlrev_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x05,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcb,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcd,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcf,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd7,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd9,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xdb,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xdd,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xdf,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf7,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf9,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xff,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xe1,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xef,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf7,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf9,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xfb,0x01,0x00]
+
+v_and_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x05,0x02,0x00]
+
+v_and_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x13,0xd1,0x01,0x05,0x02,0x00]
+
+v_and_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xff,0x05,0x02,0x00]
+
+v_and_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x65,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x66,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x67,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x6a,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x6b,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x6c,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x6d,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x6e,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x6f,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x7b,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x7c,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x7e,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x7f,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x80,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xc1,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xf0,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xf7,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xfb,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xfc,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xfd,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xfe,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xff,0x03,0x00]
+
+v_and_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x05,0x00,0x00]
+
+v_and_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcb,0x00,0x00]
+
+v_and_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcd,0x00,0x00]
+
+v_and_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcf,0x00,0x00]
+
+v_and_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd5,0x00,0x00]
+
+v_and_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd7,0x00,0x00]
+
+v_and_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd9,0x00,0x00]
+
+v_and_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xdb,0x00,0x00]
+
+v_and_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xdd,0x00,0x00]
+
+v_and_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xdf,0x00,0x00]
+
+v_and_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf7,0x00,0x00]
+
+v_and_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf9,0x00,0x00]
+
+v_and_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xfd,0x00,0x00]
+
+v_and_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xff,0x00,0x00]
+
+v_and_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x01,0x01,0x00]
+
+v_and_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x83,0x01,0x00]
+
+v_and_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xe1,0x01,0x00]
+
+v_and_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xef,0x01,0x00]
+
+v_and_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf7,0x01,0x00]
+
+v_and_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf9,0x01,0x00]
+
+v_and_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xfb,0x01,0x00]
+
+v_or_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x05,0x02,0x00]
+
+v_or_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x14,0xd1,0x01,0x05,0x02,0x00]
+
+v_or_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xff,0x05,0x02,0x00]
+
+v_or_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x65,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x66,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x67,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x6a,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x6b,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x6c,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x6d,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x6e,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x6f,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x7b,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x7c,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x7e,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x7f,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x80,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xc1,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xf0,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xf7,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xfb,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xfc,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xfd,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xfe,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xff,0x03,0x00]
+
+v_or_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x05,0x00,0x00]
+
+v_or_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcb,0x00,0x00]
+
+v_or_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcd,0x00,0x00]
+
+v_or_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcf,0x00,0x00]
+
+v_or_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd5,0x00,0x00]
+
+v_or_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd7,0x00,0x00]
+
+v_or_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd9,0x00,0x00]
+
+v_or_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xdb,0x00,0x00]
+
+v_or_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xdd,0x00,0x00]
+
+v_or_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xdf,0x00,0x00]
+
+v_or_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf7,0x00,0x00]
+
+v_or_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf9,0x00,0x00]
+
+v_or_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xfd,0x00,0x00]
+
+v_or_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xff,0x00,0x00]
+
+v_or_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x01,0x01,0x00]
+
+v_or_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x83,0x01,0x00]
+
+v_or_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xe1,0x01,0x00]
+
+v_or_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xef,0x01,0x00]
+
+v_or_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf7,0x01,0x00]
+
+v_or_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf9,0x01,0x00]
+
+v_or_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xfb,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x05,0x02,0x00]
+
+v_xor_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x15,0xd1,0x01,0x05,0x02,0x00]
+
+v_xor_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xff,0x05,0x02,0x00]
+
+v_xor_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x65,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x66,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x67,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x6a,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x6b,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x6c,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x6d,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x6e,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x6f,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x7b,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x7c,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x7e,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x7f,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x80,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xc1,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xf0,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xf7,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xfb,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xfc,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xfd,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xfe,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xff,0x03,0x00]
+
+v_xor_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x05,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcb,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcd,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcf,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd5,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd7,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd9,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xdb,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xdd,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xdf,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf7,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf9,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xfd,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xff,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x01,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x83,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xe1,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xef,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf7,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf9,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xff,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x65,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x66,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x67,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x80,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xff,0x03,0x00]
+
+v_mac_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xff,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x01,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x83,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xef,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mac_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x20]
+
+v_mac_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x40]
+
+v_mac_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x60]
+
+v_mac_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x08]
+
+v_mac_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x10]
+
+v_mac_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x18]
+
+v_add_u32_e64 v5, s[12:13], v1, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v255, s[12:13], v1, v2
+// CHECK: [0xff,0x0c,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, s[14:15], v1, v2
+// CHECK: [0x05,0x0e,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, s[100:101], v1, v2
+// CHECK: [0x05,0x64,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, flat_scratch, v1, v2
+// CHECK: [0x05,0x66,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, vcc, v1, v2
+// CHECK: [0x05,0x6a,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, tba, v1, v2
+// CHECK: [0x05,0x6c,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, tma, v1, v2
+// CHECK: [0x05,0x6e,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, ttmp[10:11], v1, v2
+// CHECK: [0x05,0x7a,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], v255, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xff,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], s1, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], s101, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x65,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], flat_scratch_lo, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x66,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], flat_scratch_hi, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x67,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], vcc_lo, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x6a,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], vcc_hi, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x6b,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], tba_lo, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x6c,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], tba_hi, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x6d,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], tma_lo, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x6e,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], tma_hi, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x6f,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], ttmp11, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x7b,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], m0, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x7c,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], exec_lo, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x7e,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], exec_hi, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x7f,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], 0, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x80,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], -1, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xc1,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], 0.5, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xf0,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], -4.0, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xf7,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], src_vccz, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xfb,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], src_execz, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xfc,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], src_scc, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xfd,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], src_lds_direct, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xfe,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, v255
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xff,0x03,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, s2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x05,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, s101
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcb,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, flat_scratch_lo
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcd,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, flat_scratch_hi
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcf,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, vcc_lo
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd5,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, vcc_hi
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd7,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, tba_lo
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd9,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, tba_hi
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xdb,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, tma_lo
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xdd,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, tma_hi
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xdf,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, ttmp11
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf7,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, m0
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf9,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, exec_lo
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xfd,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, exec_hi
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xff,0x00,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, 0
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x01,0x01,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, -1
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x83,0x01,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, 0.5
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xe1,0x01,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, -4.0
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xef,0x01,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, src_vccz
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf7,0x01,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, src_execz
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf9,0x01,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, src_scc
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xfb,0x01,0x00]
+
+v_add_u32_e64 v5, s[12:13], v1, v2 clamp
+// CHECK: [0x05,0x8c,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v255, s[12:13], v1, v2
+// CHECK: [0xff,0x0c,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, s[14:15], v1, v2
+// CHECK: [0x05,0x0e,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, s[100:101], v1, v2
+// CHECK: [0x05,0x64,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, flat_scratch, v1, v2
+// CHECK: [0x05,0x66,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, vcc, v1, v2
+// CHECK: [0x05,0x6a,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, tba, v1, v2
+// CHECK: [0x05,0x6c,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, tma, v1, v2
+// CHECK: [0x05,0x6e,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, ttmp[10:11], v1, v2
+// CHECK: [0x05,0x7a,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v255, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xff,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], s1, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], s101, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x65,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], flat_scratch_lo, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x66,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], flat_scratch_hi, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x67,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], vcc_lo, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], vcc_hi, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x6b,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], tba_lo, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x6c,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], tba_hi, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x6d,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], tma_lo, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x6e,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], tma_hi, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x6f,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], ttmp11, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x7b,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], m0, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x7c,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], exec_lo, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], exec_hi, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x7f,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], 0, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x80,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], -1, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], 0.5, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xf0,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], -4.0, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xf7,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], src_vccz, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], src_execz, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], src_scc, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], src_lds_direct, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xfe,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, v255
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xff,0x03,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, s2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x05,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, s101
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcb,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, flat_scratch_lo
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcd,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, flat_scratch_hi
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcf,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, vcc_lo
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, vcc_hi
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd7,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, tba_lo
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd9,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, tba_hi
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xdb,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, tma_lo
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xdd,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, tma_hi
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xdf,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, ttmp11
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf7,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, m0
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf9,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, exec_lo
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, exec_hi
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xff,0x00,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, 0
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x01,0x01,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, -1
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x83,0x01,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, 0.5
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xe1,0x01,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, -4.0
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xef,0x01,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, src_vccz
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, src_execz
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, src_scc
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_sub_u32_e64 v5, s[12:13], v1, v2 clamp
+// CHECK: [0x05,0x8c,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v255, s[12:13], v1, v2
+// CHECK: [0xff,0x0c,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[14:15], v1, v2
+// CHECK: [0x05,0x0e,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[100:101], v1, v2
+// CHECK: [0x05,0x64,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, flat_scratch, v1, v2
+// CHECK: [0x05,0x66,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, vcc, v1, v2
+// CHECK: [0x05,0x6a,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, tba, v1, v2
+// CHECK: [0x05,0x6c,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, tma, v1, v2
+// CHECK: [0x05,0x6e,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, ttmp[10:11], v1, v2
+// CHECK: [0x05,0x7a,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v255, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xff,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], s1, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], s101, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x65,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], flat_scratch_lo, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x66,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], flat_scratch_hi, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x67,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], vcc_lo, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x6a,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], vcc_hi, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x6b,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], tba_lo, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x6c,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], tba_hi, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x6d,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], tma_lo, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x6e,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], tma_hi, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x6f,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], ttmp11, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x7b,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], m0, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x7c,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], exec_lo, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x7e,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], exec_hi, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x7f,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], 0, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x80,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], -1, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xc1,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], 0.5, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xf0,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], -4.0, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xf7,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], src_vccz, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xfb,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], src_execz, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xfc,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], src_scc, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xfd,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, v255
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xff,0x03,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, s2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x05,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, s101
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcb,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, flat_scratch_lo
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcd,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, flat_scratch_hi
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcf,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, vcc_lo
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd5,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, vcc_hi
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd7,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, tba_lo
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd9,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, tba_hi
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xdb,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, tma_lo
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xdd,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, tma_hi
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xdf,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, ttmp11
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf7,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, m0
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf9,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, exec_lo
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xfd,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, exec_hi
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xff,0x00,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, 0
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x01,0x01,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, -1
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x83,0x01,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, 0.5
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xe1,0x01,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, -4.0
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xef,0x01,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, src_vccz
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf7,0x01,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, src_execz
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf9,0x01,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, src_scc
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xfb,0x01,0x00]
+
+v_subrev_u32_e64 v5, s[12:13], v1, v2 clamp
+// CHECK: [0x05,0x8c,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// CHECK: [0xff,0x0c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x0e,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[100:101], v1, v2, s[6:7]
+// CHECK: [0x05,0x64,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
+// CHECK: [0x05,0x66,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, vcc, v1, v2, s[6:7]
+// CHECK: [0x05,0x6a,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, tba, v1, v2, s[6:7]
+// CHECK: [0x05,0x6c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, tma, v1, v2, s[6:7]
+// CHECK: [0x05,0x6e,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
+// CHECK: [0x05,0x7a,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xff,0x05,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x80,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xc1,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xf0,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xf7,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], src_lds_direct, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xfe,0x04,0x1a,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xff,0x1b,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x01,0x19,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x83,0x19,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xe1,0x19,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xef,0x19,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x22,0x00]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x92,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x9a,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xaa,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xb2,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xba,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xea,0x01]
+
+v_addc_u32_e64 v5, s[12:13], v1, v2, s[6:7] clamp
+// CHECK: [0x05,0x8c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// CHECK: [0xff,0x0c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x0e,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[100:101], v1, v2, s[6:7]
+// CHECK: [0x05,0x64,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
+// CHECK: [0x05,0x66,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, vcc, v1, v2, s[6:7]
+// CHECK: [0x05,0x6a,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, tba, v1, v2, s[6:7]
+// CHECK: [0x05,0x6c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, tma, v1, v2, s[6:7]
+// CHECK: [0x05,0x6e,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
+// CHECK: [0x05,0x7a,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xff,0x05,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x80,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xc1,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xf0,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xf7,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], src_lds_direct, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xfe,0x04,0x1a,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xff,0x1b,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x01,0x19,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x83,0x19,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xe1,0x19,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xef,0x19,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x22,0x00]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x92,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x9a,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xaa,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xb2,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xba,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xea,0x01]
+
+v_subb_u32_e64 v5, s[12:13], v1, v2, s[6:7] clamp
+// CHECK: [0x05,0x8c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// CHECK: [0xff,0x0c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x0e,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[100:101], v1, v2, s[6:7]
+// CHECK: [0x05,0x64,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
+// CHECK: [0x05,0x66,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, vcc, v1, v2, s[6:7]
+// CHECK: [0x05,0x6a,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, tba, v1, v2, s[6:7]
+// CHECK: [0x05,0x6c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, tma, v1, v2, s[6:7]
+// CHECK: [0x05,0x6e,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, ttmp[10:11], v1, v2, s[6:7]
+// CHECK: [0x05,0x7a,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0xff,0x05,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x80,0x04,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0xc1,0x04,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0xf0,0x04,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0xf7,0x04,0x1a,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xff,0x1b,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x01,0x19,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x83,0x19,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xe1,0x19,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xef,0x19,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x22,0x00]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x92,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x9a,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xaa,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xb2,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xba,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xea,0x01]
+
+v_subbrev_u32_e64 v5, s[12:13], v1, v2, s[6:7] clamp
+// CHECK: [0x05,0x8c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_add_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xff,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x65,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x66,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x67,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x6a,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x6b,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x6c,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x6d,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x6e,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x6f,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x7b,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x7c,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x7e,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x7f,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x80,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xc1,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xf0,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xf7,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xfb,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xfc,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xfd,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xfe,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xff,0x03,0x00]
+
+v_add_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x00,0x00]
+
+v_add_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcb,0x00,0x00]
+
+v_add_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcd,0x00,0x00]
+
+v_add_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcf,0x00,0x00]
+
+v_add_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd5,0x00,0x00]
+
+v_add_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd7,0x00,0x00]
+
+v_add_f16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd9,0x00,0x00]
+
+v_add_f16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xdb,0x00,0x00]
+
+v_add_f16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xdd,0x00,0x00]
+
+v_add_f16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xdf,0x00,0x00]
+
+v_add_f16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf7,0x00,0x00]
+
+v_add_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf9,0x00,0x00]
+
+v_add_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xfd,0x00,0x00]
+
+v_add_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xff,0x00,0x00]
+
+v_add_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x01,0x01,0x00]
+
+v_add_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x83,0x01,0x00]
+
+v_add_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xe1,0x01,0x00]
+
+v_add_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xef,0x01,0x00]
+
+v_add_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf7,0x01,0x00]
+
+v_add_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf9,0x01,0x00]
+
+v_add_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xfb,0x01,0x00]
+
+v_add_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x20]
+
+v_add_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x40]
+
+v_add_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x60]
+
+v_add_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xff,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x65,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x66,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x67,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x6a,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x6b,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x6c,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x6d,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x6e,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x6f,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x7b,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x7c,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x7e,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x7f,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x80,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xc1,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xf0,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xf7,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xfb,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xfc,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xfd,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xfe,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xff,0x03,0x00]
+
+v_sub_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcb,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcd,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcf,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd5,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd7,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd9,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xdb,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xdd,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xdf,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf7,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf9,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xfd,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xff,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x01,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x83,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xe1,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xef,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf7,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf9,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xfb,0x01,0x00]
+
+v_sub_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x20]
+
+v_sub_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x40]
+
+v_sub_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x60]
+
+v_sub_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xff,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x65,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x66,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x67,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x6a,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x6b,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x6c,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x6d,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x6e,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x6f,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x7b,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x7c,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x7e,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x7f,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x80,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xc1,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xf0,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xf7,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xfb,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xfc,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xfd,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xff,0x03,0x00]
+
+v_subrev_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcb,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcd,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcf,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd5,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd7,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd9,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xdb,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xdd,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xdf,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf7,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf9,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xfd,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xff,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x01,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x83,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xe1,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xef,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf7,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf9,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xfb,0x01,0x00]
+
+v_subrev_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x20]
+
+v_subrev_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x40]
+
+v_subrev_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x60]
+
+v_subrev_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x20]
+
+v_mul_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x40]
+
+v_mul_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x60]
+
+v_mul_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xff,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x65,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x66,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x67,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x80,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xff,0x03,0x00]
+
+v_mac_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xff,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x01,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x83,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xef,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mac_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x20]
+
+v_mac_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x40]
+
+v_mac_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x60]
+
+v_mac_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xff,0x05,0x02,0x00]
+
+v_add_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x65,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x66,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x67,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x6a,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x6b,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x6c,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x6d,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x6e,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x6f,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x7b,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x7c,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x7e,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x7f,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x80,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xc1,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xfb,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xfc,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xfd,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xfe,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xff,0x03,0x00]
+
+v_add_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x05,0x00,0x00]
+
+v_add_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcb,0x00,0x00]
+
+v_add_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcd,0x00,0x00]
+
+v_add_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcf,0x00,0x00]
+
+v_add_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd5,0x00,0x00]
+
+v_add_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd7,0x00,0x00]
+
+v_add_u16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd9,0x00,0x00]
+
+v_add_u16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xdb,0x00,0x00]
+
+v_add_u16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xdd,0x00,0x00]
+
+v_add_u16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xdf,0x00,0x00]
+
+v_add_u16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf7,0x00,0x00]
+
+v_add_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf9,0x00,0x00]
+
+v_add_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xfd,0x00,0x00]
+
+v_add_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xff,0x00,0x00]
+
+v_add_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x01,0x01,0x00]
+
+v_add_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x83,0x01,0x00]
+
+v_add_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf7,0x01,0x00]
+
+v_add_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf9,0x01,0x00]
+
+v_add_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xfb,0x01,0x00]
+
+v_add_u16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x27,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xff,0x05,0x02,0x00]
+
+v_sub_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x65,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x66,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x67,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x6a,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x6b,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x6c,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x6d,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x6e,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x6f,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x7b,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x7c,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x7e,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x7f,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x80,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xc1,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xfb,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xfc,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xfd,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xfe,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x03,0x00]
+
+v_sub_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x05,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcb,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcd,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcf,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd5,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd7,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd9,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xdb,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xdd,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xdf,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf7,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf9,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xfd,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x01,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x83,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf7,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf9,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xfb,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x27,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xff,0x05,0x02,0x00]
+
+v_subrev_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x65,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x66,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x67,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x6a,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x6b,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x6c,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x6d,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x6e,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x6f,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x7b,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x7c,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x7e,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x7f,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x80,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xc1,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xfb,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xfc,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xfd,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x03,0x00]
+
+v_subrev_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x05,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcb,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcd,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcf,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd5,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd7,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd9,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xdb,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xdd,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xdf,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf7,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf9,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xfd,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x01,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x83,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf7,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf9,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xfb,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x29,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x6c,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x6d,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x6e,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x6f,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_lo_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd9,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xdb,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xdd,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xdf,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_lo_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_lo_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_lo_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_lo_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xfb,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x65,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x66,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x67,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x6c,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x6d,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x6e,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x6f,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x7b,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x03,0x00]
+
+v_lshlrev_b16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x05,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcb,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcd,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcf,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd7,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd9,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xdb,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xdd,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xdf,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf7,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf9,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2b,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x65,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x66,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x67,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x6c,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x6d,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x6e,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x6f,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x7b,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xfb,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xfc,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xfd,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x03,0x00]
+
+v_lshrrev_b16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x05,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcb,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcd,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcf,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd7,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd9,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xdb,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xdd,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xdf,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf7,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf9,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf7,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf9,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xfb,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x65,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x66,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x67,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x6c,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x6d,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x6e,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x6f,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x7b,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xfb,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xfc,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xfd,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x03,0x00]
+
+v_ashrrev_i16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x05,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcb,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcd,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcf,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd7,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd9,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xdb,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xdd,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xdf,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf7,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf9,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf7,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf9,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x6c,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x6d,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x6e,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x6f,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xf0,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xf7,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_f16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd9,0x00,0x00]
+
+v_max_f16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xdb,0x00,0x00]
+
+v_max_f16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xdd,0x00,0x00]
+
+v_max_f16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xdf,0x00,0x00]
+
+v_max_f16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xe1,0x01,0x00]
+
+v_max_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xef,0x01,0x00]
+
+v_max_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x20]
+
+v_max_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x40]
+
+v_max_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x60]
+
+v_max_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x6c,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x6d,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x6e,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x6f,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xf0,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xf7,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_f16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd9,0x00,0x00]
+
+v_min_f16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xdb,0x00,0x00]
+
+v_min_f16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xdd,0x00,0x00]
+
+v_min_f16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xdf,0x00,0x00]
+
+v_min_f16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xe1,0x01,0x00]
+
+v_min_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xef,0x01,0x00]
+
+v_min_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x20]
+
+v_min_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x40]
+
+v_min_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x60]
+
+v_min_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2f,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x6c,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x6d,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x6e,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x6f,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_u16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd9,0x00,0x00]
+
+v_max_u16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xdb,0x00,0x00]
+
+v_max_u16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xdd,0x00,0x00]
+
+v_max_u16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xdf,0x00,0x00]
+
+v_max_u16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_i16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_i16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_i16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_i16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x6c,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x6d,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x6e,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x6f,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_i16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_i16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_i16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_i16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_i16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_i16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_i16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd9,0x00,0x00]
+
+v_max_i16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xdb,0x00,0x00]
+
+v_max_i16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xdd,0x00,0x00]
+
+v_max_i16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xdf,0x00,0x00]
+
+v_max_i16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_i16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_i16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_i16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_i16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_i16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_i16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_i16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_i16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x31,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x6c,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x6d,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x6e,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x6f,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_u16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd9,0x00,0x00]
+
+v_min_u16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xdb,0x00,0x00]
+
+v_min_u16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xdd,0x00,0x00]
+
+v_min_u16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xdf,0x00,0x00]
+
+v_min_u16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_i16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_i16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x32,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_i16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_i16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x6c,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x6d,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x6e,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x6f,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_i16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_i16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_i16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_i16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_i16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_i16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_i16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd9,0x00,0x00]
+
+v_min_i16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xdb,0x00,0x00]
+
+v_min_i16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xdd,0x00,0x00]
+
+v_min_i16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xdf,0x00,0x00]
+
+v_min_i16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_i16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_i16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_i16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_i16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_i16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_i16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_i16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_i16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x33,0xd1,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xff,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x65,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x66,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x67,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x6b,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x6c,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x6d,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x6e,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x6f,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x7b,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x7c,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x7f,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x80,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xfb,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xfc,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xfd,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xfe,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xff,0x03,0x00]
+
+v_ldexp_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcb,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcd,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd9,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xdb,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xdd,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xdf,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf7,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xff,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x01,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x83,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xef,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf7,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf9,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x02,0x20]
+
+v_ldexp_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x33,0xd1,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x33,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_class_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_class_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[12:13], v[1:2], v2
+// CHECK: [0x0c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[100:101], v[1:2], v2
+// CHECK: [0x64,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 flat_scratch, v[1:2], v2
+// CHECK: [0x66,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 vcc, v[1:2], v2
+// CHECK: [0x6a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 tba, v[1:2], v2
+// CHECK: [0x6c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 tma, v[1:2], v2
+// CHECK: [0x6e,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 ttmp[10:11], v[1:2], v2
+// CHECK: [0x7a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[254:255], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], s[2:3], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], s[4:5], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], s[100:101], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], flat_scratch, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], vcc, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], tba, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], tma, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], ttmp[10:11], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], exec, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v255
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s101
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], tba_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], tba_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], tma_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], tma_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], ttmp11
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], m0
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], exec_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], exec_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], -v[1:2], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_class_f64_e64 s[10:11], |v[1:2]|, v2
+// CHECK: [0x0a,0x01,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[12:13], v[1:2], v2
+// CHECK: [0x0c,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[100:101], v[1:2], v2
+// CHECK: [0x64,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 flat_scratch, v[1:2], v2
+// CHECK: [0x66,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 vcc, v[1:2], v2
+// CHECK: [0x6a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 tba, v[1:2], v2
+// CHECK: [0x6c,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 tma, v[1:2], v2
+// CHECK: [0x6e,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 ttmp[10:11], v[1:2], v2
+// CHECK: [0x7a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[254:255], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], s[2:3], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], s[4:5], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], s[100:101], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], flat_scratch, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], vcc, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], tba, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], tma, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], ttmp[10:11], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], exec, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], v255
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], s2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], s101
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_lo
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_hi
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], tba_lo
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], tba_hi
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], tma_lo
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], tma_hi
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], ttmp11
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], m0
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_lo
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_hi
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], -v[1:2], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_class_f64_e64 s[10:11], |v[1:2]|, v2
+// CHECK: [0x0a,0x01,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_class_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_class_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_f_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_f_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_f_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_eq_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_eq_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_eq_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_le_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_le_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_le_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_gt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_gt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_gt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lg_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lg_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lg_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ge_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ge_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ge_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_o_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_o_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_o_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_u_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_u_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_u_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nge_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nge_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nge_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlg_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlg_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ngt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ngt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nle_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nle_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nle_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_neq_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_neq_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_neq_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_tru_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_tru_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_tru_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_f_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_f_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_f_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_eq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_eq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_eq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_le_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_le_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_le_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_gt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_gt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_gt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_o_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_o_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_o_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_u_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_u_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_u_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ngt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ngt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nle_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nle_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nle_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_neq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_neq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_neq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_tru_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_tru_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_tru_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_f_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_eq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_le_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_gt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_o_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_u_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ngt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nle_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_neq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_tru_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 tba, v1, v2
+// CHECK: [0x6c,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 tma, v1, v2
+// CHECK: [0x6e,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 ttmp[10:11], v1, v2
+// CHECK: [0x7a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], tba_lo, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], tba_hi, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x6d,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], tma_lo, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], tma_hi, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x6f,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], ttmp11, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, tba_lo
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, tba_hi
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xdb,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, tma_lo
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, tma_hi
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xdf,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, ttmp11
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 tba, v[1:2], v[2:3]
+// CHECK: [0x6c,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 tma, v[1:2], v[2:3]
+// CHECK: [0x6e,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 ttmp[10:11], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], tba, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x6c,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], tma, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x6e,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], ttmp[10:11], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], tba
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xd9,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], tma
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xdd,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], ttmp[10:11]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfb,0x01,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s b/llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s
new file mode 100644
index 0000000000000..8cee668043dbf
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vop3_e64.s
@@ -0,0 +1,13501 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+v_mad_legacy_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_legacy_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_legacy_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_legacy_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xb6,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xba,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xbe,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_legacy_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_legacy_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x24]
+
+v_mad_legacy_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_legacy_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x84]
+
+v_mad_legacy_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_mad_legacy_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_mad_legacy_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x14]
+
+v_mad_legacy_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_mad_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mad_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_mad_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mad_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_mad_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mad_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mad_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mad_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mad_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mad_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xb6,0x01]
+
+v_mad_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xba,0x01]
+
+v_mad_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xbe,0x01]
+
+v_mad_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x24]
+
+v_mad_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x84]
+
+v_mad_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_mad_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_mad_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x14]
+
+v_mad_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_mad_i32_i24 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_i32_i24 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_i32_i24 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_i32_i24 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_i32_i24 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_i32_i24 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_i32_i24 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_i32_i24 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_i32_i24 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mad_i32_i24 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xb6,0x01]
+
+v_mad_i32_i24 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xba,0x01]
+
+v_mad_i32_i24 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xbe,0x01]
+
+v_mad_i32_i24 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_i32_i24 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_i32_i24 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_i32_i24 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_i32_i24 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_i32_i24 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_i32_i24 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_i32_i24 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_i32_i24 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_i32_i24 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_i32_i24 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_i32_i24 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_u32_u24 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_u32_u24 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_u32_u24 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_u32_u24 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_u32_u24 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_u32_u24 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_u32_u24 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_u32_u24 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mad_u32_u24 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xb6,0x01]
+
+v_mad_u32_u24 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xba,0x01]
+
+v_mad_u32_u24 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xbe,0x01]
+
+v_mad_u32_u24 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_u32_u24 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_u32_u24 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_u32_u24 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_u32_u24 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_u32_u24 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_u32_u24 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_u32_u24 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_u32_u24 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_u32_u24 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_u32_u24 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_u32_u24 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cubeid_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cubeid_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cubeid_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x96,0x01]
+
+v_cubeid_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cubeid_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cubeid_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cubeid_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xae,0x01]
+
+v_cubeid_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xb2,0x01]
+
+v_cubeid_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xb6,0x01]
+
+v_cubeid_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xba,0x01]
+
+v_cubeid_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xbe,0x01]
+
+v_cubeid_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xee,0x01]
+
+v_cubeid_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cubeid_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cubeid_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cubeid_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x02,0x02]
+
+v_cubeid_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x06,0x03]
+
+v_cubeid_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cubeid_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xde,0x03]
+
+v_cubeid_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xee,0x03]
+
+v_cubeid_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cubeid_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cubeid_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cubeid_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x44]
+
+v_cubeid_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x84]
+
+v_cubeid_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_cubeid_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_cubeid_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x14]
+
+v_cubeid_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_cubesc_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cubesc_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cubesc_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cubesc_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x96,0x01]
+
+v_cubesc_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cubesc_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cubesc_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cubesc_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xae,0x01]
+
+v_cubesc_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xb2,0x01]
+
+v_cubesc_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xb6,0x01]
+
+v_cubesc_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xba,0x01]
+
+v_cubesc_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xbe,0x01]
+
+v_cubesc_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xee,0x01]
+
+v_cubesc_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cubesc_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cubesc_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cubesc_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x02,0x02]
+
+v_cubesc_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x06,0x03]
+
+v_cubesc_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cubesc_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xde,0x03]
+
+v_cubesc_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xee,0x03]
+
+v_cubesc_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cubesc_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cubesc_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cubesc_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x44]
+
+v_cubesc_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x84]
+
+v_cubesc_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_cubesc_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_cubesc_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x14]
+
+v_cubesc_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_cubetc_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cubetc_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cubetc_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cubetc_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x96,0x01]
+
+v_cubetc_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cubetc_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cubetc_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cubetc_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xae,0x01]
+
+v_cubetc_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xb2,0x01]
+
+v_cubetc_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xb6,0x01]
+
+v_cubetc_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xba,0x01]
+
+v_cubetc_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xbe,0x01]
+
+v_cubetc_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xee,0x01]
+
+v_cubetc_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cubetc_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cubetc_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cubetc_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x02,0x02]
+
+v_cubetc_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x06,0x03]
+
+v_cubetc_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cubetc_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xde,0x03]
+
+v_cubetc_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xee,0x03]
+
+v_cubetc_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cubetc_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cubetc_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cubetc_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x44]
+
+v_cubetc_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x84]
+
+v_cubetc_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_cubetc_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_cubetc_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x14]
+
+v_cubetc_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_cubema_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cubema_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cubema_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cubema_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cubema_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cubema_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cubema_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cubema_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_cubema_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_cubema_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_cubema_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_cubema_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cubema_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cubema_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cubema_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cubema_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cubema_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cubema_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cubema_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cubema_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cubema_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cubema_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cubema_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cubema_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cubema_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x96,0x01]
+
+v_cubema_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cubema_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cubema_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cubema_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xae,0x01]
+
+v_cubema_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xb2,0x01]
+
+v_cubema_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xb6,0x01]
+
+v_cubema_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xba,0x01]
+
+v_cubema_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xbe,0x01]
+
+v_cubema_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xee,0x01]
+
+v_cubema_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cubema_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cubema_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cubema_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x02,0x02]
+
+v_cubema_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x06,0x03]
+
+v_cubema_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cubema_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xde,0x03]
+
+v_cubema_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xee,0x03]
+
+v_cubema_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cubema_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cubema_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cubema_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x44]
+
+v_cubema_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x84]
+
+v_cubema_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_cubema_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_cubema_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x14]
+
+v_cubema_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_bfe_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfe_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfe_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xff,0x05,0x0e,0x04]
+
+v_bfe_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x65,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x66,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x67,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x80,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xff,0x0f,0x04]
+
+v_bfe_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0c,0x04]
+
+v_bfe_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_bfe_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_bfe_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_bfe_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_bfe_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_bfe_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_bfe_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_bfe_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_bfe_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_bfe_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_bfe_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_bfe_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_bfe_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xff,0x0c,0x04]
+
+v_bfe_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x01,0x0d,0x04]
+
+v_bfe_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x83,0x0d,0x04]
+
+v_bfe_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_bfe_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xef,0x0d,0x04]
+
+v_bfe_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_bfe_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_bfe_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_bfe_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfe,0x07]
+
+v_bfe_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x00]
+
+v_bfe_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x96,0x01]
+
+v_bfe_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x9a,0x01]
+
+v_bfe_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x9e,0x01]
+
+v_bfe_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xaa,0x01]
+
+v_bfe_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xae,0x01]
+
+v_bfe_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xb2,0x01]
+
+v_bfe_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xb6,0x01]
+
+v_bfe_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xba,0x01]
+
+v_bfe_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xbe,0x01]
+
+v_bfe_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xee,0x01]
+
+v_bfe_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xf2,0x01]
+
+v_bfe_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfa,0x01]
+
+v_bfe_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfe,0x01]
+
+v_bfe_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x02,0x02]
+
+v_bfe_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x06,0x03]
+
+v_bfe_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xc2,0x03]
+
+v_bfe_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xde,0x03]
+
+v_bfe_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xee,0x03]
+
+v_bfe_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xf2,0x03]
+
+v_bfe_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xf6,0x03]
+
+v_bfe_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfe_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfe_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xff,0x05,0x0e,0x04]
+
+v_bfe_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x65,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x66,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x67,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x80,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xff,0x0f,0x04]
+
+v_bfe_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0c,0x04]
+
+v_bfe_i32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_bfe_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_bfe_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_bfe_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_bfe_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_bfe_i32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_bfe_i32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_bfe_i32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_bfe_i32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_bfe_i32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_bfe_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_bfe_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_bfe_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xff,0x0c,0x04]
+
+v_bfe_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x01,0x0d,0x04]
+
+v_bfe_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x83,0x0d,0x04]
+
+v_bfe_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_bfe_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xef,0x0d,0x04]
+
+v_bfe_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_bfe_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_bfe_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_bfe_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfe,0x07]
+
+v_bfe_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x00]
+
+v_bfe_i32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x96,0x01]
+
+v_bfe_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x9a,0x01]
+
+v_bfe_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x9e,0x01]
+
+v_bfe_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xaa,0x01]
+
+v_bfe_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xae,0x01]
+
+v_bfe_i32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xb2,0x01]
+
+v_bfe_i32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xb6,0x01]
+
+v_bfe_i32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xba,0x01]
+
+v_bfe_i32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xbe,0x01]
+
+v_bfe_i32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xee,0x01]
+
+v_bfe_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xf2,0x01]
+
+v_bfe_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfa,0x01]
+
+v_bfe_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfe,0x01]
+
+v_bfe_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x02,0x02]
+
+v_bfe_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x06,0x03]
+
+v_bfe_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xc2,0x03]
+
+v_bfe_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xde,0x03]
+
+v_bfe_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xee,0x03]
+
+v_bfe_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xf2,0x03]
+
+v_bfe_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xf6,0x03]
+
+v_bfi_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfi_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xca,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfi_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xff,0x05,0x0e,0x04]
+
+v_bfi_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x65,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x66,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x67,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x80,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xff,0x0f,0x04]
+
+v_bfi_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0c,0x04]
+
+v_bfi_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_bfi_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_bfi_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_bfi_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_bfi_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_bfi_b32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_bfi_b32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_bfi_b32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_bfi_b32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_bfi_b32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_bfi_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_bfi_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_bfi_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xff,0x0c,0x04]
+
+v_bfi_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x01,0x0d,0x04]
+
+v_bfi_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x83,0x0d,0x04]
+
+v_bfi_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_bfi_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xef,0x0d,0x04]
+
+v_bfi_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_bfi_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_bfi_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_bfi_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfe,0x07]
+
+v_bfi_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0e,0x00]
+
+v_bfi_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x96,0x01]
+
+v_bfi_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x9a,0x01]
+
+v_bfi_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x9e,0x01]
+
+v_bfi_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xaa,0x01]
+
+v_bfi_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xae,0x01]
+
+v_bfi_b32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xb2,0x01]
+
+v_bfi_b32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xb6,0x01]
+
+v_bfi_b32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xba,0x01]
+
+v_bfi_b32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xbe,0x01]
+
+v_bfi_b32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xee,0x01]
+
+v_bfi_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xf2,0x01]
+
+v_bfi_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfa,0x01]
+
+v_bfi_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfe,0x01]
+
+v_bfi_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x02,0x02]
+
+v_bfi_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x06,0x03]
+
+v_bfi_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xc2,0x03]
+
+v_bfi_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xde,0x03]
+
+v_bfi_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xee,0x03]
+
+v_bfi_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xf2,0x03]
+
+v_bfi_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xff,0x05,0x0e,0x04]
+
+v_fma_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x04,0x0e,0x04]
+
+v_fma_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x65,0x04,0x0e,0x04]
+
+v_fma_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x66,0x04,0x0e,0x04]
+
+v_fma_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x67,0x04,0x0e,0x04]
+
+v_fma_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_fma_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_fma_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_fma_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_fma_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_fma_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_fma_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_fma_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_fma_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_fma_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_fma_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x80,0x04,0x0e,0x04]
+
+v_fma_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_fma_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_fma_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_fma_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xff,0x0f,0x04]
+
+v_fma_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0c,0x04]
+
+v_fma_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_fma_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_fma_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_fma_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_fma_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_fma_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_fma_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_fma_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_fma_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_fma_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_fma_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_fma_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_fma_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xff,0x0c,0x04]
+
+v_fma_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x01,0x0d,0x04]
+
+v_fma_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x83,0x0d,0x04]
+
+v_fma_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_fma_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xef,0x0d,0x04]
+
+v_fma_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_fma_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_fma_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_fma_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfe,0x07]
+
+v_fma_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x00]
+
+v_fma_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x96,0x01]
+
+v_fma_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x9a,0x01]
+
+v_fma_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x9e,0x01]
+
+v_fma_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xaa,0x01]
+
+v_fma_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xae,0x01]
+
+v_fma_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xb2,0x01]
+
+v_fma_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xb6,0x01]
+
+v_fma_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xba,0x01]
+
+v_fma_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xbe,0x01]
+
+v_fma_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xee,0x01]
+
+v_fma_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xf2,0x01]
+
+v_fma_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfa,0x01]
+
+v_fma_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfe,0x01]
+
+v_fma_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x02,0x02]
+
+v_fma_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x06,0x03]
+
+v_fma_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xc2,0x03]
+
+v_fma_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xde,0x03]
+
+v_fma_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xee,0x03]
+
+v_fma_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xf2,0x03]
+
+v_fma_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x24]
+
+v_fma_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x44]
+
+v_fma_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x84]
+
+v_fma_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_fma_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_fma_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x14]
+
+v_fma_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[2:3], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x02,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[4:5], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x04,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[100:101], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x64,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x66,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], tba, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], tma, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], exec, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x80,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], src_vccz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], src_execz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], src_scc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfd,0x0f,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[4:5], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x09,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[6:7], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x0d,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[100:101], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xc9,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], tba, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], tma, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xf5,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], exec, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x01,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x83,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xef,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xfa,0x07]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[6:7]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x1a,0x00]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[8:9]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x22,0x00]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[100:101]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x92,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], flat_scratch
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x9a,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xaa,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], tba
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xb2,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], tma
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xba,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xea,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], exec
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xfa,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], 0
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x02,0x02]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -1
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x06,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xc2,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xde,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], src_vccz
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xee,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], src_execz
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xf2,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], src_scc
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x24]
+
+v_fma_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x44]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x84]
+
+v_fma_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_fma_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// CHECK: [0x05,0x01,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// CHECK: [0x05,0x02,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// CHECK: [0x05,0x04,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// CHECK: [0x05,0x07,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// CHECK: [0x05,0x80,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x14]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_lerp_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_lerp_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_lerp_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xff,0x05,0x0e,0x04]
+
+v_lerp_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x65,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x66,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x67,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x80,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xff,0x0f,0x04]
+
+v_lerp_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0c,0x04]
+
+v_lerp_u8 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_lerp_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_lerp_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_lerp_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_lerp_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_lerp_u8 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_lerp_u8 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_lerp_u8 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_lerp_u8 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_lerp_u8 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_lerp_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_lerp_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_lerp_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xff,0x0c,0x04]
+
+v_lerp_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x01,0x0d,0x04]
+
+v_lerp_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x83,0x0d,0x04]
+
+v_lerp_u8 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_lerp_u8 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xef,0x0d,0x04]
+
+v_lerp_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_lerp_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_lerp_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_lerp_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfe,0x07]
+
+v_lerp_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x00]
+
+v_lerp_u8 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x96,0x01]
+
+v_lerp_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x9a,0x01]
+
+v_lerp_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x9e,0x01]
+
+v_lerp_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xaa,0x01]
+
+v_lerp_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xae,0x01]
+
+v_lerp_u8 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xb2,0x01]
+
+v_lerp_u8 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xb6,0x01]
+
+v_lerp_u8 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xba,0x01]
+
+v_lerp_u8 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xbe,0x01]
+
+v_lerp_u8 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xee,0x01]
+
+v_lerp_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xf2,0x01]
+
+v_lerp_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfa,0x01]
+
+v_lerp_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfe,0x01]
+
+v_lerp_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x02,0x02]
+
+v_lerp_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x06,0x03]
+
+v_lerp_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xc2,0x03]
+
+v_lerp_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xde,0x03]
+
+v_lerp_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xee,0x03]
+
+v_lerp_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xf2,0x03]
+
+v_lerp_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xf6,0x03]
+
+v_alignbit_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0e,0x04]
+
+v_alignbit_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xce,0xd1,0x01,0x05,0x0e,0x04]
+
+v_alignbit_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xff,0x05,0x0e,0x04]
+
+v_alignbit_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x65,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x66,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x67,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x80,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xff,0x0f,0x04]
+
+v_alignbit_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xff,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x01,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x83,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xef,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x07]
+
+v_alignbit_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0e,0x00]
+
+v_alignbit_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x96,0x01]
+
+v_alignbit_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x9a,0x01]
+
+v_alignbit_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x9e,0x01]
+
+v_alignbit_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xaa,0x01]
+
+v_alignbit_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xae,0x01]
+
+v_alignbit_b32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xb2,0x01]
+
+v_alignbit_b32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xb6,0x01]
+
+v_alignbit_b32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xba,0x01]
+
+v_alignbit_b32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xbe,0x01]
+
+v_alignbit_b32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xee,0x01]
+
+v_alignbit_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xf2,0x01]
+
+v_alignbit_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfa,0x01]
+
+v_alignbit_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x01]
+
+v_alignbit_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x02,0x02]
+
+v_alignbit_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x06,0x03]
+
+v_alignbit_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xc2,0x03]
+
+v_alignbit_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xde,0x03]
+
+v_alignbit_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xee,0x03]
+
+v_alignbit_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xf2,0x03]
+
+v_alignbit_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xf6,0x03]
+
+v_alignbyte_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xff,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x65,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x66,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x67,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x80,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xff,0x0f,0x04]
+
+v_alignbyte_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xff,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x01,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x83,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xef,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x07]
+
+v_alignbyte_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x00]
+
+v_alignbyte_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x96,0x01]
+
+v_alignbyte_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x9a,0x01]
+
+v_alignbyte_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x9e,0x01]
+
+v_alignbyte_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xaa,0x01]
+
+v_alignbyte_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xae,0x01]
+
+v_alignbyte_b32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xb2,0x01]
+
+v_alignbyte_b32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xb6,0x01]
+
+v_alignbyte_b32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xba,0x01]
+
+v_alignbyte_b32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xbe,0x01]
+
+v_alignbyte_b32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xee,0x01]
+
+v_alignbyte_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xf2,0x01]
+
+v_alignbyte_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfa,0x01]
+
+v_alignbyte_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x01]
+
+v_alignbyte_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x02,0x02]
+
+v_alignbyte_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x06,0x03]
+
+v_alignbyte_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xc2,0x03]
+
+v_alignbyte_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xde,0x03]
+
+v_alignbyte_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xee,0x03]
+
+v_alignbyte_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xf2,0x03]
+
+v_alignbyte_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xff,0x05,0x0e,0x04]
+
+v_min3_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x04,0x0e,0x04]
+
+v_min3_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x65,0x04,0x0e,0x04]
+
+v_min3_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x66,0x04,0x0e,0x04]
+
+v_min3_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x67,0x04,0x0e,0x04]
+
+v_min3_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_min3_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_min3_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_min3_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_min3_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_min3_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_min3_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_min3_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_min3_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_min3_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_min3_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x80,0x04,0x0e,0x04]
+
+v_min3_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_min3_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_min3_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_min3_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xff,0x0f,0x04]
+
+v_min3_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0c,0x04]
+
+v_min3_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_min3_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_min3_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_min3_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_min3_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_min3_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_min3_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_min3_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_min3_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_min3_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_min3_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_min3_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_min3_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xff,0x0c,0x04]
+
+v_min3_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x01,0x0d,0x04]
+
+v_min3_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x83,0x0d,0x04]
+
+v_min3_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_min3_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xef,0x0d,0x04]
+
+v_min3_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_min3_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_min3_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_min3_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfe,0x07]
+
+v_min3_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x00]
+
+v_min3_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x96,0x01]
+
+v_min3_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x9a,0x01]
+
+v_min3_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x9e,0x01]
+
+v_min3_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xaa,0x01]
+
+v_min3_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xae,0x01]
+
+v_min3_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xb2,0x01]
+
+v_min3_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xb6,0x01]
+
+v_min3_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xba,0x01]
+
+v_min3_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xbe,0x01]
+
+v_min3_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xee,0x01]
+
+v_min3_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xf2,0x01]
+
+v_min3_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfa,0x01]
+
+v_min3_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfe,0x01]
+
+v_min3_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x02,0x02]
+
+v_min3_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x06,0x03]
+
+v_min3_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xc2,0x03]
+
+v_min3_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xde,0x03]
+
+v_min3_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xee,0x03]
+
+v_min3_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xf2,0x03]
+
+v_min3_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x24]
+
+v_min3_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x44]
+
+v_min3_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x84]
+
+v_min3_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_min3_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_min3_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x14]
+
+v_min3_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_min3_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xff,0x05,0x0e,0x04]
+
+v_min3_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x04,0x0e,0x04]
+
+v_min3_i32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x65,0x04,0x0e,0x04]
+
+v_min3_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x66,0x04,0x0e,0x04]
+
+v_min3_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x67,0x04,0x0e,0x04]
+
+v_min3_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_min3_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_min3_i32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_min3_i32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_min3_i32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_min3_i32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_min3_i32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_min3_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_min3_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_min3_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_min3_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x80,0x04,0x0e,0x04]
+
+v_min3_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_min3_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_min3_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_min3_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xff,0x0f,0x04]
+
+v_min3_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0c,0x04]
+
+v_min3_i32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_min3_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_min3_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_min3_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_min3_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_min3_i32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_min3_i32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_min3_i32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_min3_i32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_min3_i32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_min3_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_min3_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_min3_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xff,0x0c,0x04]
+
+v_min3_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x01,0x0d,0x04]
+
+v_min3_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x83,0x0d,0x04]
+
+v_min3_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_min3_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xef,0x0d,0x04]
+
+v_min3_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_min3_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_min3_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_min3_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfe,0x07]
+
+v_min3_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x00]
+
+v_min3_i32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x96,0x01]
+
+v_min3_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x9a,0x01]
+
+v_min3_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x9e,0x01]
+
+v_min3_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xaa,0x01]
+
+v_min3_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xae,0x01]
+
+v_min3_i32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xb2,0x01]
+
+v_min3_i32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xb6,0x01]
+
+v_min3_i32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xba,0x01]
+
+v_min3_i32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xbe,0x01]
+
+v_min3_i32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xee,0x01]
+
+v_min3_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xf2,0x01]
+
+v_min3_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfa,0x01]
+
+v_min3_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfe,0x01]
+
+v_min3_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x02,0x02]
+
+v_min3_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x06,0x03]
+
+v_min3_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xc2,0x03]
+
+v_min3_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xde,0x03]
+
+v_min3_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xee,0x03]
+
+v_min3_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xf2,0x03]
+
+v_min3_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xff,0x05,0x0e,0x04]
+
+v_min3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x04,0x0e,0x04]
+
+v_min3_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x65,0x04,0x0e,0x04]
+
+v_min3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x66,0x04,0x0e,0x04]
+
+v_min3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x67,0x04,0x0e,0x04]
+
+v_min3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_min3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_min3_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_min3_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_min3_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_min3_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_min3_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_min3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_min3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_min3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_min3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x80,0x04,0x0e,0x04]
+
+v_min3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_min3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_min3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_min3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xff,0x0f,0x04]
+
+v_min3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0c,0x04]
+
+v_min3_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_min3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_min3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_min3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_min3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_min3_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_min3_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_min3_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_min3_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_min3_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_min3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_min3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_min3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xff,0x0c,0x04]
+
+v_min3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x01,0x0d,0x04]
+
+v_min3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x83,0x0d,0x04]
+
+v_min3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_min3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xef,0x0d,0x04]
+
+v_min3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_min3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_min3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_min3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfe,0x07]
+
+v_min3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x00]
+
+v_min3_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x96,0x01]
+
+v_min3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x9a,0x01]
+
+v_min3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x9e,0x01]
+
+v_min3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xaa,0x01]
+
+v_min3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xae,0x01]
+
+v_min3_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xb2,0x01]
+
+v_min3_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xb6,0x01]
+
+v_min3_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xba,0x01]
+
+v_min3_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xbe,0x01]
+
+v_min3_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xee,0x01]
+
+v_min3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xf2,0x01]
+
+v_min3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfa,0x01]
+
+v_min3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfe,0x01]
+
+v_min3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x02,0x02]
+
+v_min3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x06,0x03]
+
+v_min3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xc2,0x03]
+
+v_min3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xde,0x03]
+
+v_min3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xee,0x03]
+
+v_min3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xf2,0x03]
+
+v_min3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xf6,0x03]
+
+v_max3_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xff,0x05,0x0e,0x04]
+
+v_max3_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x04,0x0e,0x04]
+
+v_max3_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x65,0x04,0x0e,0x04]
+
+v_max3_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x66,0x04,0x0e,0x04]
+
+v_max3_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x67,0x04,0x0e,0x04]
+
+v_max3_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_max3_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_max3_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_max3_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_max3_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_max3_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_max3_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_max3_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_max3_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_max3_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_max3_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x80,0x04,0x0e,0x04]
+
+v_max3_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_max3_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_max3_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_max3_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xff,0x0f,0x04]
+
+v_max3_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0c,0x04]
+
+v_max3_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_max3_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_max3_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_max3_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_max3_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_max3_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_max3_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_max3_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_max3_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_max3_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_max3_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_max3_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_max3_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xff,0x0c,0x04]
+
+v_max3_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x01,0x0d,0x04]
+
+v_max3_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x83,0x0d,0x04]
+
+v_max3_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_max3_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xef,0x0d,0x04]
+
+v_max3_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_max3_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_max3_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_max3_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfe,0x07]
+
+v_max3_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x00]
+
+v_max3_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x96,0x01]
+
+v_max3_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x9a,0x01]
+
+v_max3_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x9e,0x01]
+
+v_max3_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xaa,0x01]
+
+v_max3_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xae,0x01]
+
+v_max3_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xb2,0x01]
+
+v_max3_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xb6,0x01]
+
+v_max3_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xba,0x01]
+
+v_max3_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xbe,0x01]
+
+v_max3_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xee,0x01]
+
+v_max3_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xf2,0x01]
+
+v_max3_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfa,0x01]
+
+v_max3_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfe,0x01]
+
+v_max3_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x02,0x02]
+
+v_max3_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x06,0x03]
+
+v_max3_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xc2,0x03]
+
+v_max3_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xde,0x03]
+
+v_max3_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xee,0x03]
+
+v_max3_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xf2,0x03]
+
+v_max3_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xf6,0x03]
+
+v_max3_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x24]
+
+v_max3_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x44]
+
+v_max3_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x84]
+
+v_max3_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_max3_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_max3_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x14]
+
+v_max3_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_max3_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xff,0x05,0x0e,0x04]
+
+v_max3_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x04,0x0e,0x04]
+
+v_max3_i32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x65,0x04,0x0e,0x04]
+
+v_max3_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x66,0x04,0x0e,0x04]
+
+v_max3_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x67,0x04,0x0e,0x04]
+
+v_max3_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_max3_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_max3_i32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_max3_i32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_max3_i32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_max3_i32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_max3_i32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_max3_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_max3_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_max3_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_max3_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x80,0x04,0x0e,0x04]
+
+v_max3_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_max3_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_max3_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_max3_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xff,0x0f,0x04]
+
+v_max3_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0c,0x04]
+
+v_max3_i32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_max3_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_max3_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_max3_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_max3_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_max3_i32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_max3_i32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_max3_i32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_max3_i32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_max3_i32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_max3_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_max3_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_max3_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xff,0x0c,0x04]
+
+v_max3_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x01,0x0d,0x04]
+
+v_max3_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x83,0x0d,0x04]
+
+v_max3_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_max3_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xef,0x0d,0x04]
+
+v_max3_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_max3_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_max3_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_max3_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfe,0x07]
+
+v_max3_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x00]
+
+v_max3_i32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x96,0x01]
+
+v_max3_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x9a,0x01]
+
+v_max3_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x9e,0x01]
+
+v_max3_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xaa,0x01]
+
+v_max3_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xae,0x01]
+
+v_max3_i32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xb2,0x01]
+
+v_max3_i32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xb6,0x01]
+
+v_max3_i32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xba,0x01]
+
+v_max3_i32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xbe,0x01]
+
+v_max3_i32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xee,0x01]
+
+v_max3_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xf2,0x01]
+
+v_max3_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfa,0x01]
+
+v_max3_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfe,0x01]
+
+v_max3_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x02,0x02]
+
+v_max3_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x06,0x03]
+
+v_max3_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xc2,0x03]
+
+v_max3_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xde,0x03]
+
+v_max3_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xee,0x03]
+
+v_max3_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xf2,0x03]
+
+v_max3_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xf6,0x03]
+
+v_max3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xff,0x05,0x0e,0x04]
+
+v_max3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x04,0x0e,0x04]
+
+v_max3_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x65,0x04,0x0e,0x04]
+
+v_max3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x66,0x04,0x0e,0x04]
+
+v_max3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x67,0x04,0x0e,0x04]
+
+v_max3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_max3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_max3_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_max3_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_max3_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_max3_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_max3_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_max3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_max3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_max3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_max3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x80,0x04,0x0e,0x04]
+
+v_max3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_max3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_max3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_max3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xff,0x0f,0x04]
+
+v_max3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0c,0x04]
+
+v_max3_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_max3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_max3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_max3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_max3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_max3_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_max3_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_max3_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_max3_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_max3_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_max3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_max3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_max3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xff,0x0c,0x04]
+
+v_max3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x01,0x0d,0x04]
+
+v_max3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x83,0x0d,0x04]
+
+v_max3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_max3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xef,0x0d,0x04]
+
+v_max3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_max3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_max3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_max3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfe,0x07]
+
+v_max3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x00]
+
+v_max3_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x96,0x01]
+
+v_max3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x9a,0x01]
+
+v_max3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x9e,0x01]
+
+v_max3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xaa,0x01]
+
+v_max3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xae,0x01]
+
+v_max3_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xb2,0x01]
+
+v_max3_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xb6,0x01]
+
+v_max3_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xba,0x01]
+
+v_max3_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xbe,0x01]
+
+v_max3_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xee,0x01]
+
+v_max3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xf2,0x01]
+
+v_max3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfa,0x01]
+
+v_max3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfe,0x01]
+
+v_max3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x02,0x02]
+
+v_max3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x06,0x03]
+
+v_max3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xc2,0x03]
+
+v_max3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xde,0x03]
+
+v_max3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xee,0x03]
+
+v_max3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xf2,0x03]
+
+v_max3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xf6,0x03]
+
+v_med3_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xff,0x05,0x0e,0x04]
+
+v_med3_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x04,0x0e,0x04]
+
+v_med3_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x65,0x04,0x0e,0x04]
+
+v_med3_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x66,0x04,0x0e,0x04]
+
+v_med3_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x67,0x04,0x0e,0x04]
+
+v_med3_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_med3_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_med3_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_med3_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_med3_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_med3_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_med3_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_med3_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_med3_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_med3_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_med3_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x80,0x04,0x0e,0x04]
+
+v_med3_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_med3_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_med3_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_med3_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xff,0x0f,0x04]
+
+v_med3_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0c,0x04]
+
+v_med3_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_med3_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_med3_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_med3_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_med3_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_med3_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_med3_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_med3_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_med3_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_med3_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_med3_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_med3_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_med3_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xff,0x0c,0x04]
+
+v_med3_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x01,0x0d,0x04]
+
+v_med3_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x83,0x0d,0x04]
+
+v_med3_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_med3_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xef,0x0d,0x04]
+
+v_med3_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_med3_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_med3_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_med3_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfe,0x07]
+
+v_med3_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x00]
+
+v_med3_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x96,0x01]
+
+v_med3_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x9a,0x01]
+
+v_med3_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x9e,0x01]
+
+v_med3_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xaa,0x01]
+
+v_med3_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xae,0x01]
+
+v_med3_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xb2,0x01]
+
+v_med3_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xb6,0x01]
+
+v_med3_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xba,0x01]
+
+v_med3_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xbe,0x01]
+
+v_med3_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xee,0x01]
+
+v_med3_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xf2,0x01]
+
+v_med3_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfa,0x01]
+
+v_med3_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfe,0x01]
+
+v_med3_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x02,0x02]
+
+v_med3_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x06,0x03]
+
+v_med3_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xc2,0x03]
+
+v_med3_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xde,0x03]
+
+v_med3_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xee,0x03]
+
+v_med3_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xf2,0x03]
+
+v_med3_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xf6,0x03]
+
+v_med3_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x24]
+
+v_med3_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x44]
+
+v_med3_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x84]
+
+v_med3_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_med3_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_med3_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x14]
+
+v_med3_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_med3_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xff,0x05,0x0e,0x04]
+
+v_med3_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x04,0x0e,0x04]
+
+v_med3_i32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x65,0x04,0x0e,0x04]
+
+v_med3_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x66,0x04,0x0e,0x04]
+
+v_med3_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x67,0x04,0x0e,0x04]
+
+v_med3_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_med3_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_med3_i32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_med3_i32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_med3_i32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_med3_i32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_med3_i32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_med3_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_med3_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_med3_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_med3_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x80,0x04,0x0e,0x04]
+
+v_med3_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_med3_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_med3_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_med3_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xff,0x0f,0x04]
+
+v_med3_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0c,0x04]
+
+v_med3_i32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_med3_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_med3_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_med3_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_med3_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_med3_i32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_med3_i32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_med3_i32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_med3_i32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_med3_i32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_med3_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_med3_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_med3_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xff,0x0c,0x04]
+
+v_med3_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x01,0x0d,0x04]
+
+v_med3_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x83,0x0d,0x04]
+
+v_med3_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_med3_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xef,0x0d,0x04]
+
+v_med3_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_med3_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_med3_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_med3_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfe,0x07]
+
+v_med3_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x00]
+
+v_med3_i32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x96,0x01]
+
+v_med3_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x9a,0x01]
+
+v_med3_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x9e,0x01]
+
+v_med3_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xaa,0x01]
+
+v_med3_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xae,0x01]
+
+v_med3_i32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xb2,0x01]
+
+v_med3_i32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xb6,0x01]
+
+v_med3_i32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xba,0x01]
+
+v_med3_i32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xbe,0x01]
+
+v_med3_i32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xee,0x01]
+
+v_med3_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xf2,0x01]
+
+v_med3_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfa,0x01]
+
+v_med3_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfe,0x01]
+
+v_med3_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x02,0x02]
+
+v_med3_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x06,0x03]
+
+v_med3_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xc2,0x03]
+
+v_med3_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xde,0x03]
+
+v_med3_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xee,0x03]
+
+v_med3_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xf2,0x03]
+
+v_med3_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xf6,0x03]
+
+v_med3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xff,0x05,0x0e,0x04]
+
+v_med3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x04,0x0e,0x04]
+
+v_med3_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x65,0x04,0x0e,0x04]
+
+v_med3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x66,0x04,0x0e,0x04]
+
+v_med3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x67,0x04,0x0e,0x04]
+
+v_med3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_med3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_med3_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_med3_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_med3_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_med3_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_med3_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_med3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_med3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_med3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_med3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x80,0x04,0x0e,0x04]
+
+v_med3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_med3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_med3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_med3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xff,0x0f,0x04]
+
+v_med3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0c,0x04]
+
+v_med3_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_med3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_med3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_med3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_med3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_med3_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_med3_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_med3_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_med3_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_med3_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_med3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_med3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_med3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xff,0x0c,0x04]
+
+v_med3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x01,0x0d,0x04]
+
+v_med3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x83,0x0d,0x04]
+
+v_med3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_med3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xef,0x0d,0x04]
+
+v_med3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_med3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_med3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_med3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfe,0x07]
+
+v_med3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x00]
+
+v_med3_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x96,0x01]
+
+v_med3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x9a,0x01]
+
+v_med3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x9e,0x01]
+
+v_med3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xaa,0x01]
+
+v_med3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xae,0x01]
+
+v_med3_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xb2,0x01]
+
+v_med3_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xb6,0x01]
+
+v_med3_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xba,0x01]
+
+v_med3_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xbe,0x01]
+
+v_med3_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xee,0x01]
+
+v_med3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xf2,0x01]
+
+v_med3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfa,0x01]
+
+v_med3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfe,0x01]
+
+v_med3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x02,0x02]
+
+v_med3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x06,0x03]
+
+v_med3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xc2,0x03]
+
+v_med3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xde,0x03]
+
+v_med3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xee,0x03]
+
+v_med3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xf2,0x03]
+
+v_med3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xff,0x05,0x0e,0x04]
+
+v_sad_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x04,0x0e,0x04]
+
+v_sad_u8 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x65,0x04,0x0e,0x04]
+
+v_sad_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x66,0x04,0x0e,0x04]
+
+v_sad_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x67,0x04,0x0e,0x04]
+
+v_sad_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_sad_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_sad_u8 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_sad_u8 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_sad_u8 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_sad_u8 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_sad_u8 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_sad_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_sad_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_sad_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_sad_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x80,0x04,0x0e,0x04]
+
+v_sad_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_sad_u8 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_sad_u8 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_sad_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xff,0x0f,0x04]
+
+v_sad_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0c,0x04]
+
+v_sad_u8 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_sad_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_sad_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_sad_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_sad_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_sad_u8 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_sad_u8 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_sad_u8 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_sad_u8 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_sad_u8 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_sad_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_sad_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_sad_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xff,0x0c,0x04]
+
+v_sad_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x01,0x0d,0x04]
+
+v_sad_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x83,0x0d,0x04]
+
+v_sad_u8 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_sad_u8 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xef,0x0d,0x04]
+
+v_sad_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_sad_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_sad_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_sad_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfe,0x07]
+
+v_sad_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x00]
+
+v_sad_u8 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x96,0x01]
+
+v_sad_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x9a,0x01]
+
+v_sad_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x9e,0x01]
+
+v_sad_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xaa,0x01]
+
+v_sad_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xae,0x01]
+
+v_sad_u8 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xb2,0x01]
+
+v_sad_u8 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xb6,0x01]
+
+v_sad_u8 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xba,0x01]
+
+v_sad_u8 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xbe,0x01]
+
+v_sad_u8 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xee,0x01]
+
+v_sad_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xf2,0x01]
+
+v_sad_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfa,0x01]
+
+v_sad_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfe,0x01]
+
+v_sad_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x02,0x02]
+
+v_sad_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x06,0x03]
+
+v_sad_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xc2,0x03]
+
+v_sad_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xde,0x03]
+
+v_sad_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xee,0x03]
+
+v_sad_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xf2,0x03]
+
+v_sad_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_u8 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xd9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xda,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xff,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x65,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x66,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x67,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x80,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xff,0x0f,0x04]
+
+v_sad_hi_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xff,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x01,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x83,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xef,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfe,0x07]
+
+v_sad_hi_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0e,0x00]
+
+v_sad_hi_u8 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x96,0x01]
+
+v_sad_hi_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x9a,0x01]
+
+v_sad_hi_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x9e,0x01]
+
+v_sad_hi_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xaa,0x01]
+
+v_sad_hi_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xae,0x01]
+
+v_sad_hi_u8 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xb2,0x01]
+
+v_sad_hi_u8 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xb6,0x01]
+
+v_sad_hi_u8 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xba,0x01]
+
+v_sad_hi_u8 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xbe,0x01]
+
+v_sad_hi_u8 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xee,0x01]
+
+v_sad_hi_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xf2,0x01]
+
+v_sad_hi_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfa,0x01]
+
+v_sad_hi_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfe,0x01]
+
+v_sad_hi_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x02,0x02]
+
+v_sad_hi_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x06,0x03]
+
+v_sad_hi_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xc2,0x03]
+
+v_sad_hi_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xde,0x03]
+
+v_sad_hi_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xee,0x03]
+
+v_sad_hi_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xf2,0x03]
+
+v_sad_hi_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_hi_u8 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xda,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xff,0x05,0x0e,0x04]
+
+v_sad_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x04,0x0e,0x04]
+
+v_sad_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x65,0x04,0x0e,0x04]
+
+v_sad_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x66,0x04,0x0e,0x04]
+
+v_sad_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x67,0x04,0x0e,0x04]
+
+v_sad_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_sad_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_sad_u16 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_sad_u16 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_sad_u16 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_sad_u16 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_sad_u16 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_sad_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_sad_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_sad_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_sad_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x80,0x04,0x0e,0x04]
+
+v_sad_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_sad_u16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_sad_u16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_sad_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xff,0x0f,0x04]
+
+v_sad_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0c,0x04]
+
+v_sad_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_sad_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_sad_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_sad_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_sad_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_sad_u16 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_sad_u16 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_sad_u16 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_sad_u16 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_sad_u16 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_sad_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_sad_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_sad_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xff,0x0c,0x04]
+
+v_sad_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x01,0x0d,0x04]
+
+v_sad_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x83,0x0d,0x04]
+
+v_sad_u16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_sad_u16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xef,0x0d,0x04]
+
+v_sad_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_sad_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_sad_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_sad_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfe,0x07]
+
+v_sad_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x00]
+
+v_sad_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x96,0x01]
+
+v_sad_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x9a,0x01]
+
+v_sad_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x9e,0x01]
+
+v_sad_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xaa,0x01]
+
+v_sad_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xae,0x01]
+
+v_sad_u16 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xb2,0x01]
+
+v_sad_u16 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xb6,0x01]
+
+v_sad_u16 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xba,0x01]
+
+v_sad_u16 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xbe,0x01]
+
+v_sad_u16 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xee,0x01]
+
+v_sad_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xf2,0x01]
+
+v_sad_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfa,0x01]
+
+v_sad_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfe,0x01]
+
+v_sad_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x02,0x02]
+
+v_sad_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x06,0x03]
+
+v_sad_u16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xc2,0x03]
+
+v_sad_u16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xde,0x03]
+
+v_sad_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xee,0x03]
+
+v_sad_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xf2,0x03]
+
+v_sad_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_u16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xdb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xff,0x05,0x0e,0x04]
+
+v_sad_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x04,0x0e,0x04]
+
+v_sad_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x65,0x04,0x0e,0x04]
+
+v_sad_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x66,0x04,0x0e,0x04]
+
+v_sad_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x67,0x04,0x0e,0x04]
+
+v_sad_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_sad_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_sad_u32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_sad_u32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_sad_u32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_sad_u32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_sad_u32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_sad_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_sad_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_sad_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_sad_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x80,0x04,0x0e,0x04]
+
+v_sad_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_sad_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_sad_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_sad_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xff,0x0f,0x04]
+
+v_sad_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0c,0x04]
+
+v_sad_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_sad_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_sad_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_sad_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_sad_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_sad_u32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_sad_u32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_sad_u32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_sad_u32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_sad_u32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_sad_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_sad_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_sad_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xff,0x0c,0x04]
+
+v_sad_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x01,0x0d,0x04]
+
+v_sad_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x83,0x0d,0x04]
+
+v_sad_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_sad_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xef,0x0d,0x04]
+
+v_sad_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_sad_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_sad_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_sad_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfe,0x07]
+
+v_sad_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x00]
+
+v_sad_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x96,0x01]
+
+v_sad_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x9a,0x01]
+
+v_sad_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x9e,0x01]
+
+v_sad_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xaa,0x01]
+
+v_sad_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xae,0x01]
+
+v_sad_u32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xb2,0x01]
+
+v_sad_u32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xb6,0x01]
+
+v_sad_u32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xba,0x01]
+
+v_sad_u32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xbe,0x01]
+
+v_sad_u32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xee,0x01]
+
+v_sad_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xf2,0x01]
+
+v_sad_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfa,0x01]
+
+v_sad_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfe,0x01]
+
+v_sad_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x02,0x02]
+
+v_sad_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x06,0x03]
+
+v_sad_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xc2,0x03]
+
+v_sad_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xde,0x03]
+
+v_sad_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xee,0x03]
+
+v_sad_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xf2,0x03]
+
+v_sad_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_u32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xdc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cvt_pk_u8_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cvt_pk_u8_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x96,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xae,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xb2,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xb6,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xba,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xbe,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xee,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x02,0x02]
+
+v_cvt_pk_u8_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x06,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xde,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xee,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cvt_pk_u8_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cvt_pk_u8_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xdd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xff,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x65,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x67,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xff,0x0f,0x04]
+
+v_div_fixup_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xff,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfe,0x07]
+
+v_div_fixup_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x00]
+
+v_div_fixup_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x96,0x01]
+
+v_div_fixup_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_fixup_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x9e,0x01]
+
+v_div_fixup_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xae,0x01]
+
+v_div_fixup_f32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xb2,0x01]
+
+v_div_fixup_f32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xb6,0x01]
+
+v_div_fixup_f32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xba,0x01]
+
+v_div_fixup_f32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xbe,0x01]
+
+v_div_fixup_f32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xee,0x01]
+
+v_div_fixup_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xf2,0x01]
+
+v_div_fixup_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfe,0x01]
+
+v_div_fixup_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_fixup_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_fixup_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_div_fixup_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x14]
+
+v_div_fixup_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[2:3], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x02,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[4:5], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x04,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[100:101], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x64,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], tba, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], tma, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], ttmp[10:11], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], exec, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], src_vccz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], src_execz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], src_scc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfd,0x0f,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[4:5], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x09,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[6:7], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x0d,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[100:101], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xc9,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], tba, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], tma, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], ttmp[10:11], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xf5,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], exec, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xfa,0x07]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[6:7]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x1a,0x00]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[8:9]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x22,0x00]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[100:101]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x92,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], flat_scratch
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], tba
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xb2,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], tma
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xba,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], ttmp[10:11]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xea,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], exec
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -1
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], src_vccz
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], src_execz
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], src_scc
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// CHECK: [0x05,0x01,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// CHECK: [0x05,0x02,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// CHECK: [0x05,0x04,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// CHECK: [0x05,0x07,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// CHECK: [0x05,0x80,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x14]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_div_scale_f32 v5, vcc, v1, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f32 v255, vcc, v1, v2, v3
+// CHECK: [0xff,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, v255, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xff,0x05,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, s1, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, s101, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x65,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x67,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, vcc_lo, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, vcc_hi, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, tba_lo, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, tba_hi, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, tma_lo, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, tma_hi, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, ttmp11, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, m0, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, exec_lo, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, exec_hi, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, 0, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, -1, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, 0.5, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, -4.0, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_vccz, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_execz, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_scc, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_lds_direct, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, v1, v255, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xff,0x0f,0x04]
+
+v_div_scale_f32 v5, vcc, v1, s2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, s101, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, vcc_lo, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, vcc_hi, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, tba_lo, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, tba_hi, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, tma_lo, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, tma_hi, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, ttmp11, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, m0, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, exec_lo, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, exec_hi, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xff,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, 0, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, -1, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, 0.5, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, -4.0, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, src_vccz, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, src_execz, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, src_scc, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, v2, v255
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfe,0x07]
+
+v_div_scale_f32 v5, vcc, v1, v2, s3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x00]
+
+v_div_scale_f32 v5, vcc, v1, v2, s101
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x96,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x9e,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, vcc_lo
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, vcc_hi
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xae,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, tba_lo
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xb2,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, tba_hi
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xb6,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, tma_lo
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xba,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, tma_hi
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xbe,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, ttmp11
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xee,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, m0
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xf2,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, exec_lo
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, exec_hi
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfe,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, 0
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_scale_f32 v5, vcc, v1, v2, -1
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, 0.5
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, -4.0
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, src_vccz
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, src_execz
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, src_scc
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f64 v[254:255], vcc, v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x6a,0xe1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, s[2:3], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x02,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, s[4:5], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x04,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, s[100:101], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x64,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, flat_scratch, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, tba, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, tma, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, ttmp[10:11], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, exec, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, src_vccz, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, src_execz, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, src_scc, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfd,0x0f,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], s[4:5], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x09,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], s[6:7], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x0d,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], s[100:101], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xc9,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], flat_scratch, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], tba, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], tma, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], ttmp[10:11], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xf5,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], exec, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xfa,0x07]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[6:7]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x1a,0x00]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[8:9]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x22,0x00]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[100:101]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x92,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], flat_scratch
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], tba
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xb2,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], tma
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xba,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], ttmp[10:11]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xea,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], exec
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -1
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], src_vccz
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], src_execz
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], src_scc
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_fmas_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xff,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xff,0x0f,0x04]
+
+v_div_fmas_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xfe,0x07]
+
+v_div_fmas_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fmas_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fmas_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fmas_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fmas_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fmas_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fmas_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fmas_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fmas_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_div_fmas_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x14]
+
+v_div_fmas_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xfd,0x0f,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xfa,0x07]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -1
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fmas_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fmas_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fmas_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fmas_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// CHECK: [0x05,0x01,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// CHECK: [0x05,0x02,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// CHECK: [0x05,0x04,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// CHECK: [0x05,0x07,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// CHECK: [0x05,0x80,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x14]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_msad_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_msad_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_msad_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xff,0x05,0x0e,0x04]
+
+v_msad_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x04,0x0e,0x04]
+
+v_msad_u8 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x65,0x04,0x0e,0x04]
+
+v_msad_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x66,0x04,0x0e,0x04]
+
+v_msad_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x67,0x04,0x0e,0x04]
+
+v_msad_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_msad_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_msad_u8 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_msad_u8 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_msad_u8 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_msad_u8 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_msad_u8 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_msad_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_msad_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_msad_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_msad_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x80,0x04,0x0e,0x04]
+
+v_msad_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_msad_u8 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_msad_u8 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_msad_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xff,0x0f,0x04]
+
+v_msad_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0c,0x04]
+
+v_msad_u8 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_msad_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_msad_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_msad_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_msad_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_msad_u8 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_msad_u8 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_msad_u8 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_msad_u8 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_msad_u8 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_msad_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_msad_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_msad_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xff,0x0c,0x04]
+
+v_msad_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x01,0x0d,0x04]
+
+v_msad_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x83,0x0d,0x04]
+
+v_msad_u8 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_msad_u8 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xef,0x0d,0x04]
+
+v_msad_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_msad_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_msad_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_msad_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfe,0x07]
+
+v_msad_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x00]
+
+v_msad_u8 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x96,0x01]
+
+v_msad_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x9a,0x01]
+
+v_msad_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x9e,0x01]
+
+v_msad_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xaa,0x01]
+
+v_msad_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xae,0x01]
+
+v_msad_u8 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xb2,0x01]
+
+v_msad_u8 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xb6,0x01]
+
+v_msad_u8 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xba,0x01]
+
+v_msad_u8 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xbe,0x01]
+
+v_msad_u8 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xee,0x01]
+
+v_msad_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xf2,0x01]
+
+v_msad_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfa,0x01]
+
+v_msad_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfe,0x01]
+
+v_msad_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x02,0x02]
+
+v_msad_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x06,0x03]
+
+v_msad_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xc2,0x03]
+
+v_msad_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xde,0x03]
+
+v_msad_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xee,0x03]
+
+v_msad_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xf2,0x03]
+
+v_msad_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xf6,0x03]
+
+v_msad_u8 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xe4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
+// CHECK: [0xfe,0x00,0xe5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x02,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x04,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[100:101], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x64,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x66,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], tba, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], tma, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x80,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xff,0x0f,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s101, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], tba_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], tba_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], tma_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], tma_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xff,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x01,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x83,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xef,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xfa,0x07]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x1a,0x00]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x22,0x00]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[100:101]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x92,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x9a,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xaa,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, tba
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xb2,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, tma
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xba,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xea,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xfa,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x02,0x02]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x06,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0.5
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xc2,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -4.0
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xde,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, src_vccz
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xee,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, src_execz
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xf2,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, src_scc
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xf6,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
+// CHECK: [0x05,0x80,0xe5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
+// CHECK: [0xfe,0x00,0xe6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x02,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x04,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[100:101], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x64,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], tba, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], tma, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], ttmp[10:11], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s101, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], tba_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], tba_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], tma_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], tma_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], ttmp11, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xfa,0x07]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x1a,0x00]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x22,0x00]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[100:101]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x92,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, tba
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, tma
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xba,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[10:11]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xea,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x02,0x02]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x06,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0.5
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -4.0
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xde,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, src_vccz
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xee,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, src_execz
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, src_scc
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
+// CHECK: [0x05,0x80,0xe6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[2:3], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x02,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[4:5], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x04,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[100:101], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x64,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], flat_scratch, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], vcc, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], tba, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], tma, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], ttmp[10:11], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], exec, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], 0, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], -1, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], 0.5, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], -4.0, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], src_vccz, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], src_execz, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], src_scc, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], s2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], s101, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], vcc_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], vcc_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], tba_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], tba_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], tma_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], tma_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], ttmp11, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], m0, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], exec_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], exec_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], 0, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], -1, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], 0.5, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], -4.0, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], src_vccz, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], src_execz, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], src_scc, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6] clamp
+// CHECK: [0xfc,0x80,0xe7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[254:255], s[12:13], v1, v2, v[3:4]
+// CHECK: [0xfe,0x0c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[14:15], v1, v2, v[3:4]
+// CHECK: [0x05,0x0e,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[100:101], v1, v2, v[3:4]
+// CHECK: [0x05,0x64,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], flat_scratch, v1, v2, v[3:4]
+// CHECK: [0x05,0x66,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], vcc, v1, v2, v[3:4]
+// CHECK: [0x05,0x6a,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], tba, v1, v2, v[3:4]
+// CHECK: [0x05,0x6c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], tma, v1, v2, v[3:4]
+// CHECK: [0x05,0x6e,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], ttmp[10:11], v1, v2, v[3:4]
+// CHECK: [0x05,0x7a,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v255, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], s1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], s101, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], tba_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], tba_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], tma_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], tma_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], ttmp11, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], m0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], 0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], -1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_lds_direct, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v255, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, s2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, s101, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, tba_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, tba_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, tma_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, tma_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, ttmp11, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, m0, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, 0, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, -1, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, 0.5, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, -4.0, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, src_vccz, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, src_execz, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, src_scc, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[254:255]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xfa,0x07]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x1a,0x00]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x22,0x00]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x92,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xba,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xea,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, exec
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -1
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -4.0
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, src_vccz
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, src_execz
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, src_scc
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4] clamp
+// CHECK: [0x05,0x8c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[254:255], s[12:13], v1, v2, v[3:4]
+// CHECK: [0xfe,0x0c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[14:15], v1, v2, v[3:4]
+// CHECK: [0x05,0x0e,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[100:101], v1, v2, v[3:4]
+// CHECK: [0x05,0x64,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], flat_scratch, v1, v2, v[3:4]
+// CHECK: [0x05,0x66,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], vcc, v1, v2, v[3:4]
+// CHECK: [0x05,0x6a,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], tba, v1, v2, v[3:4]
+// CHECK: [0x05,0x6c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], tma, v1, v2, v[3:4]
+// CHECK: [0x05,0x6e,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], ttmp[10:11], v1, v2, v[3:4]
+// CHECK: [0x05,0x7a,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v255, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], s1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], s101, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], tba_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], tba_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], tma_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], tma_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], ttmp11, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], m0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], 0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], -1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_lds_direct, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v255, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, s2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, s101, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, tba_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, tba_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, tma_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, tma_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, ttmp11, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, m0, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, 0, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, -1, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, 0.5, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, -4.0, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, src_vccz, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, src_execz, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, src_scc, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[254:255]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xfa,0x07]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x1a,0x00]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x22,0x00]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x92,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, tba
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, tma
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xba,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, ttmp[10:11]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xea,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, exec
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -1
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -4.0
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, src_vccz
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, src_execz
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, src_scc
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4] clamp
+// CHECK: [0x05,0x8c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_f16 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mad_f16 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_mad_f16 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mad_f16 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_mad_f16 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_f16 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mad_f16 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mad_f16 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mad_f16 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mad_f16 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_f16 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mad_f16 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xb6,0x01]
+
+v_mad_f16 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xba,0x01]
+
+v_mad_f16 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xbe,0x01]
+
+v_mad_f16 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x24]
+
+v_mad_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x84]
+
+v_mad_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_mad_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_u16 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mad_u16 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_mad_u16 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mad_u16 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_mad_u16 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_u16 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mad_u16 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mad_u16 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mad_u16 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mad_u16 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_u16 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mad_u16 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xb6,0x01]
+
+v_mad_u16 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xba,0x01]
+
+v_mad_u16 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xbe,0x01]
+
+v_mad_u16 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_u16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xeb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xec,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_i16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_i16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_i16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_i16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_i16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_i16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_i16 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_mad_i16 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_mad_i16 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_mad_i16 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_mad_i16 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_i16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_i16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_i16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_i16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_i16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_i16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_i16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_i16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_i16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_i16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_i16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_i16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_i16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_i16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_i16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_i16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_i16 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_mad_i16 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_mad_i16 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_mad_i16 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_mad_i16 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_i16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_i16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_i16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_i16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_i16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_i16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_i16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_i16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_i16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_i16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_i16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_i16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_i16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_i16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_i16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_i16 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xb2,0x01]
+
+v_mad_i16 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xb6,0x01]
+
+v_mad_i16 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xba,0x01]
+
+v_mad_i16 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xbe,0x01]
+
+v_mad_i16 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_i16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_i16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_i16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_i16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_i16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_i16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_i16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_i16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_i16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xec,0xd1,0x01,0x05,0x0e,0x04]
+
+v_perm_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0e,0x04]
+
+v_perm_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xed,0xd1,0x01,0x05,0x0e,0x04]
+
+v_perm_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xff,0x05,0x0e,0x04]
+
+v_perm_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x04,0x0e,0x04]
+
+v_perm_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x65,0x04,0x0e,0x04]
+
+v_perm_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x66,0x04,0x0e,0x04]
+
+v_perm_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x67,0x04,0x0e,0x04]
+
+v_perm_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_perm_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_perm_b32 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_perm_b32 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_perm_b32 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_perm_b32 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_perm_b32 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_perm_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_perm_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_perm_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_perm_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x80,0x04,0x0e,0x04]
+
+v_perm_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_perm_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_perm_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_perm_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_perm_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_perm_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_perm_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_perm_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xff,0x0f,0x04]
+
+v_perm_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0c,0x04]
+
+v_perm_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_perm_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_perm_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_perm_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_perm_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_perm_b32 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_perm_b32 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_perm_b32 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_perm_b32 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_perm_b32 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_perm_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_perm_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_perm_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xff,0x0c,0x04]
+
+v_perm_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x01,0x0d,0x04]
+
+v_perm_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x83,0x0d,0x04]
+
+v_perm_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_perm_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xef,0x0d,0x04]
+
+v_perm_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_perm_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_perm_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_perm_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfe,0x07]
+
+v_perm_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0e,0x00]
+
+v_perm_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x96,0x01]
+
+v_perm_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x9a,0x01]
+
+v_perm_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x9e,0x01]
+
+v_perm_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xaa,0x01]
+
+v_perm_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xae,0x01]
+
+v_perm_b32 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xb2,0x01]
+
+v_perm_b32 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xb6,0x01]
+
+v_perm_b32 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xba,0x01]
+
+v_perm_b32 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xbe,0x01]
+
+v_perm_b32 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xee,0x01]
+
+v_perm_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xf2,0x01]
+
+v_perm_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfa,0x01]
+
+v_perm_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfe,0x01]
+
+v_perm_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x02,0x02]
+
+v_perm_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x06,0x03]
+
+v_perm_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xc2,0x03]
+
+v_perm_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xde,0x03]
+
+v_perm_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xee,0x03]
+
+v_perm_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xf2,0x03]
+
+v_perm_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xff,0x05,0x0e,0x04]
+
+v_fma_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x04,0x0e,0x04]
+
+v_fma_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x65,0x04,0x0e,0x04]
+
+v_fma_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x66,0x04,0x0e,0x04]
+
+v_fma_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x67,0x04,0x0e,0x04]
+
+v_fma_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_fma_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_fma_f16 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_fma_f16 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_fma_f16 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_fma_f16 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_fma_f16 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_fma_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_fma_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_fma_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_fma_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x80,0x04,0x0e,0x04]
+
+v_fma_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_fma_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_fma_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_fma_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_fma_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_fma_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_fma_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_fma_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xff,0x0f,0x04]
+
+v_fma_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0c,0x04]
+
+v_fma_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_fma_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_fma_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_fma_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_fma_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_fma_f16 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_fma_f16 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_fma_f16 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_fma_f16 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_fma_f16 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_fma_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_fma_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_fma_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xff,0x0c,0x04]
+
+v_fma_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x01,0x0d,0x04]
+
+v_fma_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x83,0x0d,0x04]
+
+v_fma_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_fma_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xef,0x0d,0x04]
+
+v_fma_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_fma_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_fma_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_fma_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfe,0x07]
+
+v_fma_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x00]
+
+v_fma_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x96,0x01]
+
+v_fma_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x9a,0x01]
+
+v_fma_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x9e,0x01]
+
+v_fma_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xaa,0x01]
+
+v_fma_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xae,0x01]
+
+v_fma_f16 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xb2,0x01]
+
+v_fma_f16 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xb6,0x01]
+
+v_fma_f16 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xba,0x01]
+
+v_fma_f16 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xbe,0x01]
+
+v_fma_f16 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xee,0x01]
+
+v_fma_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xf2,0x01]
+
+v_fma_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfa,0x01]
+
+v_fma_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfe,0x01]
+
+v_fma_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x02,0x02]
+
+v_fma_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x06,0x03]
+
+v_fma_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xc2,0x03]
+
+v_fma_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xde,0x03]
+
+v_fma_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xee,0x03]
+
+v_fma_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xf2,0x03]
+
+v_fma_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x24]
+
+v_fma_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x44]
+
+v_fma_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
+
+v_fma_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_fma_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xff,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x65,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x67,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, tba_lo, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x6c,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, tba_hi, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x6d,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, tma_lo, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x6e,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, tma_hi, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x6f,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, ttmp11, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xff,0x0f,0x04]
+
+v_div_fixup_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, tba_lo, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd9,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, tba_hi, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xdb,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, tma_lo, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xdd,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, tma_hi, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xdf,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, ttmp11, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xff,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfe,0x07]
+
+v_div_fixup_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x00]
+
+v_div_fixup_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x96,0x01]
+
+v_div_fixup_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_fixup_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x9e,0x01]
+
+v_div_fixup_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xae,0x01]
+
+v_div_fixup_f16 v5, v1, v2, tba_lo
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xb2,0x01]
+
+v_div_fixup_f16 v5, v1, v2, tba_hi
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xb6,0x01]
+
+v_div_fixup_f16 v5, v1, v2, tma_lo
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xba,0x01]
+
+v_div_fixup_f16 v5, v1, v2, tma_hi
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xbe,0x01]
+
+v_div_fixup_f16 v5, v1, v2, ttmp11
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xee,0x01]
+
+v_div_fixup_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xf2,0x01]
+
+v_div_fixup_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfe,0x01]
+
+v_div_fixup_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_fixup_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_fixup_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cvt_pkaccum_u8_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0xf0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xff,0x05,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x65,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x66,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x67,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x6c,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x6d,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x6e,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x6f,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x80,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xff,0x03,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcb,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd9,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xdb,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xdd,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xdf,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xff,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x01,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x83,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xef,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x02,0x20]
+
+v_cvt_pkaccum_u8_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0xf0,0xd1,0x01,0x05,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v255, v2, attr0.x
+// CHECK: [0xff,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr1.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr31.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr32.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x20,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v255, attr0.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0xfe,0x03,0x00]
+
+v_interp_p1ll_f16 v5, -v2, attr0.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p1ll_f16 v5, |v2|, attr0.x
+// CHECK: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.y
+// CHECK: [0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.z
+// CHECK: [0x05,0x00,0x74,0xd2,0x80,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.w
+// CHECK: [0x05,0x00,0x74,0xd2,0xc0,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x high
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x clamp
+// CHECK: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x mul:2
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x08]
+
+v_interp_p1ll_f16 v5, v2, attr0.x mul:4
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x10]
+
+v_interp_p1ll_f16 v5, v2, attr0.x div:2
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v255, v2, attr0.x, v3
+// CHECK: [0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr1.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x01,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr31.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x1f,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr32.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v255, attr0.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0xfe,0x0f,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v255
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0xfe,0x07]
+
+v_interp_p1lv_f16 v5, -v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, -v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
+
+v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
+// CHECK: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
+// CHECK: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.y, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x40,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.z, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x80,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.w, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0xc0,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
+// CHECK: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x0c]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:4
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x1c]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v255, v2, attr0.x, v3
+// CHECK: [0xff,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr1.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr31.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr32.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x20,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v255, attr0.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0xfe,0x0f,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v255
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0xfe,0x07]
+
+v_interp_p2_f16 v5, -v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p2_f16 v5, v2, attr0.x, -v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
+
+v_interp_p2_f16 v5, |v2|, attr0.x, v3
+// CHECK: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, |v3|
+// CHECK: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.y, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x40,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.z, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x80,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.w, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 high
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
+// CHECK: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_add_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xfe,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x02,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x04,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], s[100:101], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x64,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x66,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x6a,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], tba, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x6c,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], tma, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x6e,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], ttmp[10:11], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x7a,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x7e,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x80,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xc1,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xf0,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xf7,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xfb,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xfc,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xfd,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x03,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x09,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x0d,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[100:101]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xc9,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xcd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd5,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], tba
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd9,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], tma
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xdd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], ttmp[10:11]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf5,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x01,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x83,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xe1,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xef,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf7,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf9,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfb,0x01,0x00]
+
+v_add_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x20]
+
+v_add_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x40]
+
+v_add_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x60]
+
+v_add_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x80,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x08]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x10]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x18]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xfe,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x02,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x04,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], s[100:101], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x64,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x66,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], tba, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], tma, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], ttmp[10:11], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x7a,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x03,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x09,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x0d,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[100:101]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xc9,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], tba
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], tma
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], ttmp[10:11]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xf5,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x20]
+
+v_mul_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x40]
+
+v_mul_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x60]
+
+v_mul_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x80,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x08]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x10]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x18]
+
+v_min_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xfe,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x02,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x04,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], s[100:101], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x64,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x66,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x6a,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], tba, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x6c,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], tma, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x6e,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], ttmp[10:11], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x7a,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x7e,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x80,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xc1,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xf0,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xf7,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xfb,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xfc,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xfd,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x03,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x09,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x0d,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[100:101]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xc9,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xcd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd5,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], tba
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd9,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], tma
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xdd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], ttmp[10:11]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf5,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x01,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x83,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xe1,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xef,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf7,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf9,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfb,0x01,0x00]
+
+v_min_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x20]
+
+v_min_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x40]
+
+v_min_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x60]
+
+v_min_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x80,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x08]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x10]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x18]
+
+v_max_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xfe,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x02,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x04,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], s[100:101], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x64,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x66,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x6a,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], tba, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x6c,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], tma, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x6e,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], ttmp[10:11], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x7a,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x7e,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x80,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xc1,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xf0,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xf7,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xfb,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xfc,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xfd,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x03,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x09,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x0d,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[100:101]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xc9,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xcd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xd5,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], tba
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xd9,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], tma
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xdd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], ttmp[10:11]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xf5,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x01,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x83,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xe1,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xef,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xf7,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xf9,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfb,0x01,0x00]
+
+v_max_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x20]
+
+v_max_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x40]
+
+v_max_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x60]
+
+v_max_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x80,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x08]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x10]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x18]
+
+v_ldexp_f64 v[5:6], v[1:2], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[254:255], v[1:2], v2
+// CHECK: [0xfe,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[254:255], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xfe,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[2:3], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x02,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[4:5], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x04,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[100:101], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x64,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], flat_scratch, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x66,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], vcc, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], tba, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x6c,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], tma, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x6e,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], ttmp[10:11], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x7a,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], exec, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], 0, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x80,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], -1, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], 0.5, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], -4.0, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], src_vccz, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], src_execz, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], src_scc, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v255
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x03,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s101
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcb,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], flat_scratch_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcd,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], flat_scratch_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], vcc_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], vcc_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], tba_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd9,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], tba_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdb,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], tma_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdd,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], tma_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xdf,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], ttmp11
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf7,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], m0
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], exec_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], exec_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x01,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x83,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xef,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f64 v[5:6], -v[1:2], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x20]
+
+v_ldexp_f64 v[5:6], |v[1:2]|, v2
+// CHECK: [0x05,0x01,0x84,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 clamp
+// CHECK: [0x05,0x80,0x84,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 mul:2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x08]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 mul:4
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x10]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 div:2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x18]
+
+v_mul_lo_u32 v5, v1, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u32 v255, v1, v2
+// CHECK: [0xff,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u32 v5, v255, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_lo_u32 v5, s1, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, s101, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x65,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x66,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, m0, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, 0, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, -1, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, v1, v255
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_lo_u32 v5, v1, s2
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, s101
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, m0
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, 0
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, -1
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32 v255, v1, v2
+// CHECK: [0xff,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32 v5, v255, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_hi_u32 v5, s1, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, s101, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x65,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x66,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, m0, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, 0, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, -1, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, v1, v255
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_hi_u32 v5, v1, s2
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, s101
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, m0
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, 0
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, -1
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32 v255, v1, v2
+// CHECK: [0xff,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32 v5, v255, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_hi_i32 v5, s1, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, s101, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x65,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x66,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, m0, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, 0, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, -1, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, v1, v255
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_hi_i32 v5, v1, s2
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, s101
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, m0
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, 0
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, -1
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xff,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x65,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x66,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x67,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x6b,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x6c,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x6d,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x6e,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x6f,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x7b,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x7c,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x7f,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x80,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xfe,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x03,0x00]
+
+v_ldexp_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x00,0x00]
+
+v_ldexp_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcb,0x00,0x00]
+
+v_ldexp_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcd,0x00,0x00]
+
+v_ldexp_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd9,0x00,0x00]
+
+v_ldexp_f32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdb,0x00,0x00]
+
+v_ldexp_f32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdd,0x00,0x00]
+
+v_ldexp_f32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xdf,0x00,0x00]
+
+v_ldexp_f32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf7,0x00,0x00]
+
+v_ldexp_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x00,0x00]
+
+v_ldexp_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x01,0x01,0x00]
+
+v_ldexp_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x83,0x01,0x00]
+
+v_ldexp_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xef,0x01,0x00]
+
+v_ldexp_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ldexp_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ldexp_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x20]
+
+v_ldexp_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x88,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x88,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x08]
+
+v_ldexp_f32 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x10]
+
+v_ldexp_f32 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x18]
+
+v_readlane_b32 s5, v1, s2
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 s101, v1, s2
+// CHECK: [0x65,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 flat_scratch_lo, v1, s2
+// CHECK: [0x66,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 flat_scratch_hi, v1, s2
+// CHECK: [0x67,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 tba_lo, v1, s2
+// CHECK: [0x6c,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 tba_hi, v1, s2
+// CHECK: [0x6d,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 tma_lo, v1, s2
+// CHECK: [0x6e,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 tma_hi, v1, s2
+// CHECK: [0x6f,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 ttmp11, v1, s2
+// CHECK: [0x7b,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 s5, v255, s2
+// CHECK: [0x05,0x00,0x89,0xd2,0xff,0x05,0x00,0x00]
+
+v_readlane_b32 s5, src_lds_direct, s2
+// CHECK: [0x05,0x00,0x89,0xd2,0xfe,0x04,0x00,0x00]
+
+v_readlane_b32 s5, v1, s101
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcb,0x00,0x00]
+
+v_readlane_b32 s5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcd,0x00,0x00]
+
+v_readlane_b32 s5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcf,0x00,0x00]
+
+v_readlane_b32 s5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd5,0x00,0x00]
+
+v_readlane_b32 s5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd7,0x00,0x00]
+
+v_readlane_b32 s5, v1, tba_lo
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd9,0x00,0x00]
+
+v_readlane_b32 s5, v1, tba_hi
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xdb,0x00,0x00]
+
+v_readlane_b32 s5, v1, tma_lo
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xdd,0x00,0x00]
+
+v_readlane_b32 s5, v1, tma_hi
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xdf,0x00,0x00]
+
+v_readlane_b32 s5, v1, ttmp11
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xf7,0x00,0x00]
+
+v_readlane_b32 s5, v1, m0
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xf9,0x00,0x00]
+
+v_readlane_b32 s5, v1, 0
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0x01,0x01,0x00]
+
+v_writelane_b32 v5, 0, s2
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
+
+v_writelane_b32 v255, 0, s2
+// CHECK: [0xff,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
+
+v_writelane_b32 v5, -1, s2
+// CHECK: [0x05,0x00,0x8a,0xd2,0xc1,0x04,0x00,0x00]
+
+v_writelane_b32 v5, 0.5, s2
+// CHECK: [0x05,0x00,0x8a,0xd2,0xf0,0x04,0x00,0x00]
+
+v_writelane_b32 v5, -4.0, s2
+// CHECK: [0x05,0x00,0x8a,0xd2,0xf7,0x04,0x00,0x00]
+
+v_writelane_b32 v5, 0, s101
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xca,0x00,0x00]
+
+v_writelane_b32 v5, 0, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xcc,0x00,0x00]
+
+v_writelane_b32 v5, 0, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xce,0x00,0x00]
+
+v_writelane_b32 v5, 0, vcc_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd4,0x00,0x00]
+
+v_writelane_b32 v5, 0, vcc_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd6,0x00,0x00]
+
+v_writelane_b32 v5, 0, tba_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd8,0x00,0x00]
+
+v_writelane_b32 v5, 0, tba_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xda,0x00,0x00]
+
+v_writelane_b32 v5, 0, tma_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xdc,0x00,0x00]
+
+v_writelane_b32 v5, 0, tma_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xde,0x00,0x00]
+
+v_writelane_b32 v5, 0, ttmp11
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xf6,0x00,0x00]
+
+v_writelane_b32 v5, 0, m0
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xf8,0x00,0x00]
+
+v_writelane_b32 v5, 0, 0
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x00,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v255, v1, v2
+// CHECK: [0xff,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v5, v255, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xff,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v5, s1, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, s101, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x65,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x66,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x67,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x6a,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x6b,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x6c,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x6d,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x6e,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x6f,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x7b,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, m0, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x7c,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x7e,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x7f,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, 0, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x80,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, -1, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xc1,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xf0,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xf7,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xfb,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xfc,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xfd,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xfe,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, v1, v255
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x03,0x00]
+
+v_bcnt_u32_b32 v5, v1, s2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, s101
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcb,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcd,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcf,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd5,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd7,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd9,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xdb,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xdd,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xdf,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf7,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, m0
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf9,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xfd,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, 0
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x01,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, -1
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x83,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xe1,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xef,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf7,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf9,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v255, v1, v2
+// CHECK: [0xff,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v255, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xff,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, s1, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, s101, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x65,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x66,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x67,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, m0, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, 0, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x80,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, -1, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, v255
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x03,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, s2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, s101
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, m0
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, 0
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x01,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, -1
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x83,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xef,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v255, v1, v2
+// CHECK: [0xff,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v255, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xff,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, s1, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, s101, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x65,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x66,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x67,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x6c,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x6d,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x6e,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x6f,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, m0, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, 0, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x80,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, -1, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, v255
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x03,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, s2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, s101
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd9,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xdb,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xdd,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xdf,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, m0
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, 0
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x01,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, -1
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x83,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xef,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xfb,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b64 v[254:255], v1, v[2:3]
+// CHECK: [0xfe,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], v255, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], s1, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], s101, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x65,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], flat_scratch_lo, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x66,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], flat_scratch_hi, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x67,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], vcc_lo, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], vcc_hi, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], tba_lo, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x6c,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], tba_hi, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x6d,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], tma_lo, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x6e,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], tma_hi, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x6f,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], ttmp11, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x7b,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], m0, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], exec_lo, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], exec_hi, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], v1, v[254:255]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x03,0x00]
+
+v_lshlrev_b64 v[5:6], v1, s[4:5]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x09,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, s[6:7]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x0d,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, s[100:101]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xc9,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, flat_scratch
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xcd,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, vcc
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, tba
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xd9,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, tma
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xdd,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, ttmp[10:11]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xf5,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, exec
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, 0
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, -1
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, 0.5
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, -4.0
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, src_vccz
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, src_execz
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, src_scc
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfb,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b64 v[254:255], v1, v[2:3]
+// CHECK: [0xfe,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], v255, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], s1, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], s101, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x65,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], flat_scratch_lo, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x66,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], flat_scratch_hi, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x67,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], vcc_lo, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], vcc_hi, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], tba_lo, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x6c,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], tba_hi, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x6d,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], tma_lo, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x6e,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], tma_hi, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x6f,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], ttmp11, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x7b,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], m0, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], exec_lo, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], exec_hi, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], v1, v[254:255]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x03,0x00]
+
+v_lshrrev_b64 v[5:6], v1, s[4:5]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x09,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, s[6:7]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x0d,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, s[100:101]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xc9,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, flat_scratch
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xcd,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, vcc
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, tba
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd9,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, tma
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xdd,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, ttmp[10:11]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf5,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, exec
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, 0
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, -1
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, 0.5
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, -4.0
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, src_vccz
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, src_execz
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, src_scc
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i64 v[254:255], v1, v[2:3]
+// CHECK: [0xfe,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], v255, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], s1, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], s101, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x65,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], flat_scratch_lo, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x66,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], flat_scratch_hi, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x67,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], vcc_lo, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], vcc_hi, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], tba_lo, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x6c,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], tba_hi, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x6d,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], tma_lo, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x6e,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], tma_hi, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x6f,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], ttmp11, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x7b,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], m0, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], exec_lo, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], exec_hi, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], v1, v[254:255]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x03,0x00]
+
+v_ashrrev_i64 v[5:6], v1, s[4:5]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x09,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, s[6:7]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x0d,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, s[100:101]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xc9,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, flat_scratch
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xcd,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, vcc
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, tba
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xd9,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, tma
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xdd,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, ttmp[10:11]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xf5,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, exec
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, 0
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, -1
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, 0.5
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, -4.0
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xef,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, src_vccz
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, src_execz
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, src_scc
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfb,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[254:255], v[1:2], v2
+// CHECK: [0xfe,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[254:255], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xfe,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[2:3], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x02,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[4:5], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x04,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[100:101], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x64,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], flat_scratch, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x66,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], vcc, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x6a,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], tba, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x6c,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], tma, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x6e,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], ttmp[10:11], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x7a,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], exec, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x7e,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], 0, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x80,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], -1, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xc1,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], 0.5, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xf0,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], -4.0, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xf7,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], src_vccz, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xfb,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], src_execz, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xfc,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], src_scc, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xfd,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v255
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x03,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s101
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcb,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcd,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcf,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], vcc_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd5,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], vcc_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd7,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], tba_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd9,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], tba_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdb,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], tma_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdd,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], tma_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xdf,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], ttmp11
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf7,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], m0
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], exec_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfd,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], exec_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x01,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x83,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xe1,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xef,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf7,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfb,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], -v[1:2], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x20]
+
+v_trig_preop_f64 v[5:6], |v[1:2]|, v2
+// CHECK: [0x05,0x01,0x92,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 clamp
+// CHECK: [0x05,0x80,0x92,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 mul:2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x08]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 mul:4
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x10]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 div:2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x18]
+
+v_bfm_b32 v5, v1, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
+
+v_bfm_b32 v255, v1, v2
+// CHECK: [0xff,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
+
+v_bfm_b32 v5, v255, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xff,0x05,0x02,0x00]
+
+v_bfm_b32 v5, s1, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x04,0x02,0x00]
+
+v_bfm_b32 v5, s101, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x65,0x04,0x02,0x00]
+
+v_bfm_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x66,0x04,0x02,0x00]
+
+v_bfm_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x67,0x04,0x02,0x00]
+
+v_bfm_b32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x6a,0x04,0x02,0x00]
+
+v_bfm_b32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x6b,0x04,0x02,0x00]
+
+v_bfm_b32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x6c,0x04,0x02,0x00]
+
+v_bfm_b32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x6d,0x04,0x02,0x00]
+
+v_bfm_b32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x6e,0x04,0x02,0x00]
+
+v_bfm_b32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x6f,0x04,0x02,0x00]
+
+v_bfm_b32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x7b,0x04,0x02,0x00]
+
+v_bfm_b32 v5, m0, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x7c,0x04,0x02,0x00]
+
+v_bfm_b32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x7e,0x04,0x02,0x00]
+
+v_bfm_b32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x7f,0x04,0x02,0x00]
+
+v_bfm_b32 v5, 0, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x80,0x04,0x02,0x00]
+
+v_bfm_b32 v5, -1, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xc1,0x04,0x02,0x00]
+
+v_bfm_b32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xf0,0x04,0x02,0x00]
+
+v_bfm_b32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xf7,0x04,0x02,0x00]
+
+v_bfm_b32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xfb,0x04,0x02,0x00]
+
+v_bfm_b32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xfc,0x04,0x02,0x00]
+
+v_bfm_b32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xfd,0x04,0x02,0x00]
+
+v_bfm_b32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xfe,0x04,0x02,0x00]
+
+v_bfm_b32 v5, v1, v255
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x03,0x00]
+
+v_bfm_b32 v5, v1, s2
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x00,0x00]
+
+v_bfm_b32 v5, v1, s101
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcb,0x00,0x00]
+
+v_bfm_b32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcd,0x00,0x00]
+
+v_bfm_b32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcf,0x00,0x00]
+
+v_bfm_b32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd5,0x00,0x00]
+
+v_bfm_b32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd7,0x00,0x00]
+
+v_bfm_b32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd9,0x00,0x00]
+
+v_bfm_b32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xdb,0x00,0x00]
+
+v_bfm_b32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xdd,0x00,0x00]
+
+v_bfm_b32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xdf,0x00,0x00]
+
+v_bfm_b32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf7,0x00,0x00]
+
+v_bfm_b32 v5, v1, m0
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf9,0x00,0x00]
+
+v_bfm_b32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xfd,0x00,0x00]
+
+v_bfm_b32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x00,0x00]
+
+v_bfm_b32 v5, v1, 0
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x01,0x01,0x00]
+
+v_bfm_b32 v5, v1, -1
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x83,0x01,0x00]
+
+v_bfm_b32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xe1,0x01,0x00]
+
+v_bfm_b32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xef,0x01,0x00]
+
+v_bfm_b32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf7,0x01,0x00]
+
+v_bfm_b32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf9,0x01,0x00]
+
+v_bfm_b32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_i16_f32 v5, v1, -v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_i16_f32 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_i16_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_u16_f32 v5, v1, -v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_u16_f32 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_u16_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pkrtz_f16_f32 v5, v1, -v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pkrtz_f16_f32 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pkrtz_f16_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v255, v1, v2
+// CHECK: [0xff,0x00,0x97,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v255, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, s1, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, s101, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, m0, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, 0, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, -1, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, v255
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, s2
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, s101
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, m0
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, 0
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, -1
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v255, v1, v2
+// CHECK: [0xff,0x00,0x98,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, v255, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, s1, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, s101, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, tba_lo, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x6c,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, tba_hi, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x6d,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, tma_lo, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x6e,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, tma_hi, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x6f,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, ttmp11, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, m0, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, 0, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, -1, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, v255
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, s2
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, s101
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, tba_lo
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd9,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, tba_hi
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xdb,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, tma_lo
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xdd,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, tma_hi
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xdf,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, ttmp11
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, m0
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, 0
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, -1
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfb,0x01,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
new file mode 100644
index 0000000000000..31e9ad58b7d78
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx8_asm_vopc.s
@@ -0,0 +1,22963 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
+
+v_cmp_class_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x20,0x7c]
+
+v_cmp_class_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x20,0x7c]
+
+v_cmp_class_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x20,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_class_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x20,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_class_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x21,0x7c]
+
+v_cmpx_class_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x22,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x22,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_class_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x23,0x7c]
+
+v_cmp_class_f64 vcc, v[1:2], v2
+// CHECK: [0x01,0x05,0x24,0x7c]
+
+v_cmp_class_f64 vcc, v[254:255], v2
+// CHECK: [0xfe,0x05,0x24,0x7c]
+
+v_cmp_class_f64 vcc, s[2:3], v2
+// CHECK: [0x02,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, s[4:5], v2
+// CHECK: [0x04,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, s[100:101], v2
+// CHECK: [0x64,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, flat_scratch, v2
+// CHECK: [0x66,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, vcc, v2
+// CHECK: [0x6a,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, tba, v2
+// CHECK: [0x6c,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, tma, v2
+// CHECK: [0x6e,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, ttmp[10:11], v2
+// CHECK: [0x7a,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, exec, v2
+// CHECK: [0x7e,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, 0, v2
+// CHECK: [0x80,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x24,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_class_f64 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x24,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_class_f64 vcc, v[1:2], v255
+// CHECK: [0x01,0xff,0x25,0x7c]
+
+v_cmpx_class_f64 vcc, v[1:2], v2
+// CHECK: [0x01,0x05,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, v[254:255], v2
+// CHECK: [0xfe,0x05,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, s[2:3], v2
+// CHECK: [0x02,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, s[4:5], v2
+// CHECK: [0x04,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, s[100:101], v2
+// CHECK: [0x64,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, flat_scratch, v2
+// CHECK: [0x66,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, vcc, v2
+// CHECK: [0x6a,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, tba, v2
+// CHECK: [0x6c,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, tma, v2
+// CHECK: [0x6e,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, ttmp[10:11], v2
+// CHECK: [0x7a,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, exec, v2
+// CHECK: [0x7e,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, 0, v2
+// CHECK: [0x80,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x26,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f64 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x26,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_class_f64 vcc, v[1:2], v255
+// CHECK: [0x01,0xff,0x27,0x7c]
+
+v_cmp_class_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x28,0x7c]
+
+v_cmp_class_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x28,0x7c]
+
+v_cmp_class_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x28,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_class_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x28,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_class_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x29,0x7c]
+
+v_cmpx_class_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x2a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_class_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x2a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_class_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x2b,0x7c]
+
+v_cmp_f_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x40,0x7c]
+
+v_cmp_f_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x40,0x7c]
+
+v_cmp_f_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x40,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_f_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x40,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_f_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x41,0x7c]
+
+v_cmp_lt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x42,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x42,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_lt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x43,0x7c]
+
+v_cmp_eq_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x44,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_eq_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x44,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_eq_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x45,0x7c]
+
+v_cmp_le_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x46,0x7c]
+
+v_cmp_le_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x46,0x7c]
+
+v_cmp_le_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x46,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_le_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x46,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_le_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x47,0x7c]
+
+v_cmp_gt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x48,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_gt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x48,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_gt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x49,0x7c]
+
+v_cmp_lg_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lg_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_lg_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4b,0x7c]
+
+v_cmp_ge_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4c,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ge_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_ge_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4d,0x7c]
+
+v_cmp_o_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4e,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_o_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_o_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4f,0x7c]
+
+v_cmp_u_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x50,0x7c]
+
+v_cmp_u_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x50,0x7c]
+
+v_cmp_u_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x50,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_u_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x50,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_u_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x51,0x7c]
+
+v_cmp_nge_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x52,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nge_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x52,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_nge_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x53,0x7c]
+
+v_cmp_nlg_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x54,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nlg_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x54,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_nlg_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x55,0x7c]
+
+v_cmp_ngt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x56,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ngt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x56,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_ngt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x57,0x7c]
+
+v_cmp_nle_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x58,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nle_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x58,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_nle_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x59,0x7c]
+
+v_cmp_neq_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_neq_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_neq_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5b,0x7c]
+
+v_cmp_nlt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5c,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nlt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_nlt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5d,0x7c]
+
+v_cmp_tru_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5e,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_tru_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_tru_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5f,0x7c]
+
+v_cmpx_f_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x60,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_f_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x60,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_f_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x61,0x7c]
+
+v_cmpx_lt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x62,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x62,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x63,0x7c]
+
+v_cmpx_eq_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x64,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x64,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_eq_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x65,0x7c]
+
+v_cmpx_le_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x66,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x66,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_le_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x67,0x7c]
+
+v_cmpx_gt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x68,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x68,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_gt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x69,0x7c]
+
+v_cmpx_lg_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lg_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_lg_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6b,0x7c]
+
+v_cmpx_ge_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6c,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6c,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_ge_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6d,0x7c]
+
+v_cmpx_o_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6e,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_o_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6e,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_o_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6f,0x7c]
+
+v_cmpx_u_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x70,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_u_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x70,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_u_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x71,0x7c]
+
+v_cmpx_nge_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x72,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nge_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x72,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_nge_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x73,0x7c]
+
+v_cmpx_nlg_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x74,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlg_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x74,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_nlg_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x75,0x7c]
+
+v_cmpx_ngt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x76,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ngt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x76,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_ngt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x77,0x7c]
+
+v_cmpx_nle_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x78,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nle_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x78,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_nle_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x79,0x7c]
+
+v_cmpx_neq_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_neq_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_neq_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7b,0x7c]
+
+v_cmpx_nlt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7c,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7c,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_nlt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7d,0x7c]
+
+v_cmpx_tru_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7e,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_tru_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7e,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_tru_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7f,0x7c]
+
+v_cmp_f_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x80,0x7c]
+
+v_cmp_f_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x80,0x7c]
+
+v_cmp_f_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x80,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x80,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x81,0x7c]
+
+v_cmp_lt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x82,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x82,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x83,0x7c]
+
+v_cmp_eq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x84,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x84,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x85,0x7c]
+
+v_cmp_le_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x86,0x7c]
+
+v_cmp_le_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x86,0x7c]
+
+v_cmp_le_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x86,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x86,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x87,0x7c]
+
+v_cmp_gt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x88,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x88,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x89,0x7c]
+
+v_cmp_lg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8b,0x7c]
+
+v_cmp_ge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8d,0x7c]
+
+v_cmp_o_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_o_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_o_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8f,0x7c]
+
+v_cmp_u_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x90,0x7c]
+
+v_cmp_u_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x90,0x7c]
+
+v_cmp_u_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x90,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_u_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x90,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_u_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x91,0x7c]
+
+v_cmp_nge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x92,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x92,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x93,0x7c]
+
+v_cmp_nlg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x94,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x94,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x95,0x7c]
+
+v_cmp_ngt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x96,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ngt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x96,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ngt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x97,0x7c]
+
+v_cmp_nle_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x98,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nle_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x98,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nle_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x99,0x7c]
+
+v_cmp_neq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_neq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_neq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9b,0x7c]
+
+v_cmp_nlt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9d,0x7c]
+
+v_cmp_tru_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_tru_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_tru_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9f,0x7c]
+
+v_cmpx_f_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa1,0x7c]
+
+v_cmpx_lt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa3,0x7c]
+
+v_cmpx_eq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa5,0x7c]
+
+v_cmpx_le_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa7,0x7c]
+
+v_cmpx_gt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa9,0x7c]
+
+v_cmpx_lg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xaa,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xaa,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xab,0x7c]
+
+v_cmpx_ge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xac,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xac,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xad,0x7c]
+
+v_cmpx_o_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xae,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xae,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_o_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xaf,0x7c]
+
+v_cmpx_u_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_u_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb1,0x7c]
+
+v_cmpx_nge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb3,0x7c]
+
+v_cmpx_nlg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb5,0x7c]
+
+v_cmpx_ngt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ngt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb7,0x7c]
+
+v_cmpx_nle_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nle_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb9,0x7c]
+
+v_cmpx_neq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xba,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xba,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_neq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbb,0x7c]
+
+v_cmpx_nlt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbd,0x7c]
+
+v_cmpx_tru_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbe,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_tru_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbe,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_tru_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbf,0x7c]
+
+v_cmp_f_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc1,0x7c]
+
+v_cmp_lt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc3,0x7c]
+
+v_cmp_eq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc5,0x7c]
+
+v_cmp_le_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc7,0x7c]
+
+v_cmp_gt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc9,0x7c]
+
+v_cmp_lg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcb,0x7c]
+
+v_cmp_ge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcd,0x7c]
+
+v_cmp_o_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xce,0x7c]
+
+v_cmp_o_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xce,0x7c]
+
+v_cmp_o_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_o_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_o_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcf,0x7c]
+
+v_cmp_u_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_u_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_u_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd1,0x7c]
+
+v_cmp_nge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd3,0x7c]
+
+v_cmp_nlg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd5,0x7c]
+
+v_cmp_ngt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ngt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ngt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd7,0x7c]
+
+v_cmp_nle_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nle_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nle_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd9,0x7c]
+
+v_cmp_neq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_neq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_neq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdb,0x7c]
+
+v_cmp_nlt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdd,0x7c]
+
+v_cmp_tru_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_tru_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_tru_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdf,0x7c]
+
+v_cmpx_f_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe1,0x7c]
+
+v_cmpx_lt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe3,0x7c]
+
+v_cmpx_eq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe5,0x7c]
+
+v_cmpx_le_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe7,0x7c]
+
+v_cmpx_gt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe9,0x7c]
+
+v_cmpx_lg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xeb,0x7c]
+
+v_cmpx_ge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xed,0x7c]
+
+v_cmpx_o_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_o_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xef,0x7c]
+
+v_cmpx_u_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_u_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf1,0x7c]
+
+v_cmpx_nge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf3,0x7c]
+
+v_cmpx_nlg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf5,0x7c]
+
+v_cmpx_ngt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ngt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf7,0x7c]
+
+v_cmpx_nle_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nle_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf9,0x7c]
+
+v_cmpx_neq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_neq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfb,0x7c]
+
+v_cmpx_nlt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfd,0x7c]
+
+v_cmpx_tru_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_tru_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_tru_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xff,0x7c]
+
+v_cmp_f_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x40,0x7d]
+
+v_cmp_f_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x40,0x7d]
+
+v_cmp_f_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x40,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_f_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x40,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_f_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x40,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_f_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x40,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_f_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x41,0x7d]
+
+v_cmp_lt_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x42,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_lt_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x42,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_lt_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x42,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lt_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x42,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_lt_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x43,0x7d]
+
+v_cmp_eq_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x44,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_eq_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x44,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_eq_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x44,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_eq_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x44,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_eq_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x45,0x7d]
+
+v_cmp_le_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x46,0x7d]
+
+v_cmp_le_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x46,0x7d]
+
+v_cmp_le_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x46,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_le_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x46,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_le_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x46,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_le_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x46,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_le_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x47,0x7d]
+
+v_cmp_gt_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x48,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_gt_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x48,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_gt_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x48,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_gt_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x48,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_gt_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x49,0x7d]
+
+v_cmp_ne_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x4a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_ne_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x4a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_ne_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ne_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_ne_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4b,0x7d]
+
+v_cmp_ge_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x4c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_ge_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x4c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_ge_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ge_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_ge_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4d,0x7d]
+
+v_cmp_t_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x4e,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_t_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x4e,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_t_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_t_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_t_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4f,0x7d]
+
+v_cmp_f_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x50,0x7d]
+
+v_cmp_f_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x50,0x7d]
+
+v_cmp_f_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_f_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_f_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_f_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_f_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x51,0x7d]
+
+v_cmp_lt_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x52,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_lt_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x52,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_lt_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x52,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lt_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x52,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_lt_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x53,0x7d]
+
+v_cmp_eq_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x54,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_eq_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x54,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_eq_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x54,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_eq_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x54,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_eq_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x55,0x7d]
+
+v_cmp_le_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x56,0x7d]
+
+v_cmp_le_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x56,0x7d]
+
+v_cmp_le_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x56,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_le_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x56,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_le_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x56,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_le_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x56,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_le_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x57,0x7d]
+
+v_cmp_gt_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x58,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_gt_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x58,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_gt_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x58,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_gt_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x58,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_gt_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x59,0x7d]
+
+v_cmp_ne_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x5a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_ne_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x5a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_ne_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ne_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_ne_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5b,0x7d]
+
+v_cmp_ge_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x5c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_ge_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x5c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_ge_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ge_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_ge_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5d,0x7d]
+
+v_cmp_t_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x5e,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_t_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x5e,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_t_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_t_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5e,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_t_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5f,0x7d]
+
+v_cmpx_f_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x60,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_f_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x60,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_f_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x60,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_f_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x60,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_f_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x61,0x7d]
+
+v_cmpx_lt_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x62,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x62,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_lt_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x62,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x62,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x63,0x7d]
+
+v_cmpx_eq_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x64,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x64,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x64,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x64,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_eq_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x65,0x7d]
+
+v_cmpx_le_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x66,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x66,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x66,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x66,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_le_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x67,0x7d]
+
+v_cmpx_gt_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x68,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x68,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x68,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x68,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_gt_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x69,0x7d]
+
+v_cmpx_ne_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x6a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x6a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ne_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6b,0x7d]
+
+v_cmpx_ge_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x6c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x6c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ge_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6d,0x7d]
+
+v_cmpx_t_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x6e,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_t_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x6e,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_t_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_t_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6e,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_t_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6f,0x7d]
+
+v_cmpx_f_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_f_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_f_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_f_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_f_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x71,0x7d]
+
+v_cmpx_lt_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x72,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x72,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_lt_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x72,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x72,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x73,0x7d]
+
+v_cmpx_eq_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x74,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x74,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x74,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x74,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_eq_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x75,0x7d]
+
+v_cmpx_le_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x76,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x76,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x76,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x76,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_le_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x77,0x7d]
+
+v_cmpx_gt_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x78,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x78,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x78,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x78,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_gt_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x79,0x7d]
+
+v_cmpx_ne_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x7a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x7a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ne_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7b,0x7d]
+
+v_cmpx_ge_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x7c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x7c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ge_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7d,0x7d]
+
+v_cmpx_t_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x7e,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_t_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x7e,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_t_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_t_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7e,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_t_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7f,0x7d]
+
+v_cmp_f_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x80,0x7d]
+
+v_cmp_f_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x80,0x7d]
+
+v_cmp_f_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x81,0x7d]
+
+v_cmp_lt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x83,0x7d]
+
+v_cmp_eq_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x85,0x7d]
+
+v_cmp_le_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x86,0x7d]
+
+v_cmp_le_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x86,0x7d]
+
+v_cmp_le_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x87,0x7d]
+
+v_cmp_gt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x89,0x7d]
+
+v_cmp_ne_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8b,0x7d]
+
+v_cmp_ge_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8d,0x7d]
+
+v_cmp_t_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8f,0x7d]
+
+v_cmp_f_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x90,0x7d]
+
+v_cmp_f_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x90,0x7d]
+
+v_cmp_f_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x90,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x90,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x91,0x7d]
+
+v_cmp_lt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x92,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x92,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x93,0x7d]
+
+v_cmp_eq_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x94,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x94,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x95,0x7d]
+
+v_cmp_le_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x96,0x7d]
+
+v_cmp_le_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x96,0x7d]
+
+v_cmp_le_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x96,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x96,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x97,0x7d]
+
+v_cmp_gt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x98,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x98,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x99,0x7d]
+
+v_cmp_ne_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9b,0x7d]
+
+v_cmp_ge_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9d,0x7d]
+
+v_cmp_t_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9f,0x7d]
+
+v_cmpx_f_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa1,0x7d]
+
+v_cmpx_lt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa3,0x7d]
+
+v_cmpx_eq_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa5,0x7d]
+
+v_cmpx_le_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa7,0x7d]
+
+v_cmpx_gt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa9,0x7d]
+
+v_cmpx_ne_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xaa,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xaa,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xab,0x7d]
+
+v_cmpx_ge_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xac,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xac,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xad,0x7d]
+
+v_cmpx_t_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xae,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xae,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xaf,0x7d]
+
+v_cmpx_f_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb1,0x7d]
+
+v_cmpx_lt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb3,0x7d]
+
+v_cmpx_eq_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb5,0x7d]
+
+v_cmpx_le_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb7,0x7d]
+
+v_cmpx_gt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb9,0x7d]
+
+v_cmpx_ne_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xba,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xba,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbb,0x7d]
+
+v_cmpx_ge_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbc,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbc,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbd,0x7d]
+
+v_cmpx_t_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, tba_lo, v2
+// CHECK: [0x6c,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, tba_hi, v2
+// CHECK: [0x6d,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, tma_lo, v2
+// CHECK: [0x6e,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, tma_hi, v2
+// CHECK: [0x6f,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, ttmp11, v2
+// CHECK: [0x7b,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbe,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbe,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbf,0x7d]
+
+v_cmp_f_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc1,0x7d]
+
+v_cmp_lt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc3,0x7d]
+
+v_cmp_eq_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc5,0x7d]
+
+v_cmp_le_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc7,0x7d]
+
+v_cmp_gt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc9,0x7d]
+
+v_cmp_ne_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcb,0x7d]
+
+v_cmp_ge_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcd,0x7d]
+
+v_cmp_t_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xce,0x7d]
+
+v_cmp_t_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xce,0x7d]
+
+v_cmp_t_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcf,0x7d]
+
+v_cmp_f_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd1,0x7d]
+
+v_cmp_lt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd3,0x7d]
+
+v_cmp_eq_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd5,0x7d]
+
+v_cmp_le_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd7,0x7d]
+
+v_cmp_gt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd9,0x7d]
+
+v_cmp_ne_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdb,0x7d]
+
+v_cmp_ge_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdd,0x7d]
+
+v_cmp_t_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xde,0x7d]
+
+v_cmp_t_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xde,0x7d]
+
+v_cmp_t_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdf,0x7d]
+
+v_cmpx_f_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe1,0x7d]
+
+v_cmpx_lt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe3,0x7d]
+
+v_cmpx_eq_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe5,0x7d]
+
+v_cmpx_le_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe7,0x7d]
+
+v_cmpx_gt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe9,0x7d]
+
+v_cmpx_ne_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xeb,0x7d]
+
+v_cmpx_ge_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xed,0x7d]
+
+v_cmpx_t_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xef,0x7d]
+
+v_cmpx_f_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf1,0x7d]
+
+v_cmpx_lt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf3,0x7d]
+
+v_cmpx_eq_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf5,0x7d]
+
+v_cmpx_le_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf7,0x7d]
+
+v_cmpx_gt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf9,0x7d]
+
+v_cmpx_ne_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfb,0x7d]
+
+v_cmpx_ge_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfd,0x7d]
+
+v_cmpx_t_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, tba, v[2:3]
+// CHECK: [0x6c,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, tma, v[2:3]
+// CHECK: [0x6e,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, ttmp[10:11], v[2:3]
+// CHECK: [0x7a,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xff,0x7d]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x21,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_class_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_class_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_class_f32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x0e]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x23,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_class_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_class_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_class_f32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x0e]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x29,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_class_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_class_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_class_f16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x0e]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x2b,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_class_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_class_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_class_f16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x0e]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x41,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_f_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_f_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_f_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_f_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x43,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_lt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_lt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_lt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_lt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x45,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_eq_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_eq_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_eq_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_eq_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x47,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_le_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_le_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_le_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_le_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x49,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_gt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_gt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_gt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_gt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4b,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_lg_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_lg_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_lg_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_lg_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4d,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_ge_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_ge_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_ge_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_ge_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4f,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_o_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_o_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_o_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_o_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x51,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_u_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_u_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_u_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_u_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x53,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_nge_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_nge_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_nge_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_nge_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x55,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_nlg_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_nlg_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x57,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_ngt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_ngt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x59,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_nle_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_nle_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_nle_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_nle_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5b,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_neq_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_neq_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_neq_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_neq_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5d,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_nlt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_nlt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5f,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_tru_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_tru_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_tru_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_tru_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x61,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_f_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_f_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x63,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_lt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x65,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_eq_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x67,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_le_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_le_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x69,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_gt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6b,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_lg_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_lg_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6d,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_ge_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6f,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_o_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_o_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_o_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_o_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x71,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_u_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_u_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_u_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_u_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x73,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nge_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nge_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x75,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x77,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x79,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nle_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nle_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7b,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_neq_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_neq_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7d,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7f,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_tru_f16_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_tru_f16_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x81,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_f_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_f_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_f_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_f_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x83,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_lt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_lt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_lt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_lt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x85,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_eq_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_eq_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_eq_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_eq_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x87,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_le_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_le_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_le_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_le_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x89,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_gt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_gt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_gt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_gt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8b,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_lg_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_lg_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_lg_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_lg_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8d,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_ge_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_ge_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_ge_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_ge_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8f,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_o_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_o_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_o_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_o_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x91,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_u_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_u_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_u_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_u_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x93,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_nge_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_nge_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_nge_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_nge_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x95,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_nlg_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_nlg_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x97,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_ngt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_ngt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x99,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_nle_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_nle_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_nle_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_nle_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9b,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_neq_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_neq_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_neq_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_neq_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9d,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_nlt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_nlt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9f,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmp_tru_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmp_tru_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmp_tru_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmp_tru_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa1,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_f_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_f_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa3,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_lt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa5,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_eq_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa7,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_le_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_le_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa9,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_gt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xab,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_lg_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_lg_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xad,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_ge_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xaf,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_o_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_o_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_o_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_o_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb1,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_u_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_u_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_u_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_u_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb3,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nge_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nge_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb5,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb7,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb9,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nle_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nle_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbb,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_neq_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_neq_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbd,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0xff,0x00,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbf,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 clamp src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x20,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x00,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x01,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x02,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x03,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x04,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x05,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x16,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x26,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x00]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x01]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x02]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x03]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x04]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x05]
+
+v_cmpx_tru_f32_sdwa vcc, v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x16]
+
+v_cmpx_tru_f32_sdwa vcc, v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x26]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x41,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_f_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_f_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x43,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_lt_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_lt_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x45,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_eq_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_eq_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x47,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_le_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_le_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x49,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_gt_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_gt_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4b,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_ne_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_ne_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4d,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_ge_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_ge_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4f,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_t_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_t_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x51,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_f_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_f_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x53,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_lt_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_lt_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x55,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_eq_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_eq_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x57,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_le_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_le_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x59,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_gt_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_gt_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5b,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_ne_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_ne_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5d,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_ge_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_ge_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5f,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_t_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_t_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x61,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x63,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x65,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x67,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x69,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6b,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ne_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6d,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6f,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_t_i16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_t_i16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x71,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x73,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x75,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x77,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x79,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7b,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ne_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7d,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7f,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_t_u16_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_t_u16_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x81,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_f_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_f_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x83,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_lt_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_lt_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x85,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_eq_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_eq_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x87,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_le_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_le_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x89,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_gt_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_gt_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8b,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_ne_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_ne_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8d,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_ge_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_ge_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8f,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_t_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_t_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x91,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_f_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_f_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x93,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_lt_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_lt_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x95,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_eq_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_eq_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x97,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_le_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_le_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x99,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_gt_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_gt_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9b,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_ne_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_ne_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9d,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_ge_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_ge_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9f,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmp_t_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmp_t_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa1,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa3,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa5,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa7,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa9,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xab,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ne_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xad,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xaf,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_t_i32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_t_i32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb1,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_f_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_f_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb3,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_lt_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb5,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_eq_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb7,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_le_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_le_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb9,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_gt_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbb,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ne_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbd,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_ge_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x0e]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0xff,0x00,0x06,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbf,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x00,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x01,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x02,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x03,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x04,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x05,0x06]
+
+v_cmpx_t_u32_sdwa vcc, sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x0e,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x00]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x01]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x02]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x03]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x04]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x05]
+
+v_cmpx_t_u32_sdwa vcc, v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x0e]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_all.s b/llvm/test/MC/AMDGPU/gfx9_asm_all.s
deleted file mode 100644
index 21ca46885e07f..0000000000000
--- a/llvm/test/MC/AMDGPU/gfx9_asm_all.s
+++ /dev/null
@@ -1,119325 +0,0 @@
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -mattr=+d16-preserves-unused-bits -show-encoding %s | FileCheck %s
-// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -mattr=+d16-preserves-unused-bits %s 2>&1 | FileCheck -check-prefix=CHECK-ERR --implicit-check-not=error: %s
-
-ds_add_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd8,0xff,0x02,0x00,0x00]
-
-ds_add_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd8,0x01,0xff,0x00,0x00]
-
-ds_add_u32 v1, v2
-// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x01,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd8,0xff,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd8,0x01,0xff,0x00,0x00]
-
-ds_sub_u32 v1, v2
-// CHECK: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x03,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd8,0xff,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd8,0x01,0xff,0x00,0x00]
-
-ds_rsub_u32 v1, v2
-// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x05,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd8,0xff,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd8,0x01,0xff,0x00,0x00]
-
-ds_inc_u32 v1, v2
-// CHECK: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x07,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
-
-ds_dec_u32 v1, v2
-// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x09,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_i32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0xff,0x00,0x00]
-
-ds_min_i32 v1, v2
-// CHECK: [0x00,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x0b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_i32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0xff,0x00,0x00]
-
-ds_max_i32 v1, v2
-// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x0d,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0xff,0x00,0x00]
-
-ds_min_u32 v1, v2
-// CHECK: [0x00,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x0f,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_u32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd8,0x01,0xff,0x00,0x00]
-
-ds_max_u32 v1, v2
-// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x11,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd8,0xff,0x02,0x00,0x00]
-
-ds_and_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd8,0x01,0xff,0x00,0x00]
-
-ds_and_b32 v1, v2
-// CHECK: [0x00,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x13,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd8,0xff,0x02,0x00,0x00]
-
-ds_or_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd8,0x01,0xff,0x00,0x00]
-
-ds_or_b32 v1, v2
-// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x15,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd8,0xff,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd8,0x01,0xff,0x00,0x00]
-
-ds_xor_b32 v1, v2
-// CHECK: [0x00,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x17,0xd8,0x01,0x02,0x00,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0xff,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0x01,0xff,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0xff,0x00]
-
-ds_mskor_b32 v1, v2, v3
-// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b32 v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x19,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write_b32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b32 v1, v2
-// CHECK: [0x00,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x1b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1c,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0xff,0x03,0x00]
-
-ds_write2_b32 v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0x02,0xff,0x00]
-
-ds_write2_b32 v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x1c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b32 v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x1d,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1e,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0xff,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0x02,0xff,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x1e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x1f,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0x01,0xff,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0xff,0x00]
-
-ds_cmpst_b32 v1, v2, v3
-// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b32 v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x21,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x22,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x22,0xd8,0x01,0xff,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0xff,0x00]
-
-ds_cmpst_f32 v1, v2, v3
-// CHECK: [0x00,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f32 v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x23,0xd8,0x01,0x02,0x03,0x00]
-
-ds_min_f32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_f32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd8,0x01,0xff,0x00,0x00]
-
-ds_min_f32 v1, v2
-// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x25,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_f32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd8,0x01,0xff,0x00,0x00]
-
-ds_max_f32 v1, v2
-// CHECK: [0x00,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x27,0xd8,0x01,0x02,0x00,0x00]
-
-ds_nop
-// CHECK: [0x00,0x00,0x28,0xd8,0x00,0x00,0x00,0x00]
-
-ds_add_f32 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_f32 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x2a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_add_f32 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0xff,0x00,0x00]
-
-ds_add_f32 v1, v2
-// CHECK: [0x00,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_f32 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_f32 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_f32 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x2b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x3c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x3c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b8 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x3c,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b8 v1, v2
-// CHECK: [0x00,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x3d,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x3e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x3e,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b16 v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x3e,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b16 v1, v2
-// CHECK: [0x00,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:0
-// CHECK: [0x00,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:4
-// CHECK: [0x04,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16 v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x3f,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,0xff]
-
-ds_add_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0xff,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x40,0xd8,0x01,0xff,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x41,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x00,0xff]
-
-ds_sub_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x42,0xd8,0xff,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x42,0xd8,0x01,0xff,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x43,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00,0xff]
-
-ds_rsub_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0xff,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x44,0xd8,0x01,0xff,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x45,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x00,0xff]
-
-ds_inc_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x46,0xd8,0xff,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x46,0xd8,0x01,0xff,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x47,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0xff]
-
-ds_dec_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0xff,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x48,0xd8,0x01,0xff,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x49,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_i32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x4a,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2
-// CHECK: [0x00,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x4b,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_i32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2
-// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x4d,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x4e,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x4f,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x50,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x50,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_u32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x50,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x50,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2
-// CHECK: [0x00,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x51,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x52,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x52,0xd8,0x01,0x02,0x00,0xff]
-
-ds_and_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x52,0xd8,0xff,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x52,0xd8,0x01,0xff,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x53,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x54,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x54,0xd8,0x01,0x02,0x00,0xff]
-
-ds_or_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x54,0xd8,0xff,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x54,0xd8,0x01,0xff,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x55,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x56,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x56,0xd8,0x01,0x02,0x00,0xff]
-
-ds_xor_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x56,0xd8,0xff,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x56,0xd8,0x01,0xff,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x57,0xd8,0x01,0x02,0x00,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0x03,0xff]
-
-ds_mskor_rtn_b32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0xff,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0x01,0xff,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0xff,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x59,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0x02,0x00,0xff]
-
-ds_wrxchg_rtn_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x5a,0xd8,0xff,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0xff,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x5b,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_wrxchg2_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x5c,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x5d,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset1:255
-// CHECK: [0x00,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127
-// CHECK: [0x7f,0x00,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x5e,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x5f,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0x03,0xff]
-
-ds_cmpst_rtn_b32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0x01,0xff,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0xff,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x61,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0x03,0xff]
-
-ds_cmpst_rtn_f32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0x01,0xff,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0xff,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x63,0xd8,0x01,0x02,0x03,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x64,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x64,0xd8,0x01,0x02,0x00,0xff]
-
-ds_min_rtn_f32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x64,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x64,0xd8,0x01,0xff,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2
-// CHECK: [0x00,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x65,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x02,0x00,0xff]
-
-ds_max_rtn_f32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x66,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x66,0xd8,0x01,0xff,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2
-// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x67,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0x03,0xff]
-
-ds_wrap_rtn_b32 v5, v255, v2, v3 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v255, v3 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0x01,0xff,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v255 offset:65535
-// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0xff,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3
-// CHECK: [0x00,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:0
-// CHECK: [0x00,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:4
-// CHECK: [0x04,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535 gds
-// CHECK: [0xff,0xff,0x69,0xd8,0x01,0x02,0x03,0x05]
-
-ds_add_rtn_f32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0x02,0x00,0xff]
-
-ds_add_rtn_f32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x6a,0xd8,0xff,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0xff,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v2
-// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_f32 v5, v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0x6b,0xd8,0x01,0x02,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x6c,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x6c,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_b32 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x6c,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1
-// CHECK: [0x00,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b32 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x6d,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x6e,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read2_b32 v[5:6], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x6e,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset1:255
-// CHECK: [0x00,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127
-// CHECK: [0x7f,0x00,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x6e,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x6f,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x70,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read2st64_b32 v[5:6], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x70,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset1:255
-// CHECK: [0x00,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127
-// CHECK: [0x7f,0x00,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x70,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x71,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x72,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x72,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i8 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x72,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1
-// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x73,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x74,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x74,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u8 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x74,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1
-// CHECK: [0x00,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x75,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i16 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x76,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1
-// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i16 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x77,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u16 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x78,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1
-// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x79,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0xff]
-
-ds_swizzle_b32 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd8,0xff,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1
-// CHECK: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:0
-// CHECK: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:4
-// CHECK: [0x04,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
-
-ds_swizzle_b32 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05]
-
-ds_permute_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_permute_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0xff]
-
-ds_permute_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0xff,0x02,0x00,0x05]
-
-ds_permute_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0xff,0x00,0x05]
-
-ds_permute_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_permute_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_permute_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_bpermute_b32 v255, v1, v2 offset:65535
-// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0xff]
-
-ds_bpermute_b32 v5, v255, v2 offset:65535
-// CHECK: [0xff,0xff,0x7e,0xd8,0xff,0x02,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v255 offset:65535
-// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0xff,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v2
-// CHECK: [0x00,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v2 offset:0
-// CHECK: [0x00,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_bpermute_b32 v5, v1, v2 offset:4
-// CHECK: [0x04,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0xff,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x80,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_add_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
-
-ds_add_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x81,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x82,0xd8,0xff,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x82,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
-
-ds_sub_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x83,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0xff,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x84,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
-
-ds_rsub_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x85,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x86,0xd8,0xff,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x86,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
-
-ds_inc_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x87,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0xff,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x88,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
-
-ds_dec_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x89,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_min_i64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_i64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x8b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_max_i64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_i64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x8d,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_min_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x8f,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x90,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_max_u64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_u64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x91,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x92,0xd8,0xff,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x92,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_and_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
-
-ds_and_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x93,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0xff,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x94,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_or_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
-
-ds_or_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x95,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x96,0xd8,0xff,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x96,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
-
-ds_xor_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x97,0xd8,0x01,0x02,0x00,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0xff,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
-
-ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0x99,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write_b64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_write_b64 v1, v[2:3]
-// CHECK: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0x9b,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9c,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x9c,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x9d,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9e,0xd8,0xff,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0x9e,0xd8,0x01,0x02,0x03,0x00]
-
-ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0x9f,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xa1,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa2,0xd8,0xff,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0xfe,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0xfe,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
-
-ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xa3,0xd8,0x01,0x02,0x03,0x00]
-
-ds_min_f64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0xff,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_min_f64 v1, v[2:3]
-// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
-
-ds_min_f64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xa5,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd8,0xff,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0xfe,0x00,0x00]
-
-ds_max_f64 v1, v[2:3]
-// CHECK: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
-
-ds_max_f64 v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xa7,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v255, v2 offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v255 offset:65535
-// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2
-// CHECK: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2 offset:0
-// CHECK: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2 offset:4
-// CHECK: [0x04,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b8_d16_hi v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0xa9,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2 offset:65535
-// CHECK: [0xff,0xff,0xaa,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v255, v2 offset:65535
-// CHECK: [0xff,0xff,0xaa,0xd8,0xff,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v255 offset:65535
-// CHECK: [0xff,0xff,0xaa,0xd8,0x01,0xff,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2
-// CHECK: [0x00,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2 offset:0
-// CHECK: [0x00,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2 offset:4
-// CHECK: [0x04,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
-
-ds_write_b16_d16_hi v1, v2 offset:65535 gds
-// CHECK: [0xff,0xff,0xab,0xd8,0x01,0x02,0x00,0x00]
-
-ds_read_u8_d16 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xac,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xac,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u8_d16 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xac,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u8_d16 v5, v1
-// CHECK: [0x00,0x00,0xac,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16 v5, v1 offset:0
-// CHECK: [0x00,0x00,0xac,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16 v5, v1 offset:4
-// CHECK: [0x04,0x00,0xac,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xad,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xae,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xae,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u8_d16_hi v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xae,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1
-// CHECK: [0x00,0x00,0xae,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1 offset:0
-// CHECK: [0x00,0x00,0xae,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1 offset:4
-// CHECK: [0x04,0x00,0xae,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u8_d16_hi v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xaf,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i8_d16 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xb0,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1
-// CHECK: [0x00,0x00,0xb0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1 offset:0
-// CHECK: [0x00,0x00,0xb0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1 offset:4
-// CHECK: [0x04,0x00,0xb0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xb1,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xb2,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xb2,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_i8_d16_hi v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xb2,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1
-// CHECK: [0x00,0x00,0xb2,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1 offset:0
-// CHECK: [0x00,0x00,0xb2,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1 offset:4
-// CHECK: [0x04,0x00,0xb2,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_i8_d16_hi v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xb3,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u16_d16 v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xb4,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1
-// CHECK: [0x00,0x00,0xb4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1 offset:0
-// CHECK: [0x00,0x00,0xb4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1 offset:4
-// CHECK: [0x04,0x00,0xb4,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16 v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xb5,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1 offset:65535
-// CHECK: [0xff,0xff,0xb6,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v255, v1 offset:65535
-// CHECK: [0xff,0xff,0xb6,0xd8,0x01,0x00,0x00,0xff]
-
-ds_read_u16_d16_hi v5, v255 offset:65535
-// CHECK: [0xff,0xff,0xb6,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1
-// CHECK: [0x00,0x00,0xb6,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1 offset:0
-// CHECK: [0x00,0x00,0xb6,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1 offset:4
-// CHECK: [0x04,0x00,0xb6,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_u16_d16_hi v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xb7,0xd8,0x01,0x00,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0xff,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc1,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_sub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc2,0xd8,0xff,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc3,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_rsub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0xff,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc5,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_inc_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc6,0xd8,0xff,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc7,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_dec_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0xff,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
-
-ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xc9,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_i64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xca,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xca,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xcb,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_i64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xcd,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xce,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xce,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xcf,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_u64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xd1,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_and_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd2,0xd8,0xff,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
-
-ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xd3,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_or_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0xff,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xd5,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_xor_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xd6,0xd8,0xff,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xd7,0xd8,0x01,0x02,0x00,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_mskor_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0xff,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
-
-ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xd9,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_wrxchg_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xda,0xd8,0xff,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xda,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xdb,0xd8,0x01,0x02,0x00,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0x03,0xfc]
-
-ds_wrxchg2_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xdc,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xdd,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0x03,0xfc]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0xff,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
-// CHECK: [0x00,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
-// CHECK: [0x7f,0x00,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xde,0xd8,0x01,0x02,0x03,0x05]
-
-ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xdf,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_cmpst_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xe1,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[254:255], v1, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0x03,0xfe]
-
-ds_cmpst_rtn_f64 v[5:6], v255, v[2:3], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0xff,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[254:255], v[3:4] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0xfe,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0xfe,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4]
-// CHECK: [0x00,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:0
-// CHECK: [0x00,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:4
-// CHECK: [0x04,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
-
-ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xe3,0xd8,0x01,0x02,0x03,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_min_rtn_f64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0xff,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
-
-ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xe5,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_max_rtn_f64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xe6,0xd8,0xff,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
-
-ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xe7,0xd8,0x01,0x02,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:65535
-// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[254:255], v1 offset:65535
-// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0xfe]
-
-ds_read_b64 v[5:6], v255 offset:65535
-// CHECK: [0xff,0xff,0xec,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1
-// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:0
-// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:4
-// CHECK: [0x04,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read_b64 v[5:6], v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xed,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xee,0xd8,0x01,0x00,0x00,0xfc]
-
-ds_read2_b64 v[5:8], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xee,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset1:255
-// CHECK: [0x00,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127
-// CHECK: [0x7f,0x00,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xee,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2_b64 v[5:8], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xef,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xf0,0xd8,0x01,0x00,0x00,0xfc]
-
-ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255
-// CHECK: [0x7f,0xff,0xf0,0xd8,0xff,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset1:255
-// CHECK: [0x00,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:0 offset1:255
-// CHECK: [0x00,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:16 offset1:255
-// CHECK: [0x10,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127
-// CHECK: [0x7f,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:0
-// CHECK: [0x7f,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:1
-// CHECK: [0x7f,0x01,0xf0,0xd8,0x01,0x00,0x00,0x05]
-
-ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255 gds
-// CHECK: [0x7f,0xff,0xf1,0xd8,0x01,0x00,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[254:255], v1, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0x02,0x00,0xfe]
-
-ds_condxchg32_rtn_b64 v[5:6], v255, v[2:3] offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd8,0xff,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0xfe,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:0
-// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:4
-// CHECK: [0x04,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
-
-ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
-// CHECK: [0xff,0xff,0xfd,0xd8,0x01,0x02,0x00,0x05]
-
-ds_add_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x00,0xd9,0xff,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1
-// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x01,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x02,0xd9,0xff,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1
-// CHECK: [0x00,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x03,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x04,0xd9,0xff,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1
-// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x05,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x06,0xd9,0xff,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1
-// CHECK: [0x00,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x07,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x08,0xd9,0xff,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1
-// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x09,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v255 offset:65535
-// CHECK: [0xff,0xff,0x0a,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1
-// CHECK: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:0
-// CHECK: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:4
-// CHECK: [0x04,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v255 offset:65535
-// CHECK: [0xff,0xff,0x0c,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1
-// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:0
-// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:4
-// CHECK: [0x04,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0d,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x0e,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1
-// CHECK: [0x00,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x0f,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v255 offset:65535
-// CHECK: [0xff,0xff,0x10,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1
-// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:0
-// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:4
-// CHECK: [0x04,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x11,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x12,0xd9,0xff,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1
-// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x13,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x14,0xd9,0xff,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1
-// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x15,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x16,0xd9,0xff,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1
-// CHECK: [0x00,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x17,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v255 offset:65535
-// CHECK: [0xff,0xff,0x1a,0xd9,0xff,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1
-// CHECK: [0x00,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:0
-// CHECK: [0x00,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:4
-// CHECK: [0x04,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x1b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v255 offset:65535
-// CHECK: [0xff,0xff,0x24,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1
-// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:0
-// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:4
-// CHECK: [0x04,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x25,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v255 offset:65535
-// CHECK: [0xff,0xff,0x26,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1
-// CHECK: [0x00,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:0
-// CHECK: [0x00,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:4
-// CHECK: [0x04,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f32 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x27,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:65535 gds
-// CHECK: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all gds
-// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:0 gds
-// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_release_all offset:4 gds
-// CHECK: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_init v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x33,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_init v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x33,0xd9,0xff,0x00,0x00,0x00]
-
-ds_gws_init v1 gds
-// CHECK: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_init v1 offset:0 gds
-// CHECK: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_init v1 offset:4 gds
-// CHECK: [0x04,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:65535 gds
-// CHECK: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v gds
-// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:0 gds
-// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_v offset:4 gds
-// CHECK: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x37,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_br v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x37,0xd9,0xff,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 gds
-// CHECK: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 offset:0 gds
-// CHECK: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_br v1 offset:4 gds
-// CHECK: [0x04,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:65535 gds
-// CHECK: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p gds
-// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:0 gds
-// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_sema_p offset:4 gds
-// CHECK: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
-
-ds_gws_barrier v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x3b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_barrier v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x3b,0xd9,0xff,0x00,0x00,0x00]
-
-ds_gws_barrier v1 gds
-// CHECK: [0x00,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_barrier v1 offset:0 gds
-// CHECK: [0x00,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_gws_barrier v1 offset:4 gds
-// CHECK: [0x04,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_consume v5 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0x05]
-
-ds_consume v255 offset:65535
-// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0xff]
-
-ds_consume v5
-// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:0
-// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:4
-// CHECK: [0x04,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
-
-ds_consume v5 offset:65535 gds
-// CHECK: [0xff,0xff,0x7b,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v255 offset:65535
-// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0xff]
-
-ds_append v5
-// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:0
-// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:4
-// CHECK: [0x04,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
-
-ds_append v5 offset:65535 gds
-// CHECK: [0xff,0xff,0x7d,0xd9,0x00,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x7f,0xd9,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v255, v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x7f,0xd9,0x01,0x00,0x00,0xff]
-
-ds_ordered_count v5, v255 offset:65535 gds
-// CHECK: [0xff,0xff,0x7f,0xd9,0xff,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 gds
-// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:0 gds
-// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
-
-ds_ordered_count v5, v1 offset:4 gds
-// CHECK: [0x04,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
-
-ds_add_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x80,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x80,0xd9,0xff,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1
-// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
-
-ds_add_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x81,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x82,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x82,0xd9,0xff,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1
-// CHECK: [0x00,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
-
-ds_sub_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x83,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x84,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x84,0xd9,0xff,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1
-// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
-
-ds_rsub_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x85,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x86,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x86,0xd9,0xff,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1
-// CHECK: [0x00,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
-
-ds_inc_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x87,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x88,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x88,0xd9,0xff,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1
-// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
-
-ds_dec_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x89,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v255 offset:65535
-// CHECK: [0xff,0xff,0x8a,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1
-// CHECK: [0x00,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:0
-// CHECK: [0x00,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:4
-// CHECK: [0x04,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_i64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x8b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v255 offset:65535
-// CHECK: [0xff,0xff,0x8c,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1
-// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:0
-// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:4
-// CHECK: [0x04,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_i64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x8d,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x8e,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1
-// CHECK: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x8f,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:65535
-// CHECK: [0xff,0xff,0x90,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v255 offset:65535
-// CHECK: [0xff,0xff,0x90,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1
-// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:0
-// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:4
-// CHECK: [0x04,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_u64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x91,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x92,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x92,0xd9,0xff,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1
-// CHECK: [0x00,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
-
-ds_and_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x93,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x94,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x94,0xd9,0xff,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1
-// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
-
-ds_or_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x95,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x96,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x96,0xd9,0xff,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1
-// CHECK: [0x00,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
-
-ds_xor_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x97,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v255 offset:65535
-// CHECK: [0xff,0xff,0x9a,0xd9,0xff,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1
-// CHECK: [0x00,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:0
-// CHECK: [0x00,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:4
-// CHECK: [0x04,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_src2_b64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0x9b,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v255 offset:65535
-// CHECK: [0xff,0xff,0xa4,0xd9,0xff,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1
-// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:0
-// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:4
-// CHECK: [0x04,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
-
-ds_min_src2_f64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xa5,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v255 offset:65535
-// CHECK: [0xff,0xff,0xa6,0xd9,0xff,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1
-// CHECK: [0x00,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:0
-// CHECK: [0x00,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:4
-// CHECK: [0x04,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
-
-ds_max_src2_f64 v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xa7,0xd9,0x01,0x00,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:65535
-// CHECK: [0xff,0xff,0xbc,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v255, v[2:4] offset:65535
-// CHECK: [0xff,0xff,0xbc,0xd9,0xff,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[253:255] offset:65535
-// CHECK: [0xff,0xff,0xbc,0xd9,0x01,0xfd,0x00,0x00]
-
-ds_write_b96 v1, v[2:4]
-// CHECK: [0x00,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:0
-// CHECK: [0x00,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:4
-// CHECK: [0x04,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b96 v1, v[2:4] offset:65535 gds
-// CHECK: [0xff,0xff,0xbd,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:65535
-// CHECK: [0xff,0xff,0xbe,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v255, v[2:5] offset:65535
-// CHECK: [0xff,0xff,0xbe,0xd9,0xff,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[252:255] offset:65535
-// CHECK: [0xff,0xff,0xbe,0xd9,0x01,0xfc,0x00,0x00]
-
-ds_write_b128 v1, v[2:5]
-// CHECK: [0x00,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:0
-// CHECK: [0x00,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:4
-// CHECK: [0x04,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
-
-ds_write_b128 v1, v[2:5] offset:65535 gds
-// CHECK: [0xff,0xff,0xbf,0xd9,0x01,0x02,0x00,0x00]
-
-ds_read_b96 v[5:7], v1 offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[253:255], v1 offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd9,0x01,0x00,0x00,0xfd]
-
-ds_read_b96 v[5:7], v255 offset:65535
-// CHECK: [0xff,0xff,0xfc,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1
-// CHECK: [0x00,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:0
-// CHECK: [0x00,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:4
-// CHECK: [0x04,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b96 v[5:7], v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xfd,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:65535
-// CHECK: [0xff,0xff,0xfe,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[252:255], v1 offset:65535
-// CHECK: [0xff,0xff,0xfe,0xd9,0x01,0x00,0x00,0xfc]
-
-ds_read_b128 v[5:8], v255 offset:65535
-// CHECK: [0xff,0xff,0xfe,0xd9,0xff,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1
-// CHECK: [0x00,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:0
-// CHECK: [0x00,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:4
-// CHECK: [0x04,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
-
-ds_read_b128 v[5:8], v1 offset:65535 gds
-// CHECK: [0xff,0xff,0xff,0xd9,0x01,0x00,0x00,0x05]
-
-exp mrt0 v0, v0, v0, v0
-// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrtz v0, v0, v0, v0
-// CHECK: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp null v0, v0, v0, v0
-// CHECK: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp pos0 v0, v0, v0, v0
-// CHECK: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp param0 v0, v0, v0, v0
-// CHECK: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v255, v0, v0, v0
-// CHECK: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00]
-
-exp mrt0 v0, v255, v0, v0
-// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00]
-
-exp mrt0 v0, v0, v255, v0
-// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00]
-
-exp mrt0 v0, v0, v0, v255
-// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff]
-
-exp mrt0 v0, off, off, off
-// CHECK: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, off, off
-// CHECK: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, off, off
-// CHECK: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, v0, off
-// CHECK: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, off, v0, off
-// CHECK: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, v0, off
-// CHECK: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, off
-// CHECK: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, off, v0
-// CHECK: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, off, off, v0
-// CHECK: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, off, v0
-// CHECK: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, off, v0
-// CHECK: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, v0, v0
-// CHECK: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, off, v0, v0
-// CHECK: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, v0, v0, v0
-// CHECK: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 off, off, off, off
-// CHECK: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, v0 done
-// CHECK: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, v0 compr
-// CHECK: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-exp mrt0 v0, v0, v0, v0 vm
-// CHECK: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00]
-
-flat_load_ubyte v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_ubyte v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x40,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_ubyte v5, v[1:2]
-// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x41,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x42,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x44,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x44,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_sbyte v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x44,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2]
-// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x44,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x45,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x46,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x48,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x48,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_ushort v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x48,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2]
-// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x48,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x49,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ushort v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x4a,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_sshort v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2]
-// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x4c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x4d,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sshort v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x4e,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x50,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x50,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_dword v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x50,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2]
-// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x50,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x51,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dword v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x52,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x54,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[254:255], v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x54,0xdc,0x01,0x00,0x00,0xfe]
-
-flat_load_dwordx2 v[5:6], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x54,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2]
-// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2] offset:0
-// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2] offset:7
-// CHECK: [0x07,0x00,0x54,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x55,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx2 v[5:6], v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x56,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x58,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[253:255], v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x58,0xdc,0x01,0x00,0x00,0xfd]
-
-flat_load_dwordx3 v[5:7], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x58,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2]
-// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2] offset:0
-// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2] offset:7
-// CHECK: [0x07,0x00,0x58,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x59,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx3 v[5:7], v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x5a,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[252:255], v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xdc,0x01,0x00,0x00,0xfc]
-
-flat_load_dwordx4 v[5:8], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2]
-// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2] offset:0
-// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2] offset:7
-// CHECK: [0x07,0x00,0x5c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x5d,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_dwordx4 v[5:8], v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x5e,0xdc,0x01,0x00,0x00,0x05]
-
-flat_store_byte v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_byte v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_byte v[1:2], v2
-// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x61,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x62,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte_d16_hi v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte_d16_hi v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_byte_d16_hi v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_byte_d16_hi v[1:2], v2
-// CHECK: [0x00,0x00,0x64,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte_d16_hi v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x64,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte_d16_hi v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x64,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte_d16_hi v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x65,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_byte_d16_hi v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x66,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_short v[1:2], v2
-// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x69,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x6a,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short_d16_hi v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short_d16_hi v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_short_d16_hi v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_short_d16_hi v[1:2], v2
-// CHECK: [0x00,0x00,0x6c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short_d16_hi v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x6c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short_d16_hi v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x6c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short_d16_hi v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x6d,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_short_d16_hi v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x6e,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xdc,0x01,0xff,0x00,0x00]
-
-flat_store_dword v[1:2], v2
-// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x71,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dword v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x72,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x74,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x74,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x74,0xdc,0x01,0xfe,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0x75,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0x76,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4] offset:4095
-// CHECK: [0xff,0x0f,0x78,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[254:255], v[2:4] offset:4095
-// CHECK: [0xff,0x0f,0x78,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[253:255] offset:4095
-// CHECK: [0xff,0x0f,0x78,0xdc,0x01,0xfd,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4]
-// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4] offset:0
-// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4] offset:7
-// CHECK: [0x07,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4] offset:4095 glc
-// CHECK: [0xff,0x0f,0x79,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx3 v[1:2], v[2:4] offset:4095 slc
-// CHECK: [0xff,0x0f,0x7a,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5] offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[254:255], v[2:5] offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xdc,0xfe,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[252:255] offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xdc,0x01,0xfc,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5]
-// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5] offset:0
-// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5] offset:7
-// CHECK: [0x07,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5] offset:4095 glc
-// CHECK: [0xff,0x0f,0x7d,0xdc,0x01,0x02,0x00,0x00]
-
-flat_store_dwordx4 v[1:2], v[2:5] offset:4095 slc
-// CHECK: [0xff,0x0f,0x7e,0xdc,0x01,0x02,0x00,0x00]
-
-flat_load_ubyte_d16 v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x80,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16 v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x80,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_ubyte_d16 v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x80,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_ubyte_d16 v5, v[1:2]
-// CHECK: [0x00,0x00,0x80,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16 v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x80,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16 v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x80,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16 v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x81,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16 v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x82,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16_hi v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x84,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16_hi v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x84,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_ubyte_d16_hi v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x84,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_ubyte_d16_hi v5, v[1:2]
-// CHECK: [0x00,0x00,0x84,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16_hi v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x84,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16_hi v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x84,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16_hi v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x85,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_ubyte_d16_hi v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x86,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16 v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x88,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16 v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x88,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_sbyte_d16 v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x88,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_sbyte_d16 v5, v[1:2]
-// CHECK: [0x00,0x00,0x88,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16 v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x88,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16 v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x88,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16 v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x89,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16 v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x8a,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16_hi v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16_hi v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_sbyte_d16_hi v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_sbyte_d16_hi v5, v[1:2]
-// CHECK: [0x00,0x00,0x8c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16_hi v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x8c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16_hi v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x8c,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16_hi v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x8d,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_sbyte_d16_hi v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x8e,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16 v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x90,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16 v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x90,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_short_d16 v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x90,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_short_d16 v5, v[1:2]
-// CHECK: [0x00,0x00,0x90,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16 v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x90,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16 v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x90,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16 v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x91,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16 v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x92,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16_hi v5, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x94,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16_hi v255, v[1:2] offset:4095
-// CHECK: [0xff,0x0f,0x94,0xdc,0x01,0x00,0x00,0xff]
-
-flat_load_short_d16_hi v5, v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x94,0xdc,0xfe,0x00,0x00,0x05]
-
-flat_load_short_d16_hi v5, v[1:2]
-// CHECK: [0x00,0x00,0x94,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16_hi v5, v[1:2] offset:0
-// CHECK: [0x00,0x00,0x94,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16_hi v5, v[1:2] offset:7
-// CHECK: [0x07,0x00,0x94,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16_hi v5, v[1:2] offset:4095 glc
-// CHECK: [0xff,0x0f,0x95,0xdc,0x01,0x00,0x00,0x05]
-
-flat_load_short_d16_hi v5, v[1:2] offset:4095 slc
-// CHECK: [0xff,0x0f,0x96,0xdc,0x01,0x00,0x00,0x05]
-
-flat_atomic_swap v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_swap v[1:2], v2
-// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x01,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x02,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x04,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x04,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x04,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x04,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0x04,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0x04,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v0, v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0x05,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0x06,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_add v[1:2], v2
-// CHECK: [0x00,0x00,0x08,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x08,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x08,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x09,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_sub v[1:2], v2
-// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x0c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x0d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_smin v[1:2], v2
-// CHECK: [0x00,0x00,0x10,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x10,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x10,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x11,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x12,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_umin v[1:2], v2
-// CHECK: [0x00,0x00,0x14,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x14,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x14,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x15,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x16,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_smax v[1:2], v2
-// CHECK: [0x00,0x00,0x18,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x18,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x18,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x19,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_umax v[1:2], v2
-// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x1c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x1d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_and v[1:2], v2
-// CHECK: [0x00,0x00,0x20,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x20,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x20,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x21,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x22,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_or v[1:2], v2
-// CHECK: [0x00,0x00,0x24,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x24,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x24,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x25,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x26,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_xor v[1:2], v2
-// CHECK: [0x00,0x00,0x28,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x28,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x28,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x29,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_inc v[1:2], v2
-// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x2c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x2d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v2 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[254:255], v2 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v255 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xdd,0x01,0xff,0x00,0x00]
-
-flat_atomic_dec v[1:2], v2
-// CHECK: [0x00,0x00,0x30,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v2 offset:0
-// CHECK: [0x00,0x00,0x30,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v2 offset:7
-// CHECK: [0x07,0x00,0x30,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v0, v[1:2], v2 offset:4095 glc
-// CHECK: [0xff,0x0f,0x31,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec v[1:2], v2 offset:4095 slc
-// CHECK: [0xff,0x0f,0x32,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x80,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x80,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x80,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0x81,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_swap_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0x82,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5] offset:4095
-// CHECK: [0xff,0x0f,0x84,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[254:255], v[2:5] offset:4095
-// CHECK: [0xff,0x0f,0x84,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[252:255] offset:4095
-// CHECK: [0xff,0x0f,0x84,0xdd,0x01,0xfc,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5]
-// CHECK: [0x00,0x00,0x84,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5] offset:0
-// CHECK: [0x00,0x00,0x84,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5] offset:7
-// CHECK: [0x07,0x00,0x84,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[0:1], v[1:2], v[2:5] offset:4095 glc
-// CHECK: [0xff,0x0f,0x85,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_cmpswap_x2 v[1:2], v[2:5] offset:4095 slc
-// CHECK: [0xff,0x0f,0x86,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x88,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x88,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x88,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x88,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0x88,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0x88,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0x89,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_add_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0x8a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0x8c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0x8d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_sub_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0x8e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x90,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x90,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x90,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x90,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0x90,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0x90,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0x91,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smin_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0x92,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x94,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x94,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x94,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x94,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0x94,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0x94,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0x95,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umin_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0x96,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x98,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x98,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x98,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x98,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0x98,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0x98,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0x99,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_smax_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0x9a,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0x9c,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0x9d,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_umax_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0x9e,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0xa0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0xa1,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_and_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0xa2,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0xa4,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0xa5,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_or_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0xa6,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0xa8,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0xa9,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_xor_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0xaa,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xac,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xac,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0xac,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xac,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0xac,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0xac,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0xad,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_inc_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0xae,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[254:255], v[2:3] offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xdd,0xfe,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[254:255] offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xdd,0x01,0xfe,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3]
-// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3] offset:0
-// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3] offset:7
-// CHECK: [0x07,0x00,0xb0,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
-// CHECK: [0xff,0x0f,0xb1,0xdd,0x01,0x02,0x00,0x00]
-
-flat_atomic_dec_x2 v[1:2], v[2:3] offset:4095 slc
-// CHECK: [0xff,0x0f,0xb2,0xdd,0x01,0x02,0x00,0x00]
-
-global_load_ubyte v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_ubyte v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_ubyte v5, v[1:2], off
-// CHECK: [0x00,0x80,0x40,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_sbyte v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_sbyte v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_sbyte v5, v[1:2], off
-// CHECK: [0x00,0x80,0x44,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_ushort v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_ushort v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_ushort v5, v[1:2], off
-// CHECK: [0x00,0x80,0x48,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_sshort v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_sshort v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_sshort v5, v[1:2], off
-// CHECK: [0x00,0x80,0x4c,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_dword v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_dword v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_dword v5, v[1:2], off
-// CHECK: [0x00,0x80,0x50,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_dwordx2 v[5:6], v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_dwordx2 v[254:255], v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x7f,0xfe]
-
-global_load_dwordx2 v[5:6], v[1:2], off
-// CHECK: [0x00,0x80,0x54,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_dwordx3 v[5:7], v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_dwordx3 v[253:255], v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x7f,0xfd]
-
-global_load_dwordx3 v[5:7], v[1:2], off
-// CHECK: [0x00,0x80,0x58,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_dwordx4 v[5:8], v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_dwordx4 v[252:255], v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x7f,0xfc]
-
-global_load_dwordx4 v[5:8], v[1:2], off
-// CHECK: [0x00,0x80,0x5c,0xdc,0x01,0x00,0x7f,0x05]
-
-global_store_byte v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_byte v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0xff,0x7f,0x00]
-
-global_store_byte v[1:2], v2, off
-// CHECK: [0x00,0x80,0x60,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_byte_d16_hi v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_byte_d16_hi v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0xff,0x7f,0x00]
-
-global_store_byte_d16_hi v[1:2], v2, off
-// CHECK: [0x00,0x80,0x64,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_short v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_short v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0xff,0x7f,0x00]
-
-global_store_short v[1:2], v2, off
-// CHECK: [0x00,0x80,0x68,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_short_d16_hi v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_short_d16_hi v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0xff,0x7f,0x00]
-
-global_store_short_d16_hi v[1:2], v2, off
-// CHECK: [0x00,0x80,0x6c,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_dword v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_dword v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0xff,0x7f,0x00]
-
-global_store_dword v[1:2], v2, off
-// CHECK: [0x00,0x80,0x70,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_dwordx2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_dwordx2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0xfe,0x7f,0x00]
-
-global_store_dwordx2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0x74,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_dwordx3 v[1:2], v[2:4], off offset:-1
-// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_dwordx3 v[1:2], v[253:255], off offset:-1
-// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0xfd,0x7f,0x00]
-
-global_store_dwordx3 v[1:2], v[2:4], off
-// CHECK: [0x00,0x80,0x78,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_dwordx4 v[1:2], v[2:5], off offset:-1
-// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0x02,0x7f,0x00]
-
-global_store_dwordx4 v[1:2], v[252:255], off offset:-1
-// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0xfc,0x7f,0x00]
-
-global_store_dwordx4 v[1:2], v[2:5], off
-// CHECK: [0x00,0x80,0x7c,0xdc,0x01,0x02,0x7f,0x00]
-
-global_load_ubyte_d16 v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_ubyte_d16 v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_ubyte_d16 v5, v[1:2], off
-// CHECK: [0x00,0x80,0x80,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_ubyte_d16_hi v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_ubyte_d16_hi v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_ubyte_d16_hi v5, v[1:2], off
-// CHECK: [0x00,0x80,0x84,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_sbyte_d16 v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_sbyte_d16 v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_sbyte_d16 v5, v[1:2], off
-// CHECK: [0x00,0x80,0x88,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_sbyte_d16_hi v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_sbyte_d16_hi v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_sbyte_d16_hi v5, v[1:2], off
-// CHECK: [0x00,0x80,0x8c,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_short_d16 v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_short_d16 v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_short_d16 v5, v[1:2], off
-// CHECK: [0x00,0x80,0x90,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_short_d16_hi v5, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x7f,0x05]
-
-global_load_short_d16_hi v255, v[1:2], off offset:-1
-// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x7f,0xff]
-
-global_load_short_d16_hi v5, v[1:2], off
-// CHECK: [0x00,0x80,0x94,0xdc,0x01,0x00,0x7f,0x05]
-
-global_atomic_swap v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_swap v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_swap v[1:2], v2, off
-// CHECK: [0x00,0x80,0x00,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_cmpswap v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_cmpswap v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_cmpswap v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0x04,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_cmpswap v1, v[2:3], v[4:5], off offset:-1 glc
-// CHECK: [0xff,0x9f,0x05,0xdd,0x02,0x04,0x7f,0x01]
-
-global_atomic_cmpswap v1, v[2:3], v[254:255], off offset:-1 glc
-// CHECK: [0xff,0x9f,0x05,0xdd,0x02,0xfe,0x7f,0x01]
-
-global_atomic_cmpswap v1, v2, v[4:5], s[2:3] offset:-1 glc
-// CHECK: [0xff,0x9f,0x05,0xdd,0x02,0x04,0x02,0x01]
-
-global_atomic_cmpswap v1, v[2:3], v[4:5], off glc
-// CHECK:  [0x00,0x80,0x05,0xdd,0x02,0x04,0x7f,0x01]
-
-global_atomic_add v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_add v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_add v[1:2], v2, off
-// CHECK: [0x00,0x80,0x08,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_sub v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_sub v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_sub v[1:2], v2, off
-// CHECK: [0x00,0x80,0x0c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_smin v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_smin v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_smin v[1:2], v2, off
-// CHECK: [0x00,0x80,0x10,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_umin v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_umin v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_umin v[1:2], v2, off
-// CHECK: [0x00,0x80,0x14,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_smax v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_smax v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_smax v[1:2], v2, off
-// CHECK: [0x00,0x80,0x18,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_umax v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_umax v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_umax v[1:2], v2, off
-// CHECK: [0x00,0x80,0x1c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_and v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_and v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_and v[1:2], v2, off
-// CHECK: [0x00,0x80,0x20,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_or v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_or v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_or v[1:2], v2, off
-// CHECK: [0x00,0x80,0x24,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_xor v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_xor v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_xor v[1:2], v2, off
-// CHECK: [0x00,0x80,0x28,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_inc v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_inc v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_inc v[1:2], v2, off
-// CHECK: [0x00,0x80,0x2c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_dec v[1:2], v2, off offset:-1
-// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_dec v[1:2], v255, off offset:-1
-// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0xff,0x7f,0x00]
-
-global_atomic_dec v[1:2], v2, off
-// CHECK: [0x00,0x80,0x30,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_swap_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_swap_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_swap_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0x80,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_cmpswap_x2 v[1:2], v[2:5], off offset:-1
-// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_cmpswap_x2 v[1:2], v[252:255], off offset:-1
-// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0xfc,0x7f,0x00]
-
-global_atomic_cmpswap_x2 v[1:2], v[2:5], off
-// CHECK: [0x00,0x80,0x84,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off offset:-1 glc
-// CHECK: [0xff,0x9f,0x85,0xdd,0x05,0x07,0x7f,0x01]
-
-global_atomic_cmpswap_x2 v[1:2], v[5:6], v[252:255], off offset:-1 glc
-// CHECK: [0xff,0x9f,0x85,0xdd,0x05,0xfc,0x7f,0x01]
-
-global_atomic_cmpswap_x2 v[1:2], v5, v[252:255], s[2:3] offset:-1 glc
-// CHECK: [0xff,0x9f,0x85,0xdd,0x05,0xfc,0x02,0x01]
-
-global_atomic_cmpswap_x2 v[1:2], v[5:6], v[7:10], off glc
-// CHECK: [0x00,0x80,0x85,0xdd,0x05,0x07,0x7f,0x01]
-
-global_atomic_add_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_add_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_add_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0x88,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_sub_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_sub_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_sub_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0x8c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_smin_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_smin_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_smin_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0x90,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_umin_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_umin_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_umin_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0x94,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_smax_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_smax_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_smax_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0x98,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_umax_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_umax_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_umax_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0x9c,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_and_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_and_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_and_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0xa0,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_or_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_or_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_or_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0xa4,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_xor_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_xor_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_xor_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0xa8,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_inc_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_inc_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_inc_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0xac,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_dec_x2 v[1:2], v[2:3], off offset:-1
-// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0x02,0x7f,0x00]
-
-global_atomic_dec_x2 v[1:2], v[254:255], off offset:-1
-// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0xfe,0x7f,0x00]
-
-global_atomic_dec_x2 v[1:2], v[2:3], off
-// CHECK: [0x00,0x80,0xb0,0xdd,0x01,0x02,0x7f,0x00]
-
-scratch_load_ubyte v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_ubyte v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_ubyte v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_ubyte v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_ubyte v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_ubyte v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_ubyte v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_ubyte v5, off, s2
-// CHECK: [0x00,0x40,0x40,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x40,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x40,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x40,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x41,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x42,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_sbyte v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_sbyte v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_sbyte v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_sbyte v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_sbyte v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_sbyte v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_sbyte v5, off, s2
-// CHECK: [0x00,0x40,0x44,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x44,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x44,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x44,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x45,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x46,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ushort v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ushort v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_ushort v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_ushort v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_ushort v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_ushort v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_ushort v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_ushort v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_ushort v5, off, s2
-// CHECK: [0x00,0x40,0x48,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ushort v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x48,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ushort v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x48,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ushort v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x48,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ushort v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x49,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ushort v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x4a,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sshort v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sshort v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_sshort v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_sshort v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_sshort v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_sshort v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_sshort v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_sshort v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_sshort v5, off, s2
-// CHECK: [0x00,0x40,0x4c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sshort v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x4c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sshort v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x4c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sshort v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x4c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sshort v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x4d,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sshort v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x4e,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dword v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dword v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_dword v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_dword v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_dword v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_dword v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_dword v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_dword v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_dword v5, off, s2
-// CHECK: [0x00,0x40,0x50,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dword v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x50,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dword v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x50,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dword v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x50,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dword v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x51,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dword v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x52,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx2 v[5:6], off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx2 v[254:255], off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x02,0xfe]
-
-scratch_load_dwordx2 v[5:6], off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_dwordx2 v[5:6], off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_dwordx2 v[5:6], off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_dwordx2 v[5:6], off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_dwordx2 v[5:6], off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_dwordx2 v[5:6], v0, off offset:-1
-// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_dwordx2 v[5:6], off, s2
-// CHECK: [0x00,0x40,0x54,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx2 v[5:6], off, s2 offset:0
-// CHECK: [0x00,0x40,0x54,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx2 v[5:6], off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x54,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx2 v[5:6], off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x54,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx2 v[5:6], off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x55,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx2 v[5:6], off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x56,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx3 v[5:7], off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx3 v[253:255], off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x02,0xfd]
-
-scratch_load_dwordx3 v[5:7], off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_dwordx3 v[5:7], off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_dwordx3 v[5:7], off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_dwordx3 v[5:7], off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_dwordx3 v[5:7], off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_dwordx3 v[5:7], v0, off offset:-1
-// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_dwordx3 v[5:7], off, s2
-// CHECK: [0x00,0x40,0x58,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx3 v[5:7], off, s2 offset:0
-// CHECK: [0x00,0x40,0x58,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx3 v[5:7], off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x58,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx3 v[5:7], off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x58,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx3 v[5:7], off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x59,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx3 v[5:7], off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x5a,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx4 v[5:8], off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx4 v[252:255], off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x02,0xfc]
-
-scratch_load_dwordx4 v[5:8], off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_dwordx4 v[5:8], off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_dwordx4 v[5:8], off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_dwordx4 v[5:8], off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_dwordx4 v[5:8], off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_dwordx4 v[5:8], v0, off offset:-1
-// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_dwordx4 v[5:8], off, s2
-// CHECK: [0x00,0x40,0x5c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx4 v[5:8], off, s2 offset:0
-// CHECK: [0x00,0x40,0x5c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx4 v[5:8], off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x5c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx4 v[5:8], off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x5c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx4 v[5:8], off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x5d,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_dwordx4 v[5:8], off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x5e,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_store_byte off, v2, s3 offset:-1
-// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte off, v255, s3 offset:-1
-// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0xff,0x03,0x00]
-
-scratch_store_byte off, v2, s101 offset:-1
-// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x65,0x00]
-
-scratch_store_byte off, v2, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x66,0x00]
-
-scratch_store_byte off, v2, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x67,0x00]
-
-scratch_store_byte off, v2, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x6a,0x00]
-
-scratch_store_byte off, v2, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x6b,0x00]
-
-scratch_store_byte v0, v2, off offset:-1
-// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x7f,0x00]
-
-scratch_store_byte off, v2, s3
-// CHECK: [0x00,0x40,0x60,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte off, v2, s3 offset:0
-// CHECK: [0x00,0x40,0x60,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte off, v2, s3 offset:4095
-// CHECK: [0xff,0x4f,0x60,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte off, v2, s3 offset:-4096
-// CHECK: [0x00,0x50,0x60,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte off, v2, s3 offset:-1 glc
-// CHECK: [0xff,0x5f,0x61,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte off, v2, s3 offset:-1 slc
-// CHECK: [0xff,0x5f,0x62,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte_d16_hi off, v2, s3 offset:-1
-// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte_d16_hi off, v255, s3 offset:-1
-// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0xff,0x03,0x00]
-
-scratch_store_byte_d16_hi off, v2, s101 offset:-1
-// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x65,0x00]
-
-scratch_store_byte_d16_hi off, v2, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x66,0x00]
-
-scratch_store_byte_d16_hi off, v2, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x67,0x00]
-
-scratch_store_byte_d16_hi off, v2, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x6a,0x00]
-
-scratch_store_byte_d16_hi off, v2, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x6b,0x00]
-
-scratch_store_byte_d16_hi v0, v2, off offset:-1
-// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x7f,0x00]
-
-scratch_store_byte_d16_hi off, v2, s3
-// CHECK: [0x00,0x40,0x64,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte_d16_hi off, v2, s3 offset:0
-// CHECK: [0x00,0x40,0x64,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte_d16_hi off, v2, s3 offset:4095
-// CHECK: [0xff,0x4f,0x64,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte_d16_hi off, v2, s3 offset:-4096
-// CHECK: [0x00,0x50,0x64,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte_d16_hi off, v2, s3 offset:-1 glc
-// CHECK: [0xff,0x5f,0x65,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_byte_d16_hi off, v2, s3 offset:-1 slc
-// CHECK: [0xff,0x5f,0x66,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short off, v2, s3 offset:-1
-// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short off, v255, s3 offset:-1
-// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0xff,0x03,0x00]
-
-scratch_store_short off, v2, s101 offset:-1
-// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x65,0x00]
-
-scratch_store_short off, v2, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x66,0x00]
-
-scratch_store_short off, v2, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x67,0x00]
-
-scratch_store_short off, v2, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x6a,0x00]
-
-scratch_store_short off, v2, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x6b,0x00]
-
-scratch_store_short v0, v2, off offset:-1
-// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x7f,0x00]
-
-scratch_store_short off, v2, s3
-// CHECK: [0x00,0x40,0x68,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short off, v2, s3 offset:0
-// CHECK: [0x00,0x40,0x68,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short off, v2, s3 offset:4095
-// CHECK: [0xff,0x4f,0x68,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short off, v2, s3 offset:-4096
-// CHECK: [0x00,0x50,0x68,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short off, v2, s3 offset:-1 glc
-// CHECK: [0xff,0x5f,0x69,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short off, v2, s3 offset:-1 slc
-// CHECK: [0xff,0x5f,0x6a,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short_d16_hi off, v2, s3 offset:-1
-// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short_d16_hi off, v255, s3 offset:-1
-// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0xff,0x03,0x00]
-
-scratch_store_short_d16_hi off, v2, s101 offset:-1
-// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x65,0x00]
-
-scratch_store_short_d16_hi off, v2, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x66,0x00]
-
-scratch_store_short_d16_hi off, v2, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x67,0x00]
-
-scratch_store_short_d16_hi off, v2, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x6a,0x00]
-
-scratch_store_short_d16_hi off, v2, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x6b,0x00]
-
-scratch_store_short_d16_hi v0, v2, off offset:-1
-// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x7f,0x00]
-
-scratch_store_short_d16_hi off, v2, s3
-// CHECK: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short_d16_hi off, v2, s3 offset:0
-// CHECK: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short_d16_hi off, v2, s3 offset:4095
-// CHECK: [0xff,0x4f,0x6c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short_d16_hi off, v2, s3 offset:-4096
-// CHECK: [0x00,0x50,0x6c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short_d16_hi off, v2, s3 offset:-1 glc
-// CHECK: [0xff,0x5f,0x6d,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_short_d16_hi off, v2, s3 offset:-1 slc
-// CHECK: [0xff,0x5f,0x6e,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dword off, v2, s3 offset:-1
-// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dword off, v255, s3 offset:-1
-// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0xff,0x03,0x00]
-
-scratch_store_dword off, v2, s101 offset:-1
-// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x65,0x00]
-
-scratch_store_dword off, v2, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x66,0x00]
-
-scratch_store_dword off, v2, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x67,0x00]
-
-scratch_store_dword off, v2, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x6a,0x00]
-
-scratch_store_dword off, v2, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x6b,0x00]
-
-scratch_store_dword v0, v2, off offset:-1
-// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x7f,0x00]
-
-scratch_store_dword off, v2, s3
-// CHECK: [0x00,0x40,0x70,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dword off, v2, s3 offset:0
-// CHECK: [0x00,0x40,0x70,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dword off, v2, s3 offset:4095
-// CHECK: [0xff,0x4f,0x70,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dword off, v2, s3 offset:-4096
-// CHECK: [0x00,0x50,0x70,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dword off, v2, s3 offset:-1 glc
-// CHECK: [0xff,0x5f,0x71,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dword off, v2, s3 offset:-1 slc
-// CHECK: [0xff,0x5f,0x72,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx2 off, v[2:3], s3 offset:-1
-// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx2 off, v[254:255], s3 offset:-1
-// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0xfe,0x03,0x00]
-
-scratch_store_dwordx2 off, v[2:3], s101 offset:-1
-// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x65,0x00]
-
-scratch_store_dwordx2 off, v[2:3], flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x66,0x00]
-
-scratch_store_dwordx2 off, v[2:3], flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x67,0x00]
-
-scratch_store_dwordx2 off, v[2:3], vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x6a,0x00]
-
-scratch_store_dwordx2 off, v[2:3], vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x6b,0x00]
-
-scratch_store_dwordx2 v0, v[2:3], off offset:-1
-// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x7f,0x00]
-
-scratch_store_dwordx2 off, v[2:3], s3
-// CHECK: [0x00,0x40,0x74,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx2 off, v[2:3], s3 offset:0
-// CHECK: [0x00,0x40,0x74,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx2 off, v[2:3], s3 offset:4095
-// CHECK: [0xff,0x4f,0x74,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx2 off, v[2:3], s3 offset:-4096
-// CHECK: [0x00,0x50,0x74,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx2 off, v[2:3], s3 offset:-1 glc
-// CHECK: [0xff,0x5f,0x75,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx2 off, v[2:3], s3 offset:-1 slc
-// CHECK: [0xff,0x5f,0x76,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx3 off, v[2:4], s3 offset:-1
-// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx3 off, v[253:255], s3 offset:-1
-// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0xfd,0x03,0x00]
-
-scratch_store_dwordx3 off, v[2:4], s101 offset:-1
-// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x65,0x00]
-
-scratch_store_dwordx3 off, v[2:4], flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x66,0x00]
-
-scratch_store_dwordx3 off, v[2:4], flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x67,0x00]
-
-scratch_store_dwordx3 off, v[2:4], vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x6a,0x00]
-
-scratch_store_dwordx3 off, v[2:4], vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x6b,0x00]
-
-scratch_store_dwordx3 v0, v[2:4], off offset:-1
-// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x7f,0x00]
-
-scratch_store_dwordx3 off, v[2:4], s3
-// CHECK: [0x00,0x40,0x78,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx3 off, v[2:4], s3 offset:0
-// CHECK: [0x00,0x40,0x78,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx3 off, v[2:4], s3 offset:4095
-// CHECK: [0xff,0x4f,0x78,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx3 off, v[2:4], s3 offset:-4096
-// CHECK: [0x00,0x50,0x78,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx3 off, v[2:4], s3 offset:-1 glc
-// CHECK: [0xff,0x5f,0x79,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx3 off, v[2:4], s3 offset:-1 slc
-// CHECK: [0xff,0x5f,0x7a,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx4 off, v[2:5], s3 offset:-1
-// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx4 off, v[252:255], s3 offset:-1
-// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0xfc,0x03,0x00]
-
-scratch_store_dwordx4 off, v[2:5], s101 offset:-1
-// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x65,0x00]
-
-scratch_store_dwordx4 off, v[2:5], flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x66,0x00]
-
-scratch_store_dwordx4 off, v[2:5], flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x67,0x00]
-
-scratch_store_dwordx4 off, v[2:5], vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x6a,0x00]
-
-scratch_store_dwordx4 off, v[2:5], vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x6b,0x00]
-
-scratch_store_dwordx4 v0, v[2:5], off offset:-1
-// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x7f,0x00]
-
-scratch_store_dwordx4 off, v[2:5], s3
-// CHECK: [0x00,0x40,0x7c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx4 off, v[2:5], s3 offset:0
-// CHECK: [0x00,0x40,0x7c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx4 off, v[2:5], s3 offset:4095
-// CHECK: [0xff,0x4f,0x7c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx4 off, v[2:5], s3 offset:-4096
-// CHECK: [0x00,0x50,0x7c,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx4 off, v[2:5], s3 offset:-1 glc
-// CHECK: [0xff,0x5f,0x7d,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_store_dwordx4 off, v[2:5], s3 offset:-1 slc
-// CHECK: [0xff,0x5f,0x7e,0xdc,0x00,0x02,0x03,0x00]
-
-scratch_load_ubyte_d16 v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16 v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_ubyte_d16 v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_ubyte_d16 v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_ubyte_d16 v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_ubyte_d16 v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_ubyte_d16 v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_ubyte_d16 v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_ubyte_d16 v5, off, s2
-// CHECK: [0x00,0x40,0x80,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16 v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x80,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16 v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x80,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16 v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x80,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16 v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x81,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16 v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x82,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16_hi v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_ubyte_d16_hi v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_ubyte_d16_hi v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, s2
-// CHECK: [0x00,0x40,0x84,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x84,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x84,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x84,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x85,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_ubyte_d16_hi v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x86,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16 v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16 v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_sbyte_d16 v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_sbyte_d16 v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_sbyte_d16 v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_sbyte_d16 v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_sbyte_d16 v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_sbyte_d16 v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_sbyte_d16 v5, off, s2
-// CHECK: [0x00,0x40,0x88,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16 v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x88,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16 v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x88,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16 v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x88,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16 v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x89,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16 v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x8a,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16_hi v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_sbyte_d16_hi v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_sbyte_d16_hi v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, s2
-// CHECK: [0x00,0x40,0x8c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x8c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x8c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x8c,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x8d,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_sbyte_d16_hi v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x8e,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16 v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16 v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_short_d16 v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_short_d16 v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_short_d16 v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_short_d16 v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_short_d16 v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_short_d16 v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_short_d16 v5, off, s2
-// CHECK: [0x00,0x40,0x90,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16 v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x90,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16 v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x90,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16 v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x90,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16 v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x91,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16 v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x92,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16_hi v5, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16_hi v255, off, s2 offset:-1
-// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x02,0xff]
-
-scratch_load_short_d16_hi v5, off, s101 offset:-1
-// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x65,0x05]
-
-scratch_load_short_d16_hi v5, off, flat_scratch_lo offset:-1
-// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x66,0x05]
-
-scratch_load_short_d16_hi v5, off, flat_scratch_hi offset:-1
-// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x67,0x05]
-
-scratch_load_short_d16_hi v5, off, vcc_lo offset:-1
-// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x6a,0x05]
-
-scratch_load_short_d16_hi v5, off, vcc_hi offset:-1
-// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x6b,0x05]
-
-scratch_load_short_d16_hi v5, v0, off offset:-1
-// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x7f,0x05]
-
-scratch_load_short_d16_hi v5, off, s2
-// CHECK: [0x00,0x40,0x94,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16_hi v5, off, s2 offset:0
-// CHECK: [0x00,0x40,0x94,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16_hi v5, off, s2 offset:4095
-// CHECK: [0xff,0x4f,0x94,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16_hi v5, off, s2 offset:-4096
-// CHECK: [0x00,0x50,0x94,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16_hi v5, off, s2 offset:-1 glc
-// CHECK: [0xff,0x5f,0x95,0xdc,0x00,0x00,0x02,0x05]
-
-scratch_load_short_d16_hi v5, off, s2 offset:-1 slc
-// CHECK: [0xff,0x5f,0x96,0xdc,0x00,0x00,0x02,0x05]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v252, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0xfc,0x02,0x00]
-
-image_load v5, v[252:255], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0xfc,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[12:19] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x03,0x00]
-
-image_load v5, v[1:4], s[92:99] dmask:0x1
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x17,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x2
-// CHECK: [0x00,0x02,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x3
-// CHECK: [0x00,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x4
-// CHECK: [0x00,0x04,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x5
-// CHECK: [0x00,0x05,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x6
-// CHECK: [0x00,0x06,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0x7
-// CHECK: [0x00,0x07,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x8
-// CHECK: [0x00,0x08,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x9
-// CHECK: [0x00,0x09,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v[5:7], v[1:4], s[8:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x0
-// CHECK: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00]
-
-image_load v[5:6], v[1:4], s[8:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x02,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x00,0xf0,0x01,0x05,0x02,0x00]
-
-image_load v5, v[1:4], s[8:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x80]
-
-image_load v[0:4], v5, s[0:7] dmask:0xf unorm tfe
-// CHECK: [0x00,0x1f,0x01,0xf0,0x05,0x00,0x00,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v252, v[1:4], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0xfc,0x02,0x00]
-
-image_load_mip v5, v[252:255], s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0xfc,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[12:19] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x03,0x00]
-
-image_load_mip v5, v[1:4], s[92:99] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x17,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x2
-// CHECK: [0x00,0x02,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x3
-// CHECK: [0x00,0x03,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x4
-// CHECK: [0x00,0x04,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x5
-// CHECK: [0x00,0x05,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x6
-// CHECK: [0x00,0x06,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0x7
-// CHECK: [0x00,0x07,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x8
-// CHECK: [0x00,0x08,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x9
-// CHECK: [0x00,0x09,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:7], v[1:4], s[8:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x0
-// CHECK: [0x00,0x00,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00]
-
-image_load_mip v[5:6], v[1:4], s[8:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x06,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x04,0xf0,0x01,0x05,0x02,0x00]
-
-image_load_mip v5, v[1:4], s[8:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x80]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v252, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0xfc,0x03,0x00]
-
-image_store v1, v[252:255], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0xfc,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x04,0x00]
-
-image_store v1, v[2:5], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x17,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x2 unorm
-// CHECK: [0x00,0x12,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x4 unorm
-// CHECK: [0x00,0x14,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x5 unorm
-// CHECK: [0x00,0x15,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x6 unorm
-// CHECK: [0x00,0x16,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0x7 unorm
-// CHECK: [0x00,0x17,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x8 unorm
-// CHECK: [0x00,0x18,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0x9 unorm
-// CHECK: [0x00,0x19,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0xa unorm
-// CHECK: [0x00,0x1a,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0xb unorm
-// CHECK: [0x00,0x1b,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:2], v[2:5], s[12:19] dmask:0xc unorm
-// CHECK: [0x00,0x1c,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0xd unorm
-// CHECK: [0x00,0x1d,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:3], v[2:5], s[12:19] dmask:0xe unorm
-// CHECK: [0x00,0x1e,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v[1:4], v[2:5], s[12:19] dmask:0xf unorm
-// CHECK: [0x00,0x1f,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x0 unorm
-// CHECK: [0x00,0x10,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x20,0xf2,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x22,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x20,0xf0,0x02,0x01,0x03,0x00]
-
-image_store v1, v[2:5], s[12:19] dmask:0x1 unorm d16
-// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x80]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v252, v[2:5], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0xfc,0x03,0x00]
-
-image_store_mip v1, v[252:255], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0xfc,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[16:23] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x04,0x00]
-
-image_store_mip v1, v[2:5], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x17,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x2 unorm
-// CHECK: [0x00,0x12,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x4 unorm
-// CHECK: [0x00,0x14,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x5 unorm
-// CHECK: [0x00,0x15,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x6 unorm
-// CHECK: [0x00,0x16,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0x7 unorm
-// CHECK: [0x00,0x17,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x8 unorm
-// CHECK: [0x00,0x18,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0x9 unorm
-// CHECK: [0x00,0x19,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0xa unorm
-// CHECK: [0x00,0x1a,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0xb unorm
-// CHECK: [0x00,0x1b,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:2], v[2:5], s[12:19] dmask:0xc unorm
-// CHECK: [0x00,0x1c,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0xd unorm
-// CHECK: [0x00,0x1d,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:3], v[2:5], s[12:19] dmask:0xe unorm
-// CHECK: [0x00,0x1e,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v[1:4], v[2:5], s[12:19] dmask:0xf unorm
-// CHECK: [0x00,0x1f,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x0 unorm
-// CHECK: [0x00,0x10,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x24,0xf2,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x26,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x24,0xf0,0x02,0x01,0x03,0x00]
-
-image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm d16
-// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x80]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v252, v1, s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0xfc,0x02,0x00]
-
-image_get_resinfo v5, v255, s[8:15] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0xff,0x05,0x02,0x00]
-
-image_get_resinfo v5, v1, s[12:19] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x03,0x00]
-
-image_get_resinfo v5, v1, s[92:99] dmask:0x1
-// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x17,0x00]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x2
-// CHECK: [0x00,0x02,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v1, s[8:15] dmask:0x3
-// CHECK: [0x00,0x03,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x4
-// CHECK: [0x00,0x04,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v1, s[8:15] dmask:0x5
-// CHECK: [0x00,0x05,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v1, s[8:15] dmask:0x6
-// CHECK: [0x00,0x06,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v1, s[8:15] dmask:0x7
-// CHECK: [0x00,0x07,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x8
-// CHECK: [0x00,0x08,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v1, s[8:15] dmask:0x9
-// CHECK: [0x00,0x09,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v1, s[8:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v1, s[8:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v1, s[8:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v1, s[8:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:7], v1, s[8:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:8], v1, s[8:15] dmask:0xf
-// CHECK: [0x00,0x0f,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x0
-// CHECK: [0x00,0x00,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v[5:6], v1, s[8:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x3a,0xf0,0x01,0x05,0x02,0x00]
-
-image_get_resinfo v5, v1, s[8:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x38,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_swap v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_swap v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_swap v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_swap v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x40,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x40,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x40,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x42,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_swap v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x40,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[252:253], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v[252:255], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v[1:4], s[12:19] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_cmpswap v[5:6], v[1:4], s[92:99] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_cmpswap v[5:8], v[1:4], s[8:15] dmask:0xf unorm
-// CHECK: [0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v[1:4], s[8:15] dmask:0x3 unorm glc
-// CHECK: [0x00,0x33,0x44,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v[1:4], s[8:15] dmask:0x3 unorm slc
-// CHECK: [0x00,0x13,0x44,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v[1:4], s[8:15] dmask:0x3 unorm lwe
-// CHECK: [0x00,0x13,0x46,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_cmpswap v[5:6], v[1:4], s[8:15] dmask:0x3 unorm da
-// CHECK: [0x00,0x53,0x44,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_add v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_add v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_add v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_add v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x48,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x48,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x4a,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_add v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x48,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_sub v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_sub v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_sub v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_sub v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x4c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x4c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x4c,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x4e,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_sub v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x4c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_smin v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_smin v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_smin v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_smin v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x50,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x50,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x50,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x52,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smin v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x50,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_umin v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_umin v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_umin v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_umin v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x54,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x54,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x54,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x56,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umin v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x54,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_smax v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_smax v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_smax v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_smax v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x58,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x58,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x58,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x5a,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_smax v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x58,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_umax v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_umax v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_umax v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_umax v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x5c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x5c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x5c,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x5e,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_umax v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x5c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_and v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_and v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_and v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_and v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x60,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x60,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x60,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x62,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_and v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x60,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_or v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_or v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_or v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_or v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x64,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x64,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x64,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x66,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_or v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x64,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_xor v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_xor v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_xor v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_xor v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x68,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x68,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x68,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x6a,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_xor v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x68,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_inc v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_inc v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_inc v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_inc v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x6c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x6c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x6c,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x6e,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_inc v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x6c,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v252, v[1:4], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x01,0xfc,0x02,0x00]
-
-image_atomic_dec v5, v[252:255], s[8:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0xfc,0x05,0x02,0x00]
-
-image_atomic_dec v5, v[1:4], s[12:19] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x03,0x00]
-
-image_atomic_dec v5, v[1:4], s[92:99] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x17,0x00]
-
-image_atomic_dec v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
-// CHECK: [0x00,0x13,0x70,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v[1:4], s[8:15] dmask:0x1 unorm glc
-// CHECK: [0x00,0x31,0x70,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v[1:4], s[8:15] dmask:0x1 unorm slc
-// CHECK: [0x00,0x11,0x70,0xf2,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v[1:4], s[8:15] dmask:0x1 unorm lwe
-// CHECK: [0x00,0x11,0x72,0xf0,0x01,0x05,0x02,0x00]
-
-image_atomic_dec v5, v[1:4], s[8:15] dmask:0x1 unorm da
-// CHECK: [0x00,0x51,0x70,0xf0,0x01,0x05,0x02,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_cl v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x86,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x84,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_l v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_l v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x92,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x90,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_b v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_b v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x96,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x94,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xa2,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xa0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_c_lz v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_c_lz v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xbe,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xbc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_o v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xc0,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xc0,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xc1,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xc2,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xc0,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x80]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0xfc,0x62,0x00]
-
-image_sample_lz_o v5, v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xdc,0xf0,0xfc,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x63,0x00]
-
-image_sample_lz_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x77,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x82,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x02,0x03]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
-// CHECK: [0x00,0x03,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
-// CHECK: [0x00,0x05,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
-// CHECK: [0x00,0x06,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
-// CHECK: [0x00,0x07,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
-// CHECK: [0x00,0x09,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
-// CHECK: [0x00,0x0a,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
-// CHECK: [0x00,0x0b,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
-// CHECK: [0x00,0x0c,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
-// CHECK: [0x00,0x0d,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
-// CHECK: [0x00,0x0e,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
-// CHECK: [0x00,0x00,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0xdc,0xf2,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
-// CHECK: [0x00,0x01,0xdd,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0xde,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0xdc,0xf0,0x01,0x05,0x62,0x00]
-
-image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x80]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_cl v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x04,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x06,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x04,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_l v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x10,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x12,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x10,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_b v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x14,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x16,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x14,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x20,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x22,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x20,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x3c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x3e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x3c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_c_lz v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x40,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x42,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x40,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x80]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0xfc,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[252:255], s[8:15], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0xfc,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x63,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x77,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x82,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x02,0x03]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
-// CHECK: [0x00,0x02,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
-// CHECK: [0x00,0x04,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
-// CHECK: [0x00,0x08,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
-// CHECK: [0x00,0x11,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
-// CHECK: [0x00,0x21,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
-// CHECK: [0x00,0x01,0x5c,0xf3,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
-// CHECK: [0x00,0x01,0x5e,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
-// CHECK: [0x00,0x41,0x5c,0xf1,0x01,0x05,0x62,0x00]
-
-image_gather4_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
-// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x80]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_format_x v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_x v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_x v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_x v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_x v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x00,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xy v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x04,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x06,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0xfd,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x08,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0a,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0xfc,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x0c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0e,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_format_x v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_x v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_x v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_x v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_x v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x10,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x12,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xy v[1:2], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x14,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x16,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0xfd,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x18,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1a,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0xfc,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x1c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1e,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_d16_x v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_d16_x v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_d16_x v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_d16_x v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_d16_x v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_d16_x v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_d16_x v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x20,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x22,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_format_d16_xy v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_d16_xy v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_d16_xy v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_d16_xy v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_d16_xy v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_d16_xy v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_d16_xy v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_d16_xy v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_d16_xy v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x24,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x26,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_d16_xyz v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_d16_xyz v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x28,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2a,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_format_d16_xyzw v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x2c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2e,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_d16_x v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_d16_x v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_d16_x v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_d16_x v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_d16_x v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_d16_x v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_d16_x v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x30,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x32,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_format_d16_xy v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_d16_xy v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_d16_xy v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_d16_xy v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_d16_xy v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_d16_xy v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_d16_xy v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_d16_xy v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_d16_xy v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x34,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x36,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_d16_xyz v[1:2], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_d16_xyz v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x38,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x3a,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_format_d16_xyzw v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x3c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x3e,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ubyte v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_ubyte v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ubyte v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ubyte v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ubyte v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ubyte v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ubyte v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x40,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sbyte v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_sbyte v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sbyte v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sbyte v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sbyte v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sbyte v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sbyte v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x44,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ushort v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ushort v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_ushort v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ushort v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ushort v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ushort v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ushort v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x48,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sshort v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sshort v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_sshort v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sshort v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sshort v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sshort v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sshort v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sshort v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x4c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_dword v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dword v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dword v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dword v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dword v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dword v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dword v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dword v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dword v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x50,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds
-// CHECK: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0xfe,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x54,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x56,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[253:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0xfd,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x58,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x5a,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[252:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0xfc,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x5c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x5e,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_byte v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_byte v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_byte v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_byte v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_byte v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_byte v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_byte v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_byte v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_byte v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x60,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x62,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte_d16_hi v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_byte_d16_hi v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_byte_d16_hi v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_byte_d16_hi v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x64,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte_d16_hi v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x64,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x64,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x64,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x64,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x64,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x66,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_short v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_short v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_short v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_short v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_short v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_short v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_short v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_short v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_short v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x68,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x6a,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short_d16_hi v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_short_d16_hi v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_short_d16_hi v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_short_d16_hi v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_short_d16_hi v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_short_d16_hi v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_short_d16_hi v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_short_d16_hi v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_short_d16_hi v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_short_d16_hi v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x6c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short_d16_hi v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x6c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short_d16_hi v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x6c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x6c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x6e,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v255, off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0xff,0x03,0x04]
-
-buffer_store_dword v1, off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dword v1, off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dword v1, off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dword v1, off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dword v1, off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dword v1, off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dword v1, off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dword v1, off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dword v1, v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4
-// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x70,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dword v1, off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x72,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[254:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0xfe,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x74,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x76,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[253:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0xfd,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x78,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x7a,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[252:255], off, s[12:15], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0xfc,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[16:19], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x04,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[96:99], s4 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x18,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s101 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x65]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], m0 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7c]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], 0 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x80]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], -1 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xc1]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf0]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf7]
-
-buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 idxen offset:4095
-// CHECK: [0xff,0x2f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 offen offset:4095
-// CHECK: [0xff,0x1f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4
-// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:0
-// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:7
-// CHECK: [0x07,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc
-// CHECK: [0xff,0x4f,0x7c,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 slc
-// CHECK: [0xff,0x0f,0x7e,0xe0,0x00,0x01,0x03,0x04]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16 v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ubyte_d16 v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ubyte_d16 v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ubyte_d16 v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x80,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16 v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x80,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x80,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x80,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x80,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x80,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x82,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16_hi v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_ubyte_d16_hi v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_ubyte_d16_hi v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_ubyte_d16_hi v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x84,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16_hi v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x84,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x84,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x84,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x84,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x84,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x86,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16 v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sbyte_d16 v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sbyte_d16 v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sbyte_d16 v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x88,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16 v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x88,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x88,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x88,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x88,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x88,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x8a,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16_hi v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_sbyte_d16_hi v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_sbyte_d16_hi v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_sbyte_d16_hi v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x8c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16_hi v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x8c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x8c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x8c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x8c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x8c,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x8e,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16 v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16 v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_short_d16 v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_short_d16 v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_short_d16 v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_short_d16 v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_short_d16 v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_short_d16 v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_short_d16 v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_short_d16 v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_short_d16 v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x90,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16 v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x90,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16 v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x90,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16 v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x90,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16 v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x90,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16 v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x90,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16 v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x92,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16_hi v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0xff,0x02,0x03]
-
-buffer_load_short_d16_hi v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x03,0x03]
-
-buffer_load_short_d16_hi v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x18,0x03]
-
-buffer_load_short_d16_hi v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x65]
-
-buffer_load_short_d16_hi v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x7c]
-
-buffer_load_short_d16_hi v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x80]
-
-buffer_load_short_d16_hi v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0xc1]
-
-buffer_load_short_d16_hi v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0xf0]
-
-buffer_load_short_d16_hi v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0xf7]
-
-buffer_load_short_d16_hi v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x94,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16_hi v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x94,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16_hi v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x94,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x94,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x94,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x94,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x96,0xe0,0x00,0x05,0x02,0x03]
-
-buffer_wbinvl1
-// CHECK: [0x00,0x00,0xf8,0xe0,0x00,0x00,0x00,0x00]
-
-buffer_wbinvl1_vol
-// CHECK: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_swap v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_swap v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_swap v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_swap v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_swap v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_swap v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_swap v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x00,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x02,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x04,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x06,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_add v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_add v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_add v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_add v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_add v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_add v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_add v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x08,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_sub v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_sub v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_sub v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_sub v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_sub v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_sub v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_sub v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x0c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x0e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smin v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smin v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smin v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smin v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smin v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_smin v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_smin v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x10,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x12,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umin v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umin v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umin v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umin v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umin v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_umin v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_umin v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x14,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x16,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smax v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smax v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smax v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smax v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smax v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_smax v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_smax v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x18,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umax v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umax v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umax v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umax v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umax v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_umax v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_umax v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x1c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x1e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_and v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_and v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_and v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_and v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_and v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_and v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_and v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_and v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x20,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x22,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_or v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_or v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_or v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_or v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_or v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_or v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_or v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_or v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x24,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x26,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_xor v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_xor v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_xor v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_xor v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_xor v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_xor v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_xor v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x28,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_inc v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_inc v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_inc v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_inc v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_inc v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_inc v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_inc v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x2c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x2e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v255, off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0xff,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_dec v5, off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_dec v5, off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_dec v5, off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_dec v5, off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_dec v5, off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_dec v5, off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_dec v5, v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3
-// CHECK: [0x00,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x30,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x32,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x80,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x82,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[252:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0xfc,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x84,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x86,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x88,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x8a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x8c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x8e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x90,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x92,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x94,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x96,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x98,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x9a,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0x9c,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0x9e,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xa0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xa2,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xa4,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xa6,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xa8,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xaa,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xac,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xae,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[254:255], off, s[8:11], s3 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0xfe,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[12:15], s3 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x03,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[96:99], s3 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x18,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s101 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x65]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], m0 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7c]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x80]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], -1 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xc1]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0.5 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xf0]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], -4.0 offset:4095
-// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xf7]
-
-buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
-// CHECK: [0xff,0x2f,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
-// CHECK: [0xff,0x1f,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3
-// CHECK: [0x00,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:0
-// CHECK: [0x00,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:7
-// CHECK: [0x07,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
-// CHECK: [0xff,0x4f,0xb0,0xe1,0x00,0x05,0x02,0x03]
-
-buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
-// CHECK: [0xff,0x0f,0xb2,0xe1,0x00,0x05,0x02,0x03]
-
-s_load_dword s5, s[2:3], s0
-// CHECK: [0x41,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword s101, s[2:3], s0
-// CHECK: [0x41,0x19,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword flat_scratch_lo, s[2:3], s0
-// CHECK: [0x81,0x19,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword flat_scratch_hi, s[2:3], s0
-// CHECK: [0xc1,0x19,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword vcc_lo, s[2:3], s0
-// CHECK: [0x81,0x1a,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword vcc_hi, s[2:3], s0
-// CHECK: [0xc1,0x1a,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[4:5], s0
-// CHECK: [0x42,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[100:101], s0
-// CHECK: [0x72,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, flat_scratch, s0
-// CHECK: [0x73,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, vcc, s0
-// CHECK: [0x75,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], s101
-// CHECK: [0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], flat_scratch_lo
-// CHECK: [0x41,0x01,0x00,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], flat_scratch_hi
-// CHECK: [0x41,0x01,0x00,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], vcc_lo
-// CHECK: [0x41,0x01,0x00,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], vcc_hi
-// CHECK: [0x41,0x01,0x00,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], m0
-// CHECK: [0x41,0x01,0x00,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], 0x0
-// CHECK: [0x41,0x01,0x02,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dword s5, s[2:3], s0 glc
-// CHECK: [0x41,0x01,0x01,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], s0
-// CHECK: [0x81,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[12:13], s[2:3], s0
-// CHECK: [0x01,0x03,0x04,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[100:101], s[2:3], s0
-// CHECK: [0x01,0x19,0x04,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 flat_scratch, s[2:3], s0
-// CHECK: [0x81,0x19,0x04,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 vcc, s[2:3], s0
-// CHECK: [0x81,0x1a,0x04,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[4:5], s0
-// CHECK: [0x82,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[100:101], s0
-// CHECK: [0xb2,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], flat_scratch, s0
-// CHECK: [0xb3,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], vcc, s0
-// CHECK: [0xb5,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], s101
-// CHECK: [0x81,0x02,0x04,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x81,0x02,0x04,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x81,0x02,0x04,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x81,0x02,0x04,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x81,0x02,0x04,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], m0
-// CHECK: [0x81,0x02,0x04,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], 0x0
-// CHECK: [0x81,0x02,0x06,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx2 s[10:11], s[2:3], s0 glc
-// CHECK: [0x81,0x02,0x05,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], s0
-// CHECK: [0x01,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[24:27], s[2:3], s0
-// CHECK: [0x01,0x06,0x08,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[96:99], s[2:3], s0
-// CHECK: [0x01,0x18,0x08,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[4:5], s0
-// CHECK: [0x02,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[100:101], s0
-// CHECK: [0x32,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], flat_scratch, s0
-// CHECK: [0x33,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], vcc, s0
-// CHECK: [0x35,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], s101
-// CHECK: [0x01,0x05,0x08,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], flat_scratch_lo
-// CHECK: [0x01,0x05,0x08,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], flat_scratch_hi
-// CHECK: [0x01,0x05,0x08,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], vcc_lo
-// CHECK: [0x01,0x05,0x08,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], vcc_hi
-// CHECK: [0x01,0x05,0x08,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], m0
-// CHECK: [0x01,0x05,0x08,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], 0x0
-// CHECK: [0x01,0x05,0x0a,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx4 s[20:23], s[2:3], s0 glc
-// CHECK: [0x01,0x05,0x09,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], s0
-// CHECK: [0x01,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[24:31], s[2:3], s0
-// CHECK: [0x01,0x06,0x0c,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[92:99], s[2:3], s0
-// CHECK: [0x01,0x17,0x0c,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[4:5], s0
-// CHECK: [0x02,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[100:101], s0
-// CHECK: [0x32,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], flat_scratch, s0
-// CHECK: [0x33,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], vcc, s0
-// CHECK: [0x35,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], s101
-// CHECK: [0x01,0x05,0x0c,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], flat_scratch_lo
-// CHECK: [0x01,0x05,0x0c,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], flat_scratch_hi
-// CHECK: [0x01,0x05,0x0c,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], vcc_lo
-// CHECK: [0x01,0x05,0x0c,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], vcc_hi
-// CHECK: [0x01,0x05,0x0c,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], m0
-// CHECK: [0x01,0x05,0x0c,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], 0x0
-// CHECK: [0x01,0x05,0x0e,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx8 s[20:27], s[2:3], s0 glc
-// CHECK: [0x01,0x05,0x0d,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], s0
-// CHECK: [0x01,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[24:39], s[2:3], s0
-// CHECK: [0x01,0x06,0x10,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[84:99], s[2:3], s0
-// CHECK: [0x01,0x15,0x10,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[4:5], s0
-// CHECK: [0x02,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[100:101], s0
-// CHECK: [0x32,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], flat_scratch, s0
-// CHECK: [0x33,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], vcc, s0
-// CHECK: [0x35,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], s101
-// CHECK: [0x01,0x05,0x10,0xc0,0x65,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], flat_scratch_lo
-// CHECK: [0x01,0x05,0x10,0xc0,0x66,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], flat_scratch_hi
-// CHECK: [0x01,0x05,0x10,0xc0,0x67,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], vcc_lo
-// CHECK: [0x01,0x05,0x10,0xc0,0x6a,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], vcc_hi
-// CHECK: [0x01,0x05,0x10,0xc0,0x6b,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], m0
-// CHECK: [0x01,0x05,0x10,0xc0,0x7c,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], 0x0
-// CHECK: [0x01,0x05,0x12,0xc0,0x00,0x00,0x00,0x00]
-
-s_load_dwordx16 s[20:35], s[2:3], s0 glc
-// CHECK: [0x01,0x05,0x11,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], s0
-// CHECK: [0x42,0x01,0x20,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s101, s[4:7], s0
-// CHECK: [0x42,0x19,0x20,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword flat_scratch_lo, s[4:7], s0
-// CHECK: [0x82,0x19,0x20,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword flat_scratch_hi, s[4:7], s0
-// CHECK: [0xc2,0x19,0x20,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword vcc_lo, s[4:7], s0
-// CHECK: [0x82,0x1a,0x20,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword vcc_hi, s[4:7], s0
-// CHECK: [0xc2,0x1a,0x20,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[8:11], s0
-// CHECK: [0x44,0x01,0x20,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[96:99], s0
-// CHECK: [0x70,0x01,0x20,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], s101
-// CHECK: [0x42,0x01,0x20,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], flat_scratch_lo
-// CHECK: [0x42,0x01,0x20,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], flat_scratch_hi
-// CHECK: [0x42,0x01,0x20,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], vcc_lo
-// CHECK: [0x42,0x01,0x20,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], vcc_hi
-// CHECK: [0x42,0x01,0x20,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], m0
-// CHECK: [0x42,0x01,0x20,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], 0x0
-// CHECK: [0x42,0x01,0x22,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dword s5, s[4:7], s0 glc
-// CHECK: [0x42,0x01,0x21,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s0
-// CHECK: [0x82,0x02,0x24,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[12:13], s[4:7], s0
-// CHECK: [0x02,0x03,0x24,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[100:101], s[4:7], s0
-// CHECK: [0x02,0x19,0x24,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 flat_scratch, s[4:7], s0
-// CHECK: [0x82,0x19,0x24,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 vcc, s[4:7], s0
-// CHECK: [0x82,0x1a,0x24,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[8:11], s0
-// CHECK: [0x84,0x02,0x24,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[96:99], s0
-// CHECK: [0xb0,0x02,0x24,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s101
-// CHECK: [0x82,0x02,0x24,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_lo
-// CHECK: [0x82,0x02,0x24,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_hi
-// CHECK: [0x82,0x02,0x24,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_lo
-// CHECK: [0x82,0x02,0x24,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
-// CHECK: [0x82,0x02,0x24,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], m0
-// CHECK: [0x82,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], 0x0
-// CHECK: [0x82,0x02,0x26,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc
-// CHECK: [0x82,0x02,0x25,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s0
-// CHECK: [0x02,0x05,0x28,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[24:27], s[4:7], s0
-// CHECK: [0x02,0x06,0x28,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[96:99], s[4:7], s0
-// CHECK: [0x02,0x18,0x28,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[8:11], s0
-// CHECK: [0x04,0x05,0x28,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[96:99], s0
-// CHECK: [0x30,0x05,0x28,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s101
-// CHECK: [0x02,0x05,0x28,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_lo
-// CHECK: [0x02,0x05,0x28,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_hi
-// CHECK: [0x02,0x05,0x28,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_lo
-// CHECK: [0x02,0x05,0x28,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
-// CHECK: [0x02,0x05,0x28,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], m0
-// CHECK: [0x02,0x05,0x28,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], 0x0
-// CHECK: [0x02,0x05,0x2a,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc
-// CHECK: [0x02,0x05,0x29,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s0
-// CHECK: [0x02,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[24:31], s[4:7], s0
-// CHECK: [0x02,0x06,0x2c,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[92:99], s[4:7], s0
-// CHECK: [0x02,0x17,0x2c,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[8:11], s0
-// CHECK: [0x04,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[96:99], s0
-// CHECK: [0x30,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s101
-// CHECK: [0x02,0x05,0x2c,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_lo
-// CHECK: [0x02,0x05,0x2c,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_hi
-// CHECK: [0x02,0x05,0x2c,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_lo
-// CHECK: [0x02,0x05,0x2c,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
-// CHECK: [0x02,0x05,0x2c,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], m0
-// CHECK: [0x02,0x05,0x2c,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], 0x0
-// CHECK: [0x02,0x05,0x2e,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc
-// CHECK: [0x02,0x05,0x2d,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s0
-// CHECK: [0x02,0x05,0x30,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[24:39], s[4:7], s0
-// CHECK: [0x02,0x06,0x30,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[84:99], s[4:7], s0
-// CHECK: [0x02,0x15,0x30,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[8:11], s0
-// CHECK: [0x04,0x05,0x30,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[96:99], s0
-// CHECK: [0x30,0x05,0x30,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s101
-// CHECK: [0x02,0x05,0x30,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_lo
-// CHECK: [0x02,0x05,0x30,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_hi
-// CHECK: [0x02,0x05,0x30,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_lo
-// CHECK: [0x02,0x05,0x30,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
-// CHECK: [0x02,0x05,0x30,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], m0
-// CHECK: [0x02,0x05,0x30,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], 0x0
-// CHECK: [0x02,0x05,0x32,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc
-// CHECK: [0x02,0x05,0x31,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], s0
-// CHECK: [0x42,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword s101, s[4:5], s0
-// CHECK: [0x42,0x19,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword flat_scratch_lo, s[4:5], s0
-// CHECK: [0x82,0x19,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword flat_scratch_hi, s[4:5], s0
-// CHECK: [0xc2,0x19,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword vcc_lo, s[4:5], s0
-// CHECK: [0x82,0x1a,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword vcc_hi, s[4:5], s0
-// CHECK: [0xc2,0x1a,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[6:7], s0
-// CHECK: [0x43,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[100:101], s0
-// CHECK: [0x72,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, flat_scratch, s0
-// CHECK: [0x73,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, vcc, s0
-// CHECK: [0x75,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], s101
-// CHECK: [0x42,0x00,0x40,0xc0,0x65,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], flat_scratch_lo
-// CHECK: [0x42,0x00,0x40,0xc0,0x66,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], flat_scratch_hi
-// CHECK: [0x42,0x00,0x40,0xc0,0x67,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], vcc_lo
-// CHECK: [0x42,0x00,0x40,0xc0,0x6a,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], vcc_hi
-// CHECK: [0x42,0x00,0x40,0xc0,0x6b,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], m0
-// CHECK: [0x42,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], 0x0
-// CHECK: [0x42,0x00,0x42,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dword s1, s[4:5], s0 glc
-// CHECK: [0x42,0x00,0x41,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], s0
-// CHECK: [0x82,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[4:5], s[4:5], s0
-// CHECK: [0x02,0x01,0x44,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[100:101], s[4:5], s0
-// CHECK: [0x02,0x19,0x44,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 flat_scratch, s[4:5], s0
-// CHECK: [0x82,0x19,0x44,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 vcc, s[4:5], s0
-// CHECK: [0x82,0x1a,0x44,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[6:7], s0
-// CHECK: [0x83,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[100:101], s0
-// CHECK: [0xb2,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], flat_scratch, s0
-// CHECK: [0xb3,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], vcc, s0
-// CHECK: [0xb5,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], s101
-// CHECK: [0x82,0x00,0x44,0xc0,0x65,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], flat_scratch_lo
-// CHECK: [0x82,0x00,0x44,0xc0,0x66,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], flat_scratch_hi
-// CHECK: [0x82,0x00,0x44,0xc0,0x67,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], vcc_lo
-// CHECK: [0x82,0x00,0x44,0xc0,0x6a,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], vcc_hi
-// CHECK: [0x82,0x00,0x44,0xc0,0x6b,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], m0
-// CHECK: [0x82,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], 0x0
-// CHECK: [0x82,0x00,0x46,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx2 s[2:3], s[4:5], s0 glc
-// CHECK: [0x82,0x00,0x45,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], s0
-// CHECK: [0x02,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[8:11], s[4:5], s0
-// CHECK: [0x02,0x02,0x48,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[96:99], s[4:5], s0
-// CHECK: [0x02,0x18,0x48,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[6:7], s0
-// CHECK: [0x03,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[100:101], s0
-// CHECK: [0x32,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], flat_scratch, s0
-// CHECK: [0x33,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], vcc, s0
-// CHECK: [0x35,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], s101
-// CHECK: [0x02,0x01,0x48,0xc0,0x65,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], flat_scratch_lo
-// CHECK: [0x02,0x01,0x48,0xc0,0x66,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], flat_scratch_hi
-// CHECK: [0x02,0x01,0x48,0xc0,0x67,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], vcc_lo
-// CHECK: [0x02,0x01,0x48,0xc0,0x6a,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], vcc_hi
-// CHECK: [0x02,0x01,0x48,0xc0,0x6b,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], m0
-// CHECK: [0x02,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], 0x0
-// CHECK: [0x02,0x01,0x4a,0xc0,0x00,0x00,0x00,0x00]
-
-s_store_dwordx4 s[4:7], s[4:5], s0 glc
-// CHECK: [0x02,0x01,0x49,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], s0
-// CHECK: [0x44,0x00,0x60,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s101, s[8:11], s0
-// CHECK: [0x44,0x19,0x60,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword flat_scratch_lo, s[8:11], s0
-// CHECK: [0x84,0x19,0x60,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword flat_scratch_hi, s[8:11], s0
-// CHECK: [0xc4,0x19,0x60,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword vcc_lo, s[8:11], s0
-// CHECK: [0x84,0x1a,0x60,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword vcc_hi, s[8:11], s0
-// CHECK: [0xc4,0x1a,0x60,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[12:15], s0
-// CHECK: [0x46,0x00,0x60,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[96:99], s0
-// CHECK: [0x70,0x00,0x60,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], s101
-// CHECK: [0x44,0x00,0x60,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], flat_scratch_lo
-// CHECK: [0x44,0x00,0x60,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], flat_scratch_hi
-// CHECK: [0x44,0x00,0x60,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], vcc_lo
-// CHECK: [0x44,0x00,0x60,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], vcc_hi
-// CHECK: [0x44,0x00,0x60,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], m0
-// CHECK: [0x44,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], 0x0
-// CHECK: [0x44,0x00,0x62,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dword s1, s[8:11], s0 glc
-// CHECK: [0x44,0x00,0x61,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], s0
-// CHECK: [0x84,0x00,0x64,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[4:5], s[8:11], s0
-// CHECK: [0x04,0x01,0x64,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[100:101], s[8:11], s0
-// CHECK: [0x04,0x19,0x64,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 flat_scratch, s[8:11], s0
-// CHECK: [0x84,0x19,0x64,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 vcc, s[8:11], s0
-// CHECK: [0x84,0x1a,0x64,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[12:15], s0
-// CHECK: [0x86,0x00,0x64,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[96:99], s0
-// CHECK: [0xb0,0x00,0x64,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], s101
-// CHECK: [0x84,0x00,0x64,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], flat_scratch_lo
-// CHECK: [0x84,0x00,0x64,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], flat_scratch_hi
-// CHECK: [0x84,0x00,0x64,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], vcc_lo
-// CHECK: [0x84,0x00,0x64,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], vcc_hi
-// CHECK: [0x84,0x00,0x64,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], m0
-// CHECK: [0x84,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], 0x0
-// CHECK: [0x84,0x00,0x66,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx2 s[2:3], s[8:11], s0 glc
-// CHECK: [0x84,0x00,0x65,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], s0
-// CHECK: [0x04,0x01,0x68,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[8:11], s[8:11], s0
-// CHECK: [0x04,0x02,0x68,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[96:99], s[8:11], s0
-// CHECK: [0x04,0x18,0x68,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[12:15], s0
-// CHECK: [0x06,0x01,0x68,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[96:99], s0
-// CHECK: [0x30,0x01,0x68,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], s101
-// CHECK: [0x04,0x01,0x68,0xc0,0x65,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], flat_scratch_lo
-// CHECK: [0x04,0x01,0x68,0xc0,0x66,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], flat_scratch_hi
-// CHECK: [0x04,0x01,0x68,0xc0,0x67,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], vcc_lo
-// CHECK: [0x04,0x01,0x68,0xc0,0x6a,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], vcc_hi
-// CHECK: [0x04,0x01,0x68,0xc0,0x6b,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], m0
-// CHECK: [0x04,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], 0x0
-// CHECK: [0x04,0x01,0x6a,0xc0,0x00,0x00,0x00,0x00]
-
-s_buffer_store_dwordx4 s[4:7], s[8:11], s0 glc
-// CHECK: [0x04,0x01,0x69,0xc0,0x00,0x00,0x00,0x00]
-
-s_dcache_inv
-// CHECK: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
-
-s_dcache_wb
-// CHECK: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
-
-s_dcache_inv_vol
-// CHECK: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
-
-s_dcache_wb_vol
-// CHECK: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime s[10:11]
-// CHECK: [0x80,0x02,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime s[12:13]
-// CHECK: [0x00,0x03,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime s[100:101]
-// CHECK: [0x00,0x19,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime flat_scratch
-// CHECK: [0x80,0x19,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memtime vcc
-// CHECK: [0x80,0x1a,0x90,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime s[10:11]
-// CHECK: [0x80,0x02,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime s[12:13]
-// CHECK: [0x00,0x03,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime s[100:101]
-// CHECK: [0x00,0x19,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime flat_scratch
-// CHECK: [0x80,0x19,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_memrealtime vcc
-// CHECK: [0x80,0x1a,0x94,0xc0,0x00,0x00,0x00,0x00]
-
-s_mov_b32 s5, s1
-// CHECK: [0x01,0x00,0x85,0xbe]
-
-s_mov_b32 s101, s1
-// CHECK: [0x01,0x00,0xe5,0xbe]
-
-s_mov_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x00,0xe6,0xbe]
-
-s_mov_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x00,0xe7,0xbe]
-
-s_mov_b32 vcc_lo, s1
-// CHECK: [0x01,0x00,0xea,0xbe]
-
-s_mov_b32 vcc_hi, s1
-// CHECK: [0x01,0x00,0xeb,0xbe]
-
-s_mov_b32 m0, s1
-// CHECK: [0x01,0x00,0xfc,0xbe]
-
-s_mov_b32 exec_lo, s1
-// CHECK: [0x01,0x00,0xfe,0xbe]
-
-s_mov_b32 exec_hi, s1
-// CHECK: [0x01,0x00,0xff,0xbe]
-
-s_mov_b32 s5, s101
-// CHECK: [0x65,0x00,0x85,0xbe]
-
-s_mov_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x00,0x85,0xbe]
-
-s_mov_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x00,0x85,0xbe]
-
-s_mov_b32 s5, vcc_lo
-// CHECK: [0x6a,0x00,0x85,0xbe]
-
-s_mov_b32 s5, vcc_hi
-// CHECK: [0x6b,0x00,0x85,0xbe]
-
-s_mov_b32 s5, m0
-// CHECK: [0x7c,0x00,0x85,0xbe]
-
-s_mov_b32 s5, exec_lo
-// CHECK: [0x7e,0x00,0x85,0xbe]
-
-s_mov_b32 s5, exec_hi
-// CHECK: [0x7f,0x00,0x85,0xbe]
-
-s_mov_b32 s5, 0
-// CHECK: [0x80,0x00,0x85,0xbe]
-
-s_mov_b32 s5, -1
-// CHECK: [0xc1,0x00,0x85,0xbe]
-
-s_mov_b32 s5, 0.5
-// CHECK: [0xf0,0x00,0x85,0xbe]
-
-s_mov_b32 s5, -4.0
-// CHECK: [0xf7,0x00,0x85,0xbe]
-
-s_mov_b32 s5, 0xaf123456
-// CHECK: [0xff,0x00,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_mov_b32 s5, 0x3f717273
-// CHECK: [0xff,0x00,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_mov_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x01,0x8a,0xbe]
-
-s_mov_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x01,0x8c,0xbe]
-
-s_mov_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x01,0xe4,0xbe]
-
-s_mov_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x01,0xe6,0xbe]
-
-s_mov_b64 vcc, s[2:3]
-// CHECK: [0x02,0x01,0xea,0xbe]
-
-s_mov_b64 exec, s[2:3]
-// CHECK: [0x02,0x01,0xfe,0xbe]
-
-s_mov_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], vcc
-// CHECK: [0x6a,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], exec
-// CHECK: [0x7e,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], 0
-// CHECK: [0x80,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], -1
-// CHECK: [0xc1,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x01,0x8a,0xbe]
-
-s_mov_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x01,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_mov_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x01,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cmov_b32 s5, s1
-// CHECK: [0x01,0x02,0x85,0xbe]
-
-s_cmov_b32 s101, s1
-// CHECK: [0x01,0x02,0xe5,0xbe]
-
-s_cmov_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x02,0xe6,0xbe]
-
-s_cmov_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x02,0xe7,0xbe]
-
-s_cmov_b32 vcc_lo, s1
-// CHECK: [0x01,0x02,0xea,0xbe]
-
-s_cmov_b32 vcc_hi, s1
-// CHECK: [0x01,0x02,0xeb,0xbe]
-
-s_cmov_b32 m0, s1
-// CHECK: [0x01,0x02,0xfc,0xbe]
-
-s_cmov_b32 exec_lo, s1
-// CHECK: [0x01,0x02,0xfe,0xbe]
-
-s_cmov_b32 exec_hi, s1
-// CHECK: [0x01,0x02,0xff,0xbe]
-
-s_cmov_b32 s5, s101
-// CHECK: [0x65,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, vcc_lo
-// CHECK: [0x6a,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, vcc_hi
-// CHECK: [0x6b,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, m0
-// CHECK: [0x7c,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, exec_lo
-// CHECK: [0x7e,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, exec_hi
-// CHECK: [0x7f,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, 0
-// CHECK: [0x80,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, -1
-// CHECK: [0xc1,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, 0.5
-// CHECK: [0xf0,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, -4.0
-// CHECK: [0xf7,0x02,0x85,0xbe]
-
-s_cmov_b32 s5, 0xaf123456
-// CHECK: [0xff,0x02,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_cmov_b32 s5, 0x3f717273
-// CHECK: [0xff,0x02,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cmov_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x03,0x8c,0xbe]
-
-s_cmov_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x03,0xe4,0xbe]
-
-s_cmov_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x03,0xe6,0xbe]
-
-s_cmov_b64 vcc, s[2:3]
-// CHECK: [0x02,0x03,0xea,0xbe]
-
-s_cmov_b64 exec, s[2:3]
-// CHECK: [0x02,0x03,0xfe,0xbe]
-
-s_cmov_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], vcc
-// CHECK: [0x6a,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], exec
-// CHECK: [0x7e,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], 0
-// CHECK: [0x80,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], -1
-// CHECK: [0xc1,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x03,0x8a,0xbe]
-
-s_cmov_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x03,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_cmov_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x03,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_not_b32 s5, s1
-// CHECK: [0x01,0x04,0x85,0xbe]
-
-s_not_b32 s101, s1
-// CHECK: [0x01,0x04,0xe5,0xbe]
-
-s_not_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x04,0xe6,0xbe]
-
-s_not_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x04,0xe7,0xbe]
-
-s_not_b32 vcc_lo, s1
-// CHECK: [0x01,0x04,0xea,0xbe]
-
-s_not_b32 vcc_hi, s1
-// CHECK: [0x01,0x04,0xeb,0xbe]
-
-s_not_b32 m0, s1
-// CHECK: [0x01,0x04,0xfc,0xbe]
-
-s_not_b32 exec_lo, s1
-// CHECK: [0x01,0x04,0xfe,0xbe]
-
-s_not_b32 exec_hi, s1
-// CHECK: [0x01,0x04,0xff,0xbe]
-
-s_not_b32 s5, s101
-// CHECK: [0x65,0x04,0x85,0xbe]
-
-s_not_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x04,0x85,0xbe]
-
-s_not_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x04,0x85,0xbe]
-
-s_not_b32 s5, vcc_lo
-// CHECK: [0x6a,0x04,0x85,0xbe]
-
-s_not_b32 s5, vcc_hi
-// CHECK: [0x6b,0x04,0x85,0xbe]
-
-s_not_b32 s5, m0
-// CHECK: [0x7c,0x04,0x85,0xbe]
-
-s_not_b32 s5, exec_lo
-// CHECK: [0x7e,0x04,0x85,0xbe]
-
-s_not_b32 s5, exec_hi
-// CHECK: [0x7f,0x04,0x85,0xbe]
-
-s_not_b32 s5, 0
-// CHECK: [0x80,0x04,0x85,0xbe]
-
-s_not_b32 s5, -1
-// CHECK: [0xc1,0x04,0x85,0xbe]
-
-s_not_b32 s5, 0.5
-// CHECK: [0xf0,0x04,0x85,0xbe]
-
-s_not_b32 s5, -4.0
-// CHECK: [0xf7,0x04,0x85,0xbe]
-
-s_not_b32 s5, 0xaf123456
-// CHECK: [0xff,0x04,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_not_b32 s5, 0x3f717273
-// CHECK: [0xff,0x04,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_not_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x05,0x8a,0xbe]
-
-s_not_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x05,0x8c,0xbe]
-
-s_not_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x05,0xe4,0xbe]
-
-s_not_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x05,0xe6,0xbe]
-
-s_not_b64 vcc, s[2:3]
-// CHECK: [0x02,0x05,0xea,0xbe]
-
-s_not_b64 exec, s[2:3]
-// CHECK: [0x02,0x05,0xfe,0xbe]
-
-s_not_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], vcc
-// CHECK: [0x6a,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], exec
-// CHECK: [0x7e,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], 0
-// CHECK: [0x80,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], -1
-// CHECK: [0xc1,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x05,0x8a,0xbe]
-
-s_not_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x05,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_not_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x05,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_wqm_b32 s5, s1
-// CHECK: [0x01,0x06,0x85,0xbe]
-
-s_wqm_b32 s101, s1
-// CHECK: [0x01,0x06,0xe5,0xbe]
-
-s_wqm_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x06,0xe6,0xbe]
-
-s_wqm_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x06,0xe7,0xbe]
-
-s_wqm_b32 vcc_lo, s1
-// CHECK: [0x01,0x06,0xea,0xbe]
-
-s_wqm_b32 vcc_hi, s1
-// CHECK: [0x01,0x06,0xeb,0xbe]
-
-s_wqm_b32 m0, s1
-// CHECK: [0x01,0x06,0xfc,0xbe]
-
-s_wqm_b32 exec_lo, s1
-// CHECK: [0x01,0x06,0xfe,0xbe]
-
-s_wqm_b32 exec_hi, s1
-// CHECK: [0x01,0x06,0xff,0xbe]
-
-s_wqm_b32 s5, s101
-// CHECK: [0x65,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, vcc_lo
-// CHECK: [0x6a,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, vcc_hi
-// CHECK: [0x6b,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, m0
-// CHECK: [0x7c,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, exec_lo
-// CHECK: [0x7e,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, exec_hi
-// CHECK: [0x7f,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, 0
-// CHECK: [0x80,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, -1
-// CHECK: [0xc1,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, 0.5
-// CHECK: [0xf0,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, -4.0
-// CHECK: [0xf7,0x06,0x85,0xbe]
-
-s_wqm_b32 s5, 0xaf123456
-// CHECK: [0xff,0x06,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_wqm_b32 s5, 0x3f717273
-// CHECK: [0xff,0x06,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_wqm_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x07,0x8c,0xbe]
-
-s_wqm_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x07,0xe4,0xbe]
-
-s_wqm_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x07,0xe6,0xbe]
-
-s_wqm_b64 vcc, s[2:3]
-// CHECK: [0x02,0x07,0xea,0xbe]
-
-s_wqm_b64 exec, s[2:3]
-// CHECK: [0x02,0x07,0xfe,0xbe]
-
-s_wqm_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], vcc
-// CHECK: [0x6a,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], exec
-// CHECK: [0x7e,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], 0
-// CHECK: [0x80,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], -1
-// CHECK: [0xc1,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x07,0x8a,0xbe]
-
-s_wqm_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x07,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_wqm_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x07,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_brev_b32 s5, s1
-// CHECK: [0x01,0x08,0x85,0xbe]
-
-s_brev_b32 s101, s1
-// CHECK: [0x01,0x08,0xe5,0xbe]
-
-s_brev_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x08,0xe6,0xbe]
-
-s_brev_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x08,0xe7,0xbe]
-
-s_brev_b32 vcc_lo, s1
-// CHECK: [0x01,0x08,0xea,0xbe]
-
-s_brev_b32 vcc_hi, s1
-// CHECK: [0x01,0x08,0xeb,0xbe]
-
-s_brev_b32 m0, s1
-// CHECK: [0x01,0x08,0xfc,0xbe]
-
-s_brev_b32 exec_lo, s1
-// CHECK: [0x01,0x08,0xfe,0xbe]
-
-s_brev_b32 exec_hi, s1
-// CHECK: [0x01,0x08,0xff,0xbe]
-
-s_brev_b32 s5, s101
-// CHECK: [0x65,0x08,0x85,0xbe]
-
-s_brev_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x08,0x85,0xbe]
-
-s_brev_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x08,0x85,0xbe]
-
-s_brev_b32 s5, vcc_lo
-// CHECK: [0x6a,0x08,0x85,0xbe]
-
-s_brev_b32 s5, vcc_hi
-// CHECK: [0x6b,0x08,0x85,0xbe]
-
-s_brev_b32 s5, m0
-// CHECK: [0x7c,0x08,0x85,0xbe]
-
-s_brev_b32 s5, exec_lo
-// CHECK: [0x7e,0x08,0x85,0xbe]
-
-s_brev_b32 s5, exec_hi
-// CHECK: [0x7f,0x08,0x85,0xbe]
-
-s_brev_b32 s5, 0
-// CHECK: [0x80,0x08,0x85,0xbe]
-
-s_brev_b32 s5, -1
-// CHECK: [0xc1,0x08,0x85,0xbe]
-
-s_brev_b32 s5, 0.5
-// CHECK: [0xf0,0x08,0x85,0xbe]
-
-s_brev_b32 s5, -4.0
-// CHECK: [0xf7,0x08,0x85,0xbe]
-
-s_brev_b32 s5, 0xaf123456
-// CHECK: [0xff,0x08,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_brev_b32 s5, 0x3f717273
-// CHECK: [0xff,0x08,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_brev_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x09,0x8a,0xbe]
-
-s_brev_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x09,0x8c,0xbe]
-
-s_brev_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x09,0xe4,0xbe]
-
-s_brev_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x09,0xe6,0xbe]
-
-s_brev_b64 vcc, s[2:3]
-// CHECK: [0x02,0x09,0xea,0xbe]
-
-s_brev_b64 exec, s[2:3]
-// CHECK: [0x02,0x09,0xfe,0xbe]
-
-s_brev_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], vcc
-// CHECK: [0x6a,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], exec
-// CHECK: [0x7e,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], 0
-// CHECK: [0x80,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], -1
-// CHECK: [0xc1,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x09,0x8a,0xbe]
-
-s_brev_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x09,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_brev_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x09,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt0_i32_b32 s5, s1
-// CHECK: [0x01,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s101, s1
-// CHECK: [0x01,0x0a,0xe5,0xbe]
-
-s_bcnt0_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x0a,0xe6,0xbe]
-
-s_bcnt0_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x0a,0xe7,0xbe]
-
-s_bcnt0_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x0a,0xea,0xbe]
-
-s_bcnt0_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x0a,0xeb,0xbe]
-
-s_bcnt0_i32_b32 m0, s1
-// CHECK: [0x01,0x0a,0xfc,0xbe]
-
-s_bcnt0_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x0a,0xfe,0xbe]
-
-s_bcnt0_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x0a,0xff,0xbe]
-
-s_bcnt0_i32_b32 s5, s101
-// CHECK: [0x65,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, m0
-// CHECK: [0x7c,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, 0
-// CHECK: [0x80,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, -1
-// CHECK: [0xc1,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x0a,0x85,0xbe]
-
-s_bcnt0_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x0a,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt0_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x0a,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt0_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x0b,0xe5,0xbe]
-
-s_bcnt0_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x0b,0xe6,0xbe]
-
-s_bcnt0_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x0b,0xe7,0xbe]
-
-s_bcnt0_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x0b,0xea,0xbe]
-
-s_bcnt0_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x0b,0xeb,0xbe]
-
-s_bcnt0_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x0b,0xfc,0xbe]
-
-s_bcnt0_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x0b,0xfe,0xbe]
-
-s_bcnt0_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x0b,0xff,0xbe]
-
-s_bcnt0_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, vcc
-// CHECK: [0x6a,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, exec
-// CHECK: [0x7e,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, 0
-// CHECK: [0x80,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, -1
-// CHECK: [0xc1,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x0b,0x85,0xbe]
-
-s_bcnt0_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x0b,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt0_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x0b,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt1_i32_b32 s5, s1
-// CHECK: [0x01,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s101, s1
-// CHECK: [0x01,0x0c,0xe5,0xbe]
-
-s_bcnt1_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x0c,0xe6,0xbe]
-
-s_bcnt1_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x0c,0xe7,0xbe]
-
-s_bcnt1_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x0c,0xea,0xbe]
-
-s_bcnt1_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x0c,0xeb,0xbe]
-
-s_bcnt1_i32_b32 m0, s1
-// CHECK: [0x01,0x0c,0xfc,0xbe]
-
-s_bcnt1_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x0c,0xfe,0xbe]
-
-s_bcnt1_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x0c,0xff,0xbe]
-
-s_bcnt1_i32_b32 s5, s101
-// CHECK: [0x65,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, m0
-// CHECK: [0x7c,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, 0
-// CHECK: [0x80,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, -1
-// CHECK: [0xc1,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x0c,0x85,0xbe]
-
-s_bcnt1_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x0c,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt1_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x0c,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bcnt1_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x0d,0xe5,0xbe]
-
-s_bcnt1_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x0d,0xe6,0xbe]
-
-s_bcnt1_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x0d,0xe7,0xbe]
-
-s_bcnt1_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x0d,0xea,0xbe]
-
-s_bcnt1_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x0d,0xeb,0xbe]
-
-s_bcnt1_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x0d,0xfc,0xbe]
-
-s_bcnt1_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x0d,0xfe,0xbe]
-
-s_bcnt1_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x0d,0xff,0xbe]
-
-s_bcnt1_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, vcc
-// CHECK: [0x6a,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, exec
-// CHECK: [0x7e,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, 0
-// CHECK: [0x80,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, -1
-// CHECK: [0xc1,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x0d,0x85,0xbe]
-
-s_bcnt1_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x0d,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bcnt1_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x0d,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff0_i32_b32 s5, s1
-// CHECK: [0x01,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s101, s1
-// CHECK: [0x01,0x0e,0xe5,0xbe]
-
-s_ff0_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x0e,0xe6,0xbe]
-
-s_ff0_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x0e,0xe7,0xbe]
-
-s_ff0_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x0e,0xea,0xbe]
-
-s_ff0_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x0e,0xeb,0xbe]
-
-s_ff0_i32_b32 m0, s1
-// CHECK: [0x01,0x0e,0xfc,0xbe]
-
-s_ff0_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x0e,0xfe,0xbe]
-
-s_ff0_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x0e,0xff,0xbe]
-
-s_ff0_i32_b32 s5, s101
-// CHECK: [0x65,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, m0
-// CHECK: [0x7c,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, 0
-// CHECK: [0x80,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, -1
-// CHECK: [0xc1,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x0e,0x85,0xbe]
-
-s_ff0_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x0e,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff0_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x0e,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff0_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x0f,0xe5,0xbe]
-
-s_ff0_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x0f,0xe6,0xbe]
-
-s_ff0_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x0f,0xe7,0xbe]
-
-s_ff0_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x0f,0xea,0xbe]
-
-s_ff0_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x0f,0xeb,0xbe]
-
-s_ff0_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x0f,0xfc,0xbe]
-
-s_ff0_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x0f,0xfe,0xbe]
-
-s_ff0_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x0f,0xff,0xbe]
-
-s_ff0_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, vcc
-// CHECK: [0x6a,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, exec
-// CHECK: [0x7e,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, 0
-// CHECK: [0x80,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, -1
-// CHECK: [0xc1,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x0f,0x85,0xbe]
-
-s_ff0_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x0f,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff0_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x0f,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff1_i32_b32 s5, s1
-// CHECK: [0x01,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s101, s1
-// CHECK: [0x01,0x10,0xe5,0xbe]
-
-s_ff1_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x10,0xe6,0xbe]
-
-s_ff1_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x10,0xe7,0xbe]
-
-s_ff1_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x10,0xea,0xbe]
-
-s_ff1_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x10,0xeb,0xbe]
-
-s_ff1_i32_b32 m0, s1
-// CHECK: [0x01,0x10,0xfc,0xbe]
-
-s_ff1_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x10,0xfe,0xbe]
-
-s_ff1_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x10,0xff,0xbe]
-
-s_ff1_i32_b32 s5, s101
-// CHECK: [0x65,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, m0
-// CHECK: [0x7c,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, 0
-// CHECK: [0x80,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, -1
-// CHECK: [0xc1,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x10,0x85,0xbe]
-
-s_ff1_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x10,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff1_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x10,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_ff1_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x11,0xe5,0xbe]
-
-s_ff1_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x11,0xe6,0xbe]
-
-s_ff1_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x11,0xe7,0xbe]
-
-s_ff1_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x11,0xea,0xbe]
-
-s_ff1_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x11,0xeb,0xbe]
-
-s_ff1_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x11,0xfc,0xbe]
-
-s_ff1_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x11,0xfe,0xbe]
-
-s_ff1_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x11,0xff,0xbe]
-
-s_ff1_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, vcc
-// CHECK: [0x6a,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, exec
-// CHECK: [0x7e,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, 0
-// CHECK: [0x80,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, -1
-// CHECK: [0xc1,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x11,0x85,0xbe]
-
-s_ff1_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x11,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_ff1_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x11,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_b32 s5, s1
-// CHECK: [0x01,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s101, s1
-// CHECK: [0x01,0x12,0xe5,0xbe]
-
-s_flbit_i32_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x12,0xe6,0xbe]
-
-s_flbit_i32_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x12,0xe7,0xbe]
-
-s_flbit_i32_b32 vcc_lo, s1
-// CHECK: [0x01,0x12,0xea,0xbe]
-
-s_flbit_i32_b32 vcc_hi, s1
-// CHECK: [0x01,0x12,0xeb,0xbe]
-
-s_flbit_i32_b32 m0, s1
-// CHECK: [0x01,0x12,0xfc,0xbe]
-
-s_flbit_i32_b32 exec_lo, s1
-// CHECK: [0x01,0x12,0xfe,0xbe]
-
-s_flbit_i32_b32 exec_hi, s1
-// CHECK: [0x01,0x12,0xff,0xbe]
-
-s_flbit_i32_b32 s5, s101
-// CHECK: [0x65,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, vcc_lo
-// CHECK: [0x6a,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, vcc_hi
-// CHECK: [0x6b,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, m0
-// CHECK: [0x7c,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, exec_lo
-// CHECK: [0x7e,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, exec_hi
-// CHECK: [0x7f,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, 0
-// CHECK: [0x80,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, -1
-// CHECK: [0xc1,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, 0.5
-// CHECK: [0xf0,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, -4.0
-// CHECK: [0xf7,0x12,0x85,0xbe]
-
-s_flbit_i32_b32 s5, 0xaf123456
-// CHECK: [0xff,0x12,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_b32 s5, 0x3f717273
-// CHECK: [0xff,0x12,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_b64 s5, s[2:3]
-// CHECK: [0x02,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s101, s[2:3]
-// CHECK: [0x02,0x13,0xe5,0xbe]
-
-s_flbit_i32_b64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x13,0xe6,0xbe]
-
-s_flbit_i32_b64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x13,0xe7,0xbe]
-
-s_flbit_i32_b64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x13,0xea,0xbe]
-
-s_flbit_i32_b64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x13,0xeb,0xbe]
-
-s_flbit_i32_b64 m0, s[2:3]
-// CHECK: [0x02,0x13,0xfc,0xbe]
-
-s_flbit_i32_b64 exec_lo, s[2:3]
-// CHECK: [0x02,0x13,0xfe,0xbe]
-
-s_flbit_i32_b64 exec_hi, s[2:3]
-// CHECK: [0x02,0x13,0xff,0xbe]
-
-s_flbit_i32_b64 s5, s[4:5]
-// CHECK: [0x04,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, s[100:101]
-// CHECK: [0x64,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, flat_scratch
-// CHECK: [0x66,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, vcc
-// CHECK: [0x6a,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, exec
-// CHECK: [0x7e,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, 0
-// CHECK: [0x80,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, -1
-// CHECK: [0xc1,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, 0.5
-// CHECK: [0xf0,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, -4.0
-// CHECK: [0xf7,0x13,0x85,0xbe]
-
-s_flbit_i32_b64 s5, 0xaf123456
-// CHECK: [0xff,0x13,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_b64 s5, 0x3f717273
-// CHECK: [0xff,0x13,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32 s5, s1
-// CHECK: [0x01,0x14,0x85,0xbe]
-
-s_flbit_i32 s101, s1
-// CHECK: [0x01,0x14,0xe5,0xbe]
-
-s_flbit_i32 flat_scratch_lo, s1
-// CHECK: [0x01,0x14,0xe6,0xbe]
-
-s_flbit_i32 flat_scratch_hi, s1
-// CHECK: [0x01,0x14,0xe7,0xbe]
-
-s_flbit_i32 vcc_lo, s1
-// CHECK: [0x01,0x14,0xea,0xbe]
-
-s_flbit_i32 vcc_hi, s1
-// CHECK: [0x01,0x14,0xeb,0xbe]
-
-s_flbit_i32 m0, s1
-// CHECK: [0x01,0x14,0xfc,0xbe]
-
-s_flbit_i32 exec_lo, s1
-// CHECK: [0x01,0x14,0xfe,0xbe]
-
-s_flbit_i32 exec_hi, s1
-// CHECK: [0x01,0x14,0xff,0xbe]
-
-s_flbit_i32 s5, s101
-// CHECK: [0x65,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, flat_scratch_lo
-// CHECK: [0x66,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, flat_scratch_hi
-// CHECK: [0x67,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, vcc_lo
-// CHECK: [0x6a,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, vcc_hi
-// CHECK: [0x6b,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, m0
-// CHECK: [0x7c,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, exec_lo
-// CHECK: [0x7e,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, exec_hi
-// CHECK: [0x7f,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, 0
-// CHECK: [0x80,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, -1
-// CHECK: [0xc1,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, 0.5
-// CHECK: [0xf0,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, -4.0
-// CHECK: [0xf7,0x14,0x85,0xbe]
-
-s_flbit_i32 s5, 0xaf123456
-// CHECK: [0xff,0x14,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32 s5, 0x3f717273
-// CHECK: [0xff,0x14,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_flbit_i32_i64 s5, s[2:3]
-// CHECK: [0x02,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s101, s[2:3]
-// CHECK: [0x02,0x15,0xe5,0xbe]
-
-s_flbit_i32_i64 flat_scratch_lo, s[2:3]
-// CHECK: [0x02,0x15,0xe6,0xbe]
-
-s_flbit_i32_i64 flat_scratch_hi, s[2:3]
-// CHECK: [0x02,0x15,0xe7,0xbe]
-
-s_flbit_i32_i64 vcc_lo, s[2:3]
-// CHECK: [0x02,0x15,0xea,0xbe]
-
-s_flbit_i32_i64 vcc_hi, s[2:3]
-// CHECK: [0x02,0x15,0xeb,0xbe]
-
-s_flbit_i32_i64 m0, s[2:3]
-// CHECK: [0x02,0x15,0xfc,0xbe]
-
-s_flbit_i32_i64 exec_lo, s[2:3]
-// CHECK: [0x02,0x15,0xfe,0xbe]
-
-s_flbit_i32_i64 exec_hi, s[2:3]
-// CHECK: [0x02,0x15,0xff,0xbe]
-
-s_flbit_i32_i64 s5, s[4:5]
-// CHECK: [0x04,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, s[100:101]
-// CHECK: [0x64,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, flat_scratch
-// CHECK: [0x66,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, vcc
-// CHECK: [0x6a,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, exec
-// CHECK: [0x7e,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, 0
-// CHECK: [0x80,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, -1
-// CHECK: [0xc1,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, 0.5
-// CHECK: [0xf0,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, -4.0
-// CHECK: [0xf7,0x15,0x85,0xbe]
-
-s_flbit_i32_i64 s5, 0xaf123456
-// CHECK: [0xff,0x15,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_flbit_i32_i64 s5, 0x3f717273
-// CHECK: [0xff,0x15,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_sext_i32_i8 s5, s1
-// CHECK: [0x01,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s101, s1
-// CHECK: [0x01,0x16,0xe5,0xbe]
-
-s_sext_i32_i8 flat_scratch_lo, s1
-// CHECK: [0x01,0x16,0xe6,0xbe]
-
-s_sext_i32_i8 flat_scratch_hi, s1
-// CHECK: [0x01,0x16,0xe7,0xbe]
-
-s_sext_i32_i8 vcc_lo, s1
-// CHECK: [0x01,0x16,0xea,0xbe]
-
-s_sext_i32_i8 vcc_hi, s1
-// CHECK: [0x01,0x16,0xeb,0xbe]
-
-s_sext_i32_i8 m0, s1
-// CHECK: [0x01,0x16,0xfc,0xbe]
-
-s_sext_i32_i8 exec_lo, s1
-// CHECK: [0x01,0x16,0xfe,0xbe]
-
-s_sext_i32_i8 exec_hi, s1
-// CHECK: [0x01,0x16,0xff,0xbe]
-
-s_sext_i32_i8 s5, s101
-// CHECK: [0x65,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, flat_scratch_lo
-// CHECK: [0x66,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, flat_scratch_hi
-// CHECK: [0x67,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, vcc_lo
-// CHECK: [0x6a,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, vcc_hi
-// CHECK: [0x6b,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, m0
-// CHECK: [0x7c,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, exec_lo
-// CHECK: [0x7e,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, exec_hi
-// CHECK: [0x7f,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, 0
-// CHECK: [0x80,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, -1
-// CHECK: [0xc1,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, 0.5
-// CHECK: [0xf0,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, -4.0
-// CHECK: [0xf7,0x16,0x85,0xbe]
-
-s_sext_i32_i8 s5, 0x71
-// CHECK: [0xff,0x16,0x85,0xbe,0x71,0x00,0x00,0x00]
-
-s_sext_i32_i8 s5, 0xf0
-// CHECK: [0xff,0x16,0x85,0xbe,0xf0,0x00,0x00,0x00]
-
-s_sext_i32_i16 s5, s1
-// CHECK: [0x01,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s101, s1
-// CHECK: [0x01,0x17,0xe5,0xbe]
-
-s_sext_i32_i16 flat_scratch_lo, s1
-// CHECK: [0x01,0x17,0xe6,0xbe]
-
-s_sext_i32_i16 flat_scratch_hi, s1
-// CHECK: [0x01,0x17,0xe7,0xbe]
-
-s_sext_i32_i16 vcc_lo, s1
-// CHECK: [0x01,0x17,0xea,0xbe]
-
-s_sext_i32_i16 vcc_hi, s1
-// CHECK: [0x01,0x17,0xeb,0xbe]
-
-s_sext_i32_i16 m0, s1
-// CHECK: [0x01,0x17,0xfc,0xbe]
-
-s_sext_i32_i16 exec_lo, s1
-// CHECK: [0x01,0x17,0xfe,0xbe]
-
-s_sext_i32_i16 exec_hi, s1
-// CHECK: [0x01,0x17,0xff,0xbe]
-
-s_sext_i32_i16 s5, s101
-// CHECK: [0x65,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, flat_scratch_lo
-// CHECK: [0x66,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, flat_scratch_hi
-// CHECK: [0x67,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, vcc_lo
-// CHECK: [0x6a,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, vcc_hi
-// CHECK: [0x6b,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, m0
-// CHECK: [0x7c,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, exec_lo
-// CHECK: [0x7e,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, exec_hi
-// CHECK: [0x7f,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, 0
-// CHECK: [0x80,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, -1
-// CHECK: [0xc1,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, 0.5
-// CHECK: [0xf0,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, -4.0
-// CHECK: [0xf7,0x17,0x85,0xbe]
-
-s_sext_i32_i16 s5, 0xfe0b
-// CHECK: [0xff,0x17,0x85,0xbe,0x0b,0xfe,0x00,0x00]
-
-s_sext_i32_i16 s5, 0x3456
-// CHECK: [0xff,0x17,0x85,0xbe,0x56,0x34,0x00,0x00]
-
-s_bitset0_b32 s5, s1
-// CHECK: [0x01,0x18,0x85,0xbe]
-
-s_bitset0_b32 s101, s1
-// CHECK: [0x01,0x18,0xe5,0xbe]
-
-s_bitset0_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x18,0xe6,0xbe]
-
-s_bitset0_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x18,0xe7,0xbe]
-
-s_bitset0_b32 vcc_lo, s1
-// CHECK: [0x01,0x18,0xea,0xbe]
-
-s_bitset0_b32 vcc_hi, s1
-// CHECK: [0x01,0x18,0xeb,0xbe]
-
-s_bitset0_b32 m0, s1
-// CHECK: [0x01,0x18,0xfc,0xbe]
-
-s_bitset0_b32 exec_lo, s1
-// CHECK: [0x01,0x18,0xfe,0xbe]
-
-s_bitset0_b32 exec_hi, s1
-// CHECK: [0x01,0x18,0xff,0xbe]
-
-s_bitset0_b32 s5, s101
-// CHECK: [0x65,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, vcc_lo
-// CHECK: [0x6a,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, vcc_hi
-// CHECK: [0x6b,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, m0
-// CHECK: [0x7c,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, exec_lo
-// CHECK: [0x7e,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, exec_hi
-// CHECK: [0x7f,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, 0
-// CHECK: [0x80,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, -1
-// CHECK: [0xc1,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, 0.5
-// CHECK: [0xf0,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, -4.0
-// CHECK: [0xf7,0x18,0x85,0xbe]
-
-s_bitset0_b32 s5, 0xaf123456
-// CHECK: [0xff,0x18,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset0_b32 s5, 0x3f717273
-// CHECK: [0xff,0x18,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset0_b64 s[10:11], s1
-// CHECK: [0x01,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[12:13], s1
-// CHECK: [0x01,0x19,0x8c,0xbe]
-
-s_bitset0_b64 s[100:101], s1
-// CHECK: [0x01,0x19,0xe4,0xbe]
-
-s_bitset0_b64 flat_scratch, s1
-// CHECK: [0x01,0x19,0xe6,0xbe]
-
-s_bitset0_b64 vcc, s1
-// CHECK: [0x01,0x19,0xea,0xbe]
-
-s_bitset0_b64 exec, s1
-// CHECK: [0x01,0x19,0xfe,0xbe]
-
-s_bitset0_b64 s[10:11], s101
-// CHECK: [0x65,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], flat_scratch_lo
-// CHECK: [0x66,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], flat_scratch_hi
-// CHECK: [0x67,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], vcc_lo
-// CHECK: [0x6a,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], vcc_hi
-// CHECK: [0x6b,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], m0
-// CHECK: [0x7c,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], exec_lo
-// CHECK: [0x7e,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], exec_hi
-// CHECK: [0x7f,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], 0
-// CHECK: [0x80,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], -1
-// CHECK: [0xc1,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x19,0x8a,0xbe]
-
-s_bitset0_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x19,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset0_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x19,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset1_b32 s5, s1
-// CHECK: [0x01,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s101, s1
-// CHECK: [0x01,0x1a,0xe5,0xbe]
-
-s_bitset1_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x1a,0xe6,0xbe]
-
-s_bitset1_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x1a,0xe7,0xbe]
-
-s_bitset1_b32 vcc_lo, s1
-// CHECK: [0x01,0x1a,0xea,0xbe]
-
-s_bitset1_b32 vcc_hi, s1
-// CHECK: [0x01,0x1a,0xeb,0xbe]
-
-s_bitset1_b32 m0, s1
-// CHECK: [0x01,0x1a,0xfc,0xbe]
-
-s_bitset1_b32 exec_lo, s1
-// CHECK: [0x01,0x1a,0xfe,0xbe]
-
-s_bitset1_b32 exec_hi, s1
-// CHECK: [0x01,0x1a,0xff,0xbe]
-
-s_bitset1_b32 s5, s101
-// CHECK: [0x65,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, vcc_lo
-// CHECK: [0x6a,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, vcc_hi
-// CHECK: [0x6b,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, m0
-// CHECK: [0x7c,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, exec_lo
-// CHECK: [0x7e,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, exec_hi
-// CHECK: [0x7f,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, 0
-// CHECK: [0x80,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, -1
-// CHECK: [0xc1,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, 0.5
-// CHECK: [0xf0,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, -4.0
-// CHECK: [0xf7,0x1a,0x85,0xbe]
-
-s_bitset1_b32 s5, 0xaf123456
-// CHECK: [0xff,0x1a,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset1_b32 s5, 0x3f717273
-// CHECK: [0xff,0x1a,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_bitset1_b64 s[10:11], s1
-// CHECK: [0x01,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[12:13], s1
-// CHECK: [0x01,0x1b,0x8c,0xbe]
-
-s_bitset1_b64 s[100:101], s1
-// CHECK: [0x01,0x1b,0xe4,0xbe]
-
-s_bitset1_b64 flat_scratch, s1
-// CHECK: [0x01,0x1b,0xe6,0xbe]
-
-s_bitset1_b64 vcc, s1
-// CHECK: [0x01,0x1b,0xea,0xbe]
-
-s_bitset1_b64 exec, s1
-// CHECK: [0x01,0x1b,0xfe,0xbe]
-
-s_bitset1_b64 s[10:11], s101
-// CHECK: [0x65,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], flat_scratch_lo
-// CHECK: [0x66,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], flat_scratch_hi
-// CHECK: [0x67,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], vcc_lo
-// CHECK: [0x6a,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], vcc_hi
-// CHECK: [0x6b,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], m0
-// CHECK: [0x7c,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], exec_lo
-// CHECK: [0x7e,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], exec_hi
-// CHECK: [0x7f,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], 0
-// CHECK: [0x80,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], -1
-// CHECK: [0xc1,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x1b,0x8a,0xbe]
-
-s_bitset1_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x1b,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_bitset1_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x1b,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_getpc_b64 s[10:11]
-// CHECK: [0x00,0x1c,0x8a,0xbe]
-
-s_getpc_b64 s[12:13]
-// CHECK: [0x00,0x1c,0x8c,0xbe]
-
-s_getpc_b64 s[100:101]
-// CHECK: [0x00,0x1c,0xe4,0xbe]
-
-s_getpc_b64 flat_scratch
-// CHECK: [0x00,0x1c,0xe6,0xbe]
-
-s_getpc_b64 vcc
-// CHECK: [0x00,0x1c,0xea,0xbe]
-
-s_getpc_b64 exec
-// CHECK: [0x00,0x1c,0xfe,0xbe]
-
-s_setpc_b64 s[2:3]
-// CHECK: [0x02,0x1d,0x80,0xbe]
-
-s_setpc_b64 s[4:5]
-// CHECK: [0x04,0x1d,0x80,0xbe]
-
-s_setpc_b64 s[100:101]
-// CHECK: [0x64,0x1d,0x80,0xbe]
-
-s_setpc_b64 flat_scratch
-// CHECK: [0x66,0x1d,0x80,0xbe]
-
-s_setpc_b64 vcc
-// CHECK: [0x6a,0x1d,0x80,0xbe]
-
-s_swappc_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x1e,0x8c,0xbe]
-
-s_swappc_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x1e,0xe4,0xbe]
-
-s_swappc_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x1e,0xe6,0xbe]
-
-s_swappc_b64 vcc, s[2:3]
-// CHECK: [0x02,0x1e,0xea,0xbe]
-
-s_swappc_b64 exec, s[2:3]
-// CHECK: [0x02,0x1e,0xfe,0xbe]
-
-s_swappc_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x1e,0x8a,0xbe]
-
-s_swappc_b64 s[10:11], vcc
-// CHECK: [0x6a,0x1e,0x8a,0xbe]
-
-s_rfe_b64 s[2:3]
-// CHECK: [0x02,0x1f,0x80,0xbe]
-
-s_rfe_b64 s[4:5]
-// CHECK: [0x04,0x1f,0x80,0xbe]
-
-s_rfe_b64 s[100:101]
-// CHECK: [0x64,0x1f,0x80,0xbe]
-
-s_rfe_b64 flat_scratch
-// CHECK: [0x66,0x1f,0x80,0xbe]
-
-s_rfe_b64 vcc
-// CHECK: [0x6a,0x1f,0x80,0xbe]
-
-s_and_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x20,0x8c,0xbe]
-
-s_and_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x20,0xe4,0xbe]
-
-s_and_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x20,0xe6,0xbe]
-
-s_and_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x20,0xea,0xbe]
-
-s_and_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x20,0x8a,0xbe]
-
-s_and_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x20,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_and_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x20,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_or_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x21,0x8c,0xbe]
-
-s_or_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x21,0xe4,0xbe]
-
-s_or_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x21,0xe6,0xbe]
-
-s_or_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x21,0xea,0xbe]
-
-s_or_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x21,0x8a,0xbe]
-
-s_or_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x21,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_or_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x21,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xor_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x22,0x8c,0xbe]
-
-s_xor_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x22,0xe4,0xbe]
-
-s_xor_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x22,0xe6,0xbe]
-
-s_xor_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x22,0xea,0xbe]
-
-s_xor_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x22,0x8a,0xbe]
-
-s_xor_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x22,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xor_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x22,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_andn2_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x23,0x8c,0xbe]
-
-s_andn2_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x23,0xe4,0xbe]
-
-s_andn2_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x23,0xe6,0xbe]
-
-s_andn2_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x23,0xea,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x23,0x8a,0xbe]
-
-s_andn2_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x23,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_andn2_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x23,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_orn2_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x24,0x8c,0xbe]
-
-s_orn2_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x24,0xe4,0xbe]
-
-s_orn2_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x24,0xe6,0xbe]
-
-s_orn2_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x24,0xea,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x24,0x8a,0xbe]
-
-s_orn2_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x24,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_orn2_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x24,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nand_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x25,0x8c,0xbe]
-
-s_nand_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x25,0xe4,0xbe]
-
-s_nand_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x25,0xe6,0xbe]
-
-s_nand_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x25,0xea,0xbe]
-
-s_nand_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x25,0x8a,0xbe]
-
-s_nand_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x25,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nand_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x25,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_nor_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x26,0x8c,0xbe]
-
-s_nor_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x26,0xe4,0xbe]
-
-s_nor_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x26,0xe6,0xbe]
-
-s_nor_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x26,0xea,0xbe]
-
-s_nor_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x26,0x8a,0xbe]
-
-s_nor_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x26,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_nor_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x26,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_xnor_saveexec_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x27,0x8c,0xbe]
-
-s_xnor_saveexec_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x27,0xe4,0xbe]
-
-s_xnor_saveexec_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x27,0xe6,0xbe]
-
-s_xnor_saveexec_b64 vcc, s[2:3]
-// CHECK: [0x02,0x27,0xea,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], vcc
-// CHECK: [0x6a,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], exec
-// CHECK: [0x7e,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], 0
-// CHECK: [0x80,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], -1
-// CHECK: [0xc1,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x27,0x8a,0xbe]
-
-s_xnor_saveexec_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x27,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_xnor_saveexec_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x27,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_quadmask_b32 s5, s1
-// CHECK: [0x01,0x28,0x85,0xbe]
-
-s_quadmask_b32 s101, s1
-// CHECK: [0x01,0x28,0xe5,0xbe]
-
-s_quadmask_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x28,0xe6,0xbe]
-
-s_quadmask_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x28,0xe7,0xbe]
-
-s_quadmask_b32 vcc_lo, s1
-// CHECK: [0x01,0x28,0xea,0xbe]
-
-s_quadmask_b32 vcc_hi, s1
-// CHECK: [0x01,0x28,0xeb,0xbe]
-
-s_quadmask_b32 m0, s1
-// CHECK: [0x01,0x28,0xfc,0xbe]
-
-s_quadmask_b32 exec_lo, s1
-// CHECK: [0x01,0x28,0xfe,0xbe]
-
-s_quadmask_b32 exec_hi, s1
-// CHECK: [0x01,0x28,0xff,0xbe]
-
-s_quadmask_b32 s5, s101
-// CHECK: [0x65,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, vcc_lo
-// CHECK: [0x6a,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, vcc_hi
-// CHECK: [0x6b,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, m0
-// CHECK: [0x7c,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, exec_lo
-// CHECK: [0x7e,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, exec_hi
-// CHECK: [0x7f,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, 0
-// CHECK: [0x80,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, -1
-// CHECK: [0xc1,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, 0.5
-// CHECK: [0xf0,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, -4.0
-// CHECK: [0xf7,0x28,0x85,0xbe]
-
-s_quadmask_b32 s5, 0xaf123456
-// CHECK: [0xff,0x28,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_quadmask_b32 s5, 0x3f717273
-// CHECK: [0xff,0x28,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_quadmask_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x29,0x8c,0xbe]
-
-s_quadmask_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x29,0xe4,0xbe]
-
-s_quadmask_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x29,0xe6,0xbe]
-
-s_quadmask_b64 vcc, s[2:3]
-// CHECK: [0x02,0x29,0xea,0xbe]
-
-s_quadmask_b64 exec, s[2:3]
-// CHECK: [0x02,0x29,0xfe,0xbe]
-
-s_quadmask_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], vcc
-// CHECK: [0x6a,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], exec
-// CHECK: [0x7e,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], 0
-// CHECK: [0x80,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], -1
-// CHECK: [0xc1,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x29,0x8a,0xbe]
-
-s_quadmask_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x29,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_quadmask_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x29,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_movrels_b32 s5, s1
-// CHECK: [0x01,0x2a,0x85,0xbe]
-
-s_movrels_b32 s101, s1
-// CHECK: [0x01,0x2a,0xe5,0xbe]
-
-s_movrels_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x2a,0xe6,0xbe]
-
-s_movrels_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x2a,0xe7,0xbe]
-
-s_movrels_b32 vcc_lo, s1
-// CHECK: [0x01,0x2a,0xea,0xbe]
-
-s_movrels_b32 vcc_hi, s1
-// CHECK: [0x01,0x2a,0xeb,0xbe]
-
-s_movrels_b32 m0, s1
-// CHECK: [0x01,0x2a,0xfc,0xbe]
-
-s_movrels_b32 exec_lo, s1
-// CHECK: [0x01,0x2a,0xfe,0xbe]
-
-s_movrels_b32 exec_hi, s1
-// CHECK: [0x01,0x2a,0xff,0xbe]
-
-s_movrels_b32 s5, s101
-// CHECK: [0x65,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, vcc_lo
-// CHECK: [0x6a,0x2a,0x85,0xbe]
-
-s_movrels_b32 s5, vcc_hi
-// CHECK: [0x6b,0x2a,0x85,0xbe]
-
-s_movrels_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x2b,0x8c,0xbe]
-
-s_movrels_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x2b,0xe4,0xbe]
-
-s_movrels_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x2b,0xe6,0xbe]
-
-s_movrels_b64 vcc, s[2:3]
-// CHECK: [0x02,0x2b,0xea,0xbe]
-
-s_movrels_b64 exec, s[2:3]
-// CHECK: [0x02,0x2b,0xfe,0xbe]
-
-s_movrels_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x2b,0x8a,0xbe]
-
-s_movrels_b64 s[10:11], vcc
-// CHECK: [0x6a,0x2b,0x8a,0xbe]
-
-s_movreld_b32 s5, s1
-// CHECK: [0x01,0x2c,0x85,0xbe]
-
-s_movreld_b32 s101, s1
-// CHECK: [0x01,0x2c,0xe5,0xbe]
-
-s_movreld_b32 flat_scratch_lo, s1
-// CHECK: [0x01,0x2c,0xe6,0xbe]
-
-s_movreld_b32 flat_scratch_hi, s1
-// CHECK: [0x01,0x2c,0xe7,0xbe]
-
-s_movreld_b32 vcc_lo, s1
-// CHECK: [0x01,0x2c,0xea,0xbe]
-
-s_movreld_b32 vcc_hi, s1
-// CHECK: [0x01,0x2c,0xeb,0xbe]
-
-s_movreld_b32 s5, s101
-// CHECK: [0x65,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, flat_scratch_lo
-// CHECK: [0x66,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, flat_scratch_hi
-// CHECK: [0x67,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, vcc_lo
-// CHECK: [0x6a,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, vcc_hi
-// CHECK: [0x6b,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, m0
-// CHECK: [0x7c,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, 0
-// CHECK: [0x80,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, -1
-// CHECK: [0xc1,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, 0.5
-// CHECK: [0xf0,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, -4.0
-// CHECK: [0xf7,0x2c,0x85,0xbe]
-
-s_movreld_b32 s5, 0xaf123456
-// CHECK: [0xff,0x2c,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_movreld_b32 s5, 0x3f717273
-// CHECK: [0xff,0x2c,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_movreld_b64 s[10:11], s[2:3]
-// CHECK: [0x02,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[12:13], s[2:3]
-// CHECK: [0x02,0x2d,0x8c,0xbe]
-
-s_movreld_b64 s[100:101], s[2:3]
-// CHECK: [0x02,0x2d,0xe4,0xbe]
-
-s_movreld_b64 flat_scratch, s[2:3]
-// CHECK: [0x02,0x2d,0xe6,0xbe]
-
-s_movreld_b64 vcc, s[2:3]
-// CHECK: [0x02,0x2d,0xea,0xbe]
-
-s_movreld_b64 s[10:11], s[4:5]
-// CHECK: [0x04,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], s[100:101]
-// CHECK: [0x64,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], flat_scratch
-// CHECK: [0x66,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], vcc
-// CHECK: [0x6a,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], 0
-// CHECK: [0x80,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], -1
-// CHECK: [0xc1,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], 0.5
-// CHECK: [0xf0,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], -4.0
-// CHECK: [0xf7,0x2d,0x8a,0xbe]
-
-s_movreld_b64 s[10:11], 0xaf123456
-// CHECK: [0xff,0x2d,0x8a,0xbe,0x56,0x34,0x12,0xaf]
-
-s_movreld_b64 s[10:11], 0x3f717273
-// CHECK: [0xff,0x2d,0x8a,0xbe,0x73,0x72,0x71,0x3f]
-
-s_cbranch_join s1
-// CHECK: [0x01,0x2e,0x80,0xbe]
-
-s_cbranch_join s101
-// CHECK: [0x65,0x2e,0x80,0xbe]
-
-s_cbranch_join flat_scratch_lo
-// CHECK: [0x66,0x2e,0x80,0xbe]
-
-s_cbranch_join flat_scratch_hi
-// CHECK: [0x67,0x2e,0x80,0xbe]
-
-s_cbranch_join vcc_lo
-// CHECK: [0x6a,0x2e,0x80,0xbe]
-
-s_cbranch_join vcc_hi
-// CHECK: [0x6b,0x2e,0x80,0xbe]
-
-s_abs_i32 s5, s1
-// CHECK: [0x01,0x30,0x85,0xbe]
-
-s_abs_i32 s101, s1
-// CHECK: [0x01,0x30,0xe5,0xbe]
-
-s_abs_i32 flat_scratch_lo, s1
-// CHECK: [0x01,0x30,0xe6,0xbe]
-
-s_abs_i32 flat_scratch_hi, s1
-// CHECK: [0x01,0x30,0xe7,0xbe]
-
-s_abs_i32 vcc_lo, s1
-// CHECK: [0x01,0x30,0xea,0xbe]
-
-s_abs_i32 vcc_hi, s1
-// CHECK: [0x01,0x30,0xeb,0xbe]
-
-s_abs_i32 m0, s1
-// CHECK: [0x01,0x30,0xfc,0xbe]
-
-s_abs_i32 exec_lo, s1
-// CHECK: [0x01,0x30,0xfe,0xbe]
-
-s_abs_i32 exec_hi, s1
-// CHECK: [0x01,0x30,0xff,0xbe]
-
-s_abs_i32 s5, s101
-// CHECK: [0x65,0x30,0x85,0xbe]
-
-s_abs_i32 s5, flat_scratch_lo
-// CHECK: [0x66,0x30,0x85,0xbe]
-
-s_abs_i32 s5, flat_scratch_hi
-// CHECK: [0x67,0x30,0x85,0xbe]
-
-s_abs_i32 s5, vcc_lo
-// CHECK: [0x6a,0x30,0x85,0xbe]
-
-s_abs_i32 s5, vcc_hi
-// CHECK: [0x6b,0x30,0x85,0xbe]
-
-s_abs_i32 s5, m0
-// CHECK: [0x7c,0x30,0x85,0xbe]
-
-s_abs_i32 s5, exec_lo
-// CHECK: [0x7e,0x30,0x85,0xbe]
-
-s_abs_i32 s5, exec_hi
-// CHECK: [0x7f,0x30,0x85,0xbe]
-
-s_abs_i32 s5, 0
-// CHECK: [0x80,0x30,0x85,0xbe]
-
-s_abs_i32 s5, -1
-// CHECK: [0xc1,0x30,0x85,0xbe]
-
-s_abs_i32 s5, 0.5
-// CHECK: [0xf0,0x30,0x85,0xbe]
-
-s_abs_i32 s5, -4.0
-// CHECK: [0xf7,0x30,0x85,0xbe]
-
-s_abs_i32 s5, 0xaf123456
-// CHECK: [0xff,0x30,0x85,0xbe,0x56,0x34,0x12,0xaf]
-
-s_abs_i32 s5, 0x3f717273
-// CHECK: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f]
-
-s_set_gpr_idx_idx s1
-// CHECK: [0x01,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx s101
-// CHECK: [0x65,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx flat_scratch_lo
-// CHECK: [0x66,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx flat_scratch_hi
-// CHECK: [0x67,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx vcc_lo
-// CHECK: [0x6a,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx vcc_hi
-// CHECK: [0x6b,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx m0
-// CHECK: [0x7c,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx 0
-// CHECK: [0x80,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx -1
-// CHECK: [0xc1,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx 0.5
-// CHECK: [0xf0,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx -4.0
-// CHECK: [0xf7,0x32,0x80,0xbe]
-
-s_set_gpr_idx_idx 0xaf123456
-// CHECK: [0xff,0x32,0x80,0xbe,0x56,0x34,0x12,0xaf]
-
-s_set_gpr_idx_idx 0x3f717273
-// CHECK: [0xff,0x32,0x80,0xbe,0x73,0x72,0x71,0x3f]
-
-s_add_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x80]
-
-s_add_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x80]
-
-s_add_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x80]
-
-s_add_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x80]
-
-s_add_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x80]
-
-s_add_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x80]
-
-s_add_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x80]
-
-s_add_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x80]
-
-s_add_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x80]
-
-s_add_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x80]
-
-s_add_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x80]
-
-s_add_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x80]
-
-s_add_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x80]
-
-s_add_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x80]
-
-s_add_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x80]
-
-s_add_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x80]
-
-s_add_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x80]
-
-s_add_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x80]
-
-s_add_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x80]
-
-s_add_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x80]
-
-s_add_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x80]
-
-s_add_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x80,0x56,0x34,0x12,0xaf]
-
-s_add_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x80,0x73,0x72,0x71,0x3f]
-
-s_add_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x80]
-
-s_add_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x80]
-
-s_add_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x80]
-
-s_add_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x80]
-
-s_add_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x80]
-
-s_add_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x80]
-
-s_add_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x80]
-
-s_add_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x80]
-
-s_add_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x80]
-
-s_add_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x80]
-
-s_add_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x80]
-
-s_add_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x80]
-
-s_add_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x80,0x56,0x34,0x12,0xaf]
-
-s_add_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x80,0x73,0x72,0x71,0x3f]
-
-s_sub_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x80]
-
-s_sub_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x80]
-
-s_sub_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x80]
-
-s_sub_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x80]
-
-s_sub_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x80]
-
-s_sub_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x80]
-
-s_sub_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x80]
-
-s_sub_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x80]
-
-s_sub_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x80]
-
-s_sub_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x80]
-
-s_sub_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x80]
-
-s_sub_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x80]
-
-s_sub_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x80]
-
-s_sub_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x80]
-
-s_sub_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x80]
-
-s_sub_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x80]
-
-s_sub_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x80]
-
-s_sub_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x80]
-
-s_sub_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x80]
-
-s_sub_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x80]
-
-s_sub_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x80]
-
-s_sub_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x80,0x56,0x34,0x12,0xaf]
-
-s_sub_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x80,0x73,0x72,0x71,0x3f]
-
-s_sub_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x80]
-
-s_sub_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x80]
-
-s_sub_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x80]
-
-s_sub_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x80]
-
-s_sub_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x80]
-
-s_sub_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x80]
-
-s_sub_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x80]
-
-s_sub_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x80]
-
-s_sub_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x80]
-
-s_sub_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x80]
-
-s_sub_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x80]
-
-s_sub_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x80]
-
-s_sub_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x80,0x56,0x34,0x12,0xaf]
-
-s_sub_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x80,0x73,0x72,0x71,0x3f]
-
-s_add_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x81]
-
-s_add_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x81]
-
-s_add_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x81]
-
-s_add_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x81]
-
-s_add_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x81]
-
-s_add_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x81]
-
-s_add_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x81]
-
-s_add_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x81]
-
-s_add_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x81]
-
-s_add_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x81]
-
-s_add_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x81]
-
-s_add_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x81]
-
-s_add_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x81]
-
-s_add_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x81]
-
-s_add_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x81]
-
-s_add_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x81]
-
-s_add_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x81]
-
-s_add_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x81]
-
-s_add_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x81]
-
-s_add_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x81]
-
-s_add_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x81]
-
-s_add_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x81,0x56,0x34,0x12,0xaf]
-
-s_add_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x81,0x73,0x72,0x71,0x3f]
-
-s_add_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x81]
-
-s_add_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x81]
-
-s_add_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x81]
-
-s_add_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x81]
-
-s_add_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x81]
-
-s_add_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x81]
-
-s_add_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x81]
-
-s_add_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x81]
-
-s_add_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x81]
-
-s_add_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x81]
-
-s_add_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x81]
-
-s_add_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x81]
-
-s_add_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x81,0x56,0x34,0x12,0xaf]
-
-s_add_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x81,0x73,0x72,0x71,0x3f]
-
-s_sub_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x81]
-
-s_sub_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x81]
-
-s_sub_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x81]
-
-s_sub_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x81]
-
-s_sub_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x81]
-
-s_sub_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x81]
-
-s_sub_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x81]
-
-s_sub_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x81]
-
-s_sub_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x81]
-
-s_sub_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x81]
-
-s_sub_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x81]
-
-s_sub_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x81]
-
-s_sub_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x81]
-
-s_sub_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x81]
-
-s_sub_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x81]
-
-s_sub_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x81]
-
-s_sub_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x81]
-
-s_sub_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x81]
-
-s_sub_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x81]
-
-s_sub_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x81]
-
-s_sub_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x81]
-
-s_sub_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x81,0x56,0x34,0x12,0xaf]
-
-s_sub_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x81,0x73,0x72,0x71,0x3f]
-
-s_sub_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x81]
-
-s_sub_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x81]
-
-s_sub_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x81]
-
-s_sub_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x81]
-
-s_sub_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x81]
-
-s_sub_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x81]
-
-s_sub_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x81]
-
-s_sub_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x81]
-
-s_sub_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x81]
-
-s_sub_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x81]
-
-s_sub_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x81]
-
-s_sub_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x81]
-
-s_sub_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x81,0x56,0x34,0x12,0xaf]
-
-s_sub_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x81,0x73,0x72,0x71,0x3f]
-
-s_addc_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x82]
-
-s_addc_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x82]
-
-s_addc_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x82]
-
-s_addc_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x82]
-
-s_addc_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x82]
-
-s_addc_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x82]
-
-s_addc_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x82]
-
-s_addc_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x82]
-
-s_addc_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x82]
-
-s_addc_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x82]
-
-s_addc_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x82]
-
-s_addc_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x82]
-
-s_addc_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x82]
-
-s_addc_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x82]
-
-s_addc_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x82]
-
-s_addc_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x82]
-
-s_addc_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x82]
-
-s_addc_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x82]
-
-s_addc_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x82]
-
-s_addc_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x82]
-
-s_addc_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x82]
-
-s_addc_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x82,0x56,0x34,0x12,0xaf]
-
-s_addc_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x82,0x73,0x72,0x71,0x3f]
-
-s_addc_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x82]
-
-s_addc_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x82]
-
-s_addc_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x82]
-
-s_addc_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x82]
-
-s_addc_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x82]
-
-s_addc_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x82]
-
-s_addc_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x82]
-
-s_addc_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x82]
-
-s_addc_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x82]
-
-s_addc_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x82]
-
-s_addc_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x82]
-
-s_addc_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x82]
-
-s_addc_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x82,0x56,0x34,0x12,0xaf]
-
-s_addc_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x82,0x73,0x72,0x71,0x3f]
-
-s_subb_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x82]
-
-s_subb_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x82]
-
-s_subb_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x82]
-
-s_subb_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x82]
-
-s_subb_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x82]
-
-s_subb_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x82]
-
-s_subb_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x82]
-
-s_subb_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x82]
-
-s_subb_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x82]
-
-s_subb_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x82]
-
-s_subb_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x82]
-
-s_subb_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x82]
-
-s_subb_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x82]
-
-s_subb_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x82]
-
-s_subb_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x82]
-
-s_subb_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x82]
-
-s_subb_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x82]
-
-s_subb_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x82]
-
-s_subb_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x82]
-
-s_subb_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x82]
-
-s_subb_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x82]
-
-s_subb_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x82,0x56,0x34,0x12,0xaf]
-
-s_subb_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x82,0x73,0x72,0x71,0x3f]
-
-s_subb_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x82]
-
-s_subb_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x82]
-
-s_subb_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x82]
-
-s_subb_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x82]
-
-s_subb_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x82]
-
-s_subb_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x82]
-
-s_subb_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x82]
-
-s_subb_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x82]
-
-s_subb_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x82]
-
-s_subb_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x82]
-
-s_subb_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x82]
-
-s_subb_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x82]
-
-s_subb_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x82,0x56,0x34,0x12,0xaf]
-
-s_subb_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x82,0x73,0x72,0x71,0x3f]
-
-s_min_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x83]
-
-s_min_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x83]
-
-s_min_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x83]
-
-s_min_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x83]
-
-s_min_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x83]
-
-s_min_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x83]
-
-s_min_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x83]
-
-s_min_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x83]
-
-s_min_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x83]
-
-s_min_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x83]
-
-s_min_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x83]
-
-s_min_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x83]
-
-s_min_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x83]
-
-s_min_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x83]
-
-s_min_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x83]
-
-s_min_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x83]
-
-s_min_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x83]
-
-s_min_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x83]
-
-s_min_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x83]
-
-s_min_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x83]
-
-s_min_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x83]
-
-s_min_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x83]
-
-s_min_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x83]
-
-s_min_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x83]
-
-s_min_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x83]
-
-s_min_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x83]
-
-s_min_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x83]
-
-s_min_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x83]
-
-s_min_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x83]
-
-s_min_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x83]
-
-s_min_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x83]
-
-s_min_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x83]
-
-s_min_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x83]
-
-s_min_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x83]
-
-s_min_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x83]
-
-s_min_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x83]
-
-s_min_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x83]
-
-s_min_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x83]
-
-s_min_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x83]
-
-s_min_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x83]
-
-s_min_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x83]
-
-s_min_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x83]
-
-s_min_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x83]
-
-s_min_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x83]
-
-s_min_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x83]
-
-s_min_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x83]
-
-s_min_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x83]
-
-s_min_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x83]
-
-s_min_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x83]
-
-s_min_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x83]
-
-s_min_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x83]
-
-s_min_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x83]
-
-s_min_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x83]
-
-s_min_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x83]
-
-s_min_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x83,0x73,0x72,0x71,0x3f]
-
-s_min_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x83]
-
-s_min_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x83]
-
-s_min_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x83]
-
-s_min_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x83]
-
-s_min_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x83]
-
-s_min_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x83]
-
-s_min_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x83]
-
-s_min_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x83]
-
-s_min_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x83]
-
-s_min_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x83]
-
-s_min_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x83]
-
-s_min_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x83]
-
-s_min_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x83,0x56,0x34,0x12,0xaf]
-
-s_min_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x83,0x73,0x72,0x71,0x3f]
-
-s_max_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x84]
-
-s_max_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x84]
-
-s_max_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x84]
-
-s_max_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x84]
-
-s_max_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x84]
-
-s_max_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x84]
-
-s_max_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x84]
-
-s_max_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x84]
-
-s_max_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x84]
-
-s_max_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x84]
-
-s_max_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x84]
-
-s_max_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x84]
-
-s_max_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x84]
-
-s_max_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x84]
-
-s_max_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x84]
-
-s_max_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x84]
-
-s_max_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x84]
-
-s_max_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x84]
-
-s_max_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x84]
-
-s_max_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x84]
-
-s_max_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x84]
-
-s_max_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x84]
-
-s_max_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x84]
-
-s_max_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x84]
-
-s_max_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x84]
-
-s_max_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x84]
-
-s_max_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x84]
-
-s_max_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x84]
-
-s_max_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x84]
-
-s_max_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x84]
-
-s_max_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x84]
-
-s_max_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x84]
-
-s_max_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x84]
-
-s_max_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x84]
-
-s_max_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x84]
-
-s_max_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x84]
-
-s_max_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x84]
-
-s_max_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x84]
-
-s_max_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x84]
-
-s_max_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x84]
-
-s_max_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x84]
-
-s_max_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x84]
-
-s_max_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x84]
-
-s_max_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x84]
-
-s_max_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x84]
-
-s_max_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x84]
-
-s_max_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x84]
-
-s_max_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x84]
-
-s_max_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x84]
-
-s_max_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x84]
-
-s_max_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x84]
-
-s_max_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x84]
-
-s_max_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x84]
-
-s_max_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x84]
-
-s_max_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x84,0x73,0x72,0x71,0x3f]
-
-s_max_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x84]
-
-s_max_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x84]
-
-s_max_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x84]
-
-s_max_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x84]
-
-s_max_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x84]
-
-s_max_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x84]
-
-s_max_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x84]
-
-s_max_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x84]
-
-s_max_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x84]
-
-s_max_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x84]
-
-s_max_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x84]
-
-s_max_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x84]
-
-s_max_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x84,0x56,0x34,0x12,0xaf]
-
-s_max_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x84,0x73,0x72,0x71,0x3f]
-
-s_cselect_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x85]
-
-s_cselect_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x85]
-
-s_cselect_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x85]
-
-s_cselect_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x85]
-
-s_cselect_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x85]
-
-s_cselect_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x85]
-
-s_cselect_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x85]
-
-s_cselect_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x85]
-
-s_cselect_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x85]
-
-s_cselect_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x85]
-
-s_cselect_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x85]
-
-s_cselect_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x85]
-
-s_cselect_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x85]
-
-s_cselect_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x85]
-
-s_cselect_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x85]
-
-s_cselect_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x85]
-
-s_cselect_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x85]
-
-s_cselect_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x85]
-
-s_cselect_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x85]
-
-s_cselect_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x85]
-
-s_cselect_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x85]
-
-s_cselect_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x85]
-
-s_cselect_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x85]
-
-s_cselect_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x85]
-
-s_cselect_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x85]
-
-s_cselect_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x85]
-
-s_cselect_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x85]
-
-s_cselect_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x85]
-
-s_cselect_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x85]
-
-s_cselect_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x85]
-
-s_cselect_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x85]
-
-s_cselect_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x85]
-
-s_cselect_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x85]
-
-s_cselect_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x85]
-
-s_cselect_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x85]
-
-s_cselect_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x85]
-
-s_cselect_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x85]
-
-s_cselect_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x85]
-
-s_cselect_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x85]
-
-s_cselect_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x85]
-
-s_cselect_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x85,0x73,0x72,0x71,0x3f]
-
-s_cselect_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x85]
-
-s_cselect_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x85,0x56,0x34,0x12,0xaf]
-
-s_cselect_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x85,0x73,0x72,0x71,0x3f]
-
-s_and_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x86]
-
-s_and_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x86]
-
-s_and_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x86]
-
-s_and_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x86]
-
-s_and_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x86]
-
-s_and_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x86]
-
-s_and_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x86]
-
-s_and_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x86]
-
-s_and_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x86]
-
-s_and_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x86]
-
-s_and_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x86]
-
-s_and_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x86]
-
-s_and_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x86]
-
-s_and_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x86]
-
-s_and_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x86]
-
-s_and_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x86]
-
-s_and_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x86]
-
-s_and_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x86]
-
-s_and_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x86]
-
-s_and_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x86]
-
-s_and_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x86]
-
-s_and_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x86,0x56,0x34,0x12,0xaf]
-
-s_and_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x86,0x73,0x72,0x71,0x3f]
-
-s_and_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x86]
-
-s_and_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x86]
-
-s_and_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x86]
-
-s_and_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x86]
-
-s_and_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x86]
-
-s_and_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x86]
-
-s_and_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x86]
-
-s_and_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x86]
-
-s_and_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x86]
-
-s_and_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x86]
-
-s_and_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x86]
-
-s_and_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x86]
-
-s_and_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x86,0x56,0x34,0x12,0xaf]
-
-s_and_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x86,0x73,0x72,0x71,0x3f]
-
-s_and_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x86]
-
-s_and_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x86]
-
-s_and_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x86]
-
-s_and_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x86]
-
-s_and_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x86]
-
-s_and_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x86]
-
-s_and_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x86]
-
-s_and_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x86,0x56,0x34,0x12,0xaf]
-
-s_and_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x86,0x73,0x72,0x71,0x3f]
-
-s_and_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x86]
-
-s_and_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x86,0x56,0x34,0x12,0xaf]
-
-s_and_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x86,0x73,0x72,0x71,0x3f]
-
-s_or_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x87]
-
-s_or_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x87]
-
-s_or_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x87]
-
-s_or_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x87]
-
-s_or_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x87]
-
-s_or_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x87]
-
-s_or_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x87]
-
-s_or_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x87]
-
-s_or_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x87]
-
-s_or_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x87]
-
-s_or_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x87]
-
-s_or_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x87]
-
-s_or_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x87]
-
-s_or_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x87]
-
-s_or_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x87]
-
-s_or_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x87]
-
-s_or_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x87]
-
-s_or_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x87]
-
-s_or_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x87]
-
-s_or_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x87]
-
-s_or_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x87]
-
-s_or_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x87,0x56,0x34,0x12,0xaf]
-
-s_or_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x87,0x73,0x72,0x71,0x3f]
-
-s_or_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x87]
-
-s_or_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x87]
-
-s_or_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x87]
-
-s_or_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x87]
-
-s_or_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x87]
-
-s_or_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x87]
-
-s_or_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x87]
-
-s_or_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x87]
-
-s_or_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x87]
-
-s_or_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x87]
-
-s_or_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x87]
-
-s_or_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x87]
-
-s_or_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x87,0x56,0x34,0x12,0xaf]
-
-s_or_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x87,0x73,0x72,0x71,0x3f]
-
-s_or_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x87]
-
-s_or_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x87]
-
-s_or_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x87]
-
-s_or_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x87]
-
-s_or_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x87]
-
-s_or_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x87]
-
-s_or_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x87]
-
-s_or_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x87,0x56,0x34,0x12,0xaf]
-
-s_or_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x87,0x73,0x72,0x71,0x3f]
-
-s_or_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x87]
-
-s_or_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x87,0x56,0x34,0x12,0xaf]
-
-s_or_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x87,0x73,0x72,0x71,0x3f]
-
-s_xor_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x88]
-
-s_xor_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x88]
-
-s_xor_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x88]
-
-s_xor_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x88]
-
-s_xor_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x88]
-
-s_xor_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x88]
-
-s_xor_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x88]
-
-s_xor_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x88]
-
-s_xor_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x88]
-
-s_xor_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x88]
-
-s_xor_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x88]
-
-s_xor_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x88]
-
-s_xor_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x88]
-
-s_xor_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x88]
-
-s_xor_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x88]
-
-s_xor_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x88]
-
-s_xor_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x88]
-
-s_xor_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x88]
-
-s_xor_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x88]
-
-s_xor_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x88]
-
-s_xor_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x88]
-
-s_xor_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x88,0x56,0x34,0x12,0xaf]
-
-s_xor_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x88,0x73,0x72,0x71,0x3f]
-
-s_xor_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x88]
-
-s_xor_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x88]
-
-s_xor_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x88]
-
-s_xor_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x88]
-
-s_xor_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x88]
-
-s_xor_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x88]
-
-s_xor_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x88]
-
-s_xor_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x88]
-
-s_xor_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x88]
-
-s_xor_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x88]
-
-s_xor_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x88]
-
-s_xor_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x88]
-
-s_xor_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x88,0x56,0x34,0x12,0xaf]
-
-s_xor_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x88,0x73,0x72,0x71,0x3f]
-
-s_xor_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x88]
-
-s_xor_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x88]
-
-s_xor_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x88]
-
-s_xor_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x88]
-
-s_xor_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x88]
-
-s_xor_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x88]
-
-s_xor_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x88]
-
-s_xor_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x88,0x56,0x34,0x12,0xaf]
-
-s_xor_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x88,0x73,0x72,0x71,0x3f]
-
-s_xor_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x88]
-
-s_xor_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x88,0x56,0x34,0x12,0xaf]
-
-s_xor_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x88,0x73,0x72,0x71,0x3f]
-
-s_andn2_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x89]
-
-s_andn2_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x89]
-
-s_andn2_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x89]
-
-s_andn2_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x89]
-
-s_andn2_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x89]
-
-s_andn2_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x89]
-
-s_andn2_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x89]
-
-s_andn2_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x89]
-
-s_andn2_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x89]
-
-s_andn2_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x89]
-
-s_andn2_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x89]
-
-s_andn2_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x89]
-
-s_andn2_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x89]
-
-s_andn2_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x89]
-
-s_andn2_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x89]
-
-s_andn2_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x89]
-
-s_andn2_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x89]
-
-s_andn2_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x89]
-
-s_andn2_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x89]
-
-s_andn2_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x89]
-
-s_andn2_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x89]
-
-s_andn2_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x89,0x56,0x34,0x12,0xaf]
-
-s_andn2_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x89,0x73,0x72,0x71,0x3f]
-
-s_andn2_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x89]
-
-s_andn2_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x89]
-
-s_andn2_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x89]
-
-s_andn2_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x89]
-
-s_andn2_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x89]
-
-s_andn2_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x89]
-
-s_andn2_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x89]
-
-s_andn2_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x89]
-
-s_andn2_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x89]
-
-s_andn2_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x89]
-
-s_andn2_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x89]
-
-s_andn2_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x89]
-
-s_andn2_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x89,0x56,0x34,0x12,0xaf]
-
-s_andn2_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x89,0x73,0x72,0x71,0x3f]
-
-s_andn2_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x89]
-
-s_andn2_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x89]
-
-s_andn2_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x89]
-
-s_andn2_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x89]
-
-s_andn2_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x89]
-
-s_andn2_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x89]
-
-s_andn2_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x89]
-
-s_andn2_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x89,0x56,0x34,0x12,0xaf]
-
-s_andn2_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x89,0x73,0x72,0x71,0x3f]
-
-s_andn2_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x89]
-
-s_andn2_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x89,0x56,0x34,0x12,0xaf]
-
-s_andn2_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x89,0x73,0x72,0x71,0x3f]
-
-s_orn2_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8a]
-
-s_orn2_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8a]
-
-s_orn2_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8a]
-
-s_orn2_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8a]
-
-s_orn2_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8a]
-
-s_orn2_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8a]
-
-s_orn2_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8a]
-
-s_orn2_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8a]
-
-s_orn2_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8a]
-
-s_orn2_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8a]
-
-s_orn2_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8a,0x56,0x34,0x12,0xaf]
-
-s_orn2_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8a,0x73,0x72,0x71,0x3f]
-
-s_orn2_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8a]
-
-s_orn2_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8a]
-
-s_orn2_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8a]
-
-s_orn2_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8a]
-
-s_orn2_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8a]
-
-s_orn2_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8a]
-
-s_orn2_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8a]
-
-s_orn2_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8a]
-
-s_orn2_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8a]
-
-s_orn2_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8a]
-
-s_orn2_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8a]
-
-s_orn2_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8a]
-
-s_orn2_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8a,0x56,0x34,0x12,0xaf]
-
-s_orn2_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8a,0x73,0x72,0x71,0x3f]
-
-s_orn2_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8a]
-
-s_orn2_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x8a]
-
-s_orn2_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8a]
-
-s_orn2_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8a]
-
-s_orn2_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8a]
-
-s_orn2_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8a,0x56,0x34,0x12,0xaf]
-
-s_orn2_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8a,0x73,0x72,0x71,0x3f]
-
-s_orn2_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8a]
-
-s_orn2_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8a,0x56,0x34,0x12,0xaf]
-
-s_orn2_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8a,0x73,0x72,0x71,0x3f]
-
-s_nand_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8b]
-
-s_nand_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8b]
-
-s_nand_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8b]
-
-s_nand_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8b]
-
-s_nand_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8b]
-
-s_nand_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8b]
-
-s_nand_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8b]
-
-s_nand_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8b]
-
-s_nand_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8b]
-
-s_nand_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8b]
-
-s_nand_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8b]
-
-s_nand_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8b]
-
-s_nand_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8b]
-
-s_nand_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8b]
-
-s_nand_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8b]
-
-s_nand_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8b]
-
-s_nand_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8b]
-
-s_nand_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8b]
-
-s_nand_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8b]
-
-s_nand_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8b]
-
-s_nand_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8b]
-
-s_nand_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8b,0x56,0x34,0x12,0xaf]
-
-s_nand_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8b,0x73,0x72,0x71,0x3f]
-
-s_nand_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8b]
-
-s_nand_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8b]
-
-s_nand_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8b]
-
-s_nand_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8b]
-
-s_nand_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8b]
-
-s_nand_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8b]
-
-s_nand_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8b]
-
-s_nand_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8b]
-
-s_nand_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8b]
-
-s_nand_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8b]
-
-s_nand_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8b]
-
-s_nand_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8b]
-
-s_nand_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8b,0x56,0x34,0x12,0xaf]
-
-s_nand_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8b,0x73,0x72,0x71,0x3f]
-
-s_nand_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8b]
-
-s_nand_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8b]
-
-s_nand_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x8b]
-
-s_nand_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8b]
-
-s_nand_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8b]
-
-s_nand_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8b]
-
-s_nand_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8b]
-
-s_nand_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8b,0x56,0x34,0x12,0xaf]
-
-s_nand_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8b,0x73,0x72,0x71,0x3f]
-
-s_nand_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8b]
-
-s_nand_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8b,0x56,0x34,0x12,0xaf]
-
-s_nand_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8b,0x73,0x72,0x71,0x3f]
-
-s_nor_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8c]
-
-s_nor_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8c]
-
-s_nor_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8c]
-
-s_nor_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8c]
-
-s_nor_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8c]
-
-s_nor_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8c]
-
-s_nor_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8c]
-
-s_nor_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8c]
-
-s_nor_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8c]
-
-s_nor_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8c]
-
-s_nor_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8c]
-
-s_nor_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8c]
-
-s_nor_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8c]
-
-s_nor_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8c]
-
-s_nor_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8c]
-
-s_nor_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8c]
-
-s_nor_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8c]
-
-s_nor_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8c]
-
-s_nor_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8c]
-
-s_nor_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8c]
-
-s_nor_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8c]
-
-s_nor_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nor_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nor_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8c]
-
-s_nor_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8c]
-
-s_nor_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8c]
-
-s_nor_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8c]
-
-s_nor_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8c]
-
-s_nor_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8c]
-
-s_nor_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8c]
-
-s_nor_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8c]
-
-s_nor_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8c]
-
-s_nor_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8c]
-
-s_nor_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8c]
-
-s_nor_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8c]
-
-s_nor_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nor_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nor_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8c]
-
-s_nor_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8c]
-
-s_nor_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x8c]
-
-s_nor_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8c]
-
-s_nor_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8c]
-
-s_nor_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8c]
-
-s_nor_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8c]
-
-s_nor_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nor_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8c,0x73,0x72,0x71,0x3f]
-
-s_nor_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8c]
-
-s_nor_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8c,0x56,0x34,0x12,0xaf]
-
-s_nor_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8c,0x73,0x72,0x71,0x3f]
-
-s_xnor_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8d]
-
-s_xnor_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8d]
-
-s_xnor_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8d]
-
-s_xnor_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8d]
-
-s_xnor_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8d]
-
-s_xnor_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8d]
-
-s_xnor_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8d]
-
-s_xnor_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8d]
-
-s_xnor_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8d]
-
-s_xnor_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8d]
-
-s_xnor_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8d,0x56,0x34,0x12,0xaf]
-
-s_xnor_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8d,0x73,0x72,0x71,0x3f]
-
-s_xnor_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8d]
-
-s_xnor_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8d]
-
-s_xnor_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8d]
-
-s_xnor_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8d]
-
-s_xnor_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8d]
-
-s_xnor_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8d]
-
-s_xnor_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8d]
-
-s_xnor_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8d]
-
-s_xnor_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8d]
-
-s_xnor_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8d]
-
-s_xnor_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8d]
-
-s_xnor_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8d]
-
-s_xnor_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8d,0x56,0x34,0x12,0xaf]
-
-s_xnor_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8d,0x73,0x72,0x71,0x3f]
-
-s_xnor_b64 s[10:11], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[12:13], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x8c,0x8d]
-
-s_xnor_b64 s[100:101], s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe4,0x8d]
-
-s_xnor_b64 flat_scratch, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xe6,0x8d]
-
-s_xnor_b64 vcc, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xea,0x8d]
-
-s_xnor_b64 exec, s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0xfe,0x8d]
-
-s_xnor_b64 s[10:11], s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], exec, s[4:5]
-// CHECK: [0x7e,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], 0, s[4:5]
-// CHECK: [0x80,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], -1, s[4:5]
-// CHECK: [0xc1,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8d,0x56,0x34,0x12,0xaf]
-
-s_xnor_b64 s[10:11], 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x8a,0x8d,0x73,0x72,0x71,0x3f]
-
-s_xnor_b64 s[10:11], s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], vcc
-// CHECK: [0x02,0x6a,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], exec
-// CHECK: [0x02,0x7e,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8d]
-
-s_xnor_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8d,0x56,0x34,0x12,0xaf]
-
-s_xnor_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8d,0x73,0x72,0x71,0x3f]
-
-s_lshl_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8e]
-
-s_lshl_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8e]
-
-s_lshl_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8e]
-
-s_lshl_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8e]
-
-s_lshl_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8e]
-
-s_lshl_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8e]
-
-s_lshl_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8e]
-
-s_lshl_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8e]
-
-s_lshl_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8e]
-
-s_lshl_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8e]
-
-s_lshl_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8e,0x56,0x34,0x12,0xaf]
-
-s_lshl_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8e,0x73,0x72,0x71,0x3f]
-
-s_lshl_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8e]
-
-s_lshl_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8e]
-
-s_lshl_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8e]
-
-s_lshl_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8e]
-
-s_lshl_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8e]
-
-s_lshl_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8e]
-
-s_lshl_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8e]
-
-s_lshl_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8e]
-
-s_lshl_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8e]
-
-s_lshl_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8e]
-
-s_lshl_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8e]
-
-s_lshl_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8e]
-
-s_lshl_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8e,0x56,0x34,0x12,0xaf]
-
-s_lshl_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8e,0x73,0x72,0x71,0x3f]
-
-s_lshl_b64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x8e]
-
-s_lshl_b64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0xe4,0x8e]
-
-s_lshl_b64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x8e]
-
-s_lshl_b64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x8e]
-
-s_lshl_b64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x8e]
-
-s_lshl_b64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x8e,0x56,0x34,0x12,0xaf]
-
-s_lshl_b64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x8e,0x73,0x72,0x71,0x3f]
-
-s_lshl_b64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8e]
-
-s_lshl_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8e,0x56,0x34,0x12,0xaf]
-
-s_lshl_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8e,0x73,0x72,0x71,0x3f]
-
-s_lshr_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x8f]
-
-s_lshr_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x8f]
-
-s_lshr_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x8f]
-
-s_lshr_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x8f]
-
-s_lshr_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x8f]
-
-s_lshr_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x8f]
-
-s_lshr_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x8f]
-
-s_lshr_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x8f]
-
-s_lshr_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x8f]
-
-s_lshr_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x8f]
-
-s_lshr_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshr_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshr_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x8f]
-
-s_lshr_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x8f]
-
-s_lshr_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x8f]
-
-s_lshr_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x8f]
-
-s_lshr_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x8f]
-
-s_lshr_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x8f]
-
-s_lshr_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x8f]
-
-s_lshr_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x8f]
-
-s_lshr_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x8f]
-
-s_lshr_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x8f]
-
-s_lshr_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x8f]
-
-s_lshr_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x8f]
-
-s_lshr_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshr_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshr_b64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x8f]
-
-s_lshr_b64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0xe4,0x8f]
-
-s_lshr_b64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x8f]
-
-s_lshr_b64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x8f]
-
-s_lshr_b64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x8f]
-
-s_lshr_b64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshr_b64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x8f,0x73,0x72,0x71,0x3f]
-
-s_lshr_b64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x8f]
-
-s_lshr_b64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x8f,0x56,0x34,0x12,0xaf]
-
-s_lshr_b64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x8f,0x73,0x72,0x71,0x3f]
-
-s_ashr_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x90]
-
-s_ashr_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x90]
-
-s_ashr_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x90]
-
-s_ashr_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x90]
-
-s_ashr_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x90]
-
-s_ashr_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x90]
-
-s_ashr_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x90]
-
-s_ashr_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x90]
-
-s_ashr_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x90]
-
-s_ashr_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x90]
-
-s_ashr_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x90]
-
-s_ashr_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x90]
-
-s_ashr_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x90]
-
-s_ashr_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x90]
-
-s_ashr_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x90]
-
-s_ashr_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x90]
-
-s_ashr_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x90]
-
-s_ashr_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x90]
-
-s_ashr_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x90]
-
-s_ashr_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x90]
-
-s_ashr_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x90]
-
-s_ashr_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x90,0x56,0x34,0x12,0xaf]
-
-s_ashr_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x90,0x73,0x72,0x71,0x3f]
-
-s_ashr_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x90]
-
-s_ashr_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x90]
-
-s_ashr_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x90]
-
-s_ashr_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x90]
-
-s_ashr_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x90]
-
-s_ashr_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x90]
-
-s_ashr_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x90]
-
-s_ashr_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x90]
-
-s_ashr_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x90]
-
-s_ashr_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x90]
-
-s_ashr_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x90]
-
-s_ashr_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x90]
-
-s_ashr_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x90,0x56,0x34,0x12,0xaf]
-
-s_ashr_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x90,0x73,0x72,0x71,0x3f]
-
-s_ashr_i64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x90]
-
-s_ashr_i64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x90]
-
-s_ashr_i64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0xe4,0x90]
-
-s_ashr_i64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x90]
-
-s_ashr_i64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x90]
-
-s_ashr_i64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x90]
-
-s_ashr_i64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x90]
-
-s_ashr_i64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x90,0x56,0x34,0x12,0xaf]
-
-s_ashr_i64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x90,0x73,0x72,0x71,0x3f]
-
-s_ashr_i64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x90]
-
-s_ashr_i64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x90,0x56,0x34,0x12,0xaf]
-
-s_ashr_i64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x90,0x73,0x72,0x71,0x3f]
-
-s_bfm_b32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x91]
-
-s_bfm_b32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x91]
-
-s_bfm_b32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x91]
-
-s_bfm_b32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x91]
-
-s_bfm_b32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x91]
-
-s_bfm_b32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x91]
-
-s_bfm_b32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x91]
-
-s_bfm_b32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x91]
-
-s_bfm_b32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x91]
-
-s_bfm_b32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x91]
-
-s_bfm_b32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x91]
-
-s_bfm_b32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x91]
-
-s_bfm_b32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x91]
-
-s_bfm_b32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x91]
-
-s_bfm_b32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x91]
-
-s_bfm_b32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x91]
-
-s_bfm_b32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x91]
-
-s_bfm_b32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x91]
-
-s_bfm_b32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x91]
-
-s_bfm_b32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x91]
-
-s_bfm_b32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x91]
-
-s_bfm_b32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x91,0x56,0x34,0x12,0xaf]
-
-s_bfm_b32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x91,0x73,0x72,0x71,0x3f]
-
-s_bfm_b32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x91]
-
-s_bfm_b32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x91]
-
-s_bfm_b32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x91]
-
-s_bfm_b32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x91]
-
-s_bfm_b32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x91]
-
-s_bfm_b32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x91]
-
-s_bfm_b32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x91]
-
-s_bfm_b32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x91]
-
-s_bfm_b32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x91]
-
-s_bfm_b32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x91]
-
-s_bfm_b32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x91]
-
-s_bfm_b32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x91]
-
-s_bfm_b32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x91,0x56,0x34,0x12,0xaf]
-
-s_bfm_b32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x91,0x73,0x72,0x71,0x3f]
-
-s_bfm_b64 s[10:11], s1, s2
-// CHECK: [0x01,0x02,0x8a,0x91]
-
-s_bfm_b64 s[12:13], s1, s2
-// CHECK: [0x01,0x02,0x8c,0x91]
-
-s_bfm_b64 s[100:101], s1, s2
-// CHECK: [0x01,0x02,0xe4,0x91]
-
-s_bfm_b64 flat_scratch, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x91]
-
-s_bfm_b64 vcc, s1, s2
-// CHECK: [0x01,0x02,0xea,0x91]
-
-s_bfm_b64 exec, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x91]
-
-s_bfm_b64 s[10:11], s101, s2
-// CHECK: [0x65,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], vcc_lo, s2
-// CHECK: [0x6a,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], vcc_hi, s2
-// CHECK: [0x6b,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], m0, s2
-// CHECK: [0x7c,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], exec_lo, s2
-// CHECK: [0x7e,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], exec_hi, s2
-// CHECK: [0x7f,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x91]
-
-s_bfm_b64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x91,0x56,0x34,0x12,0xaf]
-
-s_bfm_b64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x91,0x73,0x72,0x71,0x3f]
-
-s_bfm_b64 s[10:11], s1, s101
-// CHECK: [0x01,0x65,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, vcc_lo
-// CHECK: [0x01,0x6a,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, vcc_hi
-// CHECK: [0x01,0x6b,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, m0
-// CHECK: [0x01,0x7c,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, exec_lo
-// CHECK: [0x01,0x7e,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, exec_hi
-// CHECK: [0x01,0x7f,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, 0
-// CHECK: [0x01,0x80,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, -1
-// CHECK: [0x01,0xc1,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, 0.5
-// CHECK: [0x01,0xf0,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, -4.0
-// CHECK: [0x01,0xf7,0x8a,0x91]
-
-s_bfm_b64 s[10:11], s1, 0xaf123456
-// CHECK: [0x01,0xff,0x8a,0x91,0x56,0x34,0x12,0xaf]
-
-s_bfm_b64 s[10:11], s1, 0x3f717273
-// CHECK: [0x01,0xff,0x8a,0x91,0x73,0x72,0x71,0x3f]
-
-s_mul_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x92]
-
-s_mul_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x92]
-
-s_mul_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x92]
-
-s_mul_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x92]
-
-s_mul_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x92]
-
-s_mul_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x92]
-
-s_mul_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x92]
-
-s_mul_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x92]
-
-s_mul_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x92]
-
-s_mul_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x92]
-
-s_mul_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x92]
-
-s_mul_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x92]
-
-s_mul_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x92]
-
-s_mul_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x92]
-
-s_mul_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x92]
-
-s_mul_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x92]
-
-s_mul_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x92]
-
-s_mul_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x92]
-
-s_mul_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x92]
-
-s_mul_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x92]
-
-s_mul_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x92]
-
-s_mul_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x92,0x56,0x34,0x12,0xaf]
-
-s_mul_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x92,0x73,0x72,0x71,0x3f]
-
-s_mul_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x92]
-
-s_mul_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x92]
-
-s_mul_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x92]
-
-s_mul_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x92]
-
-s_mul_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x92]
-
-s_mul_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x92]
-
-s_mul_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x92]
-
-s_mul_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x92]
-
-s_mul_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x92]
-
-s_mul_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x92]
-
-s_mul_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x92]
-
-s_mul_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x92]
-
-s_mul_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x92,0x56,0x34,0x12,0xaf]
-
-s_mul_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfe_u32 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x92]
-
-s_bfe_u32 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x92]
-
-s_bfe_u32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x92]
-
-s_bfe_u32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x92]
-
-s_bfe_u32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x92]
-
-s_bfe_u32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x92]
-
-s_bfe_u32 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x92]
-
-s_bfe_u32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x92]
-
-s_bfe_u32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x92]
-
-s_bfe_u32 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x92]
-
-s_bfe_u32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x92]
-
-s_bfe_u32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x92]
-
-s_bfe_u32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x92]
-
-s_bfe_u32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x92]
-
-s_bfe_u32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x92]
-
-s_bfe_u32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x92]
-
-s_bfe_u32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x92]
-
-s_bfe_u32 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x92]
-
-s_bfe_u32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x92]
-
-s_bfe_u32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x92]
-
-s_bfe_u32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x92]
-
-s_bfe_u32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x85,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfe_u32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x85,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfe_u32 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x92]
-
-s_bfe_u32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x92]
-
-s_bfe_u32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x92]
-
-s_bfe_u32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x92]
-
-s_bfe_u32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x92]
-
-s_bfe_u32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x92]
-
-s_bfe_u32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x92]
-
-s_bfe_u32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x92]
-
-s_bfe_u32 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x92]
-
-s_bfe_u32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x92]
-
-s_bfe_u32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x92]
-
-s_bfe_u32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x92]
-
-s_bfe_u32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x92,0x56,0x34,0x12,0xaf]
-
-s_bfe_u32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x92,0x73,0x72,0x71,0x3f]
-
-s_bfe_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x93]
-
-s_bfe_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x93]
-
-s_bfe_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x93]
-
-s_bfe_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x93]
-
-s_bfe_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x93]
-
-s_bfe_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x93]
-
-s_bfe_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x93]
-
-s_bfe_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x93]
-
-s_bfe_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x93]
-
-s_bfe_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x93]
-
-s_bfe_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x93]
-
-s_bfe_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x93]
-
-s_bfe_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x93]
-
-s_bfe_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x93]
-
-s_bfe_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x93]
-
-s_bfe_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x93]
-
-s_bfe_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x93]
-
-s_bfe_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x93]
-
-s_bfe_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x93]
-
-s_bfe_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x93]
-
-s_bfe_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x93]
-
-s_bfe_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x93]
-
-s_bfe_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x93]
-
-s_bfe_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x93]
-
-s_bfe_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x93]
-
-s_bfe_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x93]
-
-s_bfe_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x93]
-
-s_bfe_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x93]
-
-s_bfe_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x93]
-
-s_bfe_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x93]
-
-s_bfe_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x93]
-
-s_bfe_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x93]
-
-s_bfe_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x93]
-
-s_bfe_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_u64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x8a,0x93]
-
-s_bfe_u64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x8c,0x93]
-
-s_bfe_u64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0xe4,0x93]
-
-s_bfe_u64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0xe6,0x93]
-
-s_bfe_u64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0xea,0x93]
-
-s_bfe_u64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0xfe,0x93]
-
-s_bfe_u64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x8a,0x93]
-
-s_bfe_u64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x8a,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_u64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x8a,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_u64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x8a,0x93]
-
-s_bfe_u64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x8a,0x93,0x56,0x34,0x12,0xaf]
-
-s_bfe_u64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x8a,0x93,0x73,0x72,0x71,0x3f]
-
-s_bfe_i64 s[10:11], s[2:3], s2
-// CHECK: [0x02,0x02,0x0a,0x94]
-
-s_bfe_i64 s[12:13], s[2:3], s2
-// CHECK: [0x02,0x02,0x0c,0x94]
-
-s_bfe_i64 s[100:101], s[2:3], s2
-// CHECK: [0x02,0x02,0x64,0x94]
-
-s_bfe_i64 flat_scratch, s[2:3], s2
-// CHECK: [0x02,0x02,0x66,0x94]
-
-s_bfe_i64 vcc, s[2:3], s2
-// CHECK: [0x02,0x02,0x6a,0x94]
-
-s_bfe_i64 exec, s[2:3], s2
-// CHECK: [0x02,0x02,0x7e,0x94]
-
-s_bfe_i64 s[10:11], s[4:5], s2
-// CHECK: [0x04,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[100:101], s2
-// CHECK: [0x64,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], flat_scratch, s2
-// CHECK: [0x66,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], vcc, s2
-// CHECK: [0x6a,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], exec, s2
-// CHECK: [0x7e,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], 0, s2
-// CHECK: [0x80,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], -1, s2
-// CHECK: [0xc1,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], 0.5, s2
-// CHECK: [0xf0,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], -4.0, s2
-// CHECK: [0xf7,0x02,0x0a,0x94]
-
-s_bfe_i64 s[10:11], 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0a,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_i64 s[10:11], 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0a,0x94,0x73,0x72,0x71,0x3f]
-
-s_bfe_i64 s[10:11], s[2:3], s101
-// CHECK: [0x02,0x65,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], m0
-// CHECK: [0x02,0x7c,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], 0
-// CHECK: [0x02,0x80,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], -1
-// CHECK: [0x02,0xc1,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x0a,0x94]
-
-s_bfe_i64 s[10:11], s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x0a,0x94,0x56,0x34,0x12,0xaf]
-
-s_bfe_i64 s[10:11], s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x0a,0x94,0x73,0x72,0x71,0x3f]
-
-s_cbranch_g_fork s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x80,0x94]
-
-s_cbranch_g_fork s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x80,0x94]
-
-s_cbranch_g_fork s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x80,0x94]
-
-s_cbranch_g_fork flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x80,0x94]
-
-s_cbranch_g_fork vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x80,0x94]
-
-s_cbranch_g_fork exec, s[4:5]
-// CHECK: [0x7e,0x04,0x80,0x94]
-
-s_cbranch_g_fork 0, s[4:5]
-// CHECK: [0x80,0x04,0x80,0x94]
-
-s_cbranch_g_fork -1, s[4:5]
-// CHECK: [0xc1,0x04,0x80,0x94]
-
-s_cbranch_g_fork 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x80,0x94]
-
-s_cbranch_g_fork -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], vcc
-// CHECK: [0x02,0x6a,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], exec
-// CHECK: [0x02,0x7e,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], 0
-// CHECK: [0x02,0x80,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], -1
-// CHECK: [0x02,0xc1,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x80,0x94]
-
-s_cbranch_g_fork s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x80,0x94]
-
-s_absdiff_i32 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x95]
-
-s_absdiff_i32 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x95]
-
-s_absdiff_i32 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x95]
-
-s_absdiff_i32 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x95]
-
-s_absdiff_i32 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x95]
-
-s_absdiff_i32 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x95]
-
-s_absdiff_i32 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x95]
-
-s_absdiff_i32 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x95]
-
-s_absdiff_i32 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x95]
-
-s_absdiff_i32 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x95]
-
-s_absdiff_i32 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x95,0x56,0x34,0x12,0xaf]
-
-s_absdiff_i32 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x95,0x73,0x72,0x71,0x3f]
-
-s_absdiff_i32 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x95]
-
-s_absdiff_i32 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x95]
-
-s_absdiff_i32 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x95]
-
-s_absdiff_i32 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x95]
-
-s_absdiff_i32 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x95]
-
-s_absdiff_i32 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x95]
-
-s_absdiff_i32 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x95]
-
-s_absdiff_i32 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x95]
-
-s_absdiff_i32 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x95]
-
-s_absdiff_i32 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x95]
-
-s_absdiff_i32 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x95]
-
-s_absdiff_i32 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x95]
-
-s_absdiff_i32 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x95,0x56,0x34,0x12,0xaf]
-
-s_absdiff_i32 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x95,0x73,0x72,0x71,0x3f]
-
-s_rfe_restore_b64 s[2:3], s2
-// CHECK: [0x02,0x02,0x80,0x95]
-
-s_rfe_restore_b64 s[4:5], s2
-// CHECK: [0x04,0x02,0x80,0x95]
-
-s_rfe_restore_b64 s[100:101], s2
-// CHECK: [0x64,0x02,0x80,0x95]
-
-s_rfe_restore_b64 flat_scratch, s2
-// CHECK: [0x66,0x02,0x80,0x95]
-
-s_rfe_restore_b64 vcc, s2
-// CHECK: [0x6a,0x02,0x80,0x95]
-
-s_rfe_restore_b64 exec, s2
-// CHECK: [0x7e,0x02,0x80,0x95]
-
-s_rfe_restore_b64 0, s2
-// CHECK: [0x80,0x02,0x80,0x95]
-
-s_rfe_restore_b64 -1, s2
-// CHECK: [0xc1,0x02,0x80,0x95]
-
-s_rfe_restore_b64 0.5, s2
-// CHECK: [0xf0,0x02,0x80,0x95]
-
-s_rfe_restore_b64 -4.0, s2
-// CHECK: [0xf7,0x02,0x80,0x95]
-
-s_rfe_restore_b64 0xaf123456, s2
-// CHECK: [0xff,0x02,0x80,0x95,0x56,0x34,0x12,0xaf]
-
-s_rfe_restore_b64 0x3f717273, s2
-// CHECK: [0xff,0x02,0x80,0x95,0x73,0x72,0x71,0x3f]
-
-s_rfe_restore_b64 s[2:3], s101
-// CHECK: [0x02,0x65,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], m0
-// CHECK: [0x02,0x7c,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], 0
-// CHECK: [0x02,0x80,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x80,0x95]
-
-s_rfe_restore_b64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x80,0x95,0x56,0x34,0x12,0xaf]
-
-s_rfe_restore_b64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x80,0x95,0x73,0x72,0x71,0x3f]
-
-s_pack_ll_b32_b16 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x99]
-
-s_pack_ll_b32_b16 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x99]
-
-s_pack_ll_b32_b16 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x99]
-
-s_pack_ll_b32_b16 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x99]
-
-s_pack_ll_b32_b16 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x99]
-
-s_pack_ll_b32_b16 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x99]
-
-s_pack_ll_b32_b16 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x99]
-
-s_pack_ll_b32_b16 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x99]
-
-s_pack_ll_b32_b16 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, 0xfe0b, s2
-// CHECK: [0xff,0x02,0x05,0x99,0x0b,0xfe,0x00,0x00]
-
-s_pack_ll_b32_b16 s5, 0x3456, s2
-// CHECK: [0xff,0x02,0x05,0x99,0x56,0x34,0x00,0x00]
-
-s_pack_ll_b32_b16 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x99]
-
-s_pack_ll_b32_b16 s5, s1, 0xfe0b
-// CHECK: [0x01,0xff,0x05,0x99,0x0b,0xfe,0x00,0x00]
-
-s_pack_ll_b32_b16 s5, s1, 0x3456
-// CHECK: [0x01,0xff,0x05,0x99,0x56,0x34,0x00,0x00]
-
-s_pack_lh_b32_b16 s5, s1, s2
-// CHECK: [0x01,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s101, s1, s2
-// CHECK: [0x01,0x02,0xe5,0x99]
-
-s_pack_lh_b32_b16 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0xe6,0x99]
-
-s_pack_lh_b32_b16 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0xe7,0x99]
-
-s_pack_lh_b32_b16 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0xea,0x99]
-
-s_pack_lh_b32_b16 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0xeb,0x99]
-
-s_pack_lh_b32_b16 m0, s1, s2
-// CHECK: [0x01,0x02,0xfc,0x99]
-
-s_pack_lh_b32_b16 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0xfe,0x99]
-
-s_pack_lh_b32_b16 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0xff,0x99]
-
-s_pack_lh_b32_b16 s5, s101, s2
-// CHECK: [0x65,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, m0, s2
-// CHECK: [0x7c,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, 0, s2
-// CHECK: [0x80,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, -1, s2
-// CHECK: [0xc1,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, 0xfe0b, s2
-// CHECK: [0xff,0x02,0x85,0x99,0x0b,0xfe,0x00,0x00]
-
-s_pack_lh_b32_b16 s5, 0x3456, s2
-// CHECK: [0xff,0x02,0x85,0x99,0x56,0x34,0x00,0x00]
-
-s_pack_lh_b32_b16 s5, s1, s101
-// CHECK: [0x01,0x65,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, m0
-// CHECK: [0x01,0x7c,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, 0
-// CHECK: [0x01,0x80,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, -1
-// CHECK: [0x01,0xc1,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x85,0x99]
-
-s_pack_lh_b32_b16 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x85,0x99,0x56,0x34,0x12,0xaf]
-
-s_pack_lh_b32_b16 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x85,0x99,0x73,0x72,0x71,0x3f]
-
-s_pack_hh_b32_b16 s5, s1, s2
-// CHECK: [0x01,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s101, s1, s2
-// CHECK: [0x01,0x02,0x65,0x9a]
-
-s_pack_hh_b32_b16 flat_scratch_lo, s1, s2
-// CHECK: [0x01,0x02,0x66,0x9a]
-
-s_pack_hh_b32_b16 flat_scratch_hi, s1, s2
-// CHECK: [0x01,0x02,0x67,0x9a]
-
-s_pack_hh_b32_b16 vcc_lo, s1, s2
-// CHECK: [0x01,0x02,0x6a,0x9a]
-
-s_pack_hh_b32_b16 vcc_hi, s1, s2
-// CHECK: [0x01,0x02,0x6b,0x9a]
-
-s_pack_hh_b32_b16 m0, s1, s2
-// CHECK: [0x01,0x02,0x7c,0x9a]
-
-s_pack_hh_b32_b16 exec_lo, s1, s2
-// CHECK: [0x01,0x02,0x7e,0x9a]
-
-s_pack_hh_b32_b16 exec_hi, s1, s2
-// CHECK: [0x01,0x02,0x7f,0x9a]
-
-s_pack_hh_b32_b16 s5, s101, s2
-// CHECK: [0x65,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, m0, s2
-// CHECK: [0x7c,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, 0, s2
-// CHECK: [0x80,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, -1, s2
-// CHECK: [0xc1,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0x9a,0x56,0x34,0x12,0xaf]
-
-s_pack_hh_b32_b16 s5, 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0x9a,0x73,0x72,0x71,0x3f]
-
-s_pack_hh_b32_b16 s5, s1, s101
-// CHECK: [0x01,0x65,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, m0
-// CHECK: [0x01,0x7c,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, 0
-// CHECK: [0x01,0x80,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, -1
-// CHECK: [0x01,0xc1,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0x9a]
-
-s_pack_hh_b32_b16 s5, s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0x9a,0x56,0x34,0x12,0xaf]
-
-s_pack_hh_b32_b16 s5, s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0x9a,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_i32 s1, s2
-// CHECK: [0x01,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 s101, s2
-// CHECK: [0x65,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 m0, s2
-// CHECK: [0x7c,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 0, s2
-// CHECK: [0x80,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 -1, s2
-// CHECK: [0xc1,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x00,0xbf]
-
-s_cmp_eq_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x00,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x00,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_i32 s1, s101
-// CHECK: [0x01,0x65,0x00,0xbf]
-
-s_cmp_eq_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x00,0xbf]
-
-s_cmp_eq_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x00,0xbf]
-
-s_cmp_eq_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x00,0xbf]
-
-s_cmp_eq_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x00,0xbf]
-
-s_cmp_eq_i32 s1, m0
-// CHECK: [0x01,0x7c,0x00,0xbf]
-
-s_cmp_eq_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x00,0xbf]
-
-s_cmp_eq_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x00,0xbf]
-
-s_cmp_eq_i32 s1, 0
-// CHECK: [0x01,0x80,0x00,0xbf]
-
-s_cmp_eq_i32 s1, -1
-// CHECK: [0x01,0xc1,0x00,0xbf]
-
-s_cmp_eq_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x00,0xbf]
-
-s_cmp_eq_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x00,0xbf]
-
-s_cmp_eq_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_i32 s1, s2
-// CHECK: [0x01,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 s101, s2
-// CHECK: [0x65,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 m0, s2
-// CHECK: [0x7c,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 0, s2
-// CHECK: [0x80,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 -1, s2
-// CHECK: [0xc1,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x01,0xbf]
-
-s_cmp_lg_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x01,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x01,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_i32 s1, s101
-// CHECK: [0x01,0x65,0x01,0xbf]
-
-s_cmp_lg_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x01,0xbf]
-
-s_cmp_lg_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x01,0xbf]
-
-s_cmp_lg_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x01,0xbf]
-
-s_cmp_lg_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x01,0xbf]
-
-s_cmp_lg_i32 s1, m0
-// CHECK: [0x01,0x7c,0x01,0xbf]
-
-s_cmp_lg_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x01,0xbf]
-
-s_cmp_lg_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x01,0xbf]
-
-s_cmp_lg_i32 s1, 0
-// CHECK: [0x01,0x80,0x01,0xbf]
-
-s_cmp_lg_i32 s1, -1
-// CHECK: [0x01,0xc1,0x01,0xbf]
-
-s_cmp_lg_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x01,0xbf]
-
-s_cmp_lg_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x01,0xbf]
-
-s_cmp_lg_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_i32 s1, s2
-// CHECK: [0x01,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 s101, s2
-// CHECK: [0x65,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 m0, s2
-// CHECK: [0x7c,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 0, s2
-// CHECK: [0x80,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 -1, s2
-// CHECK: [0xc1,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x02,0xbf]
-
-s_cmp_gt_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x02,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x02,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_i32 s1, s101
-// CHECK: [0x01,0x65,0x02,0xbf]
-
-s_cmp_gt_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x02,0xbf]
-
-s_cmp_gt_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x02,0xbf]
-
-s_cmp_gt_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x02,0xbf]
-
-s_cmp_gt_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x02,0xbf]
-
-s_cmp_gt_i32 s1, m0
-// CHECK: [0x01,0x7c,0x02,0xbf]
-
-s_cmp_gt_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x02,0xbf]
-
-s_cmp_gt_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x02,0xbf]
-
-s_cmp_gt_i32 s1, 0
-// CHECK: [0x01,0x80,0x02,0xbf]
-
-s_cmp_gt_i32 s1, -1
-// CHECK: [0x01,0xc1,0x02,0xbf]
-
-s_cmp_gt_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x02,0xbf]
-
-s_cmp_gt_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x02,0xbf]
-
-s_cmp_gt_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_i32 s1, s2
-// CHECK: [0x01,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 s101, s2
-// CHECK: [0x65,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 m0, s2
-// CHECK: [0x7c,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 0, s2
-// CHECK: [0x80,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 -1, s2
-// CHECK: [0xc1,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x03,0xbf]
-
-s_cmp_ge_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x03,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x03,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_i32 s1, s101
-// CHECK: [0x01,0x65,0x03,0xbf]
-
-s_cmp_ge_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x03,0xbf]
-
-s_cmp_ge_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x03,0xbf]
-
-s_cmp_ge_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x03,0xbf]
-
-s_cmp_ge_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x03,0xbf]
-
-s_cmp_ge_i32 s1, m0
-// CHECK: [0x01,0x7c,0x03,0xbf]
-
-s_cmp_ge_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x03,0xbf]
-
-s_cmp_ge_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x03,0xbf]
-
-s_cmp_ge_i32 s1, 0
-// CHECK: [0x01,0x80,0x03,0xbf]
-
-s_cmp_ge_i32 s1, -1
-// CHECK: [0x01,0xc1,0x03,0xbf]
-
-s_cmp_ge_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x03,0xbf]
-
-s_cmp_ge_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x03,0xbf]
-
-s_cmp_ge_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_i32 s1, s2
-// CHECK: [0x01,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 s101, s2
-// CHECK: [0x65,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 m0, s2
-// CHECK: [0x7c,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 0, s2
-// CHECK: [0x80,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 -1, s2
-// CHECK: [0xc1,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x04,0xbf]
-
-s_cmp_lt_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x04,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x04,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_i32 s1, s101
-// CHECK: [0x01,0x65,0x04,0xbf]
-
-s_cmp_lt_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x04,0xbf]
-
-s_cmp_lt_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x04,0xbf]
-
-s_cmp_lt_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x04,0xbf]
-
-s_cmp_lt_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x04,0xbf]
-
-s_cmp_lt_i32 s1, m0
-// CHECK: [0x01,0x7c,0x04,0xbf]
-
-s_cmp_lt_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x04,0xbf]
-
-s_cmp_lt_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x04,0xbf]
-
-s_cmp_lt_i32 s1, 0
-// CHECK: [0x01,0x80,0x04,0xbf]
-
-s_cmp_lt_i32 s1, -1
-// CHECK: [0x01,0xc1,0x04,0xbf]
-
-s_cmp_lt_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x04,0xbf]
-
-s_cmp_lt_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x04,0xbf]
-
-s_cmp_lt_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_i32 s1, s2
-// CHECK: [0x01,0x02,0x05,0xbf]
-
-s_cmp_le_i32 s101, s2
-// CHECK: [0x65,0x02,0x05,0xbf]
-
-s_cmp_le_i32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x05,0xbf]
-
-s_cmp_le_i32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x05,0xbf]
-
-s_cmp_le_i32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x05,0xbf]
-
-s_cmp_le_i32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x05,0xbf]
-
-s_cmp_le_i32 m0, s2
-// CHECK: [0x7c,0x02,0x05,0xbf]
-
-s_cmp_le_i32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x05,0xbf]
-
-s_cmp_le_i32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x05,0xbf]
-
-s_cmp_le_i32 0, s2
-// CHECK: [0x80,0x02,0x05,0xbf]
-
-s_cmp_le_i32 -1, s2
-// CHECK: [0xc1,0x02,0x05,0xbf]
-
-s_cmp_le_i32 0.5, s2
-// CHECK: [0xf0,0x02,0x05,0xbf]
-
-s_cmp_le_i32 -4.0, s2
-// CHECK: [0xf7,0x02,0x05,0xbf]
-
-s_cmp_le_i32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x05,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_i32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x05,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_i32 s1, s101
-// CHECK: [0x01,0x65,0x05,0xbf]
-
-s_cmp_le_i32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x05,0xbf]
-
-s_cmp_le_i32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x05,0xbf]
-
-s_cmp_le_i32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x05,0xbf]
-
-s_cmp_le_i32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x05,0xbf]
-
-s_cmp_le_i32 s1, m0
-// CHECK: [0x01,0x7c,0x05,0xbf]
-
-s_cmp_le_i32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x05,0xbf]
-
-s_cmp_le_i32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x05,0xbf]
-
-s_cmp_le_i32 s1, 0
-// CHECK: [0x01,0x80,0x05,0xbf]
-
-s_cmp_le_i32 s1, -1
-// CHECK: [0x01,0xc1,0x05,0xbf]
-
-s_cmp_le_i32 s1, 0.5
-// CHECK: [0x01,0xf0,0x05,0xbf]
-
-s_cmp_le_i32 s1, -4.0
-// CHECK: [0x01,0xf7,0x05,0xbf]
-
-s_cmp_le_i32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_i32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u32 s1, s2
-// CHECK: [0x01,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 s101, s2
-// CHECK: [0x65,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 m0, s2
-// CHECK: [0x7c,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 0, s2
-// CHECK: [0x80,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 -1, s2
-// CHECK: [0xc1,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x06,0xbf]
-
-s_cmp_eq_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x06,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x06,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u32 s1, s101
-// CHECK: [0x01,0x65,0x06,0xbf]
-
-s_cmp_eq_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x06,0xbf]
-
-s_cmp_eq_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x06,0xbf]
-
-s_cmp_eq_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x06,0xbf]
-
-s_cmp_eq_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x06,0xbf]
-
-s_cmp_eq_u32 s1, m0
-// CHECK: [0x01,0x7c,0x06,0xbf]
-
-s_cmp_eq_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x06,0xbf]
-
-s_cmp_eq_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x06,0xbf]
-
-s_cmp_eq_u32 s1, 0
-// CHECK: [0x01,0x80,0x06,0xbf]
-
-s_cmp_eq_u32 s1, -1
-// CHECK: [0x01,0xc1,0x06,0xbf]
-
-s_cmp_eq_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x06,0xbf]
-
-s_cmp_eq_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x06,0xbf]
-
-s_cmp_eq_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u32 s1, s2
-// CHECK: [0x01,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 s101, s2
-// CHECK: [0x65,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 m0, s2
-// CHECK: [0x7c,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 0, s2
-// CHECK: [0x80,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 -1, s2
-// CHECK: [0xc1,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x07,0xbf]
-
-s_cmp_lg_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x07,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x07,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u32 s1, s101
-// CHECK: [0x01,0x65,0x07,0xbf]
-
-s_cmp_lg_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x07,0xbf]
-
-s_cmp_lg_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x07,0xbf]
-
-s_cmp_lg_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x07,0xbf]
-
-s_cmp_lg_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x07,0xbf]
-
-s_cmp_lg_u32 s1, m0
-// CHECK: [0x01,0x7c,0x07,0xbf]
-
-s_cmp_lg_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x07,0xbf]
-
-s_cmp_lg_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x07,0xbf]
-
-s_cmp_lg_u32 s1, 0
-// CHECK: [0x01,0x80,0x07,0xbf]
-
-s_cmp_lg_u32 s1, -1
-// CHECK: [0x01,0xc1,0x07,0xbf]
-
-s_cmp_lg_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x07,0xbf]
-
-s_cmp_lg_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x07,0xbf]
-
-s_cmp_lg_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_u32 s1, s2
-// CHECK: [0x01,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 s101, s2
-// CHECK: [0x65,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 m0, s2
-// CHECK: [0x7c,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 0, s2
-// CHECK: [0x80,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 -1, s2
-// CHECK: [0xc1,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x08,0xbf]
-
-s_cmp_gt_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x08,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x08,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_gt_u32 s1, s101
-// CHECK: [0x01,0x65,0x08,0xbf]
-
-s_cmp_gt_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x08,0xbf]
-
-s_cmp_gt_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x08,0xbf]
-
-s_cmp_gt_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x08,0xbf]
-
-s_cmp_gt_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x08,0xbf]
-
-s_cmp_gt_u32 s1, m0
-// CHECK: [0x01,0x7c,0x08,0xbf]
-
-s_cmp_gt_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x08,0xbf]
-
-s_cmp_gt_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x08,0xbf]
-
-s_cmp_gt_u32 s1, 0
-// CHECK: [0x01,0x80,0x08,0xbf]
-
-s_cmp_gt_u32 s1, -1
-// CHECK: [0x01,0xc1,0x08,0xbf]
-
-s_cmp_gt_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x08,0xbf]
-
-s_cmp_gt_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x08,0xbf]
-
-s_cmp_gt_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_gt_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_u32 s1, s2
-// CHECK: [0x01,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 s101, s2
-// CHECK: [0x65,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 m0, s2
-// CHECK: [0x7c,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 0, s2
-// CHECK: [0x80,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 -1, s2
-// CHECK: [0xc1,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x09,0xbf]
-
-s_cmp_ge_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x09,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x09,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_ge_u32 s1, s101
-// CHECK: [0x01,0x65,0x09,0xbf]
-
-s_cmp_ge_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x09,0xbf]
-
-s_cmp_ge_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x09,0xbf]
-
-s_cmp_ge_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x09,0xbf]
-
-s_cmp_ge_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x09,0xbf]
-
-s_cmp_ge_u32 s1, m0
-// CHECK: [0x01,0x7c,0x09,0xbf]
-
-s_cmp_ge_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x09,0xbf]
-
-s_cmp_ge_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x09,0xbf]
-
-s_cmp_ge_u32 s1, 0
-// CHECK: [0x01,0x80,0x09,0xbf]
-
-s_cmp_ge_u32 s1, -1
-// CHECK: [0x01,0xc1,0x09,0xbf]
-
-s_cmp_ge_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x09,0xbf]
-
-s_cmp_ge_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x09,0xbf]
-
-s_cmp_ge_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_ge_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_u32 s1, s2
-// CHECK: [0x01,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 s101, s2
-// CHECK: [0x65,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 m0, s2
-// CHECK: [0x7c,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 0, s2
-// CHECK: [0x80,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 -1, s2
-// CHECK: [0xc1,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0a,0xbf]
-
-s_cmp_lt_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0a,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0a,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lt_u32 s1, s101
-// CHECK: [0x01,0x65,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, m0
-// CHECK: [0x01,0x7c,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, 0
-// CHECK: [0x01,0x80,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, -1
-// CHECK: [0x01,0xc1,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0a,0xbf]
-
-s_cmp_lt_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lt_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_u32 s1, s2
-// CHECK: [0x01,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 s101, s2
-// CHECK: [0x65,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 m0, s2
-// CHECK: [0x7c,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 0, s2
-// CHECK: [0x80,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 -1, s2
-// CHECK: [0xc1,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 0.5, s2
-// CHECK: [0xf0,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0b,0xbf]
-
-s_cmp_le_u32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0b,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_u32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0b,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_le_u32 s1, s101
-// CHECK: [0x01,0x65,0x0b,0xbf]
-
-s_cmp_le_u32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x0b,0xbf]
-
-s_cmp_le_u32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x0b,0xbf]
-
-s_cmp_le_u32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0b,0xbf]
-
-s_cmp_le_u32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0b,0xbf]
-
-s_cmp_le_u32 s1, m0
-// CHECK: [0x01,0x7c,0x0b,0xbf]
-
-s_cmp_le_u32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0b,0xbf]
-
-s_cmp_le_u32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0b,0xbf]
-
-s_cmp_le_u32 s1, 0
-// CHECK: [0x01,0x80,0x0b,0xbf]
-
-s_cmp_le_u32 s1, -1
-// CHECK: [0x01,0xc1,0x0b,0xbf]
-
-s_cmp_le_u32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0b,0xbf]
-
-s_cmp_le_u32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0b,0xbf]
-
-s_cmp_le_u32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_le_u32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b32 s1, s2
-// CHECK: [0x01,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 s101, s2
-// CHECK: [0x65,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 m0, s2
-// CHECK: [0x7c,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 0, s2
-// CHECK: [0x80,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 -1, s2
-// CHECK: [0xc1,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 0.5, s2
-// CHECK: [0xf0,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0c,0xbf]
-
-s_bitcmp0_b32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0c,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0c,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b32 s1, s101
-// CHECK: [0x01,0x65,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, m0
-// CHECK: [0x01,0x7c,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, 0
-// CHECK: [0x01,0x80,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, -1
-// CHECK: [0x01,0xc1,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0c,0xbf]
-
-s_bitcmp0_b32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b32 s1, s2
-// CHECK: [0x01,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 s101, s2
-// CHECK: [0x65,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 vcc_lo, s2
-// CHECK: [0x6a,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 vcc_hi, s2
-// CHECK: [0x6b,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 m0, s2
-// CHECK: [0x7c,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 exec_lo, s2
-// CHECK: [0x7e,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 exec_hi, s2
-// CHECK: [0x7f,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 0, s2
-// CHECK: [0x80,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 -1, s2
-// CHECK: [0xc1,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 0.5, s2
-// CHECK: [0xf0,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 -4.0, s2
-// CHECK: [0xf7,0x02,0x0d,0xbf]
-
-s_bitcmp1_b32 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0d,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b32 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0d,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b32 s1, s101
-// CHECK: [0x01,0x65,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, vcc_lo
-// CHECK: [0x01,0x6a,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, vcc_hi
-// CHECK: [0x01,0x6b,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, m0
-// CHECK: [0x01,0x7c,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, exec_lo
-// CHECK: [0x01,0x7e,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, exec_hi
-// CHECK: [0x01,0x7f,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, 0
-// CHECK: [0x01,0x80,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, -1
-// CHECK: [0x01,0xc1,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, 0.5
-// CHECK: [0x01,0xf0,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, -4.0
-// CHECK: [0x01,0xf7,0x0d,0xbf]
-
-s_bitcmp1_b32 s1, 0xaf123456
-// CHECK: [0x01,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b32 s1, 0x3f717273
-// CHECK: [0x01,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b64 s[2:3], s2
-// CHECK: [0x02,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 s[4:5], s2
-// CHECK: [0x04,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 s[100:101], s2
-// CHECK: [0x64,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 flat_scratch, s2
-// CHECK: [0x66,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 vcc, s2
-// CHECK: [0x6a,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 exec, s2
-// CHECK: [0x7e,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 0, s2
-// CHECK: [0x80,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 -1, s2
-// CHECK: [0xc1,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 0.5, s2
-// CHECK: [0xf0,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 -4.0, s2
-// CHECK: [0xf7,0x02,0x0e,0xbf]
-
-s_bitcmp0_b64 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0e,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b64 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0e,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp0_b64 s[2:3], s101
-// CHECK: [0x02,0x65,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], m0
-// CHECK: [0x02,0x7c,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], 0
-// CHECK: [0x02,0x80,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x0e,0xbf]
-
-s_bitcmp0_b64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp0_b64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b64 s[2:3], s2
-// CHECK: [0x02,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 s[4:5], s2
-// CHECK: [0x04,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 s[100:101], s2
-// CHECK: [0x64,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 flat_scratch, s2
-// CHECK: [0x66,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 vcc, s2
-// CHECK: [0x6a,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 exec, s2
-// CHECK: [0x7e,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 0, s2
-// CHECK: [0x80,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 -1, s2
-// CHECK: [0xc1,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 0.5, s2
-// CHECK: [0xf0,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 -4.0, s2
-// CHECK: [0xf7,0x02,0x0f,0xbf]
-
-s_bitcmp1_b64 0xaf123456, s2
-// CHECK: [0xff,0x02,0x0f,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b64 0x3f717273, s2
-// CHECK: [0xff,0x02,0x0f,0xbf,0x73,0x72,0x71,0x3f]
-
-s_bitcmp1_b64 s[2:3], s101
-// CHECK: [0x02,0x65,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], flat_scratch_lo
-// CHECK: [0x02,0x66,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], flat_scratch_hi
-// CHECK: [0x02,0x67,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], vcc_lo
-// CHECK: [0x02,0x6a,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], vcc_hi
-// CHECK: [0x02,0x6b,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], m0
-// CHECK: [0x02,0x7c,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], exec_lo
-// CHECK: [0x02,0x7e,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], exec_hi
-// CHECK: [0x02,0x7f,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], 0
-// CHECK: [0x02,0x80,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x0f,0xbf]
-
-s_bitcmp1_b64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf]
-
-s_bitcmp1_b64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f]
-
-s_setvskip s1, s2
-// CHECK: [0x01,0x02,0x10,0xbf]
-
-s_setvskip s101, s2
-// CHECK: [0x65,0x02,0x10,0xbf]
-
-s_setvskip flat_scratch_lo, s2
-// CHECK: [0x66,0x02,0x10,0xbf]
-
-s_setvskip flat_scratch_hi, s2
-// CHECK: [0x67,0x02,0x10,0xbf]
-
-s_setvskip vcc_lo, s2
-// CHECK: [0x6a,0x02,0x10,0xbf]
-
-s_setvskip vcc_hi, s2
-// CHECK: [0x6b,0x02,0x10,0xbf]
-
-s_setvskip m0, s2
-// CHECK: [0x7c,0x02,0x10,0xbf]
-
-s_setvskip exec_lo, s2
-// CHECK: [0x7e,0x02,0x10,0xbf]
-
-s_setvskip exec_hi, s2
-// CHECK: [0x7f,0x02,0x10,0xbf]
-
-s_setvskip 0, s2
-// CHECK: [0x80,0x02,0x10,0xbf]
-
-s_setvskip -1, s2
-// CHECK: [0xc1,0x02,0x10,0xbf]
-
-s_setvskip 0.5, s2
-// CHECK: [0xf0,0x02,0x10,0xbf]
-
-s_setvskip -4.0, s2
-// CHECK: [0xf7,0x02,0x10,0xbf]
-
-s_setvskip 0xaf123456, s2
-// CHECK: [0xff,0x02,0x10,0xbf,0x56,0x34,0x12,0xaf]
-
-s_setvskip 0x3f717273, s2
-// CHECK: [0xff,0x02,0x10,0xbf,0x73,0x72,0x71,0x3f]
-
-s_setvskip s1, s101
-// CHECK: [0x01,0x65,0x10,0xbf]
-
-s_setvskip s1, flat_scratch_lo
-// CHECK: [0x01,0x66,0x10,0xbf]
-
-s_setvskip s1, flat_scratch_hi
-// CHECK: [0x01,0x67,0x10,0xbf]
-
-s_setvskip s1, vcc_lo
-// CHECK: [0x01,0x6a,0x10,0xbf]
-
-s_setvskip s1, vcc_hi
-// CHECK: [0x01,0x6b,0x10,0xbf]
-
-s_setvskip s1, m0
-// CHECK: [0x01,0x7c,0x10,0xbf]
-
-s_setvskip s1, exec_lo
-// CHECK: [0x01,0x7e,0x10,0xbf]
-
-s_setvskip s1, exec_hi
-// CHECK: [0x01,0x7f,0x10,0xbf]
-
-s_setvskip s1, 0
-// CHECK: [0x01,0x80,0x10,0xbf]
-
-s_setvskip s1, -1
-// CHECK: [0x01,0xc1,0x10,0xbf]
-
-s_setvskip s1, 0.5
-// CHECK: [0x01,0xf0,0x10,0xbf]
-
-s_setvskip s1, -4.0
-// CHECK: [0x01,0xf7,0x10,0xbf]
-
-s_setvskip s1, 0xaf123456
-// CHECK: [0x01,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf]
-
-s_setvskip s1, 0x3f717273
-// CHECK: [0x01,0xff,0x10,0xbf,0x73,0x72,0x71,0x3f]
-
-s_set_gpr_idx_on s1, 0x0
-// CHECK: [0x01,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on s101, 0x0
-// CHECK: [0x65,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on flat_scratch_lo, 0x0
-// CHECK: [0x66,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on flat_scratch_hi, 0x0
-// CHECK: [0x67,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on vcc_lo, 0x0
-// CHECK: [0x6a,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on vcc_hi, 0x0
-// CHECK: [0x6b,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on m0, 0x0
-// CHECK: [0x7c,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on 0, 0x0
-// CHECK: [0x80,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on -1, 0x0
-// CHECK: [0xc1,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on 0.5, 0x0
-// CHECK: [0xf0,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on -4.0, 0x0
-// CHECK: [0xf7,0x00,0x11,0xbf]
-
-s_set_gpr_idx_on 0xaf123456, 0x0
-// CHECK: [0xff,0x00,0x11,0xbf,0x56,0x34,0x12,0xaf]
-
-s_set_gpr_idx_on 0x3f717273, 0x0
-// CHECK: [0xff,0x00,0x11,0xbf,0x73,0x72,0x71,0x3f]
-
-s_set_gpr_idx_on s1, 0x1
-// CHECK: [0x01,0x01,0x11,0xbf]
-
-s_set_gpr_idx_on s1, 0xF
-// CHECK: [0x01,0x0f,0x11,0xbf]
-
-s_cmp_eq_u64 s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 exec, s[4:5]
-// CHECK: [0x7e,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 0, s[4:5]
-// CHECK: [0x80,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 -1, s[4:5]
-// CHECK: [0xc1,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x12,0xbf]
-
-s_cmp_eq_u64 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x12,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u64 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x12,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_eq_u64 s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], vcc
-// CHECK: [0x02,0x6a,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], exec
-// CHECK: [0x02,0x7e,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], 0
-// CHECK: [0x02,0x80,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x12,0xbf]
-
-s_cmp_eq_u64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x12,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_eq_u64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x12,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u64 s[2:3], s[4:5]
-// CHECK: [0x02,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 s[4:5], s[4:5]
-// CHECK: [0x04,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 s[100:101], s[4:5]
-// CHECK: [0x64,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 flat_scratch, s[4:5]
-// CHECK: [0x66,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 vcc, s[4:5]
-// CHECK: [0x6a,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 exec, s[4:5]
-// CHECK: [0x7e,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 0, s[4:5]
-// CHECK: [0x80,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 -1, s[4:5]
-// CHECK: [0xc1,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 0.5, s[4:5]
-// CHECK: [0xf0,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 -4.0, s[4:5]
-// CHECK: [0xf7,0x04,0x13,0xbf]
-
-s_cmp_lg_u64 0xaf123456, s[4:5]
-// CHECK: [0xff,0x04,0x13,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u64 0x3f717273, s[4:5]
-// CHECK: [0xff,0x04,0x13,0xbf,0x73,0x72,0x71,0x3f]
-
-s_cmp_lg_u64 s[2:3], s[6:7]
-// CHECK: [0x02,0x06,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], s[100:101]
-// CHECK: [0x02,0x64,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], flat_scratch
-// CHECK: [0x02,0x66,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], vcc
-// CHECK: [0x02,0x6a,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], exec
-// CHECK: [0x02,0x7e,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], 0
-// CHECK: [0x02,0x80,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], -1
-// CHECK: [0x02,0xc1,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], 0.5
-// CHECK: [0x02,0xf0,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], -4.0
-// CHECK: [0x02,0xf7,0x13,0xbf]
-
-s_cmp_lg_u64 s[2:3], 0xaf123456
-// CHECK: [0x02,0xff,0x13,0xbf,0x56,0x34,0x12,0xaf]
-
-s_cmp_lg_u64 s[2:3], 0x3f717273
-// CHECK: [0x02,0xff,0x13,0xbf,0x73,0x72,0x71,0x3f]
-
-s_movk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x05,0xb0]
-
-s_movk_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb0]
-
-s_movk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb0]
-
-s_movk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb0]
-
-s_movk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb0]
-
-s_movk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb0]
-
-s_movk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb0]
-
-s_movk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb0]
-
-s_movk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb0]
-
-s_movk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x05,0xb0]
-
-s_cmovk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x85,0xb0]
-
-s_cmovk_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb0]
-
-s_cmovk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb0]
-
-s_cmovk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb0]
-
-s_cmovk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb0]
-
-s_cmovk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb0]
-
-s_cmovk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb0]
-
-s_cmovk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb0]
-
-s_cmovk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb0]
-
-s_cmovk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x85,0xb0]
-
-s_cmpk_eq_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb1]
-
-s_cmpk_eq_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb1]
-
-s_cmpk_eq_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb1]
-
-s_cmpk_eq_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb1]
-
-s_cmpk_eq_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb1]
-
-s_cmpk_eq_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb1]
-
-s_cmpk_eq_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb1]
-
-s_cmpk_eq_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb1]
-
-s_cmpk_eq_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb1]
-
-s_cmpk_eq_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb1]
-
-s_cmpk_lg_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb1]
-
-s_cmpk_lg_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb1]
-
-s_cmpk_lg_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb1]
-
-s_cmpk_lg_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb1]
-
-s_cmpk_lg_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb1]
-
-s_cmpk_lg_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb1]
-
-s_cmpk_lg_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb1]
-
-s_cmpk_lg_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb1]
-
-s_cmpk_lg_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb1]
-
-s_cmpk_lg_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb1]
-
-s_cmpk_gt_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb2]
-
-s_cmpk_gt_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb2]
-
-s_cmpk_gt_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb2]
-
-s_cmpk_gt_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb2]
-
-s_cmpk_gt_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb2]
-
-s_cmpk_gt_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb2]
-
-s_cmpk_gt_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb2]
-
-s_cmpk_gt_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb2]
-
-s_cmpk_gt_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb2]
-
-s_cmpk_gt_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb2]
-
-s_cmpk_ge_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb2]
-
-s_cmpk_ge_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb2]
-
-s_cmpk_ge_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb2]
-
-s_cmpk_ge_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb2]
-
-s_cmpk_ge_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb2]
-
-s_cmpk_ge_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb2]
-
-s_cmpk_ge_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb2]
-
-s_cmpk_ge_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb2]
-
-s_cmpk_ge_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb2]
-
-s_cmpk_ge_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb2]
-
-s_cmpk_lt_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb3]
-
-s_cmpk_lt_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb3]
-
-s_cmpk_lt_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb3]
-
-s_cmpk_lt_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb3]
-
-s_cmpk_lt_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb3]
-
-s_cmpk_lt_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb3]
-
-s_cmpk_lt_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb3]
-
-s_cmpk_lt_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb3]
-
-s_cmpk_lt_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb3]
-
-s_cmpk_lt_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb3]
-
-s_cmpk_le_i32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb3]
-
-s_cmpk_le_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb3]
-
-s_cmpk_le_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb3]
-
-s_cmpk_le_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb3]
-
-s_cmpk_le_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb3]
-
-s_cmpk_le_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb3]
-
-s_cmpk_le_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb3]
-
-s_cmpk_le_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb3]
-
-s_cmpk_le_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb3]
-
-s_cmpk_le_i32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb3]
-
-s_cmpk_eq_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb4]
-
-s_cmpk_eq_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb4]
-
-s_cmpk_eq_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb4]
-
-s_cmpk_eq_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb4]
-
-s_cmpk_eq_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb4]
-
-s_cmpk_eq_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb4]
-
-s_cmpk_eq_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb4]
-
-s_cmpk_eq_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb4]
-
-s_cmpk_eq_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb4]
-
-s_cmpk_eq_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb4]
-
-s_cmpk_lg_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb4]
-
-s_cmpk_lg_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb4]
-
-s_cmpk_lg_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb4]
-
-s_cmpk_lg_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb4]
-
-s_cmpk_lg_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb4]
-
-s_cmpk_lg_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb4]
-
-s_cmpk_lg_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb4]
-
-s_cmpk_lg_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb4]
-
-s_cmpk_lg_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb4]
-
-s_cmpk_lg_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb4]
-
-s_cmpk_gt_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb5]
-
-s_cmpk_gt_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb5]
-
-s_cmpk_gt_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb5]
-
-s_cmpk_gt_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb5]
-
-s_cmpk_gt_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb5]
-
-s_cmpk_gt_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb5]
-
-s_cmpk_gt_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb5]
-
-s_cmpk_gt_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb5]
-
-s_cmpk_gt_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb5]
-
-s_cmpk_gt_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb5]
-
-s_cmpk_ge_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb5]
-
-s_cmpk_ge_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb5]
-
-s_cmpk_ge_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb5]
-
-s_cmpk_ge_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb5]
-
-s_cmpk_ge_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb5]
-
-s_cmpk_ge_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb5]
-
-s_cmpk_ge_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb5]
-
-s_cmpk_ge_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb5]
-
-s_cmpk_ge_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb5]
-
-s_cmpk_ge_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb5]
-
-s_cmpk_lt_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x01,0xb6]
-
-s_cmpk_lt_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb6]
-
-s_cmpk_lt_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb6]
-
-s_cmpk_lt_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb6]
-
-s_cmpk_lt_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb6]
-
-s_cmpk_lt_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb6]
-
-s_cmpk_lt_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb6]
-
-s_cmpk_lt_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb6]
-
-s_cmpk_lt_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb6]
-
-s_cmpk_lt_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x01,0xb6]
-
-s_cmpk_le_u32 s1, 0x3141
-// CHECK: [0x41,0x31,0x81,0xb6]
-
-s_cmpk_le_u32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb6]
-
-s_cmpk_le_u32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb6]
-
-s_cmpk_le_u32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb6]
-
-s_cmpk_le_u32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb6]
-
-s_cmpk_le_u32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb6]
-
-s_cmpk_le_u32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb6]
-
-s_cmpk_le_u32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb6]
-
-s_cmpk_le_u32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb6]
-
-s_cmpk_le_u32 s1, 0xc1d1
-// CHECK: [0xd1,0xc1,0x81,0xb6]
-
-s_addk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x05,0xb7]
-
-s_addk_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0x65,0xb7]
-
-s_addk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0x66,0xb7]
-
-s_addk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0x67,0xb7]
-
-s_addk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0x6a,0xb7]
-
-s_addk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0x6b,0xb7]
-
-s_addk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0x7c,0xb7]
-
-s_addk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0x7e,0xb7]
-
-s_addk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0x7f,0xb7]
-
-s_addk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x05,0xb7]
-
-s_mulk_i32 s5, 0x3141
-// CHECK: [0x41,0x31,0x85,0xb7]
-
-s_mulk_i32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb7]
-
-s_mulk_i32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb7]
-
-s_mulk_i32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb7]
-
-s_mulk_i32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb7]
-
-s_mulk_i32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb7]
-
-s_mulk_i32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb7]
-
-s_mulk_i32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb7]
-
-s_mulk_i32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb7]
-
-s_mulk_i32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x85,0xb7]
-
-s_cbranch_i_fork s[2:3], 12609
-// CHECK: [0x41,0x31,0x02,0xb8]
-
-s_cbranch_i_fork s[4:5], 12609
-// CHECK: [0x41,0x31,0x04,0xb8]
-
-s_cbranch_i_fork s[100:101], 12609
-// CHECK: [0x41,0x31,0x64,0xb8]
-
-s_cbranch_i_fork flat_scratch, 12609
-// CHECK: [0x41,0x31,0x66,0xb8]
-
-s_cbranch_i_fork vcc, 12609
-// CHECK: [0x41,0x31,0x6a,0xb8]
-
-s_cbranch_i_fork exec, 12609
-// CHECK: [0x41,0x31,0x7e,0xb8]
-
-s_cbranch_i_fork s[2:3], 49617
-// CHECK: [0xd1,0xc1,0x02,0xb8]
-
-s_getreg_b32 s5, 0x3141
-// CHECK: [0x41,0x31,0x85,0xb8]
-
-s_getreg_b32 s101, 0x3141
-// CHECK: [0x41,0x31,0xe5,0xb8]
-
-s_getreg_b32 flat_scratch_lo, 0x3141
-// CHECK: [0x41,0x31,0xe6,0xb8]
-
-s_getreg_b32 flat_scratch_hi, 0x3141
-// CHECK: [0x41,0x31,0xe7,0xb8]
-
-s_getreg_b32 vcc_lo, 0x3141
-// CHECK: [0x41,0x31,0xea,0xb8]
-
-s_getreg_b32 vcc_hi, 0x3141
-// CHECK: [0x41,0x31,0xeb,0xb8]
-
-s_getreg_b32 m0, 0x3141
-// CHECK: [0x41,0x31,0xfc,0xb8]
-
-s_getreg_b32 exec_lo, 0x3141
-// CHECK: [0x41,0x31,0xfe,0xb8]
-
-s_getreg_b32 exec_hi, 0x3141
-// CHECK: [0x41,0x31,0xff,0xb8]
-
-s_getreg_b32 s5, 0xc1d1
-// CHECK: [0xd1,0xc1,0x85,0xb8]
-
-s_setreg_b32 0x3141, s1
-// CHECK: [0x41,0x31,0x01,0xb9]
-
-s_setreg_b32 0xc1d1, s1
-// CHECK: [0xd1,0xc1,0x01,0xb9]
-
-s_setreg_b32 0x3141, s101
-// CHECK: [0x41,0x31,0x65,0xb9]
-
-s_setreg_b32 0x3141, flat_scratch_lo
-// CHECK: [0x41,0x31,0x66,0xb9]
-
-s_setreg_b32 0x3141, flat_scratch_hi
-// CHECK: [0x41,0x31,0x67,0xb9]
-
-s_setreg_b32 0x3141, vcc_lo
-// CHECK: [0x41,0x31,0x6a,0xb9]
-
-s_setreg_b32 0x3141, vcc_hi
-// CHECK: [0x41,0x31,0x6b,0xb9]
-
-s_setreg_b32 0x3141, m0
-// CHECK: [0x41,0x31,0x7c,0xb9]
-
-s_setreg_b32 0x3141, exec_lo
-// CHECK: [0x41,0x31,0x7e,0xb9]
-
-s_setreg_b32 0x3141, exec_hi
-// CHECK: [0x41,0x31,0x7f,0xb9]
-
-s_setreg_imm32_b32 0x3141, 0x11213141
-// CHECK: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
-
-s_setreg_imm32_b32 0xc1d1, 0x11213141
-// CHECK: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
-
-s_setreg_imm32_b32 0x3141, 0xa1b1c1d1
-// CHECK: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]
-
-s_nop 0x3141
-// CHECK: [0x41,0x31,0x80,0xbf]
-
-s_nop 0xc1d1
-// CHECK: [0xd1,0xc1,0x80,0xbf]
-
-s_endpgm
-// CHECK: [0x00,0x00,0x81,0xbf]
-
-s_branch 12609
-// CHECK: [0x41,0x31,0x82,0xbf]
-
-s_branch 49617
-// CHECK: [0xd1,0xc1,0x82,0xbf]
-
-s_wakeup
-// CHECK: [0x00,0x00,0x83,0xbf]
-
-s_cbranch_scc0 12609
-// CHECK: [0x41,0x31,0x84,0xbf]
-
-s_cbranch_scc0 49617
-// CHECK: [0xd1,0xc1,0x84,0xbf]
-
-s_cbranch_scc1 12609
-// CHECK: [0x41,0x31,0x85,0xbf]
-
-s_cbranch_scc1 49617
-// CHECK: [0xd1,0xc1,0x85,0xbf]
-
-s_cbranch_vccz 12609
-// CHECK: [0x41,0x31,0x86,0xbf]
-
-s_cbranch_vccz 49617
-// CHECK: [0xd1,0xc1,0x86,0xbf]
-
-s_cbranch_vccnz 12609
-// CHECK: [0x41,0x31,0x87,0xbf]
-
-s_cbranch_vccnz 49617
-// CHECK: [0xd1,0xc1,0x87,0xbf]
-
-s_cbranch_execz 12609
-// CHECK: [0x41,0x31,0x88,0xbf]
-
-s_cbranch_execz 49617
-// CHECK: [0xd1,0xc1,0x88,0xbf]
-
-s_cbranch_execnz 12609
-// CHECK: [0x41,0x31,0x89,0xbf]
-
-s_cbranch_execnz 49617
-// CHECK: [0xd1,0xc1,0x89,0xbf]
-
-s_barrier
-// CHECK: [0x00,0x00,0x8a,0xbf]
-
-s_setkill 0x3141
-// CHECK: [0x41,0x31,0x8b,0xbf]
-
-s_setkill 0xc1d1
-// CHECK: [0xd1,0xc1,0x8b,0xbf]
-
-s_waitcnt 0x3141
-// CHECK: [0x41,0x31,0x8c,0xbf]
-
-s_waitcnt 0xc1d1
-// CHECK: [0xd1,0xc1,0x8c,0xbf]
-
-s_sethalt 0x3141
-// CHECK: [0x41,0x31,0x8d,0xbf]
-
-s_sethalt 0xc1d1
-// CHECK: [0xd1,0xc1,0x8d,0xbf]
-
-s_sleep 0x3141
-// CHECK: [0x41,0x31,0x8e,0xbf]
-
-s_sleep 0xc1d1
-// CHECK: [0xd1,0xc1,0x8e,0xbf]
-
-s_setprio 0x3141
-// CHECK: [0x41,0x31,0x8f,0xbf]
-
-s_setprio 0xc1d1
-// CHECK: [0xd1,0xc1,0x8f,0xbf]
-
-s_sendmsg 0x3141
-// CHECK: [0x41,0x31,0x90,0xbf]
-
-s_sendmsg 0xc1d1
-// CHECK: [0xd1,0xc1,0x90,0xbf]
-
-s_sendmsghalt 0x3141
-// CHECK: [0x41,0x31,0x91,0xbf]
-
-s_sendmsghalt 0xc1d1
-// CHECK: [0xd1,0xc1,0x91,0xbf]
-
-s_trap 0x3141
-// CHECK: [0x41,0x31,0x92,0xbf]
-
-s_trap 0xc1d1
-// CHECK: [0xd1,0xc1,0x92,0xbf]
-
-s_icache_inv
-// CHECK: [0x00,0x00,0x93,0xbf]
-
-s_incperflevel 0x3141
-// CHECK: [0x41,0x31,0x94,0xbf]
-
-s_incperflevel 0xc1d1
-// CHECK: [0xd1,0xc1,0x94,0xbf]
-
-s_decperflevel 0x3141
-// CHECK: [0x41,0x31,0x95,0xbf]
-
-s_decperflevel 0xc1d1
-// CHECK: [0xd1,0xc1,0x95,0xbf]
-
-s_ttracedata
-// CHECK: [0x00,0x00,0x96,0xbf]
-
-s_cbranch_cdbgsys 12609
-// CHECK: [0x41,0x31,0x97,0xbf]
-
-s_cbranch_cdbgsys 49617
-// CHECK: [0xd1,0xc1,0x97,0xbf]
-
-s_cbranch_cdbguser 12609
-// CHECK: [0x41,0x31,0x98,0xbf]
-
-s_cbranch_cdbguser 49617
-// CHECK: [0xd1,0xc1,0x98,0xbf]
-
-s_cbranch_cdbgsys_or_user 12609
-// CHECK: [0x41,0x31,0x99,0xbf]
-
-s_cbranch_cdbgsys_or_user 49617
-// CHECK: [0xd1,0xc1,0x99,0xbf]
-
-s_cbranch_cdbgsys_and_user 12609
-// CHECK: [0x41,0x31,0x9a,0xbf]
-
-s_cbranch_cdbgsys_and_user 49617
-// CHECK: [0xd1,0xc1,0x9a,0xbf]
-
-s_endpgm_saved
-// CHECK: [0x00,0x00,0x9b,0xbf]
-
-s_set_gpr_idx_off
-// CHECK: [0x00,0x00,0x9c,0xbf]
-
-s_set_gpr_idx_mode 0x0
-// CHECK: [0x00,0x00,0x9d,0xbf]
-
-s_set_gpr_idx_mode 0x1
-// CHECK: [0x01,0x00,0x9d,0xbf]
-
-s_set_gpr_idx_mode 0xF
-// CHECK: [0x0f,0x00,0x9d,0xbf]
-
-v_interp_p1_f32 v5, v1, attr0.x
-// CHECK: [0x01,0x00,0x14,0xd4]
-
-v_interp_p1_f32 v255, v1, attr0.x
-// CHECK: [0x01,0x00,0xfc,0xd7]
-
-v_interp_p1_f32 v5, v255, attr0.x
-// CHECK: [0xff,0x00,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr1.x
-// CHECK: [0x01,0x04,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr31.x
-// CHECK: [0x01,0x7c,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr32.x
-// CHECK: [0x01,0x80,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr0.y
-// CHECK: [0x01,0x01,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr0.z
-// CHECK: [0x01,0x02,0x14,0xd4]
-
-v_interp_p1_f32 v5, v1, attr0.w
-// CHECK: [0x01,0x03,0x14,0xd4]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v255, v2, attr0.x
-// CHECK: [0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr1.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr31.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x1f,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr32.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x20,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v255, attr0.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0xfe,0x03,0x00]
-
-v_interp_p1_f32_e64 v5, -v2, attr0.x
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
-
-v_interp_p1_f32_e64 v5, |v2|, attr0.x
-// CHECK: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.y
-// CHECK: [0x05,0x00,0x70,0xd2,0x40,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.z
-// CHECK: [0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.w
-// CHECK: [0x05,0x00,0x70,0xd2,0xc0,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x clamp
-// CHECK: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x mul:4
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x10]
-
-v_interp_p1_f32_e64 v5, v2, attr0.x div:2
-// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x18]
-
-v_interp_p2_f32 v5, v1, attr0.x
-// CHECK: [0x01,0x00,0x15,0xd4]
-
-v_interp_p2_f32 v255, v1, attr0.x
-// CHECK: [0x01,0x00,0xfd,0xd7]
-
-v_interp_p2_f32 v5, v255, attr0.x
-// CHECK: [0xff,0x00,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr1.x
-// CHECK: [0x01,0x04,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr31.x
-// CHECK: [0x01,0x7c,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr32.x
-// CHECK: [0x01,0x80,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr0.y
-// CHECK: [0x01,0x01,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr0.z
-// CHECK: [0x01,0x02,0x15,0xd4]
-
-v_interp_p2_f32 v5, v1, attr0.w
-// CHECK: [0x01,0x03,0x15,0xd4]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v255, v2, attr0.x
-// CHECK: [0xff,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr1.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x01,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr31.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr32.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x20,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v255, attr0.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0xfe,0x03,0x00]
-
-v_interp_p2_f32_e64 v5, -v2, attr0.x
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
-
-v_interp_p2_f32_e64 v5, |v2|, attr0.x
-// CHECK: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.y
-// CHECK: [0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.z
-// CHECK: [0x05,0x00,0x71,0xd2,0x80,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.w
-// CHECK: [0x05,0x00,0x71,0xd2,0xc0,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x clamp
-// CHECK: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x mul:2
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x08]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x mul:4
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10]
-
-v_interp_p2_f32_e64 v5, v2, attr0.x div:2
-// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x18]
-
-v_interp_mov_f32 v5, p10, attr0.x
-// CHECK: [0x00,0x00,0x16,0xd4]
-
-v_interp_mov_f32 v255, p10, attr0.x
-// CHECK: [0x00,0x00,0xfe,0xd7]
-
-v_interp_mov_f32 v5, p20, attr0.x
-// CHECK: [0x01,0x00,0x16,0xd4]
-
-v_interp_mov_f32 v5, p0, attr0.x
-// CHECK: [0x02,0x00,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr1.x
-// CHECK: [0x00,0x04,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr31.x
-// CHECK: [0x00,0x7c,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr32.x
-// CHECK: [0x00,0x80,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr0.y
-// CHECK: [0x00,0x01,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr0.z
-// CHECK: [0x00,0x02,0x16,0xd4]
-
-v_interp_mov_f32 v5, p10, attr0.w
-// CHECK: [0x00,0x03,0x16,0xd4]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v255, p10, attr0.x
-// CHECK: [0xff,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr1.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x01,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr31.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x1f,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr32.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p20, attr0.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p0, attr0.x
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x04,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.y
-// CHECK: [0x05,0x00,0x72,0xd2,0x40,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.z
-// CHECK: [0x05,0x00,0x72,0xd2,0x80,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.w
-// CHECK: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x clamp
-// CHECK: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
-
-v_interp_mov_f32_e64 v5, p10, attr0.x div:2
-// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
-
-v_nop
-// CHECK: [0x00,0x00,0x00,0x7e]
-
-v_nop_e64
-// CHECK: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
-
-v_mov_b32 v5, v1
-// CHECK: [0x01,0x03,0x0a,0x7e]
-
-v_mov_b32 v255, v1
-// CHECK: [0x01,0x03,0xfe,0x7f]
-
-v_mov_b32 v5, v255
-// CHECK: [0xff,0x03,0x0a,0x7e]
-
-v_mov_b32 v5, s1
-// CHECK: [0x01,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, s101
-// CHECK: [0x65,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, flat_scratch_lo
-// CHECK: [0x66,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, flat_scratch_hi
-// CHECK: [0x67,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, vcc_lo
-// CHECK: [0x6a,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, vcc_hi
-// CHECK: [0x6b,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, m0
-// CHECK: [0x7c,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, exec_lo
-// CHECK: [0x7e,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, exec_hi
-// CHECK: [0x7f,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, 0
-// CHECK: [0x80,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, -1
-// CHECK: [0xc1,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, 0.5
-// CHECK: [0xf0,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, -4.0
-// CHECK: [0xf7,0x02,0x0a,0x7e]
-
-v_mov_b32 v5, 0xaf123456
-// CHECK: [0xff,0x02,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_mov_b32 v5, 0x3f717273
-// CHECK: [0xff,0x02,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_mov_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x41,0xd1,0x01,0x01,0x00,0x00]
-
-v_mov_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x41,0xd1,0x01,0x01,0x00,0x00]
-
-v_mov_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x41,0xd1,0xff,0x01,0x00,0x00]
-
-v_mov_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x41,0xd1,0x01,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, s101
-// CHECK: [0x05,0x00,0x41,0xd1,0x65,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x41,0xd1,0x66,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x41,0xd1,0x67,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x41,0xd1,0x6a,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x41,0xd1,0x6b,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x41,0xd1,0x7c,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x41,0xd1,0x7e,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x41,0xd1,0x7f,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x41,0xd1,0x80,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x41,0xd1,0xc1,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x41,0xd1,0xf0,0x00,0x00,0x00]
-
-v_mov_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x41,0xd1,0xf7,0x00,0x00,0x00]
-
-v_readfirstlane_b32 s5, v1
-// CHECK: [0x01,0x05,0x0a,0x7e]
-
-v_readfirstlane_b32 s101, v1
-// CHECK: [0x01,0x05,0xca,0x7e]
-
-v_readfirstlane_b32 flat_scratch_lo, v1
-// CHECK: [0x01,0x05,0xcc,0x7e]
-
-v_readfirstlane_b32 flat_scratch_hi, v1
-// CHECK: [0x01,0x05,0xce,0x7e]
-
-v_readfirstlane_b32 s5, v255
-// CHECK: [0xff,0x05,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, v[1:2]
-// CHECK: [0x01,0x07,0x0a,0x7e]
-
-v_cvt_i32_f64 v255, v[1:2]
-// CHECK: [0x01,0x07,0xfe,0x7f]
-
-v_cvt_i32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x07,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, s[2:3]
-// CHECK: [0x02,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, s[4:5]
-// CHECK: [0x04,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, s[100:101]
-// CHECK: [0x64,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, flat_scratch
-// CHECK: [0x66,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, vcc
-// CHECK: [0x6a,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, exec
-// CHECK: [0x7e,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, 0
-// CHECK: [0x80,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, -1
-// CHECK: [0xc1,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, 0.5
-// CHECK: [0xf0,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, -4.0
-// CHECK: [0xf7,0x06,0x0a,0x7e]
-
-v_cvt_i32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x06,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_i32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x06,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_i32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x43,0xd1,0x02,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x43,0xd1,0x04,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, s[100:101]
-// CHECK: [0x05,0x00,0x43,0xd1,0x64,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x43,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x43,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x43,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x43,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x43,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x43,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x43,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_i32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x43,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f64_e64 v5, v[1:2] clamp
-// CHECK: [0x05,0x80,0x43,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32 v[5:6], v1
-// CHECK: [0x01,0x09,0x0a,0x7e]
-
-v_cvt_f64_i32 v[254:255], v1
-// CHECK: [0x01,0x09,0xfc,0x7f]
-
-v_cvt_f64_i32 v[5:6], v255
-// CHECK: [0xff,0x09,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], s1
-// CHECK: [0x01,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], s101
-// CHECK: [0x65,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], flat_scratch_lo
-// CHECK: [0x66,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], flat_scratch_hi
-// CHECK: [0x67,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], vcc_lo
-// CHECK: [0x6a,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], vcc_hi
-// CHECK: [0x6b,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], m0
-// CHECK: [0x7c,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], exec_lo
-// CHECK: [0x7e,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], exec_hi
-// CHECK: [0x7f,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], 0
-// CHECK: [0x80,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], -1
-// CHECK: [0xc1,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], 0.5
-// CHECK: [0xf0,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], -4.0
-// CHECK: [0xf7,0x08,0x0a,0x7e]
-
-v_cvt_f64_i32 v[5:6], 0xaf123456
-// CHECK: [0xff,0x08,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_i32 v[5:6], 0x3f717273
-// CHECK: [0xff,0x08,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_i32_e64 v[5:6], v1
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[254:255], v1
-// CHECK: [0xfe,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v255
-// CHECK: [0x05,0x00,0x44,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], s1
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], s101
-// CHECK: [0x05,0x00,0x44,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], flat_scratch_lo
-// CHECK: [0x05,0x00,0x44,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], flat_scratch_hi
-// CHECK: [0x05,0x00,0x44,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], vcc_lo
-// CHECK: [0x05,0x00,0x44,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], vcc_hi
-// CHECK: [0x05,0x00,0x44,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], m0
-// CHECK: [0x05,0x00,0x44,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], exec_lo
-// CHECK: [0x05,0x00,0x44,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], exec_hi
-// CHECK: [0x05,0x00,0x44,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x44,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x44,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x44,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x44,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v1 clamp
-// CHECK: [0x05,0x80,0x44,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_i32_e64 v[5:6], v1 mul:2
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_i32_e64 v[5:6], v1 mul:4
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_i32_e64 v[5:6], v1 div:2
-// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_i32 v5, v1
-// CHECK: [0x01,0x0b,0x0a,0x7e]
-
-v_cvt_f32_i32 v255, v1
-// CHECK: [0x01,0x0b,0xfe,0x7f]
-
-v_cvt_f32_i32 v5, v255
-// CHECK: [0xff,0x0b,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, s1
-// CHECK: [0x01,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, s101
-// CHECK: [0x65,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, flat_scratch_lo
-// CHECK: [0x66,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, flat_scratch_hi
-// CHECK: [0x67,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, vcc_lo
-// CHECK: [0x6a,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, vcc_hi
-// CHECK: [0x6b,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, m0
-// CHECK: [0x7c,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, exec_lo
-// CHECK: [0x7e,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, exec_hi
-// CHECK: [0x7f,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, 0
-// CHECK: [0x80,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, -1
-// CHECK: [0xc1,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, 0.5
-// CHECK: [0xf0,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, -4.0
-// CHECK: [0xf7,0x0a,0x0a,0x7e]
-
-v_cvt_f32_i32 v5, 0xaf123456
-// CHECK: [0xff,0x0a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_i32 v5, 0x3f717273
-// CHECK: [0xff,0x0a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_i32_e64 v5, v1
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v255, v1
-// CHECK: [0xff,0x00,0x45,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v255
-// CHECK: [0x05,0x00,0x45,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, s1
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, s101
-// CHECK: [0x05,0x00,0x45,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x45,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x45,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x45,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x45,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, m0
-// CHECK: [0x05,0x00,0x45,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x45,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x45,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, 0
-// CHECK: [0x05,0x00,0x45,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, -1
-// CHECK: [0x05,0x00,0x45,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x45,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x45,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x45,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_i32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_i32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_i32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_u32 v5, v1
-// CHECK: [0x01,0x0d,0x0a,0x7e]
-
-v_cvt_f32_u32 v255, v1
-// CHECK: [0x01,0x0d,0xfe,0x7f]
-
-v_cvt_f32_u32 v5, v255
-// CHECK: [0xff,0x0d,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, s1
-// CHECK: [0x01,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, s101
-// CHECK: [0x65,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, flat_scratch_lo
-// CHECK: [0x66,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, flat_scratch_hi
-// CHECK: [0x67,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, vcc_lo
-// CHECK: [0x6a,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, vcc_hi
-// CHECK: [0x6b,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, m0
-// CHECK: [0x7c,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, exec_lo
-// CHECK: [0x7e,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, exec_hi
-// CHECK: [0x7f,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, 0
-// CHECK: [0x80,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, -1
-// CHECK: [0xc1,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, 0.5
-// CHECK: [0xf0,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, -4.0
-// CHECK: [0xf7,0x0c,0x0a,0x7e]
-
-v_cvt_f32_u32 v5, 0xaf123456
-// CHECK: [0xff,0x0c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_u32 v5, 0x3f717273
-// CHECK: [0xff,0x0c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_u32_e64 v5, v1
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v255, v1
-// CHECK: [0xff,0x00,0x46,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v255
-// CHECK: [0x05,0x00,0x46,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, s1
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, s101
-// CHECK: [0x05,0x00,0x46,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x46,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x46,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x46,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x46,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, m0
-// CHECK: [0x05,0x00,0x46,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x46,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x46,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, 0
-// CHECK: [0x05,0x00,0x46,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, -1
-// CHECK: [0x05,0x00,0x46,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x46,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x46,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x46,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_u32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_u32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_u32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_u32_f32 v5, v1
-// CHECK: [0x01,0x0f,0x0a,0x7e]
-
-v_cvt_u32_f32 v255, v1
-// CHECK: [0x01,0x0f,0xfe,0x7f]
-
-v_cvt_u32_f32 v5, v255
-// CHECK: [0xff,0x0f,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, s1
-// CHECK: [0x01,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, s101
-// CHECK: [0x65,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, m0
-// CHECK: [0x7c,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, exec_lo
-// CHECK: [0x7e,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, exec_hi
-// CHECK: [0x7f,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, 0
-// CHECK: [0x80,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, -1
-// CHECK: [0xc1,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, 0.5
-// CHECK: [0xf0,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, -4.0
-// CHECK: [0xf7,0x0e,0x0a,0x7e]
-
-v_cvt_u32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x0e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_u32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x0e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_u32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x47,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x47,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x47,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x47,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x47,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x47,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x47,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x47,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x47,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x47,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x47,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x47,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x47,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x47,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_u32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x47,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x47,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32 v5, v1
-// CHECK: [0x01,0x11,0x0a,0x7e]
-
-v_cvt_i32_f32 v255, v1
-// CHECK: [0x01,0x11,0xfe,0x7f]
-
-v_cvt_i32_f32 v5, v255
-// CHECK: [0xff,0x11,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, s1
-// CHECK: [0x01,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, s101
-// CHECK: [0x65,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, m0
-// CHECK: [0x7c,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, 0
-// CHECK: [0x80,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, -1
-// CHECK: [0xc1,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x10,0x0a,0x7e]
-
-v_cvt_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x10,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x10,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x48,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x48,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x48,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x48,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x48,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x48,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x48,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x48,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x48,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x48,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x48,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x48,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x48,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x48,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i32_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x48,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32 v5, v1
-// CHECK: [0x01,0x15,0x0a,0x7e]
-
-v_cvt_f16_f32 v255, v1
-// CHECK: [0x01,0x15,0xfe,0x7f]
-
-v_cvt_f16_f32 v5, v255
-// CHECK: [0xff,0x15,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, s1
-// CHECK: [0x01,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, s101
-// CHECK: [0x65,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, vcc_lo
-// CHECK: [0x6a,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, vcc_hi
-// CHECK: [0x6b,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, m0
-// CHECK: [0x7c,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, exec_lo
-// CHECK: [0x7e,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, exec_hi
-// CHECK: [0x7f,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0
-// CHECK: [0x80,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, -1
-// CHECK: [0xc1,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0.5
-// CHECK: [0xf0,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, -4.0
-// CHECK: [0xf7,0x14,0x0a,0x7e]
-
-v_cvt_f16_f32 v5, 0xaf123456
-// CHECK: [0xff,0x14,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f16_f32 v5, 0x3f717273
-// CHECK: [0xff,0x14,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f16_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x4a,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x4a,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4a,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4a,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4a,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x4a,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4a,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x4a,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x4a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4a,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4a,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_f16_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x4a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x4a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f16_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f16_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_f16 v5, v1
-// CHECK: [0x01,0x17,0x0a,0x7e]
-
-v_cvt_f32_f16 v255, v1
-// CHECK: [0x01,0x17,0xfe,0x7f]
-
-v_cvt_f32_f16 v5, v255
-// CHECK: [0xff,0x17,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, s1
-// CHECK: [0x01,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, s101
-// CHECK: [0x65,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, vcc_lo
-// CHECK: [0x6a,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, vcc_hi
-// CHECK: [0x6b,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, m0
-// CHECK: [0x7c,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, exec_lo
-// CHECK: [0x7e,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, exec_hi
-// CHECK: [0x7f,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, 0
-// CHECK: [0x80,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, -1
-// CHECK: [0xc1,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, 0.5
-// CHECK: [0xf0,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, -4.0
-// CHECK: [0xf7,0x16,0x0a,0x7e]
-
-v_cvt_f32_f16 v5, 0xfe0b
-// CHECK: [0xff,0x16,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_f32_f16 v5, 0x3456
-// CHECK: [0xff,0x16,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x4b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x4b,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x4b,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4b,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4b,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x4b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x4b,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x4b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_f32_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x4b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x4b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f16_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_f16_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_f16_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_rpi_i32_f32 v5, v1
-// CHECK: [0x01,0x19,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v255, v1
-// CHECK: [0x01,0x19,0xfe,0x7f]
-
-v_cvt_rpi_i32_f32 v5, v255
-// CHECK: [0xff,0x19,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, s1
-// CHECK: [0x01,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, s101
-// CHECK: [0x65,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, m0
-// CHECK: [0x7c,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0
-// CHECK: [0x80,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, -1
-// CHECK: [0xc1,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x18,0x0a,0x7e]
-
-v_cvt_rpi_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x18,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_rpi_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x18,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_rpi_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x4c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x4c,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x4c,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4c,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4c,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x4c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x4c,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x4c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_rpi_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_rpi_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x4c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32 v5, v1
-// CHECK: [0x01,0x1b,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v255, v1
-// CHECK: [0x01,0x1b,0xfe,0x7f]
-
-v_cvt_flr_i32_f32 v5, v255
-// CHECK: [0xff,0x1b,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, s1
-// CHECK: [0x01,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, s101
-// CHECK: [0x65,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, m0
-// CHECK: [0x7c,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0
-// CHECK: [0x80,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, -1
-// CHECK: [0xc1,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x1a,0x0a,0x7e]
-
-v_cvt_flr_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x1a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_flr_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x1a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_flr_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x4d,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x4d,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x4d,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4d,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4d,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4d,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4d,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x4d,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4d,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4d,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x4d,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x4d,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4d,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4d,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_flr_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_flr_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x4d,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4 v5, v1
-// CHECK: [0x01,0x1d,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v255, v1
-// CHECK: [0x01,0x1d,0xfe,0x7f]
-
-v_cvt_off_f32_i4 v5, v255
-// CHECK: [0xff,0x1d,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, s1
-// CHECK: [0x01,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, s101
-// CHECK: [0x65,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, flat_scratch_lo
-// CHECK: [0x66,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, flat_scratch_hi
-// CHECK: [0x67,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, vcc_lo
-// CHECK: [0x6a,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, vcc_hi
-// CHECK: [0x6b,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, m0
-// CHECK: [0x7c,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, exec_lo
-// CHECK: [0x7e,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, exec_hi
-// CHECK: [0x7f,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0
-// CHECK: [0x80,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, -1
-// CHECK: [0xc1,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0.5
-// CHECK: [0xf0,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, -4.0
-// CHECK: [0xf7,0x1c,0x0a,0x7e]
-
-v_cvt_off_f32_i4 v5, 0x4f
-// CHECK: [0xff,0x1c,0x0a,0x7e,0x4f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4 v5, 0x41
-// CHECK: [0xff,0x1c,0x0a,0x7e,0x41,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v255, v1
-// CHECK: [0xff,0x00,0x4e,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v255
-// CHECK: [0x05,0x00,0x4e,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, s1
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, s101
-// CHECK: [0x05,0x00,0x4e,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x4e,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x4e,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x4e,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x4e,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, m0
-// CHECK: [0x05,0x00,0x4e,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x4e,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x4e,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, 0
-// CHECK: [0x05,0x00,0x4e,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, -1
-// CHECK: [0x05,0x00,0x4e,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4e,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4e,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x4e,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_off_f32_i4_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_off_f32_i4_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_off_f32_i4_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_f64 v5, v[1:2]
-// CHECK: [0x01,0x1f,0x0a,0x7e]
-
-v_cvt_f32_f64 v255, v[1:2]
-// CHECK: [0x01,0x1f,0xfe,0x7f]
-
-v_cvt_f32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x1f,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[2:3]
-// CHECK: [0x02,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[4:5]
-// CHECK: [0x04,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, s[100:101]
-// CHECK: [0x64,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, flat_scratch
-// CHECK: [0x66,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, vcc
-// CHECK: [0x6a,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, exec
-// CHECK: [0x7e,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0
-// CHECK: [0x80,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, -1
-// CHECK: [0xc1,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0.5
-// CHECK: [0xf0,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, -4.0
-// CHECK: [0xf7,0x1e,0x0a,0x7e]
-
-v_cvt_f32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x1e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x1e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x4f,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x4f,0xd1,0xfe,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x02,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x04,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, s[100:101]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x64,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x4f,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x4f,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x4f,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x4f,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x4f,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x4f,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x4f,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_f32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x4f,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[1:2] clamp
-// CHECK: [0x05,0x80,0x4f,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_f64_e64 v5, v[1:2] mul:2
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_f64_e64 v5, v[1:2] mul:4
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_f64_e64 v5, v[1:2] div:2
-// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f64_f32 v[5:6], v1
-// CHECK: [0x01,0x21,0x0a,0x7e]
-
-v_cvt_f64_f32 v[254:255], v1
-// CHECK: [0x01,0x21,0xfc,0x7f]
-
-v_cvt_f64_f32 v[5:6], v255
-// CHECK: [0xff,0x21,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], s1
-// CHECK: [0x01,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], s101
-// CHECK: [0x65,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], flat_scratch_lo
-// CHECK: [0x66,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], flat_scratch_hi
-// CHECK: [0x67,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], vcc_lo
-// CHECK: [0x6a,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], vcc_hi
-// CHECK: [0x6b,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], m0
-// CHECK: [0x7c,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], exec_lo
-// CHECK: [0x7e,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], exec_hi
-// CHECK: [0x7f,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0
-// CHECK: [0x80,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], -1
-// CHECK: [0xc1,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0.5
-// CHECK: [0xf0,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], -4.0
-// CHECK: [0xf7,0x20,0x0a,0x7e]
-
-v_cvt_f64_f32 v[5:6], 0xaf123456
-// CHECK: [0xff,0x20,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_f32 v[5:6], 0x3f717273
-// CHECK: [0xff,0x20,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_f32_e64 v[5:6], v1
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[254:255], v1
-// CHECK: [0xfe,0x00,0x50,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v255
-// CHECK: [0x05,0x00,0x50,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], s1
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], s101
-// CHECK: [0x05,0x00,0x50,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], flat_scratch_lo
-// CHECK: [0x05,0x00,0x50,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], flat_scratch_hi
-// CHECK: [0x05,0x00,0x50,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], vcc_lo
-// CHECK: [0x05,0x00,0x50,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], vcc_hi
-// CHECK: [0x05,0x00,0x50,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], m0
-// CHECK: [0x05,0x00,0x50,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], exec_lo
-// CHECK: [0x05,0x00,0x50,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], exec_hi
-// CHECK: [0x05,0x00,0x50,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x50,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x50,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x50,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x50,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], -v1
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_f64_f32_e64 v[5:6], |v1|
-// CHECK: [0x05,0x01,0x50,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v1 clamp
-// CHECK: [0x05,0x80,0x50,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_f32_e64 v[5:6], v1 mul:2
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_f32_e64 v[5:6], v1 mul:4
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_f32_e64 v[5:6], v1 div:2
-// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte0 v5, v1
-// CHECK: [0x01,0x23,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v255, v1
-// CHECK: [0x01,0x23,0xfe,0x7f]
-
-v_cvt_f32_ubyte0 v5, v255
-// CHECK: [0xff,0x23,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, s1
-// CHECK: [0x01,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, s101
-// CHECK: [0x65,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, flat_scratch_lo
-// CHECK: [0x66,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, flat_scratch_hi
-// CHECK: [0x67,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, vcc_lo
-// CHECK: [0x6a,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, vcc_hi
-// CHECK: [0x6b,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, m0
-// CHECK: [0x7c,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, exec_lo
-// CHECK: [0x7e,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, exec_hi
-// CHECK: [0x7f,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0
-// CHECK: [0x80,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, -1
-// CHECK: [0xc1,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0.5
-// CHECK: [0xf0,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, -4.0
-// CHECK: [0xf7,0x22,0x0a,0x7e]
-
-v_cvt_f32_ubyte0 v5, 0xaf123456
-// CHECK: [0xff,0x22,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte0 v5, 0x3f717273
-// CHECK: [0xff,0x22,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte0_e64 v5, v1
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v255, v1
-// CHECK: [0xff,0x00,0x51,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v255
-// CHECK: [0x05,0x00,0x51,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, s1
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, s101
-// CHECK: [0x05,0x00,0x51,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x51,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x51,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x51,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x51,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, m0
-// CHECK: [0x05,0x00,0x51,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x51,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x51,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, 0
-// CHECK: [0x05,0x00,0x51,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, -1
-// CHECK: [0x05,0x00,0x51,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x51,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x51,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x51,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte0_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte0_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte0_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte1 v5, v1
-// CHECK: [0x01,0x25,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v255, v1
-// CHECK: [0x01,0x25,0xfe,0x7f]
-
-v_cvt_f32_ubyte1 v5, v255
-// CHECK: [0xff,0x25,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, s1
-// CHECK: [0x01,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, s101
-// CHECK: [0x65,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, flat_scratch_lo
-// CHECK: [0x66,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, flat_scratch_hi
-// CHECK: [0x67,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, vcc_lo
-// CHECK: [0x6a,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, vcc_hi
-// CHECK: [0x6b,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, m0
-// CHECK: [0x7c,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, exec_lo
-// CHECK: [0x7e,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, exec_hi
-// CHECK: [0x7f,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0
-// CHECK: [0x80,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, -1
-// CHECK: [0xc1,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0.5
-// CHECK: [0xf0,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, -4.0
-// CHECK: [0xf7,0x24,0x0a,0x7e]
-
-v_cvt_f32_ubyte1 v5, 0xaf123456
-// CHECK: [0xff,0x24,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte1 v5, 0x3f717273
-// CHECK: [0xff,0x24,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte1_e64 v5, v1
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v255, v1
-// CHECK: [0xff,0x00,0x52,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v255
-// CHECK: [0x05,0x00,0x52,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, s1
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, s101
-// CHECK: [0x05,0x00,0x52,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x52,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x52,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x52,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x52,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, m0
-// CHECK: [0x05,0x00,0x52,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x52,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x52,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, 0
-// CHECK: [0x05,0x00,0x52,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, -1
-// CHECK: [0x05,0x00,0x52,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x52,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x52,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x52,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte1_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte1_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte1_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte2 v5, v1
-// CHECK: [0x01,0x27,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v255, v1
-// CHECK: [0x01,0x27,0xfe,0x7f]
-
-v_cvt_f32_ubyte2 v5, v255
-// CHECK: [0xff,0x27,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, s1
-// CHECK: [0x01,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, s101
-// CHECK: [0x65,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, flat_scratch_lo
-// CHECK: [0x66,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, flat_scratch_hi
-// CHECK: [0x67,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, vcc_lo
-// CHECK: [0x6a,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, vcc_hi
-// CHECK: [0x6b,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, m0
-// CHECK: [0x7c,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, exec_lo
-// CHECK: [0x7e,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, exec_hi
-// CHECK: [0x7f,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0
-// CHECK: [0x80,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, -1
-// CHECK: [0xc1,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0.5
-// CHECK: [0xf0,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, -4.0
-// CHECK: [0xf7,0x26,0x0a,0x7e]
-
-v_cvt_f32_ubyte2 v5, 0xaf123456
-// CHECK: [0xff,0x26,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte2 v5, 0x3f717273
-// CHECK: [0xff,0x26,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte2_e64 v5, v1
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v255, v1
-// CHECK: [0xff,0x00,0x53,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v255
-// CHECK: [0x05,0x00,0x53,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, s1
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, s101
-// CHECK: [0x05,0x00,0x53,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x53,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x53,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x53,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x53,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, m0
-// CHECK: [0x05,0x00,0x53,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x53,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x53,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, 0
-// CHECK: [0x05,0x00,0x53,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, -1
-// CHECK: [0x05,0x00,0x53,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x53,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x53,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x53,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte2_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte2_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte2_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_f32_ubyte3 v5, v1
-// CHECK: [0x01,0x29,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v255, v1
-// CHECK: [0x01,0x29,0xfe,0x7f]
-
-v_cvt_f32_ubyte3 v5, v255
-// CHECK: [0xff,0x29,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, s1
-// CHECK: [0x01,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, s101
-// CHECK: [0x65,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, flat_scratch_lo
-// CHECK: [0x66,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, flat_scratch_hi
-// CHECK: [0x67,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, vcc_lo
-// CHECK: [0x6a,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, vcc_hi
-// CHECK: [0x6b,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, m0
-// CHECK: [0x7c,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, exec_lo
-// CHECK: [0x7e,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, exec_hi
-// CHECK: [0x7f,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0
-// CHECK: [0x80,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, -1
-// CHECK: [0xc1,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0.5
-// CHECK: [0xf0,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, -4.0
-// CHECK: [0xf7,0x28,0x0a,0x7e]
-
-v_cvt_f32_ubyte3 v5, 0xaf123456
-// CHECK: [0xff,0x28,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f32_ubyte3 v5, 0x3f717273
-// CHECK: [0xff,0x28,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f32_ubyte3_e64 v5, v1
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v255, v1
-// CHECK: [0xff,0x00,0x54,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v255
-// CHECK: [0x05,0x00,0x54,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, s1
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, s101
-// CHECK: [0x05,0x00,0x54,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x54,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x54,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x54,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x54,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, m0
-// CHECK: [0x05,0x00,0x54,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x54,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x54,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, 0
-// CHECK: [0x05,0x00,0x54,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, -1
-// CHECK: [0x05,0x00,0x54,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x54,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x54,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x54,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f32_ubyte3_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f32_ubyte3_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f32_ubyte3_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x18]
-
-v_cvt_u32_f64 v5, v[1:2]
-// CHECK: [0x01,0x2b,0x0a,0x7e]
-
-v_cvt_u32_f64 v255, v[1:2]
-// CHECK: [0x01,0x2b,0xfe,0x7f]
-
-v_cvt_u32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x2b,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[2:3]
-// CHECK: [0x02,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[4:5]
-// CHECK: [0x04,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, s[100:101]
-// CHECK: [0x64,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, flat_scratch
-// CHECK: [0x66,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, vcc
-// CHECK: [0x6a,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, exec
-// CHECK: [0x7e,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0
-// CHECK: [0x80,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, -1
-// CHECK: [0xc1,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0.5
-// CHECK: [0xf0,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, -4.0
-// CHECK: [0xf7,0x2a,0x0a,0x7e]
-
-v_cvt_u32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x2a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_u32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x2a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_u32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x55,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x55,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x55,0xd1,0xfe,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x55,0xd1,0x02,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x55,0xd1,0x04,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, s[100:101]
-// CHECK: [0x05,0x00,0x55,0xd1,0x64,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x55,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x55,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x55,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x55,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x55,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x55,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x55,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x55,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_u32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x55,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u32_f64_e64 v5, v[1:2] clamp
-// CHECK: [0x05,0x80,0x55,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32 v[5:6], v1
-// CHECK: [0x01,0x2d,0x0a,0x7e]
-
-v_cvt_f64_u32 v[254:255], v1
-// CHECK: [0x01,0x2d,0xfc,0x7f]
-
-v_cvt_f64_u32 v[5:6], v255
-// CHECK: [0xff,0x2d,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], s1
-// CHECK: [0x01,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], s101
-// CHECK: [0x65,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], flat_scratch_lo
-// CHECK: [0x66,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], flat_scratch_hi
-// CHECK: [0x67,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], vcc_lo
-// CHECK: [0x6a,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], vcc_hi
-// CHECK: [0x6b,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], m0
-// CHECK: [0x7c,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], exec_lo
-// CHECK: [0x7e,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], exec_hi
-// CHECK: [0x7f,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0
-// CHECK: [0x80,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], -1
-// CHECK: [0xc1,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0.5
-// CHECK: [0xf0,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], -4.0
-// CHECK: [0xf7,0x2c,0x0a,0x7e]
-
-v_cvt_f64_u32 v[5:6], 0xaf123456
-// CHECK: [0xff,0x2c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cvt_f64_u32 v[5:6], 0x3f717273
-// CHECK: [0xff,0x2c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cvt_f64_u32_e64 v[5:6], v1
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[254:255], v1
-// CHECK: [0xfe,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v255
-// CHECK: [0x05,0x00,0x56,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], s1
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], s101
-// CHECK: [0x05,0x00,0x56,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], flat_scratch_lo
-// CHECK: [0x05,0x00,0x56,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], flat_scratch_hi
-// CHECK: [0x05,0x00,0x56,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], vcc_lo
-// CHECK: [0x05,0x00,0x56,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], vcc_hi
-// CHECK: [0x05,0x00,0x56,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], m0
-// CHECK: [0x05,0x00,0x56,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], exec_lo
-// CHECK: [0x05,0x00,0x56,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], exec_hi
-// CHECK: [0x05,0x00,0x56,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x56,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x56,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x56,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x56,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v1 clamp
-// CHECK: [0x05,0x80,0x56,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f64_u32_e64 v[5:6], v1 mul:2
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x08]
-
-v_cvt_f64_u32_e64 v[5:6], v1 mul:4
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x10]
-
-v_cvt_f64_u32_e64 v[5:6], v1 div:2
-// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x18]
-
-v_trunc_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x2f,0x0a,0x7e]
-
-v_trunc_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x2f,0xfc,0x7f]
-
-v_trunc_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x2f,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], vcc
-// CHECK: [0x6a,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], exec
-// CHECK: [0x7e,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0
-// CHECK: [0x80,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], -1
-// CHECK: [0xc1,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x2e,0x0a,0x7e]
-
-v_trunc_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x2e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_trunc_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x2e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_trunc_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x57,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x57,0xd1,0xfe,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x57,0xd1,0x02,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x57,0xd1,0x04,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x57,0xd1,0x64,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x57,0xd1,0x66,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x57,0xd1,0x6a,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x57,0xd1,0x7e,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x57,0xd1,0x80,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x57,0xd1,0xc1,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x57,0xd1,0xf0,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x57,0xd1,0xf7,0x00,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x20]
-
-v_trunc_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x57,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x57,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x08]
-
-v_trunc_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x10]
-
-v_trunc_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x18]
-
-v_ceil_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x31,0x0a,0x7e]
-
-v_ceil_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x31,0xfc,0x7f]
-
-v_ceil_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x31,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], vcc
-// CHECK: [0x6a,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], exec
-// CHECK: [0x7e,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0
-// CHECK: [0x80,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], -1
-// CHECK: [0xc1,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x30,0x0a,0x7e]
-
-v_ceil_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x30,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ceil_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x30,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ceil_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x58,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x58,0xd1,0xfe,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x58,0xd1,0x02,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x58,0xd1,0x04,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x58,0xd1,0x64,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x58,0xd1,0x66,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x58,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x58,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x58,0xd1,0x80,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x58,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x58,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x58,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x20]
-
-v_ceil_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x58,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x58,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x08]
-
-v_ceil_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x10]
-
-v_ceil_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x18]
-
-v_rndne_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x33,0x0a,0x7e]
-
-v_rndne_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x33,0xfc,0x7f]
-
-v_rndne_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x33,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], vcc
-// CHECK: [0x6a,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], exec
-// CHECK: [0x7e,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0
-// CHECK: [0x80,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], -1
-// CHECK: [0xc1,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x32,0x0a,0x7e]
-
-v_rndne_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x32,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rndne_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x32,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rndne_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x59,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x59,0xd1,0xfe,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x59,0xd1,0x02,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x59,0xd1,0x04,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x59,0xd1,0x64,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x59,0xd1,0x66,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x59,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x59,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x59,0xd1,0x80,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x59,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x59,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x59,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x20]
-
-v_rndne_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x59,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x08]
-
-v_rndne_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x10]
-
-v_rndne_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x18]
-
-v_floor_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x35,0x0a,0x7e]
-
-v_floor_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x35,0xfc,0x7f]
-
-v_floor_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x35,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], vcc
-// CHECK: [0x6a,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], exec
-// CHECK: [0x7e,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0
-// CHECK: [0x80,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], -1
-// CHECK: [0xc1,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x34,0x0a,0x7e]
-
-v_floor_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x34,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_floor_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x34,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_floor_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x5a,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x5a,0xd1,0xfe,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x02,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x04,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x64,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x5a,0xd1,0x66,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x5a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x5a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x5a,0xd1,0x80,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x5a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x5a,0xd1,0xf0,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x5a,0xd1,0xf7,0x00,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x20]
-
-v_floor_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x5a,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x08]
-
-v_floor_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x10]
-
-v_floor_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x18]
-
-v_fract_f32 v5, v1
-// CHECK: [0x01,0x37,0x0a,0x7e]
-
-v_fract_f32 v255, v1
-// CHECK: [0x01,0x37,0xfe,0x7f]
-
-v_fract_f32 v5, v255
-// CHECK: [0xff,0x37,0x0a,0x7e]
-
-v_fract_f32 v5, s1
-// CHECK: [0x01,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, s101
-// CHECK: [0x65,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, vcc_lo
-// CHECK: [0x6a,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, vcc_hi
-// CHECK: [0x6b,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, m0
-// CHECK: [0x7c,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, exec_lo
-// CHECK: [0x7e,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, exec_hi
-// CHECK: [0x7f,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, 0
-// CHECK: [0x80,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, -1
-// CHECK: [0xc1,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, 0.5
-// CHECK: [0xf0,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, -4.0
-// CHECK: [0xf7,0x36,0x0a,0x7e]
-
-v_fract_f32 v5, 0xaf123456
-// CHECK: [0xff,0x36,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_fract_f32 v5, 0x3f717273
-// CHECK: [0xff,0x36,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_fract_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5b,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5b,0xd1,0xff,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5b,0xd1,0x65,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5b,0xd1,0x66,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5b,0xd1,0x67,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5b,0xd1,0x80,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_fract_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x20]
-
-v_fract_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5b,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x08]
-
-v_fract_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x10]
-
-v_fract_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x18]
-
-v_trunc_f32 v5, v1
-// CHECK: [0x01,0x39,0x0a,0x7e]
-
-v_trunc_f32 v255, v1
-// CHECK: [0x01,0x39,0xfe,0x7f]
-
-v_trunc_f32 v5, v255
-// CHECK: [0xff,0x39,0x0a,0x7e]
-
-v_trunc_f32 v5, s1
-// CHECK: [0x01,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, s101
-// CHECK: [0x65,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, vcc_lo
-// CHECK: [0x6a,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, vcc_hi
-// CHECK: [0x6b,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, m0
-// CHECK: [0x7c,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, exec_lo
-// CHECK: [0x7e,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, exec_hi
-// CHECK: [0x7f,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, 0
-// CHECK: [0x80,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, -1
-// CHECK: [0xc1,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, 0.5
-// CHECK: [0xf0,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, -4.0
-// CHECK: [0xf7,0x38,0x0a,0x7e]
-
-v_trunc_f32 v5, 0xaf123456
-// CHECK: [0xff,0x38,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_trunc_f32 v5, 0x3f717273
-// CHECK: [0xff,0x38,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_trunc_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5c,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5c,0xd1,0xff,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5c,0xd1,0x65,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5c,0xd1,0x66,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5c,0xd1,0x67,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5c,0xd1,0x80,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_trunc_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x20]
-
-v_trunc_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5c,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x08]
-
-v_trunc_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x10]
-
-v_trunc_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x18]
-
-v_ceil_f32 v5, v1
-// CHECK: [0x01,0x3b,0x0a,0x7e]
-
-v_ceil_f32 v255, v1
-// CHECK: [0x01,0x3b,0xfe,0x7f]
-
-v_ceil_f32 v5, v255
-// CHECK: [0xff,0x3b,0x0a,0x7e]
-
-v_ceil_f32 v5, s1
-// CHECK: [0x01,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, s101
-// CHECK: [0x65,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, vcc_lo
-// CHECK: [0x6a,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, vcc_hi
-// CHECK: [0x6b,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, m0
-// CHECK: [0x7c,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, exec_lo
-// CHECK: [0x7e,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, exec_hi
-// CHECK: [0x7f,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, 0
-// CHECK: [0x80,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, -1
-// CHECK: [0xc1,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, 0.5
-// CHECK: [0xf0,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, -4.0
-// CHECK: [0xf7,0x3a,0x0a,0x7e]
-
-v_ceil_f32 v5, 0xaf123456
-// CHECK: [0xff,0x3a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ceil_f32 v5, 0x3f717273
-// CHECK: [0xff,0x3a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ceil_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5d,0xd1,0xff,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5d,0xd1,0x65,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5d,0xd1,0x66,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5d,0xd1,0x67,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5d,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5d,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5d,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5d,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5d,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5d,0xd1,0x80,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5d,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5d,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ceil_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x20]
-
-v_ceil_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x08]
-
-v_ceil_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x10]
-
-v_ceil_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x18]
-
-v_rndne_f32 v5, v1
-// CHECK: [0x01,0x3d,0x0a,0x7e]
-
-v_rndne_f32 v255, v1
-// CHECK: [0x01,0x3d,0xfe,0x7f]
-
-v_rndne_f32 v5, v255
-// CHECK: [0xff,0x3d,0x0a,0x7e]
-
-v_rndne_f32 v5, s1
-// CHECK: [0x01,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, s101
-// CHECK: [0x65,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, vcc_lo
-// CHECK: [0x6a,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, vcc_hi
-// CHECK: [0x6b,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, m0
-// CHECK: [0x7c,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, exec_lo
-// CHECK: [0x7e,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, exec_hi
-// CHECK: [0x7f,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, 0
-// CHECK: [0x80,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, -1
-// CHECK: [0xc1,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, 0.5
-// CHECK: [0xf0,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, -4.0
-// CHECK: [0xf7,0x3c,0x0a,0x7e]
-
-v_rndne_f32 v5, 0xaf123456
-// CHECK: [0xff,0x3c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rndne_f32 v5, 0x3f717273
-// CHECK: [0xff,0x3c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rndne_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5e,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5e,0xd1,0xff,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5e,0xd1,0x65,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5e,0xd1,0x66,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5e,0xd1,0x67,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5e,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5e,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5e,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5e,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5e,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5e,0xd1,0x80,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5e,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5e,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5e,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rndne_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x20]
-
-v_rndne_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5e,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x08]
-
-v_rndne_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x10]
-
-v_rndne_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x18]
-
-v_floor_f32 v5, v1
-// CHECK: [0x01,0x3f,0x0a,0x7e]
-
-v_floor_f32 v255, v1
-// CHECK: [0x01,0x3f,0xfe,0x7f]
-
-v_floor_f32 v5, v255
-// CHECK: [0xff,0x3f,0x0a,0x7e]
-
-v_floor_f32 v5, s1
-// CHECK: [0x01,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, s101
-// CHECK: [0x65,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, vcc_lo
-// CHECK: [0x6a,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, vcc_hi
-// CHECK: [0x6b,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, m0
-// CHECK: [0x7c,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, exec_lo
-// CHECK: [0x7e,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, exec_hi
-// CHECK: [0x7f,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, 0
-// CHECK: [0x80,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, -1
-// CHECK: [0xc1,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, 0.5
-// CHECK: [0xf0,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, -4.0
-// CHECK: [0xf7,0x3e,0x0a,0x7e]
-
-v_floor_f32 v5, 0xaf123456
-// CHECK: [0xff,0x3e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_floor_f32 v5, 0x3f717273
-// CHECK: [0xff,0x3e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_floor_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x5f,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x5f,0xd1,0xff,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x5f,0xd1,0x65,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x5f,0xd1,0x66,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x5f,0xd1,0x67,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x5f,0xd1,0x6a,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x5f,0xd1,0x6b,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x5f,0xd1,0x7c,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x5f,0xd1,0x7e,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x5f,0xd1,0x7f,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x5f,0xd1,0x80,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x5f,0xd1,0xc1,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x5f,0xd1,0xf0,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x5f,0xd1,0xf7,0x00,0x00,0x00]
-
-v_floor_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x20]
-
-v_floor_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x5f,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x5f,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x08]
-
-v_floor_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x10]
-
-v_floor_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x18]
-
-v_exp_f32 v5, v1
-// CHECK: [0x01,0x41,0x0a,0x7e]
-
-v_exp_f32 v255, v1
-// CHECK: [0x01,0x41,0xfe,0x7f]
-
-v_exp_f32 v5, v255
-// CHECK: [0xff,0x41,0x0a,0x7e]
-
-v_exp_f32 v5, s1
-// CHECK: [0x01,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, s101
-// CHECK: [0x65,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, vcc_lo
-// CHECK: [0x6a,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, vcc_hi
-// CHECK: [0x6b,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, m0
-// CHECK: [0x7c,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, exec_lo
-// CHECK: [0x7e,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, exec_hi
-// CHECK: [0x7f,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, 0
-// CHECK: [0x80,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, -1
-// CHECK: [0xc1,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, 0.5
-// CHECK: [0xf0,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, -4.0
-// CHECK: [0xf7,0x40,0x0a,0x7e]
-
-v_exp_f32 v5, 0xaf123456
-// CHECK: [0xff,0x40,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_exp_f32 v5, 0x3f717273
-// CHECK: [0xff,0x40,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_exp_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x60,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x60,0xd1,0xff,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x60,0xd1,0x65,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x60,0xd1,0x66,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x60,0xd1,0x67,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x60,0xd1,0x6a,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x60,0xd1,0x6b,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x60,0xd1,0x7c,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x60,0xd1,0x7e,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x60,0xd1,0x7f,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x60,0xd1,0x80,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x60,0xd1,0xc1,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x60,0xd1,0xf0,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x60,0xd1,0xf7,0x00,0x00,0x00]
-
-v_exp_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x20]
-
-v_exp_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x60,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x60,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x08]
-
-v_exp_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x10]
-
-v_exp_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x18]
-
-v_log_f32 v5, v1
-// CHECK: [0x01,0x43,0x0a,0x7e]
-
-v_log_f32 v255, v1
-// CHECK: [0x01,0x43,0xfe,0x7f]
-
-v_log_f32 v5, v255
-// CHECK: [0xff,0x43,0x0a,0x7e]
-
-v_log_f32 v5, s1
-// CHECK: [0x01,0x42,0x0a,0x7e]
-
-v_log_f32 v5, s101
-// CHECK: [0x65,0x42,0x0a,0x7e]
-
-v_log_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x42,0x0a,0x7e]
-
-v_log_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x42,0x0a,0x7e]
-
-v_log_f32 v5, vcc_lo
-// CHECK: [0x6a,0x42,0x0a,0x7e]
-
-v_log_f32 v5, vcc_hi
-// CHECK: [0x6b,0x42,0x0a,0x7e]
-
-v_log_f32 v5, m0
-// CHECK: [0x7c,0x42,0x0a,0x7e]
-
-v_log_f32 v5, exec_lo
-// CHECK: [0x7e,0x42,0x0a,0x7e]
-
-v_log_f32 v5, exec_hi
-// CHECK: [0x7f,0x42,0x0a,0x7e]
-
-v_log_f32 v5, 0
-// CHECK: [0x80,0x42,0x0a,0x7e]
-
-v_log_f32 v5, -1
-// CHECK: [0xc1,0x42,0x0a,0x7e]
-
-v_log_f32 v5, 0.5
-// CHECK: [0xf0,0x42,0x0a,0x7e]
-
-v_log_f32 v5, -4.0
-// CHECK: [0xf7,0x42,0x0a,0x7e]
-
-v_log_f32 v5, 0xaf123456
-// CHECK: [0xff,0x42,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_log_f32 v5, 0x3f717273
-// CHECK: [0xff,0x42,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_log_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x61,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x61,0xd1,0xff,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x61,0xd1,0x65,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x61,0xd1,0x66,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x61,0xd1,0x67,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x61,0xd1,0x6a,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x61,0xd1,0x6b,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x61,0xd1,0x7c,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x61,0xd1,0x7e,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x61,0xd1,0x7f,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x61,0xd1,0x80,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x61,0xd1,0xc1,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x61,0xd1,0xf0,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x61,0xd1,0xf7,0x00,0x00,0x00]
-
-v_log_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x20]
-
-v_log_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x61,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x61,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x08]
-
-v_log_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x10]
-
-v_log_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x18]
-
-v_rcp_f32 v5, v1
-// CHECK: [0x01,0x45,0x0a,0x7e]
-
-v_rcp_f32 v255, v1
-// CHECK: [0x01,0x45,0xfe,0x7f]
-
-v_rcp_f32 v5, v255
-// CHECK: [0xff,0x45,0x0a,0x7e]
-
-v_rcp_f32 v5, s1
-// CHECK: [0x01,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, s101
-// CHECK: [0x65,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, vcc_lo
-// CHECK: [0x6a,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, vcc_hi
-// CHECK: [0x6b,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, m0
-// CHECK: [0x7c,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, exec_lo
-// CHECK: [0x7e,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, exec_hi
-// CHECK: [0x7f,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, 0
-// CHECK: [0x80,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, -1
-// CHECK: [0xc1,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, 0.5
-// CHECK: [0xf0,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, -4.0
-// CHECK: [0xf7,0x44,0x0a,0x7e]
-
-v_rcp_f32 v5, 0xaf123456
-// CHECK: [0xff,0x44,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_f32 v5, 0x3f717273
-// CHECK: [0xff,0x44,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x62,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x62,0xd1,0xff,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x62,0xd1,0x65,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x62,0xd1,0x66,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x62,0xd1,0x67,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x62,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x62,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x62,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x62,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x62,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x62,0xd1,0x80,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x62,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x62,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x62,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rcp_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x20]
-
-v_rcp_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x62,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x62,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x08]
-
-v_rcp_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x10]
-
-v_rcp_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x18]
-
-v_rcp_iflag_f32 v5, v1
-// CHECK: [0x01,0x47,0x0a,0x7e]
-
-v_rcp_iflag_f32 v255, v1
-// CHECK: [0x01,0x47,0xfe,0x7f]
-
-v_rcp_iflag_f32 v5, v255
-// CHECK: [0xff,0x47,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, s1
-// CHECK: [0x01,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, s101
-// CHECK: [0x65,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, vcc_lo
-// CHECK: [0x6a,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, vcc_hi
-// CHECK: [0x6b,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, m0
-// CHECK: [0x7c,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, exec_lo
-// CHECK: [0x7e,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, exec_hi
-// CHECK: [0x7f,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0
-// CHECK: [0x80,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, -1
-// CHECK: [0xc1,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0.5
-// CHECK: [0xf0,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, -4.0
-// CHECK: [0xf7,0x46,0x0a,0x7e]
-
-v_rcp_iflag_f32 v5, 0xaf123456
-// CHECK: [0xff,0x46,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_iflag_f32 v5, 0x3f717273
-// CHECK: [0xff,0x46,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_iflag_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x63,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x63,0xd1,0xff,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x63,0xd1,0x65,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x63,0xd1,0x66,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x63,0xd1,0x67,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x63,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x63,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x63,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x63,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x63,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x63,0xd1,0x80,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x63,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x63,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x63,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x20]
-
-v_rcp_iflag_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x63,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x63,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_iflag_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x08]
-
-v_rcp_iflag_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x10]
-
-v_rcp_iflag_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x18]
-
-v_rsq_f32 v5, v1
-// CHECK: [0x01,0x49,0x0a,0x7e]
-
-v_rsq_f32 v255, v1
-// CHECK: [0x01,0x49,0xfe,0x7f]
-
-v_rsq_f32 v5, v255
-// CHECK: [0xff,0x49,0x0a,0x7e]
-
-v_rsq_f32 v5, s1
-// CHECK: [0x01,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, s101
-// CHECK: [0x65,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, vcc_lo
-// CHECK: [0x6a,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, vcc_hi
-// CHECK: [0x6b,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, m0
-// CHECK: [0x7c,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, exec_lo
-// CHECK: [0x7e,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, exec_hi
-// CHECK: [0x7f,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, 0
-// CHECK: [0x80,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, -1
-// CHECK: [0xc1,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, 0.5
-// CHECK: [0xf0,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, -4.0
-// CHECK: [0xf7,0x48,0x0a,0x7e]
-
-v_rsq_f32 v5, 0xaf123456
-// CHECK: [0xff,0x48,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_f32 v5, 0x3f717273
-// CHECK: [0xff,0x48,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x64,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x64,0xd1,0xff,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x64,0xd1,0x65,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x64,0xd1,0x66,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x64,0xd1,0x67,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x64,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x64,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x64,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x64,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x64,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x64,0xd1,0x80,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x64,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x64,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x64,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rsq_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x20]
-
-v_rsq_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x64,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x64,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x08]
-
-v_rsq_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x10]
-
-v_rsq_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x18]
-
-v_rcp_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x4b,0x0a,0x7e]
-
-v_rcp_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x4b,0xfc,0x7f]
-
-v_rcp_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x4b,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], vcc
-// CHECK: [0x6a,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], exec
-// CHECK: [0x7e,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0
-// CHECK: [0x80,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], -1
-// CHECK: [0xc1,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x4a,0x0a,0x7e]
-
-v_rcp_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x4a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rcp_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x4a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rcp_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x65,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x65,0xd1,0xfe,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x65,0xd1,0x02,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x65,0xd1,0x04,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x65,0xd1,0x64,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x65,0xd1,0x66,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x65,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x65,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x65,0xd1,0x80,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x65,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x65,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x65,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x20]
-
-v_rcp_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x65,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x65,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x08]
-
-v_rcp_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x10]
-
-v_rcp_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x18]
-
-v_rsq_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x4d,0x0a,0x7e]
-
-v_rsq_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x4d,0xfc,0x7f]
-
-v_rsq_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x4d,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], vcc
-// CHECK: [0x6a,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], exec
-// CHECK: [0x7e,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0
-// CHECK: [0x80,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], -1
-// CHECK: [0xc1,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x4c,0x0a,0x7e]
-
-v_rsq_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x4c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_rsq_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x4c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_rsq_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x66,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x66,0xd1,0xfe,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x66,0xd1,0x02,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x66,0xd1,0x04,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x66,0xd1,0x64,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x66,0xd1,0x66,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x66,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x66,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x66,0xd1,0x80,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x66,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x66,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x66,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x20]
-
-v_rsq_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x66,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x66,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x08]
-
-v_rsq_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x10]
-
-v_rsq_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x18]
-
-v_sqrt_f32 v5, v1
-// CHECK: [0x01,0x4f,0x0a,0x7e]
-
-v_sqrt_f32 v255, v1
-// CHECK: [0x01,0x4f,0xfe,0x7f]
-
-v_sqrt_f32 v5, v255
-// CHECK: [0xff,0x4f,0x0a,0x7e]
-
-v_sqrt_f32 v5, s1
-// CHECK: [0x01,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, s101
-// CHECK: [0x65,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, vcc_lo
-// CHECK: [0x6a,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, vcc_hi
-// CHECK: [0x6b,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, m0
-// CHECK: [0x7c,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, exec_lo
-// CHECK: [0x7e,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, exec_hi
-// CHECK: [0x7f,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0
-// CHECK: [0x80,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, -1
-// CHECK: [0xc1,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0.5
-// CHECK: [0xf0,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, -4.0
-// CHECK: [0xf7,0x4e,0x0a,0x7e]
-
-v_sqrt_f32 v5, 0xaf123456
-// CHECK: [0xff,0x4e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sqrt_f32 v5, 0x3f717273
-// CHECK: [0xff,0x4e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sqrt_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x67,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x67,0xd1,0xff,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x67,0xd1,0x65,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x67,0xd1,0x66,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x67,0xd1,0x67,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x67,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x67,0xd1,0x6b,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x67,0xd1,0x7c,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x67,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x67,0xd1,0x7f,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x67,0xd1,0x80,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x67,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x67,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x67,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x20]
-
-v_sqrt_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x67,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x67,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x08]
-
-v_sqrt_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x10]
-
-v_sqrt_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x18]
-
-v_sqrt_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x51,0x0a,0x7e]
-
-v_sqrt_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x51,0xfc,0x7f]
-
-v_sqrt_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x51,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], vcc
-// CHECK: [0x6a,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], exec
-// CHECK: [0x7e,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0
-// CHECK: [0x80,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], -1
-// CHECK: [0xc1,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x50,0x0a,0x7e]
-
-v_sqrt_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x50,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sqrt_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x50,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sqrt_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x68,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x68,0xd1,0xfe,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x68,0xd1,0x02,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x68,0xd1,0x04,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x68,0xd1,0x64,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x68,0xd1,0x66,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x68,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x68,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x68,0xd1,0x80,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x68,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x68,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x68,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x20]
-
-v_sqrt_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x68,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x68,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x08]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x10]
-
-v_sqrt_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x18]
-
-v_sin_f32 v5, v1
-// CHECK: [0x01,0x53,0x0a,0x7e]
-
-v_sin_f32 v255, v1
-// CHECK: [0x01,0x53,0xfe,0x7f]
-
-v_sin_f32 v5, v255
-// CHECK: [0xff,0x53,0x0a,0x7e]
-
-v_sin_f32 v5, s1
-// CHECK: [0x01,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, s101
-// CHECK: [0x65,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, vcc_lo
-// CHECK: [0x6a,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, vcc_hi
-// CHECK: [0x6b,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, m0
-// CHECK: [0x7c,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, exec_lo
-// CHECK: [0x7e,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, exec_hi
-// CHECK: [0x7f,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, 0
-// CHECK: [0x80,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, -1
-// CHECK: [0xc1,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, 0.5
-// CHECK: [0xf0,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, -4.0
-// CHECK: [0xf7,0x52,0x0a,0x7e]
-
-v_sin_f32 v5, 0xaf123456
-// CHECK: [0xff,0x52,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_sin_f32 v5, 0x3f717273
-// CHECK: [0xff,0x52,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_sin_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x69,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x69,0xd1,0xff,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x69,0xd1,0x65,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x69,0xd1,0x66,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x69,0xd1,0x67,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x69,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x69,0xd1,0x6b,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x69,0xd1,0x7c,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x69,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x69,0xd1,0x7f,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x69,0xd1,0x80,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x69,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x69,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x69,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sin_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x20]
-
-v_sin_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x69,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x69,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x08]
-
-v_sin_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x10]
-
-v_sin_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x18]
-
-v_cos_f32 v5, v1
-// CHECK: [0x01,0x55,0x0a,0x7e]
-
-v_cos_f32 v255, v1
-// CHECK: [0x01,0x55,0xfe,0x7f]
-
-v_cos_f32 v5, v255
-// CHECK: [0xff,0x55,0x0a,0x7e]
-
-v_cos_f32 v5, s1
-// CHECK: [0x01,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, s101
-// CHECK: [0x65,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, vcc_lo
-// CHECK: [0x6a,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, vcc_hi
-// CHECK: [0x6b,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, m0
-// CHECK: [0x7c,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, exec_lo
-// CHECK: [0x7e,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, exec_hi
-// CHECK: [0x7f,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, 0
-// CHECK: [0x80,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, -1
-// CHECK: [0xc1,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, 0.5
-// CHECK: [0xf0,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, -4.0
-// CHECK: [0xf7,0x54,0x0a,0x7e]
-
-v_cos_f32 v5, 0xaf123456
-// CHECK: [0xff,0x54,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_cos_f32 v5, 0x3f717273
-// CHECK: [0xff,0x54,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_cos_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6a,0xd1,0xff,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6a,0xd1,0x65,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6a,0xd1,0x66,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6a,0xd1,0x67,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6a,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6a,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6a,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6a,0xd1,0x80,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6a,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6a,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cos_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x20]
-
-v_cos_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x6a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x6a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x08]
-
-v_cos_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x10]
-
-v_cos_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x18]
-
-v_not_b32 v5, v1
-// CHECK: [0x01,0x57,0x0a,0x7e]
-
-v_not_b32 v255, v1
-// CHECK: [0x01,0x57,0xfe,0x7f]
-
-v_not_b32 v5, v255
-// CHECK: [0xff,0x57,0x0a,0x7e]
-
-v_not_b32 v5, s1
-// CHECK: [0x01,0x56,0x0a,0x7e]
-
-v_not_b32 v5, s101
-// CHECK: [0x65,0x56,0x0a,0x7e]
-
-v_not_b32 v5, flat_scratch_lo
-// CHECK: [0x66,0x56,0x0a,0x7e]
-
-v_not_b32 v5, flat_scratch_hi
-// CHECK: [0x67,0x56,0x0a,0x7e]
-
-v_not_b32 v5, vcc_lo
-// CHECK: [0x6a,0x56,0x0a,0x7e]
-
-v_not_b32 v5, vcc_hi
-// CHECK: [0x6b,0x56,0x0a,0x7e]
-
-v_not_b32 v5, m0
-// CHECK: [0x7c,0x56,0x0a,0x7e]
-
-v_not_b32 v5, exec_lo
-// CHECK: [0x7e,0x56,0x0a,0x7e]
-
-v_not_b32 v5, exec_hi
-// CHECK: [0x7f,0x56,0x0a,0x7e]
-
-v_not_b32 v5, 0
-// CHECK: [0x80,0x56,0x0a,0x7e]
-
-v_not_b32 v5, -1
-// CHECK: [0xc1,0x56,0x0a,0x7e]
-
-v_not_b32 v5, 0.5
-// CHECK: [0xf0,0x56,0x0a,0x7e]
-
-v_not_b32 v5, -4.0
-// CHECK: [0xf7,0x56,0x0a,0x7e]
-
-v_not_b32 v5, 0xaf123456
-// CHECK: [0xff,0x56,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_not_b32 v5, 0x3f717273
-// CHECK: [0xff,0x56,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_not_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
-
-v_not_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
-
-v_not_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6b,0xd1,0xff,0x01,0x00,0x00]
-
-v_not_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6b,0xd1,0x01,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6b,0xd1,0x65,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6b,0xd1,0x66,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6b,0xd1,0x67,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6b,0xd1,0x80,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_not_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_bfrev_b32 v5, v1
-// CHECK: [0x01,0x59,0x0a,0x7e]
-
-v_bfrev_b32 v255, v1
-// CHECK: [0x01,0x59,0xfe,0x7f]
-
-v_bfrev_b32 v5, v255
-// CHECK: [0xff,0x59,0x0a,0x7e]
-
-v_bfrev_b32 v5, s1
-// CHECK: [0x01,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, s101
-// CHECK: [0x65,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, flat_scratch_lo
-// CHECK: [0x66,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, flat_scratch_hi
-// CHECK: [0x67,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, vcc_lo
-// CHECK: [0x6a,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, vcc_hi
-// CHECK: [0x6b,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, m0
-// CHECK: [0x7c,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, exec_lo
-// CHECK: [0x7e,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, exec_hi
-// CHECK: [0x7f,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0
-// CHECK: [0x80,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, -1
-// CHECK: [0xc1,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0.5
-// CHECK: [0xf0,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, -4.0
-// CHECK: [0xf7,0x58,0x0a,0x7e]
-
-v_bfrev_b32 v5, 0xaf123456
-// CHECK: [0xff,0x58,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_bfrev_b32 v5, 0x3f717273
-// CHECK: [0xff,0x58,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_bfrev_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6c,0xd1,0x01,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6c,0xd1,0x01,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6c,0xd1,0xff,0x01,0x00,0x00]
-
-v_bfrev_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6c,0xd1,0x01,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6c,0xd1,0x65,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6c,0xd1,0x66,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6c,0xd1,0x67,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6c,0xd1,0x80,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_bfrev_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ffbh_u32 v5, v1
-// CHECK: [0x01,0x5b,0x0a,0x7e]
-
-v_ffbh_u32 v255, v1
-// CHECK: [0x01,0x5b,0xfe,0x7f]
-
-v_ffbh_u32 v5, v255
-// CHECK: [0xff,0x5b,0x0a,0x7e]
-
-v_ffbh_u32 v5, s1
-// CHECK: [0x01,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, s101
-// CHECK: [0x65,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, flat_scratch_lo
-// CHECK: [0x66,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, flat_scratch_hi
-// CHECK: [0x67,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, vcc_lo
-// CHECK: [0x6a,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, vcc_hi
-// CHECK: [0x6b,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, m0
-// CHECK: [0x7c,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, exec_lo
-// CHECK: [0x7e,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, exec_hi
-// CHECK: [0x7f,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0
-// CHECK: [0x80,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, -1
-// CHECK: [0xc1,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0.5
-// CHECK: [0xf0,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, -4.0
-// CHECK: [0xf7,0x5a,0x0a,0x7e]
-
-v_ffbh_u32 v5, 0xaf123456
-// CHECK: [0xff,0x5a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbh_u32 v5, 0x3f717273
-// CHECK: [0xff,0x5a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbh_u32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6d,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6d,0xd1,0xff,0x01,0x00,0x00]
-
-v_ffbh_u32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6d,0xd1,0x01,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6d,0xd1,0x65,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6d,0xd1,0x66,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6d,0xd1,0x67,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6d,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6d,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6d,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6d,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6d,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6d,0xd1,0x80,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6d,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6d,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ffbh_u32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6d,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ffbl_b32 v5, v1
-// CHECK: [0x01,0x5d,0x0a,0x7e]
-
-v_ffbl_b32 v255, v1
-// CHECK: [0x01,0x5d,0xfe,0x7f]
-
-v_ffbl_b32 v5, v255
-// CHECK: [0xff,0x5d,0x0a,0x7e]
-
-v_ffbl_b32 v5, s1
-// CHECK: [0x01,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, s101
-// CHECK: [0x65,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, flat_scratch_lo
-// CHECK: [0x66,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, flat_scratch_hi
-// CHECK: [0x67,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, vcc_lo
-// CHECK: [0x6a,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, vcc_hi
-// CHECK: [0x6b,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, m0
-// CHECK: [0x7c,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, exec_lo
-// CHECK: [0x7e,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, exec_hi
-// CHECK: [0x7f,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0
-// CHECK: [0x80,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, -1
-// CHECK: [0xc1,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0.5
-// CHECK: [0xf0,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, -4.0
-// CHECK: [0xf7,0x5c,0x0a,0x7e]
-
-v_ffbl_b32 v5, 0xaf123456
-// CHECK: [0xff,0x5c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbl_b32 v5, 0x3f717273
-// CHECK: [0xff,0x5c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbl_b32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6e,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6e,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6e,0xd1,0xff,0x01,0x00,0x00]
-
-v_ffbl_b32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6e,0xd1,0x01,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6e,0xd1,0x65,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6e,0xd1,0x66,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6e,0xd1,0x67,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6e,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6e,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6e,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6e,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6e,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6e,0xd1,0x80,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6e,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6e,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ffbl_b32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6e,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ffbh_i32 v5, v1
-// CHECK: [0x01,0x5f,0x0a,0x7e]
-
-v_ffbh_i32 v255, v1
-// CHECK: [0x01,0x5f,0xfe,0x7f]
-
-v_ffbh_i32 v5, v255
-// CHECK: [0xff,0x5f,0x0a,0x7e]
-
-v_ffbh_i32 v5, s1
-// CHECK: [0x01,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, s101
-// CHECK: [0x65,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, flat_scratch_lo
-// CHECK: [0x66,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, flat_scratch_hi
-// CHECK: [0x67,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, vcc_lo
-// CHECK: [0x6a,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, vcc_hi
-// CHECK: [0x6b,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, m0
-// CHECK: [0x7c,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, exec_lo
-// CHECK: [0x7e,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, exec_hi
-// CHECK: [0x7f,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0
-// CHECK: [0x80,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, -1
-// CHECK: [0xc1,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0.5
-// CHECK: [0xf0,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, -4.0
-// CHECK: [0xf7,0x5e,0x0a,0x7e]
-
-v_ffbh_i32 v5, 0xaf123456
-// CHECK: [0xff,0x5e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_ffbh_i32 v5, 0x3f717273
-// CHECK: [0xff,0x5e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_ffbh_i32_e64 v5, v1
-// CHECK: [0x05,0x00,0x6f,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v255, v1
-// CHECK: [0xff,0x00,0x6f,0xd1,0x01,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v5, v255
-// CHECK: [0x05,0x00,0x6f,0xd1,0xff,0x01,0x00,0x00]
-
-v_ffbh_i32_e64 v5, s1
-// CHECK: [0x05,0x00,0x6f,0xd1,0x01,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, s101
-// CHECK: [0x05,0x00,0x6f,0xd1,0x65,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x6f,0xd1,0x66,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x6f,0xd1,0x67,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x6f,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x6f,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, m0
-// CHECK: [0x05,0x00,0x6f,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x6f,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x6f,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, 0
-// CHECK: [0x05,0x00,0x6f,0xd1,0x80,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, -1
-// CHECK: [0x05,0x00,0x6f,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x6f,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ffbh_i32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x6f,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64 v5, v[1:2]
-// CHECK: [0x01,0x61,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v255, v[1:2]
-// CHECK: [0x01,0x61,0xfe,0x7f]
-
-v_frexp_exp_i32_f64 v5, v[254:255]
-// CHECK: [0xfe,0x61,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[2:3]
-// CHECK: [0x02,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[4:5]
-// CHECK: [0x04,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, s[100:101]
-// CHECK: [0x64,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, flat_scratch
-// CHECK: [0x66,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, vcc
-// CHECK: [0x6a,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, exec
-// CHECK: [0x7e,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0
-// CHECK: [0x80,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, -1
-// CHECK: [0xc1,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0.5
-// CHECK: [0xf0,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, -4.0
-// CHECK: [0xf7,0x60,0x0a,0x7e]
-
-v_frexp_exp_i32_f64 v5, 0xaf123456
-// CHECK: [0xff,0x60,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_exp_i32_f64 v5, 0x3f717273
-// CHECK: [0xff,0x60,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_exp_i32_f64_e64 v5, v[1:2]
-// CHECK: [0x05,0x00,0x70,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v255, v[1:2]
-// CHECK: [0xff,0x00,0x70,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, v[254:255]
-// CHECK: [0x05,0x00,0x70,0xd1,0xfe,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[2:3]
-// CHECK: [0x05,0x00,0x70,0xd1,0x02,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[4:5]
-// CHECK: [0x05,0x00,0x70,0xd1,0x04,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, s[100:101]
-// CHECK: [0x05,0x00,0x70,0xd1,0x64,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, flat_scratch
-// CHECK: [0x05,0x00,0x70,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, vcc
-// CHECK: [0x05,0x00,0x70,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, exec
-// CHECK: [0x05,0x00,0x70,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, 0
-// CHECK: [0x05,0x00,0x70,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -1
-// CHECK: [0x05,0x00,0x70,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x70,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x70,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f64_e64 v5, -v[1:2]
-// CHECK: [0x05,0x00,0x70,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
-// CHECK: [0x05,0x01,0x70,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x63,0x0a,0x7e]
-
-v_frexp_mant_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x63,0xfc,0x7f]
-
-v_frexp_mant_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x63,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], vcc
-// CHECK: [0x6a,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], exec
-// CHECK: [0x7e,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0
-// CHECK: [0x80,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], -1
-// CHECK: [0xc1,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x62,0x0a,0x7e]
-
-v_frexp_mant_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x62,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_mant_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x62,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x71,0xd1,0xfe,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x71,0xd1,0x02,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x71,0xd1,0x04,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x71,0xd1,0x64,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x71,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x71,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x71,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x71,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x71,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x71,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x71,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x71,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x71,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x08]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x10]
-
-v_frexp_mant_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x18]
-
-v_fract_f64 v[5:6], v[1:2]
-// CHECK: [0x01,0x65,0x0a,0x7e]
-
-v_fract_f64 v[254:255], v[1:2]
-// CHECK: [0x01,0x65,0xfc,0x7f]
-
-v_fract_f64 v[5:6], v[254:255]
-// CHECK: [0xfe,0x65,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[2:3]
-// CHECK: [0x02,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[4:5]
-// CHECK: [0x04,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], s[100:101]
-// CHECK: [0x64,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], flat_scratch
-// CHECK: [0x66,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], vcc
-// CHECK: [0x6a,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], exec
-// CHECK: [0x7e,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0
-// CHECK: [0x80,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], -1
-// CHECK: [0xc1,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0.5
-// CHECK: [0xf0,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], -4.0
-// CHECK: [0xf7,0x64,0x0a,0x7e]
-
-v_fract_f64 v[5:6], 0xaf123456
-// CHECK: [0xff,0x64,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_fract_f64 v[5:6], 0x3f717273
-// CHECK: [0xff,0x64,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_fract_f64_e64 v[5:6], v[1:2]
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[254:255], v[1:2]
-// CHECK: [0xfe,0x00,0x72,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[254:255]
-// CHECK: [0x05,0x00,0x72,0xd1,0xfe,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[2:3]
-// CHECK: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[4:5]
-// CHECK: [0x05,0x00,0x72,0xd1,0x04,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], s[100:101]
-// CHECK: [0x05,0x00,0x72,0xd1,0x64,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], flat_scratch
-// CHECK: [0x05,0x00,0x72,0xd1,0x66,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], vcc
-// CHECK: [0x05,0x00,0x72,0xd1,0x6a,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], exec
-// CHECK: [0x05,0x00,0x72,0xd1,0x7e,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], 0
-// CHECK: [0x05,0x00,0x72,0xd1,0x80,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -1
-// CHECK: [0x05,0x00,0x72,0xd1,0xc1,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], 0.5
-// CHECK: [0x05,0x00,0x72,0xd1,0xf0,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -4.0
-// CHECK: [0x05,0x00,0x72,0xd1,0xf7,0x00,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], -v[1:2]
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x20]
-
-v_fract_f64_e64 v[5:6], |v[1:2]|
-// CHECK: [0x05,0x01,0x72,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[1:2] clamp
-// CHECK: [0x05,0x80,0x72,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f64_e64 v[5:6], v[1:2] mul:2
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x08]
-
-v_fract_f64_e64 v[5:6], v[1:2] mul:4
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x10]
-
-v_fract_f64_e64 v[5:6], v[1:2] div:2
-// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x18]
-
-v_frexp_exp_i32_f32 v5, v1
-// CHECK: [0x01,0x67,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v255, v1
-// CHECK: [0x01,0x67,0xfe,0x7f]
-
-v_frexp_exp_i32_f32 v5, v255
-// CHECK: [0xff,0x67,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, s1
-// CHECK: [0x01,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, s101
-// CHECK: [0x65,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, vcc_lo
-// CHECK: [0x6a,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, vcc_hi
-// CHECK: [0x6b,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, m0
-// CHECK: [0x7c,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, exec_lo
-// CHECK: [0x7e,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, exec_hi
-// CHECK: [0x7f,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0
-// CHECK: [0x80,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, -1
-// CHECK: [0xc1,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0.5
-// CHECK: [0xf0,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, -4.0
-// CHECK: [0xf7,0x66,0x0a,0x7e]
-
-v_frexp_exp_i32_f32 v5, 0xaf123456
-// CHECK: [0xff,0x66,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_exp_i32_f32 v5, 0x3f717273
-// CHECK: [0xff,0x66,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_exp_i32_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x73,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x73,0xd1,0xff,0x01,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x73,0xd1,0x65,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x73,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x73,0xd1,0x67,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x73,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x73,0xd1,0x6b,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x73,0xd1,0x7c,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x73,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x73,0xd1,0x7f,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x73,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x73,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x73,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x73,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i32_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i32_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x73,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32 v5, v1
-// CHECK: [0x01,0x69,0x0a,0x7e]
-
-v_frexp_mant_f32 v255, v1
-// CHECK: [0x01,0x69,0xfe,0x7f]
-
-v_frexp_mant_f32 v5, v255
-// CHECK: [0xff,0x69,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, s1
-// CHECK: [0x01,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, s101
-// CHECK: [0x65,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, vcc_lo
-// CHECK: [0x6a,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, vcc_hi
-// CHECK: [0x6b,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, m0
-// CHECK: [0x7c,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, exec_lo
-// CHECK: [0x7e,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, exec_hi
-// CHECK: [0x7f,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0
-// CHECK: [0x80,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, -1
-// CHECK: [0xc1,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0.5
-// CHECK: [0xf0,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, -4.0
-// CHECK: [0xf7,0x68,0x0a,0x7e]
-
-v_frexp_mant_f32 v5, 0xaf123456
-// CHECK: [0xff,0x68,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_frexp_mant_f32 v5, 0x3f717273
-// CHECK: [0xff,0x68,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_frexp_mant_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x74,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x74,0xd1,0xff,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x74,0xd1,0x65,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x74,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x74,0xd1,0x67,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x74,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x74,0xd1,0x6b,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x74,0xd1,0x7c,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x74,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x74,0xd1,0x7f,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x74,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x74,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x74,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x74,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x74,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x74,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x08]
-
-v_frexp_mant_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x10]
-
-v_frexp_mant_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x18]
-
-v_clrexcp
-// CHECK: [0x00,0x6a,0x00,0x7e]
-
-v_clrexcp_e64
-// CHECK: [0x00,0x00,0x75,0xd1,0x00,0x00,0x00,0x00]
-
-v_cvt_f16_u16 v5, v1
-// CHECK: [0x01,0x73,0x0a,0x7e]
-
-v_cvt_f16_u16 v255, v1
-// CHECK: [0x01,0x73,0xfe,0x7f]
-
-v_cvt_f16_u16 v5, v255
-// CHECK: [0xff,0x73,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, s1
-// CHECK: [0x01,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, s101
-// CHECK: [0x65,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, flat_scratch_lo
-// CHECK: [0x66,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, flat_scratch_hi
-// CHECK: [0x67,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, vcc_lo
-// CHECK: [0x6a,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, vcc_hi
-// CHECK: [0x6b,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, m0
-// CHECK: [0x7c,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, exec_lo
-// CHECK: [0x7e,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, exec_hi
-// CHECK: [0x7f,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, 0
-// CHECK: [0x80,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, -1
-// CHECK: [0xc1,0x72,0x0a,0x7e]
-
-v_cvt_f16_u16 v5, 0.5
-// CHECK: encoding: [0xff,0x72,0x0a,0x7e,0x00,0x38,0x00,0x00]
-
-v_cvt_f16_u16 v5, -4.0
-// CHECK: encoding: [0xff,0x72,0x0a,0x7e,0x00,0xc4,0x00,0x00]
-
-v_cvt_f16_u16 v5, 0xfe0b
-// CHECK: [0xff,0x72,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_f16_u16 v5, 0x3456
-// CHECK: [0xff,0x72,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, v1
-// CHECK: [0x05,0x00,0x79,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_u16_e64 v255, v1
-// CHECK: [0xff,0x00,0x79,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, v255
-// CHECK: [0x05,0x00,0x79,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, s1
-// CHECK: [0x05,0x00,0x79,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, s101
-// CHECK: [0x05,0x00,0x79,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x79,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x79,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x79,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x79,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, m0
-// CHECK: [0x05,0x00,0x79,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x79,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x79,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, 0
-// CHECK: [0x05,0x00,0x79,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, -1
-// CHECK: [0x05,0x00,0x79,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_u16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x79,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_i16 v5, v1
-// CHECK: [0x01,0x75,0x0a,0x7e]
-
-v_cvt_f16_i16 v255, v1
-// CHECK: [0x01,0x75,0xfe,0x7f]
-
-v_cvt_f16_i16 v5, v255
-// CHECK: [0xff,0x75,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, s1
-// CHECK: [0x01,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, s101
-// CHECK: [0x65,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, flat_scratch_lo
-// CHECK: [0x66,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, flat_scratch_hi
-// CHECK: [0x67,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, vcc_lo
-// CHECK: [0x6a,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, vcc_hi
-// CHECK: [0x6b,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, m0
-// CHECK: [0x7c,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, exec_lo
-// CHECK: [0x7e,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, exec_hi
-// CHECK: [0x7f,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, 0
-// CHECK: [0x80,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, -1
-// CHECK: [0xc1,0x74,0x0a,0x7e]
-
-v_cvt_f16_i16 v5, 0.5
-// CHECK: encoding: [0xff,0x74,0x0a,0x7e,0x00,0x38,0x00,0x00]
-
-v_cvt_f16_i16 v5, -4.0
-// CHECK: encoding: [0xff,0x74,0x0a,0x7e,0x00,0xc4,0x00,0x00]
-
-v_cvt_f16_i16 v5, 0xfe0b
-// CHECK: [0xff,0x74,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_f16_i16 v5, 0x3456
-// CHECK: [0xff,0x74,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_i16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7a,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7a,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7a,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7a,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7a,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7a,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7a,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7a,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7a,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_f16_i16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16 v5, v1
-// CHECK: [0x01,0x77,0x0a,0x7e]
-
-v_cvt_u16_f16 v255, v1
-// CHECK: [0x01,0x77,0xfe,0x7f]
-
-v_cvt_u16_f16 v5, v255
-// CHECK: [0xff,0x77,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, s1
-// CHECK: [0x01,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, s101
-// CHECK: [0x65,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, vcc_lo
-// CHECK: [0x6a,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, vcc_hi
-// CHECK: [0x6b,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, m0
-// CHECK: [0x7c,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, exec_lo
-// CHECK: [0x7e,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, exec_hi
-// CHECK: [0x7f,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, 0
-// CHECK: [0x80,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, -1
-// CHECK: [0xc1,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, 0.5
-// CHECK: [0xf0,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, -4.0
-// CHECK: [0xf7,0x76,0x0a,0x7e]
-
-v_cvt_u16_f16 v5, 0xfe0b
-// CHECK: [0xff,0x76,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_u16_f16 v5, 0x3456
-// CHECK: [0xff,0x76,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7b,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7b,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7b,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7b,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7b,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_u16_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_u16_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7b,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16 v5, v1
-// CHECK: [0x01,0x79,0x0a,0x7e]
-
-v_cvt_i16_f16 v255, v1
-// CHECK: [0x01,0x79,0xfe,0x7f]
-
-v_cvt_i16_f16 v5, v255
-// CHECK: [0xff,0x79,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, s1
-// CHECK: [0x01,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, s101
-// CHECK: [0x65,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, vcc_lo
-// CHECK: [0x6a,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, vcc_hi
-// CHECK: [0x6b,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, m0
-// CHECK: [0x7c,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, exec_lo
-// CHECK: [0x7e,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, exec_hi
-// CHECK: [0x7f,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, 0
-// CHECK: [0x80,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, -1
-// CHECK: [0xc1,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, 0.5
-// CHECK: [0xf0,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, -4.0
-// CHECK: [0xf7,0x78,0x0a,0x7e]
-
-v_cvt_i16_f16 v5, 0xfe0b
-// CHECK: [0xff,0x78,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cvt_i16_f16 v5, 0x3456
-// CHECK: [0xff,0x78,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7c,0xd1,0xff,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7c,0xd1,0x65,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7c,0xd1,0x66,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7c,0xd1,0x67,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7c,0xd1,0x80,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x20]
-
-v_cvt_i16_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7c,0xd1,0x01,0x01,0x00,0x00]
-
-v_cvt_i16_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7c,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f16 v5, v1
-// CHECK: [0x01,0x7b,0x0a,0x7e]
-
-v_rcp_f16 v255, v1
-// CHECK: [0x01,0x7b,0xfe,0x7f]
-
-v_rcp_f16 v5, v255
-// CHECK: [0xff,0x7b,0x0a,0x7e]
-
-v_rcp_f16 v5, s1
-// CHECK: [0x01,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, s101
-// CHECK: [0x65,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, vcc_lo
-// CHECK: [0x6a,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, vcc_hi
-// CHECK: [0x6b,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, m0
-// CHECK: [0x7c,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, exec_lo
-// CHECK: [0x7e,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, exec_hi
-// CHECK: [0x7f,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, 0
-// CHECK: [0x80,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, -1
-// CHECK: [0xc1,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, 0.5
-// CHECK: [0xf0,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, -4.0
-// CHECK: [0xf7,0x7a,0x0a,0x7e]
-
-v_rcp_f16 v5, 0xfe0b
-// CHECK: [0xff,0x7a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_rcp_f16 v5, 0x3456
-// CHECK: [0xff,0x7a,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_rcp_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7d,0xd1,0xff,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7d,0xd1,0x65,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7d,0xd1,0x66,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7d,0xd1,0x67,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7d,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7d,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7d,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7d,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7d,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7d,0xd1,0x80,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7d,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7d,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7d,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rcp_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x20]
-
-v_rcp_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7d,0xd1,0x01,0x01,0x00,0x00]
-
-v_rcp_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7d,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16 v5, v1
-// CHECK: [0x01,0x7d,0x0a,0x7e]
-
-v_sqrt_f16 v255, v1
-// CHECK: [0x01,0x7d,0xfe,0x7f]
-
-v_sqrt_f16 v5, v255
-// CHECK: [0xff,0x7d,0x0a,0x7e]
-
-v_sqrt_f16 v5, s1
-// CHECK: [0x01,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, s101
-// CHECK: [0x65,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, vcc_lo
-// CHECK: [0x6a,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, vcc_hi
-// CHECK: [0x6b,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, m0
-// CHECK: [0x7c,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, exec_lo
-// CHECK: [0x7e,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, exec_hi
-// CHECK: [0x7f,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, 0
-// CHECK: [0x80,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, -1
-// CHECK: [0xc1,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, 0.5
-// CHECK: [0xf0,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, -4.0
-// CHECK: [0xf7,0x7c,0x0a,0x7e]
-
-v_sqrt_f16 v5, 0xfe0b
-// CHECK: [0xff,0x7c,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_sqrt_f16 v5, 0x3456
-// CHECK: [0xff,0x7c,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_sqrt_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7e,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7e,0xd1,0xff,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7e,0xd1,0x65,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7e,0xd1,0x66,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7e,0xd1,0x67,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7e,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7e,0xd1,0x6b,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7e,0xd1,0x7c,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7e,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7e,0xd1,0x7f,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7e,0xd1,0x80,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7e,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7e,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7e,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sqrt_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x01,0x00,0x20]
-
-v_sqrt_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7e,0xd1,0x01,0x01,0x00,0x00]
-
-v_sqrt_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7e,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f16 v5, v1
-// CHECK: [0x01,0x7f,0x0a,0x7e]
-
-v_rsq_f16 v255, v1
-// CHECK: [0x01,0x7f,0xfe,0x7f]
-
-v_rsq_f16 v5, v255
-// CHECK: [0xff,0x7f,0x0a,0x7e]
-
-v_rsq_f16 v5, s1
-// CHECK: [0x01,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, s101
-// CHECK: [0x65,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, vcc_lo
-// CHECK: [0x6a,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, vcc_hi
-// CHECK: [0x6b,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, m0
-// CHECK: [0x7c,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, exec_lo
-// CHECK: [0x7e,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, exec_hi
-// CHECK: [0x7f,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, 0
-// CHECK: [0x80,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, -1
-// CHECK: [0xc1,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, 0.5
-// CHECK: [0xf0,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, -4.0
-// CHECK: [0xf7,0x7e,0x0a,0x7e]
-
-v_rsq_f16 v5, 0xfe0b
-// CHECK: [0xff,0x7e,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_rsq_f16 v5, 0x3456
-// CHECK: [0xff,0x7e,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_rsq_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x7f,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x7f,0xd1,0xff,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x7f,0xd1,0x65,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x7f,0xd1,0x66,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x7f,0xd1,0x67,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x7f,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x7f,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x7f,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x7f,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x7f,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x7f,0xd1,0x80,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x7f,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x7f,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x7f,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rsq_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x01,0x00,0x20]
-
-v_rsq_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x7f,0xd1,0x01,0x01,0x00,0x00]
-
-v_rsq_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x7f,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f16 v5, v1
-// CHECK: [0x01,0x81,0x0a,0x7e]
-
-v_log_f16 v255, v1
-// CHECK: [0x01,0x81,0xfe,0x7f]
-
-v_log_f16 v5, v255
-// CHECK: [0xff,0x81,0x0a,0x7e]
-
-v_log_f16 v5, s1
-// CHECK: [0x01,0x80,0x0a,0x7e]
-
-v_log_f16 v5, s101
-// CHECK: [0x65,0x80,0x0a,0x7e]
-
-v_log_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x80,0x0a,0x7e]
-
-v_log_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x80,0x0a,0x7e]
-
-v_log_f16 v5, vcc_lo
-// CHECK: [0x6a,0x80,0x0a,0x7e]
-
-v_log_f16 v5, vcc_hi
-// CHECK: [0x6b,0x80,0x0a,0x7e]
-
-v_log_f16 v5, m0
-// CHECK: [0x7c,0x80,0x0a,0x7e]
-
-v_log_f16 v5, exec_lo
-// CHECK: [0x7e,0x80,0x0a,0x7e]
-
-v_log_f16 v5, exec_hi
-// CHECK: [0x7f,0x80,0x0a,0x7e]
-
-v_log_f16 v5, 0
-// CHECK: [0x80,0x80,0x0a,0x7e]
-
-v_log_f16 v5, -1
-// CHECK: [0xc1,0x80,0x0a,0x7e]
-
-v_log_f16 v5, 0.5
-// CHECK: [0xf0,0x80,0x0a,0x7e]
-
-v_log_f16 v5, -4.0
-// CHECK: [0xf7,0x80,0x0a,0x7e]
-
-v_log_f16 v5, 0xfe0b
-// CHECK: [0xff,0x80,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_log_f16 v5, 0x3456
-// CHECK: [0xff,0x80,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_log_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x80,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x80,0xd1,0xff,0x01,0x00,0x00]
-
-v_log_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x80,0xd1,0x65,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x80,0xd1,0x66,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x80,0xd1,0x67,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x80,0xd1,0x6a,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x80,0xd1,0x6b,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x80,0xd1,0x7c,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x80,0xd1,0x7e,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x80,0xd1,0x7f,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x80,0xd1,0x80,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x80,0xd1,0xc1,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x80,0xd1,0xf0,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x80,0xd1,0xf7,0x00,0x00,0x00]
-
-v_log_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x01,0x00,0x20]
-
-v_log_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x80,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x80,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f16 v5, v1
-// CHECK: [0x01,0x83,0x0a,0x7e]
-
-v_exp_f16 v255, v1
-// CHECK: [0x01,0x83,0xfe,0x7f]
-
-v_exp_f16 v5, v255
-// CHECK: [0xff,0x83,0x0a,0x7e]
-
-v_exp_f16 v5, s1
-// CHECK: [0x01,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, s101
-// CHECK: [0x65,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, vcc_lo
-// CHECK: [0x6a,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, vcc_hi
-// CHECK: [0x6b,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, m0
-// CHECK: [0x7c,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, exec_lo
-// CHECK: [0x7e,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, exec_hi
-// CHECK: [0x7f,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, 0
-// CHECK: [0x80,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, -1
-// CHECK: [0xc1,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, 0.5
-// CHECK: [0xf0,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, -4.0
-// CHECK: [0xf7,0x82,0x0a,0x7e]
-
-v_exp_f16 v5, 0xfe0b
-// CHECK: [0xff,0x82,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_exp_f16 v5, 0x3456
-// CHECK: [0xff,0x82,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_exp_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x81,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x81,0xd1,0xff,0x01,0x00,0x00]
-
-v_exp_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x81,0xd1,0x65,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x81,0xd1,0x66,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x81,0xd1,0x67,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x81,0xd1,0x6a,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x81,0xd1,0x6b,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x81,0xd1,0x7c,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x81,0xd1,0x7e,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x81,0xd1,0x7f,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x81,0xd1,0x80,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x81,0xd1,0xc1,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x81,0xd1,0xf0,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x81,0xd1,0xf7,0x00,0x00,0x00]
-
-v_exp_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x01,0x00,0x20]
-
-v_exp_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x81,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x81,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16 v5, v1
-// CHECK: [0x01,0x85,0x0a,0x7e]
-
-v_frexp_mant_f16 v255, v1
-// CHECK: [0x01,0x85,0xfe,0x7f]
-
-v_frexp_mant_f16 v5, v255
-// CHECK: [0xff,0x85,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, s1
-// CHECK: [0x01,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, s101
-// CHECK: [0x65,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, vcc_lo
-// CHECK: [0x6a,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, vcc_hi
-// CHECK: [0x6b,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, m0
-// CHECK: [0x7c,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, exec_lo
-// CHECK: [0x7e,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, exec_hi
-// CHECK: [0x7f,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, 0
-// CHECK: [0x80,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, -1
-// CHECK: [0xc1,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, 0.5
-// CHECK: [0xf0,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, -4.0
-// CHECK: [0xf7,0x84,0x0a,0x7e]
-
-v_frexp_mant_f16 v5, 0xfe0b
-// CHECK: [0xff,0x84,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_frexp_mant_f16 v5, 0x3456
-// CHECK: [0xff,0x84,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x82,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x82,0xd1,0xff,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x82,0xd1,0x65,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x82,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x82,0xd1,0x67,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x82,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x82,0xd1,0x6b,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x82,0xd1,0x7c,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x82,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x82,0xd1,0x7f,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x82,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x82,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x82,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x82,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_mant_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x82,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_mant_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x82,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16 v5, v1
-// CHECK: [0x01,0x87,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v255, v1
-// CHECK: [0x01,0x87,0xfe,0x7f]
-
-v_frexp_exp_i16_f16 v5, v255
-// CHECK: [0xff,0x87,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, s1
-// CHECK: [0x01,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, s101
-// CHECK: [0x65,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, vcc_lo
-// CHECK: [0x6a,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, vcc_hi
-// CHECK: [0x6b,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, m0
-// CHECK: [0x7c,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, exec_lo
-// CHECK: [0x7e,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, exec_hi
-// CHECK: [0x7f,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, 0
-// CHECK: [0x80,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, -1
-// CHECK: [0xc1,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, 0.5
-// CHECK: [0xf0,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, -4.0
-// CHECK: [0xf7,0x86,0x0a,0x7e]
-
-v_frexp_exp_i16_f16 v5, 0xfe0b
-// CHECK: [0xff,0x86,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_frexp_exp_i16_f16 v5, 0x3456
-// CHECK: [0xff,0x86,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x83,0xd1,0x01,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x83,0xd1,0xff,0x01,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x83,0xd1,0x65,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x83,0xd1,0x66,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x83,0xd1,0x67,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x83,0xd1,0x6a,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x83,0xd1,0x6b,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x83,0xd1,0x7c,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x83,0xd1,0x7e,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x83,0xd1,0x7f,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x83,0xd1,0x80,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x83,0xd1,0xc1,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x83,0xd1,0xf0,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x83,0xd1,0xf7,0x00,0x00,0x00]
-
-v_frexp_exp_i16_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x01,0x00,0x20]
-
-v_frexp_exp_i16_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x83,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f16 v5, v1
-// CHECK: [0x01,0x89,0x0a,0x7e]
-
-v_floor_f16 v255, v1
-// CHECK: [0x01,0x89,0xfe,0x7f]
-
-v_floor_f16 v5, v255
-// CHECK: [0xff,0x89,0x0a,0x7e]
-
-v_floor_f16 v5, s1
-// CHECK: [0x01,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, s101
-// CHECK: [0x65,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, vcc_lo
-// CHECK: [0x6a,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, vcc_hi
-// CHECK: [0x6b,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, m0
-// CHECK: [0x7c,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, exec_lo
-// CHECK: [0x7e,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, exec_hi
-// CHECK: [0x7f,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, 0
-// CHECK: [0x80,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, -1
-// CHECK: [0xc1,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, 0.5
-// CHECK: [0xf0,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, -4.0
-// CHECK: [0xf7,0x88,0x0a,0x7e]
-
-v_floor_f16 v5, 0xfe0b
-// CHECK: [0xff,0x88,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_floor_f16 v5, 0x3456
-// CHECK: [0xff,0x88,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_floor_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x84,0xd1,0xff,0x01,0x00,0x00]
-
-v_floor_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x84,0xd1,0x65,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x84,0xd1,0x66,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x84,0xd1,0x67,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x84,0xd1,0x6a,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x84,0xd1,0x6b,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x84,0xd1,0x7c,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x84,0xd1,0x7e,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x84,0xd1,0x7f,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x84,0xd1,0x80,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x84,0xd1,0xc1,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x84,0xd1,0xf0,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x84,0xd1,0xf7,0x00,0x00,0x00]
-
-v_floor_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x20]
-
-v_floor_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x84,0xd1,0x01,0x01,0x00,0x00]
-
-v_floor_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x84,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f16 v5, v1
-// CHECK: [0x01,0x8b,0x0a,0x7e]
-
-v_ceil_f16 v255, v1
-// CHECK: [0x01,0x8b,0xfe,0x7f]
-
-v_ceil_f16 v5, v255
-// CHECK: [0xff,0x8b,0x0a,0x7e]
-
-v_ceil_f16 v5, s1
-// CHECK: [0x01,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, s101
-// CHECK: [0x65,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, vcc_lo
-// CHECK: [0x6a,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, vcc_hi
-// CHECK: [0x6b,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, m0
-// CHECK: [0x7c,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, exec_lo
-// CHECK: [0x7e,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, exec_hi
-// CHECK: [0x7f,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, 0
-// CHECK: [0x80,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, -1
-// CHECK: [0xc1,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, 0.5
-// CHECK: [0xf0,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, -4.0
-// CHECK: [0xf7,0x8a,0x0a,0x7e]
-
-v_ceil_f16 v5, 0xfe0b
-// CHECK: [0xff,0x8a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_ceil_f16 v5, 0x3456
-// CHECK: [0xff,0x8a,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_ceil_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x85,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x85,0xd1,0xff,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x85,0xd1,0x65,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x85,0xd1,0x66,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x85,0xd1,0x67,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x85,0xd1,0x6a,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x85,0xd1,0x6b,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x85,0xd1,0x7c,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x85,0xd1,0x7e,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x85,0xd1,0x7f,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x85,0xd1,0x80,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x85,0xd1,0xc1,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x85,0xd1,0xf0,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x85,0xd1,0xf7,0x00,0x00,0x00]
-
-v_ceil_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x01,0x00,0x20]
-
-v_ceil_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x85,0xd1,0x01,0x01,0x00,0x00]
-
-v_ceil_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x85,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f16 v5, v1
-// CHECK: [0x01,0x8d,0x0a,0x7e]
-
-v_trunc_f16 v255, v1
-// CHECK: [0x01,0x8d,0xfe,0x7f]
-
-v_trunc_f16 v5, v255
-// CHECK: [0xff,0x8d,0x0a,0x7e]
-
-v_trunc_f16 v5, s1
-// CHECK: [0x01,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, s101
-// CHECK: [0x65,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, vcc_lo
-// CHECK: [0x6a,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, vcc_hi
-// CHECK: [0x6b,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, m0
-// CHECK: [0x7c,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, exec_lo
-// CHECK: [0x7e,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, exec_hi
-// CHECK: [0x7f,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, 0
-// CHECK: [0x80,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, -1
-// CHECK: [0xc1,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, 0.5
-// CHECK: [0xf0,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, -4.0
-// CHECK: [0xf7,0x8c,0x0a,0x7e]
-
-v_trunc_f16 v5, 0xfe0b
-// CHECK: [0xff,0x8c,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_trunc_f16 v5, 0x3456
-// CHECK: [0xff,0x8c,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_trunc_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x86,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x86,0xd1,0xff,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x86,0xd1,0x65,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x86,0xd1,0x66,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x86,0xd1,0x67,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x86,0xd1,0x6a,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x86,0xd1,0x6b,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x86,0xd1,0x7c,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x86,0xd1,0x7e,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x86,0xd1,0x7f,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x86,0xd1,0x80,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x86,0xd1,0xc1,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x86,0xd1,0xf0,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x86,0xd1,0xf7,0x00,0x00,0x00]
-
-v_trunc_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x01,0x00,0x20]
-
-v_trunc_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x86,0xd1,0x01,0x01,0x00,0x00]
-
-v_trunc_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x86,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f16 v5, v1
-// CHECK: [0x01,0x8f,0x0a,0x7e]
-
-v_rndne_f16 v255, v1
-// CHECK: [0x01,0x8f,0xfe,0x7f]
-
-v_rndne_f16 v5, v255
-// CHECK: [0xff,0x8f,0x0a,0x7e]
-
-v_rndne_f16 v5, s1
-// CHECK: [0x01,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, s101
-// CHECK: [0x65,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, vcc_lo
-// CHECK: [0x6a,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, vcc_hi
-// CHECK: [0x6b,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, m0
-// CHECK: [0x7c,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, exec_lo
-// CHECK: [0x7e,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, exec_hi
-// CHECK: [0x7f,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, 0
-// CHECK: [0x80,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, -1
-// CHECK: [0xc1,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, 0.5
-// CHECK: [0xf0,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, -4.0
-// CHECK: [0xf7,0x8e,0x0a,0x7e]
-
-v_rndne_f16 v5, 0xfe0b
-// CHECK: [0xff,0x8e,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_rndne_f16 v5, 0x3456
-// CHECK: [0xff,0x8e,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_rndne_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x87,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x87,0xd1,0xff,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x87,0xd1,0x65,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x87,0xd1,0x66,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x87,0xd1,0x67,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x87,0xd1,0x6a,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x87,0xd1,0x6b,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x87,0xd1,0x7c,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x87,0xd1,0x7e,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x87,0xd1,0x7f,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x87,0xd1,0x80,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x87,0xd1,0xc1,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x87,0xd1,0xf0,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x87,0xd1,0xf7,0x00,0x00,0x00]
-
-v_rndne_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x01,0x00,0x20]
-
-v_rndne_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x87,0xd1,0x01,0x01,0x00,0x00]
-
-v_rndne_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x87,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f16 v5, v1
-// CHECK: [0x01,0x91,0x0a,0x7e]
-
-v_fract_f16 v255, v1
-// CHECK: [0x01,0x91,0xfe,0x7f]
-
-v_fract_f16 v5, v255
-// CHECK: [0xff,0x91,0x0a,0x7e]
-
-v_fract_f16 v5, s1
-// CHECK: [0x01,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, s101
-// CHECK: [0x65,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, vcc_lo
-// CHECK: [0x6a,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, vcc_hi
-// CHECK: [0x6b,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, m0
-// CHECK: [0x7c,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, exec_lo
-// CHECK: [0x7e,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, exec_hi
-// CHECK: [0x7f,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, 0
-// CHECK: [0x80,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, -1
-// CHECK: [0xc1,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, 0.5
-// CHECK: [0xf0,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, -4.0
-// CHECK: [0xf7,0x90,0x0a,0x7e]
-
-v_fract_f16 v5, 0xfe0b
-// CHECK: [0xff,0x90,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_fract_f16 v5, 0x3456
-// CHECK: [0xff,0x90,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_fract_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x88,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x88,0xd1,0xff,0x01,0x00,0x00]
-
-v_fract_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x88,0xd1,0x65,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x88,0xd1,0x66,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x88,0xd1,0x67,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x88,0xd1,0x6a,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x88,0xd1,0x6b,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x88,0xd1,0x7c,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x88,0xd1,0x7e,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x88,0xd1,0x7f,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x88,0xd1,0x80,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x88,0xd1,0xc1,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x88,0xd1,0xf0,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x88,0xd1,0xf7,0x00,0x00,0x00]
-
-v_fract_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x01,0x00,0x20]
-
-v_fract_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x88,0xd1,0x01,0x01,0x00,0x00]
-
-v_fract_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x88,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f16 v5, v1
-// CHECK: [0x01,0x93,0x0a,0x7e]
-
-v_sin_f16 v255, v1
-// CHECK: [0x01,0x93,0xfe,0x7f]
-
-v_sin_f16 v5, v255
-// CHECK: [0xff,0x93,0x0a,0x7e]
-
-v_sin_f16 v5, s1
-// CHECK: [0x01,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, s101
-// CHECK: [0x65,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, vcc_lo
-// CHECK: [0x6a,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, vcc_hi
-// CHECK: [0x6b,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, m0
-// CHECK: [0x7c,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, exec_lo
-// CHECK: [0x7e,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, exec_hi
-// CHECK: [0x7f,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, 0
-// CHECK: [0x80,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, -1
-// CHECK: [0xc1,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, 0.5
-// CHECK: [0xf0,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, -4.0
-// CHECK: [0xf7,0x92,0x0a,0x7e]
-
-v_sin_f16 v5, 0xfe0b
-// CHECK: [0xff,0x92,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_sin_f16 v5, 0x3456
-// CHECK: [0xff,0x92,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_sin_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x89,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x89,0xd1,0xff,0x01,0x00,0x00]
-
-v_sin_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x89,0xd1,0x65,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x89,0xd1,0x66,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x89,0xd1,0x67,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x89,0xd1,0x6a,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x89,0xd1,0x6b,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x89,0xd1,0x7c,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x89,0xd1,0x7e,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x89,0xd1,0x7f,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x89,0xd1,0x80,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x89,0xd1,0xc1,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x89,0xd1,0xf0,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x89,0xd1,0xf7,0x00,0x00,0x00]
-
-v_sin_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x01,0x00,0x20]
-
-v_sin_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x89,0xd1,0x01,0x01,0x00,0x00]
-
-v_sin_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x89,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f16 v5, v1
-// CHECK: [0x01,0x95,0x0a,0x7e]
-
-v_cos_f16 v255, v1
-// CHECK: [0x01,0x95,0xfe,0x7f]
-
-v_cos_f16 v5, v255
-// CHECK: [0xff,0x95,0x0a,0x7e]
-
-v_cos_f16 v5, s1
-// CHECK: [0x01,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, s101
-// CHECK: [0x65,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, flat_scratch_lo
-// CHECK: [0x66,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, flat_scratch_hi
-// CHECK: [0x67,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, vcc_lo
-// CHECK: [0x6a,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, vcc_hi
-// CHECK: [0x6b,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, m0
-// CHECK: [0x7c,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, exec_lo
-// CHECK: [0x7e,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, exec_hi
-// CHECK: [0x7f,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, 0
-// CHECK: [0x80,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, -1
-// CHECK: [0xc1,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, 0.5
-// CHECK: [0xf0,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, -4.0
-// CHECK: [0xf7,0x94,0x0a,0x7e]
-
-v_cos_f16 v5, 0xfe0b
-// CHECK: [0xff,0x94,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
-
-v_cos_f16 v5, 0x3456
-// CHECK: [0xff,0x94,0x0a,0x7e,0x56,0x34,0x00,0x00]
-
-v_cos_f16_e64 v5, v1
-// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f16_e64 v255, v1
-// CHECK: [0xff,0x00,0x8a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f16_e64 v5, v255
-// CHECK: [0x05,0x00,0x8a,0xd1,0xff,0x01,0x00,0x00]
-
-v_cos_f16_e64 v5, s1
-// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, s101
-// CHECK: [0x05,0x00,0x8a,0xd1,0x65,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8a,0xd1,0x66,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8a,0xd1,0x67,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x8a,0xd1,0x6a,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x8a,0xd1,0x6b,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, m0
-// CHECK: [0x05,0x00,0x8a,0xd1,0x7c,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x8a,0xd1,0x7e,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x8a,0xd1,0x7f,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, 0
-// CHECK: [0x05,0x00,0x8a,0xd1,0x80,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, -1
-// CHECK: [0x05,0x00,0x8a,0xd1,0xc1,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x8a,0xd1,0xf0,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x8a,0xd1,0xf7,0x00,0x00,0x00]
-
-v_cos_f16_e64 v5, -v1
-// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x01,0x00,0x20]
-
-v_cos_f16_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x8a,0xd1,0x01,0x01,0x00,0x00]
-
-v_cos_f16_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x8a,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32 v5, v1
-// CHECK: [0x01,0x97,0x0a,0x7e]
-
-v_exp_legacy_f32 v255, v1
-// CHECK: [0x01,0x97,0xfe,0x7f]
-
-v_exp_legacy_f32 v5, v255
-// CHECK: [0xff,0x97,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, s1
-// CHECK: [0x01,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, s101
-// CHECK: [0x65,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, vcc_lo
-// CHECK: [0x6a,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, vcc_hi
-// CHECK: [0x6b,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, m0
-// CHECK: [0x7c,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, exec_lo
-// CHECK: [0x7e,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, exec_hi
-// CHECK: [0x7f,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, 0
-// CHECK: [0x80,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, -1
-// CHECK: [0xc1,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, 0.5
-// CHECK: [0xf0,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, -4.0
-// CHECK: [0xf7,0x96,0x0a,0x7e]
-
-v_exp_legacy_f32 v5, 0xaf123456
-// CHECK: [0xff,0x96,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_exp_legacy_f32 v5, 0x3f717273
-// CHECK: [0xff,0x96,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_exp_legacy_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x8b,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x8b,0xd1,0xff,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x8b,0xd1,0x65,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8b,0xd1,0x66,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8b,0xd1,0x67,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x8b,0xd1,0x6a,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x8b,0xd1,0x6b,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x8b,0xd1,0x7c,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x8b,0xd1,0x7e,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x8b,0xd1,0x7f,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x8b,0xd1,0x80,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x8b,0xd1,0xc1,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x8b,0xd1,0xf0,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x8b,0xd1,0xf7,0x00,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x20]
-
-v_exp_legacy_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x8b,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x8b,0xd1,0x01,0x01,0x00,0x00]
-
-v_exp_legacy_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x08]
-
-v_exp_legacy_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x10]
-
-v_exp_legacy_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x18]
-
-v_log_legacy_f32 v5, v1
-// CHECK: [0x01,0x99,0x0a,0x7e]
-
-v_log_legacy_f32 v255, v1
-// CHECK: [0x01,0x99,0xfe,0x7f]
-
-v_log_legacy_f32 v5, v255
-// CHECK: [0xff,0x99,0x0a,0x7e]
-
-v_log_legacy_f32 v5, s1
-// CHECK: [0x01,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, s101
-// CHECK: [0x65,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, flat_scratch_lo
-// CHECK: [0x66,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, flat_scratch_hi
-// CHECK: [0x67,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, vcc_lo
-// CHECK: [0x6a,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, vcc_hi
-// CHECK: [0x6b,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, m0
-// CHECK: [0x7c,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, exec_lo
-// CHECK: [0x7e,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, exec_hi
-// CHECK: [0x7f,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, 0
-// CHECK: [0x80,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, -1
-// CHECK: [0xc1,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, 0.5
-// CHECK: [0xf0,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, -4.0
-// CHECK: [0xf7,0x98,0x0a,0x7e]
-
-v_log_legacy_f32 v5, 0xaf123456
-// CHECK: [0xff,0x98,0x0a,0x7e,0x56,0x34,0x12,0xaf]
-
-v_log_legacy_f32 v5, 0x3f717273
-// CHECK: [0xff,0x98,0x0a,0x7e,0x73,0x72,0x71,0x3f]
-
-v_log_legacy_f32_e64 v5, v1
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v255, v1
-// CHECK: [0xff,0x00,0x8c,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, v255
-// CHECK: [0x05,0x00,0x8c,0xd1,0xff,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, s1
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, s101
-// CHECK: [0x05,0x00,0x8c,0xd1,0x65,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8c,0xd1,0x66,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8c,0xd1,0x67,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, vcc_lo
-// CHECK: [0x05,0x00,0x8c,0xd1,0x6a,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, vcc_hi
-// CHECK: [0x05,0x00,0x8c,0xd1,0x6b,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, m0
-// CHECK: [0x05,0x00,0x8c,0xd1,0x7c,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, exec_lo
-// CHECK: [0x05,0x00,0x8c,0xd1,0x7e,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, exec_hi
-// CHECK: [0x05,0x00,0x8c,0xd1,0x7f,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, 0
-// CHECK: [0x05,0x00,0x8c,0xd1,0x80,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, -1
-// CHECK: [0x05,0x00,0x8c,0xd1,0xc1,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, 0.5
-// CHECK: [0x05,0x00,0x8c,0xd1,0xf0,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, -4.0
-// CHECK: [0x05,0x00,0x8c,0xd1,0xf7,0x00,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, -v1
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x20]
-
-v_log_legacy_f32_e64 v5, |v1|
-// CHECK: [0x05,0x01,0x8c,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, v1 clamp
-// CHECK: [0x05,0x80,0x8c,0xd1,0x01,0x01,0x00,0x00]
-
-v_log_legacy_f32_e64 v5, v1 mul:2
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x08]
-
-v_log_legacy_f32_e64 v5, v1 mul:4
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x10]
-
-v_log_legacy_f32_e64 v5, v1 div:2
-// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x18]
-
-v_swap_b32 v5, v1
-// CHECK: [0x01,0xa3,0x0a,0x7e]
-
-v_swap_b32 v255, v1
-// CHECK: [0x01,0xa3,0xfe,0x7f]
-
-v_swap_b32 v5, v255
-// CHECK: [0xff,0xa3,0x0a,0x7e]
-
-v_cndmask_b32 v5, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x00]
-
-v_cndmask_b32 v255, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x01]
-
-v_cndmask_b32 v5, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x00]
-
-v_cndmask_b32 v5, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x00]
-
-v_cndmask_b32 v5, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x00]
-
-v_cndmask_b32_e64 v5, v1, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x1a,0x00]
-
-v_cndmask_b32_e64 v255, v1, v2, s[6:7]
-// CHECK: [0xff,0x00,0x00,0xd1,0x01,0x05,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, v255, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0xff,0x05,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, 0, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x80,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, -1, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0xc1,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, 0.5, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0xf0,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, -4.0, v2, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0xf7,0x04,0x1a,0x00]
-
-v_cndmask_b32_e64 v5, v1, v255, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xff,0x1b,0x00]
-
-v_cndmask_b32_e64 v5, v1, 0, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x01,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, -1, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x83,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, 0.5, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xe1,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, -4.0, s[6:7]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xef,0x19,0x00]
-
-v_cndmask_b32_e64 v5, v1, v2, s[8:9]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x22,0x00]
-
-v_cndmask_b32_e64 v5, v1, v2, s[100:101]
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x92,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, flat_scratch
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cndmask_b32_e64 v5, v1, v2, vcc
-// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xaa,0x01]
-
-v_add_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x02]
-
-v_add_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x03]
-
-v_add_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x02]
-
-v_add_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x02]
-
-v_add_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x02]
-
-v_add_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x02]
-
-v_add_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x02]
-
-v_add_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x02]
-
-v_add_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x02]
-
-v_add_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x02]
-
-v_add_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x02]
-
-v_add_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x02]
-
-v_add_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x02]
-
-v_add_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x02]
-
-v_add_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x02]
-
-v_add_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x02]
-
-v_add_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x02,0x56,0x34,0x12,0xaf]
-
-v_add_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x02,0x73,0x72,0x71,0x3f]
-
-v_add_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x02]
-
-v_add_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x65,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x66,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x67,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x6a,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x6b,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x7c,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x7e,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x7f,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x80,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0xc1,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0xf0,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0xf7,0x04,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xff,0x03,0x00]
-
-v_add_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x00,0x00]
-
-v_add_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcb,0x00,0x00]
-
-v_add_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcd,0x00,0x00]
-
-v_add_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcf,0x00,0x00]
-
-v_add_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd5,0x00,0x00]
-
-v_add_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd7,0x00,0x00]
-
-v_add_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf9,0x00,0x00]
-
-v_add_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xfd,0x00,0x00]
-
-v_add_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xff,0x00,0x00]
-
-v_add_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x01,0x01,0x00]
-
-v_add_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x83,0x01,0x00]
-
-v_add_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xe1,0x01,0x00]
-
-v_add_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xef,0x01,0x00]
-
-v_add_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x20]
-
-v_add_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x40]
-
-v_add_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x60]
-
-v_add_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x01,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x08]
-
-v_add_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x10]
-
-v_add_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x18]
-
-v_sub_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x04]
-
-v_sub_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x05]
-
-v_sub_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x04]
-
-v_sub_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x04]
-
-v_sub_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x04]
-
-v_sub_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x04]
-
-v_sub_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x04]
-
-v_sub_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x04]
-
-v_sub_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x04]
-
-v_sub_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x04]
-
-v_sub_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x04]
-
-v_sub_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x04]
-
-v_sub_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x04]
-
-v_sub_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x04]
-
-v_sub_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x04]
-
-v_sub_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x04]
-
-v_sub_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x04,0x56,0x34,0x12,0xaf]
-
-v_sub_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x04,0x73,0x72,0x71,0x3f]
-
-v_sub_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x04]
-
-v_sub_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0xff,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x65,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x66,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x67,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x6a,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x6b,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x7c,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x7e,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x7f,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x80,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0xc1,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0xf0,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0xf7,0x04,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xff,0x03,0x00]
-
-v_sub_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcb,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcd,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcf,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd5,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd7,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf9,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xfd,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xff,0x00,0x00]
-
-v_sub_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x01,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xe1,0x01,0x00]
-
-v_sub_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xef,0x01,0x00]
-
-v_sub_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x20]
-
-v_sub_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x40]
-
-v_sub_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x60]
-
-v_sub_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x02,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x08]
-
-v_sub_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x10]
-
-v_sub_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x18]
-
-v_subrev_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x06]
-
-v_subrev_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x07]
-
-v_subrev_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x06]
-
-v_subrev_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x06]
-
-v_subrev_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x06,0x56,0x34,0x12,0xaf]
-
-v_subrev_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x06,0x73,0x72,0x71,0x3f]
-
-v_subrev_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x06]
-
-v_subrev_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0xff,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x65,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x66,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x67,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x6a,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x6b,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x7c,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x7e,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x7f,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x80,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0xc1,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0xf0,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0xf7,0x04,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xff,0x03,0x00]
-
-v_subrev_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcb,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcd,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcf,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd5,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd7,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf9,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xfd,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xff,0x00,0x00]
-
-v_subrev_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x01,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x83,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xe1,0x01,0x00]
-
-v_subrev_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xef,0x01,0x00]
-
-v_subrev_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x20]
-
-v_subrev_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x40]
-
-v_subrev_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x60]
-
-v_subrev_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x03,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x08]
-
-v_subrev_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x10]
-
-v_subrev_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x18]
-
-v_mul_legacy_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x08]
-
-v_mul_legacy_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x09]
-
-v_mul_legacy_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x08]
-
-v_mul_legacy_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x08]
-
-v_mul_legacy_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x08,0x56,0x34,0x12,0xaf]
-
-v_mul_legacy_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x08,0x73,0x72,0x71,0x3f]
-
-v_mul_legacy_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x08]
-
-v_mul_legacy_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_legacy_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x20]
-
-v_mul_legacy_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x40]
-
-v_mul_legacy_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x60]
-
-v_mul_legacy_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x04,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_legacy_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x08]
-
-v_mul_legacy_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x10]
-
-v_mul_legacy_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x18]
-
-v_mul_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x0a]
-
-v_mul_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x0b]
-
-v_mul_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x0a]
-
-v_mul_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x0a]
-
-v_mul_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x0a,0x56,0x34,0x12,0xaf]
-
-v_mul_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x0a,0x73,0x72,0x71,0x3f]
-
-v_mul_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x0a]
-
-v_mul_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x20]
-
-v_mul_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x40]
-
-v_mul_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x60]
-
-v_mul_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x05,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x08]
-
-v_mul_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x10]
-
-v_mul_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x18]
-
-v_mul_i32_i24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x0c]
-
-v_mul_i32_i24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x0d]
-
-v_mul_i32_i24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x0c]
-
-v_mul_i32_i24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x0c]
-
-v_mul_i32_i24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x0c,0x56,0x34,0x12,0xaf]
-
-v_mul_i32_i24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x0c,0x73,0x72,0x71,0x3f]
-
-v_mul_i32_i24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x0c]
-
-v_mul_i32_i24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x06,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_i32_i24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_i32_i24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_i32_i24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_i32_i24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_hi_i32_i24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x0f]
-
-v_mul_hi_i32_i24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x0e]
-
-v_mul_hi_i32_i24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x0e,0x56,0x34,0x12,0xaf]
-
-v_mul_hi_i32_i24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x0e,0x73,0x72,0x71,0x3f]
-
-v_mul_hi_i32_i24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x0e]
-
-v_mul_hi_i32_i24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x07,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x07,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_i32_i24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_u32_u24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x10]
-
-v_mul_u32_u24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x11]
-
-v_mul_u32_u24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x10]
-
-v_mul_u32_u24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x10]
-
-v_mul_u32_u24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x10,0x56,0x34,0x12,0xaf]
-
-v_mul_u32_u24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x10,0x73,0x72,0x71,0x3f]
-
-v_mul_u32_u24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x10]
-
-v_mul_u32_u24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x08,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_u32_u24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_u32_u24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_u32_u24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_u32_u24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_hi_u32_u24 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x12]
-
-v_mul_hi_u32_u24 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x13]
-
-v_mul_hi_u32_u24 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x12]
-
-v_mul_hi_u32_u24 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0xaf]
-
-v_mul_hi_u32_u24 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x3f]
-
-v_mul_hi_u32_u24 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x12]
-
-v_mul_hi_u32_u24_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x09,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x09,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_u32_u24_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xef,0x01,0x00]
-
-v_min_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x14]
-
-v_min_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x15]
-
-v_min_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x14]
-
-v_min_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x14]
-
-v_min_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x14]
-
-v_min_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x14]
-
-v_min_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x14]
-
-v_min_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x14]
-
-v_min_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x14]
-
-v_min_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x14]
-
-v_min_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x14]
-
-v_min_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x14]
-
-v_min_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x14]
-
-v_min_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x14]
-
-v_min_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x14]
-
-v_min_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x14]
-
-v_min_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x14,0x56,0x34,0x12,0xaf]
-
-v_min_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x14,0x73,0x72,0x71,0x3f]
-
-v_min_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x14]
-
-v_min_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0xf0,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0xf7,0x04,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xe1,0x01,0x00]
-
-v_min_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xef,0x01,0x00]
-
-v_min_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x20]
-
-v_min_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x40]
-
-v_min_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x60]
-
-v_min_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x0a,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x08]
-
-v_min_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x10]
-
-v_min_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x18]
-
-v_max_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x16]
-
-v_max_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x17]
-
-v_max_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x16]
-
-v_max_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x16]
-
-v_max_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x16]
-
-v_max_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x16]
-
-v_max_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x16]
-
-v_max_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x16]
-
-v_max_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x16]
-
-v_max_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x16]
-
-v_max_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x16]
-
-v_max_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x16]
-
-v_max_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x16]
-
-v_max_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x16]
-
-v_max_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x16]
-
-v_max_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x16]
-
-v_max_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x16,0x56,0x34,0x12,0xaf]
-
-v_max_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x16,0x73,0x72,0x71,0x3f]
-
-v_max_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x16]
-
-v_max_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0xf0,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0xf7,0x04,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xe1,0x01,0x00]
-
-v_max_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xef,0x01,0x00]
-
-v_max_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x20]
-
-v_max_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x40]
-
-v_max_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x60]
-
-v_max_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x0b,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x08]
-
-v_max_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x10]
-
-v_max_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x18]
-
-v_min_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x18]
-
-v_min_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x19]
-
-v_min_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x18]
-
-v_min_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x18]
-
-v_min_i32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x18]
-
-v_min_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x18]
-
-v_min_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x18]
-
-v_min_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x18]
-
-v_min_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x18]
-
-v_min_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x18]
-
-v_min_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x18]
-
-v_min_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x18]
-
-v_min_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x18]
-
-v_min_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x18]
-
-v_min_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x18]
-
-v_min_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x18]
-
-v_min_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x18,0x56,0x34,0x12,0xaf]
-
-v_min_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x18,0x73,0x72,0x71,0x3f]
-
-v_min_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x18]
-
-v_min_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0xf0,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0c,0xd1,0xf7,0x04,0x02,0x00]
-
-v_min_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_i32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xe1,0x01,0x00]
-
-v_min_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xef,0x01,0x00]
-
-v_max_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x1a]
-
-v_max_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x1b]
-
-v_max_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x1a]
-
-v_max_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x1a]
-
-v_max_i32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x1a]
-
-v_max_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x1a]
-
-v_max_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x1a]
-
-v_max_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x1a]
-
-v_max_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x1a]
-
-v_max_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x1a]
-
-v_max_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x1a]
-
-v_max_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x1a]
-
-v_max_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x1a]
-
-v_max_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x1a]
-
-v_max_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x1a]
-
-v_max_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x1a]
-
-v_max_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x1a,0x56,0x34,0x12,0xaf]
-
-v_max_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x1a,0x73,0x72,0x71,0x3f]
-
-v_max_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x1a]
-
-v_max_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0xf0,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0d,0xd1,0xf7,0x04,0x02,0x00]
-
-v_max_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_i32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xe1,0x01,0x00]
-
-v_max_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xef,0x01,0x00]
-
-v_min_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x1c]
-
-v_min_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x1d]
-
-v_min_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x1c]
-
-v_min_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x1c]
-
-v_min_u32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x1c]
-
-v_min_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x1c]
-
-v_min_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x1c]
-
-v_min_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x1c]
-
-v_min_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x1c]
-
-v_min_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x1c]
-
-v_min_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x1c]
-
-v_min_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x1c]
-
-v_min_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x1c]
-
-v_min_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x1c]
-
-v_min_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x1c]
-
-v_min_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x1c]
-
-v_min_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x1c,0x56,0x34,0x12,0xaf]
-
-v_min_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x1c,0x73,0x72,0x71,0x3f]
-
-v_min_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x1c]
-
-v_min_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0xf0,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0e,0xd1,0xf7,0x04,0x02,0x00]
-
-v_min_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_u32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xe1,0x01,0x00]
-
-v_min_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xef,0x01,0x00]
-
-v_max_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x1e]
-
-v_max_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x1f]
-
-v_max_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x1e]
-
-v_max_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x1e]
-
-v_max_u32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x1e]
-
-v_max_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x1e]
-
-v_max_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x1e]
-
-v_max_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x1e]
-
-v_max_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x1e]
-
-v_max_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x1e]
-
-v_max_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x1e]
-
-v_max_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x1e]
-
-v_max_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x1e]
-
-v_max_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x1e]
-
-v_max_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x1e]
-
-v_max_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x1e]
-
-v_max_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x1e,0x56,0x34,0x12,0xaf]
-
-v_max_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x1e,0x73,0x72,0x71,0x3f]
-
-v_max_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x1e]
-
-v_max_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x0f,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0xf0,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x0f,0xd1,0xf7,0x04,0x02,0x00]
-
-v_max_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_u32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xe1,0x01,0x00]
-
-v_max_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xef,0x01,0x00]
-
-v_lshrrev_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x20]
-
-v_lshrrev_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x21]
-
-v_lshrrev_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x20]
-
-v_lshrrev_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x20]
-
-v_lshrrev_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x20,0x56,0x34,0x12,0xaf]
-
-v_lshrrev_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x20,0x73,0x72,0x71,0x3f]
-
-v_lshrrev_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x20]
-
-v_lshrrev_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x65,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x66,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x67,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0xf0,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x10,0xd1,0xf7,0x04,0x02,0x00]
-
-v_lshrrev_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xff,0x03,0x00]
-
-v_lshrrev_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x05,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcb,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcd,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcf,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd7,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf9,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xff,0x00,0x00]
-
-v_lshrrev_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xe1,0x01,0x00]
-
-v_lshrrev_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xef,0x01,0x00]
-
-v_ashrrev_i32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x22]
-
-v_ashrrev_i32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x23]
-
-v_ashrrev_i32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x22]
-
-v_ashrrev_i32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x22]
-
-v_ashrrev_i32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x22,0x56,0x34,0x12,0xaf]
-
-v_ashrrev_i32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x22,0x73,0x72,0x71,0x3f]
-
-v_ashrrev_i32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x22]
-
-v_ashrrev_i32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x11,0xd1,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x65,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x66,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x67,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0xf0,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x11,0xd1,0xf7,0x04,0x02,0x00]
-
-v_ashrrev_i32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xff,0x03,0x00]
-
-v_ashrrev_i32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x05,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcb,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcd,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcf,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd7,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf9,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xff,0x00,0x00]
-
-v_ashrrev_i32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xe1,0x01,0x00]
-
-v_ashrrev_i32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xef,0x01,0x00]
-
-v_lshlrev_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x24]
-
-v_lshlrev_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x25]
-
-v_lshlrev_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x24]
-
-v_lshlrev_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x24]
-
-v_lshlrev_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x24,0x56,0x34,0x12,0xaf]
-
-v_lshlrev_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x24,0x73,0x72,0x71,0x3f]
-
-v_lshlrev_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x24]
-
-v_lshlrev_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x12,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x65,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x66,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x67,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0xf0,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x12,0xd1,0xf7,0x04,0x02,0x00]
-
-v_lshlrev_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xff,0x03,0x00]
-
-v_lshlrev_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x05,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcb,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcd,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcf,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd7,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf9,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xff,0x00,0x00]
-
-v_lshlrev_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xe1,0x01,0x00]
-
-v_lshlrev_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xef,0x01,0x00]
-
-v_and_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x26]
-
-v_and_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x27]
-
-v_and_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x26]
-
-v_and_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x26]
-
-v_and_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x26]
-
-v_and_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x26]
-
-v_and_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x26]
-
-v_and_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x26]
-
-v_and_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x26]
-
-v_and_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x26]
-
-v_and_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x26]
-
-v_and_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x26]
-
-v_and_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x26]
-
-v_and_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x26]
-
-v_and_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x26]
-
-v_and_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x26]
-
-v_and_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x26,0x56,0x34,0x12,0xaf]
-
-v_and_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x26,0x73,0x72,0x71,0x3f]
-
-v_and_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x26]
-
-v_and_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x05,0x02,0x00]
-
-v_and_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x13,0xd1,0x01,0x05,0x02,0x00]
-
-v_and_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0xff,0x05,0x02,0x00]
-
-v_and_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x65,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x66,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x67,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x6a,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x6b,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x7c,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x7e,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x7f,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0x80,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0xc1,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0xf0,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x13,0xd1,0xf7,0x04,0x02,0x00]
-
-v_and_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xff,0x03,0x00]
-
-v_and_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x05,0x00,0x00]
-
-v_and_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcb,0x00,0x00]
-
-v_and_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcd,0x00,0x00]
-
-v_and_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcf,0x00,0x00]
-
-v_and_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd5,0x00,0x00]
-
-v_and_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd7,0x00,0x00]
-
-v_and_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf9,0x00,0x00]
-
-v_and_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xfd,0x00,0x00]
-
-v_and_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xff,0x00,0x00]
-
-v_and_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x01,0x01,0x00]
-
-v_and_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x83,0x01,0x00]
-
-v_and_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xe1,0x01,0x00]
-
-v_and_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xef,0x01,0x00]
-
-v_or_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x28]
-
-v_or_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x29]
-
-v_or_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x28]
-
-v_or_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x28]
-
-v_or_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x28]
-
-v_or_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x28]
-
-v_or_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x28]
-
-v_or_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x28]
-
-v_or_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x28]
-
-v_or_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x28]
-
-v_or_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x28]
-
-v_or_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x28]
-
-v_or_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x28]
-
-v_or_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x28]
-
-v_or_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x28]
-
-v_or_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x28]
-
-v_or_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x28,0x56,0x34,0x12,0xaf]
-
-v_or_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x28,0x73,0x72,0x71,0x3f]
-
-v_or_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x28]
-
-v_or_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x05,0x02,0x00]
-
-v_or_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x14,0xd1,0x01,0x05,0x02,0x00]
-
-v_or_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0xff,0x05,0x02,0x00]
-
-v_or_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x65,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x66,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x67,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x6a,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x6b,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x7c,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x7e,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x7f,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0x80,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0xc1,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0xf0,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x14,0xd1,0xf7,0x04,0x02,0x00]
-
-v_or_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xff,0x03,0x00]
-
-v_or_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x05,0x00,0x00]
-
-v_or_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcb,0x00,0x00]
-
-v_or_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcd,0x00,0x00]
-
-v_or_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcf,0x00,0x00]
-
-v_or_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd5,0x00,0x00]
-
-v_or_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd7,0x00,0x00]
-
-v_or_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf9,0x00,0x00]
-
-v_or_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xfd,0x00,0x00]
-
-v_or_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xff,0x00,0x00]
-
-v_or_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x01,0x01,0x00]
-
-v_or_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x83,0x01,0x00]
-
-v_or_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xe1,0x01,0x00]
-
-v_or_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xef,0x01,0x00]
-
-v_xor_b32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x2a]
-
-v_xor_b32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x2b]
-
-v_xor_b32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x2a]
-
-v_xor_b32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x2a]
-
-v_xor_b32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x2a,0x56,0x34,0x12,0xaf]
-
-v_xor_b32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x2a,0x73,0x72,0x71,0x3f]
-
-v_xor_b32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x2a]
-
-v_xor_b32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x05,0x02,0x00]
-
-v_xor_b32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x15,0xd1,0x01,0x05,0x02,0x00]
-
-v_xor_b32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0xff,0x05,0x02,0x00]
-
-v_xor_b32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x65,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x66,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x67,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x6a,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x6b,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x7c,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x7e,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x7f,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0x80,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0xc1,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0xf0,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x15,0xd1,0xf7,0x04,0x02,0x00]
-
-v_xor_b32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xff,0x03,0x00]
-
-v_xor_b32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x05,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcb,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcd,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcf,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd5,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd7,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf9,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xfd,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xff,0x00,0x00]
-
-v_xor_b32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x01,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x83,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xe1,0x01,0x00]
-
-v_xor_b32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xef,0x01,0x00]
-
-v_mac_f32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x2c]
-
-v_mac_f32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x2d]
-
-v_mac_f32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x2c]
-
-v_mac_f32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x2c]
-
-v_mac_f32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x2c,0x56,0x34,0x12,0xaf]
-
-v_mac_f32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x2c,0x73,0x72,0x71,0x3f]
-
-v_mac_f32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x2c]
-
-v_mac_f32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0xff,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x65,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x66,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x67,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x80,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xff,0x03,0x00]
-
-v_mac_f32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xff,0x00,0x00]
-
-v_mac_f32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x01,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x83,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mac_f32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xef,0x01,0x00]
-
-v_mac_f32_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x20]
-
-v_mac_f32_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x40]
-
-v_mac_f32_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x60]
-
-v_mac_f32_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x16,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f32_e64 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x08]
-
-v_mac_f32_e64 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x10]
-
-v_mac_f32_e64 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x18]
-
-v_madmk_f32 v5, v1, 0x11213141, v3
-// CHECK: [0x01,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v255, v1, 0x11213141, v3
-// CHECK: [0x01,0x07,0xfe,0x2f,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, v255, 0x11213141, v3
-// CHECK: [0xff,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, 0, 0x11213141, v3
-// CHECK: [0x80,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, -1, 0x11213141, v3
-// CHECK: [0xc1,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, 0.5, 0x11213141, v3
-// CHECK: [0xf0,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, -4.0, 0x11213141, v3
-// CHECK: [0xf7,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
-
-v_madmk_f32 v5, v1, 0xa1b1c1d1, v3
-// CHECK: [0x01,0x07,0x0a,0x2e,0xd1,0xc1,0xb1,0xa1]
-
-v_madmk_f32 v5, v1, 0x11213141, v255
-// CHECK: [0x01,0xff,0x0b,0x2e,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v2, 0x11213141
-// CHECK: [0x01,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v255, v1, v2, 0x11213141
-// CHECK: [0x01,0x05,0xfe,0x31,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v255, v2, 0x11213141
-// CHECK: [0xff,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, 0, v2, 0x11213141
-// CHECK: [0x80,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, -1, v2, 0x11213141
-// CHECK: [0xc1,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, 0.5, v2, 0x11213141
-// CHECK: [0xf0,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, -4.0, v2, 0x11213141
-// CHECK: [0xf7,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v255, 0x11213141
-// CHECK: [0x01,0xff,0x0b,0x30,0x41,0x31,0x21,0x11]
-
-v_madak_f32 v5, v1, v2, 0xa1b1c1d1
-// CHECK: [0x01,0x05,0x0a,0x30,0xd1,0xc1,0xb1,0xa1]
-
-v_add_co_u32 v5, vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x32]
-
-v_add_co_u32 v255, vcc, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x33]
-
-v_add_co_u32 v5, vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x32]
-
-v_add_co_u32 v5, vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x32,0x56,0x34,0x12,0xaf]
-
-v_add_co_u32 v5, vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x32,0x73,0x72,0x71,0x3f]
-
-v_add_co_u32 v5, vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x32]
-
-v_add_co_u32_e64 v5, s[12:13], v1, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_co_u32_e64 v255, s[12:13], v1, v2
-// CHECK: [0xff,0x0c,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[14:15], v1, v2
-// CHECK: [0x05,0x0e,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[100:101], v1, v2
-// CHECK: [0x05,0x64,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_co_u32_e64 v5, flat_scratch, v1, v2
-// CHECK: [0x05,0x66,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_co_u32_e64 v5, vcc, v1, v2
-// CHECK: [0x05,0x6a,0x19,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v255, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0xff,0x05,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], s1, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], s101, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x65,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], flat_scratch_lo, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x66,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], flat_scratch_hi, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x67,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], vcc_lo, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x6a,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], vcc_hi, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x6b,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], m0, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x7c,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], exec_lo, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x7e,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], exec_hi, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x7f,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], 0, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x80,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], -1, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0xc1,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], 0.5, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0xf0,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], -4.0, v2
-// CHECK: [0x05,0x0c,0x19,0xd1,0xf7,0x04,0x02,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, v255
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xff,0x03,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, s2
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x05,0x00,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, s101
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcb,0x00,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, flat_scratch_lo
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcd,0x00,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, flat_scratch_hi
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcf,0x00,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, vcc_lo
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd5,0x00,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, vcc_hi
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd7,0x00,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, m0
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf9,0x00,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, exec_lo
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xfd,0x00,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, exec_hi
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xff,0x00,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, 0
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x01,0x01,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, -1
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x83,0x01,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, 0.5
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xe1,0x01,0x00]
-
-v_add_co_u32_e64 v5, s[12:13], v1, -4.0
-// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xef,0x01,0x00]
-
-v_sub_co_u32 v5, vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x34]
-
-v_sub_co_u32 v255, vcc, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x35]
-
-v_sub_co_u32 v5, vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x34]
-
-v_sub_co_u32 v5, vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x34,0x56,0x34,0x12,0xaf]
-
-v_sub_co_u32 v5, vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x34,0x73,0x72,0x71,0x3f]
-
-v_sub_co_u32 v5, vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x34]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_co_u32_e64 v255, s[12:13], v1, v2
-// CHECK: [0xff,0x0c,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[14:15], v1, v2
-// CHECK: [0x05,0x0e,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[100:101], v1, v2
-// CHECK: [0x05,0x64,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_co_u32_e64 v5, flat_scratch, v1, v2
-// CHECK: [0x05,0x66,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_co_u32_e64 v5, vcc, v1, v2
-// CHECK: [0x05,0x6a,0x1a,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v255, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0xff,0x05,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], s1, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], s101, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x65,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], flat_scratch_lo, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x66,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], flat_scratch_hi, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x67,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], vcc_lo, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], vcc_hi, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x6b,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], m0, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x7c,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], exec_lo, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], exec_hi, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x7f,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], 0, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x80,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], -1, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], 0.5, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0xf0,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], -4.0, v2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0xf7,0x04,0x02,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, v255
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xff,0x03,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, s2
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x05,0x00,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, s101
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcb,0x00,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, flat_scratch_lo
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcd,0x00,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, flat_scratch_hi
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcf,0x00,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, vcc_lo
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, vcc_hi
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd7,0x00,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, m0
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf9,0x00,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, exec_lo
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, exec_hi
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xff,0x00,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, 0
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x01,0x01,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, -1
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, 0.5
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xe1,0x01,0x00]
-
-v_sub_co_u32_e64 v5, s[12:13], v1, -4.0
-// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xef,0x01,0x00]
-
-v_subrev_co_u32 v5, vcc, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x36]
-
-v_subrev_co_u32 v255, vcc, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x37]
-
-v_subrev_co_u32 v5, vcc, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x36]
-
-v_subrev_co_u32 v5, vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x36,0x56,0x34,0x12,0xaf]
-
-v_subrev_co_u32 v5, vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x36,0x73,0x72,0x71,0x3f]
-
-v_subrev_co_u32 v5, vcc, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x36]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_co_u32_e64 v255, s[12:13], v1, v2
-// CHECK: [0xff,0x0c,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[14:15], v1, v2
-// CHECK: [0x05,0x0e,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[100:101], v1, v2
-// CHECK: [0x05,0x64,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, flat_scratch, v1, v2
-// CHECK: [0x05,0x66,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, vcc, v1, v2
-// CHECK: [0x05,0x6a,0x1b,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v255, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0xff,0x05,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], s1, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], s101, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x65,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], flat_scratch_lo, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x66,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], flat_scratch_hi, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x67,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], vcc_lo, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x6a,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], vcc_hi, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x6b,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], m0, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x7c,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], exec_lo, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x7e,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], exec_hi, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x7f,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], 0, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x80,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], -1, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0xc1,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], 0.5, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0xf0,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], -4.0, v2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0xf7,0x04,0x02,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, v255
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xff,0x03,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, s2
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x05,0x00,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, s101
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcb,0x00,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, flat_scratch_lo
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcd,0x00,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, flat_scratch_hi
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcf,0x00,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, vcc_lo
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd5,0x00,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, vcc_hi
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd7,0x00,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, m0
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf9,0x00,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, exec_lo
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xfd,0x00,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, exec_hi
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xff,0x00,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, 0
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x01,0x01,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, -1
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x83,0x01,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, 0.5
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xe1,0x01,0x00]
-
-v_subrev_co_u32_e64 v5, s[12:13], v1, -4.0
-// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xef,0x01,0x00]
-
-v_addc_co_u32 v5, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x38]
-
-v_addc_co_u32 v255, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x39]
-
-v_addc_co_u32 v5, vcc, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x38]
-
-v_addc_co_u32 v5, vcc, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x38]
-
-v_addc_co_u32 v5, vcc, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x38]
-
-v_addc_co_u32 v5, vcc, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x38]
-
-v_addc_co_u32 v5, vcc, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x38]
-
-v_addc_co_u32 v5, vcc, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x38]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_co_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: [0xff,0x0c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// CHECK: [0x05,0x0e,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, s[100:101], v1, v2, s[6:7]
-// CHECK: [0x05,0x64,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
-// CHECK: [0x05,0x66,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, vcc, v1, v2, s[6:7]
-// CHECK: [0x05,0x6a,0x1c,0xd1,0x01,0x05,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0xff,0x05,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x80,0x04,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0xc1,0x04,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0xf0,0x04,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0xf7,0x04,0x1a,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xff,0x1b,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x01,0x19,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x83,0x19,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xe1,0x19,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xef,0x19,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x22,0x00]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x92,0x01]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x9a,0x01]
-
-v_addc_co_u32_e64 v5, s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xaa,0x01]
-
-v_subb_co_u32 v5, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x3a]
-
-v_subb_co_u32 v255, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x3b]
-
-v_subb_co_u32 v5, vcc, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x3a]
-
-v_subb_co_u32 v5, vcc, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x3a]
-
-v_subb_co_u32 v5, vcc, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x3a]
-
-v_subb_co_u32 v5, vcc, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x3a]
-
-v_subb_co_u32 v5, vcc, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x3a]
-
-v_subb_co_u32 v5, vcc, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x3a]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_co_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: [0xff,0x0c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// CHECK: [0x05,0x0e,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, s[100:101], v1, v2, s[6:7]
-// CHECK: [0x05,0x64,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
-// CHECK: [0x05,0x66,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, vcc, v1, v2, s[6:7]
-// CHECK: [0x05,0x6a,0x1d,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0xff,0x05,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x80,0x04,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0xc1,0x04,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0xf0,0x04,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0xf7,0x04,0x1a,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xff,0x1b,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x01,0x19,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x83,0x19,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xe1,0x19,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xef,0x19,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x22,0x00]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x92,0x01]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x9a,0x01]
-
-v_subb_co_u32_e64 v5, s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xaa,0x01]
-
-v_subbrev_co_u32 v5, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0x0a,0x3c]
-
-v_subbrev_co_u32 v255, vcc, v1, v2, vcc
-// CHECK: [0x01,0x05,0xfe,0x3d]
-
-v_subbrev_co_u32 v5, vcc, v255, v2, vcc
-// CHECK: [0xff,0x05,0x0a,0x3c]
-
-v_subbrev_co_u32 v5, vcc, 0, v2, vcc
-// CHECK: [0x80,0x04,0x0a,0x3c]
-
-v_subbrev_co_u32 v5, vcc, -1, v2, vcc
-// CHECK: [0xc1,0x04,0x0a,0x3c]
-
-v_subbrev_co_u32 v5, vcc, 0.5, v2, vcc
-// CHECK: [0xf0,0x04,0x0a,0x3c]
-
-v_subbrev_co_u32 v5, vcc, -4.0, v2, vcc
-// CHECK: [0xf7,0x04,0x0a,0x3c]
-
-v_subbrev_co_u32 v5, vcc, v1, v255, vcc
-// CHECK: [0x01,0xff,0x0b,0x3c]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v255, s[12:13], v1, v2, s[6:7]
-// CHECK: [0xff,0x0c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, s[14:15], v1, v2, s[6:7]
-// CHECK: [0x05,0x0e,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, s[100:101], v1, v2, s[6:7]
-// CHECK: [0x05,0x64,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
-// CHECK: [0x05,0x66,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, vcc, v1, v2, s[6:7]
-// CHECK: [0x05,0x6a,0x1e,0xd1,0x01,0x05,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v255, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0xff,0x05,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], 0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x80,0x04,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], -1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0xc1,0x04,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0xf0,0x04,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0xf7,0x04,0x1a,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, v255, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xff,0x1b,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, 0, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x01,0x19,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, -1, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x83,0x19,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xe1,0x19,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xef,0x19,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x22,0x00]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x92,0x01]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x9a,0x01]
-
-v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xaa,0x01]
-
-v_add_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x3e]
-
-v_add_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x3f]
-
-v_add_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x3e]
-
-v_add_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x3e]
-
-v_add_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x3e]
-
-v_add_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x3e]
-
-v_add_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x3e]
-
-v_add_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x3e]
-
-v_add_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x3e]
-
-v_add_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x3e]
-
-v_add_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x3e]
-
-v_add_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x3e]
-
-v_add_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x3e]
-
-v_add_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x3e]
-
-v_add_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x3e]
-
-v_add_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x3e]
-
-v_add_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x3e,0x0b,0xfe,0x00,0x00]
-
-v_add_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x3e,0x56,0x34,0x00,0x00]
-
-v_add_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x3e]
-
-v_add_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0xff,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x65,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x66,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x67,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x6a,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x6b,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x7c,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x7e,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x7f,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x80,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0xc1,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0xf0,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0xf7,0x04,0x02,0x00]
-
-v_add_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xff,0x03,0x00]
-
-v_add_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x00,0x00]
-
-v_add_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcb,0x00,0x00]
-
-v_add_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcd,0x00,0x00]
-
-v_add_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcf,0x00,0x00]
-
-v_add_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd5,0x00,0x00]
-
-v_add_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd7,0x00,0x00]
-
-v_add_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf9,0x00,0x00]
-
-v_add_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xfd,0x00,0x00]
-
-v_add_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xff,0x00,0x00]
-
-v_add_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x01,0x01,0x00]
-
-v_add_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x83,0x01,0x00]
-
-v_add_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xe1,0x01,0x00]
-
-v_add_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xef,0x01,0x00]
-
-v_add_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x20]
-
-v_add_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x40]
-
-v_add_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x60]
-
-v_add_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x1f,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x40]
-
-v_sub_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x41]
-
-v_sub_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x40]
-
-v_sub_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x40]
-
-v_sub_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x40]
-
-v_sub_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x40]
-
-v_sub_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x40]
-
-v_sub_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x40]
-
-v_sub_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x40]
-
-v_sub_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x40]
-
-v_sub_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x40]
-
-v_sub_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x40]
-
-v_sub_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x40]
-
-v_sub_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x40]
-
-v_sub_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x40]
-
-v_sub_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x40]
-
-v_sub_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x40,0x0b,0xfe,0x00,0x00]
-
-v_sub_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x40,0x56,0x34,0x00,0x00]
-
-v_sub_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x40]
-
-v_sub_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0xff,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x65,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x66,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x67,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x6a,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x6b,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x7c,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x7e,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x7f,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x80,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0xc1,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0xf0,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0xf7,0x04,0x02,0x00]
-
-v_sub_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xff,0x03,0x00]
-
-v_sub_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcb,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcd,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcf,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd5,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd7,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf9,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xfd,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xff,0x00,0x00]
-
-v_sub_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x01,0x01,0x00]
-
-v_sub_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xe1,0x01,0x00]
-
-v_sub_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xef,0x01,0x00]
-
-v_sub_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x20]
-
-v_sub_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x40]
-
-v_sub_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x60]
-
-v_sub_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x20,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x42]
-
-v_subrev_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x43]
-
-v_subrev_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x42]
-
-v_subrev_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x42]
-
-v_subrev_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x42,0x0b,0xfe,0x00,0x00]
-
-v_subrev_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x42,0x56,0x34,0x00,0x00]
-
-v_subrev_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x42]
-
-v_subrev_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0xff,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x65,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x66,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x67,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x6a,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x6b,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x7c,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x7e,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x7f,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x80,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0xc1,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0xf0,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0xf7,0x04,0x02,0x00]
-
-v_subrev_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xff,0x03,0x00]
-
-v_subrev_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcb,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcd,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcf,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd5,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd7,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf9,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xfd,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xff,0x00,0x00]
-
-v_subrev_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x01,0x01,0x00]
-
-v_subrev_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x83,0x01,0x00]
-
-v_subrev_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xe1,0x01,0x00]
-
-v_subrev_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xef,0x01,0x00]
-
-v_subrev_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x20]
-
-v_subrev_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x40]
-
-v_subrev_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x60]
-
-v_subrev_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x21,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x44]
-
-v_mul_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x45]
-
-v_mul_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x44]
-
-v_mul_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x44]
-
-v_mul_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x44]
-
-v_mul_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x44]
-
-v_mul_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x44]
-
-v_mul_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x44]
-
-v_mul_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x44]
-
-v_mul_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x44]
-
-v_mul_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x44]
-
-v_mul_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x44]
-
-v_mul_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x44]
-
-v_mul_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x44]
-
-v_mul_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x44]
-
-v_mul_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x44]
-
-v_mul_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x44,0x0b,0xfe,0x00,0x00]
-
-v_mul_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x44,0x56,0x34,0x00,0x00]
-
-v_mul_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x44]
-
-v_mul_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mul_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mul_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xef,0x01,0x00]
-
-v_mul_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x20]
-
-v_mul_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x40]
-
-v_mul_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x60]
-
-v_mul_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x22,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x46]
-
-v_mac_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x47]
-
-v_mac_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x46]
-
-v_mac_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x46]
-
-v_mac_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x46]
-
-v_mac_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x46]
-
-v_mac_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x46]
-
-v_mac_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x46]
-
-v_mac_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x46]
-
-v_mac_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x46]
-
-v_mac_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x46]
-
-v_mac_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x46]
-
-v_mac_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x46]
-
-v_mac_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x46]
-
-v_mac_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x46]
-
-v_mac_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x46]
-
-v_mac_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x46,0x0b,0xfe,0x00,0x00]
-
-v_mac_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x46,0x56,0x34,0x00,0x00]
-
-v_mac_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x46]
-
-v_mac_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0xff,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x65,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x66,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x67,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x80,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0xf0,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0xf7,0x04,0x02,0x00]
-
-v_mac_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xff,0x03,0x00]
-
-v_mac_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xff,0x00,0x00]
-
-v_mac_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x01,0x01,0x00]
-
-v_mac_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x83,0x01,0x00]
-
-v_mac_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xe1,0x01,0x00]
-
-v_mac_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xef,0x01,0x00]
-
-v_mac_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x20]
-
-v_mac_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x40]
-
-v_mac_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x60]
-
-v_mac_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_mac_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x23,0xd1,0x01,0x05,0x02,0x00]
-
-v_madmk_f16 v5, v1, 0x1121, v3
-// CHECK: [0x01,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v255, v1, 0x1121, v3
-// CHECK: [0x01,0x07,0xfe,0x49,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, v255, 0x1121, v3
-// CHECK: [0xff,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, 0, 0x1121, v3
-// CHECK: [0x80,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, -1, 0x1121, v3
-// CHECK: [0xc1,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, 0.5, 0x1121, v3
-// CHECK: [0xf0,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, -4.0, 0x1121, v3
-// CHECK: [0xf7,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
-
-v_madmk_f16 v5, v1, 0xa1b1, v3
-// CHECK: [0x01,0x07,0x0a,0x48,0xb1,0xa1,0x00,0x00]
-
-v_madmk_f16 v5, v1, 0x1121, v255
-// CHECK: [0x01,0xff,0x0b,0x48,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, v1, v2, 0x1121
-// CHECK: [0x01,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v255, v1, v2, 0x1121
-// CHECK: [0x01,0x05,0xfe,0x4b,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, v255, v2, 0x1121
-// CHECK: [0xff,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, 0, v2, 0x1121
-// CHECK: [0x80,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, -1, v2, 0x1121
-// CHECK: [0xc1,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, 0.5, v2, 0x1121
-// CHECK: [0xf0,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, -4.0, v2, 0x1121
-// CHECK: [0xf7,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, v1, v255, 0x1121
-// CHECK: [0x01,0xff,0x0b,0x4a,0x21,0x11,0x00,0x00]
-
-v_madak_f16 v5, v1, v2, 0xa1b1
-// CHECK: [0x01,0x05,0x0a,0x4a,0xb1,0xa1,0x00,0x00]
-
-v_add_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x4c]
-
-v_add_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x4d]
-
-v_add_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x4c]
-
-v_add_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x4c]
-
-v_add_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x4c]
-
-v_add_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x4c]
-
-v_add_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x4c]
-
-v_add_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x4c]
-
-v_add_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x4c]
-
-v_add_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x4c]
-
-v_add_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x4c]
-
-v_add_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x4c]
-
-v_add_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x4c]
-
-v_add_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x4c]
-
-v_add_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x4c,0x00,0x38,0x00,0x00]
-
-v_add_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x4c,0x00,0xc4,0x00,0x00]
-
-v_add_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x4c,0x0b,0xfe,0x00,0x00]
-
-v_add_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x4c,0x56,0x34,0x00,0x00]
-
-v_add_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x4c]
-
-v_add_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0xff,0x05,0x02,0x00]
-
-v_add_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x65,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x66,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x67,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x6a,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x6b,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x7c,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x7e,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x7f,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0x80,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x26,0xd1,0xc1,0x04,0x02,0x00]
-
-v_add_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xff,0x03,0x00]
-
-v_add_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x05,0x00,0x00]
-
-v_add_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcb,0x00,0x00]
-
-v_add_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcd,0x00,0x00]
-
-v_add_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcf,0x00,0x00]
-
-v_add_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd5,0x00,0x00]
-
-v_add_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd7,0x00,0x00]
-
-v_add_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf9,0x00,0x00]
-
-v_add_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xfd,0x00,0x00]
-
-v_add_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xff,0x00,0x00]
-
-v_add_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x01,0x01,0x00]
-
-v_add_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x4e]
-
-v_sub_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x4f]
-
-v_sub_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x4e]
-
-v_sub_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x4e]
-
-v_sub_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x4e,0x00,0x38,0x00,0x00]
-
-v_sub_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x4e,0x00,0xc4,0x00,0x00]
-
-v_sub_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x4e,0x0b,0xfe,0x00,0x00]
-
-v_sub_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x4e,0x56,0x34,0x00,0x00]
-
-v_sub_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x4e]
-
-v_sub_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x27,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0xff,0x05,0x02,0x00]
-
-v_sub_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x65,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x66,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x67,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x6a,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x6b,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x7c,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x7e,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x7f,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0x80,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x27,0xd1,0xc1,0x04,0x02,0x00]
-
-v_sub_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x03,0x00]
-
-v_sub_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x05,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcb,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcd,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcf,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd5,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd7,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf9,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xfd,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x00,0x00]
-
-v_sub_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x01,0x01,0x00]
-
-v_sub_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_subrev_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x50]
-
-v_subrev_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x51]
-
-v_subrev_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x50]
-
-v_subrev_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x50]
-
-v_subrev_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x50,0x00,0x38,0x00,0x00]
-
-v_subrev_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x50,0x00,0xc4,0x00,0x00]
-
-v_subrev_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x50,0x0b,0xfe,0x00,0x00]
-
-v_subrev_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x50,0x56,0x34,0x00,0x00]
-
-v_subrev_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x50]
-
-v_subrev_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0xff,0x05,0x02,0x00]
-
-v_subrev_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x65,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x66,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x67,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x6a,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x6b,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x7c,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x7e,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x7f,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0x80,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x28,0xd1,0xc1,0x04,0x02,0x00]
-
-v_subrev_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_subrev_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_subrev_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x03,0x00]
-
-v_subrev_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x05,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcb,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcd,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcf,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd5,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd7,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf9,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xfd,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x00,0x00]
-
-v_subrev_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x01,0x01,0x00]
-
-v_subrev_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_lo_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x52]
-
-v_mul_lo_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x53]
-
-v_mul_lo_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x52]
-
-v_mul_lo_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x52]
-
-v_mul_lo_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x52,0x00,0x38,0x00,0x00]
-
-v_mul_lo_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x52,0x00,0xc4,0x00,0x00]
-
-v_mul_lo_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x52,0x0b,0xfe,0x00,0x00]
-
-v_mul_lo_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x52,0x56,0x34,0x00,0x00]
-
-v_mul_lo_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x52]
-
-v_mul_lo_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x29,0xd1,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0xff,0x05,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x65,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x66,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x67,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x6a,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x6b,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x7c,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x7e,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x7f,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0x80,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x29,0xd1,0xc1,0x04,0x02,0x00]
-
-v_mul_lo_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_mul_lo_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_mul_lo_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x03,0x00]
-
-v_mul_lo_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x05,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcb,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcd,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcf,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd5,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd7,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf9,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xfd,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x00,0x00]
-
-v_mul_lo_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x01,0x01,0x00]
-
-v_mul_lo_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x83,0x01,0x00]
-
-v_mul_lo_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_mul_lo_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshlrev_b16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x54]
-
-v_lshlrev_b16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x55]
-
-v_lshlrev_b16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x54]
-
-v_lshlrev_b16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x54]
-
-v_lshlrev_b16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x54,0x00,0x38,0x00,0x00]
-
-v_lshlrev_b16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x54,0x00,0xc4,0x00,0x00]
-
-v_lshlrev_b16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x54,0x0b,0xfe,0x00,0x00]
-
-v_lshlrev_b16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x54,0x56,0x34,0x00,0x00]
-
-v_lshlrev_b16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x54]
-
-v_lshlrev_b16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x65,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x66,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x67,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2a,0xd1,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshlrev_b16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshlrev_b16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x03,0x00]
-
-v_lshlrev_b16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x05,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcb,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcd,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcf,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd7,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf9,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x00,0x00]
-
-v_lshlrev_b16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshlrev_b16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshrrev_b16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x56]
-
-v_lshrrev_b16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x57]
-
-v_lshrrev_b16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x56]
-
-v_lshrrev_b16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x56]
-
-v_lshrrev_b16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x56,0x00,0x38,0x00,0x00]
-
-v_lshrrev_b16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x56,0x00,0xc4,0x00,0x00]
-
-v_lshrrev_b16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x56,0x0b,0xfe,0x00,0x00]
-
-v_lshrrev_b16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x56,0x56,0x34,0x00,0x00]
-
-v_lshrrev_b16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x56]
-
-v_lshrrev_b16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2b,0xd1,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x65,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x66,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x67,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2b,0xd1,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshrrev_b16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshrrev_b16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x03,0x00]
-
-v_lshrrev_b16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x05,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcb,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcd,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcf,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd7,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf9,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x00,0x00]
-
-v_lshrrev_b16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_lshrrev_b16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_ashrrev_i16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x58]
-
-v_ashrrev_i16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x59]
-
-v_ashrrev_i16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x58]
-
-v_ashrrev_i16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x58]
-
-v_ashrrev_i16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x58,0x00,0x38,0x00,0x00]
-
-v_ashrrev_i16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x58,0x00,0xc4,0x00,0x00]
-
-v_ashrrev_i16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x58,0x0b,0xfe,0x00,0x00]
-
-v_ashrrev_i16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x58,0x56,0x34,0x00,0x00]
-
-v_ashrrev_i16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x58]
-
-v_ashrrev_i16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x65,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x66,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x67,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2c,0xd1,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_ashrrev_i16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_ashrrev_i16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x03,0x00]
-
-v_ashrrev_i16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x05,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcb,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcd,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcf,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd7,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf9,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x00,0x00]
-
-v_ashrrev_i16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_ashrrev_i16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x5a]
-
-v_max_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x5b]
-
-v_max_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x5a]
-
-v_max_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x5a]
-
-v_max_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x5a]
-
-v_max_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x5a]
-
-v_max_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x5a]
-
-v_max_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x5a]
-
-v_max_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x5a]
-
-v_max_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x5a]
-
-v_max_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x5a]
-
-v_max_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x5a]
-
-v_max_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x5a]
-
-v_max_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x5a]
-
-v_max_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x5a]
-
-v_max_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x5a]
-
-v_max_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x5a,0x0b,0xfe,0x00,0x00]
-
-v_max_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x5a,0x56,0x34,0x00,0x00]
-
-v_max_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x5a]
-
-v_max_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0xf0,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0xf7,0x04,0x02,0x00]
-
-v_max_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xe1,0x01,0x00]
-
-v_max_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xef,0x01,0x00]
-
-v_max_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x20]
-
-v_max_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x40]
-
-v_max_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x60]
-
-v_max_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x2d,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x5c]
-
-v_min_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x5d]
-
-v_min_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x5c]
-
-v_min_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x5c]
-
-v_min_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x5c]
-
-v_min_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x5c]
-
-v_min_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x5c]
-
-v_min_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x5c]
-
-v_min_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x5c]
-
-v_min_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x5c]
-
-v_min_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x5c]
-
-v_min_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x5c]
-
-v_min_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x5c]
-
-v_min_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x5c]
-
-v_min_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x5c]
-
-v_min_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x5c]
-
-v_min_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x5c,0x0b,0xfe,0x00,0x00]
-
-v_min_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x5c,0x56,0x34,0x00,0x00]
-
-v_min_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x5c]
-
-v_min_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0xf0,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0xf7,0x04,0x02,0x00]
-
-v_min_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xe1,0x01,0x00]
-
-v_min_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xef,0x01,0x00]
-
-v_min_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x20]
-
-v_min_f16_e64 v5, v1, -v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x40]
-
-v_min_f16_e64 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x60]
-
-v_min_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x2e,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x5e]
-
-v_max_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x5f]
-
-v_max_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x5e]
-
-v_max_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x5e]
-
-v_max_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x5e]
-
-v_max_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x5e]
-
-v_max_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x5e]
-
-v_max_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x5e]
-
-v_max_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x5e]
-
-v_max_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x5e]
-
-v_max_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x5e]
-
-v_max_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x5e]
-
-v_max_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x5e]
-
-v_max_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x5e]
-
-v_max_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x5e,0x00,0x38,0x00,0x00]
-
-v_max_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x5e,0x00,0xc4,0x00,0x00]
-
-v_max_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x5e,0x0b,0xfe,0x00,0x00]
-
-v_max_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x5e,0x56,0x34,0x00,0x00]
-
-v_max_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x5e]
-
-v_max_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x2f,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x2f,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_i16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x60]
-
-v_max_i16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x61]
-
-v_max_i16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x60]
-
-v_max_i16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x60]
-
-v_max_i16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x60]
-
-v_max_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x60]
-
-v_max_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x60]
-
-v_max_i16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x60]
-
-v_max_i16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x60]
-
-v_max_i16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x60]
-
-v_max_i16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x60]
-
-v_max_i16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x60]
-
-v_max_i16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x60]
-
-v_max_i16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x60]
-
-v_max_i16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x60,0x00,0x38,0x00,0x00]
-
-v_max_i16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x60,0x00,0xc4,0x00,0x00]
-
-v_max_i16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x60,0x0b,0xfe,0x00,0x00]
-
-v_max_i16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x60,0x56,0x34,0x00,0x00]
-
-v_max_i16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x60]
-
-v_max_i16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_i16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
-
-v_max_i16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0xff,0x05,0x02,0x00]
-
-v_max_i16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x65,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x66,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x67,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x6a,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x6b,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x7c,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x7e,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x7f,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0x80,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x30,0xd1,0xc1,0x04,0x02,0x00]
-
-v_max_i16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_i16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_i16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x03,0x00]
-
-v_max_i16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x05,0x00,0x00]
-
-v_max_i16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcb,0x00,0x00]
-
-v_max_i16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcd,0x00,0x00]
-
-v_max_i16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcf,0x00,0x00]
-
-v_max_i16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd5,0x00,0x00]
-
-v_max_i16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd7,0x00,0x00]
-
-v_max_i16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf9,0x00,0x00]
-
-v_max_i16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xfd,0x00,0x00]
-
-v_max_i16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x00,0x00]
-
-v_max_i16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x01,0x01,0x00]
-
-v_max_i16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x83,0x01,0x00]
-
-v_max_i16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_max_i16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_u16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x62]
-
-v_min_u16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x63]
-
-v_min_u16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x62]
-
-v_min_u16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x62]
-
-v_min_u16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x62]
-
-v_min_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x62]
-
-v_min_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x62]
-
-v_min_u16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x62]
-
-v_min_u16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x62]
-
-v_min_u16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x62]
-
-v_min_u16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x62]
-
-v_min_u16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x62]
-
-v_min_u16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x62]
-
-v_min_u16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x62]
-
-v_min_u16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x62,0x00,0x38,0x00,0x00]
-
-v_min_u16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x62,0x00,0xc4,0x00,0x00]
-
-v_min_u16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x62,0x0b,0xfe,0x00,0x00]
-
-v_min_u16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x62,0x56,0x34,0x00,0x00]
-
-v_min_u16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x62]
-
-v_min_u16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_u16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x31,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_u16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_u16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x31,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_u16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_u16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_u16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_u16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_u16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_u16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_u16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_u16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_u16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_u16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_u16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_u16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_u16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_u16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_u16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_u16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_i16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x64]
-
-v_min_i16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x65]
-
-v_min_i16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x64]
-
-v_min_i16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x64]
-
-v_min_i16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x64]
-
-v_min_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x64]
-
-v_min_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x64]
-
-v_min_i16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x64]
-
-v_min_i16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x64]
-
-v_min_i16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x64]
-
-v_min_i16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x64]
-
-v_min_i16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x64]
-
-v_min_i16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x64]
-
-v_min_i16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x64]
-
-v_min_i16 v5, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x64,0x00,0x38,0x00,0x00]
-
-v_min_i16 v5, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x0a,0x64,0x00,0xc4,0x00,0x00]
-
-v_min_i16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x64,0x0b,0xfe,0x00,0x00]
-
-v_min_i16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x64,0x56,0x34,0x00,0x00]
-
-v_min_i16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x64]
-
-v_min_i16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_i16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x32,0xd1,0x01,0x05,0x02,0x00]
-
-v_min_i16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0xff,0x05,0x02,0x00]
-
-v_min_i16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x65,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x66,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x67,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x6a,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x6b,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x7c,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x7e,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x7f,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0x80,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x32,0xd1,0xc1,0x04,0x02,0x00]
-
-v_min_i16_e64 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_i16_e64 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_i16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x03,0x00]
-
-v_min_i16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x05,0x00,0x00]
-
-v_min_i16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcb,0x00,0x00]
-
-v_min_i16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcd,0x00,0x00]
-
-v_min_i16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcf,0x00,0x00]
-
-v_min_i16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd5,0x00,0x00]
-
-v_min_i16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd7,0x00,0x00]
-
-v_min_i16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf9,0x00,0x00]
-
-v_min_i16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xfd,0x00,0x00]
-
-v_min_i16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x00,0x00]
-
-v_min_i16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x01,0x01,0x00]
-
-v_min_i16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x83,0x01,0x00]
-
-v_min_i16_e64 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_min_i16_e64 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_ldexp_f16 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x66]
-
-v_ldexp_f16 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x67]
-
-v_ldexp_f16 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x66]
-
-v_ldexp_f16 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x66]
-
-v_ldexp_f16 v5, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x0a,0x66,0x0b,0xfe,0x00,0x00]
-
-v_ldexp_f16 v5, 0x3456, v2
-// CHECK: [0xff,0x04,0x0a,0x66,0x56,0x34,0x00,0x00]
-
-v_ldexp_f16 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x66]
-
-v_ldexp_f16_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x33,0xd1,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0xff,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x65,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x66,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x67,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x6b,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x7c,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x7f,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x80,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f16_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xff,0x03,0x00]
-
-v_ldexp_f16_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcb,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcd,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xff,0x00,0x00]
-
-v_ldexp_f16_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x01,0x01,0x00]
-
-v_ldexp_f16_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x83,0x01,0x00]
-
-v_ldexp_f16_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f16_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xef,0x01,0x00]
-
-v_ldexp_f16_e64 v5, -v1, v2
-// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x02,0x20]
-
-v_ldexp_f16_e64 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x33,0xd1,0x01,0x05,0x02,0x00]
-
-v_ldexp_f16_e64 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x33,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x68]
-
-v_add_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x69]
-
-v_add_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x68]
-
-v_add_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x68]
-
-v_add_u32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x68]
-
-v_add_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x68]
-
-v_add_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x68]
-
-v_add_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x68]
-
-v_add_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x68]
-
-v_add_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x68]
-
-v_add_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x68]
-
-v_add_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x68]
-
-v_add_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x68]
-
-v_add_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x68]
-
-v_add_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x68]
-
-v_add_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x68]
-
-v_add_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x68,0x56,0x34,0x12,0xaf]
-
-v_add_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x68,0x73,0x72,0x71,0x3f]
-
-v_add_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x68]
-
-v_add_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x34,0xd1,0x01,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0xff,0x05,0x02,0x00]
-
-v_add_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x65,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x66,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x67,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x6a,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x6b,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x7c,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x7e,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x7f,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0x80,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0xc1,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0xf0,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x34,0xd1,0xf7,0x04,0x02,0x00]
-
-v_add_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xff,0x03,0x00]
-
-v_add_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x05,0x00,0x00]
-
-v_add_u32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xcb,0x00,0x00]
-
-v_add_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xcd,0x00,0x00]
-
-v_add_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xcf,0x00,0x00]
-
-v_add_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xd5,0x00,0x00]
-
-v_add_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xd7,0x00,0x00]
-
-v_add_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xf9,0x00,0x00]
-
-v_add_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xfd,0x00,0x00]
-
-v_add_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xff,0x00,0x00]
-
-v_add_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x01,0x01,0x00]
-
-v_add_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x83,0x01,0x00]
-
-v_add_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xe1,0x01,0x00]
-
-v_add_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xef,0x01,0x00]
-
-v_sub_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x6a]
-
-v_sub_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x6b]
-
-v_sub_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x6a]
-
-v_sub_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x6a]
-
-v_sub_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x6a,0x56,0x34,0x12,0xaf]
-
-v_sub_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x6a,0x73,0x72,0x71,0x3f]
-
-v_sub_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x6a]
-
-v_sub_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x35,0xd1,0x01,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0xff,0x05,0x02,0x00]
-
-v_sub_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x65,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x66,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x67,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x6a,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x6b,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x7c,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x7e,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x7f,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0x80,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0xc1,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0xf0,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x35,0xd1,0xf7,0x04,0x02,0x00]
-
-v_sub_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xff,0x03,0x00]
-
-v_sub_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x05,0x00,0x00]
-
-v_sub_u32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xcb,0x00,0x00]
-
-v_sub_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xcd,0x00,0x00]
-
-v_sub_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xcf,0x00,0x00]
-
-v_sub_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xd5,0x00,0x00]
-
-v_sub_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xd7,0x00,0x00]
-
-v_sub_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xf9,0x00,0x00]
-
-v_sub_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xfd,0x00,0x00]
-
-v_sub_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xff,0x00,0x00]
-
-v_sub_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x01,0x01,0x00]
-
-v_sub_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x83,0x01,0x00]
-
-v_sub_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xe1,0x01,0x00]
-
-v_sub_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xef,0x01,0x00]
-
-v_subrev_u32 v5, v1, v2
-// CHECK: [0x01,0x05,0x0a,0x6c]
-
-v_subrev_u32 v255, v1, v2
-// CHECK: [0x01,0x05,0xfe,0x6d]
-
-v_subrev_u32 v5, v255, v2
-// CHECK: [0xff,0x05,0x0a,0x6c]
-
-v_subrev_u32 v5, s1, v2
-// CHECK: [0x01,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, s101, v2
-// CHECK: [0x65,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, m0, v2
-// CHECK: [0x7c,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, exec_lo, v2
-// CHECK: [0x7e,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, exec_hi, v2
-// CHECK: [0x7f,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, 0, v2
-// CHECK: [0x80,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, -1, v2
-// CHECK: [0xc1,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, 0.5, v2
-// CHECK: [0xf0,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, -4.0, v2
-// CHECK: [0xf7,0x04,0x0a,0x6c]
-
-v_subrev_u32 v5, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x0a,0x6c,0x56,0x34,0x12,0xaf]
-
-v_subrev_u32 v5, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x0a,0x6c,0x73,0x72,0x71,0x3f]
-
-v_subrev_u32 v5, v1, v255
-// CHECK: [0x01,0xff,0x0b,0x6c]
-
-v_subrev_u32_e64 v5, v1, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v255, v1, v2
-// CHECK: [0xff,0x00,0x36,0xd1,0x01,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, v255, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0xff,0x05,0x02,0x00]
-
-v_subrev_u32_e64 v5, s1, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, s101, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x65,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x66,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x67,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x6a,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x6b,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, m0, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x7c,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x7e,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x7f,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, 0, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0x80,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, -1, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0xc1,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0xf0,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x36,0xd1,0xf7,0x04,0x02,0x00]
-
-v_subrev_u32_e64 v5, v1, v255
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xff,0x03,0x00]
-
-v_subrev_u32_e64 v5, v1, s2
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x05,0x00,0x00]
-
-v_subrev_u32_e64 v5, v1, s101
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xcb,0x00,0x00]
-
-v_subrev_u32_e64 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xcd,0x00,0x00]
-
-v_subrev_u32_e64 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xcf,0x00,0x00]
-
-v_subrev_u32_e64 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xd5,0x00,0x00]
-
-v_subrev_u32_e64 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xd7,0x00,0x00]
-
-v_subrev_u32_e64 v5, v1, m0
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xf9,0x00,0x00]
-
-v_subrev_u32_e64 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xfd,0x00,0x00]
-
-v_subrev_u32_e64 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xff,0x00,0x00]
-
-v_subrev_u32_e64 v5, v1, 0
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x01,0x01,0x00]
-
-v_subrev_u32_e64 v5, v1, -1
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x83,0x01,0x00]
-
-v_subrev_u32_e64 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xe1,0x01,0x00]
-
-v_subrev_u32_e64 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xef,0x01,0x00]
-
-v_mad_legacy_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_legacy_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_legacy_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_legacy_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_legacy_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_legacy_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_legacy_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_legacy_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_legacy_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_legacy_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x24]
-
-v_mad_legacy_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x44]
-
-v_mad_legacy_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x84]
-
-v_mad_legacy_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_mad_legacy_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_mad_legacy_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x14]
-
-v_mad_legacy_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_mad_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x24]
-
-v_mad_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x44]
-
-v_mad_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x84]
-
-v_mad_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_mad_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_mad_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x14]
-
-v_mad_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_mad_i32_i24 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_i32_i24 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_i32_i24 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_i32_i24 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_i32_i24 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_i32_i24 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_i32_i24 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_i32_i24 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_i32_i24 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_i32_i24 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_i32_i24 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_i32_i24 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_i32_i24 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_i32_i24 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_i32_i24 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_i32_i24 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_i32_i24 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_i32_i24 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_i32_i24 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_i32_i24 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_u32_u24 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_u32_u24 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_u32_u24 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_u32_u24 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_u32_u24 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_u32_u24 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_u32_u24 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_u32_u24 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_u32_u24 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_u32_u24 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_u32_u24 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_u32_u24 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_u32_u24 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_u32_u24 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_u32_u24 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_u32_u24 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_u32_u24 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_u32_u24 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_u32_u24 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cubeid_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cubeid_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cubeid_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cubeid_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cubeid_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x96,0x01]
-
-v_cubeid_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cubeid_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cubeid_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cubeid_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xae,0x01]
-
-v_cubeid_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cubeid_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cubeid_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cubeid_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x02,0x02]
-
-v_cubeid_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x06,0x03]
-
-v_cubeid_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cubeid_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xde,0x03]
-
-v_cubeid_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cubeid_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x44]
-
-v_cubeid_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x84]
-
-v_cubeid_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_cubeid_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubeid_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_cubeid_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x14]
-
-v_cubeid_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_cubesc_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cubesc_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cubesc_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cubesc_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cubesc_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cubesc_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x96,0x01]
-
-v_cubesc_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cubesc_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cubesc_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cubesc_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xae,0x01]
-
-v_cubesc_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cubesc_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cubesc_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cubesc_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x02,0x02]
-
-v_cubesc_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x06,0x03]
-
-v_cubesc_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cubesc_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xde,0x03]
-
-v_cubesc_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cubesc_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x44]
-
-v_cubesc_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x84]
-
-v_cubesc_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_cubesc_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubesc_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_cubesc_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x14]
-
-v_cubesc_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_cubetc_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cubetc_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cubetc_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cubetc_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cubetc_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cubetc_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x96,0x01]
-
-v_cubetc_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cubetc_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cubetc_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cubetc_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xae,0x01]
-
-v_cubetc_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cubetc_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cubetc_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cubetc_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x02,0x02]
-
-v_cubetc_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x06,0x03]
-
-v_cubetc_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cubetc_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xde,0x03]
-
-v_cubetc_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cubetc_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x44]
-
-v_cubetc_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x84]
-
-v_cubetc_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_cubetc_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubetc_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_cubetc_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x14]
-
-v_cubetc_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_cubema_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cubema_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cubema_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cubema_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cubema_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cubema_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cubema_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cubema_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cubema_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cubema_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cubema_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cubema_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cubema_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cubema_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cubema_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cubema_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cubema_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x96,0x01]
-
-v_cubema_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cubema_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cubema_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cubema_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xae,0x01]
-
-v_cubema_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cubema_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cubema_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cubema_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x02,0x02]
-
-v_cubema_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x06,0x03]
-
-v_cubema_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cubema_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xde,0x03]
-
-v_cubema_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cubema_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x44]
-
-v_cubema_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x84]
-
-v_cubema_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_cubema_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xc7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cubema_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_cubema_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x14]
-
-v_cubema_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_bfe_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfe_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfe_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0xff,0x05,0x0e,0x04]
-
-v_bfe_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x65,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x66,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x67,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x80,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_bfe_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xff,0x0f,0x04]
-
-v_bfe_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0c,0x04]
-
-v_bfe_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_bfe_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_bfe_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_bfe_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_bfe_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_bfe_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_bfe_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_bfe_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xff,0x0c,0x04]
-
-v_bfe_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x01,0x0d,0x04]
-
-v_bfe_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x83,0x0d,0x04]
-
-v_bfe_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_bfe_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xef,0x0d,0x04]
-
-v_bfe_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfe,0x07]
-
-v_bfe_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x00]
-
-v_bfe_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x96,0x01]
-
-v_bfe_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x9a,0x01]
-
-v_bfe_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x9e,0x01]
-
-v_bfe_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xaa,0x01]
-
-v_bfe_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xae,0x01]
-
-v_bfe_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xf2,0x01]
-
-v_bfe_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfa,0x01]
-
-v_bfe_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfe,0x01]
-
-v_bfe_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x02,0x02]
-
-v_bfe_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x06,0x03]
-
-v_bfe_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xc2,0x03]
-
-v_bfe_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xde,0x03]
-
-v_bfe_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfe_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfe_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0xff,0x05,0x0e,0x04]
-
-v_bfe_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x65,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x66,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x67,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x80,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_bfe_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xff,0x0f,0x04]
-
-v_bfe_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0c,0x04]
-
-v_bfe_i32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_bfe_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_bfe_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_bfe_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_bfe_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_bfe_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_bfe_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_bfe_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xff,0x0c,0x04]
-
-v_bfe_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x01,0x0d,0x04]
-
-v_bfe_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x83,0x0d,0x04]
-
-v_bfe_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_bfe_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xef,0x0d,0x04]
-
-v_bfe_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfe,0x07]
-
-v_bfe_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x00]
-
-v_bfe_i32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x96,0x01]
-
-v_bfe_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x9a,0x01]
-
-v_bfe_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x9e,0x01]
-
-v_bfe_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xaa,0x01]
-
-v_bfe_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xae,0x01]
-
-v_bfe_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xf2,0x01]
-
-v_bfe_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfa,0x01]
-
-v_bfe_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfe,0x01]
-
-v_bfe_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x02,0x02]
-
-v_bfe_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x06,0x03]
-
-v_bfe_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xc2,0x03]
-
-v_bfe_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xde,0x03]
-
-v_bfi_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfi_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xca,0xd1,0x01,0x05,0x0e,0x04]
-
-v_bfi_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0xff,0x05,0x0e,0x04]
-
-v_bfi_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x65,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x66,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x67,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x80,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_bfi_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xff,0x0f,0x04]
-
-v_bfi_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0c,0x04]
-
-v_bfi_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_bfi_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_bfi_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_bfi_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_bfi_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_bfi_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_bfi_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_bfi_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xff,0x0c,0x04]
-
-v_bfi_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x01,0x0d,0x04]
-
-v_bfi_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x83,0x0d,0x04]
-
-v_bfi_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_bfi_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xef,0x0d,0x04]
-
-v_bfi_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfe,0x07]
-
-v_bfi_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0e,0x00]
-
-v_bfi_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x96,0x01]
-
-v_bfi_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x9a,0x01]
-
-v_bfi_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x9e,0x01]
-
-v_bfi_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xaa,0x01]
-
-v_bfi_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xae,0x01]
-
-v_bfi_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xf2,0x01]
-
-v_bfi_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfa,0x01]
-
-v_bfi_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfe,0x01]
-
-v_bfi_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x02,0x02]
-
-v_bfi_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x06,0x03]
-
-v_bfi_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xc2,0x03]
-
-v_bfi_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xde,0x03]
-
-v_fma_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0xff,0x05,0x0e,0x04]
-
-v_fma_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x04,0x0e,0x04]
-
-v_fma_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x65,0x04,0x0e,0x04]
-
-v_fma_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x66,0x04,0x0e,0x04]
-
-v_fma_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x67,0x04,0x0e,0x04]
-
-v_fma_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_fma_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_fma_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_fma_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_fma_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_fma_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x80,0x04,0x0e,0x04]
-
-v_fma_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_fma_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_fma_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_fma_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xff,0x0f,0x04]
-
-v_fma_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0c,0x04]
-
-v_fma_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_fma_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_fma_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_fma_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_fma_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_fma_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_fma_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_fma_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xff,0x0c,0x04]
-
-v_fma_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x01,0x0d,0x04]
-
-v_fma_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x83,0x0d,0x04]
-
-v_fma_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_fma_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xef,0x0d,0x04]
-
-v_fma_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfe,0x07]
-
-v_fma_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x00]
-
-v_fma_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x96,0x01]
-
-v_fma_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x9a,0x01]
-
-v_fma_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x9e,0x01]
-
-v_fma_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xaa,0x01]
-
-v_fma_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xae,0x01]
-
-v_fma_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xf2,0x01]
-
-v_fma_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfa,0x01]
-
-v_fma_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfe,0x01]
-
-v_fma_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x02,0x02]
-
-v_fma_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x06,0x03]
-
-v_fma_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xc2,0x03]
-
-v_fma_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xde,0x03]
-
-v_fma_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x24]
-
-v_fma_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x44]
-
-v_fma_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x84]
-
-v_fma_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_fma_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xcb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_fma_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x14]
-
-v_fma_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[2:3], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x02,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[4:5], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x04,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], s[100:101], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x64,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x66,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], exec, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x80,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfd,0x0f,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[4:5], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x09,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[6:7], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x0d,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], s[100:101], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xc9,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], exec, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_fma_f64 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x01,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x83,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xef,0x0d,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xfa,0x07]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[6:7]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x1a,0x00]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[8:9]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x22,0x00]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], s[100:101]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x92,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], flat_scratch
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x9a,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xaa,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], exec
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xfa,0x01]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], 0
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x02,0x02]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -1
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x06,0x03]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xc2,0x03]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xde,0x03]
-
-v_fma_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x24]
-
-v_fma_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x44]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x84]
-
-v_fma_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_fma_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// CHECK: [0x05,0x01,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// CHECK: [0x05,0x02,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// CHECK: [0x05,0x04,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// CHECK: [0x05,0x07,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// CHECK: [0x05,0x80,0xcc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x14]
-
-v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_lerp_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_lerp_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_lerp_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0xff,0x05,0x0e,0x04]
-
-v_lerp_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x65,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x66,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x67,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x80,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_lerp_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xff,0x0f,0x04]
-
-v_lerp_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0c,0x04]
-
-v_lerp_u8 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_lerp_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_lerp_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_lerp_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_lerp_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_lerp_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_lerp_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_lerp_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xff,0x0c,0x04]
-
-v_lerp_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x01,0x0d,0x04]
-
-v_lerp_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x83,0x0d,0x04]
-
-v_lerp_u8 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_lerp_u8 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xef,0x0d,0x04]
-
-v_lerp_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfe,0x07]
-
-v_lerp_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x00]
-
-v_lerp_u8 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x96,0x01]
-
-v_lerp_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x9a,0x01]
-
-v_lerp_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x9e,0x01]
-
-v_lerp_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xaa,0x01]
-
-v_lerp_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xae,0x01]
-
-v_lerp_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xf2,0x01]
-
-v_lerp_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfa,0x01]
-
-v_lerp_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfe,0x01]
-
-v_lerp_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x02,0x02]
-
-v_lerp_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x06,0x03]
-
-v_lerp_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xc2,0x03]
-
-v_lerp_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xde,0x03]
-
-v_alignbit_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0e,0x04]
-
-v_alignbit_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xce,0xd1,0x01,0x05,0x0e,0x04]
-
-v_alignbit_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0xff,0x05,0x0e,0x04]
-
-v_alignbit_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x65,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x66,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x67,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_alignbit_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xff,0x0f,0x04]
-
-v_alignbit_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xff,0x0c,0x04]
-
-v_alignbit_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x07]
-
-v_alignbit_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0e,0x00]
-
-v_alignbit_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x96,0x01]
-
-v_alignbit_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x9a,0x01]
-
-v_alignbit_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x9e,0x01]
-
-v_alignbit_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xaa,0x01]
-
-v_alignbit_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xae,0x01]
-
-v_alignbit_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xf2,0x01]
-
-v_alignbit_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfa,0x01]
-
-v_alignbit_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x01]
-
-v_alignbyte_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0xff,0x05,0x0e,0x04]
-
-v_alignbyte_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x65,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x66,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x67,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_alignbyte_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xff,0x0f,0x04]
-
-v_alignbyte_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xff,0x0c,0x04]
-
-v_alignbyte_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x07]
-
-v_alignbyte_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x00]
-
-v_alignbyte_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x96,0x01]
-
-v_alignbyte_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x9a,0x01]
-
-v_alignbyte_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x9e,0x01]
-
-v_alignbyte_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xaa,0x01]
-
-v_alignbyte_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xae,0x01]
-
-v_alignbyte_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xf2,0x01]
-
-v_alignbyte_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfa,0x01]
-
-v_alignbyte_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0xff,0x05,0x0e,0x04]
-
-v_min3_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x04,0x0e,0x04]
-
-v_min3_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x65,0x04,0x0e,0x04]
-
-v_min3_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x66,0x04,0x0e,0x04]
-
-v_min3_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x67,0x04,0x0e,0x04]
-
-v_min3_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_min3_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_min3_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_min3_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_min3_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_min3_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x80,0x04,0x0e,0x04]
-
-v_min3_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_min3_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_min3_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_min3_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xff,0x0f,0x04]
-
-v_min3_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0c,0x04]
-
-v_min3_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_min3_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_min3_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_min3_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_min3_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_min3_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_min3_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_min3_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xff,0x0c,0x04]
-
-v_min3_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x01,0x0d,0x04]
-
-v_min3_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x83,0x0d,0x04]
-
-v_min3_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_min3_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xef,0x0d,0x04]
-
-v_min3_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfe,0x07]
-
-v_min3_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x00]
-
-v_min3_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x96,0x01]
-
-v_min3_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x9a,0x01]
-
-v_min3_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x9e,0x01]
-
-v_min3_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xaa,0x01]
-
-v_min3_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xae,0x01]
-
-v_min3_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xf2,0x01]
-
-v_min3_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfa,0x01]
-
-v_min3_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x02,0x02]
-
-v_min3_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x06,0x03]
-
-v_min3_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xc2,0x03]
-
-v_min3_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xde,0x03]
-
-v_min3_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x24]
-
-v_min3_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x44]
-
-v_min3_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x84]
-
-v_min3_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_min3_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xd0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_min3_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x14]
-
-v_min3_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_min3_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0xff,0x05,0x0e,0x04]
-
-v_min3_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x04,0x0e,0x04]
-
-v_min3_i32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x65,0x04,0x0e,0x04]
-
-v_min3_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x66,0x04,0x0e,0x04]
-
-v_min3_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x67,0x04,0x0e,0x04]
-
-v_min3_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_min3_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_min3_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_min3_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_min3_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_min3_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x80,0x04,0x0e,0x04]
-
-v_min3_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_min3_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_min3_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_min3_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xff,0x0f,0x04]
-
-v_min3_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0c,0x04]
-
-v_min3_i32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_min3_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_min3_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_min3_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_min3_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_min3_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_min3_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_min3_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xff,0x0c,0x04]
-
-v_min3_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x01,0x0d,0x04]
-
-v_min3_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x83,0x0d,0x04]
-
-v_min3_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_min3_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xef,0x0d,0x04]
-
-v_min3_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfe,0x07]
-
-v_min3_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x00]
-
-v_min3_i32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x96,0x01]
-
-v_min3_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x9a,0x01]
-
-v_min3_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x9e,0x01]
-
-v_min3_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xaa,0x01]
-
-v_min3_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xae,0x01]
-
-v_min3_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xf2,0x01]
-
-v_min3_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfa,0x01]
-
-v_min3_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x02,0x02]
-
-v_min3_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x06,0x03]
-
-v_min3_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xc2,0x03]
-
-v_min3_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xde,0x03]
-
-v_min3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0xff,0x05,0x0e,0x04]
-
-v_min3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x04,0x0e,0x04]
-
-v_min3_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x65,0x04,0x0e,0x04]
-
-v_min3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x66,0x04,0x0e,0x04]
-
-v_min3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x67,0x04,0x0e,0x04]
-
-v_min3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_min3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_min3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_min3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_min3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_min3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x80,0x04,0x0e,0x04]
-
-v_min3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_min3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_min3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_min3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xff,0x0f,0x04]
-
-v_min3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0c,0x04]
-
-v_min3_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_min3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_min3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_min3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_min3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_min3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_min3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_min3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xff,0x0c,0x04]
-
-v_min3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x01,0x0d,0x04]
-
-v_min3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x83,0x0d,0x04]
-
-v_min3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_min3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xef,0x0d,0x04]
-
-v_min3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfe,0x07]
-
-v_min3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x00]
-
-v_min3_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x96,0x01]
-
-v_min3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x9a,0x01]
-
-v_min3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x9e,0x01]
-
-v_min3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xaa,0x01]
-
-v_min3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xae,0x01]
-
-v_min3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xf2,0x01]
-
-v_min3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfa,0x01]
-
-v_min3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x02,0x02]
-
-v_min3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x06,0x03]
-
-v_min3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xc2,0x03]
-
-v_min3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xde,0x03]
-
-v_max3_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0xff,0x05,0x0e,0x04]
-
-v_max3_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x04,0x0e,0x04]
-
-v_max3_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x65,0x04,0x0e,0x04]
-
-v_max3_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x66,0x04,0x0e,0x04]
-
-v_max3_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x67,0x04,0x0e,0x04]
-
-v_max3_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_max3_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_max3_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_max3_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_max3_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_max3_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x80,0x04,0x0e,0x04]
-
-v_max3_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_max3_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_max3_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_max3_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xff,0x0f,0x04]
-
-v_max3_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0c,0x04]
-
-v_max3_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_max3_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_max3_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_max3_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_max3_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_max3_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_max3_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_max3_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xff,0x0c,0x04]
-
-v_max3_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x01,0x0d,0x04]
-
-v_max3_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x83,0x0d,0x04]
-
-v_max3_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_max3_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xef,0x0d,0x04]
-
-v_max3_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfe,0x07]
-
-v_max3_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x00]
-
-v_max3_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x96,0x01]
-
-v_max3_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x9a,0x01]
-
-v_max3_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x9e,0x01]
-
-v_max3_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xaa,0x01]
-
-v_max3_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xae,0x01]
-
-v_max3_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xf2,0x01]
-
-v_max3_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfa,0x01]
-
-v_max3_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfe,0x01]
-
-v_max3_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x02,0x02]
-
-v_max3_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x06,0x03]
-
-v_max3_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xc2,0x03]
-
-v_max3_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xde,0x03]
-
-v_max3_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x24]
-
-v_max3_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x44]
-
-v_max3_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x84]
-
-v_max3_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_max3_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xd3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_max3_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x14]
-
-v_max3_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_max3_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0xff,0x05,0x0e,0x04]
-
-v_max3_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x04,0x0e,0x04]
-
-v_max3_i32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x65,0x04,0x0e,0x04]
-
-v_max3_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x66,0x04,0x0e,0x04]
-
-v_max3_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x67,0x04,0x0e,0x04]
-
-v_max3_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_max3_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_max3_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_max3_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_max3_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_max3_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x80,0x04,0x0e,0x04]
-
-v_max3_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_max3_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_max3_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_max3_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xff,0x0f,0x04]
-
-v_max3_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0c,0x04]
-
-v_max3_i32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_max3_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_max3_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_max3_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_max3_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_max3_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_max3_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_max3_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xff,0x0c,0x04]
-
-v_max3_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x01,0x0d,0x04]
-
-v_max3_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x83,0x0d,0x04]
-
-v_max3_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_max3_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xef,0x0d,0x04]
-
-v_max3_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfe,0x07]
-
-v_max3_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x00]
-
-v_max3_i32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x96,0x01]
-
-v_max3_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x9a,0x01]
-
-v_max3_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x9e,0x01]
-
-v_max3_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xaa,0x01]
-
-v_max3_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xae,0x01]
-
-v_max3_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xf2,0x01]
-
-v_max3_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfa,0x01]
-
-v_max3_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfe,0x01]
-
-v_max3_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x02,0x02]
-
-v_max3_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x06,0x03]
-
-v_max3_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xc2,0x03]
-
-v_max3_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xde,0x03]
-
-v_max3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0xff,0x05,0x0e,0x04]
-
-v_max3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x04,0x0e,0x04]
-
-v_max3_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x65,0x04,0x0e,0x04]
-
-v_max3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x66,0x04,0x0e,0x04]
-
-v_max3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x67,0x04,0x0e,0x04]
-
-v_max3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_max3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_max3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_max3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_max3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_max3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x80,0x04,0x0e,0x04]
-
-v_max3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_max3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_max3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_max3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xff,0x0f,0x04]
-
-v_max3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0c,0x04]
-
-v_max3_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_max3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_max3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_max3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_max3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_max3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_max3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_max3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xff,0x0c,0x04]
-
-v_max3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x01,0x0d,0x04]
-
-v_max3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x83,0x0d,0x04]
-
-v_max3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_max3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xef,0x0d,0x04]
-
-v_max3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfe,0x07]
-
-v_max3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x00]
-
-v_max3_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x96,0x01]
-
-v_max3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x9a,0x01]
-
-v_max3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x9e,0x01]
-
-v_max3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xaa,0x01]
-
-v_max3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xae,0x01]
-
-v_max3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xf2,0x01]
-
-v_max3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfa,0x01]
-
-v_max3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfe,0x01]
-
-v_max3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x02,0x02]
-
-v_max3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x06,0x03]
-
-v_max3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xc2,0x03]
-
-v_max3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xde,0x03]
-
-v_med3_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0xff,0x05,0x0e,0x04]
-
-v_med3_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x04,0x0e,0x04]
-
-v_med3_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x65,0x04,0x0e,0x04]
-
-v_med3_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x66,0x04,0x0e,0x04]
-
-v_med3_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x67,0x04,0x0e,0x04]
-
-v_med3_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_med3_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_med3_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_med3_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_med3_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_med3_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x80,0x04,0x0e,0x04]
-
-v_med3_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_med3_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_med3_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_med3_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xff,0x0f,0x04]
-
-v_med3_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0c,0x04]
-
-v_med3_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_med3_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_med3_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_med3_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_med3_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_med3_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_med3_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_med3_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xff,0x0c,0x04]
-
-v_med3_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x01,0x0d,0x04]
-
-v_med3_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x83,0x0d,0x04]
-
-v_med3_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_med3_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xef,0x0d,0x04]
-
-v_med3_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfe,0x07]
-
-v_med3_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x00]
-
-v_med3_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x96,0x01]
-
-v_med3_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x9a,0x01]
-
-v_med3_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x9e,0x01]
-
-v_med3_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xaa,0x01]
-
-v_med3_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xae,0x01]
-
-v_med3_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xf2,0x01]
-
-v_med3_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfa,0x01]
-
-v_med3_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfe,0x01]
-
-v_med3_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x02,0x02]
-
-v_med3_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x06,0x03]
-
-v_med3_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xc2,0x03]
-
-v_med3_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xde,0x03]
-
-v_med3_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x24]
-
-v_med3_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x44]
-
-v_med3_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x84]
-
-v_med3_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_med3_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xd6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_med3_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x14]
-
-v_med3_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_med3_i32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0xff,0x05,0x0e,0x04]
-
-v_med3_i32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x04,0x0e,0x04]
-
-v_med3_i32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x65,0x04,0x0e,0x04]
-
-v_med3_i32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x66,0x04,0x0e,0x04]
-
-v_med3_i32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x67,0x04,0x0e,0x04]
-
-v_med3_i32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_med3_i32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_med3_i32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_med3_i32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_med3_i32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_med3_i32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x80,0x04,0x0e,0x04]
-
-v_med3_i32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_med3_i32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_med3_i32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_med3_i32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xff,0x0f,0x04]
-
-v_med3_i32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0c,0x04]
-
-v_med3_i32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_med3_i32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_med3_i32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_med3_i32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_med3_i32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_med3_i32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_med3_i32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_med3_i32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xff,0x0c,0x04]
-
-v_med3_i32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x01,0x0d,0x04]
-
-v_med3_i32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x83,0x0d,0x04]
-
-v_med3_i32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_med3_i32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xef,0x0d,0x04]
-
-v_med3_i32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfe,0x07]
-
-v_med3_i32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x00]
-
-v_med3_i32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x96,0x01]
-
-v_med3_i32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x9a,0x01]
-
-v_med3_i32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x9e,0x01]
-
-v_med3_i32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xaa,0x01]
-
-v_med3_i32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xae,0x01]
-
-v_med3_i32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xf2,0x01]
-
-v_med3_i32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfa,0x01]
-
-v_med3_i32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfe,0x01]
-
-v_med3_i32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x02,0x02]
-
-v_med3_i32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x06,0x03]
-
-v_med3_i32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xc2,0x03]
-
-v_med3_i32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xde,0x03]
-
-v_med3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0xff,0x05,0x0e,0x04]
-
-v_med3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x04,0x0e,0x04]
-
-v_med3_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x65,0x04,0x0e,0x04]
-
-v_med3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x66,0x04,0x0e,0x04]
-
-v_med3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x67,0x04,0x0e,0x04]
-
-v_med3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_med3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_med3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_med3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_med3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_med3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x80,0x04,0x0e,0x04]
-
-v_med3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_med3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_med3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_med3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xff,0x0f,0x04]
-
-v_med3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0c,0x04]
-
-v_med3_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_med3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_med3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_med3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_med3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_med3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_med3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_med3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xff,0x0c,0x04]
-
-v_med3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x01,0x0d,0x04]
-
-v_med3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x83,0x0d,0x04]
-
-v_med3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_med3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xef,0x0d,0x04]
-
-v_med3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfe,0x07]
-
-v_med3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x00]
-
-v_med3_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x96,0x01]
-
-v_med3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x9a,0x01]
-
-v_med3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x9e,0x01]
-
-v_med3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xaa,0x01]
-
-v_med3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xae,0x01]
-
-v_med3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xf2,0x01]
-
-v_med3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfa,0x01]
-
-v_med3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfe,0x01]
-
-v_med3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x02,0x02]
-
-v_med3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x06,0x03]
-
-v_med3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xc2,0x03]
-
-v_med3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0xff,0x05,0x0e,0x04]
-
-v_sad_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x04,0x0e,0x04]
-
-v_sad_u8 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x65,0x04,0x0e,0x04]
-
-v_sad_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x66,0x04,0x0e,0x04]
-
-v_sad_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x67,0x04,0x0e,0x04]
-
-v_sad_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_sad_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_sad_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_sad_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_sad_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_sad_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x80,0x04,0x0e,0x04]
-
-v_sad_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_sad_u8 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_sad_u8 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_sad_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xff,0x0f,0x04]
-
-v_sad_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0c,0x04]
-
-v_sad_u8 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_sad_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_sad_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_sad_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_sad_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_sad_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_sad_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_sad_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xff,0x0c,0x04]
-
-v_sad_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x01,0x0d,0x04]
-
-v_sad_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x83,0x0d,0x04]
-
-v_sad_u8 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_sad_u8 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xef,0x0d,0x04]
-
-v_sad_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfe,0x07]
-
-v_sad_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x00]
-
-v_sad_u8 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x96,0x01]
-
-v_sad_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x9a,0x01]
-
-v_sad_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x9e,0x01]
-
-v_sad_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xaa,0x01]
-
-v_sad_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xae,0x01]
-
-v_sad_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xf2,0x01]
-
-v_sad_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfa,0x01]
-
-v_sad_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfe,0x01]
-
-v_sad_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x02,0x02]
-
-v_sad_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x06,0x03]
-
-v_sad_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xc2,0x03]
-
-v_sad_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_u8 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xd9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xda,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0xff,0x05,0x0e,0x04]
-
-v_sad_hi_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x65,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x66,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x67,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x80,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_sad_hi_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xff,0x0f,0x04]
-
-v_sad_hi_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xff,0x0c,0x04]
-
-v_sad_hi_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x01,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x83,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xef,0x0d,0x04]
-
-v_sad_hi_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfe,0x07]
-
-v_sad_hi_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0e,0x00]
-
-v_sad_hi_u8 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x96,0x01]
-
-v_sad_hi_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x9a,0x01]
-
-v_sad_hi_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x9e,0x01]
-
-v_sad_hi_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xaa,0x01]
-
-v_sad_hi_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xae,0x01]
-
-v_sad_hi_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xf2,0x01]
-
-v_sad_hi_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfa,0x01]
-
-v_sad_hi_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfe,0x01]
-
-v_sad_hi_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x02,0x02]
-
-v_sad_hi_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x06,0x03]
-
-v_sad_hi_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xc2,0x03]
-
-v_sad_hi_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_hi_u8 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xda,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0xff,0x05,0x0e,0x04]
-
-v_sad_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x04,0x0e,0x04]
-
-v_sad_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x65,0x04,0x0e,0x04]
-
-v_sad_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x66,0x04,0x0e,0x04]
-
-v_sad_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x67,0x04,0x0e,0x04]
-
-v_sad_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_sad_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_sad_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_sad_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_sad_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_sad_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x80,0x04,0x0e,0x04]
-
-v_sad_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_sad_u16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_sad_u16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_sad_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xff,0x0f,0x04]
-
-v_sad_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0c,0x04]
-
-v_sad_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_sad_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_sad_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_sad_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_sad_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_sad_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_sad_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_sad_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xff,0x0c,0x04]
-
-v_sad_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x01,0x0d,0x04]
-
-v_sad_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x83,0x0d,0x04]
-
-v_sad_u16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_sad_u16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xef,0x0d,0x04]
-
-v_sad_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfe,0x07]
-
-v_sad_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x00]
-
-v_sad_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x96,0x01]
-
-v_sad_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x9a,0x01]
-
-v_sad_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x9e,0x01]
-
-v_sad_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xaa,0x01]
-
-v_sad_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xae,0x01]
-
-v_sad_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xf2,0x01]
-
-v_sad_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfa,0x01]
-
-v_sad_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfe,0x01]
-
-v_sad_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x02,0x02]
-
-v_sad_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x06,0x03]
-
-v_sad_u16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xc2,0x03]
-
-v_sad_u16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_u16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xdb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_sad_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0xff,0x05,0x0e,0x04]
-
-v_sad_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x04,0x0e,0x04]
-
-v_sad_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x65,0x04,0x0e,0x04]
-
-v_sad_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x66,0x04,0x0e,0x04]
-
-v_sad_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x67,0x04,0x0e,0x04]
-
-v_sad_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_sad_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_sad_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_sad_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_sad_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_sad_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x80,0x04,0x0e,0x04]
-
-v_sad_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_sad_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_sad_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_sad_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xff,0x0f,0x04]
-
-v_sad_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0c,0x04]
-
-v_sad_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_sad_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_sad_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_sad_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_sad_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_sad_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_sad_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_sad_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xff,0x0c,0x04]
-
-v_sad_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x01,0x0d,0x04]
-
-v_sad_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x83,0x0d,0x04]
-
-v_sad_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_sad_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xef,0x0d,0x04]
-
-v_sad_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfe,0x07]
-
-v_sad_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x00]
-
-v_sad_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x96,0x01]
-
-v_sad_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x9a,0x01]
-
-v_sad_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x9e,0x01]
-
-v_sad_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xaa,0x01]
-
-v_sad_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xae,0x01]
-
-v_sad_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xf2,0x01]
-
-v_sad_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfa,0x01]
-
-v_sad_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfe,0x01]
-
-v_sad_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x02,0x02]
-
-v_sad_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x06,0x03]
-
-v_sad_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xc2,0x03]
-
-v_sad_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xde,0x03]
-
-v_sad_u32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xdc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0xff,0x05,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x65,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x66,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x67,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x80,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xff,0x0f,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xff,0x0c,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x01,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x83,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xef,0x0d,0x04]
-
-v_cvt_pk_u8_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfe,0x07]
-
-v_cvt_pk_u8_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x00]
-
-v_cvt_pk_u8_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x96,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x9a,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x9e,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xaa,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xae,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xf2,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfa,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfe,0x01]
-
-v_cvt_pk_u8_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x02,0x02]
-
-v_cvt_pk_u8_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x06,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xc2,0x03]
-
-v_cvt_pk_u8_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xde,0x03]
-
-v_cvt_pk_u8_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x24]
-
-v_cvt_pk_u8_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xdd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0xff,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x65,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x67,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xff,0x0f,0x04]
-
-v_div_fixup_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xff,0x0c,0x04]
-
-v_div_fixup_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfe,0x07]
-
-v_div_fixup_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x00]
-
-v_div_fixup_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x96,0x01]
-
-v_div_fixup_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_fixup_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x9e,0x01]
-
-v_div_fixup_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xae,0x01]
-
-v_div_fixup_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xf2,0x01]
-
-v_div_fixup_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfe,0x01]
-
-v_div_fixup_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xde,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_div_fixup_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x14]
-
-v_div_fixup_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[2:3], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x02,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[4:5], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x04,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], s[100:101], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x64,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], exec, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfd,0x0f,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[4:5], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x09,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[6:7], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x0d,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], s[100:101], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xc9,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], exec, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xfa,0x07]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[6:7]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x1a,0x00]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[8:9]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x22,0x00]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[100:101]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x92,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], flat_scratch
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], exec
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -1
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// CHECK: [0x05,0x01,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// CHECK: [0x05,0x02,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// CHECK: [0x05,0x04,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// CHECK: [0x05,0x07,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// CHECK: [0x05,0x80,0xdf,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x14]
-
-v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_div_scale_f32 v5, vcc, v1, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f32 v255, vcc, v1, v2, v3
-// CHECK: [0xff,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, v255, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0xff,0x05,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, s1, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, s101, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x65,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x67,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, vcc_lo, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, vcc_hi, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, m0, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, exec_lo, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, exec_hi, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, 0, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, -1, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, 0.5, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, -4.0, v2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_scale_f32 v5, vcc, v1, v255, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xff,0x0f,0x04]
-
-v_div_scale_f32 v5, vcc, v1, s2, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, s101, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, vcc_lo, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, vcc_hi, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, m0, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, exec_lo, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, exec_hi, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xff,0x0c,0x04]
-
-v_div_scale_f32 v5, vcc, v1, 0, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, -1, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, 0.5, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, -4.0, v3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_scale_f32 v5, vcc, v1, v2, v255
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfe,0x07]
-
-v_div_scale_f32 v5, vcc, v1, v2, s3
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x00]
-
-v_div_scale_f32 v5, vcc, v1, v2, s101
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x96,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x9e,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, vcc_lo
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, vcc_hi
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xae,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, m0
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xf2,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, exec_lo
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, exec_hi
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfe,0x01]
-
-v_div_scale_f32 v5, vcc, v1, v2, 0
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_scale_f32 v5, vcc, v1, v2, -1
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_scale_f32 v5, vcc, v1, v2, 0.5
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_scale_f32 v5, vcc, v1, v2, -4.0
-// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f64 v[254:255], vcc, v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x6a,0xe1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, s[2:3], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x02,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, s[4:5], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x04,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, s[100:101], v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x64,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, flat_scratch, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, exec, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfd,0x0f,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], s[4:5], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x09,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], s[6:7], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x0d,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], s[100:101], v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xc9,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], flat_scratch, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], exec, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xfa,0x07]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[6:7]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x1a,0x00]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[8:9]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x22,0x00]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[100:101]
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x92,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], flat_scratch
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], exec
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -1
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0xff,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xff,0x0f,0x04]
-
-v_div_fmas_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xfe,0x07]
-
-v_div_fmas_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_fmas_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_fmas_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_fmas_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fmas_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fmas_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fmas_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fmas_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xe2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f32 v5, v1, v2, v3 mul:2
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_div_fmas_f32 v5, v1, v2, v3 mul:4
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x14]
-
-v_div_fmas_f32 v5, v1, v2, v3 div:2
-// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[254:255], v[1:2], v[2:3], v[3:4]
-// CHECK: [0xfe,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[254:255], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], vcc, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], 0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x80,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], -1, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], 0.5, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], -4.0, v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[254:255], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xfd,0x0f,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], vcc, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x01,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x83,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xef,0x0d,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[254:255]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xfa,0x07]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], vcc
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x02,0x02]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -1
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x06,0x03]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0.5
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xc2,0x03]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -4.0
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xde,0x03]
-
-v_div_fmas_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fmas_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fmas_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fmas_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
-// CHECK: [0x05,0x01,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
-// CHECK: [0x05,0x02,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
-// CHECK: [0x05,0x04,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
-// CHECK: [0x05,0x07,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
-// CHECK: [0x05,0x80,0xe3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x0c]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x14]
-
-v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
-// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x1c]
-
-v_msad_u8 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_msad_u8 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_msad_u8 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0xff,0x05,0x0e,0x04]
-
-v_msad_u8 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x04,0x0e,0x04]
-
-v_msad_u8 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x65,0x04,0x0e,0x04]
-
-v_msad_u8 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x66,0x04,0x0e,0x04]
-
-v_msad_u8 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x67,0x04,0x0e,0x04]
-
-v_msad_u8 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_msad_u8 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_msad_u8 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_msad_u8 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_msad_u8 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_msad_u8 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x80,0x04,0x0e,0x04]
-
-v_msad_u8 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_msad_u8 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_msad_u8 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_msad_u8 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xff,0x0f,0x04]
-
-v_msad_u8 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0c,0x04]
-
-v_msad_u8 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_msad_u8 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_msad_u8 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_msad_u8 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_msad_u8 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_msad_u8 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_msad_u8 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_msad_u8 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xff,0x0c,0x04]
-
-v_msad_u8 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x01,0x0d,0x04]
-
-v_msad_u8 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x83,0x0d,0x04]
-
-v_msad_u8 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_msad_u8 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xef,0x0d,0x04]
-
-v_msad_u8 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfe,0x07]
-
-v_msad_u8 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x00]
-
-v_msad_u8 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x96,0x01]
-
-v_msad_u8 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x9a,0x01]
-
-v_msad_u8 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x9e,0x01]
-
-v_msad_u8 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xaa,0x01]
-
-v_msad_u8 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xae,0x01]
-
-v_msad_u8 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xf2,0x01]
-
-v_msad_u8 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfa,0x01]
-
-v_msad_u8 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfe,0x01]
-
-v_msad_u8 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x02,0x02]
-
-v_msad_u8 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x06,0x03]
-
-v_msad_u8 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xc2,0x03]
-
-v_msad_u8 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xde,0x03]
-
-v_msad_u8 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xe4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
-// CHECK: [0xfe,0x00,0xe5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x02,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x04,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], s[100:101], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x64,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x66,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x80,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xff,0x0f,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], s101, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xff,0x0c,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x01,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x83,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xef,0x0d,0x04]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xfa,0x07]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x1a,0x00]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x22,0x00]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[100:101]
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x92,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x9a,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xaa,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xfa,0x01]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x02,0x02]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x06,0x03]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0.5
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xc2,0x03]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -4.0
-// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xde,0x03]
-
-v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
-// CHECK: [0x05,0x80,0xe5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
-// CHECK: [0xfe,0x00,0xe6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0xfe,0x05,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x02,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x04,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], s[100:101], v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x64,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], s101, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0.5, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], -4.0, v[3:4]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xfa,0x07]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x1a,0x00]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x22,0x00]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[100:101]
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x92,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x02,0x02]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x06,0x03]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0.5
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -4.0
-// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xde,0x03]
-
-v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
-// CHECK: [0x05,0x80,0xe6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[2:3], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x02,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[4:5], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x04,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], s[100:101], v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x64,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], flat_scratch, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], vcc, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], exec, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], 0, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], -1, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], 0.5, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], -4.0, v2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], s2, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], s101, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], vcc_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], vcc_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], m0, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], exec_lo, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], exec_hi, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], 0, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], -1, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], 0.5, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], -4.0, v[3:6]
-// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6] clamp
-// CHECK: [0xfc,0x80,0xe7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[254:255], s[12:13], v1, v2, v[3:4]
-// CHECK: [0xfe,0x0c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[14:15], v1, v2, v[3:4]
-// CHECK: [0x05,0x0e,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[100:101], v1, v2, v[3:4]
-// CHECK: [0x05,0x64,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], flat_scratch, v1, v2, v[3:4]
-// CHECK: [0x05,0x66,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], vcc, v1, v2, v[3:4]
-// CHECK: [0x05,0x6a,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v255, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], s1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], s101, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], m0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], 0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], -1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v255, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, s2, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, s101, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, m0, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, 0, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, -1, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, 0.5, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, -4.0, v[3:4]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[254:255]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xfa,0x07]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x1a,0x00]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x22,0x00]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x92,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, exec
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -1
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0.5
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -4.0
-// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4] clamp
-// CHECK: [0x05,0x8c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[254:255], s[12:13], v1, v2, v[3:4]
-// CHECK: [0xfe,0x0c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[14:15], v1, v2, v[3:4]
-// CHECK: [0x05,0x0e,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[100:101], v1, v2, v[3:4]
-// CHECK: [0x05,0x64,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], flat_scratch, v1, v2, v[3:4]
-// CHECK: [0x05,0x66,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], vcc, v1, v2, v[3:4]
-// CHECK: [0x05,0x6a,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v255, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], s1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], s101, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], m0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], 0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], -1, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], 0.5, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], -4.0, v2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v255, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, s2, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, s101, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, m0, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, 0, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, -1, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, 0.5, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, -4.0, v[3:4]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xef,0x0d,0x04]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[254:255]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xfa,0x07]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[6:7]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x1a,0x00]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[8:9]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x22,0x00]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[100:101]
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x92,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, flat_scratch
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, vcc
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, exec
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -1
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0.5
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -4.0
-// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4] clamp
-// CHECK: [0x05,0x8c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_legacy_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_legacy_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_legacy_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_legacy_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_legacy_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_legacy_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_legacy_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_legacy_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_legacy_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_legacy_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_legacy_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_legacy_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_legacy_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_legacy_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_legacy_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_legacy_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_legacy_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_legacy_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_legacy_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_legacy_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_legacy_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_legacy_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_legacy_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_legacy_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_legacy_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_legacy_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_legacy_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_legacy_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_legacy_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_legacy_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x24]
-
-v_mad_legacy_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
-
-v_mad_legacy_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x84]
-
-v_mad_legacy_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_mad_legacy_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_legacy_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_legacy_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_legacy_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_legacy_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_legacy_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_legacy_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_legacy_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_legacy_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_legacy_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_legacy_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_legacy_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_legacy_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_legacy_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_legacy_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_legacy_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_legacy_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_legacy_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_legacy_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_legacy_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_legacy_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_legacy_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_legacy_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_legacy_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_legacy_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_legacy_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_legacy_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_legacy_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_legacy_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_legacy_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_legacy_u16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xeb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_i16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_i16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xec,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_legacy_i16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_legacy_i16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_legacy_i16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_legacy_i16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_legacy_i16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_legacy_i16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_legacy_i16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_legacy_i16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_legacy_i16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_legacy_i16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_legacy_i16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_legacy_i16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_legacy_i16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_legacy_i16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_legacy_i16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_legacy_i16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_legacy_i16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_legacy_i16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_legacy_i16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_legacy_i16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_legacy_i16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_legacy_i16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_legacy_i16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_legacy_i16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_legacy_i16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_legacy_i16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_legacy_i16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_legacy_i16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_legacy_i16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_legacy_i16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_legacy_i16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xec,0xd1,0x01,0x05,0x0e,0x04]
-
-v_perm_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0e,0x04]
-
-v_perm_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xed,0xd1,0x01,0x05,0x0e,0x04]
-
-v_perm_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0xff,0x05,0x0e,0x04]
-
-v_perm_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x04,0x0e,0x04]
-
-v_perm_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x65,0x04,0x0e,0x04]
-
-v_perm_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x66,0x04,0x0e,0x04]
-
-v_perm_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x67,0x04,0x0e,0x04]
-
-v_perm_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_perm_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_perm_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_perm_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_perm_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_perm_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x80,0x04,0x0e,0x04]
-
-v_perm_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_perm_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_perm_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_perm_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xff,0x0f,0x04]
-
-v_perm_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0c,0x04]
-
-v_perm_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_perm_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_perm_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_perm_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_perm_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_perm_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_perm_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_perm_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xff,0x0c,0x04]
-
-v_perm_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x01,0x0d,0x04]
-
-v_perm_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x83,0x0d,0x04]
-
-v_perm_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_perm_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xef,0x0d,0x04]
-
-v_perm_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfe,0x07]
-
-v_perm_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0e,0x00]
-
-v_perm_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x96,0x01]
-
-v_perm_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x9a,0x01]
-
-v_perm_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x9e,0x01]
-
-v_perm_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xaa,0x01]
-
-v_perm_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xae,0x01]
-
-v_perm_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xf2,0x01]
-
-v_perm_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfa,0x01]
-
-v_perm_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfe,0x01]
-
-v_perm_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x02,0x02]
-
-v_perm_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x06,0x03]
-
-v_perm_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xc2,0x03]
-
-v_perm_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xde,0x03]
-
-v_fma_legacy_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_legacy_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_legacy_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0xff,0x05,0x0e,0x04]
-
-v_fma_legacy_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x04,0x0e,0x04]
-
-v_fma_legacy_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x65,0x04,0x0e,0x04]
-
-v_fma_legacy_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x66,0x04,0x0e,0x04]
-
-v_fma_legacy_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x67,0x04,0x0e,0x04]
-
-v_fma_legacy_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_fma_legacy_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_fma_legacy_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_fma_legacy_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_fma_legacy_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_fma_legacy_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xff,0x0f,0x04]
-
-v_fma_legacy_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0c,0x04]
-
-v_fma_legacy_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_fma_legacy_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_fma_legacy_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_fma_legacy_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_fma_legacy_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_fma_legacy_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_fma_legacy_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_fma_legacy_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xff,0x0c,0x04]
-
-v_fma_legacy_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfe,0x07]
-
-v_fma_legacy_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x00]
-
-v_fma_legacy_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x96,0x01]
-
-v_fma_legacy_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x9a,0x01]
-
-v_fma_legacy_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x9e,0x01]
-
-v_fma_legacy_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xaa,0x01]
-
-v_fma_legacy_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xae,0x01]
-
-v_fma_legacy_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xf2,0x01]
-
-v_fma_legacy_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfa,0x01]
-
-v_fma_legacy_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfe,0x01]
-
-v_fma_legacy_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x24]
-
-v_fma_legacy_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x44]
-
-v_fma_legacy_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
-
-v_fma_legacy_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_fma_legacy_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_legacy_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_legacy_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_legacy_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_fma_legacy_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0xff,0x05,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x04,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x65,0x04,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x66,0x04,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x67,0x04,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xff,0x0f,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0c,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xff,0x0c,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfe,0x07]
-
-v_div_fixup_legacy_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x00]
-
-v_div_fixup_legacy_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x96,0x01]
-
-v_div_fixup_legacy_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x9a,0x01]
-
-v_div_fixup_legacy_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x9e,0x01]
-
-v_div_fixup_legacy_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_legacy_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xae,0x01]
-
-v_div_fixup_legacy_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xf2,0x01]
-
-v_div_fixup_legacy_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_legacy_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfe,0x01]
-
-v_div_fixup_legacy_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_legacy_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_legacy_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_legacy_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_legacy_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
-
-v_cvt_pkaccum_u8_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0xf0,0xd1,0x01,0x05,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0xff,0x05,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x65,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x66,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x67,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x6a,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x6b,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x7c,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x7e,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x7f,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x80,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0xc1,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0xf0,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0xf7,0x04,0x02,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xff,0x03,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcb,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcd,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcf,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd5,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd7,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf9,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xfd,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xff,0x00,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x01,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x83,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xe1,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xef,0x01,0x00]
-
-v_cvt_pkaccum_u8_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x02,0x20]
-
-v_cvt_pkaccum_u8_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0xf0,0xd1,0x01,0x05,0x02,0x00]
-
-v_mad_u32_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_u32_u16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u32_u16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u32_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_u32_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_u32_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_u32_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_u32_u16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u32_u16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u32_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_u32_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_u32_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_u32_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_u32_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_u32_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_u32_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_u32_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_u32_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_u32_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_u32_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_u32_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_u32_u16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_u32_u16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xf1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xf1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xf1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xf1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xf1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_u32_u16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xf1,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0xff,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x65,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x66,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x67,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x80,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_mad_i32_i16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i32_i16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i32_i16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xff,0x0f,0x04]
-
-v_mad_i32_i16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xff,0x0c,0x04]
-
-v_mad_i32_i16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x01,0x0d,0x04]
-
-v_mad_i32_i16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x83,0x0d,0x04]
-
-v_mad_i32_i16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i32_i16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i32_i16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xfe,0x07]
-
-v_mad_i32_i16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x00]
-
-v_mad_i32_i16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x96,0x01]
-
-v_mad_i32_i16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x9a,0x01]
-
-v_mad_i32_i16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x9e,0x01]
-
-v_mad_i32_i16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xaa,0x01]
-
-v_mad_i32_i16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xae,0x01]
-
-v_mad_i32_i16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xf2,0x01]
-
-v_mad_i32_i16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xfa,0x01]
-
-v_mad_i32_i16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xfe,0x01]
-
-v_mad_i32_i16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x02,0x02]
-
-v_mad_i32_i16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x06,0x03]
-
-v_mad_i32_i16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xc2,0x03]
-
-v_mad_i32_i16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xde,0x03]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xf2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xf2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xf2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xf2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xf2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_mad_i32_i16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xf2,0xd1,0x01,0x05,0x0e,0x04]
-
-v_xad_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_xad_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xf3,0xd1,0x01,0x05,0x0e,0x04]
-
-v_xad_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0xff,0x05,0x0e,0x04]
-
-v_xad_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x04,0x0e,0x04]
-
-v_xad_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x65,0x04,0x0e,0x04]
-
-v_xad_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x66,0x04,0x0e,0x04]
-
-v_xad_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x67,0x04,0x0e,0x04]
-
-v_xad_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_xad_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_xad_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_xad_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_xad_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_xad_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x80,0x04,0x0e,0x04]
-
-v_xad_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_xad_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_xad_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_xad_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xff,0x0f,0x04]
-
-v_xad_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x0c,0x04]
-
-v_xad_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_xad_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_xad_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_xad_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_xad_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_xad_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_xad_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_xad_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xff,0x0c,0x04]
-
-v_xad_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x01,0x0d,0x04]
-
-v_xad_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x83,0x0d,0x04]
-
-v_xad_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_xad_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xef,0x0d,0x04]
-
-v_xad_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xfe,0x07]
-
-v_xad_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x0e,0x00]
-
-v_xad_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x96,0x01]
-
-v_xad_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x9a,0x01]
-
-v_xad_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x9e,0x01]
-
-v_xad_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xaa,0x01]
-
-v_xad_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xae,0x01]
-
-v_xad_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xf2,0x01]
-
-v_xad_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xfa,0x01]
-
-v_xad_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xfe,0x01]
-
-v_xad_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x02,0x02]
-
-v_xad_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x06,0x03]
-
-v_xad_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xc2,0x03]
-
-v_xad_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xde,0x03]
-
-v_min3_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0xff,0x05,0x0e,0x04]
-
-v_min3_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x04,0x0e,0x04]
-
-v_min3_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x65,0x04,0x0e,0x04]
-
-v_min3_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x66,0x04,0x0e,0x04]
-
-v_min3_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x67,0x04,0x0e,0x04]
-
-v_min3_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_min3_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_min3_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_min3_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_min3_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_min3_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x80,0x04,0x0e,0x04]
-
-v_min3_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_min3_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_min3_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_min3_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xff,0x0f,0x04]
-
-v_min3_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0c,0x04]
-
-v_min3_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_min3_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_min3_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_min3_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_min3_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_min3_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_min3_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_min3_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xff,0x0c,0x04]
-
-v_min3_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x01,0x0d,0x04]
-
-v_min3_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x83,0x0d,0x04]
-
-v_min3_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_min3_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xef,0x0d,0x04]
-
-v_min3_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xfe,0x07]
-
-v_min3_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x00]
-
-v_min3_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x96,0x01]
-
-v_min3_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x9a,0x01]
-
-v_min3_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x9e,0x01]
-
-v_min3_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xaa,0x01]
-
-v_min3_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xae,0x01]
-
-v_min3_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xf2,0x01]
-
-v_min3_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xfa,0x01]
-
-v_min3_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x02,0x02]
-
-v_min3_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x06,0x03]
-
-v_min3_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xc2,0x03]
-
-v_min3_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xde,0x03]
-
-v_min3_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x24]
-
-v_min3_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x44]
-
-v_min3_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x84]
-
-v_min3_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_min3_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xf4,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0xff,0x05,0x0e,0x04]
-
-v_min3_i16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x04,0x0e,0x04]
-
-v_min3_i16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x65,0x04,0x0e,0x04]
-
-v_min3_i16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x66,0x04,0x0e,0x04]
-
-v_min3_i16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x67,0x04,0x0e,0x04]
-
-v_min3_i16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_min3_i16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_min3_i16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_min3_i16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_min3_i16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_min3_i16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x80,0x04,0x0e,0x04]
-
-v_min3_i16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_min3_i16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_i16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_i16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xff,0x0f,0x04]
-
-v_min3_i16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0c,0x04]
-
-v_min3_i16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_min3_i16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_min3_i16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_min3_i16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_min3_i16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_min3_i16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_min3_i16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_min3_i16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xff,0x0c,0x04]
-
-v_min3_i16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x01,0x0d,0x04]
-
-v_min3_i16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x83,0x0d,0x04]
-
-v_min3_i16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_i16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_i16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xfe,0x07]
-
-v_min3_i16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x00]
-
-v_min3_i16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x96,0x01]
-
-v_min3_i16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x9a,0x01]
-
-v_min3_i16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x9e,0x01]
-
-v_min3_i16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xaa,0x01]
-
-v_min3_i16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xae,0x01]
-
-v_min3_i16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xf2,0x01]
-
-v_min3_i16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xfa,0x01]
-
-v_min3_i16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_i16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x02,0x02]
-
-v_min3_i16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x06,0x03]
-
-v_min3_i16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_i16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xf5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xf5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xf5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xf5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xf5,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xf6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0xff,0x05,0x0e,0x04]
-
-v_min3_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x04,0x0e,0x04]
-
-v_min3_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x65,0x04,0x0e,0x04]
-
-v_min3_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x66,0x04,0x0e,0x04]
-
-v_min3_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x67,0x04,0x0e,0x04]
-
-v_min3_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_min3_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_min3_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_min3_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_min3_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_min3_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x80,0x04,0x0e,0x04]
-
-v_min3_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_min3_u16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_u16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xff,0x0f,0x04]
-
-v_min3_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x0c,0x04]
-
-v_min3_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_min3_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_min3_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_min3_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_min3_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_min3_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_min3_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_min3_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xff,0x0c,0x04]
-
-v_min3_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x01,0x0d,0x04]
-
-v_min3_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x83,0x0d,0x04]
-
-v_min3_u16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_u16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xfe,0x07]
-
-v_min3_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x0e,0x00]
-
-v_min3_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x96,0x01]
-
-v_min3_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x9a,0x01]
-
-v_min3_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x9e,0x01]
-
-v_min3_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xaa,0x01]
-
-v_min3_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xae,0x01]
-
-v_min3_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xf2,0x01]
-
-v_min3_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xfa,0x01]
-
-v_min3_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xfe,0x01]
-
-v_min3_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x02,0x02]
-
-v_min3_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x06,0x03]
-
-v_min3_u16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_u16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xf6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xf6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xf6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xf6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_min3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xf6,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0xff,0x05,0x0e,0x04]
-
-v_max3_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x04,0x0e,0x04]
-
-v_max3_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x65,0x04,0x0e,0x04]
-
-v_max3_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x66,0x04,0x0e,0x04]
-
-v_max3_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x67,0x04,0x0e,0x04]
-
-v_max3_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_max3_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_max3_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_max3_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_max3_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_max3_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x80,0x04,0x0e,0x04]
-
-v_max3_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_max3_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_max3_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_max3_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xff,0x0f,0x04]
-
-v_max3_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0c,0x04]
-
-v_max3_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_max3_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_max3_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_max3_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_max3_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_max3_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_max3_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_max3_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xff,0x0c,0x04]
-
-v_max3_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x01,0x0d,0x04]
-
-v_max3_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x83,0x0d,0x04]
-
-v_max3_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_max3_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xef,0x0d,0x04]
-
-v_max3_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xfe,0x07]
-
-v_max3_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x00]
-
-v_max3_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x96,0x01]
-
-v_max3_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x9a,0x01]
-
-v_max3_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x9e,0x01]
-
-v_max3_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xaa,0x01]
-
-v_max3_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xae,0x01]
-
-v_max3_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xf2,0x01]
-
-v_max3_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xfa,0x01]
-
-v_max3_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xfe,0x01]
-
-v_max3_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x02,0x02]
-
-v_max3_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x06,0x03]
-
-v_max3_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xc2,0x03]
-
-v_max3_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xde,0x03]
-
-v_max3_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x24]
-
-v_max3_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x44]
-
-v_max3_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x84]
-
-v_max3_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_max3_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xf7,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0xff,0x05,0x0e,0x04]
-
-v_max3_i16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x04,0x0e,0x04]
-
-v_max3_i16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x65,0x04,0x0e,0x04]
-
-v_max3_i16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x66,0x04,0x0e,0x04]
-
-v_max3_i16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x67,0x04,0x0e,0x04]
-
-v_max3_i16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_max3_i16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_max3_i16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_max3_i16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_max3_i16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_max3_i16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x80,0x04,0x0e,0x04]
-
-v_max3_i16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_max3_i16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_i16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_i16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xff,0x0f,0x04]
-
-v_max3_i16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0c,0x04]
-
-v_max3_i16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_max3_i16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_max3_i16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_max3_i16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_max3_i16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_max3_i16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_max3_i16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_max3_i16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xff,0x0c,0x04]
-
-v_max3_i16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x01,0x0d,0x04]
-
-v_max3_i16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x83,0x0d,0x04]
-
-v_max3_i16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_i16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_i16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xfe,0x07]
-
-v_max3_i16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x00]
-
-v_max3_i16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x96,0x01]
-
-v_max3_i16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x9a,0x01]
-
-v_max3_i16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x9e,0x01]
-
-v_max3_i16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xaa,0x01]
-
-v_max3_i16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xae,0x01]
-
-v_max3_i16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xf2,0x01]
-
-v_max3_i16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xfa,0x01]
-
-v_max3_i16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xfe,0x01]
-
-v_max3_i16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x02,0x02]
-
-v_max3_i16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x06,0x03]
-
-v_max3_i16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_i16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xf8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xf8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xf8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xf8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xf8,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xf9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0xff,0x05,0x0e,0x04]
-
-v_max3_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x04,0x0e,0x04]
-
-v_max3_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x65,0x04,0x0e,0x04]
-
-v_max3_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x66,0x04,0x0e,0x04]
-
-v_max3_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x67,0x04,0x0e,0x04]
-
-v_max3_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_max3_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_max3_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_max3_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_max3_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_max3_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x80,0x04,0x0e,0x04]
-
-v_max3_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_max3_u16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_u16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xff,0x0f,0x04]
-
-v_max3_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x0c,0x04]
-
-v_max3_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_max3_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_max3_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_max3_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_max3_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_max3_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_max3_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_max3_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xff,0x0c,0x04]
-
-v_max3_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x01,0x0d,0x04]
-
-v_max3_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x83,0x0d,0x04]
-
-v_max3_u16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_u16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xfe,0x07]
-
-v_max3_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x0e,0x00]
-
-v_max3_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x96,0x01]
-
-v_max3_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x9a,0x01]
-
-v_max3_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x9e,0x01]
-
-v_max3_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xaa,0x01]
-
-v_max3_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xae,0x01]
-
-v_max3_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xf2,0x01]
-
-v_max3_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xfa,0x01]
-
-v_max3_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xfe,0x01]
-
-v_max3_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x02,0x02]
-
-v_max3_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x06,0x03]
-
-v_max3_u16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_u16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xf9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xf9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xf9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xf9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_max3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xf9,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0xff,0x05,0x0e,0x04]
-
-v_med3_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x04,0x0e,0x04]
-
-v_med3_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x65,0x04,0x0e,0x04]
-
-v_med3_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x66,0x04,0x0e,0x04]
-
-v_med3_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x67,0x04,0x0e,0x04]
-
-v_med3_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_med3_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_med3_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_med3_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_med3_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_med3_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x80,0x04,0x0e,0x04]
-
-v_med3_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_med3_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_med3_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_med3_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xff,0x0f,0x04]
-
-v_med3_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0c,0x04]
-
-v_med3_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_med3_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_med3_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_med3_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_med3_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_med3_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_med3_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_med3_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xff,0x0c,0x04]
-
-v_med3_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x01,0x0d,0x04]
-
-v_med3_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x83,0x0d,0x04]
-
-v_med3_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_med3_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xef,0x0d,0x04]
-
-v_med3_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xfe,0x07]
-
-v_med3_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x00]
-
-v_med3_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x96,0x01]
-
-v_med3_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x9a,0x01]
-
-v_med3_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x9e,0x01]
-
-v_med3_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xaa,0x01]
-
-v_med3_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xae,0x01]
-
-v_med3_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xf2,0x01]
-
-v_med3_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xfa,0x01]
-
-v_med3_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xfe,0x01]
-
-v_med3_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x02,0x02]
-
-v_med3_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x06,0x03]
-
-v_med3_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xc2,0x03]
-
-v_med3_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xde,0x03]
-
-v_med3_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x24]
-
-v_med3_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x44]
-
-v_med3_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x84]
-
-v_med3_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0xe4]
-
-v_med3_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xfa,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0xff,0x05,0x0e,0x04]
-
-v_med3_i16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x04,0x0e,0x04]
-
-v_med3_i16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x65,0x04,0x0e,0x04]
-
-v_med3_i16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x66,0x04,0x0e,0x04]
-
-v_med3_i16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x67,0x04,0x0e,0x04]
-
-v_med3_i16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_med3_i16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_med3_i16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_med3_i16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_med3_i16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_med3_i16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x80,0x04,0x0e,0x04]
-
-v_med3_i16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_med3_i16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_i16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_i16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xff,0x0f,0x04]
-
-v_med3_i16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0c,0x04]
-
-v_med3_i16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_med3_i16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_med3_i16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_med3_i16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_med3_i16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_med3_i16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_med3_i16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_med3_i16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xff,0x0c,0x04]
-
-v_med3_i16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x01,0x0d,0x04]
-
-v_med3_i16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x83,0x0d,0x04]
-
-v_med3_i16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_i16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_i16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xfe,0x07]
-
-v_med3_i16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x00]
-
-v_med3_i16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x96,0x01]
-
-v_med3_i16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x9a,0x01]
-
-v_med3_i16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x9e,0x01]
-
-v_med3_i16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xaa,0x01]
-
-v_med3_i16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xae,0x01]
-
-v_med3_i16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xf2,0x01]
-
-v_med3_i16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xfa,0x01]
-
-v_med3_i16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xfe,0x01]
-
-v_med3_i16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x02,0x02]
-
-v_med3_i16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x06,0x03]
-
-v_med3_i16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_i16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xfb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xfb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xfb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xfb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xfb,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xfc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0xff,0x05,0x0e,0x04]
-
-v_med3_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x04,0x0e,0x04]
-
-v_med3_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x65,0x04,0x0e,0x04]
-
-v_med3_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x66,0x04,0x0e,0x04]
-
-v_med3_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x67,0x04,0x0e,0x04]
-
-v_med3_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_med3_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_med3_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_med3_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_med3_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_med3_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x80,0x04,0x0e,0x04]
-
-v_med3_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_med3_u16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_u16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xff,0x0f,0x04]
-
-v_med3_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x0c,0x04]
-
-v_med3_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_med3_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_med3_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_med3_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_med3_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_med3_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_med3_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_med3_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xff,0x0c,0x04]
-
-v_med3_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x01,0x0d,0x04]
-
-v_med3_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x83,0x0d,0x04]
-
-v_med3_u16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_u16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xfe,0x07]
-
-v_med3_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x0e,0x00]
-
-v_med3_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x96,0x01]
-
-v_med3_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x9a,0x01]
-
-v_med3_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x9e,0x01]
-
-v_med3_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xaa,0x01]
-
-v_med3_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xae,0x01]
-
-v_med3_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xf2,0x01]
-
-v_med3_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xfa,0x01]
-
-v_med3_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xfe,0x01]
-
-v_med3_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x02,0x02]
-
-v_med3_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x06,0x03]
-
-v_med3_u16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_u16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0xfc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0xfc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0xfc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0xfc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_med3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0xfc,0xd1,0x01,0x05,0x0e,0x04]
-
-v_lshl_add_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_lshl_add_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xfd,0xd1,0x01,0x05,0x0e,0x04]
-
-v_lshl_add_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0xff,0x05,0x0e,0x04]
-
-v_lshl_add_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x65,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x66,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x67,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x80,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_lshl_add_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xff,0x0f,0x04]
-
-v_lshl_add_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xff,0x0c,0x04]
-
-v_lshl_add_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x01,0x0d,0x04]
-
-v_lshl_add_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x83,0x0d,0x04]
-
-v_lshl_add_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_lshl_add_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xef,0x0d,0x04]
-
-v_lshl_add_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xfe,0x07]
-
-v_lshl_add_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x0e,0x00]
-
-v_lshl_add_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x96,0x01]
-
-v_lshl_add_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x9a,0x01]
-
-v_lshl_add_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x9e,0x01]
-
-v_lshl_add_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xaa,0x01]
-
-v_lshl_add_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xae,0x01]
-
-v_lshl_add_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xf2,0x01]
-
-v_lshl_add_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xfa,0x01]
-
-v_lshl_add_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xfe,0x01]
-
-v_lshl_add_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x02,0x02]
-
-v_lshl_add_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x06,0x03]
-
-v_lshl_add_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xc2,0x03]
-
-v_lshl_add_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xde,0x03]
-
-v_add_lshl_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x0e,0x04]
-
-v_add_lshl_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xfe,0xd1,0x01,0x05,0x0e,0x04]
-
-v_add_lshl_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0xff,0x05,0x0e,0x04]
-
-v_add_lshl_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x65,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x66,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x67,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x80,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_add_lshl_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xff,0x0f,0x04]
-
-v_add_lshl_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xff,0x0c,0x04]
-
-v_add_lshl_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x01,0x0d,0x04]
-
-v_add_lshl_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x83,0x0d,0x04]
-
-v_add_lshl_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_add_lshl_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xef,0x0d,0x04]
-
-v_add_lshl_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xfe,0x07]
-
-v_add_lshl_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x0e,0x00]
-
-v_add_lshl_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x96,0x01]
-
-v_add_lshl_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x9a,0x01]
-
-v_add_lshl_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x9e,0x01]
-
-v_add_lshl_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xaa,0x01]
-
-v_add_lshl_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xae,0x01]
-
-v_add_lshl_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xf2,0x01]
-
-v_add_lshl_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xfa,0x01]
-
-v_add_lshl_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xfe,0x01]
-
-v_add_lshl_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x02,0x02]
-
-v_add_lshl_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x06,0x03]
-
-v_add_lshl_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xc2,0x03]
-
-v_add_lshl_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xde,0x03]
-
-v_add3_u32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x0e,0x04]
-
-v_add3_u32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xff,0xd1,0x01,0x05,0x0e,0x04]
-
-v_add3_u32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0xff,0x05,0x0e,0x04]
-
-v_add3_u32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x04,0x0e,0x04]
-
-v_add3_u32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x65,0x04,0x0e,0x04]
-
-v_add3_u32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x66,0x04,0x0e,0x04]
-
-v_add3_u32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x67,0x04,0x0e,0x04]
-
-v_add3_u32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x6a,0x04,0x0e,0x04]
-
-v_add3_u32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x6b,0x04,0x0e,0x04]
-
-v_add3_u32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x7c,0x04,0x0e,0x04]
-
-v_add3_u32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x7e,0x04,0x0e,0x04]
-
-v_add3_u32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x7f,0x04,0x0e,0x04]
-
-v_add3_u32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x80,0x04,0x0e,0x04]
-
-v_add3_u32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0xc1,0x04,0x0e,0x04]
-
-v_add3_u32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0xf0,0x04,0x0e,0x04]
-
-v_add3_u32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0xf7,0x04,0x0e,0x04]
-
-v_add3_u32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xff,0x0f,0x04]
-
-v_add3_u32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x0c,0x04]
-
-v_add3_u32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xcb,0x0c,0x04]
-
-v_add3_u32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xcd,0x0c,0x04]
-
-v_add3_u32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xcf,0x0c,0x04]
-
-v_add3_u32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xd5,0x0c,0x04]
-
-v_add3_u32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xd7,0x0c,0x04]
-
-v_add3_u32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xf9,0x0c,0x04]
-
-v_add3_u32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xfd,0x0c,0x04]
-
-v_add3_u32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xff,0x0c,0x04]
-
-v_add3_u32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x01,0x0d,0x04]
-
-v_add3_u32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x83,0x0d,0x04]
-
-v_add3_u32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xe1,0x0d,0x04]
-
-v_add3_u32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xef,0x0d,0x04]
-
-v_add3_u32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xfe,0x07]
-
-v_add3_u32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x0e,0x00]
-
-v_add3_u32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x96,0x01]
-
-v_add3_u32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x9a,0x01]
-
-v_add3_u32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x9e,0x01]
-
-v_add3_u32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xaa,0x01]
-
-v_add3_u32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xae,0x01]
-
-v_add3_u32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xf2,0x01]
-
-v_add3_u32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xfa,0x01]
-
-v_add3_u32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xfe,0x01]
-
-v_add3_u32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x02,0x02]
-
-v_add3_u32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x06,0x03]
-
-v_add3_u32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xc2,0x03]
-
-v_add3_u32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xde,0x03]
-
-v_lshl_or_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x0e,0x04]
-
-v_lshl_or_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x00,0xd2,0x01,0x05,0x0e,0x04]
-
-v_lshl_or_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0xff,0x05,0x0e,0x04]
-
-v_lshl_or_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x65,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x66,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x67,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x80,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_lshl_or_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xff,0x0f,0x04]
-
-v_lshl_or_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xcb,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xff,0x0c,0x04]
-
-v_lshl_or_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x01,0x0d,0x04]
-
-v_lshl_or_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x83,0x0d,0x04]
-
-v_lshl_or_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_lshl_or_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xef,0x0d,0x04]
-
-v_lshl_or_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xfe,0x07]
-
-v_lshl_or_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x0e,0x00]
-
-v_lshl_or_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x96,0x01]
-
-v_lshl_or_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x9a,0x01]
-
-v_lshl_or_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x9e,0x01]
-
-v_lshl_or_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xaa,0x01]
-
-v_lshl_or_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xae,0x01]
-
-v_lshl_or_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xf2,0x01]
-
-v_lshl_or_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xfa,0x01]
-
-v_lshl_or_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xfe,0x01]
-
-v_lshl_or_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x02,0x02]
-
-v_lshl_or_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x06,0x03]
-
-v_lshl_or_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xc2,0x03]
-
-v_lshl_or_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xde,0x03]
-
-v_and_or_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x0e,0x04]
-
-v_and_or_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x01,0xd2,0x01,0x05,0x0e,0x04]
-
-v_and_or_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0xff,0x05,0x0e,0x04]
-
-v_and_or_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x65,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x66,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x67,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x80,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_and_or_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xff,0x0f,0x04]
-
-v_and_or_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x0c,0x04]
-
-v_and_or_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xcb,0x0c,0x04]
-
-v_and_or_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_and_or_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_and_or_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_and_or_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_and_or_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_and_or_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_and_or_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xff,0x0c,0x04]
-
-v_and_or_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x01,0x0d,0x04]
-
-v_and_or_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x83,0x0d,0x04]
-
-v_and_or_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_and_or_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xef,0x0d,0x04]
-
-v_and_or_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xfe,0x07]
-
-v_and_or_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x0e,0x00]
-
-v_and_or_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x96,0x01]
-
-v_and_or_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x9a,0x01]
-
-v_and_or_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x9e,0x01]
-
-v_and_or_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xaa,0x01]
-
-v_and_or_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xae,0x01]
-
-v_and_or_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xf2,0x01]
-
-v_and_or_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xfa,0x01]
-
-v_and_or_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xfe,0x01]
-
-v_and_or_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x02,0x02]
-
-v_and_or_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x06,0x03]
-
-v_and_or_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xc2,0x03]
-
-v_and_or_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xde,0x03]
-
-v_or3_b32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x0e,0x04]
-
-v_or3_b32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x02,0xd2,0x01,0x05,0x0e,0x04]
-
-v_or3_b32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0xff,0x05,0x0e,0x04]
-
-v_or3_b32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x04,0x0e,0x04]
-
-v_or3_b32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x65,0x04,0x0e,0x04]
-
-v_or3_b32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x66,0x04,0x0e,0x04]
-
-v_or3_b32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x67,0x04,0x0e,0x04]
-
-v_or3_b32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_or3_b32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_or3_b32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_or3_b32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_or3_b32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_or3_b32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x80,0x04,0x0e,0x04]
-
-v_or3_b32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_or3_b32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_or3_b32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_or3_b32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xff,0x0f,0x04]
-
-v_or3_b32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x0c,0x04]
-
-v_or3_b32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xcb,0x0c,0x04]
-
-v_or3_b32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_or3_b32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_or3_b32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_or3_b32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_or3_b32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_or3_b32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_or3_b32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xff,0x0c,0x04]
-
-v_or3_b32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x01,0x0d,0x04]
-
-v_or3_b32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x83,0x0d,0x04]
-
-v_or3_b32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_or3_b32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xef,0x0d,0x04]
-
-v_or3_b32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xfe,0x07]
-
-v_or3_b32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x0e,0x00]
-
-v_or3_b32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x96,0x01]
-
-v_or3_b32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x9a,0x01]
-
-v_or3_b32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x9e,0x01]
-
-v_or3_b32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xaa,0x01]
-
-v_or3_b32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xae,0x01]
-
-v_or3_b32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xf2,0x01]
-
-v_or3_b32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xfa,0x01]
-
-v_or3_b32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xfe,0x01]
-
-v_or3_b32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x02,0x02]
-
-v_or3_b32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x06,0x03]
-
-v_or3_b32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xc2,0x03]
-
-v_or3_b32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xde,0x03]
-
-v_mad_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mad_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mad_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x65,0x04,0x0e,0x04]
-
-v_mad_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x66,0x04,0x0e,0x04]
-
-v_mad_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mad_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mad_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mad_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mad_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mad_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mad_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mad_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mad_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_mad_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_mad_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mad_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mad_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xcb,0x0c,0x04]
-
-v_mad_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_mad_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mad_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mad_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mad_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mad_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mad_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mad_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mad_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_mad_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xef,0x0d,0x04]
-
-v_mad_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xfe,0x07]
-
-v_mad_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x00]
-
-v_mad_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x96,0x01]
-
-v_mad_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x9a,0x01]
-
-v_mad_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x9e,0x01]
-
-v_mad_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mad_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xae,0x01]
-
-v_mad_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xf2,0x01]
-
-v_mad_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mad_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xfe,0x01]
-
-v_mad_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x02,0x02]
-
-v_mad_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x06,0x03]
-
-v_mad_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
-
-v_mad_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xde,0x03]
-
-v_mad_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x24]
-
-v_mad_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x44]
-
-v_mad_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x84]
-
-v_mad_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_mad_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x04,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mad_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mad_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x65,0x04,0x0e,0x04]
-
-v_mad_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x66,0x04,0x0e,0x04]
-
-v_mad_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mad_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mad_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mad_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mad_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mad_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mad_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mad_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mad_u16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mad_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mad_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xcb,0x0c,0x04]
-
-v_mad_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_mad_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mad_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mad_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mad_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mad_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mad_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mad_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mad_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_u16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x07]
-
-v_mad_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0e,0x00]
-
-v_mad_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x96,0x01]
-
-v_mad_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x9a,0x01]
-
-v_mad_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x9e,0x01]
-
-v_mad_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mad_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xae,0x01]
-
-v_mad_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xf2,0x01]
-
-v_mad_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mad_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x01]
-
-v_mad_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x02,0x02]
-
-v_mad_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x06,0x03]
-
-v_mad_u16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0x04,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0x04,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0x04,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0x04,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_u16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x05,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0xff,0x05,0x0e,0x04]
-
-v_mad_i16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x04,0x0e,0x04]
-
-v_mad_i16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x65,0x04,0x0e,0x04]
-
-v_mad_i16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x66,0x04,0x0e,0x04]
-
-v_mad_i16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x67,0x04,0x0e,0x04]
-
-v_mad_i16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_mad_i16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_mad_i16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_mad_i16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_mad_i16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_mad_i16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
-
-v_mad_i16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_mad_i16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xff,0x0f,0x04]
-
-v_mad_i16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x0c,0x04]
-
-v_mad_i16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xcb,0x0c,0x04]
-
-v_mad_i16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_mad_i16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_mad_i16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_mad_i16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_mad_i16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_mad_i16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_mad_i16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xff,0x0c,0x04]
-
-v_mad_i16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x01,0x0d,0x04]
-
-v_mad_i16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
-
-v_mad_i16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x07]
-
-v_mad_i16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x0e,0x00]
-
-v_mad_i16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x96,0x01]
-
-v_mad_i16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x9a,0x01]
-
-v_mad_i16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x9e,0x01]
-
-v_mad_i16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xaa,0x01]
-
-v_mad_i16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xae,0x01]
-
-v_mad_i16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xf2,0x01]
-
-v_mad_i16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfa,0x01]
-
-v_mad_i16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x01]
-
-v_mad_i16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x02,0x02]
-
-v_mad_i16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x06,0x03]
-
-v_mad_i16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0x05,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0x05,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0x05,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0x05,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0x05,0xd2,0x01,0x05,0x0e,0x04]
-
-v_mad_i16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0x05,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0xff,0x05,0x0e,0x04]
-
-v_fma_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x04,0x0e,0x04]
-
-v_fma_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x65,0x04,0x0e,0x04]
-
-v_fma_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x66,0x04,0x0e,0x04]
-
-v_fma_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x67,0x04,0x0e,0x04]
-
-v_fma_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_fma_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_fma_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_fma_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_fma_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_fma_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x80,0x04,0x0e,0x04]
-
-v_fma_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_fma_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_fma_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_fma_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xff,0x0f,0x04]
-
-v_fma_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0c,0x04]
-
-v_fma_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xcb,0x0c,0x04]
-
-v_fma_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_fma_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_fma_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_fma_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_fma_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_fma_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_fma_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xff,0x0c,0x04]
-
-v_fma_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x01,0x0d,0x04]
-
-v_fma_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x83,0x0d,0x04]
-
-v_fma_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_fma_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xef,0x0d,0x04]
-
-v_fma_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xfe,0x07]
-
-v_fma_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x00]
-
-v_fma_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x96,0x01]
-
-v_fma_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x9a,0x01]
-
-v_fma_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x9e,0x01]
-
-v_fma_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xaa,0x01]
-
-v_fma_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xae,0x01]
-
-v_fma_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xf2,0x01]
-
-v_fma_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xfa,0x01]
-
-v_fma_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xfe,0x01]
-
-v_fma_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x02]
-
-v_fma_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x06,0x03]
-
-v_fma_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xc2,0x03]
-
-v_fma_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xde,0x03]
-
-v_fma_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24]
-
-v_fma_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x44]
-
-v_fma_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x84]
-
-v_fma_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_fma_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_fma_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0xff,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x65,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x66,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x67,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x6a,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x6b,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x7c,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x7e,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x7f,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x80,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0xc1,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0xf7,0x04,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xff,0x0f,0x04]
-
-v_div_fixup_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xcb,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xcd,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xcf,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xd5,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xd7,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xf9,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xfd,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xff,0x0c,0x04]
-
-v_div_fixup_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x01,0x0d,0x04]
-
-v_div_fixup_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x83,0x0d,0x04]
-
-v_div_fixup_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
-
-v_div_fixup_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xef,0x0d,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xfe,0x07]
-
-v_div_fixup_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x00]
-
-v_div_fixup_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x96,0x01]
-
-v_div_fixup_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x9a,0x01]
-
-v_div_fixup_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x9e,0x01]
-
-v_div_fixup_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xaa,0x01]
-
-v_div_fixup_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xae,0x01]
-
-v_div_fixup_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xf2,0x01]
-
-v_div_fixup_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xfa,0x01]
-
-v_div_fixup_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xfe,0x01]
-
-v_div_fixup_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x02,0x02]
-
-v_div_fixup_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x06,0x03]
-
-v_div_fixup_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
-
-v_div_fixup_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xde,0x03]
-
-v_div_fixup_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x24]
-
-v_div_fixup_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x44]
-
-v_div_fixup_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x84]
-
-v_div_fixup_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4]
-
-v_div_fixup_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
-// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
-// CHECK: [0x05,0x08,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
-// CHECK: [0x05,0x10,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
-// CHECK: [0x05,0x20,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
-// CHECK: [0x05,0x40,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
-// CHECK: [0x05,0x78,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_div_fixup_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
-
-v_interp_p1ll_f16 v5, v2, attr0.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v255, v2, attr0.x
-// CHECK: [0xff,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr1.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr31.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x1f,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr32.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x20,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v255, attr0.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0xfe,0x03,0x00]
-
-v_interp_p1ll_f16 v5, -v2, attr0.x
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
-
-v_interp_p1ll_f16 v5, |v2|, attr0.x
-// CHECK: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.y
-// CHECK: [0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.z
-// CHECK: [0x05,0x00,0x74,0xd2,0x80,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.w
-// CHECK: [0x05,0x00,0x74,0xd2,0xc0,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x high
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x clamp
-// CHECK: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
-
-v_interp_p1ll_f16 v5, v2, attr0.x mul:2
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x08]
-
-v_interp_p1ll_f16 v5, v2, attr0.x mul:4
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x10]
-
-v_interp_p1ll_f16 v5, v2, attr0.x div:2
-// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v255, v2, attr0.x, v3
-// CHECK: [0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr1.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x01,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr31.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x1f,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr32.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v255, attr0.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0xfe,0x0f,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v255
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0xfe,0x07]
-
-v_interp_p1lv_f16 v5, -v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, -v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
-
-v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
-// CHECK: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
-// CHECK: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.y, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x40,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.z, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0x80,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.w, v3
-// CHECK: [0x05,0x00,0x75,0xd2,0xc0,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
-// CHECK: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x0c]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:4
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14]
-
-v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
-// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x1c]
-
-v_interp_p2_legacy_f16 v5, v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v255, v2, attr0.x, v3
-// CHECK: [0xff,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr1.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr31.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr32.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x20,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v255, attr0.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0xfe,0x0f,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr0.x, v255
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0xfe,0x07]
-
-v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
-
-v_interp_p2_legacy_f16 v5, v2, attr0.x, -v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
-
-v_interp_p2_legacy_f16 v5, |v2|, attr0.x, v3
-// CHECK: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3|
-// CHECK: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr0.y, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x40,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr0.z, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0x80,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr0.w, v3
-// CHECK: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high
-// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
-
-v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp
-// CHECK: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v255, v2, attr0.x, v3
-// CHECK: [0xff,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr1.x, v3
-// CHECK: [0x05,0x00,0x77,0xd2,0x01,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr31.x, v3
-// CHECK: [0x05,0x00,0x77,0xd2,0x1f,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr32.x, v3
-// CHECK: [0x05,0x00,0x77,0xd2,0x20,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v255, attr0.x, v3
-// CHECK: [0x05,0x00,0x77,0xd2,0x00,0xfe,0x0f,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v255
-// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x04,0xfe,0x07]
-
-v_interp_p2_f16 v5, -v2, attr0.x, v3
-// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44]
-
-v_interp_p2_f16 v5, v2, attr0.x, -v3
-// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x84]
-
-v_interp_p2_f16 v5, |v2|, attr0.x, v3
-// CHECK: [0x05,0x02,0x77,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, |v3|
-// CHECK: [0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.y, v3
-// CHECK: [0x05,0x00,0x77,0xd2,0x40,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.z, v3
-// CHECK: [0x05,0x00,0x77,0xd2,0x80,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.w, v3
-// CHECK: [0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v3 high
-// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x04]
-
-v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
-// CHECK: [0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04]
-
-v_add_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0xfe,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x02,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x04,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], s[100:101], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x64,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x66,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x6a,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x7e,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x80,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0xc1,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0xf0,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0xf7,0x04,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x03,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x09,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x0d,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], s[100:101]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xc9,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xcd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd5,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x00,0x00]
-
-v_add_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x01,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x83,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xe1,0x01,0x00]
-
-v_add_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xef,0x01,0x00]
-
-v_add_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x20]
-
-v_add_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x40]
-
-v_add_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x60]
-
-v_add_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x80,0x80,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x08]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x10]
-
-v_add_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x18]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0xfe,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x02,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x04,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], s[100:101], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x64,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x66,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x03,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x09,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x0d,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], s[100:101]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xc9,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x20]
-
-v_mul_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x40]
-
-v_mul_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x60]
-
-v_mul_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x80,0x81,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x08]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x10]
-
-v_mul_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x18]
-
-v_min_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0xfe,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x02,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x04,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], s[100:101], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x64,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x66,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x6a,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x7e,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x80,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0xc1,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0xf0,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0xf7,0x04,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x03,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x09,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x0d,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], s[100:101]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xc9,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xcd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd5,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x00,0x00]
-
-v_min_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x01,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x83,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xe1,0x01,0x00]
-
-v_min_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xef,0x01,0x00]
-
-v_min_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x20]
-
-v_min_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x40]
-
-v_min_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x60]
-
-v_min_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x80,0x82,0xd2,0x01,0x05,0x02,0x00]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x08]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x10]
-
-v_min_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x18]
-
-v_max_f64 v[5:6], v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[254:255], v[1:2], v[2:3]
-// CHECK: [0xfe,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[254:255], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0xfe,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], s[2:3], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x02,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], s[4:5], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x04,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], s[100:101], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x64,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], flat_scratch, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x66,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], vcc, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x6a,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], exec, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x7e,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x80,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0xc1,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0xf0,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0xf7,0x04,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[254:255]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x03,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[4:5]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x09,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[6:7]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x0d,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], s[100:101]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xc9,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], flat_scratch
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xcd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], vcc
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xd5,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], exec
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x00,0x00]
-
-v_max_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x01,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x83,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xe1,0x01,0x00]
-
-v_max_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xef,0x01,0x00]
-
-v_max_f64 v[5:6], -v[1:2], v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x20]
-
-v_max_f64 v[5:6], v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x40]
-
-v_max_f64 v[5:6], -v[1:2], -v[2:3]
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x60]
-
-v_max_f64 v[5:6], |v[1:2]|, v[2:3]
-// CHECK: [0x05,0x01,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], |v[2:3]|
-// CHECK: [0x05,0x02,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|
-// CHECK: [0x05,0x03,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] clamp
-// CHECK: [0x05,0x80,0x83,0xd2,0x01,0x05,0x02,0x00]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] mul:2
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x08]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] mul:4
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x10]
-
-v_max_f64 v[5:6], v[1:2], v[2:3] div:2
-// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x18]
-
-v_ldexp_f64 v[5:6], v[1:2], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[254:255], v[1:2], v2
-// CHECK: [0xfe,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[254:255], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0xfe,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[2:3], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x02,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[4:5], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x04,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], s[100:101], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x64,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], flat_scratch, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x66,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], vcc, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], exec, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], 0, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x80,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], -1, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], 0.5, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], -4.0, v2
-// CHECK: [0x05,0x00,0x84,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v255
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x03,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], s2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], s101
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcb,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], flat_scratch_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcd,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], flat_scratch_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], vcc_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], vcc_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], m0
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], exec_lo
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], exec_hi
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x00,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x01,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x83,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xef,0x01,0x00]
-
-v_ldexp_f64 v[5:6], -v[1:2], v2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x20]
-
-v_ldexp_f64 v[5:6], |v[1:2]|, v2
-// CHECK: [0x05,0x01,0x84,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 clamp
-// CHECK: [0x05,0x80,0x84,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 mul:2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x08]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 mul:4
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x10]
-
-v_ldexp_f64 v[5:6], v[1:2], v2 div:2
-// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x18]
-
-v_mul_lo_u32 v5, v1, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u32 v255, v1, v2
-// CHECK: [0xff,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_lo_u32 v5, v255, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_lo_u32 v5, s1, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, s101, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x65,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x66,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, m0, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, 0, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, -1, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x85,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_lo_u32 v5, v1, v255
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_lo_u32 v5, v1, s2
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, s101
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, m0
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_lo_u32 v5, v1, 0
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, -1
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_lo_u32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32 v255, v1, v2
-// CHECK: [0xff,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_u32 v5, v255, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_hi_u32 v5, s1, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, s101, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x65,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x66,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, m0, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, 0, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, -1, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x86,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_u32 v5, v1, v255
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_hi_u32 v5, v1, s2
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, s101
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, m0
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_hi_u32 v5, v1, 0
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, -1
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_u32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xef,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32 v255, v1, v2
-// CHECK: [0xff,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
-
-v_mul_hi_i32 v5, v255, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0xff,0x05,0x02,0x00]
-
-v_mul_hi_i32 v5, s1, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, s101, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x65,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x66,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x67,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, m0, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, 0, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0x80,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, -1, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x87,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mul_hi_i32 v5, v1, v255
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x03,0x00]
-
-v_mul_hi_i32 v5, v1, s2
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, s101
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, m0
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x00,0x00]
-
-v_mul_hi_i32 v5, v1, 0
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, -1
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x83,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mul_hi_i32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xef,0x01,0x00]
-
-v_ldexp_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0xff,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x65,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x66,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x67,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x6b,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x7c,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x7f,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x80,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ldexp_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x03,0x00]
-
-v_ldexp_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x00,0x00]
-
-v_ldexp_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcb,0x00,0x00]
-
-v_ldexp_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcd,0x00,0x00]
-
-v_ldexp_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcf,0x00,0x00]
-
-v_ldexp_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ldexp_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd7,0x00,0x00]
-
-v_ldexp_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x00,0x00]
-
-v_ldexp_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ldexp_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x00,0x00]
-
-v_ldexp_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x01,0x01,0x00]
-
-v_ldexp_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x83,0x01,0x00]
-
-v_ldexp_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ldexp_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xef,0x01,0x00]
-
-v_ldexp_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x20]
-
-v_ldexp_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x88,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x88,0xd2,0x01,0x05,0x02,0x00]
-
-v_ldexp_f32 v5, v1, v2 mul:2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x08]
-
-v_ldexp_f32 v5, v1, v2 mul:4
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x10]
-
-v_ldexp_f32 v5, v1, v2 div:2
-// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x18]
-
-v_readlane_b32 s5, v1, s2
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 s101, v1, s2
-// CHECK: [0x65,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 flat_scratch_lo, v1, s2
-// CHECK: [0x66,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 flat_scratch_hi, v1, s2
-// CHECK: [0x67,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
-
-v_readlane_b32 s5, v255, s2
-// CHECK: [0x05,0x00,0x89,0xd2,0xff,0x05,0x00,0x00]
-
-v_readlane_b32 s5, v1, s101
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcb,0x00,0x00]
-
-v_readlane_b32 s5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcd,0x00,0x00]
-
-v_readlane_b32 s5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcf,0x00,0x00]
-
-v_readlane_b32 s5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd5,0x00,0x00]
-
-v_readlane_b32 s5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd7,0x00,0x00]
-
-v_readlane_b32 s5, v1, m0
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xf9,0x00,0x00]
-
-v_readlane_b32 s5, v1, 0
-// CHECK: [0x05,0x00,0x89,0xd2,0x01,0x01,0x01,0x00]
-
-v_writelane_b32 v5, 0, s2
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
-
-v_writelane_b32 v255, 0, s2
-// CHECK: [0xff,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
-
-v_writelane_b32 v5, -1, s2
-// CHECK: [0x05,0x00,0x8a,0xd2,0xc1,0x04,0x00,0x00]
-
-v_writelane_b32 v5, 0.5, s2
-// CHECK: [0x05,0x00,0x8a,0xd2,0xf0,0x04,0x00,0x00]
-
-v_writelane_b32 v5, -4.0, s2
-// CHECK: [0x05,0x00,0x8a,0xd2,0xf7,0x04,0x00,0x00]
-
-v_writelane_b32 v5, 0, s101
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xca,0x00,0x00]
-
-v_writelane_b32 v5, 0, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xcc,0x00,0x00]
-
-v_writelane_b32 v5, 0, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xce,0x00,0x00]
-
-v_writelane_b32 v5, 0, vcc_lo
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd4,0x00,0x00]
-
-v_writelane_b32 v5, 0, vcc_hi
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd6,0x00,0x00]
-
-v_writelane_b32 v5, 0, m0
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xf8,0x00,0x00]
-
-v_writelane_b32 v5, 0, 0
-// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x00,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
-
-v_bcnt_u32_b32 v255, v1, v2
-// CHECK: [0xff,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
-
-v_bcnt_u32_b32 v5, v255, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0xff,0x05,0x02,0x00]
-
-v_bcnt_u32_b32 v5, s1, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, s101, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x65,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x66,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x67,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x6a,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x6b,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, m0, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x7c,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x7e,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x7f,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, 0, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x80,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, -1, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0xc1,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0xf0,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x8b,0xd2,0xf7,0x04,0x02,0x00]
-
-v_bcnt_u32_b32 v5, v1, v255
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x03,0x00]
-
-v_bcnt_u32_b32 v5, v1, s2
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, s101
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcb,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcd,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcf,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd5,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd7,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, m0
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf9,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xfd,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x00,0x00]
-
-v_bcnt_u32_b32 v5, v1, 0
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x01,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, -1
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x83,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xe1,0x01,0x00]
-
-v_bcnt_u32_b32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xef,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v255, v1, v2
-// CHECK: [0xff,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v255, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0xff,0x05,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, s1, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, s101, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x65,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x66,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x67,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, m0, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, 0, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x80,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, -1, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x8c,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, v255
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x03,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, s2
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, s101
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, m0
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x00,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, 0
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x01,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, -1
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x83,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mbcnt_lo_u32_b32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xef,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v255, v1, v2
-// CHECK: [0xff,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v255, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0xff,0x05,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, s1, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, s101, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x65,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x66,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x67,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x6a,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x6b,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, m0, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x7c,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x7e,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x7f,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, 0, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x80,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, -1, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0xc1,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0xf0,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x8d,0xd2,0xf7,0x04,0x02,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, v255
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x03,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, s2
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, s101
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcb,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcd,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcf,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd5,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd7,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, m0
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf9,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xfd,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x00,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, 0
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x01,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, -1
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x83,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xe1,0x01,0x00]
-
-v_mbcnt_hi_u32_b32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xef,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b64 v[254:255], v1, v[2:3]
-// CHECK: [0xfe,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], v255, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0xff,0x05,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], s1, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], s101, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x65,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], flat_scratch_lo, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x66,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], flat_scratch_hi, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x67,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], vcc_lo, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], vcc_hi, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x6b,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], m0, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x7c,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], exec_lo, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], exec_hi, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x7f,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x8f,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshlrev_b64 v[5:6], v1, v[254:255]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x03,0x00]
-
-v_lshlrev_b64 v[5:6], v1, s[4:5]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x09,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, s[6:7]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x0d,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, s[100:101]
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xc9,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, flat_scratch
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xcd,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, vcc
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, exec
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshlrev_b64 v[5:6], v1, 0
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, -1
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, 0.5
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshlrev_b64 v[5:6], v1, -4.0
-// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xef,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b64 v[254:255], v1, v[2:3]
-// CHECK: [0xfe,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], v255, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0xff,0x05,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], s1, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], s101, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x65,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], flat_scratch_lo, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x66,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], flat_scratch_hi, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x67,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], vcc_lo, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x6a,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], vcc_hi, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x6b,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], m0, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x7c,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], exec_lo, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x7e,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], exec_hi, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x7f,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0x80,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0xc1,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0xf0,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x90,0xd2,0xf7,0x04,0x02,0x00]
-
-v_lshrrev_b64 v[5:6], v1, v[254:255]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x03,0x00]
-
-v_lshrrev_b64 v[5:6], v1, s[4:5]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x09,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, s[6:7]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x0d,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, s[100:101]
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xc9,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, flat_scratch
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xcd,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, vcc
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd5,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, exec
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x00,0x00]
-
-v_lshrrev_b64 v[5:6], v1, 0
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, -1
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x83,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, 0.5
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xe1,0x01,0x00]
-
-v_lshrrev_b64 v[5:6], v1, -4.0
-// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xef,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i64 v[254:255], v1, v[2:3]
-// CHECK: [0xfe,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], v255, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0xff,0x05,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], s1, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], s101, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x65,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], flat_scratch_lo, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x66,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], flat_scratch_hi, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x67,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], vcc_lo, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x6a,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], vcc_hi, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x6b,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], m0, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x7c,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], exec_lo, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x7e,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], exec_hi, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x7f,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], 0, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0x80,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], -1, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0xc1,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], 0.5, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0xf0,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], -4.0, v[2:3]
-// CHECK: [0x05,0x00,0x91,0xd2,0xf7,0x04,0x02,0x00]
-
-v_ashrrev_i64 v[5:6], v1, v[254:255]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x03,0x00]
-
-v_ashrrev_i64 v[5:6], v1, s[4:5]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x09,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, s[6:7]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x0d,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, s[100:101]
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xc9,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, flat_scratch
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xcd,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, vcc
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xd5,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, exec
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x00,0x00]
-
-v_ashrrev_i64 v[5:6], v1, 0
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, -1
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x83,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, 0.5
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xe1,0x01,0x00]
-
-v_ashrrev_i64 v[5:6], v1, -4.0
-// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xef,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[254:255], v[1:2], v2
-// CHECK: [0xfe,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[254:255], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0xfe,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[2:3], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x02,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[4:5], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x04,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], s[100:101], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x64,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], flat_scratch, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x66,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], vcc, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x6a,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], exec, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x7e,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], 0, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x80,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], -1, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0xc1,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], 0.5, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0xf0,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], -4.0, v2
-// CHECK: [0x05,0x00,0x92,0xd2,0xf7,0x04,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v255
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x03,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], s2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], s101
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcb,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcd,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcf,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], vcc_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd5,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], vcc_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd7,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], m0
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], exec_lo
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfd,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], exec_hi
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x00,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], 0
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x01,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], -1
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x83,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], 0.5
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xe1,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], -4.0
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xef,0x01,0x00]
-
-v_trig_preop_f64 v[5:6], -v[1:2], v2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x20]
-
-v_trig_preop_f64 v[5:6], |v[1:2]|, v2
-// CHECK: [0x05,0x01,0x92,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 clamp
-// CHECK: [0x05,0x80,0x92,0xd2,0x01,0x05,0x02,0x00]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 mul:2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x08]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 mul:4
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x10]
-
-v_trig_preop_f64 v[5:6], v[1:2], v2 div:2
-// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x18]
-
-v_bfm_b32 v5, v1, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
-
-v_bfm_b32 v255, v1, v2
-// CHECK: [0xff,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
-
-v_bfm_b32 v5, v255, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0xff,0x05,0x02,0x00]
-
-v_bfm_b32 v5, s1, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x04,0x02,0x00]
-
-v_bfm_b32 v5, s101, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x65,0x04,0x02,0x00]
-
-v_bfm_b32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x66,0x04,0x02,0x00]
-
-v_bfm_b32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x67,0x04,0x02,0x00]
-
-v_bfm_b32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x6a,0x04,0x02,0x00]
-
-v_bfm_b32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x6b,0x04,0x02,0x00]
-
-v_bfm_b32 v5, m0, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x7c,0x04,0x02,0x00]
-
-v_bfm_b32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x7e,0x04,0x02,0x00]
-
-v_bfm_b32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x7f,0x04,0x02,0x00]
-
-v_bfm_b32 v5, 0, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0x80,0x04,0x02,0x00]
-
-v_bfm_b32 v5, -1, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0xc1,0x04,0x02,0x00]
-
-v_bfm_b32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0xf0,0x04,0x02,0x00]
-
-v_bfm_b32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x93,0xd2,0xf7,0x04,0x02,0x00]
-
-v_bfm_b32 v5, v1, v255
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x03,0x00]
-
-v_bfm_b32 v5, v1, s2
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x00,0x00]
-
-v_bfm_b32 v5, v1, s101
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcb,0x00,0x00]
-
-v_bfm_b32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcd,0x00,0x00]
-
-v_bfm_b32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcf,0x00,0x00]
-
-v_bfm_b32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd5,0x00,0x00]
-
-v_bfm_b32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd7,0x00,0x00]
-
-v_bfm_b32 v5, v1, m0
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf9,0x00,0x00]
-
-v_bfm_b32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xfd,0x00,0x00]
-
-v_bfm_b32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x00,0x00]
-
-v_bfm_b32 v5, v1, 0
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x01,0x01,0x00]
-
-v_bfm_b32 v5, v1, -1
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x83,0x01,0x00]
-
-v_bfm_b32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xe1,0x01,0x00]
-
-v_bfm_b32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_i16_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_i16_f32 v5, v1, -v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_i16_f32 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_i16_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f32 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x94,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_u16_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_u16_f32 v5, v1, -v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_u16_f32 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_u16_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f32 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x95,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v255, v1, v2
-// CHECK: [0xff,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v255, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, s1, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, s101, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, m0, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, 0, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, -1, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, v255
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, s2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, s101
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, m0
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, 0
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, -1
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, -v1, v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pkrtz_f16_f32 v5, v1, -v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pkrtz_f16_f32 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pkrtz_f16_f32 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pkrtz_f16_f32 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x96,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v255, v1, v2
-// CHECK: [0xff,0x00,0x97,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v255, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, s1, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, s101, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, m0, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, 0, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, -1, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x97,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, v255
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, s2
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, s101
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, m0
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, 0
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, -1
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pk_u16_u32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32 v255, v1, v2
-// CHECK: [0xff,0x00,0x98,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, v255, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, s1, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, s101, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, m0, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, 0, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, -1, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x98,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, v255
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, s2
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, s101
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, m0
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, 0
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, -1
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pk_i16_i32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v255, v1, v2
-// CHECK: [0xff,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v255, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, s1, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, s101, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, m0, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, 0, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, -1, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v255
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, s2
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, s101
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, m0
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, 0
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, -1
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_i16_f16 v5, -v1, v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_i16_f16 v5, v1, -v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_i16_f16 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_i16_f16 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,0]
-// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,0,0]
-// CHECK: [0x05,0x08,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,1,0]
-// CHECK: [0x05,0x10,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,1]
-// CHECK: [0x05,0x40,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,1,1]
-// CHECK: [0x05,0x58,0x99,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v255, v1, v2
-// CHECK: [0xff,0x00,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v255, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0xff,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, s1, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, s101, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x65,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x66,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x67,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x6a,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x6b,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, m0, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x7c,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x7e,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x7f,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, 0, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x80,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, -1, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0xc1,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0xf0,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0xf7,0x04,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v255
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xff,0x03,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, s2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, s101
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xcb,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xcd,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xcf,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd5,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd7,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, m0
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf9,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xfd,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xff,0x00,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, 0
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x01,0x01,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, -1
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x83,0x01,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xe1,0x01,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xef,0x01,0x00]
-
-v_cvt_pknorm_u16_f16 v5, -v1, v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x20]
-
-v_cvt_pknorm_u16_f16 v5, v1, -v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x40]
-
-v_cvt_pknorm_u16_f16 v5, -v1, -v2
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x60]
-
-v_cvt_pknorm_u16_f16 v5, |v1|, v2
-// CHECK: [0x05,0x01,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, |v2|
-// CHECK: [0x05,0x02,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,0]
-// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,0,0]
-// CHECK: [0x05,0x08,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,1,0]
-// CHECK: [0x05,0x10,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,1]
-// CHECK: [0x05,0x40,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1]
-// CHECK: [0x05,0x58,0x9a,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32 v5, v1, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32 v255, v1, v2
-// CHECK: [0xff,0x00,0x9c,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i32 v5, v255, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0xff,0x05,0x02,0x00]
-
-v_add_i32 v5, s1, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x04,0x02,0x00]
-
-v_add_i32 v5, s101, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x65,0x04,0x02,0x00]
-
-v_add_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x66,0x04,0x02,0x00]
-
-v_add_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x67,0x04,0x02,0x00]
-
-v_add_i32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x6a,0x04,0x02,0x00]
-
-v_add_i32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x6b,0x04,0x02,0x00]
-
-v_add_i32 v5, m0, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x7c,0x04,0x02,0x00]
-
-v_add_i32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x7e,0x04,0x02,0x00]
-
-v_add_i32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x7f,0x04,0x02,0x00]
-
-v_add_i32 v5, 0, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x80,0x04,0x02,0x00]
-
-v_add_i32 v5, -1, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0xc1,0x04,0x02,0x00]
-
-v_add_i32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0xf0,0x04,0x02,0x00]
-
-v_add_i32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x9c,0xd2,0xf7,0x04,0x02,0x00]
-
-v_add_i32 v5, v1, v255
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xff,0x03,0x00]
-
-v_add_i32 v5, v1, s2
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x00,0x00]
-
-v_add_i32 v5, v1, s101
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xcb,0x00,0x00]
-
-v_add_i32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xcd,0x00,0x00]
-
-v_add_i32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xcf,0x00,0x00]
-
-v_add_i32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd5,0x00,0x00]
-
-v_add_i32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd7,0x00,0x00]
-
-v_add_i32 v5, v1, m0
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf9,0x00,0x00]
-
-v_add_i32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xfd,0x00,0x00]
-
-v_add_i32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xff,0x00,0x00]
-
-v_add_i32 v5, v1, 0
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x01,0x01,0x00]
-
-v_add_i32 v5, v1, -1
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x83,0x01,0x00]
-
-v_add_i32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xe1,0x01,0x00]
-
-v_add_i32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xef,0x01,0x00]
-
-v_sub_i32 v5, v1, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32 v255, v1, v2
-// CHECK: [0xff,0x00,0x9d,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i32 v5, v255, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0xff,0x05,0x02,0x00]
-
-v_sub_i32 v5, s1, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x04,0x02,0x00]
-
-v_sub_i32 v5, s101, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x65,0x04,0x02,0x00]
-
-v_sub_i32 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x66,0x04,0x02,0x00]
-
-v_sub_i32 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x67,0x04,0x02,0x00]
-
-v_sub_i32 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x6a,0x04,0x02,0x00]
-
-v_sub_i32 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x6b,0x04,0x02,0x00]
-
-v_sub_i32 v5, m0, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x7c,0x04,0x02,0x00]
-
-v_sub_i32 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x7e,0x04,0x02,0x00]
-
-v_sub_i32 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x7f,0x04,0x02,0x00]
-
-v_sub_i32 v5, 0, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x80,0x04,0x02,0x00]
-
-v_sub_i32 v5, -1, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0xc1,0x04,0x02,0x00]
-
-v_sub_i32 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0xf0,0x04,0x02,0x00]
-
-v_sub_i32 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x9d,0xd2,0xf7,0x04,0x02,0x00]
-
-v_sub_i32 v5, v1, v255
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xff,0x03,0x00]
-
-v_sub_i32 v5, v1, s2
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x05,0x00,0x00]
-
-v_sub_i32 v5, v1, s101
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xcb,0x00,0x00]
-
-v_sub_i32 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xcd,0x00,0x00]
-
-v_sub_i32 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xcf,0x00,0x00]
-
-v_sub_i32 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xd5,0x00,0x00]
-
-v_sub_i32 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xd7,0x00,0x00]
-
-v_sub_i32 v5, v1, m0
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xf9,0x00,0x00]
-
-v_sub_i32 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xfd,0x00,0x00]
-
-v_sub_i32 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xff,0x00,0x00]
-
-v_sub_i32 v5, v1, 0
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x01,0x01,0x00]
-
-v_sub_i32 v5, v1, -1
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x83,0x01,0x00]
-
-v_sub_i32 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xe1,0x01,0x00]
-
-v_sub_i32 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xef,0x01,0x00]
-
-v_add_i16 v5, v1, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i16 v255, v1, v2
-// CHECK: [0xff,0x00,0x9e,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i16 v5, v255, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0xff,0x05,0x02,0x00]
-
-v_add_i16 v5, s1, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x04,0x02,0x00]
-
-v_add_i16 v5, s101, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x65,0x04,0x02,0x00]
-
-v_add_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x66,0x04,0x02,0x00]
-
-v_add_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x67,0x04,0x02,0x00]
-
-v_add_i16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x6a,0x04,0x02,0x00]
-
-v_add_i16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x6b,0x04,0x02,0x00]
-
-v_add_i16 v5, m0, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x7c,0x04,0x02,0x00]
-
-v_add_i16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x7e,0x04,0x02,0x00]
-
-v_add_i16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x7f,0x04,0x02,0x00]
-
-v_add_i16 v5, 0, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x80,0x04,0x02,0x00]
-
-v_add_i16 v5, -1, v2
-// CHECK: [0x05,0x00,0x9e,0xd2,0xc1,0x04,0x02,0x00]
-
-v_add_i16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_add_i16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_add_i16 v5, v1, v255
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xff,0x03,0x00]
-
-v_add_i16 v5, v1, s2
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x00,0x00]
-
-v_add_i16 v5, v1, s101
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xcb,0x00,0x00]
-
-v_add_i16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xcd,0x00,0x00]
-
-v_add_i16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xcf,0x00,0x00]
-
-v_add_i16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd5,0x00,0x00]
-
-v_add_i16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd7,0x00,0x00]
-
-v_add_i16 v5, v1, m0
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf9,0x00,0x00]
-
-v_add_i16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xfd,0x00,0x00]
-
-v_add_i16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xff,0x00,0x00]
-
-v_add_i16 v5, v1, 0
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x01,0x01,0x00]
-
-v_add_i16 v5, v1, -1
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x83,0x01,0x00]
-
-v_add_i16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_add_i16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_add_i16 v5, v1, v2 op_sel:[0,0,0]
-// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i16 v5, v1, v2 op_sel:[1,0,0]
-// CHECK: [0x05,0x08,0x9e,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i16 v5, v1, v2 op_sel:[0,1,0]
-// CHECK: [0x05,0x10,0x9e,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i16 v5, v1, v2 op_sel:[0,0,1]
-// CHECK: [0x05,0x40,0x9e,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i16 v5, v1, v2 op_sel:[1,1,1]
-// CHECK: [0x05,0x58,0x9e,0xd2,0x01,0x05,0x02,0x00]
-
-v_add_i16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x9e,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i16 v5, v1, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i16 v255, v1, v2
-// CHECK: [0xff,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i16 v5, v255, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0xff,0x05,0x02,0x00]
-
-v_sub_i16 v5, s1, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x04,0x02,0x00]
-
-v_sub_i16 v5, s101, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x65,0x04,0x02,0x00]
-
-v_sub_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x66,0x04,0x02,0x00]
-
-v_sub_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x67,0x04,0x02,0x00]
-
-v_sub_i16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x6a,0x04,0x02,0x00]
-
-v_sub_i16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x6b,0x04,0x02,0x00]
-
-v_sub_i16 v5, m0, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x7c,0x04,0x02,0x00]
-
-v_sub_i16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x7e,0x04,0x02,0x00]
-
-v_sub_i16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x7f,0x04,0x02,0x00]
-
-v_sub_i16 v5, 0, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x80,0x04,0x02,0x00]
-
-v_sub_i16 v5, -1, v2
-// CHECK: [0x05,0x00,0x9f,0xd2,0xc1,0x04,0x02,0x00]
-
-v_sub_i16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_i16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_i16 v5, v1, v255
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xff,0x03,0x00]
-
-v_sub_i16 v5, v1, s2
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x00,0x00]
-
-v_sub_i16 v5, v1, s101
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xcb,0x00,0x00]
-
-v_sub_i16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xcd,0x00,0x00]
-
-v_sub_i16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xcf,0x00,0x00]
-
-v_sub_i16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xd5,0x00,0x00]
-
-v_sub_i16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xd7,0x00,0x00]
-
-v_sub_i16 v5, v1, m0
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xf9,0x00,0x00]
-
-v_sub_i16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xfd,0x00,0x00]
-
-v_sub_i16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xff,0x00,0x00]
-
-v_sub_i16 v5, v1, 0
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x01,0x01,0x00]
-
-v_sub_i16 v5, v1, -1
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x83,0x01,0x00]
-
-v_sub_i16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_i16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_sub_i16 v5, v1, v2 op_sel:[0,0,0]
-// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i16 v5, v1, v2 op_sel:[1,0,0]
-// CHECK: [0x05,0x08,0x9f,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i16 v5, v1, v2 op_sel:[0,1,0]
-// CHECK: [0x05,0x10,0x9f,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i16 v5, v1, v2 op_sel:[0,0,1]
-// CHECK: [0x05,0x40,0x9f,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i16 v5, v1, v2 op_sel:[1,1,1]
-// CHECK: [0x05,0x58,0x9f,0xd2,0x01,0x05,0x02,0x00]
-
-v_sub_i16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x9f,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v255, v1, v2
-// CHECK: [0xff,0x00,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v255, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0xff,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, s1, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, s101, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x65,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x66,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x67,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x6a,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x6b,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, m0, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x7c,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x7e,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x7f,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, 0, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x80,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, -1, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0xc1,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, 0.5, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0xf0,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, -4.0, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0xf7,0x04,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v255
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xff,0x03,0x00]
-
-v_pack_b32_f16 v5, v1, s2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, s101
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xcb,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xcd,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xcf,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd5,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd7,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, m0
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf9,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xfd,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xff,0x00,0x00]
-
-v_pack_b32_f16 v5, v1, 0
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x01,0x01,0x00]
-
-v_pack_b32_f16 v5, v1, -1
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x83,0x01,0x00]
-
-v_pack_b32_f16 v5, v1, 0.5
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xe1,0x01,0x00]
-
-v_pack_b32_f16 v5, v1, -4.0
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xef,0x01,0x00]
-
-v_pack_b32_f16 v5, -v1, v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x20]
-
-v_pack_b32_f16 v5, v1, -v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x40]
-
-v_pack_b32_f16 v5, -v1, -v2
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x60]
-
-v_pack_b32_f16 v5, |v1|, v2
-// CHECK: [0x05,0x01,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, |v2|
-// CHECK: [0x05,0x02,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, |v1|, |v2|
-// CHECK: [0x05,0x03,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,0]
-// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[1,0,0]
-// CHECK: [0x05,0x08,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[0,1,0]
-// CHECK: [0x05,0x10,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,1]
-// CHECK: [0x05,0x40,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pack_b32_f16 v5, v1, v2 op_sel:[1,1,1]
-// CHECK: [0x05,0x58,0xa0,0xd2,0x01,0x05,0x02,0x00]
-
-v_pk_mad_i16 v5, v1, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_i16 v255, v1, v2, v3
-// CHECK: [0xff,0x40,0x80,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_i16 v5, v255, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0xff,0x05,0x0e,0x1c]
-
-v_pk_mad_i16 v5, s1, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, s101, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x65,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x66,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x67,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x6a,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x6b,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, m0, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x7c,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x7e,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x7f,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, 0, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x80,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, -1, v2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0xc1,0x04,0x0e,0x1c]
-
-v_pk_mad_i16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_i16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_i16 v5, v1, v255, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xff,0x0f,0x1c]
-
-v_pk_mad_i16 v5, v1, s2, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0c,0x1c]
-
-v_pk_mad_i16 v5, v1, s101, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xcb,0x0c,0x1c]
-
-v_pk_mad_i16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xcd,0x0c,0x1c]
-
-v_pk_mad_i16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xcf,0x0c,0x1c]
-
-v_pk_mad_i16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xd5,0x0c,0x1c]
-
-v_pk_mad_i16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xd7,0x0c,0x1c]
-
-v_pk_mad_i16 v5, v1, m0, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xf9,0x0c,0x1c]
-
-v_pk_mad_i16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xfd,0x0c,0x1c]
-
-v_pk_mad_i16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xff,0x0c,0x1c]
-
-v_pk_mad_i16 v5, v1, 0, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x01,0x0d,0x1c]
-
-v_pk_mad_i16 v5, v1, -1, v3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x83,0x0d,0x1c]
-
-v_pk_mad_i16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_i16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_i16 v5, v1, v2, v255
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xfe,0x1f]
-
-v_pk_mad_i16 v5, v1, v2, s3
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x18]
-
-v_pk_mad_i16 v5, v1, v2, s101
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x96,0x19]
-
-v_pk_mad_i16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x9a,0x19]
-
-v_pk_mad_i16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x9e,0x19]
-
-v_pk_mad_i16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xaa,0x19]
-
-v_pk_mad_i16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xae,0x19]
-
-v_pk_mad_i16 v5, v1, v2, m0
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xf2,0x19]
-
-v_pk_mad_i16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xfa,0x19]
-
-v_pk_mad_i16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xfe,0x19]
-
-v_pk_mad_i16 v5, v1, v2, 0
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x02,0x1a]
-
-v_pk_mad_i16 v5, v1, v2, -1
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x06,0x1b]
-
-v_pk_mad_i16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_i16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_i16 v5, v1, v2, v3 op_sel:[1,0,0]
-// CHECK: [0x05,0x48,0x80,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_i16 v5, v1, v2, v3 op_sel:[0,1,0]
-// CHECK: [0x05,0x50,0x80,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_i16 v5, v1, v2, v3 op_sel:[0,0,1]
-// CHECK: [0x05,0x60,0x80,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1]
-// CHECK: [0x05,0x78,0x80,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_i16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
-// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x05,0x0e,0x04]
-
-v_pk_mad_i16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
-// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x05,0x0e,0x0c]
-
-v_pk_mad_i16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
-// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x05,0x0e,0x14]
-
-v_pk_mad_i16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
-// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x04]
-
-v_pk_mad_i16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0xc0,0x80,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mul_lo_u16 v5, v1, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_lo_u16 v255, v1, v2
-// CHECK: [0xff,0x00,0x81,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, v255, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, s1, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, s101, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, m0, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, 0, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, -1, v2
-// CHECK: [0x05,0x00,0x81,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mul_lo_u16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mul_lo_u16 v5, v1, v255
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_mul_lo_u16 v5, v1, s2
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_mul_lo_u16 v5, v1, s101
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_mul_lo_u16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_mul_lo_u16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_mul_lo_u16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_mul_lo_u16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_mul_lo_u16 v5, v1, m0
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_mul_lo_u16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_mul_lo_u16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_mul_lo_u16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, v1, 0
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_mul_lo_u16 v5, v1, -1
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_mul_lo_u16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mul_lo_u16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mul_lo_u16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x81,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x81,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x81,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_lo_u16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_mul_lo_u16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_mul_lo_u16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_add_i16 v5, v1, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_i16 v255, v1, v2
-// CHECK: [0xff,0x00,0x82,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_i16 v5, v255, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_add_i16 v5, s1, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, s101, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, m0, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, 0, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, -1, v2
-// CHECK: [0x05,0x00,0x82,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_add_i16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_add_i16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_add_i16 v5, v1, v255
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_add_i16 v5, v1, s2
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_add_i16 v5, v1, s101
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_add_i16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_add_i16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_add_i16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_add_i16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_add_i16 v5, v1, m0
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_add_i16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_add_i16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_add_i16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_i16 v5, v1, 0
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_add_i16 v5, v1, -1
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_add_i16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_add_i16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_add_i16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x82,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_i16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x82,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_i16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x82,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_i16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_i16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_add_i16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_add_i16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_add_i16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x82,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_i16 v5, v1, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_i16 v255, v1, v2
-// CHECK: [0xff,0x00,0x83,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_i16 v5, v255, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_sub_i16 v5, s1, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, s101, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, m0, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, 0, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, -1, v2
-// CHECK: [0x05,0x00,0x83,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_sub_i16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_sub_i16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_sub_i16 v5, v1, v255
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_sub_i16 v5, v1, s2
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_sub_i16 v5, v1, s101
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_sub_i16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_sub_i16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_sub_i16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_sub_i16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_sub_i16 v5, v1, m0
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_sub_i16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_sub_i16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_sub_i16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_i16 v5, v1, 0
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_sub_i16 v5, v1, -1
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_sub_i16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_sub_i16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_sub_i16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x83,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_i16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x83,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_i16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x83,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_i16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_i16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_sub_i16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_sub_i16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_sub_i16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x83,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, v1, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshlrev_b16 v255, v1, v2
-// CHECK: [0xff,0x00,0x84,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, v255, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, s1, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, s101, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, m0, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, 0, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, -1, v2
-// CHECK: [0x05,0x00,0x84,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_lshlrev_b16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_lshlrev_b16 v5, v1, v255
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_lshlrev_b16 v5, v1, s2
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_lshlrev_b16 v5, v1, s101
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_lshlrev_b16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_lshlrev_b16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_lshlrev_b16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_lshlrev_b16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_lshlrev_b16 v5, v1, m0
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_lshlrev_b16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_lshlrev_b16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_lshlrev_b16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, v1, 0
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_lshlrev_b16 v5, v1, -1
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_lshlrev_b16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_lshlrev_b16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_lshlrev_b16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x84,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x84,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x84,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshlrev_b16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_lshlrev_b16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_lshlrev_b16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_lshrrev_b16 v5, v1, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshrrev_b16 v255, v1, v2
-// CHECK: [0xff,0x00,0x85,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, v255, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, s1, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, s101, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, m0, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, 0, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, -1, v2
-// CHECK: [0x05,0x00,0x85,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_lshrrev_b16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_lshrrev_b16 v5, v1, v255
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_lshrrev_b16 v5, v1, s2
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_lshrrev_b16 v5, v1, s101
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_lshrrev_b16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_lshrrev_b16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_lshrrev_b16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_lshrrev_b16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_lshrrev_b16 v5, v1, m0
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_lshrrev_b16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_lshrrev_b16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_lshrrev_b16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, v1, 0
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_lshrrev_b16 v5, v1, -1
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_lshrrev_b16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_lshrrev_b16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_lshrrev_b16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x85,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x85,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x85,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_lshrrev_b16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_lshrrev_b16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_lshrrev_b16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_ashrrev_i16 v5, v1, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_ashrrev_i16 v255, v1, v2
-// CHECK: [0xff,0x00,0x86,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, v255, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, s1, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, s101, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, m0, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, 0, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, -1, v2
-// CHECK: [0x05,0x00,0x86,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_ashrrev_i16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_ashrrev_i16 v5, v1, v255
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_ashrrev_i16 v5, v1, s2
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_ashrrev_i16 v5, v1, s101
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_ashrrev_i16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_ashrrev_i16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_ashrrev_i16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_ashrrev_i16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_ashrrev_i16 v5, v1, m0
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_ashrrev_i16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_ashrrev_i16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_ashrrev_i16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, v1, 0
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_ashrrev_i16 v5, v1, -1
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_ashrrev_i16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_ashrrev_i16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_ashrrev_i16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x86,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x86,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x86,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_ashrrev_i16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_ashrrev_i16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_ashrrev_i16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_max_i16 v5, v1, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_i16 v255, v1, v2
-// CHECK: [0xff,0x00,0x87,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_i16 v5, v255, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_max_i16 v5, s1, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, s101, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, m0, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, 0, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, -1, v2
-// CHECK: [0x05,0x00,0x87,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_max_i16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_max_i16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_max_i16 v5, v1, v255
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_max_i16 v5, v1, s2
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_max_i16 v5, v1, s101
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_max_i16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_max_i16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_max_i16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_max_i16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_max_i16 v5, v1, m0
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_max_i16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_max_i16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_max_i16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_i16 v5, v1, 0
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_max_i16 v5, v1, -1
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_max_i16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_max_i16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_max_i16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x87,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_i16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x87,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_i16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x87,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_i16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_i16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_max_i16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_max_i16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_min_i16 v5, v1, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_i16 v255, v1, v2
-// CHECK: [0xff,0x00,0x88,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_i16 v5, v255, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_min_i16 v5, s1, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, s101, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, m0, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, 0, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, -1, v2
-// CHECK: [0x05,0x00,0x88,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_min_i16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_min_i16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_min_i16 v5, v1, v255
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_min_i16 v5, v1, s2
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_min_i16 v5, v1, s101
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_min_i16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_min_i16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_min_i16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_min_i16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_min_i16 v5, v1, m0
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_min_i16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_min_i16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_min_i16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_i16 v5, v1, 0
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_min_i16 v5, v1, -1
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_min_i16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_min_i16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_min_i16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x88,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_i16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x88,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_i16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x88,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_i16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_i16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_min_i16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_min_i16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_mad_u16 v5, v1, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_u16 v255, v1, v2, v3
-// CHECK: [0xff,0x40,0x89,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_u16 v5, v255, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0xff,0x05,0x0e,0x1c]
-
-v_pk_mad_u16 v5, s1, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, s101, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x65,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x66,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x67,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x6a,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x6b,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, m0, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x7c,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x7e,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x7f,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, 0, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x80,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, -1, v2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0xc1,0x04,0x0e,0x1c]
-
-v_pk_mad_u16 v5, 0.5, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_u16 v5, -4.0, v2, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_u16 v5, v1, v255, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xff,0x0f,0x1c]
-
-v_pk_mad_u16 v5, v1, s2, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0c,0x1c]
-
-v_pk_mad_u16 v5, v1, s101, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xcb,0x0c,0x1c]
-
-v_pk_mad_u16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xcd,0x0c,0x1c]
-
-v_pk_mad_u16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xcf,0x0c,0x1c]
-
-v_pk_mad_u16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xd5,0x0c,0x1c]
-
-v_pk_mad_u16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xd7,0x0c,0x1c]
-
-v_pk_mad_u16 v5, v1, m0, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xf9,0x0c,0x1c]
-
-v_pk_mad_u16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xfd,0x0c,0x1c]
-
-v_pk_mad_u16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xff,0x0c,0x1c]
-
-v_pk_mad_u16 v5, v1, 0, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x01,0x0d,0x1c]
-
-v_pk_mad_u16 v5, v1, -1, v3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x83,0x0d,0x1c]
-
-v_pk_mad_u16 v5, v1, 0.5, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_u16 v5, v1, -4.0, v3
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_u16 v5, v1, v2, v255
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xfe,0x1f]
-
-v_pk_mad_u16 v5, v1, v2, s3
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0e,0x18]
-
-v_pk_mad_u16 v5, v1, v2, s101
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x96,0x19]
-
-v_pk_mad_u16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x9a,0x19]
-
-v_pk_mad_u16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x9e,0x19]
-
-v_pk_mad_u16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xaa,0x19]
-
-v_pk_mad_u16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xae,0x19]
-
-v_pk_mad_u16 v5, v1, v2, m0
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xf2,0x19]
-
-v_pk_mad_u16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xfa,0x19]
-
-v_pk_mad_u16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xfe,0x19]
-
-v_pk_mad_u16 v5, v1, v2, 0
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x02,0x1a]
-
-v_pk_mad_u16 v5, v1, v2, -1
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x06,0x1b]
-
-v_pk_mad_u16 v5, v1, v2, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_u16 v5, v1, v2, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0]
-// CHECK: [0x05,0x48,0x89,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_u16 v5, v1, v2, v3 op_sel:[0,1,0]
-// CHECK: [0x05,0x50,0x89,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_u16 v5, v1, v2, v3 op_sel:[0,0,1]
-// CHECK: [0x05,0x60,0x89,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1]
-// CHECK: [0x05,0x78,0x89,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_mad_u16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
-// CHECK: [0x05,0x00,0x89,0xd3,0x01,0x05,0x0e,0x04]
-
-v_pk_mad_u16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
-// CHECK: [0x05,0x00,0x89,0xd3,0x01,0x05,0x0e,0x0c]
-
-v_pk_mad_u16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
-// CHECK: [0x05,0x00,0x89,0xd3,0x01,0x05,0x0e,0x14]
-
-v_pk_mad_u16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
-// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0e,0x04]
-
-v_pk_mad_u16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0xc0,0x89,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_add_u16 v5, v1, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_u16 v255, v1, v2
-// CHECK: [0xff,0x00,0x8a,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_u16 v5, v255, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_add_u16 v5, s1, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, s101, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, m0, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, 0, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, -1, v2
-// CHECK: [0x05,0x00,0x8a,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_add_u16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_add_u16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_add_u16 v5, v1, v255
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_add_u16 v5, v1, s2
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_add_u16 v5, v1, s101
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_add_u16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_add_u16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_add_u16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_add_u16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_add_u16 v5, v1, m0
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_add_u16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_add_u16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_add_u16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_u16 v5, v1, 0
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_add_u16 v5, v1, -1
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_add_u16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_add_u16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_add_u16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x8a,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_u16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x8a,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_u16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x8a,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_u16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_u16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_add_u16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_add_u16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_add_u16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x8a,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_u16 v5, v1, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_u16 v255, v1, v2
-// CHECK: [0xff,0x00,0x8b,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_u16 v5, v255, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_sub_u16 v5, s1, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, s101, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, m0, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, 0, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, -1, v2
-// CHECK: [0x05,0x00,0x8b,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_sub_u16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_sub_u16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_sub_u16 v5, v1, v255
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_sub_u16 v5, v1, s2
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_sub_u16 v5, v1, s101
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_sub_u16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_sub_u16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_sub_u16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_sub_u16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_sub_u16 v5, v1, m0
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_sub_u16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_sub_u16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_sub_u16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_u16 v5, v1, 0
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_sub_u16 v5, v1, -1
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_sub_u16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_sub_u16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_sub_u16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x8b,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_u16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x8b,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_u16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x8b,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_u16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_sub_u16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_sub_u16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_sub_u16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_sub_u16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x8b,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_u16 v5, v1, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_u16 v255, v1, v2
-// CHECK: [0xff,0x00,0x8c,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_u16 v5, v255, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_max_u16 v5, s1, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, s101, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, m0, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, 0, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, -1, v2
-// CHECK: [0x05,0x00,0x8c,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_max_u16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_max_u16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_max_u16 v5, v1, v255
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_max_u16 v5, v1, s2
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_max_u16 v5, v1, s101
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_max_u16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_max_u16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_max_u16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_max_u16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_max_u16 v5, v1, m0
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_max_u16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_max_u16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_max_u16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_u16 v5, v1, 0
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_max_u16 v5, v1, -1
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_max_u16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_max_u16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_max_u16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x8c,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_u16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x8c,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_u16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x8c,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_u16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_u16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_max_u16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_max_u16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_min_u16 v5, v1, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_u16 v255, v1, v2
-// CHECK: [0xff,0x00,0x8d,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_u16 v5, v255, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_min_u16 v5, s1, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, s101, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, m0, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, 0, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, -1, v2
-// CHECK: [0x05,0x00,0x8d,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_min_u16 v5, 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_min_u16 v5, -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_min_u16 v5, v1, v255
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_min_u16 v5, v1, s2
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_min_u16 v5, v1, s101
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_min_u16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_min_u16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_min_u16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_min_u16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_min_u16 v5, v1, m0
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_min_u16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_min_u16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_min_u16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_u16 v5, v1, 0
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_min_u16 v5, v1, -1
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_min_u16 v5, v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_min_u16 v5, v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_pk_min_u16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x8d,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_u16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x8d,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_u16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x8d,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_u16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_u16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_min_u16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_min_u16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_fma_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0xff,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x65,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x66,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x67,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x6a,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x6b,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x7c,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x7e,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x7f,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x80,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0xc1,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0xf0,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0xf7,0x04,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xff,0x0f,0x1c]
-
-v_pk_fma_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0c,0x1c]
-
-v_pk_fma_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xcb,0x0c,0x1c]
-
-v_pk_fma_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xcd,0x0c,0x1c]
-
-v_pk_fma_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xcf,0x0c,0x1c]
-
-v_pk_fma_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xd5,0x0c,0x1c]
-
-v_pk_fma_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xd7,0x0c,0x1c]
-
-v_pk_fma_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xf9,0x0c,0x1c]
-
-v_pk_fma_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xfd,0x0c,0x1c]
-
-v_pk_fma_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xff,0x0c,0x1c]
-
-v_pk_fma_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x01,0x0d,0x1c]
-
-v_pk_fma_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x83,0x0d,0x1c]
-
-v_pk_fma_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xe1,0x0d,0x1c]
-
-v_pk_fma_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xef,0x0d,0x1c]
-
-v_pk_fma_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xfe,0x1f]
-
-v_pk_fma_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x18]
-
-v_pk_fma_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x96,0x19]
-
-v_pk_fma_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x9a,0x19]
-
-v_pk_fma_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x9e,0x19]
-
-v_pk_fma_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xaa,0x19]
-
-v_pk_fma_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xae,0x19]
-
-v_pk_fma_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xf2,0x19]
-
-v_pk_fma_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xfa,0x19]
-
-v_pk_fma_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xfe,0x19]
-
-v_pk_fma_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x02,0x1a]
-
-v_pk_fma_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x06,0x1b]
-
-v_pk_fma_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xc2,0x1b]
-
-v_pk_fma_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xde,0x1b]
-
-v_pk_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0]
-// CHECK: [0x05,0x48,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0]
-// CHECK: [0x05,0x50,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v1, v2, v3 op_sel:[0,0,1]
-// CHECK: [0x05,0x60,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1]
-// CHECK: [0x05,0x78,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
-// CHECK: [0x05,0x00,0x8e,0xd3,0x01,0x05,0x0e,0x04]
-
-v_pk_fma_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
-// CHECK: [0x05,0x00,0x8e,0xd3,0x01,0x05,0x0e,0x0c]
-
-v_pk_fma_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
-// CHECK: [0x05,0x00,0x8e,0xd3,0x01,0x05,0x0e,0x14]
-
-v_pk_fma_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x04]
-
-v_pk_fma_f16 v5, v1, v2, v3 neg_lo:[1,0,0]
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x3c]
-
-v_pk_fma_f16 v5, v1, v2, v3 neg_lo:[0,1,0]
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x5c]
-
-v_pk_fma_f16 v5, v1, v2, v3 neg_lo:[0,0,1]
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x9c]
-
-v_pk_fma_f16 v5, v1, v2, v3 neg_lo:[1,1,1]
-// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0xfc]
-
-v_pk_fma_f16 v5, v1, v2, v3 neg_hi:[1,0,0]
-// CHECK: [0x05,0x41,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v1, v2, v3 neg_hi:[0,1,0]
-// CHECK: [0x05,0x42,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v1, v2, v3 neg_hi:[0,0,1]
-// CHECK: [0x05,0x44,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v1, v2, v3 neg_hi:[1,1,1]
-// CHECK: [0x05,0x47,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_fma_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0xc0,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_pk_add_f16 v5, v1, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v255, v1, v2
-// CHECK: [0xff,0x00,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, v255, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, s1, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, s101, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, m0, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, 0, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, -1, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0xf0,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x8f,0xd3,0xf7,0x04,0x02,0x18]
-
-v_pk_add_f16 v5, v1, v255
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_add_f16 v5, v1, s2
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_add_f16 v5, v1, s101
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_add_f16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_add_f16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_add_f16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_add_f16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_add_f16 v5, v1, m0
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_add_f16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_add_f16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_add_f16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, v1, 0
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_add_f16 v5, v1, -1
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_add_f16 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xe1,0x01,0x18]
-
-v_pk_add_f16 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xef,0x01,0x18]
-
-v_pk_add_f16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_add_f16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_add_f16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_add_f16 v5, v1, v2 neg_lo:[1,0]
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x38]
-
-v_pk_add_f16 v5, v1, v2 neg_lo:[0,1]
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x58]
-
-v_pk_add_f16 v5, v1, v2 neg_lo:[1,1]
-// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x78]
-
-v_pk_add_f16 v5, v1, v2 neg_hi:[1,0]
-// CHECK: [0x05,0x01,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, v1, v2 neg_hi:[0,1]
-// CHECK: [0x05,0x02,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, v1, v2 neg_hi:[1,1]
-// CHECK: [0x05,0x03,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_add_f16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x8f,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v255, v1, v2
-// CHECK: [0xff,0x00,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v255, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, s1, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, s101, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, m0, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, 0, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, -1, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0xf0,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x90,0xd3,0xf7,0x04,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, v255
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_mul_f16 v5, v1, s2
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_mul_f16 v5, v1, s101
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_mul_f16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_mul_f16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_mul_f16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_mul_f16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_mul_f16 v5, v1, m0
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_mul_f16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_mul_f16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_mul_f16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, 0
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_mul_f16 v5, v1, -1
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_mul_f16 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xe1,0x01,0x18]
-
-v_pk_mul_f16 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xef,0x01,0x18]
-
-v_pk_mul_f16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_mul_f16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_mul_f16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_mul_f16 v5, v1, v2 neg_lo:[1,0]
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x38]
-
-v_pk_mul_f16 v5, v1, v2 neg_lo:[0,1]
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x58]
-
-v_pk_mul_f16 v5, v1, v2 neg_lo:[1,1]
-// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x78]
-
-v_pk_mul_f16 v5, v1, v2 neg_hi:[1,0]
-// CHECK: [0x05,0x01,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, v2 neg_hi:[0,1]
-// CHECK: [0x05,0x02,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, v2 neg_hi:[1,1]
-// CHECK: [0x05,0x03,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_mul_f16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x90,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v1, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v255, v1, v2
-// CHECK: [0xff,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v255, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, s1, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, s101, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, m0, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, 0, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, -1, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0xf0,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x91,0xd3,0xf7,0x04,0x02,0x18]
-
-v_pk_min_f16 v5, v1, v255
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_min_f16 v5, v1, s2
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_min_f16 v5, v1, s101
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_min_f16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_min_f16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_min_f16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_min_f16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_min_f16 v5, v1, m0
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_min_f16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_min_f16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_min_f16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v1, 0
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_min_f16 v5, v1, -1
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_min_f16 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xe1,0x01,0x18]
-
-v_pk_min_f16 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xef,0x01,0x18]
-
-v_pk_min_f16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_min_f16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_min_f16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_min_f16 v5, v1, v2 neg_lo:[1,0]
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x38]
-
-v_pk_min_f16 v5, v1, v2 neg_lo:[0,1]
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x58]
-
-v_pk_min_f16 v5, v1, v2 neg_lo:[1,1]
-// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x78]
-
-v_pk_min_f16 v5, v1, v2 neg_hi:[1,0]
-// CHECK: [0x05,0x01,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v1, v2 neg_hi:[0,1]
-// CHECK: [0x05,0x02,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v1, v2 neg_hi:[1,1]
-// CHECK: [0x05,0x03,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_min_f16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x91,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v1, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v255, v1, v2
-// CHECK: [0xff,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v255, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0xff,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, s1, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, s101, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x65,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, flat_scratch_lo, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x66,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, flat_scratch_hi, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x67,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, vcc_lo, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x6a,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, vcc_hi, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x6b,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, m0, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x7c,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, exec_lo, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x7e,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, exec_hi, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x7f,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, 0, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0x80,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, -1, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0xc1,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, 0.5, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0xf0,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, -4.0, v2
-// CHECK: [0x05,0x00,0x92,0xd3,0xf7,0x04,0x02,0x18]
-
-v_pk_max_f16 v5, v1, v255
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xff,0x03,0x18]
-
-v_pk_max_f16 v5, v1, s2
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x00,0x18]
-
-v_pk_max_f16 v5, v1, s101
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xcb,0x00,0x18]
-
-v_pk_max_f16 v5, v1, flat_scratch_lo
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xcd,0x00,0x18]
-
-v_pk_max_f16 v5, v1, flat_scratch_hi
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xcf,0x00,0x18]
-
-v_pk_max_f16 v5, v1, vcc_lo
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xd5,0x00,0x18]
-
-v_pk_max_f16 v5, v1, vcc_hi
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xd7,0x00,0x18]
-
-v_pk_max_f16 v5, v1, m0
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xf9,0x00,0x18]
-
-v_pk_max_f16 v5, v1, exec_lo
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xfd,0x00,0x18]
-
-v_pk_max_f16 v5, v1, exec_hi
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xff,0x00,0x18]
-
-v_pk_max_f16 v5, v1, v2 op_sel:[0,0]
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v1, 0
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x01,0x01,0x18]
-
-v_pk_max_f16 v5, v1, -1
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x83,0x01,0x18]
-
-v_pk_max_f16 v5, v1, 0.5
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xe1,0x01,0x18]
-
-v_pk_max_f16 v5, v1, -4.0
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xef,0x01,0x18]
-
-v_pk_max_f16 v5, v1, v2 op_sel:[1,0]
-// CHECK: [0x05,0x08,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v1, v2 op_sel:[0,1]
-// CHECK: [0x05,0x10,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v1, v2 op_sel:[1,1]
-// CHECK: [0x05,0x18,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v1, v2 op_sel_hi:[1,1]
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v1, v2 op_sel_hi:[0,0]
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x00]
-
-v_pk_max_f16 v5, v1, v2 op_sel_hi:[1,0]
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x08]
-
-v_pk_max_f16 v5, v1, v2 op_sel_hi:[0,1]
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x10]
-
-v_pk_max_f16 v5, v1, v2 neg_lo:[1,0]
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x38]
-
-v_pk_max_f16 v5, v1, v2 neg_lo:[0,1]
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x58]
-
-v_pk_max_f16 v5, v1, v2 neg_lo:[1,1]
-// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x78]
-
-v_pk_max_f16 v5, v1, v2 neg_hi:[1,0]
-// CHECK: [0x05,0x01,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v1, v2 neg_hi:[0,1]
-// CHECK: [0x05,0x02,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v1, v2 neg_hi:[1,1]
-// CHECK: [0x05,0x03,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_pk_max_f16 v5, v1, v2 clamp
-// CHECK: [0x05,0x80,0x92,0xd3,0x01,0x05,0x02,0x18]
-
-v_mad_mix_f32 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x65,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x66,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x6b,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x7c,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x80,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0xc1,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0xf0,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0xf7,0x04,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04]
-
-v_mad_mix_f32 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0c,0x04]
-
-v_mad_mix_f32 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xcb,0x0c,0x04]
-
-v_mad_mix_f32 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xcd,0x0c,0x04]
-
-v_mad_mix_f32 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xcf,0x0c,0x04]
-
-v_mad_mix_f32 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xd5,0x0c,0x04]
-
-v_mad_mix_f32 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xd7,0x0c,0x04]
-
-v_mad_mix_f32 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0c,0x04]
-
-v_mad_mix_f32 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04]
-
-v_mad_mix_f32 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04]
-
-v_mad_mix_f32 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x01,0x0d,0x04]
-
-v_mad_mix_f32 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x83,0x0d,0x04]
-
-v_mad_mix_f32 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xe1,0x0d,0x04]
-
-v_mad_mix_f32 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xef,0x0d,0x04]
-
-v_mad_mix_f32 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07]
-
-v_mad_mix_f32 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x00]
-
-v_mad_mix_f32 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x96,0x01]
-
-v_mad_mix_f32 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9a,0x01]
-
-v_mad_mix_f32 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9e,0x01]
-
-v_mad_mix_f32 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xaa,0x01]
-
-v_mad_mix_f32 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xae,0x01]
-
-v_mad_mix_f32 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x01]
-
-v_mad_mix_f32 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01]
-
-v_mad_mix_f32 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01]
-
-v_mad_mix_f32 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x02,0x02]
-
-v_mad_mix_f32 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x06,0x03]
-
-v_mad_mix_f32 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xc2,0x03]
-
-v_mad_mix_f32 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xde,0x03]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,0]
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,0,0]
-// CHECK: [0x05,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,1,0]
-// CHECK: [0x05,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,1]
-// CHECK: [0x05,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,1,1]
-// CHECK: [0x05,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,0]
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,0,0]
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,1,0]
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,1]
-// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,1,1]
-// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_mad_mix_f32 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
-
-v_mad_mix_f32 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
-
-v_mad_mix_f32 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
-
-v_mad_mix_f32 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0xe4]
-
-v_mad_mix_f32 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mix_f32 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xa0,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0xff,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x65,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x66,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x67,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x6a,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x6b,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x7c,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x7e,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x7f,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x80,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0xc1,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0xf0,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0xf7,0x04,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0f,0x04]
-
-v_mad_mixlo_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0c,0x04]
-
-v_mad_mixlo_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xcb,0x0c,0x04]
-
-v_mad_mixlo_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xcd,0x0c,0x04]
-
-v_mad_mixlo_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xcf,0x0c,0x04]
-
-v_mad_mixlo_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xd5,0x0c,0x04]
-
-v_mad_mixlo_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xd7,0x0c,0x04]
-
-v_mad_mixlo_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xf9,0x0c,0x04]
-
-v_mad_mixlo_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xfd,0x0c,0x04]
-
-v_mad_mixlo_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0c,0x04]
-
-v_mad_mixlo_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x01,0x0d,0x04]
-
-v_mad_mixlo_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x83,0x0d,0x04]
-
-v_mad_mixlo_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xe1,0x0d,0x04]
-
-v_mad_mixlo_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xef,0x0d,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x07]
-
-v_mad_mixlo_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x00]
-
-v_mad_mixlo_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x96,0x01]
-
-v_mad_mixlo_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9a,0x01]
-
-v_mad_mixlo_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9e,0x01]
-
-v_mad_mixlo_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xaa,0x01]
-
-v_mad_mixlo_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xae,0x01]
-
-v_mad_mixlo_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xf2,0x01]
-
-v_mad_mixlo_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfa,0x01]
-
-v_mad_mixlo_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x01]
-
-v_mad_mixlo_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x02,0x02]
-
-v_mad_mixlo_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x06,0x03]
-
-v_mad_mixlo_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xc2,0x03]
-
-v_mad_mixlo_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xde,0x03]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,0,0]
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,0,0]
-// CHECK: [0x05,0x08,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,1,0]
-// CHECK: [0x05,0x10,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,0,1]
-// CHECK: [0x05,0x20,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,1,1]
-// CHECK: [0x05,0x38,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x0c]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x14]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
-// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1]
-// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_mad_mixlo_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x24]
-
-v_mad_mixlo_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x44]
-
-v_mad_mixlo_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x84]
-
-v_mad_mixlo_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0xe4]
-
-v_mad_mixlo_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixlo_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v255, v1, v2, v3
-// CHECK: [0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v255, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, s1, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, s101, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, flat_scratch_lo, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x66,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, flat_scratch_hi, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x67,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, vcc_lo, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, vcc_hi, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, m0, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, exec_lo, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x7e,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, exec_hi, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x7f,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, 0, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x80,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, -1, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0xc1,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, 0.5, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0xf0,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, -4.0, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0xf7,0x04,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v255, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0f,0x04]
-
-v_mad_mixhi_f16 v5, v1, s2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0c,0x04]
-
-v_mad_mixhi_f16 v5, v1, s101, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xcb,0x0c,0x04]
-
-v_mad_mixhi_f16 v5, v1, flat_scratch_lo, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xcd,0x0c,0x04]
-
-v_mad_mixhi_f16 v5, v1, flat_scratch_hi, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xcf,0x0c,0x04]
-
-v_mad_mixhi_f16 v5, v1, vcc_lo, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xd5,0x0c,0x04]
-
-v_mad_mixhi_f16 v5, v1, vcc_hi, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xd7,0x0c,0x04]
-
-v_mad_mixhi_f16 v5, v1, m0, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xf9,0x0c,0x04]
-
-v_mad_mixhi_f16 v5, v1, exec_lo, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xfd,0x0c,0x04]
-
-v_mad_mixhi_f16 v5, v1, exec_hi, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0c,0x04]
-
-v_mad_mixhi_f16 v5, v1, 0, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x01,0x0d,0x04]
-
-v_mad_mixhi_f16 v5, v1, -1, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x83,0x0d,0x04]
-
-v_mad_mixhi_f16 v5, v1, 0.5, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xe1,0x0d,0x04]
-
-v_mad_mixhi_f16 v5, v1, -4.0, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xef,0x0d,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v255
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x07]
-
-v_mad_mixhi_f16 v5, v1, v2, s3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x00]
-
-v_mad_mixhi_f16 v5, v1, v2, s101
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x96,0x01]
-
-v_mad_mixhi_f16 v5, v1, v2, flat_scratch_lo
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9a,0x01]
-
-v_mad_mixhi_f16 v5, v1, v2, flat_scratch_hi
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9e,0x01]
-
-v_mad_mixhi_f16 v5, v1, v2, vcc_lo
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xaa,0x01]
-
-v_mad_mixhi_f16 v5, v1, v2, vcc_hi
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xae,0x01]
-
-v_mad_mixhi_f16 v5, v1, v2, m0
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xf2,0x01]
-
-v_mad_mixhi_f16 v5, v1, v2, exec_lo
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfa,0x01]
-
-v_mad_mixhi_f16 v5, v1, v2, exec_hi
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x01]
-
-v_mad_mixhi_f16 v5, v1, v2, 0
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x02,0x02]
-
-v_mad_mixhi_f16 v5, v1, v2, -1
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x06,0x03]
-
-v_mad_mixhi_f16 v5, v1, v2, 0.5
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xc2,0x03]
-
-v_mad_mixhi_f16 v5, v1, v2, -4.0
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xde,0x03]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,0,0]
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,0,0]
-// CHECK: [0x05,0x08,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,1,0]
-// CHECK: [0x05,0x10,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,0,1]
-// CHECK: [0x05,0x20,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,1,1]
-// CHECK: [0x05,0x38,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x0c]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x14]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
-// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1]
-// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
-
-v_mad_mixhi_f16 v5, -v1, v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x24]
-
-v_mad_mixhi_f16 v5, v1, -v2, v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x44]
-
-v_mad_mixhi_f16 v5, v1, v2, -v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x84]
-
-v_mad_mixhi_f16 v5, -v1, -v2, -v3
-// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0xe4]
-
-v_mad_mixhi_f16 v5, |v1|, v2, v3
-// CHECK: [0x05,0x01,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, |v2|, v3
-// CHECK: [0x05,0x02,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, |v3|
-// CHECK: [0x05,0x04,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, |v1|, |v2|, |v3|
-// CHECK: [0x05,0x07,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_mad_mixhi_f16 v5, v1, v2, v3 clamp
-// CHECK: [0x05,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
-
-v_cmp_class_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x20,0x7c]
-
-v_cmp_class_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x20,0x7c]
-
-v_cmp_class_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x20,0x7c]
-
-v_cmp_class_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x20,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_class_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x20,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_class_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x21,0x7c]
-
-v_cmp_class_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_class_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x22,0x7c]
-
-v_cmpx_class_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x22,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_class_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x22,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_class_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x23,0x7c]
-
-v_cmpx_class_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_class_f64 vcc, v[1:2], v2
-// CHECK: [0x01,0x05,0x24,0x7c]
-
-v_cmp_class_f64 vcc, v[254:255], v2
-// CHECK: [0xfe,0x05,0x24,0x7c]
-
-v_cmp_class_f64 vcc, s[2:3], v2
-// CHECK: [0x02,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, s[4:5], v2
-// CHECK: [0x04,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, s[100:101], v2
-// CHECK: [0x64,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, flat_scratch, v2
-// CHECK: [0x66,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, vcc, v2
-// CHECK: [0x6a,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, exec, v2
-// CHECK: [0x7e,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, 0, v2
-// CHECK: [0x80,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x24,0x7c]
-
-v_cmp_class_f64 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x24,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_class_f64 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x24,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_class_f64 vcc, v[1:2], v255
-// CHECK: [0x01,0xff,0x25,0x7c]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[12:13], v[1:2], v2
-// CHECK: [0x0c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[100:101], v[1:2], v2
-// CHECK: [0x64,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 flat_scratch, v[1:2], v2
-// CHECK: [0x66,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 vcc, v[1:2], v2
-// CHECK: [0x6a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[254:255], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], s[2:3], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], s[4:5], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], s[100:101], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], flat_scratch, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], vcc, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], exec, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], v255
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], s2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], s101
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], m0
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], exec_lo
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], exec_hi
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f64_e64 s[10:11], -v[1:2], v2
-// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_class_f64 vcc, v[1:2], v2
-// CHECK: [0x01,0x05,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, v[254:255], v2
-// CHECK: [0xfe,0x05,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, s[2:3], v2
-// CHECK: [0x02,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, s[4:5], v2
-// CHECK: [0x04,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, s[100:101], v2
-// CHECK: [0x64,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, flat_scratch, v2
-// CHECK: [0x66,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, vcc, v2
-// CHECK: [0x6a,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, exec, v2
-// CHECK: [0x7e,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, 0, v2
-// CHECK: [0x80,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x26,0x7c]
-
-v_cmpx_class_f64 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x26,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_class_f64 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x26,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_class_f64 vcc, v[1:2], v255
-// CHECK: [0x01,0xff,0x27,0x7c]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[12:13], v[1:2], v2
-// CHECK: [0x0c,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[100:101], v[1:2], v2
-// CHECK: [0x64,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 flat_scratch, v[1:2], v2
-// CHECK: [0x66,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 vcc, v[1:2], v2
-// CHECK: [0x6a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 exec, v[1:2], v2
-// CHECK: [0x7e,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[254:255], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], s[2:3], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], s[4:5], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], s[100:101], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], flat_scratch, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], vcc, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], exec, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], v255
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], s2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], s101
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_lo
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_hi
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], m0
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_lo
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_hi
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f64_e64 s[10:11], -v[1:2], v2
-// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_class_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x28,0x7c]
-
-v_cmp_class_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x28,0x7c]
-
-v_cmp_class_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x28,0x7c]
-
-v_cmp_class_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x28,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_class_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x28,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_class_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x29,0x7c]
-
-v_cmp_class_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_class_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_class_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_class_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x2a,0x7c]
-
-v_cmpx_class_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x2a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_class_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x2a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_class_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x2b,0x7c]
-
-v_cmpx_class_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_class_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x40,0x7c]
-
-v_cmp_f_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x40,0x7c]
-
-v_cmp_f_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x40,0x7c]
-
-v_cmp_f_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x40,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_f_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x40,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_f_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x41,0x7c]
-
-v_cmp_f_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_f_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_f_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x20,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x42,0x7c]
-
-v_cmp_lt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x42,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_lt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x42,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_lt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x43,0x7c]
-
-v_cmp_lt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x21,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x44,0x7c]
-
-v_cmp_eq_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x44,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_eq_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x44,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_eq_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x45,0x7c]
-
-v_cmp_eq_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_eq_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_eq_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_eq_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x22,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x46,0x7c]
-
-v_cmp_le_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x46,0x7c]
-
-v_cmp_le_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x46,0x7c]
-
-v_cmp_le_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x46,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_le_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x46,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_le_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x47,0x7c]
-
-v_cmp_le_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_le_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_le_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_le_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x23,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x48,0x7c]
-
-v_cmp_gt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x48,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_gt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x48,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_gt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x49,0x7c]
-
-v_cmp_gt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_gt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_gt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_gt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x24,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x4a,0x7c]
-
-v_cmp_lg_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_lg_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_lg_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4b,0x7c]
-
-v_cmp_lg_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lg_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lg_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lg_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lg_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x25,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x4c,0x7c]
-
-v_cmp_ge_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4c,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ge_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_ge_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4d,0x7c]
-
-v_cmp_ge_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ge_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ge_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ge_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x26,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x4e,0x7c]
-
-v_cmp_o_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4e,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_o_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_o_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4f,0x7c]
-
-v_cmp_o_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_o_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_o_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_o_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_o_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_o_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x27,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x50,0x7c]
-
-v_cmp_u_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x50,0x7c]
-
-v_cmp_u_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x50,0x7c]
-
-v_cmp_u_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x50,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_u_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x50,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_u_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x51,0x7c]
-
-v_cmp_u_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_u_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_u_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_u_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_u_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_u_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x28,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x52,0x7c]
-
-v_cmp_nge_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x52,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_nge_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x52,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_nge_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x53,0x7c]
-
-v_cmp_nge_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nge_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nge_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nge_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nge_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x29,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x54,0x7c]
-
-v_cmp_nlg_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x54,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_nlg_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x54,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_nlg_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x55,0x7c]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlg_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlg_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlg_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x56,0x7c]
-
-v_cmp_ngt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x56,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ngt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x56,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_ngt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x57,0x7c]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ngt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ngt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ngt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x58,0x7c]
-
-v_cmp_nle_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x58,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_nle_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x58,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_nle_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x59,0x7c]
-
-v_cmp_nle_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nle_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nle_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nle_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nle_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x5a,0x7c]
-
-v_cmp_neq_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_neq_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_neq_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5b,0x7c]
-
-v_cmp_neq_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_neq_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_neq_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_neq_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_neq_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x5c,0x7c]
-
-v_cmp_nlt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5c,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_nlt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_nlt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5d,0x7c]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x5e,0x7c]
-
-v_cmp_tru_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5e,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmp_tru_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmp_tru_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5f,0x7c]
-
-v_cmp_tru_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_tru_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_tru_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_tru_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_tru_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x2f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x60,0x7c]
-
-v_cmpx_f_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x60,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_f_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x60,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_f_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x61,0x7c]
-
-v_cmpx_f_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x30,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x62,0x7c]
-
-v_cmpx_lt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x62,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x62,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_lt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x63,0x7c]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x31,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x64,0x7c]
-
-v_cmpx_eq_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x64,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_eq_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x64,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_eq_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x65,0x7c]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x32,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x66,0x7c]
-
-v_cmpx_le_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x66,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_le_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x66,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_le_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x67,0x7c]
-
-v_cmpx_le_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x33,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x68,0x7c]
-
-v_cmpx_gt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x68,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_gt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x68,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_gt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x69,0x7c]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x34,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x6a,0x7c]
-
-v_cmpx_lg_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lg_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_lg_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6b,0x7c]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x35,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x6c,0x7c]
-
-v_cmpx_ge_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6c,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ge_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6c,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_ge_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6d,0x7c]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x36,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x6e,0x7c]
-
-v_cmpx_o_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6e,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_o_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6e,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_o_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6f,0x7c]
-
-v_cmpx_o_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x37,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x70,0x7c]
-
-v_cmpx_u_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x70,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_u_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x70,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_u_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x71,0x7c]
-
-v_cmpx_u_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x38,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x72,0x7c]
-
-v_cmpx_nge_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x72,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nge_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x72,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_nge_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x73,0x7c]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x39,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x74,0x7c]
-
-v_cmpx_nlg_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x74,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nlg_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x74,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_nlg_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x75,0x7c]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x76,0x7c]
-
-v_cmpx_ngt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x76,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ngt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x76,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_ngt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x77,0x7c]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x78,0x7c]
-
-v_cmpx_nle_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x78,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nle_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x78,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_nle_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x79,0x7c]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x7a,0x7c]
-
-v_cmpx_neq_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7a,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_neq_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7a,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_neq_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7b,0x7c]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x7c,0x7c]
-
-v_cmpx_nlt_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7c,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_nlt_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7c,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_nlt_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7d,0x7c]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x7e,0x7c]
-
-v_cmpx_tru_f16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7e,0x7c,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_tru_f16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7e,0x7c,0x56,0x34,0x00,0x00]
-
-v_cmpx_tru_f16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7f,0x7c]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f16_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f16_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f16_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x3f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x80,0x7c]
-
-v_cmp_f_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x80,0x7c]
-
-v_cmp_f_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x80,0x7c]
-
-v_cmp_f_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x80,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x80,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x81,0x7c]
-
-v_cmp_f_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_f_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_f_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x40,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x82,0x7c]
-
-v_cmp_lt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x82,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x82,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x83,0x7c]
-
-v_cmp_lt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x41,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x84,0x7c]
-
-v_cmp_eq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x84,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x84,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x85,0x7c]
-
-v_cmp_eq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_eq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_eq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_eq_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x42,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x86,0x7c]
-
-v_cmp_le_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x86,0x7c]
-
-v_cmp_le_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x86,0x7c]
-
-v_cmp_le_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x86,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x86,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x87,0x7c]
-
-v_cmp_le_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_le_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_le_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_le_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x43,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x88,0x7c]
-
-v_cmp_gt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x88,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x88,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x89,0x7c]
-
-v_cmp_gt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_gt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_gt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_gt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x44,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8a,0x7c]
-
-v_cmp_lg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8b,0x7c]
-
-v_cmp_lg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lg_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x45,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8c,0x7c]
-
-v_cmp_ge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8d,0x7c]
-
-v_cmp_ge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ge_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x46,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8e,0x7c]
-
-v_cmp_o_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_o_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_o_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8f,0x7c]
-
-v_cmp_o_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_o_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_o_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_o_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_o_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x47,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x90,0x7c]
-
-v_cmp_u_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x90,0x7c]
-
-v_cmp_u_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x90,0x7c]
-
-v_cmp_u_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x90,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_u_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x90,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_u_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x91,0x7c]
-
-v_cmp_u_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_u_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_u_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_u_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_u_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x48,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x92,0x7c]
-
-v_cmp_nge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x92,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x92,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x93,0x7c]
-
-v_cmp_nge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nge_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x49,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x94,0x7c]
-
-v_cmp_nlg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x94,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x94,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x95,0x7c]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlg_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x96,0x7c]
-
-v_cmp_ngt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x96,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ngt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x96,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ngt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x97,0x7c]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ngt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ngt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ngt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x98,0x7c]
-
-v_cmp_nle_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x98,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nle_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x98,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nle_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x99,0x7c]
-
-v_cmp_nle_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nle_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nle_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nle_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nle_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9a,0x7c]
-
-v_cmp_neq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9a,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_neq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9a,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_neq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9b,0x7c]
-
-v_cmp_neq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_neq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_neq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_neq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_neq_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9c,0x7c]
-
-v_cmp_nlt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9c,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9c,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9d,0x7c]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9e,0x7c]
-
-v_cmp_tru_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9e,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_tru_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9e,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_tru_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9f,0x7c]
-
-v_cmp_tru_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_tru_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_tru_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_tru_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_tru_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x4f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa0,0x7c]
-
-v_cmpx_f_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa1,0x7c]
-
-v_cmpx_f_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x50,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa2,0x7c]
-
-v_cmpx_lt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa3,0x7c]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x51,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa4,0x7c]
-
-v_cmpx_eq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa5,0x7c]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x52,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa6,0x7c]
-
-v_cmpx_le_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa7,0x7c]
-
-v_cmpx_le_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x53,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa8,0x7c]
-
-v_cmpx_gt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa9,0x7c]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x54,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xaa,0x7c]
-
-v_cmpx_lg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xaa,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xaa,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xab,0x7c]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x55,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xac,0x7c]
-
-v_cmpx_ge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xac,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xac,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xad,0x7c]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x56,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xae,0x7c]
-
-v_cmpx_o_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xae,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_o_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xae,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_o_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xaf,0x7c]
-
-v_cmpx_o_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x57,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb0,0x7c]
-
-v_cmpx_u_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_u_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_u_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb1,0x7c]
-
-v_cmpx_u_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x58,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb2,0x7c]
-
-v_cmpx_nge_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nge_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nge_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb3,0x7c]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x59,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb4,0x7c]
-
-v_cmpx_nlg_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlg_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlg_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb5,0x7c]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb6,0x7c]
-
-v_cmpx_ngt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ngt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ngt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb7,0x7c]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb8,0x7c]
-
-v_cmpx_nle_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nle_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nle_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb9,0x7c]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xba,0x7c]
-
-v_cmpx_neq_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xba,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_neq_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xba,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_neq_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbb,0x7c]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbc,0x7c]
-
-v_cmpx_nlt_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlt_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlt_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbd,0x7c]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbe,0x7c]
-
-v_cmpx_tru_f32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbe,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_tru_f32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbe,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_tru_f32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbf,0x7c]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f32_e64 s[10:11], -v1, v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, -v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f32_e64 s[10:11], -v1, -v2
-// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f32_e64 s[10:11], v1, v2 clamp
-// CHECK: [0x0a,0x80,0x5f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc0,0x7c]
-
-v_cmp_f_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc1,0x7c]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x60,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc2,0x7c]
-
-v_cmp_lt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc3,0x7c]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x61,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc4,0x7c]
-
-v_cmp_eq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc5,0x7c]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x62,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc6,0x7c]
-
-v_cmp_le_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc7,0x7c]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x63,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc8,0x7c]
-
-v_cmp_gt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc9,0x7c]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x64,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xca,0x7c]
-
-v_cmp_lg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_lg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_lg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcb,0x7c]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x65,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xcc,0x7c]
-
-v_cmp_ge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcd,0x7c]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x66,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xce,0x7c]
-
-v_cmp_o_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xce,0x7c]
-
-v_cmp_o_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xce,0x7c]
-
-v_cmp_o_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_o_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_o_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcf,0x7c]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_o_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x67,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd0,0x7c]
-
-v_cmp_u_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_u_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_u_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd1,0x7c]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_u_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x68,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd2,0x7c]
-
-v_cmp_nge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd3,0x7c]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x69,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd4,0x7c]
-
-v_cmp_nlg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd5,0x7c]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd6,0x7c]
-
-v_cmp_ngt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_ngt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_ngt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd7,0x7c]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd8,0x7c]
-
-v_cmp_nle_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nle_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nle_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd9,0x7c]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xda,0x7c]
-
-v_cmp_neq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_neq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_neq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdb,0x7c]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xdc,0x7c]
-
-v_cmp_nlt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_nlt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_nlt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdd,0x7c]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xde,0x7c]
-
-v_cmp_tru_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmp_tru_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmp_tru_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdf,0x7c]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmp_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x6f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe0,0x7c]
-
-v_cmpx_f_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe1,0x7c]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x70,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe2,0x7c]
-
-v_cmpx_lt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe3,0x7c]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x71,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe4,0x7c]
-
-v_cmpx_eq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe5,0x7c]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x72,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe6,0x7c]
-
-v_cmpx_le_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe7,0x7c]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x73,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe8,0x7c]
-
-v_cmpx_gt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe9,0x7c]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x74,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xea,0x7c]
-
-v_cmpx_lg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xeb,0x7c]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x75,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xec,0x7c]
-
-v_cmpx_ge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xed,0x7c]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x76,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xee,0x7c]
-
-v_cmpx_o_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_o_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_o_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xef,0x7c]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_o_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x77,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf0,0x7c]
-
-v_cmpx_u_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_u_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_u_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf1,0x7c]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_u_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x78,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf2,0x7c]
-
-v_cmpx_nge_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nge_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nge_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf3,0x7c]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x79,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf4,0x7c]
-
-v_cmpx_nlg_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlg_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlg_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf5,0x7c]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7a,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf6,0x7c]
-
-v_cmpx_ngt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ngt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ngt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf7,0x7c]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7b,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf8,0x7c]
-
-v_cmpx_nle_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nle_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nle_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf9,0x7c]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7c,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfa,0x7c]
-
-v_cmpx_neq_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_neq_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_neq_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfb,0x7c]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7d,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfc,0x7c]
-
-v_cmpx_nlt_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_nlt_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_nlt_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfd,0x7c]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7e,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfe,0x7c]
-
-v_cmpx_tru_f64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7c,0x56,0x34,0x12,0xaf]
-
-v_cmpx_tru_f64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7c,0x73,0x72,0x71,0x3f]
-
-v_cmpx_tru_f64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xff,0x7c]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x20]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x40]
-
-v_cmpx_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
-// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x60]
-
-v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
-// CHECK: [0x0a,0x80,0x7f,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x40,0x7d]
-
-v_cmp_f_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x40,0x7d]
-
-v_cmp_f_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x40,0x7d]
-
-v_cmp_f_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x40,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_f_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x40,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_f_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x40,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_f_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x40,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_f_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x41,0x7d]
-
-v_cmp_f_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x42,0x7d]
-
-v_cmp_lt_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x42,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_lt_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x42,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_lt_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x42,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_lt_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x42,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_lt_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x43,0x7d]
-
-v_cmp_lt_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x44,0x7d]
-
-v_cmp_eq_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x44,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_eq_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x44,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_eq_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x44,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_eq_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x44,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_eq_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x45,0x7d]
-
-v_cmp_eq_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x46,0x7d]
-
-v_cmp_le_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x46,0x7d]
-
-v_cmp_le_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x46,0x7d]
-
-v_cmp_le_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x46,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_le_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x46,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_le_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x46,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_le_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x46,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_le_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x47,0x7d]
-
-v_cmp_le_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x48,0x7d]
-
-v_cmp_gt_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x48,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_gt_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x48,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_gt_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x48,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_gt_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x48,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_gt_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x49,0x7d]
-
-v_cmp_gt_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4a,0x7d]
-
-v_cmp_ne_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x4a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_ne_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x4a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_ne_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ne_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_ne_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4b,0x7d]
-
-v_cmp_ne_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4c,0x7d]
-
-v_cmp_ge_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x4c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_ge_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x4c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_ge_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ge_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_ge_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4d,0x7d]
-
-v_cmp_ge_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x4e,0x7d]
-
-v_cmp_t_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x4e,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_t_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x4e,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_t_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x4e,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_t_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_t_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x4f,0x7d]
-
-v_cmp_t_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x50,0x7d]
-
-v_cmp_f_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x50,0x7d]
-
-v_cmp_f_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x50,0x7d]
-
-v_cmp_f_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x50,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_f_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x50,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_f_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x50,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_f_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x50,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_f_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x51,0x7d]
-
-v_cmp_f_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x52,0x7d]
-
-v_cmp_lt_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x52,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_lt_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x52,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_lt_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x52,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_lt_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x52,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_lt_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x53,0x7d]
-
-v_cmp_lt_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_lt_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x54,0x7d]
-
-v_cmp_eq_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x54,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_eq_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x54,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_eq_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x54,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_eq_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x54,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_eq_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x55,0x7d]
-
-v_cmp_eq_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_eq_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x56,0x7d]
-
-v_cmp_le_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x56,0x7d]
-
-v_cmp_le_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x56,0x7d]
-
-v_cmp_le_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x56,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_le_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x56,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_le_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x56,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_le_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x56,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_le_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x57,0x7d]
-
-v_cmp_le_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xab,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_le_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x58,0x7d]
-
-v_cmp_gt_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x58,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_gt_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x58,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_gt_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x58,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_gt_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x58,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_gt_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x59,0x7d]
-
-v_cmp_gt_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xac,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_gt_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5a,0x7d]
-
-v_cmp_ne_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x5a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_ne_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x5a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_ne_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ne_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_ne_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5b,0x7d]
-
-v_cmp_ne_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xad,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ne_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5c,0x7d]
-
-v_cmp_ge_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x5c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_ge_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x5c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_ge_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_ge_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_ge_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5d,0x7d]
-
-v_cmp_ge_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xae,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_ge_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x5e,0x7d]
-
-v_cmp_t_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x5e,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmp_t_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x5e,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmp_t_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x5e,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmp_t_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x5e,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmp_t_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x5f,0x7d]
-
-v_cmp_t_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_t_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x60,0x7d]
-
-v_cmpx_f_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x60,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_f_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x60,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_f_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x60,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_f_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x60,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_f_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x61,0x7d]
-
-v_cmpx_f_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x62,0x7d]
-
-v_cmpx_lt_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x62,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x62,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_lt_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x62,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lt_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x62,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_lt_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x63,0x7d]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x64,0x7d]
-
-v_cmpx_eq_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x64,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x64,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x64,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_eq_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x64,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_eq_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x65,0x7d]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x66,0x7d]
-
-v_cmpx_le_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x66,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x66,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x66,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_le_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x66,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_le_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x67,0x7d]
-
-v_cmpx_le_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x68,0x7d]
-
-v_cmpx_gt_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x68,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x68,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x68,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_gt_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x68,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_gt_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x69,0x7d]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6a,0x7d]
-
-v_cmpx_ne_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x6a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x6a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ne_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ne_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6b,0x7d]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6c,0x7d]
-
-v_cmpx_ge_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x6c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x6c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ge_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ge_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6d,0x7d]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_i16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x6e,0x7d]
-
-v_cmpx_t_i16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x6e,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_t_i16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x6e,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_t_i16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x6e,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_t_i16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x6e,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_t_i16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x6f,0x7d]
-
-v_cmpx_t_i16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_i16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_i16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_i16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x70,0x7d]
-
-v_cmpx_f_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x70,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_f_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x70,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_f_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x70,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_f_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x70,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_f_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x71,0x7d]
-
-v_cmpx_f_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_f_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x72,0x7d]
-
-v_cmpx_lt_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x72,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_lt_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x72,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_lt_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x72,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_lt_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x72,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_lt_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x73,0x7d]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_lt_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x74,0x7d]
-
-v_cmpx_eq_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x74,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_eq_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x74,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_eq_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x74,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_eq_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x74,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_eq_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x75,0x7d]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xba,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_eq_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x76,0x7d]
-
-v_cmpx_le_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x76,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_le_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x76,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_le_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x76,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_le_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x76,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_le_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x77,0x7d]
-
-v_cmpx_le_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_le_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x78,0x7d]
-
-v_cmpx_gt_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x78,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_gt_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x78,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_gt_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x78,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_gt_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x78,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_gt_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x79,0x7d]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_gt_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7a,0x7d]
-
-v_cmpx_ne_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x7a,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ne_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x7a,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ne_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7a,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ne_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7a,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ne_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7b,0x7d]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ne_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7c,0x7d]
-
-v_cmpx_ge_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x7c,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_ge_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x7c,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_ge_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7c,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_ge_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7c,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_ge_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7d,0x7d]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_ge_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_u16 vcc, v1, v2
-// CHECK: [0x01,0x05,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, v255, v2
-// CHECK: [0xff,0x05,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, s1, v2
-// CHECK: [0x01,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, s101, v2
-// CHECK: [0x65,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, 0, v2
-// CHECK: [0x80,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x7e,0x7d]
-
-v_cmpx_t_u16 vcc, 0.5, v2
-// CHECK: encoding: [0xff,0x04,0x7e,0x7d,0x00,0x38,0x00,0x00]
-
-v_cmpx_t_u16 vcc, -4.0, v2
-// CHECK: encoding: [0xff,0x04,0x7e,0x7d,0x00,0xc4,0x00,0x00]
-
-v_cmpx_t_u16 vcc, 0xfe0b, v2
-// CHECK: [0xff,0x04,0x7e,0x7d,0x0b,0xfe,0x00,0x00]
-
-v_cmpx_t_u16 vcc, 0x3456, v2
-// CHECK: [0xff,0x04,0x7e,0x7d,0x56,0x34,0x00,0x00]
-
-v_cmpx_t_u16 vcc, v1, v255
-// CHECK: [0x01,0xff,0x7f,0x7d]
-
-v_cmpx_t_u16_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], 0.5, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_u16_e64 s[10:11], -4.0, v2
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_u16_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u16_e64 s[10:11], v1, 0.5
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmpx_t_u16_e64 s[10:11], v1, -4.0
-// CHECK-ERR: error: literal operands are not supported
-
-v_cmp_f_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x80,0x7d]
-
-v_cmp_f_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x80,0x7d]
-
-v_cmp_f_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x80,0x7d]
-
-v_cmp_f_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x81,0x7d]
-
-v_cmp_f_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x82,0x7d]
-
-v_cmp_lt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x83,0x7d]
-
-v_cmp_lt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x84,0x7d]
-
-v_cmp_eq_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x85,0x7d]
-
-v_cmp_eq_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x86,0x7d]
-
-v_cmp_le_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x86,0x7d]
-
-v_cmp_le_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x86,0x7d]
-
-v_cmp_le_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x87,0x7d]
-
-v_cmp_le_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x88,0x7d]
-
-v_cmp_gt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x89,0x7d]
-
-v_cmp_gt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8a,0x7d]
-
-v_cmp_ne_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8b,0x7d]
-
-v_cmp_ne_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8c,0x7d]
-
-v_cmp_ge_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8d,0x7d]
-
-v_cmp_ge_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_t_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x8e,0x7d]
-
-v_cmp_t_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x8f,0x7d]
-
-v_cmp_t_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x90,0x7d]
-
-v_cmp_f_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x90,0x7d]
-
-v_cmp_f_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x90,0x7d]
-
-v_cmp_f_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x90,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x90,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x91,0x7d]
-
-v_cmp_f_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x92,0x7d]
-
-v_cmp_lt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x92,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x92,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x93,0x7d]
-
-v_cmp_lt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x94,0x7d]
-
-v_cmp_eq_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x94,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x94,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x95,0x7d]
-
-v_cmp_eq_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xca,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x96,0x7d]
-
-v_cmp_le_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x96,0x7d]
-
-v_cmp_le_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x96,0x7d]
-
-v_cmp_le_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x96,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x96,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x97,0x7d]
-
-v_cmp_le_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x98,0x7d]
-
-v_cmp_gt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x98,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x98,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x99,0x7d]
-
-v_cmp_gt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9a,0x7d]
-
-v_cmp_ne_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9a,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9a,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9b,0x7d]
-
-v_cmp_ne_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9c,0x7d]
-
-v_cmp_ge_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9c,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9c,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9d,0x7d]
-
-v_cmp_ge_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xce,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_t_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0x9e,0x7d]
-
-v_cmp_t_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0x9e,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0x9e,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0x9f,0x7d]
-
-v_cmp_t_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa0,0x7d]
-
-v_cmpx_f_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa1,0x7d]
-
-v_cmpx_f_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa2,0x7d]
-
-v_cmpx_lt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa3,0x7d]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa4,0x7d]
-
-v_cmpx_eq_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa5,0x7d]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa6,0x7d]
-
-v_cmpx_le_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa7,0x7d]
-
-v_cmpx_le_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xa8,0x7d]
-
-v_cmpx_gt_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xa8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xa8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xa9,0x7d]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xaa,0x7d]
-
-v_cmpx_ne_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xaa,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xaa,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xab,0x7d]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xac,0x7d]
-
-v_cmpx_ge_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xac,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xac,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xad,0x7d]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_i32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xae,0x7d]
-
-v_cmpx_t_i32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xae,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_i32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xae,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_i32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xaf,0x7d]
-
-v_cmpx_t_i32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_i32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb0,0x7d]
-
-v_cmpx_f_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb1,0x7d]
-
-v_cmpx_f_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb2,0x7d]
-
-v_cmpx_lt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb3,0x7d]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb4,0x7d]
-
-v_cmpx_eq_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb5,0x7d]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xda,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb6,0x7d]
-
-v_cmpx_le_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb7,0x7d]
-
-v_cmpx_le_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xb8,0x7d]
-
-v_cmpx_gt_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xb8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xb8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xb9,0x7d]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xba,0x7d]
-
-v_cmpx_ne_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xba,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xba,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbb,0x7d]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbc,0x7d]
-
-v_cmpx_ge_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbc,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbc,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbd,0x7d]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xde,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_u32 vcc, v1, v2
-// CHECK: [0x01,0x05,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, v255, v2
-// CHECK: [0xff,0x05,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, s1, v2
-// CHECK: [0x01,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, s101, v2
-// CHECK: [0x65,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, flat_scratch_lo, v2
-// CHECK: [0x66,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, flat_scratch_hi, v2
-// CHECK: [0x67,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, vcc_lo, v2
-// CHECK: [0x6a,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, vcc_hi, v2
-// CHECK: [0x6b,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, m0, v2
-// CHECK: [0x7c,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, exec_lo, v2
-// CHECK: [0x7e,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, exec_hi, v2
-// CHECK: [0x7f,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, 0, v2
-// CHECK: [0x80,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, -1, v2
-// CHECK: [0xc1,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, 0.5, v2
-// CHECK: [0xf0,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, -4.0, v2
-// CHECK: [0xf7,0x04,0xbe,0x7d]
-
-v_cmpx_t_u32 vcc, 0xaf123456, v2
-// CHECK: [0xff,0x04,0xbe,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_u32 vcc, 0x3f717273, v2
-// CHECK: [0xff,0x04,0xbe,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_u32 vcc, v1, v255
-// CHECK: [0x01,0xff,0xbf,0x7d]
-
-v_cmpx_t_u32_e64 s[10:11], v1, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[12:13], v1, v2
-// CHECK: [0x0c,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[100:101], v1, v2
-// CHECK: [0x64,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 flat_scratch, v1, v2
-// CHECK: [0x66,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 vcc, v1, v2
-// CHECK: [0x6a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 exec, v1, v2
-// CHECK: [0x7e,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v255, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0xff,0x05,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], s1, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], s101, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x65,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], flat_scratch_lo, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], flat_scratch_hi, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x67,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], vcc_lo, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], vcc_hi, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x6b,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], m0, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x7c,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], exec_lo, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], exec_hi, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x7f,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], 0, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], -1, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], 0.5, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], -4.0, v2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, v255
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xff,0x03,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, s2
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x05,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, s101
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcb,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_lo
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_hi
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcf,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, vcc_lo
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, vcc_hi
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd7,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, m0
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf9,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, exec_lo
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, exec_hi
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xff,0x00,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, 0
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, -1
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, 0.5
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_u32_e64 s[10:11], v1, -4.0
-// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc0,0x7d]
-
-v_cmp_f_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc1,0x7d]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc2,0x7d]
-
-v_cmp_lt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc3,0x7d]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc4,0x7d]
-
-v_cmp_eq_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc5,0x7d]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc6,0x7d]
-
-v_cmp_le_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc7,0x7d]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xc8,0x7d]
-
-v_cmp_gt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xc9,0x7d]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xca,0x7d]
-
-v_cmp_ne_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcb,0x7d]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xcc,0x7d]
-
-v_cmp_ge_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcd,0x7d]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_t_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xce,0x7d]
-
-v_cmp_t_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xce,0x7d]
-
-v_cmp_t_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xce,0x7d]
-
-v_cmp_t_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xcf,0x7d]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_f_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd0,0x7d]
-
-v_cmp_f_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_f_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_f_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd1,0x7d]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_f_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_lt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd2,0x7d]
-
-v_cmp_lt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_lt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_lt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd3,0x7d]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_lt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_eq_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd4,0x7d]
-
-v_cmp_eq_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_eq_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_eq_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd5,0x7d]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xea,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_eq_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_le_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd6,0x7d]
-
-v_cmp_le_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_le_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_le_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd7,0x7d]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_le_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_gt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xd8,0x7d]
-
-v_cmp_gt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_gt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xd8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_gt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xd9,0x7d]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xec,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_gt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ne_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xda,0x7d]
-
-v_cmp_ne_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ne_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xda,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ne_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdb,0x7d]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xed,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ne_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_ge_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xdc,0x7d]
-
-v_cmp_ge_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_ge_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xdc,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_ge_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdd,0x7d]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xee,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_ge_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmp_t_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xde,0x7d]
-
-v_cmp_t_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xde,0x7d]
-
-v_cmp_t_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xde,0x7d]
-
-v_cmp_t_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmp_t_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xde,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmp_t_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xdf,0x7d]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xef,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmp_t_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe0,0x7d]
-
-v_cmpx_f_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe1,0x7d]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe2,0x7d]
-
-v_cmpx_lt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe3,0x7d]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe4,0x7d]
-
-v_cmpx_eq_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe5,0x7d]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe6,0x7d]
-
-v_cmpx_le_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe7,0x7d]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xe8,0x7d]
-
-v_cmpx_gt_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xe8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xe9,0x7d]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xea,0x7d]
-
-v_cmpx_ne_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xea,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xeb,0x7d]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xec,0x7d]
-
-v_cmpx_ge_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xec,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xed,0x7d]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_i64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xee,0x7d]
-
-v_cmpx_t_i64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_i64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xee,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_i64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xef,0x7d]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_i64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_f_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf0,0x7d]
-
-v_cmpx_f_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_f_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf0,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_f_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf1,0x7d]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_f_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_lt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf2,0x7d]
-
-v_cmpx_lt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_lt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf2,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_lt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf3,0x7d]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_lt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_eq_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf4,0x7d]
-
-v_cmpx_eq_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_eq_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf4,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_eq_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf5,0x7d]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_eq_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_le_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf6,0x7d]
-
-v_cmpx_le_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_le_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf6,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_le_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf7,0x7d]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_le_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_gt_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xf8,0x7d]
-
-v_cmpx_gt_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_gt_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xf8,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_gt_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xf9,0x7d]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_gt_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ne_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfa,0x7d]
-
-v_cmpx_ne_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ne_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfa,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ne_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfb,0x7d]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ne_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_ge_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfc,0x7d]
-
-v_cmpx_ge_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_ge_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfc,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_ge_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xfd,0x7d]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_ge_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xef,0x01,0x00]
-
-v_cmpx_t_u64 vcc, v[1:2], v[2:3]
-// CHECK: [0x01,0x05,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, v[254:255], v[2:3]
-// CHECK: [0xfe,0x05,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, s[2:3], v[2:3]
-// CHECK: [0x02,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, s[4:5], v[2:3]
-// CHECK: [0x04,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, s[100:101], v[2:3]
-// CHECK: [0x64,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, flat_scratch, v[2:3]
-// CHECK: [0x66,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, vcc, v[2:3]
-// CHECK: [0x6a,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, exec, v[2:3]
-// CHECK: [0x7e,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, 0, v[2:3]
-// CHECK: [0x80,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, -1, v[2:3]
-// CHECK: [0xc1,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, 0.5, v[2:3]
-// CHECK: [0xf0,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, -4.0, v[2:3]
-// CHECK: [0xf7,0x04,0xfe,0x7d]
-
-v_cmpx_t_u64 vcc, 0xaf123456, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7d,0x56,0x34,0x12,0xaf]
-
-v_cmpx_t_u64 vcc, 0x3f717273, v[2:3]
-// CHECK: [0xff,0x04,0xfe,0x7d,0x73,0x72,0x71,0x3f]
-
-v_cmpx_t_u64 vcc, v[1:2], v[254:255]
-// CHECK: [0x01,0xfd,0xff,0x7d]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[12:13], v[1:2], v[2:3]
-// CHECK: [0x0c,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[100:101], v[1:2], v[2:3]
-// CHECK: [0x64,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 flat_scratch, v[1:2], v[2:3]
-// CHECK: [0x66,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 vcc, v[1:2], v[2:3]
-// CHECK: [0x6a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 exec, v[1:2], v[2:3]
-// CHECK: [0x7e,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[254:255], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0xfe,0x05,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], s[2:3], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x02,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], s[4:5], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x04,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], s[100:101], v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x64,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], flat_scratch, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x66,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], vcc, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x6a,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], exec, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x7e,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], 0, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x80,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], -1, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0xc1,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], 0.5, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0xf0,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], -4.0, v[2:3]
-// CHECK: [0x0a,0x00,0xff,0xd0,0xf7,0x04,0x02,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], v[254:255]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfd,0x03,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], s[4:5]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x09,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], s[6:7]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x0d,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], s[100:101]
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xc9,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], flat_scratch
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xcd,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], vcc
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xd5,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], exec
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfd,0x00,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], 0
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x01,0x01,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], -1
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x83,0x01,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], 0.5
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xe1,0x01,0x00]
-
-v_cmpx_t_u64_e64 s[10:11], v[1:2], -4.0
-// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xef,0x01,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_mov_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_mov_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_mov_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_mov_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_u32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_u32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_u32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_u32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_u32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f16_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_f16_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f16_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_f16_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_f32_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_f32_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_rpi_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_rpi_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_flr_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_flr_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_off_f32_i4_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte0_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte1_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte2_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f32_ubyte3_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_fract_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_fract_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_fract_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_fract_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_fract_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_fract_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_fract_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_fract_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_trunc_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_trunc_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_trunc_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_trunc_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_trunc_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_trunc_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_trunc_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_trunc_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_ceil_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ceil_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_ceil_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ceil_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ceil_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ceil_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ceil_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_ceil_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_rndne_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rndne_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rndne_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rndne_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rndne_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rndne_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rndne_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rndne_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_floor_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_floor_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_floor_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_floor_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_floor_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_floor_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_floor_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_floor_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_exp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_exp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_exp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_exp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_exp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_exp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_exp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_exp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_log_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_log_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_log_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_log_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_log_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_log_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_log_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_log_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_log_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_log_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_log_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_log_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_log_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_rcp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rcp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rcp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rcp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rcp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rcp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rcp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rcp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rcp_iflag_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rcp_iflag_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rcp_iflag_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rcp_iflag_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_rsq_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rsq_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rsq_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rsq_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rsq_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rsq_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rsq_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rsq_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_sqrt_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sqrt_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sqrt_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sqrt_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_sqrt_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_sin_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sin_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sin_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sin_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sin_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sin_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sin_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_sin_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cos_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cos_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cos_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cos_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cos_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cos_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cos_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cos_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_not_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_not_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_not_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_not_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_not_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_not_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_not_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_not_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_not_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_not_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_bfrev_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_bfrev_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_bfrev_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ffbh_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ffbh_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ffbh_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ffbl_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ffbl_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ffbl_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ffbh_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ffbh_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ffbh_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_exp_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_frexp_exp_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_mant_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_mant_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_mant_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_frexp_mant_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f16_u16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cvt_f16_u16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cvt_f16_u16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f16_u16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_u16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_u16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_f16_i16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cvt_f16_i16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cvt_f16_i16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_f16_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x0e,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_i16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_f16_i16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_u16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_u16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_u16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_u16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_u16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cvt_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cvt_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cvt_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cvt_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cvt_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cvt_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_rcp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rcp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rcp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rcp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rcp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rcp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rcp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rcp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_sqrt_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sqrt_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sqrt_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sqrt_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sqrt_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_sqrt_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_rsq_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rsq_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rsq_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rsq_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rsq_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rsq_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rsq_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rsq_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_log_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_log_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_log_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_log_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_log_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_log_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_log_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_log_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_log_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_log_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_log_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_log_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_log_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_exp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_exp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_exp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_exp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_exp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_exp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_exp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_exp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_mant_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_mant_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_mant_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_mant_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_frexp_mant_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_frexp_exp_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_frexp_exp_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_floor_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_floor_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_floor_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_floor_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_floor_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_floor_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_floor_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_floor_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_ceil_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_ceil_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_ceil_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_ceil_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_ceil_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_ceil_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_ceil_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_ceil_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_trunc_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_trunc_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_trunc_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_trunc_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_trunc_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_rndne_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_rndne_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_rndne_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_rndne_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_rndne_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_rndne_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_rndne_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_rndne_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_fract_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_fract_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_fract_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_fract_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_fract_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_fract_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_fract_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_fract_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_sin_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_sin_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_sin_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_sin_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_sin_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_sin_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_sin_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_sin_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_cos_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_cos_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_cos_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_cos_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_cos_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_cos_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_cos_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_cos_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_exp_legacy_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_exp_legacy_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_exp_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_exp_legacy_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_exp_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_exp_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0xfe,0x7f,0x01,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0xff,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x65,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x66,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x67,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x6a,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x6b,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x7c,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x7e,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x7f,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x80,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0xc1,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0xf0,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0xf7,0x06,0x86,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x26,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x46,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x86,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0xc6,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x00,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x01,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x02,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x03,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x04,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x05,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x0e,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x16,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x00,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x01,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x02,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x03,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x04,0x00]
-
-v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x05,0x00]
-
-v_log_legacy_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x16,0x00]
-
-v_log_legacy_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x26,0x00]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x00]
-
-v_log_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0xfe,0x7f,0x01,0xe4,0x00,0x00]
-
-v_log_legacy_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0xff,0xe4,0x00,0x00]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x1b,0x00,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x40,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x41,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x42,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x43,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x30,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x34,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x38,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x3c,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x01,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x0f,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x11,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x1f,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x21,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x2f,0x01,0x00]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x10]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x30]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x01]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x03]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
-
-v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00]
-
-v_log_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x10,0x00]
-
-v_log_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x20,0x00]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x03,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0xff,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x65,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x66,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x67,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x6a,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x6b,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x7c,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x7e,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x7f,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x80,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0xc1,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0xf0,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0xf7,0x06,0x86,0x06]
-
-v_add_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x26,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x46,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x86,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0xc6,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x00,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x01,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x02,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x03,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x04,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x05,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x0e,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x00,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x01,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x02,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x03,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x04,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x05,0x06]
-
-v_add_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x16,0x06]
-
-v_add_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x00]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x01]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x02]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x03]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x04]
-
-v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x05]
-
-v_add_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x16]
-
-v_add_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x26]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
-
-v_add_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x03,0x01,0xe4,0x00,0x00]
-
-v_add_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0xff,0xe4,0x00,0x00]
-
-v_add_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x02,0x01,0xe4,0x00,0x00]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x42,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x43,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x30,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x34,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x38,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x3c,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0x00]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x10]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x30]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x01]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x03]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
-
-v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00]
-
-v_add_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x10,0x00]
-
-v_add_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x20,0x00]
-
-v_add_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x40,0x00]
-
-v_add_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x80,0x00]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x05,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0xff,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x65,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x66,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x67,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x6a,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x6b,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x7c,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x7e,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x7f,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x80,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0xc1,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0xf0,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0xf7,0x06,0x86,0x06]
-
-v_sub_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x26,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x46,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x86,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0xc6,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x00,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x01,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x02,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x03,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x04,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x05,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x0e,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x00,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x01,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x02,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x03,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x04,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x05,0x06]
-
-v_sub_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x16,0x06]
-
-v_sub_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x26,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x00]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x01]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x02]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x03]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x04]
-
-v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x05]
-
-v_sub_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x16]
-
-v_sub_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x26]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x05,0x01,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0xff,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x04,0x01,0xe4,0x00,0x00]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x42,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x43,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x30,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x34,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x38,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x3c,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0x00]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x10]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x30]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
-
-v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
-
-v_sub_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
-
-v_sub_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
-
-v_sub_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x40,0x00]
-
-v_sub_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x80,0x00]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x07,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0xff,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x65,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x66,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x67,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x6a,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x6b,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x7c,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x7e,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x7f,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x80,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0xc1,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0xf0,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0xf7,0x06,0x86,0x06]
-
-v_subrev_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x26,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x46,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x86,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0xc6,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x00,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x01,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x02,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x03,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x04,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x05,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x0e,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x00,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x01,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x02,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x03,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x04,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x05,0x06]
-
-v_subrev_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x16,0x06]
-
-v_subrev_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x26,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x00]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x01]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x02]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x03]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x04]
-
-v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x05]
-
-v_subrev_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x16]
-
-v_subrev_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x26]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0xff,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x06,0x01,0xe4,0x00,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x42,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x43,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x30,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x34,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x38,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x3c,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0x00]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x10]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x30]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
-
-v_subrev_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00]
-
-v_subrev_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00]
-
-v_subrev_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x40,0x00]
-
-v_subrev_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x80,0x00]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x09,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0xff,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x65,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x66,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x67,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x6a,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x6b,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x7c,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x7e,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x7f,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x80,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0xc1,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0xf0,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0xf7,0x06,0x86,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x26,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x46,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x86,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0xc6,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x00,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x01,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x02,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x03,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x04,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x05,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x0e,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x00,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x01,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x02,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x03,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x04,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x05,0x06]
-
-v_mul_legacy_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x16,0x06]
-
-v_mul_legacy_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x26,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x00]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x01]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x02]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x03]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x04]
-
-v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x05]
-
-v_mul_legacy_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x16]
-
-v_mul_legacy_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x26]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x09,0x01,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0xff,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x08,0x01,0xe4,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x42,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x43,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x30,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x34,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x38,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x3c,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x10]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x30]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
-
-v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
-
-v_mul_legacy_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00]
-
-v_mul_legacy_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x40,0x00]
-
-v_mul_legacy_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x80,0x00]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x0b,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0xff,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x65,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x66,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x67,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x6a,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x6b,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x7c,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x7e,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x7f,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x80,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0xc1,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0xf0,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0xf7,0x06,0x86,0x06]
-
-v_mul_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x26,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x46,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x86,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0xc6,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x00,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x01,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x02,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x03,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x04,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x05,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x0e,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x00,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x01,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x02,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x03,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x04,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x05,0x06]
-
-v_mul_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x16,0x06]
-
-v_mul_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x26,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x00]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x01]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x02]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x03]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x04]
-
-v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x05]
-
-v_mul_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x16]
-
-v_mul_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x26]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x0b,0x01,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0xff,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x0a,0x01,0xe4,0x00,0x00]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x42,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x43,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x30,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x34,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x38,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x3c,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0x00]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x10]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x30]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
-
-v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
-
-v_mul_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00]
-
-v_mul_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00]
-
-v_mul_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x40,0x00]
-
-v_mul_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x80,0x00]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x0d,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0xff,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x65,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x66,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x67,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x6a,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x6b,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x7c,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x7e,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x7f,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x80,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0xc1,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0xf0,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0xf7,0x06,0x86,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x26,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x00,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x01,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x02,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x03,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x04,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x05,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x0e,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x00,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x01,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x02,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x03,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x04,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x05,0x06]
-
-v_mul_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x0e,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x00]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x01]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x02]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x03]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x04]
-
-v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x05]
-
-v_mul_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x0e]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x0d,0x01,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0xff,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x0c,0x01,0xe4,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1b,0x00,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x40,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x41,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x42,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x43,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x30,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x34,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x38,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x3c,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x01,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x0f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x11,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x21,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x2f,0x01,0x00]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x10]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x30]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x01]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x03]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
-
-v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0xff,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x65,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x66,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x67,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x6a,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x6b,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x7c,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x7e,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x7f,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x80,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0xc1,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0xf0,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0xf7,0x06,0x86,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x00,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x01,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x02,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x03,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x04,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x05,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x0e,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x00,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x01,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x02,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x03,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x04,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x05,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x0e,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x00]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x01]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x02]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x03]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x04]
-
-v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x05]
-
-v_mul_hi_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x0e]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x0f,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0xff,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x0e,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x42,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x43,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x30,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x34,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x38,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x3c,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0x00]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x10]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x30]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0xff,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x65,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x66,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x67,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x6a,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x6b,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x7c,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x7e,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x7f,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x80,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0xc1,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0xf0,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0xf7,0x06,0x86,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x26,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x00,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x01,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x02,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x03,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x04,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x05,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x0e,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x00,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x01,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x02,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x03,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x04,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x05,0x06]
-
-v_mul_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x0e,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x00]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x01]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x02]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x03]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x04]
-
-v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x05]
-
-v_mul_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x0e]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x11,0x01,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0xff,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x10,0x01,0xe4,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x42,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x43,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x30,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x34,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x38,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x3c,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0x00]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x10]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x30]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
-
-v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0xff,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x65,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x66,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x67,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x6a,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x6b,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x7c,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x7e,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x7f,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x80,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0xc1,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0xf0,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0xf7,0x06,0x86,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x00,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x01,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x02,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x03,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x04,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x05,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x0e,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x00,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x01,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x02,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x03,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x04,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x05,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x0e,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x00]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x01]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x02]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x03]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x04]
-
-v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x05]
-
-v_mul_hi_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x0e]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x13,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0xff,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x12,0x01,0xe4,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x42,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x43,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x30,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x34,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x38,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x3c,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0x00]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x10]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x30]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
-
-v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0xff,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x65,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x66,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x67,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x6a,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x6b,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x7c,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x7e,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x7f,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x80,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0xc1,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0xf0,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0xf7,0x06,0x86,0x06]
-
-v_min_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x26,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x46,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x86,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0xc6,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x00,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x01,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x02,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x03,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x04,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x05,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x0e,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x00,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x01,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x02,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x03,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x04,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x05,0x06]
-
-v_min_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x16,0x06]
-
-v_min_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x26,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x00]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x01]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x02]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x03]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x04]
-
-v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x05]
-
-v_min_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x16]
-
-v_min_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x26]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x00]
-
-v_min_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x15,0x01,0xe4,0x00,0x00]
-
-v_min_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0xff,0xe4,0x00,0x00]
-
-v_min_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x14,0x01,0xe4,0x00,0x00]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x42,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x43,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x30,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x34,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x38,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x3c,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0x00]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x10]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x30]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
-
-v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
-
-v_min_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x10,0x00]
-
-v_min_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x20,0x00]
-
-v_min_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x40,0x00]
-
-v_min_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x80,0x00]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0xff,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x65,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x66,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x67,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x6a,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x6b,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x7c,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x7e,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x7f,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x80,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0xc1,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0xf0,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0xf7,0x06,0x86,0x06]
-
-v_max_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x26,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x46,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x86,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0xc6,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x00,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x01,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x02,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x03,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x04,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x05,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x0e,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x00,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x01,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x02,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x03,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x04,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x05,0x06]
-
-v_max_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x16,0x06]
-
-v_max_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x26,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x00]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x01]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x02]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x03]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x04]
-
-v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x05]
-
-v_max_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x16]
-
-v_max_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x26]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x00]
-
-v_max_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x17,0x01,0xe4,0x00,0x00]
-
-v_max_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0xff,0xe4,0x00,0x00]
-
-v_max_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x16,0x01,0xe4,0x00,0x00]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x42,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x43,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x30,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x34,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x38,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x3c,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0x00]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x10]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x30]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
-
-v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
-
-v_max_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x10,0x00]
-
-v_max_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x20,0x00]
-
-v_max_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x40,0x00]
-
-v_max_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x80,0x00]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x19,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0xff,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x65,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x66,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x67,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x6a,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x6b,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x7c,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x7e,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x7f,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x80,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0xc1,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0xf0,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0xf7,0x06,0x86,0x06]
-
-v_min_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x00,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x01,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x02,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x03,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x04,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x05,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x0e,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x00,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x01,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x02,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x03,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x04,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x05,0x06]
-
-v_min_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x0e,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x00]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x01]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x02]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x03]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x04]
-
-v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x05]
-
-v_min_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x0e]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x00]
-
-v_min_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x19,0x01,0xe4,0x00,0x00]
-
-v_min_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0xff,0xe4,0x00,0x00]
-
-v_min_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x18,0x01,0xe4,0x00,0x00]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x42,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x43,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x30,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x34,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x38,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x3c,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0x00]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x10]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x30]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
-
-v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x1b,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0xff,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x65,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x66,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x67,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x6a,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x6b,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x7c,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x7e,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x7f,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x80,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0xc1,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0xf0,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0xf7,0x06,0x86,0x06]
-
-v_max_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x00,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x01,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x02,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x03,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x04,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x05,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x0e,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x00,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x01,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x02,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x03,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x04,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x05,0x06]
-
-v_max_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x0e,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x00]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x01]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x02]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x03]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x04]
-
-v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x05]
-
-v_max_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x0e]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x00]
-
-v_max_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x1b,0x01,0xe4,0x00,0x00]
-
-v_max_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0xff,0xe4,0x00,0x00]
-
-v_max_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x1a,0x01,0xe4,0x00,0x00]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1b,0x00,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x40,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x41,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x42,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x43,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x30,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x34,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x38,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x3c,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x01,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x0f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x11,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x21,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x2f,0x01,0x00]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x10]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x30]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
-
-v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x1d,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0xff,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x65,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x66,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x67,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x6a,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x6b,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x7c,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x7e,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x7f,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x80,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0xc1,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0xf0,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0xf7,0x06,0x86,0x06]
-
-v_min_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x00,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x01,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x02,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x03,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x04,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x05,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x0e,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x00,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x01,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x02,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x03,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x04,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x05,0x06]
-
-v_min_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x0e,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x00]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x01]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x02]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x03]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x04]
-
-v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x05]
-
-v_min_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x0e]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x00]
-
-v_min_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x1d,0x01,0xe4,0x00,0x00]
-
-v_min_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0xff,0xe4,0x00,0x00]
-
-v_min_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x1c,0x01,0xe4,0x00,0x00]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1b,0x00,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x40,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x41,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x42,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x43,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x30,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x34,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x38,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x3c,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x01,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x0f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x11,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x21,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x2f,0x01,0x00]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x10]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x30]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x01]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x03]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
-
-v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0xff,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x65,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x66,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x67,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x6a,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x6b,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x7c,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x7e,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x7f,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x80,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0xc1,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0xf0,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0xf7,0x06,0x86,0x06]
-
-v_max_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x00,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x01,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x02,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x03,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x04,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x05,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x0e,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x00,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x01,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x02,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x03,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x04,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x05,0x06]
-
-v_max_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x0e,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x00]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x01]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x02]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x03]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x04]
-
-v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x05]
-
-v_max_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x0e]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x00]
-
-v_max_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x1f,0x01,0xe4,0x00,0x00]
-
-v_max_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0xff,0xe4,0x00,0x00]
-
-v_max_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x1e,0x01,0xe4,0x00,0x00]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x42,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x43,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x30,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x34,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x38,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x3c,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0x00]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x10]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x30]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
-
-v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0xff,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x65,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x66,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x67,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x6a,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x6b,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x7c,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x7e,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x7f,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x80,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0xc1,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0xf0,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0xf7,0x06,0x86,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x00,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x01,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x02,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x03,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x04,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x05,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x0e,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x00,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x01,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x02,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x03,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x04,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x05,0x06]
-
-v_lshrrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x0e,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x00]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x01]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x02]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x03]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x04]
-
-v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x05]
-
-v_lshrrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x0e]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x21,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0xff,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x20,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x42,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x43,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x30,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x34,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x38,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x3c,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0x00]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x10]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x30]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
-
-v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0xff,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x65,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x66,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x67,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x6a,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x6b,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x7c,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x7e,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x7f,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x80,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0xc1,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0xf0,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0xf7,0x06,0x86,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x00,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x01,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x02,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x03,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x04,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x05,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x0e,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x00,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x01,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x02,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x03,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x04,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x05,0x06]
-
-v_ashrrev_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x0e,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x00]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x01]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x02]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x03]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x04]
-
-v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x05]
-
-v_ashrrev_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x0e]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0xff,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x22,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x42,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x43,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x30,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x34,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x38,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x3c,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0x00]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x10]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x30]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
-
-v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0xff,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x65,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x66,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x67,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x6a,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x6b,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x7c,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x7e,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x7f,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x80,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0xc1,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0xf0,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0xf7,0x06,0x86,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x00,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x01,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x02,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x03,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x04,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x05,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x0e,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x00,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x01,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x02,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x03,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x04,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x05,0x06]
-
-v_lshlrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x0e,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x00]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x01]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x02]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x03]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x04]
-
-v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x05]
-
-v_lshlrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x0e]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0xff,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x24,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x42,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x43,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x30,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x34,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x38,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x3c,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0x00]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x10]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x30]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
-
-v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0xff,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x65,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x66,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x67,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x6a,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x6b,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x7c,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x7e,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x7f,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x80,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0xc1,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0xf0,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0xf7,0x06,0x86,0x06]
-
-v_and_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x00,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x01,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x02,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x03,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x04,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x05,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x0e,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x00,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x01,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x02,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x03,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x04,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x05,0x06]
-
-v_and_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x0e,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x00]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x01]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x02]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x03]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x04]
-
-v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x05]
-
-v_and_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x0e]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00]
-
-v_and_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00]
-
-v_and_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0xff,0xe4,0x00,0x00]
-
-v_and_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x26,0x01,0xe4,0x00,0x00]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x42,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x43,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x30,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x34,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x38,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x3c,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0x00]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x10]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x30]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
-
-v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0xff,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x65,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x66,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x67,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x6a,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x6b,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x7c,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x7e,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x7f,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x80,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0xc1,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0xf0,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0xf7,0x06,0x86,0x06]
-
-v_or_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x00,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x01,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x02,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x03,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x04,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x05,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x0e,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x00,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x01,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x02,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x03,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x04,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x05,0x06]
-
-v_or_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x0e,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x00]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x01]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x02]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x03]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x04]
-
-v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x05]
-
-v_or_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x0e]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00]
-
-v_or_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00]
-
-v_or_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0xff,0xe4,0x00,0x00]
-
-v_or_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x28,0x01,0xe4,0x00,0x00]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x42,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x43,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x30,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x34,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x38,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x3c,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0x00]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x10]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x30]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
-
-v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x2b,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0xff,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x65,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x66,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x67,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x6a,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x6b,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x7c,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x7e,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x7f,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x80,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0xc1,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0xf0,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0xf7,0x06,0x86,0x06]
-
-v_xor_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x00,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x01,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x02,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x03,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x04,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x05,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x0e,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x00,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x01,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x02,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x03,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x04,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x05,0x06]
-
-v_xor_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x0e,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x00]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x01]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x02]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x03]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x04]
-
-v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x05]
-
-v_xor_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x0e]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x2b,0x01,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0xff,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x2a,0x01,0xe4,0x00,0x00]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x42,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x43,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x30,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x34,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x38,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x3c,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0x00]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x10]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x30]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x01]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x03]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
-
-v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
-
-v_mac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
-
-v_mac_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0xff,0xe4,0x00,0x00]
-
-v_mac_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x2c,0x01,0xe4,0x00,0x00]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x42,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x43,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x30,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x34,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x38,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x3c,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0x00]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x10]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x30]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
-
-v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
-
-v_mac_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x10,0x00]
-
-v_mac_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x20,0x00]
-
-v_mac_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x40,0x00]
-
-v_mac_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x80,0x00]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
-
-v_add_co_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x33,0x01,0x06,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0xff,0x06,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x65,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x66,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x67,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x6a,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x6b,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x7c,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x7e,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x7f,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x80,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0xc1,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0xf0,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0xf7,0x06,0x86,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x32,0x01,0x06,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x26,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x00,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x01,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x02,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x03,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x04,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x05,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x0e,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x00,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x01,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x02,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x03,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x04,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x05,0x06]
-
-v_add_co_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x0e,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x00]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x01]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x02]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x03]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x04]
-
-v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x05]
-
-v_add_co_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x0e]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x00]
-
-v_add_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x33,0x01,0xe4,0x00,0x00]
-
-v_add_co_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0xff,0xe4,0x00,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x32,0x01,0xe4,0x00,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x42,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x43,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x30,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x34,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x38,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x3c,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0x00]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x10]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x30]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x01]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x03]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
-
-v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_co_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0xff,0x06,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x65,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x66,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x67,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x6a,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x6b,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x7c,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x7e,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x7f,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x80,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0xc1,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0xf0,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0xf7,0x06,0x86,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x26,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x00,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x01,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x02,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x03,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x04,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x05,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x0e,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x00,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x01,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x02,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x03,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x04,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x05,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x0e,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x00]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x01]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x02]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x03]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x04]
-
-v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x05]
-
-v_sub_co_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x0e]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00]
-
-v_sub_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0xff,0xe4,0x00,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x34,0x01,0xe4,0x00,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x42,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x43,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x30,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x34,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x38,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x3c,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0x00]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x10]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x30]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
-
-v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_co_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0xff,0x06,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x65,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x66,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x67,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x6a,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x6b,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x7c,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x7e,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x7f,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x80,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0xc1,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0xf0,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0xf7,0x06,0x86,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x26,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x00,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x01,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x02,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x03,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x04,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x05,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x0e,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x00,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x01,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x02,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x03,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x04,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x05,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x0e,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x00]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x01]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x02]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x03]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x04]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x05]
-
-v_subrev_co_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x0e]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x00]
-
-v_subrev_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x37,0x01,0xe4,0x00,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0xff,0xe4,0x00,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x36,0x01,0xe4,0x00,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x42,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x43,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x30,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x34,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x38,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x3c,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0x00]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x10]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x30]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
-
-v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_co_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0xff,0x06,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, 0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x80,0x06,0x86,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0xc1,0x06,0x86,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, 0.5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0xf0,0x06,0x86,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, -4.0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0xf7,0x06,0x86,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x26,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x00,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x01,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x02,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x03,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x04,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x05,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x0e,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x00,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x01,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x02,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x03,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x04,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x05,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x0e,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x00]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x01]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x02]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x03]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x04]
-
-v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x05]
-
-v_addc_co_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x0e]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x00]
-
-v_addc_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x39,0x01,0xe4,0x00,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0xff,0xe4,0x00,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x38,0x01,0xe4,0x00,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x42,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x43,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x30,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x34,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x38,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x3c,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0x00]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x10]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x30]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
-
-v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_co_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0xff,0x06,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, 0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x80,0x06,0x86,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0xc1,0x06,0x86,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, 0.5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0xf0,0x06,0x86,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, -4.0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0xf7,0x06,0x86,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x26,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x00,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x01,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x02,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x03,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x04,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x05,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x0e,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x00,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x01,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x02,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x03,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x04,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x05,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x0e,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x00]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x01]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x02]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x03]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x04]
-
-v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x05]
-
-v_subb_co_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x0e]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x00]
-
-v_subb_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x3b,0x01,0xe4,0x00,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0xff,0xe4,0x00,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x3a,0x01,0xe4,0x00,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x42,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x43,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x30,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x34,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x38,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x3c,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0x00]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x10]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x30]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
-
-v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0xff,0x06,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, 0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x80,0x06,0x86,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0xc1,0x06,0x86,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, 0.5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0xf0,0x06,0x86,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, -4.0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0xf7,0x06,0x86,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x26,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x00,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x01,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x02,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x03,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x04,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x05,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x0e,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x00,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x01,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x02,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x03,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x04,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x05,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x0e,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x00]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x01]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x02]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x03]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x04]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x05]
-
-v_subbrev_co_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x0e]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x00]
-
-v_subbrev_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x3d,0x01,0xe4,0x00,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0xff,0xe4,0x00,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x3c,0x01,0xe4,0x00,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x42,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x43,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x30,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x34,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x38,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x3c,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0x00]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x10]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x30]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
-
-v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x3f,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0xff,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x65,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x66,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x67,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x6a,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x6b,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x7c,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x7e,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x7f,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x80,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0xc1,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0xf0,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0xf7,0x06,0x86,0x06]
-
-v_add_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x26,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x00,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x01,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x02,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x03,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x04,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x05,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x0e,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x00,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x01,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x02,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x03,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x04,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x05,0x06]
-
-v_add_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x16,0x06]
-
-v_add_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x26,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x00]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x01]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x02]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x03]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x04]
-
-v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x05]
-
-v_add_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x16]
-
-v_add_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x26]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x00]
-
-v_add_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x3f,0x01,0xe4,0x00,0x00]
-
-v_add_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0xff,0xe4,0x00,0x00]
-
-v_add_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x3e,0x01,0xe4,0x00,0x00]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x00,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x40,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x41,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x42,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x43,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x30,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x34,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x38,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x3c,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x01,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x0f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x11,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x21,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x2f,0x01,0x00]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x10]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x30]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x01]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x03]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
-
-v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00]
-
-v_add_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x10,0x00]
-
-v_add_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x20,0x00]
-
-v_add_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x40,0x00]
-
-v_add_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x80,0x00]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x41,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0xff,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x65,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x66,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x67,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x6a,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x6b,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x7c,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x7e,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x7f,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x80,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0xc1,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0xf0,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0xf7,0x06,0x86,0x06]
-
-v_sub_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x26,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x00,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x01,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x02,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x03,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x04,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x05,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x0e,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x00,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x01,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x02,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x03,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x04,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x05,0x06]
-
-v_sub_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x16,0x06]
-
-v_sub_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x26,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x00]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x01]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x02]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x03]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x04]
-
-v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x05]
-
-v_sub_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x16]
-
-v_sub_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x26]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x41,0x01,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0xff,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x40,0x01,0xe4,0x00,0x00]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x42,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x43,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x30,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x34,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x38,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x3c,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0x00]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x10]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x30]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x01]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x03]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
-
-v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00]
-
-v_sub_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x10,0x00]
-
-v_sub_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x20,0x00]
-
-v_sub_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x40,0x00]
-
-v_sub_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x80,0x00]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x43,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0xff,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x65,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x66,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x67,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x6a,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x6b,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x7c,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x7e,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x7f,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x80,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0xc1,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0xf0,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0xf7,0x06,0x86,0x06]
-
-v_subrev_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x26,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x00,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x01,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x02,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x03,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x04,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x05,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x0e,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x00,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x01,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x02,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x03,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x04,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x05,0x06]
-
-v_subrev_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x16,0x06]
-
-v_subrev_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x26,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x00]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x01]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x02]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x03]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x04]
-
-v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x05]
-
-v_subrev_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x16]
-
-v_subrev_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x26]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x43,0x01,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0xff,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x42,0x01,0xe4,0x00,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x42,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x43,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x30,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x34,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x38,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x3c,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0x00]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x10]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x30]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x01]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x03]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
-
-v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00]
-
-v_subrev_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x10,0x00]
-
-v_subrev_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x20,0x00]
-
-v_subrev_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x40,0x00]
-
-v_subrev_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x80,0x00]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x45,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0xff,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x65,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x66,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x67,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x6a,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x6b,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x7c,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x7e,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x7f,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x80,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0xc1,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0xf0,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0xf7,0x06,0x86,0x06]
-
-v_mul_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x26,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x00,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x01,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x02,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x03,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x04,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x05,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x0e,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x00,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x01,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x02,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x03,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x04,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x05,0x06]
-
-v_mul_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x16,0x06]
-
-v_mul_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x26,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x00]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x01]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x02]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x03]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x04]
-
-v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x05]
-
-v_mul_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x16]
-
-v_mul_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x26]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x45,0x01,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0xff,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x44,0x01,0xe4,0x00,0x00]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x42,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x43,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x30,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x34,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x38,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x3c,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0x00]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x10]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x30]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x01]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x03]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
-
-v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00]
-
-v_mul_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x10,0x00]
-
-v_mul_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x20,0x00]
-
-v_mul_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x40,0x00]
-
-v_mul_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x80,0x00]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x00]
-
-v_mac_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x47,0x01,0xe4,0x00,0x00]
-
-v_mac_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0xff,0xe4,0x00,0x00]
-
-v_mac_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x46,0x01,0xe4,0x00,0x00]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1b,0x00,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x40,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x41,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x42,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x43,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x30,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x34,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x38,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x3c,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x01,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x0f,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x11,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1f,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x21,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x2f,0x01,0x00]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x10]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x30]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x01]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x03]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
-
-v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00]
-
-v_mac_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x10,0x00]
-
-v_mac_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x20,0x00]
-
-v_mac_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x40,0x00]
-
-v_mac_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x80,0x00]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x4d,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0xff,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x65,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x66,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x67,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x6a,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x6b,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x7c,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x7e,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x7f,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x80,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0xc1,0x06,0x86,0x06]
-
-v_add_u16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_add_u16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_add_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x26,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x00,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x01,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x02,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x03,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x04,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x05,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x0e,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x00,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x01,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x02,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x03,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x04,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x05,0x06]
-
-v_add_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x0e,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x00]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x01]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x02]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x03]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x04]
-
-v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x05]
-
-v_add_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x0e]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x00]
-
-v_add_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x4d,0x01,0xe4,0x00,0x00]
-
-v_add_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0xff,0xe4,0x00,0x00]
-
-v_add_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x4c,0x01,0xe4,0x00,0x00]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x42,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x43,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x30,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x34,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x38,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x3c,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0x00]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x10]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x30]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x01]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x03]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
-
-v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0xff,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x65,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x66,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x67,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x6a,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x6b,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x7c,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x7e,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x7f,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x80,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0xc1,0x06,0x86,0x06]
-
-v_sub_u16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_sub_u16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_sub_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x26,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x00,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x01,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x02,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x03,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x04,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x05,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x0e,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x00,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x01,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x02,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x03,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x04,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x05,0x06]
-
-v_sub_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x0e,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x00]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x01]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x02]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x03]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x04]
-
-v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x05]
-
-v_sub_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x0e]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x00]
-
-v_sub_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x4f,0x01,0xe4,0x00,0x00]
-
-v_sub_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0xff,0xe4,0x00,0x00]
-
-v_sub_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x4e,0x01,0xe4,0x00,0x00]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x42,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x43,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x30,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x34,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x38,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x3c,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0x00]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x10]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x30]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x01]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x03]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
-
-v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x65,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x66,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x67,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x6a,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x6b,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x7c,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x7e,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x7f,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x80,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0xc1,0x06,0x86,0x06]
-
-v_subrev_u16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_subrev_u16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_subrev_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x26,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x00,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x01,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x02,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x03,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x04,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x05,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x0e,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x00,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x01,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x02,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x03,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x04,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x05,0x06]
-
-v_subrev_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x0e,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x00]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x01]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x02]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x03]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x04]
-
-v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x05]
-
-v_subrev_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x0e]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00]
-
-v_subrev_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x51,0x01,0xe4,0x00,0x00]
-
-v_subrev_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0xff,0xe4,0x00,0x00]
-
-v_subrev_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x50,0x01,0xe4,0x00,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x40,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x41,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x42,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x43,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x30,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x34,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x38,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x3c,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x01,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x0f,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x11,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1f,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x21,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x2f,0x01,0x00]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x10]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x30]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x01]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x03]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
-
-v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x65,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x66,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x67,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x6a,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x6b,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x7c,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x7e,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x7f,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x80,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0xc1,0x06,0x86,0x06]
-
-v_mul_lo_u16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_mul_lo_u16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_mul_lo_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x00,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x01,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x02,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x03,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x04,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x05,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x0e,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x00,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x01,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x02,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x03,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x04,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x05,0x06]
-
-v_mul_lo_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x0e,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x00]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x01]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x02]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x03]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x04]
-
-v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x05]
-
-v_mul_lo_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x0e]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x00]
-
-v_mul_lo_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x53,0x01,0xe4,0x00,0x00]
-
-v_mul_lo_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0xff,0xe4,0x00,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x52,0x01,0xe4,0x00,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x00,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x40,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x41,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x42,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x43,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x30,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x34,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x38,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x3c,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x01,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x0f,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x11,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1f,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x21,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x2f,0x01,0x00]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x10]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x30]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x01]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x03]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
-
-v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x65,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x66,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x67,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x6a,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x6b,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x7c,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x7e,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x7f,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x80,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0xc1,0x06,0x86,0x06]
-
-v_lshlrev_b16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_lshlrev_b16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_lshlrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x00,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x01,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x02,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x03,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x04,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x05,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x0e,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x00,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x01,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x02,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x03,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x04,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x05,0x06]
-
-v_lshlrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x0e,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x00]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x01]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x02]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x03]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x04]
-
-v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x05]
-
-v_lshlrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x0e]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x55,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0xff,0xe4,0x00,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x54,0x01,0xe4,0x00,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x00,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x40,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x41,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x42,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x43,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x30,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x34,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x38,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x3c,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x01,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x0f,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x11,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1f,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x21,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x2f,0x01,0x00]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x10]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x30]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x01]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x03]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
-
-v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x57,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0xff,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x65,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x66,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x67,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x6a,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x6b,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x7c,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x7e,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x7f,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x80,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0xc1,0x06,0x86,0x06]
-
-v_lshrrev_b16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_lshrrev_b16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_lshrrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x00,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x01,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x02,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x03,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x04,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x05,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x0e,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x00,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x01,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x02,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x03,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x04,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x05,0x06]
-
-v_lshrrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x0e,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x00]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x01]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x02]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x03]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x04]
-
-v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x05]
-
-v_lshrrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x0e]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x57,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0xff,0xe4,0x00,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x56,0x01,0xe4,0x00,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x42,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x43,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x30,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x34,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x38,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x3c,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0x00]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x10]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x30]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x01]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x03]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
-
-v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x59,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0xff,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x65,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x66,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x67,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x6a,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x6b,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x7c,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x7e,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x7f,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x80,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0xc1,0x06,0x86,0x06]
-
-v_ashrrev_i16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_ashrrev_i16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_ashrrev_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x00,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x01,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x02,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x03,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x04,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x05,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x0e,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x00,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x01,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x02,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x03,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x04,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x05,0x06]
-
-v_ashrrev_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x0e,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x00]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x01]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x02]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x03]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x04]
-
-v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x05]
-
-v_ashrrev_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x0e]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x59,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0xff,0xe4,0x00,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x58,0x01,0xe4,0x00,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1b,0x00,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x40,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x41,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x42,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x43,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x30,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x34,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x38,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x3c,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x01,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x0f,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x11,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1f,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x21,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x2f,0x01,0x00]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x10]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x30]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x01]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x03]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
-
-v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x5b,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0xff,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x65,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x66,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x67,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x6a,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x6b,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x7c,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x7e,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x7f,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x80,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0xc1,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0xf0,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0xf7,0x06,0x86,0x06]
-
-v_max_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x26,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x00,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x01,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x02,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x03,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x04,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x05,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x0e,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x00,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x01,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x02,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x03,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x04,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x05,0x06]
-
-v_max_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x16,0x06]
-
-v_max_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x26,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x00]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x01]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x02]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x03]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x04]
-
-v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x05]
-
-v_max_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x16]
-
-v_max_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x26]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x00]
-
-v_max_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x5b,0x01,0xe4,0x00,0x00]
-
-v_max_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0xff,0xe4,0x00,0x00]
-
-v_max_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x5a,0x01,0xe4,0x00,0x00]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1b,0x00,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x40,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x41,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x42,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x43,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x30,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x34,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x38,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x3c,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x01,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x0f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x11,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x21,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x2f,0x01,0x00]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x10]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x30]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x01]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x03]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
-
-v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00]
-
-v_max_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x10,0x00]
-
-v_max_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x20,0x00]
-
-v_max_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x40,0x00]
-
-v_max_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x80,0x00]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x5d,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0xff,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x65,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x66,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x67,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x6a,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x6b,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x7c,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x7e,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x7f,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x80,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0xc1,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0xf0,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0xf7,0x06,0x86,0x06]
-
-v_min_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x26,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x00,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x01,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x02,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x03,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x04,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x05,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x0e,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x00,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x01,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x02,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x03,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x04,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x05,0x06]
-
-v_min_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x16,0x06]
-
-v_min_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x26,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x00]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x01]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x02]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x03]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x04]
-
-v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x05]
-
-v_min_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x16]
-
-v_min_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x26]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x00]
-
-v_min_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x5d,0x01,0xe4,0x00,0x00]
-
-v_min_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0xff,0xe4,0x00,0x00]
-
-v_min_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x5c,0x01,0xe4,0x00,0x00]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1b,0x00,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x40,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x41,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x42,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x43,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x30,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x34,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x38,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x3c,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x01,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x0f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x11,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x21,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x2f,0x01,0x00]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x10]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x30]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x01]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x03]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
-
-v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00]
-
-v_min_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x10,0x00]
-
-v_min_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x20,0x00]
-
-v_min_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x40,0x00]
-
-v_min_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x80,0x00]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x5f,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0xff,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x65,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x66,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x67,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x6a,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x6b,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x7c,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x7e,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x7f,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x80,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0xc1,0x06,0x86,0x06]
-
-v_max_u16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_max_u16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_max_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x00,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x01,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x02,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x03,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x04,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x05,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x0e,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x00,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x01,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x02,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x03,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x04,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x05,0x06]
-
-v_max_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x0e,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x00]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x01]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x02]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x03]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x04]
-
-v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x05]
-
-v_max_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x0e]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x00]
-
-v_max_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x5f,0x01,0xe4,0x00,0x00]
-
-v_max_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0xff,0xe4,0x00,0x00]
-
-v_max_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x5e,0x01,0xe4,0x00,0x00]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x42,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x43,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x30,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x34,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x38,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x3c,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0x00]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x10]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x30]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x01]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x03]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
-
-v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x61,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0xff,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x65,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x66,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x67,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x6a,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x6b,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x7c,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x7e,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x7f,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x80,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0xc1,0x06,0x86,0x06]
-
-v_max_i16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_max_i16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_max_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x00,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x01,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x02,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x03,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x04,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x05,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x0e,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x00,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x01,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x02,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x03,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x04,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x05,0x06]
-
-v_max_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x0e,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x00]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x01]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x02]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x03]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x04]
-
-v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x05]
-
-v_max_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x0e]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x00]
-
-v_max_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x61,0x01,0xe4,0x00,0x00]
-
-v_max_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0xff,0xe4,0x00,0x00]
-
-v_max_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x60,0x01,0xe4,0x00,0x00]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x42,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x43,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x30,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x34,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x38,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x3c,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0x00]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x10]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x30]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x01]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x03]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
-
-v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x63,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0xff,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x65,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x66,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x67,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x6a,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x6b,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x7c,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x7e,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x7f,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x80,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0xc1,0x06,0x86,0x06]
-
-v_min_u16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_min_u16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_min_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x00,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x01,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x02,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x03,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x04,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x05,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x0e,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x00,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x01,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x02,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x03,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x04,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x05,0x06]
-
-v_min_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x0e,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x00]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x01]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x02]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x03]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x04]
-
-v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x05]
-
-v_min_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x0e]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x00]
-
-v_min_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x63,0x01,0xe4,0x00,0x00]
-
-v_min_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0xff,0xe4,0x00,0x00]
-
-v_min_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x62,0x01,0xe4,0x00,0x00]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x42,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x43,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x30,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x34,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x38,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x3c,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0x00]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x10]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x30]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x01]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x03]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
-
-v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0xff,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x65,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x66,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x67,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x6a,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x6b,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x7c,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x7e,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x7f,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x80,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0xc1,0x06,0x86,0x06]
-
-v_min_i16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_min_i16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_min_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x00,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x01,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x02,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x03,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x04,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x05,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x0e,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x00,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x01,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x02,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x03,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x04,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x05,0x06]
-
-v_min_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x0e,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x00]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x01]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x02]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x03]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x04]
-
-v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x05]
-
-v_min_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x0e]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x00]
-
-v_min_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00]
-
-v_min_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0xff,0xe4,0x00,0x00]
-
-v_min_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x64,0x01,0xe4,0x00,0x00]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x42,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x43,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x30,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x34,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x38,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x3c,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0x00]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x10]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x30]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
-
-v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0xff,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x65,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x66,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x67,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x6a,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x6b,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x7c,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x7e,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x7f,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x80,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0xc1,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0xf0,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0xf7,0x06,0x86,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x26,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x00,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x01,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x02,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x03,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x04,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x05,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x0e,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x00,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x01,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x02,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x03,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x04,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x05,0x06]
-
-v_ldexp_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x16,0x06]
-
-v_ldexp_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x26,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x00]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x01]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x02]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x03]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x04]
-
-v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x05]
-
-v_ldexp_f16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x0e]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0xff,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x66,0x01,0xe4,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x42,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x43,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x30,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x34,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x38,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x3c,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0x00]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x10]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x30]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
-
-v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
-
-v_ldexp_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
-
-v_ldexp_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x69,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0xff,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x65,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x66,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x67,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x6a,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x6b,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x7c,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x7e,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x7f,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x80,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0xc1,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0xf0,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0xf7,0x06,0x86,0x06]
-
-v_add_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x68,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x26,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x00,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x01,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x02,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x03,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x04,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x05,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x0e,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x16,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x16,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x00,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x01,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x02,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x03,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x04,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x05,0x06]
-
-v_add_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x0e,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x00]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x01]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x02]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x03]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x04]
-
-v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x05]
-
-v_add_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x0e]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x00]
-
-v_add_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x69,0x01,0xe4,0x00,0x00]
-
-v_add_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0xff,0xe4,0x00,0x00]
-
-v_add_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x68,0x01,0xe4,0x00,0x00]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x42,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x43,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x30,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x34,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x38,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x3c,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0x00]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x10]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x30]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xf0]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xf0]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x01]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x03]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x0f]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x0f]
-
-v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x6b,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0xff,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x65,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x66,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x67,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x6a,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x6b,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x7c,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x7e,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x7f,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x80,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0xc1,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0xf0,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0xf7,0x06,0x86,0x06]
-
-v_sub_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x6a,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x26,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x00,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x01,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x02,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x03,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x04,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x05,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x0e,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x16,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x16,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x00,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x01,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x02,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x03,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x04,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x05,0x06]
-
-v_sub_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x0e,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x00]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x01]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x02]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x03]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x04]
-
-v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x05]
-
-v_sub_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x0e]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x00]
-
-v_sub_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x6b,0x01,0xe4,0x00,0x00]
-
-v_sub_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0xff,0xe4,0x00,0x00]
-
-v_sub_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x6a,0x01,0xe4,0x00,0x00]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x42,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x43,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x30,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x34,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x38,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x3c,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0x00]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x10]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x30]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xf0]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xf0]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x01]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x03]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x0f]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x0f]
-
-v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xfe,0x6d,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0xff,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x65,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x66,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x67,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x6a,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x6b,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x7c,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x7e,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x7f,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x80,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0xc1,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0xf0,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0xf7,0x06,0x86,0x06]
-
-v_subrev_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x0b,0x6c,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x26,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x00,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x01,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x02,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x03,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x04,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x05,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x0e,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x16,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x16,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x00,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x01,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x02,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x03,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x04,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x05,0x06]
-
-v_subrev_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x0e,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x00]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x01]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x02]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x03]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x04]
-
-v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x05]
-
-v_subrev_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x0e]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x00]
-
-v_subrev_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0xfe,0x6d,0x01,0xe4,0x00,0x00]
-
-v_subrev_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0xff,0xe4,0x00,0x00]
-
-v_subrev_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0xfe,0x0b,0x6c,0x01,0xe4,0x00,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x42,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x43,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x30,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x34,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x38,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x3c,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0x00]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x10]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x30]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xf0]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xf0]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x01]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x03]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x0f]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x0f]
-
-v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
-// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x08,0x00]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_class_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_class_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_class_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x21,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_class_f32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x0e]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_class_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_class_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_class_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x23,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_class_f32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x0e]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_class_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_class_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_class_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x29,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_class_f16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x0e]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_class_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_class_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_class_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x2b,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_class_f16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x0e]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_f_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_f_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_f_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x41,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_f_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_f_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_lt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_lt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x43,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_lt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_eq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_eq_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x45,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_eq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_le_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_le_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_le_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x47,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_le_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_le_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_gt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_gt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x49,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_gt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_lg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_lg_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4b,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_lg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_ge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_ge_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4d,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_ge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_o_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_o_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_o_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4f,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_o_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_o_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_u_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_u_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_u_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x51,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_u_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_u_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_nge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_nge_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x53,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_nge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x55,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_nlg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x57,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_ngt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nle_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_nle_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_nle_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x59,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_nle_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_neq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_neq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_neq_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5b,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_neq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5d,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_nlt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_tru_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_tru_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_tru_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5f,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_tru_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_f_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_f_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x61,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_f_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x63,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_lt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x65,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_eq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_le_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_le_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x67,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_le_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x69,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_gt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6b,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_lg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6d,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_ge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_o_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_o_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_o_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6f,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_o_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_u_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_u_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_u_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x71,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_u_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x73,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_nge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x75,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_nlg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x77,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_ngt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x79,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_nle_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7b,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_neq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7d,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_nlt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7f,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_tru_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_f_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_f_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_f_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x81,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_f_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_f_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_lt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_lt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x83,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_lt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_eq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_eq_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x85,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_eq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_le_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_le_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_le_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x87,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_le_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_le_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_gt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_gt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x89,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_gt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_lg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_lg_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8b,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_lg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_ge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_ge_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8d,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_ge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_o_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_o_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_o_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8f,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_o_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_o_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_u_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_u_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_u_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x91,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_u_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_u_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_nge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_nge_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x93,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_nge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x95,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_nlg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x97,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_ngt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nle_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_nle_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_nle_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x99,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_nle_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_neq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_neq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_neq_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9b,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_neq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9d,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_nlt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_tru_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmp_tru_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmp_tru_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9f,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmp_tru_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_f_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_f_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa1,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_f_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa3,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_lt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa5,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_eq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_le_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_le_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa7,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_le_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa9,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_gt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xab,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_lg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xad,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_ge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_o_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_o_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_o_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xaf,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_o_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_u_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_u_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_u_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb1,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_u_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb3,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_nge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb5,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_nlg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb7,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_ngt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb9,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_nle_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbb,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_neq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbd,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_nlt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x88,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0xe4,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0xe6,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0xff,0x86,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x65,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x66,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x67,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x6a,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x6b,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x7c,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x7e,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x7f,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x80,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0xc1,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0xf0,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0xf7,0x86,0x86,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbf,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x00,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x01,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x02,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x03,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x04,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x05,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x16,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x26,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x06]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x00]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x01]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x02]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x03]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x04]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x05]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x16]
-
-v_cmpx_tru_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x26]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_f_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_f_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_f_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_f_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x41,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_f_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_lt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_lt_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x43,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_lt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_eq_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_eq_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x45,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_eq_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_le_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_le_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_le_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x47,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_le_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_gt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_gt_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x49,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_gt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_ne_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_ne_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4b,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_ne_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_ge_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_ge_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4d,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_ge_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_t_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_t_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_t_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_t_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x4f,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_t_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_f_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_f_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_f_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_f_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x51,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_f_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_lt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_lt_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x53,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_lt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_eq_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_eq_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x55,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_eq_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_le_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_le_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_le_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x57,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_le_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_gt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_gt_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x59,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_gt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_ne_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_ne_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5b,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_ne_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_ge_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_ge_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5d,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_ge_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_t_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_t_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_t_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmp_t_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x5f,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_t_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_f_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_f_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_f_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x61,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_f_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_lt_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x63,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_lt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_eq_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x65,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_eq_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_le_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_le_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_le_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x67,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_le_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_gt_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x69,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_gt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_ne_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6b,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_ne_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_ge_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6d,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_ge_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_t_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_t_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_t_i16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x6f,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_t_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_f_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_f_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_f_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x71,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_f_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_lt_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x73,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_lt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_eq_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x75,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_eq_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_le_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_le_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_le_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x77,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_le_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_gt_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x79,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_gt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_ne_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7b,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_ne_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_ge_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7d,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_ge_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_t_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_t_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_t_u16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK-ERR: error: invalid operand for instruction
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x7f,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_t_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_f_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_f_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x81,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_f_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_lt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_lt_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x83,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_lt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_eq_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_eq_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x85,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_eq_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_le_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_le_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x87,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_le_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_gt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_gt_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x89,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_gt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_ne_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_ne_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8b,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_ne_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_ge_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_ge_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8d,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_ge_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_t_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_t_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x8f,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_t_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_f_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_f_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x91,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_f_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_lt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_lt_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x93,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_lt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_eq_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_eq_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x95,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_eq_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_le_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_le_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x97,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_le_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_gt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_gt_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x99,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_gt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_ne_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_ne_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9b,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_ne_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_ge_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_ge_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9d,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_ge_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmp_t_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmp_t_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0x9f,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmp_t_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_f_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_f_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa1,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_f_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa3,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_lt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa5,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_eq_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_le_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_le_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa7,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_le_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xa9,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_gt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xab,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_ne_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xad,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_ge_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_t_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_t_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xaf,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_t_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_f_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_f_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb1,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_f_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb3,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_lt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb5,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_eq_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_le_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_le_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb7,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_le_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xb9,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_gt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbb,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_ne_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbd,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_ge_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x0e]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x88,0x06,0x06]
-
-v_cmpx_t_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0xe4,0x06,0x06]
-
-v_cmpx_t_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0xe6,0x06,0x06]
-
-v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0xff,0x86,0x06,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x65,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x66,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x67,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x6a,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x6b,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x7c,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x7e,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x7f,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x80,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0xc1,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0xf0,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0xf7,0x86,0x86,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0xfe,0xbf,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x00,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x01,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x02,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x03,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x04,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x05,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x0e,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x06]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x00]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x01]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x02]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x03]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x04]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x05]
-
-v_cmpx_t_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
-// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x0e]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_ds.s b/llvm/test/MC/AMDGPU/gfx9_asm_ds.s
new file mode 100644
index 0000000000000..bc33579b10389
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_ds.s
@@ -0,0 +1,3364 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+ds_add_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd8,0xff,0x02,0x00,0x00]
+
+ds_add_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd8,0x01,0xff,0x00,0x00]
+
+ds_add_u32 v1, v2
+// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x00,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x01,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd8,0xff,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd8,0x01,0xff,0x00,0x00]
+
+ds_sub_u32 v1, v2
+// CHECK: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x02,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x03,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd8,0xff,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd8,0x01,0xff,0x00,0x00]
+
+ds_rsub_u32 v1, v2
+// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x04,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x05,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd8,0xff,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd8,0x01,0xff,0x00,0x00]
+
+ds_inc_u32 v1, v2
+// CHECK: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x06,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x07,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd8,0xff,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd8,0x01,0xff,0x00,0x00]
+
+ds_dec_u32 v1, v2
+// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x08,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x09,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_i32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd8,0x01,0xff,0x00,0x00]
+
+ds_min_i32 v1, v2
+// CHECK: [0x00,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x0a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x0b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_i32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd8,0x01,0xff,0x00,0x00]
+
+ds_max_i32 v1, v2
+// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x0c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x0d,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd8,0x01,0xff,0x00,0x00]
+
+ds_min_u32 v1, v2
+// CHECK: [0x00,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x0e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x0f,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_u32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd8,0x01,0xff,0x00,0x00]
+
+ds_max_u32 v1, v2
+// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x10,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x11,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd8,0xff,0x02,0x00,0x00]
+
+ds_and_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd8,0x01,0xff,0x00,0x00]
+
+ds_and_b32 v1, v2
+// CHECK: [0x00,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x12,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x13,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd8,0xff,0x02,0x00,0x00]
+
+ds_or_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd8,0x01,0xff,0x00,0x00]
+
+ds_or_b32 v1, v2
+// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x14,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x15,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd8,0xff,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd8,0x01,0xff,0x00,0x00]
+
+ds_xor_b32 v1, v2
+// CHECK: [0x00,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x16,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x17,0xd8,0x01,0x02,0x00,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0xff,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0x01,0xff,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x18,0xd8,0x01,0x02,0xff,0x00]
+
+ds_mskor_b32 v1, v2, v3
+// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x18,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b32 v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x19,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write_b32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b32 v1, v2
+// CHECK: [0x00,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x1a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x1b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1c,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0xff,0x03,0x00]
+
+ds_write2_b32 v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1c,0xd8,0x01,0x02,0xff,0x00]
+
+ds_write2_b32 v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x1c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b32 v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x1d,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1e,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0xff,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x1e,0xd8,0x01,0x02,0xff,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x1e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b32 v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x1f,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0x01,0xff,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x20,0xd8,0x01,0x02,0xff,0x00]
+
+ds_cmpst_b32 v1, v2, v3
+// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x20,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b32 v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x21,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x22,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x22,0xd8,0x01,0xff,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x22,0xd8,0x01,0x02,0xff,0x00]
+
+ds_cmpst_f32 v1, v2, v3
+// CHECK: [0x00,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x22,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f32 v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x23,0xd8,0x01,0x02,0x03,0x00]
+
+ds_min_f32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_f32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd8,0x01,0xff,0x00,0x00]
+
+ds_min_f32 v1, v2
+// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x24,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x25,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_f32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd8,0x01,0xff,0x00,0x00]
+
+ds_max_f32 v1, v2
+// CHECK: [0x00,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x26,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x27,0xd8,0x01,0x02,0x00,0x00]
+
+ds_nop
+// CHECK: [0x00,0x00,0x28,0xd8,0x00,0x00,0x00,0x00]
+
+ds_add_f32 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_f32 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_add_f32 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd8,0x01,0xff,0x00,0x00]
+
+ds_add_f32 v1, v2
+// CHECK: [0x00,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_f32 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_f32 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x2a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_f32 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x2b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_addtid_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x3a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_addtid_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x3a,0xd8,0x00,0xff,0x00,0x00]
+
+ds_write_addtid_b32 v1
+// CHECK: [0x00,0x00,0x3a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_addtid_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x3a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_addtid_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x3a,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_addtid_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x3b,0xd8,0x00,0x01,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x3c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x3c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b8 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x3c,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b8 v1, v2
+// CHECK: [0x00,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x3c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x3d,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x3e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x3e,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b16 v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x3e,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b16 v1, v2
+// CHECK: [0x00,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:0
+// CHECK: [0x00,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:4
+// CHECK: [0x04,0x00,0x3e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16 v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x3f,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0x01,0x02,0x00,0xff]
+
+ds_add_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0xff,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x40,0xd8,0x01,0xff,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x40,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x41,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x42,0xd8,0x01,0x02,0x00,0xff]
+
+ds_sub_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x42,0xd8,0xff,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x42,0xd8,0x01,0xff,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x42,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x43,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0x01,0x02,0x00,0xff]
+
+ds_rsub_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0xff,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x44,0xd8,0x01,0xff,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x44,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x45,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x46,0xd8,0x01,0x02,0x00,0xff]
+
+ds_inc_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x46,0xd8,0xff,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x46,0xd8,0x01,0xff,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x46,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x47,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0x01,0x02,0x00,0xff]
+
+ds_dec_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0xff,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x48,0xd8,0x01,0xff,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x48,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x49,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_i32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x4a,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x4a,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2
+// CHECK: [0x00,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x4a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x4b,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_i32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x4c,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2
+// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x4c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x4d,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x4e,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x4e,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x4e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x4f,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x50,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x50,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_u32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x50,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x50,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2
+// CHECK: [0x00,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x50,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x51,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x52,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x52,0xd8,0x01,0x02,0x00,0xff]
+
+ds_and_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x52,0xd8,0xff,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x52,0xd8,0x01,0xff,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x52,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x53,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x54,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x54,0xd8,0x01,0x02,0x00,0xff]
+
+ds_or_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x54,0xd8,0xff,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x54,0xd8,0x01,0xff,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x54,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x55,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x56,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x56,0xd8,0x01,0x02,0x00,0xff]
+
+ds_xor_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x56,0xd8,0xff,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x56,0xd8,0x01,0xff,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x56,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x57,0xd8,0x01,0x02,0x00,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0x03,0xff]
+
+ds_mskor_rtn_b32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0xff,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0x01,0xff,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x58,0xd8,0x01,0x02,0xff,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x58,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x59,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0x02,0x00,0xff]
+
+ds_wrxchg_rtn_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x5a,0xd8,0xff,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x5a,0xd8,0x01,0xff,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x5a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x5b,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_wrxchg2_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5c,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x5c,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x5d,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v255, v2, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v255, v3 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x5e,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset1:255
+// CHECK: [0x00,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127
+// CHECK: [0x7f,0x00,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x5e,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b32 v[5:6], v1, v2, v3 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x5f,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0x03,0xff]
+
+ds_cmpst_rtn_b32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0x01,0xff,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x60,0xd8,0x01,0x02,0xff,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x60,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x61,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0x03,0xff]
+
+ds_cmpst_rtn_f32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0x01,0xff,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x62,0xd8,0x01,0x02,0xff,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x62,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x63,0xd8,0x01,0x02,0x03,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x64,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x64,0xd8,0x01,0x02,0x00,0xff]
+
+ds_min_rtn_f32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x64,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x64,0xd8,0x01,0xff,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2
+// CHECK: [0x00,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x64,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x65,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x66,0xd8,0x01,0x02,0x00,0xff]
+
+ds_max_rtn_f32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x66,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x66,0xd8,0x01,0xff,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2
+// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x66,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x67,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v255, v1, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0x03,0xff]
+
+ds_wrap_rtn_b32 v5, v255, v2, v3 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v255, v3 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0x01,0xff,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v255 offset:65535
+// CHECK: [0xff,0xff,0x68,0xd8,0x01,0x02,0xff,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3
+// CHECK: [0x00,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:0
+// CHECK: [0x00,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:4
+// CHECK: [0x04,0x00,0x68,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrap_rtn_b32 v5, v1, v2, v3 offset:65535 gds
+// CHECK: [0xff,0xff,0x69,0xd8,0x01,0x02,0x03,0x05]
+
+ds_add_rtn_f32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0x02,0x00,0xff]
+
+ds_add_rtn_f32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x6a,0xd8,0xff,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x6a,0xd8,0x01,0xff,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v2
+// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x6a,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_f32 v5, v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0x6b,0xd8,0x01,0x02,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x6c,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x6c,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_b32 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x6c,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1
+// CHECK: [0x00,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x6c,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b32 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x6d,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x6e,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read2_b32 v[5:6], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x6e,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset1:255
+// CHECK: [0x00,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127
+// CHECK: [0x7f,0x00,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x6e,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b32 v[5:6], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x6f,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x70,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read2st64_b32 v[5:6], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x70,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset1:255
+// CHECK: [0x00,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127
+// CHECK: [0x7f,0x00,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x70,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b32 v[5:6], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x71,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x72,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x72,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i8 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x72,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1
+// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x72,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x73,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x74,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x74,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u8 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x74,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1
+// CHECK: [0x00,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x74,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x75,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x76,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i16 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x76,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1
+// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x76,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i16 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x77,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x78,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u16 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x78,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1
+// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x78,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x79,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd8,0x01,0x00,0x00,0xff]
+
+ds_swizzle_b32 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd8,0xff,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1
+// CHECK: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:0
+// CHECK: [0x00,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:4
+// CHECK: [0x04,0x00,0x7a,0xd8,0x01,0x00,0x00,0x05]
+
+ds_swizzle_b32 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x7b,0xd8,0x01,0x00,0x00,0x05]
+
+ds_permute_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_permute_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0x02,0x00,0xff]
+
+ds_permute_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0xff,0x02,0x00,0x05]
+
+ds_permute_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd8,0x01,0xff,0x00,0x05]
+
+ds_permute_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_permute_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_permute_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x7c,0xd8,0x01,0x02,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_bpermute_b32 v255, v1, v2 offset:65535
+// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0x02,0x00,0xff]
+
+ds_bpermute_b32 v5, v255, v2 offset:65535
+// CHECK: [0xff,0xff,0x7e,0xd8,0xff,0x02,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v255 offset:65535
+// CHECK: [0xff,0xff,0x7e,0xd8,0x01,0xff,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v2
+// CHECK: [0x00,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v2 offset:0
+// CHECK: [0x00,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_bpermute_b32 v5, v1, v2 offset:4
+// CHECK: [0x04,0x00,0x7e,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0xff,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x80,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_add_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x80,0xd8,0x01,0x02,0x00,0x00]
+
+ds_add_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x81,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x82,0xd8,0xff,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x82,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x82,0xd8,0x01,0x02,0x00,0x00]
+
+ds_sub_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x83,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0xff,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x84,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x84,0xd8,0x01,0x02,0x00,0x00]
+
+ds_rsub_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x85,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x86,0xd8,0xff,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x86,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x86,0xd8,0x01,0x02,0x00,0x00]
+
+ds_inc_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x87,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0xff,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x88,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x88,0xd8,0x01,0x02,0x00,0x00]
+
+ds_dec_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x89,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_min_i64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x8a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_i64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x8b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_max_i64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x8c,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_i64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x8d,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_min_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x8e,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x8f,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x90,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_max_u64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x90,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_u64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x91,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x92,0xd8,0xff,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x92,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_and_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x92,0xd8,0x01,0x02,0x00,0x00]
+
+ds_and_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x93,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0xff,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x94,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_or_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x94,0xd8,0x01,0x02,0x00,0x00]
+
+ds_or_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x95,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x96,0xd8,0xff,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x96,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x96,0xd8,0x01,0x02,0x00,0x00]
+
+ds_xor_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x97,0xd8,0x01,0x02,0x00,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0xff,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x98,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0x98,0xd8,0x01,0x02,0x03,0x00]
+
+ds_mskor_b64 v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0x99,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write_b64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_write_b64 v1, v[2:3]
+// CHECK: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0x9a,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0x9b,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9c,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9c,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x9c,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x9d,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9e,0xd8,0xff,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0x9e,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0x9e,0xd8,0x01,0x02,0x03,0x00]
+
+ds_write2st64_b64 v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0x9f,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa0,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xa0,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_b64 v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xa1,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa2,0xd8,0xff,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0xfe,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa2,0xd8,0x01,0x02,0xfe,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xa2,0xd8,0x01,0x02,0x03,0x00]
+
+ds_cmpst_f64 v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xa3,0xd8,0x01,0x02,0x03,0x00]
+
+ds_min_f64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0xff,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_min_f64 v1, v[2:3]
+// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xa4,0xd8,0x01,0x02,0x00,0x00]
+
+ds_min_f64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xa5,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd8,0xff,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd8,0x01,0xfe,0x00,0x00]
+
+ds_max_f64 v1, v[2:3]
+// CHECK: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xa6,0xd8,0x01,0x02,0x00,0x00]
+
+ds_max_f64 v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xa7,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v255, v2 offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v255 offset:65535
+// CHECK: [0xff,0xff,0xa8,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2
+// CHECK: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2 offset:0
+// CHECK: [0x00,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2 offset:4
+// CHECK: [0x04,0x00,0xa8,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b8_d16_hi v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0xa9,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2 offset:65535
+// CHECK: [0xff,0xff,0xaa,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v255, v2 offset:65535
+// CHECK: [0xff,0xff,0xaa,0xd8,0xff,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v255 offset:65535
+// CHECK: [0xff,0xff,0xaa,0xd8,0x01,0xff,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2
+// CHECK: [0x00,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2 offset:0
+// CHECK: [0x00,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2 offset:4
+// CHECK: [0x04,0x00,0xaa,0xd8,0x01,0x02,0x00,0x00]
+
+ds_write_b16_d16_hi v1, v2 offset:65535 gds
+// CHECK: [0xff,0xff,0xab,0xd8,0x01,0x02,0x00,0x00]
+
+ds_read_u8_d16 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xac,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xac,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u8_d16 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xac,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u8_d16 v5, v1
+// CHECK: [0x00,0x00,0xac,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16 v5, v1 offset:0
+// CHECK: [0x00,0x00,0xac,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16 v5, v1 offset:4
+// CHECK: [0x04,0x00,0xac,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xad,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xae,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xae,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u8_d16_hi v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xae,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1
+// CHECK: [0x00,0x00,0xae,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1 offset:0
+// CHECK: [0x00,0x00,0xae,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1 offset:4
+// CHECK: [0x04,0x00,0xae,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u8_d16_hi v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xaf,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i8_d16 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xb0,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1
+// CHECK: [0x00,0x00,0xb0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1 offset:0
+// CHECK: [0x00,0x00,0xb0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1 offset:4
+// CHECK: [0x04,0x00,0xb0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xb1,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xb2,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xb2,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_i8_d16_hi v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xb2,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1
+// CHECK: [0x00,0x00,0xb2,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1 offset:0
+// CHECK: [0x00,0x00,0xb2,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1 offset:4
+// CHECK: [0x04,0x00,0xb2,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_i8_d16_hi v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xb3,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u16_d16 v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xb4,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1
+// CHECK: [0x00,0x00,0xb4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1 offset:0
+// CHECK: [0x00,0x00,0xb4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1 offset:4
+// CHECK: [0x04,0x00,0xb4,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16 v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xb5,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1 offset:65535
+// CHECK: [0xff,0xff,0xb6,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v255, v1 offset:65535
+// CHECK: [0xff,0xff,0xb6,0xd8,0x01,0x00,0x00,0xff]
+
+ds_read_u16_d16_hi v5, v255 offset:65535
+// CHECK: [0xff,0xff,0xb6,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1
+// CHECK: [0x00,0x00,0xb6,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1 offset:0
+// CHECK: [0x00,0x00,0xb6,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1 offset:4
+// CHECK: [0x04,0x00,0xb6,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_u16_d16_hi v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xb7,0xd8,0x01,0x00,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_add_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0xff,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc0,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc1,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_sub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc2,0xd8,0xff,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc2,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_sub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc3,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_rsub_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0xff,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc4,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_rsub_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc5,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_inc_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc6,0xd8,0xff,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc6,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_inc_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc7,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_dec_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0xff,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xc8,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xc8,0xd8,0x01,0x02,0x00,0x05]
+
+ds_dec_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xc9,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xca,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_i64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xca,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xca,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xca,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xcb,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_i64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xcc,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xcc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_i64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xcd,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xce,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xce,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xce,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xce,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xcf,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_u64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd0,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xd0,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_u64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xd1,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_and_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd2,0xd8,0xff,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd2,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xd2,0xd8,0x01,0x02,0x00,0x05]
+
+ds_and_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xd3,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_or_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0xff,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd4,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xd4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_or_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xd5,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_xor_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xd6,0xd8,0xff,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd6,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xd6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_xor_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xd7,0xd8,0x01,0x02,0x00,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_mskor_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0xff,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xd8,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xd8,0xd8,0x01,0x02,0x03,0x05]
+
+ds_mskor_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xd9,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xda,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_wrxchg_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xda,0xd8,0xff,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xda,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xda,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xdb,0xd8,0x01,0x02,0x00,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0x03,0xfc]
+
+ds_wrxchg2_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xdc,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xdc,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xdd,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0x03,0xfc]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v255, v[2:3], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0xff,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[254:255], v[3:4] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[254:255] offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xde,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset1:255
+// CHECK: [0x00,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127
+// CHECK: [0x7f,0x00,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xde,0xd8,0x01,0x02,0x03,0x05]
+
+ds_wrxchg2st64_rtn_b64 v[5:8], v1, v[2:3], v[3:4] offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xdf,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_cmpst_rtn_b64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xe0,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xe0,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_b64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xe1,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[254:255], v1, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0x03,0xfe]
+
+ds_cmpst_rtn_f64 v[5:6], v255, v[2:3], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0xff,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[254:255], v[3:4] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0xfe,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xe2,0xd8,0x01,0x02,0xfe,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4]
+// CHECK: [0x00,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:0
+// CHECK: [0x00,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:4
+// CHECK: [0x04,0x00,0xe2,0xd8,0x01,0x02,0x03,0x05]
+
+ds_cmpst_rtn_f64 v[5:6], v1, v[2:3], v[3:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xe3,0xd8,0x01,0x02,0x03,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_min_rtn_f64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0xff,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xe4,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xe4,0xd8,0x01,0x02,0x00,0x05]
+
+ds_min_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xe5,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_max_rtn_f64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xe6,0xd8,0xff,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xe6,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xe6,0xd8,0x01,0x02,0x00,0x05]
+
+ds_max_rtn_f64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xe7,0xd8,0x01,0x02,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:65535
+// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[254:255], v1 offset:65535
+// CHECK: [0xff,0xff,0xec,0xd8,0x01,0x00,0x00,0xfe]
+
+ds_read_b64 v[5:6], v255 offset:65535
+// CHECK: [0xff,0xff,0xec,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1
+// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:0
+// CHECK: [0x00,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:4
+// CHECK: [0x04,0x00,0xec,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read_b64 v[5:6], v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xed,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xee,0xd8,0x01,0x00,0x00,0xfc]
+
+ds_read2_b64 v[5:8], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xee,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset1:255
+// CHECK: [0x00,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127
+// CHECK: [0x7f,0x00,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xee,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2_b64 v[5:8], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xef,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xf0,0xd8,0x01,0x00,0x00,0xfc]
+
+ds_read2st64_b64 v[5:8], v255 offset0:127 offset1:255
+// CHECK: [0x7f,0xff,0xf0,0xd8,0xff,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset1:255
+// CHECK: [0x00,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:0 offset1:255
+// CHECK: [0x00,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:16 offset1:255
+// CHECK: [0x10,0xff,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127
+// CHECK: [0x7f,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:0
+// CHECK: [0x7f,0x00,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:1
+// CHECK: [0x7f,0x01,0xf0,0xd8,0x01,0x00,0x00,0x05]
+
+ds_read2st64_b64 v[5:8], v1 offset0:127 offset1:255 gds
+// CHECK: [0x7f,0xff,0xf1,0xd8,0x01,0x00,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[254:255], v1, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0x02,0x00,0xfe]
+
+ds_condxchg32_rtn_b64 v[5:6], v255, v[2:3] offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd8,0xff,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[254:255] offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd8,0x01,0xfe,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:0
+// CHECK: [0x00,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:4
+// CHECK: [0x04,0x00,0xfc,0xd8,0x01,0x02,0x00,0x05]
+
+ds_condxchg32_rtn_b64 v[5:6], v1, v[2:3] offset:65535 gds
+// CHECK: [0xff,0xff,0xfd,0xd8,0x01,0x02,0x00,0x05]
+
+ds_add_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x00,0xd9,0xff,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1
+// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x00,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x01,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x02,0xd9,0xff,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1
+// CHECK: [0x00,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x02,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x03,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x04,0xd9,0xff,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1
+// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x04,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x05,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x06,0xd9,0xff,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1
+// CHECK: [0x00,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x06,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x07,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x08,0xd9,0xff,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1
+// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x08,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x09,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v255 offset:65535
+// CHECK: [0xff,0xff,0x0a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1
+// CHECK: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:0
+// CHECK: [0x00,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:4
+// CHECK: [0x04,0x00,0x0a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v255 offset:65535
+// CHECK: [0xff,0xff,0x0c,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1
+// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:0
+// CHECK: [0x00,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:4
+// CHECK: [0x04,0x00,0x0c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0d,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x0e,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1
+// CHECK: [0x00,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x0e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x0f,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v255 offset:65535
+// CHECK: [0xff,0xff,0x10,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1
+// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:0
+// CHECK: [0x00,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:4
+// CHECK: [0x04,0x00,0x10,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x11,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x12,0xd9,0xff,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1
+// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x12,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x13,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x14,0xd9,0xff,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1
+// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x14,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x15,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x16,0xd9,0xff,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1
+// CHECK: [0x00,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x16,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x17,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x1a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1
+// CHECK: [0x00,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:0
+// CHECK: [0x00,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:4
+// CHECK: [0x04,0x00,0x1a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x1b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v255 offset:65535
+// CHECK: [0xff,0xff,0x24,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1
+// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:0
+// CHECK: [0x00,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:4
+// CHECK: [0x04,0x00,0x24,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x25,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v255 offset:65535
+// CHECK: [0xff,0xff,0x26,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1
+// CHECK: [0x00,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:0
+// CHECK: [0x00,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:4
+// CHECK: [0x04,0x00,0x26,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x27,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v255 offset:65535
+// CHECK: [0xff,0xff,0x2a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1
+// CHECK: [0x00,0x00,0x2a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:0
+// CHECK: [0x00,0x00,0x2a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:4
+// CHECK: [0x04,0x00,0x2a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_f32 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x2b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:65535 gds
+// CHECK: [0xff,0xff,0x31,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all gds
+// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:0 gds
+// CHECK: [0x00,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_release_all offset:4 gds
+// CHECK: [0x04,0x00,0x31,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_init v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x33,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_init v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x33,0xd9,0xff,0x00,0x00,0x00]
+
+ds_gws_init v1 gds
+// CHECK: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_init v1 offset:0 gds
+// CHECK: [0x00,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_init v1 offset:4 gds
+// CHECK: [0x04,0x00,0x33,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:65535 gds
+// CHECK: [0xff,0xff,0x35,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v gds
+// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:0 gds
+// CHECK: [0x00,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_v offset:4 gds
+// CHECK: [0x04,0x00,0x35,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x37,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_br v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x37,0xd9,0xff,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 gds
+// CHECK: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 offset:0 gds
+// CHECK: [0x00,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_br v1 offset:4 gds
+// CHECK: [0x04,0x00,0x37,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:65535 gds
+// CHECK: [0xff,0xff,0x39,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p gds
+// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:0 gds
+// CHECK: [0x00,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_sema_p offset:4 gds
+// CHECK: [0x04,0x00,0x39,0xd9,0x00,0x00,0x00,0x00]
+
+ds_gws_barrier v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x3b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_barrier v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x3b,0xd9,0xff,0x00,0x00,0x00]
+
+ds_gws_barrier v1 gds
+// CHECK: [0x00,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_barrier v1 offset:0 gds
+// CHECK: [0x00,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_gws_barrier v1 offset:4 gds
+// CHECK: [0x04,0x00,0x3b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_read_addtid_b32 v5 offset:65535
+// CHECK: [0xff,0xff,0x6c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_read_addtid_b32 v255 offset:65535
+// CHECK: [0xff,0xff,0x6c,0xd9,0x00,0x00,0x00,0xff]
+
+ds_read_addtid_b32 v5
+// CHECK: [0x00,0x00,0x6c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_read_addtid_b32 v5 offset:0
+// CHECK: [0x00,0x00,0x6c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_read_addtid_b32 v5 offset:4
+// CHECK: [0x04,0x00,0x6c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_read_addtid_b32 v5 offset:65535 gds
+// CHECK: [0xff,0xff,0x6d,0xd9,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0x05]
+
+ds_consume v255 offset:65535
+// CHECK: [0xff,0xff,0x7a,0xd9,0x00,0x00,0x00,0xff]
+
+ds_consume v5
+// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:0
+// CHECK: [0x00,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:4
+// CHECK: [0x04,0x00,0x7a,0xd9,0x00,0x00,0x00,0x05]
+
+ds_consume v5 offset:65535 gds
+// CHECK: [0xff,0xff,0x7b,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v255 offset:65535
+// CHECK: [0xff,0xff,0x7c,0xd9,0x00,0x00,0x00,0xff]
+
+ds_append v5
+// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:0
+// CHECK: [0x00,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:4
+// CHECK: [0x04,0x00,0x7c,0xd9,0x00,0x00,0x00,0x05]
+
+ds_append v5 offset:65535 gds
+// CHECK: [0xff,0xff,0x7d,0xd9,0x00,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x7f,0xd9,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v255, v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x7f,0xd9,0x01,0x00,0x00,0xff]
+
+ds_ordered_count v5, v255 offset:65535 gds
+// CHECK: [0xff,0xff,0x7f,0xd9,0xff,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 gds
+// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:0 gds
+// CHECK: [0x00,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
+
+ds_ordered_count v5, v1 offset:4 gds
+// CHECK: [0x04,0x00,0x7f,0xd9,0x01,0x00,0x00,0x05]
+
+ds_add_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x80,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x80,0xd9,0xff,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1
+// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x80,0xd9,0x01,0x00,0x00,0x00]
+
+ds_add_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x81,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x82,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x82,0xd9,0xff,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1
+// CHECK: [0x00,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x82,0xd9,0x01,0x00,0x00,0x00]
+
+ds_sub_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x83,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x84,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x84,0xd9,0xff,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1
+// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x84,0xd9,0x01,0x00,0x00,0x00]
+
+ds_rsub_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x85,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x86,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x86,0xd9,0xff,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1
+// CHECK: [0x00,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x86,0xd9,0x01,0x00,0x00,0x00]
+
+ds_inc_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x87,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x88,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x88,0xd9,0xff,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1
+// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x88,0xd9,0x01,0x00,0x00,0x00]
+
+ds_dec_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x89,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v255 offset:65535
+// CHECK: [0xff,0xff,0x8a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1
+// CHECK: [0x00,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:0
+// CHECK: [0x00,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:4
+// CHECK: [0x04,0x00,0x8a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_i64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x8b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v255 offset:65535
+// CHECK: [0xff,0xff,0x8c,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1
+// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:0
+// CHECK: [0x00,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:4
+// CHECK: [0x04,0x00,0x8c,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_i64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x8d,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x8e,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1
+// CHECK: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x8e,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x8f,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:65535
+// CHECK: [0xff,0xff,0x90,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v255 offset:65535
+// CHECK: [0xff,0xff,0x90,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1
+// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:0
+// CHECK: [0x00,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:4
+// CHECK: [0x04,0x00,0x90,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_u64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x91,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x92,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x92,0xd9,0xff,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1
+// CHECK: [0x00,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x92,0xd9,0x01,0x00,0x00,0x00]
+
+ds_and_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x93,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x94,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x94,0xd9,0xff,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1
+// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x94,0xd9,0x01,0x00,0x00,0x00]
+
+ds_or_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x95,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x96,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x96,0xd9,0xff,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1
+// CHECK: [0x00,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x96,0xd9,0x01,0x00,0x00,0x00]
+
+ds_xor_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x97,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v255 offset:65535
+// CHECK: [0xff,0xff,0x9a,0xd9,0xff,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1
+// CHECK: [0x00,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:0
+// CHECK: [0x00,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:4
+// CHECK: [0x04,0x00,0x9a,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_src2_b64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0x9b,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v255 offset:65535
+// CHECK: [0xff,0xff,0xa4,0xd9,0xff,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1
+// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:0
+// CHECK: [0x00,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:4
+// CHECK: [0x04,0x00,0xa4,0xd9,0x01,0x00,0x00,0x00]
+
+ds_min_src2_f64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xa5,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v255 offset:65535
+// CHECK: [0xff,0xff,0xa6,0xd9,0xff,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1
+// CHECK: [0x00,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:0
+// CHECK: [0x00,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:4
+// CHECK: [0x04,0x00,0xa6,0xd9,0x01,0x00,0x00,0x00]
+
+ds_max_src2_f64 v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xa7,0xd9,0x01,0x00,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:65535
+// CHECK: [0xff,0xff,0xbc,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v255, v[2:4] offset:65535
+// CHECK: [0xff,0xff,0xbc,0xd9,0xff,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[253:255] offset:65535
+// CHECK: [0xff,0xff,0xbc,0xd9,0x01,0xfd,0x00,0x00]
+
+ds_write_b96 v1, v[2:4]
+// CHECK: [0x00,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:0
+// CHECK: [0x00,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:4
+// CHECK: [0x04,0x00,0xbc,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b96 v1, v[2:4] offset:65535 gds
+// CHECK: [0xff,0xff,0xbd,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:65535
+// CHECK: [0xff,0xff,0xbe,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v255, v[2:5] offset:65535
+// CHECK: [0xff,0xff,0xbe,0xd9,0xff,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[252:255] offset:65535
+// CHECK: [0xff,0xff,0xbe,0xd9,0x01,0xfc,0x00,0x00]
+
+ds_write_b128 v1, v[2:5]
+// CHECK: [0x00,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:0
+// CHECK: [0x00,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:4
+// CHECK: [0x04,0x00,0xbe,0xd9,0x01,0x02,0x00,0x00]
+
+ds_write_b128 v1, v[2:5] offset:65535 gds
+// CHECK: [0xff,0xff,0xbf,0xd9,0x01,0x02,0x00,0x00]
+
+ds_read_b96 v[5:7], v1 offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[253:255], v1 offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd9,0x01,0x00,0x00,0xfd]
+
+ds_read_b96 v[5:7], v255 offset:65535
+// CHECK: [0xff,0xff,0xfc,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1
+// CHECK: [0x00,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:0
+// CHECK: [0x00,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:4
+// CHECK: [0x04,0x00,0xfc,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b96 v[5:7], v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xfd,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:65535
+// CHECK: [0xff,0xff,0xfe,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[252:255], v1 offset:65535
+// CHECK: [0xff,0xff,0xfe,0xd9,0x01,0x00,0x00,0xfc]
+
+ds_read_b128 v[5:8], v255 offset:65535
+// CHECK: [0xff,0xff,0xfe,0xd9,0xff,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1
+// CHECK: [0x00,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:0
+// CHECK: [0x00,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:4
+// CHECK: [0x04,0x00,0xfe,0xd9,0x01,0x00,0x00,0x05]
+
+ds_read_b128 v[5:8], v1 offset:65535 gds
+// CHECK: [0xff,0xff,0xff,0xd9,0x01,0x00,0x00,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_exp.s b/llvm/test/MC/AMDGPU/gfx9_asm_exp.s
new file mode 100644
index 0000000000000..689a19ff46292
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_exp.s
@@ -0,0 +1,82 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+exp mrt0 v0, v0, v0, v0
+// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrtz v0, v0, v0, v0
+// CHECK: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp null v0, v0, v0, v0
+// CHECK: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp pos0 v0, v0, v0, v0
+// CHECK: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp param0 v0, v0, v0, v0
+// CHECK: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v255, v0, v0, v0
+// CHECK: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00]
+
+exp mrt0 v0, v255, v0, v0
+// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00]
+
+exp mrt0 v0, v0, v255, v0
+// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00]
+
+exp mrt0 v0, v0, v0, v255
+// CHECK: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff]
+
+exp mrt0 v0, off, off, off
+// CHECK: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, off, off
+// CHECK: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, off, off
+// CHECK: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, v0, off
+// CHECK: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, off, v0, off
+// CHECK: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, v0, off
+// CHECK: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, off
+// CHECK: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, off, v0
+// CHECK: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, off, off, v0
+// CHECK: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, off, v0
+// CHECK: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, off, v0
+// CHECK: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, v0, v0
+// CHECK: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, off, v0, v0
+// CHECK: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, v0, v0, v0
+// CHECK: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 off, off, off, off
+// CHECK: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, v0 done
+// CHECK: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, v0 compr
+// CHECK: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00]
+
+exp mrt0 v0, v0, v0, v0 vm
+// CHECK: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_flat.s b/llvm/test/MC/AMDGPU/gfx9_asm_flat.s
new file mode 100644
index 0000000000000..7612308d6930a
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_flat.s
@@ -0,0 +1,4303 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+flat_load_ubyte v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x40,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_ubyte v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x40,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_ubyte v5, v[1:2]
+// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x40,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x41,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x42,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x44,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x44,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_sbyte v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x44,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2]
+// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x44,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x44,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x45,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x46,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x48,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x48,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_ushort v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x48,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2]
+// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x48,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x48,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x49,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ushort v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x4a,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_sshort v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2]
+// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x4c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x4c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x4d,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sshort v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x4e,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x50,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x50,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_dword v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x50,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2]
+// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x50,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x50,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x51,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dword v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x52,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x54,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[254:255], v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x54,0xdc,0x01,0x00,0x00,0xfe]
+
+flat_load_dwordx2 v[5:6], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x54,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2]
+// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2] offset:0
+// CHECK: [0x00,0x00,0x54,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2] offset:7
+// CHECK: [0x07,0x00,0x54,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x55,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx2 v[5:6], v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x56,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x58,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[253:255], v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x58,0xdc,0x01,0x00,0x00,0xfd]
+
+flat_load_dwordx3 v[5:7], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x58,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2]
+// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2] offset:0
+// CHECK: [0x00,0x00,0x58,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2] offset:7
+// CHECK: [0x07,0x00,0x58,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x59,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx3 v[5:7], v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x5a,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[252:255], v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xdc,0x01,0x00,0x00,0xfc]
+
+flat_load_dwordx4 v[5:8], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2]
+// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2] offset:0
+// CHECK: [0x00,0x00,0x5c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2] offset:7
+// CHECK: [0x07,0x00,0x5c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x5d,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_dwordx4 v[5:8], v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x5e,0xdc,0x01,0x00,0x00,0x05]
+
+flat_store_byte v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_byte v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_byte v[1:2], v2
+// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x60,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x61,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x62,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte_d16_hi v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte_d16_hi v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_byte_d16_hi v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_byte_d16_hi v[1:2], v2
+// CHECK: [0x00,0x00,0x64,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte_d16_hi v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x64,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte_d16_hi v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x64,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte_d16_hi v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x65,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_byte_d16_hi v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x66,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_short v[1:2], v2
+// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x68,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x69,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x6a,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short_d16_hi v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short_d16_hi v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_short_d16_hi v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_short_d16_hi v[1:2], v2
+// CHECK: [0x00,0x00,0x6c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short_d16_hi v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x6c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short_d16_hi v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x6c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short_d16_hi v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x6d,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_short_d16_hi v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x6e,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xdc,0x01,0xff,0x00,0x00]
+
+flat_store_dword v[1:2], v2
+// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x70,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x71,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dword v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x72,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x74,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x74,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x74,0xdc,0x01,0xfe,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0x74,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0x75,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0x76,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4] offset:4095
+// CHECK: [0xff,0x0f,0x78,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[254:255], v[2:4] offset:4095
+// CHECK: [0xff,0x0f,0x78,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[253:255] offset:4095
+// CHECK: [0xff,0x0f,0x78,0xdc,0x01,0xfd,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4]
+// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4] offset:0
+// CHECK: [0x00,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4] offset:7
+// CHECK: [0x07,0x00,0x78,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4] offset:4095 glc
+// CHECK: [0xff,0x0f,0x79,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx3 v[1:2], v[2:4] offset:4095 slc
+// CHECK: [0xff,0x0f,0x7a,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5] offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[254:255], v[2:5] offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xdc,0xfe,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[252:255] offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xdc,0x01,0xfc,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5]
+// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5] offset:0
+// CHECK: [0x00,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5] offset:7
+// CHECK: [0x07,0x00,0x7c,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5] offset:4095 glc
+// CHECK: [0xff,0x0f,0x7d,0xdc,0x01,0x02,0x00,0x00]
+
+flat_store_dwordx4 v[1:2], v[2:5] offset:4095 slc
+// CHECK: [0xff,0x0f,0x7e,0xdc,0x01,0x02,0x00,0x00]
+
+flat_load_ubyte_d16 v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x80,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16 v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x80,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_ubyte_d16 v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x80,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_ubyte_d16 v5, v[1:2]
+// CHECK: [0x00,0x00,0x80,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16 v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x80,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16 v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x80,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16 v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x81,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16 v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x82,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16_hi v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x84,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16_hi v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x84,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_ubyte_d16_hi v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x84,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_ubyte_d16_hi v5, v[1:2]
+// CHECK: [0x00,0x00,0x84,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16_hi v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x84,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16_hi v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x84,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16_hi v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x85,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_ubyte_d16_hi v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x86,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16 v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16 v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_sbyte_d16 v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_sbyte_d16 v5, v[1:2]
+// CHECK: [0x00,0x00,0x88,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16 v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x88,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16 v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x88,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16 v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x89,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16 v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x8a,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16_hi v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16_hi v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_sbyte_d16_hi v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_sbyte_d16_hi v5, v[1:2]
+// CHECK: [0x00,0x00,0x8c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16_hi v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x8c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16_hi v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x8c,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16_hi v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x8d,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_sbyte_d16_hi v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x8e,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16 v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x90,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16 v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x90,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_short_d16 v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x90,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_short_d16 v5, v[1:2]
+// CHECK: [0x00,0x00,0x90,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16 v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x90,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16 v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x90,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16 v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x91,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16 v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x92,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16_hi v5, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x94,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16_hi v255, v[1:2] offset:4095
+// CHECK: [0xff,0x0f,0x94,0xdc,0x01,0x00,0x00,0xff]
+
+flat_load_short_d16_hi v5, v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x94,0xdc,0xfe,0x00,0x00,0x05]
+
+flat_load_short_d16_hi v5, v[1:2]
+// CHECK: [0x00,0x00,0x94,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16_hi v5, v[1:2] offset:0
+// CHECK: [0x00,0x00,0x94,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16_hi v5, v[1:2] offset:7
+// CHECK: [0x07,0x00,0x94,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16_hi v5, v[1:2] offset:4095 glc
+// CHECK: [0xff,0x0f,0x95,0xdc,0x01,0x00,0x00,0x05]
+
+flat_load_short_d16_hi v5, v[1:2] offset:4095 slc
+// CHECK: [0xff,0x0f,0x96,0xdc,0x01,0x00,0x00,0x05]
+
+flat_atomic_swap v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_swap v[1:2], v2
+// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x00,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x01,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x02,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x04,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x04,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x04,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x04,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0x04,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0x04,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v0, v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0x05,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0x06,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_add v[1:2], v2
+// CHECK: [0x00,0x00,0x08,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x08,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x08,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x09,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_sub v[1:2], v2
+// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x0c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x0c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x0d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_smin v[1:2], v2
+// CHECK: [0x00,0x00,0x10,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x10,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x10,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x11,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x12,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_umin v[1:2], v2
+// CHECK: [0x00,0x00,0x14,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x14,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x14,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x15,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x16,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_smax v[1:2], v2
+// CHECK: [0x00,0x00,0x18,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x18,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x18,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x19,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_umax v[1:2], v2
+// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x1c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x1c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x1d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_and v[1:2], v2
+// CHECK: [0x00,0x00,0x20,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x20,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x20,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x21,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x22,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_or v[1:2], v2
+// CHECK: [0x00,0x00,0x24,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x24,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x24,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x25,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x26,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_xor v[1:2], v2
+// CHECK: [0x00,0x00,0x28,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x28,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x28,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x29,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_inc v[1:2], v2
+// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x2c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x2c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x2d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v2 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[254:255], v2 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v255 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xdd,0x01,0xff,0x00,0x00]
+
+flat_atomic_dec v[1:2], v2
+// CHECK: [0x00,0x00,0x30,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v2 offset:0
+// CHECK: [0x00,0x00,0x30,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v2 offset:7
+// CHECK: [0x07,0x00,0x30,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v0, v[1:2], v2 offset:4095 glc
+// CHECK: [0xff,0x0f,0x31,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec v[1:2], v2 offset:4095 slc
+// CHECK: [0xff,0x0f,0x32,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x80,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x80,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x80,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0x80,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0x81,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_swap_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0x82,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5] offset:4095
+// CHECK: [0xff,0x0f,0x84,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[254:255], v[2:5] offset:4095
+// CHECK: [0xff,0x0f,0x84,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[252:255] offset:4095
+// CHECK: [0xff,0x0f,0x84,0xdd,0x01,0xfc,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5]
+// CHECK: [0x00,0x00,0x84,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5] offset:0
+// CHECK: [0x00,0x00,0x84,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5] offset:7
+// CHECK: [0x07,0x00,0x84,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[0:1], v[1:2], v[2:5] offset:4095 glc
+// CHECK: [0xff,0x0f,0x85,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_cmpswap_x2 v[1:2], v[2:5] offset:4095 slc
+// CHECK: [0xff,0x0f,0x86,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x88,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0x88,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0x88,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0x89,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_add_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0x8a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0x8c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0x8c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0x8d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_sub_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0x8e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x90,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x90,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x90,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x90,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0x90,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0x90,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0x91,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smin_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0x92,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x94,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x94,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x94,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x94,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0x94,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0x94,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0x95,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umin_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0x96,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x98,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x98,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x98,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x98,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0x98,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0x98,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0x99,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_smax_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0x9a,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0x9c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0x9c,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0x9d,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_umax_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0x9e,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0xa0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0xa1,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_and_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0xa2,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa4,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0xa4,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0xa5,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_or_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0xa6,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0xa8,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0xa8,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0xa9,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_xor_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0xaa,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xac,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xac,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0xac,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xac,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0xac,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0xac,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0xad,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_inc_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0xae,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[254:255], v[2:3] offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xdd,0xfe,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[254:255] offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xdd,0x01,0xfe,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3]
+// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3] offset:0
+// CHECK: [0x00,0x00,0xb0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3] offset:7
+// CHECK: [0x07,0x00,0xb0,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[0:1], v[1:2], v[2:3] offset:4095 glc
+// CHECK: [0xff,0x0f,0xb1,0xdd,0x01,0x02,0x00,0x00]
+
+flat_atomic_dec_x2 v[1:2], v[2:3] offset:4095 slc
+// CHECK: [0xff,0x0f,0xb2,0xdd,0x01,0x02,0x00,0x00]
+
+global_load_ubyte v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_ubyte v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x40,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_ubyte v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_ubyte v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_ubyte v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_ubyte v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_ubyte v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_ubyte v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x40,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_ubyte v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x40,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x40,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x40,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x40,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x41,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x42,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_sbyte v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x44,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_sbyte v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_sbyte v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_sbyte v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_sbyte v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_sbyte v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_sbyte v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x44,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_sbyte v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x44,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x44,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x44,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x44,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x45,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x46,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ushort v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ushort v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_ushort v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x48,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_ushort v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_ushort v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_ushort v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_ushort v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_ushort v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_ushort v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x48,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_ushort v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x48,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ushort v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x48,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ushort v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x48,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ushort v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x48,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ushort v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x49,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ushort v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x4a,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sshort v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sshort v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_sshort v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x4c,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_sshort v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_sshort v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_sshort v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_sshort v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_sshort v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_sshort v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x4c,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_sshort v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x4c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sshort v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x4c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sshort v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x4c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sshort v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x4c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sshort v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x4d,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sshort v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x4e,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dword v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dword v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_dword v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x50,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_dword v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_dword v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_dword v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_dword v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_dword v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_dword v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x50,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_dword v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x50,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dword v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x50,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dword v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x50,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dword v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x50,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dword v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x51,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dword v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x52,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx2 v[5:6], v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx2 v[254:255], v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x04,0xfe]
+
+global_load_dwordx2 v[5:6], v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x54,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_dwordx2 v[5:6], v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_dwordx2 v[5:6], v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_dwordx2 v[5:6], v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_dwordx2 v[5:6], v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_dwordx2 v[5:6], v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_dwordx2 v[5:6], v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x54,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_dwordx2 v[5:6], v1, s[4:5]
+// CHECK: [0x00,0x80,0x54,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx2 v[5:6], v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x54,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx2 v[5:6], v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x54,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx2 v[5:6], v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x54,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx2 v[5:6], v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x55,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx2 v[5:6], v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x56,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx3 v[5:7], v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx3 v[253:255], v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x04,0xfd]
+
+global_load_dwordx3 v[5:7], v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x58,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_dwordx3 v[5:7], v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_dwordx3 v[5:7], v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_dwordx3 v[5:7], v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_dwordx3 v[5:7], v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_dwordx3 v[5:7], v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_dwordx3 v[5:7], v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x58,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_dwordx3 v[5:7], v1, s[4:5]
+// CHECK: [0x00,0x80,0x58,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx3 v[5:7], v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x58,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx3 v[5:7], v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x58,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx3 v[5:7], v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x58,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx3 v[5:7], v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x59,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx3 v[5:7], v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x5a,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx4 v[5:8], v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx4 v[252:255], v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x04,0xfc]
+
+global_load_dwordx4 v[5:8], v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x5c,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_dwordx4 v[5:8], v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_dwordx4 v[5:8], v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_dwordx4 v[5:8], v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_dwordx4 v[5:8], v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_dwordx4 v[5:8], v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_dwordx4 v[5:8], v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x5c,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_dwordx4 v[5:8], v1, s[4:5]
+// CHECK: [0x00,0x80,0x5c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx4 v[5:8], v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x5c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx4 v[5:8], v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x5c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx4 v[5:8], v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x5c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx4 v[5:8], v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x5d,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_dwordx4 v[5:8], v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x5e,0xdc,0x01,0x00,0x04,0x05]
+
+global_store_byte v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x60,0xdc,0xff,0x02,0x06,0x00]
+
+global_store_byte v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0xff,0x06,0x00]
+
+global_store_byte v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0x02,0x08,0x00]
+
+global_store_byte v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0x02,0x64,0x00]
+
+global_store_byte v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0x02,0x66,0x00]
+
+global_store_byte v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0x02,0x6a,0x00]
+
+global_store_byte v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0x02,0x7a,0x00]
+
+global_store_byte v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x60,0xdc,0x01,0x02,0x7f,0x00]
+
+global_store_byte v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x60,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x60,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x60,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x60,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x61,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x62,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte_d16_hi v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte_d16_hi v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x64,0xdc,0xff,0x02,0x06,0x00]
+
+global_store_byte_d16_hi v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0xff,0x06,0x00]
+
+global_store_byte_d16_hi v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0x02,0x08,0x00]
+
+global_store_byte_d16_hi v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0x02,0x64,0x00]
+
+global_store_byte_d16_hi v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0x02,0x66,0x00]
+
+global_store_byte_d16_hi v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0x02,0x6a,0x00]
+
+global_store_byte_d16_hi v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0x02,0x7a,0x00]
+
+global_store_byte_d16_hi v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x64,0xdc,0x01,0x02,0x7f,0x00]
+
+global_store_byte_d16_hi v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x64,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte_d16_hi v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x64,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte_d16_hi v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x64,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte_d16_hi v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x64,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte_d16_hi v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x65,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_byte_d16_hi v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x66,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x68,0xdc,0xff,0x02,0x06,0x00]
+
+global_store_short v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0xff,0x06,0x00]
+
+global_store_short v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0x02,0x08,0x00]
+
+global_store_short v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0x02,0x64,0x00]
+
+global_store_short v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0x02,0x66,0x00]
+
+global_store_short v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0x02,0x6a,0x00]
+
+global_store_short v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0x02,0x7a,0x00]
+
+global_store_short v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x68,0xdc,0x01,0x02,0x7f,0x00]
+
+global_store_short v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x68,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x68,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x68,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x68,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x69,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x6a,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short_d16_hi v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short_d16_hi v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x6c,0xdc,0xff,0x02,0x06,0x00]
+
+global_store_short_d16_hi v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0xff,0x06,0x00]
+
+global_store_short_d16_hi v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0x02,0x08,0x00]
+
+global_store_short_d16_hi v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0x02,0x64,0x00]
+
+global_store_short_d16_hi v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0x02,0x66,0x00]
+
+global_store_short_d16_hi v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0x02,0x6a,0x00]
+
+global_store_short_d16_hi v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0x02,0x7a,0x00]
+
+global_store_short_d16_hi v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x6c,0xdc,0x01,0x02,0x7f,0x00]
+
+global_store_short_d16_hi v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x6c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short_d16_hi v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x6c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short_d16_hi v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x6c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short_d16_hi v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x6c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short_d16_hi v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x6d,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_short_d16_hi v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x6e,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dword v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dword v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x70,0xdc,0xff,0x02,0x06,0x00]
+
+global_store_dword v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0xff,0x06,0x00]
+
+global_store_dword v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0x02,0x08,0x00]
+
+global_store_dword v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0x02,0x64,0x00]
+
+global_store_dword v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0x02,0x66,0x00]
+
+global_store_dword v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0x02,0x6a,0x00]
+
+global_store_dword v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0x02,0x7a,0x00]
+
+global_store_dword v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x70,0xdc,0x01,0x02,0x7f,0x00]
+
+global_store_dword v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x70,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dword v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x70,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dword v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x70,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dword v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x70,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dword v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x71,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dword v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x72,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x74,0xdc,0xff,0x02,0x06,0x00]
+
+global_store_dwordx2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0xfe,0x06,0x00]
+
+global_store_dwordx2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0x02,0x08,0x00]
+
+global_store_dwordx2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0x02,0x64,0x00]
+
+global_store_dwordx2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0x02,0x66,0x00]
+
+global_store_dwordx2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0x02,0x6a,0x00]
+
+global_store_dwordx2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0x02,0x7a,0x00]
+
+global_store_dwordx2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0x74,0xdc,0x01,0x02,0x7f,0x00]
+
+global_store_dwordx2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0x74,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x74,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x74,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x74,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx2 v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x75,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x76,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx3 v1, v[2:4], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx3 v255, v[2:4], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x78,0xdc,0xff,0x02,0x06,0x00]
+
+global_store_dwordx3 v1, v[253:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0xfd,0x06,0x00]
+
+global_store_dwordx3 v1, v[2:4], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0x02,0x08,0x00]
+
+global_store_dwordx3 v1, v[2:4], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0x02,0x64,0x00]
+
+global_store_dwordx3 v1, v[2:4], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0x02,0x66,0x00]
+
+global_store_dwordx3 v1, v[2:4], vcc offset:-1
+// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0x02,0x6a,0x00]
+
+global_store_dwordx3 v1, v[2:4], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0x02,0x7a,0x00]
+
+global_store_dwordx3 v[1:2], v[2:4], off offset:-1
+// CHECK: [0xff,0x9f,0x78,0xdc,0x01,0x02,0x7f,0x00]
+
+global_store_dwordx3 v1, v[2:4], s[6:7]
+// CHECK: [0x00,0x80,0x78,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx3 v1, v[2:4], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x78,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx3 v1, v[2:4], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x78,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx3 v1, v[2:4], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x78,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx3 v1, v[2:4], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x79,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx3 v1, v[2:4], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x7a,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx4 v1, v[2:5], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx4 v255, v[2:5], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x7c,0xdc,0xff,0x02,0x06,0x00]
+
+global_store_dwordx4 v1, v[252:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0xfc,0x06,0x00]
+
+global_store_dwordx4 v1, v[2:5], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0x02,0x08,0x00]
+
+global_store_dwordx4 v1, v[2:5], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0x02,0x64,0x00]
+
+global_store_dwordx4 v1, v[2:5], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0x02,0x66,0x00]
+
+global_store_dwordx4 v1, v[2:5], vcc offset:-1
+// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0x02,0x6a,0x00]
+
+global_store_dwordx4 v1, v[2:5], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0x02,0x7a,0x00]
+
+global_store_dwordx4 v[1:2], v[2:5], off offset:-1
+// CHECK: [0xff,0x9f,0x7c,0xdc,0x01,0x02,0x7f,0x00]
+
+global_store_dwordx4 v1, v[2:5], s[6:7]
+// CHECK: [0x00,0x80,0x7c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx4 v1, v[2:5], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x7c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx4 v1, v[2:5], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x7c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx4 v1, v[2:5], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x7c,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx4 v1, v[2:5], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x7d,0xdc,0x01,0x02,0x06,0x00]
+
+global_store_dwordx4 v1, v[2:5], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x7e,0xdc,0x01,0x02,0x06,0x00]
+
+global_load_ubyte_d16 v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16 v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_ubyte_d16 v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_ubyte_d16 v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_ubyte_d16 v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_ubyte_d16 v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_ubyte_d16 v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_ubyte_d16 v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_ubyte_d16 v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_ubyte_d16 v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x80,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16 v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x80,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16 v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x80,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16 v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x80,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16 v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x81,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16 v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x82,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16_hi v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16_hi v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_ubyte_d16_hi v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_ubyte_d16_hi v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_ubyte_d16_hi v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_ubyte_d16_hi v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_ubyte_d16_hi v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_ubyte_d16_hi v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_ubyte_d16_hi v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_ubyte_d16_hi v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x84,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16_hi v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x84,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16_hi v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x84,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16_hi v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x84,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16_hi v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x85,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_ubyte_d16_hi v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x86,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16 v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16 v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_sbyte_d16 v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_sbyte_d16 v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_sbyte_d16 v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_sbyte_d16 v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_sbyte_d16 v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_sbyte_d16 v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_sbyte_d16 v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_sbyte_d16 v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x88,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16 v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x88,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16 v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16 v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x88,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16 v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x89,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16 v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x8a,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16_hi v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16_hi v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_sbyte_d16_hi v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_sbyte_d16_hi v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_sbyte_d16_hi v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_sbyte_d16_hi v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_sbyte_d16_hi v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_sbyte_d16_hi v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_sbyte_d16_hi v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_sbyte_d16_hi v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x8c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16_hi v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x8c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16_hi v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16_hi v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x8c,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16_hi v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x8d,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_sbyte_d16_hi v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x8e,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16 v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16 v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_short_d16 v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_short_d16 v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_short_d16 v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_short_d16 v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_short_d16 v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_short_d16 v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_short_d16 v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_short_d16 v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x90,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16 v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x90,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16 v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x90,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16 v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x90,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16 v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x91,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16 v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x92,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16_hi v5, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16_hi v255, v1, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x04,0xff]
+
+global_load_short_d16_hi v5, v255, s[4:5] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdc,0xff,0x00,0x04,0x05]
+
+global_load_short_d16_hi v5, v1, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x06,0x05]
+
+global_load_short_d16_hi v5, v1, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x64,0x05]
+
+global_load_short_d16_hi v5, v1, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x66,0x05]
+
+global_load_short_d16_hi v5, v1, vcc offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x6a,0x05]
+
+global_load_short_d16_hi v5, v1, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x7a,0x05]
+
+global_load_short_d16_hi v5, v[1:2], off offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdc,0x01,0x00,0x7f,0x05]
+
+global_load_short_d16_hi v5, v1, s[4:5]
+// CHECK: [0x00,0x80,0x94,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16_hi v5, v1, s[4:5] offset:0
+// CHECK: [0x00,0x80,0x94,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16_hi v5, v1, s[4:5] offset:4095
+// CHECK: [0xff,0x8f,0x94,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16_hi v5, v1, s[4:5] offset:-4096
+// CHECK: [0x00,0x90,0x94,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16_hi v5, v1, s[4:5] offset:-1 glc
+// CHECK: [0xff,0x9f,0x95,0xdc,0x01,0x00,0x04,0x05]
+
+global_load_short_d16_hi v5, v1, s[4:5] offset:-1 slc
+// CHECK: [0xff,0x9f,0x96,0xdc,0x01,0x00,0x04,0x05]
+
+global_atomic_swap v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x00,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_swap v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_swap v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_swap v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_swap v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_swap v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_swap v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_swap v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x00,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_swap v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x00,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x00,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x00,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x00,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x01,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x02,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x04,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_cmpswap v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_cmpswap v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_cmpswap v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_cmpswap v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_cmpswap v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_cmpswap v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_cmpswap v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0x04,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_cmpswap v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0x04,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x04,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x04,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x04,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap v0, v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x05,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x06,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x08,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_add v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_add v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_add v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_add v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_add v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_add v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_add v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x08,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_add v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x08,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x08,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x08,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x09,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x0a,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x0c,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_sub v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_sub v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_sub v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_sub v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_sub v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_sub v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_sub v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x0c,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_sub v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x0c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x0c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x0c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x0d,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x0e,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x10,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_smin v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_smin v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_smin v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_smin v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_smin v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_smin v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_smin v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x10,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_smin v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x10,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x10,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x10,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x10,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x11,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x12,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x14,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_umin v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_umin v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_umin v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_umin v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_umin v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_umin v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_umin v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x14,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_umin v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x14,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x14,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x14,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x14,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x15,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x16,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x18,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_smax v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_smax v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_smax v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_smax v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_smax v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_smax v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_smax v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x18,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_smax v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x18,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x18,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x18,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x18,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x19,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x1a,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x1c,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_umax v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_umax v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_umax v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_umax v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_umax v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_umax v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_umax v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x1c,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_umax v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x1c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x1c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x1c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x1c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x1d,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x1e,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x20,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_and v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_and v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_and v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_and v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_and v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_and v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_and v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x20,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_and v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x20,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x20,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x20,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x20,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x21,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x22,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x24,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_or v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_or v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_or v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_or v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_or v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_or v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_or v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x24,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_or v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x24,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x24,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x24,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x24,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x25,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x26,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x28,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_xor v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_xor v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_xor v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_xor v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_xor v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_xor v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_xor v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x28,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_xor v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x28,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x28,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x28,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x28,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x29,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x2a,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x2c,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_inc v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_inc v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_inc v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_inc v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_inc v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_inc v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_inc v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x2c,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_inc v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x2c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x2c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x2c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x2c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x2d,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x2e,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec v1, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec v255, v2, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x30,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_dec v1, v255, s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0xff,0x06,0x00]
+
+global_atomic_dec v1, v2, s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_dec v1, v2, s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_dec v1, v2, flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_dec v1, v2, vcc offset:-1
+// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_dec v1, v2, ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_dec v[1:2], v2, off offset:-1
+// CHECK: [0xff,0x9f,0x30,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_dec v1, v2, s[6:7]
+// CHECK: [0x00,0x80,0x30,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec v1, v2, s[6:7] offset:0
+// CHECK: [0x00,0x80,0x30,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec v1, v2, s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x30,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec v1, v2, s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x30,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec v0, v1, v2, s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x31,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec v1, v2, s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x32,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_swap_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_swap_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0x80,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0x80,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x80,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x80,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x80,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x81,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_swap_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x82,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap_x2 v255, v[2:5], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_cmpswap_x2 v1, v[252:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0xfc,0x06,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], vcc offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_cmpswap_x2 v[1:2], v[2:5], off offset:-1
+// CHECK: [0xff,0x9f,0x84,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], s[6:7]
+// CHECK: [0x00,0x80,0x84,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x84,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x84,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x84,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap_x2 v[0:1], v1, v[2:5], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x85,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_cmpswap_x2 v1, v[2:5], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x86,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_add_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_add_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_add_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_add_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_add_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_add_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_add_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0x88,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_add_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0x88,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x88,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x88,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x89,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_add_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x8a,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_sub_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_sub_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0x8c,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0x8c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x8c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x8c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x8d,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_sub_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x8e,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_smin_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_smin_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0x90,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0x90,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x90,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x90,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x90,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x91,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smin_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x92,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_umin_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_umin_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0x94,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0x94,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x94,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x94,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x94,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x95,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umin_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x96,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x98,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_smax_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_smax_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0x98,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0x98,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x98,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x98,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x98,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x99,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_smax_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x9a,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x9c,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_umax_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_umax_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0x9c,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0x9c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0x9c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0x9c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0x9c,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0x9d,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_umax_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0x9e,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xa0,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_and_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_and_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_and_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_and_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_and_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_and_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_and_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0xa0,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_and_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0xa0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0xa0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0xa0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0xa0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0xa1,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_and_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0xa2,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xa4,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_or_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_or_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_or_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_or_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_or_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_or_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_or_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0xa4,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_or_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0xa4,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0xa4,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0xa4,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0xa4,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0xa5,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_or_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0xa6,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xa8,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_xor_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_xor_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0xa8,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0xa8,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0xa8,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0xa8,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0xa8,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0xa9,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_xor_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0xaa,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xac,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_inc_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_inc_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0xac,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0xac,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0xac,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0xac,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0xac,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0xad,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_inc_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0xae,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec_x2 v255, v[2:3], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xb0,0xdd,0xff,0x02,0x06,0x00]
+
+global_atomic_dec_x2 v1, v[254:255], s[6:7] offset:-1
+// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0xfe,0x06,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], s[8:9] offset:-1
+// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0x02,0x08,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], s[100:101] offset:-1
+// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0x02,0x64,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], flat_scratch offset:-1
+// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0x02,0x66,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], vcc offset:-1
+// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0x02,0x6a,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], ttmp[14:15] offset:-1
+// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0x02,0x7a,0x00]
+
+global_atomic_dec_x2 v[1:2], v[2:3], off offset:-1
+// CHECK: [0xff,0x9f,0xb0,0xdd,0x01,0x02,0x7f,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], s[6:7]
+// CHECK: [0x00,0x80,0xb0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], s[6:7] offset:0
+// CHECK: [0x00,0x80,0xb0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], s[6:7] offset:4095
+// CHECK: [0xff,0x8f,0xb0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], s[6:7] offset:-4096
+// CHECK: [0x00,0x90,0xb0,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec_x2 v[0:1], v1, v[2:3], s[6:7] offset:-1 glc
+// CHECK: [0xff,0x9f,0xb1,0xdd,0x01,0x02,0x06,0x00]
+
+global_atomic_dec_x2 v1, v[2:3], s[6:7] offset:-1 slc
+// CHECK: [0xff,0x9f,0xb2,0xdd,0x01,0x02,0x06,0x00]
+
+scratch_load_ubyte v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_ubyte v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_ubyte v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_ubyte v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_ubyte v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_ubyte v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_ubyte v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_ubyte v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x40,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_ubyte v5, off, s2
+// CHECK: [0x00,0x40,0x40,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x40,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x40,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x40,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x41,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x42,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_sbyte v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_sbyte v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_sbyte v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_sbyte v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_sbyte v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_sbyte v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_sbyte v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x44,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_sbyte v5, off, s2
+// CHECK: [0x00,0x40,0x44,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x44,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x44,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x44,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x45,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x46,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ushort v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ushort v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_ushort v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_ushort v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_ushort v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_ushort v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_ushort v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_ushort v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_ushort v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x48,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_ushort v5, off, s2
+// CHECK: [0x00,0x40,0x48,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ushort v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x48,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ushort v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x48,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ushort v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x48,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ushort v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x49,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ushort v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x4a,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sshort v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sshort v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_sshort v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_sshort v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_sshort v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_sshort v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_sshort v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_sshort v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_sshort v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x4c,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_sshort v5, off, s2
+// CHECK: [0x00,0x40,0x4c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sshort v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x4c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sshort v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x4c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sshort v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x4c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sshort v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x4d,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sshort v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x4e,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dword v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dword v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_dword v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_dword v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_dword v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_dword v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_dword v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_dword v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_dword v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x50,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_dword v5, off, s2
+// CHECK: [0x00,0x40,0x50,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dword v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x50,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dword v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x50,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dword v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x50,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dword v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x51,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dword v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x52,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx2 v[5:6], off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx2 v[254:255], off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x02,0xfe]
+
+scratch_load_dwordx2 v[5:6], off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_dwordx2 v[5:6], off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_dwordx2 v[5:6], off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_dwordx2 v[5:6], off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_dwordx2 v[5:6], off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_dwordx2 v[5:6], off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_dwordx2 v[5:6], v0, off offset:-1
+// CHECK: [0xff,0x5f,0x54,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_dwordx2 v[5:6], off, s2
+// CHECK: [0x00,0x40,0x54,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx2 v[5:6], off, s2 offset:0
+// CHECK: [0x00,0x40,0x54,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx2 v[5:6], off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x54,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx2 v[5:6], off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x54,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx2 v[5:6], off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x55,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx2 v[5:6], off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x56,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx3 v[5:7], off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx3 v[253:255], off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x02,0xfd]
+
+scratch_load_dwordx3 v[5:7], off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_dwordx3 v[5:7], off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_dwordx3 v[5:7], off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_dwordx3 v[5:7], off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_dwordx3 v[5:7], off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_dwordx3 v[5:7], off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_dwordx3 v[5:7], v0, off offset:-1
+// CHECK: [0xff,0x5f,0x58,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_dwordx3 v[5:7], off, s2
+// CHECK: [0x00,0x40,0x58,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx3 v[5:7], off, s2 offset:0
+// CHECK: [0x00,0x40,0x58,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx3 v[5:7], off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x58,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx3 v[5:7], off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x58,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx3 v[5:7], off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x59,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx3 v[5:7], off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x5a,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx4 v[5:8], off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx4 v[252:255], off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x02,0xfc]
+
+scratch_load_dwordx4 v[5:8], off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_dwordx4 v[5:8], off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_dwordx4 v[5:8], off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_dwordx4 v[5:8], off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_dwordx4 v[5:8], off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_dwordx4 v[5:8], off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_dwordx4 v[5:8], v0, off offset:-1
+// CHECK: [0xff,0x5f,0x5c,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_dwordx4 v[5:8], off, s2
+// CHECK: [0x00,0x40,0x5c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx4 v[5:8], off, s2 offset:0
+// CHECK: [0x00,0x40,0x5c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx4 v[5:8], off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x5c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx4 v[5:8], off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x5c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx4 v[5:8], off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x5d,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_dwordx4 v[5:8], off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x5e,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_store_byte off, v2, s3 offset:-1
+// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte off, v255, s3 offset:-1
+// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0xff,0x03,0x00]
+
+scratch_store_byte off, v2, s101 offset:-1
+// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x65,0x00]
+
+scratch_store_byte off, v2, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x66,0x00]
+
+scratch_store_byte off, v2, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x67,0x00]
+
+scratch_store_byte off, v2, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x6a,0x00]
+
+scratch_store_byte off, v2, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x6b,0x00]
+
+scratch_store_byte off, v2, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x7b,0x00]
+
+scratch_store_byte v0, v2, off offset:-1
+// CHECK: [0xff,0x5f,0x60,0xdc,0x00,0x02,0x7f,0x00]
+
+scratch_store_byte off, v2, s3
+// CHECK: [0x00,0x40,0x60,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte off, v2, s3 offset:0
+// CHECK: [0x00,0x40,0x60,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte off, v2, s3 offset:4095
+// CHECK: [0xff,0x4f,0x60,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte off, v2, s3 offset:-4096
+// CHECK: [0x00,0x50,0x60,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte off, v2, s3 offset:-1 glc
+// CHECK: [0xff,0x5f,0x61,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte off, v2, s3 offset:-1 slc
+// CHECK: [0xff,0x5f,0x62,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte_d16_hi off, v2, s3 offset:-1
+// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte_d16_hi off, v255, s3 offset:-1
+// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0xff,0x03,0x00]
+
+scratch_store_byte_d16_hi off, v2, s101 offset:-1
+// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x65,0x00]
+
+scratch_store_byte_d16_hi off, v2, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x66,0x00]
+
+scratch_store_byte_d16_hi off, v2, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x67,0x00]
+
+scratch_store_byte_d16_hi off, v2, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x6a,0x00]
+
+scratch_store_byte_d16_hi off, v2, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x6b,0x00]
+
+scratch_store_byte_d16_hi off, v2, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x7b,0x00]
+
+scratch_store_byte_d16_hi v0, v2, off offset:-1
+// CHECK: [0xff,0x5f,0x64,0xdc,0x00,0x02,0x7f,0x00]
+
+scratch_store_byte_d16_hi off, v2, s3
+// CHECK: [0x00,0x40,0x64,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte_d16_hi off, v2, s3 offset:0
+// CHECK: [0x00,0x40,0x64,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte_d16_hi off, v2, s3 offset:4095
+// CHECK: [0xff,0x4f,0x64,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte_d16_hi off, v2, s3 offset:-4096
+// CHECK: [0x00,0x50,0x64,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte_d16_hi off, v2, s3 offset:-1 glc
+// CHECK: [0xff,0x5f,0x65,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_byte_d16_hi off, v2, s3 offset:-1 slc
+// CHECK: [0xff,0x5f,0x66,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short off, v2, s3 offset:-1
+// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short off, v255, s3 offset:-1
+// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0xff,0x03,0x00]
+
+scratch_store_short off, v2, s101 offset:-1
+// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x65,0x00]
+
+scratch_store_short off, v2, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x66,0x00]
+
+scratch_store_short off, v2, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x67,0x00]
+
+scratch_store_short off, v2, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x6a,0x00]
+
+scratch_store_short off, v2, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x6b,0x00]
+
+scratch_store_short off, v2, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x7b,0x00]
+
+scratch_store_short v0, v2, off offset:-1
+// CHECK: [0xff,0x5f,0x68,0xdc,0x00,0x02,0x7f,0x00]
+
+scratch_store_short off, v2, s3
+// CHECK: [0x00,0x40,0x68,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short off, v2, s3 offset:0
+// CHECK: [0x00,0x40,0x68,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short off, v2, s3 offset:4095
+// CHECK: [0xff,0x4f,0x68,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short off, v2, s3 offset:-4096
+// CHECK: [0x00,0x50,0x68,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short off, v2, s3 offset:-1 glc
+// CHECK: [0xff,0x5f,0x69,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short off, v2, s3 offset:-1 slc
+// CHECK: [0xff,0x5f,0x6a,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short_d16_hi off, v2, s3 offset:-1
+// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short_d16_hi off, v255, s3 offset:-1
+// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0xff,0x03,0x00]
+
+scratch_store_short_d16_hi off, v2, s101 offset:-1
+// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x65,0x00]
+
+scratch_store_short_d16_hi off, v2, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x66,0x00]
+
+scratch_store_short_d16_hi off, v2, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x67,0x00]
+
+scratch_store_short_d16_hi off, v2, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x6a,0x00]
+
+scratch_store_short_d16_hi off, v2, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x6b,0x00]
+
+scratch_store_short_d16_hi off, v2, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x7b,0x00]
+
+scratch_store_short_d16_hi v0, v2, off offset:-1
+// CHECK: [0xff,0x5f,0x6c,0xdc,0x00,0x02,0x7f,0x00]
+
+scratch_store_short_d16_hi off, v2, s3
+// CHECK: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short_d16_hi off, v2, s3 offset:0
+// CHECK: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short_d16_hi off, v2, s3 offset:4095
+// CHECK: [0xff,0x4f,0x6c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short_d16_hi off, v2, s3 offset:-4096
+// CHECK: [0x00,0x50,0x6c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short_d16_hi off, v2, s3 offset:-1 glc
+// CHECK: [0xff,0x5f,0x6d,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_short_d16_hi off, v2, s3 offset:-1 slc
+// CHECK: [0xff,0x5f,0x6e,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dword off, v2, s3 offset:-1
+// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dword off, v255, s3 offset:-1
+// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0xff,0x03,0x00]
+
+scratch_store_dword off, v2, s101 offset:-1
+// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x65,0x00]
+
+scratch_store_dword off, v2, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x66,0x00]
+
+scratch_store_dword off, v2, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x67,0x00]
+
+scratch_store_dword off, v2, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x6a,0x00]
+
+scratch_store_dword off, v2, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x6b,0x00]
+
+scratch_store_dword off, v2, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x7b,0x00]
+
+scratch_store_dword v0, v2, off offset:-1
+// CHECK: [0xff,0x5f,0x70,0xdc,0x00,0x02,0x7f,0x00]
+
+scratch_store_dword off, v2, s3
+// CHECK: [0x00,0x40,0x70,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dword off, v2, s3 offset:0
+// CHECK: [0x00,0x40,0x70,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dword off, v2, s3 offset:4095
+// CHECK: [0xff,0x4f,0x70,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dword off, v2, s3 offset:-4096
+// CHECK: [0x00,0x50,0x70,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dword off, v2, s3 offset:-1 glc
+// CHECK: [0xff,0x5f,0x71,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dword off, v2, s3 offset:-1 slc
+// CHECK: [0xff,0x5f,0x72,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx2 off, v[2:3], s3 offset:-1
+// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx2 off, v[254:255], s3 offset:-1
+// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0xfe,0x03,0x00]
+
+scratch_store_dwordx2 off, v[2:3], s101 offset:-1
+// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x65,0x00]
+
+scratch_store_dwordx2 off, v[2:3], flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x66,0x00]
+
+scratch_store_dwordx2 off, v[2:3], flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x67,0x00]
+
+scratch_store_dwordx2 off, v[2:3], vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x6a,0x00]
+
+scratch_store_dwordx2 off, v[2:3], vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x6b,0x00]
+
+scratch_store_dwordx2 off, v[2:3], ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x7b,0x00]
+
+scratch_store_dwordx2 v0, v[2:3], off offset:-1
+// CHECK: [0xff,0x5f,0x74,0xdc,0x00,0x02,0x7f,0x00]
+
+scratch_store_dwordx2 off, v[2:3], s3
+// CHECK: [0x00,0x40,0x74,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx2 off, v[2:3], s3 offset:0
+// CHECK: [0x00,0x40,0x74,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx2 off, v[2:3], s3 offset:4095
+// CHECK: [0xff,0x4f,0x74,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx2 off, v[2:3], s3 offset:-4096
+// CHECK: [0x00,0x50,0x74,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx2 off, v[2:3], s3 offset:-1 glc
+// CHECK: [0xff,0x5f,0x75,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx2 off, v[2:3], s3 offset:-1 slc
+// CHECK: [0xff,0x5f,0x76,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx3 off, v[2:4], s3 offset:-1
+// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx3 off, v[253:255], s3 offset:-1
+// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0xfd,0x03,0x00]
+
+scratch_store_dwordx3 off, v[2:4], s101 offset:-1
+// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x65,0x00]
+
+scratch_store_dwordx3 off, v[2:4], flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x66,0x00]
+
+scratch_store_dwordx3 off, v[2:4], flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x67,0x00]
+
+scratch_store_dwordx3 off, v[2:4], vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x6a,0x00]
+
+scratch_store_dwordx3 off, v[2:4], vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x6b,0x00]
+
+scratch_store_dwordx3 off, v[2:4], ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x7b,0x00]
+
+scratch_store_dwordx3 v0, v[2:4], off offset:-1
+// CHECK: [0xff,0x5f,0x78,0xdc,0x00,0x02,0x7f,0x00]
+
+scratch_store_dwordx3 off, v[2:4], s3
+// CHECK: [0x00,0x40,0x78,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx3 off, v[2:4], s3 offset:0
+// CHECK: [0x00,0x40,0x78,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx3 off, v[2:4], s3 offset:4095
+// CHECK: [0xff,0x4f,0x78,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx3 off, v[2:4], s3 offset:-4096
+// CHECK: [0x00,0x50,0x78,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx3 off, v[2:4], s3 offset:-1 glc
+// CHECK: [0xff,0x5f,0x79,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx3 off, v[2:4], s3 offset:-1 slc
+// CHECK: [0xff,0x5f,0x7a,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx4 off, v[2:5], s3 offset:-1
+// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx4 off, v[252:255], s3 offset:-1
+// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0xfc,0x03,0x00]
+
+scratch_store_dwordx4 off, v[2:5], s101 offset:-1
+// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x65,0x00]
+
+scratch_store_dwordx4 off, v[2:5], flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x66,0x00]
+
+scratch_store_dwordx4 off, v[2:5], flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x67,0x00]
+
+scratch_store_dwordx4 off, v[2:5], vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x6a,0x00]
+
+scratch_store_dwordx4 off, v[2:5], vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x6b,0x00]
+
+scratch_store_dwordx4 off, v[2:5], ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x7b,0x00]
+
+scratch_store_dwordx4 v0, v[2:5], off offset:-1
+// CHECK: [0xff,0x5f,0x7c,0xdc,0x00,0x02,0x7f,0x00]
+
+scratch_store_dwordx4 off, v[2:5], s3
+// CHECK: [0x00,0x40,0x7c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx4 off, v[2:5], s3 offset:0
+// CHECK: [0x00,0x40,0x7c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx4 off, v[2:5], s3 offset:4095
+// CHECK: [0xff,0x4f,0x7c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx4 off, v[2:5], s3 offset:-4096
+// CHECK: [0x00,0x50,0x7c,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx4 off, v[2:5], s3 offset:-1 glc
+// CHECK: [0xff,0x5f,0x7d,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_store_dwordx4 off, v[2:5], s3 offset:-1 slc
+// CHECK: [0xff,0x5f,0x7e,0xdc,0x00,0x02,0x03,0x00]
+
+scratch_load_ubyte_d16 v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16 v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_ubyte_d16 v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_ubyte_d16 v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_ubyte_d16 v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_ubyte_d16 v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_ubyte_d16 v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_ubyte_d16 v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_ubyte_d16 v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x80,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_ubyte_d16 v5, off, s2
+// CHECK: [0x00,0x40,0x80,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16 v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x80,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16 v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x80,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16 v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x80,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16 v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x81,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16 v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x82,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16_hi v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_ubyte_d16_hi v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_ubyte_d16_hi v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x84,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, s2
+// CHECK: [0x00,0x40,0x84,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x84,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x84,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x84,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x85,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_ubyte_d16_hi v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x86,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16 v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16 v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_sbyte_d16 v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_sbyte_d16 v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_sbyte_d16 v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_sbyte_d16 v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_sbyte_d16 v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_sbyte_d16 v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_sbyte_d16 v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x88,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_sbyte_d16 v5, off, s2
+// CHECK: [0x00,0x40,0x88,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16 v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x88,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16 v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x88,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16 v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x88,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16 v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x89,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16 v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x8a,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16_hi v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_sbyte_d16_hi v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_sbyte_d16_hi v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x8c,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, s2
+// CHECK: [0x00,0x40,0x8c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x8c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x8c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x8c,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x8d,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_sbyte_d16_hi v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x8e,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16 v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16 v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_short_d16 v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_short_d16 v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_short_d16 v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_short_d16 v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_short_d16 v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_short_d16 v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_short_d16 v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x90,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_short_d16 v5, off, s2
+// CHECK: [0x00,0x40,0x90,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16 v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x90,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16 v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x90,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16 v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x90,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16 v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x91,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16 v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x92,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16_hi v5, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16_hi v255, off, s2 offset:-1
+// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x02,0xff]
+
+scratch_load_short_d16_hi v5, off, s101 offset:-1
+// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x65,0x05]
+
+scratch_load_short_d16_hi v5, off, flat_scratch_lo offset:-1
+// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x66,0x05]
+
+scratch_load_short_d16_hi v5, off, flat_scratch_hi offset:-1
+// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x67,0x05]
+
+scratch_load_short_d16_hi v5, off, vcc_lo offset:-1
+// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x6a,0x05]
+
+scratch_load_short_d16_hi v5, off, vcc_hi offset:-1
+// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x6b,0x05]
+
+scratch_load_short_d16_hi v5, off, ttmp15 offset:-1
+// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x7b,0x05]
+
+scratch_load_short_d16_hi v5, v0, off offset:-1
+// CHECK: [0xff,0x5f,0x94,0xdc,0x00,0x00,0x7f,0x05]
+
+scratch_load_short_d16_hi v5, off, s2
+// CHECK: [0x00,0x40,0x94,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16_hi v5, off, s2 offset:0
+// CHECK: [0x00,0x40,0x94,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16_hi v5, off, s2 offset:4095
+// CHECK: [0xff,0x4f,0x94,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16_hi v5, off, s2 offset:-4096
+// CHECK: [0x00,0x50,0x94,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16_hi v5, off, s2 offset:-1 glc
+// CHECK: [0xff,0x5f,0x95,0xdc,0x00,0x00,0x02,0x05]
+
+scratch_load_short_d16_hi v5, off, s2 offset:-1 slc
+// CHECK: [0xff,0x5f,0x96,0xdc,0x00,0x00,0x02,0x05]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx9_asm_mimg.s
new file mode 100644
index 0000000000000..bfda147ac34da
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_mimg.s
@@ -0,0 +1,7108 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+image_load v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x03,0x00]
+
+image_load v5, v1, s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x17,0x00]
+
+image_load v5, v1, ttmp[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x00,0xf2,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x01,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x02,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x00,0xf0,0x01,0x05,0x02,0x00]
+
+image_load v5, v1, s[8:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x00,0xf0,0x01,0x05,0x02,0x80]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v252, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_mip v5, v[252:253], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_mip v5, v[1:2], s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_mip v5, v[1:2], ttmp[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:7], v[1:2], s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:8], v[1:2], s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x04,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v1, s[8:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v[5:6], v[1:2], s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x05,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x06,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x04,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip v5, v[1:2], s[8:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x04,0xf0,0x01,0x05,0x02,0x80]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_pck v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_pck v5, v1, s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_pck v5, v1, ttmp[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x08,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x09,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x0a,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x08,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_pck_sgn v5, v252, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_pck_sgn v5, v1, s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_pck_sgn v5, v1, ttmp[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x0c,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x0d,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x0e,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_pck_sgn v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x0c,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v252, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_mip_pck v5, v[252:253], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_mip_pck v5, v[1:2], s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_mip_pck v5, v[1:2], ttmp[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:7], v[1:2], s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:8], v[1:2], s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x10,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v1, s[8:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v[5:6], v[1:2], s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x11,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x12,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x10,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v252, v[1:2], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0xfc,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[252:253], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0xfc,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x03,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x17,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], ttmp[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x1d,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:7], v[1:2], s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:8], v[1:2], s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:3], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:4], s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x14,0xf2,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v1, s[8:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v[5:6], v[1:2], s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x15,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x16,0xf0,0x01,0x05,0x02,0x00]
+
+image_load_mip_pck_sgn v5, v[1:2], s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x14,0xf0,0x01,0x05,0x02,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store v1, v252, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x04,0x00]
+
+image_store v1, v2, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x17,0x00]
+
+image_store v1, v2, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:2], v2, s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:3], v2, s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v[1:4], v2, s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x20,0xf2,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x22,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x20,0xf0,0x02,0x01,0x03,0x00]
+
+image_store v1, v2, s[12:19] dmask:0x1 unorm d16
+// CHECK: [0x00,0x11,0x20,0xf0,0x02,0x01,0x03,0x80]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v252, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_mip v1, v[252:253], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x04,0x00]
+
+image_store_mip v1, v[2:3], s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x17,0x00]
+
+image_store_mip v1, v[2:3], ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:2], v[2:3], s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:3], v[2:3], s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v[1:4], v[2:3], s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x24,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v2, s[12:19] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x26,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x24,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip v1, v[2:3], s[12:19] dmask:0x1 unorm d16
+// CHECK: [0x00,0x11,0x24,0xf0,0x02,0x01,0x03,0x80]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v252, v2, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_pck v1, v252, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x04,0x00]
+
+image_store_pck v1, v2, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x17,0x00]
+
+image_store_pck v1, v2, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:2], v2, s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:3], v2, s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v[1:4], v2, s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x28,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x2a,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_pck v1, v2, s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x28,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
+
+image_store_mip_pck v1, v[252:253], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0xfc,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[16:23] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x04,0x00]
+
+image_store_mip_pck v1, v[2:3], s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x17,0x00]
+
+image_store_mip_pck v1, v[2:3], ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x1d,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x2 unorm
+// CHECK: [0x00,0x12,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x4 unorm
+// CHECK: [0x00,0x14,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x5 unorm
+// CHECK: [0x00,0x15,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x6 unorm
+// CHECK: [0x00,0x16,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0x7 unorm
+// CHECK: [0x00,0x17,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x8 unorm
+// CHECK: [0x00,0x18,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0x9 unorm
+// CHECK: [0x00,0x19,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0xa unorm
+// CHECK: [0x00,0x1a,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0xb unorm
+// CHECK: [0x00,0x1b,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:2], v[2:3], s[12:19] dmask:0xc unorm
+// CHECK: [0x00,0x1c,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0xd unorm
+// CHECK: [0x00,0x1d,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:3], v[2:3], s[12:19] dmask:0xe unorm
+// CHECK: [0x00,0x1e,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v[1:4], v[2:3], s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x0 unorm
+// CHECK: [0x00,0x10,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:4], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:5], s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x2c,0xf2,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v2, s[12:19] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x2e,0xf0,0x02,0x01,0x03,0x00]
+
+image_store_mip_pck v1, v[2:3], s[12:19] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x2c,0xf0,0x02,0x01,0x03,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v252, v1, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0xfc,0x02,0x00]
+
+image_get_resinfo v5, v255, s[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0xff,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[12:19] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x03,0x00]
+
+image_get_resinfo v5, v1, s[92:99] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x17,0x00]
+
+image_get_resinfo v5, v1, ttmp[8:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf0,0x01,0x05,0x1d,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x2
+// CHECK: [0x00,0x02,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x3
+// CHECK: [0x00,0x03,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x4
+// CHECK: [0x00,0x04,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x5
+// CHECK: [0x00,0x05,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x6
+// CHECK: [0x00,0x06,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0x7
+// CHECK: [0x00,0x07,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x8
+// CHECK: [0x00,0x08,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x9
+// CHECK: [0x00,0x09,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:7], v1, s[8:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:8], v1, s[8:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x0
+// CHECK: [0x00,0x00,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x38,0xf2,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v[5:6], v1, s[8:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x39,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x3a,0xf0,0x01,0x05,0x02,0x00]
+
+image_get_resinfo v5, v1, s[8:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x38,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_swap v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_swap v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_swap v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_swap v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x40,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x42,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_swap v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x40,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[252:253], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v252, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[92:99] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_cmpswap v[5:6], v1, ttmp[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_cmpswap v[5:8], v1, s[8:15] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v[1:2], s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v[1:3], s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v[1:4], s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm glc
+// CHECK: [0x00,0x33,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm slc
+// CHECK: [0x00,0x13,0x44,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm a16
+// CHECK: [0x00,0x93,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm lwe
+// CHECK: [0x00,0x13,0x46,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_cmpswap v[5:6], v1, s[8:15] dmask:0x3 unorm da
+// CHECK: [0x00,0x53,0x44,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_add v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_add v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_add v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_add v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x48,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x4a,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_add v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x48,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_sub v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_sub v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_sub v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_sub v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x4c,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x4e,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_sub v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x4c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_smin v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_smin v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_smin v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_smin v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x50,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x52,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smin v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x50,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_umin v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_umin v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_umin v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_umin v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x54,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x56,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umin v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x54,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_smax v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_smax v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_smax v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_smax v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x58,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x5a,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_smax v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x58,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_umax v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_umax v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_umax v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_umax v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x5c,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x5e,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_umax v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x5c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_and v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_and v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_and v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_and v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x60,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x62,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_and v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x60,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_or v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_or v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_or v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_or v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x64,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x66,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_or v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x64,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_xor v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_xor v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_xor v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_xor v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x68,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x6a,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_xor v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x68,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_inc v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_inc v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_inc v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_inc v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x6c,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x6e,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_inc v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x6c,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v252, v1, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0xfc,0x02,0x00]
+
+image_atomic_dec v5, v252, s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0xfc,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[12:19] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x03,0x00]
+
+image_atomic_dec v5, v1, s[92:99] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x17,0x00]
+
+image_atomic_dec v5, v1, ttmp[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x1d,0x00]
+
+image_atomic_dec v[5:6], v1, s[8:15] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v[1:2], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v[1:3], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v[1:4], s[8:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm glc
+// CHECK: [0x00,0x31,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm slc
+// CHECK: [0x00,0x11,0x70,0xf2,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm a16
+// CHECK: [0x00,0x91,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm lwe
+// CHECK: [0x00,0x11,0x72,0xf0,0x01,0x05,0x02,0x00]
+
+image_atomic_dec v5, v1, s[8:15] dmask:0x1 unorm da
+// CHECK: [0x00,0x51,0x70,0xf0,0x01,0x05,0x02,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v252, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample v5, v253, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0xfd,0x05,0x62,0x00]
+
+image_sample v5, v1, s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample v5, v1, s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample v5, v1, ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample v5, v1, s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample v5, v1, s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample v5, v1, s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:7], v1, s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:8], v1, s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x80,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x81,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x82,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x80,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample v5, v1, s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x80,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_cl v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_cl v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_cl v5, v[1:2], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_cl v5, v[1:2], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x84,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v1, s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x85,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x86,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x84,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x84,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d v5, v[247:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0xf7,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_d v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_d v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x88,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x89,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x8a,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x88,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x88,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d_cl v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_d_cl v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_d_cl v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x8c,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x8d,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x8e,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x8c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x8c,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_l v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_l v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_l v5, v[1:2], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_l v5, v[1:2], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x90,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v1, s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x91,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x92,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x90,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x90,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_b v5, v[1:2], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_b v5, v[1:2], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x94,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x95,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x96,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x94,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x94,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b_cl v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b_cl v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_b_cl v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_b_cl v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x98,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x99,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x9a,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x98,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x98,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v252, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_lz v5, v253, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0xfd,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_lz v5, v1, s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_lz v5, v1, ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_lz v5, v1, s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:7], v1, s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:8], v1, s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x9c,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x9d,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x9e,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x9c,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz v5, v1, s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x9c,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c v5, v[1:2], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c v5, v[1:2], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cl v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_cl v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_cl v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_cl v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_d v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_d v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xaa,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d_cl v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_d_cl v5, v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xac,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xad,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xae,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xac,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xac,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_l v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_l v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_l v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_l v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_b v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_b v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b_cl v5, v[250:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0xfa,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_b_cl v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xba,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_lz v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_lz v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_lz v5, v[1:2], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_lz v5, v[1:2], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xbc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xbd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xbe,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xbc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xbc,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_o v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_o v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_o v5, v[1:2], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_o v5, v[1:2], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xc0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xc1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xc2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xc0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xc0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_cl_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_cl_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_cl_o v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_cl_o v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xc4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xc5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xc6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xc4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xc4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d_o v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0xf6,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_d_o v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_d_o v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xc8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xc9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xca,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xc8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xc8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_d_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_d_cl_o v5, v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xcc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xcd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xce,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xcc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xcc,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_l_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_l_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_l_o v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_l_o v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xd0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xd1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xd2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xd0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xd0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_b_o v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_b_o v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xd4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xd5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xd6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xd4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xd4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_b_cl_o v5, v[250:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0xfa,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_b_cl_o v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xd8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xd9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xda,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xd8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xd8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v252, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_lz_o v5, v[252:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0xfc,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_lz_o v5, v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_lz_o v5, v[1:2], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_lz_o v5, v[1:2], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:7], v[1:2], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xdc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xdd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xde,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xdc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_lz_o v5, v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xdc,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_o v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_o v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xe0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xe1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xe2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xe0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xe0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cl_o v5, v[250:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0xfa,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_cl_o v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xe4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xe5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xe6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xe4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xe4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0xf5,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_d_o v5, v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xe8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xe9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xea,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xe8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xe8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[244:251], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0xf4,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xec,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xed,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xee,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xec,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_d_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xec,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_l_o v5, v[250:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0xfa,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_l_o v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xf0,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xf1,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xf2,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xf0,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_l_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xf0,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b_o v5, v[250:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0xfa,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_b_o v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xf4,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xf5,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xf6,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xf4,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xf4,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xf8,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xf9,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xfa,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xf8,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_b_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xf8,0xf0,0x01,0x05,0x62,0x80]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0xfc,0x62,0x00]
+
+image_sample_c_lz_o v5, v[251:253], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0xfb,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x63,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x77,0x00]
+
+image_sample_c_lz_o v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x7d,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x82,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x02,0x03]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0xc2,0x03]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xfc,0xf2,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xfd,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xfe,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xfc,0xf0,0x01,0x05,0x62,0x00]
+
+image_sample_c_lz_o v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xfc,0xf0,0x01,0x05,0x62,0x80]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[252:255], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4 v[5:8], v[253:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0xfd,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4 v[5:8], v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4 v[5:8], v[1:2], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4 v[5:8], v[1:2], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x00,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v1, s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x02,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x00,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4 v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x00,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_cl v[5:8], v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0xfc,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_cl v[5:8], v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x04,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x06,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x04,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x04,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_l v[5:8], v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0xfc,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_l v[5:8], v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x10,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x12,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x10,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x10,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b v[5:8], v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0xfc,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_b v[5:8], v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x14,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x16,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x14,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x14,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0xfb,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x18,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x1a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x18,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x18,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[252:255], v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_lz v[5:8], v[253:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0xfd,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_lz v[5:8], v[1:2], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x1c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v1, s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x1e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x1c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz v[5:6], v[1:2], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x1c,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c v[5:8], v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0xfc,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c v[5:8], v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x20,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x22,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x20,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x20,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0xfb,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x24,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x26,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x24,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x24,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0xfb,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x30,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x32,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x30,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x30,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0xfb,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x34,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x36,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x34,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x34,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x38,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x3a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x38,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x38,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0xfc,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x3c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x3e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x3c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x3c,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_o v[5:8], v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0xfc,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_o v[5:8], v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x40,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x42,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x40,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x40,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0xfb,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x44,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x46,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x44,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_cl_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x44,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0xfb,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x50,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x52,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x50,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_l_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x50,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0xfb,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x54,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x56,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x54,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x54,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x58,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x5a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x58,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x58,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[252:255], v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[252:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0xfc,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x5c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:2], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x5e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x5c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_lz_o v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x5c,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0xfb,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x60,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x62,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x60,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x60,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x64,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x66,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x64,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x64,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x70,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x72,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x70,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_l_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x70,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x74,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x76,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x74,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x74,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[252:255], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x78,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x7a,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x78,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_b_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x78,0xf1,0x01,0x05,0x62,0x80]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[252:255], v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0xfc,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[251:254], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0xfb,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x63,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x77,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x7d,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x82,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x02,0x03]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0xc2,0x03]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x7c,0xf3,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x7e,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x7c,0xf1,0x01,0x05,0x62,0x00]
+
+image_gather4_c_lz_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0x7c,0xf1,0x01,0x05,0x62,0x80]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v252, v1, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0xfc,0x62,0x00]
+
+image_get_lod v5, v253, s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0xfd,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x63,0x00]
+
+image_get_lod v5, v1, s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x77,0x00]
+
+image_get_lod v5, v1, ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x7d,0x00]
+
+image_get_lod v5, v1, s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x82,0x00]
+
+image_get_lod v5, v1, s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x02,0x03]
+
+image_get_lod v5, v1, s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0xc2,0x03]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:7], v1, s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:8], v1, s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v[1:2], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0x80,0xf3,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v[5:6], v1, s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0x81,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0x82,0xf1,0x01,0x05,0x62,0x00]
+
+image_get_lod v5, v1, s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0x80,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v252, v[1:3], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd v5, v[247:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0xf7,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd v5, v[1:3], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_cd v5, v[1:3], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_cd v5, v[1:3], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:7], v[1:3], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:8], v[1:3], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa0,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v[5:6], v[1:3], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa1,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa2,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd v5, v[1:3], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa0,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd_cl v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_cd_cl v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa4,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:3], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa5,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xa6,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa4,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_c_cd v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_c_cd v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xa8,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xa9,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xaa,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xa8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xa8,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xac,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xad,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xae,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xac,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xac,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd_o v5, v[246:249], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0xf6,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd_o v5, v[1:4], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_cd_o v5, v[1:4], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_cd_o v5, v[1:4], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:7], v[1:4], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:8], v[1:4], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb0,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb1,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb2,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb0,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb0,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb4,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:4], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb5,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xb6,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb4,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb4,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd_o v5, v[245:252], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0xf5,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_c_cd_o v5, v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xb8,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xb9,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xba,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xb8,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xb8,0xf1,0x01,0x05,0x62,0x80]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v252, v[1:8], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0xfc,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[244:251], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0xf4,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[12:19], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x63,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[92:99], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x77,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], ttmp[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x7d,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[16:19] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x82,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[96:99] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x02,0x03]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], ttmp[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0xc2,0x03]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x2
+// CHECK: [0x00,0x02,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x3
+// CHECK: [0x00,0x03,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x4
+// CHECK: [0x00,0x04,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x5
+// CHECK: [0x00,0x05,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x6
+// CHECK: [0x00,0x06,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0x7
+// CHECK: [0x00,0x07,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x8
+// CHECK: [0x00,0x08,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x9
+// CHECK: [0x00,0x09,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xa
+// CHECK: [0x00,0x0a,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xb
+// CHECK: [0x00,0x0b,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0xc
+// CHECK: [0x00,0x0c,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xd
+// CHECK: [0x00,0x0d,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:7], v[1:8], s[8:15], s[12:15] dmask:0xe
+// CHECK: [0x00,0x0e,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:8], v[1:8], s[8:15], s[12:15] dmask:0xf
+// CHECK: [0x00,0x0f,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x0
+// CHECK: [0x00,0x00,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:16], s[8:15], s[12:15] dmask:0x1
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 unorm
+// CHECK: [0x00,0x11,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 glc
+// CHECK: [0x00,0x21,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 slc
+// CHECK: [0x00,0x01,0xbc,0xf3,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 a16
+// CHECK: [0x00,0x81,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v[5:6], v[1:8], s[8:15], s[12:15] dmask:0x1 tfe
+// CHECK: [0x00,0x01,0xbd,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 lwe
+// CHECK: [0x00,0x01,0xbe,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 da
+// CHECK: [0x00,0x41,0xbc,0xf1,0x01,0x05,0x62,0x00]
+
+image_sample_c_cd_cl_o v5, v[1:8], s[8:15], s[12:15] dmask:0x1 d16
+// CHECK: [0x00,0x01,0xbc,0xf1,0x01,0x05,0x62,0x80]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s b/llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s
new file mode 100644
index 0000000000000..59d18196fa61b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_mtbuf.s
@@ -0,0 +1,2497 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0xff,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_x v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_x v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_x v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x08,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x88,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x08,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0xfe,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_xy v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x10,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x18,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x20,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x28,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x30,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x38,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x40,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x48,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x50,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x58,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x60,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x68,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x70,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x78,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x00,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x08,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x88,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0xaf,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x9f,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x80,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x80,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x80,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0xcf,0x08,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x8f,0x08,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0xfd,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x11,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x19,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x21,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x29,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x31,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x39,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x41,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x49,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x51,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x59,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x61,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x69,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x71,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x79,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x01,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x09,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x89,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x09,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0xfc,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x11,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x19,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x21,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x29,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x31,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x39,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x41,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x49,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x51,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x59,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x61,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x69,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x71,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x79,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x01,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x89,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x89,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x89,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x09,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x89,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0xaf,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x9f,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x80,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x80,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x80,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0xcf,0x09,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x8f,0x09,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0xff,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_x v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_x v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_x v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x12,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x22,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x32,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x42,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x52,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x62,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x72,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x02,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0a,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8a,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0a,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0xfe,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_xy v[1:2], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x12,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x22,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x32,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x42,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x52,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x62,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x72,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x02,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8a,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8a,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0a,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8a,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x9f,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x80,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x80,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x80,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0a,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0a,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0xfd,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x13,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x23,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x33,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x43,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x53,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x63,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x73,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x03,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0b,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8b,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0b,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0xfc,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x13,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x23,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x33,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x43,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x53,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x63,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x73,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x03,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8b,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8b,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0b,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8b,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x9f,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x80,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x80,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x80,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0b,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0b,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0xff,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_d16_x v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0c,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0xff,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_d16_xy v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x14,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x24,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x34,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x44,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x54,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x64,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x74,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x04,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0c,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8c,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x9f,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3
+// CHECK: [0x00,0x80,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x80,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x80,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0c,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xy v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0c,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0xfe,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x15,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x25,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x35,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x45,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x55,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x65,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x75,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x05,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0d,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8d,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0d,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0xfe,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x03,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x18,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x1e,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x65]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x66]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x67]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x6a]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x6b]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x7b]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x7c]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x7e]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x7f]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x80]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xc1]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xf0]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xf7]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xfb]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xfc]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0xfd]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x15,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x25,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x35,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x45,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x55,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x65,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x75,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x05,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8d,0xe9,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8d,0xea,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0d,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8d,0xeb,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x9f,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x80,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x80,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x80,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0d,0xe8,0x00,0x05,0x02,0x03]
+
+tbuffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0d,0xe8,0x00,0x05,0x42,0x03]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0xff,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_d16_x v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x16,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x26,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x36,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x46,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x56,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x66,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x76,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x06,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0e,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0xff,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_d16_xy v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x16,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x26,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x36,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x46,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x56,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x66,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x76,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x06,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8e,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8e,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8e,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x9f,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4
+// CHECK: [0x00,0x80,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x80,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x80,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0e,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xy v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0e,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0xfe,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x0f,0x17,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x1f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x0f,0x27,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x2f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x0f,0x37,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x0f,0x3f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x0f,0x47,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x0f,0x4f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x0f,0x57,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x5f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x0f,0x67,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x6f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x0f,0x77,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x0f,0x7f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x0f,0x07,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x0f,0x0f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x0f,0x8f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0f,0xe8,0x00,0x01,0x43,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0xfe,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x04,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x18,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x1e,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x65]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x66]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x67]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x6a]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x6b]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x7b]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x7c]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x7e]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x7f]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x80]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xc1]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xf0]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xf7]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xfb]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xfc]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0xfd]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16] offset:4095
+// CHECK: [0xff,0x8f,0x17,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x1f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32] offset:4095
+// CHECK: [0xff,0x8f,0x27,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x2f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_11_11] offset:4095
+// CHECK: [0xff,0x8f,0x37,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_11_11_10] offset:4095
+// CHECK: [0xff,0x8f,0x3f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_10_10_10_2] offset:4095
+// CHECK: [0xff,0x8f,0x47,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_2_10_10_10] offset:4095
+// CHECK: [0xff,0x8f,0x4f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_8_8_8_8] offset:4095
+// CHECK: [0xff,0x8f,0x57,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x5f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_16_16_16_16] offset:4095
+// CHECK: [0xff,0x8f,0x67,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x6f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_32_32_32_32] offset:4095
+// CHECK: [0xff,0x8f,0x77,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_RESERVED_15] offset:4095
+// CHECK: [0xff,0x8f,0x7f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_DATA_FORMAT_INVALID] offset:4095
+// CHECK: [0xff,0x8f,0x07,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UNORM] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SNORM] offset:4095
+// CHECK: [0xff,0x8f,0x8f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_USCALED] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SSCALED] offset:4095
+// CHECK: [0xff,0x8f,0x8f,0xe9,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_UINT] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_SINT] offset:4095
+// CHECK: [0xff,0x8f,0x8f,0xea,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_RESERVED_6] offset:4095
+// CHECK: [0xff,0x8f,0x0f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 format:[BUF_NUM_FORMAT_FLOAT] offset:4095
+// CHECK: [0xff,0x8f,0x8f,0xeb,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0xaf,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x9f,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x80,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x80,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x80,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0xcf,0x0f,0xe8,0x00,0x01,0x03,0x04]
+
+tbuffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x8f,0x0f,0xe8,0x00,0x01,0x43,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s b/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
new file mode 100644
index 0000000000000..f20d9cc59e94b
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_mubuf.s
@@ -0,0 +1,5638 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_format_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_x v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_x v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_x v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x00,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x02,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_x v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x01,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xy v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_xy v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_xy v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_xy v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_xy v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_xy v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_xy v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xy v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_xy v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_xy v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xy v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xy v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xy v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xy v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_xy v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_xy v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_xy v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x04,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xy v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x06,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0xfd,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_xyz v[5:7], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_xyz v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x08,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyz v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0xfc,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_xyzw v[5:8], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_xyzw v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0e,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_format_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_x v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_x v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_x v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x10,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x12,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xy v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_xy v[1:2], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_xy v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_xy v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_xy v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_xy v[1:2], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_xy v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xy v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_xy v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_xy v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xy v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xy v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xy v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xy v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_xy v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_xy v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_xy v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x14,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xy v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x16,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0xfd,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_xyz v[1:3], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_xyz v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x18,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyz v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1a,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0xfc,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_xyzw v[1:4], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x1c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_xyzw v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1e,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_d16_x v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_d16_x v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_d16_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_d16_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_d16_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_d16_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_d16_x v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_d16_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_d16_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_d16_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_d16_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_d16_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_d16_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_d16_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_d16_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_d16_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_d16_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_d16_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x20,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x22,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_format_d16_xy v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_d16_xy v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_d16_xy v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_d16_xy v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_d16_xy v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_d16_xy v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_d16_xy v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_d16_xy v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_d16_xy v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_d16_xy v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_d16_xy v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_d16_xy v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_d16_xy v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_d16_xy v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_d16_xy v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_d16_xy v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_d16_xy v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_d16_xy v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_d16_xy v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_d16_xy v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x24,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xy v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x26,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_d16_xyz v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x28,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyz v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_d16_xyzw v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x2c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_xyzw v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2e,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_d16_x v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_d16_x v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_d16_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_d16_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_d16_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_d16_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_d16_x v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_d16_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_d16_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_d16_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_d16_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_d16_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_d16_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_d16_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_d16_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_d16_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_d16_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_d16_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x30,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x32,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_format_d16_xy v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_d16_xy v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_d16_xy v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_d16_xy v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_d16_xy v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_d16_xy v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_d16_xy v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_d16_xy v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_d16_xy v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_d16_xy v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_d16_xy v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_d16_xy v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_d16_xy v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_d16_xy v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_d16_xy v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_d16_xy v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_d16_xy v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_d16_xy v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_d16_xy v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x34,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_d16_xy v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x34,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xy v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x36,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x38,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_d16_xyz v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x38,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyz v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x3a,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x3c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_d16_xyzw v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x3c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_xyzw v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x3e,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ubyte v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_ubyte v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_ubyte v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_ubyte v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_ubyte v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_ubyte v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_ubyte v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_ubyte v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ubyte v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_ubyte v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_ubyte v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ubyte v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ubyte v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ubyte v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ubyte v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_ubyte v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_ubyte v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x40,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_ubyte v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x40,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x42,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x41,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sbyte v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_sbyte v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_sbyte v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_sbyte v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_sbyte v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_sbyte v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_sbyte v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_sbyte v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sbyte v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_sbyte v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_sbyte v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sbyte v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sbyte v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sbyte v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sbyte v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_sbyte v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_sbyte v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x44,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_sbyte v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x44,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x46,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x45,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ushort v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ushort v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_ushort v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_ushort v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_ushort v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_ushort v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_ushort v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_ushort v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_ushort v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ushort v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_ushort v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_ushort v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ushort v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ushort v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ushort v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ushort v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_ushort v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_ushort v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x48,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_ushort v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x48,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x4a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ushort v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x49,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sshort v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sshort v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_sshort v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_sshort v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_sshort v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_sshort v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_sshort v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_sshort v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_sshort v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sshort v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_sshort v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_sshort v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sshort v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sshort v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sshort v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sshort v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_sshort v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_sshort v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x4c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_sshort v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x4c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x4e,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sshort v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x4d,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_dword v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dword v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dword v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dword v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dword v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_dword v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dword v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dword v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dword v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dword v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dword v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dword v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dword v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dword v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dword v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dword v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dword v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dword v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dword v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x50,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dword v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x50,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x52,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dword v5, off, s[8:11], s3 offset:4095 lds
+// CHECK: [0xff,0x0f,0x51,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0xfe,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dwordx2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x54,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x54,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x56,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[253:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0xfd,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dwordx3 v[5:7], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x58,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x58,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx3 v[5:7], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x5a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0xfc,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_dwordx4 v[5:8], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x5c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x5c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_dwordx4 v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x5e,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_byte v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_byte v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_byte v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_byte v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_byte v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_byte v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_byte v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_byte v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_byte v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_byte v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_byte v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_byte v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_byte v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_byte v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_byte v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_byte v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_byte v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_byte v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_byte v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x60,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_byte v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x60,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x62,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte_d16_hi v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_byte_d16_hi v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_byte_d16_hi v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_byte_d16_hi v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x64,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_byte_d16_hi v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x64,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte_d16_hi v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x64,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x64,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x64,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x64,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x64,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_byte_d16_hi v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x66,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_short v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_short v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_short v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_short v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_short v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_short v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_short v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_short v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_short v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_short v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_short v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_short v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_short v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_short v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_short v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_short v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_short v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_short v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_short v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x68,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_short v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x68,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x6a,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short_d16_hi v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_short_d16_hi v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_short_d16_hi v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_short_d16_hi v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_short_d16_hi v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_short_d16_hi v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_short_d16_hi v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_short_d16_hi v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_short_d16_hi v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_short_d16_hi v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_short_d16_hi v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_short_d16_hi v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_short_d16_hi v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_short_d16_hi v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_short_d16_hi v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_short_d16_hi v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_short_d16_hi v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_short_d16_hi v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_short_d16_hi v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_short_d16_hi v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x6c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_short_d16_hi v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x6c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short_d16_hi v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x6c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short_d16_hi v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x6c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x6c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x6c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_short_d16_hi v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x6e,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_dword v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dword v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dword v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dword v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dword v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_dword v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dword v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dword v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dword v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dword v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dword v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dword v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dword v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dword v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dword v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dword v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dword v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dword v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dword v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x70,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dword v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x70,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dword v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x72,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[254:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0xfe,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dwordx2 v[1:2], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x74,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x74,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx2 v[1:2], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x76,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[253:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0xfd,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dwordx3 v[1:3], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x78,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x78,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx3 v[1:3], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x7a,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[252:255], off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0xfc,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_dwordx4 v[1:4], off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x7c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4
+// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x7c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_dwordx4 v[1:4], off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x7e,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16 v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ubyte_d16 v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ubyte_d16 v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_ubyte_d16 v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_ubyte_d16 v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x80,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16 v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x80,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x80,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x80,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x80,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x80,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16 v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x82,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16_hi v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_ubyte_d16_hi v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x84,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16_hi v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x84,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x84,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x84,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x84,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x84,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_ubyte_d16_hi v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x86,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16 v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sbyte_d16 v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sbyte_d16 v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_sbyte_d16 v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_sbyte_d16 v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x88,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16 v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x88,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x88,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x88,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x88,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x88,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16 v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x8a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16_hi v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_sbyte_d16_hi v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x8c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16_hi v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x8c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x8c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x8c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x8c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x8c,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_sbyte_d16_hi v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x8e,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16 v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16 v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_short_d16 v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_short_d16 v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_short_d16 v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_short_d16 v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_short_d16 v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_short_d16 v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_short_d16 v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_short_d16 v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_short_d16 v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_short_d16 v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_short_d16 v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_short_d16 v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_short_d16 v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_short_d16 v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_short_d16 v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_short_d16 v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_short_d16 v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_short_d16 v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_short_d16 v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_short_d16 v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x90,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16 v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x90,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16 v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x90,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16 v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x90,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16 v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x90,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16 v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x90,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16 v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x92,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16_hi v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_short_d16_hi v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_short_d16_hi v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_short_d16_hi v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_short_d16_hi v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_short_d16_hi v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_short_d16_hi v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_short_d16_hi v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_short_d16_hi v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_short_d16_hi v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_short_d16_hi v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_short_d16_hi v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_short_d16_hi v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_short_d16_hi v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_short_d16_hi v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_short_d16_hi v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_short_d16_hi v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_short_d16_hi v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_short_d16_hi v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_short_d16_hi v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_short_d16_hi v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x94,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16_hi v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x94,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16_hi v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x94,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x94,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x94,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x94,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_short_d16_hi v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x96,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_hi_x v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0xff,0x02,0x03]
+
+buffer_load_format_d16_hi_x v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x03,0x03]
+
+buffer_load_format_d16_hi_x v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x18,0x03]
+
+buffer_load_format_d16_hi_x v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x1e,0x03]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x65]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x66]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x67]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x6a]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x6b]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x7b]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x7c]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x7e]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x7f]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0x80]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0xc1]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0xf0]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0xf7]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0xfb]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0xfc]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe0,0x00,0x05,0x02,0xfd]
+
+buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x98,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_hi_x v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x98,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x98,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x98,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x98,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x98,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_load_format_d16_hi_x v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x9a,0xe0,0x00,0x05,0x02,0x03]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_hi_x v255, off, s[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0xff,0x03,0x04]
+
+buffer_store_format_d16_hi_x v1, off, s[16:19], s4 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x04,0x04]
+
+buffer_store_format_d16_hi_x v1, off, s[96:99], s4 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x18,0x04]
+
+buffer_store_format_d16_hi_x v1, off, ttmp[12:15], s4 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x1e,0x04]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], s101 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x65]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x66]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x67]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x6a]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x6b]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x7b]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], m0 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x7c]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x7e]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x7f]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], 0 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0x80]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], -1 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0xc1]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0xf0]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0xf7]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0xfb]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0xfc]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe0,0x00,0x01,0x03,0xfd]
+
+buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 idxen offset:4095
+// CHECK: [0xff,0x2f,0x9c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_hi_x v1, v0, s[12:15], s4 offen offset:4095
+// CHECK: [0xff,0x1f,0x9c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], s4
+// CHECK: [0x00,0x00,0x9c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:0
+// CHECK: [0x00,0x00,0x9c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:7
+// CHECK: [0x07,0x00,0x9c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 glc
+// CHECK: [0xff,0x4f,0x9c,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_format_d16_hi_x v1, off, s[12:15], s4 offset:4095 slc
+// CHECK: [0xff,0x0f,0x9e,0xe0,0x00,0x01,0x03,0x04]
+
+buffer_store_lds_dword s[4:7], s0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[8:11], s0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x02,0x00]
+
+buffer_store_lds_dword s[96:99], s0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x18,0x00]
+
+buffer_store_lds_dword ttmp[12:15], s0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x1e,0x00]
+
+buffer_store_lds_dword s[4:7], s101 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x65]
+
+buffer_store_lds_dword s[4:7], flat_scratch_lo offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x66]
+
+buffer_store_lds_dword s[4:7], flat_scratch_hi offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x67]
+
+buffer_store_lds_dword s[4:7], vcc_lo offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x6a]
+
+buffer_store_lds_dword s[4:7], vcc_hi offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x6b]
+
+buffer_store_lds_dword s[4:7], ttmp15 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x7b]
+
+buffer_store_lds_dword s[4:7], m0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x7c]
+
+buffer_store_lds_dword s[4:7], exec_lo offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x7e]
+
+buffer_store_lds_dword s[4:7], exec_hi offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x7f]
+
+buffer_store_lds_dword s[4:7], 0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0x80]
+
+buffer_store_lds_dword s[4:7], -1 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xc1]
+
+buffer_store_lds_dword s[4:7], 0.5 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xf0]
+
+buffer_store_lds_dword s[4:7], -4.0 offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xf7]
+
+buffer_store_lds_dword s[4:7], src_vccz offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xfb]
+
+buffer_store_lds_dword s[4:7], src_execz offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xfc]
+
+buffer_store_lds_dword s[4:7], src_scc offset:4095 lds
+// CHECK: [0xff,0x0f,0xf5,0xe0,0x00,0x00,0x01,0xfd]
+
+buffer_store_lds_dword s[4:7], s0 lds
+// CHECK: [0x00,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[4:7], s0 offset:0 lds
+// CHECK: [0x00,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_store_lds_dword s[4:7], s0 offset:7 lds
+// CHECK: [0x07,0x00,0xf5,0xe0,0x00,0x00,0x01,0x00]
+
+buffer_wbinvl1
+// CHECK: [0x00,0x00,0xf8,0xe0,0x00,0x00,0x00,0x00]
+
+buffer_wbinvl1_vol
+// CHECK: [0x00,0x00,0xfc,0xe0,0x00,0x00,0x00,0x00]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_swap v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_swap v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_swap v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_swap v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_swap v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_swap v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_swap v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_swap v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_swap v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_swap v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_swap v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_swap v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_swap v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_swap v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_swap v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_swap v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_swap v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x00,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_swap v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x00,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x02,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x04,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x04,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x06,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_add v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_add v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_add v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_add v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_add v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_add v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_add v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_add v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_add v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_add v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_add v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_add v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_add v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_add v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_add v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_add v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_add v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_add v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x08,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_add v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x08,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_sub v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_sub v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_sub v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_sub v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_sub v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_sub v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_sub v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_sub v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_sub v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_sub v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_sub v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_sub v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_sub v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_sub v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_sub v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_sub v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_sub v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x0c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_sub v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x0c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x0e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smin v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smin v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smin v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_smin v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_smin v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_smin v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_smin v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_smin v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smin v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_smin v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_smin v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smin v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smin v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_smin v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_smin v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_smin v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_smin v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x10,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_smin v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x10,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x12,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umin v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umin v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umin v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_umin v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_umin v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_umin v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_umin v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_umin v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umin v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_umin v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_umin v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umin v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umin v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_umin v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_umin v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_umin v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_umin v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x14,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_umin v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x14,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x16,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smax v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smax v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smax v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_smax v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_smax v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_smax v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_smax v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_smax v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smax v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_smax v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_smax v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smax v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smax v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_smax v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_smax v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_smax v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_smax v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x18,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_smax v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x18,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umax v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umax v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umax v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_umax v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_umax v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_umax v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_umax v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_umax v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umax v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_umax v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_umax v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umax v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umax v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_umax v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_umax v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_umax v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_umax v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x1c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_umax v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x1c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x1e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_and v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_and v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_and v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_and v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_and v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_and v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_and v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_and v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_and v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_and v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_and v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_and v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_and v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_and v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_and v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_and v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_and v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_and v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x20,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_and v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x20,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x22,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_or v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_or v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_or v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_or v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_or v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_or v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_or v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_or v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_or v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_or v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_or v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_or v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_or v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_or v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_or v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_or v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_or v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_or v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x24,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_or v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x24,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x26,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_xor v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_xor v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_xor v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_xor v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_xor v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_xor v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_xor v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_xor v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_xor v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_xor v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_xor v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_xor v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_xor v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_xor v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_xor v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_xor v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_xor v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x28,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_xor v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x28,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_inc v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_inc v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_inc v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_inc v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_inc v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_inc v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_inc v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_inc v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_inc v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_inc v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_inc v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_inc v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_inc v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_inc v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_inc v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_inc v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_inc v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x2c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_inc v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x2c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x2e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v255, off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0xff,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_dec v5, off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_dec v5, off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_dec v5, off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_dec v5, off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_dec v5, off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_dec v5, off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_dec v5, off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_dec v5, off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_dec v5, off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_dec v5, off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_dec v5, off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_dec v5, off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_dec v5, off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_dec v5, off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_dec v5, off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_dec v5, off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_dec v5, off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x30,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_dec v5, v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3
+// CHECK: [0x00,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x30,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec v5, off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x32,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x80,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x80,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_swap_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x82,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[252:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0xfc,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x84,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x84,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_cmpswap_x2 v[5:8], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x86,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x88,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x88,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_add_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x8a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x8c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x8c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_sub_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x8e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x90,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x90,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x92,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x94,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x94,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umin_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x96,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x98,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x98,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_smax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x9a,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0x9c,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0x9c,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_umax_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0x9e,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xa0,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xa0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_and_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xa2,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xa4,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xa4,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_or_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xa6,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xa8,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xa8,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_xor_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xaa,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xac,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xac,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_inc_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xae,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[254:255], off, s[8:11], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0xfe,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x03,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[96:99], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x18,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, ttmp[12:15], s3 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x1e,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s101 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x65]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], flat_scratch_lo offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x66]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], flat_scratch_hi offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x67]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], vcc_lo offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x6a]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], vcc_hi offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x6b]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], ttmp15 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7b]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], m0 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7c]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], exec_lo offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7e]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], exec_hi offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x7f]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0x80]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], -1 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xc1]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], 0.5 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xf0]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], -4.0 offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xf7]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], src_vccz offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xfb]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], src_execz offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xfc]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], src_scc offset:4095
+// CHECK: [0xff,0x0f,0xb0,0xe1,0x00,0x05,0x02,0xfd]
+
+buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 idxen offset:4095
+// CHECK: [0xff,0x2f,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], v0, s[8:11], s3 offen offset:4095
+// CHECK: [0xff,0x1f,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3
+// CHECK: [0x00,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:0
+// CHECK: [0x00,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:7
+// CHECK: [0x07,0x00,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 glc
+// CHECK: [0xff,0x4f,0xb0,0xe1,0x00,0x05,0x02,0x03]
+
+buffer_atomic_dec_x2 v[5:6], off, s[8:11], s3 offset:4095 slc
+// CHECK: [0xff,0x0f,0xb2,0xe1,0x00,0x05,0x02,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_smem.s b/llvm/test/MC/AMDGPU/gfx9_asm_smem.s
new file mode 100644
index 0000000000000..1989062e3a509
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_smem.s
@@ -0,0 +1,4477 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+s_load_dword s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, vcc, s0
+// CHECK: [0x75,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x00,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x00,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x00,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x00,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x00,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x00,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x00,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x00,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x02,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dword s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x01,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x04,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x04,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x04,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x04,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x04,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x04,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x04,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x04,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x06,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x05,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], s0
+// CHECK: [0x01,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[24:27], s[2:3], s0
+// CHECK: [0x01,0x06,0x08,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[96:99], s[2:3], s0
+// CHECK: [0x01,0x18,0x08,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 ttmp[12:15], s[2:3], s0
+// CHECK: [0x01,0x1e,0x08,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[4:5], s0
+// CHECK: [0x02,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[100:101], s0
+// CHECK: [0x32,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], flat_scratch, s0
+// CHECK: [0x33,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], vcc, s0
+// CHECK: [0x35,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], ttmp[14:15], s0
+// CHECK: [0x3d,0x05,0x08,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], s101
+// CHECK: [0x01,0x05,0x08,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x05,0x08,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x05,0x08,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], vcc_lo
+// CHECK: [0x01,0x05,0x08,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], vcc_hi
+// CHECK: [0x01,0x05,0x08,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], ttmp15
+// CHECK: [0x01,0x05,0x08,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], m0
+// CHECK: [0x01,0x05,0x08,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], 0x0
+// CHECK: [0x01,0x05,0x0a,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx4 s[20:23], s[2:3], s0 glc
+// CHECK: [0x01,0x05,0x09,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], s0
+// CHECK: [0x01,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[24:31], s[2:3], s0
+// CHECK: [0x01,0x06,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[92:99], s[2:3], s0
+// CHECK: [0x01,0x17,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 ttmp[8:15], s[2:3], s0
+// CHECK: [0x01,0x1d,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[4:5], s0
+// CHECK: [0x02,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[100:101], s0
+// CHECK: [0x32,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], flat_scratch, s0
+// CHECK: [0x33,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], vcc, s0
+// CHECK: [0x35,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], ttmp[14:15], s0
+// CHECK: [0x3d,0x05,0x0c,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], s101
+// CHECK: [0x01,0x05,0x0c,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x05,0x0c,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x05,0x0c,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], vcc_lo
+// CHECK: [0x01,0x05,0x0c,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], vcc_hi
+// CHECK: [0x01,0x05,0x0c,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], ttmp15
+// CHECK: [0x01,0x05,0x0c,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], m0
+// CHECK: [0x01,0x05,0x0c,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], 0x0
+// CHECK: [0x01,0x05,0x0e,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx8 s[20:27], s[2:3], s0 glc
+// CHECK: [0x01,0x05,0x0d,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], s0
+// CHECK: [0x01,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[24:39], s[2:3], s0
+// CHECK: [0x01,0x06,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[84:99], s[2:3], s0
+// CHECK: [0x01,0x15,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 ttmp[0:15], s[2:3], s0
+// CHECK: [0x01,0x1b,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[4:5], s0
+// CHECK: [0x02,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[100:101], s0
+// CHECK: [0x32,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], flat_scratch, s0
+// CHECK: [0x33,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], vcc, s0
+// CHECK: [0x35,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], ttmp[14:15], s0
+// CHECK: [0x3d,0x05,0x10,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], s101
+// CHECK: [0x01,0x05,0x10,0xc0,0x65,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x05,0x10,0xc0,0x66,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x05,0x10,0xc0,0x67,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], vcc_lo
+// CHECK: [0x01,0x05,0x10,0xc0,0x6a,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], vcc_hi
+// CHECK: [0x01,0x05,0x10,0xc0,0x6b,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], ttmp15
+// CHECK: [0x01,0x05,0x10,0xc0,0x7b,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], m0
+// CHECK: [0x01,0x05,0x10,0xc0,0x7c,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], 0x0
+// CHECK: [0x01,0x05,0x12,0xc0,0x00,0x00,0x00,0x00]
+
+s_load_dwordx16 s[20:35], s[2:3], s0 glc
+// CHECK: [0x01,0x05,0x11,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, vcc, s0
+// CHECK: [0x75,0x01,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x14,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x14,0xc0,0x65,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x14,0xc0,0x66,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x14,0xc0,0x67,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x14,0xc0,0x6a,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x14,0xc0,0x6b,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x14,0xc0,0x7b,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x14,0xc0,0x7c,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x16,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dword s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x15,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x18,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x18,0xc0,0x65,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x18,0xc0,0x66,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x18,0xc0,0x67,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x18,0xc0,0x6a,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x18,0xc0,0x6b,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x18,0xc0,0x7b,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x18,0xc0,0x7c,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x1a,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x19,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], s0
+// CHECK: [0x01,0x05,0x1c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[24:27], s[2:3], s0
+// CHECK: [0x01,0x06,0x1c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[96:99], s[2:3], s0
+// CHECK: [0x01,0x18,0x1c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 ttmp[12:15], s[2:3], s0
+// CHECK: [0x01,0x1e,0x1c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[4:5], s0
+// CHECK: [0x02,0x05,0x1c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[100:101], s0
+// CHECK: [0x32,0x05,0x1c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], flat_scratch, s0
+// CHECK: [0x33,0x05,0x1c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], vcc, s0
+// CHECK: [0x35,0x05,0x1c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], ttmp[14:15], s0
+// CHECK: [0x3d,0x05,0x1c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], s101
+// CHECK: [0x01,0x05,0x1c,0xc0,0x65,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x05,0x1c,0xc0,0x66,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x05,0x1c,0xc0,0x67,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], vcc_lo
+// CHECK: [0x01,0x05,0x1c,0xc0,0x6a,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], vcc_hi
+// CHECK: [0x01,0x05,0x1c,0xc0,0x6b,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], ttmp15
+// CHECK: [0x01,0x05,0x1c,0xc0,0x7b,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], m0
+// CHECK: [0x01,0x05,0x1c,0xc0,0x7c,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], 0x0
+// CHECK: [0x01,0x05,0x1e,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_load_dwordx4 s[20:23], s[2:3], s0 glc
+// CHECK: [0x01,0x05,0x1d,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x20,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x20,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x20,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x20,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x20,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x20,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x20,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x20,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x22,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dword s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x21,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0x24,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0x24,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0x24,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0x24,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0x24,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0x24,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0x24,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0x24,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0x24,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x24,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x24,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x24,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x24,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x24,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0x24,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x24,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0x26,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0x25,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s0
+// CHECK: [0x02,0x05,0x28,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[24:27], s[4:7], s0
+// CHECK: [0x02,0x06,0x28,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[96:99], s[4:7], s0
+// CHECK: [0x02,0x18,0x28,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 ttmp[12:15], s[4:7], s0
+// CHECK: [0x02,0x1e,0x28,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[8:11], s0
+// CHECK: [0x04,0x05,0x28,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[96:99], s0
+// CHECK: [0x30,0x05,0x28,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], ttmp[12:15], s0
+// CHECK: [0x3c,0x05,0x28,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s101
+// CHECK: [0x02,0x05,0x28,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_lo
+// CHECK: [0x02,0x05,0x28,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], flat_scratch_hi
+// CHECK: [0x02,0x05,0x28,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_lo
+// CHECK: [0x02,0x05,0x28,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], vcc_hi
+// CHECK: [0x02,0x05,0x28,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], ttmp15
+// CHECK: [0x02,0x05,0x28,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], m0
+// CHECK: [0x02,0x05,0x28,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], 0x0
+// CHECK: [0x02,0x05,0x2a,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx4 s[20:23], s[4:7], s0 glc
+// CHECK: [0x02,0x05,0x29,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s0
+// CHECK: [0x02,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[24:31], s[4:7], s0
+// CHECK: [0x02,0x06,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[92:99], s[4:7], s0
+// CHECK: [0x02,0x17,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 ttmp[8:15], s[4:7], s0
+// CHECK: [0x02,0x1d,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[8:11], s0
+// CHECK: [0x04,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[96:99], s0
+// CHECK: [0x30,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], ttmp[12:15], s0
+// CHECK: [0x3c,0x05,0x2c,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s101
+// CHECK: [0x02,0x05,0x2c,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_lo
+// CHECK: [0x02,0x05,0x2c,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], flat_scratch_hi
+// CHECK: [0x02,0x05,0x2c,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_lo
+// CHECK: [0x02,0x05,0x2c,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], vcc_hi
+// CHECK: [0x02,0x05,0x2c,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], ttmp15
+// CHECK: [0x02,0x05,0x2c,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], m0
+// CHECK: [0x02,0x05,0x2c,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], 0x0
+// CHECK: [0x02,0x05,0x2e,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx8 s[20:27], s[4:7], s0 glc
+// CHECK: [0x02,0x05,0x2d,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s0
+// CHECK: [0x02,0x05,0x30,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[24:39], s[4:7], s0
+// CHECK: [0x02,0x06,0x30,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[84:99], s[4:7], s0
+// CHECK: [0x02,0x15,0x30,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 ttmp[0:15], s[4:7], s0
+// CHECK: [0x02,0x1b,0x30,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[8:11], s0
+// CHECK: [0x04,0x05,0x30,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[96:99], s0
+// CHECK: [0x30,0x05,0x30,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], ttmp[12:15], s0
+// CHECK: [0x3c,0x05,0x30,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s101
+// CHECK: [0x02,0x05,0x30,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_lo
+// CHECK: [0x02,0x05,0x30,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], flat_scratch_hi
+// CHECK: [0x02,0x05,0x30,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_lo
+// CHECK: [0x02,0x05,0x30,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], vcc_hi
+// CHECK: [0x02,0x05,0x30,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], ttmp15
+// CHECK: [0x02,0x05,0x30,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], m0
+// CHECK: [0x02,0x05,0x30,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], 0x0
+// CHECK: [0x02,0x05,0x32,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_load_dwordx16 s[20:35], s[4:7], s0 glc
+// CHECK: [0x02,0x05,0x31,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], s0
+// CHECK: [0x42,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword s101, s[4:5], s0
+// CHECK: [0x42,0x19,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword flat_scratch_lo, s[4:5], s0
+// CHECK: [0x82,0x19,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword flat_scratch_hi, s[4:5], s0
+// CHECK: [0xc2,0x19,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword vcc_lo, s[4:5], s0
+// CHECK: [0x82,0x1a,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword vcc_hi, s[4:5], s0
+// CHECK: [0xc2,0x1a,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword ttmp15, s[4:5], s0
+// CHECK: [0xc2,0x1e,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[6:7], s0
+// CHECK: [0x43,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[100:101], s0
+// CHECK: [0x72,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, flat_scratch, s0
+// CHECK: [0x73,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, vcc, s0
+// CHECK: [0x75,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, ttmp[14:15], s0
+// CHECK: [0x7d,0x00,0x40,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], s101
+// CHECK: [0x42,0x00,0x40,0xc0,0x65,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], flat_scratch_lo
+// CHECK: [0x42,0x00,0x40,0xc0,0x66,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], flat_scratch_hi
+// CHECK: [0x42,0x00,0x40,0xc0,0x67,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], vcc_lo
+// CHECK: [0x42,0x00,0x40,0xc0,0x6a,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], vcc_hi
+// CHECK: [0x42,0x00,0x40,0xc0,0x6b,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], ttmp15
+// CHECK: [0x42,0x00,0x40,0xc0,0x7b,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], m0
+// CHECK: [0x42,0x00,0x40,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], 0x0
+// CHECK: [0x42,0x00,0x42,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dword s1, s[4:5], s0 glc
+// CHECK: [0x42,0x00,0x41,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], s0
+// CHECK: [0x82,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[4:5], s[4:5], s0
+// CHECK: [0x02,0x01,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[100:101], s[4:5], s0
+// CHECK: [0x02,0x19,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 flat_scratch, s[4:5], s0
+// CHECK: [0x82,0x19,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 vcc, s[4:5], s0
+// CHECK: [0x82,0x1a,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 ttmp[14:15], s[4:5], s0
+// CHECK: [0x82,0x1e,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[6:7], s0
+// CHECK: [0x83,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[100:101], s0
+// CHECK: [0xb2,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], flat_scratch, s0
+// CHECK: [0xb3,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], vcc, s0
+// CHECK: [0xb5,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], ttmp[14:15], s0
+// CHECK: [0xbd,0x00,0x44,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], s101
+// CHECK: [0x82,0x00,0x44,0xc0,0x65,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], flat_scratch_lo
+// CHECK: [0x82,0x00,0x44,0xc0,0x66,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], flat_scratch_hi
+// CHECK: [0x82,0x00,0x44,0xc0,0x67,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], vcc_lo
+// CHECK: [0x82,0x00,0x44,0xc0,0x6a,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], vcc_hi
+// CHECK: [0x82,0x00,0x44,0xc0,0x6b,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], ttmp15
+// CHECK: [0x82,0x00,0x44,0xc0,0x7b,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], m0
+// CHECK: [0x82,0x00,0x44,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], 0x0
+// CHECK: [0x82,0x00,0x46,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx2 s[2:3], s[4:5], s0 glc
+// CHECK: [0x82,0x00,0x45,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], s0
+// CHECK: [0x02,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[8:11], s[4:5], s0
+// CHECK: [0x02,0x02,0x48,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[96:99], s[4:5], s0
+// CHECK: [0x02,0x18,0x48,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 ttmp[12:15], s[4:5], s0
+// CHECK: [0x02,0x1e,0x48,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[6:7], s0
+// CHECK: [0x03,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[100:101], s0
+// CHECK: [0x32,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], flat_scratch, s0
+// CHECK: [0x33,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], vcc, s0
+// CHECK: [0x35,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], ttmp[14:15], s0
+// CHECK: [0x3d,0x01,0x48,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], s101
+// CHECK: [0x02,0x01,0x48,0xc0,0x65,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], flat_scratch_lo
+// CHECK: [0x02,0x01,0x48,0xc0,0x66,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], flat_scratch_hi
+// CHECK: [0x02,0x01,0x48,0xc0,0x67,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], vcc_lo
+// CHECK: [0x02,0x01,0x48,0xc0,0x6a,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], vcc_hi
+// CHECK: [0x02,0x01,0x48,0xc0,0x6b,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], ttmp15
+// CHECK: [0x02,0x01,0x48,0xc0,0x7b,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], m0
+// CHECK: [0x02,0x01,0x48,0xc0,0x7c,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], 0x0
+// CHECK: [0x02,0x01,0x4a,0xc0,0x00,0x00,0x00,0x00]
+
+s_store_dwordx4 s[4:7], s[4:5], s0 glc
+// CHECK: [0x02,0x01,0x49,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], s0
+// CHECK: [0x42,0x00,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s101, s[4:5], s0
+// CHECK: [0x42,0x19,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword flat_scratch_lo, s[4:5], s0
+// CHECK: [0x82,0x19,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword flat_scratch_hi, s[4:5], s0
+// CHECK: [0xc2,0x19,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword vcc_lo, s[4:5], s0
+// CHECK: [0x82,0x1a,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword vcc_hi, s[4:5], s0
+// CHECK: [0xc2,0x1a,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword ttmp15, s[4:5], s0
+// CHECK: [0xc2,0x1e,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[6:7], s0
+// CHECK: [0x43,0x00,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[100:101], s0
+// CHECK: [0x72,0x00,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, flat_scratch, s0
+// CHECK: [0x73,0x00,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, vcc, s0
+// CHECK: [0x75,0x00,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, ttmp[14:15], s0
+// CHECK: [0x7d,0x00,0x54,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], s101
+// CHECK: [0x42,0x00,0x54,0xc0,0x65,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], flat_scratch_lo
+// CHECK: [0x42,0x00,0x54,0xc0,0x66,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], flat_scratch_hi
+// CHECK: [0x42,0x00,0x54,0xc0,0x67,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], vcc_lo
+// CHECK: [0x42,0x00,0x54,0xc0,0x6a,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], vcc_hi
+// CHECK: [0x42,0x00,0x54,0xc0,0x6b,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], ttmp15
+// CHECK: [0x42,0x00,0x54,0xc0,0x7b,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], m0
+// CHECK: [0x42,0x00,0x54,0xc0,0x7c,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], 0x0
+// CHECK: [0x42,0x00,0x56,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dword s1, s[4:5], s0 glc
+// CHECK: [0x42,0x00,0x55,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], s0
+// CHECK: [0x82,0x00,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[4:5], s[4:5], s0
+// CHECK: [0x02,0x01,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[100:101], s[4:5], s0
+// CHECK: [0x02,0x19,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 flat_scratch, s[4:5], s0
+// CHECK: [0x82,0x19,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 vcc, s[4:5], s0
+// CHECK: [0x82,0x1a,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 ttmp[14:15], s[4:5], s0
+// CHECK: [0x82,0x1e,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[6:7], s0
+// CHECK: [0x83,0x00,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[100:101], s0
+// CHECK: [0xb2,0x00,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], flat_scratch, s0
+// CHECK: [0xb3,0x00,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], vcc, s0
+// CHECK: [0xb5,0x00,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], ttmp[14:15], s0
+// CHECK: [0xbd,0x00,0x58,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], s101
+// CHECK: [0x82,0x00,0x58,0xc0,0x65,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], flat_scratch_lo
+// CHECK: [0x82,0x00,0x58,0xc0,0x66,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], flat_scratch_hi
+// CHECK: [0x82,0x00,0x58,0xc0,0x67,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], vcc_lo
+// CHECK: [0x82,0x00,0x58,0xc0,0x6a,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], vcc_hi
+// CHECK: [0x82,0x00,0x58,0xc0,0x6b,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], ttmp15
+// CHECK: [0x82,0x00,0x58,0xc0,0x7b,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], m0
+// CHECK: [0x82,0x00,0x58,0xc0,0x7c,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], 0x0
+// CHECK: [0x82,0x00,0x5a,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx2 s[2:3], s[4:5], s0 glc
+// CHECK: [0x82,0x00,0x59,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], s0
+// CHECK: [0x02,0x01,0x5c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[8:11], s[4:5], s0
+// CHECK: [0x02,0x02,0x5c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[96:99], s[4:5], s0
+// CHECK: [0x02,0x18,0x5c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 ttmp[12:15], s[4:5], s0
+// CHECK: [0x02,0x1e,0x5c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[6:7], s0
+// CHECK: [0x03,0x01,0x5c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[100:101], s0
+// CHECK: [0x32,0x01,0x5c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], flat_scratch, s0
+// CHECK: [0x33,0x01,0x5c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], vcc, s0
+// CHECK: [0x35,0x01,0x5c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], ttmp[14:15], s0
+// CHECK: [0x3d,0x01,0x5c,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], s101
+// CHECK: [0x02,0x01,0x5c,0xc0,0x65,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], flat_scratch_lo
+// CHECK: [0x02,0x01,0x5c,0xc0,0x66,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], flat_scratch_hi
+// CHECK: [0x02,0x01,0x5c,0xc0,0x67,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], vcc_lo
+// CHECK: [0x02,0x01,0x5c,0xc0,0x6a,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], vcc_hi
+// CHECK: [0x02,0x01,0x5c,0xc0,0x6b,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], ttmp15
+// CHECK: [0x02,0x01,0x5c,0xc0,0x7b,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], m0
+// CHECK: [0x02,0x01,0x5c,0xc0,0x7c,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], 0x0
+// CHECK: [0x02,0x01,0x5e,0xc0,0x00,0x00,0x00,0x00]
+
+s_scratch_store_dwordx4 s[4:7], s[4:5], s0 glc
+// CHECK: [0x02,0x01,0x5d,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], s0
+// CHECK: [0x44,0x00,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s101, s[8:11], s0
+// CHECK: [0x44,0x19,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword flat_scratch_lo, s[8:11], s0
+// CHECK: [0x84,0x19,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword flat_scratch_hi, s[8:11], s0
+// CHECK: [0xc4,0x19,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword vcc_lo, s[8:11], s0
+// CHECK: [0x84,0x1a,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword vcc_hi, s[8:11], s0
+// CHECK: [0xc4,0x1a,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword ttmp15, s[8:11], s0
+// CHECK: [0xc4,0x1e,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[12:15], s0
+// CHECK: [0x46,0x00,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[96:99], s0
+// CHECK: [0x70,0x00,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, ttmp[12:15], s0
+// CHECK: [0x7c,0x00,0x60,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], s101
+// CHECK: [0x44,0x00,0x60,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], flat_scratch_lo
+// CHECK: [0x44,0x00,0x60,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], flat_scratch_hi
+// CHECK: [0x44,0x00,0x60,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], vcc_lo
+// CHECK: [0x44,0x00,0x60,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], vcc_hi
+// CHECK: [0x44,0x00,0x60,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], ttmp15
+// CHECK: [0x44,0x00,0x60,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], m0
+// CHECK: [0x44,0x00,0x60,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], 0x0
+// CHECK: [0x44,0x00,0x62,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dword s1, s[8:11], s0 glc
+// CHECK: [0x44,0x00,0x61,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], s0
+// CHECK: [0x84,0x00,0x64,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[4:5], s[8:11], s0
+// CHECK: [0x04,0x01,0x64,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[100:101], s[8:11], s0
+// CHECK: [0x04,0x19,0x64,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 flat_scratch, s[8:11], s0
+// CHECK: [0x84,0x19,0x64,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 vcc, s[8:11], s0
+// CHECK: [0x84,0x1a,0x64,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 ttmp[14:15], s[8:11], s0
+// CHECK: [0x84,0x1e,0x64,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[12:15], s0
+// CHECK: [0x86,0x00,0x64,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[96:99], s0
+// CHECK: [0xb0,0x00,0x64,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], ttmp[12:15], s0
+// CHECK: [0xbc,0x00,0x64,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], s101
+// CHECK: [0x84,0x00,0x64,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], flat_scratch_lo
+// CHECK: [0x84,0x00,0x64,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], flat_scratch_hi
+// CHECK: [0x84,0x00,0x64,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], vcc_lo
+// CHECK: [0x84,0x00,0x64,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], vcc_hi
+// CHECK: [0x84,0x00,0x64,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], ttmp15
+// CHECK: [0x84,0x00,0x64,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], m0
+// CHECK: [0x84,0x00,0x64,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], 0x0
+// CHECK: [0x84,0x00,0x66,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx2 s[2:3], s[8:11], s0 glc
+// CHECK: [0x84,0x00,0x65,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], s0
+// CHECK: [0x04,0x01,0x68,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[8:11], s[8:11], s0
+// CHECK: [0x04,0x02,0x68,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[96:99], s[8:11], s0
+// CHECK: [0x04,0x18,0x68,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 ttmp[12:15], s[8:11], s0
+// CHECK: [0x04,0x1e,0x68,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[12:15], s0
+// CHECK: [0x06,0x01,0x68,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[96:99], s0
+// CHECK: [0x30,0x01,0x68,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], ttmp[12:15], s0
+// CHECK: [0x3c,0x01,0x68,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], s101
+// CHECK: [0x04,0x01,0x68,0xc0,0x65,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], flat_scratch_lo
+// CHECK: [0x04,0x01,0x68,0xc0,0x66,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], flat_scratch_hi
+// CHECK: [0x04,0x01,0x68,0xc0,0x67,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], vcc_lo
+// CHECK: [0x04,0x01,0x68,0xc0,0x6a,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], vcc_hi
+// CHECK: [0x04,0x01,0x68,0xc0,0x6b,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], ttmp15
+// CHECK: [0x04,0x01,0x68,0xc0,0x7b,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], m0
+// CHECK: [0x04,0x01,0x68,0xc0,0x7c,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], 0x0
+// CHECK: [0x04,0x01,0x6a,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_store_dwordx4 s[4:7], s[8:11], s0 glc
+// CHECK: [0x04,0x01,0x69,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_inv
+// CHECK: [0x00,0x00,0x80,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_wb
+// CHECK: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_inv_vol
+// CHECK: [0x00,0x00,0x88,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_wb_vol
+// CHECK: [0x00,0x00,0x8c,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime s[10:11]
+// CHECK: [0x80,0x02,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime s[12:13]
+// CHECK: [0x00,0x03,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime s[100:101]
+// CHECK: [0x00,0x19,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime flat_scratch
+// CHECK: [0x80,0x19,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime vcc
+// CHECK: [0x80,0x1a,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memtime ttmp[14:15]
+// CHECK: [0x80,0x1e,0x90,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime s[10:11]
+// CHECK: [0x80,0x02,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime s[12:13]
+// CHECK: [0x00,0x03,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime s[100:101]
+// CHECK: [0x00,0x19,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime flat_scratch
+// CHECK: [0x80,0x19,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime vcc
+// CHECK: [0x80,0x1a,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_memrealtime ttmp[14:15]
+// CHECK: [0x80,0x1e,0x94,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], s0
+// CHECK: [0x02,0x00,0x98,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x1, s[4:5], s0
+// CHECK: [0x42,0x00,0x98,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x7, s[4:5], s0
+// CHECK: [0xc2,0x01,0x98,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[6:7], s0
+// CHECK: [0x03,0x00,0x98,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[100:101], s0
+// CHECK: [0x32,0x00,0x98,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x0, flat_scratch, s0
+// CHECK: [0x33,0x00,0x98,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x0, vcc, s0
+// CHECK: [0x35,0x00,0x98,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x0, ttmp[14:15], s0
+// CHECK: [0x3d,0x00,0x98,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], s101
+// CHECK: [0x02,0x00,0x98,0xc0,0x65,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], flat_scratch_lo
+// CHECK: [0x02,0x00,0x98,0xc0,0x66,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], flat_scratch_hi
+// CHECK: [0x02,0x00,0x98,0xc0,0x67,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], vcc_lo
+// CHECK: [0x02,0x00,0x98,0xc0,0x6a,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], vcc_hi
+// CHECK: [0x02,0x00,0x98,0xc0,0x6b,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], ttmp15
+// CHECK: [0x02,0x00,0x98,0xc0,0x7b,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], m0
+// CHECK: [0x02,0x00,0x98,0xc0,0x7c,0x00,0x00,0x00]
+
+s_atc_probe 0x0, s[4:5], 0x0
+// CHECK: [0x02,0x00,0x9a,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], s0
+// CHECK: [0x04,0x00,0x9c,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x1, s[8:11], s0
+// CHECK: [0x44,0x00,0x9c,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x7, s[8:11], s0
+// CHECK: [0xc4,0x01,0x9c,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[12:15], s0
+// CHECK: [0x06,0x00,0x9c,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[96:99], s0
+// CHECK: [0x30,0x00,0x9c,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, ttmp[12:15], s0
+// CHECK: [0x3c,0x00,0x9c,0xc0,0x00,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], s101
+// CHECK: [0x04,0x00,0x9c,0xc0,0x65,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], flat_scratch_lo
+// CHECK: [0x04,0x00,0x9c,0xc0,0x66,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], flat_scratch_hi
+// CHECK: [0x04,0x00,0x9c,0xc0,0x67,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], vcc_lo
+// CHECK: [0x04,0x00,0x9c,0xc0,0x6a,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], vcc_hi
+// CHECK: [0x04,0x00,0x9c,0xc0,0x6b,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], ttmp15
+// CHECK: [0x04,0x00,0x9c,0xc0,0x7b,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], m0
+// CHECK: [0x04,0x00,0x9c,0xc0,0x7c,0x00,0x00,0x00]
+
+s_atc_probe_buffer 0x0, s[8:11], 0x0
+// CHECK: [0x04,0x00,0x9e,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard s[2:3], s0
+// CHECK: [0x01,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard s[4:5], s0
+// CHECK: [0x02,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard s[100:101], s0
+// CHECK: [0x32,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard flat_scratch, s0
+// CHECK: [0x33,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard vcc, s0
+// CHECK: [0x35,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard ttmp[14:15], s0
+// CHECK: [0x3d,0x00,0xa0,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard s[2:3], s101
+// CHECK: [0x01,0x00,0xa0,0xc0,0x65,0x00,0x00,0x00]
+
+s_dcache_discard s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x00,0xa0,0xc0,0x66,0x00,0x00,0x00]
+
+s_dcache_discard s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x00,0xa0,0xc0,0x67,0x00,0x00,0x00]
+
+s_dcache_discard s[2:3], vcc_lo
+// CHECK: [0x01,0x00,0xa0,0xc0,0x6a,0x00,0x00,0x00]
+
+s_dcache_discard s[2:3], vcc_hi
+// CHECK: [0x01,0x00,0xa0,0xc0,0x6b,0x00,0x00,0x00]
+
+s_dcache_discard s[2:3], ttmp15
+// CHECK: [0x01,0x00,0xa0,0xc0,0x7b,0x00,0x00,0x00]
+
+s_dcache_discard s[2:3], m0
+// CHECK: [0x01,0x00,0xa0,0xc0,0x7c,0x00,0x00,0x00]
+
+s_dcache_discard s[2:3], 0x0
+// CHECK: [0x01,0x00,0xa2,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[2:3], s0
+// CHECK: [0x01,0x00,0xa4,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[4:5], s0
+// CHECK: [0x02,0x00,0xa4,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[100:101], s0
+// CHECK: [0x32,0x00,0xa4,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard_x2 flat_scratch, s0
+// CHECK: [0x33,0x00,0xa4,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard_x2 vcc, s0
+// CHECK: [0x35,0x00,0xa4,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard_x2 ttmp[14:15], s0
+// CHECK: [0x3d,0x00,0xa4,0xc0,0x00,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[2:3], s101
+// CHECK: [0x01,0x00,0xa4,0xc0,0x65,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x00,0xa4,0xc0,0x66,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x00,0xa4,0xc0,0x67,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[2:3], vcc_lo
+// CHECK: [0x01,0x00,0xa4,0xc0,0x6a,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[2:3], vcc_hi
+// CHECK: [0x01,0x00,0xa4,0xc0,0x6b,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[2:3], ttmp15
+// CHECK: [0x01,0x00,0xa4,0xc0,0x7b,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[2:3], m0
+// CHECK: [0x01,0x00,0xa4,0xc0,0x7c,0x00,0x00,0x00]
+
+s_dcache_discard_x2 s[2:3], 0x0
+// CHECK: [0x01,0x00,0xa6,0xc0,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x00,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x00,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x00,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x00,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x00,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x00,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x00,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x00,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x02,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x01,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0x04,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0x04,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0x04,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0x04,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0x04,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0x04,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0x04,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0x04,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0x04,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x04,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x04,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x04,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x04,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x04,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0x04,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x04,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0x06,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0x05,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x08,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x08,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x08,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x08,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x08,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x08,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x08,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x08,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x0a,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x09,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x0c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x0c,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x0c,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x0c,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x0c,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x0c,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x0c,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x0c,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x0e,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x0d,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x10,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x10,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x10,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x10,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x10,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x10,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x10,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x10,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x12,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x11,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x14,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x14,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x14,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x14,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x14,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x14,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x14,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x14,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x16,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x15,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x18,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x18,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x18,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x18,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x18,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x18,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x18,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x18,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x1a,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x19,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x1c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x1c,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x1c,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x1c,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x1c,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x1c,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x1c,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x1c,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x1e,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x1d,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x20,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x20,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x20,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x20,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x20,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x20,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x20,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x20,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x22,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x21,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x24,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x24,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x24,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x24,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x24,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x24,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x24,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x24,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x26,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x25,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x28,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x28,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x28,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x28,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x28,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x28,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x28,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x28,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x2a,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x29,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x2c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x2c,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x2c,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x2c,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x2c,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x2c,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x2c,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x2c,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x2e,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x2d,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], s0
+// CHECK: [0x42,0x01,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s101, s[4:7], s0
+// CHECK: [0x42,0x19,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec flat_scratch_lo, s[4:7], s0
+// CHECK: [0x82,0x19,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec flat_scratch_hi, s[4:7], s0
+// CHECK: [0xc2,0x19,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec vcc_lo, s[4:7], s0
+// CHECK: [0x82,0x1a,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec vcc_hi, s[4:7], s0
+// CHECK: [0xc2,0x1a,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec ttmp15, s[4:7], s0
+// CHECK: [0xc2,0x1e,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[8:11], s0
+// CHECK: [0x44,0x01,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[96:99], s0
+// CHECK: [0x70,0x01,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, ttmp[12:15], s0
+// CHECK: [0x7c,0x01,0x30,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], s101
+// CHECK: [0x42,0x01,0x30,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], flat_scratch_lo
+// CHECK: [0x42,0x01,0x30,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], flat_scratch_hi
+// CHECK: [0x42,0x01,0x30,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], vcc_lo
+// CHECK: [0x42,0x01,0x30,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], vcc_hi
+// CHECK: [0x42,0x01,0x30,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], ttmp15
+// CHECK: [0x42,0x01,0x30,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], m0
+// CHECK: [0x42,0x01,0x30,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], 0x0
+// CHECK: [0x42,0x01,0x32,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec s5, s[4:7], s0 glc
+// CHECK: [0x42,0x01,0x31,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0x80,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0x80,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0x80,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0x80,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0x80,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0x80,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0x80,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0x80,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0x80,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x80,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x80,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x80,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x80,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x80,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0x80,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x80,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0x82,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_swap_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0x81,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], s0
+// CHECK: [0x02,0x05,0x84,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[24:27], s[4:7], s0
+// CHECK: [0x02,0x06,0x84,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[96:99], s[4:7], s0
+// CHECK: [0x02,0x18,0x84,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 ttmp[12:15], s[4:7], s0
+// CHECK: [0x02,0x1e,0x84,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[8:11], s0
+// CHECK: [0x04,0x05,0x84,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[96:99], s0
+// CHECK: [0x30,0x05,0x84,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], ttmp[12:15], s0
+// CHECK: [0x3c,0x05,0x84,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], s101
+// CHECK: [0x02,0x05,0x84,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], flat_scratch_lo
+// CHECK: [0x02,0x05,0x84,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], flat_scratch_hi
+// CHECK: [0x02,0x05,0x84,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], vcc_lo
+// CHECK: [0x02,0x05,0x84,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], vcc_hi
+// CHECK: [0x02,0x05,0x84,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], ttmp15
+// CHECK: [0x02,0x05,0x84,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], m0
+// CHECK: [0x02,0x05,0x84,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], 0x0
+// CHECK: [0x02,0x05,0x86,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_cmpswap_x2 s[20:23], s[4:7], s0 glc
+// CHECK: [0x02,0x05,0x85,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0x88,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0x88,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0x88,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0x88,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0x88,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0x88,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0x88,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0x88,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0x88,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x88,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x88,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x88,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x88,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x88,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0x88,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x88,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0x8a,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_add_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0x89,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0x8c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0x8c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0x8c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0x8c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0x8c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0x8c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0x8c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0x8c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0x8c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x8c,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x8c,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x8c,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x8c,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x8c,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0x8c,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x8c,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0x8e,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_sub_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0x8d,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0x90,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0x90,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0x90,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0x90,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0x90,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0x90,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0x90,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0x90,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0x90,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x90,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x90,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x90,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x90,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x90,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0x90,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x90,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0x92,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smin_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0x91,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0x94,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0x94,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0x94,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0x94,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0x94,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0x94,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0x94,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0x94,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0x94,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x94,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x94,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x94,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x94,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x94,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0x94,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x94,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0x96,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umin_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0x95,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0x98,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0x98,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0x98,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0x98,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0x98,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0x98,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0x98,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0x98,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0x98,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x98,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x98,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x98,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x98,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x98,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0x98,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x98,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0x9a,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_smax_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0x99,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0x9c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0x9c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0x9c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0x9c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0x9c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0x9c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0x9c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0x9c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0x9c,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0x9c,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0x9c,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0x9c,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0x9c,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0x9c,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0x9c,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0x9c,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0x9e,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_umax_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0x9d,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0xa0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0xa0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0xa0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0xa0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0xa0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0xa0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0xa0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0xa0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0xa0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0xa0,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0xa0,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0xa0,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0xa0,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0xa0,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0xa0,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0xa0,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0xa2,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_and_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0xa1,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0xa4,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0xa4,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0xa4,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0xa4,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0xa4,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0xa4,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0xa4,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0xa4,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0xa4,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0xa4,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0xa4,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0xa4,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0xa4,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0xa4,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0xa4,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0xa4,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0xa6,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_or_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0xa5,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0xa8,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0xa8,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0xa8,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0xa8,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0xa8,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0xa8,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0xa8,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0xa8,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0xa8,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0xa8,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0xa8,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0xa8,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0xa8,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0xa8,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0xa8,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0xa8,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0xaa,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_xor_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0xa9,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0xac,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0xac,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0xac,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0xac,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0xac,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0xac,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0xac,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0xac,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0xac,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0xac,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0xac,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0xac,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0xac,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0xac,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0xac,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0xac,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0xae,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_inc_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0xad,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], s0
+// CHECK: [0x82,0x02,0xb0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[12:13], s[4:7], s0
+// CHECK: [0x02,0x03,0xb0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[100:101], s[4:7], s0
+// CHECK: [0x02,0x19,0xb0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 flat_scratch, s[4:7], s0
+// CHECK: [0x82,0x19,0xb0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 vcc, s[4:7], s0
+// CHECK: [0x82,0x1a,0xb0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 ttmp[14:15], s[4:7], s0
+// CHECK: [0x82,0x1e,0xb0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[8:11], s0
+// CHECK: [0x84,0x02,0xb0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[96:99], s0
+// CHECK: [0xb0,0x02,0xb0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], ttmp[12:15], s0
+// CHECK: [0xbc,0x02,0xb0,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], s101
+// CHECK: [0x82,0x02,0xb0,0xc1,0x65,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], flat_scratch_lo
+// CHECK: [0x82,0x02,0xb0,0xc1,0x66,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], flat_scratch_hi
+// CHECK: [0x82,0x02,0xb0,0xc1,0x67,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], vcc_lo
+// CHECK: [0x82,0x02,0xb0,0xc1,0x6a,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], vcc_hi
+// CHECK: [0x82,0x02,0xb0,0xc1,0x6b,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], ttmp15
+// CHECK: [0x82,0x02,0xb0,0xc1,0x7b,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], m0
+// CHECK: [0x82,0x02,0xb0,0xc1,0x7c,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], 0x0
+// CHECK: [0x82,0x02,0xb2,0xc1,0x00,0x00,0x00,0x00]
+
+s_buffer_atomic_dec_x2 s[10:11], s[4:7], s0 glc
+// CHECK: [0x82,0x02,0xb1,0xc1,0x00,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap s5, vcc, s0
+// CHECK: [0x75,0x01,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x00,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x00,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x00,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x00,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x00,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x00,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x00,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x00,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x02,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x01,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x04,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x04,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x04,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x04,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x04,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x04,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x04,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x04,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x06,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x05,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add s5, vcc, s0
+// CHECK: [0x75,0x01,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x08,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x08,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x08,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x08,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x08,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x08,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x08,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x08,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x0a,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x09,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub s5, vcc, s0
+// CHECK: [0x75,0x01,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x0c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x0c,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x0c,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x0c,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x0c,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x0c,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x0c,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x0c,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x0e,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x0d,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin s5, vcc, s0
+// CHECK: [0x75,0x01,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x10,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x10,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x10,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x10,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x10,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x10,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x10,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x10,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x12,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x11,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin s5, vcc, s0
+// CHECK: [0x75,0x01,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x14,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x14,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x14,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x14,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x14,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x14,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x14,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x14,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x16,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x15,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax s5, vcc, s0
+// CHECK: [0x75,0x01,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x18,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x18,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x18,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x18,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x18,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x18,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x18,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x18,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x1a,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x19,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax s5, vcc, s0
+// CHECK: [0x75,0x01,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x1c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x1c,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x1c,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x1c,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x1c,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x1c,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x1c,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x1c,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x1e,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x1d,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and s5, vcc, s0
+// CHECK: [0x75,0x01,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x20,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x20,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x20,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x20,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x20,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x20,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x20,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x20,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x22,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x21,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or s5, vcc, s0
+// CHECK: [0x75,0x01,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x24,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x24,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x24,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x24,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x24,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x24,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x24,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x24,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x26,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x25,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor s5, vcc, s0
+// CHECK: [0x75,0x01,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x28,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x28,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x28,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x28,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x28,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x28,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x28,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x28,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x2a,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x29,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc s5, vcc, s0
+// CHECK: [0x75,0x01,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x2c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x2c,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x2c,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x2c,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x2c,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x2c,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x2c,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x2c,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x2e,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x2d,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], s0
+// CHECK: [0x41,0x01,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec s101, s[2:3], s0
+// CHECK: [0x41,0x19,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec flat_scratch_lo, s[2:3], s0
+// CHECK: [0x81,0x19,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec flat_scratch_hi, s[2:3], s0
+// CHECK: [0xc1,0x19,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec vcc_lo, s[2:3], s0
+// CHECK: [0x81,0x1a,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec vcc_hi, s[2:3], s0
+// CHECK: [0xc1,0x1a,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec ttmp15, s[2:3], s0
+// CHECK: [0xc1,0x1e,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[4:5], s0
+// CHECK: [0x42,0x01,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[100:101], s0
+// CHECK: [0x72,0x01,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec s5, flat_scratch, s0
+// CHECK: [0x73,0x01,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec s5, vcc, s0
+// CHECK: [0x75,0x01,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec s5, ttmp[14:15], s0
+// CHECK: [0x7d,0x01,0x30,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], s101
+// CHECK: [0x41,0x01,0x30,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], flat_scratch_lo
+// CHECK: [0x41,0x01,0x30,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], flat_scratch_hi
+// CHECK: [0x41,0x01,0x30,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], vcc_lo
+// CHECK: [0x41,0x01,0x30,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], vcc_hi
+// CHECK: [0x41,0x01,0x30,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], ttmp15
+// CHECK: [0x41,0x01,0x30,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], m0
+// CHECK: [0x41,0x01,0x30,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], 0x0
+// CHECK: [0x41,0x01,0x32,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec s5, s[2:3], s0 glc
+// CHECK: [0x41,0x01,0x31,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x80,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x80,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x80,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x80,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x80,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x80,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x80,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x80,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x82,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_swap_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x81,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], s0
+// CHECK: [0x01,0x05,0x84,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[24:27], s[2:3], s0
+// CHECK: [0x01,0x06,0x84,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[96:99], s[2:3], s0
+// CHECK: [0x01,0x18,0x84,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 ttmp[12:15], s[2:3], s0
+// CHECK: [0x01,0x1e,0x84,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[4:5], s0
+// CHECK: [0x02,0x05,0x84,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[100:101], s0
+// CHECK: [0x32,0x05,0x84,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], flat_scratch, s0
+// CHECK: [0x33,0x05,0x84,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], vcc, s0
+// CHECK: [0x35,0x05,0x84,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], ttmp[14:15], s0
+// CHECK: [0x3d,0x05,0x84,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], s101
+// CHECK: [0x01,0x05,0x84,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], flat_scratch_lo
+// CHECK: [0x01,0x05,0x84,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], flat_scratch_hi
+// CHECK: [0x01,0x05,0x84,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], vcc_lo
+// CHECK: [0x01,0x05,0x84,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], vcc_hi
+// CHECK: [0x01,0x05,0x84,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], ttmp15
+// CHECK: [0x01,0x05,0x84,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], m0
+// CHECK: [0x01,0x05,0x84,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], 0x0
+// CHECK: [0x01,0x05,0x86,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_cmpswap_x2 s[20:23], s[2:3], s0 glc
+// CHECK: [0x01,0x05,0x85,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x88,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x88,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x88,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x88,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x88,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x88,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x88,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x88,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x8a,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_add_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x89,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x8c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x8c,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x8c,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x8c,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x8c,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x8c,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x8c,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x8c,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x8e,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_sub_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x8d,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x90,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x90,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x90,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x90,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x90,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x90,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x90,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x90,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x92,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smin_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x91,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x94,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x94,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x94,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x94,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x94,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x94,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x94,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x94,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x96,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umin_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x95,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x98,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x98,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x98,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x98,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x98,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x98,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x98,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x98,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x9a,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_smax_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x99,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0x9c,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0x9c,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0x9c,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0x9c,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0x9c,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0x9c,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0x9c,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0x9c,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0x9e,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_umax_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0x9d,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0xa0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0xa0,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0xa0,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0xa0,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0xa0,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0xa0,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0xa0,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0xa0,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0xa2,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_and_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0xa1,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0xa4,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0xa4,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0xa4,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0xa4,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0xa4,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0xa4,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0xa4,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0xa4,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0xa6,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_or_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0xa5,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0xa8,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0xa8,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0xa8,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0xa8,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0xa8,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0xa8,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0xa8,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0xa8,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0xaa,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_xor_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0xa9,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0xac,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0xac,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0xac,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0xac,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0xac,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0xac,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0xac,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0xac,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0xae,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_inc_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0xad,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], s0
+// CHECK: [0x81,0x02,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[12:13], s[2:3], s0
+// CHECK: [0x01,0x03,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[100:101], s[2:3], s0
+// CHECK: [0x01,0x19,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 flat_scratch, s[2:3], s0
+// CHECK: [0x81,0x19,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 vcc, s[2:3], s0
+// CHECK: [0x81,0x1a,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 ttmp[14:15], s[2:3], s0
+// CHECK: [0x81,0x1e,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[4:5], s0
+// CHECK: [0x82,0x02,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[100:101], s0
+// CHECK: [0xb2,0x02,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], flat_scratch, s0
+// CHECK: [0xb3,0x02,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], vcc, s0
+// CHECK: [0xb5,0x02,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], ttmp[14:15], s0
+// CHECK: [0xbd,0x02,0xb0,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], s101
+// CHECK: [0x81,0x02,0xb0,0xc2,0x65,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x81,0x02,0xb0,0xc2,0x66,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x81,0x02,0xb0,0xc2,0x67,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x81,0x02,0xb0,0xc2,0x6a,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x81,0x02,0xb0,0xc2,0x6b,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], ttmp15
+// CHECK: [0x81,0x02,0xb0,0xc2,0x7b,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], m0
+// CHECK: [0x81,0x02,0xb0,0xc2,0x7c,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], 0x0
+// CHECK: [0x81,0x02,0xb2,0xc2,0x00,0x00,0x00,0x00]
+
+s_atomic_dec_x2 s[10:11], s[2:3], s0 glc
+// CHECK: [0x81,0x02,0xb1,0xc2,0x00,0x00,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sop1.s b/llvm/test/MC/AMDGPU/gfx9_asm_sop1.s
new file mode 100644
index 0000000000000..d787c88f61689
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sop1.s
@@ -0,0 +1,3634 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+s_mov_b32 s5, s1
+// CHECK: [0x01,0x00,0x85,0xbe]
+
+s_mov_b32 s101, s1
+// CHECK: [0x01,0x00,0xe5,0xbe]
+
+s_mov_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x00,0xe6,0xbe]
+
+s_mov_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x00,0xe7,0xbe]
+
+s_mov_b32 vcc_lo, s1
+// CHECK: [0x01,0x00,0xea,0xbe]
+
+s_mov_b32 vcc_hi, s1
+// CHECK: [0x01,0x00,0xeb,0xbe]
+
+s_mov_b32 ttmp15, s1
+// CHECK: [0x01,0x00,0xfb,0xbe]
+
+s_mov_b32 m0, s1
+// CHECK: [0x01,0x00,0xfc,0xbe]
+
+s_mov_b32 exec_lo, s1
+// CHECK: [0x01,0x00,0xfe,0xbe]
+
+s_mov_b32 exec_hi, s1
+// CHECK: [0x01,0x00,0xff,0xbe]
+
+s_mov_b32 s5, s101
+// CHECK: [0x65,0x00,0x85,0xbe]
+
+s_mov_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x00,0x85,0xbe]
+
+s_mov_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x00,0x85,0xbe]
+
+s_mov_b32 s5, vcc_lo
+// CHECK: [0x6a,0x00,0x85,0xbe]
+
+s_mov_b32 s5, vcc_hi
+// CHECK: [0x6b,0x00,0x85,0xbe]
+
+s_mov_b32 s5, ttmp15
+// CHECK: [0x7b,0x00,0x85,0xbe]
+
+s_mov_b32 s5, m0
+// CHECK: [0x7c,0x00,0x85,0xbe]
+
+s_mov_b32 s5, exec_lo
+// CHECK: [0x7e,0x00,0x85,0xbe]
+
+s_mov_b32 s5, exec_hi
+// CHECK: [0x7f,0x00,0x85,0xbe]
+
+s_mov_b32 s5, 0
+// CHECK: [0x80,0x00,0x85,0xbe]
+
+s_mov_b32 s5, -1
+// CHECK: [0xc1,0x00,0x85,0xbe]
+
+s_mov_b32 s5, 0.5
+// CHECK: [0xf0,0x00,0x85,0xbe]
+
+s_mov_b32 s5, -4.0
+// CHECK: [0xf7,0x00,0x85,0xbe]
+
+s_mov_b32 s5, src_vccz
+// CHECK: [0xfb,0x00,0x85,0xbe]
+
+s_mov_b32 s5, src_execz
+// CHECK: [0xfc,0x00,0x85,0xbe]
+
+s_mov_b32 s5, src_scc
+// CHECK: [0xfd,0x00,0x85,0xbe]
+
+s_mov_b32 s5, 0xaf123456
+// CHECK: [0xff,0x00,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_mov_b32 s5, 0x3f717273
+// CHECK: [0xff,0x00,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_mov_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x01,0x8a,0xbe]
+
+s_mov_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x01,0x8c,0xbe]
+
+s_mov_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x01,0xe4,0xbe]
+
+s_mov_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x01,0xe6,0xbe]
+
+s_mov_b64 vcc, s[2:3]
+// CHECK: [0x02,0x01,0xea,0xbe]
+
+s_mov_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x01,0xfa,0xbe]
+
+s_mov_b64 exec, s[2:3]
+// CHECK: [0x02,0x01,0xfe,0xbe]
+
+s_mov_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], vcc
+// CHECK: [0x6a,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], exec
+// CHECK: [0x7e,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], 0
+// CHECK: [0x80,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], -1
+// CHECK: [0xc1,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x01,0x8a,0xbe]
+
+s_mov_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x01,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_mov_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x01,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cmov_b32 s5, s1
+// CHECK: [0x01,0x02,0x85,0xbe]
+
+s_cmov_b32 s101, s1
+// CHECK: [0x01,0x02,0xe5,0xbe]
+
+s_cmov_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x02,0xe6,0xbe]
+
+s_cmov_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x02,0xe7,0xbe]
+
+s_cmov_b32 vcc_lo, s1
+// CHECK: [0x01,0x02,0xea,0xbe]
+
+s_cmov_b32 vcc_hi, s1
+// CHECK: [0x01,0x02,0xeb,0xbe]
+
+s_cmov_b32 ttmp15, s1
+// CHECK: [0x01,0x02,0xfb,0xbe]
+
+s_cmov_b32 m0, s1
+// CHECK: [0x01,0x02,0xfc,0xbe]
+
+s_cmov_b32 exec_lo, s1
+// CHECK: [0x01,0x02,0xfe,0xbe]
+
+s_cmov_b32 exec_hi, s1
+// CHECK: [0x01,0x02,0xff,0xbe]
+
+s_cmov_b32 s5, s101
+// CHECK: [0x65,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, vcc_lo
+// CHECK: [0x6a,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, vcc_hi
+// CHECK: [0x6b,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, ttmp15
+// CHECK: [0x7b,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, m0
+// CHECK: [0x7c,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, exec_lo
+// CHECK: [0x7e,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, exec_hi
+// CHECK: [0x7f,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, 0
+// CHECK: [0x80,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, -1
+// CHECK: [0xc1,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, 0.5
+// CHECK: [0xf0,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, -4.0
+// CHECK: [0xf7,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, src_vccz
+// CHECK: [0xfb,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, src_execz
+// CHECK: [0xfc,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, src_scc
+// CHECK: [0xfd,0x02,0x85,0xbe]
+
+s_cmov_b32 s5, 0xaf123456
+// CHECK: [0xff,0x02,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_cmov_b32 s5, 0x3f717273
+// CHECK: [0xff,0x02,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cmov_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x03,0x8c,0xbe]
+
+s_cmov_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x03,0xe4,0xbe]
+
+s_cmov_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x03,0xe6,0xbe]
+
+s_cmov_b64 vcc, s[2:3]
+// CHECK: [0x02,0x03,0xea,0xbe]
+
+s_cmov_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x03,0xfa,0xbe]
+
+s_cmov_b64 exec, s[2:3]
+// CHECK: [0x02,0x03,0xfe,0xbe]
+
+s_cmov_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], vcc
+// CHECK: [0x6a,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], exec
+// CHECK: [0x7e,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], 0
+// CHECK: [0x80,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], -1
+// CHECK: [0xc1,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x03,0x8a,0xbe]
+
+s_cmov_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x03,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_cmov_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x03,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_not_b32 s5, s1
+// CHECK: [0x01,0x04,0x85,0xbe]
+
+s_not_b32 s101, s1
+// CHECK: [0x01,0x04,0xe5,0xbe]
+
+s_not_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x04,0xe6,0xbe]
+
+s_not_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x04,0xe7,0xbe]
+
+s_not_b32 vcc_lo, s1
+// CHECK: [0x01,0x04,0xea,0xbe]
+
+s_not_b32 vcc_hi, s1
+// CHECK: [0x01,0x04,0xeb,0xbe]
+
+s_not_b32 ttmp15, s1
+// CHECK: [0x01,0x04,0xfb,0xbe]
+
+s_not_b32 m0, s1
+// CHECK: [0x01,0x04,0xfc,0xbe]
+
+s_not_b32 exec_lo, s1
+// CHECK: [0x01,0x04,0xfe,0xbe]
+
+s_not_b32 exec_hi, s1
+// CHECK: [0x01,0x04,0xff,0xbe]
+
+s_not_b32 s5, s101
+// CHECK: [0x65,0x04,0x85,0xbe]
+
+s_not_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x04,0x85,0xbe]
+
+s_not_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x04,0x85,0xbe]
+
+s_not_b32 s5, vcc_lo
+// CHECK: [0x6a,0x04,0x85,0xbe]
+
+s_not_b32 s5, vcc_hi
+// CHECK: [0x6b,0x04,0x85,0xbe]
+
+s_not_b32 s5, ttmp15
+// CHECK: [0x7b,0x04,0x85,0xbe]
+
+s_not_b32 s5, m0
+// CHECK: [0x7c,0x04,0x85,0xbe]
+
+s_not_b32 s5, exec_lo
+// CHECK: [0x7e,0x04,0x85,0xbe]
+
+s_not_b32 s5, exec_hi
+// CHECK: [0x7f,0x04,0x85,0xbe]
+
+s_not_b32 s5, 0
+// CHECK: [0x80,0x04,0x85,0xbe]
+
+s_not_b32 s5, -1
+// CHECK: [0xc1,0x04,0x85,0xbe]
+
+s_not_b32 s5, 0.5
+// CHECK: [0xf0,0x04,0x85,0xbe]
+
+s_not_b32 s5, -4.0
+// CHECK: [0xf7,0x04,0x85,0xbe]
+
+s_not_b32 s5, src_vccz
+// CHECK: [0xfb,0x04,0x85,0xbe]
+
+s_not_b32 s5, src_execz
+// CHECK: [0xfc,0x04,0x85,0xbe]
+
+s_not_b32 s5, src_scc
+// CHECK: [0xfd,0x04,0x85,0xbe]
+
+s_not_b32 s5, 0xaf123456
+// CHECK: [0xff,0x04,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_not_b32 s5, 0x3f717273
+// CHECK: [0xff,0x04,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_not_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x05,0x8a,0xbe]
+
+s_not_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x05,0x8c,0xbe]
+
+s_not_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x05,0xe4,0xbe]
+
+s_not_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x05,0xe6,0xbe]
+
+s_not_b64 vcc, s[2:3]
+// CHECK: [0x02,0x05,0xea,0xbe]
+
+s_not_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x05,0xfa,0xbe]
+
+s_not_b64 exec, s[2:3]
+// CHECK: [0x02,0x05,0xfe,0xbe]
+
+s_not_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], vcc
+// CHECK: [0x6a,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], exec
+// CHECK: [0x7e,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], 0
+// CHECK: [0x80,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], -1
+// CHECK: [0xc1,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x05,0x8a,0xbe]
+
+s_not_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x05,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_not_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x05,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_wqm_b32 s5, s1
+// CHECK: [0x01,0x06,0x85,0xbe]
+
+s_wqm_b32 s101, s1
+// CHECK: [0x01,0x06,0xe5,0xbe]
+
+s_wqm_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x06,0xe6,0xbe]
+
+s_wqm_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x06,0xe7,0xbe]
+
+s_wqm_b32 vcc_lo, s1
+// CHECK: [0x01,0x06,0xea,0xbe]
+
+s_wqm_b32 vcc_hi, s1
+// CHECK: [0x01,0x06,0xeb,0xbe]
+
+s_wqm_b32 ttmp15, s1
+// CHECK: [0x01,0x06,0xfb,0xbe]
+
+s_wqm_b32 m0, s1
+// CHECK: [0x01,0x06,0xfc,0xbe]
+
+s_wqm_b32 exec_lo, s1
+// CHECK: [0x01,0x06,0xfe,0xbe]
+
+s_wqm_b32 exec_hi, s1
+// CHECK: [0x01,0x06,0xff,0xbe]
+
+s_wqm_b32 s5, s101
+// CHECK: [0x65,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, vcc_lo
+// CHECK: [0x6a,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, vcc_hi
+// CHECK: [0x6b,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, ttmp15
+// CHECK: [0x7b,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, m0
+// CHECK: [0x7c,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, exec_lo
+// CHECK: [0x7e,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, exec_hi
+// CHECK: [0x7f,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, 0
+// CHECK: [0x80,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, -1
+// CHECK: [0xc1,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, 0.5
+// CHECK: [0xf0,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, -4.0
+// CHECK: [0xf7,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, src_vccz
+// CHECK: [0xfb,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, src_execz
+// CHECK: [0xfc,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, src_scc
+// CHECK: [0xfd,0x06,0x85,0xbe]
+
+s_wqm_b32 s5, 0xaf123456
+// CHECK: [0xff,0x06,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_wqm_b32 s5, 0x3f717273
+// CHECK: [0xff,0x06,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_wqm_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x07,0x8c,0xbe]
+
+s_wqm_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x07,0xe4,0xbe]
+
+s_wqm_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x07,0xe6,0xbe]
+
+s_wqm_b64 vcc, s[2:3]
+// CHECK: [0x02,0x07,0xea,0xbe]
+
+s_wqm_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x07,0xfa,0xbe]
+
+s_wqm_b64 exec, s[2:3]
+// CHECK: [0x02,0x07,0xfe,0xbe]
+
+s_wqm_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], vcc
+// CHECK: [0x6a,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], exec
+// CHECK: [0x7e,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], 0
+// CHECK: [0x80,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], -1
+// CHECK: [0xc1,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x07,0x8a,0xbe]
+
+s_wqm_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x07,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_wqm_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x07,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_brev_b32 s5, s1
+// CHECK: [0x01,0x08,0x85,0xbe]
+
+s_brev_b32 s101, s1
+// CHECK: [0x01,0x08,0xe5,0xbe]
+
+s_brev_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x08,0xe6,0xbe]
+
+s_brev_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x08,0xe7,0xbe]
+
+s_brev_b32 vcc_lo, s1
+// CHECK: [0x01,0x08,0xea,0xbe]
+
+s_brev_b32 vcc_hi, s1
+// CHECK: [0x01,0x08,0xeb,0xbe]
+
+s_brev_b32 ttmp15, s1
+// CHECK: [0x01,0x08,0xfb,0xbe]
+
+s_brev_b32 m0, s1
+// CHECK: [0x01,0x08,0xfc,0xbe]
+
+s_brev_b32 exec_lo, s1
+// CHECK: [0x01,0x08,0xfe,0xbe]
+
+s_brev_b32 exec_hi, s1
+// CHECK: [0x01,0x08,0xff,0xbe]
+
+s_brev_b32 s5, s101
+// CHECK: [0x65,0x08,0x85,0xbe]
+
+s_brev_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x08,0x85,0xbe]
+
+s_brev_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x08,0x85,0xbe]
+
+s_brev_b32 s5, vcc_lo
+// CHECK: [0x6a,0x08,0x85,0xbe]
+
+s_brev_b32 s5, vcc_hi
+// CHECK: [0x6b,0x08,0x85,0xbe]
+
+s_brev_b32 s5, ttmp15
+// CHECK: [0x7b,0x08,0x85,0xbe]
+
+s_brev_b32 s5, m0
+// CHECK: [0x7c,0x08,0x85,0xbe]
+
+s_brev_b32 s5, exec_lo
+// CHECK: [0x7e,0x08,0x85,0xbe]
+
+s_brev_b32 s5, exec_hi
+// CHECK: [0x7f,0x08,0x85,0xbe]
+
+s_brev_b32 s5, 0
+// CHECK: [0x80,0x08,0x85,0xbe]
+
+s_brev_b32 s5, -1
+// CHECK: [0xc1,0x08,0x85,0xbe]
+
+s_brev_b32 s5, 0.5
+// CHECK: [0xf0,0x08,0x85,0xbe]
+
+s_brev_b32 s5, -4.0
+// CHECK: [0xf7,0x08,0x85,0xbe]
+
+s_brev_b32 s5, src_vccz
+// CHECK: [0xfb,0x08,0x85,0xbe]
+
+s_brev_b32 s5, src_execz
+// CHECK: [0xfc,0x08,0x85,0xbe]
+
+s_brev_b32 s5, src_scc
+// CHECK: [0xfd,0x08,0x85,0xbe]
+
+s_brev_b32 s5, 0xaf123456
+// CHECK: [0xff,0x08,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_brev_b32 s5, 0x3f717273
+// CHECK: [0xff,0x08,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_brev_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x09,0x8a,0xbe]
+
+s_brev_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x09,0x8c,0xbe]
+
+s_brev_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x09,0xe4,0xbe]
+
+s_brev_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x09,0xe6,0xbe]
+
+s_brev_b64 vcc, s[2:3]
+// CHECK: [0x02,0x09,0xea,0xbe]
+
+s_brev_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x09,0xfa,0xbe]
+
+s_brev_b64 exec, s[2:3]
+// CHECK: [0x02,0x09,0xfe,0xbe]
+
+s_brev_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], vcc
+// CHECK: [0x6a,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], exec
+// CHECK: [0x7e,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], 0
+// CHECK: [0x80,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], -1
+// CHECK: [0xc1,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x09,0x8a,0xbe]
+
+s_brev_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x09,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_brev_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x09,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt0_i32_b32 s5, s1
+// CHECK: [0x01,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s101, s1
+// CHECK: [0x01,0x0a,0xe5,0xbe]
+
+s_bcnt0_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x0a,0xe6,0xbe]
+
+s_bcnt0_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x0a,0xe7,0xbe]
+
+s_bcnt0_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x0a,0xea,0xbe]
+
+s_bcnt0_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x0a,0xeb,0xbe]
+
+s_bcnt0_i32_b32 ttmp15, s1
+// CHECK: [0x01,0x0a,0xfb,0xbe]
+
+s_bcnt0_i32_b32 m0, s1
+// CHECK: [0x01,0x0a,0xfc,0xbe]
+
+s_bcnt0_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x0a,0xfe,0xbe]
+
+s_bcnt0_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x0a,0xff,0xbe]
+
+s_bcnt0_i32_b32 s5, s101
+// CHECK: [0x65,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, ttmp15
+// CHECK: [0x7b,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, m0
+// CHECK: [0x7c,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, 0
+// CHECK: [0x80,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, -1
+// CHECK: [0xc1,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x0a,0x85,0xbe]
+
+s_bcnt0_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x0a,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt0_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x0a,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt0_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x0b,0xe5,0xbe]
+
+s_bcnt0_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x0b,0xe6,0xbe]
+
+s_bcnt0_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x0b,0xe7,0xbe]
+
+s_bcnt0_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x0b,0xea,0xbe]
+
+s_bcnt0_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x0b,0xeb,0xbe]
+
+s_bcnt0_i32_b64 ttmp15, s[2:3]
+// CHECK: [0x02,0x0b,0xfb,0xbe]
+
+s_bcnt0_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x0b,0xfc,0xbe]
+
+s_bcnt0_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x0b,0xfe,0xbe]
+
+s_bcnt0_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x0b,0xff,0xbe]
+
+s_bcnt0_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, vcc
+// CHECK: [0x6a,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, ttmp[14:15]
+// CHECK: [0x7a,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, exec
+// CHECK: [0x7e,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, 0
+// CHECK: [0x80,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, -1
+// CHECK: [0xc1,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x0b,0x85,0xbe]
+
+s_bcnt0_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x0b,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt0_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x0b,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt1_i32_b32 s5, s1
+// CHECK: [0x01,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s101, s1
+// CHECK: [0x01,0x0c,0xe5,0xbe]
+
+s_bcnt1_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x0c,0xe6,0xbe]
+
+s_bcnt1_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x0c,0xe7,0xbe]
+
+s_bcnt1_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x0c,0xea,0xbe]
+
+s_bcnt1_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x0c,0xeb,0xbe]
+
+s_bcnt1_i32_b32 ttmp15, s1
+// CHECK: [0x01,0x0c,0xfb,0xbe]
+
+s_bcnt1_i32_b32 m0, s1
+// CHECK: [0x01,0x0c,0xfc,0xbe]
+
+s_bcnt1_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x0c,0xfe,0xbe]
+
+s_bcnt1_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x0c,0xff,0xbe]
+
+s_bcnt1_i32_b32 s5, s101
+// CHECK: [0x65,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, ttmp15
+// CHECK: [0x7b,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, m0
+// CHECK: [0x7c,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, 0
+// CHECK: [0x80,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, -1
+// CHECK: [0xc1,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x0c,0x85,0xbe]
+
+s_bcnt1_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x0c,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt1_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x0c,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bcnt1_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x0d,0xe5,0xbe]
+
+s_bcnt1_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x0d,0xe6,0xbe]
+
+s_bcnt1_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x0d,0xe7,0xbe]
+
+s_bcnt1_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x0d,0xea,0xbe]
+
+s_bcnt1_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x0d,0xeb,0xbe]
+
+s_bcnt1_i32_b64 ttmp15, s[2:3]
+// CHECK: [0x02,0x0d,0xfb,0xbe]
+
+s_bcnt1_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x0d,0xfc,0xbe]
+
+s_bcnt1_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x0d,0xfe,0xbe]
+
+s_bcnt1_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x0d,0xff,0xbe]
+
+s_bcnt1_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, vcc
+// CHECK: [0x6a,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, ttmp[14:15]
+// CHECK: [0x7a,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, exec
+// CHECK: [0x7e,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, 0
+// CHECK: [0x80,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, -1
+// CHECK: [0xc1,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x0d,0x85,0xbe]
+
+s_bcnt1_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x0d,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bcnt1_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x0d,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff0_i32_b32 s5, s1
+// CHECK: [0x01,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s101, s1
+// CHECK: [0x01,0x0e,0xe5,0xbe]
+
+s_ff0_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x0e,0xe6,0xbe]
+
+s_ff0_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x0e,0xe7,0xbe]
+
+s_ff0_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x0e,0xea,0xbe]
+
+s_ff0_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x0e,0xeb,0xbe]
+
+s_ff0_i32_b32 ttmp15, s1
+// CHECK: [0x01,0x0e,0xfb,0xbe]
+
+s_ff0_i32_b32 m0, s1
+// CHECK: [0x01,0x0e,0xfc,0xbe]
+
+s_ff0_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x0e,0xfe,0xbe]
+
+s_ff0_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x0e,0xff,0xbe]
+
+s_ff0_i32_b32 s5, s101
+// CHECK: [0x65,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, ttmp15
+// CHECK: [0x7b,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, m0
+// CHECK: [0x7c,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, 0
+// CHECK: [0x80,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, -1
+// CHECK: [0xc1,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x0e,0x85,0xbe]
+
+s_ff0_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x0e,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff0_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x0e,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff0_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x0f,0xe5,0xbe]
+
+s_ff0_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x0f,0xe6,0xbe]
+
+s_ff0_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x0f,0xe7,0xbe]
+
+s_ff0_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x0f,0xea,0xbe]
+
+s_ff0_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x0f,0xeb,0xbe]
+
+s_ff0_i32_b64 ttmp15, s[2:3]
+// CHECK: [0x02,0x0f,0xfb,0xbe]
+
+s_ff0_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x0f,0xfc,0xbe]
+
+s_ff0_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x0f,0xfe,0xbe]
+
+s_ff0_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x0f,0xff,0xbe]
+
+s_ff0_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, vcc
+// CHECK: [0x6a,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, ttmp[14:15]
+// CHECK: [0x7a,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, exec
+// CHECK: [0x7e,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, 0
+// CHECK: [0x80,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, -1
+// CHECK: [0xc1,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x0f,0x85,0xbe]
+
+s_ff0_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x0f,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff0_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x0f,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff1_i32_b32 s5, s1
+// CHECK: [0x01,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s101, s1
+// CHECK: [0x01,0x10,0xe5,0xbe]
+
+s_ff1_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x10,0xe6,0xbe]
+
+s_ff1_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x10,0xe7,0xbe]
+
+s_ff1_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x10,0xea,0xbe]
+
+s_ff1_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x10,0xeb,0xbe]
+
+s_ff1_i32_b32 ttmp15, s1
+// CHECK: [0x01,0x10,0xfb,0xbe]
+
+s_ff1_i32_b32 m0, s1
+// CHECK: [0x01,0x10,0xfc,0xbe]
+
+s_ff1_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x10,0xfe,0xbe]
+
+s_ff1_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x10,0xff,0xbe]
+
+s_ff1_i32_b32 s5, s101
+// CHECK: [0x65,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, ttmp15
+// CHECK: [0x7b,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, m0
+// CHECK: [0x7c,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, 0
+// CHECK: [0x80,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, -1
+// CHECK: [0xc1,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x10,0x85,0xbe]
+
+s_ff1_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x10,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff1_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x10,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_ff1_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x11,0xe5,0xbe]
+
+s_ff1_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x11,0xe6,0xbe]
+
+s_ff1_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x11,0xe7,0xbe]
+
+s_ff1_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x11,0xea,0xbe]
+
+s_ff1_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x11,0xeb,0xbe]
+
+s_ff1_i32_b64 ttmp15, s[2:3]
+// CHECK: [0x02,0x11,0xfb,0xbe]
+
+s_ff1_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x11,0xfc,0xbe]
+
+s_ff1_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x11,0xfe,0xbe]
+
+s_ff1_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x11,0xff,0xbe]
+
+s_ff1_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, vcc
+// CHECK: [0x6a,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, ttmp[14:15]
+// CHECK: [0x7a,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, exec
+// CHECK: [0x7e,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, 0
+// CHECK: [0x80,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, -1
+// CHECK: [0xc1,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x11,0x85,0xbe]
+
+s_ff1_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x11,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_ff1_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x11,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_b32 s5, s1
+// CHECK: [0x01,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s101, s1
+// CHECK: [0x01,0x12,0xe5,0xbe]
+
+s_flbit_i32_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x12,0xe6,0xbe]
+
+s_flbit_i32_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x12,0xe7,0xbe]
+
+s_flbit_i32_b32 vcc_lo, s1
+// CHECK: [0x01,0x12,0xea,0xbe]
+
+s_flbit_i32_b32 vcc_hi, s1
+// CHECK: [0x01,0x12,0xeb,0xbe]
+
+s_flbit_i32_b32 ttmp15, s1
+// CHECK: [0x01,0x12,0xfb,0xbe]
+
+s_flbit_i32_b32 m0, s1
+// CHECK: [0x01,0x12,0xfc,0xbe]
+
+s_flbit_i32_b32 exec_lo, s1
+// CHECK: [0x01,0x12,0xfe,0xbe]
+
+s_flbit_i32_b32 exec_hi, s1
+// CHECK: [0x01,0x12,0xff,0xbe]
+
+s_flbit_i32_b32 s5, s101
+// CHECK: [0x65,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, vcc_lo
+// CHECK: [0x6a,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, vcc_hi
+// CHECK: [0x6b,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, ttmp15
+// CHECK: [0x7b,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, m0
+// CHECK: [0x7c,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, exec_lo
+// CHECK: [0x7e,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, exec_hi
+// CHECK: [0x7f,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, 0
+// CHECK: [0x80,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, -1
+// CHECK: [0xc1,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, 0.5
+// CHECK: [0xf0,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, -4.0
+// CHECK: [0xf7,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, src_vccz
+// CHECK: [0xfb,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, src_execz
+// CHECK: [0xfc,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, src_scc
+// CHECK: [0xfd,0x12,0x85,0xbe]
+
+s_flbit_i32_b32 s5, 0xaf123456
+// CHECK: [0xff,0x12,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_b32 s5, 0x3f717273
+// CHECK: [0xff,0x12,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_b64 s5, s[2:3]
+// CHECK: [0x02,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s101, s[2:3]
+// CHECK: [0x02,0x13,0xe5,0xbe]
+
+s_flbit_i32_b64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x13,0xe6,0xbe]
+
+s_flbit_i32_b64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x13,0xe7,0xbe]
+
+s_flbit_i32_b64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x13,0xea,0xbe]
+
+s_flbit_i32_b64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x13,0xeb,0xbe]
+
+s_flbit_i32_b64 ttmp15, s[2:3]
+// CHECK: [0x02,0x13,0xfb,0xbe]
+
+s_flbit_i32_b64 m0, s[2:3]
+// CHECK: [0x02,0x13,0xfc,0xbe]
+
+s_flbit_i32_b64 exec_lo, s[2:3]
+// CHECK: [0x02,0x13,0xfe,0xbe]
+
+s_flbit_i32_b64 exec_hi, s[2:3]
+// CHECK: [0x02,0x13,0xff,0xbe]
+
+s_flbit_i32_b64 s5, s[4:5]
+// CHECK: [0x04,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, s[100:101]
+// CHECK: [0x64,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, flat_scratch
+// CHECK: [0x66,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, vcc
+// CHECK: [0x6a,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, ttmp[14:15]
+// CHECK: [0x7a,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, exec
+// CHECK: [0x7e,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, 0
+// CHECK: [0x80,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, -1
+// CHECK: [0xc1,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, 0.5
+// CHECK: [0xf0,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, -4.0
+// CHECK: [0xf7,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, src_vccz
+// CHECK: [0xfb,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, src_execz
+// CHECK: [0xfc,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, src_scc
+// CHECK: [0xfd,0x13,0x85,0xbe]
+
+s_flbit_i32_b64 s5, 0xaf123456
+// CHECK: [0xff,0x13,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_b64 s5, 0x3f717273
+// CHECK: [0xff,0x13,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32 s5, s1
+// CHECK: [0x01,0x14,0x85,0xbe]
+
+s_flbit_i32 s101, s1
+// CHECK: [0x01,0x14,0xe5,0xbe]
+
+s_flbit_i32 flat_scratch_lo, s1
+// CHECK: [0x01,0x14,0xe6,0xbe]
+
+s_flbit_i32 flat_scratch_hi, s1
+// CHECK: [0x01,0x14,0xe7,0xbe]
+
+s_flbit_i32 vcc_lo, s1
+// CHECK: [0x01,0x14,0xea,0xbe]
+
+s_flbit_i32 vcc_hi, s1
+// CHECK: [0x01,0x14,0xeb,0xbe]
+
+s_flbit_i32 ttmp15, s1
+// CHECK: [0x01,0x14,0xfb,0xbe]
+
+s_flbit_i32 m0, s1
+// CHECK: [0x01,0x14,0xfc,0xbe]
+
+s_flbit_i32 exec_lo, s1
+// CHECK: [0x01,0x14,0xfe,0xbe]
+
+s_flbit_i32 exec_hi, s1
+// CHECK: [0x01,0x14,0xff,0xbe]
+
+s_flbit_i32 s5, s101
+// CHECK: [0x65,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, flat_scratch_lo
+// CHECK: [0x66,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, flat_scratch_hi
+// CHECK: [0x67,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, vcc_lo
+// CHECK: [0x6a,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, vcc_hi
+// CHECK: [0x6b,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, ttmp15
+// CHECK: [0x7b,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, m0
+// CHECK: [0x7c,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, exec_lo
+// CHECK: [0x7e,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, exec_hi
+// CHECK: [0x7f,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, 0
+// CHECK: [0x80,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, -1
+// CHECK: [0xc1,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, 0.5
+// CHECK: [0xf0,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, -4.0
+// CHECK: [0xf7,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, src_vccz
+// CHECK: [0xfb,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, src_execz
+// CHECK: [0xfc,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, src_scc
+// CHECK: [0xfd,0x14,0x85,0xbe]
+
+s_flbit_i32 s5, 0xaf123456
+// CHECK: [0xff,0x14,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32 s5, 0x3f717273
+// CHECK: [0xff,0x14,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_flbit_i32_i64 s5, s[2:3]
+// CHECK: [0x02,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s101, s[2:3]
+// CHECK: [0x02,0x15,0xe5,0xbe]
+
+s_flbit_i32_i64 flat_scratch_lo, s[2:3]
+// CHECK: [0x02,0x15,0xe6,0xbe]
+
+s_flbit_i32_i64 flat_scratch_hi, s[2:3]
+// CHECK: [0x02,0x15,0xe7,0xbe]
+
+s_flbit_i32_i64 vcc_lo, s[2:3]
+// CHECK: [0x02,0x15,0xea,0xbe]
+
+s_flbit_i32_i64 vcc_hi, s[2:3]
+// CHECK: [0x02,0x15,0xeb,0xbe]
+
+s_flbit_i32_i64 ttmp15, s[2:3]
+// CHECK: [0x02,0x15,0xfb,0xbe]
+
+s_flbit_i32_i64 m0, s[2:3]
+// CHECK: [0x02,0x15,0xfc,0xbe]
+
+s_flbit_i32_i64 exec_lo, s[2:3]
+// CHECK: [0x02,0x15,0xfe,0xbe]
+
+s_flbit_i32_i64 exec_hi, s[2:3]
+// CHECK: [0x02,0x15,0xff,0xbe]
+
+s_flbit_i32_i64 s5, s[4:5]
+// CHECK: [0x04,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, s[100:101]
+// CHECK: [0x64,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, flat_scratch
+// CHECK: [0x66,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, vcc
+// CHECK: [0x6a,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, ttmp[14:15]
+// CHECK: [0x7a,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, exec
+// CHECK: [0x7e,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, 0
+// CHECK: [0x80,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, -1
+// CHECK: [0xc1,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, 0.5
+// CHECK: [0xf0,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, -4.0
+// CHECK: [0xf7,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, src_vccz
+// CHECK: [0xfb,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, src_execz
+// CHECK: [0xfc,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, src_scc
+// CHECK: [0xfd,0x15,0x85,0xbe]
+
+s_flbit_i32_i64 s5, 0xaf123456
+// CHECK: [0xff,0x15,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_flbit_i32_i64 s5, 0x3f717273
+// CHECK: [0xff,0x15,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_sext_i32_i8 s5, s1
+// CHECK: [0x01,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s101, s1
+// CHECK: [0x01,0x16,0xe5,0xbe]
+
+s_sext_i32_i8 flat_scratch_lo, s1
+// CHECK: [0x01,0x16,0xe6,0xbe]
+
+s_sext_i32_i8 flat_scratch_hi, s1
+// CHECK: [0x01,0x16,0xe7,0xbe]
+
+s_sext_i32_i8 vcc_lo, s1
+// CHECK: [0x01,0x16,0xea,0xbe]
+
+s_sext_i32_i8 vcc_hi, s1
+// CHECK: [0x01,0x16,0xeb,0xbe]
+
+s_sext_i32_i8 ttmp15, s1
+// CHECK: [0x01,0x16,0xfb,0xbe]
+
+s_sext_i32_i8 m0, s1
+// CHECK: [0x01,0x16,0xfc,0xbe]
+
+s_sext_i32_i8 exec_lo, s1
+// CHECK: [0x01,0x16,0xfe,0xbe]
+
+s_sext_i32_i8 exec_hi, s1
+// CHECK: [0x01,0x16,0xff,0xbe]
+
+s_sext_i32_i8 s5, s101
+// CHECK: [0x65,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, flat_scratch_lo
+// CHECK: [0x66,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, flat_scratch_hi
+// CHECK: [0x67,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, vcc_lo
+// CHECK: [0x6a,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, vcc_hi
+// CHECK: [0x6b,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, ttmp15
+// CHECK: [0x7b,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, m0
+// CHECK: [0x7c,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, exec_lo
+// CHECK: [0x7e,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, exec_hi
+// CHECK: [0x7f,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, 0
+// CHECK: [0x80,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, -1
+// CHECK: [0xc1,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, 0.5
+// CHECK: [0xf0,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, -4.0
+// CHECK: [0xf7,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, src_vccz
+// CHECK: [0xfb,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, src_execz
+// CHECK: [0xfc,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, src_scc
+// CHECK: [0xfd,0x16,0x85,0xbe]
+
+s_sext_i32_i8 s5, 0x71
+// CHECK: [0xff,0x16,0x85,0xbe,0x71,0x00,0x00,0x00]
+
+s_sext_i32_i8 s5, 0xf0
+// CHECK: [0xff,0x16,0x85,0xbe,0xf0,0x00,0x00,0x00]
+
+s_sext_i32_i16 s5, s1
+// CHECK: [0x01,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s101, s1
+// CHECK: [0x01,0x17,0xe5,0xbe]
+
+s_sext_i32_i16 flat_scratch_lo, s1
+// CHECK: [0x01,0x17,0xe6,0xbe]
+
+s_sext_i32_i16 flat_scratch_hi, s1
+// CHECK: [0x01,0x17,0xe7,0xbe]
+
+s_sext_i32_i16 vcc_lo, s1
+// CHECK: [0x01,0x17,0xea,0xbe]
+
+s_sext_i32_i16 vcc_hi, s1
+// CHECK: [0x01,0x17,0xeb,0xbe]
+
+s_sext_i32_i16 ttmp15, s1
+// CHECK: [0x01,0x17,0xfb,0xbe]
+
+s_sext_i32_i16 m0, s1
+// CHECK: [0x01,0x17,0xfc,0xbe]
+
+s_sext_i32_i16 exec_lo, s1
+// CHECK: [0x01,0x17,0xfe,0xbe]
+
+s_sext_i32_i16 exec_hi, s1
+// CHECK: [0x01,0x17,0xff,0xbe]
+
+s_sext_i32_i16 s5, s101
+// CHECK: [0x65,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, flat_scratch_lo
+// CHECK: [0x66,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, flat_scratch_hi
+// CHECK: [0x67,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, vcc_lo
+// CHECK: [0x6a,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, vcc_hi
+// CHECK: [0x6b,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, ttmp15
+// CHECK: [0x7b,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, m0
+// CHECK: [0x7c,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, exec_lo
+// CHECK: [0x7e,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, exec_hi
+// CHECK: [0x7f,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, 0
+// CHECK: [0x80,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, -1
+// CHECK: [0xc1,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, 0.5
+// CHECK: [0xf0,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, -4.0
+// CHECK: [0xf7,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, src_vccz
+// CHECK: [0xfb,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, src_execz
+// CHECK: [0xfc,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, src_scc
+// CHECK: [0xfd,0x17,0x85,0xbe]
+
+s_sext_i32_i16 s5, 0xfe0b
+// CHECK: [0xff,0x17,0x85,0xbe,0x0b,0xfe,0x00,0x00]
+
+s_sext_i32_i16 s5, 0x3456
+// CHECK: [0xff,0x17,0x85,0xbe,0x56,0x34,0x00,0x00]
+
+s_bitset0_b32 s5, s1
+// CHECK: [0x01,0x18,0x85,0xbe]
+
+s_bitset0_b32 s101, s1
+// CHECK: [0x01,0x18,0xe5,0xbe]
+
+s_bitset0_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x18,0xe6,0xbe]
+
+s_bitset0_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x18,0xe7,0xbe]
+
+s_bitset0_b32 vcc_lo, s1
+// CHECK: [0x01,0x18,0xea,0xbe]
+
+s_bitset0_b32 vcc_hi, s1
+// CHECK: [0x01,0x18,0xeb,0xbe]
+
+s_bitset0_b32 ttmp15, s1
+// CHECK: [0x01,0x18,0xfb,0xbe]
+
+s_bitset0_b32 m0, s1
+// CHECK: [0x01,0x18,0xfc,0xbe]
+
+s_bitset0_b32 exec_lo, s1
+// CHECK: [0x01,0x18,0xfe,0xbe]
+
+s_bitset0_b32 exec_hi, s1
+// CHECK: [0x01,0x18,0xff,0xbe]
+
+s_bitset0_b32 s5, s101
+// CHECK: [0x65,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, vcc_lo
+// CHECK: [0x6a,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, vcc_hi
+// CHECK: [0x6b,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, ttmp15
+// CHECK: [0x7b,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, m0
+// CHECK: [0x7c,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, exec_lo
+// CHECK: [0x7e,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, exec_hi
+// CHECK: [0x7f,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, 0
+// CHECK: [0x80,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, -1
+// CHECK: [0xc1,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, 0.5
+// CHECK: [0xf0,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, -4.0
+// CHECK: [0xf7,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, src_vccz
+// CHECK: [0xfb,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, src_execz
+// CHECK: [0xfc,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, src_scc
+// CHECK: [0xfd,0x18,0x85,0xbe]
+
+s_bitset0_b32 s5, 0xaf123456
+// CHECK: [0xff,0x18,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset0_b32 s5, 0x3f717273
+// CHECK: [0xff,0x18,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset0_b64 s[10:11], s1
+// CHECK: [0x01,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[12:13], s1
+// CHECK: [0x01,0x19,0x8c,0xbe]
+
+s_bitset0_b64 s[100:101], s1
+// CHECK: [0x01,0x19,0xe4,0xbe]
+
+s_bitset0_b64 flat_scratch, s1
+// CHECK: [0x01,0x19,0xe6,0xbe]
+
+s_bitset0_b64 vcc, s1
+// CHECK: [0x01,0x19,0xea,0xbe]
+
+s_bitset0_b64 ttmp[14:15], s1
+// CHECK: [0x01,0x19,0xfa,0xbe]
+
+s_bitset0_b64 exec, s1
+// CHECK: [0x01,0x19,0xfe,0xbe]
+
+s_bitset0_b64 s[10:11], s101
+// CHECK: [0x65,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], flat_scratch_lo
+// CHECK: [0x66,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], flat_scratch_hi
+// CHECK: [0x67,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], vcc_lo
+// CHECK: [0x6a,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], vcc_hi
+// CHECK: [0x6b,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], ttmp15
+// CHECK: [0x7b,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], m0
+// CHECK: [0x7c,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], exec_lo
+// CHECK: [0x7e,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], exec_hi
+// CHECK: [0x7f,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], 0
+// CHECK: [0x80,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], -1
+// CHECK: [0xc1,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x19,0x8a,0xbe]
+
+s_bitset0_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x19,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset0_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x19,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset1_b32 s5, s1
+// CHECK: [0x01,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s101, s1
+// CHECK: [0x01,0x1a,0xe5,0xbe]
+
+s_bitset1_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x1a,0xe6,0xbe]
+
+s_bitset1_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x1a,0xe7,0xbe]
+
+s_bitset1_b32 vcc_lo, s1
+// CHECK: [0x01,0x1a,0xea,0xbe]
+
+s_bitset1_b32 vcc_hi, s1
+// CHECK: [0x01,0x1a,0xeb,0xbe]
+
+s_bitset1_b32 ttmp15, s1
+// CHECK: [0x01,0x1a,0xfb,0xbe]
+
+s_bitset1_b32 m0, s1
+// CHECK: [0x01,0x1a,0xfc,0xbe]
+
+s_bitset1_b32 exec_lo, s1
+// CHECK: [0x01,0x1a,0xfe,0xbe]
+
+s_bitset1_b32 exec_hi, s1
+// CHECK: [0x01,0x1a,0xff,0xbe]
+
+s_bitset1_b32 s5, s101
+// CHECK: [0x65,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, vcc_lo
+// CHECK: [0x6a,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, vcc_hi
+// CHECK: [0x6b,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, ttmp15
+// CHECK: [0x7b,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, m0
+// CHECK: [0x7c,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, exec_lo
+// CHECK: [0x7e,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, exec_hi
+// CHECK: [0x7f,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, 0
+// CHECK: [0x80,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, -1
+// CHECK: [0xc1,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, 0.5
+// CHECK: [0xf0,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, -4.0
+// CHECK: [0xf7,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, src_vccz
+// CHECK: [0xfb,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, src_execz
+// CHECK: [0xfc,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, src_scc
+// CHECK: [0xfd,0x1a,0x85,0xbe]
+
+s_bitset1_b32 s5, 0xaf123456
+// CHECK: [0xff,0x1a,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset1_b32 s5, 0x3f717273
+// CHECK: [0xff,0x1a,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitset1_b64 s[10:11], s1
+// CHECK: [0x01,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[12:13], s1
+// CHECK: [0x01,0x1b,0x8c,0xbe]
+
+s_bitset1_b64 s[100:101], s1
+// CHECK: [0x01,0x1b,0xe4,0xbe]
+
+s_bitset1_b64 flat_scratch, s1
+// CHECK: [0x01,0x1b,0xe6,0xbe]
+
+s_bitset1_b64 vcc, s1
+// CHECK: [0x01,0x1b,0xea,0xbe]
+
+s_bitset1_b64 ttmp[14:15], s1
+// CHECK: [0x01,0x1b,0xfa,0xbe]
+
+s_bitset1_b64 exec, s1
+// CHECK: [0x01,0x1b,0xfe,0xbe]
+
+s_bitset1_b64 s[10:11], s101
+// CHECK: [0x65,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], flat_scratch_lo
+// CHECK: [0x66,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], flat_scratch_hi
+// CHECK: [0x67,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], vcc_lo
+// CHECK: [0x6a,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], vcc_hi
+// CHECK: [0x6b,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], ttmp15
+// CHECK: [0x7b,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], m0
+// CHECK: [0x7c,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], exec_lo
+// CHECK: [0x7e,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], exec_hi
+// CHECK: [0x7f,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], 0
+// CHECK: [0x80,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], -1
+// CHECK: [0xc1,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x1b,0x8a,0xbe]
+
+s_bitset1_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x1b,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitset1_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x1b,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_getpc_b64 s[10:11]
+// CHECK: [0x00,0x1c,0x8a,0xbe]
+
+s_getpc_b64 s[12:13]
+// CHECK: [0x00,0x1c,0x8c,0xbe]
+
+s_getpc_b64 s[100:101]
+// CHECK: [0x00,0x1c,0xe4,0xbe]
+
+s_getpc_b64 flat_scratch
+// CHECK: [0x00,0x1c,0xe6,0xbe]
+
+s_getpc_b64 vcc
+// CHECK: [0x00,0x1c,0xea,0xbe]
+
+s_getpc_b64 ttmp[14:15]
+// CHECK: [0x00,0x1c,0xfa,0xbe]
+
+s_getpc_b64 exec
+// CHECK: [0x00,0x1c,0xfe,0xbe]
+
+s_setpc_b64 s[2:3]
+// CHECK: [0x02,0x1d,0x80,0xbe]
+
+s_setpc_b64 s[4:5]
+// CHECK: [0x04,0x1d,0x80,0xbe]
+
+s_setpc_b64 s[100:101]
+// CHECK: [0x64,0x1d,0x80,0xbe]
+
+s_setpc_b64 flat_scratch
+// CHECK: [0x66,0x1d,0x80,0xbe]
+
+s_setpc_b64 vcc
+// CHECK: [0x6a,0x1d,0x80,0xbe]
+
+s_setpc_b64 ttmp[14:15]
+// CHECK: [0x7a,0x1d,0x80,0xbe]
+
+s_swappc_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x1e,0x8c,0xbe]
+
+s_swappc_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x1e,0xe4,0xbe]
+
+s_swappc_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x1e,0xe6,0xbe]
+
+s_swappc_b64 vcc, s[2:3]
+// CHECK: [0x02,0x1e,0xea,0xbe]
+
+s_swappc_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x1e,0xfa,0xbe]
+
+s_swappc_b64 exec, s[2:3]
+// CHECK: [0x02,0x1e,0xfe,0xbe]
+
+s_swappc_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], vcc
+// CHECK: [0x6a,0x1e,0x8a,0xbe]
+
+s_swappc_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x1e,0x8a,0xbe]
+
+s_rfe_b64 s[2:3]
+// CHECK: [0x02,0x1f,0x80,0xbe]
+
+s_rfe_b64 s[4:5]
+// CHECK: [0x04,0x1f,0x80,0xbe]
+
+s_rfe_b64 s[100:101]
+// CHECK: [0x64,0x1f,0x80,0xbe]
+
+s_rfe_b64 flat_scratch
+// CHECK: [0x66,0x1f,0x80,0xbe]
+
+s_rfe_b64 vcc
+// CHECK: [0x6a,0x1f,0x80,0xbe]
+
+s_rfe_b64 ttmp[14:15]
+// CHECK: [0x7a,0x1f,0x80,0xbe]
+
+s_and_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x20,0x8c,0xbe]
+
+s_and_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x20,0xe4,0xbe]
+
+s_and_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x20,0xe6,0xbe]
+
+s_and_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x20,0xea,0xbe]
+
+s_and_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x20,0xfa,0xbe]
+
+s_and_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x20,0x8a,0xbe]
+
+s_and_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x20,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_and_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x20,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_or_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x21,0x8c,0xbe]
+
+s_or_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x21,0xe4,0xbe]
+
+s_or_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x21,0xe6,0xbe]
+
+s_or_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x21,0xea,0xbe]
+
+s_or_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x21,0xfa,0xbe]
+
+s_or_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x21,0x8a,0xbe]
+
+s_or_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x21,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_or_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x21,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xor_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x22,0x8c,0xbe]
+
+s_xor_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x22,0xe4,0xbe]
+
+s_xor_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x22,0xe6,0xbe]
+
+s_xor_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x22,0xea,0xbe]
+
+s_xor_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x22,0xfa,0xbe]
+
+s_xor_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x22,0x8a,0xbe]
+
+s_xor_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x22,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xor_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x22,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn2_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x23,0x8c,0xbe]
+
+s_andn2_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x23,0xe4,0xbe]
+
+s_andn2_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x23,0xe6,0xbe]
+
+s_andn2_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x23,0xea,0xbe]
+
+s_andn2_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x23,0xfa,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x23,0x8a,0xbe]
+
+s_andn2_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x23,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn2_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x23,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_orn2_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x24,0x8c,0xbe]
+
+s_orn2_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x24,0xe4,0xbe]
+
+s_orn2_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x24,0xe6,0xbe]
+
+s_orn2_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x24,0xea,0xbe]
+
+s_orn2_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x24,0xfa,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x24,0x8a,0xbe]
+
+s_orn2_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x24,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_orn2_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x24,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nand_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x25,0x8c,0xbe]
+
+s_nand_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x25,0xe4,0xbe]
+
+s_nand_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x25,0xe6,0xbe]
+
+s_nand_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x25,0xea,0xbe]
+
+s_nand_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x25,0xfa,0xbe]
+
+s_nand_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x25,0x8a,0xbe]
+
+s_nand_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x25,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nand_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x25,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_nor_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x26,0x8c,0xbe]
+
+s_nor_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x26,0xe4,0xbe]
+
+s_nor_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x26,0xe6,0xbe]
+
+s_nor_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x26,0xea,0xbe]
+
+s_nor_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x26,0xfa,0xbe]
+
+s_nor_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x26,0x8a,0xbe]
+
+s_nor_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x26,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_nor_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x26,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_xnor_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x27,0x8c,0xbe]
+
+s_xnor_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x27,0xe4,0xbe]
+
+s_xnor_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x27,0xe6,0xbe]
+
+s_xnor_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x27,0xea,0xbe]
+
+s_xnor_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x27,0xfa,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x27,0x8a,0xbe]
+
+s_xnor_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x27,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_xnor_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x27,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_quadmask_b32 s5, s1
+// CHECK: [0x01,0x28,0x85,0xbe]
+
+s_quadmask_b32 s101, s1
+// CHECK: [0x01,0x28,0xe5,0xbe]
+
+s_quadmask_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x28,0xe6,0xbe]
+
+s_quadmask_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x28,0xe7,0xbe]
+
+s_quadmask_b32 vcc_lo, s1
+// CHECK: [0x01,0x28,0xea,0xbe]
+
+s_quadmask_b32 vcc_hi, s1
+// CHECK: [0x01,0x28,0xeb,0xbe]
+
+s_quadmask_b32 ttmp15, s1
+// CHECK: [0x01,0x28,0xfb,0xbe]
+
+s_quadmask_b32 m0, s1
+// CHECK: [0x01,0x28,0xfc,0xbe]
+
+s_quadmask_b32 exec_lo, s1
+// CHECK: [0x01,0x28,0xfe,0xbe]
+
+s_quadmask_b32 exec_hi, s1
+// CHECK: [0x01,0x28,0xff,0xbe]
+
+s_quadmask_b32 s5, s101
+// CHECK: [0x65,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, vcc_lo
+// CHECK: [0x6a,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, vcc_hi
+// CHECK: [0x6b,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, ttmp15
+// CHECK: [0x7b,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, m0
+// CHECK: [0x7c,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, exec_lo
+// CHECK: [0x7e,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, exec_hi
+// CHECK: [0x7f,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, 0
+// CHECK: [0x80,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, -1
+// CHECK: [0xc1,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, 0.5
+// CHECK: [0xf0,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, -4.0
+// CHECK: [0xf7,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, src_vccz
+// CHECK: [0xfb,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, src_execz
+// CHECK: [0xfc,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, src_scc
+// CHECK: [0xfd,0x28,0x85,0xbe]
+
+s_quadmask_b32 s5, 0xaf123456
+// CHECK: [0xff,0x28,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_quadmask_b32 s5, 0x3f717273
+// CHECK: [0xff,0x28,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_quadmask_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x29,0x8c,0xbe]
+
+s_quadmask_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x29,0xe4,0xbe]
+
+s_quadmask_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x29,0xe6,0xbe]
+
+s_quadmask_b64 vcc, s[2:3]
+// CHECK: [0x02,0x29,0xea,0xbe]
+
+s_quadmask_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x29,0xfa,0xbe]
+
+s_quadmask_b64 exec, s[2:3]
+// CHECK: [0x02,0x29,0xfe,0xbe]
+
+s_quadmask_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], vcc
+// CHECK: [0x6a,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], exec
+// CHECK: [0x7e,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], 0
+// CHECK: [0x80,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], -1
+// CHECK: [0xc1,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x29,0x8a,0xbe]
+
+s_quadmask_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x29,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_quadmask_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x29,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_movrels_b32 s5, s1
+// CHECK: [0x01,0x2a,0x85,0xbe]
+
+s_movrels_b32 s101, s1
+// CHECK: [0x01,0x2a,0xe5,0xbe]
+
+s_movrels_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x2a,0xe6,0xbe]
+
+s_movrels_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x2a,0xe7,0xbe]
+
+s_movrels_b32 vcc_lo, s1
+// CHECK: [0x01,0x2a,0xea,0xbe]
+
+s_movrels_b32 vcc_hi, s1
+// CHECK: [0x01,0x2a,0xeb,0xbe]
+
+s_movrels_b32 ttmp15, s1
+// CHECK: [0x01,0x2a,0xfb,0xbe]
+
+s_movrels_b32 m0, s1
+// CHECK: [0x01,0x2a,0xfc,0xbe]
+
+s_movrels_b32 exec_lo, s1
+// CHECK: [0x01,0x2a,0xfe,0xbe]
+
+s_movrels_b32 exec_hi, s1
+// CHECK: [0x01,0x2a,0xff,0xbe]
+
+s_movrels_b32 s5, s101
+// CHECK: [0x65,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, vcc_lo
+// CHECK: [0x6a,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, vcc_hi
+// CHECK: [0x6b,0x2a,0x85,0xbe]
+
+s_movrels_b32 s5, ttmp15
+// CHECK: [0x7b,0x2a,0x85,0xbe]
+
+s_movrels_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x2b,0x8c,0xbe]
+
+s_movrels_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x2b,0xe4,0xbe]
+
+s_movrels_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x2b,0xe6,0xbe]
+
+s_movrels_b64 vcc, s[2:3]
+// CHECK: [0x02,0x2b,0xea,0xbe]
+
+s_movrels_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x2b,0xfa,0xbe]
+
+s_movrels_b64 exec, s[2:3]
+// CHECK: [0x02,0x2b,0xfe,0xbe]
+
+s_movrels_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], vcc
+// CHECK: [0x6a,0x2b,0x8a,0xbe]
+
+s_movrels_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x2b,0x8a,0xbe]
+
+s_movreld_b32 s5, s1
+// CHECK: [0x01,0x2c,0x85,0xbe]
+
+s_movreld_b32 s101, s1
+// CHECK: [0x01,0x2c,0xe5,0xbe]
+
+s_movreld_b32 flat_scratch_lo, s1
+// CHECK: [0x01,0x2c,0xe6,0xbe]
+
+s_movreld_b32 flat_scratch_hi, s1
+// CHECK: [0x01,0x2c,0xe7,0xbe]
+
+s_movreld_b32 vcc_lo, s1
+// CHECK: [0x01,0x2c,0xea,0xbe]
+
+s_movreld_b32 vcc_hi, s1
+// CHECK: [0x01,0x2c,0xeb,0xbe]
+
+s_movreld_b32 ttmp15, s1
+// CHECK: [0x01,0x2c,0xfb,0xbe]
+
+s_movreld_b32 s5, s101
+// CHECK: [0x65,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, flat_scratch_lo
+// CHECK: [0x66,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, flat_scratch_hi
+// CHECK: [0x67,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, vcc_lo
+// CHECK: [0x6a,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, vcc_hi
+// CHECK: [0x6b,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, ttmp15
+// CHECK: [0x7b,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, m0
+// CHECK: [0x7c,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, 0
+// CHECK: [0x80,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, -1
+// CHECK: [0xc1,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, 0.5
+// CHECK: [0xf0,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, -4.0
+// CHECK: [0xf7,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, src_vccz
+// CHECK: [0xfb,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, src_execz
+// CHECK: [0xfc,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, src_scc
+// CHECK: [0xfd,0x2c,0x85,0xbe]
+
+s_movreld_b32 s5, 0xaf123456
+// CHECK: [0xff,0x2c,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_movreld_b32 s5, 0x3f717273
+// CHECK: [0xff,0x2c,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_movreld_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x2d,0x8c,0xbe]
+
+s_movreld_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x2d,0xe4,0xbe]
+
+s_movreld_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x2d,0xe6,0xbe]
+
+s_movreld_b64 vcc, s[2:3]
+// CHECK: [0x02,0x2d,0xea,0xbe]
+
+s_movreld_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x2d,0xfa,0xbe]
+
+s_movreld_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], vcc
+// CHECK: [0x6a,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], 0
+// CHECK: [0x80,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], -1
+// CHECK: [0xc1,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x2d,0x8a,0xbe]
+
+s_movreld_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x2d,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_movreld_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x2d,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_cbranch_join s1
+// CHECK: [0x01,0x2e,0x80,0xbe]
+
+s_cbranch_join s101
+// CHECK: [0x65,0x2e,0x80,0xbe]
+
+s_cbranch_join flat_scratch_lo
+// CHECK: [0x66,0x2e,0x80,0xbe]
+
+s_cbranch_join flat_scratch_hi
+// CHECK: [0x67,0x2e,0x80,0xbe]
+
+s_cbranch_join vcc_lo
+// CHECK: [0x6a,0x2e,0x80,0xbe]
+
+s_cbranch_join vcc_hi
+// CHECK: [0x6b,0x2e,0x80,0xbe]
+
+s_cbranch_join ttmp15
+// CHECK: [0x7b,0x2e,0x80,0xbe]
+
+s_abs_i32 s5, s1
+// CHECK: [0x01,0x30,0x85,0xbe]
+
+s_abs_i32 s101, s1
+// CHECK: [0x01,0x30,0xe5,0xbe]
+
+s_abs_i32 flat_scratch_lo, s1
+// CHECK: [0x01,0x30,0xe6,0xbe]
+
+s_abs_i32 flat_scratch_hi, s1
+// CHECK: [0x01,0x30,0xe7,0xbe]
+
+s_abs_i32 vcc_lo, s1
+// CHECK: [0x01,0x30,0xea,0xbe]
+
+s_abs_i32 vcc_hi, s1
+// CHECK: [0x01,0x30,0xeb,0xbe]
+
+s_abs_i32 ttmp15, s1
+// CHECK: [0x01,0x30,0xfb,0xbe]
+
+s_abs_i32 m0, s1
+// CHECK: [0x01,0x30,0xfc,0xbe]
+
+s_abs_i32 exec_lo, s1
+// CHECK: [0x01,0x30,0xfe,0xbe]
+
+s_abs_i32 exec_hi, s1
+// CHECK: [0x01,0x30,0xff,0xbe]
+
+s_abs_i32 s5, s101
+// CHECK: [0x65,0x30,0x85,0xbe]
+
+s_abs_i32 s5, flat_scratch_lo
+// CHECK: [0x66,0x30,0x85,0xbe]
+
+s_abs_i32 s5, flat_scratch_hi
+// CHECK: [0x67,0x30,0x85,0xbe]
+
+s_abs_i32 s5, vcc_lo
+// CHECK: [0x6a,0x30,0x85,0xbe]
+
+s_abs_i32 s5, vcc_hi
+// CHECK: [0x6b,0x30,0x85,0xbe]
+
+s_abs_i32 s5, ttmp15
+// CHECK: [0x7b,0x30,0x85,0xbe]
+
+s_abs_i32 s5, m0
+// CHECK: [0x7c,0x30,0x85,0xbe]
+
+s_abs_i32 s5, exec_lo
+// CHECK: [0x7e,0x30,0x85,0xbe]
+
+s_abs_i32 s5, exec_hi
+// CHECK: [0x7f,0x30,0x85,0xbe]
+
+s_abs_i32 s5, 0
+// CHECK: [0x80,0x30,0x85,0xbe]
+
+s_abs_i32 s5, -1
+// CHECK: [0xc1,0x30,0x85,0xbe]
+
+s_abs_i32 s5, 0.5
+// CHECK: [0xf0,0x30,0x85,0xbe]
+
+s_abs_i32 s5, -4.0
+// CHECK: [0xf7,0x30,0x85,0xbe]
+
+s_abs_i32 s5, src_vccz
+// CHECK: [0xfb,0x30,0x85,0xbe]
+
+s_abs_i32 s5, src_execz
+// CHECK: [0xfc,0x30,0x85,0xbe]
+
+s_abs_i32 s5, src_scc
+// CHECK: [0xfd,0x30,0x85,0xbe]
+
+s_abs_i32 s5, 0xaf123456
+// CHECK: [0xff,0x30,0x85,0xbe,0x56,0x34,0x12,0xaf]
+
+s_abs_i32 s5, 0x3f717273
+// CHECK: [0xff,0x30,0x85,0xbe,0x73,0x72,0x71,0x3f]
+
+s_set_gpr_idx_idx s1
+// CHECK: [0x01,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx s101
+// CHECK: [0x65,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx flat_scratch_lo
+// CHECK: [0x66,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx flat_scratch_hi
+// CHECK: [0x67,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx vcc_lo
+// CHECK: [0x6a,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx vcc_hi
+// CHECK: [0x6b,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx ttmp15
+// CHECK: [0x7b,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx m0
+// CHECK: [0x7c,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx 0
+// CHECK: [0x80,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx -1
+// CHECK: [0xc1,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx 0.5
+// CHECK: [0xf0,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx -4.0
+// CHECK: [0xf7,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx src_vccz
+// CHECK: [0xfb,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx src_execz
+// CHECK: [0xfc,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx src_scc
+// CHECK: [0xfd,0x32,0x80,0xbe]
+
+s_set_gpr_idx_idx 0xaf123456
+// CHECK: [0xff,0x32,0x80,0xbe,0x56,0x34,0x12,0xaf]
+
+s_set_gpr_idx_idx 0x3f717273
+// CHECK: [0xff,0x32,0x80,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn1_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x33,0x8c,0xbe]
+
+s_andn1_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x33,0xe4,0xbe]
+
+s_andn1_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x33,0xe6,0xbe]
+
+s_andn1_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x33,0xea,0xbe]
+
+s_andn1_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x33,0xfa,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x33,0x8a,0xbe]
+
+s_andn1_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x33,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn1_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x33,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_orn1_saveexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x34,0x8c,0xbe]
+
+s_orn1_saveexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x34,0xe4,0xbe]
+
+s_orn1_saveexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x34,0xe6,0xbe]
+
+s_orn1_saveexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x34,0xea,0xbe]
+
+s_orn1_saveexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x34,0xfa,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], 0
+// CHECK: [0x80,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x34,0x8a,0xbe]
+
+s_orn1_saveexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x34,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_orn1_saveexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x34,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn1_wrexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x35,0x8c,0xbe]
+
+s_andn1_wrexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x35,0xe4,0xbe]
+
+s_andn1_wrexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x35,0xe6,0xbe]
+
+s_andn1_wrexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x35,0xea,0xbe]
+
+s_andn1_wrexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x35,0xfa,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], 0
+// CHECK: [0x80,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x35,0x8a,0xbe]
+
+s_andn1_wrexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x35,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn1_wrexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x35,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_andn2_wrexec_b64 s[10:11], s[2:3]
+// CHECK: [0x02,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[12:13], s[2:3]
+// CHECK: [0x02,0x36,0x8c,0xbe]
+
+s_andn2_wrexec_b64 s[100:101], s[2:3]
+// CHECK: [0x02,0x36,0xe4,0xbe]
+
+s_andn2_wrexec_b64 flat_scratch, s[2:3]
+// CHECK: [0x02,0x36,0xe6,0xbe]
+
+s_andn2_wrexec_b64 vcc, s[2:3]
+// CHECK: [0x02,0x36,0xea,0xbe]
+
+s_andn2_wrexec_b64 ttmp[14:15], s[2:3]
+// CHECK: [0x02,0x36,0xfa,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], s[4:5]
+// CHECK: [0x04,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], s[100:101]
+// CHECK: [0x64,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], flat_scratch
+// CHECK: [0x66,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], vcc
+// CHECK: [0x6a,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], ttmp[14:15]
+// CHECK: [0x7a,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], exec
+// CHECK: [0x7e,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], 0
+// CHECK: [0x80,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], -1
+// CHECK: [0xc1,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], 0.5
+// CHECK: [0xf0,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], -4.0
+// CHECK: [0xf7,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], src_vccz
+// CHECK: [0xfb,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], src_execz
+// CHECK: [0xfc,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], src_scc
+// CHECK: [0xfd,0x36,0x8a,0xbe]
+
+s_andn2_wrexec_b64 s[10:11], 0xaf123456
+// CHECK: [0xff,0x36,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_andn2_wrexec_b64 s[10:11], 0x3f717273
+// CHECK: [0xff,0x36,0x8a,0xbe,0x73,0x72,0x71,0x3f]
+
+s_bitreplicate_b64_b32 s[10:11], s1
+// CHECK: [0x01,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[12:13], s1
+// CHECK: [0x01,0x37,0x8c,0xbe]
+
+s_bitreplicate_b64_b32 s[100:101], s1
+// CHECK: [0x01,0x37,0xe4,0xbe]
+
+s_bitreplicate_b64_b32 flat_scratch, s1
+// CHECK: [0x01,0x37,0xe6,0xbe]
+
+s_bitreplicate_b64_b32 vcc, s1
+// CHECK: [0x01,0x37,0xea,0xbe]
+
+s_bitreplicate_b64_b32 ttmp[14:15], s1
+// CHECK: [0x01,0x37,0xfa,0xbe]
+
+s_bitreplicate_b64_b32 exec, s1
+// CHECK: [0x01,0x37,0xfe,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], s101
+// CHECK: [0x65,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], flat_scratch_lo
+// CHECK: [0x66,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], flat_scratch_hi
+// CHECK: [0x67,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], vcc_lo
+// CHECK: [0x6a,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], vcc_hi
+// CHECK: [0x6b,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], ttmp15
+// CHECK: [0x7b,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], m0
+// CHECK: [0x7c,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], exec_lo
+// CHECK: [0x7e,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], exec_hi
+// CHECK: [0x7f,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], 0
+// CHECK: [0x80,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], -1
+// CHECK: [0xc1,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], 0.5
+// CHECK: [0xf0,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], -4.0
+// CHECK: [0xf7,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], src_vccz
+// CHECK: [0xfb,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], src_execz
+// CHECK: [0xfc,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], src_scc
+// CHECK: [0xfd,0x37,0x8a,0xbe]
+
+s_bitreplicate_b64_b32 s[10:11], 0xaf123456
+// CHECK: [0xff,0x37,0x8a,0xbe,0x56,0x34,0x12,0xaf]
+
+s_bitreplicate_b64_b32 s[10:11], 0x3f717273
+// CHECK: [0xff,0x37,0x8a,0xbe,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sop2.s b/llvm/test/MC/AMDGPU/gfx9_asm_sop2.s
new file mode 100644
index 0000000000000..554e766760afe
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sop2.s
@@ -0,0 +1,6880 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+s_add_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x80]
+
+s_add_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x80]
+
+s_add_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x80]
+
+s_add_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x80]
+
+s_add_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x80]
+
+s_add_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x80]
+
+s_add_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x80]
+
+s_add_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x80]
+
+s_add_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x80]
+
+s_add_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x80]
+
+s_add_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x80]
+
+s_add_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x80]
+
+s_add_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x80]
+
+s_add_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x80]
+
+s_add_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x80]
+
+s_add_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x80]
+
+s_add_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x80]
+
+s_add_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x80]
+
+s_add_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x80]
+
+s_add_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x80]
+
+s_add_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x80]
+
+s_add_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x80]
+
+s_add_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x80]
+
+s_add_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x80]
+
+s_add_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x80]
+
+s_add_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x80]
+
+s_add_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x80,0x56,0x34,0x12,0xaf]
+
+s_add_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x80,0x73,0x72,0x71,0x3f]
+
+s_add_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x80]
+
+s_add_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x80]
+
+s_add_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x80]
+
+s_add_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x80]
+
+s_add_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x80]
+
+s_add_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x80]
+
+s_add_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x80]
+
+s_add_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x80]
+
+s_add_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x80]
+
+s_add_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x80]
+
+s_add_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x80]
+
+s_add_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x80]
+
+s_add_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x80]
+
+s_add_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x80]
+
+s_add_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x80]
+
+s_add_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x80]
+
+s_add_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x80,0x56,0x34,0x12,0xaf]
+
+s_add_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x80,0x73,0x72,0x71,0x3f]
+
+s_sub_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x80]
+
+s_sub_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x80]
+
+s_sub_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x80]
+
+s_sub_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x80]
+
+s_sub_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x80]
+
+s_sub_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x80]
+
+s_sub_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x80]
+
+s_sub_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x80]
+
+s_sub_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x80]
+
+s_sub_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x80]
+
+s_sub_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x80]
+
+s_sub_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x80]
+
+s_sub_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x80]
+
+s_sub_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x80]
+
+s_sub_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x80]
+
+s_sub_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x80]
+
+s_sub_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x80]
+
+s_sub_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x80]
+
+s_sub_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x80]
+
+s_sub_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x80]
+
+s_sub_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x80]
+
+s_sub_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x80]
+
+s_sub_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x80]
+
+s_sub_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x80]
+
+s_sub_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x80]
+
+s_sub_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x80]
+
+s_sub_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x80,0x56,0x34,0x12,0xaf]
+
+s_sub_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x80,0x73,0x72,0x71,0x3f]
+
+s_sub_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x80]
+
+s_sub_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x80]
+
+s_sub_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x80]
+
+s_sub_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x80]
+
+s_sub_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x80]
+
+s_sub_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x80]
+
+s_sub_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x80]
+
+s_sub_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x80]
+
+s_sub_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x80]
+
+s_sub_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x80]
+
+s_sub_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x80]
+
+s_sub_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x80]
+
+s_sub_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x80]
+
+s_sub_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x80]
+
+s_sub_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x80]
+
+s_sub_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x80]
+
+s_sub_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x80,0x56,0x34,0x12,0xaf]
+
+s_sub_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x80,0x73,0x72,0x71,0x3f]
+
+s_add_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x81]
+
+s_add_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x81]
+
+s_add_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x81]
+
+s_add_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x81]
+
+s_add_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x81]
+
+s_add_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x81]
+
+s_add_i32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x81]
+
+s_add_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x81]
+
+s_add_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x81]
+
+s_add_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x81]
+
+s_add_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x81]
+
+s_add_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x81]
+
+s_add_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x81]
+
+s_add_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x81]
+
+s_add_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x81]
+
+s_add_i32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x81]
+
+s_add_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x81]
+
+s_add_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x81]
+
+s_add_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x81]
+
+s_add_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x81]
+
+s_add_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x81]
+
+s_add_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x81]
+
+s_add_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x81]
+
+s_add_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x81]
+
+s_add_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x81]
+
+s_add_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x81]
+
+s_add_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x81,0x56,0x34,0x12,0xaf]
+
+s_add_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x81,0x73,0x72,0x71,0x3f]
+
+s_add_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x81]
+
+s_add_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x81]
+
+s_add_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x81]
+
+s_add_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x81]
+
+s_add_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x81]
+
+s_add_i32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x81]
+
+s_add_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x81]
+
+s_add_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x81]
+
+s_add_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x81]
+
+s_add_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x81]
+
+s_add_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x81]
+
+s_add_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x81]
+
+s_add_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x81]
+
+s_add_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x81]
+
+s_add_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x81]
+
+s_add_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x81]
+
+s_add_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x81,0x56,0x34,0x12,0xaf]
+
+s_add_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x81,0x73,0x72,0x71,0x3f]
+
+s_sub_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x81]
+
+s_sub_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x81]
+
+s_sub_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x81]
+
+s_sub_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x81]
+
+s_sub_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x81]
+
+s_sub_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x81]
+
+s_sub_i32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x81]
+
+s_sub_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x81]
+
+s_sub_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x81]
+
+s_sub_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x81]
+
+s_sub_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x81]
+
+s_sub_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x81]
+
+s_sub_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x81]
+
+s_sub_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x81]
+
+s_sub_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x81]
+
+s_sub_i32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x81]
+
+s_sub_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x81]
+
+s_sub_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x81]
+
+s_sub_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x81]
+
+s_sub_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x81]
+
+s_sub_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x81]
+
+s_sub_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x81]
+
+s_sub_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x81]
+
+s_sub_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x81]
+
+s_sub_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x81]
+
+s_sub_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x81]
+
+s_sub_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x81,0x56,0x34,0x12,0xaf]
+
+s_sub_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x81,0x73,0x72,0x71,0x3f]
+
+s_sub_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x81]
+
+s_sub_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x81]
+
+s_sub_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x81]
+
+s_sub_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x81]
+
+s_sub_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x81]
+
+s_sub_i32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x81]
+
+s_sub_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x81]
+
+s_sub_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x81]
+
+s_sub_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x81]
+
+s_sub_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x81]
+
+s_sub_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x81]
+
+s_sub_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x81]
+
+s_sub_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x81]
+
+s_sub_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x81]
+
+s_sub_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x81]
+
+s_sub_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x81]
+
+s_sub_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x81,0x56,0x34,0x12,0xaf]
+
+s_sub_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x81,0x73,0x72,0x71,0x3f]
+
+s_addc_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x82]
+
+s_addc_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x82]
+
+s_addc_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x82]
+
+s_addc_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x82]
+
+s_addc_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x82]
+
+s_addc_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x82]
+
+s_addc_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x82]
+
+s_addc_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x82]
+
+s_addc_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x82]
+
+s_addc_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x82]
+
+s_addc_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x82]
+
+s_addc_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x82]
+
+s_addc_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x82]
+
+s_addc_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x82]
+
+s_addc_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x82]
+
+s_addc_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x82]
+
+s_addc_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x82]
+
+s_addc_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x82]
+
+s_addc_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x82]
+
+s_addc_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x82]
+
+s_addc_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x82]
+
+s_addc_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x82]
+
+s_addc_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x82]
+
+s_addc_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x82]
+
+s_addc_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x82]
+
+s_addc_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x82]
+
+s_addc_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x82,0x56,0x34,0x12,0xaf]
+
+s_addc_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x82,0x73,0x72,0x71,0x3f]
+
+s_addc_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x82]
+
+s_addc_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x82]
+
+s_addc_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x82]
+
+s_addc_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x82]
+
+s_addc_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x82]
+
+s_addc_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x82]
+
+s_addc_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x82]
+
+s_addc_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x82]
+
+s_addc_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x82]
+
+s_addc_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x82]
+
+s_addc_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x82]
+
+s_addc_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x82]
+
+s_addc_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x82]
+
+s_addc_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x82]
+
+s_addc_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x82]
+
+s_addc_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x82]
+
+s_addc_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x82,0x56,0x34,0x12,0xaf]
+
+s_addc_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x82,0x73,0x72,0x71,0x3f]
+
+s_subb_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x82]
+
+s_subb_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x82]
+
+s_subb_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x82]
+
+s_subb_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x82]
+
+s_subb_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x82]
+
+s_subb_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x82]
+
+s_subb_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x82]
+
+s_subb_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x82]
+
+s_subb_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x82]
+
+s_subb_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x82]
+
+s_subb_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x82]
+
+s_subb_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x82]
+
+s_subb_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x82]
+
+s_subb_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x82]
+
+s_subb_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x82]
+
+s_subb_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x82]
+
+s_subb_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x82]
+
+s_subb_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x82]
+
+s_subb_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x82]
+
+s_subb_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x82]
+
+s_subb_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x82]
+
+s_subb_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x82]
+
+s_subb_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x82]
+
+s_subb_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x82]
+
+s_subb_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x82]
+
+s_subb_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x82]
+
+s_subb_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x82,0x56,0x34,0x12,0xaf]
+
+s_subb_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x82,0x73,0x72,0x71,0x3f]
+
+s_subb_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x82]
+
+s_subb_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x82]
+
+s_subb_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x82]
+
+s_subb_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x82]
+
+s_subb_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x82]
+
+s_subb_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x82]
+
+s_subb_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x82]
+
+s_subb_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x82]
+
+s_subb_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x82]
+
+s_subb_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x82]
+
+s_subb_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x82]
+
+s_subb_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x82]
+
+s_subb_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x82]
+
+s_subb_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x82]
+
+s_subb_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x82]
+
+s_subb_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x82]
+
+s_subb_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x82,0x56,0x34,0x12,0xaf]
+
+s_subb_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x82,0x73,0x72,0x71,0x3f]
+
+s_min_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x83]
+
+s_min_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x83]
+
+s_min_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x83]
+
+s_min_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x83]
+
+s_min_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x83]
+
+s_min_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x83]
+
+s_min_i32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x83]
+
+s_min_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x83]
+
+s_min_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x83]
+
+s_min_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x83]
+
+s_min_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x83]
+
+s_min_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x83]
+
+s_min_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x83]
+
+s_min_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x83]
+
+s_min_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x83]
+
+s_min_i32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x83]
+
+s_min_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x83]
+
+s_min_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x83]
+
+s_min_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x83]
+
+s_min_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x83]
+
+s_min_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x83]
+
+s_min_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x83]
+
+s_min_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x83]
+
+s_min_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x83]
+
+s_min_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x83]
+
+s_min_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x83]
+
+s_min_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x83]
+
+s_min_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x83]
+
+s_min_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x83]
+
+s_min_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x83]
+
+s_min_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x83]
+
+s_min_i32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x83]
+
+s_min_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x83]
+
+s_min_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x83]
+
+s_min_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x83]
+
+s_min_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x83]
+
+s_min_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x83]
+
+s_min_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x83]
+
+s_min_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x83]
+
+s_min_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x83]
+
+s_min_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x83]
+
+s_min_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x83]
+
+s_min_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x83]
+
+s_min_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x83]
+
+s_min_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x83]
+
+s_min_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x83]
+
+s_min_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x83]
+
+s_min_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x83]
+
+s_min_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x83]
+
+s_min_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x83]
+
+s_min_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x83]
+
+s_min_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x83]
+
+s_min_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x83]
+
+s_min_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x83]
+
+s_min_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x83]
+
+s_min_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x83]
+
+s_min_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x83]
+
+s_min_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x83]
+
+s_min_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x83]
+
+s_min_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x83]
+
+s_min_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x83]
+
+s_min_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x83]
+
+s_min_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x83]
+
+s_min_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x83]
+
+s_min_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x83]
+
+s_min_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x83]
+
+s_min_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x83]
+
+s_min_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x83]
+
+s_min_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x83,0x73,0x72,0x71,0x3f]
+
+s_min_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x83]
+
+s_min_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x83]
+
+s_min_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x83]
+
+s_min_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x83]
+
+s_min_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x83]
+
+s_min_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x83]
+
+s_min_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x83]
+
+s_min_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x83]
+
+s_min_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x83]
+
+s_min_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x83]
+
+s_min_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x83]
+
+s_min_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x83]
+
+s_min_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x83]
+
+s_min_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x83]
+
+s_min_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x83]
+
+s_min_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x83]
+
+s_min_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x83,0x56,0x34,0x12,0xaf]
+
+s_min_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x83,0x73,0x72,0x71,0x3f]
+
+s_max_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x84]
+
+s_max_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x84]
+
+s_max_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x84]
+
+s_max_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x84]
+
+s_max_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x84]
+
+s_max_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x84]
+
+s_max_i32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x84]
+
+s_max_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x84]
+
+s_max_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x84]
+
+s_max_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x84]
+
+s_max_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x84]
+
+s_max_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x84]
+
+s_max_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x84]
+
+s_max_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x84]
+
+s_max_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x84]
+
+s_max_i32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x84]
+
+s_max_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x84]
+
+s_max_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x84]
+
+s_max_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x84]
+
+s_max_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x84]
+
+s_max_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x84]
+
+s_max_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x84]
+
+s_max_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x84]
+
+s_max_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x84]
+
+s_max_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x84]
+
+s_max_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x84]
+
+s_max_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x84]
+
+s_max_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x84]
+
+s_max_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x84]
+
+s_max_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x84]
+
+s_max_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x84]
+
+s_max_i32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x84]
+
+s_max_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x84]
+
+s_max_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x84]
+
+s_max_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x84]
+
+s_max_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x84]
+
+s_max_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x84]
+
+s_max_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x84]
+
+s_max_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x84]
+
+s_max_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x84]
+
+s_max_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x84]
+
+s_max_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x84]
+
+s_max_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x84]
+
+s_max_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x84]
+
+s_max_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x84]
+
+s_max_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x84]
+
+s_max_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x84]
+
+s_max_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x84]
+
+s_max_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x84]
+
+s_max_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x84]
+
+s_max_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x84]
+
+s_max_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x84]
+
+s_max_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x84]
+
+s_max_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x84]
+
+s_max_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x84]
+
+s_max_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x84]
+
+s_max_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x84]
+
+s_max_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x84]
+
+s_max_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x84]
+
+s_max_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x84]
+
+s_max_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x84]
+
+s_max_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x84]
+
+s_max_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x84]
+
+s_max_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x84]
+
+s_max_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x84]
+
+s_max_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x84]
+
+s_max_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x84]
+
+s_max_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x84]
+
+s_max_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x84,0x73,0x72,0x71,0x3f]
+
+s_max_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x84]
+
+s_max_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x84]
+
+s_max_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x84]
+
+s_max_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x84]
+
+s_max_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x84]
+
+s_max_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x84]
+
+s_max_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x84]
+
+s_max_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x84]
+
+s_max_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x84]
+
+s_max_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x84]
+
+s_max_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x84]
+
+s_max_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x84]
+
+s_max_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x84]
+
+s_max_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x84]
+
+s_max_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x84]
+
+s_max_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x84]
+
+s_max_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x84,0x56,0x34,0x12,0xaf]
+
+s_max_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x84,0x73,0x72,0x71,0x3f]
+
+s_cselect_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x85]
+
+s_cselect_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x85]
+
+s_cselect_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x85]
+
+s_cselect_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x85]
+
+s_cselect_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x85]
+
+s_cselect_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x85]
+
+s_cselect_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x85]
+
+s_cselect_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x85]
+
+s_cselect_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x85]
+
+s_cselect_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x85]
+
+s_cselect_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x85]
+
+s_cselect_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x85]
+
+s_cselect_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x85]
+
+s_cselect_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x85]
+
+s_cselect_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x85]
+
+s_cselect_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x85]
+
+s_cselect_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x85]
+
+s_cselect_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x85]
+
+s_cselect_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x85]
+
+s_cselect_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x85]
+
+s_cselect_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x85]
+
+s_cselect_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x85]
+
+s_cselect_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x85]
+
+s_cselect_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x85]
+
+s_cselect_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x85]
+
+s_cselect_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x85]
+
+s_cselect_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x85]
+
+s_cselect_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x85]
+
+s_cselect_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x85]
+
+s_cselect_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x85]
+
+s_cselect_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x85]
+
+s_cselect_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x85]
+
+s_cselect_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x85]
+
+s_cselect_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x85]
+
+s_cselect_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x85]
+
+s_cselect_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x85]
+
+s_cselect_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x85]
+
+s_cselect_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x85]
+
+s_cselect_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x85]
+
+s_cselect_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x85]
+
+s_cselect_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x85]
+
+s_cselect_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x85]
+
+s_cselect_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x85]
+
+s_cselect_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x85]
+
+s_cselect_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x85]
+
+s_cselect_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x85]
+
+s_cselect_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x85]
+
+s_cselect_b64 ttmp[14:15], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x85]
+
+s_cselect_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x85]
+
+s_cselect_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x85]
+
+s_cselect_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x85,0x73,0x72,0x71,0x3f]
+
+s_cselect_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x85]
+
+s_cselect_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x85,0x56,0x34,0x12,0xaf]
+
+s_cselect_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x85,0x73,0x72,0x71,0x3f]
+
+s_and_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x86]
+
+s_and_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x86]
+
+s_and_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x86]
+
+s_and_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x86]
+
+s_and_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x86]
+
+s_and_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x86]
+
+s_and_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x86]
+
+s_and_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x86]
+
+s_and_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x86]
+
+s_and_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x86]
+
+s_and_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x86]
+
+s_and_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x86]
+
+s_and_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x86]
+
+s_and_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x86]
+
+s_and_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x86]
+
+s_and_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x86]
+
+s_and_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x86]
+
+s_and_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x86]
+
+s_and_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x86]
+
+s_and_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x86]
+
+s_and_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x86]
+
+s_and_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x86]
+
+s_and_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x86]
+
+s_and_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x86]
+
+s_and_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x86]
+
+s_and_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x86]
+
+s_and_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x86,0x56,0x34,0x12,0xaf]
+
+s_and_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x86,0x73,0x72,0x71,0x3f]
+
+s_and_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x86]
+
+s_and_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x86]
+
+s_and_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x86]
+
+s_and_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x86]
+
+s_and_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x86]
+
+s_and_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x86]
+
+s_and_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x86]
+
+s_and_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x86]
+
+s_and_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x86]
+
+s_and_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x86]
+
+s_and_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x86]
+
+s_and_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x86]
+
+s_and_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x86]
+
+s_and_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x86]
+
+s_and_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x86]
+
+s_and_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x86]
+
+s_and_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x86,0x56,0x34,0x12,0xaf]
+
+s_and_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x86,0x73,0x72,0x71,0x3f]
+
+s_and_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x86]
+
+s_and_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x86]
+
+s_and_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x86]
+
+s_and_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x86]
+
+s_and_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x86]
+
+s_and_b64 ttmp[14:15], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x86]
+
+s_and_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x86]
+
+s_and_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x86]
+
+s_and_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x86,0x56,0x34,0x12,0xaf]
+
+s_and_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x86,0x73,0x72,0x71,0x3f]
+
+s_and_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x86]
+
+s_and_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x86,0x56,0x34,0x12,0xaf]
+
+s_and_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x86,0x73,0x72,0x71,0x3f]
+
+s_or_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x87]
+
+s_or_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x87]
+
+s_or_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x87]
+
+s_or_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x87]
+
+s_or_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x87]
+
+s_or_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x87]
+
+s_or_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x87]
+
+s_or_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x87]
+
+s_or_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x87]
+
+s_or_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x87]
+
+s_or_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x87]
+
+s_or_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x87]
+
+s_or_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x87]
+
+s_or_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x87]
+
+s_or_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x87]
+
+s_or_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x87]
+
+s_or_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x87]
+
+s_or_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x87]
+
+s_or_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x87]
+
+s_or_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x87]
+
+s_or_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x87]
+
+s_or_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x87]
+
+s_or_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x87]
+
+s_or_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x87]
+
+s_or_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x87]
+
+s_or_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x87]
+
+s_or_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x87,0x56,0x34,0x12,0xaf]
+
+s_or_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x87,0x73,0x72,0x71,0x3f]
+
+s_or_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x87]
+
+s_or_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x87]
+
+s_or_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x87]
+
+s_or_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x87]
+
+s_or_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x87]
+
+s_or_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x87]
+
+s_or_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x87]
+
+s_or_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x87]
+
+s_or_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x87]
+
+s_or_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x87]
+
+s_or_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x87]
+
+s_or_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x87]
+
+s_or_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x87]
+
+s_or_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x87]
+
+s_or_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x87]
+
+s_or_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x87]
+
+s_or_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x87,0x56,0x34,0x12,0xaf]
+
+s_or_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x87,0x73,0x72,0x71,0x3f]
+
+s_or_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x87]
+
+s_or_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x87]
+
+s_or_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x87]
+
+s_or_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x87]
+
+s_or_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x87]
+
+s_or_b64 ttmp[14:15], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x87]
+
+s_or_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x87]
+
+s_or_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x87]
+
+s_or_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x87,0x56,0x34,0x12,0xaf]
+
+s_or_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x87,0x73,0x72,0x71,0x3f]
+
+s_or_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x87]
+
+s_or_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x87,0x56,0x34,0x12,0xaf]
+
+s_or_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x87,0x73,0x72,0x71,0x3f]
+
+s_xor_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x88]
+
+s_xor_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x88]
+
+s_xor_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x88]
+
+s_xor_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x88]
+
+s_xor_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x88]
+
+s_xor_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x88]
+
+s_xor_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x88]
+
+s_xor_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x88]
+
+s_xor_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x88]
+
+s_xor_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x88]
+
+s_xor_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x88]
+
+s_xor_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x88]
+
+s_xor_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x88]
+
+s_xor_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x88]
+
+s_xor_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x88]
+
+s_xor_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x88]
+
+s_xor_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x88]
+
+s_xor_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x88]
+
+s_xor_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x88]
+
+s_xor_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x88]
+
+s_xor_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x88]
+
+s_xor_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x88]
+
+s_xor_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x88]
+
+s_xor_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x88]
+
+s_xor_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x88]
+
+s_xor_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x88]
+
+s_xor_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x88,0x56,0x34,0x12,0xaf]
+
+s_xor_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x88,0x73,0x72,0x71,0x3f]
+
+s_xor_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x88]
+
+s_xor_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x88]
+
+s_xor_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x88]
+
+s_xor_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x88]
+
+s_xor_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x88]
+
+s_xor_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x88]
+
+s_xor_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x88]
+
+s_xor_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x88]
+
+s_xor_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x88]
+
+s_xor_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x88]
+
+s_xor_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x88]
+
+s_xor_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x88]
+
+s_xor_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x88]
+
+s_xor_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x88]
+
+s_xor_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x88]
+
+s_xor_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x88]
+
+s_xor_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x88,0x56,0x34,0x12,0xaf]
+
+s_xor_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x88,0x73,0x72,0x71,0x3f]
+
+s_xor_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x88]
+
+s_xor_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x88]
+
+s_xor_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x88]
+
+s_xor_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x88]
+
+s_xor_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x88]
+
+s_xor_b64 ttmp[14:15], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x88]
+
+s_xor_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x88]
+
+s_xor_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x88]
+
+s_xor_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x88,0x56,0x34,0x12,0xaf]
+
+s_xor_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x88,0x73,0x72,0x71,0x3f]
+
+s_xor_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x88]
+
+s_xor_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x88,0x56,0x34,0x12,0xaf]
+
+s_xor_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x88,0x73,0x72,0x71,0x3f]
+
+s_andn2_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x89]
+
+s_andn2_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x89]
+
+s_andn2_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x89]
+
+s_andn2_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x89]
+
+s_andn2_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x89]
+
+s_andn2_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x89]
+
+s_andn2_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x89]
+
+s_andn2_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x89]
+
+s_andn2_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x89]
+
+s_andn2_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x89]
+
+s_andn2_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x89]
+
+s_andn2_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x89]
+
+s_andn2_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x89]
+
+s_andn2_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x89]
+
+s_andn2_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x89]
+
+s_andn2_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x89]
+
+s_andn2_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x89]
+
+s_andn2_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x89]
+
+s_andn2_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x89]
+
+s_andn2_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x89]
+
+s_andn2_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x89]
+
+s_andn2_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x89]
+
+s_andn2_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x89]
+
+s_andn2_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x89]
+
+s_andn2_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x89]
+
+s_andn2_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x89]
+
+s_andn2_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x89,0x56,0x34,0x12,0xaf]
+
+s_andn2_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x89,0x73,0x72,0x71,0x3f]
+
+s_andn2_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x89]
+
+s_andn2_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x89]
+
+s_andn2_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x89]
+
+s_andn2_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x89]
+
+s_andn2_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x89]
+
+s_andn2_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x89]
+
+s_andn2_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x89]
+
+s_andn2_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x89]
+
+s_andn2_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x89]
+
+s_andn2_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x89]
+
+s_andn2_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x89]
+
+s_andn2_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x89]
+
+s_andn2_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x89]
+
+s_andn2_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x89]
+
+s_andn2_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x89]
+
+s_andn2_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x89]
+
+s_andn2_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x89,0x56,0x34,0x12,0xaf]
+
+s_andn2_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x89,0x73,0x72,0x71,0x3f]
+
+s_andn2_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x89]
+
+s_andn2_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x89]
+
+s_andn2_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x89]
+
+s_andn2_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x89]
+
+s_andn2_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x89]
+
+s_andn2_b64 ttmp[14:15], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x89]
+
+s_andn2_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x89]
+
+s_andn2_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x89]
+
+s_andn2_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x89,0x56,0x34,0x12,0xaf]
+
+s_andn2_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x89,0x73,0x72,0x71,0x3f]
+
+s_andn2_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x89]
+
+s_andn2_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x89,0x56,0x34,0x12,0xaf]
+
+s_andn2_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x89,0x73,0x72,0x71,0x3f]
+
+s_orn2_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8a]
+
+s_orn2_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8a]
+
+s_orn2_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8a]
+
+s_orn2_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8a]
+
+s_orn2_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8a]
+
+s_orn2_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8a]
+
+s_orn2_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8a]
+
+s_orn2_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8a]
+
+s_orn2_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8a]
+
+s_orn2_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8a]
+
+s_orn2_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8a]
+
+s_orn2_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8a,0x56,0x34,0x12,0xaf]
+
+s_orn2_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8a,0x73,0x72,0x71,0x3f]
+
+s_orn2_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8a]
+
+s_orn2_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8a]
+
+s_orn2_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8a]
+
+s_orn2_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8a]
+
+s_orn2_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8a]
+
+s_orn2_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x8a]
+
+s_orn2_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8a]
+
+s_orn2_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8a]
+
+s_orn2_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8a]
+
+s_orn2_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8a]
+
+s_orn2_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8a]
+
+s_orn2_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8a]
+
+s_orn2_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8a]
+
+s_orn2_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8a]
+
+s_orn2_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8a]
+
+s_orn2_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8a]
+
+s_orn2_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8a,0x56,0x34,0x12,0xaf]
+
+s_orn2_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8a,0x73,0x72,0x71,0x3f]
+
+s_orn2_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8a]
+
+s_orn2_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x8a]
+
+s_orn2_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8a]
+
+s_orn2_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8a]
+
+s_orn2_b64 ttmp[14:15], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8a]
+
+s_orn2_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8a]
+
+s_orn2_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8a,0x56,0x34,0x12,0xaf]
+
+s_orn2_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8a,0x73,0x72,0x71,0x3f]
+
+s_orn2_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8a]
+
+s_orn2_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8a,0x56,0x34,0x12,0xaf]
+
+s_orn2_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8a,0x73,0x72,0x71,0x3f]
+
+s_nand_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8b]
+
+s_nand_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8b]
+
+s_nand_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8b]
+
+s_nand_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8b]
+
+s_nand_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8b]
+
+s_nand_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8b]
+
+s_nand_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8b]
+
+s_nand_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8b]
+
+s_nand_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8b]
+
+s_nand_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8b]
+
+s_nand_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8b]
+
+s_nand_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8b]
+
+s_nand_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8b]
+
+s_nand_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8b]
+
+s_nand_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8b]
+
+s_nand_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x8b]
+
+s_nand_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8b]
+
+s_nand_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8b]
+
+s_nand_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8b]
+
+s_nand_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8b]
+
+s_nand_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8b]
+
+s_nand_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8b]
+
+s_nand_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8b]
+
+s_nand_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8b]
+
+s_nand_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8b]
+
+s_nand_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8b]
+
+s_nand_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8b,0x56,0x34,0x12,0xaf]
+
+s_nand_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8b,0x73,0x72,0x71,0x3f]
+
+s_nand_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8b]
+
+s_nand_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8b]
+
+s_nand_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8b]
+
+s_nand_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8b]
+
+s_nand_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8b]
+
+s_nand_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x8b]
+
+s_nand_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8b]
+
+s_nand_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8b]
+
+s_nand_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8b]
+
+s_nand_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8b]
+
+s_nand_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8b]
+
+s_nand_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8b]
+
+s_nand_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8b]
+
+s_nand_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8b]
+
+s_nand_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8b]
+
+s_nand_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8b]
+
+s_nand_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8b,0x56,0x34,0x12,0xaf]
+
+s_nand_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8b,0x73,0x72,0x71,0x3f]
+
+s_nand_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8b]
+
+s_nand_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8b]
+
+s_nand_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x8b]
+
+s_nand_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8b]
+
+s_nand_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8b]
+
+s_nand_b64 ttmp[14:15], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8b]
+
+s_nand_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8b]
+
+s_nand_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8b]
+
+s_nand_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8b,0x56,0x34,0x12,0xaf]
+
+s_nand_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8b,0x73,0x72,0x71,0x3f]
+
+s_nand_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8b]
+
+s_nand_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8b,0x56,0x34,0x12,0xaf]
+
+s_nand_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8b,0x73,0x72,0x71,0x3f]
+
+s_nor_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8c]
+
+s_nor_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8c]
+
+s_nor_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8c]
+
+s_nor_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8c]
+
+s_nor_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8c]
+
+s_nor_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8c]
+
+s_nor_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8c]
+
+s_nor_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8c]
+
+s_nor_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8c]
+
+s_nor_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8c]
+
+s_nor_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8c]
+
+s_nor_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8c]
+
+s_nor_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8c]
+
+s_nor_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8c]
+
+s_nor_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8c]
+
+s_nor_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x8c]
+
+s_nor_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8c]
+
+s_nor_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8c]
+
+s_nor_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8c]
+
+s_nor_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8c]
+
+s_nor_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8c]
+
+s_nor_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8c]
+
+s_nor_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8c]
+
+s_nor_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8c]
+
+s_nor_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8c]
+
+s_nor_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8c]
+
+s_nor_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nor_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nor_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8c]
+
+s_nor_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8c]
+
+s_nor_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8c]
+
+s_nor_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8c]
+
+s_nor_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8c]
+
+s_nor_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x8c]
+
+s_nor_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8c]
+
+s_nor_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8c]
+
+s_nor_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8c]
+
+s_nor_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8c]
+
+s_nor_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8c]
+
+s_nor_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8c]
+
+s_nor_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8c]
+
+s_nor_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8c]
+
+s_nor_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8c]
+
+s_nor_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8c]
+
+s_nor_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nor_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nor_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8c]
+
+s_nor_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8c]
+
+s_nor_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x8c]
+
+s_nor_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8c]
+
+s_nor_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8c]
+
+s_nor_b64 ttmp[14:15], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8c]
+
+s_nor_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8c]
+
+s_nor_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8c]
+
+s_nor_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nor_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8c,0x73,0x72,0x71,0x3f]
+
+s_nor_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8c]
+
+s_nor_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8c,0x56,0x34,0x12,0xaf]
+
+s_nor_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8c,0x73,0x72,0x71,0x3f]
+
+s_xnor_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8d]
+
+s_xnor_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8d]
+
+s_xnor_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8d]
+
+s_xnor_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8d]
+
+s_xnor_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8d]
+
+s_xnor_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8d]
+
+s_xnor_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8d]
+
+s_xnor_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8d]
+
+s_xnor_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8d]
+
+s_xnor_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8d]
+
+s_xnor_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8d]
+
+s_xnor_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8d,0x56,0x34,0x12,0xaf]
+
+s_xnor_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8d,0x73,0x72,0x71,0x3f]
+
+s_xnor_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8d]
+
+s_xnor_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8d]
+
+s_xnor_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8d]
+
+s_xnor_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8d]
+
+s_xnor_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8d]
+
+s_xnor_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x8d]
+
+s_xnor_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8d]
+
+s_xnor_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8d]
+
+s_xnor_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8d]
+
+s_xnor_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8d]
+
+s_xnor_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8d]
+
+s_xnor_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8d]
+
+s_xnor_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8d]
+
+s_xnor_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8d]
+
+s_xnor_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8d]
+
+s_xnor_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8d]
+
+s_xnor_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8d,0x56,0x34,0x12,0xaf]
+
+s_xnor_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8d,0x73,0x72,0x71,0x3f]
+
+s_xnor_b64 s[10:11], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[12:13], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x8c,0x8d]
+
+s_xnor_b64 s[100:101], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe4,0x8d]
+
+s_xnor_b64 flat_scratch, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xe6,0x8d]
+
+s_xnor_b64 vcc, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xea,0x8d]
+
+s_xnor_b64 ttmp[14:15], s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfa,0x8d]
+
+s_xnor_b64 exec, s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0xfe,0x8d]
+
+s_xnor_b64 s[10:11], s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], exec, s[4:5]
+// CHECK: [0x7e,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], 0, s[4:5]
+// CHECK: [0x80,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], -1, s[4:5]
+// CHECK: [0xc1,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8d,0x56,0x34,0x12,0xaf]
+
+s_xnor_b64 s[10:11], 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x8a,0x8d,0x73,0x72,0x71,0x3f]
+
+s_xnor_b64 s[10:11], s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], vcc
+// CHECK: [0x02,0x6a,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], exec
+// CHECK: [0x02,0x7e,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8d]
+
+s_xnor_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8d,0x56,0x34,0x12,0xaf]
+
+s_xnor_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8d,0x73,0x72,0x71,0x3f]
+
+s_lshl_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8e]
+
+s_lshl_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8e]
+
+s_lshl_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8e]
+
+s_lshl_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8e]
+
+s_lshl_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8e]
+
+s_lshl_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8e]
+
+s_lshl_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8e]
+
+s_lshl_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8e]
+
+s_lshl_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8e]
+
+s_lshl_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8e]
+
+s_lshl_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8e]
+
+s_lshl_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8e,0x56,0x34,0x12,0xaf]
+
+s_lshl_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8e,0x73,0x72,0x71,0x3f]
+
+s_lshl_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8e]
+
+s_lshl_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8e]
+
+s_lshl_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8e]
+
+s_lshl_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8e]
+
+s_lshl_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8e]
+
+s_lshl_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x8e]
+
+s_lshl_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8e]
+
+s_lshl_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8e]
+
+s_lshl_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8e]
+
+s_lshl_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8e]
+
+s_lshl_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8e]
+
+s_lshl_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8e]
+
+s_lshl_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8e]
+
+s_lshl_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8e]
+
+s_lshl_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8e]
+
+s_lshl_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8e]
+
+s_lshl_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8e,0x56,0x34,0x12,0xaf]
+
+s_lshl_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8e,0x73,0x72,0x71,0x3f]
+
+s_lshl_b64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x8e]
+
+s_lshl_b64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0xe4,0x8e]
+
+s_lshl_b64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x8e]
+
+s_lshl_b64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x8e]
+
+s_lshl_b64 ttmp[14:15], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x8e]
+
+s_lshl_b64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x8e]
+
+s_lshl_b64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], ttmp[14:15], s2
+// CHECK: [0x7a,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x8e,0x56,0x34,0x12,0xaf]
+
+s_lshl_b64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x8e,0x73,0x72,0x71,0x3f]
+
+s_lshl_b64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], ttmp15
+// CHECK: [0x02,0x7b,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8e]
+
+s_lshl_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8e,0x56,0x34,0x12,0xaf]
+
+s_lshl_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8e,0x73,0x72,0x71,0x3f]
+
+s_lshr_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x8f]
+
+s_lshr_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x8f]
+
+s_lshr_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x8f]
+
+s_lshr_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x8f]
+
+s_lshr_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x8f]
+
+s_lshr_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x8f]
+
+s_lshr_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x8f]
+
+s_lshr_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x8f]
+
+s_lshr_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x8f]
+
+s_lshr_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x8f]
+
+s_lshr_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x8f]
+
+s_lshr_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshr_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshr_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x8f]
+
+s_lshr_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x8f]
+
+s_lshr_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x8f]
+
+s_lshr_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x8f]
+
+s_lshr_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x8f]
+
+s_lshr_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x8f]
+
+s_lshr_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x8f]
+
+s_lshr_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x8f]
+
+s_lshr_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x8f]
+
+s_lshr_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x8f]
+
+s_lshr_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x8f]
+
+s_lshr_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x8f]
+
+s_lshr_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x8f]
+
+s_lshr_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x8f]
+
+s_lshr_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x8f]
+
+s_lshr_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x8f]
+
+s_lshr_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshr_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshr_b64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x8f]
+
+s_lshr_b64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0xe4,0x8f]
+
+s_lshr_b64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x8f]
+
+s_lshr_b64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x8f]
+
+s_lshr_b64 ttmp[14:15], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x8f]
+
+s_lshr_b64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x8f]
+
+s_lshr_b64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], ttmp[14:15], s2
+// CHECK: [0x7a,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshr_b64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x8f,0x73,0x72,0x71,0x3f]
+
+s_lshr_b64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], ttmp15
+// CHECK: [0x02,0x7b,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x8f]
+
+s_lshr_b64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x8f,0x56,0x34,0x12,0xaf]
+
+s_lshr_b64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x8f,0x73,0x72,0x71,0x3f]
+
+s_ashr_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x90]
+
+s_ashr_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x90]
+
+s_ashr_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x90]
+
+s_ashr_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x90]
+
+s_ashr_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x90]
+
+s_ashr_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x90]
+
+s_ashr_i32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x90]
+
+s_ashr_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x90]
+
+s_ashr_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x90]
+
+s_ashr_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x90]
+
+s_ashr_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x90]
+
+s_ashr_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x90]
+
+s_ashr_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x90]
+
+s_ashr_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x90]
+
+s_ashr_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x90]
+
+s_ashr_i32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x90]
+
+s_ashr_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x90]
+
+s_ashr_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x90]
+
+s_ashr_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x90]
+
+s_ashr_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x90]
+
+s_ashr_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x90]
+
+s_ashr_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x90]
+
+s_ashr_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x90]
+
+s_ashr_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x90]
+
+s_ashr_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x90]
+
+s_ashr_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x90]
+
+s_ashr_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x90,0x56,0x34,0x12,0xaf]
+
+s_ashr_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x90,0x73,0x72,0x71,0x3f]
+
+s_ashr_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x90]
+
+s_ashr_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x90]
+
+s_ashr_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x90]
+
+s_ashr_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x90]
+
+s_ashr_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x90]
+
+s_ashr_i32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x90]
+
+s_ashr_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x90]
+
+s_ashr_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x90]
+
+s_ashr_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x90]
+
+s_ashr_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x90]
+
+s_ashr_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x90]
+
+s_ashr_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x90]
+
+s_ashr_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x90]
+
+s_ashr_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x90]
+
+s_ashr_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x90]
+
+s_ashr_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x90]
+
+s_ashr_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x90,0x56,0x34,0x12,0xaf]
+
+s_ashr_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x90,0x73,0x72,0x71,0x3f]
+
+s_ashr_i64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x90]
+
+s_ashr_i64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x90]
+
+s_ashr_i64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0xe4,0x90]
+
+s_ashr_i64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x90]
+
+s_ashr_i64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x90]
+
+s_ashr_i64 ttmp[14:15], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x90]
+
+s_ashr_i64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x90]
+
+s_ashr_i64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], ttmp[14:15], s2
+// CHECK: [0x7a,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x90]
+
+s_ashr_i64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x90,0x56,0x34,0x12,0xaf]
+
+s_ashr_i64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x90,0x73,0x72,0x71,0x3f]
+
+s_ashr_i64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], ttmp15
+// CHECK: [0x02,0x7b,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x90]
+
+s_ashr_i64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x90,0x56,0x34,0x12,0xaf]
+
+s_ashr_i64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x90,0x73,0x72,0x71,0x3f]
+
+s_bfm_b32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x91]
+
+s_bfm_b32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x91]
+
+s_bfm_b32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x91]
+
+s_bfm_b32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x91]
+
+s_bfm_b32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x91]
+
+s_bfm_b32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x91]
+
+s_bfm_b32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x91]
+
+s_bfm_b32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x91]
+
+s_bfm_b32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x91]
+
+s_bfm_b32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x91]
+
+s_bfm_b32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x91]
+
+s_bfm_b32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x91]
+
+s_bfm_b32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x91]
+
+s_bfm_b32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x91]
+
+s_bfm_b32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x91]
+
+s_bfm_b32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x91]
+
+s_bfm_b32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x91]
+
+s_bfm_b32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x91]
+
+s_bfm_b32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x91]
+
+s_bfm_b32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x91]
+
+s_bfm_b32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x91]
+
+s_bfm_b32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x91]
+
+s_bfm_b32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x91]
+
+s_bfm_b32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x91]
+
+s_bfm_b32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x91]
+
+s_bfm_b32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x91]
+
+s_bfm_b32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x91,0x56,0x34,0x12,0xaf]
+
+s_bfm_b32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x91,0x73,0x72,0x71,0x3f]
+
+s_bfm_b32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x91]
+
+s_bfm_b32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x91]
+
+s_bfm_b32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x91]
+
+s_bfm_b32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x91]
+
+s_bfm_b32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x91]
+
+s_bfm_b32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x91]
+
+s_bfm_b32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x91]
+
+s_bfm_b32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x91]
+
+s_bfm_b32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x91]
+
+s_bfm_b32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x91]
+
+s_bfm_b32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x91]
+
+s_bfm_b32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x91]
+
+s_bfm_b32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x91]
+
+s_bfm_b32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x91]
+
+s_bfm_b32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x91]
+
+s_bfm_b32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x91]
+
+s_bfm_b32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x91,0x56,0x34,0x12,0xaf]
+
+s_bfm_b32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x91,0x73,0x72,0x71,0x3f]
+
+s_bfm_b64 s[10:11], s1, s2
+// CHECK: [0x01,0x02,0x8a,0x91]
+
+s_bfm_b64 s[12:13], s1, s2
+// CHECK: [0x01,0x02,0x8c,0x91]
+
+s_bfm_b64 s[100:101], s1, s2
+// CHECK: [0x01,0x02,0xe4,0x91]
+
+s_bfm_b64 flat_scratch, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x91]
+
+s_bfm_b64 vcc, s1, s2
+// CHECK: [0x01,0x02,0xea,0x91]
+
+s_bfm_b64 ttmp[14:15], s1, s2
+// CHECK: [0x01,0x02,0xfa,0x91]
+
+s_bfm_b64 exec, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x91]
+
+s_bfm_b64 s[10:11], s101, s2
+// CHECK: [0x65,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], vcc_lo, s2
+// CHECK: [0x6a,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], vcc_hi, s2
+// CHECK: [0x6b,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], ttmp15, s2
+// CHECK: [0x7b,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], m0, s2
+// CHECK: [0x7c,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], exec_lo, s2
+// CHECK: [0x7e,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], exec_hi, s2
+// CHECK: [0x7f,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x91]
+
+s_bfm_b64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x91,0x56,0x34,0x12,0xaf]
+
+s_bfm_b64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x91,0x73,0x72,0x71,0x3f]
+
+s_bfm_b64 s[10:11], s1, s101
+// CHECK: [0x01,0x65,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, vcc_lo
+// CHECK: [0x01,0x6a,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, vcc_hi
+// CHECK: [0x01,0x6b,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, ttmp15
+// CHECK: [0x01,0x7b,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, m0
+// CHECK: [0x01,0x7c,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, exec_lo
+// CHECK: [0x01,0x7e,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, exec_hi
+// CHECK: [0x01,0x7f,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, 0
+// CHECK: [0x01,0x80,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, -1
+// CHECK: [0x01,0xc1,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, 0.5
+// CHECK: [0x01,0xf0,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, -4.0
+// CHECK: [0x01,0xf7,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, src_vccz
+// CHECK: [0x01,0xfb,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, src_execz
+// CHECK: [0x01,0xfc,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, src_scc
+// CHECK: [0x01,0xfd,0x8a,0x91]
+
+s_bfm_b64 s[10:11], s1, 0xaf123456
+// CHECK: [0x01,0xff,0x8a,0x91,0x56,0x34,0x12,0xaf]
+
+s_bfm_b64 s[10:11], s1, 0x3f717273
+// CHECK: [0x01,0xff,0x8a,0x91,0x73,0x72,0x71,0x3f]
+
+s_mul_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x92]
+
+s_mul_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x92]
+
+s_mul_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x92]
+
+s_mul_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x92]
+
+s_mul_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x92]
+
+s_mul_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x92]
+
+s_mul_i32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x92]
+
+s_mul_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x92]
+
+s_mul_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x92]
+
+s_mul_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x92]
+
+s_mul_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x92]
+
+s_mul_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x92]
+
+s_mul_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x92]
+
+s_mul_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x92]
+
+s_mul_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x92]
+
+s_mul_i32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x92]
+
+s_mul_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x92]
+
+s_mul_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x92]
+
+s_mul_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x92]
+
+s_mul_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x92]
+
+s_mul_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x92]
+
+s_mul_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x92]
+
+s_mul_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x92]
+
+s_mul_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x92]
+
+s_mul_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x92]
+
+s_mul_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x92]
+
+s_mul_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x92,0x56,0x34,0x12,0xaf]
+
+s_mul_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x92,0x73,0x72,0x71,0x3f]
+
+s_mul_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x92]
+
+s_mul_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x92]
+
+s_mul_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x92]
+
+s_mul_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x92]
+
+s_mul_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x92]
+
+s_mul_i32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x92]
+
+s_mul_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x92]
+
+s_mul_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x92]
+
+s_mul_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x92]
+
+s_mul_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x92]
+
+s_mul_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x92]
+
+s_mul_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x92]
+
+s_mul_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x92]
+
+s_mul_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x92]
+
+s_mul_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x92]
+
+s_mul_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x92]
+
+s_mul_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x92,0x56,0x34,0x12,0xaf]
+
+s_mul_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfe_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x92]
+
+s_bfe_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x92]
+
+s_bfe_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x92]
+
+s_bfe_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x92]
+
+s_bfe_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x92]
+
+s_bfe_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x92]
+
+s_bfe_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x92]
+
+s_bfe_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x92]
+
+s_bfe_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x92]
+
+s_bfe_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x92]
+
+s_bfe_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x92]
+
+s_bfe_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x92]
+
+s_bfe_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x92]
+
+s_bfe_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x92]
+
+s_bfe_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x92]
+
+s_bfe_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x92]
+
+s_bfe_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x92]
+
+s_bfe_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x92]
+
+s_bfe_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x92]
+
+s_bfe_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x92]
+
+s_bfe_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x92]
+
+s_bfe_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x92]
+
+s_bfe_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x92]
+
+s_bfe_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x92]
+
+s_bfe_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x92]
+
+s_bfe_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x92]
+
+s_bfe_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfe_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfe_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x92]
+
+s_bfe_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x92]
+
+s_bfe_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x92]
+
+s_bfe_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x92]
+
+s_bfe_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x92]
+
+s_bfe_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x92]
+
+s_bfe_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x92]
+
+s_bfe_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x92]
+
+s_bfe_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x92]
+
+s_bfe_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x92]
+
+s_bfe_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x92]
+
+s_bfe_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x92]
+
+s_bfe_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x92]
+
+s_bfe_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x92]
+
+s_bfe_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x92]
+
+s_bfe_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x92]
+
+s_bfe_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x92,0x56,0x34,0x12,0xaf]
+
+s_bfe_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x92,0x73,0x72,0x71,0x3f]
+
+s_bfe_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x93]
+
+s_bfe_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x93]
+
+s_bfe_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x93]
+
+s_bfe_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x93]
+
+s_bfe_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x93]
+
+s_bfe_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x93]
+
+s_bfe_i32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x93]
+
+s_bfe_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x93]
+
+s_bfe_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x93]
+
+s_bfe_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x93]
+
+s_bfe_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x93]
+
+s_bfe_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x93]
+
+s_bfe_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x93]
+
+s_bfe_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x93]
+
+s_bfe_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x93]
+
+s_bfe_i32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x93]
+
+s_bfe_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x93]
+
+s_bfe_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x93]
+
+s_bfe_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x93]
+
+s_bfe_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x93]
+
+s_bfe_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x93]
+
+s_bfe_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x93]
+
+s_bfe_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x93]
+
+s_bfe_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x93]
+
+s_bfe_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x93]
+
+s_bfe_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x93]
+
+s_bfe_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x93]
+
+s_bfe_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x93]
+
+s_bfe_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x93]
+
+s_bfe_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x93]
+
+s_bfe_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x93]
+
+s_bfe_i32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x93]
+
+s_bfe_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x93]
+
+s_bfe_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x93]
+
+s_bfe_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x93]
+
+s_bfe_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x93]
+
+s_bfe_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x93]
+
+s_bfe_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x93]
+
+s_bfe_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x93]
+
+s_bfe_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x93]
+
+s_bfe_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x93]
+
+s_bfe_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x93]
+
+s_bfe_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_u64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x8a,0x93]
+
+s_bfe_u64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x8c,0x93]
+
+s_bfe_u64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0xe4,0x93]
+
+s_bfe_u64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0xe6,0x93]
+
+s_bfe_u64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0xea,0x93]
+
+s_bfe_u64 ttmp[14:15], s[2:3], s2
+// CHECK: [0x02,0x02,0xfa,0x93]
+
+s_bfe_u64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0xfe,0x93]
+
+s_bfe_u64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], ttmp[14:15], s2
+// CHECK: [0x7a,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x8a,0x93]
+
+s_bfe_u64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x8a,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_u64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x8a,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_u64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], ttmp15
+// CHECK: [0x02,0x7b,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x8a,0x93]
+
+s_bfe_u64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x8a,0x93,0x56,0x34,0x12,0xaf]
+
+s_bfe_u64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x8a,0x93,0x73,0x72,0x71,0x3f]
+
+s_bfe_i64 s[10:11], s[2:3], s2
+// CHECK: [0x02,0x02,0x0a,0x94]
+
+s_bfe_i64 s[12:13], s[2:3], s2
+// CHECK: [0x02,0x02,0x0c,0x94]
+
+s_bfe_i64 s[100:101], s[2:3], s2
+// CHECK: [0x02,0x02,0x64,0x94]
+
+s_bfe_i64 flat_scratch, s[2:3], s2
+// CHECK: [0x02,0x02,0x66,0x94]
+
+s_bfe_i64 vcc, s[2:3], s2
+// CHECK: [0x02,0x02,0x6a,0x94]
+
+s_bfe_i64 ttmp[14:15], s[2:3], s2
+// CHECK: [0x02,0x02,0x7a,0x94]
+
+s_bfe_i64 exec, s[2:3], s2
+// CHECK: [0x02,0x02,0x7e,0x94]
+
+s_bfe_i64 s[10:11], s[4:5], s2
+// CHECK: [0x04,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[100:101], s2
+// CHECK: [0x64,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], flat_scratch, s2
+// CHECK: [0x66,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], vcc, s2
+// CHECK: [0x6a,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], ttmp[14:15], s2
+// CHECK: [0x7a,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], exec, s2
+// CHECK: [0x7e,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], 0, s2
+// CHECK: [0x80,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], -1, s2
+// CHECK: [0xc1,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], 0.5, s2
+// CHECK: [0xf0,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], -4.0, s2
+// CHECK: [0xf7,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], src_vccz, s2
+// CHECK: [0xfb,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], src_execz, s2
+// CHECK: [0xfc,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], src_scc, s2
+// CHECK: [0xfd,0x02,0x0a,0x94]
+
+s_bfe_i64 s[10:11], 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0a,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_i64 s[10:11], 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0a,0x94,0x73,0x72,0x71,0x3f]
+
+s_bfe_i64 s[10:11], s[2:3], s101
+// CHECK: [0x02,0x65,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], ttmp15
+// CHECK: [0x02,0x7b,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], m0
+// CHECK: [0x02,0x7c,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], 0
+// CHECK: [0x02,0x80,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], -1
+// CHECK: [0x02,0xc1,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x0a,0x94]
+
+s_bfe_i64 s[10:11], s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x0a,0x94,0x56,0x34,0x12,0xaf]
+
+s_bfe_i64 s[10:11], s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x0a,0x94,0x73,0x72,0x71,0x3f]
+
+s_cbranch_g_fork s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x80,0x94]
+
+s_cbranch_g_fork s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x80,0x94]
+
+s_cbranch_g_fork s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x80,0x94]
+
+s_cbranch_g_fork flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x80,0x94]
+
+s_cbranch_g_fork vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x80,0x94]
+
+s_cbranch_g_fork ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x80,0x94]
+
+s_cbranch_g_fork exec, s[4:5]
+// CHECK: [0x7e,0x04,0x80,0x94]
+
+s_cbranch_g_fork 0, s[4:5]
+// CHECK: [0x80,0x04,0x80,0x94]
+
+s_cbranch_g_fork -1, s[4:5]
+// CHECK: [0xc1,0x04,0x80,0x94]
+
+s_cbranch_g_fork 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x80,0x94]
+
+s_cbranch_g_fork -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x80,0x94]
+
+s_cbranch_g_fork src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x80,0x94]
+
+s_cbranch_g_fork src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x80,0x94]
+
+s_cbranch_g_fork src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], vcc
+// CHECK: [0x02,0x6a,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], exec
+// CHECK: [0x02,0x7e,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], 0
+// CHECK: [0x02,0x80,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], -1
+// CHECK: [0x02,0xc1,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x80,0x94]
+
+s_cbranch_g_fork s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x80,0x94]
+
+s_absdiff_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x95]
+
+s_absdiff_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x95]
+
+s_absdiff_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x95]
+
+s_absdiff_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x95]
+
+s_absdiff_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x95]
+
+s_absdiff_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x95]
+
+s_absdiff_i32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x95]
+
+s_absdiff_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x95]
+
+s_absdiff_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x95]
+
+s_absdiff_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x95]
+
+s_absdiff_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x95]
+
+s_absdiff_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x95,0x56,0x34,0x12,0xaf]
+
+s_absdiff_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x95,0x73,0x72,0x71,0x3f]
+
+s_absdiff_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x95]
+
+s_absdiff_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x95]
+
+s_absdiff_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x95]
+
+s_absdiff_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x95]
+
+s_absdiff_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x95]
+
+s_absdiff_i32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x95]
+
+s_absdiff_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x95]
+
+s_absdiff_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x95]
+
+s_absdiff_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x95]
+
+s_absdiff_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x95]
+
+s_absdiff_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x95]
+
+s_absdiff_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x95]
+
+s_absdiff_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x95]
+
+s_absdiff_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x95]
+
+s_absdiff_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x95]
+
+s_absdiff_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x95]
+
+s_absdiff_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x95,0x56,0x34,0x12,0xaf]
+
+s_absdiff_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x95,0x73,0x72,0x71,0x3f]
+
+s_rfe_restore_b64 s[2:3], s2
+// CHECK: [0x02,0x02,0x80,0x95]
+
+s_rfe_restore_b64 s[4:5], s2
+// CHECK: [0x04,0x02,0x80,0x95]
+
+s_rfe_restore_b64 s[100:101], s2
+// CHECK: [0x64,0x02,0x80,0x95]
+
+s_rfe_restore_b64 flat_scratch, s2
+// CHECK: [0x66,0x02,0x80,0x95]
+
+s_rfe_restore_b64 vcc, s2
+// CHECK: [0x6a,0x02,0x80,0x95]
+
+s_rfe_restore_b64 ttmp[14:15], s2
+// CHECK: [0x7a,0x02,0x80,0x95]
+
+s_rfe_restore_b64 exec, s2
+// CHECK: [0x7e,0x02,0x80,0x95]
+
+s_rfe_restore_b64 0, s2
+// CHECK: [0x80,0x02,0x80,0x95]
+
+s_rfe_restore_b64 -1, s2
+// CHECK: [0xc1,0x02,0x80,0x95]
+
+s_rfe_restore_b64 0.5, s2
+// CHECK: [0xf0,0x02,0x80,0x95]
+
+s_rfe_restore_b64 -4.0, s2
+// CHECK: [0xf7,0x02,0x80,0x95]
+
+s_rfe_restore_b64 src_vccz, s2
+// CHECK: [0xfb,0x02,0x80,0x95]
+
+s_rfe_restore_b64 src_execz, s2
+// CHECK: [0xfc,0x02,0x80,0x95]
+
+s_rfe_restore_b64 src_scc, s2
+// CHECK: [0xfd,0x02,0x80,0x95]
+
+s_rfe_restore_b64 0xaf123456, s2
+// CHECK: [0xff,0x02,0x80,0x95,0x56,0x34,0x12,0xaf]
+
+s_rfe_restore_b64 0x3f717273, s2
+// CHECK: [0xff,0x02,0x80,0x95,0x73,0x72,0x71,0x3f]
+
+s_rfe_restore_b64 s[2:3], s101
+// CHECK: [0x02,0x65,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], ttmp15
+// CHECK: [0x02,0x7b,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], m0
+// CHECK: [0x02,0x7c,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], 0
+// CHECK: [0x02,0x80,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x80,0x95]
+
+s_rfe_restore_b64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x80,0x95,0x56,0x34,0x12,0xaf]
+
+s_rfe_restore_b64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x80,0x95,0x73,0x72,0x71,0x3f]
+
+s_mul_hi_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x96]
+
+s_mul_hi_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x96]
+
+s_mul_hi_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x96]
+
+s_mul_hi_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x96]
+
+s_mul_hi_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x96]
+
+s_mul_hi_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x96]
+
+s_mul_hi_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x96]
+
+s_mul_hi_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x96]
+
+s_mul_hi_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x96]
+
+s_mul_hi_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x96]
+
+s_mul_hi_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x96]
+
+s_mul_hi_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x96,0x56,0x34,0x12,0xaf]
+
+s_mul_hi_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x96,0x73,0x72,0x71,0x3f]
+
+s_mul_hi_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x96]
+
+s_mul_hi_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x96,0x56,0x34,0x12,0xaf]
+
+s_mul_hi_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x96,0x73,0x72,0x71,0x3f]
+
+s_mul_hi_i32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x96]
+
+s_mul_hi_i32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x96]
+
+s_mul_hi_i32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x96]
+
+s_mul_hi_i32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x96]
+
+s_mul_hi_i32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x96]
+
+s_mul_hi_i32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x96]
+
+s_mul_hi_i32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x96]
+
+s_mul_hi_i32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x96]
+
+s_mul_hi_i32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x96]
+
+s_mul_hi_i32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x96]
+
+s_mul_hi_i32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x96]
+
+s_mul_hi_i32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x96,0x56,0x34,0x12,0xaf]
+
+s_mul_hi_i32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x96,0x73,0x72,0x71,0x3f]
+
+s_mul_hi_i32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x96]
+
+s_mul_hi_i32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x96,0x56,0x34,0x12,0xaf]
+
+s_mul_hi_i32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x96,0x73,0x72,0x71,0x3f]
+
+s_lshl1_add_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x97]
+
+s_lshl1_add_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x97]
+
+s_lshl1_add_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x97]
+
+s_lshl1_add_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x97]
+
+s_lshl1_add_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x97]
+
+s_lshl1_add_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x97]
+
+s_lshl1_add_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x97]
+
+s_lshl1_add_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x97]
+
+s_lshl1_add_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x97]
+
+s_lshl1_add_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x97]
+
+s_lshl1_add_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x97,0x56,0x34,0x12,0xaf]
+
+s_lshl1_add_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x97,0x73,0x72,0x71,0x3f]
+
+s_lshl1_add_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x97]
+
+s_lshl1_add_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x97,0x56,0x34,0x12,0xaf]
+
+s_lshl1_add_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x97,0x73,0x72,0x71,0x3f]
+
+s_lshl2_add_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x97]
+
+s_lshl2_add_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x97]
+
+s_lshl2_add_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x97]
+
+s_lshl2_add_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x97]
+
+s_lshl2_add_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x97]
+
+s_lshl2_add_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x97]
+
+s_lshl2_add_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x97]
+
+s_lshl2_add_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x97]
+
+s_lshl2_add_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x97]
+
+s_lshl2_add_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x97]
+
+s_lshl2_add_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x97,0x56,0x34,0x12,0xaf]
+
+s_lshl2_add_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x97,0x73,0x72,0x71,0x3f]
+
+s_lshl2_add_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x97]
+
+s_lshl2_add_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x97,0x56,0x34,0x12,0xaf]
+
+s_lshl2_add_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x97,0x73,0x72,0x71,0x3f]
+
+s_lshl3_add_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x98]
+
+s_lshl3_add_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x98]
+
+s_lshl3_add_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x98]
+
+s_lshl3_add_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x98]
+
+s_lshl3_add_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x98]
+
+s_lshl3_add_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x98]
+
+s_lshl3_add_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x98]
+
+s_lshl3_add_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x98]
+
+s_lshl3_add_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x98]
+
+s_lshl3_add_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x98]
+
+s_lshl3_add_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x98,0x56,0x34,0x12,0xaf]
+
+s_lshl3_add_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x98,0x73,0x72,0x71,0x3f]
+
+s_lshl3_add_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x98]
+
+s_lshl3_add_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x98,0x56,0x34,0x12,0xaf]
+
+s_lshl3_add_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x98,0x73,0x72,0x71,0x3f]
+
+s_lshl4_add_u32 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x98]
+
+s_lshl4_add_u32 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x98]
+
+s_lshl4_add_u32 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x98]
+
+s_lshl4_add_u32 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x98]
+
+s_lshl4_add_u32 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x98]
+
+s_lshl4_add_u32 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x98]
+
+s_lshl4_add_u32 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x98]
+
+s_lshl4_add_u32 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x98]
+
+s_lshl4_add_u32 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x98]
+
+s_lshl4_add_u32 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x98]
+
+s_lshl4_add_u32 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x85,0x98,0x56,0x34,0x12,0xaf]
+
+s_lshl4_add_u32 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x85,0x98,0x73,0x72,0x71,0x3f]
+
+s_lshl4_add_u32 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x98]
+
+s_lshl4_add_u32 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x98,0x56,0x34,0x12,0xaf]
+
+s_lshl4_add_u32 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x98,0x73,0x72,0x71,0x3f]
+
+s_pack_ll_b32_b16 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x99]
+
+s_pack_ll_b32_b16 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x99]
+
+s_pack_ll_b32_b16 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x99]
+
+s_pack_ll_b32_b16 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x99]
+
+s_pack_ll_b32_b16 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x99]
+
+s_pack_ll_b32_b16 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x99]
+
+s_pack_ll_b32_b16 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x99]
+
+s_pack_ll_b32_b16 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x99]
+
+s_pack_ll_b32_b16 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x99]
+
+s_pack_ll_b32_b16 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, 0xfe0b, s2
+// CHECK: [0xff,0x02,0x05,0x99,0x0b,0xfe,0x00,0x00]
+
+s_pack_ll_b32_b16 s5, 0x3456, s2
+// CHECK: [0xff,0x02,0x05,0x99,0x56,0x34,0x00,0x00]
+
+s_pack_ll_b32_b16 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x99]
+
+s_pack_ll_b32_b16 s5, s1, 0xfe0b
+// CHECK: [0x01,0xff,0x05,0x99,0x0b,0xfe,0x00,0x00]
+
+s_pack_ll_b32_b16 s5, s1, 0x3456
+// CHECK: [0x01,0xff,0x05,0x99,0x56,0x34,0x00,0x00]
+
+s_pack_lh_b32_b16 s5, s1, s2
+// CHECK: [0x01,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s101, s1, s2
+// CHECK: [0x01,0x02,0xe5,0x99]
+
+s_pack_lh_b32_b16 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0xe6,0x99]
+
+s_pack_lh_b32_b16 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0xe7,0x99]
+
+s_pack_lh_b32_b16 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0xea,0x99]
+
+s_pack_lh_b32_b16 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0xeb,0x99]
+
+s_pack_lh_b32_b16 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0xfb,0x99]
+
+s_pack_lh_b32_b16 m0, s1, s2
+// CHECK: [0x01,0x02,0xfc,0x99]
+
+s_pack_lh_b32_b16 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0xfe,0x99]
+
+s_pack_lh_b32_b16 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0xff,0x99]
+
+s_pack_lh_b32_b16 s5, s101, s2
+// CHECK: [0x65,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, m0, s2
+// CHECK: [0x7c,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, 0, s2
+// CHECK: [0x80,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, -1, s2
+// CHECK: [0xc1,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, 0xfe0b, s2
+// CHECK: [0xff,0x02,0x85,0x99,0x0b,0xfe,0x00,0x00]
+
+s_pack_lh_b32_b16 s5, 0x3456, s2
+// CHECK: [0xff,0x02,0x85,0x99,0x56,0x34,0x00,0x00]
+
+s_pack_lh_b32_b16 s5, s1, s101
+// CHECK: [0x01,0x65,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, m0
+// CHECK: [0x01,0x7c,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, 0
+// CHECK: [0x01,0x80,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, -1
+// CHECK: [0x01,0xc1,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x85,0x99]
+
+s_pack_lh_b32_b16 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x85,0x99,0x56,0x34,0x12,0xaf]
+
+s_pack_lh_b32_b16 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x85,0x99,0x73,0x72,0x71,0x3f]
+
+s_pack_hh_b32_b16 s5, s1, s2
+// CHECK: [0x01,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s101, s1, s2
+// CHECK: [0x01,0x02,0x65,0x9a]
+
+s_pack_hh_b32_b16 flat_scratch_lo, s1, s2
+// CHECK: [0x01,0x02,0x66,0x9a]
+
+s_pack_hh_b32_b16 flat_scratch_hi, s1, s2
+// CHECK: [0x01,0x02,0x67,0x9a]
+
+s_pack_hh_b32_b16 vcc_lo, s1, s2
+// CHECK: [0x01,0x02,0x6a,0x9a]
+
+s_pack_hh_b32_b16 vcc_hi, s1, s2
+// CHECK: [0x01,0x02,0x6b,0x9a]
+
+s_pack_hh_b32_b16 ttmp15, s1, s2
+// CHECK: [0x01,0x02,0x7b,0x9a]
+
+s_pack_hh_b32_b16 m0, s1, s2
+// CHECK: [0x01,0x02,0x7c,0x9a]
+
+s_pack_hh_b32_b16 exec_lo, s1, s2
+// CHECK: [0x01,0x02,0x7e,0x9a]
+
+s_pack_hh_b32_b16 exec_hi, s1, s2
+// CHECK: [0x01,0x02,0x7f,0x9a]
+
+s_pack_hh_b32_b16 s5, s101, s2
+// CHECK: [0x65,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, m0, s2
+// CHECK: [0x7c,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, 0, s2
+// CHECK: [0x80,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, -1, s2
+// CHECK: [0xc1,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0x9a,0x56,0x34,0x12,0xaf]
+
+s_pack_hh_b32_b16 s5, 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0x9a,0x73,0x72,0x71,0x3f]
+
+s_pack_hh_b32_b16 s5, s1, s101
+// CHECK: [0x01,0x65,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, m0
+// CHECK: [0x01,0x7c,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, 0
+// CHECK: [0x01,0x80,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, -1
+// CHECK: [0x01,0xc1,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0x9a]
+
+s_pack_hh_b32_b16 s5, s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0x9a,0x56,0x34,0x12,0xaf]
+
+s_pack_hh_b32_b16 s5, s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0x9a,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sopc.s b/llvm/test/MC/AMDGPU/gfx9_asm_sopc.s
new file mode 100644
index 0000000000000..2001d9ab4f3b9
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sopc.s
@@ -0,0 +1,2113 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+s_cmp_eq_i32 s1, s2
+// CHECK: [0x01,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 s101, s2
+// CHECK: [0x65,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 m0, s2
+// CHECK: [0x7c,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 0, s2
+// CHECK: [0x80,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 -1, s2
+// CHECK: [0xc1,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x00,0xbf]
+
+s_cmp_eq_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x00,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x00,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_i32 s1, s101
+// CHECK: [0x01,0x65,0x00,0xbf]
+
+s_cmp_eq_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x00,0xbf]
+
+s_cmp_eq_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x00,0xbf]
+
+s_cmp_eq_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x00,0xbf]
+
+s_cmp_eq_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x00,0xbf]
+
+s_cmp_eq_i32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x00,0xbf]
+
+s_cmp_eq_i32 s1, m0
+// CHECK: [0x01,0x7c,0x00,0xbf]
+
+s_cmp_eq_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x00,0xbf]
+
+s_cmp_eq_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x00,0xbf]
+
+s_cmp_eq_i32 s1, 0
+// CHECK: [0x01,0x80,0x00,0xbf]
+
+s_cmp_eq_i32 s1, -1
+// CHECK: [0x01,0xc1,0x00,0xbf]
+
+s_cmp_eq_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x00,0xbf]
+
+s_cmp_eq_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x00,0xbf]
+
+s_cmp_eq_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x00,0xbf]
+
+s_cmp_eq_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x00,0xbf]
+
+s_cmp_eq_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x00,0xbf]
+
+s_cmp_eq_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x00,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x00,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_i32 s1, s2
+// CHECK: [0x01,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 s101, s2
+// CHECK: [0x65,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 m0, s2
+// CHECK: [0x7c,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 0, s2
+// CHECK: [0x80,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 -1, s2
+// CHECK: [0xc1,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x01,0xbf]
+
+s_cmp_lg_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x01,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x01,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_i32 s1, s101
+// CHECK: [0x01,0x65,0x01,0xbf]
+
+s_cmp_lg_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x01,0xbf]
+
+s_cmp_lg_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x01,0xbf]
+
+s_cmp_lg_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x01,0xbf]
+
+s_cmp_lg_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x01,0xbf]
+
+s_cmp_lg_i32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x01,0xbf]
+
+s_cmp_lg_i32 s1, m0
+// CHECK: [0x01,0x7c,0x01,0xbf]
+
+s_cmp_lg_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x01,0xbf]
+
+s_cmp_lg_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x01,0xbf]
+
+s_cmp_lg_i32 s1, 0
+// CHECK: [0x01,0x80,0x01,0xbf]
+
+s_cmp_lg_i32 s1, -1
+// CHECK: [0x01,0xc1,0x01,0xbf]
+
+s_cmp_lg_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x01,0xbf]
+
+s_cmp_lg_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x01,0xbf]
+
+s_cmp_lg_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x01,0xbf]
+
+s_cmp_lg_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x01,0xbf]
+
+s_cmp_lg_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x01,0xbf]
+
+s_cmp_lg_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x01,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x01,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_i32 s1, s2
+// CHECK: [0x01,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 s101, s2
+// CHECK: [0x65,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 m0, s2
+// CHECK: [0x7c,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 0, s2
+// CHECK: [0x80,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 -1, s2
+// CHECK: [0xc1,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x02,0xbf]
+
+s_cmp_gt_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x02,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x02,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_i32 s1, s101
+// CHECK: [0x01,0x65,0x02,0xbf]
+
+s_cmp_gt_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x02,0xbf]
+
+s_cmp_gt_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x02,0xbf]
+
+s_cmp_gt_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x02,0xbf]
+
+s_cmp_gt_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x02,0xbf]
+
+s_cmp_gt_i32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x02,0xbf]
+
+s_cmp_gt_i32 s1, m0
+// CHECK: [0x01,0x7c,0x02,0xbf]
+
+s_cmp_gt_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x02,0xbf]
+
+s_cmp_gt_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x02,0xbf]
+
+s_cmp_gt_i32 s1, 0
+// CHECK: [0x01,0x80,0x02,0xbf]
+
+s_cmp_gt_i32 s1, -1
+// CHECK: [0x01,0xc1,0x02,0xbf]
+
+s_cmp_gt_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x02,0xbf]
+
+s_cmp_gt_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x02,0xbf]
+
+s_cmp_gt_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x02,0xbf]
+
+s_cmp_gt_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x02,0xbf]
+
+s_cmp_gt_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x02,0xbf]
+
+s_cmp_gt_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x02,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x02,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_i32 s1, s2
+// CHECK: [0x01,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 s101, s2
+// CHECK: [0x65,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 m0, s2
+// CHECK: [0x7c,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 0, s2
+// CHECK: [0x80,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 -1, s2
+// CHECK: [0xc1,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x03,0xbf]
+
+s_cmp_ge_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x03,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x03,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_i32 s1, s101
+// CHECK: [0x01,0x65,0x03,0xbf]
+
+s_cmp_ge_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x03,0xbf]
+
+s_cmp_ge_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x03,0xbf]
+
+s_cmp_ge_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x03,0xbf]
+
+s_cmp_ge_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x03,0xbf]
+
+s_cmp_ge_i32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x03,0xbf]
+
+s_cmp_ge_i32 s1, m0
+// CHECK: [0x01,0x7c,0x03,0xbf]
+
+s_cmp_ge_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x03,0xbf]
+
+s_cmp_ge_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x03,0xbf]
+
+s_cmp_ge_i32 s1, 0
+// CHECK: [0x01,0x80,0x03,0xbf]
+
+s_cmp_ge_i32 s1, -1
+// CHECK: [0x01,0xc1,0x03,0xbf]
+
+s_cmp_ge_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x03,0xbf]
+
+s_cmp_ge_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x03,0xbf]
+
+s_cmp_ge_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x03,0xbf]
+
+s_cmp_ge_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x03,0xbf]
+
+s_cmp_ge_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x03,0xbf]
+
+s_cmp_ge_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x03,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x03,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_i32 s1, s2
+// CHECK: [0x01,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 s101, s2
+// CHECK: [0x65,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 m0, s2
+// CHECK: [0x7c,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 0, s2
+// CHECK: [0x80,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 -1, s2
+// CHECK: [0xc1,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x04,0xbf]
+
+s_cmp_lt_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x04,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x04,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_i32 s1, s101
+// CHECK: [0x01,0x65,0x04,0xbf]
+
+s_cmp_lt_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x04,0xbf]
+
+s_cmp_lt_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x04,0xbf]
+
+s_cmp_lt_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x04,0xbf]
+
+s_cmp_lt_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x04,0xbf]
+
+s_cmp_lt_i32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x04,0xbf]
+
+s_cmp_lt_i32 s1, m0
+// CHECK: [0x01,0x7c,0x04,0xbf]
+
+s_cmp_lt_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x04,0xbf]
+
+s_cmp_lt_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x04,0xbf]
+
+s_cmp_lt_i32 s1, 0
+// CHECK: [0x01,0x80,0x04,0xbf]
+
+s_cmp_lt_i32 s1, -1
+// CHECK: [0x01,0xc1,0x04,0xbf]
+
+s_cmp_lt_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x04,0xbf]
+
+s_cmp_lt_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x04,0xbf]
+
+s_cmp_lt_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x04,0xbf]
+
+s_cmp_lt_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x04,0xbf]
+
+s_cmp_lt_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x04,0xbf]
+
+s_cmp_lt_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x04,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x04,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_i32 s1, s2
+// CHECK: [0x01,0x02,0x05,0xbf]
+
+s_cmp_le_i32 s101, s2
+// CHECK: [0x65,0x02,0x05,0xbf]
+
+s_cmp_le_i32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x05,0xbf]
+
+s_cmp_le_i32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x05,0xbf]
+
+s_cmp_le_i32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x05,0xbf]
+
+s_cmp_le_i32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x05,0xbf]
+
+s_cmp_le_i32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x05,0xbf]
+
+s_cmp_le_i32 m0, s2
+// CHECK: [0x7c,0x02,0x05,0xbf]
+
+s_cmp_le_i32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x05,0xbf]
+
+s_cmp_le_i32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x05,0xbf]
+
+s_cmp_le_i32 0, s2
+// CHECK: [0x80,0x02,0x05,0xbf]
+
+s_cmp_le_i32 -1, s2
+// CHECK: [0xc1,0x02,0x05,0xbf]
+
+s_cmp_le_i32 0.5, s2
+// CHECK: [0xf0,0x02,0x05,0xbf]
+
+s_cmp_le_i32 -4.0, s2
+// CHECK: [0xf7,0x02,0x05,0xbf]
+
+s_cmp_le_i32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x05,0xbf]
+
+s_cmp_le_i32 src_execz, s2
+// CHECK: [0xfc,0x02,0x05,0xbf]
+
+s_cmp_le_i32 src_scc, s2
+// CHECK: [0xfd,0x02,0x05,0xbf]
+
+s_cmp_le_i32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x05,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_i32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x05,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_i32 s1, s101
+// CHECK: [0x01,0x65,0x05,0xbf]
+
+s_cmp_le_i32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x05,0xbf]
+
+s_cmp_le_i32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x05,0xbf]
+
+s_cmp_le_i32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x05,0xbf]
+
+s_cmp_le_i32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x05,0xbf]
+
+s_cmp_le_i32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x05,0xbf]
+
+s_cmp_le_i32 s1, m0
+// CHECK: [0x01,0x7c,0x05,0xbf]
+
+s_cmp_le_i32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x05,0xbf]
+
+s_cmp_le_i32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x05,0xbf]
+
+s_cmp_le_i32 s1, 0
+// CHECK: [0x01,0x80,0x05,0xbf]
+
+s_cmp_le_i32 s1, -1
+// CHECK: [0x01,0xc1,0x05,0xbf]
+
+s_cmp_le_i32 s1, 0.5
+// CHECK: [0x01,0xf0,0x05,0xbf]
+
+s_cmp_le_i32 s1, -4.0
+// CHECK: [0x01,0xf7,0x05,0xbf]
+
+s_cmp_le_i32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x05,0xbf]
+
+s_cmp_le_i32 s1, src_execz
+// CHECK: [0x01,0xfc,0x05,0xbf]
+
+s_cmp_le_i32 s1, src_scc
+// CHECK: [0x01,0xfd,0x05,0xbf]
+
+s_cmp_le_i32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x05,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_i32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x05,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u32 s1, s2
+// CHECK: [0x01,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 s101, s2
+// CHECK: [0x65,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 m0, s2
+// CHECK: [0x7c,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 0, s2
+// CHECK: [0x80,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 -1, s2
+// CHECK: [0xc1,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x06,0xbf]
+
+s_cmp_eq_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x06,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x06,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u32 s1, s101
+// CHECK: [0x01,0x65,0x06,0xbf]
+
+s_cmp_eq_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x06,0xbf]
+
+s_cmp_eq_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x06,0xbf]
+
+s_cmp_eq_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x06,0xbf]
+
+s_cmp_eq_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x06,0xbf]
+
+s_cmp_eq_u32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x06,0xbf]
+
+s_cmp_eq_u32 s1, m0
+// CHECK: [0x01,0x7c,0x06,0xbf]
+
+s_cmp_eq_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x06,0xbf]
+
+s_cmp_eq_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x06,0xbf]
+
+s_cmp_eq_u32 s1, 0
+// CHECK: [0x01,0x80,0x06,0xbf]
+
+s_cmp_eq_u32 s1, -1
+// CHECK: [0x01,0xc1,0x06,0xbf]
+
+s_cmp_eq_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x06,0xbf]
+
+s_cmp_eq_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x06,0xbf]
+
+s_cmp_eq_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x06,0xbf]
+
+s_cmp_eq_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x06,0xbf]
+
+s_cmp_eq_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x06,0xbf]
+
+s_cmp_eq_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x06,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x06,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u32 s1, s2
+// CHECK: [0x01,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 s101, s2
+// CHECK: [0x65,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 m0, s2
+// CHECK: [0x7c,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 0, s2
+// CHECK: [0x80,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 -1, s2
+// CHECK: [0xc1,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x07,0xbf]
+
+s_cmp_lg_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x07,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x07,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u32 s1, s101
+// CHECK: [0x01,0x65,0x07,0xbf]
+
+s_cmp_lg_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x07,0xbf]
+
+s_cmp_lg_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x07,0xbf]
+
+s_cmp_lg_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x07,0xbf]
+
+s_cmp_lg_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x07,0xbf]
+
+s_cmp_lg_u32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x07,0xbf]
+
+s_cmp_lg_u32 s1, m0
+// CHECK: [0x01,0x7c,0x07,0xbf]
+
+s_cmp_lg_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x07,0xbf]
+
+s_cmp_lg_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x07,0xbf]
+
+s_cmp_lg_u32 s1, 0
+// CHECK: [0x01,0x80,0x07,0xbf]
+
+s_cmp_lg_u32 s1, -1
+// CHECK: [0x01,0xc1,0x07,0xbf]
+
+s_cmp_lg_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x07,0xbf]
+
+s_cmp_lg_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x07,0xbf]
+
+s_cmp_lg_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x07,0xbf]
+
+s_cmp_lg_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x07,0xbf]
+
+s_cmp_lg_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x07,0xbf]
+
+s_cmp_lg_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x07,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x07,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_u32 s1, s2
+// CHECK: [0x01,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 s101, s2
+// CHECK: [0x65,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 m0, s2
+// CHECK: [0x7c,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 0, s2
+// CHECK: [0x80,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 -1, s2
+// CHECK: [0xc1,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x08,0xbf]
+
+s_cmp_gt_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x08,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x08,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_gt_u32 s1, s101
+// CHECK: [0x01,0x65,0x08,0xbf]
+
+s_cmp_gt_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x08,0xbf]
+
+s_cmp_gt_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x08,0xbf]
+
+s_cmp_gt_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x08,0xbf]
+
+s_cmp_gt_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x08,0xbf]
+
+s_cmp_gt_u32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x08,0xbf]
+
+s_cmp_gt_u32 s1, m0
+// CHECK: [0x01,0x7c,0x08,0xbf]
+
+s_cmp_gt_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x08,0xbf]
+
+s_cmp_gt_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x08,0xbf]
+
+s_cmp_gt_u32 s1, 0
+// CHECK: [0x01,0x80,0x08,0xbf]
+
+s_cmp_gt_u32 s1, -1
+// CHECK: [0x01,0xc1,0x08,0xbf]
+
+s_cmp_gt_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x08,0xbf]
+
+s_cmp_gt_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x08,0xbf]
+
+s_cmp_gt_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x08,0xbf]
+
+s_cmp_gt_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x08,0xbf]
+
+s_cmp_gt_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x08,0xbf]
+
+s_cmp_gt_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x08,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_gt_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x08,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_u32 s1, s2
+// CHECK: [0x01,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 s101, s2
+// CHECK: [0x65,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 m0, s2
+// CHECK: [0x7c,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 0, s2
+// CHECK: [0x80,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 -1, s2
+// CHECK: [0xc1,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x09,0xbf]
+
+s_cmp_ge_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x09,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x09,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_ge_u32 s1, s101
+// CHECK: [0x01,0x65,0x09,0xbf]
+
+s_cmp_ge_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x09,0xbf]
+
+s_cmp_ge_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x09,0xbf]
+
+s_cmp_ge_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x09,0xbf]
+
+s_cmp_ge_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x09,0xbf]
+
+s_cmp_ge_u32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x09,0xbf]
+
+s_cmp_ge_u32 s1, m0
+// CHECK: [0x01,0x7c,0x09,0xbf]
+
+s_cmp_ge_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x09,0xbf]
+
+s_cmp_ge_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x09,0xbf]
+
+s_cmp_ge_u32 s1, 0
+// CHECK: [0x01,0x80,0x09,0xbf]
+
+s_cmp_ge_u32 s1, -1
+// CHECK: [0x01,0xc1,0x09,0xbf]
+
+s_cmp_ge_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x09,0xbf]
+
+s_cmp_ge_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x09,0xbf]
+
+s_cmp_ge_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x09,0xbf]
+
+s_cmp_ge_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x09,0xbf]
+
+s_cmp_ge_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x09,0xbf]
+
+s_cmp_ge_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x09,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_ge_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x09,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_u32 s1, s2
+// CHECK: [0x01,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 s101, s2
+// CHECK: [0x65,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 m0, s2
+// CHECK: [0x7c,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 0, s2
+// CHECK: [0x80,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 -1, s2
+// CHECK: [0xc1,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0a,0xbf]
+
+s_cmp_lt_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0a,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0a,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lt_u32 s1, s101
+// CHECK: [0x01,0x65,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, m0
+// CHECK: [0x01,0x7c,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, 0
+// CHECK: [0x01,0x80,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, -1
+// CHECK: [0x01,0xc1,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0a,0xbf]
+
+s_cmp_lt_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0a,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lt_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0a,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_u32 s1, s2
+// CHECK: [0x01,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 s101, s2
+// CHECK: [0x65,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 m0, s2
+// CHECK: [0x7c,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 0, s2
+// CHECK: [0x80,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 -1, s2
+// CHECK: [0xc1,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 0.5, s2
+// CHECK: [0xf0,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0b,0xbf]
+
+s_cmp_le_u32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0b,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_u32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0b,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_le_u32 s1, s101
+// CHECK: [0x01,0x65,0x0b,0xbf]
+
+s_cmp_le_u32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x0b,0xbf]
+
+s_cmp_le_u32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x0b,0xbf]
+
+s_cmp_le_u32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0b,0xbf]
+
+s_cmp_le_u32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0b,0xbf]
+
+s_cmp_le_u32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x0b,0xbf]
+
+s_cmp_le_u32 s1, m0
+// CHECK: [0x01,0x7c,0x0b,0xbf]
+
+s_cmp_le_u32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0b,0xbf]
+
+s_cmp_le_u32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0b,0xbf]
+
+s_cmp_le_u32 s1, 0
+// CHECK: [0x01,0x80,0x0b,0xbf]
+
+s_cmp_le_u32 s1, -1
+// CHECK: [0x01,0xc1,0x0b,0xbf]
+
+s_cmp_le_u32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0b,0xbf]
+
+s_cmp_le_u32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0b,0xbf]
+
+s_cmp_le_u32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0b,0xbf]
+
+s_cmp_le_u32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0b,0xbf]
+
+s_cmp_le_u32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0b,0xbf]
+
+s_cmp_le_u32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0b,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_le_u32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0b,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b32 s1, s2
+// CHECK: [0x01,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 s101, s2
+// CHECK: [0x65,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 m0, s2
+// CHECK: [0x7c,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 0, s2
+// CHECK: [0x80,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 -1, s2
+// CHECK: [0xc1,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 0.5, s2
+// CHECK: [0xf0,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0c,0xbf]
+
+s_bitcmp0_b32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0c,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0c,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b32 s1, s101
+// CHECK: [0x01,0x65,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, m0
+// CHECK: [0x01,0x7c,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, 0
+// CHECK: [0x01,0x80,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, -1
+// CHECK: [0x01,0xc1,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0c,0xbf]
+
+s_bitcmp0_b32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0c,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0c,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b32 s1, s2
+// CHECK: [0x01,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 s101, s2
+// CHECK: [0x65,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 vcc_lo, s2
+// CHECK: [0x6a,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 vcc_hi, s2
+// CHECK: [0x6b,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 ttmp15, s2
+// CHECK: [0x7b,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 m0, s2
+// CHECK: [0x7c,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 exec_lo, s2
+// CHECK: [0x7e,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 exec_hi, s2
+// CHECK: [0x7f,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 0, s2
+// CHECK: [0x80,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 -1, s2
+// CHECK: [0xc1,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 0.5, s2
+// CHECK: [0xf0,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 -4.0, s2
+// CHECK: [0xf7,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 src_execz, s2
+// CHECK: [0xfc,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 src_scc, s2
+// CHECK: [0xfd,0x02,0x0d,0xbf]
+
+s_bitcmp1_b32 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0d,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b32 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0d,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b32 s1, s101
+// CHECK: [0x01,0x65,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, vcc_lo
+// CHECK: [0x01,0x6a,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, vcc_hi
+// CHECK: [0x01,0x6b,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, ttmp15
+// CHECK: [0x01,0x7b,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, m0
+// CHECK: [0x01,0x7c,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, exec_lo
+// CHECK: [0x01,0x7e,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, exec_hi
+// CHECK: [0x01,0x7f,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, 0
+// CHECK: [0x01,0x80,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, -1
+// CHECK: [0x01,0xc1,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, 0.5
+// CHECK: [0x01,0xf0,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, -4.0
+// CHECK: [0x01,0xf7,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, src_vccz
+// CHECK: [0x01,0xfb,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, src_execz
+// CHECK: [0x01,0xfc,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, src_scc
+// CHECK: [0x01,0xfd,0x0d,0xbf]
+
+s_bitcmp1_b32 s1, 0xaf123456
+// CHECK: [0x01,0xff,0x0d,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b32 s1, 0x3f717273
+// CHECK: [0x01,0xff,0x0d,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b64 s[2:3], s2
+// CHECK: [0x02,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 s[4:5], s2
+// CHECK: [0x04,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 s[100:101], s2
+// CHECK: [0x64,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 flat_scratch, s2
+// CHECK: [0x66,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 vcc, s2
+// CHECK: [0x6a,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 ttmp[14:15], s2
+// CHECK: [0x7a,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 exec, s2
+// CHECK: [0x7e,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 0, s2
+// CHECK: [0x80,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 -1, s2
+// CHECK: [0xc1,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 0.5, s2
+// CHECK: [0xf0,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 -4.0, s2
+// CHECK: [0xf7,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 src_execz, s2
+// CHECK: [0xfc,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 src_scc, s2
+// CHECK: [0xfd,0x02,0x0e,0xbf]
+
+s_bitcmp0_b64 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0e,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b64 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0e,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp0_b64 s[2:3], s101
+// CHECK: [0x02,0x65,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], ttmp15
+// CHECK: [0x02,0x7b,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], m0
+// CHECK: [0x02,0x7c,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], 0
+// CHECK: [0x02,0x80,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x0e,0xbf]
+
+s_bitcmp0_b64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x0e,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp0_b64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x0e,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b64 s[2:3], s2
+// CHECK: [0x02,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 s[4:5], s2
+// CHECK: [0x04,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 s[100:101], s2
+// CHECK: [0x64,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 flat_scratch, s2
+// CHECK: [0x66,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 vcc, s2
+// CHECK: [0x6a,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 ttmp[14:15], s2
+// CHECK: [0x7a,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 exec, s2
+// CHECK: [0x7e,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 0, s2
+// CHECK: [0x80,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 -1, s2
+// CHECK: [0xc1,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 0.5, s2
+// CHECK: [0xf0,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 -4.0, s2
+// CHECK: [0xf7,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 src_vccz, s2
+// CHECK: [0xfb,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 src_execz, s2
+// CHECK: [0xfc,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 src_scc, s2
+// CHECK: [0xfd,0x02,0x0f,0xbf]
+
+s_bitcmp1_b64 0xaf123456, s2
+// CHECK: [0xff,0x02,0x0f,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b64 0x3f717273, s2
+// CHECK: [0xff,0x02,0x0f,0xbf,0x73,0x72,0x71,0x3f]
+
+s_bitcmp1_b64 s[2:3], s101
+// CHECK: [0x02,0x65,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], flat_scratch_lo
+// CHECK: [0x02,0x66,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], flat_scratch_hi
+// CHECK: [0x02,0x67,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], vcc_lo
+// CHECK: [0x02,0x6a,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], vcc_hi
+// CHECK: [0x02,0x6b,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], ttmp15
+// CHECK: [0x02,0x7b,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], m0
+// CHECK: [0x02,0x7c,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], exec_lo
+// CHECK: [0x02,0x7e,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], exec_hi
+// CHECK: [0x02,0x7f,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], 0
+// CHECK: [0x02,0x80,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x0f,0xbf]
+
+s_bitcmp1_b64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x0f,0xbf,0x56,0x34,0x12,0xaf]
+
+s_bitcmp1_b64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x0f,0xbf,0x73,0x72,0x71,0x3f]
+
+s_setvskip s1, s2
+// CHECK: [0x01,0x02,0x10,0xbf]
+
+s_setvskip s101, s2
+// CHECK: [0x65,0x02,0x10,0xbf]
+
+s_setvskip flat_scratch_lo, s2
+// CHECK: [0x66,0x02,0x10,0xbf]
+
+s_setvskip flat_scratch_hi, s2
+// CHECK: [0x67,0x02,0x10,0xbf]
+
+s_setvskip vcc_lo, s2
+// CHECK: [0x6a,0x02,0x10,0xbf]
+
+s_setvskip vcc_hi, s2
+// CHECK: [0x6b,0x02,0x10,0xbf]
+
+s_setvskip ttmp15, s2
+// CHECK: [0x7b,0x02,0x10,0xbf]
+
+s_setvskip m0, s2
+// CHECK: [0x7c,0x02,0x10,0xbf]
+
+s_setvskip exec_lo, s2
+// CHECK: [0x7e,0x02,0x10,0xbf]
+
+s_setvskip exec_hi, s2
+// CHECK: [0x7f,0x02,0x10,0xbf]
+
+s_setvskip 0, s2
+// CHECK: [0x80,0x02,0x10,0xbf]
+
+s_setvskip -1, s2
+// CHECK: [0xc1,0x02,0x10,0xbf]
+
+s_setvskip 0.5, s2
+// CHECK: [0xf0,0x02,0x10,0xbf]
+
+s_setvskip -4.0, s2
+// CHECK: [0xf7,0x02,0x10,0xbf]
+
+s_setvskip src_vccz, s2
+// CHECK: [0xfb,0x02,0x10,0xbf]
+
+s_setvskip src_execz, s2
+// CHECK: [0xfc,0x02,0x10,0xbf]
+
+s_setvskip src_scc, s2
+// CHECK: [0xfd,0x02,0x10,0xbf]
+
+s_setvskip 0xaf123456, s2
+// CHECK: [0xff,0x02,0x10,0xbf,0x56,0x34,0x12,0xaf]
+
+s_setvskip 0x3f717273, s2
+// CHECK: [0xff,0x02,0x10,0xbf,0x73,0x72,0x71,0x3f]
+
+s_setvskip s1, s101
+// CHECK: [0x01,0x65,0x10,0xbf]
+
+s_setvskip s1, flat_scratch_lo
+// CHECK: [0x01,0x66,0x10,0xbf]
+
+s_setvskip s1, flat_scratch_hi
+// CHECK: [0x01,0x67,0x10,0xbf]
+
+s_setvskip s1, vcc_lo
+// CHECK: [0x01,0x6a,0x10,0xbf]
+
+s_setvskip s1, vcc_hi
+// CHECK: [0x01,0x6b,0x10,0xbf]
+
+s_setvskip s1, ttmp15
+// CHECK: [0x01,0x7b,0x10,0xbf]
+
+s_setvskip s1, m0
+// CHECK: [0x01,0x7c,0x10,0xbf]
+
+s_setvskip s1, exec_lo
+// CHECK: [0x01,0x7e,0x10,0xbf]
+
+s_setvskip s1, exec_hi
+// CHECK: [0x01,0x7f,0x10,0xbf]
+
+s_setvskip s1, 0
+// CHECK: [0x01,0x80,0x10,0xbf]
+
+s_setvskip s1, -1
+// CHECK: [0x01,0xc1,0x10,0xbf]
+
+s_setvskip s1, 0.5
+// CHECK: [0x01,0xf0,0x10,0xbf]
+
+s_setvskip s1, -4.0
+// CHECK: [0x01,0xf7,0x10,0xbf]
+
+s_setvskip s1, src_vccz
+// CHECK: [0x01,0xfb,0x10,0xbf]
+
+s_setvskip s1, src_execz
+// CHECK: [0x01,0xfc,0x10,0xbf]
+
+s_setvskip s1, src_scc
+// CHECK: [0x01,0xfd,0x10,0xbf]
+
+s_setvskip s1, 0xaf123456
+// CHECK: [0x01,0xff,0x10,0xbf,0x56,0x34,0x12,0xaf]
+
+s_setvskip s1, 0x3f717273
+// CHECK: [0x01,0xff,0x10,0xbf,0x73,0x72,0x71,0x3f]
+
+s_set_gpr_idx_on s1, 0x0
+// CHECK: [0x01,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on s101, 0x0
+// CHECK: [0x65,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on flat_scratch_lo, 0x0
+// CHECK: [0x66,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on flat_scratch_hi, 0x0
+// CHECK: [0x67,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on vcc_lo, 0x0
+// CHECK: [0x6a,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on vcc_hi, 0x0
+// CHECK: [0x6b,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on ttmp15, 0x0
+// CHECK: [0x7b,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on m0, 0x0
+// CHECK: [0x7c,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on 0, 0x0
+// CHECK: [0x80,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on -1, 0x0
+// CHECK: [0xc1,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on 0.5, 0x0
+// CHECK: [0xf0,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on -4.0, 0x0
+// CHECK: [0xf7,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on src_vccz, 0x0
+// CHECK: [0xfb,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on src_execz, 0x0
+// CHECK: [0xfc,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on src_scc, 0x0
+// CHECK: [0xfd,0x00,0x11,0xbf]
+
+s_set_gpr_idx_on 0xaf123456, 0x0
+// CHECK: [0xff,0x00,0x11,0xbf,0x56,0x34,0x12,0xaf]
+
+s_set_gpr_idx_on 0x3f717273, 0x0
+// CHECK: [0xff,0x00,0x11,0xbf,0x73,0x72,0x71,0x3f]
+
+s_set_gpr_idx_on s1, 0x1
+// CHECK: [0x01,0x01,0x11,0xbf]
+
+s_set_gpr_idx_on s1, 0xF
+// CHECK: [0x01,0x0f,0x11,0xbf]
+
+s_cmp_eq_u64 s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 exec, s[4:5]
+// CHECK: [0x7e,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 0, s[4:5]
+// CHECK: [0x80,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 -1, s[4:5]
+// CHECK: [0xc1,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x12,0xbf]
+
+s_cmp_eq_u64 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x12,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u64 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x12,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_eq_u64 s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], vcc
+// CHECK: [0x02,0x6a,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], exec
+// CHECK: [0x02,0x7e,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], 0
+// CHECK: [0x02,0x80,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x12,0xbf]
+
+s_cmp_eq_u64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x12,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_eq_u64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x12,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u64 s[2:3], s[4:5]
+// CHECK: [0x02,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 s[4:5], s[4:5]
+// CHECK: [0x04,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 s[100:101], s[4:5]
+// CHECK: [0x64,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 flat_scratch, s[4:5]
+// CHECK: [0x66,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 vcc, s[4:5]
+// CHECK: [0x6a,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 ttmp[14:15], s[4:5]
+// CHECK: [0x7a,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 exec, s[4:5]
+// CHECK: [0x7e,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 0, s[4:5]
+// CHECK: [0x80,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 -1, s[4:5]
+// CHECK: [0xc1,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 0.5, s[4:5]
+// CHECK: [0xf0,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 -4.0, s[4:5]
+// CHECK: [0xf7,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 src_vccz, s[4:5]
+// CHECK: [0xfb,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 src_execz, s[4:5]
+// CHECK: [0xfc,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 src_scc, s[4:5]
+// CHECK: [0xfd,0x04,0x13,0xbf]
+
+s_cmp_lg_u64 0xaf123456, s[4:5]
+// CHECK: [0xff,0x04,0x13,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u64 0x3f717273, s[4:5]
+// CHECK: [0xff,0x04,0x13,0xbf,0x73,0x72,0x71,0x3f]
+
+s_cmp_lg_u64 s[2:3], s[6:7]
+// CHECK: [0x02,0x06,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], s[100:101]
+// CHECK: [0x02,0x64,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], flat_scratch
+// CHECK: [0x02,0x66,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], vcc
+// CHECK: [0x02,0x6a,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], ttmp[14:15]
+// CHECK: [0x02,0x7a,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], exec
+// CHECK: [0x02,0x7e,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], 0
+// CHECK: [0x02,0x80,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], -1
+// CHECK: [0x02,0xc1,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], 0.5
+// CHECK: [0x02,0xf0,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], -4.0
+// CHECK: [0x02,0xf7,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], src_vccz
+// CHECK: [0x02,0xfb,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], src_execz
+// CHECK: [0x02,0xfc,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], src_scc
+// CHECK: [0x02,0xfd,0x13,0xbf]
+
+s_cmp_lg_u64 s[2:3], 0xaf123456
+// CHECK: [0x02,0xff,0x13,0xbf,0x56,0x34,0x12,0xaf]
+
+s_cmp_lg_u64 s[2:3], 0x3f717273
+// CHECK: [0x02,0xff,0x13,0xbf,0x73,0x72,0x71,0x3f]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sopk.s b/llvm/test/MC/AMDGPU/gfx9_asm_sopk.s
new file mode 100644
index 0000000000000..23e2cd294f0a2
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sopk.s
@@ -0,0 +1,652 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+s_movk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x05,0xb0]
+
+s_movk_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb0]
+
+s_movk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb0]
+
+s_movk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb0]
+
+s_movk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb0]
+
+s_movk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb0]
+
+s_movk_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb0]
+
+s_movk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb0]
+
+s_movk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb0]
+
+s_movk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb0]
+
+s_movk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x05,0xb0]
+
+s_cmovk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x85,0xb0]
+
+s_cmovk_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb0]
+
+s_cmovk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb0]
+
+s_cmovk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb0]
+
+s_cmovk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb0]
+
+s_cmovk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb0]
+
+s_cmovk_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb0]
+
+s_cmovk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb0]
+
+s_cmovk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb0]
+
+s_cmovk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb0]
+
+s_cmovk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x85,0xb0]
+
+s_cmpk_eq_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb1]
+
+s_cmpk_eq_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb1]
+
+s_cmpk_eq_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb1]
+
+s_cmpk_eq_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb1]
+
+s_cmpk_eq_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb1]
+
+s_cmpk_eq_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb1]
+
+s_cmpk_eq_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb1]
+
+s_cmpk_eq_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb1]
+
+s_cmpk_eq_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb1]
+
+s_cmpk_eq_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb1]
+
+s_cmpk_eq_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb1]
+
+s_cmpk_lg_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb1]
+
+s_cmpk_lg_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb1]
+
+s_cmpk_lg_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb1]
+
+s_cmpk_lg_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb1]
+
+s_cmpk_lg_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb1]
+
+s_cmpk_lg_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb1]
+
+s_cmpk_lg_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb1]
+
+s_cmpk_lg_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb1]
+
+s_cmpk_lg_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb1]
+
+s_cmpk_lg_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb1]
+
+s_cmpk_lg_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb1]
+
+s_cmpk_gt_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb2]
+
+s_cmpk_gt_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb2]
+
+s_cmpk_gt_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb2]
+
+s_cmpk_gt_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb2]
+
+s_cmpk_gt_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb2]
+
+s_cmpk_gt_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb2]
+
+s_cmpk_gt_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb2]
+
+s_cmpk_gt_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb2]
+
+s_cmpk_gt_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb2]
+
+s_cmpk_gt_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb2]
+
+s_cmpk_gt_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb2]
+
+s_cmpk_ge_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb2]
+
+s_cmpk_ge_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb2]
+
+s_cmpk_ge_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb2]
+
+s_cmpk_ge_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb2]
+
+s_cmpk_ge_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb2]
+
+s_cmpk_ge_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb2]
+
+s_cmpk_ge_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb2]
+
+s_cmpk_ge_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb2]
+
+s_cmpk_ge_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb2]
+
+s_cmpk_ge_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb2]
+
+s_cmpk_ge_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb2]
+
+s_cmpk_lt_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb3]
+
+s_cmpk_lt_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb3]
+
+s_cmpk_lt_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb3]
+
+s_cmpk_lt_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb3]
+
+s_cmpk_lt_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb3]
+
+s_cmpk_lt_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb3]
+
+s_cmpk_lt_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb3]
+
+s_cmpk_lt_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb3]
+
+s_cmpk_lt_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb3]
+
+s_cmpk_lt_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb3]
+
+s_cmpk_lt_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb3]
+
+s_cmpk_le_i32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb3]
+
+s_cmpk_le_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb3]
+
+s_cmpk_le_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb3]
+
+s_cmpk_le_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb3]
+
+s_cmpk_le_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb3]
+
+s_cmpk_le_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb3]
+
+s_cmpk_le_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb3]
+
+s_cmpk_le_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb3]
+
+s_cmpk_le_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb3]
+
+s_cmpk_le_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb3]
+
+s_cmpk_le_i32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb3]
+
+s_cmpk_eq_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb4]
+
+s_cmpk_eq_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb4]
+
+s_cmpk_eq_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb4]
+
+s_cmpk_eq_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb4]
+
+s_cmpk_eq_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb4]
+
+s_cmpk_eq_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb4]
+
+s_cmpk_eq_u32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb4]
+
+s_cmpk_eq_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb4]
+
+s_cmpk_eq_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb4]
+
+s_cmpk_eq_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb4]
+
+s_cmpk_eq_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb4]
+
+s_cmpk_lg_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb4]
+
+s_cmpk_lg_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb4]
+
+s_cmpk_lg_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb4]
+
+s_cmpk_lg_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb4]
+
+s_cmpk_lg_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb4]
+
+s_cmpk_lg_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb4]
+
+s_cmpk_lg_u32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb4]
+
+s_cmpk_lg_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb4]
+
+s_cmpk_lg_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb4]
+
+s_cmpk_lg_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb4]
+
+s_cmpk_lg_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb4]
+
+s_cmpk_gt_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb5]
+
+s_cmpk_gt_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb5]
+
+s_cmpk_gt_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb5]
+
+s_cmpk_gt_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb5]
+
+s_cmpk_gt_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb5]
+
+s_cmpk_gt_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb5]
+
+s_cmpk_gt_u32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb5]
+
+s_cmpk_gt_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb5]
+
+s_cmpk_gt_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb5]
+
+s_cmpk_gt_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb5]
+
+s_cmpk_gt_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb5]
+
+s_cmpk_ge_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb5]
+
+s_cmpk_ge_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb5]
+
+s_cmpk_ge_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb5]
+
+s_cmpk_ge_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb5]
+
+s_cmpk_ge_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb5]
+
+s_cmpk_ge_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb5]
+
+s_cmpk_ge_u32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb5]
+
+s_cmpk_ge_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb5]
+
+s_cmpk_ge_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb5]
+
+s_cmpk_ge_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb5]
+
+s_cmpk_ge_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb5]
+
+s_cmpk_lt_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x01,0xb6]
+
+s_cmpk_lt_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb6]
+
+s_cmpk_lt_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb6]
+
+s_cmpk_lt_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb6]
+
+s_cmpk_lt_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb6]
+
+s_cmpk_lt_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb6]
+
+s_cmpk_lt_u32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb6]
+
+s_cmpk_lt_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb6]
+
+s_cmpk_lt_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb6]
+
+s_cmpk_lt_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb6]
+
+s_cmpk_lt_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x01,0xb6]
+
+s_cmpk_le_u32 s1, 0x3141
+// CHECK: [0x41,0x31,0x81,0xb6]
+
+s_cmpk_le_u32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb6]
+
+s_cmpk_le_u32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb6]
+
+s_cmpk_le_u32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb6]
+
+s_cmpk_le_u32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb6]
+
+s_cmpk_le_u32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb6]
+
+s_cmpk_le_u32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb6]
+
+s_cmpk_le_u32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb6]
+
+s_cmpk_le_u32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb6]
+
+s_cmpk_le_u32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb6]
+
+s_cmpk_le_u32 s1, 0xc1d1
+// CHECK: [0xd1,0xc1,0x81,0xb6]
+
+s_addk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x05,0xb7]
+
+s_addk_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0x65,0xb7]
+
+s_addk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0x66,0xb7]
+
+s_addk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0x67,0xb7]
+
+s_addk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0x6a,0xb7]
+
+s_addk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0x6b,0xb7]
+
+s_addk_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0x7b,0xb7]
+
+s_addk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0x7c,0xb7]
+
+s_addk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0x7e,0xb7]
+
+s_addk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0x7f,0xb7]
+
+s_addk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x05,0xb7]
+
+s_mulk_i32 s5, 0x3141
+// CHECK: [0x41,0x31,0x85,0xb7]
+
+s_mulk_i32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb7]
+
+s_mulk_i32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb7]
+
+s_mulk_i32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb7]
+
+s_mulk_i32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb7]
+
+s_mulk_i32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb7]
+
+s_mulk_i32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb7]
+
+s_mulk_i32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb7]
+
+s_mulk_i32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb7]
+
+s_mulk_i32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb7]
+
+s_mulk_i32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x85,0xb7]
+
+s_cbranch_i_fork s[2:3], 12609
+// CHECK: [0x41,0x31,0x02,0xb8]
+
+s_cbranch_i_fork s[4:5], 12609
+// CHECK: [0x41,0x31,0x04,0xb8]
+
+s_cbranch_i_fork s[100:101], 12609
+// CHECK: [0x41,0x31,0x64,0xb8]
+
+s_cbranch_i_fork flat_scratch, 12609
+// CHECK: [0x41,0x31,0x66,0xb8]
+
+s_cbranch_i_fork vcc, 12609
+// CHECK: [0x41,0x31,0x6a,0xb8]
+
+s_cbranch_i_fork ttmp[14:15], 12609
+// CHECK: [0x41,0x31,0x7a,0xb8]
+
+s_cbranch_i_fork exec, 12609
+// CHECK: [0x41,0x31,0x7e,0xb8]
+
+s_cbranch_i_fork s[2:3], 49617
+// CHECK: [0xd1,0xc1,0x02,0xb8]
+
+s_getreg_b32 s5, 0x3141
+// CHECK: [0x41,0x31,0x85,0xb8]
+
+s_getreg_b32 s101, 0x3141
+// CHECK: [0x41,0x31,0xe5,0xb8]
+
+s_getreg_b32 flat_scratch_lo, 0x3141
+// CHECK: [0x41,0x31,0xe6,0xb8]
+
+s_getreg_b32 flat_scratch_hi, 0x3141
+// CHECK: [0x41,0x31,0xe7,0xb8]
+
+s_getreg_b32 vcc_lo, 0x3141
+// CHECK: [0x41,0x31,0xea,0xb8]
+
+s_getreg_b32 vcc_hi, 0x3141
+// CHECK: [0x41,0x31,0xeb,0xb8]
+
+s_getreg_b32 ttmp15, 0x3141
+// CHECK: [0x41,0x31,0xfb,0xb8]
+
+s_getreg_b32 m0, 0x3141
+// CHECK: [0x41,0x31,0xfc,0xb8]
+
+s_getreg_b32 exec_lo, 0x3141
+// CHECK: [0x41,0x31,0xfe,0xb8]
+
+s_getreg_b32 exec_hi, 0x3141
+// CHECK: [0x41,0x31,0xff,0xb8]
+
+s_getreg_b32 s5, 0xc1d1
+// CHECK: [0xd1,0xc1,0x85,0xb8]
+
+s_setreg_b32 0x3141, s1
+// CHECK: [0x41,0x31,0x01,0xb9]
+
+s_setreg_b32 0xc1d1, s1
+// CHECK: [0xd1,0xc1,0x01,0xb9]
+
+s_setreg_b32 0x3141, s101
+// CHECK: [0x41,0x31,0x65,0xb9]
+
+s_setreg_b32 0x3141, flat_scratch_lo
+// CHECK: [0x41,0x31,0x66,0xb9]
+
+s_setreg_b32 0x3141, flat_scratch_hi
+// CHECK: [0x41,0x31,0x67,0xb9]
+
+s_setreg_b32 0x3141, vcc_lo
+// CHECK: [0x41,0x31,0x6a,0xb9]
+
+s_setreg_b32 0x3141, vcc_hi
+// CHECK: [0x41,0x31,0x6b,0xb9]
+
+s_setreg_b32 0x3141, ttmp15
+// CHECK: [0x41,0x31,0x7b,0xb9]
+
+s_setreg_b32 0x3141, m0
+// CHECK: [0x41,0x31,0x7c,0xb9]
+
+s_setreg_b32 0x3141, exec_lo
+// CHECK: [0x41,0x31,0x7e,0xb9]
+
+s_setreg_b32 0x3141, exec_hi
+// CHECK: [0x41,0x31,0x7f,0xb9]
+
+s_setreg_imm32_b32 0x3141, 0x11213141
+// CHECK: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
+
+s_setreg_imm32_b32 0xc1d1, 0x11213141
+// CHECK: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
+
+s_setreg_imm32_b32 0x3141, 0xa1b1c1d1
+// CHECK: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]
+
+s_call_b64 s[10:11], 12609
+// CHECK: [0x41,0x31,0x8a,0xba]
+
+s_call_b64 s[12:13], 12609
+// CHECK: [0x41,0x31,0x8c,0xba]
+
+s_call_b64 s[100:101], 12609
+// CHECK: [0x41,0x31,0xe4,0xba]
+
+s_call_b64 flat_scratch, 12609
+// CHECK: [0x41,0x31,0xe6,0xba]
+
+s_call_b64 vcc, 12609
+// CHECK: [0x41,0x31,0xea,0xba]
+
+s_call_b64 ttmp[14:15], 12609
+// CHECK: [0x41,0x31,0xfa,0xba]
+
+s_call_b64 exec, 12609
+// CHECK: [0x41,0x31,0xfe,0xba]
+
+s_call_b64 s[10:11], 49617
+// CHECK: [0xd1,0xc1,0x8a,0xba]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_sopp.s b/llvm/test/MC/AMDGPU/gfx9_asm_sopp.s
new file mode 100644
index 0000000000000..a19a2833a65ad
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_sopp.s
@@ -0,0 +1,166 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+s_nop 0x3141
+// CHECK: [0x41,0x31,0x80,0xbf]
+
+s_nop 0xc1d1
+// CHECK: [0xd1,0xc1,0x80,0xbf]
+
+s_endpgm
+// CHECK: [0x00,0x00,0x81,0xbf]
+
+s_branch 12609
+// CHECK: [0x41,0x31,0x82,0xbf]
+
+s_branch 49617
+// CHECK: [0xd1,0xc1,0x82,0xbf]
+
+s_wakeup
+// CHECK: [0x00,0x00,0x83,0xbf]
+
+s_cbranch_scc0 12609
+// CHECK: [0x41,0x31,0x84,0xbf]
+
+s_cbranch_scc0 49617
+// CHECK: [0xd1,0xc1,0x84,0xbf]
+
+s_cbranch_scc1 12609
+// CHECK: [0x41,0x31,0x85,0xbf]
+
+s_cbranch_scc1 49617
+// CHECK: [0xd1,0xc1,0x85,0xbf]
+
+s_cbranch_vccz 12609
+// CHECK: [0x41,0x31,0x86,0xbf]
+
+s_cbranch_vccz 49617
+// CHECK: [0xd1,0xc1,0x86,0xbf]
+
+s_cbranch_vccnz 12609
+// CHECK: [0x41,0x31,0x87,0xbf]
+
+s_cbranch_vccnz 49617
+// CHECK: [0xd1,0xc1,0x87,0xbf]
+
+s_cbranch_execz 12609
+// CHECK: [0x41,0x31,0x88,0xbf]
+
+s_cbranch_execz 49617
+// CHECK: [0xd1,0xc1,0x88,0xbf]
+
+s_cbranch_execnz 12609
+// CHECK: [0x41,0x31,0x89,0xbf]
+
+s_cbranch_execnz 49617
+// CHECK: [0xd1,0xc1,0x89,0xbf]
+
+s_barrier
+// CHECK: [0x00,0x00,0x8a,0xbf]
+
+s_setkill 0x3141
+// CHECK: [0x41,0x31,0x8b,0xbf]
+
+s_setkill 0xc1d1
+// CHECK: [0xd1,0xc1,0x8b,0xbf]
+
+s_waitcnt 0x3141
+// CHECK: [0x41,0x31,0x8c,0xbf]
+
+s_waitcnt 0xc1d1
+// CHECK: [0xd1,0xc1,0x8c,0xbf]
+
+s_sethalt 0x3141
+// CHECK: [0x41,0x31,0x8d,0xbf]
+
+s_sethalt 0xc1d1
+// CHECK: [0xd1,0xc1,0x8d,0xbf]
+
+s_sleep 0x3141
+// CHECK: [0x41,0x31,0x8e,0xbf]
+
+s_sleep 0xc1d1
+// CHECK: [0xd1,0xc1,0x8e,0xbf]
+
+s_setprio 0x3141
+// CHECK: [0x41,0x31,0x8f,0xbf]
+
+s_setprio 0xc1d1
+// CHECK: [0xd1,0xc1,0x8f,0xbf]
+
+s_sendmsg 0x3141
+// CHECK: [0x41,0x31,0x90,0xbf]
+
+s_sendmsg 0xc1d1
+// CHECK: [0xd1,0xc1,0x90,0xbf]
+
+s_sendmsghalt 0x3141
+// CHECK: [0x41,0x31,0x91,0xbf]
+
+s_sendmsghalt 0xc1d1
+// CHECK: [0xd1,0xc1,0x91,0xbf]
+
+s_trap 0x3141
+// CHECK: [0x41,0x31,0x92,0xbf]
+
+s_trap 0xc1d1
+// CHECK: [0xd1,0xc1,0x92,0xbf]
+
+s_icache_inv
+// CHECK: [0x00,0x00,0x93,0xbf]
+
+s_incperflevel 0x3141
+// CHECK: [0x41,0x31,0x94,0xbf]
+
+s_incperflevel 0xc1d1
+// CHECK: [0xd1,0xc1,0x94,0xbf]
+
+s_decperflevel 0x3141
+// CHECK: [0x41,0x31,0x95,0xbf]
+
+s_decperflevel 0xc1d1
+// CHECK: [0xd1,0xc1,0x95,0xbf]
+
+s_ttracedata
+// CHECK: [0x00,0x00,0x96,0xbf]
+
+s_cbranch_cdbgsys 12609
+// CHECK: [0x41,0x31,0x97,0xbf]
+
+s_cbranch_cdbgsys 49617
+// CHECK: [0xd1,0xc1,0x97,0xbf]
+
+s_cbranch_cdbguser 12609
+// CHECK: [0x41,0x31,0x98,0xbf]
+
+s_cbranch_cdbguser 49617
+// CHECK: [0xd1,0xc1,0x98,0xbf]
+
+s_cbranch_cdbgsys_or_user 12609
+// CHECK: [0x41,0x31,0x99,0xbf]
+
+s_cbranch_cdbgsys_or_user 49617
+// CHECK: [0xd1,0xc1,0x99,0xbf]
+
+s_cbranch_cdbgsys_and_user 12609
+// CHECK: [0x41,0x31,0x9a,0xbf]
+
+s_cbranch_cdbgsys_and_user 49617
+// CHECK: [0xd1,0xc1,0x9a,0xbf]
+
+s_endpgm_saved
+// CHECK: [0x00,0x00,0x9b,0xbf]
+
+s_set_gpr_idx_off
+// CHECK: [0x00,0x00,0x9c,0xbf]
+
+s_set_gpr_idx_mode 0x0
+// CHECK: [0x00,0x00,0x9d,0xbf]
+
+s_set_gpr_idx_mode 0x1
+// CHECK: [0x01,0x00,0x9d,0xbf]
+
+s_set_gpr_idx_mode 0xF
+// CHECK: [0x0f,0x00,0x9d,0xbf]
+
+s_endpgm_ordered_ps_done
+// CHECK: [0x00,0x00,0x9e,0xbf]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s b/llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s
new file mode 100644
index 0000000000000..06893eae141c3
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vintrp.s
@@ -0,0 +1,85 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+v_interp_p1_f32 v5, v1, attr0.x
+// CHECK: [0x01,0x00,0x14,0xd4]
+
+v_interp_p1_f32 v255, v1, attr0.x
+// CHECK: [0x01,0x00,0xfc,0xd7]
+
+v_interp_p1_f32 v5, v255, attr0.x
+// CHECK: [0xff,0x00,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr1.x
+// CHECK: [0x01,0x04,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr31.x
+// CHECK: [0x01,0x7c,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr32.x
+// CHECK: [0x01,0x80,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr0.y
+// CHECK: [0x01,0x01,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr0.z
+// CHECK: [0x01,0x02,0x14,0xd4]
+
+v_interp_p1_f32 v5, v1, attr0.w
+// CHECK: [0x01,0x03,0x14,0xd4]
+
+v_interp_p2_f32 v5, v1, attr0.x
+// CHECK: [0x01,0x00,0x15,0xd4]
+
+v_interp_p2_f32 v255, v1, attr0.x
+// CHECK: [0x01,0x00,0xfd,0xd7]
+
+v_interp_p2_f32 v5, v255, attr0.x
+// CHECK: [0xff,0x00,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr1.x
+// CHECK: [0x01,0x04,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr31.x
+// CHECK: [0x01,0x7c,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr32.x
+// CHECK: [0x01,0x80,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr0.y
+// CHECK: [0x01,0x01,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr0.z
+// CHECK: [0x01,0x02,0x15,0xd4]
+
+v_interp_p2_f32 v5, v1, attr0.w
+// CHECK: [0x01,0x03,0x15,0xd4]
+
+v_interp_mov_f32 v5, p10, attr0.x
+// CHECK: [0x00,0x00,0x16,0xd4]
+
+v_interp_mov_f32 v255, p10, attr0.x
+// CHECK: [0x00,0x00,0xfe,0xd7]
+
+v_interp_mov_f32 v5, p20, attr0.x
+// CHECK: [0x01,0x00,0x16,0xd4]
+
+v_interp_mov_f32 v5, p0, attr0.x
+// CHECK: [0x02,0x00,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr1.x
+// CHECK: [0x00,0x04,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr31.x
+// CHECK: [0x00,0x7c,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr32.x
+// CHECK: [0x00,0x80,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr0.y
+// CHECK: [0x00,0x01,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr0.z
+// CHECK: [0x00,0x02,0x16,0xd4]
+
+v_interp_mov_f32 v5, p10, attr0.w
+// CHECK: [0x00,0x03,0x16,0xd4]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop1.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop1.s
new file mode 100644
index 0000000000000..1e48240162a51
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop1.s
@@ -0,0 +1,17017 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+v_nop
+// CHECK: [0x00,0x00,0x00,0x7e]
+
+v_mov_b32 v5, v1
+// CHECK: [0x01,0x03,0x0a,0x7e]
+
+v_mov_b32 v255, v1
+// CHECK: [0x01,0x03,0xfe,0x7f]
+
+v_mov_b32 v5, v255
+// CHECK: [0xff,0x03,0x0a,0x7e]
+
+v_mov_b32 v5, s1
+// CHECK: [0x01,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, s101
+// CHECK: [0x65,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, flat_scratch_lo
+// CHECK: [0x66,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, flat_scratch_hi
+// CHECK: [0x67,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, vcc_lo
+// CHECK: [0x6a,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, vcc_hi
+// CHECK: [0x6b,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, ttmp15
+// CHECK: [0x7b,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, m0
+// CHECK: [0x7c,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, exec_lo
+// CHECK: [0x7e,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, exec_hi
+// CHECK: [0x7f,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0
+// CHECK: [0x80,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, -1
+// CHECK: [0xc1,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0.5
+// CHECK: [0xf0,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, -4.0
+// CHECK: [0xf7,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_vccz
+// CHECK: [0xfb,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_execz
+// CHECK: [0xfc,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_scc
+// CHECK: [0xfd,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x02,0x0a,0x7e]
+
+v_mov_b32 v5, 0xaf123456
+// CHECK: [0xff,0x02,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_mov_b32 v5, 0x3f717273
+// CHECK: [0xff,0x02,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_readfirstlane_b32 s5, v1
+// CHECK: [0x01,0x05,0x0a,0x7e]
+
+v_readfirstlane_b32 s101, v1
+// CHECK: [0x01,0x05,0xca,0x7e]
+
+v_readfirstlane_b32 flat_scratch_lo, v1
+// CHECK: [0x01,0x05,0xcc,0x7e]
+
+v_readfirstlane_b32 flat_scratch_hi, v1
+// CHECK: [0x01,0x05,0xce,0x7e]
+
+v_readfirstlane_b32 ttmp15, v1
+// CHECK: [0x01,0x05,0xf6,0x7e]
+
+v_readfirstlane_b32 s5, v255
+// CHECK: [0xff,0x05,0x0a,0x7e]
+
+v_readfirstlane_b32 s5, src_lds_direct
+// CHECK: [0xfe,0x04,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, v[1:2]
+// CHECK: [0x01,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64 v255, v[1:2]
+// CHECK: [0x01,0x07,0xfe,0x7f]
+
+v_cvt_i32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x07,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[2:3]
+// CHECK: [0x02,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[4:5]
+// CHECK: [0x04,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, s[100:101]
+// CHECK: [0x64,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, flat_scratch
+// CHECK: [0x66,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, vcc
+// CHECK: [0x6a,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, ttmp[14:15]
+// CHECK: [0x7a,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, exec
+// CHECK: [0x7e,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0
+// CHECK: [0x80,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, -1
+// CHECK: [0xc1,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0.5
+// CHECK: [0xf0,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, -4.0
+// CHECK: [0xf7,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_vccz
+// CHECK: [0xfb,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_execz
+// CHECK: [0xfc,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, src_scc
+// CHECK: [0xfd,0x06,0x0a,0x7e]
+
+v_cvt_i32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x06,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x06,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_i32 v[5:6], v1
+// CHECK: [0x01,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32 v[254:255], v1
+// CHECK: [0x01,0x09,0xfc,0x7f]
+
+v_cvt_f64_i32 v[5:6], v255
+// CHECK: [0xff,0x09,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], s1
+// CHECK: [0x01,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], s101
+// CHECK: [0x65,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], flat_scratch_lo
+// CHECK: [0x66,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], flat_scratch_hi
+// CHECK: [0x67,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], vcc_lo
+// CHECK: [0x6a,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], vcc_hi
+// CHECK: [0x6b,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], ttmp15
+// CHECK: [0x7b,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], m0
+// CHECK: [0x7c,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], exec_lo
+// CHECK: [0x7e,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], exec_hi
+// CHECK: [0x7f,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0
+// CHECK: [0x80,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], -1
+// CHECK: [0xc1,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0.5
+// CHECK: [0xf0,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], -4.0
+// CHECK: [0xf7,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_vccz
+// CHECK: [0xfb,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_execz
+// CHECK: [0xfc,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_scc
+// CHECK: [0xfd,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], src_lds_direct
+// CHECK: [0xfe,0x08,0x0a,0x7e]
+
+v_cvt_f64_i32 v[5:6], 0xaf123456
+// CHECK: [0xff,0x08,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_i32 v[5:6], 0x3f717273
+// CHECK: [0xff,0x08,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_i32 v5, v1
+// CHECK: [0x01,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32 v255, v1
+// CHECK: [0x01,0x0b,0xfe,0x7f]
+
+v_cvt_f32_i32 v5, v255
+// CHECK: [0xff,0x0b,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, s1
+// CHECK: [0x01,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, s101
+// CHECK: [0x65,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, flat_scratch_lo
+// CHECK: [0x66,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, flat_scratch_hi
+// CHECK: [0x67,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, vcc_lo
+// CHECK: [0x6a,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, vcc_hi
+// CHECK: [0x6b,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, ttmp15
+// CHECK: [0x7b,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, m0
+// CHECK: [0x7c,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, exec_lo
+// CHECK: [0x7e,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, exec_hi
+// CHECK: [0x7f,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0
+// CHECK: [0x80,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, -1
+// CHECK: [0xc1,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0.5
+// CHECK: [0xf0,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, -4.0
+// CHECK: [0xf7,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_vccz
+// CHECK: [0xfb,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_execz
+// CHECK: [0xfc,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_scc
+// CHECK: [0xfd,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, src_lds_direct
+// CHECK: [0xfe,0x0a,0x0a,0x7e]
+
+v_cvt_f32_i32 v5, 0xaf123456
+// CHECK: [0xff,0x0a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_i32 v5, 0x3f717273
+// CHECK: [0xff,0x0a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_u32 v5, v1
+// CHECK: [0x01,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32 v255, v1
+// CHECK: [0x01,0x0d,0xfe,0x7f]
+
+v_cvt_f32_u32 v5, v255
+// CHECK: [0xff,0x0d,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, s1
+// CHECK: [0x01,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, s101
+// CHECK: [0x65,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, flat_scratch_lo
+// CHECK: [0x66,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, flat_scratch_hi
+// CHECK: [0x67,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, vcc_lo
+// CHECK: [0x6a,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, vcc_hi
+// CHECK: [0x6b,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, ttmp15
+// CHECK: [0x7b,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, m0
+// CHECK: [0x7c,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, exec_lo
+// CHECK: [0x7e,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, exec_hi
+// CHECK: [0x7f,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0
+// CHECK: [0x80,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, -1
+// CHECK: [0xc1,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0.5
+// CHECK: [0xf0,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, -4.0
+// CHECK: [0xf7,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_vccz
+// CHECK: [0xfb,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_execz
+// CHECK: [0xfc,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_scc
+// CHECK: [0xfd,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, src_lds_direct
+// CHECK: [0xfe,0x0c,0x0a,0x7e]
+
+v_cvt_f32_u32 v5, 0xaf123456
+// CHECK: [0xff,0x0c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_u32 v5, 0x3f717273
+// CHECK: [0xff,0x0c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_u32_f32 v5, v1
+// CHECK: [0x01,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32 v255, v1
+// CHECK: [0x01,0x0f,0xfe,0x7f]
+
+v_cvt_u32_f32 v5, v255
+// CHECK: [0xff,0x0f,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, s1
+// CHECK: [0x01,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, s101
+// CHECK: [0x65,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, ttmp15
+// CHECK: [0x7b,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, m0
+// CHECK: [0x7c,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, exec_lo
+// CHECK: [0x7e,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, exec_hi
+// CHECK: [0x7f,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0
+// CHECK: [0x80,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, -1
+// CHECK: [0xc1,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0.5
+// CHECK: [0xf0,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, -4.0
+// CHECK: [0xf7,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_vccz
+// CHECK: [0xfb,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_execz
+// CHECK: [0xfc,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_scc
+// CHECK: [0xfd,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x0e,0x0a,0x7e]
+
+v_cvt_u32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x0e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x0e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_i32_f32 v5, v1
+// CHECK: [0x01,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32 v255, v1
+// CHECK: [0x01,0x11,0xfe,0x7f]
+
+v_cvt_i32_f32 v5, v255
+// CHECK: [0xff,0x11,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, s1
+// CHECK: [0x01,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, s101
+// CHECK: [0x65,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, ttmp15
+// CHECK: [0x7b,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, m0
+// CHECK: [0x7c,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0
+// CHECK: [0x80,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, -1
+// CHECK: [0xc1,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x10,0x0a,0x7e]
+
+v_cvt_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x10,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x10,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f16_f32 v5, v1
+// CHECK: [0x01,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v255, v1
+// CHECK: [0x01,0x15,0xfe,0x7f]
+
+v_cvt_f16_f32 v5, v255
+// CHECK: [0xff,0x15,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s1
+// CHECK: [0x01,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, s101
+// CHECK: [0x65,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_lo
+// CHECK: [0x6a,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, vcc_hi
+// CHECK: [0x6b,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, ttmp15
+// CHECK: [0x7b,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, m0
+// CHECK: [0x7c,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_lo
+// CHECK: [0x7e,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, exec_hi
+// CHECK: [0x7f,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0
+// CHECK: [0x80,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, -1
+// CHECK: [0xc1,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0.5
+// CHECK: [0xf0,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, -4.0
+// CHECK: [0xf7,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_vccz
+// CHECK: [0xfb,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_execz
+// CHECK: [0xfc,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_scc
+// CHECK: [0xfd,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x14,0x0a,0x7e]
+
+v_cvt_f16_f32 v5, 0xaf123456
+// CHECK: [0xff,0x14,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f16_f32 v5, 0x3f717273
+// CHECK: [0xff,0x14,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_f16 v5, v1
+// CHECK: [0x01,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v255, v1
+// CHECK: [0x01,0x17,0xfe,0x7f]
+
+v_cvt_f32_f16 v5, v255
+// CHECK: [0xff,0x17,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s1
+// CHECK: [0x01,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, s101
+// CHECK: [0x65,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_lo
+// CHECK: [0x6a,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, vcc_hi
+// CHECK: [0x6b,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, ttmp15
+// CHECK: [0x7b,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, m0
+// CHECK: [0x7c,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_lo
+// CHECK: [0x7e,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, exec_hi
+// CHECK: [0x7f,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, 0
+// CHECK: [0x80,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, -1
+// CHECK: [0xc1,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, 0.5
+// CHECK: [0xf0,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, -4.0
+// CHECK: [0xf7,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_vccz
+// CHECK: [0xfb,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_execz
+// CHECK: [0xfc,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_scc
+// CHECK: [0xfd,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x16,0x0a,0x7e]
+
+v_cvt_f32_f16 v5, 0xfe0b
+// CHECK: [0xff,0x16,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f32_f16 v5, 0x3456
+// CHECK: [0xff,0x16,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_rpi_i32_f32 v5, v1
+// CHECK: [0x01,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v255, v1
+// CHECK: [0x01,0x19,0xfe,0x7f]
+
+v_cvt_rpi_i32_f32 v5, v255
+// CHECK: [0xff,0x19,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s1
+// CHECK: [0x01,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, s101
+// CHECK: [0x65,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, ttmp15
+// CHECK: [0x7b,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, m0
+// CHECK: [0x7c,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0
+// CHECK: [0x80,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, -1
+// CHECK: [0xc1,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x18,0x0a,0x7e]
+
+v_cvt_rpi_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x18,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_rpi_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x18,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_flr_i32_f32 v5, v1
+// CHECK: [0x01,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v255, v1
+// CHECK: [0x01,0x1b,0xfe,0x7f]
+
+v_cvt_flr_i32_f32 v5, v255
+// CHECK: [0xff,0x1b,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s1
+// CHECK: [0x01,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, s101
+// CHECK: [0x65,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, ttmp15
+// CHECK: [0x7b,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, m0
+// CHECK: [0x7c,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0
+// CHECK: [0x80,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, -1
+// CHECK: [0xc1,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x1a,0x0a,0x7e]
+
+v_cvt_flr_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x1a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_flr_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x1a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_off_f32_i4 v5, v1
+// CHECK: [0x01,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v255, v1
+// CHECK: [0x01,0x1d,0xfe,0x7f]
+
+v_cvt_off_f32_i4 v5, v255
+// CHECK: [0xff,0x1d,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s1
+// CHECK: [0x01,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, s101
+// CHECK: [0x65,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, flat_scratch_lo
+// CHECK: [0x66,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, flat_scratch_hi
+// CHECK: [0x67,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_lo
+// CHECK: [0x6a,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, vcc_hi
+// CHECK: [0x6b,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, ttmp15
+// CHECK: [0x7b,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, m0
+// CHECK: [0x7c,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_lo
+// CHECK: [0x7e,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, exec_hi
+// CHECK: [0x7f,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0
+// CHECK: [0x80,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, -1
+// CHECK: [0xc1,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0.5
+// CHECK: [0xf0,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, -4.0
+// CHECK: [0xf7,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_vccz
+// CHECK: [0xfb,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_execz
+// CHECK: [0xfc,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_scc
+// CHECK: [0xfd,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, src_lds_direct
+// CHECK: [0xfe,0x1c,0x0a,0x7e]
+
+v_cvt_off_f32_i4 v5, 0x4f
+// CHECK: [0xff,0x1c,0x0a,0x7e,0x4f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4 v5, 0x41
+// CHECK: [0xff,0x1c,0x0a,0x7e,0x41,0x00,0x00,0x00]
+
+v_cvt_f32_f64 v5, v[1:2]
+// CHECK: [0x01,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v255, v[1:2]
+// CHECK: [0x01,0x1f,0xfe,0x7f]
+
+v_cvt_f32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x1f,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[2:3]
+// CHECK: [0x02,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[4:5]
+// CHECK: [0x04,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, s[100:101]
+// CHECK: [0x64,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, flat_scratch
+// CHECK: [0x66,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, vcc
+// CHECK: [0x6a,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, ttmp[14:15]
+// CHECK: [0x7a,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, exec
+// CHECK: [0x7e,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0
+// CHECK: [0x80,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, -1
+// CHECK: [0xc1,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0.5
+// CHECK: [0xf0,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, -4.0
+// CHECK: [0xf7,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_vccz
+// CHECK: [0xfb,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_execz
+// CHECK: [0xfc,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, src_scc
+// CHECK: [0xfd,0x1e,0x0a,0x7e]
+
+v_cvt_f32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x1e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x1e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_f32 v[5:6], v1
+// CHECK: [0x01,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[254:255], v1
+// CHECK: [0x01,0x21,0xfc,0x7f]
+
+v_cvt_f64_f32 v[5:6], v255
+// CHECK: [0xff,0x21,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s1
+// CHECK: [0x01,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], s101
+// CHECK: [0x65,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], flat_scratch_lo
+// CHECK: [0x66,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], flat_scratch_hi
+// CHECK: [0x67,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_lo
+// CHECK: [0x6a,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], vcc_hi
+// CHECK: [0x6b,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], ttmp15
+// CHECK: [0x7b,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], m0
+// CHECK: [0x7c,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_lo
+// CHECK: [0x7e,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], exec_hi
+// CHECK: [0x7f,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0
+// CHECK: [0x80,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], -1
+// CHECK: [0xc1,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0.5
+// CHECK: [0xf0,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], -4.0
+// CHECK: [0xf7,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_vccz
+// CHECK: [0xfb,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_execz
+// CHECK: [0xfc,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_scc
+// CHECK: [0xfd,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], src_lds_direct
+// CHECK: [0xfe,0x20,0x0a,0x7e]
+
+v_cvt_f64_f32 v[5:6], 0xaf123456
+// CHECK: [0xff,0x20,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_f32 v[5:6], 0x3f717273
+// CHECK: [0xff,0x20,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte0 v5, v1
+// CHECK: [0x01,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v255, v1
+// CHECK: [0x01,0x23,0xfe,0x7f]
+
+v_cvt_f32_ubyte0 v5, v255
+// CHECK: [0xff,0x23,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s1
+// CHECK: [0x01,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, s101
+// CHECK: [0x65,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, flat_scratch_lo
+// CHECK: [0x66,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, flat_scratch_hi
+// CHECK: [0x67,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_lo
+// CHECK: [0x6a,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, vcc_hi
+// CHECK: [0x6b,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, ttmp15
+// CHECK: [0x7b,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, m0
+// CHECK: [0x7c,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_lo
+// CHECK: [0x7e,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, exec_hi
+// CHECK: [0x7f,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0
+// CHECK: [0x80,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, -1
+// CHECK: [0xc1,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0.5
+// CHECK: [0xf0,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, -4.0
+// CHECK: [0xf7,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_vccz
+// CHECK: [0xfb,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_execz
+// CHECK: [0xfc,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_scc
+// CHECK: [0xfd,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, src_lds_direct
+// CHECK: [0xfe,0x22,0x0a,0x7e]
+
+v_cvt_f32_ubyte0 v5, 0xaf123456
+// CHECK: [0xff,0x22,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte0 v5, 0x3f717273
+// CHECK: [0xff,0x22,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte1 v5, v1
+// CHECK: [0x01,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v255, v1
+// CHECK: [0x01,0x25,0xfe,0x7f]
+
+v_cvt_f32_ubyte1 v5, v255
+// CHECK: [0xff,0x25,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s1
+// CHECK: [0x01,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, s101
+// CHECK: [0x65,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, flat_scratch_lo
+// CHECK: [0x66,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, flat_scratch_hi
+// CHECK: [0x67,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_lo
+// CHECK: [0x6a,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, vcc_hi
+// CHECK: [0x6b,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, ttmp15
+// CHECK: [0x7b,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, m0
+// CHECK: [0x7c,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_lo
+// CHECK: [0x7e,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, exec_hi
+// CHECK: [0x7f,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0
+// CHECK: [0x80,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, -1
+// CHECK: [0xc1,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0.5
+// CHECK: [0xf0,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, -4.0
+// CHECK: [0xf7,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_vccz
+// CHECK: [0xfb,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_execz
+// CHECK: [0xfc,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_scc
+// CHECK: [0xfd,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, src_lds_direct
+// CHECK: [0xfe,0x24,0x0a,0x7e]
+
+v_cvt_f32_ubyte1 v5, 0xaf123456
+// CHECK: [0xff,0x24,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte1 v5, 0x3f717273
+// CHECK: [0xff,0x24,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte2 v5, v1
+// CHECK: [0x01,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v255, v1
+// CHECK: [0x01,0x27,0xfe,0x7f]
+
+v_cvt_f32_ubyte2 v5, v255
+// CHECK: [0xff,0x27,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s1
+// CHECK: [0x01,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, s101
+// CHECK: [0x65,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, flat_scratch_lo
+// CHECK: [0x66,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, flat_scratch_hi
+// CHECK: [0x67,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_lo
+// CHECK: [0x6a,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, vcc_hi
+// CHECK: [0x6b,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, ttmp15
+// CHECK: [0x7b,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, m0
+// CHECK: [0x7c,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_lo
+// CHECK: [0x7e,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, exec_hi
+// CHECK: [0x7f,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0
+// CHECK: [0x80,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, -1
+// CHECK: [0xc1,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0.5
+// CHECK: [0xf0,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, -4.0
+// CHECK: [0xf7,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_vccz
+// CHECK: [0xfb,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_execz
+// CHECK: [0xfc,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_scc
+// CHECK: [0xfd,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, src_lds_direct
+// CHECK: [0xfe,0x26,0x0a,0x7e]
+
+v_cvt_f32_ubyte2 v5, 0xaf123456
+// CHECK: [0xff,0x26,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte2 v5, 0x3f717273
+// CHECK: [0xff,0x26,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f32_ubyte3 v5, v1
+// CHECK: [0x01,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v255, v1
+// CHECK: [0x01,0x29,0xfe,0x7f]
+
+v_cvt_f32_ubyte3 v5, v255
+// CHECK: [0xff,0x29,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s1
+// CHECK: [0x01,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, s101
+// CHECK: [0x65,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, flat_scratch_lo
+// CHECK: [0x66,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, flat_scratch_hi
+// CHECK: [0x67,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_lo
+// CHECK: [0x6a,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, vcc_hi
+// CHECK: [0x6b,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, ttmp15
+// CHECK: [0x7b,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, m0
+// CHECK: [0x7c,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_lo
+// CHECK: [0x7e,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, exec_hi
+// CHECK: [0x7f,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0
+// CHECK: [0x80,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, -1
+// CHECK: [0xc1,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0.5
+// CHECK: [0xf0,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, -4.0
+// CHECK: [0xf7,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_vccz
+// CHECK: [0xfb,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_execz
+// CHECK: [0xfc,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_scc
+// CHECK: [0xfd,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, src_lds_direct
+// CHECK: [0xfe,0x28,0x0a,0x7e]
+
+v_cvt_f32_ubyte3 v5, 0xaf123456
+// CHECK: [0xff,0x28,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f32_ubyte3 v5, 0x3f717273
+// CHECK: [0xff,0x28,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_u32_f64 v5, v[1:2]
+// CHECK: [0x01,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v255, v[1:2]
+// CHECK: [0x01,0x2b,0xfe,0x7f]
+
+v_cvt_u32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x2b,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[2:3]
+// CHECK: [0x02,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[4:5]
+// CHECK: [0x04,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, s[100:101]
+// CHECK: [0x64,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, flat_scratch
+// CHECK: [0x66,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, vcc
+// CHECK: [0x6a,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, ttmp[14:15]
+// CHECK: [0x7a,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, exec
+// CHECK: [0x7e,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0
+// CHECK: [0x80,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, -1
+// CHECK: [0xc1,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0.5
+// CHECK: [0xf0,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, -4.0
+// CHECK: [0xf7,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_vccz
+// CHECK: [0xfb,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_execz
+// CHECK: [0xfc,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, src_scc
+// CHECK: [0xfd,0x2a,0x0a,0x7e]
+
+v_cvt_u32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x2a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_u32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x2a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f64_u32 v[5:6], v1
+// CHECK: [0x01,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[254:255], v1
+// CHECK: [0x01,0x2d,0xfc,0x7f]
+
+v_cvt_f64_u32 v[5:6], v255
+// CHECK: [0xff,0x2d,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s1
+// CHECK: [0x01,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], s101
+// CHECK: [0x65,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], flat_scratch_lo
+// CHECK: [0x66,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], flat_scratch_hi
+// CHECK: [0x67,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_lo
+// CHECK: [0x6a,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], vcc_hi
+// CHECK: [0x6b,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], ttmp15
+// CHECK: [0x7b,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], m0
+// CHECK: [0x7c,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_lo
+// CHECK: [0x7e,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], exec_hi
+// CHECK: [0x7f,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0
+// CHECK: [0x80,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], -1
+// CHECK: [0xc1,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0.5
+// CHECK: [0xf0,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], -4.0
+// CHECK: [0xf7,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_vccz
+// CHECK: [0xfb,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_execz
+// CHECK: [0xfc,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_scc
+// CHECK: [0xfd,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], src_lds_direct
+// CHECK: [0xfe,0x2c,0x0a,0x7e]
+
+v_cvt_f64_u32 v[5:6], 0xaf123456
+// CHECK: [0xff,0x2c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cvt_f64_u32 v[5:6], 0x3f717273
+// CHECK: [0xff,0x2c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_trunc_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x2f,0xfc,0x7f]
+
+v_trunc_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x2f,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], vcc
+// CHECK: [0x6a,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], ttmp[14:15]
+// CHECK: [0x7a,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], exec
+// CHECK: [0x7e,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0
+// CHECK: [0x80,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], -1
+// CHECK: [0xc1,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x2e,0x0a,0x7e]
+
+v_trunc_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x2e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_trunc_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x2e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ceil_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x31,0xfc,0x7f]
+
+v_ceil_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x31,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], vcc
+// CHECK: [0x6a,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], ttmp[14:15]
+// CHECK: [0x7a,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], exec
+// CHECK: [0x7e,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0
+// CHECK: [0x80,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], -1
+// CHECK: [0xc1,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x30,0x0a,0x7e]
+
+v_ceil_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x30,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ceil_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x30,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rndne_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x33,0xfc,0x7f]
+
+v_rndne_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x33,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], vcc
+// CHECK: [0x6a,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], ttmp[14:15]
+// CHECK: [0x7a,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], exec
+// CHECK: [0x7e,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0
+// CHECK: [0x80,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], -1
+// CHECK: [0xc1,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x32,0x0a,0x7e]
+
+v_rndne_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x32,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rndne_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x32,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_floor_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x35,0x0a,0x7e]
+
+v_floor_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x35,0xfc,0x7f]
+
+v_floor_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x35,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], vcc
+// CHECK: [0x6a,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], ttmp[14:15]
+// CHECK: [0x7a,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], exec
+// CHECK: [0x7e,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0
+// CHECK: [0x80,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], -1
+// CHECK: [0xc1,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x34,0x0a,0x7e]
+
+v_floor_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x34,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_floor_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x34,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_fract_f32 v5, v1
+// CHECK: [0x01,0x37,0x0a,0x7e]
+
+v_fract_f32 v255, v1
+// CHECK: [0x01,0x37,0xfe,0x7f]
+
+v_fract_f32 v5, v255
+// CHECK: [0xff,0x37,0x0a,0x7e]
+
+v_fract_f32 v5, s1
+// CHECK: [0x01,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, s101
+// CHECK: [0x65,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_lo
+// CHECK: [0x6a,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, vcc_hi
+// CHECK: [0x6b,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, ttmp15
+// CHECK: [0x7b,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, m0
+// CHECK: [0x7c,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, exec_lo
+// CHECK: [0x7e,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, exec_hi
+// CHECK: [0x7f,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, 0
+// CHECK: [0x80,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, -1
+// CHECK: [0xc1,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, 0.5
+// CHECK: [0xf0,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, -4.0
+// CHECK: [0xf7,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, src_vccz
+// CHECK: [0xfb,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, src_execz
+// CHECK: [0xfc,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, src_scc
+// CHECK: [0xfd,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x36,0x0a,0x7e]
+
+v_fract_f32 v5, 0xaf123456
+// CHECK: [0xff,0x36,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_fract_f32 v5, 0x3f717273
+// CHECK: [0xff,0x36,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_trunc_f32 v5, v1
+// CHECK: [0x01,0x39,0x0a,0x7e]
+
+v_trunc_f32 v255, v1
+// CHECK: [0x01,0x39,0xfe,0x7f]
+
+v_trunc_f32 v5, v255
+// CHECK: [0xff,0x39,0x0a,0x7e]
+
+v_trunc_f32 v5, s1
+// CHECK: [0x01,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, s101
+// CHECK: [0x65,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_lo
+// CHECK: [0x6a,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, vcc_hi
+// CHECK: [0x6b,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, ttmp15
+// CHECK: [0x7b,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, m0
+// CHECK: [0x7c,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_lo
+// CHECK: [0x7e,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, exec_hi
+// CHECK: [0x7f,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, 0
+// CHECK: [0x80,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, -1
+// CHECK: [0xc1,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, 0.5
+// CHECK: [0xf0,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, -4.0
+// CHECK: [0xf7,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, src_vccz
+// CHECK: [0xfb,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, src_execz
+// CHECK: [0xfc,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, src_scc
+// CHECK: [0xfd,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x38,0x0a,0x7e]
+
+v_trunc_f32 v5, 0xaf123456
+// CHECK: [0xff,0x38,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_trunc_f32 v5, 0x3f717273
+// CHECK: [0xff,0x38,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ceil_f32 v5, v1
+// CHECK: [0x01,0x3b,0x0a,0x7e]
+
+v_ceil_f32 v255, v1
+// CHECK: [0x01,0x3b,0xfe,0x7f]
+
+v_ceil_f32 v5, v255
+// CHECK: [0xff,0x3b,0x0a,0x7e]
+
+v_ceil_f32 v5, s1
+// CHECK: [0x01,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, s101
+// CHECK: [0x65,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_lo
+// CHECK: [0x6a,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, vcc_hi
+// CHECK: [0x6b,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, ttmp15
+// CHECK: [0x7b,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, m0
+// CHECK: [0x7c,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_lo
+// CHECK: [0x7e,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, exec_hi
+// CHECK: [0x7f,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, 0
+// CHECK: [0x80,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, -1
+// CHECK: [0xc1,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, 0.5
+// CHECK: [0xf0,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, -4.0
+// CHECK: [0xf7,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, src_vccz
+// CHECK: [0xfb,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, src_execz
+// CHECK: [0xfc,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, src_scc
+// CHECK: [0xfd,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x3a,0x0a,0x7e]
+
+v_ceil_f32 v5, 0xaf123456
+// CHECK: [0xff,0x3a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ceil_f32 v5, 0x3f717273
+// CHECK: [0xff,0x3a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rndne_f32 v5, v1
+// CHECK: [0x01,0x3d,0x0a,0x7e]
+
+v_rndne_f32 v255, v1
+// CHECK: [0x01,0x3d,0xfe,0x7f]
+
+v_rndne_f32 v5, v255
+// CHECK: [0xff,0x3d,0x0a,0x7e]
+
+v_rndne_f32 v5, s1
+// CHECK: [0x01,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, s101
+// CHECK: [0x65,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_lo
+// CHECK: [0x6a,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, vcc_hi
+// CHECK: [0x6b,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, ttmp15
+// CHECK: [0x7b,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, m0
+// CHECK: [0x7c,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_lo
+// CHECK: [0x7e,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, exec_hi
+// CHECK: [0x7f,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, 0
+// CHECK: [0x80,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, -1
+// CHECK: [0xc1,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, 0.5
+// CHECK: [0xf0,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, -4.0
+// CHECK: [0xf7,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, src_vccz
+// CHECK: [0xfb,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, src_execz
+// CHECK: [0xfc,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, src_scc
+// CHECK: [0xfd,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x3c,0x0a,0x7e]
+
+v_rndne_f32 v5, 0xaf123456
+// CHECK: [0xff,0x3c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rndne_f32 v5, 0x3f717273
+// CHECK: [0xff,0x3c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_floor_f32 v5, v1
+// CHECK: [0x01,0x3f,0x0a,0x7e]
+
+v_floor_f32 v255, v1
+// CHECK: [0x01,0x3f,0xfe,0x7f]
+
+v_floor_f32 v5, v255
+// CHECK: [0xff,0x3f,0x0a,0x7e]
+
+v_floor_f32 v5, s1
+// CHECK: [0x01,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, s101
+// CHECK: [0x65,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_lo
+// CHECK: [0x6a,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, vcc_hi
+// CHECK: [0x6b,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, ttmp15
+// CHECK: [0x7b,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, m0
+// CHECK: [0x7c,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, exec_lo
+// CHECK: [0x7e,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, exec_hi
+// CHECK: [0x7f,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, 0
+// CHECK: [0x80,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, -1
+// CHECK: [0xc1,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, 0.5
+// CHECK: [0xf0,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, -4.0
+// CHECK: [0xf7,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, src_vccz
+// CHECK: [0xfb,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, src_execz
+// CHECK: [0xfc,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, src_scc
+// CHECK: [0xfd,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x3e,0x0a,0x7e]
+
+v_floor_f32 v5, 0xaf123456
+// CHECK: [0xff,0x3e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_floor_f32 v5, 0x3f717273
+// CHECK: [0xff,0x3e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_exp_f32 v5, v1
+// CHECK: [0x01,0x41,0x0a,0x7e]
+
+v_exp_f32 v255, v1
+// CHECK: [0x01,0x41,0xfe,0x7f]
+
+v_exp_f32 v5, v255
+// CHECK: [0xff,0x41,0x0a,0x7e]
+
+v_exp_f32 v5, s1
+// CHECK: [0x01,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, s101
+// CHECK: [0x65,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_lo
+// CHECK: [0x6a,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, vcc_hi
+// CHECK: [0x6b,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, ttmp15
+// CHECK: [0x7b,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, m0
+// CHECK: [0x7c,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, exec_lo
+// CHECK: [0x7e,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, exec_hi
+// CHECK: [0x7f,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, 0
+// CHECK: [0x80,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, -1
+// CHECK: [0xc1,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, 0.5
+// CHECK: [0xf0,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, -4.0
+// CHECK: [0xf7,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, src_vccz
+// CHECK: [0xfb,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, src_execz
+// CHECK: [0xfc,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, src_scc
+// CHECK: [0xfd,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x40,0x0a,0x7e]
+
+v_exp_f32 v5, 0xaf123456
+// CHECK: [0xff,0x40,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_exp_f32 v5, 0x3f717273
+// CHECK: [0xff,0x40,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_log_f32 v5, v1
+// CHECK: [0x01,0x43,0x0a,0x7e]
+
+v_log_f32 v255, v1
+// CHECK: [0x01,0x43,0xfe,0x7f]
+
+v_log_f32 v5, v255
+// CHECK: [0xff,0x43,0x0a,0x7e]
+
+v_log_f32 v5, s1
+// CHECK: [0x01,0x42,0x0a,0x7e]
+
+v_log_f32 v5, s101
+// CHECK: [0x65,0x42,0x0a,0x7e]
+
+v_log_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x42,0x0a,0x7e]
+
+v_log_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x42,0x0a,0x7e]
+
+v_log_f32 v5, vcc_lo
+// CHECK: [0x6a,0x42,0x0a,0x7e]
+
+v_log_f32 v5, vcc_hi
+// CHECK: [0x6b,0x42,0x0a,0x7e]
+
+v_log_f32 v5, ttmp15
+// CHECK: [0x7b,0x42,0x0a,0x7e]
+
+v_log_f32 v5, m0
+// CHECK: [0x7c,0x42,0x0a,0x7e]
+
+v_log_f32 v5, exec_lo
+// CHECK: [0x7e,0x42,0x0a,0x7e]
+
+v_log_f32 v5, exec_hi
+// CHECK: [0x7f,0x42,0x0a,0x7e]
+
+v_log_f32 v5, 0
+// CHECK: [0x80,0x42,0x0a,0x7e]
+
+v_log_f32 v5, -1
+// CHECK: [0xc1,0x42,0x0a,0x7e]
+
+v_log_f32 v5, 0.5
+// CHECK: [0xf0,0x42,0x0a,0x7e]
+
+v_log_f32 v5, -4.0
+// CHECK: [0xf7,0x42,0x0a,0x7e]
+
+v_log_f32 v5, src_vccz
+// CHECK: [0xfb,0x42,0x0a,0x7e]
+
+v_log_f32 v5, src_execz
+// CHECK: [0xfc,0x42,0x0a,0x7e]
+
+v_log_f32 v5, src_scc
+// CHECK: [0xfd,0x42,0x0a,0x7e]
+
+v_log_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x42,0x0a,0x7e]
+
+v_log_f32 v5, 0xaf123456
+// CHECK: [0xff,0x42,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_log_f32 v5, 0x3f717273
+// CHECK: [0xff,0x42,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_f32 v5, v1
+// CHECK: [0x01,0x45,0x0a,0x7e]
+
+v_rcp_f32 v255, v1
+// CHECK: [0x01,0x45,0xfe,0x7f]
+
+v_rcp_f32 v5, v255
+// CHECK: [0xff,0x45,0x0a,0x7e]
+
+v_rcp_f32 v5, s1
+// CHECK: [0x01,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, s101
+// CHECK: [0x65,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_lo
+// CHECK: [0x6a,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, vcc_hi
+// CHECK: [0x6b,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, ttmp15
+// CHECK: [0x7b,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, m0
+// CHECK: [0x7c,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_lo
+// CHECK: [0x7e,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, exec_hi
+// CHECK: [0x7f,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, 0
+// CHECK: [0x80,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, -1
+// CHECK: [0xc1,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, 0.5
+// CHECK: [0xf0,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, -4.0
+// CHECK: [0xf7,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, src_vccz
+// CHECK: [0xfb,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, src_execz
+// CHECK: [0xfc,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, src_scc
+// CHECK: [0xfd,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x44,0x0a,0x7e]
+
+v_rcp_f32 v5, 0xaf123456
+// CHECK: [0xff,0x44,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_f32 v5, 0x3f717273
+// CHECK: [0xff,0x44,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_iflag_f32 v5, v1
+// CHECK: [0x01,0x47,0x0a,0x7e]
+
+v_rcp_iflag_f32 v255, v1
+// CHECK: [0x01,0x47,0xfe,0x7f]
+
+v_rcp_iflag_f32 v5, v255
+// CHECK: [0xff,0x47,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s1
+// CHECK: [0x01,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, s101
+// CHECK: [0x65,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_lo
+// CHECK: [0x6a,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, vcc_hi
+// CHECK: [0x6b,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, ttmp15
+// CHECK: [0x7b,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, m0
+// CHECK: [0x7c,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_lo
+// CHECK: [0x7e,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, exec_hi
+// CHECK: [0x7f,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0
+// CHECK: [0x80,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, -1
+// CHECK: [0xc1,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0.5
+// CHECK: [0xf0,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, -4.0
+// CHECK: [0xf7,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_vccz
+// CHECK: [0xfb,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_execz
+// CHECK: [0xfc,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_scc
+// CHECK: [0xfd,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x46,0x0a,0x7e]
+
+v_rcp_iflag_f32 v5, 0xaf123456
+// CHECK: [0xff,0x46,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_iflag_f32 v5, 0x3f717273
+// CHECK: [0xff,0x46,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_f32 v5, v1
+// CHECK: [0x01,0x49,0x0a,0x7e]
+
+v_rsq_f32 v255, v1
+// CHECK: [0x01,0x49,0xfe,0x7f]
+
+v_rsq_f32 v5, v255
+// CHECK: [0xff,0x49,0x0a,0x7e]
+
+v_rsq_f32 v5, s1
+// CHECK: [0x01,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, s101
+// CHECK: [0x65,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_lo
+// CHECK: [0x6a,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, vcc_hi
+// CHECK: [0x6b,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, ttmp15
+// CHECK: [0x7b,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, m0
+// CHECK: [0x7c,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_lo
+// CHECK: [0x7e,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, exec_hi
+// CHECK: [0x7f,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, 0
+// CHECK: [0x80,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, -1
+// CHECK: [0xc1,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, 0.5
+// CHECK: [0xf0,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, -4.0
+// CHECK: [0xf7,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, src_vccz
+// CHECK: [0xfb,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, src_execz
+// CHECK: [0xfc,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, src_scc
+// CHECK: [0xfd,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x48,0x0a,0x7e]
+
+v_rsq_f32 v5, 0xaf123456
+// CHECK: [0xff,0x48,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_f32 v5, 0x3f717273
+// CHECK: [0xff,0x48,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rcp_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x4b,0x0a,0x7e]
+
+v_rcp_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x4b,0xfc,0x7f]
+
+v_rcp_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x4b,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], vcc
+// CHECK: [0x6a,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], ttmp[14:15]
+// CHECK: [0x7a,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], exec
+// CHECK: [0x7e,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0
+// CHECK: [0x80,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], -1
+// CHECK: [0xc1,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x4a,0x0a,0x7e]
+
+v_rcp_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x4a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rcp_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x4a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_rsq_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x4d,0x0a,0x7e]
+
+v_rsq_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x4d,0xfc,0x7f]
+
+v_rsq_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x4d,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], vcc
+// CHECK: [0x6a,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], ttmp[14:15]
+// CHECK: [0x7a,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], exec
+// CHECK: [0x7e,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0
+// CHECK: [0x80,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], -1
+// CHECK: [0xc1,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x4c,0x0a,0x7e]
+
+v_rsq_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x4c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_rsq_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x4c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sqrt_f32 v5, v1
+// CHECK: [0x01,0x4f,0x0a,0x7e]
+
+v_sqrt_f32 v255, v1
+// CHECK: [0x01,0x4f,0xfe,0x7f]
+
+v_sqrt_f32 v5, v255
+// CHECK: [0xff,0x4f,0x0a,0x7e]
+
+v_sqrt_f32 v5, s1
+// CHECK: [0x01,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, s101
+// CHECK: [0x65,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_lo
+// CHECK: [0x6a,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, vcc_hi
+// CHECK: [0x6b,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, ttmp15
+// CHECK: [0x7b,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, m0
+// CHECK: [0x7c,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_lo
+// CHECK: [0x7e,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, exec_hi
+// CHECK: [0x7f,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0
+// CHECK: [0x80,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, -1
+// CHECK: [0xc1,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0.5
+// CHECK: [0xf0,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, -4.0
+// CHECK: [0xf7,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_vccz
+// CHECK: [0xfb,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_execz
+// CHECK: [0xfc,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_scc
+// CHECK: [0xfd,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x4e,0x0a,0x7e]
+
+v_sqrt_f32 v5, 0xaf123456
+// CHECK: [0xff,0x4e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f32 v5, 0x3f717273
+// CHECK: [0xff,0x4e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sqrt_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x51,0x0a,0x7e]
+
+v_sqrt_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x51,0xfc,0x7f]
+
+v_sqrt_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x51,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], vcc
+// CHECK: [0x6a,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], ttmp[14:15]
+// CHECK: [0x7a,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], exec
+// CHECK: [0x7e,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0
+// CHECK: [0x80,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], -1
+// CHECK: [0xc1,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x50,0x0a,0x7e]
+
+v_sqrt_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x50,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sqrt_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x50,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_sin_f32 v5, v1
+// CHECK: [0x01,0x53,0x0a,0x7e]
+
+v_sin_f32 v255, v1
+// CHECK: [0x01,0x53,0xfe,0x7f]
+
+v_sin_f32 v5, v255
+// CHECK: [0xff,0x53,0x0a,0x7e]
+
+v_sin_f32 v5, s1
+// CHECK: [0x01,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, s101
+// CHECK: [0x65,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_lo
+// CHECK: [0x6a,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, vcc_hi
+// CHECK: [0x6b,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, ttmp15
+// CHECK: [0x7b,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, m0
+// CHECK: [0x7c,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, exec_lo
+// CHECK: [0x7e,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, exec_hi
+// CHECK: [0x7f,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, 0
+// CHECK: [0x80,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, -1
+// CHECK: [0xc1,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, 0.5
+// CHECK: [0xf0,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, -4.0
+// CHECK: [0xf7,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, src_vccz
+// CHECK: [0xfb,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, src_execz
+// CHECK: [0xfc,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, src_scc
+// CHECK: [0xfd,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x52,0x0a,0x7e]
+
+v_sin_f32 v5, 0xaf123456
+// CHECK: [0xff,0x52,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_sin_f32 v5, 0x3f717273
+// CHECK: [0xff,0x52,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cos_f32 v5, v1
+// CHECK: [0x01,0x55,0x0a,0x7e]
+
+v_cos_f32 v255, v1
+// CHECK: [0x01,0x55,0xfe,0x7f]
+
+v_cos_f32 v5, v255
+// CHECK: [0xff,0x55,0x0a,0x7e]
+
+v_cos_f32 v5, s1
+// CHECK: [0x01,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, s101
+// CHECK: [0x65,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_lo
+// CHECK: [0x6a,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, vcc_hi
+// CHECK: [0x6b,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, ttmp15
+// CHECK: [0x7b,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, m0
+// CHECK: [0x7c,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, exec_lo
+// CHECK: [0x7e,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, exec_hi
+// CHECK: [0x7f,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, 0
+// CHECK: [0x80,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, -1
+// CHECK: [0xc1,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, 0.5
+// CHECK: [0xf0,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, -4.0
+// CHECK: [0xf7,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, src_vccz
+// CHECK: [0xfb,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, src_execz
+// CHECK: [0xfc,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, src_scc
+// CHECK: [0xfd,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x54,0x0a,0x7e]
+
+v_cos_f32 v5, 0xaf123456
+// CHECK: [0xff,0x54,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_cos_f32 v5, 0x3f717273
+// CHECK: [0xff,0x54,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_not_b32 v5, v1
+// CHECK: [0x01,0x57,0x0a,0x7e]
+
+v_not_b32 v255, v1
+// CHECK: [0x01,0x57,0xfe,0x7f]
+
+v_not_b32 v5, v255
+// CHECK: [0xff,0x57,0x0a,0x7e]
+
+v_not_b32 v5, s1
+// CHECK: [0x01,0x56,0x0a,0x7e]
+
+v_not_b32 v5, s101
+// CHECK: [0x65,0x56,0x0a,0x7e]
+
+v_not_b32 v5, flat_scratch_lo
+// CHECK: [0x66,0x56,0x0a,0x7e]
+
+v_not_b32 v5, flat_scratch_hi
+// CHECK: [0x67,0x56,0x0a,0x7e]
+
+v_not_b32 v5, vcc_lo
+// CHECK: [0x6a,0x56,0x0a,0x7e]
+
+v_not_b32 v5, vcc_hi
+// CHECK: [0x6b,0x56,0x0a,0x7e]
+
+v_not_b32 v5, ttmp15
+// CHECK: [0x7b,0x56,0x0a,0x7e]
+
+v_not_b32 v5, m0
+// CHECK: [0x7c,0x56,0x0a,0x7e]
+
+v_not_b32 v5, exec_lo
+// CHECK: [0x7e,0x56,0x0a,0x7e]
+
+v_not_b32 v5, exec_hi
+// CHECK: [0x7f,0x56,0x0a,0x7e]
+
+v_not_b32 v5, 0
+// CHECK: [0x80,0x56,0x0a,0x7e]
+
+v_not_b32 v5, -1
+// CHECK: [0xc1,0x56,0x0a,0x7e]
+
+v_not_b32 v5, 0.5
+// CHECK: [0xf0,0x56,0x0a,0x7e]
+
+v_not_b32 v5, -4.0
+// CHECK: [0xf7,0x56,0x0a,0x7e]
+
+v_not_b32 v5, src_vccz
+// CHECK: [0xfb,0x56,0x0a,0x7e]
+
+v_not_b32 v5, src_execz
+// CHECK: [0xfc,0x56,0x0a,0x7e]
+
+v_not_b32 v5, src_scc
+// CHECK: [0xfd,0x56,0x0a,0x7e]
+
+v_not_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x56,0x0a,0x7e]
+
+v_not_b32 v5, 0xaf123456
+// CHECK: [0xff,0x56,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_not_b32 v5, 0x3f717273
+// CHECK: [0xff,0x56,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_bfrev_b32 v5, v1
+// CHECK: [0x01,0x59,0x0a,0x7e]
+
+v_bfrev_b32 v255, v1
+// CHECK: [0x01,0x59,0xfe,0x7f]
+
+v_bfrev_b32 v5, v255
+// CHECK: [0xff,0x59,0x0a,0x7e]
+
+v_bfrev_b32 v5, s1
+// CHECK: [0x01,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, s101
+// CHECK: [0x65,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, flat_scratch_lo
+// CHECK: [0x66,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, flat_scratch_hi
+// CHECK: [0x67,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_lo
+// CHECK: [0x6a,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, vcc_hi
+// CHECK: [0x6b,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, ttmp15
+// CHECK: [0x7b,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, m0
+// CHECK: [0x7c,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_lo
+// CHECK: [0x7e,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, exec_hi
+// CHECK: [0x7f,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0
+// CHECK: [0x80,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, -1
+// CHECK: [0xc1,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0.5
+// CHECK: [0xf0,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, -4.0
+// CHECK: [0xf7,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_vccz
+// CHECK: [0xfb,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_execz
+// CHECK: [0xfc,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_scc
+// CHECK: [0xfd,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x58,0x0a,0x7e]
+
+v_bfrev_b32 v5, 0xaf123456
+// CHECK: [0xff,0x58,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_bfrev_b32 v5, 0x3f717273
+// CHECK: [0xff,0x58,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbh_u32 v5, v1
+// CHECK: [0x01,0x5b,0x0a,0x7e]
+
+v_ffbh_u32 v255, v1
+// CHECK: [0x01,0x5b,0xfe,0x7f]
+
+v_ffbh_u32 v5, v255
+// CHECK: [0xff,0x5b,0x0a,0x7e]
+
+v_ffbh_u32 v5, s1
+// CHECK: [0x01,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, s101
+// CHECK: [0x65,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, flat_scratch_lo
+// CHECK: [0x66,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, flat_scratch_hi
+// CHECK: [0x67,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_lo
+// CHECK: [0x6a,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, vcc_hi
+// CHECK: [0x6b,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, ttmp15
+// CHECK: [0x7b,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, m0
+// CHECK: [0x7c,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_lo
+// CHECK: [0x7e,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, exec_hi
+// CHECK: [0x7f,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0
+// CHECK: [0x80,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, -1
+// CHECK: [0xc1,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0.5
+// CHECK: [0xf0,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, -4.0
+// CHECK: [0xf7,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_vccz
+// CHECK: [0xfb,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_execz
+// CHECK: [0xfc,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_scc
+// CHECK: [0xfd,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, src_lds_direct
+// CHECK: [0xfe,0x5a,0x0a,0x7e]
+
+v_ffbh_u32 v5, 0xaf123456
+// CHECK: [0xff,0x5a,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbh_u32 v5, 0x3f717273
+// CHECK: [0xff,0x5a,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbl_b32 v5, v1
+// CHECK: [0x01,0x5d,0x0a,0x7e]
+
+v_ffbl_b32 v255, v1
+// CHECK: [0x01,0x5d,0xfe,0x7f]
+
+v_ffbl_b32 v5, v255
+// CHECK: [0xff,0x5d,0x0a,0x7e]
+
+v_ffbl_b32 v5, s1
+// CHECK: [0x01,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, s101
+// CHECK: [0x65,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, flat_scratch_lo
+// CHECK: [0x66,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, flat_scratch_hi
+// CHECK: [0x67,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_lo
+// CHECK: [0x6a,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, vcc_hi
+// CHECK: [0x6b,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, ttmp15
+// CHECK: [0x7b,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, m0
+// CHECK: [0x7c,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_lo
+// CHECK: [0x7e,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, exec_hi
+// CHECK: [0x7f,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0
+// CHECK: [0x80,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, -1
+// CHECK: [0xc1,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0.5
+// CHECK: [0xf0,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, -4.0
+// CHECK: [0xf7,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_vccz
+// CHECK: [0xfb,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_execz
+// CHECK: [0xfc,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_scc
+// CHECK: [0xfd,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x5c,0x0a,0x7e]
+
+v_ffbl_b32 v5, 0xaf123456
+// CHECK: [0xff,0x5c,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbl_b32 v5, 0x3f717273
+// CHECK: [0xff,0x5c,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_ffbh_i32 v5, v1
+// CHECK: [0x01,0x5f,0x0a,0x7e]
+
+v_ffbh_i32 v255, v1
+// CHECK: [0x01,0x5f,0xfe,0x7f]
+
+v_ffbh_i32 v5, v255
+// CHECK: [0xff,0x5f,0x0a,0x7e]
+
+v_ffbh_i32 v5, s1
+// CHECK: [0x01,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, s101
+// CHECK: [0x65,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, flat_scratch_lo
+// CHECK: [0x66,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, flat_scratch_hi
+// CHECK: [0x67,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_lo
+// CHECK: [0x6a,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, vcc_hi
+// CHECK: [0x6b,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, ttmp15
+// CHECK: [0x7b,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, m0
+// CHECK: [0x7c,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_lo
+// CHECK: [0x7e,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, exec_hi
+// CHECK: [0x7f,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0
+// CHECK: [0x80,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, -1
+// CHECK: [0xc1,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0.5
+// CHECK: [0xf0,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, -4.0
+// CHECK: [0xf7,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_vccz
+// CHECK: [0xfb,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_execz
+// CHECK: [0xfc,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_scc
+// CHECK: [0xfd,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, src_lds_direct
+// CHECK: [0xfe,0x5e,0x0a,0x7e]
+
+v_ffbh_i32 v5, 0xaf123456
+// CHECK: [0xff,0x5e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_ffbh_i32 v5, 0x3f717273
+// CHECK: [0xff,0x5e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_exp_i32_f64 v5, v[1:2]
+// CHECK: [0x01,0x61,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v255, v[1:2]
+// CHECK: [0x01,0x61,0xfe,0x7f]
+
+v_frexp_exp_i32_f64 v5, v[254:255]
+// CHECK: [0xfe,0x61,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[2:3]
+// CHECK: [0x02,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[4:5]
+// CHECK: [0x04,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, s[100:101]
+// CHECK: [0x64,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, flat_scratch
+// CHECK: [0x66,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, vcc
+// CHECK: [0x6a,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, ttmp[14:15]
+// CHECK: [0x7a,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, exec
+// CHECK: [0x7e,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0
+// CHECK: [0x80,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, -1
+// CHECK: [0xc1,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0.5
+// CHECK: [0xf0,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, -4.0
+// CHECK: [0xf7,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_vccz
+// CHECK: [0xfb,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_execz
+// CHECK: [0xfc,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, src_scc
+// CHECK: [0xfd,0x60,0x0a,0x7e]
+
+v_frexp_exp_i32_f64 v5, 0xaf123456
+// CHECK: [0xff,0x60,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f64 v5, 0x3f717273
+// CHECK: [0xff,0x60,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_mant_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x63,0x0a,0x7e]
+
+v_frexp_mant_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x63,0xfc,0x7f]
+
+v_frexp_mant_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x63,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], vcc
+// CHECK: [0x6a,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], ttmp[14:15]
+// CHECK: [0x7a,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], exec
+// CHECK: [0x7e,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0
+// CHECK: [0x80,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], -1
+// CHECK: [0xc1,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x62,0x0a,0x7e]
+
+v_frexp_mant_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x62,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x62,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_fract_f64 v[5:6], v[1:2]
+// CHECK: [0x01,0x65,0x0a,0x7e]
+
+v_fract_f64 v[254:255], v[1:2]
+// CHECK: [0x01,0x65,0xfc,0x7f]
+
+v_fract_f64 v[5:6], v[254:255]
+// CHECK: [0xfe,0x65,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[2:3]
+// CHECK: [0x02,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[4:5]
+// CHECK: [0x04,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], s[100:101]
+// CHECK: [0x64,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], flat_scratch
+// CHECK: [0x66,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], vcc
+// CHECK: [0x6a,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], ttmp[14:15]
+// CHECK: [0x7a,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], exec
+// CHECK: [0x7e,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0
+// CHECK: [0x80,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], -1
+// CHECK: [0xc1,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0.5
+// CHECK: [0xf0,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], -4.0
+// CHECK: [0xf7,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_vccz
+// CHECK: [0xfb,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_execz
+// CHECK: [0xfc,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], src_scc
+// CHECK: [0xfd,0x64,0x0a,0x7e]
+
+v_fract_f64 v[5:6], 0xaf123456
+// CHECK: [0xff,0x64,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_fract_f64 v[5:6], 0x3f717273
+// CHECK: [0xff,0x64,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_exp_i32_f32 v5, v1
+// CHECK: [0x01,0x67,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v255, v1
+// CHECK: [0x01,0x67,0xfe,0x7f]
+
+v_frexp_exp_i32_f32 v5, v255
+// CHECK: [0xff,0x67,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s1
+// CHECK: [0x01,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, s101
+// CHECK: [0x65,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_lo
+// CHECK: [0x6a,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, vcc_hi
+// CHECK: [0x6b,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, ttmp15
+// CHECK: [0x7b,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, m0
+// CHECK: [0x7c,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_lo
+// CHECK: [0x7e,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, exec_hi
+// CHECK: [0x7f,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0
+// CHECK: [0x80,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, -1
+// CHECK: [0xc1,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0.5
+// CHECK: [0xf0,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, -4.0
+// CHECK: [0xf7,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_vccz
+// CHECK: [0xfb,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_execz
+// CHECK: [0xfc,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_scc
+// CHECK: [0xfd,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x66,0x0a,0x7e]
+
+v_frexp_exp_i32_f32 v5, 0xaf123456
+// CHECK: [0xff,0x66,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_exp_i32_f32 v5, 0x3f717273
+// CHECK: [0xff,0x66,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_frexp_mant_f32 v5, v1
+// CHECK: [0x01,0x69,0x0a,0x7e]
+
+v_frexp_mant_f32 v255, v1
+// CHECK: [0x01,0x69,0xfe,0x7f]
+
+v_frexp_mant_f32 v5, v255
+// CHECK: [0xff,0x69,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s1
+// CHECK: [0x01,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, s101
+// CHECK: [0x65,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_lo
+// CHECK: [0x6a,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, vcc_hi
+// CHECK: [0x6b,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, ttmp15
+// CHECK: [0x7b,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, m0
+// CHECK: [0x7c,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_lo
+// CHECK: [0x7e,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, exec_hi
+// CHECK: [0x7f,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0
+// CHECK: [0x80,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, -1
+// CHECK: [0xc1,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0.5
+// CHECK: [0xf0,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, -4.0
+// CHECK: [0xf7,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_vccz
+// CHECK: [0xfb,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_execz
+// CHECK: [0xfc,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_scc
+// CHECK: [0xfd,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x68,0x0a,0x7e]
+
+v_frexp_mant_f32 v5, 0xaf123456
+// CHECK: [0xff,0x68,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_frexp_mant_f32 v5, 0x3f717273
+// CHECK: [0xff,0x68,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_clrexcp
+// CHECK: [0x00,0x6a,0x00,0x7e]
+
+v_screen_partition_4se_b32 v5, v1
+// CHECK: [0x01,0x6f,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v255, v1
+// CHECK: [0x01,0x6f,0xfe,0x7f]
+
+v_screen_partition_4se_b32 v5, v255
+// CHECK: [0xff,0x6f,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, s1
+// CHECK: [0x01,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, s101
+// CHECK: [0x65,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, flat_scratch_lo
+// CHECK: [0x66,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, flat_scratch_hi
+// CHECK: [0x67,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, vcc_lo
+// CHECK: [0x6a,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, vcc_hi
+// CHECK: [0x6b,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, ttmp15
+// CHECK: [0x7b,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, m0
+// CHECK: [0x7c,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, exec_lo
+// CHECK: [0x7e,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, exec_hi
+// CHECK: [0x7f,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, 0
+// CHECK: [0x80,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, -1
+// CHECK: [0xc1,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, 0.5
+// CHECK: [0xf0,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, -4.0
+// CHECK: [0xf7,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, src_vccz
+// CHECK: [0xfb,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, src_execz
+// CHECK: [0xfc,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, src_scc
+// CHECK: [0xfd,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, src_lds_direct
+// CHECK: [0xfe,0x6e,0x0a,0x7e]
+
+v_screen_partition_4se_b32 v5, 0xaf123456
+// CHECK: [0xff,0x6e,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_screen_partition_4se_b32 v5, 0x3f717273
+// CHECK: [0xff,0x6e,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_f16_u16 v5, v1
+// CHECK: [0x01,0x73,0x0a,0x7e]
+
+v_cvt_f16_u16 v255, v1
+// CHECK: [0x01,0x73,0xfe,0x7f]
+
+v_cvt_f16_u16 v5, v255
+// CHECK: [0xff,0x73,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, s1
+// CHECK: [0x01,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, s101
+// CHECK: [0x65,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, flat_scratch_lo
+// CHECK: [0x66,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, flat_scratch_hi
+// CHECK: [0x67,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, vcc_lo
+// CHECK: [0x6a,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, vcc_hi
+// CHECK: [0x6b,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, ttmp15
+// CHECK: [0x7b,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, m0
+// CHECK: [0x7c,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, exec_lo
+// CHECK: [0x7e,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, exec_hi
+// CHECK: [0x7f,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, 0
+// CHECK: [0x80,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, -1
+// CHECK: [0xc1,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, 0.5
+// CHECK: [0xff,0x72,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_u16 v5, -4.0
+// CHECK: [0xff,0x72,0x0a,0x7e,0x00,0xc4,0x00,0x00]
+
+v_cvt_f16_u16 v5, src_vccz
+// CHECK: [0xfb,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, src_execz
+// CHECK: [0xfc,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, src_scc
+// CHECK: [0xfd,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, src_lds_direct
+// CHECK: [0xfe,0x72,0x0a,0x7e]
+
+v_cvt_f16_u16 v5, 0xfe0b
+// CHECK: [0xff,0x72,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f16_u16 v5, 0x3456
+// CHECK: [0xff,0x72,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_f16_i16 v5, v1
+// CHECK: [0x01,0x75,0x0a,0x7e]
+
+v_cvt_f16_i16 v255, v1
+// CHECK: [0x01,0x75,0xfe,0x7f]
+
+v_cvt_f16_i16 v5, v255
+// CHECK: [0xff,0x75,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, s1
+// CHECK: [0x01,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, s101
+// CHECK: [0x65,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, flat_scratch_lo
+// CHECK: [0x66,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, flat_scratch_hi
+// CHECK: [0x67,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, vcc_lo
+// CHECK: [0x6a,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, vcc_hi
+// CHECK: [0x6b,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, ttmp15
+// CHECK: [0x7b,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, m0
+// CHECK: [0x7c,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, exec_lo
+// CHECK: [0x7e,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, exec_hi
+// CHECK: [0x7f,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, 0
+// CHECK: [0x80,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, -1
+// CHECK: [0xc1,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, 0.5
+// CHECK: [0xff,0x74,0x0a,0x7e,0x00,0x38,0x00,0x00]
+
+v_cvt_f16_i16 v5, -4.0
+// CHECK: [0xff,0x74,0x0a,0x7e,0x00,0xc4,0x00,0x00]
+
+v_cvt_f16_i16 v5, src_vccz
+// CHECK: [0xfb,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, src_execz
+// CHECK: [0xfc,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, src_scc
+// CHECK: [0xfd,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, src_lds_direct
+// CHECK: [0xfe,0x74,0x0a,0x7e]
+
+v_cvt_f16_i16 v5, 0xfe0b
+// CHECK: [0xff,0x74,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_f16_i16 v5, 0x3456
+// CHECK: [0xff,0x74,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_u16_f16 v5, v1
+// CHECK: [0x01,0x77,0x0a,0x7e]
+
+v_cvt_u16_f16 v255, v1
+// CHECK: [0x01,0x77,0xfe,0x7f]
+
+v_cvt_u16_f16 v5, v255
+// CHECK: [0xff,0x77,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, s1
+// CHECK: [0x01,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, s101
+// CHECK: [0x65,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, vcc_lo
+// CHECK: [0x6a,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, vcc_hi
+// CHECK: [0x6b,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, ttmp15
+// CHECK: [0x7b,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, m0
+// CHECK: [0x7c,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, exec_lo
+// CHECK: [0x7e,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, exec_hi
+// CHECK: [0x7f,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, 0
+// CHECK: [0x80,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, -1
+// CHECK: [0xc1,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, 0.5
+// CHECK: [0xf0,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, -4.0
+// CHECK: [0xf7,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, src_vccz
+// CHECK: [0xfb,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, src_execz
+// CHECK: [0xfc,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, src_scc
+// CHECK: [0xfd,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x76,0x0a,0x7e]
+
+v_cvt_u16_f16 v5, 0xfe0b
+// CHECK: [0xff,0x76,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_u16_f16 v5, 0x3456
+// CHECK: [0xff,0x76,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_i16_f16 v5, v1
+// CHECK: [0x01,0x79,0x0a,0x7e]
+
+v_cvt_i16_f16 v255, v1
+// CHECK: [0x01,0x79,0xfe,0x7f]
+
+v_cvt_i16_f16 v5, v255
+// CHECK: [0xff,0x79,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, s1
+// CHECK: [0x01,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, s101
+// CHECK: [0x65,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, vcc_lo
+// CHECK: [0x6a,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, vcc_hi
+// CHECK: [0x6b,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, ttmp15
+// CHECK: [0x7b,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, m0
+// CHECK: [0x7c,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, exec_lo
+// CHECK: [0x7e,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, exec_hi
+// CHECK: [0x7f,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, 0
+// CHECK: [0x80,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, -1
+// CHECK: [0xc1,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, 0.5
+// CHECK: [0xf0,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, -4.0
+// CHECK: [0xf7,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, src_vccz
+// CHECK: [0xfb,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, src_execz
+// CHECK: [0xfc,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, src_scc
+// CHECK: [0xfd,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x78,0x0a,0x7e]
+
+v_cvt_i16_f16 v5, 0xfe0b
+// CHECK: [0xff,0x78,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_i16_f16 v5, 0x3456
+// CHECK: [0xff,0x78,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_rcp_f16 v5, v1
+// CHECK: [0x01,0x7b,0x0a,0x7e]
+
+v_rcp_f16 v255, v1
+// CHECK: [0x01,0x7b,0xfe,0x7f]
+
+v_rcp_f16 v5, v255
+// CHECK: [0xff,0x7b,0x0a,0x7e]
+
+v_rcp_f16 v5, s1
+// CHECK: [0x01,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, s101
+// CHECK: [0x65,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, vcc_lo
+// CHECK: [0x6a,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, vcc_hi
+// CHECK: [0x6b,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, ttmp15
+// CHECK: [0x7b,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, m0
+// CHECK: [0x7c,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, exec_lo
+// CHECK: [0x7e,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, exec_hi
+// CHECK: [0x7f,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, 0
+// CHECK: [0x80,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, -1
+// CHECK: [0xc1,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, 0.5
+// CHECK: [0xf0,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, -4.0
+// CHECK: [0xf7,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, src_vccz
+// CHECK: [0xfb,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, src_execz
+// CHECK: [0xfc,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, src_scc
+// CHECK: [0xfd,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x7a,0x0a,0x7e]
+
+v_rcp_f16 v5, 0xfe0b
+// CHECK: [0xff,0x7a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rcp_f16 v5, 0x3456
+// CHECK: [0xff,0x7a,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_sqrt_f16 v5, v1
+// CHECK: [0x01,0x7d,0x0a,0x7e]
+
+v_sqrt_f16 v255, v1
+// CHECK: [0x01,0x7d,0xfe,0x7f]
+
+v_sqrt_f16 v5, v255
+// CHECK: [0xff,0x7d,0x0a,0x7e]
+
+v_sqrt_f16 v5, s1
+// CHECK: [0x01,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, s101
+// CHECK: [0x65,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, vcc_lo
+// CHECK: [0x6a,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, vcc_hi
+// CHECK: [0x6b,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, ttmp15
+// CHECK: [0x7b,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, m0
+// CHECK: [0x7c,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, exec_lo
+// CHECK: [0x7e,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, exec_hi
+// CHECK: [0x7f,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, 0
+// CHECK: [0x80,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, -1
+// CHECK: [0xc1,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, 0.5
+// CHECK: [0xf0,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, -4.0
+// CHECK: [0xf7,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, src_vccz
+// CHECK: [0xfb,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, src_execz
+// CHECK: [0xfc,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, src_scc
+// CHECK: [0xfd,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x7c,0x0a,0x7e]
+
+v_sqrt_f16 v5, 0xfe0b
+// CHECK: [0xff,0x7c,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sqrt_f16 v5, 0x3456
+// CHECK: [0xff,0x7c,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_rsq_f16 v5, v1
+// CHECK: [0x01,0x7f,0x0a,0x7e]
+
+v_rsq_f16 v255, v1
+// CHECK: [0x01,0x7f,0xfe,0x7f]
+
+v_rsq_f16 v5, v255
+// CHECK: [0xff,0x7f,0x0a,0x7e]
+
+v_rsq_f16 v5, s1
+// CHECK: [0x01,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, s101
+// CHECK: [0x65,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, vcc_lo
+// CHECK: [0x6a,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, vcc_hi
+// CHECK: [0x6b,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, ttmp15
+// CHECK: [0x7b,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, m0
+// CHECK: [0x7c,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, exec_lo
+// CHECK: [0x7e,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, exec_hi
+// CHECK: [0x7f,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, 0
+// CHECK: [0x80,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, -1
+// CHECK: [0xc1,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, 0.5
+// CHECK: [0xf0,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, -4.0
+// CHECK: [0xf7,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, src_vccz
+// CHECK: [0xfb,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, src_execz
+// CHECK: [0xfc,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, src_scc
+// CHECK: [0xfd,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x7e,0x0a,0x7e]
+
+v_rsq_f16 v5, 0xfe0b
+// CHECK: [0xff,0x7e,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rsq_f16 v5, 0x3456
+// CHECK: [0xff,0x7e,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_log_f16 v5, v1
+// CHECK: [0x01,0x81,0x0a,0x7e]
+
+v_log_f16 v255, v1
+// CHECK: [0x01,0x81,0xfe,0x7f]
+
+v_log_f16 v5, v255
+// CHECK: [0xff,0x81,0x0a,0x7e]
+
+v_log_f16 v5, s1
+// CHECK: [0x01,0x80,0x0a,0x7e]
+
+v_log_f16 v5, s101
+// CHECK: [0x65,0x80,0x0a,0x7e]
+
+v_log_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x80,0x0a,0x7e]
+
+v_log_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x80,0x0a,0x7e]
+
+v_log_f16 v5, vcc_lo
+// CHECK: [0x6a,0x80,0x0a,0x7e]
+
+v_log_f16 v5, vcc_hi
+// CHECK: [0x6b,0x80,0x0a,0x7e]
+
+v_log_f16 v5, ttmp15
+// CHECK: [0x7b,0x80,0x0a,0x7e]
+
+v_log_f16 v5, m0
+// CHECK: [0x7c,0x80,0x0a,0x7e]
+
+v_log_f16 v5, exec_lo
+// CHECK: [0x7e,0x80,0x0a,0x7e]
+
+v_log_f16 v5, exec_hi
+// CHECK: [0x7f,0x80,0x0a,0x7e]
+
+v_log_f16 v5, 0
+// CHECK: [0x80,0x80,0x0a,0x7e]
+
+v_log_f16 v5, -1
+// CHECK: [0xc1,0x80,0x0a,0x7e]
+
+v_log_f16 v5, 0.5
+// CHECK: [0xf0,0x80,0x0a,0x7e]
+
+v_log_f16 v5, -4.0
+// CHECK: [0xf7,0x80,0x0a,0x7e]
+
+v_log_f16 v5, src_vccz
+// CHECK: [0xfb,0x80,0x0a,0x7e]
+
+v_log_f16 v5, src_execz
+// CHECK: [0xfc,0x80,0x0a,0x7e]
+
+v_log_f16 v5, src_scc
+// CHECK: [0xfd,0x80,0x0a,0x7e]
+
+v_log_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x80,0x0a,0x7e]
+
+v_log_f16 v5, 0xfe0b
+// CHECK: [0xff,0x80,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_log_f16 v5, 0x3456
+// CHECK: [0xff,0x80,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_exp_f16 v5, v1
+// CHECK: [0x01,0x83,0x0a,0x7e]
+
+v_exp_f16 v255, v1
+// CHECK: [0x01,0x83,0xfe,0x7f]
+
+v_exp_f16 v5, v255
+// CHECK: [0xff,0x83,0x0a,0x7e]
+
+v_exp_f16 v5, s1
+// CHECK: [0x01,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, s101
+// CHECK: [0x65,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, vcc_lo
+// CHECK: [0x6a,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, vcc_hi
+// CHECK: [0x6b,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, ttmp15
+// CHECK: [0x7b,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, m0
+// CHECK: [0x7c,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, exec_lo
+// CHECK: [0x7e,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, exec_hi
+// CHECK: [0x7f,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, 0
+// CHECK: [0x80,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, -1
+// CHECK: [0xc1,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, 0.5
+// CHECK: [0xf0,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, -4.0
+// CHECK: [0xf7,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, src_vccz
+// CHECK: [0xfb,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, src_execz
+// CHECK: [0xfc,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, src_scc
+// CHECK: [0xfd,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x82,0x0a,0x7e]
+
+v_exp_f16 v5, 0xfe0b
+// CHECK: [0xff,0x82,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_exp_f16 v5, 0x3456
+// CHECK: [0xff,0x82,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_frexp_mant_f16 v5, v1
+// CHECK: [0x01,0x85,0x0a,0x7e]
+
+v_frexp_mant_f16 v255, v1
+// CHECK: [0x01,0x85,0xfe,0x7f]
+
+v_frexp_mant_f16 v5, v255
+// CHECK: [0xff,0x85,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, s1
+// CHECK: [0x01,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, s101
+// CHECK: [0x65,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, vcc_lo
+// CHECK: [0x6a,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, vcc_hi
+// CHECK: [0x6b,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, ttmp15
+// CHECK: [0x7b,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, m0
+// CHECK: [0x7c,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, exec_lo
+// CHECK: [0x7e,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, exec_hi
+// CHECK: [0x7f,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, 0
+// CHECK: [0x80,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, -1
+// CHECK: [0xc1,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, 0.5
+// CHECK: [0xf0,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, -4.0
+// CHECK: [0xf7,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, src_vccz
+// CHECK: [0xfb,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, src_execz
+// CHECK: [0xfc,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, src_scc
+// CHECK: [0xfd,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x84,0x0a,0x7e]
+
+v_frexp_mant_f16 v5, 0xfe0b
+// CHECK: [0xff,0x84,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_frexp_mant_f16 v5, 0x3456
+// CHECK: [0xff,0x84,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_frexp_exp_i16_f16 v5, v1
+// CHECK: [0x01,0x87,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v255, v1
+// CHECK: [0x01,0x87,0xfe,0x7f]
+
+v_frexp_exp_i16_f16 v5, v255
+// CHECK: [0xff,0x87,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, s1
+// CHECK: [0x01,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, s101
+// CHECK: [0x65,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, vcc_lo
+// CHECK: [0x6a,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, vcc_hi
+// CHECK: [0x6b,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, ttmp15
+// CHECK: [0x7b,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, m0
+// CHECK: [0x7c,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, exec_lo
+// CHECK: [0x7e,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, exec_hi
+// CHECK: [0x7f,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, 0
+// CHECK: [0x80,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, -1
+// CHECK: [0xc1,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, 0.5
+// CHECK: [0xf0,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, -4.0
+// CHECK: [0xf7,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, src_vccz
+// CHECK: [0xfb,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, src_execz
+// CHECK: [0xfc,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, src_scc
+// CHECK: [0xfd,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x86,0x0a,0x7e]
+
+v_frexp_exp_i16_f16 v5, 0xfe0b
+// CHECK: [0xff,0x86,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_frexp_exp_i16_f16 v5, 0x3456
+// CHECK: [0xff,0x86,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_floor_f16 v5, v1
+// CHECK: [0x01,0x89,0x0a,0x7e]
+
+v_floor_f16 v255, v1
+// CHECK: [0x01,0x89,0xfe,0x7f]
+
+v_floor_f16 v5, v255
+// CHECK: [0xff,0x89,0x0a,0x7e]
+
+v_floor_f16 v5, s1
+// CHECK: [0x01,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, s101
+// CHECK: [0x65,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, vcc_lo
+// CHECK: [0x6a,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, vcc_hi
+// CHECK: [0x6b,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, ttmp15
+// CHECK: [0x7b,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, m0
+// CHECK: [0x7c,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, exec_lo
+// CHECK: [0x7e,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, exec_hi
+// CHECK: [0x7f,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, 0
+// CHECK: [0x80,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, -1
+// CHECK: [0xc1,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, 0.5
+// CHECK: [0xf0,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, -4.0
+// CHECK: [0xf7,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, src_vccz
+// CHECK: [0xfb,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, src_execz
+// CHECK: [0xfc,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, src_scc
+// CHECK: [0xfd,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x88,0x0a,0x7e]
+
+v_floor_f16 v5, 0xfe0b
+// CHECK: [0xff,0x88,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_floor_f16 v5, 0x3456
+// CHECK: [0xff,0x88,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_ceil_f16 v5, v1
+// CHECK: [0x01,0x8b,0x0a,0x7e]
+
+v_ceil_f16 v255, v1
+// CHECK: [0x01,0x8b,0xfe,0x7f]
+
+v_ceil_f16 v5, v255
+// CHECK: [0xff,0x8b,0x0a,0x7e]
+
+v_ceil_f16 v5, s1
+// CHECK: [0x01,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, s101
+// CHECK: [0x65,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, vcc_lo
+// CHECK: [0x6a,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, vcc_hi
+// CHECK: [0x6b,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, ttmp15
+// CHECK: [0x7b,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, m0
+// CHECK: [0x7c,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, exec_lo
+// CHECK: [0x7e,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, exec_hi
+// CHECK: [0x7f,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, 0
+// CHECK: [0x80,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, -1
+// CHECK: [0xc1,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, 0.5
+// CHECK: [0xf0,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, -4.0
+// CHECK: [0xf7,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, src_vccz
+// CHECK: [0xfb,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, src_execz
+// CHECK: [0xfc,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, src_scc
+// CHECK: [0xfd,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x8a,0x0a,0x7e]
+
+v_ceil_f16 v5, 0xfe0b
+// CHECK: [0xff,0x8a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_ceil_f16 v5, 0x3456
+// CHECK: [0xff,0x8a,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_trunc_f16 v5, v1
+// CHECK: [0x01,0x8d,0x0a,0x7e]
+
+v_trunc_f16 v255, v1
+// CHECK: [0x01,0x8d,0xfe,0x7f]
+
+v_trunc_f16 v5, v255
+// CHECK: [0xff,0x8d,0x0a,0x7e]
+
+v_trunc_f16 v5, s1
+// CHECK: [0x01,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, s101
+// CHECK: [0x65,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, vcc_lo
+// CHECK: [0x6a,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, vcc_hi
+// CHECK: [0x6b,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, ttmp15
+// CHECK: [0x7b,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, m0
+// CHECK: [0x7c,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, exec_lo
+// CHECK: [0x7e,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, exec_hi
+// CHECK: [0x7f,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, 0
+// CHECK: [0x80,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, -1
+// CHECK: [0xc1,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, 0.5
+// CHECK: [0xf0,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, -4.0
+// CHECK: [0xf7,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, src_vccz
+// CHECK: [0xfb,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, src_execz
+// CHECK: [0xfc,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, src_scc
+// CHECK: [0xfd,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x8c,0x0a,0x7e]
+
+v_trunc_f16 v5, 0xfe0b
+// CHECK: [0xff,0x8c,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_trunc_f16 v5, 0x3456
+// CHECK: [0xff,0x8c,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_rndne_f16 v5, v1
+// CHECK: [0x01,0x8f,0x0a,0x7e]
+
+v_rndne_f16 v255, v1
+// CHECK: [0x01,0x8f,0xfe,0x7f]
+
+v_rndne_f16 v5, v255
+// CHECK: [0xff,0x8f,0x0a,0x7e]
+
+v_rndne_f16 v5, s1
+// CHECK: [0x01,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, s101
+// CHECK: [0x65,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, vcc_lo
+// CHECK: [0x6a,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, vcc_hi
+// CHECK: [0x6b,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, ttmp15
+// CHECK: [0x7b,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, m0
+// CHECK: [0x7c,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, exec_lo
+// CHECK: [0x7e,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, exec_hi
+// CHECK: [0x7f,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, 0
+// CHECK: [0x80,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, -1
+// CHECK: [0xc1,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, 0.5
+// CHECK: [0xf0,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, -4.0
+// CHECK: [0xf7,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, src_vccz
+// CHECK: [0xfb,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, src_execz
+// CHECK: [0xfc,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, src_scc
+// CHECK: [0xfd,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x8e,0x0a,0x7e]
+
+v_rndne_f16 v5, 0xfe0b
+// CHECK: [0xff,0x8e,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_rndne_f16 v5, 0x3456
+// CHECK: [0xff,0x8e,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_fract_f16 v5, v1
+// CHECK: [0x01,0x91,0x0a,0x7e]
+
+v_fract_f16 v255, v1
+// CHECK: [0x01,0x91,0xfe,0x7f]
+
+v_fract_f16 v5, v255
+// CHECK: [0xff,0x91,0x0a,0x7e]
+
+v_fract_f16 v5, s1
+// CHECK: [0x01,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, s101
+// CHECK: [0x65,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, vcc_lo
+// CHECK: [0x6a,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, vcc_hi
+// CHECK: [0x6b,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, ttmp15
+// CHECK: [0x7b,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, m0
+// CHECK: [0x7c,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, exec_lo
+// CHECK: [0x7e,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, exec_hi
+// CHECK: [0x7f,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, 0
+// CHECK: [0x80,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, -1
+// CHECK: [0xc1,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, 0.5
+// CHECK: [0xf0,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, -4.0
+// CHECK: [0xf7,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, src_vccz
+// CHECK: [0xfb,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, src_execz
+// CHECK: [0xfc,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, src_scc
+// CHECK: [0xfd,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x90,0x0a,0x7e]
+
+v_fract_f16 v5, 0xfe0b
+// CHECK: [0xff,0x90,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_fract_f16 v5, 0x3456
+// CHECK: [0xff,0x90,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_sin_f16 v5, v1
+// CHECK: [0x01,0x93,0x0a,0x7e]
+
+v_sin_f16 v255, v1
+// CHECK: [0x01,0x93,0xfe,0x7f]
+
+v_sin_f16 v5, v255
+// CHECK: [0xff,0x93,0x0a,0x7e]
+
+v_sin_f16 v5, s1
+// CHECK: [0x01,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, s101
+// CHECK: [0x65,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, vcc_lo
+// CHECK: [0x6a,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, vcc_hi
+// CHECK: [0x6b,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, ttmp15
+// CHECK: [0x7b,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, m0
+// CHECK: [0x7c,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, exec_lo
+// CHECK: [0x7e,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, exec_hi
+// CHECK: [0x7f,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, 0
+// CHECK: [0x80,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, -1
+// CHECK: [0xc1,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, 0.5
+// CHECK: [0xf0,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, -4.0
+// CHECK: [0xf7,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, src_vccz
+// CHECK: [0xfb,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, src_execz
+// CHECK: [0xfc,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, src_scc
+// CHECK: [0xfd,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x92,0x0a,0x7e]
+
+v_sin_f16 v5, 0xfe0b
+// CHECK: [0xff,0x92,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sin_f16 v5, 0x3456
+// CHECK: [0xff,0x92,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cos_f16 v5, v1
+// CHECK: [0x01,0x95,0x0a,0x7e]
+
+v_cos_f16 v255, v1
+// CHECK: [0x01,0x95,0xfe,0x7f]
+
+v_cos_f16 v5, v255
+// CHECK: [0xff,0x95,0x0a,0x7e]
+
+v_cos_f16 v5, s1
+// CHECK: [0x01,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, s101
+// CHECK: [0x65,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, vcc_lo
+// CHECK: [0x6a,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, vcc_hi
+// CHECK: [0x6b,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, ttmp15
+// CHECK: [0x7b,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, m0
+// CHECK: [0x7c,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, exec_lo
+// CHECK: [0x7e,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, exec_hi
+// CHECK: [0x7f,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, 0
+// CHECK: [0x80,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, -1
+// CHECK: [0xc1,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, 0.5
+// CHECK: [0xf0,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, -4.0
+// CHECK: [0xf7,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, src_vccz
+// CHECK: [0xfb,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, src_execz
+// CHECK: [0xfc,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, src_scc
+// CHECK: [0xfd,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x94,0x0a,0x7e]
+
+v_cos_f16 v5, 0xfe0b
+// CHECK: [0xff,0x94,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cos_f16 v5, 0x3456
+// CHECK: [0xff,0x94,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_exp_legacy_f32 v5, v1
+// CHECK: [0x01,0x97,0x0a,0x7e]
+
+v_exp_legacy_f32 v255, v1
+// CHECK: [0x01,0x97,0xfe,0x7f]
+
+v_exp_legacy_f32 v5, v255
+// CHECK: [0xff,0x97,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, s1
+// CHECK: [0x01,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, s101
+// CHECK: [0x65,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, vcc_lo
+// CHECK: [0x6a,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, vcc_hi
+// CHECK: [0x6b,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, ttmp15
+// CHECK: [0x7b,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, m0
+// CHECK: [0x7c,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, exec_lo
+// CHECK: [0x7e,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, exec_hi
+// CHECK: [0x7f,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, 0
+// CHECK: [0x80,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, -1
+// CHECK: [0xc1,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, 0.5
+// CHECK: [0xf0,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, -4.0
+// CHECK: [0xf7,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_vccz
+// CHECK: [0xfb,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_execz
+// CHECK: [0xfc,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_scc
+// CHECK: [0xfd,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x96,0x0a,0x7e]
+
+v_exp_legacy_f32 v5, 0xaf123456
+// CHECK: [0xff,0x96,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_exp_legacy_f32 v5, 0x3f717273
+// CHECK: [0xff,0x96,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_log_legacy_f32 v5, v1
+// CHECK: [0x01,0x99,0x0a,0x7e]
+
+v_log_legacy_f32 v255, v1
+// CHECK: [0x01,0x99,0xfe,0x7f]
+
+v_log_legacy_f32 v5, v255
+// CHECK: [0xff,0x99,0x0a,0x7e]
+
+v_log_legacy_f32 v5, s1
+// CHECK: [0x01,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, s101
+// CHECK: [0x65,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, flat_scratch_lo
+// CHECK: [0x66,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, flat_scratch_hi
+// CHECK: [0x67,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, vcc_lo
+// CHECK: [0x6a,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, vcc_hi
+// CHECK: [0x6b,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, ttmp15
+// CHECK: [0x7b,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, m0
+// CHECK: [0x7c,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, exec_lo
+// CHECK: [0x7e,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, exec_hi
+// CHECK: [0x7f,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, 0
+// CHECK: [0x80,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, -1
+// CHECK: [0xc1,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, 0.5
+// CHECK: [0xf0,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, -4.0
+// CHECK: [0xf7,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_vccz
+// CHECK: [0xfb,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_execz
+// CHECK: [0xfc,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_scc
+// CHECK: [0xfd,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, src_lds_direct
+// CHECK: [0xfe,0x98,0x0a,0x7e]
+
+v_log_legacy_f32 v5, 0xaf123456
+// CHECK: [0xff,0x98,0x0a,0x7e,0x56,0x34,0x12,0xaf]
+
+v_log_legacy_f32 v5, 0x3f717273
+// CHECK: [0xff,0x98,0x0a,0x7e,0x73,0x72,0x71,0x3f]
+
+v_cvt_norm_i16_f16 v5, v1
+// CHECK: [0x01,0x9b,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v255, v1
+// CHECK: [0x01,0x9b,0xfe,0x7f]
+
+v_cvt_norm_i16_f16 v5, v255
+// CHECK: [0xff,0x9b,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, s1
+// CHECK: [0x01,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, s101
+// CHECK: [0x65,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, vcc_lo
+// CHECK: [0x6a,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, vcc_hi
+// CHECK: [0x6b,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, ttmp15
+// CHECK: [0x7b,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, m0
+// CHECK: [0x7c,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, exec_lo
+// CHECK: [0x7e,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, exec_hi
+// CHECK: [0x7f,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, 0
+// CHECK: [0x80,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, -1
+// CHECK: [0xc1,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, 0.5
+// CHECK: [0xf0,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, -4.0
+// CHECK: [0xf7,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, src_vccz
+// CHECK: [0xfb,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, src_execz
+// CHECK: [0xfc,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, src_scc
+// CHECK: [0xfd,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x9a,0x0a,0x7e]
+
+v_cvt_norm_i16_f16 v5, 0xfe0b
+// CHECK: [0xff,0x9a,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_norm_i16_f16 v5, 0x3456
+// CHECK: [0xff,0x9a,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_cvt_norm_u16_f16 v5, v1
+// CHECK: [0x01,0x9d,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v255, v1
+// CHECK: [0x01,0x9d,0xfe,0x7f]
+
+v_cvt_norm_u16_f16 v5, v255
+// CHECK: [0xff,0x9d,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, s1
+// CHECK: [0x01,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, s101
+// CHECK: [0x65,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, flat_scratch_lo
+// CHECK: [0x66,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, flat_scratch_hi
+// CHECK: [0x67,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, vcc_lo
+// CHECK: [0x6a,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, vcc_hi
+// CHECK: [0x6b,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, ttmp15
+// CHECK: [0x7b,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, m0
+// CHECK: [0x7c,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, exec_lo
+// CHECK: [0x7e,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, exec_hi
+// CHECK: [0x7f,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, 0
+// CHECK: [0x80,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, -1
+// CHECK: [0xc1,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, 0.5
+// CHECK: [0xf0,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, -4.0
+// CHECK: [0xf7,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, src_vccz
+// CHECK: [0xfb,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, src_execz
+// CHECK: [0xfc,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, src_scc
+// CHECK: [0xfd,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, src_lds_direct
+// CHECK: [0xfe,0x9c,0x0a,0x7e]
+
+v_cvt_norm_u16_f16 v5, 0xfe0b
+// CHECK: [0xff,0x9c,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_cvt_norm_u16_f16 v5, 0x3456
+// CHECK: [0xff,0x9c,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_sat_pk_u8_i16 v5, v1
+// CHECK: [0x01,0x9f,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v255, v1
+// CHECK: [0x01,0x9f,0xfe,0x7f]
+
+v_sat_pk_u8_i16 v5, v255
+// CHECK: [0xff,0x9f,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, s1
+// CHECK: [0x01,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, s101
+// CHECK: [0x65,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, flat_scratch_lo
+// CHECK: [0x66,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, flat_scratch_hi
+// CHECK: [0x67,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, vcc_lo
+// CHECK: [0x6a,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, vcc_hi
+// CHECK: [0x6b,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, ttmp15
+// CHECK: [0x7b,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, m0
+// CHECK: [0x7c,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, exec_lo
+// CHECK: [0x7e,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, exec_hi
+// CHECK: [0x7f,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, 0
+// CHECK: [0x80,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, -1
+// CHECK: [0xc1,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, 0.5
+// CHECK: [0xf0,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, -4.0
+// CHECK: [0xf7,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, src_vccz
+// CHECK: [0xfb,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, src_execz
+// CHECK: [0xfc,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, src_scc
+// CHECK: [0xfd,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, src_lds_direct
+// CHECK: [0xfe,0x9e,0x0a,0x7e]
+
+v_sat_pk_u8_i16 v5, 0xfe0b
+// CHECK: [0xff,0x9e,0x0a,0x7e,0x0b,0xfe,0x00,0x00]
+
+v_sat_pk_u8_i16 v5, 0x3456
+// CHECK: [0xff,0x9e,0x0a,0x7e,0x56,0x34,0x00,0x00]
+
+v_swap_b32 v5, v1
+// CHECK: [0x01,0xa3,0x0a,0x7e]
+
+v_swap_b32 v255, v1
+// CHECK: [0x01,0xa3,0xfe,0x7f]
+
+v_swap_b32 v5, v255
+// CHECK: [0xff,0xa3,0x0a,0x7e]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_mov_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_mov_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x02,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_mov_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_mov_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_mov_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x0a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x0c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_u32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_u32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_u32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x0e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_u32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_u32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_u32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x0e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x10,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x10,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f16_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f16_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_f16_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x14,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f16_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_f16_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x14,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_f32_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x16,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_f32_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x16,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_rpi_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x18,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_rpi_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x18,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_flr_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_flr_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_off_f32_i4_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x1c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x1c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte0_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x22,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x22,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte1_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x24,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x24,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte2_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x26,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x26,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f32_ubyte3_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x28,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x28,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_fract_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_fract_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_fract_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_fract_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x36,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_fract_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_fract_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_fract_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_fract_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_fract_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x36,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_trunc_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_trunc_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_trunc_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_trunc_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x38,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_trunc_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_trunc_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_trunc_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_trunc_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_trunc_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x38,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_ceil_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ceil_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ceil_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_ceil_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ceil_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ceil_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ceil_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ceil_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_ceil_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_rndne_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rndne_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rndne_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rndne_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3c,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rndne_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rndne_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rndne_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rndne_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rndne_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_floor_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_floor_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_floor_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_floor_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x3e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_floor_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_floor_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_floor_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_floor_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_floor_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x3e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_exp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_exp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_exp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_exp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x40,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_exp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_exp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_exp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_exp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_exp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x40,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_log_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_log_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_log_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_log_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x42,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_log_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_log_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_log_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_log_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_log_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_log_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_log_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_log_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_log_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_log_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x42,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_rcp_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rcp_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rcp_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rcp_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x44,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rcp_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rcp_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rcp_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rcp_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rcp_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x44,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rcp_iflag_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rcp_iflag_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rcp_iflag_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x46,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_iflag_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rcp_iflag_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rcp_iflag_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x46,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_rsq_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rsq_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rsq_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rsq_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x48,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rsq_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rsq_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rsq_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rsq_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rsq_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x48,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_sqrt_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sqrt_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sqrt_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sqrt_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x4e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sqrt_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_sqrt_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x4e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_sin_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sin_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sin_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sin_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x52,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sin_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sin_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sin_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sin_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_sin_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x52,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cos_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cos_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cos_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cos_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x54,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cos_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cos_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cos_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cos_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cos_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x54,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_not_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_not_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_not_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x56,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_not_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_not_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_not_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_not_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_not_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_not_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_not_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_not_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_not_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x56,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_bfrev_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_bfrev_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x58,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_bfrev_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_bfrev_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x58,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ffbh_u32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ffbh_u32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5a,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ffbh_u32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ffbh_u32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_u32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x5a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ffbl_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ffbl_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5c,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ffbl_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ffbl_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbl_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x5c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ffbh_i32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ffbh_i32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x5e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ffbh_i32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ffbh_i32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ffbh_i32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x5e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_exp_i32_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x66,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_frexp_exp_i32_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x66,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_mant_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_mant_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_mant_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x68,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_mant_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_frexp_mant_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x68,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_screen_partition_4se_b32_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x6e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_screen_partition_4se_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_screen_partition_4se_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x6e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f16_u16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f16_u16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x72,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_u16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_u16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_u16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x72,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_f16_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_f16_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x74,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_i16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_f16_i16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_f16_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x74,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_u16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_u16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x76,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_u16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_u16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_u16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x76,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x78,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x78,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_rcp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rcp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rcp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rcp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rcp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rcp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rcp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rcp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rcp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rcp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_sqrt_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sqrt_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sqrt_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sqrt_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7c,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sqrt_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sqrt_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sqrt_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_sqrt_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_rsq_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rsq_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rsq_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rsq_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x7e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rsq_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rsq_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rsq_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rsq_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rsq_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rsq_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x7e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_log_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_log_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_log_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_log_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x80,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_log_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_log_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_log_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_log_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_log_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_log_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_log_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_log_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_log_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_log_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x80,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_exp_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_exp_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_exp_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_exp_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x82,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_exp_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_exp_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_exp_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_exp_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_exp_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x82,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_mant_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_mant_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_mant_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x84,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_mant_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_mant_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_mant_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_frexp_mant_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x84,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_frexp_exp_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x86,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_frexp_exp_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x86,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_floor_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_floor_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_floor_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_floor_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x88,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_floor_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_floor_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_floor_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_floor_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_floor_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_floor_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x88,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_ceil_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_ceil_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_ceil_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_ceil_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_ceil_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_ceil_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_ceil_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_ceil_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_ceil_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_ceil_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_trunc_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_trunc_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_trunc_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_trunc_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8c,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_trunc_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_trunc_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_trunc_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_trunc_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_trunc_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_trunc_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_rndne_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_rndne_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_rndne_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_rndne_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x8e,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_rndne_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_rndne_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_rndne_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_rndne_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_rndne_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_rndne_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x8e,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_fract_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_fract_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_fract_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_fract_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x90,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_fract_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_fract_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_fract_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_fract_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_fract_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_fract_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x90,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_sin_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sin_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sin_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_sin_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x92,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sin_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sin_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sin_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sin_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_sin_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_sin_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x92,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cos_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cos_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cos_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cos_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x94,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cos_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cos_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cos_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cos_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cos_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cos_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x94,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_exp_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_exp_legacy_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_exp_legacy_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x96,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_exp_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_exp_legacy_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_exp_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_exp_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_exp_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x96,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x46,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x86,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0xc6,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_log_legacy_f32_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_log_legacy_f32_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_log_legacy_f32_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x98,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_log_legacy_f32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_log_legacy_f32_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_log_legacy_f32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_log_legacy_f32_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_log_legacy_f32_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x98,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_norm_i16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9a,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_norm_i16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_norm_i16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9a,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x26,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, -v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x16,0x00]
+
+v_cvt_norm_u16_f16_sdwa v5, |v1| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9c,0x0a,0x7e,0x01,0x06,0x26,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_cvt_norm_u16_f16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x08,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, -v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x10,0x00]
+
+v_cvt_norm_u16_f16_dpp v5, |v1| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9c,0x0a,0x7e,0x01,0xe4,0x20,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v255, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0xfe,0x7f,0x01,0x06,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0xff,0x06,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, s1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, s101 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x65,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, flat_scratch_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x66,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, flat_scratch_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x67,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x6a,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x6b,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, ttmp15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x7b,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, m0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x7c,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, exec_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x7e,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, exec_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x7f,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x80,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, -1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0xc1,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, 0.5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0xf0,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, -4.0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0xf7,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, src_vccz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0xfb,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, src_execz dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0xfc,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, src_scc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0xfd,0x06,0x86,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x00,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x01,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x02,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x03,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x04,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x05,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x0e,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x16,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x06,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x00,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x01,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x02,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x03,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x04,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x05,0x00]
+
+v_sat_pk_u8_i16_sdwa v5, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x9e,0x0a,0x7e,0x01,0x06,0x0e,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x00,0x00]
+
+v_sat_pk_u8_i16_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0xfe,0x7f,0x01,0xe4,0x00,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0xff,0xe4,0x00,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x40,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x41,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x42,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x43,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x30,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x34,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x38,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x3c,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x01,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x0f,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x11,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x1f,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x21,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0x2f,0x01,0x00]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x00,0x10]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x00,0x30]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x00,0xf0]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x00,0x01]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x00,0x03]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x00,0x0f]
+
+v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x9e,0x0a,0x7e,0x01,0xe4,0x08,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s
new file mode 100644
index 0000000000000..9642aa06ddad9
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop2.s
@@ -0,0 +1,14962 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+v_cndmask_b32 v5, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x00]
+
+v_cndmask_b32 v255, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x01]
+
+v_cndmask_b32 v5, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x00]
+
+v_cndmask_b32 v5, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, src_lds_direct, v2, vcc
+// CHECK: [0xfe,0x04,0x0a,0x00]
+
+v_cndmask_b32 v5, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x00]
+
+v_add_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x02]
+
+v_add_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x03]
+
+v_add_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x02]
+
+v_add_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x02]
+
+v_add_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x02]
+
+v_add_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x02]
+
+v_add_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x02]
+
+v_add_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x02]
+
+v_add_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x02]
+
+v_add_f32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x02]
+
+v_add_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x02]
+
+v_add_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x02]
+
+v_add_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x02]
+
+v_add_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x02]
+
+v_add_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x02]
+
+v_add_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x02]
+
+v_add_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x02]
+
+v_add_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x02]
+
+v_add_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x02]
+
+v_add_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x02]
+
+v_add_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x02]
+
+v_add_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x02,0x56,0x34,0x12,0xaf]
+
+v_add_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x02,0x73,0x72,0x71,0x3f]
+
+v_add_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x02]
+
+v_sub_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x04]
+
+v_sub_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x05]
+
+v_sub_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x04]
+
+v_sub_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x04]
+
+v_sub_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x04]
+
+v_sub_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x04]
+
+v_sub_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x04]
+
+v_sub_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x04]
+
+v_sub_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x04]
+
+v_sub_f32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x04]
+
+v_sub_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x04]
+
+v_sub_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x04]
+
+v_sub_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x04]
+
+v_sub_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x04]
+
+v_sub_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x04]
+
+v_sub_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x04]
+
+v_sub_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x04]
+
+v_sub_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x04]
+
+v_sub_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x04]
+
+v_sub_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x04]
+
+v_sub_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x04]
+
+v_sub_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x04,0x56,0x34,0x12,0xaf]
+
+v_sub_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x04,0x73,0x72,0x71,0x3f]
+
+v_sub_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x04]
+
+v_subrev_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x06]
+
+v_subrev_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x07]
+
+v_subrev_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x06]
+
+v_subrev_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x06]
+
+v_subrev_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x06,0x56,0x34,0x12,0xaf]
+
+v_subrev_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x06,0x73,0x72,0x71,0x3f]
+
+v_subrev_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x06]
+
+v_mul_legacy_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x08]
+
+v_mul_legacy_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x09]
+
+v_mul_legacy_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x08]
+
+v_mul_legacy_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x08]
+
+v_mul_legacy_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x08,0x56,0x34,0x12,0xaf]
+
+v_mul_legacy_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x08,0x73,0x72,0x71,0x3f]
+
+v_mul_legacy_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x08]
+
+v_mul_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x0a]
+
+v_mul_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x0b]
+
+v_mul_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x0a]
+
+v_mul_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x0a]
+
+v_mul_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x0a,0x56,0x34,0x12,0xaf]
+
+v_mul_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x0a,0x73,0x72,0x71,0x3f]
+
+v_mul_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x0a]
+
+v_mul_i32_i24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x0c]
+
+v_mul_i32_i24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x0d]
+
+v_mul_i32_i24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x0c]
+
+v_mul_i32_i24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x0c]
+
+v_mul_i32_i24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x0c,0x56,0x34,0x12,0xaf]
+
+v_mul_i32_i24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x0c,0x73,0x72,0x71,0x3f]
+
+v_mul_i32_i24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x0c]
+
+v_mul_hi_i32_i24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x0f]
+
+v_mul_hi_i32_i24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x0e]
+
+v_mul_hi_i32_i24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x0e,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_i32_i24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x0e,0x73,0x72,0x71,0x3f]
+
+v_mul_hi_i32_i24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x0e]
+
+v_mul_u32_u24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x10]
+
+v_mul_u32_u24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x11]
+
+v_mul_u32_u24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x10]
+
+v_mul_u32_u24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x10]
+
+v_mul_u32_u24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x10,0x56,0x34,0x12,0xaf]
+
+v_mul_u32_u24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x10,0x73,0x72,0x71,0x3f]
+
+v_mul_u32_u24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x10]
+
+v_mul_hi_u32_u24 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x12]
+
+v_mul_hi_u32_u24 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x13]
+
+v_mul_hi_u32_u24 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x12]
+
+v_mul_hi_u32_u24 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0xaf]
+
+v_mul_hi_u32_u24 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x3f]
+
+v_mul_hi_u32_u24 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x12]
+
+v_min_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x14]
+
+v_min_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x15]
+
+v_min_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x14]
+
+v_min_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x14]
+
+v_min_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x14]
+
+v_min_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x14]
+
+v_min_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x14]
+
+v_min_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x14]
+
+v_min_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x14]
+
+v_min_f32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x14]
+
+v_min_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x14]
+
+v_min_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x14]
+
+v_min_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x14]
+
+v_min_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x14]
+
+v_min_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x14]
+
+v_min_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x14]
+
+v_min_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x14]
+
+v_min_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x14]
+
+v_min_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x14]
+
+v_min_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x14]
+
+v_min_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x14]
+
+v_min_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x14,0x56,0x34,0x12,0xaf]
+
+v_min_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x14,0x73,0x72,0x71,0x3f]
+
+v_min_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x14]
+
+v_max_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x16]
+
+v_max_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x17]
+
+v_max_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x16]
+
+v_max_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x16]
+
+v_max_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x16]
+
+v_max_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x16]
+
+v_max_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x16]
+
+v_max_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x16]
+
+v_max_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x16]
+
+v_max_f32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x16]
+
+v_max_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x16]
+
+v_max_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x16]
+
+v_max_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x16]
+
+v_max_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x16]
+
+v_max_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x16]
+
+v_max_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x16]
+
+v_max_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x16]
+
+v_max_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x16]
+
+v_max_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x16]
+
+v_max_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x16]
+
+v_max_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x16]
+
+v_max_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x16,0x56,0x34,0x12,0xaf]
+
+v_max_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x16,0x73,0x72,0x71,0x3f]
+
+v_max_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x16]
+
+v_min_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x18]
+
+v_min_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x19]
+
+v_min_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x18]
+
+v_min_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x18]
+
+v_min_i32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x18]
+
+v_min_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x18]
+
+v_min_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x18]
+
+v_min_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x18]
+
+v_min_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x18]
+
+v_min_i32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x18]
+
+v_min_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x18]
+
+v_min_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x18]
+
+v_min_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x18]
+
+v_min_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x18]
+
+v_min_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x18]
+
+v_min_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x18]
+
+v_min_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x18]
+
+v_min_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x18]
+
+v_min_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x18]
+
+v_min_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x18]
+
+v_min_i32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x18]
+
+v_min_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x18,0x56,0x34,0x12,0xaf]
+
+v_min_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x18,0x73,0x72,0x71,0x3f]
+
+v_min_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x18]
+
+v_max_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x1a]
+
+v_max_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x1b]
+
+v_max_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x1a]
+
+v_max_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x1a]
+
+v_max_i32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x1a]
+
+v_max_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x1a]
+
+v_max_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x1a]
+
+v_max_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x1a]
+
+v_max_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x1a]
+
+v_max_i32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x1a]
+
+v_max_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x1a]
+
+v_max_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x1a]
+
+v_max_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x1a]
+
+v_max_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x1a]
+
+v_max_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x1a]
+
+v_max_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x1a]
+
+v_max_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x1a]
+
+v_max_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x1a]
+
+v_max_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x1a]
+
+v_max_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x1a]
+
+v_max_i32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x1a]
+
+v_max_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x1a,0x56,0x34,0x12,0xaf]
+
+v_max_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x1a,0x73,0x72,0x71,0x3f]
+
+v_max_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x1a]
+
+v_min_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x1c]
+
+v_min_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x1d]
+
+v_min_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x1c]
+
+v_min_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x1c]
+
+v_min_u32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x1c]
+
+v_min_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x1c]
+
+v_min_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x1c]
+
+v_min_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x1c]
+
+v_min_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x1c]
+
+v_min_u32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x1c]
+
+v_min_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x1c]
+
+v_min_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x1c]
+
+v_min_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x1c]
+
+v_min_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x1c]
+
+v_min_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x1c]
+
+v_min_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x1c]
+
+v_min_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x1c]
+
+v_min_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x1c]
+
+v_min_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x1c]
+
+v_min_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x1c]
+
+v_min_u32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x1c]
+
+v_min_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x1c,0x56,0x34,0x12,0xaf]
+
+v_min_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x1c,0x73,0x72,0x71,0x3f]
+
+v_min_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x1c]
+
+v_max_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x1e]
+
+v_max_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x1f]
+
+v_max_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x1e]
+
+v_max_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x1e]
+
+v_max_u32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x1e]
+
+v_max_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x1e]
+
+v_max_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x1e]
+
+v_max_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x1e]
+
+v_max_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x1e]
+
+v_max_u32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x1e]
+
+v_max_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x1e]
+
+v_max_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x1e]
+
+v_max_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x1e]
+
+v_max_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x1e]
+
+v_max_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x1e]
+
+v_max_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x1e]
+
+v_max_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x1e]
+
+v_max_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x1e]
+
+v_max_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x1e]
+
+v_max_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x1e]
+
+v_max_u32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x1e]
+
+v_max_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x1e,0x56,0x34,0x12,0xaf]
+
+v_max_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x1e,0x73,0x72,0x71,0x3f]
+
+v_max_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x1e]
+
+v_lshrrev_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x20]
+
+v_lshrrev_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x21]
+
+v_lshrrev_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x20]
+
+v_lshrrev_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x20]
+
+v_lshrrev_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x20,0x56,0x34,0x12,0xaf]
+
+v_lshrrev_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x20,0x73,0x72,0x71,0x3f]
+
+v_lshrrev_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x20]
+
+v_ashrrev_i32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x22]
+
+v_ashrrev_i32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x23]
+
+v_ashrrev_i32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x22]
+
+v_ashrrev_i32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x22]
+
+v_ashrrev_i32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x22,0x56,0x34,0x12,0xaf]
+
+v_ashrrev_i32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x22,0x73,0x72,0x71,0x3f]
+
+v_ashrrev_i32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x22]
+
+v_lshlrev_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x24]
+
+v_lshlrev_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x25]
+
+v_lshlrev_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x24]
+
+v_lshlrev_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x24]
+
+v_lshlrev_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x24,0x56,0x34,0x12,0xaf]
+
+v_lshlrev_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x24,0x73,0x72,0x71,0x3f]
+
+v_lshlrev_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x24]
+
+v_and_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x26]
+
+v_and_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x27]
+
+v_and_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x26]
+
+v_and_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x26]
+
+v_and_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x26]
+
+v_and_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x26]
+
+v_and_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x26]
+
+v_and_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x26]
+
+v_and_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x26]
+
+v_and_b32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x26]
+
+v_and_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x26]
+
+v_and_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x26]
+
+v_and_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x26]
+
+v_and_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x26]
+
+v_and_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x26]
+
+v_and_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x26]
+
+v_and_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x26]
+
+v_and_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x26]
+
+v_and_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x26]
+
+v_and_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x26]
+
+v_and_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x26]
+
+v_and_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x26,0x56,0x34,0x12,0xaf]
+
+v_and_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x26,0x73,0x72,0x71,0x3f]
+
+v_and_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x26]
+
+v_or_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x28]
+
+v_or_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x29]
+
+v_or_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x28]
+
+v_or_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x28]
+
+v_or_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x28]
+
+v_or_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x28]
+
+v_or_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x28]
+
+v_or_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x28]
+
+v_or_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x28]
+
+v_or_b32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x28]
+
+v_or_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x28]
+
+v_or_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x28]
+
+v_or_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x28]
+
+v_or_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x28]
+
+v_or_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x28]
+
+v_or_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x28]
+
+v_or_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x28]
+
+v_or_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x28]
+
+v_or_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x28]
+
+v_or_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x28]
+
+v_or_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x28]
+
+v_or_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x28,0x56,0x34,0x12,0xaf]
+
+v_or_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x28,0x73,0x72,0x71,0x3f]
+
+v_or_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x28]
+
+v_xor_b32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x2a]
+
+v_xor_b32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x2b]
+
+v_xor_b32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x2a]
+
+v_xor_b32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x2a]
+
+v_xor_b32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x2a,0x56,0x34,0x12,0xaf]
+
+v_xor_b32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x2a,0x73,0x72,0x71,0x3f]
+
+v_xor_b32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x2a]
+
+v_mac_f32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x2c]
+
+v_mac_f32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x2d]
+
+v_mac_f32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x2c]
+
+v_mac_f32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x2c]
+
+v_mac_f32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x2c,0x56,0x34,0x12,0xaf]
+
+v_mac_f32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x2c,0x73,0x72,0x71,0x3f]
+
+v_mac_f32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x2c]
+
+v_madmk_f32 v5, v1, 0x11213141, v3
+// CHECK: [0x01,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v255, v1, 0x11213141, v3
+// CHECK: [0x01,0x07,0xfe,0x2f,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, v255, 0x11213141, v3
+// CHECK: [0xff,0x07,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, 0, 0x11213141, v3
+// CHECK: [0x80,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, -1, 0x11213141, v3
+// CHECK: [0xc1,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, 0.5, 0x11213141, v3
+// CHECK: [0xf0,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, -4.0, 0x11213141, v3
+// CHECK: [0xf7,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, src_lds_direct, 0x11213141, v3
+// CHECK: [0xfe,0x06,0x0a,0x2e,0x41,0x31,0x21,0x11]
+
+v_madmk_f32 v5, v1, 0xa1b1c1d1, v3
+// CHECK: [0x01,0x07,0x0a,0x2e,0xd1,0xc1,0xb1,0xa1]
+
+v_madmk_f32 v5, v1, 0x11213141, v255
+// CHECK: [0x01,0xff,0x0b,0x2e,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v2, 0x11213141
+// CHECK: [0x01,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v255, v1, v2, 0x11213141
+// CHECK: [0x01,0x05,0xfe,0x31,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v255, v2, 0x11213141
+// CHECK: [0xff,0x05,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, 0, v2, 0x11213141
+// CHECK: [0x80,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, -1, v2, 0x11213141
+// CHECK: [0xc1,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, 0.5, v2, 0x11213141
+// CHECK: [0xf0,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, -4.0, v2, 0x11213141
+// CHECK: [0xf7,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, src_lds_direct, v2, 0x11213141
+// CHECK: [0xfe,0x04,0x0a,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v255, 0x11213141
+// CHECK: [0x01,0xff,0x0b,0x30,0x41,0x31,0x21,0x11]
+
+v_madak_f32 v5, v1, v2, 0xa1b1c1d1
+// CHECK: [0x01,0x05,0x0a,0x30,0xd1,0xc1,0xb1,0xa1]
+
+v_add_co_u32 v5, vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x32]
+
+v_add_co_u32 v255, vcc, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x33]
+
+v_add_co_u32 v5, vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x32]
+
+v_add_co_u32 v5, vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x32,0x56,0x34,0x12,0xaf]
+
+v_add_co_u32 v5, vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x32,0x73,0x72,0x71,0x3f]
+
+v_add_co_u32 v5, vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x32]
+
+v_sub_co_u32 v5, vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x34]
+
+v_sub_co_u32 v255, vcc, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x35]
+
+v_sub_co_u32 v5, vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x34]
+
+v_sub_co_u32 v5, vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x34,0x56,0x34,0x12,0xaf]
+
+v_sub_co_u32 v5, vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x34,0x73,0x72,0x71,0x3f]
+
+v_sub_co_u32 v5, vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x34]
+
+v_subrev_co_u32 v5, vcc, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x36]
+
+v_subrev_co_u32 v255, vcc, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x37]
+
+v_subrev_co_u32 v5, vcc, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x36]
+
+v_subrev_co_u32 v5, vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x36,0x56,0x34,0x12,0xaf]
+
+v_subrev_co_u32 v5, vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x36,0x73,0x72,0x71,0x3f]
+
+v_subrev_co_u32 v5, vcc, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x36]
+
+v_addc_co_u32 v5, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x38]
+
+v_addc_co_u32 v255, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x39]
+
+v_addc_co_u32 v5, vcc, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x38]
+
+v_addc_co_u32 v5, vcc, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x38]
+
+v_addc_co_u32 v5, vcc, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x38]
+
+v_addc_co_u32 v5, vcc, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x38]
+
+v_addc_co_u32 v5, vcc, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x38]
+
+v_addc_co_u32 v5, vcc, src_lds_direct, v2, vcc
+// CHECK: [0xfe,0x04,0x0a,0x38]
+
+v_addc_co_u32 v5, vcc, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x38]
+
+v_subb_co_u32 v5, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x3a]
+
+v_subb_co_u32 v255, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x3b]
+
+v_subb_co_u32 v5, vcc, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x3a]
+
+v_subb_co_u32 v5, vcc, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x3a]
+
+v_subb_co_u32 v5, vcc, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x3a]
+
+v_subb_co_u32 v5, vcc, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x3a]
+
+v_subb_co_u32 v5, vcc, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x3a]
+
+v_subb_co_u32 v5, vcc, src_lds_direct, v2, vcc
+// CHECK: [0xfe,0x04,0x0a,0x3a]
+
+v_subb_co_u32 v5, vcc, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x3a]
+
+v_subbrev_co_u32 v5, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0x0a,0x3c]
+
+v_subbrev_co_u32 v255, vcc, v1, v2, vcc
+// CHECK: [0x01,0x05,0xfe,0x3d]
+
+v_subbrev_co_u32 v5, vcc, v255, v2, vcc
+// CHECK: [0xff,0x05,0x0a,0x3c]
+
+v_subbrev_co_u32 v5, vcc, 0, v2, vcc
+// CHECK: [0x80,0x04,0x0a,0x3c]
+
+v_subbrev_co_u32 v5, vcc, -1, v2, vcc
+// CHECK: [0xc1,0x04,0x0a,0x3c]
+
+v_subbrev_co_u32 v5, vcc, 0.5, v2, vcc
+// CHECK: [0xf0,0x04,0x0a,0x3c]
+
+v_subbrev_co_u32 v5, vcc, -4.0, v2, vcc
+// CHECK: [0xf7,0x04,0x0a,0x3c]
+
+v_subbrev_co_u32 v5, vcc, v1, v255, vcc
+// CHECK: [0x01,0xff,0x0b,0x3c]
+
+v_add_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x3e]
+
+v_add_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x3f]
+
+v_add_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x3e]
+
+v_add_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x3e]
+
+v_add_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x3e]
+
+v_add_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x3e]
+
+v_add_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x3e]
+
+v_add_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x3e]
+
+v_add_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x3e]
+
+v_add_f16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x3e]
+
+v_add_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x3e]
+
+v_add_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x3e]
+
+v_add_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x3e]
+
+v_add_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x3e]
+
+v_add_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x3e]
+
+v_add_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x3e]
+
+v_add_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x3e]
+
+v_add_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x3e]
+
+v_add_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x3e]
+
+v_add_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x3e]
+
+v_add_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x3e]
+
+v_add_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x3e,0x0b,0xfe,0x00,0x00]
+
+v_add_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x3e,0x56,0x34,0x00,0x00]
+
+v_add_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x3e]
+
+v_sub_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x40]
+
+v_sub_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x41]
+
+v_sub_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x40]
+
+v_sub_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x40]
+
+v_sub_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x40]
+
+v_sub_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x40]
+
+v_sub_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x40]
+
+v_sub_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x40]
+
+v_sub_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x40]
+
+v_sub_f16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x40]
+
+v_sub_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x40]
+
+v_sub_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x40]
+
+v_sub_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x40]
+
+v_sub_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x40]
+
+v_sub_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x40]
+
+v_sub_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x40]
+
+v_sub_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x40]
+
+v_sub_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x40]
+
+v_sub_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x40]
+
+v_sub_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x40]
+
+v_sub_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x40]
+
+v_sub_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x40,0x0b,0xfe,0x00,0x00]
+
+v_sub_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x40,0x56,0x34,0x00,0x00]
+
+v_sub_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x40]
+
+v_subrev_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x42]
+
+v_subrev_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x43]
+
+v_subrev_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x42]
+
+v_subrev_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x42]
+
+v_subrev_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x42,0x0b,0xfe,0x00,0x00]
+
+v_subrev_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x42,0x56,0x34,0x00,0x00]
+
+v_subrev_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x42]
+
+v_mul_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x44]
+
+v_mul_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x45]
+
+v_mul_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x44]
+
+v_mul_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x44]
+
+v_mul_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x44]
+
+v_mul_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x44]
+
+v_mul_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x44]
+
+v_mul_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x44]
+
+v_mul_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x44]
+
+v_mul_f16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x44]
+
+v_mul_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x44]
+
+v_mul_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x44]
+
+v_mul_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x44]
+
+v_mul_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x44]
+
+v_mul_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x44]
+
+v_mul_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x44]
+
+v_mul_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x44]
+
+v_mul_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x44]
+
+v_mul_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x44]
+
+v_mul_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x44]
+
+v_mul_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x44]
+
+v_mul_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x44,0x0b,0xfe,0x00,0x00]
+
+v_mul_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x44,0x56,0x34,0x00,0x00]
+
+v_mul_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x44]
+
+v_mac_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x46]
+
+v_mac_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x47]
+
+v_mac_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x46]
+
+v_mac_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x46]
+
+v_mac_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x46]
+
+v_mac_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x46]
+
+v_mac_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x46]
+
+v_mac_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x46]
+
+v_mac_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x46]
+
+v_mac_f16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x46]
+
+v_mac_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x46]
+
+v_mac_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x46]
+
+v_mac_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x46]
+
+v_mac_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x46]
+
+v_mac_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x46]
+
+v_mac_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x46]
+
+v_mac_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x46]
+
+v_mac_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x46]
+
+v_mac_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x46]
+
+v_mac_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x46]
+
+v_mac_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x46]
+
+v_mac_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x46,0x0b,0xfe,0x00,0x00]
+
+v_mac_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x46,0x56,0x34,0x00,0x00]
+
+v_mac_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x46]
+
+v_madmk_f16 v5, v1, 0x1121, v3
+// CHECK: [0x01,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v255, v1, 0x1121, v3
+// CHECK: [0x01,0x07,0xfe,0x49,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, v255, 0x1121, v3
+// CHECK: [0xff,0x07,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, 0, 0x1121, v3
+// CHECK: [0x80,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, -1, 0x1121, v3
+// CHECK: [0xc1,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, 0.5, 0x1121, v3
+// CHECK: [0xf0,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, -4.0, 0x1121, v3
+// CHECK: [0xf7,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, src_lds_direct, 0x1121, v3
+// CHECK: [0xfe,0x06,0x0a,0x48,0x21,0x11,0x00,0x00]
+
+v_madmk_f16 v5, v1, 0xa1b1, v3
+// CHECK: [0x01,0x07,0x0a,0x48,0xb1,0xa1,0x00,0x00]
+
+v_madmk_f16 v5, v1, 0x1121, v255
+// CHECK: [0x01,0xff,0x0b,0x48,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, v1, v2, 0x1121
+// CHECK: [0x01,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v255, v1, v2, 0x1121
+// CHECK: [0x01,0x05,0xfe,0x4b,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, v255, v2, 0x1121
+// CHECK: [0xff,0x05,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, 0, v2, 0x1121
+// CHECK: [0x80,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, -1, v2, 0x1121
+// CHECK: [0xc1,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, 0.5, v2, 0x1121
+// CHECK: [0xf0,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, -4.0, v2, 0x1121
+// CHECK: [0xf7,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, src_lds_direct, v2, 0x1121
+// CHECK: [0xfe,0x04,0x0a,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, v1, v255, 0x1121
+// CHECK: [0x01,0xff,0x0b,0x4a,0x21,0x11,0x00,0x00]
+
+v_madak_f16 v5, v1, v2, 0xa1b1
+// CHECK: [0x01,0x05,0x0a,0x4a,0xb1,0xa1,0x00,0x00]
+
+v_add_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x4c]
+
+v_add_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x4d]
+
+v_add_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x4c]
+
+v_add_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x4c]
+
+v_add_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x4c]
+
+v_add_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x4c]
+
+v_add_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x4c]
+
+v_add_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x4c]
+
+v_add_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x4c]
+
+v_add_u16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x4c]
+
+v_add_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x4c]
+
+v_add_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x4c]
+
+v_add_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x4c]
+
+v_add_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x4c]
+
+v_add_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x4c]
+
+v_add_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x00,0x38,0x00,0x00]
+
+v_add_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x00,0xc4,0x00,0x00]
+
+v_add_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x4c]
+
+v_add_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x4c]
+
+v_add_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x4c]
+
+v_add_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x4c]
+
+v_add_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x0b,0xfe,0x00,0x00]
+
+v_add_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x4c,0x56,0x34,0x00,0x00]
+
+v_add_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x4c]
+
+v_sub_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x4e]
+
+v_sub_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x4f]
+
+v_sub_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x4e]
+
+v_sub_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x00,0x38,0x00,0x00]
+
+v_sub_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x00,0xc4,0x00,0x00]
+
+v_sub_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x4e]
+
+v_sub_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x0b,0xfe,0x00,0x00]
+
+v_sub_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x4e,0x56,0x34,0x00,0x00]
+
+v_sub_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x4e]
+
+v_subrev_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x50]
+
+v_subrev_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x51]
+
+v_subrev_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x50]
+
+v_subrev_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x50,0x00,0x38,0x00,0x00]
+
+v_subrev_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x50,0x00,0xc4,0x00,0x00]
+
+v_subrev_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x50]
+
+v_subrev_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x50,0x0b,0xfe,0x00,0x00]
+
+v_subrev_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x50,0x56,0x34,0x00,0x00]
+
+v_subrev_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x50]
+
+v_mul_lo_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x52]
+
+v_mul_lo_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x53]
+
+v_mul_lo_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x52]
+
+v_mul_lo_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x52,0x00,0x38,0x00,0x00]
+
+v_mul_lo_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x52,0x00,0xc4,0x00,0x00]
+
+v_mul_lo_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x52]
+
+v_mul_lo_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x52,0x0b,0xfe,0x00,0x00]
+
+v_mul_lo_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x52,0x56,0x34,0x00,0x00]
+
+v_mul_lo_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x52]
+
+v_lshlrev_b16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x54]
+
+v_lshlrev_b16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x55]
+
+v_lshlrev_b16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x54]
+
+v_lshlrev_b16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x54,0x00,0x38,0x00,0x00]
+
+v_lshlrev_b16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x54,0x00,0xc4,0x00,0x00]
+
+v_lshlrev_b16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x54]
+
+v_lshlrev_b16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x54,0x0b,0xfe,0x00,0x00]
+
+v_lshlrev_b16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x54,0x56,0x34,0x00,0x00]
+
+v_lshlrev_b16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x54]
+
+v_lshrrev_b16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x56]
+
+v_lshrrev_b16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x57]
+
+v_lshrrev_b16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x56]
+
+v_lshrrev_b16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x00,0x38,0x00,0x00]
+
+v_lshrrev_b16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x00,0xc4,0x00,0x00]
+
+v_lshrrev_b16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x56]
+
+v_lshrrev_b16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x0b,0xfe,0x00,0x00]
+
+v_lshrrev_b16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x56,0x56,0x34,0x00,0x00]
+
+v_lshrrev_b16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x56]
+
+v_ashrrev_i16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x58]
+
+v_ashrrev_i16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x59]
+
+v_ashrrev_i16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x58]
+
+v_ashrrev_i16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x00,0x38,0x00,0x00]
+
+v_ashrrev_i16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x00,0xc4,0x00,0x00]
+
+v_ashrrev_i16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x58]
+
+v_ashrrev_i16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x0b,0xfe,0x00,0x00]
+
+v_ashrrev_i16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x58,0x56,0x34,0x00,0x00]
+
+v_ashrrev_i16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x58]
+
+v_max_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x5a]
+
+v_max_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x5b]
+
+v_max_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x5a]
+
+v_max_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x5a]
+
+v_max_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x5a]
+
+v_max_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x5a]
+
+v_max_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x5a]
+
+v_max_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x5a]
+
+v_max_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x5a]
+
+v_max_f16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x5a]
+
+v_max_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x5a]
+
+v_max_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x5a]
+
+v_max_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x5a]
+
+v_max_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x5a]
+
+v_max_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x5a]
+
+v_max_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x5a]
+
+v_max_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x5a]
+
+v_max_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x5a]
+
+v_max_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x5a]
+
+v_max_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x5a]
+
+v_max_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x5a]
+
+v_max_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x5a,0x0b,0xfe,0x00,0x00]
+
+v_max_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x5a,0x56,0x34,0x00,0x00]
+
+v_max_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x5a]
+
+v_min_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x5c]
+
+v_min_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x5d]
+
+v_min_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x5c]
+
+v_min_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x5c]
+
+v_min_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x5c]
+
+v_min_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x5c]
+
+v_min_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x5c]
+
+v_min_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x5c]
+
+v_min_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x5c]
+
+v_min_f16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x5c]
+
+v_min_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x5c]
+
+v_min_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x5c]
+
+v_min_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x5c]
+
+v_min_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x5c]
+
+v_min_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x5c]
+
+v_min_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x5c]
+
+v_min_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x5c]
+
+v_min_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x5c]
+
+v_min_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x5c]
+
+v_min_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x5c]
+
+v_min_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x5c]
+
+v_min_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x5c,0x0b,0xfe,0x00,0x00]
+
+v_min_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x5c,0x56,0x34,0x00,0x00]
+
+v_min_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x5c]
+
+v_max_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x5e]
+
+v_max_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x5f]
+
+v_max_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x5e]
+
+v_max_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x5e]
+
+v_max_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x5e]
+
+v_max_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x5e]
+
+v_max_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x5e]
+
+v_max_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x5e]
+
+v_max_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x5e]
+
+v_max_u16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x5e]
+
+v_max_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x5e]
+
+v_max_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x5e]
+
+v_max_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x5e]
+
+v_max_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x5e]
+
+v_max_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x5e]
+
+v_max_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x00,0x38,0x00,0x00]
+
+v_max_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x00,0xc4,0x00,0x00]
+
+v_max_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x5e]
+
+v_max_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x5e]
+
+v_max_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x5e]
+
+v_max_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x5e]
+
+v_max_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x0b,0xfe,0x00,0x00]
+
+v_max_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x5e,0x56,0x34,0x00,0x00]
+
+v_max_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x5e]
+
+v_max_i16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x60]
+
+v_max_i16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x61]
+
+v_max_i16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x60]
+
+v_max_i16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x60]
+
+v_max_i16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x60]
+
+v_max_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x60]
+
+v_max_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x60]
+
+v_max_i16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x60]
+
+v_max_i16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x60]
+
+v_max_i16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x60]
+
+v_max_i16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x60]
+
+v_max_i16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x60]
+
+v_max_i16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x60]
+
+v_max_i16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x60]
+
+v_max_i16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x60]
+
+v_max_i16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x00,0x38,0x00,0x00]
+
+v_max_i16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x00,0xc4,0x00,0x00]
+
+v_max_i16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x60]
+
+v_max_i16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x60]
+
+v_max_i16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x60]
+
+v_max_i16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x60]
+
+v_max_i16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x0b,0xfe,0x00,0x00]
+
+v_max_i16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x60,0x56,0x34,0x00,0x00]
+
+v_max_i16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x60]
+
+v_min_u16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x62]
+
+v_min_u16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x63]
+
+v_min_u16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x62]
+
+v_min_u16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x62]
+
+v_min_u16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x62]
+
+v_min_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x62]
+
+v_min_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x62]
+
+v_min_u16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x62]
+
+v_min_u16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x62]
+
+v_min_u16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x62]
+
+v_min_u16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x62]
+
+v_min_u16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x62]
+
+v_min_u16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x62]
+
+v_min_u16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x62]
+
+v_min_u16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x62]
+
+v_min_u16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x00,0x38,0x00,0x00]
+
+v_min_u16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x00,0xc4,0x00,0x00]
+
+v_min_u16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x62]
+
+v_min_u16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x62]
+
+v_min_u16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x62]
+
+v_min_u16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x62]
+
+v_min_u16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x0b,0xfe,0x00,0x00]
+
+v_min_u16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x62,0x56,0x34,0x00,0x00]
+
+v_min_u16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x62]
+
+v_min_i16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x64]
+
+v_min_i16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x65]
+
+v_min_i16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x64]
+
+v_min_i16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x64]
+
+v_min_i16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x64]
+
+v_min_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x64]
+
+v_min_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x64]
+
+v_min_i16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x64]
+
+v_min_i16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x64]
+
+v_min_i16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x64]
+
+v_min_i16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x64]
+
+v_min_i16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x64]
+
+v_min_i16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x64]
+
+v_min_i16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x64]
+
+v_min_i16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x64]
+
+v_min_i16 v5, 0.5, v2
+// CHECK: [0xff,0x04,0x0a,0x64,0x00,0x38,0x00,0x00]
+
+v_min_i16 v5, -4.0, v2
+// CHECK: [0xff,0x04,0x0a,0x64,0x00,0xc4,0x00,0x00]
+
+v_min_i16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x64]
+
+v_min_i16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x64]
+
+v_min_i16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x64]
+
+v_min_i16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x64]
+
+v_min_i16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x64,0x0b,0xfe,0x00,0x00]
+
+v_min_i16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x64,0x56,0x34,0x00,0x00]
+
+v_min_i16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x64]
+
+v_ldexp_f16 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x66]
+
+v_ldexp_f16 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x67]
+
+v_ldexp_f16 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x66]
+
+v_ldexp_f16 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x66]
+
+v_ldexp_f16 v5, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x0a,0x66,0x0b,0xfe,0x00,0x00]
+
+v_ldexp_f16 v5, 0x3456, v2
+// CHECK: [0xff,0x04,0x0a,0x66,0x56,0x34,0x00,0x00]
+
+v_ldexp_f16 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x66]
+
+v_add_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x68]
+
+v_add_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x69]
+
+v_add_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x68]
+
+v_add_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x68]
+
+v_add_u32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x68]
+
+v_add_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x68]
+
+v_add_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x68]
+
+v_add_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x68]
+
+v_add_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x68]
+
+v_add_u32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x68]
+
+v_add_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x68]
+
+v_add_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x68]
+
+v_add_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x68]
+
+v_add_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x68]
+
+v_add_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x68]
+
+v_add_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x68]
+
+v_add_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x68]
+
+v_add_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x68]
+
+v_add_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x68]
+
+v_add_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x68]
+
+v_add_u32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x68]
+
+v_add_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x68,0x56,0x34,0x12,0xaf]
+
+v_add_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x68,0x73,0x72,0x71,0x3f]
+
+v_add_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x68]
+
+v_sub_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x6a]
+
+v_sub_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x6b]
+
+v_sub_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x6a]
+
+v_sub_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x0a,0x6a]
+
+v_sub_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x6a,0x56,0x34,0x12,0xaf]
+
+v_sub_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x6a,0x73,0x72,0x71,0x3f]
+
+v_sub_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x6a]
+
+v_subrev_u32 v5, v1, v2
+// CHECK: [0x01,0x05,0x0a,0x6c]
+
+v_subrev_u32 v255, v1, v2
+// CHECK: [0x01,0x05,0xfe,0x6d]
+
+v_subrev_u32 v5, v255, v2
+// CHECK: [0xff,0x05,0x0a,0x6c]
+
+v_subrev_u32 v5, s1, v2
+// CHECK: [0x01,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, s101, v2
+// CHECK: [0x65,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, ttmp15, v2
+// CHECK: [0x7b,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, m0, v2
+// CHECK: [0x7c,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, exec_lo, v2
+// CHECK: [0x7e,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, exec_hi, v2
+// CHECK: [0x7f,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, 0, v2
+// CHECK: [0x80,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, -1, v2
+// CHECK: [0xc1,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, 0.5, v2
+// CHECK: [0xf0,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, -4.0, v2
+// CHECK: [0xf7,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, src_vccz, v2
+// CHECK: [0xfb,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, src_execz, v2
+// CHECK: [0xfc,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, src_scc, v2
+// CHECK: [0xfd,0x04,0x0a,0x6c]
+
+v_subrev_u32 v5, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x0a,0x6c,0x56,0x34,0x12,0xaf]
+
+v_subrev_u32 v5, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x0a,0x6c,0x73,0x72,0x71,0x3f]
+
+v_subrev_u32 v5, v1, v255
+// CHECK: [0x01,0xff,0x0b,0x6c]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v255, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x01,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0xff,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, 0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x80,0x06,0x86,0x06]
+
+v_cndmask_b32_sdwa v5, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0xc1,0x06,0x86,0x06]
+
+v_cndmask_b32_sdwa v5, 0.5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0xf0,0x06,0x86,0x06]
+
+v_cndmask_b32_sdwa v5, -4.0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0xf7,0x06,0x86,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x00,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x01,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x02,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x03,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x04,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x05,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x0e,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x16,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x16,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x00,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x01,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x02,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x03,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x04,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x05,0x06]
+
+v_cndmask_b32_sdwa v5, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x0e,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x06]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x00]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x01]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x02]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x03]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x04]
+
+v_cndmask_b32_sdwa v5, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x05]
+
+v_cndmask_b32_sdwa v5, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x00,0x01,0x06,0x06,0x0e]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x00]
+
+v_cndmask_b32_dpp v255, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x01,0x01,0xe4,0x00,0x00]
+
+v_cndmask_b32_dpp v5, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0xff,0xe4,0x00,0x00]
+
+v_cndmask_b32_dpp v5, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x00,0x01,0xe4,0x00,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x1b,0x00,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x40,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x41,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x42,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x43,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x30,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x34,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x38,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x3c,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x01,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x0f,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x11,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x1f,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x21,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0x2f,0x01,0x00]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x10]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x30]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0xf0]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0xf0]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x01]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x03]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x00,0x0f]
+
+v_cndmask_b32_dpp v5, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x00,0x01,0xe4,0x08,0x00]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x03,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0xff,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x65,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x66,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x67,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x6a,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x6b,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x7b,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x7c,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x7e,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x7f,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x80,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0xc1,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0xf0,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0xf7,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0xfb,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0xfc,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0xfd,0x06,0x86,0x06]
+
+v_add_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x26,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x46,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x86,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0xc6,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x00,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x01,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x02,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x03,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x04,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x05,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x0e,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x00,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x01,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x02,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x03,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x04,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x05,0x06]
+
+v_add_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x16,0x06]
+
+v_add_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x26,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x06]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x00]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x01]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x02]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x03]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x04]
+
+v_add_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x05]
+
+v_add_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x16]
+
+v_add_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x02,0x01,0x06,0x06,0x26]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00]
+
+v_add_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x03,0x01,0xe4,0x00,0x00]
+
+v_add_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0xff,0xe4,0x00,0x00]
+
+v_add_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x02,0x01,0xe4,0x00,0x00]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1b,0x00,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x40,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x41,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x42,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x43,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x30,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x34,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x38,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x3c,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x01,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x0f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x11,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x1f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x21,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0x2f,0x01,0x00]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x10]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x30]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0xf0]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x01]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x03]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x0f]
+
+v_add_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x08,0x00]
+
+v_add_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x10,0x00]
+
+v_add_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x20,0x00]
+
+v_add_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x40,0x00]
+
+v_add_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x02,0x01,0xe4,0x80,0x00]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x05,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0xff,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x65,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x66,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x67,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x6a,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x6b,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x7b,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x7c,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x7e,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x7f,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x80,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0xc1,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0xf0,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0xf7,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0xfb,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0xfc,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0xfd,0x06,0x86,0x06]
+
+v_sub_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x26,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x46,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x86,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0xc6,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x00,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x01,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x02,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x03,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x04,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x05,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x0e,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x16,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x00,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x01,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x02,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x03,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x04,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x05,0x06]
+
+v_sub_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x16,0x06]
+
+v_sub_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x26,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x06]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x00]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x01]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x02]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x03]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x04]
+
+v_sub_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x05]
+
+v_sub_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x16]
+
+v_sub_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x04,0x01,0x06,0x06,0x26]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x05,0x01,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0xff,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x04,0x01,0xe4,0x00,0x00]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1b,0x00,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x40,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x41,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x42,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x43,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x30,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x34,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x38,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x3c,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x01,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x0f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x11,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x1f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x21,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0x2f,0x01,0x00]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x10]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x30]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0xf0]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x01]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x03]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x00,0x0f]
+
+v_sub_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x08,0x00]
+
+v_sub_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x10,0x00]
+
+v_sub_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x20,0x00]
+
+v_sub_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x40,0x00]
+
+v_sub_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x04,0x01,0xe4,0x80,0x00]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x07,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0xff,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x65,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x66,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x67,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x6a,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x6b,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x7b,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x7c,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x7e,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x7f,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x80,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0xc1,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0xf0,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0xf7,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0xfb,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0xfc,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0xfd,0x06,0x86,0x06]
+
+v_subrev_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x26,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x46,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x86,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0xc6,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x00,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x01,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x02,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x03,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x04,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x05,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x0e,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x16,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x00,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x01,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x02,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x03,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x04,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x05,0x06]
+
+v_subrev_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x16,0x06]
+
+v_subrev_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x26,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x06]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x00]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x01]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x02]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x03]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x04]
+
+v_subrev_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x05]
+
+v_subrev_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x16]
+
+v_subrev_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x06,0x01,0x06,0x06,0x26]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x07,0x01,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0xff,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x06,0x01,0xe4,0x00,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x40,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x41,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x42,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x43,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x30,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x34,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x38,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x3c,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x01,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x0f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x11,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x1f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x21,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0x2f,0x01,0x00]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x10]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x30]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x01]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x03]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x08,0x00]
+
+v_subrev_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x10,0x00]
+
+v_subrev_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x20,0x00]
+
+v_subrev_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x40,0x00]
+
+v_subrev_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x06,0x01,0xe4,0x80,0x00]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x09,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0xff,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x65,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x66,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x67,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x6a,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x6b,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x7b,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x7c,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x7e,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x7f,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x80,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0xc1,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0xf0,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0xf7,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0xfb,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0xfc,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0xfd,0x06,0x86,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x26,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x46,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x86,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0xc6,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x00,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x01,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x02,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x03,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x04,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x05,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x0e,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x16,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x00,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x01,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x02,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x03,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x04,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x05,0x06]
+
+v_mul_legacy_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x16,0x06]
+
+v_mul_legacy_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x26,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x06]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x00]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x01]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x02]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x03]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x04]
+
+v_mul_legacy_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x05]
+
+v_mul_legacy_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x16]
+
+v_mul_legacy_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x08,0x01,0x06,0x06,0x26]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x09,0x01,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0xff,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x08,0x01,0xe4,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x40,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x41,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x42,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x43,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x30,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x34,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x38,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x3c,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x01,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x0f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x11,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x1f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x21,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0x2f,0x01,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x10]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x30]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0xf0]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x01]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x03]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x00,0x0f]
+
+v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x08,0x00]
+
+v_mul_legacy_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x10,0x00]
+
+v_mul_legacy_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x20,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x40,0x00]
+
+v_mul_legacy_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x08,0x01,0xe4,0x80,0x00]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x0b,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0xff,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x65,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x66,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x67,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x6a,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x6b,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x7b,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x7c,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x7e,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x7f,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x80,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0xc1,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0xf0,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0xf7,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0xfb,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0xfc,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0xfd,0x06,0x86,0x06]
+
+v_mul_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x26,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x46,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x86,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0xc6,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x00,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x01,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x02,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x03,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x04,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x05,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x0e,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x16,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x00,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x01,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x02,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x03,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x04,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x05,0x06]
+
+v_mul_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x16,0x06]
+
+v_mul_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x26,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x06]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x00]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x01]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x02]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x03]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x04]
+
+v_mul_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x05]
+
+v_mul_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x16]
+
+v_mul_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0a,0x01,0x06,0x06,0x26]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x0b,0x01,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0xff,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x0a,0x01,0xe4,0x00,0x00]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x40,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x41,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x42,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x43,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x30,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x34,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x38,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x3c,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x01,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x0f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x11,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x1f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x21,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0x2f,0x01,0x00]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x10]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x30]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0xf0]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x01]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x03]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x00,0x0f]
+
+v_mul_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x08,0x00]
+
+v_mul_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x10,0x00]
+
+v_mul_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x20,0x00]
+
+v_mul_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x40,0x00]
+
+v_mul_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0a,0x01,0xe4,0x80,0x00]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x0d,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0xff,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x65,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x66,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x67,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x6a,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x6b,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x7b,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x7c,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x7e,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x7f,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x80,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0xc1,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0xf0,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0xf7,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0xfb,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0xfc,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0xfd,0x06,0x86,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x26,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x00,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x01,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x02,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x03,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x04,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x05,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x0e,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x16,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x00,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x01,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x02,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x03,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x04,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x05,0x06]
+
+v_mul_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x0e,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x06]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x00]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x01]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x02]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x03]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x04]
+
+v_mul_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x05]
+
+v_mul_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0c,0x01,0x06,0x06,0x0e]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x0d,0x01,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0xff,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x0c,0x01,0xe4,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1b,0x00,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x40,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x41,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x42,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x43,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x30,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x34,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x38,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x3c,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x01,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x0f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x11,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x1f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x21,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0x2f,0x01,0x00]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x10]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x30]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0xf0]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x01]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x03]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x00,0x0f]
+
+v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x0c,0x01,0xe4,0x08,0x00]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x0f,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0xff,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x65,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x66,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x67,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x6a,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x6b,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x7b,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x7c,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x7e,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x7f,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x80,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0xc1,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0xf0,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0xf7,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0xfb,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0xfc,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0xfd,0x06,0x86,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x00,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x01,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x02,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x03,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x04,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x05,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x0e,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x16,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x00,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x01,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x02,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x03,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x04,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x05,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x0e,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x06]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x00]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x01]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x02]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x03]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x04]
+
+v_mul_hi_i32_i24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x05]
+
+v_mul_hi_i32_i24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x06,0x0e]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x0f,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0xff,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x0e,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x40,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x41,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x42,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x43,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x30,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x34,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x38,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x3c,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x0f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x11,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x1f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x21,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0x2f,0x01,0x00]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x10]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x30]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x01]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x03]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x0e,0x01,0xe4,0x08,0x00]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x11,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0xff,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x65,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x66,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x67,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x6a,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x6b,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x7b,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x7c,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x7e,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x7f,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x80,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0xc1,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0xf0,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0xf7,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0xfb,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0xfc,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0xfd,0x06,0x86,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x26,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x00,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x01,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x02,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x03,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x04,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x05,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x0e,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x16,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x00,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x01,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x02,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x03,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x04,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x05,0x06]
+
+v_mul_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x0e,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x06]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x00]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x01]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x02]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x03]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x04]
+
+v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x05]
+
+v_mul_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x10,0x01,0x06,0x06,0x0e]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x11,0x01,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0xff,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x10,0x01,0xe4,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x40,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x41,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x42,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x43,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x30,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x34,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x38,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x3c,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x01,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x0f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x11,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x1f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x21,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0x2f,0x01,0x00]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x10]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x30]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0xf0]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x01]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x03]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x00,0x0f]
+
+v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x10,0x01,0xe4,0x08,0x00]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x13,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0xff,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x65,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x66,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x67,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x6a,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x6b,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x7b,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x7c,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x7e,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x7f,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x80,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0xc1,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0xf0,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0xf7,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0xfb,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0xfc,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0xfd,0x06,0x86,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x00,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x01,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x02,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x03,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x04,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x05,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x0e,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x16,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x00,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x01,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x02,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x03,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x04,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x05,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x0e,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x06]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x00]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x01]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x02]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x03]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x04]
+
+v_mul_hi_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x05]
+
+v_mul_hi_u32_u24_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x12,0x01,0x06,0x06,0x0e]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x13,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0xff,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x12,0x01,0xe4,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x40,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x41,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x42,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x43,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x30,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x34,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x38,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x3c,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x0f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x11,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x1f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x21,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0x2f,0x01,0x00]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x10]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x30]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0xf0]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x01]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x03]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x00,0x0f]
+
+v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x12,0x01,0xe4,0x08,0x00]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x15,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0xff,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x65,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x66,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x67,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x6a,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x6b,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x7b,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x7c,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x7e,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x7f,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x80,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0xc1,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0xf0,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0xf7,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0xfb,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0xfc,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0xfd,0x06,0x86,0x06]
+
+v_min_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x26,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x46,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x86,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0xc6,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x00,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x01,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x02,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x03,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x04,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x05,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x0e,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x16,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x00,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x01,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x02,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x03,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x04,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x05,0x06]
+
+v_min_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x16,0x06]
+
+v_min_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x26,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x06]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x00]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x01]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x02]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x03]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x04]
+
+v_min_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x05]
+
+v_min_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x16]
+
+v_min_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x14,0x01,0x06,0x06,0x26]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x00]
+
+v_min_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x15,0x01,0xe4,0x00,0x00]
+
+v_min_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0xff,0xe4,0x00,0x00]
+
+v_min_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x14,0x01,0xe4,0x00,0x00]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x40,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x41,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x42,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x43,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x30,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x34,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x38,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x3c,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x01,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x0f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x11,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x1f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x21,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0x2f,0x01,0x00]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x10]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x30]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0xf0]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x01]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x03]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x00,0x0f]
+
+v_min_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x08,0x00]
+
+v_min_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x10,0x00]
+
+v_min_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x20,0x00]
+
+v_min_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x40,0x00]
+
+v_min_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x14,0x01,0xe4,0x80,0x00]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x17,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0xff,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x65,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x66,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x67,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x6a,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x6b,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x7b,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x7c,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x7e,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x7f,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x80,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0xc1,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0xf0,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0xf7,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0xfb,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0xfc,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0xfd,0x06,0x86,0x06]
+
+v_max_f32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x26,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 mul:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x46,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 mul:4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x86,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 div:2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0xc6,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x00,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x01,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x02,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x03,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x04,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x05,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x0e,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x16,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x00,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x01,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x02,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x03,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x04,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x05,0x06]
+
+v_max_f32_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x16,0x06]
+
+v_max_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x26,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x06]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x00]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x01]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x02]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x03]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x04]
+
+v_max_f32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x05]
+
+v_max_f32_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x16]
+
+v_max_f32_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x16,0x01,0x06,0x06,0x26]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x00]
+
+v_max_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x17,0x01,0xe4,0x00,0x00]
+
+v_max_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0xff,0xe4,0x00,0x00]
+
+v_max_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x16,0x01,0xe4,0x00,0x00]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x40,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x41,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x42,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x43,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x30,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x34,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x38,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x3c,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x01,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x0f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x11,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x1f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x21,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0x2f,0x01,0x00]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x10]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x30]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0xf0]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x01]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x03]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x00,0x0f]
+
+v_max_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x08,0x00]
+
+v_max_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x10,0x00]
+
+v_max_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x20,0x00]
+
+v_max_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x40,0x00]
+
+v_max_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x16,0x01,0xe4,0x80,0x00]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x19,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0xff,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x65,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x66,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x67,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x6a,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x6b,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x7b,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x7c,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x7e,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x7f,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x80,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0xc1,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0xf0,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0xf7,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0xfb,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0xfc,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0xfd,0x06,0x86,0x06]
+
+v_min_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x00,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x01,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x02,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x03,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x04,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x05,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x0e,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x16,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x00,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x01,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x02,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x03,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x04,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x05,0x06]
+
+v_min_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x0e,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x06]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x00]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x01]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x02]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x03]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x04]
+
+v_min_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x05]
+
+v_min_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x18,0x01,0x06,0x06,0x0e]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x00]
+
+v_min_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x19,0x01,0xe4,0x00,0x00]
+
+v_min_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0xff,0xe4,0x00,0x00]
+
+v_min_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x18,0x01,0xe4,0x00,0x00]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x40,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x41,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x42,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x43,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x30,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x34,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x38,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x3c,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x01,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x0f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x11,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x1f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x21,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0x2f,0x01,0x00]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x10]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x30]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0xf0]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x01]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x03]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x00,0x0f]
+
+v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x18,0x01,0xe4,0x08,0x00]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x1b,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0xff,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x65,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x66,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x67,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x6a,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x6b,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x7b,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x7c,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x7e,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x7f,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x80,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0xc1,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0xf0,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0xf7,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0xfb,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0xfc,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0xfd,0x06,0x86,0x06]
+
+v_max_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x00,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x01,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x02,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x03,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x04,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x05,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x0e,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x16,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x00,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x01,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x02,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x03,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x04,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x05,0x06]
+
+v_max_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x0e,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x06]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x00]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x01]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x02]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x03]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x04]
+
+v_max_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x05]
+
+v_max_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1a,0x01,0x06,0x06,0x0e]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x00]
+
+v_max_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x1b,0x01,0xe4,0x00,0x00]
+
+v_max_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0xff,0xe4,0x00,0x00]
+
+v_max_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x1a,0x01,0xe4,0x00,0x00]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1b,0x00,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x40,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x41,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x42,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x43,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x30,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x34,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x38,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x3c,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x01,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x0f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x11,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x1f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x21,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0x2f,0x01,0x00]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x10]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x30]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0xf0]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x01]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x03]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x00,0x0f]
+
+v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x1a,0x01,0xe4,0x08,0x00]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x1d,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0xff,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x65,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x66,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x67,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x6a,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x6b,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x7b,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x7c,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x7e,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x7f,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x80,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0xc1,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0xf0,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0xf7,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0xfb,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0xfc,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0xfd,0x06,0x86,0x06]
+
+v_min_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x00,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x01,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x02,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x03,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x04,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x05,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x0e,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x16,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x00,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x01,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x02,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x03,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x04,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x05,0x06]
+
+v_min_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x0e,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x06]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x00]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x01]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x02]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x03]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x04]
+
+v_min_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x05]
+
+v_min_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1c,0x01,0x06,0x06,0x0e]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x00]
+
+v_min_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x1d,0x01,0xe4,0x00,0x00]
+
+v_min_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0xff,0xe4,0x00,0x00]
+
+v_min_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x1c,0x01,0xe4,0x00,0x00]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1b,0x00,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x40,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x41,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x42,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x43,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x30,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x34,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x38,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x3c,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x01,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x0f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x11,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x1f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x21,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0x2f,0x01,0x00]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x10]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x30]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0xf0]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x01]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x03]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x00,0x0f]
+
+v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x1c,0x01,0xe4,0x08,0x00]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x1f,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0xff,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x65,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x66,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x67,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x6a,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x6b,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x7b,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x7c,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x7e,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x7f,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x80,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0xc1,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0xf0,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0xf7,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0xfb,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0xfc,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0xfd,0x06,0x86,0x06]
+
+v_max_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x00,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x01,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x02,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x03,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x04,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x05,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x0e,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x16,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x00,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x01,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x02,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x03,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x04,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x05,0x06]
+
+v_max_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x0e,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x06]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x00]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x01]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x02]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x03]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x04]
+
+v_max_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x05]
+
+v_max_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x1e,0x01,0x06,0x06,0x0e]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x00]
+
+v_max_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x1f,0x01,0xe4,0x00,0x00]
+
+v_max_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0xff,0xe4,0x00,0x00]
+
+v_max_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x1e,0x01,0xe4,0x00,0x00]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x40,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x41,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x42,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x43,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x30,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x34,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x38,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x3c,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x01,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x0f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x11,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x1f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x21,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0x2f,0x01,0x00]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x10]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x30]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0xf0]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x01]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x03]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x00,0x0f]
+
+v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x1e,0x01,0xe4,0x08,0x00]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x21,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0xff,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x65,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x66,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x67,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x6a,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x6b,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x7b,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x7c,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x7e,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x7f,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x80,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0xc1,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0xf0,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0xf7,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0xfb,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0xfc,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0xfd,0x06,0x86,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x00,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x01,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x02,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x03,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x04,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x05,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x0e,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x00,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x01,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x02,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x03,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x04,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x05,0x06]
+
+v_lshrrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x0e,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x00]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x01]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x02]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x03]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x04]
+
+v_lshrrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x05]
+
+v_lshrrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x20,0x01,0x06,0x06,0x0e]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x21,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0xff,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x20,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x40,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x41,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x42,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x43,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x30,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x34,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x38,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x3c,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x0f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x11,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x1f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x21,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0x2f,0x01,0x00]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x10]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x30]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0xf0]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x01]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x03]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x00,0x0f]
+
+v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x20,0x01,0xe4,0x08,0x00]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x23,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0xff,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x65,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x66,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x67,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x6a,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x6b,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x7b,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x7c,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x7e,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x7f,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x80,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0xc1,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0xf0,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0xf7,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0xfb,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0xfc,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0xfd,0x06,0x86,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x00,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x01,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x02,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x03,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x04,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x05,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x0e,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x00,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x01,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x02,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x03,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x04,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x05,0x06]
+
+v_ashrrev_i32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x0e,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x00]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x01]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x02]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x03]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x04]
+
+v_ashrrev_i32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x05]
+
+v_ashrrev_i32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x22,0x01,0x06,0x06,0x0e]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0xff,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x22,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x40,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x41,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x42,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x43,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x30,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x34,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x38,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x3c,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x0f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x11,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x1f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x21,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0x2f,0x01,0x00]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x10]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x30]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0xf0]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x01]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x03]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x0f]
+
+v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x08,0x00]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x25,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0xff,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x65,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x66,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x67,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x6a,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x6b,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x7b,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x7c,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x7e,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x7f,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x80,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0xc1,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0xf0,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0xf7,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0xfb,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0xfc,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0xfd,0x06,0x86,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x00,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x01,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x02,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x03,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x04,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x05,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x0e,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x00,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x01,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x02,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x03,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x04,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x05,0x06]
+
+v_lshlrev_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x0e,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x00]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x01]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x02]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x03]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x04]
+
+v_lshlrev_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x05]
+
+v_lshlrev_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x24,0x01,0x06,0x06,0x0e]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0xff,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x24,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x40,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x41,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x42,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x43,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x30,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x34,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x38,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x3c,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x0f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x11,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x1f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x21,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0x2f,0x01,0x00]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x10]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x30]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0xf0]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x01]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x03]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x0f]
+
+v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x08,0x00]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x27,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0xff,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x65,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x66,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x67,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x6a,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x6b,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x7b,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x7c,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x7e,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x7f,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x80,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0xc1,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0xf0,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0xf7,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0xfb,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0xfc,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0xfd,0x06,0x86,0x06]
+
+v_and_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x00,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x01,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x02,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x03,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x04,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x05,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x0e,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x16,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x00,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x01,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x02,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x03,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x04,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x05,0x06]
+
+v_and_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x0e,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x06]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x00]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x01]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x02]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x03]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x04]
+
+v_and_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x05]
+
+v_and_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x26,0x01,0x06,0x06,0x0e]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00]
+
+v_and_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00]
+
+v_and_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0xff,0xe4,0x00,0x00]
+
+v_and_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x26,0x01,0xe4,0x00,0x00]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x40,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x41,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x42,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x43,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x30,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x34,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x38,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x3c,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x01,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x0f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x11,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x1f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x21,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0x2f,0x01,0x00]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x10]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x30]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0xf0]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x01]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x03]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x0f]
+
+v_and_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x08,0x00]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x29,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0xff,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x65,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x66,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x67,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x6a,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x6b,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x7b,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x7c,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x7e,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x7f,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x80,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0xc1,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0xf0,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0xf7,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0xfb,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0xfc,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0xfd,0x06,0x86,0x06]
+
+v_or_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x00,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x01,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x02,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x03,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x04,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x05,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x0e,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x16,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x00,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x01,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x02,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x03,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x04,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x05,0x06]
+
+v_or_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x0e,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x06]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x00]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x01]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x02]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x03]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x04]
+
+v_or_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x05]
+
+v_or_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x28,0x01,0x06,0x06,0x0e]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00]
+
+v_or_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00]
+
+v_or_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0xff,0xe4,0x00,0x00]
+
+v_or_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x28,0x01,0xe4,0x00,0x00]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x40,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x41,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x42,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x43,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x30,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x34,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x38,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x3c,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x01,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x0f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x11,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x1f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x21,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0x2f,0x01,0x00]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x10]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x30]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0xf0]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x01]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x03]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x0f]
+
+v_or_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x08,0x00]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x2b,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0xff,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x65,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x66,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x67,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x6a,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x6b,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x7b,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x7c,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x7e,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x7f,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x80,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0xc1,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0xf0,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0xf7,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0xfb,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0xfc,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0xfd,0x06,0x86,0x06]
+
+v_xor_b32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x00,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x01,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x02,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x03,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x04,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x05,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x0e,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x16,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x00,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x01,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x02,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x03,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x04,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x05,0x06]
+
+v_xor_b32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x0e,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x06]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x00]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x01]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x02]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x03]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x04]
+
+v_xor_b32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x05]
+
+v_xor_b32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x2a,0x01,0x06,0x06,0x0e]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x2b,0x01,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0xff,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x2a,0x01,0xe4,0x00,0x00]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1b,0x00,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x40,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x41,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x42,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x43,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x30,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x34,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x38,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x3c,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x01,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x0f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x11,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x1f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x21,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0x2f,0x01,0x00]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x10]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x30]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0xf0]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x01]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x03]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x00,0x0f]
+
+v_xor_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x2a,0x01,0xe4,0x08,0x00]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
+
+v_mac_f32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
+
+v_mac_f32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0xff,0xe4,0x00,0x00]
+
+v_mac_f32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x2c,0x01,0xe4,0x00,0x00]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x40,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x41,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x42,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x43,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x30,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x34,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x38,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x3c,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x01,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x0f,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x11,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x1f,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x21,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0x2f,0x01,0x00]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x10]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x30]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0xf0]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x01]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x03]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x0f]
+
+v_mac_f32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x08,0x00]
+
+v_mac_f32_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x10,0x00]
+
+v_mac_f32_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x20,0x00]
+
+v_mac_f32_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x40,0x00]
+
+v_mac_f32_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x80,0x00]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
+
+v_add_co_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x33,0x01,0x06,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0xff,0x06,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x65,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x66,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x67,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x6a,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x6b,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x7b,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x7c,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x7e,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x7f,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x80,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0xc1,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0xf0,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0xf7,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0xfb,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0xfc,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0xfd,0x06,0x86,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x32,0x01,0x06,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x26,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x00,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x01,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x02,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x03,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x04,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x05,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x0e,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x16,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x00,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x01,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x02,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x03,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x04,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x05,0x06]
+
+v_add_co_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x0e,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x06]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x00]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x01]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x02]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x03]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x04]
+
+v_add_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x05]
+
+v_add_co_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x32,0x01,0x06,0x06,0x0e]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x00]
+
+v_add_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x33,0x01,0xe4,0x00,0x00]
+
+v_add_co_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0xff,0xe4,0x00,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x32,0x01,0xe4,0x00,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1b,0x00,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x40,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x41,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x42,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x43,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x30,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x34,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x38,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x3c,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x01,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x0f,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x11,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x1f,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x21,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0x2f,0x01,0x00]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x10]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x30]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0xf0]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x01]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x03]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x00,0x0f]
+
+v_add_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x32,0x01,0xe4,0x08,0x00]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_co_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x35,0x01,0x06,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0xff,0x06,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x65,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x66,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x67,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x6a,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x6b,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x7b,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x7c,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x7e,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x7f,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x80,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0xc1,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0xf0,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0xf7,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0xfb,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0xfc,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0xfd,0x06,0x86,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x26,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x00,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x01,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x02,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x03,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x04,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x05,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x0e,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x16,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x00,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x01,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x02,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x03,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x04,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x05,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x0e,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x06]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x00]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x01]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x02]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x03]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x04]
+
+v_sub_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x05]
+
+v_sub_co_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x34,0x01,0x06,0x06,0x0e]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00]
+
+v_sub_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0xff,0xe4,0x00,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x34,0x01,0xe4,0x00,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x40,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x41,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x42,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x43,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x30,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x34,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x38,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x3c,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x01,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x0f,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x11,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x1f,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x21,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0x2f,0x01,0x00]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x10]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x30]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0xf0]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x01]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x03]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x0f]
+
+v_sub_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x08,0x00]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_co_u32_sdwa v255, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x37,0x01,0x06,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0xff,0x06,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x65,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x66,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x67,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x6a,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x6b,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x7b,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x7c,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x7e,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x7f,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x80,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0xc1,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0xf0,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0xf7,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0xfb,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0xfc,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0xfd,0x06,0x86,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x26,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x00,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x01,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x02,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x03,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x04,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x05,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x0e,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x16,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x00,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x01,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x02,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x03,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x04,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x05,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x0e,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x06]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x00]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x01]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x02]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x03]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x04]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x05]
+
+v_subrev_co_u32_sdwa v5, vcc, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x36,0x01,0x06,0x06,0x0e]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x00]
+
+v_subrev_co_u32_dpp v255, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x37,0x01,0xe4,0x00,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0xff,0xe4,0x00,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x36,0x01,0xe4,0x00,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x40,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x41,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x42,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x43,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x30,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x34,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x38,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x3c,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x01,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x0f,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x11,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x1f,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x21,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0x2f,0x01,0x00]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x10]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x30]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0xf0]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x01]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x03]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x00,0x0f]
+
+v_subrev_co_u32_dpp v5, vcc, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x36,0x01,0xe4,0x08,0x00]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_co_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x39,0x01,0x06,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0xff,0x06,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, 0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x80,0x06,0x86,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0xc1,0x06,0x86,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, 0.5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0xf0,0x06,0x86,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, -4.0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0xf7,0x06,0x86,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x26,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x00,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x01,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x02,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x03,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x04,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x05,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x0e,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x16,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x00,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x01,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x02,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x03,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x04,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x05,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x0e,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x06]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x00]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x01]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x02]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x03]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x04]
+
+v_addc_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x05]
+
+v_addc_co_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x38,0x01,0x06,0x06,0x0e]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x00]
+
+v_addc_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x39,0x01,0xe4,0x00,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0xff,0xe4,0x00,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x38,0x01,0xe4,0x00,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x40,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x41,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x42,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x43,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x30,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x34,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x38,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x3c,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x01,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x0f,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x11,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x1f,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x21,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0x2f,0x01,0x00]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x10]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x30]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0xf0]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x01]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x03]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x00,0x0f]
+
+v_addc_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x38,0x01,0xe4,0x08,0x00]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_co_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x3b,0x01,0x06,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0xff,0x06,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, 0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x80,0x06,0x86,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0xc1,0x06,0x86,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, 0.5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0xf0,0x06,0x86,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, -4.0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0xf7,0x06,0x86,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x26,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x00,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x01,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x02,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x03,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x04,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x05,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x0e,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x16,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x00,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x01,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x02,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x03,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x04,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x05,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x0e,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x06]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x00]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x01]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x02]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x03]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x04]
+
+v_subb_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x05]
+
+v_subb_co_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3a,0x01,0x06,0x06,0x0e]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x00]
+
+v_subb_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x3b,0x01,0xe4,0x00,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0xff,0xe4,0x00,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x3a,0x01,0xe4,0x00,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x40,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x41,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x42,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x43,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x30,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x34,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x38,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x3c,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x01,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x0f,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x11,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x1f,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x21,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0x2f,0x01,0x00]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x10]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x30]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0xf0]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x01]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x03]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x00,0x0f]
+
+v_subb_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x3a,0x01,0xe4,0x08,0x00]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v255, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x3d,0x01,0x06,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0xff,0x06,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, 0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x80,0x06,0x86,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, -1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0xc1,0x06,0x86,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, 0.5, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0xf0,0x06,0x86,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, -4.0, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0xf7,0x06,0x86,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x26,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x00,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x01,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x02,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x03,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x04,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x05,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x0e,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x16,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x00,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x01,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x02,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x03,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x04,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x05,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, sext(v1), v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x0e,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x06]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x00]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x01]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x02]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x03]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x04]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x05]
+
+v_subbrev_co_u32_sdwa v5, vcc, v1, sext(v2), vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3c,0x01,0x06,0x06,0x0e]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x00]
+
+v_subbrev_co_u32_dpp v255, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x3d,0x01,0xe4,0x00,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v255, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0xff,0xe4,0x00,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v255, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x3c,0x01,0xe4,0x00,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x40,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x41,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x42,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x43,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x30,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x34,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x38,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x3c,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x01,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x0f,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x11,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x1f,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x21,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0x2f,0x01,0x00]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x10]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x30]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0xf0]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x01]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x03]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x00,0x0f]
+
+v_subbrev_co_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x3c,0x01,0xe4,0x08,0x00]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x3f,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0xff,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x65,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x66,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x67,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x6a,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x6b,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x7b,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x7c,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x7e,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x7f,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x80,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0xc1,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0xf0,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0xf7,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0xfb,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0xfc,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0xfd,0x06,0x86,0x06]
+
+v_add_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x26,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x00,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x01,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x02,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x03,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x04,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x05,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x0e,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x16,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x00,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x01,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x02,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x03,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x04,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x05,0x06]
+
+v_add_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x16,0x06]
+
+v_add_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x26,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x06]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x00]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x01]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x02]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x03]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x04]
+
+v_add_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x05]
+
+v_add_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x16]
+
+v_add_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x3e,0x01,0x06,0x06,0x26]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x00]
+
+v_add_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x3f,0x01,0xe4,0x00,0x00]
+
+v_add_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0xff,0xe4,0x00,0x00]
+
+v_add_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x3e,0x01,0xe4,0x00,0x00]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x00,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x40,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x41,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x42,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x43,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x30,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x34,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x38,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x3c,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x01,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x0f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x11,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x1f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x21,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0x2f,0x01,0x00]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x10]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x30]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0xf0]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x01]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x03]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x00,0x0f]
+
+v_add_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x08,0x00]
+
+v_add_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x10,0x00]
+
+v_add_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x20,0x00]
+
+v_add_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x40,0x00]
+
+v_add_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x3e,0x01,0xe4,0x80,0x00]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x41,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0xff,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x65,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x66,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x67,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x6a,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x6b,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x7b,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x7c,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x7e,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x7f,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x80,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0xc1,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0xf0,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0xf7,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0xfb,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0xfc,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0xfd,0x06,0x86,0x06]
+
+v_sub_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x26,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x00,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x01,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x02,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x03,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x04,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x05,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x0e,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x16,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x00,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x01,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x02,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x03,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x04,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x05,0x06]
+
+v_sub_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x16,0x06]
+
+v_sub_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x26,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x06]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x00]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x01]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x02]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x03]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x04]
+
+v_sub_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x05]
+
+v_sub_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x16]
+
+v_sub_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x40,0x01,0x06,0x06,0x26]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x41,0x01,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0xff,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x40,0x01,0xe4,0x00,0x00]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1b,0x00,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x40,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x41,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x42,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x43,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x30,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x34,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x38,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x3c,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x01,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x0f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x11,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x1f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x21,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0x2f,0x01,0x00]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x10]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x30]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0xf0]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x01]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x03]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x00,0x0f]
+
+v_sub_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x08,0x00]
+
+v_sub_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x10,0x00]
+
+v_sub_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x20,0x00]
+
+v_sub_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x40,0x00]
+
+v_sub_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x40,0x01,0xe4,0x80,0x00]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x43,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0xff,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x65,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x66,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x67,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x6a,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x6b,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x7b,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x7c,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x7e,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x7f,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x80,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0xc1,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0xf0,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0xf7,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0xfb,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0xfc,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0xfd,0x06,0x86,0x06]
+
+v_subrev_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x26,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x00,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x01,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x02,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x03,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x04,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x05,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x0e,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x16,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x00,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x01,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x02,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x03,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x04,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x05,0x06]
+
+v_subrev_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x16,0x06]
+
+v_subrev_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x26,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x06]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x00]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x01]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x02]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x03]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x04]
+
+v_subrev_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x05]
+
+v_subrev_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x16]
+
+v_subrev_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x42,0x01,0x06,0x06,0x26]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x43,0x01,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0xff,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x42,0x01,0xe4,0x00,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1b,0x00,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x40,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x41,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x42,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x43,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x30,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x34,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x38,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x3c,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x01,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x0f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x11,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x1f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x21,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0x2f,0x01,0x00]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x10]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x30]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0xf0]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x01]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x03]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x00,0x0f]
+
+v_subrev_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x08,0x00]
+
+v_subrev_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x10,0x00]
+
+v_subrev_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x20,0x00]
+
+v_subrev_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x40,0x00]
+
+v_subrev_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x42,0x01,0xe4,0x80,0x00]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x45,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0xff,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x65,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x66,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x67,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x6a,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x6b,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x7b,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x7c,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x7e,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x7f,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x80,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0xc1,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0xf0,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0xf7,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0xfb,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0xfc,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0xfd,0x06,0x86,0x06]
+
+v_mul_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x26,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x00,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x01,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x02,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x03,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x04,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x05,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x0e,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x16,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x00,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x01,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x02,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x03,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x04,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x05,0x06]
+
+v_mul_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x16,0x06]
+
+v_mul_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x26,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x06]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x00]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x01]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x02]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x03]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x04]
+
+v_mul_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x05]
+
+v_mul_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x16]
+
+v_mul_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x44,0x01,0x06,0x06,0x26]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x45,0x01,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0xff,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x44,0x01,0xe4,0x00,0x00]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1b,0x00,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x40,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x41,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x42,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x43,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x30,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x34,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x38,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x3c,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x01,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x0f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x11,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x1f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x21,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0x2f,0x01,0x00]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x10]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x30]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0xf0]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x01]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x03]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x00,0x0f]
+
+v_mul_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x08,0x00]
+
+v_mul_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x10,0x00]
+
+v_mul_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x20,0x00]
+
+v_mul_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x40,0x00]
+
+v_mul_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x44,0x01,0xe4,0x80,0x00]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x00]
+
+v_mac_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x47,0x01,0xe4,0x00,0x00]
+
+v_mac_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0xff,0xe4,0x00,0x00]
+
+v_mac_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x46,0x01,0xe4,0x00,0x00]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1b,0x00,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x40,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x41,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x42,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x43,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x30,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x34,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x38,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x3c,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x01,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x0f,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x11,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x1f,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x21,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0x2f,0x01,0x00]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x10]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x30]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0xf0]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x01]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x03]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x00,0x0f]
+
+v_mac_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x08,0x00]
+
+v_mac_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x10,0x00]
+
+v_mac_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x20,0x00]
+
+v_mac_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x40,0x00]
+
+v_mac_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x46,0x01,0xe4,0x80,0x00]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x4d,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0xff,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x65,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x66,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x67,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x6a,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x6b,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x7b,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x7c,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x7e,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x7f,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x80,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0xc1,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0xfb,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0xfc,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0xfd,0x06,0x86,0x06]
+
+v_add_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x26,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x00,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x01,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x02,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x03,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x04,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x05,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x0e,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x16,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x00,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x01,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x02,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x03,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x04,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x05,0x06]
+
+v_add_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x0e,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x06]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x00]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x01]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x02]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x03]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x04]
+
+v_add_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x05]
+
+v_add_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4c,0x01,0x06,0x06,0x0e]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x00]
+
+v_add_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x4d,0x01,0xe4,0x00,0x00]
+
+v_add_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0xff,0xe4,0x00,0x00]
+
+v_add_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x4c,0x01,0xe4,0x00,0x00]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x00,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x42,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x43,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x30,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x34,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x38,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x3c,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x01,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x0f,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x11,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x1f,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x21,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0x2f,0x01,0x00]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x10]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x30]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0xf0]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x01]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x03]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x00,0x0f]
+
+v_add_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x4c,0x01,0xe4,0x08,0x00]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x4f,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0xff,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x65,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x66,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x67,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x6a,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x6b,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x7b,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x7c,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x7e,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x7f,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x80,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0xc1,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0xfb,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0xfc,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0xfd,0x06,0x86,0x06]
+
+v_sub_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x26,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x00,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x01,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x02,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x03,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x04,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x05,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x0e,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x16,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x00,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x01,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x02,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x03,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x04,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x05,0x06]
+
+v_sub_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x0e,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x06]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x00]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x01]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x02]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x03]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x04]
+
+v_sub_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x05]
+
+v_sub_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x4e,0x01,0x06,0x06,0x0e]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x00]
+
+v_sub_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x4f,0x01,0xe4,0x00,0x00]
+
+v_sub_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0xff,0xe4,0x00,0x00]
+
+v_sub_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x4e,0x01,0xe4,0x00,0x00]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x40,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x41,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x42,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x43,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x30,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x34,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x38,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x3c,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x01,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x0f,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x11,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x1f,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x21,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0x2f,0x01,0x00]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x10]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x30]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0xf0]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x01]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x03]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x00,0x0f]
+
+v_sub_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x4e,0x01,0xe4,0x08,0x00]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x51,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x65,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x66,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x67,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x6a,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x6b,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x7b,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x7c,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x7e,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x7f,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x80,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0xc1,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0xfb,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0xfc,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0xfd,0x06,0x86,0x06]
+
+v_subrev_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x26,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x00,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x01,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x02,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x03,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x04,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x05,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x0e,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x16,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x00,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x01,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x02,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x03,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x04,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x05,0x06]
+
+v_subrev_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x0e,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x06]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x00]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x01]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x02]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x03]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x04]
+
+v_subrev_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x05]
+
+v_subrev_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x50,0x01,0x06,0x06,0x0e]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00]
+
+v_subrev_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x51,0x01,0xe4,0x00,0x00]
+
+v_subrev_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0xff,0xe4,0x00,0x00]
+
+v_subrev_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x50,0x01,0xe4,0x00,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x40,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x41,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x42,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x43,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x30,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x34,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x38,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x3c,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x01,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x0f,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x11,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x1f,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x21,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0x2f,0x01,0x00]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x10]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x30]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0xf0]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x01]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x03]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x0f]
+
+v_subrev_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x08,0x00]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x53,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x65,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x66,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x67,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x6a,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x6b,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x7b,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x7c,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x7e,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x7f,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x80,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0xc1,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0xfb,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0xfc,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0xfd,0x06,0x86,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x00,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x01,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x02,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x03,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x04,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x05,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x0e,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x16,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x00,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x01,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x02,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x03,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x04,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x05,0x06]
+
+v_mul_lo_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x0e,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x06]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x00]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x01]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x02]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x03]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x04]
+
+v_mul_lo_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x05]
+
+v_mul_lo_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x52,0x01,0x06,0x06,0x0e]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x00]
+
+v_mul_lo_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x53,0x01,0xe4,0x00,0x00]
+
+v_mul_lo_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0xff,0xe4,0x00,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x52,0x01,0xe4,0x00,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x00,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x40,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x41,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x42,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x43,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x30,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x34,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x38,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x3c,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x01,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x0f,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x11,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x1f,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x21,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0x2f,0x01,0x00]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x10]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x30]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0xf0]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x01]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x03]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x0f]
+
+v_mul_lo_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x08,0x00]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x55,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x65,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x66,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x67,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x6a,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x6b,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x7b,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x7c,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x7e,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x7f,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x80,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0xc1,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0xfb,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0xfc,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0xfd,0x06,0x86,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x00,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x01,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x02,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x03,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x04,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x05,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x0e,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x16,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x00,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x01,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x02,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x03,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x04,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x05,0x06]
+
+v_lshlrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x0e,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x06]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x00]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x01]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x02]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x03]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x04]
+
+v_lshlrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x05]
+
+v_lshlrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x54,0x01,0x06,0x06,0x0e]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x55,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0xff,0xe4,0x00,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x54,0x01,0xe4,0x00,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x00,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x40,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x41,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x42,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x43,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x30,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x34,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x38,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x3c,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x0f,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x11,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x1f,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x21,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0x2f,0x01,0x00]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x10]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x30]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0xf0]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x01]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x03]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x0f]
+
+v_lshlrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x08,0x00]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x57,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0xff,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x65,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x66,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x67,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x6a,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x6b,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x7b,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x7c,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x7e,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x7f,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x80,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0xc1,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0xfb,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0xfc,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0xfd,0x06,0x86,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x00,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x01,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x02,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x03,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x04,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x05,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x0e,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x16,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x00,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x01,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x02,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x03,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x04,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x05,0x06]
+
+v_lshrrev_b16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x0e,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x06]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x00]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x01]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x02]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x03]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x04]
+
+v_lshrrev_b16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x05]
+
+v_lshrrev_b16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x56,0x01,0x06,0x06,0x0e]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x57,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0xff,0xe4,0x00,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x56,0x01,0xe4,0x00,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x40,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x41,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x42,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x43,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x30,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x34,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x38,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x3c,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x0f,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x11,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x1f,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x21,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0x2f,0x01,0x00]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x10]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x30]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0xf0]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x01]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x03]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x00,0x0f]
+
+v_lshrrev_b16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x56,0x01,0xe4,0x08,0x00]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x59,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0xff,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x65,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x66,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x67,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x6a,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x6b,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x7b,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x7c,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x7e,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x7f,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x80,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0xc1,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0xfb,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0xfc,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0xfd,0x06,0x86,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x00,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x01,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x02,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x03,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x04,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x05,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x0e,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x16,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x00,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x01,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x02,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x03,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x04,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x05,0x06]
+
+v_ashrrev_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x0e,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x06]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x00]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x01]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x02]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x03]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x04]
+
+v_ashrrev_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x05]
+
+v_ashrrev_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x58,0x01,0x06,0x06,0x0e]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x59,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0xff,0xe4,0x00,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x58,0x01,0xe4,0x00,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1b,0x00,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x40,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x41,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x42,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x43,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x30,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x34,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x38,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x3c,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x0f,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x11,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x1f,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x21,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0x2f,0x01,0x00]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x10]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x30]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0xf0]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x01]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x03]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x00,0x0f]
+
+v_ashrrev_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x58,0x01,0xe4,0x08,0x00]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x5b,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0xff,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x65,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x66,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x67,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x6a,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x6b,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x7b,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x7c,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x7e,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x7f,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x80,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0xc1,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0xf0,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0xf7,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0xfb,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0xfc,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0xfd,0x06,0x86,0x06]
+
+v_max_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x26,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x00,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x01,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x02,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x03,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x04,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x05,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x0e,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x16,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x00,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x01,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x02,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x03,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x04,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x05,0x06]
+
+v_max_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x16,0x06]
+
+v_max_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x26,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x06]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x00]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x01]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x02]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x03]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x04]
+
+v_max_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x05]
+
+v_max_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x16]
+
+v_max_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5a,0x01,0x06,0x06,0x26]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x00]
+
+v_max_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x5b,0x01,0xe4,0x00,0x00]
+
+v_max_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0xff,0xe4,0x00,0x00]
+
+v_max_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x5a,0x01,0xe4,0x00,0x00]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1b,0x00,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x40,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x41,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x42,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x43,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x30,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x34,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x38,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x3c,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x01,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x0f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x11,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x1f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x21,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0x2f,0x01,0x00]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x10]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x30]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0xf0]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x01]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x03]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x00,0x0f]
+
+v_max_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x08,0x00]
+
+v_max_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x10,0x00]
+
+v_max_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x20,0x00]
+
+v_max_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x40,0x00]
+
+v_max_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5a,0x01,0xe4,0x80,0x00]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x5d,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0xff,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x65,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x66,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x67,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x6a,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x6b,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x7b,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x7c,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x7e,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x7f,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x80,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0xc1,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0xf0,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0xf7,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0xfb,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0xfc,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0xfd,0x06,0x86,0x06]
+
+v_min_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x26,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x00,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x01,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x02,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x03,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x04,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x05,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x0e,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x16,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x00,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x01,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x02,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x03,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x04,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x05,0x06]
+
+v_min_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x16,0x06]
+
+v_min_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x26,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x06]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x00]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x01]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x02]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x03]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x04]
+
+v_min_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x05]
+
+v_min_f16_sdwa v5, v1, -v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x16]
+
+v_min_f16_sdwa v5, v1, |v2| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5c,0x01,0x06,0x06,0x26]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x00]
+
+v_min_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x5d,0x01,0xe4,0x00,0x00]
+
+v_min_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0xff,0xe4,0x00,0x00]
+
+v_min_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x5c,0x01,0xe4,0x00,0x00]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1b,0x00,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x40,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x41,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x42,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x43,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x30,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x34,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x38,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x3c,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x01,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x0f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x11,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x1f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x21,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0x2f,0x01,0x00]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x10]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x30]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0xf0]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x01]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x03]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x00,0x0f]
+
+v_min_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x08,0x00]
+
+v_min_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x10,0x00]
+
+v_min_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x20,0x00]
+
+v_min_f16_dpp v5, v1, -v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x40,0x00]
+
+v_min_f16_dpp v5, v1, |v2| quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5c,0x01,0xe4,0x80,0x00]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x5f,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0xff,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x65,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x66,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x67,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x6a,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x6b,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x7b,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x7c,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x7e,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x7f,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x80,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0xc1,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0xfb,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0xfc,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0xfd,0x06,0x86,0x06]
+
+v_max_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x00,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x01,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x02,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x03,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x04,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x05,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x0e,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x16,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x00,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x01,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x02,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x03,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x04,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x05,0x06]
+
+v_max_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x0e,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x06]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x00]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x01]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x02]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x03]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x04]
+
+v_max_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x05]
+
+v_max_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x5e,0x01,0x06,0x06,0x0e]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x00]
+
+v_max_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x5f,0x01,0xe4,0x00,0x00]
+
+v_max_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0xff,0xe4,0x00,0x00]
+
+v_max_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x5e,0x01,0xe4,0x00,0x00]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1b,0x00,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x40,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x41,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x42,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x43,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x30,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x34,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x38,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x3c,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x01,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x0f,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x11,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x1f,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x21,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0x2f,0x01,0x00]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x10]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x30]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0xf0]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x01]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x03]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x00,0x0f]
+
+v_max_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x5e,0x01,0xe4,0x08,0x00]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x61,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0xff,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x65,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x66,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x67,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x6a,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x6b,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x7b,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x7c,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x7e,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x7f,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x80,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0xc1,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0xfb,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0xfc,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0xfd,0x06,0x86,0x06]
+
+v_max_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x00,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x01,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x02,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x03,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x04,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x05,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x0e,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x16,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x00,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x01,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x02,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x03,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x04,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x05,0x06]
+
+v_max_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x0e,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x06]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x00]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x01]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x02]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x03]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x04]
+
+v_max_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x05]
+
+v_max_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x60,0x01,0x06,0x06,0x0e]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x00]
+
+v_max_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x61,0x01,0xe4,0x00,0x00]
+
+v_max_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0xff,0xe4,0x00,0x00]
+
+v_max_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x60,0x01,0xe4,0x00,0x00]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1b,0x00,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x40,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x41,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x42,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x43,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x30,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x34,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x38,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x3c,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x01,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x0f,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x11,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x1f,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x21,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0x2f,0x01,0x00]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x10]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x30]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0xf0]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x01]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x03]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x00,0x0f]
+
+v_max_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x60,0x01,0xe4,0x08,0x00]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x63,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0xff,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x65,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x66,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x67,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x6a,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x6b,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x7b,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x7c,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x7e,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x7f,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x80,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0xc1,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0xfb,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0xfc,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0xfd,0x06,0x86,0x06]
+
+v_min_u16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x00,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x01,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x02,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x03,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x04,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x05,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x0e,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x16,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x00,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x01,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x02,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x03,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x04,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x05,0x06]
+
+v_min_u16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x0e,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x06]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x00]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x01]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x02]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x03]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x04]
+
+v_min_u16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x05]
+
+v_min_u16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x62,0x01,0x06,0x06,0x0e]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x00]
+
+v_min_u16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x63,0x01,0xe4,0x00,0x00]
+
+v_min_u16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0xff,0xe4,0x00,0x00]
+
+v_min_u16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x62,0x01,0xe4,0x00,0x00]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1b,0x00,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x40,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x41,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x42,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x43,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x30,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x34,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x38,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x3c,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x01,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x0f,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x11,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x1f,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x21,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0x2f,0x01,0x00]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x10]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x30]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0xf0]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x01]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x03]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x00,0x0f]
+
+v_min_u16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x62,0x01,0xe4,0x08,0x00]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x65,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0xff,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x65,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x66,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x67,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x6a,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x6b,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x7b,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x7c,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x7e,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x7f,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x80,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0xc1,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0xfb,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0xfc,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0xfd,0x06,0x86,0x06]
+
+v_min_i16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x00,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x01,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x02,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x03,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x04,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x05,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x0e,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x16,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x00,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x01,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x02,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x03,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x04,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x05,0x06]
+
+v_min_i16_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x0e,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x06]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x00]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x01]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x02]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x03]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x04]
+
+v_min_i16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x05]
+
+v_min_i16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x64,0x01,0x06,0x06,0x0e]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x00]
+
+v_min_i16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00]
+
+v_min_i16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0xff,0xe4,0x00,0x00]
+
+v_min_i16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x64,0x01,0xe4,0x00,0x00]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x40,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x41,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x42,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x43,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x30,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x34,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x38,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x3c,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x01,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x0f,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x11,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x1f,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x21,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0x2f,0x01,0x00]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x10]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x30]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0xf0]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x01]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x03]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x00,0x0f]
+
+v_min_i16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x08,0x00]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x67,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0xff,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x65,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x66,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x67,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x6a,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x6b,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x7b,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x7c,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x7e,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x7f,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x80,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0xc1,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0xf0,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0xf7,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0xfb,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0xfc,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0xfd,0x06,0x86,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x26,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x00,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x01,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x02,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x03,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x04,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x05,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x0e,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x16,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x00,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x01,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x02,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x03,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x04,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x05,0x06]
+
+v_ldexp_f16_sdwa v5, -v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x16,0x06]
+
+v_ldexp_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x26,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x06]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x00]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x01]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x02]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x03]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x04]
+
+v_ldexp_f16_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x05]
+
+v_ldexp_f16_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x66,0x01,0x06,0x06,0x0e]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0xff,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x66,0x01,0xe4,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x40,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x41,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x42,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x43,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x30,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x34,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x38,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x3c,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x01,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x0f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x11,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x1f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x21,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0x2f,0x01,0x00]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x10]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x30]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0xf0]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x01]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x03]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x00,0x0f]
+
+v_ldexp_f16_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x08,0x00]
+
+v_ldexp_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
+
+v_ldexp_f16_dpp v5, |v1|, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x20,0x00]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x69,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0xff,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x65,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x66,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x67,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x6a,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x6b,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x7b,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x7c,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x7e,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x7f,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x80,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0xc1,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0xf0,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0xf7,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0xfb,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0xfc,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0xfd,0x06,0x86,0x06]
+
+v_add_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x68,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x26,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x00,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x01,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x02,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x03,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x04,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x05,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x0e,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x16,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x16,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x00,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x01,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x02,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x03,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x04,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x05,0x06]
+
+v_add_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x0e,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x06]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x00]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x01]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x02]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x03]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x04]
+
+v_add_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x05]
+
+v_add_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x68,0x01,0x06,0x06,0x0e]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x00]
+
+v_add_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x69,0x01,0xe4,0x00,0x00]
+
+v_add_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0xff,0xe4,0x00,0x00]
+
+v_add_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x68,0x01,0xe4,0x00,0x00]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x40,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x41,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x42,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x43,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x30,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x34,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x38,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x3c,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x01,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x0f,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x11,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x1f,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x21,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0x2f,0x01,0x00]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x10]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x30]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xf0]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0xf0]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x01]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x03]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x0f]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x00,0x0f]
+
+v_add_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x08,0x00]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x6b,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0xff,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x65,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x66,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x67,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x6a,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x6b,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x7b,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x7c,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x7e,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x7f,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x80,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0xc1,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0xf0,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0xf7,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0xfb,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0xfc,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0xfd,0x06,0x86,0x06]
+
+v_sub_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x6a,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x26,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x00,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x01,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x02,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x03,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x04,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x05,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x0e,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x16,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x16,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x00,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x01,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x02,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x03,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x04,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x05,0x06]
+
+v_sub_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x0e,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x06]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x00]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x01]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x02]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x03]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x04]
+
+v_sub_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x05]
+
+v_sub_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6a,0x01,0x06,0x06,0x0e]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x00]
+
+v_sub_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x6b,0x01,0xe4,0x00,0x00]
+
+v_sub_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0xff,0xe4,0x00,0x00]
+
+v_sub_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x6a,0x01,0xe4,0x00,0x00]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x40,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x41,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x42,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x43,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x30,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x34,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x38,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x3c,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x01,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x0f,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x11,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x1f,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x21,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0x2f,0x01,0x00]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x10]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x30]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xf0]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0xf0]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x01]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x03]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x0f]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x00,0x0f]
+
+v_sub_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x6a,0x01,0xe4,0x08,0x00]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v255, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xfe,0x6d,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v255, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0xff,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, s1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, s101, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x65,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, flat_scratch_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x66,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, flat_scratch_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x67,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x6a,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x6b,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, ttmp15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x7b,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, m0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x7c,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, exec_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x7e,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, exec_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x7f,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, 0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x80,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, -1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0xc1,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, 0.5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0xf0,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, -4.0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0xf7,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, src_vccz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0xfb,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, src_execz, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0xfc,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, src_scc, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0xfd,0x06,0x86,0x06]
+
+v_subrev_u32_sdwa v5, v1, v255 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x0b,0x6c,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 clamp dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x26,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x00,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x01,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:BYTE_2 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x02,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x03,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x04,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x05,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_SEXT src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x0e,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x16,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x16,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x00,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x01,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x02,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x03,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x04,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x05,0x06]
+
+v_subrev_u32_sdwa v5, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x0e,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x06]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x00]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x01]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x02]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x03]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x04]
+
+v_subrev_u32_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x05]
+
+v_subrev_u32_sdwa v5, v1, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x0a,0x6c,0x01,0x06,0x06,0x0e]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x00]
+
+v_subrev_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0xfe,0x6d,0x01,0xe4,0x00,0x00]
+
+v_subrev_u32_dpp v5, v255, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0xff,0xe4,0x00,0x00]
+
+v_subrev_u32_dpp v5, v1, v255 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0xfe,0x0b,0x6c,0x01,0xe4,0x00,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x40,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x41,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_bcast:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x42,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_bcast:31 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x43,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 wave_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x30,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 wave_rol:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x34,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 wave_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x38,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 wave_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x3c,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_shl:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x01,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_shl:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x0f,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_shr:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x11,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_shr:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x1f,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_ror:1 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x21,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 row_ror:15 row_mask:0x0 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0x2f,0x01,0x00]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x1 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x10]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x3 bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x30]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xf0]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] bank_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0xf0]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x1
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x01]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x3
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x03]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0xf
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x0f]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x00,0x0f]
+
+v_subrev_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
+// CHECK: [0xfa,0x04,0x0a,0x6c,0x01,0xe4,0x08,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
new file mode 100644
index 0000000000000..ab5b827cda866
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop3.s
@@ -0,0 +1,37702 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+v_interp_p1_f32_e64 v5, v2, attr0.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v255, v2, attr0.x
+// CHECK: [0xff,0x00,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr1.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x01,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr31.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr32.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x20,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v255, attr0.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0xfe,0x03,0x00]
+
+v_interp_p1_f32_e64 v5, -v2, attr0.x
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p1_f32_e64 v5, |v2|, attr0.x
+// CHECK: [0x05,0x02,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.y
+// CHECK: [0x05,0x00,0x70,0xd2,0x40,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.z
+// CHECK: [0x05,0x00,0x70,0xd2,0x80,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.w
+// CHECK: [0x05,0x00,0x70,0xd2,0xc0,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x clamp
+// CHECK: [0x05,0x80,0x70,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:2
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x08]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x mul:4
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x10]
+
+v_interp_p1_f32_e64 v5, v2, attr0.x div:2
+// CHECK: [0x05,0x00,0x70,0xd2,0x00,0x04,0x02,0x18]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v255, v2, attr0.x
+// CHECK: [0xff,0x00,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr1.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x01,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr31.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr32.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x20,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v255, attr0.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0xfe,0x03,0x00]
+
+v_interp_p2_f32_e64 v5, -v2, attr0.x
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p2_f32_e64 v5, |v2|, attr0.x
+// CHECK: [0x05,0x02,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.y
+// CHECK: [0x05,0x00,0x71,0xd2,0x40,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.z
+// CHECK: [0x05,0x00,0x71,0xd2,0x80,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.w
+// CHECK: [0x05,0x00,0x71,0xd2,0xc0,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x clamp
+// CHECK: [0x05,0x80,0x71,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x mul:2
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x08]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x mul:4
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x10]
+
+v_interp_p2_f32_e64 v5, v2, attr0.x div:2
+// CHECK: [0x05,0x00,0x71,0xd2,0x00,0x04,0x02,0x18]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v255, p10, attr0.x
+// CHECK: [0xff,0x00,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr1.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x01,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr31.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x1f,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr32.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x20,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p20, attr0.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x02,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p0, attr0.x
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x04,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.y
+// CHECK: [0x05,0x00,0x72,0xd2,0x40,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.z
+// CHECK: [0x05,0x00,0x72,0xd2,0x80,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.w
+// CHECK: [0x05,0x00,0x72,0xd2,0xc0,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x clamp
+// CHECK: [0x05,0x80,0x72,0xd2,0x00,0x00,0x00,0x00]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:2
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x08]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x mul:4
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x10]
+
+v_interp_mov_f32_e64 v5, p10, attr0.x div:2
+// CHECK: [0x05,0x00,0x72,0xd2,0x00,0x00,0x00,0x18]
+
+v_nop_e64
+// CHECK: [0x00,0x00,0x40,0xd1,0x00,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x41,0xd1,0x01,0x01,0x00,0x00]
+
+v_mov_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x41,0xd1,0x01,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x41,0xd1,0xff,0x01,0x00,0x00]
+
+v_mov_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x41,0xd1,0x01,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, s101
+// CHECK: [0x05,0x00,0x41,0xd1,0x65,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x41,0xd1,0x66,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x41,0xd1,0x67,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x41,0xd1,0x6a,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x41,0xd1,0x6b,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x41,0xd1,0x7b,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x41,0xd1,0x7c,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x41,0xd1,0x7e,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x41,0xd1,0x7f,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x41,0xd1,0x80,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x41,0xd1,0xc1,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x41,0xd1,0xf0,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x41,0xd1,0xf7,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x41,0xd1,0xfb,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x41,0xd1,0xfc,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x41,0xd1,0xfd,0x00,0x00,0x00]
+
+v_mov_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x41,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x43,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x43,0xd1,0xfe,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x43,0xd1,0x02,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x43,0xd1,0x04,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, s[100:101]
+// CHECK: [0x05,0x00,0x43,0xd1,0x64,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x43,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x43,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, ttmp[14:15]
+// CHECK: [0x05,0x00,0x43,0xd1,0x7a,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x43,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x43,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x43,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x43,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x43,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x43,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x43,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x43,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x43,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_i32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x43,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f64_e64 v5, v[1:2] clamp
+// CHECK: [0x05,0x80,0x43,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[254:255], v1
+// CHECK: [0xfe,0x00,0x44,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v255
+// CHECK: [0x05,0x00,0x44,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s1
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], s101
+// CHECK: [0x05,0x00,0x44,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], flat_scratch_lo
+// CHECK: [0x05,0x00,0x44,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], flat_scratch_hi
+// CHECK: [0x05,0x00,0x44,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_lo
+// CHECK: [0x05,0x00,0x44,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], vcc_hi
+// CHECK: [0x05,0x00,0x44,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], ttmp15
+// CHECK: [0x05,0x00,0x44,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], m0
+// CHECK: [0x05,0x00,0x44,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_lo
+// CHECK: [0x05,0x00,0x44,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], exec_hi
+// CHECK: [0x05,0x00,0x44,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x44,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x44,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x44,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x44,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x44,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x44,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x44,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], src_lds_direct
+// CHECK: [0x05,0x00,0x44,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1 clamp
+// CHECK: [0x05,0x80,0x44,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_i32_e64 v[5:6], v1 mul:2
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_i32_e64 v[5:6], v1 mul:4
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_i32_e64 v[5:6], v1 div:2
+// CHECK: [0x05,0x00,0x44,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_i32_e64 v5, v1
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v255, v1
+// CHECK: [0xff,0x00,0x45,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v255
+// CHECK: [0x05,0x00,0x45,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s1
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, s101
+// CHECK: [0x05,0x00,0x45,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x45,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x45,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x45,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x45,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x45,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, m0
+// CHECK: [0x05,0x00,0x45,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x45,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x45,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, 0
+// CHECK: [0x05,0x00,0x45,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, -1
+// CHECK: [0x05,0x00,0x45,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x45,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x45,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x45,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x45,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x45,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x45,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x45,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_i32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_i32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_i32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x45,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_u32_e64 v5, v1
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v255, v1
+// CHECK: [0xff,0x00,0x46,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v255
+// CHECK: [0x05,0x00,0x46,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s1
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, s101
+// CHECK: [0x05,0x00,0x46,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x46,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x46,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x46,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x46,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x46,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, m0
+// CHECK: [0x05,0x00,0x46,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x46,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x46,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, 0
+// CHECK: [0x05,0x00,0x46,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, -1
+// CHECK: [0x05,0x00,0x46,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x46,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x46,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x46,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x46,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x46,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x46,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x46,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_u32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_u32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_u32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x46,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_u32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x47,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x47,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x47,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x47,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x47,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x47,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x47,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x47,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x47,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x47,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x47,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x47,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x47,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x47,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x47,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x47,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x47,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x47,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x47,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x47,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_u32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x47,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x47,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x48,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x48,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x48,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x48,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x48,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x48,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x48,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x48,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x48,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x48,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x48,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x48,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x48,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x48,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x48,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x48,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x48,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x48,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x48,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x48,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x48,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i32_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x48,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x4a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x4a,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x4a,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4a,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4a,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4a,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x4a,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x4a,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4a,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x4a,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x4a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4a,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4a,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4a,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_f16_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x4a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f16_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f16_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x4a,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x4b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x4b,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x4b,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4b,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4b,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x4b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x4b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x4b,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x4b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_f32_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x4b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f16_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_f16_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_f16_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x4b,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_rpi_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x4c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x4c,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x4c,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4c,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4c,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x4c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x4c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x4c,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x4c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_rpi_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4c,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_rpi_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x4d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x4d,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x4d,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4d,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4d,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4d,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4d,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x4d,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x4d,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4d,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4d,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x4d,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x4d,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4d,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4d,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4d,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4d,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4d,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4d,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_flr_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x4d,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_flr_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x4d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v255, v1
+// CHECK: [0xff,0x00,0x4e,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v255
+// CHECK: [0x05,0x00,0x4e,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s1
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, s101
+// CHECK: [0x05,0x00,0x4e,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x4e,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x4e,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x4e,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x4e,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x4e,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, m0
+// CHECK: [0x05,0x00,0x4e,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x4e,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x4e,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, 0
+// CHECK: [0x05,0x00,0x4e,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, -1
+// CHECK: [0x05,0x00,0x4e,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4e,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4e,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4e,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4e,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4e,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x4e,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x4e,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_off_f32_i4_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_off_f32_i4_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_off_f32_i4_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x4e,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x4f,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x4f,0xd1,0xfe,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x02,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x04,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, s[100:101]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x64,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x4f,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x4f,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, ttmp[14:15]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x7a,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x4f,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x4f,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x4f,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x4f,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x4f,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x4f,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x4f,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x4f,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_f32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x4f,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[1:2] clamp
+// CHECK: [0x05,0x80,0x4f,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_f64_e64 v5, v[1:2] mul:2
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_f64_e64 v5, v[1:2] mul:4
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_f64_e64 v5, v[1:2] div:2
+// CHECK: [0x05,0x00,0x4f,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f64_f32_e64 v[5:6], v1
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[254:255], v1
+// CHECK: [0xfe,0x00,0x50,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v255
+// CHECK: [0x05,0x00,0x50,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s1
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], s101
+// CHECK: [0x05,0x00,0x50,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], flat_scratch_lo
+// CHECK: [0x05,0x00,0x50,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], flat_scratch_hi
+// CHECK: [0x05,0x00,0x50,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_lo
+// CHECK: [0x05,0x00,0x50,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], vcc_hi
+// CHECK: [0x05,0x00,0x50,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], ttmp15
+// CHECK: [0x05,0x00,0x50,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], m0
+// CHECK: [0x05,0x00,0x50,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_lo
+// CHECK: [0x05,0x00,0x50,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], exec_hi
+// CHECK: [0x05,0x00,0x50,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x50,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x50,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x50,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x50,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x50,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x50,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x50,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], src_lds_direct
+// CHECK: [0x05,0x00,0x50,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], -v1
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_f64_f32_e64 v[5:6], |v1|
+// CHECK: [0x05,0x01,0x50,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v1 clamp
+// CHECK: [0x05,0x80,0x50,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_f32_e64 v[5:6], v1 mul:2
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_f32_e64 v[5:6], v1 mul:4
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_f32_e64 v[5:6], v1 div:2
+// CHECK: [0x05,0x00,0x50,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte0_e64 v5, v1
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v255, v1
+// CHECK: [0xff,0x00,0x51,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v255
+// CHECK: [0x05,0x00,0x51,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s1
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, s101
+// CHECK: [0x05,0x00,0x51,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x51,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x51,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x51,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x51,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x51,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, m0
+// CHECK: [0x05,0x00,0x51,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x51,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x51,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, 0
+// CHECK: [0x05,0x00,0x51,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, -1
+// CHECK: [0x05,0x00,0x51,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x51,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x51,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x51,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x51,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x51,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x51,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x51,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte0_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte0_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte0_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x51,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte1_e64 v5, v1
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v255, v1
+// CHECK: [0xff,0x00,0x52,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v255
+// CHECK: [0x05,0x00,0x52,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s1
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, s101
+// CHECK: [0x05,0x00,0x52,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x52,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x52,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x52,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x52,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x52,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, m0
+// CHECK: [0x05,0x00,0x52,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x52,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x52,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, 0
+// CHECK: [0x05,0x00,0x52,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, -1
+// CHECK: [0x05,0x00,0x52,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x52,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x52,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x52,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x52,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x52,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x52,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x52,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte1_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte1_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte1_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x52,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte2_e64 v5, v1
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v255, v1
+// CHECK: [0xff,0x00,0x53,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v255
+// CHECK: [0x05,0x00,0x53,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s1
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, s101
+// CHECK: [0x05,0x00,0x53,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x53,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x53,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x53,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x53,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x53,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, m0
+// CHECK: [0x05,0x00,0x53,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x53,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x53,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, 0
+// CHECK: [0x05,0x00,0x53,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, -1
+// CHECK: [0x05,0x00,0x53,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x53,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x53,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x53,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x53,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x53,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x53,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x53,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte2_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte2_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte2_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x53,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_f32_ubyte3_e64 v5, v1
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v255, v1
+// CHECK: [0xff,0x00,0x54,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v255
+// CHECK: [0x05,0x00,0x54,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s1
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, s101
+// CHECK: [0x05,0x00,0x54,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x54,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x54,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x54,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x54,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x54,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, m0
+// CHECK: [0x05,0x00,0x54,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x54,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x54,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, 0
+// CHECK: [0x05,0x00,0x54,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, -1
+// CHECK: [0x05,0x00,0x54,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x54,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x54,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x54,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x54,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x54,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x54,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x54,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f32_ubyte3_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f32_ubyte3_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f32_ubyte3_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x54,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_u32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x55,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x55,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x55,0xd1,0xfe,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x55,0xd1,0x02,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x55,0xd1,0x04,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, s[100:101]
+// CHECK: [0x05,0x00,0x55,0xd1,0x64,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x55,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x55,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, ttmp[14:15]
+// CHECK: [0x05,0x00,0x55,0xd1,0x7a,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x55,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x55,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x55,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x55,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x55,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x55,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x55,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x55,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x55,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_u32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x55,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u32_f64_e64 v5, v[1:2] clamp
+// CHECK: [0x05,0x80,0x55,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[254:255], v1
+// CHECK: [0xfe,0x00,0x56,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v255
+// CHECK: [0x05,0x00,0x56,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s1
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], s101
+// CHECK: [0x05,0x00,0x56,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], flat_scratch_lo
+// CHECK: [0x05,0x00,0x56,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], flat_scratch_hi
+// CHECK: [0x05,0x00,0x56,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_lo
+// CHECK: [0x05,0x00,0x56,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], vcc_hi
+// CHECK: [0x05,0x00,0x56,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], ttmp15
+// CHECK: [0x05,0x00,0x56,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], m0
+// CHECK: [0x05,0x00,0x56,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_lo
+// CHECK: [0x05,0x00,0x56,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], exec_hi
+// CHECK: [0x05,0x00,0x56,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x56,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x56,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x56,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x56,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x56,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x56,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x56,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], src_lds_direct
+// CHECK: [0x05,0x00,0x56,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1 clamp
+// CHECK: [0x05,0x80,0x56,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f64_u32_e64 v[5:6], v1 mul:2
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x08]
+
+v_cvt_f64_u32_e64 v[5:6], v1 mul:4
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x10]
+
+v_cvt_f64_u32_e64 v[5:6], v1 div:2
+// CHECK: [0x05,0x00,0x56,0xd1,0x01,0x01,0x00,0x18]
+
+v_trunc_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x57,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x57,0xd1,0xfe,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x57,0xd1,0x02,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x57,0xd1,0x04,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x57,0xd1,0x64,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x57,0xd1,0x66,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x57,0xd1,0x6a,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], ttmp[14:15]
+// CHECK: [0x05,0x00,0x57,0xd1,0x7a,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x57,0xd1,0x7e,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x57,0xd1,0x80,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x57,0xd1,0xc1,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x57,0xd1,0xf0,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x57,0xd1,0xf7,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x57,0xd1,0xfb,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x57,0xd1,0xfc,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x57,0xd1,0xfd,0x00,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x20]
+
+v_trunc_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x57,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x57,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x08]
+
+v_trunc_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x10]
+
+v_trunc_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x57,0xd1,0x01,0x01,0x00,0x18]
+
+v_ceil_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x58,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x58,0xd1,0xfe,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x58,0xd1,0x02,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x58,0xd1,0x04,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x58,0xd1,0x64,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x58,0xd1,0x66,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x58,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], ttmp[14:15]
+// CHECK: [0x05,0x00,0x58,0xd1,0x7a,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x58,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x58,0xd1,0x80,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x58,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x58,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x58,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x58,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x58,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x58,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x20]
+
+v_ceil_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x58,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x58,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x08]
+
+v_ceil_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x10]
+
+v_ceil_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x58,0xd1,0x01,0x01,0x00,0x18]
+
+v_rndne_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x59,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x59,0xd1,0xfe,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x59,0xd1,0x02,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x59,0xd1,0x04,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x59,0xd1,0x64,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x59,0xd1,0x66,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x59,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], ttmp[14:15]
+// CHECK: [0x05,0x00,0x59,0xd1,0x7a,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x59,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x59,0xd1,0x80,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x59,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x59,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x59,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x59,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x59,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x59,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x20]
+
+v_rndne_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x59,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x59,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x08]
+
+v_rndne_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x10]
+
+v_rndne_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x59,0xd1,0x01,0x01,0x00,0x18]
+
+v_floor_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x5a,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x5a,0xd1,0xfe,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x02,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x04,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x64,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x5a,0xd1,0x66,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x5a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], ttmp[14:15]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x7a,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x5a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x5a,0xd1,0x80,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x5a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x5a,0xd1,0xf0,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x5a,0xd1,0xf7,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x5a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x5a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x5a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x20]
+
+v_floor_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x5a,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x5a,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x08]
+
+v_floor_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x10]
+
+v_floor_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x5a,0xd1,0x01,0x01,0x00,0x18]
+
+v_fract_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5b,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5b,0xd1,0xff,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5b,0xd1,0x65,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5b,0xd1,0x66,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5b,0xd1,0x67,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x5b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5b,0xd1,0x80,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_fract_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x20]
+
+v_fract_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5b,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5b,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x08]
+
+v_fract_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x10]
+
+v_fract_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5b,0xd1,0x01,0x01,0x00,0x18]
+
+v_trunc_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5c,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5c,0xd1,0xff,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5c,0xd1,0x65,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5c,0xd1,0x66,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5c,0xd1,0x67,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x5c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5c,0xd1,0x80,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_trunc_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x20]
+
+v_trunc_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5c,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5c,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x08]
+
+v_trunc_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x10]
+
+v_trunc_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5c,0xd1,0x01,0x01,0x00,0x18]
+
+v_ceil_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5d,0xd1,0xff,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5d,0xd1,0x65,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5d,0xd1,0x66,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5d,0xd1,0x67,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5d,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5d,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x5d,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5d,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5d,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5d,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5d,0xd1,0x80,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5d,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5d,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5d,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5d,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5d,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5d,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ceil_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x20]
+
+v_ceil_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x08]
+
+v_ceil_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x10]
+
+v_ceil_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5d,0xd1,0x01,0x01,0x00,0x18]
+
+v_rndne_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5e,0xd1,0xff,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5e,0xd1,0x65,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5e,0xd1,0x66,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5e,0xd1,0x67,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5e,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5e,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x5e,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5e,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5e,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5e,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5e,0xd1,0x80,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5e,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5e,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5e,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5e,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5e,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5e,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5e,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rndne_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x20]
+
+v_rndne_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x08]
+
+v_rndne_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x10]
+
+v_rndne_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5e,0xd1,0x01,0x01,0x00,0x18]
+
+v_floor_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x5f,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x5f,0xd1,0xff,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x5f,0xd1,0x65,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x5f,0xd1,0x66,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x5f,0xd1,0x67,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x5f,0xd1,0x6a,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x5f,0xd1,0x6b,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x5f,0xd1,0x7b,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x5f,0xd1,0x7c,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x5f,0xd1,0x7e,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x5f,0xd1,0x7f,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x5f,0xd1,0x80,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x5f,0xd1,0xc1,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x5f,0xd1,0xf0,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x5f,0xd1,0xf7,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x5f,0xd1,0xfb,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x5f,0xd1,0xfc,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x5f,0xd1,0xfd,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x5f,0xd1,0xfe,0x00,0x00,0x00]
+
+v_floor_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x20]
+
+v_floor_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x5f,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x5f,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x08]
+
+v_floor_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x10]
+
+v_floor_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x5f,0xd1,0x01,0x01,0x00,0x18]
+
+v_exp_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x60,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x60,0xd1,0xff,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x60,0xd1,0x65,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x60,0xd1,0x66,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x60,0xd1,0x67,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x60,0xd1,0x6a,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x60,0xd1,0x6b,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x60,0xd1,0x7b,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x60,0xd1,0x7c,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x60,0xd1,0x7e,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x60,0xd1,0x7f,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x60,0xd1,0x80,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x60,0xd1,0xc1,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x60,0xd1,0xf0,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x60,0xd1,0xf7,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x60,0xd1,0xfb,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x60,0xd1,0xfc,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x60,0xd1,0xfd,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x60,0xd1,0xfe,0x00,0x00,0x00]
+
+v_exp_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x20]
+
+v_exp_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x60,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x60,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x08]
+
+v_exp_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x10]
+
+v_exp_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x60,0xd1,0x01,0x01,0x00,0x18]
+
+v_log_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x61,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x61,0xd1,0xff,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x61,0xd1,0x65,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x61,0xd1,0x66,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x61,0xd1,0x67,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x61,0xd1,0x6a,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x61,0xd1,0x6b,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x61,0xd1,0x7b,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x61,0xd1,0x7c,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x61,0xd1,0x7e,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x61,0xd1,0x7f,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x61,0xd1,0x80,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x61,0xd1,0xc1,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x61,0xd1,0xf0,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x61,0xd1,0xf7,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x61,0xd1,0xfb,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x61,0xd1,0xfc,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x61,0xd1,0xfd,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x61,0xd1,0xfe,0x00,0x00,0x00]
+
+v_log_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x20]
+
+v_log_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x61,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x61,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x08]
+
+v_log_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x10]
+
+v_log_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x61,0xd1,0x01,0x01,0x00,0x18]
+
+v_rcp_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x62,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x62,0xd1,0xff,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x62,0xd1,0x65,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x62,0xd1,0x66,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x62,0xd1,0x67,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x62,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x62,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x62,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x62,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x62,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x62,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x62,0xd1,0x80,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x62,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x62,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x62,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x62,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x62,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x62,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x62,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rcp_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x20]
+
+v_rcp_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x62,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x62,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x08]
+
+v_rcp_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x10]
+
+v_rcp_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x62,0xd1,0x01,0x01,0x00,0x18]
+
+v_rcp_iflag_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x63,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x63,0xd1,0xff,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x63,0xd1,0x65,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x63,0xd1,0x66,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x63,0xd1,0x67,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x63,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x63,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x63,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x63,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x63,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x63,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x63,0xd1,0x80,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x63,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x63,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x63,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x63,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x63,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x63,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x63,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x20]
+
+v_rcp_iflag_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x63,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x63,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_iflag_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x08]
+
+v_rcp_iflag_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x10]
+
+v_rcp_iflag_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x63,0xd1,0x01,0x01,0x00,0x18]
+
+v_rsq_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x64,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x64,0xd1,0xff,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x64,0xd1,0x65,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x64,0xd1,0x66,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x64,0xd1,0x67,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x64,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x64,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x64,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x64,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x64,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x64,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x64,0xd1,0x80,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x64,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x64,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x64,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x64,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x64,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x64,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x64,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rsq_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x20]
+
+v_rsq_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x64,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x64,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x08]
+
+v_rsq_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x10]
+
+v_rsq_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x64,0xd1,0x01,0x01,0x00,0x18]
+
+v_rcp_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x65,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x65,0xd1,0xfe,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x65,0xd1,0x02,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x65,0xd1,0x04,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x65,0xd1,0x64,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x65,0xd1,0x66,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x65,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], ttmp[14:15]
+// CHECK: [0x05,0x00,0x65,0xd1,0x7a,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x65,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x65,0xd1,0x80,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x65,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x65,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x65,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x65,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x65,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x65,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x20]
+
+v_rcp_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x65,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x65,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x08]
+
+v_rcp_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x10]
+
+v_rcp_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x65,0xd1,0x01,0x01,0x00,0x18]
+
+v_rsq_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x66,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x66,0xd1,0xfe,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x66,0xd1,0x02,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x66,0xd1,0x04,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x66,0xd1,0x64,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x66,0xd1,0x66,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x66,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], ttmp[14:15]
+// CHECK: [0x05,0x00,0x66,0xd1,0x7a,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x66,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x66,0xd1,0x80,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x66,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x66,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x66,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x66,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x66,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x66,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x20]
+
+v_rsq_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x66,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x66,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x08]
+
+v_rsq_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x10]
+
+v_rsq_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x66,0xd1,0x01,0x01,0x00,0x18]
+
+v_sqrt_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x67,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x67,0xd1,0xff,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x67,0xd1,0x65,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x67,0xd1,0x66,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x67,0xd1,0x67,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x67,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x67,0xd1,0x6b,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x67,0xd1,0x7b,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x67,0xd1,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x67,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x67,0xd1,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x67,0xd1,0x80,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x67,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x67,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x67,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x67,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x67,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x67,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x67,0xd1,0xfe,0x00,0x00,0x00]
+
+v_sqrt_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x20]
+
+v_sqrt_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x67,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x67,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x08]
+
+v_sqrt_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x10]
+
+v_sqrt_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x67,0xd1,0x01,0x01,0x00,0x18]
+
+v_sqrt_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x68,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x68,0xd1,0xfe,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x68,0xd1,0x02,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x68,0xd1,0x04,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x68,0xd1,0x64,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x68,0xd1,0x66,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x68,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], ttmp[14:15]
+// CHECK: [0x05,0x00,0x68,0xd1,0x7a,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x68,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x68,0xd1,0x80,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x68,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x68,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x68,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x68,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x68,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x68,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x20]
+
+v_sqrt_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x68,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x68,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x08]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x10]
+
+v_sqrt_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x68,0xd1,0x01,0x01,0x00,0x18]
+
+v_sin_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x69,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x69,0xd1,0xff,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x69,0xd1,0x65,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x69,0xd1,0x66,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x69,0xd1,0x67,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x69,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x69,0xd1,0x6b,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x69,0xd1,0x7b,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x69,0xd1,0x7c,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x69,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x69,0xd1,0x7f,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x69,0xd1,0x80,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x69,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x69,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x69,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x69,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x69,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x69,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x69,0xd1,0xfe,0x00,0x00,0x00]
+
+v_sin_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x20]
+
+v_sin_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x69,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x69,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x08]
+
+v_sin_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x10]
+
+v_sin_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x69,0xd1,0x01,0x01,0x00,0x18]
+
+v_cos_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6a,0xd1,0xff,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6a,0xd1,0x65,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6a,0xd1,0x66,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6a,0xd1,0x67,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6a,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x6a,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6a,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6a,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6a,0xd1,0x80,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6a,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6a,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6a,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cos_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x20]
+
+v_cos_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x6a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x6a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x08]
+
+v_cos_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x10]
+
+v_cos_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x6a,0xd1,0x01,0x01,0x00,0x18]
+
+v_not_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
+
+v_not_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6b,0xd1,0x01,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6b,0xd1,0xff,0x01,0x00,0x00]
+
+v_not_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6b,0xd1,0x01,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6b,0xd1,0x65,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6b,0xd1,0x66,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6b,0xd1,0x67,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x6b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6b,0xd1,0x80,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_not_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6c,0xd1,0x01,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6c,0xd1,0x01,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6c,0xd1,0xff,0x01,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6c,0xd1,0x01,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6c,0xd1,0x65,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6c,0xd1,0x66,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6c,0xd1,0x67,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x6c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6c,0xd1,0x80,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_bfrev_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6d,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6d,0xd1,0xff,0x01,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6d,0xd1,0x01,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6d,0xd1,0x65,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6d,0xd1,0x66,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6d,0xd1,0x67,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6d,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6d,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x6d,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6d,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6d,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6d,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6d,0xd1,0x80,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6d,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6d,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6d,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6d,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6d,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6d,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ffbh_u32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6d,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6e,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6e,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6e,0xd1,0xff,0x01,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6e,0xd1,0x01,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6e,0xd1,0x65,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6e,0xd1,0x66,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6e,0xd1,0x67,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6e,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6e,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x6e,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6e,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6e,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6e,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6e,0xd1,0x80,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6e,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6e,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6e,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6e,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6e,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6e,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ffbl_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6e,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, v1
+// CHECK: [0x05,0x00,0x6f,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v255, v1
+// CHECK: [0xff,0x00,0x6f,0xd1,0x01,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, v255
+// CHECK: [0x05,0x00,0x6f,0xd1,0xff,0x01,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s1
+// CHECK: [0x05,0x00,0x6f,0xd1,0x01,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, s101
+// CHECK: [0x05,0x00,0x6f,0xd1,0x65,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x6f,0xd1,0x66,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x6f,0xd1,0x67,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x6f,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x6f,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x6f,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, m0
+// CHECK: [0x05,0x00,0x6f,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x6f,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x6f,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, 0
+// CHECK: [0x05,0x00,0x6f,0xd1,0x80,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, -1
+// CHECK: [0x05,0x00,0x6f,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x6f,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x6f,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x6f,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x6f,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x6f,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ffbh_i32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x6f,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, v[1:2]
+// CHECK: [0x05,0x00,0x70,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v255, v[1:2]
+// CHECK: [0xff,0x00,0x70,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, v[254:255]
+// CHECK: [0x05,0x00,0x70,0xd1,0xfe,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[2:3]
+// CHECK: [0x05,0x00,0x70,0xd1,0x02,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[4:5]
+// CHECK: [0x05,0x00,0x70,0xd1,0x04,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, s[100:101]
+// CHECK: [0x05,0x00,0x70,0xd1,0x64,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, flat_scratch
+// CHECK: [0x05,0x00,0x70,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, vcc
+// CHECK: [0x05,0x00,0x70,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, ttmp[14:15]
+// CHECK: [0x05,0x00,0x70,0xd1,0x7a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, exec
+// CHECK: [0x05,0x00,0x70,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, 0
+// CHECK: [0x05,0x00,0x70,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -1
+// CHECK: [0x05,0x00,0x70,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x70,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x70,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x70,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x70,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x70,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f64_e64 v5, -v[1:2]
+// CHECK: [0x05,0x00,0x70,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i32_f64_e64 v5, |v[1:2]|
+// CHECK: [0x05,0x01,0x70,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x71,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x71,0xd1,0xfe,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x71,0xd1,0x02,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x71,0xd1,0x04,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x71,0xd1,0x64,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x71,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x71,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], ttmp[14:15]
+// CHECK: [0x05,0x00,0x71,0xd1,0x7a,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x71,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x71,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x71,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x71,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x71,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x71,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x71,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x71,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x71,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x71,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x08]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x10]
+
+v_frexp_mant_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x71,0xd1,0x01,0x01,0x00,0x18]
+
+v_fract_f64_e64 v[5:6], v[1:2]
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[254:255], v[1:2]
+// CHECK: [0xfe,0x00,0x72,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[254:255]
+// CHECK: [0x05,0x00,0x72,0xd1,0xfe,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[2:3]
+// CHECK: [0x05,0x00,0x72,0xd1,0x02,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[4:5]
+// CHECK: [0x05,0x00,0x72,0xd1,0x04,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], s[100:101]
+// CHECK: [0x05,0x00,0x72,0xd1,0x64,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], flat_scratch
+// CHECK: [0x05,0x00,0x72,0xd1,0x66,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], vcc
+// CHECK: [0x05,0x00,0x72,0xd1,0x6a,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], ttmp[14:15]
+// CHECK: [0x05,0x00,0x72,0xd1,0x7a,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], exec
+// CHECK: [0x05,0x00,0x72,0xd1,0x7e,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], 0
+// CHECK: [0x05,0x00,0x72,0xd1,0x80,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -1
+// CHECK: [0x05,0x00,0x72,0xd1,0xc1,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], 0.5
+// CHECK: [0x05,0x00,0x72,0xd1,0xf0,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -4.0
+// CHECK: [0x05,0x00,0x72,0xd1,0xf7,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], src_vccz
+// CHECK: [0x05,0x00,0x72,0xd1,0xfb,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], src_execz
+// CHECK: [0x05,0x00,0x72,0xd1,0xfc,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], src_scc
+// CHECK: [0x05,0x00,0x72,0xd1,0xfd,0x00,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], -v[1:2]
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x20]
+
+v_fract_f64_e64 v[5:6], |v[1:2]|
+// CHECK: [0x05,0x01,0x72,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[1:2] clamp
+// CHECK: [0x05,0x80,0x72,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f64_e64 v[5:6], v[1:2] mul:2
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x08]
+
+v_fract_f64_e64 v[5:6], v[1:2] mul:4
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x10]
+
+v_fract_f64_e64 v[5:6], v[1:2] div:2
+// CHECK: [0x05,0x00,0x72,0xd1,0x01,0x01,0x00,0x18]
+
+v_frexp_exp_i32_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x73,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x73,0xd1,0xff,0x01,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x73,0xd1,0x65,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x73,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x73,0xd1,0x67,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x73,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x73,0xd1,0x6b,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x73,0xd1,0x7b,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x73,0xd1,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x73,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x73,0xd1,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x73,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x73,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x73,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x73,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x73,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x73,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x73,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x73,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_exp_i32_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x73,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i32_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x73,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x74,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x74,0xd1,0xff,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x74,0xd1,0x65,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x74,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x74,0xd1,0x67,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x74,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x74,0xd1,0x6b,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x74,0xd1,0x7b,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x74,0xd1,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x74,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x74,0xd1,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x74,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x74,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x74,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x74,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x74,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x74,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x74,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x74,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x74,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x74,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x08]
+
+v_frexp_mant_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x10]
+
+v_frexp_mant_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x74,0xd1,0x01,0x01,0x00,0x18]
+
+v_clrexcp_e64
+// CHECK: [0x00,0x00,0x75,0xd1,0x00,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, v1
+// CHECK: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v255, v1
+// CHECK: [0xff,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, v255
+// CHECK: [0x05,0x00,0x77,0xd1,0xff,0x01,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, s1
+// CHECK: [0x05,0x00,0x77,0xd1,0x01,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, s101
+// CHECK: [0x05,0x00,0x77,0xd1,0x65,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x77,0xd1,0x66,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x77,0xd1,0x67,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x77,0xd1,0x6a,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x77,0xd1,0x6b,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x77,0xd1,0x7b,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, m0
+// CHECK: [0x05,0x00,0x77,0xd1,0x7c,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x77,0xd1,0x7e,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x77,0xd1,0x7f,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, 0
+// CHECK: [0x05,0x00,0x77,0xd1,0x80,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, -1
+// CHECK: [0x05,0x00,0x77,0xd1,0xc1,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x77,0xd1,0xf0,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x77,0xd1,0xf7,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x77,0xd1,0xfb,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x77,0xd1,0xfc,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x77,0xd1,0xfd,0x00,0x00,0x00]
+
+v_screen_partition_4se_b32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x77,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v1
+// CHECK: [0x05,0x00,0x79,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v255, v1
+// CHECK: [0xff,0x00,0x79,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v255
+// CHECK: [0x05,0x00,0x79,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, s1
+// CHECK: [0x05,0x00,0x79,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, s101
+// CHECK: [0x05,0x00,0x79,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x79,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x79,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x79,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x79,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x79,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, m0
+// CHECK: [0x05,0x00,0x79,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x79,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x79,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, 0
+// CHECK: [0x05,0x00,0x79,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, -1
+// CHECK: [0x05,0x00,0x79,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x79,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x79,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x79,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x79,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f16_u16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x79,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7a,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7a,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7a,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7a,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7a,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7a,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x7a,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7a,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7a,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7a,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7a,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_f16_i16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7b,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7b,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7b,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7b,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x7b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7b,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7b,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_u16_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_u16_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7b,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7c,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7c,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7c,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7c,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x7c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7c,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7c,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_i16_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7c,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_i16_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7c,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7d,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7d,0xd1,0xff,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7d,0xd1,0x65,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7d,0xd1,0x66,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7d,0xd1,0x67,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7d,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7d,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x7d,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7d,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7d,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7d,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7d,0xd1,0x80,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7d,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7d,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7d,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7d,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7d,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7d,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7d,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rcp_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7d,0xd1,0x01,0x01,0x00,0x20]
+
+v_rcp_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7d,0xd1,0x01,0x01,0x00,0x00]
+
+v_rcp_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7d,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7e,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7e,0xd1,0xff,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7e,0xd1,0x65,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7e,0xd1,0x66,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7e,0xd1,0x67,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7e,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7e,0xd1,0x6b,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x7e,0xd1,0x7b,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7e,0xd1,0x7c,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7e,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7e,0xd1,0x7f,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7e,0xd1,0x80,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7e,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7e,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7e,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7e,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7e,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7e,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7e,0xd1,0xfe,0x00,0x00,0x00]
+
+v_sqrt_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7e,0xd1,0x01,0x01,0x00,0x20]
+
+v_sqrt_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7e,0xd1,0x01,0x01,0x00,0x00]
+
+v_sqrt_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7e,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x7f,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x7f,0xd1,0xff,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x7f,0xd1,0x65,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x7f,0xd1,0x66,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x7f,0xd1,0x67,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x7f,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x7f,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x7f,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x7f,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x7f,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x7f,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x7f,0xd1,0x80,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x7f,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x7f,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x7f,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x7f,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x7f,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x7f,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x7f,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rsq_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x7f,0xd1,0x01,0x01,0x00,0x20]
+
+v_rsq_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x7f,0xd1,0x01,0x01,0x00,0x00]
+
+v_rsq_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x7f,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x80,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x80,0xd1,0xff,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x80,0xd1,0x65,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x80,0xd1,0x66,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x80,0xd1,0x67,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x80,0xd1,0x6a,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x80,0xd1,0x6b,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x80,0xd1,0x7b,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x80,0xd1,0x7c,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x80,0xd1,0x7e,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x80,0xd1,0x7f,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x80,0xd1,0x80,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x80,0xd1,0xc1,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x80,0xd1,0xf0,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x80,0xd1,0xf7,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x80,0xd1,0xfb,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x80,0xd1,0xfc,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x80,0xd1,0xfd,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x80,0xd1,0xfe,0x00,0x00,0x00]
+
+v_log_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x80,0xd1,0x01,0x01,0x00,0x20]
+
+v_log_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x80,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x80,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x81,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x81,0xd1,0xff,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x81,0xd1,0x65,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x81,0xd1,0x66,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x81,0xd1,0x67,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x81,0xd1,0x6a,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x81,0xd1,0x6b,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x81,0xd1,0x7b,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x81,0xd1,0x7c,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x81,0xd1,0x7e,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x81,0xd1,0x7f,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x81,0xd1,0x80,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x81,0xd1,0xc1,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x81,0xd1,0xf0,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x81,0xd1,0xf7,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x81,0xd1,0xfb,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x81,0xd1,0xfc,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x81,0xd1,0xfd,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x81,0xd1,0xfe,0x00,0x00,0x00]
+
+v_exp_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x81,0xd1,0x01,0x01,0x00,0x20]
+
+v_exp_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x81,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x81,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x82,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x82,0xd1,0xff,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x82,0xd1,0x65,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x82,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x82,0xd1,0x67,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x82,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x82,0xd1,0x6b,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x82,0xd1,0x7b,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x82,0xd1,0x7c,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x82,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x82,0xd1,0x7f,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x82,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x82,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x82,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x82,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x82,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x82,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x82,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x82,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x82,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_mant_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x82,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_mant_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x82,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x83,0xd1,0x01,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x83,0xd1,0xff,0x01,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x83,0xd1,0x65,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x83,0xd1,0x66,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x83,0xd1,0x67,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x83,0xd1,0x6a,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x83,0xd1,0x6b,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x83,0xd1,0x7b,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x83,0xd1,0x7c,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x83,0xd1,0x7e,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x83,0xd1,0x7f,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x83,0xd1,0x80,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x83,0xd1,0xc1,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x83,0xd1,0xf0,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x83,0xd1,0xf7,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x83,0xd1,0xfb,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x83,0xd1,0xfc,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x83,0xd1,0xfd,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x83,0xd1,0xfe,0x00,0x00,0x00]
+
+v_frexp_exp_i16_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x83,0xd1,0x01,0x01,0x00,0x20]
+
+v_frexp_exp_i16_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x83,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x84,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x84,0xd1,0xff,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x84,0xd1,0x65,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x84,0xd1,0x66,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x84,0xd1,0x67,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x84,0xd1,0x6a,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x84,0xd1,0x6b,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x84,0xd1,0x7b,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x84,0xd1,0x7c,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x84,0xd1,0x7e,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x84,0xd1,0x7f,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x84,0xd1,0x80,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x84,0xd1,0xc1,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x84,0xd1,0xf0,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x84,0xd1,0xf7,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x84,0xd1,0xfb,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x84,0xd1,0xfc,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x84,0xd1,0xfd,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x84,0xd1,0xfe,0x00,0x00,0x00]
+
+v_floor_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x84,0xd1,0x01,0x01,0x00,0x20]
+
+v_floor_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x84,0xd1,0x01,0x01,0x00,0x00]
+
+v_floor_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x84,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x85,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x85,0xd1,0xff,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x85,0xd1,0x65,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x85,0xd1,0x66,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x85,0xd1,0x67,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x85,0xd1,0x6a,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x85,0xd1,0x6b,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x85,0xd1,0x7b,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x85,0xd1,0x7c,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x85,0xd1,0x7e,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x85,0xd1,0x7f,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x85,0xd1,0x80,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x85,0xd1,0xc1,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x85,0xd1,0xf0,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x85,0xd1,0xf7,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x85,0xd1,0xfb,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x85,0xd1,0xfc,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x85,0xd1,0xfd,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x85,0xd1,0xfe,0x00,0x00,0x00]
+
+v_ceil_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x85,0xd1,0x01,0x01,0x00,0x20]
+
+v_ceil_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x85,0xd1,0x01,0x01,0x00,0x00]
+
+v_ceil_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x85,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x86,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x86,0xd1,0xff,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x86,0xd1,0x65,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x86,0xd1,0x66,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x86,0xd1,0x67,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x86,0xd1,0x6a,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x86,0xd1,0x6b,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x86,0xd1,0x7b,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x86,0xd1,0x7c,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x86,0xd1,0x7e,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x86,0xd1,0x7f,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x86,0xd1,0x80,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x86,0xd1,0xc1,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x86,0xd1,0xf0,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x86,0xd1,0xf7,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x86,0xd1,0xfb,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x86,0xd1,0xfc,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x86,0xd1,0xfd,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x86,0xd1,0xfe,0x00,0x00,0x00]
+
+v_trunc_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x86,0xd1,0x01,0x01,0x00,0x20]
+
+v_trunc_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x86,0xd1,0x01,0x01,0x00,0x00]
+
+v_trunc_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x86,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x87,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x87,0xd1,0xff,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x87,0xd1,0x65,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x87,0xd1,0x66,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x87,0xd1,0x67,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x87,0xd1,0x6a,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x87,0xd1,0x6b,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x87,0xd1,0x7b,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x87,0xd1,0x7c,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x87,0xd1,0x7e,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x87,0xd1,0x7f,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x87,0xd1,0x80,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x87,0xd1,0xc1,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x87,0xd1,0xf0,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x87,0xd1,0xf7,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x87,0xd1,0xfb,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x87,0xd1,0xfc,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x87,0xd1,0xfd,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x87,0xd1,0xfe,0x00,0x00,0x00]
+
+v_rndne_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x87,0xd1,0x01,0x01,0x00,0x20]
+
+v_rndne_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x87,0xd1,0x01,0x01,0x00,0x00]
+
+v_rndne_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x87,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x88,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x88,0xd1,0xff,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x88,0xd1,0x65,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x88,0xd1,0x66,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x88,0xd1,0x67,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x88,0xd1,0x6a,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x88,0xd1,0x6b,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x88,0xd1,0x7b,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x88,0xd1,0x7c,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x88,0xd1,0x7e,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x88,0xd1,0x7f,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x88,0xd1,0x80,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x88,0xd1,0xc1,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x88,0xd1,0xf0,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x88,0xd1,0xf7,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x88,0xd1,0xfb,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x88,0xd1,0xfc,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x88,0xd1,0xfd,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x88,0xd1,0xfe,0x00,0x00,0x00]
+
+v_fract_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x88,0xd1,0x01,0x01,0x00,0x20]
+
+v_fract_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x88,0xd1,0x01,0x01,0x00,0x00]
+
+v_fract_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x88,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x89,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x89,0xd1,0xff,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x89,0xd1,0x65,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x89,0xd1,0x66,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x89,0xd1,0x67,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x89,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x89,0xd1,0x6b,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x89,0xd1,0x7b,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x89,0xd1,0x7c,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x89,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x89,0xd1,0x7f,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x89,0xd1,0x80,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x89,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x89,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x89,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x89,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x89,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x89,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x89,0xd1,0xfe,0x00,0x00,0x00]
+
+v_sin_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x89,0xd1,0x01,0x01,0x00,0x20]
+
+v_sin_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x89,0xd1,0x01,0x01,0x00,0x00]
+
+v_sin_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x89,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x8a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x8a,0xd1,0xff,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x8a,0xd1,0x65,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8a,0xd1,0x66,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8a,0xd1,0x67,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8a,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8a,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x8a,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x8a,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8a,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8a,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x8a,0xd1,0x80,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x8a,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8a,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8a,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8a,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8a,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8a,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8a,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cos_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8a,0xd1,0x01,0x01,0x00,0x20]
+
+v_cos_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8a,0xd1,0x01,0x01,0x00,0x00]
+
+v_cos_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x8a,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x8b,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x8b,0xd1,0xff,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x8b,0xd1,0x65,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8b,0xd1,0x66,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8b,0xd1,0x67,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8b,0xd1,0x6a,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8b,0xd1,0x6b,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x8b,0xd1,0x7b,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x8b,0xd1,0x7c,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8b,0xd1,0x7e,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8b,0xd1,0x7f,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x8b,0xd1,0x80,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x8b,0xd1,0xc1,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8b,0xd1,0xf0,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8b,0xd1,0xf7,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8b,0xd1,0xfb,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8b,0xd1,0xfc,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8b,0xd1,0xfd,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8b,0xd1,0xfe,0x00,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x20]
+
+v_exp_legacy_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8b,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x8b,0xd1,0x01,0x01,0x00,0x00]
+
+v_exp_legacy_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x08]
+
+v_exp_legacy_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x10]
+
+v_exp_legacy_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x8b,0xd1,0x01,0x01,0x00,0x18]
+
+v_log_legacy_f32_e64 v5, v1
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v255, v1
+// CHECK: [0xff,0x00,0x8c,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v255
+// CHECK: [0x05,0x00,0x8c,0xd1,0xff,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, s1
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, s101
+// CHECK: [0x05,0x00,0x8c,0xd1,0x65,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8c,0xd1,0x66,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8c,0xd1,0x67,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8c,0xd1,0x6a,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8c,0xd1,0x6b,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x8c,0xd1,0x7b,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, m0
+// CHECK: [0x05,0x00,0x8c,0xd1,0x7c,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8c,0xd1,0x7e,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8c,0xd1,0x7f,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, 0
+// CHECK: [0x05,0x00,0x8c,0xd1,0x80,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, -1
+// CHECK: [0x05,0x00,0x8c,0xd1,0xc1,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8c,0xd1,0xf0,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8c,0xd1,0xf7,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8c,0xd1,0xfb,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8c,0xd1,0xfc,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8c,0xd1,0xfd,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8c,0xd1,0xfe,0x00,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x20]
+
+v_log_legacy_f32_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8c,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x8c,0xd1,0x01,0x01,0x00,0x00]
+
+v_log_legacy_f32_e64 v5, v1 mul:2
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x08]
+
+v_log_legacy_f32_e64 v5, v1 mul:4
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x10]
+
+v_log_legacy_f32_e64 v5, v1 div:2
+// CHECK: [0x05,0x00,0x8c,0xd1,0x01,0x01,0x00,0x18]
+
+v_cvt_norm_i16_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x8d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x8d,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x8d,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x8d,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8d,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8d,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8d,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8d,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x8d,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x8d,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8d,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8d,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x8d,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x8d,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8d,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8d,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8d,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8d,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8d,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8d,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8d,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_norm_i16_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_i16_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x8d,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, v1
+// CHECK: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v255, v1
+// CHECK: [0xff,0x00,0x8e,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, v255
+// CHECK: [0x05,0x00,0x8e,0xd1,0xff,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, s1
+// CHECK: [0x05,0x00,0x8e,0xd1,0x01,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, s101
+// CHECK: [0x05,0x00,0x8e,0xd1,0x65,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8e,0xd1,0x66,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8e,0xd1,0x67,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8e,0xd1,0x6a,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8e,0xd1,0x6b,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x8e,0xd1,0x7b,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, m0
+// CHECK: [0x05,0x00,0x8e,0xd1,0x7c,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8e,0xd1,0x7e,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8e,0xd1,0x7f,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, 0
+// CHECK: [0x05,0x00,0x8e,0xd1,0x80,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, -1
+// CHECK: [0x05,0x00,0x8e,0xd1,0xc1,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8e,0xd1,0xf0,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8e,0xd1,0xf7,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8e,0xd1,0xfb,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8e,0xd1,0xfc,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8e,0xd1,0xfd,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8e,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, -v1
+// CHECK: [0x05,0x00,0x8e,0xd1,0x01,0x01,0x00,0x20]
+
+v_cvt_norm_u16_f16_e64 v5, |v1|
+// CHECK: [0x05,0x01,0x8e,0xd1,0x01,0x01,0x00,0x00]
+
+v_cvt_norm_u16_f16_e64 v5, v1 clamp
+// CHECK: [0x05,0x80,0x8e,0xd1,0x01,0x01,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, v1
+// CHECK: [0x05,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v255, v1
+// CHECK: [0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, v255
+// CHECK: [0x05,0x00,0x8f,0xd1,0xff,0x01,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, s1
+// CHECK: [0x05,0x00,0x8f,0xd1,0x01,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, s101
+// CHECK: [0x05,0x00,0x8f,0xd1,0x65,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8f,0xd1,0x66,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8f,0xd1,0x67,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, vcc_lo
+// CHECK: [0x05,0x00,0x8f,0xd1,0x6a,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, vcc_hi
+// CHECK: [0x05,0x00,0x8f,0xd1,0x6b,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, ttmp15
+// CHECK: [0x05,0x00,0x8f,0xd1,0x7b,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, m0
+// CHECK: [0x05,0x00,0x8f,0xd1,0x7c,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, exec_lo
+// CHECK: [0x05,0x00,0x8f,0xd1,0x7e,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, exec_hi
+// CHECK: [0x05,0x00,0x8f,0xd1,0x7f,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, 0
+// CHECK: [0x05,0x00,0x8f,0xd1,0x80,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, -1
+// CHECK: [0x05,0x00,0x8f,0xd1,0xc1,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, 0.5
+// CHECK: [0x05,0x00,0x8f,0xd1,0xf0,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, -4.0
+// CHECK: [0x05,0x00,0x8f,0xd1,0xf7,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, src_vccz
+// CHECK: [0x05,0x00,0x8f,0xd1,0xfb,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, src_execz
+// CHECK: [0x05,0x00,0x8f,0xd1,0xfc,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, src_scc
+// CHECK: [0x05,0x00,0x8f,0xd1,0xfd,0x00,0x00,0x00]
+
+v_sat_pk_u8_i16_e64 v5, src_lds_direct
+// CHECK: [0x05,0x00,0x8f,0xd1,0xfe,0x00,0x00,0x00]
+
+v_cndmask_b32_e64 v5, v1, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x1a,0x00]
+
+v_cndmask_b32_e64 v255, v1, v2, s[6:7]
+// CHECK: [0xff,0x00,0x00,0xd1,0x01,0x05,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, v255, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xff,0x05,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, 0, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x80,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, -1, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xc1,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, 0.5, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xf0,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, -4.0, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xf7,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, src_lds_direct, v2, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0xfe,0x04,0x1a,0x00]
+
+v_cndmask_b32_e64 v5, v1, v255, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xff,0x1b,0x00]
+
+v_cndmask_b32_e64 v5, v1, 0, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x01,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, -1, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x83,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, 0.5, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xe1,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, -4.0, s[6:7]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0xef,0x19,0x00]
+
+v_cndmask_b32_e64 v5, v1, v2, s[8:9]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x22,0x00]
+
+v_cndmask_b32_e64 v5, v1, v2, s[100:101]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x92,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, flat_scratch
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, vcc
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cndmask_b32_e64 v5, v1, v2, ttmp[14:15]
+// CHECK: [0x05,0x00,0x00,0xd1,0x01,0x05,0xea,0x01]
+
+v_add_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xff,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x65,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x66,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x67,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x6a,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x6b,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x7b,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x7c,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x7e,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x7f,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x80,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xc1,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xf0,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xf7,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xfb,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xfc,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xfd,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0xfe,0x04,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xff,0x03,0x00]
+
+v_add_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x00,0x00]
+
+v_add_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcb,0x00,0x00]
+
+v_add_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcd,0x00,0x00]
+
+v_add_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xcf,0x00,0x00]
+
+v_add_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd5,0x00,0x00]
+
+v_add_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xd7,0x00,0x00]
+
+v_add_f32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf7,0x00,0x00]
+
+v_add_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf9,0x00,0x00]
+
+v_add_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xfd,0x00,0x00]
+
+v_add_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xff,0x00,0x00]
+
+v_add_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x01,0x01,0x00]
+
+v_add_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x83,0x01,0x00]
+
+v_add_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xe1,0x01,0x00]
+
+v_add_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xef,0x01,0x00]
+
+v_add_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf7,0x01,0x00]
+
+v_add_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xf9,0x01,0x00]
+
+v_add_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0xfb,0x01,0x00]
+
+v_add_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x20]
+
+v_add_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x40]
+
+v_add_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x60]
+
+v_add_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x01,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x08]
+
+v_add_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x10]
+
+v_add_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x01,0xd1,0x01,0x05,0x02,0x18]
+
+v_sub_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xff,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x65,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x66,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x67,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x6a,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x6b,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x7b,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x7c,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x7e,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x7f,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x80,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xc1,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xf0,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xf7,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xfb,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xfc,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xfd,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0xfe,0x04,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xff,0x03,0x00]
+
+v_sub_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcb,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcd,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xcf,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd5,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xd7,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf7,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf9,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xfd,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xff,0x00,0x00]
+
+v_sub_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x01,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x83,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xe1,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xef,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf7,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xf9,0x01,0x00]
+
+v_sub_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0xfb,0x01,0x00]
+
+v_sub_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x20]
+
+v_sub_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x40]
+
+v_sub_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x60]
+
+v_sub_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x02,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x08]
+
+v_sub_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x10]
+
+v_sub_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x02,0xd1,0x01,0x05,0x02,0x18]
+
+v_subrev_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xff,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x65,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x66,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x67,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x6a,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x6b,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x7b,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x7c,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x7e,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x7f,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x80,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xc1,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xf0,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xf7,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xfb,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xfc,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0xfd,0x04,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xff,0x03,0x00]
+
+v_subrev_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcb,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcd,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xcf,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd5,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xd7,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf7,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf9,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xfd,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xff,0x00,0x00]
+
+v_subrev_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x01,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x83,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xe1,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xef,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf7,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xf9,0x01,0x00]
+
+v_subrev_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0xfb,0x01,0x00]
+
+v_subrev_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x20]
+
+v_subrev_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x40]
+
+v_subrev_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x60]
+
+v_subrev_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x03,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x08]
+
+v_subrev_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x10]
+
+v_subrev_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x03,0xd1,0x01,0x05,0x02,0x18]
+
+v_mul_legacy_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_legacy_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x20]
+
+v_mul_legacy_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x40]
+
+v_mul_legacy_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x60]
+
+v_mul_legacy_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x04,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_legacy_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x08]
+
+v_mul_legacy_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x10]
+
+v_mul_legacy_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x04,0xd1,0x01,0x05,0x02,0x18]
+
+v_mul_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x20]
+
+v_mul_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x40]
+
+v_mul_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x60]
+
+v_mul_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x05,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x08]
+
+v_mul_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x10]
+
+v_mul_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x05,0xd1,0x01,0x05,0x02,0x18]
+
+v_mul_i32_i24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x06,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_i32_i24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_i32_i24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_i32_i24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x06,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_i32_i24_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x06,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x07,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x07,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_i32_i24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x07,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x08,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_u32_u24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_u32_u24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_u32_u24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x08,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_u32_u24_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x08,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x09,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x09,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_u32_u24_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x09,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xf0,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xf7,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_f32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xe1,0x01,0x00]
+
+v_min_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xef,0x01,0x00]
+
+v_min_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x20]
+
+v_min_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x40]
+
+v_min_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x60]
+
+v_min_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x0a,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x08]
+
+v_min_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x10]
+
+v_min_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x0a,0xd1,0x01,0x05,0x02,0x18]
+
+v_max_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xf0,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xf7,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_f32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xe1,0x01,0x00]
+
+v_max_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xef,0x01,0x00]
+
+v_max_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x20]
+
+v_max_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x40]
+
+v_max_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x60]
+
+v_max_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x0b,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x08]
+
+v_max_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x10]
+
+v_max_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x0b,0xd1,0x01,0x05,0x02,0x18]
+
+v_min_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0c,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xf0,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xf7,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0c,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_i32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_i32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xe1,0x01,0x00]
+
+v_min_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xef,0x01,0x00]
+
+v_min_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0c,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xf0,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xf7,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0d,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_i32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_i32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xe1,0x01,0x00]
+
+v_max_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xef,0x01,0x00]
+
+v_max_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0d,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xf0,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xf7,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0e,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_u32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_u32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xe1,0x01,0x00]
+
+v_min_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xef,0x01,0x00]
+
+v_min_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0e,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x0f,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xf0,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xf7,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x0f,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_u32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_u32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xe1,0x01,0x00]
+
+v_max_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xef,0x01,0x00]
+
+v_max_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x0f,0xd1,0x01,0xfb,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x10,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x65,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x66,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x67,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x7b,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xf0,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xf7,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xfb,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xfc,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x10,0xd1,0xfd,0x04,0x02,0x00]
+
+v_lshrrev_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xff,0x03,0x00]
+
+v_lshrrev_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x05,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcb,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcd,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xcf,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xd7,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf7,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf9,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xff,0x00,0x00]
+
+v_lshrrev_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xe1,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xef,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf7,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xf9,0x01,0x00]
+
+v_lshrrev_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x10,0xd1,0x01,0xfb,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x11,0xd1,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x65,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x66,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x67,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x7b,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xf0,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xf7,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xfb,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xfc,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x11,0xd1,0xfd,0x04,0x02,0x00]
+
+v_ashrrev_i32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xff,0x03,0x00]
+
+v_ashrrev_i32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x05,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcb,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcd,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xcf,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xd7,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf7,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf9,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xff,0x00,0x00]
+
+v_ashrrev_i32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xe1,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xef,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf7,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xf9,0x01,0x00]
+
+v_ashrrev_i32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x11,0xd1,0x01,0xfb,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x12,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x65,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x66,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x67,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x7b,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xf0,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xf7,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xfb,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xfc,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x12,0xd1,0xfd,0x04,0x02,0x00]
+
+v_lshlrev_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xff,0x03,0x00]
+
+v_lshlrev_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x05,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcb,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcd,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xcf,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xd7,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf7,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf9,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xff,0x00,0x00]
+
+v_lshlrev_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xe1,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xef,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf7,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xf9,0x01,0x00]
+
+v_lshlrev_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x12,0xd1,0x01,0xfb,0x01,0x00]
+
+v_and_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x05,0x02,0x00]
+
+v_and_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x13,0xd1,0x01,0x05,0x02,0x00]
+
+v_and_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xff,0x05,0x02,0x00]
+
+v_and_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x65,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x66,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x67,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x6a,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x6b,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x7b,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x7c,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x7e,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x7f,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0x80,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xc1,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xf0,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xf7,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xfb,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xfc,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xfd,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x13,0xd1,0xfe,0x04,0x02,0x00]
+
+v_and_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xff,0x03,0x00]
+
+v_and_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x05,0x00,0x00]
+
+v_and_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcb,0x00,0x00]
+
+v_and_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcd,0x00,0x00]
+
+v_and_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xcf,0x00,0x00]
+
+v_and_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd5,0x00,0x00]
+
+v_and_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xd7,0x00,0x00]
+
+v_and_b32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf7,0x00,0x00]
+
+v_and_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf9,0x00,0x00]
+
+v_and_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xfd,0x00,0x00]
+
+v_and_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xff,0x00,0x00]
+
+v_and_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x01,0x01,0x00]
+
+v_and_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0x83,0x01,0x00]
+
+v_and_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xe1,0x01,0x00]
+
+v_and_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xef,0x01,0x00]
+
+v_and_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf7,0x01,0x00]
+
+v_and_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xf9,0x01,0x00]
+
+v_and_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x13,0xd1,0x01,0xfb,0x01,0x00]
+
+v_or_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x05,0x02,0x00]
+
+v_or_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x14,0xd1,0x01,0x05,0x02,0x00]
+
+v_or_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xff,0x05,0x02,0x00]
+
+v_or_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x65,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x66,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x67,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x6a,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x6b,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x7b,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x7c,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x7e,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x7f,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0x80,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xc1,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xf0,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xf7,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xfb,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xfc,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xfd,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x14,0xd1,0xfe,0x04,0x02,0x00]
+
+v_or_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xff,0x03,0x00]
+
+v_or_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x05,0x00,0x00]
+
+v_or_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcb,0x00,0x00]
+
+v_or_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcd,0x00,0x00]
+
+v_or_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xcf,0x00,0x00]
+
+v_or_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd5,0x00,0x00]
+
+v_or_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xd7,0x00,0x00]
+
+v_or_b32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf7,0x00,0x00]
+
+v_or_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf9,0x00,0x00]
+
+v_or_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xfd,0x00,0x00]
+
+v_or_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xff,0x00,0x00]
+
+v_or_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x01,0x01,0x00]
+
+v_or_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0x83,0x01,0x00]
+
+v_or_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xe1,0x01,0x00]
+
+v_or_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xef,0x01,0x00]
+
+v_or_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf7,0x01,0x00]
+
+v_or_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xf9,0x01,0x00]
+
+v_or_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x14,0xd1,0x01,0xfb,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x05,0x02,0x00]
+
+v_xor_b32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x15,0xd1,0x01,0x05,0x02,0x00]
+
+v_xor_b32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xff,0x05,0x02,0x00]
+
+v_xor_b32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x65,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x66,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x67,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x6a,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x6b,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x7b,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x7c,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x7e,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x7f,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0x80,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xc1,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xf0,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xf7,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xfb,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xfc,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xfd,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x15,0xd1,0xfe,0x04,0x02,0x00]
+
+v_xor_b32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xff,0x03,0x00]
+
+v_xor_b32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x05,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcb,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcd,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xcf,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd5,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xd7,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf7,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf9,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xfd,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xff,0x00,0x00]
+
+v_xor_b32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x01,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0x83,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xe1,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xef,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf7,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xf9,0x01,0x00]
+
+v_xor_b32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x15,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xff,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x65,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x66,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x67,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x80,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xff,0x03,0x00]
+
+v_mac_f32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xff,0x00,0x00]
+
+v_mac_f32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x01,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x83,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xef,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mac_f32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mac_f32_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x20]
+
+v_mac_f32_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x40]
+
+v_mac_f32_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x60]
+
+v_mac_f32_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x16,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f32_e64 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x08]
+
+v_mac_f32_e64 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x10]
+
+v_mac_f32_e64 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x16,0xd1,0x01,0x05,0x02,0x18]
+
+v_add_co_u32_e64 v5, s[12:13], v1, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_co_u32_e64 v255, s[12:13], v1, v2
+// CHECK: [0xff,0x0c,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[14:15], v1, v2
+// CHECK: [0x05,0x0e,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[100:101], v1, v2
+// CHECK: [0x05,0x64,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_co_u32_e64 v5, flat_scratch, v1, v2
+// CHECK: [0x05,0x66,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_co_u32_e64 v5, vcc, v1, v2
+// CHECK: [0x05,0x6a,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_co_u32_e64 v5, ttmp[14:15], v1, v2
+// CHECK: [0x05,0x7a,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v255, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xff,0x05,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], s1, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], s101, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x65,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], flat_scratch_lo, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x66,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], flat_scratch_hi, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x67,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], vcc_lo, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x6a,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], vcc_hi, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x6b,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], ttmp15, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x7b,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], m0, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x7c,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], exec_lo, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x7e,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], exec_hi, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x7f,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], 0, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x80,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], -1, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xc1,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], 0.5, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xf0,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], -4.0, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xf7,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], src_vccz, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xfb,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], src_execz, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xfc,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], src_scc, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xfd,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], src_lds_direct, v2
+// CHECK: [0x05,0x0c,0x19,0xd1,0xfe,0x04,0x02,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, v255
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xff,0x03,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, s2
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x05,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, s101
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcb,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, flat_scratch_lo
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcd,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, flat_scratch_hi
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xcf,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, vcc_lo
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd5,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, vcc_hi
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xd7,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, ttmp15
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf7,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, m0
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf9,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, exec_lo
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xfd,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, exec_hi
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xff,0x00,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, 0
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x01,0x01,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, -1
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0x83,0x01,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, 0.5
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xe1,0x01,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, -4.0
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xef,0x01,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, src_vccz
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf7,0x01,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, src_execz
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xf9,0x01,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, src_scc
+// CHECK: [0x05,0x0c,0x19,0xd1,0x01,0xfb,0x01,0x00]
+
+v_add_co_u32_e64 v5, s[12:13], v1, v2 clamp
+// CHECK: [0x05,0x8c,0x19,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_co_u32_e64 v255, s[12:13], v1, v2
+// CHECK: [0xff,0x0c,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[14:15], v1, v2
+// CHECK: [0x05,0x0e,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[100:101], v1, v2
+// CHECK: [0x05,0x64,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_co_u32_e64 v5, flat_scratch, v1, v2
+// CHECK: [0x05,0x66,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_co_u32_e64 v5, vcc, v1, v2
+// CHECK: [0x05,0x6a,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_co_u32_e64 v5, ttmp[14:15], v1, v2
+// CHECK: [0x05,0x7a,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v255, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xff,0x05,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], s1, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], s101, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x65,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], flat_scratch_lo, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x66,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], flat_scratch_hi, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x67,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], vcc_lo, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], vcc_hi, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x6b,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], ttmp15, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x7b,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], m0, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x7c,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], exec_lo, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], exec_hi, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x7f,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], 0, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x80,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], -1, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], 0.5, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xf0,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], -4.0, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xf7,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], src_vccz, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], src_execz, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], src_scc, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], src_lds_direct, v2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0xfe,0x04,0x02,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, v255
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xff,0x03,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, s2
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x05,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, s101
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcb,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, flat_scratch_lo
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcd,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, flat_scratch_hi
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xcf,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, vcc_lo
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, vcc_hi
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xd7,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, ttmp15
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf7,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, m0
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf9,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, exec_lo
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, exec_hi
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xff,0x00,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, 0
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x01,0x01,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, -1
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0x83,0x01,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, 0.5
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xe1,0x01,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, -4.0
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xef,0x01,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, src_vccz
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, src_execz
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, src_scc
+// CHECK: [0x05,0x0c,0x1a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_sub_co_u32_e64 v5, s[12:13], v1, v2 clamp
+// CHECK: [0x05,0x8c,0x1a,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_co_u32_e64 v255, s[12:13], v1, v2
+// CHECK: [0xff,0x0c,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[14:15], v1, v2
+// CHECK: [0x05,0x0e,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[100:101], v1, v2
+// CHECK: [0x05,0x64,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, flat_scratch, v1, v2
+// CHECK: [0x05,0x66,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, vcc, v1, v2
+// CHECK: [0x05,0x6a,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, ttmp[14:15], v1, v2
+// CHECK: [0x05,0x7a,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v255, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xff,0x05,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], s1, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], s101, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x65,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], flat_scratch_lo, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x66,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], flat_scratch_hi, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x67,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], vcc_lo, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x6a,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], vcc_hi, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x6b,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], ttmp15, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x7b,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], m0, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x7c,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], exec_lo, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x7e,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], exec_hi, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x7f,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], 0, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x80,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], -1, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xc1,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], 0.5, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xf0,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], -4.0, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xf7,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], src_vccz, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xfb,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], src_execz, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xfc,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], src_scc, v2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0xfd,0x04,0x02,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, v255
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xff,0x03,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, s2
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x05,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, s101
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcb,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, flat_scratch_lo
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcd,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, flat_scratch_hi
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xcf,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, vcc_lo
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd5,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, vcc_hi
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xd7,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, ttmp15
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf7,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, m0
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf9,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, exec_lo
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xfd,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, exec_hi
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xff,0x00,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, 0
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x01,0x01,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, -1
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0x83,0x01,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, 0.5
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xe1,0x01,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, -4.0
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xef,0x01,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, src_vccz
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf7,0x01,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, src_execz
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xf9,0x01,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, src_scc
+// CHECK: [0x05,0x0c,0x1b,0xd1,0x01,0xfb,0x01,0x00]
+
+v_subrev_co_u32_e64 v5, s[12:13], v1, v2 clamp
+// CHECK: [0x05,0x8c,0x1b,0xd1,0x01,0x05,0x02,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_co_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// CHECK: [0xff,0x0c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x0e,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, s[100:101], v1, v2, s[6:7]
+// CHECK: [0x05,0x64,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
+// CHECK: [0x05,0x66,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, vcc, v1, v2, s[6:7]
+// CHECK: [0x05,0x6a,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, ttmp[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x7a,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xff,0x05,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x80,0x04,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xc1,0x04,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xf0,0x04,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xf7,0x04,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], src_lds_direct, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0xfe,0x04,0x1a,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xff,0x1b,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x01,0x19,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x83,0x19,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xe1,0x19,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0xef,0x19,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x22,0x00]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x92,0x01]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0x9a,0x01]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xaa,0x01]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, v2, ttmp[14:15]
+// CHECK: [0x05,0x0c,0x1c,0xd1,0x01,0x05,0xea,0x01]
+
+v_addc_co_u32_e64 v5, s[12:13], v1, v2, s[6:7] clamp
+// CHECK: [0x05,0x8c,0x1c,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_co_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// CHECK: [0xff,0x0c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x0e,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[100:101], v1, v2, s[6:7]
+// CHECK: [0x05,0x64,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
+// CHECK: [0x05,0x66,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, vcc, v1, v2, s[6:7]
+// CHECK: [0x05,0x6a,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, ttmp[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x7a,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xff,0x05,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x80,0x04,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xc1,0x04,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xf0,0x04,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xf7,0x04,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], src_lds_direct, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0xfe,0x04,0x1a,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xff,0x1b,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x01,0x19,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x83,0x19,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xe1,0x19,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0xef,0x19,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x22,0x00]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x92,0x01]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0x9a,0x01]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xaa,0x01]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, v2, ttmp[14:15]
+// CHECK: [0x05,0x0c,0x1d,0xd1,0x01,0x05,0xea,0x01]
+
+v_subb_co_u32_e64 v5, s[12:13], v1, v2, s[6:7] clamp
+// CHECK: [0x05,0x8c,0x1d,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v255, s[12:13], v1, v2, s[6:7]
+// CHECK: [0xff,0x0c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, s[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x0e,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, s[100:101], v1, v2, s[6:7]
+// CHECK: [0x05,0x64,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, flat_scratch, v1, v2, s[6:7]
+// CHECK: [0x05,0x66,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, vcc, v1, v2, s[6:7]
+// CHECK: [0x05,0x6a,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, ttmp[14:15], v1, v2, s[6:7]
+// CHECK: [0x05,0x7a,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v255, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0xff,0x05,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], 0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x80,0x04,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], -1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0xc1,0x04,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], 0.5, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0xf0,0x04,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], -4.0, v2, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0xf7,0x04,0x1a,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, v255, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xff,0x1b,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, 0, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x01,0x19,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, -1, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x83,0x19,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, 0.5, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xe1,0x19,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, -4.0, s[6:7]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0xef,0x19,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x22,0x00]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x92,0x01]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0x9a,0x01]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xaa,0x01]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, ttmp[14:15]
+// CHECK: [0x05,0x0c,0x1e,0xd1,0x01,0x05,0xea,0x01]
+
+v_subbrev_co_u32_e64 v5, s[12:13], v1, v2, s[6:7] clamp
+// CHECK: [0x05,0x8c,0x1e,0xd1,0x01,0x05,0x1a,0x00]
+
+v_add_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xff,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x65,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x66,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x67,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x6a,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x6b,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x7b,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x7c,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x7e,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x7f,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x80,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xc1,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xf0,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xf7,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xfb,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xfc,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xfd,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0xfe,0x04,0x02,0x00]
+
+v_add_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xff,0x03,0x00]
+
+v_add_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x00,0x00]
+
+v_add_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcb,0x00,0x00]
+
+v_add_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcd,0x00,0x00]
+
+v_add_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xcf,0x00,0x00]
+
+v_add_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd5,0x00,0x00]
+
+v_add_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xd7,0x00,0x00]
+
+v_add_f16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf7,0x00,0x00]
+
+v_add_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf9,0x00,0x00]
+
+v_add_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xfd,0x00,0x00]
+
+v_add_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xff,0x00,0x00]
+
+v_add_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x01,0x01,0x00]
+
+v_add_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x83,0x01,0x00]
+
+v_add_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xe1,0x01,0x00]
+
+v_add_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xef,0x01,0x00]
+
+v_add_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf7,0x01,0x00]
+
+v_add_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xf9,0x01,0x00]
+
+v_add_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0xfb,0x01,0x00]
+
+v_add_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x20]
+
+v_add_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x40]
+
+v_add_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x1f,0xd1,0x01,0x05,0x02,0x60]
+
+v_add_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x1f,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xff,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x65,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x66,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x67,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x6a,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x6b,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x7b,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x7c,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x7e,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x7f,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x80,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xc1,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xf0,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xf7,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xfb,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xfc,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xfd,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0xfe,0x04,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xff,0x03,0x00]
+
+v_sub_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcb,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcd,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xcf,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd5,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xd7,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf7,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf9,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xfd,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xff,0x00,0x00]
+
+v_sub_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x01,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x83,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xe1,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xef,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf7,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xf9,0x01,0x00]
+
+v_sub_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0xfb,0x01,0x00]
+
+v_sub_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x20]
+
+v_sub_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x40]
+
+v_sub_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x20,0xd1,0x01,0x05,0x02,0x60]
+
+v_sub_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x20,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xff,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x65,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x66,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x67,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x6a,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x6b,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x7b,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x7c,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x7e,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x7f,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x80,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xc1,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xf0,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xf7,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xfb,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xfc,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0xfd,0x04,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xff,0x03,0x00]
+
+v_subrev_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcb,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcd,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xcf,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd5,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xd7,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf7,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf9,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xfd,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xff,0x00,0x00]
+
+v_subrev_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x01,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x83,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xe1,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xef,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf7,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xf9,0x01,0x00]
+
+v_subrev_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0xfb,0x01,0x00]
+
+v_subrev_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x20]
+
+v_subrev_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x40]
+
+v_subrev_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x21,0xd1,0x01,0x05,0x02,0x60]
+
+v_subrev_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x21,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xef,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mul_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x20]
+
+v_mul_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x40]
+
+v_mul_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x22,0xd1,0x01,0x05,0x02,0x60]
+
+v_mul_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x22,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xff,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x65,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x66,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x67,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x80,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xf0,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xf7,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mac_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xff,0x03,0x00]
+
+v_mac_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xff,0x00,0x00]
+
+v_mac_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x01,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x83,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xe1,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xef,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mac_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0xfb,0x01,0x00]
+
+v_mac_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x20]
+
+v_mac_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x40]
+
+v_mac_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x23,0xd1,0x01,0x05,0x02,0x60]
+
+v_mac_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_mac_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x23,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xff,0x05,0x02,0x00]
+
+v_add_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x65,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x66,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x67,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x6a,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x6b,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x7b,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x7c,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x7e,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x7f,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0x80,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xc1,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xfb,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xfc,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xfd,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x26,0xd1,0xfe,0x04,0x02,0x00]
+
+v_add_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xff,0x03,0x00]
+
+v_add_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x05,0x00,0x00]
+
+v_add_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcb,0x00,0x00]
+
+v_add_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcd,0x00,0x00]
+
+v_add_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xcf,0x00,0x00]
+
+v_add_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd5,0x00,0x00]
+
+v_add_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xd7,0x00,0x00]
+
+v_add_u16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf7,0x00,0x00]
+
+v_add_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf9,0x00,0x00]
+
+v_add_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xfd,0x00,0x00]
+
+v_add_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xff,0x00,0x00]
+
+v_add_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x01,0x01,0x00]
+
+v_add_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0x83,0x01,0x00]
+
+v_add_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf7,0x01,0x00]
+
+v_add_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xf9,0x01,0x00]
+
+v_add_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x26,0xd1,0x01,0xfb,0x01,0x00]
+
+v_add_u16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x26,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x27,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xff,0x05,0x02,0x00]
+
+v_sub_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x65,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x66,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x67,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x6a,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x6b,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x7b,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x7c,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x7e,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x7f,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0x80,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xc1,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xfb,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xfc,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xfd,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x27,0xd1,0xfe,0x04,0x02,0x00]
+
+v_sub_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x03,0x00]
+
+v_sub_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x05,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcb,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcd,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xcf,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd5,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xd7,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf7,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf9,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xfd,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xff,0x00,0x00]
+
+v_sub_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x01,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0x83,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf7,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xf9,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x27,0xd1,0x01,0xfb,0x01,0x00]
+
+v_sub_u16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x27,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xff,0x05,0x02,0x00]
+
+v_subrev_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x65,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x66,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x67,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x6a,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x6b,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x7b,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x7c,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x7e,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x7f,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0x80,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xc1,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xfb,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xfc,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x28,0xd1,0xfd,0x04,0x02,0x00]
+
+v_subrev_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x03,0x00]
+
+v_subrev_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x05,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcb,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcd,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xcf,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd5,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xd7,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf7,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf9,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xfd,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xff,0x00,0x00]
+
+v_subrev_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x01,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0x83,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf7,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xf9,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x28,0xd1,0x01,0xfb,0x01,0x00]
+
+v_subrev_u16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x28,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x29,0xd1,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xff,0x05,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x65,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x66,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x67,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x7b,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x7c,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x7e,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x7f,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0x80,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xc1,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xfb,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xfc,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xfd,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x29,0xd1,0xfe,0x04,0x02,0x00]
+
+v_mul_lo_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x03,0x00]
+
+v_mul_lo_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x05,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcb,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcd,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xcf,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd5,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xd7,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf7,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf9,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xfd,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xff,0x00,0x00]
+
+v_mul_lo_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x01,0x01,0x00]
+
+v_mul_lo_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0x83,0x01,0x00]
+
+v_mul_lo_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf7,0x01,0x00]
+
+v_mul_lo_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xf9,0x01,0x00]
+
+v_mul_lo_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x29,0xd1,0x01,0xfb,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2a,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x65,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x66,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x67,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x7b,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xfb,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xfc,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2a,0xd1,0xfd,0x04,0x02,0x00]
+
+v_lshlrev_b16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x03,0x00]
+
+v_lshlrev_b16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x05,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcb,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcd,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xcf,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xd7,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf7,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf9,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xff,0x00,0x00]
+
+v_lshlrev_b16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf7,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xf9,0x01,0x00]
+
+v_lshlrev_b16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2a,0xd1,0x01,0xfb,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2b,0xd1,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x65,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x66,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x67,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x7b,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xfb,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xfc,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2b,0xd1,0xfd,0x04,0x02,0x00]
+
+v_lshrrev_b16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x03,0x00]
+
+v_lshrrev_b16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x05,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcb,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcd,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xcf,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xd7,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf7,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf9,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xff,0x00,0x00]
+
+v_lshrrev_b16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf7,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xf9,0x01,0x00]
+
+v_lshrrev_b16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2b,0xd1,0x01,0xfb,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2c,0xd1,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x65,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x66,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x67,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x7b,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xfb,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xfc,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2c,0xd1,0xfd,0x04,0x02,0x00]
+
+v_ashrrev_i16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x03,0x00]
+
+v_ashrrev_i16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x05,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcb,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcd,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xcf,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xd7,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf7,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf9,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xff,0x00,0x00]
+
+v_ashrrev_i16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf7,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xf9,0x01,0x00]
+
+v_ashrrev_i16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2c,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xf0,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xf7,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_f16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xe1,0x01,0x00]
+
+v_max_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xef,0x01,0x00]
+
+v_max_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x20]
+
+v_max_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x40]
+
+v_max_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x2d,0xd1,0x01,0x05,0x02,0x60]
+
+v_max_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x2d,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xf0,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xf7,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_f16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xe1,0x01,0x00]
+
+v_min_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xef,0x01,0x00]
+
+v_min_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x20]
+
+v_min_f16_e64 v5, v1, -v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x40]
+
+v_min_f16_e64 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x2e,0xd1,0x01,0x05,0x02,0x60]
+
+v_min_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x2e,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x2f,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x2f,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_u16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x2f,0xd1,0x01,0xfb,0x01,0x00]
+
+v_max_i16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_i16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x30,0xd1,0x01,0x05,0x02,0x00]
+
+v_max_i16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xff,0x05,0x02,0x00]
+
+v_max_i16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x65,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x66,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x67,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x6a,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x6b,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x7b,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x7c,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x7e,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x7f,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0x80,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xc1,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xfb,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xfc,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xfd,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x30,0xd1,0xfe,0x04,0x02,0x00]
+
+v_max_i16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x03,0x00]
+
+v_max_i16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x05,0x00,0x00]
+
+v_max_i16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcb,0x00,0x00]
+
+v_max_i16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcd,0x00,0x00]
+
+v_max_i16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xcf,0x00,0x00]
+
+v_max_i16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd5,0x00,0x00]
+
+v_max_i16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xd7,0x00,0x00]
+
+v_max_i16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf7,0x00,0x00]
+
+v_max_i16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf9,0x00,0x00]
+
+v_max_i16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xfd,0x00,0x00]
+
+v_max_i16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xff,0x00,0x00]
+
+v_max_i16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x01,0x01,0x00]
+
+v_max_i16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0x83,0x01,0x00]
+
+v_max_i16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf7,0x01,0x00]
+
+v_max_i16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xf9,0x01,0x00]
+
+v_max_i16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x30,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_u16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_u16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x31,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_u16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_u16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x31,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_u16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_u16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_u16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_u16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_u16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_u16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_u16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_u16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_u16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_u16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_u16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_u16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_u16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_u16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_u16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_u16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x31,0xd1,0x01,0xfb,0x01,0x00]
+
+v_min_i16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_i16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x32,0xd1,0x01,0x05,0x02,0x00]
+
+v_min_i16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xff,0x05,0x02,0x00]
+
+v_min_i16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x65,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x66,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x67,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x6a,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x6b,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x7b,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x7c,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x7e,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x7f,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0x80,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xc1,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xfb,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xfc,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xfd,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x32,0xd1,0xfe,0x04,0x02,0x00]
+
+v_min_i16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x03,0x00]
+
+v_min_i16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x05,0x00,0x00]
+
+v_min_i16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcb,0x00,0x00]
+
+v_min_i16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcd,0x00,0x00]
+
+v_min_i16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xcf,0x00,0x00]
+
+v_min_i16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd5,0x00,0x00]
+
+v_min_i16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xd7,0x00,0x00]
+
+v_min_i16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf7,0x00,0x00]
+
+v_min_i16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf9,0x00,0x00]
+
+v_min_i16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xfd,0x00,0x00]
+
+v_min_i16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xff,0x00,0x00]
+
+v_min_i16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x01,0x01,0x00]
+
+v_min_i16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0x83,0x01,0x00]
+
+v_min_i16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf7,0x01,0x00]
+
+v_min_i16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xf9,0x01,0x00]
+
+v_min_i16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x32,0xd1,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x33,0xd1,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xff,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x65,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x66,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x67,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x6b,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x7b,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x7c,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x7f,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x80,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xfb,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xfc,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xfd,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0xfe,0x04,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xff,0x03,0x00]
+
+v_ldexp_f16_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcb,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcd,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf7,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xff,0x00,0x00]
+
+v_ldexp_f16_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x01,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x83,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xef,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf7,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xf9,0x01,0x00]
+
+v_ldexp_f16_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f16_e64 v5, -v1, v2
+// CHECK: [0x05,0x00,0x33,0xd1,0x01,0x05,0x02,0x20]
+
+v_ldexp_f16_e64 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x33,0xd1,0x01,0x05,0x02,0x00]
+
+v_ldexp_f16_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x33,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x34,0xd1,0x01,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0xff,0x05,0x02,0x00]
+
+v_add_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x65,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x66,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x67,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x6a,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x6b,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x7b,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x7c,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x7e,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x7f,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0x80,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0xc1,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0xf0,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0xf7,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0xfb,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0xfc,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0xfd,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x34,0xd1,0xfe,0x04,0x02,0x00]
+
+v_add_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xff,0x03,0x00]
+
+v_add_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x05,0x00,0x00]
+
+v_add_u32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xcb,0x00,0x00]
+
+v_add_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xcd,0x00,0x00]
+
+v_add_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xcf,0x00,0x00]
+
+v_add_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xd5,0x00,0x00]
+
+v_add_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xd7,0x00,0x00]
+
+v_add_u32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xf7,0x00,0x00]
+
+v_add_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xf9,0x00,0x00]
+
+v_add_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xfd,0x00,0x00]
+
+v_add_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xff,0x00,0x00]
+
+v_add_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x01,0x01,0x00]
+
+v_add_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0x83,0x01,0x00]
+
+v_add_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xe1,0x01,0x00]
+
+v_add_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xef,0x01,0x00]
+
+v_add_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xf7,0x01,0x00]
+
+v_add_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xf9,0x01,0x00]
+
+v_add_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x34,0xd1,0x01,0xfb,0x01,0x00]
+
+v_add_u32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x34,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x35,0xd1,0x01,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0xff,0x05,0x02,0x00]
+
+v_sub_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x65,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x66,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x67,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x6a,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x6b,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x7b,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x7c,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x7e,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x7f,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0x80,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0xc1,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0xf0,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0xf7,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0xfb,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0xfc,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0xfd,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x35,0xd1,0xfe,0x04,0x02,0x00]
+
+v_sub_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xff,0x03,0x00]
+
+v_sub_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x05,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xcb,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xcd,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xcf,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xd5,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xd7,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xf7,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xf9,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xfd,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xff,0x00,0x00]
+
+v_sub_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x01,0x01,0x00]
+
+v_sub_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0x83,0x01,0x00]
+
+v_sub_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xe1,0x01,0x00]
+
+v_sub_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xef,0x01,0x00]
+
+v_sub_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xf7,0x01,0x00]
+
+v_sub_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xf9,0x01,0x00]
+
+v_sub_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x35,0xd1,0x01,0xfb,0x01,0x00]
+
+v_sub_u32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x35,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, v1, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v255, v1, v2
+// CHECK: [0xff,0x00,0x36,0xd1,0x01,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, v255, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0xff,0x05,0x02,0x00]
+
+v_subrev_u32_e64 v5, s1, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, s101, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x65,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x66,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x67,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x6a,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x6b,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x7b,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, m0, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x7c,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x7e,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x7f,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, 0, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0x80,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, -1, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0xc1,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0xf0,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0xf7,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0xfb,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0xfc,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x36,0xd1,0xfd,0x04,0x02,0x00]
+
+v_subrev_u32_e64 v5, v1, v255
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xff,0x03,0x00]
+
+v_subrev_u32_e64 v5, v1, s2
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x05,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, s101
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xcb,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xcd,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xcf,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xd5,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xd7,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xf7,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, m0
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xf9,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xfd,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xff,0x00,0x00]
+
+v_subrev_u32_e64 v5, v1, 0
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x01,0x01,0x00]
+
+v_subrev_u32_e64 v5, v1, -1
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0x83,0x01,0x00]
+
+v_subrev_u32_e64 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xe1,0x01,0x00]
+
+v_subrev_u32_e64 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xef,0x01,0x00]
+
+v_subrev_u32_e64 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xf7,0x01,0x00]
+
+v_subrev_u32_e64 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xf9,0x01,0x00]
+
+v_subrev_u32_e64 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x36,0xd1,0x01,0xfb,0x01,0x00]
+
+v_subrev_u32_e64 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x36,0xd1,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_class_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x10,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_class_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x10,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_class_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x11,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_class_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x11,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[12:13], v[1:2], v2
+// CHECK: [0x0c,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[100:101], v[1:2], v2
+// CHECK: [0x64,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 flat_scratch, v[1:2], v2
+// CHECK: [0x66,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 vcc, v[1:2], v2
+// CHECK: [0x6a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 ttmp[14:15], v[1:2], v2
+// CHECK: [0x7a,0x00,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[254:255], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], s[2:3], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], s[4:5], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], s[100:101], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], flat_scratch, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], vcc, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], ttmp[14:15], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], exec, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], v255
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], s101
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], vcc_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], ttmp15
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], m0
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], exec_lo
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], exec_hi
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_class_f64_e64 s[10:11], -v[1:2], v2
+// CHECK: [0x0a,0x00,0x12,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_class_f64_e64 s[10:11], |v[1:2]|, v2
+// CHECK: [0x0a,0x01,0x12,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[12:13], v[1:2], v2
+// CHECK: [0x0c,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[100:101], v[1:2], v2
+// CHECK: [0x64,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 flat_scratch, v[1:2], v2
+// CHECK: [0x66,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 vcc, v[1:2], v2
+// CHECK: [0x6a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 ttmp[14:15], v[1:2], v2
+// CHECK: [0x7a,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 exec, v[1:2], v2
+// CHECK: [0x7e,0x00,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[254:255], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], s[2:3], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], s[4:5], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], s[100:101], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], flat_scratch, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], vcc, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], ttmp[14:15], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], exec, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], v255
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], s2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], s101
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_lo
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], flat_scratch_hi
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_lo
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], vcc_hi
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], ttmp15
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], m0
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_lo
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], exec_hi
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_class_f64_e64 s[10:11], -v[1:2], v2
+// CHECK: [0x0a,0x00,0x13,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_class_f64_e64 s[10:11], |v[1:2]|, v2
+// CHECK: [0x0a,0x01,0x13,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_class_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x14,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_class_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x14,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_class_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x15,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_class_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x15,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_f_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_f_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x20,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_f_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x20,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x21,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x21,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_eq_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_eq_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x22,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_eq_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x22,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_le_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_le_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x23,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_le_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x23,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_gt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_gt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x24,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_gt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x24,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lg_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lg_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x25,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lg_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x25,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ge_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ge_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x26,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ge_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x26,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_o_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_o_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_o_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x27,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_o_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x27,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_u_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_u_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_u_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x28,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_u_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x28,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nge_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nge_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x29,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nge_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x29,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlg_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlg_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ngt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ngt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nle_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nle_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nle_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_neq_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_neq_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_neq_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_tru_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_tru_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x2f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_tru_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x2f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x30,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x30,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x31,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x31,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x32,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x32,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x33,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x33,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x34,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x34,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x35,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x35,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x36,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x36,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x37,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x37,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x38,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x38,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x39,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x39,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f16_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x3f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f16_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f16_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x3f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_f_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_f_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x40,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_f_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x40,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x41,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x41,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_eq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_eq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x42,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_eq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x42,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_le_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_le_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x43,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_le_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x43,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_gt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_gt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x44,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_gt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x44,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x45,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x45,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x46,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x46,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_o_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_o_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_o_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x47,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_o_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x47,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_u_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_u_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_u_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x48,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_u_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x48,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x49,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x49,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ngt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ngt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nle_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nle_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nle_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_neq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_neq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_neq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_tru_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_tru_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x4f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_tru_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x4f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x50,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x50,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x51,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x51,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x52,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x52,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x53,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x53,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x54,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x54,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x55,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x55,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x56,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x56,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x57,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x57,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x58,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x58,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x59,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x59,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], -v1, v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, -v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f32_e64 s[10:11], -v1, -v2
+// CHECK: [0x0a,0x00,0x5f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f32_e64 s[10:11], |v1|, v2
+// CHECK: [0x0a,0x01,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, |v2|
+// CHECK: [0x0a,0x02,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], |v1|, |v2|
+// CHECK: [0x0a,0x03,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f32_e64 s[10:11], v1, v2 clamp
+// CHECK: [0x0a,0x80,0x5f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x60,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_f_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x60,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x61,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x61,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x62,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_eq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x62,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x63,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_le_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x63,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x64,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_gt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x64,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x65,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_lg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x65,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x66,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x66,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_o_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x67,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_o_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x67,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_u_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x68,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_u_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x68,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x69,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x69,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_ngt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nle_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_neq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_nlt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmp_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x6f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmp_tru_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x6f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_f_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x70,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_f_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x70,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x71,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x71,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_eq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x72,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_eq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x72,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_le_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x73,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_le_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x73,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_gt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x74,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_gt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x74,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_lg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x75,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_lg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x75,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x76,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x76,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_o_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x77,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_o_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_o_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x77,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_u_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x78,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_u_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_u_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x78,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nge_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x79,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nge_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nge_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x79,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlg_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7a,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlg_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlg_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7a,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_ngt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7b,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_ngt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ngt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7b,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nle_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7c,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nle_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nle_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7c,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_neq_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7d,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_neq_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_neq_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7d,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_nlt_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7e,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_nlt_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_nlt_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7e,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], -v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x20]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x40]
+
+v_cmpx_tru_f64_e64 s[10:11], -v[1:2], -v[2:3]
+// CHECK: [0x0a,0x00,0x7f,0xd0,0x01,0x05,0x02,0x60]
+
+v_cmpx_tru_f64_e64 s[10:11], |v[1:2]|, v[2:3]
+// CHECK: [0x0a,0x01,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], |v[2:3]|
+// CHECK: [0x0a,0x02,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], |v[1:2]|, |v[2:3]|
+// CHECK: [0x0a,0x03,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_tru_f64_e64 s[10:11], v[1:2], v[2:3] clamp
+// CHECK: [0x0a,0x80,0x7f,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xa9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xa9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xaa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xaa,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xab,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xab,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xab,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xac,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xac,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xac,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xad,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xad,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xad,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xae,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xae,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xae,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xaf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xaf,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_i16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xb9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xb9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xba,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xba,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xba,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xbb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xbc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xbd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbd,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xbe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbe,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xbf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_u16_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xbf,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xc9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xc9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xca,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xca,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xca,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xcb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xcb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xcc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xcc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xcd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xcd,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xce,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xce,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xce,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xcf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xcf,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_i32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xd9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xd9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xda,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xda,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xda,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xdb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xdb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xdc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xdc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xdd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xdd,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xde,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xde,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xde,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[12:13], v1, v2
+// CHECK: [0x0c,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[100:101], v1, v2
+// CHECK: [0x64,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 flat_scratch, v1, v2
+// CHECK: [0x66,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 vcc, v1, v2
+// CHECK: [0x6a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 ttmp[14:15], v1, v2
+// CHECK: [0x7a,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 exec, v1, v2
+// CHECK: [0x7e,0x00,0xdf,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v255, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xff,0x05,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], s1, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], s101, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x65,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], flat_scratch_lo, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], flat_scratch_hi, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x67,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], vcc_lo, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], vcc_hi, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x6b,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], ttmp15, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x7b,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], m0, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x7c,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], exec_lo, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], exec_hi, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x7f,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], 0, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], -1, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], 0.5, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], -4.0, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_vccz, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_execz, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_scc, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], src_lds_direct, v2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0xfe,0x04,0x02,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, v255
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xff,0x03,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, s2
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x05,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, s101
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcb,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_lo
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, flat_scratch_hi
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xcf,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, vcc_lo
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, vcc_hi
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xd7,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, ttmp15
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf7,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, m0
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf9,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, exec_lo
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, exec_hi
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xff,0x00,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, 0
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, -1
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, 0.5
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, -4.0
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, src_vccz
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, src_execz
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_u32_e64 s[10:11], v1, src_scc
+// CHECK: [0x0a,0x00,0xdf,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_f_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xe9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_lt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xe9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xea,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xea,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_eq_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xea,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xeb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_le_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xeb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xec,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xec,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_gt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xec,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xed,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xed,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ne_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xed,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xee,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xee,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_ge_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xee,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xef,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xef,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmp_t_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xef,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf0,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf0,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf1,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf1,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf2,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf2,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf3,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf3,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf4,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf4,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf5,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf5,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf6,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf6,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf7,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_i64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf7,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf8,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_f_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf8,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xf9,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_lt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xf9,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xfa,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_eq_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfa,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xfb,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_le_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfb,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xfc,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_gt_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfc,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xfd,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ne_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfd,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xfe,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_ge_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xfe,0xd0,0x01,0xfb,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[12:13], v[1:2], v[2:3]
+// CHECK: [0x0c,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[100:101], v[1:2], v[2:3]
+// CHECK: [0x64,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 flat_scratch, v[1:2], v[2:3]
+// CHECK: [0x66,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 vcc, v[1:2], v[2:3]
+// CHECK: [0x6a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 ttmp[14:15], v[1:2], v[2:3]
+// CHECK: [0x7a,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 exec, v[1:2], v[2:3]
+// CHECK: [0x7e,0x00,0xff,0xd0,0x01,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[254:255], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xfe,0x05,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], s[2:3], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x02,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], s[4:5], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x04,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], s[100:101], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x64,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], flat_scratch, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x66,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], vcc, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x6a,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], ttmp[14:15], v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x7a,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], exec, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x7e,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], 0, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x80,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], -1, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xc1,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], 0.5, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xf0,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], -4.0, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xf7,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], src_vccz, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xfb,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], src_execz, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xfc,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], src_scc, v[2:3]
+// CHECK: [0x0a,0x00,0xff,0xd0,0xfd,0x04,0x02,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], v[254:255]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfd,0x03,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], s[4:5]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x09,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], s[6:7]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x0d,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], s[100:101]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xc9,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], flat_scratch
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xcd,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], vcc
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xd5,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], ttmp[14:15]
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xf5,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], exec
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfd,0x00,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], 0
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x01,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], -1
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0x83,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], 0.5
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xe1,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], -4.0
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xef,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], src_vccz
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xf7,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], src_execz
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xf9,0x01,0x00]
+
+v_cmpx_t_u64_e64 s[10:11], v[1:2], src_scc
+// CHECK: [0x0a,0x00,0xff,0xd0,0x01,0xfb,0x01,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
new file mode 100644
index 0000000000000..d8fc1e8fce4d3
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop3_e64.s
@@ -0,0 +1,16642 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+v_mad_legacy_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_legacy_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_legacy_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_legacy_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_legacy_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_legacy_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_legacy_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_legacy_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_legacy_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x24]
+
+v_mad_legacy_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_legacy_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x84]
+
+v_mad_legacy_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_mad_legacy_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_mad_legacy_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x14]
+
+v_mad_legacy_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc0,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_mad_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x24]
+
+v_mad_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x84]
+
+v_mad_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_mad_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_mad_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x14]
+
+v_mad_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc1,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_mad_i32_i24 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_i32_i24 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_i32_i24 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_i32_i24 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_i32_i24 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_i32_i24 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_i32_i24 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_i32_i24 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_i32_i24 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_i32_i24 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_i32_i24 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_i32_i24 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_i32_i24 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_i32_i24 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_i32_i24 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_i32_i24 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_i32_i24 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_i32_i24 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_i32_i24 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_i32_i24 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_i32_i24 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_i32_i24 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_i32_i24 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc2,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_i32_i24 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_u32_u24 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_u32_u24 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_u32_u24 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_u32_u24 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_u32_u24 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_u32_u24 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_u32_u24 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_u32_u24 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_u32_u24 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_u32_u24 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_u32_u24 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_u32_u24 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_u32_u24 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_u32_u24 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_u32_u24 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_u32_u24 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_u32_u24 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_u32_u24 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_u32_u24 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_u32_u24 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_u32_u24 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_u32_u24 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc3,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_u32_u24 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cubeid_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cubeid_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cubeid_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cubeid_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cubeid_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x96,0x01]
+
+v_cubeid_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cubeid_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cubeid_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cubeid_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xae,0x01]
+
+v_cubeid_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xee,0x01]
+
+v_cubeid_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cubeid_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cubeid_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cubeid_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x02,0x02]
+
+v_cubeid_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x06,0x03]
+
+v_cubeid_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cubeid_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xde,0x03]
+
+v_cubeid_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xee,0x03]
+
+v_cubeid_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cubeid_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cubeid_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cubeid_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x44]
+
+v_cubeid_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x84]
+
+v_cubeid_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_cubeid_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubeid_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_cubeid_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x14]
+
+v_cubeid_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc4,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_cubesc_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cubesc_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cubesc_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cubesc_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cubesc_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cubesc_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x96,0x01]
+
+v_cubesc_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cubesc_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cubesc_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cubesc_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xae,0x01]
+
+v_cubesc_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xee,0x01]
+
+v_cubesc_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cubesc_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cubesc_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cubesc_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x02,0x02]
+
+v_cubesc_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x06,0x03]
+
+v_cubesc_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cubesc_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xde,0x03]
+
+v_cubesc_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xee,0x03]
+
+v_cubesc_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cubesc_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cubesc_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cubesc_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x44]
+
+v_cubesc_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x84]
+
+v_cubesc_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_cubesc_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubesc_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_cubesc_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x14]
+
+v_cubesc_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc5,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_cubetc_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cubetc_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cubetc_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cubetc_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cubetc_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cubetc_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x96,0x01]
+
+v_cubetc_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cubetc_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cubetc_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cubetc_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xae,0x01]
+
+v_cubetc_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xee,0x01]
+
+v_cubetc_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cubetc_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cubetc_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cubetc_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x02,0x02]
+
+v_cubetc_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x06,0x03]
+
+v_cubetc_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cubetc_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xde,0x03]
+
+v_cubetc_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xee,0x03]
+
+v_cubetc_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cubetc_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cubetc_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cubetc_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x44]
+
+v_cubetc_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x84]
+
+v_cubetc_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_cubetc_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubetc_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_cubetc_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x14]
+
+v_cubetc_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc6,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_cubema_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cubema_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cubema_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cubema_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cubema_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cubema_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cubema_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cubema_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cubema_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cubema_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cubema_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cubema_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cubema_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cubema_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cubema_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cubema_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cubema_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cubema_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cubema_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cubema_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cubema_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x96,0x01]
+
+v_cubema_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cubema_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cubema_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cubema_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xae,0x01]
+
+v_cubema_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xee,0x01]
+
+v_cubema_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cubema_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cubema_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cubema_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x02,0x02]
+
+v_cubema_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x06,0x03]
+
+v_cubema_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cubema_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xde,0x03]
+
+v_cubema_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xee,0x03]
+
+v_cubema_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cubema_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cubema_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cubema_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x44]
+
+v_cubema_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x84]
+
+v_cubema_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_cubema_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xc7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cubema_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_cubema_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x14]
+
+v_cubema_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xc7,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_bfe_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfe_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfe_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xff,0x05,0x0e,0x04]
+
+v_bfe_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x65,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x66,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x67,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x80,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_bfe_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xff,0x0f,0x04]
+
+v_bfe_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0c,0x04]
+
+v_bfe_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_bfe_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_bfe_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_bfe_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_bfe_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_bfe_u32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_bfe_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_bfe_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_bfe_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xff,0x0c,0x04]
+
+v_bfe_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x01,0x0d,0x04]
+
+v_bfe_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x83,0x0d,0x04]
+
+v_bfe_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_bfe_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xef,0x0d,0x04]
+
+v_bfe_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_bfe_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_bfe_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_bfe_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfe,0x07]
+
+v_bfe_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x0e,0x00]
+
+v_bfe_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x96,0x01]
+
+v_bfe_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x9a,0x01]
+
+v_bfe_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x9e,0x01]
+
+v_bfe_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xaa,0x01]
+
+v_bfe_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xae,0x01]
+
+v_bfe_u32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xee,0x01]
+
+v_bfe_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xf2,0x01]
+
+v_bfe_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfa,0x01]
+
+v_bfe_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xfe,0x01]
+
+v_bfe_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x02,0x02]
+
+v_bfe_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0x06,0x03]
+
+v_bfe_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xc2,0x03]
+
+v_bfe_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xde,0x03]
+
+v_bfe_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xee,0x03]
+
+v_bfe_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xf2,0x03]
+
+v_bfe_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc8,0xd1,0x01,0x05,0xf6,0x03]
+
+v_bfe_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfe_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfe_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xff,0x05,0x0e,0x04]
+
+v_bfe_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x65,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x66,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x67,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x80,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_bfe_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xff,0x0f,0x04]
+
+v_bfe_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0c,0x04]
+
+v_bfe_i32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_bfe_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_bfe_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_bfe_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_bfe_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_bfe_i32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_bfe_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_bfe_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_bfe_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xff,0x0c,0x04]
+
+v_bfe_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x01,0x0d,0x04]
+
+v_bfe_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x83,0x0d,0x04]
+
+v_bfe_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_bfe_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xef,0x0d,0x04]
+
+v_bfe_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_bfe_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_bfe_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_bfe_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfe,0x07]
+
+v_bfe_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x0e,0x00]
+
+v_bfe_i32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x96,0x01]
+
+v_bfe_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x9a,0x01]
+
+v_bfe_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x9e,0x01]
+
+v_bfe_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xaa,0x01]
+
+v_bfe_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xae,0x01]
+
+v_bfe_i32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xee,0x01]
+
+v_bfe_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xf2,0x01]
+
+v_bfe_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfa,0x01]
+
+v_bfe_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xfe,0x01]
+
+v_bfe_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x02,0x02]
+
+v_bfe_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0x06,0x03]
+
+v_bfe_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xc2,0x03]
+
+v_bfe_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xde,0x03]
+
+v_bfe_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xee,0x03]
+
+v_bfe_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xf2,0x03]
+
+v_bfe_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xc9,0xd1,0x01,0x05,0xf6,0x03]
+
+v_bfi_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfi_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xca,0xd1,0x01,0x05,0x0e,0x04]
+
+v_bfi_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xff,0x05,0x0e,0x04]
+
+v_bfi_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x65,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x66,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x67,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x80,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_bfi_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xff,0x0f,0x04]
+
+v_bfi_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0c,0x04]
+
+v_bfi_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_bfi_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_bfi_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_bfi_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_bfi_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_bfi_b32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_bfi_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_bfi_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_bfi_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xff,0x0c,0x04]
+
+v_bfi_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x01,0x0d,0x04]
+
+v_bfi_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x83,0x0d,0x04]
+
+v_bfi_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_bfi_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xef,0x0d,0x04]
+
+v_bfi_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_bfi_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_bfi_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_bfi_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfe,0x07]
+
+v_bfi_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x0e,0x00]
+
+v_bfi_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x96,0x01]
+
+v_bfi_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x9a,0x01]
+
+v_bfi_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x9e,0x01]
+
+v_bfi_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xaa,0x01]
+
+v_bfi_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xae,0x01]
+
+v_bfi_b32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xee,0x01]
+
+v_bfi_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xf2,0x01]
+
+v_bfi_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfa,0x01]
+
+v_bfi_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xfe,0x01]
+
+v_bfi_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x02,0x02]
+
+v_bfi_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0x06,0x03]
+
+v_bfi_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xc2,0x03]
+
+v_bfi_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xde,0x03]
+
+v_bfi_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xee,0x03]
+
+v_bfi_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xf2,0x03]
+
+v_bfi_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xca,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xff,0x05,0x0e,0x04]
+
+v_fma_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x04,0x0e,0x04]
+
+v_fma_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x65,0x04,0x0e,0x04]
+
+v_fma_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x66,0x04,0x0e,0x04]
+
+v_fma_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x67,0x04,0x0e,0x04]
+
+v_fma_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_fma_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_fma_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_fma_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_fma_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_fma_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_fma_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x80,0x04,0x0e,0x04]
+
+v_fma_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_fma_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_fma_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_fma_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_fma_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xff,0x0f,0x04]
+
+v_fma_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0c,0x04]
+
+v_fma_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_fma_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_fma_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_fma_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_fma_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_fma_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_fma_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_fma_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_fma_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xff,0x0c,0x04]
+
+v_fma_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x01,0x0d,0x04]
+
+v_fma_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x83,0x0d,0x04]
+
+v_fma_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_fma_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xef,0x0d,0x04]
+
+v_fma_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_fma_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_fma_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_fma_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfe,0x07]
+
+v_fma_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x00]
+
+v_fma_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x96,0x01]
+
+v_fma_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x9a,0x01]
+
+v_fma_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x9e,0x01]
+
+v_fma_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xaa,0x01]
+
+v_fma_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xae,0x01]
+
+v_fma_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xee,0x01]
+
+v_fma_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xf2,0x01]
+
+v_fma_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfa,0x01]
+
+v_fma_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xfe,0x01]
+
+v_fma_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x02,0x02]
+
+v_fma_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x06,0x03]
+
+v_fma_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xc2,0x03]
+
+v_fma_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xde,0x03]
+
+v_fma_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xee,0x03]
+
+v_fma_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xf2,0x03]
+
+v_fma_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x24]
+
+v_fma_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x44]
+
+v_fma_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x84]
+
+v_fma_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_fma_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xcb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_fma_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x14]
+
+v_fma_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xcb,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[2:3], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x02,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[4:5], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x04,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], s[100:101], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x64,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x66,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], ttmp[14:15], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], exec, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x80,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], src_vccz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], src_execz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], src_scc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfd,0x0f,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[4:5], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x09,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[6:7], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x0d,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], s[100:101], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xc9,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], ttmp[14:15], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xf5,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], exec, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_fma_f64 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x01,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x83,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xef,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xfa,0x07]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[6:7]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x1a,0x00]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[8:9]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x22,0x00]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], s[100:101]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x92,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], flat_scratch
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x9a,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xaa,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], ttmp[14:15]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xea,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], exec
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xfa,0x01]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], 0
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x02,0x02]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -1
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x06,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xc2,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xde,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], src_vccz
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xee,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], src_execz
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xf2,0x03]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], src_scc
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x24]
+
+v_fma_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x44]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x84]
+
+v_fma_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_fma_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// CHECK: [0x05,0x01,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// CHECK: [0x05,0x02,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// CHECK: [0x05,0x04,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// CHECK: [0x05,0x07,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// CHECK: [0x05,0x80,0xcc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x14]
+
+v_fma_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// CHECK: [0x05,0x00,0xcc,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_lerp_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_lerp_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_lerp_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xff,0x05,0x0e,0x04]
+
+v_lerp_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x65,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x66,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x67,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x80,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_lerp_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xff,0x0f,0x04]
+
+v_lerp_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0c,0x04]
+
+v_lerp_u8 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_lerp_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_lerp_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_lerp_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_lerp_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_lerp_u8 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_lerp_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_lerp_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_lerp_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xff,0x0c,0x04]
+
+v_lerp_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x01,0x0d,0x04]
+
+v_lerp_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x83,0x0d,0x04]
+
+v_lerp_u8 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_lerp_u8 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xef,0x0d,0x04]
+
+v_lerp_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_lerp_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_lerp_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_lerp_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfe,0x07]
+
+v_lerp_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x0e,0x00]
+
+v_lerp_u8 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x96,0x01]
+
+v_lerp_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x9a,0x01]
+
+v_lerp_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x9e,0x01]
+
+v_lerp_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xaa,0x01]
+
+v_lerp_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xae,0x01]
+
+v_lerp_u8 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xee,0x01]
+
+v_lerp_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xf2,0x01]
+
+v_lerp_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfa,0x01]
+
+v_lerp_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xfe,0x01]
+
+v_lerp_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x02,0x02]
+
+v_lerp_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0x06,0x03]
+
+v_lerp_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xc2,0x03]
+
+v_lerp_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xde,0x03]
+
+v_lerp_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xee,0x03]
+
+v_lerp_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xf2,0x03]
+
+v_lerp_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xcd,0xd1,0x01,0x05,0xf6,0x03]
+
+v_alignbit_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0e,0x04]
+
+v_alignbit_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xce,0xd1,0x01,0x05,0x0e,0x04]
+
+v_alignbit_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xff,0x05,0x0e,0x04]
+
+v_alignbit_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x65,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x66,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x67,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x80,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_alignbit_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xff,0x0f,0x04]
+
+v_alignbit_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xff,0x0c,0x04]
+
+v_alignbit_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x01,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x83,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xef,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_alignbit_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x07]
+
+v_alignbit_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x0e,0x00]
+
+v_alignbit_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x96,0x01]
+
+v_alignbit_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x9a,0x01]
+
+v_alignbit_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x9e,0x01]
+
+v_alignbit_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xaa,0x01]
+
+v_alignbit_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xae,0x01]
+
+v_alignbit_b32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xee,0x01]
+
+v_alignbit_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xf2,0x01]
+
+v_alignbit_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfa,0x01]
+
+v_alignbit_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xfe,0x01]
+
+v_alignbit_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x02,0x02]
+
+v_alignbit_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0x06,0x03]
+
+v_alignbit_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xc2,0x03]
+
+v_alignbit_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xde,0x03]
+
+v_alignbit_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xee,0x03]
+
+v_alignbit_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xf2,0x03]
+
+v_alignbit_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xce,0xd1,0x01,0x05,0xf6,0x03]
+
+v_alignbyte_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xff,0x05,0x0e,0x04]
+
+v_alignbyte_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x65,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x66,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x67,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x80,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_alignbyte_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xff,0x0f,0x04]
+
+v_alignbyte_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xff,0x0c,0x04]
+
+v_alignbyte_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x01,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x83,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xef,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_alignbyte_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x07]
+
+v_alignbyte_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x0e,0x00]
+
+v_alignbyte_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x96,0x01]
+
+v_alignbyte_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x9a,0x01]
+
+v_alignbyte_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x9e,0x01]
+
+v_alignbyte_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xaa,0x01]
+
+v_alignbyte_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xae,0x01]
+
+v_alignbyte_b32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xee,0x01]
+
+v_alignbyte_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xf2,0x01]
+
+v_alignbyte_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfa,0x01]
+
+v_alignbyte_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xfe,0x01]
+
+v_alignbyte_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x02,0x02]
+
+v_alignbyte_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0x06,0x03]
+
+v_alignbyte_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xc2,0x03]
+
+v_alignbyte_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xde,0x03]
+
+v_alignbyte_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xee,0x03]
+
+v_alignbyte_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xf2,0x03]
+
+v_alignbyte_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xcf,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xff,0x05,0x0e,0x04]
+
+v_min3_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x04,0x0e,0x04]
+
+v_min3_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x65,0x04,0x0e,0x04]
+
+v_min3_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x66,0x04,0x0e,0x04]
+
+v_min3_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x67,0x04,0x0e,0x04]
+
+v_min3_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_min3_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_min3_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_min3_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_min3_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_min3_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_min3_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x80,0x04,0x0e,0x04]
+
+v_min3_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_min3_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_min3_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_min3_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_min3_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xff,0x0f,0x04]
+
+v_min3_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0c,0x04]
+
+v_min3_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_min3_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_min3_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_min3_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_min3_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_min3_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_min3_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_min3_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_min3_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xff,0x0c,0x04]
+
+v_min3_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x01,0x0d,0x04]
+
+v_min3_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x83,0x0d,0x04]
+
+v_min3_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_min3_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xef,0x0d,0x04]
+
+v_min3_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_min3_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_min3_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_min3_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfe,0x07]
+
+v_min3_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x00]
+
+v_min3_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x96,0x01]
+
+v_min3_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x9a,0x01]
+
+v_min3_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x9e,0x01]
+
+v_min3_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xaa,0x01]
+
+v_min3_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xae,0x01]
+
+v_min3_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xee,0x01]
+
+v_min3_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xf2,0x01]
+
+v_min3_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfa,0x01]
+
+v_min3_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xfe,0x01]
+
+v_min3_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x02,0x02]
+
+v_min3_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x06,0x03]
+
+v_min3_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xc2,0x03]
+
+v_min3_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xde,0x03]
+
+v_min3_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xee,0x03]
+
+v_min3_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xf2,0x03]
+
+v_min3_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x24]
+
+v_min3_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x44]
+
+v_min3_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x84]
+
+v_min3_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_min3_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xd0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_min3_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x14]
+
+v_min3_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xd0,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_min3_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xff,0x05,0x0e,0x04]
+
+v_min3_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x04,0x0e,0x04]
+
+v_min3_i32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x65,0x04,0x0e,0x04]
+
+v_min3_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x66,0x04,0x0e,0x04]
+
+v_min3_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x67,0x04,0x0e,0x04]
+
+v_min3_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_min3_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_min3_i32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_min3_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_min3_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_min3_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_min3_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x80,0x04,0x0e,0x04]
+
+v_min3_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_min3_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_min3_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_min3_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_min3_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xff,0x0f,0x04]
+
+v_min3_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0c,0x04]
+
+v_min3_i32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_min3_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_min3_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_min3_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_min3_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_min3_i32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_min3_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_min3_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_min3_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xff,0x0c,0x04]
+
+v_min3_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x01,0x0d,0x04]
+
+v_min3_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x83,0x0d,0x04]
+
+v_min3_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_min3_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xef,0x0d,0x04]
+
+v_min3_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_min3_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_min3_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_min3_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfe,0x07]
+
+v_min3_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x0e,0x00]
+
+v_min3_i32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x96,0x01]
+
+v_min3_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x9a,0x01]
+
+v_min3_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x9e,0x01]
+
+v_min3_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xaa,0x01]
+
+v_min3_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xae,0x01]
+
+v_min3_i32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xee,0x01]
+
+v_min3_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xf2,0x01]
+
+v_min3_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfa,0x01]
+
+v_min3_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xfe,0x01]
+
+v_min3_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x02,0x02]
+
+v_min3_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0x06,0x03]
+
+v_min3_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xc2,0x03]
+
+v_min3_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xde,0x03]
+
+v_min3_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xee,0x03]
+
+v_min3_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xf2,0x03]
+
+v_min3_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd1,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xff,0x05,0x0e,0x04]
+
+v_min3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x04,0x0e,0x04]
+
+v_min3_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x65,0x04,0x0e,0x04]
+
+v_min3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x66,0x04,0x0e,0x04]
+
+v_min3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x67,0x04,0x0e,0x04]
+
+v_min3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_min3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_min3_u32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_min3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_min3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_min3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_min3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x80,0x04,0x0e,0x04]
+
+v_min3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_min3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_min3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_min3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_min3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xff,0x0f,0x04]
+
+v_min3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0c,0x04]
+
+v_min3_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_min3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_min3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_min3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_min3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_min3_u32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_min3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_min3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_min3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xff,0x0c,0x04]
+
+v_min3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x01,0x0d,0x04]
+
+v_min3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x83,0x0d,0x04]
+
+v_min3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_min3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xef,0x0d,0x04]
+
+v_min3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_min3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_min3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_min3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfe,0x07]
+
+v_min3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x0e,0x00]
+
+v_min3_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x96,0x01]
+
+v_min3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x9a,0x01]
+
+v_min3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x9e,0x01]
+
+v_min3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xaa,0x01]
+
+v_min3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xae,0x01]
+
+v_min3_u32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xee,0x01]
+
+v_min3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xf2,0x01]
+
+v_min3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfa,0x01]
+
+v_min3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xfe,0x01]
+
+v_min3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x02,0x02]
+
+v_min3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0x06,0x03]
+
+v_min3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xc2,0x03]
+
+v_min3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xde,0x03]
+
+v_min3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xee,0x03]
+
+v_min3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xf2,0x03]
+
+v_min3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd2,0xd1,0x01,0x05,0xf6,0x03]
+
+v_max3_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xff,0x05,0x0e,0x04]
+
+v_max3_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x04,0x0e,0x04]
+
+v_max3_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x65,0x04,0x0e,0x04]
+
+v_max3_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x66,0x04,0x0e,0x04]
+
+v_max3_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x67,0x04,0x0e,0x04]
+
+v_max3_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_max3_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_max3_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_max3_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_max3_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_max3_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_max3_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x80,0x04,0x0e,0x04]
+
+v_max3_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_max3_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_max3_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_max3_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_max3_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xff,0x0f,0x04]
+
+v_max3_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0c,0x04]
+
+v_max3_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_max3_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_max3_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_max3_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_max3_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_max3_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_max3_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_max3_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_max3_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xff,0x0c,0x04]
+
+v_max3_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x01,0x0d,0x04]
+
+v_max3_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x83,0x0d,0x04]
+
+v_max3_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_max3_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xef,0x0d,0x04]
+
+v_max3_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_max3_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_max3_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_max3_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfe,0x07]
+
+v_max3_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x00]
+
+v_max3_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x96,0x01]
+
+v_max3_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x9a,0x01]
+
+v_max3_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x9e,0x01]
+
+v_max3_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xaa,0x01]
+
+v_max3_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xae,0x01]
+
+v_max3_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xee,0x01]
+
+v_max3_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xf2,0x01]
+
+v_max3_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfa,0x01]
+
+v_max3_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xfe,0x01]
+
+v_max3_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x02,0x02]
+
+v_max3_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x06,0x03]
+
+v_max3_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xc2,0x03]
+
+v_max3_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xde,0x03]
+
+v_max3_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xee,0x03]
+
+v_max3_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xf2,0x03]
+
+v_max3_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0xf6,0x03]
+
+v_max3_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x24]
+
+v_max3_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x44]
+
+v_max3_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x84]
+
+v_max3_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_max3_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xd3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_max3_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x14]
+
+v_max3_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xd3,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_max3_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xff,0x05,0x0e,0x04]
+
+v_max3_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x04,0x0e,0x04]
+
+v_max3_i32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x65,0x04,0x0e,0x04]
+
+v_max3_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x66,0x04,0x0e,0x04]
+
+v_max3_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x67,0x04,0x0e,0x04]
+
+v_max3_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_max3_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_max3_i32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_max3_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_max3_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_max3_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_max3_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x80,0x04,0x0e,0x04]
+
+v_max3_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_max3_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_max3_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_max3_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_max3_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xff,0x0f,0x04]
+
+v_max3_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0c,0x04]
+
+v_max3_i32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_max3_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_max3_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_max3_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_max3_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_max3_i32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_max3_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_max3_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_max3_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xff,0x0c,0x04]
+
+v_max3_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x01,0x0d,0x04]
+
+v_max3_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x83,0x0d,0x04]
+
+v_max3_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_max3_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xef,0x0d,0x04]
+
+v_max3_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_max3_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_max3_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_max3_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfe,0x07]
+
+v_max3_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x0e,0x00]
+
+v_max3_i32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x96,0x01]
+
+v_max3_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x9a,0x01]
+
+v_max3_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x9e,0x01]
+
+v_max3_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xaa,0x01]
+
+v_max3_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xae,0x01]
+
+v_max3_i32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xee,0x01]
+
+v_max3_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xf2,0x01]
+
+v_max3_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfa,0x01]
+
+v_max3_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xfe,0x01]
+
+v_max3_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x02,0x02]
+
+v_max3_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0x06,0x03]
+
+v_max3_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xc2,0x03]
+
+v_max3_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xde,0x03]
+
+v_max3_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xee,0x03]
+
+v_max3_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xf2,0x03]
+
+v_max3_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd4,0xd1,0x01,0x05,0xf6,0x03]
+
+v_max3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xff,0x05,0x0e,0x04]
+
+v_max3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x04,0x0e,0x04]
+
+v_max3_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x65,0x04,0x0e,0x04]
+
+v_max3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x66,0x04,0x0e,0x04]
+
+v_max3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x67,0x04,0x0e,0x04]
+
+v_max3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_max3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_max3_u32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_max3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_max3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_max3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_max3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x80,0x04,0x0e,0x04]
+
+v_max3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_max3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_max3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_max3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_max3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xff,0x0f,0x04]
+
+v_max3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0c,0x04]
+
+v_max3_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_max3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_max3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_max3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_max3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_max3_u32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_max3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_max3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_max3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xff,0x0c,0x04]
+
+v_max3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x01,0x0d,0x04]
+
+v_max3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x83,0x0d,0x04]
+
+v_max3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_max3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xef,0x0d,0x04]
+
+v_max3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_max3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_max3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_max3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfe,0x07]
+
+v_max3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x0e,0x00]
+
+v_max3_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x96,0x01]
+
+v_max3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x9a,0x01]
+
+v_max3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x9e,0x01]
+
+v_max3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xaa,0x01]
+
+v_max3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xae,0x01]
+
+v_max3_u32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xee,0x01]
+
+v_max3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xf2,0x01]
+
+v_max3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfa,0x01]
+
+v_max3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xfe,0x01]
+
+v_max3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x02,0x02]
+
+v_max3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0x06,0x03]
+
+v_max3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xc2,0x03]
+
+v_max3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xde,0x03]
+
+v_max3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xee,0x03]
+
+v_max3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xf2,0x03]
+
+v_max3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd5,0xd1,0x01,0x05,0xf6,0x03]
+
+v_med3_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xff,0x05,0x0e,0x04]
+
+v_med3_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x04,0x0e,0x04]
+
+v_med3_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x65,0x04,0x0e,0x04]
+
+v_med3_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x66,0x04,0x0e,0x04]
+
+v_med3_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x67,0x04,0x0e,0x04]
+
+v_med3_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_med3_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_med3_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_med3_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_med3_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_med3_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_med3_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x80,0x04,0x0e,0x04]
+
+v_med3_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_med3_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_med3_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_med3_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_med3_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xff,0x0f,0x04]
+
+v_med3_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0c,0x04]
+
+v_med3_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_med3_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_med3_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_med3_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_med3_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_med3_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_med3_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_med3_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_med3_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xff,0x0c,0x04]
+
+v_med3_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x01,0x0d,0x04]
+
+v_med3_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x83,0x0d,0x04]
+
+v_med3_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_med3_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xef,0x0d,0x04]
+
+v_med3_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_med3_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_med3_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_med3_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfe,0x07]
+
+v_med3_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x00]
+
+v_med3_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x96,0x01]
+
+v_med3_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x9a,0x01]
+
+v_med3_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x9e,0x01]
+
+v_med3_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xaa,0x01]
+
+v_med3_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xae,0x01]
+
+v_med3_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xee,0x01]
+
+v_med3_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xf2,0x01]
+
+v_med3_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfa,0x01]
+
+v_med3_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xfe,0x01]
+
+v_med3_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x02,0x02]
+
+v_med3_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x06,0x03]
+
+v_med3_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xc2,0x03]
+
+v_med3_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xde,0x03]
+
+v_med3_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xee,0x03]
+
+v_med3_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xf2,0x03]
+
+v_med3_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0xf6,0x03]
+
+v_med3_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x24]
+
+v_med3_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x44]
+
+v_med3_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x84]
+
+v_med3_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_med3_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xd6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_med3_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x14]
+
+v_med3_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xd6,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_med3_i32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xff,0x05,0x0e,0x04]
+
+v_med3_i32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x04,0x0e,0x04]
+
+v_med3_i32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x65,0x04,0x0e,0x04]
+
+v_med3_i32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x66,0x04,0x0e,0x04]
+
+v_med3_i32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x67,0x04,0x0e,0x04]
+
+v_med3_i32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_med3_i32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_med3_i32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_med3_i32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_med3_i32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_med3_i32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_med3_i32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x80,0x04,0x0e,0x04]
+
+v_med3_i32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_med3_i32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_med3_i32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_med3_i32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_med3_i32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xff,0x0f,0x04]
+
+v_med3_i32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0c,0x04]
+
+v_med3_i32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_med3_i32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_med3_i32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_med3_i32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_med3_i32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_med3_i32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_med3_i32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_med3_i32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_med3_i32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xff,0x0c,0x04]
+
+v_med3_i32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x01,0x0d,0x04]
+
+v_med3_i32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x83,0x0d,0x04]
+
+v_med3_i32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_med3_i32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xef,0x0d,0x04]
+
+v_med3_i32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_med3_i32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_med3_i32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_med3_i32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfe,0x07]
+
+v_med3_i32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x0e,0x00]
+
+v_med3_i32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x96,0x01]
+
+v_med3_i32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x9a,0x01]
+
+v_med3_i32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x9e,0x01]
+
+v_med3_i32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xaa,0x01]
+
+v_med3_i32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xae,0x01]
+
+v_med3_i32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xee,0x01]
+
+v_med3_i32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xf2,0x01]
+
+v_med3_i32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfa,0x01]
+
+v_med3_i32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xfe,0x01]
+
+v_med3_i32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x02,0x02]
+
+v_med3_i32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0x06,0x03]
+
+v_med3_i32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xc2,0x03]
+
+v_med3_i32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xde,0x03]
+
+v_med3_i32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xee,0x03]
+
+v_med3_i32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xf2,0x03]
+
+v_med3_i32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd7,0xd1,0x01,0x05,0xf6,0x03]
+
+v_med3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xff,0x05,0x0e,0x04]
+
+v_med3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x04,0x0e,0x04]
+
+v_med3_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x65,0x04,0x0e,0x04]
+
+v_med3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x66,0x04,0x0e,0x04]
+
+v_med3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x67,0x04,0x0e,0x04]
+
+v_med3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_med3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_med3_u32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_med3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_med3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_med3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_med3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x80,0x04,0x0e,0x04]
+
+v_med3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_med3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_med3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_med3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_med3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xff,0x0f,0x04]
+
+v_med3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0c,0x04]
+
+v_med3_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_med3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_med3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_med3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_med3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_med3_u32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_med3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_med3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_med3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xff,0x0c,0x04]
+
+v_med3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x01,0x0d,0x04]
+
+v_med3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x83,0x0d,0x04]
+
+v_med3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_med3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xef,0x0d,0x04]
+
+v_med3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_med3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_med3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_med3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfe,0x07]
+
+v_med3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x0e,0x00]
+
+v_med3_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x96,0x01]
+
+v_med3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x9a,0x01]
+
+v_med3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x9e,0x01]
+
+v_med3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xaa,0x01]
+
+v_med3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xae,0x01]
+
+v_med3_u32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xee,0x01]
+
+v_med3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xf2,0x01]
+
+v_med3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfa,0x01]
+
+v_med3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xfe,0x01]
+
+v_med3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x02,0x02]
+
+v_med3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0x06,0x03]
+
+v_med3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xc2,0x03]
+
+v_med3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xde,0x03]
+
+v_med3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xee,0x03]
+
+v_med3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xf2,0x03]
+
+v_med3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd8,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xff,0x05,0x0e,0x04]
+
+v_sad_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x04,0x0e,0x04]
+
+v_sad_u8 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x65,0x04,0x0e,0x04]
+
+v_sad_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x66,0x04,0x0e,0x04]
+
+v_sad_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x67,0x04,0x0e,0x04]
+
+v_sad_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_sad_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_sad_u8 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_sad_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_sad_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_sad_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_sad_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x80,0x04,0x0e,0x04]
+
+v_sad_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_sad_u8 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_sad_u8 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_sad_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_sad_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xff,0x0f,0x04]
+
+v_sad_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0c,0x04]
+
+v_sad_u8 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_sad_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_sad_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_sad_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_sad_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_sad_u8 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_sad_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_sad_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_sad_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xff,0x0c,0x04]
+
+v_sad_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x01,0x0d,0x04]
+
+v_sad_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x83,0x0d,0x04]
+
+v_sad_u8 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_sad_u8 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xef,0x0d,0x04]
+
+v_sad_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_sad_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_sad_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_sad_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfe,0x07]
+
+v_sad_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x0e,0x00]
+
+v_sad_u8 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x96,0x01]
+
+v_sad_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x9a,0x01]
+
+v_sad_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x9e,0x01]
+
+v_sad_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xaa,0x01]
+
+v_sad_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xae,0x01]
+
+v_sad_u8 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xee,0x01]
+
+v_sad_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xf2,0x01]
+
+v_sad_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfa,0x01]
+
+v_sad_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xfe,0x01]
+
+v_sad_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x02,0x02]
+
+v_sad_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0x06,0x03]
+
+v_sad_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xc2,0x03]
+
+v_sad_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xde,0x03]
+
+v_sad_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xee,0x03]
+
+v_sad_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xf2,0x03]
+
+v_sad_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xd9,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_u8 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xd9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xda,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xff,0x05,0x0e,0x04]
+
+v_sad_hi_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x65,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x66,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x67,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x80,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_sad_hi_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xff,0x0f,0x04]
+
+v_sad_hi_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xff,0x0c,0x04]
+
+v_sad_hi_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x01,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x83,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xef,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_sad_hi_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfe,0x07]
+
+v_sad_hi_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x0e,0x00]
+
+v_sad_hi_u8 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x96,0x01]
+
+v_sad_hi_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x9a,0x01]
+
+v_sad_hi_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x9e,0x01]
+
+v_sad_hi_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xaa,0x01]
+
+v_sad_hi_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xae,0x01]
+
+v_sad_hi_u8 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xee,0x01]
+
+v_sad_hi_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xf2,0x01]
+
+v_sad_hi_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfa,0x01]
+
+v_sad_hi_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xfe,0x01]
+
+v_sad_hi_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x02,0x02]
+
+v_sad_hi_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0x06,0x03]
+
+v_sad_hi_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xc2,0x03]
+
+v_sad_hi_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xde,0x03]
+
+v_sad_hi_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xee,0x03]
+
+v_sad_hi_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xf2,0x03]
+
+v_sad_hi_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xda,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_hi_u8 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xda,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xff,0x05,0x0e,0x04]
+
+v_sad_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x04,0x0e,0x04]
+
+v_sad_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x65,0x04,0x0e,0x04]
+
+v_sad_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x66,0x04,0x0e,0x04]
+
+v_sad_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x67,0x04,0x0e,0x04]
+
+v_sad_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_sad_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_sad_u16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_sad_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_sad_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_sad_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_sad_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x80,0x04,0x0e,0x04]
+
+v_sad_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_sad_u16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_sad_u16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_sad_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_sad_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xff,0x0f,0x04]
+
+v_sad_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0c,0x04]
+
+v_sad_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_sad_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_sad_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_sad_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_sad_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_sad_u16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_sad_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_sad_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_sad_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xff,0x0c,0x04]
+
+v_sad_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x01,0x0d,0x04]
+
+v_sad_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x83,0x0d,0x04]
+
+v_sad_u16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_sad_u16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xef,0x0d,0x04]
+
+v_sad_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_sad_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_sad_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_sad_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfe,0x07]
+
+v_sad_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x0e,0x00]
+
+v_sad_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x96,0x01]
+
+v_sad_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x9a,0x01]
+
+v_sad_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x9e,0x01]
+
+v_sad_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xaa,0x01]
+
+v_sad_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xae,0x01]
+
+v_sad_u16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xee,0x01]
+
+v_sad_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xf2,0x01]
+
+v_sad_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfa,0x01]
+
+v_sad_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xfe,0x01]
+
+v_sad_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x02,0x02]
+
+v_sad_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0x06,0x03]
+
+v_sad_u16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xc2,0x03]
+
+v_sad_u16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xde,0x03]
+
+v_sad_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xee,0x03]
+
+v_sad_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xf2,0x03]
+
+v_sad_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xdb,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_u16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xdb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_sad_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xff,0x05,0x0e,0x04]
+
+v_sad_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x04,0x0e,0x04]
+
+v_sad_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x65,0x04,0x0e,0x04]
+
+v_sad_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x66,0x04,0x0e,0x04]
+
+v_sad_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x67,0x04,0x0e,0x04]
+
+v_sad_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_sad_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_sad_u32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_sad_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_sad_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_sad_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_sad_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x80,0x04,0x0e,0x04]
+
+v_sad_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_sad_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_sad_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_sad_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_sad_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xff,0x0f,0x04]
+
+v_sad_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0c,0x04]
+
+v_sad_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_sad_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_sad_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_sad_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_sad_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_sad_u32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_sad_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_sad_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_sad_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xff,0x0c,0x04]
+
+v_sad_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x01,0x0d,0x04]
+
+v_sad_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x83,0x0d,0x04]
+
+v_sad_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_sad_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xef,0x0d,0x04]
+
+v_sad_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_sad_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_sad_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_sad_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfe,0x07]
+
+v_sad_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x0e,0x00]
+
+v_sad_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x96,0x01]
+
+v_sad_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x9a,0x01]
+
+v_sad_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x9e,0x01]
+
+v_sad_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xaa,0x01]
+
+v_sad_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xae,0x01]
+
+v_sad_u32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xee,0x01]
+
+v_sad_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xf2,0x01]
+
+v_sad_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfa,0x01]
+
+v_sad_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xfe,0x01]
+
+v_sad_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x02,0x02]
+
+v_sad_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0x06,0x03]
+
+v_sad_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xc2,0x03]
+
+v_sad_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xde,0x03]
+
+v_sad_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xee,0x03]
+
+v_sad_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xf2,0x03]
+
+v_sad_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xdc,0xd1,0x01,0x05,0xf6,0x03]
+
+v_sad_u32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xdc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xff,0x05,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x65,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x66,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x67,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x80,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xff,0x0f,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xff,0x0c,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x01,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x83,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xef,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_cvt_pk_u8_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfe,0x07]
+
+v_cvt_pk_u8_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x00]
+
+v_cvt_pk_u8_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x96,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x9a,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x9e,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xaa,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xae,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xee,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xf2,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfa,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xfe,0x01]
+
+v_cvt_pk_u8_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x02,0x02]
+
+v_cvt_pk_u8_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x06,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xc2,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xde,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xee,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xf2,0x03]
+
+v_cvt_pk_u8_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0xf6,0x03]
+
+v_cvt_pk_u8_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xdd,0xd1,0x01,0x05,0x0e,0x24]
+
+v_cvt_pk_u8_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xdd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xff,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x65,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x67,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xff,0x0f,0x04]
+
+v_div_fixup_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xff,0x0c,0x04]
+
+v_div_fixup_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfe,0x07]
+
+v_div_fixup_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x00]
+
+v_div_fixup_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x96,0x01]
+
+v_div_fixup_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_fixup_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x9e,0x01]
+
+v_div_fixup_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xae,0x01]
+
+v_div_fixup_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xee,0x01]
+
+v_div_fixup_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xf2,0x01]
+
+v_div_fixup_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xfe,0x01]
+
+v_div_fixup_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_fixup_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_fixup_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xde,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_div_fixup_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x14]
+
+v_div_fixup_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xde,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[2:3], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x02,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[4:5], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x04,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], s[100:101], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x64,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], flat_scratch, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], ttmp[14:15], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], exec, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], src_vccz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], src_execz, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], src_scc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfd,0x0f,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[4:5], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x09,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[6:7], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x0d,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], s[100:101], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xc9,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], flat_scratch, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], ttmp[14:15], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xf5,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], exec, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xfa,0x07]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[6:7]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x1a,0x00]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[8:9]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x22,0x00]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], s[100:101]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x92,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], flat_scratch
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], ttmp[14:15]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xea,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], exec
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -1
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], src_vccz
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], src_execz
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], src_scc
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// CHECK: [0x05,0x01,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// CHECK: [0x05,0x02,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// CHECK: [0x05,0x04,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// CHECK: [0x05,0x07,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// CHECK: [0x05,0x80,0xdf,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x14]
+
+v_div_fixup_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// CHECK: [0x05,0x00,0xdf,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_div_scale_f32 v5, vcc, v1, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f32 v255, vcc, v1, v2, v3
+// CHECK: [0xff,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, v255, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xff,0x05,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, s1, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, s101, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x65,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x67,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, vcc_lo, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, vcc_hi, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, ttmp15, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, m0, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, exec_lo, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, exec_hi, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, 0, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, -1, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, 0.5, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, -4.0, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_vccz, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_execz, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_scc, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, src_lds_direct, v2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_div_scale_f32 v5, vcc, v1, v255, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xff,0x0f,0x04]
+
+v_div_scale_f32 v5, vcc, v1, s2, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, s101, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, vcc_lo, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, vcc_hi, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, ttmp15, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, m0, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, exec_lo, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, exec_hi, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xff,0x0c,0x04]
+
+v_div_scale_f32 v5, vcc, v1, 0, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, -1, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, 0.5, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, -4.0, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, src_vccz, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, src_execz, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, src_scc, v3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_scale_f32 v5, vcc, v1, v2, v255
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfe,0x07]
+
+v_div_scale_f32 v5, vcc, v1, v2, s3
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x0e,0x00]
+
+v_div_scale_f32 v5, vcc, v1, v2, s101
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x96,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x9e,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, vcc_lo
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, vcc_hi
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xae,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, ttmp15
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xee,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, m0
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xf2,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, exec_lo
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, exec_hi
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xfe,0x01]
+
+v_div_scale_f32 v5, vcc, v1, v2, 0
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_scale_f32 v5, vcc, v1, v2, -1
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, 0.5
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, -4.0
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, src_vccz
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, src_execz
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_scale_f32 v5, vcc, v1, v2, src_scc
+// CHECK: [0x05,0x6a,0xe0,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f64 v[254:255], vcc, v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x6a,0xe1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, s[2:3], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x02,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, s[4:5], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x04,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, s[100:101], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x64,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, flat_scratch, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, ttmp[14:15], v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, exec, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, src_vccz, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, src_execz, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, src_scc, v[2:3], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfd,0x0f,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], s[4:5], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x09,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], s[6:7], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x0d,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], s[100:101], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xc9,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], flat_scratch, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], ttmp[14:15], v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xf5,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], exec, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xfa,0x07]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[6:7]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x1a,0x00]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[8:9]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x22,0x00]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], s[100:101]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x92,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], flat_scratch
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], ttmp[14:15]
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xea,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], exec
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -1
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], src_vccz
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], src_execz
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_scale_f64 v[5:6], vcc, v[1:2], v[2:3], src_scc
+// CHECK: [0x05,0x6a,0xe1,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_fmas_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xff,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xff,0x0f,0x04]
+
+v_div_fmas_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xfe,0x07]
+
+v_div_fmas_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fmas_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fmas_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fmas_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fmas_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fmas_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fmas_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fmas_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fmas_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xe2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f32 v5, v1, v2, v3 mul:2
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_div_fmas_f32 v5, v1, v2, v3 mul:4
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x14]
+
+v_div_fmas_f32 v5, v1, v2, v3 div:2
+// CHECK: [0x05,0x00,0xe2,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[254:255], v[1:2], v[2:3], v[3:4]
+// CHECK: [0xfe,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[254:255], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], vcc, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], 0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], -1, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], 0.5, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], -4.0, v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[254:255], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xfd,0x0f,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], vcc, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[254:255]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xfa,0x07]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], vcc
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -1
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], 0.5
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -4.0
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fmas_f64 v[5:6], -v[1:2], v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fmas_f64 v[5:6], v[1:2], -v[2:3], v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fmas_f64 v[5:6], -v[1:2], -v[2:3], -v[3:4]
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fmas_f64 v[5:6], |v[1:2]|, v[2:3], v[3:4]
+// CHECK: [0x05,0x01,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], |v[2:3]|, v[3:4]
+// CHECK: [0x05,0x02,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], |v[3:4]|
+// CHECK: [0x05,0x04,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], |v[1:2]|, |v[2:3]|, |v[3:4]|
+// CHECK: [0x05,0x07,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] clamp
+// CHECK: [0x05,0x80,0xe3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:2
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x0c]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] mul:4
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x14]
+
+v_div_fmas_f64 v[5:6], v[1:2], v[2:3], v[3:4] div:2
+// CHECK: [0x05,0x00,0xe3,0xd1,0x01,0x05,0x0e,0x1c]
+
+v_msad_u8 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_msad_u8 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_msad_u8 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xff,0x05,0x0e,0x04]
+
+v_msad_u8 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x04,0x0e,0x04]
+
+v_msad_u8 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x65,0x04,0x0e,0x04]
+
+v_msad_u8 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x66,0x04,0x0e,0x04]
+
+v_msad_u8 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x67,0x04,0x0e,0x04]
+
+v_msad_u8 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_msad_u8 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_msad_u8 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_msad_u8 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_msad_u8 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_msad_u8 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_msad_u8 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x80,0x04,0x0e,0x04]
+
+v_msad_u8 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_msad_u8 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_msad_u8 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_msad_u8 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_msad_u8 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xff,0x0f,0x04]
+
+v_msad_u8 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0c,0x04]
+
+v_msad_u8 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_msad_u8 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_msad_u8 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_msad_u8 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_msad_u8 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_msad_u8 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_msad_u8 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_msad_u8 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_msad_u8 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xff,0x0c,0x04]
+
+v_msad_u8 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x01,0x0d,0x04]
+
+v_msad_u8 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x83,0x0d,0x04]
+
+v_msad_u8 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_msad_u8 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xef,0x0d,0x04]
+
+v_msad_u8 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_msad_u8 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_msad_u8 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_msad_u8 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfe,0x07]
+
+v_msad_u8 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x0e,0x00]
+
+v_msad_u8 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x96,0x01]
+
+v_msad_u8 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x9a,0x01]
+
+v_msad_u8 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x9e,0x01]
+
+v_msad_u8 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xaa,0x01]
+
+v_msad_u8 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xae,0x01]
+
+v_msad_u8 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xee,0x01]
+
+v_msad_u8 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xf2,0x01]
+
+v_msad_u8 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfa,0x01]
+
+v_msad_u8 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xfe,0x01]
+
+v_msad_u8 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x02,0x02]
+
+v_msad_u8 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0x06,0x03]
+
+v_msad_u8 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xc2,0x03]
+
+v_msad_u8 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xde,0x03]
+
+v_msad_u8 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xee,0x03]
+
+v_msad_u8 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xf2,0x03]
+
+v_msad_u8 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xe4,0xd1,0x01,0x05,0xf6,0x03]
+
+v_msad_u8 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xe4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
+// CHECK: [0xfe,0x00,0xe5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x02,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x04,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], s[100:101], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x64,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x66,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], ttmp[14:15], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x80,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xff,0x0f,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], s101, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], ttmp15, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xff,0x0c,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x01,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x83,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xef,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xfa,0x07]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x1a,0x00]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x22,0x00]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, s[100:101]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x92,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x9a,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xaa,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15]
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xea,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xfa,0x01]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x02,0x02]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0x06,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, 0.5
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xc2,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, -4.0
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xde,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, src_vccz
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xee,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, src_execz
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xf2,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, src_scc
+// CHECK: [0x05,0x00,0xe5,0xd1,0x01,0x05,0xf6,0x03]
+
+v_qsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
+// CHECK: [0x05,0x80,0xe5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4]
+// CHECK: [0xfe,0x00,0xe6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[254:255], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xfe,0x05,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[2:3], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x02,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[4:5], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x04,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], s[100:101], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x64,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], flat_scratch, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], vcc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], ttmp[14:15], v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], exec, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], 0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], -1, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v255, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s2, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], s101, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], vcc_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], ttmp15, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], m0, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_lo, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], exec_hi, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], -1, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], 0.5, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], -4.0, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], src_vccz, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], src_execz, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], src_scc, v[3:4]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[254:255]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xfa,0x07]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[6:7]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x1a,0x00]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[8:9]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x22,0x00]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, s[100:101]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x92,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, flat_scratch
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, vcc
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, ttmp[14:15]
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xea,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, exec
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x02,0x02]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -1
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0x06,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, 0.5
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, -4.0
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xde,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, src_vccz
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xee,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, src_execz
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, src_scc
+// CHECK: [0x05,0x00,0xe6,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mqsad_pk_u16_u8 v[5:6], v[1:2], v2, v[3:4] clamp
+// CHECK: [0x05,0x80,0xe6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[2:3], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x02,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[4:5], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x04,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], s[100:101], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x64,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], flat_scratch, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], vcc, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], ttmp[14:15], v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x7a,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], exec, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], 0, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], -1, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], 0.5, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], -4.0, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], src_vccz, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], src_execz, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], src_scc, v2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], s2, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], s101, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], flat_scratch_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], vcc_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], vcc_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], ttmp15, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], m0, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], exec_lo, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], exec_hi, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], 0, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], -1, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], 0.5, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], -4.0, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], src_vccz, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], src_execz, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], src_scc, v[3:6]
+// CHECK: [0xfc,0x00,0xe7,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mqsad_u32_u8 v[252:255], v[1:2], v2, v[3:6] clamp
+// CHECK: [0xfc,0x80,0xe7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[254:255], s[12:13], v1, v2, v[3:4]
+// CHECK: [0xfe,0x0c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[14:15], v1, v2, v[3:4]
+// CHECK: [0x05,0x0e,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[100:101], v1, v2, v[3:4]
+// CHECK: [0x05,0x64,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], flat_scratch, v1, v2, v[3:4]
+// CHECK: [0x05,0x66,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], vcc, v1, v2, v[3:4]
+// CHECK: [0x05,0x6a,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], ttmp[14:15], v1, v2, v[3:4]
+// CHECK: [0x05,0x7a,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v255, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], s1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], s101, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], ttmp15, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], m0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], 0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], -1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], src_lds_direct, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v255, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, s2, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, s101, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, ttmp15, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, m0, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, 0, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, -1, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, 0.5, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, -4.0, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, src_vccz, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, src_execz, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, src_scc, v[3:4]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[254:255]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xfa,0x07]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x1a,0x00]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x22,0x00]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x92,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, ttmp[14:15]
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xea,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, exec
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, 0
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -1
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, -4.0
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, src_vccz
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, src_execz
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, src_scc
+// CHECK: [0x05,0x0c,0xe8,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_u64_u32 v[5:6], s[12:13], v1, v2, v[3:4] clamp
+// CHECK: [0x05,0x8c,0xe8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[254:255], s[12:13], v1, v2, v[3:4]
+// CHECK: [0xfe,0x0c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[14:15], v1, v2, v[3:4]
+// CHECK: [0x05,0x0e,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[100:101], v1, v2, v[3:4]
+// CHECK: [0x05,0x64,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], flat_scratch, v1, v2, v[3:4]
+// CHECK: [0x05,0x66,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], vcc, v1, v2, v[3:4]
+// CHECK: [0x05,0x6a,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], ttmp[14:15], v1, v2, v[3:4]
+// CHECK: [0x05,0x7a,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v255, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], s1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], s101, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], flat_scratch_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], vcc_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], vcc_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], ttmp15, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], m0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], exec_lo, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], exec_hi, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], 0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], -1, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], 0.5, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], -4.0, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_vccz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_execz, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_scc, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], src_lds_direct, v2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v255, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, s2, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, s101, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, flat_scratch_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, vcc_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, ttmp15, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, m0, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, exec_lo, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, exec_hi, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, 0, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, -1, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, 0.5, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, -4.0, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, src_vccz, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, src_execz, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, src_scc, v[3:4]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[254:255]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xfa,0x07]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[6:7]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x1a,0x00]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[8:9]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x22,0x00]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, s[100:101]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x92,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, flat_scratch
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, vcc
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, ttmp[14:15]
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xea,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, exec
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, 0
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -1
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, -4.0
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, src_vccz
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, src_execz
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, src_scc
+// CHECK: [0x05,0x0c,0xe9,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_i64_i32 v[5:6], s[12:13], v1, v2, v[3:4] clamp
+// CHECK: [0x05,0x8c,0xe9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_legacy_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_legacy_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_legacy_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_mad_legacy_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xef,0x0d,0x04]
+
+v_mad_legacy_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_legacy_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_legacy_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_legacy_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_legacy_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_legacy_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_legacy_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_legacy_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_legacy_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_legacy_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_legacy_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_legacy_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_legacy_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_legacy_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_legacy_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_legacy_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_legacy_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_legacy_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_legacy_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_legacy_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_legacy_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_legacy_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x24]
+
+v_mad_legacy_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x44]
+
+v_mad_legacy_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0x84]
+
+v_mad_legacy_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xea,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_mad_legacy_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xea,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_legacy_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_legacy_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_legacy_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_legacy_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_legacy_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_legacy_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_legacy_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_legacy_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_legacy_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_legacy_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_legacy_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_legacy_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_legacy_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_legacy_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_legacy_u16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_legacy_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_legacy_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_legacy_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_legacy_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_legacy_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_legacy_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_legacy_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_legacy_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xeb,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_legacy_u16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xeb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_i16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_i16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xec,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_legacy_i16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_legacy_i16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_legacy_i16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_legacy_i16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_legacy_i16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_legacy_i16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_legacy_i16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_legacy_i16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_legacy_i16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_legacy_i16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_legacy_i16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_legacy_i16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_legacy_i16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_legacy_i16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_legacy_i16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_legacy_i16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_legacy_i16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_legacy_i16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_legacy_i16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_legacy_i16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_legacy_i16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_legacy_i16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_legacy_i16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_legacy_i16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_legacy_i16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xec,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_legacy_i16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xec,0xd1,0x01,0x05,0x0e,0x04]
+
+v_perm_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0e,0x04]
+
+v_perm_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xed,0xd1,0x01,0x05,0x0e,0x04]
+
+v_perm_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xff,0x05,0x0e,0x04]
+
+v_perm_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x04,0x0e,0x04]
+
+v_perm_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x65,0x04,0x0e,0x04]
+
+v_perm_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x66,0x04,0x0e,0x04]
+
+v_perm_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x67,0x04,0x0e,0x04]
+
+v_perm_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_perm_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_perm_b32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_perm_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_perm_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_perm_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_perm_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x80,0x04,0x0e,0x04]
+
+v_perm_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_perm_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_perm_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_perm_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_perm_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_perm_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_perm_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_perm_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xff,0x0f,0x04]
+
+v_perm_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0c,0x04]
+
+v_perm_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_perm_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_perm_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_perm_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_perm_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_perm_b32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_perm_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_perm_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_perm_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xff,0x0c,0x04]
+
+v_perm_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x01,0x0d,0x04]
+
+v_perm_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x83,0x0d,0x04]
+
+v_perm_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_perm_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xef,0x0d,0x04]
+
+v_perm_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_perm_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_perm_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_perm_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfe,0x07]
+
+v_perm_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x0e,0x00]
+
+v_perm_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x96,0x01]
+
+v_perm_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x9a,0x01]
+
+v_perm_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x9e,0x01]
+
+v_perm_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xaa,0x01]
+
+v_perm_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xae,0x01]
+
+v_perm_b32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xee,0x01]
+
+v_perm_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xf2,0x01]
+
+v_perm_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfa,0x01]
+
+v_perm_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xfe,0x01]
+
+v_perm_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x02,0x02]
+
+v_perm_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0x06,0x03]
+
+v_perm_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xc2,0x03]
+
+v_perm_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xde,0x03]
+
+v_perm_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xee,0x03]
+
+v_perm_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xf2,0x03]
+
+v_perm_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xed,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_legacy_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xff,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x65,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x66,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x67,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x80,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_fma_legacy_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xff,0x0f,0x04]
+
+v_fma_legacy_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xff,0x0c,0x04]
+
+v_fma_legacy_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x01,0x0d,0x04]
+
+v_fma_legacy_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x83,0x0d,0x04]
+
+v_fma_legacy_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_fma_legacy_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xef,0x0d,0x04]
+
+v_fma_legacy_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_fma_legacy_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_fma_legacy_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_fma_legacy_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfe,0x07]
+
+v_fma_legacy_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x00]
+
+v_fma_legacy_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x96,0x01]
+
+v_fma_legacy_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x9a,0x01]
+
+v_fma_legacy_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x9e,0x01]
+
+v_fma_legacy_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xaa,0x01]
+
+v_fma_legacy_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xae,0x01]
+
+v_fma_legacy_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xee,0x01]
+
+v_fma_legacy_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xf2,0x01]
+
+v_fma_legacy_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfa,0x01]
+
+v_fma_legacy_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xfe,0x01]
+
+v_fma_legacy_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x02,0x02]
+
+v_fma_legacy_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x06,0x03]
+
+v_fma_legacy_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xc2,0x03]
+
+v_fma_legacy_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xde,0x03]
+
+v_fma_legacy_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xee,0x03]
+
+v_fma_legacy_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xf2,0x03]
+
+v_fma_legacy_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0xf6,0x03]
+
+v_fma_legacy_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x24]
+
+v_fma_legacy_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x44]
+
+v_fma_legacy_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0x84]
+
+v_fma_legacy_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xee,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_fma_legacy_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_fma_legacy_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xee,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xff,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x65,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x66,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x67,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xff,0x0f,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xff,0x0c,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfe,0x07]
+
+v_div_fixup_legacy_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x00]
+
+v_div_fixup_legacy_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x96,0x01]
+
+v_div_fixup_legacy_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x9a,0x01]
+
+v_div_fixup_legacy_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x9e,0x01]
+
+v_div_fixup_legacy_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_legacy_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xae,0x01]
+
+v_div_fixup_legacy_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xee,0x01]
+
+v_div_fixup_legacy_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xf2,0x01]
+
+v_div_fixup_legacy_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_legacy_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xfe,0x01]
+
+v_div_fixup_legacy_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x02,0x02]
+
+v_div_fixup_legacy_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x06,0x03]
+
+v_div_fixup_legacy_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_legacy_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xde,0x03]
+
+v_div_fixup_legacy_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xee,0x03]
+
+v_div_fixup_legacy_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xf2,0x03]
+
+v_div_fixup_legacy_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_legacy_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_legacy_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_legacy_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_legacy_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xef,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_legacy_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_legacy_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xef,0xd1,0x01,0x05,0x0e,0x04]
+
+v_cvt_pkaccum_u8_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0xf0,0xd1,0x01,0x05,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xff,0x05,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x65,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x66,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x67,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x6a,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x6b,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x7b,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x7c,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x7e,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x7f,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x80,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xc1,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xf0,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xf7,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xfb,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xfc,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xfd,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0xfe,0x04,0x02,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xff,0x03,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcb,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcd,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xcf,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd5,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xd7,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf7,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf9,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xfd,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xff,0x00,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x01,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x83,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xe1,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xef,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf7,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xf9,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0xfb,0x01,0x00]
+
+v_cvt_pkaccum_u8_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0xf0,0xd1,0x01,0x05,0x02,0x20]
+
+v_cvt_pkaccum_u8_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0xf0,0xd1,0x01,0x05,0x02,0x00]
+
+v_mad_u32_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_u32_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_u32_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_u32_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_u32_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_u32_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_u32_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_u32_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_u32_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_u32_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_u32_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_u32_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_u32_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_u32_u16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_u32_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_u32_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_u32_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_u32_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_u32_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_u32_u16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_u32_u16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_u32_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_u32_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_u32_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xf1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xf1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xf1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xf1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xf1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xf1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_u32_u16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xf1,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0xff,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x65,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x66,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x67,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x80,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xff,0x0f,0x04]
+
+v_mad_i32_i16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xff,0x0c,0x04]
+
+v_mad_i32_i16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x01,0x0d,0x04]
+
+v_mad_i32_i16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x83,0x0d,0x04]
+
+v_mad_i32_i16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_mad_i32_i16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_mad_i32_i16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xfe,0x07]
+
+v_mad_i32_i16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x00]
+
+v_mad_i32_i16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x96,0x01]
+
+v_mad_i32_i16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x9a,0x01]
+
+v_mad_i32_i16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x9e,0x01]
+
+v_mad_i32_i16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xaa,0x01]
+
+v_mad_i32_i16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xae,0x01]
+
+v_mad_i32_i16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xee,0x01]
+
+v_mad_i32_i16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xf2,0x01]
+
+v_mad_i32_i16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xfa,0x01]
+
+v_mad_i32_i16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xfe,0x01]
+
+v_mad_i32_i16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x02,0x02]
+
+v_mad_i32_i16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x06,0x03]
+
+v_mad_i32_i16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xc2,0x03]
+
+v_mad_i32_i16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xde,0x03]
+
+v_mad_i32_i16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xee,0x03]
+
+v_mad_i32_i16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xf2,0x03]
+
+v_mad_i32_i16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0xf6,0x03]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xf2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xf2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xf2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xf2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xf2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xf2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_mad_i32_i16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xf2,0xd1,0x01,0x05,0x0e,0x04]
+
+v_xad_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_xad_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xf3,0xd1,0x01,0x05,0x0e,0x04]
+
+v_xad_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0xff,0x05,0x0e,0x04]
+
+v_xad_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x04,0x0e,0x04]
+
+v_xad_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x65,0x04,0x0e,0x04]
+
+v_xad_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x66,0x04,0x0e,0x04]
+
+v_xad_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x67,0x04,0x0e,0x04]
+
+v_xad_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_xad_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_xad_u32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_xad_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_xad_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_xad_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_xad_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x80,0x04,0x0e,0x04]
+
+v_xad_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_xad_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_xad_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_xad_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_xad_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_xad_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_xad_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_xad_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xff,0x0f,0x04]
+
+v_xad_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x0c,0x04]
+
+v_xad_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_xad_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_xad_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_xad_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_xad_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_xad_u32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_xad_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_xad_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_xad_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xff,0x0c,0x04]
+
+v_xad_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x01,0x0d,0x04]
+
+v_xad_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x83,0x0d,0x04]
+
+v_xad_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_xad_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xef,0x0d,0x04]
+
+v_xad_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_xad_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_xad_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_xad_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xfe,0x07]
+
+v_xad_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x0e,0x00]
+
+v_xad_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x96,0x01]
+
+v_xad_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x9a,0x01]
+
+v_xad_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x9e,0x01]
+
+v_xad_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xaa,0x01]
+
+v_xad_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xae,0x01]
+
+v_xad_u32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xee,0x01]
+
+v_xad_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xf2,0x01]
+
+v_xad_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xfa,0x01]
+
+v_xad_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xfe,0x01]
+
+v_xad_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x02,0x02]
+
+v_xad_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0x06,0x03]
+
+v_xad_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xc2,0x03]
+
+v_xad_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xde,0x03]
+
+v_xad_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xee,0x03]
+
+v_xad_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xf2,0x03]
+
+v_xad_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xf3,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0xff,0x05,0x0e,0x04]
+
+v_min3_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x04,0x0e,0x04]
+
+v_min3_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x65,0x04,0x0e,0x04]
+
+v_min3_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x66,0x04,0x0e,0x04]
+
+v_min3_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x67,0x04,0x0e,0x04]
+
+v_min3_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_min3_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_min3_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_min3_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_min3_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_min3_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_min3_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x80,0x04,0x0e,0x04]
+
+v_min3_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_min3_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_min3_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_min3_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_min3_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_min3_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_min3_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_min3_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xff,0x0f,0x04]
+
+v_min3_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0c,0x04]
+
+v_min3_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_min3_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_min3_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_min3_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_min3_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_min3_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_min3_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_min3_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_min3_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xff,0x0c,0x04]
+
+v_min3_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x01,0x0d,0x04]
+
+v_min3_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x83,0x0d,0x04]
+
+v_min3_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_min3_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xef,0x0d,0x04]
+
+v_min3_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_min3_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_min3_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_min3_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xfe,0x07]
+
+v_min3_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x00]
+
+v_min3_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x96,0x01]
+
+v_min3_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x9a,0x01]
+
+v_min3_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x9e,0x01]
+
+v_min3_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xaa,0x01]
+
+v_min3_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xae,0x01]
+
+v_min3_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xee,0x01]
+
+v_min3_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xf2,0x01]
+
+v_min3_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xfa,0x01]
+
+v_min3_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xfe,0x01]
+
+v_min3_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x02,0x02]
+
+v_min3_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x06,0x03]
+
+v_min3_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xc2,0x03]
+
+v_min3_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xde,0x03]
+
+v_min3_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xee,0x03]
+
+v_min3_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xf2,0x03]
+
+v_min3_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x24]
+
+v_min3_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x44]
+
+v_min3_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x84]
+
+v_min3_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_min3_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xf4,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0xff,0x05,0x0e,0x04]
+
+v_min3_i16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x04,0x0e,0x04]
+
+v_min3_i16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x65,0x04,0x0e,0x04]
+
+v_min3_i16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x66,0x04,0x0e,0x04]
+
+v_min3_i16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x67,0x04,0x0e,0x04]
+
+v_min3_i16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_min3_i16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_min3_i16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_min3_i16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_min3_i16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_min3_i16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_min3_i16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x80,0x04,0x0e,0x04]
+
+v_min3_i16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_min3_i16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_min3_i16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_min3_i16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_min3_i16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_min3_i16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xff,0x0f,0x04]
+
+v_min3_i16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0c,0x04]
+
+v_min3_i16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_min3_i16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_min3_i16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_min3_i16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_min3_i16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_min3_i16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_min3_i16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_min3_i16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_min3_i16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xff,0x0c,0x04]
+
+v_min3_i16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x01,0x0d,0x04]
+
+v_min3_i16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x83,0x0d,0x04]
+
+v_min3_i16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_min3_i16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_min3_i16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_min3_i16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xfe,0x07]
+
+v_min3_i16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x00]
+
+v_min3_i16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x96,0x01]
+
+v_min3_i16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x9a,0x01]
+
+v_min3_i16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x9e,0x01]
+
+v_min3_i16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xaa,0x01]
+
+v_min3_i16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xae,0x01]
+
+v_min3_i16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xee,0x01]
+
+v_min3_i16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xf2,0x01]
+
+v_min3_i16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xfa,0x01]
+
+v_min3_i16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xfe,0x01]
+
+v_min3_i16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x02,0x02]
+
+v_min3_i16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x06,0x03]
+
+v_min3_i16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xee,0x03]
+
+v_min3_i16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xf2,0x03]
+
+v_min3_i16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xf5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xf5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xf5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xf5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xf5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xf5,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xf6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0xff,0x05,0x0e,0x04]
+
+v_min3_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x04,0x0e,0x04]
+
+v_min3_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x65,0x04,0x0e,0x04]
+
+v_min3_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x66,0x04,0x0e,0x04]
+
+v_min3_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x67,0x04,0x0e,0x04]
+
+v_min3_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_min3_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_min3_u16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_min3_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_min3_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_min3_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_min3_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x80,0x04,0x0e,0x04]
+
+v_min3_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_min3_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_min3_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_min3_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_min3_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_min3_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xff,0x0f,0x04]
+
+v_min3_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x0c,0x04]
+
+v_min3_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_min3_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_min3_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_min3_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_min3_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_min3_u16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_min3_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_min3_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_min3_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xff,0x0c,0x04]
+
+v_min3_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x01,0x0d,0x04]
+
+v_min3_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x83,0x0d,0x04]
+
+v_min3_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_min3_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_min3_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_min3_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xfe,0x07]
+
+v_min3_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x0e,0x00]
+
+v_min3_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x96,0x01]
+
+v_min3_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x9a,0x01]
+
+v_min3_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x9e,0x01]
+
+v_min3_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xaa,0x01]
+
+v_min3_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xae,0x01]
+
+v_min3_u16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xee,0x01]
+
+v_min3_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xf2,0x01]
+
+v_min3_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xfa,0x01]
+
+v_min3_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xfe,0x01]
+
+v_min3_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x02,0x02]
+
+v_min3_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x06,0x03]
+
+v_min3_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xee,0x03]
+
+v_min3_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xf2,0x03]
+
+v_min3_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0xf6,0x03]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xf6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xf6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xf6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xf6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xf6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_min3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xf6,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0xff,0x05,0x0e,0x04]
+
+v_max3_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x04,0x0e,0x04]
+
+v_max3_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x65,0x04,0x0e,0x04]
+
+v_max3_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x66,0x04,0x0e,0x04]
+
+v_max3_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x67,0x04,0x0e,0x04]
+
+v_max3_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_max3_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_max3_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_max3_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_max3_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_max3_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_max3_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x80,0x04,0x0e,0x04]
+
+v_max3_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_max3_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_max3_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_max3_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_max3_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_max3_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_max3_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_max3_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xff,0x0f,0x04]
+
+v_max3_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0c,0x04]
+
+v_max3_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_max3_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_max3_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_max3_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_max3_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_max3_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_max3_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_max3_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_max3_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xff,0x0c,0x04]
+
+v_max3_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x01,0x0d,0x04]
+
+v_max3_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x83,0x0d,0x04]
+
+v_max3_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_max3_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xef,0x0d,0x04]
+
+v_max3_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_max3_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_max3_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_max3_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xfe,0x07]
+
+v_max3_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x00]
+
+v_max3_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x96,0x01]
+
+v_max3_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x9a,0x01]
+
+v_max3_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x9e,0x01]
+
+v_max3_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xaa,0x01]
+
+v_max3_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xae,0x01]
+
+v_max3_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xee,0x01]
+
+v_max3_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xf2,0x01]
+
+v_max3_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xfa,0x01]
+
+v_max3_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xfe,0x01]
+
+v_max3_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x02,0x02]
+
+v_max3_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x06,0x03]
+
+v_max3_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xc2,0x03]
+
+v_max3_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xde,0x03]
+
+v_max3_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xee,0x03]
+
+v_max3_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xf2,0x03]
+
+v_max3_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0xf6,0x03]
+
+v_max3_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x24]
+
+v_max3_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x44]
+
+v_max3_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x84]
+
+v_max3_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_max3_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xf7,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0xff,0x05,0x0e,0x04]
+
+v_max3_i16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x04,0x0e,0x04]
+
+v_max3_i16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x65,0x04,0x0e,0x04]
+
+v_max3_i16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x66,0x04,0x0e,0x04]
+
+v_max3_i16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x67,0x04,0x0e,0x04]
+
+v_max3_i16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_max3_i16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_max3_i16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_max3_i16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_max3_i16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_max3_i16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_max3_i16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x80,0x04,0x0e,0x04]
+
+v_max3_i16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_max3_i16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_max3_i16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_max3_i16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_max3_i16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_max3_i16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xff,0x0f,0x04]
+
+v_max3_i16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0c,0x04]
+
+v_max3_i16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_max3_i16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_max3_i16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_max3_i16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_max3_i16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_max3_i16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_max3_i16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_max3_i16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_max3_i16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xff,0x0c,0x04]
+
+v_max3_i16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x01,0x0d,0x04]
+
+v_max3_i16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x83,0x0d,0x04]
+
+v_max3_i16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_max3_i16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_max3_i16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_max3_i16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xfe,0x07]
+
+v_max3_i16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x00]
+
+v_max3_i16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x96,0x01]
+
+v_max3_i16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x9a,0x01]
+
+v_max3_i16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x9e,0x01]
+
+v_max3_i16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xaa,0x01]
+
+v_max3_i16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xae,0x01]
+
+v_max3_i16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xee,0x01]
+
+v_max3_i16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xf2,0x01]
+
+v_max3_i16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xfa,0x01]
+
+v_max3_i16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xfe,0x01]
+
+v_max3_i16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x02,0x02]
+
+v_max3_i16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x06,0x03]
+
+v_max3_i16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xee,0x03]
+
+v_max3_i16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xf2,0x03]
+
+v_max3_i16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0xf6,0x03]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xf8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xf8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xf8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xf8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xf8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xf8,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xf9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0xff,0x05,0x0e,0x04]
+
+v_max3_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x04,0x0e,0x04]
+
+v_max3_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x65,0x04,0x0e,0x04]
+
+v_max3_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x66,0x04,0x0e,0x04]
+
+v_max3_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x67,0x04,0x0e,0x04]
+
+v_max3_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_max3_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_max3_u16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_max3_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_max3_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_max3_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_max3_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x80,0x04,0x0e,0x04]
+
+v_max3_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_max3_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_max3_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_max3_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_max3_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_max3_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xff,0x0f,0x04]
+
+v_max3_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x0c,0x04]
+
+v_max3_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_max3_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_max3_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_max3_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_max3_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_max3_u16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_max3_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_max3_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_max3_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xff,0x0c,0x04]
+
+v_max3_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x01,0x0d,0x04]
+
+v_max3_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x83,0x0d,0x04]
+
+v_max3_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_max3_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_max3_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_max3_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xfe,0x07]
+
+v_max3_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x0e,0x00]
+
+v_max3_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x96,0x01]
+
+v_max3_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x9a,0x01]
+
+v_max3_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x9e,0x01]
+
+v_max3_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xaa,0x01]
+
+v_max3_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xae,0x01]
+
+v_max3_u16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xee,0x01]
+
+v_max3_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xf2,0x01]
+
+v_max3_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xfa,0x01]
+
+v_max3_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xfe,0x01]
+
+v_max3_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x02,0x02]
+
+v_max3_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x06,0x03]
+
+v_max3_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xee,0x03]
+
+v_max3_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xf2,0x03]
+
+v_max3_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0xf6,0x03]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xf9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xf9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xf9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xf9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xf9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_max3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xf9,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0xff,0x05,0x0e,0x04]
+
+v_med3_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x04,0x0e,0x04]
+
+v_med3_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x65,0x04,0x0e,0x04]
+
+v_med3_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x66,0x04,0x0e,0x04]
+
+v_med3_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x67,0x04,0x0e,0x04]
+
+v_med3_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_med3_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_med3_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_med3_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_med3_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_med3_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_med3_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x80,0x04,0x0e,0x04]
+
+v_med3_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_med3_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_med3_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_med3_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_med3_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_med3_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_med3_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_med3_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xff,0x0f,0x04]
+
+v_med3_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0c,0x04]
+
+v_med3_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_med3_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_med3_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_med3_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_med3_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_med3_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_med3_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_med3_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_med3_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xff,0x0c,0x04]
+
+v_med3_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x01,0x0d,0x04]
+
+v_med3_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x83,0x0d,0x04]
+
+v_med3_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_med3_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xef,0x0d,0x04]
+
+v_med3_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_med3_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_med3_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_med3_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xfe,0x07]
+
+v_med3_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x00]
+
+v_med3_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x96,0x01]
+
+v_med3_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x9a,0x01]
+
+v_med3_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x9e,0x01]
+
+v_med3_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xaa,0x01]
+
+v_med3_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xae,0x01]
+
+v_med3_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xee,0x01]
+
+v_med3_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xf2,0x01]
+
+v_med3_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xfa,0x01]
+
+v_med3_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xfe,0x01]
+
+v_med3_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x02,0x02]
+
+v_med3_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x06,0x03]
+
+v_med3_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xc2,0x03]
+
+v_med3_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xde,0x03]
+
+v_med3_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xee,0x03]
+
+v_med3_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xf2,0x03]
+
+v_med3_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0xf6,0x03]
+
+v_med3_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x24]
+
+v_med3_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x44]
+
+v_med3_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x84]
+
+v_med3_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0xe4]
+
+v_med3_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xfa,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0xff,0x05,0x0e,0x04]
+
+v_med3_i16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x04,0x0e,0x04]
+
+v_med3_i16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x65,0x04,0x0e,0x04]
+
+v_med3_i16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x66,0x04,0x0e,0x04]
+
+v_med3_i16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x67,0x04,0x0e,0x04]
+
+v_med3_i16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_med3_i16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_med3_i16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_med3_i16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_med3_i16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_med3_i16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_med3_i16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x80,0x04,0x0e,0x04]
+
+v_med3_i16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_med3_i16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_med3_i16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_med3_i16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_med3_i16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_med3_i16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xff,0x0f,0x04]
+
+v_med3_i16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0c,0x04]
+
+v_med3_i16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_med3_i16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_med3_i16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_med3_i16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_med3_i16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_med3_i16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_med3_i16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_med3_i16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_med3_i16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xff,0x0c,0x04]
+
+v_med3_i16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x01,0x0d,0x04]
+
+v_med3_i16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x83,0x0d,0x04]
+
+v_med3_i16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_med3_i16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_med3_i16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_med3_i16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xfe,0x07]
+
+v_med3_i16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x00]
+
+v_med3_i16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x96,0x01]
+
+v_med3_i16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x9a,0x01]
+
+v_med3_i16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x9e,0x01]
+
+v_med3_i16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xaa,0x01]
+
+v_med3_i16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xae,0x01]
+
+v_med3_i16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xee,0x01]
+
+v_med3_i16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xf2,0x01]
+
+v_med3_i16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xfa,0x01]
+
+v_med3_i16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xfe,0x01]
+
+v_med3_i16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x02,0x02]
+
+v_med3_i16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x06,0x03]
+
+v_med3_i16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xee,0x03]
+
+v_med3_i16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xf2,0x03]
+
+v_med3_i16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0xf6,0x03]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xfb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xfb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xfb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xfb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xfb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xfb,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xfc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0xff,0x05,0x0e,0x04]
+
+v_med3_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x04,0x0e,0x04]
+
+v_med3_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x65,0x04,0x0e,0x04]
+
+v_med3_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x66,0x04,0x0e,0x04]
+
+v_med3_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x67,0x04,0x0e,0x04]
+
+v_med3_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_med3_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_med3_u16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_med3_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_med3_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_med3_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_med3_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x80,0x04,0x0e,0x04]
+
+v_med3_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_med3_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_med3_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_med3_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_med3_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_med3_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xff,0x0f,0x04]
+
+v_med3_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x0c,0x04]
+
+v_med3_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_med3_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_med3_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_med3_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_med3_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_med3_u16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_med3_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_med3_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_med3_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xff,0x0c,0x04]
+
+v_med3_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x01,0x0d,0x04]
+
+v_med3_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x83,0x0d,0x04]
+
+v_med3_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_med3_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_med3_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_med3_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xfe,0x07]
+
+v_med3_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x0e,0x00]
+
+v_med3_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x96,0x01]
+
+v_med3_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x9a,0x01]
+
+v_med3_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x9e,0x01]
+
+v_med3_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xaa,0x01]
+
+v_med3_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xae,0x01]
+
+v_med3_u16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xee,0x01]
+
+v_med3_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xf2,0x01]
+
+v_med3_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xfa,0x01]
+
+v_med3_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xfe,0x01]
+
+v_med3_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x02,0x02]
+
+v_med3_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x06,0x03]
+
+v_med3_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xee,0x03]
+
+v_med3_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xf2,0x03]
+
+v_med3_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0xf6,0x03]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0xfc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0xfc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0xfc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0xfc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0xfc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_med3_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0xfc,0xd1,0x01,0x05,0x0e,0x04]
+
+v_lshl_add_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_lshl_add_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xfd,0xd1,0x01,0x05,0x0e,0x04]
+
+v_lshl_add_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0xff,0x05,0x0e,0x04]
+
+v_lshl_add_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x65,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x66,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x67,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x80,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_lshl_add_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xff,0x0f,0x04]
+
+v_lshl_add_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xff,0x0c,0x04]
+
+v_lshl_add_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x01,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x83,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xef,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_lshl_add_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xfe,0x07]
+
+v_lshl_add_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x0e,0x00]
+
+v_lshl_add_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x96,0x01]
+
+v_lshl_add_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x9a,0x01]
+
+v_lshl_add_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x9e,0x01]
+
+v_lshl_add_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xaa,0x01]
+
+v_lshl_add_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xae,0x01]
+
+v_lshl_add_u32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xee,0x01]
+
+v_lshl_add_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xf2,0x01]
+
+v_lshl_add_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xfa,0x01]
+
+v_lshl_add_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xfe,0x01]
+
+v_lshl_add_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x02,0x02]
+
+v_lshl_add_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0x06,0x03]
+
+v_lshl_add_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xc2,0x03]
+
+v_lshl_add_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xde,0x03]
+
+v_lshl_add_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xee,0x03]
+
+v_lshl_add_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xf2,0x03]
+
+v_lshl_add_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xfd,0xd1,0x01,0x05,0xf6,0x03]
+
+v_add_lshl_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x0e,0x04]
+
+v_add_lshl_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xfe,0xd1,0x01,0x05,0x0e,0x04]
+
+v_add_lshl_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0xff,0x05,0x0e,0x04]
+
+v_add_lshl_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x65,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x66,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x67,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x80,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_add_lshl_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xff,0x0f,0x04]
+
+v_add_lshl_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xff,0x0c,0x04]
+
+v_add_lshl_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x01,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x83,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xef,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_add_lshl_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xfe,0x07]
+
+v_add_lshl_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x0e,0x00]
+
+v_add_lshl_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x96,0x01]
+
+v_add_lshl_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x9a,0x01]
+
+v_add_lshl_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x9e,0x01]
+
+v_add_lshl_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xaa,0x01]
+
+v_add_lshl_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xae,0x01]
+
+v_add_lshl_u32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xee,0x01]
+
+v_add_lshl_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xf2,0x01]
+
+v_add_lshl_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xfa,0x01]
+
+v_add_lshl_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xfe,0x01]
+
+v_add_lshl_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x02,0x02]
+
+v_add_lshl_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0x06,0x03]
+
+v_add_lshl_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xc2,0x03]
+
+v_add_lshl_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xde,0x03]
+
+v_add_lshl_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xee,0x03]
+
+v_add_lshl_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xf2,0x03]
+
+v_add_lshl_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xfe,0xd1,0x01,0x05,0xf6,0x03]
+
+v_add3_u32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x0e,0x04]
+
+v_add3_u32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xff,0xd1,0x01,0x05,0x0e,0x04]
+
+v_add3_u32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0xff,0x05,0x0e,0x04]
+
+v_add3_u32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x04,0x0e,0x04]
+
+v_add3_u32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x65,0x04,0x0e,0x04]
+
+v_add3_u32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x66,0x04,0x0e,0x04]
+
+v_add3_u32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x67,0x04,0x0e,0x04]
+
+v_add3_u32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x6a,0x04,0x0e,0x04]
+
+v_add3_u32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x6b,0x04,0x0e,0x04]
+
+v_add3_u32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x7b,0x04,0x0e,0x04]
+
+v_add3_u32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x7c,0x04,0x0e,0x04]
+
+v_add3_u32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x7e,0x04,0x0e,0x04]
+
+v_add3_u32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x7f,0x04,0x0e,0x04]
+
+v_add3_u32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x80,0x04,0x0e,0x04]
+
+v_add3_u32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0xc1,0x04,0x0e,0x04]
+
+v_add3_u32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0xf0,0x04,0x0e,0x04]
+
+v_add3_u32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0xf7,0x04,0x0e,0x04]
+
+v_add3_u32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0xfb,0x04,0x0e,0x04]
+
+v_add3_u32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0xfc,0x04,0x0e,0x04]
+
+v_add3_u32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0xfd,0x04,0x0e,0x04]
+
+v_add3_u32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0xfe,0x04,0x0e,0x04]
+
+v_add3_u32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xff,0x0f,0x04]
+
+v_add3_u32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x0c,0x04]
+
+v_add3_u32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xcb,0x0c,0x04]
+
+v_add3_u32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xcd,0x0c,0x04]
+
+v_add3_u32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xcf,0x0c,0x04]
+
+v_add3_u32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xd5,0x0c,0x04]
+
+v_add3_u32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xd7,0x0c,0x04]
+
+v_add3_u32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xf7,0x0c,0x04]
+
+v_add3_u32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xf9,0x0c,0x04]
+
+v_add3_u32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xfd,0x0c,0x04]
+
+v_add3_u32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xff,0x0c,0x04]
+
+v_add3_u32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x01,0x0d,0x04]
+
+v_add3_u32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x83,0x0d,0x04]
+
+v_add3_u32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xe1,0x0d,0x04]
+
+v_add3_u32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xef,0x0d,0x04]
+
+v_add3_u32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xf7,0x0d,0x04]
+
+v_add3_u32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xf9,0x0d,0x04]
+
+v_add3_u32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0xfb,0x0d,0x04]
+
+v_add3_u32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xfe,0x07]
+
+v_add3_u32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x0e,0x00]
+
+v_add3_u32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x96,0x01]
+
+v_add3_u32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x9a,0x01]
+
+v_add3_u32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x9e,0x01]
+
+v_add3_u32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xaa,0x01]
+
+v_add3_u32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xae,0x01]
+
+v_add3_u32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xee,0x01]
+
+v_add3_u32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xf2,0x01]
+
+v_add3_u32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xfa,0x01]
+
+v_add3_u32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xfe,0x01]
+
+v_add3_u32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x02,0x02]
+
+v_add3_u32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0x06,0x03]
+
+v_add3_u32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xc2,0x03]
+
+v_add3_u32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xde,0x03]
+
+v_add3_u32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xee,0x03]
+
+v_add3_u32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xf2,0x03]
+
+v_add3_u32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xff,0xd1,0x01,0x05,0xf6,0x03]
+
+v_lshl_or_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x0e,0x04]
+
+v_lshl_or_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x00,0xd2,0x01,0x05,0x0e,0x04]
+
+v_lshl_or_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0xff,0x05,0x0e,0x04]
+
+v_lshl_or_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x65,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x66,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x67,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x80,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_lshl_or_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xff,0x0f,0x04]
+
+v_lshl_or_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xcb,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xff,0x0c,0x04]
+
+v_lshl_or_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x01,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x83,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xef,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_lshl_or_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xfe,0x07]
+
+v_lshl_or_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x0e,0x00]
+
+v_lshl_or_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x96,0x01]
+
+v_lshl_or_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x9a,0x01]
+
+v_lshl_or_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x9e,0x01]
+
+v_lshl_or_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xaa,0x01]
+
+v_lshl_or_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xae,0x01]
+
+v_lshl_or_b32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xee,0x01]
+
+v_lshl_or_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xf2,0x01]
+
+v_lshl_or_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xfa,0x01]
+
+v_lshl_or_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xfe,0x01]
+
+v_lshl_or_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x02,0x02]
+
+v_lshl_or_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0x06,0x03]
+
+v_lshl_or_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xc2,0x03]
+
+v_lshl_or_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xde,0x03]
+
+v_lshl_or_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xee,0x03]
+
+v_lshl_or_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xf2,0x03]
+
+v_lshl_or_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x00,0xd2,0x01,0x05,0xf6,0x03]
+
+v_and_or_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x0e,0x04]
+
+v_and_or_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x01,0xd2,0x01,0x05,0x0e,0x04]
+
+v_and_or_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0xff,0x05,0x0e,0x04]
+
+v_and_or_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x65,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x66,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x67,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x80,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_and_or_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xff,0x0f,0x04]
+
+v_and_or_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x0c,0x04]
+
+v_and_or_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xcb,0x0c,0x04]
+
+v_and_or_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_and_or_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_and_or_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_and_or_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_and_or_b32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_and_or_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_and_or_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_and_or_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xff,0x0c,0x04]
+
+v_and_or_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x01,0x0d,0x04]
+
+v_and_or_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x83,0x0d,0x04]
+
+v_and_or_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_and_or_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xef,0x0d,0x04]
+
+v_and_or_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_and_or_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_and_or_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_and_or_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xfe,0x07]
+
+v_and_or_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x0e,0x00]
+
+v_and_or_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x96,0x01]
+
+v_and_or_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x9a,0x01]
+
+v_and_or_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x9e,0x01]
+
+v_and_or_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xaa,0x01]
+
+v_and_or_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xae,0x01]
+
+v_and_or_b32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xee,0x01]
+
+v_and_or_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xf2,0x01]
+
+v_and_or_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xfa,0x01]
+
+v_and_or_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xfe,0x01]
+
+v_and_or_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x02,0x02]
+
+v_and_or_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0x06,0x03]
+
+v_and_or_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xc2,0x03]
+
+v_and_or_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xde,0x03]
+
+v_and_or_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xee,0x03]
+
+v_and_or_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xf2,0x03]
+
+v_and_or_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x01,0xd2,0x01,0x05,0xf6,0x03]
+
+v_or3_b32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x0e,0x04]
+
+v_or3_b32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x02,0xd2,0x01,0x05,0x0e,0x04]
+
+v_or3_b32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0xff,0x05,0x0e,0x04]
+
+v_or3_b32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x04,0x0e,0x04]
+
+v_or3_b32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x65,0x04,0x0e,0x04]
+
+v_or3_b32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x66,0x04,0x0e,0x04]
+
+v_or3_b32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x67,0x04,0x0e,0x04]
+
+v_or3_b32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_or3_b32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_or3_b32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_or3_b32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_or3_b32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_or3_b32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_or3_b32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x80,0x04,0x0e,0x04]
+
+v_or3_b32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_or3_b32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_or3_b32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_or3_b32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_or3_b32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_or3_b32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_or3_b32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_or3_b32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xff,0x0f,0x04]
+
+v_or3_b32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x0c,0x04]
+
+v_or3_b32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xcb,0x0c,0x04]
+
+v_or3_b32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_or3_b32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_or3_b32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_or3_b32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_or3_b32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_or3_b32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_or3_b32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_or3_b32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xff,0x0c,0x04]
+
+v_or3_b32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x01,0x0d,0x04]
+
+v_or3_b32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x83,0x0d,0x04]
+
+v_or3_b32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_or3_b32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xef,0x0d,0x04]
+
+v_or3_b32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_or3_b32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_or3_b32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_or3_b32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xfe,0x07]
+
+v_or3_b32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x0e,0x00]
+
+v_or3_b32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x96,0x01]
+
+v_or3_b32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x9a,0x01]
+
+v_or3_b32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x9e,0x01]
+
+v_or3_b32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xaa,0x01]
+
+v_or3_b32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xae,0x01]
+
+v_or3_b32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xee,0x01]
+
+v_or3_b32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xf2,0x01]
+
+v_or3_b32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xfa,0x01]
+
+v_or3_b32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xfe,0x01]
+
+v_or3_b32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x02,0x02]
+
+v_or3_b32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0x06,0x03]
+
+v_or3_b32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xc2,0x03]
+
+v_or3_b32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xde,0x03]
+
+v_or3_b32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xee,0x03]
+
+v_or3_b32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xf2,0x03]
+
+v_or3_b32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x02,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mad_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mad_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mad_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x65,0x04,0x0e,0x04]
+
+v_mad_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x66,0x04,0x0e,0x04]
+
+v_mad_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mad_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mad_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mad_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mad_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mad_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mad_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mad_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mad_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_mad_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_mad_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mad_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mad_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mad_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mad_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mad_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mad_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xcb,0x0c,0x04]
+
+v_mad_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_mad_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mad_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mad_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mad_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mad_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mad_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mad_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mad_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mad_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_mad_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xef,0x0d,0x04]
+
+v_mad_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mad_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mad_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xfe,0x07]
+
+v_mad_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x00]
+
+v_mad_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x96,0x01]
+
+v_mad_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x9a,0x01]
+
+v_mad_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x9e,0x01]
+
+v_mad_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mad_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xae,0x01]
+
+v_mad_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xee,0x01]
+
+v_mad_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xf2,0x01]
+
+v_mad_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mad_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xfe,0x01]
+
+v_mad_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x02,0x02]
+
+v_mad_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x06,0x03]
+
+v_mad_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xc2,0x03]
+
+v_mad_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xde,0x03]
+
+v_mad_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xee,0x03]
+
+v_mad_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mad_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mad_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x24]
+
+v_mad_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x44]
+
+v_mad_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x84]
+
+v_mad_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_mad_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0x03,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mad_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mad_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x65,0x04,0x0e,0x04]
+
+v_mad_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x66,0x04,0x0e,0x04]
+
+v_mad_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mad_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mad_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mad_u16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mad_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mad_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mad_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mad_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mad_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mad_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mad_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mad_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mad_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mad_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mad_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xcb,0x0c,0x04]
+
+v_mad_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_mad_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mad_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mad_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mad_u16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mad_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mad_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mad_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mad_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mad_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mad_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mad_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x07]
+
+v_mad_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0e,0x00]
+
+v_mad_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x96,0x01]
+
+v_mad_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x9a,0x01]
+
+v_mad_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x9e,0x01]
+
+v_mad_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mad_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xae,0x01]
+
+v_mad_u16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xee,0x01]
+
+v_mad_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xf2,0x01]
+
+v_mad_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mad_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xfe,0x01]
+
+v_mad_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x02,0x02]
+
+v_mad_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x06,0x03]
+
+v_mad_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xee,0x03]
+
+v_mad_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mad_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_u16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0x04,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0xff,0x05,0x0e,0x04]
+
+v_mad_i16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x04,0x0e,0x04]
+
+v_mad_i16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x65,0x04,0x0e,0x04]
+
+v_mad_i16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x66,0x04,0x0e,0x04]
+
+v_mad_i16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x67,0x04,0x0e,0x04]
+
+v_mad_i16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_mad_i16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_mad_i16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_mad_i16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_mad_i16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_mad_i16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_mad_i16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x80,0x04,0x0e,0x04]
+
+v_mad_i16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_mad_i16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_mad_i16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_mad_i16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_mad_i16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_mad_i16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xff,0x0f,0x04]
+
+v_mad_i16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x0c,0x04]
+
+v_mad_i16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xcb,0x0c,0x04]
+
+v_mad_i16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_mad_i16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_mad_i16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_mad_i16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_mad_i16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_mad_i16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_mad_i16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_mad_i16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xff,0x0c,0x04]
+
+v_mad_i16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x01,0x0d,0x04]
+
+v_mad_i16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x83,0x0d,0x04]
+
+v_mad_i16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_mad_i16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_mad_i16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_mad_i16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x07]
+
+v_mad_i16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x0e,0x00]
+
+v_mad_i16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x96,0x01]
+
+v_mad_i16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x9a,0x01]
+
+v_mad_i16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x9e,0x01]
+
+v_mad_i16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xaa,0x01]
+
+v_mad_i16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xae,0x01]
+
+v_mad_i16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xee,0x01]
+
+v_mad_i16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xf2,0x01]
+
+v_mad_i16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfa,0x01]
+
+v_mad_i16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xfe,0x01]
+
+v_mad_i16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x02,0x02]
+
+v_mad_i16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x06,0x03]
+
+v_mad_i16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xee,0x03]
+
+v_mad_i16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xf2,0x03]
+
+v_mad_i16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0xf6,0x03]
+
+v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
+v_mad_i16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0x05,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0xff,0x05,0x0e,0x04]
+
+v_fma_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x04,0x0e,0x04]
+
+v_fma_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x65,0x04,0x0e,0x04]
+
+v_fma_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x66,0x04,0x0e,0x04]
+
+v_fma_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x67,0x04,0x0e,0x04]
+
+v_fma_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_fma_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_fma_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_fma_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_fma_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_fma_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_fma_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x80,0x04,0x0e,0x04]
+
+v_fma_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_fma_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_fma_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_fma_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_fma_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_fma_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_fma_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_fma_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xff,0x0f,0x04]
+
+v_fma_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0c,0x04]
+
+v_fma_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xcb,0x0c,0x04]
+
+v_fma_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_fma_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_fma_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_fma_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_fma_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_fma_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_fma_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_fma_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xff,0x0c,0x04]
+
+v_fma_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x01,0x0d,0x04]
+
+v_fma_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x83,0x0d,0x04]
+
+v_fma_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_fma_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xef,0x0d,0x04]
+
+v_fma_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_fma_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_fma_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_fma_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xfe,0x07]
+
+v_fma_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x00]
+
+v_fma_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x96,0x01]
+
+v_fma_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x9a,0x01]
+
+v_fma_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x9e,0x01]
+
+v_fma_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xaa,0x01]
+
+v_fma_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xae,0x01]
+
+v_fma_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xee,0x01]
+
+v_fma_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xf2,0x01]
+
+v_fma_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xfa,0x01]
+
+v_fma_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xfe,0x01]
+
+v_fma_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x02,0x02]
+
+v_fma_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x06,0x03]
+
+v_fma_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xc2,0x03]
+
+v_fma_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xde,0x03]
+
+v_fma_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xee,0x03]
+
+v_fma_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xf2,0x03]
+
+v_fma_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0xf6,0x03]
+
+v_fma_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x24]
+
+v_fma_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x44]
+
+v_fma_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x84]
+
+v_fma_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_fma_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_fma_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0x06,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0xff,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x65,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x66,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x67,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x6a,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x6b,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x7b,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x7c,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x7e,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x7f,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x80,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0xc1,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0xf0,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0xf7,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0xfb,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0xfc,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0xfd,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0xfe,0x04,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xff,0x0f,0x04]
+
+v_div_fixup_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xcb,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xcd,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xcf,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xd5,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xd7,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xf7,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xf9,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xfd,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xff,0x0c,0x04]
+
+v_div_fixup_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x01,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x83,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xe1,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xef,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xf7,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xf9,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0xfb,0x0d,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xfe,0x07]
+
+v_div_fixup_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x00]
+
+v_div_fixup_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x96,0x01]
+
+v_div_fixup_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x9a,0x01]
+
+v_div_fixup_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x9e,0x01]
+
+v_div_fixup_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xaa,0x01]
+
+v_div_fixup_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xae,0x01]
+
+v_div_fixup_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xee,0x01]
+
+v_div_fixup_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xf2,0x01]
+
+v_div_fixup_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xfa,0x01]
+
+v_div_fixup_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xfe,0x01]
+
+v_div_fixup_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x02,0x02]
+
+v_div_fixup_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x06,0x03]
+
+v_div_fixup_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xc2,0x03]
+
+v_div_fixup_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xde,0x03]
+
+v_div_fixup_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xee,0x03]
+
+v_div_fixup_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xf2,0x03]
+
+v_div_fixup_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0xf6,0x03]
+
+v_div_fixup_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x24]
+
+v_div_fixup_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x44]
+
+v_div_fixup_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x84]
+
+v_div_fixup_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0xe4]
+
+v_div_fixup_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,0]
+// CHECK: [0x05,0x00,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,0,0,0]
+// CHECK: [0x05,0x08,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,1,0,0]
+// CHECK: [0x05,0x10,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,1,0]
+// CHECK: [0x05,0x20,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 op_sel:[0,0,0,1]
+// CHECK: [0x05,0x40,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 op_sel:[1,1,1,1]
+// CHECK: [0x05,0x78,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_div_fixup_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0x07,0xd2,0x01,0x05,0x0e,0x04]
+
+v_interp_p1ll_f16 v5, v2, attr0.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v255, v2, attr0.x
+// CHECK: [0xff,0x00,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr1.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x01,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr31.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x1f,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr32.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x20,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v255, attr0.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0xfe,0x03,0x00]
+
+v_interp_p1ll_f16 v5, -v2, attr0.x
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x40]
+
+v_interp_p1ll_f16 v5, |v2|, attr0.x
+// CHECK: [0x05,0x02,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.y
+// CHECK: [0x05,0x00,0x74,0xd2,0x40,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.z
+// CHECK: [0x05,0x00,0x74,0xd2,0x80,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.w
+// CHECK: [0x05,0x00,0x74,0xd2,0xc0,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x high
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x05,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x clamp
+// CHECK: [0x05,0x80,0x74,0xd2,0x00,0x04,0x02,0x00]
+
+v_interp_p1ll_f16 v5, v2, attr0.x mul:2
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x08]
+
+v_interp_p1ll_f16 v5, v2, attr0.x mul:4
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x10]
+
+v_interp_p1ll_f16 v5, v2, attr0.x div:2
+// CHECK: [0x05,0x00,0x74,0xd2,0x00,0x04,0x02,0x18]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v255, v2, attr0.x, v3
+// CHECK: [0xff,0x00,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr1.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x01,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr31.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x1f,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr32.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x20,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v255, attr0.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0xfe,0x0f,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v255
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0xfe,0x07]
+
+v_interp_p1lv_f16 v5, -v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, -v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x84]
+
+v_interp_p1lv_f16 v5, |v2|, attr0.x, v3
+// CHECK: [0x05,0x02,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, |v3|
+// CHECK: [0x05,0x04,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.y, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x40,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.z, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0x80,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.w, v3
+// CHECK: [0x05,0x00,0x75,0xd2,0xc0,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 high
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 clamp
+// CHECK: [0x05,0x80,0x75,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:2
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x0c]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 mul:4
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x14]
+
+v_interp_p1lv_f16 v5, v2, attr0.x, v3 div:2
+// CHECK: [0x05,0x00,0x75,0xd2,0x00,0x04,0x0e,0x1c]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v255, v2, attr0.x, v3
+// CHECK: [0xff,0x00,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr1.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x01,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr31.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x1f,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr32.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x20,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v255, attr0.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0xfe,0x0f,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.x, v255
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0xfe,0x07]
+
+v_interp_p2_legacy_f16 v5, -v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.x, -v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x04,0x0e,0x84]
+
+v_interp_p2_legacy_f16 v5, |v2|, attr0.x, v3
+// CHECK: [0x05,0x02,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.x, |v3|
+// CHECK: [0x05,0x04,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.y, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x40,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.z, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0x80,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.w, v3
+// CHECK: [0x05,0x00,0x76,0xd2,0xc0,0x04,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 high
+// CHECK: [0x05,0x00,0x76,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p2_legacy_f16 v5, v2, attr0.x, v3 clamp
+// CHECK: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v255, v2, attr0.x, v3
+// CHECK: [0xff,0x00,0x77,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr1.x, v3
+// CHECK: [0x05,0x00,0x77,0xd2,0x01,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr31.x, v3
+// CHECK: [0x05,0x00,0x77,0xd2,0x1f,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr32.x, v3
+// CHECK: [0x05,0x00,0x77,0xd2,0x20,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v255, attr0.x, v3
+// CHECK: [0x05,0x00,0x77,0xd2,0x00,0xfe,0x0f,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v255
+// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x04,0xfe,0x07]
+
+v_interp_p2_f16 v5, -v2, attr0.x, v3
+// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x44]
+
+v_interp_p2_f16 v5, v2, attr0.x, -v3
+// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x04,0x0e,0x84]
+
+v_interp_p2_f16 v5, |v2|, attr0.x, v3
+// CHECK: [0x05,0x02,0x77,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, |v3|
+// CHECK: [0x05,0x04,0x77,0xd2,0x00,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.y, v3
+// CHECK: [0x05,0x00,0x77,0xd2,0x40,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.z, v3
+// CHECK: [0x05,0x00,0x77,0xd2,0x80,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.w, v3
+// CHECK: [0x05,0x00,0x77,0xd2,0xc0,0x04,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 high
+// CHECK: [0x05,0x00,0x77,0xd2,0x00,0x05,0x0e,0x04]
+
+v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
+// CHECK: [0x05,0x80,0x77,0xd2,0x00,0x04,0x0e,0x04]
+
+v_add_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xfe,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x02,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x04,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], s[100:101], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x64,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x66,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x6a,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], ttmp[14:15], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x7a,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x7e,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x80,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xc1,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xf0,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xf7,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xfb,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xfc,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0xfd,0x04,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x03,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x09,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x0d,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], s[100:101]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xc9,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xcd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xd5,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], ttmp[14:15]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf5,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfd,0x00,0x00]
+
+v_add_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x01,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x83,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xe1,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xef,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf7,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xf9,0x01,0x00]
+
+v_add_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0xfb,0x01,0x00]
+
+v_add_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x20]
+
+v_add_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x40]
+
+v_add_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x60]
+
+v_add_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x80,0x80,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x08]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x10]
+
+v_add_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0x80,0xd2,0x01,0x05,0x02,0x18]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xfe,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x02,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x04,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], s[100:101], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x64,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x66,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], ttmp[14:15], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x7a,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x03,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x09,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x0d,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], s[100:101]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xc9,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], ttmp[14:15]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xf5,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x20]
+
+v_mul_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x40]
+
+v_mul_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x60]
+
+v_mul_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x80,0x81,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x08]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x10]
+
+v_mul_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0x81,0xd2,0x01,0x05,0x02,0x18]
+
+v_min_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xfe,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x02,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x04,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], s[100:101], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x64,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x66,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x6a,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], ttmp[14:15], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x7a,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x7e,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x80,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xc1,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xf0,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xf7,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xfb,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xfc,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0xfd,0x04,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x03,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x09,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x0d,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], s[100:101]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xc9,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xcd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xd5,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], ttmp[14:15]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf5,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfd,0x00,0x00]
+
+v_min_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x01,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x83,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xe1,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xef,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf7,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xf9,0x01,0x00]
+
+v_min_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0xfb,0x01,0x00]
+
+v_min_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x20]
+
+v_min_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x40]
+
+v_min_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x60]
+
+v_min_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x80,0x82,0xd2,0x01,0x05,0x02,0x00]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x08]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x10]
+
+v_min_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0x82,0xd2,0x01,0x05,0x02,0x18]
+
+v_max_f64 v[5:6], v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[254:255], v[1:2], v[2:3]
+// CHECK: [0xfe,0x00,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[254:255], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xfe,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], s[2:3], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x02,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], s[4:5], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x04,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], s[100:101], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x64,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], flat_scratch, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x66,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], vcc, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x6a,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], ttmp[14:15], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x7a,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], exec, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x7e,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x80,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xc1,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xf0,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xf7,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xfb,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xfc,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0xfd,0x04,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[254:255]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x03,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[4:5]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x09,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[6:7]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x0d,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], s[100:101]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xc9,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], flat_scratch
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xcd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], vcc
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xd5,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], ttmp[14:15]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xf5,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], exec
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfd,0x00,0x00]
+
+v_max_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x01,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x83,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xe1,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xef,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xf7,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xf9,0x01,0x00]
+
+v_max_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0xfb,0x01,0x00]
+
+v_max_f64 v[5:6], -v[1:2], v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x20]
+
+v_max_f64 v[5:6], v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x40]
+
+v_max_f64 v[5:6], -v[1:2], -v[2:3]
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x60]
+
+v_max_f64 v[5:6], |v[1:2]|, v[2:3]
+// CHECK: [0x05,0x01,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], |v[2:3]|
+// CHECK: [0x05,0x02,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|
+// CHECK: [0x05,0x03,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] clamp
+// CHECK: [0x05,0x80,0x83,0xd2,0x01,0x05,0x02,0x00]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] mul:2
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x08]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] mul:4
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x10]
+
+v_max_f64 v[5:6], v[1:2], v[2:3] div:2
+// CHECK: [0x05,0x00,0x83,0xd2,0x01,0x05,0x02,0x18]
+
+v_ldexp_f64 v[5:6], v[1:2], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[254:255], v[1:2], v2
+// CHECK: [0xfe,0x00,0x84,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[254:255], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xfe,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[2:3], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x02,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[4:5], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x04,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], s[100:101], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x64,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], flat_scratch, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x66,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], vcc, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], ttmp[14:15], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x7a,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], exec, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], 0, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x80,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], -1, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], 0.5, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], -4.0, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], src_vccz, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], src_execz, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], src_scc, v2
+// CHECK: [0x05,0x00,0x84,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v255
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x03,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], s101
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcb,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], flat_scratch_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcd,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], flat_scratch_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], vcc_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], vcc_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], ttmp15
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf7,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], m0
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], exec_lo
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], exec_hi
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xff,0x00,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x01,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x83,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xef,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f64 v[5:6], -v[1:2], v2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x20]
+
+v_ldexp_f64 v[5:6], |v[1:2]|, v2
+// CHECK: [0x05,0x01,0x84,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 clamp
+// CHECK: [0x05,0x80,0x84,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 mul:2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x08]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 mul:4
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x10]
+
+v_ldexp_f64 v[5:6], v[1:2], v2 div:2
+// CHECK: [0x05,0x00,0x84,0xd2,0x01,0x05,0x02,0x18]
+
+v_mul_lo_u32 v5, v1, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u32 v255, v1, v2
+// CHECK: [0xff,0x00,0x85,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_lo_u32 v5, v255, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_lo_u32 v5, s1, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, s101, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x65,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x66,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, m0, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, 0, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, -1, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x85,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_lo_u32 v5, v1, v255
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_lo_u32 v5, v1, s2
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, s101
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, m0
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_lo_u32 v5, v1, 0
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, -1
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_lo_u32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x85,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32 v255, v1, v2
+// CHECK: [0xff,0x00,0x86,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_u32 v5, v255, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_hi_u32 v5, s1, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, s101, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x65,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x66,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, m0, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, 0, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, -1, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x86,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_u32 v5, v1, v255
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_hi_u32 v5, v1, s2
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, s101
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, m0
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_hi_u32 v5, v1, 0
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, -1
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_u32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x86,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32 v255, v1, v2
+// CHECK: [0xff,0x00,0x87,0xd2,0x01,0x05,0x02,0x00]
+
+v_mul_hi_i32 v5, v255, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xff,0x05,0x02,0x00]
+
+v_mul_hi_i32 v5, s1, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, s101, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x65,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x66,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x67,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, m0, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, 0, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0x80,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, -1, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x87,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mul_hi_i32 v5, v1, v255
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x03,0x00]
+
+v_mul_hi_i32 v5, v1, s2
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x05,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, s101
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, m0
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xff,0x00,0x00]
+
+v_mul_hi_i32 v5, v1, 0
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x01,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, -1
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0x83,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xef,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mul_hi_i32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x87,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0x88,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xff,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x65,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x66,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x67,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x6b,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x7b,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x7c,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x7f,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x80,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0xfe,0x04,0x02,0x00]
+
+v_ldexp_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x03,0x00]
+
+v_ldexp_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x00,0x00]
+
+v_ldexp_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcb,0x00,0x00]
+
+v_ldexp_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcd,0x00,0x00]
+
+v_ldexp_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xcf,0x00,0x00]
+
+v_ldexp_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ldexp_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xd7,0x00,0x00]
+
+v_ldexp_f32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf7,0x00,0x00]
+
+v_ldexp_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x00,0x00]
+
+v_ldexp_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ldexp_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xff,0x00,0x00]
+
+v_ldexp_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x01,0x01,0x00]
+
+v_ldexp_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x83,0x01,0x00]
+
+v_ldexp_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ldexp_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xef,0x01,0x00]
+
+v_ldexp_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ldexp_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ldexp_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ldexp_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x20]
+
+v_ldexp_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x88,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x88,0xd2,0x01,0x05,0x02,0x00]
+
+v_ldexp_f32 v5, v1, v2 mul:2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x08]
+
+v_ldexp_f32 v5, v1, v2 mul:4
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x10]
+
+v_ldexp_f32 v5, v1, v2 div:2
+// CHECK: [0x05,0x00,0x88,0xd2,0x01,0x05,0x02,0x18]
+
+v_readlane_b32 s5, v1, s2
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 s101, v1, s2
+// CHECK: [0x65,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 flat_scratch_lo, v1, s2
+// CHECK: [0x66,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 flat_scratch_hi, v1, s2
+// CHECK: [0x67,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 ttmp15, v1, s2
+// CHECK: [0x7b,0x00,0x89,0xd2,0x01,0x05,0x00,0x00]
+
+v_readlane_b32 s5, v255, s2
+// CHECK: [0x05,0x00,0x89,0xd2,0xff,0x05,0x00,0x00]
+
+v_readlane_b32 s5, src_lds_direct, s2
+// CHECK: [0x05,0x00,0x89,0xd2,0xfe,0x04,0x00,0x00]
+
+v_readlane_b32 s5, v1, s101
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcb,0x00,0x00]
+
+v_readlane_b32 s5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcd,0x00,0x00]
+
+v_readlane_b32 s5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xcf,0x00,0x00]
+
+v_readlane_b32 s5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd5,0x00,0x00]
+
+v_readlane_b32 s5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xd7,0x00,0x00]
+
+v_readlane_b32 s5, v1, ttmp15
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xf7,0x00,0x00]
+
+v_readlane_b32 s5, v1, m0
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0xf9,0x00,0x00]
+
+v_readlane_b32 s5, v1, 0
+// CHECK: [0x05,0x00,0x89,0xd2,0x01,0x01,0x01,0x00]
+
+v_writelane_b32 v5, 0, s2
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
+
+v_writelane_b32 v255, 0, s2
+// CHECK: [0xff,0x00,0x8a,0xd2,0x80,0x04,0x00,0x00]
+
+v_writelane_b32 v5, -1, s2
+// CHECK: [0x05,0x00,0x8a,0xd2,0xc1,0x04,0x00,0x00]
+
+v_writelane_b32 v5, 0.5, s2
+// CHECK: [0x05,0x00,0x8a,0xd2,0xf0,0x04,0x00,0x00]
+
+v_writelane_b32 v5, -4.0, s2
+// CHECK: [0x05,0x00,0x8a,0xd2,0xf7,0x04,0x00,0x00]
+
+v_writelane_b32 v5, 0, s101
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xca,0x00,0x00]
+
+v_writelane_b32 v5, 0, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xcc,0x00,0x00]
+
+v_writelane_b32 v5, 0, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xce,0x00,0x00]
+
+v_writelane_b32 v5, 0, vcc_lo
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd4,0x00,0x00]
+
+v_writelane_b32 v5, 0, vcc_hi
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xd6,0x00,0x00]
+
+v_writelane_b32 v5, 0, ttmp15
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xf6,0x00,0x00]
+
+v_writelane_b32 v5, 0, m0
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0xf8,0x00,0x00]
+
+v_writelane_b32 v5, 0, 0
+// CHECK: [0x05,0x00,0x8a,0xd2,0x80,0x00,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v255, v1, v2
+// CHECK: [0xff,0x00,0x8b,0xd2,0x01,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v5, v255, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xff,0x05,0x02,0x00]
+
+v_bcnt_u32_b32 v5, s1, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, s101, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x65,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x66,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x67,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x6a,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x6b,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x7b,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, m0, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x7c,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x7e,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x7f,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, 0, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x80,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, -1, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xc1,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xf0,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xf7,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xfb,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xfc,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xfd,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8b,0xd2,0xfe,0x04,0x02,0x00]
+
+v_bcnt_u32_b32 v5, v1, v255
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x03,0x00]
+
+v_bcnt_u32_b32 v5, v1, s2
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x05,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, s101
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcb,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcd,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xcf,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd5,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xd7,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf7,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, m0
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf9,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xfd,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xff,0x00,0x00]
+
+v_bcnt_u32_b32 v5, v1, 0
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x01,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, -1
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0x83,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xe1,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xef,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf7,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xf9,0x01,0x00]
+
+v_bcnt_u32_b32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8b,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v255, v1, v2
+// CHECK: [0xff,0x00,0x8c,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v255, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xff,0x05,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, s1, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, s101, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x65,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x66,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x67,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, m0, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, 0, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x80,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, -1, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8c,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, v255
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x03,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, s2
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x05,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, s101
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, m0
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xff,0x00,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, 0
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x01,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, -1
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0x83,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xef,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mbcnt_lo_u32_b32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8c,0xd2,0x01,0xfb,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v255, v1, v2
+// CHECK: [0xff,0x00,0x8d,0xd2,0x01,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v255, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xff,0x05,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, s1, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, s101, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x65,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x66,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x67,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x6a,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x6b,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x7b,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, m0, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x7c,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x7e,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x7f,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, 0, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x80,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, -1, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xc1,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xf0,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xf7,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xfb,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xfc,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xfd,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8d,0xd2,0xfe,0x04,0x02,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, v255
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x03,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, s2
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x05,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, s101
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcb,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcd,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xcf,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd5,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xd7,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf7,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, m0
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf9,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xfd,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xff,0x00,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, 0
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x01,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, -1
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0x83,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xe1,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xef,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf7,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xf9,0x01,0x00]
+
+v_mbcnt_hi_u32_b32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8d,0xd2,0x01,0xfb,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b64 v[254:255], v1, v[2:3]
+// CHECK: [0xfe,0x00,0x8f,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], v255, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xff,0x05,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], s1, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], s101, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x65,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], flat_scratch_lo, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x66,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], flat_scratch_hi, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x67,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], vcc_lo, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], vcc_hi, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x6b,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], ttmp15, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x7b,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], m0, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x7c,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], exec_lo, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], exec_hi, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x7f,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x8f,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshlrev_b64 v[5:6], v1, v[254:255]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x03,0x00]
+
+v_lshlrev_b64 v[5:6], v1, s[4:5]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x09,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, s[6:7]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x0d,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, s[100:101]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xc9,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, flat_scratch
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xcd,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, vcc
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, ttmp[14:15]
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xf5,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, exec
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshlrev_b64 v[5:6], v1, 0
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, -1
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, 0.5
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, -4.0
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, src_vccz
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, src_execz
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshlrev_b64 v[5:6], v1, src_scc
+// CHECK: [0x05,0x00,0x8f,0xd2,0x01,0xfb,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b64 v[254:255], v1, v[2:3]
+// CHECK: [0xfe,0x00,0x90,0xd2,0x01,0x05,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], v255, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xff,0x05,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], s1, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], s101, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x65,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], flat_scratch_lo, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x66,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], flat_scratch_hi, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x67,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], vcc_lo, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x6a,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], vcc_hi, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x6b,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], ttmp15, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x7b,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], m0, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x7c,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], exec_lo, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x7e,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], exec_hi, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x7f,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0x80,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xc1,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xf0,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xf7,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xfb,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xfc,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x90,0xd2,0xfd,0x04,0x02,0x00]
+
+v_lshrrev_b64 v[5:6], v1, v[254:255]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x03,0x00]
+
+v_lshrrev_b64 v[5:6], v1, s[4:5]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x09,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, s[6:7]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x0d,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, s[100:101]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xc9,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, flat_scratch
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xcd,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, vcc
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xd5,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, ttmp[14:15]
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf5,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, exec
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfd,0x00,0x00]
+
+v_lshrrev_b64 v[5:6], v1, 0
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x01,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, -1
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0x83,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, 0.5
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xe1,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, -4.0
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xef,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, src_vccz
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf7,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, src_execz
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xf9,0x01,0x00]
+
+v_lshrrev_b64 v[5:6], v1, src_scc
+// CHECK: [0x05,0x00,0x90,0xd2,0x01,0xfb,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i64 v[254:255], v1, v[2:3]
+// CHECK: [0xfe,0x00,0x91,0xd2,0x01,0x05,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], v255, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xff,0x05,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], s1, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], s101, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x65,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], flat_scratch_lo, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x66,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], flat_scratch_hi, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x67,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], vcc_lo, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x6a,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], vcc_hi, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x6b,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], ttmp15, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x7b,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], m0, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x7c,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], exec_lo, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x7e,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], exec_hi, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x7f,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], 0, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0x80,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], -1, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xc1,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], 0.5, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xf0,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], -4.0, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xf7,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], src_vccz, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xfb,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], src_execz, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xfc,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], src_scc, v[2:3]
+// CHECK: [0x05,0x00,0x91,0xd2,0xfd,0x04,0x02,0x00]
+
+v_ashrrev_i64 v[5:6], v1, v[254:255]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x03,0x00]
+
+v_ashrrev_i64 v[5:6], v1, s[4:5]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x09,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, s[6:7]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x0d,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, s[100:101]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xc9,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, flat_scratch
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xcd,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, vcc
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xd5,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, ttmp[14:15]
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xf5,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, exec
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfd,0x00,0x00]
+
+v_ashrrev_i64 v[5:6], v1, 0
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x01,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, -1
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0x83,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, 0.5
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xe1,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, -4.0
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xef,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, src_vccz
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xf7,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, src_execz
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xf9,0x01,0x00]
+
+v_ashrrev_i64 v[5:6], v1, src_scc
+// CHECK: [0x05,0x00,0x91,0xd2,0x01,0xfb,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[254:255], v[1:2], v2
+// CHECK: [0xfe,0x00,0x92,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[254:255], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xfe,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[2:3], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x02,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[4:5], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x04,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], s[100:101], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x64,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], flat_scratch, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x66,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], vcc, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x6a,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], ttmp[14:15], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x7a,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], exec, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x7e,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], 0, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x80,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], -1, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xc1,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], 0.5, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xf0,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], -4.0, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xf7,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], src_vccz, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xfb,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], src_execz, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xfc,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], src_scc, v2
+// CHECK: [0x05,0x00,0x92,0xd2,0xfd,0x04,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v255
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x03,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], s101
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcb,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcd,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], flat_scratch_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xcf,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], vcc_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd5,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], vcc_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xd7,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], ttmp15
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf7,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], m0
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], exec_lo
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfd,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], exec_hi
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xff,0x00,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], 0
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x01,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], -1
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x83,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], 0.5
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xe1,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], -4.0
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xef,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], src_vccz
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf7,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], src_execz
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xf9,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], src_scc
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0xfb,0x01,0x00]
+
+v_trig_preop_f64 v[5:6], -v[1:2], v2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x20]
+
+v_trig_preop_f64 v[5:6], |v[1:2]|, v2
+// CHECK: [0x05,0x01,0x92,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 clamp
+// CHECK: [0x05,0x80,0x92,0xd2,0x01,0x05,0x02,0x00]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 mul:2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x08]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 mul:4
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x10]
+
+v_trig_preop_f64 v[5:6], v[1:2], v2 div:2
+// CHECK: [0x05,0x00,0x92,0xd2,0x01,0x05,0x02,0x18]
+
+v_bfm_b32 v5, v1, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
+
+v_bfm_b32 v255, v1, v2
+// CHECK: [0xff,0x00,0x93,0xd2,0x01,0x05,0x02,0x00]
+
+v_bfm_b32 v5, v255, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xff,0x05,0x02,0x00]
+
+v_bfm_b32 v5, s1, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x04,0x02,0x00]
+
+v_bfm_b32 v5, s101, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x65,0x04,0x02,0x00]
+
+v_bfm_b32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x66,0x04,0x02,0x00]
+
+v_bfm_b32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x67,0x04,0x02,0x00]
+
+v_bfm_b32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x6a,0x04,0x02,0x00]
+
+v_bfm_b32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x6b,0x04,0x02,0x00]
+
+v_bfm_b32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x7b,0x04,0x02,0x00]
+
+v_bfm_b32 v5, m0, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x7c,0x04,0x02,0x00]
+
+v_bfm_b32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x7e,0x04,0x02,0x00]
+
+v_bfm_b32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x7f,0x04,0x02,0x00]
+
+v_bfm_b32 v5, 0, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0x80,0x04,0x02,0x00]
+
+v_bfm_b32 v5, -1, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xc1,0x04,0x02,0x00]
+
+v_bfm_b32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xf0,0x04,0x02,0x00]
+
+v_bfm_b32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xf7,0x04,0x02,0x00]
+
+v_bfm_b32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xfb,0x04,0x02,0x00]
+
+v_bfm_b32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xfc,0x04,0x02,0x00]
+
+v_bfm_b32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xfd,0x04,0x02,0x00]
+
+v_bfm_b32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x93,0xd2,0xfe,0x04,0x02,0x00]
+
+v_bfm_b32 v5, v1, v255
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x03,0x00]
+
+v_bfm_b32 v5, v1, s2
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x05,0x00,0x00]
+
+v_bfm_b32 v5, v1, s101
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcb,0x00,0x00]
+
+v_bfm_b32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcd,0x00,0x00]
+
+v_bfm_b32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xcf,0x00,0x00]
+
+v_bfm_b32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd5,0x00,0x00]
+
+v_bfm_b32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xd7,0x00,0x00]
+
+v_bfm_b32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf7,0x00,0x00]
+
+v_bfm_b32 v5, v1, m0
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf9,0x00,0x00]
+
+v_bfm_b32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xfd,0x00,0x00]
+
+v_bfm_b32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xff,0x00,0x00]
+
+v_bfm_b32 v5, v1, 0
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x01,0x01,0x00]
+
+v_bfm_b32 v5, v1, -1
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0x83,0x01,0x00]
+
+v_bfm_b32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xe1,0x01,0x00]
+
+v_bfm_b32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xef,0x01,0x00]
+
+v_bfm_b32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf7,0x01,0x00]
+
+v_bfm_b32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xf9,0x01,0x00]
+
+v_bfm_b32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x93,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_i16_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_i16_f32 v5, v1, -v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_i16_f32 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x94,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_i16_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f32 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x94,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_u16_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_u16_f32 v5, v1, -v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_u16_f32 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x95,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_u16_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f32 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x95,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v255, v1, v2
+// CHECK: [0xff,0x00,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v255, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, s1, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, s101, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, m0, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, 0, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, -1, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, v255
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, s2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, s101
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, m0
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, 0
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, -1
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, -v1, v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pkrtz_f16_f32 v5, v1, -v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pkrtz_f16_f32 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x96,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pkrtz_f16_f32 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pkrtz_f16_f32 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x96,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v255, v1, v2
+// CHECK: [0xff,0x00,0x97,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v255, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, s1, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, s101, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, m0, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, 0, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, -1, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x97,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, v255
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, s2
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, s101
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, m0
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, 0
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, -1
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pk_u16_u32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x97,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v255, v1, v2
+// CHECK: [0xff,0x00,0x98,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, v255, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, s1, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, s101, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, m0, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, 0, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, -1, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x98,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, v255
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, s2
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, s101
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, m0
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, 0
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, -1
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pk_i16_i32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x98,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v255, v1, v2
+// CHECK: [0xff,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v255, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, s1, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, s101, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, m0, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, 0, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, -1, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v255
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, s2
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, s101
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, m0
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, 0
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, -1
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_i16_f16 v5, -v1, v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_i16_f16 v5, v1, -v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_i16_f16 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_i16_f16 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,0]
+// CHECK: [0x05,0x00,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,0,0]
+// CHECK: [0x05,0x08,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,1,0]
+// CHECK: [0x05,0x10,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[0,0,1]
+// CHECK: [0x05,0x40,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_i16_f16 v5, v1, v2 op_sel:[1,1,1]
+// CHECK: [0x05,0x58,0x99,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v255, v1, v2
+// CHECK: [0xff,0x00,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v255, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0xff,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, s1, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, s101, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x65,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x66,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x67,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x6a,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x6b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x7b,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, m0, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x7c,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x7e,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x7f,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, 0, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x80,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, -1, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0xc1,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0xf0,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0xf7,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0xfb,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0xfc,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0xfd,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0xfe,0x04,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v255
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xff,0x03,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, s2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, s101
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xcb,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xcd,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xcf,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd5,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xd7,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf7,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, m0
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf9,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xfd,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xff,0x00,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, 0
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x01,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, -1
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x83,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xe1,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xef,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf7,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xf9,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0xfb,0x01,0x00]
+
+v_cvt_pknorm_u16_f16 v5, -v1, v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x20]
+
+v_cvt_pknorm_u16_f16 v5, v1, -v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x40]
+
+v_cvt_pknorm_u16_f16 v5, -v1, -v2
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x60]
+
+v_cvt_pknorm_u16_f16 v5, |v1|, v2
+// CHECK: [0x05,0x01,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, |v2|
+// CHECK: [0x05,0x02,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,0]
+// CHECK: [0x05,0x00,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,0,0]
+// CHECK: [0x05,0x08,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,1,0]
+// CHECK: [0x05,0x10,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[0,0,1]
+// CHECK: [0x05,0x40,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_cvt_pknorm_u16_f16 v5, v1, v2 op_sel:[1,1,1]
+// CHECK: [0x05,0x58,0x9a,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32 v5, v1, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32 v255, v1, v2
+// CHECK: [0xff,0x00,0x9c,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i32 v5, v255, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0xff,0x05,0x02,0x00]
+
+v_add_i32 v5, s1, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x04,0x02,0x00]
+
+v_add_i32 v5, s101, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x65,0x04,0x02,0x00]
+
+v_add_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x66,0x04,0x02,0x00]
+
+v_add_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x67,0x04,0x02,0x00]
+
+v_add_i32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x6a,0x04,0x02,0x00]
+
+v_add_i32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x6b,0x04,0x02,0x00]
+
+v_add_i32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x7b,0x04,0x02,0x00]
+
+v_add_i32 v5, m0, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x7c,0x04,0x02,0x00]
+
+v_add_i32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x7e,0x04,0x02,0x00]
+
+v_add_i32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x7f,0x04,0x02,0x00]
+
+v_add_i32 v5, 0, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x80,0x04,0x02,0x00]
+
+v_add_i32 v5, -1, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0xc1,0x04,0x02,0x00]
+
+v_add_i32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0xf0,0x04,0x02,0x00]
+
+v_add_i32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0xf7,0x04,0x02,0x00]
+
+v_add_i32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0xfb,0x04,0x02,0x00]
+
+v_add_i32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0xfc,0x04,0x02,0x00]
+
+v_add_i32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0xfd,0x04,0x02,0x00]
+
+v_add_i32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x9c,0xd2,0xfe,0x04,0x02,0x00]
+
+v_add_i32 v5, v1, v255
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xff,0x03,0x00]
+
+v_add_i32 v5, v1, s2
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x05,0x00,0x00]
+
+v_add_i32 v5, v1, s101
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xcb,0x00,0x00]
+
+v_add_i32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xcd,0x00,0x00]
+
+v_add_i32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xcf,0x00,0x00]
+
+v_add_i32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd5,0x00,0x00]
+
+v_add_i32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xd7,0x00,0x00]
+
+v_add_i32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf7,0x00,0x00]
+
+v_add_i32 v5, v1, m0
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf9,0x00,0x00]
+
+v_add_i32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xfd,0x00,0x00]
+
+v_add_i32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xff,0x00,0x00]
+
+v_add_i32 v5, v1, 0
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x01,0x01,0x00]
+
+v_add_i32 v5, v1, -1
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0x83,0x01,0x00]
+
+v_add_i32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xe1,0x01,0x00]
+
+v_add_i32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xef,0x01,0x00]
+
+v_add_i32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf7,0x01,0x00]
+
+v_add_i32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xf9,0x01,0x00]
+
+v_add_i32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x9c,0xd2,0x01,0xfb,0x01,0x00]
+
+v_add_i32 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x9c,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32 v5, v1, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32 v255, v1, v2
+// CHECK: [0xff,0x00,0x9d,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i32 v5, v255, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0xff,0x05,0x02,0x00]
+
+v_sub_i32 v5, s1, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x04,0x02,0x00]
+
+v_sub_i32 v5, s101, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x65,0x04,0x02,0x00]
+
+v_sub_i32 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x66,0x04,0x02,0x00]
+
+v_sub_i32 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x67,0x04,0x02,0x00]
+
+v_sub_i32 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x6a,0x04,0x02,0x00]
+
+v_sub_i32 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x6b,0x04,0x02,0x00]
+
+v_sub_i32 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x7b,0x04,0x02,0x00]
+
+v_sub_i32 v5, m0, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x7c,0x04,0x02,0x00]
+
+v_sub_i32 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x7e,0x04,0x02,0x00]
+
+v_sub_i32 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x7f,0x04,0x02,0x00]
+
+v_sub_i32 v5, 0, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x80,0x04,0x02,0x00]
+
+v_sub_i32 v5, -1, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0xc1,0x04,0x02,0x00]
+
+v_sub_i32 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0xf0,0x04,0x02,0x00]
+
+v_sub_i32 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0xf7,0x04,0x02,0x00]
+
+v_sub_i32 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0xfb,0x04,0x02,0x00]
+
+v_sub_i32 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0xfc,0x04,0x02,0x00]
+
+v_sub_i32 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0xfd,0x04,0x02,0x00]
+
+v_sub_i32 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x9d,0xd2,0xfe,0x04,0x02,0x00]
+
+v_sub_i32 v5, v1, v255
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xff,0x03,0x00]
+
+v_sub_i32 v5, v1, s2
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x05,0x00,0x00]
+
+v_sub_i32 v5, v1, s101
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xcb,0x00,0x00]
+
+v_sub_i32 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xcd,0x00,0x00]
+
+v_sub_i32 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xcf,0x00,0x00]
+
+v_sub_i32 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xd5,0x00,0x00]
+
+v_sub_i32 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xd7,0x00,0x00]
+
+v_sub_i32 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xf7,0x00,0x00]
+
+v_sub_i32 v5, v1, m0
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xf9,0x00,0x00]
+
+v_sub_i32 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xfd,0x00,0x00]
+
+v_sub_i32 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xff,0x00,0x00]
+
+v_sub_i32 v5, v1, 0
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x01,0x01,0x00]
+
+v_sub_i32 v5, v1, -1
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0x83,0x01,0x00]
+
+v_sub_i32 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xe1,0x01,0x00]
+
+v_sub_i32 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xef,0x01,0x00]
+
+v_sub_i32 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xf7,0x01,0x00]
+
+v_sub_i32 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xf9,0x01,0x00]
+
+v_sub_i32 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x9d,0xd2,0x01,0xfb,0x01,0x00]
+
+v_sub_i32 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x9d,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i16 v5, v1, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i16 v255, v1, v2
+// CHECK: [0xff,0x00,0x9e,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i16 v5, v255, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0xff,0x05,0x02,0x00]
+
+v_add_i16 v5, s1, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x04,0x02,0x00]
+
+v_add_i16 v5, s101, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x65,0x04,0x02,0x00]
+
+v_add_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x66,0x04,0x02,0x00]
+
+v_add_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x67,0x04,0x02,0x00]
+
+v_add_i16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x6a,0x04,0x02,0x00]
+
+v_add_i16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x6b,0x04,0x02,0x00]
+
+v_add_i16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x7b,0x04,0x02,0x00]
+
+v_add_i16 v5, m0, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x7c,0x04,0x02,0x00]
+
+v_add_i16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x7e,0x04,0x02,0x00]
+
+v_add_i16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x7f,0x04,0x02,0x00]
+
+v_add_i16 v5, 0, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x80,0x04,0x02,0x00]
+
+v_add_i16 v5, -1, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0xc1,0x04,0x02,0x00]
+
+v_add_i16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0xfb,0x04,0x02,0x00]
+
+v_add_i16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0xfc,0x04,0x02,0x00]
+
+v_add_i16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0xfd,0x04,0x02,0x00]
+
+v_add_i16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x9e,0xd2,0xfe,0x04,0x02,0x00]
+
+v_add_i16 v5, v1, v255
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xff,0x03,0x00]
+
+v_add_i16 v5, v1, s2
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x00,0x00]
+
+v_add_i16 v5, v1, s101
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xcb,0x00,0x00]
+
+v_add_i16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xcd,0x00,0x00]
+
+v_add_i16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xcf,0x00,0x00]
+
+v_add_i16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd5,0x00,0x00]
+
+v_add_i16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xd7,0x00,0x00]
+
+v_add_i16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf7,0x00,0x00]
+
+v_add_i16 v5, v1, m0
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf9,0x00,0x00]
+
+v_add_i16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xfd,0x00,0x00]
+
+v_add_i16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xff,0x00,0x00]
+
+v_add_i16 v5, v1, 0
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x01,0x01,0x00]
+
+v_add_i16 v5, v1, -1
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x83,0x01,0x00]
+
+v_add_i16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf7,0x01,0x00]
+
+v_add_i16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xf9,0x01,0x00]
+
+v_add_i16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0xfb,0x01,0x00]
+
+v_add_i16 v5, v1, v2 op_sel:[0,0,0]
+// CHECK: [0x05,0x00,0x9e,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i16 v5, v1, v2 op_sel:[1,0,0]
+// CHECK: [0x05,0x08,0x9e,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i16 v5, v1, v2 op_sel:[0,1,0]
+// CHECK: [0x05,0x10,0x9e,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i16 v5, v1, v2 op_sel:[0,0,1]
+// CHECK: [0x05,0x40,0x9e,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i16 v5, v1, v2 op_sel:[1,1,1]
+// CHECK: [0x05,0x58,0x9e,0xd2,0x01,0x05,0x02,0x00]
+
+v_add_i16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x9e,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i16 v5, v1, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i16 v255, v1, v2
+// CHECK: [0xff,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i16 v5, v255, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0xff,0x05,0x02,0x00]
+
+v_sub_i16 v5, s1, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x04,0x02,0x00]
+
+v_sub_i16 v5, s101, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x65,0x04,0x02,0x00]
+
+v_sub_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x66,0x04,0x02,0x00]
+
+v_sub_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x67,0x04,0x02,0x00]
+
+v_sub_i16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x6a,0x04,0x02,0x00]
+
+v_sub_i16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x6b,0x04,0x02,0x00]
+
+v_sub_i16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x7b,0x04,0x02,0x00]
+
+v_sub_i16 v5, m0, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x7c,0x04,0x02,0x00]
+
+v_sub_i16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x7e,0x04,0x02,0x00]
+
+v_sub_i16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x7f,0x04,0x02,0x00]
+
+v_sub_i16 v5, 0, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x80,0x04,0x02,0x00]
+
+v_sub_i16 v5, -1, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0xc1,0x04,0x02,0x00]
+
+v_sub_i16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0xfb,0x04,0x02,0x00]
+
+v_sub_i16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0xfc,0x04,0x02,0x00]
+
+v_sub_i16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0xfd,0x04,0x02,0x00]
+
+v_sub_i16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x9f,0xd2,0xfe,0x04,0x02,0x00]
+
+v_sub_i16 v5, v1, v255
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xff,0x03,0x00]
+
+v_sub_i16 v5, v1, s2
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x00,0x00]
+
+v_sub_i16 v5, v1, s101
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xcb,0x00,0x00]
+
+v_sub_i16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xcd,0x00,0x00]
+
+v_sub_i16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xcf,0x00,0x00]
+
+v_sub_i16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xd5,0x00,0x00]
+
+v_sub_i16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xd7,0x00,0x00]
+
+v_sub_i16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xf7,0x00,0x00]
+
+v_sub_i16 v5, v1, m0
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xf9,0x00,0x00]
+
+v_sub_i16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xfd,0x00,0x00]
+
+v_sub_i16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xff,0x00,0x00]
+
+v_sub_i16 v5, v1, 0
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x01,0x01,0x00]
+
+v_sub_i16 v5, v1, -1
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x83,0x01,0x00]
+
+v_sub_i16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xf7,0x01,0x00]
+
+v_sub_i16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xf9,0x01,0x00]
+
+v_sub_i16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0xfb,0x01,0x00]
+
+v_sub_i16 v5, v1, v2 op_sel:[0,0,0]
+// CHECK: [0x05,0x00,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i16 v5, v1, v2 op_sel:[1,0,0]
+// CHECK: [0x05,0x08,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i16 v5, v1, v2 op_sel:[0,1,0]
+// CHECK: [0x05,0x10,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i16 v5, v1, v2 op_sel:[0,0,1]
+// CHECK: [0x05,0x40,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i16 v5, v1, v2 op_sel:[1,1,1]
+// CHECK: [0x05,0x58,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_sub_i16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x9f,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v255, v1, v2
+// CHECK: [0xff,0x00,0xa0,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v255, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0xff,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, s1, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, s101, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x65,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x66,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x67,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x6a,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x6b,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x7b,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, m0, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x7c,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x7e,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x7f,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, 0, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x80,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, -1, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0xc1,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, 0.5, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0xf0,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, -4.0, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0xf7,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0xfb,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0xfc,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0xfd,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0xfe,0x04,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v255
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xff,0x03,0x00]
+
+v_pack_b32_f16 v5, v1, s2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, s101
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xcb,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xcd,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xcf,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd5,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xd7,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf7,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, m0
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf9,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xfd,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xff,0x00,0x00]
+
+v_pack_b32_f16 v5, v1, 0
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x01,0x01,0x00]
+
+v_pack_b32_f16 v5, v1, -1
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x83,0x01,0x00]
+
+v_pack_b32_f16 v5, v1, 0.5
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xe1,0x01,0x00]
+
+v_pack_b32_f16 v5, v1, -4.0
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xef,0x01,0x00]
+
+v_pack_b32_f16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf7,0x01,0x00]
+
+v_pack_b32_f16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xf9,0x01,0x00]
+
+v_pack_b32_f16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0xfb,0x01,0x00]
+
+v_pack_b32_f16 v5, -v1, v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x20]
+
+v_pack_b32_f16 v5, v1, -v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x40]
+
+v_pack_b32_f16 v5, -v1, -v2
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x60]
+
+v_pack_b32_f16 v5, |v1|, v2
+// CHECK: [0x05,0x01,0xa0,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, |v2|
+// CHECK: [0x05,0x02,0xa0,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, |v1|, |v2|
+// CHECK: [0x05,0x03,0xa0,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,0]
+// CHECK: [0x05,0x00,0xa0,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[1,0,0]
+// CHECK: [0x05,0x08,0xa0,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[0,1,0]
+// CHECK: [0x05,0x10,0xa0,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[0,0,1]
+// CHECK: [0x05,0x40,0xa0,0xd2,0x01,0x05,0x02,0x00]
+
+v_pack_b32_f16 v5, v1, v2 op_sel:[1,1,1]
+// CHECK: [0x05,0x58,0xa0,0xd2,0x01,0x05,0x02,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s b/llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s
new file mode 100644
index 0000000000000..690b83bdcbf1a
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vop3p.s
@@ -0,0 +1,3484 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+v_pk_mad_i16 v5, v1, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_i16 v255, v1, v2, v3
+// CHECK: [0xff,0x40,0x80,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_i16 v5, v255, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0xff,0x05,0x0e,0x1c]
+
+v_pk_mad_i16 v5, s1, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, s101, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x65,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x66,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x67,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x6a,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x6b,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x7b,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, m0, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x7c,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x7e,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x7f,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, 0, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x80,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, -1, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0xc1,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0xfb,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0xfc,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0xfd,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0xfe,0x04,0x0e,0x1c]
+
+v_pk_mad_i16 v5, v1, v255, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xff,0x0f,0x1c]
+
+v_pk_mad_i16 v5, v1, s2, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, s101, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xcb,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xcd,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xcf,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xd5,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xd7,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xf7,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, m0, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xf9,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xfd,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xff,0x0c,0x1c]
+
+v_pk_mad_i16 v5, v1, 0, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x01,0x0d,0x1c]
+
+v_pk_mad_i16 v5, v1, -1, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x83,0x0d,0x1c]
+
+v_pk_mad_i16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xf7,0x0d,0x1c]
+
+v_pk_mad_i16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xf9,0x0d,0x1c]
+
+v_pk_mad_i16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0xfb,0x0d,0x1c]
+
+v_pk_mad_i16 v5, v1, v2, v255
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xfe,0x1f]
+
+v_pk_mad_i16 v5, v1, v2, s3
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x18]
+
+v_pk_mad_i16 v5, v1, v2, s101
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x96,0x19]
+
+v_pk_mad_i16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x9a,0x19]
+
+v_pk_mad_i16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x9e,0x19]
+
+v_pk_mad_i16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xaa,0x19]
+
+v_pk_mad_i16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xae,0x19]
+
+v_pk_mad_i16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xee,0x19]
+
+v_pk_mad_i16 v5, v1, v2, m0
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xf2,0x19]
+
+v_pk_mad_i16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xfa,0x19]
+
+v_pk_mad_i16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xfe,0x19]
+
+v_pk_mad_i16 v5, v1, v2, 0
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x02,0x1a]
+
+v_pk_mad_i16 v5, v1, v2, -1
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x06,0x1b]
+
+v_pk_mad_i16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xee,0x1b]
+
+v_pk_mad_i16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xf2,0x1b]
+
+v_pk_mad_i16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0xf6,0x1b]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel:[0,0,0]
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel:[1,0,0]
+// CHECK: [0x05,0x48,0x80,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel:[0,1,0]
+// CHECK: [0x05,0x50,0x80,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel:[0,0,1]
+// CHECK: [0x05,0x60,0x80,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel:[1,1,1]
+// CHECK: [0x05,0x78,0x80,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel_hi:[1,1,1]
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
+// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x05,0x0e,0x04]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
+// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
+// CHECK: [0x05,0x00,0x80,0xd3,0x01,0x05,0x0e,0x14]
+
+v_pk_mad_i16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
+// CHECK: [0x05,0x40,0x80,0xd3,0x01,0x05,0x0e,0x04]
+
+v_pk_mad_i16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0xc0,0x80,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mul_lo_u16 v5, v1, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_lo_u16 v255, v1, v2
+// CHECK: [0xff,0x00,0x81,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, v255, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, s1, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, s101, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, m0, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, 0, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, -1, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x81,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, v1, v255
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_mul_lo_u16 v5, v1, s2
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, s101
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, m0
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_mul_lo_u16 v5, v1, 0
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_mul_lo_u16 v5, v1, -1
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_mul_lo_u16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_mul_lo_u16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_mul_lo_u16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_mul_lo_u16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x81,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x81,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x81,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_lo_u16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_mul_lo_u16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_mul_lo_u16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x81,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_add_i16 v5, v1, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_i16 v255, v1, v2
+// CHECK: [0xff,0x00,0x82,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_i16 v5, v255, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_add_i16 v5, s1, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, s101, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, m0, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, 0, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, -1, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x82,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_add_i16 v5, v1, v255
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_add_i16 v5, v1, s2
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_add_i16 v5, v1, s101
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_add_i16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_add_i16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_add_i16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_add_i16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_add_i16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_add_i16 v5, v1, m0
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_add_i16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_add_i16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_add_i16 v5, v1, 0
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_add_i16 v5, v1, -1
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_add_i16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_add_i16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_add_i16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_add_i16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_i16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x82,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_i16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x82,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_i16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x82,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_i16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_i16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_add_i16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_add_i16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x82,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_add_i16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x82,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_i16 v5, v1, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_i16 v255, v1, v2
+// CHECK: [0xff,0x00,0x83,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_i16 v5, v255, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_sub_i16 v5, s1, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, s101, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, m0, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, 0, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, -1, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x83,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_sub_i16 v5, v1, v255
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_sub_i16 v5, v1, s2
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, s101
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, m0
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_sub_i16 v5, v1, 0
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_sub_i16 v5, v1, -1
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_sub_i16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_sub_i16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_sub_i16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_sub_i16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_i16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x83,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_i16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x83,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_i16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x83,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_i16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_i16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_sub_i16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_sub_i16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x83,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_sub_i16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x83,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, v1, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v255, v1, v2
+// CHECK: [0xff,0x00,0x84,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, v255, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, s1, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, s101, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, m0, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, 0, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, -1, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x84,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, v1, v255
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_lshlrev_b16 v5, v1, s2
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, s101
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, m0
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_lshlrev_b16 v5, v1, 0
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_lshlrev_b16 v5, v1, -1
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_lshlrev_b16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_lshlrev_b16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_lshlrev_b16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_lshlrev_b16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x84,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x84,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x84,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshlrev_b16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_lshlrev_b16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_lshlrev_b16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x84,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_lshrrev_b16 v5, v1, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshrrev_b16 v255, v1, v2
+// CHECK: [0xff,0x00,0x85,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, v255, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, s1, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, s101, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, m0, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, 0, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, -1, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x85,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, v1, v255
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_lshrrev_b16 v5, v1, s2
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, s101
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, m0
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_lshrrev_b16 v5, v1, 0
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_lshrrev_b16 v5, v1, -1
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_lshrrev_b16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_lshrrev_b16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_lshrrev_b16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_lshrrev_b16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x85,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x85,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x85,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_lshrrev_b16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_lshrrev_b16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_lshrrev_b16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x85,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_ashrrev_i16 v5, v1, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_ashrrev_i16 v255, v1, v2
+// CHECK: [0xff,0x00,0x86,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, v255, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, s1, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, s101, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, m0, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, 0, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, -1, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x86,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, v1, v255
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_ashrrev_i16 v5, v1, s2
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, s101
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, m0
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_ashrrev_i16 v5, v1, 0
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_ashrrev_i16 v5, v1, -1
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_ashrrev_i16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_ashrrev_i16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_ashrrev_i16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_ashrrev_i16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x86,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x86,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x86,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_ashrrev_i16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_ashrrev_i16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_ashrrev_i16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x86,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_max_i16 v5, v1, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_i16 v255, v1, v2
+// CHECK: [0xff,0x00,0x87,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_i16 v5, v255, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_max_i16 v5, s1, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, s101, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, m0, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, 0, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, -1, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x87,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_max_i16 v5, v1, v255
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_max_i16 v5, v1, s2
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_max_i16 v5, v1, s101
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_max_i16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_max_i16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_max_i16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_max_i16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_max_i16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_max_i16 v5, v1, m0
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_max_i16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_max_i16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_max_i16 v5, v1, 0
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_max_i16 v5, v1, -1
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_max_i16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_max_i16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_max_i16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_max_i16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_i16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x87,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_i16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x87,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_i16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x87,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_i16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_i16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_max_i16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_max_i16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x87,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_min_i16 v5, v1, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_i16 v255, v1, v2
+// CHECK: [0xff,0x00,0x88,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_i16 v5, v255, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_min_i16 v5, s1, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, s101, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, m0, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, 0, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, -1, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x88,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_min_i16 v5, v1, v255
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_min_i16 v5, v1, s2
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_min_i16 v5, v1, s101
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_min_i16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_min_i16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_min_i16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_min_i16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_min_i16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_min_i16 v5, v1, m0
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_min_i16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_min_i16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_min_i16 v5, v1, 0
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_min_i16 v5, v1, -1
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_min_i16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_min_i16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_min_i16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_min_i16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_i16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x88,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_i16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x88,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_i16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x88,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_i16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_i16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_min_i16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_min_i16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x88,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_mad_u16 v5, v1, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_u16 v255, v1, v2, v3
+// CHECK: [0xff,0x40,0x89,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_u16 v5, v255, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0xff,0x05,0x0e,0x1c]
+
+v_pk_mad_u16 v5, s1, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, s101, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x65,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x66,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x67,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x6a,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x6b,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x7b,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, m0, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x7c,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x7e,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x7f,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, 0, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x80,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, -1, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0xc1,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0xfb,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0xfc,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0xfd,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0xfe,0x04,0x0e,0x1c]
+
+v_pk_mad_u16 v5, v1, v255, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xff,0x0f,0x1c]
+
+v_pk_mad_u16 v5, v1, s2, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, s101, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xcb,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xcd,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xcf,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xd5,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xd7,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xf7,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, m0, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xf9,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xfd,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xff,0x0c,0x1c]
+
+v_pk_mad_u16 v5, v1, 0, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x01,0x0d,0x1c]
+
+v_pk_mad_u16 v5, v1, -1, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x83,0x0d,0x1c]
+
+v_pk_mad_u16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xf7,0x0d,0x1c]
+
+v_pk_mad_u16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xf9,0x0d,0x1c]
+
+v_pk_mad_u16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0xfb,0x0d,0x1c]
+
+v_pk_mad_u16 v5, v1, v2, v255
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xfe,0x1f]
+
+v_pk_mad_u16 v5, v1, v2, s3
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0e,0x18]
+
+v_pk_mad_u16 v5, v1, v2, s101
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x96,0x19]
+
+v_pk_mad_u16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x9a,0x19]
+
+v_pk_mad_u16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x9e,0x19]
+
+v_pk_mad_u16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xaa,0x19]
+
+v_pk_mad_u16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xae,0x19]
+
+v_pk_mad_u16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xee,0x19]
+
+v_pk_mad_u16 v5, v1, v2, m0
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xf2,0x19]
+
+v_pk_mad_u16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xfa,0x19]
+
+v_pk_mad_u16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xfe,0x19]
+
+v_pk_mad_u16 v5, v1, v2, 0
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x02,0x1a]
+
+v_pk_mad_u16 v5, v1, v2, -1
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x06,0x1b]
+
+v_pk_mad_u16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xee,0x1b]
+
+v_pk_mad_u16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xf2,0x1b]
+
+v_pk_mad_u16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0xf6,0x1b]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel:[0,0,0]
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel:[1,0,0]
+// CHECK: [0x05,0x48,0x89,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel:[0,1,0]
+// CHECK: [0x05,0x50,0x89,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel:[0,0,1]
+// CHECK: [0x05,0x60,0x89,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel:[1,1,1]
+// CHECK: [0x05,0x78,0x89,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel_hi:[1,1,1]
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
+// CHECK: [0x05,0x00,0x89,0xd3,0x01,0x05,0x0e,0x04]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
+// CHECK: [0x05,0x00,0x89,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
+// CHECK: [0x05,0x00,0x89,0xd3,0x01,0x05,0x0e,0x14]
+
+v_pk_mad_u16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
+// CHECK: [0x05,0x40,0x89,0xd3,0x01,0x05,0x0e,0x04]
+
+v_pk_mad_u16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0xc0,0x89,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_add_u16 v5, v1, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_u16 v255, v1, v2
+// CHECK: [0xff,0x00,0x8a,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_u16 v5, v255, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_add_u16 v5, s1, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, s101, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, m0, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, 0, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, -1, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8a,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_add_u16 v5, v1, v255
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_add_u16 v5, v1, s2
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_add_u16 v5, v1, s101
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_add_u16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_add_u16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_add_u16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_add_u16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_add_u16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_add_u16 v5, v1, m0
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_add_u16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_add_u16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_add_u16 v5, v1, 0
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_add_u16 v5, v1, -1
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_add_u16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_add_u16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_add_u16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_add_u16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_u16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x8a,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_u16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x8a,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_u16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x8a,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_u16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_u16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_add_u16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_add_u16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x8a,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_add_u16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x8a,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_u16 v5, v1, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_u16 v255, v1, v2
+// CHECK: [0xff,0x00,0x8b,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_u16 v5, v255, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_sub_u16 v5, s1, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, s101, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, m0, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, 0, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, -1, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8b,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_sub_u16 v5, v1, v255
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_sub_u16 v5, v1, s2
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, s101
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, m0
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_sub_u16 v5, v1, 0
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_sub_u16 v5, v1, -1
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_sub_u16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_sub_u16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_sub_u16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_sub_u16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_u16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x8b,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_u16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x8b,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_u16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x8b,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_u16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_sub_u16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_sub_u16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_sub_u16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x8b,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_sub_u16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x8b,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_u16 v5, v1, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_u16 v255, v1, v2
+// CHECK: [0xff,0x00,0x8c,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_u16 v5, v255, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_max_u16 v5, s1, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, s101, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, m0, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, 0, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, -1, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8c,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_max_u16 v5, v1, v255
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_max_u16 v5, v1, s2
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_max_u16 v5, v1, s101
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_max_u16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_max_u16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_max_u16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_max_u16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_max_u16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_max_u16 v5, v1, m0
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_max_u16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_max_u16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_max_u16 v5, v1, 0
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_max_u16 v5, v1, -1
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_max_u16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_max_u16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_max_u16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_max_u16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_u16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x8c,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_u16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x8c,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_u16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x8c,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_u16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_u16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_max_u16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_max_u16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x8c,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_min_u16 v5, v1, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_u16 v255, v1, v2
+// CHECK: [0xff,0x00,0x8d,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_u16 v5, v255, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_min_u16 v5, s1, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, s101, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, m0, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, 0, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, -1, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8d,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_min_u16 v5, v1, v255
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_min_u16 v5, v1, s2
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_min_u16 v5, v1, s101
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_min_u16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_min_u16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_min_u16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_min_u16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_min_u16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_min_u16 v5, v1, m0
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_min_u16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_min_u16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_min_u16 v5, v1, 0
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_min_u16 v5, v1, -1
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_min_u16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_min_u16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_min_u16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_min_u16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_u16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x8d,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_u16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x8d,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_u16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x8d,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_u16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_u16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_min_u16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_min_u16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x8d,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_fma_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0xff,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x65,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x66,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x67,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x6a,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x6b,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x7b,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x7c,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x7e,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x7f,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x80,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0xc1,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0xf0,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0xf7,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0xfb,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0xfc,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0xfd,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0xfe,0x04,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xff,0x0f,0x1c]
+
+v_pk_fma_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xcb,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xcd,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xcf,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xd5,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xd7,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xf7,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xf9,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xfd,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xff,0x0c,0x1c]
+
+v_pk_fma_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x01,0x0d,0x1c]
+
+v_pk_fma_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x83,0x0d,0x1c]
+
+v_pk_fma_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xe1,0x0d,0x1c]
+
+v_pk_fma_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xef,0x0d,0x1c]
+
+v_pk_fma_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xf7,0x0d,0x1c]
+
+v_pk_fma_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xf9,0x0d,0x1c]
+
+v_pk_fma_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0xfb,0x0d,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xfe,0x1f]
+
+v_pk_fma_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x18]
+
+v_pk_fma_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x96,0x19]
+
+v_pk_fma_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x9a,0x19]
+
+v_pk_fma_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x9e,0x19]
+
+v_pk_fma_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xaa,0x19]
+
+v_pk_fma_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xae,0x19]
+
+v_pk_fma_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xee,0x19]
+
+v_pk_fma_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xf2,0x19]
+
+v_pk_fma_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xfa,0x19]
+
+v_pk_fma_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xfe,0x19]
+
+v_pk_fma_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x02,0x1a]
+
+v_pk_fma_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x06,0x1b]
+
+v_pk_fma_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xc2,0x1b]
+
+v_pk_fma_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xde,0x1b]
+
+v_pk_fma_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xee,0x1b]
+
+v_pk_fma_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xf2,0x1b]
+
+v_pk_fma_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0xf6,0x1b]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel:[0,0,0]
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel:[1,0,0]
+// CHECK: [0x05,0x48,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel:[0,1,0]
+// CHECK: [0x05,0x50,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel:[0,0,1]
+// CHECK: [0x05,0x60,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel:[1,1,1]
+// CHECK: [0x05,0x78,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1]
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
+// CHECK: [0x05,0x00,0x8e,0xd3,0x01,0x05,0x0e,0x04]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
+// CHECK: [0x05,0x00,0x8e,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
+// CHECK: [0x05,0x00,0x8e,0xd3,0x01,0x05,0x0e,0x14]
+
+v_pk_fma_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x04]
+
+v_pk_fma_f16 v5, v1, v2, v3 neg_lo:[1,0,0]
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x3c]
+
+v_pk_fma_f16 v5, v1, v2, v3 neg_lo:[0,1,0]
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x5c]
+
+v_pk_fma_f16 v5, v1, v2, v3 neg_lo:[0,0,1]
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0x9c]
+
+v_pk_fma_f16 v5, v1, v2, v3 neg_lo:[1,1,1]
+// CHECK: [0x05,0x40,0x8e,0xd3,0x01,0x05,0x0e,0xfc]
+
+v_pk_fma_f16 v5, v1, v2, v3 neg_hi:[1,0,0]
+// CHECK: [0x05,0x41,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 neg_hi:[0,1,0]
+// CHECK: [0x05,0x42,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 neg_hi:[0,0,1]
+// CHECK: [0x05,0x44,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 neg_hi:[1,1,1]
+// CHECK: [0x05,0x47,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_fma_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0xc0,0x8e,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_pk_add_f16 v5, v1, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v255, v1, v2
+// CHECK: [0xff,0x00,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v255, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, s1, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, s101, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, m0, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, 0, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, -1, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0xf0,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0xf7,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x8f,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_add_f16 v5, v1, v255
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_add_f16 v5, v1, s2
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_add_f16 v5, v1, s101
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_add_f16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_add_f16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_add_f16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_add_f16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_add_f16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_add_f16 v5, v1, m0
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_add_f16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_add_f16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_add_f16 v5, v1, 0
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_add_f16 v5, v1, -1
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_add_f16 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xe1,0x01,0x18]
+
+v_pk_add_f16 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xef,0x01,0x18]
+
+v_pk_add_f16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_add_f16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_add_f16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_add_f16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_add_f16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_add_f16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_add_f16 v5, v1, v2 neg_lo:[1,0]
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x38]
+
+v_pk_add_f16 v5, v1, v2 neg_lo:[0,1]
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x58]
+
+v_pk_add_f16 v5, v1, v2 neg_lo:[1,1]
+// CHECK: [0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x78]
+
+v_pk_add_f16 v5, v1, v2 neg_hi:[1,0]
+// CHECK: [0x05,0x01,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v1, v2 neg_hi:[0,1]
+// CHECK: [0x05,0x02,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v1, v2 neg_hi:[1,1]
+// CHECK: [0x05,0x03,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_add_f16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x8f,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v255, v1, v2
+// CHECK: [0xff,0x00,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v255, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, s1, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, s101, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, m0, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, 0, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, -1, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0xf0,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0xf7,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x90,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v255
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_mul_f16 v5, v1, s2
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, s101
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, m0
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_mul_f16 v5, v1, 0
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_mul_f16 v5, v1, -1
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_mul_f16 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xe1,0x01,0x18]
+
+v_pk_mul_f16 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xef,0x01,0x18]
+
+v_pk_mul_f16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_mul_f16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_mul_f16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_mul_f16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_mul_f16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_mul_f16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_mul_f16 v5, v1, v2 neg_lo:[1,0]
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x38]
+
+v_pk_mul_f16 v5, v1, v2 neg_lo:[0,1]
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x58]
+
+v_pk_mul_f16 v5, v1, v2 neg_lo:[1,1]
+// CHECK: [0x05,0x00,0x90,0xd3,0x01,0x05,0x02,0x78]
+
+v_pk_mul_f16 v5, v1, v2 neg_hi:[1,0]
+// CHECK: [0x05,0x01,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v2 neg_hi:[0,1]
+// CHECK: [0x05,0x02,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v2 neg_hi:[1,1]
+// CHECK: [0x05,0x03,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_mul_f16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x90,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v255, v1, v2
+// CHECK: [0xff,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v255, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, s1, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, s101, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, m0, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, 0, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, -1, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0xf0,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0xf7,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x91,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v255
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_min_f16 v5, v1, s2
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_min_f16 v5, v1, s101
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_min_f16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_min_f16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_min_f16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_min_f16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_min_f16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_min_f16 v5, v1, m0
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_min_f16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_min_f16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_min_f16 v5, v1, 0
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_min_f16 v5, v1, -1
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_min_f16 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xe1,0x01,0x18]
+
+v_pk_min_f16 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xef,0x01,0x18]
+
+v_pk_min_f16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_min_f16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_min_f16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_min_f16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_min_f16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_min_f16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_min_f16 v5, v1, v2 neg_lo:[1,0]
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x38]
+
+v_pk_min_f16 v5, v1, v2 neg_lo:[0,1]
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x58]
+
+v_pk_min_f16 v5, v1, v2 neg_lo:[1,1]
+// CHECK: [0x05,0x00,0x91,0xd3,0x01,0x05,0x02,0x78]
+
+v_pk_min_f16 v5, v1, v2 neg_hi:[1,0]
+// CHECK: [0x05,0x01,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v2 neg_hi:[0,1]
+// CHECK: [0x05,0x02,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v2 neg_hi:[1,1]
+// CHECK: [0x05,0x03,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_min_f16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x91,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v255, v1, v2
+// CHECK: [0xff,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v255, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0xff,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, s1, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, s101, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x65,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, flat_scratch_lo, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x66,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, flat_scratch_hi, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x67,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, vcc_lo, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x6a,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, vcc_hi, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x6b,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, ttmp15, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x7b,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, m0, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x7c,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, exec_lo, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x7e,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, exec_hi, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x7f,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, 0, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0x80,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, -1, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0xc1,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, 0.5, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0xf0,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, -4.0, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0xf7,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, src_vccz, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0xfb,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, src_execz, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0xfc,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, src_scc, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0xfd,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, src_lds_direct, v2
+// CHECK: [0x05,0x00,0x92,0xd3,0xfe,0x04,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v255
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xff,0x03,0x18]
+
+v_pk_max_f16 v5, v1, s2
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x00,0x18]
+
+v_pk_max_f16 v5, v1, s101
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xcb,0x00,0x18]
+
+v_pk_max_f16 v5, v1, flat_scratch_lo
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xcd,0x00,0x18]
+
+v_pk_max_f16 v5, v1, flat_scratch_hi
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xcf,0x00,0x18]
+
+v_pk_max_f16 v5, v1, vcc_lo
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xd5,0x00,0x18]
+
+v_pk_max_f16 v5, v1, vcc_hi
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xd7,0x00,0x18]
+
+v_pk_max_f16 v5, v1, ttmp15
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xf7,0x00,0x18]
+
+v_pk_max_f16 v5, v1, m0
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xf9,0x00,0x18]
+
+v_pk_max_f16 v5, v1, exec_lo
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xfd,0x00,0x18]
+
+v_pk_max_f16 v5, v1, exec_hi
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xff,0x00,0x18]
+
+v_pk_max_f16 v5, v1, 0
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x01,0x01,0x18]
+
+v_pk_max_f16 v5, v1, -1
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x83,0x01,0x18]
+
+v_pk_max_f16 v5, v1, 0.5
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xe1,0x01,0x18]
+
+v_pk_max_f16 v5, v1, -4.0
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xef,0x01,0x18]
+
+v_pk_max_f16 v5, v1, src_vccz
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xf7,0x01,0x18]
+
+v_pk_max_f16 v5, v1, src_execz
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xf9,0x01,0x18]
+
+v_pk_max_f16 v5, v1, src_scc
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0xfb,0x01,0x18]
+
+v_pk_max_f16 v5, v1, v2 op_sel:[0,0]
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v2 op_sel:[1,0]
+// CHECK: [0x05,0x08,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v2 op_sel:[0,1]
+// CHECK: [0x05,0x10,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v2 op_sel:[1,1]
+// CHECK: [0x05,0x18,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v2 op_sel_hi:[1,1]
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v2 op_sel_hi:[0,0]
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x00]
+
+v_pk_max_f16 v5, v1, v2 op_sel_hi:[1,0]
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x08]
+
+v_pk_max_f16 v5, v1, v2 op_sel_hi:[0,1]
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x10]
+
+v_pk_max_f16 v5, v1, v2 neg_lo:[1,0]
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x38]
+
+v_pk_max_f16 v5, v1, v2 neg_lo:[0,1]
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x58]
+
+v_pk_max_f16 v5, v1, v2 neg_lo:[1,1]
+// CHECK: [0x05,0x00,0x92,0xd3,0x01,0x05,0x02,0x78]
+
+v_pk_max_f16 v5, v1, v2 neg_hi:[1,0]
+// CHECK: [0x05,0x01,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v2 neg_hi:[0,1]
+// CHECK: [0x05,0x02,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v2 neg_hi:[1,1]
+// CHECK: [0x05,0x03,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_pk_max_f16 v5, v1, v2 clamp
+// CHECK: [0x05,0x80,0x92,0xd3,0x01,0x05,0x02,0x18]
+
+v_mad_mix_f32 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0xff,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x65,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x66,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x67,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x6a,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x6b,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x7b,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x7c,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x7e,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x7f,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x80,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0xc1,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0xf0,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0xf7,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0xfb,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0xfc,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0xfd,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0xfe,0x04,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0f,0x04]
+
+v_mad_mix_f32 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xcb,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xcd,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xcf,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xd5,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xd7,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xf7,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xfd,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xff,0x0c,0x04]
+
+v_mad_mix_f32 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x01,0x0d,0x04]
+
+v_mad_mix_f32 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x83,0x0d,0x04]
+
+v_mad_mix_f32 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xe1,0x0d,0x04]
+
+v_mad_mix_f32 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xef,0x0d,0x04]
+
+v_mad_mix_f32 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xf7,0x0d,0x04]
+
+v_mad_mix_f32 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xf9,0x0d,0x04]
+
+v_mad_mix_f32 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0xfb,0x0d,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x07]
+
+v_mad_mix_f32 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x00]
+
+v_mad_mix_f32 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x96,0x01]
+
+v_mad_mix_f32 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9a,0x01]
+
+v_mad_mix_f32 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x9e,0x01]
+
+v_mad_mix_f32 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xaa,0x01]
+
+v_mad_mix_f32 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xae,0x01]
+
+v_mad_mix_f32 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xee,0x01]
+
+v_mad_mix_f32 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x01]
+
+v_mad_mix_f32 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfa,0x01]
+
+v_mad_mix_f32 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xfe,0x01]
+
+v_mad_mix_f32 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x02,0x02]
+
+v_mad_mix_f32 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x06,0x03]
+
+v_mad_mix_f32 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xc2,0x03]
+
+v_mad_mix_f32 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xde,0x03]
+
+v_mad_mix_f32 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xee,0x03]
+
+v_mad_mix_f32 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xf2,0x03]
+
+v_mad_mix_f32 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0xf6,0x03]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,0]
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,0,0]
+// CHECK: [0x05,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,1,0]
+// CHECK: [0x05,0x10,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[0,0,1]
+// CHECK: [0x05,0x20,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel:[1,1,1]
+// CHECK: [0x05,0x38,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,0]
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,0,0]
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,1,0]
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x14]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[0,0,1]
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v3 op_sel_hi:[1,1,1]
+// CHECK: [0x05,0x40,0xa0,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mix_f32 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x24]
+
+v_mad_mix_f32 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x44]
+
+v_mad_mix_f32 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x84]
+
+v_mad_mix_f32 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xa0,0xd3,0x01,0x05,0x0e,0xe4]
+
+v_mad_mix_f32 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mix_f32 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xa0,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0xff,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x65,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x66,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x67,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x6a,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x6b,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x7b,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x7c,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x7e,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x7f,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x80,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0xc1,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0xf0,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0xf7,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0xfb,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0xfc,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0xfd,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0xfe,0x04,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0f,0x04]
+
+v_mad_mixlo_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xcb,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xcd,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xcf,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xd5,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xd7,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xf7,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xf9,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xfd,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xff,0x0c,0x04]
+
+v_mad_mixlo_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x01,0x0d,0x04]
+
+v_mad_mixlo_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x83,0x0d,0x04]
+
+v_mad_mixlo_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xe1,0x0d,0x04]
+
+v_mad_mixlo_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xef,0x0d,0x04]
+
+v_mad_mixlo_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xf7,0x0d,0x04]
+
+v_mad_mixlo_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xf9,0x0d,0x04]
+
+v_mad_mixlo_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0xfb,0x0d,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x07]
+
+v_mad_mixlo_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x00]
+
+v_mad_mixlo_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x96,0x01]
+
+v_mad_mixlo_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9a,0x01]
+
+v_mad_mixlo_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x9e,0x01]
+
+v_mad_mixlo_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xaa,0x01]
+
+v_mad_mixlo_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xae,0x01]
+
+v_mad_mixlo_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xee,0x01]
+
+v_mad_mixlo_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xf2,0x01]
+
+v_mad_mixlo_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfa,0x01]
+
+v_mad_mixlo_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xfe,0x01]
+
+v_mad_mixlo_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x02,0x02]
+
+v_mad_mixlo_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x06,0x03]
+
+v_mad_mixlo_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xc2,0x03]
+
+v_mad_mixlo_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xde,0x03]
+
+v_mad_mixlo_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xee,0x03]
+
+v_mad_mixlo_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xf2,0x03]
+
+v_mad_mixlo_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0xf6,0x03]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,0,0]
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,0,0]
+// CHECK: [0x05,0x08,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,1,0]
+// CHECK: [0x05,0x10,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[0,0,1]
+// CHECK: [0x05,0x20,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel:[1,1,1]
+// CHECK: [0x05,0x38,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x14]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1]
+// CHECK: [0x05,0x40,0xa1,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixlo_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x24]
+
+v_mad_mixlo_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x44]
+
+v_mad_mixlo_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0x84]
+
+v_mad_mixlo_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xa1,0xd3,0x01,0x05,0x0e,0xe4]
+
+v_mad_mixlo_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixlo_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xa1,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v255, v1, v2, v3
+// CHECK: [0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v255, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, s1, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, s101, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, flat_scratch_lo, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x66,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, flat_scratch_hi, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x67,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, vcc_lo, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, vcc_hi, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, ttmp15, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x7b,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, m0, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, exec_lo, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x7e,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, exec_hi, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x7f,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, 0, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x80,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, -1, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0xc1,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, 0.5, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0xf0,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, -4.0, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0xf7,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, src_vccz, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0xfb,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, src_execz, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0xfc,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, src_scc, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0xfd,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, src_lds_direct, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0xfe,0x04,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v255, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0f,0x04]
+
+v_mad_mixhi_f16 v5, v1, s2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, s101, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xcb,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, flat_scratch_lo, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xcd,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, flat_scratch_hi, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xcf,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, vcc_lo, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xd5,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, vcc_hi, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xd7,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, ttmp15, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xf7,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, m0, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xf9,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, exec_lo, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xfd,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, exec_hi, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xff,0x0c,0x04]
+
+v_mad_mixhi_f16 v5, v1, 0, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x01,0x0d,0x04]
+
+v_mad_mixhi_f16 v5, v1, -1, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x83,0x0d,0x04]
+
+v_mad_mixhi_f16 v5, v1, 0.5, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xe1,0x0d,0x04]
+
+v_mad_mixhi_f16 v5, v1, -4.0, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xef,0x0d,0x04]
+
+v_mad_mixhi_f16 v5, v1, src_vccz, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xf7,0x0d,0x04]
+
+v_mad_mixhi_f16 v5, v1, src_execz, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xf9,0x0d,0x04]
+
+v_mad_mixhi_f16 v5, v1, src_scc, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0xfb,0x0d,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v255
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x07]
+
+v_mad_mixhi_f16 v5, v1, v2, s3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x00]
+
+v_mad_mixhi_f16 v5, v1, v2, s101
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x96,0x01]
+
+v_mad_mixhi_f16 v5, v1, v2, flat_scratch_lo
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9a,0x01]
+
+v_mad_mixhi_f16 v5, v1, v2, flat_scratch_hi
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x9e,0x01]
+
+v_mad_mixhi_f16 v5, v1, v2, vcc_lo
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xaa,0x01]
+
+v_mad_mixhi_f16 v5, v1, v2, vcc_hi
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xae,0x01]
+
+v_mad_mixhi_f16 v5, v1, v2, ttmp15
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xee,0x01]
+
+v_mad_mixhi_f16 v5, v1, v2, m0
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xf2,0x01]
+
+v_mad_mixhi_f16 v5, v1, v2, exec_lo
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfa,0x01]
+
+v_mad_mixhi_f16 v5, v1, v2, exec_hi
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xfe,0x01]
+
+v_mad_mixhi_f16 v5, v1, v2, 0
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x02,0x02]
+
+v_mad_mixhi_f16 v5, v1, v2, -1
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x06,0x03]
+
+v_mad_mixhi_f16 v5, v1, v2, 0.5
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xc2,0x03]
+
+v_mad_mixhi_f16 v5, v1, v2, -4.0
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xde,0x03]
+
+v_mad_mixhi_f16 v5, v1, v2, src_vccz
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xee,0x03]
+
+v_mad_mixhi_f16 v5, v1, v2, src_execz
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xf2,0x03]
+
+v_mad_mixhi_f16 v5, v1, v2, src_scc
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0xf6,0x03]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,0,0]
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,0,0]
+// CHECK: [0x05,0x08,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,1,0]
+// CHECK: [0x05,0x10,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[0,0,1]
+// CHECK: [0x05,0x20,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel:[1,1,1]
+// CHECK: [0x05,0x38,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,0,0]
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,0,0]
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x0c]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,1,0]
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x14]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[0,0,1]
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 op_sel_hi:[1,1,1]
+// CHECK: [0x05,0x40,0xa2,0xd3,0x01,0x05,0x0e,0x1c]
+
+v_mad_mixhi_f16 v5, -v1, v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x24]
+
+v_mad_mixhi_f16 v5, v1, -v2, v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x44]
+
+v_mad_mixhi_f16 v5, v1, v2, -v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x84]
+
+v_mad_mixhi_f16 v5, -v1, -v2, -v3
+// CHECK: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0xe4]
+
+v_mad_mixhi_f16 v5, |v1|, v2, v3
+// CHECK: [0x05,0x01,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, |v2|, v3
+// CHECK: [0x05,0x02,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, |v3|
+// CHECK: [0x05,0x04,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, |v1|, |v2|, |v3|
+// CHECK: [0x05,0x07,0xa2,0xd3,0x01,0x05,0x0e,0x04]
+
+v_mad_mixhi_f16 v5, v1, v2, v3 clamp
+// CHECK: [0x05,0x80,0xa2,0xd3,0x01,0x05,0x0e,0x04]
diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_vopc.s b/llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
new file mode 100644
index 0000000000000..9d97f20cf0161
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx9_asm_vopc.s
@@ -0,0 +1,29311 @@
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s
+
+v_cmp_class_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x20,0x7c]
+
+v_cmp_class_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x20,0x7c]
+
+v_cmp_class_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x20,0x7c]
+
+v_cmp_class_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x20,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_class_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x20,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_class_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x21,0x7c]
+
+v_cmpx_class_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x22,0x7c]
+
+v_cmpx_class_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x22,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x22,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_class_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x23,0x7c]
+
+v_cmp_class_f64 vcc, v[1:2], v2
+// CHECK: [0x01,0x05,0x24,0x7c]
+
+v_cmp_class_f64 vcc, v[254:255], v2
+// CHECK: [0xfe,0x05,0x24,0x7c]
+
+v_cmp_class_f64 vcc, s[2:3], v2
+// CHECK: [0x02,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, s[4:5], v2
+// CHECK: [0x04,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, s[100:101], v2
+// CHECK: [0x64,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, flat_scratch, v2
+// CHECK: [0x66,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, vcc, v2
+// CHECK: [0x6a,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, ttmp[14:15], v2
+// CHECK: [0x7a,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, exec, v2
+// CHECK: [0x7e,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, 0, v2
+// CHECK: [0x80,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x24,0x7c]
+
+v_cmp_class_f64 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x24,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_class_f64 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x24,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_class_f64 vcc, v[1:2], v255
+// CHECK: [0x01,0xff,0x25,0x7c]
+
+v_cmpx_class_f64 vcc, v[1:2], v2
+// CHECK: [0x01,0x05,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, v[254:255], v2
+// CHECK: [0xfe,0x05,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, s[2:3], v2
+// CHECK: [0x02,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, s[4:5], v2
+// CHECK: [0x04,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, s[100:101], v2
+// CHECK: [0x64,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, flat_scratch, v2
+// CHECK: [0x66,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, vcc, v2
+// CHECK: [0x6a,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, ttmp[14:15], v2
+// CHECK: [0x7a,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, exec, v2
+// CHECK: [0x7e,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, 0, v2
+// CHECK: [0x80,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x26,0x7c]
+
+v_cmpx_class_f64 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x26,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_class_f64 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x26,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_class_f64 vcc, v[1:2], v255
+// CHECK: [0x01,0xff,0x27,0x7c]
+
+v_cmp_class_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x28,0x7c]
+
+v_cmp_class_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x28,0x7c]
+
+v_cmp_class_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x28,0x7c]
+
+v_cmp_class_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x28,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_class_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x28,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_class_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x29,0x7c]
+
+v_cmpx_class_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x2a,0x7c]
+
+v_cmpx_class_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x2a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_class_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x2a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_class_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x2b,0x7c]
+
+v_cmp_f_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x40,0x7c]
+
+v_cmp_f_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x40,0x7c]
+
+v_cmp_f_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x40,0x7c]
+
+v_cmp_f_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x40,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_f_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x40,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_f_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x41,0x7c]
+
+v_cmp_lt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x42,0x7c]
+
+v_cmp_lt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x42,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x42,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_lt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x43,0x7c]
+
+v_cmp_eq_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x44,0x7c]
+
+v_cmp_eq_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x44,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_eq_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x44,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_eq_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x45,0x7c]
+
+v_cmp_le_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x46,0x7c]
+
+v_cmp_le_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x46,0x7c]
+
+v_cmp_le_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x46,0x7c]
+
+v_cmp_le_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x46,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_le_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x46,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_le_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x47,0x7c]
+
+v_cmp_gt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x48,0x7c]
+
+v_cmp_gt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x48,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_gt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x48,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_gt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x49,0x7c]
+
+v_cmp_lg_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4a,0x7c]
+
+v_cmp_lg_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lg_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_lg_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4b,0x7c]
+
+v_cmp_ge_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4c,0x7c]
+
+v_cmp_ge_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4c,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ge_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4c,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_ge_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4d,0x7c]
+
+v_cmp_o_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4e,0x7c]
+
+v_cmp_o_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4e,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_o_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4e,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_o_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4f,0x7c]
+
+v_cmp_u_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x50,0x7c]
+
+v_cmp_u_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x50,0x7c]
+
+v_cmp_u_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x50,0x7c]
+
+v_cmp_u_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x50,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_u_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x50,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_u_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x51,0x7c]
+
+v_cmp_nge_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x52,0x7c]
+
+v_cmp_nge_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x52,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nge_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x52,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_nge_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x53,0x7c]
+
+v_cmp_nlg_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x54,0x7c]
+
+v_cmp_nlg_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x54,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nlg_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x54,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_nlg_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x55,0x7c]
+
+v_cmp_ngt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x56,0x7c]
+
+v_cmp_ngt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x56,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ngt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x56,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_ngt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x57,0x7c]
+
+v_cmp_nle_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x58,0x7c]
+
+v_cmp_nle_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x58,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nle_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x58,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_nle_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x59,0x7c]
+
+v_cmp_neq_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5a,0x7c]
+
+v_cmp_neq_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_neq_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_neq_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5b,0x7c]
+
+v_cmp_nlt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5c,0x7c]
+
+v_cmp_nlt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5c,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_nlt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5c,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_nlt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5d,0x7c]
+
+v_cmp_tru_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5e,0x7c]
+
+v_cmp_tru_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5e,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmp_tru_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5e,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmp_tru_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5f,0x7c]
+
+v_cmpx_f_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x60,0x7c]
+
+v_cmpx_f_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x60,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_f_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x60,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_f_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x61,0x7c]
+
+v_cmpx_lt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x62,0x7c]
+
+v_cmpx_lt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x62,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x62,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x63,0x7c]
+
+v_cmpx_eq_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x64,0x7c]
+
+v_cmpx_eq_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x64,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x64,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_eq_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x65,0x7c]
+
+v_cmpx_le_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x66,0x7c]
+
+v_cmpx_le_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x66,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x66,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_le_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x67,0x7c]
+
+v_cmpx_gt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x68,0x7c]
+
+v_cmpx_gt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x68,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x68,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_gt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x69,0x7c]
+
+v_cmpx_lg_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6a,0x7c]
+
+v_cmpx_lg_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lg_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_lg_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6b,0x7c]
+
+v_cmpx_ge_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6c,0x7c]
+
+v_cmpx_ge_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6c,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6c,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_ge_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6d,0x7c]
+
+v_cmpx_o_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6e,0x7c]
+
+v_cmpx_o_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6e,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_o_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6e,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_o_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6f,0x7c]
+
+v_cmpx_u_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x70,0x7c]
+
+v_cmpx_u_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x70,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_u_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x70,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_u_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x71,0x7c]
+
+v_cmpx_nge_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x72,0x7c]
+
+v_cmpx_nge_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x72,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nge_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x72,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_nge_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x73,0x7c]
+
+v_cmpx_nlg_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x74,0x7c]
+
+v_cmpx_nlg_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x74,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlg_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x74,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_nlg_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x75,0x7c]
+
+v_cmpx_ngt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x76,0x7c]
+
+v_cmpx_ngt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x76,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ngt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x76,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_ngt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x77,0x7c]
+
+v_cmpx_nle_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x78,0x7c]
+
+v_cmpx_nle_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x78,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nle_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x78,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_nle_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x79,0x7c]
+
+v_cmpx_neq_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7a,0x7c]
+
+v_cmpx_neq_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7a,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_neq_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7a,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_neq_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7b,0x7c]
+
+v_cmpx_nlt_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7c,0x7c]
+
+v_cmpx_nlt_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7c,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_nlt_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7c,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_nlt_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7d,0x7c]
+
+v_cmpx_tru_f16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7e,0x7c]
+
+v_cmpx_tru_f16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7e,0x7c,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_tru_f16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7e,0x7c,0x56,0x34,0x00,0x00]
+
+v_cmpx_tru_f16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7f,0x7c]
+
+v_cmp_f_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x80,0x7c]
+
+v_cmp_f_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x80,0x7c]
+
+v_cmp_f_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x80,0x7c]
+
+v_cmp_f_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x80,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x80,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x81,0x7c]
+
+v_cmp_lt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x82,0x7c]
+
+v_cmp_lt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x82,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x82,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x83,0x7c]
+
+v_cmp_eq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x84,0x7c]
+
+v_cmp_eq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x84,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x84,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x85,0x7c]
+
+v_cmp_le_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x86,0x7c]
+
+v_cmp_le_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x86,0x7c]
+
+v_cmp_le_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x86,0x7c]
+
+v_cmp_le_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x86,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x86,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x87,0x7c]
+
+v_cmp_gt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x88,0x7c]
+
+v_cmp_gt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x88,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x88,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x89,0x7c]
+
+v_cmp_lg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8a,0x7c]
+
+v_cmp_lg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8b,0x7c]
+
+v_cmp_ge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8c,0x7c]
+
+v_cmp_ge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8d,0x7c]
+
+v_cmp_o_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8e,0x7c]
+
+v_cmp_o_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_o_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_o_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8f,0x7c]
+
+v_cmp_u_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x90,0x7c]
+
+v_cmp_u_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x90,0x7c]
+
+v_cmp_u_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x90,0x7c]
+
+v_cmp_u_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x90,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_u_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x90,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_u_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x91,0x7c]
+
+v_cmp_nge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x92,0x7c]
+
+v_cmp_nge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x92,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x92,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x93,0x7c]
+
+v_cmp_nlg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x94,0x7c]
+
+v_cmp_nlg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x94,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x94,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x95,0x7c]
+
+v_cmp_ngt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x96,0x7c]
+
+v_cmp_ngt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x96,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ngt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x96,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ngt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x97,0x7c]
+
+v_cmp_nle_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x98,0x7c]
+
+v_cmp_nle_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x98,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nle_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x98,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nle_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x99,0x7c]
+
+v_cmp_neq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9a,0x7c]
+
+v_cmp_neq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9a,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_neq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9a,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_neq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9b,0x7c]
+
+v_cmp_nlt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9c,0x7c]
+
+v_cmp_nlt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9c,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9c,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9d,0x7c]
+
+v_cmp_tru_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9e,0x7c]
+
+v_cmp_tru_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9e,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_tru_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9e,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_tru_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9f,0x7c]
+
+v_cmpx_f_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa0,0x7c]
+
+v_cmpx_f_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa1,0x7c]
+
+v_cmpx_lt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa2,0x7c]
+
+v_cmpx_lt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa3,0x7c]
+
+v_cmpx_eq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa4,0x7c]
+
+v_cmpx_eq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa5,0x7c]
+
+v_cmpx_le_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa6,0x7c]
+
+v_cmpx_le_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa7,0x7c]
+
+v_cmpx_gt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa8,0x7c]
+
+v_cmpx_gt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa9,0x7c]
+
+v_cmpx_lg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xaa,0x7c]
+
+v_cmpx_lg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xaa,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xaa,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xab,0x7c]
+
+v_cmpx_ge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xac,0x7c]
+
+v_cmpx_ge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xac,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xac,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xad,0x7c]
+
+v_cmpx_o_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xae,0x7c]
+
+v_cmpx_o_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xae,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xae,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_o_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xaf,0x7c]
+
+v_cmpx_u_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb0,0x7c]
+
+v_cmpx_u_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_u_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb1,0x7c]
+
+v_cmpx_nge_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb2,0x7c]
+
+v_cmpx_nge_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nge_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb3,0x7c]
+
+v_cmpx_nlg_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb4,0x7c]
+
+v_cmpx_nlg_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlg_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb5,0x7c]
+
+v_cmpx_ngt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb6,0x7c]
+
+v_cmpx_ngt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ngt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb7,0x7c]
+
+v_cmpx_nle_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb8,0x7c]
+
+v_cmpx_nle_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nle_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb9,0x7c]
+
+v_cmpx_neq_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xba,0x7c]
+
+v_cmpx_neq_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xba,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xba,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_neq_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbb,0x7c]
+
+v_cmpx_nlt_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbc,0x7c]
+
+v_cmpx_nlt_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlt_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbd,0x7c]
+
+v_cmpx_tru_f32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbe,0x7c]
+
+v_cmpx_tru_f32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbe,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_tru_f32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbe,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_tru_f32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbf,0x7c]
+
+v_cmp_f_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc0,0x7c]
+
+v_cmp_f_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc1,0x7c]
+
+v_cmp_lt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc2,0x7c]
+
+v_cmp_lt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc3,0x7c]
+
+v_cmp_eq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc4,0x7c]
+
+v_cmp_eq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc5,0x7c]
+
+v_cmp_le_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc6,0x7c]
+
+v_cmp_le_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc7,0x7c]
+
+v_cmp_gt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc8,0x7c]
+
+v_cmp_gt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc9,0x7c]
+
+v_cmp_lg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xca,0x7c]
+
+v_cmp_lg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_lg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_lg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcb,0x7c]
+
+v_cmp_ge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xcc,0x7c]
+
+v_cmp_ge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcd,0x7c]
+
+v_cmp_o_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xce,0x7c]
+
+v_cmp_o_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xce,0x7c]
+
+v_cmp_o_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xce,0x7c]
+
+v_cmp_o_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_o_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_o_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcf,0x7c]
+
+v_cmp_u_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd0,0x7c]
+
+v_cmp_u_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_u_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_u_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd1,0x7c]
+
+v_cmp_nge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd2,0x7c]
+
+v_cmp_nge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd3,0x7c]
+
+v_cmp_nlg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd4,0x7c]
+
+v_cmp_nlg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd5,0x7c]
+
+v_cmp_ngt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd6,0x7c]
+
+v_cmp_ngt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_ngt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_ngt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd7,0x7c]
+
+v_cmp_nle_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd8,0x7c]
+
+v_cmp_nle_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nle_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nle_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd9,0x7c]
+
+v_cmp_neq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xda,0x7c]
+
+v_cmp_neq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_neq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_neq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdb,0x7c]
+
+v_cmp_nlt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xdc,0x7c]
+
+v_cmp_nlt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_nlt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_nlt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdd,0x7c]
+
+v_cmp_tru_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xde,0x7c]
+
+v_cmp_tru_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmp_tru_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmp_tru_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdf,0x7c]
+
+v_cmpx_f_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe0,0x7c]
+
+v_cmpx_f_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe1,0x7c]
+
+v_cmpx_lt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe2,0x7c]
+
+v_cmpx_lt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe3,0x7c]
+
+v_cmpx_eq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe4,0x7c]
+
+v_cmpx_eq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe5,0x7c]
+
+v_cmpx_le_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe6,0x7c]
+
+v_cmpx_le_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe7,0x7c]
+
+v_cmpx_gt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe8,0x7c]
+
+v_cmpx_gt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe9,0x7c]
+
+v_cmpx_lg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xea,0x7c]
+
+v_cmpx_lg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xeb,0x7c]
+
+v_cmpx_ge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xec,0x7c]
+
+v_cmpx_ge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xed,0x7c]
+
+v_cmpx_o_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xee,0x7c]
+
+v_cmpx_o_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_o_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_o_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xef,0x7c]
+
+v_cmpx_u_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf0,0x7c]
+
+v_cmpx_u_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_u_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_u_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf1,0x7c]
+
+v_cmpx_nge_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf2,0x7c]
+
+v_cmpx_nge_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nge_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nge_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf3,0x7c]
+
+v_cmpx_nlg_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf4,0x7c]
+
+v_cmpx_nlg_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlg_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlg_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf5,0x7c]
+
+v_cmpx_ngt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf6,0x7c]
+
+v_cmpx_ngt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ngt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ngt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf7,0x7c]
+
+v_cmpx_nle_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf8,0x7c]
+
+v_cmpx_nle_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nle_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nle_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf9,0x7c]
+
+v_cmpx_neq_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfa,0x7c]
+
+v_cmpx_neq_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_neq_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_neq_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfb,0x7c]
+
+v_cmpx_nlt_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfc,0x7c]
+
+v_cmpx_nlt_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_nlt_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_nlt_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfd,0x7c]
+
+v_cmpx_tru_f64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfe,0x7c]
+
+v_cmpx_tru_f64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7c,0x56,0x34,0x12,0xaf]
+
+v_cmpx_tru_f64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7c,0x73,0x72,0x71,0x3f]
+
+v_cmpx_tru_f64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xff,0x7c]
+
+v_cmp_f_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x40,0x7d]
+
+v_cmp_f_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x40,0x7d]
+
+v_cmp_f_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x40,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_f_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x40,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_f_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x40,0x7d]
+
+v_cmp_f_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x40,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_f_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x40,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_f_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x41,0x7d]
+
+v_cmp_lt_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x42,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_lt_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x42,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_lt_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x42,0x7d]
+
+v_cmp_lt_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x42,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lt_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x42,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_lt_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x43,0x7d]
+
+v_cmp_eq_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x44,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_eq_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x44,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_eq_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x44,0x7d]
+
+v_cmp_eq_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x44,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_eq_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x44,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_eq_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x45,0x7d]
+
+v_cmp_le_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x46,0x7d]
+
+v_cmp_le_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x46,0x7d]
+
+v_cmp_le_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x46,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_le_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x46,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_le_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x46,0x7d]
+
+v_cmp_le_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x46,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_le_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x46,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_le_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x47,0x7d]
+
+v_cmp_gt_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x48,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_gt_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x48,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_gt_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x48,0x7d]
+
+v_cmp_gt_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x48,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_gt_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x48,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_gt_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x49,0x7d]
+
+v_cmp_ne_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x4a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_ne_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x4a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_ne_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4a,0x7d]
+
+v_cmp_ne_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ne_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_ne_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4b,0x7d]
+
+v_cmp_ge_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x4c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_ge_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x4c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_ge_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4c,0x7d]
+
+v_cmp_ge_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ge_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_ge_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4d,0x7d]
+
+v_cmp_t_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x4e,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_t_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x4e,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_t_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x4e,0x7d]
+
+v_cmp_t_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x4e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_t_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x4e,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_t_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x4f,0x7d]
+
+v_cmp_f_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x50,0x7d]
+
+v_cmp_f_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x50,0x7d]
+
+v_cmp_f_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_f_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_f_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x50,0x7d]
+
+v_cmp_f_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_f_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x50,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_f_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x51,0x7d]
+
+v_cmp_lt_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x52,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_lt_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x52,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_lt_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x52,0x7d]
+
+v_cmp_lt_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x52,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_lt_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x52,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_lt_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x53,0x7d]
+
+v_cmp_eq_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x54,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_eq_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x54,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_eq_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x54,0x7d]
+
+v_cmp_eq_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x54,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_eq_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x54,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_eq_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x55,0x7d]
+
+v_cmp_le_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x56,0x7d]
+
+v_cmp_le_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x56,0x7d]
+
+v_cmp_le_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x56,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_le_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x56,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_le_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x56,0x7d]
+
+v_cmp_le_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x56,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_le_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x56,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_le_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x57,0x7d]
+
+v_cmp_gt_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x58,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_gt_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x58,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_gt_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x58,0x7d]
+
+v_cmp_gt_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x58,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_gt_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x58,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_gt_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x59,0x7d]
+
+v_cmp_ne_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x5a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_ne_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x5a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_ne_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5a,0x7d]
+
+v_cmp_ne_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ne_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_ne_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5b,0x7d]
+
+v_cmp_ge_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x5c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_ge_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x5c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_ge_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5c,0x7d]
+
+v_cmp_ge_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_ge_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_ge_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5d,0x7d]
+
+v_cmp_t_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x5e,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmp_t_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x5e,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmp_t_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x5e,0x7d]
+
+v_cmp_t_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x5e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmp_t_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x5e,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmp_t_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x5f,0x7d]
+
+v_cmpx_f_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x60,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_f_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x60,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_f_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x60,0x7d]
+
+v_cmpx_f_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x60,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_f_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x60,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_f_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x61,0x7d]
+
+v_cmpx_lt_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x62,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x62,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_lt_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x62,0x7d]
+
+v_cmpx_lt_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x62,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x62,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x63,0x7d]
+
+v_cmpx_eq_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x64,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x64,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x64,0x7d]
+
+v_cmpx_eq_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x64,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x64,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_eq_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x65,0x7d]
+
+v_cmpx_le_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x66,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x66,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x66,0x7d]
+
+v_cmpx_le_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x66,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x66,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_le_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x67,0x7d]
+
+v_cmpx_gt_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x68,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x68,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x68,0x7d]
+
+v_cmpx_gt_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x68,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x68,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_gt_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x69,0x7d]
+
+v_cmpx_ne_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x6a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x6a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6a,0x7d]
+
+v_cmpx_ne_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ne_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6b,0x7d]
+
+v_cmpx_ge_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x6c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x6c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6c,0x7d]
+
+v_cmpx_ge_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ge_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6d,0x7d]
+
+v_cmpx_t_i16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x6e,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_t_i16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x6e,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_t_i16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x6e,0x7d]
+
+v_cmpx_t_i16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x6e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_t_i16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x6e,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_t_i16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x6f,0x7d]
+
+v_cmpx_f_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_f_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_f_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x70,0x7d]
+
+v_cmpx_f_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_f_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x70,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_f_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x71,0x7d]
+
+v_cmpx_lt_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x72,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_lt_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x72,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_lt_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x72,0x7d]
+
+v_cmpx_lt_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x72,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_lt_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x72,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_lt_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x73,0x7d]
+
+v_cmpx_eq_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x74,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_eq_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x74,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_eq_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x74,0x7d]
+
+v_cmpx_eq_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x74,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_eq_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x74,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_eq_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x75,0x7d]
+
+v_cmpx_le_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x76,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_le_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x76,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_le_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x76,0x7d]
+
+v_cmpx_le_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x76,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_le_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x76,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_le_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x77,0x7d]
+
+v_cmpx_gt_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x78,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_gt_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x78,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_gt_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x78,0x7d]
+
+v_cmpx_gt_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x78,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_gt_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x78,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_gt_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x79,0x7d]
+
+v_cmpx_ne_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x7a,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ne_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x7a,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ne_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7a,0x7d]
+
+v_cmpx_ne_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7a,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ne_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7a,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ne_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7b,0x7d]
+
+v_cmpx_ge_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x7c,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_ge_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x7c,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_ge_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7c,0x7d]
+
+v_cmpx_ge_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7c,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_ge_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7c,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_ge_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7d,0x7d]
+
+v_cmpx_t_u16 vcc, v1, v2
+// CHECK: [0x01,0x05,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, v255, v2
+// CHECK: [0xff,0x05,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, s1, v2
+// CHECK: [0x01,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, s101, v2
+// CHECK: [0x65,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, 0, v2
+// CHECK: [0x80,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, 0.5, v2
+// CHECK: [0xff,0x04,0x7e,0x7d,0x00,0x38,0x00,0x00]
+
+v_cmpx_t_u16 vcc, -4.0, v2
+// CHECK: [0xff,0x04,0x7e,0x7d,0x00,0xc4,0x00,0x00]
+
+v_cmpx_t_u16 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x7e,0x7d]
+
+v_cmpx_t_u16 vcc, 0xfe0b, v2
+// CHECK: [0xff,0x04,0x7e,0x7d,0x0b,0xfe,0x00,0x00]
+
+v_cmpx_t_u16 vcc, 0x3456, v2
+// CHECK: [0xff,0x04,0x7e,0x7d,0x56,0x34,0x00,0x00]
+
+v_cmpx_t_u16 vcc, v1, v255
+// CHECK: [0x01,0xff,0x7f,0x7d]
+
+v_cmp_f_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x80,0x7d]
+
+v_cmp_f_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x80,0x7d]
+
+v_cmp_f_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x80,0x7d]
+
+v_cmp_f_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x80,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x80,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x81,0x7d]
+
+v_cmp_lt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x82,0x7d]
+
+v_cmp_lt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x82,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x82,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x83,0x7d]
+
+v_cmp_eq_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x84,0x7d]
+
+v_cmp_eq_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x84,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x84,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x85,0x7d]
+
+v_cmp_le_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x86,0x7d]
+
+v_cmp_le_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x86,0x7d]
+
+v_cmp_le_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x86,0x7d]
+
+v_cmp_le_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x86,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x86,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x87,0x7d]
+
+v_cmp_gt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x88,0x7d]
+
+v_cmp_gt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x88,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x88,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x89,0x7d]
+
+v_cmp_ne_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8a,0x7d]
+
+v_cmp_ne_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8b,0x7d]
+
+v_cmp_ge_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8c,0x7d]
+
+v_cmp_ge_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8d,0x7d]
+
+v_cmp_t_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x8e,0x7d]
+
+v_cmp_t_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x8e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x8e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x8f,0x7d]
+
+v_cmp_f_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x90,0x7d]
+
+v_cmp_f_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x90,0x7d]
+
+v_cmp_f_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x90,0x7d]
+
+v_cmp_f_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x90,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x90,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x91,0x7d]
+
+v_cmp_lt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x92,0x7d]
+
+v_cmp_lt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x92,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x92,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x93,0x7d]
+
+v_cmp_eq_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x94,0x7d]
+
+v_cmp_eq_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x94,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x94,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x95,0x7d]
+
+v_cmp_le_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x96,0x7d]
+
+v_cmp_le_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x96,0x7d]
+
+v_cmp_le_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x96,0x7d]
+
+v_cmp_le_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x96,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x96,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x97,0x7d]
+
+v_cmp_gt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x98,0x7d]
+
+v_cmp_gt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x98,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x98,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x99,0x7d]
+
+v_cmp_ne_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9a,0x7d]
+
+v_cmp_ne_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9a,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9a,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9b,0x7d]
+
+v_cmp_ge_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9c,0x7d]
+
+v_cmp_ge_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9c,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9c,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9d,0x7d]
+
+v_cmp_t_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0x9e,0x7d]
+
+v_cmp_t_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0x9e,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0x9e,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0x9f,0x7d]
+
+v_cmpx_f_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa0,0x7d]
+
+v_cmpx_f_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa1,0x7d]
+
+v_cmpx_lt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa2,0x7d]
+
+v_cmpx_lt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa3,0x7d]
+
+v_cmpx_eq_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa4,0x7d]
+
+v_cmpx_eq_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa5,0x7d]
+
+v_cmpx_le_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa6,0x7d]
+
+v_cmpx_le_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa7,0x7d]
+
+v_cmpx_gt_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xa8,0x7d]
+
+v_cmpx_gt_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xa8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xa8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xa9,0x7d]
+
+v_cmpx_ne_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xaa,0x7d]
+
+v_cmpx_ne_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xaa,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xaa,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xab,0x7d]
+
+v_cmpx_ge_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xac,0x7d]
+
+v_cmpx_ge_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xac,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xac,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xad,0x7d]
+
+v_cmpx_t_i32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xae,0x7d]
+
+v_cmpx_t_i32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xae,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_i32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xae,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_i32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xaf,0x7d]
+
+v_cmpx_f_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb0,0x7d]
+
+v_cmpx_f_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb1,0x7d]
+
+v_cmpx_lt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb2,0x7d]
+
+v_cmpx_lt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb3,0x7d]
+
+v_cmpx_eq_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb4,0x7d]
+
+v_cmpx_eq_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb5,0x7d]
+
+v_cmpx_le_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb6,0x7d]
+
+v_cmpx_le_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb7,0x7d]
+
+v_cmpx_gt_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xb8,0x7d]
+
+v_cmpx_gt_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xb8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xb8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xb9,0x7d]
+
+v_cmpx_ne_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xba,0x7d]
+
+v_cmpx_ne_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xba,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xba,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbb,0x7d]
+
+v_cmpx_ge_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbc,0x7d]
+
+v_cmpx_ge_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbc,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbc,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbd,0x7d]
+
+v_cmpx_t_u32 vcc, v1, v2
+// CHECK: [0x01,0x05,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, v255, v2
+// CHECK: [0xff,0x05,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, s1, v2
+// CHECK: [0x01,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, s101, v2
+// CHECK: [0x65,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, flat_scratch_lo, v2
+// CHECK: [0x66,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, flat_scratch_hi, v2
+// CHECK: [0x67,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, vcc_lo, v2
+// CHECK: [0x6a,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, vcc_hi, v2
+// CHECK: [0x6b,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, ttmp15, v2
+// CHECK: [0x7b,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, m0, v2
+// CHECK: [0x7c,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, exec_lo, v2
+// CHECK: [0x7e,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, exec_hi, v2
+// CHECK: [0x7f,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, 0, v2
+// CHECK: [0x80,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, -1, v2
+// CHECK: [0xc1,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, 0.5, v2
+// CHECK: [0xf0,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, -4.0, v2
+// CHECK: [0xf7,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, src_vccz, v2
+// CHECK: [0xfb,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, src_execz, v2
+// CHECK: [0xfc,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, src_scc, v2
+// CHECK: [0xfd,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, src_lds_direct, v2
+// CHECK: [0xfe,0x04,0xbe,0x7d]
+
+v_cmpx_t_u32 vcc, 0xaf123456, v2
+// CHECK: [0xff,0x04,0xbe,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_u32 vcc, 0x3f717273, v2
+// CHECK: [0xff,0x04,0xbe,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_u32 vcc, v1, v255
+// CHECK: [0x01,0xff,0xbf,0x7d]
+
+v_cmp_f_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc0,0x7d]
+
+v_cmp_f_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc1,0x7d]
+
+v_cmp_lt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc2,0x7d]
+
+v_cmp_lt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc3,0x7d]
+
+v_cmp_eq_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc4,0x7d]
+
+v_cmp_eq_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc5,0x7d]
+
+v_cmp_le_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc6,0x7d]
+
+v_cmp_le_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc7,0x7d]
+
+v_cmp_gt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xc8,0x7d]
+
+v_cmp_gt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xc8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xc9,0x7d]
+
+v_cmp_ne_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xca,0x7d]
+
+v_cmp_ne_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xca,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcb,0x7d]
+
+v_cmp_ge_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xcc,0x7d]
+
+v_cmp_ge_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xcc,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcd,0x7d]
+
+v_cmp_t_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xce,0x7d]
+
+v_cmp_t_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xce,0x7d]
+
+v_cmp_t_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xce,0x7d]
+
+v_cmp_t_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xce,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xcf,0x7d]
+
+v_cmp_f_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd0,0x7d]
+
+v_cmp_f_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_f_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_f_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd1,0x7d]
+
+v_cmp_lt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd2,0x7d]
+
+v_cmp_lt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_lt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_lt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd3,0x7d]
+
+v_cmp_eq_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd4,0x7d]
+
+v_cmp_eq_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_eq_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_eq_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd5,0x7d]
+
+v_cmp_le_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd6,0x7d]
+
+v_cmp_le_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_le_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_le_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd7,0x7d]
+
+v_cmp_gt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xd8,0x7d]
+
+v_cmp_gt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_gt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xd8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_gt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xd9,0x7d]
+
+v_cmp_ne_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xda,0x7d]
+
+v_cmp_ne_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ne_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xda,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ne_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdb,0x7d]
+
+v_cmp_ge_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xdc,0x7d]
+
+v_cmp_ge_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_ge_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xdc,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_ge_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdd,0x7d]
+
+v_cmp_t_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xde,0x7d]
+
+v_cmp_t_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xde,0x7d]
+
+v_cmp_t_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xde,0x7d]
+
+v_cmp_t_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmp_t_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xde,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmp_t_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xdf,0x7d]
+
+v_cmpx_f_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe0,0x7d]
+
+v_cmpx_f_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe1,0x7d]
+
+v_cmpx_lt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe2,0x7d]
+
+v_cmpx_lt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe3,0x7d]
+
+v_cmpx_eq_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe4,0x7d]
+
+v_cmpx_eq_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe5,0x7d]
+
+v_cmpx_le_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe6,0x7d]
+
+v_cmpx_le_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe7,0x7d]
+
+v_cmpx_gt_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xe8,0x7d]
+
+v_cmpx_gt_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xe8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xe9,0x7d]
+
+v_cmpx_ne_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xea,0x7d]
+
+v_cmpx_ne_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xea,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xeb,0x7d]
+
+v_cmpx_ge_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xec,0x7d]
+
+v_cmpx_ge_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xec,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xed,0x7d]
+
+v_cmpx_t_i64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xee,0x7d]
+
+v_cmpx_t_i64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_i64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xee,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_i64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xef,0x7d]
+
+v_cmpx_f_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf0,0x7d]
+
+v_cmpx_f_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_f_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf0,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_f_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf1,0x7d]
+
+v_cmpx_lt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf2,0x7d]
+
+v_cmpx_lt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_lt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf2,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_lt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf3,0x7d]
+
+v_cmpx_eq_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf4,0x7d]
+
+v_cmpx_eq_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_eq_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf4,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_eq_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf5,0x7d]
+
+v_cmpx_le_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf6,0x7d]
+
+v_cmpx_le_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_le_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf6,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_le_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf7,0x7d]
+
+v_cmpx_gt_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xf8,0x7d]
+
+v_cmpx_gt_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_gt_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xf8,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_gt_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xf9,0x7d]
+
+v_cmpx_ne_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfa,0x7d]
+
+v_cmpx_ne_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ne_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfa,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ne_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfb,0x7d]
+
+v_cmpx_ge_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfc,0x7d]
+
+v_cmpx_ge_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_ge_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfc,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_ge_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xfd,0x7d]
+
+v_cmpx_t_u64 vcc, v[1:2], v[2:3]
+// CHECK: [0x01,0x05,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, v[254:255], v[2:3]
+// CHECK: [0xfe,0x05,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, s[2:3], v[2:3]
+// CHECK: [0x02,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, s[4:5], v[2:3]
+// CHECK: [0x04,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, s[100:101], v[2:3]
+// CHECK: [0x64,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, flat_scratch, v[2:3]
+// CHECK: [0x66,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, vcc, v[2:3]
+// CHECK: [0x6a,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, ttmp[14:15], v[2:3]
+// CHECK: [0x7a,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, exec, v[2:3]
+// CHECK: [0x7e,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, 0, v[2:3]
+// CHECK: [0x80,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, -1, v[2:3]
+// CHECK: [0xc1,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, 0.5, v[2:3]
+// CHECK: [0xf0,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, -4.0, v[2:3]
+// CHECK: [0xf7,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, src_vccz, v[2:3]
+// CHECK: [0xfb,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, src_execz, v[2:3]
+// CHECK: [0xfc,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, src_scc, v[2:3]
+// CHECK: [0xfd,0x04,0xfe,0x7d]
+
+v_cmpx_t_u64 vcc, 0xaf123456, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7d,0x56,0x34,0x12,0xaf]
+
+v_cmpx_t_u64 vcc, 0x3f717273, v[2:3]
+// CHECK: [0xff,0x04,0xfe,0x7d,0x73,0x72,0x71,0x3f]
+
+v_cmpx_t_u64 vcc, v[1:2], v[254:255]
+// CHECK: [0x01,0xfd,0xff,0x7d]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_class_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_class_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_class_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x21,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_class_f32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x20,0x7c,0x01,0x86,0x06,0x0e]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_class_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_class_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_class_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_class_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x23,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_class_f32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x22,0x7c,0x01,0x86,0x06,0x0e]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_class_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_class_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_class_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_class_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x29,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_class_f16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x28,0x7c,0x01,0x86,0x06,0x0e]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_class_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_class_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_class_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_class_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x2b,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_class_f16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x2a,0x7c,0x01,0x86,0x06,0x0e]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_f_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_f_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_f_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x41,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_f_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_f_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_lt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_lt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x43,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_lt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_eq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_eq_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x45,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_eq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_le_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_le_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_le_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x47,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_le_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_le_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_gt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_gt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x49,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_gt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_lg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_lg_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4b,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_lg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_ge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_ge_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4d,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_ge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_o_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_o_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_o_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4f,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_o_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_o_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_u_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_u_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_u_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x51,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_u_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_u_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_nge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_nge_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x53,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_nge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x55,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_nlg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x57,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_ngt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nle_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_nle_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_nle_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x59,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_nle_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_neq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_neq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_neq_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5b,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_neq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5d,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_nlt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_tru_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_tru_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_tru_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5f,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_tru_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_f_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_f_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_f_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x61,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_f_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x63,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_lt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x65,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_eq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_le_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_le_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_le_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x67,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_le_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x69,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_gt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6b,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_lg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6d,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_ge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_o_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_o_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_o_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_o_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6f,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_o_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_u_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_u_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_u_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_u_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x71,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_u_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x73,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_nge_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x75,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_nlg_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x77,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_ngt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x79,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_nle_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7b,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_neq_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7d,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_nlt_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7f,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_tru_f16_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_f_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_f_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_f_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_f_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x81,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_f_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_f_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_lt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_lt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x83,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_lt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_eq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_eq_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x85,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_eq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_le_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_le_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_le_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_le_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x87,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_le_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_le_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_gt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_gt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x89,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_gt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_lg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_lg_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_lg_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8b,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_lg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_ge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_ge_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8d,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_ge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_o_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_o_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_o_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_o_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8f,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_o_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_o_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_u_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_u_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_u_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_u_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x91,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_u_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_u_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_nge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_nge_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nge_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x93,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_nge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x95,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_nlg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x97,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_ngt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nle_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_nle_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_nle_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nle_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x99,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_nle_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_neq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_neq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_neq_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_neq_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9b,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_neq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9d,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_nlt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_tru_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmp_tru_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmp_tru_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmp_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmp_tru_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9f,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmp_tru_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_f_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_f_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_f_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa1,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_f_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa3,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_lt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa5,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_eq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_le_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_le_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_le_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa7,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_le_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa9,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_gt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xab,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_lg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xad,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_ge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_o_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_o_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_o_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_o_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_o_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xaf,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_o_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_u_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_u_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_u_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_u_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_u_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb1,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_u_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb3,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_nge_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb5,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_nlg_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb7,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_ngt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb9,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_nle_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbb,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_neq_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbd,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_nlt_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x88,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0xe4,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0xe6,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x00,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0xfa,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0xff,0x86,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x65,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x66,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x67,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x6a,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x6b,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x7b,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x7c,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x7e,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x7f,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x80,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0xc1,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0xf0,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0xf7,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0xfb,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0xfc,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0xfd,0x86,0x86,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbf,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x00,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x01,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x02,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x03,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x04,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x05,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], -v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x16,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], |v1|, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x26,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x06]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x00]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x01]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x02]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x03]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x04]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x05]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, -v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x16]
+
+v_cmpx_tru_f32_sdwa s[6:7], v1, |v2| src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7c,0x01,0x86,0x06,0x26]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_f_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_f_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x41,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_f_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x40,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_lt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_lt_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x43,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_lt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x42,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_eq_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_eq_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x45,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_eq_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x44,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_le_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_le_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x47,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_le_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x46,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_gt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_gt_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x49,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_gt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x48,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_ne_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_ne_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4b,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_ne_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4a,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_ge_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_ge_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4d,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_ge_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4c,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_t_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_t_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x4f,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_t_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x4e,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_f_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_f_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x51,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_f_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x50,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_lt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_lt_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x53,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_lt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x52,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_eq_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_eq_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x55,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_eq_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x54,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_le_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_le_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x57,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_le_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x56,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_gt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_gt_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x59,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_gt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x58,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_ne_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_ne_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5b,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_ne_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5a,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_ge_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_ge_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5d,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_ge_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5c,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_t_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_t_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x5f,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_t_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x5e,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_f_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_f_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_f_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x61,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_f_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x60,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x63,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_lt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x62,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x65,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_eq_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x64,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_le_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_le_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_le_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x67,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_le_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x66,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x69,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_gt_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x68,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6b,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_ne_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6a,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6d,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_ge_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6c,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_i16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_t_i16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_t_i16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_t_i16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x6f,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_t_i16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x6e,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_f_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_f_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_f_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x71,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_f_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x70,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x73,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_lt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x72,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x75,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_eq_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x74,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_le_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_le_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_le_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x77,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_le_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x76,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x79,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_gt_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x78,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7b,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_ne_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7a,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7d,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_ge_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7c,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_u16_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_t_u16_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_t_u16_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_t_u16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u16_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x7f,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_t_u16_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x7e,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_f_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_f_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x81,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_f_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x80,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_lt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_lt_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x83,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_lt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x82,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_eq_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_eq_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x85,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_eq_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x84,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_le_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_le_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x87,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_le_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x86,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_gt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_gt_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x89,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_gt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x88,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_ne_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_ne_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8b,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_ne_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8a,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_ge_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_ge_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8d,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_ge_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8c,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_t_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_t_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x8f,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_t_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x8e,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_f_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_f_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_f_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x91,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_f_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x90,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_lt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_lt_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_lt_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x93,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_lt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x92,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_eq_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_eq_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_eq_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x95,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_eq_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x94,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_le_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_le_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_le_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x97,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_le_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x96,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_gt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_gt_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_gt_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x99,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_gt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x98,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_ne_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_ne_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ne_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9b,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_ne_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9a,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_ge_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_ge_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_ge_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9d,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_ge_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9c,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmp_t_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmp_t_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmp_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmp_t_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0x9f,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmp_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmp_t_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0x9e,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_f_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_f_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_f_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa1,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_f_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa0,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa3,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_lt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa2,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa5,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_eq_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa4,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_le_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_le_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_le_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa7,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_le_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa6,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xa9,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_gt_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xa8,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xab,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_ne_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xaa,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xad,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_ge_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xac,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_i32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_t_i32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_t_i32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_t_i32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_i32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xaf,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_t_i32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xae,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_f_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_f_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_f_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_f_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb1,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_f_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb0,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb3,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_lt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb2,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb5,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_eq_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb4,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_le_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_le_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_le_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_le_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb7,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_le_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb6,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xb9,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_gt_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xb8,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbb,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_ne_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xba,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbd,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_ge_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbc,0x7d,0x01,0x86,0x06,0x0e]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_u32_sdwa s[8:9], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x88,0x06,0x06]
+
+v_cmpx_t_u32_sdwa s[100:101], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0xe4,0x06,0x06]
+
+v_cmpx_t_u32_sdwa flat_scratch, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0xe6,0x06,0x06]
+
+v_cmpx_t_u32_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x00,0x06,0x06]
+
+v_cmpx_t_u32_sdwa ttmp[14:15], v1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0xfa,0x06,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v255, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0xff,0x86,0x06,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], s1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], s101, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x65,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], flat_scratch_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x66,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], flat_scratch_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x67,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], vcc_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x6a,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], vcc_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x6b,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], ttmp15, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x7b,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], m0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x7c,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], exec_lo, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x7e,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], exec_hi, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x7f,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], 0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x80,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], -1, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0xc1,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], 0.5, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0xf0,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], -4.0, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0xf7,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], src_vccz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0xfb,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], src_execz, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0xfc,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], src_scc, v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0xfd,0x86,0x86,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v255 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0xfe,0xbf,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x00,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x01,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_2 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x02,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:BYTE_3 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x03,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_0 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x04,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x05,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], sext(v1), v2 src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x0e,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x06]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_0
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x00]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_1
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x01]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_2
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x02]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:BYTE_3
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x03]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_0
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x04]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, v2 src0_sel:DWORD src1_sel:WORD_1
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x05]
+
+v_cmpx_t_u32_sdwa s[6:7], v1, sext(v2) src0_sel:DWORD src1_sel:DWORD
+// CHECK: [0xf9,0x04,0xbe,0x7d,0x01,0x86,0x06,0x0e]
diff --git a/llvm/test/MC/AMDGPU/literal16.s b/llvm/test/MC/AMDGPU/literal16.s
index 97d16c3742851..2a641d53a9b66 100644
--- a/llvm/test/MC/AMDGPU/literal16.s
+++ b/llvm/test/MC/AMDGPU/literal16.s
@@ -146,3 +146,4 @@ v_madmk_f16 v1, v2, 64.0, v3
 
 
 v_add_f16_e32 v1, 64.0, v2
+// VI: v_add_f16_e32 v1, 0x5400, v2 ; encoding: [0xff,0x04,0x02,0x3e,0x00,0x54,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/mad-mix.s b/llvm/test/MC/AMDGPU/mad-mix.s
index f1de62b5a5482..4b28d03bb8284 100644
--- a/llvm/test/MC/AMDGPU/mad-mix.s
+++ b/llvm/test/MC/AMDGPU/mad-mix.s
@@ -22,8 +22,6 @@ v_mad_mix_f32 v0, abs(v1), v2, v3
 // GFX9-MADMIX: v_mad_mix_f32 v0, |v1|, v2, v3 ; encoding: [0x00,0x01,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 // GFX9-FMAMIX-ERR: error: instruction not supported on this GPU
 
-// FIXME: Improve diagnistics
-
 v_mad_mix_f32 v0, v1, abs(v2), v3
 // GFX9-MADMIX: v_mad_mix_f32 v0, v1, |v2|, v3 ; encoding: [0x00,0x02,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 // GFX9-FMAMIX-ERR: error: instruction not supported on this GPU
@@ -80,8 +78,6 @@ v_mad_mix_f32 v0, v1, v2, v3 op_sel:[0,0,0]
 // GFX9-MADMIX: v_mad_mix_f32 v0, v1, v2, v3 ; encoding: [0x00,0x00,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 // GFX9-FMAMIX-ERR: error: instruction not supported on this GPU
 
-// FIXME: Improve diagnistics
-
 v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0]
 // GFX9-MADMIX: v_mad_mix_f32 v0, v1, v2, v3 op_sel:[1,0,0] ; encoding: [0x00,0x08,0xa0,0xd3,0x01,0x05,0x0e,0x04]
 // GFX9-FMAMIX-ERR: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/smem.s b/llvm/test/MC/AMDGPU/smem.s
index ff725dbba4132..46bf2baa1c61f 100644
--- a/llvm/test/MC/AMDGPU/smem.s
+++ b/llvm/test/MC/AMDGPU/smem.s
@@ -63,7 +63,6 @@ s_memrealtime ttmp[0:1]
 // GFX10: s_memrealtime ttmp[0:1] ; encoding: [0x00,0x1b,0x94,0xf4,0x00,0x00,0x00,0x00]
 // NOSICI: error: instruction not supported on this GPU
 
-// FIXME: Should error about instruction on GPU
 s_store_dword s1, s[2:3], 0xfc
 // GFX89: s_store_dword s1, s[2:3], 0xfc  ; encoding: [0x41,0x00,0x42,0xc0,0xfc,0x00,0x00,0x00]
 // GFX1012: s_store_dword s1, s[2:3], 0xfc ; encoding: [0x41,0x00,0x40,0xf4,0xfc,0x00,0x00,0xfa]
diff --git a/llvm/test/MC/AMDGPU/vintrp-err.s b/llvm/test/MC/AMDGPU/vintrp-err.s
index 00491e0fe9877..d260e9c3eb48f 100644
--- a/llvm/test/MC/AMDGPU/vintrp-err.s
+++ b/llvm/test/MC/AMDGPU/vintrp-err.s
@@ -1,45 +1,68 @@
 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=SI --implicit-check-not=error: %s
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI --implicit-check-not=error: %s
 
+v_interp_p1_f32 v0, v1
+// GCN: error: too few operands for instruction
+
 v_interp_p1_f32 v0, v1, attr64.w
-// GCN: :25: error: out of bounds attr
+// GCN: error: out of bounds interpolation attribute number
 
 v_interp_p1_f32 v0, v1, attr64.x
-// GCN: :25: error: out of bounds attr
+// GCN: error: out of bounds interpolation attribute number
 
 v_interp_p2_f32 v9, v1, attr64.x
-// GCN: :25: error: out of bounds attr
+// GCN: error: out of bounds interpolation attribute number
 
 v_interp_p2_f32 v0, v1, attr64.x
-// GCN: :25: error: out of bounds attr
+// GCN: error: out of bounds interpolation attribute number
 
 v_interp_p2_f32 v0, v1, attr0.q
-// GCN: :25: error: failed parsing operand.
+// GCN: error: invalid or missing interpolation attribute channel
 
 v_interp_p2_f32 v0, v1, attr0.
-// GCN: :25: error: failed parsing operand.
+// GCN: error: invalid or missing interpolation attribute channel
 
 v_interp_p2_f32 v0, v1, attr
-// GCN: :25: error: failed parsing operand.
+// GCN: error: invalid or missing interpolation attribute channel
 
-// XXX - Why does this one parse?
 v_interp_p2_f32 v0, v1, att
-// GCN: :25: error: invalid operand for instruction
+// GCN: error: invalid interpolation attribute
 
 v_interp_p2_f32 v0, v1, attrq
-// GCN: :25: error: failed parsing operand.
+// GCN: error: invalid or missing interpolation attribute channel
+
+v_interp_p2_f32 v7, v1, attr.x
+// GCN: error: invalid or missing interpolation attribute number
+
+v_interp_p2_f32 v7, v1, attr-1.x
+// GCN: error: invalid or missing interpolation attribute channel
+
+v_interp_p2_f32 v7, v1, attrA.x
+// GCN: error: invalid or missing interpolation attribute number
 
 v_interp_mov_f32 v11, invalid_param_3, attr0.y
-// GCN: :23: error: failed parsing operand.
+// GCN: error: invalid interpolation slot
 
 v_interp_mov_f32 v12, invalid_param_10, attr0.x
-// GCN: :23: error: failed parsing operand.
+// GCN: error: invalid interpolation slot
 
 v_interp_mov_f32 v3, invalid_param_3, attr0.x
-// GCN: :22: error: failed parsing operand.
+// GCN: error: invalid interpolation slot
 
 v_interp_mov_f32 v8, invalid_param_8, attr0.x
-// GCN: :22: error: failed parsing operand.
+// GCN: error: invalid interpolation slot
 
 v_interp_mov_f32 v8, foo, attr0.x
-// GCN: :22: error: failed parsing operand.
+// GCN: error: invalid interpolation slot
+
+v_interp_mov_f32 v8, 0, attr0.x
+// GCN: error: invalid operand for instruction
+
+v_interp_mov_f32 v8, -1, attr0.x
+// GCN: error: invalid operand for instruction
+
+v_interp_mov_f32 v8, p-1, attr0.x
+// GCN: error: invalid interpolation slot
+
+v_interp_mov_f32 v8, p1, attr0.x
+// GCN: error: invalid interpolation slot
diff --git a/llvm/test/MC/AMDGPU/vop1-gfx9-err.s b/llvm/test/MC/AMDGPU/vop1-gfx9-err.s
index 42feac2f0aa21..0afa306182a93 100644
--- a/llvm/test/MC/AMDGPU/vop1-gfx9-err.s
+++ b/llvm/test/MC/AMDGPU/vop1-gfx9-err.s
@@ -12,7 +12,6 @@ v_swap_b32 v1, s0
 // GFX9: error: invalid operand for instruction
 // VI: error: instruction not supported on this GPU
 
-// FIXME: Better error for it requiring VOP1 encoding
 v_swap_b32_e64 v1, v2
 // GFX9: :1: error: e64 variant of this instruction is not supported
 // CI: :1: error: instruction not supported on this GPU
diff --git a/llvm/test/MC/AMDGPU/vop1.s b/llvm/test/MC/AMDGPU/vop1.s
index 12a033c92992c..df0b384e3efd4 100644
--- a/llvm/test/MC/AMDGPU/vop1.s
+++ b/llvm/test/MC/AMDGPU/vop1.s
@@ -1,6 +1,6 @@
 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SI --check-prefix=SICI
-// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=SICI --check-prefix=CIVI
+// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CI --check-prefix=SICI --check-prefix=CIVI
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
 
 // RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI --implicit-check-not=error:
diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt b/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
index fbbd8ae864122..fe9617a1ae16a 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/vop3_gfx9.txt
@@ -693,7 +693,7 @@
 # GFX9: v_sat_pk_u8_i16_e64 v255, v1 ; encoding: [0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00]
 0xff,0x00,0x8f,0xd1,0x01,0x01,0x00,0x00
 
-# GXF9: v_screen_partition_4se_b32_e64 v5, v1 ; encoding: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
+# GFX9: v_screen_partition_4se_b32_e64 v5, v1 ; encoding: [0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00]
 0x05,0x00,0x77,0xd1,0x01,0x01,0x00,0x00
 
 # GFX9: v_add_u32_e64 v84, v13, s31 clamp ; encoding: [0x54,0x80,0x34,0xd1,0x0d,0x3f,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt
index cd9a65cc13e83..5ee8b00fd044a 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/vop3_vi.txt
@@ -225,7 +225,7 @@
 # VI:   v_div_scale_f32 v24, vcc, v22, v22, v20 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0x52,0x04]
 0x18 0x6a 0xe0 0xd1 0x16 0x2d 0x52 0x04
 
-# FIXME:   v_div_scale_f32 v24, vcc, s[10:11], v22, v20 ; encoding: [0x18,0x6a,0xe0,0xd1,0x0a,0x2c,0x52,0x04]
+# VI:   v_div_scale_f32 v24, vcc, s10, v22, v20 ; encoding: [0x18,0x6a,0xe0,0xd1,0x0a,0x2c,0x52,0x04]
 0x18 0x6a 0xe0 0xd1 0x0a 0x2c 0x52 0x04
 
 # VI:   v_div_scale_f32 v24, s[10:11], v22, v22, v20 ; encoding: [0x18,0x0a,0xe0,0xd1,0x16,0x2d,0x52,0x04]
diff --git a/llvm/test/MC/Disassembler/WebAssembly/wasm.txt b/llvm/test/MC/Disassembler/WebAssembly/wasm.txt
index bb50b646ab549..8201213e54b26 100644
--- a/llvm/test/MC/Disassembler/WebAssembly/wasm.txt
+++ b/llvm/test/MC/Disassembler/WebAssembly/wasm.txt
@@ -36,7 +36,7 @@
 # CHECK: v128.const 50462976, 117835012, 185207048, 252579084
 0xFD 0x0C 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
 
-# CHECK: v8x16.shuffle 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+# CHECK: i8x16.shuffle 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
 0xFD 0x0D 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
 
 # Check LEB128 encoding of SIMD instructions
diff --git a/llvm/test/MC/ELF/fde.s b/llvm/test/MC/ELF/cfi-fde-encoding.s
similarity index 100%
rename from llvm/test/MC/ELF/fde.s
rename to llvm/test/MC/ELF/cfi-fde-encoding.s
diff --git a/llvm/test/MC/X86/return-column.s b/llvm/test/MC/ELF/cfi-return-column.s
similarity index 100%
rename from llvm/test/MC/X86/return-column.s
rename to llvm/test/MC/ELF/cfi-return-column.s
diff --git a/llvm/test/MC/X86/cfi-scope-errors.s b/llvm/test/MC/ELF/cfi-scope-errors.s
similarity index 100%
rename from llvm/test/MC/X86/cfi-scope-errors.s
rename to llvm/test/MC/ELF/cfi-scope-errors.s
diff --git a/llvm/test/MC/X86/cfi-open-within-another-crash.s b/llvm/test/MC/ELF/cfi-scope-errors2.s
similarity index 87%
rename from llvm/test/MC/X86/cfi-open-within-another-crash.s
rename to llvm/test/MC/ELF/cfi-scope-errors2.s
index 6ec5338f54b47..d29c05636d0df 100644
--- a/llvm/test/MC/X86/cfi-open-within-another-crash.s
+++ b/llvm/test/MC/ELF/cfi-scope-errors2.s
@@ -4,15 +4,10 @@
 # RUN: not llvm-mc %s -filetype=obj -triple=x86_64-unknown-linux -o /dev/null 2>&1 | FileCheck %s
 
 .text
-.globl proc_one
-proc_one:
  .cfi_startproc
- 
+
 .text
-.globl proc_two
-proc_two:
  .cfi_startproc
 # CHECK: [[#@LINE]]:1: error: starting new .cfi frame before finishing the previous one
 
  .cfi_endproc
-
diff --git a/llvm/test/MC/X86/expand-var.s b/llvm/test/MC/ELF/expand-var.s
similarity index 100%
rename from llvm/test/MC/X86/expand-var.s
rename to llvm/test/MC/ELF/expand-var.s
diff --git a/llvm/test/MC/PowerPC/ppc-machine.s b/llvm/test/MC/PowerPC/ppc-machine.s
index 22a6cd7ef73aa..f7b71f8687994 100644
--- a/llvm/test/MC/PowerPC/ppc-machine.s
+++ b/llvm/test/MC/PowerPC/ppc-machine.s
@@ -15,3 +15,8 @@
 	.machine "pop"
 
 	.machine ppc64
+
+# Used in glibc.
+	.machine altivec
+	.machine power4
+	.machine power8
diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s
index b741cce7abd71..fb7b4a0378e14 100644
--- a/llvm/test/MC/RISCV/rvv/invalid.s
+++ b/llvm/test/MC/RISCV/rvv/invalid.s
@@ -632,3 +632,23 @@ vmerge.vxm v0, v1, x1, v0
 vfmerge.vfm v0, v1, f1, v0
 # CHECK-ERROR: The destination vector register group cannot be V0.
 # CHECK-ERROR-LABEL: vfmerge.vfm v0, v1, f1, v0
+
+vle8.v v0, (a0), v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vle8.v v0, (a0), v0.t
+
+vfclass.v v0, v1, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfclass.v v0, v1, v0.t
+
+vfsqrt.v v0, v1, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfsqrt.v v0, v1, v0.t
+
+vzext.vf2 v0, v1, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vzext.vf2 v0, v1, v0.t
+
+vid.v v0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vid.v v0, v0.t
diff --git a/llvm/test/MC/WebAssembly/simd-encodings.s b/llvm/test/MC/WebAssembly/simd-encodings.s
index 509f4246475f0..91e1f07fe44c4 100644
--- a/llvm/test/MC/WebAssembly/simd-encodings.s
+++ b/llvm/test/MC/WebAssembly/simd-encodings.s
@@ -24,17 +24,17 @@ main:
     # CHECK: i64x2.load32x2_u 32 # encoding: [0xfd,0x06,0x03,0x20]
     i64x2.load32x2_u 32
 
-    # CHECK: v8x16.load_splat 48 # encoding: [0xfd,0x07,0x00,0x30]
-    v8x16.load_splat 48
+    # CHECK: v128.load8_splat 48 # encoding: [0xfd,0x07,0x00,0x30]
+    v128.load8_splat 48
 
-    # CHECK: v16x8.load_splat 48 # encoding: [0xfd,0x08,0x01,0x30]
-    v16x8.load_splat 48
+    # CHECK: v128.load16_splat 48 # encoding: [0xfd,0x08,0x01,0x30]
+    v128.load16_splat 48
 
-    # CHECK: v32x4.load_splat 48 # encoding: [0xfd,0x09,0x02,0x30]
-    v32x4.load_splat 48
+    # CHECK: v128.load32_splat 48 # encoding: [0xfd,0x09,0x02,0x30]
+    v128.load32_splat 48
 
-    # CHECK: v64x2.load_splat 48 # encoding: [0xfd,0x0a,0x03,0x30]
-    v64x2.load_splat 48
+    # CHECK: v128.load64_splat 48 # encoding: [0xfd,0x0a,0x03,0x30]
+    v128.load64_splat 48
 
     # CHECK: v128.store 48 # encoding: [0xfd,0x0b,0x04,0x30]
     v128.store 48
@@ -66,15 +66,15 @@ main:
     # CHECK-SAME: 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f]
     v128.const 0x1.60504030201p-911, 0x1.e0d0c0b0a0908p-783
 
-    # CHECK: v8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23,
+    # CHECK: i8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23,
     # CHECK-SAME:          8, 25, 10, 27, 12, 29, 14, 31
     # CHECK-SAME: # encoding: [0xfd,0x0d,
     # CHECK-SAME: 0x00,0x11,0x02,0x13,0x04,0x15,0x06,0x17,
     # CHECK-SAME: 0x08,0x19,0x0a,0x1b,0x0c,0x1d,0x0e,0x1f]
-    v8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31
+    i8x16.shuffle 0, 17, 2, 19, 4, 21, 6, 23, 8, 25, 10, 27, 12, 29, 14, 31
 
-    # CHECK: v8x16.swizzle # encoding: [0xfd,0x0e]
-    v8x16.swizzle
+    # CHECK: i8x16.swizzle # encoding: [0xfd,0x0e]
+    i8x16.swizzle
 
     # CHECK: i8x16.splat # encoding: [0xfd,0x0f]
     i8x16.splat
diff --git a/llvm/test/MC/X86/pr38826.s b/llvm/test/MC/X86/cfi_offset-eip.s
similarity index 100%
rename from llvm/test/MC/X86/pr38826.s
rename to llvm/test/MC/X86/cfi_offset-eip.s
diff --git a/llvm/test/MC/X86/cfi_def_cfa-crash.s b/llvm/test/MC/X86/compact-unwind-cfi_def_cfa.s
similarity index 100%
rename from llvm/test/MC/X86/cfi_def_cfa-crash.s
rename to llvm/test/MC/X86/compact-unwind-cfi_def_cfa.s
diff --git a/llvm/test/MC/X86/fde-reloc.s b/llvm/test/MC/X86/fde-reloc.s
deleted file mode 100644
index 63ac976621884..0000000000000
--- a/llvm/test/MC/X86/fde-reloc.s
+++ /dev/null
@@ -1,11 +0,0 @@
-// RUN: llvm-mc -filetype=obj %s -o - -triple x86_64-pc-linux | llvm-objdump -r - | FileCheck --check-prefix=X86-64 %s
-// RUN: llvm-mc -filetype=obj %s -o - -triple i686-pc-linux | llvm-objdump -r - | FileCheck --check-prefix=I686 %s
-
-// PR15448
-
-func:
-	.cfi_startproc
-	.cfi_endproc
-
-// X86-64: R_X86_64_PC32
-// I686: R_386_PC32
diff --git a/llvm/test/Object/elf-unknown-type.test b/llvm/test/Object/elf-unknown-type.test
deleted file mode 100644
index 508e831ae90e0..0000000000000
--- a/llvm/test/Object/elf-unknown-type.test
+++ /dev/null
@@ -1,10 +0,0 @@
-# RUN: yaml2obj %s | llvm-readobj --file-headers - | FileCheck %s
-
-!ELF
-FileHeader: !FileHeader
-  Class: ELFCLASS64
-  Data: ELFDATA2LSB
-  Type: 42
-  Machine: EM_X86_64
-
-# CHECK: Type: 0x2A
diff --git a/llvm/test/Other/scalable-vectors-core-ir.ll b/llvm/test/Other/scalable-vectors-core-ir.ll
index 60cbab3cdff60..f04184a417666 100644
--- a/llvm/test/Other/scalable-vectors-core-ir.ll
+++ b/llvm/test/Other/scalable-vectors-core-ir.ll
@@ -200,6 +200,16 @@ define <vscale x 8 x half> @shufflevector(half %val) {
   ret <vscale x 8 x half> %r
 }
 
+define <vscale x 8 x half> @shufflevector2(half %val) {
+; CHECK-LABEL: @shufflevector
+; CHECK: %insvec = insertelement <vscale x 8 x half> poison, half %val, i32 0
+; CHECK-NEXT: %r = shufflevector <vscale x 8 x half> %insvec, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+; CHECK-NEXT: ret <vscale x 8 x half> %r
+  %insvec = insertelement <vscale x 8 x half> poison, half %val, i32 0
+  %r = shufflevector <vscale x 8 x half> %insvec, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x half> %r
+}
+
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;; Memory Access and Addressing Operations
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -390,4 +400,4 @@ define <vscale x 4 x i32> @call(<vscale x 4 x i32> %val) {
 ; CHECK-NEXT: ret <vscale x 4 x i32> %r
   %r = call <vscale x 4 x i32> @callee(<vscale x 4 x i32> %val)
   ret <vscale x 4 x i32> %r
-}
\ No newline at end of file
+}
diff --git a/llvm/test/SYCLLowerIR/scalar_fptoui.ll b/llvm/test/SYCLLowerIR/scalar_fptoui.ll
new file mode 100644
index 0000000000000..a17270c711206
--- /dev/null
+++ b/llvm/test/SYCLLowerIR/scalar_fptoui.ll
@@ -0,0 +1,17 @@
+; This is a regression test for LowerESIMD crashing on a scalar fptoui
+; instruction.
+;
+; RUN: opt < %s -LowerESIMD -S | FileCheck %s
+
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
+target triple = "spir64-unknown-unknown-sycldevice"
+
+; Function Attrs: convergent norecurse
+define dso_local spir_func i32 @foo(float %x) !sycl_explicit_simd !1 {
+  %y = fptoui float %x to i32
+; check that the scalar float to unsigned int conversion is left intact
+; CHECK: %y = fptoui float %x to i32
+  ret i32 %y
+}
+
+!1 = !{i32 0, i32 0}
diff --git a/llvm/test/TableGen/directive1.td b/llvm/test/TableGen/directive1.td
index 5d9be74e9fce5..a63b4065f86aa 100644
--- a/llvm/test/TableGen/directive1.td
+++ b/llvm/test/TableGen/directive1.td
@@ -95,6 +95,7 @@ def TDL_DirA : Directive<"dira"> {
 // CHECK-NEXT:  bool isAllowedClauseForDirective(Directive D, Clause C, unsigned Version);
 // CHECK-EMPTY:
 // CHECK-NEXT:  AKind getAKind(StringRef);
+// CHECK-NEXT:  llvm::StringRef getTdlAKindName(AKind);
 // CHECK-EMPTY:
 // CHECK-NEXT:  } // namespace tdl
 // CHECK-NEXT:  } // namespace llvm
@@ -147,6 +148,18 @@ def TDL_DirA : Directive<"dira"> {
 // IMPL-NEXT:      .Default(TDLCV_valc);
 // IMPL-NEXT:  }
 // IMPL-EMPTY:
+// IMPL-NEXT:  llvm::StringRef llvm::tdl::getTdlAKindName(llvm::tdl::AKind x) {
+// IMPL-NEXT:    switch (x) {
+// IMPL-NEXT:      case TDLCV_vala:
+// IMPL-NEXT:        return "vala";
+// IMPL-NEXT:      case TDLCV_valb:
+// IMPL-NEXT:        return "valb";
+// IMPL-NEXT:      case TDLCV_valc:
+// IMPL-NEXT:        return "valc";
+// IMPL-NEXT:    }
+// IMPL-NEXT:    llvm_unreachable("Invalid Tdl AKind kind");
+// IMPL-NEXT:  }
+// IMPL-EMPTY:
 // IMPL-NEXT:  bool llvm::tdl::isAllowedClauseForDirective(Directive D, Clause C, unsigned Version) {
 // IMPL-NEXT:    assert(unsigned(D) <= llvm::tdl::Directive_enumSize);
 // IMPL-NEXT:    assert(unsigned(C) <= llvm::tdl::Clause_enumSize);
diff --git a/llvm/test/TableGen/interleave.td b/llvm/test/TableGen/interleave.td
index 098542ab29a18..c4d5c825d0fc3 100644
--- a/llvm/test/TableGen/interleave.td
+++ b/llvm/test/TableGen/interleave.td
@@ -77,6 +77,15 @@ def Rec6 {
   code OperatorList = !interleave(!listconcat(Operators, [[{;}]]), ", ");
 }
 
+// CHECK: def Rec7
+// CHECK:   str = "foo/bar/zoo";
+
+def Rec7 {
+  string foo = "foo";
+  string zoo = "oops, not zoo";
+  string str = !interleave([foo, "bar", zoo], "/");
+  let zoo = "zoo";
+}
 
 #ifdef ERROR1
 def op;
diff --git a/llvm/test/TableGen/substr.td b/llvm/test/TableGen/substr.td
new file mode 100644
index 0000000000000..5efe4ce69215e
--- /dev/null
+++ b/llvm/test/TableGen/substr.td
@@ -0,0 +1,81 @@
+// RUN: llvm-tblgen %s | FileCheck %s
+// RUN: not llvm-tblgen -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
+
+defvar claim = "This is the end of the world!";
+
+// CHECK: def Rec1
+// CHECK:   fullNoLength = "This is the end of the world!";
+// CHECK:   fullLength = "This is the end of the world!";
+// CHECK:   thisIsTheEnd = "This is the end";
+// CHECK:   DoorsSong = "the end";
+// CHECK:   finalNoLength = "end of the world!";
+// CHECK:   finalLength = "end of the world!";
+
+def Rec1 {
+  string fullNoLength = !substr(claim, 0);
+  string fullLength = !substr(claim, 0, 999);
+  string thisIsTheEnd = !substr(claim, 0, 15);
+  string DoorsSong = !substr(claim, 8, 7);
+  string finalNoLength = !substr(claim, 12);
+  string finalLength = !substr(claim, 12, !sub(!size(claim), 12));
+}
+
+// CHECK: def Rec2 {
+// CHECK:   lastName = "Flintstone";
+
+def Rec2 {
+  string firstName = "Fred";
+  string name = firstName # " " # "Flintstone";
+  string lastName = !substr(name, !add(!size(firstName), 1));
+}
+
+// CHECK: def Rec3 {
+// CHECK:   test1 = "";
+// CHECK:   test2 = "";
+// CHECK:   test3 = "";
+// CHECK:   test4 = "h";
+// CHECK:   test5 = "hello";
+// CHECK:   test6 = "";
+
+def Rec3 {
+  string test1 = !substr("", 0, 0);
+  string test2 = !substr("", 0, 9);
+  string test3 = !substr("hello", 0, 0);
+  string test4 = !substr("hello", 0, 1);
+  string test5 = !substr("hello", 0, 99);
+  string test6 = !substr("hello", 5, 99);
+}
+
+// CHECK: def Rec4
+// CHECK:   message = "This is the end of the world!";
+// CHECK:   messagePrefix = "This is th...";
+// CHECK:   warning = "Bad message: 'This is th...'";
+
+class C<string msg> {
+  string message = msg;
+  string messagePrefix = !substr(message, 0, 10) # "...";
+}
+
+def Rec4 : C<claim> {
+  string warning = "Bad message: '" # messagePrefix # "'";
+}
+
+#ifdef ERROR1
+
+// ERROR1: expected string, got type 'int'
+// ERROR1: expected int, got type 'bits<3>'
+// ERROR1: expected int, got type 'string'
+// ERROR1: !substr start position is out of range 0...29: 30
+// ERROR1: !substr length must be nonnegative
+
+def Rec8 {
+  string claim1 = !substr(42, 0, 3);
+  string claim2 = !substr(claim, 0b101);
+  string claim3 = !substr(claim, 0, "oops");
+}
+
+def Rec9 {
+  string claim1 = !substr(claim, !add(!size(claim), 1));
+  string claim2 = !substr(claim, 0, -13);
+}
+#endif
diff --git a/llvm/test/Transforms/AggressiveInstCombine/funnel.ll b/llvm/test/Transforms/AggressiveInstCombine/funnel.ll
index 545b8e1759827..1322e95920d20 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/funnel.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/funnel.ll
@@ -7,14 +7,11 @@ define i32 @fshl(i32 %a, i32 %b, i32 %c) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[END:%.*]], label [[FSHBB:%.*]]
 ; CHECK:       fshbb:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 32, [[C]]
-; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[B:%.*]], [[SUB]]
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[A:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[OR]], [[FSHBB]] ], [ [[A]], [[ENTRY:%.*]] ]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = freeze i32 [[B:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A:%.*]], i32 [[TMP0]], i32 [[C]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 entry:
   %cmp = icmp eq i32 %c, 0
@@ -38,14 +35,11 @@ define i32 @fshl_commute_phi(i32 %a, i32 %b, i32 %c) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[END:%.*]], label [[FSHBB:%.*]]
 ; CHECK:       fshbb:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 32, [[C]]
-; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[B:%.*]], [[SUB]]
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[A:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[A]], [[ENTRY:%.*]] ], [ [[OR]], [[FSHBB]] ]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = freeze i32 [[B:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A:%.*]], i32 [[TMP0]], i32 [[C]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 entry:
   %cmp = icmp eq i32 %c, 0
@@ -69,14 +63,11 @@ define i32 @fshl_commute_or(i32 %a, i32 %b, i32 %c) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[END:%.*]], label [[FSHBB:%.*]]
 ; CHECK:       fshbb:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 32, [[C]]
-; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[B:%.*]], [[SUB]]
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[A:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[A]], [[ENTRY:%.*]] ], [ [[OR]], [[FSHBB]] ]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = freeze i32 [[B:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A:%.*]], i32 [[TMP0]], i32 [[C]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 entry:
   %cmp = icmp eq i32 %c, 0
@@ -102,15 +93,12 @@ define i32 @fshl_insert_valid_location(i32 %a, i32 %b, i32 %c) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[END:%.*]], label [[FSHBB:%.*]]
 ; CHECK:       fshbb:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 32, [[C]]
-; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[B:%.*]], [[SUB]]
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[A:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[OR]], [[FSHBB]] ], [ [[A]], [[ENTRY:%.*]] ]
-; CHECK-NEXT:    [[OTHER:%.*]] = phi i32 [ 1, [[FSHBB]] ], [ 2, [[ENTRY]] ]
-; CHECK-NEXT:    [[RES:%.*]] = or i32 [[COND]], [[OTHER]]
+; CHECK-NEXT:    [[OTHER:%.*]] = phi i32 [ 1, [[FSHBB]] ], [ 2, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = freeze i32 [[B:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A:%.*]], i32 [[TMP0]], i32 [[C]])
+; CHECK-NEXT:    [[RES:%.*]] = or i32 [[TMP1]], [[OTHER]]
 ; CHECK-NEXT:    ret i32 [[RES]]
 ;
 entry:
@@ -137,14 +125,11 @@ define i32 @fshr(i32 %a, i32 %b, i32 %c) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[END:%.*]], label [[FSHBB:%.*]]
 ; CHECK:       fshbb:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 32, [[C]]
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
-; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[B:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[OR]], [[FSHBB]] ], [ [[B]], [[ENTRY:%.*]] ]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = freeze i32 [[A:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.fshr.i32(i32 [[TMP0]], i32 [[B:%.*]], i32 [[C]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 entry:
   %cmp = icmp eq i32 %c, 0
@@ -168,14 +153,11 @@ define i32 @fshr_commute_phi(i32 %a, i32 %b, i32 %c) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[END:%.*]], label [[FSHBB:%.*]]
 ; CHECK:       fshbb:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 32, [[C]]
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
-; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[B:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[B]], [[ENTRY:%.*]] ], [ [[OR]], [[FSHBB]] ]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = freeze i32 [[A:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.fshr.i32(i32 [[TMP0]], i32 [[B:%.*]], i32 [[C]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 entry:
   %cmp = icmp eq i32 %c, 0
@@ -199,14 +181,11 @@ define i32 @fshr_commute_or(i32 %a, i32 %b, i32 %c) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[END:%.*]], label [[FSHBB:%.*]]
 ; CHECK:       fshbb:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 32, [[C]]
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[A:%.*]], [[SUB]]
-; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[B:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[B]], [[ENTRY:%.*]] ], [ [[OR]], [[FSHBB]] ]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = freeze i32 [[A:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.fshr.i32(i32 [[TMP0]], i32 [[B:%.*]], i32 [[C]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 entry:
   %cmp = icmp eq i32 %c, 0
@@ -396,7 +375,7 @@ end:
   ret i32 %cond
 }
 
-; Negative test - wrong shift.
+; Negative test - wrong shift for rotate (but can be folded to a generic funnel shift).
 
 define i32 @not_fshr_5(i32 %a, i32 %b, i32 %c) {
 ; CHECK-LABEL: @not_fshr_5(
@@ -404,14 +383,11 @@ define i32 @not_fshr_5(i32 %a, i32 %b, i32 %c) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[C:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[END:%.*]], label [[FSHBB:%.*]]
 ; CHECK:       fshbb:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 32, [[C]]
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[C]], [[SUB]]
-; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[B:%.*]], [[C]]
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[B]], [[ENTRY:%.*]] ], [ [[OR]], [[FSHBB]] ]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = freeze i32 [[C]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.fshr.i32(i32 [[TMP0]], i32 [[B:%.*]], i32 [[C]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 entry:
   %cmp = icmp eq i32 %c, 0
@@ -500,3 +476,45 @@ end:
   ret i32 %cond
 }
 
+; PR48068 - Ensure we don't fold a funnel shift that depends on a shift value that
+; can't be hoisted out of a basic block.
+@a = global i32 0, align 4
+declare i32 @i(...)
+declare i32 @f(...)
+
+define i32 @PR48068() {
+; CHECK-LABEL: @PR48068(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CALL:%.*]] = call i32 bitcast (i32 (...)* @i to i32 ()*)()
+; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* @a, align 4
+; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
+; CHECK-NEXT:    br i1 [[TOBOOL_NOT]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[CALL]], [[TMP0]]
+; CHECK-NEXT:    [[CALL_I:%.*]] = call i32 bitcast (i32 (...)* @f to i32 ()*)()
+; CHECK-NEXT:    [[SUB_I:%.*]] = sub nsw i32 32, [[TMP0]]
+; CHECK-NEXT:    [[SHR_I:%.*]] = lshr i32 [[CALL_I]], [[SUB_I]]
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], [[SHR_I]]
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[H_0:%.*]] = phi i32 [ [[OR]], [[IF_THEN]] ], [ [[CALL]], [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32 [[H_0]]
+;
+entry:
+  %call = call i32 bitcast (i32 (...)* @i to i32 ()*)()
+  %0 = load i32, i32* @a, align 4
+  %tobool.not = icmp eq i32 %0, 0
+  br i1 %tobool.not, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %shl = shl i32 %call, %0
+  %call.i = call i32 bitcast (i32 (...)* @f to i32 ()*)()
+  %sub.i = sub nsw i32 32, %0
+  %shr.i = lshr i32 %call.i, %sub.i
+  %or = or i32 %shl, %shr.i
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  %h.0 = phi i32 [ %or, %if.then ], [ %call, %entry ]
+  ret i32 %h.0
+}
diff --git a/llvm/test/Transforms/AggressiveInstCombine/rotate.ll b/llvm/test/Transforms/AggressiveInstCombine/rotate.ll
index e47fa9be6f83e..0abc6c574603c 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/rotate.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/rotate.ll
@@ -370,7 +370,7 @@ end:
   ret i32 %cond
 }
 
-; Negative test - wrong shift.
+; Negative test - wrong shift for rotate (but can be folded to a generic funnel shift).
 
 define i32 @not_rotr_5(i32 %a, i32 %b) {
 ; CHECK-LABEL: @not_rotr_5(
@@ -378,14 +378,11 @@ define i32 @not_rotr_5(i32 %a, i32 %b) {
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[B:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP]], label [[END:%.*]], label [[ROTBB:%.*]]
 ; CHECK:       rotbb:
-; CHECK-NEXT:    [[SUB:%.*]] = sub i32 32, [[B]]
-; CHECK-NEXT:    [[SHL:%.*]] = shl i32 [[B]], [[SUB]]
-; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[A:%.*]], [[B]]
-; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
-; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[A]], [[ENTRY:%.*]] ], [ [[OR]], [[ROTBB]] ]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP0:%.*]] = freeze i32 [[B]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.fshr.i32(i32 [[TMP0]], i32 [[A:%.*]], i32 [[B]])
+; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
 entry:
   %cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll b/llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll
new file mode 100644
index 0000000000000..845a00dc4e9d8
--- /dev/null
+++ b/llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll
@@ -0,0 +1,847 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-attributes
+; RUN: opt -attributor -enable-new-pm=0 -attributor-manifest-internal  -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_NPM,NOT_CGSCC_OPM,NOT_TUNIT_NPM,IS__TUNIT____,IS________OPM,IS__TUNIT_OPM
+; RUN: opt -aa-pipeline=basic-aa -passes=attributor -attributor-manifest-internal  -attributor-max-iterations-verify -attributor-annotate-decl-cs -attributor-max-iterations=1 -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_CGSCC_OPM,NOT_CGSCC_NPM,NOT_TUNIT_OPM,IS__TUNIT____,IS________NPM,IS__TUNIT_NPM
+; RUN: opt -attributor-cgscc -enable-new-pm=0 -attributor-manifest-internal  -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_NPM,IS__CGSCC____,IS________OPM,IS__CGSCC_OPM
+; RUN: opt -aa-pipeline=basic-aa -passes=attributor-cgscc -attributor-manifest-internal  -attributor-annotate-decl-cs -S < %s | FileCheck %s --check-prefixes=CHECK,NOT_TUNIT_NPM,NOT_TUNIT_OPM,NOT_CGSCC_OPM,IS__CGSCC____,IS________NPM,IS__CGSCC_NPM
+
+; Determine dereference-ability before unused loads get deleted:
+; https://bugs.llvm.org/show_bug.cgi?id=21780
+
+define <4 x double> @PR21780(double* %ptr) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind readonly willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@PR21780
+; IS__TUNIT____-SAME: (double* nocapture nofree nonnull readonly align 8 dereferenceable(32) [[PTR:%.*]]) [[ATTR0:#.*]] {
+; IS__TUNIT____-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[PTR]], i64 1
+; IS__TUNIT____-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[PTR]], i64 2
+; IS__TUNIT____-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[PTR]], i64 3
+; IS__TUNIT____-NEXT:    [[T0:%.*]] = load double, double* [[PTR]], align 8
+; IS__TUNIT____-NEXT:    [[T1:%.*]] = load double, double* [[ARRAYIDX1]], align 8
+; IS__TUNIT____-NEXT:    [[T2:%.*]] = load double, double* [[ARRAYIDX2]], align 8
+; IS__TUNIT____-NEXT:    [[T3:%.*]] = load double, double* [[ARRAYIDX3]], align 8
+; IS__TUNIT____-NEXT:    [[VECINIT0:%.*]] = insertelement <4 x double> poison, double [[T0]], i32 0
+; IS__TUNIT____-NEXT:    [[VECINIT1:%.*]] = insertelement <4 x double> [[VECINIT0]], double [[T1]], i32 1
+; IS__TUNIT____-NEXT:    [[VECINIT2:%.*]] = insertelement <4 x double> [[VECINIT1]], double [[T2]], i32 2
+; IS__TUNIT____-NEXT:    [[VECINIT3:%.*]] = insertelement <4 x double> [[VECINIT2]], double [[T3]], i32 3
+; IS__TUNIT____-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x double> [[VECINIT3]], <4 x double> [[VECINIT3]], <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+; IS__TUNIT____-NEXT:    ret <4 x double> [[SHUFFLE]]
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@PR21780
+; IS__CGSCC____-SAME: (double* nocapture nofree nonnull readonly align 8 dereferenceable(32) [[PTR:%.*]]) [[ATTR0:#.*]] {
+; IS__CGSCC____-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds double, double* [[PTR]], i64 1
+; IS__CGSCC____-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds double, double* [[PTR]], i64 2
+; IS__CGSCC____-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[PTR]], i64 3
+; IS__CGSCC____-NEXT:    [[T0:%.*]] = load double, double* [[PTR]], align 8
+; IS__CGSCC____-NEXT:    [[T1:%.*]] = load double, double* [[ARRAYIDX1]], align 8
+; IS__CGSCC____-NEXT:    [[T2:%.*]] = load double, double* [[ARRAYIDX2]], align 8
+; IS__CGSCC____-NEXT:    [[T3:%.*]] = load double, double* [[ARRAYIDX3]], align 8
+; IS__CGSCC____-NEXT:    [[VECINIT0:%.*]] = insertelement <4 x double> poison, double [[T0]], i32 0
+; IS__CGSCC____-NEXT:    [[VECINIT1:%.*]] = insertelement <4 x double> [[VECINIT0]], double [[T1]], i32 1
+; IS__CGSCC____-NEXT:    [[VECINIT2:%.*]] = insertelement <4 x double> [[VECINIT1]], double [[T2]], i32 2
+; IS__CGSCC____-NEXT:    [[VECINIT3:%.*]] = insertelement <4 x double> [[VECINIT2]], double [[T3]], i32 3
+; IS__CGSCC____-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x double> [[VECINIT3]], <4 x double> [[VECINIT3]], <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+; IS__CGSCC____-NEXT:    ret <4 x double> [[SHUFFLE]]
+;
+
+  ; GEP of index 0 is simplified away.
+  %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 1
+  %arrayidx2 = getelementptr inbounds double, double* %ptr, i64 2
+  %arrayidx3 = getelementptr inbounds double, double* %ptr, i64 3
+
+  %t0 = load double, double* %ptr, align 8
+  %t1 = load double, double* %arrayidx1, align 8
+  %t2 = load double, double* %arrayidx2, align 8
+  %t3 = load double, double* %arrayidx3, align 8
+
+  %vecinit0 = insertelement <4 x double> poison, double %t0, i32 0
+  %vecinit1 = insertelement <4 x double> %vecinit0, double %t1, i32 1
+  %vecinit2 = insertelement <4 x double> %vecinit1, double %t2, i32 2
+  %vecinit3 = insertelement <4 x double> %vecinit2, double %t3, i32 3
+  %shuffle = shufflevector <4 x double> %vecinit3, <4 x double> %vecinit3, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+  ret <4 x double> %shuffle
+}
+
+
+define double @PR21780_only_access3_with_inbounds(double* %ptr) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind readonly willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@PR21780_only_access3_with_inbounds
+; IS__TUNIT____-SAME: (double* nocapture nofree nonnull readonly align 8 dereferenceable(32) [[PTR:%.*]]) [[ATTR0]] {
+; IS__TUNIT____-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[PTR]], i64 3
+; IS__TUNIT____-NEXT:    [[T3:%.*]] = load double, double* [[ARRAYIDX3]], align 8
+; IS__TUNIT____-NEXT:    ret double [[T3]]
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@PR21780_only_access3_with_inbounds
+; IS__CGSCC____-SAME: (double* nocapture nofree nonnull readonly align 8 dereferenceable(32) [[PTR:%.*]]) [[ATTR0]] {
+; IS__CGSCC____-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds double, double* [[PTR]], i64 3
+; IS__CGSCC____-NEXT:    [[T3:%.*]] = load double, double* [[ARRAYIDX3]], align 8
+; IS__CGSCC____-NEXT:    ret double [[T3]]
+;
+
+  %arrayidx3 = getelementptr inbounds double, double* %ptr, i64 3
+  %t3 = load double, double* %arrayidx3, align 8
+  ret double %t3
+}
+
+define double @PR21780_only_access3_without_inbounds(double* %ptr) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind readonly willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@PR21780_only_access3_without_inbounds
+; IS__TUNIT____-SAME: (double* nocapture nofree readonly align 8 [[PTR:%.*]]) [[ATTR0]] {
+; IS__TUNIT____-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr double, double* [[PTR]], i64 3
+; IS__TUNIT____-NEXT:    [[T3:%.*]] = load double, double* [[ARRAYIDX3]], align 8
+; IS__TUNIT____-NEXT:    ret double [[T3]]
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@PR21780_only_access3_without_inbounds
+; IS__CGSCC____-SAME: (double* nocapture nofree readonly align 8 [[PTR:%.*]]) [[ATTR0]] {
+; IS__CGSCC____-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr double, double* [[PTR]], i64 3
+; IS__CGSCC____-NEXT:    [[T3:%.*]] = load double, double* [[ARRAYIDX3]], align 8
+; IS__CGSCC____-NEXT:    ret double [[T3]]
+;
+  %arrayidx3 = getelementptr double, double* %ptr, i64 3
+  %t3 = load double, double* %arrayidx3, align 8
+  ret double %t3
+}
+
+define double @PR21780_without_inbounds(double* %ptr) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind readonly willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@PR21780_without_inbounds
+; IS__TUNIT____-SAME: (double* nocapture nofree nonnull readonly align 8 dereferenceable(32) [[PTR:%.*]]) [[ATTR0]] {
+; IS__TUNIT____-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr double, double* [[PTR]], i64 3
+; IS__TUNIT____-NEXT:    [[T3:%.*]] = load double, double* [[ARRAYIDX3]], align 8
+; IS__TUNIT____-NEXT:    ret double [[T3]]
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind readonly willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@PR21780_without_inbounds
+; IS__CGSCC____-SAME: (double* nocapture nofree nonnull readonly align 8 dereferenceable(32) [[PTR:%.*]]) [[ATTR0]] {
+; IS__CGSCC____-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr double, double* [[PTR]], i64 3
+; IS__CGSCC____-NEXT:    [[T3:%.*]] = load double, double* [[ARRAYIDX3]], align 8
+; IS__CGSCC____-NEXT:    ret double [[T3]]
+;
+
+  %arrayidx1 = getelementptr double, double* %ptr, i64 1
+  %arrayidx2 = getelementptr double, double* %ptr, i64 2
+  %arrayidx3 = getelementptr double, double* %ptr, i64 3
+
+  %t0 = load double, double* %ptr, align 8
+  %t1 = load double, double* %arrayidx1, align 8
+  %t2 = load double, double* %arrayidx2, align 8
+  %t3 = load double, double* %arrayidx3, align 8
+
+  ret double %t3
+}
+
+; Unsimplified, but still valid. Also, throw in some bogus arguments.
+
+define void @gep0(i8* %unused, i8* %other, i8* %ptr) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@gep0
+; IS__TUNIT____-SAME: (i8* nocapture nofree readnone [[UNUSED:%.*]], i8* nocapture nofree nonnull writeonly dereferenceable(1) [[OTHER:%.*]], i8* nocapture nofree nonnull readonly dereferenceable(3) [[PTR:%.*]]) [[ATTR1:#.*]] {
+; IS__TUNIT____-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr i8, i8* [[PTR]], i64 2
+; IS__TUNIT____-NEXT:    [[T2:%.*]] = load i8, i8* [[ARRAYIDX2]], align 1
+; IS__TUNIT____-NEXT:    store i8 [[T2]], i8* [[OTHER]], align 1
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@gep0
+; IS__CGSCC____-SAME: (i8* nocapture nofree readnone [[UNUSED:%.*]], i8* nocapture nofree nonnull writeonly dereferenceable(1) [[OTHER:%.*]], i8* nocapture nofree nonnull readonly dereferenceable(3) [[PTR:%.*]]) [[ATTR1:#.*]] {
+; IS__CGSCC____-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr i8, i8* [[PTR]], i64 2
+; IS__CGSCC____-NEXT:    [[T2:%.*]] = load i8, i8* [[ARRAYIDX2]], align 1
+; IS__CGSCC____-NEXT:    store i8 [[T2]], i8* [[OTHER]], align 1
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx0 = getelementptr i8, i8* %ptr, i64 0
+  %arrayidx1 = getelementptr i8, i8* %ptr, i64 1
+  %arrayidx2 = getelementptr i8, i8* %ptr, i64 2
+  %t0 = load i8, i8* %arrayidx0
+  %t1 = load i8, i8* %arrayidx1
+  %t2 = load i8, i8* %arrayidx2
+  store i8 %t2, i8* %other
+  ret void
+}
+
+; Order of accesses does not change computation.
+; Multiple arguments may be dereferenceable.
+
+define void @ordering(i8* %ptr1, i32* %ptr2) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@ordering
+; IS__TUNIT____-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(3) [[PTR1:%.*]], i32* nocapture nofree nonnull readnone align 4 dereferenceable(8) [[PTR2:%.*]]) [[ATTR2:#.*]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@ordering
+; IS__CGSCC____-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(3) [[PTR1:%.*]], i32* nocapture nofree nonnull readnone align 4 dereferenceable(8) [[PTR2:%.*]]) [[ATTR2:#.*]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %a20 = getelementptr i32, i32* %ptr2, i64 0
+  %a12 = getelementptr i8, i8* %ptr1, i64 2
+  %t12 = load i8, i8* %a12
+  %a11 = getelementptr i8, i8* %ptr1, i64 1
+  %t20 = load i32, i32* %a20
+  %a10 = getelementptr i8, i8* %ptr1, i64 0
+  %t10 = load i8, i8* %a10
+  %t11 = load i8, i8* %a11
+  %a21 = getelementptr i32, i32* %ptr2, i64 1
+  %t21 = load i32, i32* %a21
+  ret void
+}
+
+; Not in entry block.
+
+define void @not_entry_but_guaranteed_to_execute(i8* %ptr) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@not_entry_but_guaranteed_to_execute
+; IS__TUNIT____-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(3) [[PTR:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:  entry:
+; IS__TUNIT____-NEXT:    br label [[EXIT:%.*]]
+; IS__TUNIT____:       exit:
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@not_entry_but_guaranteed_to_execute
+; IS__CGSCC____-SAME: (i8* nocapture nofree nonnull readnone dereferenceable(3) [[PTR:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:  entry:
+; IS__CGSCC____-NEXT:    br label [[EXIT:%.*]]
+; IS__CGSCC____:       exit:
+; IS__CGSCC____-NEXT:    ret void
+;
+entry:
+  br label %exit
+exit:
+  %arrayidx0 = getelementptr i8, i8* %ptr, i64 0
+  %arrayidx1 = getelementptr i8, i8* %ptr, i64 1
+  %arrayidx2 = getelementptr i8, i8* %ptr, i64 2
+  %t0 = load i8, i8* %arrayidx0
+  %t1 = load i8, i8* %arrayidx1
+  %t2 = load i8, i8* %arrayidx2
+  ret void
+}
+
+; Not in entry block and not guaranteed to execute.
+
+define void @not_entry_not_guaranteed_to_execute(i8* %ptr, i1 %cond) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@not_entry_not_guaranteed_to_execute
+; IS__TUNIT____-SAME: (i8* nocapture nofree readnone [[PTR:%.*]], i1 [[COND:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:  entry:
+; IS__TUNIT____-NEXT:    br i1 [[COND]], label [[LOADS:%.*]], label [[EXIT:%.*]]
+; IS__TUNIT____:       loads:
+; IS__TUNIT____-NEXT:    ret void
+; IS__TUNIT____:       exit:
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@not_entry_not_guaranteed_to_execute
+; IS__CGSCC____-SAME: (i8* nocapture nofree readnone [[PTR:%.*]], i1 [[COND:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:  entry:
+; IS__CGSCC____-NEXT:    br i1 [[COND]], label [[LOADS:%.*]], label [[EXIT:%.*]]
+; IS__CGSCC____:       loads:
+; IS__CGSCC____-NEXT:    ret void
+; IS__CGSCC____:       exit:
+; IS__CGSCC____-NEXT:    ret void
+;
+entry:
+  br i1 %cond, label %loads, label %exit
+loads:
+  %arrayidx0 = getelementptr i8, i8* %ptr, i64 0
+  %arrayidx1 = getelementptr i8, i8* %ptr, i64 1
+  %arrayidx2 = getelementptr i8, i8* %ptr, i64 2
+  %t0 = load i8, i8* %arrayidx0
+  %t1 = load i8, i8* %arrayidx1
+  %t2 = load i8, i8* %arrayidx2
+  ret void
+exit:
+  ret void
+}
+
+; The last load may not execute, so derefenceable bytes only covers the 1st two loads.
+
+define void @partial_in_entry(i16* %ptr, i1 %cond) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@partial_in_entry
+; IS__TUNIT____-SAME: (i16* nocapture nofree nonnull readnone align 2 dereferenceable(4) [[PTR:%.*]], i1 [[COND:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:  entry:
+; IS__TUNIT____-NEXT:    br i1 [[COND]], label [[LOADS:%.*]], label [[EXIT:%.*]]
+; IS__TUNIT____:       loads:
+; IS__TUNIT____-NEXT:    ret void
+; IS__TUNIT____:       exit:
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@partial_in_entry
+; IS__CGSCC____-SAME: (i16* nocapture nofree nonnull readnone align 2 dereferenceable(4) [[PTR:%.*]], i1 [[COND:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:  entry:
+; IS__CGSCC____-NEXT:    br i1 [[COND]], label [[LOADS:%.*]], label [[EXIT:%.*]]
+; IS__CGSCC____:       loads:
+; IS__CGSCC____-NEXT:    ret void
+; IS__CGSCC____:       exit:
+; IS__CGSCC____-NEXT:    ret void
+;
+entry:
+  %arrayidx0 = getelementptr i16, i16* %ptr, i64 0
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t0 = load i16, i16* %arrayidx0
+  %t1 = load i16, i16* %arrayidx1
+  br i1 %cond, label %loads, label %exit
+loads:
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+exit:
+  ret void
+}
+
+; The volatile load can't be used to prove a non-volatile access is allowed.
+; The 2nd and 3rd loads may never execute.
+
+define void @volatile_is_not_dereferenceable(i16* %ptr) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nounwind willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@volatile_is_not_dereferenceable
+; IS__TUNIT____-SAME: (i16* nofree align 2 [[PTR:%.*]]) [[ATTR3:#.*]] {
+; IS__TUNIT____-NEXT:    [[ARRAYIDX0:%.*]] = getelementptr i16, i16* [[PTR]], i64 0
+; IS__TUNIT____-NEXT:    [[T0:%.*]] = load volatile i16, i16* [[ARRAYIDX0]], align 2
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nounwind willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@volatile_is_not_dereferenceable
+; IS__CGSCC____-SAME: (i16* nofree align 2 [[PTR:%.*]]) [[ATTR3:#.*]] {
+; IS__CGSCC____-NEXT:    [[ARRAYIDX0:%.*]] = getelementptr i16, i16* [[PTR]], i64 0
+; IS__CGSCC____-NEXT:    [[T0:%.*]] = load volatile i16, i16* [[ARRAYIDX0]], align 2
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx0 = getelementptr i16, i16* %ptr, i64 0
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t0 = load volatile i16, i16* %arrayidx0
+  %t1 = load i16, i16* %arrayidx1
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+}
+
+; TODO: We should allow inference for atomic (but not volatile) ops.
+
+define void @atomic_is_alright(i16* %ptr) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@atomic_is_alright
+; IS__TUNIT____-SAME: (i16* nocapture nofree nonnull readnone align 2 dereferenceable(6) [[PTR:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@atomic_is_alright
+; IS__CGSCC____-SAME: (i16* nocapture nofree nonnull readnone align 2 dereferenceable(6) [[PTR:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx0 = getelementptr i16, i16* %ptr, i64 0
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t0 = load atomic i16, i16* %arrayidx0 unordered, align 2
+  %t1 = load i16, i16* %arrayidx1
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+}
+
+declare void @may_not_return()
+
+define void @not_guaranteed_to_transfer_execution(i16* %ptr) {
+; CHECK-LABEL: define {{[^@]+}}@not_guaranteed_to_transfer_execution
+; CHECK-SAME: (i16* nocapture nofree nonnull readnone align 2 dereferenceable(2) [[PTR:%.*]]) {
+; CHECK-NEXT:    call void @may_not_return()
+; CHECK-NEXT:    ret void
+;
+  %arrayidx0 = getelementptr i16, i16* %ptr, i64 0
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t0 = load i16, i16* %arrayidx0
+  call void @may_not_return()
+  %t1 = load i16, i16* %arrayidx1
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+}
+
+; We must have consecutive accesses.
+
+define void @variable_gep_index(i8* %unused, i8* %ptr, i64 %variable_index) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@variable_gep_index
+; IS__TUNIT____-SAME: (i8* nocapture nofree readnone [[UNUSED:%.*]], i8* nocapture nofree nonnull readnone dereferenceable(1) [[PTR:%.*]], i64 [[VARIABLE_INDEX:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@variable_gep_index
+; IS__CGSCC____-SAME: (i8* nocapture nofree readnone [[UNUSED:%.*]], i8* nocapture nofree nonnull readnone dereferenceable(1) [[PTR:%.*]], i64 [[VARIABLE_INDEX:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx1 = getelementptr i8, i8* %ptr, i64 %variable_index
+  %arrayidx2 = getelementptr i8, i8* %ptr, i64 2
+  %t0 = load i8, i8* %ptr
+  %t1 = load i8, i8* %arrayidx1
+  %t2 = load i8, i8* %arrayidx2
+  ret void
+}
+
+; Deal with >1 GEP index.
+
+define void @multi_index_gep(<4 x i8>* %ptr) {
+; FIXME: %ptr should be dereferenceable(4)
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@multi_index_gep
+; IS__TUNIT____-SAME: (<4 x i8>* nocapture nofree nonnull readnone dereferenceable(1) [[PTR:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@multi_index_gep
+; IS__CGSCC____-SAME: (<4 x i8>* nocapture nofree nonnull readnone dereferenceable(1) [[PTR:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx00 = getelementptr <4 x i8>, <4 x i8>* %ptr, i64 0, i64 0
+  %t0 = load i8, i8* %arrayidx00
+  ret void
+}
+
+; Could round weird bitwidths down?
+
+define void @not_byte_multiple(i9* %ptr) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@not_byte_multiple
+; IS__TUNIT____-SAME: (i9* nocapture nofree nonnull readnone align 2 dereferenceable(2) [[PTR:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@not_byte_multiple
+; IS__CGSCC____-SAME: (i9* nocapture nofree nonnull readnone align 2 dereferenceable(2) [[PTR:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx0 = getelementptr i9, i9* %ptr, i64 0
+  %t0 = load i9, i9* %arrayidx0
+  ret void
+}
+
+; Missing direct access from the pointer.
+
+define void @no_pointer_deref(i16* %ptr) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@no_pointer_deref
+; IS__TUNIT____-SAME: (i16* nocapture nofree readnone align 2 [[PTR:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@no_pointer_deref
+; IS__CGSCC____-SAME: (i16* nocapture nofree readnone align 2 [[PTR:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t1 = load i16, i16* %arrayidx1
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+}
+
+; Out-of-order is ok, but missing access concludes dereferenceable range.
+
+define void @non_consecutive(i32* %ptr) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@non_consecutive
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(8) [[PTR:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@non_consecutive
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(8) [[PTR:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx1 = getelementptr i32, i32* %ptr, i64 1
+  %arrayidx0 = getelementptr i32, i32* %ptr, i64 0
+  %arrayidx3 = getelementptr i32, i32* %ptr, i64 3
+  %t1 = load i32, i32* %arrayidx1
+  %t0 = load i32, i32* %arrayidx0
+  %t3 = load i32, i32* %arrayidx3
+  ret void
+}
+
+; Improve on existing dereferenceable attribute.
+
+define void @more_bytes(i32* dereferenceable(8) %ptr) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@more_bytes
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(16) [[PTR:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@more_bytes
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(16) [[PTR:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx3 = getelementptr i32, i32* %ptr, i64 3
+  %arrayidx1 = getelementptr i32, i32* %ptr, i64 1
+  %arrayidx0 = getelementptr i32, i32* %ptr, i64 0
+  %arrayidx2 = getelementptr i32, i32* %ptr, i64 2
+  %t3 = load i32, i32* %arrayidx3
+  %t1 = load i32, i32* %arrayidx1
+  %t2 = load i32, i32* %arrayidx2
+  %t0 = load i32, i32* %arrayidx0
+  ret void
+}
+
+; Improve on existing dereferenceable_or_null attribute.
+
+define void @more_bytes_and_not_null(i32* dereferenceable_or_null(8) %ptr) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@more_bytes_and_not_null
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(16) [[PTR:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@more_bytes_and_not_null
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(16) [[PTR:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx3 = getelementptr i32, i32* %ptr, i64 3
+  %arrayidx1 = getelementptr i32, i32* %ptr, i64 1
+  %arrayidx0 = getelementptr i32, i32* %ptr, i64 0
+  %arrayidx2 = getelementptr i32, i32* %ptr, i64 2
+  %t3 = load i32, i32* %arrayidx3
+  %t1 = load i32, i32* %arrayidx1
+  %t2 = load i32, i32* %arrayidx2
+  %t0 = load i32, i32* %arrayidx0
+  ret void
+}
+
+; But don't pessimize existing dereferenceable attribute.
+
+define void @better_bytes(i32* dereferenceable(100) %ptr) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@better_bytes
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(100) [[PTR:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@better_bytes
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(100) [[PTR:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arrayidx3 = getelementptr i32, i32* %ptr, i64 3
+  %arrayidx1 = getelementptr i32, i32* %ptr, i64 1
+  %arrayidx0 = getelementptr i32, i32* %ptr, i64 0
+  %arrayidx2 = getelementptr i32, i32* %ptr, i64 2
+  %t3 = load i32, i32* %arrayidx3
+  %t1 = load i32, i32* %arrayidx1
+  %t2 = load i32, i32* %arrayidx2
+  %t0 = load i32, i32* %arrayidx0
+  ret void
+}
+
+define void @bitcast(i32* %arg) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@bitcast
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(8) [[ARG:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@bitcast
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(8) [[ARG:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %ptr = bitcast i32* %arg to float*
+  %arrayidx0 = getelementptr float, float* %ptr, i64 0
+  %arrayidx1 = getelementptr float, float* %ptr, i64 1
+  %t0 = load float, float* %arrayidx0
+  %t1 = load float, float* %arrayidx1
+  ret void
+}
+
+define void @bitcast_different_sizes(double* %arg1, i8* %arg2) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@bitcast_different_sizes
+; IS__TUNIT____-SAME: (double* nocapture nofree nonnull readnone align 4 dereferenceable(12) [[ARG1:%.*]], i8* nocapture nofree nonnull readnone align 4 dereferenceable(16) [[ARG2:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@bitcast_different_sizes
+; IS__CGSCC____-SAME: (double* nocapture nofree nonnull readnone align 4 dereferenceable(12) [[ARG1:%.*]], i8* nocapture nofree nonnull readnone align 4 dereferenceable(16) [[ARG2:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %ptr1 = bitcast double* %arg1 to float*
+  %a10 = getelementptr float, float* %ptr1, i64 0
+  %a11 = getelementptr float, float* %ptr1, i64 1
+  %a12 = getelementptr float, float* %ptr1, i64 2
+  %ld10 = load float, float* %a10
+  %ld11 = load float, float* %a11
+  %ld12 = load float, float* %a12
+
+  %ptr2 = bitcast i8* %arg2 to i64*
+  %a20 = getelementptr i64, i64* %ptr2, i64 0
+  %a21 = getelementptr i64, i64* %ptr2, i64 1
+  %ld20 = load i64, i64* %a20
+  %ld21 = load i64, i64* %a21
+  ret void
+}
+
+define void @negative_offset(i32* %arg) {
+; IS__TUNIT____: Function Attrs: nofree nosync nounwind readnone willreturn
+; IS__TUNIT____-LABEL: define {{[^@]+}}@negative_offset
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(4) [[ARG:%.*]]) [[ATTR2]] {
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: nofree norecurse nosync nounwind readnone willreturn
+; IS__CGSCC____-LABEL: define {{[^@]+}}@negative_offset
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull readnone align 4 dereferenceable(4) [[ARG:%.*]]) [[ATTR2]] {
+; IS__CGSCC____-NEXT:    ret void
+;
+  %ptr = bitcast i32* %arg to float*
+  %arrayidx0 = getelementptr float, float* %ptr, i64 0
+  %arrayidx1 = getelementptr float, float* %ptr, i64 -1
+  %t0 = load float, float* %arrayidx0
+  %t1 = load float, float* %arrayidx1
+  ret void
+}
+
+define void @stores(i32* %arg) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
+; IS__TUNIT____-LABEL: define {{[^@]+}}@stores
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull writeonly align 4 dereferenceable(8) [[ARG:%.*]]) [[ATTR4:#.*]] {
+; IS__TUNIT____-NEXT:    [[PTR:%.*]] = bitcast i32* [[ARG]] to float*
+; IS__TUNIT____-NEXT:    [[ARRAYIDX0:%.*]] = getelementptr float, float* [[PTR]], i64 0
+; IS__TUNIT____-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr float, float* [[PTR]], i64 1
+; IS__TUNIT____-NEXT:    store float 1.000000e+00, float* [[ARRAYIDX0]], align 4
+; IS__TUNIT____-NEXT:    store float 2.000000e+00, float* [[ARRAYIDX1]], align 4
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly
+; IS__CGSCC____-LABEL: define {{[^@]+}}@stores
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull writeonly align 4 dereferenceable(8) [[ARG:%.*]]) [[ATTR4:#.*]] {
+; IS__CGSCC____-NEXT:    [[PTR:%.*]] = bitcast i32* [[ARG]] to float*
+; IS__CGSCC____-NEXT:    [[ARRAYIDX0:%.*]] = getelementptr float, float* [[PTR]], i64 0
+; IS__CGSCC____-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr float, float* [[PTR]], i64 1
+; IS__CGSCC____-NEXT:    store float 1.000000e+00, float* [[ARRAYIDX0]], align 4
+; IS__CGSCC____-NEXT:    store float 2.000000e+00, float* [[ARRAYIDX1]], align 4
+; IS__CGSCC____-NEXT:    ret void
+;
+  %ptr = bitcast i32* %arg to float*
+  %arrayidx0 = getelementptr float, float* %ptr, i64 0
+  %arrayidx1 = getelementptr float, float* %ptr, i64 1
+  store float 1.0, float* %arrayidx0
+  store float 2.0, float* %arrayidx1
+  ret void
+}
+
+define void @load_store(i32* %arg) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
+; IS__TUNIT____-LABEL: define {{[^@]+}}@load_store
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull writeonly align 4 dereferenceable(8) [[ARG:%.*]]) [[ATTR4]] {
+; IS__TUNIT____-NEXT:    [[PTR:%.*]] = bitcast i32* [[ARG]] to float*
+; IS__TUNIT____-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr float, float* [[PTR]], i64 1
+; IS__TUNIT____-NEXT:    store float 2.000000e+00, float* [[ARRAYIDX1]], align 4
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly
+; IS__CGSCC____-LABEL: define {{[^@]+}}@load_store
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull writeonly align 4 dereferenceable(8) [[ARG:%.*]]) [[ATTR4]] {
+; IS__CGSCC____-NEXT:    [[PTR:%.*]] = bitcast i32* [[ARG]] to float*
+; IS__CGSCC____-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr float, float* [[PTR]], i64 1
+; IS__CGSCC____-NEXT:    store float 2.000000e+00, float* [[ARRAYIDX1]], align 4
+; IS__CGSCC____-NEXT:    ret void
+;
+  %ptr = bitcast i32* %arg to float*
+  %arrayidx0 = getelementptr float, float* %ptr, i64 0
+  %arrayidx1 = getelementptr float, float* %ptr, i64 1
+  %t1 = load float, float* %arrayidx0
+  store float 2.0, float* %arrayidx1
+  ret void
+}
+
+define void @different_size1(i32* %arg) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
+; IS__TUNIT____-LABEL: define {{[^@]+}}@different_size1
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull writeonly align 8 dereferenceable(8) [[ARG:%.*]]) [[ATTR4]] {
+; IS__TUNIT____-NEXT:    [[ARG_CAST:%.*]] = bitcast i32* [[ARG]] to double*
+; IS__TUNIT____-NEXT:    store double 0.000000e+00, double* [[ARG_CAST]], align 8
+; IS__TUNIT____-NEXT:    store i32 0, i32* [[ARG]], align 8
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly
+; IS__CGSCC____-LABEL: define {{[^@]+}}@different_size1
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull writeonly align 8 dereferenceable(8) [[ARG:%.*]]) [[ATTR4]] {
+; IS__CGSCC____-NEXT:    [[ARG_CAST:%.*]] = bitcast i32* [[ARG]] to double*
+; IS__CGSCC____-NEXT:    store double 0.000000e+00, double* [[ARG_CAST]], align 8
+; IS__CGSCC____-NEXT:    store i32 0, i32* [[ARG]], align 8
+; IS__CGSCC____-NEXT:    ret void
+;
+  %arg-cast = bitcast i32* %arg to double*
+  store double 0.000000e+00, double* %arg-cast
+  store i32 0, i32* %arg
+  ret void
+}
+
+define void @different_size2(i32* %arg) {
+; IS__TUNIT____: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
+; IS__TUNIT____-LABEL: define {{[^@]+}}@different_size2
+; IS__TUNIT____-SAME: (i32* nocapture nofree nonnull writeonly align 8 dereferenceable(8) [[ARG:%.*]]) [[ATTR4]] {
+; IS__TUNIT____-NEXT:    store i32 0, i32* [[ARG]], align 8
+; IS__TUNIT____-NEXT:    [[ARG_CAST:%.*]] = bitcast i32* [[ARG]] to double*
+; IS__TUNIT____-NEXT:    store double 0.000000e+00, double* [[ARG_CAST]], align 8
+; IS__TUNIT____-NEXT:    ret void
+;
+; IS__CGSCC____: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly
+; IS__CGSCC____-LABEL: define {{[^@]+}}@different_size2
+; IS__CGSCC____-SAME: (i32* nocapture nofree nonnull writeonly align 8 dereferenceable(8) [[ARG:%.*]]) [[ATTR4]] {
+; IS__CGSCC____-NEXT:    store i32 0, i32* [[ARG]], align 8
+; IS__CGSCC____-NEXT:    [[ARG_CAST:%.*]] = bitcast i32* [[ARG]] to double*
+; IS__CGSCC____-NEXT:    store double 0.000000e+00, double* [[ARG_CAST]], align 8
+; IS__CGSCC____-NEXT:    ret void
+;
+  store i32 0, i32* %arg
+  %arg-cast = bitcast i32* %arg to double*
+  store double 0.000000e+00, double* %arg-cast
+  ret void
+}
+
+; Make use of MustBeExecuted Explorer
+;
+; [CFG]
+; entry
+;  / \
+; l1 l2
+; | X |
+; l3 l4
+;  \ /
+;  l5
+;  / \
+; l6 l7
+;  \ /
+;  end
+; According to the above CFG, we can see that instructions in l5 Block must be executed.
+; Therefore, %p must be dereferenced.
+;
+; ATTRIBUTOR_CGSCC_NPM-LABEL: define i32 @require_cfg_analysis(i32 %c, i32* {{.*}} dereferenceable(4) %p)
+define i32 @require_cfg_analysis(i32 %c, i32* %p) {
+; IS__TUNIT_OPM: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
+; IS__TUNIT_OPM-LABEL: define {{[^@]+}}@require_cfg_analysis
+; IS__TUNIT_OPM-SAME: (i32 [[C:%.*]], i32* nocapture nofree writeonly [[P:%.*]]) [[ATTR4:#.*]] {
+; IS__TUNIT_OPM-NEXT:    [[TOBOOL1:%.*]] = icmp eq i32 [[C]], 0
+; IS__TUNIT_OPM-NEXT:    br i1 [[TOBOOL1]], label [[L1:%.*]], label [[L2:%.*]]
+; IS__TUNIT_OPM:       l1:
+; IS__TUNIT_OPM-NEXT:    [[TOBOOL2:%.*]] = icmp eq i32 [[C]], 1
+; IS__TUNIT_OPM-NEXT:    br i1 [[TOBOOL2]], label [[L3:%.*]], label [[L4:%.*]]
+; IS__TUNIT_OPM:       l2:
+; IS__TUNIT_OPM-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[C]], 2
+; IS__TUNIT_OPM-NEXT:    br i1 [[TOBOOL3]], label [[L3]], label [[L4]]
+; IS__TUNIT_OPM:       l3:
+; IS__TUNIT_OPM-NEXT:    br label [[L5:%.*]]
+; IS__TUNIT_OPM:       l4:
+; IS__TUNIT_OPM-NEXT:    br label [[L5]]
+; IS__TUNIT_OPM:       l5:
+; IS__TUNIT_OPM-NEXT:    [[TOBOOL4:%.*]] = icmp eq i32 [[C]], 4
+; IS__TUNIT_OPM-NEXT:    br i1 [[TOBOOL4]], label [[L6:%.*]], label [[L7:%.*]]
+; IS__TUNIT_OPM:       l6:
+; IS__TUNIT_OPM-NEXT:    store i32 0, i32* [[P]], align 4
+; IS__TUNIT_OPM-NEXT:    br label [[END:%.*]]
+; IS__TUNIT_OPM:       l7:
+; IS__TUNIT_OPM-NEXT:    store i32 1, i32* [[P]], align 4
+; IS__TUNIT_OPM-NEXT:    br label [[END]]
+; IS__TUNIT_OPM:       end:
+; IS__TUNIT_OPM-NEXT:    ret i32 1
+;
+; IS__TUNIT_NPM: Function Attrs: argmemonly nofree nosync nounwind willreturn writeonly
+; IS__TUNIT_NPM-LABEL: define {{[^@]+}}@require_cfg_analysis
+; IS__TUNIT_NPM-SAME: (i32 [[C:%.*]], i32* nocapture nofree nonnull writeonly align 4 dereferenceable(4) [[P:%.*]]) [[ATTR4:#.*]] {
+; IS__TUNIT_NPM-NEXT:    [[TOBOOL1:%.*]] = icmp eq i32 [[C]], 0
+; IS__TUNIT_NPM-NEXT:    br i1 [[TOBOOL1]], label [[L1:%.*]], label [[L2:%.*]]
+; IS__TUNIT_NPM:       l1:
+; IS__TUNIT_NPM-NEXT:    br label [[L4:%.*]]
+; IS__TUNIT_NPM:       l2:
+; IS__TUNIT_NPM-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[C]], 2
+; IS__TUNIT_NPM-NEXT:    br i1 [[TOBOOL3]], label [[L3:%.*]], label [[L4]]
+; IS__TUNIT_NPM:       l3:
+; IS__TUNIT_NPM-NEXT:    br label [[L5:%.*]]
+; IS__TUNIT_NPM:       l4:
+; IS__TUNIT_NPM-NEXT:    br label [[L5]]
+; IS__TUNIT_NPM:       l5:
+; IS__TUNIT_NPM-NEXT:    [[TOBOOL4:%.*]] = icmp eq i32 [[C]], 4
+; IS__TUNIT_NPM-NEXT:    br i1 [[TOBOOL4]], label [[L6:%.*]], label [[L7:%.*]]
+; IS__TUNIT_NPM:       l6:
+; IS__TUNIT_NPM-NEXT:    store i32 0, i32* [[P]], align 4
+; IS__TUNIT_NPM-NEXT:    br label [[END:%.*]]
+; IS__TUNIT_NPM:       l7:
+; IS__TUNIT_NPM-NEXT:    store i32 1, i32* [[P]], align 4
+; IS__TUNIT_NPM-NEXT:    br label [[END]]
+; IS__TUNIT_NPM:       end:
+; IS__TUNIT_NPM-NEXT:    ret i32 1
+;
+; IS__CGSCC_OPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly
+; IS__CGSCC_OPM-LABEL: define {{[^@]+}}@require_cfg_analysis
+; IS__CGSCC_OPM-SAME: (i32 [[C:%.*]], i32* nocapture nofree writeonly [[P:%.*]]) [[ATTR4:#.*]] {
+; IS__CGSCC_OPM-NEXT:    [[TOBOOL1:%.*]] = icmp eq i32 [[C]], 0
+; IS__CGSCC_OPM-NEXT:    br i1 [[TOBOOL1]], label [[L1:%.*]], label [[L2:%.*]]
+; IS__CGSCC_OPM:       l1:
+; IS__CGSCC_OPM-NEXT:    [[TOBOOL2:%.*]] = icmp eq i32 [[C]], 1
+; IS__CGSCC_OPM-NEXT:    br i1 [[TOBOOL2]], label [[L3:%.*]], label [[L4:%.*]]
+; IS__CGSCC_OPM:       l2:
+; IS__CGSCC_OPM-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[C]], 2
+; IS__CGSCC_OPM-NEXT:    br i1 [[TOBOOL3]], label [[L3]], label [[L4]]
+; IS__CGSCC_OPM:       l3:
+; IS__CGSCC_OPM-NEXT:    br label [[L5:%.*]]
+; IS__CGSCC_OPM:       l4:
+; IS__CGSCC_OPM-NEXT:    br label [[L5]]
+; IS__CGSCC_OPM:       l5:
+; IS__CGSCC_OPM-NEXT:    [[TOBOOL4:%.*]] = icmp eq i32 [[C]], 4
+; IS__CGSCC_OPM-NEXT:    br i1 [[TOBOOL4]], label [[L6:%.*]], label [[L7:%.*]]
+; IS__CGSCC_OPM:       l6:
+; IS__CGSCC_OPM-NEXT:    store i32 0, i32* [[P]], align 4
+; IS__CGSCC_OPM-NEXT:    br label [[END:%.*]]
+; IS__CGSCC_OPM:       l7:
+; IS__CGSCC_OPM-NEXT:    store i32 1, i32* [[P]], align 4
+; IS__CGSCC_OPM-NEXT:    br label [[END]]
+; IS__CGSCC_OPM:       end:
+; IS__CGSCC_OPM-NEXT:    ret i32 1
+;
+; IS__CGSCC_NPM: Function Attrs: argmemonly nofree norecurse nosync nounwind willreturn writeonly
+; IS__CGSCC_NPM-LABEL: define {{[^@]+}}@require_cfg_analysis
+; IS__CGSCC_NPM-SAME: (i32 [[C:%.*]], i32* nocapture nofree nonnull writeonly align 4 dereferenceable(4) [[P:%.*]]) [[ATTR4:#.*]] {
+; IS__CGSCC_NPM-NEXT:    [[TOBOOL1:%.*]] = icmp eq i32 [[C]], 0
+; IS__CGSCC_NPM-NEXT:    br i1 [[TOBOOL1]], label [[L1:%.*]], label [[L2:%.*]]
+; IS__CGSCC_NPM:       l1:
+; IS__CGSCC_NPM-NEXT:    br label [[L4:%.*]]
+; IS__CGSCC_NPM:       l2:
+; IS__CGSCC_NPM-NEXT:    [[TOBOOL3:%.*]] = icmp eq i32 [[C]], 2
+; IS__CGSCC_NPM-NEXT:    br i1 [[TOBOOL3]], label [[L3:%.*]], label [[L4]]
+; IS__CGSCC_NPM:       l3:
+; IS__CGSCC_NPM-NEXT:    br label [[L5:%.*]]
+; IS__CGSCC_NPM:       l4:
+; IS__CGSCC_NPM-NEXT:    br label [[L5]]
+; IS__CGSCC_NPM:       l5:
+; IS__CGSCC_NPM-NEXT:    [[TOBOOL4:%.*]] = icmp eq i32 [[C]], 4
+; IS__CGSCC_NPM-NEXT:    br i1 [[TOBOOL4]], label [[L6:%.*]], label [[L7:%.*]]
+; IS__CGSCC_NPM:       l6:
+; IS__CGSCC_NPM-NEXT:    store i32 0, i32* [[P]], align 4
+; IS__CGSCC_NPM-NEXT:    br label [[END:%.*]]
+; IS__CGSCC_NPM:       l7:
+; IS__CGSCC_NPM-NEXT:    store i32 1, i32* [[P]], align 4
+; IS__CGSCC_NPM-NEXT:    br label [[END]]
+; IS__CGSCC_NPM:       end:
+; IS__CGSCC_NPM-NEXT:    ret i32 1
+;
+  %tobool1 = icmp eq i32 %c, 0
+  br i1 %tobool1, label %l1, label %l2
+l1:
+  %tobool2 = icmp eq i32 %c, 1
+  br i1 %tobool2, label %l3, label %l4
+l2:
+  %tobool3 = icmp eq i32 %c, 2
+  br i1 %tobool3, label %l3, label %l4
+l3:
+  br label %l5
+l4:
+  br label %l5
+l5:
+  %tobool4 = icmp eq i32 %c, 4
+  br i1 %tobool4, label %l6, label %l7
+l6:
+  store i32 0, i32* %p
+  br label %end
+l7:
+  store i32 1, i32* %p
+  br label %end
+end:
+  ret i32 1
+}
diff --git a/llvm/test/Transforms/Attributor/nonnull.ll b/llvm/test/Transforms/Attributor/nonnull.ll
index 97526dba7bf1b..23653c80299a6 100644
--- a/llvm/test/Transforms/Attributor/nonnull.ll
+++ b/llvm/test/Transforms/Attributor/nonnull.ll
@@ -1404,24 +1404,40 @@ hd2:
 ; Original from PR43833
 declare void @sink(i32*)
 
-; FIXME: the sink argument should be marked nonnull as in @PR43833_simple.
 define void @PR43833(i32* %0, i32 %1) {
-; CHECK-LABEL: define {{[^@]+}}@PR43833
-; CHECK-SAME: (i32* [[TMP0:%.*]], i32 [[TMP1:%.*]]) {
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp sgt i32 [[TMP1]], 1
-; CHECK-NEXT:    br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP7:%.*]]
-; CHECK:       4:
-; CHECK-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP1]] to i64
-; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[TMP5]]
-; CHECK-NEXT:    br label [[TMP8:%.*]]
-; CHECK:       7:
-; CHECK-NEXT:    ret void
-; CHECK:       8:
-; CHECK-NEXT:    [[TMP9:%.*]] = phi i32 [ 1, [[TMP4]] ], [ [[TMP10:%.*]], [[TMP8]] ]
-; CHECK-NEXT:    tail call void @sink(i32* [[TMP6]])
-; CHECK-NEXT:    [[TMP10]] = add nuw nsw i32 [[TMP9]], 1
-; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[TMP10]], [[TMP1]]
-; CHECK-NEXT:    br i1 [[TMP11]], label [[TMP7]], label [[TMP8]]
+; IS________OPM-LABEL: define {{[^@]+}}@PR43833
+; IS________OPM-SAME: (i32* [[TMP0:%.*]], i32 [[TMP1:%.*]]) {
+; IS________OPM-NEXT:    [[TMP3:%.*]] = icmp sgt i32 [[TMP1]], 1
+; IS________OPM-NEXT:    br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP7:%.*]]
+; IS________OPM:       4:
+; IS________OPM-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP1]] to i64
+; IS________OPM-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[TMP5]]
+; IS________OPM-NEXT:    br label [[TMP8:%.*]]
+; IS________OPM:       7:
+; IS________OPM-NEXT:    ret void
+; IS________OPM:       8:
+; IS________OPM-NEXT:    [[TMP9:%.*]] = phi i32 [ 1, [[TMP4]] ], [ [[TMP10:%.*]], [[TMP8]] ]
+; IS________OPM-NEXT:    tail call void @sink(i32* [[TMP6]])
+; IS________OPM-NEXT:    [[TMP10]] = add nuw nsw i32 [[TMP9]], 1
+; IS________OPM-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[TMP10]], [[TMP1]]
+; IS________OPM-NEXT:    br i1 [[TMP11]], label [[TMP7]], label [[TMP8]]
+;
+; IS________NPM-LABEL: define {{[^@]+}}@PR43833
+; IS________NPM-SAME: (i32* [[TMP0:%.*]], i32 [[TMP1:%.*]]) {
+; IS________NPM-NEXT:    [[TMP3:%.*]] = icmp sgt i32 [[TMP1]], 1
+; IS________NPM-NEXT:    br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP7:%.*]]
+; IS________NPM:       4:
+; IS________NPM-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP1]] to i64
+; IS________NPM-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 [[TMP5]]
+; IS________NPM-NEXT:    br label [[TMP8:%.*]]
+; IS________NPM:       7:
+; IS________NPM-NEXT:    ret void
+; IS________NPM:       8:
+; IS________NPM-NEXT:    [[TMP9:%.*]] = phi i32 [ 1, [[TMP4]] ], [ [[TMP10:%.*]], [[TMP8]] ]
+; IS________NPM-NEXT:    tail call void @sink(i32* nonnull [[TMP6]])
+; IS________NPM-NEXT:    [[TMP10]] = add nuw nsw i32 [[TMP9]], 1
+; IS________NPM-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[TMP10]], [[TMP1]]
+; IS________NPM-NEXT:    br i1 [[TMP11]], label [[TMP7]], label [[TMP8]]
 ;
   %3 = icmp sgt i32 %1, 1
   br i1 %3, label %4, label %7
diff --git a/llvm/test/Transforms/BDCE/vectors-inseltpoison.ll b/llvm/test/Transforms/BDCE/vectors-inseltpoison.ll
new file mode 100644
index 0000000000000..c38562b0096b0
--- /dev/null
+++ b/llvm/test/Transforms/BDCE/vectors-inseltpoison.ll
@@ -0,0 +1,102 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -bdce < %s | FileCheck %s
+
+; BDCE applied to integer vectors.
+
+define <2 x i32> @test_basic(<2 x i32> %a, <2 x i32> %b) {
+; CHECK-LABEL: @test_basic(
+; CHECK-NEXT:    [[A3:%.*]] = and <2 x i32> zeroinitializer, <i32 4, i32 4>
+; CHECK-NEXT:    [[B2:%.*]] = add <2 x i32> [[B:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[B3:%.*]] = and <2 x i32> [[B2]], <i32 8, i32 8>
+; CHECK-NEXT:    [[C:%.*]] = or <2 x i32> [[A3]], [[B3]]
+; CHECK-NEXT:    [[D:%.*]] = ashr <2 x i32> [[C]], <i32 3, i32 3>
+; CHECK-NEXT:    ret <2 x i32> [[D]]
+;
+  %a2 = add <2 x i32> %a, <i32 1, i32 1>
+  %a3 = and <2 x i32> %a2, <i32 4, i32 4>
+  %b2 = add <2 x i32> %b, <i32 1, i32 1>
+  %b3 = and <2 x i32> %b2, <i32 8, i32 8>
+  %c = or <2 x i32> %a3, %b3
+  %d = ashr <2 x i32> %c, <i32 3, i32 3>
+  ret <2 x i32> %d
+}
+
+; Going vector -> scalar
+define i32 @test_extractelement(<2 x i32> %a, <2 x i32> %b) {
+; CHECK-LABEL: @test_extractelement(
+; CHECK-NEXT:    [[A3:%.*]] = and <2 x i32> zeroinitializer, <i32 4, i32 4>
+; CHECK-NEXT:    [[B2:%.*]] = add <2 x i32> [[B:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[B3:%.*]] = and <2 x i32> [[B2]], <i32 8, i32 8>
+; CHECK-NEXT:    [[C:%.*]] = or <2 x i32> [[A3]], [[B3]]
+; CHECK-NEXT:    [[D:%.*]] = extractelement <2 x i32> [[C]], i32 0
+; CHECK-NEXT:    [[E:%.*]] = ashr i32 [[D]], 3
+; CHECK-NEXT:    ret i32 [[E]]
+;
+  %a2 = add <2 x i32> %a, <i32 1, i32 1>
+  %a3 = and <2 x i32> %a2, <i32 4, i32 4>
+  %b2 = add <2 x i32> %b, <i32 1, i32 1>
+  %b3 = and <2 x i32> %b2, <i32 8, i32 8>
+  %c = or <2 x i32> %a3, %b3
+  %d = extractelement <2 x i32> %c, i32 0
+  %e = ashr i32 %d, 3
+  ret i32 %e
+}
+
+; Going scalar -> vector
+define <2 x i32> @test_insertelement(i32 %a, i32 %b) {
+; CHECK-LABEL: @test_insertelement(
+; CHECK-NEXT:    [[X3:%.*]] = and <2 x i32> zeroinitializer, <i32 4, i32 4>
+; CHECK-NEXT:    [[Y:%.*]] = insertelement <2 x i32> poison, i32 [[B:%.*]], i32 0
+; CHECK-NEXT:    [[Y2:%.*]] = insertelement <2 x i32> [[Y]], i32 [[A:%.*]], i32 1
+; CHECK-NEXT:    [[Y3:%.*]] = and <2 x i32> [[Y2]], <i32 8, i32 8>
+; CHECK-NEXT:    [[Z:%.*]] = or <2 x i32> [[X3]], [[Y3]]
+; CHECK-NEXT:    [[U:%.*]] = ashr <2 x i32> [[Z]], <i32 3, i32 3>
+; CHECK-NEXT:    ret <2 x i32> [[U]]
+;
+  %x = insertelement <2 x i32> poison, i32 %a, i32 0
+  %x2 = insertelement <2 x i32> %x, i32 %b, i32 1
+  %x3 = and <2 x i32> %x2, <i32 4, i32 4>
+  %y = insertelement <2 x i32> poison, i32 %b, i32 0
+  %y2 = insertelement <2 x i32> %y, i32 %a, i32 1
+  %y3 = and <2 x i32> %y2, <i32 8, i32 8>
+  %z = or <2 x i32> %x3, %y3
+  %u = ashr <2 x i32> %z, <i32 3, i32 3>
+  ret <2 x i32> %u
+}
+
+; Some non-int vectors and conversions
+define <2 x i32> @test_conversion(<2 x i32> %a) {
+; CHECK-LABEL: @test_conversion(
+; CHECK-NEXT:    [[A2:%.*]] = add <2 x i32> [[A:%.*]], <i32 1, i32 1>
+; CHECK-NEXT:    [[A3:%.*]] = and <2 x i32> [[A2]], <i32 2, i32 2>
+; CHECK-NEXT:    [[X:%.*]] = uitofp <2 x i32> [[A3]] to <2 x double>
+; CHECK-NEXT:    [[Y:%.*]] = fadd <2 x double> [[X]], <double 1.000000e+00, double 1.000000e+00>
+; CHECK-NEXT:    [[Z:%.*]] = fptoui <2 x double> [[Y]] to <2 x i32>
+; CHECK-NEXT:    [[U:%.*]] = ashr <2 x i32> [[Z]], <i32 3, i32 3>
+; CHECK-NEXT:    ret <2 x i32> [[U]]
+;
+  %a2 = add <2 x i32> %a, <i32 1, i32 1>
+  %a3 = and <2 x i32> %a2, <i32 2, i32 2>
+  %x = uitofp <2 x i32> %a3 to <2 x double>
+  %y = fadd <2 x double> %x, <double 1.0, double 1.0>
+  %z = fptoui <2 x double> %y to <2 x i32>
+  %u = ashr <2 x i32> %z, <i32 3, i32 3>
+  ret <2 x i32> %u
+}
+
+; Assumption invalidation (adapted from invalidate-assumptions.ll)
+define <2 x i1> @test_assumption_invalidation(<2 x i1> %b, <2 x i8> %x) {
+; CHECK-LABEL: @test_assumption_invalidation(
+; CHECK-NEXT:    [[LITTLE_NUMBER:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i8>
+; CHECK-NEXT:    [[BIG_NUMBER:%.*]] = shl <2 x i8> zeroinitializer, <i8 1, i8 1>
+; CHECK-NEXT:    [[SUB:%.*]] = sub <2 x i8> [[BIG_NUMBER]], [[LITTLE_NUMBER]]
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <2 x i8> [[SUB]] to <2 x i1>
+; CHECK-NEXT:    ret <2 x i1> [[TRUNC]]
+;
+  %setbit = or <2 x i8> %x, <i8 64, i8 64>
+  %little_number = zext <2 x i1> %b to <2 x i8>
+  %big_number = shl <2 x i8> %setbit, <i8 1, i8 1>
+  %sub = sub nuw <2 x i8> %big_number, %little_number
+  %trunc = trunc <2 x i8> %sub to <2 x i1>
+  ret <2 x i1> %trunc
+}
diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll
new file mode 100644
index 0000000000000..5611ac7068bab
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll
@@ -0,0 +1,113 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -codegenprepare < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+%struct.a = type { i32, i32 }
+@c = external dso_local global %struct.a, align 4
+@glob_array = internal unnamed_addr constant [16 x i32] [i32 1, i32 1, i32 2, i32 3, i32 5, i32 8, i32 13, i32 21, i32 34, i32 55, i32 89, i32 144, i32 233, i32 377, i32 610, i32 987], align 16
+
+define <vscale x 4 x i32> @splat_base(i32* %base, <vscale x 4 x i64> %index, <vscale x 4 x i1> %mask) #0 {
+; CHECK-LABEL: @splat_base(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], <vscale x 4 x i64> [[INDEX:%.*]]
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP1]], i32 4, <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[RES]]
+;
+  %broadcast.splatinsert = insertelement <vscale x 4 x i32*> poison, i32* %base, i32 0
+  %broadcast.splat = shufflevector <vscale x 4 x i32*> %broadcast.splatinsert, <vscale x 4 x i32*> undef, <vscale x 4 x i32> zeroinitializer
+  %gep = getelementptr i32, <vscale x 4 x i32*> %broadcast.splat, <vscale x 4 x i64> %index
+  %res = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %gep, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> undef)
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 4 x i32> @splat_struct(%struct.a* %base, <vscale x 4 x i1> %mask) #0 {
+; CHECK-LABEL: @splat_struct(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr [[STRUCT_A:%.*]], %struct.a* [[BASE:%.*]], i64 0, i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], <vscale x 4 x i64> zeroinitializer
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP2]], i32 4, <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[RES]]
+;
+  %gep = getelementptr %struct.a, %struct.a* %base, <vscale x 4 x i64> zeroinitializer, i32 1
+  %res = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %gep, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> undef)
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 4 x i32> @scalar_index(i32* %base, i64 %index, <vscale x 4 x i1> %mask) #0 {
+; CHECK-LABEL: @scalar_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[INDEX:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], <vscale x 4 x i64> zeroinitializer
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP2]], i32 4, <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[RES]]
+;
+  %broadcast.splatinsert = insertelement <vscale x 4 x i32*> poison, i32* %base, i32 0
+  %broadcast.splat = shufflevector <vscale x 4 x i32*> %broadcast.splatinsert, <vscale x 4 x i32*> undef, <vscale x 4 x i32> zeroinitializer
+  %gep = getelementptr i32, <vscale x 4 x i32*> %broadcast.splat, i64 %index
+  %res = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %gep, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> undef)
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 4 x i32> @splat_index(i32* %base, i64 %index, <vscale x 4 x i1> %mask) #0 {
+; CHECK-LABEL: @splat_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[INDEX:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], <vscale x 4 x i64> zeroinitializer
+; CHECK-NEXT:    [[RES:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP2]], i32 4, <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[RES]]
+;
+  %broadcast.splatinsert = insertelement <vscale x 4 x i64> poison, i64 %index, i32 0
+  %broadcast.splat = shufflevector <vscale x 4 x i64> %broadcast.splatinsert, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %gep = getelementptr i32, i32* %base, <vscale x 4 x i64> %broadcast.splat
+  %res = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %gep, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> undef)
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 4 x i32> @test_global_array(<vscale x 4 x i64> %indxs, <vscale x 4 x i1> %mask) #0 {
+; CHECK-LABEL: @test_global_array(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @glob_array, i64 0, i64 0), <vscale x 4 x i64> [[INDXS:%.*]]
+; CHECK-NEXT:    [[G:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP1]], i32 4, <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[G]]
+;
+  %p = getelementptr inbounds [16 x i32], [16 x i32]* @glob_array, i64 0, <vscale x 4 x i64> %indxs
+  %g = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %p, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> undef)
+  ret <vscale x 4 x i32> %g
+}
+
+define <vscale x 4 x i32> @global_struct_splat(<vscale x 4 x i1> %mask) #0 {
+; CHECK-LABEL: @global_struct_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> shufflevector (<vscale x 4 x i32*> insertelement (<vscale x 4 x i32*> undef, i32* getelementptr inbounds (%struct.a, %struct.a* @c, i64 0, i32 1), i32 0), <vscale x 4 x i32*> undef, <vscale x 4 x i32> zeroinitializer), i32 4, <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP1]]
+;
+  %1 = insertelement <vscale x 4 x %struct.a*> poison, %struct.a* @c, i32 0
+  %2 = shufflevector <vscale x 4 x %struct.a*> %1, <vscale x 4 x %struct.a*> undef, <vscale x 4 x i32> zeroinitializer
+  %3 = getelementptr %struct.a, <vscale x 4 x %struct.a*> %2, <vscale x 4 x i64> zeroinitializer, i32 1
+  %4 = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %3, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> undef)
+  ret <vscale x 4 x i32> %4
+}
+
+define <vscale x 4 x i32> @splat_ptr_gather(i32* %ptr, <vscale x 4 x i1> %mask, <vscale x 4 x i32> %passthru) #0 {
+; CHECK-LABEL: @splat_ptr_gather(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], <vscale x 4 x i64> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP1]], i32 4, <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> [[PASSTHRU:%.*]])
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP2]]
+;
+  %1 = insertelement <vscale x 4 x i32*> poison, i32* %ptr, i32 0
+  %2 = shufflevector <vscale x 4 x i32*> %1, <vscale x 4 x i32*> undef, <vscale x 4 x i32> zeroinitializer
+  %3 = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %2, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> %passthru)
+  ret <vscale x 4 x i32> %3
+}
+
+define void @splat_ptr_scatter(i32* %ptr, <vscale x 4 x i1> %mask, <vscale x 4 x i32> %val) #0 {
+; CHECK-LABEL: @splat_ptr_scatter(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], <vscale x 4 x i64> zeroinitializer
+; CHECK-NEXT:    call void @llvm.masked.scatter.nxv4i32.nxv4p0i32(<vscale x 4 x i32> [[VAL:%.*]], <vscale x 4 x i32*> [[TMP1]], i32 4, <vscale x 4 x i1> [[MASK:%.*]])
+; CHECK-NEXT:    ret void
+;
+  %1 = insertelement <vscale x 4 x i32*> poison, i32* %ptr, i32 0
+  %2 = shufflevector <vscale x 4 x i32*> %1, <vscale x 4 x i32*> undef, <vscale x 4 x i32> zeroinitializer
+  call void @llvm.masked.scatter.nxv4i32.nxv4p0i32(<vscale x 4 x i32> %val, <vscale x 4 x i32*> %2, i32 4, <vscale x 4 x i1> %mask)
+  ret void
+}
+
+declare <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*>, i32, <vscale x 4 x i1>, <vscale x 4 x i32>)
+declare void @llvm.masked.scatter.nxv4i32.nxv4p0i32(<vscale x 4 x i32>, <vscale x 4 x i32*>, i32, <vscale x 4 x i1>)
+
+attributes #0 = { "target-features"="+sve" }
diff --git a/llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info-inseltpoison.ll
new file mode 100644
index 0000000000000..8c198a3c7d607
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/AMDGPU/bypass-slow-div-debug-info-inseltpoison.ll
@@ -0,0 +1,76 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -codegenprepare %s | FileCheck %s
+; Make sure BypassSlowDivision doesn't drop debug info
+
+define i64 @sdiv64(i64 %a, i64 %b) {
+; CHECK-LABEL: @sdiv64(
+; CHECK-NEXT:    [[TMP1:%.*]] = or i64 [[A:%.*]], [[B:%.*]], [[DBG6:!dbg !.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = and i64 [[TMP1]], -4294967296, [[DBG6]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[TMP2]], 0, [[DBG6]]
+; CHECK-NEXT:    br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP9:%.*]], [[DBG6]]
+; CHECK:       4:
+; CHECK-NEXT:    [[TMP5:%.*]] = trunc i64 [[B]] to i32, [[DBG6]]
+; CHECK-NEXT:    [[TMP6:%.*]] = trunc i64 [[A]] to i32, [[DBG6]]
+; CHECK-NEXT:    [[TMP7:%.*]] = udiv i32 [[TMP6]], [[TMP5]], [[DBG6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64, [[DBG6]]
+; CHECK-NEXT:    br label [[TMP11:%.*]], [[DBG6]]
+; CHECK:       9:
+; CHECK-NEXT:    [[TMP10:%.*]] = sdiv i64 [[A]], [[B]], [[DBG6]]
+; CHECK-NEXT:    br label [[TMP11]], [[DBG6]]
+; CHECK:       11:
+; CHECK-NEXT:    [[TMP12:%.*]] = phi i64 [ [[TMP8]], [[TMP4]] ], [ [[TMP10]], [[TMP9]] ], [[DBG6]]
+; CHECK-NEXT:    ret i64 [[TMP12]]
+;
+  %d = sdiv i64 %a, %b, !dbg !6
+  ret i64 %d
+}
+
+; FIXME: The debugloc for the rem parts end up with the dbg of the
+; division.
+define <2 x i64> @sdivrem64(i64 %a, i64 %b) {
+; CHECK-LABEL: @sdivrem64(
+; CHECK-NEXT:    [[TMP1:%.*]] = or i64 [[A:%.*]], [[B:%.*]], [[DBG6]]
+; CHECK-NEXT:    [[TMP2:%.*]] = and i64 [[TMP1]], -4294967296, [[DBG6]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i64 [[TMP2]], 0, [[DBG6]]
+; CHECK-NEXT:    br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP11:%.*]], [[DBG6]]
+; CHECK:       4:
+; CHECK-NEXT:    [[TMP5:%.*]] = trunc i64 [[B]] to i32, [[DBG6]]
+; CHECK-NEXT:    [[TMP6:%.*]] = trunc i64 [[A]] to i32, [[DBG6]]
+; CHECK-NEXT:    [[TMP7:%.*]] = udiv i32 [[TMP6]], [[TMP5]], [[DBG6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = urem i32 [[TMP6]], [[TMP5]], [[DBG6]]
+; CHECK-NEXT:    [[TMP9:%.*]] = zext i32 [[TMP7]] to i64, [[DBG6]]
+; CHECK-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP8]] to i64, [[DBG6]]
+; CHECK-NEXT:    br label [[TMP14:%.*]], [[DBG6]]
+; CHECK:       11:
+; CHECK-NEXT:    [[TMP12:%.*]] = sdiv i64 [[A]], [[B]], [[DBG6]]
+; CHECK-NEXT:    [[TMP13:%.*]] = srem i64 [[A]], [[B]], [[DBG6]]
+; CHECK-NEXT:    br label [[TMP14]], [[DBG6]]
+; CHECK:       14:
+; CHECK-NEXT:    [[TMP15:%.*]] = phi i64 [ [[TMP9]], [[TMP4]] ], [ [[TMP12]], [[TMP11]] ], [[DBG6]]
+; CHECK-NEXT:    [[TMP16:%.*]] = phi i64 [ [[TMP10]], [[TMP4]] ], [ [[TMP13]], [[TMP11]] ], [[DBG6]]
+; CHECK-NEXT:    [[INS0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP15]], i32 0
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <2 x i64> [[INS0]], i64 [[TMP16]], i32 1
+; CHECK-NEXT:    ret <2 x i64> [[INS1]]
+;
+  %d = sdiv i64 %a, %b, !dbg !6
+  %r = srem i64 %a, %b, !dbg !10
+  %ins0 = insertelement <2 x i64> poison, i64 %d, i32 0
+  %ins1 = insertelement <2 x i64> %ins0, i64 %r, i32 1
+  ret <2 x i64> %ins1
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4}
+!llvm.ident = !{!5}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.5 ", isOptimized: false, runtimeVersion: 0, emissionKind: NoDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2)
+!1 = !DIFile(filename: "basic.c", directory: ".")
+!2 = !{}
+!3 = !{i32 2, !"Dwarf Version", i32 4}
+!4 = !{i32 1, !"Debug Info Version", i32 3}
+!5 = !{!"clang version 3.5 "}
+!6 = !DILocation(line: 3, scope: !7)
+!7 = distinct !DILexicalBlock(scope: !8, file: !1, line: 3)
+!8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !9, scopeLine: 1, virtualIndex: 6, flags: DIFlagPrototyped, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !2)
+!9 = !DISubroutineType(types: !2)
+!10 = !DILocation(line: 4, scope: !7)
diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector-inseltpoison.ll
new file mode 100644
index 0000000000000..f43b8f6d540de
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/ARM/sink-add-mul-shufflevector-inseltpoison.ll
@@ -0,0 +1,219 @@
+; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s
+
+define void @sink_add_mul(i32* %s1, i32 %x, i32* %d, i32 %n) {
+; CHECK-LABEL: @sink_add_mul(
+; CHECK:    vector.ph:
+; CHECK-NOT:  [[BROADCAST_SPLATINSERT8:%.*]] = insertelement <4 x i32> undef, i32 [[X:%.*]], i32 0
+; CHECK-NOT:  [[BROADCAST_SPLAT9:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT8]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK:    vector.body:
+; CHECK:      [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK:      [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> undef, <4 x i32> zeroinitializer
+;
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %vector.ph, label %for.cond.cleanup
+
+vector.ph:                                        ; preds = %for.body.preheader
+  %n.vec = and i32 %n, -4
+  %broadcast.splatinsert8 = insertelement <4 x i32> poison, i32 %x, i32 0
+  %broadcast.splat9 = shufflevector <4 x i32> %broadcast.splatinsert8, <4 x i32> undef, <4 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds i32, i32* %s1, i32 %index
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load = load <4 x i32>, <4 x i32>* %1, align 4
+  %2 = mul nsw <4 x i32> %wide.load, %broadcast.splat9
+  %3 = getelementptr inbounds i32, i32* %d, i32 %index
+  %4 = bitcast i32* %3 to <4 x i32>*
+  %wide.load10 = load <4 x i32>, <4 x i32>* %4, align 4
+  %5 = add nsw <4 x i32> %wide.load10, %2
+  %6 = bitcast i32* %3 to <4 x i32>*
+  store <4 x i32> %5, <4 x i32>* %6, align 4
+  %index.next = add i32 %index, 4
+  %7 = icmp eq i32 %index.next, %n.vec
+  br i1 %7, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup:                                 ; preds = %for.body, %middle.block, %entry
+  ret void
+}
+
+define void @sink_add_mul_multiple(i32* %s1, i32* %s2, i32 %x, i32* %d, i32* %d2, i32 %n) {
+; CHECK-LABEL: @sink_add_mul_multiple(
+; CHECK:    vector.ph:
+; CHECK-NOT:  [[BROADCAST_SPLATINSERT8:%.*]] = insertelement <4 x i32> undef, i32 [[X:%.*]], i32 0
+; CHECK-NOT:  [[BROADCAST_SPLAT9:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT8]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK:    vector.body:
+; CHECK:      [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 %x, i32 0
+; CHECK:      [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK:      mul nsw <4 x i32> %wide.load, [[TMP3]]
+; CHECK:      [[TMP2b:%.*]] = insertelement <4 x i32> poison, i32 %x, i32 0
+; CHECK:      [[TMP3b:%.*]] = shufflevector <4 x i32> [[TMP2b]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK:      mul nsw <4 x i32> %wide.load18, [[TMP3b]]
+;
+entry:
+  %cmp13 = icmp sgt i32 %n, 0
+  br i1 %cmp13, label %vector.ph, label %for.cond.cleanup
+
+vector.ph:                                        ; preds = %for.body.preheader
+  %n.vec = and i32 %n, -4
+  %broadcast.splatinsert15 = insertelement <4 x i32> poison, i32 %x, i32 0
+  %broadcast.splat16 = shufflevector <4 x i32> %broadcast.splatinsert15, <4 x i32> undef, <4 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds i32, i32* %s1, i32 %index
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load = load <4 x i32>, <4 x i32>* %1, align 4
+  %2 = mul nsw <4 x i32> %wide.load, %broadcast.splat16
+  %3 = getelementptr inbounds i32, i32* %d, i32 %index
+  %4 = bitcast i32* %3 to <4 x i32>*
+  %wide.load17 = load <4 x i32>, <4 x i32>* %4, align 4
+  %5 = add nsw <4 x i32> %wide.load17, %2
+  %6 = bitcast i32* %3 to <4 x i32>*
+  store <4 x i32> %5, <4 x i32>* %6, align 4
+  %7 = getelementptr inbounds i32, i32* %s2, i32 %index
+  %8 = bitcast i32* %7 to <4 x i32>*
+  %wide.load18 = load <4 x i32>, <4 x i32>* %8, align 4
+  %9 = mul nsw <4 x i32> %wide.load18, %broadcast.splat16
+  %10 = getelementptr inbounds i32, i32* %d2, i32 %index
+  %11 = bitcast i32* %10 to <4 x i32>*
+  %wide.load19 = load <4 x i32>, <4 x i32>* %11, align 4
+  %12 = add nsw <4 x i32> %wide.load19, %9
+  %13 = bitcast i32* %10 to <4 x i32>*
+  store <4 x i32> %12, <4 x i32>* %13, align 4
+  %index.next = add i32 %index, 4
+  %14 = icmp eq i32 %index.next, %n.vec
+  br i1 %14, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup:                                 ; preds = %for.body, %middle.block, %entry
+  ret void
+}
+
+
+define void @sink_add_sub_unsinkable(i32* %s1, i32* %s2, i32 %x, i32* %d, i32* %d2, i32 %n) {
+; CHECK-LABEL: @sink_add_sub_unsinkable(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP13:%.*]] = icmp sgt i32 [[N:%.*]], 0
+; CHECK-NEXT:    br i1 [[CMP13]], label [[VECTOR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N]], -4
+; CHECK-NEXT:    [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BROADCAST_SPLAT16:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT15]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+;
+entry:
+  %cmp13 = icmp sgt i32 %n, 0
+  br i1 %cmp13, label %vector.ph, label %for.cond.cleanup
+
+vector.ph:                                        ; preds = %for.body.preheader
+  %n.vec = and i32 %n, -4
+  %broadcast.splatinsert15 = insertelement <4 x i32> poison, i32 %x, i32 0
+  %broadcast.splat16 = shufflevector <4 x i32> %broadcast.splatinsert15, <4 x i32> undef, <4 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds i32, i32* %s1, i32 %index
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load = load <4 x i32>, <4 x i32>* %1, align 4
+  %2 = mul nsw <4 x i32> %wide.load, %broadcast.splat16
+  %3 = getelementptr inbounds i32, i32* %d, i32 %index
+  %4 = bitcast i32* %3 to <4 x i32>*
+  %wide.load17 = load <4 x i32>, <4 x i32>* %4, align 4
+  %5 = add nsw <4 x i32> %wide.load17, %2
+  %6 = bitcast i32* %3 to <4 x i32>*
+  store <4 x i32> %5, <4 x i32>* %6, align 4
+  %7 = getelementptr inbounds i32, i32* %s2, i32 %index
+  %8 = bitcast i32* %7 to <4 x i32>*
+  %wide.load18 = load <4 x i32>, <4 x i32>* %8, align 4
+  %9 = sub nsw <4 x i32> %broadcast.splat16, %wide.load18
+  %10 = getelementptr inbounds i32, i32* %d2, i32 %index
+  %11 = bitcast i32* %10 to <4 x i32>*
+  %wide.load19 = load <4 x i32>, <4 x i32>* %11, align 4
+  %12 = add nsw <4 x i32> %wide.load19, %9
+  %13 = bitcast i32* %10 to <4 x i32>*
+  store <4 x i32> %12, <4 x i32>* %13, align 4
+  %index.next = add i32 %index, 4
+  %14 = icmp eq i32 %index.next, %n.vec
+  br i1 %14, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup:                                 ; preds = %for.body, %middle.block, %entry
+  ret void
+}
+
+define void @sink_sub(i32* %s1, i32 %x, i32* %d, i32 %n) {
+; CHECK-LABEL: @sink_sub(
+; CHECK:    vector.ph:
+; CHECK-NOT:  [[BROADCAST_SPLATINSERT8:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK-NOT:  [[BROADCAST_SPLAT9:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT8]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK:    vector.body:
+; CHECK:      [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK:      [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> undef, <4 x i32> zeroinitializer
+;
+entry:
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %vector.ph, label %for.cond.cleanup
+
+vector.ph:                                        ; preds = %for.body.preheader
+  %n.vec = and i32 %n, -4
+  %broadcast.splatinsert8 = insertelement <4 x i32> poison, i32 %x, i32 0
+  %broadcast.splat9 = shufflevector <4 x i32> %broadcast.splatinsert8, <4 x i32> undef, <4 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds i32, i32* %s1, i32 %index
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load = load <4 x i32>, <4 x i32>* %1, align 4
+  %2 = sub nsw <4 x i32> %wide.load, %broadcast.splat9
+  %3 = getelementptr inbounds i32, i32* %d, i32 %index
+  %4 = bitcast i32* %3 to <4 x i32>*
+  store <4 x i32> %2, <4 x i32>* %4, align 4
+  %index.next = add i32 %index, 4
+  %5 = icmp eq i32 %index.next, %n.vec
+  br i1 %5, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup:                                 ; preds = %for.body, %middle.block, %entry
+  ret void
+}
+
+define void @sink_sub_unsinkable(i32* %s1, i32 %x, i32* %d, i32 %n) {
+entry:
+; CHECK-LABEL: @sink_sub_unsinkable(
+; CHECK:      vector.ph:
+; CHECK-NEXT:   [[N_VEC:%.*]] = and i32 [[N]], -4
+; CHECK-NEXT:   [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK-NEXT:   [[BROADCAST_SPLAT16:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT15]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:   br label [[VECTOR_BODY:%.*]]
+; CHECK:      vector.body:
+; CHECK-NOT:    [[TMP2:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK-NOT:    [[TMP3:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> undef, <4 x i32> zeroinitializer
+;
+  %cmp6 = icmp sgt i32 %n, 0
+  br i1 %cmp6, label %vector.ph, label %for.cond.cleanup
+
+vector.ph:                                        ; preds = %for.body.preheader
+  %n.vec = and i32 %n, -4
+  %broadcast.splatinsert8 = insertelement <4 x i32> poison, i32 %x, i32 0
+  %broadcast.splat9 = shufflevector <4 x i32> %broadcast.splatinsert8, <4 x i32> undef, <4 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds i32, i32* %s1, i32 %index
+  %1 = bitcast i32* %0 to <4 x i32>*
+  %wide.load = load <4 x i32>, <4 x i32>* %1, align 4
+  %2 = sub nsw <4 x i32> %broadcast.splat9, %wide.load
+  %3 = getelementptr inbounds i32, i32* %d, i32 %index
+  %4 = bitcast i32* %3 to <4 x i32>*
+  store <4 x i32> %2, <4 x i32>* %4, align 4
+  %index.next = add i32 %index, 4
+  %5 = icmp eq i32 %index.next, %n.vec
+  br i1 %5, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup:                                 ; preds = %for.body, %middle.block, %entry
+  ret void
+}
diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll
new file mode 100644
index 0000000000000..7cffedea8a35b
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/ARM/sinkchain-inseltpoison.ll
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp < %s -codegenprepare -S | FileCheck -check-prefix=CHECK %s
+
+; Sink the shufflevector/insertelement pair, followed by the trunc. The sunk instruction end up dead.
+define signext i8 @dead(i16* noalias nocapture readonly %s1, i16 zeroext %x, i8* noalias nocapture %d, i32 %n) {
+; CHECK-LABEL: @dead(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N:%.*]], -8
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = trunc i16 [[X:%.*]] to i8
+; CHECK-NEXT:    [[L6:%.*]] = getelementptr inbounds i16, i16* [[S1:%.*]], i32 [[INDEX]]
+; CHECK-NEXT:    [[L7:%.*]] = bitcast i16* [[L6]] to <8 x i16>*
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i16>, <8 x i16>* [[L7]], align 2
+; CHECK-NEXT:    [[L8:%.*]] = trunc <8 x i16> [[WIDE_LOAD]] to <8 x i8>
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[L9:%.*]] = mul <8 x i8> [[TMP2]], [[L8]]
+; CHECK-NEXT:    [[L13:%.*]] = getelementptr inbounds i8, i8* [[D:%.*]], i32 [[INDEX]]
+; CHECK-NEXT:    [[L14:%.*]] = bitcast i8* [[L13]] to <8 x i8>*
+; CHECK-NEXT:    store <8 x i8> [[L9]], <8 x i8>* [[L14]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 8
+; CHECK-NEXT:    [[L15:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[L15]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i8 0
+;
+entry:
+  %n.vec = and i32 %n, -8
+  %l0 = trunc i16 %x to i8
+  %l1 = insertelement <8 x i8> poison, i8 %l0, i32 0
+  %broadcast.splat26 = shufflevector <8 x i8> %l1, <8 x i8> undef, <8 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+  %l6 = getelementptr inbounds i16, i16* %s1, i32 %index
+  %l7 = bitcast i16* %l6 to <8 x i16>*
+  %wide.load = load <8 x i16>, <8 x i16>* %l7, align 2
+  %l8 = trunc <8 x i16> %wide.load to <8 x i8>
+  %l9 = mul <8 x i8> %broadcast.splat26, %l8
+  %l13 = getelementptr inbounds i8, i8* %d, i32 %index
+  %l14 = bitcast i8* %l13 to <8 x i8>*
+  store <8 x i8> %l9, <8 x i8>* %l14, align 1
+  %index.next = add i32 %index, 8
+  %l15 = icmp eq i32 %index.next, %n.vec
+  br i1 %l15, label %exit, label %vector.body
+
+exit:                                     ; preds = %vector.body
+  ret i8 0
+}
+
+; Same as above, but the shuffle has an extra use meaning it shouldnt be deleted
+define signext i8 @alive(i16* noalias nocapture readonly %s1, i16 zeroext %x, i8* noalias nocapture %d, i32 %n) {
+; CHECK-LABEL: @alive(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[N:%.*]], -8
+; CHECK-NEXT:    [[L0:%.*]] = trunc i16 [[X:%.*]] to i8
+; CHECK-NEXT:    [[L1:%.*]] = insertelement <8 x i8> poison, i8 [[L0]], i32 0
+; CHECK-NEXT:    [[BROADCAST_SPLAT26:%.*]] = shufflevector <8 x i8> [[L1]], <8 x i8> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[L2:%.*]] = sub <8 x i8> zeroinitializer, [[BROADCAST_SPLAT26]]
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = trunc i16 [[X]] to i8
+; CHECK-NEXT:    [[L6:%.*]] = getelementptr inbounds i16, i16* [[S1:%.*]], i32 [[INDEX]]
+; CHECK-NEXT:    [[L7:%.*]] = bitcast i16* [[L6]] to <8 x i16>*
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i16>, <8 x i16>* [[L7]], align 2
+; CHECK-NEXT:    [[L8:%.*]] = trunc <8 x i16> [[WIDE_LOAD]] to <8 x i8>
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <8 x i8> poison, i8 [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i8> [[TMP1]], <8 x i8> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[L9:%.*]] = mul <8 x i8> [[TMP2]], [[L8]]
+; CHECK-NEXT:    [[L13:%.*]] = getelementptr inbounds i8, i8* [[D:%.*]], i32 [[INDEX]]
+; CHECK-NEXT:    [[L14:%.*]] = bitcast i8* [[L13]] to <8 x i8>*
+; CHECK-NEXT:    store <8 x i8> [[L9]], <8 x i8>* [[L14]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 8
+; CHECK-NEXT:    [[L15:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[L15]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i8 0
+;
+entry:
+  %n.vec = and i32 %n, -8
+  %l0 = trunc i16 %x to i8
+  %l1 = insertelement <8 x i8> poison, i8 %l0, i32 0
+  %broadcast.splat26 = shufflevector <8 x i8> %l1, <8 x i8> undef, <8 x i32> zeroinitializer
+  %l2 = sub <8 x i8> zeroinitializer, %broadcast.splat26
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %entry
+  %index = phi i32 [ 0, %entry ], [ %index.next, %vector.body ]
+  %l6 = getelementptr inbounds i16, i16* %s1, i32 %index
+  %l7 = bitcast i16* %l6 to <8 x i16>*
+  %wide.load = load <8 x i16>, <8 x i16>* %l7, align 2
+  %l8 = trunc <8 x i16> %wide.load to <8 x i8>
+  %l9 = mul <8 x i8> %broadcast.splat26, %l8
+  %l13 = getelementptr inbounds i8, i8* %d, i32 %index
+  %l14 = bitcast i8* %l13 to <8 x i8>*
+  store <8 x i8> %l9, <8 x i8>* %l14, align 1
+  %index.next = add i32 %index, 8
+  %l15 = icmp eq i32 %index.next, %n.vec
+  br i1 %l15, label %exit, label %vector.body
+
+exit:                                     ; preds = %vector.body
+  ret i8 0
+}
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
new file mode 100644
index 0000000000000..88967ac1ef7c7
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
@@ -0,0 +1,113 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -codegenprepare < %s | FileCheck %s
+
+target datalayout =
+"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+%struct.a = type { i32, i32 }
+@c = external dso_local global %struct.a, align 4
+@glob_array = internal unnamed_addr constant [16 x i32] [i32 1, i32 1, i32 2, i32 3, i32 5, i32 8, i32 13, i32 21, i32 34, i32 55, i32 89, i32 144, i32 233, i32 377, i32 610, i32 987], align 16
+
+define <4 x i32> @splat_base(i32* %base, <4 x i64> %index) {
+; CHECK-LABEL: @splat_base(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], <4 x i64> [[INDEX:%.*]]
+; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP1]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+; CHECK-NEXT:    ret <4 x i32> [[RES]]
+;
+  %broadcast.splatinsert = insertelement <4 x i32*> poison, i32* %base, i32 0
+  %broadcast.splat = shufflevector <4 x i32*> %broadcast.splatinsert, <4 x i32*> undef, <4 x i32> zeroinitializer
+  %gep = getelementptr i32, <4 x i32*> %broadcast.splat, <4 x i64> %index
+  %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @splat_struct(%struct.a* %base) {
+; CHECK-LABEL: @splat_struct(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr [[STRUCT_A:%.*]], %struct.a* [[BASE:%.*]], i64 0, i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], <4 x i64> zeroinitializer
+; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP2]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+; CHECK-NEXT:    ret <4 x i32> [[RES]]
+;
+  %gep = getelementptr %struct.a, %struct.a* %base, <4 x i64> zeroinitializer, i32 1
+  %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @scalar_index(i32* %base, i64 %index) {
+; CHECK-LABEL: @scalar_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[INDEX:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], <4 x i64> zeroinitializer
+; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP2]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+; CHECK-NEXT:    ret <4 x i32> [[RES]]
+;
+  %broadcast.splatinsert = insertelement <4 x i32*> poison, i32* %base, i32 0
+  %broadcast.splat = shufflevector <4 x i32*> %broadcast.splatinsert, <4 x i32*> undef, <4 x i32> zeroinitializer
+  %gep = getelementptr i32, <4 x i32*> %broadcast.splat, i64 %index
+  %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @splat_index(i32* %base, i64 %index) {
+; CHECK-LABEL: @splat_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[INDEX:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i32, i32* [[TMP1]], <4 x i64> zeroinitializer
+; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP2]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+; CHECK-NEXT:    ret <4 x i32> [[RES]]
+;
+  %broadcast.splatinsert = insertelement <4 x i64> poison, i64 %index, i32 0
+  %broadcast.splat = shufflevector <4 x i64> %broadcast.splatinsert, <4 x i64> undef, <4 x i32> zeroinitializer
+  %gep = getelementptr i32, i32* %base, <4 x i64> %broadcast.splat
+  %res = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %gep, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_global_array(<4 x i64> %indxs) {
+; CHECK-LABEL: @test_global_array(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @glob_array, i64 0, i64 0), <4 x i64> [[INDXS:%.*]]
+; CHECK-NEXT:    [[G:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP1]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+; CHECK-NEXT:    ret <4 x i32> [[G]]
+;
+  %p = getelementptr inbounds [16 x i32], [16 x i32]* @glob_array, i64 0, <4 x i64> %indxs
+  %g = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %p, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+  ret <4 x i32> %g
+}
+
+define <4 x i32> @global_struct_splat() {
+; CHECK-LABEL: @global_struct_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> <i32* getelementptr inbounds (%struct.a, %struct.a* @c, i64 0, i32 1), i32* getelementptr inbounds (%struct.a, %struct.a* @c, i64 0, i32 1), i32* getelementptr inbounds (%struct.a, %struct.a* @c, i64 0, i32 1), i32* getelementptr inbounds (%struct.a, %struct.a* @c, i64 0, i32 1)>, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = insertelement <4 x %struct.a*> poison, %struct.a* @c, i32 0
+  %2 = shufflevector <4 x %struct.a*> %1, <4 x %struct.a*> undef, <4 x i32> zeroinitializer
+  %3 = getelementptr %struct.a, <4 x %struct.a*> %2, <4 x i64> zeroinitializer, i32 1
+  %4 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %3, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
+  ret <4 x i32> %4
+}
+
+define <4 x i32> @splat_ptr_gather(i32* %ptr, <4 x i1> %mask, <4 x i32> %passthru) {
+; CHECK-LABEL: @splat_ptr_gather(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], <4 x i64> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP1]], i32 4, <4 x i1> [[MASK:%.*]], <4 x i32> [[PASSTHRU:%.*]])
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = insertelement <4 x i32*> poison, i32* %ptr, i32 0
+  %2 = shufflevector <4 x i32*> %1, <4 x i32*> undef, <4 x i32> zeroinitializer
+  %3 = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %2, i32 4, <4 x i1> %mask, <4 x i32> %passthru)
+  ret <4 x i32> %3
+}
+
+define void @splat_ptr_scatter(i32* %ptr, <4 x i1> %mask, <4 x i32> %val) {
+; CHECK-LABEL: @splat_ptr_scatter(
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr i32, i32* [[PTR:%.*]], <4 x i64> zeroinitializer
+; CHECK-NEXT:    call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> [[VAL:%.*]], <4 x i32*> [[TMP1]], i32 4, <4 x i1> [[MASK:%.*]])
+; CHECK-NEXT:    ret void
+;
+  %1 = insertelement <4 x i32*> poison, i32* %ptr, i32 0
+  %2 = shufflevector <4 x i32*> %1, <4 x i32*> undef, <4 x i32> zeroinitializer
+  call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %val, <4 x i32*> %2, i32 4, <4 x i1> %mask)
+  ret void
+}
+
+declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
+declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>)
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll
new file mode 100644
index 0000000000000..c208ac6a9fbeb
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-inseltpoison.ll
@@ -0,0 +1,321 @@
+; RUN: opt -S -codegenprepare < %s | FileCheck %s
+
+target datalayout =
+"e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@x = external global [1 x [2 x <4 x float>]]
+
+; Can we sink single addressing mode computation to use?
+define void @test1(i1 %cond, i64* %base) {
+; CHECK-LABEL: @test1
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+entry:
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
+  %casted = bitcast i64* %addr to i32*
+  br i1 %cond, label %if.then, label %fallthrough
+
+if.then:
+  %v = load i32, i32* %casted, align 4
+  br label %fallthrough
+
+fallthrough:
+  ret void
+}
+
+declare void @foo(i32)
+
+; Make sure sinking two copies of addressing mode into different blocks works
+define void @test2(i1 %cond, i64* %base) {
+; CHECK-LABEL: @test2
+entry:
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
+  %casted = bitcast i64* %addr to i32*
+  br i1 %cond, label %if.then, label %fallthrough
+
+if.then:
+; CHECK-LABEL: if.then:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  %v1 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v1)
+  %cmp = icmp eq i32 %v1, 0
+  br i1 %cmp, label %next, label %fallthrough
+
+next:
+; CHECK-LABEL: next:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  %v2 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v2)
+  br label %fallthrough
+
+fallthrough:
+  ret void
+}
+
+; If we have two loads in the same block, only need one copy of addressing mode
+; - instruction selection will duplicate if needed
+define void @test3(i1 %cond, i64* %base) {
+; CHECK-LABEL: @test3
+entry:
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
+  %casted = bitcast i64* %addr to i32*
+  br i1 %cond, label %if.then, label %fallthrough
+
+if.then:
+; CHECK-LABEL: if.then:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  %v1 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v1)
+; CHECK-NOT: getelementptr inbounds i8, {{.+}} 40
+  %v2 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v2)
+  br label %fallthrough
+
+fallthrough:
+  ret void
+}
+
+; Can we still sink addressing mode if there's a cold use of the
+; address itself?  
+define void @test4(i1 %cond, i64* %base) {
+; CHECK-LABEL: @test4
+entry:
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
+  %casted = bitcast i64* %addr to i32*
+  br i1 %cond, label %if.then, label %fallthrough
+
+if.then:
+; CHECK-LABEL: if.then:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  %v1 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v1)
+  %cmp = icmp eq i32 %v1, 0
+  br i1 %cmp, label %rare.1, label %fallthrough
+
+fallthrough:
+  ret void
+
+rare.1:
+; CHECK-LABEL: rare.1:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  call void @slowpath(i32 %v1, i32* %casted) cold
+  br label %fallthrough
+}
+
+; Negative test - don't want to duplicate addressing into hot path
+define void @test5(i1 %cond, i64* %base) {
+; CHECK-LABEL: @test5
+entry:
+; CHECK: %addr = getelementptr inbounds
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
+  %casted = bitcast i64* %addr to i32*
+  br i1 %cond, label %if.then, label %fallthrough
+
+if.then:
+; CHECK-LABEL: if.then:
+; CHECK-NOT: getelementptr inbounds i8, {{.+}} 40
+  %v1 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v1)
+  %cmp = icmp eq i32 %v1, 0
+  br i1 %cmp, label %rare.1, label %fallthrough
+
+fallthrough:
+  ret void
+
+rare.1:
+  call void @slowpath(i32 %v1, i32* %casted) ;; NOT COLD
+  br label %fallthrough
+}
+
+; Negative test - opt for size
+define void @test6(i1 %cond, i64* %base) minsize {
+; CHECK-LABEL: @test6
+entry:
+; CHECK: %addr = getelementptr
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
+  %casted = bitcast i64* %addr to i32*
+  br i1 %cond, label %if.then, label %fallthrough
+
+if.then:
+; CHECK-LABEL: if.then:
+; CHECK-NOT: getelementptr inbounds i8, {{.+}} 40
+  %v1 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v1)
+  %cmp = icmp eq i32 %v1, 0
+  br i1 %cmp, label %rare.1, label %fallthrough
+
+fallthrough:
+  ret void
+
+rare.1:
+  call void @slowpath(i32 %v1, i32* %casted) cold
+  br label %fallthrough
+}
+
+; Negative test - opt for size
+define void @test6_pgso(i1 %cond, i64* %base) !prof !14 {
+; CHECK-LABEL: @test6
+entry:
+; CHECK: %addr = getelementptr
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
+  %casted = bitcast i64* %addr to i32*
+  br i1 %cond, label %if.then, label %fallthrough
+
+if.then:
+; CHECK-LABEL: if.then:
+; CHECK-NOT: getelementptr inbounds i8, {{.+}} 40
+  %v1 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v1)
+  %cmp = icmp eq i32 %v1, 0
+  br i1 %cmp, label %rare.1, label %fallthrough
+
+fallthrough:
+  ret void
+
+rare.1:
+  call void @slowpath(i32 %v1, i32* %casted) cold
+  br label %fallthrough
+}
+
+; Make sure sinking two copies of addressing mode into different blocks works
+; when there are cold paths for each.
+define void @test7(i1 %cond, i64* %base) {
+; CHECK-LABEL: @test7
+entry:
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
+  %casted = bitcast i64* %addr to i32*
+  br i1 %cond, label %if.then, label %fallthrough
+
+if.then:
+; CHECK-LABEL: if.then:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  %v1 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v1)
+  %cmp = icmp eq i32 %v1, 0
+  br i1 %cmp, label %rare.1, label %next
+
+next:
+; CHECK-LABEL: next:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  %v2 = load i32, i32* %casted, align 4
+  call void @foo(i32 %v2)
+  %cmp2 = icmp eq i32 %v2, 0
+  br i1 %cmp2, label %rare.1, label %fallthrough
+
+fallthrough:
+  ret void
+
+rare.1:
+; CHECK-LABEL: rare.1:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  call void @slowpath(i32 %v1, i32* %casted) cold
+  br label %next
+
+rare.2:
+; CHECK-LABEL: rare.2:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  call void @slowpath(i32 %v2, i32* %casted) cold
+  br label %fallthrough
+}
+
+declare void @slowpath(i32, i32*)
+
+; Make sure we don't end up in an infinite loop after we fail to sink.
+; CHECK-LABEL: define void @test8
+; CHECK: %ptr = getelementptr i8, i8* %aFOO_load_ptr2int_2void, i32 undef
+define void @test8() {
+allocas:
+  %aFOO_load = load float*, float** undef
+  %aFOO_load_ptr2int = ptrtoint float* %aFOO_load to i64
+  %aFOO_load_ptr2int_broadcast_init = insertelement <4 x i64> poison, i64 %aFOO_load_ptr2int, i32 0
+  %aFOO_load_ptr2int_2void = inttoptr i64 %aFOO_load_ptr2int to i8*
+  %ptr = getelementptr i8, i8* %aFOO_load_ptr2int_2void, i32 undef
+  br label %load.i145
+
+load.i145:
+  %ptr.i143 = bitcast i8* %ptr to <4 x float>*
+  %valall.i144 = load <4 x float>, <4 x float>* %ptr.i143, align 4
+  %x_offset = getelementptr [1 x [2 x <4 x float>]], [1 x [2 x <4 x float>]]* @x, i32 0, i64 0
+  br label %pl_loop.i.i122
+
+pl_loop.i.i122:
+  br label %pl_loop.i.i122
+}
+
+; Make sure we can sink address computation even
+; if there is a cycle in phi nodes.
+define void @test9(i1 %cond, i64* %base) {
+; CHECK-LABEL: @test9
+entry:
+  %addr = getelementptr inbounds i64, i64* %base, i64 5
+  %casted = bitcast i64* %addr to i32*
+  br label %header
+
+header:
+  %iv = phi i32 [0, %entry], [%iv.inc, %backedge]
+  %casted.loop = phi i32* [%casted, %entry], [%casted.merged, %backedge]
+  br i1 %cond, label %if.then, label %backedge
+
+if.then:
+  call void @foo(i32 %iv)
+  %addr.1 = getelementptr inbounds i64, i64* %base, i64 5
+  %casted.1 = bitcast i64* %addr.1 to i32*
+  br label %backedge
+
+backedge:
+; CHECK-LABEL: backedge:
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+  %casted.merged = phi i32* [%casted.loop, %header], [%casted.1, %if.then]
+  %v = load i32, i32* %casted.merged, align 4
+  call void @foo(i32 %v)
+  %iv.inc = add i32 %iv, 1
+  %cmp = icmp slt i32 %iv.inc, 1000
+  br i1 %cmp, label %header, label %exit
+
+exit:
+  ret void
+}
+
+; Make sure we can eliminate a select when both arguments perform equivalent
+; address computation.
+define void @test10(i1 %cond, i64* %base) {
+; CHECK-LABEL: @test10
+; CHECK: getelementptr inbounds i8, {{.+}} 40
+; CHECK-NOT: select
+entry:
+  %gep1 = getelementptr inbounds i64, i64* %base, i64 5
+  %gep1.casted = bitcast i64* %gep1 to i32*
+  %base.casted = bitcast i64* %base to i32*
+  %gep2 = getelementptr inbounds i32, i32* %base.casted, i64 10
+  %casted.merged = select i1 %cond, i32* %gep1.casted, i32* %gep2
+  %v = load i32, i32* %casted.merged, align 4
+  call void @foo(i32 %v)
+  ret void
+}
+
+; Found by fuzzer, getSExtValue of > 64 bit constant
+define void @i96_mul(i1* %base, i96 %offset) {
+BB:
+  ;; RHS = 0x7FFFFFFFFFFFFFFFFFFFFFFF
+  %B84 = mul i96 %offset, 39614081257132168796771975167
+  %G23 = getelementptr i1, i1* %base, i96 %B84
+  store i1 false, i1* %G23
+  ret void
+}
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"ProfileSummary", !1}
+!1 = !{!2, !3, !4, !5, !6, !7, !8, !9}
+!2 = !{!"ProfileFormat", !"InstrProf"}
+!3 = !{!"TotalCount", i64 10000}
+!4 = !{!"MaxCount", i64 10}
+!5 = !{!"MaxInternalCount", i64 1}
+!6 = !{!"MaxFunctionCount", i64 1000}
+!7 = !{!"NumCounts", i64 3}
+!8 = !{!"NumFunctions", i64 3}
+!9 = !{!"DetailedSummary", !10}
+!10 = !{!11, !12, !13}
+!11 = !{i32 10000, i64 100, i32 1}
+!12 = !{i32 999000, i64 100, i32 1}
+!13 = !{i32 999999, i64 1, i32 2}
+!14 = !{!"function_entry_count", i64 0}
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll
new file mode 100644
index 0000000000000..1d26beeb236ea
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/vec-shift-inseltpoison.ll
@@ -0,0 +1,406 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx -S < %s | FileCheck %s --check-prefixes=ALL,AVX1
+; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx2 -S < %s | FileCheck %s --check-prefixes=ALL,AVX2
+; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx512bw -S < %s | FileCheck %s --check-prefixes=ALL,AVX512BW
+; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx,+xop -S < %s | FileCheck %s --check-prefixes=ALL,XOP
+; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx2,+xop -S < %s | FileCheck %s --check-prefixes=ALL,XOP
+; RUN: opt -codegenprepare -mtriple=x86_64-- -mattr=+avx -S -enable-debugify < %s 2>&1 | FileCheck %s -check-prefix=DEBUG
+
+define <4 x i32> @vector_variable_shift_right_v4i32(<4 x i1> %cond, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
+; AVX1-LABEL: @vector_variable_shift_right_v4i32(
+; AVX1-NEXT:    [[SPLAT1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:    [[SPLAT2:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:    [[SEL:%.*]] = select <4 x i1> [[COND:%.*]], <4 x i32> [[SPLAT1]], <4 x i32> [[SPLAT2]]
+; AVX1-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SPLAT1]]
+; AVX1-NEXT:    [[TMP2:%.*]] = lshr <4 x i32> [[Z]], [[SPLAT2]]
+; AVX1-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[COND]], <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
+; AVX1-NEXT:    ret <4 x i32> [[TMP3]]
+;
+; AVX2-LABEL: @vector_variable_shift_right_v4i32(
+; AVX2-NEXT:    [[SPLAT1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:    [[SPLAT2:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:    [[SEL:%.*]] = select <4 x i1> [[COND:%.*]], <4 x i32> [[SPLAT1]], <4 x i32> [[SPLAT2]]
+; AVX2-NEXT:    [[SH:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SEL]]
+; AVX2-NEXT:    ret <4 x i32> [[SH]]
+;
+; AVX512BW-LABEL: @vector_variable_shift_right_v4i32(
+; AVX512BW-NEXT:    [[SPLAT1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX512BW-NEXT:    [[SPLAT2:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX512BW-NEXT:    [[SEL:%.*]] = select <4 x i1> [[COND:%.*]], <4 x i32> [[SPLAT1]], <4 x i32> [[SPLAT2]]
+; AVX512BW-NEXT:    [[SH:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SEL]]
+; AVX512BW-NEXT:    ret <4 x i32> [[SH]]
+;
+; XOP-LABEL: @vector_variable_shift_right_v4i32(
+; XOP-NEXT:    [[SPLAT1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; XOP-NEXT:    [[SPLAT2:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; XOP-NEXT:    [[SEL:%.*]] = select <4 x i1> [[COND:%.*]], <4 x i32> [[SPLAT1]], <4 x i32> [[SPLAT2]]
+; XOP-NEXT:    [[SH:%.*]] = lshr <4 x i32> [[Z:%.*]], [[SEL]]
+; XOP-NEXT:    ret <4 x i32> [[SH]]
+;
+  %splat1 = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> zeroinitializer
+  %splat2 = shufflevector <4 x i32> %y, <4 x i32> undef, <4 x i32> zeroinitializer
+  %sel = select <4 x i1> %cond, <4 x i32> %splat1, <4 x i32> %splat2
+  %sh = lshr <4 x i32> %z, %sel
+  ret <4 x i32> %sh
+}
+
+define <16 x i16> @vector_variable_shift_right_v16i16(<16 x i1> %cond, <16 x i16> %x, <16 x i16> %y, <16 x i16> %z) {
+; AVX1-LABEL: @vector_variable_shift_right_v16i16(
+; AVX1-NEXT:    [[SPLAT1:%.*]] = shufflevector <16 x i16> [[X:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:    [[SPLAT2:%.*]] = shufflevector <16 x i16> [[Y:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX1-NEXT:    [[SEL:%.*]] = select <16 x i1> [[COND:%.*]], <16 x i16> [[SPLAT1]], <16 x i16> [[SPLAT2]]
+; AVX1-NEXT:    [[TMP1:%.*]] = lshr <16 x i16> [[Z:%.*]], [[SPLAT1]]
+; AVX1-NEXT:    [[TMP2:%.*]] = lshr <16 x i16> [[Z]], [[SPLAT2]]
+; AVX1-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[COND]], <16 x i16> [[TMP1]], <16 x i16> [[TMP2]]
+; AVX1-NEXT:    ret <16 x i16> [[TMP3]]
+;
+; AVX2-LABEL: @vector_variable_shift_right_v16i16(
+; AVX2-NEXT:    [[SPLAT1:%.*]] = shufflevector <16 x i16> [[X:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:    [[SPLAT2:%.*]] = shufflevector <16 x i16> [[Y:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX2-NEXT:    [[SEL:%.*]] = select <16 x i1> [[COND:%.*]], <16 x i16> [[SPLAT1]], <16 x i16> [[SPLAT2]]
+; AVX2-NEXT:    [[TMP1:%.*]] = lshr <16 x i16> [[Z:%.*]], [[SPLAT1]]
+; AVX2-NEXT:    [[TMP2:%.*]] = lshr <16 x i16> [[Z]], [[SPLAT2]]
+; AVX2-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[COND]], <16 x i16> [[TMP1]], <16 x i16> [[TMP2]]
+; AVX2-NEXT:    ret <16 x i16> [[TMP3]]
+;
+; AVX512BW-LABEL: @vector_variable_shift_right_v16i16(
+; AVX512BW-NEXT:    [[SPLAT1:%.*]] = shufflevector <16 x i16> [[X:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX512BW-NEXT:    [[SPLAT2:%.*]] = shufflevector <16 x i16> [[Y:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; AVX512BW-NEXT:    [[SEL:%.*]] = select <16 x i1> [[COND:%.*]], <16 x i16> [[SPLAT1]], <16 x i16> [[SPLAT2]]
+; AVX512BW-NEXT:    [[SH:%.*]] = lshr <16 x i16> [[Z:%.*]], [[SEL]]
+; AVX512BW-NEXT:    ret <16 x i16> [[SH]]
+;
+; XOP-LABEL: @vector_variable_shift_right_v16i16(
+; XOP-NEXT:    [[SPLAT1:%.*]] = shufflevector <16 x i16> [[X:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; XOP-NEXT:    [[SPLAT2:%.*]] = shufflevector <16 x i16> [[Y:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; XOP-NEXT:    [[SEL:%.*]] = select <16 x i1> [[COND:%.*]], <16 x i16> [[SPLAT1]], <16 x i16> [[SPLAT2]]
+; XOP-NEXT:    [[SH:%.*]] = lshr <16 x i16> [[Z:%.*]], [[SEL]]
+; XOP-NEXT:    ret <16 x i16> [[SH]]
+;
+  %splat1 = shufflevector <16 x i16> %x, <16 x i16> undef, <16 x i32> zeroinitializer
+  %splat2 = shufflevector <16 x i16> %y, <16 x i16> undef, <16 x i32> zeroinitializer
+  %sel = select <16 x i1> %cond, <16 x i16> %splat1, <16 x i16> %splat2
+  %sh = lshr <16 x i16> %z, %sel
+  ret <16 x i16> %sh
+}
+
+define <32 x i8> @vector_variable_shift_right_v32i8(<32 x i1> %cond, <32 x i8> %x, <32 x i8> %y, <32 x i8> %z) {
+; ALL-LABEL: @vector_variable_shift_right_v32i8(
+; ALL-NEXT:    [[SPLAT1:%.*]] = shufflevector <32 x i8> [[X:%.*]], <32 x i8> undef, <32 x i32> zeroinitializer
+; ALL-NEXT:    [[SPLAT2:%.*]] = shufflevector <32 x i8> [[Y:%.*]], <32 x i8> undef, <32 x i32> zeroinitializer
+; ALL-NEXT:    [[SEL:%.*]] = select <32 x i1> [[COND:%.*]], <32 x i8> [[SPLAT1]], <32 x i8> [[SPLAT2]]
+; ALL-NEXT:    [[SH:%.*]] = lshr <32 x i8> [[Z:%.*]], [[SEL]]
+; ALL-NEXT:    ret <32 x i8> [[SH]]
+;
+  %splat1 = shufflevector <32 x i8> %x, <32 x i8> undef, <32 x i32> zeroinitializer
+  %splat2 = shufflevector <32 x i8> %y, <32 x i8> undef, <32 x i32> zeroinitializer
+  %sel = select <32 x i1> %cond, <32 x i8> %splat1, <32 x i8> %splat2
+  %sh = lshr <32 x i8> %z, %sel
+  ret <32 x i8> %sh
+}
+
+; PR37428 - https://bugs.llvm.org/show_bug.cgi?id=37428
+
+define void @vector_variable_shift_left_loop(i32* nocapture %arr, i8* nocapture readonly %control, i32 %count, i32 %amt0, i32 %amt1, i32 %x) {
+; AVX1-LABEL: @vector_variable_shift_left_loop(
+; AVX1-NEXT:  entry:
+; AVX1-NEXT:    [[CMP16:%.*]] = icmp sgt i32 [[COUNT:%.*]], 0
+; AVX1-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[COUNT]] to i64
+; AVX1-NEXT:    br i1 [[CMP16]], label [[VECTOR_PH:%.*]], label [[EXIT:%.*]]
+; AVX1:       vector.ph:
+; AVX1-NEXT:    [[N_VEC:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 4294967292
+; AVX1-NEXT:    [[SPLATINSERT18:%.*]] = insertelement <4 x i32> poison, i32 [[AMT0:%.*]], i32 0
+; AVX1-NEXT:    [[SPLAT1:%.*]] = shufflevector <4 x i32> [[SPLATINSERT18]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:    [[SPLATINSERT20:%.*]] = insertelement <4 x i32> poison, i32 [[AMT1:%.*]], i32 0
+; AVX1-NEXT:    [[SPLAT2:%.*]] = shufflevector <4 x i32> [[SPLATINSERT20]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:    [[SPLATINSERT22:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; AVX1-NEXT:    [[SPLAT3:%.*]] = shufflevector <4 x i32> [[SPLATINSERT22]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:    br label [[VECTOR_BODY:%.*]]
+; AVX1:       vector.body:
+; AVX1-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; AVX1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[CONTROL:%.*]], i64 [[INDEX]]
+; AVX1-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i8>*
+; AVX1-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; AVX1-NEXT:    [[TMP2:%.*]] = icmp eq <4 x i8> [[WIDE_LOAD]], zeroinitializer
+; AVX1-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[SPLAT1]], <4 x i32> [[SPLAT2]]
+; AVX1-NEXT:    [[TMP4:%.*]] = shufflevector <4 x i32> [[SPLATINSERT18]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:    [[TMP5:%.*]] = shl <4 x i32> [[SPLAT3]], [[TMP4]]
+; AVX1-NEXT:    [[TMP6:%.*]] = shufflevector <4 x i32> [[SPLATINSERT20]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX1-NEXT:    [[TMP7:%.*]] = shl <4 x i32> [[SPLAT3]], [[TMP6]]
+; AVX1-NEXT:    [[TMP8:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[TMP5]], <4 x i32> [[TMP7]]
+; AVX1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; AVX1-NEXT:    [[TMP10:%.*]] = bitcast i32* [[TMP9]] to <4 x i32>*
+; AVX1-NEXT:    store <4 x i32> [[TMP8]], <4 x i32>* [[TMP10]], align 4
+; AVX1-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 4
+; AVX1-NEXT:    [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; AVX1-NEXT:    br i1 [[TMP11]], label [[EXIT]], label [[VECTOR_BODY]]
+; AVX1:       exit:
+; AVX1-NEXT:    ret void
+;
+; AVX2-LABEL: @vector_variable_shift_left_loop(
+; AVX2-NEXT:  entry:
+; AVX2-NEXT:    [[CMP16:%.*]] = icmp sgt i32 [[COUNT:%.*]], 0
+; AVX2-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[COUNT]] to i64
+; AVX2-NEXT:    br i1 [[CMP16]], label [[VECTOR_PH:%.*]], label [[EXIT:%.*]]
+; AVX2:       vector.ph:
+; AVX2-NEXT:    [[N_VEC:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 4294967292
+; AVX2-NEXT:    [[SPLATINSERT18:%.*]] = insertelement <4 x i32> poison, i32 [[AMT0:%.*]], i32 0
+; AVX2-NEXT:    [[SPLAT1:%.*]] = shufflevector <4 x i32> [[SPLATINSERT18]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:    [[SPLATINSERT20:%.*]] = insertelement <4 x i32> poison, i32 [[AMT1:%.*]], i32 0
+; AVX2-NEXT:    [[SPLAT2:%.*]] = shufflevector <4 x i32> [[SPLATINSERT20]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:    [[SPLATINSERT22:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; AVX2-NEXT:    [[SPLAT3:%.*]] = shufflevector <4 x i32> [[SPLATINSERT22]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:    br label [[VECTOR_BODY:%.*]]
+; AVX2:       vector.body:
+; AVX2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; AVX2-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[CONTROL:%.*]], i64 [[INDEX]]
+; AVX2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i8>*
+; AVX2-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; AVX2-NEXT:    [[TMP2:%.*]] = icmp eq <4 x i8> [[WIDE_LOAD]], zeroinitializer
+; AVX2-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[SPLAT1]], <4 x i32> [[SPLAT2]]
+; AVX2-NEXT:    [[TMP4:%.*]] = shl <4 x i32> [[SPLAT3]], [[TMP3]]
+; AVX2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; AVX2-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP5]] to <4 x i32>*
+; AVX2-NEXT:    store <4 x i32> [[TMP4]], <4 x i32>* [[TMP6]], align 4
+; AVX2-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 4
+; AVX2-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; AVX2-NEXT:    br i1 [[TMP7]], label [[EXIT]], label [[VECTOR_BODY]]
+; AVX2:       exit:
+; AVX2-NEXT:    ret void
+;
+; AVX512BW-LABEL: @vector_variable_shift_left_loop(
+; AVX512BW-NEXT:  entry:
+; AVX512BW-NEXT:    [[CMP16:%.*]] = icmp sgt i32 [[COUNT:%.*]], 0
+; AVX512BW-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[COUNT]] to i64
+; AVX512BW-NEXT:    br i1 [[CMP16]], label [[VECTOR_PH:%.*]], label [[EXIT:%.*]]
+; AVX512BW:       vector.ph:
+; AVX512BW-NEXT:    [[N_VEC:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 4294967292
+; AVX512BW-NEXT:    [[SPLATINSERT18:%.*]] = insertelement <4 x i32> poison, i32 [[AMT0:%.*]], i32 0
+; AVX512BW-NEXT:    [[SPLAT1:%.*]] = shufflevector <4 x i32> [[SPLATINSERT18]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX512BW-NEXT:    [[SPLATINSERT20:%.*]] = insertelement <4 x i32> poison, i32 [[AMT1:%.*]], i32 0
+; AVX512BW-NEXT:    [[SPLAT2:%.*]] = shufflevector <4 x i32> [[SPLATINSERT20]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX512BW-NEXT:    [[SPLATINSERT22:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; AVX512BW-NEXT:    [[SPLAT3:%.*]] = shufflevector <4 x i32> [[SPLATINSERT22]], <4 x i32> undef, <4 x i32> zeroinitializer
+; AVX512BW-NEXT:    br label [[VECTOR_BODY:%.*]]
+; AVX512BW:       vector.body:
+; AVX512BW-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; AVX512BW-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[CONTROL:%.*]], i64 [[INDEX]]
+; AVX512BW-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i8>*
+; AVX512BW-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; AVX512BW-NEXT:    [[TMP2:%.*]] = icmp eq <4 x i8> [[WIDE_LOAD]], zeroinitializer
+; AVX512BW-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[SPLAT1]], <4 x i32> [[SPLAT2]]
+; AVX512BW-NEXT:    [[TMP4:%.*]] = shl <4 x i32> [[SPLAT3]], [[TMP3]]
+; AVX512BW-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; AVX512BW-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP5]] to <4 x i32>*
+; AVX512BW-NEXT:    store <4 x i32> [[TMP4]], <4 x i32>* [[TMP6]], align 4
+; AVX512BW-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 4
+; AVX512BW-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; AVX512BW-NEXT:    br i1 [[TMP7]], label [[EXIT]], label [[VECTOR_BODY]]
+; AVX512BW:       exit:
+; AVX512BW-NEXT:    ret void
+;
+; XOP-LABEL: @vector_variable_shift_left_loop(
+; XOP-NEXT:  entry:
+; XOP-NEXT:    [[CMP16:%.*]] = icmp sgt i32 [[COUNT:%.*]], 0
+; XOP-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[COUNT]] to i64
+; XOP-NEXT:    br i1 [[CMP16]], label [[VECTOR_PH:%.*]], label [[EXIT:%.*]]
+; XOP:       vector.ph:
+; XOP-NEXT:    [[N_VEC:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 4294967292
+; XOP-NEXT:    [[SPLATINSERT18:%.*]] = insertelement <4 x i32> poison, i32 [[AMT0:%.*]], i32 0
+; XOP-NEXT:    [[SPLAT1:%.*]] = shufflevector <4 x i32> [[SPLATINSERT18]], <4 x i32> undef, <4 x i32> zeroinitializer
+; XOP-NEXT:    [[SPLATINSERT20:%.*]] = insertelement <4 x i32> poison, i32 [[AMT1:%.*]], i32 0
+; XOP-NEXT:    [[SPLAT2:%.*]] = shufflevector <4 x i32> [[SPLATINSERT20]], <4 x i32> undef, <4 x i32> zeroinitializer
+; XOP-NEXT:    [[SPLATINSERT22:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; XOP-NEXT:    [[SPLAT3:%.*]] = shufflevector <4 x i32> [[SPLATINSERT22]], <4 x i32> undef, <4 x i32> zeroinitializer
+; XOP-NEXT:    br label [[VECTOR_BODY:%.*]]
+; XOP:       vector.body:
+; XOP-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; XOP-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i8, i8* [[CONTROL:%.*]], i64 [[INDEX]]
+; XOP-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to <4 x i8>*
+; XOP-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; XOP-NEXT:    [[TMP2:%.*]] = icmp eq <4 x i8> [[WIDE_LOAD]], zeroinitializer
+; XOP-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> [[SPLAT1]], <4 x i32> [[SPLAT2]]
+; XOP-NEXT:    [[TMP4:%.*]] = shl <4 x i32> [[SPLAT3]], [[TMP3]]
+; XOP-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; XOP-NEXT:    [[TMP6:%.*]] = bitcast i32* [[TMP5]] to <4 x i32>*
+; XOP-NEXT:    store <4 x i32> [[TMP4]], <4 x i32>* [[TMP6]], align 4
+; XOP-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 4
+; XOP-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; XOP-NEXT:    br i1 [[TMP7]], label [[EXIT]], label [[VECTOR_BODY]]
+; XOP:       exit:
+; XOP-NEXT:    ret void
+;
+entry:
+  %cmp16 = icmp sgt i32 %count, 0
+  %wide.trip.count = zext i32 %count to i64
+  br i1 %cmp16, label %vector.ph, label %exit
+
+vector.ph:
+  %n.vec = and i64 %wide.trip.count, 4294967292
+  %splatinsert18 = insertelement <4 x i32> poison, i32 %amt0, i32 0
+  %splat1 = shufflevector <4 x i32> %splatinsert18, <4 x i32> undef, <4 x i32> zeroinitializer
+  %splatinsert20 = insertelement <4 x i32> poison, i32 %amt1, i32 0
+  %splat2 = shufflevector <4 x i32> %splatinsert20, <4 x i32> undef, <4 x i32> zeroinitializer
+  %splatinsert22 = insertelement <4 x i32> poison, i32 %x, i32 0
+  %splat3 = shufflevector <4 x i32> %splatinsert22, <4 x i32> undef, <4 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:
+  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %0 = getelementptr inbounds i8, i8* %control, i64 %index
+  %1 = bitcast i8* %0 to <4 x i8>*
+  %wide.load = load <4 x i8>, <4 x i8>* %1, align 1
+  %2 = icmp eq <4 x i8> %wide.load, zeroinitializer
+  %3 = select <4 x i1> %2, <4 x i32> %splat1, <4 x i32> %splat2
+  %4 = shl <4 x i32> %splat3, %3
+  %5 = getelementptr inbounds i32, i32* %arr, i64 %index
+  %6 = bitcast i32* %5 to <4 x i32>*
+  store <4 x i32> %4, <4 x i32>* %6, align 4
+  %index.next = add i64 %index, 4
+  %7 = icmp eq i64 %index.next, %n.vec
+  br i1 %7, label %exit, label %vector.body
+
+exit:
+  ret void
+}
+
+; PR37426 - https://bugs.llvm.org/show_bug.cgi?id=37426
+; If we don't have real vector shift instructions (AVX1), convert the funnel
+; shift into 2 funnel shifts and sink the splat shuffles into the loop.
+
+define void @fancierRotate2(i32* %arr, i8* %control, i32 %rot0, i32 %rot1) {
+; AVX1-LABEL: @fancierRotate2(
+; AVX1-NEXT:  entry:
+; AVX1-NEXT:    [[I0:%.*]] = insertelement <8 x i32> poison, i32 [[ROT0:%.*]], i32 0
+; AVX1-NEXT:    [[S0:%.*]] = shufflevector <8 x i32> [[I0]], <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:    [[I1:%.*]] = insertelement <8 x i32> poison, i32 [[ROT1:%.*]], i32 0
+; AVX1-NEXT:    [[S1:%.*]] = shufflevector <8 x i32> [[I1]], <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:    br label [[LOOP:%.*]]
+; AVX1:       loop:
+; AVX1-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ]
+; AVX1-NEXT:    [[T0:%.*]] = getelementptr inbounds i8, i8* [[CONTROL:%.*]], i64 [[INDEX]]
+; AVX1-NEXT:    [[T1:%.*]] = bitcast i8* [[T0]] to <8 x i8>*
+; AVX1-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i8>, <8 x i8>* [[T1]], align 1
+; AVX1-NEXT:    [[T2:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer
+; AVX1-NEXT:    [[SHAMT:%.*]] = select <8 x i1> [[T2]], <8 x i32> [[S0]], <8 x i32> [[S1]]
+; AVX1-NEXT:    [[T4:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; AVX1-NEXT:    [[T5:%.*]] = bitcast i32* [[T4]] to <8 x i32>*
+; AVX1-NEXT:    [[WIDE_LOAD21:%.*]] = load <8 x i32>, <8 x i32>* [[T5]], align 4
+; AVX1-NEXT:    [[TMP0:%.*]] = shufflevector <8 x i32> [[I0]], <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:    [[TMP1:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD21]], <8 x i32> [[WIDE_LOAD21]], <8 x i32> [[TMP0]])
+; AVX1-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i32> [[I1]], <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX1-NEXT:    [[TMP3:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD21]], <8 x i32> [[WIDE_LOAD21]], <8 x i32> [[TMP2]])
+; AVX1-NEXT:    [[TMP4:%.*]] = select <8 x i1> [[T2]], <8 x i32> [[TMP1]], <8 x i32> [[TMP3]]
+; AVX1-NEXT:    store <8 x i32> [[TMP4]], <8 x i32>* [[T5]], align 4
+; AVX1-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 8
+; AVX1-NEXT:    [[T7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; AVX1-NEXT:    br i1 [[T7]], label [[EXIT:%.*]], label [[LOOP]]
+; AVX1:       exit:
+; AVX1-NEXT:    ret void
+;
+; AVX2-LABEL: @fancierRotate2(
+; AVX2-NEXT:  entry:
+; AVX2-NEXT:    [[I0:%.*]] = insertelement <8 x i32> poison, i32 [[ROT0:%.*]], i32 0
+; AVX2-NEXT:    [[S0:%.*]] = shufflevector <8 x i32> [[I0]], <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX2-NEXT:    [[I1:%.*]] = insertelement <8 x i32> poison, i32 [[ROT1:%.*]], i32 0
+; AVX2-NEXT:    [[S1:%.*]] = shufflevector <8 x i32> [[I1]], <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX2-NEXT:    br label [[LOOP:%.*]]
+; AVX2:       loop:
+; AVX2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ]
+; AVX2-NEXT:    [[T0:%.*]] = getelementptr inbounds i8, i8* [[CONTROL:%.*]], i64 [[INDEX]]
+; AVX2-NEXT:    [[T1:%.*]] = bitcast i8* [[T0]] to <8 x i8>*
+; AVX2-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i8>, <8 x i8>* [[T1]], align 1
+; AVX2-NEXT:    [[T2:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer
+; AVX2-NEXT:    [[SHAMT:%.*]] = select <8 x i1> [[T2]], <8 x i32> [[S0]], <8 x i32> [[S1]]
+; AVX2-NEXT:    [[T4:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; AVX2-NEXT:    [[T5:%.*]] = bitcast i32* [[T4]] to <8 x i32>*
+; AVX2-NEXT:    [[WIDE_LOAD21:%.*]] = load <8 x i32>, <8 x i32>* [[T5]], align 4
+; AVX2-NEXT:    [[ROT:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD21]], <8 x i32> [[WIDE_LOAD21]], <8 x i32> [[SHAMT]])
+; AVX2-NEXT:    store <8 x i32> [[ROT]], <8 x i32>* [[T5]], align 4
+; AVX2-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 8
+; AVX2-NEXT:    [[T7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; AVX2-NEXT:    br i1 [[T7]], label [[EXIT:%.*]], label [[LOOP]]
+; AVX2:       exit:
+; AVX2-NEXT:    ret void
+;
+; AVX512BW-LABEL: @fancierRotate2(
+; AVX512BW-NEXT:  entry:
+; AVX512BW-NEXT:    [[I0:%.*]] = insertelement <8 x i32> poison, i32 [[ROT0:%.*]], i32 0
+; AVX512BW-NEXT:    [[S0:%.*]] = shufflevector <8 x i32> [[I0]], <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX512BW-NEXT:    [[I1:%.*]] = insertelement <8 x i32> poison, i32 [[ROT1:%.*]], i32 0
+; AVX512BW-NEXT:    [[S1:%.*]] = shufflevector <8 x i32> [[I1]], <8 x i32> undef, <8 x i32> zeroinitializer
+; AVX512BW-NEXT:    br label [[LOOP:%.*]]
+; AVX512BW:       loop:
+; AVX512BW-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ]
+; AVX512BW-NEXT:    [[T0:%.*]] = getelementptr inbounds i8, i8* [[CONTROL:%.*]], i64 [[INDEX]]
+; AVX512BW-NEXT:    [[T1:%.*]] = bitcast i8* [[T0]] to <8 x i8>*
+; AVX512BW-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i8>, <8 x i8>* [[T1]], align 1
+; AVX512BW-NEXT:    [[T2:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer
+; AVX512BW-NEXT:    [[SHAMT:%.*]] = select <8 x i1> [[T2]], <8 x i32> [[S0]], <8 x i32> [[S1]]
+; AVX512BW-NEXT:    [[T4:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; AVX512BW-NEXT:    [[T5:%.*]] = bitcast i32* [[T4]] to <8 x i32>*
+; AVX512BW-NEXT:    [[WIDE_LOAD21:%.*]] = load <8 x i32>, <8 x i32>* [[T5]], align 4
+; AVX512BW-NEXT:    [[ROT:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD21]], <8 x i32> [[WIDE_LOAD21]], <8 x i32> [[SHAMT]])
+; AVX512BW-NEXT:    store <8 x i32> [[ROT]], <8 x i32>* [[T5]], align 4
+; AVX512BW-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 8
+; AVX512BW-NEXT:    [[T7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; AVX512BW-NEXT:    br i1 [[T7]], label [[EXIT:%.*]], label [[LOOP]]
+; AVX512BW:       exit:
+; AVX512BW-NEXT:    ret void
+;
+; XOP-LABEL: @fancierRotate2(
+; XOP-NEXT:  entry:
+; XOP-NEXT:    [[I0:%.*]] = insertelement <8 x i32> poison, i32 [[ROT0:%.*]], i32 0
+; XOP-NEXT:    [[S0:%.*]] = shufflevector <8 x i32> [[I0]], <8 x i32> undef, <8 x i32> zeroinitializer
+; XOP-NEXT:    [[I1:%.*]] = insertelement <8 x i32> poison, i32 [[ROT1:%.*]], i32 0
+; XOP-NEXT:    [[S1:%.*]] = shufflevector <8 x i32> [[I1]], <8 x i32> undef, <8 x i32> zeroinitializer
+; XOP-NEXT:    br label [[LOOP:%.*]]
+; XOP:       loop:
+; XOP-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ]
+; XOP-NEXT:    [[T0:%.*]] = getelementptr inbounds i8, i8* [[CONTROL:%.*]], i64 [[INDEX]]
+; XOP-NEXT:    [[T1:%.*]] = bitcast i8* [[T0]] to <8 x i8>*
+; XOP-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i8>, <8 x i8>* [[T1]], align 1
+; XOP-NEXT:    [[T2:%.*]] = icmp eq <8 x i8> [[WIDE_LOAD]], zeroinitializer
+; XOP-NEXT:    [[SHAMT:%.*]] = select <8 x i1> [[T2]], <8 x i32> [[S0]], <8 x i32> [[S1]]
+; XOP-NEXT:    [[T4:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; XOP-NEXT:    [[T5:%.*]] = bitcast i32* [[T4]] to <8 x i32>*
+; XOP-NEXT:    [[WIDE_LOAD21:%.*]] = load <8 x i32>, <8 x i32>* [[T5]], align 4
+; XOP-NEXT:    [[ROT:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD21]], <8 x i32> [[WIDE_LOAD21]], <8 x i32> [[SHAMT]])
+; XOP-NEXT:    store <8 x i32> [[ROT]], <8 x i32>* [[T5]], align 4
+; XOP-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 8
+; XOP-NEXT:    [[T7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1024
+; XOP-NEXT:    br i1 [[T7]], label [[EXIT:%.*]], label [[LOOP]]
+; XOP:       exit:
+; XOP-NEXT:    ret void
+;
+entry:
+  %i0 = insertelement <8 x i32> poison, i32 %rot0, i32 0
+  %s0 = shufflevector <8 x i32> %i0, <8 x i32> undef, <8 x i32> zeroinitializer
+  %i1 = insertelement <8 x i32> poison, i32 %rot1, i32 0
+  %s1 = shufflevector <8 x i32> %i1, <8 x i32> undef, <8 x i32> zeroinitializer
+  br label %loop
+
+loop:
+  %index = phi i64 [ 0, %entry ], [ %index.next, %loop ]
+  %t0 = getelementptr inbounds i8, i8* %control, i64 %index
+  %t1 = bitcast i8* %t0 to <8 x i8>*
+  %wide.load = load <8 x i8>, <8 x i8>* %t1, align 1
+  %t2 = icmp eq <8 x i8> %wide.load, zeroinitializer
+  %shamt = select <8 x i1> %t2, <8 x i32> %s0, <8 x i32> %s1
+  %t4 = getelementptr inbounds i32, i32* %arr, i64 %index
+  %t5 = bitcast i32* %t4 to <8 x i32>*
+  %wide.load21 = load <8 x i32>, <8 x i32>* %t5, align 4
+  %rot = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %wide.load21, <8 x i32> %wide.load21, <8 x i32> %shamt)
+  store <8 x i32> %rot, <8 x i32>* %t5, align 4
+  %index.next = add i64 %index, 8
+  %t7 = icmp eq i64 %index.next, 1024
+  br i1 %t7, label %exit, label %loop
+
+exit:
+  ret void
+}
+
+declare <8 x i32> @llvm.fshl.v8i32(<8 x i32>, <8 x i32>, <8 x i32>) #1
+
+; Check that every instruction inserted by -codegenprepare has a debug location.
+; DEBUG: CheckModuleDebugify: PASS
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inseltpoison.ll
new file mode 100644
index 0000000000000..4e9f09fa32bc7
--- /dev/null
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink-inseltpoison.ll
@@ -0,0 +1,257 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -codegenprepare -mcpu=corei7 %s | FileCheck %s --check-prefixes=CHECK,CHECK-SSE2
+; RUN: opt -S -codegenprepare -mcpu=bdver2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-XOP
+; RUN: opt -S -codegenprepare -mcpu=core-avx2 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX2
+; RUN: opt -S -codegenprepare -mcpu=skylake-avx512 %s | FileCheck %s --check-prefixes=CHECK,CHECK-AVX,CHECK-AVX512BW
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-darwin10.9.0"
+
+define <16 x i8> @test_8bit(<16 x i8> %lhs, <16 x i8> %tmp, i1 %tst) {
+; CHECK-LABEL: @test_8bit(
+; CHECK-NEXT:    [[MASK:%.*]] = shufflevector <16 x i8> [[TMP:%.*]], <16 x i8> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK:       if_true:
+; CHECK-NEXT:    ret <16 x i8> [[MASK]]
+; CHECK:       if_false:
+; CHECK-NEXT:    [[RES:%.*]] = shl <16 x i8> [[LHS:%.*]], [[MASK]]
+; CHECK-NEXT:    ret <16 x i8> [[RES]]
+;
+  %mask = shufflevector <16 x i8> %tmp, <16 x i8> undef, <16 x i32> zeroinitializer
+  br i1 %tst, label %if_true, label %if_false
+
+if_true:
+  ret <16 x i8> %mask
+
+if_false:
+  %res = shl <16 x i8> %lhs, %mask
+  ret <16 x i8> %res
+}
+
+define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) {
+; CHECK-SSE2-LABEL: @test_16bit(
+; CHECK-SSE2-NEXT:    [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-SSE2-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-SSE2:       if_true:
+; CHECK-SSE2-NEXT:    ret <8 x i16> [[MASK]]
+; CHECK-SSE2:       if_false:
+; CHECK-SSE2-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-SSE2-NEXT:    [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
+; CHECK-SSE2-NEXT:    ret <8 x i16> [[RES]]
+;
+; CHECK-XOP-LABEL: @test_16bit(
+; CHECK-XOP-NEXT:    [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-XOP-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-XOP:       if_true:
+; CHECK-XOP-NEXT:    ret <8 x i16> [[MASK]]
+; CHECK-XOP:       if_false:
+; CHECK-XOP-NEXT:    [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]]
+; CHECK-XOP-NEXT:    ret <8 x i16> [[RES]]
+;
+; CHECK-AVX2-LABEL: @test_16bit(
+; CHECK-AVX2-NEXT:    [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-AVX2-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-AVX2:       if_true:
+; CHECK-AVX2-NEXT:    ret <8 x i16> [[MASK]]
+; CHECK-AVX2:       if_false:
+; CHECK-AVX2-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-AVX2-NEXT:    [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
+; CHECK-AVX2-NEXT:    ret <8 x i16> [[RES]]
+;
+; CHECK-AVX512BW-LABEL: @test_16bit(
+; CHECK-AVX512BW-NEXT:    [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-AVX512BW-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-AVX512BW:       if_true:
+; CHECK-AVX512BW-NEXT:    ret <8 x i16> [[MASK]]
+; CHECK-AVX512BW:       if_false:
+; CHECK-AVX512BW-NEXT:    [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[MASK]]
+; CHECK-AVX512BW-NEXT:    ret <8 x i16> [[RES]]
+;
+  %mask = shufflevector <8 x i16> %tmp, <8 x i16> undef, <8 x i32> zeroinitializer
+  br i1 %tst, label %if_true, label %if_false
+
+if_true:
+  ret <8 x i16> %mask
+
+if_false:
+  %res = shl <8 x i16> %lhs, %mask
+  ret <8 x i16> %res
+}
+
+define <4 x i32> @test_notsplat(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) {
+; CHECK-LABEL: @test_notsplat(
+; CHECK-NEXT:    [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
+; CHECK-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK:       if_true:
+; CHECK-NEXT:    ret <4 x i32> [[MASK]]
+; CHECK:       if_false:
+; CHECK-NEXT:    [[RES:%.*]] = shl <4 x i32> [[LHS:%.*]], [[MASK]]
+; CHECK-NEXT:    ret <4 x i32> [[RES]]
+;
+  %mask = shufflevector <4 x i32> %tmp, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0>
+  br i1 %tst, label %if_true, label %if_false
+
+if_true:
+  ret <4 x i32> %mask
+
+if_false:
+  %res = shl <4 x i32> %lhs, %mask
+  ret <4 x i32> %res
+}
+
+define <4 x i32> @test_32bit(<4 x i32> %lhs, <4 x i32> %tmp, i1 %tst) {
+; CHECK-SSE2-LABEL: @test_32bit(
+; CHECK-SSE2-NEXT:    [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
+; CHECK-SSE2-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-SSE2:       if_true:
+; CHECK-SSE2-NEXT:    ret <4 x i32> [[MASK]]
+; CHECK-SSE2:       if_false:
+; CHECK-SSE2-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
+; CHECK-SSE2-NEXT:    [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[TMP1]]
+; CHECK-SSE2-NEXT:    ret <4 x i32> [[RES]]
+;
+; CHECK-XOP-LABEL: @test_32bit(
+; CHECK-XOP-NEXT:    [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
+; CHECK-XOP-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-XOP:       if_true:
+; CHECK-XOP-NEXT:    ret <4 x i32> [[MASK]]
+; CHECK-XOP:       if_false:
+; CHECK-XOP-NEXT:    [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[MASK]]
+; CHECK-XOP-NEXT:    ret <4 x i32> [[RES]]
+;
+; CHECK-AVX-LABEL: @test_32bit(
+; CHECK-AVX-NEXT:    [[MASK:%.*]] = shufflevector <4 x i32> [[TMP:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
+; CHECK-AVX-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-AVX:       if_true:
+; CHECK-AVX-NEXT:    ret <4 x i32> [[MASK]]
+; CHECK-AVX:       if_false:
+; CHECK-AVX-NEXT:    [[RES:%.*]] = ashr <4 x i32> [[LHS:%.*]], [[MASK]]
+; CHECK-AVX-NEXT:    ret <4 x i32> [[RES]]
+;
+  %mask = shufflevector <4 x i32> %tmp, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
+  br i1 %tst, label %if_true, label %if_false
+
+if_true:
+  ret <4 x i32> %mask
+
+if_false:
+  %res = ashr <4 x i32> %lhs, %mask
+  ret <4 x i32> %res
+}
+
+define <2 x i64> @test_64bit(<2 x i64> %lhs, <2 x i64> %tmp, i1 %tst) {
+; CHECK-SSE2-LABEL: @test_64bit(
+; CHECK-SSE2-NEXT:    [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer
+; CHECK-SSE2-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-SSE2:       if_true:
+; CHECK-SSE2-NEXT:    ret <2 x i64> [[MASK]]
+; CHECK-SSE2:       if_false:
+; CHECK-SSE2-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <2 x i32> zeroinitializer
+; CHECK-SSE2-NEXT:    [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[TMP1]]
+; CHECK-SSE2-NEXT:    ret <2 x i64> [[RES]]
+;
+; CHECK-XOP-LABEL: @test_64bit(
+; CHECK-XOP-NEXT:    [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer
+; CHECK-XOP-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-XOP:       if_true:
+; CHECK-XOP-NEXT:    ret <2 x i64> [[MASK]]
+; CHECK-XOP:       if_false:
+; CHECK-XOP-NEXT:    [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[MASK]]
+; CHECK-XOP-NEXT:    ret <2 x i64> [[RES]]
+;
+; CHECK-AVX-LABEL: @test_64bit(
+; CHECK-AVX-NEXT:    [[MASK:%.*]] = shufflevector <2 x i64> [[TMP:%.*]], <2 x i64> undef, <2 x i32> zeroinitializer
+; CHECK-AVX-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK-AVX:       if_true:
+; CHECK-AVX-NEXT:    ret <2 x i64> [[MASK]]
+; CHECK-AVX:       if_false:
+; CHECK-AVX-NEXT:    [[RES:%.*]] = lshr <2 x i64> [[LHS:%.*]], [[MASK]]
+; CHECK-AVX-NEXT:    ret <2 x i64> [[RES]]
+;
+  %mask = shufflevector <2 x i64> %tmp, <2 x i64> undef, <2 x i32> zeroinitializer
+  br i1 %tst, label %if_true, label %if_false
+
+if_true:
+  ret <2 x i64> %mask
+
+if_false:
+  %res = lshr <2 x i64> %lhs, %mask
+  ret <2 x i64> %res
+}
+
+define void @funnel_splatvar(i32* nocapture %arr, i32 %rot) {
+; CHECK-SSE2-LABEL: @funnel_splatvar(
+; CHECK-SSE2-NEXT:  entry:
+; CHECK-SSE2-NEXT:    [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <8 x i32> poison, i32 [[ROT:%.*]], i32 0
+; CHECK-SSE2-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK-SSE2:       vector.body:
+; CHECK-SSE2-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-SSE2-NEXT:    [[T0:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; CHECK-SSE2-NEXT:    [[T1:%.*]] = bitcast i32* [[T0]] to <8 x i32>*
+; CHECK-SSE2-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i32>, <8 x i32>* [[T1]], align 4
+; CHECK-SSE2-NEXT:    [[TMP0:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT15]], <8 x i32> undef, <8 x i32> zeroinitializer
+; CHECK-SSE2-NEXT:    [[T2:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[TMP0]])
+; CHECK-SSE2-NEXT:    store <8 x i32> [[T2]], <8 x i32>* [[T1]], align 4
+; CHECK-SSE2-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 8
+; CHECK-SSE2-NEXT:    [[T3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
+; CHECK-SSE2-NEXT:    br i1 [[T3]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
+; CHECK-SSE2:       for.cond.cleanup:
+; CHECK-SSE2-NEXT:    ret void
+;
+; CHECK-XOP-LABEL: @funnel_splatvar(
+; CHECK-XOP-NEXT:  entry:
+; CHECK-XOP-NEXT:    [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <8 x i32> poison, i32 [[ROT:%.*]], i32 0
+; CHECK-XOP-NEXT:    [[BROADCAST_SPLAT16:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT15]], <8 x i32> undef, <8 x i32> zeroinitializer
+; CHECK-XOP-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK-XOP:       vector.body:
+; CHECK-XOP-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-XOP-NEXT:    [[T0:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; CHECK-XOP-NEXT:    [[T1:%.*]] = bitcast i32* [[T0]] to <8 x i32>*
+; CHECK-XOP-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i32>, <8 x i32>* [[T1]], align 4
+; CHECK-XOP-NEXT:    [[T2:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[BROADCAST_SPLAT16]])
+; CHECK-XOP-NEXT:    store <8 x i32> [[T2]], <8 x i32>* [[T1]], align 4
+; CHECK-XOP-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 8
+; CHECK-XOP-NEXT:    [[T3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
+; CHECK-XOP-NEXT:    br i1 [[T3]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
+; CHECK-XOP:       for.cond.cleanup:
+; CHECK-XOP-NEXT:    ret void
+;
+; CHECK-AVX-LABEL: @funnel_splatvar(
+; CHECK-AVX-NEXT:  entry:
+; CHECK-AVX-NEXT:    [[BROADCAST_SPLATINSERT15:%.*]] = insertelement <8 x i32> poison, i32 [[ROT:%.*]], i32 0
+; CHECK-AVX-NEXT:    [[BROADCAST_SPLAT16:%.*]] = shufflevector <8 x i32> [[BROADCAST_SPLATINSERT15]], <8 x i32> undef, <8 x i32> zeroinitializer
+; CHECK-AVX-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK-AVX:       vector.body:
+; CHECK-AVX-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-AVX-NEXT:    [[T0:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[INDEX]]
+; CHECK-AVX-NEXT:    [[T1:%.*]] = bitcast i32* [[T0]] to <8 x i32>*
+; CHECK-AVX-NEXT:    [[WIDE_LOAD:%.*]] = load <8 x i32>, <8 x i32>* [[T1]], align 4
+; CHECK-AVX-NEXT:    [[T2:%.*]] = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> [[WIDE_LOAD]], <8 x i32> [[WIDE_LOAD]], <8 x i32> [[BROADCAST_SPLAT16]])
+; CHECK-AVX-NEXT:    store <8 x i32> [[T2]], <8 x i32>* [[T1]], align 4
+; CHECK-AVX-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 8
+; CHECK-AVX-NEXT:    [[T3:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
+; CHECK-AVX-NEXT:    br i1 [[T3]], label [[FOR_COND_CLEANUP:%.*]], label [[VECTOR_BODY]]
+; CHECK-AVX:       for.cond.cleanup:
+; CHECK-AVX-NEXT:    ret void
+;
+entry:
+  %broadcast.splatinsert15 = insertelement <8 x i32> poison, i32 %rot, i32 0
+  %broadcast.splat16 = shufflevector <8 x i32> %broadcast.splatinsert15, <8 x i32> undef, <8 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:
+  %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
+  %t0 = getelementptr inbounds i32, i32* %arr, i64 %index
+  %t1 = bitcast i32* %t0 to <8 x i32>*
+  %wide.load = load <8 x i32>, <8 x i32>* %t1, align 4
+  %t2 = call <8 x i32> @llvm.fshl.v8i32(<8 x i32> %wide.load, <8 x i32> %wide.load, <8 x i32> %broadcast.splat16)
+  store <8 x i32> %t2, <8 x i32>* %t1, align 4
+  %index.next = add i64 %index, 8
+  %t3 = icmp eq i64 %index.next, 65536
+  br i1 %t3, label %for.cond.cleanup, label %vector.body
+
+for.cond.cleanup:
+  ret void
+}
+
+declare <8 x i32> @llvm.fshl.v8i32(<8 x i32>, <8 x i32>, <8 x i32>)
diff --git a/llvm/test/Transforms/Coroutines/coro-async.ll b/llvm/test/Transforms/Coroutines/coro-async.ll
index f0036440c803b..bca65c37e7d31 100644
--- a/llvm/test/Transforms/Coroutines/coro-async.ll
+++ b/llvm/test/Transforms/Coroutines/coro-async.ll
@@ -94,7 +94,7 @@ entry:
   call void @some_user(i64 %val.2)
 
   tail call swiftcc void @asyncReturn(i8* %async.ctxt, %async.task* %task.2, %async.actor* %actor)
-  call i1 @llvm.coro.end(i8* %hdl, i1 0)
+  call i1 (i8*, i1, ...) @llvm.coro.end.async(i8* %hdl, i1 0)
   unreachable
 }
 
@@ -311,12 +311,75 @@ entry:
   %continuation_task_arg = extractvalue {i8*, i8*, i8*} %res, 1
   %task.2 =  bitcast i8* %continuation_task_arg to %async.task*
   tail call swiftcc void @asyncReturn(i8* %async.ctxt, %async.task* %task.2, %async.actor* %actor)
-  call i1 @llvm.coro.end(i8* %hdl, i1 0)
+  call i1 (i8*, i1, ...) @llvm.coro.end.async(i8* %hdl, i1 0)
   unreachable
 }
+
+@multiple_coro_end_async_fp = constant <{ i32, i32 }>
+  <{ i32 trunc ( ; Relative pointer to async function
+       i64 sub (
+         i64 ptrtoint (void (i8*, %async.task*, %async.actor*)* @multiple_coro_end_async to i64),
+         i64 ptrtoint (i32* getelementptr inbounds (<{ i32, i32 }>, <{ i32, i32 }>* @multiple_coro_end_async_fp, i32 0, i32 1) to i64)
+       )
+     to i32),
+     i32 128    ; Initial async context size without space for frame
+}>
+
+define swiftcc void @must_tail_call_return(i8* %async.ctxt, %async.task* %task, %async.actor* %actor) {
+  musttail call swiftcc void @asyncReturn(i8* %async.ctxt, %async.task* %task, %async.actor* %actor)
+  ret void
+}
+
+define swiftcc void @multiple_coro_end_async(i8* %async.ctxt, %async.task* %task, %async.actor* %actor)  {
+entry:
+  %id = call token @llvm.coro.id.async(i32 128, i32 16, i32 0,
+          i8* bitcast (<{i32, i32}>* @dont_crash_on_cf_fp to i8*))
+  %hdl = call i8* @llvm.coro.begin(token %id, i8* null)
+  %arg0 = bitcast %async.task* %task to i8*
+  %arg1 = bitcast <{ i32, i32}>* @my_other_async_function_fp to i8*
+  %callee_context = call i8* @llvm.coro.async.context.alloc(i8* %arg0, i8* %arg1)
+	%callee_context.0 = bitcast i8* %callee_context to %async.ctxt*
+  %callee_context.return_to_caller.addr = getelementptr inbounds %async.ctxt, %async.ctxt* %callee_context.0, i32 0, i32 1
+  %return_to_caller.addr = bitcast void(i8*, %async.task*, %async.actor*)** %callee_context.return_to_caller.addr to i8**
+  %resume.func_ptr = call i8* @llvm.coro.async.resume()
+  store i8* %resume.func_ptr, i8** %return_to_caller.addr
+  %callee_context.caller_context.addr = getelementptr inbounds %async.ctxt, %async.ctxt* %callee_context.0, i32 0, i32 0
+  store i8* %async.ctxt, i8** %callee_context.caller_context.addr
+  %resume_proj_fun = bitcast i8*(i8*)* @resume_context_projection to i8*
+  %callee = bitcast void(i8*, %async.task*, %async.actor*)* @asyncSuspend to i8*
+  %res = call {i8*, i8*, i8*} (i8*, i8*, ...) @llvm.coro.suspend.async(
+                                                  i8* %resume.func_ptr,
+                                                  i8* %resume_proj_fun,
+                                                  void (i8*, i8*, %async.task*, %async.actor*)* @dont_crash_on_cf_dispatch,
+                                                  i8* %callee, i8* %callee_context, %async.task* %task, %async.actor *%actor)
+
+  call void @llvm.coro.async.context.dealloc(i8* %callee_context)
+  %continuation_task_arg = extractvalue {i8*, i8*, i8*} %res, 1
+  %task.2 =  bitcast i8* %continuation_task_arg to %async.task*
+  %eq = icmp eq i8 * %continuation_task_arg, null
+  br i1 %eq, label %is_equal, label %is_not_equal
+
+is_equal:
+  tail call swiftcc void @asyncReturn(i8* %async.ctxt, %async.task* %task.2, %async.actor* %actor)
+  call i1 (i8*, i1, ...) @llvm.coro.end.async(i8* %hdl, i1 0)
+  unreachable
+
+is_not_equal:
+  call i1 (i8*, i1, ...) @llvm.coro.end.async(
+                           i8* %hdl, i1 0,
+                           void (i8*, %async.task*, %async.actor*)* @must_tail_call_return,
+                           i8* %async.ctxt, %async.task* %task.2, %async.actor* null)
+  unreachable
+}
+
+; CHECK-LABEL: define internal swiftcc void @multiple_coro_end_async.resume.0(
+; CHECK: musttail call swiftcc void @asyncReturn(
+; CHECK: ret void
+
 declare i8* @llvm.coro.prepare.async(i8*)
 declare token @llvm.coro.id.async(i32, i32, i32, i8*)
 declare i8* @llvm.coro.begin(token, i8*)
+declare i1 @llvm.coro.end.async(i8*, i1, ...)
 declare i1 @llvm.coro.end(i8*, i1)
 declare {i8*, i8*, i8*} @llvm.coro.suspend.async(i8*, i8*, ...)
 declare i8* @llvm.coro.async.context.alloc(i8*, i8*)
diff --git a/llvm/test/Transforms/Coroutines/coro-inline.ll b/llvm/test/Transforms/Coroutines/coro-inline.ll
index 2cc679a0127d5..5142dd7e45cfa 100644
--- a/llvm/test/Transforms/Coroutines/coro-inline.ll
+++ b/llvm/test/Transforms/Coroutines/coro-inline.ll
@@ -1,4 +1,4 @@
-; RUN: opt < %s -always-inline -barrier -coro-split -S | FileCheck %s
+; RUN: opt < %s -always-inline -barrier -coro-split -S -enable-new-pm=0 | FileCheck %s
 ; RUN: opt < %s -passes='always-inline,cgscc(coro-split)' -S | FileCheck %s
 ; RUN: opt < %s -sample-profile-file=%S/Inputs/sample.text.prof -pgo-kind=pgo-sample-use-pipeline -sample-profile -coro-split -disable-inlining=true -S | FileCheck %s
 ; RUN: opt < %s -sample-profile-file=%S/Inputs/sample.text.prof -pgo-kind=pgo-sample-use-pipeline -passes='sample-profile,cgscc(coro-split)' -disable-inlining=true -S | FileCheck %s
diff --git a/llvm/test/Transforms/CorrelatedValuePropagation/basic.ll b/llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
index 0c41bb6270f9e..bec6f9431c9df 100644
--- a/llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
+++ b/llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
@@ -1061,6 +1061,200 @@ exit2:
   ret i1 %cmp2
 }
 
+define void @select_and(i32 %a, i1* %p) {
+; CHECK-LABEL: @select_and(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -10
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[A]], 10
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[CMP1]], i1 [[CMP2]], i1 false
+; CHECK-NEXT:    br i1 [[AND]], label [[GUARD:%.*]], label [[EXIT:%.*]]
+; CHECK:       guard:
+; CHECK-NEXT:    store i1 false, i1* [[P:%.*]], align 1
+; CHECK-NEXT:    store i1 false, i1* [[P]], align 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %cmp1 = icmp sgt i32 %a, -10
+  %cmp2 = icmp slt i32 %a, 10
+  %and = select i1 %cmp1, i1 %cmp2, i1 false
+  br i1 %and, label %guard, label %exit
+
+guard:
+  %c1 = icmp sgt i32 %a, 20
+  store i1 %c1, i1* %p
+  %c2 = icmp slt i32 %a, -20
+  store i1 %c2, i1* %p
+  br label %exit
+
+exit:
+  ret void
+}
+
+define void @select_and_wrong_const(i32 %a, i1* %p) {
+; CHECK-LABEL: @select_and_wrong_const(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -10
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[A]], 10
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[CMP1]], i1 [[CMP2]], i1 true
+; CHECK-NEXT:    br i1 [[AND]], label [[GUARD:%.*]], label [[EXIT:%.*]]
+; CHECK:       guard:
+; CHECK-NEXT:    [[C1:%.*]] = icmp sgt i32 [[A]], 20
+; CHECK-NEXT:    store i1 [[C1]], i1* [[P:%.*]], align 1
+; CHECK-NEXT:    [[C2:%.*]] = icmp slt i32 [[A]], -20
+; CHECK-NEXT:    store i1 [[C2]], i1* [[P]], align 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %cmp1 = icmp sgt i32 %a, -10
+  %cmp2 = icmp slt i32 %a, 10
+  %and = select i1 %cmp1, i1 %cmp2, i1 true
+  br i1 %and, label %guard, label %exit
+
+guard:
+  %c1 = icmp sgt i32 %a, 20
+  store i1 %c1, i1* %p
+  %c2 = icmp slt i32 %a, -20
+  store i1 %c2, i1* %p
+  br label %exit
+
+exit:
+  ret void
+}
+
+define void @select_and_wrong_operand(i32 %a, i1* %p) {
+; CHECK-LABEL: @select_and_wrong_operand(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[A:%.*]], -10
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[A]], 10
+; CHECK-NEXT:    [[AND:%.*]] = select i1 [[CMP1]], i1 false, i1 [[CMP2]]
+; CHECK-NEXT:    br i1 [[AND]], label [[GUARD:%.*]], label [[EXIT:%.*]]
+; CHECK:       guard:
+; CHECK-NEXT:    [[C1:%.*]] = icmp sgt i32 [[A]], 20
+; CHECK-NEXT:    store i1 [[C1]], i1* [[P:%.*]], align 1
+; CHECK-NEXT:    [[C2:%.*]] = icmp slt i32 [[A]], -20
+; CHECK-NEXT:    store i1 [[C2]], i1* [[P]], align 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %cmp1 = icmp sgt i32 %a, -10
+  %cmp2 = icmp slt i32 %a, 10
+  %and = select i1 %cmp1, i1 false, i1 %cmp2
+  br i1 %and, label %guard, label %exit
+
+guard:
+  %c1 = icmp sgt i32 %a, 20
+  store i1 %c1, i1* %p
+  %c2 = icmp slt i32 %a, -20
+  store i1 %c2, i1* %p
+  br label %exit
+
+exit:
+  ret void
+}
+
+define void @select_or(i32 %a, i1* %p) {
+; CHECK-LABEL: @select_or(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], -10
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp sgt i32 [[A]], 10
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
+; CHECK-NEXT:    br i1 [[OR]], label [[EXIT:%.*]], label [[GUARD:%.*]]
+; CHECK:       guard:
+; CHECK-NEXT:    store i1 false, i1* [[P:%.*]], align 1
+; CHECK-NEXT:    store i1 false, i1* [[P]], align 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %cmp1 = icmp slt i32 %a, -10
+  %cmp2 = icmp sgt i32 %a, 10
+  %or = select i1 %cmp1, i1 true, i1 %cmp2
+  br i1 %or, label %exit, label %guard
+
+guard:
+  %c1 = icmp sgt i32 %a, 20
+  store i1 %c1, i1* %p
+  %c2 = icmp slt i32 %a, -20
+  store i1 %c2, i1* %p
+  br label %exit
+
+exit:
+  ret void
+}
+
+define void @select_or_wrong_const(i32 %a, i1* %p) {
+; CHECK-LABEL: @select_or_wrong_const(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], -10
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp sgt i32 [[A]], 10
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[CMP1]], i1 false, i1 [[CMP2]]
+; CHECK-NEXT:    br i1 [[OR]], label [[EXIT:%.*]], label [[GUARD:%.*]]
+; CHECK:       guard:
+; CHECK-NEXT:    [[C1:%.*]] = icmp sgt i32 [[A]], 20
+; CHECK-NEXT:    store i1 [[C1]], i1* [[P:%.*]], align 1
+; CHECK-NEXT:    [[C2:%.*]] = icmp slt i32 [[A]], -20
+; CHECK-NEXT:    store i1 [[C2]], i1* [[P]], align 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %cmp1 = icmp slt i32 %a, -10
+  %cmp2 = icmp sgt i32 %a, 10
+  %or = select i1 %cmp1, i1 false, i1 %cmp2
+  br i1 %or, label %exit, label %guard
+
+guard:
+  %c1 = icmp sgt i32 %a, 20
+  store i1 %c1, i1* %p
+  %c2 = icmp slt i32 %a, -20
+  store i1 %c2, i1* %p
+  br label %exit
+
+exit:
+  ret void
+}
+
+define void @select_or_wrong_operand(i32 %a, i1* %p) {
+; CHECK-LABEL: @select_or_wrong_operand(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[A:%.*]], -10
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp sgt i32 [[A]], 10
+; CHECK-NEXT:    [[OR:%.*]] = select i1 [[CMP1]], i1 [[CMP2]], i1 true
+; CHECK-NEXT:    br i1 [[OR]], label [[EXIT:%.*]], label [[GUARD:%.*]]
+; CHECK:       guard:
+; CHECK-NEXT:    [[C1:%.*]] = icmp sgt i32 [[A]], 20
+; CHECK-NEXT:    store i1 [[C1]], i1* [[P:%.*]], align 1
+; CHECK-NEXT:    [[C2:%.*]] = icmp slt i32 [[A]], -20
+; CHECK-NEXT:    store i1 [[C2]], i1* [[P]], align 1
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %cmp1 = icmp slt i32 %a, -10
+  %cmp2 = icmp sgt i32 %a, 10
+  %or = select i1 %cmp1, i1 %cmp2, i1 true
+  br i1 %or, label %exit, label %guard
+
+guard:
+  %c1 = icmp sgt i32 %a, 20
+  store i1 %c1, i1* %p
+  %c2 = icmp slt i32 %a, -20
+  store i1 %c2, i1* %p
+  br label %exit
+
+exit:
+  ret void
+}
+
 declare i32 @llvm.uadd.sat.i32(i32, i32)
 declare i32 @llvm.usub.sat.i32(i32, i32)
 declare i32 @llvm.sadd.sat.i32(i32, i32)
diff --git a/llvm/test/Transforms/EarlyCSE/and_or.ll b/llvm/test/Transforms/EarlyCSE/and_or.ll
index b70d0cea3f7fb..2c04e7e3cf905 100644
--- a/llvm/test/Transforms/EarlyCSE/and_or.ll
+++ b/llvm/test/Transforms/EarlyCSE/and_or.ll
@@ -55,6 +55,34 @@ if.false:
   ret i32 %y
 }
 
+define i32 @test_02_select(i32 %a, i32 %b, i1 %c) {
+; CHECK-LABEL: @test_02_select(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[AND_COND:%.*]] = select i1 [[COND]], i1 [[C:%.*]], i1 false
+; CHECK-NEXT:    br i1 [[AND_COND]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK:       if.true:
+; CHECK-NEXT:    ret i32 [[A]]
+; CHECK:       if.false:
+; CHECK-NEXT:    [[Y:%.*]] = select i1 [[COND]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT:    ret i32 [[Y]]
+;
+entry:
+  %cond = icmp slt i32 %a, %b
+  %and.cond = select i1 %cond, i1 %c, i1 false
+  br i1 %and.cond, label %if.true, label %if.false
+
+if.true:
+  %cond2 = icmp slt i32 %a, %b
+  %x = select i1 %cond2, i32 %a, i32 %b
+  ret i32 %x
+
+if.false:
+  %cond3 = icmp slt i32 %a, %b
+  %y = select i1 %cond3, i32 %a, i32 %b
+  ret i32 %y
+}
+
 define i32 @test_03(i32 %a, i32 %b, i1 %c) {
 ; CHECK-LABEL: @test_03(
 ; CHECK-NEXT:  entry:
@@ -83,6 +111,34 @@ if.false:
   ret i32 %y
 }
 
+define i32 @test_03_select(i32 %a, i32 %b, i1 %c) {
+; CHECK-LABEL: @test_03_select(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[COND]], i1 true, i1 [[C:%.*]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK:       if.true:
+; CHECK-NEXT:    [[X:%.*]] = select i1 [[COND]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT:    ret i32 [[X]]
+; CHECK:       if.false:
+; CHECK-NEXT:    ret i32 [[B]]
+;
+entry:
+  %cond = icmp slt i32 %a, %b
+  %or.cond = select i1 %cond, i1 true, i1 %c
+  br i1 %or.cond, label %if.true, label %if.false
+
+if.true:
+  %cond2 = icmp slt i32 %a, %b
+  %x = select i1 %cond2, i32 %a, i32 %b
+  ret i32 %x
+
+if.false:
+  %cond3 = icmp slt i32 %a, %b
+  %y = select i1 %cond3, i32 %a, i32 %b
+  ret i32 %y
+}
+
 define i32 @test_04(i32 %a, i32 %b, i1 %c1, i1 %c2) {
 ; CHECK-LABEL: @test_04(
 ; CHECK-NEXT:  entry:
@@ -113,6 +169,36 @@ if.false:
   ret i32 %y
 }
 
+define i32 @test_04_select(i32 %a, i32 %b, i1 %c1, i1 %c2) {
+; CHECK-LABEL: @test_04_select(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[AND_COND1:%.*]] = select i1 [[COND]], i1 [[C1:%.*]], i1 false
+; CHECK-NEXT:    [[AND_COND2:%.*]] = select i1 [[AND_COND1]], i1 [[C2:%.*]], i1 false
+; CHECK-NEXT:    br i1 [[AND_COND2]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK:       if.true:
+; CHECK-NEXT:    ret i32 [[A]]
+; CHECK:       if.false:
+; CHECK-NEXT:    [[Y:%.*]] = select i1 [[COND]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT:    ret i32 [[Y]]
+;
+entry:
+  %cond = icmp slt i32 %a, %b
+  %and.cond1 = select i1 %cond, i1 %c1, i1 false
+  %and.cond2 = select i1 %and.cond1, i1 %c2, i1 false
+  br i1 %and.cond2, label %if.true, label %if.false
+
+if.true:
+  %cond2 = icmp slt i32 %a, %b
+  %x = select i1 %cond2, i32 %a, i32 %b
+  ret i32 %x
+
+if.false:
+  %cond3 = icmp slt i32 %a, %b
+  %y = select i1 %cond3, i32 %a, i32 %b
+  ret i32 %y
+}
+
 define i32 @test_05(i32 %a, i32 %b, i1 %c1, i1 %c2) {
 ; CHECK-LABEL: @test_05(
 ; CHECK-NEXT:  entry:
@@ -142,3 +228,33 @@ if.false:
   %y = select i1 %cond3, i32 %a, i32 %b
   ret i32 %y
 }
+
+define i32 @test_05_select(i32 %a, i32 %b, i1 %c1, i1 %c2) {
+; CHECK-LABEL: @test_05_select(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[COND:%.*]] = icmp slt i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[OR_COND1:%.*]] = select i1 [[COND]], i1 true, i1 [[C1:%.*]]
+; CHECK-NEXT:    [[OR_COND2:%.*]] = select i1 [[OR_COND1]], i1 true, i1 [[C2:%.*]]
+; CHECK-NEXT:    br i1 [[OR_COND2]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
+; CHECK:       if.true:
+; CHECK-NEXT:    [[X:%.*]] = select i1 [[COND]], i32 [[A]], i32 [[B]]
+; CHECK-NEXT:    ret i32 [[X]]
+; CHECK:       if.false:
+; CHECK-NEXT:    ret i32 [[B]]
+;
+entry:
+  %cond = icmp slt i32 %a, %b
+  %or.cond1 = select i1 %cond, i1 true, i1 %c1
+  %or.cond2 = select i1 %or.cond1, i1 true, i1 %c2
+  br i1 %or.cond2, label %if.true, label %if.false
+
+if.true:
+  %cond2 = icmp slt i32 %a, %b
+  %x = select i1 %cond2, i32 %a, i32 %b
+  ret i32 %x
+
+if.false:
+  %cond3 = icmp slt i32 %a, %b
+  %y = select i1 %cond3, i32 %a, i32 %b
+  ret i32 %y
+}
diff --git a/llvm/test/Transforms/GVN/2016-08-30-MaskedScatterGather-inseltpoison.ll b/llvm/test/Transforms/GVN/2016-08-30-MaskedScatterGather-inseltpoison.ll
new file mode 100644
index 0000000000000..1d5428702a883
--- /dev/null
+++ b/llvm/test/Transforms/GVN/2016-08-30-MaskedScatterGather-inseltpoison.ll
@@ -0,0 +1,42 @@
+; RUN: opt < %s -basic-aa -gvn -S | FileCheck %s
+
+declare void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> , <2 x i32*> , i32 , <2 x i1> )
+declare <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*>, i32, <2 x i1>, <2 x i32>)
+
+; This test ensures that masked scatter and gather operations, which take vectors of pointers,
+; do not have pointer aliasing ignored when being processed.
+; No scatter/gather calls should end up eliminated
+; CHECK: llvm.masked.gather
+; CHECK: llvm.masked.gather
+; CHECK: llvm.masked.scatter
+; CHECK: llvm.masked.gather
+; CHECK: llvm.masked.scatter
+; CHECK: llvm.masked.gather
+define spir_kernel void @test(<2 x i32*> %in1, <2 x i32*> %in2, i32* %out) {
+entry:
+  ; Just some temporary storage
+  %tmp.0 = alloca i32
+  %tmp.1 = alloca i32
+  %tmp.i = insertelement <2 x i32*> poison, i32* %tmp.0, i32 0
+  %tmp = insertelement <2 x i32*> %tmp.i, i32* %tmp.1, i32 1
+  ; Read from in1 and in2
+  %in1.v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %in1, i32 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1
+  %in2.v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %in2, i32 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1
+  ; Store in1 to the allocas
+  call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %in1.v, <2 x i32*> %tmp, i32 1, <2 x i1> <i1 true, i1 true>);
+  ; Read in1 from the allocas
+  ; This gather should alias the scatter we just saw
+  %tmp.v.0 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %tmp, i32 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1
+  ; Store in2 to the allocas
+  call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %in2.v, <2 x i32*> %tmp, i32 1, <2 x i1> <i1 true, i1 true>);
+  ; Read in2 from the allocas
+  ; This gather should alias the scatter we just saw, and not be eliminated
+  %tmp.v.1 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %tmp, i32 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1
+  ; Store in2 to out for good measure
+  %tmp.v.1.0 = extractelement <2 x i32> %tmp.v.1, i32 0
+  %tmp.v.1.1 = extractelement <2 x i32> %tmp.v.1, i32 1
+  store i32 %tmp.v.1.0, i32* %out
+  %out.1 = getelementptr i32, i32* %out, i32 1
+  store i32 %tmp.v.1.1, i32* %out.1
+  ret void
+}
diff --git a/llvm/test/Transforms/GVN/PRE/modified-status.ll b/llvm/test/Transforms/GVN/PRE/modified-status.ll
new file mode 100644
index 0000000000000..6a329db51d7c3
--- /dev/null
+++ b/llvm/test/Transforms/GVN/PRE/modified-status.ll
@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -gvn -S %s | FileCheck %s
+
+; Make sure GVN correctly sets the modified status when doing PRE.
+
+define i32 @test(i64 %v, i32* %ptr.1, i32** %ptr.2, i1 %c)  {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[L_0:%.*]] = load i32, i32* [[PTR_1:%.*]], align 4
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    ret i32 10
+; CHECK:       if.end:
+; CHECK-NEXT:    [[L_0_EXT:%.*]] = zext i32 [[L_0]] to i64
+; CHECK-NEXT:    [[C_2:%.*]] = icmp eq i64 [[L_0_EXT]], 10
+; CHECK-NEXT:    br i1 [[C_2]], label [[IF_2_END:%.*]], label [[IF_2_THEN:%.*]]
+; CHECK:       if.2.then:
+; CHECK-NEXT:    [[GEP_1:%.*]] = getelementptr inbounds i32, i32* [[PTR_1]], i64 [[V:%.*]]
+; CHECK-NEXT:    [[L_2:%.*]] = load i32, i32* [[GEP_1]], align 4
+; CHECK-NEXT:    [[DOTPRE:%.*]] = zext i32 [[L_2]] to i64
+; CHECK-NEXT:    br label [[IF_2_END]]
+; CHECK:       if.2.end:
+; CHECK-NEXT:    [[REP_0_EXT_PRE_PHI:%.*]] = phi i64 [ [[DOTPRE]], [[IF_2_THEN]] ], [ 10, [[IF_END]] ]
+; CHECK-NEXT:    [[REP_0:%.*]] = phi i32 [ [[L_2]], [[IF_2_THEN]] ], [ [[L_0]], [[IF_END]] ]
+; CHECK-NEXT:    [[L_3:%.*]] = load i32*, i32** [[PTR_2:%.*]], align 8
+; CHECK-NEXT:    [[GEP_2:%.*]] = getelementptr inbounds i32, i32* [[PTR_1]], i64 [[REP_0_EXT_PRE_PHI]]
+; CHECK-NEXT:    [[L_4:%.*]] = load i32, i32* [[GEP_2]], align 4
+; CHECK-NEXT:    [[GEP_3:%.*]] = getelementptr inbounds i32, i32* [[L_3]], i64 10
+; CHECK-NEXT:    [[L_5:%.*]] = load i32, i32* [[GEP_3]], align 4
+; CHECK-NEXT:    [[R:%.*]] = add i32 [[L_4]], [[L_5]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+entry:
+  %l.0 = load i32, i32* %ptr.1, align 4
+  br i1 %c, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  ret i32 10
+
+if.end:                                           ; preds = %entry
+  %l.0.ext = zext i32 %l.0 to i64
+  %c.2 = icmp eq i64 %l.0.ext, 10
+  br i1 %c.2, label %if.2.end, label %if.2.then
+
+if.2.then:                                         ; preds = %if.end
+  %gep.1 = getelementptr inbounds i32, i32* %ptr.1, i64 %v
+  %l.2 = load i32, i32* %gep.1, align 4
+  br label %if.2.end
+
+if.2.end:                                         ; preds = %if.then7, %if.end
+  %rep.0 = phi i32 [ %l.2, %if.2.then ], [ %l.0, %if.end ]
+  %l.3 = load i32*, i32** %ptr.2, align 8
+  %rep.0.ext = zext i32 %rep.0 to i64
+  %gep.2 = getelementptr inbounds i32, i32* %ptr.1, i64 %rep.0.ext
+  %l.4 = load i32, i32* %gep.2, align 4
+  %gep.3 = getelementptr inbounds i32, i32* %l.3, i64 10
+  %l.5 = load i32, i32* %gep.3, align 4
+  %r = add i32 %l.4, %l.5
+  ret i32 %r
+}
diff --git a/llvm/test/Transforms/GVN/PRE/pre-gep-load.ll b/llvm/test/Transforms/GVN/PRE/pre-gep-load.ll
index cfea28eff03c8..33f145b707035 100644
--- a/llvm/test/Transforms/GVN/PRE/pre-gep-load.ll
+++ b/llvm/test/Transforms/GVN/PRE/pre-gep-load.ll
@@ -38,7 +38,7 @@ define double @foo(i32 %stat, i32 %i, double** %p) {
 ; CHECK-NEXT:    [[TMP3:%.*]] = phi double* [ [[DOTPRE]], [[ENTRY_SW_BB2_CRIT_EDGE]] ], [ [[TMP0]], [[IF_END]] ]
 ; CHECK-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds double, double* [[TMP3]], i64 [[IDXPROM3_PRE_PHI]]
 ; CHECK-NEXT:    [[SUB6:%.*]] = fsub double 3.000000e+00, [[TMP2]]
-; CHECK-NEXT:    store double [[SUB6]], double* [[ARRAYIDX5]]
+; CHECK-NEXT:    store double [[SUB6]], double* [[ARRAYIDX5]], align 8
 ; CHECK-NEXT:    br label [[RETURN]]
 ; CHECK:       sw.default:
 ; CHECK-NEXT:    br label [[RETURN]]
@@ -93,18 +93,15 @@ return:                                           ; preds = %sw.default, %sw.bb2
 
 define void @test_shortcut_safe(i1 %tst, i32 %p1, i32* %a) {
 ; CHECK-LABEL: @test_shortcut_safe(
-; CHECK-NEXT:    br i1 [[TST:%.*]], label [[SEXT1:%.*]], label [[DOTPRE_DEST_CRIT_EDGE:%.*]]
-; CHECK:       .pre.dest_crit_edge:
-; CHECK-NEXT:    [[DOTPRE1:%.*]] = sext i32 [[P1:%.*]] to i64
-; CHECK-NEXT:    br label [[PRE_DEST:%.*]]
+; CHECK-NEXT:    br i1 [[TST:%.*]], label [[SEXT1:%.*]], label [[PRE_DEST:%.*]]
 ; CHECK:       pre.dest:
-; CHECK-NEXT:    [[DOTPRE_PRE_PHI:%.*]] = phi i64 [ [[DOTPRE1]], [[DOTPRE_DEST_CRIT_EDGE]] ], [ [[IDXPROM2_PRE_PHI:%.*]], [[SEXT_USE:%.*]] ]
-; CHECK-NEXT:    br label [[SEXT_USE]]
+; CHECK-NEXT:    [[DOTPRE:%.*]] = sext i32 [[P1:%.*]] to i64
+; CHECK-NEXT:    br label [[SEXT_USE:%.*]]
 ; CHECK:       sext1:
 ; CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[P1]] to i64
 ; CHECK-NEXT:    br label [[SEXT_USE]]
 ; CHECK:       sext.use:
-; CHECK-NEXT:    [[IDXPROM2_PRE_PHI]] = phi i64 [ [[IDXPROM]], [[SEXT1]] ], [ [[DOTPRE_PRE_PHI]], [[PRE_DEST]] ]
+; CHECK-NEXT:    [[IDXPROM2_PRE_PHI:%.*]] = phi i64 [ [[IDXPROM]], [[SEXT1]] ], [ [[DOTPRE]], [[PRE_DEST]] ]
 ; CHECK-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i64 [[IDXPROM2_PRE_PHI]]
 ; CHECK-NEXT:    [[VAL:%.*]] = load i32, i32* [[ARRAYIDX3]], align 4
 ; CHECK-NEXT:    tail call void @g(i32 [[VAL]])
diff --git a/llvm/test/Transforms/GVN/condprop.ll b/llvm/test/Transforms/GVN/condprop.ll
index 1c07ad8441ee5..bb7befce9e820 100644
--- a/llvm/test/Transforms/GVN/condprop.ll
+++ b/llvm/test/Transforms/GVN/condprop.ll
@@ -79,6 +79,72 @@ nope:
   ret void
 }
 
+; CHECK-LABEL: @test3_select(
+define void @test3_select(i32 %x, i32 %y) {
+  %xz = icmp eq i32 %x, 0
+  %yz = icmp eq i32 %y, 0
+  %z = select i1 %xz, i1 %yz, i1 false
+  br i1 %z, label %both_zero, label %nope
+both_zero:
+  call void @foo(i1 %xz)
+; CHECK: call void @foo(i1 true)
+  call void @foo(i1 %yz)
+; CHECK: call void @foo(i1 true)
+  call void @bar(i32 %x)
+; CHECK: call void @bar(i32 0)
+  call void @bar(i32 %y)
+; CHECK: call void @bar(i32 0)
+  ret void
+nope:
+  call void @foo(i1 %z)
+; CHECK: call void @foo(i1 false)
+  ret void
+}
+
+; CHECK-LABEL: @test3_or(
+define void @test3_or(i32 %x, i32 %y) {
+  %xz = icmp ne i32 %x, 0
+  %yz = icmp ne i32 %y, 0
+  %z = or i1 %xz, %yz
+  br i1 %z, label %nope, label %both_zero
+both_zero:
+  call void @foo(i1 %xz)
+; CHECK: call void @foo(i1 false)
+  call void @foo(i1 %yz)
+; CHECK: call void @foo(i1 false)
+  call void @bar(i32 %x)
+; CHECK: call void @bar(i32 0)
+  call void @bar(i32 %y)
+; CHECK: call void @bar(i32 0)
+  ret void
+nope:
+  call void @foo(i1 %z)
+; CHECK: call void @foo(i1 true)
+  ret void
+}
+
+; CHECK-LABEL: @test3_or_select(
+define void @test3_or_select(i32 %x, i32 %y) {
+  %xz = icmp ne i32 %x, 0
+  %yz = icmp ne i32 %y, 0
+  %z = select i1 %xz, i1 true, i1 %yz
+  br i1 %z, label %nope, label %both_zero
+both_zero:
+  call void @foo(i1 %xz)
+; CHECK: call void @foo(i1 false)
+  call void @foo(i1 %yz)
+; CHECK: call void @foo(i1 false)
+  call void @bar(i32 %x)
+; CHECK: call void @bar(i32 0)
+  call void @bar(i32 %y)
+; CHECK: call void @bar(i32 0)
+  ret void
+nope:
+  call void @foo(i1 %z)
+; CHECK: call void @foo(i1 true)
+  ret void
+}
+
 ; CHECK-LABEL: @test4(
 define void @test4(i1 %b, i32 %x) {
   br i1 %b, label %sw, label %case3
diff --git a/llvm/test/Transforms/GVN/constexpr-vector-constainsundef-crash-inseltpoison.ll b/llvm/test/Transforms/GVN/constexpr-vector-constainsundef-crash-inseltpoison.ll
new file mode 100644
index 0000000000000..6750b858e03fb
--- /dev/null
+++ b/llvm/test/Transforms/GVN/constexpr-vector-constainsundef-crash-inseltpoison.ll
@@ -0,0 +1,25 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -gvn -S %s | FileCheck %s
+
+; Reduced test case from
+; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=24278
+
+; Make sure we do not crash when dealing with a vector constant expression.
+define <4 x i64*> @test(i64* %ptr) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[L3:%.*]] = load i64, i64* [[PTR:%.*]], align 4
+; CHECK-NEXT:    [[I6:%.*]] = insertelement <4 x i64*> getelementptr (i64, i64* null, <4 x i64> <i64 poison, i64 poison, i64 poison, i64 -128>), i64* undef, i64 [[L3]]
+; CHECK-NEXT:    ret <4 x i64*> [[I6]]
+;
+entry:
+  %B9 = sdiv i16 -32768, 256
+  %L3 = load i64, i64* %ptr, align 4
+  %B3 = sub i16 0, %B9
+  %0 = insertelement <4 x i16> poison, i16 %B3, i32 3
+  %1 = sub <4 x i16> zeroinitializer, %0
+  %2 = sext <4 x i16> %1 to <4 x i32>
+  %3 = getelementptr inbounds i64, i64* null, <4 x i32> %2
+  %I6 = insertelement <4 x i64*> %3, i64* undef, i64 %L3
+  ret <4 x i64*> %I6
+}
diff --git a/llvm/test/Transforms/GVN/non-integral-pointers-inseltpoison.ll b/llvm/test/Transforms/GVN/non-integral-pointers-inseltpoison.ll
new file mode 100644
index 0000000000000..2aef7620841bd
--- /dev/null
+++ b/llvm/test/Transforms/GVN/non-integral-pointers-inseltpoison.ll
@@ -0,0 +1,456 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -gvn -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:4:5"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @f0(i1 %alwaysFalse, i64 %val, i64* %loc) {
+; CHECK-LABEL: @f0(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    store i64 [[VAL:%.*]], i64* [[LOC:%.*]], align 8
+; CHECK-NEXT:    br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
+; CHECK:       neverTaken:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i64* [[LOC]] to i8 addrspace(4)**
+; CHECK-NEXT:    [[PTR:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)** [[LOC_BC]], align 8
+; CHECK-NEXT:    store i8 5, i8 addrspace(4)* [[PTR]], align 1
+; CHECK-NEXT:    ret void
+; CHECK:       alwaysTaken:
+; CHECK-NEXT:    ret void
+;
+  entry:
+  store i64 %val, i64* %loc
+  br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
+
+  neverTaken:
+  %loc.bc = bitcast i64* %loc to i8 addrspace(4)**
+  %ptr = load i8 addrspace(4)*, i8 addrspace(4)** %loc.bc
+  store i8 5, i8 addrspace(4)* %ptr
+  ret void
+
+  alwaysTaken:
+  ret void
+}
+
+define i64 @f1(i1 %alwaysFalse, i8 addrspace(4)* %val, i8 addrspace(4)** %loc) {
+; CHECK-LABEL: @f1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    store i8 addrspace(4)* [[VAL:%.*]], i8 addrspace(4)** [[LOC:%.*]], align 8
+; CHECK-NEXT:    br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
+; CHECK:       neverTaken:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)** [[LOC]] to i64*
+; CHECK-NEXT:    [[INT:%.*]] = load i64, i64* [[LOC_BC]], align 8
+; CHECK-NEXT:    ret i64 [[INT]]
+; CHECK:       alwaysTaken:
+; CHECK-NEXT:    ret i64 42
+;
+  entry:
+  store i8 addrspace(4)* %val, i8 addrspace(4)** %loc
+  br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
+
+  neverTaken:
+  %loc.bc = bitcast i8 addrspace(4)** %loc to i64*
+  %int = load i64, i64* %loc.bc
+  ret i64 %int
+
+  alwaysTaken:
+  ret i64 42
+}
+
+;; Note: For terseness, we stop using the %alwaysfalse trick for the
+;; tests below and just exercise the bits of forwarding logic directly.
+
+declare void @llvm.memset.p4i8.i64(i8 addrspace(4)* nocapture, i8, i64, i1) nounwind
+
+; Can't forward as the load might be dead.  (Pretend we wrote out the alwaysfalse idiom above.)
+define i8 addrspace(4)* @neg_forward_memset(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_forward_memset(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8 7, i64 8, i1 false)
+; CHECK-NEXT:    [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], align 8
+; CHECK-NEXT:    ret i8 addrspace(4)* [[REF]]
+;
+  entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
+  call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8 7, i64 8, i1 false)
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
+  ret i8 addrspace(4)* %ref
+}
+
+define <1 x i8 addrspace(4)*> @neg_forward_memset_vload(<1 x i8 addrspace(4)*> addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_forward_memset_vload(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast <1 x i8 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8 7, i64 8, i1 false)
+; CHECK-NEXT:    [[REF:%.*]] = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* [[LOC]], align 8
+; CHECK-NEXT:    ret <1 x i8 addrspace(4)*> [[REF]]
+;
+  entry:
+  %loc.bc = bitcast <1 x i8 addrspace(4)*> addrspace(4)* %loc to i8 addrspace(4)*
+  call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8 7, i64 8, i1 false)
+  %ref = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* %loc
+  ret <1 x i8 addrspace(4)*> %ref
+}
+
+
+; Can forward since we can do so w/o breaking types
+define i8 addrspace(4)* @forward_memset_zero(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @forward_memset_zero(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8 0, i64 8, i1 false)
+; CHECK-NEXT:    ret i8 addrspace(4)* null
+;
+  entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
+  call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8 0, i64 8, i1 false)
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
+  ret i8 addrspace(4)* %ref
+}
+
+; Can't forward as the load might be dead.  (Pretend we wrote out the alwaysfalse idiom above.)
+define i8 addrspace(4)* @neg_forward_store(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_forward_store(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i64 addrspace(4)*
+; CHECK-NEXT:    store i64 5, i64 addrspace(4)* [[LOC_BC]], align 8
+; CHECK-NEXT:    [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], align 8
+; CHECK-NEXT:    ret i8 addrspace(4)* [[REF]]
+;
+  entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i64 addrspace(4)*
+  store i64 5, i64 addrspace(4)* %loc.bc
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
+  ret i8 addrspace(4)* %ref
+}
+
+define <1 x i8 addrspace(4)*> @neg_forward_store_vload(<1 x i8 addrspace(4)*> addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_forward_store_vload(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast <1 x i8 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i64 addrspace(4)*
+; CHECK-NEXT:    store i64 5, i64 addrspace(4)* [[LOC_BC]], align 8
+; CHECK-NEXT:    [[REF:%.*]] = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* [[LOC]], align 8
+; CHECK-NEXT:    ret <1 x i8 addrspace(4)*> [[REF]]
+;
+  entry:
+  %loc.bc = bitcast <1 x i8 addrspace(4)*> addrspace(4)* %loc to i64 addrspace(4)*
+  store i64 5, i64 addrspace(4)* %loc.bc
+  %ref = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* %loc
+  ret <1 x i8 addrspace(4)*> %ref
+}
+
+; Nulls have known bit patterns, so we can forward
+define i8 addrspace(4)* @forward_store_zero(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @forward_store_zero(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i64 addrspace(4)*
+; CHECK-NEXT:    store i64 0, i64 addrspace(4)* [[LOC_BC]], align 8
+; CHECK-NEXT:    ret i8 addrspace(4)* null
+;
+  entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i64 addrspace(4)*
+  store i64 0, i64 addrspace(4)* %loc.bc
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
+  ret i8 addrspace(4)* %ref
+}
+
+; Nulls have known bit patterns, so we can forward
+define i8 addrspace(4)* @forward_store_zero2(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @forward_store_zero2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i32> addrspace(4)*
+; CHECK-NEXT:    store <2 x i32> zeroinitializer, <2 x i32> addrspace(4)* [[LOC_BC]], align 8
+; CHECK-NEXT:    ret i8 addrspace(4)* null
+;
+  entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i32> addrspace(4)*
+  store <2 x i32> zeroinitializer, <2 x i32> addrspace(4)* %loc.bc
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
+  ret i8 addrspace(4)* %ref
+}
+
+
+
+@NonZeroConstant = constant <4 x i64> <i64 3, i64 3, i64 3, i64 3>
+@NonZeroConstant2 = constant <4 x i64 addrspace(4)*> <
+  i64 addrspace(4)* getelementptr (i64, i64 addrspace(4)* null, i32 3),
+  i64 addrspace(4)* getelementptr (i64, i64 addrspace(4)* null, i32 3),
+  i64 addrspace(4)* getelementptr (i64, i64 addrspace(4)* null, i32 3),
+  i64 addrspace(4)* getelementptr (i64, i64 addrspace(4)* null, i32 3)>
+@ZeroConstant = constant <4 x i64> zeroinitializer
+
+
+; Can't forward as the load might be dead.  (Pretend we wrote out the alwaysfalse idiom above.)
+define i8 addrspace(4)* @neg_forward_memcopy(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_forward_memcopy(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @NonZeroConstant to i8*), i64 8, i1 false)
+; CHECK-NEXT:    [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], align 8
+; CHECK-NEXT:    ret i8 addrspace(4)* [[REF]]
+;
+entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
+  %src.bc = bitcast <4 x i64>* @NonZeroConstant to i8*
+  call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false)
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
+  ret i8 addrspace(4)* %ref
+}
+
+define i64 addrspace(4)* @neg_forward_memcopy2(i64 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_forward_memcopy2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i64 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @NonZeroConstant to i8*), i64 8, i1 false)
+; CHECK-NEXT:    [[REF:%.*]] = load i64 addrspace(4)*, i64 addrspace(4)* addrspace(4)* [[LOC]], align 8
+; CHECK-NEXT:    ret i64 addrspace(4)* [[REF]]
+;
+entry:
+  %loc.bc = bitcast i64 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
+  %src.bc = bitcast <4 x i64>* @NonZeroConstant to i8*
+  call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false)
+  %ref = load i64 addrspace(4)*, i64 addrspace(4)* addrspace(4)* %loc
+  ret i64 addrspace(4)* %ref
+}
+
+; TODO: missed optimization
+define i8 addrspace(4)* @forward_memcopy(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @forward_memcopy(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64 addrspace(4)*>* @NonZeroConstant2 to i8*), i64 8, i1 false)
+; CHECK-NEXT:    [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], align 8
+; CHECK-NEXT:    ret i8 addrspace(4)* [[REF]]
+;
+entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
+  %src.bc = bitcast <4 x i64 addrspace(4)*>* @NonZeroConstant2 to i8*
+  call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false)
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
+  ret i8 addrspace(4)* %ref
+}
+
+define i64 addrspace(4)* @forward_memcopy2(i64 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @forward_memcopy2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i64 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64 addrspace(4)*>* @NonZeroConstant2 to i8*), i64 8, i1 false)
+; CHECK-NEXT:    ret i64 addrspace(4)* getelementptr (i64, i64 addrspace(4)* null, i32 3)
+;
+entry:
+  %loc.bc = bitcast i64 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
+  %src.bc = bitcast <4 x i64 addrspace(4)*>* @NonZeroConstant2 to i8*
+  call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false)
+  %ref = load i64 addrspace(4)*, i64 addrspace(4)* addrspace(4)* %loc
+  ret i64 addrspace(4)* %ref
+}
+
+define <1 x i8 addrspace(4)*> @neg_forward_memcpy_vload(<1 x i8 addrspace(4)*> addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_forward_memcpy_vload(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast <1 x i8 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @NonZeroConstant to i8*), i64 8, i1 false)
+; CHECK-NEXT:    [[REF:%.*]] = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* [[LOC]], align 8
+; CHECK-NEXT:    ret <1 x i8 addrspace(4)*> [[REF]]
+;
+entry:
+  %loc.bc = bitcast <1 x i8 addrspace(4)*> addrspace(4)* %loc to i8 addrspace(4)*
+  %src.bc = bitcast <4 x i64>* @NonZeroConstant to i8*
+  call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false)
+  %ref = load <1 x i8 addrspace(4)*>, <1 x i8 addrspace(4)*> addrspace(4)* %loc
+  ret <1 x i8 addrspace(4)*> %ref
+}
+
+define <4 x i64 addrspace(4)*> @neg_forward_memcpy_vload2(<4 x i64 addrspace(4)*> addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_forward_memcpy_vload2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast <4 x i64 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @NonZeroConstant to i8*), i64 32, i1 false)
+; CHECK-NEXT:    [[REF:%.*]] = load <4 x i64 addrspace(4)*>, <4 x i64 addrspace(4)*> addrspace(4)* [[LOC]], align 32
+; CHECK-NEXT:    ret <4 x i64 addrspace(4)*> [[REF]]
+;
+entry:
+  %loc.bc = bitcast <4 x i64 addrspace(4)*> addrspace(4)* %loc to i8 addrspace(4)*
+  %src.bc = bitcast <4 x i64>* @NonZeroConstant to i8*
+  call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 32, i1 false)
+  %ref = load <4 x i64 addrspace(4)*>, <4 x i64 addrspace(4)*> addrspace(4)* %loc
+  ret <4 x i64 addrspace(4)*> %ref
+}
+
+define <4 x i64> @neg_forward_memcpy_vload3(<4 x i64> addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_forward_memcpy_vload3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast <4 x i64> addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64 addrspace(4)*>* @NonZeroConstant2 to i8*), i64 32, i1 false)
+; CHECK-NEXT:    [[REF:%.*]] = load <4 x i64>, <4 x i64> addrspace(4)* [[LOC]], align 32
+; CHECK-NEXT:    ret <4 x i64> [[REF]]
+;
+entry:
+  %loc.bc = bitcast <4 x i64> addrspace(4)* %loc to i8 addrspace(4)*
+  %src.bc = bitcast <4 x i64 addrspace(4)*>* @NonZeroConstant2 to i8*
+  call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 32, i1 false)
+  %ref = load <4 x i64>, <4 x i64> addrspace(4)* %loc
+  ret <4 x i64> %ref
+}
+
+define <1 x i64 addrspace(4)*> @forward_memcpy_vload3(<4 x i64 addrspace(4)*> addrspace(4)* %loc) {
+; CHECK-LABEL: @forward_memcpy_vload3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast <4 x i64 addrspace(4)*> addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64 addrspace(4)*>* @NonZeroConstant2 to i8*), i64 32, i1 false)
+; CHECK-NEXT:    ret <1 x i64 addrspace(4)*> <i64 addrspace(4)* getelementptr (i64, i64 addrspace(4)* null, i32 3)>
+;
+entry:
+  %loc.bc = bitcast <4 x i64 addrspace(4)*> addrspace(4)* %loc to i8 addrspace(4)*
+  %src.bc = bitcast <4 x i64 addrspace(4)*>* @NonZeroConstant2 to i8*
+  call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 32, i1 false)
+  %ref = load <4 x i64 addrspace(4)*>, <4 x i64 addrspace(4)*> addrspace(4)* %loc
+  %val = extractelement <4 x i64 addrspace(4)*> %ref, i32 0
+  %ret = insertelement <1 x i64 addrspace(4)*> poison, i64 addrspace(4)* %val, i32 0
+  ret <1 x i64 addrspace(4)*> %ret
+}
+
+; Can forward since we can do so w/o breaking types
+define i8 addrspace(4)* @forward_memcpy_zero(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @forward_memcpy_zero(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to i8 addrspace(4)*
+; CHECK-NEXT:    call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 [[LOC_BC]], i8* bitcast (<4 x i64>* @ZeroConstant to i8*), i64 8, i1 false)
+; CHECK-NEXT:    ret i8 addrspace(4)* null
+;
+entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to i8 addrspace(4)*
+  %src.bc = bitcast <4 x i64>* @ZeroConstant to i8*
+  call void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* align 4 %loc.bc, i8* %src.bc, i64 8, i1 false)
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc
+  ret i8 addrspace(4)* %ref
+}
+
+declare void @llvm.memcpy.p4i8.p0i8.i64(i8 addrspace(4)* nocapture, i8* nocapture, i64, i1) nounwind
+
+
+; Same as the neg_forward_store cases, but for non defs.
+; (Pretend we wrote out the alwaysfalse idiom above.)
+define i8 addrspace(4)* @neg_store_clobber(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_store_clobber(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i64> addrspace(4)*
+; CHECK-NEXT:    store <2 x i64> <i64 4, i64 4>, <2 x i64> addrspace(4)* [[LOC_BC]], align 16
+; CHECK-NEXT:    [[LOC_OFF:%.*]] = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], i64 1
+; CHECK-NEXT:    [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC_OFF]], align 8
+; CHECK-NEXT:    ret i8 addrspace(4)* [[REF]]
+;
+entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i64> addrspace(4)*
+  store <2 x i64> <i64 4, i64 4>, <2 x i64> addrspace(4)* %loc.bc
+  %loc.off = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc, i64 1
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc.off
+  ret i8 addrspace(4)* %ref
+}
+
+declare void @use(<2 x i64>) inaccessiblememonly
+
+; Same as the neg_forward_store cases, but for non defs.
+; (Pretend we wrote out the alwaysfalse idiom above.)
+define i8 addrspace(4)* @neg_load_clobber(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @neg_load_clobber(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i64> addrspace(4)*
+; CHECK-NEXT:    [[V:%.*]] = load <2 x i64>, <2 x i64> addrspace(4)* [[LOC_BC]], align 16
+; CHECK-NEXT:    call void @use(<2 x i64> [[V]])
+; CHECK-NEXT:    [[LOC_OFF:%.*]] = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], i64 1
+; CHECK-NEXT:    [[REF:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC_OFF]], align 8
+; CHECK-NEXT:    ret i8 addrspace(4)* [[REF]]
+;
+entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i64> addrspace(4)*
+  %v = load <2 x i64>, <2 x i64> addrspace(4)* %loc.bc
+  call void @use(<2 x i64> %v)
+  %loc.off = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc, i64 1
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc.off
+  ret i8 addrspace(4)* %ref
+}
+
+define i8 addrspace(4)* @store_clobber_zero(i8 addrspace(4)* addrspace(4)* %loc) {
+; CHECK-LABEL: @store_clobber_zero(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)* addrspace(4)* [[LOC:%.*]] to <2 x i64> addrspace(4)*
+; CHECK-NEXT:    store <2 x i64> zeroinitializer, <2 x i64> addrspace(4)* [[LOC_BC]], align 16
+; CHECK-NEXT:    [[LOC_OFF:%.*]] = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* [[LOC]], i64 1
+; CHECK-NEXT:    ret i8 addrspace(4)* null
+;
+entry:
+  %loc.bc = bitcast i8 addrspace(4)* addrspace(4)* %loc to <2 x i64> addrspace(4)*
+  store <2 x i64> zeroinitializer, <2 x i64> addrspace(4)* %loc.bc
+  %loc.off = getelementptr i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc, i64 1
+  %ref = load i8 addrspace(4)*, i8 addrspace(4)* addrspace(4)* %loc.off
+  ret i8 addrspace(4)* %ref
+}
+
+
+define void @smaller_vector(i8* %p) {
+; CHECK-LABEL: @smaller_vector(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = bitcast i8* [[P:%.*]] to <4 x i64 addrspace(4)*>*
+; CHECK-NEXT:    [[B:%.*]] = bitcast i8* [[P]] to <2 x i64 addrspace(4)*>*
+; CHECK-NEXT:    [[V4:%.*]] = load <4 x i64 addrspace(4)*>, <4 x i64 addrspace(4)*>* [[A]], align 32
+; CHECK-NEXT:    [[V2:%.*]] = load <2 x i64 addrspace(4)*>, <2 x i64 addrspace(4)*>* [[B]], align 32
+; CHECK-NEXT:    call void @use.v2(<2 x i64 addrspace(4)*> [[V2]])
+; CHECK-NEXT:    call void @use.v4(<4 x i64 addrspace(4)*> [[V4]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = bitcast i8* %p to <4 x i64 addrspace(4)*>*
+  %b = bitcast i8* %p to <2 x i64 addrspace(4)*>*
+  %v4 = load <4 x i64 addrspace(4)*>, <4 x i64 addrspace(4)*>* %a, align 32
+  %v2 = load <2 x i64 addrspace(4)*>, <2 x i64 addrspace(4)*>* %b, align 32
+  call void @use.v2(<2 x i64 addrspace(4)*> %v2)
+  call void @use.v4(<4 x i64 addrspace(4)*> %v4)
+  ret void
+}
+
+define i64 addrspace(4)* @vector_extract(i8* %p) {
+; CHECK-LABEL: @vector_extract(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = bitcast i8* [[P:%.*]] to <4 x i64 addrspace(4)*>*
+; CHECK-NEXT:    [[B:%.*]] = bitcast i8* [[P]] to i64 addrspace(4)**
+; CHECK-NEXT:    [[V4:%.*]] = load <4 x i64 addrspace(4)*>, <4 x i64 addrspace(4)*>* [[A]], align 32
+; CHECK-NEXT:    [[RES:%.*]] = load i64 addrspace(4)*, i64 addrspace(4)** [[B]], align 32
+; CHECK-NEXT:    call void @use.v4(<4 x i64 addrspace(4)*> [[V4]])
+; CHECK-NEXT:    ret i64 addrspace(4)* [[RES]]
+;
+entry:
+  %a = bitcast i8* %p to <4 x i64 addrspace(4)*>*
+  %b = bitcast i8* %p to i64 addrspace(4)**
+  %v4 = load <4 x i64 addrspace(4)*>, <4 x i64 addrspace(4)*>* %a, align 32
+  %res = load i64 addrspace(4)*, i64 addrspace(4)** %b, align 32
+  call void @use.v4(<4 x i64 addrspace(4)*> %v4)
+  ret i64 addrspace(4)* %res
+}
+
+declare void @use.v2(<2 x i64 addrspace(4)*>)
+declare void @use.v4(<4 x i64 addrspace(4)*>)
+ define i8 addrspace(5)* @multini(i1 %alwaysFalse, i8 addrspace(4)* %val, i8 addrspace(4)** %loc) {
+; CHECK-LABEL: @multini(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    store i8 addrspace(4)* [[VAL:%.*]], i8 addrspace(4)** [[LOC:%.*]], align 8
+; CHECK-NEXT:    br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
+; CHECK:       neverTaken:
+; CHECK-NEXT:    [[LOC_BC:%.*]] = bitcast i8 addrspace(4)** [[LOC]] to i8 addrspace(5)**
+; CHECK-NEXT:    [[DIFFERENTAS:%.*]] = load i8 addrspace(5)*, i8 addrspace(5)** [[LOC_BC]], align 8
+; CHECK-NEXT:    ret i8 addrspace(5)* [[DIFFERENTAS]]
+; CHECK:       alwaysTaken:
+; CHECK-NEXT:    ret i8 addrspace(5)* null
+;
+  entry:
+  store i8 addrspace(4)* %val, i8 addrspace(4)** %loc
+  br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
+
+  neverTaken:
+  %loc.bc = bitcast i8 addrspace(4)** %loc to i8 addrspace(5)**
+  %differentas = load i8 addrspace(5)*, i8 addrspace(5)** %loc.bc
+  ret i8 addrspace(5)* %differentas
+
+  alwaysTaken:
+  ret i8 addrspace(5)* null
+  }
diff --git a/llvm/test/Transforms/IROutliner/outlining-commutative-fp.ll b/llvm/test/Transforms/IROutliner/outlining-commutative-fp.ll
new file mode 100644
index 0000000000000..35d8d27dab0f1
--- /dev/null
+++ b/llvm/test/Transforms/IROutliner/outlining-commutative-fp.ll
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -verify -iroutliner < %s | FileCheck %s
+
+; This test checks that floating point commutative instructions are not treated
+; as commutative.  Even though an ffadd is technically commutative, the order
+; of operands still needs to be enforced since the process of fadding floating
+; point values requires the order to be the same.
+
+; We make sure that we outline the identical regions from the first two
+; functions, but not the third.  this is because the operands are in a different
+; order in a floating point instruction in this section.
+
+define void @outline_from_fadd1() {
+; CHECK-LABEL: @outline_from_fadd1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca double, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca double, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca double, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_0(double* [[A]], double* [[B]], double* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca double, align 4
+  %b = alloca double, align 4
+  %c = alloca double, align 4
+  store double 2.0, double* %a, align 4
+  store double 3.0, double* %b, align 4
+  store double 4.0, double* %c, align 4
+  %al = load double, double* %a
+  %bl = load double, double* %b
+  %cl = load double, double* %c
+  %0 = fadd double %al, %bl
+  %1 = fadd double %al, %cl
+  %2 = fadd double %bl, %cl
+  ret void
+}
+
+define void @outline_from_fadd2.0() {
+; CHECK-LABEL: @outline_from_fadd2.0(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca double, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca double, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca double, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_0(double* [[A]], double* [[B]], double* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca double, align 4
+  %b = alloca double, align 4
+  %c = alloca double, align 4
+  store double 2.0, double* %a, align 4
+  store double 3.0, double* %b, align 4
+  store double 4.0, double* %c, align 4
+  %al = load double, double* %a
+  %bl = load double, double* %b
+  %cl = load double, double* %c
+  %0 = fadd double %al, %bl
+  %1 = fadd double %al, %cl
+  %2 = fadd double %bl, %cl
+  ret void
+}
+
+define void @outline_from_flipped_fadd3.0() {
+; CHECK-LABEL: @outline_from_flipped_fadd3.0(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca double, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca double, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca double, align 4
+; CHECK-NEXT:    store double 2.000000e+00, double* [[A]], align 4
+; CHECK-NEXT:    store double 3.000000e+00, double* [[B]], align 4
+; CHECK-NEXT:    store double 4.000000e+00, double* [[C]], align 4
+; CHECK-NEXT:    [[AL:%.*]] = load double, double* [[A]], align 8
+; CHECK-NEXT:    [[BL:%.*]] = load double, double* [[B]], align 8
+; CHECK-NEXT:    [[CL:%.*]] = load double, double* [[C]], align 8
+; CHECK-NEXT:    [[TMP0:%.*]] = fadd double [[BL]], [[AL]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd double [[CL]], [[AL]]
+; CHECK-NEXT:    [[TMP2:%.*]] = fadd double [[CL]], [[BL]]
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca double, align 4
+  %b = alloca double, align 4
+  %c = alloca double, align 4
+  store double 2.0, double* %a, align 4
+  store double 3.0, double* %b, align 4
+  store double 4.0, double* %c, align 4
+  %al = load double, double* %a
+  %bl = load double, double* %b
+  %cl = load double, double* %c
+  %0 = fadd double %bl, %al
+  %1 = fadd double %cl, %al
+  %2 = fadd double %cl, %bl
+  ret void
+}
+
+; CHECK: define internal void @outlined_ir_func_0(double* [[ARG0:%.*]], double* [[ARG1:%.*]], double* [[ARG2:%.*]]) #0 {
+; CHECK: entry_to_outline:
+; CHECK-NEXT:    store double 2.000000e+00, double* [[ARG0]], align 4
+; CHECK-NEXT:    store double 3.000000e+00, double* [[ARG1]], align 4
+; CHECK-NEXT:    store double 4.000000e+00, double* [[ARG2]], align 4
+; CHECK-NEXT:    [[AL:%.*]] = load double, double* [[ARG0]], align 8
+; CHECK-NEXT:    [[BL:%.*]] = load double, double* [[ARG1]], align 8
+; CHECK-NEXT:    [[CL:%.*]] = load double, double* [[ARG2]], align 8
+; CHECK-NEXT:    [[TMP0:%.*]] = fadd double [[AL]], [[BL]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd double [[AL]], [[CL]]
+; CHECK-NEXT:    [[TMP2:%.*]] = fadd double [[BL]], [[CL]]
+
diff --git a/llvm/test/Transforms/IROutliner/outlining-commutative.ll b/llvm/test/Transforms/IROutliner/outlining-commutative.ll
new file mode 100644
index 0000000000000..c52792910cc56
--- /dev/null
+++ b/llvm/test/Transforms/IROutliner/outlining-commutative.ll
@@ -0,0 +1,254 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -verify -iroutliner < %s | FileCheck %s
+
+; This test checks that commutative instructions where the operands are
+; swapped are outlined as the same function.
+
+; It also checks that non-commutative instructions outlined as different
+; functions when the operands are swapped;
+
+; These are identical functions, except that in the flipped functions,
+; the operands in the adds are commuted.  However, since add instructions
+; are commutative, we should still outline from all four as the same
+; instruction.
+
+define void @outline_from_add1() {
+; CHECK-LABEL: @outline_from_add1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  store i32 4, i32* %c, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %cl = load i32, i32* %c
+  %0 = add i32 %al, %bl
+  %1 = add i32 %al, %cl
+  %2 = add i32 %bl, %cl
+  ret void
+}
+
+define void @outline_from_add2() {
+; CHECK-LABEL: @outline_from_add2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  store i32 4, i32* %c, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %cl = load i32, i32* %c
+  %0 = add i32 %al, %bl
+  %1 = add i32 %al, %cl
+  %2 = add i32 %bl, %cl
+  ret void
+}
+
+define void @outline_from_flipped_add3() {
+; CHECK-LABEL: @outline_from_flipped_add3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  store i32 4, i32* %c, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %cl = load i32, i32* %c
+  %0 = add i32 %bl, %al
+  %1 = add i32 %cl, %al
+  %2 = add i32 %cl, %bl
+  ret void
+}
+
+define void @outline_from_flipped_add4() {
+; CHECK-LABEL: @outline_from_flipped_add4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  store i32 4, i32* %c, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %cl = load i32, i32* %c
+  %0 = add i32 %bl, %al
+  %1 = add i32 %cl, %al
+  %2 = add i32 %cl, %bl
+  ret void
+}
+
+; These are identical functions, except that in the flipped functions,
+; the operands in the subtractions are commuted.  Since subtraction
+; instructions are not commutative, we should outline the first two functions
+; differently than the second two functions.
+
+define void @outline_from_sub1() {
+; CHECK-LABEL: @outline_from_sub1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_2(i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  store i32 4, i32* %c, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %cl = load i32, i32* %c
+  %0 = sub i32 %al, %bl
+  %1 = sub i32 %al, %cl
+  %2 = sub i32 %bl, %cl
+  ret void
+}
+
+define void @outline_from_sub2() {
+; CHECK-LABEL: @outline_from_sub2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_2(i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  store i32 4, i32* %c, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %cl = load i32, i32* %c
+  %0 = sub i32 %al, %bl
+  %1 = sub i32 %al, %cl
+  %2 = sub i32 %bl, %cl
+  ret void
+}
+
+define void @dontoutline_from_flipped_sub3() {
+; CHECK-LABEL: @dontoutline_from_flipped_sub3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_1(i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  store i32 4, i32* %c, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %cl = load i32, i32* %c
+  %0 = sub i32 %bl, %al
+  %1 = sub i32 %cl, %al
+  %2 = sub i32 %cl, %bl
+  ret void
+}
+
+define void @dontoutline_from_flipped_sub4() {
+; CHECK-LABEL: @dontoutline_from_flipped_sub4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_1(i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  %c = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  store i32 4, i32* %c, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %cl = load i32, i32* %c
+  %0 = sub i32 %bl, %al
+  %1 = sub i32 %cl, %al
+  %2 = sub i32 %cl, %bl
+  ret void
+}
+
+; CHECK: define internal void @outlined_ir_func_0(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2:%.*]]) #0 {
+; CHECK: entry_to_outline:
+; CHECK-NEXT:    store i32 2, i32* [[ARG0]], align 4
+; CHECK-NEXT:    store i32 3, i32* [[ARG1]], align 4
+; CHECK-NEXT:    store i32 4, i32* [[ARG2]], align 4
+; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[ARG0]], align 4
+; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[ARG1]], align 4
+; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[ARG2]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[AL]], [[BL]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[AL]], [[CL]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[BL]], [[CL]]
+
+; CHECK: define internal void @outlined_ir_func_1(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2:%.*]]) #0 {
+; CHECK: entry_to_outline:
+; CHECK-NEXT:    store i32 2, i32* [[ARG0]], align 4
+; CHECK-NEXT:    store i32 3, i32* [[ARG1]], align 4
+; CHECK-NEXT:    store i32 4, i32* [[ARG2]], align 4
+; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[ARG0]], align 4
+; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[ARG1]], align 4
+; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[ARG2]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 [[BL]], [[AL]]
+; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[CL]], [[AL]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sub i32 [[CL]], [[BL]]
+
+; CHECK: define internal void @outlined_ir_func_2(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2:%.*]]) #0 {
+; CHECK: entry_to_outline:
+; CHECK-NEXT:    store i32 2, i32* [[ARG0]], align 4
+; CHECK-NEXT:    store i32 3, i32* [[ARG1]], align 4
+; CHECK-NEXT:    store i32 4, i32* [[ARG2]], align 4
+; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[ARG0]], align 4
+; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[ARG1]], align 4
+; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[ARG2]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 [[AL]], [[BL]]
+; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[AL]], [[CL]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sub i32 [[BL]], [[CL]]
diff --git a/llvm/test/Transforms/IROutliner/outlining-constants-vs-registers.ll b/llvm/test/Transforms/IROutliner/outlining-constants-vs-registers.ll
index 7f57ecdb10c32..6809a396404d2 100644
--- a/llvm/test/Transforms/IROutliner/outlining-constants-vs-registers.ll
+++ b/llvm/test/Transforms/IROutliner/outlining-constants-vs-registers.ll
@@ -15,14 +15,10 @@ define void @function_registers_first(i32 %0, i32 %1, i32 %2) {
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
-; CHECK-NEXT:    store i32 [[TMP0:%.*]], i32* [[A]], align 4
-; CHECK-NEXT:    store i32 [[TMP1:%.*]], i32* [[B]], align 4
-; CHECK-NEXT:    store i32 [[TMP2:%.*]], i32* [[C]], align 4
+; CHECK-NEXT:    call void @outlined_ir_func_1(i32 [[TMP0:%.*]], i32* [[A]], i32 [[TMP1:%.*]], i32* [[B]], i32 [[TMP2:%.*]], i32* [[C]])
 ; CHECK-NEXT:    ret void
 ; CHECK:       next:
-; CHECK-NEXT:    store i32 2, i32* [[A]], align 4
-; CHECK-NEXT:    store i32 3, i32* [[B]], align 4
-; CHECK-NEXT:    store i32 4, i32* [[C]], align 4
+; CHECK-NEXT:    call void @outlined_ir_func_1(i32 2, i32* [[A]], i32 3, i32* [[B]], i32 4, i32* [[C]])
 ; CHECK-NEXT:    ret void
 ;
 entry:
@@ -40,7 +36,7 @@ next:
   ret void
 }
 
-define void @function_with_constants_first() {
+define void @function_with_constants_first(i32 %0, i32 %1, i32 %2) {
 ; CHECK-LABEL: @function_with_constants_first(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
@@ -49,14 +45,10 @@ define void @function_with_constants_first() {
 ; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[A]], align 4
 ; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[B]], align 4
 ; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[C]], align 4
-; CHECK-NEXT:    [[TMP0:%.*]] = add i32 2, [[AL]]
-; CHECK-NEXT:    [[TMP1:%.*]] = add i32 3, [[BL]]
-; CHECK-NEXT:    [[TMP2:%.*]] = add i32 4, [[CL]]
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32 2, i32 [[AL]], i32 3, i32 [[BL]], i32 4, i32 [[CL]])
 ; CHECK-NEXT:    ret void
 ; CHECK:       next:
-; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[TMP0]], [[AL]]
-; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[TMP1]], [[BL]]
-; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP2]], [[CL]]
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32 [[TMP0:%.*]], i32 [[AL]], i32 [[TMP1:%.*]], i32 [[BL]], i32 [[TMP2:%.*]], i32 [[CL]])
 ; CHECK-NEXT:    ret void
 ;
 entry:
@@ -66,13 +58,25 @@ entry:
   %al = load i32, i32* %a
   %bl = load i32, i32* %b
   %cl = load i32, i32* %c
-  %0 = add i32 2, %al
-  %1 = add i32 3, %bl
-  %2 = add i32 4, %cl
+  %3 = add i32 2, %al
+  %4 = add i32 3, %bl
+  %5 = add i32 4, %cl
   ret void
 next:
-  %3 = add i32 %0, %al
-  %4 = add i32 %1, %bl
-  %5 = add i32 %2, %cl
+  %6 = add i32 %0, %al
+  %7 = add i32 %1, %bl
+  %8 = add i32 %2, %cl
   ret void
 }
+
+; CHECK: define internal void @outlined_ir_func_0(i32 [[ARG0:%.*]], i32 [[ARG1:%.*]], i32 [[ARG2:%.*]], i32 [[ARG3:%.*]], i32 [[ARG4:%.*]], i32 [[ARG5:%.*]])
+; CHECK: entry_to_outline:
+; CHECK-NEXT: add i32 [[ARG0]], [[ARG1]]
+; CHECK-NEXT: add i32 [[ARG2]], [[ARG3]]
+; CHECK-NEXT: add i32 [[ARG4]], [[ARG5]]
+
+; CHECK: define internal void @outlined_ir_func_1(i32 [[ARG0:%.*]], i32* [[ARG1:%.*]], i32 [[ARG2:%.*]], i32* [[ARG3:%.*]], i32 [[ARG4:%.*]], i32* [[ARG5:%.*]])
+; CHECK: entry_to_outline:
+; CHECK-NEXT: store i32 [[ARG0]], i32* [[ARG1]]
+; CHECK-NEXT: store i32 [[ARG2]], i32* [[ARG3]]
+; CHECK-NEXT: store i32 [[ARG4]], i32* [[ARG5]]
diff --git a/llvm/test/Transforms/IROutliner/outlining-different-constants.ll b/llvm/test/Transforms/IROutliner/outlining-different-constants.ll
index d5937cae76ee6..c81f7f62c38cf 100644
--- a/llvm/test/Transforms/IROutliner/outlining-different-constants.ll
+++ b/llvm/test/Transforms/IROutliner/outlining-different-constants.ll
@@ -2,8 +2,7 @@
 ; RUN: opt -S -verify -iroutliner < %s | FileCheck %s
 
 ; This test looks at the constants in the regions, and if it they are the
-; differents it does not outline them as they cannot be consolidated into the
-; the same function.
+; differents it elevates the constants to arguments.
 
 define void @outline_constants1() {
 ; CHECK-LABEL: @outline_constants1(
@@ -11,10 +10,7 @@ define void @outline_constants1() {
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
-; CHECK-NEXT:    store i32 3, i32* [[A]], align 4
-; CHECK-NEXT:    store i32 4, i32* [[B]], align 4
-; CHECK-NEXT:    store i32 5, i32* [[C]], align 4
-; CHECK-NEXT:    call void @[[FUNCTION_0:.*]](i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32 3, i32* [[A]], i32 4, i32* [[B]], i32 5, i32* [[C]])
 ; CHECK-NEXT:    ret void
 ;
 entry:
@@ -36,10 +32,7 @@ define void @outline_constants2() {
 ; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
 ; CHECK-NEXT:    [[C:%.*]] = alloca i32, align 4
-; CHECK-NEXT:    store i32 2, i32* [[A]], align 4
-; CHECK-NEXT:    store i32 3, i32* [[B]], align 4
-; CHECK-NEXT:    store i32 4, i32* [[C]], align 4
-; CHECK-NEXT:    call void @[[FUNCTION_0]](i32* [[A]], i32* [[B]], i32* [[C]])
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32 2, i32* [[A]], i32 3, i32* [[B]], i32 4, i32* [[C]])
 ; CHECK-NEXT:    ret void
 ;
 entry:
@@ -55,8 +48,11 @@ entry:
   ret void
 }
 
-; CHECK: define internal void @[[FUNCTION_0]](i32* [[ARG0:%.*]], i32* [[ARG1:%.*]], i32* [[ARG2:%.*]])
+; CHECK: define internal void @outlined_ir_func_0(i32 [[ARG0:%.*]], i32* [[ARG1:%.*]], i32 [[ARG2:%.*]], i32* [[ARG3:%.*]], i32 [[ARG4:%.*]], i32* [[ARG5:%.*]]) #0 {
 ; CHECK: entry_to_outline:
-; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[ARG0]], align 4
-; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[ARG1]], align 4
-; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[ARG2]], align 4
+; CHECK-NEXT:    store i32 [[ARG0]], i32* [[ARG1]], align 4
+; CHECK-NEXT:    store i32 [[ARG2]], i32* [[ARG3]], align 4
+; CHECK-NEXT:    store i32 [[ARG4]], i32* [[ARG5]], align 4
+; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[ARG1]], align 4
+; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[ARG3]], align 4
+; CHECK-NEXT:    [[CL:%.*]] = load i32, i32* [[ARG5]], align 4
diff --git a/llvm/test/Transforms/IROutliner/outlining-different-globals.ll b/llvm/test/Transforms/IROutliner/outlining-different-globals.ll
index 84134fcdf7ef2..4624bb53f230b 100644
--- a/llvm/test/Transforms/IROutliner/outlining-different-globals.ll
+++ b/llvm/test/Transforms/IROutliner/outlining-different-globals.ll
@@ -12,9 +12,7 @@
 define void @outline_globals1() {
 ; CHECK-LABEL: @outline_globals1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* @global1, align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* @global2, align 4
-; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32* @global1, i32* @global2)
 ; CHECK-NEXT:    ret void
 ;
 entry:
@@ -27,9 +25,7 @@ entry:
 define void @outline_globals2() {
 ; CHECK-LABEL: @outline_globals2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* @global3, align 4
-; CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* @global4, align 4
-; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[TMP0]], [[TMP1]]
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32* @global3, i32* @global4)
 ; CHECK-NEXT:    ret void
 ;
 entry:
@@ -38,3 +34,9 @@ entry:
   %2 = add i32 %0, %1
   ret void
 }
+
+; CHECK: define internal void @outlined_ir_func_0(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]])
+; CHECK: entry_to_outline:
+; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[ARG0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* [[ARG1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[TMP0]], [[TMP1]]
diff --git a/llvm/test/Transforms/IROutliner/outlining-isomorphic-predicates.ll b/llvm/test/Transforms/IROutliner/outlining-isomorphic-predicates.ll
new file mode 100644
index 0000000000000..16233beff87c9
--- /dev/null
+++ b/llvm/test/Transforms/IROutliner/outlining-isomorphic-predicates.ll
@@ -0,0 +1,170 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -verify -iroutliner < %s | FileCheck %s
+
+; This test checks the isomorphic comparisons can be outlined together into one
+; function.
+
+; The following three function are identical, except that in the third, the
+; operand order, and predicate are swapped, meaning it is structurally the same
+; and should be outlined together.
+
+define void @outline_slt1() {
+; CHECK-LABEL: @outline_slt1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_1(i32* [[A]], i32* [[B]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %0 = icmp slt i32 %al, %bl
+  ret void
+}
+
+define void @outline_slt2() {
+; CHECK-LABEL: @outline_slt2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_1(i32* [[A]], i32* [[B]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %0 = icmp slt i32 %al, %bl
+  ret void
+}
+
+define void @outline_sgt() {
+; CHECK-LABEL: @outline_sgt(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_1(i32* [[A]], i32* [[B]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %0 = icmp sgt i32 %bl, %al
+  ret void
+}
+
+; This has a swapped predicate, but not swapped operands, so it cannot use
+; the same outlined function as the ones above.
+
+define void @dontoutline_sgt() {
+; CHECK-LABEL: @dontoutline_sgt(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    store i32 2, i32* [[A]], align 4
+; CHECK-NEXT:    store i32 3, i32* [[B]], align 4
+; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[A]], align 4
+; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[B]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i32 [[AL]], [[BL]]
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %0 = icmp sgt i32 %al, %bl
+  ret void
+}
+
+; The below functions use a different kind of predicate that is not compatible
+; with the ones above, and should use a different outlined function.
+; The other difference here is that the predicate with swapped operands comes
+; first this time.
+
+define void @outline_ugt1() {
+; CHECK-LABEL: @outline_ugt1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %0 = icmp ugt i32 %al, %bl
+  ret void
+}
+
+define void @outline_ugt2() {
+; CHECK-LABEL: @outline_ugt2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %0 = icmp ugt i32 %al, %bl
+  ret void
+}
+
+define void @outline_ult() {
+; CHECK-LABEL: @outline_ult(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[A:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    [[B:%.*]] = alloca i32, align 4
+; CHECK-NEXT:    call void @outlined_ir_func_0(i32* [[A]], i32* [[B]])
+; CHECK-NEXT:    ret void
+;
+entry:
+  %a = alloca i32, align 4
+  %b = alloca i32, align 4
+  store i32 2, i32* %a, align 4
+  store i32 3, i32* %b, align 4
+  %al = load i32, i32* %a
+  %bl = load i32, i32* %b
+  %0 = icmp ult i32 %bl, %al
+  ret void
+}
+
+; CHECK: define internal void @outlined_ir_func_0(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]]) #0 {
+; CHECK: entry_to_outline:
+; CHECK-NEXT:    store i32 2, i32* [[ARG0]], align 4
+; CHECK-NEXT:    store i32 3, i32* [[ARG1]], align 4
+; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[ARG0]], align 4
+; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[ARG1]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp ugt i32 [[AL]], [[BL]]
+
+; CHECK: define internal void @outlined_ir_func_1(i32* [[ARG0:%.*]], i32* [[ARG1:%.*]]) #0 {
+; CHECK: entry_to_outline:
+; CHECK-NEXT:    store i32 2, i32* [[ARG0]], align 4
+; CHECK-NEXT:    store i32 3, i32* [[ARG1]], align 4
+; CHECK-NEXT:    [[AL:%.*]] = load i32, i32* [[ARG0]], align 4
+; CHECK-NEXT:    [[BL:%.*]] = load i32, i32* [[ARG1]], align 4
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp slt i32 [[AL]], [[BL]]
diff --git a/llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll b/llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll
index a100f7b4e8222..e86277adf9369 100644
--- a/llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll
+++ b/llvm/test/Transforms/IndVarSimplify/X86/pr45360.ll
@@ -21,29 +21,29 @@ define dso_local i32 @main() {
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    [[I6:%.*]] = load i32, i32* @a, align 4
 ; CHECK-NEXT:    [[I24:%.*]] = load i32, i32* @b, align 4
-; CHECK-NEXT:    [[D_PROMOTED8:%.*]] = load i32, i32* @d, align 4
-; CHECK-NEXT:    br label [[BB19:%.*]]
-; CHECK:       bb19:
-; CHECK-NEXT:    [[I8_LCSSA9:%.*]] = phi i32 [ [[D_PROMOTED8]], [[BB:%.*]] ], [ [[I8:%.*]], [[BB27:%.*]] ]
-; CHECK-NEXT:    [[I8]] = and i32 [[I8_LCSSA9]], [[I6]]
+; CHECK-NEXT:    [[D_PROMOTED9:%.*]] = load i32, i32* @d, align 4
+; CHECK-NEXT:    br label [[BB1:%.*]]
+; CHECK:       bb1:
+; CHECK-NEXT:    [[I8_LCSSA10:%.*]] = phi i32 [ [[D_PROMOTED9]], [[BB:%.*]] ], [ [[I8:%.*]], [[BB19_PREHEADER:%.*]] ]
+; CHECK-NEXT:    [[I8]] = and i32 [[I8_LCSSA10]], [[I6]]
 ; CHECK-NEXT:    [[I21:%.*]] = icmp eq i32 [[I8]], 0
-; CHECK-NEXT:    br i1 [[I21]], label [[BB27_THREAD:%.*]], label [[BB27]]
-; CHECK:       bb27.thread:
+; CHECK-NEXT:    br i1 [[I21]], label [[BB13_PREHEADER_BB27_THREAD_SPLIT_CRIT_EDGE:%.*]], label [[BB19_PREHEADER]]
+; CHECK:       bb19.preheader:
+; CHECK-NEXT:    [[I26:%.*]] = urem i32 [[I24]], [[I8]]
+; CHECK-NEXT:    store i32 [[I26]], i32* @e, align 4
+; CHECK-NEXT:    [[I30_NOT:%.*]] = icmp eq i32 [[I26]], 0
+; CHECK-NEXT:    br i1 [[I30_NOT]], label [[BB32_LOOPEXIT:%.*]], label [[BB1]]
+; CHECK:       bb13.preheader.bb27.thread.split_crit_edge:
 ; CHECK-NEXT:    store i32 -1, i32* @f, align 4
 ; CHECK-NEXT:    store i32 0, i32* @d, align 4
 ; CHECK-NEXT:    store i32 0, i32* @c, align 4
 ; CHECK-NEXT:    br label [[BB32:%.*]]
-; CHECK:       bb27:
-; CHECK-NEXT:    [[I26:%.*]] = urem i32 [[I24]], [[I8]]
-; CHECK-NEXT:    store i32 [[I26]], i32* @e, align 4
-; CHECK-NEXT:    [[I30:%.*]] = icmp eq i32 [[I26]], 0
-; CHECK-NEXT:    br i1 [[I30]], label [[BB32_LOOPEXIT:%.*]], label [[BB19]]
 ; CHECK:       bb32.loopexit:
 ; CHECK-NEXT:    store i32 -1, i32* @f, align 4
 ; CHECK-NEXT:    store i32 [[I8]], i32* @d, align 4
 ; CHECK-NEXT:    br label [[BB32]]
 ; CHECK:       bb32:
-; CHECK-NEXT:    [[C_SINK:%.*]] = phi i32* [ @c, [[BB32_LOOPEXIT]] ], [ @e, [[BB27_THREAD]] ]
+; CHECK-NEXT:    [[C_SINK:%.*]] = phi i32* [ @c, [[BB32_LOOPEXIT]] ], [ @e, [[BB13_PREHEADER_BB27_THREAD_SPLIT_CRIT_EDGE]] ]
 ; CHECK-NEXT:    store i32 0, i32* [[C_SINK]], align 4
 ; CHECK-NEXT:    ret i32 0
 ;
diff --git a/llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regressions-inseltpoison.ll b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regressions-inseltpoison.ll
new file mode 100644
index 0000000000000..e0bf4f1058f9e
--- /dev/null
+++ b/llvm/test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regressions-inseltpoison.ll
@@ -0,0 +1,143 @@
+; RUN: opt -data-layout=A5 -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
+
+; Regression tests from old HSAIL addrspacecast optimization pass
+
+@data = internal addrspace(1) global [100 x double] [double 0.00, double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, double 5.000000e-01, double 6.000000e-01, double 7.000000e-01, double 8.000000e-01, double 9.000000e-01, double 1.00, double 1.10, double 1.20, double 1.30, double 1.40, double 1.50, double 1.60, double 1.70, double 1.80, double 1.90, double 2.00, double 2.10, double 2.20, double 2.30, double 2.40, double 2.50, double 2.60, double 2.70, double 2.80, double 2.90, double 3.00, double 3.10, double 3.20, double 3.30, double 3.40, double 3.50, double 3.60, double 3.70, double 3.80, double 3.90, double 4.00, double 4.10, double 4.20, double 4.30, double 4.40, double 4.50, double 4.60, double 4.70, double 4.80, double 4.90, double 5.00, double 5.10, double 5.20, double 5.30, double 5.40, double 5.50, double 5.60, double 5.70, double 5.80, double 5.90, double 6.00, double 6.10, double 6.20, double 6.30, double 6.40, double 6.50, double 6.60, double 6.70, double 6.80, double 6.90, double 7.00, double 7.10, double 7.20, double 7.30, double 7.40, double 7.50, double 7.60, double 7.70, double 7.80, double 7.90, double 8.00, double 8.10, double 8.20, double 8.30, double 8.40, double 8.50, double 8.60, double 8.70, double 8.80, double 8.90, double 9.00, double 9.10, double 9.20, double 9.30, double 9.40, double 9.50, double 9.60, double 9.70, double 9.80, double 9.90], align 8
+
+
+; Should generate flat load
+
+; CHECK-LABEL: @generic_address_bitcast_const(
+; CHECK: %vecload1 = load <2 x double>, <2 x double> addrspace(1)* bitcast (double addrspace(1)* getelementptr inbounds ([100 x double], [100 x double] addrspace(1)* @data, i64 0, i64 4) to <2 x double> addrspace(1)*), align 8
+define amdgpu_kernel void @generic_address_bitcast_const(i64 %arg0, i32 addrspace(1)* nocapture %results) #0 {
+entry:
+  %tmp1 = call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp2 = zext i32 %tmp1 to i64
+  %tmp3 = add i64 %tmp2, %arg0
+  %vecload1 = load <2 x double>, <2 x double>* bitcast (double* getelementptr ([100 x double], [100 x double]* addrspacecast ([100 x double] addrspace(1)* @data to [100 x double]*), i64 0, i64 4) to <2 x double>*), align 8
+  %cmp = fcmp ord <2 x double> %vecload1, zeroinitializer
+  %sext = sext <2 x i1> %cmp to <2 x i64>
+  %tmp4 = extractelement <2 x i64> %sext, i64 0
+  %tmp5 = extractelement <2 x i64> %sext, i64 1
+  %tmp6 = and i64 %tmp4, %tmp5
+  %tmp7 = lshr i64 %tmp6, 63
+  %tmp8 = trunc i64 %tmp7 to i32
+  %idxprom = and i64 %tmp3, 4294967295
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %results, i64 %idxprom
+  store i32 %tmp8, i32 addrspace(1)* %arrayidx, align 4
+  ret void
+}
+
+@generic_address_bug9749.val = internal addrspace(1) global float 0.0, align 4
+
+declare i32 @_Z9get_fencePv(i8*)
+%opencl.pipe_t = type opaque
+
+; This is a compile time assert bug, but we still want to check optimization
+; is performed to generate ld_global.
+; CHECK-LABEL: @generic_address_pipe_bug9673(
+; CHECK: %tmp1 = bitcast %opencl.pipe_t addrspace(3)* %in_pipe to i32 addrspace(3)*
+; CHECK: %add.ptr = getelementptr inbounds i32, i32 addrspace(3)* %tmp1, i32 2
+; CHECK: %tmp2 = load i32, i32 addrspace(3)* %add.ptr, align 4
+define amdgpu_kernel void @generic_address_pipe_bug9673(%opencl.pipe_t addrspace(3)* nocapture %in_pipe, i32 addrspace(1)* nocapture %dst) #0 {
+entry:
+  %tmp = call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp1 = bitcast %opencl.pipe_t addrspace(3)* %in_pipe to i32 addrspace(3)*
+  %add.ptr = getelementptr inbounds i32, i32 addrspace(3)* %tmp1, i32 2
+  %tmp2 = load i32, i32 addrspace(3)* %add.ptr, align 4
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %dst, i32 %tmp
+  store i32 %tmp2, i32 addrspace(1)* %arrayidx, align 4
+  ret void
+}
+
+; Should generate flat load
+; CHECK-LABEL: @generic_address_bug9749(
+; CHECK: br i1
+; CHECK: load float, float*
+; CHECK: br label
+define amdgpu_kernel void @generic_address_bug9749(i32 addrspace(1)* nocapture %results) #0 {
+entry:
+  %ptr = alloca float*, align 8, addrspace(5)
+  %tmp = call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp1 = zext i32 %tmp to i64
+  store float 0x3FB99999A0000000, float addrspace(1)* @generic_address_bug9749.val, align 4
+  store volatile float* addrspacecast (float addrspace(1)* @generic_address_bug9749.val to float*), float* addrspace(5)* %ptr, align 8
+  %tmp2 = load volatile float*, float* addrspace(5)* %ptr, align 8
+  %tmp3 = load float, float addrspace(1)* @generic_address_bug9749.val, align 4
+  %tmp4 = bitcast float* %tmp2 to i8*
+  %call.i = call i32 @_Z9get_fencePv(i8* %tmp4) #1
+  %switch.i.i = icmp ult i32 %call.i, 4
+  br i1 %switch.i.i, label %if.end.i, label %helperFunction.exit
+
+if.end.i:                                         ; preds = %entry
+  %tmp5 = load float, float* %tmp2, align 4
+  %not.cmp.i = fcmp oeq float %tmp5, %tmp3
+  %phitmp = zext i1 %not.cmp.i to i32
+  br label %helperFunction.exit
+
+helperFunction.exit:                              ; preds = %if.end.i, %entry
+  %retval.0.i = phi i32 [ 0, %entry ], [ %phitmp, %if.end.i ]
+  %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %results, i64 %tmp1
+  store i32 %retval.0.i, i32 addrspace(1)* %arrayidx, align 4
+  ret void
+}
+
+; CHECK-LABEL: @generic_address_opt_phi_bug9776_simple_phi_kernel(
+; CHECK: phi i32 addrspace(3)*
+; CHECK: store i32 %i.03, i32 addrspace(3)* %
+define amdgpu_kernel void @generic_address_opt_phi_bug9776_simple_phi_kernel(i32 addrspace(3)* nocapture %in, i32 %numElems) #0 {
+entry:
+  %cmp1 = icmp eq i32 %numElems, 0
+  br i1 %cmp1, label %for.end, label %for.body.lr.ph
+
+for.body.lr.ph:                                   ; preds = %entry
+  %tmp = addrspacecast i32 addrspace(3)* %in to i32*
+  br label %for.body
+
+for.body:                                         ; preds = %for.body, %for.body.lr.ph
+  %i.03 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
+  %ptr.02 = phi i32* [ %tmp, %for.body.lr.ph ], [ %add.ptr, %for.body ]
+  store i32 %i.03, i32* %ptr.02, align 4
+  %add.ptr = getelementptr inbounds i32, i32* %ptr.02, i64 4
+  %inc = add nuw i32 %i.03, 1
+  %exitcond = icmp eq i32 %inc, %numElems
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+; CHECK-LABEL: @generic_address_bug9899(
+; CHECK: %vecload = load <2 x i32>, <2 x i32> addrspace(3)*
+; CHECK: store <2 x i32> %tmp16, <2 x i32> addrspace(3)*
+define amdgpu_kernel void @generic_address_bug9899(i64 %arg0, i32 addrspace(3)* nocapture %sourceA, i32 addrspace(3)* nocapture %destValues) #0 {
+entry:
+  %tmp1 = call i32 @llvm.amdgcn.workitem.id.x()
+  %tmp2 = zext i32 %tmp1 to i64
+  %tmp3 = add i64 %tmp2, %arg0
+  %sext = shl i64 %tmp3, 32
+  %tmp4 = addrspacecast i32 addrspace(3)* %destValues to i32*
+  %tmp5 = addrspacecast i32 addrspace(3)* %sourceA to i32*
+  %tmp6 = ashr exact i64 %sext, 31
+  %tmp7 = getelementptr inbounds i32, i32* %tmp5, i64 %tmp6
+  %arrayidx_v4 = bitcast i32* %tmp7 to <2 x i32>*
+  %vecload = load <2 x i32>, <2 x i32>* %arrayidx_v4, align 4
+  %tmp8 = extractelement <2 x i32> %vecload, i32 0
+  %tmp9 = extractelement <2 x i32> %vecload, i32 1
+  %tmp10 = icmp eq i32 %tmp8, 0
+  %tmp11 = select i1 %tmp10, i32 32, i32 %tmp8
+  %tmp12 = icmp eq i32 %tmp9, 0
+  %tmp13 = select i1 %tmp12, i32 32, i32 %tmp9
+  %tmp14 = getelementptr inbounds i32, i32* %tmp4, i64 %tmp6
+  %tmp15 = insertelement <2 x i32> poison, i32 %tmp11, i32 0
+  %tmp16 = insertelement <2 x i32> %tmp15, i32 %tmp13, i32 1
+  %arrayidx_v41 = bitcast i32* %tmp14 to <2 x i32>*
+  store <2 x i32> %tmp16, <2 x i32>* %arrayidx_v41, align 4
+  ret void
+}
+
+declare i32 @llvm.amdgcn.workitem.id.x() #2
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly }
+attributes #2 = { nounwind readnone }
diff --git a/llvm/test/Transforms/InferFunctionAttrs/dereferenceable-inseltpoison.ll b/llvm/test/Transforms/InferFunctionAttrs/dereferenceable-inseltpoison.ll
new file mode 100644
index 0000000000000..ac3245e8a86c0
--- /dev/null
+++ b/llvm/test/Transforms/InferFunctionAttrs/dereferenceable-inseltpoison.ll
@@ -0,0 +1,357 @@
+; RUN: opt < %s -inferattrs -S | FileCheck %s
+
+
+
+; Determine dereference-ability before unused loads get deleted:
+; https://bugs.llvm.org/show_bug.cgi?id=21780
+
+define <4 x double> @PR21780(double* %ptr) {
+; CHECK-LABEL: @PR21780(double* %ptr)
+
+  ; GEP of index 0 is simplified away.
+  %arrayidx1 = getelementptr inbounds double, double* %ptr, i64 1
+  %arrayidx2 = getelementptr inbounds double, double* %ptr, i64 2
+  %arrayidx3 = getelementptr inbounds double, double* %ptr, i64 3
+
+  %t0 = load double, double* %ptr, align 8
+  %t1 = load double, double* %arrayidx1, align 8
+  %t2 = load double, double* %arrayidx2, align 8
+  %t3 = load double, double* %arrayidx3, align 8
+
+  %vecinit0 = insertelement <4 x double> poison, double %t0, i32 0
+  %vecinit1 = insertelement <4 x double> %vecinit0, double %t1, i32 1
+  %vecinit2 = insertelement <4 x double> %vecinit1, double %t2, i32 2
+  %vecinit3 = insertelement <4 x double> %vecinit2, double %t3, i32 3
+  %shuffle = shufflevector <4 x double> %vecinit3, <4 x double> %vecinit3, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
+  ret <4 x double> %shuffle
+}
+
+
+define double @PR21780_only_access3_with_inbounds(double* %ptr) {
+; CHECK-LABEL: @PR21780_only_access3_with_inbounds(double* %ptr)
+
+  %arrayidx3 = getelementptr inbounds double, double* %ptr, i64 3
+  %t3 = load double, double* %arrayidx3, align 8
+  ret double %t3
+}
+
+define double @PR21780_only_access3_without_inbounds(double* %ptr) {
+; CHECK-LABEL: @PR21780_only_access3_without_inbounds(double* %ptr)
+  %arrayidx3 = getelementptr double, double* %ptr, i64 3
+  %t3 = load double, double* %arrayidx3, align 8
+  ret double %t3
+}
+
+define double @PR21780_without_inbounds(double* %ptr) {
+; CHECK-LABEL: @PR21780_without_inbounds(double* %ptr)
+
+  %arrayidx1 = getelementptr double, double* %ptr, i64 1
+  %arrayidx2 = getelementptr double, double* %ptr, i64 2
+  %arrayidx3 = getelementptr double, double* %ptr, i64 3
+
+  %t0 = load double, double* %ptr, align 8
+  %t1 = load double, double* %arrayidx1, align 8
+  %t2 = load double, double* %arrayidx2, align 8
+  %t3 = load double, double* %arrayidx3, align 8
+
+  ret double %t3
+}
+
+; Unsimplified, but still valid. Also, throw in some bogus arguments.
+
+define void @gep0(i8* %unused, i8* %other, i8* %ptr) {
+; CHECK-LABEL: @gep0(i8* %unused, i8* %other, i8* %ptr)
+  %arrayidx0 = getelementptr i8, i8* %ptr, i64 0
+  %arrayidx1 = getelementptr i8, i8* %ptr, i64 1
+  %arrayidx2 = getelementptr i8, i8* %ptr, i64 2
+  %t0 = load i8, i8* %arrayidx0
+  %t1 = load i8, i8* %arrayidx1
+  %t2 = load i8, i8* %arrayidx2
+  store i8 %t2, i8* %other
+  ret void
+}
+
+; Order of accesses does not change computation.
+; Multiple arguments may be dereferenceable.
+
+define void @ordering(i8* %ptr1, i32* %ptr2) {
+; CHECK-LABEL: @ordering(i8* %ptr1, i32* %ptr2)
+  %a20 = getelementptr i32, i32* %ptr2, i64 0
+  %a12 = getelementptr i8, i8* %ptr1, i64 2
+  %t12 = load i8, i8* %a12
+  %a11 = getelementptr i8, i8* %ptr1, i64 1
+  %t20 = load i32, i32* %a20
+  %a10 = getelementptr i8, i8* %ptr1, i64 0
+  %t10 = load i8, i8* %a10
+  %t11 = load i8, i8* %a11
+  %a21 = getelementptr i32, i32* %ptr2, i64 1
+  %t21 = load i32, i32* %a21
+  ret void
+}
+
+; Not in entry block.
+
+define void @not_entry_but_guaranteed_to_execute(i8* %ptr) {
+; CHECK-LABEL: @not_entry_but_guaranteed_to_execute(i8* %ptr)
+entry:
+  br label %exit
+exit:
+  %arrayidx0 = getelementptr i8, i8* %ptr, i64 0
+  %arrayidx1 = getelementptr i8, i8* %ptr, i64 1
+  %arrayidx2 = getelementptr i8, i8* %ptr, i64 2
+  %t0 = load i8, i8* %arrayidx0
+  %t1 = load i8, i8* %arrayidx1
+  %t2 = load i8, i8* %arrayidx2
+  ret void
+}
+
+; Not in entry block and not guaranteed to execute.
+
+define void @not_entry_not_guaranteed_to_execute(i8* %ptr, i1 %cond) {
+; CHECK-LABEL: @not_entry_not_guaranteed_to_execute(i8* %ptr, i1 %cond)
+entry:
+  br i1 %cond, label %loads, label %exit
+loads:
+  %arrayidx0 = getelementptr i8, i8* %ptr, i64 0
+  %arrayidx1 = getelementptr i8, i8* %ptr, i64 1
+  %arrayidx2 = getelementptr i8, i8* %ptr, i64 2
+  %t0 = load i8, i8* %arrayidx0
+  %t1 = load i8, i8* %arrayidx1
+  %t2 = load i8, i8* %arrayidx2
+  ret void
+exit:
+  ret void
+}
+
+; The last load may not execute, so derefenceable bytes only covers the 1st two loads.
+
+define void @partial_in_entry(i16* %ptr, i1 %cond) {
+; CHECK-LABEL: @partial_in_entry(i16* %ptr, i1 %cond)
+entry:
+  %arrayidx0 = getelementptr i16, i16* %ptr, i64 0
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t0 = load i16, i16* %arrayidx0
+  %t1 = load i16, i16* %arrayidx1
+  br i1 %cond, label %loads, label %exit
+loads:
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+exit:
+  ret void
+}
+
+; The volatile load can't be used to prove a non-volatile access is allowed.
+; The 2nd and 3rd loads may never execute.
+
+define void @volatile_is_not_dereferenceable(i16* %ptr) {
+; CHECK-LABEL: @volatile_is_not_dereferenceable(i16* %ptr)
+  %arrayidx0 = getelementptr i16, i16* %ptr, i64 0
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t0 = load volatile i16, i16* %arrayidx0
+  %t1 = load i16, i16* %arrayidx1
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+}
+
+; TODO: We should allow inference for atomic (but not volatile) ops.
+
+define void @atomic_is_alright(i16* %ptr) {
+; CHECK-LABEL: @atomic_is_alright(i16* %ptr)
+  %arrayidx0 = getelementptr i16, i16* %ptr, i64 0
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t0 = load atomic i16, i16* %arrayidx0 unordered, align 2
+  %t1 = load i16, i16* %arrayidx1
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+}
+
+declare void @may_not_return()
+
+define void @not_guaranteed_to_transfer_execution(i16* %ptr) {
+; CHECK-LABEL: @not_guaranteed_to_transfer_execution(i16* %ptr)
+  %arrayidx0 = getelementptr i16, i16* %ptr, i64 0
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t0 = load i16, i16* %arrayidx0
+  call void @may_not_return()
+  %t1 = load i16, i16* %arrayidx1
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+}
+
+; We must have consecutive accesses.
+
+define void @variable_gep_index(i8* %unused, i8* %ptr, i64 %variable_index) {
+; CHECK-LABEL: @variable_gep_index(i8* %unused, i8* %ptr, i64 %variable_index)
+  %arrayidx1 = getelementptr i8, i8* %ptr, i64 %variable_index
+  %arrayidx2 = getelementptr i8, i8* %ptr, i64 2
+  %t0 = load i8, i8* %ptr
+  %t1 = load i8, i8* %arrayidx1
+  %t2 = load i8, i8* %arrayidx2
+  ret void
+}
+
+; Deal with >1 GEP index.
+
+define void @multi_index_gep(<4 x i8>* %ptr) {
+; CHECK-LABEL: @multi_index_gep(<4 x i8>* %ptr)
+; FIXME: %ptr should be dereferenceable(4)
+  %arrayidx00 = getelementptr <4 x i8>, <4 x i8>* %ptr, i64 0, i64 0
+  %t0 = load i8, i8* %arrayidx00
+  ret void
+}
+
+; Could round weird bitwidths down?
+
+define void @not_byte_multiple(i9* %ptr) {
+; CHECK-LABEL: @not_byte_multiple(i9* %ptr)
+  %arrayidx0 = getelementptr i9, i9* %ptr, i64 0
+  %t0 = load i9, i9* %arrayidx0
+  ret void
+}
+
+; Missing direct access from the pointer.
+
+define void @no_pointer_deref(i16* %ptr) {
+; CHECK-LABEL: @no_pointer_deref(i16* %ptr)
+  %arrayidx1 = getelementptr i16, i16* %ptr, i64 1
+  %arrayidx2 = getelementptr i16, i16* %ptr, i64 2
+  %t1 = load i16, i16* %arrayidx1
+  %t2 = load i16, i16* %arrayidx2
+  ret void
+}
+
+; Out-of-order is ok, but missing access concludes dereferenceable range.
+
+define void @non_consecutive(i32* %ptr) {
+; CHECK-LABEL: @non_consecutive(i32* %ptr)
+  %arrayidx1 = getelementptr i32, i32* %ptr, i64 1
+  %arrayidx0 = getelementptr i32, i32* %ptr, i64 0
+  %arrayidx3 = getelementptr i32, i32* %ptr, i64 3
+  %t1 = load i32, i32* %arrayidx1
+  %t0 = load i32, i32* %arrayidx0
+  %t3 = load i32, i32* %arrayidx3
+  ret void
+}
+
+; Improve on existing dereferenceable attribute.
+
+define void @more_bytes(i32* dereferenceable(8) %ptr) {
+; CHECK-LABEL: @more_bytes(i32* dereferenceable(8) %ptr)
+  %arrayidx3 = getelementptr i32, i32* %ptr, i64 3
+  %arrayidx1 = getelementptr i32, i32* %ptr, i64 1
+  %arrayidx0 = getelementptr i32, i32* %ptr, i64 0
+  %arrayidx2 = getelementptr i32, i32* %ptr, i64 2
+  %t3 = load i32, i32* %arrayidx3
+  %t1 = load i32, i32* %arrayidx1
+  %t2 = load i32, i32* %arrayidx2
+  %t0 = load i32, i32* %arrayidx0
+  ret void
+}
+
+; Improve on existing dereferenceable_or_null attribute.
+
+define void @more_bytes_and_not_null(i32* dereferenceable_or_null(8) %ptr) {
+; CHECK-LABEL: @more_bytes_and_not_null(i32* dereferenceable_or_null(8) %ptr)
+  %arrayidx3 = getelementptr i32, i32* %ptr, i64 3
+  %arrayidx1 = getelementptr i32, i32* %ptr, i64 1
+  %arrayidx0 = getelementptr i32, i32* %ptr, i64 0
+  %arrayidx2 = getelementptr i32, i32* %ptr, i64 2
+  %t3 = load i32, i32* %arrayidx3
+  %t1 = load i32, i32* %arrayidx1
+  %t2 = load i32, i32* %arrayidx2
+  %t0 = load i32, i32* %arrayidx0
+  ret void
+}
+
+; But don't pessimize existing dereferenceable attribute.
+
+define void @better_bytes(i32* dereferenceable(100) %ptr) {
+; CHECK-LABEL: @better_bytes(i32* dereferenceable(100) %ptr)
+  %arrayidx3 = getelementptr i32, i32* %ptr, i64 3
+  %arrayidx1 = getelementptr i32, i32* %ptr, i64 1
+  %arrayidx0 = getelementptr i32, i32* %ptr, i64 0
+  %arrayidx2 = getelementptr i32, i32* %ptr, i64 2
+  %t3 = load i32, i32* %arrayidx3
+  %t1 = load i32, i32* %arrayidx1
+  %t2 = load i32, i32* %arrayidx2
+  %t0 = load i32, i32* %arrayidx0
+  ret void
+}
+
+define void @bitcast(i32* %arg) {
+; CHECK-LABEL: @bitcast(i32* %arg)
+  %ptr = bitcast i32* %arg to float*
+  %arrayidx0 = getelementptr float, float* %ptr, i64 0
+  %arrayidx1 = getelementptr float, float* %ptr, i64 1
+  %t0 = load float, float* %arrayidx0
+  %t1 = load float, float* %arrayidx1
+  ret void
+}
+
+define void @bitcast_different_sizes(double* %arg1, i8* %arg2) {
+; CHECK-LABEL: @bitcast_different_sizes(double* %arg1, i8* %arg2)
+  %ptr1 = bitcast double* %arg1 to float*
+  %a10 = getelementptr float, float* %ptr1, i64 0
+  %a11 = getelementptr float, float* %ptr1, i64 1
+  %a12 = getelementptr float, float* %ptr1, i64 2
+  %ld10 = load float, float* %a10
+  %ld11 = load float, float* %a11
+  %ld12 = load float, float* %a12
+
+  %ptr2 = bitcast i8* %arg2 to i64*
+  %a20 = getelementptr i64, i64* %ptr2, i64 0
+  %a21 = getelementptr i64, i64* %ptr2, i64 1
+  %ld20 = load i64, i64* %a20
+  %ld21 = load i64, i64* %a21
+  ret void
+}
+
+define void @negative_offset(i32* %arg) {
+; CHECK-LABEL: @negative_offset(i32* %arg)
+  %ptr = bitcast i32* %arg to float*
+  %arrayidx0 = getelementptr float, float* %ptr, i64 0
+  %arrayidx1 = getelementptr float, float* %ptr, i64 -1
+  %t0 = load float, float* %arrayidx0
+  %t1 = load float, float* %arrayidx1
+  ret void
+}
+
+define void @stores(i32* %arg) {
+; CHECK-LABEL: @stores(i32* %arg)
+  %ptr = bitcast i32* %arg to float*
+  %arrayidx0 = getelementptr float, float* %ptr, i64 0
+  %arrayidx1 = getelementptr float, float* %ptr, i64 1
+  store float 1.0, float* %arrayidx0
+  store float 2.0, float* %arrayidx1
+  ret void
+}
+
+define void @load_store(i32* %arg) {
+; CHECK-LABEL: @load_store(i32* %arg)
+  %ptr = bitcast i32* %arg to float*
+  %arrayidx0 = getelementptr float, float* %ptr, i64 0
+  %arrayidx1 = getelementptr float, float* %ptr, i64 1
+  %t1 = load float, float* %arrayidx0
+  store float 2.0, float* %arrayidx1
+  ret void
+}
+
+define void @different_size1(i32* %arg) {
+; CHECK-LABEL: @different_size1(i32* %arg)
+  %arg-cast = bitcast i32* %arg to double*
+  store double 0.000000e+00, double* %arg-cast
+  store i32 0, i32* %arg
+  ret void
+}
+
+define void @different_size2(i32* %arg) {
+; CHECK-LABEL: @different_size2(i32* %arg)
+  store i32 0, i32* %arg
+  %arg-cast = bitcast i32* %arg to double*
+  store double 0.000000e+00, double* %arg-cast
+  ret void
+}
diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-bitcast-inseltpoison.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-bitcast-inseltpoison.ll
new file mode 100644
index 0000000000000..d0cc892b0e692
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/AArch64/sve-bitcast-inseltpoison.ll
@@ -0,0 +1,13 @@
+; RUN: opt -instcombine -mtriple=aarch64-linux-gnu -mattr=+sve -S < %s | FileCheck %s
+
+; We shouldn't fold bitcast(insert <vscale x 1 x iX> .., iX %val, i32 0)
+; into bitcast(iX %val) for scalable vectors.
+define <vscale x 2 x i8> @bitcast_of_insert_i8_i16(i16 %val) #0 {
+; CHECK-LABEL: @bitcast_of_insert_i8_i16(
+; CHECK-NOT:   bitcast i16 %val to <vscale x 2 x i8>
+; CHECK:       bitcast <vscale x 1 x i16> %op2 to <vscale x 2 x i8>
+entry:
+  %op2 = insertelement <vscale x 1 x i16> poison, i16 %val, i32 0
+  %0 = bitcast <vscale x 1 x i16> %op2 to <vscale x 2 x i8>
+  ret <vscale x 2 x i8> %0
+}
diff --git a/llvm/test/Transforms/InstCombine/AArch64/tbl1.ll b/llvm/test/Transforms/InstCombine/AArch64/tbl1.ll
index 176e8d0a3dc34..42a346bc7e670 100644
--- a/llvm/test/Transforms/InstCombine/AArch64/tbl1.ll
+++ b/llvm/test/Transforms/InstCombine/AArch64/tbl1.ll
@@ -12,7 +12,7 @@ target triple = "aarch64-arm-none-eabi"
 define <8 x i8> @tbl1_8x8(<16 x i8> %vec) {
 ; CHECK-LABEL: @tbl1_8x8(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <16 x i8> [[VEC:%.*]], <16 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <16 x i8> [[VEC:%.*]], <16 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
 ; CHECK-NEXT:    ret <8 x i8> [[TMP0]]
 ;
 entry:
diff --git a/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
new file mode 100644
index 0000000000000..8363ed461f94a
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll
@@ -0,0 +1,3828 @@
+; RUN: opt -S -instcombine -mtriple=amdgcn-amd-amdhsa %s | FileCheck %s
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.buffer.load
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @buffer_load_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @buffer_load_f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  ret float %data
+}
+
+; CHECK-LABEL: @buffer_load_v1f32(
+; CHECK-NEXT: %data = call <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret <1 x float> %data
+define amdgpu_ps <1 x float> @buffer_load_v1f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  ret <1 x float> %data
+}
+
+; CHECK-LABEL: @buffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  ret <2 x float> %data
+}
+
+; CHECK-LABEL: @buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret <4 x float> %data
+define amdgpu_ps <4 x float> @buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  ret <4 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_buffer_load_v2f32(
+; CHECK: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_buffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt1 = extractelement <2 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_buffer_load_v4f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt1 = extractelement <4 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt1 = extractelement <4 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 3
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt3_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt1 = extractelement <4 x float> %data, i32 3
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt2_elt3_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt2_elt3_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_elt3_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt2_elt3_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_buffer_load_v4f32_2(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %elt0 = extractelement <2 x float> %data, i32 0
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: %ins0 = insertvalue { float, float } undef, float %elt0, 0
+; CHECK-NEXT: %ins1 = insertvalue { float, float } %ins0, float %elt1, 1
+; CHECK-NEXT: ret { float, float } %ins1
+define amdgpu_ps { float, float } @extract_elt0_elt1_buffer_load_v4f32_2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  %elt1 = extractelement <4 x float> %data, i32 1
+  %ins0 = insertvalue { float, float } undef, float %elt0, 0
+  %ins1 = insertvalue { float, float } %ins0, float %elt1, 1
+  ret { float, float } %ins1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_2(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %elt0 = extractelement <3 x float> %data, i32 0
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 1
+; CHECK-NEXT: %elt2 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: %ins0 = insertvalue { float, float, float } undef, float %elt0, 0
+; CHECK-NEXT: %ins1 = insertvalue { float, float, float } %ins0, float %elt1, 1
+; CHECK-NEXT: %ins2 = insertvalue { float, float, float } %ins1, float %elt2, 2
+; CHECK-NEXT: ret { float, float, float } %ins2
+define amdgpu_ps { float, float, float } @extract_elt0_elt1_elt2_buffer_load_v4f32_2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  %elt1 = extractelement <4 x float> %data, i32 1
+  %elt2 = extractelement <4 x float> %data, i32 2
+  %ins0 = insertvalue { float, float, float } undef, float %elt0, 0
+  %ins1 = insertvalue { float, float, float } %ins0, float %elt1, 1
+  %ins2 = insertvalue { float, float, float } %ins1, float %elt2, 2
+  ret { float, float, float } %ins2
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_3(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %ins1 = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 undef, i32 1>
+; CHECK-NEXT: %ret = fadd <2 x float> %ins1, %shuf
+define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_3(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  %elt2 = extractelement <4 x float> %data, i32 2
+  %ins0 = insertelement <2 x float> poison, float %elt0, i32 0
+  %ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 4, i32 1>
+  %ret = fadd <2 x float> %ins1, %shuf
+  ret <2 x float> %ret
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_4(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %ins1 = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 undef>
+; CHECK-NEXT: %ret = fadd <2 x float> %ins1, %shuf
+; CHECK-NEXT: ret <2 x float> %ret
+define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_4(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  %elt2 = extractelement <4 x float> %data, i32 2
+  %ins0 = insertelement <2 x float> poison, float %elt0, i32 0
+  %ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
+  %shuf = shufflevector <4 x float> undef, <4 x float> %data, <2 x i32> <i32 5, i32 1>
+  %ret = fadd <2 x float> %ins1, %shuf
+  ret <2 x float> %ret
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_5(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %ins1 = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 2, i32 2>
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT: %ret = fadd <2 x float> %ins1, %shuf
+define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_5(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt2 = extractelement <4 x float> %data, i32 2
+  %ins0 = insertelement <2 x float> poison, float %elt2, i32 0
+  %ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
+  %shuf = shufflevector <4 x float> %data, <4 x float> %data, <2 x i32> <i32 0, i32 5>
+  %ret = fadd <2 x float> %ins1, %shuf
+  ret <2 x float> %ret
+}
+
+; CHECK-LABEL: @extract_elt0_buffer_load_v3f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt0 = extractelement <3 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_buffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt1 = extractelement <3 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_buffer_load_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %elt1 = extractelement <3 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_buffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_buffer_load_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @preserve_metadata_extract_elt0_buffer_load_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false), !fpmath !0
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @preserve_metadata_extract_elt0_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false), !fpmath !0
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.buffer.load.format
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @buffer_load_format_v1f32(
+; CHECK-NEXT: %data = call <1 x float> @llvm.amdgcn.buffer.load.format.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 true)
+; CHECK-NEXT: ret <1 x float> %data
+define amdgpu_ps <1 x float> @buffer_load_format_v1f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <1 x float> @llvm.amdgcn.buffer.load.format.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 true)
+  ret <1 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_buffer_load_format_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 true, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 true, i1 false)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt0_elt1_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt0_elt1_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; The initial insertion point is at the extractelement
+; CHECK-LABEL: @extract01_bitcast_buffer_load_format_v4f32(
+; CHECK-NEXT: %tmp = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false)
+; CHECK-NEXT: %1 = shufflevector <2 x float> %tmp, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT: %tmp1 = bitcast <4 x float> %1 to <2 x double>
+; CHECK-NEXT: %tmp2 = extractelement <2 x double> %tmp1, i32 0
+; CHECK-NEXT: ret double %tmp2
+define double @extract01_bitcast_buffer_load_format_v4f32(i32 %arg) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false) #3
+  %tmp1 = bitcast <4 x float> %tmp to <2 x double>
+  %tmp2 = extractelement <2 x double> %tmp1, i32 0
+  ret double %tmp2
+}
+
+; CHECK-LABEL: @extract0_bitcast_buffer_load_format_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false)
+; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
+; CHECK-NEXT: ret i32 %tmp2
+define i32 @extract0_bitcast_buffer_load_format_v4f32(i32 %arg) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false) #3
+  %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
+  %tmp2 = extractelement <4 x i32> %tmp1, i32 0
+  ret i32 %tmp2
+}
+
+; CHECK-LABEL: @extract_lo16_0_bitcast_buffer_load_format_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false)
+; CHECK-NEXT: %1 = bitcast float %tmp to i32
+; CHECK-NEXT: %tmp2 = trunc i32 %1 to i16
+; CHECK-NEXT: ret i16 %tmp2
+define i16 @extract_lo16_0_bitcast_buffer_load_format_v4f32(i32 %arg) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %arg, i32 16, i1 false, i1 false) #3
+  %tmp1 = bitcast <4 x float> %tmp to <8 x i16>
+  %tmp2 = extractelement <8 x i16> %tmp1, i32 0
+  ret i16 %tmp2
+}
+
+declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <1 x float> @llvm.amdgcn.buffer.load.format.v1f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <3 x float> @llvm.amdgcn.buffer.load.format.v3f32(<4 x i32>, i32, i32, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.raw.buffer.load
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @raw_buffer_load_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @raw_buffer_load_f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  ret float %data
+}
+
+; CHECK-LABEL: @raw_buffer_load_v1f32(
+; CHECK-NEXT: %data = call <1 x float> @llvm.amdgcn.raw.buffer.load.v1f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <1 x float> %data
+define amdgpu_ps <1 x float> @raw_buffer_load_v1f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <1 x float> @llvm.amdgcn.raw.buffer.load.v1f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  ret <1 x float> %data
+}
+
+; CHECK-LABEL: @raw_buffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @raw_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  ret <2 x float> %data
+}
+
+; CHECK-LABEL: @raw_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <4 x float> %data
+define amdgpu_ps <4 x float> @raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  ret <4 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_raw_buffer_load_v2f32(
+; CHECK: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_raw_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_v2f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_raw_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <2 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_raw_buffer_load_v4f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_raw_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 8
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt2_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_raw_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 12
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt3_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 3
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_raw_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_raw_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt1_elt2_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt2_elt3_raw_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 8
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt2_elt3_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_raw_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_elt3_raw_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt2_elt3_raw_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_raw_buffer_load_v3f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_raw_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <3 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_v3f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_raw_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_raw_buffer_load_v3f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 8
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt2_raw_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_raw_buffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_raw_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_raw_buffer_load_v3f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt1_elt2_raw_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract0_bitcast_raw_buffer_load_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
+; CHECK-NEXT: ret i32 %tmp2
+define i32 @extract0_bitcast_raw_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
+  %tmp2 = extractelement <4 x i32> %tmp1, i32 0
+  ret i32 %tmp2
+}
+
+; CHECK-LABEL: @extract0_bitcast_raw_buffer_load_v4i32(
+; CHECK-NEXT: %tmp = call i32 @llvm.amdgcn.raw.buffer.load.i32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast i32 %tmp to float
+; CHECK-NEXT: ret float %tmp2
+define float @extract0_bitcast_raw_buffer_load_v4i32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %tmp = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %tmp1 = bitcast <4 x i32> %tmp to <4 x float>
+  %tmp2 = extractelement <4 x float> %tmp1, i32 0
+  ret float %tmp2
+}
+
+; CHECK-LABEL: @preserve_metadata_extract_elt0_raw_buffer_load_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0), !fpmath !0
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @preserve_metadata_extract_elt0_raw_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0), !fpmath !0
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32) #1
+declare <1 x float> @llvm.amdgcn.raw.buffer.load.v1f32(<4 x i32>, i32, i32, i32) #1
+declare <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32>, i32, i32, i32) #1
+declare <3 x float> @llvm.amdgcn.raw.buffer.load.v3f32(<4 x i32>, i32, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32>, i32, i32, i32) #1
+
+declare <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32>, i32, i32, i32) #1
+
+; CHECK-LABEL: @extract_elt0_raw_buffer_load_v2f16(
+; CHECK: %data = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt0_raw_buffer_load_v2f16(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <2 x half> %data, i32 0
+  ret half %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_v2f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 2
+; CHECK-NEXT: %data = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_raw_buffer_load_v2f16(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <2 x half> %data, i32 1
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_v3f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 2
+; CHECK-NEXT: %data = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_raw_buffer_load_v3f16(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x half> @llvm.amdgcn.raw.buffer.load.v3f16(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <3 x half> %data, i32 1
+  ret half %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_v4f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 2
+; CHECK-NEXT: %data = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_raw_buffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 1
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_raw_buffer_load_v4f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 6
+; CHECK-NEXT: %data = call half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt3_raw_buffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 3
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_raw_buffer_load_v4f16(
+; CHECK-NEXT: %data = call <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x half>
+define amdgpu_ps <2 x half> @extract_elt0_elt1_raw_buffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x half> %data, <4 x half> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x half> %shuf
+}
+
+declare half @llvm.amdgcn.raw.buffer.load.f16(<4 x i32>, i32, i32, i32) #1
+declare <2 x half> @llvm.amdgcn.raw.buffer.load.v2f16(<4 x i32>, i32, i32, i32) #1
+declare <3 x half> @llvm.amdgcn.raw.buffer.load.v3f16(<4 x i32>, i32, i32, i32) #1
+declare <4 x half> @llvm.amdgcn.raw.buffer.load.v4f16(<4 x i32>, i32, i32, i32) #1
+
+; CHECK-LABEL: @extract_elt0_raw_buffer_load_v2i8(
+; CHECK: %data = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt0_raw_buffer_load_v2i8(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x i8> @llvm.amdgcn.raw.buffer.load.v2i8(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <2 x i8> %data, i32 0
+  ret i8 %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_v2i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 1
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt1_raw_buffer_load_v2i8(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x i8> @llvm.amdgcn.raw.buffer.load.v2i8(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <2 x i8> %data, i32 1
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_v3i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 1
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt1_raw_buffer_load_v3i8(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x i8> @llvm.amdgcn.raw.buffer.load.v3i8(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <3 x i8> %data, i32 1
+  ret i8 %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_v4i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 1
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt1_raw_buffer_load_v4i8(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x i8> @llvm.amdgcn.raw.buffer.load.v4i8(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x i8> %data, i32 1
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_raw_buffer_load_v4i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 3
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt3_raw_buffer_load_v4i8(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x i8> @llvm.amdgcn.raw.buffer.load.v4i8(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x i8> %data, i32 3
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_raw_buffer_load_v4i8(
+; CHECK-NEXT: %data = call <2 x i8> @llvm.amdgcn.raw.buffer.load.v2i8(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x i8>
+define amdgpu_ps <2 x i8> @extract_elt0_elt1_raw_buffer_load_v4i8(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x i8> @llvm.amdgcn.raw.buffer.load.v4i8(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x i8> %data, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x i8> %shuf
+}
+
+declare i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32>, i32, i32, i32) #1
+declare <2 x i8> @llvm.amdgcn.raw.buffer.load.v2i8(<4 x i32>, i32, i32, i32) #1
+declare <3 x i8> @llvm.amdgcn.raw.buffer.load.v3i8(<4 x i32>, i32, i32, i32) #1
+declare <4 x i8> @llvm.amdgcn.raw.buffer.load.v4i8(<4 x i32>, i32, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.s.buffer.load
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @s_buffer_load_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @s_buffer_load_f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  ret float %data
+}
+
+; CHECK-LABEL: @s_buffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @s_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  ret <2 x float> %data
+}
+
+; CHECK-LABEL: @s_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret <4 x float> %data
+define amdgpu_ps <4 x float> @s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  ret <4 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_s_buffer_load_v2f32(
+; CHECK: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_s_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_s_buffer_load_v2f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_s_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <2 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_s_buffer_load_v4f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_s_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_s_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 8
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt2_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_s_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 12
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt3_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 3
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_s_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_s_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt1_elt2_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt2_elt3_s_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 8
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt2_elt3_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_s_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt2_elt3_s_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_s_buffer_load_v3f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_s_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt0 = extractelement <3 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_s_buffer_load_v3f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_s_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_s_buffer_load_v3f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 8
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt2_s_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_s_buffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_s_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_s_buffer_load_v3f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt1_elt2_s_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; Do not trim to vec3 s_buffer_load in instcombine, as the load will most likely be widened
+; to vec4 anyway during lowering.
+; CHECK-LABEL: @extract_elt1_elt2_elt3_s_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract0_bitcast_s_buffer_load_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
+; CHECK-NEXT: ret i32 %tmp2
+define i32 @extract0_bitcast_s_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
+  %tmp2 = extractelement <4 x i32> %tmp1, i32 0
+  ret i32 %tmp2
+}
+
+; CHECK-LABEL: @extract0_bitcast_s_buffer_load_v4i32(
+; CHECK-NEXT: %tmp = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast i32 %tmp to float
+; CHECK-NEXT: ret float %tmp2
+define float @extract0_bitcast_s_buffer_load_v4i32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %tmp = call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %tmp1 = bitcast <4 x i32> %tmp to <4 x float>
+  %tmp2 = extractelement <4 x float> %tmp1, i32 0
+  ret float %tmp2
+}
+
+; CHECK-LABEL: @preserve_metadata_extract_elt0_s_buffer_load_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.s.buffer.load.f32(<4 x i32> %rsrc, i32 %ofs, i32 0), !fpmath !0
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @preserve_metadata_extract_elt0_s_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 0), !fpmath !0
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare float @llvm.amdgcn.s.buffer.load.f32(<4 x i32>, i32, i32) #1
+declare <2 x float> @llvm.amdgcn.s.buffer.load.v2f32(<4 x i32>, i32, i32) #1
+declare <3 x float> @llvm.amdgcn.s.buffer.load.v3f32(<4 x i32>, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.s.buffer.load.v4f32(<4 x i32>, i32, i32) #1
+declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32) #1
+
+; CHECK-LABEL: @extract_elt0_s_buffer_load_v2f16(
+; CHECK: %data = call half @llvm.amdgcn.s.buffer.load.f16(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt0_s_buffer_load_v2f16(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <2 x half> @llvm.amdgcn.s.buffer.load.v2f16(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt0 = extractelement <2 x half> %data, i32 0
+  ret half %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_s_buffer_load_v2f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 2
+; CHECK-NEXT: %data = call half @llvm.amdgcn.s.buffer.load.f16(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_s_buffer_load_v2f16(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <2 x half> @llvm.amdgcn.s.buffer.load.v2f16(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <2 x half> %data, i32 1
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_s_buffer_load_v3f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 2
+; CHECK-NEXT: %data = call half @llvm.amdgcn.s.buffer.load.f16(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_s_buffer_load_v3f16(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <3 x half> @llvm.amdgcn.s.buffer.load.v3f16(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <3 x half> %data, i32 1
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_s_buffer_load_v4f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 2
+; CHECK-NEXT: %data = call half @llvm.amdgcn.s.buffer.load.f16(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_s_buffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x half> @llvm.amdgcn.s.buffer.load.v4f16(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 1
+  ret half %elt1
+}
+
+
+; CHECK-LABEL: @extract_elt3_s_buffer_load_v4f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 6
+; CHECK-NEXT: %data = call half @llvm.amdgcn.s.buffer.load.f16(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt3_s_buffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x half> @llvm.amdgcn.s.buffer.load.v4f16(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 3
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_s_buffer_load_v4f16(
+; CHECK-NEXT: %data = call <2 x half> @llvm.amdgcn.s.buffer.load.v2f16(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret <2 x half>
+define amdgpu_ps <2 x half> @extract_elt0_elt1_s_buffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x half> @llvm.amdgcn.s.buffer.load.v4f16(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <4 x half> %data, <4 x half> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x half> %shuf
+}
+
+declare half @llvm.amdgcn.s.buffer.load.f16(<4 x i32>, i32, i32) #1
+declare <2 x half> @llvm.amdgcn.s.buffer.load.v2f16(<4 x i32>, i32, i32) #1
+declare <3 x half> @llvm.amdgcn.s.buffer.load.v3f16(<4 x i32>, i32, i32) #1
+declare <4 x half> @llvm.amdgcn.s.buffer.load.v4f16(<4 x i32>, i32, i32) #1
+
+; CHECK-LABEL: @extract_elt0_s_buffer_load_v2i8(
+; CHECK: %data = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt0_s_buffer_load_v2i8(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <2 x i8> @llvm.amdgcn.s.buffer.load.v2i8(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt0 = extractelement <2 x i8> %data, i32 0
+  ret i8 %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_s_buffer_load_v2i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 1
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt1_s_buffer_load_v2i8(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <2 x i8> @llvm.amdgcn.s.buffer.load.v2i8(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <2 x i8> %data, i32 1
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_s_buffer_load_v3i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 1
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt1_s_buffer_load_v3i8(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <3 x i8> @llvm.amdgcn.s.buffer.load.v3i8(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <3 x i8> %data, i32 1
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_s_buffer_load_v4i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 1
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt1_s_buffer_load_v4i8(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x i8> @llvm.amdgcn.s.buffer.load.v4i8(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <4 x i8> %data, i32 1
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_s_buffer_load_v4i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 3
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32> %rsrc, i32 %1, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt3_s_buffer_load_v4i8(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x i8> @llvm.amdgcn.s.buffer.load.v4i8(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %elt1 = extractelement <4 x i8> %data, i32 3
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_s_buffer_load_v4i8(
+; CHECK-NEXT: %data = call <2 x i8> @llvm.amdgcn.s.buffer.load.v2i8(<4 x i32> %rsrc, i32 %ofs, i32 0)
+; CHECK-NEXT: ret <2 x i8>
+define amdgpu_ps <2 x i8> @extract_elt0_elt1_s_buffer_load_v4i8(<4 x i32> inreg %rsrc, i32 %ofs) #0 {
+  %data = call <4 x i8> @llvm.amdgcn.s.buffer.load.v4i8(<4 x i32> %rsrc, i32 %ofs, i32 0)
+  %shuf = shufflevector <4 x i8> %data, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x i8> %shuf
+}
+
+declare i8 @llvm.amdgcn.s.buffer.load.i8(<4 x i32>, i32, i32) #1
+declare <2 x i8> @llvm.amdgcn.s.buffer.load.v2i8(<4 x i32>, i32, i32) #1
+declare <3 x i8> @llvm.amdgcn.s.buffer.load.v3i8(<4 x i32>, i32, i32) #1
+declare <4 x i8> @llvm.amdgcn.s.buffer.load.v4i8(<4 x i32>, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.raw.buffer.load.format
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @raw_buffer_load_format_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @raw_buffer_load_format_f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  ret float %data
+}
+
+; CHECK-LABEL: @raw_buffer_load_format_v1f32(
+; CHECK-NEXT: %data = call <1 x float> @llvm.amdgcn.raw.buffer.load.format.v1f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <1 x float> %data
+define amdgpu_ps <1 x float> @raw_buffer_load_format_v1f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <1 x float> @llvm.amdgcn.raw.buffer.load.format.v1f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  ret <1 x float> %data
+}
+
+; CHECK-LABEL: @raw_buffer_load_format_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @raw_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  ret <2 x float> %data
+}
+
+; CHECK-LABEL: @raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <4 x float> %data
+define amdgpu_ps <4 x float> @raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  ret <4 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_raw_buffer_load_format_v2f32(
+; CHECK: %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_raw_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_format_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_raw_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <2 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 3
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt3_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 3
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt2_elt3_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt2_elt3_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_elt3_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt2_elt3_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_raw_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_raw_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <3 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_raw_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_raw_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_raw_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_raw_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_raw_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_raw_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_raw_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract0_bitcast_raw_buffer_load_format_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
+; CHECK-NEXT: ret i32 %tmp2
+define i32 @extract0_bitcast_raw_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
+  %tmp2 = extractelement <4 x i32> %tmp1, i32 0
+  ret i32 %tmp2
+}
+
+; CHECK-LABEL: @extract0_bitcast_raw_buffer_load_format_v4i32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %tmp
+define float @extract0_bitcast_raw_buffer_load_format_v4i32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0)
+  %tmp1 = extractelement <4 x float> %tmp, i32 0
+  ret float %tmp1
+}
+
+; CHECK-LABEL: @preserve_metadata_extract_elt0_raw_buffer_load_format_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0), !fpmath !0
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @preserve_metadata_extract_elt0_raw_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %ofs, i32 %sofs, i32 0), !fpmath !0
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare float @llvm.amdgcn.raw.buffer.load.format.f32(<4 x i32>, i32, i32, i32) #1
+declare <1 x float> @llvm.amdgcn.raw.buffer.load.format.v1f32(<4 x i32>, i32, i32, i32) #1
+declare <2 x float> @llvm.amdgcn.raw.buffer.load.format.v2f32(<4 x i32>, i32, i32, i32) #1
+declare <3 x float> @llvm.amdgcn.raw.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.struct.buffer.load
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @struct_buffer_load_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @struct_buffer_load_f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  ret float %data
+}
+
+; CHECK-LABEL: @struct_buffer_load_v1f32(
+; CHECK-NEXT: %data = call <1 x float> @llvm.amdgcn.struct.buffer.load.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <1 x float> %data
+define amdgpu_ps <1 x float> @struct_buffer_load_v1f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <1 x float> @llvm.amdgcn.struct.buffer.load.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  ret <1 x float> %data
+}
+
+; CHECK-LABEL: @struct_buffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @struct_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  ret <2 x float> %data
+}
+
+; CHECK-LABEL: @struct_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <4 x float> %data
+define amdgpu_ps <4 x float> @struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  ret <4 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_struct_buffer_load_v2f32(
+; CHECK: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_struct_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_v2f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_struct_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <2 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_struct_buffer_load_v4f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_struct_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 8
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt2_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_struct_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 12
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt3_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 3
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_struct_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_struct_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt1_elt2_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt2_elt3_struct_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 8
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt2_elt3_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_struct_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_elt3_struct_buffer_load_v4f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt2_elt3_struct_buffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_struct_buffer_load_v3f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_struct_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <3 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_v3f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_struct_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_struct_buffer_load_v3f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 8
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt2_struct_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_struct_buffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_struct_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_struct_buffer_load_v3f32(
+; CHECK-NEXT: %1 = add i32 %ofs, 4
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt1_elt2_struct_buffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract0_bitcast_struct_buffer_load_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
+; CHECK-NEXT: ret i32 %tmp2
+define i32 @extract0_bitcast_struct_buffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
+  %tmp2 = extractelement <4 x i32> %tmp1, i32 0
+  ret i32 %tmp2
+}
+
+; CHECK-LABEL: @extract0_bitcast_struct_buffer_load_v4i32(
+; CHECK-NEXT: %tmp = call i32 @llvm.amdgcn.struct.buffer.load.i32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast i32 %tmp to float
+; CHECK-NEXT: ret float %tmp2
+define float @extract0_bitcast_struct_buffer_load_v4i32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %tmp = call <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %tmp1 = bitcast <4 x i32> %tmp to <4 x float>
+  %tmp2 = extractelement <4 x float> %tmp1, i32 0
+  ret float %tmp2
+}
+
+; CHECK-LABEL: @preserve_metadata_extract_elt0_struct_buffer_load_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0), !fpmath !0
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @preserve_metadata_extract_elt0_struct_buffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0), !fpmath !0
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare float @llvm.amdgcn.struct.buffer.load.f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <1 x float> @llvm.amdgcn.struct.buffer.load.v1f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <2 x float> @llvm.amdgcn.struct.buffer.load.v2f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <3 x float> @llvm.amdgcn.struct.buffer.load.v3f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #1
+
+declare <4 x i32> @llvm.amdgcn.struct.buffer.load.v4i32(<4 x i32>, i32, i32, i32, i32) #1
+
+; CHECK-LABEL: @extract_elt0_struct_buffer_load_v2f16(
+; CHECK: %data = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt0_struct_buffer_load_v2f16(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <2 x half> %data, i32 0
+  ret half %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_v2f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 2
+; CHECK-NEXT: %data = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_struct_buffer_load_v2f16(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <2 x half> %data, i32 1
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_v3f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 2
+; CHECK-NEXT: %data = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_struct_buffer_load_v3f16(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x half> @llvm.amdgcn.struct.buffer.load.v3f16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x half> %data, i32 1
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_v4f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 2
+; CHECK-NEXT: %data = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_struct_buffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 1
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_struct_buffer_load_v4f16(
+; CHECK-NEXT: %1 = add i32 %ofs, 6
+; CHECK-NEXT: %data = call half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt3_struct_buffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 3
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_struct_buffer_load_v4f16(
+; CHECK-NEXT: %data = call <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x half>
+define amdgpu_ps <2 x half> @extract_elt0_elt1_struct_buffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x half> %data, <4 x half> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x half> %shuf
+}
+
+declare half @llvm.amdgcn.struct.buffer.load.f16(<4 x i32>, i32, i32, i32, i32) #1
+declare <2 x half> @llvm.amdgcn.struct.buffer.load.v2f16(<4 x i32>, i32, i32, i32, i32) #1
+declare <3 x half> @llvm.amdgcn.struct.buffer.load.v3f16(<4 x i32>, i32, i32, i32, i32) #1
+declare <4 x half> @llvm.amdgcn.struct.buffer.load.v4f16(<4 x i32>, i32, i32, i32, i32) #1
+
+; CHECK-LABEL: @extract_elt0_struct_buffer_load_v2i8(
+; CHECK: %data = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt0_struct_buffer_load_v2i8(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x i8> @llvm.amdgcn.struct.buffer.load.v2i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <2 x i8> %data, i32 0
+  ret i8 %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_v2i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 1
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt1_struct_buffer_load_v2i8(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x i8> @llvm.amdgcn.struct.buffer.load.v2i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <2 x i8> %data, i32 1
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_v3i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 1
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt1_struct_buffer_load_v3i8(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x i8> @llvm.amdgcn.struct.buffer.load.v3i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x i8> %data, i32 1
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_v4i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 1
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt1_struct_buffer_load_v4i8(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x i8> @llvm.amdgcn.struct.buffer.load.v4i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x i8> %data, i32 1
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_struct_buffer_load_v4i8(
+; CHECK-NEXT: %1 = add i32 %ofs, 3
+; CHECK-NEXT: %data = call i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32> %rsrc, i32 %idx, i32 %1, i32 %sofs, i32 0)
+; CHECK-NEXT: ret i8 %data
+define amdgpu_ps i8 @extract_elt3_struct_buffer_load_v4i8(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x i8> @llvm.amdgcn.struct.buffer.load.v4i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x i8> %data, i32 3
+  ret i8 %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_struct_buffer_load_v4i8(
+; CHECK-NEXT: %data = call <2 x i8> @llvm.amdgcn.struct.buffer.load.v2i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x i8>
+define amdgpu_ps <2 x i8> @extract_elt0_elt1_struct_buffer_load_v4i8(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x i8> @llvm.amdgcn.struct.buffer.load.v4i8(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x i8> %data, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x i8> %shuf
+}
+
+declare i8 @llvm.amdgcn.struct.buffer.load.i8(<4 x i32>, i32, i32, i32, i32) #1
+declare <2 x i8> @llvm.amdgcn.struct.buffer.load.v2i8(<4 x i32>, i32, i32, i32, i32) #1
+declare <3 x i8> @llvm.amdgcn.struct.buffer.load.v3i8(<4 x i32>, i32, i32, i32, i32) #1
+declare <4 x i8> @llvm.amdgcn.struct.buffer.load.v4i8(<4 x i32>, i32, i32, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.struct.buffer.load.format
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @struct_buffer_load_format_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @struct_buffer_load_format_f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  ret float %data
+}
+
+; CHECK-LABEL: @struct_buffer_load_format_v1f32(
+; CHECK-NEXT: %data = call <1 x float> @llvm.amdgcn.struct.buffer.load.format.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <1 x float> %data
+define amdgpu_ps <1 x float> @struct_buffer_load_format_v1f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <1 x float> @llvm.amdgcn.struct.buffer.load.format.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  ret <1 x float> %data
+}
+
+; CHECK-LABEL: @struct_buffer_load_format_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @struct_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  ret <2 x float> %data
+}
+
+; CHECK-LABEL: @struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <4 x float> %data
+define amdgpu_ps <4 x float> @struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  ret <4 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_struct_buffer_load_format_v2f32(
+; CHECK: %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_struct_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_format_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_struct_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <2 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 3
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt3_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 3
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt2_elt3_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt2_elt3_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_elt3_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt2_elt3_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_struct_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_struct_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt0 = extractelement <3 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_struct_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_struct_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_struct_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_struct_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_struct_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_struct_buffer_load_format_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_struct_buffer_load_format_v3f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract0_bitcast_struct_buffer_load_format_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
+; CHECK-NEXT: ret i32 %tmp2
+define i32 @extract0_bitcast_struct_buffer_load_format_v4f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0)
+  %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
+  %tmp2 = extractelement <4 x i32> %tmp1, i32 0
+  ret i32 %tmp2
+}
+
+; CHECK-LABEL: @preserve_metadata_extract_elt0_struct_buffer_load_format_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0), !fpmath !0
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @preserve_metadata_extract_elt0_struct_buffer_load_format_v2f32(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs, i32 %sofs) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i32 %sofs, i32 0), !fpmath !0
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare float @llvm.amdgcn.struct.buffer.load.format.f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <1 x float> @llvm.amdgcn.struct.buffer.load.format.v1f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <2 x float> @llvm.amdgcn.struct.buffer.load.format.v2f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <3 x float> @llvm.amdgcn.struct.buffer.load.format.v3f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32) #1
+
+declare <4 x i32> @llvm.amdgcn.struct.buffer.load.format.v4i32(<4 x i32>, i32, i32, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.raw.tbuffer.load
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @raw_tbuffer_load_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @raw_tbuffer_load_f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  ret float %data
+}
+
+; CHECK-LABEL: @raw_tbuffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @raw_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  ret <2 x float> %data
+}
+
+; CHECK-LABEL: @raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret <4 x float> %data
+define amdgpu_ps <4 x float> @raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  ret <4 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_raw_tbuffer_load_v2f32(
+; CHECK: %data = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_raw_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_tbuffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_raw_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <2 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 3
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt3_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 3
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt2_elt3_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt2_elt3_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_elt3_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt2_elt3_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_raw_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_raw_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt0 = extractelement <3 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_raw_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_raw_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_raw_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_raw_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_raw_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_raw_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_raw_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_raw_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract0_bitcast_raw_tbuffer_load_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
+; CHECK-NEXT: ret i32 %tmp2
+define i32 @extract0_bitcast_raw_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
+  %tmp2 = extractelement <4 x i32> %tmp1, i32 0
+  ret i32 %tmp2
+}
+
+; CHECK-LABEL: @preserve_metadata_extract_elt0_raw_tbuffer_load_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0), !fpmath !0
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @preserve_metadata_extract_elt0_raw_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0), !fpmath !0
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare float @llvm.amdgcn.raw.tbuffer.load.f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <2 x float> @llvm.amdgcn.raw.tbuffer.load.v2f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <3 x float> @llvm.amdgcn.raw.tbuffer.load.v3f32(<4 x i32>, i32, i32, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.raw.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32, i32) #1
+
+declare <4 x i32> @llvm.amdgcn.raw.tbuffer.load.v4i32(<4 x i32>, i32, i32, i32, i32) #1
+
+; CHECK-LABEL: @extract_elt3_raw_tbuffer_load_v4f16(
+; CHECK-NEXT: %data = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <4 x half> %data, i32 3
+; CHECK-NEXT: ret half %elt1
+define amdgpu_ps half @extract_elt3_raw_tbuffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 3
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_raw_tbuffer_load_v4f16(
+; CHECK-NEXT: %data = call <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <3 x half> %data, i32 2
+; CHECK-NEXT: ret half %elt1
+define amdgpu_ps half @extract_elt2_raw_tbuffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 2
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt1_raw_tbuffer_load_v4f16(
+; CHECK-NEXT: %data = call <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x half> %data, i32 1
+; CHECK-NEXT: ret half %elt1
+define amdgpu_ps half @extract_elt1_raw_tbuffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 1
+  ret half %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_raw_tbuffer_load_v4f16(
+; CHECK-NEXT: %data = call half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt0_raw_tbuffer_load_v4f16(<4 x i32> inreg %rsrc, i32 %arg0, i32 inreg %arg1) #0 {
+  %data = call <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 78, i32 0)
+  %elt1 = extractelement <4 x half> %data, i32 0
+  ret half %elt1
+}
+
+declare half @llvm.amdgcn.raw.tbuffer.load.f16(<4 x i32>, i32, i32, i32, i32) #1
+declare <2 x half> @llvm.amdgcn.raw.tbuffer.load.v2f16(<4 x i32>, i32, i32, i32, i32) #1
+declare <3 x half> @llvm.amdgcn.raw.tbuffer.load.v3f16(<4 x i32>, i32, i32, i32, i32) #1
+declare <4 x half> @llvm.amdgcn.raw.tbuffer.load.v4f16(<4 x i32>, i32, i32, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.struct.tbuffer.load
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @struct_tbuffer_load_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @struct_tbuffer_load_f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  ret float %data
+}
+
+; CHECK-LABEL: @struct_tbuffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @struct_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  ret <2 x float> %data
+}
+
+; CHECK-LABEL: @struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: ret <4 x float> %data
+define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  ret <4 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_struct_tbuffer_load_v2f32(
+; CHECK: %data = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_struct_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_tbuffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_struct_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %elt1 = extractelement <2 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 3
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt3_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %elt1 = extractelement <4 x float> %data, i32 3
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt2_elt3_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt2_elt3_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_elt3_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt2_elt3_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_struct_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_struct_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %elt0 = extractelement <3 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_struct_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_struct_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_struct_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_struct_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %elt1 = extractelement <3 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_struct_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_struct_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_struct_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_struct_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract0_bitcast_struct_tbuffer_load_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
+; CHECK-NEXT: ret i32 %tmp2
+define i32 @extract0_bitcast_struct_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0)
+  %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
+  %tmp2 = extractelement <4 x i32> %tmp1, i32 0
+  ret i32 %tmp2
+}
+
+; CHECK-LABEL: @preserve_metadata_extract_elt0_struct_tbuffer_load_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0), !fpmath !0
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @preserve_metadata_extract_elt0_struct_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1, i32 inreg %arg2) #0 {
+  %data = call <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 %arg2, i32 78, i32 0), !fpmath !0
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare float @llvm.amdgcn.struct.tbuffer.load.f32(<4 x i32>, i32, i32, i32, i32, i32) #1
+declare <2 x float> @llvm.amdgcn.struct.tbuffer.load.v2f32(<4 x i32>, i32, i32, i32, i32, i32) #1
+declare <3 x float> @llvm.amdgcn.struct.tbuffer.load.v3f32(<4 x i32>, i32, i32, i32, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.struct.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32, i32, i32) #1
+
+declare <4 x i32> @llvm.amdgcn.struct.tbuffer.load.v4i32(<4 x i32>, i32, i32, i32, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.tbuffer.load
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @tbuffer_load_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @tbuffer_load_f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call float @llvm.amdgcn.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  ret float %data
+}
+
+; CHECK-LABEL: @tbuffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  ret <2 x float> %data
+}
+
+; CHECK-LABEL: @tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: ret <4 x float> %data
+define amdgpu_ps <4 x float> @tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  ret <4 x float> %data
+}
+
+; CHECK-LABEL: @extract_elt0_tbuffer_load_v2f32(
+; CHECK: %data = call float @llvm.amdgcn.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_tbuffer_load_v2f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %elt1 = extractelement <2 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %elt1 = extractelement <4 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %elt1 = extractelement <4 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt3_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <4 x float> %data, i32 3
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt3_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %elt1 = extractelement <4 x float> %data, i32 3
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt2_elt3_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt2_elt3_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 2, i32 3>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_elt3_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt2_elt3_tbuffer_load_v4f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt2_elt3_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %elt0 = extractelement <3 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <2 x float> %data, i32 1
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt1_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %elt1 = extractelement <3 x float> %data, i32 1
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt2_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %elt1 = extractelement <3 x float> %data, i32 2
+; CHECK-NEXT: ret float %elt1
+define amdgpu_ps float @extract_elt2_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %elt1 = extractelement <3 x float> %data, i32 2
+  ret float %elt1
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: ret <2 x float>
+define amdgpu_ps <2 x float> @extract_elt0_elt1_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt1_elt2_tbuffer_load_v3f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT: ret <2 x float> %shuf
+define amdgpu_ps <2 x float> @extract_elt1_elt2_tbuffer_load_v3f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %shuf = shufflevector <3 x float> %data, <3 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract0_bitcast_tbuffer_load_v4f32(
+; CHECK-NEXT: %tmp = call float @llvm.amdgcn.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+; CHECK-NEXT: %tmp2 = bitcast float %tmp to i32
+; CHECK-NEXT: ret i32 %tmp2
+define i32 @extract0_bitcast_tbuffer_load_v4f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %tmp = call <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false)
+  %tmp1 = bitcast <4 x float> %tmp to <4 x i32>
+  %tmp2 = extractelement <4 x i32> %tmp1, i32 0
+  ret i32 %tmp2
+}
+
+; CHECK-LABEL: @preserve_metadata_extract_elt0_tbuffer_load_v2f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.tbuffer.load.f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false), !fpmath !0
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @preserve_metadata_extract_elt0_tbuffer_load_v2f32(<4 x i32> inreg %rsrc, i32 %arg0, i32 %arg1) #0 {
+  %data = call <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32> %rsrc, i32 %arg0, i32 %arg1, i32 0, i32 0, i32 14, i32 4, i1 false, i1 false), !fpmath !0
+  %elt0 = extractelement <2 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare float @llvm.amdgcn.tbuffer.load.f32(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #1
+declare <1 x float> @llvm.amdgcn.tbuffer.load.v1f32(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #1
+declare <2 x float> @llvm.amdgcn.tbuffer.load.v2f32(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #1
+declare <3 x float> @llvm.amdgcn.tbuffer.load.v3f32(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #1
+declare <4 x float> @llvm.amdgcn.tbuffer.load.v4f32(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #1
+
+declare <4 x i32> @llvm.amdgcn.tbuffer.load.v4i32(<4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_1d_v4f32_f32(float %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; Check that the intrinsic remains unchanged in the presence of TFE or LWE
+; CHECK-LABEL: @extract_elt0_image_sample_1d_v4f32_f32_tfe(
+; CHECK-NEXT: %data = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32(i32 15, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 1, i32 0)
+; CHECK: ret float %elt0
+define amdgpu_ps float @extract_elt0_image_sample_1d_v4f32_f32_tfe(float %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32(i32 15, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 1, i32 0)
+  %data.vec = extractvalue {<4 x float>,i32} %data, 0
+  %elt0 = extractelement <4 x float> %data.vec, i32 0
+  ret float %elt0
+}
+
+; Check that the intrinsic remains unchanged in the presence of TFE or LWE
+; CHECK-LABEL: @extract_elt0_image_sample_1d_v4f32_f32_lwe(
+; CHECK-NEXT: %data = call { <4 x float>, i32 } @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32(i32 15, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 2, i32 0)
+; CHECK: ret float %elt0
+define amdgpu_ps float @extract_elt0_image_sample_1d_v4f32_f32_lwe(float %vaddr, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32(i32 15, float %vaddr, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 2, i32 0)
+  %data.vec = extractvalue {<4 x float>,i32} %data, 0
+  %elt0 = extractelement <4 x float> %data.vec, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_2d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.2d.f32.f32(i32 1, float %s, float %t, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_2d_v4f32_f32(float %s, float %t, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32 15, float %s, float %t, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_0000_image_sample_3d_v4f32_f32(
+; CHECK-NEXT: ret float undef
+define amdgpu_ps float @extract_elt0_dmask_0000_image_sample_3d_v4f32_f32(float %s, float %t, float %r, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32 0, float %s, float %t, float %r, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_0001_image_sample_1darray_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1darray.f32.f32(i32 1, float %s, float %slice, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0001_image_sample_1darray_v4f32_f32(float %s, float %slice, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32(i32 1, float %s, float %slice, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_0010_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 2, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0010_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 2, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_0100_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 4, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0100_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 4, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_1000_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 8, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_1000_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 8, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_1001_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_1001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 9, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_0011_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 3, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_dmask_0111_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_dmask_0111_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 7, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: %1 = insertelement <2 x float> undef, float %data, i32 0
+; CHECK-NEXT: ret <2 x float> %1
+define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_dmask_0011_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 3, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_dmask_0111_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0111_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 7, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_dmask_0101_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 5, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0101_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 5, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: %1 = insertelement <3 x float> undef, float %data, i32 0
+; CHECK-NEXT: ret <3 x float> %1
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0011_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 3, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <2 x float> %data, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 3, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0101_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.1d.v2f32.f32(i32 5, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: %shuf = shufflevector <2 x float> %data, <2 x float> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+; CHECK-NEXT: ret <3 x float> %shuf
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0101_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 5, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0111_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.image.sample.1d.v3f32.f32(i32 7, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0111_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 7, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_1111_image_sample_1d_v4f32_f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.image.sample.1d.v3f32.f32(i32 7, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_1111_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 15, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
+  ret <3 x float> %shuf
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+declare {<4 x float>,i32} @llvm.amdgcn.image.sample.1d.sl_v4f32i32s.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.image.sample.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.image.sample.3d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+declare <4 x float> @llvm.amdgcn.image.sample.1darray.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt1_image_sample_cl_2darray_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cl.2darray.f32.f32(i32 2, float %s, float %t, float %slice, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_image_sample_cl_2darray_v4f32_f32(float %s, float %t, float %slice, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cl.2darray.v4f32.f32(i32 15, float %s, float %t, float %slice, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 1
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cl.2darray.v4f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.d
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt2_image_sample_d_cube_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.cube.f32.f32.f32(i32 4, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %face, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt2_image_sample_d_cube_v4f32_f32_f32(float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %face, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.d.cube.v4f32.f32.f32(i32 15, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %face, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 2
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.d.cube.v4f32.f32.f32(i32, float, float, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.d.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt3_image_sample_d_cl_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.cl.1d.f32.f32.f32(i32 8, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt3_image_sample_d_cl_1d_v4f32_f32_f32(float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 3
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.d.cl.1d.v4f32.f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.l
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt1_dmask_0110_image_sample_l_1d_v2f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.l.1d.f32.f32(i32 4, float %s, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_dmask_0110_image_sample_l_1d_v2f32_f32(float %s, float %lod, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <2 x float> @llvm.amdgcn.image.sample.l.1d.v2f32.f32(i32 6, float %s, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <2 x float> %data, i32 1
+  ret float %elt0
+}
+
+declare <2 x float> @llvm.amdgcn.image.sample.l.1d.v2f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.b
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt1_dmask_1001_image_sample_b_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.1d.f32.f32.f32(i32 8, float %bias, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt1_dmask_1001_image_sample_b_1d_v4f32_f32_f32(float %bias, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32(i32 9, float %bias, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 1
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.b.1d.v4f32.f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.b.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt1_elt2_dmask_1101_image_sample_b_cl_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.b.cl.1d.v2f32.f32.f32(i32 12, float %bias, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt1_elt2_dmask_1101_image_sample_b_cl_1d_v4f32_f32_f32(float %bias, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f32.f32(i32 13, float %bias, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 2>
+  ret <2 x float> %shuf
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.b.cl.1d.v4f32.f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.lz
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt1_elt3_image_sample_lz_1d_v4f32_f32(
+; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.image.sample.lz.1d.v2f32.f32(i32 10, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret <2 x float> %data
+define amdgpu_ps <2 x float> @extract_elt1_elt3_image_sample_lz_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32(i32 15, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <2 x i32> <i32 1, i32 3>
+  ret <2 x float> %shuf
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.lz.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cd
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt1_elt2_elt3_image_sample_cd_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call <3 x float> @llvm.amdgcn.image.sample.cd.1d.v3f32.f32.f32(i32 14, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret <3 x float> %data
+define amdgpu_ps <3 x float> @extract_elt1_elt2_elt3_image_sample_cd_1d_v4f32_f32_f32(float %dsdh, float %dsdv, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %shuf = shufflevector <4 x float> %data, <4 x float> undef, <3 x i32> <i32 1, i32 2, i32 3>
+  ret <3 x float> %shuf
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cd.1d.v4f32.f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cd.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt3_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call half @llvm.amdgcn.image.sample.cd.cl.1d.f16.f32.f32(i32 8, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt3_image_sample_cd_cl_1d_v4f16_f32_f32(float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x half> %data, i32 3
+  ret half %elt0
+}
+
+; CHECK-LABEL: @extract_elt2_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call half @llvm.amdgcn.image.sample.cd.cl.1d.f16.f32.f32(i32 4, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt2_image_sample_cd_cl_1d_v4f16_f32_f32(float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x half> %data, i32 2
+  ret half %elt0
+}
+
+; CHECK-LABEL: @extract_elt1_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call half @llvm.amdgcn.image.sample.cd.cl.1d.f16.f32.f32(i32 2, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt1_image_sample_cd_cl_1d_v4f16_f32_f32(float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x half> %data, i32 1
+  ret half %elt0
+}
+
+; CHECK-LABEL: @extract_elt_to3_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call <3 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v3f16.f32.f32(i32 7, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: %res = shufflevector <3 x half> %data, <3 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
+; CHECK-NEXT: ret <4 x half> %res
+define amdgpu_ps <4 x half> @extract_elt_to3_image_sample_cd_cl_1d_v4f16_f32_f32(float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %res = shufflevector <4 x half> %data, <4 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
+  ret <4 x half> %res
+}
+
+; CHECK-LABEL: @extract_elt_to2_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call <2 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v2f16.f32.f32(i32 3, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: %res = shufflevector <2 x half> %data, <2 x half> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT: ret <4 x half> %res
+define amdgpu_ps <4 x half> @extract_elt_to2_image_sample_cd_cl_1d_v4f16_f32_f32(float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %res = shufflevector <4 x half> %data, <4 x half> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+  ret <4 x half> %res
+}
+
+; CHECK-LABEL: @extract_elt_to1_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call half @llvm.amdgcn.image.sample.cd.cl.1d.f16.f32.f32(i32 1, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: %res = insertelement <4 x half> undef, half %data, i64 0
+; CHECK-NEXT: ret <4 x half> %res
+define amdgpu_ps <4 x half> @extract_elt_to1_image_sample_cd_cl_1d_v4f16_f32_f32(float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %res = shufflevector <4 x half> %data, <4 x half> undef, <4 x i32> <i32 0, i32 4, i32 5, i32 6>
+  ret <4 x half> %res
+}
+
+; CHECK-LABEL: @extract_elt0_image_sample_cd_cl_1d_v4f16_f32_f32(
+; CHECK-NEXT: %data = call half @llvm.amdgcn.image.sample.cd.cl.1d.f16.f32.f32(i32 1, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret half %data
+define amdgpu_ps half @extract_elt0_image_sample_cd_cl_1d_v4f16_f32_f32(float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32 15, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x half> %data, i32 0
+  ret half %elt0
+}
+
+declare <4 x half> @llvm.amdgcn.image.sample.cd.cl.1d.v4f16.f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.1d.f32.f32(i32 1, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_1d_v4f32_f32(float %zcompare, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32 15, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cl_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cl.1d.f32.f32(i32 1, float %zcompare, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cl_1d_v4f32_f32(float %zcompare, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f32(i32 15, float %zcompare, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cl.1d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.d
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_d_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.1d.f32.f32.f32(i32 1, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_d_1d_v4f32_f32_f32(float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f32(i32 15, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.d.1d.v4f32.f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.d.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_d_cl_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.cl.1d.f32.f32.f32(i32 1, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_d_cl_1d_v4f32_f32_f32(float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f32(i32 15, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.1d.v4f32.f32.f32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.l
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_l_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.l.1d.f32.f32(i32 1, float %zcompare, float %s, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_l_1d_v4f32_f32(float %zcompare, float %s, float %lod, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32(i32 15, float %zcompare, float %s, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.b
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_b_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.1d.f32.f32.f32(i32 1, float %bias, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_b_1d_v4f32_f32_f32(float %bias, float %zcompare, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.f32(i32 15, float %bias, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.b.1d.v4f32.f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.b.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_b_cl_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.cl.1d.f32.f32.f32(i32 1, float %bias, float %zcompare, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_b_cl_1d_v4f32_f32_f32(float %bias, float %zcompare, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f32.f32(i32 15, float %bias, float %zcompare, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.1d.v4f32.f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.lz
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_lz_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.lz.1d.f32.f32(i32 1, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_lz_1d_v4f32_f32(float %zcompare, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f32(i32 15, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.lz.1d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cd
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cd_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.1d.f32.f32.f32(i32 1, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cd_1d_v4f32_f32_f32(float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f32(i32 15, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cd.1d.v4f32.f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cd.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cd_cl_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.cl.1d.f32.f32.f32(i32 1, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cd_cl_1d_v4f32_f32_f32(float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f32(i32 15, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.1d.v4f32.f32.f32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_o_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.o.1d.f32.f32(i32 1, i32 %offset, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_o_1d_v4f32_f32(i32 %offset, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.o.1d.v4f32.f32(i32, i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_cl_o_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cl.o.1d.f32.f32(i32 1, i32 %offset, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_cl_o_1d_v4f32_f32(i32 %offset, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cl.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cl.o.1d.v4f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.d.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_d_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.o.1d.f32.f32.f32(i32 1, i32 %offset, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_d_o_1d_v4f32_f32_f32(i32 %offset, float %dsdh, float %dsdv, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.d.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.d.o.1d.v4f32.f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.d.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_d_cl_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.d.cl.o.1d.f32.f32.f32(i32 1, i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_d_cl_o_1d_v4f32_f32_f32(i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.d.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.d.cl.o.1d.v4f32.f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.l.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_l_o_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.l.o.1d.f32.f32(i32 1, i32 %offset, float %s, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_l_o_1d_v4f32_f32(i32 %offset, float %s, float %lod, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.b.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_b_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.o.1d.f32.f32.f32(i32 1, i32 %offset, float %bias, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_b_o_1d_v4f32_f32_f32(i32 %offset, float %bias, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.b.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %bias, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.b.o.1d.v4f32.f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.b.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_b_cl_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.b.cl.o.1d.f32.f32.f32(i32 1, i32 %offset, float %bias, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_b_cl_o_1d_v4f32_f32_f32(i32 %offset, float %bias, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.b.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %bias, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.b.cl.o.1d.v4f32.f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.lz.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_lz_o_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.lz.o.1d.f32.f32(i32 1, i32 %offset, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_lz_o_1d_v4f32_f32(i32 %offset, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.lz.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.lz.o.1d.v4f32.f32(i32, i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cd.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_cd_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.o.1d.f32.f32.f32(i32 1, i32 %offset, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_cd_o_1d_v4f32_f32_f32(i32 %offset, float %dsdh, float %dsdv, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cd.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cd.o.1d.v4f32.f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.cd.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_cd_cl_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.cd.cl.o.1d.f32.f32.f32(i32 1, i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_cd_cl_o_1d_v4f32_f32_f32(i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.1d.v4f32.f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_o_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.o.1d.f32.f32(i32 1, i32 %offset, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_o_1d_v4f32_f32(i32 %offset, float %zcompare, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.o.1d.v4f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cl_o_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cl.o.1d.f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cl_o_1d_v4f32_f32(i32 %offset, float %zcompare, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cl.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cl.o.1d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.d.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_d_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.o.1d.f32.f32.f32(i32 1, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_d_o_1d_v4f32_f32_f32(i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.d.o.1d.v4f32.f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.d.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_d_cl_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.d.cl.o.1d.f32.f32.f32(i32 1, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_d_cl_o_1d_v4f32_f32_f32(i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.1d.v4f32.f32.f32(i32, i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.l.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_l_o_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.l.o.1d.f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_l_o_1d_v4f32_f32(i32 %offset, float %zcompare, float %s, float %lod, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.b.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_b_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.o.1d.f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_b_o_1d_v4f32_f32_f32(i32 %offset, float %bias, float %zcompare, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %bias, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.1d.v4f32.f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.b.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_b_cl_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.b.cl.o.1d.f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_b_cl_o_1d_v4f32_f32_f32(i32 %offset, float %bias, float %zcompare, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %bias, float %zcompare, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.1d.v4f32.f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.lz.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_lz_o_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.lz.o.1d.f32.f32(i32 1, i32 %offset, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_lz_o_1d_v4f32_f32(i32 %offset, float %zcompare, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.lz.o.1d.v4f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cd.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cd_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.o.1d.f32.f32.f32(i32 1, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cd_o_1d_v4f32_f32_f32(i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cd.o.1d.v4f32.f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.sample.c.cd.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_sample_c_cd_cl_o_1d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.sample.c.cd.cl.o.1d.f32.f32.f32(i32 1, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_sample_c_cd_cl_o_1d_v4f32_f32_f32(i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.1d.v4f32.f32.f32(i32, i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4
+; --------------------------------------------------------------------
+
+; Don't handle gather4*
+
+; CHECK-LABEL: @extract_elt0_image_gather4_2d_v4f32_f32(
+; CHECK: %data = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_2d_v4f32_f32(float %s, float %t, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32 1, float %s, float %t, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.2d.v4f32.f32(i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_cl_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f32(i32 2, float %s, float %t, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_cl_2d_v4f32_f32(float %s, float %t, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f32(i32 2, float %s, float %t, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.cl.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.l
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_l_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 4, float %s, float %t, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_l_2d_v4f32_f32(float %s, float %t, float %lod, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 4, float %s, float %t, float %lod, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.b
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_b_2darray_v4f32_f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.2darray.v4f32.f32.f32(i32 8, float %bias, float %s, float %t, float %slice, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_b_2darray_v4f32_f32_f32(float %bias, float %s, float %t, float %slice, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.b.2darray.v4f32.f32.f32(i32 8, float %bias, float %s, float %t, float %slice, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.b.2darray.v4f32.f32.f32(i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.b.cl
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_b_cl_cube_v4f32_f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.cube.v4f32.f32.f32(i32 1, float %bias, float %s, float %t, float %face, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_b_cl_cube_v4f32_f32_f32(float %bias, float %s, float %t, float %face, float %clamp, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.cube.v4f32.f32.f32(i32 1, float %bias, float %s, float %t, float %face, float %clamp, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.cube.v4f32.f32.f32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.lz
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_lz_2d_v4f32_f16(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_lz_2d_v4f32_f16(half %s, half %t, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32 1, half %s, half %t, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.lz.2d.v4f32.f16(i32, half, half, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_o_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_o_2d_v4f32_f32(i32 %offset, float %s, float %t, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.o.2d.v4f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_cl_o_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, float %clamp, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_cl_o_2d_v4f32_f32(i32 %offset, float %s, float %t, float %clamp, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.cl.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, float %clamp, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.cl.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.l.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_l_o_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, float %lod, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_l_o_2d_v4f32_f32(i32 %offset, float %s, float %t, float %lod, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, float %lod, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.b.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_b_o_2d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_b_o_2d_v4f32_f32_f32(i32 %offset, float %bias, float %s, float %t, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.b.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.b.o.2d.v4f32.f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.b.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_b_cl_o_2d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %s, float %t, float %clamp, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_b_cl_o_2d_v4f32_f32_f32(i32 %offset, float %bias, float %s, float %t, float %clamp, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %s, float %t, float %clamp, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.2d.v4f32.f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.lz.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_lz_o_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_lz_o_2d_v4f32_f32(i32 %offset, float %s, float %t, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.2d.v4f32.f32(i32 1, i32 %offset, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.lz.o.2d.v4f32.f32(i32, i32, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_o_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_c_o_2d_v4f32_f32(i32 %offset, float %zcompare, float %s, float %t, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_cl_o_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_c_cl_o_2d_v4f32_f32(i32 %offset, float %zcompare, float %s, float %t, float %clamp, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.2d.v4f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.l.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_l_o_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, float %lod, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_c_l_o_2d_v4f32_f32(i32 %offset, float %zcompare, float %s, float %t, float %lod, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, float %lod, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.b.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_b_o_2d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_c_b_o_2d_v4f32_f32_f32(i32 %offset, float %bias, float %zcompare, float %s, float %t, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.o.2d.v4f32.f32.f32(i32, i32, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.b.cl.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_b_cl_o_2d_v4f32_f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_c_b_cl_o_2d_v4f32_f32_f32(i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.2d.v4f32.f32.f32(i32, i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.gather4.c.lz.o
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_gather4_c_lz_o_2d_v4f32_f32(
+; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+define amdgpu_ps float @extract_elt0_image_gather4_c_lz_o_2d_v4f32_f32(i32 %offset, float %zcompare, float %s, float %t, <8 x i32> inreg %gather4r, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.2d.v4f32.f32(i32 1, i32 %offset, float %zcompare, float %s, float %t, <8 x i32> %gather4r, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.2d.v4f32.f32(i32, i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.getlod
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_getlod_1d_v4f32_f32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.getlod.1d.f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_getlod_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32 15, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.getlod.1d.v4f32.f32(i32, float, <8 x i32>, <4 x i32>, i1, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.load
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_load_2dmsaa_v4f32_i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32(i32 1, i32 %s, i32 %t, i32 %sample, <8 x i32> %sampler, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_load_2dmsaa_v4f32_i32(i32 %s, i32 %t, i32 %sample, <8 x i32> inreg %sampler) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %sample, <8 x i32> %sampler, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i32(i32, i32, i32, i32, <8 x i32>, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.load.mip
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_load_mip_1d_v4f32_i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.load.mip.1d.f32.i32(i32 1, i32 %s, i32 %mip, <8 x i32> %sampler, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_load_mip_1d_v4f32_i32(i32 %s, i32 %mip, <8 x i32> inreg %sampler) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 15, i32 %s, i32 %mip, <8 x i32> %sampler, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32, i32, i32, <8 x i32>, i32, i32) #1
+
+; --------------------------------------------------------------------
+; llvm.amdgcn.image.getresinfo
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_image_getresinfo_1d_v4f32_i32(
+; CHECK-NEXT: %data = call float @llvm.amdgcn.image.getresinfo.1d.f32.i32(i32 1, i32 %mip, <8 x i32> %sampler, i32 0, i32 0)
+; CHECK-NEXT: ret float %data
+define amdgpu_ps float @extract_elt0_image_getresinfo_1d_v4f32_i32(i32 %mip, <8 x i32> inreg %sampler) #0 {
+  %data = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32 15, i32 %mip, <8 x i32> %sampler, i32 0, i32 0)
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #1
+
+; --------------------------------------------------------------------
+; TFE / LWE
+; --------------------------------------------------------------------
+
+; CHECK-LABEL: @extract_elt0_tfe_image_load_1d_v4f32i32_i32(
+; CHECK-NEXT: %data = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1)
+define amdgpu_ps float @extract_elt0_tfe_image_load_1d_v4f32i32_i32(i32 %s, <8 x i32> inreg %rsrc) #0 {
+  %data = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1)
+  %rgba = extractvalue { <4 x float>, i32 } %data, 0
+  %elt0 = extractelement <4 x float> %rgba, i32 0
+  ret float %elt0
+}
+
+declare {<4 x float>, i32} @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32(i32, i32, <8 x i32>, i32, i32) #1
+
+; CHECK: @tfe_check_assert(
+; CHECK: %data = call float @llvm.amdgcn.image.load.2d.f32.i32(i32 1, i32 undef, i32 undef, <8 x i32> undef, i32 0, i32 1)
+; CHECK-NEXT: ret float %data
+define amdgpu_hs float @tfe_check_assert() #0 {
+  %data = call nsz <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 undef, i32 undef, <8 x i32> undef, i32 0, i32 1) #2
+  %elt0 = extractelement <4 x float> %data, i32 0
+  ret float %elt0
+}
+
+declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #1
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readonly }
+
+!0 = !{float 2.500000e+00}
diff --git a/llvm/test/Transforms/InstCombine/ARM/tbl1.ll b/llvm/test/Transforms/InstCombine/ARM/tbl1.ll
index f3cd9102cdf4e..ec4b842bb7893 100644
--- a/llvm/test/Transforms/InstCombine/ARM/tbl1.ll
+++ b/llvm/test/Transforms/InstCombine/ARM/tbl1.ll
@@ -12,7 +12,7 @@ target triple = "armv8-arm-none-eabi"
 define <8 x i8> @tbl1_8x8(<8 x i8> %vec) {
 ; CHECK-LABEL: @tbl1_8x8(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <8 x i8> [[VEC:%.*]], <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <8 x i8> [[VEC:%.*]], <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
 ; CHECK-NEXT:    ret <8 x i8> [[TMP0]]
 ;
 entry:
diff --git a/llvm/test/Transforms/InstCombine/X86/clmulqdq.ll b/llvm/test/Transforms/InstCombine/X86/clmulqdq.ll
index 7ec7e1a20d5d9..26da05f806979 100644
--- a/llvm/test/Transforms/InstCombine/X86/clmulqdq.ll
+++ b/llvm/test/Transforms/InstCombine/X86/clmulqdq.ll
@@ -18,7 +18,7 @@ define <2 x i64> @test_demanded_elts_pclmulqdq_0(<2 x i64> %a0, <2 x i64> %a1) {
 
 define <2 x i64> @test_demanded_elts_pclmulqdq_1(<2 x i64> %a0, <2 x i64> %a1) {
 ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_1(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> [[A1:%.*]], i8 1)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 1>, <2 x i64> [[A1:%.*]], i8 1)
 ; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
 ;
   %1 = insertelement <2 x i64> %a0, i64 1, i64 1
@@ -29,7 +29,7 @@ define <2 x i64> @test_demanded_elts_pclmulqdq_1(<2 x i64> %a0, <2 x i64> %a1) {
 
 define <2 x i64> @test_demanded_elts_pclmulqdq_16(<2 x i64> %a0, <2 x i64> %a1) {
 ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_16(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> [[A0:%.*]], <2 x i64> <i64 undef, i64 1>, i8 16)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> [[A0:%.*]], <2 x i64> <i64 poison, i64 1>, i8 16)
 ; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
 ;
   %1 = insertelement <2 x i64> %a0, i64 1, i64 1
@@ -40,7 +40,7 @@ define <2 x i64> @test_demanded_elts_pclmulqdq_16(<2 x i64> %a0, <2 x i64> %a1)
 
 define <2 x i64> @test_demanded_elts_pclmulqdq_17(<2 x i64> %a0, <2 x i64> %a1) {
 ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_17(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> <i64 undef, i64 1>, i8 17)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 1>, <2 x i64> <i64 poison, i64 1>, i8 17)
 ; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
 ;
   %1 = insertelement <2 x i64> %a0, i64 1, i64 1
@@ -96,7 +96,7 @@ define <4 x i64> @test_demanded_elts_pclmulqdq_256_0(<4 x i64> %a0, <4 x i64> %a
 
 define <4 x i64> @test_demanded_elts_pclmulqdq_256_1(<4 x i64> %a0, <4 x i64> %a1) {
 ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_1(
-; CHECK-NEXT:    [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> [[A1:%.*]], i8 1)
+; CHECK-NEXT:    [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 1, i64 poison, i64 1>, <4 x i64> [[A1:%.*]], i8 1)
 ; CHECK-NEXT:    ret <4 x i64> [[RES]]
 ;
   %1 = insertelement <4 x i64> %a0, i64 1, i64 1
@@ -109,7 +109,7 @@ define <4 x i64> @test_demanded_elts_pclmulqdq_256_1(<4 x i64> %a0, <4 x i64> %a
 
 define <4 x i64> @test_demanded_elts_pclmulqdq_256_16(<4 x i64> %a0, <4 x i64> %a1) {
 ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_16(
-; CHECK-NEXT:    [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> [[A0:%.*]], <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 16)
+; CHECK-NEXT:    [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> [[A0:%.*]], <4 x i64> <i64 poison, i64 1, i64 poison, i64 1>, i8 16)
 ; CHECK-NEXT:    ret <4 x i64> [[RES]]
 ;
   %1 = insertelement <4 x i64> %a0, i64 1, i64 1
@@ -122,7 +122,7 @@ define <4 x i64> @test_demanded_elts_pclmulqdq_256_16(<4 x i64> %a0, <4 x i64> %
 
 define <4 x i64> @test_demanded_elts_pclmulqdq_256_17(<4 x i64> %a0, <4 x i64> %a1) {
 ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_17(
-; CHECK-NEXT:    [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 17)
+; CHECK-NEXT:    [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 1, i64 poison, i64 1>, <4 x i64> <i64 poison, i64 1, i64 poison, i64 1>, i8 17)
 ; CHECK-NEXT:    ret <4 x i64> [[RES]]
 ;
   %1 = insertelement <4 x i64> %a0, i64 1, i64 1
@@ -184,7 +184,7 @@ define <8 x i64> @test_demanded_elts_pclmulqdq_512_0(<8 x i64> %a0, <8 x i64> %a
 
 define <8 x i64> @test_demanded_elts_pclmulqdq_512_1(<8 x i64> %a0, <8 x i64> %a1) {
 ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_1(
-; CHECK-NEXT:    [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> [[A1:%.*]], i8 1)
+; CHECK-NEXT:    [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1>, <8 x i64> [[A1:%.*]], i8 1)
 ; CHECK-NEXT:    ret <8 x i64> [[RES]]
 ;
   %1 = insertelement <8 x i64> %a0, i64 1, i64 1
@@ -201,7 +201,7 @@ define <8 x i64> @test_demanded_elts_pclmulqdq_512_1(<8 x i64> %a0, <8 x i64> %a
 
 define <8 x i64> @test_demanded_elts_pclmulqdq_512_16(<8 x i64> %a0, <8 x i64> %a1) {
 ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_16(
-; CHECK-NEXT:    [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> [[A0:%.*]], <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 16)
+; CHECK-NEXT:    [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> [[A0:%.*]], <8 x i64> <i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1>, i8 16)
 ; CHECK-NEXT:    ret <8 x i64> [[RES]]
 ;
   %1 = insertelement <8 x i64> %a0, i64 1, i64 1
@@ -218,7 +218,7 @@ define <8 x i64> @test_demanded_elts_pclmulqdq_512_16(<8 x i64> %a0, <8 x i64> %
 
 define <8 x i64> @test_demanded_elts_pclmulqdq_512_17(<8 x i64> %a0, <8 x i64> %a1) {
 ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_17(
-; CHECK-NEXT:    [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 17)
+; CHECK-NEXT:    [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1>, <8 x i64> <i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1, i64 poison, i64 1>, i8 17)
 ; CHECK-NEXT:    ret <8 x i64> [[RES]]
 ;
   %1 = insertelement <8 x i64> %a0, i64 1, i64 1
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-addsub-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-addsub-inseltpoison.ll
new file mode 100644
index 0000000000000..a4cf1351a787b
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-addsub-inseltpoison.ll
@@ -0,0 +1,194 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+
+declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>)
+declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)
+declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>)
+declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>)
+declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #0
+
+;
+; Demanded Elts
+;
+
+define double @elts_addsub_v2f64(<2 x double> %0, <2 x double> %1) {
+; CHECK-LABEL: @elts_addsub_v2f64(
+; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1:%.*]], <2 x double> undef, <2 x i32> <i32 1, i32 undef>
+; CHECK-NEXT:    [[TMP4:%.*]] = fsub <2 x double> [[TMP0:%.*]], [[TMP3]]
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0
+; CHECK-NEXT:    ret double [[TMP5]]
+;
+  %3 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+  %4 = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> <i32 1, i32 1>
+  %5 = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %3, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define double @elts_addsub_v2f64_sub(<2 x double> %0, <2 x double> %1) {
+; CHECK-LABEL: @elts_addsub_v2f64_sub(
+; CHECK-NEXT:    [[TMP3:%.*]] = fsub <2 x double> [[TMP0:%.*]], [[TMP1:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
+; CHECK-NEXT:    ret double [[TMP4]]
+;
+  %3 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+  %4 = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> <i32 0, i32 0>
+  %5 = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %3, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define float @elts_addsub_v4f32(<4 x float> %0, <4 x float> %1) {
+; CHECK-LABEL: @elts_addsub_v4f32(
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP0:%.*]], <4 x float> [[TMP1:%.*]])
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP6:%.*]] = fadd float [[TMP4]], [[TMP5]]
+; CHECK-NEXT:    ret float [[TMP6]]
+;
+  %3 = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %4 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %5 = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %3, <4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 0
+  %7 = extractelement <4 x float> %5, i32 1
+  %8 = fadd float %6, %7
+  ret float %8
+}
+
+define float @elts_addsub_v4f32_add(<4 x float> %0, <4 x float> %1) {
+; CHECK-LABEL: @elts_addsub_v4f32_add(
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd <4 x float> [[TMP0:%.*]], [[TMP1:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP6:%.*]] = fadd float [[TMP4]], [[TMP5]]
+; CHECK-NEXT:    ret float [[TMP6]]
+;
+  %3 = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %4 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %5 = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %3, <4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 1
+  %7 = extractelement <4 x float> %5, i32 3
+  %8 = fadd float %6, %7
+  ret float %8
+}
+
+define double @elts_addsub_v4f64(<4 x double> %0, <4 x double> %1) {
+; CHECK-LABEL: @elts_addsub_v4f64(
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> [[TMP0:%.*]], <4 x double> [[TMP1:%.*]])
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x double> [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x double> [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP6:%.*]] = fadd double [[TMP4]], [[TMP5]]
+; CHECK-NEXT:    ret double [[TMP6]]
+;
+  %3 = shufflevector <4 x double> %0, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>
+  %4 = shufflevector <4 x double> %1, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>
+  %5 = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %3, <4 x double> %4)
+  %6 = extractelement <4 x double> %5, i32 0
+  %7 = extractelement <4 x double> %5, i32 1
+  %8 = fadd double %6, %7
+  ret double %8
+}
+
+define double @elts_addsub_v4f64_add(<4 x double> %0, <4 x double> %1) {
+; CHECK-LABEL: @elts_addsub_v4f64_add(
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd <4 x double> [[TMP0:%.*]], [[TMP1:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x double> [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x double> [[TMP3]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = fadd double [[TMP4]], [[TMP5]]
+; CHECK-NEXT:    ret double [[TMP6]]
+;
+  %3 = shufflevector <4 x double> %0, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>
+  %4 = shufflevector <4 x double> %1, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3>
+  %5 = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %3, <4 x double> %4)
+  %6 = extractelement <4 x double> %5, i32 1
+  %7 = extractelement <4 x double> %5, i32 3
+  %8 = fadd double %6, %7
+  ret double %8
+}
+
+define float @elts_addsub_v8f32(<8 x float> %0, <8 x float> %1) {
+; CHECK-LABEL: @elts_addsub_v8f32(
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> [[TMP0:%.*]], <8 x float> [[TMP1:%.*]])
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x float> [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x float> [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP6:%.*]] = fadd float [[TMP4]], [[TMP5]]
+; CHECK-NEXT:    ret float [[TMP6]]
+;
+  %3 = shufflevector <8 x float> %0, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>
+  %4 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>
+  %5 = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %3, <8 x float> %4)
+  %6 = extractelement <8 x float> %5, i32 0
+  %7 = extractelement <8 x float> %5, i32 1
+  %8 = fadd float %6, %7
+  ret float %8
+}
+
+define float @elts_addsub_v8f32_sub(<8 x float> %0, <8 x float> %1) {
+; CHECK-LABEL: @elts_addsub_v8f32_sub(
+; CHECK-NEXT:    [[TMP3:%.*]] = fsub <8 x float> [[TMP0:%.*]], [[TMP1:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x float> [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x float> [[TMP3]], i32 4
+; CHECK-NEXT:    [[TMP6:%.*]] = fadd float [[TMP4]], [[TMP5]]
+; CHECK-NEXT:    ret float [[TMP6]]
+;
+  %3 = shufflevector <8 x float> %0, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>
+  %4 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4>
+  %5 = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %3, <8 x float> %4)
+  %6 = extractelement <8 x float> %5, i32 0
+  %7 = extractelement <8 x float> %5, i32 4
+  %8 = fadd float %6, %7
+  ret float %8
+}
+
+define void @PR46277(float %0, float %1, float %2, float %3, <4 x float> %4, float* %5) {
+; CHECK-LABEL: @PR46277(
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x float> poison, float [[TMP0:%.*]], i32 0
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[TMP1:%.*]], i32 1
+; CHECK-NEXT:    [[TMP9:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP8]], <4 x float> [[TMP4:%.*]])
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <4 x float> [[TMP9]], i32 0
+; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr inbounds float, float* [[TMP5:%.*]], i64 1
+; CHECK-NEXT:    store float [[TMP10]], float* [[TMP5]], align 4
+; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <4 x float> [[TMP9]], i32 1
+; CHECK-NEXT:    store float [[TMP12]], float* [[TMP11]], align 4
+; CHECK-NEXT:    ret void
+;
+  %7 = insertelement <4 x float> poison, float %0, i32 0
+  %8 = insertelement <4 x float> %7, float %1, i32 1
+  %9 = insertelement <4 x float> %8, float %2, i32 2
+  %10 = insertelement <4 x float> %9, float %3, i32 3
+  %11 = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %10, <4 x float> %4)
+  %12 = extractelement <4 x float> %11, i32 0
+  %13 = getelementptr inbounds float, float* %5, i64 1
+  store float %12, float* %5, align 4
+  %14 = extractelement <4 x float> %11, i32 1
+  store float %14, float* %13, align 4
+  ret void
+}
+
+define double @PR48476_fsub(<2 x double> %x) {
+; CHECK-LABEL: @PR48476_fsub(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <2 x double> <double 0.000000e+00, double poison>, [[X:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]], <2 x double> [[X]], i8 6)
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <2 x double> [[T2]], i32 0
+; CHECK-NEXT:    ret double [[VECEXT]]
+;
+  %t1 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> zeroinitializer, <2 x double> %x)
+  %t2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %t1, <2 x double> %x, i8 6)
+  %vecext = extractelement <2 x double> %t2, i32 0
+  ret double %vecext
+}
+
+define double @PR48476_fadd_fsub(<2 x double> %x) {
+; CHECK-LABEL: @PR48476_fadd_fsub(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x double> [[X:%.*]], <double poison, double 0.000000e+00>
+; CHECK-NEXT:    [[S:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> undef, <2 x i32> <i32 1, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = fsub <2 x double> [[S]], [[X]]
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
+; CHECK-NEXT:    ret double [[VECEXT]]
+;
+  %t1 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> zeroinitializer, <2 x double> %x)
+  %s = shufflevector <2 x double> %t1, <2 x double> undef, <2 x i32> <i32 1, i32 0>
+  %t2 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %s, <2 x double> %x)
+  %vecext = extractelement <2 x double> %t2, i32 0
+  ret double %vecext
+}
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll b/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll
index 0b9831be8fcf7..9551492a0ca32 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll
@@ -167,7 +167,7 @@ define void @PR46277(float %0, float %1, float %2, float %3, <4 x float> %4, flo
 
 define double @PR48476_fsub(<2 x double> %x) {
 ; CHECK-LABEL: @PR48476_fsub(
-; CHECK-NEXT:    [[TMP1:%.*]] = fsub <2 x double> <double 0.000000e+00, double undef>, [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <2 x double> <double 0.000000e+00, double poison>, [[X:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]], <2 x double> [[X]], i8 6)
 ; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <2 x double> [[T2]], i32 0
 ; CHECK-NEXT:    ret double [[VECEXT]]
@@ -180,7 +180,7 @@ define double @PR48476_fsub(<2 x double> %x) {
 
 define double @PR48476_fadd_fsub(<2 x double> %x) {
 ; CHECK-LABEL: @PR48476_fadd_fsub(
-; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x double> [[X:%.*]], <double undef, double 0.000000e+00>
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x double> [[X:%.*]], <double poison, double 0.000000e+00>
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> undef, <2 x i32> <i32 1, i32 undef>
 ; CHECK-NEXT:    [[TMP2:%.*]] = fsub <2 x double> [[S]], [[X]]
 ; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
new file mode 100644
index 0000000000000..199b6f0f2b2c7
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll
@@ -0,0 +1,3407 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+declare <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
+
+define <4 x float> @test_add_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_add_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd float [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x float> [[A]], float [[TMP3]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP4]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_add_ss_round(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_add_ss_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_add_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_add_ss_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd float [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i1> [[TMP4]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> [[A]], float [[TMP7]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP8]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_add_ss_mask_round(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_add_ss_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]], i8 [[MASK:%.*]], i32 8)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 8)
+  ret <4 x float> %4
+}
+
+define float @test_add_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_add_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 8)
+  %10 = extractelement <4 x float> %9, i32 1
+  ret float %10
+}
+
+declare <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
+
+define <2 x double> @test_add_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_add_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd double [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x double> [[A]], double [[TMP3]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP4]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_add_sd_round(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_add_sd_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_add_sd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd double [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i1> [[TMP4]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x double> [[A]], double [[TMP7]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP8]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_add_sd_mask_round(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_add_sd_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]], i8 [[MASK:%.*]], i32 8)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 8)
+  ret <2 x double> %2
+}
+
+define double @test_add_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_add_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 8)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
+
+define <4 x float> @test_sub_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_sub_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fsub float [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x float> [[A]], float [[TMP3]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP4]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_sub_ss_round(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_sub_ss_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_sub_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_sub_ss_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fsub float [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i1> [[TMP4]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> [[A]], float [[TMP7]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP8]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_sub_ss_mask_round(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_sub_ss_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]], i8 [[MASK:%.*]], i32 8)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 8)
+  ret <4 x float> %4
+}
+
+define float @test_sub_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_sub_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 8)
+  %10 = extractelement <4 x float> %9, i32 1
+  ret float %10
+}
+
+declare <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
+
+define <2 x double> @test_sub_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_sub_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fsub double [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x double> [[A]], double [[TMP3]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP4]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_sub_sd_round(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_sub_sd_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_sub_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_sub_sd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fsub double [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i1> [[TMP4]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x double> [[A]], double [[TMP7]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP8]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_sub_sd_mask_round(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_sub_sd_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]], i8 [[MASK:%.*]], i32 8)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 8)
+  ret <2 x double> %2
+}
+
+define double @test_sub_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_sub_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 8)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
+
+define <4 x float> @test_mul_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_mul_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fmul float [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x float> [[A]], float [[TMP3]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP4]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_mul_ss_round(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_mul_ss_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_mul_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mul_ss_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fmul float [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i1> [[TMP4]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> [[A]], float [[TMP7]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP8]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_mul_ss_mask_round(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mul_ss_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]], i8 [[MASK:%.*]], i32 8)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 8)
+  ret <4 x float> %4
+}
+
+define float @test_mul_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_mul_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 8)
+  %10 = extractelement <4 x float> %9, i32 1
+  ret float %10
+}
+
+declare <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
+
+define <2 x double> @test_mul_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_mul_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fmul double [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x double> [[A]], double [[TMP3]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP4]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_mul_sd_round(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_mul_sd_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_mul_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mul_sd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fmul double [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i1> [[TMP4]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x double> [[A]], double [[TMP7]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP8]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_mul_sd_mask_round(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mul_sd_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]], i8 [[MASK:%.*]], i32 8)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 8)
+  ret <2 x double> %2
+}
+
+define double @test_mul_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_mul_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 8)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
+
+define <4 x float> @test_div_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_div_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fdiv float [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x float> [[A]], float [[TMP3]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP4]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_div_ss_round(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_div_ss_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_div_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_div_ss_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fdiv float [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i1> [[TMP4]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], float [[TMP3]], float [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> [[A]], float [[TMP7]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP8]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_div_ss_mask_round(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_div_ss_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]], i8 [[MASK:%.*]], i32 8)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 8)
+  ret <4 x float> %4
+}
+
+define float @test_div_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_div_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 8)
+  %10 = extractelement <4 x float> %9, i32 1
+  ret float %10
+}
+
+declare <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
+
+define <2 x double> @test_div_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_div_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fdiv double [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x double> [[A]], double [[TMP3]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP4]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_div_sd_round(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_div_sd_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_div_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_div_sd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = fdiv double [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i1> [[TMP4]], i64 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP5]], double [[TMP3]], double [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x double> [[A]], double [[TMP7]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP8]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_div_sd_mask_round(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_div_sd_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]], i8 [[MASK:%.*]], i32 8)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 8)
+  ret <2 x double> %2
+}
+
+define double @test_div_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_div_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 8)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
+
+define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_max_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_max_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_max_ss_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]], i8 [[MASK:%.*]], i32 4)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 4)
+  ret <4 x float> %4
+}
+
+define float @test_max_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_max_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 8)
+  %10 = extractelement <4 x float> %9, i32 1
+  ret float %10
+}
+
+declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
+
+define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_max_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_max_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_max_sd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]], i8 [[MASK:%.*]], i32 4)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 4)
+  ret <2 x double> %2
+}
+
+define double @test_max_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_max_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 8)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+declare <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
+
+define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_min_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
+  ret <4 x float> %4
+}
+
+define <4 x float> @test_min_ss_mask(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_min_ss_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]], i8 [[MASK:%.*]], i32 4)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> %a, <4 x float> %b, <4 x float> %3, i8 %mask, i32 4)
+  ret <4 x float> %4
+}
+
+define float @test_min_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_min_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> %4, <4 x float> %8, <4 x float> undef, i8 -1, i32 8)
+  %10 = extractelement <4 x float> %9, i32 1
+  ret float %10
+}
+
+declare <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
+
+define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_min_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
+  ret <2 x double> %2
+}
+
+define <2 x double> @test_min_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_min_sd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]], i8 [[MASK:%.*]], i32 4)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> %a, <2 x double> %b, <2 x double> %1, i8 %mask, i32 4)
+  ret <2 x double> %2
+}
+
+define double @test_min_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_min_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> %2, <2 x double> %4, <2 x double> undef, i8 -1, i32 8)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+declare i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float>, <4 x float>, i32, i8, i32)
+
+define i8 @test_cmp_ss(<4 x float> %a, <4 x float> %b, i8 %mask) {
+; CHECK-LABEL: @test_cmp_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], i32 3, i8 [[MASK:%.*]], i32 4)
+; CHECK-NEXT:    ret i8 [[TMP1]]
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = insertelement <4 x float> %b, float 4.000000e+00, i32 1
+  %5 = insertelement <4 x float> %4, float 5.000000e+00, i32 2
+  %6 = insertelement <4 x float> %5, float 6.000000e+00, i32 3
+  %7 = tail call i8 @llvm.x86.avx512.mask.cmp.ss(<4 x float> %3, <4 x float> %6, i32 3, i8 %mask, i32 4)
+  ret i8 %7
+}
+
+declare i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double>, <2 x double>, i32, i8, i32)
+
+define i8 @test_cmp_sd(<2 x double> %a, <2 x double> %b, i8 %mask) {
+; CHECK-LABEL: @test_cmp_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], i32 3, i8 [[MASK:%.*]], i32 4)
+; CHECK-NEXT:    ret i8 [[TMP1]]
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1
+  %2 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
+  %3 = tail call i8 @llvm.x86.avx512.mask.cmp.sd(<2 x double> %1, <2 x double> %2, i32 3, i8 %mask, i32 4)
+  ret i8 %3
+}
+
+define i64 @test(float %f, double %d) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:    [[V03:%.*]] = insertelement <4 x float> poison, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[T0:%.*]] = tail call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> [[V03]], i32 4)
+; CHECK-NEXT:    [[V13:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
+; CHECK-NEXT:    [[T1:%.*]] = tail call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> [[V13]], i32 4)
+; CHECK-NEXT:    [[V23:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
+; CHECK-NEXT:    [[T2:%.*]] = tail call i32 @llvm.x86.avx512.cvttss2si(<4 x float> [[V23]], i32 4)
+; CHECK-NEXT:    [[V33:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
+; CHECK-NEXT:    [[T3:%.*]] = tail call i64 @llvm.x86.avx512.cvttss2si64(<4 x float> [[V33]], i32 4)
+; CHECK-NEXT:    [[V41:%.*]] = insertelement <2 x double> poison, double [[D:%.*]], i32 0
+; CHECK-NEXT:    [[T4:%.*]] = tail call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> [[V41]], i32 4)
+; CHECK-NEXT:    [[V51:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
+; CHECK-NEXT:    [[T5:%.*]] = tail call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> [[V51]], i32 4)
+; CHECK-NEXT:    [[V61:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
+; CHECK-NEXT:    [[T6:%.*]] = tail call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> [[V61]], i32 4)
+; CHECK-NEXT:    [[V71:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
+; CHECK-NEXT:    [[T7:%.*]] = tail call i64 @llvm.x86.avx512.cvttsd2si64(<2 x double> [[V71]], i32 4)
+; CHECK-NEXT:    [[T8:%.*]] = add i32 [[T0]], [[T2]]
+; CHECK-NEXT:    [[T9:%.*]] = add i32 [[T4]], [[T6]]
+; CHECK-NEXT:    [[T10:%.*]] = add i32 [[T8]], [[T9]]
+; CHECK-NEXT:    [[T11:%.*]] = sext i32 [[T10]] to i64
+; CHECK-NEXT:    [[T12:%.*]] = add i64 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T13:%.*]] = add i64 [[T5]], [[T7]]
+; CHECK-NEXT:    [[T14:%.*]] = add i64 [[T12]], [[T13]]
+; CHECK-NEXT:    [[T15:%.*]] = add i64 [[T14]], [[T11]]
+; CHECK-NEXT:    ret i64 [[T15]]
+;
+  %v00 = insertelement <4 x float> poison, float %f, i32 0
+  %v01 = insertelement <4 x float> %v00, float 0.000000e+00, i32 1
+  %v02 = insertelement <4 x float> %v01, float 0.000000e+00, i32 2
+  %v03 = insertelement <4 x float> %v02, float 0.000000e+00, i32 3
+  %t0 = tail call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> %v03, i32 4)
+  %v10 = insertelement <4 x float> poison, float %f, i32 0
+  %v11 = insertelement <4 x float> %v10, float 0.000000e+00, i32 1
+  %v12 = insertelement <4 x float> %v11, float 0.000000e+00, i32 2
+  %v13 = insertelement <4 x float> %v12, float 0.000000e+00, i32 3
+  %t1 = tail call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> %v13, i32 4)
+  %v20 = insertelement <4 x float> poison, float %f, i32 0
+  %v21 = insertelement <4 x float> %v20, float 0.000000e+00, i32 1
+  %v22 = insertelement <4 x float> %v21, float 0.000000e+00, i32 2
+  %v23 = insertelement <4 x float> %v22, float 0.000000e+00, i32 3
+  %t2 = tail call i32 @llvm.x86.avx512.cvttss2si(<4 x float> %v23, i32 4)
+  %v30 = insertelement <4 x float> poison, float %f, i32 0
+  %v31 = insertelement <4 x float> %v30, float 0.000000e+00, i32 1
+  %v32 = insertelement <4 x float> %v31, float 0.000000e+00, i32 2
+  %v33 = insertelement <4 x float> %v32, float 0.000000e+00, i32 3
+  %t3 = tail call i64 @llvm.x86.avx512.cvttss2si64(<4 x float> %v33, i32 4)
+  %v40 = insertelement <2 x double> poison, double %d, i32 0
+  %v41 = insertelement <2 x double> %v40, double 0.000000e+00, i32 1
+  %t4 = tail call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> %v41, i32 4)
+  %v50 = insertelement <2 x double> poison, double %d, i32 0
+  %v51 = insertelement <2 x double> %v50, double 0.000000e+00, i32 1
+  %t5 = tail call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> %v51, i32 4)
+  %v60 = insertelement <2 x double> poison, double %d, i32 0
+  %v61 = insertelement <2 x double> %v60, double 0.000000e+00, i32 1
+  %t6 = tail call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> %v61, i32 4)
+  %v70 = insertelement <2 x double> poison, double %d, i32 0
+  %v71 = insertelement <2 x double> %v70, double 0.000000e+00, i32 1
+  %t7 = tail call i64 @llvm.x86.avx512.cvttsd2si64(<2 x double> %v71, i32 4)
+  %t8 = add i32 %t0, %t2
+  %t9 = add i32 %t4, %t6
+  %t10 = add i32 %t8, %t9
+  %t11 = sext i32 %t10 to i64
+  %t12 = add i64 %t1, %t3
+  %t13 = add i64 %t5, %t7
+  %t14 = add i64 %t12, %t13
+  %t15 = add i64 %t11, %t14
+  ret i64 %t15
+}
+
+declare i32 @llvm.x86.avx512.vcvtss2si32(<4 x float>, i32)
+declare i64 @llvm.x86.avx512.vcvtss2si64(<4 x float>, i32)
+declare i32 @llvm.x86.avx512.cvttss2si(<4 x float>, i32)
+declare i64 @llvm.x86.avx512.cvttss2si64(<4 x float>, i32)
+declare i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double>, i32)
+declare i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double>, i32)
+declare i32 @llvm.x86.avx512.cvttsd2si(<2 x double>, i32)
+declare i64 @llvm.x86.avx512.cvttsd2si64(<2 x double>, i32)
+
+define i64 @test2(float %f, double %d) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    [[V03:%.*]] = insertelement <4 x float> poison, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[T0:%.*]] = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> [[V03]], i32 4)
+; CHECK-NEXT:    [[V13:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
+; CHECK-NEXT:    [[T1:%.*]] = tail call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> [[V13]], i32 4)
+; CHECK-NEXT:    [[V23:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
+; CHECK-NEXT:    [[T2:%.*]] = tail call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> [[V23]], i32 4)
+; CHECK-NEXT:    [[V33:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
+; CHECK-NEXT:    [[T3:%.*]] = tail call i64 @llvm.x86.avx512.cvttss2usi64(<4 x float> [[V33]], i32 4)
+; CHECK-NEXT:    [[V41:%.*]] = insertelement <2 x double> poison, double [[D:%.*]], i32 0
+; CHECK-NEXT:    [[T4:%.*]] = tail call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> [[V41]], i32 4)
+; CHECK-NEXT:    [[V51:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
+; CHECK-NEXT:    [[T5:%.*]] = tail call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> [[V51]], i32 4)
+; CHECK-NEXT:    [[V61:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
+; CHECK-NEXT:    [[T6:%.*]] = tail call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> [[V61]], i32 4)
+; CHECK-NEXT:    [[V71:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
+; CHECK-NEXT:    [[T7:%.*]] = tail call i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double> [[V71]], i32 4)
+; CHECK-NEXT:    [[T8:%.*]] = add i32 [[T0]], [[T2]]
+; CHECK-NEXT:    [[T9:%.*]] = add i32 [[T4]], [[T6]]
+; CHECK-NEXT:    [[T10:%.*]] = add i32 [[T8]], [[T9]]
+; CHECK-NEXT:    [[T11:%.*]] = sext i32 [[T10]] to i64
+; CHECK-NEXT:    [[T12:%.*]] = add i64 [[T1]], [[T3]]
+; CHECK-NEXT:    [[T13:%.*]] = add i64 [[T5]], [[T7]]
+; CHECK-NEXT:    [[T14:%.*]] = add i64 [[T12]], [[T13]]
+; CHECK-NEXT:    [[T15:%.*]] = add i64 [[T14]], [[T11]]
+; CHECK-NEXT:    ret i64 [[T15]]
+;
+  %v00 = insertelement <4 x float> poison, float %f, i32 0
+  %v01 = insertelement <4 x float> %v00, float 0.000000e+00, i32 1
+  %v02 = insertelement <4 x float> %v01, float 0.000000e+00, i32 2
+  %v03 = insertelement <4 x float> %v02, float 0.000000e+00, i32 3
+  %t0 = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> %v03, i32 4)
+  %v10 = insertelement <4 x float> poison, float %f, i32 0
+  %v11 = insertelement <4 x float> %v10, float 0.000000e+00, i32 1
+  %v12 = insertelement <4 x float> %v11, float 0.000000e+00, i32 2
+  %v13 = insertelement <4 x float> %v12, float 0.000000e+00, i32 3
+  %t1 = tail call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> %v13, i32 4)
+  %v20 = insertelement <4 x float> poison, float %f, i32 0
+  %v21 = insertelement <4 x float> %v20, float 0.000000e+00, i32 1
+  %v22 = insertelement <4 x float> %v21, float 0.000000e+00, i32 2
+  %v23 = insertelement <4 x float> %v22, float 0.000000e+00, i32 3
+  %t2 = tail call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> %v23, i32 4)
+  %v30 = insertelement <4 x float> poison, float %f, i32 0
+  %v31 = insertelement <4 x float> %v30, float 0.000000e+00, i32 1
+  %v32 = insertelement <4 x float> %v31, float 0.000000e+00, i32 2
+  %v33 = insertelement <4 x float> %v32, float 0.000000e+00, i32 3
+  %t3 = tail call i64 @llvm.x86.avx512.cvttss2usi64(<4 x float> %v33, i32 4)
+  %v40 = insertelement <2 x double> poison, double %d, i32 0
+  %v41 = insertelement <2 x double> %v40, double 0.000000e+00, i32 1
+  %t4 = tail call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> %v41, i32 4)
+  %v50 = insertelement <2 x double> poison, double %d, i32 0
+  %v51 = insertelement <2 x double> %v50, double 0.000000e+00, i32 1
+  %t5 = tail call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> %v51, i32 4)
+  %v60 = insertelement <2 x double> poison, double %d, i32 0
+  %v61 = insertelement <2 x double> %v60, double 0.000000e+00, i32 1
+  %t6 = tail call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> %v61, i32 4)
+  %v70 = insertelement <2 x double> poison, double %d, i32 0
+  %v71 = insertelement <2 x double> %v70, double 0.000000e+00, i32 1
+  %t7 = tail call i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double> %v71, i32 4)
+  %t8 = add i32 %t0, %t2
+  %t9 = add i32 %t4, %t6
+  %t10 = add i32 %t8, %t9
+  %t11 = sext i32 %t10 to i64
+  %t12 = add i64 %t1, %t3
+  %t13 = add i64 %t5, %t7
+  %t14 = add i64 %t12, %t13
+  %t15 = add i64 %t11, %t14
+  ret i64 %t15
+}
+
+declare i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float>, i32)
+declare i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float>, i32)
+declare i32 @llvm.x86.avx512.cvttss2usi(<4 x float>, i32)
+declare i64 @llvm.x86.avx512.cvttss2usi64(<4 x float>, i32)
+declare i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double>, i32)
+declare i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double>, i32)
+declare i32 @llvm.x86.avx512.cvttsd2usi(<2 x double>, i32)
+declare i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double>, i32)
+
+declare float @llvm.fma.f32(float, float, float) #1
+
+define <4 x float> @test_mask_vfmadd_ss(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask_vfmadd_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call float @llvm.fma.f32(float [[TMP1]], float [[TMP2]], float [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], float [[TMP4]], float [[TMP1]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> [[A]], float [[TMP7]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP8]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = insertelement <4 x float> %c, float 4.000000e+00, i32 1
+  %5 = insertelement <4 x float> %4, float 5.000000e+00, i32 2
+  %6 = insertelement <4 x float> %5, float 6.000000e+00, i32 3
+  %7 = extractelement <4 x float> %a, i64 0
+  %8 = extractelement <4 x float> %3, i64 0
+  %9 = extractelement <4 x float> %6, i64 0
+  %10 = call float @llvm.fma.f32(float %7, float %8, float %9)
+  %11 = bitcast i8 %mask to <8 x i1>
+  %12 = extractelement <8 x i1> %11, i64 0
+  %13 = select i1 %12, float %10, float %7
+  %14 = insertelement <4 x float> %a, float %13, i64 0
+  ret <4 x float> %14
+}
+
+define float @test_mask_vfmadd_ss_0(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask_vfmadd_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call float @llvm.fma.f32(float [[TMP1]], float [[TMP2]], float [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], float [[TMP4]], float [[TMP1]]
+; CHECK-NEXT:    ret float [[TMP7]]
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = extractelement <4 x float> %3, i64 0
+  %5 = extractelement <4 x float> %b, i64 0
+  %6 = extractelement <4 x float> %c, i64 0
+  %7 = call float @llvm.fma.f32(float %4, float %5, float %6)
+  %8 = bitcast i8 %mask to <8 x i1>
+  %9 = extractelement <8 x i1> %8, i64 0
+  %10 = select i1 %9, float %7, float %4
+  %11 = insertelement <4 x float> %3, float %10, i64 0
+  %12 = extractelement <4 x float> %11, i32 0
+  ret float %12
+}
+
+define float @test_mask_vfmadd_ss_1(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask_vfmadd_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = extractelement <4 x float> %3, i64 0
+  %5 = extractelement <4 x float> %b, i64 0
+  %6 = extractelement <4 x float> %c, i64 0
+  %7 = call float @llvm.fma.f32(float %4, float %5, float %6)
+  %8 = bitcast i8 %mask to <8 x i1>
+  %9 = extractelement <8 x i1> %8, i64 0
+  %10 = select i1 %9, float %7, float %4
+  %11 = insertelement <4 x float> %3, float %10, i64 0
+  %12 = extractelement <4 x float> %11, i32 1
+  ret float %12
+}
+
+declare double @llvm.fma.f64(double, double, double) #1
+
+define <2 x double> @test_mask_vfmadd_sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask_vfmadd_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call double @llvm.fma.f64(double [[TMP1]], double [[TMP2]], double [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], double [[TMP4]], double [[TMP1]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x double> [[A]], double [[TMP7]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP8]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = insertelement <2 x double> %c, double 2.000000e+00, i32 1
+  %3 = extractelement <2 x double> %a, i64 0
+  %4 = extractelement <2 x double> %1, i64 0
+  %5 = extractelement <2 x double> %2, i64 0
+  %6 = call double @llvm.fma.f64(double %3, double %4, double %5)
+  %7 = bitcast i8 %mask to <8 x i1>
+  %8 = extractelement <8 x i1> %7, i64 0
+  %9 = select i1 %8, double %6, double %3
+  %10 = insertelement <2 x double> %a, double %9, i64 0
+  ret <2 x double> %10
+}
+
+define double @test_mask_vfmadd_sd_0(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask_vfmadd_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call double @llvm.fma.f64(double [[TMP1]], double [[TMP2]], double [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], double [[TMP4]], double [[TMP1]]
+; CHECK-NEXT:    ret double [[TMP7]]
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1
+  %2 = extractelement <2 x double> %1, i64 0
+  %3 = extractelement <2 x double> %b, i64 0
+  %4 = extractelement <2 x double> %c, i64 0
+  %5 = call double @llvm.fma.f64(double %2, double %3, double %4)
+  %6 = bitcast i8 %mask to <8 x i1>
+  %7 = extractelement <8 x i1> %6, i64 0
+  %8 = select i1 %7, double %5, double %2
+  %9 = insertelement <2 x double> %1, double %8, i64 0
+  %10 = extractelement <2 x double> %9, i32 0
+  ret double %10
+}
+
+define double @test_mask_vfmadd_sd_1(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask_vfmadd_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1
+  %2 = extractelement <2 x double> %1, i64 0
+  %3 = extractelement <2 x double> %b, i64 0
+  %4 = extractelement <2 x double> %c, i64 0
+  %5 = call double @llvm.fma.f64(double %2, double %3, double %4)
+  %6 = bitcast i8 %mask to <8 x i1>
+  %7 = extractelement <8 x i1> %6, i64 0
+  %8 = select i1 %7, double %5, double %2
+  %9 = insertelement <2 x double> %1, double %8, i64 0
+  %10 = extractelement <2 x double> %9, i32 1
+  ret double %10
+}
+
+define <4 x float> @test_maskz_vfmadd_ss(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_maskz_vfmadd_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call float @llvm.fma.f32(float [[TMP1]], float [[TMP2]], float [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], float [[TMP4]], float 0.000000e+00
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> [[A]], float [[TMP7]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP8]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = insertelement <4 x float> %c, float 4.000000e+00, i32 1
+  %5 = insertelement <4 x float> %4, float 5.000000e+00, i32 2
+  %6 = insertelement <4 x float> %5, float 6.000000e+00, i32 3
+  %7 = extractelement <4 x float> %a, i64 0
+  %8 = extractelement <4 x float> %3, i64 0
+  %9 = extractelement <4 x float> %6, i64 0
+  %10 = call float @llvm.fma.f32(float %7, float %8, float %9)
+  %11 = bitcast i8 %mask to <8 x i1>
+  %12 = extractelement <8 x i1> %11, i64 0
+  %13 = select i1 %12, float %10, float 0.000000e+00
+  %14 = insertelement <4 x float> %a, float %13, i64 0
+  ret <4 x float> %14
+}
+
+define float @test_maskz_vfmadd_ss_0(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_maskz_vfmadd_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call float @llvm.fma.f32(float [[TMP1]], float [[TMP2]], float [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], float [[TMP4]], float 0.000000e+00
+; CHECK-NEXT:    ret float [[TMP7]]
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = extractelement <4 x float> %3, i64 0
+  %5 = extractelement <4 x float> %b, i64 0
+  %6 = extractelement <4 x float> %c, i64 0
+  %7 = call float @llvm.fma.f32(float %4, float %5, float %6)
+  %8 = bitcast i8 %mask to <8 x i1>
+  %9 = extractelement <8 x i1> %8, i64 0
+  %10 = select i1 %9, float %7, float 0.000000e+00
+  %11 = insertelement <4 x float> %3, float %10, i64 0
+  %12 = extractelement <4 x float> %11, i32 0
+  ret float %12
+}
+
+define float @test_maskz_vfmadd_ss_1(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_maskz_vfmadd_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = extractelement <4 x float> %3, i64 0
+  %5 = extractelement <4 x float> %b, i64 0
+  %6 = extractelement <4 x float> %c, i64 0
+  %7 = call float @llvm.fma.f32(float %4, float %5, float %6)
+  %8 = bitcast i8 %mask to <8 x i1>
+  %9 = extractelement <8 x i1> %8, i64 0
+  %10 = select i1 %9, float %7, float 0.000000e+00
+  %11 = insertelement <4 x float> %3, float %10, i64 0
+  %12 = extractelement <4 x float> %11, i32 1
+  ret float %12
+}
+
+define <2 x double> @test_maskz_vfmadd_sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_maskz_vfmadd_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call double @llvm.fma.f64(double [[TMP1]], double [[TMP2]], double [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], double [[TMP4]], double 0.000000e+00
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x double> [[A]], double [[TMP7]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP8]]
+;
+  %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
+  %2 = insertelement <2 x double> %c, double 2.000000e+00, i32 1
+  %3 = extractelement <2 x double> %a, i64 0
+  %4 = extractelement <2 x double> %1, i64 0
+  %5 = extractelement <2 x double> %2, i64 0
+  %6 = call double @llvm.fma.f64(double %3, double %4, double %5)
+  %7 = bitcast i8 %mask to <8 x i1>
+  %8 = extractelement <8 x i1> %7, i64 0
+  %9 = select i1 %8, double %6, double 0.000000e+00
+  %10 = insertelement <2 x double> %a, double %9, i64 0
+  ret <2 x double> %10
+}
+
+define double @test_maskz_vfmadd_sd_0(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_maskz_vfmadd_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call double @llvm.fma.f64(double [[TMP1]], double [[TMP2]], double [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], double [[TMP4]], double 0.000000e+00
+; CHECK-NEXT:    ret double [[TMP7]]
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1
+  %2 = extractelement <2 x double> %1, i64 0
+  %3 = extractelement <2 x double> %b, i64 0
+  %4 = extractelement <2 x double> %c, i64 0
+  %5 = call double @llvm.fma.f64(double %2, double %3, double %4)
+  %6 = bitcast i8 %mask to <8 x i1>
+  %7 = extractelement <8 x i1> %6, i64 0
+  %8 = select i1 %7, double %5, double 0.000000e+00
+  %9 = insertelement <2 x double> %1, double %8, i64 0
+  %10 = extractelement <2 x double> %9, i32 0
+  ret double %10
+}
+
+define double @test_maskz_vfmadd_sd_1(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_maskz_vfmadd_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1
+  %2 = extractelement <2 x double> %1, i64 0
+  %3 = extractelement <2 x double> %b, i64 0
+  %4 = extractelement <2 x double> %c, i64 0
+  %5 = call double @llvm.fma.f64(double %2, double %3, double %4)
+  %6 = bitcast i8 %mask to <8 x i1>
+  %7 = extractelement <8 x i1> %6, i64 0
+  %8 = select i1 %7, double %5, double 0.000000e+00
+  %9 = insertelement <2 x double> %1, double %8, i64 0
+  %10 = extractelement <2 x double> %9, i32 1
+  ret double %10
+}
+
+define <4 x float> @test_mask3_vfmadd_ss(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmadd_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call float @llvm.fma.f32(float [[TMP1]], float [[TMP2]], float [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], float [[TMP4]], float [[TMP3]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <4 x float> [[C]], float [[TMP7]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP8]]
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = insertelement <4 x float> %b, float 4.000000e+00, i32 1
+  %5 = insertelement <4 x float> %4, float 5.000000e+00, i32 2
+  %6 = insertelement <4 x float> %5, float 6.000000e+00, i32 3
+  %7 = extractelement <4 x float> %3, i64 0
+  %8 = extractelement <4 x float> %6, i64 0
+  %9 = extractelement <4 x float> %c, i64 0
+  %10 = call float @llvm.fma.f32(float %7, float %8, float %9)
+  %11 = bitcast i8 %mask to <8 x i1>
+  %12 = extractelement <8 x i1> %11, i64 0
+  %13 = select i1 %12, float %10, float %9
+  %14 = insertelement <4 x float> %c, float %13, i64 0
+  ret <4 x float> %14
+}
+
+define float @test_mask3_vfmadd_ss_0(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmadd_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[C:%.*]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call float @llvm.fma.f32(float [[TMP1]], float [[TMP2]], float [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], float [[TMP4]], float [[TMP3]]
+; CHECK-NEXT:    ret float [[TMP7]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = extractelement <4 x float> %a, i64 0
+  %5 = extractelement <4 x float> %b, i64 0
+  %6 = extractelement <4 x float> %3, i64 0
+  %7 = call float @llvm.fma.f32(float %4, float %5, float %6)
+  %8 = bitcast i8 %mask to <8 x i1>
+  %9 = extractelement <8 x i1> %8, i64 0
+  %10 = select i1 %9, float %7, float %6
+  %11 = insertelement <4 x float> %3, float %10, i64 0
+  %12 = extractelement <4 x float> %11, i32 0
+  ret float %12
+}
+
+define float @test_mask3_vfmadd_ss_1(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmadd_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = extractelement <4 x float> %a, i64 0
+  %5 = extractelement <4 x float> %b, i64 0
+  %6 = extractelement <4 x float> %3, i64 0
+  %7 = call float @llvm.fma.f32(float %4, float %5, float %6)
+  %8 = bitcast i8 %mask to <8 x i1>
+  %9 = extractelement <8 x i1> %8, i64 0
+  %10 = select i1 %9, float %7, float %6
+  %11 = insertelement <4 x float> %3, float %10, i64 0
+  %12 = extractelement <4 x float> %11, i32 1
+  ret float %12
+}
+
+define <2 x double> @test_mask3_vfmadd_sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmadd_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call double @llvm.fma.f64(double [[TMP1]], double [[TMP2]], double [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], double [[TMP4]], double [[TMP3]]
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x double> [[C]], double [[TMP7]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP8]]
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1
+  %2 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
+  %3 = extractelement <2 x double> %1, i64 0
+  %4 = extractelement <2 x double> %2, i64 0
+  %5 = extractelement <2 x double> %c, i64 0
+  %6 = call double @llvm.fma.f64(double %3, double %4, double %5)
+  %7 = bitcast i8 %mask to <8 x i1>
+  %8 = extractelement <8 x i1> %7, i64 0
+  %9 = select i1 %8, double %6, double %5
+  %10 = insertelement <2 x double> %c, double %9, i64 0
+  ret <2 x double> %10
+}
+
+define double @test_mask3_vfmadd_sd_0(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmadd_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = call double @llvm.fma.f64(double [[TMP1]], double [[TMP2]], double [[TMP3]])
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i1> [[TMP5]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = select i1 [[TMP6]], double [[TMP4]], double [[TMP3]]
+; CHECK-NEXT:    ret double [[TMP7]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = extractelement <2 x double> %a, i64 0
+  %3 = extractelement <2 x double> %b, i64 0
+  %4 = extractelement <2 x double> %1, i64 0
+  %5 = call double @llvm.fma.f64(double %2, double %3, double %4)
+  %6 = bitcast i8 %mask to <8 x i1>
+  %7 = extractelement <8 x i1> %6, i64 0
+  %8 = select i1 %7, double %5, double %4
+  %9 = insertelement <2 x double> %1, double %8, i64 0
+  %10 = extractelement <2 x double> %9, i32 0
+  ret double %10
+}
+
+define double @test_mask3_vfmadd_sd_1(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmadd_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = extractelement <2 x double> %a, i64 0
+  %3 = extractelement <2 x double> %b, i64 0
+  %4 = extractelement <2 x double> %1, i64 0
+  %5 = call double @llvm.fma.f64(double %2, double %3, double %4)
+  %6 = bitcast i8 %mask to <8 x i1>
+  %7 = extractelement <8 x i1> %6, i64 0
+  %8 = select i1 %7, double %5, double %4
+  %9 = insertelement <2 x double> %1, double %8, i64 0
+  %10 = extractelement <2 x double> %9, i32 1
+  ret double %10
+}
+
+define <4 x float> @test_mask3_vfmsub_ss(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmsub_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = fneg float [[TMP3]]
+; CHECK-NEXT:    [[TMP5:%.*]] = call float @llvm.fma.f32(float [[TMP1]], float [[TMP2]], float [[TMP4]])
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[C]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x i1> [[TMP7]], i64 0
+; CHECK-NEXT:    [[TMP9:%.*]] = select i1 [[TMP8]], float [[TMP5]], float [[TMP6]]
+; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <4 x float> [[C]], float [[TMP9]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP10]]
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = insertelement <4 x float> %b, float 4.000000e+00, i32 1
+  %5 = insertelement <4 x float> %4, float 5.000000e+00, i32 2
+  %6 = insertelement <4 x float> %5, float 6.000000e+00, i32 3
+  %7 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c
+  %8 = extractelement <4 x float> %3, i64 0
+  %9 = extractelement <4 x float> %6, i64 0
+  %10 = extractelement <4 x float> %7, i64 0
+  %11 = call float @llvm.fma.f32(float %8, float %9, float %10)
+  %12 = extractelement <4 x float> %c, i64 0
+  %13 = bitcast i8 %mask to <8 x i1>
+  %14 = extractelement <8 x i1> %13, i64 0
+  %15 = select i1 %14, float %11, float %12
+  %16 = insertelement <4 x float> %c, float %15, i64 0
+  ret <4 x float> %16
+}
+
+define float @test_mask3_vfmsub_ss_0(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmsub_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[C:%.*]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = fneg float [[TMP3]]
+; CHECK-NEXT:    [[TMP5:%.*]] = call float @llvm.fma.f32(float [[TMP1]], float [[TMP2]], float [[TMP4]])
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[C]], i32 0
+; CHECK-NEXT:    [[TMP7:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x i1> [[TMP7]], i64 0
+; CHECK-NEXT:    [[TMP9:%.*]] = select i1 [[TMP8]], float [[TMP5]], float [[TMP6]]
+; CHECK-NEXT:    ret float [[TMP9]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %3
+  %5 = extractelement <4 x float> %a, i64 0
+  %6 = extractelement <4 x float> %b, i64 0
+  %7 = extractelement <4 x float> %4, i64 0
+  %8 = call float @llvm.fma.f32(float %5, float %6, float %7)
+  %9 = extractelement <4 x float> %3, i64 0
+  %10 = bitcast i8 %mask to <8 x i1>
+  %11 = extractelement <8 x i1> %10, i64 0
+  %12 = select i1 %11, float %8, float %9
+  %13 = insertelement <4 x float> %3, float %12, i64 0
+  %14 = extractelement <4 x float> %13, i32 0
+  ret float %14
+}
+
+define float @test_mask3_vfmsub_ss_1(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmsub_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %3
+  %5 = extractelement <4 x float> %a, i64 0
+  %6 = extractelement <4 x float> %b, i64 0
+  %7 = extractelement <4 x float> %4, i64 0
+  %8 = call float @llvm.fma.f32(float %5, float %6, float %7)
+  %9 = extractelement <4 x float> %3, i64 0
+  %10 = bitcast i8 %mask to <8 x i1>
+  %11 = extractelement <8 x i1> %10, i64 0
+  %12 = select i1 %11, float %8, float %9
+  %13 = insertelement <4 x float> %3, float %12, i64 0
+  %14 = extractelement <4 x float> %13, i32 1
+  ret float %14
+}
+
+define float @test_mask3_vfmsub_ss_1_unary_fneg(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmsub_ss_1_unary_fneg(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = fneg <4 x float> %3
+  %5 = extractelement <4 x float> %a, i64 0
+  %6 = extractelement <4 x float> %b, i64 0
+  %7 = extractelement <4 x float> %4, i64 0
+  %8 = call float @llvm.fma.f32(float %5, float %6, float %7)
+  %9 = extractelement <4 x float> %3, i64 0
+  %10 = bitcast i8 %mask to <8 x i1>
+  %11 = extractelement <8 x i1> %10, i64 0
+  %12 = select i1 %11, float %8, float %9
+  %13 = insertelement <4 x float> %3, float %12, i64 0
+  %14 = extractelement <4 x float> %13, i32 1
+  ret float %14
+}
+
+define <2 x double> @test_mask3_vfmsub_sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmsub_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = fneg double [[TMP3]]
+; CHECK-NEXT:    [[TMP5:%.*]] = call double @llvm.fma.f64(double [[TMP1]], double [[TMP2]], double [[TMP4]])
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x double> [[C]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x i1> [[TMP7]], i64 0
+; CHECK-NEXT:    [[TMP9:%.*]] = select i1 [[TMP8]], double [[TMP5]], double [[TMP6]]
+; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <2 x double> [[C]], double [[TMP9]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP10]]
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1
+  %2 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
+  %3 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %c
+  %4 = extractelement <2 x double> %1, i64 0
+  %5 = extractelement <2 x double> %2, i64 0
+  %6 = extractelement <2 x double> %3, i64 0
+  %7 = call double @llvm.fma.f64(double %4, double %5, double %6)
+  %8 = extractelement <2 x double> %c, i64 0
+  %9 = bitcast i8 %mask to <8 x i1>
+  %10 = extractelement <8 x i1> %9, i64 0
+  %11 = select i1 %10, double %7, double %8
+  %12 = insertelement <2 x double> %c, double %11, i64 0
+  ret <2 x double> %12
+}
+
+define double @test_mask3_vfmsub_sd_0(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmsub_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = fneg double [[TMP3]]
+; CHECK-NEXT:    [[TMP5:%.*]] = call double @llvm.fma.f64(double [[TMP1]], double [[TMP2]], double [[TMP4]])
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x double> [[C]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x i1> [[TMP7]], i64 0
+; CHECK-NEXT:    [[TMP9:%.*]] = select i1 [[TMP8]], double [[TMP5]], double [[TMP6]]
+; CHECK-NEXT:    ret double [[TMP9]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %1
+  %3 = extractelement <2 x double> %a, i64 0
+  %4 = extractelement <2 x double> %b, i64 0
+  %5 = extractelement <2 x double> %2, i64 0
+  %6 = call double @llvm.fma.f64(double %3, double %4, double %5)
+  %7 = extractelement <2 x double> %1, i64 0
+  %8 = bitcast i8 %mask to <8 x i1>
+  %9 = extractelement <8 x i1> %8, i64 0
+  %10 = select i1 %9, double %6, double %7
+  %11 = insertelement <2 x double> %1, double %10, i64 0
+  %12 = extractelement <2 x double> %11, i32 0
+  ret double %12
+}
+
+define double @test_mask3_vfmsub_sd_1(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmsub_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %1
+  %3 = extractelement <2 x double> %a, i64 0
+  %4 = extractelement <2 x double> %b, i64 0
+  %5 = extractelement <2 x double> %2, i64 0
+  %6 = call double @llvm.fma.f64(double %3, double %4, double %5)
+  %7 = extractelement <2 x double> %1, i64 0
+  %8 = bitcast i8 %mask to <8 x i1>
+  %9 = extractelement <8 x i1> %8, i64 0
+  %10 = select i1 %9, double %6, double %7
+  %11 = insertelement <2 x double> %1, double %10, i64 0
+  %12 = extractelement <2 x double> %11, i32 1
+  ret double %12
+}
+
+define double @test_mask3_vfmsub_sd_1_unary_fneg(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfmsub_sd_1_unary_fneg(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = fneg <2 x double> %1
+  %3 = extractelement <2 x double> %a, i64 0
+  %4 = extractelement <2 x double> %b, i64 0
+  %5 = extractelement <2 x double> %2, i64 0
+  %6 = call double @llvm.fma.f64(double %3, double %4, double %5)
+  %7 = extractelement <2 x double> %1, i64 0
+  %8 = bitcast i8 %mask to <8 x i1>
+  %9 = extractelement <8 x i1> %8, i64 0
+  %10 = select i1 %9, double %6, double %7
+  %11 = insertelement <2 x double> %1, double %10, i64 0
+  %12 = extractelement <2 x double> %11, i32 1
+  ret double %12
+}
+
+define <4 x float> @test_mask3_vfnmsub_ss(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfnmsub_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = fneg float [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP5:%.*]] = fneg float [[TMP4]]
+; CHECK-NEXT:    [[TMP6:%.*]] = call float @llvm.fma.f32(float [[TMP2]], float [[TMP3]], float [[TMP5]])
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <4 x float> [[C]], i64 0
+; CHECK-NEXT:    [[TMP8:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x i1> [[TMP8]], i64 0
+; CHECK-NEXT:    [[TMP10:%.*]] = select i1 [[TMP9]], float [[TMP6]], float [[TMP7]]
+; CHECK-NEXT:    [[TMP11:%.*]] = insertelement <4 x float> [[C]], float [[TMP10]], i64 0
+; CHECK-NEXT:    ret <4 x float> [[TMP11]]
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = insertelement <4 x float> %b, float 4.000000e+00, i32 1
+  %5 = insertelement <4 x float> %4, float 5.000000e+00, i32 2
+  %6 = insertelement <4 x float> %5, float 6.000000e+00, i32 3
+  %7 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %3
+  %8 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c
+  %9 = extractelement <4 x float> %7, i64 0
+  %10 = extractelement <4 x float> %6, i64 0
+  %11 = extractelement <4 x float> %8, i64 0
+  %12 = call float @llvm.fma.f32(float %9, float %10, float %11)
+  %13 = extractelement <4 x float> %c, i64 0
+  %14 = bitcast i8 %mask to <8 x i1>
+  %15 = extractelement <8 x i1> %14, i64 0
+  %16 = select i1 %15, float %12, float %13
+  %17 = insertelement <4 x float> %c, float %16, i64 0
+  ret <4 x float> %17
+}
+
+define float @test_mask3_vfnmsub_ss_0(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfnmsub_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = fneg float [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[C:%.*]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = fneg float [[TMP4]]
+; CHECK-NEXT:    [[TMP6:%.*]] = call float @llvm.fma.f32(float [[TMP2]], float [[TMP3]], float [[TMP5]])
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <4 x float> [[C]], i32 0
+; CHECK-NEXT:    [[TMP8:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x i1> [[TMP8]], i64 0
+; CHECK-NEXT:    [[TMP10:%.*]] = select i1 [[TMP9]], float [[TMP6]], float [[TMP7]]
+; CHECK-NEXT:    ret float [[TMP10]]
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a
+  %5 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %3
+  %6 = extractelement <4 x float> %4, i64 0
+  %7 = extractelement <4 x float> %b, i64 0
+  %8 = extractelement <4 x float> %5, i64 0
+  %9 = call float @llvm.fma.f32(float %6, float %7, float %8)
+  %10 = extractelement <4 x float> %3, i64 0
+  %11 = bitcast i8 %mask to <8 x i1>
+  %12 = extractelement <8 x i1> %11, i64 0
+  %13 = select i1 %12, float %9, float %10
+  %14 = insertelement <4 x float> %3, float %13, i64 0
+  %15 = extractelement <4 x float> %14, i32 0
+  ret float %15
+}
+
+define float @test_mask3_vfnmsub_ss_1(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfnmsub_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %a
+  %5 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %3
+  %6 = extractelement <4 x float> %4, i64 0
+  %7 = extractelement <4 x float> %b, i64 0
+  %8 = extractelement <4 x float> %5, i64 0
+  %9 = call float @llvm.fma.f32(float %6, float %7, float %8)
+  %10 = extractelement <4 x float> %3, i64 0
+  %11 = bitcast i8 %mask to <8 x i1>
+  %12 = extractelement <8 x i1> %11, i64 0
+  %13 = select i1 %12, float %9, float %10
+  %14 = insertelement <4 x float> %3, float %13, i64 0
+  %15 = extractelement <4 x float> %14, i32 1
+  ret float %15
+}
+
+define float @test_mask3_vfnmsub_ss_1_unary_fneg(<4 x float> %a, <4 x float> %b, <4 x float> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfnmsub_ss_1_unary_fneg(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> %c, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = fneg <4 x float> %a
+  %5 = fneg <4 x float> %3
+  %6 = extractelement <4 x float> %4, i64 0
+  %7 = extractelement <4 x float> %b, i64 0
+  %8 = extractelement <4 x float> %5, i64 0
+  %9 = call float @llvm.fma.f32(float %6, float %7, float %8)
+  %10 = extractelement <4 x float> %3, i64 0
+  %11 = bitcast i8 %mask to <8 x i1>
+  %12 = extractelement <8 x i1> %11, i64 0
+  %13 = select i1 %12, float %9, float %10
+  %14 = insertelement <4 x float> %3, float %13, i64 0
+  %15 = extractelement <4 x float> %14, i32 1
+  ret float %15
+}
+
+define <2 x double> @test_mask3_vfnmsub_sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfnmsub_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = fneg double [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP5:%.*]] = fneg double [[TMP4]]
+; CHECK-NEXT:    [[TMP6:%.*]] = call double @llvm.fma.f64(double [[TMP2]], double [[TMP3]], double [[TMP5]])
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x double> [[C]], i64 0
+; CHECK-NEXT:    [[TMP8:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x i1> [[TMP8]], i64 0
+; CHECK-NEXT:    [[TMP10:%.*]] = select i1 [[TMP9]], double [[TMP6]], double [[TMP7]]
+; CHECK-NEXT:    [[TMP11:%.*]] = insertelement <2 x double> [[C]], double [[TMP10]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[TMP11]]
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1
+  %2 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
+  %3 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %1
+  %4 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %c
+  %5 = extractelement <2 x double> %3, i64 0
+  %6 = extractelement <2 x double> %2, i64 0
+  %7 = extractelement <2 x double> %4, i64 0
+  %8 = call double @llvm.fma.f64(double %5, double %6, double %7)
+  %9 = extractelement <2 x double> %c, i64 0
+  %10 = bitcast i8 %mask to <8 x i1>
+  %11 = extractelement <8 x i1> %10, i64 0
+  %12 = select i1 %11, double %8, double %9
+  %13 = insertelement <2 x double> %c, double %12, i64 0
+  ret <2 x double> %13
+}
+
+define double @test_mask3_vfnmsub_sd_0(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfnmsub_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[A:%.*]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = fneg double [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[B:%.*]], i64 0
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x double> [[C:%.*]], i64 0
+; CHECK-NEXT:    [[TMP5:%.*]] = fneg double [[TMP4]]
+; CHECK-NEXT:    [[TMP6:%.*]] = call double @llvm.fma.f64(double [[TMP2]], double [[TMP3]], double [[TMP5]])
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x double> [[C]], i64 0
+; CHECK-NEXT:    [[TMP8:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x i1> [[TMP8]], i64 0
+; CHECK-NEXT:    [[TMP10:%.*]] = select i1 [[TMP9]], double [[TMP6]], double [[TMP7]]
+; CHECK-NEXT:    ret double [[TMP10]]
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a
+  %3 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %1
+  %4 = extractelement <2 x double> %2, i64 0
+  %5 = extractelement <2 x double> %b, i64 0
+  %6 = extractelement <2 x double> %3, i64 0
+  %7 = call double @llvm.fma.f64(double %4, double %5, double %6)
+  %8 = extractelement <2 x double> %1, i64 0
+  %9 = bitcast i8 %mask to <8 x i1>
+  %10 = extractelement <8 x i1> %9, i64 0
+  %11 = select i1 %10, double %7, double %8
+  %12 = insertelement <2 x double> %1, double %11, i64 0
+  %13 = extractelement <2 x double> %12, i32 0
+  ret double %13
+}
+
+define double @test_mask3_vfnmsub_sd_1(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfnmsub_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %a
+  %3 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %1
+  %4 = extractelement <2 x double> %2, i64 0
+  %5 = extractelement <2 x double> %b, i64 0
+  %6 = extractelement <2 x double> %3, i64 0
+  %7 = call double @llvm.fma.f64(double %4, double %5, double %6)
+  %8 = extractelement <2 x double> %1, i64 0
+  %9 = bitcast i8 %mask to <8 x i1>
+  %10 = extractelement <8 x i1> %9, i64 0
+  %11 = select i1 %10, double %7, double %8
+  %12 = insertelement <2 x double> %1, double %11, i64 0
+  %13 = extractelement <2 x double> %12, i32 1
+  ret double %13
+}
+
+define double @test_mask3_vfnmsub_sd_1_unary_fneg(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mask3_vfnmsub_sd_1_unary_fneg(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> %c, double 1.000000e+00, i32 1
+  %2 = fneg <2 x double> %a
+  %3 = fneg <2 x double> %1
+  %4 = extractelement <2 x double> %2, i64 0
+  %5 = extractelement <2 x double> %b, i64 0
+  %6 = extractelement <2 x double> %3, i64 0
+  %7 = call double @llvm.fma.f64(double %4, double %5, double %6)
+  %8 = extractelement <2 x double> %1, i64 0
+  %9 = bitcast i8 %mask to <8 x i1>
+  %10 = extractelement <8 x i1> %9, i64 0
+  %11 = select i1 %10, double %7, double %8
+  %12 = insertelement <2 x double> %1, double %11, i64 0
+  %13 = extractelement <2 x double> %12, i32 1
+  ret double %13
+}
+
+declare <8 x i32> @llvm.x86.avx2.permd(<8 x i32>, <8 x i32>)
+
+define <8 x i32> @identity_test_permvar_si_256(<8 x i32> %a0) {
+; CHECK-LABEL: @identity_test_permvar_si_256(
+; CHECK-NEXT:    ret <8 x i32> [[A0:%.*]]
+;
+  %1 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @identity_test_permvar_si_256_mask(<8 x i32> %a0, <8 x i32> %passthru, i8 %mask) {
+; CHECK-LABEL: @identity_test_permvar_si_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i32> [[A0:%.*]], <8 x i32> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP2]]
+;
+  %1 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> %passthru
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @zero_test_permvar_si_256(<8 x i32> %a0) {
+; CHECK-LABEL: @zero_test_permvar_si_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> zeroinitializer)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @zero_test_permvar_si_256_mask(<8 x i32> %a0, <8 x i32> %passthru, i8 %mask) {
+; CHECK-LABEL: @zero_test_permvar_si_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP1]], <8 x i32> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP3]]
+;
+  %1 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> zeroinitializer)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> %passthru
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @shuffle_test_permvar_si_256(<8 x i32> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_si_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @shuffle_test_permvar_si_256_mask(<8 x i32> %a0, <8 x i32> %passthru, i8 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_si_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP1]], <8 x i32> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP3]]
+;
+  %1 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> %passthru
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @undef_test_permvar_si_256(<8 x i32> %a0) {
+; CHECK-LABEL: @undef_test_permvar_si_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @undef_test_permvar_si_256_mask(<8 x i32> %a0, <8 x i32> %passthru, i8 %mask) {
+; CHECK-LABEL: @undef_test_permvar_si_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i32> [[TMP1]], <8 x i32> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP3]]
+;
+  %1 = call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i32> %1, <8 x i32> %passthru
+  ret <8 x i32> %3
+}
+
+declare <8 x float> @llvm.x86.avx2.permps(<8 x float>, <8 x i32>)
+
+define <8 x float> @identity_test_permvar_sf_256(<8 x float> %a0) {
+; CHECK-LABEL: @identity_test_permvar_sf_256(
+; CHECK-NEXT:    ret <8 x float> [[A0:%.*]]
+;
+  %1 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>)
+  ret <8 x float> %1
+}
+
+define <8 x float> @identity_test_permvar_sf_256_mask(<8 x float> %a0, <8 x float> %passthru, i8 %mask) {
+; CHECK-LABEL: @identity_test_permvar_sf_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x float> [[A0:%.*]], <8 x float> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x float> [[TMP2]]
+;
+  %1 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> %passthru
+  ret <8 x float> %3
+}
+
+define <8 x float> @zero_test_permvar_sf_256(<8 x float> %a0) {
+; CHECK-LABEL: @zero_test_permvar_sf_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    ret <8 x float> [[TMP1]]
+;
+  %1 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> zeroinitializer)
+  ret <8 x float> %1
+}
+
+define <8 x float> @zero_test_permvar_sf_256_mask(<8 x float> %a0, <8 x float> %passthru, i8 %mask) {
+; CHECK-LABEL: @zero_test_permvar_sf_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x float> [[TMP3]]
+;
+  %1 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> zeroinitializer)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> %passthru
+  ret <8 x float> %3
+}
+
+define <8 x float> @shuffle_test_permvar_sf_256(<8 x float> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_sf_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x float> [[TMP1]]
+;
+  %1 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  ret <8 x float> %1
+}
+
+define <8 x float> @shuffle_test_permvar_sf_256_mask(<8 x float> %a0, <8 x float> %passthru, i8 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_sf_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x float> [[TMP3]]
+;
+  %1 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> %passthru
+  ret <8 x float> %3
+}
+
+define <8 x float> @undef_test_permvar_sf_256(<8 x float> %a0) {
+; CHECK-LABEL: @undef_test_permvar_sf_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x float> [[TMP1]]
+;
+  %1 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  ret <8 x float> %1
+}
+
+define <8 x float> @undef_test_permvar_sf_256_mask(<8 x float> %a0, <8 x float> %passthru, i8 %mask) {
+; CHECK-LABEL: @undef_test_permvar_sf_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x float> [[TMP1]], <8 x float> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x float> [[TMP3]]
+;
+  %1 = call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x float> %1, <8 x float> %passthru
+  ret <8 x float> %3
+}
+
+declare <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64>, <4 x i64>)
+
+define <4 x i64> @identity_test_permvar_di_256(<4 x i64> %a0) {
+; CHECK-LABEL: @identity_test_permvar_di_256(
+; CHECK-NEXT:    ret <4 x i64> [[A0:%.*]]
+;
+  %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @identity_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
+; CHECK-LABEL: @identity_test_permvar_di_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[A0:%.*]], <4 x i64> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP2]]
+;
+  %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
+  ret <4 x i64> %3
+}
+
+define <4 x i64> @zero_test_permvar_di_256(<4 x i64> %a0) {
+; CHECK-LABEL: @zero_test_permvar_di_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @zero_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
+; CHECK-LABEL: @zero_test_permvar_di_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP3]]
+;
+  %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> zeroinitializer)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
+  ret <4 x i64> %3
+}
+
+define <4 x i64> @shuffle_test_permvar_di_256(<4 x i64> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_di_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @shuffle_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_di_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP3]]
+;
+  %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
+  ret <4 x i64> %3
+}
+
+define <4 x i64> @undef_test_permvar_di_256(<4 x i64> %a0) {
+; CHECK-LABEL: @undef_test_permvar_di_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @undef_test_permvar_di_256_mask(<4 x i64> %a0, <4 x i64> %passthru, i8 %mask) {
+; CHECK-LABEL: @undef_test_permvar_di_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i64> [[A0:%.*]], <4 x i64> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x i64> [[TMP1]], <4 x i64> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP3]]
+;
+  %1 = call <4 x i64> @llvm.x86.avx512.permvar.di.256(<4 x i64> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = select <4 x i1> %extract, <4 x i64> %1, <4 x i64> %passthru
+  ret <4 x i64> %3
+}
+
+declare <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double>, <4 x i64>)
+
+define <4 x double> @identity_test_permvar_df_256(<4 x double> %a0) {
+; CHECK-LABEL: @identity_test_permvar_df_256(
+; CHECK-NEXT:    ret <4 x double> [[A0:%.*]]
+;
+  %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
+  ret <4 x double> %1
+}
+
+define <4 x double> @identity_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
+; CHECK-LABEL: @identity_test_permvar_df_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[A0:%.*]], <4 x double> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <4 x double> [[TMP2]]
+;
+  %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 0, i64 1, i64 2, i64 3>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
+  ret <4 x double> %3
+}
+
+define <4 x double> @zero_test_permvar_df_256(<4 x double> %a0) {
+; CHECK-LABEL: @zero_test_permvar_df_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    ret <4 x double> [[TMP1]]
+;
+  %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer)
+  ret <4 x double> %1
+}
+
+define <4 x double> @zero_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
+; CHECK-LABEL: @zero_test_permvar_df_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <4 x double> [[TMP3]]
+;
+  %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> zeroinitializer)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
+  ret <4 x double> %3
+}
+
+define <4 x double> @shuffle_test_permvar_df_256(<4 x double> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_df_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <4 x double> [[TMP1]]
+;
+  %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
+  ret <4 x double> %1
+}
+
+define <4 x double> @shuffle_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_df_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <4 x double> [[TMP3]]
+;
+  %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 3, i64 2, i64 1, i64 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
+  ret <4 x double> %3
+}
+
+define <4 x double> @undef_test_permvar_df_256(<4 x double> %a0) {
+; CHECK-LABEL: @undef_test_permvar_df_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <4 x double> [[TMP1]]
+;
+  %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
+  ret <4 x double> %1
+}
+
+define <4 x double> @undef_test_permvar_df_256_mask(<4 x double> %a0, <4 x double> %passthru, i8 %mask) {
+; CHECK-LABEL: @undef_test_permvar_df_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A0:%.*]], <4 x double> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[EXTRACT:%.*]] = shufflevector <8 x i1> [[TMP2]], <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <4 x i1> [[EXTRACT]], <4 x double> [[TMP1]], <4 x double> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <4 x double> [[TMP3]]
+;
+  %1 = call <4 x double> @llvm.x86.avx512.permvar.df.256(<4 x double> %a0, <4 x i64> <i64 undef, i64 2, i64 1, i64 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %extract = shufflevector <8 x i1> %2, <8 x i1> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %3 = select <4 x i1> %extract, <4 x double> %1, <4 x double> %passthru
+  ret <4 x double> %3
+}
+
+declare <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32>, <16 x i32>)
+
+define <16 x i32> @identity_test_permvar_si_512(<16 x i32> %a0) {
+; CHECK-LABEL: @identity_test_permvar_si_512(
+; CHECK-NEXT:    ret <16 x i32> [[A0:%.*]]
+;
+  %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %a0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @identity_test_permvar_si_512_mask(<16 x i32> %a0, <16 x i32> %passthru, i16 %mask) {
+; CHECK-LABEL: @identity_test_permvar_si_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <16 x i1> [[TMP1]], <16 x i32> [[A0:%.*]], <16 x i32> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i32> [[TMP2]]
+;
+  %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %a0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %passthru
+  ret <16 x i32> %3
+}
+
+define <16 x i32> @zero_test_permvar_si_512(<16 x i32> %a0) {
+; CHECK-LABEL: @zero_test_permvar_si_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %a0, <16 x i32> zeroinitializer)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @zero_test_permvar_si_512_mask(<16 x i32> %a0, <16 x i32> %passthru, i16 %mask) {
+; CHECK-LABEL: @zero_test_permvar_si_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x i32> [[TMP1]], <16 x i32> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i32> [[TMP3]]
+;
+  %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %a0, <16 x i32> zeroinitializer)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %passthru
+  ret <16 x i32> %3
+}
+
+define <16 x i32> @shuffle_test_permvar_si_512(<16 x i32> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_si_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %a0, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @shuffle_test_permvar_si_512_mask(<16 x i32> %a0, <16 x i32> %passthru, i16 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_si_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x i32> [[TMP1]], <16 x i32> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i32> [[TMP3]]
+;
+  %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %a0, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %passthru
+  ret <16 x i32> %3
+}
+
+define <16 x i32> @undef_test_permvar_si_512(<16 x i32> %a0) {
+; CHECK-LABEL: @undef_test_permvar_si_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %a0, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @undef_test_permvar_si_512_mask(<16 x i32> %a0, <16 x i32> %passthru, i16 %mask) {
+; CHECK-LABEL: @undef_test_permvar_si_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x i32> [[TMP1]], <16 x i32> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i32> [[TMP3]]
+;
+  %1 = call <16 x i32> @llvm.x86.avx512.permvar.si.512(<16 x i32> %a0, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i32> %1, <16 x i32> %passthru
+  ret <16 x i32> %3
+}
+
+declare <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float>, <16 x i32>)
+
+define <16 x float> @identity_test_permvar_sf_512(<16 x float> %a0) {
+; CHECK-LABEL: @identity_test_permvar_sf_512(
+; CHECK-NEXT:    ret <16 x float> [[A0:%.*]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %a0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>)
+  ret <16 x float> %1
+}
+
+define <16 x float> @identity_test_permvar_sf_512_mask(<16 x float> %a0, <16 x float> %passthru, i16 %mask) {
+; CHECK-LABEL: @identity_test_permvar_sf_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <16 x i1> [[TMP1]], <16 x float> [[A0:%.*]], <16 x float> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP2]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %a0, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru
+  ret <16 x float> %3
+}
+
+define <16 x float> @zero_test_permvar_sf_512(<16 x float> %a0) {
+; CHECK-LABEL: @zero_test_permvar_sf_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x float> [[A0:%.*]], <16 x float> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %a0, <16 x i32> zeroinitializer)
+  ret <16 x float> %1
+}
+
+define <16 x float> @zero_test_permvar_sf_512_mask(<16 x float> %a0, <16 x float> %passthru, i16 %mask) {
+; CHECK-LABEL: @zero_test_permvar_sf_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x float> [[A0:%.*]], <16 x float> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %a0, <16 x i32> zeroinitializer)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru
+  ret <16 x float> %3
+}
+
+define <16 x float> @shuffle_test_permvar_sf_512(<16 x float> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_sf_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x float> [[A0:%.*]], <16 x float> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %a0, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  ret <16 x float> %1
+}
+
+define <16 x float> @shuffle_test_permvar_sf_512_mask(<16 x float> %a0, <16 x float> %passthru, i16 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_sf_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x float> [[A0:%.*]], <16 x float> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %a0, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru
+  ret <16 x float> %3
+}
+
+define <16 x float> @undef_test_permvar_sf_512(<16 x float> %a0) {
+; CHECK-LABEL: @undef_test_permvar_sf_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x float> [[A0:%.*]], <16 x float> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %a0, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  ret <16 x float> %1
+}
+
+define <16 x float> @undef_test_permvar_sf_512_mask(<16 x float> %a0, <16 x float> %passthru, i16 %mask) {
+; CHECK-LABEL: @undef_test_permvar_sf_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x float> [[A0:%.*]], <16 x float> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.permvar.sf.512(<16 x float> %a0, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %passthru
+  ret <16 x float> %3
+}
+
+declare <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64>, <8 x i64>)
+
+define <8 x i64> @identity_test_permvar_di_512(<8 x i64> %a0) {
+; CHECK-LABEL: @identity_test_permvar_di_512(
+; CHECK-NEXT:    ret <8 x i64> [[A0:%.*]]
+;
+  %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %a0, <8 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @identity_test_permvar_di_512_mask(<8 x i64> %a0, <8 x i64> %passthru, i8 %mask) {
+; CHECK-LABEL: @identity_test_permvar_di_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i64> [[A0:%.*]], <8 x i64> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i64> [[TMP2]]
+;
+  %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %a0, <8 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> %passthru
+  ret <8 x i64> %3
+}
+
+define <8 x i64> @zero_test_permvar_di_512(<8 x i64> %a0) {
+; CHECK-LABEL: @zero_test_permvar_di_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %a0, <8 x i64> zeroinitializer)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @zero_test_permvar_di_512_mask(<8 x i64> %a0, <8 x i64> %passthru, i8 %mask) {
+; CHECK-LABEL: @zero_test_permvar_di_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i64> [[TMP1]], <8 x i64> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i64> [[TMP3]]
+;
+  %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %a0, <8 x i64> zeroinitializer)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> %passthru
+  ret <8 x i64> %3
+}
+
+define <8 x i64> @shuffle_test_permvar_di_512(<8 x i64> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_di_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %a0, <8 x i64> <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @shuffle_test_permvar_di_512_mask(<8 x i64> %a0, <8 x i64> %passthru, i8 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_di_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i64> [[TMP1]], <8 x i64> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i64> [[TMP3]]
+;
+  %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %a0, <8 x i64> <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> %passthru
+  ret <8 x i64> %3
+}
+
+define <8 x i64> @undef_test_permvar_di_512(<8 x i64> %a0) {
+; CHECK-LABEL: @undef_test_permvar_di_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %a0, <8 x i64> <i64 undef, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @undef_test_permvar_di_512_mask(<8 x i64> %a0, <8 x i64> %passthru, i8 %mask) {
+; CHECK-LABEL: @undef_test_permvar_di_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i64> [[A0:%.*]], <8 x i64> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i64> [[TMP1]], <8 x i64> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i64> [[TMP3]]
+;
+  %1 = call <8 x i64> @llvm.x86.avx512.permvar.di.512(<8 x i64> %a0, <8 x i64> <i64 undef, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i64> %1, <8 x i64> %passthru
+  ret <8 x i64> %3
+}
+
+declare <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double>, <8 x i64>)
+
+define <8 x double> @identity_test_permvar_df_512(<8 x double> %a0) {
+; CHECK-LABEL: @identity_test_permvar_df_512(
+; CHECK-NEXT:    ret <8 x double> [[A0:%.*]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %a0, <8 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>)
+  ret <8 x double> %1
+}
+
+define <8 x double> @identity_test_permvar_df_512_mask(<8 x double> %a0, <8 x double> %passthru, i8 %mask) {
+; CHECK-LABEL: @identity_test_permvar_df_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x double> [[A0:%.*]], <8 x double> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP2]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %a0, <8 x i64> <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %passthru
+  ret <8 x double> %3
+}
+
+define <8 x double> @zero_test_permvar_df_512(<8 x double> %a0) {
+; CHECK-LABEL: @zero_test_permvar_df_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x double> [[A0:%.*]], <8 x double> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %a0, <8 x i64> zeroinitializer)
+  ret <8 x double> %1
+}
+
+define <8 x double> @zero_test_permvar_df_512_mask(<8 x double> %a0, <8 x double> %passthru, i8 %mask) {
+; CHECK-LABEL: @zero_test_permvar_df_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x double> [[A0:%.*]], <8 x double> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %a0, <8 x i64> zeroinitializer)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %passthru
+  ret <8 x double> %3
+}
+
+define <8 x double> @shuffle_test_permvar_df_512(<8 x double> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_df_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x double> [[A0:%.*]], <8 x double> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %a0, <8 x i64> <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>)
+  ret <8 x double> %1
+}
+
+define <8 x double> @shuffle_test_permvar_df_512_mask(<8 x double> %a0, <8 x double> %passthru, i8 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_df_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x double> [[A0:%.*]], <8 x double> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %a0, <8 x i64> <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %passthru
+  ret <8 x double> %3
+}
+
+define <8 x double> @undef_test_permvar_df_512(<8 x double> %a0) {
+; CHECK-LABEL: @undef_test_permvar_df_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x double> [[A0:%.*]], <8 x double> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %a0, <8 x i64> <i64 undef, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>)
+  ret <8 x double> %1
+}
+
+define <8 x double> @undef_test_permvar_df_512_mask(<8 x double> %a0, <8 x double> %passthru, i8 %mask) {
+; CHECK-LABEL: @undef_test_permvar_df_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x double> [[A0:%.*]], <8 x double> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.permvar.df.512(<8 x double> %a0, <8 x i64> <i64 undef, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %passthru
+  ret <8 x double> %3
+}
+
+declare <8 x i16> @llvm.x86.avx512.permvar.hi.128(<8 x i16>, <8 x i16>)
+
+define <8 x i16> @identity_test_permvar_hi_128(<8 x i16> %a0) {
+; CHECK-LABEL: @identity_test_permvar_hi_128(
+; CHECK-NEXT:    ret <8 x i16> [[A0:%.*]]
+;
+  %1 = call <8 x i16> @llvm.x86.avx512.permvar.hi.128(<8 x i16> %a0, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @identity_test_permvar_hi_128_mask(<8 x i16> %a0, <8 x i16> %passthru, i8 %mask) {
+; CHECK-LABEL: @identity_test_permvar_hi_128_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <8 x i1> [[TMP1]], <8 x i16> [[A0:%.*]], <8 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+;
+  %1 = call <8 x i16> @llvm.x86.avx512.permvar.hi.128(<8 x i16> %a0, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> %passthru
+  ret <8 x i16> %3
+}
+
+define <8 x i16> @zero_test_permvar_hi_128(<8 x i16> %a0) {
+; CHECK-LABEL: @zero_test_permvar_hi_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[A0:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = call <8 x i16> @llvm.x86.avx512.permvar.hi.128(<8 x i16> %a0, <8 x i16> zeroinitializer)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @zero_test_permvar_hi_128_mask(<8 x i16> %a0, <8 x i16> %passthru, i8 %mask) {
+; CHECK-LABEL: @zero_test_permvar_hi_128_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[A0:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i16> [[TMP1]], <8 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+;
+  %1 = call <8 x i16> @llvm.x86.avx512.permvar.hi.128(<8 x i16> %a0, <8 x i16> zeroinitializer)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> %passthru
+  ret <8 x i16> %3
+}
+
+define <8 x i16> @shuffle_test_permvar_hi_128(<8 x i16> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_hi_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[A0:%.*]], <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = call <8 x i16> @llvm.x86.avx512.permvar.hi.128(<8 x i16> %a0, <8 x i16> <i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @shuffle_test_permvar_hi_128_mask(<8 x i16> %a0, <8 x i16> %passthru, i8 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_hi_128_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[A0:%.*]], <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i16> [[TMP1]], <8 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+;
+  %1 = call <8 x i16> @llvm.x86.avx512.permvar.hi.128(<8 x i16> %a0, <8 x i16> <i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> %passthru
+  ret <8 x i16> %3
+}
+
+define <8 x i16> @undef_test_permvar_hi_128(<8 x i16> %a0) {
+; CHECK-LABEL: @undef_test_permvar_hi_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[A0:%.*]], <8 x i16> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = call <8 x i16> @llvm.x86.avx512.permvar.hi.128(<8 x i16> %a0, <8 x i16> <i16 undef, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @undef_test_permvar_hi_128_mask(<8 x i16> %a0, <8 x i16> %passthru, i8 %mask) {
+; CHECK-LABEL: @undef_test_permvar_hi_128_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[A0:%.*]], <8 x i16> undef, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x i16> [[TMP1]], <8 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+;
+  %1 = call <8 x i16> @llvm.x86.avx512.permvar.hi.128(<8 x i16> %a0, <8 x i16> <i16 undef, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> %passthru
+  ret <8 x i16> %3
+}
+
+declare <16 x i16> @llvm.x86.avx512.permvar.hi.256(<16 x i16>, <16 x i16>)
+
+define <16 x i16> @identity_test_permvar_hi_256(<16 x i16> %a0) {
+; CHECK-LABEL: @identity_test_permvar_hi_256(
+; CHECK-NEXT:    ret <16 x i16> [[A0:%.*]]
+;
+  %1 = call <16 x i16> @llvm.x86.avx512.permvar.hi.256(<16 x i16> %a0, <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @identity_test_permvar_hi_256_mask(<16 x i16> %a0, <16 x i16> %passthru, i16 %mask) {
+; CHECK-LABEL: @identity_test_permvar_hi_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <16 x i1> [[TMP1]], <16 x i16> [[A0:%.*]], <16 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i16> [[TMP2]]
+;
+  %1 = call <16 x i16> @llvm.x86.avx512.permvar.hi.256(<16 x i16> %a0, <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %passthru
+  ret <16 x i16> %3
+}
+
+define <16 x i16> @zero_test_permvar_hi_256(<16 x i16> %a0) {
+; CHECK-LABEL: @zero_test_permvar_hi_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A0:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = call <16 x i16> @llvm.x86.avx512.permvar.hi.256(<16 x i16> %a0, <16 x i16> zeroinitializer)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @zero_test_permvar_hi_256_mask(<16 x i16> %a0, <16 x i16> %passthru, i16 %mask) {
+; CHECK-LABEL: @zero_test_permvar_hi_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A0:%.*]], <16 x i16> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x i16> [[TMP1]], <16 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %1 = call <16 x i16> @llvm.x86.avx512.permvar.hi.256(<16 x i16> %a0, <16 x i16> zeroinitializer)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %passthru
+  ret <16 x i16> %3
+}
+
+define <16 x i16> @shuffle_test_permvar_hi_256(<16 x i16> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_hi_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A0:%.*]], <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = call <16 x i16> @llvm.x86.avx512.permvar.hi.256(<16 x i16> %a0, <16 x i16> <i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @shuffle_test_permvar_hi_256_mask(<16 x i16> %a0, <16 x i16> %passthru, i16 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_hi_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A0:%.*]], <16 x i16> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x i16> [[TMP1]], <16 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %1 = call <16 x i16> @llvm.x86.avx512.permvar.hi.256(<16 x i16> %a0, <16 x i16> <i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %passthru
+  ret <16 x i16> %3
+}
+
+define <16 x i16> @undef_test_permvar_hi_256(<16 x i16> %a0) {
+; CHECK-LABEL: @undef_test_permvar_hi_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A0:%.*]], <16 x i16> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = call <16 x i16> @llvm.x86.avx512.permvar.hi.256(<16 x i16> %a0, <16 x i16> <i16 undef, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @undef_test_permvar_hi_256_mask(<16 x i16> %a0, <16 x i16> %passthru, i16 %mask) {
+; CHECK-LABEL: @undef_test_permvar_hi_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A0:%.*]], <16 x i16> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x i16> [[TMP1]], <16 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %1 = call <16 x i16> @llvm.x86.avx512.permvar.hi.256(<16 x i16> %a0, <16 x i16> <i16 undef, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i16> %1, <16 x i16> %passthru
+  ret <16 x i16> %3
+}
+
+declare <32 x i16> @llvm.x86.avx512.permvar.hi.512(<32 x i16>, <32 x i16>)
+
+define <32 x i16> @identity_test_permvar_hi_512(<32 x i16> %a0) {
+; CHECK-LABEL: @identity_test_permvar_hi_512(
+; CHECK-NEXT:    ret <32 x i16> [[A0:%.*]]
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.permvar.hi.512(<32 x i16> %a0, <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23, i16 24, i16 25, i16 26, i16 27, i16 28, i16 29, i16 30, i16 31>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @identity_test_permvar_hi_512_mask(<32 x i16> %a0, <32 x i16> %passthru, i32 %mask) {
+; CHECK-LABEL: @identity_test_permvar_hi_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[MASK:%.*]] to <32 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <32 x i1> [[TMP1]], <32 x i16> [[A0:%.*]], <32 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP2]]
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.permvar.hi.512(<32 x i16> %a0, <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 17, i16 18, i16 19, i16 20, i16 21, i16 22, i16 23, i16 24, i16 25, i16 26, i16 27, i16 28, i16 29, i16 30, i16 31>)
+  %2 = bitcast i32 %mask to <32 x i1>
+  %3 = select <32 x i1> %2, <32 x i16> %1, <32 x i16> %passthru
+  ret <32 x i16> %3
+}
+
+define <32 x i16> @zero_test_permvar_hi_512(<32 x i16> %a0) {
+; CHECK-LABEL: @zero_test_permvar_hi_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i16> [[A0:%.*]], <32 x i16> undef, <32 x i32> zeroinitializer
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.permvar.hi.512(<32 x i16> %a0, <32 x i16> zeroinitializer)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @zero_test_permvar_hi_512_mask(<32 x i16> %a0, <32 x i16> %passthru, i32 %mask) {
+; CHECK-LABEL: @zero_test_permvar_hi_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i16> [[A0:%.*]], <32 x i16> undef, <32 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[MASK:%.*]] to <32 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <32 x i1> [[TMP2]], <32 x i16> [[TMP1]], <32 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.permvar.hi.512(<32 x i16> %a0, <32 x i16> zeroinitializer)
+  %2 = bitcast i32 %mask to <32 x i1>
+  %3 = select <32 x i1> %2, <32 x i16> %1, <32 x i16> %passthru
+  ret <32 x i16> %3
+}
+
+define <32 x i16> @shuffle_test_permvar_hi_512(<32 x i16> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_hi_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i16> [[A0:%.*]], <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.permvar.hi.512(<32 x i16> %a0, <32 x i16> <i16 31, i16 30, i16 29, i16 28, i16 27, i16 26, i16 25, i16 24, i16 23, i16 22, i16 21, i16 20, i16 19, i16 18, i16 17, i16 16, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @shuffle_test_permvar_hi_512_mask(<32 x i16> %a0, <32 x i16> %passthru, i32 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_hi_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i16> [[A0:%.*]], <32 x i16> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[MASK:%.*]] to <32 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <32 x i1> [[TMP2]], <32 x i16> [[TMP1]], <32 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.permvar.hi.512(<32 x i16> %a0, <32 x i16> <i16 31, i16 30, i16 29, i16 28, i16 27, i16 26, i16 25, i16 24, i16 23, i16 22, i16 21, i16 20, i16 19, i16 18, i16 17, i16 16, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  %2 = bitcast i32 %mask to <32 x i1>
+  %3 = select <32 x i1> %2, <32 x i16> %1, <32 x i16> %passthru
+  ret <32 x i16> %3
+}
+
+define <32 x i16> @undef_test_permvar_hi_512(<32 x i16> %a0) {
+; CHECK-LABEL: @undef_test_permvar_hi_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i16> [[A0:%.*]], <32 x i16> undef, <32 x i32> <i32 undef, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.permvar.hi.512(<32 x i16> %a0, <32 x i16> <i16 undef, i16 30, i16 29, i16 28, i16 27, i16 26, i16 25, i16 24, i16 23, i16 22, i16 21, i16 20, i16 19, i16 18, i16 17, i16 16, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @undef_test_permvar_hi_512_mask(<32 x i16> %a0, <32 x i16> %passthru, i32 %mask) {
+; CHECK-LABEL: @undef_test_permvar_hi_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i16> [[A0:%.*]], <32 x i16> undef, <32 x i32> <i32 undef, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[MASK:%.*]] to <32 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <32 x i1> [[TMP2]], <32 x i16> [[TMP1]], <32 x i16> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.permvar.hi.512(<32 x i16> %a0, <32 x i16> <i16 undef, i16 30, i16 29, i16 28, i16 27, i16 26, i16 25, i16 24, i16 23, i16 22, i16 21, i16 20, i16 19, i16 18, i16 17, i16 16, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  %2 = bitcast i32 %mask to <32 x i1>
+  %3 = select <32 x i1> %2, <32 x i16> %1, <32 x i16> %passthru
+  ret <32 x i16> %3
+}
+
+declare <16 x i8> @llvm.x86.avx512.permvar.qi.128(<16 x i8>, <16 x i8>)
+
+define <16 x i8> @identity_test_permvar_qi_128(<16 x i8> %a0) {
+; CHECK-LABEL: @identity_test_permvar_qi_128(
+; CHECK-NEXT:    ret <16 x i8> [[A0:%.*]]
+;
+  %1 = call <16 x i8> @llvm.x86.avx512.permvar.qi.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
+  ret <16 x i8> %1
+}
+
+define <16 x i8> @identity_test_permvar_qi_128_mask(<16 x i8> %a0, <16 x i8> %passthru, i16 %mask) {
+; CHECK-LABEL: @identity_test_permvar_qi_128_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <16 x i1> [[TMP1]], <16 x i8> [[A0:%.*]], <16 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i8> [[TMP2]]
+;
+  %1 = call <16 x i8> @llvm.x86.avx512.permvar.qi.128(<16 x i8> %a0, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> %passthru
+  ret <16 x i8> %3
+}
+
+define <16 x i8> @zero_test_permvar_qi_128(<16 x i8> %a0) {
+; CHECK-LABEL: @zero_test_permvar_qi_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[A0:%.*]], <16 x i8> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+;
+  %1 = call <16 x i8> @llvm.x86.avx512.permvar.qi.128(<16 x i8> %a0, <16 x i8> zeroinitializer)
+  ret <16 x i8> %1
+}
+
+define <16 x i8> @zero_test_permvar_qi_128_mask(<16 x i8> %a0, <16 x i8> %passthru, i16 %mask) {
+; CHECK-LABEL: @zero_test_permvar_qi_128_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[A0:%.*]], <16 x i8> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x i8> [[TMP1]], <16 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+;
+  %1 = call <16 x i8> @llvm.x86.avx512.permvar.qi.128(<16 x i8> %a0, <16 x i8> zeroinitializer)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> %passthru
+  ret <16 x i8> %3
+}
+
+define <16 x i8> @shuffle_test_permvar_qi_128(<16 x i8> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_qi_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[A0:%.*]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+;
+  %1 = call <16 x i8> @llvm.x86.avx512.permvar.qi.128(<16 x i8> %a0, <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  ret <16 x i8> %1
+}
+
+define <16 x i8> @shuffle_test_permvar_qi_128_mask(<16 x i8> %a0, <16 x i8> %passthru, i16 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_qi_128_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[A0:%.*]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x i8> [[TMP1]], <16 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+;
+  %1 = call <16 x i8> @llvm.x86.avx512.permvar.qi.128(<16 x i8> %a0, <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> %passthru
+  ret <16 x i8> %3
+}
+
+define <16 x i8> @undef_test_permvar_qi_128(<16 x i8> %a0) {
+; CHECK-LABEL: @undef_test_permvar_qi_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[A0:%.*]], <16 x i8> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
+;
+  %1 = call <16 x i8> @llvm.x86.avx512.permvar.qi.128(<16 x i8> %a0, <16 x i8> <i8 undef, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  ret <16 x i8> %1
+}
+
+define <16 x i8> @undef_test_permvar_qi_128_mask(<16 x i8> %a0, <16 x i8> %passthru, i16 %mask) {
+; CHECK-LABEL: @undef_test_permvar_qi_128_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[A0:%.*]], <16 x i8> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x i8> [[TMP1]], <16 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+;
+  %1 = call <16 x i8> @llvm.x86.avx512.permvar.qi.128(<16 x i8> %a0, <16 x i8> <i8 undef, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x i8> %1, <16 x i8> %passthru
+  ret <16 x i8> %3
+}
+
+declare <32 x i8> @llvm.x86.avx512.permvar.qi.256(<32 x i8>, <32 x i8>)
+
+define <32 x i8> @identity_test_permvar_qi_256(<32 x i8> %a0) {
+; CHECK-LABEL: @identity_test_permvar_qi_256(
+; CHECK-NEXT:    ret <32 x i8> [[A0:%.*]]
+;
+  %1 = call <32 x i8> @llvm.x86.avx512.permvar.qi.256(<32 x i8> %a0, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>)
+  ret <32 x i8> %1
+}
+
+define <32 x i8> @identity_test_permvar_qi_256_mask(<32 x i8> %a0, <32 x i8> %passthru, i32 %mask) {
+; CHECK-LABEL: @identity_test_permvar_qi_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[MASK:%.*]] to <32 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <32 x i1> [[TMP1]], <32 x i8> [[A0:%.*]], <32 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <32 x i8> [[TMP2]]
+;
+  %1 = call <32 x i8> @llvm.x86.avx512.permvar.qi.256(<32 x i8> %a0, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31>)
+  %2 = bitcast i32 %mask to <32 x i1>
+  %3 = select <32 x i1> %2, <32 x i8> %1, <32 x i8> %passthru
+  ret <32 x i8> %3
+}
+
+define <32 x i8> @zero_test_permvar_qi_256(<32 x i8> %a0) {
+; CHECK-LABEL: @zero_test_permvar_qi_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[A0:%.*]], <32 x i8> undef, <32 x i32> zeroinitializer
+; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
+;
+  %1 = call <32 x i8> @llvm.x86.avx512.permvar.qi.256(<32 x i8> %a0, <32 x i8> zeroinitializer)
+  ret <32 x i8> %1
+}
+
+define <32 x i8> @zero_test_permvar_qi_256_mask(<32 x i8> %a0, <32 x i8> %passthru, i32 %mask) {
+; CHECK-LABEL: @zero_test_permvar_qi_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[A0:%.*]], <32 x i8> undef, <32 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[MASK:%.*]] to <32 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <32 x i1> [[TMP2]], <32 x i8> [[TMP1]], <32 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <32 x i8> [[TMP3]]
+;
+  %1 = call <32 x i8> @llvm.x86.avx512.permvar.qi.256(<32 x i8> %a0, <32 x i8> zeroinitializer)
+  %2 = bitcast i32 %mask to <32 x i1>
+  %3 = select <32 x i1> %2, <32 x i8> %1, <32 x i8> %passthru
+  ret <32 x i8> %3
+}
+
+define <32 x i8> @shuffle_test_permvar_qi_256(<32 x i8> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_qi_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[A0:%.*]], <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
+;
+  %1 = call <32 x i8> @llvm.x86.avx512.permvar.qi.256(<32 x i8> %a0, <32 x i8> <i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  ret <32 x i8> %1
+}
+
+define <32 x i8> @shuffle_test_permvar_qi_256_mask(<32 x i8> %a0, <32 x i8> %passthru, i32 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_qi_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[A0:%.*]], <32 x i8> undef, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[MASK:%.*]] to <32 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <32 x i1> [[TMP2]], <32 x i8> [[TMP1]], <32 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <32 x i8> [[TMP3]]
+;
+  %1 = call <32 x i8> @llvm.x86.avx512.permvar.qi.256(<32 x i8> %a0, <32 x i8> <i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  %2 = bitcast i32 %mask to <32 x i1>
+  %3 = select <32 x i1> %2, <32 x i8> %1, <32 x i8> %passthru
+  ret <32 x i8> %3
+}
+
+define <32 x i8> @undef_test_permvar_qi_256(<32 x i8> %a0) {
+; CHECK-LABEL: @undef_test_permvar_qi_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[A0:%.*]], <32 x i8> undef, <32 x i32> <i32 undef, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
+;
+  %1 = call <32 x i8> @llvm.x86.avx512.permvar.qi.256(<32 x i8> %a0, <32 x i8> <i8 undef, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  ret <32 x i8> %1
+}
+
+define <32 x i8> @undef_test_permvar_qi_256_mask(<32 x i8> %a0, <32 x i8> %passthru, i32 %mask) {
+; CHECK-LABEL: @undef_test_permvar_qi_256_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[A0:%.*]], <32 x i8> undef, <32 x i32> <i32 undef, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i32 [[MASK:%.*]] to <32 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <32 x i1> [[TMP2]], <32 x i8> [[TMP1]], <32 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <32 x i8> [[TMP3]]
+;
+  %1 = call <32 x i8> @llvm.x86.avx512.permvar.qi.256(<32 x i8> %a0, <32 x i8> <i8 undef, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  %2 = bitcast i32 %mask to <32 x i1>
+  %3 = select <32 x i1> %2, <32 x i8> %1, <32 x i8> %passthru
+  ret <32 x i8> %3
+}
+
+declare <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8>, <64 x i8>)
+
+define <64 x i8> @identity_test_permvar_qi_512(<64 x i8> %a0) {
+; CHECK-LABEL: @identity_test_permvar_qi_512(
+; CHECK-NEXT:    ret <64 x i8> [[A0:%.*]]
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %a0, <64 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47, i8 48, i8 49, i8 50, i8 51, i8 52, i8 53, i8 54, i8 55, i8 56, i8 57, i8 58, i8 59, i8 60, i8 61, i8 62, i8 63>)
+  ret <64 x i8> %1
+}
+
+define <64 x i8> @identity_test_permvar_qi_512_mask(<64 x i8> %a0, <64 x i8> %passthru, i64 %mask) {
+; CHECK-LABEL: @identity_test_permvar_qi_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64 [[MASK:%.*]] to <64 x i1>
+; CHECK-NEXT:    [[TMP2:%.*]] = select <64 x i1> [[TMP1]], <64 x i8> [[A0:%.*]], <64 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <64 x i8> [[TMP2]]
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %a0, <64 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 39, i8 40, i8 41, i8 42, i8 43, i8 44, i8 45, i8 46, i8 47, i8 48, i8 49, i8 50, i8 51, i8 52, i8 53, i8 54, i8 55, i8 56, i8 57, i8 58, i8 59, i8 60, i8 61, i8 62, i8 63>)
+  %2 = bitcast i64 %mask to <64 x i1>
+  %3 = select <64 x i1> %2, <64 x i8> %1, <64 x i8> %passthru
+  ret <64 x i8> %3
+}
+
+define <64 x i8> @zero_test_permvar_qi_512(<64 x i8> %a0) {
+; CHECK-LABEL: @zero_test_permvar_qi_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[A0:%.*]], <64 x i8> undef, <64 x i32> zeroinitializer
+; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %a0, <64 x i8> zeroinitializer)
+  ret <64 x i8> %1
+}
+
+define <64 x i8> @zero_test_permvar_qi_512_mask(<64 x i8> %a0, <64 x i8> %passthru, i64 %mask) {
+; CHECK-LABEL: @zero_test_permvar_qi_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[A0:%.*]], <64 x i8> undef, <64 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[MASK:%.*]] to <64 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <64 x i1> [[TMP2]], <64 x i8> [[TMP1]], <64 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <64 x i8> [[TMP3]]
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %a0, <64 x i8> zeroinitializer)
+  %2 = bitcast i64 %mask to <64 x i1>
+  %3 = select <64 x i1> %2, <64 x i8> %1, <64 x i8> %passthru
+  ret <64 x i8> %3
+}
+
+define <64 x i8> @shuffle_test_permvar_qi_512(<64 x i8> %a0) {
+; CHECK-LABEL: @shuffle_test_permvar_qi_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[A0:%.*]], <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %a0, <64 x i8> <i8 63, i8 62, i8 61, i8 60, i8 59, i8 58, i8 57, i8 56, i8 55, i8 54, i8 53, i8 52, i8 51, i8 50, i8 49, i8 48, i8 47, i8 46, i8 45, i8 44, i8 43, i8 42, i8 41, i8 40, i8 39, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  ret <64 x i8> %1
+}
+
+define <64 x i8> @shuffle_test_permvar_qi_512_mask(<64 x i8> %a0, <64 x i8> %passthru, i64 %mask) {
+; CHECK-LABEL: @shuffle_test_permvar_qi_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[A0:%.*]], <64 x i8> undef, <64 x i32> <i32 63, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[MASK:%.*]] to <64 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <64 x i1> [[TMP2]], <64 x i8> [[TMP1]], <64 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <64 x i8> [[TMP3]]
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %a0, <64 x i8> <i8 63, i8 62, i8 61, i8 60, i8 59, i8 58, i8 57, i8 56, i8 55, i8 54, i8 53, i8 52, i8 51, i8 50, i8 49, i8 48, i8 47, i8 46, i8 45, i8 44, i8 43, i8 42, i8 41, i8 40, i8 39, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  %2 = bitcast i64 %mask to <64 x i1>
+  %3 = select <64 x i1> %2, <64 x i8> %1, <64 x i8> %passthru
+  ret <64 x i8> %3
+}
+
+define <64 x i8> @undef_test_permvar_qi_512(<64 x i8> %a0) {
+; CHECK-LABEL: @undef_test_permvar_qi_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[A0:%.*]], <64 x i8> undef, <64 x i32> <i32 undef, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %a0, <64 x i8> <i8 undef, i8 62, i8 61, i8 60, i8 59, i8 58, i8 57, i8 56, i8 55, i8 54, i8 53, i8 52, i8 51, i8 50, i8 49, i8 48, i8 47, i8 46, i8 45, i8 44, i8 43, i8 42, i8 41, i8 40, i8 39, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  ret <64 x i8> %1
+}
+
+define <64 x i8> @undef_test_permvar_qi_512_mask(<64 x i8> %a0, <64 x i8> %passthru, i64 %mask) {
+; CHECK-LABEL: @undef_test_permvar_qi_512_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[A0:%.*]], <64 x i8> undef, <64 x i32> <i32 undef, i32 62, i32 61, i32 60, i32 59, i32 58, i32 57, i32 56, i32 55, i32 54, i32 53, i32 52, i32 51, i32 50, i32 49, i32 48, i32 47, i32 46, i32 45, i32 44, i32 43, i32 42, i32 41, i32 40, i32 39, i32 38, i32 37, i32 36, i32 35, i32 34, i32 33, i32 32, i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[MASK:%.*]] to <64 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <64 x i1> [[TMP2]], <64 x i8> [[TMP1]], <64 x i8> [[PASSTHRU:%.*]]
+; CHECK-NEXT:    ret <64 x i8> [[TMP3]]
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.permvar.qi.512(<64 x i8> %a0, <64 x i8> <i8 undef, i8 62, i8 61, i8 60, i8 59, i8 58, i8 57, i8 56, i8 55, i8 54, i8 53, i8 52, i8 51, i8 50, i8 49, i8 48, i8 47, i8 46, i8 45, i8 44, i8 43, i8 42, i8 41, i8 40, i8 39, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>)
+  %2 = bitcast i64 %mask to <64 x i1>
+  %3 = select <64 x i1> %2, <64 x i8> %1, <64 x i8> %passthru
+  ret <64 x i8> %3
+}
+
+declare <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float>, <16 x float>, i32)
+
+define <16 x float> @test_add_ps(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @test_add_ps(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a, <16 x float> %b, i32 4)
+  ret <16 x float> %1
+}
+
+define <16 x float> @test_add_ps_round(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @test_add_ps_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 8)
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a, <16 x float> %b, i32 8)
+  ret <16 x float> %1
+}
+
+define <16 x float> @test_add_ps_mask(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
+; CHECK-LABEL: @test_add_ps_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[C:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a, <16 x float> %b, i32 4)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %c
+  ret <16 x float> %3
+}
+
+define <16 x float> @test_add_ps_mask_round(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
+; CHECK-LABEL: @test_add_ps_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 8)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[C:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.add.ps.512(<16 x float> %a, <16 x float> %b, i32 8)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %c
+  ret <16 x float> %3
+}
+
+declare <8 x double> @llvm.x86.avx512.add.pd.512(<8 x double>, <8 x double>, i32)
+
+define <8 x double> @test_add_pd(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @test_add_pd(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.add.pd.512(<8 x double> %a, <8 x double> %b, i32 4)
+  ret <8 x double> %1
+}
+
+define <8 x double> @test_add_pd_round(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @test_add_pd_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x double> @llvm.x86.avx512.add.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 8)
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.add.pd.512(<8 x double> %a, <8 x double> %b, i32 8)
+  ret <8 x double> %1
+}
+
+define <8 x double> @test_add_pd_mask(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_add_pd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[C:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.add.pd.512(<8 x double> %a, <8 x double> %b, i32 4)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %c
+  ret <8 x double> %3
+}
+
+define <8 x double> @test_add_pd_mask_round(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_add_pd_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x double> @llvm.x86.avx512.add.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 8)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[C:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.add.pd.512(<8 x double> %a, <8 x double> %b, i32 8)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %c
+  ret <8 x double> %3
+}
+
+declare <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float>, <16 x float>, i32)
+
+define <16 x float> @test_sub_ps(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @test_sub_ps(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a, <16 x float> %b, i32 4)
+  ret <16 x float> %1
+}
+
+define <16 x float> @test_sub_ps_round(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @test_sub_ps_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 8)
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a, <16 x float> %b, i32 8)
+  ret <16 x float> %1
+}
+
+define <16 x float> @test_sub_ps_mask(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
+; CHECK-LABEL: @test_sub_ps_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[C:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a, <16 x float> %b, i32 4)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %c
+  ret <16 x float> %3
+}
+
+define <16 x float> @test_sub_ps_mask_round(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
+; CHECK-LABEL: @test_sub_ps_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 8)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[C:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.sub.ps.512(<16 x float> %a, <16 x float> %b, i32 8)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %c
+  ret <16 x float> %3
+}
+
+declare <8 x double> @llvm.x86.avx512.sub.pd.512(<8 x double>, <8 x double>, i32)
+
+define <8 x double> @test_sub_pd(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @test_sub_pd(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.sub.pd.512(<8 x double> %a, <8 x double> %b, i32 4)
+  ret <8 x double> %1
+}
+
+define <8 x double> @test_sub_pd_round(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @test_sub_pd_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x double> @llvm.x86.avx512.sub.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 8)
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.sub.pd.512(<8 x double> %a, <8 x double> %b, i32 8)
+  ret <8 x double> %1
+}
+
+define <8 x double> @test_sub_pd_mask(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_sub_pd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[C:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.sub.pd.512(<8 x double> %a, <8 x double> %b, i32 4)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %c
+  ret <8 x double> %3
+}
+
+define <8 x double> @test_sub_pd_mask_round(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_sub_pd_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x double> @llvm.x86.avx512.sub.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 8)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[C:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.sub.pd.512(<8 x double> %a, <8 x double> %b, i32 8)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %c
+  ret <8 x double> %3
+}
+
+declare <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float>, <16 x float>, i32)
+
+define <16 x float> @test_mul_ps(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @test_mul_ps(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a, <16 x float> %b, i32 4)
+  ret <16 x float> %1
+}
+
+define <16 x float> @test_mul_ps_round(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @test_mul_ps_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 8)
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a, <16 x float> %b, i32 8)
+  ret <16 x float> %1
+}
+
+define <16 x float> @test_mul_ps_mask(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
+; CHECK-LABEL: @test_mul_ps_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[C:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a, <16 x float> %b, i32 4)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %c
+  ret <16 x float> %3
+}
+
+define <16 x float> @test_mul_ps_mask_round(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
+; CHECK-LABEL: @test_mul_ps_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 8)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[C:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.mul.ps.512(<16 x float> %a, <16 x float> %b, i32 8)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %c
+  ret <16 x float> %3
+}
+
+declare <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double>, <8 x double>, i32)
+
+define <8 x double> @test_mul_pd(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @test_mul_pd(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> %a, <8 x double> %b, i32 4)
+  ret <8 x double> %1
+}
+
+define <8 x double> @test_mul_pd_round(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @test_mul_pd_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 8)
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> %a, <8 x double> %b, i32 8)
+  ret <8 x double> %1
+}
+
+define <8 x double> @test_mul_pd_mask(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mul_pd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[C:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> %a, <8 x double> %b, i32 4)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %c
+  ret <8 x double> %3
+}
+
+define <8 x double> @test_mul_pd_mask_round(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_mul_pd_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 8)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[C:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.mul.pd.512(<8 x double> %a, <8 x double> %b, i32 8)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %c
+  ret <8 x double> %3
+}
+
+declare <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float>, <16 x float>, i32)
+
+define <16 x float> @test_div_ps(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @test_div_ps(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a, <16 x float> %b, i32 4)
+  ret <16 x float> %1
+}
+
+define <16 x float> @test_div_ps_round(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @test_div_ps_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 8)
+; CHECK-NEXT:    ret <16 x float> [[TMP1]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a, <16 x float> %b, i32 8)
+  ret <16 x float> %1
+}
+
+define <16 x float> @test_div_ps_mask(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
+; CHECK-LABEL: @test_div_ps_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[C:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a, <16 x float> %b, i32 4)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %c
+  ret <16 x float> %3
+}
+
+define <16 x float> @test_div_ps_mask_round(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask) {
+; CHECK-LABEL: @test_div_ps_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> [[A:%.*]], <16 x float> [[B:%.*]], i32 8)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i16 [[MASK:%.*]] to <16 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <16 x i1> [[TMP2]], <16 x float> [[TMP1]], <16 x float> [[C:%.*]]
+; CHECK-NEXT:    ret <16 x float> [[TMP3]]
+;
+  %1 = call <16 x float> @llvm.x86.avx512.div.ps.512(<16 x float> %a, <16 x float> %b, i32 8)
+  %2 = bitcast i16 %mask to <16 x i1>
+  %3 = select <16 x i1> %2, <16 x float> %1, <16 x float> %c
+  ret <16 x float> %3
+}
+
+declare <8 x double> @llvm.x86.avx512.div.pd.512(<8 x double>, <8 x double>, i32)
+
+define <8 x double> @test_div_pd(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @test_div_pd(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.div.pd.512(<8 x double> %a, <8 x double> %b, i32 4)
+  ret <8 x double> %1
+}
+
+define <8 x double> @test_div_pd_round(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @test_div_pd_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x double> @llvm.x86.avx512.div.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 8)
+; CHECK-NEXT:    ret <8 x double> [[TMP1]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.div.pd.512(<8 x double> %a, <8 x double> %b, i32 8)
+  ret <8 x double> %1
+}
+
+define <8 x double> @test_div_pd_mask(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_div_pd_mask(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[C:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.div.pd.512(<8 x double> %a, <8 x double> %b, i32 4)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %c
+  ret <8 x double> %3
+}
+
+define <8 x double> @test_div_pd_mask_round(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 %mask) {
+; CHECK-LABEL: @test_div_pd_mask_round(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x double> @llvm.x86.avx512.div.pd.512(<8 x double> [[A:%.*]], <8 x double> [[B:%.*]], i32 8)
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8 [[MASK:%.*]] to <8 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = select <8 x i1> [[TMP2]], <8 x double> [[TMP1]], <8 x double> [[C:%.*]]
+; CHECK-NEXT:    ret <8 x double> [[TMP3]]
+;
+  %1 = call <8 x double> @llvm.x86.avx512.div.pd.512(<8 x double> %a, <8 x double> %b, i32 8)
+  %2 = bitcast i8 %mask to <8 x i1>
+  %3 = select <8 x i1> %2, <8 x double> %1, <8 x double> %c
+  ret <8 x double> %3
+}
+
+declare i32 @llvm.x86.avx512.vcomi.ss(<4 x float>, <4 x float>, i32, i32)
+
+define i32 @test_comi_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_comi_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.avx512.vcomi.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]], i32 0, i32 4)
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.avx512.vcomi.ss(<4 x float> %4, <4 x float> %8, i32 0, i32 4)
+  ret i32 %9
+}
+
+declare i32 @llvm.x86.avx512.vcomi.sd(<2 x double>, <2 x double>, i32, i32)
+
+define i32 @test_comi_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_comi_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]], i32 0, i32 4)
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> %2, <2 x double> %4, i32 0, i32 4)
+  ret i32 %5
+}
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-avx512.ll b/llvm/test/Transforms/InstCombine/X86/x86-avx512.ll
index 7eabd4165beaf..ee48cef20f204 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-avx512.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-avx512.ll
@@ -758,21 +758,21 @@ define i8 @test_cmp_sd(<2 x double> %a, <2 x double> %b, i8 %mask) {
 
 define i64 @test(float %f, double %d) {
 ; CHECK-LABEL: @test(
-; CHECK-NEXT:    [[V03:%.*]] = insertelement <4 x float> undef, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[V03:%.*]] = insertelement <4 x float> poison, float [[F:%.*]], i32 0
 ; CHECK-NEXT:    [[T0:%.*]] = tail call i32 @llvm.x86.avx512.vcvtss2si32(<4 x float> [[V03]], i32 4)
-; CHECK-NEXT:    [[V13:%.*]] = insertelement <4 x float> undef, float [[F]], i32 0
+; CHECK-NEXT:    [[V13:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
 ; CHECK-NEXT:    [[T1:%.*]] = tail call i64 @llvm.x86.avx512.vcvtss2si64(<4 x float> [[V13]], i32 4)
-; CHECK-NEXT:    [[V23:%.*]] = insertelement <4 x float> undef, float [[F]], i32 0
+; CHECK-NEXT:    [[V23:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
 ; CHECK-NEXT:    [[T2:%.*]] = tail call i32 @llvm.x86.avx512.cvttss2si(<4 x float> [[V23]], i32 4)
-; CHECK-NEXT:    [[V33:%.*]] = insertelement <4 x float> undef, float [[F]], i32 0
+; CHECK-NEXT:    [[V33:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
 ; CHECK-NEXT:    [[T3:%.*]] = tail call i64 @llvm.x86.avx512.cvttss2si64(<4 x float> [[V33]], i32 4)
-; CHECK-NEXT:    [[V41:%.*]] = insertelement <2 x double> undef, double [[D:%.*]], i32 0
+; CHECK-NEXT:    [[V41:%.*]] = insertelement <2 x double> poison, double [[D:%.*]], i32 0
 ; CHECK-NEXT:    [[T4:%.*]] = tail call i32 @llvm.x86.avx512.vcvtsd2si32(<2 x double> [[V41]], i32 4)
-; CHECK-NEXT:    [[V51:%.*]] = insertelement <2 x double> undef, double [[D]], i32 0
+; CHECK-NEXT:    [[V51:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
 ; CHECK-NEXT:    [[T5:%.*]] = tail call i64 @llvm.x86.avx512.vcvtsd2si64(<2 x double> [[V51]], i32 4)
-; CHECK-NEXT:    [[V61:%.*]] = insertelement <2 x double> undef, double [[D]], i32 0
+; CHECK-NEXT:    [[V61:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
 ; CHECK-NEXT:    [[T6:%.*]] = tail call i32 @llvm.x86.avx512.cvttsd2si(<2 x double> [[V61]], i32 4)
-; CHECK-NEXT:    [[V71:%.*]] = insertelement <2 x double> undef, double [[D]], i32 0
+; CHECK-NEXT:    [[V71:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
 ; CHECK-NEXT:    [[T7:%.*]] = tail call i64 @llvm.x86.avx512.cvttsd2si64(<2 x double> [[V71]], i32 4)
 ; CHECK-NEXT:    [[T8:%.*]] = add i32 [[T0]], [[T2]]
 ; CHECK-NEXT:    [[T9:%.*]] = add i32 [[T4]], [[T6]]
@@ -838,21 +838,21 @@ declare i64 @llvm.x86.avx512.cvttsd2si64(<2 x double>, i32)
 
 define i64 @test2(float %f, double %d) {
 ; CHECK-LABEL: @test2(
-; CHECK-NEXT:    [[V03:%.*]] = insertelement <4 x float> undef, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[V03:%.*]] = insertelement <4 x float> poison, float [[F:%.*]], i32 0
 ; CHECK-NEXT:    [[T0:%.*]] = tail call i32 @llvm.x86.avx512.vcvtss2usi32(<4 x float> [[V03]], i32 4)
-; CHECK-NEXT:    [[V13:%.*]] = insertelement <4 x float> undef, float [[F]], i32 0
+; CHECK-NEXT:    [[V13:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
 ; CHECK-NEXT:    [[T1:%.*]] = tail call i64 @llvm.x86.avx512.vcvtss2usi64(<4 x float> [[V13]], i32 4)
-; CHECK-NEXT:    [[V23:%.*]] = insertelement <4 x float> undef, float [[F]], i32 0
+; CHECK-NEXT:    [[V23:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
 ; CHECK-NEXT:    [[T2:%.*]] = tail call i32 @llvm.x86.avx512.cvttss2usi(<4 x float> [[V23]], i32 4)
-; CHECK-NEXT:    [[V33:%.*]] = insertelement <4 x float> undef, float [[F]], i32 0
+; CHECK-NEXT:    [[V33:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
 ; CHECK-NEXT:    [[T3:%.*]] = tail call i64 @llvm.x86.avx512.cvttss2usi64(<4 x float> [[V33]], i32 4)
-; CHECK-NEXT:    [[V41:%.*]] = insertelement <2 x double> undef, double [[D:%.*]], i32 0
+; CHECK-NEXT:    [[V41:%.*]] = insertelement <2 x double> poison, double [[D:%.*]], i32 0
 ; CHECK-NEXT:    [[T4:%.*]] = tail call i32 @llvm.x86.avx512.vcvtsd2usi32(<2 x double> [[V41]], i32 4)
-; CHECK-NEXT:    [[V51:%.*]] = insertelement <2 x double> undef, double [[D]], i32 0
+; CHECK-NEXT:    [[V51:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
 ; CHECK-NEXT:    [[T5:%.*]] = tail call i64 @llvm.x86.avx512.vcvtsd2usi64(<2 x double> [[V51]], i32 4)
-; CHECK-NEXT:    [[V61:%.*]] = insertelement <2 x double> undef, double [[D]], i32 0
+; CHECK-NEXT:    [[V61:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
 ; CHECK-NEXT:    [[T6:%.*]] = tail call i32 @llvm.x86.avx512.cvttsd2usi(<2 x double> [[V61]], i32 4)
-; CHECK-NEXT:    [[V71:%.*]] = insertelement <2 x double> undef, double [[D]], i32 0
+; CHECK-NEXT:    [[V71:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
 ; CHECK-NEXT:    [[T7:%.*]] = tail call i64 @llvm.x86.avx512.cvttsd2usi64(<2 x double> [[V71]], i32 4)
 ; CHECK-NEXT:    [[T8:%.*]] = add i32 [[T0]], [[T2]]
 ; CHECK-NEXT:    [[T9:%.*]] = add i32 [[T4]], [[T6]]
@@ -3372,8 +3372,8 @@ declare i32 @llvm.x86.avx512.vcomi.ss(<4 x float>, <4 x float>, i32, i32)
 
 define i32 @test_comi_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_comi_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.avx512.vcomi.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]], i32 0, i32 4)
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -3393,8 +3393,8 @@ declare i32 @llvm.x86.avx512.vcomi.sd(<2 x double>, <2 x double>, i32, i32)
 
 define i32 @test_comi_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_comi_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.avx512.vcomi.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]], i32 0, i32 4)
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-insertps.ll b/llvm/test/Transforms/InstCombine/X86/x86-insertps.ll
index 634de193c023c..0bd36e623a083 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-insertps.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-insertps.ll
@@ -36,7 +36,7 @@ define <4 x float> @insertps_0x0c(<4 x float> %v1, <4 x float> %v2) {
 
 define <4 x float> @insertps_0x15_single_input(<4 x float> %v1) {
 ; CHECK-LABEL: @insertps_0x15_single_input(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[V1:%.*]], <4 x float> <float 0.000000e+00, float undef, float 0.000000e+00, float undef>, <4 x i32> <i32 4, i32 0, i32 6, i32 3>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[V1:%.*]], <4 x float> <float 0.000000e+00, float poison, float 0.000000e+00, float poison>, <4 x i32> <i32 4, i32 0, i32 6, i32 3>
 ; CHECK-NEXT:    ret <4 x float> [[TMP1]]
 ;
   %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v1, i8 21)
@@ -47,7 +47,7 @@ define <4 x float> @insertps_0x15_single_input(<4 x float> %v1) {
 
 define <4 x float> @insertps_0x1a_single_input(<4 x float> %v1) {
 ; CHECK-LABEL: @insertps_0x1a_single_input(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[V1:%.*]], <4 x float> <float undef, float 0.000000e+00, float undef, float 0.000000e+00>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[V1:%.*]], <4 x float> <float poison, float 0.000000e+00, float poison, float 0.000000e+00>, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
 ; CHECK-NEXT:    ret <4 x float> [[TMP1]]
 ;
   %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v1, i8 26)
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-masked-memops.ll b/llvm/test/Transforms/InstCombine/X86/x86-masked-memops.ll
index ff4c05164d000..d89ec85842755 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-masked-memops.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-masked-memops.ll
@@ -66,7 +66,7 @@ define <4 x float> @mload_real_ones(i8* %f) {
 define <4 x float> @mload_one_one(i8* %f) {
 ; CHECK-LABEL: @mload_one_one(
 ; CHECK-NEXT:    [[CASTVEC:%.*]] = bitcast i8* [[F:%.*]] to <4 x float>*
-; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* [[CASTVEC]], i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef>)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* [[CASTVEC]], i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison>)
 ; CHECK-NEXT:    ret <4 x float> [[TMP1]]
 ;
   %ld = tail call <4 x float> @llvm.x86.avx.maskload.ps(i8* %f, <4 x i32> <i32 0, i32 0, i32 0, i32 -1>)
@@ -78,7 +78,7 @@ define <4 x float> @mload_one_one(i8* %f) {
 define <2 x double> @mload_one_one_double(i8* %f) {
 ; CHECK-LABEL: @mload_one_one_double(
 ; CHECK-NEXT:    [[CASTVEC:%.*]] = bitcast i8* [[F:%.*]] to <2 x double>*
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* [[CASTVEC]], i32 1, <2 x i1> <i1 true, i1 false>, <2 x double> <double undef, double 0.000000e+00>)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* [[CASTVEC]], i32 1, <2 x i1> <i1 true, i1 false>, <2 x double> <double poison, double 0.000000e+00>)
 ; CHECK-NEXT:    ret <2 x double> [[TMP1]]
 ;
   %ld = tail call <2 x double> @llvm.x86.avx.maskload.pd(i8* %f, <2 x i64> <i64 -1, i64 0>)
@@ -90,7 +90,7 @@ define <2 x double> @mload_one_one_double(i8* %f) {
 define <8 x float> @mload_v8f32(i8* %f) {
 ; CHECK-LABEL: @mload_v8f32(
 ; CHECK-NEXT:    [[CASTVEC:%.*]] = bitcast i8* [[F:%.*]] to <8 x float>*
-; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* [[CASTVEC]], i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x float> @llvm.masked.load.v8f32.p0v8f32(<8 x float>* [[CASTVEC]], i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>)
 ; CHECK-NEXT:    ret <8 x float> [[TMP1]]
 ;
   %ld = tail call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %f, <8 x i32> <i32 0, i32 0, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 0>)
@@ -118,7 +118,7 @@ define <8 x float> @mload_v8f32_cmp(i8* %f, <8 x float> %src0, <8 x float> %src1
 define <4 x double> @mload_v4f64(i8* %f) {
 ; CHECK-LABEL: @mload_v4f64(
 ; CHECK-NEXT:    [[CASTVEC:%.*]] = bitcast i8* [[F:%.*]] to <4 x double>*
-; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* [[CASTVEC]], i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> <double undef, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x double> @llvm.masked.load.v4f64.p0v4f64(<4 x double>* [[CASTVEC]], i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> <double poison, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00>)
 ; CHECK-NEXT:    ret <4 x double> [[TMP1]]
 ;
   %ld = tail call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %f, <4 x i64> <i64 -1, i64 0, i64 0, i64 0>)
@@ -130,7 +130,7 @@ define <4 x double> @mload_v4f64(i8* %f) {
 define <4 x i32> @mload_v4i32(i8* %f) {
 ; CHECK-LABEL: @mload_v4i32(
 ; CHECK-NEXT:    [[CASTVEC:%.*]] = bitcast i8* [[F:%.*]] to <4 x i32>*
-; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[CASTVEC]], i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32> <i32 0, i32 0, i32 0, i32 undef>)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* [[CASTVEC]], i32 1, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32> <i32 0, i32 0, i32 0, i32 poison>)
 ; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
 ;
   %ld = tail call <4 x i32> @llvm.x86.avx2.maskload.d(i8* %f, <4 x i32> <i32 0, i32 0, i32 0, i32 -1>)
@@ -140,7 +140,7 @@ define <4 x i32> @mload_v4i32(i8* %f) {
 define <2 x i64> @mload_v2i64(i8* %f) {
 ; CHECK-LABEL: @mload_v2i64(
 ; CHECK-NEXT:    [[CASTVEC:%.*]] = bitcast i8* [[F:%.*]] to <2 x i64>*
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* [[CASTVEC]], i32 1, <2 x i1> <i1 true, i1 false>, <2 x i64> <i64 undef, i64 0>)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.masked.load.v2i64.p0v2i64(<2 x i64>* [[CASTVEC]], i32 1, <2 x i1> <i1 true, i1 false>, <2 x i64> <i64 poison, i64 0>)
 ; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
 ;
   %ld = tail call <2 x i64> @llvm.x86.avx2.maskload.q(i8* %f, <2 x i64> <i64 -1, i64 0>)
@@ -150,7 +150,7 @@ define <2 x i64> @mload_v2i64(i8* %f) {
 define <8 x i32> @mload_v8i32(i8* %f) {
 ; CHECK-LABEL: @mload_v8i32(
 ; CHECK-NEXT:    [[CASTVEC:%.*]] = bitcast i8* [[F:%.*]] to <8 x i32>*
-; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* [[CASTVEC]], i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i32> <i32 0, i32 0, i32 0, i32 undef, i32 0, i32 0, i32 0, i32 0>)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* [[CASTVEC]], i32 1, <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i32> <i32 0, i32 0, i32 0, i32 poison, i32 0, i32 0, i32 0, i32 0>)
 ; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
 ;
   %ld = tail call <8 x i32> @llvm.x86.avx2.maskload.d.256(i8* %f, <8 x i32> <i32 0, i32 0, i32 0, i32 -1, i32 0, i32 0, i32 0, i32 0>)
@@ -160,7 +160,7 @@ define <8 x i32> @mload_v8i32(i8* %f) {
 define <4 x i64> @mload_v4i64(i8* %f) {
 ; CHECK-LABEL: @mload_v4i64(
 ; CHECK-NEXT:    [[CASTVEC:%.*]] = bitcast i8* [[F:%.*]] to <4 x i64>*
-; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* [[CASTVEC]], i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> <i64 undef, i64 0, i64 0, i64 0>)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i64> @llvm.masked.load.v4i64.p0v4i64(<4 x i64>* [[CASTVEC]], i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> <i64 poison, i64 0, i64 0, i64 0>)
 ; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
 ;
   %ld = tail call <4 x i64> @llvm.x86.avx2.maskload.q.256(i8* %f, <4 x i64> <i64 -1, i64 0, i64 0, i64 0>)
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-muldq.ll b/llvm/test/Transforms/InstCombine/X86/x86-muldq.ll
index be1ba8ad14e8f..c6e5f4791ecea 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-muldq.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-muldq.ll
@@ -163,8 +163,8 @@ define <2 x i64> @test_demanded_elts_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) {
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[A1:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <2 x i64>
 ; CHECK-NEXT:    [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64>
-; CHECK-NEXT:    [[TMP5:%.*]] = and <2 x i64> [[TMP3]], <i64 4294967295, i64 undef>
-; CHECK-NEXT:    [[TMP6:%.*]] = and <2 x i64> [[TMP4]], <i64 4294967295, i64 undef>
+; CHECK-NEXT:    [[TMP5:%.*]] = and <2 x i64> [[TMP3]], <i64 4294967295, i64 poison>
+; CHECK-NEXT:    [[TMP6:%.*]] = and <2 x i64> [[TMP4]], <i64 4294967295, i64 poison>
 ; CHECK-NEXT:    [[TMP7:%.*]] = mul <2 x i64> [[TMP5]], [[TMP6]]
 ; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP7]], <2 x i64> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i64> [[TMP8]]
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
new file mode 100644
index 0000000000000..5f3b991be512a
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll
@@ -0,0 +1,635 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+
+;
+; UNDEF Elts
+;
+
+define <8 x i16> @undef_packssdw_128() {
+; CHECK-LABEL: @undef_packssdw_128(
+; CHECK-NEXT:    ret <8 x i16> undef
+;
+  %1 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> undef, <4 x i32> undef)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @undef_packusdw_128() {
+; CHECK-LABEL: @undef_packusdw_128(
+; CHECK-NEXT:    ret <8 x i16> undef
+;
+  %1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> undef, <4 x i32> undef)
+  ret <8 x i16> %1
+}
+
+define <16 x i8> @undef_packsswb_128() {
+; CHECK-LABEL: @undef_packsswb_128(
+; CHECK-NEXT:    ret <16 x i8> undef
+;
+  %1 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> undef, <8 x i16> undef)
+  ret <16 x i8> %1
+}
+
+define <16 x i8> @undef_packuswb_128() {
+; CHECK-LABEL: @undef_packuswb_128(
+; CHECK-NEXT:    ret <16 x i8> undef
+;
+  %1 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> undef, <8 x i16> undef)
+  ret <16 x i8> %1
+}
+
+define <16 x i16> @undef_packssdw_256() {
+; CHECK-LABEL: @undef_packssdw_256(
+; CHECK-NEXT:    ret <16 x i16> undef
+;
+  %1 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> undef, <8 x i32> undef)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @undef_packusdw_256() {
+; CHECK-LABEL: @undef_packusdw_256(
+; CHECK-NEXT:    ret <16 x i16> undef
+;
+  %1 = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> undef, <8 x i32> undef)
+  ret <16 x i16> %1
+}
+
+define <32 x i8> @undef_packsswb_256() {
+; CHECK-LABEL: @undef_packsswb_256(
+; CHECK-NEXT:    ret <32 x i8> undef
+;
+  %1 = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> undef, <16 x i16> undef)
+  ret <32 x i8> %1
+}
+
+define <32 x i8> @undef_packuswb_256() {
+; CHECK-LABEL: @undef_packuswb_256(
+; CHECK-NEXT:    ret <32 x i8> undef
+;
+  %1 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> undef, <16 x i16> undef)
+  ret <32 x i8> %1
+}
+
+define <32 x i16> @undef_packssdw_512() {
+; CHECK-LABEL: @undef_packssdw_512(
+; CHECK-NEXT:    ret <32 x i16> undef
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> undef, <16 x i32> undef)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @undef_packusdw_512() {
+; CHECK-LABEL: @undef_packusdw_512(
+; CHECK-NEXT:    ret <32 x i16> undef
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> undef, <16 x i32> undef)
+  ret <32 x i16> %1
+}
+
+define <64 x i8> @undef_packsswb_512() {
+; CHECK-LABEL: @undef_packsswb_512(
+; CHECK-NEXT:    ret <64 x i8> undef
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16> undef, <32 x i16> undef)
+  ret <64 x i8> %1
+}
+
+define <64 x i8> @undef_packuswb_512() {
+; CHECK-LABEL: @undef_packuswb_512(
+; CHECK-NEXT:    ret <64 x i8> undef
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.packuswb.512(<32 x i16> undef, <32 x i16> undef)
+  ret <64 x i8> %1
+}
+
+;
+; Constant Folding
+;
+
+define <8 x i16> @fold_packssdw_128() {
+; CHECK-LABEL: @fold_packssdw_128(
+; CHECK-NEXT:    ret <8 x i16> <i16 0, i16 -1, i16 32767, i16 -32768, i16 0, i16 0, i16 0, i16 0>
+;
+  %1 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> <i32 0, i32 -1, i32 65536, i32 -131072>, <4 x i32> zeroinitializer)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @fold_packusdw_128() {
+; CHECK-LABEL: @fold_packusdw_128(
+; CHECK-NEXT:    ret <8 x i16> <i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 0, i16 -32768, i16 -1>
+;
+  %1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> undef, <4 x i32> <i32 0, i32 -1, i32 32768, i32 65537>)
+  ret <8 x i16> %1
+}
+
+define <16 x i8> @fold_packsswb_128() {
+; CHECK-LABEL: @fold_packsswb_128(
+; CHECK-NEXT:    ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>
+;
+  %1 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> zeroinitializer, <8 x i16> undef)
+  ret <16 x i8> %1
+}
+
+define <16 x i8> @fold_packuswb_128() {
+; CHECK-LABEL: @fold_packuswb_128(
+; CHECK-NEXT:    ret <16 x i8> <i8 0, i8 1, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 15, i8 0, i8 127, i8 0, i8 1, i8 0, i8 1, i8 0, i8 0>
+;
+  %1 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> <i16 0, i16 1, i16 -1, i16 255, i16 65535, i16 -32768, i16 -127, i16 15>, <8 x i16> <i16 -15, i16 127, i16 32768, i16 -65535, i16 -255, i16 1, i16 -1, i16 0>)
+  ret <16 x i8> %1
+}
+
+define <16 x i16> @fold_packssdw_256() {
+; CHECK-LABEL: @fold_packssdw_256(
+; CHECK-NEXT:    ret <16 x i16> <i16 0, i16 256, i16 32767, i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 -127, i16 -32768, i16 -32767, i16 32767, i16 undef, i16 undef, i16 undef, i16 undef>
+;
+  %1 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> <i32 0, i32 256, i32 65535, i32 -65536, i32 -127, i32 -32768, i32 -32767, i32 32767>, <8 x i32> undef)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @fold_packusdw_256() {
+; CHECK-LABEL: @fold_packusdw_256(
+; CHECK-NEXT:    ret <16 x i16> <i16 0, i16 0, i16 0, i16 -1, i16 0, i16 256, i16 -1, i16 0, i16 127, i16 -32768, i16 32767, i16 0, i16 0, i16 0, i16 0, i16 32767>
+;
+  %1 = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> <i32 0, i32 -256, i32 -65535, i32 65536, i32 127, i32 32768, i32 32767, i32 -32767>, <8 x i32> <i32 0, i32 256, i32 65535, i32 -65536, i32 -127, i32 -32768, i32 -32767, i32 32767>)
+  ret <16 x i16> %1
+}
+
+define <32 x i8> @fold_packsswb_256() {
+; CHECK-LABEL: @fold_packsswb_256(
+; CHECK-NEXT:    ret <32 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+;
+  %1 = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> undef, <16 x i16> zeroinitializer)
+  ret <32 x i8> %1
+}
+
+define <32 x i8> @fold_packuswb_256() {
+; CHECK-LABEL: @fold_packuswb_256(
+; CHECK-NEXT:    ret <32 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64>
+;
+  %1 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> zeroinitializer, <16 x i16> <i16 0, i16 -127, i16 -128, i16 -32768, i16 65536, i16 255, i16 256, i16 512, i16 -1, i16 1, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64>)
+  ret <32 x i8> %1
+}
+
+define <32 x i16> @fold_packssdw_512() {
+; CHECK-LABEL: @fold_packssdw_512(
+; CHECK-NEXT:    ret <32 x i16> <i16 0, i16 512, i16 32767, i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 -127, i16 -32768, i16 -32767, i16 32767, i16 undef, i16 undef, i16 undef, i16 undef, i16 0, i16 512, i16 32767, i16 -32768, i16 undef, i16 undef, i16 undef, i16 undef, i16 -127, i16 -32768, i16 -32767, i16 32767, i16 undef, i16 undef, i16 undef, i16 undef>
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> <i32 0, i32 512, i32 65535, i32 -65536, i32 -127, i32 -32768, i32 -32767, i32 32767, i32 0, i32 512, i32 65535, i32 -65536, i32 -127, i32 -32768, i32 -32767, i32 32767>, <16 x i32> undef)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @fold_packusdw_512() {
+; CHECK-LABEL: @fold_packusdw_512(
+; CHECK-NEXT:    ret <32 x i16> <i16 0, i16 0, i16 0, i16 -1, i16 0, i16 512, i16 -1, i16 0, i16 127, i16 -32768, i16 32767, i16 0, i16 0, i16 0, i16 0, i16 32767, i16 0, i16 0, i16 0, i16 -1, i16 0, i16 512, i16 -1, i16 0, i16 127, i16 -32768, i16 32767, i16 0, i16 0, i16 0, i16 0, i16 32767>
+;
+  %1 = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> <i32 0, i32 -512, i32 -65535, i32 65536, i32 127, i32 32768, i32 32767, i32 -32767, i32 0, i32 -512, i32 -65535, i32 65536, i32 127, i32 32768, i32 32767, i32 -32767>, <16 x i32> <i32 0, i32 512, i32 65535, i32 -65536, i32 -127, i32 -32768, i32 -32767, i32 32767, i32 0, i32 512, i32 65535, i32 -65536, i32 -127, i32 -32768, i32 -32767, i32 32767>)
+  ret <32 x i16> %1
+}
+
+define <64 x i8> @fold_packsswb_512() {
+; CHECK-LABEL: @fold_packsswb_512(
+; CHECK-NEXT:    ret <64 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16> undef, <32 x i16> zeroinitializer)
+  ret <64 x i8> %1
+}
+
+define <64 x i8> @fold_packuswb_512() {
+; CHECK-LABEL: @fold_packuswb_512(
+; CHECK-NEXT:    ret <64 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64>
+;
+  %1 = call <64 x i8> @llvm.x86.avx512.packuswb.512(<32 x i16> zeroinitializer, <32 x i16> <i16 0, i16 -127, i16 -128, i16 -32768, i16 65536, i16 255, i16 512, i16 512, i16 -1, i16 1, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64, i16 0, i16 -127, i16 -128, i16 -32768, i16 65536, i16 255, i16 512, i16 512, i16 -1, i16 1, i16 2, i16 4, i16 8, i16 16, i16 32, i16 64>)
+  ret <64 x i8> %1
+}
+
+;
+; Demanded Elts
+;
+
+define <8 x i16> @elts_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: @elts_packssdw_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[A0:%.*]], <4 x i32> undef)
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+;
+  %1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 undef, i32 undef>
+  %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 undef>
+  %3 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %1, <4 x i32> %2)
+  %4 = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 7, i32 7, i32 7, i32 7>
+  ret <8 x i16> %4
+}
+
+define <8 x i16> @elts_packusdw_128(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: @elts_packusdw_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]])
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 undef>
+; CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+;
+  %1 = insertelement <4 x i32> %a0, i32 0, i32 0
+  %2 = insertelement <4 x i32> %a1, i32 0, i32 3
+  %3 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %1, <4 x i32> %2)
+  %4 = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 undef>
+  ret <8 x i16> %4
+}
+
+define <16 x i8> @elts_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) {
+; CHECK-LABEL: @elts_packsswb_128(
+; CHECK-NEXT:    ret <16 x i8> zeroinitializer
+;
+  %1 = insertelement <8 x i16> %a0, i16 0, i32 0
+  %2 = insertelement <8 x i16> %a1, i16 0, i32 0
+  %3 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %1, <8 x i16> %2)
+  %4 = shufflevector <16 x i8> %3, <16 x i8> undef, <16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
+  ret <16 x i8> %4
+}
+
+define <16 x i8> @elts_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) {
+; CHECK-LABEL: @elts_packuswb_128(
+; CHECK-NEXT:    ret <16 x i8> undef
+;
+  %1 = insertelement <8 x i16> poison, i16 0, i32 0
+  %2 = insertelement <8 x i16> poison, i16 0, i32 0
+  %3 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %1, <8 x i16> %2)
+  %4 = shufflevector <16 x i8> %3, <16 x i8> undef, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+  ret <16 x i8> %4
+}
+
+define <16 x i16> @elts_packssdw_256(<8 x i32> %a0, <8 x i32> %a1) {
+; CHECK-LABEL: @elts_packssdw_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[A0:%.*]], <8 x i32> undef)
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> undef, <16 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 undef, i32 undef, i32 11, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <16 x i16> [[TMP2]]
+;
+  %1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 undef, i32 2, i32 1, i32 undef, i32 undef, i32 6, i32 5, i32 undef>
+  %3 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %1, <8 x i32> %2)
+  %4 = shufflevector <16 x i16> %3, <16 x i16> undef, <16 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 11, i32 12, i32 undef, i32 undef, i32 15>
+  ret <16 x i16> %4
+}
+
+define <16 x i16> @elts_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) {
+; CHECK-LABEL: @elts_packusdw_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> poison, <8 x i32> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <16 x i16> [[TMP2]], <16 x i16> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+  %3 = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %1, <8 x i32> %2)
+  %4 = shufflevector <16 x i16> %3, <16 x i16> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <16 x i16> %4
+}
+
+define <32 x i8> @elts_packsswb_256(<16 x i16> %a0, <16 x i16> %a1) {
+; CHECK-LABEL: @elts_packsswb_256(
+; CHECK-NEXT:    ret <32 x i8> zeroinitializer
+;
+  %1 = insertelement <16 x i16> %a0, i16 0, i32 0
+  %2 = insertelement <16 x i16> %a1, i16 0, i32 8
+  %3 = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %1, <16 x i16> %2)
+  %4 = shufflevector <32 x i8> %3, <32 x i8> undef, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24>
+  ret <32 x i8> %4
+}
+
+define <32 x i8> @elts_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) {
+; CHECK-LABEL: @elts_packuswb_256(
+; CHECK-NEXT:    ret <32 x i8> undef
+;
+  %1 = insertelement <16 x i16> poison, i16 0, i32 1
+  %2 = insertelement <16 x i16> poison, i16 0, i32 0
+  %3 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %1, <16 x i16> %2)
+  %4 = shufflevector <32 x i8> %3, <32 x i8> undef, <32 x i32> zeroinitializer
+  ret <32 x i8> %4
+}
+
+define <32 x i16> @elts_packssdw_512(<16 x i32> %a0, <16 x i32> %a1) {
+; CHECK-LABEL: @elts_packssdw_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> [[A0:%.*]], <16 x i32> undef)
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <32 x i16> [[TMP1]], <32 x i16> undef, <32 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 undef, i32 undef, i32 11, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 18, i32 19, i32 undef, i32 undef, i32 undef, i32 undef, i32 24, i32 undef, i32 undef, i32 27, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <32 x i16> [[TMP2]]
+;
+  %1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 undef, i32 2, i32 1, i32 undef, i32 undef, i32 6, i32 5, i32 undef, i32 undef, i32 10, i32 9, i32 undef, i32 undef, i32 14, i32 13, i32 undef>
+  %3 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> %1, <16 x i32> %2)
+  %4 = shufflevector <32 x i16> %3, <32 x i16> undef, <32 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 11, i32 12, i32 undef, i32 undef, i32 15, i32 undef, i32 undef, i32 18, i32 19, i32 20, i32 undef, i32 undef, i32 23, i32 24, i32 undef, i32 undef, i32 27, i32 28, i32 undef, i32 undef, i32 31>
+  ret <32 x i16> %4
+}
+
+define <32 x i16> @elts_packusdw_512(<16 x i32> %a0, <16 x i32> %a1) {
+; CHECK-LABEL: @elts_packusdw_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
+; CHECK-NEXT:    [[TMP2:%.*]] = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> poison, <16 x i32> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <32 x i16> [[TMP2]], <32 x i16> undef, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
+;
+  %1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  %2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
+  %3 = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> %1, <16 x i32> %2)
+  %4 = shufflevector <32 x i16> %3, <32 x i16> undef, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef>
+  ret <32 x i16> %4
+}
+
+define <64 x i8> @elts_packsswb_512(<32 x i16> %a0, <32 x i16> %a1) {
+; CHECK-LABEL: @elts_packsswb_512(
+; CHECK-NEXT:    ret <64 x i8> zeroinitializer
+;
+  %1 = insertelement <32 x i16> %a0, i16 0, i32 0
+  %2 = insertelement <32 x i16> %a1, i16 0, i32 8
+  %3 = insertelement <32 x i16> %1, i16 0, i32 16
+  %4 = insertelement <32 x i16> %2, i16 0, i32 24
+  %5 = call <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16> %3, <32 x i16> %4)
+  %6 = shufflevector <64 x i8> %5, <64 x i8> undef, <64 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56, i32 56>
+  ret <64 x i8> %6
+}
+
+define <64 x i8> @elts_packuswb_512(<32 x i16> %a0, <32 x i16> %a1) {
+; CHECK-LABEL: @elts_packuswb_512(
+; CHECK-NEXT:    ret <64 x i8> undef
+;
+  %1 = insertelement <32 x i16> poison, i16 0, i32 1
+  %2 = insertelement <32 x i16> poison, i16 0, i32 0
+  %3 = call <64 x i8> @llvm.x86.avx512.packuswb.512(<32 x i16> %1, <32 x i16> %2)
+  %4 = shufflevector <64 x i8> %3, <64 x i8> undef, <64 x i32> zeroinitializer
+  ret <64 x i8> %4
+}
+
+;
+; Truncation (without Saturation)
+;
+
+define <8 x i16> @trunc_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: @trunc_packssdw_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> [[A0:%.*]], <i32 17, i32 17, i32 17, i32 17>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <4 x i32> [[A1:%.*]], <i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])
+; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+;
+  %1 = ashr <4 x i32> %a0, <i32 17, i32 17, i32 17, i32 17>
+  %2 = and  <4 x i32> %a1, <i32 15, i32 15, i32 15, i32 15>
+  %3 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %1, <4 x i32> %2)
+  ret <8 x i16> %3
+}
+
+define <8 x i16> @trunc_packusdw_128(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: @trunc_packusdw_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> [[A0:%.*]], <i32 17, i32 17, i32 17, i32 17>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <4 x i32> [[A1:%.*]], <i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])
+; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+;
+  %1 = lshr <4 x i32> %a0, <i32 17, i32 17, i32 17, i32 17>
+  %2 = and  <4 x i32> %a1, <i32 15, i32 15, i32 15, i32 15>
+  %3 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %1, <4 x i32> %2)
+  ret <8 x i16> %3
+}
+
+define <16 x i8> @trunc_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) {
+; CHECK-LABEL: @trunc_packsswb_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i16> [[A0:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <8 x i16> [[A1:%.*]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])
+; CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+;
+  %1 = ashr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %2 = and  <8 x i16> %a1, <i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1>
+  %3 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %1, <8 x i16> %2)
+  ret <16 x i8> %3
+}
+
+define <16 x i8> @trunc_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) {
+; CHECK-LABEL: @trunc_packuswb_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i16> [[A0:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <8 x i16> [[A1:%.*]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])
+; CHECK-NEXT:    ret <16 x i8> [[TMP3]]
+;
+  %1 = lshr <8 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %2 = and  <8 x i16> %a1, <i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1>
+  %3 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %1, <8 x i16> %2)
+  ret <16 x i8> %3
+}
+
+define <16 x i16> @trunc_packssdw_256(<8 x i32> %a0, <8 x i32> %a1) {
+; CHECK-LABEL: @trunc_packssdw_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[A0:%.*]], <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <8 x i32> [[A1:%.*]], <i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[TMP1]], <8 x i32> [[TMP2]])
+; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %1 = ashr <8 x i32> %a0, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+  %2 = ashr <8 x i32> %a1, <i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23>
+  %3 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %1, <8 x i32> %2)
+  ret <16 x i16> %3
+}
+
+define <16 x i16> @trunc_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) {
+; CHECK-LABEL: @trunc_packusdw_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i32> [[A0:%.*]], <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <8 x i32> [[A1:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[TMP1]], <8 x i32> [[TMP2]])
+; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %1 = lshr <8 x i32> %a0, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+  %2 = and  <8 x i32> %a1, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+  %3 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %1, <8 x i32> %2)
+  ret <16 x i16> %3
+}
+
+define <32 x i8> @trunc_packsswb_256(<16 x i16> %a0, <16 x i16> %a1) {
+; CHECK-LABEL: @trunc_packsswb_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i16> [[A0:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <16 x i16> [[A1:%.*]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> [[TMP1]], <16 x i16> [[TMP2]])
+; CHECK-NEXT:    ret <32 x i8> [[TMP3]]
+;
+  %1 = ashr <16 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %2 = and  <16 x i16> %a1, <i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1>
+  %3 = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %1, <16 x i16> %2)
+  ret <32 x i8> %3
+}
+
+define <32 x i8> @trunc_packuswb_256(<16 x i16> %a0, <16 x i16> %a1) {
+; CHECK-LABEL: @trunc_packuswb_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i16> [[A0:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <16 x i16> [[A1:%.*]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> [[TMP1]], <16 x i16> [[TMP2]])
+; CHECK-NEXT:    ret <32 x i8> [[TMP3]]
+;
+  %1 = lshr <16 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %2 = and  <16 x i16> %a1, <i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1>
+  %3 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %1, <16 x i16> %2)
+  ret <32 x i8> %3
+}
+
+define <32 x i16> @trunc_packssdw_512(<16 x i32> %a0, <16 x i32> %a1) {
+; CHECK-LABEL: @trunc_packssdw_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i32> [[A0:%.*]], <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <16 x i32> [[A1:%.*]], <i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> [[TMP1]], <16 x i32> [[TMP2]])
+; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
+;
+  %1 = ashr <16 x i32> %a0, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+  %2 = ashr <16 x i32> %a1, <i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23>
+  %3 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> %1, <16 x i32> %2)
+  ret <32 x i16> %3
+}
+
+define <32 x i16> @trunc_packusdw_512(<16 x i32> %a0, <16 x i32> %a1) {
+; CHECK-LABEL: @trunc_packusdw_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i32> [[A0:%.*]], <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <16 x i32> [[A1:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> [[TMP1]], <16 x i32> [[TMP2]])
+; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
+;
+  %1 = lshr <16 x i32> %a0, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
+  %2 = and  <16 x i32> %a1, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+  %3 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> %1, <16 x i32> %2)
+  ret <32 x i16> %3
+}
+
+define <64 x i8> @trunc_packsswb_512(<32 x i16> %a0, <32 x i16> %a1) {
+; CHECK-LABEL: @trunc_packsswb_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <32 x i16> [[A0:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <32 x i16> [[A1:%.*]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16> [[TMP1]], <32 x i16> [[TMP2]])
+; CHECK-NEXT:    ret <64 x i8> [[TMP3]]
+;
+  %1 = ashr <32 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %2 = and  <32 x i16> %a1, <i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1>
+  %3 = call <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16> %1, <32 x i16> %2)
+  ret <64 x i8> %3
+}
+
+define <64 x i8> @trunc_packuswb_512(<32 x i16> %a0, <32 x i16> %a1) {
+; CHECK-LABEL: @trunc_packuswb_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <32 x i16> [[A0:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    [[TMP2:%.*]] = and <32 x i16> [[A1:%.*]], <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT:    [[TMP3:%.*]] = call <64 x i8> @llvm.x86.avx512.packuswb.512(<32 x i16> [[TMP1]], <32 x i16> [[TMP2]])
+; CHECK-NEXT:    ret <64 x i8> [[TMP3]]
+;
+  %1 = lshr <32 x i16> %a0, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+  %2 = and  <32 x i16> %a1, <i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1, i16  1>
+  %3 = call <64 x i8> @llvm.x86.avx512.packuswb.512(<32 x i16> %1, <32 x i16> %2)
+  ret <64 x i8> %3
+}
+
+;
+; Signed Pack Comparison Results
+;
+
+define <8 x i16> @cmp_packssdw_128(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) {
+; CHECK-LABEL: @cmp_packssdw_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <4 x i32> [[A0:%.*]], [[A1:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <4 x i32> [[A2:%.*]], [[A3:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    [[TMP4:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>
+; CHECK-NEXT:    [[TMP5:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[TMP3]], <4 x i32> [[TMP4]])
+; CHECK-NEXT:    ret <8 x i16> [[TMP5]]
+;
+  %1 = icmp eq <4 x i32> %a0, %a1
+  %2 = icmp eq <4 x i32> %a2, %a3
+  %3 = sext <4 x i1> %1 to <4 x i32>
+  %4 = sext <4 x i1> %2 to <4 x i32>
+  %5 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %3, <4 x i32> %4)
+  ret <8 x i16> %5
+}
+
+define <16 x i8> @cmp_packsswb_128(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %a2, <8 x i16> %a3) {
+; CHECK-LABEL: @cmp_packsswb_128(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <8 x i16> [[A0:%.*]], [[A1:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <8 x i16> [[A2:%.*]], [[A3:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
+; CHECK-NEXT:    [[TMP4:%.*]] = sext <8 x i1> [[TMP2]] to <8 x i16>
+; CHECK-NEXT:    [[TMP5:%.*]] = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> [[TMP3]], <8 x i16> [[TMP4]])
+; CHECK-NEXT:    ret <16 x i8> [[TMP5]]
+;
+  %1 = icmp eq <8 x i16> %a0, %a1
+  %2 = icmp eq <8 x i16> %a2, %a3
+  %3 = sext <8 x i1> %1 to <8 x i16>
+  %4 = sext <8 x i1> %2 to <8 x i16>
+  %5 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %3, <8 x i16> %4)
+  ret <16 x i8> %5
+}
+
+define <16 x i16> @cmp_packssdw_256(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> %a2, <8 x i32> %a3) {
+; CHECK-LABEL: @cmp_packssdw_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <8 x i32> [[A0:%.*]], [[A1:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <8 x i32> [[A2:%.*]], [[A3:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i32>
+; CHECK-NEXT:    [[TMP4:%.*]] = sext <8 x i1> [[TMP2]] to <8 x i32>
+; CHECK-NEXT:    [[TMP5:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[TMP3]], <8 x i32> [[TMP4]])
+; CHECK-NEXT:    ret <16 x i16> [[TMP5]]
+;
+  %1 = icmp eq <8 x i32> %a0, %a1
+  %2 = icmp eq <8 x i32> %a2, %a3
+  %3 = sext <8 x i1> %1 to <8 x i32>
+  %4 = sext <8 x i1> %2 to <8 x i32>
+  %5 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %3, <8 x i32> %4)
+  ret <16 x i16> %5
+}
+
+define <32 x i8> @cmp_packsswb_256(<16 x i16> %a0, <16 x i16> %a1, <16 x i16> %a2, <16 x i16> %a3) {
+; CHECK-LABEL: @cmp_packsswb_256(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <16 x i16> [[A0:%.*]], [[A1:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <16 x i16> [[A2:%.*]], [[A3:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = sext <16 x i1> [[TMP1]] to <16 x i16>
+; CHECK-NEXT:    [[TMP4:%.*]] = sext <16 x i1> [[TMP2]] to <16 x i16>
+; CHECK-NEXT:    [[TMP5:%.*]] = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> [[TMP3]], <16 x i16> [[TMP4]])
+; CHECK-NEXT:    ret <32 x i8> [[TMP5]]
+;
+  %1 = icmp eq <16 x i16> %a0, %a1
+  %2 = icmp eq <16 x i16> %a2, %a3
+  %3 = sext <16 x i1> %1 to <16 x i16>
+  %4 = sext <16 x i1> %2 to <16 x i16>
+  %5 = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> %3, <16 x i16> %4)
+  ret <32 x i8> %5
+}
+
+define <32 x i16> @cmp_packssdw_512(<16 x i32> %a0, <16 x i32> %a1, <16 x i32> %a2, <16 x i32> %a3) {
+; CHECK-LABEL: @cmp_packssdw_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <16 x i32> [[A0:%.*]], [[A1:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <16 x i32> [[A2:%.*]], [[A3:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = sext <16 x i1> [[TMP1]] to <16 x i32>
+; CHECK-NEXT:    [[TMP4:%.*]] = sext <16 x i1> [[TMP2]] to <16 x i32>
+; CHECK-NEXT:    [[TMP5:%.*]] = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> [[TMP3]], <16 x i32> [[TMP4]])
+; CHECK-NEXT:    ret <32 x i16> [[TMP5]]
+;
+  %1 = icmp eq <16 x i32> %a0, %a1
+  %2 = icmp eq <16 x i32> %a2, %a3
+  %3 = sext <16 x i1> %1 to <16 x i32>
+  %4 = sext <16 x i1> %2 to <16 x i32>
+  %5 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> %3, <16 x i32> %4)
+  ret <32 x i16> %5
+}
+
+define <64 x i8> @cmp_packsswb_512(<32 x i16> %a0, <32 x i16> %a1, <32 x i16> %a2, <32 x i16> %a3) {
+; CHECK-LABEL: @cmp_packsswb_512(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <32 x i16> [[A0:%.*]], [[A1:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <32 x i16> [[A2:%.*]], [[A3:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = sext <32 x i1> [[TMP1]] to <32 x i16>
+; CHECK-NEXT:    [[TMP4:%.*]] = sext <32 x i1> [[TMP2]] to <32 x i16>
+; CHECK-NEXT:    [[TMP5:%.*]] = call <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16> [[TMP3]], <32 x i16> [[TMP4]])
+; CHECK-NEXT:    ret <64 x i8> [[TMP5]]
+;
+  %1 = icmp eq <32 x i16> %a0, %a1
+  %2 = icmp eq <32 x i16> %a2, %a3
+  %3 = sext <32 x i1> %1 to <32 x i16>
+  %4 = sext <32 x i1> %2 to <32 x i16>
+  %5 = call <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16> %3, <32 x i16> %4)
+  ret <64 x i8> %5
+}
+
+declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind readnone
+declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind readnone
+declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone
+declare <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>) nounwind readnone
+declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>) nounwind readnone
+declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>) nounwind readnone
+declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>) nounwind readnone
+
+declare <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32>, <16 x i32>) nounwind readnone
+declare <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32>, <16 x i32>) nounwind readnone
+declare <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16>, <32 x i16>) nounwind readnone
+declare <64 x i8> @llvm.x86.avx512.packuswb.512(<32 x i16>, <32 x i16>) nounwind readnone
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-pack.ll b/llvm/test/Transforms/InstCombine/X86/x86-pack.ll
index 2a0f2cc5cd4e3..0dfef255c216e 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-pack.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-pack.ll
@@ -269,7 +269,7 @@ define <16 x i16> @elts_packssdw_256(<8 x i32> %a0, <8 x i32> %a1) {
 define <16 x i16> @elts_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) {
 ; CHECK-LABEL: @elts_packusdw_256(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
-; CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> undef, <8 x i32> [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> poison, <8 x i32> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <16 x i16> [[TMP2]], <16 x i16> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
 ;
@@ -318,7 +318,7 @@ define <32 x i16> @elts_packssdw_512(<16 x i32> %a0, <16 x i32> %a1) {
 define <32 x i16> @elts_packusdw_512(<16 x i32> %a0, <16 x i32> %a1) {
 ; CHECK-LABEL: @elts_packusdw_512(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
-; CHECK-NEXT:    [[TMP2:%.*]] = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> undef, <16 x i32> [[TMP1]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> poison, <16 x i32> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <32 x i16> [[TMP2]], <32 x i16> undef, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll b/llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll
index b37e6049f2183..1f6469a49d2a7 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll
@@ -72,7 +72,7 @@ define <16 x i8> @splat_test(<16 x i8> %InVec) {
 
 define <32 x i8> @splat_test_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @splat_test_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> undef, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> poison, <32 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> zeroinitializer)
@@ -81,7 +81,7 @@ define <32 x i8> @splat_test_avx2(<32 x i8> %InVec) {
 
 define <64 x i8> @splat_test_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @splat_test_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> undef, <64 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> poison, <64 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> zeroinitializer)
@@ -93,7 +93,7 @@ define <64 x i8> @splat_test_avx512(<64 x i8> %InVec) {
 
 define <16 x i8> @blend1(<16 x i8> %InVec) {
 ; CHECK-LABEL: @blend1(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 16, i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 16, i32 1, i32 16, i32 3, i32 16, i32 5, i32 16, i32 7, i32 16, i32 9, i32 16, i32 11, i32 16, i32 13, i32 16, i32 15>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 1, i8 -128, i8 3, i8 -128, i8 5, i8 -128, i8 7, i8 -128, i8 9, i8 -128, i8 11, i8 -128, i8 13, i8 -128, i8 15>)
@@ -102,7 +102,7 @@ define <16 x i8> @blend1(<16 x i8> %InVec) {
 
 define <16 x i8> @blend2(<16 x i8> %InVec) {
 ; CHECK-LABEL: @blend2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 16, i32 16, i32 2, i32 3, i32 16, i32 16, i32 6, i32 7, i32 16, i32 16, i32 10, i32 11, i32 16, i32 16, i32 14, i32 15>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 16, i32 16, i32 2, i32 3, i32 16, i32 16, i32 6, i32 7, i32 16, i32 16, i32 10, i32 11, i32 16, i32 16, i32 14, i32 15>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128, i8 2, i8 3, i8 -128, i8 -128, i8 6, i8 7, i8 -128, i8 -128, i8 10, i8 11, i8 -128, i8 -128, i8 14, i8 15>)
@@ -111,7 +111,7 @@ define <16 x i8> @blend2(<16 x i8> %InVec) {
 
 define <16 x i8> @blend3(<16 x i8> %InVec) {
 ; CHECK-LABEL: @blend3(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 4, i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 16, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 4, i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 16, i32 12, i32 13, i32 14, i32 15>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 12, i8 13, i8 14, i8 15>)
@@ -120,7 +120,7 @@ define <16 x i8> @blend3(<16 x i8> %InVec) {
 
 define <16 x i8> @blend4(<16 x i8> %InVec) {
 ; CHECK-LABEL: @blend4(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
@@ -129,7 +129,7 @@ define <16 x i8> @blend4(<16 x i8> %InVec) {
 
 define <16 x i8> @blend5(<16 x i8> %InVec) {
 ; CHECK-LABEL: @blend5(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>)
@@ -138,7 +138,7 @@ define <16 x i8> @blend5(<16 x i8> %InVec) {
 
 define <16 x i8> @blend6(<16 x i8> %InVec) {
 ; CHECK-LABEL: @blend6(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 0, i32 1, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 0, i32 1, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>)
@@ -147,7 +147,7 @@ define <16 x i8> @blend6(<16 x i8> %InVec) {
 
 define <32 x i8> @blend1_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @blend1_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 32, i32 1, i32 32, i32 3, i32 32, i32 5, i32 32, i32 7, i32 32, i32 9, i32 32, i32 11, i32 32, i32 13, i32 32, i32 15, i32 48, i32 17, i32 48, i32 19, i32 48, i32 21, i32 48, i32 23, i32 48, i32 25, i32 48, i32 27, i32 48, i32 29, i32 48, i32 31>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <32 x i32> <i32 32, i32 1, i32 32, i32 3, i32 32, i32 5, i32 32, i32 7, i32 32, i32 9, i32 32, i32 11, i32 32, i32 13, i32 32, i32 15, i32 48, i32 17, i32 48, i32 19, i32 48, i32 21, i32 48, i32 23, i32 48, i32 25, i32 48, i32 27, i32 48, i32 29, i32 48, i32 31>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 -128, i8 1, i8 -128, i8 3, i8 -128, i8 5, i8 -128, i8 7, i8 -128, i8 9, i8 -128, i8 11, i8 -128, i8 13, i8 -128, i8 15, i8 -128, i8 1, i8 -128, i8 3, i8 -128, i8 5, i8 -128, i8 7, i8 -128, i8 9, i8 -128, i8 11, i8 -128, i8 13, i8 -128, i8 15>)
@@ -156,7 +156,7 @@ define <32 x i8> @blend1_avx2(<32 x i8> %InVec) {
 
 define <32 x i8> @blend2_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @blend2_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 32, i32 32, i32 2, i32 3, i32 32, i32 32, i32 6, i32 7, i32 32, i32 32, i32 10, i32 11, i32 32, i32 32, i32 14, i32 15, i32 48, i32 48, i32 18, i32 19, i32 48, i32 48, i32 22, i32 23, i32 48, i32 48, i32 26, i32 27, i32 48, i32 48, i32 30, i32 31>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <32 x i32> <i32 32, i32 32, i32 2, i32 3, i32 32, i32 32, i32 6, i32 7, i32 32, i32 32, i32 10, i32 11, i32 32, i32 32, i32 14, i32 15, i32 48, i32 48, i32 18, i32 19, i32 48, i32 48, i32 22, i32 23, i32 48, i32 48, i32 26, i32 27, i32 48, i32 48, i32 30, i32 31>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 -128, i8 -128, i8 2, i8 3, i8 -128, i8 -128, i8 6, i8 7, i8 -128, i8 -128, i8 10, i8 11, i8 -128, i8 -128, i8 14, i8 15, i8 -128, i8 -128, i8 2, i8 3, i8 -128, i8 -128, i8 6, i8 7, i8 -128, i8 -128, i8 10, i8 11, i8 -128, i8 -128, i8 14, i8 15>)
@@ -165,7 +165,7 @@ define <32 x i8> @blend2_avx2(<32 x i8> %InVec) {
 
 define <32 x i8> @blend3_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @blend3_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 4, i32 5, i32 6, i32 7, i32 32, i32 32, i32 32, i32 32, i32 12, i32 13, i32 14, i32 15, i32 48, i32 48, i32 48, i32 48, i32 20, i32 21, i32 22, i32 23, i32 48, i32 48, i32 48, i32 48, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 4, i32 5, i32 6, i32 7, i32 32, i32 32, i32 32, i32 32, i32 12, i32 13, i32 14, i32 15, i32 48, i32 48, i32 48, i32 48, i32 20, i32 21, i32 22, i32 23, i32 48, i32 48, i32 48, i32 48, i32 28, i32 29, i32 30, i32 31>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 12, i8 13, i8 14, i8 15, i8 -128, i8 -128, i8 -128, i8 -128, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 12, i8 13, i8 14, i8 15>)
@@ -174,7 +174,7 @@ define <32 x i8> @blend3_avx2(<32 x i8> %InVec) {
 
 define <32 x i8> @blend4_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @blend4_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <32 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
@@ -183,7 +183,7 @@ define <32 x i8> @blend4_avx2(<32 x i8> %InVec) {
 
 define <32 x i8> @blend5_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @blend5_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 17, i32 18, i32 19, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 17, i32 18, i32 19, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 0, i8 1, i8 2, i8 3, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>)
@@ -192,7 +192,7 @@ define <32 x i8> @blend5_avx2(<32 x i8> %InVec) {
 
 define <32 x i8> @blend6_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @blend6_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 0, i32 1, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 17, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <32 x i32> <i32 0, i32 1, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 16, i32 17, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 1, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 0, i8 1, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>)
@@ -201,7 +201,7 @@ define <32 x i8> @blend6_avx2(<32 x i8> %InVec) {
 
 define <64 x i8> @blend1_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @blend1_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <64 x i32> <i32 64, i32 1, i32 64, i32 3, i32 64, i32 5, i32 64, i32 7, i32 64, i32 9, i32 64, i32 11, i32 64, i32 13, i32 64, i32 15, i32 80, i32 17, i32 80, i32 19, i32 80, i32 21, i32 80, i32 23, i32 80, i32 25, i32 80, i32 27, i32 80, i32 29, i32 80, i32 31, i32 96, i32 33, i32 96, i32 35, i32 96, i32 37, i32 96, i32 39, i32 96, i32 41, i32 96, i32 43, i32 96, i32 45, i32 96, i32 47, i32 112, i32 49, i32 112, i32 51, i32 112, i32 53, i32 112, i32 55, i32 112, i32 57, i32 112, i32 59, i32 112, i32 61, i32 112, i32 63>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <64 x i32> <i32 64, i32 1, i32 64, i32 3, i32 64, i32 5, i32 64, i32 7, i32 64, i32 9, i32 64, i32 11, i32 64, i32 13, i32 64, i32 15, i32 80, i32 17, i32 80, i32 19, i32 80, i32 21, i32 80, i32 23, i32 80, i32 25, i32 80, i32 27, i32 80, i32 29, i32 80, i32 31, i32 96, i32 33, i32 96, i32 35, i32 96, i32 37, i32 96, i32 39, i32 96, i32 41, i32 96, i32 43, i32 96, i32 45, i32 96, i32 47, i32 112, i32 49, i32 112, i32 51, i32 112, i32 53, i32 112, i32 55, i32 112, i32 57, i32 112, i32 59, i32 112, i32 61, i32 112, i32 63>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 -128, i8 1, i8 -128, i8 3, i8 -128, i8 5, i8 -128, i8 7, i8 -128, i8 9, i8 -128, i8 11, i8 -128, i8 13, i8 -128, i8 15, i8 -128, i8 1, i8 -128, i8 3, i8 -128, i8 5, i8 -128, i8 7, i8 -128, i8 9, i8 -128, i8 11, i8 -128, i8 13, i8 -128, i8 15, i8 -128, i8 1, i8 -128, i8 3, i8 -128, i8 5, i8 -128, i8 7, i8 -128, i8 9, i8 -128, i8 11, i8 -128, i8 13, i8 -128, i8 15, i8 -128, i8 1, i8 -128, i8 3, i8 -128, i8 5, i8 -128, i8 7, i8 -128, i8 9, i8 -128, i8 11, i8 -128, i8 13, i8 -128, i8 15>)
@@ -210,7 +210,7 @@ define <64 x i8> @blend1_avx512(<64 x i8> %InVec) {
 
 define <64 x i8> @blend2_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @blend2_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <64 x i32> <i32 64, i32 64, i32 2, i32 3, i32 64, i32 64, i32 6, i32 7, i32 64, i32 64, i32 10, i32 11, i32 64, i32 64, i32 14, i32 15, i32 80, i32 80, i32 18, i32 19, i32 80, i32 80, i32 22, i32 23, i32 80, i32 80, i32 26, i32 27, i32 80, i32 80, i32 30, i32 31, i32 96, i32 96, i32 34, i32 35, i32 96, i32 96, i32 38, i32 39, i32 96, i32 96, i32 42, i32 43, i32 96, i32 96, i32 46, i32 47, i32 112, i32 112, i32 50, i32 51, i32 112, i32 112, i32 54, i32 55, i32 112, i32 112, i32 58, i32 59, i32 112, i32 112, i32 62, i32 63>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <64 x i32> <i32 64, i32 64, i32 2, i32 3, i32 64, i32 64, i32 6, i32 7, i32 64, i32 64, i32 10, i32 11, i32 64, i32 64, i32 14, i32 15, i32 80, i32 80, i32 18, i32 19, i32 80, i32 80, i32 22, i32 23, i32 80, i32 80, i32 26, i32 27, i32 80, i32 80, i32 30, i32 31, i32 96, i32 96, i32 34, i32 35, i32 96, i32 96, i32 38, i32 39, i32 96, i32 96, i32 42, i32 43, i32 96, i32 96, i32 46, i32 47, i32 112, i32 112, i32 50, i32 51, i32 112, i32 112, i32 54, i32 55, i32 112, i32 112, i32 58, i32 59, i32 112, i32 112, i32 62, i32 63>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 -128, i8 -128, i8 2, i8 3, i8 -128, i8 -128, i8 6, i8 7, i8 -128, i8 -128, i8 10, i8 11, i8 -128, i8 -128, i8 14, i8 15, i8 -128, i8 -128, i8 2, i8 3, i8 -128, i8 -128, i8 6, i8 7, i8 -128, i8 -128, i8 10, i8 11, i8 -128, i8 -128, i8 14, i8 15, i8 -128, i8 -128, i8 2, i8 3, i8 -128, i8 -128, i8 6, i8 7, i8 -128, i8 -128, i8 10, i8 11, i8 -128, i8 -128, i8 14, i8 15, i8 -128, i8 -128, i8 2, i8 3, i8 -128, i8 -128, i8 6, i8 7, i8 -128, i8 -128, i8 10, i8 11, i8 -128, i8 -128, i8 14, i8 15>)
@@ -219,7 +219,7 @@ define <64 x i8> @blend2_avx512(<64 x i8> %InVec) {
 
 define <64 x i8> @blend3_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @blend3_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <64 x i32> <i32 64, i32 64, i32 64, i32 64, i32 4, i32 5, i32 6, i32 7, i32 64, i32 64, i32 64, i32 64, i32 12, i32 13, i32 14, i32 15, i32 80, i32 80, i32 80, i32 80, i32 20, i32 21, i32 22, i32 23, i32 80, i32 80, i32 80, i32 80, i32 28, i32 29, i32 30, i32 31, i32 96, i32 96, i32 96, i32 96, i32 36, i32 37, i32 38, i32 39, i32 96, i32 96, i32 96, i32 96, i32 44, i32 45, i32 46, i32 47, i32 112, i32 112, i32 112, i32 112, i32 52, i32 53, i32 54, i32 55, i32 112, i32 112, i32 112, i32 112, i32 60, i32 61, i32 62, i32 63>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <64 x i32> <i32 64, i32 64, i32 64, i32 64, i32 4, i32 5, i32 6, i32 7, i32 64, i32 64, i32 64, i32 64, i32 12, i32 13, i32 14, i32 15, i32 80, i32 80, i32 80, i32 80, i32 20, i32 21, i32 22, i32 23, i32 80, i32 80, i32 80, i32 80, i32 28, i32 29, i32 30, i32 31, i32 96, i32 96, i32 96, i32 96, i32 36, i32 37, i32 38, i32 39, i32 96, i32 96, i32 96, i32 96, i32 44, i32 45, i32 46, i32 47, i32 112, i32 112, i32 112, i32 112, i32 52, i32 53, i32 54, i32 55, i32 112, i32 112, i32 112, i32 112, i32 60, i32 61, i32 62, i32 63>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 12, i8 13, i8 14, i8 15, i8 -128, i8 -128, i8 -128, i8 -128, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 12, i8 13, i8 14, i8 15, i8 -128, i8 -128, i8 -128, i8 -128, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 12, i8 13, i8 14, i8 15, i8 -128, i8 -128, i8 -128, i8 -128, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 12, i8 13, i8 14, i8 15>)
@@ -228,7 +228,7 @@ define <64 x i8> @blend3_avx512(<64 x i8> %InVec) {
 
 define <64 x i8> @blend4_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @blend4_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <64 x i32> <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <64 x i32> <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
@@ -237,7 +237,7 @@ define <64 x i8> @blend4_avx512(<64 x i8> %InVec) {
 
 define <64 x i8> @blend5_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @blend5_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 16, i32 17, i32 18, i32 19, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 32, i32 33, i32 34, i32 35, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 48, i32 49, i32 50, i32 51, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 16, i32 17, i32 18, i32 19, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 32, i32 33, i32 34, i32 35, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 48, i32 49, i32 50, i32 51, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 1, i8 2, i8 3, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 0, i8 1, i8 2, i8 3, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 0, i8 1, i8 2, i8 3, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 0, i8 1, i8 2, i8 3, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>)
@@ -246,7 +246,7 @@ define <64 x i8> @blend5_avx512(<64 x i8> %InVec) {
 
 define <64 x i8> @blend6_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @blend6_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <64 x i32> <i32 0, i32 1, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 16, i32 17, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 32, i32 33, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 48, i32 49, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <64 x i32> <i32 0, i32 1, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 16, i32 17, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 32, i32 33, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 48, i32 49, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 1, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128,i8 0, i8 1, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 0, i8 1, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 0, i8 1, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>)
@@ -256,7 +256,7 @@ define <64 x i8> @blend6_avx512(<64 x i8> %InVec) {
 ; movq idiom.
 define <16 x i8> @movq_idiom(<16 x i8> %InVec) {
 ; CHECK-LABEL: @movq_idiom(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>)
@@ -265,7 +265,7 @@ define <16 x i8> @movq_idiom(<16 x i8> %InVec) {
 
 define <32 x i8> @movq_idiom_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @movq_idiom_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48, i32 48>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>)
@@ -274,7 +274,7 @@ define <32 x i8> @movq_idiom_avx2(<32 x i8> %InVec) {
 
 define <64 x i8> @movq_idiom_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @movq_idiom_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 80, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 96, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112, i32 112>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>)
@@ -285,7 +285,7 @@ define <64 x i8> @movq_idiom_avx512(<64 x i8> %InVec) {
 
 define <16 x i8> @permute1(<16 x i8> %InVec) {
 ; CHECK-LABEL: @permute1(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 4, i8 5, i8 6, i8 7, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 12, i8 13, i8 14, i8 15>)
@@ -294,7 +294,7 @@ define <16 x i8> @permute1(<16 x i8> %InVec) {
 
 define <16 x i8> @permute2(<16 x i8> %InVec) {
 ; CHECK-LABEL: @permute2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
@@ -303,7 +303,7 @@ define <16 x i8> @permute2(<16 x i8> %InVec) {
 
 define <32 x i8> @permute1_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @permute1_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> undef, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> poison, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 4, i8 5, i8 6, i8 7, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 12, i8 13, i8 14, i8 15, i8 4, i8 5, i8 6, i8 7, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 12, i8 13, i8 14, i8 15>)
@@ -312,7 +312,7 @@ define <32 x i8> @permute1_avx2(<32 x i8> %InVec) {
 
 define <32 x i8> @permute2_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @permute2_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
@@ -321,7 +321,7 @@ define <32 x i8> @permute2_avx2(<32 x i8> %InVec) {
 
 define <64 x i8> @permute1_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @permute1_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> undef, <64 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31, i32 36, i32 37, i32 38, i32 39, i32 36, i32 37, i32 38, i32 39, i32 44, i32 45, i32 46, i32 47, i32 44, i32 45, i32 46, i32 47, i32 52, i32 53, i32 54, i32 55, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 62, i32 63, i32 60, i32 61, i32 62, i32 63>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> poison, <64 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31, i32 36, i32 37, i32 38, i32 39, i32 36, i32 37, i32 38, i32 39, i32 44, i32 45, i32 46, i32 47, i32 44, i32 45, i32 46, i32 47, i32 52, i32 53, i32 54, i32 55, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 62, i32 63, i32 60, i32 61, i32 62, i32 63>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 4, i8 5, i8 6, i8 7, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 12, i8 13, i8 14, i8 15, i8 4, i8 5, i8 6, i8 7, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 12, i8 13, i8 14, i8 15, i8 4, i8 5, i8 6, i8 7, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 12, i8 13, i8 14, i8 15, i8 4, i8 5, i8 6, i8 7, i8 4, i8 5, i8 6, i8 7, i8 12, i8 13, i8 14, i8 15, i8 12, i8 13, i8 14, i8 15>)
@@ -330,7 +330,7 @@ define <64 x i8> @permute1_avx512(<64 x i8> %InVec) {
 
 define <64 x i8> @permute2_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @permute2_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> undef, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> poison, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
@@ -390,7 +390,7 @@ define <64 x i8> @fold_to_zero_vector_avx512_2(<64 x i8> %InVec) {
 
 define <16 x i8> @permute3(<16 x i8> %InVec) {
 ; CHECK-LABEL: @permute3(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 48, i8 17, i8 34, i8 51, i8 20, i8 37, i8 54, i8 23, i8 16, i8 49, i8 66, i8 19, i8 52, i8 69, i8 22, i8 55>)
@@ -399,7 +399,7 @@ define <16 x i8> @permute3(<16 x i8> %InVec) {
 
 define <32 x i8> @permute3_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @permute3_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> undef, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> poison, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 52, i8 21, i8 38, i8 55, i8 20, i8 37, i8 54, i8 23, i8 28, i8 61, i8 78, i8 31, i8 60, i8 29, i8 30, i8 79, i8 52, i8 21, i8 38, i8 55, i8 20, i8 53, i8 102, i8 23, i8 92, i8 93, i8 94, i8 95, i8 108, i8 109, i8 110, i8 111>)
@@ -408,7 +408,7 @@ define <32 x i8> @permute3_avx2(<32 x i8> %InVec) {
 
 define <64 x i8> @permute3_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @permute3_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> undef, <64 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31, i32 36, i32 37, i32 38, i32 39, i32 36, i32 37, i32 38, i32 39, i32 44, i32 45, i32 46, i32 47, i32 44, i32 45, i32 46, i32 47, i32 52, i32 53, i32 54, i32 55, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 62, i32 63, i32 60, i32 61, i32 62, i32 63>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> poison, <64 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 20, i32 21, i32 22, i32 23, i32 20, i32 21, i32 22, i32 23, i32 28, i32 29, i32 30, i32 31, i32 28, i32 29, i32 30, i32 31, i32 36, i32 37, i32 38, i32 39, i32 36, i32 37, i32 38, i32 39, i32 44, i32 45, i32 46, i32 47, i32 44, i32 45, i32 46, i32 47, i32 52, i32 53, i32 54, i32 55, i32 52, i32 53, i32 54, i32 55, i32 60, i32 61, i32 62, i32 63, i32 60, i32 61, i32 62, i32 63>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 52, i8 21, i8 38, i8 55, i8 20, i8 37, i8 54, i8 23, i8 28, i8 61, i8 78, i8 31, i8 60, i8 29, i8 30, i8 79, i8 52, i8 21, i8 38, i8 55, i8 20, i8 53, i8 102, i8 23, i8 92, i8 93, i8 94, i8 95, i8 108, i8 109, i8 110, i8 111, i8 52, i8 21, i8 38, i8 55, i8 20, i8 37, i8 54, i8 23, i8 28, i8 61, i8 78, i8 31, i8 60, i8 29, i8 30, i8 79, i8 52, i8 21, i8 38, i8 55, i8 20, i8 53, i8 102, i8 23, i8 108, i8 109, i8 110, i8 111, i8 124, i8 125, i8 126, i8 127>)
@@ -419,7 +419,7 @@ define <64 x i8> @permute3_avx512(<64 x i8> %InVec) {
 
 define <16 x i8> @fold_with_undef_elts(<16 x i8> %InVec) {
 ; CHECK-LABEL: @fold_with_undef_elts(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 0, i32 16, i32 undef, i32 16, i32 1, i32 16, i32 undef, i32 16, i32 2, i32 16, i32 undef, i32 16, i32 3, i32 16, i32 undef, i32 16>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i8> [[INVEC:%.*]], <16 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 0, i32 16, i32 undef, i32 16, i32 1, i32 16, i32 undef, i32 16, i32 2, i32 16, i32 undef, i32 16, i32 3, i32 16, i32 undef, i32 16>
 ; CHECK-NEXT:    ret <16 x i8> [[TMP1]]
 ;
   %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> <i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128>)
@@ -428,7 +428,7 @@ define <16 x i8> @fold_with_undef_elts(<16 x i8> %InVec) {
 
 define <32 x i8> @fold_with_undef_elts_avx2(<32 x i8> %InVec) {
 ; CHECK-LABEL: @fold_with_undef_elts_avx2(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <32 x i32> <i32 0, i32 32, i32 undef, i32 32, i32 1, i32 32, i32 undef, i32 32, i32 2, i32 32, i32 undef, i32 32, i32 3, i32 32, i32 undef, i32 32, i32 16, i32 48, i32 undef, i32 48, i32 17, i32 48, i32 undef, i32 48, i32 18, i32 48, i32 undef, i32 48, i32 19, i32 48, i32 undef, i32 48>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <32 x i8> [[INVEC:%.*]], <32 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <32 x i32> <i32 0, i32 32, i32 undef, i32 32, i32 1, i32 32, i32 undef, i32 32, i32 2, i32 32, i32 undef, i32 32, i32 3, i32 32, i32 undef, i32 32, i32 16, i32 48, i32 undef, i32 48, i32 17, i32 48, i32 undef, i32 48, i32 18, i32 48, i32 undef, i32 48, i32 19, i32 48, i32 undef, i32 48>
 ; CHECK-NEXT:    ret <32 x i8> [[TMP1]]
 ;
   %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> <i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128>)
@@ -437,7 +437,7 @@ define <32 x i8> @fold_with_undef_elts_avx2(<32 x i8> %InVec) {
 
 define <64 x i8> @fold_with_undef_elts_avx512(<64 x i8> %InVec) {
 ; CHECK-LABEL: @fold_with_undef_elts_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <64 x i32> <i32 0, i32 64, i32 undef, i32 64, i32 1, i32 64, i32 undef, i32 64, i32 2, i32 64, i32 undef, i32 64, i32 3, i32 64, i32 undef, i32 64, i32 16, i32 80, i32 undef, i32 80, i32 17, i32 80, i32 undef, i32 80, i32 18, i32 80, i32 undef, i32 80, i32 19, i32 80, i32 undef, i32 80, i32 32, i32 96, i32 undef, i32 96, i32 33, i32 96, i32 undef, i32 96, i32 34, i32 96, i32 undef, i32 96, i32 35, i32 96, i32 undef, i32 96, i32 48, i32 112, i32 undef, i32 112, i32 49, i32 112, i32 undef, i32 112, i32 50, i32 112, i32 undef, i32 112, i32 51, i32 112, i32 undef, i32 112>
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <64 x i8> [[INVEC:%.*]], <64 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <64 x i32> <i32 0, i32 64, i32 undef, i32 64, i32 1, i32 64, i32 undef, i32 64, i32 2, i32 64, i32 undef, i32 64, i32 3, i32 64, i32 undef, i32 64, i32 16, i32 80, i32 undef, i32 80, i32 17, i32 80, i32 undef, i32 80, i32 18, i32 80, i32 undef, i32 80, i32 19, i32 80, i32 undef, i32 80, i32 32, i32 96, i32 undef, i32 96, i32 33, i32 96, i32 undef, i32 96, i32 34, i32 96, i32 undef, i32 96, i32 35, i32 96, i32 undef, i32 96, i32 48, i32 112, i32 undef, i32 112, i32 49, i32 112, i32 undef, i32 112, i32 50, i32 112, i32 undef, i32 112, i32 51, i32 112, i32 undef, i32 112>
 ; CHECK-NEXT:    ret <64 x i8> [[TMP1]]
 ;
   %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128>)
@@ -498,7 +498,7 @@ define <32 x i8> @demanded_elts_insertion_avx2(<32 x i8> %InVec, <32 x i8> %Base
 
 define <64 x i8> @demanded_elts_insertion_avx512(<64 x i8> %InVec, <64 x i8> %BaseMask, i8 %M0, i8 %M30) {
 ; CHECK-LABEL: @demanded_elts_insertion_avx512(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <64 x i8> undef, i8 [[M0:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <64 x i8> poison, i8 [[M0:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> [[INVEC:%.*]], <64 x i8> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <64 x i8> [[TMP2]], <64 x i8> undef, <64 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <64 x i8> [[TMP3]]
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-sse-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-sse-inseltpoison.ll
new file mode 100644
index 0000000000000..adb6126d81191
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-sse-inseltpoison.ll
@@ -0,0 +1,694 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define float @test_rcp_ss_0(float %a) {
+; CHECK-LABEL: @test_rcp_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    ret float [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 0
+  ret float %6
+}
+
+define float @test_rcp_ss_1(float %a) {
+; CHECK-LABEL: @test_rcp_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 1
+  ret float %6
+}
+
+define float @test_sqrt_ss_0(float %a) {
+; CHECK-LABEL: @test_sqrt_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = call float @llvm.sqrt.f32(float [[A:%.*]])
+; CHECK-NEXT:    ret float [[TMP1]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 0
+  ret float %6
+}
+
+define float @test_sqrt_ss_2(float %a) {
+; CHECK-LABEL: @test_sqrt_ss_2(
+; CHECK-NEXT:    ret float 2.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = tail call <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 2
+  ret float %6
+}
+
+define float @test_rsqrt_ss_0(float %a) {
+; CHECK-LABEL: @test_rsqrt_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    ret float [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 0
+  ret float %6
+}
+
+define float @test_rsqrt_ss_3(float %a) {
+; CHECK-LABEL: @test_rsqrt_ss_3(
+; CHECK-NEXT:    ret float 3.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 3
+  ret float %6
+}
+
+define float @test_add_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_add_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd float [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret float [[TMP1]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %4, <4 x float> %8)
+  %r = extractelement <4 x float> %9, i32 0
+  ret float %r
+}
+
+define float @test_add_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_add_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %4, <4 x float> %5)
+  %7 = extractelement <4 x float> %6, i32 1
+  ret float %7
+}
+
+define float @test_add_ss_2(float %a) {
+; CHECK-LABEL: @test_add_ss_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd float [[A:%.*]], [[A]]
+; CHECK-NEXT:    ret float [[TMP1]]
+;
+  %1 = insertelement <4 x float> zeroinitializer, float %a, i32 0
+  %2 = tail call <4 x float> @llvm.x86.sse.add.ss(<4 x float> %1, <4 x float> %1)
+  %3 = extractelement <4 x float> %2, i32 0
+  ret float %3
+}
+
+define float @test_sub_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_sub_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub float [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret float [[TMP1]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %4, <4 x float> %8)
+  %r = extractelement <4 x float> %9, i32 0
+  ret float %r
+}
+
+define float @test_sub_ss_2(float %a, float %b) {
+; CHECK-LABEL: @test_sub_ss_2(
+; CHECK-NEXT:    ret float 2.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = tail call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %4, <4 x float> %5)
+  %7 = extractelement <4 x float> %6, i32 2
+  ret float %7
+}
+
+define float @test_sub_ss_3(float %a) {
+; CHECK-LABEL: @test_sub_ss_3(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub float [[A:%.*]], [[A]]
+; CHECK-NEXT:    ret float [[TMP1]]
+;
+  %1 = insertelement <4 x float> zeroinitializer, float %a, i32 0
+  %2 = tail call <4 x float> @llvm.x86.sse.sub.ss(<4 x float> %1, <4 x float> %1)
+  %3 = extractelement <4 x float> %2, i32 0
+  ret float %3
+}
+
+define float @test_mul_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_mul_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul float [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret float [[TMP1]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %4, <4 x float> %8)
+  %r = extractelement <4 x float> %9, i32 0
+  ret float %r
+}
+
+define float @test_mul_ss_3(float %a, float %b) {
+; CHECK-LABEL: @test_mul_ss_3(
+; CHECK-NEXT:    ret float 3.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = tail call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %4, <4 x float> %5)
+  %7 = extractelement <4 x float> %6, i32 3
+  ret float %7
+}
+
+define float @test_mul_ss_4(float %a) {
+; CHECK-LABEL: @test_mul_ss_4(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul float [[A:%.*]], [[A]]
+; CHECK-NEXT:    ret float [[TMP1]]
+;
+  %1 = insertelement <4 x float> zeroinitializer, float %a, i32 0
+  %2 = tail call <4 x float> @llvm.x86.sse.mul.ss(<4 x float> %1, <4 x float> %1)
+  %3 = extractelement <4 x float> %2, i32 0
+  ret float %3
+}
+
+define float @test_div_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_div_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv float [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret float [[TMP1]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %4, <4 x float> %8)
+  %r = extractelement <4 x float> %9, i32 0
+  ret float %r
+}
+
+define float @test_div_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_div_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %4, <4 x float> %5)
+  %7 = extractelement <4 x float> %6, i32 1
+  ret float %7
+}
+
+define float @test_div_ss_2(float %a) {
+; CHECK-LABEL: @test_div_ss_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv float [[A:%.*]], [[A]]
+; CHECK-NEXT:    ret float [[TMP1]]
+;
+  %1 = insertelement <4 x float> zeroinitializer, float %a, i32 0
+  %2 = tail call <4 x float> @llvm.x86.sse.div.ss(<4 x float> %1, <4 x float> %1)
+  %3 = extractelement <4 x float> %2, i32 0
+  ret float %3
+}
+
+define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_min_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %a, <4 x float> %3)
+  ret <4 x float> %4
+}
+
+define float @test_min_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_min_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT:    ret float [[TMP4]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %4, <4 x float> %8)
+  %10 = extractelement <4 x float> %9, i32 0
+  ret float %10
+}
+
+define float @test_min_ss_2(float %a, float %b) {
+; CHECK-LABEL: @test_min_ss_2(
+; CHECK-NEXT:    ret float 2.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %4, <4 x float> %5)
+  %7 = extractelement <4 x float> %6, i32 2
+  ret float %7
+}
+
+define float @test_min_ss_3(float %a) {
+; CHECK-LABEL: @test_min_ss_3(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP1]], <4 x float> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    ret float [[TMP3]]
+;
+  %1 = insertelement <4 x float> zeroinitializer, float %a, i32 0
+  %2 = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> %1, <4 x float> %1)
+  %3 = extractelement <4 x float> %2, i32 0
+  ret float %3
+}
+
+define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_max_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %a, <4 x float> %3)
+  ret <4 x float> %4
+}
+
+define float @test_max_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_max_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT:    ret float [[TMP4]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %4, <4 x float> %8)
+  %10 = extractelement <4 x float> %9, i32 0
+  ret float %10
+}
+
+define float @test_max_ss_3(float %a, float %b) {
+; CHECK-LABEL: @test_max_ss_3(
+; CHECK-NEXT:    ret float 3.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %4, <4 x float> %5)
+  %7 = extractelement <4 x float> %6, i32 3
+  ret float %7
+}
+
+define float @test_max_ss_4(float %a) {
+; CHECK-LABEL: @test_max_ss_4(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP1]], <4 x float> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    ret float [[TMP3]]
+;
+  %1 = insertelement <4 x float> zeroinitializer, float %a, i32 0
+  %2 = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> %1, <4 x float> %1)
+  %3 = extractelement <4 x float> %2, i32 0
+  ret float %3
+}
+
+define <4 x float> @test_cmp_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_cmp_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], i8 0)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %a, <4 x float> %3, i8 0)
+  ret <4 x float> %4
+}
+
+define float @test_cmp_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_cmp_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]], i8 0)
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT:    ret float [[R]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %4, <4 x float> %8, i8 0)
+  %r = extractelement <4 x float> %9, i32 0
+  ret float %r
+}
+
+define float @test_cmp_ss_1(float %a, float %b) {
+; CHECK-LABEL: @test_cmp_ss_1(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %4, <4 x float> %5, i8 0)
+  %7 = extractelement <4 x float> %6, i32 1
+  ret float %7
+}
+
+define float @test_cmp_ss_2(float %a) {
+; CHECK-LABEL: @test_cmp_ss_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[TMP1]], <4 x float> [[TMP1]], i8 3)
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    ret float [[TMP3]]
+;
+  %1 = insertelement <4 x float> zeroinitializer, float %a, i32 0
+  %2 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %1, <4 x float> %1, i8 3)
+  %3 = extractelement <4 x float> %2, i32 0
+  ret float %3
+}
+
+define i32 @test_comieq_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_comieq_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comieq.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.comieq.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_comige_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_comige_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comige.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.comige.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_comigt_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_comigt_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comigt.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.comigt.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_comile_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_comile_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comile.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.comile.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_comilt_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_comilt_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comilt.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.comilt.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_comineq_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_comineq_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comineq.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.comineq.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_ucomieq_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_ucomieq_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_ucomige_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_ucomige_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomige.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.ucomige.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_ucomigt_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_ucomigt_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_ucomile_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_ucomile_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomile.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.ucomile.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_ucomilt_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_ucomilt_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+define i32 @test_ucomineq_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_ucomineq_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> %4, <4 x float> %8)
+  ret i32 %9
+}
+
+declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>)
+declare <4 x float> @llvm.x86.sse.sqrt.ss(<4 x float>)
+declare <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float>)
+
+declare <4 x float> @llvm.x86.sse.add.ss(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.div.ss(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8)
+
+declare i32 @llvm.x86.sse.comieq.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.comige.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.comigt.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.comile.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.comilt.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.comineq.ss(<4 x float>, <4 x float>)
+
+declare i32 @llvm.x86.sse.ucomieq.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.ucomige.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.ucomigt.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.ucomile.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.ucomilt.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.ucomineq.ss(<4 x float>, <4 x float>)
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-sse.ll b/llvm/test/Transforms/InstCombine/X86/x86-sse.ll
index a08c9f93079fb..8bbb71ab0ae60 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-sse.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-sse.ll
@@ -4,7 +4,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 
 define float @test_rcp_ss_0(float %a) {
 ; CHECK-LABEL: @test_rcp_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret float [[TMP3]]
@@ -60,7 +60,7 @@ define float @test_sqrt_ss_2(float %a) {
 
 define float @test_rsqrt_ss_0(float %a) {
 ; CHECK-LABEL: @test_rsqrt_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret float [[TMP3]]
@@ -273,8 +273,8 @@ define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) {
 
 define float @test_min_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_min_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
 ; CHECK-NEXT:    ret float [[TMP4]]
@@ -308,7 +308,7 @@ define float @test_min_ss_2(float %a, float %b) {
 
 define float @test_min_ss_3(float %a) {
 ; CHECK-LABEL: @test_min_ss_3(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP1]], <4 x float> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret float [[TMP3]]
@@ -333,8 +333,8 @@ define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) {
 
 define float @test_max_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_max_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
 ; CHECK-NEXT:    ret float [[TMP4]]
@@ -368,7 +368,7 @@ define float @test_max_ss_3(float %a, float %b) {
 
 define float @test_max_ss_4(float %a) {
 ; CHECK-LABEL: @test_max_ss_4(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP1]], <4 x float> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret float [[TMP3]]
@@ -393,8 +393,8 @@ define <4 x float> @test_cmp_ss(<4 x float> %a, <4 x float> %b) {
 
 define float @test_cmp_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_cmp_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]], i8 0)
 ; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
 ; CHECK-NEXT:    ret float [[R]]
@@ -428,7 +428,7 @@ define float @test_cmp_ss_1(float %a, float %b) {
 
 define float @test_cmp_ss_2(float %a) {
 ; CHECK-LABEL: @test_cmp_ss_2(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> [[TMP1]], <4 x float> [[TMP1]], i8 3)
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret float [[TMP3]]
@@ -441,8 +441,8 @@ define float @test_cmp_ss_2(float %a) {
 
 define i32 @test_comieq_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_comieq_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comieq.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -460,8 +460,8 @@ define i32 @test_comieq_ss_0(float %a, float %b) {
 
 define i32 @test_comige_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_comige_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comige.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -479,8 +479,8 @@ define i32 @test_comige_ss_0(float %a, float %b) {
 
 define i32 @test_comigt_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_comigt_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comigt.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -498,8 +498,8 @@ define i32 @test_comigt_ss_0(float %a, float %b) {
 
 define i32 @test_comile_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_comile_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comile.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -517,8 +517,8 @@ define i32 @test_comile_ss_0(float %a, float %b) {
 
 define i32 @test_comilt_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_comilt_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comilt.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -536,8 +536,8 @@ define i32 @test_comilt_ss_0(float %a, float %b) {
 
 define i32 @test_comineq_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_comineq_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.comineq.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -555,8 +555,8 @@ define i32 @test_comineq_ss_0(float %a, float %b) {
 
 define i32 @test_ucomieq_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_ucomieq_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomieq.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -574,8 +574,8 @@ define i32 @test_ucomieq_ss_0(float %a, float %b) {
 
 define i32 @test_ucomige_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_ucomige_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomige.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -593,8 +593,8 @@ define i32 @test_ucomige_ss_0(float %a, float %b) {
 
 define i32 @test_ucomigt_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_ucomigt_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomigt.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -612,8 +612,8 @@ define i32 @test_ucomigt_ss_0(float %a, float %b) {
 
 define i32 @test_ucomile_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_ucomile_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomile.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -631,8 +631,8 @@ define i32 @test_ucomile_ss_0(float %a, float %b) {
 
 define i32 @test_ucomilt_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_ucomilt_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomilt.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -650,8 +650,8 @@ define i32 @test_ucomilt_ss_0(float %a, float %b) {
 
 define i32 @test_ucomineq_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_ucomineq_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse.ucomineq.ss(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-sse2-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-sse2-inseltpoison.ll
new file mode 100644
index 0000000000000..ceab6ee12163b
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-sse2-inseltpoison.ll
@@ -0,0 +1,541 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define double @test_sqrt_sd_0(double %a) {
+; CHECK-LABEL: @test_sqrt_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = call double @llvm.sqrt.f64(double [[A:%.*]])
+; CHECK-NEXT:    ret double [[TMP1]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
+  %4 = extractelement <2 x double> %3, i32 0
+  ret double %4
+}
+
+define double @test_sqrt_sd_1(double %a) {
+; CHECK-LABEL: @test_sqrt_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %2)
+  %4 = extractelement <2 x double> %3, i32 1
+  ret double %4
+}
+
+define double @test_add_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_add_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret double [[TMP1]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define double @test_add_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_add_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+define double @test_add_sd_2(double %a) {
+; CHECK-LABEL: @test_add_sd_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd double [[A:%.*]], [[A]]
+; CHECK-NEXT:    ret double [[TMP1]]
+;
+  %1 = insertelement <2 x double> zeroinitializer, double %a, i32 0
+  %2 = tail call <2 x double> @llvm.x86.sse2.add.sd(<2 x double> %1, <2 x double> %1)
+  %3 = extractelement <2 x double> %2, i32 0
+  ret double %3
+}
+
+define double @test_sub_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_sub_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret double [[TMP1]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define double @test_sub_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_sub_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+define double @test_sub_sd_2(double %a) {
+; CHECK-LABEL: @test_sub_sd_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub double [[A:%.*]], [[A]]
+; CHECK-NEXT:    ret double [[TMP1]]
+;
+  %1 = insertelement <2 x double> zeroinitializer, double %a, i32 0
+  %2 = tail call <2 x double> @llvm.x86.sse2.sub.sd(<2 x double> %1, <2 x double> %1)
+  %3 = extractelement <2 x double> %2, i32 0
+  ret double %3
+}
+
+define double @test_mul_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_mul_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret double [[TMP1]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define double @test_mul_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_mul_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+define double @test_mul_sd_2(double %a) {
+; CHECK-LABEL: @test_mul_sd_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul double [[A:%.*]], [[A]]
+; CHECK-NEXT:    ret double [[TMP1]]
+;
+  %1 = insertelement <2 x double> zeroinitializer, double %a, i32 0
+  %2 = tail call <2 x double> @llvm.x86.sse2.mul.sd(<2 x double> %1, <2 x double> %1)
+  %3 = extractelement <2 x double> %2, i32 0
+  ret double %3
+}
+
+define double @test_div_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_div_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv double [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret double [[TMP1]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define double @test_div_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_div_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+define double @test_div_sd_2(double %a) {
+; CHECK-LABEL: @test_div_sd_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv double [[A:%.*]], [[A]]
+; CHECK-NEXT:    ret double [[TMP1]]
+;
+  %1 = insertelement <2 x double> zeroinitializer, double %a, i32 0
+  %2 = tail call <2 x double> @llvm.x86.sse2.div.sd(<2 x double> %1, <2 x double> %1)
+  %3 = extractelement <2 x double> %2, i32 0
+  ret double %3
+}
+
+define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_min_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]])
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a, <2 x double> %1)
+  ret <2 x double> %2
+}
+
+define double @test_min_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_min_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
+; CHECK-NEXT:    ret double [[TMP4]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define double @test_min_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_min_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+define double @test_min_sd_2(double %a) {
+; CHECK-LABEL: @test_min_sd_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[TMP1]], <2 x double> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
+; CHECK-NEXT:    ret double [[TMP3]]
+;
+  %1 = insertelement <2 x double> zeroinitializer, double %a, i32 0
+  %2 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %1, <2 x double> %1)
+  %3 = extractelement <2 x double> %2, i32 0
+  ret double %3
+}
+
+define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_max_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]])
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a, <2 x double> %1)
+  ret <2 x double> %2
+}
+
+define double @test_max_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_max_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
+; CHECK-NEXT:    ret double [[TMP4]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define double @test_max_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_max_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %2, <2 x double> %4)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+define double @test_max_sd_2(double %a) {
+; CHECK-LABEL: @test_max_sd_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[TMP1]], <2 x double> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
+; CHECK-NEXT:    ret double [[TMP3]]
+;
+  %1 = insertelement <2 x double> zeroinitializer, double %a, i32 0
+  %2 = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %1, <2 x double> %1)
+  %3 = extractelement <2 x double> %2, i32 0
+  ret double %3
+}
+
+define <2 x double> @test_cmp_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_cmp_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], i8 0)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a, <2 x double> %1, i8 0)
+  ret <2 x double> %2
+}
+
+define double @test_cmp_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_cmp_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]], i8 0)
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
+; CHECK-NEXT:    ret double [[TMP4]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %4, i8 0)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define double @test_cmp_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_cmp_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %2, <2 x double> %4, i8 0)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+define double @test_cmp_sd_2(double %a) {
+; CHECK-LABEL: @test_cmp_sd_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]], <2 x double> [[TMP1]], i8 3)
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
+; CHECK-NEXT:    ret double [[TMP3]]
+;
+  %1 = insertelement <2 x double> zeroinitializer, double %a, i32 0
+  %2 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %1, <2 x double> %1, i8 3)
+  %3 = extractelement <2 x double> %2, i32 0
+  ret double %3
+}
+
+define i32 @test_comieq_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_comieq_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comieq.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_comige_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_comige_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comige.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.comige.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_comigt_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_comigt_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comigt.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_comile_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_comile_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comile.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.comile.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_comilt_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_comilt_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comilt.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_comineq_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_comineq_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comineq.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_ucomieq_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_ucomieq_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_ucomige_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_ucomige_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_ucomigt_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_ucomigt_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_ucomile_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_ucomile_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_ucomilt_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_ucomilt_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+define i32 @test_ucomineq_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_ucomineq_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; CHECK-NEXT:    ret i32 [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %2, <2 x double> %4)
+  ret i32 %5
+}
+
+declare <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double>) nounwind readnone
+
+declare <2 x double> @llvm.x86.sse2.add.sd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse2.sub.sd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse2.mul.sd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>)
+declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8)
+
+declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>)
+
+declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>)
+declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>)
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-sse2.ll b/llvm/test/Transforms/InstCombine/X86/x86-sse2.ll
index ec74be9807b54..b315683f9f98a 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-sse2.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-sse2.ll
@@ -189,8 +189,8 @@ define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) {
 
 define double @test_min_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_min_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
 ; CHECK-NEXT:    ret double [[TMP4]]
@@ -219,7 +219,7 @@ define double @test_min_sd_1(double %a, double %b) {
 
 define double @test_min_sd_2(double %a) {
 ; CHECK-LABEL: @test_min_sd_2(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double undef, double 0.000000e+00>, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> [[TMP1]], <2 x double> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret double [[TMP3]]
@@ -242,8 +242,8 @@ define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) {
 
 define double @test_max_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_max_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
 ; CHECK-NEXT:    ret double [[TMP4]]
@@ -272,7 +272,7 @@ define double @test_max_sd_1(double %a, double %b) {
 
 define double @test_max_sd_2(double %a) {
 ; CHECK-LABEL: @test_max_sd_2(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double undef, double 0.000000e+00>, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> [[TMP1]], <2 x double> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret double [[TMP3]]
@@ -295,8 +295,8 @@ define <2 x double> @test_cmp_sd(<2 x double> %a, <2 x double> %b) {
 
 define double @test_cmp_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_cmp_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]], i8 0)
 ; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0
 ; CHECK-NEXT:    ret double [[TMP4]]
@@ -325,7 +325,7 @@ define double @test_cmp_sd_1(double %a, double %b) {
 
 define double @test_cmp_sd_2(double %a) {
 ; CHECK-LABEL: @test_cmp_sd_2(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double undef, double 0.000000e+00>, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> [[TMP1]], <2 x double> [[TMP1]], i8 3)
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret double [[TMP3]]
@@ -338,8 +338,8 @@ define double @test_cmp_sd_2(double %a) {
 
 define i32 @test_comieq_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_comieq_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comieq.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -353,8 +353,8 @@ define i32 @test_comieq_sd_0(double %a, double %b) {
 
 define i32 @test_comige_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_comige_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comige.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -368,8 +368,8 @@ define i32 @test_comige_sd_0(double %a, double %b) {
 
 define i32 @test_comigt_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_comigt_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comigt.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -383,8 +383,8 @@ define i32 @test_comigt_sd_0(double %a, double %b) {
 
 define i32 @test_comile_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_comile_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comile.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -398,8 +398,8 @@ define i32 @test_comile_sd_0(double %a, double %b) {
 
 define i32 @test_comilt_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_comilt_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comilt.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -413,8 +413,8 @@ define i32 @test_comilt_sd_0(double %a, double %b) {
 
 define i32 @test_comineq_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_comineq_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.comineq.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -428,8 +428,8 @@ define i32 @test_comineq_sd_0(double %a, double %b) {
 
 define i32 @test_ucomieq_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_ucomieq_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -443,8 +443,8 @@ define i32 @test_ucomieq_sd_0(double %a, double %b) {
 
 define i32 @test_ucomige_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_ucomige_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -458,8 +458,8 @@ define i32 @test_ucomige_sd_0(double %a, double %b) {
 
 define i32 @test_ucomigt_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_ucomigt_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -473,8 +473,8 @@ define i32 @test_ucomigt_sd_0(double %a, double %b) {
 
 define i32 @test_ucomile_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_ucomile_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -488,8 +488,8 @@ define i32 @test_ucomile_sd_0(double %a, double %b) {
 
 define i32 @test_ucomilt_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_ucomilt_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
@@ -503,8 +503,8 @@ define i32 @test_ucomilt_sd_0(double %a, double %b) {
 
 define i32 @test_ucomineq_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_ucomineq_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = tail call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
 ; CHECK-NEXT:    ret i32 [[TMP3]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-sse41-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-sse41-inseltpoison.ll
new file mode 100644
index 0000000000000..8c1e1ec4e2e3f
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-sse41-inseltpoison.ll
@@ -0,0 +1,124 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define <2 x double> @test_round_sd(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @test_round_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], i32 10)
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 0
+  %2 = insertelement <2 x double> %b, double 2.000000e+00, i32 1
+  %3 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %1, <2 x double> %2, i32 10)
+  ret <2 x double> %3
+}
+
+define double @test_round_sd_0(double %a, double %b) {
+; CHECK-LABEL: @test_round_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> poison, <2 x double> [[TMP1]], i32 10)
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
+; CHECK-NEXT:    ret double [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %2, <2 x double> %4, i32 10)
+  %6 = extractelement <2 x double> %5, i32 0
+  ret double %6
+}
+
+define double @test_round_sd_1(double %a, double %b) {
+; CHECK-LABEL: @test_round_sd_1(
+; CHECK-NEXT:    ret double 1.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = insertelement <2 x double> poison, double %b, i32 0
+  %4 = insertelement <2 x double> %3, double 2.000000e+00, i32 1
+  %5 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %2, <2 x double> %4, i32 10)
+  %6 = extractelement <2 x double> %5, i32 1
+  ret double %6
+}
+
+define double @test_round_sd_2(double %a) {
+; CHECK-LABEL: @test_round_sd_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> poison, <2 x double> [[TMP1]], i32 10)
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
+; CHECK-NEXT:    ret double [[TMP3]]
+;
+  %1 = insertelement <2 x double> zeroinitializer, double %a, i32 0
+  %2 = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> %1, <2 x double> %1, i32 10)
+  %3 = extractelement <2 x double> %2, i32 0
+  ret double %3
+}
+
+define <4 x float> @test_round_ss(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_round_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> <float poison, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, <4 x float> [[B:%.*]], i32 10)
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
+  %5 = insertelement <4 x float> %4, float 2.000000e+00, i32 2
+  %6 = insertelement <4 x float> %5, float 3.000000e+00, i32 3
+  %7 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %3, <4 x float> %6, i32 10)
+  ret <4 x float> %7
+}
+
+define float @test_round_ss_0(float %a, float %b) {
+; CHECK-LABEL: @test_round_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> poison, <4 x float> [[TMP1]], i32 10)
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    ret float [[R]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %4, <4 x float> %8, i32 10)
+  %r = extractelement <4 x float> %9, i32 0
+  ret float %r
+}
+
+define float @test_round_ss_2(float %a, float %b) {
+; CHECK-LABEL: @test_round_ss_2(
+; CHECK-NEXT:    ret float 2.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = insertelement <4 x float> poison, float %b, i32 0
+  %6 = insertelement <4 x float> %5, float 4.000000e+00, i32 1
+  %7 = insertelement <4 x float> %6, float 5.000000e+00, i32 2
+  %8 = insertelement <4 x float> %7, float 6.000000e+00, i32 3
+  %9 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %4, <4 x float> %8, i32 10)
+  %r = extractelement <4 x float> %9, i32 2
+  ret float %r
+}
+
+define float @test_round_ss_3(float %a) {
+; CHECK-LABEL: @test_round_ss_3(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> poison, <4 x float> [[TMP1]], i32 10)
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    ret float [[TMP3]]
+;
+  %1 = insertelement <4 x float> zeroinitializer, float %a, i32 0
+  %2 = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %1, <4 x float> %1, i32 10)
+  %3 = extractelement <4 x float> %2, i32 0
+  ret float %3
+}
+
+declare <2 x double> @llvm.x86.sse41.round.sd(<2 x double>, <2 x double>, i32) nounwind readnone
+declare <4 x float> @llvm.x86.sse41.round.ss(<4 x float>, <4 x float>, i32) nounwind readnone
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-sse41.ll b/llvm/test/Transforms/InstCombine/X86/x86-sse41.ll
index 98ed7bed0d50f..d59ce37217b24 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-sse41.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-sse41.ll
@@ -15,8 +15,8 @@ define <2 x double> @test_round_sd(<2 x double> %a, <2 x double> %b) {
 
 define double @test_round_sd_0(double %a, double %b) {
 ; CHECK-LABEL: @test_round_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[B:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> undef, <2 x double> [[TMP1]], i32 10)
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> poison, <2 x double> [[TMP1]], i32 10)
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret double [[TMP3]]
 ;
@@ -44,8 +44,8 @@ define double @test_round_sd_1(double %a, double %b) {
 
 define double @test_round_sd_2(double %a) {
 ; CHECK-LABEL: @test_round_sd_2(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> undef, <2 x double> [[TMP1]], i32 10)
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.sse41.round.sd(<2 x double> poison, <2 x double> [[TMP1]], i32 10)
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret double [[TMP3]]
 ;
@@ -57,7 +57,7 @@ define double @test_round_sd_2(double %a) {
 
 define <4 x float> @test_round_ss(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: @test_round_ss(
-; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> <float undef, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, <4 x float> [[B:%.*]], i32 10)
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> <float poison, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, <4 x float> [[B:%.*]], i32 10)
 ; CHECK-NEXT:    ret <4 x float> [[TMP1]]
 ;
   %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
@@ -72,8 +72,8 @@ define <4 x float> @test_round_ss(<4 x float> %a, <4 x float> %b) {
 
 define float @test_round_ss_0(float %a, float %b) {
 ; CHECK-LABEL: @test_round_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[B:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> undef, <4 x float> [[TMP1]], i32 10)
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> poison, <4 x float> [[TMP1]], i32 10)
 ; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret float [[R]]
 ;
@@ -109,8 +109,8 @@ define float @test_round_ss_2(float %a, float %b) {
 
 define float @test_round_ss_3(float %a) {
 ; CHECK-LABEL: @test_round_ss_3(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> undef, <4 x float> [[TMP1]], i32 10)
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> poison, <4 x float> [[TMP1]], i32 10)
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret float [[TMP3]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-sse4a.ll b/llvm/test/Transforms/InstCombine/X86/x86-sse4a.ll
index 541156c0137db..5468b9f9364a6 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-sse4a.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-sse4a.ll
@@ -25,7 +25,7 @@ define <2 x i64> @test_extrq_zero_arg0(<2 x i64> %x, <16 x i8> %y) {
 define <2 x i64> @test_extrq_zero_arg1(<2 x i64> %x, <16 x i8> %y) {
 ; CHECK-LABEL: @test_extrq_zero_arg1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[X:%.*]] to <16 x i8>
-; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
 ; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
 ;
@@ -61,7 +61,7 @@ define <2 x i64> @test_extrq_constant_undef(<2 x i64> %x, <16 x i8> %y) {
 define <2 x i64> @test_extrq_call_constexpr(<2 x i64> %x) {
 ; CHECK-LABEL: @test_extrq_call_constexpr(
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[X:%.*]] to <16 x i8>
-; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
 ; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
 ;
@@ -85,7 +85,7 @@ define <2 x i64> @test_extrqi_call(<2 x i64> %x) {
 define <2 x i64> @test_extrqi_shuffle_1zuu(<2 x i64> %x) {
 ; CHECK-LABEL: @test_extrqi_shuffle_1zuu(
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[X:%.*]] to <16 x i8>
-; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> <i8 poison, i8 poison, i8 poison, i8 poison, i8 0, i8 0, i8 0, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
 ; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
 ;
@@ -96,7 +96,7 @@ define <2 x i64> @test_extrqi_shuffle_1zuu(<2 x i64> %x) {
 define <2 x i64> @test_extrqi_shuffle_2zzzzzzzuuuuuuuu(<2 x i64> %x) {
 ; CHECK-LABEL: @test_extrqi_shuffle_2zzzzzzzuuuuuuuu(
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[X:%.*]] to <16 x i8>
-; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> <i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, <16 x i32> <i32 2, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> <i8 poison, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i32> <i32 2, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
 ; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
 ;
@@ -159,7 +159,7 @@ define <2 x i64> @test_insertq_call(<2 x i64> %x, <2 x i64> %y) {
 
 define <2 x i64> @test_insertq_to_insertqi(<2 x i64> %x, <2 x i64> %y) {
 ; CHECK-LABEL: @test_insertq_to_insertqi(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> <i64 8, i64 undef>, i8 18, i8 2)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> <i64 8, i64 poison>, i8 18, i8 2)
 ; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
 ;
   %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> <i64 8, i64 658>) nounwind
@@ -184,7 +184,7 @@ define <2 x i64> @test_insertq_constant_undef(<2 x i64> %x, <2 x i64> %y) {
 
 define <2 x i64> @test_insertq_call_constexpr(<2 x i64> %x) {
 ; CHECK-LABEL: @test_insertq_call_constexpr(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> <i64 0, i64 undef>, i8 2, i8 0)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> <i64 0, i64 poison>, i8 2, i8 0)
 ; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
 ;
   %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> bitcast (<16 x i8> trunc (<16 x i16> bitcast (<4 x i64> <i64 0, i64 undef, i64 2, i64 undef> to <16 x i16>) to <16 x i8>) to <2 x i64>))
@@ -229,7 +229,7 @@ define <2 x i64> @test_insertqi_constant(<2 x i64> %v, <2 x i64> %i) {
 
 define <2 x i64> @test_insertqi_call_constexpr(<2 x i64> %x) {
 ; CHECK-LABEL: @test_insertqi_call_constexpr(
-; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> <i64 0, i64 undef>, i8 48, i8 3)
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> <i64 0, i64 poison>, i8 48, i8 3)
 ; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
 ;
   %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> bitcast (<16 x i8> trunc (<16 x i16> bitcast (<4 x i64> <i64 0, i64 undef, i64 2, i64 undef> to <16 x i16>) to <16 x i8>) to <2 x i64>), i8 48, i8 3)
@@ -242,7 +242,7 @@ define <2 x i64> @test_insertqi_call_constexpr(<2 x i64> %x) {
 define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i) {
 ; CHECK-LABEL: @testInsert64Bits(
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[I:%.*]] to <16 x i8>
-; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
 ; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
 ;
@@ -253,7 +253,7 @@ define <2 x i64> @testInsert64Bits(<2 x i64> %v, <2 x i64> %i) {
 define <2 x i64> @testZeroLength(<2 x i64> %v, <2 x i64> %i) {
 ; CHECK-LABEL: @testZeroLength(
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[I:%.*]] to <16 x i8>
-; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>
 ; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts-inseltpoison.ll
new file mode 100644
index 0000000000000..719389470faca
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts-inseltpoison.ll
@@ -0,0 +1,110 @@
+; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define i16 @test1(float %f) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    [[TMP281:%.*]] = fadd float %f, -1.000000e+00
+; CHECK-NEXT:    [[TMP373:%.*]] = fmul float [[TMP281]], 5.000000e-01
+; CHECK-NEXT:    [[TMP374:%.*]] = insertelement <4 x float> poison, float [[TMP373]], i32 0
+; CHECK-NEXT:    [[TMP48:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP374]], <4 x float> <float 6.553500e+04, float poison, float poison, float poison>)
+; CHECK-NEXT:    [[TMP59:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP48]], <4 x float> <float 0.000000e+00, float poison, float poison, float poison>)
+; CHECK-NEXT:    [[TMP_UPGRD_1:%.*]] = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[TMP59]])
+; CHECK-NEXT:    [[TMP69:%.*]] = trunc i32 [[TMP_UPGRD_1]] to i16
+; CHECK-NEXT:    ret i16 [[TMP69]]
+;
+  %tmp = insertelement <4 x float> poison, float %f, i32 0
+  %tmp10 = insertelement <4 x float> %tmp, float 0.000000e+00, i32 1
+  %tmp11 = insertelement <4 x float> %tmp10, float 0.000000e+00, i32 2
+  %tmp12 = insertelement <4 x float> %tmp11, float 0.000000e+00, i32 3
+  %tmp28 = tail call <4 x float> @llvm.x86.sse.sub.ss( <4 x float> %tmp12, <4 x float> < float 1.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > )
+  %tmp37 = tail call <4 x float> @llvm.x86.sse.mul.ss( <4 x float> %tmp28, <4 x float> < float 5.000000e-01, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > )
+  %tmp48 = tail call <4 x float> @llvm.x86.sse.min.ss( <4 x float> %tmp37, <4 x float> < float 6.553500e+04, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00 > )
+  %tmp59 = tail call <4 x float> @llvm.x86.sse.max.ss( <4 x float> %tmp48, <4 x float> zeroinitializer )
+  %tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 )
+  %tmp69 = trunc i32 %tmp.upgrd.1 to i16
+  ret i16 %tmp69
+}
+
+define i64 @test3(float %f, double %d) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    [[V00:%.*]] = insertelement <4 x float> poison, float %f, i32 0
+; CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> [[V00]])
+; CHECK-NEXT:    [[V10:%.*]] = insertelement <4 x float> poison, float %f, i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> [[V10]])
+; CHECK-NEXT:    [[V20:%.*]] = insertelement <4 x float> poison, float %f, i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[V20]])
+; CHECK-NEXT:    [[V30:%.*]] = insertelement <4 x float> poison, float %f, i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> [[V30]])
+; CHECK-NEXT:    [[V40:%.*]] = insertelement <2 x double> poison, double %d, i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[V40]])
+; CHECK-NEXT:    [[V50:%.*]] = insertelement <2 x double> poison, double %d, i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> [[V50]])
+; CHECK-NEXT:    [[V60:%.*]] = insertelement <2 x double> poison, double %d, i32 0
+; CHECK-NEXT:    [[TMP6:%.*]] = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[V60]])
+; CHECK-NEXT:    [[V70:%.*]] = insertelement <2 x double> poison, double %d, i32 0
+; CHECK-NEXT:    [[TMP7:%.*]] = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> [[V70]])
+; CHECK-NEXT:    [[TMP8:%.*]] = add i32 [[TMP0]], [[TMP2]]
+; CHECK-NEXT:    [[TMP9:%.*]] = add i32 [[TMP4]], [[TMP6]]
+; CHECK-NEXT:    [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]]
+; CHECK-NEXT:    [[TMP11:%.*]] = sext i32 [[TMP10]] to i64
+; CHECK-NEXT:    [[TMP12:%.*]] = add i64 [[TMP1]], [[TMP3]]
+; CHECK-NEXT:    [[TMP13:%.*]] = add i64 [[TMP5]], [[TMP7]]
+; CHECK-NEXT:    [[TMP14:%.*]] = add i64 [[TMP12]], [[TMP13]]
+; CHECK-NEXT:    [[TMP15:%.*]] = add i64 [[TMP14]], [[TMP11]]
+; CHECK-NEXT:    ret i64 [[TMP15]]
+;
+  %v00 = insertelement <4 x float> poison, float %f, i32 0
+  %v01 = insertelement <4 x float> %v00, float 0.000000e+00, i32 1
+  %v02 = insertelement <4 x float> %v01, float 0.000000e+00, i32 2
+  %v03 = insertelement <4 x float> %v02, float 0.000000e+00, i32 3
+  %tmp0 = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> %v03)
+  %v10 = insertelement <4 x float> poison, float %f, i32 0
+  %v11 = insertelement <4 x float> %v10, float 0.000000e+00, i32 1
+  %v12 = insertelement <4 x float> %v11, float 0.000000e+00, i32 2
+  %v13 = insertelement <4 x float> %v12, float 0.000000e+00, i32 3
+  %tmp1 = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %v13)
+  %v20 = insertelement <4 x float> poison, float %f, i32 0
+  %v21 = insertelement <4 x float> %v20, float 0.000000e+00, i32 1
+  %v22 = insertelement <4 x float> %v21, float 0.000000e+00, i32 2
+  %v23 = insertelement <4 x float> %v22, float 0.000000e+00, i32 3
+  %tmp2 = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> %v23)
+  %v30 = insertelement <4 x float> poison, float %f, i32 0
+  %v31 = insertelement <4 x float> %v30, float 0.000000e+00, i32 1
+  %v32 = insertelement <4 x float> %v31, float 0.000000e+00, i32 2
+  %v33 = insertelement <4 x float> %v32, float 0.000000e+00, i32 3
+  %tmp3 = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %v33)
+  %v40 = insertelement <2 x double> poison, double %d, i32 0
+  %v41 = insertelement <2 x double> %v40, double 0.000000e+00, i32 1
+  %tmp4 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %v41)
+  %v50 = insertelement <2 x double> poison, double %d, i32 0
+  %v51 = insertelement <2 x double> %v50, double 0.000000e+00, i32 1
+  %tmp5 = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %v51)
+  %v60 = insertelement <2 x double> poison, double %d, i32 0
+  %v61 = insertelement <2 x double> %v60, double 0.000000e+00, i32 1
+  %tmp6 = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %v61)
+  %v70 = insertelement <2 x double> poison, double %d, i32 0
+  %v71 = insertelement <2 x double> %v70, double 0.000000e+00, i32 1
+  %tmp7 = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %v71)
+  %tmp8 = add i32 %tmp0, %tmp2
+  %tmp9 = add i32 %tmp4, %tmp6
+  %tmp10 = add i32 %tmp8, %tmp9
+  %tmp11 = sext i32 %tmp10 to i64
+  %tmp12 = add i64 %tmp1, %tmp3
+  %tmp13 = add i64 %tmp5, %tmp7
+  %tmp14 = add i64 %tmp12, %tmp13
+  %tmp15 = add i64 %tmp11, %tmp14
+  ret i64 %tmp15
+}
+
+declare <4 x float> @llvm.x86.sse.sub.ss(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.mul.ss(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.min.ss(<4 x float>, <4 x float>)
+declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>)
+declare i32 @llvm.x86.sse.cvtss2si(<4 x float>)
+declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>)
+declare i32 @llvm.x86.sse.cvttss2si(<4 x float>)
+declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>)
+declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>)
+declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>)
+declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>)
+declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>)
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts.ll b/llvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts.ll
index c0add457e1e39..1ecf3bca08147 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-vec_demanded_elts.ll
@@ -1,13 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 
 define i16 @test1(float %f) {
 ; CHECK-LABEL: @test1(
-; CHECK-NEXT:    [[TMP281:%.*]] = fadd float %f, -1.000000e+00
-; CHECK-NEXT:    [[TMP373:%.*]] = fmul float [[TMP281]], 5.000000e-01
-; CHECK-NEXT:    [[TMP374:%.*]] = insertelement <4 x float> undef, float [[TMP373]], i32 0
-; CHECK-NEXT:    [[TMP48:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP374]], <4 x float> <float 6.553500e+04, float undef, float undef, float undef>)
-; CHECK-NEXT:    [[TMP59:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP48]], <4 x float> <float 0.000000e+00, float undef, float undef, float undef>)
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd float [[F:%.*]], -1.000000e+00
+; CHECK-NEXT:    [[TMP2:%.*]] = fmul float [[TMP1]], 5.000000e-01
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP48:%.*]] = tail call <4 x float> @llvm.x86.sse.min.ss(<4 x float> [[TMP3]], <4 x float> <float 6.553500e+04, float poison, float poison, float poison>)
+; CHECK-NEXT:    [[TMP59:%.*]] = tail call <4 x float> @llvm.x86.sse.max.ss(<4 x float> [[TMP48]], <4 x float> <float 0.000000e+00, float poison, float poison, float poison>)
 ; CHECK-NEXT:    [[TMP_UPGRD_1:%.*]] = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[TMP59]])
 ; CHECK-NEXT:    [[TMP69:%.*]] = trunc i32 [[TMP_UPGRD_1]] to i16
 ; CHECK-NEXT:    ret i16 [[TMP69]]
@@ -27,22 +28,22 @@ define i16 @test1(float %f) {
 
 define i64 @test3(float %f, double %d) {
 ; CHECK-LABEL: @test3(
-; CHECK-NEXT:    [[V00:%.*]] = insertelement <4 x float> undef, float %f, i32 0
-; CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> [[V00]])
-; CHECK-NEXT:    [[V10:%.*]] = insertelement <4 x float> undef, float %f, i32 0
-; CHECK-NEXT:    [[TMP1:%.*]] = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> [[V10]])
-; CHECK-NEXT:    [[V20:%.*]] = insertelement <4 x float> undef, float %f, i32 0
-; CHECK-NEXT:    [[TMP2:%.*]] = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[V20]])
-; CHECK-NEXT:    [[V30:%.*]] = insertelement <4 x float> undef, float %f, i32 0
-; CHECK-NEXT:    [[TMP3:%.*]] = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> [[V30]])
-; CHECK-NEXT:    [[V40:%.*]] = insertelement <2 x double> undef, double %d, i32 0
-; CHECK-NEXT:    [[TMP4:%.*]] = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[V40]])
-; CHECK-NEXT:    [[V50:%.*]] = insertelement <2 x double> undef, double %d, i32 0
-; CHECK-NEXT:    [[TMP5:%.*]] = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> [[V50]])
-; CHECK-NEXT:    [[V60:%.*]] = insertelement <2 x double> undef, double %d, i32 0
-; CHECK-NEXT:    [[TMP6:%.*]] = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[V60]])
-; CHECK-NEXT:    [[V70:%.*]] = insertelement <2 x double> undef, double %d, i32 0
-; CHECK-NEXT:    [[TMP7:%.*]] = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> [[V70]])
+; CHECK-NEXT:    [[V03:%.*]] = insertelement <4 x float> poison, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[TMP0:%.*]] = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> [[V03]])
+; CHECK-NEXT:    [[V13:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> [[V13]])
+; CHECK-NEXT:    [[V23:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> [[V23]])
+; CHECK-NEXT:    [[V33:%.*]] = insertelement <4 x float> poison, float [[F]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> [[V33]])
+; CHECK-NEXT:    [[V41:%.*]] = insertelement <2 x double> poison, double [[D:%.*]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> [[V41]])
+; CHECK-NEXT:    [[V51:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> [[V51]])
+; CHECK-NEXT:    [[V61:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
+; CHECK-NEXT:    [[TMP6:%.*]] = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> [[V61]])
+; CHECK-NEXT:    [[V71:%.*]] = insertelement <2 x double> poison, double [[D]], i32 0
+; CHECK-NEXT:    [[TMP7:%.*]] = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> [[V71]])
 ; CHECK-NEXT:    [[TMP8:%.*]] = add i32 [[TMP0]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP9:%.*]] = add i32 [[TMP4]], [[TMP6]]
 ; CHECK-NEXT:    [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]]
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
new file mode 100644
index 0000000000000..e23e222748c20
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll
@@ -0,0 +1,3783 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+;
+; ASHR - Immediate
+;
+
+define <8 x i16> @sse2_psrai_w_0(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrai_w_0(
+; CHECK-NEXT:    ret <8 x i16> [[V:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 0)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psrai_w_15(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrai_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 15)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psrai_w_64(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrai_w_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 64)
+  ret <8 x i16> %1
+}
+
+define <4 x i32> @sse2_psrai_d_0(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrai_d_0(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 0)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psrai_d_15(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrai_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 15)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psrai_d_64(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrai_d_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %v, i32 64)
+  ret <4 x i32> %1
+}
+
+define <16 x i16> @avx2_psrai_w_0(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrai_w_0(
+; CHECK-NEXT:    ret <16 x i16> [[V:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %v, i32 0)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psrai_w_15(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrai_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %v, i32 15)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psrai_w_64(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrai_w_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %v, i32 64)
+  ret <16 x i16> %1
+}
+
+define <8 x i32> @avx2_psrai_d_0(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrai_d_0(
+; CHECK-NEXT:    ret <8 x i32> [[V:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %v, i32 0)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psrai_d_15(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrai_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %v, i32 15)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psrai_d_64(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrai_d_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %v, i32 64)
+  ret <8 x i32> %1
+}
+
+define <2 x i64> @avx512_psrai_q_128_0(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psrai_q_128_0(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> %v, i32 0)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @avx512_psrai_q_128_15(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psrai_q_128_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 15, i64 15>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> %v, i32 15)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @avx512_psrai_q_128_64(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psrai_q_128_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 63, i64 63>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64> %v, i32 64)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx512_psrai_q_256_0(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psrai_q_256_0(
+; CHECK-NEXT:    ret <4 x i64> [[V:%.*]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> %v, i32 0)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx512_psrai_q_256_15(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psrai_q_256_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> %v, i32 15)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx512_psrai_q_256_64(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psrai_q_256_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 63, i64 63, i64 63, i64 63>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64> %v, i32 64)
+  ret <4 x i64> %1
+}
+
+define <32 x i16> @avx512_psrai_w_512_0(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrai_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[V:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrai.w.512(<32 x i16> %v, i32 0)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrai_w_512_15(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrai_w_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrai.w.512(<32 x i16> %v, i32 15)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrai_w_512_64(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrai_w_512_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrai.w.512(<32 x i16> %v, i32 64)
+  ret <32 x i16> %1
+}
+
+define <16 x i32> @avx512_psrai_d_512_0(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrai_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[V:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %v, i32 0)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrai_d_512_15(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrai_d_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %v, i32 15)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrai_d_512_64(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrai_d_512_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %v, i32 64)
+  ret <16 x i32> %1
+}
+
+define <8 x i64> @avx512_psrai_q_512_0(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrai_q_512_0(
+; CHECK-NEXT:    ret <8 x i64> [[V:%.*]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> %v, i32 0)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrai_q_512_15(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrai_q_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> %v, i32 15)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrai_q_512_64(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrai_q_512_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> %v, i32 64)
+  ret <8 x i64> %1
+}
+
+;
+; LSHR - Immediate
+;
+
+define <8 x i16> @sse2_psrli_w_0(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrli_w_0(
+; CHECK-NEXT:    ret <8 x i16> [[V:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 0)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psrli_w_15(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrli_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 15)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psrli_w_64(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrli_w_64(
+; CHECK-NEXT:    ret <8 x i16> zeroinitializer
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %v, i32 64)
+  ret <8 x i16> %1
+}
+
+define <4 x i32> @sse2_psrli_d_0(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrli_d_0(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 0)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psrli_d_15(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrli_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 15)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psrli_d_64(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrli_d_64(
+; CHECK-NEXT:    ret <4 x i32> zeroinitializer
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 64)
+  ret <4 x i32> %1
+}
+
+define <2 x i64> @sse2_psrli_q_0(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_psrli_q_0(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %v, i32 0)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @sse2_psrli_q_15(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_psrli_q_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i64> [[V:%.*]], <i64 15, i64 15>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %v, i32 15)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @sse2_psrli_q_64(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_psrli_q_64(
+; CHECK-NEXT:    ret <2 x i64> zeroinitializer
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %v, i32 64)
+  ret <2 x i64> %1
+}
+
+define <16 x i16> @avx2_psrli_w_0(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrli_w_0(
+; CHECK-NEXT:    ret <16 x i16> [[V:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %v, i32 0)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psrli_w_15(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrli_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %v, i32 15)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psrli_w_64(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrli_w_64(
+; CHECK-NEXT:    ret <16 x i16> zeroinitializer
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %v, i32 64)
+  ret <16 x i16> %1
+}
+
+define <8 x i32> @avx2_psrli_d_0(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrli_d_0(
+; CHECK-NEXT:    ret <8 x i32> [[V:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %v, i32 0)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psrli_d_15(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrli_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %v, i32 15)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psrli_d_64(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrli_d_64(
+; CHECK-NEXT:    ret <8 x i32> zeroinitializer
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %v, i32 64)
+  ret <8 x i32> %1
+}
+
+define <4 x i64> @avx2_psrli_q_0(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrli_q_0(
+; CHECK-NEXT:    ret <4 x i64> [[V:%.*]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %v, i32 0)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx2_psrli_q_15(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrli_q_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %v, i32 15)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx2_psrli_q_64(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrli_q_64(
+; CHECK-NEXT:    ret <4 x i64> zeroinitializer
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %v, i32 64)
+  ret <4 x i64> %1
+}
+
+define <32 x i16> @avx512_psrli_w_512_0(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrli_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[V:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrli.w.512(<32 x i16> %v, i32 0)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrli_w_512_15(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrli_w_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrli.w.512(<32 x i16> %v, i32 15)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrli_w_512_64(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrli_w_512_64(
+; CHECK-NEXT:    ret <32 x i16> zeroinitializer
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrli.w.512(<32 x i16> %v, i32 64)
+  ret <32 x i16> %1
+}
+
+define <16 x i32> @avx512_psrli_d_512_0(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrli_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[V:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> %v, i32 0)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrli_d_512_15(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrli_d_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> %v, i32 15)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrli_d_512_64(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrli_d_512_64(
+; CHECK-NEXT:    ret <16 x i32> zeroinitializer
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32> %v, i32 64)
+  ret <16 x i32> %1
+}
+
+define <8 x i64> @avx512_psrli_q_512_0(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrli_q_512_0(
+; CHECK-NEXT:    ret <8 x i64> [[V:%.*]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> %v, i32 0)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrli_q_512_15(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrli_q_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> %v, i32 15)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrli_q_512_64(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrli_q_512_64(
+; CHECK-NEXT:    ret <8 x i64> zeroinitializer
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64> %v, i32 64)
+  ret <8 x i64> %1
+}
+
+;
+; SHL - Immediate
+;
+
+define <8 x i16> @sse2_pslli_w_0(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_pslli_w_0(
+; CHECK-NEXT:    ret <8 x i16> [[V:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %v, i32 0)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_pslli_w_15(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_pslli_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %v, i32 15)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_pslli_w_64(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_pslli_w_64(
+; CHECK-NEXT:    ret <8 x i16> zeroinitializer
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %v, i32 64)
+  ret <8 x i16> %1
+}
+
+define <4 x i32> @sse2_pslli_d_0(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_pslli_d_0(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %v, i32 0)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_pslli_d_15(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_pslli_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <4 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %v, i32 15)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_pslli_d_64(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_pslli_d_64(
+; CHECK-NEXT:    ret <4 x i32> zeroinitializer
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %v, i32 64)
+  ret <4 x i32> %1
+}
+
+define <2 x i64> @sse2_pslli_q_0(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_pslli_q_0(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %v, i32 0)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @sse2_pslli_q_15(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_pslli_q_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i64> [[V:%.*]], <i64 15, i64 15>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %v, i32 15)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @sse2_pslli_q_64(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_pslli_q_64(
+; CHECK-NEXT:    ret <2 x i64> zeroinitializer
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %v, i32 64)
+  ret <2 x i64> %1
+}
+
+define <16 x i16> @avx2_pslli_w_0(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_pslli_w_0(
+; CHECK-NEXT:    ret <16 x i16> [[V:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %v, i32 0)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_pslli_w_15(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_pslli_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %v, i32 15)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_pslli_w_64(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_pslli_w_64(
+; CHECK-NEXT:    ret <16 x i16> zeroinitializer
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %v, i32 64)
+  ret <16 x i16> %1
+}
+
+define <8 x i32> @avx2_pslli_d_0(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_pslli_d_0(
+; CHECK-NEXT:    ret <8 x i32> [[V:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %v, i32 0)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_pslli_d_15(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_pslli_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %v, i32 15)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_pslli_d_64(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_pslli_d_64(
+; CHECK-NEXT:    ret <8 x i32> zeroinitializer
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %v, i32 64)
+  ret <8 x i32> %1
+}
+
+define <4 x i64> @avx2_pslli_q_0(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_pslli_q_0(
+; CHECK-NEXT:    ret <4 x i64> [[V:%.*]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %v, i32 0)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx2_pslli_q_15(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_pslli_q_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <4 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %v, i32 15)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx2_pslli_q_64(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_pslli_q_64(
+; CHECK-NEXT:    ret <4 x i64> zeroinitializer
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %v, i32 64)
+  ret <4 x i64> %1
+}
+
+define <32 x i16> @avx512_pslli_w_512_0(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_pslli_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[V:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.pslli.w.512(<32 x i16> %v, i32 0)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_pslli_w_512_15(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_pslli_w_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.pslli.w.512(<32 x i16> %v, i32 15)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_pslli_w_512_64(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_pslli_w_512_64(
+; CHECK-NEXT:    ret <32 x i16> zeroinitializer
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.pslli.w.512(<32 x i16> %v, i32 64)
+  ret <32 x i16> %1
+}
+
+define <16 x i32> @avx512_pslli_d_512_0(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_pslli_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[V:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> %v, i32 0)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_pslli_d_512_15(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_pslli_d_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <16 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> %v, i32 15)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_pslli_d_512_64(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_pslli_d_512_64(
+; CHECK-NEXT:    ret <16 x i32> zeroinitializer
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> %v, i32 64)
+  ret <16 x i32> %1
+}
+
+define <8 x i64> @avx512_pslli_q_512_0(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_pslli_q_512_0(
+; CHECK-NEXT:    ret <8 x i64> [[V:%.*]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> %v, i32 0)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_pslli_q_512_15(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_pslli_q_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> %v, i32 15)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_pslli_q_512_64(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_pslli_q_512_64(
+; CHECK-NEXT:    ret <8 x i64> zeroinitializer
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64> %v, i32 64)
+  ret <8 x i64> %1
+}
+
+;
+; ASHR - Constant Vector
+;
+
+define <8 x i16> @sse2_psra_w_0(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psra_w_0(
+; CHECK-NEXT:    ret <8 x i16> [[V:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> zeroinitializer)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psra_w_15(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psra_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psra_w_15_splat(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psra_w_15_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psra_w_64(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psra_w_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <8 x i16> %1
+}
+
+define <4 x i32> @sse2_psra_d_0(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psra_d_0(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> zeroinitializer)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psra_d_15(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psra_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psra_d_15_splat(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psra_d_15_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psra_d_64(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psra_d_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
+  ret <4 x i32> %1
+}
+
+define <16 x i16> @avx2_psra_w_0(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psra_w_0(
+; CHECK-NEXT:    ret <16 x i16> [[V:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> zeroinitializer)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psra_w_15(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psra_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psra_w_15_splat(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psra_w_15_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psra_w_64(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psra_w_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <16 x i16> %1
+}
+
+define <8 x i32> @avx2_psra_d_0(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psra_d_0(
+; CHECK-NEXT:    ret <8 x i32> [[V:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> zeroinitializer)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psra_d_15(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psra_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psra_d_15_splat(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psra_d_15_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psra_d_64(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psra_d_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
+  ret <8 x i32> %1
+}
+
+define <2 x i64> @avx512_psra_q_128_0(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psra_q_128_0(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> %v, <2 x i64> zeroinitializer)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @avx512_psra_q_128_15(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psra_q_128_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 15, i64 15>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> %v, <2 x i64> <i64 15, i64 9999>)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @avx512_psra_q_128_64(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psra_q_128_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 63, i64 63>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> %v, <2 x i64> <i64 64, i64 9999>)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx512_psra_q_256_0(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psra_q_256_0(
+; CHECK-NEXT:    ret <4 x i64> [[V:%.*]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> %v, <2 x i64> zeroinitializer)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx512_psra_q_256_15(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psra_q_256_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> %v, <2 x i64> <i64 15, i64 9999>)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx512_psra_q_256_64(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psra_q_256_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 63, i64 63, i64 63, i64 63>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> %v, <2 x i64> <i64 64, i64 9999>)
+  ret <4 x i64> %1
+}
+
+define <32 x i16> @avx512_psra_w_512_0(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psra_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[V:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psra.w.512(<32 x i16> %v, <8 x i16> zeroinitializer)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psra_w_512_15(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psra_w_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psra.w.512(<32 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psra_w_512_15_splat(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psra_w_512_15_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psra.w.512(<32 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psra_w_512_64(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psra_w_512_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psra.w.512(<32 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <32 x i16> %1
+}
+
+define <16 x i32> @avx512_psra_d_512_0(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psra_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[V:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %v, <4 x i32> zeroinitializer)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psra_d_512_15(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psra_d_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psra_d_512_15_splat(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psra_d_512_15_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psra_d_512_64(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psra_d_512_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
+  ret <16 x i32> %1
+}
+
+define <8 x i64> @avx512_psra_q_512_0(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psra_q_512_0(
+; CHECK-NEXT:    ret <8 x i64> [[V:%.*]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> %v, <2 x i64> zeroinitializer)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psra_q_512_15(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psra_q_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> %v, <2 x i64> <i64 15, i64 9999>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psra_q_512_64(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psra_q_512_64(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> %v, <2 x i64> <i64 64, i64 9999>)
+  ret <8 x i64> %1
+}
+
+;
+; LSHR - Constant Vector
+;
+
+define <8 x i16> @sse2_psrl_w_0(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrl_w_0(
+; CHECK-NEXT:    ret <8 x i16> [[V:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> zeroinitializer)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psrl_w_15(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrl_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psrl_w_15_splat(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrl_w_15_splat(
+; CHECK-NEXT:    ret <8 x i16> zeroinitializer
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psrl_w_64(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psrl_w_64(
+; CHECK-NEXT:    ret <8 x i16> zeroinitializer
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <8 x i16> %1
+}
+
+define <4 x i32> @sse2_psrl_d_0(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrl_d_0(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> zeroinitializer)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psrl_d_15(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrl_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psrl_d_15_splat(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrl_d_15_splat(
+; CHECK-NEXT:    ret <4 x i32> zeroinitializer
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psrl_d_64(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psrl_d_64(
+; CHECK-NEXT:    ret <4 x i32> zeroinitializer
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
+  ret <4 x i32> %1
+}
+
+define <2 x i64> @sse2_psrl_q_0(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_psrl_q_0(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> zeroinitializer)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @sse2_psrl_q_15(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_psrl_q_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i64> [[V:%.*]], <i64 15, i64 15>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> <i64 15, i64 9999>)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @sse2_psrl_q_64(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_psrl_q_64(
+; CHECK-NEXT:    ret <2 x i64> zeroinitializer
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> <i64 64, i64 9999>)
+  ret <2 x i64> %1
+}
+
+define <16 x i16> @avx2_psrl_w_0(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrl_w_0(
+; CHECK-NEXT:    ret <16 x i16> [[V:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> zeroinitializer)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psrl_w_15(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrl_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psrl_w_15_splat(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrl_w_15_splat(
+; CHECK-NEXT:    ret <16 x i16> zeroinitializer
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psrl_w_64(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psrl_w_64(
+; CHECK-NEXT:    ret <16 x i16> zeroinitializer
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <16 x i16> %1
+}
+
+define <8 x i32> @avx2_psrl_d_0(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrl_d_0(
+; CHECK-NEXT:    ret <8 x i32> [[V:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> zeroinitializer)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psrl_d_15(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrl_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psrl_d_15_splat(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrl_d_15_splat(
+; CHECK-NEXT:    ret <8 x i32> zeroinitializer
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psrl_d_64(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrl_d_64(
+; CHECK-NEXT:    ret <8 x i32> zeroinitializer
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
+  ret <8 x i32> %1
+}
+
+define <4 x i64> @avx2_psrl_q_0(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrl_q_0(
+; CHECK-NEXT:    ret <4 x i64> [[V:%.*]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> zeroinitializer)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx2_psrl_q_15(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrl_q_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> <i64 15, i64 9999>)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx2_psrl_q_64(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrl_q_64(
+; CHECK-NEXT:    ret <4 x i64> zeroinitializer
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> <i64 64, i64 9999>)
+  ret <4 x i64> %1
+}
+
+define <32 x i16> @avx512_psrl_w_512_0(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrl_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[V:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> %v, <8 x i16> zeroinitializer)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrl_w_512_15(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrl_w_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrl_w_512_15_splat(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrl_w_512_15_splat(
+; CHECK-NEXT:    ret <32 x i16> zeroinitializer
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrl_w_512_64(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrl_w_512_64(
+; CHECK-NEXT:    ret <32 x i16> zeroinitializer
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <32 x i16> %1
+}
+
+define <16 x i32> @avx512_psrl_d_512_0(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrl_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[V:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> %v, <4 x i32> zeroinitializer)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrl_d_512_15(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrl_d_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrl_d_512_15_splat(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrl_d_512_15_splat(
+; CHECK-NEXT:    ret <16 x i32> zeroinitializer
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrl_d_512_64(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrl_d_512_64(
+; CHECK-NEXT:    ret <16 x i32> zeroinitializer
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
+  ret <16 x i32> %1
+}
+
+define <8 x i64> @avx512_psrl_q_512_0(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrl_q_512_0(
+; CHECK-NEXT:    ret <8 x i64> [[V:%.*]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> %v, <2 x i64> zeroinitializer)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrl_q_512_15(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrl_q_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> %v, <2 x i64> <i64 15, i64 9999>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrl_q_512_64(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrl_q_512_64(
+; CHECK-NEXT:    ret <8 x i64> zeroinitializer
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> %v, <2 x i64> <i64 64, i64 9999>)
+  ret <8 x i64> %1
+}
+
+;
+; SHL - Constant Vector
+;
+
+define <8 x i16> @sse2_psll_w_0(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psll_w_0(
+; CHECK-NEXT:    ret <8 x i16> [[V:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> zeroinitializer)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psll_w_15(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psll_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psll_w_15_splat(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psll_w_15_splat(
+; CHECK-NEXT:    ret <8 x i16> zeroinitializer
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @sse2_psll_w_64(<8 x i16> %v) {
+; CHECK-LABEL: @sse2_psll_w_64(
+; CHECK-NEXT:    ret <8 x i16> zeroinitializer
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <8 x i16> %1
+}
+
+define <4 x i32> @sse2_psll_d_0(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psll_d_0(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> zeroinitializer)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psll_d_15(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psll_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <4 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psll_d_15_splat(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psll_d_15_splat(
+; CHECK-NEXT:    ret <4 x i32> zeroinitializer
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @sse2_psll_d_64(<4 x i32> %v) {
+; CHECK-LABEL: @sse2_psll_d_64(
+; CHECK-NEXT:    ret <4 x i32> zeroinitializer
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
+  ret <4 x i32> %1
+}
+
+define <2 x i64> @sse2_psll_q_0(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_psll_q_0(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> zeroinitializer)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @sse2_psll_q_15(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_psll_q_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i64> [[V:%.*]], <i64 15, i64 15>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> <i64 15, i64 9999>)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @sse2_psll_q_64(<2 x i64> %v) {
+; CHECK-LABEL: @sse2_psll_q_64(
+; CHECK-NEXT:    ret <2 x i64> zeroinitializer
+;
+  %1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> <i64 64, i64 9999>)
+  ret <2 x i64> %1
+}
+
+define <16 x i16> @avx2_psll_w_0(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psll_w_0(
+; CHECK-NEXT:    ret <16 x i16> [[V:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> zeroinitializer)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psll_w_15(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psll_w_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psll_w_15_splat(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psll_w_15_splat(
+; CHECK-NEXT:    ret <16 x i16> zeroinitializer
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx2_psll_w_64(<16 x i16> %v) {
+; CHECK-LABEL: @avx2_psll_w_64(
+; CHECK-NEXT:    ret <16 x i16> zeroinitializer
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <16 x i16> %1
+}
+
+define <8 x i32> @avx2_psll_d_0(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psll_d_0(
+; CHECK-NEXT:    ret <8 x i32> [[V:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> zeroinitializer)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psll_d_15(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psll_d_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psll_d_15_splat(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psll_d_15_splat(
+; CHECK-NEXT:    ret <8 x i32> zeroinitializer
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+  ret <8 x i32> %1
+}
+
+define <8 x i32> @avx2_psll_d_64(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psll_d_64(
+; CHECK-NEXT:    ret <8 x i32> zeroinitializer
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
+  ret <8 x i32> %1
+}
+
+define <4 x i64> @avx2_psll_q_0(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psll_q_0(
+; CHECK-NEXT:    ret <4 x i64> [[V:%.*]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> zeroinitializer)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx2_psll_q_15(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psll_q_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <4 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> <i64 15, i64 9999>)
+  ret <4 x i64> %1
+}
+
+define <4 x i64> @avx2_psll_q_64(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psll_q_64(
+; CHECK-NEXT:    ret <4 x i64> zeroinitializer
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> <i64 64, i64 9999>)
+  ret <4 x i64> %1
+}
+
+define <32 x i16> @avx512_psll_w_512_0(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psll_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[V:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psll.w.512(<32 x i16> %v, <8 x i16> zeroinitializer)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psll_w_512_15(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psll_w_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psll.w.512(<32 x i16> %v, <8 x i16> <i16 15, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psll_w_15_512_splat(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psll_w_15_512_splat(
+; CHECK-NEXT:    ret <32 x i16> zeroinitializer
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psll.w.512(<32 x i16> %v, <8 x i16> <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psll_w_512_64(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psll_w_512_64(
+; CHECK-NEXT:    ret <32 x i16> zeroinitializer
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psll.w.512(<32 x i16> %v, <8 x i16> <i16 64, i16 0, i16 0, i16 0, i16 9999, i16 9999, i16 9999, i16 9999>)
+  ret <32 x i16> %1
+}
+
+define <16 x i32> @avx512_psll_d_512_0(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psll_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[V:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> %v, <4 x i32> zeroinitializer)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psll_d_512_15(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psll_d_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <16 x i32> [[V:%.*]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> %v, <4 x i32> <i32 15, i32 0, i32 9999, i32 9999>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psll_d_512_15_splat(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psll_d_512_15_splat(
+; CHECK-NEXT:    ret <16 x i32> zeroinitializer
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psll_d_512_64(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psll_d_512_64(
+; CHECK-NEXT:    ret <16 x i32> zeroinitializer
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> %v, <4 x i32> <i32 64, i32 0, i32 9999, i32 9999>)
+  ret <16 x i32> %1
+}
+
+define <8 x i64> @avx512_psll_q_512_0(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psll_q_512_0(
+; CHECK-NEXT:    ret <8 x i64> [[V:%.*]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> %v, <2 x i64> zeroinitializer)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psll_q_512_15(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psll_q_512_15(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i64> [[V:%.*]], <i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15, i64 15>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> %v, <2 x i64> <i64 15, i64 9999>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psll_q_512_64(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psll_q_512_64(
+; CHECK-NEXT:    ret <8 x i64> zeroinitializer
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> %v, <2 x i64> <i64 64, i64 9999>)
+  ret <8 x i64> %1
+}
+
+;
+; ASHR - Constant Per-Element Vector
+;
+
+define <4 x i32> @avx2_psrav_d_128_0(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psrav_d_128_0(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> zeroinitializer)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psrav_d_256_0(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrav_d_256_0(
+; CHECK-NEXT:    ret <8 x i32> [[V:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> zeroinitializer)
+  ret <8 x i32> %1
+}
+
+define <16 x i32> @avx512_psrav_d_512_0(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrav_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[V:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %v, <16 x i32> zeroinitializer)
+  ret <16 x i32> %1
+}
+
+define <4 x i32> @avx2_psrav_d_128_var(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psrav_d_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> [[V:%.*]], <i32 0, i32 8, i32 16, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 64>)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psrav_d_256_var(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrav_d_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[V:%.*]], <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>)
+  ret <8 x i32> %1
+}
+
+define <16 x i32> @avx512_psrav_d_512_var(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrav_d_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i32> [[V:%.*]], <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>)
+  ret <16 x i32> %1
+}
+
+define <4 x i32> @avx2_psrav_d_128_allbig(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psrav_d_128_allbig(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> [[V:%.*]], <i32 31, i32 31, i32 31, i32 undef>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> <i32 32, i32 100, i32 -255, i32 undef>)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psrav_d_256_allbig(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrav_d_256_allbig(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[V:%.*]], <i32 undef, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
+  ret <8 x i32> %1
+}
+
+define <16 x i32> @avx512_psrav_d_512_allbig(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrav_d_512_allbig(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i32> [[V:%.*]], <i32 undef, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 undef, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %v, <16 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555, i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
+  ret <16 x i32> %1
+}
+
+define <4 x i32> @avx2_psrav_d_128_undef(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psrav_d_128_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i32> [[V:%.*]], <i32 undef, i32 8, i32 16, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 64>, i32 undef, i32 0
+  %2 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <8 x i32> @avx2_psrav_d_256_undef(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrav_d_256_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>, i32 undef, i32 1
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <16 x i32> @avx512_psrav_d_512_undef(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrav_d_512_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 32, i32 24, i32 8, i32 0>, i32 undef, i32 1
+  %2 = tail call <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32> %v, <16 x i32> %1)
+  ret <16 x i32> %2
+}
+
+define <2 x i64> @avx512_psrav_q_128_0(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_128_0(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %v, <2 x i64> zeroinitializer)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx512_psrav_q_256_0(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_256_0(
+; CHECK-NEXT:    ret <4 x i64> [[V:%.*]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %v, <4 x i64> zeroinitializer)
+  ret <4 x i64> %1
+}
+
+define <2 x i64> @avx512_psrav_q_128_var(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 0, i64 8>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %v, <2 x i64> <i64 0, i64 8>)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx512_psrav_q_256_var(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 31>)
+  ret <4 x i64> %1
+}
+
+define <2 x i64> @avx512_psrav_q_128_allbig(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_128_allbig(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 63, i64 undef>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %v, <2 x i64> <i64 64, i64 undef>)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx512_psrav_q_256_allbig(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_256_allbig(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 63, i64 undef, i64 63, i64 63>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %v, <4 x i64> <i64 64, i64 undef, i64 -128, i64 -60>)
+  ret <4 x i64> %1
+}
+
+define <2 x i64> @avx512_psrav_q_128_undef(<2 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_128_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 undef, i64 8>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = insertelement <2 x i64> <i64 0, i64 8>, i64 undef, i64 0
+  %2 = tail call <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64> %v, <2 x i64> %1)
+  ret <2 x i64> %2
+}
+
+define <4 x i64> @avx512_psrav_q_256_undef(<4 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_256_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
+  %2 = tail call <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64> %v, <4 x i64> %1)
+  ret <4 x i64> %2
+}
+
+define <8 x i64> @avx512_psrav_q_512_0(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_512_0(
+; CHECK-NEXT:    ret <8 x i64> [[V:%.*]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %v, <8 x i64> zeroinitializer)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrav_q_512_var(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrav_q_512_allbig(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_512_allbig(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 63, i64 undef, i64 63, i64 63, i64 63, i64 undef, i64 63, i64 63>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %v, <8 x i64> <i64 64, i64 undef, i64 -128, i64 -60, i64 64, i64 undef, i64 -128, i64 -60>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrav_q_512_undef(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrav_q_512_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64> %v, <8 x i64> %1)
+  ret <8 x i64> %2
+}
+
+define <8 x i16> @avx512_psrav_w_128_0(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_128_0(
+; CHECK-NEXT:    ret <8 x i16> [[V:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psrav.w.128(<8 x i16> %v, <8 x i16> zeroinitializer)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psrav_w_128_var(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psrav.w.128(<8 x i16> %v, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psrav_w_128_allbig(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_128_allbig(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 undef>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psrav.w.128(<8 x i16> %v, <8 x i16> <i16 20, i16 -1, i16 -2, i16 33, i16 44, i16 55, i16 66, i16 undef>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psrav_w_128_undef(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_128_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = insertelement <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 undef, i64 0
+  %2 = tail call <8 x i16> @llvm.x86.avx512.psrav.w.128(<8 x i16> %v, <8 x i16> %1)
+  ret <8 x i16> %2
+}
+
+define <16 x i16> @avx512_psrav_w_256_0(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_256_0(
+; CHECK-NEXT:    ret <16 x i16> [[V:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psrav.w.256(<16 x i16> %v, <16 x i16> zeroinitializer)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psrav_w_256_var(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psrav.w.256(<16 x i16> %v, <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psrav_w_256_allbig(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_256_allbig(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 undef, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psrav.w.256(<16 x i16> %v, <16 x i16> <i16 20, i16 -1, i16 -2, i16 33, i16 44, i16 55, i16 66, i16 -7, i16 undef, i16 64, i16 -10, i16 256, i16 16, i16 28, i16 65535, i16 32767>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psrav_w_256_undef(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_256_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = insertelement <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, i16 undef, i64 0
+  %2 = tail call <16 x i16> @llvm.x86.avx512.psrav.w.256(<16 x i16> %v, <16 x i16> %1)
+  ret <16 x i16> %2
+}
+
+define <32 x i16> @avx512_psrav_w_512_0(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[V:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16> %v, <32 x i16> zeroinitializer)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrav_w_512_var(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16> %v, <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrav_w_512_allbig(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_512_allbig(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 undef, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 undef, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 undef, i16 15, i16 15, i16 undef, i16 15, i16 15>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16> %v, <32 x i16> <i16 20, i16 -1, i16 -2, i16 33, i16 44, i16 55, i16 66, i16 -7, i16 undef, i16 64, i16 -10, i16 128, i16 16, i16 28, i16 65535, i16 32767, i16 56, i16 -14, i16 undef, i16 16, i16 67, i16 567, i16 -32768, i16 4096, i16 8192, i16 -12345, i16 undef, i16 345, i16 123, i16 undef, i16 1024, i16 54321>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrav_w_512_undef(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrav_w_512_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = insertelement <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 undef, i64 0
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16> %v, <32 x i16> %1)
+  ret <32 x i16> %2
+}
+
+;
+; LSHR - Constant Per-Element Vector
+;
+
+define <4 x i32> @avx2_psrlv_d_128_0(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_128_0(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> zeroinitializer)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psrlv_d_256_0(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_256_0(
+; CHECK-NEXT:    ret <8 x i32> [[V:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> zeroinitializer)
+  ret <8 x i32> %1
+}
+
+define <4 x i32> @avx2_psrlv_d_128_var(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> [[V:%.*]], <i32 0, i32 8, i32 16, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 31>)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psrlv_d_256_var(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i32> [[V:%.*]], <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
+  ret <8 x i32> %1
+}
+
+define <4 x i32> @avx2_psrlv_d_128_big(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_128_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> [[V:%.*]], <4 x i32> <i32 0, i32 8, i32 16, i32 64>)
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 64>)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psrlv_d_256_big(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_256_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> [[V:%.*]], <8 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
+  ret <8 x i32> %1
+}
+
+define <4 x i32> @avx2_psrlv_d_128_allbig(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_128_allbig(
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> <i32 32, i32 100, i32 -255, i32 undef>)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psrlv_d_256_allbig(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_256_allbig(
+; CHECK-NEXT:    ret <8 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
+  ret <8 x i32> %1
+}
+
+define <4 x i32> @avx2_psrlv_d_128_undef(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_128_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> [[V:%.*]], <i32 undef, i32 8, i32 16, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 31>, i32 undef, i32 0
+  %2 = tail call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <8 x i32> @avx2_psrlv_d_256_undef(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_256_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 undef, i32 1
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <2 x i64> @avx2_psrlv_q_128_0(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_128_0(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> zeroinitializer)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx2_psrlv_q_256_0(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_256_0(
+; CHECK-NEXT:    ret <4 x i64> [[V:%.*]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> zeroinitializer)
+  ret <4 x i64> %1
+}
+
+define <2 x i64> @avx2_psrlv_q_128_var(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i64> [[V:%.*]], <i64 0, i64 8>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 8>)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx2_psrlv_q_256_var(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i64> [[V:%.*]], <i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 31>)
+  ret <4 x i64> %1
+}
+
+define <2 x i64> @avx2_psrlv_q_128_big(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_128_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> [[V:%.*]], <2 x i64> <i64 0, i64 128>)
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 128>)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx2_psrlv_q_256_big(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_256_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> [[V:%.*]], <4 x i64> <i64 0, i64 8, i64 16, i64 64>)
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 64>)
+  ret <4 x i64> %1
+}
+
+define <2 x i64> @avx2_psrlv_q_128_allbig(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_128_allbig(
+; CHECK-NEXT:    ret <2 x i64> zeroinitializer
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> <i64 128, i64 -64>)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx2_psrlv_q_256_allbig(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_256_allbig(
+; CHECK-NEXT:    ret <4 x i64> <i64 0, i64 undef, i64 0, i64 0>
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> <i64 64, i64 undef, i64 -128, i64 -60>)
+  ret <4 x i64> %1
+}
+
+; The shift amount is 0 (the undef lane could be 0), so we return the unshifted input.
+
+define <2 x i64> @avx2_psrlv_q_128_undef(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_128_undef(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = insertelement <2 x i64> <i64 0, i64 8>, i64 undef, i64 1
+  %2 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> %1)
+  ret <2 x i64> %2
+}
+
+define <4 x i64> @avx2_psrlv_q_256_undef(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psrlv_q_256_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
+  %2 = tail call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %v, <4 x i64> %1)
+  ret <4 x i64> %2
+}
+
+define <16 x i32> @avx2_psrlv_d_512_0(<16 x i32> %v) {
+; CHECK-LABEL: @avx2_psrlv_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[V:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> zeroinitializer)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrlv_d_512_var(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrlv_d_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i32> [[V:%.*]], <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrlv_d_512_big(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrlv_d_512_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> [[V:%.*]], <16 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrlv_d_512_allbig(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrlv_d_512_allbig(
+; CHECK-NEXT:    ret <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555, i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psrlv_d_512_undef(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psrlv_d_512_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 undef, i32 1
+  %2 = tail call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> %v, <16 x i32> %1)
+  ret <16 x i32> %2
+}
+
+define <8 x i64> @avx512_psrlv_q_512_0(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrlv_q_512_0(
+; CHECK-NEXT:    ret <8 x i64> [[V:%.*]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> zeroinitializer)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrlv_q_512_var(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrlv_q_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i64> [[V:%.*]], <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrlv_q_512_big(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrlv_q_512_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> [[V:%.*]], <8 x i64> <i64 0, i64 8, i64 16, i64 64, i64 0, i64 8, i64 16, i64 64>)
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 64, i64 0, i64 8, i64 16, i64 64>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrlv_q_512_allbig(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrlv_q_512_allbig(
+; CHECK-NEXT:    ret <8 x i64> <i64 0, i64 undef, i64 0, i64 0, i64 0, i64 undef, i64 0, i64 0>
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> <i64 64, i64 undef, i64 -128, i64 -60, i64 64, i64 undef, i64 -128, i64 -60>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psrlv_q_512_undef(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psrlv_q_512_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> %1)
+  ret <8 x i64> %2
+}
+
+define <8 x i16> @avx512_psrlv_w_128_0(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_128_0(
+; CHECK-NEXT:    ret <8 x i16> [[V:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16> %v, <8 x i16> zeroinitializer)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psrlv_w_128_var(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i16> [[V:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16> %v, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psrlv_w_128_big(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_128_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16> [[V:%.*]], <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 16>)
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16> %v, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 16>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psrlv_w_128_allbig(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_128_allbig(
+; CHECK-NEXT:    ret <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef>
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16> %v, <8 x i16> <i16 20, i16 -1, i16 -2, i16 33, i16 44, i16 55, i16 66, i16 undef>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psrlv_w_128_undef(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_128_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <8 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = insertelement <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 undef, i64 0
+  %2 = tail call <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16> %v, <8 x i16> %1)
+  ret <8 x i16> %2
+}
+
+define <16 x i16> @avx512_psrlv_w_256_0(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_256_0(
+; CHECK-NEXT:    ret <16 x i16> [[V:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16> %v, <16 x i16> zeroinitializer)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psrlv_w_256_var(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i16> [[V:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16> %v, <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psrlv_w_256_big(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_256_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16> [[V:%.*]], <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 16>)
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16> %v, <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 16>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psrlv_w_256_allbig(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_256_allbig(
+; CHECK-NEXT:    ret <16 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16> %v, <16 x i16> <i16 20, i16 -1, i16 -2, i16 33, i16 44, i16 55, i16 66, i16 -7, i16 undef, i16 64, i16 -10, i16 256, i16 16, i16 28, i16 65535, i16 32767>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psrlv_w_256_undef(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_256_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <16 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = insertelement <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, i16 undef, i64 0
+  %2 = tail call <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16> %v, <16 x i16> %1)
+  ret <16 x i16> %2
+}
+
+define <32 x i16> @avx512_psrlv_w_512_0(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[V:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16> %v, <32 x i16> zeroinitializer)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrlv_w_512_var(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <32 x i16> [[V:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16> %v, <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrlv_w_512_big(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_512_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16> [[V:%.*]], <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16> %v, <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrlv_w_512_allbig(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_512_allbig(
+; CHECK-NEXT:    ret <32 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 undef, i16 0, i16 0>
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16> %v, <32 x i16> <i16 20, i16 -1, i16 -2, i16 33, i16 44, i16 55, i16 66, i16 -7, i16 undef, i16 64, i16 -10, i16 128, i16 16, i16 28, i16 65535, i16 32767, i16 56, i16 -14, i16 undef, i16 16, i16 67, i16 567, i16 -32768, i16 4096, i16 8192, i16 -12345, i16 undef, i16 345, i16 123, i16 undef, i16 1024, i16 54321>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psrlv_w_512_undef(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psrlv_w_512_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <32 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = insertelement <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 undef, i64 0
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16> %v, <32 x i16> %1)
+  ret <32 x i16> %2
+}
+
+;
+; SHL - Constant Per-Element Vector
+;
+
+define <4 x i32> @avx2_psllv_d_128_0(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_128_0(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> zeroinitializer)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psllv_d_256_0(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_256_0(
+; CHECK-NEXT:    ret <8 x i32> [[V:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> zeroinitializer)
+  ret <8 x i32> %1
+}
+
+define <4 x i32> @avx2_psllv_d_128_var(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <4 x i32> [[V:%.*]], <i32 0, i32 8, i32 16, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 31>)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psllv_d_256_var(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i32> [[V:%.*]], <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
+  ret <8 x i32> %1
+}
+
+define <4 x i32> @avx2_psllv_d_128_big(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_128_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> [[V:%.*]], <4 x i32> <i32 0, i32 8, i32 16, i32 64>)
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> <i32 0, i32 8, i32 16, i32 64>)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psllv_d_256_big(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_256_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> [[V:%.*]], <8 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
+  ret <8 x i32> %1
+}
+
+define <4 x i32> @avx2_psllv_d_128_allbig(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_128_allbig(
+; CHECK-NEXT:    ret <4 x i32> <i32 0, i32 0, i32 0, i32 undef>
+;
+  %1 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> <i32 32, i32 100, i32 -255, i32 undef>)
+  ret <4 x i32> %1
+}
+
+define <8 x i32> @avx2_psllv_d_256_allbig(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_256_allbig(
+; CHECK-NEXT:    ret <8 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
+  ret <8 x i32> %1
+}
+
+define <4 x i32> @avx2_psllv_d_128_undef(<4 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_128_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <4 x i32> [[V:%.*]], <i32 undef, i32 8, i32 16, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 31>, i32 undef, i32 0
+  %2 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <8 x i32> @avx2_psllv_d_256_undef(<8 x i32> %v) {
+; CHECK-LABEL: @avx2_psllv_d_256_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 undef, i32 1
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %v, <8 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <2 x i64> @avx2_psllv_q_128_0(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_128_0(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> zeroinitializer)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx2_psllv_q_256_0(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_256_0(
+; CHECK-NEXT:    ret <4 x i64> [[V:%.*]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> zeroinitializer)
+  ret <4 x i64> %1
+}
+
+define <2 x i64> @avx2_psllv_q_128_var(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i64> [[V:%.*]], <i64 0, i64 8>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 8>)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx2_psllv_q_256_var(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <4 x i64> [[V:%.*]], <i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 31>)
+  ret <4 x i64> %1
+}
+
+define <2 x i64> @avx2_psllv_q_128_big(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_128_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> [[V:%.*]], <2 x i64> <i64 0, i64 128>)
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> <i64 0, i64 128>)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx2_psllv_q_256_big(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_256_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> [[V:%.*]], <4 x i64> <i64 0, i64 8, i64 16, i64 64>)
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> <i64 0, i64 8, i64 16, i64 64>)
+  ret <4 x i64> %1
+}
+
+define <2 x i64> @avx2_psllv_q_128_allbig(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_128_allbig(
+; CHECK-NEXT:    ret <2 x i64> zeroinitializer
+;
+  %1 = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> <i64 128, i64 -64>)
+  ret <2 x i64> %1
+}
+
+define <4 x i64> @avx2_psllv_q_256_allbig(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_256_allbig(
+; CHECK-NEXT:    ret <4 x i64> <i64 0, i64 undef, i64 0, i64 0>
+;
+  %1 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> <i64 64, i64 undef, i64 -128, i64 -60>)
+  ret <4 x i64> %1
+}
+
+; The shift amount is 0 (the undef lane could be 0), so we return the unshifted input.
+
+define <2 x i64> @avx2_psllv_q_128_undef(<2 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_128_undef(
+; CHECK-NEXT:    ret <2 x i64> [[V:%.*]]
+;
+  %1 = insertelement <2 x i64> <i64 0, i64 8>, i64 undef, i64 1
+  %2 = tail call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %v, <2 x i64> %1)
+  ret <2 x i64> %2
+}
+
+define <4 x i64> @avx2_psllv_q_256_undef(<4 x i64> %v) {
+; CHECK-LABEL: @avx2_psllv_q_256_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <4 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
+  %2 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> %1)
+  ret <4 x i64> %2
+}
+
+define <16 x i32> @avx512_psllv_d_512_0(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psllv_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[V:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> zeroinitializer)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psllv_d_512_var(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psllv_d_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <16 x i32> [[V:%.*]], <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 24, i32 31, i32 24, i32 8, i32 0>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psllv_d_512_big(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psllv_d_512_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> [[V:%.*]], <16 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> <i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 64, i32 31, i32 24, i32 8, i32 0>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psllv_d_512_allbig(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psllv_d_512_allbig(
+; CHECK-NEXT:    ret <16 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> <i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555, i32 undef, i32 100, i32 255, i32 55555, i32 -32, i32 -100, i32 -255, i32 -55555>)
+  ret <16 x i32> %1
+}
+
+define <16 x i32> @avx512_psllv_d_512_undef(<16 x i32> %v) {
+; CHECK-LABEL: @avx512_psllv_d_512_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <16 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 undef, i32 1
+  %2 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %v, <16 x i32> %1)
+  ret <16 x i32> %2
+}
+
+define <8 x i64> @avx512_psllv_q_512_0(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psllv_q_512_0(
+; CHECK-NEXT:    ret <8 x i64> [[V:%.*]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> zeroinitializer)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psllv_q_512_var(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psllv_q_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i64> [[V:%.*]], <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psllv_q_512_big(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psllv_q_512_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> [[V:%.*]], <8 x i64> <i64 0, i64 8, i64 16, i64 64, i64 0, i64 8, i64 16, i64 64>)
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> <i64 0, i64 8, i64 16, i64 64, i64 0, i64 8, i64 16, i64 64>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psllv_q_512_allbig(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psllv_q_512_allbig(
+; CHECK-NEXT:    ret <8 x i64> <i64 0, i64 undef, i64 0, i64 0, i64 0, i64 undef, i64 0, i64 0>
+;
+  %1 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> <i64 64, i64 undef, i64 -128, i64 -60, i64 64, i64 undef, i64 -128, i64 -60>)
+  ret <8 x i64> %1
+}
+
+define <8 x i64> @avx512_psllv_q_512_undef(<8 x i64> %v) {
+; CHECK-LABEL: @avx512_psllv_q_512_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 undef, i64 0
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> %v, <8 x i64> %1)
+  ret <8 x i64> %2
+}
+
+define <8 x i16> @avx512_psllv_w_128_0(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_128_0(
+; CHECK-NEXT:    ret <8 x i16> [[V:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16> %v, <8 x i16> zeroinitializer)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psllv_w_128_var(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i16> [[V:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16> %v, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psllv_w_128_big(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_128_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16> [[V:%.*]], <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 16>)
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16> %v, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 16>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psllv_w_128_allbig(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_128_allbig(
+; CHECK-NEXT:    ret <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef>
+;
+  %1 = tail call <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16> %v, <8 x i16> <i16 20, i16 -1, i16 -2, i16 33, i16 44, i16 55, i16 66, i16 undef>)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @avx512_psllv_w_128_undef(<8 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_128_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <8 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = insertelement <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 undef, i64 0
+  %2 = tail call <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16> %v, <8 x i16> %1)
+  ret <8 x i16> %2
+}
+
+define <16 x i16> @avx512_psllv_w_256_0(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_256_0(
+; CHECK-NEXT:    ret <16 x i16> [[V:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16> %v, <16 x i16> zeroinitializer)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psllv_w_256_var(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <16 x i16> [[V:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16> %v, <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psllv_w_256_big(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_256_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16> [[V:%.*]], <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 16>)
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16> %v, <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 16>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psllv_w_256_allbig(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_256_allbig(
+; CHECK-NEXT:    ret <16 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16> %v, <16 x i16> <i16 20, i16 -1, i16 -2, i16 33, i16 44, i16 55, i16 66, i16 -7, i16 undef, i16 64, i16 -10, i16 256, i16 16, i16 28, i16 65535, i16 32767>)
+  ret <16 x i16> %1
+}
+
+define <16 x i16> @avx512_psllv_w_256_undef(<16 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_256_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <16 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = insertelement <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, i16 undef, i64 0
+  %2 = tail call <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16> %v, <16 x i16> %1)
+  ret <16 x i16> %2
+}
+
+define <32 x i16> @avx512_psllv_w_512_0(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[V:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> %v, <32 x i16> zeroinitializer)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psllv_w_512_var(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <32 x i16> [[V:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> %v, <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psllv_w_512_big(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_512_big(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> [[V:%.*]], <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> %v, <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psllv_w_512_allbig(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_512_allbig(
+; CHECK-NEXT:    ret <32 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 undef, i16 0, i16 0>
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> %v, <32 x i16> <i16 20, i16 -1, i16 -2, i16 33, i16 44, i16 55, i16 66, i16 -7, i16 undef, i16 64, i16 -10, i16 128, i16 16, i16 28, i16 65535, i16 32767, i16 56, i16 -14, i16 undef, i16 16, i16 67, i16 567, i16 -32768, i16 4096, i16 8192, i16 -12345, i16 undef, i16 345, i16 123, i16 undef, i16 1024, i16 54321>)
+  ret <32 x i16> %1
+}
+
+define <32 x i16> @avx512_psllv_w_512_undef(<32 x i16> %v) {
+; CHECK-LABEL: @avx512_psllv_w_512_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <32 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = insertelement <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 undef, i64 0
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> %v, <32 x i16> %1)
+  ret <32 x i16> %2
+}
+
+;
+; Vector Masked Shift Amounts
+;
+
+define <8 x i16> @sse2_psra_w_128_masked(<8 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @sse2_psra_w_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], <i16 15, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = ashr <8 x i16> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+;
+  %1 = and <8 x i16> %a, <i16 15, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>
+  %2 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> %1)
+  ret <8 x i16> %2
+}
+
+define <8 x i32> @avx2_psra_d_256_masked(<8 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psra_d_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = ashr <8 x i32> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP3]]
+;
+  %1 = and <4 x i32> %a, <i32 31, i32 0, i32 undef, i32 undef>
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <8 x i64> @avx512_psra_q_512_masked(<8 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx512_psra_q_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 63, i64 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = ashr <8 x i64> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <8 x i64> [[TMP3]]
+;
+  %1 = and <2 x i64> %a, <i64 63, i64 undef>
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> %v, <2 x i64> %1)
+  ret <8 x i64> %2
+}
+
+define <4 x i32> @sse2_psrl_d_128_masked(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @sse2_psrl_d_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr <4 x i32> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
+;
+  %1 = and <4 x i32> %a, <i32 31, i32 0, i32 undef, i32 undef>
+  %2 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <4 x i64> @avx2_psrl_q_256_masked(<4 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx2_psrl_q_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 63, i64 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr <4 x i64> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP3]]
+;
+  %1 = and <2 x i64> %a, <i64 63, i64 undef>
+  %2 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> %1)
+  ret <4 x i64> %2
+}
+
+define <32 x i16> @avx512_psrl_w_512_masked(<32 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @avx512_psrl_w_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], <i16 15, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <32 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr <32 x i16> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
+;
+  %1 = and <8 x i16> %a, <i16 15, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> %v, <8 x i16> %1)
+  ret <32 x i16> %2
+}
+
+define <2 x i64> @sse2_psll_q_128_masked(<2 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @sse2_psll_q_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 63, i64 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = shl <2 x i64> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
+;
+  %1 = and <2 x i64> %a, <i64 63, i64 undef>
+  %2 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> %1)
+  ret <2 x i64> %2
+}
+
+define <16 x i16> @avx2_psll_w_256_masked(<16 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @avx2_psll_w_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], <i16 15, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = shl <16 x i16> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %1 = and <8 x i16> %a, <i16 15, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef>
+  %2 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> %1)
+  ret <16 x i16> %2
+}
+
+define <16 x i32> @avx512_psll_d_512_masked(<16 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx512_psll_d_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = shl <16 x i32> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <16 x i32> [[TMP3]]
+;
+  %1 = and <4 x i32> %a, <i32 31, i32 0, i32 undef, i32 undef>
+  %2 = tail call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> %v, <4 x i32> %1)
+  ret <16 x i32> %2
+}
+
+define <8 x i16> @sse2_psrai_w_128_masked(<8 x i16> %v, i32 %a) {
+; CHECK-LABEL: @sse2_psrai_w_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[A:%.*]] to i16
+; CHECK-NEXT:    [[TMP2:%.*]] = and i16 [[TMP1]], 15
+; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i32 0
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <8 x i16> [[DOTSPLATINSERT]], <8 x i16> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = ashr <8 x i16> [[V:%.*]], [[DOTSPLAT]]
+; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+;
+  %1 = and i32 %a, 15
+  %2 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %v, i32 %1)
+  ret <8 x i16> %2
+}
+
+define <8 x i32> @avx2_psrai_d_256_masked(<8 x i32> %v, i32 %a) {
+; CHECK-LABEL: @avx2_psrai_d_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 31
+; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <8 x i32> undef, i32 [[TMP1]], i32 0
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <8 x i32> [[DOTSPLATINSERT]], <8 x i32> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <8 x i32> [[V:%.*]], [[DOTSPLAT]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP2]]
+;
+  %1 = and i32 %a, 31
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %v, i32 %1)
+  ret <8 x i32> %2
+}
+
+define <8 x i64> @avx512_psrai_q_512_masked(<8 x i64> %v, i32 %a) {
+; CHECK-LABEL: @avx512_psrai_q_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 63
+; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <8 x i64> undef, i64 [[TMP2]], i32 0
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <8 x i64> [[DOTSPLATINSERT]], <8 x i64> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = ashr <8 x i64> [[V:%.*]], [[DOTSPLAT]]
+; CHECK-NEXT:    ret <8 x i64> [[TMP3]]
+;
+  %1 = and i32 %a, 63
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64> %v, i32 %1)
+  ret <8 x i64> %2
+}
+
+define <4 x i32> @sse2_psrli_d_128_masked(<4 x i32> %v, i32 %a) {
+; CHECK-LABEL: @sse2_psrli_d_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 31
+; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[TMP1]], i32 0
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <4 x i32> [[DOTSPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr <4 x i32> [[V:%.*]], [[DOTSPLAT]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = and i32 %a, 31
+  %2 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %v, i32 %1)
+  ret <4 x i32> %2
+}
+
+define <4 x i64> @avx2_psrli_q_256_masked(<4 x i64> %v, i32 %a) {
+; CHECK-LABEL: @avx2_psrli_q_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 63
+; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <4 x i64> undef, i64 [[TMP2]], i32 0
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <4 x i64> [[DOTSPLATINSERT]], <4 x i64> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr <4 x i64> [[V:%.*]], [[DOTSPLAT]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP3]]
+;
+  %1 = and i32 %a, 63
+  %2 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %v, i32 %1)
+  ret <4 x i64> %2
+}
+
+define <32 x i16> @avx512_psrli_w_512_masked(<32 x i16> %v, i32 %a) {
+; CHECK-LABEL: @avx512_psrli_w_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[A:%.*]] to i16
+; CHECK-NEXT:    [[TMP2:%.*]] = and i16 [[TMP1]], 15
+; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <32 x i16> undef, i16 [[TMP2]], i32 0
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <32 x i16> [[DOTSPLATINSERT]], <32 x i16> undef, <32 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = lshr <32 x i16> [[V:%.*]], [[DOTSPLAT]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
+;
+  %1 = and i32 %a, 15
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psrli.w.512(<32 x i16> %v, i32 %1)
+  ret <32 x i16> %2
+}
+
+define <2 x i64> @sse2_pslli_q_128_masked(<2 x i64> %v, i32 %a) {
+; CHECK-LABEL: @sse2_pslli_q_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 63
+; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2]], i32 0
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <2 x i64> [[DOTSPLATINSERT]], <2 x i64> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = shl <2 x i64> [[V:%.*]], [[DOTSPLAT]]
+; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
+;
+  %1 = and i32 %a, 63
+  %2 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %v, i32 %1)
+  ret <2 x i64> %2
+}
+
+define <16 x i16> @avx2_pslli_w_256_masked(<16 x i16> %v, i32 %a) {
+; CHECK-LABEL: @avx2_pslli_w_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[A:%.*]] to i16
+; CHECK-NEXT:    [[TMP2:%.*]] = and i16 [[TMP1]], 15
+; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <16 x i16> undef, i16 [[TMP2]], i32 0
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <16 x i16> [[DOTSPLATINSERT]], <16 x i16> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = shl <16 x i16> [[V:%.*]], [[DOTSPLAT]]
+; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %1 = and i32 %a, 15
+  %2 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %v, i32 %1)
+  ret <16 x i16> %2
+}
+
+define <16 x i32> @avx512_pslli_d_512_masked(<16 x i32> %v, i32 %a) {
+; CHECK-LABEL: @avx512_pslli_d_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[A:%.*]], 31
+; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <16 x i32> undef, i32 [[TMP1]], i32 0
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <16 x i32> [[DOTSPLATINSERT]], <16 x i32> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = shl <16 x i32> [[V:%.*]], [[DOTSPLAT]]
+; CHECK-NEXT:    ret <16 x i32> [[TMP2]]
+;
+  %1 = and i32 %a, 31
+  %2 = tail call <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32> %v, i32 %1)
+  ret <16 x i32> %2
+}
+
+define <4 x i32> @avx2_psrav_d_128_masked(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psrav_d_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <4 x i32> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = and <4 x i32> %a, <i32 31, i32 31, i32 31, i32 31>
+  %2 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <4 x i32> @avx2_psrav_d_128_masked_shuffle(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psrav_d_128_masked_shuffle(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 poison, i32 poison, i32 15, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = ashr <4 x i32> [[V:%.*]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
+;
+  %1 = and <4 x i32> %a, <i32 undef, i32 undef, i32 15, i32 31>
+  %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
+  %3 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> %2)
+  ret <4 x i32> %3
+}
+
+define <8 x i32> @avx2_psrav_d_256_masked(<8 x i32> %v, <8 x i32> %a) {
+; CHECK-LABEL: @avx2_psrav_d_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i32> [[A:%.*]], <i32 0, i32 1, i32 7, i32 15, i32 16, i32 30, i32 31, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <8 x i32> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP2]]
+;
+  %1 = and <8 x i32> %a, <i32 0, i32 1, i32 7, i32 15, i32 16, i32 30, i32 31, i32 31>
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> %v, <8 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <32 x i16> @avx512_psrav_w_512_masked(<32 x i16> %v, <32 x i16> %a) {
+; CHECK-LABEL: @avx512_psrav_w_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <32 x i16> [[A:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    [[TMP2:%.*]] = ashr <32 x i16> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP2]]
+;
+  %1 = and <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16> %v, <32 x i16> %1)
+  ret <32 x i16> %2
+}
+
+define <2 x i64> @avx2_psrlv_q_128_masked(<2 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx2_psrlv_q_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 32, i64 63>
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr <2 x i64> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+;
+  %1 = and <2 x i64> %a, <i64 32, i64 63>
+  %2 = tail call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> %v, <2 x i64> %1)
+  ret <2 x i64> %2
+}
+
+define <8 x i32> @avx2_psrlv_d_256_masked(<8 x i32> %v, <8 x i32> %a) {
+; CHECK-LABEL: @avx2_psrlv_d_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i32> [[A:%.*]], <i32 0, i32 1, i32 7, i32 15, i32 16, i32 30, i32 31, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr <8 x i32> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP2]]
+;
+  %1 = and <8 x i32> %a, <i32 0, i32 1, i32 7, i32 15, i32 16, i32 30, i32 31, i32 31>
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> %v, <8 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <8 x i64> @avx512_psrlv_q_512_masked(<8 x i64> %v, <8 x i64> %a) {
+; CHECK-LABEL: @avx512_psrlv_q_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i64> [[A:%.*]], <i64 0, i64 1, i64 4, i64 16, i64 32, i64 47, i64 62, i64 63>
+; CHECK-NEXT:    [[TMP2:%.*]] = lshr <8 x i64> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <8 x i64> [[TMP2]]
+;
+  %1 = and <8 x i64> %a, <i64 0, i64 1, i64 4, i64 16, i64 32, i64 47, i64 62, i64 63>
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> %v, <8 x i64> %1)
+  ret <8 x i64> %2
+}
+
+define <4 x i32> @avx2_psllv_d_128_masked(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psllv_d_128_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 0, i32 15, i32 16, i32 31>
+; CHECK-NEXT:    [[TMP2:%.*]] = shl <4 x i32> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = and <4 x i32> %a, <i32 0, i32 15, i32 16, i32 31>
+  %2 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <4 x i64> @avx2_psllv_q_256_masked(<4 x i64> %v, <4 x i64> %a) {
+; CHECK-LABEL: @avx2_psllv_q_256_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i64> [[A:%.*]], <i64 0, i64 16, i64 32, i64 63>
+; CHECK-NEXT:    [[TMP2:%.*]] = shl <4 x i64> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP2]]
+;
+  %1 = and <4 x i64> %a, <i64 0, i64 16, i64 32, i64 63>
+  %2 = tail call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> %v, <4 x i64> %1)
+  ret <4 x i64> %2
+}
+
+define <32 x i16> @avx512_psllv_w_512_masked(<32 x i16> %v, <32 x i16> %a) {
+; CHECK-LABEL: @avx512_psllv_w_512_masked(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <32 x i16> [[A:%.*]], <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+; CHECK-NEXT:    [[TMP2:%.*]] = shl <32 x i16> [[V:%.*]], [[TMP1]]
+; CHECK-NEXT:    ret <32 x i16> [[TMP2]]
+;
+  %1 = and <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> %v, <32 x i16> %1)
+  ret <32 x i16> %2
+}
+
+;
+; Vector Demanded Bits
+;
+
+define <8 x i16> @sse2_psra_w_var(<8 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @sse2_psra_w_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> [[V:%.*]], <8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> %1)
+  ret <8 x i16> %2
+}
+
+define <8 x i16> @sse2_psra_w_var_bc(<8 x i16> %v, <2 x i64> %a) {
+; CHECK-LABEL: @sse2_psra_w_var_bc(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[A:%.*]] to <8 x i16>
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> [[V:%.*]], <8 x i16> [[TMP1]])
+; CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = bitcast <2 x i64> %1 to <8 x i16>
+  %3 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> %2)
+  ret <8 x i16> %3
+}
+
+define <4 x i32> @sse2_psra_d_var(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @sse2_psra_d_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> [[V:%.*]], <4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %2 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <4 x i32> @sse2_psra_d_var_bc(<4 x i32> %v, <8 x i16> %a) {
+; CHECK-LABEL: @sse2_psra_d_var_bc(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i16> [[A:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> [[V:%.*]], <4 x i32> [[TMP1]])
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = bitcast <8 x i16> %1 to <4 x i32>
+  %3 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> %2)
+  ret <4 x i32> %3
+}
+
+define <16 x i16> @avx2_psra_w_var(<16 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @avx2_psra_w_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> [[V:%.*]], <8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> %1)
+  ret <16 x i16> %2
+}
+
+define <8 x i32> @avx2_psra_d_var(<8 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psra_d_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> [[V:%.*]], <4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <2 x i64> @avx512_psra_q_128_var(<2 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx512_psra_q_128_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> [[V:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = tail call <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64> %v, <2 x i64> %1)
+  ret <2 x i64> %2
+}
+
+define <4 x i64> @avx512_psra_q_256_var(<4 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx512_psra_q_256_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> [[V:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = tail call <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64> %v, <2 x i64> %1)
+  ret <4 x i64> %2
+}
+
+define <32 x i16> @avx512_psra_w_512_var(<32 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @avx512_psra_w_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <32 x i16> @llvm.x86.avx512.psra.w.512(<32 x i16> [[V:%.*]], <8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psra.w.512(<32 x i16> %v, <8 x i16> %1)
+  ret <32 x i16> %2
+}
+
+define <16 x i32> @avx512_psra_d_512_var(<16 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx512_psra_d_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> [[V:%.*]], <4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %2 = tail call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %v, <4 x i32> %1)
+  ret <16 x i32> %2
+}
+
+define <8 x i64> @avx512_psra_q_512_var(<8 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx512_psra_q_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> [[V:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64> %v, <2 x i64> %1)
+  ret <8 x i64> %2
+}
+
+define <8 x i16> @sse2_psrl_w_var(<8 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @sse2_psrl_w_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> [[V:%.*]], <8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> %1)
+  ret <8 x i16> %2
+}
+
+define <4 x i32> @sse2_psrl_d_var(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @sse2_psrl_d_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> [[V:%.*]], <4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %2 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <2 x i64> @sse2_psrl_q_var(<2 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @sse2_psrl_q_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> [[V:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> %1)
+  ret <2 x i64> %2
+}
+
+define <16 x i16> @avx2_psrl_w_var(<16 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @avx2_psrl_w_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[V:%.*]], <8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> %1)
+  ret <16 x i16> %2
+}
+
+define <16 x i16> @avx2_psrl_w_var_bc(<16 x i16> %v, <16 x i8> %a) {
+; CHECK-LABEL: @avx2_psrl_w_var_bc(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[A:%.*]] to <8 x i16>
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> [[V:%.*]], <8 x i16> [[TMP1]])
+; CHECK-NEXT:    ret <16 x i16> [[TMP2]]
+;
+  %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %2 = bitcast <16 x i8> %1 to <8 x i16>
+  %3 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> %2)
+  ret <16 x i16> %3
+}
+
+define <8 x i32> @avx2_psrl_d_var(<8 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psrl_d_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> [[V:%.*]], <4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <8 x i32> @avx2_psrl_d_var_bc(<8 x i32> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx2_psrl_d_var_bc(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[A:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> [[V:%.*]], <4 x i32> [[TMP1]])
+; CHECK-NEXT:    ret <8 x i32> [[TMP2]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = bitcast <2 x i64> %1 to <4 x i32>
+  %3 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> %2)
+  ret <8 x i32> %3
+}
+
+define <4 x i64> @avx2_psrl_q_var(<4 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx2_psrl_q_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> [[V:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> %1)
+  ret <4 x i64> %2
+}
+
+define <32 x i16> @avx512_psrl_w_512_var(<32 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @avx512_psrl_w_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> [[V:%.*]], <8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> %v, <8 x i16> %1)
+  ret <32 x i16> %2
+}
+
+define <32 x i16> @avx512_psrl_w_512_var_bc(<32 x i16> %v, <16 x i8> %a) {
+; CHECK-LABEL: @avx512_psrl_w_512_var_bc(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8> [[A:%.*]] to <8 x i16>
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> [[V:%.*]], <8 x i16> [[TMP1]])
+; CHECK-NEXT:    ret <32 x i16> [[TMP2]]
+;
+  %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %2 = bitcast <16 x i8> %1 to <8 x i16>
+  %3 = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> %v, <8 x i16> %2)
+  ret <32 x i16> %3
+}
+
+define <16 x i32> @avx512_psrl_d_512_var(<16 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx512_psrl_d_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> [[V:%.*]], <4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %2 = tail call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> %v, <4 x i32> %1)
+  ret <16 x i32> %2
+}
+
+define <16 x i32> @avx512_psrl_d_512_var_bc(<16 x i32> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx512_psrl_d_512_var_bc(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[A:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> [[V:%.*]], <4 x i32> [[TMP1]])
+; CHECK-NEXT:    ret <16 x i32> [[TMP2]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = bitcast <2 x i64> %1 to <4 x i32>
+  %3 = tail call <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32> %v, <4 x i32> %2)
+  ret <16 x i32> %3
+}
+
+define <8 x i64> @avx512_psrl_q_512_var(<8 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx512_psrl_q_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> [[V:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64> %v, <2 x i64> %1)
+  ret <8 x i64> %2
+}
+
+define <8 x i16> @sse2_psll_w_var(<8 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @sse2_psll_w_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> [[V:%.*]], <8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <8 x i16> [[TMP1]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> %1)
+  ret <8 x i16> %2
+}
+
+define <4 x i32> @sse2_psll_d_var(<4 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @sse2_psll_d_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> [[V:%.*]], <4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %2 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> %1)
+  ret <4 x i32> %2
+}
+
+define <2 x i64> @sse2_psll_q_var(<2 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @sse2_psll_q_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> [[V:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> %1)
+  ret <2 x i64> %2
+}
+
+define <16 x i16> @avx2_psll_w_var(<16 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @avx2_psll_w_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> [[V:%.*]], <8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <16 x i16> [[TMP1]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> %1)
+  ret <16 x i16> %2
+}
+
+define <8 x i32> @avx2_psll_d_var(<8 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx2_psll_d_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> [[V:%.*]], <4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> %1)
+  ret <8 x i32> %2
+}
+
+define <4 x i64> @avx2_psll_q_var(<4 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx2_psll_q_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> [[V:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <4 x i64> [[TMP1]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> %1)
+  ret <4 x i64> %2
+}
+
+define <32 x i16> @avx512_psll_w_512_var(<32 x i16> %v, <8 x i16> %a) {
+; CHECK-LABEL: @avx512_psll_w_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <32 x i16> @llvm.x86.avx512.psll.w.512(<32 x i16> [[V:%.*]], <8 x i16> [[A:%.*]])
+; CHECK-NEXT:    ret <32 x i16> [[TMP1]]
+;
+  %1 = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psll.w.512(<32 x i16> %v, <8 x i16> %1)
+  ret <32 x i16> %2
+}
+
+define <16 x i32> @avx512_psll_d_512_var(<16 x i32> %v, <4 x i32> %a) {
+; CHECK-LABEL: @avx512_psll_d_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> [[V:%.*]], <4 x i32> [[A:%.*]])
+; CHECK-NEXT:    ret <16 x i32> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %2 = tail call <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32> %v, <4 x i32> %1)
+  ret <16 x i32> %2
+}
+
+define <8 x i64> @avx512_psll_q_512_var(<8 x i64> %v, <2 x i64> %a) {
+; CHECK-LABEL: @avx512_psll_q_512_var(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> [[V:%.*]], <2 x i64> [[A:%.*]])
+; CHECK-NEXT:    ret <8 x i64> [[TMP1]]
+;
+  %1 = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
+  %2 = tail call <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64> %v, <2 x i64> %1)
+  ret <8 x i64> %2
+}
+
+;
+; Constant Folding
+;
+
+define <8 x i16> @test_sse2_psra_w_0(<8 x i16> %A) {
+; CHECK-LABEL: @test_sse2_psra_w_0(
+; CHECK-NEXT:    ret <8 x i16> [[A:%.*]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %A, i32 0)
+  %2 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %1, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
+  %3 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %2, i32 0)
+  ret <8 x i16> %3
+}
+
+define <8 x i16> @test_sse2_psra_w_8() {
+; CHECK-LABEL: @test_sse2_psra_w_8(
+; CHECK-NEXT:    ret <8 x i16> <i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16>
+;
+  %1 = bitcast <2 x i64> <i64 1152956690052710400, i64 1152956690052710400> to <8 x i16>
+  %2 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %1, i32 3)
+  %3 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %2, <8 x i16> <i16 3, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
+  %4 = tail call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %3, i32 2)
+  ret <8 x i16> %4
+}
+
+define <4 x i32> @test_sse2_psra_d_0(<4 x i32> %A) {
+; CHECK-LABEL: @test_sse2_psra_d_0(
+; CHECK-NEXT:    ret <4 x i32> [[A:%.*]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %A, i32 0)
+  %2 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %1, <4 x i32> <i32 0, i32 0, i32 7, i32 0>)
+  %3 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %1, i32 0)
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @sse2_psra_d_8() {
+; CHECK-LABEL: @sse2_psra_d_8(
+; CHECK-NEXT:    ret <4 x i32> <i32 4194432, i32 1048608, i32 4194432, i32 1048608>
+;
+  %1 = bitcast <2 x i64> <i64 1152956690052710400, i64 1152956690052710400> to <4 x i32>
+  %2 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %1, i32 3)
+  %3 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %2, <4 x i32> <i32 3, i32 0, i32 7, i32 0>)
+  %4 = tail call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %3, i32 2)
+  ret <4 x i32> %4
+}
+
+define <16 x i16> @test_avx2_psra_w_0(<16 x i16> %A) {
+; CHECK-LABEL: @test_avx2_psra_w_0(
+; CHECK-NEXT:    ret <16 x i16> [[A:%.*]]
+;
+  %1 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %A, i32 0)
+  %2 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %1, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
+  %3 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %2, i32 0)
+  ret <16 x i16> %3
+}
+
+define <16 x i16> @test_avx2_psra_w_8(<16 x i16> %A) {
+; CHECK-LABEL: @test_avx2_psra_w_8(
+; CHECK-NEXT:    ret <16 x i16> <i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16>
+;
+  %1 = bitcast <4 x i64> <i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400> to <16 x i16>
+  %2 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %1, i32 3)
+  %3 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %2, <8 x i16> <i16 3, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
+  %4 = tail call <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16> %3, i32 2)
+  ret <16 x i16> %4
+}
+
+define <8 x i32> @test_avx2_psra_d_0(<8 x i32> %A) {
+; CHECK-LABEL: @test_avx2_psra_d_0(
+; CHECK-NEXT:    ret <8 x i32> [[A:%.*]]
+;
+  %1 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %A, i32 0)
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %1, <4 x i32> <i32 0, i32 0, i32 7, i32 0>)
+  %3 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %2, i32 0)
+  ret <8 x i32> %3
+}
+
+define <8 x i32> @test_avx2_psra_d_8() {
+; CHECK-LABEL: @test_avx2_psra_d_8(
+; CHECK-NEXT:    ret <8 x i32> <i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608>
+;
+  %1 = bitcast <4 x i64> <i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400> to <8 x i32>
+  %2 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %1, i32 3)
+  %3 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %2, <4 x i32> <i32 3, i32 0, i32 7, i32 0>)
+  %4 = tail call <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32> %3, i32 2)
+  ret <8 x i32> %4
+}
+
+define <32 x i16> @test_avx512_psra_w_512_0(<32 x i16> %A) {
+; CHECK-LABEL: @test_avx512_psra_w_512_0(
+; CHECK-NEXT:    ret <32 x i16> [[A:%.*]]
+;
+  %1 = tail call <32 x i16> @llvm.x86.avx512.psrai.w.512(<32 x i16> %A, i32 0)
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psra.w.512(<32 x i16> %1, <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
+  %3 = tail call <32 x i16> @llvm.x86.avx512.psrai.w.512(<32 x i16> %2, i32 0)
+  ret <32 x i16> %3
+}
+
+define <32 x i16> @test_avx512_psra_w_512_8(<32 x i16> %A) {
+; CHECK-LABEL: @test_avx512_psra_w_512_8(
+; CHECK-NEXT:    ret <32 x i16> <i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16, i16 -128, i16 64, i16 32, i16 16>
+;
+  %1 = bitcast <8 x i64> <i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400> to <32 x i16>
+  %2 = tail call <32 x i16> @llvm.x86.avx512.psrai.w.512(<32 x i16> %1, i32 3)
+  %3 = tail call <32 x i16> @llvm.x86.avx512.psra.w.512(<32 x i16> %2, <8 x i16> <i16 3, i16 0, i16 0, i16 0, i16 7, i16 0, i16 0, i16 0>)
+  %4 = tail call <32 x i16> @llvm.x86.avx512.psrai.w.512(<32 x i16> %3, i32 2)
+  ret <32 x i16> %4
+}
+
+define <16 x i32> @test_avx512_psra_d_512_0(<16 x i32> %A) {
+; CHECK-LABEL: @test_avx512_psra_d_512_0(
+; CHECK-NEXT:    ret <16 x i32> [[A:%.*]]
+;
+  %1 = tail call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %A, i32 0)
+  %2 = tail call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %1, <4 x i32> <i32 0, i32 0, i32 7, i32 0>)
+  %3 = tail call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %2, i32 0)
+  ret <16 x i32> %3
+}
+
+define <16 x i32> @test_avx512_psra_d_512_8() {
+; CHECK-LABEL: @test_avx512_psra_d_512_8(
+; CHECK-NEXT:    ret <16 x i32> <i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608, i32 4194432, i32 1048608>
+;
+  %1 = bitcast <8 x i64> <i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400, i64 1152956690052710400> to <16 x i32>
+  %2 = tail call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %1, i32 3)
+  %3 = tail call <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32> %2, <4 x i32> <i32 3, i32 0, i32 7, i32 0>)
+  %4 = tail call <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32> %3, i32 2)
+  ret <16 x i32> %4
+}
+
+;
+; Old Tests
+;
+
+define <2 x i64> @test_sse2_1() {
+; CHECK-LABEL: @test_sse2_1(
+; CHECK-NEXT:    ret <2 x i64> <i64 72058418680037440, i64 144117112246370624>
+;
+  %S = bitcast i32 1 to i32
+  %1 = zext i32 %S to i64
+  %2 = insertelement <2 x i64> poison, i64 %1, i32 0
+  %3 = insertelement <2 x i64> %2, i64 0, i32 1
+  %4 = bitcast <2 x i64> %3 to <8 x i16>
+  %5 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, <8 x i16> %4)
+  %6 = bitcast <8 x i16> %5 to <4 x i32>
+  %7 = bitcast <2 x i64> %3 to <4 x i32>
+  %8 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %6, <4 x i32> %7)
+  %9 = bitcast <4 x i32> %8 to <2 x i64>
+  %10 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %9, <2 x i64> %3)
+  %11 = bitcast <2 x i64> %10 to <8 x i16>
+  %12 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %11, i32 %S)
+  %13 = bitcast <8 x i16> %12 to <4 x i32>
+  %14 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %13, i32 %S)
+  %15 = bitcast <4 x i32> %14 to <2 x i64>
+  %16 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %15, i32 %S)
+  ret <2 x i64> %16
+}
+
+define <4 x i64> @test_avx2_1() {
+; CHECK-LABEL: @test_avx2_1(
+; CHECK-NEXT:    ret <4 x i64> <i64 64, i64 128, i64 192, i64 256>
+;
+  %S = bitcast i32 1 to i32
+  %1 = zext i32 %S to i64
+  %2 = insertelement <2 x i64> poison, i64 %1, i32 0
+  %3 = insertelement <2 x i64> %2, i64 0, i32 1
+  %4 = bitcast <2 x i64> %3 to <8 x i16>
+  %5 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> <i16 1, i16 0, i16 0, i16 0, i16 2, i16 0, i16 0, i16 0, i16 3, i16 0, i16 0, i16 0, i16 4, i16 0, i16 0, i16 0>, <8 x i16> %4)
+  %6 = bitcast <16 x i16> %5 to <8 x i32>
+  %7 = bitcast <2 x i64> %3 to <4 x i32>
+  %8 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %6, <4 x i32> %7)
+  %9 = bitcast <8 x i32> %8 to <4 x i64>
+  %10 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %9, <2 x i64> %3)
+  %11 = bitcast <4 x i64> %10 to <16 x i16>
+  %12 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %11, i32 %S)
+  %13 = bitcast <16 x i16> %12 to <8 x i32>
+  %14 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %13, i32 %S)
+  %15 = bitcast <8 x i32> %14 to <4 x i64>
+  %16 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %15, i32 %S)
+  ret <4 x i64> %16
+}
+
+define <2 x i64> @test_sse2_0() {
+; CHECK-LABEL: @test_sse2_0(
+; CHECK-NEXT:    ret <2 x i64> zeroinitializer
+;
+  %S = bitcast i32 128 to i32
+  %1 = zext i32 %S to i64
+  %2 = insertelement <2 x i64> poison, i64 %1, i32 0
+  %3 = insertelement <2 x i64> %2, i64 0, i32 1
+  %4 = bitcast <2 x i64> %3 to <8 x i16>
+  %5 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>, <8 x i16> %4)
+  %6 = bitcast <8 x i16> %5 to <4 x i32>
+  %7 = bitcast <2 x i64> %3 to <4 x i32>
+  %8 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %6, <4 x i32> %7)
+  %9 = bitcast <4 x i32> %8 to <2 x i64>
+  %10 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %9, <2 x i64> %3)
+  %11 = bitcast <2 x i64> %10 to <8 x i16>
+  %12 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %11, i32 %S)
+  %13 = bitcast <8 x i16> %12 to <4 x i32>
+  %14 = tail call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %13, i32 %S)
+  %15 = bitcast <4 x i32> %14 to <2 x i64>
+  %16 = tail call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %15, i32 %S)
+  ret <2 x i64> %16
+}
+
+define <4 x i64> @test_avx2_0() {
+; CHECK-LABEL: @test_avx2_0(
+; CHECK-NEXT:    ret <4 x i64> zeroinitializer
+;
+  %S = bitcast i32 128 to i32
+  %1 = zext i32 %S to i64
+  %2 = insertelement <2 x i64> poison, i64 %1, i32 0
+  %3 = insertelement <2 x i64> %2, i64 0, i32 1
+  %4 = bitcast <2 x i64> %3 to <8 x i16>
+  %5 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> <i16 1, i16 0, i16 0, i16 0, i16 2, i16 0, i16 0, i16 0, i16 3, i16 0, i16 0, i16 0, i16 4, i16 0, i16 0, i16 0>, <8 x i16> %4)
+  %6 = bitcast <16 x i16> %5 to <8 x i32>
+  %7 = bitcast <2 x i64> %3 to <4 x i32>
+  %8 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %6, <4 x i32> %7)
+  %9 = bitcast <8 x i32> %8 to <4 x i64>
+  %10 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %9, <2 x i64> %3)
+  %11 = bitcast <4 x i64> %10 to <16 x i16>
+  %12 = tail call <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16> %11, i32 %S)
+  %13 = bitcast <16 x i16> %12 to <8 x i32>
+  %14 = tail call <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32> %13, i32 %S)
+  %15 = bitcast <8 x i32> %14 to <4 x i64>
+  %16 = tail call <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64> %15, i32 %S)
+  ret <4 x i64> %16
+}
+define <2 x i64> @test_sse2_psrl_1() {
+; CHECK-LABEL: @test_sse2_psrl_1(
+; CHECK-NEXT:    ret <2 x i64> <i64 562954248421376, i64 9007267974742020>
+;
+  %S = bitcast i32 1 to i32
+  %1 = zext i32 %S to i64
+  %2 = insertelement <2 x i64> poison, i64 %1, i32 0
+  %3 = insertelement <2 x i64> %2, i64 0, i32 1
+  %4 = bitcast <2 x i64> %3 to <8 x i16>
+  %5 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> <i16 16, i16 32, i16 64, i16 128, i16 256, i16 512, i16 1024, i16 2048>, <8 x i16> %4)
+  %6 = bitcast <8 x i16> %5 to <4 x i32>
+  %7 = bitcast <2 x i64> %3 to <4 x i32>
+  %8 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %6, <4 x i32> %7)
+  %9 = bitcast <4 x i32> %8 to <2 x i64>
+  %10 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %9, <2 x i64> %3)
+  %11 = bitcast <2 x i64> %10 to <8 x i16>
+  %12 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %11, i32 %S)
+  %13 = bitcast <8 x i16> %12 to <4 x i32>
+  %14 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %13, i32 %S)
+  %15 = bitcast <4 x i32> %14 to <2 x i64>
+  %16 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %15, i32 %S)
+  ret <2 x i64> %16
+}
+
+define <4 x i64> @test_avx2_psrl_1() {
+; CHECK-LABEL: @test_avx2_psrl_1(
+; CHECK-NEXT:    ret <4 x i64> <i64 16, i64 32, i64 64, i64 128>
+;
+  %S = bitcast i32 1 to i32
+  %1 = zext i32 %S to i64
+  %2 = insertelement <2 x i64> poison, i64 %1, i32 0
+  %3 = insertelement <2 x i64> %2, i64 0, i32 1
+  %4 = bitcast <2 x i64> %3 to <8 x i16>
+  %5 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> <i16 1024, i16 0, i16 0, i16 0, i16 2048, i16 0, i16 0, i16 0, i16 4096, i16 0, i16 0, i16 0, i16 8192, i16 0, i16 0, i16 0>, <8 x i16> %4)
+  %6 = bitcast <16 x i16> %5 to <8 x i32>
+  %7 = bitcast <2 x i64> %3 to <4 x i32>
+  %8 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %6, <4 x i32> %7)
+  %9 = bitcast <8 x i32> %8 to <4 x i64>
+  %10 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %9, <2 x i64> %3)
+  %11 = bitcast <4 x i64> %10 to <16 x i16>
+  %12 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %11, i32 %S)
+  %13 = bitcast <16 x i16> %12 to <8 x i32>
+  %14 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %13, i32 %S)
+  %15 = bitcast <8 x i32> %14 to <4 x i64>
+  %16 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %15, i32 %S)
+  ret <4 x i64> %16
+}
+
+define <2 x i64> @test_sse2_psrl_0() {
+; CHECK-LABEL: @test_sse2_psrl_0(
+; CHECK-NEXT:    ret <2 x i64> zeroinitializer
+;
+  %S = bitcast i32 128 to i32
+  %1 = zext i32 %S to i64
+  %2 = insertelement <2 x i64> poison, i64 %1, i32 0
+  %3 = insertelement <2 x i64> %2, i64 0, i32 1
+  %4 = bitcast <2 x i64> %3 to <8 x i16>
+  %5 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> <i16 32, i16 64, i16 128, i16 256, i16 512, i16 1024, i16 2048, i16 4096>, <8 x i16> %4)
+  %6 = bitcast <8 x i16> %5 to <4 x i32>
+  %7 = bitcast <2 x i64> %3 to <4 x i32>
+  %8 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %6, <4 x i32> %7)
+  %9 = bitcast <4 x i32> %8 to <2 x i64>
+  %10 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %9, <2 x i64> %3)
+  %11 = bitcast <2 x i64> %10 to <8 x i16>
+  %12 = tail call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %11, i32 %S)
+  %13 = bitcast <8 x i16> %12 to <4 x i32>
+  %14 = tail call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %13, i32 %S)
+  %15 = bitcast <4 x i32> %14 to <2 x i64>
+  %16 = tail call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %15, i32 %S)
+  ret <2 x i64> %16
+}
+
+define <4 x i64> @test_avx2_psrl_0() {
+; CHECK-LABEL: @test_avx2_psrl_0(
+; CHECK-NEXT:    ret <4 x i64> zeroinitializer
+;
+  %S = bitcast i32 128 to i32
+  %1 = zext i32 %S to i64
+  %2 = insertelement <2 x i64> poison, i64 %1, i32 0
+  %3 = insertelement <2 x i64> %2, i64 0, i32 1
+  %4 = bitcast <2 x i64> %3 to <8 x i16>
+  %5 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> <i16 1024, i16 0, i16 0, i16 0, i16 2048, i16 0, i16 0, i16 0, i16 4096, i16 0, i16 0, i16 0, i16 8192, i16 0, i16 0, i16 0>, <8 x i16> %4)
+  %6 = bitcast <16 x i16> %5 to <8 x i32>
+  %7 = bitcast <2 x i64> %3 to <4 x i32>
+  %8 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %6, <4 x i32> %7)
+  %9 = bitcast <8 x i32> %8 to <4 x i64>
+  %10 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %9, <2 x i64> %3)
+  %11 = bitcast <4 x i64> %10 to <16 x i16>
+  %12 = tail call <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16> %11, i32 %S)
+  %13 = bitcast <16 x i16> %12 to <8 x i32>
+  %14 = tail call <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32> %13, i32 %S)
+  %15 = bitcast <8 x i32> %14 to <4 x i64>
+  %16 = tail call <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64> %15, i32 %S)
+  ret <4 x i64> %16
+}
+
+declare <8 x i64> @llvm.x86.avx512.pslli.q.512(<8 x i64>, i32) #1
+declare <16 x i32> @llvm.x86.avx512.pslli.d.512(<16 x i32>, i32) #1
+declare <32 x i16> @llvm.x86.avx512.pslli.w.512(<32 x i16>, i32) #1
+declare <8 x i64> @llvm.x86.avx512.psll.q.512(<8 x i64>, <2 x i64>) #1
+declare <16 x i32> @llvm.x86.avx512.psll.d.512(<16 x i32>, <4 x i32>) #1
+declare <32 x i16> @llvm.x86.avx512.psll.w.512(<32 x i16>, <8 x i16>) #1
+declare <4 x i64> @llvm.x86.avx2.pslli.q(<4 x i64>, i32) #1
+declare <8 x i32> @llvm.x86.avx2.pslli.d(<8 x i32>, i32) #1
+declare <16 x i16> @llvm.x86.avx2.pslli.w(<16 x i16>, i32) #1
+declare <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64>, <2 x i64>) #1
+declare <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32>, <4 x i32>) #1
+declare <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16>, <8 x i16>) #1
+declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) #1
+declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) #1
+declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) #1
+declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) #1
+declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) #1
+declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) #1
+
+declare <8 x i64> @llvm.x86.avx512.psrli.q.512(<8 x i64>, i32) #1
+declare <16 x i32> @llvm.x86.avx512.psrli.d.512(<16 x i32>, i32) #1
+declare <32 x i16> @llvm.x86.avx512.psrli.w.512(<32 x i16>, i32) #1
+declare <8 x i64> @llvm.x86.avx512.psrl.q.512(<8 x i64>, <2 x i64>) #1
+declare <16 x i32> @llvm.x86.avx512.psrl.d.512(<16 x i32>, <4 x i32>) #1
+declare <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16>, <8 x i16>) #1
+declare <4 x i64> @llvm.x86.avx2.psrli.q(<4 x i64>, i32) #1
+declare <8 x i32> @llvm.x86.avx2.psrli.d(<8 x i32>, i32) #1
+declare <16 x i16> @llvm.x86.avx2.psrli.w(<16 x i16>, i32) #1
+declare <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64>, <2 x i64>) #1
+declare <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32>, <4 x i32>) #1
+declare <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16>, <8 x i16>) #1
+declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) #1
+declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) #1
+declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) #1
+declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) #1
+declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) #1
+declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) #1
+
+declare <8 x i64> @llvm.x86.avx512.psrai.q.512(<8 x i64>, i32) #1
+declare <16 x i32> @llvm.x86.avx512.psrai.d.512(<16 x i32>, i32) #1
+declare <32 x i16> @llvm.x86.avx512.psrai.w.512(<32 x i16>, i32) #1
+declare <8 x i64> @llvm.x86.avx512.psra.q.512(<8 x i64>, <2 x i64>) #1
+declare <16 x i32> @llvm.x86.avx512.psra.d.512(<16 x i32>, <4 x i32>) #1
+declare <32 x i16> @llvm.x86.avx512.psra.w.512(<32 x i16>, <8 x i16>) #1
+declare <4 x i64> @llvm.x86.avx512.psrai.q.256(<4 x i64>, i32) #1
+declare <8 x i32> @llvm.x86.avx2.psrai.d(<8 x i32>, i32) #1
+declare <16 x i16> @llvm.x86.avx2.psrai.w(<16 x i16>, i32) #1
+declare <4 x i64> @llvm.x86.avx512.psra.q.256(<4 x i64>, <2 x i64>) #1
+declare <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32>, <4 x i32>) #1
+declare <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16>, <8 x i16>) #1
+declare <2 x i64> @llvm.x86.avx512.psrai.q.128(<2 x i64>, i32) #1
+declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) #1
+declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) #1
+declare <2 x i64> @llvm.x86.avx512.psra.q.128(<2 x i64>, <2 x i64>) #1
+declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) #1
+declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) #1
+
+declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) #1
+declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) #1
+declare <16 x i32> @llvm.x86.avx512.psrav.d.512(<16 x i32>, <16 x i32>) #1
+declare <2 x i64> @llvm.x86.avx512.psrav.q.128(<2 x i64>, <2 x i64>) #1
+declare <4 x i64> @llvm.x86.avx512.psrav.q.256(<4 x i64>, <4 x i64>) #1
+declare <8 x i64> @llvm.x86.avx512.psrav.q.512(<8 x i64>, <8 x i64>) #1
+
+declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) #1
+declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) #1
+declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) #1
+declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) #1
+declare <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32>, <16 x i32>) #1
+declare <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64>, <8 x i64>) #1
+
+declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>) #1
+declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) #1
+declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) #1
+declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) #1
+declare <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32>, <16 x i32>) #1
+declare <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64>, <8 x i64>) #1
+
+declare <8 x i16> @llvm.x86.avx512.psrav.w.128(<8 x i16>, <8 x i16>) #1
+declare <16 x i16> @llvm.x86.avx512.psrav.w.256(<16 x i16>, <16 x i16>) #1
+declare <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16>, <32 x i16>) #1
+declare <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16>, <8 x i16>) #1
+declare <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16>, <16 x i16>) #1
+declare <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16>, <32 x i16>) #1
+declare <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16>, <8 x i16>) #1
+declare <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16>, <16 x i16>) #1
+declare <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16>, <32 x i16>) #1
+
+attributes #1 = { nounwind readnone }
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll b/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
index de67b1868b10e..dc9844fc01625 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll
@@ -2680,7 +2680,7 @@ define <32 x i16> @avx512_psllv_w_512_undef(<32 x i16> %v) {
 
 define <8 x i16> @sse2_psra_w_128_masked(<8 x i16> %v, <8 x i16> %a) {
 ; CHECK-LABEL: @sse2_psra_w_128_masked(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], <i16 15, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], <i16 15, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = ashr <8 x i16> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
@@ -2692,7 +2692,7 @@ define <8 x i16> @sse2_psra_w_128_masked(<8 x i16> %v, <8 x i16> %a) {
 
 define <8 x i32> @avx2_psra_d_256_masked(<8 x i32> %v, <4 x i32> %a) {
 ; CHECK-LABEL: @avx2_psra_d_256_masked(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 poison, i32 poison, i32 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <8 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = ashr <8 x i32> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <8 x i32> [[TMP3]]
@@ -2704,7 +2704,7 @@ define <8 x i32> @avx2_psra_d_256_masked(<8 x i32> %v, <4 x i32> %a) {
 
 define <8 x i64> @avx512_psra_q_512_masked(<8 x i64> %v, <2 x i64> %a) {
 ; CHECK-LABEL: @avx512_psra_q_512_masked(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 63, i64 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 63, i64 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> undef, <8 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = ashr <8 x i64> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <8 x i64> [[TMP3]]
@@ -2716,7 +2716,7 @@ define <8 x i64> @avx512_psra_q_512_masked(<8 x i64> %v, <2 x i64> %a) {
 
 define <4 x i32> @sse2_psrl_d_128_masked(<4 x i32> %v, <4 x i32> %a) {
 ; CHECK-LABEL: @sse2_psrl_d_128_masked(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 poison, i32 poison, i32 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = lshr <4 x i32> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
@@ -2728,7 +2728,7 @@ define <4 x i32> @sse2_psrl_d_128_masked(<4 x i32> %v, <4 x i32> %a) {
 
 define <4 x i64> @avx2_psrl_q_256_masked(<4 x i64> %v, <2 x i64> %a) {
 ; CHECK-LABEL: @avx2_psrl_q_256_masked(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 63, i64 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 63, i64 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> undef, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = lshr <4 x i64> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <4 x i64> [[TMP3]]
@@ -2740,7 +2740,7 @@ define <4 x i64> @avx2_psrl_q_256_masked(<4 x i64> %v, <2 x i64> %a) {
 
 define <32 x i16> @avx512_psrl_w_512_masked(<32 x i16> %v, <8 x i16> %a) {
 ; CHECK-LABEL: @avx512_psrl_w_512_masked(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], <i16 15, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], <i16 15, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <32 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = lshr <32 x i16> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <32 x i16> [[TMP3]]
@@ -2752,7 +2752,7 @@ define <32 x i16> @avx512_psrl_w_512_masked(<32 x i16> %v, <8 x i16> %a) {
 
 define <2 x i64> @sse2_psll_q_128_masked(<2 x i64> %v, <2 x i64> %a) {
 ; CHECK-LABEL: @sse2_psll_q_128_masked(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 63, i64 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[A:%.*]], <i64 63, i64 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl <2 x i64> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
@@ -2764,7 +2764,7 @@ define <2 x i64> @sse2_psll_q_128_masked(<2 x i64> %v, <2 x i64> %a) {
 
 define <16 x i16> @avx2_psll_w_256_masked(<16 x i16> %v, <8 x i16> %a) {
 ; CHECK-LABEL: @avx2_psll_w_256_masked(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], <i16 15, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], <i16 15, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <16 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl <16 x i16> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <16 x i16> [[TMP3]]
@@ -2776,7 +2776,7 @@ define <16 x i16> @avx2_psll_w_256_masked(<16 x i16> %v, <8 x i16> %a) {
 
 define <16 x i32> @avx512_psll_d_512_masked(<16 x i32> %v, <4 x i32> %a) {
 ; CHECK-LABEL: @avx512_psll_d_512_masked(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 31, i32 poison, i32 poison, i32 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <16 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl <16 x i32> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <16 x i32> [[TMP3]]
@@ -2922,7 +2922,7 @@ define <4 x i32> @avx2_psrav_d_128_masked(<4 x i32> %v, <4 x i32> %a) {
 
 define <4 x i32> @avx2_psrav_d_128_masked_shuffle(<4 x i32> %v, <4 x i32> %a) {
 ; CHECK-LABEL: @avx2_psrav_d_128_masked_shuffle(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 undef, i32 undef, i32 15, i32 31>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 poison, i32 poison, i32 15, i32 31>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
 ; CHECK-NEXT:    [[TMP3:%.*]] = ashr <4 x i32> [[V:%.*]], [[TMP2]]
 ; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll b/llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
index b227b83fee9b8..409c0889e49b5 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll
@@ -281,7 +281,7 @@ define <4 x double> @elts_test_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> %a1
 
 define <8 x double> @elts_test_vpermilvar_pd_512(<8 x double> %a0, <8 x i64> %a1, i64 %a2) {
 ; CHECK-LABEL: @elts_test_vpermilvar_pd_512(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <8 x i64> undef, i64 [[A2:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <8 x i64> poison, i64 [[A2:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> [[A0:%.*]], <8 x i64> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <8 x double> [[TMP2]], <8 x double> undef, <8 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <8 x double> [[TMP3]]
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-xop-inseltpoison.ll b/llvm/test/Transforms/InstCombine/X86/x86-xop-inseltpoison.ll
new file mode 100644
index 0000000000000..6d2b6d9b6ebdb
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/X86/x86-xop-inseltpoison.ll
@@ -0,0 +1,305 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
+
+define <2 x double> @test_vfrcz_sd(<2 x double> %a) {
+; CHECK-LABEL: @test_vfrcz_sd(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[A:%.*]])
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %1 = insertelement <2 x double> %a, double 1.000000e+00, i32 1
+  %2 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %1)
+  ret <2 x double> %2
+}
+
+define double @test_vfrcz_sd_0(double %a) {
+; CHECK-LABEL: @test_vfrcz_sd_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
+; CHECK-NEXT:    ret double [[TMP3]]
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2)
+  %4 = extractelement <2 x double> %3, i32 0
+  ret double %4
+}
+
+define double @test_vfrcz_sd_1(double %a) {
+; CHECK-LABEL: @test_vfrcz_sd_1(
+; CHECK-NEXT:    ret double 0.000000e+00
+;
+  %1 = insertelement <2 x double> poison, double %a, i32 0
+  %2 = insertelement <2 x double> %1, double 1.000000e+00, i32 1
+  %3 = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> %2)
+  %4 = extractelement <2 x double> %3, i32 1
+  ret double %4
+}
+
+define <4 x float> @test_vfrcz_ss(<4 x float> %a) {
+; CHECK-LABEL: @test_vfrcz_ss(
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[A:%.*]])
+; CHECK-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %1 = insertelement <4 x float> %a, float 1.000000e+00, i32 1
+  %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
+  %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
+  %4 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %3)
+  ret <4 x float> %4
+}
+
+define float @test_vfrcz_ss_0(float %a) {
+; CHECK-LABEL: @test_vfrcz_ss_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[TMP1]])
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    ret float [[TMP3]]
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 0
+  ret float %6
+}
+
+define float @test_vfrcz_ss_3(float %a) {
+; CHECK-LABEL: @test_vfrcz_ss_3(
+; CHECK-NEXT:    ret float 0.000000e+00
+;
+  %1 = insertelement <4 x float> poison, float %a, i32 0
+  %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
+  %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
+  %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
+  %5 = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> %4)
+  %6 = extractelement <4 x float> %5, i32 3
+  ret float %6
+}
+
+define <2 x i64> @cmp_slt_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @cmp_slt_v2i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i64> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.xop.vpcomltq(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @cmp_ult_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @cmp_ult_v2i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult <2 x i64> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.xop.vpcomltuq(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @cmp_sle_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @cmp_sle_v2i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sle <2 x i64> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.xop.vpcomleq(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %1
+}
+
+define <2 x i64> @cmp_ule_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @cmp_ule_v2i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ule <2 x i64> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <2 x i1> [[TMP1]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+;
+  %1 = tail call <2 x i64> @llvm.x86.xop.vpcomleuq(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x i64> %1
+}
+
+define <4 x i32> @cmp_sgt_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @cmp_sgt_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.xop.vpcomgtd(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @cmp_ugt_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @cmp_ugt_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <4 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.xop.vpcomgtud(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @cmp_sge_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @cmp_sge_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sge <4 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.xop.vpcomged(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %1
+}
+
+define <4 x i32> @cmp_uge_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @cmp_uge_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp uge <4 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
+;
+  %1 = tail call <4 x i32> @llvm.x86.xop.vpcomgeud(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x i32> %1
+}
+
+define <8 x i16> @cmp_seq_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: @cmp_seq_v8i16(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <8 x i16> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
+; CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.xop.vpcomeqw(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @cmp_ueq_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: @cmp_ueq_v8i16(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <8 x i16> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
+; CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.xop.vpcomequw(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @cmp_sne_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: @cmp_sne_v8i16(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <8 x i16> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
+; CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.xop.vpcomnew(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %1
+}
+
+define <8 x i16> @cmp_une_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: @cmp_une_v8i16(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <8 x i16> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext <8 x i1> [[TMP1]] to <8 x i16>
+; CHECK-NEXT:    ret <8 x i16> [[TMP2]]
+;
+  %1 = tail call <8 x i16> @llvm.x86.xop.vpcomneuw(<8 x i16> %a, <8 x i16> %b)
+  ret <8 x i16> %1
+}
+
+define <16 x i8> @cmp_strue_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: @cmp_strue_v16i8(
+; CHECK-NEXT:    ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+;
+  %1 = tail call <16 x i8> @llvm.x86.xop.vpcomtrueb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %1
+}
+
+define <16 x i8> @cmp_utrue_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: @cmp_utrue_v16i8(
+; CHECK-NEXT:    ret <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
+;
+  %1 = tail call <16 x i8> @llvm.x86.xop.vpcomtrueub(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %1
+}
+
+define <16 x i8> @cmp_sfalse_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: @cmp_sfalse_v16i8(
+; CHECK-NEXT:    ret <16 x i8> zeroinitializer
+;
+  %1 = tail call <16 x i8> @llvm.x86.xop.vpcomfalseb(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %1
+}
+
+define <16 x i8> @cmp_ufalse_v16i8(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: @cmp_ufalse_v16i8(
+; CHECK-NEXT:    ret <16 x i8> zeroinitializer
+;
+  %1 = tail call <16 x i8> @llvm.x86.xop.vpcomfalseub(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %1
+}
+
+declare <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double>) nounwind readnone
+declare <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float>) nounwind readnone
+
+declare <16 x i8> @llvm.x86.xop.vpcomltb(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomltw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomltd(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomltq(<2 x i64>, <2 x i64>) nounwind readnone
+declare <16 x i8> @llvm.x86.xop.vpcomltub(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomltuw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomltud(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomltuq(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.x86.xop.vpcomleb(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomlew(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomled(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomleq(<2 x i64>, <2 x i64>) nounwind readnone
+declare <16 x i8> @llvm.x86.xop.vpcomleub(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomleuw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomleud(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomleuq(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.x86.xop.vpcomgtb(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomgtw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomgtd(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomgtq(<2 x i64>, <2 x i64>) nounwind readnone
+declare <16 x i8> @llvm.x86.xop.vpcomgtub(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomgtuw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomgtud(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomgtuq(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.x86.xop.vpcomgeb(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomgew(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomged(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomgeq(<2 x i64>, <2 x i64>) nounwind readnone
+declare <16 x i8> @llvm.x86.xop.vpcomgeub(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomgeuw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomgeud(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomgeuq(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.x86.xop.vpcomeqb(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomeqw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomeqd(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomeqq(<2 x i64>, <2 x i64>) nounwind readnone
+declare <16 x i8> @llvm.x86.xop.vpcomequb(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomequw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomequd(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomequq(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.x86.xop.vpcomneb(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomnew(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomned(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomneq(<2 x i64>, <2 x i64>) nounwind readnone
+declare <16 x i8> @llvm.x86.xop.vpcomneub(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomneuw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomneud(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomneuq(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.x86.xop.vpcomfalseb(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomfalsew(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomfalsed(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomfalseq(<2 x i64>, <2 x i64>) nounwind readnone
+declare <16 x i8> @llvm.x86.xop.vpcomfalseub(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomfalseuw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomfalseud(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomfalseuq(<2 x i64>, <2 x i64>) nounwind readnone
+
+declare <16 x i8> @llvm.x86.xop.vpcomtrueb(<16 x i8>, <16 x i8>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomtrued(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomtrueq(<2 x i64>, <2 x i64>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomtruew(<8 x i16>, <8 x i16>) nounwind readnone
+declare <16 x i8> @llvm.x86.xop.vpcomtrueub(<16 x i8>, <16 x i8>) nounwind readnone
+declare <8 x i16> @llvm.x86.xop.vpcomtrueuw(<8 x i16>, <8 x i16>) nounwind readnone
+declare <4 x i32> @llvm.x86.xop.vpcomtrueud(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.xop.vpcomtrueuq(<2 x i64>, <2 x i64>) nounwind readnone
diff --git a/llvm/test/Transforms/InstCombine/X86/x86-xop.ll b/llvm/test/Transforms/InstCombine/X86/x86-xop.ll
index bef9861ea6d91..616c7f6b33abd 100644
--- a/llvm/test/Transforms/InstCombine/X86/x86-xop.ll
+++ b/llvm/test/Transforms/InstCombine/X86/x86-xop.ll
@@ -13,7 +13,7 @@ define <2 x double> @test_vfrcz_sd(<2 x double> %a) {
 
 define double @test_vfrcz_sd_0(double %a) {
 ; CHECK-LABEL: @test_vfrcz_sd_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <2 x double> @llvm.x86.xop.vfrcz.sd(<2 x double> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret double [[TMP3]]
@@ -50,7 +50,7 @@ define <4 x float> @test_vfrcz_ss(<4 x float> %a) {
 
 define float @test_vfrcz_ss_0(float %a) {
 ; CHECK-LABEL: @test_vfrcz_ss_0(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.xop.vfrcz.ss(<4 x float> [[TMP1]])
 ; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
 ; CHECK-NEXT:    ret float [[TMP3]]
diff --git a/llvm/test/Transforms/InstCombine/abs-1.ll b/llvm/test/Transforms/InstCombine/abs-1.ll
index fbc0fc1a835c3..7e5eadf5b25e4 100644
--- a/llvm/test/Transforms/InstCombine/abs-1.ll
+++ b/llvm/test/Transforms/InstCombine/abs-1.ll
@@ -226,8 +226,8 @@ define <2 x i8> @nabs_canonical_2_vec_undef_elts(<2 x i8> %x) {
 
 define i8 @nabs_canonical_3(i8 %x) {
 ; CHECK-LABEL: @nabs_canonical_3(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[ABS:%.*]] = sub nsw i8 0, [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i8 @llvm.abs.i8(i8 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[ABS:%.*]] = sub i8 0, [[TMP1]]
 ; CHECK-NEXT:    ret i8 [[ABS]]
 ;
   %cmp = icmp slt i8 %x, 0
@@ -251,7 +251,7 @@ define i8 @nabs_canonical_4(i8 %x) {
 define i32 @nabs_canonical_5(i8 %x) {
 ; CHECK-LABEL: @nabs_canonical_5(
 ; CHECK-NEXT:    [[CONV:%.*]] = sext i8 [[X:%.*]] to i32
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[CONV]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[CONV]], i1 false)
 ; CHECK-NEXT:    [[ABS:%.*]] = sub nsw i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[ABS]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/abs_abs.ll b/llvm/test/Transforms/InstCombine/abs_abs.ll
index f2faf35a25155..cb0118261bb62 100644
--- a/llvm/test/Transforms/InstCombine/abs_abs.ll
+++ b/llvm/test/Transforms/InstCombine/abs_abs.ll
@@ -319,9 +319,9 @@ define <2 x i32> @abs_abs_x03_vec(<2 x i32> %x, <2 x i32> %y) {
 
 define i32 @nabs_nabs_x01(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x01(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
@@ -334,9 +334,9 @@ define i32 @nabs_nabs_x01(i32 %x) {
 
 define i32 @nabs_nabs_x02(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x02(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
@@ -349,9 +349,9 @@ define i32 @nabs_nabs_x02(i32 %x) {
 
 define i32 @nabs_nabs_x03(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x03(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
@@ -364,9 +364,9 @@ define i32 @nabs_nabs_x03(i32 %x) {
 
 define i32 @nabs_nabs_x04(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x04(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
@@ -379,9 +379,9 @@ define i32 @nabs_nabs_x04(i32 %x) {
 
 define i32 @nabs_nabs_x05(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x05(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
@@ -394,9 +394,9 @@ define i32 @nabs_nabs_x05(i32 %x) {
 
 define i32 @nabs_nabs_x06(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x06(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
@@ -409,9 +409,9 @@ define i32 @nabs_nabs_x06(i32 %x) {
 
 define i32 @nabs_nabs_x07(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x07(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
@@ -424,9 +424,9 @@ define i32 @nabs_nabs_x07(i32 %x) {
 
 define i32 @nabs_nabs_x08(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x08(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
@@ -439,9 +439,9 @@ define i32 @nabs_nabs_x08(i32 %x) {
 
 define i32 @nabs_nabs_x09(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x09(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
@@ -454,9 +454,9 @@ define i32 @nabs_nabs_x09(i32 %x) {
 
 define i32 @nabs_nabs_x10(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x10(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
@@ -469,9 +469,9 @@ define i32 @nabs_nabs_x10(i32 %x) {
 
 define i32 @nabs_nabs_x11(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x11(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
@@ -484,9 +484,9 @@ define i32 @nabs_nabs_x11(i32 %x) {
 
 define i32 @nabs_nabs_x12(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x12(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
@@ -499,9 +499,9 @@ define i32 @nabs_nabs_x12(i32 %x) {
 
 define i32 @nabs_nabs_x13(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x13(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp sgt i32 %x, -1
   %sub = sub nsw i32 0, %x
@@ -514,9 +514,9 @@ define i32 @nabs_nabs_x13(i32 %x) {
 
 define i32 @nabs_nabs_x14(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x14(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp sgt i32 %x, 0
   %sub = sub nsw i32 0, %x
@@ -529,9 +529,9 @@ define i32 @nabs_nabs_x14(i32 %x) {
 
 define i32 @nabs_nabs_x15(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x15(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp slt i32 %x, 0
   %sub = sub nsw i32 0, %x
@@ -544,9 +544,9 @@ define i32 @nabs_nabs_x15(i32 %x) {
 
 define i32 @nabs_nabs_x16(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x16(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %cmp = icmp slt i32 %x, 1
   %sub = sub nsw i32 0, %x
@@ -560,9 +560,9 @@ define i32 @nabs_nabs_x16(i32 %x) {
 ; nabs(nabs(-x)) -> nabs(-x) -> nabs(x)
 define i32 @nabs_nabs_x17(i32 %x) {
 ; CHECK-LABEL: @nabs_nabs_x17(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw i32 0, [[TMP1]]
-; CHECK-NEXT:    ret i32 [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
+; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %sub = sub nsw i32 0, %x
   %cmp = icmp sgt i32 %sub, -1
@@ -594,9 +594,9 @@ define i32 @nabs_nabs_x18(i32 %x, i32 %y) {
 ; nabs(nabs(-x)) -> nabs(-x) -> nabs(x)
 define <2 x i32> @nabs_nabs_x01_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @nabs_nabs_x01_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
-; CHECK-NEXT:    [[COND:%.*]] = sub nsw <2 x i32> zeroinitializer, [[TMP1]]
-; CHECK-NEXT:    ret <2 x i32> [[COND]]
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 false)
+; CHECK-NEXT:    [[COND18:%.*]] = sub <2 x i32> zeroinitializer, [[TMP1]]
+; CHECK-NEXT:    ret <2 x i32> [[COND18]]
 ;
   %sub = sub nsw <2 x i32> zeroinitializer, %x
   %cmp = icmp sgt <2 x i32> %sub, <i32 -1, i32 -1>
@@ -627,7 +627,7 @@ define <2 x i32> @nabs_nabs_x02_vec(<2 x i32> %x, <2 x i32> %y) {
 
 define i32 @abs_nabs_x01(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x01(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
@@ -641,7 +641,7 @@ define i32 @abs_nabs_x01(i32 %x) {
 
 define i32 @abs_nabs_x02(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x02(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
@@ -655,7 +655,7 @@ define i32 @abs_nabs_x02(i32 %x) {
 
 define i32 @abs_nabs_x03(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x03(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
@@ -669,7 +669,7 @@ define i32 @abs_nabs_x03(i32 %x) {
 
 define i32 @abs_nabs_x04(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x04(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
@@ -683,7 +683,7 @@ define i32 @abs_nabs_x04(i32 %x) {
 
 define i32 @abs_nabs_x05(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x05(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
@@ -697,7 +697,7 @@ define i32 @abs_nabs_x05(i32 %x) {
 
 define i32 @abs_nabs_x06(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x06(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
@@ -711,7 +711,7 @@ define i32 @abs_nabs_x06(i32 %x) {
 
 define i32 @abs_nabs_x07(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x07(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
@@ -725,7 +725,7 @@ define i32 @abs_nabs_x07(i32 %x) {
 
 define i32 @abs_nabs_x08(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x08(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
@@ -739,7 +739,7 @@ define i32 @abs_nabs_x08(i32 %x) {
 
 define i32 @abs_nabs_x09(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x09(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
@@ -753,7 +753,7 @@ define i32 @abs_nabs_x09(i32 %x) {
 
 define i32 @abs_nabs_x10(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x10(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
@@ -767,7 +767,7 @@ define i32 @abs_nabs_x10(i32 %x) {
 
 define i32 @abs_nabs_x11(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x11(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
@@ -781,7 +781,7 @@ define i32 @abs_nabs_x11(i32 %x) {
 
 define i32 @abs_nabs_x12(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x12(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
@@ -795,7 +795,7 @@ define i32 @abs_nabs_x12(i32 %x) {
 
 define i32 @abs_nabs_x13(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x13(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
@@ -809,7 +809,7 @@ define i32 @abs_nabs_x13(i32 %x) {
 
 define i32 @abs_nabs_x14(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x14(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, 0
@@ -823,7 +823,7 @@ define i32 @abs_nabs_x14(i32 %x) {
 
 define i32 @abs_nabs_x15(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x15(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 0
@@ -837,7 +837,7 @@ define i32 @abs_nabs_x15(i32 %x) {
 
 define i32 @abs_nabs_x16(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x16(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp slt i32 %x, 1
@@ -852,7 +852,7 @@ define i32 @abs_nabs_x16(i32 %x) {
 ; abs(nabs(-x)) -> abs(-x) -> abs(x)
 define i32 @abs_nabs_x17(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x17(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %sub = sub nsw i32 0, %x
@@ -884,7 +884,7 @@ define i32 @abs_nabs_x18(i32 %x, i32 %y) {
 ; abs(nabs(-x)) -> abs(-x) -> abs(x)
 define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @abs_nabs_x01_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %sub = sub nsw <2 x i32> zeroinitializer, %x
@@ -1174,7 +1174,7 @@ define i32 @nabs_abs_x18(i32 %x, i32 %y) {
 ; CHECK-LABEL: @nabs_abs_x18(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[A]], i1 false)
-; CHECK-NEXT:    [[COND18:%.*]] = sub nsw i32 0, [[TMP1]]
+; CHECK-NEXT:    [[COND18:%.*]] = sub i32 0, [[TMP1]]
 ; CHECK-NEXT:    ret i32 [[COND18]]
 ;
   %a = sub nsw i32 %x, %y
@@ -1208,7 +1208,7 @@ define <2 x i32> @nabs_abs_x02_vec(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @nabs_abs_x02_vec(
 ; CHECK-NEXT:    [[A:%.*]] = sub nsw <2 x i32> [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[A]], i1 false)
-; CHECK-NEXT:    [[COND18:%.*]] = sub nsw <2 x i32> zeroinitializer, [[TMP1]]
+; CHECK-NEXT:    [[COND18:%.*]] = sub <2 x i32> zeroinitializer, [[TMP1]]
 ; CHECK-NEXT:    ret <2 x i32> [[COND18]]
 ;
   %a = sub nsw <2 x i32> %x, %y
diff --git a/llvm/test/Transforms/InstCombine/and-xor-or.ll b/llvm/test/Transforms/InstCombine/and-xor-or.ll
index 6e54c5318d216..4cb88d0766bae 100644
--- a/llvm/test/Transforms/InstCombine/and-xor-or.ll
+++ b/llvm/test/Transforms/InstCombine/and-xor-or.ll
@@ -96,6 +96,49 @@ define i32 @and_xor_not_common_op(i32 %a, i32 %b) {
   ret i32 %t4
 }
 
+; a & (a ^ ~b) --> a & b
+
+define i32 @and_xor_not_common_op_extrause(i32 %a, i32 %b, i32* %dst) {
+; CHECK-LABEL: @and_xor_not_common_op_extrause(
+; CHECK-NEXT:    [[B2:%.*]] = xor i32 [[B:%.*]], -1
+; CHECK-NEXT:    store i32 [[B2]], i32* [[DST:%.*]], align 4
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[A:%.*]], [[B]]
+; CHECK-NEXT:    ret i32 [[T4]]
+;
+  %b2 = xor i32 %b, -1
+  store i32 %b2, i32* %dst
+  %t2 = xor i32 %a, %b2
+  %t4 = and i32 %t2, %a
+  ret i32 %t4
+}
+
+; a & ~(a ^ b) --> a & b
+
+define i32 @and_not_xor_common_op(i32 %a, i32 %b) {
+; CHECK-LABEL: @and_not_xor_common_op(
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret i32 [[T4]]
+;
+  %b2 = xor i32 %b, %a
+  %t2 = xor i32 %b2, -1
+  %t4 = and i32 %t2, %a
+  ret i32 %t4
+}
+
+declare i32 @gen32()
+define i32 @and_not_xor_common_op_commutative(i32 %b) {
+; CHECK-LABEL: @and_not_xor_common_op_commutative(
+; CHECK-NEXT:    [[A:%.*]] = call i32 @gen32()
+; CHECK-NEXT:    [[T4:%.*]] = and i32 [[A]], [[B:%.*]]
+; CHECK-NEXT:    ret i32 [[T4]]
+;
+  %a = call i32 @gen32()
+  %b2 = xor i32 %a, %b ; swapped order
+  %t2 = xor i32 %b2, -1
+  %t4 = and i32 %a, %t2 ; swapped order
+  ret i32 %t4
+}
+
 ; rdar://10770603
 ; (x & y) | (x ^ y) -> x | y
 
diff --git a/llvm/test/Transforms/InstCombine/bitcast-bigendian.ll b/llvm/test/Transforms/InstCombine/bitcast-bigendian.ll
index 0001fab8c16ae..9a672ed0c1621 100644
--- a/llvm/test/Transforms/InstCombine/bitcast-bigendian.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast-bigendian.ll
@@ -51,7 +51,7 @@ define float @test3(<2 x float> %A, <2 x i64> %B) {
 
 define <2 x i32> @test4(i32 %A, i32 %B){
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i32> undef, i32 [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[A:%.*]], i32 1
 ; CHECK-NEXT:    ret <2 x i32> [[TMP2]]
 ;
@@ -65,7 +65,7 @@ define <2 x i32> @test4(i32 %A, i32 %B){
 
 define <2 x float> @test5(float %A, float %B) {
 ; CHECK-LABEL: @test5(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> undef, float [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> poison, float [[B:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[A:%.*]], i32 1
 ; CHECK-NEXT:    ret <2 x float> [[TMP2]]
 ;
@@ -81,7 +81,7 @@ define <2 x float> @test5(float %A, float %B) {
 
 define <2 x float> @test6(float %A){
 ; CHECK-LABEL: @test6(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> <float undef, float 4.200000e+01>, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> <float poison, float 4.200000e+01>, float [[A:%.*]], i32 0
 ; CHECK-NEXT:    ret <2 x float> [[TMP1]]
 ;
   %tmp23 = bitcast float %A to i32
diff --git a/llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll b/llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll
new file mode 100644
index 0000000000000..fa31ab76f2a72
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/bitcast-inseltpoison.ll
@@ -0,0 +1,573 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin10.0.0"
+
+; Bitcasts between vectors and scalars are valid.
+; PR4487
+define i32 @test1(i64 %a) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    ret i32 0
+;
+  %t1 = bitcast i64 %a to <2 x i32>
+  %t2 = bitcast i64 %a to <2 x i32>
+  %t3 = xor <2 x i32> %t1, %t2
+  %t4 = extractelement <2 x i32> %t3, i32 0
+  ret i32 %t4
+}
+
+; Perform the bitwise logic in the source type of the operands to eliminate bitcasts.
+
+define <2 x i32> @xor_two_vector_bitcasts(<1 x i64> %a, <1 x i64> %b) {
+; CHECK-LABEL: @xor_two_vector_bitcasts(
+; CHECK-NEXT:    [[T31:%.*]] = xor <1 x i64> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[T3:%.*]] = bitcast <1 x i64> [[T31]] to <2 x i32>
+; CHECK-NEXT:    ret <2 x i32> [[T3]]
+;
+  %t1 = bitcast <1 x i64> %a to <2 x i32>
+  %t2 = bitcast <1 x i64> %b to <2 x i32>
+  %t3 = xor <2 x i32> %t1, %t2
+  ret <2 x i32> %t3
+}
+
+; No change. Bitcasts are canonicalized above bitwise logic.
+
+define <2 x i32> @xor_bitcast_vec_to_vec(<1 x i64> %a) {
+; CHECK-LABEL: @xor_bitcast_vec_to_vec(
+; CHECK-NEXT:    [[T1:%.*]] = bitcast <1 x i64> [[A:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[T2:%.*]] = xor <2 x i32> [[T1]], <i32 1, i32 2>
+; CHECK-NEXT:    ret <2 x i32> [[T2]]
+;
+  %t1 = bitcast <1 x i64> %a to <2 x i32>
+  %t2 = xor <2 x i32> <i32 1, i32 2>, %t1
+  ret <2 x i32> %t2
+}
+
+; No change. Bitcasts are canonicalized above bitwise logic.
+
+define i64 @and_bitcast_vec_to_int(<2 x i32> %a) {
+; CHECK-LABEL: @and_bitcast_vec_to_int(
+; CHECK-NEXT:    [[T1:%.*]] = bitcast <2 x i32> [[A:%.*]] to i64
+; CHECK-NEXT:    [[T2:%.*]] = and i64 [[T1]], 3
+; CHECK-NEXT:    ret i64 [[T2]]
+;
+  %t1 = bitcast <2 x i32> %a to i64
+  %t2 = and i64 %t1, 3
+  ret i64 %t2
+}
+
+; No change. Bitcasts are canonicalized above bitwise logic.
+
+define <2 x i32> @or_bitcast_int_to_vec(i64 %a) {
+; CHECK-LABEL: @or_bitcast_int_to_vec(
+; CHECK-NEXT:    [[T1:%.*]] = bitcast i64 [[A:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[T2:%.*]] = or <2 x i32> [[T1]], <i32 1, i32 2>
+; CHECK-NEXT:    ret <2 x i32> [[T2]]
+;
+  %t1 = bitcast i64 %a to <2 x i32>
+  %t2 = or <2 x i32> %t1, <i32 1, i32 2>
+  ret <2 x i32> %t2
+}
+
+; PR26702 - https://bugs.llvm.org//show_bug.cgi?id=26702
+; Bitcast is canonicalized above logic, so we can see the not-not pattern.
+
+define <2 x i64> @is_negative(<4 x i32> %x) {
+; CHECK-LABEL: @is_negative(
+; CHECK-NEXT:    [[LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x i32> [[LOBIT]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %lobit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+  %not = xor <4 x i32> %lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %bc = bitcast <4 x i32> %not to <2 x i64>
+  %notnot = xor <2 x i64> %bc, <i64 -1, i64 -1>
+  ret <2 x i64> %notnot
+}
+
+; This variation has an extra bitcast at the end. This means that the 2nd xor
+; can be done in <4 x i32> to eliminate a bitcast regardless of canonicalizaion.
+
+define <4 x i32> @is_negative_bonus_bitcast(<4 x i32> %x) {
+; CHECK-LABEL: @is_negative_bonus_bitcast(
+; CHECK-NEXT:    [[LOBIT:%.*]] = ashr <4 x i32> [[X:%.*]], <i32 31, i32 31, i32 31, i32 31>
+; CHECK-NEXT:    ret <4 x i32> [[LOBIT]]
+;
+  %lobit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+  %not = xor <4 x i32> %lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %bc = bitcast <4 x i32> %not to <2 x i64>
+  %notnot = xor <2 x i64> %bc, <i64 -1, i64 -1>
+  %bc2 = bitcast <2 x i64> %notnot to <4 x i32>
+  ret <4 x i32> %bc2
+}
+
+; Bitcasts are canonicalized above bitwise logic.
+
+define <2 x i8> @canonicalize_bitcast_logic_with_constant(<4 x i4> %x) {
+; CHECK-LABEL: @canonicalize_bitcast_logic_with_constant(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <4 x i4> [[X:%.*]] to <2 x i8>
+; CHECK-NEXT:    [[B:%.*]] = and <2 x i8> [[TMP1]], <i8 -128, i8 -128>
+; CHECK-NEXT:    ret <2 x i8> [[B]]
+;
+  %a = and <4 x i4> %x, <i4 0, i4 8, i4 0, i4 8>
+  %b = bitcast <4 x i4> %a to <2 x i8>
+  ret <2 x i8> %b
+}
+
+; PR27925 - https://llvm.org/bugs/show_bug.cgi?id=27925
+
+define <4 x i32> @bitcasts_and_bitcast(<4 x i32> %a, <8 x i16> %b) {
+; CHECK-LABEL: @bitcasts_and_bitcast(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x i16> [[B:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[BC3:%.*]] = and <4 x i32> [[TMP1]], [[A:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[BC3]]
+;
+  %bc1 = bitcast <4 x i32> %a to <2 x i64>
+  %bc2 = bitcast <8 x i16> %b to <2 x i64>
+  %and = and <2 x i64> %bc2, %bc1
+  %bc3 = bitcast <2 x i64> %and to <4 x i32>
+  ret <4 x i32> %bc3
+}
+
+; The destination must have an integer element type.
+; FIXME: We can still eliminate one bitcast in this test by doing the logic op
+; in the type of the input that has an integer element type.
+
+define <4 x float> @bitcasts_and_bitcast_to_fp(<4 x float> %a, <8 x i16> %b) {
+; CHECK-LABEL: @bitcasts_and_bitcast_to_fp(
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <4 x float> [[A:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[BC2:%.*]] = bitcast <8 x i16> [[B:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i64> [[BC2]], [[BC1]]
+; CHECK-NEXT:    [[BC3:%.*]] = bitcast <2 x i64> [[AND]] to <4 x float>
+; CHECK-NEXT:    ret <4 x float> [[BC3]]
+;
+  %bc1 = bitcast <4 x float> %a to <2 x i64>
+  %bc2 = bitcast <8 x i16> %b to <2 x i64>
+  %and = and <2 x i64> %bc2, %bc1
+  %bc3 = bitcast <2 x i64> %and to <4 x float>
+  ret <4 x float> %bc3
+}
+
+; FIXME: Transform limited from changing vector op to integer op to avoid codegen problems.
+
+define i128 @bitcast_or_bitcast(i128 %a, <2 x i64> %b) {
+; CHECK-LABEL: @bitcast_or_bitcast(
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast i128 [[A:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[OR:%.*]] = or <2 x i64> [[BC1]], [[B:%.*]]
+; CHECK-NEXT:    [[BC2:%.*]] = bitcast <2 x i64> [[OR]] to i128
+; CHECK-NEXT:    ret i128 [[BC2]]
+;
+  %bc1 = bitcast i128 %a to <2 x i64>
+  %or = or <2 x i64> %b, %bc1
+  %bc2 = bitcast <2 x i64> %or to i128
+  ret i128 %bc2
+}
+
+; FIXME: Transform limited from changing integer op to vector op to avoid codegen problems.
+
+define <4 x i32> @bitcast_xor_bitcast(<4 x i32> %a, i128 %b) {
+; CHECK-LABEL: @bitcast_xor_bitcast(
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <4 x i32> [[A:%.*]] to i128
+; CHECK-NEXT:    [[XOR:%.*]] = xor i128 [[BC1]], [[B:%.*]]
+; CHECK-NEXT:    [[BC2:%.*]] = bitcast i128 [[XOR]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[BC2]]
+;
+  %bc1 = bitcast <4 x i32> %a to i128
+  %xor = xor i128 %bc1, %b
+  %bc2 = bitcast i128 %xor to <4 x i32>
+  ret <4 x i32> %bc2
+}
+
+; https://llvm.org/bugs/show_bug.cgi?id=6137#c6
+
+define <4 x float> @bitcast_vector_select(<4 x float> %x, <2 x i64> %y, <4 x i1> %cmp) {
+; CHECK-LABEL: @bitcast_vector_select(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[Y:%.*]] to <4 x float>
+; CHECK-NEXT:    [[T7:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x float> [[X:%.*]], <4 x float> [[TMP1]]
+; CHECK-NEXT:    ret <4 x float> [[T7]]
+;
+  %t4 = bitcast <4 x float> %x to <4 x i32>
+  %t5 = bitcast <2 x i64> %y to <4 x i32>
+  %t6 = select <4 x i1> %cmp, <4 x i32> %t4, <4 x i32> %t5
+  %t7 = bitcast <4 x i32> %t6 to <4 x float>
+  ret <4 x float> %t7
+}
+
+define float @bitcast_scalar_select_of_scalars(float %x, i32 %y, i1 %cmp) {
+; CHECK-LABEL: @bitcast_scalar_select_of_scalars(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32 [[Y:%.*]] to float
+; CHECK-NEXT:    [[T7:%.*]] = select i1 [[CMP:%.*]], float [[X:%.*]], float [[TMP1]]
+; CHECK-NEXT:    ret float [[T7]]
+;
+  %t4 = bitcast float %x to i32
+  %t6 = select i1 %cmp, i32 %t4, i32 %y
+  %t7 = bitcast i32 %t6 to float
+  ret float %t7
+}
+
+; FIXME: We should change the select operand types to scalars, but we need to make
+; sure the backend can reverse that transform if needed.
+
+define float @bitcast_scalar_select_type_mismatch1(float %x, <4 x i8> %y, i1 %cmp) {
+; CHECK-LABEL: @bitcast_scalar_select_type_mismatch1(
+; CHECK-NEXT:    [[T4:%.*]] = bitcast float [[X:%.*]] to <4 x i8>
+; CHECK-NEXT:    [[T6:%.*]] = select i1 [[CMP:%.*]], <4 x i8> [[T4]], <4 x i8> [[Y:%.*]]
+; CHECK-NEXT:    [[T7:%.*]] = bitcast <4 x i8> [[T6]] to float
+; CHECK-NEXT:    ret float [[T7]]
+;
+  %t4 = bitcast float %x to <4 x i8>
+  %t6 = select i1 %cmp, <4 x i8> %t4, <4 x i8> %y
+  %t7 = bitcast <4 x i8> %t6 to float
+  ret float %t7
+}
+
+; FIXME: We should change the select operand types to vectors, but we need to make
+; sure the backend can reverse that transform if needed.
+
+define <4 x i8> @bitcast_scalar_select_type_mismatch2(<4 x i8> %x, float %y, i1 %cmp) {
+; CHECK-LABEL: @bitcast_scalar_select_type_mismatch2(
+; CHECK-NEXT:    [[T4:%.*]] = bitcast <4 x i8> [[X:%.*]] to float
+; CHECK-NEXT:    [[T6:%.*]] = select i1 [[CMP:%.*]], float [[T4]], float [[Y:%.*]]
+; CHECK-NEXT:    [[T7:%.*]] = bitcast float [[T6]] to <4 x i8>
+; CHECK-NEXT:    ret <4 x i8> [[T7]]
+;
+  %t4 = bitcast <4 x i8> %x to float
+  %t6 = select i1 %cmp, float %t4, float %y
+  %t7 = bitcast float %t6 to <4 x i8>
+  ret <4 x i8> %t7
+}
+
+define <4 x float> @bitcast_scalar_select_of_vectors(<4 x float> %x, <2 x i64> %y, i1 %cmp) {
+; CHECK-LABEL: @bitcast_scalar_select_of_vectors(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x i64> [[Y:%.*]] to <4 x float>
+; CHECK-NEXT:    [[T7:%.*]] = select i1 [[CMP:%.*]], <4 x float> [[X:%.*]], <4 x float> [[TMP1]]
+; CHECK-NEXT:    ret <4 x float> [[T7]]
+;
+  %t4 = bitcast <4 x float> %x to <4 x i32>
+  %t5 = bitcast <2 x i64> %y to <4 x i32>
+  %t6 = select i1 %cmp, <4 x i32> %t4, <4 x i32> %t5
+  %t7 = bitcast <4 x i32> %t6 to <4 x float>
+  ret <4 x float> %t7
+}
+
+; Can't change the type of the vector select if the dest type is scalar.
+
+define float @bitcast_vector_select_no_fold1(float %x, <2 x i16> %y, <4 x i1> %cmp) {
+; CHECK-LABEL: @bitcast_vector_select_no_fold1(
+; CHECK-NEXT:    [[T4:%.*]] = bitcast float [[X:%.*]] to <4 x i8>
+; CHECK-NEXT:    [[T5:%.*]] = bitcast <2 x i16> [[Y:%.*]] to <4 x i8>
+; CHECK-NEXT:    [[T6:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i8> [[T4]], <4 x i8> [[T5]]
+; CHECK-NEXT:    [[T7:%.*]] = bitcast <4 x i8> [[T6]] to float
+; CHECK-NEXT:    ret float [[T7]]
+;
+  %t4 = bitcast float %x to <4 x i8>
+  %t5 = bitcast <2 x i16> %y to <4 x i8>
+  %t6 = select <4 x i1> %cmp, <4 x i8> %t4, <4 x i8> %t5
+  %t7 = bitcast <4 x i8> %t6 to float
+  ret float %t7
+}
+
+; Can't change the type of the vector select if the number of elements in the dest type is not the same.
+
+define <2 x float> @bitcast_vector_select_no_fold2(<2 x float> %x, <4 x i16> %y, <8 x i1> %cmp) {
+; CHECK-LABEL: @bitcast_vector_select_no_fold2(
+; CHECK-NEXT:    [[T4:%.*]] = bitcast <2 x float> [[X:%.*]] to <8 x i8>
+; CHECK-NEXT:    [[T5:%.*]] = bitcast <4 x i16> [[Y:%.*]] to <8 x i8>
+; CHECK-NEXT:    [[T6:%.*]] = select <8 x i1> [[CMP:%.*]], <8 x i8> [[T4]], <8 x i8> [[T5]]
+; CHECK-NEXT:    [[T7:%.*]] = bitcast <8 x i8> [[T6]] to <2 x float>
+; CHECK-NEXT:    ret <2 x float> [[T7]]
+;
+  %t4 = bitcast <2 x float> %x to <8 x i8>
+  %t5 = bitcast <4 x i16> %y to <8 x i8>
+  %t6 = select <8 x i1> %cmp, <8 x i8> %t4, <8 x i8> %t5
+  %t7 = bitcast <8 x i8> %t6 to <2 x float>
+  ret <2 x float> %t7
+}
+
+; Optimize bitcasts that are extracting low element of vector.  This happens because of SRoA.
+; rdar://7892780
+define float @test2(<2 x float> %A, <2 x i32> %B) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <2 x float> [[A:%.*]], i32 0
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <2 x i32> [[B:%.*]] to <2 x float>
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x float> [[BC]], i32 0
+; CHECK-NEXT:    [[ADD:%.*]] = fadd float [[TMP24]], [[TMP4]]
+; CHECK-NEXT:    ret float [[ADD]]
+;
+  %tmp28 = bitcast <2 x float> %A to i64  ; <i64> [#uses=2]
+  %tmp23 = trunc i64 %tmp28 to i32                ; <i32> [#uses=1]
+  %tmp24 = bitcast i32 %tmp23 to float            ; <float> [#uses=1]
+
+  %tmp = bitcast <2 x i32> %B to i64
+  %tmp2 = trunc i64 %tmp to i32                ; <i32> [#uses=1]
+  %tmp4 = bitcast i32 %tmp2 to float            ; <float> [#uses=1]
+
+  %add = fadd float %tmp24, %tmp4
+  ret float %add
+}
+
+; Optimize bitcasts that are extracting other elements of a vector.  This happens because of SRoA.
+; rdar://7892780
+define float @test3(<2 x float> %A, <2 x i64> %B) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    [[TMP24:%.*]] = extractelement <2 x float> [[A:%.*]], i32 1
+; CHECK-NEXT:    [[BC2:%.*]] = bitcast <2 x i64> [[B:%.*]] to <4 x float>
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[BC2]], i32 2
+; CHECK-NEXT:    [[ADD:%.*]] = fadd float [[TMP24]], [[TMP4]]
+; CHECK-NEXT:    ret float [[ADD]]
+;
+  %tmp28 = bitcast <2 x float> %A to i64
+  %tmp29 = lshr i64 %tmp28, 32
+  %tmp23 = trunc i64 %tmp29 to i32
+  %tmp24 = bitcast i32 %tmp23 to float
+
+  %tmp = bitcast <2 x i64> %B to i128
+  %tmp1 = lshr i128 %tmp, 64
+  %tmp2 = trunc i128 %tmp1 to i32
+  %tmp4 = bitcast i32 %tmp2 to float
+
+  %add = fadd float %tmp24, %tmp4
+  ret float %add
+}
+
+; Both bitcasts are unnecessary; change the extractelement.
+
+define float @bitcast_extelt1(<2 x float> %A) {
+; CHECK-LABEL: @bitcast_extelt1(
+; CHECK-NEXT:    [[BC2:%.*]] = extractelement <2 x float> [[A:%.*]], i32 0
+; CHECK-NEXT:    ret float [[BC2]]
+;
+  %bc1 = bitcast <2 x float> %A to <2 x i32>
+  %ext = extractelement <2 x i32> %bc1, i32 0
+  %bc2 = bitcast i32 %ext to float
+  ret float %bc2
+}
+
+; Second bitcast can be folded into the first.
+
+define i64 @bitcast_extelt2(<4 x float> %A) {
+; CHECK-LABEL: @bitcast_extelt2(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <4 x float> [[A:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[BC2:%.*]] = extractelement <2 x i64> [[BC]], i32 1
+; CHECK-NEXT:    ret i64 [[BC2]]
+;
+  %bc1 = bitcast <4 x float> %A to <2 x double>
+  %ext = extractelement <2 x double> %bc1, i32 1
+  %bc2 = bitcast double %ext to i64
+  ret i64 %bc2
+}
+
+; TODO: This should return %A.
+
+define <2 x i32> @bitcast_extelt3(<2 x i32> %A) {
+; CHECK-LABEL: @bitcast_extelt3(
+; CHECK-NEXT:    [[BC1:%.*]] = bitcast <2 x i32> [[A:%.*]] to <1 x i64>
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <1 x i64> [[BC1]], i32 0
+; CHECK-NEXT:    [[BC2:%.*]] = bitcast i64 [[EXT]] to <2 x i32>
+; CHECK-NEXT:    ret <2 x i32> [[BC2]]
+;
+  %bc1 = bitcast <2 x i32> %A to <1 x i64>
+  %ext = extractelement <1 x i64> %bc1, i32 0
+  %bc2 = bitcast i64 %ext to <2 x i32>
+  ret <2 x i32> %bc2
+}
+
+; Handle the case where the input is not a vector.
+
+define double @bitcast_extelt4(i128 %A) {
+; CHECK-LABEL: @bitcast_extelt4(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast i128 [[A:%.*]] to <2 x double>
+; CHECK-NEXT:    [[BC2:%.*]] = extractelement <2 x double> [[BC]], i32 0
+; CHECK-NEXT:    ret double [[BC2]]
+;
+  %bc1 = bitcast i128 %A to <2 x i64>
+  %ext = extractelement <2 x i64> %bc1, i32 0
+  %bc2 = bitcast i64 %ext to double
+  ret double %bc2
+}
+
+define <2 x i32> @test4(i32 %A, i32 %B){
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B:%.*]], i32 1
+; CHECK-NEXT:    ret <2 x i32> [[TMP2]]
+;
+  %tmp38 = zext i32 %A to i64
+  %tmp32 = zext i32 %B to i64
+  %tmp33 = shl i64 %tmp32, 32
+  %ins35 = or i64 %tmp33, %tmp38
+  %tmp43 = bitcast i64 %ins35 to <2 x i32>
+  ret <2 x i32> %tmp43
+}
+
+; rdar://8360454
+define <2 x float> @test5(float %A, float %B) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[B:%.*]], i32 1
+; CHECK-NEXT:    ret <2 x float> [[TMP2]]
+;
+  %tmp37 = bitcast float %A to i32
+  %tmp38 = zext i32 %tmp37 to i64
+  %tmp31 = bitcast float %B to i32
+  %tmp32 = zext i32 %tmp31 to i64
+  %tmp33 = shl i64 %tmp32, 32
+  %ins35 = or i64 %tmp33, %tmp38
+  %tmp43 = bitcast i64 %ins35 to <2 x float>
+  ret <2 x float> %tmp43
+}
+
+define <2 x float> @test6(float %A){
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> <float 4.200000e+01, float poison>, float [[A:%.*]], i32 1
+; CHECK-NEXT:    ret <2 x float> [[TMP1]]
+;
+  %tmp23 = bitcast float %A to i32
+  %tmp24 = zext i32 %tmp23 to i64
+  %tmp25 = shl i64 %tmp24, 32
+  %mask20 = or i64 %tmp25, 1109917696
+  %tmp35 = bitcast i64 %mask20 to <2 x float>
+  ret <2 x float> %tmp35
+}
+
+define i64 @ISPC0(i64 %in) {
+; CHECK-LABEL: @ISPC0(
+; CHECK-NEXT:    ret i64 0
+;
+  %out = and i64 %in, xor (i64 bitcast (<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1> to i64), i64 -1)
+  ret i64 %out
+}
+
+
+define i64 @Vec2(i64 %in) {
+; CHECK-LABEL: @Vec2(
+; CHECK-NEXT:    ret i64 0
+;
+  %out = and i64 %in, xor (i64 bitcast (<4 x i16> <i16 0, i16 0, i16 0, i16 0> to i64), i64 0)
+  ret i64 %out
+}
+
+define i64 @All11(i64 %in) {
+; CHECK-LABEL: @All11(
+; CHECK-NEXT:    ret i64 0
+;
+  %out = and i64 %in, xor (i64 bitcast (<2 x float> bitcast (i64 -1 to <2 x float>) to i64), i64 -1)
+  ret i64 %out
+}
+
+
+define i32 @All111(i32 %in) {
+; CHECK-LABEL: @All111(
+; CHECK-NEXT:    ret i32 0
+;
+  %out = and i32 %in, xor (i32 bitcast (<1 x float> bitcast (i32 -1 to <1 x float>) to i32), i32 -1)
+  ret i32 %out
+}
+
+define <2 x i16> @BitcastInsert(i32 %a) {
+; CHECK-LABEL: @BitcastInsert(
+; CHECK-NEXT:    [[R:%.*]] = bitcast i32 [[A:%.*]] to <2 x i16>
+; CHECK-NEXT:    ret <2 x i16> [[R]]
+;
+  %v = insertelement <1 x i32> poison, i32 %a, i32 0
+  %r = bitcast <1 x i32> %v to <2 x i16>
+  ret <2 x i16> %r
+}
+
+; PR17293
+define <2 x i64> @test7(<2 x i8*>* %arg) nounwind {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:    [[CAST:%.*]] = bitcast <2 x i8*>* [[ARG:%.*]] to <2 x i64>*
+; CHECK-NEXT:    [[LOAD:%.*]] = load <2 x i64>, <2 x i64>* [[CAST]], align 16
+; CHECK-NEXT:    ret <2 x i64> [[LOAD]]
+;
+  %cast = bitcast <2 x i8*>* %arg to <2 x i64>*
+  %load = load <2 x i64>, <2 x i64>* %cast, align 16
+  ret <2 x i64> %load
+}
+
+define i8 @test8() {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT:    ret i8 -85
+;
+  %res = bitcast <8 x i1> <i1 true, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true> to i8
+  ret i8 %res
+}
+
+@g = internal unnamed_addr global i32 undef
+
+define void @constant_fold_vector_to_double() {
+; CHECK-LABEL: @constant_fold_vector_to_double(
+; CHECK-NEXT:    store volatile double 1.000000e+00, double* undef, align 8
+; CHECK-NEXT:    store volatile double 1.000000e+00, double* undef, align 8
+; CHECK-NEXT:    store volatile double 1.000000e+00, double* undef, align 8
+; CHECK-NEXT:    store volatile double 1.000000e+00, double* undef, align 8
+; CHECK-NEXT:    store volatile double 0xFFFFFFFFFFFFFFFF, double* undef, align 8
+; CHECK-NEXT:    store volatile double 0x162E000004D2, double* undef, align 8
+; CHECK-NEXT:    store volatile double bitcast (<2 x i32> <i32 1234, i32 ptrtoint (i32* @g to i32)> to double), double* undef, align 8
+; CHECK-NEXT:    store volatile double 0x400000003F800000, double* undef, align 8
+; CHECK-NEXT:    store volatile double 0.000000e+00, double* undef, align 8
+; CHECK-NEXT:    store volatile double 0.000000e+00, double* undef, align 8
+; CHECK-NEXT:    store volatile double 0.000000e+00, double* undef, align 8
+; CHECK-NEXT:    store volatile double 0.000000e+00, double* undef, align 8
+; CHECK-NEXT:    store volatile double 0.000000e+00, double* undef, align 8
+; CHECK-NEXT:    store volatile double 0.000000e+00, double* undef, align 8
+; CHECK-NEXT:    ret void
+;
+  store volatile double bitcast (<1 x i64> <i64 4607182418800017408> to double), double* undef
+  store volatile double bitcast (<2 x i32> <i32 0, i32 1072693248> to double), double* undef
+  store volatile double bitcast (<4 x i16> <i16 0, i16 0, i16 0, i16 16368> to double), double* undef
+  store volatile double bitcast (<8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 240, i8 63> to double), double* undef
+
+  store volatile double bitcast (<2 x i32> <i32 -1, i32 -1> to double), double* undef
+  store volatile double bitcast (<2 x i32> <i32 1234, i32 5678> to double), double* undef
+
+  store volatile double bitcast (<2 x i32> <i32 1234, i32 ptrtoint (i32* @g to i32)> to double), double* undef
+  store volatile double bitcast (<2 x float> <float 1.0, float 2.0> to double), double* undef
+
+  store volatile double bitcast (<2 x i32> zeroinitializer to double), double* undef
+  store volatile double bitcast (<4 x i16> zeroinitializer to double), double* undef
+  store volatile double bitcast (<8 x i8> zeroinitializer to double), double* undef
+  store volatile double bitcast (<16 x i4> zeroinitializer to double), double* undef
+  store volatile double bitcast (<32 x i2> zeroinitializer to double), double* undef
+  store volatile double bitcast (<64 x i1> zeroinitializer to double), double* undef
+  ret void
+}
+
+define void @constant_fold_vector_to_float() {
+; CHECK-LABEL: @constant_fold_vector_to_float(
+; CHECK-NEXT:    store volatile float 1.000000e+00, float* undef, align 4
+; CHECK-NEXT:    store volatile float 1.000000e+00, float* undef, align 4
+; CHECK-NEXT:    store volatile float 1.000000e+00, float* undef, align 4
+; CHECK-NEXT:    store volatile float 1.000000e+00, float* undef, align 4
+; CHECK-NEXT:    ret void
+;
+  store volatile float bitcast (<1 x i32> <i32 1065353216> to float), float* undef
+  store volatile float bitcast (<2 x i16> <i16 0, i16 16256> to float), float* undef
+  store volatile float bitcast (<4 x i8> <i8 0, i8 0, i8 128, i8 63> to float), float* undef
+  store volatile float bitcast (<32 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 0, i1 0> to float), float* undef
+
+  ret void
+}
+
+define void @constant_fold_vector_to_half() {
+; CHECK-LABEL: @constant_fold_vector_to_half(
+; CHECK-NEXT:    store volatile half 0xH4000, half* undef, align 2
+; CHECK-NEXT:    store volatile half 0xH4000, half* undef, align 2
+; CHECK-NEXT:    ret void
+;
+  store volatile half bitcast (<2 x i8> <i8 0, i8 64> to half), half* undef
+  store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef
+  ret void
+}
+
+; Ensure that we do not crash when looking at such a weird bitcast.
+define i8* @bitcast_from_single_element_pointer_vector_to_pointer(<1 x i8*> %ptrvec) {
+; CHECK-LABEL: @bitcast_from_single_element_pointer_vector_to_pointer(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <1 x i8*> [[PTRVEC:%.*]], i32 0
+; CHECK-NEXT:    ret i8* [[TMP1]]
+;
+  %ptr = bitcast <1 x i8*> %ptrvec to i8*
+  ret i8* %ptr
+}
diff --git a/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll b/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll
new file mode 100644
index 0000000000000..02a2bbe6e9877
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll
@@ -0,0 +1,167 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define double @a(<1 x i64> %y) {
+; CHECK-LABEL: @a(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <1 x i64> [[Y:%.*]] to <1 x double>
+; CHECK-NEXT:    [[C:%.*]] = extractelement <1 x double> [[BC]], i32 0
+; CHECK-NEXT:    ret double [[C]]
+;
+  %c = bitcast <1 x i64> %y to double
+  ret double %c
+}
+
+define i64 @b(<1 x i64> %y) {
+; CHECK-LABEL: @b(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <1 x i64> [[Y:%.*]], i32 0
+; CHECK-NEXT:    ret i64 [[TMP1]]
+;
+  %c = bitcast <1 x i64> %y to i64
+  ret i64 %c
+}
+
+define <1 x i64> @c(double %y) {
+; CHECK-LABEL: @c(
+; CHECK-NEXT:    [[C:%.*]] = bitcast double [[Y:%.*]] to <1 x i64>
+; CHECK-NEXT:    ret <1 x i64> [[C]]
+;
+  %c = bitcast double %y to <1 x i64>
+  ret <1 x i64> %c
+}
+
+define <1 x i64> @d(i64 %y) {
+; CHECK-LABEL: @d(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[Y:%.*]], i32 0
+; CHECK-NEXT:    ret <1 x i64> [[TMP1]]
+;
+  %c = bitcast i64 %y to <1 x i64>
+  ret <1 x i64> %c
+}
+
+define x86_mmx @e(<1 x i64> %y) {
+; CHECK-LABEL: @e(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <1 x i64> [[Y:%.*]], i32 0
+; CHECK-NEXT:    [[C:%.*]] = bitcast i64 [[TMP1]] to x86_mmx
+; CHECK-NEXT:    ret x86_mmx [[C]]
+;
+  %c = bitcast <1 x i64> %y to x86_mmx
+  ret x86_mmx %c
+}
+
+define <1 x i64> @f(x86_mmx %y) {
+; CHECK-LABEL: @f(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast x86_mmx [[Y:%.*]] to i64
+; CHECK-NEXT:    [[C:%.*]] = insertelement <1 x i64> undef, i64 [[TMP1]], i32 0
+; CHECK-NEXT:    ret <1 x i64> [[C]]
+;
+  %c = bitcast x86_mmx %y to <1 x i64>
+  ret <1 x i64> %c
+}
+
+define double @g(x86_mmx %x) {
+; CHECK-LABEL: @g(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast x86_mmx [[X:%.*]] to double
+; CHECK-NEXT:    ret double [[TMP0]]
+;
+entry:
+  %0 = bitcast x86_mmx %x to <1 x i64>
+  %1 = bitcast <1 x i64> %0 to double
+  ret double %1
+}
+
+; FP source is ok.
+
+define <3 x i64> @bitcast_inselt_undef(double %x, i32 %idx) {
+; CHECK-LABEL: @bitcast_inselt_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i32 [[IDX:%.*]]
+; CHECK-NEXT:    [[I:%.*]] = bitcast <3 x double> [[TMP1]] to <3 x i64>
+; CHECK-NEXT:    ret <3 x i64> [[I]]
+;
+  %xb = bitcast double %x to i64
+  %i = insertelement <3 x i64> poison, i64 %xb, i32 %idx
+  ret <3 x i64> %i
+}
+
+; Integer source is ok; index is anything.
+
+define <3 x float> @bitcast_inselt_undef_fp(i32 %x, i567 %idx) {
+; CHECK-LABEL: @bitcast_inselt_undef_fp(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <3 x i32> undef, i32 [[X:%.*]], i567 [[IDX:%.*]]
+; CHECK-NEXT:    [[I:%.*]] = bitcast <3 x i32> [[TMP1]] to <3 x float>
+; CHECK-NEXT:    ret <3 x float> [[I]]
+;
+  %xb = bitcast i32 %x to float
+  %i = insertelement <3 x float> poison, float %xb, i567 %idx
+  ret <3 x float> %i
+}
+
+define <vscale x 3 x float> @bitcast_inselt_undef_vscale(i32 %x, i567 %idx) {
+; CHECK-LABEL: @bitcast_inselt_undef_vscale(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <vscale x 3 x i32> undef, i32 [[X:%.*]], i567 [[IDX:%.*]]
+; CHECK-NEXT:    [[I:%.*]] = bitcast <vscale x 3 x i32> [[TMP1]] to <vscale x 3 x float>
+; CHECK-NEXT:    ret <vscale x 3 x float> [[I]]
+;
+  %xb = bitcast i32 %x to float
+  %i = insertelement <vscale x 3 x float> poison, float %xb, i567 %idx
+  ret <vscale x 3 x float> %i
+}
+
+declare void @use(i64)
+
+; Negative test - extra use prevents canonicalization
+
+define <3 x i64> @bitcast_inselt_undef_extra_use(double %x, i32 %idx) {
+; CHECK-LABEL: @bitcast_inselt_undef_extra_use(
+; CHECK-NEXT:    [[XB:%.*]] = bitcast double [[X:%.*]] to i64
+; CHECK-NEXT:    call void @use(i64 [[XB]])
+; CHECK-NEXT:    [[I:%.*]] = insertelement <3 x i64> poison, i64 [[XB]], i32 [[IDX:%.*]]
+; CHECK-NEXT:    ret <3 x i64> [[I]]
+;
+  %xb = bitcast double %x to i64
+  call void @use(i64 %xb)
+  %i = insertelement <3 x i64> poison, i64 %xb, i32 %idx
+  ret <3 x i64> %i
+}
+
+; Negative test - source type must be scalar
+
+define <3 x i64> @bitcast_inselt_undef_vec_src(<2 x i32> %x, i32 %idx) {
+; CHECK-LABEL: @bitcast_inselt_undef_vec_src(
+; CHECK-NEXT:    [[XB:%.*]] = bitcast <2 x i32> [[X:%.*]] to i64
+; CHECK-NEXT:    [[I:%.*]] = insertelement <3 x i64> poison, i64 [[XB]], i32 [[IDX:%.*]]
+; CHECK-NEXT:    ret <3 x i64> [[I]]
+;
+  %xb = bitcast <2 x i32> %x to i64
+  %i = insertelement <3 x i64> poison, i64 %xb, i32 %idx
+  ret <3 x i64> %i
+}
+
+; Negative test - source type must be scalar
+
+define <3 x i64> @bitcast_inselt_undef_from_mmx(x86_mmx %x, i32 %idx) {
+; CHECK-LABEL: @bitcast_inselt_undef_from_mmx(
+; CHECK-NEXT:    [[XB:%.*]] = bitcast x86_mmx [[X:%.*]] to i64
+; CHECK-NEXT:    [[I:%.*]] = insertelement <3 x i64> poison, i64 [[XB]], i32 [[IDX:%.*]]
+; CHECK-NEXT:    ret <3 x i64> [[I]]
+;
+  %xb = bitcast x86_mmx %x to i64
+  %i = insertelement <3 x i64> poison, i64 %xb, i32 %idx
+  ret <3 x i64> %i
+}
+
+; Reduce number of casts
+
+define <2 x i64> @PR45748(double %x, double %y) {
+; CHECK-LABEL: @PR45748(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[I1:%.*]] = bitcast <2 x double> [[TMP2]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[I1]]
+;
+  %xb = bitcast double %x to i64
+  %i0 = insertelement <2 x i64> poison, i64 %xb, i32 0
+  %yb = bitcast double %y to i64
+  %i1 = insertelement <2 x i64> %i0, i64 %yb, i32 1
+  ret <2 x i64> %i1
+}
diff --git a/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll b/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
index e90f60c5f67e9..cac2c0a6617cd 100644
--- a/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll
@@ -31,8 +31,8 @@ define <1 x i64> @c(double %y) {
 
 define <1 x i64> @d(i64 %y) {
 ; CHECK-LABEL: @d(
-; CHECK-NEXT:    [[C:%.*]] = insertelement <1 x i64> undef, i64 [[Y:%.*]], i32 0
-; CHECK-NEXT:    ret <1 x i64> [[C]]
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <1 x i64> poison, i64 [[Y:%.*]], i32 0
+; CHECK-NEXT:    ret <1 x i64> [[TMP1]]
 ;
   %c = bitcast i64 %y to <1 x i64>
   ret <1 x i64> %c
diff --git a/llvm/test/Transforms/InstCombine/bitcast.ll b/llvm/test/Transforms/InstCombine/bitcast.ll
index 3a3da5587d14e..5f89bb91ea72b 100644
--- a/llvm/test/Transforms/InstCombine/bitcast.ll
+++ b/llvm/test/Transforms/InstCombine/bitcast.ll
@@ -389,7 +389,7 @@ define double @bitcast_extelt4(i128 %A) {
 
 define <2 x i32> @test4(i32 %A, i32 %B){
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i32> undef, i32 [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[B:%.*]], i32 1
 ; CHECK-NEXT:    ret <2 x i32> [[TMP2]]
 ;
@@ -404,7 +404,7 @@ define <2 x i32> @test4(i32 %A, i32 %B){
 ; rdar://8360454
 define <2 x float> @test5(float %A, float %B) {
 ; CHECK-LABEL: @test5(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> poison, float [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x float> [[TMP1]], float [[B:%.*]], i32 1
 ; CHECK-NEXT:    ret <2 x float> [[TMP2]]
 ;
@@ -420,7 +420,7 @@ define <2 x float> @test5(float %A, float %B) {
 
 define <2 x float> @test6(float %A){
 ; CHECK-LABEL: @test6(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> <float 4.200000e+01, float undef>, float [[A:%.*]], i32 1
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> <float 4.200000e+01, float poison>, float [[A:%.*]], i32 1
 ; CHECK-NEXT:    ret <2 x float> [[TMP1]]
 ;
   %tmp23 = bitcast float %A to i32
diff --git a/llvm/test/Transforms/InstCombine/broadcast-inseltpoison.ll b/llvm/test/Transforms/InstCombine/broadcast-inseltpoison.ll
new file mode 100644
index 0000000000000..11c92b37ba3ec
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/broadcast-inseltpoison.ll
@@ -0,0 +1,179 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+define <4 x float> @good1(float %arg) {
+; CHECK-LABEL: @good1(
+; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    ret <4 x float> [[T6]]
+;
+  %t = insertelement <4 x float> poison, float %arg, i32 0
+  %t4 = insertelement <4 x float> %t, float %arg, i32 1
+  %t5 = insertelement <4 x float> %t4, float %arg, i32 2
+  %t6 = insertelement <4 x float> %t5, float %arg, i32 3
+  ret <4 x float> %t6
+}
+
+define <4 x float> @good2(float %arg) {
+; CHECK-LABEL: @good2(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T6:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    ret <4 x float> [[T6]]
+;
+  %t = insertelement <4 x float> poison, float %arg, i32 1
+  %t4 = insertelement <4 x float> %t, float %arg, i32 2
+  %t5 = insertelement <4 x float> %t4, float %arg, i32 0
+  %t6 = insertelement <4 x float> %t5, float %arg, i32 3
+  ret <4 x float> %t6
+}
+
+define <4 x float> @good3(float %arg) {
+; CHECK-LABEL: @good3(
+; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    ret <4 x float> [[T6]]
+;
+  %t = insertelement <4 x float> zeroinitializer, float %arg, i32 0
+  %t4 = insertelement <4 x float> %t, float %arg, i32 1
+  %t5 = insertelement <4 x float> %t4, float %arg, i32 2
+  %t6 = insertelement <4 x float> %t5, float %arg, i32 3
+  ret <4 x float> %t6
+}
+
+define <4 x float> @good4(float %arg) {
+; CHECK-LABEL: @good4(
+; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <4 x float> [[T]], [[T]]
+; CHECK-NEXT:    [[T7:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    ret <4 x float> [[T7]]
+;
+  %t = insertelement <4 x float> zeroinitializer, float %arg, i32 0
+  %t4 = insertelement <4 x float> %t, float %arg, i32 1
+  %t5 = insertelement <4 x float> %t4, float %arg, i32 2
+  %t6 = insertelement <4 x float> %t5, float %arg, i32 3
+  %t7 = fadd <4 x float> %t6, %t6
+  ret <4 x float> %t7
+}
+
+define <4 x float> @good5(float %v) {
+; CHECK-LABEL: @good5(
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> poison, float [[V:%.*]], i32 0
+; CHECK-NEXT:    [[A1:%.*]] = fadd <4 x float> [[INS1]], [[INS1]]
+; CHECK-NEXT:    [[INS4:%.*]] = shufflevector <4 x float> [[INS1]], <4 x float> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[RES:%.*]] = fadd <4 x float> [[A1]], [[INS4]]
+; CHECK-NEXT:    ret <4 x float> [[RES]]
+;
+  %ins1 = insertelement <4 x float> poison, float %v, i32 0
+  %a1 = fadd <4 x float> %ins1, %ins1
+  %ins2 = insertelement<4 x float> %ins1, float %v, i32 1
+  %ins3 = insertelement<4 x float> %ins2, float %v, i32 2
+  %ins4 = insertelement<4 x float> %ins3, float %v, i32 3
+  %res = fadd <4 x float> %a1, %ins4
+  ret <4 x float> %res
+}
+
+; The insert is changed to allow the canonical shuffle-splat pattern from element 0.
+
+define <4 x float> @splat_undef1(float %arg) {
+; CHECK-LABEL: @splat_undef1(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T6:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
+; CHECK-NEXT:    ret <4 x float> [[T6]]
+;
+  %t = insertelement <4 x float> poison, float %arg, i32 1
+  %t4 = insertelement <4 x float> %t, float %arg, i32 1
+  %t5 = insertelement <4 x float> %t4, float %arg, i32 2
+  %t6 = insertelement <4 x float> %t5, float %arg, i32 3
+  ret <4 x float> %t6
+}
+
+; Re-uses the existing first insertelement.
+
+define <4 x float> @splat_undef2(float %arg) {
+; CHECK-LABEL: @splat_undef2(
+; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 0>
+; CHECK-NEXT:    ret <4 x float> [[T6]]
+;
+  %t = insertelement <4 x float> poison, float %arg, i32 0
+  %t5 = insertelement <4 x float> %t, float %arg, i32 2
+  %t6 = insertelement <4 x float> %t5, float %arg, i32 3
+  ret <4 x float> %t6
+}
+
+define <4 x float> @bad3(float %arg, float %arg2) {
+; CHECK-LABEL: @bad3(
+; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG2:%.*]], i32 1
+; CHECK-NEXT:    [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG]], i32 2
+; CHECK-NEXT:    [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[T6]]
+;
+  %t = insertelement <4 x float> poison, float %arg, i32 0
+  %t4 = insertelement <4 x float> %t, float %arg2, i32 1
+  %t5 = insertelement <4 x float> %t4, float %arg, i32 2
+  %t6 = insertelement <4 x float> %t5, float %arg, i32 3
+  ret <4 x float> %t6
+}
+
+define <1 x float> @bad4(float %arg) {
+; CHECK-LABEL: @bad4(
+; CHECK-NEXT:    [[T:%.*]] = insertelement <1 x float> poison, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    ret <1 x float> [[T]]
+;
+  %t = insertelement <1 x float> poison, float %arg, i32 0
+  ret <1 x float> %t
+}
+
+; Multiple undef elements are ok.
+; TODO: Multiple uses triggers the transform at %t4, but we should sink/scalarize/CSE the splats?
+
+define <4 x float> @splat_undef3(float %arg) {
+; CHECK-LABEL: @splat_undef3(
+; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T4:%.*]] = shufflevector <4 x float> [[T]], <4 x float> undef, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>
+; CHECK-NEXT:    [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[T7:%.*]] = fadd <4 x float> [[T6]], [[T4]]
+; CHECK-NEXT:    ret <4 x float> [[T7]]
+;
+  %t = insertelement <4 x float> poison, float %arg, i32 0
+  %t4 = insertelement <4 x float> %t, float %arg, i32 1
+  %t5 = insertelement <4 x float> %t4, float %arg, i32 2
+  %t6 = insertelement <4 x float> %t5, float %arg, i32 3
+  %t7 = fadd <4 x float> %t6, %t4
+  ret <4 x float> %t7
+}
+
+define <4 x float> @bad6(float %arg, i32 %k) {
+; CHECK-LABEL: @bad6(
+; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG]], i32 1
+; CHECK-NEXT:    [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG]], i32 [[K:%.*]]
+; CHECK-NEXT:    [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[T6]]
+;
+  %t = insertelement <4 x float> poison, float %arg, i32 0
+  %t4 = insertelement <4 x float> %t, float %arg, i32 1
+  %t5 = insertelement <4 x float> %t4, float %arg, i32 %k
+  %t6 = insertelement <4 x float> %t5, float %arg, i32 3
+  ret <4 x float> %t6
+}
+
+define <4 x float> @bad7(float %v) {
+; CHECK-LABEL: @bad7(
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> poison, float [[V:%.*]], i32 1
+; CHECK-NEXT:    [[A1:%.*]] = fadd <4 x float> [[INS1]], [[INS1]]
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float [[V]], i32 2
+; CHECK-NEXT:    [[INS3:%.*]] = insertelement <4 x float> [[INS2]], float [[V]], i32 3
+; CHECK-NEXT:    [[INS4:%.*]] = insertelement <4 x float> [[INS3]], float [[V]], i32 0
+; CHECK-NEXT:    [[RES:%.*]] = fadd <4 x float> [[A1]], [[INS4]]
+; CHECK-NEXT:    ret <4 x float> [[RES]]
+;
+  %ins1 = insertelement <4 x float> poison, float %v, i32 1
+  %a1 = fadd <4 x float> %ins1, %ins1
+  %ins2 = insertelement<4 x float> %ins1, float %v, i32 2
+  %ins3 = insertelement<4 x float> %ins2, float %v, i32 3
+  %ins4 = insertelement<4 x float> %ins3, float %v, i32 0
+  %res = fadd <4 x float> %a1, %ins4
+  ret <4 x float> %res
+}
diff --git a/llvm/test/Transforms/InstCombine/broadcast.ll b/llvm/test/Transforms/InstCombine/broadcast.ll
index 49ff3129a68d3..1fb94d4087610 100644
--- a/llvm/test/Transforms/InstCombine/broadcast.ll
+++ b/llvm/test/Transforms/InstCombine/broadcast.ll
@@ -29,7 +29,7 @@ define <4 x float> @good2(float %arg) {
 
 define <4 x float> @good3(float %arg) {
 ; CHECK-LABEL: @good3(
-; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
 ; CHECK-NEXT:    [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> undef, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <4 x float> [[T6]]
 ;
@@ -42,7 +42,7 @@ define <4 x float> @good3(float %arg) {
 
 define <4 x float> @good4(float %arg) {
 ; CHECK-LABEL: @good4(
-; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP1:%.*]] = fadd <4 x float> [[T]], [[T]]
 ; CHECK-NEXT:    [[T7:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <4 x float> [[T7]]
diff --git a/llvm/test/Transforms/InstCombine/builtin-dynamic-object-size.ll b/llvm/test/Transforms/InstCombine/builtin-dynamic-object-size.ll
index 4093a121060c4..91c9d3c2827ff 100644
--- a/llvm/test/Transforms/InstCombine/builtin-dynamic-object-size.ll
+++ b/llvm/test/Transforms/InstCombine/builtin-dynamic-object-size.ll
@@ -14,7 +14,7 @@ entry:
 
 ; CHECK:      define i64 @weird_identity_but_ok(i64 %sz)
 ; CHECK-NEXT: entry:
-; CHECK-NEXT:   ret i64 %sz
+; CHECK:   ret i64 %sz
 ; CHECK-NEXT: }
 
 define i64 @phis_are_neat(i1 %which) {
@@ -101,6 +101,57 @@ for.end:                                          ; preds = %for.body, %entry
 ; CHECK:   define void @f()
 ; CHECK:     call i64 @llvm.objectsize.i64.p0i8(
 
+define void @bdos_cmpm1(i64 %alloc) {
+entry:
+  %obj = call i8* @malloc(i64 %alloc)
+  %objsize = call i64 @llvm.objectsize.i64.p0i8(i8* %obj, i1 0, i1 0, i1 1)
+  %cmp.not = icmp eq i64 %objsize, -1
+  br i1 %cmp.not, label %if.else, label %if.then
+
+if.then:
+  call void @fortified_chk(i8* %obj, i64 %objsize)
+  br label %if.end
+
+if.else:
+  call void @unfortified(i8* %obj, i64 %objsize)
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+; CHECK:  define void @bdos_cmpm1(
+; CHECK:    [[TMP:%.*]] = icmp ne i64 %alloc, -1
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP]])
+; CHECK-NEXT:    br i1 false, label %if.else, label %if.then
+; CHECK:    call void @fortified_chk(i8* %obj, i64 %alloc)
+
+define void @bdos_cmpm1_expr(i64 %alloc, i64 %part) {
+entry:
+  %sz = udiv i64 %alloc, %part
+  %obj = call i8* @malloc(i64 %sz)
+  %objsize = call i64 @llvm.objectsize.i64.p0i8(i8* %obj, i1 0, i1 0, i1 1)
+  %cmp.not = icmp eq i64 %objsize, -1
+  br i1 %cmp.not, label %if.else, label %if.then
+
+if.then:
+  call void @fortified_chk(i8* %obj, i64 %objsize)
+  br label %if.end
+
+if.else:
+  call void @unfortified(i8* %obj, i64 %objsize)
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+; CHECK:  define void @bdos_cmpm1_expr(
+; CHECK:    [[TMP:%.*]] = icmp ne i64 [[SZ:%.*]], -1
+; CHECK-NEXT:    call void @llvm.assume(i1 [[TMP]])
+; CHECK-NEXT:    br i1 false, label %if.else, label %if.then
+; CHECK:    call void @fortified_chk(i8* %obj, i64 [[SZ]])
+
 declare void @bury(i32) local_unnamed_addr #2
 
 ; Function Attrs: nounwind allocsize(0)
@@ -113,3 +164,7 @@ declare void @free(i8* nocapture)
 
 ; Function Attrs: nounwind readnone speculatable
 declare i64 @llvm.objectsize.i64.p0i8(i8*, i1, i1, i1)
+
+declare void @fortified_chk(i8*, i64)
+
+declare void @unfortified(i8*, i64)
diff --git a/llvm/test/Transforms/InstCombine/cast.ll b/llvm/test/Transforms/InstCombine/cast.ll
index 2b58fb616e46d..38965f7879c2a 100644
--- a/llvm/test/Transforms/InstCombine/cast.ll
+++ b/llvm/test/Transforms/InstCombine/cast.ll
@@ -874,11 +874,11 @@ define <3 x i32> @test60(<4 x i32> %call4) {
 
 define <4 x i32> @test61(<3 x i32> %call4) {
 ; BE-LABEL: @test61(
-; BE-NEXT:    [[P10:%.*]] = shufflevector <3 x i32> [[CALL4:%.*]], <3 x i32> <i32 0, i32 undef, i32 undef>, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
+; BE-NEXT:    [[P10:%.*]] = shufflevector <3 x i32> [[CALL4:%.*]], <3 x i32> <i32 0, i32 poison, i32 poison>, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
 ; BE-NEXT:    ret <4 x i32> [[P10]]
 ;
 ; LE-LABEL: @test61(
-; LE-NEXT:    [[P10:%.*]] = shufflevector <3 x i32> [[CALL4:%.*]], <3 x i32> <i32 0, i32 undef, i32 undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; LE-NEXT:    [[P10:%.*]] = shufflevector <3 x i32> [[CALL4:%.*]], <3 x i32> <i32 0, i32 poison, i32 poison>, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 ; LE-NEXT:    ret <4 x i32> [[P10]]
 ;
   %p11 = bitcast <3 x i32> %call4 to i96
@@ -890,12 +890,12 @@ define <4 x i32> @test61(<3 x i32> %call4) {
 define <4 x i32> @test62(<3 x float> %call4) {
 ; BE-LABEL: @test62(
 ; BE-NEXT:    [[TMP1:%.*]] = bitcast <3 x float> [[CALL4:%.*]] to <3 x i32>
-; BE-NEXT:    [[P10:%.*]] = shufflevector <3 x i32> [[TMP1]], <3 x i32> <i32 0, i32 undef, i32 undef>, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
+; BE-NEXT:    [[P10:%.*]] = shufflevector <3 x i32> [[TMP1]], <3 x i32> <i32 0, i32 poison, i32 poison>, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
 ; BE-NEXT:    ret <4 x i32> [[P10]]
 ;
 ; LE-LABEL: @test62(
 ; LE-NEXT:    [[TMP1:%.*]] = bitcast <3 x float> [[CALL4:%.*]] to <3 x i32>
-; LE-NEXT:    [[P10:%.*]] = shufflevector <3 x i32> [[TMP1]], <3 x i32> <i32 0, i32 undef, i32 undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; LE-NEXT:    [[P10:%.*]] = shufflevector <3 x i32> [[TMP1]], <3 x i32> <i32 0, i32 poison, i32 poison>, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
 ; LE-NEXT:    ret <4 x i32> [[P10]]
 ;
   %p11 = bitcast <3 x float> %call4 to i96
diff --git a/llvm/test/Transforms/InstCombine/ctpop.ll b/llvm/test/Transforms/InstCombine/ctpop.ll
index 33b95b02dd2e3..237fb04582257 100644
--- a/llvm/test/Transforms/InstCombine/ctpop.ll
+++ b/llvm/test/Transforms/InstCombine/ctpop.ll
@@ -84,11 +84,11 @@ define <2 x i1> @test5vec(<2 x i32> %arg) {
   ret <2 x i1> %res
 }
 
-; Make sure we don't add range metadata to i1 ctpop.
+; No intrinsic or range needed - ctpop of bool bit is the bit itself.
+
 define i1 @test6(i1 %arg) {
 ; CHECK-LABEL: @test6(
-; CHECK-NEXT:    [[CNT:%.*]] = call i1 @llvm.ctpop.i1(i1 [[ARG:%.*]])
-; CHECK-NEXT:    ret i1 [[CNT]]
+; CHECK-NEXT:    ret i1 [[ARG:%.*]]
 ;
   %cnt = call i1 @llvm.ctpop.i1(i1 %arg)
   ret i1 %cnt
diff --git a/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll b/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll
new file mode 100644
index 0000000000000..d614bb06879e0
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/extractelement-inseltpoison.ll
@@ -0,0 +1,332 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S -data-layout="e" | FileCheck %s --check-prefixes=ANY,LE
+; RUN: opt < %s -instcombine -S -data-layout="E" | FileCheck %s --check-prefixes=ANY,BE
+
+define i32 @extractelement_out_of_range(<2 x i32> %x) {
+; ANY-LABEL: @extractelement_out_of_range(
+; ANY-NEXT:    ret i32 undef
+;
+  %E1 = extractelement <2 x i32> %x, i8 16
+  ret i32 %E1
+}
+
+define i32 @extractelement_type_out_of_range(<2 x i32> %x) {
+; ANY-LABEL: @extractelement_type_out_of_range(
+; ANY-NEXT:    [[E1:%.*]] = extractelement <2 x i32> [[X:%.*]], i128 0
+; ANY-NEXT:    ret i32 [[E1]]
+;
+  %E1 = extractelement <2 x i32> %x, i128 0
+  ret i32 %E1
+}
+
+define i32 @bitcasted_inselt_equal_num_elts(float %f) {
+; ANY-LABEL: @bitcasted_inselt_equal_num_elts(
+; ANY-NEXT:    [[R:%.*]] = bitcast float [[F:%.*]] to i32
+; ANY-NEXT:    ret i32 [[R]]
+;
+  %vf = insertelement <4 x float> poison, float %f, i32 0
+  %vi = bitcast <4 x float> %vf to <4 x i32>
+  %r = extractelement <4 x i32> %vi, i32 0
+  ret i32 %r
+}
+
+define i64 @test2(i64 %in) {
+; ANY-LABEL: @test2(
+; ANY-NEXT:    ret i64 [[IN:%.*]]
+;
+  %vec = insertelement <8 x i64> poison, i64 %in, i32 0
+  %splat = shufflevector <8 x i64> %vec, <8 x i64> undef, <8 x i32> zeroinitializer
+  %add = add <8 x i64> %splat, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
+  %r = extractelement <8 x i64> %add, i32 0
+  ret i64 %r
+}
+
+define i32 @bitcasted_inselt_wide_source_zero_elt(i64 %x) {
+; LE-LABEL: @bitcasted_inselt_wide_source_zero_elt(
+; LE-NEXT:    [[R:%.*]] = trunc i64 [[X:%.*]] to i32
+; LE-NEXT:    ret i32 [[R]]
+;
+; BE-LABEL: @bitcasted_inselt_wide_source_zero_elt(
+; BE-NEXT:    [[TMP1:%.*]] = lshr i64 [[X:%.*]], 32
+; BE-NEXT:    [[R:%.*]] = trunc i64 [[TMP1]] to i32
+; BE-NEXT:    ret i32 [[R]]
+;
+  %i = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
+  %b = bitcast <2 x i64> %i to <4 x i32>
+  %r = extractelement <4 x i32> %b, i32 0
+  ret i32 %r
+}
+
+define i16 @bitcasted_inselt_wide_source_modulo_elt(i64 %x) {
+; LE-LABEL: @bitcasted_inselt_wide_source_modulo_elt(
+; LE-NEXT:    [[R:%.*]] = trunc i64 [[X:%.*]] to i16
+; LE-NEXT:    ret i16 [[R]]
+;
+; BE-LABEL: @bitcasted_inselt_wide_source_modulo_elt(
+; BE-NEXT:    [[TMP1:%.*]] = lshr i64 [[X:%.*]], 48
+; BE-NEXT:    [[R:%.*]] = trunc i64 [[TMP1]] to i16
+; BE-NEXT:    ret i16 [[R]]
+;
+  %i = insertelement <2 x i64> poison, i64 %x, i32 1
+  %b = bitcast <2 x i64> %i to <8 x i16>
+  %r = extractelement <8 x i16> %b, i32 4
+  ret i16 %r
+}
+
+define i32 @bitcasted_inselt_wide_source_not_modulo_elt(i64 %x) {
+; LE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt(
+; LE-NEXT:    [[TMP1:%.*]] = lshr i64 [[X:%.*]], 32
+; LE-NEXT:    [[R:%.*]] = trunc i64 [[TMP1]] to i32
+; LE-NEXT:    ret i32 [[R]]
+;
+; BE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt(
+; BE-NEXT:    [[R:%.*]] = trunc i64 [[X:%.*]] to i32
+; BE-NEXT:    ret i32 [[R]]
+;
+  %i = insertelement <2 x i64> poison, i64 %x, i32 0
+  %b = bitcast <2 x i64> %i to <4 x i32>
+  %r = extractelement <4 x i32> %b, i32 1
+  ret i32 %r
+}
+
+define i8 @bitcasted_inselt_wide_source_not_modulo_elt_not_half(i32 %x) {
+; LE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt_not_half(
+; LE-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 16
+; LE-NEXT:    [[R:%.*]] = trunc i32 [[TMP1]] to i8
+; LE-NEXT:    ret i8 [[R]]
+;
+; BE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt_not_half(
+; BE-NEXT:    [[TMP1:%.*]] = lshr i32 [[X:%.*]], 8
+; BE-NEXT:    [[R:%.*]] = trunc i32 [[TMP1]] to i8
+; BE-NEXT:    ret i8 [[R]]
+;
+  %i = insertelement <2 x i32> poison, i32 %x, i32 0
+  %b = bitcast <2 x i32> %i to <8 x i8>
+  %r = extractelement <8 x i8> %b, i32 2
+  ret i8 %r
+}
+
+define i3 @bitcasted_inselt_wide_source_not_modulo_elt_not_half_weird_types(i15 %x) {
+; LE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt_not_half_weird_types(
+; LE-NEXT:    [[TMP1:%.*]] = lshr i15 [[X:%.*]], 3
+; LE-NEXT:    [[R:%.*]] = trunc i15 [[TMP1]] to i3
+; LE-NEXT:    ret i3 [[R]]
+;
+; BE-LABEL: @bitcasted_inselt_wide_source_not_modulo_elt_not_half_weird_types(
+; BE-NEXT:    [[TMP1:%.*]] = lshr i15 [[X:%.*]], 9
+; BE-NEXT:    [[R:%.*]] = trunc i15 [[TMP1]] to i3
+; BE-NEXT:    ret i3 [[R]]
+;
+  %i = insertelement <3 x i15> poison, i15 %x, i32 0
+  %b = bitcast <3 x i15> %i to <15 x i3>
+  %r = extractelement <15 x i3> %b, i32 1
+  ret i3 %r
+}
+
+; Negative test for the above fold, but we can remove the insert here.
+
+define i8 @bitcasted_inselt_wide_source_wrong_insert(<2 x i32> %v, i32 %x) {
+; ANY-LABEL: @bitcasted_inselt_wide_source_wrong_insert(
+; ANY-NEXT:    [[B:%.*]] = bitcast <2 x i32> [[V:%.*]] to <8 x i8>
+; ANY-NEXT:    [[R:%.*]] = extractelement <8 x i8> [[B]], i32 2
+; ANY-NEXT:    ret i8 [[R]]
+;
+  %i = insertelement <2 x i32> %v, i32 %x, i32 1
+  %b = bitcast <2 x i32> %i to <8 x i8>
+  %r = extractelement <8 x i8> %b, i32 2
+  ret i8 %r
+}
+
+; Partial negative test for the above fold, extra uses are not allowed if shift is needed.
+
+declare void @use(<8 x i8>)
+
+define i8 @bitcasted_inselt_wide_source_uses(i32 %x) {
+; LE-LABEL: @bitcasted_inselt_wide_source_uses(
+; LE-NEXT:    [[I:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
+; LE-NEXT:    [[B:%.*]] = bitcast <2 x i32> [[I]] to <8 x i8>
+; LE-NEXT:    call void @use(<8 x i8> [[B]])
+; LE-NEXT:    [[R:%.*]] = extractelement <8 x i8> [[B]], i32 3
+; LE-NEXT:    ret i8 [[R]]
+;
+; BE-LABEL: @bitcasted_inselt_wide_source_uses(
+; BE-NEXT:    [[I:%.*]] = insertelement <2 x i32> poison, i32 [[X:%.*]], i32 0
+; BE-NEXT:    [[B:%.*]] = bitcast <2 x i32> [[I]] to <8 x i8>
+; BE-NEXT:    call void @use(<8 x i8> [[B]])
+; BE-NEXT:    [[R:%.*]] = trunc i32 [[X]] to i8
+; BE-NEXT:    ret i8 [[R]]
+;
+  %i = insertelement <2 x i32> poison, i32 %x, i32 0
+  %b = bitcast <2 x i32> %i to <8 x i8>
+  call void @use(<8 x i8> %b)
+  %r = extractelement <8 x i8> %b, i32 3
+  ret i8 %r
+}
+
+define float @bitcasted_inselt_to_FP(i64 %x) {
+; LE-LABEL: @bitcasted_inselt_to_FP(
+; LE-NEXT:    [[TMP1:%.*]] = lshr i64 [[X:%.*]], 32
+; LE-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
+; LE-NEXT:    [[R:%.*]] = bitcast i32 [[TMP2]] to float
+; LE-NEXT:    ret float [[R]]
+;
+; BE-LABEL: @bitcasted_inselt_to_FP(
+; BE-NEXT:    [[TMP1:%.*]] = trunc i64 [[X:%.*]] to i32
+; BE-NEXT:    [[R:%.*]] = bitcast i32 [[TMP1]] to float
+; BE-NEXT:    ret float [[R]]
+;
+  %i = insertelement <2 x i64> poison, i64 %x, i32 0
+  %b = bitcast <2 x i64> %i to <4 x float>
+  %r = extractelement <4 x float> %b, i32 1
+  ret float %r
+}
+
+declare void @use_v2i128(<2 x i128>)
+declare void @use_v8f32(<8 x float>)
+
+define float @bitcasted_inselt_to_FP_uses(i128 %x) {
+; ANY-LABEL: @bitcasted_inselt_to_FP_uses(
+; ANY-NEXT:    [[I:%.*]] = insertelement <2 x i128> poison, i128 [[X:%.*]], i32 0
+; ANY-NEXT:    call void @use_v2i128(<2 x i128> [[I]])
+; ANY-NEXT:    [[B:%.*]] = bitcast <2 x i128> [[I]] to <8 x float>
+; ANY-NEXT:    [[R:%.*]] = extractelement <8 x float> [[B]], i32 1
+; ANY-NEXT:    ret float [[R]]
+;
+  %i = insertelement <2 x i128> poison, i128 %x, i32 0
+  call void @use_v2i128(<2 x i128> %i)
+  %b = bitcast <2 x i128> %i to <8 x float>
+  %r = extractelement <8 x float> %b, i32 1
+  ret float %r
+}
+
+define float @bitcasted_inselt_to_FP_uses2(i128 %x) {
+; ANY-LABEL: @bitcasted_inselt_to_FP_uses2(
+; ANY-NEXT:    [[I:%.*]] = insertelement <2 x i128> poison, i128 [[X:%.*]], i32 0
+; ANY-NEXT:    [[B:%.*]] = bitcast <2 x i128> [[I]] to <8 x float>
+; ANY-NEXT:    call void @use_v8f32(<8 x float> [[B]])
+; ANY-NEXT:    [[R:%.*]] = extractelement <8 x float> [[B]], i32 1
+; ANY-NEXT:    ret float [[R]]
+;
+  %i = insertelement <2 x i128> poison, i128 %x, i32 0
+  %b = bitcast <2 x i128> %i to <8 x float>
+  call void @use_v8f32(<8 x float> %b)
+  %r = extractelement <8 x float> %b, i32 1
+  ret float %r
+}
+
+define i32 @bitcasted_inselt_from_FP(double %x) {
+; LE-LABEL: @bitcasted_inselt_from_FP(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast double [[X:%.*]] to i64
+; LE-NEXT:    [[TMP2:%.*]] = lshr i64 [[TMP1]], 32
+; LE-NEXT:    [[R:%.*]] = trunc i64 [[TMP2]] to i32
+; LE-NEXT:    ret i32 [[R]]
+;
+; BE-LABEL: @bitcasted_inselt_from_FP(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast double [[X:%.*]] to i64
+; BE-NEXT:    [[R:%.*]] = trunc i64 [[TMP1]] to i32
+; BE-NEXT:    ret i32 [[R]]
+;
+  %i = insertelement <2 x double> poison, double %x, i32 0
+  %b = bitcast <2 x double> %i to <4 x i32>
+  %r = extractelement <4 x i32> %b, i32 1
+  ret i32 %r
+}
+
+declare void @use_v2f64(<2 x double>)
+declare void @use_v8i16(<8 x i16>)
+
+define i16 @bitcasted_inselt_from_FP_uses(double %x) {
+; ANY-LABEL: @bitcasted_inselt_from_FP_uses(
+; ANY-NEXT:    [[I:%.*]] = insertelement <2 x double> poison, double [[X:%.*]], i32 0
+; ANY-NEXT:    call void @use_v2f64(<2 x double> [[I]])
+; ANY-NEXT:    [[B:%.*]] = bitcast <2 x double> [[I]] to <8 x i16>
+; ANY-NEXT:    [[R:%.*]] = extractelement <8 x i16> [[B]], i32 1
+; ANY-NEXT:    ret i16 [[R]]
+;
+  %i = insertelement <2 x double> poison, double %x, i32 0
+  call void @use_v2f64(<2 x double> %i)
+  %b = bitcast <2 x double> %i to <8 x i16>
+  %r = extractelement <8 x i16> %b, i32 1
+  ret i16 %r
+}
+
+define i16 @bitcasted_inselt_from_FP_uses2(double %x) {
+; ANY-LABEL: @bitcasted_inselt_from_FP_uses2(
+; ANY-NEXT:    [[I:%.*]] = insertelement <2 x double> poison, double [[X:%.*]], i32 0
+; ANY-NEXT:    [[B:%.*]] = bitcast <2 x double> [[I]] to <8 x i16>
+; ANY-NEXT:    call void @use_v8i16(<8 x i16> [[B]])
+; ANY-NEXT:    [[R:%.*]] = extractelement <8 x i16> [[B]], i32 1
+; ANY-NEXT:    ret i16 [[R]]
+;
+  %i = insertelement <2 x double> poison, double %x, i32 0
+  %b = bitcast <2 x double> %i to <8 x i16>
+  call void @use_v8i16(<8 x i16> %b)
+  %r = extractelement <8 x i16> %b, i32 1
+  ret i16 %r
+}
+
+define float @bitcasted_inselt_to_and_from_FP(double %x) {
+; ANY-LABEL: @bitcasted_inselt_to_and_from_FP(
+; ANY-NEXT:    [[I:%.*]] = insertelement <2 x double> poison, double [[X:%.*]], i32 0
+; ANY-NEXT:    [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float>
+; ANY-NEXT:    [[R:%.*]] = extractelement <4 x float> [[B]], i32 1
+; ANY-NEXT:    ret float [[R]]
+;
+  %i = insertelement <2 x double> poison, double %x, i32 0
+  %b = bitcast <2 x double> %i to <4 x float>
+  %r = extractelement <4 x float> %b, i32 1
+  ret float %r
+}
+
+define float @bitcasted_inselt_to_and_from_FP_uses(double %x) {
+; ANY-LABEL: @bitcasted_inselt_to_and_from_FP_uses(
+; ANY-NEXT:    [[I:%.*]] = insertelement <2 x double> poison, double [[X:%.*]], i32 0
+; ANY-NEXT:    call void @use_v2f64(<2 x double> [[I]])
+; ANY-NEXT:    [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float>
+; ANY-NEXT:    [[R:%.*]] = extractelement <4 x float> [[B]], i32 1
+; ANY-NEXT:    ret float [[R]]
+;
+  %i = insertelement <2 x double> poison, double %x, i32 0
+  call void @use_v2f64(<2 x double> %i)
+  %b = bitcast <2 x double> %i to <4 x float>
+  %r = extractelement <4 x float> %b, i32 1
+  ret float %r
+}
+
+declare void @use_v4f32(<4 x float>)
+
+define float @bitcasted_inselt_to_and_from_FP_uses2(double %x) {
+; ANY-LABEL: @bitcasted_inselt_to_and_from_FP_uses2(
+; ANY-NEXT:    [[I:%.*]] = insertelement <2 x double> poison, double [[X:%.*]], i32 0
+; ANY-NEXT:    [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float>
+; ANY-NEXT:    call void @use_v4f32(<4 x float> [[B]])
+; ANY-NEXT:    [[R:%.*]] = extractelement <4 x float> [[B]], i32 1
+; ANY-NEXT:    ret float [[R]]
+;
+  %i = insertelement <2 x double> poison, double %x, i32 0
+  %b = bitcast <2 x double> %i to <4 x float>
+  call void @use_v4f32(<4 x float> %b)
+  %r = extractelement <4 x float> %b, i32 1
+  ret float %r
+}
+
+; This would crash/assert because the logic for collectShuffleElements()
+; does not consider the possibility of invalid insert/extract operands.
+
+define <4 x double> @invalid_extractelement(<2 x double> %a, <4 x double> %b, double* %p) {
+; ANY-LABEL: @invalid_extractelement(
+; ANY-NEXT:    [[TMP1:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; ANY-NEXT:    [[T4:%.*]] = shufflevector <4 x double> [[B:%.*]], <4 x double> [[TMP1]], <4 x i32> <i32 undef, i32 1, i32 4, i32 3>
+; ANY-NEXT:    [[E:%.*]] = extractelement <4 x double> [[B]], i32 1
+; ANY-NEXT:    store double [[E]], double* [[P:%.*]], align 8
+; ANY-NEXT:    [[R:%.*]] = insertelement <4 x double> [[T4]], double undef, i64 0
+; ANY-NEXT:    ret <4 x double> [[R]]
+;
+  %t3 = extractelement <2 x double> %a, i32 0
+  %t4 = insertelement <4 x double> %b, double %t3, i32 2
+  %e = extractelement <4 x double> %t4, i32 1
+  store double %e, double* %p
+  %e1 = extractelement <2 x double> %a, i32 4 ; invalid index
+  %r = insertelement <4 x double> %t4, double %e1, i64 0
+  ret <4 x double> %r
+}
diff --git a/llvm/test/Transforms/InstCombine/fold-vector-zero-inseltpoison.ll b/llvm/test/Transforms/InstCombine/fold-vector-zero-inseltpoison.ll
new file mode 100644
index 0000000000000..0584116b2ff38
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/fold-vector-zero-inseltpoison.ll
@@ -0,0 +1,35 @@
+; RUN: opt < %s -instcombine -S | not grep zeroinitializer
+
+define void @foo(i64 %A, i64 %B) {
+bb8:
+	br label %bb30
+
+bb30:
+	%s0 = phi i64 [ 0, %bb8 ], [ %r21, %bb30 ]
+	%l0 = phi i64 [ -2222, %bb8 ], [ %r23, %bb30 ]
+	%r2 = add i64 %s0, %B
+	%r3 = inttoptr i64 %r2 to <2 x double>*
+	%r4 = load <2 x double>, <2 x double>* %r3, align 8
+	%r6 = bitcast <2 x double> %r4 to <2 x i64>
+	%r7 = bitcast <2 x double> zeroinitializer to <2 x i64>
+	%r8 = insertelement <2 x i64> poison, i64 9223372036854775807, i32 0
+	%r9 = insertelement <2 x i64> poison, i64 -9223372036854775808, i32 0
+	%r10 = insertelement <2 x i64> %r8, i64 9223372036854775807, i32 1
+	%r11 = insertelement <2 x i64> %r9, i64 -9223372036854775808, i32 1
+	%r12 = and <2 x i64> %r6, %r10
+	%r13 = and <2 x i64> %r7, %r11
+	%r14 = or <2 x i64> %r12, %r13
+	%r15 = bitcast <2 x i64> %r14 to <2 x double>
+	%r18 = add i64 %s0, %A
+	%r19 = inttoptr i64 %r18 to <2 x double>*
+	store <2 x double> %r15, <2 x double>* %r19, align 8
+	%r21 = add i64 16, %s0
+	%r23 = add i64 1, %l0
+	%r25 = icmp slt i64 %r23, 0
+	%r26 = zext i1 %r25 to i64
+	%r27 = icmp ne i64 %r26, 0
+	br i1 %r27, label %bb30, label %bb5
+
+bb5:
+	ret void
+}
diff --git a/llvm/test/Transforms/InstCombine/getelementptr.ll b/llvm/test/Transforms/InstCombine/getelementptr.ll
index 85ef011b3212b..048dd9cceedfc 100644
--- a/llvm/test/Transforms/InstCombine/getelementptr.ll
+++ b/llvm/test/Transforms/InstCombine/getelementptr.ll
@@ -217,7 +217,7 @@ define <2 x i1> @test13_vector2(i64 %X, <2 x %S*> %P) nounwind {
 ; CHECK-LABEL: @test13_vector2(
 ; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> undef, i64 [[X:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i64> [[DOTSPLATINSERT]], <i64 2, i64 0>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], <i64 -4, i64 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], <i64 -4, i64 poison>
 ; CHECK-NEXT:    [[C:%.*]] = shufflevector <2 x i1> [[TMP2]], <2 x i1> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
@@ -232,7 +232,7 @@ define <2 x i1> @test13_vector3(i64 %X, <2 x %S*> %P) nounwind {
 ; CHECK-LABEL: @test13_vector3(
 ; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> undef, i64 [[X:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i64> [[DOTSPLATINSERT]], <i64 2, i64 0>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], <i64 4, i64 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], <i64 4, i64 poison>
 ; CHECK-NEXT:    [[C:%.*]] = shufflevector <2 x i1> [[TMP2]], <2 x i1> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
@@ -1237,4 +1237,40 @@ define i32* @PR45084_extra_use(i1 %cond, %struct.f** %p) {
   ret i32* %gep
 }
 
+define i8* @gep_null_inbounds(i64 %idx) {
+; CHECK-LABEL: @gep_null_inbounds(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds i8, i8* null, i64 [[IDX:%.*]]
+; CHECK-NEXT:    ret i8* [[GEP]]
+;
+  %gep = getelementptr inbounds i8, i8* null, i64 %idx
+  ret i8* %gep
+}
+
+define i8* @gep_null_not_inbounds(i64 %idx) {
+; CHECK-LABEL: @gep_null_not_inbounds(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i8, i8* null, i64 [[IDX:%.*]]
+; CHECK-NEXT:    ret i8* [[GEP]]
+;
+  %gep = getelementptr i8, i8* null, i64 %idx
+  ret i8* %gep
+}
+
+define i8* @gep_null_defined(i64 %idx) null_pointer_is_valid {
+; CHECK-LABEL: @gep_null_defined(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds i8, i8* null, i64 [[IDX:%.*]]
+; CHECK-NEXT:    ret i8* [[GEP]]
+;
+  %gep = getelementptr inbounds i8, i8* null, i64 %idx
+  ret i8* %gep
+}
+
+define i8* @gep_null_inbounds_different_type(i64 %idx1, i64 %idx2) {
+; CHECK-LABEL: @gep_null_inbounds_different_type(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds [0 x i8], [0 x i8]* null, i64 0, i64 [[IDX2:%.*]]
+; CHECK-NEXT:    ret i8* [[GEP]]
+;
+  %gep = getelementptr inbounds [0 x i8], [0 x i8]* null, i64 %idx1, i64 %idx2
+  ret i8* %gep
+}
+
 !0 = !{!"branch_weights", i32 2, i32 10}
diff --git a/llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll b/llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll
new file mode 100644
index 0000000000000..14227d304df78
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor-by-value.ll
@@ -0,0 +1,89 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+declare i8 @gen8()
+declare void @use8(i8)
+
+@a = global i8 17
+
+define i8 @t0_scalar(i8 %x, i8 %y) {
+; CHECK-LABEL: @t0_scalar(
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = xor i8 [[TMP1]], 42
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %i0 = xor i8 %x, 42
+  %r = xor i8 %i0, %y
+  ret i8 %r
+}
+
+define <2 x i8> @t1_splatvec(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @t1_splatvec(
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i8> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = xor <2 x i8> [[TMP1]], <i8 42, i8 42>
+; CHECK-NEXT:    ret <2 x i8> [[R]]
+;
+  %i0 = xor <2 x i8> %x, <i8 42, i8 42>
+  %r = xor <2 x i8> %i0, %y
+  ret <2 x i8> %r
+}
+define <2 x i8> @t2_vec(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @t2_vec(
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i8> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = xor <2 x i8> [[TMP1]], <i8 42, i8 24>
+; CHECK-NEXT:    ret <2 x i8> [[R]]
+;
+  %i0 = xor <2 x i8> %x, <i8 42, i8 24>
+  %r = xor <2 x i8> %i0, %y
+  ret <2 x i8> %r
+}
+define <2 x i8> @t3_vec_undef(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @t3_vec_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i8> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = xor <2 x i8> [[TMP1]], <i8 42, i8 undef>
+; CHECK-NEXT:    ret <2 x i8> [[R]]
+;
+  %i0 = xor <2 x i8> %x, <i8 42, i8 undef>
+  %r = xor <2 x i8> %i0, %y
+  ret <2 x i8> %r
+}
+
+define i8 @t4_extrause(i8 %x, i8 %y) {
+; CHECK-LABEL: @t4_extrause(
+; CHECK-NEXT:    [[I0:%.*]] = xor i8 [[X:%.*]], 42
+; CHECK-NEXT:    call void @use8(i8 [[I0]])
+; CHECK-NEXT:    [[R:%.*]] = xor i8 [[I0]], [[Y:%.*]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %i0 = xor i8 %x, 42
+  call void @use8(i8 %i0)
+  %r = xor i8 %i0, %y
+  ret i8 %r
+}
+
+define i8 @t5_commutativity(i8 %x) {
+; CHECK-LABEL: @t5_commutativity(
+; CHECK-NEXT:    [[Y:%.*]] = call i8 @gen8()
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[Y]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = xor i8 [[TMP1]], 42
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %i0 = xor i8 %x, 42
+  %y = call i8 @gen8()
+  %r = xor i8 %y, %i0
+  ret i8 %r
+}
+
+@global_constant = internal global i32 0, align 4
+@global_constant2 = internal global i32 0, align 4
+
+define i8 @constantexpr(i8 %or) local_unnamed_addr #0 {
+; CHECK-LABEL: @constantexpr(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[R:%.*]] = xor i8 [[OR:%.*]], xor (i8 ptrtoint (i32* @global_constant to i8), i8 ptrtoint (i32* @global_constant2 to i8))
+; CHECK-NEXT:    ret i8 [[R]]
+;
+entry:
+  %r = xor i8 %or, xor (i8 xor (i8 ptrtoint (i32* @global_constant to i8), i8 -1), i8 xor (i8 ptrtoint (i32* @global_constant2 to i8), i8 -1))
+  ret i8 %r
+}
diff --git a/llvm/test/Transforms/InstCombine/icmp-bc-vec-inseltpoison.ll b/llvm/test/Transforms/InstCombine/icmp-bc-vec-inseltpoison.ll
new file mode 100644
index 0000000000000..5df11093b1473
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/icmp-bc-vec-inseltpoison.ll
@@ -0,0 +1,127 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Tests to verify proper functioning of the icmp folding implemented in
+;  InstCombiner::foldICmpBitCastConstant
+; Specifically, folding:
+;   icmp <pred> iN X, C
+;  where X = bitcast <M x iK> (shufflevector <M x iK> %vec, undef, SC)) to iN
+;    and C is a splat of a K-bit pattern
+;    and SC is a constant vector = <C', C', C', ..., C'>
+; Into:
+;  %E = extractelement <M x iK> %vec, i32 C'
+;  icmp <pred> iK %E, trunc(C)
+
+define i1 @test_i1_0(i1 %val) {
+; CHECK-LABEL: @test_i1_0(
+; CHECK-NEXT:    [[COND:%.*]] = xor i1 [[VAL:%.*]], true
+; CHECK-NEXT:    ret i1 [[COND]]
+;
+  %insvec = insertelement <4 x i1> poison, i1 %val, i32 0
+  %vec = shufflevector <4 x i1> %insvec, <4 x i1> undef, <4 x i32> zeroinitializer
+  %cast = bitcast <4 x i1> %vec to i4
+  %cond = icmp eq i4 %cast, 0
+  ret i1 %cond
+}
+
+define i1 @test_i1_0_2(i1 %val) {
+; CHECK-LABEL: @test_i1_0_2(
+; CHECK-NEXT:    [[COND:%.*]] = xor i1 [[VAL:%.*]], true
+; CHECK-NEXT:    ret i1 [[COND]]
+;
+  %insvec = insertelement <4 x i1> poison, i1 %val, i32 2
+  %vec = shufflevector <4 x i1> %insvec, <4 x i1> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
+  %cast = bitcast <4 x i1> %vec to i4
+  %cond = icmp eq i4 %cast, 0
+  ret i1 %cond
+}
+
+define i1 @test_i1_m1(i1 %val) {
+; CHECK-LABEL: @test_i1_m1(
+; CHECK-NEXT:    ret i1 [[VAL:%.*]]
+;
+  %insvec = insertelement <4 x i1> poison, i1 %val, i32 0
+  %vec = shufflevector <4 x i1> %insvec, <4 x i1> undef, <4 x i32> zeroinitializer
+  %cast = bitcast <4 x i1> %vec to i4
+  %cond = icmp eq i4 %cast, -1
+  ret i1 %cond
+}
+
+define i1 @test_i8_pattern(i8 %val) {
+; CHECK-LABEL: @test_i8_pattern(
+; CHECK-NEXT:    [[COND:%.*]] = icmp eq i8 [[VAL:%.*]], 72
+; CHECK-NEXT:    ret i1 [[COND]]
+;
+  %insvec = insertelement <4 x i8> poison, i8 %val, i32 0
+  %vec = shufflevector <4 x i8> %insvec, <4 x i8> undef, <4 x i32> zeroinitializer
+  %cast = bitcast <4 x i8> %vec to i32
+  %cond = icmp eq i32 %cast, 1212696648
+  ret i1 %cond
+}
+
+define i1 @test_i8_pattern_2(i8 %val) {
+; CHECK-LABEL: @test_i8_pattern_2(
+; CHECK-NEXT:    [[COND:%.*]] = icmp eq i8 [[VAL:%.*]], 72
+; CHECK-NEXT:    ret i1 [[COND]]
+;
+  %insvec = insertelement <4 x i8> poison, i8 %val, i32 2
+  %vec = shufflevector <4 x i8> %insvec, <4 x i8> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
+  %cast = bitcast <4 x i8> %vec to i32
+  %cond = icmp eq i32 %cast, 1212696648
+  ret i1 %cond
+}
+
+; Make sure we don't try to fold if the shufflemask has differing element values
+define i1 @test_i8_pattern_3(<4 x i8> %invec) {
+; CHECK-LABEL: @test_i8_pattern_3(
+; CHECK-NEXT:    [[VEC:%.*]] = shufflevector <4 x i8> [[INVEC:%.*]], <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+; CHECK-NEXT:    [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
+; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696648
+; CHECK-NEXT:    ret i1 [[COND]]
+;
+  %vec = shufflevector <4 x i8> %invec, <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+  %cast = bitcast <4 x i8> %vec to i32
+  %cond = icmp eq i32 %cast, 1212696648
+  ret i1 %cond
+}
+
+; Make sure we don't try to fold if the compared-to constant isn't a splatted value
+define i1 @test_i8_nopattern(i8 %val) {
+; CHECK-LABEL: @test_i8_nopattern(
+; CHECK-NEXT:    [[INSVEC:%.*]] = insertelement <4 x i8> poison, i8 [[VAL:%.*]], i32 0
+; CHECK-NEXT:    [[VEC:%.*]] = shufflevector <4 x i8> [[INSVEC]], <4 x i8> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
+; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696647
+; CHECK-NEXT:    ret i1 [[COND]]
+;
+  %insvec = insertelement <4 x i8> poison, i8 %val, i32 0
+  %vec = shufflevector <4 x i8> %insvec, <4 x i8> undef, <4 x i32> zeroinitializer
+  %cast = bitcast <4 x i8> %vec to i32
+  %cond = icmp eq i32 %cast, 1212696647
+  ret i1 %cond
+}
+
+; Verify that we fold more than just the eq predicate
+define i1 @test_i8_ult_pattern(i8 %val) {
+; CHECK-LABEL: @test_i8_ult_pattern(
+; CHECK-NEXT:    [[COND:%.*]] = icmp ult i8 [[VAL:%.*]], 72
+; CHECK-NEXT:    ret i1 [[COND]]
+;
+  %insvec = insertelement <4 x i8> poison, i8 %val, i32 0
+  %vec = shufflevector <4 x i8> %insvec, <4 x i8> undef, <4 x i32> zeroinitializer
+  %cast = bitcast <4 x i8> %vec to i32
+  %cond = icmp ult i32 %cast, 1212696648
+  ret i1 %cond
+}
+
+define i1 @extending_shuffle_with_weird_types(<2 x i9> %v) {
+; CHECK-LABEL: @extending_shuffle_with_weird_types(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i9> [[V:%.*]], i32 0
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i9 [[TMP1]], 1
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %splat = shufflevector <2 x i9> %v, <2 x i9> undef, <3 x i32> zeroinitializer
+  %cast = bitcast <3 x i9> %splat to i27
+  %cmp = icmp slt i27 %cast, 262657 ; 0x040201
+  ret i1 %cmp
+}
diff --git a/llvm/test/Transforms/InstCombine/inselt-binop-inseltpoison.ll b/llvm/test/Transforms/InstCombine/inselt-binop-inseltpoison.ll
new file mode 100644
index 0000000000000..856eb61ba0ba0
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/inselt-binop-inseltpoison.ll
@@ -0,0 +1,635 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine %s | FileCheck %s
+
+define <2 x i8> @add_constant(i8 %x) {
+; CHECK-LABEL: @add_constant(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 undef>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = add <2 x i8> %ins, <i8 42, i8 undef>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @add_constant_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @add_constant_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 -42>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = add <2 x i8> %ins, <i8 42, i8 -42>
+  ret <2 x i8> %bo
+}
+
+; IR flags are not required, but they should propagate.
+
+define <2 x i8> @sub_constant_op0(i8 %x) {
+; CHECK-LABEL: @sub_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = sub nuw nsw <2 x i8> <i8 undef, i8 -42>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = sub nsw nuw <2 x i8> <i8 undef, i8 -42>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @sub_constant_op0_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @sub_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = sub nuw <2 x i8> <i8 42, i8 -42>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = sub nuw <2 x i8> <i8 42, i8 -42>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @sub_constant_op1(i8 %x) {
+; CHECK-LABEL: @sub_constant_op1(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 undef>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = sub nuw <2 x i8> %ins, <i8 42, i8 undef>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @sub_constant_op1_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @sub_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 42>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = sub nuw <2 x i8> %ins, <i8 42, i8 -42>
+  ret <2 x i8> %bo
+}
+
+define <3 x i8> @mul_constant(i8 %x) {
+; CHECK-LABEL: @mul_constant(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <3 x i8> poison, i8 [[X:%.*]], i32 2
+; CHECK-NEXT:    [[BO:%.*]] = mul <3 x i8> [[INS]], <i8 undef, i8 undef, i8 -42>
+; CHECK-NEXT:    ret <3 x i8> [[BO]]
+;
+  %ins = insertelement <3 x i8> poison, i8 %x, i32 2
+  %bo = mul <3 x i8> %ins, <i8 undef, i8 undef, i8 -42>
+  ret <3 x i8> %bo
+}
+
+define <3 x i8> @mul_constant_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @mul_constant_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <3 x i8> poison, i8 [[X:%.*]], i32 2
+; CHECK-NEXT:    [[BO:%.*]] = mul <3 x i8> [[INS]], <i8 42, i8 undef, i8 -42>
+; CHECK-NEXT:    ret <3 x i8> [[BO]]
+;
+  %ins = insertelement <3 x i8> poison, i8 %x, i32 2
+  %bo = mul <3 x i8> %ins, <i8 42, i8 undef, i8 -42>
+  ret <3 x i8> %bo
+}
+
+define <2 x i8> @shl_constant_op0(i8 %x) {
+; CHECK-LABEL: @shl_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = shl <2 x i8> <i8 undef, i8 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = shl <2 x i8> <i8 undef, i8 2>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @shl_constant_op0_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @shl_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = shl <2 x i8> <i8 5, i8 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = shl <2 x i8> <i8 5, i8 2>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @shl_constant_op1(i8 %x) {
+; CHECK-LABEL: @shl_constant_op1(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = shl nuw <2 x i8> [[INS]], <i8 5, i8 undef>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = shl nuw <2 x i8> %ins, <i8 5, i8 undef>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @shl_constant_op1_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @shl_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = shl nuw <2 x i8> [[INS]], <i8 5, i8 2>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = shl nuw <2 x i8> %ins, <i8 5, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @ashr_constant_op0(i8 %x) {
+; CHECK-LABEL: @ashr_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = ashr exact <2 x i8> <i8 undef, i8 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = ashr exact <2 x i8> <i8 undef, i8 2>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @ashr_constant_op0_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @ashr_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = ashr exact <2 x i8> <i8 5, i8 2>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @ashr_constant_op1(i8 %x) {
+; CHECK-LABEL: @ashr_constant_op1(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 undef>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = ashr <2 x i8> %ins, <i8 5, i8 undef>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @ashr_constant_op1_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @ashr_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 2>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = ashr <2 x i8> %ins, <i8 5, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @lshr_constant_op0(i8 %x) {
+; CHECK-LABEL: @lshr_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 undef>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = lshr <2 x i8> <i8 5, i8 undef>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @lshr_constant_op0_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @lshr_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = lshr <2 x i8> <i8 5, i8 2>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @lshr_constant_op1(i8 %x) {
+; CHECK-LABEL: @lshr_constant_op1(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = lshr exact <2 x i8> [[INS]], <i8 undef, i8 2>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = lshr exact <2 x i8> %ins, <i8 undef, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @lshr_constant_op1_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @lshr_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = lshr exact <2 x i8> [[INS]], <i8 5, i8 2>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = lshr exact <2 x i8> %ins, <i8 5, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @urem_constant_op0(i8 %x) {
+; CHECK-LABEL: @urem_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = urem <2 x i8> <i8 5, i8 undef>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = urem <2 x i8> <i8 5, i8 undef>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @urem_constant_op0_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @urem_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = urem <2 x i8> <i8 5, i8 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = urem <2 x i8> <i8 5, i8 2>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @urem_constant_op1(i8 %x) {
+; CHECK-LABEL: @urem_constant_op1(
+; CHECK-NEXT:    ret <2 x i8> undef
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = urem <2 x i8> %ins, <i8 undef, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @urem_constant_op1_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @urem_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = urem <2 x i8> [[INS]], <i8 5, i8 2>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = urem <2 x i8> %ins, <i8 5, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @srem_constant_op0(i8 %x) {
+; CHECK-LABEL: @srem_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = srem <2 x i8> <i8 5, i8 undef>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = srem <2 x i8> <i8 5, i8 undef>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @srem_constant_op0_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @srem_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = srem <2 x i8> <i8 5, i8 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = srem <2 x i8> <i8 5, i8 2>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @srem_constant_op1(i8 %x) {
+; CHECK-LABEL: @srem_constant_op1(
+; CHECK-NEXT:    ret <2 x i8> undef
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = srem <2 x i8> %ins, <i8 undef, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @srem_constant_op1_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @srem_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = srem <2 x i8> [[INS]], <i8 5, i8 2>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = srem <2 x i8> %ins, <i8 5, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @udiv_constant_op0(i8 %x) {
+; CHECK-LABEL: @udiv_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = udiv exact <2 x i8> <i8 5, i8 undef>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = udiv exact <2 x i8> <i8 5, i8 undef>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @udiv_constant_op0_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @udiv_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = udiv exact <2 x i8> <i8 5, i8 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = udiv exact <2 x i8> <i8 5, i8 2>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @udiv_constant_op1(i8 %x) {
+; CHECK-LABEL: @udiv_constant_op1(
+; CHECK-NEXT:    ret <2 x i8> undef
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = udiv <2 x i8> %ins, <i8 undef, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @udiv_constant_op1_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @udiv_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = udiv <2 x i8> [[INS]], <i8 5, i8 2>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = udiv <2 x i8> %ins, <i8 5, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @sdiv_constant_op0(i8 %x) {
+; CHECK-LABEL: @sdiv_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = sdiv <2 x i8> <i8 5, i8 undef>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = sdiv <2 x i8> <i8 5, i8 undef>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @sdiv_constant_op0_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @sdiv_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = sdiv <2 x i8> <i8 5, i8 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = sdiv <2 x i8> <i8 5, i8 2>, %ins
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @sdiv_constant_op1(i8 %x) {
+; CHECK-LABEL: @sdiv_constant_op1(
+; CHECK-NEXT:    ret <2 x i8> undef
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = sdiv exact <2 x i8> %ins, <i8 undef, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @sdiv_constant_op1_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @sdiv_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = sdiv exact <2 x i8> [[INS]], <i8 5, i8 2>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = sdiv exact <2 x i8> %ins, <i8 5, i8 2>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @and_constant(i8 %x) {
+; CHECK-LABEL: @and_constant(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = and <2 x i8> [[INS]], <i8 42, i8 undef>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = and <2 x i8> %ins, <i8 42, i8 undef>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @and_constant_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @and_constant_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = and <2 x i8> [[INS]], <i8 42, i8 -42>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = and <2 x i8> %ins, <i8 42, i8 -42>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @or_constant(i8 %x) {
+; CHECK-LABEL: @or_constant(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = or <2 x i8> [[INS]], <i8 undef, i8 -42>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = or <2 x i8> %ins, <i8 undef, i8 -42>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @or_constant_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @or_constant_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = or <2 x i8> [[INS]], <i8 42, i8 -42>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 1
+  %bo = or <2 x i8> %ins, <i8 42, i8 -42>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @xor_constant(i8 %x) {
+; CHECK-LABEL: @xor_constant(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = xor <2 x i8> [[INS]], <i8 42, i8 undef>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = xor <2 x i8> %ins, <i8 42, i8 undef>
+  ret <2 x i8> %bo
+}
+
+define <2 x i8> @xor_constant_not_undef_lane(i8 %x) {
+; CHECK-LABEL: @xor_constant_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = xor <2 x i8> [[INS]], <i8 42, i8 -42>
+; CHECK-NEXT:    ret <2 x i8> [[BO]]
+;
+  %ins = insertelement <2 x i8> poison, i8 %x, i32 0
+  %bo = xor <2 x i8> %ins, <i8 42, i8 -42>
+  ret <2 x i8> %bo
+}
+
+define <2 x float> @fadd_constant(float %x) {
+; CHECK-LABEL: @fadd_constant(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = fadd <2 x float> [[INS]], <float 4.200000e+01, float undef>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 0
+  %bo = fadd <2 x float> %ins, <float 42.0, float undef>
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fadd_constant_not_undef_lane(float %x) {
+; CHECK-LABEL: @fadd_constant_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = fadd <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 1
+  %bo = fadd <2 x float> %ins, <float 42.0, float -42.0>
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fsub_constant_op0(float %x) {
+; CHECK-LABEL: @fsub_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = fsub fast <2 x float> <float 4.200000e+01, float undef>, [[INS]]
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 0
+  %bo = fsub fast <2 x float> <float 42.0, float undef>, %ins
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fsub_constant_op0_not_undef_lane(float %x) {
+; CHECK-LABEL: @fsub_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = fsub nsz <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]]
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 1
+  %bo = fsub nsz <2 x float> <float 42.0, float -42.0>, %ins
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fsub_constant_op1(float %x) {
+; CHECK-LABEL: @fsub_constant_op1(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = fadd <2 x float> [[INS]], <float undef, float -4.200000e+01>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 1
+  %bo = fsub <2 x float> %ins, <float undef, float 42.0>
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fsub_constant_op1_not_undef_lane(float %x) {
+; CHECK-LABEL: @fsub_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = fadd <2 x float> [[INS]], <float -4.200000e+01, float 4.200000e+01>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 0
+  %bo = fsub <2 x float> %ins, <float 42.0, float -42.0>
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fmul_constant(float %x) {
+; CHECK-LABEL: @fmul_constant(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = fmul reassoc <2 x float> [[INS]], <float 4.200000e+01, float undef>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 0
+  %bo = fmul reassoc <2 x float> %ins, <float 42.0, float undef>
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fmul_constant_not_undef_lane(float %x) {
+; CHECK-LABEL: @fmul_constant_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = fmul <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 1
+  %bo = fmul <2 x float> %ins, <float 42.0, float -42.0>
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fdiv_constant_op0(float %x) {
+; CHECK-LABEL: @fdiv_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = fdiv nnan <2 x float> <float undef, float 4.200000e+01>, [[INS]]
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 1
+  %bo = fdiv nnan <2 x float> <float undef, float 42.0>, %ins
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fdiv_constant_op0_not_undef_lane(float %x) {
+; CHECK-LABEL: @fdiv_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = fdiv ninf <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]]
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 0
+  %bo = fdiv ninf <2 x float> <float 42.0, float -42.0>, %ins
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fdiv_constant_op1(float %x) {
+; CHECK-LABEL: @fdiv_constant_op1(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = fdiv <2 x float> [[INS]], <float 4.200000e+01, float undef>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 0
+  %bo = fdiv <2 x float> %ins, <float 42.0, float undef>
+  ret <2 x float> %bo
+}
+
+define <2 x float> @fdiv_constant_op1_not_undef_lane(float %x) {
+; CHECK-LABEL: @fdiv_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = fdiv <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 0
+  %bo = fdiv <2 x float> %ins, <float 42.0, float -42.0>
+  ret <2 x float> %bo
+}
+
+define <2 x float> @frem_constant_op0(float %x) {
+; CHECK-LABEL: @frem_constant_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = frem fast <2 x float> <float 4.200000e+01, float undef>, [[INS]]
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 0
+  %bo = frem fast <2 x float> <float 42.0, float undef>, %ins
+  ret <2 x float> %bo
+}
+
+define <2 x float> @frem_constant_op0_not_undef_lane(float %x) {
+; CHECK-LABEL: @frem_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = frem <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]]
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 1
+  %bo = frem <2 x float> <float 42.0, float -42.0>, %ins
+  ret <2 x float> %bo
+}
+
+define <2 x float> @frem_constant_op1(float %x) {
+; CHECK-LABEL: @frem_constant_op1(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = frem ninf <2 x float> [[INS]], <float undef, float 4.200000e+01>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 1
+  %bo = frem ninf <2 x float> %ins, <float undef, float 42.0>
+  ret <2 x float> %bo
+}
+
+define <2 x float> @frem_constant_op1_not_undef_lane(float %x) {
+; CHECK-LABEL: @frem_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = frem nnan <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
+; CHECK-NEXT:    ret <2 x float> [[BO]]
+;
+  %ins = insertelement <2 x float> poison, float %x, i32 0
+  %bo = frem nnan <2 x float> %ins, <float 42.0, float -42.0>
+  ret <2 x float> %bo
+}
+
diff --git a/llvm/test/Transforms/InstCombine/insert-const-shuf.ll b/llvm/test/Transforms/InstCombine/insert-const-shuf.ll
index f1f2b650bea92..6c3680dbc68f1 100644
--- a/llvm/test/Transforms/InstCombine/insert-const-shuf.ll
+++ b/llvm/test/Transforms/InstCombine/insert-const-shuf.ll
@@ -5,7 +5,7 @@
 
 define <4 x float> @PR29126(<4 x float> %x) {
 ; CHECK-LABEL: @PR29126(
-; CHECK-NEXT:    [[INS:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float undef, float 1.000000e+00, float 2.000000e+00, float 4.200000e+01>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    [[INS:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, float 1.000000e+00, float 2.000000e+00, float 4.200000e+01>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
 ; CHECK-NEXT:    ret <4 x float> [[INS]]
 ;
   %shuf = shufflevector <4 x float> %x, <4 x float> <float undef, float 1.0, float 2.0, float undef>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
@@ -17,7 +17,7 @@ define <4 x float> @PR29126(<4 x float> %x) {
 
 define <4 x float> @twoInserts(<4 x float> %x) {
 ; CHECK-LABEL: @twoInserts(
-; CHECK-NEXT:    [[INS2:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float undef, float 0.000000e+00, float 4.200000e+01, float 1.100000e+01>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    [[INS2:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, float 0.000000e+00, float 4.200000e+01, float 1.100000e+01>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
 ; CHECK-NEXT:    ret <4 x float> [[INS2]]
 ;
   %shuf = shufflevector <4 x float> %x, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
@@ -28,7 +28,7 @@ define <4 x float> @twoInserts(<4 x float> %x) {
 
 define <4 x i32> @shuffleRetain(<4 x i32> %base) {
 ; CHECK-LABEL: @shuffleRetain(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[BASE:%.*]], <4 x i32> <i32 undef, i32 undef, i32 undef, i32 1>, <4 x i32> <i32 1, i32 2, i32 undef, i32 7>
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[BASE:%.*]], <4 x i32> <i32 poison, i32 poison, i32 poison, i32 1>, <4 x i32> <i32 1, i32 2, i32 undef, i32 7>
 ; CHECK-NEXT:    ret <4 x i32> [[SHUF]]
 ;
   %shuf = shufflevector <4 x i32> %base, <4 x i32> <i32 4, i32 3, i32 2, i32 1>, <4 x i32> <i32 1, i32 2, i32 undef, i32 7>
@@ -39,7 +39,7 @@ define <4 x i32> @shuffleRetain(<4 x i32> %base) {
 
 define <4 x float> @disguisedSelect(<4 x float> %x) {
 ; CHECK-LABEL: @disguisedSelect(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float undef, float 1.000000e+00, float 2.000000e+00, float undef>, <4 x i32> <i32 undef, i32 6, i32 5, i32 3>
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, float 1.000000e+00, float 2.000000e+00, float poison>, <4 x i32> <i32 undef, i32 6, i32 5, i32 3>
 ; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i32 0
 ; CHECK-NEXT:    ret <4 x float> [[INS]]
 ;
@@ -52,7 +52,7 @@ define <4 x float> @disguisedSelect(<4 x float> %x) {
 
 define <4 x float> @notSelectButNoMaskDifference(<4 x float> %x) {
 ; CHECK-LABEL: @notSelectButNoMaskDifference(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float undef, float 1.000000e+00, float 2.000000e+00, float undef>, <4 x i32> <i32 1, i32 5, i32 6, i32 undef>
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, float 1.000000e+00, float 2.000000e+00, float poison>, <4 x i32> <i32 1, i32 5, i32 6, i32 undef>
 ; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i32 3
 ; CHECK-NEXT:    ret <4 x float> [[INS]]
 ;
@@ -65,7 +65,7 @@ define <4 x float> @notSelectButNoMaskDifference(<4 x float> %x) {
 
 define <4 x float> @tooRisky(<4 x float> %x) {
 ; CHECK-LABEL: @tooRisky(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float 1.000000e+00, float undef, float undef, float undef>, <4 x i32> <i32 1, i32 4, i32 4, i32 undef>
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float 1.000000e+00, float poison, float poison, float poison>, <4 x i32> <i32 1, i32 4, i32 4, i32 undef>
 ; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x float> [[SHUF]], float 4.000000e+00, i32 3
 ; CHECK-NEXT:    ret <4 x float> [[INS]]
 ;
@@ -79,7 +79,7 @@ define <4 x float> @tooRisky(<4 x float> %x) {
 
 define <3 x float> @twoShufUses(<3 x float> %x) {
 ; CHECK-LABEL: @twoShufUses(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float undef, float 1.000000e+00, float 2.000000e+00>, <3 x i32> <i32 0, i32 4, i32 5>
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <3 x float> [[X:%.*]], <3 x float> <float poison, float 1.000000e+00, float 2.000000e+00>, <3 x i32> <i32 0, i32 4, i32 5>
 ; CHECK-NEXT:    [[INS:%.*]] = insertelement <3 x float> [[SHUF]], float 4.200000e+01, i2 1
 ; CHECK-NEXT:    [[ADD:%.*]] = fadd <3 x float> [[SHUF]], [[INS]]
 ; CHECK-NEXT:    ret <3 x float> [[ADD]]
@@ -94,7 +94,7 @@ define <3 x float> @twoShufUses(<3 x float> %x) {
 
 define <5 x i8> @longerMask(<3 x i8> %x) {
 ; CHECK-LABEL: @longerMask(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> <i8 undef, i8 1, i8 undef>, <5 x i32> <i32 2, i32 1, i32 4, i32 undef, i32 undef>
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> <i8 poison, i8 1, i8 poison>, <5 x i32> <i32 2, i32 1, i32 4, i32 undef, i32 undef>
 ; CHECK-NEXT:    [[INS:%.*]] = insertelement <5 x i8> [[SHUF]], i8 42, i17 4
 ; CHECK-NEXT:    ret <5 x i8> [[INS]]
 ;
@@ -107,7 +107,7 @@ define <5 x i8> @longerMask(<3 x i8> %x) {
 
 define <3 x i8> @shorterMask(<5 x i8> %x) {
 ; CHECK-LABEL: @shorterMask(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <5 x i8> [[X:%.*]], <5 x i8> undef, <3 x i32> <i32 undef, i32 1, i32 4>
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <5 x i8> [[X:%.*]], <5 x i8> poison, <3 x i32> <i32 undef, i32 1, i32 4>
 ; CHECK-NEXT:    [[INS:%.*]] = insertelement <3 x i8> [[SHUF]], i8 42, i21 0
 ; CHECK-NEXT:    ret <3 x i8> [[INS]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll b/llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
new file mode 100644
index 0000000000000..64958b9ccd5a7
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll
@@ -0,0 +1,735 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine %s | FileCheck %s
+
+define <1 x i8> @test1(<8 x i8> %in) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    [[VEC:%.*]] = shufflevector <8 x i8> [[IN:%.*]], <8 x i8> undef, <1 x i32> <i32 5>
+; CHECK-NEXT:    ret <1 x i8> [[VEC]]
+;
+  %val = extractelement <8 x i8> %in, i32 5
+  %vec = insertelement <1 x i8> poison, i8 %val, i32 0
+  ret <1 x i8> %vec
+}
+
+define <4 x i16> @test2(<8 x i16> %in, <8 x i16> %in2) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    [[VEC_3:%.*]] = shufflevector <8 x i16> [[IN2:%.*]], <8 x i16> [[IN:%.*]], <4 x i32> <i32 11, i32 9, i32 0, i32 10>
+; CHECK-NEXT:    ret <4 x i16> [[VEC_3]]
+;
+  %elt0 = extractelement <8 x i16> %in, i32 3
+  %elt1 = extractelement <8 x i16> %in, i32 1
+  %elt2 = extractelement <8 x i16> %in2, i32 0
+  %elt3 = extractelement <8 x i16> %in, i32 2
+
+  %vec.0 = insertelement <4 x i16> poison, i16 %elt0, i32 0
+  %vec.1 = insertelement <4 x i16> %vec.0, i16 %elt1, i32 1
+  %vec.2 = insertelement <4 x i16> %vec.1, i16 %elt2, i32 2
+  %vec.3 = insertelement <4 x i16> %vec.2, i16 %elt3, i32 3
+
+  ret <4 x i16> %vec.3
+}
+
+define <2 x i64> @test_vcopyq_lane_p64(<2 x i64> %a, <1 x i64> %b) {
+; CHECK-LABEL: @test_vcopyq_lane_p64(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <1 x i64> [[B:%.*]], <1 x i64> undef, <2 x i32> <i32 0, i32 undef>
+; CHECK-NEXT:    [[RES:%.*]] = shufflevector <2 x i64> [[A:%.*]], <2 x i64> [[TMP1]], <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT:    ret <2 x i64> [[RES]]
+;
+  %elt = extractelement <1 x i64> %b, i32 0
+  %res = insertelement <2 x i64> %a, i64 %elt, i32 1
+  ret <2 x i64> %res
+}
+
+; PR2109: https://llvm.org/bugs/show_bug.cgi?id=2109
+
+define <4 x float> @widen_extract2(<4 x float> %ins, <2 x float> %ext) {
+; CHECK-LABEL: @widen_extract2(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x float> [[EXT:%.*]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[I2:%.*]] = shufflevector <4 x float> [[INS:%.*]], <4 x float> [[TMP1]], <4 x i32> <i32 0, i32 4, i32 2, i32 5>
+; CHECK-NEXT:    ret <4 x float> [[I2]]
+;
+  %e1 = extractelement <2 x float> %ext, i32 0
+  %e2 = extractelement <2 x float> %ext, i32 1
+  %i1 = insertelement <4 x float> %ins, float %e1, i32 1
+  %i2 = insertelement <4 x float> %i1, float %e2, i32 3
+  ret <4 x float> %i2
+}
+
+define <4 x float> @widen_extract3(<4 x float> %ins, <3 x float> %ext) {
+; CHECK-LABEL: @widen_extract3(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <3 x float> [[EXT:%.*]], <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
+; CHECK-NEXT:    [[I3:%.*]] = shufflevector <4 x float> [[INS:%.*]], <4 x float> [[TMP1]], <4 x i32> <i32 6, i32 5, i32 4, i32 3>
+; CHECK-NEXT:    ret <4 x float> [[I3]]
+;
+  %e1 = extractelement <3 x float> %ext, i32 0
+  %e2 = extractelement <3 x float> %ext, i32 1
+  %e3 = extractelement <3 x float> %ext, i32 2
+  %i1 = insertelement <4 x float> %ins, float %e1, i32 2
+  %i2 = insertelement <4 x float> %i1, float %e2, i32 1
+  %i3 = insertelement <4 x float> %i2, float %e3, i32 0
+  ret <4 x float> %i3
+}
+
+define <8 x float> @widen_extract4(<8 x float> %ins, <2 x float> %ext) {
+; CHECK-LABEL: @widen_extract4(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x float> [[EXT:%.*]], <2 x float> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[I1:%.*]] = shufflevector <8 x float> [[INS:%.*]], <8 x float> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 8, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    ret <8 x float> [[I1]]
+;
+  %e1 = extractelement <2 x float> %ext, i32 0
+  %i1 = insertelement <8 x float> %ins, float %e1, i32 2
+  ret <8 x float> %i1
+}
+
+; PR26015: https://llvm.org/bugs/show_bug.cgi?id=26015
+; The widening shuffle must be inserted before any uses.
+
+define <8 x i16> @pr26015(<4 x i16> %t0) {
+; CHECK-LABEL: @pr26015(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i16> [[T0:%.*]], <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[T5:%.*]] = shufflevector <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 0, i16 0, i16 0, i16 poison>, <8 x i16> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 10, i32 4, i32 5, i32 6, i32 11>
+; CHECK-NEXT:    ret <8 x i16> [[T5]]
+;
+  %t1 = extractelement <4 x i16> %t0, i32 2
+  %t2 = insertelement <8 x i16> zeroinitializer, i16 %t1, i32 3
+  %t3 = insertelement <8 x i16> %t2, i16 0, i32 6
+  %t4 = extractelement <4 x i16> %t0, i32 3
+  %t5 = insertelement <8 x i16> %t3, i16 %t4, i32 7
+  ret <8 x i16> %t5
+}
+
+; PR25999: https://llvm.org/bugs/show_bug.cgi?id=25999
+; TODO: The widening shuffle could be inserted at the start of the function to allow the first extract to use it.
+
+define <8 x i16> @pr25999(<4 x i16> %t0, i1 %b) {
+; CHECK-LABEL: @pr25999(
+; CHECK-NEXT:    [[T1:%.*]] = extractelement <4 x i16> [[T0:%.*]], i32 2
+; CHECK-NEXT:    br i1 [[B:%.*]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i16> [[T0]], <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[T3:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 0, i16 0, i16 0, i16 poison>, i16 [[T1]], i32 3
+; CHECK-NEXT:    [[T5:%.*]] = shufflevector <8 x i16> [[T3]], <8 x i16> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 11>
+; CHECK-NEXT:    ret <8 x i16> [[T5]]
+; CHECK:       end:
+; CHECK-NEXT:    [[A1:%.*]] = add i16 [[T1]], 4
+; CHECK-NEXT:    [[T6:%.*]] = insertelement <8 x i16> <i16 poison, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 [[A1]], i32 0
+; CHECK-NEXT:    ret <8 x i16> [[T6]]
+;
+
+  %t1 = extractelement <4 x i16> %t0, i32 2
+  br i1 %b, label %if, label %end
+
+if:
+  %t2 = insertelement <8 x i16> zeroinitializer, i16 %t1, i32 3
+  %t3 = insertelement <8 x i16> %t2, i16 0, i32 6
+  %t4 = extractelement <4 x i16> %t0, i32 3
+  %t5 = insertelement <8 x i16> %t3, i16 %t4, i32 7
+  ret <8 x i16> %t5
+
+end:
+  %a1 = add i16 %t1, 4
+  %t6 = insertelement <8 x i16> zeroinitializer, i16 %a1, i32 0
+  ret <8 x i16> %t6
+}
+
+; The widening shuffle must be inserted at a valid point (after the PHIs).
+
+define <4 x double> @pr25999_phis1(i1 %c, <2 x double> %a, <4 x double> %b) {
+; CHECK-LABEL: @pr25999_phis1(
+; CHECK-NEXT:  bb1:
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]
+; CHECK:       bb2:
+; CHECK-NEXT:    [[R:%.*]] = call <2 x double> @dummy(<2 x double> [[A:%.*]])
+; CHECK-NEXT:    br label [[BB3]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[TMP1:%.*]] = phi <2 x double> [ [[A]], [[BB1:%.*]] ], [ [[R]], [[BB2]] ]
+; CHECK-NEXT:    [[TMP2:%.*]] = phi <4 x double> [ [[B:%.*]], [[BB1]] ], [ zeroinitializer, [[BB2]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP0]], <4 x i32> <i32 0, i32 1, i32 4, i32 3>
+; CHECK-NEXT:    ret <4 x double> [[TMP4]]
+;
+bb1:
+  br i1 %c, label %bb2, label %bb3
+
+bb2:
+  %r = call <2 x double> @dummy(<2 x double> %a)
+  br label %bb3
+
+bb3:
+  %tmp1 = phi <2 x double> [ %a, %bb1 ], [ %r, %bb2 ]
+  %tmp2 = phi <4 x double> [ %b, %bb1 ], [ zeroinitializer, %bb2 ]
+  %tmp3 = extractelement <2 x double> %tmp1, i32 0
+  %tmp4 = insertelement <4 x double> %tmp2, double %tmp3, i32 2
+  ret <4 x double> %tmp4
+}
+
+declare <2 x double> @dummy(<2 x double>)
+
+define <4 x double> @pr25999_phis2(i1 %c, <2 x double> %a, <4 x double> %b) {
+; CHECK-LABEL: @pr25999_phis2(
+; CHECK-NEXT:  bb1:
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[BB2:%.*]], label [[BB3:%.*]]
+; CHECK:       bb2:
+; CHECK-NEXT:    [[R:%.*]] = call <2 x double> @dummy(<2 x double> [[A:%.*]])
+; CHECK-NEXT:    br label [[BB3]]
+; CHECK:       bb3:
+; CHECK-NEXT:    [[TMP1:%.*]] = phi <2 x double> [ [[A]], [[BB1:%.*]] ], [ [[R]], [[BB2]] ]
+; CHECK-NEXT:    [[TMP2:%.*]] = phi <4 x double> [ [[B:%.*]], [[BB1]] ], [ zeroinitializer, [[BB2]] ]
+; CHECK-NEXT:    [[D:%.*]] = fadd <2 x double> [[TMP1]], [[TMP1]]
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <2 x double> [[D]], <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP0]], <4 x i32> <i32 0, i32 1, i32 4, i32 3>
+; CHECK-NEXT:    ret <4 x double> [[TMP4]]
+;
+bb1:
+  br i1 %c, label %bb2, label %bb3
+
+bb2:
+  %r = call <2 x double> @dummy(<2 x double> %a)
+  br label %bb3
+
+bb3:
+  %tmp1 = phi <2 x double> [ %a, %bb1 ], [ %r, %bb2 ]
+  %tmp2 = phi <4 x double> [ %b, %bb1 ], [ zeroinitializer, %bb2 ]
+  %d = fadd <2 x double> %tmp1, %tmp1
+  %tmp3 = extractelement <2 x double> %d, i32 0
+  %tmp4 = insertelement <4 x double> %tmp2, double %tmp3, i32 2
+  ret <4 x double> %tmp4
+}
+
+; PR26354: https://llvm.org/bugs/show_bug.cgi?id=26354
+; Don't create a shufflevector if we know that we're not going to replace the insertelement.
+
+define double @pr26354(<2 x double>* %tmp, i1 %B) {
+; CHECK-LABEL: @pr26354(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[LD:%.*]] = load <2 x double>, <2 x double>* [[TMP:%.*]], align 16
+; CHECK-NEXT:    br i1 [[B:%.*]], label [[IF:%.*]], label [[END:%.*]]
+; CHECK:       if:
+; CHECK-NEXT:    [[E2:%.*]] = extractelement <2 x double> [[LD]], i32 1
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double poison>, double [[E2]], i32 3
+; CHECK-NEXT:    br label [[END]]
+; CHECK:       end:
+; CHECK-NEXT:    [[PH:%.*]] = phi <4 x double> [ undef, [[ENTRY:%.*]] ], [ [[I1]], [[IF]] ]
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <2 x double> [[LD]], i32 0
+; CHECK-NEXT:    [[E3:%.*]] = extractelement <4 x double> [[PH]], i32 1
+; CHECK-NEXT:    [[MU:%.*]] = fmul double [[E1]], [[E3]]
+; CHECK-NEXT:    ret double [[MU]]
+;
+
+entry:
+  %ld = load <2 x double>, <2 x double>* %tmp
+  %e1 = extractelement <2 x double> %ld, i32 0
+  %e2 = extractelement <2 x double> %ld, i32 1
+  br i1 %B, label %if, label %end
+
+if:
+  %i1 = insertelement <4 x double> zeroinitializer, double %e2, i32 3
+  br label %end
+
+end:
+  %ph = phi <4 x double> [ undef, %entry ], [ %i1, %if ]
+  %e3 = extractelement <4 x double> %ph, i32 1
+  %mu = fmul double %e1, %e3
+  ret double %mu
+}
+
+; https://llvm.org/bugs/show_bug.cgi?id=30923
+; Delete the widening shuffle if we're not going to reduce the extract/insert to a shuffle.
+
+define <4 x float> @PR30923(<2 x float> %x) {
+; CHECK-LABEL: @PR30923(
+; CHECK-NEXT:  bb1:
+; CHECK-NEXT:    [[EXT1:%.*]] = extractelement <2 x float> [[X:%.*]], i32 1
+; CHECK-NEXT:    store float [[EXT1]], float* undef, align 4
+; CHECK-NEXT:    br label [[BB2:%.*]]
+; CHECK:       bb2:
+; CHECK-NEXT:    [[EXT2:%.*]] = extractelement <2 x float> [[X]], i32 0
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float poison, float poison>, float [[EXT2]], i32 2
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float [[EXT1]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[INS2]]
+;
+bb1:
+  %ext1 = extractelement <2 x float> %x, i32 1
+  store float %ext1, float* undef, align 4
+  br label %bb2
+
+bb2:
+  %widen = shufflevector <2 x float> %x, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %ext2 = extractelement <4 x float> %widen, i32 0
+  %ins1 = insertelement <4 x float> <float 0.0, float 0.0, float undef, float undef>, float %ext2, i32 2
+  %ins2 = insertelement <4 x float> %ins1, float %ext1, i32 3
+  ret <4 x float> %ins2
+}
+
+; Don't insert extractelements from the wider vector before the def of the index operand.
+
+define <4 x i32> @extractelt_insertion(<2 x i32> %x, i32 %y) {
+; CHECK-LABEL: @extractelt_insertion(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[B:%.*]] = shufflevector <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, <4 x i32> [[TMP0]], <4 x i32> <i32 0, i32 1, i32 2, i32 5>
+; CHECK-NEXT:    [[C:%.*]] = add i32 [[Y:%.*]], 3
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 [[C]]
+; CHECK-NEXT:    [[E:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT:    [[RET:%.*]] = select i1 [[E]], <4 x i32> [[B]], <4 x i32> zeroinitializer
+; CHECK-NEXT:    ret <4 x i32> [[RET]]
+;
+entry:
+  %a = extractelement <2 x i32> %x, i32 1
+  %b = insertelement <4 x i32> zeroinitializer, i32 %a, i64 3
+  %c = add i32 %y, 3
+  %d = extractelement <2 x i32> %x, i32 %c
+  %e = icmp eq i32 %d, 0
+  %ret = select i1 %e, <4 x i32> %b, <4 x i32> zeroinitializer
+  ret <4 x i32> %ret
+}
+
+; PR34724: https://bugs.llvm.org/show_bug.cgi?id=34724
+
+define <4 x float> @collectShuffleElts(<2 x float> %x, float %y) {
+; CHECK-LABEL: @collectShuffleElts(
+; CHECK-NEXT:    [[X0:%.*]] = extractelement <2 x float> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[X1:%.*]] = extractelement <2 x float> [[X]], i32 1
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <4 x float> poison, float [[X0]], i32 1
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[X1]], i32 2
+; CHECK-NEXT:    [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[Y:%.*]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[V3]]
+;
+  %x0 = extractelement <2 x float> %x, i32 0
+  %x1 = extractelement <2 x float> %x, i32 1
+  %v1 = insertelement <4 x float> poison, float %x0, i32 1
+  %v2 = insertelement <4 x float> %v1, float %x1, i32 2
+  %v3 = insertelement <4 x float> %v2, float %y, i32 3
+  ret <4 x float> %v3
+}
+
+; Simplest case - insert scalar into undef, then shuffle that value in place into another vector.
+
+define <4 x float> @insert_shuffle(float %x, <4 x float> %y) {
+; CHECK-LABEL: @insert_shuffle(
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i32 0
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> poison, float %x, i32 0
+  %r = shufflevector <4 x float> %xv, <4 x float> %y, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  ret <4 x float> %r
+}
+
+; Insert scalar into some element of a dummy vector, then move it to a different element in another vector.
+
+define <4 x float> @insert_shuffle_translate(float %x, <4 x float> %y) {
+; CHECK-LABEL: @insert_shuffle_translate(
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i32 1
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> poison, float %x, i32 0
+  %r = shufflevector <4 x float> %xv, <4 x float> %y, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
+  ret <4 x float> %r
+}
+
+; The vector operand of the insert is irrelevant.
+
+define <4 x float> @insert_not_undef_shuffle_translate(float %x, <4 x float> %y, <4 x float> %q) {
+; CHECK-LABEL: @insert_not_undef_shuffle_translate(
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i32 2
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> %q, float %x, i32 3
+  %r = shufflevector <4 x float> %xv, <4 x float> %y, <4 x i32> <i32 4, i32 5, i32 3, i32 7>
+  ret <4 x float> %r
+}
+
+; The insert may be the 2nd operand of the shuffle. The shuffle mask can include undef elements.
+
+define <4 x float> @insert_not_undef_shuffle_translate_commute(float %x, <4 x float> %y, <4 x float> %q) {
+; CHECK-LABEL: @insert_not_undef_shuffle_translate_commute(
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i32 1
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> %q, float %x, i32 2
+  %r = shufflevector <4 x float> %y, <4 x float> %xv, <4 x i32> <i32 0, i32 6, i32 2, i32 undef>
+  ret <4 x float> %r
+}
+
+; Both shuffle operands may be inserts - choose the correct side.
+
+define <4 x float> @insert_insert_shuffle_translate(float %x1, float %x2, <4 x float> %q) {
+; CHECK-LABEL: @insert_insert_shuffle_translate(
+; CHECK-NEXT:    [[XV2:%.*]] = insertelement <4 x float> [[Q:%.*]], float [[X2:%.*]], i32 2
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[XV2]], float [[X1:%.*]], i32 1
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv1 = insertelement <4 x float> %q, float %x1, i32 0
+  %xv2 = insertelement <4 x float> %q, float %x2, i32 2
+  %r = shufflevector <4 x float> %xv1, <4 x float> %xv2, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
+  ret <4 x float> %r
+}
+
+; Both shuffle operands may be inserts - choose the correct side.
+
+define <4 x float> @insert_insert_shuffle_translate_commute(float %x1, float %x2, <4 x float> %q) {
+; CHECK-LABEL: @insert_insert_shuffle_translate_commute(
+; CHECK-NEXT:    [[XV1:%.*]] = insertelement <4 x float> [[Q:%.*]], float [[X1:%.*]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[XV1]], float [[X2:%.*]], i32 1
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv1 = insertelement <4 x float> %q, float %x1, i32 0
+  %xv2 = insertelement <4 x float> %q, float %x2, i32 2
+  %r = shufflevector <4 x float> %xv1, <4 x float> %xv2, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
+  ret <4 x float> %r
+}
+
+; Negative test - this only works if the shuffle is choosing exactly 1 element from 1 of the inputs.
+; TODO: But this could be a special-case because we're inserting into the same base vector.
+
+define <4 x float> @insert_insert_shuffle_translate_wrong_mask(float %x1, float %x2, <4 x float> %q) {
+; CHECK-LABEL: @insert_insert_shuffle_translate_wrong_mask(
+; CHECK-NEXT:    [[XV1:%.*]] = insertelement <4 x float> [[Q:%.*]], float [[X1:%.*]], i32 0
+; CHECK-NEXT:    [[XV2:%.*]] = insertelement <4 x float> [[Q]], float [[X2:%.*]], i32 2
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[XV1]], <4 x float> [[XV2]], <4 x i32> <i32 0, i32 6, i32 2, i32 7>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv1 = insertelement <4 x float> %q, float %x1, i32 0
+  %xv2 = insertelement <4 x float> %q, float %x2, i32 2
+  %r = shufflevector <4 x float> %xv1, <4 x float> %xv2, <4 x i32> <i32 0, i32 6, i32 2, i32 7>
+  ret <4 x float> %r
+}
+
+; The insert may have other uses.
+
+declare void @use(<4 x float>)
+
+define <4 x float> @insert_not_undef_shuffle_translate_commute_uses(float %x, <4 x float> %y, <4 x float> %q) {
+; CHECK-LABEL: @insert_not_undef_shuffle_translate_commute_uses(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> [[Q:%.*]], float [[X:%.*]], i32 2
+; CHECK-NEXT:    call void @use(<4 x float> [[XV]])
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X]], i32 0
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> %q, float %x, i32 2
+  call void @use(<4 x float> %xv)
+  %r = shufflevector <4 x float> %y, <4 x float> %xv, <4 x i32> <i32 6, i32 undef, i32 2, i32 3>
+  ret <4 x float> %r
+}
+
+; Negative test - size-changing shuffle.
+
+define <5 x float> @insert_not_undef_shuffle_translate_commute_lengthen(float %x, <4 x float> %y, <4 x float> %q) {
+; CHECK-LABEL: @insert_not_undef_shuffle_translate_commute_lengthen(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 2
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[Y:%.*]], <4 x float> [[XV]], <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <5 x float> [[R]]
+;
+  %xv = insertelement <4 x float> %q, float %x, i32 2
+  %r = shufflevector <4 x float> %y, <4 x float> %xv, <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef>
+  ret <5 x float> %r
+}
+
+define <4 x float> @insert_nonzero_index_splat(float %x) {
+; CHECK-LABEL: @insert_nonzero_index_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[SPLAT]]
+;
+  %xv = insertelement <4 x float> poison, float %x, i32 2
+  %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef>
+  ret <4 x float> %splat
+}
+
+define <3 x double> @insert_nonzero_index_splat_narrow(double %x) {
+; CHECK-LABEL: @insert_nonzero_index_splat_narrow(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <3 x double> [[TMP1]], <3 x double> undef, <3 x i32> <i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x double> [[SPLAT]]
+;
+  %xv = insertelement <4 x double> poison, double %x, i32 3
+  %splat = shufflevector <4 x double> %xv, <4 x double> undef, <3 x i32> <i32 3, i32 undef, i32 3>
+  ret <3 x double> %splat
+}
+
+define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) {
+; CHECK-LABEL: @insert_nonzero_index_splat_widen(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <5 x i7> undef, i7 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> undef, <5 x i32> <i32 undef, i32 0, i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    ret <5 x i7> [[SPLAT]]
+;
+  %xv = insertelement <4 x i7> poison, i7 %x, i32 1
+  %splat = shufflevector <4 x i7> %xv, <4 x i7> undef, <5 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 1>
+  ret <5 x i7> %splat
+}
+
+; Negative test - don't increase instruction count
+
+define <4 x float> @insert_nonzero_index_splat_extra_use(float %x) {
+; CHECK-LABEL: @insert_nonzero_index_splat_extra_use(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 2
+; CHECK-NEXT:    call void @use(<4 x float> [[XV]])
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[SPLAT]]
+;
+  %xv = insertelement <4 x float> poison, float %x, i32 2
+  call void @use(<4 x float> %xv)
+  %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef>
+  ret <4 x float> %splat
+}
+
+; Negative test - non-undef base vector
+
+define <4 x float> @insert_nonzero_index_splat_wrong_base(float %x, <4 x float> %y) {
+; CHECK-LABEL: @insert_nonzero_index_splat_wrong_base(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i32 2
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 3, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[SPLAT]]
+;
+  %xv = insertelement <4 x float> %y, float %x, i32 2
+  %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 3, i32 undef>
+  ret <4 x float> %splat
+}
+
+; Negative test - non-constant insert index
+
+define <4 x float> @insert_nonzero_index_splat_wrong_index(float %x, i32 %index) {
+; CHECK-LABEL: @insert_nonzero_index_splat_wrong_index(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 [[INDEX:%.*]]
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[SPLAT]]
+;
+  %xv = insertelement <4 x float> poison, float %x, i32 %index
+  %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
+  ret <4 x float> %splat
+}
+
+define <4 x float> @insert_in_splat(float %x) {
+; CHECK-LABEL: @insert_in_splat(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> poison, float %x, i32 0
+  %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
+  %r = insertelement <4 x float> %splat, float %x, i32 3
+  ret <4 x float> %r
+}
+
+define <4 x float> @insert_in_splat_extra_uses(float %x) {
+; CHECK-LABEL: @insert_in_splat_extra_uses(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    call void @use(<4 x float> [[XV]])
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
+; CHECK-NEXT:    call void @use(<4 x float> [[SPLAT]])
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> poison, float %x, i32 0
+  call void @use(<4 x float> %xv)
+  %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
+  call void @use(<4 x float> %splat)
+  %r = insertelement <4 x float> %splat, float %x, i32 3
+  ret <4 x float> %r
+}
+
+; Negative test - not a constant index insert
+
+define <4 x float> @insert_in_splat_variable_index(float %x, i32 %y) {
+; CHECK-LABEL: @insert_in_splat_variable_index(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[SPLAT]], float [[X]], i32 [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> poison, float %x, i32 0
+  %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
+  %r = insertelement <4 x float> %splat, float %x, i32 %y
+  ret <4 x float> %r
+}
+
+; Negative test - not a splat shuffle
+
+define <4 x float> @insert_in_nonsplat(float %x, <4 x float> %y) {
+; CHECK-LABEL: @insert_in_nonsplat(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> [[Y:%.*]], <4 x i32> <i32 undef, i32 0, i32 4, i32 undef>
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[SPLAT]], float [[X]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> poison, float %x, i32 0
+  %splat = shufflevector <4 x float> %xv, <4 x float> %y, <4 x i32> <i32 undef, i32 0, i32 4, i32 undef>
+  %r = insertelement <4 x float> %splat, float %x, i32 3
+  ret <4 x float> %r
+}
+
+; Negative test - not a splat shuffle
+
+define <4 x float> @insert_in_nonsplat2(float %x, <4 x float> %y) {
+; CHECK-LABEL: @insert_in_nonsplat2(
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> [[SPLAT]], float [[X]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %xv = insertelement <4 x float> %y, float %x, i32 0
+  %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
+  %r = insertelement <4 x float> %splat, float %x, i32 3
+  ret <4 x float> %r
+}
+
+define <4 x i8> @shuf_identity_padding(<2 x i8> %x, i8 %y) {
+; CHECK-LABEL: @shuf_identity_padding(
+; CHECK-NEXT:    [[V1:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i32 2
+; CHECK-NEXT:    ret <4 x i8> [[V2]]
+;
+  %v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %x1 = extractelement <2 x i8> %x, i32 1
+  %v1 = insertelement <4 x i8> %v0, i8 %x1, i32 1
+  %v2 = insertelement <4 x i8> %v1, i8 %y, i32 2
+  ret <4 x i8> %v2
+}
+
+define <3 x i8> @shuf_identity_extract(<4 x i8> %x, i8 %y) {
+; CHECK-LABEL: @shuf_identity_extract(
+; CHECK-NEXT:    [[V1:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <3 x i8> [[V1]], i8 [[Y:%.*]], i32 2
+; CHECK-NEXT:    ret <3 x i8> [[V2]]
+;
+  %v0 = shufflevector <4 x i8> %x, <4 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 undef>
+  %x1 = extractelement <4 x i8> %x, i32 1
+  %v1 = insertelement <3 x i8> %v0, i8 %x1, i32 1
+  %v2 = insertelement <3 x i8> %v1, i8 %y, i32 2
+  ret <3 x i8> %v2
+}
+
+define <4 x float> @shuf_identity_extract_extra_use(<6 x float> %x, float %y) {
+; CHECK-LABEL: @shuf_identity_extract_extra_use(
+; CHECK-NEXT:    [[V0:%.*]] = shufflevector <6 x float> [[X:%.*]], <6 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 3>
+; CHECK-NEXT:    call void @use(<4 x float> [[V0]])
+; CHECK-NEXT:    [[V1:%.*]] = shufflevector <6 x float> [[X]], <6 x float> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 3>
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[Y:%.*]], i32 1
+; CHECK-NEXT:    ret <4 x float> [[V2]]
+;
+  %v0 = shufflevector <6 x float> %x, <6 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 3>
+  call void @use(<4 x float> %v0)
+  %x1 = extractelement <6 x float> %x, i32 2
+  %v1 = insertelement <4 x float> %v0, float %x1, i32 2
+  %v2 = insertelement <4 x float> %v1, float %y, i32 1
+  ret <4 x float> %v2
+}
+
+; Negative test - can't map variable index to shuffle mask.
+
+define <4 x i8> @shuf_identity_padding_variable_index(<2 x i8> %x, i8 %y, i32 %index) {
+; CHECK-LABEL: @shuf_identity_padding_variable_index(
+; CHECK-NEXT:    [[V0:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[X1:%.*]] = extractelement <2 x i8> [[X]], i32 [[INDEX:%.*]]
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <4 x i8> [[V0]], i8 [[X1]], i32 [[INDEX]]
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i32 2
+; CHECK-NEXT:    ret <4 x i8> [[V2]]
+;
+  %v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %x1 = extractelement <2 x i8> %x, i32 %index
+  %v1 = insertelement <4 x i8> %v0, i8 %x1, i32 %index
+  %v2 = insertelement <4 x i8> %v1, i8 %y, i32 2
+  ret <4 x i8> %v2
+}
+
+; Negative test - don't create arbitrary shuffle masks.
+
+define <4 x i8> @shuf_identity_padding_wrong_source_vec(<2 x i8> %x, i8 %y, <2 x i8> %other) {
+; CHECK-LABEL: @shuf_identity_padding_wrong_source_vec(
+; CHECK-NEXT:    [[V0:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[X1:%.*]] = extractelement <2 x i8> [[OTHER:%.*]], i32 1
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <4 x i8> [[V0]], i8 [[X1]], i32 1
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i32 2
+; CHECK-NEXT:    ret <4 x i8> [[V2]]
+;
+  %v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %x1 = extractelement <2 x i8> %other, i32 1
+  %v1 = insertelement <4 x i8> %v0, i8 %x1, i32 1
+  %v2 = insertelement <4 x i8> %v1, i8 %y, i32 2
+  ret <4 x i8> %v2
+}
+
+; Negative test - don't create arbitrary shuffle masks.
+
+define <4 x i8> @shuf_identity_padding_wrong_index(<2 x i8> %x, i8 %y) {
+; CHECK-LABEL: @shuf_identity_padding_wrong_index(
+; CHECK-NEXT:    [[V0:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[X1:%.*]] = extractelement <2 x i8> [[X]], i32 1
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <4 x i8> [[V0]], i8 [[X1]], i32 2
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i32 3
+; CHECK-NEXT:    ret <4 x i8> [[V2]]
+;
+  %v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %x1 = extractelement <2 x i8> %x, i32 1
+  %v1 = insertelement <4 x i8> %v0, i8 %x1, i32 2
+  %v2 = insertelement <4 x i8> %v1, i8 %y, i32 3
+  ret <4 x i8> %v2
+}
+
+define <4 x float> @insert_undemanded_element_op0(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: @insert_undemanded_element_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.200000e+01, i32 3
+; CHECK-NEXT:    call void @use(<4 x float> [[INS]])
+; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x float> [[X]], <4 x float> [[Y:%.*]], <4 x i32> <i32 0, i32 7, i32 1, i32 4>
+; CHECK-NEXT:    ret <4 x float> [[S]]
+;
+  %ins = insertelement <4 x float> %x, float 42.0, i32 3
+  call void @use(<4 x float> %ins)
+  %s = shufflevector <4 x float> %ins, <4 x float> %y, <4 x i32> <i32 0, i32 7, i32 1, i32 4>
+  ret <4 x float> %s
+}
+
+define <4 x float> @insert_undemanded_element_op1(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: @insert_undemanded_element_op1(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.200000e+01, i32 3
+; CHECK-NEXT:    call void @use(<4 x float> [[INS]])
+; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x float> [[Y:%.*]], <4 x float> [[X]], <4 x i32> <i32 3, i32 2, i32 1, i32 4>
+; CHECK-NEXT:    ret <4 x float> [[S]]
+;
+  %ins = insertelement <4 x float> %x, float 42.0, i32 3
+  call void @use(<4 x float> %ins)
+  %s = shufflevector <4 x float> %y, <4 x float> %ins, <4 x i32> <i32 3, i32 2, i32 1, i32 4>
+  ret <4 x float> %s
+}
+
+; Negative test - shuffle chooses the inserted constant.
+
+define <4 x float> @insert_demanded_element_op0(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: @insert_demanded_element_op0(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.200000e+01, i32 3
+; CHECK-NEXT:    call void @use(<4 x float> [[INS]])
+; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x float> [[INS]], <4 x float> [[Y:%.*]], <4 x i32> <i32 3, i32 2, i32 1, i32 4>
+; CHECK-NEXT:    ret <4 x float> [[S]]
+;
+  %ins = insertelement <4 x float> %x, float 42.0, i32 3
+  call void @use(<4 x float> %ins)
+  %s = shufflevector <4 x float> %ins, <4 x float> %y, <4 x i32> <i32 3, i32 2, i32 1, i32 4>
+  ret <4 x float> %s
+}
+
+; Negative test - shuffle chooses the inserted constant.
+
+define <4 x float> @insert_demanded_element_op1(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: @insert_demanded_element_op1(
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <4 x float> [[X:%.*]], float 4.300000e+01, i32 3
+; CHECK-NEXT:    call void @use(<4 x float> [[INS]])
+; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x float> [[Y:%.*]], <4 x float> [[INS]], <4 x i32> <i32 0, i32 7, i32 1, i32 4>
+; CHECK-NEXT:    ret <4 x float> [[S]]
+;
+  %ins = insertelement <4 x float> %x, float 43.0, i32 3
+  call void @use(<4 x float> %ins)
+  %s = shufflevector <4 x float> %y, <4 x float> %ins, <4 x i32> <i32 0, i32 7, i32 1, i32 4>
+  ret <4 x float> %s
+}
+
+define <4 x float> @splat_constant(<4 x float> %x) {
+; CHECK-LABEL: @splat_constant(
+; CHECK-NEXT:    [[INS3:%.*]] = insertelement <4 x float> [[X:%.*]], float 3.000000e+00, i32 3
+; CHECK-NEXT:    [[R:%.*]] = fadd <4 x float> [[INS3]], <float 3.000000e+00, float 3.000000e+00, float 3.000000e+00, float 3.000000e+00>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %ins3 = insertelement <4 x float> %x, float 3.0, i32 3
+  %splat3 = shufflevector <4 x float> %ins3, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  %r = fadd <4 x float> %ins3, %splat3
+  ret <4 x float> %r
+}
diff --git a/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll b/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
index 53c82702c9eb6..8671915a32e62 100644
--- a/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
+++ b/llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll
@@ -87,7 +87,7 @@ define <8 x float> @widen_extract4(<8 x float> %ins, <2 x float> %ext) {
 define <8 x i16> @pr26015(<4 x i16> %t0) {
 ; CHECK-LABEL: @pr26015(
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i16> [[T0:%.*]], <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
-; CHECK-NEXT:    [[T5:%.*]] = shufflevector <8 x i16> <i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 undef>, <8 x i16> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 10, i32 4, i32 5, i32 6, i32 11>
+; CHECK-NEXT:    [[T5:%.*]] = shufflevector <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 0, i16 0, i16 0, i16 poison>, <8 x i16> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 10, i32 4, i32 5, i32 6, i32 11>
 ; CHECK-NEXT:    ret <8 x i16> [[T5]]
 ;
   %t1 = extractelement <4 x i16> %t0, i32 2
@@ -107,12 +107,12 @@ define <8 x i16> @pr25999(<4 x i16> %t0, i1 %b) {
 ; CHECK-NEXT:    br i1 [[B:%.*]], label [[IF:%.*]], label [[END:%.*]]
 ; CHECK:       if:
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i16> [[T0]], <4 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
-; CHECK-NEXT:    [[T3:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 undef, i16 0, i16 0, i16 0, i16 undef>, i16 [[T1]], i32 3
+; CHECK-NEXT:    [[T3:%.*]] = insertelement <8 x i16> <i16 0, i16 0, i16 0, i16 poison, i16 0, i16 0, i16 0, i16 poison>, i16 [[T1]], i32 3
 ; CHECK-NEXT:    [[T5:%.*]] = shufflevector <8 x i16> [[T3]], <8 x i16> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 11>
 ; CHECK-NEXT:    ret <8 x i16> [[T5]]
 ; CHECK:       end:
 ; CHECK-NEXT:    [[A1:%.*]] = add i16 [[T1]], 4
-; CHECK-NEXT:    [[T6:%.*]] = insertelement <8 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 [[A1]], i32 0
+; CHECK-NEXT:    [[T6:%.*]] = insertelement <8 x i16> <i16 poison, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 [[A1]], i32 0
 ; CHECK-NEXT:    ret <8 x i16> [[T6]]
 ;
 
@@ -206,7 +206,7 @@ define double @pr26354(<2 x double>* %tmp, i1 %B) {
 ; CHECK-NEXT:    br i1 [[B:%.*]], label [[IF:%.*]], label [[END:%.*]]
 ; CHECK:       if:
 ; CHECK-NEXT:    [[E2:%.*]] = extractelement <2 x double> [[LD]], i32 1
-; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double undef>, double [[E2]], i32 3
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x double> <double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double poison>, double [[E2]], i32 3
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
 ; CHECK-NEXT:    [[PH:%.*]] = phi <4 x double> [ undef, [[ENTRY:%.*]] ], [ [[I1]], [[IF]] ]
@@ -244,7 +244,7 @@ define <4 x float> @PR30923(<2 x float> %x) {
 ; CHECK-NEXT:    br label [[BB2:%.*]]
 ; CHECK:       bb2:
 ; CHECK-NEXT:    [[EXT2:%.*]] = extractelement <2 x float> [[X]], i32 0
-; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float undef, float undef>, float [[EXT2]], i32 2
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float poison, float poison>, float [[EXT2]], i32 2
 ; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float [[EXT1]], i32 3
 ; CHECK-NEXT:    ret <4 x float> [[INS2]]
 ;
@@ -267,7 +267,7 @@ define <4 x i32> @extractelt_insertion(<2 x i32> %x, i32 %y) {
 ; CHECK-LABEL: @extractelt_insertion(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
-; CHECK-NEXT:    [[B:%.*]] = shufflevector <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, <4 x i32> [[TMP0]], <4 x i32> <i32 0, i32 1, i32 2, i32 5>
+; CHECK-NEXT:    [[B:%.*]] = shufflevector <4 x i32> <i32 0, i32 0, i32 0, i32 poison>, <4 x i32> [[TMP0]], <4 x i32> <i32 0, i32 1, i32 2, i32 5>
 ; CHECK-NEXT:    [[C:%.*]] = add i32 [[Y:%.*]], 3
 ; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 [[C]]
 ; CHECK-NEXT:    [[E:%.*]] = icmp eq i32 [[TMP1]], 0
@@ -416,7 +416,7 @@ define <4 x float> @insert_not_undef_shuffle_translate_commute_uses(float %x, <4
 
 define <5 x float> @insert_not_undef_shuffle_translate_commute_lengthen(float %x, <4 x float> %y, <4 x float> %q) {
 ; CHECK-LABEL: @insert_not_undef_shuffle_translate_commute_lengthen(
-; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 2
+; CHECK-NEXT:    [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 2
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[Y:%.*]], <4 x float> [[XV]], <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef>
 ; CHECK-NEXT:    ret <5 x float> [[R]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-scalar.ll b/llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-scalar.ll
index b7cf96d1f22af..e1bda5903f6f5 100644
--- a/llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-scalar.ll
+++ b/llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-scalar.ll
@@ -52,9 +52,8 @@ define i4 @in_constant_varx_6_invmask(i4 %x, i4 %mask) {
 
 define i4 @in_constant_mone_vary_invmask(i4 %y, i4 %mask) {
 ; CHECK-LABEL: @in_constant_mone_vary_invmask(
-; CHECK-NEXT:    [[N1_DEMORGAN:%.*]] = or i4 [[Y:%.*]], [[MASK:%.*]]
-; CHECK-NEXT:    [[N1:%.*]] = xor i4 [[N1_DEMORGAN]], -1
-; CHECK-NEXT:    [[R:%.*]] = xor i4 [[N1]], [[Y]]
+; CHECK-NEXT:    [[MASK_NOT:%.*]] = xor i4 [[MASK:%.*]], -1
+; CHECK-NEXT:    [[R:%.*]] = or i4 [[MASK_NOT]], [[Y:%.*]]
 ; CHECK-NEXT:    ret i4 [[R]]
 ;
   %notmask = xor i4 %mask, -1
diff --git a/llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-vector.ll b/llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-vector.ll
index a2e427b0c4640..44e12fb64b957 100644
--- a/llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-vector.ll
+++ b/llvm/test/Transforms/InstCombine/invert-variable-mask-in-masked-merge-vector.ll
@@ -94,9 +94,8 @@ define <3 x i4> @in_constant_varx_6_invmask_undef(<3 x i4> %x, <3 x i4> %mask) {
 
 define <2 x i4> @in_constant_mone_vary_invmask(<2 x i4> %y, <2 x i4> %mask) {
 ; CHECK-LABEL: @in_constant_mone_vary_invmask(
-; CHECK-NEXT:    [[N1_DEMORGAN:%.*]] = or <2 x i4> [[Y:%.*]], [[MASK:%.*]]
-; CHECK-NEXT:    [[N1:%.*]] = xor <2 x i4> [[N1_DEMORGAN]], <i4 -1, i4 -1>
-; CHECK-NEXT:    [[R:%.*]] = xor <2 x i4> [[N1]], [[Y]]
+; CHECK-NEXT:    [[MASK_NOT:%.*]] = xor <2 x i4> [[MASK:%.*]], <i4 -1, i4 -1>
+; CHECK-NEXT:    [[R:%.*]] = or <2 x i4> [[MASK_NOT]], [[Y:%.*]]
 ; CHECK-NEXT:    ret <2 x i4> [[R]]
 ;
   %notmask = xor <2 x i4> %mask, <i4 -1, i4 -1>
diff --git a/llvm/test/Transforms/InstCombine/known-non-zero.ll b/llvm/test/Transforms/InstCombine/known-non-zero.ll
index 5467db556632d..3ad1ebe55b2ce 100644
--- a/llvm/test/Transforms/InstCombine/known-non-zero.ll
+++ b/llvm/test/Transforms/InstCombine/known-non-zero.ll
@@ -13,7 +13,7 @@ define i32 @test0(i64 %x) {
 ; CHECK-NEXT:    [[C:%.*]] = icmp eq i64 [[X:%.*]], 0
 ; CHECK-NEXT:    br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
 ; CHECK:       non_zero:
-; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.cttz.i64(i64 [[X]], i1 true), !range !0
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.cttz.i64(i64 [[X]], i1 true), [[RNG0:!range !.*]]
 ; CHECK-NEXT:    [[CTZ32:%.*]] = trunc i64 [[CTZ]] to i32
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
@@ -40,7 +40,7 @@ define i32 @test1(i64 %x) {
 ; CHECK-NEXT:    [[C:%.*]] = icmp eq i64 [[X:%.*]], 0
 ; CHECK-NEXT:    br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
 ; CHECK:       non_zero:
-; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range !0
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
 ; CHECK-NEXT:    [[CTZ32:%.*]] = trunc i64 [[CTZ]] to i32
 ; CHECK-NEXT:    br label [[EXIT]]
 ; CHECK:       exit:
@@ -93,8 +93,8 @@ exit:
 }
 
 ; Test that exposed a bug in the PHI handling after D60846. No folding should happen here!
-define void @D60846_misompile(i1* %p) {
-; CHECK-LABEL: @D60846_misompile(
+define void @D60846_miscompile(i1* %p) {
+; CHECK-LABEL: @D60846_miscompile(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
@@ -133,3 +133,187 @@ common:                                           ; preds = %non_zero, %loop
 exit:                                             ; preds = %common
   ret void
 }
+
+define i64 @test_sgt_zero(i64 %x) {
+; CHECK-LABEL: @test_sgt_zero(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    [[C:%.*]] = icmp sgt i64 [[X:%.*]], 0
+; CHECK-NEXT:    br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]]
+; CHECK:       non_zero:
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT:    ret i64 [[CTZ]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i64 -1
+;
+start:
+  %c = icmp sgt i64 %x, 0
+  br i1 %c, label %non_zero, label %exit
+
+non_zero:
+  %ctz = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+  ret i64 %ctz
+
+exit:
+  ret i64 -1
+}
+
+define i64 @test_slt_neg_ten(i64 %x) {
+; CHECK-LABEL: @test_slt_neg_ten(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    [[C:%.*]] = icmp slt i64 [[X:%.*]], -10
+; CHECK-NEXT:    br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]]
+; CHECK:       non_zero:
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT:    ret i64 [[CTZ]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i64 -1
+;
+start:
+  %c = icmp slt i64 %x, -10
+  br i1 %c, label %non_zero, label %exit
+
+non_zero:
+  %ctz = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+  ret i64 %ctz
+
+exit:
+  ret i64 -1
+}
+
+define i64 @test_slt_ten(i64 %x) {
+; CHECK-LABEL: @test_slt_ten(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    [[C:%.*]] = icmp slt i64 [[X:%.*]], 10
+; CHECK-NEXT:    br i1 [[C]], label [[MAYBE_ZERO:%.*]], label [[EXIT:%.*]]
+; CHECK:       maybe_zero:
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), [[RNG0]]
+; CHECK-NEXT:    ret i64 [[CTZ]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i64 -1
+;
+start:
+  %c = icmp slt i64 %x, 10
+  br i1 %c, label %maybe_zero, label %exit
+
+maybe_zero:
+  %ctz = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+  ret i64 %ctz
+
+exit:
+  ret i64 -1
+}
+
+define i64 @test_ugt_unknown(i64 %x, i64 %y) {
+; CHECK-LABEL: @test_ugt_unknown(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    [[C:%.*]] = icmp ugt i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]]
+; CHECK:       non_zero:
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT:    ret i64 [[CTZ]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i64 -1
+;
+start:
+  %c = icmp ugt i64 %x, %y
+  br i1 %c, label %non_zero, label %exit
+
+non_zero:
+  %ctz = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+  ret i64 %ctz
+
+exit:
+  ret i64 -1
+}
+
+define i64 @test_sle_zero(i64 %x) {
+; CHECK-LABEL: @test_sle_zero(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    [[C:%.*]] = icmp slt i64 [[X:%.*]], 1
+; CHECK-NEXT:    br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
+; CHECK:       non_zero:
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT:    ret i64 [[CTZ]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i64 -1
+;
+start:
+  %c = icmp sle i64 %x, 0
+  br i1 %c, label %exit, label %non_zero
+
+non_zero:
+  %ctz = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+  ret i64 %ctz
+
+exit:
+  ret i64 -1
+}
+
+define i64 @test_sge_neg_ten(i64 %x) {
+; CHECK-LABEL: @test_sge_neg_ten(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    [[C:%.*]] = icmp sgt i64 [[X:%.*]], -11
+; CHECK-NEXT:    br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]]
+; CHECK:       non_zero:
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT:    ret i64 [[CTZ]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i64 -1
+;
+start:
+  %c = icmp sge i64 %x, -10
+  br i1 %c, label %exit, label %non_zero
+
+non_zero:
+  %ctz = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+  ret i64 %ctz
+
+exit:
+  ret i64 -1
+}
+
+define i64 @test_sge_ten(i64 %x) {
+; CHECK-LABEL: @test_sge_ten(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    [[C:%.*]] = icmp sgt i64 [[X:%.*]], 9
+; CHECK-NEXT:    br i1 [[C]], label [[EXIT:%.*]], label [[MAYBE_ZERO:%.*]]
+; CHECK:       maybe_zero:
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), [[RNG0]]
+; CHECK-NEXT:    ret i64 [[CTZ]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i64 -1
+;
+start:
+  %c = icmp sge i64 %x, 10
+  br i1 %c, label %exit, label %maybe_zero
+
+maybe_zero:
+  %ctz = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+  ret i64 %ctz
+
+exit:
+  ret i64 -1
+}
+
+define i64 @test_ule_unknown(i64 %x, i64 %y) {
+; CHECK-LABEL: @test_ule_unknown(
+; CHECK-NEXT:  start:
+; CHECK-NEXT:    [[C_NOT:%.*]] = icmp ugt i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    br i1 [[C_NOT]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]]
+; CHECK:       non_zero:
+; CHECK-NEXT:    [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), [[RNG0]]
+; CHECK-NEXT:    ret i64 [[CTZ]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret i64 -1
+;
+start:
+  %c = icmp ule i64 %x, %y
+  br i1 %c, label %exit, label %non_zero
+
+non_zero:
+  %ctz = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
+  ret i64 %ctz
+
+exit:
+  ret i64 -1
+}
diff --git a/llvm/test/Transforms/InstCombine/limit-max-iterations.ll b/llvm/test/Transforms/InstCombine/limit-max-iterations.ll
deleted file mode 100644
index a29166c042564..0000000000000
--- a/llvm/test/Transforms/InstCombine/limit-max-iterations.ll
+++ /dev/null
@@ -1,39 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -instcombine --instcombine-max-iterations=0 -S | FileCheck %s --check-prefix=ZERO
-; RUN: opt < %s -instcombine --instcombine-max-iterations=1 -S | FileCheck %s --check-prefix=ONE
-; RUN: opt < %s -instcombine -S | FileCheck %s --check-prefix=FIXPOINT
-; RUN: not --crash opt < %s -instcombine -S --instcombine-infinite-loop-threshold=2 2>&1 | FileCheck %s --check-prefix=LOOP
-
-; Based on builtin-dynamic-object-size.ll. This requires multiple iterations of
-; InstCombine to reach a fixpoint.
-
-define i64 @weird_identity_but_ok(i64 %sz) {
-; ZERO-LABEL: @weird_identity_but_ok(
-; ZERO-NEXT:  entry:
-; ZERO-NEXT:    [[CALL:%.*]] = tail call i8* @malloc(i64 [[SZ:%.*]])
-; ZERO-NEXT:    [[CALC_SIZE:%.*]] = tail call i64 @llvm.objectsize.i64.p0i8(i8* [[CALL]], i1 false, i1 true, i1 true)
-; ZERO-NEXT:    tail call void @free(i8* [[CALL]])
-; ZERO-NEXT:    ret i64 [[CALC_SIZE]]
-;
-; ONE-LABEL: @weird_identity_but_ok(
-; ONE-NEXT:  entry:
-; ONE-NEXT:    [[TMP0:%.*]] = sub i64 [[SZ:%.*]], 0
-; ONE-NEXT:    [[TMP1:%.*]] = icmp ult i64 [[SZ]], 0
-; ONE-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i64 0, i64 [[TMP0]]
-; ONE-NEXT:    ret i64 [[TMP2]]
-;
-; FIXPOINT-LABEL: @weird_identity_but_ok(
-; FIXPOINT-NEXT:  entry:
-; FIXPOINT-NEXT:    ret i64 [[SZ:%.*]]
-;
-; LOOP: LLVM ERROR: Instruction Combining seems stuck in an infinite loop after 2 iterations.
-entry:
-  %call = tail call i8* @malloc(i64 %sz)
-  %calc_size = tail call i64 @llvm.objectsize.i64.p0i8(i8* %call, i1 false, i1 true, i1 true)
-  tail call void @free(i8* %call)
-  ret i64 %calc_size
-}
-
-declare i64 @llvm.objectsize.i64.p0i8(i8*, i1, i1, i1)
-declare i8* @malloc(i64)
-declare void @free(i8*)
diff --git a/llvm/test/Transforms/InstCombine/load.ll b/llvm/test/Transforms/InstCombine/load.ll
index 79adbe1173332..a6a2155be0b56 100644
--- a/llvm/test/Transforms/InstCombine/load.ll
+++ b/llvm/test/Transforms/InstCombine/load.ll
@@ -57,13 +57,23 @@ define i32 @test5(i1 %C) {
   ret i32 %Z
 }
 
-define i32 @test7(i32 %X) {
-; CHECK-LABEL: @test7(
+define i32 @load_gep_null_inbounds(i64 %X) {
+; CHECK-LABEL: @load_gep_null_inbounds(
 ; CHECK-NEXT:    store i32 undef, i32* null, align 536870912
 ; CHECK-NEXT:    ret i32 undef
 ;
-  %V = getelementptr i32, i32* null, i32 %X		; <i32*> [#uses=1]
-  %R = load i32, i32* %V		; <i32> [#uses=1]
+  %V = getelementptr inbounds i32, i32* null, i64 %X
+  %R = load i32, i32* %V
+  ret i32 %R
+}
+
+define i32 @load_gep_null_not_inbounds(i64 %X) {
+; CHECK-LABEL: @load_gep_null_not_inbounds(
+; CHECK-NEXT:    store i32 undef, i32* null, align 536870912
+; CHECK-NEXT:    ret i32 undef
+;
+  %V = getelementptr i32, i32* null, i64 %X
+  %R = load i32, i32* %V
   ret i32 %R
 }
 
diff --git a/llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll b/llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
new file mode 100644
index 0000000000000..4243e823e257f
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll
@@ -0,0 +1,271 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+declare <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptrs, i32, <2 x i1> %mask, <2 x double> %src0)
+declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %ptrs, i32, <2 x i1> %mask)
+declare <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32, <2 x i1> %mask, <2 x double> %passthru)
+declare <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> %ptrs, i32, <4 x i1> %mask, <4 x double> %passthru)
+declare void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> %val, <2 x double*> %ptrs, i32, <2 x i1> %mask)
+
+define <2 x double> @load_zeromask(<2 x double>* %ptr, <2 x double> %passthru)  {
+; CHECK-LABEL: @load_zeromask(
+; CHECK-NEXT:    ret <2 x double> [[PASSTHRU:%.*]]
+;
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 1, <2 x i1> zeroinitializer, <2 x double> %passthru)
+  ret <2 x double> %res
+}
+
+define <2 x double> @load_onemask(<2 x double>* %ptr, <2 x double> %passthru)  {
+; CHECK-LABEL: @load_onemask(
+; CHECK-NEXT:    [[UNMASKEDLOAD:%.*]] = load <2 x double>, <2 x double>* [[PTR:%.*]], align 2
+; CHECK-NEXT:    ret <2 x double> [[UNMASKEDLOAD]]
+;
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 2, <2 x i1> <i1 1, i1 1>, <2 x double> %passthru)
+  ret <2 x double> %res
+}
+
+define <2 x double> @load_undefmask(<2 x double>* %ptr, <2 x double> %passthru)  {
+; CHECK-LABEL: @load_undefmask(
+; CHECK-NEXT:    [[UNMASKEDLOAD:%.*]] = load <2 x double>, <2 x double>* [[PTR:%.*]], align 2
+; CHECK-NEXT:    ret <2 x double> [[UNMASKEDLOAD]]
+;
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 2, <2 x i1> <i1 1, i1 undef>, <2 x double> %passthru)
+  ret <2 x double> %res
+}
+
+@G = external global i8
+
+define <2 x double> @load_cemask(<2 x double>* %ptr, <2 x double> %passthru)  {
+; CHECK-LABEL: @load_cemask(
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* [[PTR:%.*]], i32 2, <2 x i1> <i1 true, i1 ptrtoint (i8* @G to i1)>, <2 x double> [[PASSTHRU:%.*]])
+; CHECK-NEXT:    ret <2 x double> [[RES]]
+;
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 2, <2 x i1> <i1 1, i1 ptrtoint (i8* @G to i1)>, <2 x double> %passthru)
+  ret <2 x double> %res
+}
+
+define <2 x double> @load_lane0(<2 x double>* %ptr, double %pt)  {
+; CHECK-LABEL: @load_lane0(
+; CHECK-NEXT:    [[PTV2:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 1
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* [[PTR:%.*]], i32 2, <2 x i1> <i1 true, i1 false>, <2 x double> [[PTV2]])
+; CHECK-NEXT:    ret <2 x double> [[RES]]
+;
+  %ptv1 = insertelement <2 x double> poison, double %pt, i64 0
+  %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 2, <2 x i1> <i1 true, i1 false>, <2 x double> %ptv2)
+  ret <2 x double> %res
+}
+
+define double @load_all(double* %base, double %pt)  {
+; CHECK-LABEL: @load_all(
+; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[BASE:%.*]], <4 x i64> <i64 0, i64 poison, i64 2, i64 3>
+; CHECK-NEXT:    [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> [[PTRS]], i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> undef)
+; CHECK-NEXT:    [[ELT:%.*]] = extractelement <4 x double> [[RES]], i64 2
+; CHECK-NEXT:    ret double [[ELT]]
+;
+  %ptrs = getelementptr double, double* %base, <4 x i64> <i64 0, i64 1, i64 2, i64 3>
+  %res = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> %ptrs, i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> undef)
+  %elt = extractelement <4 x double> %res, i64 2
+  ret double %elt
+}
+
+define <2 x double> @load_generic(<2 x double>* %ptr, double %pt, <2 x i1> %mask)  {
+; CHECK-LABEL: @load_generic(
+; CHECK-NEXT:    [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
+; CHECK-NEXT:    [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* [[PTR:%.*]], i32 4, <2 x i1> [[MASK:%.*]], <2 x double> [[PTV2]])
+; CHECK-NEXT:    ret <2 x double> [[RES]]
+;
+  %ptv1 = insertelement <2 x double> poison, double %pt, i64 0
+  %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2)
+  ret <2 x double> %res
+}
+
+define <2 x double> @load_speculative(<2 x double>* dereferenceable(16) align 4 %ptr, double %pt, <2 x i1> %mask)  {
+; CHECK-LABEL: @load_speculative(
+; CHECK-NEXT:    [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
+; CHECK-NEXT:    [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[UNMASKEDLOAD:%.*]] = load <2 x double>, <2 x double>* [[PTR:%.*]], align 4
+; CHECK-NEXT:    [[TMP1:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %ptv1 = insertelement <2 x double> poison, double %pt, i64 0
+  %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2)
+  ret <2 x double> %res
+}
+
+define <2 x double> @load_speculative_less_aligned(<2 x double>* dereferenceable(16) %ptr, double %pt, <2 x i1> %mask)  {
+; CHECK-LABEL: @load_speculative_less_aligned(
+; CHECK-NEXT:    [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
+; CHECK-NEXT:    [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[UNMASKEDLOAD:%.*]] = load <2 x double>, <2 x double>* [[PTR:%.*]], align 4
+; CHECK-NEXT:    [[TMP1:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
+; CHECK-NEXT:    ret <2 x double> [[TMP1]]
+;
+  %ptv1 = insertelement <2 x double> poison, double %pt, i64 0
+  %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2)
+  ret <2 x double> %res
+}
+
+; Can't speculate since only half of required size is known deref
+
+define <2 x double> @load_spec_neg_size(<2 x double>* dereferenceable(8) %ptr, double %pt, <2 x i1> %mask)  {
+; CHECK-LABEL: @load_spec_neg_size(
+; CHECK-NEXT:    [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
+; CHECK-NEXT:    [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* nonnull [[PTR:%.*]], i32 4, <2 x i1> [[MASK:%.*]], <2 x double> [[PTV2]])
+; CHECK-NEXT:    ret <2 x double> [[RES]]
+;
+  %ptv1 = insertelement <2 x double> poison, double %pt, i64 0
+  %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2)
+  ret <2 x double> %res
+}
+
+; Can only speculate one lane (but it's the only one active)
+define <2 x double> @load_spec_lan0(<2 x double>* dereferenceable(8) %ptr, double %pt, <2 x i1> %mask)  {
+; CHECK-LABEL: @load_spec_lan0(
+; CHECK-NEXT:    [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
+; CHECK-NEXT:    [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[MASK2:%.*]] = insertelement <2 x i1> [[MASK:%.*]], i1 false, i64 1
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* nonnull [[PTR:%.*]], i32 4, <2 x i1> [[MASK2]], <2 x double> [[PTV2]])
+; CHECK-NEXT:    ret <2 x double> [[RES]]
+;
+  %ptv1 = insertelement <2 x double> poison, double %pt, i64 0
+  %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
+  %mask2 = insertelement <2 x i1> %mask, i1 false, i64 1
+  %res = call <2 x double> @llvm.masked.load.v2f64.p0v2f64(<2 x double>* %ptr, i32 4, <2 x i1> %mask2, <2 x double> %ptv2)
+  ret <2 x double> %res
+}
+
+define void @store_zeromask(<2 x double>* %ptr, <2 x double> %val)  {
+; CHECK-LABEL: @store_zeromask(
+; CHECK-NEXT:    ret void
+;
+  call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %ptr, i32 4, <2 x i1> zeroinitializer)
+  ret void
+}
+
+define void @store_onemask(<2 x double>* %ptr, <2 x double> %val)  {
+; CHECK-LABEL: @store_onemask(
+; CHECK-NEXT:    store <2 x double> [[VAL:%.*]], <2 x double>* [[PTR:%.*]], align 4
+; CHECK-NEXT:    ret void
+;
+  call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %val, <2 x double>* %ptr, i32 4, <2 x i1> <i1 1, i1 1>)
+  ret void
+}
+
+define void @store_demandedelts(<2 x double>* %ptr, double %val)  {
+; CHECK-LABEL: @store_demandedelts(
+; CHECK-NEXT:    [[VALVEC1:%.*]] = insertelement <2 x double> poison, double [[VAL:%.*]], i32 0
+; CHECK-NEXT:    call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> [[VALVEC1]], <2 x double>* [[PTR:%.*]], i32 4, <2 x i1> <i1 true, i1 false>)
+; CHECK-NEXT:    ret void
+;
+  %valvec1 = insertelement <2 x double> poison, double %val, i32 0
+  %valvec2 = insertelement <2 x double> %valvec1, double %val, i32 1
+  call void @llvm.masked.store.v2f64.p0v2f64(<2 x double> %valvec2, <2 x double>* %ptr, i32 4, <2 x i1> <i1 true, i1 false>)
+  ret void
+}
+
+define <2 x double> @gather_generic(<2 x double*> %ptrs, <2 x i1> %mask, <2 x double> %passthru)  {
+; CHECK-LABEL: @gather_generic(
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> [[PTRS:%.*]], i32 4, <2 x i1> [[MASK:%.*]], <2 x double> [[PASSTHRU:%.*]])
+; CHECK-NEXT:    ret <2 x double> [[RES]]
+;
+  %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask, <2 x double> %passthru)
+  ret <2 x double> %res
+}
+
+
+define <2 x double> @gather_zeromask(<2 x double*> %ptrs, <2 x double> %passthru)  {
+; CHECK-LABEL: @gather_zeromask(
+; CHECK-NEXT:    ret <2 x double> [[PASSTHRU:%.*]]
+;
+  %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> zeroinitializer, <2 x double> %passthru)
+  ret <2 x double> %res
+}
+
+
+define <2 x double> @gather_onemask(<2 x double*> %ptrs, <2 x double> %passthru)  {
+; CHECK-LABEL: @gather_onemask(
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> [[PTRS:%.*]], i32 4, <2 x i1> <i1 true, i1 true>, <2 x double> poison)
+; CHECK-NEXT:    ret <2 x double> [[RES]]
+;
+  %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> <i1 true, i1 true>, <2 x double> %passthru)
+  ret <2 x double> %res
+}
+
+define <4 x double> @gather_lane2(double* %base, double %pt)  {
+; CHECK-LABEL: @gather_lane2(
+; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[BASE:%.*]], <4 x i64> <i64 poison, i64 poison, i64 2, i64 poison>
+; CHECK-NEXT:    [[PT_V1:%.*]] = insertelement <4 x double> poison, double [[PT:%.*]], i64 0
+; CHECK-NEXT:    [[PT_V2:%.*]] = shufflevector <4 x double> [[PT_V1]], <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 undef, i32 0>
+; CHECK-NEXT:    [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> [[PTRS]], i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> [[PT_V2]])
+; CHECK-NEXT:    ret <4 x double> [[RES]]
+;
+  %ptrs = getelementptr double, double *%base, <4 x i64> <i64 0, i64 1, i64 2, i64 3>
+  %pt_v1 = insertelement <4 x double> poison, double %pt, i64 0
+  %pt_v2 = shufflevector <4 x double> %pt_v1, <4 x double> undef, <4 x i32> zeroinitializer
+  %res = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> %ptrs, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> %pt_v2)
+  ret <4 x double> %res
+}
+
+define <2 x double> @gather_lane0_maybe(double* %base, double %pt, <2 x i1> %mask)  {
+; CHECK-LABEL: @gather_lane0_maybe(
+; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[BASE:%.*]], <2 x i64> <i64 0, i64 1>
+; CHECK-NEXT:    [[PT_V1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
+; CHECK-NEXT:    [[PT_V2:%.*]] = shufflevector <2 x double> [[PT_V1]], <2 x double> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[MASK2:%.*]] = insertelement <2 x i1> [[MASK:%.*]], i1 false, i64 1
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> [[PTRS]], i32 4, <2 x i1> [[MASK2]], <2 x double> [[PT_V2]])
+; CHECK-NEXT:    ret <2 x double> [[RES]]
+;
+  %ptrs = getelementptr double, double *%base, <2 x i64> <i64 0, i64 1>
+  %pt_v1 = insertelement <2 x double> poison, double %pt, i64 0
+  %pt_v2 = insertelement <2 x double> %pt_v1, double %pt, i64 1
+  %mask2 = insertelement <2 x i1> %mask, i1 false, i64 1
+  %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask2, <2 x double> %pt_v2)
+  ret <2 x double> %res
+}
+
+define <2 x double> @gather_lane0_maybe_spec(double* %base, double %pt, <2 x i1> %mask)  {
+; CHECK-LABEL: @gather_lane0_maybe_spec(
+; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[BASE:%.*]], <2 x i64> <i64 0, i64 1>
+; CHECK-NEXT:    [[PT_V1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
+; CHECK-NEXT:    [[PT_V2:%.*]] = shufflevector <2 x double> [[PT_V1]], <2 x double> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[MASK2:%.*]] = insertelement <2 x i1> [[MASK:%.*]], i1 false, i64 1
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> [[PTRS]], i32 4, <2 x i1> [[MASK2]], <2 x double> [[PT_V2]])
+; CHECK-NEXT:    ret <2 x double> [[RES]]
+;
+  %ptrs = getelementptr double, double *%base, <2 x i64> <i64 0, i64 1>
+  %pt_v1 = insertelement <2 x double> poison, double %pt, i64 0
+  %pt_v2 = insertelement <2 x double> %pt_v1, double %pt, i64 1
+  %mask2 = insertelement <2 x i1> %mask, i1 false, i64 1
+  %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> %mask2, <2 x double> %pt_v2)
+  ret <2 x double> %res
+}
+
+
+define void @scatter_zeromask(<2 x double*> %ptrs, <2 x double> %val)  {
+; CHECK-LABEL: @scatter_zeromask(
+; CHECK-NEXT:    ret void
+;
+  call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> %val, <2 x double*> %ptrs, i32 8, <2 x i1> zeroinitializer)
+  ret void
+}
+
+define void @scatter_demandedelts(double* %ptr, double %val)  {
+; CHECK-LABEL: @scatter_demandedelts(
+; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[PTR:%.*]], <2 x i64> <i64 0, i64 poison>
+; CHECK-NEXT:    [[VALVEC1:%.*]] = insertelement <2 x double> poison, double [[VAL:%.*]], i32 0
+; CHECK-NEXT:    call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> [[VALVEC1]], <2 x double*> [[PTRS]], i32 8, <2 x i1> <i1 true, i1 false>)
+; CHECK-NEXT:    ret void
+;
+  %ptrs = getelementptr double, double* %ptr, <2 x i64> <i64 0, i64 1>
+  %valvec1 = insertelement <2 x double> poison, double %val, i32 0
+  %valvec2 = insertelement <2 x double> %valvec1, double %val, i32 1
+  call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> %valvec2, <2 x double*> %ptrs, i32 8, <2 x i1> <i1 true, i1 false>)
+  ret void
+}
diff --git a/llvm/test/Transforms/InstCombine/masked_intrinsics.ll b/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
index 684e008cc6bcd..2b22ac74228dd 100644
--- a/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
+++ b/llvm/test/Transforms/InstCombine/masked_intrinsics.ll
@@ -58,7 +58,7 @@ define <2 x double> @load_lane0(<2 x double>* %ptr, double %pt)  {
 
 define double @load_all(double* %base, double %pt)  {
 ; CHECK-LABEL: @load_all(
-; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[BASE:%.*]], <4 x i64> <i64 0, i64 undef, i64 2, i64 3>
+; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[BASE:%.*]], <4 x i64> <i64 0, i64 poison, i64 2, i64 3>
 ; CHECK-NEXT:    [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> [[PTRS]], i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> undef)
 ; CHECK-NEXT:    [[ELT:%.*]] = extractelement <4 x double> [[RES]], i64 2
 ; CHECK-NEXT:    ret double [[ELT]]
@@ -191,7 +191,7 @@ define <2 x double> @gather_zeromask(<2 x double*> %ptrs, <2 x double> %passthru
 
 define <2 x double> @gather_onemask(<2 x double*> %ptrs, <2 x double> %passthru)  {
 ; CHECK-LABEL: @gather_onemask(
-; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> [[PTRS:%.*]], i32 4, <2 x i1> <i1 true, i1 true>, <2 x double> undef)
+; CHECK-NEXT:    [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> [[PTRS:%.*]], i32 4, <2 x i1> <i1 true, i1 true>, <2 x double> poison)
 ; CHECK-NEXT:    ret <2 x double> [[RES]]
 ;
   %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0f64(<2 x double*> %ptrs, i32 4, <2 x i1> <i1 true, i1 true>, <2 x double> %passthru)
@@ -200,7 +200,7 @@ define <2 x double> @gather_onemask(<2 x double*> %ptrs, <2 x double> %passthru)
 
 define <4 x double> @gather_lane2(double* %base, double %pt)  {
 ; CHECK-LABEL: @gather_lane2(
-; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[BASE:%.*]], <4 x i64> <i64 undef, i64 undef, i64 2, i64 undef>
+; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[BASE:%.*]], <4 x i64> <i64 poison, i64 poison, i64 2, i64 poison>
 ; CHECK-NEXT:    [[PT_V1:%.*]] = insertelement <4 x double> undef, double [[PT:%.*]], i64 0
 ; CHECK-NEXT:    [[PT_V2:%.*]] = shufflevector <4 x double> [[PT_V1]], <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 undef, i32 0>
 ; CHECK-NEXT:    [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0f64(<4 x double*> [[PTRS]], i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> [[PT_V2]])
@@ -258,7 +258,7 @@ define void @scatter_zeromask(<2 x double*> %ptrs, <2 x double> %val)  {
 
 define void @scatter_demandedelts(double* %ptr, double %val)  {
 ; CHECK-LABEL: @scatter_demandedelts(
-; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[PTR:%.*]], <2 x i64> <i64 0, i64 undef>
+; CHECK-NEXT:    [[PTRS:%.*]] = getelementptr double, double* [[PTR:%.*]], <2 x i64> <i64 0, i64 poison>
 ; CHECK-NEXT:    [[VALVEC1:%.*]] = insertelement <2 x double> undef, double [[VAL:%.*]], i32 0
 ; CHECK-NEXT:    call void @llvm.masked.scatter.v2f64.v2p0f64(<2 x double> [[VALVEC1]], <2 x double*> [[PTRS]], i32 8, <2 x i1> <i1 true, i1 false>)
 ; CHECK-NEXT:    ret void
diff --git a/llvm/test/Transforms/InstCombine/minmax-fold.ll b/llvm/test/Transforms/InstCombine/minmax-fold.ll
index dcf060c09613e..78126302f9b9f 100644
--- a/llvm/test/Transforms/InstCombine/minmax-fold.ll
+++ b/llvm/test/Transforms/InstCombine/minmax-fold.ll
@@ -1452,7 +1452,7 @@ define i8 @PR14613_smax(i8 %x) {
 define i8 @PR46271(<2 x i8> %x) {
 ; CHECK-LABEL: @PR46271(
 ; CHECK-NEXT:    [[A:%.*]] = icmp sgt <2 x i8> [[X:%.*]], <i8 -1, i8 -1>
-; CHECK-NEXT:    [[B:%.*]] = select <2 x i1> [[A]], <2 x i8> [[X]], <2 x i8> <i8 undef, i8 -1>
+; CHECK-NEXT:    [[B:%.*]] = select <2 x i1> [[A]], <2 x i8> [[X]], <2 x i8> <i8 poison, i8 -1>
 ; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i8> [[B]], i32 1
 ; CHECK-NEXT:    [[R:%.*]] = xor i8 [[TMP1]], -1
 ; CHECK-NEXT:    ret i8 [[R]]
diff --git a/llvm/test/Transforms/InstCombine/or-xor.ll b/llvm/test/Transforms/InstCombine/or-xor.ll
index 56c5fca2e76b7..2ec54c8d53e52 100644
--- a/llvm/test/Transforms/InstCombine/or-xor.ll
+++ b/llvm/test/Transforms/InstCombine/or-xor.ll
@@ -93,9 +93,15 @@ define i32 @test9(i32 %x, i32 %y) {
   ret i32 %z
 }
 
+; (A ^ B) | (~A ^ B) --> -1
+
 define i32 @test10(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test10(
-; CHECK-NEXT:    ret i32 -1
+; CHECK-NEXT:    [[XOR1:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[XOR1]], [[XOR2]]
+; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %xor1 = xor i32 %B, %A
   %not = xor i32 %A, -1
@@ -106,15 +112,63 @@ define i32 @test10(i32 %A, i32 %B) {
 
 define i32 @test10_commuted(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test10_commuted(
+; CHECK-NEXT:    [[XOR1:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[XOR1]], [[XOR2]]
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %xor1 = xor i32 %B, %A
+  %not = xor i32 %A, -1
+  %xor2 = xor i32 %not, %B
+  %or = or i32 %xor2, %xor1
+  ret i32 %or
+}
+
+define i32 @test10_extrause(i32 %A, i32 %B, i32* %dst) {
+; CHECK-LABEL: @test10_extrause(
+; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT:    store i32 [[NOT]], i32* [[DST:%.*]], align 4
+; CHECK-NEXT:    ret i32 -1
+;
+  %xor1 = xor i32 %B, %A
+  %not = xor i32 %A, -1
+  store i32 %not, i32* %dst
+  %xor2 = xor i32 %not, %B
+  %or = or i32 %xor1, %xor2
+  ret i32 %or
+}
+
+define i32 @test10_commuted_extrause(i32 %A, i32 %B, i32* %dst) {
+; CHECK-LABEL: @test10_commuted_extrause(
+; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A:%.*]], -1
+; CHECK-NEXT:    store i32 [[NOT]], i32* [[DST:%.*]], align 4
 ; CHECK-NEXT:    ret i32 -1
 ;
   %xor1 = xor i32 %B, %A
   %not = xor i32 %A, -1
+  store i32 %not, i32* %dst
   %xor2 = xor i32 %not, %B
   %or = or i32 %xor2, %xor1
   ret i32 %or
 }
 
+; (A ^ B) | ~(A ^ B) --> -1
+define i32 @test10_canonical(i32 %A, i32 %B) {
+; CHECK-LABEL: @test10_canonical(
+; CHECK-NEXT:    [[XOR1:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[A]], [[B]]
+; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[XOR2]], -1
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[XOR1]], [[NOT]]
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %xor1 = xor i32 %B, %A
+  %xor2 = xor i32 %A, %B
+  %not = xor i32 %xor2, -1
+  %or = or i32 %xor1, %not
+  ret i32 %or
+}
+
 ; (x | y) & ((~x) ^ y) -> (x & y)
 define i32 @test11(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test11(
@@ -304,9 +358,9 @@ define i8 @or_xor_or(i8 %x) {
 define i8 @test17(i8 %A, i8 %B) {
 ; CHECK-LABEL: @test17(
 ; CHECK-NEXT:    [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[NOT:%.*]] = xor i8 [[A]], 33
-; CHECK-NEXT:    [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
-; CHECK-NEXT:    [[OR:%.*]] = or i8 [[XOR1]], 33
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i8 [[TMP1]], 33
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[XOR1]], [[XOR2]]
 ; CHECK-NEXT:    [[RES:%.*]] = mul i8 [[OR]], [[XOR2]]
 ; CHECK-NEXT:    ret i8 [[RES]]
 ;
@@ -321,9 +375,9 @@ define i8 @test17(i8 %A, i8 %B) {
 define i8 @test18(i8 %A, i8 %B) {
 ; CHECK-LABEL: @test18(
 ; CHECK-NEXT:    [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[NOT:%.*]] = xor i8 [[A]], 33
-; CHECK-NEXT:    [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
-; CHECK-NEXT:    [[OR:%.*]] = or i8 [[XOR1]], 33
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i8 [[TMP1]], 33
+; CHECK-NEXT:    [[OR:%.*]] = or i8 [[XOR2]], [[XOR1]]
 ; CHECK-NEXT:    [[RES:%.*]] = mul i8 [[OR]], [[XOR2]]
 ; CHECK-NEXT:    ret i8 [[RES]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/pr2645-0.ll b/llvm/test/Transforms/InstCombine/pr2645-0.ll
index 21bfa64a8604c..da883a386b1c6 100644
--- a/llvm/test/Transforms/InstCombine/pr2645-0.ll
+++ b/llvm/test/Transforms/InstCombine/pr2645-0.ll
@@ -1,4 +1,5 @@
-; RUN: opt < %s -instcombine -S | grep "insertelement <4 x float> undef"
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | grep "insertelement <4 x float> poison"
 
 ; Instcombine should be able to prove that none of the
 ; insertelement's first operand's elements are needed.
diff --git a/llvm/test/Transforms/InstCombine/pr38984-inseltpoison.ll b/llvm/test/Transforms/InstCombine/pr38984-inseltpoison.ll
new file mode 100644
index 0000000000000..ec69291fb87cb
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/pr38984-inseltpoison.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "p:16:16"
+
+@a = external global [21 x i16], align 1
+@offsets = external global [4 x i16], align 1
+
+; The "same gep" optimization should work with vector icmp.
+define <4 x i1> @PR38984_1() {
+; CHECK-LABEL: @PR38984_1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i1> <i1 true, i1 true, i1 true, i1 true>
+;
+entry:
+  %0 = load i16, i16* getelementptr ([4 x i16], [4 x i16]* @offsets, i16 0, i16 undef), align 1
+  %1 = insertelement <4 x i16> poison, i16 %0, i32 3
+  %2 = getelementptr i32, i32* null, <4 x i16> %1
+  %3 = getelementptr i32, i32* null, <4 x i16> %1
+  %4 = icmp eq <4 x i32*> %2, %3
+  ret <4 x i1> %4
+}
+
+; The "compare base pointers" optimization should not kick in for vector icmp.
+define <4 x i1> @PR38984_2() {
+; CHECK-LABEL: @PR38984_2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load i16, i16* getelementptr ([4 x i16], [4 x i16]* @offsets, i16 0, i16 undef), align 2
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[TMP0]], i32 3
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i16, i16* getelementptr inbounds ([21 x i16], [21 x i16]* @a, i16 1, i16 0), <4 x i16> [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr i16, i16* null, <4 x i16> [[TMP1]]
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq <4 x i16*> [[TMP2]], [[TMP3]]
+; CHECK-NEXT:    ret <4 x i1> [[TMP4]]
+;
+entry:
+  %0 = load i16, i16* getelementptr ([4 x i16], [4 x i16]* @offsets, i16 0, i16 undef)
+  %1 = insertelement <4 x i16> poison, i16 %0, i32 3
+  %2 = getelementptr i16, i16* getelementptr ([21 x i16], [21 x i16]* @a, i64 1, i32 0), <4 x i16> %1
+  %3 = getelementptr i16, i16* null, <4 x i16> %1
+  %4 = icmp eq <4 x i16*> %2, %3
+  ret <4 x i1> %4
+}
diff --git a/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll b/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll
new file mode 100644
index 0000000000000..b2f815971c46b
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/scalarization-inseltpoison.ll
@@ -0,0 +1,335 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+define i32 @extract_load(<4 x i32>* %p) {
+; CHECK-LABEL: @extract_load(
+; CHECK-NEXT:    [[X:%.*]] = load <4 x i32>, <4 x i32>* [[P:%.*]], align 4
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <4 x i32> [[X]], i32 1
+; CHECK-NEXT:    ret i32 [[EXT]]
+;
+  %x = load <4 x i32>, <4 x i32>* %p, align 4
+  %ext = extractelement <4 x i32> %x, i32 1
+  ret i32 %ext
+}
+
+define double @extract_load_fp(<4 x double>* %p) {
+; CHECK-LABEL: @extract_load_fp(
+; CHECK-NEXT:    [[X:%.*]] = load <4 x double>, <4 x double>* [[P:%.*]], align 32
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <4 x double> [[X]], i32 3
+; CHECK-NEXT:    ret double [[EXT]]
+;
+  %x = load <4 x double>, <4 x double>* %p, align 32
+  %ext = extractelement <4 x double> %x, i32 3
+  ret double %ext
+}
+
+define double @extract_load_volatile(<4 x double>* %p) {
+; CHECK-LABEL: @extract_load_volatile(
+; CHECK-NEXT:    [[X:%.*]] = load volatile <4 x double>, <4 x double>* [[P:%.*]], align 32
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <4 x double> [[X]], i32 2
+; CHECK-NEXT:    ret double [[EXT]]
+;
+  %x = load volatile <4 x double>, <4 x double>* %p
+  %ext = extractelement <4 x double> %x, i32 2
+  ret double %ext
+}
+
+define double @extract_load_extra_use(<4 x double>* %p, <4 x double>* %p2) {
+; CHECK-LABEL: @extract_load_extra_use(
+; CHECK-NEXT:    [[X:%.*]] = load <4 x double>, <4 x double>* [[P:%.*]], align 8
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <4 x double> [[X]], i32 0
+; CHECK-NEXT:    store <4 x double> [[X]], <4 x double>* [[P2:%.*]], align 32
+; CHECK-NEXT:    ret double [[EXT]]
+;
+  %x = load <4 x double>, <4 x double>* %p, align 8
+  %ext = extractelement <4 x double> %x, i32 0
+  store <4 x double> %x, <4 x double>* %p2
+  ret double %ext
+}
+
+define double @extract_load_variable_index(<4 x double>* %p, i32 %y) {
+; CHECK-LABEL: @extract_load_variable_index(
+; CHECK-NEXT:    [[X:%.*]] = load <4 x double>, <4 x double>* [[P:%.*]], align 32
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <4 x double> [[X]], i32 [[Y:%.*]]
+; CHECK-NEXT:    ret double [[EXT]]
+;
+  %x = load <4 x double>, <4 x double>* %p
+  %ext = extractelement <4 x double> %x, i32 %y
+  ret double %ext
+}
+
+define void @scalarize_phi(i32 * %n, float * %inout) {
+; CHECK-LABEL: @scalarize_phi(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[T0:%.*]] = load volatile float, float* [[INOUT:%.*]], align 4
+; CHECK-NEXT:    br label [[FOR_COND:%.*]]
+; CHECK:       for.cond:
+; CHECK-NEXT:    [[TMP0:%.*]] = phi float [ [[T0]], [[ENTRY:%.*]] ], [ [[TMP1:%.*]], [[FOR_BODY:%.*]] ]
+; CHECK-NEXT:    [[I_0:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[INC:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[T1:%.*]] = load i32, i32* [[N:%.*]], align 4
+; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq i32 [[I_0]], [[T1]]
+; CHECK-NEXT:    br i1 [[CMP_NOT]], label [[FOR_END:%.*]], label [[FOR_BODY]]
+; CHECK:       for.body:
+; CHECK-NEXT:    store volatile float [[TMP0]], float* [[INOUT]], align 4
+; CHECK-NEXT:    [[TMP1]] = fmul float [[TMP0]], 0x4002A3D700000000
+; CHECK-NEXT:    [[INC]] = add nuw nsw i32 [[I_0]], 1
+; CHECK-NEXT:    br label [[FOR_COND]]
+; CHECK:       for.end:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %t0 = load volatile float, float * %inout, align 4
+  %insert = insertelement <4 x float> poison, float %t0, i32 0
+  %splat = shufflevector <4 x float> %insert, <4 x float> undef, <4 x i32> zeroinitializer
+  %insert1 = insertelement <4 x float> poison, float 3.0, i32 0
+  br label %for.cond
+
+for.cond:
+  %x.0 = phi <4 x float> [ %splat, %entry ], [ %mul, %for.body ]
+  %i.0 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %t1 = load i32, i32 * %n, align 4
+  %cmp = icmp ne i32 %i.0, %t1
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:
+  %t2 = extractelement <4 x float> %x.0, i32 1
+  store volatile float %t2, float * %inout, align 4
+  %mul = fmul <4 x float> %x.0, <float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000>
+  %inc = add nsw i32 %i.0, 1
+  br label %for.cond
+
+for.end:
+  ret void
+}
+
+define float @extract_element_binop_splat_constant_index(<4 x float> %x) {
+; CHECK-LABEL: @extract_element_binop_splat_constant_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[X:%.*]], i32 2
+; CHECK-NEXT:    [[R:%.*]] = fadd float [[TMP1]], 0x4002A3D700000000
+; CHECK-NEXT:    ret float [[R]]
+;
+  %b = fadd <4 x float> %x, <float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000, float 0x4002A3D700000000>
+  %r = extractelement <4 x float> %b, i32 2
+  ret float %r
+}
+
+define double @extract_element_binop_splat_with_undef_constant_index(<2 x double> %x) {
+; CHECK-LABEL: @extract_element_binop_splat_with_undef_constant_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x double> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = fdiv double 4.200000e+01, [[TMP1]]
+; CHECK-NEXT:    ret double [[R]]
+;
+  %b = fdiv <2 x double> <double 42.0, double undef>, %x
+  %r = extractelement <2 x double> %b, i32 0
+  ret double %r
+}
+
+define float @extract_element_binop_nonsplat_constant_index(<2 x float> %x) {
+; CHECK-LABEL: @extract_element_binop_nonsplat_constant_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x float> [[X:%.*]], i32 1
+; CHECK-NEXT:    [[R:%.*]] = fmul float [[TMP1]], 4.300000e+01
+; CHECK-NEXT:    ret float [[R]]
+;
+  %b = fmul <2 x float> %x, <float 42.0, float 43.0>
+  %r = extractelement <2 x float> %b, i32 1
+  ret float %r
+}
+
+define i8 @extract_element_binop_splat_variable_index(<4 x i8> %x, i32 %y) {
+; CHECK-LABEL: @extract_element_binop_splat_variable_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = sdiv i8 [[TMP1]], 42
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %b = sdiv <4 x i8> %x, <i8 42, i8 42, i8 42, i8 42>
+  %r = extractelement <4 x i8> %b, i32 %y
+  ret i8 %r
+}
+
+define i8 @extract_element_binop_splat_with_undef_variable_index(<4 x i8> %x, i32 %y) {
+; CHECK-LABEL: @extract_element_binop_splat_with_undef_variable_index(
+; CHECK-NEXT:    [[B:%.*]] = mul <4 x i8> [[X:%.*]], <i8 42, i8 42, i8 undef, i8 42>
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x i8> [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %b = mul <4 x i8> %x, <i8 42, i8 42, i8 undef, i8 42>
+  %r = extractelement <4 x i8> %b, i32 %y
+  ret i8 %r
+}
+
+define i8 @extract_element_binop_nonsplat_variable_index(<4 x i8> %x, i32 %y) {
+; CHECK-LABEL: @extract_element_binop_nonsplat_variable_index(
+; CHECK-NEXT:    [[B:%.*]] = lshr <4 x i8> [[X:%.*]], <i8 4, i8 3, i8 undef, i8 2>
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x i8> [[B]], i32 [[Y:%.*]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %b = lshr <4 x i8> %x, <i8 4, i8 3, i8 undef, i8 2>
+  %r = extractelement <4 x i8> %b, i32 %y
+  ret i8 %r
+}
+
+define float @extract_element_load(<4 x float> %x, <4 x float>* %ptr) {
+; CHECK-LABEL: @extract_element_load(
+; CHECK-NEXT:    [[LOAD:%.*]] = load <4 x float>, <4 x float>* [[PTR:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[LOAD]], i32 2
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[X:%.*]], i32 2
+; CHECK-NEXT:    [[R:%.*]] = fadd float [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret float [[R]]
+;
+  %load = load <4 x float>, <4 x float>* %ptr
+  %add = fadd <4 x float> %x, %load
+  %r = extractelement <4 x float> %add, i32 2
+  ret float %r
+}
+
+define float @extract_element_multi_Use_load(<4 x float> %x, <4 x float>* %ptr0, <4 x float>* %ptr1) {
+; CHECK-LABEL: @extract_element_multi_Use_load(
+; CHECK-NEXT:    [[LOAD:%.*]] = load <4 x float>, <4 x float>* [[PTR0:%.*]], align 16
+; CHECK-NEXT:    store <4 x float> [[LOAD]], <4 x float>* [[PTR1:%.*]], align 16
+; CHECK-NEXT:    [[ADD:%.*]] = fadd <4 x float> [[LOAD]], [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x float> [[ADD]], i32 2
+; CHECK-NEXT:    ret float [[R]]
+;
+  %load = load <4 x float>, <4 x float>* %ptr0
+  store <4 x float> %load, <4 x float>* %ptr1
+  %add = fadd <4 x float> %x, %load
+  %r = extractelement <4 x float> %add, i32 2
+  ret float %r
+}
+
+define float @extract_element_variable_index(<4 x float> %x, i32 %y) {
+; CHECK-LABEL: @extract_element_variable_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[X:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = fadd float [[TMP1]], 1.000000e+00
+; CHECK-NEXT:    ret float [[R]]
+;
+  %add = fadd <4 x float> %x, <float 1.0, float 1.0, float 1.0, float 1.0>
+  %r = extractelement <4 x float> %add, i32 %y
+  ret float %r
+}
+
+define float @extelt_binop_insertelt(<4 x float> %A, <4 x float> %B, float %f) {
+; CHECK-LABEL: @extelt_binop_insertelt(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[B:%.*]], i32 0
+; CHECK-NEXT:    [[E:%.*]] = fmul nnan float [[TMP1]], [[F:%.*]]
+; CHECK-NEXT:    ret float [[E]]
+;
+  %C = insertelement <4 x float> %A, float %f, i32 0
+  %D = fmul nnan <4 x float> %C, %B
+  %E = extractelement <4 x float> %D, i32 0
+  ret float %E
+}
+
+; We recurse to find a scalarizable operand.
+; FIXME: We should propagate the IR flags including wrapping flags.
+
+define i32 @extelt_binop_binop_insertelt(<4 x i32> %A, <4 x i32> %B, i32 %f) {
+; CHECK-LABEL: @extelt_binop_binop_insertelt(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[TMP1]], [[F:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i32> [[B]], i32 0
+; CHECK-NEXT:    [[E:%.*]] = mul i32 [[TMP2]], [[TMP3]]
+; CHECK-NEXT:    ret i32 [[E]]
+;
+  %v = insertelement <4 x i32> %A, i32 %f, i32 0
+  %C = add <4 x i32> %v, %B
+  %D = mul nsw <4 x i32> %C, %B
+  %E = extractelement <4 x i32> %D, i32 0
+  ret i32 %E
+}
+
+define float @extract_element_constant_vector_variable_index(i32 %y) {
+; CHECK-LABEL: @extract_element_constant_vector_variable_index(
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>, i32 [[Y:%.*]]
+; CHECK-NEXT:    ret float [[R]]
+;
+  %r = extractelement <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, i32 %y
+  ret float %r
+}
+
+define i1 @cheap_to_extract_icmp(<4 x i32> %x, <4 x i1> %y) {
+; CHECK-LABEL: @cheap_to_extract_icmp(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 2
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i1> [[Y:%.*]], i32 2
+; CHECK-NEXT:    [[R:%.*]] = and i1 [[TMP2]], [[TMP3]]
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cmp = icmp eq <4 x i32> %x, zeroinitializer
+  %and = and <4 x i1> %cmp, %y
+  %r = extractelement <4 x i1> %and, i32 2
+  ret i1 %r
+}
+
+define i1 @cheap_to_extract_fcmp(<4 x float> %x, <4 x i1> %y) {
+; CHECK-LABEL: @cheap_to_extract_fcmp(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x float> [[X:%.*]], i32 2
+; CHECK-NEXT:    [[TMP2:%.*]] = fcmp oeq float [[TMP1]], 0.000000e+00
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i1> [[Y:%.*]], i32 2
+; CHECK-NEXT:    [[R:%.*]] = and i1 [[TMP2]], [[TMP3]]
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cmp = fcmp oeq <4 x float> %x, zeroinitializer
+  %and = and <4 x i1> %cmp, %y
+  %r = extractelement <4 x i1> %and, i32 2
+  ret i1 %r
+}
+
+define i1 @extractelt_vector_icmp_constrhs(<2 x i32> %arg) {
+; CHECK-LABEL: @extractelt_vector_icmp_constrhs(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[EXT:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[EXT]]
+;
+  %cmp = icmp eq <2 x i32> %arg, zeroinitializer
+  %ext = extractelement <2 x i1> %cmp, i32 0
+  ret i1 %ext
+}
+
+define i1 @extractelt_vector_fcmp_constrhs(<2 x float> %arg) {
+; CHECK-LABEL: @extractelt_vector_fcmp_constrhs(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x float> [[ARG:%.*]], i32 0
+; CHECK-NEXT:    [[EXT:%.*]] = fcmp oeq float [[TMP1]], 0.000000e+00
+; CHECK-NEXT:    ret i1 [[EXT]]
+;
+  %cmp = fcmp oeq <2 x float> %arg, zeroinitializer
+  %ext = extractelement <2 x i1> %cmp, i32 0
+  ret i1 %ext
+}
+
+define i1 @extractelt_vector_icmp_constrhs_dynidx(<2 x i32> %arg, i32 %idx) {
+; CHECK-LABEL: @extractelt_vector_icmp_constrhs_dynidx(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i32> [[ARG:%.*]], i32 [[IDX:%.*]]
+; CHECK-NEXT:    [[EXT:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT:    ret i1 [[EXT]]
+;
+  %cmp = icmp eq <2 x i32> %arg, zeroinitializer
+  %ext = extractelement <2 x i1> %cmp, i32 %idx
+  ret i1 %ext
+}
+
+define i1 @extractelt_vector_fcmp_constrhs_dynidx(<2 x float> %arg, i32 %idx) {
+; CHECK-LABEL: @extractelt_vector_fcmp_constrhs_dynidx(
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x float> [[ARG:%.*]], i32 [[IDX:%.*]]
+; CHECK-NEXT:    [[EXT:%.*]] = fcmp oeq float [[TMP1]], 0.000000e+00
+; CHECK-NEXT:    ret i1 [[EXT]]
+;
+  %cmp = fcmp oeq <2 x float> %arg, zeroinitializer
+  %ext = extractelement <2 x i1> %cmp, i32 %idx
+  ret i1 %ext
+}
+
+define i1 @extractelt_vector_fcmp_not_cheap_to_scalarize_multi_use(<2 x float> %arg0, <2 x float> %arg1, <2 x float> %arg2, i32 %idx) {
+; CHECK-LABEL: @extractelt_vector_fcmp_not_cheap_to_scalarize_multi_use(
+; CHECK-NEXT:    [[ADD:%.*]] = fadd <2 x float> [[ARG1:%.*]], [[ARG2:%.*]]
+; CHECK-NEXT:    store volatile <2 x float> [[ADD]], <2 x float>* undef, align 8
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp oeq <2 x float> [[ADD]], [[ARG0:%.*]]
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <2 x i1> [[CMP]], i32 0
+; CHECK-NEXT:    ret i1 [[EXT]]
+;
+  %add = fadd <2 x float> %arg1, %arg2
+  store volatile <2 x float> %add, <2 x float>* undef
+  %cmp = fcmp oeq <2 x float> %arg0, %add
+  %ext = extractelement <2 x i1> %cmp, i32 0
+  ret i1 %ext
+}
diff --git a/llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll b/llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll
new file mode 100644
index 0000000000000..a59782378b9ac
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll
@@ -0,0 +1,213 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+declare void @v4float_user(<4 x float>) #0
+
+define float @extract_one_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 {
+; CHECK-LABEL: @extract_one_select(
+; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
+; CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <4 x float> [[SEL]], i32 2
+; CHECK-NEXT:    ret float [[EXTRACT]]
+;
+  %cmp = icmp ne i32 %c, 0
+  %sel = select i1 %cmp, <4 x float> %a, <4 x float> %b
+  %extract = extractelement <4 x float> %sel, i32 2
+  ret float %extract
+}
+
+; Multiple extractelements
+define <2 x float> @extract_two_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 {
+; CHECK-LABEL: @extract_two_select(
+; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
+; CHECK-NEXT:    [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT:    ret <2 x float> [[BUILD2]]
+;
+  %cmp = icmp ne i32 %c, 0
+  %sel = select i1 %cmp, <4 x float> %a, <4 x float> %b
+  %extract1 = extractelement <4 x float> %sel, i32 1
+  %extract2 = extractelement <4 x float> %sel, i32 2
+  %build1 = insertelement <2 x float> poison, float %extract1, i32 0
+  %build2 = insertelement <2 x float> %build1, float %extract2, i32 1
+  ret <2 x float> %build2
+}
+
+; Select has an extra non-extractelement user, don't change it
+define float @extract_one_select_user(<4 x float> %a, <4 x float> %b, i32 %c) #0 {
+; CHECK-LABEL: @extract_one_select_user(
+; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
+; CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <4 x float> [[SEL]], i32 2
+; CHECK-NEXT:    call void @v4float_user(<4 x float> [[SEL]])
+; CHECK-NEXT:    ret float [[EXTRACT]]
+;
+  %cmp = icmp ne i32 %c, 0
+  %sel = select i1 %cmp, <4 x float> %a, <4 x float> %b
+  %extract = extractelement <4 x float> %sel, i32 2
+  call void @v4float_user(<4 x float> %sel)
+  ret float %extract
+}
+
+define float @extract_one_vselect_user(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @extract_one_vselect_user(
+; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer
+; CHECK-NEXT:    [[SEL:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
+; CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <4 x float> [[SEL]], i32 2
+; CHECK-NEXT:    call void @v4float_user(<4 x float> [[SEL]])
+; CHECK-NEXT:    ret float [[EXTRACT]]
+;
+  %cmp = icmp ne <4 x i32> %c, zeroinitializer
+  %sel = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b
+  %extract = extractelement <4 x float> %sel, i32 2
+  call void @v4float_user(<4 x float> %sel)
+  ret float %extract
+}
+
+; Do not convert the vector select into a scalar select. That would increase
+; the instruction count and potentially obfuscate a vector min/max idiom.
+
+define float @extract_one_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @extract_one_vselect(
+; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer
+; CHECK-NEXT:    [[SELECT:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
+; CHECK-NEXT:    [[EXTRACT:%.*]] = extractelement <4 x float> [[SELECT]], i32 0
+; CHECK-NEXT:    ret float [[EXTRACT]]
+;
+  %cmp = icmp ne <4 x i32> %c, zeroinitializer
+  %select = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b
+  %extract = extractelement <4 x float> %select, i32 0
+  ret float %extract
+}
+
+; Multiple extractelements from a vector select
+define <2 x float> @extract_two_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @extract_two_vselect(
+; CHECK-NEXT:    [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer
+; CHECK-NEXT:    [[SEL:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
+; CHECK-NEXT:    [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> undef, <2 x i32> <i32 1, i32 2>
+; CHECK-NEXT:    ret <2 x float> [[BUILD2]]
+;
+  %cmp = icmp ne <4 x i32> %c, zeroinitializer
+  %sel = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b
+  %extract1 = extractelement <4 x float> %sel, i32 1
+  %extract2 = extractelement <4 x float> %sel, i32 2
+  %build1 = insertelement <2 x float> poison, float %extract1, i32 0
+  %build2 = insertelement <2 x float> %build1, float %extract2, i32 1
+  ret <2 x float> %build2
+}
+
+; The vector selects are not decomposed into scalar selects because that would increase
+; the instruction count. Extract+insert is converted to non-lane-crossing shuffles.
+; Test multiple extractelements
+define <4 x float> @simple_vector_select(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @simple_vector_select(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = extractelement <4 x i32> [[C:%.*]], i32 0
+; CHECK-NEXT:    [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP0]], 0
+; CHECK-NEXT:    [[A_SINK:%.*]] = select i1 [[TOBOOL_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[C]], i32 1
+; CHECK-NEXT:    [[TOBOOL1_NOT:%.*]] = icmp eq i32 [[TMP1]], 0
+; CHECK-NEXT:    [[A_SINK1:%.*]] = select i1 [[TOBOOL1_NOT]], <4 x float> [[B]], <4 x float> [[A]]
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x float> [[A_SINK]], <4 x float> [[A_SINK1]], <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i32> [[C]], i32 2
+; CHECK-NEXT:    [[TOBOOL6_NOT:%.*]] = icmp eq i32 [[TMP3]], 0
+; CHECK-NEXT:    [[A_SINK2:%.*]] = select i1 [[TOBOOL6_NOT]], <4 x float> [[B]], <4 x float> [[A]]
+; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> [[A_SINK2]], <4 x i32> <i32 0, i32 1, i32 6, i32 undef>
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[C]], i32 3
+; CHECK-NEXT:    [[TOBOOL11_NOT:%.*]] = icmp eq i32 [[TMP5]], 0
+; CHECK-NEXT:    [[A_SINK3:%.*]] = select i1 [[TOBOOL11_NOT]], <4 x float> [[B]], <4 x float> [[A]]
+; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> [[A_SINK3]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
+; CHECK-NEXT:    ret <4 x float> [[TMP6]]
+;
+entry:
+  %0 = extractelement <4 x i32> %c, i32 0
+  %tobool = icmp ne i32 %0, 0
+  %a.sink = select i1 %tobool, <4 x float> %a, <4 x float> %b
+  %1 = extractelement <4 x float> %a.sink, i32 0
+  %2 = insertelement <4 x float> poison, float %1, i32 0
+  %3 = extractelement <4 x i32> %c, i32 1
+  %tobool1 = icmp ne i32 %3, 0
+  %a.sink1 = select i1 %tobool1, <4 x float> %a, <4 x float> %b
+  %4 = extractelement <4 x float> %a.sink1, i32 1
+  %5 = insertelement <4 x float> %2, float %4, i32 1
+  %6 = extractelement <4 x i32> %c, i32 2
+  %tobool6 = icmp ne i32 %6, 0
+  %a.sink2 = select i1 %tobool6, <4 x float> %a, <4 x float> %b
+  %7 = extractelement <4 x float> %a.sink2, i32 2
+  %8 = insertelement <4 x float> %5, float %7, i32 2
+  %9 = extractelement <4 x i32> %c, i32 3
+  %tobool11 = icmp ne i32 %9, 0
+  %a.sink3 = select i1 %tobool11, <4 x float> %a, <4 x float> %b
+  %10 = extractelement <4 x float> %a.sink3, i32 3
+  %11 = insertelement <4 x float> %8, float %10, i32 3
+  ret <4 x float> %11
+}
+
+define <4 x i32> @extract_cond(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv) {
+; CHECK-LABEL: @extract_cond(
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <4 x i1> [[CONDV:%.*]], <4 x i1> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+; CHECK-NEXT:    [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %cond = extractelement <4 x i1> %condv, i32 3
+  %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @splat_cond(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv) {
+; CHECK-LABEL: @splat_cond(
+; CHECK-NEXT:    [[SPLATCOND:%.*]] = shufflevector <4 x i1> [[CONDV:%.*]], <4 x i1> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+; CHECK-NEXT:    [[R:%.*]] = select <4 x i1> [[SPLATCOND]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatcond = shufflevector <4 x i1> %condv, <4 x i1> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
+  %r = select <4 x i1> %splatcond, <4 x i32> %x, <4 x i32> %y
+  ret <4 x i32> %r
+}
+
+declare void @extra_use(i1)
+
+; Negative test
+
+define <4 x i32> @extract_cond_extra_use(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv) {
+; CHECK-LABEL: @extract_cond_extra_use(
+; CHECK-NEXT:    [[COND:%.*]] = extractelement <4 x i1> [[CONDV:%.*]], i32 3
+; CHECK-NEXT:    call void @extra_use(i1 [[COND]])
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %cond = extractelement <4 x i1> %condv, i32 3
+  call void @extra_use(i1 %cond)
+  %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
+  ret <4 x i32> %r
+}
+
+; Negative test
+
+define <4 x i32> @extract_cond_variable_index(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv, i32 %index) {
+; CHECK-LABEL: @extract_cond_variable_index(
+; CHECK-NEXT:    [[COND:%.*]] = extractelement <4 x i1> [[CONDV:%.*]], i32 [[INDEX:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[COND]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %cond = extractelement <4 x i1> %condv, i32 %index
+  %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
+  ret <4 x i32> %r
+}
+
+; IR shuffle can alter the number of elements in the vector, so this is ok.
+
+define <4 x i32> @extract_cond_type_mismatch(<4 x i32> %x, <4 x i32> %y, <5 x i1> %condv) {
+; CHECK-LABEL: @extract_cond_type_mismatch(
+; CHECK-NEXT:    [[DOTSPLAT:%.*]] = shufflevector <5 x i1> [[CONDV:%.*]], <5 x i1> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %cond = extractelement <5 x i1> %condv, i32 1
+  %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
+  ret <4 x i32> %r
+}
+
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/Transforms/InstCombine/select_meta.ll b/llvm/test/Transforms/InstCombine/select_meta.ll
index be9d8be857d86..66aece44c199c 100644
--- a/llvm/test/Transforms/InstCombine/select_meta.ll
+++ b/llvm/test/Transforms/InstCombine/select_meta.ll
@@ -104,7 +104,7 @@ define i16 @t7(i32 %a) {
 
 define i32 @abs_nabs_x01(i32 %x) {
 ; CHECK-LABEL: @abs_nabs_x01(
-; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret i32 [[TMP1]]
 ;
   %cmp = icmp sgt i32 %x, -1
@@ -120,7 +120,7 @@ define i32 @abs_nabs_x01(i32 %x) {
 
 define <2 x i32> @abs_nabs_x01_vec(<2 x i32> %x) {
 ; CHECK-LABEL: @abs_nabs_x01_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 true)
+; CHECK-NEXT:    [[TMP1:%.*]] = call <2 x i32> @llvm.abs.v2i32(<2 x i32> [[X:%.*]], i1 false)
 ; CHECK-NEXT:    ret <2 x i32> [[TMP1]]
 ;
   %cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
diff --git a/llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll b/llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll
new file mode 100644
index 0000000000000..8d1f068136f1c
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/shift-add-inseltpoison.ll
@@ -0,0 +1,122 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; This test makes sure that these instructions are properly eliminated.
+;
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i32 @shl_C1_add_A_C2_i32(i16 %A) {
+; CHECK-LABEL: @shl_C1_add_A_C2_i32(
+; CHECK-NEXT:    [[B:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT:    [[D:%.*]] = shl i32 192, [[B]]
+; CHECK-NEXT:    ret i32 [[D]]
+;
+  %B = zext i16 %A to i32
+  %C = add i32 %B, 5
+  %D = shl i32 6, %C
+  ret i32 %D
+}
+
+define i32 @ashr_C1_add_A_C2_i32(i32 %A) {
+; CHECK-LABEL: @ashr_C1_add_A_C2_i32(
+; CHECK-NEXT:    ret i32 0
+;
+  %B = and i32 %A, 65535
+  %C = add i32 %B, 5
+  %D = ashr i32 6, %C
+  ret i32 %D
+}
+
+define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
+; CHECK-LABEL: @lshr_C1_add_A_C2_i32(
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[A:%.*]], 65535
+; CHECK-NEXT:    [[D:%.*]] = shl i32 192, [[B]]
+; CHECK-NEXT:    ret i32 [[D]]
+;
+  %B = and i32 %A, 65535
+  %C = add i32 %B, 5
+  %D = shl i32 6, %C
+  ret i32 %D
+}
+
+define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
+; CHECK-LABEL: @shl_C1_add_A_C2_v4i32(
+; CHECK-NEXT:    [[B:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[D:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 poison, i32 -458752>, [[B]]
+; CHECK-NEXT:    ret <4 x i32> [[D]]
+;
+  %B = zext <4 x i16> %A to <4 x i32>
+  %C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
+  %D = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
+  ret <4 x i32> %D
+}
+
+define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) {
+; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32(
+; CHECK-NEXT:    [[B:%.*]] = and <4 x i32> [[A:%.*]], <i32 0, i32 15, i32 255, i32 65535>
+; CHECK-NEXT:    [[D:%.*]] = ashr <4 x i32> <i32 6, i32 1, i32 poison, i32 -1>, [[B]]
+; CHECK-NEXT:    ret <4 x i32> [[D]]
+;
+  %B = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
+  %C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
+  %D = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
+  ret <4 x i32> %D
+}
+
+define <4 x i32> @lshr_C1_add_A_C2_v4i32(<4 x i32> %A) {
+; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32(
+; CHECK-NEXT:    [[B:%.*]] = and <4 x i32> [[A:%.*]], <i32 0, i32 15, i32 255, i32 65535>
+; CHECK-NEXT:    [[D:%.*]] = lshr <4 x i32> <i32 6, i32 1, i32 poison, i32 65535>, [[B]]
+; CHECK-NEXT:    ret <4 x i32> [[D]]
+;
+  %B = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
+  %C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
+  %D = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
+  ret <4 x i32> %D
+}
+
+define <4 x i32> @shl_C1_add_A_C2_v4i32_splat(i16 %I) {
+; CHECK-LABEL: @shl_C1_add_A_C2_v4i32_splat(
+; CHECK-NEXT:    [[A:%.*]] = zext i16 [[I:%.*]] to i32
+; CHECK-NEXT:    [[B:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
+; CHECK-NEXT:    [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[E:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 poison, i32 -458752>, [[C]]
+; CHECK-NEXT:    ret <4 x i32> [[E]]
+;
+  %A = zext i16 %I to i32
+  %B = insertelement <4 x i32> poison, i32 %A, i32 0
+  %C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
+  %D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
+  %E = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
+  ret <4 x i32> %E
+}
+
+define <4 x i32> @ashr_C1_add_A_C2_v4i32_splat(i16 %I) {
+; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32_splat(
+; CHECK-NEXT:    [[A:%.*]] = zext i16 [[I:%.*]] to i32
+; CHECK-NEXT:    [[B:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
+; CHECK-NEXT:    [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[E:%.*]] = ashr <4 x i32> <i32 6, i32 1, i32 poison, i32 -1>, [[C]]
+; CHECK-NEXT:    ret <4 x i32> [[E]]
+;
+  %A = zext i16 %I to i32
+  %B = insertelement <4 x i32> poison, i32 %A, i32 0
+  %C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
+  %D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
+  %E = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
+  ret <4 x i32> %E
+}
+
+define <4 x i32> @lshr_C1_add_A_C2_v4i32_splat(i16 %I) {
+; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32_splat(
+; CHECK-NEXT:    [[A:%.*]] = zext i16 [[I:%.*]] to i32
+; CHECK-NEXT:    [[B:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
+; CHECK-NEXT:    [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[E:%.*]] = lshr <4 x i32> <i32 6, i32 1, i32 poison, i32 65535>, [[C]]
+; CHECK-NEXT:    ret <4 x i32> [[E]]
+;
+  %A = zext i16 %I to i32
+  %B = insertelement <4 x i32> poison, i32 %A, i32 0
+  %C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
+  %D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
+  %E = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
+  ret <4 x i32> %E
+}
diff --git a/llvm/test/Transforms/InstCombine/shuffle_select.ll b/llvm/test/Transforms/InstCombine/shuffle_select.ll
index d3de3e85332a8..63424a145cb46 100644
--- a/llvm/test/Transforms/InstCombine/shuffle_select.ll
+++ b/llvm/test/Transforms/InstCombine/shuffle_select.ll
@@ -52,7 +52,7 @@ define <4 x i32> @add_nuw_nsw_undef_mask_elt(<4 x i32> %v) {
 
 define <4 x i32> @sub(<4 x i32> %v) {
 ; CHECK-LABEL: @sub(
-; CHECK-NEXT:    [[B:%.*]] = sub <4 x i32> <i32 undef, i32 undef, i32 undef, i32 14>, [[V:%.*]]
+; CHECK-NEXT:    [[B:%.*]] = sub <4 x i32> <i32 poison, i32 poison, i32 poison, i32 14>, [[V:%.*]]
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i32> [[V]], <4 x i32> [[B]], <4 x i32> <i32 0, i32 1, i32 2, i32 7>
 ; CHECK-NEXT:    ret <4 x i32> [[S]]
 ;
@@ -348,7 +348,7 @@ define <4 x float> @fadd(<4 x float> %v) {
 
 define <4 x double> @fsub(<4 x double> %v) {
 ; CHECK-LABEL: @fsub(
-; CHECK-NEXT:    [[B:%.*]] = fsub <4 x double> <double undef, double undef, double 4.300000e+01, double 4.400000e+01>, [[V:%.*]]
+; CHECK-NEXT:    [[B:%.*]] = fsub <4 x double> <double poison, double poison, double 4.300000e+01, double 4.400000e+01>, [[V:%.*]]
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x double> [[V]], <4 x double> [[B]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
 ; CHECK-NEXT:    ret <4 x double> [[S]]
 ;
@@ -371,7 +371,7 @@ define <4 x float> @fmul(<4 x float> %v) {
 
 define <4 x double> @fdiv_constant_op0(<4 x double> %v) {
 ; CHECK-LABEL: @fdiv_constant_op0(
-; CHECK-NEXT:    [[B:%.*]] = fdiv fast <4 x double> <double undef, double undef, double 4.300000e+01, double 4.400000e+01>, [[V:%.*]]
+; CHECK-NEXT:    [[B:%.*]] = fdiv fast <4 x double> <double poison, double poison, double 4.300000e+01, double 4.400000e+01>, [[V:%.*]]
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x double> [[V]], <4 x double> [[B]], <4 x i32> <i32 undef, i32 1, i32 6, i32 7>
 ; CHECK-NEXT:    ret <4 x double> [[S]]
 ;
@@ -392,7 +392,7 @@ define <4 x double> @fdiv_constant_op1(<4 x double> %v) {
 
 define <4 x double> @frem(<4 x double> %v) {
 ; CHECK-LABEL: @frem(
-; CHECK-NEXT:    [[B:%.*]] = frem <4 x double> <double 4.100000e+01, double 4.200000e+01, double undef, double undef>, [[V:%.*]]
+; CHECK-NEXT:    [[B:%.*]] = frem <4 x double> <double 4.100000e+01, double 4.200000e+01, double poison, double poison>, [[V:%.*]]
 ; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x double> [[B]], <4 x double> [[V]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
 ; CHECK-NEXT:    ret <4 x double> [[S]]
 ;
@@ -791,8 +791,8 @@ define <4 x double> @fdiv_fdiv(<4 x double> %v0) {
 
 define <4 x double> @frem_frem(<4 x double> %v0) {
 ; CHECK-LABEL: @frem_frem(
-; CHECK-NEXT:    [[T1:%.*]] = frem <4 x double> <double 1.000000e+00, double 2.000000e+00, double undef, double undef>, [[V0:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = frem <4 x double> [[V0]], <double undef, double undef, double 7.000000e+00, double 8.000000e+00>
+; CHECK-NEXT:    [[T1:%.*]] = frem <4 x double> <double 1.000000e+00, double 2.000000e+00, double poison, double poison>, [[V0:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = frem <4 x double> [[V0]], <double poison, double poison, double 7.000000e+00, double 8.000000e+00>
 ; CHECK-NEXT:    [[T3:%.*]] = shufflevector <4 x double> [[T1]], <4 x double> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
 ; CHECK-NEXT:    ret <4 x double> [[T3]]
 ;
@@ -1284,8 +1284,8 @@ define <4 x double> @frem_2_vars(<4 x double> %v0, <4 x double> %v1) {
 
 define <4 x double> @fdiv_2_vars(<4 x double> %v0, <4 x double> %v1) {
 ; CHECK-LABEL: @fdiv_2_vars(
-; CHECK-NEXT:    [[T1:%.*]] = fdiv <4 x double> <double 1.000000e+00, double 2.000000e+00, double undef, double undef>, [[V0:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = fdiv <4 x double> [[V1:%.*]], <double undef, double undef, double 7.000000e+00, double 8.000000e+00>
+; CHECK-NEXT:    [[T1:%.*]] = fdiv <4 x double> <double 1.000000e+00, double 2.000000e+00, double poison, double poison>, [[V0:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = fdiv <4 x double> [[V1:%.*]], <double poison, double poison, double 7.000000e+00, double 8.000000e+00>
 ; CHECK-NEXT:    [[T3:%.*]] = shufflevector <4 x double> [[T1]], <4 x double> [[T2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
 ; CHECK-NEXT:    ret <4 x double> [[T3]]
 ;
@@ -1339,7 +1339,7 @@ define <4 x i32> @mul_is_nop_shl(<4 x i32> %v0) {
 define <4 x i32> @shl_mul_not_constant_shift_amount(<4 x i32> %v0) {
 ; CHECK-LABEL: @shl_mul_not_constant_shift_amount(
 ; CHECK-NEXT:    [[T1:%.*]] = shl <4 x i32> <i32 1, i32 2, i32 3, i32 4>, [[V0:%.*]]
-; CHECK-NEXT:    [[T2:%.*]] = mul <4 x i32> [[V0]], <i32 5, i32 6, i32 undef, i32 undef>
+; CHECK-NEXT:    [[T2:%.*]] = mul <4 x i32> [[V0]], <i32 5, i32 6, i32 poison, i32 poison>
 ; CHECK-NEXT:    [[T3:%.*]] = shufflevector <4 x i32> [[T2]], <4 x i32> [[T1]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
 ; CHECK-NEXT:    ret <4 x i32> [[T3]]
 ;
@@ -1412,8 +1412,8 @@ define <4 x i8> @or_add(<4 x i8> %v) {
 define <4 x i8> @or_add_not_enough_masking(<4 x i8> %v) {
 ; CHECK-LABEL: @or_add_not_enough_masking(
 ; CHECK-NEXT:    [[V0:%.*]] = lshr <4 x i8> [[V:%.*]], <i8 1, i8 1, i8 1, i8 1>
-; CHECK-NEXT:    [[T1:%.*]] = or <4 x i8> [[V0]], <i8 undef, i8 undef, i8 -64, i8 -64>
-; CHECK-NEXT:    [[T2:%.*]] = add <4 x i8> [[V0]], <i8 1, i8 2, i8 undef, i8 undef>
+; CHECK-NEXT:    [[T1:%.*]] = or <4 x i8> [[V0]], <i8 poison, i8 poison, i8 -64, i8 -64>
+; CHECK-NEXT:    [[T2:%.*]] = add <4 x i8> [[V0]], <i8 1, i8 2, i8 poison, i8 poison>
 ; CHECK-NEXT:    [[T3:%.*]] = shufflevector <4 x i8> [[T2]], <4 x i8> [[T1]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
 ; CHECK-NEXT:    ret <4 x i8> [[T3]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll b/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll
new file mode 100644
index 0000000000000..526048e0fc918
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll
@@ -0,0 +1,122 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S -o - | FileCheck %s
+
+; This test case was added as a reproducer for a miscompile, where instcombine
+; introduced an
+;   srem <2 x i16> %1, <i16 undef, i16 2>
+; instruction, which makes the whole srem undefined (even if we only end up
+; extracting the second element in the vector).
+define i16 @test_srem_orig(i16 %a, i1 %cmp) {
+; CHECK-LABEL: @test_srem_orig(
+; CHECK-NEXT:    [[SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[A:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = srem <2 x i16> [[SPLATINSERT]], <i16 2, i16 1>
+; CHECK-NEXT:    [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
+; CHECK-NEXT:    [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 poison, i16 1>, <2 x i16> [[SPLAT_OP]]
+; CHECK-NEXT:    [[T3:%.*]] = extractelement <2 x i16> [[T2]], i32 1
+; CHECK-NEXT:    ret i16 [[T3]]
+;
+  %splatinsert = insertelement <2 x i16> poison, i16 %a, i32 0
+  %splat = shufflevector <2 x i16> %splatinsert, <2 x i16> undef, <2 x i32> zeroinitializer
+  %t1 = select i1 %cmp, <2 x i16> <i16 1, i16 1>, <2 x i16> %splat
+  %t2 = srem <2 x i16> %t1, <i16 2, i16 2>
+  %t3 = extractelement <2 x i16> %t2, i32 1
+  ret i16 %t3
+}
+
+; This is basically a reduced version of test_srem_orig (based on what the
+; code would look like after a few iterations of instcombine, just before we
+; try to transform the shufflevector by doing
+; "evaluateInDifferentElementOrder".
+define <2 x i16> @test_srem(i16 %a, i1 %cmp) {
+; CHECK-LABEL: @test_srem(
+; CHECK-NEXT:    [[SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[A:%.*]], i32 0
+; CHECK-NEXT:    [[T1:%.*]] = srem <2 x i16> [[SPLATINSERT]], <i16 2, i16 1>
+; CHECK-NEXT:    [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
+; CHECK-NEXT:    [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
+; CHECK-NEXT:    ret <2 x i16> [[T2]]
+;
+  %splatinsert = insertelement <2 x i16> poison, i16 %a, i32 0
+  %t1 = srem <2 x i16> %splatinsert, <i16 2, i16 1>
+  %splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
+  %t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op
+  ret <2 x i16> %t2
+}
+
+define <2 x i16> @test_urem(i16 %a, i1 %cmp) {
+; CHECK-LABEL: @test_urem(
+; CHECK-NEXT:    [[SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[A:%.*]], i32 0
+; CHECK-NEXT:    [[T1:%.*]] = urem <2 x i16> [[SPLATINSERT]], <i16 3, i16 1>
+; CHECK-NEXT:    [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
+; CHECK-NEXT:    [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
+; CHECK-NEXT:    ret <2 x i16> [[T2]]
+;
+  %splatinsert = insertelement <2 x i16> poison, i16 %a, i32 0
+  %t1 = urem <2 x i16> %splatinsert, <i16 3, i16 1>
+  %splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
+  %t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op
+  ret <2 x i16> %t2
+}
+
+define <2 x i16> @test_sdiv(i16 %a, i1 %cmp) {
+; CHECK-LABEL: @test_sdiv(
+; CHECK-NEXT:    [[SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[A:%.*]], i32 0
+; CHECK-NEXT:    [[T1:%.*]] = sdiv <2 x i16> [[SPLATINSERT]], <i16 2, i16 1>
+; CHECK-NEXT:    [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
+; CHECK-NEXT:    [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
+; CHECK-NEXT:    ret <2 x i16> [[T2]]
+;
+  %splatinsert = insertelement <2 x i16> poison, i16 %a, i32 0
+  %t1 = sdiv <2 x i16> %splatinsert, <i16 2, i16 1>
+  %splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
+  %t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op
+  ret <2 x i16> %t2
+}
+
+define <2 x i16> @test_udiv(i16 %a, i1 %cmp) {
+; CHECK-LABEL: @test_udiv(
+; CHECK-NEXT:    [[SPLATINSERT:%.*]] = insertelement <2 x i16> poison, i16 [[A:%.*]], i32 0
+; CHECK-NEXT:    [[T1:%.*]] = udiv <2 x i16> [[SPLATINSERT]], <i16 3, i16 1>
+; CHECK-NEXT:    [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
+; CHECK-NEXT:    [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
+; CHECK-NEXT:    ret <2 x i16> [[T2]]
+;
+  %splatinsert = insertelement <2 x i16> poison, i16 %a, i32 0
+  %t1 = udiv <2 x i16> %splatinsert, <i16 3, i16 1>
+  %splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
+  %t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op
+  ret <2 x i16> %t2
+}
+
+; For fdiv we do not need to worry about div by undef. Verify that the
+; shufflevector is eliminated here.
+define <2 x float> @test_fdiv(float %a, float %b, i1 %cmp) {
+; CHECK-LABEL: @test_fdiv(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = fdiv <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
+; CHECK-NEXT:    [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[TMP2]]
+; CHECK-NEXT:    ret <2 x float> [[T2]]
+;
+  %splatinsert = insertelement <2 x float> poison, float %a, i32 0
+  %denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1
+  %t1 = fdiv <2 x float> %splatinsert, %denom
+  %splat.op = shufflevector <2 x float> %t1, <2 x float> undef, <2 x i32> <i32 undef, i32 0>
+  %t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op
+  ret <2 x float> %t2
+}
+
+; For frem we do not need to worry about div by undef. Verify that the
+; shufflevector is eliminated here.
+define <2 x float> @test_frem(float %a, float %b, i1 %cmp) {
+; CHECK-LABEL: @test_frem(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = frem <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
+; CHECK-NEXT:    [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[TMP2]]
+; CHECK-NEXT:    ret <2 x float> [[T2]]
+;
+  %splatinsert = insertelement <2 x float> poison, float %a, i32 0
+  %denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1
+  %t1 = frem <2 x float> %splatinsert, %denom
+  %splat.op = shufflevector <2 x float> %t1, <2 x float> undef, <2 x i32> <i32 undef, i32 0>
+  %t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op
+  ret <2 x float> %t2
+}
diff --git a/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll b/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
index 8364aab0aa232..3f12acbd39e57 100644
--- a/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
+++ b/llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll
@@ -11,7 +11,7 @@ define i16 @test_srem_orig(i16 %a, i1 %cmp) {
 ; CHECK-NEXT:    [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP1:%.*]] = srem <2 x i16> [[SPLATINSERT]], <i16 2, i16 1>
 ; CHECK-NEXT:    [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
-; CHECK-NEXT:    [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 undef, i16 1>, <2 x i16> [[SPLAT_OP]]
+; CHECK-NEXT:    [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 poison, i16 1>, <2 x i16> [[SPLAT_OP]]
 ; CHECK-NEXT:    [[T3:%.*]] = extractelement <2 x i16> [[T2]], i32 1
 ; CHECK-NEXT:    ret i16 [[T3]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/store.ll b/llvm/test/Transforms/InstCombine/store.ll
index 575fb0432d6cb..cda08f89501a2 100644
--- a/llvm/test/Transforms/InstCombine/store.ll
+++ b/llvm/test/Transforms/InstCombine/store.ll
@@ -23,8 +23,19 @@ define void @test2(i32* %P) {
   ret void
 }
 
-define void @store_at_gep_off_null(i64 %offset) {
-; CHECK-LABEL: @store_at_gep_off_null(
+define void @store_at_gep_off_null_inbounds(i64 %offset) {
+; CHECK-LABEL: @store_at_gep_off_null_inbounds(
+; CHECK-NEXT:    [[PTR:%.*]] = getelementptr inbounds i32, i32* null, i64 [[OFFSET:%.*]]
+; CHECK-NEXT:    store i32 undef, i32* [[PTR]], align 4
+; CHECK-NEXT:    ret void
+;
+  %ptr = getelementptr inbounds i32, i32 *null, i64 %offset
+  store i32 24, i32* %ptr
+  ret void
+}
+
+define void @store_at_gep_off_null_not_inbounds(i64 %offset) {
+; CHECK-LABEL: @store_at_gep_off_null_not_inbounds(
 ; CHECK-NEXT:    [[PTR:%.*]] = getelementptr i32, i32* null, i64 [[OFFSET:%.*]]
 ; CHECK-NEXT:    store i32 undef, i32* [[PTR]], align 4
 ; CHECK-NEXT:    ret void
@@ -36,11 +47,11 @@ define void @store_at_gep_off_null(i64 %offset) {
 
 define void @store_at_gep_off_no_null_opt(i64 %offset) #0 {
 ; CHECK-LABEL: @store_at_gep_off_no_null_opt(
-; CHECK-NEXT:    [[PTR:%.*]] = getelementptr i32, i32* null, i64 [[OFFSET:%.*]]
+; CHECK-NEXT:    [[PTR:%.*]] = getelementptr inbounds i32, i32* null, i64 [[OFFSET:%.*]]
 ; CHECK-NEXT:    store i32 24, i32* [[PTR]], align 4
 ; CHECK-NEXT:    ret void
 ;
-  %ptr = getelementptr i32, i32 *null, i64 %offset
+  %ptr = getelementptr inbounds i32, i32 *null, i64 %offset
   store i32 24, i32* %ptr
   ret void
 }
@@ -130,14 +141,14 @@ define void @test6(i32 %n, float* %a, i32* %gi) nounwind uwtable ssp {
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]]
 ; CHECK:       for.cond:
 ; CHECK-NEXT:    [[STOREMERGE:%.*]] = phi i32 [ 42, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
-; CHECK-NEXT:    store i32 [[STOREMERGE]], i32* [[GI:%.*]], align 4, !tbaa !0
+; CHECK-NEXT:    store i32 [[STOREMERGE]], i32* [[GI:%.*]], align 4, [[TBAA0:!tbaa !.*]]
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[STOREMERGE]], [[N:%.*]]
 ; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END:%.*]]
 ; CHECK:       for.body:
 ; CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[STOREMERGE]] to i64
 ; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[A:%.*]], i64 [[IDXPROM]]
-; CHECK-NEXT:    store float 0.000000e+00, float* [[ARRAYIDX]], align 4, !tbaa !4
-; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[GI]], align 4, !tbaa !0
+; CHECK-NEXT:    store float 0.000000e+00, float* [[ARRAYIDX]], align 4, [[TBAA4:!tbaa !.*]]
+; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[GI]], align 4, [[TBAA0]]
 ; CHECK-NEXT:    [[INC]] = add nsw i32 [[TMP0]], 1
 ; CHECK-NEXT:    br label [[FOR_COND]]
 ; CHECK:       for.end:
diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll
index 0331b3e38a633..63a13a0e9902e 100644
--- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll
+++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll
@@ -831,7 +831,7 @@ define <2 x i4> @negate_shufflevector_oneinput_second_lane_is_undef(<2 x i4> %x,
 define <2 x i4> @negate_shufflevector_twoinputs(<2 x i4> %x, <2 x i4> %y, <2 x i4> %z) {
 ; CHECK-LABEL: @negate_shufflevector_twoinputs(
 ; CHECK-NEXT:    [[T0_NEG:%.*]] = shl <2 x i4> <i4 6, i4 -5>, [[X:%.*]]
-; CHECK-NEXT:    [[T1_NEG:%.*]] = add <2 x i4> [[Y:%.*]], <i4 undef, i4 1>
+; CHECK-NEXT:    [[T1_NEG:%.*]] = add <2 x i4> [[Y:%.*]], <i4 poison, i4 1>
 ; CHECK-NEXT:    [[T2_NEG:%.*]] = shufflevector <2 x i4> [[T0_NEG]], <2 x i4> [[T1_NEG]], <2 x i32> <i32 0, i32 3>
 ; CHECK-NEXT:    [[T3:%.*]] = add <2 x i4> [[T2_NEG]], [[Z:%.*]]
 ; CHECK-NEXT:    ret <2 x i4> [[T3]]
diff --git a/llvm/test/Transforms/InstCombine/trunc-extractelement-inseltpoison.ll b/llvm/test/Transforms/InstCombine/trunc-extractelement-inseltpoison.ll
new file mode 100644
index 0000000000000..580854a432bf6
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/trunc-extractelement-inseltpoison.ll
@@ -0,0 +1,195 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S -data-layout="e" | FileCheck %s --check-prefixes=ANY,LE
+; RUN: opt < %s -instcombine -S -data-layout="E" | FileCheck %s --check-prefixes=ANY,BE
+
+define i32 @shrinkExtractElt_i64_to_i32_0(<3 x i64> %x) {
+; LE-LABEL: @shrinkExtractElt_i64_to_i32_0(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <6 x i32>
+; LE-NEXT:    [[T:%.*]] = extractelement <6 x i32> [[TMP1]], i32 0
+; LE-NEXT:    ret i32 [[T]]
+;
+; BE-LABEL: @shrinkExtractElt_i64_to_i32_0(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <6 x i32>
+; BE-NEXT:    [[T:%.*]] = extractelement <6 x i32> [[TMP1]], i32 1
+; BE-NEXT:    ret i32 [[T]]
+;
+  %e = extractelement <3 x i64> %x, i32 0
+  %t = trunc i64 %e to i32
+  ret i32 %t
+}
+
+define i32 @vscale_shrinkExtractElt_i64_to_i32_0(<vscale x 3 x i64> %x) {
+; LE-LABEL: @vscale_shrinkExtractElt_i64_to_i32_0(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 3 x i64> [[X:%.*]] to <vscale x 6 x i32>
+; LE-NEXT:    [[T:%.*]] = extractelement <vscale x 6 x i32> [[TMP1]], i32 0
+; LE-NEXT:    ret i32 [[T]]
+;
+; BE-LABEL: @vscale_shrinkExtractElt_i64_to_i32_0(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast <vscale x 3 x i64> [[X:%.*]] to <vscale x 6 x i32>
+; BE-NEXT:    [[T:%.*]] = extractelement <vscale x 6 x i32> [[TMP1]], i32 1
+; BE-NEXT:    ret i32 [[T]]
+;
+  %e = extractelement <vscale x 3 x i64> %x, i32 0
+  %t = trunc i64 %e to i32
+  ret i32 %t
+}
+
+
+define i32 @shrinkExtractElt_i64_to_i32_1(<3 x i64> %x) {
+; LE-LABEL: @shrinkExtractElt_i64_to_i32_1(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <6 x i32>
+; LE-NEXT:    [[T:%.*]] = extractelement <6 x i32> [[TMP1]], i32 2
+; LE-NEXT:    ret i32 [[T]]
+;
+; BE-LABEL: @shrinkExtractElt_i64_to_i32_1(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <6 x i32>
+; BE-NEXT:    [[T:%.*]] = extractelement <6 x i32> [[TMP1]], i32 3
+; BE-NEXT:    ret i32 [[T]]
+;
+  %e = extractelement <3 x i64> %x, i32 1
+  %t = trunc i64 %e to i32
+  ret i32 %t
+}
+
+define i32 @shrinkExtractElt_i64_to_i32_2(<3 x i64> %x) {
+; LE-LABEL: @shrinkExtractElt_i64_to_i32_2(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <6 x i32>
+; LE-NEXT:    [[T:%.*]] = extractelement <6 x i32> [[TMP1]], i32 4
+; LE-NEXT:    ret i32 [[T]]
+;
+; BE-LABEL: @shrinkExtractElt_i64_to_i32_2(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <6 x i32>
+; BE-NEXT:    [[T:%.*]] = extractelement <6 x i32> [[TMP1]], i32 5
+; BE-NEXT:    ret i32 [[T]]
+;
+  %e = extractelement <3 x i64> %x, i32 2
+  %t = trunc i64 %e to i32
+  ret i32 %t
+}
+
+define i16 @shrinkExtractElt_i64_to_i16_0(<3 x i64> %x) {
+; LE-LABEL: @shrinkExtractElt_i64_to_i16_0(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <12 x i16>
+; LE-NEXT:    [[T:%.*]] = extractelement <12 x i16> [[TMP1]], i32 0
+; LE-NEXT:    ret i16 [[T]]
+;
+; BE-LABEL: @shrinkExtractElt_i64_to_i16_0(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <12 x i16>
+; BE-NEXT:    [[T:%.*]] = extractelement <12 x i16> [[TMP1]], i32 3
+; BE-NEXT:    ret i16 [[T]]
+;
+  %e = extractelement <3 x i64> %x, i16 0
+  %t = trunc i64 %e to i16
+  ret i16 %t
+}
+
+define i16 @shrinkExtractElt_i64_to_i16_1(<3 x i64> %x) {
+; LE-LABEL: @shrinkExtractElt_i64_to_i16_1(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <12 x i16>
+; LE-NEXT:    [[T:%.*]] = extractelement <12 x i16> [[TMP1]], i32 4
+; LE-NEXT:    ret i16 [[T]]
+;
+; BE-LABEL: @shrinkExtractElt_i64_to_i16_1(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <12 x i16>
+; BE-NEXT:    [[T:%.*]] = extractelement <12 x i16> [[TMP1]], i32 7
+; BE-NEXT:    ret i16 [[T]]
+;
+  %e = extractelement <3 x i64> %x, i16 1
+  %t = trunc i64 %e to i16
+  ret i16 %t
+}
+
+define i16 @shrinkExtractElt_i64_to_i16_2(<3 x i64> %x) {
+; LE-LABEL: @shrinkExtractElt_i64_to_i16_2(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <12 x i16>
+; LE-NEXT:    [[T:%.*]] = extractelement <12 x i16> [[TMP1]], i32 8
+; LE-NEXT:    ret i16 [[T]]
+;
+; BE-LABEL: @shrinkExtractElt_i64_to_i16_2(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i64> [[X:%.*]] to <12 x i16>
+; BE-NEXT:    [[T:%.*]] = extractelement <12 x i16> [[TMP1]], i32 11
+; BE-NEXT:    ret i16 [[T]]
+;
+  %e = extractelement <3 x i64> %x, i16 2
+  %t = trunc i64 %e to i16
+  ret i16 %t
+}
+
+; Crazy types may be ok.
+define i11 @shrinkExtractElt_i33_to_11_2(<3 x i33> %x) {
+; LE-LABEL: @shrinkExtractElt_i33_to_11_2(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i33> [[X:%.*]] to <9 x i11>
+; LE-NEXT:    [[T:%.*]] = extractelement <9 x i11> [[TMP1]], i32 6
+; LE-NEXT:    ret i11 [[T]]
+;
+; BE-LABEL: @shrinkExtractElt_i33_to_11_2(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast <3 x i33> [[X:%.*]] to <9 x i11>
+; BE-NEXT:    [[T:%.*]] = extractelement <9 x i11> [[TMP1]], i32 8
+; BE-NEXT:    ret i11 [[T]]
+;
+  %e = extractelement <3 x i33> %x, i16 2
+  %t = trunc i33 %e to i11
+  ret i11 %t
+}
+
+; Do not optimize if it would result in an invalid bitcast instruction.
+define i13 @shrinkExtractElt_i67_to_i13_2(<3 x i67> %x) {
+; ANY-LABEL: @shrinkExtractElt_i67_to_i13_2(
+; ANY-NEXT:    [[E:%.*]] = extractelement <3 x i67> [[X:%.*]], i459 2
+; ANY-NEXT:    [[T:%.*]] = trunc i67 [[E]] to i13
+; ANY-NEXT:    ret i13 [[T]]
+;
+  %e = extractelement <3 x i67> %x, i459 2
+  %t = trunc i67 %e to i13
+  ret i13 %t
+}
+
+; Do not optimize if the bitcast instruction would be valid, but the
+; transform would be wrong.
+define i30 @shrinkExtractElt_i40_to_i30_1(<3 x i40> %x) {
+; ANY-LABEL: @shrinkExtractElt_i40_to_i30_1(
+; ANY-NEXT:    [[E:%.*]] = extractelement <3 x i40> [[X:%.*]], i32 1
+; ANY-NEXT:    [[T:%.*]] = trunc i40 [[E]] to i30
+; ANY-NEXT:    ret i30 [[T]]
+;
+  %e = extractelement <3 x i40> %x, i32 1
+  %t = trunc i40 %e to i30
+  ret i30 %t
+}
+
+; Do not canonicalize if that would increase the instruction count.
+declare void @use(i64)
+define i16 @shrinkExtractElt_i64_to_i16_2_extra_use(<3 x i64> %x) {
+; ANY-LABEL: @shrinkExtractElt_i64_to_i16_2_extra_use(
+; ANY-NEXT:    [[E:%.*]] = extractelement <3 x i64> [[X:%.*]], i64 2
+; ANY-NEXT:    call void @use(i64 [[E]])
+; ANY-NEXT:    [[T:%.*]] = trunc i64 [[E]] to i16
+; ANY-NEXT:    ret i16 [[T]]
+;
+  %e = extractelement <3 x i64> %x, i64 2
+  call void @use(i64 %e)
+  %t = trunc i64 %e to i16
+  ret i16 %t
+}
+
+; Check to ensure PR45314 remains fixed.
+define <4 x i64> @PR45314(<4 x i64> %x) {
+; LE-LABEL: @PR45314(
+; LE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32>
+; LE-NEXT:    [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> zeroinitializer
+; LE-NEXT:    [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64>
+; LE-NEXT:    ret <4 x i64> [[B]]
+;
+; BE-LABEL: @PR45314(
+; BE-NEXT:    [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32>
+; BE-NEXT:    [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+; BE-NEXT:    [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64>
+; BE-NEXT:    ret <4 x i64> [[B]]
+;
+  %e = extractelement <4 x i64> %x, i32 0
+  %t = trunc i64 %e to i32
+  %i = insertelement <8 x i32> poison, i32 %t, i32 0
+  %s = shufflevector <8 x i32> %i, <8 x i32> undef, <8 x i32> zeroinitializer
+  %b = bitcast <8 x i32> %s to <4 x i64>
+  ret <4 x i64> %b
+}
diff --git a/llvm/test/Transforms/InstCombine/trunc.ll b/llvm/test/Transforms/InstCombine/trunc.ll
index fc13d86bcfc39..a7cd57afc1b5a 100644
--- a/llvm/test/Transforms/InstCombine/trunc.ll
+++ b/llvm/test/Transforms/InstCombine/trunc.ll
@@ -908,7 +908,7 @@ define <8 x i16> @trunc_shl_v8i16_v8i32_4(<8 x i32> %a) {
 
 define <4 x i8> @wide_shuf(<4 x i32> %x) {
 ; CHECK-LABEL: @wide_shuf(
-; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> <i32 undef, i32 3634, i32 90, i32 undef>, <4 x i32> <i32 1, i32 5, i32 6, i32 2>
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> <i32 poison, i32 3634, i32 90, i32 poison>, <4 x i32> <i32 1, i32 5, i32 6, i32 2>
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <4 x i32> [[SHUF]] to <4 x i8>
 ; CHECK-NEXT:    ret <4 x i8> [[TRUNC]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/udiv-pow2-vscale-inseltpoison.ll b/llvm/test/Transforms/InstCombine/udiv-pow2-vscale-inseltpoison.ll
new file mode 100644
index 0000000000000..a01c53305f5eb
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/udiv-pow2-vscale-inseltpoison.ll
@@ -0,0 +1,27 @@
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+; This vscale udiv with a power-of-2 spalt on the rhs should not crash opt
+
+; CHECK: define <vscale x 2 x i32> @udiv_pow2_vscale(<vscale x 2 x i32> %lhs)
+define <vscale x 2 x i32> @udiv_pow2_vscale(<vscale x 2 x i32> %lhs) {
+  %splatter = insertelement <vscale x 2 x i32> poison, i32 2, i32 0
+  %rhs = shufflevector <vscale x 2 x i32> %splatter,
+                       <vscale x 2 x i32> undef,
+                       <vscale x 2 x i32> zeroinitializer
+  %res = udiv <vscale x 2 x i32> %lhs, %rhs
+  ret <vscale x 2 x i32> %res
+}
+
+; This fixed width udiv with a power-of-2 splat on the rhs should also not
+; crash, and instcombine should eliminate the udiv
+
+; CHECK-LABEL: define <2 x i32> @udiv_pow2_fixed(<2 x i32> %lhs)
+; CHECK-NOT: udiv
+define <2 x i32> @udiv_pow2_fixed(<2 x i32> %lhs) {
+  %splatter = insertelement <2 x i32> poison, i32 2, i32 0
+  %rhs = shufflevector <2 x i32> %splatter,
+                       <2 x i32> undef,
+                       <2 x i32> zeroinitializer
+  %res = udiv <2 x i32> %lhs, %rhs
+  ret <2 x i32> %res
+}
diff --git a/llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-scalar.ll b/llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-scalar.ll
index b3bc74d3cfe08..b78b497135e8e 100644
--- a/llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-scalar.ll
+++ b/llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-scalar.ll
@@ -60,10 +60,8 @@ define i4 @in_constant_varx_14(i4 %x, i4 %mask) {
 
 define i4 @in_constant_mone_vary(i4 %y, i4 %mask) {
 ; CHECK-LABEL: @in_constant_mone_vary(
-; CHECK-NEXT:    [[N0:%.*]] = and i4 [[Y:%.*]], 1
-; CHECK-NEXT:    [[N1:%.*]] = xor i4 [[N0]], 1
-; CHECK-NEXT:    [[R:%.*]] = xor i4 [[N1]], [[Y]]
-; CHECK-NEXT:    ret i4 [[R]]
+; CHECK-NEXT:    [[R1:%.*]] = or i4 [[Y:%.*]], 1
+; CHECK-NEXT:    ret i4 [[R1]]
 ;
   %n0 = xor i4 %y, -1 ; %x
   %n1 = and i4 %n0, 1
diff --git a/llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-vector.ll b/llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-vector.ll
index 4f92514afc87c..ef27891c1a809 100644
--- a/llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-vector.ll
+++ b/llvm/test/Transforms/InstCombine/unfold-masked-merge-with-const-mask-vector.ll
@@ -97,10 +97,8 @@ define <3 x i4> @in_constant_varx_14_undef(<3 x i4> %x, <3 x i4> %mask) {
 
 define <2 x i4> @in_constant_mone_vary(<2 x i4> %y, <2 x i4> %mask) {
 ; CHECK-LABEL: @in_constant_mone_vary(
-; CHECK-NEXT:    [[N0:%.*]] = and <2 x i4> [[Y:%.*]], <i4 1, i4 1>
-; CHECK-NEXT:    [[N1:%.*]] = xor <2 x i4> [[N0]], <i4 1, i4 1>
-; CHECK-NEXT:    [[R:%.*]] = xor <2 x i4> [[N1]], [[Y]]
-; CHECK-NEXT:    ret <2 x i4> [[R]]
+; CHECK-NEXT:    [[R1:%.*]] = or <2 x i4> [[Y:%.*]], <i4 1, i4 1>
+; CHECK-NEXT:    ret <2 x i4> [[R1]]
 ;
   %n0 = xor <2 x i4> %y, <i4 -1, i4 -1> ; %x
   %n1 = and <2 x i4> %n0, <i4 1, i4 1>
diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
new file mode 100644
index 0000000000000..080324ead116b
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
@@ -0,0 +1,850 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define i32 @test2(float %f) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    [[T5:%.*]] = fmul float [[F:%.*]], [[F]]
+; CHECK-NEXT:    [[T21:%.*]] = bitcast float [[T5]] to i32
+; CHECK-NEXT:    ret i32 [[T21]]
+;
+  %t5 = fmul float %f, %f
+  %t9 = insertelement <4 x float> poison, float %t5, i32 0
+  %t10 = insertelement <4 x float> %t9, float 0.000000e+00, i32 1
+  %t11 = insertelement <4 x float> %t10, float 0.000000e+00, i32 2
+  %t12 = insertelement <4 x float> %t11, float 0.000000e+00, i32 3
+  %t19 = bitcast <4 x float> %t12 to <4 x i32>
+  %t21 = extractelement <4 x i32> %t19, i32 0
+  ret i32 %t21
+}
+
+define void @get_image() nounwind {
+; CHECK-LABEL: @get_image(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @fgetc(i8* null) [[ATTR0:#.*]]
+; CHECK-NEXT:    br i1 false, label [[BB2:%.*]], label [[BB3:%.*]]
+; CHECK:       bb2:
+; CHECK-NEXT:    br label [[BB3]]
+; CHECK:       bb3:
+; CHECK-NEXT:    unreachable
+;
+entry:
+  %0 = call i32 @fgetc(i8* null) nounwind
+  %1 = trunc i32 %0 to i8
+  %t2 = insertelement <100 x i8> zeroinitializer, i8 %1, i32 1
+  %t1 = extractelement <100 x i8> %t2, i32 0
+  %2 = icmp eq i8 %t1, 80
+  br i1 %2, label %bb2, label %bb3
+
+bb2:            ; preds = %entry
+  br label %bb3
+
+bb3:            ; preds = %bb2, %entry
+  unreachable
+}
+
+; PR4340
+define void @vac(<4 x float>* nocapture %a) nounwind {
+; CHECK-LABEL: @vac(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    store <4 x float> zeroinitializer, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    ret void
+;
+entry:
+  %t1 = load <4 x float>, <4 x float>* %a		; <<4 x float>> [#uses=1]
+  %vecins = insertelement <4 x float> %t1, float 0.000000e+00, i32 0	; <<4 x float>> [#uses=1]
+  %vecins4 = insertelement <4 x float> %vecins, float 0.000000e+00, i32 1; <<4 x float>> [#uses=1]
+  %vecins6 = insertelement <4 x float> %vecins4, float 0.000000e+00, i32 2; <<4 x float>> [#uses=1]
+  %vecins8 = insertelement <4 x float> %vecins6, float 0.000000e+00, i32 3; <<4 x float>> [#uses=1]
+  store <4 x float> %vecins8, <4 x float>* %a
+  ret void
+}
+
+declare i32 @fgetc(i8*)
+
+define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind {
+; CHECK-LABEL: @dead_shuffle_elt(
+; CHECK-NEXT:    [[SHUFFLE_I:%.*]] = shufflevector <2 x float> [[Y:%.*]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[SHUFFLE9_I:%.*]] = shufflevector <4 x float> [[SHUFFLE_I]], <4 x float> [[X:%.*]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT:    ret <4 x float> [[SHUFFLE9_I]]
+;
+  %shuffle.i = shufflevector <2 x float> %y, <2 x float> %y, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %shuffle9.i = shufflevector <4 x float> %x, <4 x float> %shuffle.i, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+  ret <4 x float> %shuffle9.i
+}
+
+define <2 x float> @test_fptrunc(double %f) {
+; CHECK-LABEL: @test_fptrunc(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[F:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float>
+; CHECK-NEXT:    ret <2 x float> [[TMP2]]
+;
+  %t9 = insertelement <4 x double> poison, double %f, i32 0
+  %t10 = insertelement <4 x double> %t9, double 0.000000e+00, i32 1
+  %t11 = insertelement <4 x double> %t10, double 0.000000e+00, i32 2
+  %t12 = insertelement <4 x double> %t11, double 0.000000e+00, i32 3
+  %t5 = fptrunc <4 x double> %t12 to <4 x float>
+  %ret = shufflevector <4 x float> %t5, <4 x float> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x float> %ret
+}
+
+define <2 x double> @test_fpext(float %f) {
+; CHECK-LABEL: @test_fpext(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double>
+; CHECK-NEXT:    ret <2 x double> [[TMP2]]
+;
+  %t9 = insertelement <4 x float> poison, float %f, i32 0
+  %t10 = insertelement <4 x float> %t9, float 0.000000e+00, i32 1
+  %t11 = insertelement <4 x float> %t10, float 0.000000e+00, i32 2
+  %t12 = insertelement <4 x float> %t11, float 0.000000e+00, i32 3
+  %t5 = fpext <4 x float> %t12 to <4 x double>
+  %ret = shufflevector <4 x double> %t5, <4 x double> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x double> %ret
+}
+
+define <4 x double> @test_shuffle(<4 x double> %f) {
+; CHECK-LABEL: @test_shuffle(
+; CHECK-NEXT:    [[RET1:%.*]] = insertelement <4 x double> [[F:%.*]], double 1.000000e+00, i32 3
+; CHECK-NEXT:    ret <4 x double> [[RET1]]
+;
+  %ret = shufflevector <4 x double> %f, <4 x double> <double undef, double 1.0, double undef, double undef>, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
+  ret <4 x double> %ret
+}
+
+define <4 x float> @test_select(float %f, float %g) {
+; CHECK-LABEL: @test_select(
+; CHECK-NEXT:    [[A3:%.*]] = insertelement <4 x float> <float poison, float poison, float poison, float 3.000000e+00>, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[RET:%.*]] = shufflevector <4 x float> [[A3]], <4 x float> <float poison, float 4.000000e+00, float 5.000000e+00, float poison>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT:    ret <4 x float> [[RET]]
+;
+  %a0 = insertelement <4 x float> poison, float %f, i32 0
+  %a1 = insertelement <4 x float> %a0, float 1.000000e+00, i32 1
+  %a2 = insertelement <4 x float> %a1, float 2.000000e+00, i32 2
+  %a3 = insertelement <4 x float> %a2, float 3.000000e+00, i32 3
+  %b0 = insertelement <4 x float> poison, float %g, i32 0
+  %b1 = insertelement <4 x float> %b0, float 4.000000e+00, i32 1
+  %b2 = insertelement <4 x float> %b1, float 5.000000e+00, i32 2
+  %b3 = insertelement <4 x float> %b2, float 6.000000e+00, i32 3
+  %ret = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x float> %a3, <4 x float> %b3
+  ret <4 x float> %ret
+}
+
+; Check that instcombine doesn't wrongly fold away the select completely.
+
+define <2 x i64> @PR24922(<2 x i64> %v) {
+; CHECK-LABEL: @PR24922(
+; CHECK-NEXT:    [[RESULT1:%.*]] = insertelement <2 x i64> [[V:%.*]], i64 0, i32 0
+; CHECK-NEXT:    ret <2 x i64> [[RESULT1]]
+;
+  %result = select <2 x i1> <i1 icmp eq (i64 extractelement (<2 x i64> bitcast (<4 x i32> <i32 15, i32 15, i32 15, i32 15> to <2 x i64>), i64 0), i64 0), i1 true>, <2 x i64> %v, <2 x i64> zeroinitializer
+  ret <2 x i64> %result
+}
+
+; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away.
+
+define <4 x float> @inselt_shuf_no_demand(float %a1, float %a2, float %a3) {
+; CHECK-LABEL: @inselt_shuf_no_demand(
+; CHECK-NEXT:    ret <4 x float> undef
+;
+  %out1 = insertelement <4 x float> poison, float %a1, i32 1
+  %out12 = insertelement <4 x float> %out1, float %a2, i32 2
+  %out123 = insertelement <4 x float> %out12, float %a3, i32 3
+  %shuffle = shufflevector <4 x float> %out123, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+  ret <4 x float> %shuffle
+}
+
+; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away.
+
+define <4 x float> @inselt_shuf_no_demand_commute(float %a1, float %a2, float %a3) {
+; CHECK-LABEL: @inselt_shuf_no_demand_commute(
+; CHECK-NEXT:    ret <4 x float> undef
+;
+  %out1 = insertelement <4 x float> poison, float %a1, i32 1
+  %out12 = insertelement <4 x float> %out1, float %a2, i32 2
+  %out123 = insertelement <4 x float> %out12, float %a3, i32 3
+  %shuffle = shufflevector <4 x float> undef, <4 x float> %out123, <4 x i32> <i32 4, i32 undef, i32 undef, i32 undef>
+  ret <4 x float> %shuffle
+}
+
+; The add uses 'out012' giving it multiple uses after the shuffle is transformed to also
+; use 'out012'. The analysis should be able to see past that.
+
+define <4 x i32> @inselt_shuf_no_demand_multiuse(i32 %a0, i32 %a1, <4 x i32> %b) {
+; CHECK-LABEL: @inselt_shuf_no_demand_multiuse(
+; CHECK-NEXT:    [[OUT0:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i32 0
+; CHECK-NEXT:    [[OUT01:%.*]] = insertelement <4 x i32> [[OUT0]], i32 [[A1:%.*]], i32 1
+; CHECK-NEXT:    [[FOO:%.*]] = add <4 x i32> [[OUT01]], [[B:%.*]]
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[FOO]], <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x i32> [[SHUFFLE]]
+;
+  %out0 = insertelement <4 x i32> poison, i32 %a0, i32 0
+  %out01 = insertelement <4 x i32> %out0, i32 %a1, i32 1
+  %out012 = insertelement <4 x i32> %out01, i32 %a0, i32 2
+  %foo = add <4 x i32> %out012, %b
+  %out0123 = insertelement <4 x i32> %foo, i32 %a1, i32 3
+  %shuffle = shufflevector <4 x i32> %out0123, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  ret <4 x i32> %shuffle
+}
+
+define <4 x float> @inselt_shuf_no_demand_bogus_insert_index_in_chain(float %a1, float %a2, float %a3, i32 %variable_index) {
+; CHECK-LABEL: @inselt_shuf_no_demand_bogus_insert_index_in_chain(
+; CHECK-NEXT:    [[OUT12:%.*]] = insertelement <4 x float> poison, float [[A2:%.*]], i32 [[VARIABLE_INDEX:%.*]]
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x float> [[OUT12]], <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[SHUFFLE]]
+;
+  %out1 = insertelement <4 x float> poison, float %a1, i32 1
+  %out12 = insertelement <4 x float> %out1, float %a2, i32 %variable_index ; something unexpected
+  %out123 = insertelement <4 x float> %out12, float %a3, i32 3
+  %shuffle = shufflevector <4 x float> %out123, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+  ret <4 x float> %shuffle
+}
+
+; Test undef replacement in constant vector elements with binops.
+
+define <3 x i8> @shuf_add(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_add(
+; CHECK-NEXT:    [[BO:%.*]] = add <3 x i8> [[X:%.*]], <i8 poison, i8 2, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 2>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = add nsw <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 2>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_sub(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_sub(
+; CHECK-NEXT:    [[BO:%.*]] = sub <3 x i8> <i8 1, i8 poison, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 2>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = sub nuw <3 x i8> <i8 1, i8 2, i8 3>, %x
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 2>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_mul(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_mul(
+; CHECK-NEXT:    [[BO:%.*]] = mul <3 x i8> [[X:%.*]], <i8 1, i8 poison, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 2, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = mul nsw <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 2, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_and(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_and(
+; CHECK-NEXT:    [[BO:%.*]] = and <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = and <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_or(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_or(
+; CHECK-NEXT:    [[BO:%.*]] = or <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = or <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_xor(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_xor(
+; CHECK-NEXT:    [[BO:%.*]] = xor <3 x i8> [[X:%.*]], <i8 1, i8 poison, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = xor <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_lshr_const_op0(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_lshr_const_op0(
+; CHECK-NEXT:    [[BO:%.*]] = lshr <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = lshr <3 x i8> <i8 1, i8 2, i8 3>, %x
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_lshr_const_op1(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_lshr_const_op1(
+; CHECK-NEXT:    [[BO:%.*]] = lshr exact <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = lshr exact <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_ashr_const_op0(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_ashr_const_op0(
+; CHECK-NEXT:    [[BO:%.*]] = lshr <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = ashr <3 x i8> <i8 1, i8 2, i8 3>, %x
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_ashr_const_op1(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_ashr_const_op1(
+; CHECK-NEXT:    [[BO:%.*]] = ashr exact <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = ashr exact <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_shl_const_op0(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_shl_const_op0(
+; CHECK-NEXT:    [[BO:%.*]] = shl nsw <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = shl nsw <3 x i8> <i8 1, i8 2, i8 3>, %x
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_shl_const_op1(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_shl_const_op1(
+; CHECK-NEXT:    [[BO:%.*]] = shl nuw <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = shl nuw <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_sdiv_const_op0(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_sdiv_const_op0(
+; CHECK-NEXT:    [[BO:%.*]] = sdiv exact <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = sdiv exact <3 x i8> <i8 1, i8 2, i8 3>, %x
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_sdiv_const_op1(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_sdiv_const_op1(
+; CHECK-NEXT:    [[BO:%.*]] = sdiv <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = sdiv <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_srem_const_op0(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_srem_const_op0(
+; CHECK-NEXT:    [[BO:%.*]] = srem <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 2>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = srem <3 x i8> <i8 1, i8 2, i8 3>, %x
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 2>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_srem_const_op1(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_srem_const_op1(
+; CHECK-NEXT:    [[BO:%.*]] = srem <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 1>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = srem <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 1>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_udiv_const_op0(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_udiv_const_op0(
+; CHECK-NEXT:    [[BO:%.*]] = udiv exact <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = udiv exact <3 x i8> <i8 1, i8 2, i8 3>, %x
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_udiv_const_op1(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_udiv_const_op1(
+; CHECK-NEXT:    [[BO:%.*]] = udiv <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = udiv <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_urem_const_op0(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_urem_const_op0(
+; CHECK-NEXT:    [[BO:%.*]] = urem <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = urem <3 x i8> <i8 1, i8 2, i8 3>, %x
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef>
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @shuf_urem_const_op1(<3 x i8> %x) {
+; CHECK-LABEL: @shuf_urem_const_op1(
+; CHECK-NEXT:    [[BO:%.*]] = urem <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 undef, i32 1, i32 0>
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %bo = urem <3 x i8> %x, <i8 1, i8 2, i8 3>
+  %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 undef, i32 1, i32 0>
+  ret <3 x i8> %r
+}
+
+define <3 x float> @shuf_fadd(<3 x float> %x) {
+; CHECK-LABEL: @shuf_fadd(
+; CHECK-NEXT:    [[BO:%.*]] = fadd <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
+; CHECK-NEXT:    ret <3 x float> [[R]]
+;
+  %bo = fadd <3 x float> %x, <float 1.0, float 2.0, float 3.0>
+  %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
+  ret <3 x float> %r
+}
+
+define <3 x float> @shuf_fsub(<3 x float> %x) {
+; CHECK-LABEL: @shuf_fsub(
+; CHECK-NEXT:    [[BO:%.*]] = fsub fast <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2>
+; CHECK-NEXT:    ret <3 x float> [[R]]
+;
+  %bo = fsub fast <3 x float> <float 1.0, float 2.0, float 3.0>, %x
+  %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2>
+  ret <3 x float> %r
+}
+
+define <3 x float> @shuf_fmul(<3 x float> %x) {
+; CHECK-LABEL: @shuf_fmul(
+; CHECK-NEXT:    [[BO:%.*]] = fmul reassoc <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
+; CHECK-NEXT:    ret <3 x float> [[R]]
+;
+  %bo = fmul reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0>
+  %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
+  ret <3 x float> %r
+}
+
+define <3 x float> @shuf_fdiv_const_op0(<3 x float> %x) {
+; CHECK-LABEL: @shuf_fdiv_const_op0(
+; CHECK-NEXT:    [[BO:%.*]] = fdiv reassoc ninf <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2>
+; CHECK-NEXT:    ret <3 x float> [[R]]
+;
+  %bo = fdiv ninf reassoc <3 x float> <float 1.0, float 2.0, float 3.0>, %x
+  %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2>
+  ret <3 x float> %r
+}
+
+define <3 x float> @shuf_fdiv_const_op1(<3 x float> %x) {
+; CHECK-LABEL: @shuf_fdiv_const_op1(
+; CHECK-NEXT:    [[BO:%.*]] = fdiv nnan ninf <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
+; CHECK-NEXT:    ret <3 x float> [[R]]
+;
+  %bo = fdiv ninf nnan <3 x float> %x, <float 1.0, float 2.0, float 3.0>
+  %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
+  ret <3 x float> %r
+}
+
+define <3 x float> @shuf_frem_const_op0(<3 x float> %x) {
+; CHECK-LABEL: @shuf_frem_const_op0(
+; CHECK-NEXT:    [[BO:%.*]] = frem nnan <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 2, i32 0>
+; CHECK-NEXT:    ret <3 x float> [[R]]
+;
+  %bo = frem nnan <3 x float> <float 1.0, float 2.0, float 3.0>, %x
+  %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 2, i32 0>
+  ret <3 x float> %r
+}
+
+define <3 x float> @shuf_frem_const_op1(<3 x float> %x) {
+; CHECK-LABEL: @shuf_frem_const_op1(
+; CHECK-NEXT:    [[BO:%.*]] = frem reassoc ninf <3 x float> [[X:%.*]], <float poison, float 2.000000e+00, float 3.000000e+00>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 1, i32 undef, i32 2>
+; CHECK-NEXT:    ret <3 x float> [[R]]
+;
+  %bo = frem ninf reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0>
+  %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 1, i32 undef, i32 2>
+  ret <3 x float> %r
+}
+
+;; TODO: getelementptr tests below show missing simplifications for
+;; vector demanded elements on vector geps.
+
+define i32* @gep_vbase_w_s_idx(<2 x i32*> %base) {
+; CHECK-LABEL: @gep_vbase_w_s_idx(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> [[BASE:%.*]], i64 1
+; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
+; CHECK-NEXT:    ret i32* [[EE]]
+;
+  %gep = getelementptr i32, <2 x i32*> %base, i64 1
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+
+define i32* @gep_splat_base_w_s_idx(i32* %base) {
+; CHECK-LABEL: @gep_splat_base_w_s_idx(
+; CHECK-NEXT:    [[BASEVEC2:%.*]] = insertelement <2 x i32*> undef, i32* [[BASE:%.*]], i32 1
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> [[BASEVEC2]], i64 1
+; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
+; CHECK-NEXT:    ret i32* [[EE]]
+;
+  %basevec1 = insertelement <2 x i32*> poison, i32* %base, i32 0
+  %basevec2 = shufflevector <2 x i32*> %basevec1, <2 x i32*> undef, <2 x i32> zeroinitializer
+  %gep = getelementptr i32, <2 x i32*> %basevec2, i64 1
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+
+
+define i32* @gep_splat_base_w_cv_idx(i32* %base) {
+; CHECK-LABEL: @gep_splat_base_w_cv_idx(
+; CHECK-NEXT:    [[BASEVEC2:%.*]] = insertelement <2 x i32*> undef, i32* [[BASE:%.*]], i32 1
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> [[BASEVEC2]], <2 x i64> <i64 poison, i64 1>
+; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
+; CHECK-NEXT:    ret i32* [[EE]]
+;
+  %basevec1 = insertelement <2 x i32*> poison, i32* %base, i32 0
+  %basevec2 = shufflevector <2 x i32*> %basevec1, <2 x i32*> undef, <2 x i32> zeroinitializer
+  %gep = getelementptr i32, <2 x i32*> %basevec2, <2 x i64> <i64 0, i64 1>
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+
+define i32* @gep_splat_base_w_vidx(i32* %base, <2 x i64> %idxvec) {
+; CHECK-LABEL: @gep_splat_base_w_vidx(
+; CHECK-NEXT:    [[BASEVEC2:%.*]] = insertelement <2 x i32*> undef, i32* [[BASE:%.*]], i32 1
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> [[BASEVEC2]], <2 x i64> [[IDXVEC:%.*]]
+; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
+; CHECK-NEXT:    ret i32* [[EE]]
+;
+  %basevec1 = insertelement <2 x i32*> poison, i32* %base, i32 0
+  %basevec2 = shufflevector <2 x i32*> %basevec1, <2 x i32*> undef, <2 x i32> zeroinitializer
+  %gep = getelementptr i32, <2 x i32*> %basevec2, <2 x i64> %idxvec
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+
+
+@GLOBAL = internal global i32 zeroinitializer
+
+define i32* @gep_cvbase_w_s_idx(<2 x i32*> %base, i64 %raw_addr) {
+; CHECK-LABEL: @gep_cvbase_w_s_idx(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> <i32* poison, i32* @GLOBAL>, i64 [[RAW_ADDR:%.*]]
+; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
+; CHECK-NEXT:    ret i32* [[EE]]
+;
+  %gep = getelementptr i32, <2 x i32*> <i32* @GLOBAL, i32* @GLOBAL>, i64 %raw_addr
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+
+define i32* @gep_cvbase_w_cv_idx(<2 x i32*> %base, i64 %raw_addr) {
+; CHECK-LABEL: @gep_cvbase_w_cv_idx(
+; CHECK-NEXT:    ret i32* getelementptr inbounds (i32, i32* @GLOBAL, i64 1)
+;
+  %gep = getelementptr i32, <2 x i32*> <i32* @GLOBAL, i32* @GLOBAL>, <2 x i64> <i64 0, i64 1>
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+
+
+define i32* @gep_sbase_w_cv_idx(i32* %base) {
+; CHECK-LABEL: @gep_sbase_w_cv_idx(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, i32* [[BASE:%.*]], <2 x i64> <i64 poison, i64 1>
+; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
+; CHECK-NEXT:    ret i32* [[EE]]
+;
+  %gep = getelementptr i32, i32* %base, <2 x i64> <i64 0, i64 1>
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+
+define i32* @gep_sbase_w_splat_idx(i32* %base, i64 %idx) {
+; CHECK-LABEL: @gep_sbase_w_splat_idx(
+; CHECK-NEXT:    [[IDXVEC2:%.*]] = insertelement <2 x i64> undef, i64 [[IDX:%.*]], i32 1
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, i32* [[BASE:%.*]], <2 x i64> [[IDXVEC2]]
+; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
+; CHECK-NEXT:    ret i32* [[EE]]
+;
+  %idxvec1 = insertelement <2 x i64> poison, i64 %idx, i32 0
+  %idxvec2 = shufflevector <2 x i64> %idxvec1, <2 x i64> undef, <2 x i32> zeroinitializer
+  %gep = getelementptr i32, i32* %base, <2 x i64> %idxvec2
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+define i32* @gep_splat_both(i32* %base, i64 %idx) {
+; CHECK-LABEL: @gep_splat_both(
+; CHECK-NEXT:    [[BASEVEC2:%.*]] = insertelement <2 x i32*> undef, i32* [[BASE:%.*]], i32 1
+; CHECK-NEXT:    [[IDXVEC2:%.*]] = insertelement <2 x i64> undef, i64 [[IDX:%.*]], i32 1
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> [[BASEVEC2]], <2 x i64> [[IDXVEC2]]
+; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
+; CHECK-NEXT:    ret i32* [[EE]]
+;
+  %basevec1 = insertelement <2 x i32*> poison, i32* %base, i32 0
+  %basevec2 = shufflevector <2 x i32*> %basevec1, <2 x i32*> undef, <2 x i32> zeroinitializer
+  %idxvec1 = insertelement <2 x i64> poison, i64 %idx, i32 0
+  %idxvec2 = shufflevector <2 x i64> %idxvec1, <2 x i64> undef, <2 x i32> zeroinitializer
+  %gep = getelementptr i32, <2 x i32*> %basevec2, <2 x i64> %idxvec2
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+
+define <2 x i32*> @gep_all_lanes_undef(i32* %base, i64 %idx) {;
+; CHECK-LABEL: @gep_all_lanes_undef(
+; CHECK-NEXT:    ret <2 x i32*> undef
+;
+  %basevec = insertelement <2 x i32*> poison, i32* %base, i32 0
+  %idxvec = insertelement <2 x i64> poison, i64 %idx, i32 1
+  %gep = getelementptr i32, <2 x i32*> %basevec, <2 x i64> %idxvec
+  ret <2 x i32*> %gep
+}
+
+define i32* @gep_demanded_lane_undef(i32* %base, i64 %idx) {
+; CHECK-LABEL: @gep_demanded_lane_undef(
+; CHECK-NEXT:    ret i32* undef
+;
+  %basevec = insertelement <2 x i32*> poison, i32* %base, i32 0
+  %idxvec = insertelement <2 x i64> poison, i64 %idx, i32 1
+  %gep = getelementptr i32, <2 x i32*> %basevec, <2 x i64> %idxvec
+  %ee = extractelement <2 x i32*> %gep, i32 1
+  ret i32* %ee
+}
+
+
+;; LangRef has an odd quirk around FCAs which make it illegal to use undef
+;; indices.
+define i32* @PR41624(<2 x { i32, i32 }*> %a) {
+; CHECK-LABEL: @PR41624(
+; CHECK-NEXT:    [[W:%.*]] = getelementptr { i32, i32 }, <2 x { i32, i32 }*> [[A:%.*]], <2 x i64> <i64 5, i64 5>, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = extractelement <2 x i32*> [[W]], i32 0
+; CHECK-NEXT:    ret i32* [[R]]
+;
+  %w = getelementptr { i32, i32 }, <2 x { i32, i32 }*> %a, <2 x i64> <i64 5, i64 5>, <2 x i32> zeroinitializer
+  %r = extractelement <2 x i32*> %w, i32 0
+  ret i32* %r
+}
+
+@global = external global [0 x i32], align 4
+
+; Make sure we don't get stuck in a loop turning the zeroinitializer into
+; <0, undef, undef, undef> and then changing it back.
+define i32* @zero_sized_type_extract(<4 x i64> %arg, i64 %arg1) {
+; CHECK-LABEL: @zero_sized_type_extract(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[T:%.*]] = getelementptr inbounds [0 x i32], <4 x [0 x i32]*> <[0 x i32]* @global, [0 x i32]* poison, [0 x i32]* poison, [0 x i32]* poison>, <4 x i64> <i64 0, i64 poison, i64 poison, i64 poison>, <4 x i64> [[ARG:%.*]]
+; CHECK-NEXT:    [[T2:%.*]] = extractelement <4 x i32*> [[T]], i64 0
+; CHECK-NEXT:    ret i32* [[T2]]
+;
+bb:
+  %t = getelementptr inbounds [0 x i32], <4 x [0 x i32]*> <[0 x i32]* @global, [0 x i32]* @global, [0 x i32]* @global, [0 x i32]* @global>, <4 x i64> zeroinitializer, <4 x i64> %arg
+  %t2 = extractelement <4 x i32*> %t, i64 0
+  ret i32* %t2
+}
+
+; The non-zero elements of the result are always 'y', so the splat is unnecessary.
+
+define <4 x i8> @select_cond_with_eq_true_false_elts(<4 x i8> %x, <4 x i8> %y, <4 x i1> %cmp) {
+; CHECK-LABEL: @select_cond_with_eq_true_false_elts(
+; CHECK-NEXT:    [[SEL:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i8> [[SEL]], <4 x i8> [[Y]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    ret <4 x i8> [[R]]
+;
+  %tval = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  %splat = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> zeroinitializer
+  %r = select <4 x i1> %splat, <4 x i8> %tval, <4 x i8> %y
+  ret <4 x i8> %r
+}
+
+; First element of the result is always x[0], so first element of select condition is unnecessary.
+
+define <4 x i8> @select_cond_with_eq_true_false_elts2(<4 x i8> %x, <4 x i8> %y, <4 x i1> %cmp) {
+; CHECK-LABEL: @select_cond_with_eq_true_false_elts2(
+; CHECK-NEXT:    [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> undef, <4 x i32> <i32 undef, i32 1, i32 0, i32 1>
+; CHECK-NEXT:    [[SEL:%.*]] = select <4 x i1> [[COND]], <4 x i8> [[Y:%.*]], <4 x i8> [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[SEL]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    ret <4 x i8> [[R]]
+;
+  %tval = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  %cond = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %r = select <4 x i1> %cond, <4 x i8> %tval, <4 x i8> %x
+  ret <4 x i8> %r
+}
+
+; Second element of the result is always x[3], so second element of select condition is unnecessary.
+; Fourth element of the result is always undef, so fourth element of select condition is unnecessary.
+
+define <4 x float> @select_cond_with_eq_true_false_elts3(<4 x float> %x, <4 x float> %y, <4 x i1> %cmp) {
+; CHECK-LABEL: @select_cond_with_eq_true_false_elts3(
+; CHECK-NEXT:    [[TVAL:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x i32> <i32 1, i32 3, i32 5, i32 undef>
+; CHECK-NEXT:    [[FVAL:%.*]] = shufflevector <4 x float> [[Y]], <4 x float> [[X]], <4 x i32> <i32 0, i32 7, i32 6, i32 undef>
+; CHECK-NEXT:    [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> undef, <4 x i32> <i32 undef, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[R:%.*]] = select <4 x i1> [[COND]], <4 x float> [[TVAL]], <4 x float> [[FVAL]]
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %tval = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 undef>
+  %fval = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 7, i32 6, i32 undef>
+  %cond = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> <i32 undef, i32 1, i32 2, i32 3>
+  %r = select <4 x i1> %cond, <4 x float> %tval, <4 x float> %fval
+  ret <4 x float> %r
+}
+
+define <4 x i8> @select_cond_with_undef_true_false_elts(<4 x i8> %x, <4 x i8> %y, <4 x i1> %cmp) {
+; CHECK-LABEL: @select_cond_with_undef_true_false_elts(
+; CHECK-NEXT:    [[TVAL:%.*]] = shufflevector <4 x i8> [[Y:%.*]], <4 x i8> poison, <4 x i32> <i32 undef, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+; CHECK-NEXT:    [[R:%.*]] = select <4 x i1> [[COND]], <4 x i8> [[TVAL]], <4 x i8> [[X:%.*]]
+; CHECK-NEXT:    ret <4 x i8> [[R]]
+;
+  %tval = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> <i32 undef, i32 5, i32 6, i32 7>
+  %cond = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  %r = select <4 x i1> %cond, <4 x i8> %tval, <4 x i8> %x
+  ret <4 x i8> %r
+}
+
+; The insert can be safely eliminated because the shuffle blocks poison from cmp[0].
+
+define <4 x i8> @select_cond_(<4 x i8> %x, <4 x i8> %min, <4 x i1> %cmp, i1 %poison_blocker) {
+; CHECK-LABEL: @select_cond_(
+; CHECK-NEXT:    [[SEL:%.*]] = select <4 x i1> [[CMP:%.*]], <4 x i8> [[MIN:%.*]], <4 x i8> [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[SEL]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    ret <4 x i8> [[R]]
+;
+  %ins = insertelement <4 x i1> %cmp, i1 %poison_blocker, i32 0
+  %vecins = shufflevector <4 x i8> %x, <4 x i8> %min, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
+  %r = select <4 x i1> %ins, <4 x i8> %vecins, <4 x i8> %x
+  ret <4 x i8> %r
+}
+
+define <4 x float> @ins_of_ext(<4 x float> %x, float %y) {
+; CHECK-LABEL: @ins_of_ext(
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x float> [[X:%.*]], float [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[Y]], i32 2
+; CHECK-NEXT:    [[I3:%.*]] = insertelement <4 x float> [[I2]], float [[Y]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[I3]]
+;
+  %e0 = extractelement <4 x float> %x, i32 0
+  %i0 = insertelement <4 x float> poison, float %e0, i32 0
+  %i1 = insertelement <4 x float> %i0, float %y, i32 1
+  %i2 = insertelement <4 x float> %i1, float %y, i32 2
+  %i3 = insertelement <4 x float> %i2, float %y, i32 3
+  ret <4 x float> %i3
+}
+
+define <4 x float> @ins_of_ext_twice(<4 x float> %x, float %y) {
+; CHECK-LABEL: @ins_of_ext_twice(
+; CHECK-NEXT:    [[I2:%.*]] = insertelement <4 x float> [[X:%.*]], float [[Y:%.*]], i32 2
+; CHECK-NEXT:    [[I3:%.*]] = insertelement <4 x float> [[I2]], float [[Y]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[I3]]
+;
+  %e0 = extractelement <4 x float> %x, i32 0
+  %i0 = insertelement <4 x float> poison, float %e0, i32 0
+  %e1 = extractelement <4 x float> %x, i32 1
+  %i1 = insertelement <4 x float> %i0, float %e1, i32 1
+  %i2 = insertelement <4 x float> %i1, float %y, i32 2
+  %i3 = insertelement <4 x float> %i2, float %y, i32 3
+  ret <4 x float> %i3
+}
+
+; Negative test - element 3 of the result must be undef to be poison safe.
+; TODO: Could convert insert/extract to identity shuffle with undef mask elements.
+
+define <4 x float> @ins_of_ext_wrong_demand(<4 x float> %x, float %y) {
+; CHECK-LABEL: @ins_of_ext_wrong_demand(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <4 x float> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <4 x float> poison, float [[E0]], i32 0
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x float> [[I0]], float [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[Y]], i32 2
+; CHECK-NEXT:    ret <4 x float> [[I2]]
+;
+  %e0 = extractelement <4 x float> %x, i32 0
+  %i0 = insertelement <4 x float> poison, float %e0, i32 0
+  %i1 = insertelement <4 x float> %i0, float %y, i32 1
+  %i2 = insertelement <4 x float> %i1, float %y, i32 2
+  ret <4 x float> %i2
+}
+
+; Negative test - can't replace i0 with x.
+; TODO: Could convert insert/extract to identity shuffle with undef mask elements.
+
+define <4 x float> @ins_of_ext_wrong_type(<5 x float> %x, float %y) {
+; CHECK-LABEL: @ins_of_ext_wrong_type(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <5 x float> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <4 x float> poison, float [[E0]], i32 0
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x float> [[I0]], float [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[Y]], i32 2
+; CHECK-NEXT:    [[I3:%.*]] = insertelement <4 x float> [[I2]], float [[Y]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[I3]]
+;
+  %e0 = extractelement <5 x float> %x, i32 0
+  %i0 = insertelement <4 x float> poison, float %e0, i32 0
+  %i1 = insertelement <4 x float> %i0, float %y, i32 1
+  %i2 = insertelement <4 x float> %i1, float %y, i32 2
+  %i3 = insertelement <4 x float> %i2, float %y, i32 3
+  ret <4 x float> %i3
+}
+
+; This should reduce, but the shuffle mask must remain as-is (no extra undef).
+
+define <4 x i4> @ins_of_ext_undef_elts_propagation(<4 x i4> %v, <4 x i4> %v2, i4 %x) {
+; CHECK-LABEL: @ins_of_ext_undef_elts_propagation(
+; CHECK-NEXT:    [[T2:%.*]] = insertelement <4 x i4> [[V:%.*]], i4 [[X:%.*]], i32 2
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i4> [[T2]], <4 x i4> [[V2:%.*]], <4 x i32> <i32 0, i32 6, i32 2, i32 7>
+; CHECK-NEXT:    ret <4 x i4> [[R]]
+;
+  %v0 = extractelement <4 x i4> %v, i32 0
+  %t0 = insertelement <4 x i4> poison, i4 %v0, i32 0
+  %t2 = insertelement <4 x i4> %t0, i4 %x, i32 2
+  %r = shufflevector <4 x i4> %t2, <4 x i4> %v2, <4 x i32> <i32 0, i32 6, i32 2, i32 7>
+  ret <4 x i4> %r
+}
+
+; Similar to above, but more ops/uses to verify things work in more complicated cases.
+
+define <8 x i4> @ins_of_ext_undef_elts_propagation2(<8 x i4> %v, <8 x i4> %v2, i4 %x) {
+; CHECK-LABEL: @ins_of_ext_undef_elts_propagation2(
+; CHECK-NEXT:    [[I19:%.*]] = insertelement <8 x i4> [[V:%.*]], i4 [[X:%.*]], i32 2
+; CHECK-NEXT:    [[I20:%.*]] = shufflevector <8 x i4> [[I19]], <8 x i4> [[V2:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 11, i32 10, i32 9, i32 8, i32 undef>
+; CHECK-NEXT:    [[I21:%.*]] = shufflevector <8 x i4> [[I20]], <8 x i4> [[V]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
+; CHECK-NEXT:    ret <8 x i4> [[I21]]
+;
+  %i15 = extractelement <8 x i4> %v, i32 0
+  %i16 = insertelement <8 x i4> poison, i4 %i15, i32 0
+  %i17 = extractelement <8 x i4> %v, i32 1
+  %i18 = insertelement <8 x i4> %i16, i4 %i17, i32 1
+  %i19 = insertelement <8 x i4> %i18, i4 %x, i32 2
+  %i20 = shufflevector <8 x i4> %i19, <8 x i4> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 11, i32 10, i32 9, i32 8, i32 undef>
+  %i21 = shufflevector <8 x i4> %i20, <8 x i4> %v, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
+  ret <8 x i4> %i21
+}
diff --git a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
index 3f308485342ec..685b8eda250c5 100644
--- a/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
+++ b/llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
@@ -75,7 +75,7 @@ define <4 x float> @dead_shuffle_elt(<4 x float> %x, <2 x float> %y) nounwind {
 
 define <2 x float> @test_fptrunc(double %f) {
 ; CHECK-LABEL: @test_fptrunc(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double undef, double 0.000000e+00>, double [[F:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x double> <double poison, double 0.000000e+00>, double [[F:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = fptrunc <2 x double> [[TMP1]] to <2 x float>
 ; CHECK-NEXT:    ret <2 x float> [[TMP2]]
 ;
@@ -90,7 +90,7 @@ define <2 x float> @test_fptrunc(double %f) {
 
 define <2 x double> @test_fpext(float %f) {
 ; CHECK-LABEL: @test_fpext(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> <float undef, float 0.000000e+00>, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> <float poison, float 0.000000e+00>, float [[F:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = fpext <2 x float> [[TMP1]] to <2 x double>
 ; CHECK-NEXT:    ret <2 x double> [[TMP2]]
 ;
@@ -114,8 +114,8 @@ define <4 x double> @test_shuffle(<4 x double> %f) {
 
 define <4 x float> @test_select(float %f, float %g) {
 ; CHECK-LABEL: @test_select(
-; CHECK-NEXT:    [[A3:%.*]] = insertelement <4 x float> <float undef, float undef, float undef, float 3.000000e+00>, float [[F:%.*]], i32 0
-; CHECK-NEXT:    [[RET:%.*]] = shufflevector <4 x float> [[A3]], <4 x float> <float undef, float 4.000000e+00, float 5.000000e+00, float undef>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT:    [[A3:%.*]] = insertelement <4 x float> <float poison, float poison, float poison, float 3.000000e+00>, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[RET:%.*]] = shufflevector <4 x float> [[A3]], <4 x float> <float poison, float 4.000000e+00, float 5.000000e+00, float poison>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
 ; CHECK-NEXT:    ret <4 x float> [[RET]]
 ;
   %a0 = insertelement <4 x float> undef, float %f, i32 0
@@ -204,7 +204,7 @@ define <4 x float> @inselt_shuf_no_demand_bogus_insert_index_in_chain(float %a1,
 
 define <3 x i8> @shuf_add(<3 x i8> %x) {
 ; CHECK-LABEL: @shuf_add(
-; CHECK-NEXT:    [[BO:%.*]] = add <3 x i8> [[X:%.*]], <i8 undef, i8 2, i8 3>
+; CHECK-NEXT:    [[BO:%.*]] = add <3 x i8> [[X:%.*]], <i8 poison, i8 2, i8 3>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 2>
 ; CHECK-NEXT:    ret <3 x i8> [[R]]
 ;
@@ -215,7 +215,7 @@ define <3 x i8> @shuf_add(<3 x i8> %x) {
 
 define <3 x i8> @shuf_sub(<3 x i8> %x) {
 ; CHECK-LABEL: @shuf_sub(
-; CHECK-NEXT:    [[BO:%.*]] = sub <3 x i8> <i8 1, i8 undef, i8 3>, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = sub <3 x i8> <i8 1, i8 poison, i8 3>, [[X:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 2>
 ; CHECK-NEXT:    ret <3 x i8> [[R]]
 ;
@@ -226,7 +226,7 @@ define <3 x i8> @shuf_sub(<3 x i8> %x) {
 
 define <3 x i8> @shuf_mul(<3 x i8> %x) {
 ; CHECK-LABEL: @shuf_mul(
-; CHECK-NEXT:    [[BO:%.*]] = mul <3 x i8> [[X:%.*]], <i8 1, i8 undef, i8 3>
+; CHECK-NEXT:    [[BO:%.*]] = mul <3 x i8> [[X:%.*]], <i8 1, i8 poison, i8 3>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 2, i32 0>
 ; CHECK-NEXT:    ret <3 x i8> [[R]]
 ;
@@ -237,7 +237,7 @@ define <3 x i8> @shuf_mul(<3 x i8> %x) {
 
 define <3 x i8> @shuf_and(<3 x i8> %x) {
 ; CHECK-LABEL: @shuf_and(
-; CHECK-NEXT:    [[BO:%.*]] = and <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 undef>
+; CHECK-NEXT:    [[BO:%.*]] = and <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 0>
 ; CHECK-NEXT:    ret <3 x i8> [[R]]
 ;
@@ -248,7 +248,7 @@ define <3 x i8> @shuf_and(<3 x i8> %x) {
 
 define <3 x i8> @shuf_or(<3 x i8> %x) {
 ; CHECK-LABEL: @shuf_or(
-; CHECK-NEXT:    [[BO:%.*]] = or <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 undef>
+; CHECK-NEXT:    [[BO:%.*]] = or <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 0>
 ; CHECK-NEXT:    ret <3 x i8> [[R]]
 ;
@@ -259,7 +259,7 @@ define <3 x i8> @shuf_or(<3 x i8> %x) {
 
 define <3 x i8> @shuf_xor(<3 x i8> %x) {
 ; CHECK-LABEL: @shuf_xor(
-; CHECK-NEXT:    [[BO:%.*]] = xor <3 x i8> [[X:%.*]], <i8 1, i8 undef, i8 3>
+; CHECK-NEXT:    [[BO:%.*]] = xor <3 x i8> [[X:%.*]], <i8 1, i8 poison, i8 3>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
 ; CHECK-NEXT:    ret <3 x i8> [[R]]
 ;
@@ -424,7 +424,7 @@ define <3 x i8> @shuf_urem_const_op1(<3 x i8> %x) {
 
 define <3 x float> @shuf_fadd(<3 x float> %x) {
 ; CHECK-LABEL: @shuf_fadd(
-; CHECK-NEXT:    [[BO:%.*]] = fadd <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float undef>
+; CHECK-NEXT:    [[BO:%.*]] = fadd <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
 ; CHECK-NEXT:    ret <3 x float> [[R]]
 ;
@@ -435,7 +435,7 @@ define <3 x float> @shuf_fadd(<3 x float> %x) {
 
 define <3 x float> @shuf_fsub(<3 x float> %x) {
 ; CHECK-LABEL: @shuf_fsub(
-; CHECK-NEXT:    [[BO:%.*]] = fsub fast <3 x float> <float 1.000000e+00, float undef, float 3.000000e+00>, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = fsub fast <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2>
 ; CHECK-NEXT:    ret <3 x float> [[R]]
 ;
@@ -446,7 +446,7 @@ define <3 x float> @shuf_fsub(<3 x float> %x) {
 
 define <3 x float> @shuf_fmul(<3 x float> %x) {
 ; CHECK-LABEL: @shuf_fmul(
-; CHECK-NEXT:    [[BO:%.*]] = fmul reassoc <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float undef>
+; CHECK-NEXT:    [[BO:%.*]] = fmul reassoc <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
 ; CHECK-NEXT:    ret <3 x float> [[R]]
 ;
@@ -457,7 +457,7 @@ define <3 x float> @shuf_fmul(<3 x float> %x) {
 
 define <3 x float> @shuf_fdiv_const_op0(<3 x float> %x) {
 ; CHECK-LABEL: @shuf_fdiv_const_op0(
-; CHECK-NEXT:    [[BO:%.*]] = fdiv reassoc ninf <3 x float> <float 1.000000e+00, float undef, float 3.000000e+00>, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = fdiv reassoc ninf <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2>
 ; CHECK-NEXT:    ret <3 x float> [[R]]
 ;
@@ -468,7 +468,7 @@ define <3 x float> @shuf_fdiv_const_op0(<3 x float> %x) {
 
 define <3 x float> @shuf_fdiv_const_op1(<3 x float> %x) {
 ; CHECK-LABEL: @shuf_fdiv_const_op1(
-; CHECK-NEXT:    [[BO:%.*]] = fdiv nnan ninf <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float undef>
+; CHECK-NEXT:    [[BO:%.*]] = fdiv nnan ninf <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
 ; CHECK-NEXT:    ret <3 x float> [[R]]
 ;
@@ -479,7 +479,7 @@ define <3 x float> @shuf_fdiv_const_op1(<3 x float> %x) {
 
 define <3 x float> @shuf_frem_const_op0(<3 x float> %x) {
 ; CHECK-LABEL: @shuf_frem_const_op0(
-; CHECK-NEXT:    [[BO:%.*]] = frem nnan <3 x float> <float 1.000000e+00, float undef, float 3.000000e+00>, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = frem nnan <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 undef, i32 2, i32 0>
 ; CHECK-NEXT:    ret <3 x float> [[R]]
 ;
@@ -490,7 +490,7 @@ define <3 x float> @shuf_frem_const_op0(<3 x float> %x) {
 
 define <3 x float> @shuf_frem_const_op1(<3 x float> %x) {
 ; CHECK-LABEL: @shuf_frem_const_op1(
-; CHECK-NEXT:    [[BO:%.*]] = frem reassoc ninf <3 x float> [[X:%.*]], <float undef, float 2.000000e+00, float 3.000000e+00>
+; CHECK-NEXT:    [[BO:%.*]] = frem reassoc ninf <3 x float> [[X:%.*]], <float poison, float 2.000000e+00, float 3.000000e+00>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 1, i32 undef, i32 2>
 ; CHECK-NEXT:    ret <3 x float> [[R]]
 ;
@@ -531,7 +531,7 @@ define i32* @gep_splat_base_w_s_idx(i32* %base) {
 define i32* @gep_splat_base_w_cv_idx(i32* %base) {
 ; CHECK-LABEL: @gep_splat_base_w_cv_idx(
 ; CHECK-NEXT:    [[BASEVEC2:%.*]] = insertelement <2 x i32*> undef, i32* [[BASE:%.*]], i32 1
-; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> [[BASEVEC2]], <2 x i64> <i64 undef, i64 1>
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> [[BASEVEC2]], <2 x i64> <i64 poison, i64 1>
 ; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
 ; CHECK-NEXT:    ret i32* [[EE]]
 ;
@@ -561,7 +561,7 @@ define i32* @gep_splat_base_w_vidx(i32* %base, <2 x i64> %idxvec) {
 
 define i32* @gep_cvbase_w_s_idx(<2 x i32*> %base, i64 %raw_addr) {
 ; CHECK-LABEL: @gep_cvbase_w_s_idx(
-; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> <i32* undef, i32* @GLOBAL>, i64 [[RAW_ADDR:%.*]]
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, <2 x i32*> <i32* poison, i32* @GLOBAL>, i64 [[RAW_ADDR:%.*]]
 ; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
 ; CHECK-NEXT:    ret i32* [[EE]]
 ;
@@ -582,7 +582,7 @@ define i32* @gep_cvbase_w_cv_idx(<2 x i32*> %base, i64 %raw_addr) {
 
 define i32* @gep_sbase_w_cv_idx(i32* %base) {
 ; CHECK-LABEL: @gep_sbase_w_cv_idx(
-; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, i32* [[BASE:%.*]], <2 x i64> <i64 undef, i64 1>
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, i32* [[BASE:%.*]], <2 x i64> <i64 poison, i64 1>
 ; CHECK-NEXT:    [[EE:%.*]] = extractelement <2 x i32*> [[GEP]], i32 1
 ; CHECK-NEXT:    ret i32* [[EE]]
 ;
@@ -663,7 +663,7 @@ define i32* @PR41624(<2 x { i32, i32 }*> %a) {
 define i32* @zero_sized_type_extract(<4 x i64> %arg, i64 %arg1) {
 ; CHECK-LABEL: @zero_sized_type_extract(
 ; CHECK-NEXT:  bb:
-; CHECK-NEXT:    [[T:%.*]] = getelementptr inbounds [0 x i32], <4 x [0 x i32]*> <[0 x i32]* @global, [0 x i32]* undef, [0 x i32]* undef, [0 x i32]* undef>, <4 x i64> <i64 0, i64 undef, i64 undef, i64 undef>, <4 x i64> [[ARG:%.*]]
+; CHECK-NEXT:    [[T:%.*]] = getelementptr inbounds [0 x i32], <4 x [0 x i32]*> <[0 x i32]* @global, [0 x i32]* poison, [0 x i32]* poison, [0 x i32]* poison>, <4 x i64> <i64 0, i64 poison, i64 poison, i64 poison>, <4 x i64> [[ARG:%.*]]
 ; CHECK-NEXT:    [[T2:%.*]] = extractelement <4 x i32*> [[T]], i64 0
 ; CHECK-NEXT:    ret i32* [[T2]]
 ;
@@ -722,7 +722,7 @@ define <4 x float> @select_cond_with_eq_true_false_elts3(<4 x float> %x, <4 x fl
 
 define <4 x i8> @select_cond_with_undef_true_false_elts(<4 x i8> %x, <4 x i8> %y, <4 x i1> %cmp) {
 ; CHECK-LABEL: @select_cond_with_undef_true_false_elts(
-; CHECK-NEXT:    [[TVAL:%.*]] = shufflevector <4 x i8> [[Y:%.*]], <4 x i8> undef, <4 x i32> <i32 undef, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TVAL:%.*]] = shufflevector <4 x i8> [[Y:%.*]], <4 x i8> poison, <4 x i32> <i32 undef, i32 1, i32 2, i32 3>
 ; CHECK-NEXT:    [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
 ; CHECK-NEXT:    [[R:%.*]] = select <4 x i1> [[COND]], <4 x i8> [[TVAL]], <4 x i8> [[X:%.*]]
 ; CHECK-NEXT:    ret <4 x i8> [[R]]
diff --git a/llvm/test/Transforms/InstCombine/vec_extract_var_elt-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_extract_var_elt-inseltpoison.ll
new file mode 100644
index 0000000000000..48b2513a00d72
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vec_extract_var_elt-inseltpoison.ll
@@ -0,0 +1,26 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define void @test (float %b, <8 x float> * %p)  {
+; CHECK: extractelement
+; CHECK: fptosi
+  %1 = load <8 x float> , <8 x float> * %p
+  %2 = bitcast <8 x float> %1 to <8 x i32>
+  %3 = bitcast <8 x i32> %2 to <8 x float>
+  %a = fptosi <8 x float> %3 to <8 x i32>
+  %4 = fptosi float %b to i32
+  %5 = add i32 %4, -2
+  %6 = extractelement <8 x i32> %a, i32 %5
+  %7 = insertelement <8 x i32> poison, i32 %6, i32 7
+  %8 = sitofp <8 x i32> %7 to <8 x float>
+  store <8 x float> %8, <8 x float>* %p
+  ret void    
+}
+
+; PR18600
+define i32 @test2(i32 %i) {
+  %e = extractelement <4 x i32> bitcast (<2 x i64> <i64 1, i64 2> to <4 x i32>), i32 %i
+  ret i32 %e
+
+; CHECK-LABEL: @test2
+; CHECK: extractelement
+}
diff --git a/llvm/test/Transforms/InstCombine/vec_gep_scalar_arg-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_gep_scalar_arg-inseltpoison.ll
new file mode 100644
index 0000000000000..e39b3e46801fe
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vec_gep_scalar_arg-inseltpoison.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -instcombine -S < %s | FileCheck %s
+
+define <4 x i16*> @PR41270([4 x i16]* %x) {
+; CHECK-LABEL: @PR41270(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x [4 x i16]*> undef, [4 x i16]* [[X:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [4 x i16], <4 x [4 x i16]*> [[TMP1]], i64 0, i64 3
+; CHECK-NEXT:    ret <4 x i16*> [[TMP2]]
+;
+  %ins = insertelement <4 x [4 x i16]*> poison, [4 x i16]* %x, i32 0
+  %splat = shufflevector <4 x [4 x i16]*> %ins, <4 x [4 x i16]*> undef, <4 x i32> zeroinitializer
+  %t2 = getelementptr inbounds [4 x i16], <4 x [4 x i16]*> %splat, i32 0, i32 3
+  %t3 = extractelement <4 x i16*> %t2, i32 3
+  %ins2 = insertelement <4 x i16*> poison, i16* %t3, i32 0
+  ret <4 x i16*> %ins2
+}
diff --git a/llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll
new file mode 100644
index 0000000000000..ba4f88d87d3b2
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll
@@ -0,0 +1,107 @@
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define void @f(i64 %val, i32  %limit, i32 *%ptr) {
+; CHECK-LABEL: @f
+; CHECK: %0 = trunc i64 %val to i32
+; CHECK: %1 = phi i32 [ %0, %entry ], [ {{.*}}, %loop ]
+entry:
+  %tempvector = insertelement <16 x i64> poison, i64 %val, i32 0
+  %vector = shufflevector <16 x i64> %tempvector, <16 x i64> undef, <16 x i32> zeroinitializer
+  %0 = add <16 x i64> %vector, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>
+  %1 = trunc <16 x i64> %0 to <16 x i32>
+  br label %loop
+
+loop:
+  %2 = phi <16 x i32> [ %1, %entry ], [ %inc, %loop ]
+  %elt = extractelement <16 x i32> %2, i32 0
+  %end = icmp ult i32 %elt, %limit
+  %3 = add i32 10, %elt
+  %4 = sext i32 %elt to i64
+  %5 = getelementptr i32, i32* %ptr, i64 %4
+  store i32 %3, i32* %5
+  %inc = add <16 x i32> %2, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+  br i1 %end, label %loop, label %ret
+
+ret:
+  ret void
+}
+
+define void @copy(i64 %val, i32  %limit, i32 *%ptr) {
+; CHECK-LABEL: @copy
+; CHECK: %0 = trunc i64 %val to i32
+; CHECK: %1 = phi i32 [ %0, %entry ], [ {{.*}}, %loop ]
+entry:
+  %tempvector = insertelement <16 x i64> poison, i64 %val, i32 0
+  %vector = shufflevector <16 x i64> %tempvector, <16 x i64> undef, <16 x i32> zeroinitializer
+  %0 = add <16 x i64> %vector, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>
+  %1 = trunc <16 x i64> %0 to <16 x i32>
+  br label %loop
+
+loop:
+  %2 = phi <16 x i32> [ %1, %entry ], [ %inc, %loop ]
+  %elt = extractelement <16 x i32> %2, i32 0
+  %eltcopy = extractelement <16 x i32> %2, i32 0
+  %end = icmp ult i32 %elt, %limit
+  %3 = add i32 10, %eltcopy
+  %4 = sext i32 %elt to i64
+  %5 = getelementptr i32, i32* %ptr, i64 %4
+  store i32 %3, i32* %5
+  %inc = add <16 x i32> %2, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+  br i1 %end, label %loop, label %ret
+
+ret:
+  ret void
+}
+
+define void @nocopy(i64 %val, i32  %limit, i32 *%ptr) {
+; CHECK-LABEL: @nocopy
+; CHECK-NOT: phi i32
+; CHECK: phi <16 x i32> [ %3, %entry ], [ %inc, %loop ]
+entry:
+  %tempvector = insertelement <16 x i64> poison, i64 %val, i32 0
+  %vector = shufflevector <16 x i64> %tempvector, <16 x i64> undef, <16 x i32> zeroinitializer
+  %0 = add <16 x i64> %vector, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>
+  %1 = trunc <16 x i64> %0 to <16 x i32>
+  br label %loop
+
+loop:
+  %2 = phi <16 x i32> [ %1, %entry ], [ %inc, %loop ]
+  %elt = extractelement <16 x i32> %2, i32 0
+  %eltcopy = extractelement <16 x i32> %2, i32 1
+  %end = icmp ult i32 %elt, %limit
+  %3 = add i32 10, %eltcopy
+  %4 = sext i32 %elt to i64
+  %5 = getelementptr i32, i32* %ptr, i64 %4
+  store i32 %3, i32* %5
+  %inc = add <16 x i32> %2, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+  br i1 %end, label %loop, label %ret
+
+ret:
+  ret void
+}
+
+define i1 @g(<3 x i32> %input_2) {
+; CHECK-LABEL: @g
+; CHECK: extractelement <3 x i32> %input_2, i32 0
+entry:
+  br label %for.cond
+
+for.cond:
+  %input_2.addr.0 = phi <3 x i32> [ %input_2, %entry ], [ %div45, %for.body ]
+  %input_1.addr.1 = phi <3 x i32> [ undef, %entry ], [ %dec43, %for.body ]
+  br i1 undef, label %for.end, label %for.body
+
+; CHECK-NOT: extractelement <3 x i32> %{{.*}}, i32 0
+for.body:
+  %dec43 = add <3 x i32> %input_1.addr.1, <i32 -1, i32 -1, i32 -1>
+  %sub44 = sub <3 x i32> <i32 -1, i32 -1, i32 -1>, %dec43
+  %div45 = sdiv <3 x i32> %input_2.addr.0, %sub44
+  br label %for.cond
+
+for.end:
+  %0 = extractelement <3 x i32> %input_2.addr.0, i32 0
+  %.89 = select i1 false, i32 0, i32 %0
+  %tobool313 = icmp eq i32 %.89, 0
+  ret i1 %tobool313
+}
+
diff --git a/llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
new file mode 100644
index 0000000000000..27ed637963b54
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll
@@ -0,0 +1,1791 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define <4 x float> @test1(<4 x float> %v1) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    ret <4 x float> [[V1:%.*]]
+;
+  %v2 = shufflevector <4 x float> %v1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  ret <4 x float> %v2
+}
+
+define <4 x float> @test2(<4 x float> %v1) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    ret <4 x float> [[V1:%.*]]
+;
+  %v2 = shufflevector <4 x float> %v1, <4 x float> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+  ret <4 x float> %v2
+}
+
+define float @test3(<4 x float> %A, <4 x float> %B, float %f) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    ret float [[F:%.*]]
+;
+  %C = insertelement <4 x float> %A, float %f, i32 0
+  %D = shufflevector <4 x float> %C, <4 x float> %B, <4 x i32> <i32 5, i32 0, i32 2, i32 7>
+  %E = extractelement <4 x float> %D, i32 1
+  ret float %E
+}
+
+define i32 @test4(<4 x i32> %X) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %t = shufflevector <4 x i32> %X, <4 x i32> undef, <4 x i32> zeroinitializer
+  %r = extractelement <4 x i32> %t, i32 0
+  ret i32 %r
+}
+
+define i32 @test5(<4 x i32> %X) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 3
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %t = shufflevector <4 x i32> %X, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 undef, i32 undef>
+  %r = extractelement <4 x i32> %t, i32 0
+  ret i32 %r
+}
+
+define float @test6(<4 x float> %X) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x float> [[X:%.*]], i32 0
+; CHECK-NEXT:    ret float [[R]]
+;
+  %X1 = bitcast <4 x float> %X to <4 x i32>
+  %t = shufflevector <4 x i32> %X1, <4 x i32> undef, <4 x i32> zeroinitializer
+  %t2 = bitcast <4 x i32> %t to <4 x float>
+  %r = extractelement <4 x float> %t2, i32 0
+  ret float %r
+}
+
+define float @testvscale6(<vscale x 4 x float> %X) {
+; CHECK-LABEL: @testvscale6(
+; CHECK-NEXT:    [[T2:%.*]] = shufflevector <vscale x 4 x float> [[X:%.*]], <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x float> [[T2]], i32 0
+; CHECK-NEXT:    ret float [[R]]
+;
+  %X1 = bitcast <vscale x 4 x float> %X to <vscale x 4 x i32>
+  %t = shufflevector <vscale x 4 x i32> %X1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %t2 = bitcast <vscale x 4 x i32> %t to <vscale x 4 x float>
+  %r = extractelement <vscale x 4 x float> %t2, i32 0
+  ret float %r
+}
+
+
+define <4 x float> @test7(<4 x float> %x) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %r = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 6, i32 7 >
+  ret <4 x float> %r
+}
+
+; This should turn into a single shuffle.
+define <4 x float> @test8(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT:    [[T132:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> poison, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
+; CHECK-NEXT:    [[T134:%.*]] = shufflevector <4 x float> [[T132]], <4 x float> [[Y:%.*]], <4 x i32> <i32 0, i32 undef, i32 2, i32 4>
+; CHECK-NEXT:    ret <4 x float> [[T134]]
+;
+  %t4 = extractelement <4 x float> %x, i32 1
+  %t2 = extractelement <4 x float> %x, i32 3
+  %t1 = extractelement <4 x float> %y, i32 0
+  %t128 = insertelement <4 x float> poison, float %t4, i32 0
+  %t130 = insertelement <4 x float> %t128, float undef, i32 1
+  %t132 = insertelement <4 x float> %t130, float %t2, i32 2
+  %t134 = insertelement <4 x float> %t132, float %t1, i32 3
+  ret <4 x float> %t134
+}
+
+; Test fold of two shuffles where the first shuffle vectors inputs are a
+; different length then the second.
+define <4 x i8> @test9(<16 x i8> %t6) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT:    [[T9:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> undef, <4 x i32> <i32 13, i32 9, i32 4, i32 13>
+; CHECK-NEXT:    ret <4 x i8> [[T9]]
+;
+  %t7 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> < i32 13, i32 9, i32 4, i32 13 >
+  %t9 = shufflevector <4 x i8> %t7, <4 x i8> undef, <4 x i32> < i32 3, i32 1, i32 2, i32 0 >
+  ret <4 x i8> %t9
+}
+
+; Same as test9, but make sure that "undef" mask values are not confused with
+; mask values of 2*N, where N is the mask length.  These shuffles should not
+; be folded (because [8,9,4,8] may not be a mask supported by the target).
+
+define <4 x i8> @test9a(<16 x i8> %t6) {
+; CHECK-LABEL: @test9a(
+; CHECK-NEXT:    [[T7:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> undef, <4 x i32> <i32 undef, i32 9, i32 4, i32 8>
+; CHECK-NEXT:    [[T9:%.*]] = shufflevector <4 x i8> [[T7]], <4 x i8> undef, <4 x i32> <i32 3, i32 1, i32 2, i32 undef>
+; CHECK-NEXT:    ret <4 x i8> [[T9]]
+;
+  %t7 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> < i32 undef, i32 9, i32 4, i32 8 >
+  %t9 = shufflevector <4 x i8> %t7, <4 x i8> undef, <4 x i32> < i32 3, i32 1, i32 2, i32 0 >
+  ret <4 x i8> %t9
+}
+
+; Test fold of two shuffles where the first shuffle vectors inputs are a
+; different length then the second.
+define <4 x i8> @test9b(<4 x i8> %t6, <4 x i8> %t7) {
+; CHECK-LABEL: @test9b(
+; CHECK-NEXT:    [[T9:%.*]] = shufflevector <4 x i8> [[T6:%.*]], <4 x i8> [[T7:%.*]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; CHECK-NEXT:    ret <4 x i8> [[T9]]
+;
+  %t1 = shufflevector <4 x i8> %t6, <4 x i8> %t7, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 2, i32 3>
+  %t9 = shufflevector <8 x i8> %t1, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+  ret <4 x i8> %t9
+}
+
+; Redundant vector splats should be removed.  Radar 8597790.
+define <4 x i32> @test10(<4 x i32> %t5) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT:    [[T7:%.*]] = shufflevector <4 x i32> [[T5:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT:    ret <4 x i32> [[T7]]
+;
+  %t6 = shufflevector <4 x i32> %t5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+  %t7 = shufflevector <4 x i32> %t6, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %t7
+}
+
+; Test fold of two shuffles where the two shufflevector inputs's op1 are the same.
+
+define <8 x i8> @test11(<16 x i8> %t6) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT:    [[T3:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; CHECK-NEXT:    ret <8 x i8> [[T3]]
+;
+  %t1 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+  %t2 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+  %t3 = shufflevector <4 x i8> %t1, <4 x i8> %t2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i8> %t3
+}
+
+; Test fold of two shuffles where the first shufflevector's inputs are the same as the second.
+
+define <8 x i8> @test12(<8 x i8> %t6, <8 x i8> %t2) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT:    [[T3:%.*]] = shufflevector <8 x i8> [[T6:%.*]], <8 x i8> [[T2:%.*]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 9, i32 8, i32 11, i32 12>
+; CHECK-NEXT:    ret <8 x i8> [[T3]]
+;
+  %t1 = shufflevector <8 x i8> %t6, <8 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 undef, i32 7>
+  %t3 = shufflevector <8 x i8> %t1, <8 x i8> %t2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 9, i32 8, i32 11, i32 12>
+  ret <8 x i8> %t3
+}
+
+; Test fold of two shuffles where the first shufflevector's inputs are the same as the second.
+
+define <8 x i8> @test12a(<8 x i8> %t6, <8 x i8> %t2) {
+; CHECK-LABEL: @test12a(
+; CHECK-NEXT:    [[T3:%.*]] = shufflevector <8 x i8> [[T2:%.*]], <8 x i8> [[T6:%.*]], <8 x i32> <i32 0, i32 3, i32 1, i32 4, i32 8, i32 9, i32 10, i32 11>
+; CHECK-NEXT:    ret <8 x i8> [[T3]]
+;
+  %t1 = shufflevector <8 x i8> %t6, <8 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 5, i32 4, i32 undef, i32 7>
+  %t3 = shufflevector <8 x i8> %t2, <8 x i8> %t1, <8 x i32> <i32 0, i32 3, i32 1, i32 4, i32 8, i32 9, i32 10, i32 11>
+  ret <8 x i8> %t3
+}
+
+; The mask length of the 1st shuffle can be reduced to eliminate the 2nd shuffle.
+
+define <2 x i8> @extract_subvector_of_shuffle(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @extract_subvector_of_shuffle(
+; CHECK-NEXT:    [[EXTRACT_SUBV:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]], <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT:    ret <2 x i8> [[EXTRACT_SUBV]]
+;
+  %shuf = shufflevector <2 x i8> %x, <2 x i8> %y, <3 x i32> <i32 0, i32 2, i32 0>
+  %extract_subv = shufflevector <3 x i8> %shuf, <3 x i8> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x i8> %extract_subv
+}
+
+; Undef elements in either mask are ok. Undefs from the 2nd shuffle mask should propagate to the new shuffle.
+; The type of the inputs does not have to match the output type.
+
+define <4 x i8> @extract_subvector_of_shuffle_undefs_types(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @extract_subvector_of_shuffle_undefs_types(
+; CHECK-NEXT:    [[EXTRACT_SUBV:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]], <4 x i32> <i32 undef, i32 2, i32 0, i32 undef>
+; CHECK-NEXT:    ret <4 x i8> [[EXTRACT_SUBV]]
+;
+  %shuf = shufflevector <2 x i8> %x, <2 x i8> %y, <5 x i32> <i32 undef, i32 2, i32 0, i32 1, i32 0>
+  %extract_subv = shufflevector <5 x i8> %shuf, <5 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
+  ret <4 x i8> %extract_subv
+}
+
+; Extra uses are not ok - we only do the transform when we can eliminate an instruction.
+
+declare void @use_v5i8(<5 x i8>)
+
+define <4 x i8> @extract_subvector_of_shuffle_extra_use(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @extract_subvector_of_shuffle_extra_use(
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]], <5 x i32> <i32 undef, i32 2, i32 0, i32 1, i32 0>
+; CHECK-NEXT:    call void @use_v5i8(<5 x i8> [[SHUF]])
+; CHECK-NEXT:    [[EXTRACT_SUBV:%.*]] = shufflevector <5 x i8> [[SHUF]], <5 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
+; CHECK-NEXT:    ret <4 x i8> [[EXTRACT_SUBV]]
+;
+  %shuf = shufflevector <2 x i8> %x, <2 x i8> %y, <5 x i32> <i32 undef, i32 2, i32 0, i32 1, i32 0>
+  call void @use_v5i8(<5 x i8> %shuf)
+  %extract_subv = shufflevector <5 x i8> %shuf, <5 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
+  ret <4 x i8> %extract_subv
+}
+
+define <2 x i8> @test13a(i8 %x1, i8 %x2) {
+; CHECK-LABEL: @test13a(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X1:%.*]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = add <2 x i8> [[TMP2]], <i8 7, i8 5>
+; CHECK-NEXT:    ret <2 x i8> [[TMP3]]
+;
+  %A = insertelement <2 x i8> poison, i8 %x1, i32 0
+  %B = insertelement <2 x i8> %A, i8 %x2, i32 1
+  %C = add <2 x i8> %B, <i8 5, i8 7>
+  %D = shufflevector <2 x i8> %C, <2 x i8> undef, <2 x i32> <i32 1, i32 0>
+  ret <2 x i8> %D
+}
+
+; Increasing length of vector ops is not a good canonicalization.
+
+define <3 x i32> @add_wider(i32 %y, i32 %z) {
+; CHECK-LABEL: @add_wider(
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <2 x i32> poison, i32 [[Y:%.*]], i32 0
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <2 x i32> [[I0]], i32 [[Z:%.*]], i32 1
+; CHECK-NEXT:    [[A:%.*]] = add <2 x i32> [[I1]], <i32 255, i32 255>
+; CHECK-NEXT:    [[EXT:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+; CHECK-NEXT:    ret <3 x i32> [[EXT]]
+;
+  %i0 = insertelement <2 x i32> poison, i32 %y, i32 0
+  %i1 = insertelement <2 x i32> %i0, i32 %z, i32 1
+  %a = add <2 x i32> %i1, <i32 255, i32 255>
+  %ext = shufflevector <2 x i32> %a, <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+  ret <3 x i32> %ext
+}
+
+; Increasing length of vector ops must be safe from illegal undef propagation.
+
+define <3 x i32> @div_wider(i32 %y, i32 %z) {
+; CHECK-LABEL: @div_wider(
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <2 x i32> poison, i32 [[Y:%.*]], i32 0
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <2 x i32> [[I0]], i32 [[Z:%.*]], i32 1
+; CHECK-NEXT:    [[A:%.*]] = sdiv <2 x i32> [[I1]], <i32 255, i32 255>
+; CHECK-NEXT:    [[EXT:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+; CHECK-NEXT:    ret <3 x i32> [[EXT]]
+;
+  %i0 = insertelement <2 x i32> poison, i32 %y, i32 0
+  %i1 = insertelement <2 x i32> %i0, i32 %z, i32 1
+  %a = sdiv <2 x i32> %i1, <i32 255, i32 255>
+  %ext = shufflevector <2 x i32> %a, <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+  ret <3 x i32> %ext
+}
+
+; Increasing length of insertelements (no math ops) is a good canonicalization.
+
+define <3 x i8> @fold_inselts_with_widening_shuffle(i8 %x, i8 %y) {
+; CHECK-LABEL: @fold_inselts_with_widening_shuffle(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <3 x i8> [[TMP1]], i8 [[Y:%.*]], i32 1
+; CHECK-NEXT:    ret <3 x i8> [[TMP2]]
+;
+  %ins0 = insertelement <2 x i8> poison, i8 %x, i32 0
+  %ins1 = insertelement <2 x i8> %ins0, i8 %y, i32 1
+  %widen = shufflevector <2 x i8> %ins1, <2 x i8> undef, <3 x i32> <i32 0, i32 1, i32 undef>
+  ret <3 x i8> %widen
+}
+
+define <2 x i8> @test13b(i8 %x) {
+; CHECK-LABEL: @test13b(
+; CHECK-NEXT:    [[B:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    ret <2 x i8> [[B]]
+;
+  %A = insertelement <2 x i8> poison, i8 %x, i32 0
+  %B = shufflevector <2 x i8> %A, <2 x i8> undef, <2 x i32> <i32 undef, i32 0>
+  ret <2 x i8> %B
+}
+
+define <2 x i8> @test13c(i8 %x1, i8 %x2) {
+; CHECK-LABEL: @test13c(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X1:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i32 1
+; CHECK-NEXT:    ret <2 x i8> [[TMP2]]
+;
+  %A = insertelement <4 x i8> poison, i8 %x1, i32 0
+  %B = insertelement <4 x i8> %A, i8 %x2, i32 2
+  %C = shufflevector <4 x i8> %B, <4 x i8> undef, <2 x i32> <i32 0, i32 2>
+  ret <2 x i8> %C
+}
+
+define void @test14(i16 %conv10) {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT:    store <4 x i16> <i16 poison, i16 poison, i16 poison, i16 23>, <4 x i16>* undef, align 8
+; CHECK-NEXT:    ret void
+;
+  %t = alloca <4 x i16>, align 8
+  %vecinit6 = insertelement <4 x i16> poison, i16 23, i32 3
+  store <4 x i16> %vecinit6, <4 x i16>* undef
+  %t1 = load <4 x i16>, <4 x i16>* undef
+  %vecinit11 = insertelement <4 x i16> poison, i16 %conv10, i32 3
+  %div = udiv <4 x i16> %t1, %vecinit11
+  store <4 x i16> %div, <4 x i16>* %t
+  %t4 = load <4 x i16>, <4 x i16>* %t
+  %t5 = shufflevector <4 x i16> %t4, <4 x i16> undef, <2 x i32> <i32 2, i32 0>
+  %cmp = icmp ule <2 x i16> %t5, undef
+  %sext = sext <2 x i1> %cmp to <2 x i16>
+  ret void
+}
+
+; Check that sequences of insert/extract element are
+; collapsed into valid shuffle instruction with correct shuffle indexes.
+
+define <4 x float> @test15a(<4 x float> %LHS, <4 x float> %RHS) {
+; CHECK-LABEL: @test15a(
+; CHECK-NEXT:    [[T4:%.*]] = shufflevector <4 x float> [[LHS:%.*]], <4 x float> [[RHS:%.*]], <4 x i32> <i32 4, i32 0, i32 6, i32 6>
+; CHECK-NEXT:    ret <4 x float> [[T4]]
+;
+  %t1 = extractelement <4 x float> %LHS, i32 0
+  %t2 = insertelement <4 x float> %RHS, float %t1, i32 1
+  %t3 = extractelement <4 x float> %RHS, i32 2
+  %t4 = insertelement <4 x float> %t2, float %t3, i32 3
+  ret <4 x float> %t4
+}
+
+define <4 x float> @test15b(<4 x float> %LHS, <4 x float> %RHS) {
+; CHECK-LABEL: @test15b(
+; CHECK-NEXT:    [[T5:%.*]] = shufflevector <4 x float> [[LHS:%.*]], <4 x float> [[RHS:%.*]], <4 x i32> <i32 4, i32 3, i32 6, i32 6>
+; CHECK-NEXT:    ret <4 x float> [[T5]]
+;
+  %t0 = extractelement <4 x float> %LHS, i32 3
+  %t1 = insertelement <4 x float> %RHS, float %t0, i32 0
+  %t2 = extractelement <4 x float> %t1, i32 0
+  %t3 = insertelement <4 x float> %RHS, float %t2, i32 1
+  %t4 = extractelement <4 x float> %RHS, i32 2
+  %t5 = insertelement <4 x float> %t3, float %t4, i32 3
+  ret <4 x float> %t5
+}
+
+define <1 x i32> @test16a(i32 %ele) {
+; CHECK-LABEL: @test16a(
+; CHECK-NEXT:    ret <1 x i32> <i32 2>
+;
+  %t0 = insertelement <2 x i32> <i32 1, i32 undef>, i32 %ele, i32 1
+  %t1 = shl <2 x i32> %t0, <i32 1, i32 1>
+  %t2 = shufflevector <2 x i32> %t1, <2 x i32> undef, <1 x i32> <i32 0>
+  ret <1 x i32> %t2
+}
+
+define <4 x i8> @test16b(i8 %ele) {
+; CHECK-LABEL: @test16b(
+; CHECK-NEXT:    ret <4 x i8> <i8 2, i8 2, i8 2, i8 2>
+;
+  %t0 = insertelement <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 undef, i8 1>, i8 %ele, i32 6
+  %t1 = shl <8 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %t2 = shufflevector <8 x i8> %t1, <8 x i8> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
+  ret <4 x i8> %t2
+}
+
+; If composition of two shuffles is identity, shuffles can be removed.
+define <4 x i32> @shuffle_17ident(<4 x i32> %v) {
+; CHECK-LABEL: @shuffle_17ident(
+; CHECK-NEXT:    ret <4 x i32> [[V:%.*]]
+;
+  %shuffle = shufflevector <4 x i32> %v, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %shuffle2 = shufflevector <4 x i32> %shuffle, <4 x i32> zeroinitializer, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
+  ret <4 x i32> %shuffle2
+}
+
+; swizzle can be put after operation
+define <4 x i32> @shuffle_17and(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: @shuffle_17and(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <4 x i32> [[V1:%.*]], [[V2:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %t1 = shufflevector <4 x i32> %v1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %t2 = shufflevector <4 x i32> %v2, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %r = and <4 x i32> %t1, %t2
+  ret <4 x i32> %r
+}
+
+declare void @use(<2 x float>)
+
+; One extra use is ok to transform.
+
+define <2 x float> @shuffle_fadd_multiuse(<2 x float> %v1, <2 x float> %v2) {
+; CHECK-LABEL: @shuffle_fadd_multiuse(
+; CHECK-NEXT:    [[T1:%.*]] = shufflevector <2 x float> [[V1:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x float> [[V1]], [[V2:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    call void @use(<2 x float> [[T1]])
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+  %t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+  %r = fadd <2 x float> %t1, %t2
+  call void @use(<2 x float> %t1)
+  ret <2 x float> %r
+}
+
+define <2 x float> @shuffle_fdiv_multiuse(<2 x float> %v1, <2 x float> %v2) {
+; CHECK-LABEL: @shuffle_fdiv_multiuse(
+; CHECK-NEXT:    [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <2 x float> [[V1:%.*]], [[V2]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    call void @use(<2 x float> [[T2]])
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+  %t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+  %r = fdiv <2 x float> %t1, %t2
+  call void @use(<2 x float> %t2)
+  ret <2 x float> %r
+}
+
+; But 2 extra uses would require an extra instruction.
+
+define <2 x float> @shuffle_fsub_multiuse(<2 x float> %v1, <2 x float> %v2) {
+; CHECK-LABEL: @shuffle_fsub_multiuse(
+; CHECK-NEXT:    [[T1:%.*]] = shufflevector <2 x float> [[V1:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    [[R:%.*]] = fsub <2 x float> [[T1]], [[T2]]
+; CHECK-NEXT:    call void @use(<2 x float> [[T1]])
+; CHECK-NEXT:    call void @use(<2 x float> [[T2]])
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+  %t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+  %r = fsub <2 x float> %t1, %t2
+  call void @use(<2 x float> %t1)
+  call void @use(<2 x float> %t2)
+  ret <2 x float> %r
+}
+
+define <4 x i32> @shuffle_17add(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: @shuffle_17add(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[V1:%.*]], [[V2:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %t1 = shufflevector <4 x i32> %v1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %t2 = shufflevector <4 x i32> %v2, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %r = add <4 x i32> %t1, %t2
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @shuffle_17addnsw(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: @shuffle_17addnsw(
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw <4 x i32> [[V1:%.*]], [[V2:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %t1 = shufflevector <4 x i32> %v1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %t2 = shufflevector <4 x i32> %v2, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %r = add nsw <4 x i32> %t1, %t2
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @shuffle_17addnuw(<4 x i32> %v1, <4 x i32> %v2) {
+; CHECK-LABEL: @shuffle_17addnuw(
+; CHECK-NEXT:    [[TMP1:%.*]] = add nuw <4 x i32> [[V1:%.*]], [[V2:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %t1 = shufflevector <4 x i32> %v1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %t2 = shufflevector <4 x i32> %v2, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %r = add nuw <4 x i32> %t1, %t2
+  ret <4 x i32> %r
+}
+
+define <4 x float> @shuffle_17fsub_fast(<4 x float> %v1, <4 x float> %v2) {
+; CHECK-LABEL: @shuffle_17fsub_fast(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub fast <4 x float> [[V1:%.*]], [[V2:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %t1 = shufflevector <4 x float> %v1, <4 x float> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %t2 = shufflevector <4 x float> %v2, <4 x float> zeroinitializer, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %r = fsub fast <4 x float> %t1, %t2
+  ret <4 x float> %r
+}
+
+define <4 x i32> @add_const(<4 x i32> %v) {
+; CHECK-LABEL: @add_const(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[V:%.*]], <i32 44, i32 41, i32 42, i32 43>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %t1 = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+  %r = add <4 x i32> %t1, <i32 41, i32 42, i32 43, i32 44>
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @sub_const(<4 x i32> %v) {
+; CHECK-LABEL: @sub_const(
+; CHECK-NEXT:    [[TMP1:%.*]] = sub <4 x i32> <i32 44, i32 43, i32 42, i32 41>, [[V:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %t1 = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %r = sub <4 x i32> <i32 41, i32 42, i32 43, i32 44>, %t1
+  ret <4 x i32> %r
+}
+
+; Math before shuffle requires an extra shuffle.
+
+define <2 x float> @fadd_const_multiuse(<2 x float> %v) {
+; CHECK-LABEL: @fadd_const_multiuse(
+; CHECK-NEXT:    [[T1:%.*]] = shufflevector <2 x float> [[V:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    [[R:%.*]] = fadd <2 x float> [[T1]], <float 4.100000e+01, float 4.200000e+01>
+; CHECK-NEXT:    call void @use(<2 x float> [[T1]])
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %t1 = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> <i32 1, i32 0>
+  %r = fadd <2 x float> %t1, <float 41.0, float 42.0>
+  call void @use(<2 x float> %t1)
+  ret <2 x float> %r
+}
+
+; Math before splat allows replacing constant elements with undef lanes.
+
+define <4 x i32> @mul_const_splat(<4 x i32> %v) {
+; CHECK-LABEL: @mul_const_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <4 x i32> [[V:%.*]], <i32 poison, i32 42, i32 poison, i32 poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %t1 = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+  %r = mul <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %t1
+  ret <4 x i32> %r
+}
+
+; Take 2 elements of a vector and shift each of those by a different amount
+
+define <4 x i32> @lshr_const_half_splat(<4 x i32> %v) {
+; CHECK-LABEL: @lshr_const_half_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <4 x i32> <i32 undef, i32 8, i32 9, i32 undef>, [[V:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 2>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %t1 = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 2>
+  %r = lshr <4 x i32> <i32 8, i32 8, i32 9, i32 9>, %t1
+  ret <4 x i32> %r
+}
+
+; We can't change this because there's no pre-shuffle version of the fmul constant.
+
+define <2 x float> @fmul_const_invalid_constant(<2 x float> %v) {
+; CHECK-LABEL: @fmul_const_invalid_constant(
+; CHECK-NEXT:    [[T1:%.*]] = shufflevector <2 x float> [[V:%.*]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = fmul <2 x float> [[T1]], <float 4.100000e+01, float 4.200000e+01>
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %t1 = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> <i32 0, i32 0>
+  %r = fmul <2 x float> %t1, <float 41.0, float 42.0>
+  ret <2 x float> %r
+}
+
+; Reduce the width of the binop by moving it ahead of a shuffle.
+
+define <4 x i8> @widening_shuffle_add_1(<2 x i8> %x) {
+; CHECK-LABEL: @widening_shuffle_add_1(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i8> [[X:%.*]], <i8 42, i8 43>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i8> [[TMP1]], <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x i8> [[R]]
+;
+  %widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45>
+  ret <4 x i8> %r
+}
+
+; Reduce the width of the binop by moving it ahead of a shuffle.
+
+define <4 x i8> @widening_shuffle_add_2(<2 x i8> %x) {
+; CHECK-LABEL: @widening_shuffle_add_2(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i8> [[X:%.*]], <i8 43, i8 42>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i8> [[TMP1]], <2 x i8> undef, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x i8> [[R]]
+;
+  %widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>
+  %r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45>
+  ret <4 x i8> %r
+}
+
+; Negative test - widening shuffles have the same mask/constant constraint as non-size-changing shuffles.
+
+define <4 x i8> @widening_shuffle_add_invalid_constant(<2 x i8> %x) {
+; CHECK-LABEL: @widening_shuffle_add_invalid_constant(
+; CHECK-NEXT:    [[WIDEX:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 1, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i8> [[WIDEX]], <i8 42, i8 43, i8 44, i8 45>
+; CHECK-NEXT:    ret <4 x i8> [[R]]
+;
+  %widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 1, i32 1, i32 undef, i32 undef>
+  %r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45>
+  ret <4 x i8> %r
+}
+
+; Negative test - widening shuffles have an additional constraint: they must not extend with anything but undefs.
+
+define <4 x i8> @widening_shuffle_add_invalid_mask(<2 x i8> %x) {
+; CHECK-LABEL: @widening_shuffle_add_invalid_mask(
+; CHECK-NEXT:    [[WIDEX:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 0>
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i8> [[WIDEX]], <i8 42, i8 43, i8 44, i8 45>
+; CHECK-NEXT:    ret <4 x i8> [[R]]
+;
+  %widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 0>
+  %r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45>
+  ret <4 x i8> %r
+}
+
+; A binop that produces undef in the high lanes can be moved before the shuffle.
+; This is ok because 'shl C, undef --> undef'.
+
+define <4 x i16> @widening_shuffle_shl_constant_op0(<2 x i16> %v) {
+; CHECK-LABEL: @widening_shuffle_shl_constant_op0(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i16> <i16 42, i16 -42>, [[V:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x i16> [[BO]]
+;
+  %shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %bo = shl <4 x i16> <i16 42, i16 -42, i16 -1, i16 -1>, %shuf
+  ret <4 x i16> %bo
+}
+
+; A binop that produces undef in the high lanes can be moved before the shuffle.
+; This is ok because 'shl undef, 0 --> undef'.
+
+define <4 x i16> @widening_shuffle_shl_constant_op1(<2 x i16> %v) {
+; CHECK-LABEL: @widening_shuffle_shl_constant_op1(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i16> [[V:%.*]], <i16 2, i16 4>
+; CHECK-NEXT:    [[BO:%.*]] = shufflevector <2 x i16> [[TMP1]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x i16> [[BO]]
+;
+  %shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %bo = shl <4 x i16> %shuf, <i16 2, i16 4, i16 0, i16 0>
+  ret <4 x i16> %bo
+}
+
+; A binop that does not produce undef in the high lanes can not be moved before the shuffle.
+; This is not ok because 'shl undef, 1 (or 2)' --> 0' but moving the shuffle results in undef instead.
+
+define <4 x i16> @widening_shuffle_shl_constant_op1_non0(<2 x i16> %v) {
+; CHECK-LABEL: @widening_shuffle_shl_constant_op1_non0(
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <2 x i16> [[V:%.*]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[BO:%.*]] = shl <4 x i16> [[SHUF]], <i16 2, i16 4, i16 1, i16 2>
+; CHECK-NEXT:    ret <4 x i16> [[BO]]
+;
+  %shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %bo = shl <4 x i16> %shuf, <i16 2, i16 4, i16 1, i16 2>
+  ret <4 x i16> %bo
+}
+
+; A binop that does not produce undef in the high lanes can not be moved before the shuffle.
+; This is not ok because 'or -1, undef --> -1' but moving the shuffle results in undef instead.
+
+define <4 x i16> @widening_shuffle_or(<2 x i16> %v) {
+; CHECK-LABEL: @widening_shuffle_or(
+; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <2 x i16> [[V:%.*]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[BO:%.*]] = or <4 x i16> [[SHUF]], <i16 42, i16 -42, i16 -1, i16 -1>
+; CHECK-NEXT:    ret <4 x i16> [[BO]]
+;
+  %shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %bo = or <4 x i16> %shuf, <i16 42, i16 -42, i16 -1, i16 -1>
+  ret <4 x i16> %bo
+}
+
+define <4 x i32> @shuffle_17add2(<4 x i32> %v) {
+; CHECK-LABEL: @shuffle_17add2(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <4 x i32> [[V:%.*]], <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT:    ret <4 x i32> [[TMP1]]
+;
+  %t1 = shufflevector <4 x i32> %v, <4 x i32> zeroinitializer, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %t2 = add <4 x i32> %t1, %t1
+  %r = shufflevector <4 x i32> %t2, <4 x i32> zeroinitializer, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @shuffle_17mulsplat(<4 x i32> %v) {
+; CHECK-LABEL: @shuffle_17mulsplat(
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <4 x i32> [[V:%.*]], [[V]]
+; CHECK-NEXT:    [[M1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    ret <4 x i32> [[M1]]
+;
+  %s1 = shufflevector <4 x i32> %v, <4 x i32> zeroinitializer, <4 x i32> zeroinitializer
+  %m1 = mul <4 x i32> %s1, %s1
+  %s2 = shufflevector <4 x i32> %m1, <4 x i32> zeroinitializer, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
+  ret <4 x i32> %s2
+}
+
+; Do not reorder shuffle and binop if LHS of shuffles are of different size
+define <2 x i32> @pr19717(<4 x i32> %in0, <2 x i32> %in1) {
+; CHECK-LABEL: @pr19717(
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[IN0:%.*]], <4 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[SHUFFLE4:%.*]] = shufflevector <2 x i32> [[IN1:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[MUL:%.*]] = mul <2 x i32> [[SHUFFLE]], [[SHUFFLE4]]
+; CHECK-NEXT:    ret <2 x i32> [[MUL]]
+;
+  %shuffle = shufflevector <4 x i32> %in0, <4 x i32> %in0, <2 x i32> zeroinitializer
+  %shuffle4 = shufflevector <2 x i32> %in1, <2 x i32> %in1, <2 x i32> zeroinitializer
+  %mul = mul <2 x i32> %shuffle, %shuffle4
+  ret <2 x i32> %mul
+}
+
+define <4 x i16> @pr19717a(<8 x i16> %in0, <8 x i16> %in1) {
+; CHECK-LABEL: @pr19717a(
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <8 x i16> [[IN0:%.*]], [[IN1:%.*]]
+; CHECK-NEXT:    [[MUL:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <4 x i32> <i32 5, i32 5, i32 5, i32 5>
+; CHECK-NEXT:    ret <4 x i16> [[MUL]]
+;
+  %shuffle = shufflevector <8 x i16> %in0, <8 x i16> %in0, <4 x i32> <i32 5, i32 5, i32 5, i32 5>
+  %shuffle1 = shufflevector <8 x i16> %in1, <8 x i16> %in1, <4 x i32> <i32 5, i32 5, i32 5, i32 5>
+  %mul = mul <4 x i16> %shuffle, %shuffle1
+  ret <4 x i16> %mul
+}
+
+define <8 x i8> @pr19730(<16 x i8> %in0) {
+; CHECK-LABEL: @pr19730(
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <16 x i8> [[IN0:%.*]], <16 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[SHUFFLE1:%.*]] = shufflevector <8 x i8> [[SHUFFLE]], <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x i8> [[SHUFFLE1]]
+;
+  %shuffle = shufflevector <16 x i8> %in0, <16 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+  %shuffle1 = shufflevector <8 x i8> %shuffle, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+  ret <8 x i8> %shuffle1
+}
+
+define i32 @pr19737(<4 x i32> %in0) {
+; CHECK-LABEL: @pr19737(
+; CHECK-NEXT:    [[RV:%.*]] = extractelement <4 x i32> [[IN0:%.*]], i32 0
+; CHECK-NEXT:    ret i32 [[RV]]
+;
+  %shuffle.i = shufflevector <4 x i32> zeroinitializer, <4 x i32> %in0, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+  %neg.i = xor <4 x i32> %shuffle.i, <i32 -1, i32 -1, i32 -1, i32 -1>
+  %and.i = and <4 x i32> %in0, %neg.i
+  %rv = extractelement <4 x i32> %and.i, i32 0
+  ret i32 %rv
+}
+
+; In PR20059 ( http://llvm.org/pr20059 ), shufflevector operations are reordered/removed
+; for an srem operation. This is not a valid optimization because it may cause a trap
+; on div-by-zero.
+
+define <4 x i32> @pr20059(<4 x i32> %p1, <4 x i32> %p2) {
+; CHECK-LABEL: @pr20059(
+; CHECK-NEXT:    [[SPLAT1:%.*]] = shufflevector <4 x i32> [[P1:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[SPLAT2:%.*]] = shufflevector <4 x i32> [[P2:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[RETVAL:%.*]] = srem <4 x i32> [[SPLAT1]], [[SPLAT2]]
+; CHECK-NEXT:    ret <4 x i32> [[RETVAL]]
+;
+  %splat1 = shufflevector <4 x i32> %p1, <4 x i32> undef, <4 x i32> zeroinitializer
+  %splat2 = shufflevector <4 x i32> %p2, <4 x i32> undef, <4 x i32> zeroinitializer
+  %retval = srem <4 x i32> %splat1, %splat2
+  ret <4 x i32> %retval
+}
+
+define <4 x i32> @pr20114(<4 x i32> %__mask) {
+; CHECK-LABEL: @pr20114(
+; CHECK-NEXT:    [[MASK01_I:%.*]] = shufflevector <4 x i32> [[__MASK:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
+; CHECK-NEXT:    [[MASKED_NEW_I_I_I:%.*]] = and <4 x i32> [[MASK01_I]], bitcast (<2 x i64> <i64 ptrtoint (<4 x i32> (<4 x i32>)* @pr20114 to i64), i64 ptrtoint (<4 x i32> (<4 x i32>)* @pr20114 to i64)> to <4 x i32>)
+; CHECK-NEXT:    ret <4 x i32> [[MASKED_NEW_I_I_I]]
+;
+  %mask01.i = shufflevector <4 x i32> %__mask, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
+  %masked_new.i.i.i = and <4 x i32> bitcast (<2 x i64> <i64 ptrtoint (<4 x i32> (<4 x i32>)* @pr20114 to i64), i64 ptrtoint (<4 x i32> (<4 x i32>)* @pr20114 to i64)> to <4 x i32>), %mask01.i
+  ret <4 x i32> %masked_new.i.i.i
+}
+
+define <2 x i32*> @pr23113(<4 x i32*> %A) {
+; CHECK-LABEL: @pr23113(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32*> [[A:%.*]], <4 x i32*> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT:    ret <2 x i32*> [[TMP1]]
+;
+  %1 = shufflevector <4 x i32*> %A, <4 x i32*> undef, <2 x i32> <i32 0, i32 1>
+  ret <2 x i32*> %1
+}
+
+; Unused lanes in the new binop should not kill the entire op (although it may simplify anyway as shown here).
+
+define <2 x i32> @PR37648(<2 x i32> %x) {
+; CHECK-LABEL: @PR37648(
+; CHECK-NEXT:    ret <2 x i32> zeroinitializer
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = urem <2 x i32> %splat, <i32 1, i32 1>
+  ret <2 x i32> %r
+}
+
+; Test shuffle followed by binop with splat constant for all 18 binop opcodes.
+; Test with constant as operand 0 and operand 1 for non-commutative opcodes.
+
+define <2 x i32> @add_splat_constant(<2 x i32> %x) {
+; CHECK-LABEL: @add_splat_constant(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 42, i32 poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = add <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @sub_splat_constant0(<2 x i32> %x) {
+; CHECK-LABEL: @sub_splat_constant0(
+; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i32> <i32 42, i32 poison>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = sub <2 x i32> <i32 42, i32 42>, %splat
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @sub_splat_constant1(<2 x i32> %x) {
+; CHECK-LABEL: @sub_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 -42, i32 poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = sub <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @mul_splat_constant(<2 x i32> %x) {
+; CHECK-LABEL: @mul_splat_constant(
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <2 x i32> [[X:%.*]], <i32 42, i32 poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = mul <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @shl_splat_constant0(<2 x i32> %x) {
+; CHECK-LABEL: @shl_splat_constant0(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> <i32 5, i32 undef>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = shl <2 x i32> <i32 5, i32 5>, %splat
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @shl_splat_constant1(<2 x i32> %x) {
+; CHECK-LABEL: @shl_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 5, i32 0>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = shl <2 x i32> %splat, <i32 5, i32 5>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @ashr_splat_constant0(<2 x i32> %x) {
+; CHECK-LABEL: @ashr_splat_constant0(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> <i32 5, i32 undef>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = ashr <2 x i32> <i32 5, i32 5>, %splat
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @ashr_splat_constant1(<2 x i32> %x) {
+; CHECK-LABEL: @ashr_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 5, i32 0>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = ashr <2 x i32> %splat, <i32 5, i32 5>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @lshr_splat_constant0(<2 x i32> %x) {
+; CHECK-LABEL: @lshr_splat_constant0(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> <i32 5, i32 undef>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = lshr <2 x i32> <i32 5, i32 5>, %splat
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @lshr_splat_constant1(<2 x i32> %x) {
+; CHECK-LABEL: @lshr_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 5, i32 0>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = lshr <2 x i32> %splat, <i32 5, i32 5>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @urem_splat_constant0(<2 x i32> %x) {
+; CHECK-LABEL: @urem_splat_constant0(
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = urem <2 x i32> <i32 42, i32 42>, [[SPLAT]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = urem <2 x i32> <i32 42, i32 42>, %splat
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @urem_splat_constant1(<2 x i32> %x) {
+; CHECK-LABEL: @urem_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = urem <2 x i32> [[X:%.*]], <i32 42, i32 1>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = urem <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @srem_splat_constant0(<2 x i32> %x) {
+; CHECK-LABEL: @srem_splat_constant0(
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = srem <2 x i32> <i32 42, i32 42>, [[SPLAT]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = srem <2 x i32> <i32 42, i32 42>, %splat
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @srem_splat_constant1(<2 x i32> %x) {
+; CHECK-LABEL: @srem_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = srem <2 x i32> [[X:%.*]], <i32 42, i32 1>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = srem <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @udiv_splat_constant0(<2 x i32> %x) {
+; CHECK-LABEL: @udiv_splat_constant0(
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = udiv <2 x i32> <i32 42, i32 42>, [[SPLAT]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = udiv <2 x i32> <i32 42, i32 42>, %splat
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @udiv_splat_constant1(<2 x i32> %x) {
+; CHECK-LABEL: @udiv_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = udiv <2 x i32> [[X:%.*]], <i32 42, i32 1>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = udiv <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @sdiv_splat_constant0(<2 x i32> %x) {
+; CHECK-LABEL: @sdiv_splat_constant0(
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = sdiv <2 x i32> <i32 42, i32 42>, [[SPLAT]]
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = sdiv <2 x i32> <i32 42, i32 42>, %splat
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @sdiv_splat_constant1(<2 x i32> %x) {
+; CHECK-LABEL: @sdiv_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = sdiv <2 x i32> [[X:%.*]], <i32 42, i32 1>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = sdiv <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @and_splat_constant(<2 x i32> %x) {
+; CHECK-LABEL: @and_splat_constant(
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 42, i32 poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = and <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+; AND does not fold to undef for undef operands, we cannot move it
+; across a shuffle with undef masks.
+define <4 x i16> @and_constant_mask_undef(<4 x i16> %add) {
+; CHECK-LABEL: @and_constant_mask_undef(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[ADD:%.*]], <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
+; CHECK-NEXT:    [[AND:%.*]] = and <4 x i16> [[SHUFFLE]], <i16 0, i16 0, i16 -1, i16 -1>
+; CHECK-NEXT:    ret <4 x i16> [[AND]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %add, <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
+  %and = and <4 x i16> %shuffle, <i16 0, i16 0, i16 -1, i16 -1>
+  ret <4 x i16> %and
+}
+
+; AND does not fold to undef for undef operands, we cannot move it
+; across a shuffle with undef masks.
+define <4 x i16> @and_constant_mask_undef_2(<4 x i16> %add) {
+; CHECK-LABEL: @and_constant_mask_undef_2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[ADD:%.*]], <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 undef>
+; CHECK-NEXT:    [[AND:%.*]] = and <4 x i16> [[SHUFFLE]], <i16 -1, i16 -1, i16 -1, i16 0>
+; CHECK-NEXT:    ret <4 x i16> [[AND]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %add, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 undef>
+  %and = and <4 x i16> %shuffle, <i16 -1, i16 -1, i16 -1, i16 -0>
+  ret <4 x i16> %and
+}
+
+; We can move the AND across the shuffle, as -1 (AND identity value) is used for undef lanes.
+define <4 x i16> @and_constant_mask_undef_3(<4 x i16> %add) {
+; CHECK-LABEL: @and_constant_mask_undef_3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i16> <i16 0, i16 0, i16 0, i16 undef>
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %add, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 undef>
+  %and = and <4 x i16> %shuffle, <i16 0, i16 0, i16 0, i16 -1>
+  ret <4 x i16> %and
+}
+
+; We can move the AND across the shuffle, as -1 (AND identity value) is used for undef lanes.
+define <4 x i16> @and_constant_mask_undef_4(<4 x i16> %add) {
+; CHECK-LABEL: @and_constant_mask_undef_4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = and <4 x i16> [[ADD:%.*]], <i16 9, i16 20, i16 poison, i16 poison>
+; CHECK-NEXT:    [[AND:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 undef>
+; CHECK-NEXT:    ret <4 x i16> [[AND]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %add, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 undef>
+  %and = and <4 x i16> %shuffle, <i16 9, i16 20, i16 20, i16 -1>
+  ret <4 x i16> %and
+}
+
+define <4 x i16> @and_constant_mask_not_undef(<4 x i16> %add) {
+; CHECK-LABEL: @and_constant_mask_not_undef(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = and <4 x i16> [[ADD:%.*]], <i16 poison, i16 -1, i16 0, i16 0>
+; CHECK-NEXT:    [[AND:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 1>
+; CHECK-NEXT:    ret <4 x i16> [[AND]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %add, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 1>
+  %and = and <4 x i16> %shuffle, <i16 0, i16 0, i16 -1, i16 -1>
+  ret <4 x i16> %and
+}
+
+; OR does not fold to undef for undef operands, we cannot move it
+; across a shuffle with undef masks.
+define <4 x i16> @or_constant_mask_undef(<4 x i16> %in) {
+; CHECK-LABEL: @or_constant_mask_undef(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
+; CHECK-NEXT:    [[OR:%.*]] = or <4 x i16> [[SHUFFLE]], <i16 -1, i16 -1, i16 0, i16 0>
+; CHECK-NEXT:    ret <4 x i16> [[OR]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
+  %or = or <4 x i16> %shuffle, <i16 -1, i16 -1, i16 0, i16 0>
+  ret <4 x i16> %or
+}
+
+; OR does not fold to undef for undef operands, we cannot move it
+; across a shuffle with undef masks.
+define <4 x i16> @or_constant_mask_undef_2(<4 x i16> %in) {
+; CHECK-LABEL: @or_constant_mask_undef_2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
+; CHECK-NEXT:    [[OR:%.*]] = or <4 x i16> [[SHUFFLE]], <i16 -1, i16 0, i16 0, i16 -1>
+; CHECK-NEXT:    ret <4 x i16> [[OR]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
+  %or = or <4 x i16> %shuffle, <i16 -1, i16 0, i16 0, i16 -1>
+  ret <4 x i16> %or
+}
+
+; We can move the OR across the shuffle, as 0 (OR identity value) is used for undef lanes.
+define <4 x i16> @or_constant_mask_undef_3(<4 x i16> %in) {
+; CHECK-LABEL: @or_constant_mask_undef_3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    ret <4 x i16> <i16 undef, i16 -1, i16 -1, i16 undef>
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
+  %or = or <4 x i16> %shuffle, <i16 0, i16 -1, i16 -1, i16 0>
+  ret <4 x i16> %or
+}
+
+; We can move the OR across the shuffle, as 0 (OR identity value) is used for undef lanes.
+define <4 x i16> @or_constant_mask_undef_4(<4 x i16> %in) {
+; CHECK-LABEL: @or_constant_mask_undef_4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = or <4 x i16> [[IN:%.*]], <i16 poison, i16 99, i16 poison, i16 poison>
+; CHECK-NEXT:    [[OR:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
+; CHECK-NEXT:    ret <4 x i16> [[OR]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
+  %or = or <4 x i16> %shuffle, <i16 0, i16 99, i16 99, i16 0>
+  ret <4 x i16> %or
+}
+
+define <4 x i16> @or_constant_mask_not_undef(<4 x i16> %in) {
+; CHECK-LABEL: @or_constant_mask_not_undef(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = or <4 x i16> [[IN:%.*]], <i16 poison, i16 -1, i16 0, i16 0>
+; CHECK-NEXT:    [[AND:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 1>
+; CHECK-NEXT:    ret <4 x i16> [[AND]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 1>
+  %and = or <4 x i16> %shuffle, <i16 0, i16 0, i16 -1, i16 -1>
+  ret <4 x i16> %and
+}
+
+define <4 x i16> @shl_constant_mask_undef(<4 x i16> %in) {
+; CHECK-LABEL: @shl_constant_mask_undef(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 1>
+; CHECK-NEXT:    [[SHL:%.*]] = shl <4 x i16> [[SHUFFLE]], <i16 10, i16 3, i16 0, i16 0>
+; CHECK-NEXT:    ret <4 x i16> [[SHL]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 1>
+  %shl = shl <4 x i16> %shuffle, <i16 10, i16 3, i16 0, i16 0>
+  ret <4 x i16> %shl
+}
+
+define <4 x i16> @add_constant_mask_undef(<4 x i16> %in) {
+; CHECK-LABEL: @add_constant_mask_undef(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[ADD:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
+; CHECK-NEXT:    ret <4 x i16> [[ADD]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
+  %add = add <4 x i16> %shuffle, <i16 10, i16 3, i16 0, i16 0>
+  ret <4 x i16> %add
+}
+
+define <4 x i16> @add_constant_mask_undef_2(<4 x i16> %in) {
+; CHECK-LABEL: @add_constant_mask_undef_2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = add <4 x i16> [[IN:%.*]], <i16 poison, i16 0, i16 3, i16 poison>
+; CHECK-NEXT:    [[ADD:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 1>
+; CHECK-NEXT:    ret <4 x i16> [[ADD]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 1>
+  %add = add <4 x i16> %shuffle, <i16 10, i16 3, i16 0, i16 0>
+  ret <4 x i16> %add
+}
+
+define <4 x i16> @sub_constant_mask_undef(<4 x i16> %in) {
+; CHECK-LABEL: @sub_constant_mask_undef(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SUB:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
+; CHECK-NEXT:    ret <4 x i16> [[SUB]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
+  %sub = sub <4 x i16> %shuffle, <i16 10, i16 3, i16 0, i16 0>
+  ret <4 x i16> %sub
+}
+
+define <4 x i16> @sub_constant_mask_undef_2(<4 x i16> %in) {
+; CHECK-LABEL: @sub_constant_mask_undef_2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = add <4 x i16> [[IN:%.*]], <i16 poison, i16 0, i16 -10, i16 poison>
+; CHECK-NEXT:    [[SUB:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 undef>
+; CHECK-NEXT:    ret <4 x i16> [[SUB]]
+;
+entry:
+  %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 undef>
+  %sub = sub <4 x i16> %shuffle, <i16 0, i16 0, i16 10, i16 99>
+  ret <4 x i16> %sub
+}
+
+define <2 x i32> @or_splat_constant(<2 x i32> %x) {
+; CHECK-LABEL: @or_splat_constant(
+; CHECK-NEXT:    [[TMP1:%.*]] = or <2 x i32> [[X:%.*]], <i32 42, i32 poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = or <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+define <2 x i32> @xor_splat_constant(<2 x i32> %x) {
+; CHECK-LABEL: @xor_splat_constant(
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i32> [[X:%.*]], <i32 42, i32 poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32> [[R]]
+;
+  %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
+  %r = xor <2 x i32> %splat, <i32 42, i32 42>
+  ret <2 x i32> %r
+}
+
+define <2 x float> @fadd_splat_constant(<2 x float> %x) {
+; CHECK-LABEL: @fadd_splat_constant(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %r = fadd <2 x float> %splat, <float 42.0, float 42.0>
+  ret <2 x float> %r
+}
+
+define <2 x float> @fsub_splat_constant0(<2 x float> %x) {
+; CHECK-LABEL: @fsub_splat_constant0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %r = fsub <2 x float> <float 42.0, float 42.0>, %splat
+  ret <2 x float> %r
+}
+
+define <2 x float> @fsub_splat_constant1(<2 x float> %x) {
+; CHECK-LABEL: @fsub_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x float> [[X:%.*]], <float -4.200000e+01, float poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %r = fsub <2 x float> %splat, <float 42.0, float 42.0>
+  ret <2 x float> %r
+}
+
+define <2 x float> @fneg(<2 x float> %x) {
+; CHECK-LABEL: @fneg(
+; CHECK-NEXT:    [[TMP1:%.*]] = fneg <2 x float> [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %r = fsub <2 x float> <float -0.0, float -0.0>, %splat
+  ret <2 x float> %r
+}
+
+define <2 x float> @fmul_splat_constant(<2 x float> %x) {
+; CHECK-LABEL: @fmul_splat_constant(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %r = fmul <2 x float> %splat, <float 42.0, float 42.0>
+  ret <2 x float> %r
+}
+
+define <2 x float> @fdiv_splat_constant0(<2 x float> %x) {
+; CHECK-LABEL: @fdiv_splat_constant0(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %r = fdiv <2 x float> <float 42.0, float 42.0>, %splat
+  ret <2 x float> %r
+}
+
+define <2 x float> @fdiv_splat_constant1(<2 x float> %x) {
+; CHECK-LABEL: @fdiv_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %r = fdiv <2 x float> %splat, <float 42.0, float 42.0>
+  ret <2 x float> %r
+}
+
+define <2 x float> @frem_splat_constant0(<2 x float> %x) {
+; CHECK-LABEL: @frem_splat_constant0(
+; CHECK-NEXT:    [[TMP1:%.*]] = frem <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %r = frem <2 x float> <float 42.0, float 42.0>, %splat
+  ret <2 x float> %r
+}
+
+define <2 x float> @frem_splat_constant1(<2 x float> %x) {
+; CHECK-LABEL: @frem_splat_constant1(
+; CHECK-NEXT:    [[TMP1:%.*]] = frem <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %r = frem <2 x float> %splat, <float 42.0, float 42.0>
+  ret <2 x float> %r
+}
+
+; Equivalent shuffle masks, but only one is a narrowing op.
+
+define <2 x i1> @PR40734(<1 x i1> %x, <4 x i1> %y) {
+; CHECK-LABEL: @PR40734(
+; CHECK-NEXT:    [[WIDEN:%.*]] = shufflevector <1 x i1> zeroinitializer, <1 x i1> [[X:%.*]], <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT:    [[NARROW:%.*]] = shufflevector <4 x i1> [[Y:%.*]], <4 x i1> undef, <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i1> [[WIDEN]], [[NARROW]]
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %widen = shufflevector <1 x i1> zeroinitializer, <1 x i1> %x, <2 x i32> <i32 0, i32 1>
+  %narrow = shufflevector <4 x i1> %y, <4 x i1> undef, <2 x i32> <i32 0, i32 1>
+  %r = and <2 x i1> %widen, %narrow
+  ret <2 x i1> %r
+}
+
+; Negative test - do not transform non-power-of-2 unless we know the backend handles these sequences identically.
+
+define <7 x i8> @insert_subvector_shuffles(<3 x i8> %x, <3 x i8> %y) {
+; CHECK-LABEL: @insert_subvector_shuffles(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <7 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <3 x i8> [[Y:%.*]], <3 x i8> undef, <7 x i32> <i32 undef, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[S3:%.*]] = shufflevector <7 x i8> [[S1]], <7 x i8> [[S2]], <7 x i32> <i32 0, i32 8, i32 1, i32 undef, i32 8, i32 1, i32 9>
+; CHECK-NEXT:    ret <7 x i8> [[S3]]
+;
+  %s1 = shufflevector <3 x i8> %x, <3 x i8> undef, <7 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %s2 = shufflevector <3 x i8> %y, <3 x i8> undef, <7 x i32> <i32 undef, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef>
+  %s3 = shufflevector <7 x i8> %s1, <7 x i8> %s2, <7 x i32> <i32 0, i32 8, i32 1, i32 undef, i32 8, i32 1, i32 9>
+  ret <7 x i8> %s3
+}
+
+define <8 x i8> @insert_subvector_shuffles_pow2elts(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @insert_subvector_shuffles_pow2elts(
+; CHECK-NEXT:    [[S3:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]], <8 x i32> <i32 0, i32 2, i32 1, i32 undef, i32 2, i32 1, i32 3, i32 0>
+; CHECK-NEXT:    ret <8 x i8> [[S3]]
+;
+  %s1 = shufflevector <2 x i8> %x, <2 x i8> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %s2 = shufflevector <2 x i8> %y, <2 x i8> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %s3 = shufflevector <8 x i8> %s1, <8 x i8> %s2, <8 x i32> <i32 0, i32 8, i32 1, i32 undef, i32 8, i32 1, i32 9, i32 0>
+  ret <8 x i8> %s3
+}
+
+; The last shuffle may change the vector type.
+; Negative test - do not transform non-power-of-2 unless we know the backend handles these sequences identically.
+
+define <2 x i8> @insert_subvector_shuffles_narrowing(<3 x i8> %x, <3 x i8> %y) {
+; CHECK-LABEL: @insert_subvector_shuffles_narrowing(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <7 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <3 x i8> [[Y:%.*]], <3 x i8> undef, <7 x i32> <i32 undef, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[S3:%.*]] = shufflevector <7 x i8> [[S1]], <7 x i8> [[S2]], <2 x i32> <i32 0, i32 8>
+; CHECK-NEXT:    ret <2 x i8> [[S3]]
+;
+  %s1 = shufflevector <3 x i8> %x, <3 x i8> undef, <7 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %s2 = shufflevector <3 x i8> %y, <3 x i8> undef, <7 x i32> <i32 undef, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef>
+  %s3 = shufflevector <7 x i8> %s1, <7 x i8> %s2, <2 x i32> <i32 0, i32 8>
+  ret <2 x i8> %s3
+}
+
+define <2 x i8> @insert_subvector_shuffles_narrowing_pow2elts(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @insert_subvector_shuffles_narrowing_pow2elts(
+; CHECK-NEXT:    [[S3:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]], <2 x i32> <i32 0, i32 4>
+; CHECK-NEXT:    ret <2 x i8> [[S3]]
+;
+  %s1 = shufflevector <4 x i8> %x, <4 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %s2 = shufflevector <4 x i8> %y, <4 x i8> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
+  %s3 = shufflevector <8 x i8> %s1, <8 x i8> %s2, <2 x i32> <i32 0, i32 8>
+  ret <2 x i8> %s3
+}
+
+; Similar to above, but this reduces to a widen with undefs of 'x'.
+
+define <4 x double> @insert_subvector_shuffles_identity(<2 x double> %x) {
+; CHECK-LABEL: @insert_subvector_shuffles_identity(
+; CHECK-NEXT:    [[S3:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x double> [[S3]]
+;
+  %s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef>
+  %s2 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+  %s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
+  ret <4 x double> %s3
+}
+
+; Negative test - not identity with padding (although this could be folded with better analysis).
+
+define <4 x double> @not_insert_subvector_shuffle(<2 x double> %x) {
+; CHECK-LABEL: @not_insert_subvector_shuffle(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <2 x double> [[X]], <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[S3:%.*]] = shufflevector <4 x double> [[S2]], <4 x double> [[S1]], <4 x i32> <i32 0, i32 5, i32 7, i32 undef>
+; CHECK-NEXT:    ret <4 x double> [[S3]]
+;
+  %s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1>
+  %s2 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+  %s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 7, i32 undef>
+  ret <4 x double> %s3
+}
+
+; Negative test - operands are not the same size (although this could be partly folded with better analysis).
+
+define <4 x double> @not_insert_subvector_shuffles_with_same_size(<2 x double> %x, <3 x double> %y) {
+; CHECK-LABEL: @not_insert_subvector_shuffles_with_same_size(
+; CHECK-NEXT:    [[S1:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[S2:%.*]] = shufflevector <3 x double> [[Y:%.*]], <3 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[S3:%.*]] = shufflevector <4 x double> [[S2]], <4 x double> [[S1]], <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x double> [[S3]]
+;
+  %s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef>
+  %s2 = shufflevector <3 x double> %y, <3 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+  %s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
+  ret <4 x double> %s3
+}
+
+; Demanded vector elements may not be able to simplify a shuffle mask
+; before we try to narrow it. This used to crash.
+
+define <4 x float> @insert_subvector_crash_invalid_mask_elt(<2 x float> %x, <4 x float>* %p) {
+; CHECK-LABEL: @insert_subvector_crash_invalid_mask_elt(
+; CHECK-NEXT:    [[WIDEN:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[I:%.*]] = shufflevector <2 x float> [[X]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    store <4 x float> [[I]], <4 x float>* [[P:%.*]], align 16
+; CHECK-NEXT:    ret <4 x float> [[WIDEN]]
+;
+  %widen = shufflevector <2 x float> %x, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+  %ext2 = extractelement <2 x float> %x, i32 0
+  %I = insertelement <4 x float> %widen, float %ext2, i16 0
+  store <4 x float> %I, <4 x float>* %p
+  ret <4 x float> %widen
+}
+
+define <4 x i32> @splat_assoc_add(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_add(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], <i32 317426, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> zeroinitializer
+  %a = add <4 x i32> %y, <i32 317426, i32 317426, i32 317426, i32 317426>
+  %r = add <4 x i32> %splatx, %a
+  ret <4 x i32> %r
+}
+
+define <vscale x 4 x i32> @vsplat_assoc_add(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) {
+; CHECK-LABEL: @vsplat_assoc_add(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <vscale x 4 x i32> [[X:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 317426, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <vscale x 4 x i32> [[TMP1]], <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = add <vscale x 4 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+
+  %splatx = shufflevector <vscale x 4 x i32> %x, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %a = add <vscale x 4 x i32> %y, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 317426, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+  %r = add <vscale x 4 x i32> %splatx, %a
+  ret <vscale x 4 x i32> %r
+}
+
+; Undefs in splat mask are replaced with defined splat index
+
+define <4 x i32> @splat_assoc_add_undef_mask_elts(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_add_undef_mask_elts(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>
+  %a = add <4 x i32> %y, <i32 42, i32 42, i32 42, i32 42>
+  %r = add <4 x i32> %splatx, %a
+  ret <4 x i32> %r
+}
+
+; Undefs in splat mask are replaced with defined splat index
+
+define <4 x i32> @splat_assoc_add_undef_mask_elt_at_splat_index(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_add_undef_mask_elt_at_splat_index(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
+  %a = add <4 x i32> %y, <i32 42, i32 42, i32 42, i32 42>
+  %r = add <4 x i32> %splatx, %a
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @splat_assoc_add_undef_constant_elts(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_add_undef_constant_elts(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 42, i32 undef, i32 undef, i32 42>
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> zeroinitializer
+  %a = add <4 x i32> %y, <i32 42, i32 undef, i32 undef, i32 42>
+  %r = add <4 x i32> %splatx, %a
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @splat_assoc_add_undef_constant_elt_at_splat_index(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_add_undef_constant_elt_at_splat_index(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 undef, i32 42, i32 undef, i32 42>
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> zeroinitializer
+  %a = add <4 x i32> %y, <i32 undef, i32 42, i32 undef, i32 42>
+  %r = add <4 x i32> %splatx, %a
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @splat_assoc_add_undef_mask_elts_undef_constant_elts(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_add_undef_mask_elts_undef_constant_elts(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 undef>
+; CHECK-NEXT:    [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 42, i32 undef, i32 undef, i32 42>
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 undef>
+  %a = add <4 x i32> %y, <i32 42, i32 undef, i32 undef, i32 42>
+  %r = add <4 x i32> %splatx, %a
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elts(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elts(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
+; CHECK-NEXT:    [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 42, i32 undef, i32 undef, i32 42>
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
+  %a = add <4 x i32> %y, <i32 42, i32 undef, i32 undef, i32 42>
+  %r = add <4 x i32> %splatx, %a
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elt_at_splat_index(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elt_at_splat_index(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
+; CHECK-NEXT:    [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 undef, i32 42, i32 undef, i32 42>
+; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
+  %a = add <4 x i32> %y, <i32 undef, i32 42, i32 undef, i32 42>
+  %r = add <4 x i32> %splatx, %a
+  ret <4 x i32> %r
+}
+
+; Non-zero splat index; commute operands; FMF intersect
+
+define <2 x float> @splat_assoc_fmul(<2 x float> %x, <2 x float> %y) {
+; CHECK-LABEL: @splat_assoc_fmul(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nsz <2 x float> [[X:%.*]], <float poison, float 3.000000e+00>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> <i32 1, i32 1>
+; CHECK-NEXT:    [[R:%.*]] = fmul reassoc nsz <2 x float> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splatx = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> <i32 1, i32 1>
+  %a = fmul reassoc nsz <2 x float> %y, <float 3.0, float 3.0>
+  %r = fmul reassoc nsz nnan <2 x float> %a, %splatx
+  ret <2 x float> %r
+}
+
+; Two splat shuffles; drop poison-generating flags
+
+define <3 x i8> @splat_assoc_mul(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) {
+; CHECK-LABEL: @splat_assoc_mul(
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <3 x i8> [[Z:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <3 x i8> [[TMP1]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+; CHECK-NEXT:    [[R:%.*]] = mul <3 x i8> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+  %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+  %a = mul nsw <3 x i8> %y, %splatz
+  %r = mul <3 x i8> %a, %splatx
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @splat_assoc_mul_undef_elt1(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) {
+; CHECK-LABEL: @splat_assoc_mul_undef_elt1(
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <3 x i8> [[Z:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <3 x i8> [[TMP1]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+; CHECK-NEXT:    [[R:%.*]] = mul <3 x i8> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 undef, i32 2, i32 2>
+  %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+  %a = mul nsw <3 x i8> %y, %splatz
+  %r = mul nsw nuw <3 x i8> %a, %splatx
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @splat_assoc_mul_undef_elt2(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) {
+; CHECK-LABEL: @splat_assoc_mul_undef_elt2(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+; CHECK-NEXT:    [[SPLATZ:%.*]] = shufflevector <3 x i8> [[Z:%.*]], <3 x i8> undef, <3 x i32> <i32 undef, i32 2, i32 2>
+; CHECK-NEXT:    [[A:%.*]] = mul nsw <3 x i8> [[SPLATZ]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = mul nuw nsw <3 x i8> [[A]], [[SPLATX]]
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+  %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 undef, i32 2, i32 2>
+  %a = mul nsw <3 x i8> %y, %splatz
+  %r = mul nsw nuw <3 x i8> %a, %splatx
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @splat_assoc_mul_undef_elt_at_splat_index1(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) {
+; CHECK-LABEL: @splat_assoc_mul_undef_elt_at_splat_index1(
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <3 x i8> [[Z:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <3 x i8> [[TMP1]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+; CHECK-NEXT:    [[R:%.*]] = mul <3 x i8> [[TMP2]], [[Y:%.*]]
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 undef>
+  %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+  %a = mul nsw <3 x i8> %y, %splatz
+  %r = mul nsw nuw <3 x i8> %a, %splatx
+  ret <3 x i8> %r
+}
+
+define <3 x i8> @splat_assoc_mul_undef_elt_at_splat_index2(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) {
+; CHECK-LABEL: @splat_assoc_mul_undef_elt_at_splat_index2(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+; CHECK-NEXT:    [[SPLATZ:%.*]] = shufflevector <3 x i8> [[Z:%.*]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 undef>
+; CHECK-NEXT:    [[A:%.*]] = mul nsw <3 x i8> [[SPLATZ]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = mul nuw nsw <3 x i8> [[A]], [[SPLATX]]
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+  %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 undef>
+  %a = mul nsw <3 x i8> %y, %splatz
+  %r = mul nsw nuw <3 x i8> %a, %splatx
+  ret <3 x i8> %r
+}
+
+; Negative test - mismatched splat elements
+
+define <3 x i8> @splat_assoc_or(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) {
+; CHECK-LABEL: @splat_assoc_or(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 1>
+; CHECK-NEXT:    [[SPLATZ:%.*]] = shufflevector <3 x i8> [[Z:%.*]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+; CHECK-NEXT:    [[A:%.*]] = or <3 x i8> [[SPLATZ]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = or <3 x i8> [[A]], [[SPLATX]]
+; CHECK-NEXT:    ret <3 x i8> [[R]]
+;
+  %splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 1>
+  %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
+  %a = or <3 x i8> %y, %splatz
+  %r = or <3 x i8> %a, %splatx
+  ret <3 x i8> %r
+}
+
+; Negative test - not associative
+
+define <2 x float> @splat_assoc_fdiv(<2 x float> %x, <2 x float> %y) {
+; CHECK-LABEL: @splat_assoc_fdiv(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[A:%.*]] = fdiv reassoc nsz <2 x float> [[Y:%.*]], <float 3.000000e+00, float 3.000000e+00>
+; CHECK-NEXT:    [[R:%.*]] = fdiv reassoc nsz <2 x float> [[A]], [[SPLATX]]
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splatx = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
+  %a = fdiv reassoc nsz <2 x float> %y, <float 3.0, float 3.0>
+  %r = fdiv reassoc nsz <2 x float> %a, %splatx
+  ret <2 x float> %r
+}
+
+; Negative test - extra use
+
+define <2 x float> @splat_assoc_fadd(<2 x float> %x, <2 x float> %y) {
+; CHECK-LABEL: @splat_assoc_fadd(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 1>
+; CHECK-NEXT:    [[A:%.*]] = fadd fast <2 x float> [[Y:%.*]], <float 3.000000e+00, float 3.000000e+00>
+; CHECK-NEXT:    call void @use(<2 x float> [[A]])
+; CHECK-NEXT:    [[R:%.*]] = fadd fast <2 x float> [[A]], [[SPLATX]]
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %splatx = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> <i32 1, i32 1>
+  %a = fadd fast <2 x float> %y, <float 3.0, float 3.0>
+  call void @use(<2 x float> %a)
+  %r = fadd fast <2 x float> %a, %splatx
+  ret <2 x float> %r
+}
+
+; Negative test - narrowing splat
+
+define <3 x i32> @splat_assoc_and(<4 x i32> %x, <3 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_and(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <3 x i32> zeroinitializer
+; CHECK-NEXT:    [[A:%.*]] = and <3 x i32> [[Y:%.*]], <i32 42, i32 42, i32 42>
+; CHECK-NEXT:    [[R:%.*]] = and <3 x i32> [[SPLATX]], [[A]]
+; CHECK-NEXT:    ret <3 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <3 x i32> zeroinitializer
+  %a = and <3 x i32> %y, <i32 42, i32 42, i32 42>
+  %r = and <3 x i32> %splatx, %a
+  ret <3 x i32> %r
+}
+
+; Negative test - widening splat
+
+define <5 x i32> @splat_assoc_xor(<4 x i32> %x, <5 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_xor(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <5 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <5 x i32> [[SPLATX]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = xor <5 x i32> [[TMP1]], <i32 42, i32 42, i32 42, i32 42, i32 42>
+; CHECK-NEXT:    ret <5 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <5 x i32> zeroinitializer
+  %a = xor <5 x i32> %y, <i32 42, i32 42, i32 42, i32 42, i32 42>
+  %r = xor <5 x i32> %splatx, %a
+  ret <5 x i32> %r
+}
+
+; Negative test - opcode mismatch
+
+define <4 x i32> @splat_assoc_add_mul(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @splat_assoc_add_mul(
+; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 42, i32 42, i32 42, i32 42>
+; CHECK-NEXT:    [[R:%.*]] = mul <4 x i32> [[SPLATX]], [[A]]
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> zeroinitializer
+  %a = add <4 x i32> %y, <i32 42, i32 42, i32 42, i32 42>
+  %r = mul <4 x i32> %splatx, %a
+  ret <4 x i32> %r
+}
+
+
+; Do not crash on constant expressions.
+
+define <4 x i32> @PR46872(<4 x i32> %x) {
+; CHECK-LABEL: @PR46872(
+; CHECK-NEXT:    [[S:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 1>
+; CHECK-NEXT:    [[A:%.*]] = and <4 x i32> [[S]], bitcast (<2 x i64> <i64 ptrtoint (<4 x i32> (<4 x i32>)* @PR46872 to i64), i64 ptrtoint (<4 x i32> (<4 x i32>)* @PR46872 to i64)> to <4 x i32>)
+; CHECK-NEXT:    ret <4 x i32> [[A]]
+;
+  %s = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 1>
+  %a = and <4 x i32> %s, bitcast (<2 x i64> <i64 ptrtoint (<4 x i32> (<4 x i32>)* @PR46872 to i64), i64 ptrtoint (<4 x i32> (<4 x i32>)* @PR46872 to i64)> to <4 x i32>)
+  ret <4 x i32> %a
+}
+
diff --git a/llvm/test/Transforms/InstCombine/vec_shuffle.ll b/llvm/test/Transforms/InstCombine/vec_shuffle.ll
index 874189d505c87..4443c3628b081 100644
--- a/llvm/test/Transforms/InstCombine/vec_shuffle.ll
+++ b/llvm/test/Transforms/InstCombine/vec_shuffle.ll
@@ -61,8 +61,8 @@ define float @test6(<4 x float> %X) {
 
 define float @testvscale6(<vscale x 4 x float> %X) {
 ; CHECK-LABEL: @testvscale6(
-; CHECK-NEXT:    [[T:%.*]] = shufflevector <vscale x 4 x float> [[X:%.*]], <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
-; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x float> [[T]], i32 0
+; CHECK-NEXT:    [[T2:%.*]] = shufflevector <vscale x 4 x float> [[X:%.*]], <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x float> [[T2]], i32 0
 ; CHECK-NEXT:    ret float [[R]]
 ;
   %X1 = bitcast <vscale x 4 x float> %X to <vscale x 4 x i32>
@@ -544,7 +544,7 @@ define <2 x float> @fadd_const_multiuse(<2 x float> %v) {
 
 define <4 x i32> @mul_const_splat(<4 x i32> %v) {
 ; CHECK-LABEL: @mul_const_splat(
-; CHECK-NEXT:    [[TMP1:%.*]] = mul <4 x i32> [[V:%.*]], <i32 undef, i32 42, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <4 x i32> [[V:%.*]], <i32 poison, i32 42, i32 poison, i32 poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
 ; CHECK-NEXT:    ret <4 x i32> [[R]]
 ;
@@ -749,8 +749,8 @@ define <8 x i8> @pr19730(<16 x i8> %in0) {
 
 define i32 @pr19737(<4 x i32> %in0) {
 ; CHECK-LABEL: @pr19737(
-; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[IN0:%.*]], i32 0
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    [[RV:%.*]] = extractelement <4 x i32> [[IN0:%.*]], i32 0
+; CHECK-NEXT:    ret i32 [[RV]]
 ;
   %shuffle.i = shufflevector <4 x i32> zeroinitializer, <4 x i32> %in0, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
   %neg.i = xor <4 x i32> %shuffle.i, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -812,7 +812,7 @@ define <2 x i32> @PR37648(<2 x i32> %x) {
 
 define <2 x i32> @add_splat_constant(<2 x i32> %x) {
 ; CHECK-LABEL: @add_splat_constant(
-; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 42, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 42, i32 poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -823,7 +823,7 @@ define <2 x i32> @add_splat_constant(<2 x i32> %x) {
 
 define <2 x i32> @sub_splat_constant0(<2 x i32> %x) {
 ; CHECK-LABEL: @sub_splat_constant0(
-; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i32> <i32 42, i32 undef>, [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i32> <i32 42, i32 poison>, [[X:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -834,7 +834,7 @@ define <2 x i32> @sub_splat_constant0(<2 x i32> %x) {
 
 define <2 x i32> @sub_splat_constant1(<2 x i32> %x) {
 ; CHECK-LABEL: @sub_splat_constant1(
-; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 -42, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 -42, i32 poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -845,7 +845,7 @@ define <2 x i32> @sub_splat_constant1(<2 x i32> %x) {
 
 define <2 x i32> @mul_splat_constant(<2 x i32> %x) {
 ; CHECK-LABEL: @mul_splat_constant(
-; CHECK-NEXT:    [[TMP1:%.*]] = mul <2 x i32> [[X:%.*]], <i32 42, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <2 x i32> [[X:%.*]], <i32 42, i32 poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -1010,7 +1010,7 @@ define <2 x i32> @sdiv_splat_constant1(<2 x i32> %x) {
 
 define <2 x i32> @and_splat_constant(<2 x i32> %x) {
 ; CHECK-LABEL: @and_splat_constant(
-; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 42, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i32> [[X:%.*]], <i32 42, i32 poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -1065,7 +1065,7 @@ entry:
 define <4 x i16> @and_constant_mask_undef_4(<4 x i16> %add) {
 ; CHECK-LABEL: @and_constant_mask_undef_4(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = and <4 x i16> [[ADD:%.*]], <i16 9, i16 20, i16 undef, i16 undef>
+; CHECK-NEXT:    [[TMP0:%.*]] = and <4 x i16> [[ADD:%.*]], <i16 9, i16 20, i16 poison, i16 poison>
 ; CHECK-NEXT:    [[AND:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[AND]]
 ;
@@ -1078,7 +1078,7 @@ entry:
 define <4 x i16> @and_constant_mask_not_undef(<4 x i16> %add) {
 ; CHECK-LABEL: @and_constant_mask_not_undef(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = and <4 x i16> [[ADD:%.*]], <i16 undef, i16 -1, i16 0, i16 0>
+; CHECK-NEXT:    [[TMP0:%.*]] = and <4 x i16> [[ADD:%.*]], <i16 poison, i16 -1, i16 0, i16 0>
 ; CHECK-NEXT:    [[AND:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 1>
 ; CHECK-NEXT:    ret <4 x i16> [[AND]]
 ;
@@ -1134,7 +1134,7 @@ entry:
 define <4 x i16> @or_constant_mask_undef_4(<4 x i16> %in) {
 ; CHECK-LABEL: @or_constant_mask_undef_4(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = or <4 x i16> [[IN:%.*]], <i16 undef, i16 99, i16 undef, i16 undef>
+; CHECK-NEXT:    [[TMP0:%.*]] = or <4 x i16> [[IN:%.*]], <i16 poison, i16 99, i16 poison, i16 poison>
 ; CHECK-NEXT:    [[OR:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[OR]]
 ;
@@ -1147,7 +1147,7 @@ entry:
 define <4 x i16> @or_constant_mask_not_undef(<4 x i16> %in) {
 ; CHECK-LABEL: @or_constant_mask_not_undef(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = or <4 x i16> [[IN:%.*]], <i16 undef, i16 -1, i16 0, i16 0>
+; CHECK-NEXT:    [[TMP0:%.*]] = or <4 x i16> [[IN:%.*]], <i16 poison, i16 -1, i16 0, i16 0>
 ; CHECK-NEXT:    [[AND:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 1>
 ; CHECK-NEXT:    ret <4 x i16> [[AND]]
 ;
@@ -1185,7 +1185,7 @@ entry:
 define <4 x i16> @add_constant_mask_undef_2(<4 x i16> %in) {
 ; CHECK-LABEL: @add_constant_mask_undef_2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = add <4 x i16> [[IN:%.*]], <i16 undef, i16 0, i16 3, i16 undef>
+; CHECK-NEXT:    [[TMP0:%.*]] = add <4 x i16> [[IN:%.*]], <i16 poison, i16 0, i16 3, i16 poison>
 ; CHECK-NEXT:    [[ADD:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 1>
 ; CHECK-NEXT:    ret <4 x i16> [[ADD]]
 ;
@@ -1210,7 +1210,7 @@ entry:
 define <4 x i16> @sub_constant_mask_undef_2(<4 x i16> %in) {
 ; CHECK-LABEL: @sub_constant_mask_undef_2(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[TMP0:%.*]] = add <4 x i16> [[IN:%.*]], <i16 undef, i16 0, i16 -10, i16 undef>
+; CHECK-NEXT:    [[TMP0:%.*]] = add <4 x i16> [[IN:%.*]], <i16 poison, i16 0, i16 -10, i16 poison>
 ; CHECK-NEXT:    [[SUB:%.*]] = shufflevector <4 x i16> [[TMP0]], <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 undef>
 ; CHECK-NEXT:    ret <4 x i16> [[SUB]]
 ;
@@ -1222,7 +1222,7 @@ entry:
 
 define <2 x i32> @or_splat_constant(<2 x i32> %x) {
 ; CHECK-LABEL: @or_splat_constant(
-; CHECK-NEXT:    [[TMP1:%.*]] = or <2 x i32> [[X:%.*]], <i32 42, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = or <2 x i32> [[X:%.*]], <i32 42, i32 poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -1233,7 +1233,7 @@ define <2 x i32> @or_splat_constant(<2 x i32> %x) {
 
 define <2 x i32> @xor_splat_constant(<2 x i32> %x) {
 ; CHECK-LABEL: @xor_splat_constant(
-; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i32> [[X:%.*]], <i32 42, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i32> [[X:%.*]], <i32 42, i32 poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
@@ -1244,7 +1244,7 @@ define <2 x i32> @xor_splat_constant(<2 x i32> %x) {
 
 define <2 x float> @fadd_splat_constant(<2 x float> %x) {
 ; CHECK-LABEL: @fadd_splat_constant(
-; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x float> [[X:%.*]], <float 4.200000e+01, float undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x float> [[R]]
 ;
@@ -1255,7 +1255,7 @@ define <2 x float> @fadd_splat_constant(<2 x float> %x) {
 
 define <2 x float> @fsub_splat_constant0(<2 x float> %x) {
 ; CHECK-LABEL: @fsub_splat_constant0(
-; CHECK-NEXT:    [[TMP1:%.*]] = fsub <2 x float> <float 4.200000e+01, float undef>, [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x float> [[R]]
 ;
@@ -1266,7 +1266,7 @@ define <2 x float> @fsub_splat_constant0(<2 x float> %x) {
 
 define <2 x float> @fsub_splat_constant1(<2 x float> %x) {
 ; CHECK-LABEL: @fsub_splat_constant1(
-; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x float> [[X:%.*]], <float -4.200000e+01, float undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x float> [[X:%.*]], <float -4.200000e+01, float poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x float> [[R]]
 ;
@@ -1288,7 +1288,7 @@ define <2 x float> @fneg(<2 x float> %x) {
 
 define <2 x float> @fmul_splat_constant(<2 x float> %x) {
 ; CHECK-LABEL: @fmul_splat_constant(
-; CHECK-NEXT:    [[TMP1:%.*]] = fmul <2 x float> [[X:%.*]], <float 4.200000e+01, float undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x float> [[R]]
 ;
@@ -1299,7 +1299,7 @@ define <2 x float> @fmul_splat_constant(<2 x float> %x) {
 
 define <2 x float> @fdiv_splat_constant0(<2 x float> %x) {
 ; CHECK-LABEL: @fdiv_splat_constant0(
-; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <2 x float> <float 4.200000e+01, float undef>, [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x float> [[R]]
 ;
@@ -1310,7 +1310,7 @@ define <2 x float> @fdiv_splat_constant0(<2 x float> %x) {
 
 define <2 x float> @fdiv_splat_constant1(<2 x float> %x) {
 ; CHECK-LABEL: @fdiv_splat_constant1(
-; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <2 x float> [[X:%.*]], <float 4.200000e+01, float undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x float> [[R]]
 ;
@@ -1321,7 +1321,7 @@ define <2 x float> @fdiv_splat_constant1(<2 x float> %x) {
 
 define <2 x float> @frem_splat_constant0(<2 x float> %x) {
 ; CHECK-LABEL: @frem_splat_constant0(
-; CHECK-NEXT:    [[TMP1:%.*]] = frem <2 x float> <float 4.200000e+01, float undef>, [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = frem <2 x float> <float 4.200000e+01, float poison>, [[X:%.*]]
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x float> [[R]]
 ;
@@ -1332,7 +1332,7 @@ define <2 x float> @frem_splat_constant0(<2 x float> %x) {
 
 define <2 x float> @frem_splat_constant1(<2 x float> %x) {
 ; CHECK-LABEL: @frem_splat_constant1(
-; CHECK-NEXT:    [[TMP1:%.*]] = frem <2 x float> [[X:%.*]], <float 4.200000e+01, float undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = frem <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
 ; CHECK-NEXT:    [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x float> [[R]]
 ;
@@ -1471,7 +1471,7 @@ define <4 x float> @insert_subvector_crash_invalid_mask_elt(<2 x float> %x, <4 x
 
 define <4 x i32> @splat_assoc_add(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @splat_assoc_add(
-; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], <i32 317426, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], <i32 317426, i32 poison, i32 poison, i32 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[TMP2]], [[Y:%.*]]
 ; CHECK-NEXT:    ret <4 x i32> [[R]]
@@ -1500,7 +1500,7 @@ define <vscale x 4 x i32> @vsplat_assoc_add(<vscale x 4 x i32> %x, <vscale x 4 x
 
 define <4 x i32> @splat_assoc_add_undef_mask_elts(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @splat_assoc_add_undef_mask_elts(
-; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 poison, i32 poison, i32 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[TMP2]], [[Y:%.*]]
 ; CHECK-NEXT:    ret <4 x i32> [[R]]
@@ -1515,7 +1515,7 @@ define <4 x i32> @splat_assoc_add_undef_mask_elts(<4 x i32> %x, <4 x i32> %y) {
 
 define <4 x i32> @splat_assoc_add_undef_mask_elt_at_splat_index(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @splat_assoc_add_undef_mask_elt_at_splat_index(
-; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], <i32 42, i32 poison, i32 poison, i32 poison>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
 ; CHECK-NEXT:    [[R:%.*]] = add <4 x i32> [[TMP2]], [[Y:%.*]]
 ; CHECK-NEXT:    ret <4 x i32> [[R]]
@@ -1595,7 +1595,7 @@ define <4 x i32> @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_e
 
 define <2 x float> @splat_assoc_fmul(<2 x float> %x, <2 x float> %y) {
 ; CHECK-LABEL: @splat_assoc_fmul(
-; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nsz <2 x float> [[X:%.*]], <float undef, float 3.000000e+00>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul reassoc nsz <2 x float> [[X:%.*]], <float poison, float 3.000000e+00>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> undef, <2 x i32> <i32 1, i32 1>
 ; CHECK-NEXT:    [[R:%.*]] = fmul reassoc nsz <2 x float> [[TMP2]], [[Y:%.*]]
 ; CHECK-NEXT:    ret <2 x float> [[R]]
@@ -1749,8 +1749,8 @@ define <3 x i32> @splat_assoc_and(<4 x i32> %x, <3 x i32> %y) {
 define <5 x i32> @splat_assoc_xor(<4 x i32> %x, <5 x i32> %y) {
 ; CHECK-LABEL: @splat_assoc_xor(
 ; CHECK-NEXT:    [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <5 x i32> zeroinitializer
-; CHECK-NEXT:    [[A:%.*]] = xor <5 x i32> [[Y:%.*]], <i32 42, i32 42, i32 42, i32 42, i32 42>
-; CHECK-NEXT:    [[R:%.*]] = xor <5 x i32> [[SPLATX]], [[A]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <5 x i32> [[SPLATX]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = xor <5 x i32> [[TMP1]], <i32 42, i32 42, i32 42, i32 42, i32 42>
 ; CHECK-NEXT:    ret <5 x i32> [[R]]
 ;
   %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <5 x i32> zeroinitializer
diff --git a/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
new file mode 100644
index 0000000000000..09497f827b9db
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
@@ -0,0 +1,413 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Can't get smaller than this.
+
+define <2 x i1> @trunc(<2 x i64> %a) {
+; CHECK-LABEL: @trunc(
+; CHECK-NEXT:    [[T:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i1>
+; CHECK-NEXT:    ret <2 x i1> [[T]]
+;
+  %t = trunc <2 x i64> %a to <2 x i1>
+  ret <2 x i1> %t
+}
+
+; This is trunc.
+
+define <2 x i1> @and_cmp_is_trunc(<2 x i64> %a) {
+; CHECK-LABEL: @and_cmp_is_trunc(
+; CHECK-NEXT:    [[R:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i1>
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %t = and <2 x i64> %a, <i64 1, i64 1>
+  %r = icmp ne <2 x i64> %t, zeroinitializer
+  ret <2 x i1> %r
+}
+
+; This is trunc.
+
+define <2 x i1> @and_cmp_is_trunc_even_with_undef_elt(<2 x i64> %a) {
+; CHECK-LABEL: @and_cmp_is_trunc_even_with_undef_elt(
+; CHECK-NEXT:    [[R:%.*]] = trunc <2 x i64> [[A:%.*]] to <2 x i1>
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %t = and <2 x i64> %a, <i64 undef, i64 1>
+  %r = icmp ne <2 x i64> %t, zeroinitializer
+  ret <2 x i1> %r
+}
+
+; TODO: This could be just 1 instruction (trunc), but our undef matching is incomplete.
+
+define <2 x i1> @and_cmp_is_trunc_even_with_undef_elts(<2 x i64> %a) {
+; CHECK-LABEL: @and_cmp_is_trunc_even_with_undef_elts(
+; CHECK-NEXT:    [[T:%.*]] = and <2 x i64> [[A:%.*]], <i64 undef, i64 1>
+; CHECK-NEXT:    [[R:%.*]] = icmp ne <2 x i64> [[T]], <i64 undef, i64 0>
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %t = and <2 x i64> %a, <i64 undef, i64 1>
+  %r = icmp ne <2 x i64> %t, <i64 undef, i64 0>
+  ret <2 x i1> %r
+}
+
+; The ashr turns into an lshr.
+define <2 x i64> @test2(<2 x i64> %a) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    [[B:%.*]] = lshr <2 x i64> [[A:%.*]], <i64 1, i64 1>
+; CHECK-NEXT:    [[TMP1:%.*]] = and <2 x i64> [[B]], <i64 32767, i64 32767>
+; CHECK-NEXT:    ret <2 x i64> [[TMP1]]
+;
+  %b = and <2 x i64> %a, <i64 65535, i64 65535>
+  %t = ashr <2 x i64> %b, <i64 1, i64 1>
+  ret <2 x i64> %t
+}
+
+define <2 x i64> @test3(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ord <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[AND:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[CONV]]
+;
+  %cmp = fcmp ord <4 x float> %a, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp4 = fcmp ord <4 x float> %b, zeroinitializer
+  %sext5 = sext <4 x i1> %cmp4 to <4 x i32>
+  %and = and <4 x i32> %sext, %sext5
+  %conv = bitcast <4 x i32> %and to <2 x i64>
+  ret <2 x i64> %conv
+}
+
+define <2 x i64> @test4(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp uno <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[OR:%.*]] = sext <4 x i1> [[TMP1]] to <4 x i32>
+; CHECK-NEXT:    [[CONV:%.*]] = bitcast <4 x i32> [[OR]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[CONV]]
+;
+  %cmp = fcmp uno <4 x float> %a, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp4 = fcmp uno <4 x float> %b, zeroinitializer
+  %sext5 = sext <4 x i1> %cmp4 to <4 x i32>
+  %or = or <4 x i32> %sext, %sext5
+  %conv = bitcast <4 x i32> %or to <2 x i64>
+  ret <2 x i64> %conv
+}
+
+; rdar://7434900
+define <2 x i64> @test5(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp ult <4 x float> [[A:%.*]], zeroinitializer
+; CHECK-NEXT:    [[CMP4:%.*]] = fcmp ult <4 x float> [[B:%.*]], zeroinitializer
+; CHECK-NEXT:    [[AND1:%.*]] = and <4 x i1> [[CMP]], [[CMP4]]
+; CHECK-NEXT:    [[AND:%.*]] = sext <4 x i1> [[AND1]] to <4 x i32>
+; CHECK-NEXT:    [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[CONV]]
+;
+  %cmp = fcmp ult <4 x float> %a, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp4 = fcmp ult <4 x float> %b, zeroinitializer
+  %sext5 = sext <4 x i1> %cmp4 to <4 x i32>
+  %and = and <4 x i32> %sext, %sext5
+  %conv = bitcast <4 x i32> %and to <2 x i64>
+  ret <2 x i64> %conv
+}
+
+define <2 x i64> @test6(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp ult <4 x float> [[A:%.*]], zeroinitializer
+; CHECK-NEXT:    [[CMP4:%.*]] = fcmp ult <4 x float> [[B:%.*]], zeroinitializer
+; CHECK-NEXT:    [[AND1:%.*]] = or <4 x i1> [[CMP]], [[CMP4]]
+; CHECK-NEXT:    [[AND:%.*]] = sext <4 x i1> [[AND1]] to <4 x i32>
+; CHECK-NEXT:    [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[CONV]]
+;
+  %cmp = fcmp ult <4 x float> %a, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp4 = fcmp ult <4 x float> %b, zeroinitializer
+  %sext5 = sext <4 x i1> %cmp4 to <4 x i32>
+  %and = or <4 x i32> %sext, %sext5
+  %conv = bitcast <4 x i32> %and to <2 x i64>
+  ret <2 x i64> %conv
+}
+
+define <2 x i64> @test7(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:    [[CMP:%.*]] = fcmp ult <4 x float> [[A:%.*]], zeroinitializer
+; CHECK-NEXT:    [[CMP4:%.*]] = fcmp ult <4 x float> [[B:%.*]], zeroinitializer
+; CHECK-NEXT:    [[AND1:%.*]] = xor <4 x i1> [[CMP]], [[CMP4]]
+; CHECK-NEXT:    [[AND:%.*]] = sext <4 x i1> [[AND1]] to <4 x i32>
+; CHECK-NEXT:    [[CONV:%.*]] = bitcast <4 x i32> [[AND]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[CONV]]
+;
+  %cmp = fcmp ult <4 x float> %a, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  %cmp4 = fcmp ult <4 x float> %b, zeroinitializer
+  %sext5 = sext <4 x i1> %cmp4 to <4 x i32>
+  %and = xor <4 x i32> %sext, %sext5
+  %conv = bitcast <4 x i32> %and to <2 x i64>
+  ret <2 x i64> %conv
+}
+
+define void @convert(<2 x i32>* %dst.addr, <2 x i64> %src) {
+; CHECK-LABEL: @convert(
+; CHECK-NEXT:    [[VAL:%.*]] = trunc <2 x i64> [[SRC:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[ADD:%.*]] = add <2 x i32> [[VAL]], <i32 1, i32 1>
+; CHECK-NEXT:    store <2 x i32> [[ADD]], <2 x i32>* [[DST_ADDR:%.*]], align 8
+; CHECK-NEXT:    ret void
+;
+  %val = trunc <2 x i64> %src to <2 x i32>
+  %add = add <2 x i32> %val, <i32 1, i32 1>
+  store <2 x i32> %add, <2 x i32>* %dst.addr
+  ret void
+}
+
+define <2 x i65> @foo(<2 x i64> %t) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:    [[A_MASK:%.*]] = and <2 x i64> [[T:%.*]], <i64 4294967295, i64 4294967295>
+; CHECK-NEXT:    [[B:%.*]] = zext <2 x i64> [[A_MASK]] to <2 x i65>
+; CHECK-NEXT:    ret <2 x i65> [[B]]
+;
+  %a = trunc <2 x i64> %t to <2 x i32>
+  %b = zext <2 x i32> %a to <2 x i65>
+  ret <2 x i65> %b
+}
+
+define <2 x i64> @bar(<2 x i65> %t) {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc <2 x i65> [[T:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[B:%.*]] = and <2 x i64> [[TMP1]], <i64 4294967295, i64 4294967295>
+; CHECK-NEXT:    ret <2 x i64> [[B]]
+;
+  %a = trunc <2 x i65> %t to <2 x i32>
+  %b = zext <2 x i32> %a to <2 x i64>
+  ret <2 x i64> %b
+}
+
+define <2 x i64> @bars(<2 x i65> %t) {
+; CHECK-LABEL: @bars(
+; CHECK-NEXT:    [[A:%.*]] = trunc <2 x i65> [[T:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[B:%.*]] = sext <2 x i32> [[A]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[B]]
+;
+  %a = trunc <2 x i65> %t to <2 x i32>
+  %b = sext <2 x i32> %a to <2 x i64>
+  ret <2 x i64> %b
+}
+
+define <2 x i64> @quxs(<2 x i64> %t) {
+; CHECK-LABEL: @quxs(
+; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i64> [[T:%.*]], <i64 32, i64 32>
+; CHECK-NEXT:    [[B:%.*]] = ashr exact <2 x i64> [[TMP1]], <i64 32, i64 32>
+; CHECK-NEXT:    ret <2 x i64> [[B]]
+;
+  %a = trunc <2 x i64> %t to <2 x i32>
+  %b = sext <2 x i32> %a to <2 x i64>
+  ret <2 x i64> %b
+}
+
+define <2 x i64> @quxt(<2 x i64> %t) {
+; CHECK-LABEL: @quxt(
+; CHECK-NEXT:    [[A:%.*]] = shl <2 x i64> [[T:%.*]], <i64 32, i64 32>
+; CHECK-NEXT:    [[B:%.*]] = ashr exact <2 x i64> [[A]], <i64 32, i64 32>
+; CHECK-NEXT:    ret <2 x i64> [[B]]
+;
+  %a = shl <2 x i64> %t, <i64 32, i64 32>
+  %b = ashr <2 x i64> %a, <i64 32, i64 32>
+  ret <2 x i64> %b
+}
+
+define <2 x double> @fa(<2 x double> %t) {
+; CHECK-LABEL: @fa(
+; CHECK-NEXT:    [[A:%.*]] = fptrunc <2 x double> [[T:%.*]] to <2 x float>
+; CHECK-NEXT:    [[B:%.*]] = fpext <2 x float> [[A]] to <2 x double>
+; CHECK-NEXT:    ret <2 x double> [[B]]
+;
+  %a = fptrunc <2 x double> %t to <2 x float>
+  %b = fpext <2 x float> %a to <2 x double>
+  ret <2 x double> %b
+}
+
+define <2 x double> @fb(<2 x double> %t) {
+; CHECK-LABEL: @fb(
+; CHECK-NEXT:    [[A:%.*]] = fptoui <2 x double> [[T:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[B:%.*]] = uitofp <2 x i64> [[A]] to <2 x double>
+; CHECK-NEXT:    ret <2 x double> [[B]]
+;
+  %a = fptoui <2 x double> %t to <2 x i64>
+  %b = uitofp <2 x i64> %a to <2 x double>
+  ret <2 x double> %b
+}
+
+define <2 x double> @fc(<2 x double> %t) {
+; CHECK-LABEL: @fc(
+; CHECK-NEXT:    [[A:%.*]] = fptosi <2 x double> [[T:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[B:%.*]] = sitofp <2 x i64> [[A]] to <2 x double>
+; CHECK-NEXT:    ret <2 x double> [[B]]
+;
+  %a = fptosi <2 x double> %t to <2 x i64>
+  %b = sitofp <2 x i64> %a to <2 x double>
+  ret <2 x double> %b
+}
+
+; PR9228
+define <4 x float> @f(i32 %a) {
+; CHECK-LABEL: @f(
+; CHECK-NEXT:    ret <4 x float> undef
+;
+  %dim = insertelement <4 x i32> poison, i32 %a, i32 0
+  %dim30 = insertelement <4 x i32> %dim, i32 %a, i32 1
+  %dim31 = insertelement <4 x i32> %dim30, i32 %a, i32 2
+  %dim32 = insertelement <4 x i32> %dim31, i32 %a, i32 3
+
+  %offset_ptr = getelementptr <4 x float>, <4 x float>* null, i32 1
+  %offset_int = ptrtoint <4 x float>* %offset_ptr to i64
+  %sizeof32 = trunc i64 %offset_int to i32
+
+  %smearinsert33 = insertelement <4 x i32> poison, i32 %sizeof32, i32 0
+  %smearinsert34 = insertelement <4 x i32> %smearinsert33, i32 %sizeof32, i32 1
+  %smearinsert35 = insertelement <4 x i32> %smearinsert34, i32 %sizeof32, i32 2
+  %smearinsert36 = insertelement <4 x i32> %smearinsert35, i32 %sizeof32, i32 3
+
+  %delta_scale = mul <4 x i32> %dim32, %smearinsert36
+  %offset_delta = add <4 x i32> zeroinitializer, %delta_scale
+
+  %offset_varying_delta = add <4 x i32> %offset_delta, undef
+
+  ret <4 x float> undef
+}
+
+define <8 x i32> @pr24458(<8 x float> %n) {
+; CHECK-LABEL: @pr24458(
+; CHECK-NEXT:    ret <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>
+;
+  %notequal_b_load_.i = fcmp une <8 x float> %n, zeroinitializer
+  %equal_a_load72_.i = fcmp ueq <8 x float> %n, zeroinitializer
+  %notequal_b_load__to_boolvec.i = sext <8 x i1> %notequal_b_load_.i to <8 x i32>
+  %equal_a_load72__to_boolvec.i = sext <8 x i1> %equal_a_load72_.i to <8 x i32>
+  %wrong = or <8 x i32> %notequal_b_load__to_boolvec.i, %equal_a_load72__to_boolvec.i
+  ret <8 x i32> %wrong
+}
+
+; Hoist a trunc to a scalar if we're inserting into an undef vector.
+; trunc (inselt undef, X, Index) --> inselt undef, (trunc X), Index
+
+define <3 x i16> @trunc_inselt_undef(i32 %x) {
+; CHECK-LABEL: @trunc_inselt_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16
+; CHECK-NEXT:    [[TRUNC:%.*]] = insertelement <3 x i16> undef, i16 [[TMP1]], i32 1
+; CHECK-NEXT:    ret <3 x i16> [[TRUNC]]
+;
+  %vec = insertelement <3 x i32> poison, i32 %x, i32 1
+  %trunc = trunc <3 x i32> %vec to <3 x i16>
+  ret <3 x i16> %trunc
+}
+
+; Hoist a trunc to a scalar if we're inserting into an undef vector.
+; trunc (inselt undef, X, Index) --> inselt undef, (trunc X), Index
+
+define <2 x float> @fptrunc_inselt_undef(double %x, i32 %index) {
+; CHECK-LABEL: @fptrunc_inselt_undef(
+; CHECK-NEXT:    [[TMP1:%.*]] = fptrunc double [[X:%.*]] to float
+; CHECK-NEXT:    [[TRUNC:%.*]] = insertelement <2 x float> undef, float [[TMP1]], i32 [[INDEX:%.*]]
+; CHECK-NEXT:    ret <2 x float> [[TRUNC]]
+;
+  %vec = insertelement <2 x double> <double undef, double undef>, double %x, i32 %index
+  %trunc = fptrunc <2 x double> %vec to <2 x float>
+  ret <2 x float> %trunc
+}
+
+; TODO: Strengthen the backend, so we can have this canonicalization.
+; Insert a scalar int into a constant vector and truncate:
+; trunc (inselt C, X, Index) --> inselt C, (trunc X), Index
+
+define <3 x i16> @trunc_inselt1(i32 %x) {
+; CHECK-LABEL: @trunc_inselt1(
+; CHECK-NEXT:    [[VEC:%.*]] = insertelement <3 x i32> <i32 3, i32 poison, i32 65536>, i32 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <3 x i32> [[VEC]] to <3 x i16>
+; CHECK-NEXT:    ret <3 x i16> [[TRUNC]]
+;
+  %vec = insertelement <3 x i32> <i32 3, i32 -2, i32 65536>, i32 %x, i32 1
+  %trunc = trunc <3 x i32> %vec to <3 x i16>
+  ret <3 x i16> %trunc
+}
+
+; TODO: Strengthen the backend, so we can have this canonicalization.
+; Insert a scalar FP into a constant vector and FP truncate:
+; fptrunc (inselt C, X, Index) --> inselt C, (fptrunc X), Index
+
+define <2 x float> @fptrunc_inselt1(double %x, i32 %index) {
+; CHECK-LABEL: @fptrunc_inselt1(
+; CHECK-NEXT:    [[VEC:%.*]] = insertelement <2 x double> <double undef, double 3.000000e+00>, double [[X:%.*]], i32 [[INDEX:%.*]]
+; CHECK-NEXT:    [[TRUNC:%.*]] = fptrunc <2 x double> [[VEC]] to <2 x float>
+; CHECK-NEXT:    ret <2 x float> [[TRUNC]]
+;
+  %vec = insertelement <2 x double> <double undef, double 3.0>, double %x, i32 %index
+  %trunc = fptrunc <2 x double> %vec to <2 x float>
+  ret <2 x float> %trunc
+}
+
+; TODO: Strengthen the backend, so we can have this canonicalization.
+; Insert a scalar int constant into a vector and truncate:
+; trunc (inselt X, C, Index) --> inselt (trunc X), C', Index
+
+define <8 x i16> @trunc_inselt2(<8 x i32> %x, i32 %index) {
+; CHECK-LABEL: @trunc_inselt2(
+; CHECK-NEXT:    [[VEC:%.*]] = insertelement <8 x i32> [[X:%.*]], i32 1048576, i32 [[INDEX:%.*]]
+; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <8 x i32> [[VEC]] to <8 x i16>
+; CHECK-NEXT:    ret <8 x i16> [[TRUNC]]
+;
+  %vec = insertelement <8 x i32> %x, i32 1048576, i32 %index
+  %trunc = trunc <8 x i32> %vec to <8 x i16>
+  ret <8 x i16> %trunc
+}
+
+; TODO: Strengthen the backend, so we can have this canonicalization.
+; Insert a scalar FP constant into a vector and FP truncate:
+; fptrunc (inselt X, C, Index) --> inselt (fptrunc X), C', Index
+
+define <3 x float> @fptrunc_inselt2(<3 x double> %x) {
+; CHECK-LABEL: @fptrunc_inselt2(
+; CHECK-NEXT:    [[VEC:%.*]] = insertelement <3 x double> [[X:%.*]], double 4.000000e+00, i32 2
+; CHECK-NEXT:    [[TRUNC:%.*]] = fptrunc <3 x double> [[VEC]] to <3 x float>
+; CHECK-NEXT:    ret <3 x float> [[TRUNC]]
+;
+  %vec = insertelement <3 x double> %x, double 4.0, i32 2
+  %trunc = fptrunc <3 x double> %vec to <3 x float>
+  ret <3 x float> %trunc
+}
+
+; Converting to a wide type might reduce instruction count,
+; but we can not do that unless the backend can recover from
+; the creation of a potentially illegal op (like a 64-bit vmul).
+; PR40032 - https://bugs.llvm.org/show_bug.cgi?id=40032
+
+define <2 x i64> @sext_less_casting_with_wideop(<2 x i64> %x, <2 x i64> %y) {
+; CHECK-LABEL: @sext_less_casting_with_wideop(
+; CHECK-NEXT:    [[XNARROW:%.*]] = trunc <2 x i64> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[YNARROW:%.*]] = trunc <2 x i64> [[Y:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[MUL:%.*]] = mul <2 x i32> [[XNARROW]], [[YNARROW]]
+; CHECK-NEXT:    [[R:%.*]] = sext <2 x i32> [[MUL]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[R]]
+;
+  %xnarrow = trunc <2 x i64> %x to <2 x i32>
+  %ynarrow = trunc <2 x i64> %y to <2 x i32>
+  %mul = mul <2 x i32> %xnarrow, %ynarrow
+  %r = sext <2 x i32> %mul to <2 x i64>
+  ret <2 x i64> %r
+}
+
+define <2 x i64> @zext_less_casting_with_wideop(<2 x i64> %x, <2 x i64> %y) {
+; CHECK-LABEL: @zext_less_casting_with_wideop(
+; CHECK-NEXT:    [[XNARROW:%.*]] = trunc <2 x i64> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[YNARROW:%.*]] = trunc <2 x i64> [[Y:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[MUL:%.*]] = mul <2 x i32> [[XNARROW]], [[YNARROW]]
+; CHECK-NEXT:    [[R:%.*]] = zext <2 x i32> [[MUL]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[R]]
+;
+  %xnarrow = trunc <2 x i64> %x to <2 x i32>
+  %ynarrow = trunc <2 x i64> %y to <2 x i32>
+  %mul = mul <2 x i32> %xnarrow, %ynarrow
+  %r = zext <2 x i32> %mul to <2 x i64>
+  ret <2 x i64> %r
+}
+
diff --git a/llvm/test/Transforms/InstCombine/vector-casts.ll b/llvm/test/Transforms/InstCombine/vector-casts.ll
index d2acefc0fbfde..308ca141ac6da 100644
--- a/llvm/test/Transforms/InstCombine/vector-casts.ll
+++ b/llvm/test/Transforms/InstCombine/vector-casts.ll
@@ -322,7 +322,7 @@ define <2 x float> @fptrunc_inselt_undef(double %x, i32 %index) {
 
 define <3 x i16> @trunc_inselt1(i32 %x) {
 ; CHECK-LABEL: @trunc_inselt1(
-; CHECK-NEXT:    [[VEC:%.*]] = insertelement <3 x i32> <i32 3, i32 undef, i32 65536>, i32 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[VEC:%.*]] = insertelement <3 x i32> <i32 3, i32 poison, i32 65536>, i32 [[X:%.*]], i32 1
 ; CHECK-NEXT:    [[TRUNC:%.*]] = trunc <3 x i32> [[VEC]] to <3 x i16>
 ; CHECK-NEXT:    ret <3 x i16> [[TRUNC]]
 ;
diff --git a/llvm/test/Transforms/InstCombine/vector_gep1-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vector_gep1-inseltpoison.ll
new file mode 100644
index 0000000000000..29c4471183d30
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vector_gep1-inseltpoison.ll
@@ -0,0 +1,74 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+@G1 = global i8 zeroinitializer
+
+define <2 x i1> @test(<2 x i8*> %a, <2 x i8*> %b) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:    [[C:%.*]] = icmp eq <2 x i8*> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    ret <2 x i1> [[C]]
+;
+  %c = icmp eq <2 x i8*> %a, %b
+  ret <2 x i1> %c
+}
+
+define <2 x i1> @test2(<2 x i8*> %a) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    ret <2 x i1> zeroinitializer
+;
+  %c = inttoptr <2 x i32> <i32 1, i32 2> to <2 x i8*>
+  %d = icmp ult <2 x i8*> %c, zeroinitializer
+  ret <2 x i1> %d
+}
+
+define <2 x i1> @test3(<2 x i8*> %a) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    ret <2 x i1> zeroinitializer
+;
+  %g = getelementptr i8, <2 x i8*> %a, <2 x i32> <i32 1, i32 0>
+  %B = icmp ult <2 x i8*> %g, zeroinitializer
+  ret <2 x i1> %B
+}
+
+define <1 x i1> @test4(<1 x i8*> %a) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    ret <1 x i1> zeroinitializer
+;
+  %g = getelementptr i8, <1 x i8*> %a, <1 x i32> <i32 1>
+  %B = icmp ult <1 x i8*> %g, zeroinitializer
+  ret <1 x i1> %B
+}
+
+define <2 x i1> @test5(<2 x i8*> %a) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:    ret <2 x i1> zeroinitializer
+;
+  %w = getelementptr i8, <2 x i8*> %a, <2 x i32> zeroinitializer
+  %e = getelementptr i8, <2 x i8*> %w, <2 x i32> <i32 5, i32 9>
+  %g = getelementptr i8, <2 x i8*> %e, <2 x i32> <i32 1, i32 0>
+  %B = icmp ult <2 x i8*> %g, zeroinitializer
+  ret <2 x i1> %B
+}
+
+define <2 x i32*> @test7(<2 x {i32, i32}*> %a) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:    [[W:%.*]] = getelementptr { i32, i32 }, <2 x { i32, i32 }*> [[A:%.*]], <2 x i64> <i64 5, i64 9>, <2 x i32> zeroinitializer
+; CHECK-NEXT:    ret <2 x i32*> [[W]]
+;
+  %w = getelementptr {i32, i32}, <2 x {i32, i32}*> %a, <2 x i32> <i32 5, i32 9>, <2 x i32> zeroinitializer
+  ret <2 x i32*> %w
+}
+
+define <vscale x 2 x i1> @test8() {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT:    ret <vscale x 2 x i1> icmp ult (<vscale x 2 x i64> zext (<vscale x 2 x i32> shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 1, i32 0), <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer) to <vscale x 2 x i64>), <vscale x 2 x i64> zeroinitializer)
+;
+  %ins = insertelement <vscale x 2 x i32> poison, i32 1, i32 0
+  %b = shufflevector <vscale x 2 x i32> %ins, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %c = inttoptr <vscale x 2 x i32> %b to <vscale x 2 x i8*>
+  %d = icmp ult <vscale x 2 x i8*> %c, zeroinitializer
+  ret <vscale x 2 x i1> %d
+}
diff --git a/llvm/test/Transforms/InstCombine/vector_insertelt_shuffle-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vector_insertelt_shuffle-inseltpoison.ll
new file mode 100644
index 0000000000000..b08e4a7db1251
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vector_insertelt_shuffle-inseltpoison.ll
@@ -0,0 +1,93 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; insertelements should fold to shuffle
+define <4 x float> @foo(<4 x float> %x) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:    [[INS2:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, float 1.000000e+00, float 2.000000e+00, float poison>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT:    ret <4 x float> [[INS2]]
+;
+  %ins1 = insertelement<4 x float> %x, float 1.0, i32 1
+  %ins2 = insertelement<4 x float> %ins1, float 2.0, i32 2
+  ret <4 x float> %ins2
+}
+
+; Insert of a constant is canonicalized ahead of insert of a variable.
+
+define <4 x float> @bar(<4 x float> %x, float %a) {
+; CHECK-LABEL: @bar(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> [[X:%.*]], float 2.000000e+00, i32 2
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A:%.*]], i32 1
+; CHECK-NEXT:    ret <4 x float> [[INS2]]
+;
+  %ins1 = insertelement<4 x float> %x, float %a, i32 1
+  %ins2 = insertelement<4 x float> %ins1, float 2.0, i32 2
+  ret <4 x float> %ins2
+}
+
+define <4 x float> @baz(<4 x float> %x, i32 %a) {
+; CHECK-LABEL: @baz(
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> [[X:%.*]], float 1.000000e+00, i32 1
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 2.000000e+00, i32 [[A:%.*]]
+; CHECK-NEXT:    ret <4 x float> [[INS2]]
+;
+  %ins1 = insertelement<4 x float> %x, float 1.0, i32 1
+  %ins2 = insertelement<4 x float> %ins1, float 2.0, i32 %a
+  ret <4 x float> %ins2
+}
+
+; insertelements should fold to shuffle
+define <4 x float> @bazz(<4 x float> %x, i32 %a) {
+; CHECK-LABEL: @bazz(
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> [[X:%.*]], float 1.000000e+00, i32 3
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 5.000000e+00, i32 [[A:%.*]]
+; CHECK-NEXT:    [[INS5:%.*]] = shufflevector <4 x float> [[INS2]], <4 x float> <float poison, float 1.000000e+00, float 2.000000e+00, float poison>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT:    [[INS6:%.*]] = insertelement <4 x float> [[INS5]], float 7.000000e+00, i32 [[A]]
+; CHECK-NEXT:    ret <4 x float> [[INS6]]
+;
+  %ins1 = insertelement<4 x float> %x, float 1.0, i32 3
+  %ins2 = insertelement<4 x float> %ins1, float 5.0, i32 %a
+  %ins3 = insertelement<4 x float> %ins2, float 3.0, i32 2
+  %ins4 = insertelement<4 x float> %ins3, float 1.0, i32 1
+  %ins5 = insertelement<4 x float> %ins4, float 2.0, i32 2
+  %ins6 = insertelement<4 x float> %ins5, float 7.0, i32 %a
+  ret <4 x float> %ins6
+}
+
+; Out of bounds index folds to undef
+define <4 x float> @bazzz(<4 x float> %x) {
+; CHECK-LABEL: @bazzz(
+; CHECK-NEXT:    ret <4 x float> <float undef, float undef, float 2.000000e+00, float undef>
+;
+  %ins1 = insertelement<4 x float> %x, float 1.0, i32 5
+  %ins2 = insertelement<4 x float> %ins1, float 2.0, i32 2
+  ret <4 x float> %ins2
+}
+
+define <4 x float> @bazzzz(<4 x float> %x) {
+; CHECK-LABEL: @bazzzz(
+; CHECK-NEXT:    ret <4 x float> <float undef, float undef, float 2.000000e+00, float undef>
+;
+  %ins1 = insertelement<4 x float> %x, float 1.0, i32 undef
+  %ins2 = insertelement<4 x float> %ins1, float 2.0, i32 2
+  ret <4 x float> %ins2
+}
+
+define <4 x float> @bazzzzz() {
+; CHECK-LABEL: @bazzzzz(
+; CHECK-NEXT:    ret <4 x float> <float 1.000000e+00, float 5.000000e+00, float 1.000000e+01, float 4.000000e+00>
+;
+  %ins1 = insertelement <4 x float> insertelement (<4 x float> <float 1.0, float 2.0, float 3.0, float undef>, float 4.0, i32 3), float 5.0, i32 1
+  %ins2 = insertelement<4 x float> %ins1, float 10.0, i32 2
+  ret <4 x float> %ins2
+}
+
+define <4 x float> @bazzzzzz(<4 x float> %x, i32 %a) {
+; CHECK-LABEL: @bazzzzzz(
+; CHECK-NEXT:    ret <4 x float> <float poison, float 5.000000e+00, float undef, float 4.000000e+00>
+;
+  %ins1 = insertelement <4 x float> insertelement (<4 x float> shufflevector (<4 x float> poison, <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0> , <4 x i32> <i32 0, i32 5, i32 undef, i32 6> ), float 4.0, i32 3), float 5.0, i32 1
+  ret <4 x float> %ins1
+}
+
+
diff --git a/llvm/test/Transforms/InstCombine/vector_insertelt_shuffle.ll b/llvm/test/Transforms/InstCombine/vector_insertelt_shuffle.ll
index e5da608631937..30150af6209b2 100644
--- a/llvm/test/Transforms/InstCombine/vector_insertelt_shuffle.ll
+++ b/llvm/test/Transforms/InstCombine/vector_insertelt_shuffle.ll
@@ -4,7 +4,7 @@
 ; insertelements should fold to shuffle
 define <4 x float> @foo(<4 x float> %x) {
 ; CHECK-LABEL: @foo(
-; CHECK-NEXT:    [[INS2:%.*]] = shufflevector <4 x float> %x, <4 x float> <float undef, float 1.000000e+00, float 2.000000e+00, float undef>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT:    [[INS2:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, float 1.000000e+00, float 2.000000e+00, float poison>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
 ; CHECK-NEXT:    ret <4 x float> [[INS2]]
 ;
   %ins1 = insertelement<4 x float> %x, float 1.0, i32 1
@@ -16,8 +16,8 @@ define <4 x float> @foo(<4 x float> %x) {
 
 define <4 x float> @bar(<4 x float> %x, float %a) {
 ; CHECK-LABEL: @bar(
-; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> %x, float 2.000000e+00, i32 2
-; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[TMP1]], float %a, i32 1
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x float> [[X:%.*]], float 2.000000e+00, i32 2
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A:%.*]], i32 1
 ; CHECK-NEXT:    ret <4 x float> [[INS2]]
 ;
   %ins1 = insertelement<4 x float> %x, float %a, i32 1
@@ -27,8 +27,8 @@ define <4 x float> @bar(<4 x float> %x, float %a) {
 
 define <4 x float> @baz(<4 x float> %x, i32 %a) {
 ; CHECK-LABEL: @baz(
-; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> %x, float 1.000000e+00, i32 1
-; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 2.000000e+00, i32 %a
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> [[X:%.*]], float 1.000000e+00, i32 1
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 2.000000e+00, i32 [[A:%.*]]
 ; CHECK-NEXT:    ret <4 x float> [[INS2]]
 ;
   %ins1 = insertelement<4 x float> %x, float 1.0, i32 1
@@ -39,10 +39,10 @@ define <4 x float> @baz(<4 x float> %x, i32 %a) {
 ; insertelements should fold to shuffle
 define <4 x float> @bazz(<4 x float> %x, i32 %a) {
 ; CHECK-LABEL: @bazz(
-; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> %x, float 1.000000e+00, i32 3
-; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 5.000000e+00, i32 %a
-; CHECK-NEXT:    [[INS5:%.*]] = shufflevector <4 x float> [[INS2]], <4 x float> <float undef, float 1.000000e+00, float 2.000000e+00, float undef>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
-; CHECK-NEXT:    [[INS6:%.*]] = insertelement <4 x float> [[INS5]], float 7.000000e+00, i32 %a
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x float> [[X:%.*]], float 1.000000e+00, i32 3
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 5.000000e+00, i32 [[A:%.*]]
+; CHECK-NEXT:    [[INS5:%.*]] = shufflevector <4 x float> [[INS2]], <4 x float> <float poison, float 1.000000e+00, float 2.000000e+00, float poison>, <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT:    [[INS6:%.*]] = insertelement <4 x float> [[INS5]], float 7.000000e+00, i32 [[A]]
 ; CHECK-NEXT:    ret <4 x float> [[INS6]]
 ;
   %ins1 = insertelement<4 x float> %x, float 1.0, i32 3
@@ -57,7 +57,7 @@ define <4 x float> @bazz(<4 x float> %x, i32 %a) {
 ; Out of bounds index folds to undef
 define <4 x float> @bazzz(<4 x float> %x) {
 ; CHECK-LABEL: @bazzz(
-; CHECK-NEXT:   ret <4 x float> <float undef, float undef, float 2.000000e+00, float undef>
+; CHECK-NEXT:    ret <4 x float> <float undef, float undef, float 2.000000e+00, float undef>
 ;
   %ins1 = insertelement<4 x float> %x, float 1.0, i32 5
   %ins2 = insertelement<4 x float> %ins1, float 2.0, i32 2
@@ -66,7 +66,7 @@ define <4 x float> @bazzz(<4 x float> %x) {
 
 define <4 x float> @bazzzz(<4 x float> %x) {
 ; CHECK-LABEL: @bazzzz(
-; CHECK-NEXT:   ret <4 x float> <float undef, float undef, float 2.000000e+00, float undef>
+; CHECK-NEXT:    ret <4 x float> <float undef, float undef, float 2.000000e+00, float undef>
 ;
   %ins1 = insertelement<4 x float> %x, float 1.0, i32 undef
   %ins2 = insertelement<4 x float> %ins1, float 2.0, i32 2
diff --git a/llvm/test/Transforms/InstCombine/vscale_extractelement-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vscale_extractelement-inseltpoison.ll
new file mode 100644
index 0000000000000..43dc22c20cd2e
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vscale_extractelement-inseltpoison.ll
@@ -0,0 +1,185 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+define i32 @extractelement_in_range(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @extractelement_in_range(
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x i32> [[A:%.*]], i64 1
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %r = extractelement <vscale x 4 x i32> %a, i64 1
+  ret i32 %r
+}
+
+define i32 @extractelement_maybe_out_of_range(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @extractelement_maybe_out_of_range(
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x i32> [[A:%.*]], i64 4
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %r = extractelement <vscale x 4 x i32> %a, i64 4
+  ret i32 %r
+}
+
+define i32 @extractelement_bitcast(float %f) {
+; CHECK-LABEL: @extractelement_bitcast(
+; CHECK-NEXT:    [[R:%.*]] = bitcast float [[F:%.*]] to i32
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %vec_float = insertelement <vscale x 4 x float> poison, float %f, i32 0
+  %vec_int = bitcast <vscale x 4 x float> %vec_float to <vscale x 4 x i32>
+  %r = extractelement <vscale x 4 x i32> %vec_int, i32 0
+  ret i32 %r
+}
+
+define i8 @extractelement_bitcast_to_trunc(<vscale x 2 x i32> %a, i32 %x) {
+; CHECK-LABEL: @extractelement_bitcast_to_trunc(
+; CHECK-NEXT:    [[R:%.*]] = trunc i32 [[X:%.*]] to i8
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %vec = insertelement <vscale x 2 x i32> %a, i32 %x, i32 1
+  %vec_cast = bitcast <vscale x 2 x i32> %vec to <vscale x 8 x i8>
+  %r = extractelement <vscale x 8 x i8> %vec_cast, i32 4
+  ret i8 %r
+}
+
+; TODO: Instcombine could remove the insert.
+define i8 @extractelement_bitcast_wrong_insert(<vscale x 2 x i32> %a, i32 %x) {
+; CHECK-LABEL: @extractelement_bitcast_wrong_insert(
+; CHECK-NEXT:    [[VEC:%.*]] = insertelement <vscale x 2 x i32> [[A:%.*]], i32 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[VEC_CAST:%.*]] = bitcast <vscale x 2 x i32> [[VEC]] to <vscale x 8 x i8>
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 8 x i8> [[VEC_CAST]], i32 2
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %vec = insertelement <vscale x 2 x i32> %a, i32 %x, i32 1 ; <- This insert could be removed.
+  %vec_cast = bitcast <vscale x 2 x i32> %vec to <vscale x 8 x i8>
+  %r = extractelement <vscale x 8 x i8> %vec_cast, i32 2
+  ret i8 %r
+}
+
+; TODO: Instcombine could optimize to return %v.
+define i32 @extractelement_shuffle_in_range(i32 %v) {
+; CHECK-LABEL: @extractelement_shuffle_in_range(
+; CHECK-NEXT:    [[IN:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[V:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x i32> [[SPLAT]], i32 1
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %in = insertelement <vscale x 4 x i32> poison, i32 %v, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %in, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %r = extractelement <vscale x 4 x i32> %splat, i32 1
+  ret i32 %r
+}
+
+define i32 @extractelement_shuffle_maybe_out_of_range(i32 %v) {
+; CHECK-LABEL: @extractelement_shuffle_maybe_out_of_range(
+; CHECK-NEXT:    [[IN:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[V:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x i32> [[SPLAT]], i32 4
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %in = insertelement <vscale x 4 x i32> poison, i32 %v, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %in, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %r = extractelement <vscale x 4 x i32> %splat, i32 4
+  ret i32 %r
+}
+
+define i32 @extractelement_shuffle_invalid_index(i32 %v) {
+; CHECK-LABEL: @extractelement_shuffle_invalid_index(
+; CHECK-NEXT:    [[IN:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[V:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x i32> [[SPLAT]], i32 -1
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %in = insertelement <vscale x 4 x i32> poison, i32 %v, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %in, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %r = extractelement <vscale x 4 x i32> %splat, i32 -1
+  ret i32 %r
+}
+
+
+define i32 @extractelement_shuffle_symbolic_index(i32 %v, i32 %idx) {
+; CHECK-LABEL: @extractelement_shuffle_symbolic_index(
+; CHECK-NEXT:    [[IN:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[V:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x i32> [[SPLAT]], i32 [[IDX:%.*]]
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %in = insertelement <vscale x 4 x i32> poison, i32 %v, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %in, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %r = extractelement <vscale x 4 x i32> %splat, i32 %idx
+  ret i32 %r
+}
+
+define <vscale x 4 x i32> @extractelement_insertelement_same_positions(<vscale x 4 x i32> %vec) {
+; CHECK-LABEL: @extractelement_insertelement_same_positions(
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[VEC:%.*]]
+;
+  %vec.e0 = extractelement <vscale x 4 x i32> %vec, i32 0
+  %vec.e1 = extractelement <vscale x 4 x i32> %vec, i32 1
+  %vec.e2 = extractelement <vscale x 4 x i32> %vec, i32 2
+  %vec.e3 = extractelement <vscale x 4 x i32> %vec, i32 3
+  %1 = insertelement <vscale x 4 x i32> %vec, i32 %vec.e0, i32 0
+  %2 = insertelement <vscale x 4 x i32> %1, i32 %vec.e1, i32 1
+  %3 = insertelement <vscale x 4 x i32> %2, i32 %vec.e2, i32 2
+  %4 = insertelement <vscale x 4 x i32> %3, i32 %vec.e3, i32 3
+  ret <vscale x 4 x i32> %4
+}
+
+define <vscale x 4 x i32> @extractelement_insertelement_diff_positions(<vscale x 4 x i32> %vec) {
+; CHECK-LABEL: @extractelement_insertelement_diff_positions(
+; CHECK-NEXT:    [[VEC_E0:%.*]] = extractelement <vscale x 4 x i32> [[VEC:%.*]], i32 4
+; CHECK-NEXT:    [[VEC_E1:%.*]] = extractelement <vscale x 4 x i32> [[VEC]], i32 5
+; CHECK-NEXT:    [[VEC_E2:%.*]] = extractelement <vscale x 4 x i32> [[VEC]], i32 6
+; CHECK-NEXT:    [[VEC_E3:%.*]] = extractelement <vscale x 4 x i32> [[VEC]], i32 7
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <vscale x 4 x i32> [[VEC]], i32 [[VEC_E0]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <vscale x 4 x i32> [[TMP1]], i32 [[VEC_E1]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <vscale x 4 x i32> [[TMP2]], i32 [[VEC_E2]], i32 2
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <vscale x 4 x i32> [[TMP3]], i32 [[VEC_E3]], i32 3
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[TMP4]]
+;
+  %vec.e0 = extractelement <vscale x 4 x i32> %vec, i32 4
+  %vec.e1 = extractelement <vscale x 4 x i32> %vec, i32 5
+  %vec.e2 = extractelement <vscale x 4 x i32> %vec, i32 6
+  %vec.e3 = extractelement <vscale x 4 x i32> %vec, i32 7
+  %1 = insertelement <vscale x 4 x i32> %vec, i32 %vec.e0, i32 0
+  %2 = insertelement <vscale x 4 x i32> %1, i32 %vec.e1, i32 1
+  %3 = insertelement <vscale x 4 x i32> %2, i32 %vec.e2, i32 2
+  %4 = insertelement <vscale x 4 x i32> %3, i32 %vec.e3, i32 3
+  ret <vscale x 4 x i32> %4
+}
+
+define i32 @bitcast_of_extractelement( <vscale x 2 x float> %d) {
+; CHECK-LABEL: @bitcast_of_extractelement(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <vscale x 2 x float> [[D:%.*]] to <vscale x 2 x i32>
+; CHECK-NEXT:    [[CAST:%.*]] = extractelement <vscale x 2 x i32> [[BC]], i32 0
+; CHECK-NEXT:    ret i32 [[CAST]]
+;
+  %ext = extractelement <vscale x 2 x float> %d, i32 0
+  %cast = bitcast float %ext to i32
+  ret i32 %cast
+}
+
+define i1 @extractelement_is_zero(<vscale x 2 x i32> %d, i1 %b, i32 %z) {
+; CHECK-LABEL: @extractelement_is_zero(
+; CHECK-NEXT:    [[EXT:%.*]] = extractelement <vscale x 2 x i32> [[D:%.*]], i32 0
+; CHECK-NEXT:    [[BB:%.*]] = icmp eq i32 [[EXT]], 0
+; CHECK-NEXT:    ret i1 [[BB]]
+;
+  %ext = extractelement <vscale x 2 x i32> %d, i32 0
+  %bb = icmp eq i32 %ext, 0
+  ret i1 %bb
+}
+
+; OSS-Fuzz #25272
+; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=25272
+define i32 @ossfuzz_25272(float %f) {
+; CHECK-LABEL: @ossfuzz_25272(
+; CHECK-NEXT:    [[VEC_FLOAT:%.*]] = insertelement <vscale x 4 x float> poison, float [[F:%.*]], i32 0
+; CHECK-NEXT:    [[VEC_INT:%.*]] = bitcast <vscale x 4 x float> [[VEC_FLOAT]] to <vscale x 4 x i32>
+; CHECK-NEXT:    [[E:%.*]] = extractelement <vscale x 4 x i32> [[VEC_INT]], i32 2147483647
+; CHECK-NEXT:    ret i32 [[E]]
+;
+  %vec_float = insertelement <vscale x 4 x float> poison, float %f, i32 0
+  %vec_int = bitcast <vscale x 4 x float> %vec_float to <vscale x 4 x i32>
+  %E = extractelement <vscale x 4 x i32> %vec_int, i32 2147483647
+  ret i32 %E
+}
diff --git a/llvm/test/Transforms/InstCombine/vscale_insertelement-inseltpoison.ll b/llvm/test/Transforms/InstCombine/vscale_insertelement-inseltpoison.ll
new file mode 100644
index 0000000000000..252483664f9b9
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vscale_insertelement-inseltpoison.ll
@@ -0,0 +1,102 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -instcombine < %s | FileCheck %s
+
+; This test checks that bitcast is moved after insertelement when both vector and scalar are
+; bitcast from the same element type.
+; inselt (bitcast VecSrc), (bitcast ScalarSrc), IdxOp
+;  --> bitcast (inselt VecSrc, ScalarSrc, IdxOp)
+define <vscale x 4 x float> @insertelement_bitcast(<vscale x 4 x i32> %vec, i32 %x) {
+; CHECK-LABEL: @insertelement_bitcast(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <vscale x 4 x i32> [[VEC:%.*]], i32 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = bitcast <vscale x 4 x i32> [[TMP1]] to <vscale x 4 x float>
+; CHECK-NEXT:    ret <vscale x 4 x float> [[R]]
+;
+  %x_cast = bitcast i32 %x to float
+  %vec_cast = bitcast <vscale x 4 x i32> %vec to <vscale x 4 x float>
+  %r = insertelement <vscale x 4 x float> %vec_cast, float %x_cast, i32 0
+  ret <vscale x 4 x float> %r
+}
+
+; This test checks that code-path "Try to form a shuffle from a chain of extract-insert ops" is
+; not taken when both extract and insert are scalable type.
+; For scalable type, the vector length needed to create shuffle mask is not a compile-time constant.
+; Meanwhile, for scalable type shuffle mask only support splat and undef in the current code base.
+; Otherwise we crash at:
+; "Assertion `isValidOperands(V1, V2, Mask) && "Invalid shuffle vector instruction operands!"' failed."
+define <vscale x 4 x i32> @insertelement_extractelement(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
+; CHECK-LABEL: @insertelement_extractelement(
+; CHECK-NEXT:    [[T0:%.*]] = extractelement <vscale x 4 x i32> [[A:%.*]], i32 1
+; CHECK-NEXT:    [[T1:%.*]] = insertelement <vscale x 4 x i32> [[B:%.*]], i32 [[T0]], i32 0
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[T1]]
+;
+  %t0 = extractelement <vscale x 4 x i32> %a, i32 1
+  %t1 = insertelement <vscale x 4 x i32> %b, i32 %t0, i32 0
+  ret <vscale x 4 x i32> %t1
+}
+
+; This test checks that we are not attempting to create a shuffle from extract/insert chain,
+; when extract is from a scalable type, and the insert vector is fixed-length.
+define <4 x i32> @insertelement_extractelement_fixed_vec_extract_from_scalable(<vscale x 4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @insertelement_extractelement_fixed_vec_extract_from_scalable(
+; CHECK-NEXT:    [[T0:%.*]] = extractelement <vscale x 4 x i32> [[A:%.*]], i32 1
+; CHECK-NEXT:    [[T1:%.*]] = insertelement <4 x i32> [[B:%.*]], i32 [[T0]], i32 0
+; CHECK-NEXT:    ret <4 x i32> [[T1]]
+;
+  %t0 = extractelement <vscale x 4 x i32> %a, i32 1
+  %t1 = insertelement <4 x i32> %b, i32 %t0, i32 0
+  ret <4 x i32> %t1
+}
+
+; This test checks that the optimization "foldConstantInsEltInfoShuffle" is not taken for scalable type.
+; Particularly the fold:
+; insertelt (insertelt X, C1, CIndex1), C, CIndex
+;  --> shufflevector X, CVec', Mask'
+; For scalable type, the vector length needed to create shuffle mask is not a compile-time constant.
+; Meanwhile, for scalable type shuffle mask only support splat and undef in the current code base.
+; Otherwise we crash at:
+; "Assertion `isValidOperands(V1, V2, Mask) && "Invalid shuffle vector instruction operands!"' failed."
+define <vscale x 4 x i32> @insertelement_insertelement(<vscale x 4 x i32> %vec) {
+; CHECK-LABEL: @insertelement_insertelement(
+; CHECK-NEXT:    [[T0:%.*]] = insertelement <vscale x 4 x i32> [[VEC:%.*]], i32 1, i32 1
+; CHECK-NEXT:    [[T1:%.*]] = insertelement <vscale x 4 x i32> [[T0]], i32 2, i32 2
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[T1]]
+;
+  %t0 = insertelement <vscale x 4 x i32> %vec, i32 1, i32 1
+  %t1 = insertelement <vscale x 4 x i32> %t0, i32 2, i32 2
+  ret <vscale x 4 x i32> %t1
+}
+
+; This test checks that the following insertelement sequence is not folded into shuffle splat.
+; The length of scalable vector is unknown at compile-time. Therefore the following insertelements
+; may not form a valid splat.
+define <vscale x 4 x float> @insertelement_sequene_may_not_be_splat(float %x) {
+; CHECK-LABEL: @insertelement_sequene_may_not_be_splat(
+; CHECK-NEXT:    [[T0:%.*]] = insertelement <vscale x 4 x float> poison, float [[X:%.*]], i32 0
+; CHECK-NEXT:    [[T1:%.*]] = insertelement <vscale x 4 x float> [[T0]], float [[X]], i32 1
+; CHECK-NEXT:    [[T2:%.*]] = insertelement <vscale x 4 x float> [[T1]], float [[X]], i32 2
+; CHECK-NEXT:    [[T3:%.*]] = insertelement <vscale x 4 x float> [[T2]], float [[X]], i32 3
+; CHECK-NEXT:    ret <vscale x 4 x float> [[T3]]
+;
+  %t0 = insertelement <vscale x 4 x float> poison, float %x, i32 0
+  %t1 = insertelement <vscale x 4 x float> %t0, float %x, i32 1
+  %t2 = insertelement <vscale x 4 x float> %t1, float %x, i32 2
+  %t3 = insertelement <vscale x 4 x float> %t2, float %x, i32 3
+  ret <vscale x 4 x float> %t3
+}
+
+; OSS-Fuzz #27416
+; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=27416
+define void @ossfuzz_27416(i32 %v) {
+; CHECK-LABEL: @ossfuzz_27416(
+; CHECK-NEXT:    [[IN:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[V:%.*]], i32 0
+; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[IN]], <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <vscale x 4 x i32> [[SPLAT]], i32 undef, i8 -128
+; CHECK-NEXT:    store <vscale x 4 x i32> [[I1]], <vscale x 4 x i32>* undef, align 16
+; CHECK-NEXT:    ret void
+;
+  %in = insertelement <vscale x 4 x i32> poison, i32 %v, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %in, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %I1 = insertelement <vscale x 4 x i32> %splat, i32 undef, i8 -128
+  store <vscale x 4 x i32> %I1, <vscale x 4 x i32>* undef, align 16
+  ret void
+}
diff --git a/llvm/test/Transforms/InstCombine/xor2.ll b/llvm/test/Transforms/InstCombine/xor2.ll
index fe969769a0200..a8056803dd0e9 100644
--- a/llvm/test/Transforms/InstCombine/xor2.ll
+++ b/llvm/test/Transforms/InstCombine/xor2.ll
@@ -171,7 +171,11 @@ define i32 @test10b(i32 %b, i32 %c) {
 
 define i32 @test11(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test11(
-; CHECK-NEXT:    ret i32 0
+; CHECK-NEXT:    [[XOR1:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[XOR1]], [[XOR2]]
+; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %xor1 = xor i32 %B, %A
   %not = xor i32 %A, -1
@@ -182,7 +186,11 @@ define i32 @test11(i32 %A, i32 %B) {
 
 define i32 @test11b(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test11b(
-; CHECK-NEXT:    ret i32 0
+; CHECK-NEXT:    [[XOR1:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[XOR1]], [[XOR2]]
+; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %xor1 = xor i32 %B, %A
   %not = xor i32 %A, -1
@@ -194,8 +202,8 @@ define i32 @test11b(i32 %A, i32 %B) {
 define i32 @test11c(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test11c(
 ; CHECK-NEXT:    [[XOR1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A]], -1
-; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[NOT]], [[B]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[TMP1]], -1
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[XOR1]], [[XOR2]]
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
@@ -209,9 +217,9 @@ define i32 @test11c(i32 %A, i32 %B) {
 define i32 @test11d(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test11d(
 ; CHECK-NEXT:    [[XOR1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A]], -1
-; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[NOT]], [[B]]
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[XOR2]], [[XOR1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[XOR1]], [[XOR2]]
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %xor1 = xor i32 %A, %B
@@ -225,8 +233,8 @@ define i32 @test11e(i32 %A, i32 %B, i32 %C) {
 ; CHECK-LABEL: @test11e(
 ; CHECK-NEXT:    [[FORCE:%.*]] = mul i32 [[B:%.*]], [[C:%.*]]
 ; CHECK-NEXT:    [[XOR1:%.*]] = xor i32 [[FORCE]], [[A:%.*]]
-; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A]], -1
-; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[FORCE]], [[NOT]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[FORCE]], [[A]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[TMP1]], -1
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[XOR1]], [[XOR2]]
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
@@ -242,9 +250,9 @@ define i32 @test11f(i32 %A, i32 %B, i32 %C) {
 ; CHECK-LABEL: @test11f(
 ; CHECK-NEXT:    [[FORCE:%.*]] = mul i32 [[B:%.*]], [[C:%.*]]
 ; CHECK-NEXT:    [[XOR1:%.*]] = xor i32 [[FORCE]], [[A:%.*]]
-; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A]], -1
-; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[FORCE]], [[NOT]]
-; CHECK-NEXT:    [[AND:%.*]] = and i32 [[XOR2]], [[XOR1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i32 [[FORCE]], [[A]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i32 [[TMP1]], -1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[XOR1]], [[XOR2]]
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %force = mul i32 %B, %C
@@ -481,9 +489,9 @@ define i32 @xor_or_xor_common_op_extra_use3(i32 %a, i32 %b, i32 %c, i32* %p1, i3
 define i8 @test15(i8 %A, i8 %B) {
 ; CHECK-LABEL: @test15(
 ; CHECK-NEXT:    [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[NOT:%.*]] = xor i8 [[A]], 33
-; CHECK-NEXT:    [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
-; CHECK-NEXT:    [[AND:%.*]] = and i8 [[XOR1]], -34
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i8 [[TMP1]], 33
+; CHECK-NEXT:    [[AND:%.*]] = and i8 [[XOR1]], [[XOR2]]
 ; CHECK-NEXT:    [[RES:%.*]] = mul i8 [[AND]], [[XOR2]]
 ; CHECK-NEXT:    ret i8 [[RES]]
 ;
@@ -498,9 +506,9 @@ define i8 @test15(i8 %A, i8 %B) {
 define i8 @test16(i8 %A, i8 %B) {
 ; CHECK-LABEL: @test16(
 ; CHECK-NEXT:    [[XOR1:%.*]] = xor i8 [[B:%.*]], [[A:%.*]]
-; CHECK-NEXT:    [[NOT:%.*]] = xor i8 [[A]], 33
-; CHECK-NEXT:    [[XOR2:%.*]] = xor i8 [[NOT]], [[B]]
-; CHECK-NEXT:    [[AND:%.*]] = and i8 [[XOR1]], -34
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i8 [[A]], [[B]]
+; CHECK-NEXT:    [[XOR2:%.*]] = xor i8 [[TMP1]], 33
+; CHECK-NEXT:    [[AND:%.*]] = and i8 [[XOR2]], [[XOR1]]
 ; CHECK-NEXT:    [[RES:%.*]] = mul i8 [[AND]], [[XOR2]]
 ; CHECK-NEXT:    ret i8 [[RES]]
 ;
diff --git a/llvm/test/Transforms/InstSimplify/AndOrXor.ll b/llvm/test/Transforms/InstSimplify/AndOrXor.ll
index 8952acc2feb64..e23262835c3cf 100644
--- a/llvm/test/Transforms/InstSimplify/AndOrXor.ll
+++ b/llvm/test/Transforms/InstSimplify/AndOrXor.ll
@@ -885,168 +885,274 @@ define i32 @reversed_not(i32 %a) {
 
 define i64 @shl_or_and1(i32 %a, i1 %b) {
 ; CHECK-LABEL: @shl_or_and1(
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i1 [[B:%.*]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[T2:%.*]] = zext i1 [[B:%.*]] to i64
+; CHECK-NEXT:    ret i64 [[T2]]
 ;
-  %tmp1 = zext i32 %a to i64
-  %tmp2 = zext i1 %b to i64
-  %tmp3 = shl nuw i64 %tmp1, 32
-  %tmp4 = or i64 %tmp2, %tmp3
-  %tmp5 = and i64 %tmp4, 1
-  ret i64 %tmp5
+  %t1 = zext i32 %a to i64
+  %t2 = zext i1 %b to i64
+  %t3 = shl nuw i64 %t1, 32
+  %t4 = or i64 %t2, %t3
+  %t5 = and i64 %t4, 1
+  ret i64 %t5
 }
 
 define i64 @shl_or_and2(i32 %a, i1 %b) {
 ; CHECK-LABEL: @shl_or_and2(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i1 [[B:%.*]] to i64
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
-; CHECK-NEXT:    ret i64 [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = zext i1 [[B:%.*]] to i64
+; CHECK-NEXT:    [[T3:%.*]] = shl nuw i64 [[T1]], 32
+; CHECK-NEXT:    ret i64 [[T3]]
 ;
-  %tmp1 = zext i1 %b to i64
-  %tmp2 = zext i32 %a to i64
-  %tmp3 = shl nuw i64 %tmp1, 32
-  %tmp4 = or i64 %tmp2, %tmp3
-  %tmp5 = and i64 %tmp4, 4294967296
-  ret i64 %tmp5
+  %t1 = zext i1 %b to i64
+  %t2 = zext i32 %a to i64
+  %t3 = shl nuw i64 %t1, 32
+  %t4 = or i64 %t2, %t3
+  %t5 = and i64 %t4, 4294967296
+  ret i64 %t5
 }
 
 ; concatenate two 32-bit integers and extract lower 32-bit
 define i64 @shl_or_and3(i32 %a, i32 %b) {
 ; CHECK-LABEL: @shl_or_and3(
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
-; CHECK-NEXT:    ret i64 [[TMP2]]
+; CHECK-NEXT:    [[T2:%.*]] = zext i32 [[B:%.*]] to i64
+; CHECK-NEXT:    ret i64 [[T2]]
 ;
-  %tmp1 = zext i32 %a to i64
-  %tmp2 = zext i32 %b to i64
-  %tmp3 = shl nuw i64 %tmp1, 32
-  %tmp4 = or i64 %tmp2, %tmp3
-  %tmp5 = and i64 %tmp4, 4294967295
-  ret i64 %tmp5
+  %t1 = zext i32 %a to i64
+  %t2 = zext i32 %b to i64
+  %t3 = shl nuw i64 %t1, 32
+  %t4 = or i64 %t2, %t3
+  %t5 = and i64 %t4, 4294967295
+  ret i64 %t5
 }
 
 ; concatenate two 16-bit integers and extract higher 16-bit
 define i32 @shl_or_and4(i16 %a, i16 %b) {
 ; CHECK-LABEL: @shl_or_and4(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT:    [[T3:%.*]] = shl nuw i32 [[T1]], 16
+; CHECK-NEXT:    ret i32 [[T3]]
 ;
-  %tmp1 = zext i16 %a to i32
-  %tmp2 = zext i16 %b to i32
-  %tmp3 = shl nuw i32 %tmp1, 16
-  %tmp4 = or i32 %tmp2, %tmp3
-  %tmp5 = and i32 %tmp4, 4294901760 ; mask with 0xFFFF0000
-  ret i32 %tmp5
+  %t1 = zext i16 %a to i32
+  %t2 = zext i16 %b to i32
+  %t3 = shl nuw i32 %t1, 16
+  %t4 = or i32 %t2, %t3
+  %t5 = and i32 %t4, 4294901760 ; mask with 0xFFFF0000
+  ret i32 %t5
 }
 
 define i128 @shl_or_and5(i64 %a, i1 %b) {
 ; CHECK-LABEL: @shl_or_and5(
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i1 [[B:%.*]] to i128
-; CHECK-NEXT:    ret i128 [[TMP2]]
+; CHECK-NEXT:    [[T2:%.*]] = zext i1 [[B:%.*]] to i128
+; CHECK-NEXT:    ret i128 [[T2]]
 ;
-  %tmp1 = zext i64 %a to i128
-  %tmp2 = zext i1 %b to i128
-  %tmp3 = shl nuw i128 %tmp1, 64
-  %tmp4 = or i128 %tmp2, %tmp3
-  %tmp5 = and i128 %tmp4, 1
-  ret i128 %tmp5
+  %t1 = zext i64 %a to i128
+  %t2 = zext i1 %b to i128
+  %t3 = shl nuw i128 %t1, 64
+  %t4 = or i128 %t2, %t3
+  %t5 = and i128 %t4, 1
+  ret i128 %t5
 }
 
 ; A variation of above test cases; it fails due to the mask value
 define i32 @shl_or_and6(i16 %a, i16 %b) {
 ; CHECK-LABEL: @shl_or_and6(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
-; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP4]], -65535
-; CHECK-NEXT:    ret i32 [[TMP5]]
+; CHECK-NEXT:    [[T1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT:    [[T2:%.*]] = zext i16 [[B:%.*]] to i32
+; CHECK-NEXT:    [[T3:%.*]] = shl nuw i32 [[T1]], 16
+; CHECK-NEXT:    [[T4:%.*]] = or i32 [[T2]], [[T3]]
+; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], -65535
+; CHECK-NEXT:    ret i32 [[T5]]
 ;
-  %tmp1 = zext i16 %a to i32
-  %tmp2 = zext i16 %b to i32
-  %tmp3 = shl nuw i32 %tmp1, 16
-  %tmp4 = or i32 %tmp2, %tmp3
-  %tmp5 = and i32 %tmp4, 4294901761 ; mask with 0xFFFF0001
-  ret i32 %tmp5
+  %t1 = zext i16 %a to i32
+  %t2 = zext i16 %b to i32
+  %t3 = shl nuw i32 %t1, 16
+  %t4 = or i32 %t2, %t3
+  %t5 = and i32 %t4, 4294901761 ; mask with 0xFFFF0001
+  ret i32 %t5
 }
 
 ; A variation of above test cases; it fails due to the mask value
 define i32 @shl_or_and7(i16 %a, i16 %b) {
 ; CHECK-LABEL: @shl_or_and7(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
-; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP4]], -131072
-; CHECK-NEXT:    ret i32 [[TMP5]]
+; CHECK-NEXT:    [[T1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT:    [[T2:%.*]] = zext i16 [[B:%.*]] to i32
+; CHECK-NEXT:    [[T3:%.*]] = shl nuw i32 [[T1]], 16
+; CHECK-NEXT:    [[T4:%.*]] = or i32 [[T2]], [[T3]]
+; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], -131072
+; CHECK-NEXT:    ret i32 [[T5]]
 ;
-  %tmp1 = zext i16 %a to i32
-  %tmp2 = zext i16 %b to i32
-  %tmp3 = shl nuw i32 %tmp1, 16
-  %tmp4 = or i32 %tmp2, %tmp3
-  %tmp5 = and i32 %tmp4, 4294836224 ; mask with 0xFFFE0000
-  ret i32 %tmp5
+  %t1 = zext i16 %a to i32
+  %t2 = zext i16 %b to i32
+  %t3 = shl nuw i32 %t1, 16
+  %t4 = or i32 %t2, %t3
+  %t5 = and i32 %t4, 4294836224 ; mask with 0xFFFE0000
+  ret i32 %t5
 }
 
 ; A variation of above test cases; it fails due to the mask value
 define i32 @shl_or_and8(i16 %a, i16 %b) {
 ; CHECK-LABEL: @shl_or_and8(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
-; CHECK-NEXT:    [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
-; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP4]], 131071
-; CHECK-NEXT:    ret i32 [[TMP5]]
+; CHECK-NEXT:    [[T1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT:    [[T2:%.*]] = zext i16 [[B:%.*]] to i32
+; CHECK-NEXT:    [[T3:%.*]] = shl nuw i32 [[T1]], 16
+; CHECK-NEXT:    [[T4:%.*]] = or i32 [[T2]], [[T3]]
+; CHECK-NEXT:    [[T5:%.*]] = and i32 [[T4]], 131071
+; CHECK-NEXT:    ret i32 [[T5]]
 ;
-  %tmp1 = zext i16 %a to i32
-  %tmp2 = zext i16 %b to i32
-  %tmp3 = shl nuw i32 %tmp1, 16
-  %tmp4 = or i32 %tmp2, %tmp3
-  %tmp5 = and i32 %tmp4, 131071 ; mask with 0x1FFFF
-  ret i32 %tmp5
+  %t1 = zext i16 %a to i32
+  %t2 = zext i16 %b to i32
+  %t3 = shl nuw i32 %t1, 16
+  %t4 = or i32 %t2, %t3
+  %t5 = and i32 %t4, 131071 ; mask with 0x1FFFF
+  ret i32 %t5
 }
 
 define <2 x i64> @shl_or_and1v(<2 x i32> %a, <2 x i1> %b) {
 ; CHECK-LABEL: @shl_or_and1v(
-; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
-; CHECK-NEXT:    ret <2 x i64> [[TMP2]]
+; CHECK-NEXT:    [[T2:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
+; CHECK-NEXT:    ret <2 x i64> [[T2]]
 ;
-  %tmp1 = zext <2 x i32> %a to <2 x i64>
-  %tmp2 = zext <2 x i1> %b to <2 x i64>
-  %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
-  %tmp4 = or <2 x i64> %tmp3, %tmp2
-  %tmp5 = and <2 x i64> %tmp4, <i64 1, i64 1>
-  ret <2 x i64> %tmp5
+  %t1 = zext <2 x i32> %a to <2 x i64>
+  %t2 = zext <2 x i1> %b to <2 x i64>
+  %t3 = shl nuw <2 x i64> %t1, <i64 32, i64 32>
+  %t4 = or <2 x i64> %t3, %t2
+  %t5 = and <2 x i64> %t4, <i64 1, i64 1>
+  ret <2 x i64> %t5
 }
 
 define <2 x i64> @shl_or_and2v(<2 x i32> %a, <2 x i1> %b) {
 ; CHECK-LABEL: @shl_or_and2v(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw <2 x i64> [[TMP1]], <i64 32, i64 32>
-; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
+; CHECK-NEXT:    [[T1:%.*]] = zext <2 x i1> [[B:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[T3:%.*]] = shl nuw <2 x i64> [[T1]], <i64 32, i64 32>
+; CHECK-NEXT:    ret <2 x i64> [[T3]]
 ;
-  %tmp1 = zext <2 x i1> %b to <2 x i64>
-  %tmp2 = zext <2 x i32> %a to <2 x i64>
-  %tmp3 = shl nuw <2 x i64> %tmp1, <i64 32, i64 32>
-  %tmp4 = or <2 x i64> %tmp2, %tmp3
-  %tmp5 = and <2 x i64> %tmp4, <i64 4294967296, i64 4294967296>
-  ret <2 x i64> %tmp5
+  %t1 = zext <2 x i1> %b to <2 x i64>
+  %t2 = zext <2 x i32> %a to <2 x i64>
+  %t3 = shl nuw <2 x i64> %t1, <i64 32, i64 32>
+  %t4 = or <2 x i64> %t2, %t3
+  %t5 = and <2 x i64> %t4, <i64 4294967296, i64 4294967296>
+  ret <2 x i64> %t5
 }
 
-define <2 x i32> @shl_or_and3v(<2 x i16> %a, <2 x i16> %b) {
 ; A variation of above test case, but fails due to the mask value
+define <2 x i32> @shl_or_and3v(<2 x i16> %a, <2 x i16> %b) {
 ; CHECK-LABEL: @shl_or_and3v(
-; CHECK-NEXT:    [[TMP1:%.*]] = zext <2 x i16> [[A:%.*]] to <2 x i32>
-; CHECK-NEXT:    [[TMP2:%.*]] = zext <2 x i16> [[B:%.*]] to <2 x i32>
-; CHECK-NEXT:    [[TMP3:%.*]] = shl nuw <2 x i32> [[TMP1]], <i32 16, i32 16>
-; CHECK-NEXT:    [[TMP4:%.*]] = or <2 x i32> [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = and <2 x i32> [[TMP4]], <i32 -65535, i32 -65535>
-; CHECK-NEXT:    ret <2 x i32> [[TMP5]]
-;
-  %tmp1 = zext <2 x i16> %a to <2 x i32>
-  %tmp2 = zext <2 x i16> %b to <2 x i32>
-  %tmp3 = shl nuw <2 x i32> %tmp1, <i32 16, i32 16>
-  %tmp4 = or <2 x i32> %tmp2, %tmp3
-  %tmp5 = and <2 x i32> %tmp4, <i32 4294901761, i32 4294901761> ; mask with 0xFFFF0001
-  ret <2 x i32> %tmp5
+; CHECK-NEXT:    [[T1:%.*]] = zext <2 x i16> [[A:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[T2:%.*]] = zext <2 x i16> [[B:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[T3:%.*]] = shl nuw <2 x i32> [[T1]], <i32 16, i32 16>
+; CHECK-NEXT:    [[T4:%.*]] = or <2 x i32> [[T2]], [[T3]]
+; CHECK-NEXT:    [[T5:%.*]] = and <2 x i32> [[T4]], <i32 -65535, i32 -65535>
+; CHECK-NEXT:    ret <2 x i32> [[T5]]
+;
+  %t1 = zext <2 x i16> %a to <2 x i32>
+  %t2 = zext <2 x i16> %b to <2 x i32>
+  %t3 = shl nuw <2 x i32> %t1, <i32 16, i32 16>
+  %t4 = or <2 x i32> %t2, %t3
+  %t5 = and <2 x i32> %t4, <i32 4294901761, i32 4294901761> ; mask with 0xFFFF0001
+  ret <2 x i32> %t5
+}
+
+define i8 @and_add_sub(i8 %x) {
+; CHECK-LABEL: @and_add_sub(
+; CHECK-NEXT:    ret i8 0
+;
+  %a = add i8 %x, -1
+  %s = sub i8 0, %x
+  %r = and i8 %a, %s
+  ret i8 %r
+}
+
+define <2 x i8> @and_sub_add(<2 x i8> %x) {
+; CHECK-LABEL: @and_sub_add(
+; CHECK-NEXT:    ret <2 x i8> zeroinitializer
+;
+  %a = add <2 x i8> %x, <i8 -4, i8 -4>
+  %s = sub <2 x i8> <i8 3, i8 3>, %x
+  %r = and <2 x i8> %s, %a
+  ret <2 x i8> %r
+}
+
+define i89 @or_add_sub(i89 %x) {
+; CHECK-LABEL: @or_add_sub(
+; CHECK-NEXT:    ret i89 -1
+;
+  %a = add i89 %x, 5
+  %s = sub i89 -6, %x
+  %r = or i89 %a, %s
+  ret i89 %r
+}
+
+define <3 x i8> @or_sub_add(<3 x i8> %x) {
+; CHECK-LABEL: @or_sub_add(
+; CHECK-NEXT:    ret <3 x i8> <i8 -1, i8 -1, i8 -1>
+;
+  %a = add <3 x i8> %x, <i8 42, i8 -12, i8 0>
+  %s = sub <3 x i8> <i8 -43, i8 11, i8 -1>, %x
+  %r = or <3 x i8> %s, %a
+  ret <3 x i8> %r
+}
+
+
+define <2 x i17> @xor_add_sub(<2 x i17> %x) {
+; CHECK-LABEL: @xor_add_sub(
+; CHECK-NEXT:    ret <2 x i17> <i17 -1, i17 -1>
+;
+  %a = add <2 x i17> %x, <i17 3000, i17 23>
+  %s = sub <2 x i17> <i17 -3001, i17 -24>, %x
+  %r = xor <2 x i17> %a, %s
+  ret <2 x i17> %r
+}
+
+define i8 @xor_sub_add(i8 %x) {
+; CHECK-LABEL: @xor_sub_add(
+; CHECK-NEXT:    ret i8 -1
+;
+  %a = add i8 %x, 33
+  %s = sub i8 -34, %x
+  %r = xor i8 %s, %a
+  ret i8 %r
+}
+
+; Negative test
+
+define i8 @and_add_sub_wrong_const(i8 %x) {
+; CHECK-LABEL: @and_add_sub_wrong_const(
+; CHECK-NEXT:    [[A:%.*]] = add i8 [[X:%.*]], 6
+; CHECK-NEXT:    [[S:%.*]] = sub i8 -6, [[X]]
+; CHECK-NEXT:    [[R:%.*]] = and i8 [[A]], [[S]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %a = add i8 %x, 6
+  %s = sub i8 -6, %x
+  %r = and i8 %a, %s
+  ret i8 %r
+}
+
+; Negative test
+
+define i8 @or_add_sub_wrong_var(i8 %x, i8 %y) {
+; CHECK-LABEL: @or_add_sub_wrong_var(
+; CHECK-NEXT:    [[A:%.*]] = add i8 [[X:%.*]], 5
+; CHECK-NEXT:    [[S:%.*]] = sub i8 -6, [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = or i8 [[A]], [[S]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %a = add i8 %x, 5
+  %s = sub i8 -6, %y
+  %r = or i8 %a, %s
+  ret i8 %r
+}
+
+; Negative test
+
+define i8 @xor_add_sub_wrong_op(i8 %x) {
+; CHECK-LABEL: @xor_add_sub_wrong_op(
+; CHECK-NEXT:    [[A:%.*]] = add i8 [[X:%.*]], 5
+; CHECK-NEXT:    [[S:%.*]] = sub i8 [[X]], -6
+; CHECK-NEXT:    [[R:%.*]] = xor i8 [[A]], [[S]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %a = add i8 %x, 5
+  %s = sub i8 %x, -6
+  %r = xor i8 %a, %s
+  ret i8 %r
 }
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/InsertElement-inseltpoison.ll b/llvm/test/Transforms/InstSimplify/ConstProp/InsertElement-inseltpoison.ll
new file mode 100644
index 0000000000000..54b862c8514a5
--- /dev/null
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/InsertElement-inseltpoison.ll
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+define i32 @test1() {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    ret i32 2139171423
+;
+  %A = bitcast i32 2139171423 to float
+  %B = insertelement <1 x float> poison, float %A, i32 0
+  %C = extractelement <1 x float> %B, i32 0
+  %D = bitcast float %C to i32
+  ret i32 %D
+}
+
+define <4 x i64> @insertelement() {
+; CHECK-LABEL: @insertelement(
+; CHECK-NEXT:    ret <4 x i64> <i64 -1, i64 -2, i64 -3, i64 -4>
+;
+  %vec1 = insertelement <4 x i64> poison, i64 -1, i32 0
+  %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
+  %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2
+  %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
+  ret <4 x i64> %vec4
+}
+
+define <4 x i64> @insertelement_undef() {
+; CHECK-LABEL: @insertelement_undef(
+; CHECK-NEXT:    ret <4 x i64> poison
+;
+  %vec1 = insertelement <4 x i64> poison, i64 -1, i32 0
+  %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
+  %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2
+  %vec4 = insertelement <4 x i64> %vec3, i64 -4, i32 3
+  %vec5 = insertelement <4 x i64> %vec3, i64 -5, i32 4
+  ret <4 x i64> %vec5
+}
+
+define i64 @extract_undef_index_from_zero_vec() {
+; CHECK-LABEL: @extract_undef_index_from_zero_vec(
+; CHECK-NEXT:    ret i64 poison
+;
+  %E = extractelement <2 x i64> zeroinitializer, i64 undef
+  ret i64 %E
+}
+
+define i64 @extract_undef_index_from_nonzero_vec() {
+; CHECK-LABEL: @extract_undef_index_from_nonzero_vec(
+; CHECK-NEXT:    ret i64 poison
+;
+  %E = extractelement <2 x i64> <i64 -1, i64 -1>, i64 undef
+  ret i64 %E
+}
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll b/llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll
new file mode 100644
index 0000000000000..e91d943c5eb7a
--- /dev/null
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/vscale-inseltpoison.ll
@@ -0,0 +1,301 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instsimplify -S -verify | FileCheck %s
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Unary Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+define <vscale x 2 x double> @fneg(<vscale x 2 x double> %val) {
+; CHECK-LABEL: @fneg(
+; CHECK-NEXT:    ret <vscale x 2 x double> undef
+;
+  %r = fneg <vscale x 2 x double> undef
+  ret <vscale x 2 x double> %r
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Binary Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+define <vscale x 4 x i32> @add() {
+; CHECK-LABEL: @add(
+; CHECK-NEXT:    ret <vscale x 4 x i32> undef
+;
+  %r = add <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x float> @fadd() {
+; CHECK-LABEL: @fadd(
+; CHECK-NEXT:    ret <vscale x 4 x float> undef
+;
+  %r = fadd <vscale x 4 x float> undef, undef
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x i32> @sub() {
+; CHECK-LABEL: @sub(
+; CHECK-NEXT:    ret <vscale x 4 x i32> undef
+;
+  %r = sub <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @sub_splat() {
+; CHECK-LABEL: @sub_splat(
+; CHECK-NEXT:    ret <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 -16, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+;
+  %r = sub <vscale x 4 x i32> zeroinitializer, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 16, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x float> @fsub() {
+; CHECK-LABEL: @fsub(
+; CHECK-NEXT:    ret <vscale x 4 x float> undef
+;
+  %r = fsub <vscale x 4 x float> undef, undef
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x i32> @mul() {
+; CHECK-LABEL: @mul(
+; CHECK-NEXT:    ret <vscale x 4 x i32> undef
+;
+  %r = mul <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x float> @fmul() {
+; CHECK-LABEL: @fmul(
+; CHECK-NEXT:    ret <vscale x 4 x float> undef
+;
+  %r = fmul <vscale x 4 x float> undef, undef
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x i32> @udiv() {
+; CHECK-LABEL: @udiv(
+; CHECK-NEXT:    ret <vscale x 4 x i32> poison
+;
+  %r = udiv <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @udiv_splat_zero() {
+; CHECK-LABEL: @udiv_splat_zero(
+; CHECK-NEXT:    ret <vscale x 4 x i32> poison
+;
+  %r = udiv <vscale x 4 x i32> zeroinitializer, zeroinitializer
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @sdiv() {
+; CHECK-LABEL: @sdiv(
+; CHECK-NEXT:    ret <vscale x 4 x i32> poison
+;
+  %r = sdiv <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x float> @fdiv() {
+; CHECK-LABEL: @fdiv(
+; CHECK-NEXT:    ret <vscale x 4 x float> undef
+;
+  %r = fdiv <vscale x 4 x float> undef, undef
+  ret <vscale x 4 x float> %r
+}
+
+define <vscale x 4 x i32> @urem() {
+; CHECK-LABEL: @urem(
+; CHECK-NEXT:    ret <vscale x 4 x i32> poison
+;
+  %r = urem <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @srem() {
+; CHECK-LABEL: @srem(
+; CHECK-NEXT:    ret <vscale x 4 x i32> poison
+;
+  %r = srem <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x float> @frem() {
+; CHECK-LABEL: @frem(
+; CHECK-NEXT:    ret <vscale x 4 x float> undef
+;
+  %r = frem <vscale x 4 x float> undef, undef
+  ret <vscale x 4 x float> %r
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Bitwise Binary Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+define <vscale x 4 x i32> @shl() {
+; CHECK-LABEL: @shl(
+; CHECK-NEXT:    ret <vscale x 4 x i32> poison
+;
+  %r = shl <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @lshr() {
+; CHECK-LABEL: @lshr(
+; CHECK-NEXT:    ret <vscale x 4 x i32> poison
+;
+  %r = lshr <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @ashr() {
+; CHECK-LABEL: @ashr(
+; CHECK-NEXT:    ret <vscale x 4 x i32> poison
+;
+  %r = ashr <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @and() {
+; CHECK-LABEL: @and(
+; CHECK-NEXT:    ret <vscale x 4 x i32> undef
+;
+  %r = and <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @or() {
+; CHECK-LABEL: @or(
+; CHECK-NEXT:    ret <vscale x 4 x i32> undef
+;
+  %r = or <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @xor() {
+; CHECK-LABEL: @xor(
+; CHECK-NEXT:    ret <vscale x 4 x i32> zeroinitializer
+;
+  %r = xor <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i32> %r
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Vector Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+define <vscale x 4 x i32> @insertelement() {
+; CHECK-LABEL: @insertelement(
+; CHECK-NEXT:    ret <vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0)
+;
+  %i = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
+  ret <vscale x 4 x i32> %i
+}
+
+define <vscale x 4 x i32> @shufflevector() {
+; CHECK-LABEL: @shufflevector(
+; CHECK-NEXT:    ret <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+;
+  %i = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
+  %i2 = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  ret <vscale x 4 x i32> %i2
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Memory Access and Addressing Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+define <vscale x 2 x double> @load() {
+; CHECK-LABEL: @load(
+; CHECK-NEXT:    [[R:%.*]] = load <vscale x 2 x double>, <vscale x 2 x double>* getelementptr (<vscale x 2 x double>, <vscale x 2 x double>* null, i64 1), align 16
+; CHECK-NEXT:    ret <vscale x 2 x double> [[R]]
+;
+  %r = load <vscale x 2 x double>, <vscale x 2 x double>* getelementptr (<vscale x 2 x double>, <vscale x 2 x double>* null, i64 1)
+  ret <vscale x 2 x double> %r
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Conversion Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+define <vscale x 4 x float> @bitcast() {
+; CHECK-LABEL: @bitcast(
+; CHECK-NEXT:    ret <vscale x 4 x float> bitcast (<vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer) to <vscale x 4 x float>)
+;
+  %i1 = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
+  %i2 = shufflevector <vscale x 4 x i32> %i1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %i3 = bitcast <vscale x 4 x i32> %i2 to <vscale x 4 x float>
+  ret <vscale x 4 x float> %i3
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Other Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+define <vscale x 4 x i32> @select() {
+; CHECK-LABEL: @select(
+; CHECK-NEXT:    ret <vscale x 4 x i32> undef
+;
+  %r = select <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> undef
+  ret <vscale x 4 x i32> %r
+}
+
+declare <vscale x 16 x i8> @llvm.something(<vscale x 16 x i8>, <vscale x 16 x i8>)
+
+define <vscale x 16 x i8> @call() {
+; CHECK-LABEL: @call(
+; CHECK-NEXT:    [[R:%.*]] = call <vscale x 16 x i8> @llvm.something(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+; CHECK-NEXT:    ret <vscale x 16 x i8> [[R]]
+;
+  %r =  call <vscale x 16 x i8> @llvm.something(<vscale x 16 x i8> undef, <vscale x 16 x i8> undef)
+  ret <vscale x 16 x i8> %r
+}
+
+define <vscale x 4 x i1> @icmp_undef() {
+; CHECK-LABEL: @icmp_undef(
+; CHECK-NEXT:    ret <vscale x 4 x i1> undef
+;
+  %r = icmp eq <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 4 x i1> @icmp_zero() {
+; CHECK-LABEL: @icmp_zero(
+; CHECK-NEXT:    ret <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer)
+;
+  %r = icmp eq <vscale x 4 x i32> zeroinitializer, zeroinitializer
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 4 x i1> @fcmp_true() {
+; CHECK-LABEL: @fcmp_true(
+; CHECK-NEXT:    ret <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer)
+;
+  %r = fcmp true <vscale x 4 x float> undef, undef
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 4 x i1> @fcmp_false() {
+; CHECK-LABEL: @fcmp_false(
+; CHECK-NEXT:    ret <vscale x 4 x i1> zeroinitializer
+;
+  %r = fcmp false <vscale x 4 x float> undef, undef
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 4 x i1> @fcmp_undef() {
+; CHECK-LABEL: @fcmp_undef(
+; CHECK-NEXT:    ret <vscale x 4 x i1> undef
+;
+  %r = icmp ne <vscale x 4 x i32> undef, undef
+  ret <vscale x 4 x i1> %r
+}
+
+define <vscale x 4 x i1> @fcmp_not_equality() {
+; CHECK-LABEL: @fcmp_not_equality(
+; CHECK-NEXT:    ret <vscale x 4 x i1> shufflevector (<vscale x 4 x i1> insertelement (<vscale x 4 x i1> undef, i1 true, i32 0), <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer)
+;
+  %r = icmp ule <vscale x 4 x i32> undef, zeroinitializer
+  ret <vscale x 4 x i1> %r
+}
diff --git a/llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevector-inseltpoison.ll b/llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevector-inseltpoison.ll
new file mode 100644
index 0000000000000..48ec29c95f61f
--- /dev/null
+++ b/llvm/test/Transforms/InstSimplify/ConstProp/vscale-shufflevector-inseltpoison.ll
@@ -0,0 +1,39 @@
+; RUN: opt -early-cse -earlycse-debug-hash -S < %s | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64"
+
+; This test checks that SimplifyInstruction does not blow up in the face of
+; a scalable shufflevector. vscale is a constant value known only at runtime.
+; Therefore, it is not possible to know the concrete value of, or the length
+; of the mask at compile time. Simplifications that depend on the value
+; of the mask cannot be performed.
+
+; Given the fact that the value of the mask is unknown at compile time for
+; scalable vectors, very few simplifications will be done. Here, we want to
+; see that the instruction can be passed to SimplifyInstruction and not crash
+; the compiler. It happens to be the case that this will be the result.
+
+; CHECK-LABEL: define <vscale x 8 x i1> @vscale_version()
+; CHECK-NEXT: ret <vscale x 8 x i1> shufflevector (<vscale x 8 x i1> insertelement (<vscale x 8 x i1> poison, i1 true, i32 0), <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer)
+
+define <vscale x 8 x i1> @vscale_version() {
+  %splatter = insertelement <vscale x 8 x i1> poison, i1 true, i32 0
+  %foo = shufflevector <vscale x 8 x i1> %splatter,
+                       <vscale x 8 x i1> undef,
+                       <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i1> %foo
+}
+
+; The non-scalable version should be optimized as normal.
+
+; CHECK-LABEL: define <8 x i1> @fixed_length_version() {
+; CHECK-NEXT:  ret <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>
+define <8 x i1> @fixed_length_version() {
+  %splatter = insertelement <8 x i1> poison, i1 true, i32 0
+  %foo = shufflevector <8 x i1> %splatter,
+                       <8 x i1> undef,
+                       <8 x i32> zeroinitializer
+  ret <8 x i1> %foo
+}
+
diff --git a/llvm/test/Transforms/InstSimplify/call.ll b/llvm/test/Transforms/InstSimplify/call.ll
index bfbd101b046c6..841582ab89742 100644
--- a/llvm/test/Transforms/InstSimplify/call.ll
+++ b/llvm/test/Transforms/InstSimplify/call.ll
@@ -1287,6 +1287,8 @@ define i32 @call_undef_musttail() {
 
 ; This is not the builtin fmax, so we don't know anything about its behavior.
 
+declare float @fmaxf(float, float)
+
 define float @nobuiltin_fmax() {
 ; CHECK-LABEL: @nobuiltin_fmax(
 ; CHECK-NEXT:    [[M:%.*]] = call float @fmaxf(float 0.000000e+00, float 1.000000e+00) [[ATTR3:#.*]]
@@ -1298,6 +1300,64 @@ define float @nobuiltin_fmax() {
   ret float %r
 }
 
-declare float @fmaxf(float, float)
+
+declare i32 @llvm.ctpop.i32(i32)
+declare <3 x i33> @llvm.ctpop.v3i33(<3 x i33>)
+declare i1 @llvm.ctpop.i1(i1)
+
+define i32 @ctpop_lowbit(i32 %x) {
+; CHECK-LABEL: @ctpop_lowbit(
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[X:%.*]], 1
+; CHECK-NEXT:    ret i32 [[B]]
+;
+  %b = and i32 %x, 1
+  %r = call i32 @llvm.ctpop.i32(i32 %b)
+  ret i32 %r
+}
+
+; Negative test - only low bit allowed
+; This could be reduced by instcombine to and+shift.
+
+define i32 @ctpop_pow2(i32 %x) {
+; CHECK-LABEL: @ctpop_pow2(
+; CHECK-NEXT:    [[B:%.*]] = and i32 [[X:%.*]], 4
+; CHECK-NEXT:    [[R:%.*]] = call i32 @llvm.ctpop.i32(i32 [[B]])
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %b = and i32 %x, 4
+  %r = call i32 @llvm.ctpop.i32(i32 %b)
+  ret i32 %r
+}
+
+define <3 x i33> @ctpop_signbit(<3 x i33> %x) {
+; CHECK-LABEL: @ctpop_signbit(
+; CHECK-NEXT:    [[B:%.*]] = lshr <3 x i33> [[X:%.*]], <i33 32, i33 32, i33 32>
+; CHECK-NEXT:    ret <3 x i33> [[B]]
+;
+  %b = lshr <3 x i33> %x, <i33 32, i33 32, i33 32>
+  %r = tail call <3 x i33> @llvm.ctpop.v3i33(<3 x i33> %b)
+  ret <3 x i33> %r
+}
+
+; Negative test - only 1 bit allowed
+
+define <3 x i33> @ctpop_notsignbit(<3 x i33> %x) {
+; CHECK-LABEL: @ctpop_notsignbit(
+; CHECK-NEXT:    [[B:%.*]] = lshr <3 x i33> [[X:%.*]], <i33 31, i33 31, i33 31>
+; CHECK-NEXT:    [[R:%.*]] = tail call <3 x i33> @llvm.ctpop.v3i33(<3 x i33> [[B]])
+; CHECK-NEXT:    ret <3 x i33> [[R]]
+;
+  %b = lshr <3 x i33> %x, <i33 31, i33 31, i33 31>
+  %r = tail call <3 x i33> @llvm.ctpop.v3i33(<3 x i33> %b)
+  ret <3 x i33> %r
+}
+
+define i1 @ctpop_bool(i1 %x) {
+; CHECK-LABEL: @ctpop_bool(
+; CHECK-NEXT:    ret i1 [[X:%.*]]
+;
+  %r = tail call i1 @llvm.ctpop.i1(i1 %x)
+  ret i1 %r
+}
 
 attributes #0 = { nobuiltin readnone }
diff --git a/llvm/test/Transforms/InstSimplify/select-inseltpoison.ll b/llvm/test/Transforms/InstSimplify/select-inseltpoison.ll
new file mode 100644
index 0000000000000..a949740e8429c
--- /dev/null
+++ b/llvm/test/Transforms/InstSimplify/select-inseltpoison.ll
@@ -0,0 +1,1007 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instsimplify -S | FileCheck %s
+
+define i1 @bool_true_or_false(i1 %cond) {
+; CHECK-LABEL: @bool_true_or_false(
+; CHECK-NEXT:    ret i1 [[COND:%.*]]
+;
+  %s = select i1 %cond, i1 true, i1 false
+  ret i1 %s
+}
+
+define <2 x i1> @bool_true_or_false_vec(<2 x i1> %cond) {
+; CHECK-LABEL: @bool_true_or_false_vec(
+; CHECK-NEXT:    ret <2 x i1> [[COND:%.*]]
+;
+  %s = select <2 x i1> %cond, <2 x i1> <i1 true, i1 true>, <2 x i1> zeroinitializer
+  ret <2 x i1> %s
+}
+
+define <2 x i1> @bool_true_or_false_vec_undef(<2 x i1> %cond) {
+; CHECK-LABEL: @bool_true_or_false_vec_undef(
+; CHECK-NEXT:    ret <2 x i1> [[COND:%.*]]
+;
+  %s = select <2 x i1> %cond, <2 x i1> <i1 undef, i1 true>, <2 x i1> <i1 false, i1 undef>
+  ret <2 x i1> %s
+}
+
+define i32 @cond_is_false(i32 %A, i32 %B) {
+; CHECK-LABEL: @cond_is_false(
+; CHECK-NEXT:    ret i32 [[B:%.*]]
+;
+  %C = select i1 false, i32 %A, i32 %B
+  ret i32 %C
+}
+
+define i32 @cond_is_true(i32 %A, i32 %B) {
+; CHECK-LABEL: @cond_is_true(
+; CHECK-NEXT:    ret i32 [[A:%.*]]
+;
+  %C = select i1 true, i32 %A, i32 %B
+  ret i32 %C
+}
+
+define i32 @equal_arms(i1 %cond, i32 %x) {
+; CHECK-LABEL: @equal_arms(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %V = select i1 %cond, i32 %x, i32 %x
+  ret i32 %V
+}
+
+define <2 x i32> @equal_arms_vec(<2 x i1> %cond, <2 x i32> %x) {
+; CHECK-LABEL: @equal_arms_vec(
+; CHECK-NEXT:    ret <2 x i32> [[X:%.*]]
+;
+  %V = select <2 x i1> %cond, <2 x i32> %x, <2 x i32> %x
+  ret <2 x i32> %V
+}
+
+define <2 x i32> @equal_arms_vec_undef(<2 x i1> %cond) {
+; CHECK-LABEL: @equal_arms_vec_undef(
+; CHECK-NEXT:    ret <2 x i32> <i32 42, i32 42>
+;
+  %V = select <2 x i1> %cond, <2 x i32> <i32 42, i32 undef>, <2 x i32> <i32 undef, i32 42>
+  ret <2 x i32> %V
+}
+
+define <3 x float> @equal_arms_vec_less_undef(<3 x i1> %cond) {
+; CHECK-LABEL: @equal_arms_vec_less_undef(
+; CHECK-NEXT:    ret <3 x float> <float 4.200000e+01, float 4.200000e+01, float 4.300000e+01>
+;
+  %V = select <3 x i1> %cond, <3 x float> <float 42.0, float undef, float 43.0>, <3 x float> <float 42.0, float 42.0, float 43.0>
+  ret <3 x float> %V
+}
+
+define <3 x float> @equal_arms_vec_more_undef(<3 x i1> %cond) {
+; CHECK-LABEL: @equal_arms_vec_more_undef(
+; CHECK-NEXT:    ret <3 x float> <float 4.200000e+01, float undef, float 4.300000e+01>
+;
+  %V = select <3 x i1> %cond, <3 x float> <float 42.0, float undef, float undef>, <3 x float> <float undef, float undef, float 43.0>
+  ret <3 x float> %V
+}
+
+define <2 x i8> @vsel_tvec(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @vsel_tvec(
+; CHECK-NEXT:    ret <2 x i8> [[X:%.*]]
+;
+  %s = select <2 x i1><i1 true, i1 true>, <2 x i8> %x, <2 x i8> %y
+  ret <2 x i8> %s
+}
+
+define <2 x i8> @vsel_fvec(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @vsel_fvec(
+; CHECK-NEXT:    ret <2 x i8> [[Y:%.*]]
+;
+  %s = select <2 x i1><i1 false, i1 false>, <2 x i8> %x, <2 x i8> %y
+  ret <2 x i8> %s
+}
+
+define <2 x i8> @vsel_mixedvec() {
+; CHECK-LABEL: @vsel_mixedvec(
+; CHECK-NEXT:    ret <2 x i8> <i8 0, i8 3>
+;
+  %s = select <2 x i1><i1 true, i1 false>, <2 x i8> <i8 0, i8 1>, <2 x i8> <i8 2, i8 3>
+  ret <2 x i8> %s
+}
+
+; FIXME: Allow for undef elements in a constant vector condition.
+
+define <3 x i8> @vsel_undef_true_op(<3 x i8> %x, <3 x i8> %y) {
+; CHECK-LABEL: @vsel_undef_true_op(
+; CHECK-NEXT:    [[S:%.*]] = select <3 x i1> <i1 true, i1 undef, i1 true>, <3 x i8> [[X:%.*]], <3 x i8> [[Y:%.*]]
+; CHECK-NEXT:    ret <3 x i8> [[S]]
+;
+  %s = select <3 x i1><i1 1, i1 undef, i1 1>, <3 x i8> %x, <3 x i8> %y
+  ret <3 x i8> %s
+}
+
+define <3 x i4> @vsel_undef_false_op(<3 x i4> %x, <3 x i4> %y) {
+; CHECK-LABEL: @vsel_undef_false_op(
+; CHECK-NEXT:    [[S:%.*]] = select <3 x i1> <i1 false, i1 undef, i1 undef>, <3 x i4> [[X:%.*]], <3 x i4> [[Y:%.*]]
+; CHECK-NEXT:    ret <3 x i4> [[S]]
+;
+  %s = select <3 x i1><i1 0, i1 undef, i1 undef>, <3 x i4> %x, <3 x i4> %y
+  ret <3 x i4> %s
+}
+
+define i32 @test1(i32 %x) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %and = and i32 %x, 1
+  %cmp = icmp eq i32 %and, 0
+  %and1 = and i32 %x, -2
+  %and1.x = select i1 %cmp, i32 %and1, i32 %x
+  ret i32 %and1.x
+}
+
+define i32 @test2(i32 %x) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %and = and i32 %x, 1
+  %cmp = icmp ne i32 %and, 0
+  %and1 = and i32 %x, -2
+  %and1.x = select i1 %cmp, i32 %x, i32 %and1
+  ret i32 %and1.x
+}
+
+define i32 @test3(i32 %x) {
+; CHECK-LABEL: @test3(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[X:%.*]], -2
+; CHECK-NEXT:    ret i32 [[AND1]]
+;
+  %and = and i32 %x, 1
+  %cmp = icmp ne i32 %and, 0
+  %and1 = and i32 %x, -2
+  %and1.x = select i1 %cmp, i32 %and1, i32 %x
+  ret i32 %and1.x
+}
+
+define i32 @test4(i32 %X) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %cmp = icmp slt i32 %X, 0
+  %or = or i32 %X, -2147483648
+  %cond = select i1 %cmp, i32 %X, i32 %or
+  ret i32 %cond
+}
+
+; Same as above, but the compare isn't canonical
+define i32 @test4noncanon(i32 %X) {
+; CHECK-LABEL: @test4noncanon(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %cmp = icmp sle i32 %X, -1
+  %or = or i32 %X, -2147483648
+  %cond = select i1 %cmp, i32 %X, i32 %or
+  ret i32 %cond
+}
+
+define i32 @test5(i32 %X) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %cmp = icmp slt i32 %X, 0
+  %or = or i32 %X, -2147483648
+  %cond = select i1 %cmp, i32 %or, i32 %X
+  ret i32 %cond
+}
+
+define i32 @test6(i32 %X) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %cmp = icmp slt i32 %X, 0
+  %and = and i32 %X, 2147483647
+  %cond = select i1 %cmp, i32 %and, i32 %X
+  ret i32 %cond
+}
+
+define i32 @test7(i32 %X) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %cmp = icmp slt i32 %X, 0
+  %and = and i32 %X, 2147483647
+  %cond = select i1 %cmp, i32 %X, i32 %and
+  ret i32 %cond
+}
+
+define i32 @test8(i32 %X) {
+; CHECK-LABEL: @test8(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %cmp = icmp sgt i32 %X, -1
+  %or = or i32 %X, -2147483648
+  %cond = select i1 %cmp, i32 %X, i32 %or
+  ret i32 %cond
+}
+
+define i32 @test9(i32 %X) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %cmp = icmp sgt i32 %X, -1
+  %or = or i32 %X, -2147483648
+  %cond = select i1 %cmp, i32 %or, i32 %X
+  ret i32 %cond
+}
+
+; Same as above, but the compare isn't canonical
+define i32 @test9noncanon(i32 %X) {
+; CHECK-LABEL: @test9noncanon(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], -2147483648
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %cmp = icmp sge i32 %X, 0
+  %or = or i32 %X, -2147483648
+  %cond = select i1 %cmp, i32 %or, i32 %X
+  ret i32 %cond
+}
+
+define i32 @test10(i32 %X) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %cmp = icmp sgt i32 %X, -1
+  %and = and i32 %X, 2147483647
+  %cond = select i1 %cmp, i32 %and, i32 %X
+  ret i32 %cond
+}
+
+define i32 @test11(i32 %X) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 2147483647
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %cmp = icmp sgt i32 %X, -1
+  %and = and i32 %X, 2147483647
+  %cond = select i1 %cmp, i32 %X, i32 %and
+  ret i32 %cond
+}
+
+define <2 x i8> @test11vec(<2 x i8> %X) {
+; CHECK-LABEL: @test11vec(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i8> [[X:%.*]], <i8 127, i8 127>
+; CHECK-NEXT:    ret <2 x i8> [[AND]]
+;
+  %cmp = icmp sgt <2 x i8> %X, <i8 -1, i8 -1>
+  %and = and <2 x i8> %X, <i8 127, i8 127>
+  %sel = select <2 x i1> %cmp, <2 x i8> %X, <2 x i8> %and
+  ret <2 x i8> %sel
+}
+
+define i32 @test12(i32 %X) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 3
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %cmp = icmp ult i32 %X, 4
+  %and = and i32 %X, 3
+  %cond = select i1 %cmp, i32 %X, i32 %and
+  ret i32 %cond
+}
+
+; Same as above, but the compare isn't canonical
+define i32 @test12noncanon(i32 %X) {
+; CHECK-LABEL: @test12noncanon(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 3
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %cmp = icmp ule i32 %X, 3
+  %and = and i32 %X, 3
+  %cond = select i1 %cmp, i32 %X, i32 %and
+  ret i32 %cond
+}
+
+define i32 @test13(i32 %X) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 3
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %cmp = icmp ugt i32 %X, 3
+  %and = and i32 %X, 3
+  %cond = select i1 %cmp, i32 %and, i32 %X
+  ret i32 %cond
+}
+
+; Same as above, but the compare isn't canonical
+define i32 @test13noncanon(i32 %X) {
+; CHECK-LABEL: @test13noncanon(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 3
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %cmp = icmp uge i32 %X, 4
+  %and = and i32 %X, 3
+  %cond = select i1 %cmp, i32 %and, i32 %X
+  ret i32 %cond
+}
+
+define i32 @select_icmp_and_8_eq_0_or_8(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_eq_0_or_8(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], 8
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp eq i32 %and, 0
+  %or = or i32 %x, 8
+  %sel = select i1 %cmp, i32 %or, i32 %x
+  ret i32 %sel
+}
+
+define i32 @select_icmp_and_8_eq_0_or_8_alt(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_eq_0_or_8_alt(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], 8
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp ne i32 %and, 0
+  %or = or i32 %x, 8
+  %sel = select i1 %cmp, i32 %x, i32 %or
+  ret i32 %sel
+}
+
+define i32 @select_icmp_and_8_ne_0_or_8(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_ne_0_or_8(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp ne i32 %and, 0
+  %or = or i32 %x, 8
+  %sel = select i1 %cmp, i32 %or, i32 %x
+  ret i32 %sel
+}
+
+define i32 @select_icmp_and_8_ne_0_or_8_alt(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_ne_0_or_8_alt(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp eq i32 %and, 0
+  %or = or i32 %x, 8
+  %sel = select i1 %cmp, i32 %x, i32 %or
+  ret i32 %sel
+}
+
+define i32 @select_icmp_and_8_eq_0_and_not_8(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_eq_0_and_not_8(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[X:%.*]], -9
+; CHECK-NEXT:    ret i32 [[AND1]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp eq i32 %and, 0
+  %and1 = and i32 %x, -9
+  %sel = select i1 %cmp, i32 %x, i32 %and1
+  ret i32 %sel
+}
+
+define i32 @select_icmp_and_8_eq_0_and_not_8_alt(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_eq_0_and_not_8_alt(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[X:%.*]], -9
+; CHECK-NEXT:    ret i32 [[AND1]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp ne i32 %and, 0
+  %and1 = and i32 %x, -9
+  %sel = select i1 %cmp, i32 %and1, i32 %x
+  ret i32 %sel
+}
+
+define i32 @select_icmp_and_8_ne_0_and_not_8(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_ne_0_and_not_8(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp ne i32 %and, 0
+  %and1 = and i32 %x, -9
+  %sel = select i1 %cmp, i32 %x, i32 %and1
+  ret i32 %sel
+}
+
+define i32 @select_icmp_and_8_ne_0_and_not_8_alt(i32 %x) {
+; CHECK-LABEL: @select_icmp_and_8_ne_0_and_not_8_alt(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp eq i32 %and, 0
+  %and1 = and i32 %x, -9
+  %sel = select i1 %cmp, i32 %and1, i32 %x
+  ret i32 %sel
+}
+
+; PR28466: https://llvm.org/bugs/show_bug.cgi?id=28466
+; Each of the previous 8 patterns has a variant that replaces the
+; 'and' with a 'trunc' and the icmp eq/ne with icmp slt/sgt.
+
+define i32 @select_icmp_trunc_8_ne_0_or_128(i32 %x) {
+; CHECK-LABEL: @select_icmp_trunc_8_ne_0_or_128(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], 128
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %trunc = trunc i32 %x to i8
+  %cmp = icmp sgt i8 %trunc, -1
+  %or = or i32 %x, 128
+  %sel = select i1 %cmp, i32 %or, i32 %x
+  ret i32 %sel
+}
+
+define i32 @select_icmp_trunc_8_ne_0_or_128_alt(i32 %x) {
+; CHECK-LABEL: @select_icmp_trunc_8_ne_0_or_128_alt(
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[X:%.*]], 128
+; CHECK-NEXT:    ret i32 [[OR]]
+;
+  %trunc = trunc i32 %x to i8
+  %cmp = icmp slt i8 %trunc, 0
+  %or = or i32 %x, 128
+  %sel = select i1 %cmp, i32 %x, i32 %or
+  ret i32 %sel
+}
+
+define i32 @select_icmp_trunc_8_eq_0_or_128(i32 %x) {
+; CHECK-LABEL: @select_icmp_trunc_8_eq_0_or_128(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %trunc = trunc i32 %x to i8
+  %cmp = icmp slt i8 %trunc, 0
+  %or = or i32 %x, 128
+  %sel = select i1 %cmp, i32 %or, i32 %x
+  ret i32 %sel
+}
+
+define i32 @select_icmp_trunc_8_eq_0_or_128_alt(i32 %x) {
+; CHECK-LABEL: @select_icmp_trunc_8_eq_0_or_128_alt(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %trunc = trunc i32 %x to i8
+  %cmp = icmp sgt i8 %trunc, -1
+  %or = or i32 %x, 128
+  %sel = select i1 %cmp, i32 %x, i32 %or
+  ret i32 %sel
+}
+
+define i32 @select_icmp_trunc_8_eq_0_and_not_8(i32 %x) {
+; CHECK-LABEL: @select_icmp_trunc_8_eq_0_and_not_8(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], -9
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %trunc = trunc i32 %x to i4
+  %cmp = icmp sgt i4 %trunc, -1
+  %and = and i32 %x, -9
+  %sel = select i1 %cmp, i32 %x, i32 %and
+  ret i32 %sel
+}
+
+define i32 @select_icmp_trunc_8_eq_0_and_not_8_alt(i32 %x) {
+; CHECK-LABEL: @select_icmp_trunc_8_eq_0_and_not_8_alt(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], -9
+; CHECK-NEXT:    ret i32 [[AND]]
+;
+  %trunc = trunc i32 %x to i4
+  %cmp = icmp slt i4 %trunc, 0
+  %and = and i32 %x, -9
+  %sel = select i1 %cmp, i32 %and, i32 %x
+  ret i32 %sel
+}
+
+define i32 @select_icmp_trunc_8_ne_0_and_not_8(i32 %x) {
+; CHECK-LABEL: @select_icmp_trunc_8_ne_0_and_not_8(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %trunc = trunc i32 %x to i4
+  %cmp = icmp slt i4 %trunc, 0
+  %and = and i32 %x, -9
+  %sel = select i1 %cmp, i32 %x, i32 %and
+  ret i32 %sel
+}
+
+define i32 @select_icmp_trunc_8_ne_0_and_not_8_alt(i32 %x) {
+; CHECK-LABEL: @select_icmp_trunc_8_ne_0_and_not_8_alt(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %trunc = trunc i32 %x to i4
+  %cmp = icmp sgt i4 %trunc, -1
+  %and = and i32 %x, -9
+  %sel = select i1 %cmp, i32 %and, i32 %x
+  ret i32 %sel
+}
+
+; Make sure that at least a few of the same patterns are repeated with vector types.
+
+define <2 x i32> @select_icmp_and_8_ne_0_and_not_8_vec(<2 x i32> %x) {
+; CHECK-LABEL: @select_icmp_and_8_ne_0_and_not_8_vec(
+; CHECK-NEXT:    ret <2 x i32> [[X:%.*]]
+;
+  %and = and <2 x i32> %x, <i32 8, i32 8>
+  %cmp = icmp ne <2 x i32> %and, zeroinitializer
+  %and1 = and <2 x i32> %x, <i32 -9, i32 -9>
+  %sel = select <2 x i1> %cmp, <2 x i32> %x, <2 x i32> %and1
+  ret <2 x i32> %sel
+}
+
+define <2 x i32> @select_icmp_trunc_8_ne_0_and_not_8_alt_vec(<2 x i32> %x) {
+; CHECK-LABEL: @select_icmp_trunc_8_ne_0_and_not_8_alt_vec(
+; CHECK-NEXT:    ret <2 x i32> [[X:%.*]]
+;
+  %trunc = trunc <2 x i32> %x to <2 x i4>
+  %cmp = icmp sgt <2 x i4> %trunc, <i4 -1, i4 -1>
+  %and = and <2 x i32> %x, <i32 -9, i32 -9>
+  %sel = select <2 x i1> %cmp, <2 x i32> %and, <2 x i32> %x
+  ret <2 x i32> %sel
+}
+
+; Insert a bit from x into y? This should be possible in InstCombine, but not InstSimplify?
+
+define i32 @select_icmp_x_and_8_eq_0_y_and_not_8(i32 %x, i32 %y) {
+; CHECK-LABEL: @select_icmp_x_and_8_eq_0_y_and_not_8(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 [[Y:%.*]], -9
+; CHECK-NEXT:    [[Y_AND1:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[AND1]]
+; CHECK-NEXT:    ret i32 [[Y_AND1]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp eq i32 %and, 0
+  %and1 = and i32 %y, -9
+  %y.and1 = select i1 %cmp, i32 %y, i32 %and1
+  ret i32 %y.and1
+}
+
+define i64 @select_icmp_x_and_8_eq_0_y64_and_not_8(i32 %x, i64 %y) {
+; CHECK-LABEL: @select_icmp_x_and_8_eq_0_y64_and_not_8(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    [[AND1:%.*]] = and i64 [[Y:%.*]], -9
+; CHECK-NEXT:    [[Y_AND1:%.*]] = select i1 [[CMP]], i64 [[Y]], i64 [[AND1]]
+; CHECK-NEXT:    ret i64 [[Y_AND1]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp eq i32 %and, 0
+  %and1 = and i64 %y, -9
+  %y.and1 = select i1 %cmp, i64 %y, i64 %and1
+  ret i64 %y.and1
+}
+
+define i64 @select_icmp_x_and_8_ne_0_y64_and_not_8(i32 %x, i64 %y) {
+; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y64_and_not_8(
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[X:%.*]], 8
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    [[AND1:%.*]] = and i64 [[Y:%.*]], -9
+; CHECK-NEXT:    [[AND1_Y:%.*]] = select i1 [[CMP]], i64 [[AND1]], i64 [[Y]]
+; CHECK-NEXT:    ret i64 [[AND1_Y]]
+;
+  %and = and i32 %x, 8
+  %cmp = icmp eq i32 %and, 0
+  %and1 = and i64 %y, -9
+  %and1.y = select i1 %cmp, i64 %and1, i64 %y
+  ret i64 %and1.y
+}
+
+; Don't crash on a pointer or aggregate type.
+
+define i32* @select_icmp_pointers(i32* %x, i32* %y) {
+; CHECK-LABEL: @select_icmp_pointers(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32* [[X:%.*]], null
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32* [[X]], i32* [[Y:%.*]]
+; CHECK-NEXT:    ret i32* [[SEL]]
+;
+  %cmp = icmp slt i32* %x, null
+  %sel = select i1 %cmp, i32* %x, i32* %y
+  ret i32* %sel
+}
+
+; If the condition is known, we don't need to select, but we're not
+; doing this fold here to avoid compile-time cost.
+
+declare void @llvm.assume(i1)
+
+define i8 @assume_sel_cond(i1 %cond, i8 %x, i8 %y) {
+; CHECK-LABEL: @assume_sel_cond(
+; CHECK-NEXT:    call void @llvm.assume(i1 [[COND:%.*]])
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[COND]], i8 [[X:%.*]], i8 [[Y:%.*]]
+; CHECK-NEXT:    ret i8 [[SEL]]
+;
+  call void @llvm.assume(i1 %cond)
+  %sel = select i1 %cond, i8 %x, i8 %y
+  ret i8 %sel
+}
+
+define i8 @do_not_assume_sel_cond(i1 %cond, i8 %x, i8 %y) {
+; CHECK-LABEL: @do_not_assume_sel_cond(
+; CHECK-NEXT:    [[NOTCOND:%.*]] = icmp eq i1 [[COND:%.*]], false
+; CHECK-NEXT:    call void @llvm.assume(i1 [[NOTCOND]])
+; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[COND]], i8 [[X:%.*]], i8 [[Y:%.*]]
+; CHECK-NEXT:    ret i8 [[SEL]]
+;
+  %notcond = icmp eq i1 %cond, false
+  call void @llvm.assume(i1 %notcond)
+  %sel = select i1 %cond, i8 %x, i8 %y
+  ret i8 %sel
+}
+
+define i32* @select_icmp_eq_0_gep_operand(i32* %base, i64 %n) {
+; CHECK-LABEL: @select_icmp_eq_0_gep_operand(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[N:%.*]]
+; CHECK-NEXT:    ret i32* [[GEP]]
+;
+  %cond = icmp eq i64 %n, 0
+  %gep = getelementptr i32, i32* %base, i64 %n
+  %r = select i1 %cond, i32* %base, i32* %gep
+  ret i32* %r
+}
+
+define i32* @select_icmp_ne_0_gep_operand(i32* %base, i64 %n) {
+; CHECK-LABEL: @select_icmp_ne_0_gep_operand(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, i32* [[BASE:%.*]], i64 [[N:%.*]]
+; CHECK-NEXT:    ret i32* [[GEP]]
+;
+  %cond = icmp ne i64 %n, 0
+  %gep = getelementptr i32, i32* %base, i64 %n
+  %r = select i1 %cond, i32* %gep, i32* %base
+  ret i32* %r
+}
+
+define i1 @and_cmps(i32 %x) {
+; CHECK-LABEL: @and_cmps(
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[X:%.*]], 92
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[X]], 11
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMP1]], i1 [[CMP2]], i1 false
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cmp1 = icmp slt i32 %x, 92
+  %cmp2 = icmp slt i32 %x, 11
+  %r = select i1 %cmp1, i1 %cmp2, i1 false
+  ret i1 %r
+}
+
+define <2 x i1> @and_cmps_vector(<2 x i32> %x) {
+; CHECK-LABEL: @and_cmps_vector(
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 92, i32 92>
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt <2 x i32> [[X]], <i32 11, i32 11>
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[CMP1]], <2 x i1> [[CMP2]], <2 x i1> zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %cmp1 = icmp slt <2 x i32> %x, <i32 92, i32 92>
+  %cmp2 = icmp slt <2 x i32> %x, <i32 11, i32 11>
+  %r = select <2 x i1> %cmp1, <2 x i1> %cmp2, <2 x i1> <i1 false, i1 false>
+  ret <2 x i1> %r
+}
+
+define i1 @or_cmps(float %x) {
+; CHECK-LABEL: @or_cmps(
+; CHECK-NEXT:    [[CMP1:%.*]] = fcmp uno float [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[CMP2:%.*]] = fcmp uno float [[X]], 5.200000e+01
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMP1]], i1 true, i1 [[CMP2]]
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cmp1 = fcmp uno float %x, 42.0
+  %cmp2 = fcmp uno float %x, 52.0
+  %r = select i1 %cmp1, i1 true, i1 %cmp2
+  ret i1 %r
+}
+
+define <2 x i1> @or_logic_vector(<2 x i1> %x, <2 x i1> %y) {
+; CHECK-LABEL: @or_logic_vector(
+; CHECK-NEXT:    [[A:%.*]] = and <2 x i1> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[X]], <2 x i1> <i1 true, i1 true>, <2 x i1> [[A]]
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %a = and <2 x i1> %x, %y
+  %r = select <2 x i1> %x, <2 x i1> <i1 true, i1 true>, <2 x i1> %a
+  ret <2 x i1> %r
+}
+
+define i1 @and_not_cmps(i32 %x) {
+; CHECK-LABEL: @and_not_cmps(
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[X:%.*]], 92
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[X]], 11
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMP1]], i1 false, i1 [[CMP2]]
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cmp1 = icmp slt i32 %x, 92
+  %cmp2 = icmp slt i32 %x, 11
+  %r = select i1 %cmp1, i1 false, i1 %cmp2
+  ret i1 %r
+}
+
+define i1 @or_not_cmps(i32 %x) {
+; CHECK-LABEL: @or_not_cmps(
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[X:%.*]], 92
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[X]], 11
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMP1]], i1 [[CMP2]], i1 true
+; CHECK-NEXT:    ret i1 [[R]]
+;
+  %cmp1 = icmp slt i32 %x, 92
+  %cmp2 = icmp slt i32 %x, 11
+  %r = select i1 %cmp1, i1 %cmp2, i1 true
+  ret i1 %r
+}
+
+define i8 @and_cmps_wrong_type(i32 %x) {
+; CHECK-LABEL: @and_cmps_wrong_type(
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[X:%.*]], 92
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[X]], 11
+; CHECK-NEXT:    [[S:%.*]] = sext i1 [[CMP2]] to i8
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[CMP1]], i8 [[S]], i8 0
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %cmp1 = icmp slt i32 %x, 92
+  %cmp2 = icmp slt i32 %x, 11
+  %s = sext i1 %cmp2 to i8
+  %r = select i1 %cmp1, i8 %s, i8 0
+  ret i8 %r
+}
+
+define i1 @y_might_be_poison(float %x, float %y) {
+; CHECK-LABEL: @y_might_be_poison(
+; CHECK-NEXT:    [[C1:%.*]] = fcmp ord float 0.000000e+00, [[X:%.*]]
+; CHECK-NEXT:    [[C2:%.*]] = fcmp ord float [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[C3:%.*]] = select i1 [[C1]], i1 [[C2]], i1 false
+; CHECK-NEXT:    ret i1 [[C3]]
+;
+  %c1 = fcmp ord float 0.0, %x
+  %c2 = fcmp ord float %x, %y
+  %c3 = select i1 %c1, i1 %c2, i1 false
+  ret i1 %c3
+}
+
+; Negative tests to ensure we don't remove selects with undef true/false values.
+; See https://bugs.llvm.org/show_bug.cgi?id=31633
+; https://lists.llvm.org/pipermail/llvm-dev/2016-October/106182.html
+; https://reviews.llvm.org/D83360
+define i32 @false_undef(i1 %cond, i32 %x) {
+; CHECK-LABEL: @false_undef(
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[COND:%.*]], i32 [[X:%.*]], i32 undef
+; CHECK-NEXT:    ret i32 [[S]]
+;
+  %s = select i1 %cond, i32 %x, i32 undef
+  ret i32 %s
+}
+
+define i32 @true_undef(i1 %cond, i32 %x) {
+; CHECK-LABEL: @true_undef(
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[COND:%.*]], i32 undef, i32 [[X:%.*]]
+; CHECK-NEXT:    ret i32 [[S]]
+;
+  %s = select i1 %cond, i32 undef, i32 %x
+  ret i32 %s
+}
+
+define <2 x i32> @false_undef_vec(i1 %cond, <2 x i32> %x) {
+; CHECK-LABEL: @false_undef_vec(
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[COND:%.*]], <2 x i32> [[X:%.*]], <2 x i32> undef
+; CHECK-NEXT:    ret <2 x i32> [[S]]
+;
+  %s = select i1 %cond, <2 x i32> %x, <2 x i32> undef
+  ret <2 x i32> %s
+}
+
+define <2 x i32> @true_undef_vec(i1 %cond, <2 x i32> %x) {
+; CHECK-LABEL: @true_undef_vec(
+; CHECK-NEXT:    [[S:%.*]] = select i1 [[COND:%.*]], <2 x i32> undef, <2 x i32> [[X:%.*]]
+; CHECK-NEXT:    ret <2 x i32> [[S]]
+;
+  %s = select i1 %cond, <2 x i32> undef, <2 x i32> %x
+  ret <2 x i32> %s
+}
+
+; These can be folded because the other value is guaranteed not to be poison.
+define i32 @false_undef_true_constant(i1 %cond) {
+; CHECK-LABEL: @false_undef_true_constant(
+; CHECK-NEXT:    ret i32 10
+;
+  %s = select i1 %cond, i32 10, i32 undef
+  ret i32 %s
+}
+
+define i32 @true_undef_false_constant(i1 %cond) {
+; CHECK-LABEL: @true_undef_false_constant(
+; CHECK-NEXT:    ret i32 20
+;
+  %s = select i1 %cond, i32 undef, i32 20
+  ret i32 %s
+}
+
+define <2 x i32> @false_undef_true_constant_vec(i1 %cond) {
+; CHECK-LABEL: @false_undef_true_constant_vec(
+; CHECK-NEXT:    ret <2 x i32> <i32 42, i32 -42>
+;
+  %s = select i1 %cond, <2 x i32> <i32 42, i32 -42>, <2 x i32> undef
+  ret <2 x i32> %s
+}
+
+define <2 x i32> @true_undef_false_constant_vec(i1 %cond) {
+; CHECK-LABEL: @true_undef_false_constant_vec(
+; CHECK-NEXT:    ret <2 x i32> <i32 -42, i32 42>
+;
+  %s = select i1 %cond, <2 x i32> undef, <2 x i32> <i32 -42, i32 42>
+  ret <2 x i32> %s
+}
+
+; If one input is undef and the other is freeze, we can fold it to the freeze.
+define i32 @false_undef_true_freeze(i1 %cond, i32 %x) {
+; CHECK-LABEL: @false_undef_true_freeze(
+; CHECK-NEXT:    [[XF:%.*]] = freeze i32 [[X:%.*]]
+; CHECK-NEXT:    ret i32 [[XF]]
+;
+  %xf = freeze i32 %x
+  %s = select i1 %cond, i32 %xf, i32 undef
+  ret i32 %s
+}
+
+define i32 @false_undef_false_freeze(i1 %cond, i32 %x) {
+; CHECK-LABEL: @false_undef_false_freeze(
+; CHECK-NEXT:    [[XF:%.*]] = freeze i32 [[X:%.*]]
+; CHECK-NEXT:    ret i32 [[XF]]
+;
+  %xf = freeze i32 %x
+  %s = select i1 %cond, i32 undef, i32 %xf
+  ret i32 %s
+}
+
+@g = external global i32, align 1
+
+define <2 x i32> @false_undef_true_constextpr_vec(i1 %cond) {
+; CHECK-LABEL: @false_undef_true_constextpr_vec(
+; CHECK-NEXT:    ret <2 x i32> <i32 ptrtoint (i32* @g to i32), i32 ptrtoint (i32* @g to i32)>
+;
+  %s = select i1 %cond, <2 x i32> <i32 undef, i32 ptrtoint (i32* @g to i32)>, <2 x i32> <i32 ptrtoint (i32* @g to i32), i32 undef>
+  ret <2 x i32> %s
+}
+
+define i32 @all_constant_true_undef() {
+; CHECK-LABEL: @all_constant_true_undef(
+; CHECK-NEXT:    ret i32 1
+;
+  %s = select i1 ptrtoint (i32 ()* @all_constant_true_undef to i1), i32 undef, i32 1
+  ret i32 %s
+}
+
+define float @all_constant_false_undef() {
+; CHECK-LABEL: @all_constant_false_undef(
+; CHECK-NEXT:    ret float 1.000000e+00
+;
+  %s = select i1 ptrtoint (float ()* @all_constant_false_undef to i1), float undef, float 1.0
+  ret float %s
+}
+
+define <2 x i32> @all_constant_true_undef_vec() {
+; CHECK-LABEL: @all_constant_true_undef_vec(
+; CHECK-NEXT:    ret <2 x i32> <i32 1, i32 -1>
+;
+  %s = select i1 ptrtoint (<2 x i32> ()* @all_constant_true_undef_vec to i1), <2 x i32> undef, <2 x i32> <i32 1, i32 -1>
+  ret <2 x i32> %s
+}
+
+define <2 x float> @all_constant_false_undef_vec() {
+; CHECK-LABEL: @all_constant_false_undef_vec(
+; CHECK-NEXT:    ret <2 x float> <float 1.000000e+00, float -1.000000e+00>
+;
+  %s = select i1 ptrtoint (<2 x float> ()* @all_constant_false_undef_vec to i1), <2 x float> undef, <2 x float> <float 1.0, float -1.0>
+  ret <2 x float> %s
+}
+
+; Negative tests. Don't fold if the non-undef operand is a constexpr.
+define i32 @all_constant_false_undef_true_constexpr() {
+; CHECK-LABEL: @all_constant_false_undef_true_constexpr(
+; CHECK-NEXT:    [[S:%.*]] = select i1 ptrtoint (i32 ()* @all_constant_false_undef_true_constexpr to i1), i32 ptrtoint (i32 ()* @all_constant_false_undef_true_constexpr to i32), i32 undef
+; CHECK-NEXT:    ret i32 [[S]]
+;
+  %s = select i1 ptrtoint (i32 ()* @all_constant_false_undef_true_constexpr to i1), i32 ptrtoint (i32 ()* @all_constant_false_undef_true_constexpr to i32), i32 undef
+  ret i32 %s
+}
+
+define i32 @all_constant_true_undef_false_constexpr() {
+; CHECK-LABEL: @all_constant_true_undef_false_constexpr(
+; CHECK-NEXT:    [[S:%.*]] = select i1 ptrtoint (i32 ()* @all_constant_true_undef_false_constexpr to i1), i32 undef, i32 ptrtoint (i32 ()* @all_constant_true_undef_false_constexpr to i32)
+; CHECK-NEXT:    ret i32 [[S]]
+;
+  %s = select i1 ptrtoint (i32 ()* @all_constant_true_undef_false_constexpr to i1), i32 undef, i32 ptrtoint (i32 ()* @all_constant_true_undef_false_constexpr to i32)
+  ret i32 %s
+}
+
+; Negative tests. Don't fold if the non-undef operand is a vector containing a constexpr.
+define <2 x i32> @all_constant_false_undef_true_constexpr_vec() {
+; CHECK-LABEL: @all_constant_false_undef_true_constexpr_vec(
+; CHECK-NEXT:    [[S:%.*]] = select i1 ptrtoint (<2 x i32> ()* @all_constant_false_undef_true_constexpr_vec to i1), <2 x i32> <i32 ptrtoint (<2 x i32> ()* @all_constant_false_undef_true_constexpr_vec to i32), i32 -1>, <2 x i32> undef
+; CHECK-NEXT:    ret <2 x i32> [[S]]
+;
+  %s = select i1 ptrtoint (<2 x i32> ()* @all_constant_false_undef_true_constexpr_vec to i1), <2 x i32> <i32 ptrtoint (<2 x i32> ()* @all_constant_false_undef_true_constexpr_vec to i32), i32 -1>, <2 x i32> undef
+  ret <2 x i32> %s
+}
+
+define <2 x i32> @all_constant_true_undef_false_constexpr_vec() {
+; CHECK-LABEL: @all_constant_true_undef_false_constexpr_vec(
+; CHECK-NEXT:    [[S:%.*]] = select i1 ptrtoint (<2 x i32> ()* @all_constant_true_undef_false_constexpr_vec to i1), <2 x i32> undef, <2 x i32> <i32 -1, i32 ptrtoint (<2 x i32> ()* @all_constant_true_undef_false_constexpr_vec to i32)>
+; CHECK-NEXT:    ret <2 x i32> [[S]]
+;
+  %s = select i1 ptrtoint (<2 x i32> ()* @all_constant_true_undef_false_constexpr_vec to i1), <2 x i32> undef, <2 x i32><i32 -1, i32 ptrtoint (<2 x i32> ()* @all_constant_true_undef_false_constexpr_vec to i32)>
+  ret <2 x i32> %s
+}
+
+define i1 @expand_binop_undef(i32 %x, i32 %y) {
+; CHECK-LABEL: @expand_binop_undef(
+; CHECK-NEXT:    [[CMP9_NOT_1:%.*]] = icmp eq i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[CMP15:%.*]] = icmp slt i32 [[X]], [[Y]]
+; CHECK-NEXT:    [[SPEC_SELECT39:%.*]] = select i1 [[CMP9_NOT_1]], i1 undef, i1 [[CMP15]]
+; CHECK-NEXT:    [[SPEC_SELECT40:%.*]] = xor i1 [[CMP9_NOT_1]], true
+; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = and i1 [[SPEC_SELECT39]], [[SPEC_SELECT40]]
+; CHECK-NEXT:    ret i1 [[SPEC_SELECT]]
+;
+  %cmp9.not.1 = icmp eq i32 %x, %y
+  %cmp15 = icmp slt i32 %x, %y
+  %spec.select39 = select i1 %cmp9.not.1, i1 undef, i1 %cmp15
+  %spec.select40 = xor i1 %cmp9.not.1, 1
+  %spec.select  = and i1 %spec.select39, %spec.select40
+  ret i1 %spec.select
+}
+
+define i32 @pr47322_more_poisonous_replacement(i32 %arg) {
+; CHECK-LABEL: @pr47322_more_poisonous_replacement(
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i32 [[ARG:%.*]], 0
+; CHECK-NEXT:    [[TRAILING:%.*]] = call i32 @llvm.cttz.i32(i32 [[ARG]], i1 immarg true)
+; CHECK-NEXT:    [[SHIFTED:%.*]] = lshr i32 [[ARG]], [[TRAILING]]
+; CHECK-NEXT:    [[R1_SROA_0_1:%.*]] = select i1 [[CMP]], i32 0, i32 [[SHIFTED]]
+; CHECK-NEXT:    ret i32 [[R1_SROA_0_1]]
+;
+  %cmp = icmp eq i32 %arg, 0
+  %trailing = call i32 @llvm.cttz.i32(i32 %arg, i1 immarg true)
+  %shifted = lshr i32 %arg, %trailing
+  %r1.sroa.0.1 = select i1 %cmp, i32 0, i32 %shifted
+  ret i32 %r1.sroa.0.1
+}
+declare i32 @llvm.cttz.i32(i32, i1 immarg)
+
+; Partial undef scalable vectors should be ignored.
+define <vscale x 2 x i1> @ignore_scalable_undef(<vscale x 2 x i1> %cond) {
+; CHECK-LABEL: @ignore_scalable_undef(
+; CHECK-NEXT:    [[S:%.*]] = select <vscale x 2 x i1> [[COND:%.*]], <vscale x 2 x i1> undef, <vscale x 2 x i1> insertelement (<vscale x 2 x i1> poison, i1 true, i32 0)
+; CHECK-NEXT:    ret <vscale x 2 x i1> [[S]]
+;
+  %vec = insertelement <vscale x 2 x i1> poison, i1 true, i32 0
+  %s = select <vscale x 2 x i1> %cond, <vscale x 2 x i1> undef, <vscale x 2 x i1> %vec
+  ret <vscale x 2 x i1> %s
+}
+
+; TODO: these can be optimized more
+
+define i32 @poison(i32 %x, i32 %y) {
+; CHECK-LABEL: @poison(
+; CHECK-NEXT:    ret i32 [[X:%.*]]
+;
+  %v = select i1 undef, i32 %x, i32 %y
+  ret i32 %v
+}
+
+define i32 @poison2(i1 %cond, i32 %x) {
+; CHECK-LABEL: @poison2(
+; CHECK-NEXT:    [[V:%.*]] = select i1 [[COND:%.*]], i32 poison, i32 [[X:%.*]]
+; CHECK-NEXT:    ret i32 [[V]]
+;
+  %v = select i1 %cond, i32 poison, i32 %x
+  ret i32 %v
+}
+
+define i32 @poison3(i1 %cond, i32 %x) {
+; CHECK-LABEL: @poison3(
+; CHECK-NEXT:    [[V:%.*]] = select i1 [[COND:%.*]], i32 [[X:%.*]], i32 poison
+; CHECK-NEXT:    ret i32 [[V]]
+;
+  %v = select i1 %cond, i32 %x, i32 poison
+  ret i32 %v
+}
+
+define <2 x i32> @poison4(<2 x i1> %cond, <2 x i32> %x) {
+; CHECK-LABEL: @poison4(
+; CHECK-NEXT:    [[V:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i32> [[X:%.*]], <2 x i32> poison
+; CHECK-NEXT:    ret <2 x i32> [[V]]
+;
+  %v = select <2 x i1> %cond, <2 x i32> %x, <2 x i32> poison
+  ret <2 x i32> %v
+}
diff --git a/llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll b/llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll
new file mode 100644
index 0000000000000..dac1ae37f7d8e
--- /dev/null
+++ b/llvm/test/Transforms/InstSimplify/vscale-inseltpoison.ll
@@ -0,0 +1,199 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instsimplify -S -verify | FileCheck %s
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Vector Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; insertelement
+
+define <vscale x 4 x i32> @insertelement_idx_undef(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @insertelement_idx_undef(
+; CHECK-NEXT:    ret <vscale x 4 x i32> undef
+;
+  %r = insertelement <vscale x 4 x i32> %a, i32 5, i64 undef
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelement_value_undef(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @insertelement_value_undef(
+; CHECK-NEXT:    [[R:%.*]] = insertelement <vscale x 4 x i32> [[A:%.*]], i32 undef, i64 0
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = insertelement <vscale x 4 x i32> %a, i32 undef, i64 0
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelement_idx_maybe_out_of_bound(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @insertelement_idx_maybe_out_of_bound(
+; CHECK-NEXT:    [[R:%.*]] = insertelement <vscale x 4 x i32> [[A:%.*]], i32 5, i64 4
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = insertelement <vscale x 4 x i32> %a, i32 5, i64 4
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelement_idx_large_bound(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @insertelement_idx_large_bound(
+; CHECK-NEXT:    [[R:%.*]] = insertelement <vscale x 4 x i32> [[A:%.*]], i32 5, i64 12345
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[R]]
+;
+  %r = insertelement <vscale x 4 x i32> %a, i32 5, i64 12345
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insert_extract_element_same_vec_idx_1(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @insert_extract_element_same_vec_idx_1(
+; CHECK-NEXT:    ret <vscale x 4 x i32> [[A:%.*]]
+;
+  %v = extractelement <vscale x 4 x i32> %a, i64 1
+  %r = insertelement <vscale x 4 x i32> %a, i32 %v, i64 1
+  ret <vscale x 4 x i32> %r
+}
+
+define <vscale x 4 x i32> @insertelement_inline_to_ret() {
+; CHECK-LABEL: @insertelement_inline_to_ret(
+; CHECK-NEXT:    ret <vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0)
+;
+  %i = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
+  ret <vscale x 4 x i32> %i
+}
+
+define <vscale x 4 x i32> @insertelement_shufflevector_inline_to_ret() {
+; CHECK-LABEL: @insertelement_shufflevector_inline_to_ret(
+; CHECK-NEXT:    ret <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
+;
+  %i = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
+  %i2 = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  ret <vscale x 4 x i32> %i2
+}
+
+; extractelement
+
+define i32 @extractelement_idx_undef(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @extractelement_idx_undef(
+; CHECK-NEXT:    ret i32 undef
+;
+  %r = extractelement <vscale x 4 x i32> %a, i64 undef
+  ret i32 %r
+}
+
+define i32 @extractelement_vec_undef(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @extractelement_vec_undef(
+; CHECK-NEXT:    ret i32 undef
+;
+  %r = extractelement <vscale x 4 x i32> undef, i64 1
+  ret i32 %r
+}
+
+define i32 @extractelement_idx_maybe_out_of_bound(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @extractelement_idx_maybe_out_of_bound(
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x i32> [[A:%.*]], i64 4
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %r = extractelement <vscale x 4 x i32> %a, i64 4
+  ret i32 %r
+}
+define i32 @extractelement_idx_large_bound(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: @extractelement_idx_large_bound(
+; CHECK-NEXT:    [[R:%.*]] = extractelement <vscale x 4 x i32> [[A:%.*]], i64 12345
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %r = extractelement <vscale x 4 x i32> %a, i64 12345
+  ret i32 %r
+}
+
+define i32 @insert_extract_element_same_vec_idx_2() {
+; CHECK-LABEL: @insert_extract_element_same_vec_idx_2(
+; CHECK-NEXT:    ret i32 1
+;
+  %v = insertelement <vscale x 4 x i32> poison, i32 1, i64 4
+  %r = extractelement <vscale x 4 x i32> %v, i64 4
+  ret i32 %r
+}
+
+define i32 @insert_extract_element_same_vec_idx_3() {
+; CHECK-LABEL: @insert_extract_element_same_vec_idx_3(
+; CHECK-NEXT:    ret i32 1
+;
+  %r = extractelement <vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i64 4), i64 4
+  ret i32 %r
+}
+
+define i32 @insert_extract_element_same_vec_idx_4() {
+; CHECK-LABEL: @insert_extract_element_same_vec_idx_4(
+; CHECK-NEXT:    ret i32 1
+;
+  %r = extractelement <vscale x 4 x i32> insertelement (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 1, i32 4), i32 2, i64 3), i64 4
+  ret i32 %r
+}
+
+; more complicated expressions
+
+define <vscale x 2 x i1> @cmp_le_smax_always_true(<vscale x 2 x i64> %x) {
+; CHECK-LABEL: @cmp_le_smax_always_true(
+; CHECK-NEXT:    ret <vscale x 2 x i1> shufflevector (<vscale x 2 x i1> insertelement (<vscale x 2 x i1> undef, i1 true, i32 0), <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer)
+;
+  %cmp = icmp sle <vscale x 2 x i64> %x, shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 9223372036854775807, i32 0), <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer)
+  ret <vscale x 2 x i1> %cmp
+}
+
+define <vscale x 4 x float> @bitcast() {
+; CHECK-LABEL: @bitcast(
+; CHECK-NEXT:    ret <vscale x 4 x float> bitcast (<vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer) to <vscale x 4 x float>)
+;
+  %i1 = insertelement <vscale x 4 x i32> poison, i32 1, i32 0
+  %i2 = shufflevector <vscale x 4 x i32> %i1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %i3 = bitcast <vscale x 4 x i32> %i2 to <vscale x 4 x float>
+  ret <vscale x 4 x float> %i3
+}
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;; Memory Access and Addressing Operations
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; getelementptr
+
+define <vscale x 4 x i32*> @getelementptr_constant_foldable_1() {
+; CHECK-LABEL: @getelementptr_constant_foldable_1(
+; CHECK-NEXT:    ret <vscale x 4 x i32*> zeroinitializer
+;
+  %ptr = getelementptr i32, <vscale x 4 x i32*> zeroinitializer, <vscale x 4 x i64> undef
+  ret <vscale x 4 x i32*> %ptr
+}
+
+define <vscale x 4 x <vscale x 4 x i32>*> @getelementptr_constant_foldable_2() {
+; CHECK-LABEL: @getelementptr_constant_foldable_2(
+; CHECK-NEXT:    ret <vscale x 4 x <vscale x 4 x i32>*> zeroinitializer
+;
+  %ptr = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* null, <vscale x 4 x i64> undef
+  ret <vscale x 4 x <vscale x 4 x i32>*> %ptr
+}
+
+; fold getelementptr P, 0 -> P.
+define <vscale x 4 x i32>* @getelementptr_constant_foldable_3() {
+; CHECK-LABEL: @getelementptr_constant_foldable_3(
+; CHECK-NEXT:    ret <vscale x 4 x i32>* null
+;
+  %ptr = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* null, i64 0
+  ret <vscale x 4 x i32>* %ptr
+}
+
+define <vscale x 4 x i32>* @getelementptr_not_constant_foldable(i64 %x) {
+; CHECK-LABEL: @getelementptr_not_constant_foldable(
+; CHECK-NEXT:    [[PTR:%.*]] = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* null, i64 [[X:%.*]]
+; CHECK-NEXT:    ret <vscale x 4 x i32>* [[PTR]]
+;
+  %ptr = getelementptr <vscale x 4 x i32>, <vscale x 4 x i32>* null, i64 %x
+  ret <vscale x 4 x i32>* %ptr
+}
+
+; Check GEP's result is known to be non-null.
+define i1 @getelementptr_check_non_null(<vscale x 16 x i8>* %ptr) {
+; CHECK-LABEL: @getelementptr_check_non_null(
+; CHECK-NEXT:    ret i1 false
+;
+  %x = getelementptr inbounds <vscale x 16 x i8>, <vscale x 16 x i8>* %ptr, i32 1
+  %cmp = icmp eq <vscale x 16 x i8>* %x, null
+  ret i1 %cmp
+}
diff --git a/llvm/test/Transforms/JumpThreading/thread-prob-3.ll b/llvm/test/Transforms/JumpThreading/thread-prob-3.ll
index a4a432b1a8329..27d060e159522 100644
--- a/llvm/test/Transforms/JumpThreading/thread-prob-3.ll
+++ b/llvm/test/Transforms/JumpThreading/thread-prob-3.ll
@@ -5,8 +5,8 @@
 ; call DuplicateCondBranchOnPHIIntoPred(bb3, {bb2}).
 ;
 ; CHECK-LABEL: ---- Branch Probability Info : foo
-; CHECK:      set edge bb2 -> 0 successor probability to 0x7fffffff / 0x80000000 = 100.00%
-; CHECK-NEXT: set edge bb2 -> 1 successor probability to 0x00000001 / 0x80000000 = 0.00%
+; CHECK:      set edge bb2 -> 0 successor probability to 0x80000000 / 0x80000000 = 100.00%
+; CHECK-NEXT: set edge bb2 -> 1 successor probability to 0x00000000 / 0x80000000 = 0.00%
 define void @foo(i1 %f0, i1 %f1, i1 %f2) !prof !{!"function_entry_count", i64 0} {
 ; CHECK-LABEL: @foo(
 bb1:
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
index a46f4d4175b7c..5bbacbf6a034c 100644
--- a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll
@@ -9,9 +9,6 @@ target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:3
 ; ALL-LABEL: @load_unknown_offset_align1_i8(
 ; ALL: alloca [128 x i8], align 1
 ; UNALIGNED: load <2 x i8>, <2 x i8> addrspace(5)* %{{[0-9]+}}, align 1{{$}}
-
-; ALIGNED: load i8, i8 addrspace(5)* %ptr0, align 1{{$}}
-; ALIGNED: load i8, i8 addrspace(5)* %ptr1, align 1{{$}}
 define amdgpu_kernel void @load_unknown_offset_align1_i8(i8 addrspace(1)* noalias %out, i32 %offset) #0 {
   %alloca = alloca [128 x i8], align 1, addrspace(5)
   %ptr0 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %alloca, i32 0, i32 %offset
@@ -60,13 +57,11 @@ define amdgpu_kernel void @load_unknown_offset_align1_i32(i32 addrspace(1)* noal
   ret void
 }
 
-; FIXME: Should always increase alignment of the load
 ; Make sure alloca alignment isn't decreased
 ; ALL-LABEL: @load_alloca16_unknown_offset_align1_i32(
 ; ALL: alloca [128 x i32], align 16
 
-; UNALIGNED: load <2 x i32>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 1{{$}}
-; ALIGNED: load <2 x i32>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 4{{$}}
+; ALL: load <2 x i32>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 4{{$}}
 define amdgpu_kernel void @load_alloca16_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 {
   %alloca = alloca [128 x i32], align 16, addrspace(5)
   %ptr0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca, i32 0, i32 %offset
@@ -128,11 +123,8 @@ define amdgpu_kernel void @store_unknown_offset_align1_i32(i32 addrspace(1)* noa
 }
 
 ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32(
-; ALIGNED: %alloca = alloca [8 x i32], align 4, addrspace(5)
-; ALIGNED: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, <4 x i32> addrspace(5)* %1, align 4
-
-; UNALIGNED: %alloca = alloca [8 x i32], align 1, addrspace(5)
-; UNALIGNED: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, <4 x i32> addrspace(5)* %1, align 1
+; ALL: %alloca = alloca [8 x i32], align 4, addrspace(5)
+; ALL: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, <4 x i32> addrspace(5)* %1, align 4
 define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32() {
   %alloca = alloca [8 x i32], align 1, addrspace(5)
   %out = bitcast [8 x i32] addrspace(5)* %alloca to i32 addrspace(5)*
@@ -148,11 +140,8 @@ define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32() {
 }
 
 ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i8(
-; ALIGNED: %alloca = alloca [8 x i8], align 4, addrspace(5)
-; ALIGNED: store <4 x i8> <i8 9, i8 1, i8 23, i8 19>, <4 x i8> addrspace(5)* %1, align 4
-
-; UNALIGNED: %alloca = alloca [8 x i8], align 1, addrspace(5)
-; UNALIGNED: store <4 x i8> <i8 9, i8 1, i8 23, i8 19>, <4 x i8> addrspace(5)* %1, align 1
+; ALL: %alloca = alloca [8 x i8], align 4, addrspace(5)
+; ALL: store <4 x i8> <i8 9, i8 1, i8 23, i8 19>, <4 x i8> addrspace(5)* %1, align 4
 define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8() {
   %alloca = alloca [8 x i8], align 1, addrspace(5)
   %out = bitcast [8 x i8] addrspace(5)* %alloca to i8 addrspace(5)*
@@ -168,11 +157,8 @@ define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8() {
 }
 
 ; ALL-LABEL: @merge_private_load_4_vector_elts_loads_v4i32(
-; ALIGNED: %alloca = alloca [8 x i32], align 4, addrspace(5)
-; ALIGNED: load <4 x i32>, <4 x i32> addrspace(5)* %1, align 4
-
-; UNALIGNED: %alloca = alloca [8 x i32], align 1, addrspace(5)
-; UNALIGNED: load <4 x i32>, <4 x i32> addrspace(5)* %1, align 1
+; ALL: %alloca = alloca [8 x i32], align 4, addrspace(5)
+; ALL: load <4 x i32>, <4 x i32> addrspace(5)* %1, align 4
 define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i32() {
   %alloca = alloca [8 x i32], align 1, addrspace(5)
   %out = bitcast [8 x i32] addrspace(5)* %alloca to i32 addrspace(5)*
@@ -188,11 +174,8 @@ define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i32() {
 }
 
 ; ALL-LABEL: @merge_private_load_4_vector_elts_loads_v4i8(
-; ALIGNED: %alloca = alloca [8 x i8], align 4, addrspace(5)
-; ALIGNED: load <4 x i8>, <4 x i8> addrspace(5)* %1, align 4
-
-; UNALIGNED: %alloca = alloca [8 x i8], align 1, addrspace(5)
-; UNALIGNED: load <4 x i8>, <4 x i8> addrspace(5)* %1, align 1
+; ALL: %alloca = alloca [8 x i8], align 4, addrspace(5)
+; ALL: load <4 x i8>, <4 x i8> addrspace(5)* %1, align 4
 define amdgpu_kernel void @merge_private_load_4_vector_elts_loads_v4i8() {
   %alloca = alloca [8 x i8], align 1, addrspace(5)
   %out = bitcast [8 x i8] addrspace(5)* %alloca to i8 addrspace(5)*
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll
new file mode 100644
index 0000000000000..8405a4a70ce9b
--- /dev/null
+++ b/llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/selects-inseltpoison.ll
@@ -0,0 +1,95 @@
+; RUN: opt -mtriple=amdgcn-amd-amdhsa -load-store-vectorizer -dce -S -o - %s | FileCheck %s
+
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
+
+define void @base_case(i1 %cnd, i32 addrspace(1)* %a, i32 addrspace(1)* %b, <3 x i32> addrspace(1)* %out) {
+; CHECK-LABEL: @base_case
+; CHECK: load <3 x i32>
+entry:
+  %gep1 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 1
+  %gep2 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 2
+  %gep4 = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 1
+  %gep5 = getelementptr inbounds i32, i32 addrspace(1)* %b, i64 2
+  %selected = select i1 %cnd, i32 addrspace(1)* %a, i32 addrspace(1)* %b
+  %selected14 = select i1 %cnd, i32 addrspace(1)* %gep1, i32 addrspace(1)* %gep4
+  %selected25 = select i1 %cnd, i32 addrspace(1)* %gep2, i32 addrspace(1)* %gep5
+  %val0 = load i32, i32 addrspace(1)* %selected, align 4
+  %val1 = load i32, i32 addrspace(1)* %selected14, align 4
+  %val2 = load i32, i32 addrspace(1)* %selected25, align 4
+  %t0 = insertelement <3 x i32> poison, i32 %val0, i32 0
+  %t1 = insertelement <3 x i32> %t0, i32 %val1, i32 1
+  %t2 = insertelement <3 x i32> %t1, i32 %val2, i32 2
+  store <3 x i32> %t2, <3 x i32> addrspace(1)* %out
+  ret void
+}
+
+define void @scev_targeting_complex_case(i1 %cnd, i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 %base, <2 x i32> addrspace(1)* %out) {
+; CHECK-LABEL: @scev_targeting_complex_case
+; CHECK: load <2 x i32>
+entry:
+  %base.x4 = shl i32 %base, 2
+  %base.x4.p1 = add i32 %base.x4, 1
+  %base.x4.p2 = add i32 %base.x4, 2
+  %base.x4.p3 = add i32 %base.x4, 3
+  %zext.x4 = zext i32 %base.x4 to i64
+  %zext.x4.p1 = zext i32 %base.x4.p1 to i64
+  %zext.x4.p2 = zext i32 %base.x4.p2 to i64
+  %zext.x4.p3 = zext i32 %base.x4.p3 to i64
+  %base.x16 = mul i64 %zext.x4, 4
+  %base.x16.p4 = shl i64 %zext.x4.p1, 2
+  %base.x16.p8 = shl i64 %zext.x4.p2, 2
+  %base.x16.p12 = mul i64 %zext.x4.p3, 4
+  %a.pi8 = bitcast i32 addrspace(1)* %a to i8 addrspace(1)*
+  %b.pi8 = bitcast i32 addrspace(1)* %b to i8 addrspace(1)*
+  %gep.a.base.x16 = getelementptr inbounds i8, i8 addrspace(1)* %a.pi8, i64 %base.x16
+  %gep.b.base.x16.p4 = getelementptr inbounds i8, i8 addrspace(1)* %b.pi8, i64 %base.x16.p4
+  %gep.a.base.x16.p8 = getelementptr inbounds i8, i8 addrspace(1)* %a.pi8, i64 %base.x16.p8
+  %gep.b.base.x16.p12 = getelementptr inbounds i8, i8 addrspace(1)* %b.pi8, i64 %base.x16.p12
+  %a.base.x16 = bitcast i8 addrspace(1)* %gep.a.base.x16 to i32 addrspace(1)*
+  %b.base.x16.p4 = bitcast i8 addrspace(1)* %gep.b.base.x16.p4 to i32 addrspace(1)*
+  %selected.base.x16.p0.or.4 = select i1 %cnd, i32 addrspace(1)* %a.base.x16, i32 addrspace(1)* %b.base.x16.p4
+  %gep.selected.base.x16.p8.or.12 = select i1 %cnd, i8 addrspace(1)* %gep.a.base.x16.p8, i8 addrspace(1)* %gep.b.base.x16.p12
+  %selected.base.x16.p8.or.12 = bitcast i8 addrspace(1)* %gep.selected.base.x16.p8.or.12 to i32 addrspace(1)*
+  %selected.base.x16.p40.or.44 = getelementptr inbounds i32, i32 addrspace(1)* %selected.base.x16.p0.or.4, i64 10
+  %selected.base.x16.p44.or.48 = getelementptr inbounds i32, i32 addrspace(1)* %selected.base.x16.p8.or.12, i64 9
+  %val0 = load i32, i32 addrspace(1)* %selected.base.x16.p40.or.44, align 4
+  %val1 = load i32, i32 addrspace(1)* %selected.base.x16.p44.or.48, align 4
+  %t0 = insertelement <2 x i32> poison, i32 %val0, i32 0
+  %t1 = insertelement <2 x i32> %t0, i32 %val1, i32 1
+  store <2 x i32> %t1, <2 x i32> addrspace(1)* %out
+  ret void
+}
+
+define void @nested_selects(i1 %cnd0, i1 %cnd1, i32 addrspace(1)* %a, i32 addrspace(1)* %b, i32 %base, <2 x i32> addrspace(1)* %out) {
+; CHECK-LABEL: @nested_selects
+; CHECK: load <2 x i32>
+entry:
+  %base.p1 = add nsw i32 %base, 1
+  %base.p2 = add i32 %base, 2
+  %base.p3 = add nsw i32 %base, 3
+  %base.x4 = mul i32 %base, 4
+  %base.x4.p5 = add i32 %base.x4, 5
+  %base.x4.p6 = add i32 %base.x4, 6
+  %sext = sext i32 %base to i64
+  %sext.p1 = sext i32 %base.p1 to i64
+  %sext.p2 = sext i32 %base.p2 to i64
+  %sext.p3 = sext i32 %base.p3 to i64
+  %sext.x4.p5 = sext i32 %base.x4.p5 to i64
+  %sext.x4.p6 = sext i32 %base.x4.p6 to i64
+  %gep.a.base = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %sext
+  %gep.a.base.p1 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %sext.p1
+  %gep.a.base.p2 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %sext.p2
+  %gep.a.base.p3 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %sext.p3
+  %gep.b.base.x4.p5 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %sext.x4.p5
+  %gep.b.base.x4.p6 = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %sext.x4.p6
+  %selected.1.L = select i1 %cnd1, i32 addrspace(1)* %gep.a.base.p2, i32 addrspace(1)* %gep.b.base.x4.p5
+  %selected.1.R = select i1 %cnd1, i32 addrspace(1)* %gep.a.base.p3, i32 addrspace(1)* %gep.b.base.x4.p6
+  %selected.0.L = select i1 %cnd0, i32 addrspace(1)* %gep.a.base, i32 addrspace(1)* %selected.1.L
+  %selected.0.R = select i1 %cnd0, i32 addrspace(1)* %gep.a.base.p1, i32 addrspace(1)* %selected.1.R
+  %val0 = load i32, i32 addrspace(1)* %selected.0.L, align 4
+  %val1 = load i32, i32 addrspace(1)* %selected.0.R, align 4
+  %t0 = insertelement <2 x i32> poison, i32 %val0, i32 0
+  %t1 = insertelement <2 x i32> %t0, i32 %val1, i32 1
+  store <2 x i32> %t1, <2 x i32> addrspace(1)* %out
+  ret void
+}
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/load-width-inseltpoison.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/load-width-inseltpoison.ll
new file mode 100644
index 0000000000000..41e9f0b590be6
--- /dev/null
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/load-width-inseltpoison.ll
@@ -0,0 +1,40 @@
+; RUN: opt -mtriple=x86_64-unknown-linux-gnu -load-store-vectorizer -mcpu haswell -S -o - %s | FileCheck --check-prefix=CHECK-HSW %s
+; RUN: opt -mtriple=x86_64-unknown-linux-gnu -load-store-vectorizer -mcpu knl -S -o - %s | FileCheck --check-prefix=CHECK-KNL %s
+; RUN: opt -mtriple=x86_64-unknown-linux-gnu -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -mcpu haswell -S -o - %s | FileCheck --check-prefix=CHECK-HSW %s
+; RUN: opt -mtriple=x86_64-unknown-linux-gnu -aa-pipeline=basic-aa -passes='function(load-store-vectorizer)' -mcpu knl -S -o - %s | FileCheck --check-prefix=CHECK-KNL %s
+
+define <8 x double> @loadwidth_insert_extract(double* %ptr) {
+    %a = bitcast double* %ptr to <2 x double> *
+    %b = getelementptr <2 x double>, <2 x double>* %a, i32 1
+    %c = getelementptr <2 x double>, <2 x double>* %a, i32 2
+    %d = getelementptr <2 x double>, <2 x double>* %a, i32 3
+; CHECK-HSW: load <4 x double>
+; CHECK-HSW: load <4 x double>
+; CHECK-HSW-NOT: load
+; CHECK-KNL: load <8 x double>
+; CHECK-KNL-NOT: load
+    %la = load <2 x double>, <2 x double> *%a
+    %lb = load <2 x double>, <2 x double> *%b
+    %lc = load <2 x double>, <2 x double> *%c
+    %ld = load <2 x double>, <2 x double> *%d
+    ; Scalarize everything - Explicitly not a shufflevector to test this code
+    ; path in the LSV
+    %v1 = extractelement <2 x double> %la, i32 0
+    %v2 = extractelement <2 x double> %la, i32 1
+    %v3 = extractelement <2 x double> %lb, i32 0
+    %v4 = extractelement <2 x double> %lb, i32 1
+    %v5 = extractelement <2 x double> %lc, i32 0
+    %v6 = extractelement <2 x double> %lc, i32 1
+    %v7 = extractelement <2 x double> %ld, i32 0
+    %v8 = extractelement <2 x double> %ld, i32 1
+    ; Make a vector again
+    %i1 = insertelement <8 x double> poison, double %v1, i32 0
+    %i2 = insertelement <8 x double> %i1, double %v2, i32 1
+    %i3 = insertelement <8 x double> %i2, double %v3, i32 2
+    %i4 = insertelement <8 x double> %i3, double %v4, i32 3
+    %i5 = insertelement <8 x double> %i4, double %v5, i32 4
+    %i6 = insertelement <8 x double> %i5, double %v6, i32 5
+    %i7 = insertelement <8 x double> %i6, double %v7, i32 6
+    %i8 = insertelement <8 x double> %i7, double %v8, i32 7
+    ret <8 x double> %i8
+}
diff --git a/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll b/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll
new file mode 100644
index 0000000000000..babee83fd0e46
--- /dev/null
+++ b/llvm/test/Transforms/LoadStoreVectorizer/X86/vectorize-i8-nested-add-inseltpoison.ll
@@ -0,0 +1,165 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -o - -S -load-store-vectorizer -dce %s | FileCheck %s
+
+; Make sure LoadStoreVectorizer vectorizes the loads below.
+; In order to prove that the vectorization is safe, it tries to
+; match nested adds and find an expression that adds a constant
+; value to an existing index and the result doesn't overflow.
+
+target triple = "x86_64--"
+
+define void @ld_v4i8_add_nsw(i32 %v0, i32 %v1, i8* %src, <4 x i8>* %dst) {
+; CHECK-LABEL: @ld_v4i8_add_nsw(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP:%.*]] = add nsw i32 [[V0:%.*]], -1
+; CHECK-NEXT:    [[TMP1:%.*]] = add nsw i32 [[V1:%.*]], [[TMP]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[SRC:%.*]], i64 [[TMP2]]
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i8* [[TMP3]] to <4 x i8>*
+; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* [[TMP0]], align 1
+; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
+; CHECK-NEXT:    [[TMP82:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
+; CHECK-NEXT:    [[TMP133:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
+; CHECK-NEXT:    [[TMP184:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT:    [[TMP19:%.*]] = insertelement <4 x i8> poison, i8 [[TMP41]], i32 0
+; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP82]], i32 1
+; CHECK-NEXT:    [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP133]], i32 2
+; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP184]], i32 3
+; CHECK-NEXT:    store <4 x i8> [[TMP22]], <4 x i8>* [[DST:%.*]], align 4
+; CHECK-NEXT:    ret void
+;
+bb:
+  %tmp = add nsw i32 %v0, -1
+  %tmp1 = add nsw i32 %v1, %tmp
+  %tmp2 = sext i32 %tmp1 to i64
+  %tmp3 = getelementptr inbounds i8, i8* %src, i64 %tmp2
+  %tmp4 = load i8, i8* %tmp3, align 1
+  %tmp5 = add nsw i32 %v1, %v0
+  %tmp6 = sext i32 %tmp5 to i64
+  %tmp7 = getelementptr inbounds i8, i8* %src, i64 %tmp6
+  %tmp8 = load i8, i8* %tmp7, align 1
+  %tmp9 = add nsw i32 %v0, 1
+  %tmp10 = add nsw i32 %v1, %tmp9
+  %tmp11 = sext i32 %tmp10 to i64
+  %tmp12 = getelementptr inbounds i8, i8* %src, i64 %tmp11
+  %tmp13 = load i8, i8* %tmp12, align 1
+  %tmp14 = add nsw i32 %v0, 2
+  %tmp15 = add nsw i32 %v1, %tmp14
+  %tmp16 = sext i32 %tmp15 to i64
+  %tmp17 = getelementptr inbounds i8, i8* %src, i64 %tmp16
+  %tmp18 = load i8, i8* %tmp17, align 1
+  %tmp19 = insertelement <4 x i8> poison, i8 %tmp4, i32 0
+  %tmp20 = insertelement <4 x i8> %tmp19, i8 %tmp8, i32 1
+  %tmp21 = insertelement <4 x i8> %tmp20, i8 %tmp13, i32 2
+  %tmp22 = insertelement <4 x i8> %tmp21, i8 %tmp18, i32 3
+  store <4 x i8> %tmp22, <4 x i8>* %dst
+  ret void
+}
+
+define void @ld_v4i8_add_nuw(i32 %v0, i32 %v1, i8* %src, <4 x i8>* %dst) {
+; CHECK-LABEL: @ld_v4i8_add_nuw(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP:%.*]] = add nuw i32 [[V0:%.*]], -1
+; CHECK-NEXT:    [[TMP1:%.*]] = add nuw i32 [[V1:%.*]], [[TMP]]
+; CHECK-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[SRC:%.*]], i64 [[TMP2]]
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i8* [[TMP3]] to <4 x i8>*
+; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* [[TMP0]], align 1
+; CHECK-NEXT:    [[TMP41:%.*]] = extractelement <4 x i8> [[TMP1]], i32 0
+; CHECK-NEXT:    [[TMP82:%.*]] = extractelement <4 x i8> [[TMP1]], i32 1
+; CHECK-NEXT:    [[TMP133:%.*]] = extractelement <4 x i8> [[TMP1]], i32 2
+; CHECK-NEXT:    [[TMP184:%.*]] = extractelement <4 x i8> [[TMP1]], i32 3
+; CHECK-NEXT:    [[TMP19:%.*]] = insertelement <4 x i8> poison, i8 [[TMP41]], i32 0
+; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP82]], i32 1
+; CHECK-NEXT:    [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP133]], i32 2
+; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP184]], i32 3
+; CHECK-NEXT:    store <4 x i8> [[TMP22]], <4 x i8>* [[DST:%.*]], align 4
+; CHECK-NEXT:    ret void
+;
+bb:
+  %tmp = add nuw i32 %v0, -1
+  %tmp1 = add nuw i32 %v1, %tmp
+  %tmp2 = zext i32 %tmp1 to i64
+  %tmp3 = getelementptr inbounds i8, i8* %src, i64 %tmp2
+  %tmp4 = load i8, i8* %tmp3, align 1
+  %tmp5 = add nuw i32 %v1, %v0
+  %tmp6 = zext i32 %tmp5 to i64
+  %tmp7 = getelementptr inbounds i8, i8* %src, i64 %tmp6
+  %tmp8 = load i8, i8* %tmp7, align 1
+  %tmp9 = add nuw i32 %v0, 1
+  %tmp10 = add nuw i32 %v1, %tmp9
+  %tmp11 = zext i32 %tmp10 to i64
+  %tmp12 = getelementptr inbounds i8, i8* %src, i64 %tmp11
+  %tmp13 = load i8, i8* %tmp12, align 1
+  %tmp14 = add nuw i32 %v0, 2
+  %tmp15 = add nuw i32 %v1, %tmp14
+  %tmp16 = zext i32 %tmp15 to i64
+  %tmp17 = getelementptr inbounds i8, i8* %src, i64 %tmp16
+  %tmp18 = load i8, i8* %tmp17, align 1
+  %tmp19 = insertelement <4 x i8> poison, i8 %tmp4, i32 0
+  %tmp20 = insertelement <4 x i8> %tmp19, i8 %tmp8, i32 1
+  %tmp21 = insertelement <4 x i8> %tmp20, i8 %tmp13, i32 2
+  %tmp22 = insertelement <4 x i8> %tmp21, i8 %tmp18, i32 3
+  store <4 x i8> %tmp22, <4 x i8>* %dst
+  ret void
+}
+
+; Make sure we don't vectorize the loads below because the source of
+; sext instructions doesn't have the nsw flag.
+
+define void @ld_v4i8_add_not_safe(i32 %v0, i32 %v1, i8* %src, <4 x i8>* %dst) {
+; CHECK-LABEL: @ld_v4i8_add_not_safe(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP:%.*]] = add nsw i32 [[V0:%.*]], -1
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[V1:%.*]], [[TMP]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sext i32 [[TMP1]] to i64
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[SRC:%.*]], i64 [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = load i8, i8* [[TMP3]], align 1
+; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[V1]], [[V0]]
+; CHECK-NEXT:    [[TMP6:%.*]] = sext i32 [[TMP5]] to i64
+; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i8, i8* [[SRC]], i64 [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = load i8, i8* [[TMP7]], align 1
+; CHECK-NEXT:    [[TMP9:%.*]] = add nsw i32 [[V0]], 1
+; CHECK-NEXT:    [[TMP10:%.*]] = add i32 [[V1]], [[TMP9]]
+; CHECK-NEXT:    [[TMP11:%.*]] = sext i32 [[TMP10]] to i64
+; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr inbounds i8, i8* [[SRC]], i64 [[TMP11]]
+; CHECK-NEXT:    [[TMP13:%.*]] = load i8, i8* [[TMP12]], align 1
+; CHECK-NEXT:    [[TMP14:%.*]] = add nsw i32 [[V0]], 2
+; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[V1]], [[TMP14]]
+; CHECK-NEXT:    [[TMP16:%.*]] = sext i32 [[TMP15]] to i64
+; CHECK-NEXT:    [[TMP17:%.*]] = getelementptr inbounds i8, i8* [[SRC]], i64 [[TMP16]]
+; CHECK-NEXT:    [[TMP18:%.*]] = load i8, i8* [[TMP17]], align 1
+; CHECK-NEXT:    [[TMP19:%.*]] = insertelement <4 x i8> poison, i8 [[TMP4]], i32 0
+; CHECK-NEXT:    [[TMP20:%.*]] = insertelement <4 x i8> [[TMP19]], i8 [[TMP8]], i32 1
+; CHECK-NEXT:    [[TMP21:%.*]] = insertelement <4 x i8> [[TMP20]], i8 [[TMP13]], i32 2
+; CHECK-NEXT:    [[TMP22:%.*]] = insertelement <4 x i8> [[TMP21]], i8 [[TMP18]], i32 3
+; CHECK-NEXT:    store <4 x i8> [[TMP22]], <4 x i8>* [[DST:%.*]], align 4
+; CHECK-NEXT:    ret void
+;
+bb:
+  %tmp = add nsw i32 %v0, -1
+  %tmp1 = add i32 %v1, %tmp
+  %tmp2 = sext i32 %tmp1 to i64
+  %tmp3 = getelementptr inbounds i8, i8* %src, i64 %tmp2
+  %tmp4 = load i8, i8* %tmp3, align 1
+  %tmp5 = add i32 %v1, %v0
+  %tmp6 = sext i32 %tmp5 to i64
+  %tmp7 = getelementptr inbounds i8, i8* %src, i64 %tmp6
+  %tmp8 = load i8, i8* %tmp7, align 1
+  %tmp9 = add nsw i32 %v0, 1
+  %tmp10 = add i32 %v1, %tmp9
+  %tmp11 = sext i32 %tmp10 to i64
+  %tmp12 = getelementptr inbounds i8, i8* %src, i64 %tmp11
+  %tmp13 = load i8, i8* %tmp12, align 1
+  %tmp14 = add nsw i32 %v0, 2
+  %tmp15 = add i32 %v1, %tmp14
+  %tmp16 = sext i32 %tmp15 to i64
+  %tmp17 = getelementptr inbounds i8, i8* %src, i64 %tmp16
+  %tmp18 = load i8, i8* %tmp17, align 1
+  %tmp19 = insertelement <4 x i8> poison, i8 %tmp4, i32 0
+  %tmp20 = insertelement <4 x i8> %tmp19, i8 %tmp8, i32 1
+  %tmp21 = insertelement <4 x i8> %tmp20, i8 %tmp13, i32 2
+  %tmp22 = insertelement <4 x i8> %tmp21, i8 %tmp18, i32 3
+  store <4 x i8> %tmp22, <4 x i8>* %dst
+  ret void
+}
diff --git a/llvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll b/llvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
new file mode 100644
index 0000000000000..464c12f453a70
--- /dev/null
+++ b/llvm/test/Transforms/LoopDeletion/noop-loops-with-subloops.ll
@@ -0,0 +1,172 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -loop-deletion -verify-dom-info -S | FileCheck %s
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
+
+%pair_t = type { i64, i64 }
+
+; The loop %inner cannot be removed, because it has outgoing values. But the
+; outer loop is a no-op and can be removed.
+define void @test1(i64 %N, i64 %M, %pair_t* %ptr) willreturn {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
+; CHECK:       outer.header:
+; CHECK-NEXT:    [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
+; CHECK-NEXT:    br label [[INNER:%.*]]
+; CHECK:       inner:
+; CHECK-NEXT:    [[INNER_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[INNER_IV_NEXT:%.*]], [[INNER]] ]
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr [[PAIR_T:%.*]], %pair_t* [[PTR:%.*]], i64 [[INNER_IV]]
+; CHECK-NEXT:    [[P:%.*]] = load [[PAIR_T]], %pair_t* [[GEP]], align 4
+; CHECK-NEXT:    [[V_0:%.*]] = extractvalue [[PAIR_T]] [[P]], 0
+; CHECK-NEXT:    [[V_1:%.*]] = extractvalue [[PAIR_T]] [[P]], 1
+; CHECK-NEXT:    [[INNER_EC:%.*]] = icmp ult i64 [[V_0]], [[V_1]]
+; CHECK-NEXT:    [[INNER_IV_NEXT]] = add i64 [[INNER_IV]], 1
+; CHECK-NEXT:    br i1 [[INNER_EC]], label [[OUTER_LATCH]], label [[INNER]]
+; CHECK:       outer.latch:
+; CHECK-NEXT:    [[LCSSA:%.*]] = phi i64 [ [[V_1]], [[INNER]] ]
+; CHECK-NEXT:    [[OUTER_EC:%.*]] = icmp ult i64 [[OUTER_IV]], [[LCSSA]]
+; CHECK-NEXT:    [[OUTER_IV_NEXT]] = add i64 [[OUTER_IV]], 1
+; CHECK-NEXT:    br i1 [[OUTER_EC]], label [[EXIT:%.*]], label [[OUTER_HEADER]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %outer.header
+
+outer.header:
+  %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
+
+  br label %inner
+
+inner:
+  %inner.iv = phi i64 [ 0, %outer.header ], [ %inner.iv.next, %inner ]
+  %gep = getelementptr %pair_t, %pair_t* %ptr, i64 %inner.iv
+  %p = load %pair_t, %pair_t* %gep
+  %v.0 = extractvalue %pair_t %p, 0
+  %v.1 = extractvalue %pair_t %p, 1
+  %inner.ec = icmp ult i64 %v.0, %v.1
+  %inner.iv.next = add i64 %inner.iv, 1
+  br i1 %inner.ec, label %outer.latch, label %inner
+
+outer.latch:
+  %lcssa = phi i64 [ %v.1, %inner ]
+  %outer.ec = icmp ult i64 %outer.iv, %lcssa
+  %outer.iv.next = add i64 %outer.iv, 1
+  br i1 %outer.ec, label %exit, label %outer.header
+
+exit:
+  ret void
+}
+
+declare void @sideeffect()
+
+; Same as @test1, but with a call in the outer loop. Nothing can be deleted.
+define void @test2_sideeffect_in_outer(i64 %N, i64 %M, %pair_t* %ptr) willreturn {
+; CHECK-LABEL: @test2_sideeffect_in_outer(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
+; CHECK:       outer.header:
+; CHECK-NEXT:    [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
+; CHECK-NEXT:    br label [[INNER:%.*]]
+; CHECK:       inner:
+; CHECK-NEXT:    [[INNER_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[INNER_IV_NEXT:%.*]], [[INNER]] ]
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr [[PAIR_T:%.*]], %pair_t* [[PTR:%.*]], i64 [[INNER_IV]]
+; CHECK-NEXT:    [[P:%.*]] = load [[PAIR_T]], %pair_t* [[GEP]], align 4
+; CHECK-NEXT:    [[V_0:%.*]] = extractvalue [[PAIR_T]] [[P]], 0
+; CHECK-NEXT:    [[V_1:%.*]] = extractvalue [[PAIR_T]] [[P]], 1
+; CHECK-NEXT:    [[INNER_EC:%.*]] = icmp ult i64 [[V_0]], [[V_1]]
+; CHECK-NEXT:    [[INNER_IV_NEXT]] = add i64 [[INNER_IV]], 1
+; CHECK-NEXT:    br i1 [[INNER_EC]], label [[OUTER_LATCH]], label [[INNER]]
+; CHECK:       outer.latch:
+; CHECK-NEXT:    [[LCSSA:%.*]] = phi i64 [ [[V_1]], [[INNER]] ]
+; CHECK-NEXT:    [[OUTER_EC:%.*]] = icmp ult i64 [[OUTER_IV]], [[LCSSA]]
+; CHECK-NEXT:    [[OUTER_IV_NEXT]] = add i64 [[OUTER_IV]], 1
+; CHECK-NEXT:    call void @sideeffect()
+; CHECK-NEXT:    br i1 [[OUTER_EC]], label [[EXIT:%.*]], label [[OUTER_HEADER]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %outer.header
+
+outer.header:
+  %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
+
+  br label %inner
+
+inner:
+  %inner.iv = phi i64 [ 0, %outer.header ], [ %inner.iv.next, %inner ]
+  %gep = getelementptr %pair_t, %pair_t* %ptr, i64 %inner.iv
+  %p = load %pair_t, %pair_t* %gep
+  %v.0 = extractvalue %pair_t %p, 0
+  %v.1 = extractvalue %pair_t %p, 1
+  %inner.ec = icmp ult i64 %v.0, %v.1
+  %inner.iv.next = add i64 %inner.iv, 1
+  br i1 %inner.ec, label %outer.latch, label %inner
+
+outer.latch:
+  %lcssa = phi i64 [ %v.1, %inner ]
+  %outer.ec = icmp ult i64 %outer.iv, %lcssa
+  %outer.iv.next = add i64 %outer.iv, 1
+  call void @sideeffect()
+  br i1 %outer.ec, label %exit, label %outer.header
+
+exit:
+  ret void
+}
+
+; Same as @test1, but with a call in the inner loop. Nothing can be deleted.
+define void @test3_sideeffect_in_inner(i64 %N, i64 %M, %pair_t* %ptr) willreturn {
+; CHECK-LABEL: @test3_sideeffect_in_inner(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
+; CHECK:       outer.header:
+; CHECK-NEXT:    [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
+; CHECK-NEXT:    br label [[INNER:%.*]]
+; CHECK:       inner:
+; CHECK-NEXT:    [[INNER_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[INNER_IV_NEXT:%.*]], [[INNER]] ]
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr [[PAIR_T:%.*]], %pair_t* [[PTR:%.*]], i64 [[INNER_IV]]
+; CHECK-NEXT:    [[P:%.*]] = load [[PAIR_T]], %pair_t* [[GEP]], align 4
+; CHECK-NEXT:    [[V_0:%.*]] = extractvalue [[PAIR_T]] [[P]], 0
+; CHECK-NEXT:    [[V_1:%.*]] = extractvalue [[PAIR_T]] [[P]], 1
+; CHECK-NEXT:    [[INNER_EC:%.*]] = icmp ult i64 [[V_0]], [[V_1]]
+; CHECK-NEXT:    [[INNER_IV_NEXT]] = add i64 [[INNER_IV]], 1
+; CHECK-NEXT:    call void @sideeffect()
+; CHECK-NEXT:    br i1 [[INNER_EC]], label [[OUTER_LATCH]], label [[INNER]]
+; CHECK:       outer.latch:
+; CHECK-NEXT:    [[LCSSA:%.*]] = phi i64 [ [[V_1]], [[INNER]] ]
+; CHECK-NEXT:    [[OUTER_EC:%.*]] = icmp ult i64 [[OUTER_IV]], [[LCSSA]]
+; CHECK-NEXT:    [[OUTER_IV_NEXT]] = add i64 [[OUTER_IV]], 1
+; CHECK-NEXT:    br i1 [[OUTER_EC]], label [[EXIT:%.*]], label [[OUTER_HEADER]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %outer.header
+
+outer.header:
+  %outer.iv = phi i64 [ 0, %entry ], [ %outer.iv.next, %outer.latch ]
+
+  br label %inner
+
+inner:
+  %inner.iv = phi i64 [ 0, %outer.header ], [ %inner.iv.next, %inner ]
+  %gep = getelementptr %pair_t, %pair_t* %ptr, i64 %inner.iv
+  %p = load %pair_t, %pair_t* %gep
+  %v.0 = extractvalue %pair_t %p, 0
+  %v.1 = extractvalue %pair_t %p, 1
+  %inner.ec = icmp ult i64 %v.0, %v.1
+  %inner.iv.next = add i64 %inner.iv, 1
+  call void @sideeffect()
+  br i1 %inner.ec, label %outer.latch, label %inner
+
+outer.latch:
+  %lcssa = phi i64 [ %v.1, %inner ]
+  %outer.ec = icmp ult i64 %outer.iv, %lcssa
+  %outer.iv.next = add i64 %outer.iv, 1
+  br i1 %outer.ec, label %exit, label %outer.header
+
+exit:
+  ret void
+}
diff --git a/llvm/test/Transforms/LoopIdiom/X86/left-shift-until-bittest.ll b/llvm/test/Transforms/LoopIdiom/X86/left-shift-until-bittest.ll
index 09811f28aa896..17ff7fc7663b6 100644
--- a/llvm/test/Transforms/LoopIdiom/X86/left-shift-until-bittest.ll
+++ b/llvm/test/Transforms/LoopIdiom/X86/left-shift-until-bittest.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -debugify -loop-idiom -mtriple=x86_64 -mcpu=core-avx2 < %s -S | FileCheck --check-prefix=ALL %s
-; RUN: opt -debugify -loop-idiom -mtriple=x86_64 -mcpu=corei7 < %s -S | FileCheck --check-prefix=ALL %s
+; RUN: opt -debugify -loop-idiom -mtriple=x86_64 -mcpu=core-avx2 < %s -S | FileCheck --check-prefixes=ALL,LZCNT %s
+; RUN: opt -debugify -loop-idiom -mtriple=x86_64 -mcpu=corei7 < %s -S | FileCheck  --check-prefixes=ALL,NOLZCNT %s
 
 declare i32 @gen32()
 declare void @use32(i32)
@@ -15,24 +15,56 @@ declare void @external_side_effect()
 
 ; Most basic example.
 define i32 @p0_i32(i32 %x, i32 %bit) {
-; ALL-LABEL: @p0_i32(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG16:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META9:metadata !.*]], metadata !DIExpression()), [[DBG16]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG17:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG18:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META11:metadata !.*]], metadata !DIExpression()), [[DBG18]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG19:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META12:metadata !.*]], metadata !DIExpression()), [[DBG19]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG20:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META13:metadata !.*]], metadata !DIExpression()), [[DBG20]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG21:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META15:metadata !.*]], metadata !DIExpression()), [[DBG21]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG22:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG18]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG23:!dbg !.*]]
+; LZCNT-LABEL: @p0_i32(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG16:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META9:metadata !.*]], metadata !DIExpression()), [[DBG16]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG17:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG17]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG17]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG17]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG17]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG17]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG17]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG17]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG17]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG17]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG18:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG17]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG17]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META11:metadata !.*]], metadata !DIExpression()), [[DBG17]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG19:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META12:metadata !.*]], metadata !DIExpression()), [[DBG19]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG20:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META13:metadata !.*]], metadata !DIExpression()), [[DBG20]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG21:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META15:metadata !.*]], metadata !DIExpression()), [[DBG21]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG22:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG22]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG22]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG17]]
+; LZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG23:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p0_i32(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG16:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META9:metadata !.*]], metadata !DIExpression()), [[DBG16]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG17:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG18:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META11:metadata !.*]], metadata !DIExpression()), [[DBG18]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG19:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META12:metadata !.*]], metadata !DIExpression()), [[DBG19]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG20:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META13:metadata !.*]], metadata !DIExpression()), [[DBG20]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG21:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META15:metadata !.*]], metadata !DIExpression()), [[DBG21]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG22:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG18]]
+; NOLZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG23:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -51,24 +83,56 @@ end:
 
 ; Same, but in some other bit width.
 define i16 @p1_i16(i16 %x, i16 %bit) {
-; ALL-LABEL: @p1_i16(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i16 1, [[BIT:%.*]], [[DBG32:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i16 [[BITMASK]], [[META26:metadata !.*]], metadata !DIExpression()), [[DBG32]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG33:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i16 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG34:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i16 [[X_CURR]], [[META28:metadata !.*]], metadata !DIExpression()), [[DBG34]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i16 [[X_CURR]], [[BITMASK]], [[DBG35:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i16 [[X_CURR_BITMASKED]], [[META29:metadata !.*]], metadata !DIExpression()), [[DBG35]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i16 [[X_CURR_BITMASKED]], 0, [[DBG36:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META30:metadata !.*]], metadata !DIExpression()), [[DBG36]]
-; ALL-NEXT:    [[X_NEXT]] = shl i16 [[X_CURR]], 1, [[DBG37:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i16 [[X_NEXT]], [[META31:metadata !.*]], metadata !DIExpression()), [[DBG37]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG38:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i16 [ [[X_CURR]], [[LOOP]] ], [[DBG34]]
-; ALL-NEXT:    ret i16 [[X_CURR_LCSSA]], [[DBG39:!dbg !.*]]
+; LZCNT-LABEL: @p1_i16(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i16 1, [[BIT:%.*]], [[DBG32:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i16 [[BITMASK]], [[META26:metadata !.*]], metadata !DIExpression()), [[DBG32]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i16 [[BITMASK]], -1, [[DBG33:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i16 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG33]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i16 [[X:%.*]], [[BIT_MASK]], [[DBG33]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i16 @llvm.ctlz.i16(i16 [[X_MASKED]], i1 true), [[DBG33]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i16 16, [[X_MASKED_NUMLEADINGZEROS]], [[DBG33]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i16 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG33]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i16 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG33]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i16 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG33]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i16 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG33]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i16 [[X_CURR]], 1, [[DBG33]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG34:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i16 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG33]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i16 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG33]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i16 [[TMP0]], [[META28:metadata !.*]], metadata !DIExpression()), [[DBG33]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i16 [[TMP0]], [[BITMASK]], [[DBG35:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i16 [[X_CURR_BITMASKED]], [[META29:metadata !.*]], metadata !DIExpression()), [[DBG35]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i16 [[X_CURR_BITMASKED]], 0, [[DBG36:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META30:metadata !.*]], metadata !DIExpression()), [[DBG36]]
+; LZCNT-NEXT:    [[TMP1]] = shl i16 [[TMP0]], 1, [[DBG37:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i16 [[TMP1]], [[META31:metadata !.*]], metadata !DIExpression()), [[DBG37]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i16 [[LOOP_IV]], 1, [[DBG38:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i16 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG38]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG38]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i16 [ [[X_CURR]], [[LOOP]] ], [[DBG33]]
+; LZCNT-NEXT:    ret i16 [[X_CURR_LCSSA]], [[DBG39:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p1_i16(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i16 1, [[BIT:%.*]], [[DBG32:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i16 [[BITMASK]], [[META26:metadata !.*]], metadata !DIExpression()), [[DBG32]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG33:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i16 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG34:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i16 [[X_CURR]], [[META28:metadata !.*]], metadata !DIExpression()), [[DBG34]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i16 [[X_CURR]], [[BITMASK]], [[DBG35:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i16 [[X_CURR_BITMASKED]], [[META29:metadata !.*]], metadata !DIExpression()), [[DBG35]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i16 [[X_CURR_BITMASKED]], 0, [[DBG36:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META30:metadata !.*]], metadata !DIExpression()), [[DBG36]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i16 [[X_CURR]], 1, [[DBG37:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i16 [[X_NEXT]], [[META31:metadata !.*]], metadata !DIExpression()), [[DBG37]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG38:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i16 [ [[X_CURR]], [[LOOP]] ], [[DBG34]]
+; NOLZCNT-NEXT:    ret i16 [[X_CURR_LCSSA]], [[DBG39:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i16 1, %bit
@@ -85,23 +149,126 @@ end:
   ret i16 %x.curr
 }
 
-define i32 @p2_constant_mask_24thbit(i32 %x) {
-; ALL-LABEL: @p2_constant_mask_24thbit(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG46:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG47:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META42:metadata !.*]], metadata !DIExpression()), [[DBG47]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 16777216, [[DBG48:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META43:metadata !.*]], metadata !DIExpression()), [[DBG48]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG49:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META44:metadata !.*]], metadata !DIExpression()), [[DBG49]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG50:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META45:metadata !.*]], metadata !DIExpression()), [[DBG50]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG51:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG47]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG52:!dbg !.*]]
+; We don't particularly care whether %x.curr or %x.curr will live-out.
+define i32 @p2_different_liveout(i32 %x, i32 %bit) {
+; LZCNT-LABEL: @p2_different_liveout(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG47:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META42:metadata !.*]], metadata !DIExpression()), [[DBG47]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG48:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG48]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG48]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG48]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG48]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG48]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG48]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG48]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG48]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG48]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG49:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG48]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG48]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META43:metadata !.*]], metadata !DIExpression()), [[DBG48]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG50:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META44:metadata !.*]], metadata !DIExpression()), [[DBG50]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG51:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META45:metadata !.*]], metadata !DIExpression()), [[DBG51]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG52:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META46:metadata !.*]], metadata !DIExpression()), [[DBG52]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG53:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG53]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG53]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG52]]
+; LZCNT-NEXT:    ret i32 [[X_NEXT_LCSSA]], [[DBG54:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p2_different_liveout(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG47:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META42:metadata !.*]], metadata !DIExpression()), [[DBG47]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG48:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG49:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META43:metadata !.*]], metadata !DIExpression()), [[DBG49]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG50:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META44:metadata !.*]], metadata !DIExpression()), [[DBG50]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG51:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META45:metadata !.*]], metadata !DIExpression()), [[DBG51]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG52:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META46:metadata !.*]], metadata !DIExpression()), [[DBG52]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG53:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG52]]
+; NOLZCNT-NEXT:    ret i32 [[X_NEXT_LCSSA]], [[DBG54:!dbg !.*]]
+;
+entry:
+  %bitmask = shl i32 1, %bit
+  br label %loop
+
+loop:
+  %x.curr = phi i32 [ %x, %entry ], [ %x.next, %loop ]
+  %x.curr.bitmasked = and i32 %x.curr, %bitmask
+  %x.curr.isbitunset = icmp eq i32 %x.curr.bitmasked, 0
+  %x.next = shl i32 %x.curr, 1
+  br i1 %x.curr.isbitunset, label %loop, label %end
+
+end:
+  ret i32 %x.next ; not %x.curr
+}
+
+; Even both of them can liveout
+define void @p3_constant_mask_24thbit(i32 %x, i32* %p0, i32* %p1) {
+; LZCNT-LABEL: @p3_constant_mask_24thbit(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], 33554431, [[DBG61:!dbg !.*]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG61]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG61]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG61]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 24, [[X_MASKED_LEADINGONEPOS]], [[DBG61]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG61]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG61]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X]], [[LOOP_TRIPCOUNT]], [[DBG61]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG62:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG61]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG61]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META57:metadata !.*]], metadata !DIExpression()), [[DBG61]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], 16777216, [[DBG63:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META58:metadata !.*]], metadata !DIExpression()), [[DBG63]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG64:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META59:metadata !.*]], metadata !DIExpression()), [[DBG64]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG65:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META60:metadata !.*]], metadata !DIExpression()), [[DBG65]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG66:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG66]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG66]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG61]]
+; LZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG65]]
+; LZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG67:!dbg !.*]]
+; LZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG68:!dbg !.*]]
+; LZCNT-NEXT:    ret void, [[DBG69:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p3_constant_mask_24thbit(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG61:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG62:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META57:metadata !.*]], metadata !DIExpression()), [[DBG62]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 16777216, [[DBG63:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META58:metadata !.*]], metadata !DIExpression()), [[DBG63]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG64:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META59:metadata !.*]], metadata !DIExpression()), [[DBG64]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG65:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META60:metadata !.*]], metadata !DIExpression()), [[DBG65]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG66:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG62]]
+; NOLZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG65]]
+; NOLZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG67:!dbg !.*]]
+; NOLZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG68:!dbg !.*]]
+; NOLZCNT-NEXT:    ret void, [[DBG69:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -114,26 +281,62 @@ loop:
   br i1 %x.curr.isbitunset, label %loop, label %end
 
 end:
-  ret i32 %x.curr
+  store i32 %x.curr, i32* %p0
+  store i32 %x.next, i32* %p1
+  ret void
 }
 
-define i32 @p3_constant_mask_15thbit(i32 %x) {
-; ALL-LABEL: @p3_constant_mask_15thbit(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG59:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG60:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META55:metadata !.*]], metadata !DIExpression()), [[DBG60]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 32768, [[DBG61:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META56:metadata !.*]], metadata !DIExpression()), [[DBG61]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG62:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META57:metadata !.*]], metadata !DIExpression()), [[DBG62]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG63:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META58:metadata !.*]], metadata !DIExpression()), [[DBG63]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG64:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG60]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG65:!dbg !.*]]
+define void @p4_constant_mask_15thbit(i32 %x, i32* %p0, i32* %p1) {
+; LZCNT-LABEL: @p4_constant_mask_15thbit(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], 65535, [[DBG76:!dbg !.*]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG76]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG76]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG76]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 15, [[X_MASKED_LEADINGONEPOS]], [[DBG76]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG76]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG76]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X]], [[LOOP_TRIPCOUNT]], [[DBG76]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG77:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG76]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG76]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META72:metadata !.*]], metadata !DIExpression()), [[DBG76]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], 32768, [[DBG78:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META73:metadata !.*]], metadata !DIExpression()), [[DBG78]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG79:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META74:metadata !.*]], metadata !DIExpression()), [[DBG79]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG80:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META75:metadata !.*]], metadata !DIExpression()), [[DBG80]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG81:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG81]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG81]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG76]]
+; LZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG80]]
+; LZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG82:!dbg !.*]]
+; LZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG83:!dbg !.*]]
+; LZCNT-NEXT:    ret void, [[DBG84:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p4_constant_mask_15thbit(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG76:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG77:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META72:metadata !.*]], metadata !DIExpression()), [[DBG77]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 32768, [[DBG78:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META73:metadata !.*]], metadata !DIExpression()), [[DBG78]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG79:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META74:metadata !.*]], metadata !DIExpression()), [[DBG79]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG80:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META75:metadata !.*]], metadata !DIExpression()), [[DBG80]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG81:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG77]]
+; NOLZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG80]]
+; NOLZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG82:!dbg !.*]]
+; NOLZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG83:!dbg !.*]]
+; NOLZCNT-NEXT:    ret void, [[DBG84:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -146,29 +349,69 @@ loop:
   br i1 %x.curr.isbitunset, label %loop, label %end
 
 end:
-  ret i32 %x.curr
+  store i32 %x.curr, i32* %p0
+  store i32 %x.next, i32* %p1
+  ret void
 }
 
-; We don't particularly care whether %x.curr or %x.curr will live-out.
-define i32 @p4_different_liveout(i32 %x, i32 %bit) {
-; ALL-LABEL: @p4_different_liveout(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG73:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META68:metadata !.*]], metadata !DIExpression()), [[DBG73]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG74:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG75:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META69:metadata !.*]], metadata !DIExpression()), [[DBG75]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG76:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META70:metadata !.*]], metadata !DIExpression()), [[DBG76]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG77:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META71:metadata !.*]], metadata !DIExpression()), [[DBG77]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG78:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META72:metadata !.*]], metadata !DIExpression()), [[DBG78]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG79:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG78]]
-; ALL-NEXT:    ret i32 [[X_NEXT_LCSSA]], [[DBG80:!dbg !.*]]
+; All no-wrap flags can be kept on the shift.
+define void @p5_nuw(i32 %x, i32 %bit, i32* %p0, i32* %p1) {
+; LZCNT-LABEL: @p5_nuw(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG92:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META87:metadata !.*]], metadata !DIExpression()), [[DBG92]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG93:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG93]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG93]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG93]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG93]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG93]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG93]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG93]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl nuw i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG93]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl nuw i32 [[X]], [[LOOP_TRIPCOUNT]], [[DBG93]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG94:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG93]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG93]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META88:metadata !.*]], metadata !DIExpression()), [[DBG93]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG95:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META89:metadata !.*]], metadata !DIExpression()), [[DBG95]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG96:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META90:metadata !.*]], metadata !DIExpression()), [[DBG96]]
+; LZCNT-NEXT:    [[TMP1]] = shl nuw i32 [[TMP0]], 1, [[DBG97:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META91:metadata !.*]], metadata !DIExpression()), [[DBG97]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG98:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG98]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG98]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG93]]
+; LZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG97]]
+; LZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG99:!dbg !.*]]
+; LZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG100:!dbg !.*]]
+; LZCNT-NEXT:    ret void, [[DBG101:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p5_nuw(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG92:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META87:metadata !.*]], metadata !DIExpression()), [[DBG92]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG93:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG94:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META88:metadata !.*]], metadata !DIExpression()), [[DBG94]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG95:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META89:metadata !.*]], metadata !DIExpression()), [[DBG95]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG96:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META90:metadata !.*]], metadata !DIExpression()), [[DBG96]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl nuw i32 [[X_CURR]], 1, [[DBG97:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META91:metadata !.*]], metadata !DIExpression()), [[DBG97]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG98:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG94]]
+; NOLZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG97]]
+; NOLZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG99:!dbg !.*]]
+; NOLZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG100:!dbg !.*]]
+; NOLZCNT-NEXT:    ret void, [[DBG101:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -178,35 +421,71 @@ loop:
   %x.curr = phi i32 [ %x, %entry ], [ %x.next, %loop ]
   %x.curr.bitmasked = and i32 %x.curr, %bitmask
   %x.curr.isbitunset = icmp eq i32 %x.curr.bitmasked, 0
-  %x.next = shl i32 %x.curr, 1
+  %x.next = shl nuw i32 %x.curr, 1
   br i1 %x.curr.isbitunset, label %loop, label %end
 
 end:
-  ret i32 %x.next ; not %x.curr
+  store i32 %x.curr, i32* %p0
+  store i32 %x.next, i32* %p1
+  ret void
 }
-; Even both of them being live-out is fine.
-define void @p5_both_liveout(i32 %x, i32 %bit, i32* %p0, i32* %p1) {
-; ALL-LABEL: @p5_both_liveout(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG88:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META83:metadata !.*]], metadata !DIExpression()), [[DBG88]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG89:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG90:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META84:metadata !.*]], metadata !DIExpression()), [[DBG90]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG91:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META85:metadata !.*]], metadata !DIExpression()), [[DBG91]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG92:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META86:metadata !.*]], metadata !DIExpression()), [[DBG92]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG93:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META87:metadata !.*]], metadata !DIExpression()), [[DBG93]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG94:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG90]]
-; ALL-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG93]]
-; ALL-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG95:!dbg !.*]]
-; ALL-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG96:!dbg !.*]]
-; ALL-NEXT:    ret void, [[DBG97:!dbg !.*]]
+define void @p6_nsw(i32 %x, i32 %bit, i32* %p0, i32* %p1) {
+; LZCNT-LABEL: @p6_nsw(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG109:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META104:metadata !.*]], metadata !DIExpression()), [[DBG109]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG110:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG110]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG110]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG110]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG110]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG110]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG110]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG110]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl nsw i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG110]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl nsw i32 [[X]], [[LOOP_TRIPCOUNT]], [[DBG110]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG111:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG110]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG110]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META105:metadata !.*]], metadata !DIExpression()), [[DBG110]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG112:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META106:metadata !.*]], metadata !DIExpression()), [[DBG112]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG113:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META107:metadata !.*]], metadata !DIExpression()), [[DBG113]]
+; LZCNT-NEXT:    [[TMP1]] = shl nsw i32 [[TMP0]], 1, [[DBG114:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META108:metadata !.*]], metadata !DIExpression()), [[DBG114]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG115:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG115]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG115]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG110]]
+; LZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG114]]
+; LZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG116:!dbg !.*]]
+; LZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG117:!dbg !.*]]
+; LZCNT-NEXT:    ret void, [[DBG118:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p6_nsw(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG109:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META104:metadata !.*]], metadata !DIExpression()), [[DBG109]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG110:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG111:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META105:metadata !.*]], metadata !DIExpression()), [[DBG111]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG112:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META106:metadata !.*]], metadata !DIExpression()), [[DBG112]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG113:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META107:metadata !.*]], metadata !DIExpression()), [[DBG113]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl nsw i32 [[X_CURR]], 1, [[DBG114:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META108:metadata !.*]], metadata !DIExpression()), [[DBG114]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG115:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG111]]
+; NOLZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG114]]
+; NOLZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG116:!dbg !.*]]
+; NOLZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG117:!dbg !.*]]
+; NOLZCNT-NEXT:    ret void, [[DBG118:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -216,7 +495,7 @@ loop:
   %x.curr = phi i32 [ %x, %entry ], [ %x.next, %loop ]
   %x.curr.bitmasked = and i32 %x.curr, %bitmask
   %x.curr.isbitunset = icmp eq i32 %x.curr.bitmasked, 0
-  %x.next = shl i32 %x.curr, 1
+  %x.next = shl nsw i32 %x.curr, 1
   br i1 %x.curr.isbitunset, label %loop, label %end
 
 end:
@@ -224,24 +503,131 @@ end:
   store i32 %x.next, i32* %p1
   ret void
 }
+define void @p7_nuwnsw(i32 %x, i32 %bit, i32* %p0, i32* %p1) {
+; LZCNT-LABEL: @p7_nuwnsw(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG126:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META121:metadata !.*]], metadata !DIExpression()), [[DBG126]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG127:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG127]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG127]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG127]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG127]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG127]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG127]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG127]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl nuw nsw i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG127]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl nuw nsw i32 [[X]], [[LOOP_TRIPCOUNT]], [[DBG127]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG128:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG127]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG127]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META122:metadata !.*]], metadata !DIExpression()), [[DBG127]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG129:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META123:metadata !.*]], metadata !DIExpression()), [[DBG129]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG130:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META124:metadata !.*]], metadata !DIExpression()), [[DBG130]]
+; LZCNT-NEXT:    [[TMP1]] = shl nuw nsw i32 [[TMP0]], 1, [[DBG131:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META125:metadata !.*]], metadata !DIExpression()), [[DBG131]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG132:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG132]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG132]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG127]]
+; LZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG131]]
+; LZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG133:!dbg !.*]]
+; LZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG134:!dbg !.*]]
+; LZCNT-NEXT:    ret void, [[DBG135:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p7_nuwnsw(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG126:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META121:metadata !.*]], metadata !DIExpression()), [[DBG126]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG127:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG128:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META122:metadata !.*]], metadata !DIExpression()), [[DBG128]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG129:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META123:metadata !.*]], metadata !DIExpression()), [[DBG129]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG130:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META124:metadata !.*]], metadata !DIExpression()), [[DBG130]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl nuw nsw i32 [[X_CURR]], 1, [[DBG131:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META125:metadata !.*]], metadata !DIExpression()), [[DBG131]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG132:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG128]]
+; NOLZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG131]]
+; NOLZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG133:!dbg !.*]]
+; NOLZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG134:!dbg !.*]]
+; NOLZCNT-NEXT:    ret void, [[DBG135:!dbg !.*]]
+;
+entry:
+  %bitmask = shl i32 1, %bit
+  br label %loop
 
-define i32 @p6_constant_mask_signbit_noncanonical(i32 %x) {
-; ALL-LABEL: @p6_constant_mask_signbit_noncanonical(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG104:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG105:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META100:metadata !.*]], metadata !DIExpression()), [[DBG105]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], -2147483648, [[DBG106:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META101:metadata !.*]], metadata !DIExpression()), [[DBG106]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG107:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META102:metadata !.*]], metadata !DIExpression()), [[DBG107]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG108:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META103:metadata !.*]], metadata !DIExpression()), [[DBG108]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG109:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG105]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG110:!dbg !.*]]
+loop:
+  %x.curr = phi i32 [ %x, %entry ], [ %x.next, %loop ]
+  %x.curr.bitmasked = and i32 %x.curr, %bitmask
+  %x.curr.isbitunset = icmp eq i32 %x.curr.bitmasked, 0
+  %x.next = shl nuw nsw i32 %x.curr, 1
+  br i1 %x.curr.isbitunset, label %loop, label %end
+
+end:
+  store i32 %x.curr, i32* %p0
+  store i32 %x.next, i32* %p1
+  ret void
+}
+
+define void @p8_constant_mask_signbit_noncanonical(i32 %x, i32* %p0, i32* %p1) {
+; LZCNT-LABEL: @p8_constant_mask_signbit_noncanonical(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[X_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), [[DBG142:!dbg !.*]]
+; LZCNT-NEXT:    [[X_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_NUMLEADINGZEROS]], [[DBG142]]
+; LZCNT-NEXT:    [[X_LEADINGONEPOS:%.*]] = add i32 [[X_NUMACTIVEBITS]], -1, [[DBG142]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 31, [[X_LEADINGONEPOS]], [[DBG142]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG142]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG142]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG142]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG143:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG142]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG142]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META138:metadata !.*]], metadata !DIExpression()), [[DBG142]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], -2147483648, [[DBG144:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META139:metadata !.*]], metadata !DIExpression()), [[DBG144]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG145:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META140:metadata !.*]], metadata !DIExpression()), [[DBG145]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG146:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META141:metadata !.*]], metadata !DIExpression()), [[DBG146]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG147:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG147]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG147]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG142]]
+; LZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG146]]
+; LZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG148:!dbg !.*]]
+; LZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG149:!dbg !.*]]
+; LZCNT-NEXT:    ret void, [[DBG150:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p8_constant_mask_signbit_noncanonical(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG142:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG143:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META138:metadata !.*]], metadata !DIExpression()), [[DBG143]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], -2147483648, [[DBG144:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META139:metadata !.*]], metadata !DIExpression()), [[DBG144]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG145:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META140:metadata !.*]], metadata !DIExpression()), [[DBG145]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG146:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META141:metadata !.*]], metadata !DIExpression()), [[DBG146]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG147:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG143]]
+; NOLZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG146]]
+; NOLZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG148:!dbg !.*]]
+; NOLZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG149:!dbg !.*]]
+; NOLZCNT-NEXT:    ret void, [[DBG150:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -254,24 +640,57 @@ loop:
   br i1 %x.curr.isbitunset, label %loop, label %end
 
 end:
-  ret i32 %x.curr
+  store i32 %x.curr, i32* %p0
+  store i32 %x.next, i32* %p1
+  ret void
 }
 
-define i32 @p7_constant_mask_signbit_canonical(i32 %x) {
-; ALL-LABEL: @p7_constant_mask_signbit_canonical(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG116:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG117:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META113:metadata !.*]], metadata !DIExpression()), [[DBG117]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp sgt i32 [[X_CURR]], -1, [[DBG118:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META114:metadata !.*]], metadata !DIExpression()), [[DBG118]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG119:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META115:metadata !.*]], metadata !DIExpression()), [[DBG119]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG120:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG117]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG121:!dbg !.*]]
+define void @p9_constant_mask_signbit_canonical(i32 %x, i32* %p0, i32* %p1) {
+; LZCNT-LABEL: @p9_constant_mask_signbit_canonical(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[X_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), [[DBG156:!dbg !.*]]
+; LZCNT-NEXT:    [[X_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_NUMLEADINGZEROS]], [[DBG156]]
+; LZCNT-NEXT:    [[X_LEADINGONEPOS:%.*]] = add i32 [[X_NUMACTIVEBITS]], -1, [[DBG156]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 31, [[X_LEADINGONEPOS]], [[DBG156]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG156]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG156]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG156]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG157:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG156]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG156]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META153:metadata !.*]], metadata !DIExpression()), [[DBG156]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp sgt i32 [[TMP0]], -1, [[DBG158:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META154:metadata !.*]], metadata !DIExpression()), [[DBG158]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG159:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META155:metadata !.*]], metadata !DIExpression()), [[DBG159]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG160:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG160]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG160]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG156]]
+; LZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG159]]
+; LZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG161:!dbg !.*]]
+; LZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG162:!dbg !.*]]
+; LZCNT-NEXT:    ret void, [[DBG163:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p9_constant_mask_signbit_canonical(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG156:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG157:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META153:metadata !.*]], metadata !DIExpression()), [[DBG157]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp sgt i32 [[X_CURR]], -1, [[DBG158:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META154:metadata !.*]], metadata !DIExpression()), [[DBG158]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG159:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META155:metadata !.*]], metadata !DIExpression()), [[DBG159]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG160:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG157]]
+; NOLZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG159]]
+; NOLZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG161:!dbg !.*]]
+; NOLZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG162:!dbg !.*]]
+; NOLZCNT-NEXT:    ret void, [[DBG163:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -283,29 +702,138 @@ loop:
   br i1 %x.curr.isbitunset, label %loop, label %end
 
 end:
-  ret i32 %x.curr
+  store i32 %x.curr, i32* %p0
+  store i32 %x.next, i32* %p1
+  ret void
+}
+
+define void @p10_x_is_not_one(i32 %bit, i32* %p0, i32* %p1) {
+; LZCNT-LABEL: @p10_x_is_not_one(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG171:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META166:metadata !.*]], metadata !DIExpression()), [[DBG171]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG172:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG172]]
+; LZCNT-NEXT:    [[DOTMASKED:%.*]] = and i32 2, [[BIT_MASK]], [[DBG172]]
+; LZCNT-NEXT:    [[DOTMASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[DOTMASKED]], i1 true), [[DBG172]]
+; LZCNT-NEXT:    [[DOTMASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[DOTMASKED_NUMLEADINGZEROS]], [[DBG172]]
+; LZCNT-NEXT:    [[DOTMASKED_LEADINGONEPOS:%.*]] = add i32 [[DOTMASKED_NUMACTIVEBITS]], -1, [[DBG172]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[DOTMASKED_LEADINGONEPOS]], [[DBG172]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG172]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 2, [[LOOP_BACKEDGETAKENCOUNT]], [[DBG172]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG172]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG173:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG172]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ 2, [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG172]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META167:metadata !.*]], metadata !DIExpression()), [[DBG172]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG174:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META168:metadata !.*]], metadata !DIExpression()), [[DBG174]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG175:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META169:metadata !.*]], metadata !DIExpression()), [[DBG175]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG176:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META170:metadata !.*]], metadata !DIExpression()), [[DBG176]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG177:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG177]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG177]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG172]]
+; LZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG176]]
+; LZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG178:!dbg !.*]]
+; LZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG179:!dbg !.*]]
+; LZCNT-NEXT:    ret void, [[DBG180:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p10_x_is_not_one(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG171:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META166:metadata !.*]], metadata !DIExpression()), [[DBG171]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG172:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ 2, [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG173:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META167:metadata !.*]], metadata !DIExpression()), [[DBG173]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG174:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META168:metadata !.*]], metadata !DIExpression()), [[DBG174]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG175:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META169:metadata !.*]], metadata !DIExpression()), [[DBG175]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG176:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META170:metadata !.*]], metadata !DIExpression()), [[DBG176]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG177:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG173]]
+; NOLZCNT-NEXT:    [[X_NEXT_LCSSA:%.*]] = phi i32 [ [[X_NEXT]], [[LOOP]] ], [[DBG176]]
+; NOLZCNT-NEXT:    store i32 [[X_CURR_LCSSA]], i32* [[P0:%.*]], align 4, [[DBG178:!dbg !.*]]
+; NOLZCNT-NEXT:    store i32 [[X_NEXT_LCSSA]], i32* [[P1:%.*]], align 4, [[DBG179:!dbg !.*]]
+; NOLZCNT-NEXT:    ret void, [[DBG180:!dbg !.*]]
+;
+entry:
+  %bitmask = shl i32 1, %bit
+  br label %loop
+
+loop:
+  %x.curr = phi i32 [ 2, %entry ], [ %x.next, %loop ]
+  %x.curr.bitmasked = and i32 %x.curr, %bitmask
+  %x.curr.isbitunset = icmp eq i32 %x.curr.bitmasked, 0
+  %x.next = shl i32 %x.curr, 1
+  br i1 %x.curr.isbitunset, label %loop, label %end
+
+end:
+  store i32 %x.curr, i32* %p0
+  store i32 %x.next, i32* %p1
+  ret void
 }
 
 ; Check that loop backedge's cmp-br order is correctly handled
-define i32 @p8(i32 %x, i32 %bit) {
-; ALL-LABEL: @p8(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG129:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META124:metadata !.*]], metadata !DIExpression()), [[DBG129]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG130:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG131:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META125:metadata !.*]], metadata !DIExpression()), [[DBG131]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG132:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META126:metadata !.*]], metadata !DIExpression()), [[DBG132]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp ne i32 [[X_CURR_BITMASKED]], 0, [[DBG133:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META127:metadata !.*]], metadata !DIExpression()), [[DBG133]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG134:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META128:metadata !.*]], metadata !DIExpression()), [[DBG134]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[END:%.*]], label [[LOOP]], [[DBG135:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG131]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG136:!dbg !.*]]
+define i32 @p11(i32 %x, i32 %bit) {
+; LZCNT-LABEL: @p11(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG188:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META183:metadata !.*]], metadata !DIExpression()), [[DBG188]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG189:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG189]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG189]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG189]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG189]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG189]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG189]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG189]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG189]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG189]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG190:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG189]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG189]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META184:metadata !.*]], metadata !DIExpression()), [[DBG189]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG191:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META185:metadata !.*]], metadata !DIExpression()), [[DBG191]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp ne i32 [[X_CURR_BITMASKED]], 0, [[DBG192:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META186:metadata !.*]], metadata !DIExpression()), [[DBG192]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG193:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META187:metadata !.*]], metadata !DIExpression()), [[DBG193]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG194:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG194]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG194]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG189]]
+; LZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG195:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p11(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG188:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META183:metadata !.*]], metadata !DIExpression()), [[DBG188]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG189:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG190:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META184:metadata !.*]], metadata !DIExpression()), [[DBG190]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG191:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META185:metadata !.*]], metadata !DIExpression()), [[DBG191]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp ne i32 [[X_CURR_BITMASKED]], 0, [[DBG192:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META186:metadata !.*]], metadata !DIExpression()), [[DBG192]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG193:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META187:metadata !.*]], metadata !DIExpression()), [[DBG193]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[END:%.*]], label [[LOOP]], [[DBG194:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG190]]
+; NOLZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG195:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -323,25 +851,57 @@ end:
 }
 
 ; `and` is commutative, so ensure that order is irrelevant
-define i32 @p9(i32 %x, i32 %bit) {
-; ALL-LABEL: @p9(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG144:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META139:metadata !.*]], metadata !DIExpression()), [[DBG144]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG145:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG146:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META140:metadata !.*]], metadata !DIExpression()), [[DBG146]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[BITMASK]], [[X_CURR]], [[DBG147:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META141:metadata !.*]], metadata !DIExpression()), [[DBG147]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG148:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META142:metadata !.*]], metadata !DIExpression()), [[DBG148]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG149:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META143:metadata !.*]], metadata !DIExpression()), [[DBG149]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG150:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG146]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG151:!dbg !.*]]
+define i32 @p12(i32 %x, i32 %bit) {
+; LZCNT-LABEL: @p12(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG203:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META198:metadata !.*]], metadata !DIExpression()), [[DBG203]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG204:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG204]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG204]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG204]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG204]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG204]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG204]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG204]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG204]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG204]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG205:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG204]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG204]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META199:metadata !.*]], metadata !DIExpression()), [[DBG204]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[BITMASK]], [[TMP0]], [[DBG206:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META200:metadata !.*]], metadata !DIExpression()), [[DBG206]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG207:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META201:metadata !.*]], metadata !DIExpression()), [[DBG207]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG208:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META202:metadata !.*]], metadata !DIExpression()), [[DBG208]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG209:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG209]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG209]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG204]]
+; LZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG210:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p12(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG203:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META198:metadata !.*]], metadata !DIExpression()), [[DBG203]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG204:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG205:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META199:metadata !.*]], metadata !DIExpression()), [[DBG205]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[BITMASK]], [[X_CURR]], [[DBG206:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META200:metadata !.*]], metadata !DIExpression()), [[DBG206]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG207:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META201:metadata !.*]], metadata !DIExpression()), [[DBG207]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG208:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META202:metadata !.*]], metadata !DIExpression()), [[DBG208]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG209:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG205]]
+; NOLZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG210:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -360,25 +920,57 @@ end:
 
 ; PHI node does not have any particular order for it's incomings,
 ; but check that the other order still works.
-define i32 @p10(i32 %x, i32 %bit) {
-; ALL-LABEL: @p10(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG159:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META154:metadata !.*]], metadata !DIExpression()), [[DBG159]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG160:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X_NEXT:%.*]], [[LOOP]] ], [ [[X:%.*]], [[ENTRY:%.*]] ], [[DBG161:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META155:metadata !.*]], metadata !DIExpression()), [[DBG161]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG162:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META156:metadata !.*]], metadata !DIExpression()), [[DBG162]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG163:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META157:metadata !.*]], metadata !DIExpression()), [[DBG163]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG164:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META158:metadata !.*]], metadata !DIExpression()), [[DBG164]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG165:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG161]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG166:!dbg !.*]]
+define i32 @p13(i32 %x, i32 %bit) {
+; LZCNT-LABEL: @p13(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG218:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META213:metadata !.*]], metadata !DIExpression()), [[DBG218]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG219:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG219]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG219]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG219]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG219]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG219]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG219]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG219]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG219]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG219]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG220:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG219]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[TMP1:%.*]], [[LOOP]] ], [ [[X]], [[ENTRY]] ], [[DBG219]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META214:metadata !.*]], metadata !DIExpression()), [[DBG219]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG221:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META215:metadata !.*]], metadata !DIExpression()), [[DBG221]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG222:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META216:metadata !.*]], metadata !DIExpression()), [[DBG222]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG223:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META217:metadata !.*]], metadata !DIExpression()), [[DBG223]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG224:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG224]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG224]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG219]]
+; LZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG225:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p13(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG218:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META213:metadata !.*]], metadata !DIExpression()), [[DBG218]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG219:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X_NEXT:%.*]], [[LOOP]] ], [ [[X:%.*]], [[ENTRY:%.*]] ], [[DBG220:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META214:metadata !.*]], metadata !DIExpression()), [[DBG220]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG221:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META215:metadata !.*]], metadata !DIExpression()), [[DBG221]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG222:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META216:metadata !.*]], metadata !DIExpression()), [[DBG222]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG223:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META217:metadata !.*]], metadata !DIExpression()), [[DBG223]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG224:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG220]]
+; NOLZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG225:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -396,21 +988,46 @@ end:
 }
 
 ; ICmp-Br are commutative
-define i32 @p11(i32 %x) {
-; ALL-LABEL: @p11(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG172:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG173:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META169:metadata !.*]], metadata !DIExpression()), [[DBG173]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp slt i32 [[X_CURR]], 0, [[DBG174:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META170:metadata !.*]], metadata !DIExpression()), [[DBG174]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG175:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META171:metadata !.*]], metadata !DIExpression()), [[DBG175]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[END:%.*]], label [[LOOP]], [[DBG176:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG173]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG177:!dbg !.*]]
+define i32 @p14(i32 %x) {
+; LZCNT-LABEL: @p14(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[X_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), [[DBG231:!dbg !.*]]
+; LZCNT-NEXT:    [[X_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_NUMLEADINGZEROS]], [[DBG231]]
+; LZCNT-NEXT:    [[X_LEADINGONEPOS:%.*]] = add i32 [[X_NUMACTIVEBITS]], -1, [[DBG231]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 31, [[X_LEADINGONEPOS]], [[DBG231]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG231]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG231]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG231]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG232:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG231]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG231]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META228:metadata !.*]], metadata !DIExpression()), [[DBG231]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp slt i32 [[TMP0]], 0, [[DBG233:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META229:metadata !.*]], metadata !DIExpression()), [[DBG233]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG234:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META230:metadata !.*]], metadata !DIExpression()), [[DBG234]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG235:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG235]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG235]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG231]]
+; LZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG236:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @p14(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG231:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG232:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META228:metadata !.*]], metadata !DIExpression()), [[DBG232]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp slt i32 [[X_CURR]], 0, [[DBG233:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META229:metadata !.*]], metadata !DIExpression()), [[DBG233]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG234:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META230:metadata !.*]], metadata !DIExpression()), [[DBG234]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[END:%.*]], label [[LOOP]], [[DBG235:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG232]]
+; NOLZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG236:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -429,25 +1046,25 @@ end:
 ; Negative tests
 
 ; The %bitmask must be outside of the loop.
-define i32 @n12(i32 %x, i32 %bit) {
-; ALL-LABEL: @n12(
+define i32 @n15(i32 %x, i32 %bit) {
+; ALL-LABEL: @n15(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG185:!dbg !.*]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG244:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG186:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META180:metadata !.*]], metadata !DIExpression()), [[DBG186]]
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG187:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META181:metadata !.*]], metadata !DIExpression()), [[DBG187]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG188:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META182:metadata !.*]], metadata !DIExpression()), [[DBG188]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG189:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META183:metadata !.*]], metadata !DIExpression()), [[DBG189]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG190:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META184:metadata !.*]], metadata !DIExpression()), [[DBG190]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG191:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG245:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META239:metadata !.*]], metadata !DIExpression()), [[DBG245]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG246:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META240:metadata !.*]], metadata !DIExpression()), [[DBG246]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG247:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META241:metadata !.*]], metadata !DIExpression()), [[DBG247]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG248:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META242:metadata !.*]], metadata !DIExpression()), [[DBG248]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG249:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META243:metadata !.*]], metadata !DIExpression()), [[DBG249]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG250:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG186]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG192:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG245]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG251:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -465,25 +1082,25 @@ end:
 }
 
 ; The %bitmask must be loop-invariant
-define i32 @n13(i32 %x, i32 %bit) {
-; ALL-LABEL: @n13(
+define i32 @n16(i32 %x, i32 %bit) {
+; ALL-LABEL: @n16(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG200:!dbg !.*]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG259:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG201:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META195:metadata !.*]], metadata !DIExpression()), [[DBG201]]
-; ALL-NEXT:    [[BITMASK:%.*]] = call i32 @gen32(), [[DBG202:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META196:metadata !.*]], metadata !DIExpression()), [[DBG202]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG203:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META197:metadata !.*]], metadata !DIExpression()), [[DBG203]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG204:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META198:metadata !.*]], metadata !DIExpression()), [[DBG204]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG205:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META199:metadata !.*]], metadata !DIExpression()), [[DBG205]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG206:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG260:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META254:metadata !.*]], metadata !DIExpression()), [[DBG260]]
+; ALL-NEXT:    [[BITMASK:%.*]] = call i32 @gen32(), [[DBG261:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META255:metadata !.*]], metadata !DIExpression()), [[DBG261]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG262:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META256:metadata !.*]], metadata !DIExpression()), [[DBG262]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG263:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META257:metadata !.*]], metadata !DIExpression()), [[DBG263]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG264:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META258:metadata !.*]], metadata !DIExpression()), [[DBG264]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG265:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG201]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG207:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG260]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG266:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -501,25 +1118,25 @@ end:
 }
 
 ; The %bitmask must be a left-shift of a single bit.
-define i32 @n14(i32 %x, i32 %bit) {
-; ALL-LABEL: @n14(
+define i32 @n17(i32 %x, i32 %bit) {
+; ALL-LABEL: @n17(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 2, [[BIT:%.*]], [[DBG215:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META210:metadata !.*]], metadata !DIExpression()), [[DBG215]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG216:!dbg !.*]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 2, [[BIT:%.*]], [[DBG274:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META269:metadata !.*]], metadata !DIExpression()), [[DBG274]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG275:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG217:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META211:metadata !.*]], metadata !DIExpression()), [[DBG217]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG218:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META212:metadata !.*]], metadata !DIExpression()), [[DBG218]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG219:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META213:metadata !.*]], metadata !DIExpression()), [[DBG219]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG220:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META214:metadata !.*]], metadata !DIExpression()), [[DBG220]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG221:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG276:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META270:metadata !.*]], metadata !DIExpression()), [[DBG276]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG277:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META271:metadata !.*]], metadata !DIExpression()), [[DBG277]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG278:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META272:metadata !.*]], metadata !DIExpression()), [[DBG278]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG279:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META273:metadata !.*]], metadata !DIExpression()), [[DBG279]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG280:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG217]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG222:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG276]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG281:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 2, %bit ; not what we are looking for.
@@ -537,25 +1154,25 @@ end:
 }
 
 ; Bad recurrence - should be a left-shift by 1.
-define i32 @n15(i32 %x, i32 %bit) {
-; ALL-LABEL: @n15(
+define i32 @n18(i32 %x, i32 %bit) {
+; ALL-LABEL: @n18(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG230:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META225:metadata !.*]], metadata !DIExpression()), [[DBG230]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG231:!dbg !.*]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG289:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META284:metadata !.*]], metadata !DIExpression()), [[DBG289]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG290:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG232:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META226:metadata !.*]], metadata !DIExpression()), [[DBG232]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG233:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META227:metadata !.*]], metadata !DIExpression()), [[DBG233]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG234:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META228:metadata !.*]], metadata !DIExpression()), [[DBG234]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 2, [[DBG235:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META229:metadata !.*]], metadata !DIExpression()), [[DBG235]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG236:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG291:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META285:metadata !.*]], metadata !DIExpression()), [[DBG291]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG292:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META286:metadata !.*]], metadata !DIExpression()), [[DBG292]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG293:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META287:metadata !.*]], metadata !DIExpression()), [[DBG293]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 2, [[DBG294:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META288:metadata !.*]], metadata !DIExpression()), [[DBG294]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG295:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG232]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG237:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG291]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG296:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -573,25 +1190,25 @@ end:
 }
 
 ; The comparison is not what we are looking for.
-define i32 @n16(i32 %x, i32 %bit) {
-; ALL-LABEL: @n16(
+define i32 @n19(i32 %x, i32 %bit) {
+; ALL-LABEL: @n19(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG245:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META240:metadata !.*]], metadata !DIExpression()), [[DBG245]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG246:!dbg !.*]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG304:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META299:metadata !.*]], metadata !DIExpression()), [[DBG304]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG305:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG247:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META241:metadata !.*]], metadata !DIExpression()), [[DBG247]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG248:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META242:metadata !.*]], metadata !DIExpression()), [[DBG248]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp ne i32 [[X_CURR_BITMASKED]], [[BITMASK]], [[DBG249:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META243:metadata !.*]], metadata !DIExpression()), [[DBG249]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG250:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META244:metadata !.*]], metadata !DIExpression()), [[DBG250]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG251:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG306:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META300:metadata !.*]], metadata !DIExpression()), [[DBG306]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG307:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META301:metadata !.*]], metadata !DIExpression()), [[DBG307]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp ne i32 [[X_CURR_BITMASKED]], [[BITMASK]], [[DBG308:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META302:metadata !.*]], metadata !DIExpression()), [[DBG308]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG309:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META303:metadata !.*]], metadata !DIExpression()), [[DBG309]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG310:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG247]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG252:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG306]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG311:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -609,25 +1226,25 @@ end:
 }
 
 ; We should loop while %x.curr.bitmasked is 0, not exit when it is 0.
-define i32 @n17(i32 %x, i32 %bit) {
-; ALL-LABEL: @n17(
+define i32 @n20(i32 %x, i32 %bit) {
+; ALL-LABEL: @n20(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG260:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META255:metadata !.*]], metadata !DIExpression()), [[DBG260]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG261:!dbg !.*]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG319:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META314:metadata !.*]], metadata !DIExpression()), [[DBG319]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG320:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG262:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META256:metadata !.*]], metadata !DIExpression()), [[DBG262]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG263:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META257:metadata !.*]], metadata !DIExpression()), [[DBG263]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG264:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META258:metadata !.*]], metadata !DIExpression()), [[DBG264]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG265:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META259:metadata !.*]], metadata !DIExpression()), [[DBG265]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[END:%.*]], label [[LOOP]], [[DBG266:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG321:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META315:metadata !.*]], metadata !DIExpression()), [[DBG321]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG322:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META316:metadata !.*]], metadata !DIExpression()), [[DBG322]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG323:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META317:metadata !.*]], metadata !DIExpression()), [[DBG323]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG324:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META318:metadata !.*]], metadata !DIExpression()), [[DBG324]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[END:%.*]], label [[LOOP]], [[DBG325:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG262]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG267:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG321]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG326:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -645,25 +1262,25 @@ end:
 }
 
 ; We should loop while %x.curr.bitmasked is 0, not while it is not 0.
-define i32 @n18(i32 %x, i32 %bit) {
-; ALL-LABEL: @n18(
+define i32 @n21(i32 %x, i32 %bit) {
+; ALL-LABEL: @n21(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG275:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META270:metadata !.*]], metadata !DIExpression()), [[DBG275]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG276:!dbg !.*]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG334:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META329:metadata !.*]], metadata !DIExpression()), [[DBG334]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG335:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG277:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META271:metadata !.*]], metadata !DIExpression()), [[DBG277]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG278:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META272:metadata !.*]], metadata !DIExpression()), [[DBG278]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp ne i32 [[X_CURR_BITMASKED]], 0, [[DBG279:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META273:metadata !.*]], metadata !DIExpression()), [[DBG279]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG280:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META274:metadata !.*]], metadata !DIExpression()), [[DBG280]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG281:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG336:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META330:metadata !.*]], metadata !DIExpression()), [[DBG336]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG337:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META331:metadata !.*]], metadata !DIExpression()), [[DBG337]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp ne i32 [[X_CURR_BITMASKED]], 0, [[DBG338:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META332:metadata !.*]], metadata !DIExpression()), [[DBG338]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG339:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META333:metadata !.*]], metadata !DIExpression()), [[DBG339]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG340:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG277]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG282:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG336]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG341:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -681,23 +1298,23 @@ end:
 }
 
 ; PHI node is not a recurrence
-define i32 @n19(i32 %x, i32 %bit) {
-; ALL-LABEL: @n19(
+define i32 @n22(i32 %x, i32 %bit) {
+; ALL-LABEL: @n22(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG290:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META285:metadata !.*]], metadata !DIExpression()), [[DBG290]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG291:!dbg !.*]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG349:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META344:metadata !.*]], metadata !DIExpression()), [[DBG349]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG350:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X:%.*]], [[META286:metadata !.*]], metadata !DIExpression()), [[DBG292:!dbg !.*]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X]], [[BITMASK]], [[DBG293:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META287:metadata !.*]], metadata !DIExpression()), [[DBG293]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG294:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META288:metadata !.*]], metadata !DIExpression()), [[DBG294]]
-; ALL-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X]], 1, [[DBG295:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META289:metadata !.*]], metadata !DIExpression()), [[DBG295]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG296:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X:%.*]], [[META345:metadata !.*]], metadata !DIExpression()), [[DBG351:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X]], [[BITMASK]], [[DBG352:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META346:metadata !.*]], metadata !DIExpression()), [[DBG352]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG353:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META347:metadata !.*]], metadata !DIExpression()), [[DBG353]]
+; ALL-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X]], 1, [[DBG354:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META348:metadata !.*]], metadata !DIExpression()), [[DBG354]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG355:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    ret i32 [[X]], [[DBG297:!dbg !.*]]
+; ALL-NEXT:    ret i32 [[X]], [[DBG356:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -715,25 +1332,25 @@ end:
 }
 
 ; Masking wrong value
-define i32 @n20(i32 %x, i32 %bit) {
-; ALL-LABEL: @n20(
+define i32 @n23(i32 %x, i32 %bit) {
+; ALL-LABEL: @n23(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG305:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META300:metadata !.*]], metadata !DIExpression()), [[DBG305]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG306:!dbg !.*]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG364:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META359:metadata !.*]], metadata !DIExpression()), [[DBG364]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG365:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG307:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META301:metadata !.*]], metadata !DIExpression()), [[DBG307]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X]], [[BITMASK]], [[DBG308:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META302:metadata !.*]], metadata !DIExpression()), [[DBG308]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG309:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META303:metadata !.*]], metadata !DIExpression()), [[DBG309]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG310:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META304:metadata !.*]], metadata !DIExpression()), [[DBG310]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG311:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG366:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META360:metadata !.*]], metadata !DIExpression()), [[DBG366]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X]], [[BITMASK]], [[DBG367:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META361:metadata !.*]], metadata !DIExpression()), [[DBG367]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG368:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META362:metadata !.*]], metadata !DIExpression()), [[DBG368]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG369:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META363:metadata !.*]], metadata !DIExpression()), [[DBG369]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG370:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG307]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG312:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG366]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG371:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -751,25 +1368,25 @@ end:
 }
 
 ; Checking wrong value
-define i32 @n21(i32 %x, i32 %bit) {
-; ALL-LABEL: @n21(
+define i32 @n24(i32 %x, i32 %bit) {
+; ALL-LABEL: @n24(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG320:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META315:metadata !.*]], metadata !DIExpression()), [[DBG320]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG321:!dbg !.*]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG379:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META374:metadata !.*]], metadata !DIExpression()), [[DBG379]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG380:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG322:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META316:metadata !.*]], metadata !DIExpression()), [[DBG322]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG323:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META317:metadata !.*]], metadata !DIExpression()), [[DBG323]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR]], 0, [[DBG324:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META318:metadata !.*]], metadata !DIExpression()), [[DBG324]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG325:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META319:metadata !.*]], metadata !DIExpression()), [[DBG325]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG326:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG381:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META375:metadata !.*]], metadata !DIExpression()), [[DBG381]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG382:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META376:metadata !.*]], metadata !DIExpression()), [[DBG382]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR]], 0, [[DBG383:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META377:metadata !.*]], metadata !DIExpression()), [[DBG383]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG384:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META378:metadata !.*]], metadata !DIExpression()), [[DBG384]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG385:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG322]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG327:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG381]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG386:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -787,25 +1404,25 @@ end:
 }
 
 ; Shifting wrong value
-define i32 @n22(i32 %x, i32 %bit) {
-; ALL-LABEL: @n22(
+define i32 @n25(i32 %x, i32 %bit) {
+; ALL-LABEL: @n25(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG335:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META330:metadata !.*]], metadata !DIExpression()), [[DBG335]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG336:!dbg !.*]]
+; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG394:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META389:metadata !.*]], metadata !DIExpression()), [[DBG394]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG395:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG337:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META331:metadata !.*]], metadata !DIExpression()), [[DBG337]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG338:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META332:metadata !.*]], metadata !DIExpression()), [[DBG338]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG339:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META333:metadata !.*]], metadata !DIExpression()), [[DBG339]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X]], 1, [[DBG340:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META334:metadata !.*]], metadata !DIExpression()), [[DBG340]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG341:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG396:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META390:metadata !.*]], metadata !DIExpression()), [[DBG396]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG397:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META391:metadata !.*]], metadata !DIExpression()), [[DBG397]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG398:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META392:metadata !.*]], metadata !DIExpression()), [[DBG398]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X]], 1, [[DBG399:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META393:metadata !.*]], metadata !DIExpression()), [[DBG399]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG400:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG337]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG342:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG396]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG401:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -823,23 +1440,23 @@ end:
 }
 
 ; Bit mask is not a power of 2
-define i32 @n23(i32 %x) {
-; ALL-LABEL: @n23(
+define i32 @n26(i32 %x) {
+; ALL-LABEL: @n26(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG349:!dbg !.*]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG408:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG350:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META345:metadata !.*]], metadata !DIExpression()), [[DBG350]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 16777215, [[DBG351:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META346:metadata !.*]], metadata !DIExpression()), [[DBG351]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG352:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META347:metadata !.*]], metadata !DIExpression()), [[DBG352]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG353:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META348:metadata !.*]], metadata !DIExpression()), [[DBG353]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG354:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG409:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META404:metadata !.*]], metadata !DIExpression()), [[DBG409]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 16777215, [[DBG410:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META405:metadata !.*]], metadata !DIExpression()), [[DBG410]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG411:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META406:metadata !.*]], metadata !DIExpression()), [[DBG411]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG412:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META407:metadata !.*]], metadata !DIExpression()), [[DBG412]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG413:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG350]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG355:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG409]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG414:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -856,23 +1473,23 @@ end:
 }
 
 ; Bit mask is not a power of 2
-define i32 @n24(i32 %x) {
-; ALL-LABEL: @n24(
+define i32 @n27(i32 %x) {
+; ALL-LABEL: @n27(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG362:!dbg !.*]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG421:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG363:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META358:metadata !.*]], metadata !DIExpression()), [[DBG363]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 384, [[DBG364:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META359:metadata !.*]], metadata !DIExpression()), [[DBG364]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG365:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META360:metadata !.*]], metadata !DIExpression()), [[DBG365]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG366:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META361:metadata !.*]], metadata !DIExpression()), [[DBG366]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG367:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG422:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META417:metadata !.*]], metadata !DIExpression()), [[DBG422]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 384, [[DBG423:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META418:metadata !.*]], metadata !DIExpression()), [[DBG423]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG424:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META419:metadata !.*]], metadata !DIExpression()), [[DBG424]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG425:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META420:metadata !.*]], metadata !DIExpression()), [[DBG425]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG426:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG363]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG368:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG422]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG427:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -889,23 +1506,23 @@ end:
 }
 
 ; Bit mask is not a power of 2
-define i32 @n25(i32 %x) {
-; ALL-LABEL: @n25(
+define i32 @n28(i32 %x) {
+; ALL-LABEL: @n28(
 ; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG375:!dbg !.*]]
+; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG434:!dbg !.*]]
 ; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG376:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META371:metadata !.*]], metadata !DIExpression()), [[DBG376]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 32896, [[DBG377:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META372:metadata !.*]], metadata !DIExpression()), [[DBG377]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG378:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META373:metadata !.*]], metadata !DIExpression()), [[DBG378]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG379:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META374:metadata !.*]], metadata !DIExpression()), [[DBG379]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG380:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG435:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META430:metadata !.*]], metadata !DIExpression()), [[DBG435]]
+; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], 32896, [[DBG436:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META431:metadata !.*]], metadata !DIExpression()), [[DBG436]]
+; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG437:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META432:metadata !.*]], metadata !DIExpression()), [[DBG437]]
+; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG438:!dbg !.*]]
+; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META433:metadata !.*]], metadata !DIExpression()), [[DBG438]]
+; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG439:!dbg !.*]]
 ; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG376]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG381:!dbg !.*]]
+; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG435]]
+; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG440:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -925,26 +1542,59 @@ end:
 ; Tests with extra cruft.
 
 ; If loop body has any extra instructions we don't want to deal with it.
-define i32 @n26(i32 %x, i32 %bit) {
-; ALL-LABEL: @n26(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG389:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META384:metadata !.*]], metadata !DIExpression()), [[DBG389]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG390:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG391:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META385:metadata !.*]], metadata !DIExpression()), [[DBG391]]
-; ALL-NEXT:    call void @external_side_effect(), [[DBG392:!dbg !.*]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG393:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META386:metadata !.*]], metadata !DIExpression()), [[DBG393]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG394:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META387:metadata !.*]], metadata !DIExpression()), [[DBG394]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG395:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META388:metadata !.*]], metadata !DIExpression()), [[DBG395]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG396:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG391]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG397:!dbg !.*]]
+define i32 @n29(i32 %x, i32 %bit) {
+; LZCNT-LABEL: @n29(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG448:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META443:metadata !.*]], metadata !DIExpression()), [[DBG448]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG449:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG449]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG449]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG449]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG449]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG449]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG449]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG449]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG449]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG449]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG450:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG449]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG449]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META444:metadata !.*]], metadata !DIExpression()), [[DBG449]]
+; LZCNT-NEXT:    call void @external_side_effect(), [[DBG451:!dbg !.*]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG452:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META445:metadata !.*]], metadata !DIExpression()), [[DBG452]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG453:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META446:metadata !.*]], metadata !DIExpression()), [[DBG453]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG454:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META447:metadata !.*]], metadata !DIExpression()), [[DBG454]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG455:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG455]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG455]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG449]]
+; LZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG456:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @n29(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG448:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META443:metadata !.*]], metadata !DIExpression()), [[DBG448]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG449:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG450:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META444:metadata !.*]], metadata !DIExpression()), [[DBG450]]
+; NOLZCNT-NEXT:    call void @external_side_effect(), [[DBG451:!dbg !.*]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG452:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META445:metadata !.*]], metadata !DIExpression()), [[DBG452]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG453:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META446:metadata !.*]], metadata !DIExpression()), [[DBG453]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG454:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META447:metadata !.*]], metadata !DIExpression()), [[DBG454]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG455:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG450]]
+; NOLZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG456:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -962,22 +1612,48 @@ end:
   ret i32 %x.curr
 }
 
-define i32 @n27(i32 %x) {
-; ALL-LABEL: @n27(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG403:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG404:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META400:metadata !.*]], metadata !DIExpression()), [[DBG404]]
-; ALL-NEXT:    call void @external_side_effect(), [[DBG405:!dbg !.*]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp sgt i32 [[X_CURR]], -1, [[DBG406:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META401:metadata !.*]], metadata !DIExpression()), [[DBG406]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG407:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META402:metadata !.*]], metadata !DIExpression()), [[DBG407]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG408:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG404]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG409:!dbg !.*]]
+define i32 @n30(i32 %x) {
+; LZCNT-LABEL: @n30(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[X_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), [[DBG462:!dbg !.*]]
+; LZCNT-NEXT:    [[X_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_NUMLEADINGZEROS]], [[DBG462]]
+; LZCNT-NEXT:    [[X_LEADINGONEPOS:%.*]] = add i32 [[X_NUMACTIVEBITS]], -1, [[DBG462]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 31, [[X_LEADINGONEPOS]], [[DBG462]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG462]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG462]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG462]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG463:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG462]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG462]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META459:metadata !.*]], metadata !DIExpression()), [[DBG462]]
+; LZCNT-NEXT:    call void @external_side_effect(), [[DBG464:!dbg !.*]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp sgt i32 [[TMP0]], -1, [[DBG465:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META460:metadata !.*]], metadata !DIExpression()), [[DBG465]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG466:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META461:metadata !.*]], metadata !DIExpression()), [[DBG466]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG467:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG467]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG467]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG462]]
+; LZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG468:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @n30(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG462:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG463:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META459:metadata !.*]], metadata !DIExpression()), [[DBG463]]
+; NOLZCNT-NEXT:    call void @external_side_effect(), [[DBG464:!dbg !.*]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp sgt i32 [[X_CURR]], -1, [[DBG465:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META460:metadata !.*]], metadata !DIExpression()), [[DBG465]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG466:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META461:metadata !.*]], metadata !DIExpression()), [[DBG466]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG467:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG463]]
+; NOLZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG468:!dbg !.*]]
 ;
 entry:
   br label %loop
@@ -994,27 +1670,61 @@ end:
 }
 
 ; In-loop instructions should not have uses outside of the loop.
-define i32 @n28(i32 %x, i32 %bit) {
-; ALL-LABEL: @n28(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG417:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META412:metadata !.*]], metadata !DIExpression()), [[DBG417]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG418:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG419:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META413:metadata !.*]], metadata !DIExpression()), [[DBG419]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG420:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META414:metadata !.*]], metadata !DIExpression()), [[DBG420]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG421:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META415:metadata !.*]], metadata !DIExpression()), [[DBG421]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG422:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META416:metadata !.*]], metadata !DIExpression()), [[DBG422]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG423:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG419]]
-; ALL-NEXT:    [[X_CURR_BITMASKED_LCSSA:%.*]] = phi i32 [ [[X_CURR_BITMASKED]], [[LOOP]] ], [[DBG420]]
-; ALL-NEXT:    call void @use32(i32 [[X_CURR_BITMASKED_LCSSA]]), [[DBG424:!dbg !.*]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG425:!dbg !.*]]
+define i32 @n31(i32 %x, i32 %bit) {
+; LZCNT-LABEL: @n31(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG476:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META471:metadata !.*]], metadata !DIExpression()), [[DBG476]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG477:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG477]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG477]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG477]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG477]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG477]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG477]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG477]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG477]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG477]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG478:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG477]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG477]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META472:metadata !.*]], metadata !DIExpression()), [[DBG477]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG479:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META473:metadata !.*]], metadata !DIExpression()), [[DBG479]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG480:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META474:metadata !.*]], metadata !DIExpression()), [[DBG480]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG481:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META475:metadata !.*]], metadata !DIExpression()), [[DBG481]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG482:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG482]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG482]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG477]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED_LCSSA:%.*]] = phi i32 [ [[X_CURR_BITMASKED]], [[LOOP]] ], [[DBG479]]
+; LZCNT-NEXT:    call void @use32(i32 [[X_CURR_BITMASKED_LCSSA]]), [[DBG483:!dbg !.*]]
+; LZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG484:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @n31(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG476:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META471:metadata !.*]], metadata !DIExpression()), [[DBG476]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG477:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG478:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META472:metadata !.*]], metadata !DIExpression()), [[DBG478]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG479:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META473:metadata !.*]], metadata !DIExpression()), [[DBG479]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG480:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META474:metadata !.*]], metadata !DIExpression()), [[DBG480]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG481:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META475:metadata !.*]], metadata !DIExpression()), [[DBG481]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG482:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG478]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED_LCSSA:%.*]] = phi i32 [ [[X_CURR_BITMASKED]], [[LOOP]] ], [[DBG479]]
+; NOLZCNT-NEXT:    call void @use32(i32 [[X_CURR_BITMASKED_LCSSA]]), [[DBG483:!dbg !.*]]
+; NOLZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG484:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
@@ -1031,27 +1741,61 @@ end:
   call void @use32(i32 %x.curr.bitmasked)
   ret i32 %x.curr
 }
-define i32 @n29(i32 %x, i32 %bit) {
-; ALL-LABEL: @n29(
-; ALL-NEXT:  entry:
-; ALL-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG433:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META428:metadata !.*]], metadata !DIExpression()), [[DBG433]]
-; ALL-NEXT:    br label [[LOOP:%.*]], [[DBG434:!dbg !.*]]
-; ALL:       loop:
-; ALL-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG435:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META429:metadata !.*]], metadata !DIExpression()), [[DBG435]]
-; ALL-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG436:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META430:metadata !.*]], metadata !DIExpression()), [[DBG436]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG437:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META431:metadata !.*]], metadata !DIExpression()), [[DBG437]]
-; ALL-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG438:!dbg !.*]]
-; ALL-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META432:metadata !.*]], metadata !DIExpression()), [[DBG438]]
-; ALL-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG439:!dbg !.*]]
-; ALL:       end:
-; ALL-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG435]]
-; ALL-NEXT:    [[X_CURR_ISBITUNSET_LCSSA:%.*]] = phi i1 [ [[X_CURR_ISBITUNSET]], [[LOOP]] ], [[DBG437]]
-; ALL-NEXT:    call void @use1(i1 [[X_CURR_ISBITUNSET_LCSSA]]), [[DBG440:!dbg !.*]]
-; ALL-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG441:!dbg !.*]]
+define i32 @n32(i32 %x, i32 %bit) {
+; LZCNT-LABEL: @n32(
+; LZCNT-NEXT:  entry:
+; LZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG492:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META487:metadata !.*]], metadata !DIExpression()), [[DBG492]]
+; LZCNT-NEXT:    [[BIT_LOWBITMASK:%.*]] = add i32 [[BITMASK]], -1, [[DBG493:!dbg !.*]]
+; LZCNT-NEXT:    [[BIT_MASK:%.*]] = or i32 [[BIT_LOWBITMASK]], [[BITMASK]], [[DBG493]]
+; LZCNT-NEXT:    [[X_MASKED:%.*]] = and i32 [[X:%.*]], [[BIT_MASK]], [[DBG493]]
+; LZCNT-NEXT:    [[X_MASKED_NUMLEADINGZEROS:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X_MASKED]], i1 true), [[DBG493]]
+; LZCNT-NEXT:    [[X_MASKED_NUMACTIVEBITS:%.*]] = sub i32 32, [[X_MASKED_NUMLEADINGZEROS]], [[DBG493]]
+; LZCNT-NEXT:    [[X_MASKED_LEADINGONEPOS:%.*]] = add i32 [[X_MASKED_NUMACTIVEBITS]], -1, [[DBG493]]
+; LZCNT-NEXT:    [[LOOP_BACKEDGETAKENCOUNT:%.*]] = sub i32 [[BIT]], [[X_MASKED_LEADINGONEPOS]], [[DBG493]]
+; LZCNT-NEXT:    [[LOOP_TRIPCOUNT:%.*]] = add nuw i32 [[LOOP_BACKEDGETAKENCOUNT]], 1, [[DBG493]]
+; LZCNT-NEXT:    [[X_CURR:%.*]] = shl i32 [[X]], [[LOOP_BACKEDGETAKENCOUNT]], [[DBG493]]
+; LZCNT-NEXT:    [[X_NEXT:%.*]] = shl i32 [[X_CURR]], 1, [[DBG493]]
+; LZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG494:!dbg !.*]]
+; LZCNT:       loop:
+; LZCNT-NEXT:    [[LOOP_IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[LOOP_IV_NEXT:%.*]], [[LOOP]] ], [[DBG493]]
+; LZCNT-NEXT:    [[TMP0:%.*]] = phi i32 [ [[X]], [[ENTRY]] ], [ [[TMP1:%.*]], [[LOOP]] ], [[DBG493]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP0]], [[META488:metadata !.*]], metadata !DIExpression()), [[DBG493]]
+; LZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[TMP0]], [[BITMASK]], [[DBG495:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META489:metadata !.*]], metadata !DIExpression()), [[DBG495]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG496:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META490:metadata !.*]], metadata !DIExpression()), [[DBG496]]
+; LZCNT-NEXT:    [[TMP1]] = shl i32 [[TMP0]], 1, [[DBG497:!dbg !.*]]
+; LZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[TMP1]], [[META491:metadata !.*]], metadata !DIExpression()), [[DBG497]]
+; LZCNT-NEXT:    [[LOOP_IV_NEXT]] = add nuw i32 [[LOOP_IV]], 1, [[DBG498:!dbg !.*]]
+; LZCNT-NEXT:    [[LOOP_IVCHECK:%.*]] = icmp eq i32 [[LOOP_IV_NEXT]], [[LOOP_TRIPCOUNT]], [[DBG498]]
+; LZCNT-NEXT:    br i1 [[LOOP_IVCHECK]], label [[END:%.*]], label [[LOOP]], [[DBG498]]
+; LZCNT:       end:
+; LZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG493]]
+; LZCNT-NEXT:    [[X_CURR_ISBITUNSET_LCSSA:%.*]] = phi i1 [ [[X_CURR_ISBITUNSET]], [[LOOP]] ], [[DBG496]]
+; LZCNT-NEXT:    call void @use1(i1 [[X_CURR_ISBITUNSET_LCSSA]]), [[DBG499:!dbg !.*]]
+; LZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG500:!dbg !.*]]
+;
+; NOLZCNT-LABEL: @n32(
+; NOLZCNT-NEXT:  entry:
+; NOLZCNT-NEXT:    [[BITMASK:%.*]] = shl i32 1, [[BIT:%.*]], [[DBG492:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[BITMASK]], [[META487:metadata !.*]], metadata !DIExpression()), [[DBG492]]
+; NOLZCNT-NEXT:    br label [[LOOP:%.*]], [[DBG493:!dbg !.*]]
+; NOLZCNT:       loop:
+; NOLZCNT-NEXT:    [[X_CURR:%.*]] = phi i32 [ [[X:%.*]], [[ENTRY:%.*]] ], [ [[X_NEXT:%.*]], [[LOOP]] ], [[DBG494:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR]], [[META488:metadata !.*]], metadata !DIExpression()), [[DBG494]]
+; NOLZCNT-NEXT:    [[X_CURR_BITMASKED:%.*]] = and i32 [[X_CURR]], [[BITMASK]], [[DBG495:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_CURR_BITMASKED]], [[META489:metadata !.*]], metadata !DIExpression()), [[DBG495]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET:%.*]] = icmp eq i32 [[X_CURR_BITMASKED]], 0, [[DBG496:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i1 [[X_CURR_ISBITUNSET]], [[META490:metadata !.*]], metadata !DIExpression()), [[DBG496]]
+; NOLZCNT-NEXT:    [[X_NEXT]] = shl i32 [[X_CURR]], 1, [[DBG497:!dbg !.*]]
+; NOLZCNT-NEXT:    call void @llvm.dbg.value(metadata i32 [[X_NEXT]], [[META491:metadata !.*]], metadata !DIExpression()), [[DBG497]]
+; NOLZCNT-NEXT:    br i1 [[X_CURR_ISBITUNSET]], label [[LOOP]], label [[END:%.*]], [[DBG498:!dbg !.*]]
+; NOLZCNT:       end:
+; NOLZCNT-NEXT:    [[X_CURR_LCSSA:%.*]] = phi i32 [ [[X_CURR]], [[LOOP]] ], [[DBG494]]
+; NOLZCNT-NEXT:    [[X_CURR_ISBITUNSET_LCSSA:%.*]] = phi i1 [ [[X_CURR_ISBITUNSET]], [[LOOP]] ], [[DBG496]]
+; NOLZCNT-NEXT:    call void @use1(i1 [[X_CURR_ISBITUNSET_LCSSA]]), [[DBG499:!dbg !.*]]
+; NOLZCNT-NEXT:    ret i32 [[X_CURR_LCSSA]], [[DBG500:!dbg !.*]]
 ;
 entry:
   %bitmask = shl i32 1, %bit
diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll
new file mode 100644
index 0000000000000..6c21bcae05c68
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/ARM/vctp-chains-inseltpoison.ll
@@ -0,0 +1,257 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -mtriple=thumbv8.1m.main -mattr=+mve %s -S -loop-reduce -o - | FileCheck %s
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "thumbv8.1m-arm-none-eabi"
+
+define float @vctp8(float* %0, i32 %1) {
+; CHECK-LABEL: @vctp8(
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 8)
+; CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP3]], 0
+; CHECK-NEXT:    [[TMP5:%.*]] = add nsw i32 [[TMP1:%.*]], -1
+; CHECK-NEXT:    [[TMP6:%.*]] = ptrtoint float* [[TMP0:%.*]] to i32
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[TMP6]], i32 0
+; CHECK-NEXT:    [[TMP8:%.*]] = add <4 x i32> [[TMP7]], <i32 -32, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP10:%.*]] = add <4 x i32> [[TMP4]], [[TMP9]]
+; CHECK-NEXT:    br label [[TMP11:%.*]]
+; CHECK:       11:
+; CHECK-NEXT:    [[TMP12:%.*]] = phi i32 [ [[TMP5]], [[TMP2:%.*]] ], [ [[TMP21:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP13:%.*]] = phi <4 x float> [ zeroinitializer, [[TMP2]] ], [ [[TMP19:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP14:%.*]] = phi <4 x i32> [ [[TMP10]], [[TMP2]] ], [ [[TMP17:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP15:%.*]] = tail call <16 x i1> @llvm.arm.mve.vctp8(i32 [[TMP12]])
+; CHECK-NEXT:    [[MASK:%.*]] = tail call <4 x i1> @v16i1_to_v4i1(<16 x i1> [[TMP15]])
+; CHECK-NEXT:    [[TMP16:%.*]] = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> [[TMP14]], i32 32, <4 x i1> [[MASK]])
+; CHECK-NEXT:    [[TMP17]] = extractvalue { <4 x float>, <4 x i32> } [[TMP16]], 1
+; CHECK-NEXT:    [[TMP18:%.*]] = extractvalue { <4 x float>, <4 x i32> } [[TMP16]], 0
+; CHECK-NEXT:    [[TMP19]] = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> [[TMP13]], <4 x float> [[TMP18]], <4 x i1> [[MASK]], <4 x float> [[TMP13]])
+; CHECK-NEXT:    [[TMP20:%.*]] = icmp sgt i32 [[TMP12]], 4
+; CHECK-NEXT:    [[TMP21]] = add i32 [[TMP12]], -4
+; CHECK-NEXT:    br i1 [[TMP20]], label [[TMP11]], label [[TMP22:%.*]]
+; CHECK:       22:
+; CHECK-NEXT:    [[TMP23:%.*]] = tail call i32 bitcast (i32 (...)* @vecAddAcrossF32Mve to i32 (<4 x float>)*)(<4 x float> [[TMP19]])
+; CHECK-NEXT:    [[TMP24:%.*]] = sitofp i32 [[TMP23]] to float
+; CHECK-NEXT:    [[TMP25:%.*]] = tail call float @llvm.fabs.f32(float [[TMP24]])
+; CHECK-NEXT:    ret float [[TMP25]]
+;
+  %3 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 8)
+  %4 = extractvalue { <4 x i32>, i32 } %3, 0
+  %5 = add nsw i32 %1, -1
+  %6 = ptrtoint float* %0 to i32
+  %7 = insertelement <4 x i32> poison, i32 %6, i32 0
+  %8 = add <4 x i32> %7, <i32 -32, i32 undef, i32 undef, i32 undef>
+  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
+  %10 = add <4 x i32> %4, %9
+  br label %11
+
+11:                                               ; preds = %11, %2
+  %12 = phi i32 [ %5, %2 ], [ %20, %11 ]
+  %13 = phi <4 x float> [ zeroinitializer, %2 ], [ %19, %11 ]
+  %14 = phi <4 x i32> [ %10, %2 ], [ %17, %11 ]
+  %15 = tail call <16 x i1> @llvm.arm.mve.vctp8(i32 %12)
+  %mask = tail call <4 x i1> @v16i1_to_v4i1(<16 x i1> %15)
+  %16 = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %14, i32 32, <4 x i1> %mask)
+  %17 = extractvalue { <4 x float>, <4 x i32> } %16, 1
+  %18 = extractvalue { <4 x float>, <4 x i32> } %16, 0
+  %19 = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %13, <4 x float> %18, <4 x i1> %mask, <4 x float> %13)
+  %20 = add nsw i32 %12, -4
+  %21 = icmp sgt i32 %12, 4
+  br i1 %21, label %11, label %22
+
+22:                                               ; preds = %11
+  %23 = tail call i32 bitcast (i32 (...)* @vecAddAcrossF32Mve to i32 (<4 x float>)*)(<4 x float> %19)
+  %24 = sitofp i32 %23 to float
+  %25 = tail call float @llvm.fabs.f32(float %24)
+  ret float %25
+}
+
+define float @vctp16(float* %0, i32 %1) {
+; CHECK-LABEL: @vctp16(
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 8)
+; CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP3]], 0
+; CHECK-NEXT:    [[TMP5:%.*]] = add nsw i32 [[TMP1:%.*]], -1
+; CHECK-NEXT:    [[TMP6:%.*]] = ptrtoint float* [[TMP0:%.*]] to i32
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[TMP6]], i32 0
+; CHECK-NEXT:    [[TMP8:%.*]] = add <4 x i32> [[TMP7]], <i32 -32, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP10:%.*]] = add <4 x i32> [[TMP4]], [[TMP9]]
+; CHECK-NEXT:    br label [[TMP11:%.*]]
+; CHECK:       11:
+; CHECK-NEXT:    [[TMP12:%.*]] = phi i32 [ [[TMP5]], [[TMP2:%.*]] ], [ [[TMP21:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP13:%.*]] = phi <4 x float> [ zeroinitializer, [[TMP2]] ], [ [[TMP19:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP14:%.*]] = phi <4 x i32> [ [[TMP10]], [[TMP2]] ], [ [[TMP17:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP15:%.*]] = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 [[TMP12]])
+; CHECK-NEXT:    [[MASK:%.*]] = tail call <4 x i1> @v8i1_to_v4i1(<8 x i1> [[TMP15]])
+; CHECK-NEXT:    [[TMP16:%.*]] = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> [[TMP14]], i32 32, <4 x i1> [[MASK]])
+; CHECK-NEXT:    [[TMP17]] = extractvalue { <4 x float>, <4 x i32> } [[TMP16]], 1
+; CHECK-NEXT:    [[TMP18:%.*]] = extractvalue { <4 x float>, <4 x i32> } [[TMP16]], 0
+; CHECK-NEXT:    [[TMP19]] = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> [[TMP13]], <4 x float> [[TMP18]], <4 x i1> [[MASK]], <4 x float> [[TMP13]])
+; CHECK-NEXT:    [[TMP20:%.*]] = icmp sgt i32 [[TMP12]], 4
+; CHECK-NEXT:    [[TMP21]] = add i32 [[TMP12]], -4
+; CHECK-NEXT:    br i1 [[TMP20]], label [[TMP11]], label [[TMP22:%.*]]
+; CHECK:       22:
+; CHECK-NEXT:    [[TMP23:%.*]] = tail call i32 bitcast (i32 (...)* @vecAddAcrossF32Mve to i32 (<4 x float>)*)(<4 x float> [[TMP19]])
+; CHECK-NEXT:    [[TMP24:%.*]] = sitofp i32 [[TMP23]] to float
+; CHECK-NEXT:    [[TMP25:%.*]] = tail call float @llvm.fabs.f32(float [[TMP24]])
+; CHECK-NEXT:    ret float [[TMP25]]
+;
+  %3 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 8)
+  %4 = extractvalue { <4 x i32>, i32 } %3, 0
+  %5 = add nsw i32 %1, -1
+  %6 = ptrtoint float* %0 to i32
+  %7 = insertelement <4 x i32> poison, i32 %6, i32 0
+  %8 = add <4 x i32> %7, <i32 -32, i32 undef, i32 undef, i32 undef>
+  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
+  %10 = add <4 x i32> %4, %9
+  br label %11
+
+11:                                               ; preds = %11, %2
+  %12 = phi i32 [ %5, %2 ], [ %20, %11 ]
+  %13 = phi <4 x float> [ zeroinitializer, %2 ], [ %19, %11 ]
+  %14 = phi <4 x i32> [ %10, %2 ], [ %17, %11 ]
+  %15 = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %12)
+  %mask = tail call <4 x i1> @v8i1_to_v4i1(<8 x i1> %15)
+  %16 = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %14, i32 32, <4 x i1> %mask)
+  %17 = extractvalue { <4 x float>, <4 x i32> } %16, 1
+  %18 = extractvalue { <4 x float>, <4 x i32> } %16, 0
+  %19 = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %13, <4 x float> %18, <4 x i1> %mask, <4 x float> %13)
+  %20 = add nsw i32 %12, -4
+  %21 = icmp sgt i32 %12, 4
+  br i1 %21, label %11, label %22
+
+22:                                               ; preds = %11
+  %23 = tail call i32 bitcast (i32 (...)* @vecAddAcrossF32Mve to i32 (<4 x float>)*)(<4 x float> %19)
+  %24 = sitofp i32 %23 to float
+  %25 = tail call float @llvm.fabs.f32(float %24)
+  ret float %25
+}
+
+define float @vctpi32(float* %0, i32 %1) {
+; CHECK-LABEL: @vctpi32(
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 8)
+; CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP3]], 0
+; CHECK-NEXT:    [[TMP5:%.*]] = add nsw i32 [[TMP1:%.*]], -1
+; CHECK-NEXT:    [[TMP6:%.*]] = ptrtoint float* [[TMP0:%.*]] to i32
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[TMP6]], i32 0
+; CHECK-NEXT:    [[TMP8:%.*]] = add <4 x i32> [[TMP7]], <i32 -32, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP10:%.*]] = add <4 x i32> [[TMP4]], [[TMP9]]
+; CHECK-NEXT:    br label [[TMP11:%.*]]
+; CHECK:       11:
+; CHECK-NEXT:    [[TMP12:%.*]] = phi i32 [ [[TMP5]], [[TMP2:%.*]] ], [ [[TMP21:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP13:%.*]] = phi <4 x float> [ zeroinitializer, [[TMP2]] ], [ [[TMP19:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP14:%.*]] = phi <4 x i32> [ [[TMP10]], [[TMP2]] ], [ [[TMP17:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP15:%.*]] = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 [[TMP12]])
+; CHECK-NEXT:    [[TMP16:%.*]] = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> [[TMP14]], i32 32, <4 x i1> [[TMP15]])
+; CHECK-NEXT:    [[TMP17]] = extractvalue { <4 x float>, <4 x i32> } [[TMP16]], 1
+; CHECK-NEXT:    [[TMP18:%.*]] = extractvalue { <4 x float>, <4 x i32> } [[TMP16]], 0
+; CHECK-NEXT:    [[TMP19]] = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> [[TMP13]], <4 x float> [[TMP18]], <4 x i1> [[TMP15]], <4 x float> [[TMP13]])
+; CHECK-NEXT:    [[TMP20:%.*]] = icmp sgt i32 [[TMP12]], 4
+; CHECK-NEXT:    [[TMP21]] = add i32 [[TMP12]], -4
+; CHECK-NEXT:    br i1 [[TMP20]], label [[TMP11]], label [[TMP22:%.*]]
+; CHECK:       22:
+; CHECK-NEXT:    [[TMP23:%.*]] = tail call i32 bitcast (i32 (...)* @vecAddAcrossF32Mve to i32 (<4 x float>)*)(<4 x float> [[TMP19]])
+; CHECK-NEXT:    [[TMP24:%.*]] = sitofp i32 [[TMP23]] to float
+; CHECK-NEXT:    [[TMP25:%.*]] = tail call float @llvm.fabs.f32(float [[TMP24]])
+; CHECK-NEXT:    ret float [[TMP25]]
+;
+  %3 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 8)
+  %4 = extractvalue { <4 x i32>, i32 } %3, 0
+  %5 = add nsw i32 %1, -1
+  %6 = ptrtoint float* %0 to i32
+  %7 = insertelement <4 x i32> poison, i32 %6, i32 0
+  %8 = add <4 x i32> %7, <i32 -32, i32 undef, i32 undef, i32 undef>
+  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
+  %10 = add <4 x i32> %4, %9
+  br label %11
+
+11:                                               ; preds = %11, %2
+  %12 = phi i32 [ %5, %2 ], [ %20, %11 ]
+  %13 = phi <4 x float> [ zeroinitializer, %2 ], [ %19, %11 ]
+  %14 = phi <4 x i32> [ %10, %2 ], [ %17, %11 ]
+  %15 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %12)
+  %16 = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %14, i32 32, <4 x i1> %15)
+  %17 = extractvalue { <4 x float>, <4 x i32> } %16, 1
+  %18 = extractvalue { <4 x float>, <4 x i32> } %16, 0
+  %19 = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %13, <4 x float> %18, <4 x i1> %15, <4 x float> %13)
+  %20 = add nsw i32 %12, -4
+  %21 = icmp sgt i32 %12, 4
+  br i1 %21, label %11, label %22
+
+22:                                               ; preds = %11
+  %23 = tail call i32 bitcast (i32 (...)* @vecAddAcrossF32Mve to i32 (<4 x float>)*)(<4 x float> %19)
+  %24 = sitofp i32 %23 to float
+  %25 = tail call float @llvm.fabs.f32(float %24)
+  ret float %25
+}
+
+
+define float @vctpi64(float* %0, i32 %1) {
+; CHECK-LABEL: @vctpi64(
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 8)
+; CHECK-NEXT:    [[TMP4:%.*]] = extractvalue { <4 x i32>, i32 } [[TMP3]], 0
+; CHECK-NEXT:    [[TMP5:%.*]] = add nsw i32 [[TMP1:%.*]], -1
+; CHECK-NEXT:    [[TMP6:%.*]] = ptrtoint float* [[TMP0:%.*]] to i32
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[TMP6]], i32 0
+; CHECK-NEXT:    [[TMP8:%.*]] = add <4 x i32> [[TMP7]], <i32 -32, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP9:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP10:%.*]] = add <4 x i32> [[TMP4]], [[TMP9]]
+; CHECK-NEXT:    br label [[TMP11:%.*]]
+; CHECK:       11:
+; CHECK-NEXT:    [[TMP12:%.*]] = phi i32 [ [[TMP5]], [[TMP2:%.*]] ], [ [[TMP21:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP13:%.*]] = phi <4 x float> [ zeroinitializer, [[TMP2]] ], [ [[TMP19:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP14:%.*]] = phi <4 x i32> [ [[TMP10]], [[TMP2]] ], [ [[TMP17:%.*]], [[TMP11]] ]
+; CHECK-NEXT:    [[TMP15:%.*]] = tail call <4 x i1> @llvm.arm.mve.vctp64(i32 [[TMP12]])
+; CHECK-NEXT:    [[TMP16:%.*]] = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> [[TMP14]], i32 32, <4 x i1> [[TMP15]])
+; CHECK-NEXT:    [[TMP17]] = extractvalue { <4 x float>, <4 x i32> } [[TMP16]], 1
+; CHECK-NEXT:    [[TMP18:%.*]] = extractvalue { <4 x float>, <4 x i32> } [[TMP16]], 0
+; CHECK-NEXT:    [[TMP19]] = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> [[TMP13]], <4 x float> [[TMP18]], <4 x i1> [[TMP15]], <4 x float> [[TMP13]])
+; CHECK-NEXT:    [[TMP20:%.*]] = icmp sgt i32 [[TMP12]], 4
+; CHECK-NEXT:    [[TMP21]] = add i32 [[TMP12]], -4
+; CHECK-NEXT:    br i1 [[TMP20]], label [[TMP11]], label [[TMP22:%.*]]
+; CHECK:       22:
+; CHECK-NEXT:    [[TMP23:%.*]] = tail call i32 bitcast (i32 (...)* @vecAddAcrossF32Mve to i32 (<4 x float>)*)(<4 x float> [[TMP19]])
+; CHECK-NEXT:    [[TMP24:%.*]] = sitofp i32 [[TMP23]] to float
+; CHECK-NEXT:    [[TMP25:%.*]] = tail call float @llvm.fabs.f32(float [[TMP24]])
+; CHECK-NEXT:    ret float [[TMP25]]
+;
+  %3 = tail call { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32 0, i32 8)
+  %4 = extractvalue { <4 x i32>, i32 } %3, 0
+  %5 = add nsw i32 %1, -1
+  %6 = ptrtoint float* %0 to i32
+  %7 = insertelement <4 x i32> poison, i32 %6, i32 0
+  %8 = add <4 x i32> %7, <i32 -32, i32 undef, i32 undef, i32 undef>
+  %9 = shufflevector <4 x i32> %8, <4 x i32> undef, <4 x i32> zeroinitializer
+  %10 = add <4 x i32> %4, %9
+  br label %11
+
+11:                                               ; preds = %11, %2
+  %12 = phi i32 [ %5, %2 ], [ %20, %11 ]
+  %13 = phi <4 x float> [ zeroinitializer, %2 ], [ %19, %11 ]
+  %14 = phi <4 x i32> [ %10, %2 ], [ %17, %11 ]
+  %15 = tail call <4 x i1> @llvm.arm.mve.vctp64(i32 %12)
+  %16 = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32> %14, i32 32, <4 x i1> %15)
+  %17 = extractvalue { <4 x float>, <4 x i32> } %16, 1
+  %18 = extractvalue { <4 x float>, <4 x i32> } %16, 0
+  %19 = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %13, <4 x float> %18, <4 x i1> %15, <4 x float> %13)
+  %20 = add nsw i32 %12, -4
+  %21 = icmp sgt i32 %12, 4
+  br i1 %21, label %11, label %22
+
+22:                                               ; preds = %11
+  %23 = tail call i32 bitcast (i32 (...)* @vecAddAcrossF32Mve to i32 (<4 x float>)*)(<4 x float> %19)
+  %24 = sitofp i32 %23 to float
+  %25 = tail call float @llvm.fabs.f32(float %24)
+  ret float %25
+}
+
+declare { <4 x i32>, i32 } @llvm.arm.mve.vidup.v4i32(i32, i32)
+declare <16 x i1> @llvm.arm.mve.vctp8(i32)
+declare <8 x i1> @llvm.arm.mve.vctp16(i32)
+declare <4 x i1> @llvm.arm.mve.vctp32(i32)
+declare <4 x i1> @llvm.arm.mve.vctp64(i32)
+declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v4f32.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)
+declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>)
+declare i32 @vecAddAcrossF32Mve(...)
+declare <4 x i1> @v8i1_to_v4i1(<8 x i1>)
+declare <4 x i1> @v16i1_to_v4i1(<16 x i1>)
+declare float @llvm.fabs.f32(float)
diff --git a/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
new file mode 100644
index 0000000000000..9571f12098b6a
--- /dev/null
+++ b/llvm/test/Transforms/LoopUnroll/PowerPC/p8-unrolling-legalize-vectors-inseltpoison.ll
@@ -0,0 +1,256 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -S -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -loop-unroll | FileCheck %s
+; RUN: opt < %s -S -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 -loop-unroll | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-n32:64"
+target triple = "powerpc64le-unknown-linux-gnu"
+
+; Function Attrs: norecurse nounwind
+define i8* @f(i8* returned %s, i32 zeroext %x, i32 signext %k) local_unnamed_addr #0 {
+; CHECK-LABEL: @f(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[K:%.*]], 0
+; CHECK-NEXT:    br i1 [[CMP10]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_END:%.*]]
+; CHECK:       for.body.lr.ph:
+; CHECK-NEXT:    [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[K]] to i64
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[K]], 16
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    [[N_VEC:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 4294967280
+; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i32> [[BROADCAST_SPLATINSERT]], <16 x i32> undef, <16 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP0:%.*]] = add nsw i64 [[N_VEC]], -16
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i64 [[TMP0]], 4
+; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
+; CHECK-NEXT:    [[XTRAITER1:%.*]] = and i64 [[TMP2]], 1
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp ult i64 [[TMP1]], 1
+; CHECK-NEXT:    br i1 [[TMP3]], label [[MIDDLE_BLOCK_UNR_LCSSA:%.*]], label [[VECTOR_PH_NEW:%.*]]
+; CHECK:       vector.ph.new:
+; CHECK-NEXT:    [[UNROLL_ITER:%.*]] = sub i64 [[TMP2]], [[XTRAITER1]]
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH_NEW]] ], [ [[INDEX_NEXT_1:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_IND12:%.*]] = phi <16 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>, [[VECTOR_PH_NEW]] ], [ [[VEC_IND_NEXT13_1:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[NITER:%.*]] = phi i64 [ [[UNROLL_ITER]], [[VECTOR_PH_NEW]] ], [ [[NITER_NSUB_1:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP4:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND12]]
+; CHECK-NEXT:    [[TMP5:%.*]] = and <16 x i32> [[TMP4]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq <16 x i32> [[TMP5]], zeroinitializer
+; CHECK-NEXT:    [[TMP7:%.*]] = select <16 x i1> [[TMP6]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i8, i8* [[S:%.*]], i64 [[INDEX]]
+; CHECK-NEXT:    [[TMP9:%.*]] = bitcast i8* [[TMP8]] to <16 x i8>*
+; CHECK-NEXT:    store <16 x i8> [[TMP7]], <16 x i8>* [[TMP9]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT:%.*]] = add nuw nsw i64 [[INDEX]], 16
+; CHECK-NEXT:    [[VEC_IND_NEXT13:%.*]] = add <16 x i32> [[VEC_IND12]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[NITER_NSUB:%.*]] = sub i64 [[NITER]], 1
+; CHECK-NEXT:    [[TMP10:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND_NEXT13]]
+; CHECK-NEXT:    [[TMP11:%.*]] = and <16 x i32> [[TMP10]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq <16 x i32> [[TMP11]], zeroinitializer
+; CHECK-NEXT:    [[TMP13:%.*]] = select <16 x i1> [[TMP12]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
+; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDEX_NEXT]]
+; CHECK-NEXT:    [[TMP15:%.*]] = bitcast i8* [[TMP14]] to <16 x i8>*
+; CHECK-NEXT:    store <16 x i8> [[TMP13]], <16 x i8>* [[TMP15]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT_1]] = add i64 [[INDEX_NEXT]], 16
+; CHECK-NEXT:    [[VEC_IND_NEXT13_1]] = add <16 x i32> [[VEC_IND_NEXT13]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[NITER_NSUB_1]] = sub i64 [[NITER_NSUB]], 1
+; CHECK-NEXT:    [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NSUB_1]], 0
+; CHECK-NEXT:    br i1 [[NITER_NCMP_1]], label [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT:%.*]], label [[VECTOR_BODY]]
+; CHECK:       middle.block.unr-lcssa.loopexit:
+; CHECK-NEXT:    [[INDEX_UNR_PH:%.*]] = phi i64 [ [[INDEX_NEXT_1]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_IND12_UNR_PH:%.*]] = phi <16 x i32> [ [[VEC_IND_NEXT13_1]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    br label [[MIDDLE_BLOCK_UNR_LCSSA]]
+; CHECK:       middle.block.unr-lcssa:
+; CHECK-NEXT:    [[INDEX_UNR:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_UNR_PH]], [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT]] ]
+; CHECK-NEXT:    [[VEC_IND12_UNR:%.*]] = phi <16 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>, [[VECTOR_PH]] ], [ [[VEC_IND12_UNR_PH]], [[MIDDLE_BLOCK_UNR_LCSSA_LOOPEXIT]] ]
+; CHECK-NEXT:    [[LCMP_MOD2:%.*]] = icmp ne i64 [[XTRAITER1]], 0
+; CHECK-NEXT:    br i1 [[LCMP_MOD2]], label [[VECTOR_BODY_EPIL_PREHEADER:%.*]], label [[MIDDLE_BLOCK:%.*]]
+; CHECK:       vector.body.epil.preheader:
+; CHECK-NEXT:    br label [[VECTOR_BODY_EPIL:%.*]]
+; CHECK:       vector.body.epil:
+; CHECK-NEXT:    [[INDEX_EPIL:%.*]] = phi i64 [ [[INDEX_UNR]], [[VECTOR_BODY_EPIL_PREHEADER]] ]
+; CHECK-NEXT:    [[VEC_IND12_EPIL:%.*]] = phi <16 x i32> [ [[VEC_IND12_UNR]], [[VECTOR_BODY_EPIL_PREHEADER]] ]
+; CHECK-NEXT:    [[TMP16:%.*]] = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, [[VEC_IND12_EPIL]]
+; CHECK-NEXT:    [[TMP17:%.*]] = and <16 x i32> [[TMP16]], [[BROADCAST_SPLAT]]
+; CHECK-NEXT:    [[TMP18:%.*]] = icmp eq <16 x i32> [[TMP17]], zeroinitializer
+; CHECK-NEXT:    [[TMP19:%.*]] = select <16 x i1> [[TMP18]], <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
+; CHECK-NEXT:    [[TMP20:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDEX_EPIL]]
+; CHECK-NEXT:    [[TMP21:%.*]] = bitcast i8* [[TMP20]] to <16 x i8>*
+; CHECK-NEXT:    store <16 x i8> [[TMP19]], <16 x i8>* [[TMP21]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT_EPIL:%.*]] = add i64 [[INDEX_EPIL]], 16
+; CHECK-NEXT:    [[VEC_IND_NEXT13_EPIL:%.*]] = add <16 x i32> [[VEC_IND12_EPIL]], <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+; CHECK-NEXT:    [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT_EPIL]], [[N_VEC]]
+; CHECK-NEXT:    br label [[MIDDLE_BLOCK_EPILOG_LCSSA:%.*]]
+; CHECK:       middle.block.epilog-lcssa:
+; CHECK-NEXT:    br label [[MIDDLE_BLOCK]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[FOR_END]], label [[FOR_BODY_PREHEADER]]
+; CHECK:       for.body.preheader:
+; CHECK-NEXT:    [[INDVARS_IV_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_LR_PH]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT:    [[TMP23:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[INDVARS_IV_PH]]
+; CHECK-NEXT:    [[TMP24:%.*]] = add i64 [[WIDE_TRIP_COUNT]], -1
+; CHECK-NEXT:    [[TMP25:%.*]] = sub i64 [[TMP24]], [[INDVARS_IV_PH]]
+; CHECK-NEXT:    [[XTRAITER:%.*]] = and i64 [[TMP23]], 7
+; CHECK-NEXT:    [[LCMP_MOD:%.*]] = icmp ne i64 [[XTRAITER]], 0
+; CHECK-NEXT:    br i1 [[LCMP_MOD]], label [[FOR_BODY_PROL_PREHEADER:%.*]], label [[FOR_BODY_PROL_LOOPEXIT:%.*]]
+; CHECK:       for.body.prol.preheader:
+; CHECK-NEXT:    br label [[FOR_BODY_PROL:%.*]]
+; CHECK:       for.body.prol:
+; CHECK-NEXT:    [[INDVARS_IV_PROL:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL:%.*]], [[FOR_BODY_PROL]] ], [ [[INDVARS_IV_PH]], [[FOR_BODY_PROL_PREHEADER]] ]
+; CHECK-NEXT:    [[PROL_ITER:%.*]] = phi i64 [ [[XTRAITER]], [[FOR_BODY_PROL_PREHEADER]] ], [ [[PROL_ITER_SUB:%.*]], [[FOR_BODY_PROL]] ]
+; CHECK-NEXT:    [[TMP26:%.*]] = trunc i64 [[INDVARS_IV_PROL]] to i32
+; CHECK-NEXT:    [[SHL_PROL:%.*]] = shl i32 1, [[TMP26]]
+; CHECK-NEXT:    [[AND_PROL:%.*]] = and i32 [[SHL_PROL]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_PROL:%.*]] = icmp eq i32 [[AND_PROL]], 0
+; CHECK-NEXT:    [[CONV_PROL:%.*]] = select i1 [[TOBOOL_PROL]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_PROL:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_PROL]]
+; CHECK-NEXT:    store i8 [[CONV_PROL]], i8* [[ARRAYIDX_PROL]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_PROL]] = add nuw nsw i64 [[INDVARS_IV_PROL]], 1
+; CHECK-NEXT:    [[EXITCOND_PROL:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_PROL]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT:    [[PROL_ITER_SUB]] = sub i64 [[PROL_ITER]], 1
+; CHECK-NEXT:    [[PROL_ITER_CMP:%.*]] = icmp ne i64 [[PROL_ITER_SUB]], 0
+; CHECK-NEXT:    br i1 [[PROL_ITER_CMP]], label [[FOR_BODY_PROL]], label [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA:%.*]], [[LOOP0:!llvm.loop !.*]]
+; CHECK:       for.body.prol.loopexit.unr-lcssa:
+; CHECK-NEXT:    [[INDVARS_IV_UNR_PH:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_PROL]], [[FOR_BODY_PROL]] ]
+; CHECK-NEXT:    br label [[FOR_BODY_PROL_LOOPEXIT]]
+; CHECK:       for.body.prol.loopexit:
+; CHECK-NEXT:    [[INDVARS_IV_UNR:%.*]] = phi i64 [ [[INDVARS_IV_PH]], [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_UNR_PH]], [[FOR_BODY_PROL_LOOPEXIT_UNR_LCSSA]] ]
+; CHECK-NEXT:    [[TMP27:%.*]] = icmp ult i64 [[TMP25]], 7
+; CHECK-NEXT:    br i1 [[TMP27]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY_PREHEADER_NEW:%.*]]
+; CHECK:       for.body.preheader.new:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_UNR]], [[FOR_BODY_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_7:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[TMP28:%.*]] = trunc i64 [[INDVARS_IV]] to i32
+; CHECK-NEXT:    [[SHL:%.*]] = shl i32 1, [[TMP28]]
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[SHL]], [[X]]
+; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    [[CONV:%.*]] = select i1 [[TOBOOL]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV]]
+; CHECK-NEXT:    store i8 [[CONV]], i8* [[ARRAYIDX]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT:%.*]] = add nuw nsw i64 [[INDVARS_IV]], 1
+; CHECK-NEXT:    [[TMP29:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
+; CHECK-NEXT:    [[SHL_1:%.*]] = shl i32 1, [[TMP29]]
+; CHECK-NEXT:    [[AND_1:%.*]] = and i32 [[SHL_1]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_1:%.*]] = icmp eq i32 [[AND_1]], 0
+; CHECK-NEXT:    [[CONV_1:%.*]] = select i1 [[TOBOOL_1]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT]]
+; CHECK-NEXT:    store i8 [[CONV_1]], i8* [[ARRAYIDX_1]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_1:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT]], 1
+; CHECK-NEXT:    [[TMP30:%.*]] = trunc i64 [[INDVARS_IV_NEXT_1]] to i32
+; CHECK-NEXT:    [[SHL_2:%.*]] = shl i32 1, [[TMP30]]
+; CHECK-NEXT:    [[AND_2:%.*]] = and i32 [[SHL_2]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_2:%.*]] = icmp eq i32 [[AND_2]], 0
+; CHECK-NEXT:    [[CONV_2:%.*]] = select i1 [[TOBOOL_2]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_2:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_1]]
+; CHECK-NEXT:    store i8 [[CONV_2]], i8* [[ARRAYIDX_2]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_2:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_1]], 1
+; CHECK-NEXT:    [[TMP31:%.*]] = trunc i64 [[INDVARS_IV_NEXT_2]] to i32
+; CHECK-NEXT:    [[SHL_3:%.*]] = shl i32 1, [[TMP31]]
+; CHECK-NEXT:    [[AND_3:%.*]] = and i32 [[SHL_3]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_3:%.*]] = icmp eq i32 [[AND_3]], 0
+; CHECK-NEXT:    [[CONV_3:%.*]] = select i1 [[TOBOOL_3]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_3:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_2]]
+; CHECK-NEXT:    store i8 [[CONV_3]], i8* [[ARRAYIDX_3]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_3:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_2]], 1
+; CHECK-NEXT:    [[TMP32:%.*]] = trunc i64 [[INDVARS_IV_NEXT_3]] to i32
+; CHECK-NEXT:    [[SHL_4:%.*]] = shl i32 1, [[TMP32]]
+; CHECK-NEXT:    [[AND_4:%.*]] = and i32 [[SHL_4]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_4:%.*]] = icmp eq i32 [[AND_4]], 0
+; CHECK-NEXT:    [[CONV_4:%.*]] = select i1 [[TOBOOL_4]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_4:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_3]]
+; CHECK-NEXT:    store i8 [[CONV_4]], i8* [[ARRAYIDX_4]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_4:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_3]], 1
+; CHECK-NEXT:    [[TMP33:%.*]] = trunc i64 [[INDVARS_IV_NEXT_4]] to i32
+; CHECK-NEXT:    [[SHL_5:%.*]] = shl i32 1, [[TMP33]]
+; CHECK-NEXT:    [[AND_5:%.*]] = and i32 [[SHL_5]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_5:%.*]] = icmp eq i32 [[AND_5]], 0
+; CHECK-NEXT:    [[CONV_5:%.*]] = select i1 [[TOBOOL_5]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_5:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_4]]
+; CHECK-NEXT:    store i8 [[CONV_5]], i8* [[ARRAYIDX_5]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_5:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_4]], 1
+; CHECK-NEXT:    [[TMP34:%.*]] = trunc i64 [[INDVARS_IV_NEXT_5]] to i32
+; CHECK-NEXT:    [[SHL_6:%.*]] = shl i32 1, [[TMP34]]
+; CHECK-NEXT:    [[AND_6:%.*]] = and i32 [[SHL_6]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_6:%.*]] = icmp eq i32 [[AND_6]], 0
+; CHECK-NEXT:    [[CONV_6:%.*]] = select i1 [[TOBOOL_6]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_6:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_5]]
+; CHECK-NEXT:    store i8 [[CONV_6]], i8* [[ARRAYIDX_6]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_6:%.*]] = add nuw nsw i64 [[INDVARS_IV_NEXT_5]], 1
+; CHECK-NEXT:    [[TMP35:%.*]] = trunc i64 [[INDVARS_IV_NEXT_6]] to i32
+; CHECK-NEXT:    [[SHL_7:%.*]] = shl i32 1, [[TMP35]]
+; CHECK-NEXT:    [[AND_7:%.*]] = and i32 [[SHL_7]], [[X]]
+; CHECK-NEXT:    [[TOBOOL_7:%.*]] = icmp eq i32 [[AND_7]], 0
+; CHECK-NEXT:    [[CONV_7:%.*]] = select i1 [[TOBOOL_7]], i8 48, i8 49
+; CHECK-NEXT:    [[ARRAYIDX_7:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[INDVARS_IV_NEXT_6]]
+; CHECK-NEXT:    store i8 [[CONV_7]], i8* [[ARRAYIDX_7]], align 1
+; CHECK-NEXT:    [[INDVARS_IV_NEXT_7]] = add nuw nsw i64 [[INDVARS_IV_NEXT_6]], 1
+; CHECK-NEXT:    [[EXITCOND_7:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT_7]], [[WIDE_TRIP_COUNT]]
+; CHECK-NEXT:    br i1 [[EXITCOND_7]], label [[FOR_END_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY]]
+; CHECK:       for.end.loopexit.unr-lcssa:
+; CHECK-NEXT:    br label [[FOR_END_LOOPEXIT]]
+; CHECK:       for.end.loopexit:
+; CHECK-NEXT:    br label [[FOR_END]]
+; CHECK:       for.end:
+; CHECK-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[K]] to i64
+; CHECK-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, i8* [[S]], i64 [[IDXPROM1]]
+; CHECK-NEXT:    store i8 0, i8* [[ARRAYIDX2]], align 1
+; CHECK-NEXT:    ret i8* [[S]]
+;
+entry:
+  %cmp10 = icmp sgt i32 %k, 0
+  br i1 %cmp10, label %for.body.lr.ph, label %for.end
+
+for.body.lr.ph:                                   ; preds = %entry
+  %wide.trip.count = zext i32 %k to i64
+  %min.iters.check = icmp ult i32 %k, 16
+  br i1 %min.iters.check, label %for.body.preheader, label %vector.ph
+
+vector.ph:                                        ; preds = %for.body.lr.ph
+  %n.vec = and i64 %wide.trip.count, 4294967280
+  %broadcast.splatinsert = insertelement <16 x i32> poison, i32 %x, i32 0
+  %broadcast.splat = shufflevector <16 x i32> %broadcast.splatinsert, <16 x i32> undef, <16 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:                                      ; preds = %vector.body, %vector.ph
+  %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+  %vec.ind12 = phi <16 x i32> [ <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>, %vector.ph ], [ %vec.ind.next13, %vector.body ]
+  %0 = shl <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, %vec.ind12
+  %1 = and <16 x i32> %0, %broadcast.splat
+  %2 = icmp eq <16 x i32> %1, zeroinitializer
+  %3 = select <16 x i1> %2, <16 x i8> <i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48, i8 48>, <16 x i8> <i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49, i8 49>
+  %4 = getelementptr inbounds i8, i8* %s, i64 %index
+  %5 = bitcast i8* %4 to <16 x i8>*
+  store <16 x i8> %3, <16 x i8>* %5, align 1
+  %index.next = add i64 %index, 16
+  %vec.ind.next13 = add <16 x i32> %vec.ind12, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
+  %6 = icmp eq i64 %index.next, %n.vec
+  br i1 %6, label %middle.block, label %vector.body
+
+middle.block:                                     ; preds = %vector.body
+  %cmp.n = icmp eq i64 %n.vec, %wide.trip.count
+  br i1 %cmp.n, label %for.end, label %for.body.preheader
+
+for.body.preheader:                               ; preds = %middle.block, %for.body.lr.ph
+  %indvars.iv.ph = phi i64 [ 0, %for.body.lr.ph ], [ %n.vec, %middle.block ]
+  br label %for.body
+
+for.body:                                         ; preds = %for.body.preheader, %for.body
+  %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ %indvars.iv.ph, %for.body.preheader ]
+  %7 = trunc i64 %indvars.iv to i32
+  %shl = shl i32 1, %7
+  %and = and i32 %shl, %x
+  %tobool = icmp eq i32 %and, 0
+  %conv = select i1 %tobool, i8 48, i8 49
+  %arrayidx = getelementptr inbounds i8, i8* %s, i64 %indvars.iv
+  store i8 %conv, i8* %arrayidx, align 1
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
+  br i1 %exitcond, label %for.end, label %for.body
+
+for.end:                                          ; preds = %for.body, %middle.block, %entry
+  %idxprom1 = sext i32 %k to i64
+  %arrayidx2 = getelementptr inbounds i8, i8* %s, i64 %idxprom1
+  store i8 0, i8* %arrayidx2, align 1
+  ret i8* %s
+}
+
diff --git a/llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
index 4b312c8b94fe8..4e14c29ddc9f2 100644
--- a/llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
+++ b/llvm/test/Transforms/LoopVectorize/SystemZ/predicated-first-order-recurrence.ll
@@ -61,13 +61,13 @@ define void @func_21() {
 ; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 2
 ; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
 ; CHECK-NEXT:    [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 6
-; CHECK-NEXT:    br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0
+; CHECK-NEXT:    br i1 [[TMP20]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
 ; CHECK:       middle.block:
 ; CHECK-NEXT:    [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <2 x i32> [[TMP12]], i32 1
 ; CHECK-NEXT:    [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <2 x i32> [[TMP12]], i32 0
 ; CHECK-NEXT:    br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
 ; CHECK:       scalar.ph:
-; CHECK-NEXT:    [[SCALAR_RECUR_INIT:%.*]] = phi i32 [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[SCALAR_RECUR_INIT:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ]
 ; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ 6, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ]
 ; CHECK-NEXT:    br label [[LOOP:%.*]]
 ; CHECK:       loop:
@@ -79,7 +79,7 @@ define void @func_21() {
 ; CHECK-NEXT:    store i32 [[SCALAR_RECUR]], i32* [[B_PTR]], align 4
 ; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
 ; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 5
-; CHECK-NEXT:    br i1 [[EXITCOND]], label [[EXIT]], label [[LOOP]], !llvm.loop !2
+; CHECK-NEXT:    br i1 [[EXITCOND]], label [[EXIT]], label [[LOOP]], [[LOOP2:!llvm.loop !.*]]
 ; CHECK:       exit:
 ; CHECK-NEXT:    ret void
 ;
diff --git a/llvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll b/llvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll
index f106f05730b44..445db6aea08cc 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/invariant-load-gather.ll
@@ -44,7 +44,7 @@ define i32 @inv_load_conditional(i32* %a, i64 %n, i32* %b, i32 %k) {
 ; CHECK-NEXT:    br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP5:!llvm.loop !.*]]
 ; CHECK:       middle.block:
 ; CHECK-NEXT:    [[WIDE_MASKED_GATHER:%.*]] = call <16 x i32> @llvm.masked.gather.v16i32.v16p0i32(<16 x i32*> [[BROADCAST_SPLAT]], i32 4, <16 x i1> [[TMP3]], <16 x i32> undef), !alias.scope !3
-; CHECK-NEXT:    [[PREDPHI:%.*]] = select <16 x i1> [[TMP3]], <16 x i32> [[WIDE_MASKED_GATHER]], <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1>
+; CHECK-NEXT:    [[PREDPHI:%.*]] = select <16 x i1> [[TMP3]], <16 x i32> [[WIDE_MASKED_GATHER]], <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 1>
 ; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[SMAX]], [[N_VEC]]
 ; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <16 x i32> [[PREDPHI]], i32 15
 ; CHECK-NEXT:    br i1 [[CMP_N]], label [[FOR_END:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
@@ -73,7 +73,7 @@ define i32 @inv_load_conditional(i32* %a, i64 %n, i32* %b, i32 %k) {
 ; CHECK-NEXT:    br i1 [[TMP11]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], [[LOOP7:!llvm.loop !.*]]
 ; CHECK:       vec.epilog.middle.block:
 ; CHECK-NEXT:    [[WIDE_MASKED_GATHER20:%.*]] = call <8 x i32> @llvm.masked.gather.v8i32.v8p0i32(<8 x i32*> [[BROADCAST_SPLAT17]], i32 4, <8 x i1> [[TMP9]], <8 x i32> undef)
-; CHECK-NEXT:    [[PREDPHI21:%.*]] = select <8 x i1> [[TMP9]], <8 x i32> [[WIDE_MASKED_GATHER20]], <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1>
+; CHECK-NEXT:    [[PREDPHI21:%.*]] = select <8 x i1> [[TMP9]], <8 x i32> [[WIDE_MASKED_GATHER20]], <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 1>
 ; CHECK-NEXT:    [[CMP_N14:%.*]] = icmp eq i64 [[SMAX9]], [[N_VEC11]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <8 x i32> [[PREDPHI21]], i32 7
 ; CHECK-NEXT:    br i1 [[CMP_N14]], label [[FOR_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_SCALAR_PH]]
diff --git a/llvm/test/Transforms/LoopVectorize/control-flow.ll b/llvm/test/Transforms/LoopVectorize/control-flow.ll
index 8d56a17994a00..7aa065e49f584 100644
--- a/llvm/test/Transforms/LoopVectorize/control-flow.ll
+++ b/llvm/test/Transforms/LoopVectorize/control-flow.ll
@@ -10,7 +10,7 @@
 ;   return 0;
 ; }
 
-; CHECK: remark: source.cpp:5:9: loop not vectorized: loop control flow is not understood by vectorizer
+; CHECK: remark: source.cpp:5:9: loop not vectorized: could not determine number of loop iterations
 ; CHECK: remark: source.cpp:5:9: loop not vectorized
 
 ; CHECK: _Z4testPii
diff --git a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
new file mode 100644
index 0000000000000..0dba201e73fb5
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-const-TC.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -loop-vectorize -force-vector-interleave=3 -force-vector-width=2 -S | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+
+; Make sure the loop is vectorized and unrolled under -Os without folding its
+; tail based on its trip-count being provably divisible by chosen VFxIC.
+
+define dso_local void @constTC(i32* noalias nocapture %A) optsize {
+; CHECK-LABEL: @constTC(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> undef, i32 [[INDEX]], i32 0
+; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[INDUCTION:%.*]] = add <2 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1>
+; CHECK-NEXT:    [[INDUCTION1:%.*]] = add <2 x i32> [[BROADCAST_SPLAT]], <i32 2, i32 3>
+; CHECK-NEXT:    [[INDUCTION2:%.*]] = add <2 x i32> [[BROADCAST_SPLAT]], <i32 4, i32 5>
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[INDEX]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[INDEX]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[INDEX]], 4
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[TMP1]]
+; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[TMP2]]
+; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP7:%.*]] = bitcast i32* [[TMP6]] to <2 x i32>*
+; CHECK-NEXT:    store <2 x i32> <i32 13, i32 13>, <2 x i32>* [[TMP7]], align 1
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 2
+; CHECK-NEXT:    [[TMP9:%.*]] = bitcast i32* [[TMP8]] to <2 x i32>*
+; CHECK-NEXT:    store <2 x i32> <i32 13, i32 13>, <2 x i32>* [[TMP9]], align 1
+; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP3]], i32 4
+; CHECK-NEXT:    [[TMP11:%.*]] = bitcast i32* [[TMP10]] to <2 x i32>*
+; CHECK-NEXT:    store <2 x i32> <i32 13, i32 13>, <2 x i32>* [[TMP11]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 6
+; CHECK-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1800
+; CHECK-NEXT:    br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 1800, 1800
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
+; CHECK:       scalar.ph:
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ 1800, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[RIV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[RIVPLUS1:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[RIV]]
+; CHECK-NEXT:    store i32 13, i32* [[ARRAYIDX]], align 1
+; CHECK-NEXT:    [[RIVPLUS1]] = add nuw nsw i32 [[RIV]], 1
+; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[RIVPLUS1]], 1800
+; CHECK-NEXT:    br i1 [[COND]], label [[EXIT]], label [[LOOP]], [[LOOP2:!llvm.loop !.*]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %loop
+
+loop:
+  %riv = phi i32 [ 0, %entry ], [ %rivPlus1, %loop ]
+  %arrayidx = getelementptr inbounds i32, i32* %A, i32 %riv
+  store i32 13, i32* %arrayidx, align 1
+  %rivPlus1 = add nuw nsw i32 %riv, 1
+  %cond = icmp eq i32 %rivPlus1, 1800
+  br i1 %cond, label %exit, label %loop
+
+exit:
+  ret void
+}
diff --git a/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
new file mode 100644
index 0000000000000..82819a5db0772
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/dont-fold-tail-for-divisible-TC.ll
@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -loop-vectorize -force-vector-width=4 -S | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+
+; Make sure the loop is vectorized under -Os without folding its tail based on
+; its trip-count's lower bits known to be zero.
+
+define dso_local void @alignTC(i32* noalias nocapture %A, i32 %n) optsize {
+; CHECK-LABEL: @alignTC(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[ALIGNEDTC:%.*]] = and i32 [[N:%.*]], -8
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[ALIGNEDTC]], 4
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[ALIGNEDTC]], 4
+; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[ALIGNEDTC]], [[N_MOD_VF]]
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[INDEX]], i32 0
+; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[INDEX]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i32, i32* [[A:%.*]], i32 [[TMP0]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i32* [[TMP2]] to <4 x i32>*
+; CHECK-NEXT:    store <4 x i32> <i32 13, i32 13, i32 13, i32 13>, <4 x i32>* [[TMP3]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 4
+; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[ALIGNEDTC]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
+; CHECK:       scalar.ph:
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    br label [[LOOP:%.*]]
+; CHECK:       loop:
+; CHECK-NEXT:    [[RIV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[RIVPLUS1:%.*]], [[LOOP]] ]
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 [[RIV]]
+; CHECK-NEXT:    store i32 13, i32* [[ARRAYIDX]], align 1
+; CHECK-NEXT:    [[RIVPLUS1]] = add nuw nsw i32 [[RIV]], 1
+; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[RIVPLUS1]], [[ALIGNEDTC]]
+; CHECK-NEXT:    br i1 [[COND]], label [[EXIT]], label [[LOOP]], [[LOOP2:!llvm.loop !.*]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %alignedTC = and i32 %n, -8
+  br label %loop
+
+loop:
+  %riv = phi i32 [ 0, %entry ], [ %rivPlus1, %loop ]
+  %arrayidx = getelementptr inbounds i32, i32* %A, i32 %riv
+  store i32 13, i32* %arrayidx, align 1
+  %rivPlus1 = add nuw nsw i32 %riv, 1
+  %cond = icmp eq i32 %rivPlus1, %alignedTC
+  br i1 %cond, label %exit, label %loop
+
+exit:
+  ret void
+}
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
index 5a250984b1f0c..f0075d91f22bc 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence.ll
@@ -22,7 +22,7 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
 ; CHECK:       middle.block:
 ; CHECK:         %vector.recur.extract = extractelement <4 x i32> [[L1]], i32 3
 ; CHECK:       scalar.ph:
-; CHECK:         %scalar.recur.init = phi i32 [ %vector.recur.extract, %middle.block ], [ %pre_load, %vector.memcheck ], [ %pre_load, %for.preheader ]
+; CHECK:         %scalar.recur.init = phi i32 [ %pre_load, %vector.memcheck ], [ %pre_load, %for.preheader ], [ %vector.recur.extract, %middle.block ]
 ; CHECK:       scalar.body:
 ; CHECK:         %scalar.recur = phi i32 [ %scalar.recur.init, %scalar.ph ], [ {{.*}}, %scalar.body ]
 ;
@@ -79,7 +79,7 @@ for.exit:
 ; CHECK:       middle.block:
 ; CHECK:         %vector.recur.extract = extractelement <4 x i32> [[L1]], i32 3
 ; CHECK:       scalar.ph:
-; CHECK:         %scalar.recur.init = phi i32 [ %vector.recur.extract, %middle.block ], [ %.pre, %for.preheader ]
+; CHECK:         %scalar.recur.init = phi i32 [ %.pre, %for.preheader ], [ %vector.recur.extract, %middle.block ]
 ; CHECK:       scalar.body:
 ; CHECK:         %scalar.recur = phi i32 [ %scalar.recur.init, %scalar.ph ], [ {{.*}}, %scalar.body ]
 ;
@@ -147,7 +147,7 @@ scalar.body:
 ; CHECK:       middle.block:
 ; CHECK:         %vector.recur.extract = extractelement <4 x i16> [[L1]], i32 3
 ; CHECK:       scalar.ph:
-; CHECK:         %scalar.recur.init = phi i16 [ %vector.recur.extract, %middle.block ], [ %0, %vector.memcheck ], [ %0, %for.preheader ]
+; CHECK:         %scalar.recur.init = phi i16 [ %0, %vector.memcheck ], [ %0, %for.preheader ], [ %vector.recur.extract, %middle.block ]
 ; CHECK:       scalar.body:
 ; CHECK:         %scalar.recur = phi i16 [ %scalar.recur.init, %scalar.ph ], [ {{.*}}, %scalar.body ]
 ;
diff --git a/llvm/test/Transforms/LoopVectorize/induction.ll b/llvm/test/Transforms/LoopVectorize/induction.ll
index e093ee410a861..db1234d594fff 100644
--- a/llvm/test/Transforms/LoopVectorize/induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/induction.ll
@@ -427,7 +427,7 @@ for.end:
 ; UNROLL:   %[[i1:.+]] = or i64 %index, 1
 ; UNROLL:   %[[i2:.+]] = or i64 %index, 2
 ; UNROLL:   %[[i3:.+]] = or i64 %index, 3
-; UNROLL:   %[[add:.+]]= add <2 x i32> %[[splat:.+]], <i32 2, i32 undef>
+; UNROLL:   %[[add:.+]]= add <2 x i32> %[[splat:.+]], <i32 2, i32 poison>
 ; UNROLL:   getelementptr inbounds %pair.i16, %pair.i16* %p, i64 %index, i32 1
 ; UNROLL:   getelementptr inbounds %pair.i16, %pair.i16* %p, i64 %[[i1]], i32 1
 ; UNROLL:   getelementptr inbounds %pair.i16, %pair.i16* %p, i64 %[[i2]], i32 1
diff --git a/llvm/test/Transforms/LoopVectorize/loop-form.ll b/llvm/test/Transforms/LoopVectorize/loop-form.ll
index 298143ba726c3..6f4af4650f801 100644
--- a/llvm/test/Transforms/LoopVectorize/loop-form.ll
+++ b/llvm/test/Transforms/LoopVectorize/loop-form.ll
@@ -1,5 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -loop-vectorize -force-vector-width=2 < %s | FileCheck %s
+; RUN: opt -S -loop-vectorize -force-vector-width=2  -prefer-predicate-over-epilogue=predicate-dont-vectorize < %s | FileCheck --check-prefix TAILFOLD %s
+
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 
 define void @bottom_tested(i16* %p, i32 %n) {
@@ -42,6 +44,63 @@ define void @bottom_tested(i16* %p, i32 %n) {
 ; CHECK:       if.end:
 ; CHECK-NEXT:    ret void
 ;
+; TAILFOLD-LABEL: @bottom_tested(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    [[TMP0:%.*]] = icmp sgt i32 [[N:%.*]], 0
+; TAILFOLD-NEXT:    [[SMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 0
+; TAILFOLD-NEXT:    [[TMP1:%.*]] = add nuw i32 [[SMAX]], 1
+; TAILFOLD-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; TAILFOLD:       vector.ph:
+; TAILFOLD-NEXT:    [[N_RND_UP:%.*]] = add i32 [[TMP1]], 1
+; TAILFOLD-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[N_RND_UP]], 2
+; TAILFOLD-NEXT:    [[N_VEC:%.*]] = sub i32 [[N_RND_UP]], [[N_MOD_VF]]
+; TAILFOLD-NEXT:    [[TRIP_COUNT_MINUS_1:%.*]] = sub i32 [[TMP1]], 1
+; TAILFOLD-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> undef, i32 [[TRIP_COUNT_MINUS_1]], i32 0
+; TAILFOLD-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> undef, <2 x i32> zeroinitializer
+; TAILFOLD-NEXT:    br label [[VECTOR_BODY:%.*]]
+; TAILFOLD:       vector.body:
+; TAILFOLD-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ]
+; TAILFOLD-NEXT:    [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ]
+; TAILFOLD-NEXT:    [[TMP2:%.*]] = add i32 [[INDEX]], 0
+; TAILFOLD-NEXT:    [[TMP3:%.*]] = add i32 [[INDEX]], 1
+; TAILFOLD-NEXT:    [[TMP4:%.*]] = icmp ule <2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
+; TAILFOLD-NEXT:    [[TMP5:%.*]] = sext <2 x i32> [[VEC_IND]] to <2 x i64>
+; TAILFOLD-NEXT:    [[TMP6:%.*]] = extractelement <2 x i1> [[TMP4]], i32 0
+; TAILFOLD-NEXT:    br i1 [[TMP6]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
+; TAILFOLD:       pred.store.if:
+; TAILFOLD-NEXT:    [[TMP7:%.*]] = extractelement <2 x i64> [[TMP5]], i32 0
+; TAILFOLD-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[TMP7]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[TMP8]], align 4
+; TAILFOLD-NEXT:    br label [[PRED_STORE_CONTINUE]]
+; TAILFOLD:       pred.store.continue:
+; TAILFOLD-NEXT:    [[TMP9:%.*]] = extractelement <2 x i1> [[TMP4]], i32 1
+; TAILFOLD-NEXT:    br i1 [[TMP9]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]]
+; TAILFOLD:       pred.store.if1:
+; TAILFOLD-NEXT:    [[TMP10:%.*]] = extractelement <2 x i64> [[TMP5]], i32 1
+; TAILFOLD-NEXT:    [[TMP11:%.*]] = getelementptr inbounds i16, i16* [[P]], i64 [[TMP10]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[TMP11]], align 4
+; TAILFOLD-NEXT:    br label [[PRED_STORE_CONTINUE2]]
+; TAILFOLD:       pred.store.continue2:
+; TAILFOLD-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 2
+; TAILFOLD-NEXT:    [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], <i32 2, i32 2>
+; TAILFOLD-NEXT:    [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; TAILFOLD-NEXT:    br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP0:!llvm.loop !.*]]
+; TAILFOLD:       middle.block:
+; TAILFOLD-NEXT:    br i1 true, label [[IF_END:%.*]], label [[SCALAR_PH]]
+; TAILFOLD:       scalar.ph:
+; TAILFOLD-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
+; TAILFOLD-NEXT:    br label [[FOR_COND:%.*]]
+; TAILFOLD:       for.cond:
+; TAILFOLD-NEXT:    [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[FOR_COND]] ]
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; TAILFOLD-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N]]
+; TAILFOLD-NEXT:    br i1 [[CMP]], label [[FOR_COND]], label [[IF_END]], [[LOOP2:!llvm.loop !.*]]
+; TAILFOLD:       if.end:
+; TAILFOLD-NEXT:    ret void
+;
 entry:
   br label %for.cond
 
@@ -61,6 +120,90 @@ if.end:
 define void @early_exit(i16* %p, i32 %n) {
 ; CHECK-LABEL: @early_exit(
 ; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i32 [[N:%.*]], 0
+; CHECK-NEXT:    [[SMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = add nuw i32 [[SMAX]], 1
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP1]], 2
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[TMP1]], 2
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[N_MOD_VF]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP2]], i32 2, i32 [[N_MOD_VF]]
+; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[TMP1]], [[TMP3]]
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[INDEX]], 0
+; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[INDEX]], 1
+; CHECK-NEXT:    [[TMP6:%.*]] = sext i32 [[TMP4]] to i64
+; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[TMP6]]
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i16, i16* [[TMP7]], i32 0
+; CHECK-NEXT:    [[TMP9:%.*]] = bitcast i16* [[TMP8]] to <2 x i16>*
+; CHECK-NEXT:    store <2 x i16> zeroinitializer, <2 x i16>* [[TMP9]], align 4
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 2
+; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], <i32 2, i32 2>
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP4:!llvm.loop !.*]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[IF_END:%.*]], label [[SCALAR_PH]]
+; CHECK:       scalar.ph:
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    br label [[FOR_COND:%.*]]
+; CHECK:       for.cond:
+; CHECK-NEXT:    [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[IF_END]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; CHECK-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P]], i64 [[IPROM]]
+; CHECK-NEXT:    store i16 0, i16* [[B]], align 4
+; CHECK-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; CHECK-NEXT:    br label [[FOR_COND]], [[LOOP5:!llvm.loop !.*]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret void
+;
+; TAILFOLD-LABEL: @early_exit(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_COND:%.*]]
+; TAILFOLD:       for.cond:
+; TAILFOLD-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; TAILFOLD-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N:%.*]]
+; TAILFOLD-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[IF_END:%.*]]
+; TAILFOLD:       for.body:
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; TAILFOLD-NEXT:    br label [[FOR_COND]]
+; TAILFOLD:       if.end:
+; TAILFOLD-NEXT:    ret void
+;
+entry:
+  br label %for.cond
+
+for.cond:
+  %i = phi i32 [ 0, %entry ], [ %inc, %for.body ]
+  %cmp = icmp slt i32 %i, %n
+  br i1 %cmp, label %for.body, label %if.end
+
+for.body:
+  %iprom = sext i32 %i to i64
+  %b = getelementptr inbounds i16, i16* %p, i64 %iprom
+  store i16 0, i16* %b, align 4
+  %inc = add nsw i32 %i, 1
+  br label %for.cond
+
+if.end:
+  ret void
+}
+
+; Same as early_exit, but with optsize to prevent the use of
+; a scalar epilogue.  -- Can't vectorize this in either case.
+define void @optsize(i16* %p, i32 %n) optsize {
+; CHECK-LABEL: @optsize(
+; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]]
 ; CHECK:       for.cond:
 ; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
@@ -75,6 +218,22 @@ define void @early_exit(i16* %p, i32 %n) {
 ; CHECK:       if.end:
 ; CHECK-NEXT:    ret void
 ;
+; TAILFOLD-LABEL: @optsize(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_COND:%.*]]
+; TAILFOLD:       for.cond:
+; TAILFOLD-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; TAILFOLD-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N:%.*]]
+; TAILFOLD-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[IF_END:%.*]]
+; TAILFOLD:       for.body:
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; TAILFOLD-NEXT:    br label [[FOR_COND]]
+; TAILFOLD:       if.end:
+; TAILFOLD-NEXT:    ret void
+;
 entry:
   br label %for.cond
 
@@ -99,21 +258,70 @@ if.end:
 define void @multiple_unique_exit(i16* %p, i32 %n) {
 ; CHECK-LABEL: @multiple_unique_exit(
 ; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp sgt i32 [[N:%.*]], 0
+; CHECK-NEXT:    [[SMAX:%.*]] = select i1 [[TMP0]], i32 [[N]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[SMAX]], 2096
+; CHECK-NEXT:    [[UMIN:%.*]] = select i1 [[TMP1]], i32 [[SMAX]], i32 2096
+; CHECK-NEXT:    [[TMP2:%.*]] = add nuw nsw i32 [[UMIN]], 1
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ule i32 [[TMP2]], 2
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[TMP2]], 2
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i32 [[N_MOD_VF]], 0
+; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i32 2, i32 [[N_MOD_VF]]
+; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[TMP2]], [[TMP4]]
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[INDEX]], 0
+; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[INDEX]], 1
+; CHECK-NEXT:    [[TMP7:%.*]] = sext i32 [[TMP5]] to i64
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[TMP7]]
+; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i16, i16* [[TMP8]], i32 0
+; CHECK-NEXT:    [[TMP10:%.*]] = bitcast i16* [[TMP9]] to <2 x i16>*
+; CHECK-NEXT:    store <2 x i16> zeroinitializer, <2 x i16>* [[TMP10]], align 4
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i32 [[INDEX]], 2
+; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], <i32 2, i32 2>
+; CHECK-NEXT:    [[TMP11:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP6:!llvm.loop !.*]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[IF_END:%.*]], label [[SCALAR_PH]]
+; CHECK:       scalar.ph:
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]]
 ; CHECK:       for.cond:
-; CHECK-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
-; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N:%.*]]
-; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[IF_END:%.*]]
+; CHECK-NEXT:    [[I:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N]]
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[IF_END]]
 ; CHECK:       for.body:
 ; CHECK-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
-; CHECK-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; CHECK-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P]], i64 [[IPROM]]
 ; CHECK-NEXT:    store i16 0, i16* [[B]], align 4
 ; CHECK-NEXT:    [[INC]] = add nsw i32 [[I]], 1
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[I]], 2096
-; CHECK-NEXT:    br i1 [[CMP2]], label [[FOR_COND]], label [[IF_END]]
+; CHECK-NEXT:    br i1 [[CMP2]], label [[FOR_COND]], label [[IF_END]], [[LOOP7:!llvm.loop !.*]]
 ; CHECK:       if.end:
 ; CHECK-NEXT:    ret void
 ;
+; TAILFOLD-LABEL: @multiple_unique_exit(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_COND:%.*]]
+; TAILFOLD:       for.cond:
+; TAILFOLD-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; TAILFOLD-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N:%.*]]
+; TAILFOLD-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[IF_END:%.*]]
+; TAILFOLD:       for.body:
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; TAILFOLD-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[I]], 2096
+; TAILFOLD-NEXT:    br i1 [[CMP2]], label [[FOR_COND]], label [[IF_END]]
+; TAILFOLD:       if.end:
+; TAILFOLD-NEXT:    ret void
+;
 entry:
   br label %for.cond
 
@@ -154,6 +362,24 @@ define i32 @multiple_unique_exit2(i16* %p, i32 %n) {
 ; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[FOR_BODY]] ], [ [[I]], [[FOR_COND]] ]
 ; CHECK-NEXT:    ret i32 [[I_LCSSA]]
 ;
+; TAILFOLD-LABEL: @multiple_unique_exit2(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_COND:%.*]]
+; TAILFOLD:       for.cond:
+; TAILFOLD-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; TAILFOLD-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N:%.*]]
+; TAILFOLD-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[IF_END:%.*]]
+; TAILFOLD:       for.body:
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; TAILFOLD-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[I]], 2096
+; TAILFOLD-NEXT:    br i1 [[CMP2]], label [[FOR_COND]], label [[IF_END]]
+; TAILFOLD:       if.end:
+; TAILFOLD-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[FOR_BODY]] ], [ [[I]], [[FOR_COND]] ]
+; TAILFOLD-NEXT:    ret i32 [[I_LCSSA]]
+;
 entry:
   br label %for.cond
 
@@ -194,6 +420,24 @@ define i32 @multiple_unique_exit3(i16* %p, i32 %n) {
 ; CHECK-NEXT:    [[EXIT:%.*]] = phi i32 [ 0, [[FOR_COND]] ], [ 1, [[FOR_BODY]] ]
 ; CHECK-NEXT:    ret i32 [[EXIT]]
 ;
+; TAILFOLD-LABEL: @multiple_unique_exit3(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_COND:%.*]]
+; TAILFOLD:       for.cond:
+; TAILFOLD-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; TAILFOLD-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N:%.*]]
+; TAILFOLD-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[IF_END:%.*]]
+; TAILFOLD:       for.body:
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; TAILFOLD-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[I]], 2096
+; TAILFOLD-NEXT:    br i1 [[CMP2]], label [[FOR_COND]], label [[IF_END]]
+; TAILFOLD:       if.end:
+; TAILFOLD-NEXT:    [[EXIT:%.*]] = phi i32 [ 0, [[FOR_COND]] ], [ 1, [[FOR_BODY]] ]
+; TAILFOLD-NEXT:    ret i32 [[EXIT]]
+;
 entry:
   br label %for.cond
 
@@ -236,6 +480,25 @@ define i32 @multiple_exit_blocks(i16* %p, i32 %n) {
 ; CHECK:       if.end2:
 ; CHECK-NEXT:    ret i32 1
 ;
+; TAILFOLD-LABEL: @multiple_exit_blocks(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_COND:%.*]]
+; TAILFOLD:       for.cond:
+; TAILFOLD-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY:%.*]] ]
+; TAILFOLD-NEXT:    [[CMP:%.*]] = icmp slt i32 [[I]], [[N:%.*]]
+; TAILFOLD-NEXT:    br i1 [[CMP]], label [[FOR_BODY]], label [[IF_END:%.*]]
+; TAILFOLD:       for.body:
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; TAILFOLD-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[I]], 2096
+; TAILFOLD-NEXT:    br i1 [[CMP2]], label [[FOR_COND]], label [[IF_END2:%.*]]
+; TAILFOLD:       if.end:
+; TAILFOLD-NEXT:    ret i32 0
+; TAILFOLD:       if.end2:
+; TAILFOLD-NEXT:    ret i32 1
+;
 entry:
   br label %for.cond
 
@@ -279,6 +542,23 @@ define i32 @multiple_exit_switch(i16* %p, i32 %n) {
 ; CHECK-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[FOR_COND]] ], [ [[I]], [[FOR_COND]] ]
 ; CHECK-NEXT:    ret i32 [[I_LCSSA]]
 ;
+; TAILFOLD-LABEL: @multiple_exit_switch(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_COND:%.*]]
+; TAILFOLD:       for.cond:
+; TAILFOLD-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_COND]] ]
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; TAILFOLD-NEXT:    switch i32 [[I]], label [[FOR_COND]] [
+; TAILFOLD-NEXT:    i32 2096, label [[IF_END:%.*]]
+; TAILFOLD-NEXT:    i32 2097, label [[IF_END]]
+; TAILFOLD-NEXT:    ]
+; TAILFOLD:       if.end:
+; TAILFOLD-NEXT:    [[I_LCSSA:%.*]] = phi i32 [ [[I]], [[FOR_COND]] ], [ [[I]], [[FOR_COND]] ]
+; TAILFOLD-NEXT:    ret i32 [[I_LCSSA]]
+;
 entry:
   br label %for.cond
 
@@ -318,6 +598,24 @@ define i32 @multiple_exit_switch2(i16* %p, i32 %n) {
 ; CHECK:       if.end2:
 ; CHECK-NEXT:    ret i32 1
 ;
+; TAILFOLD-LABEL: @multiple_exit_switch2(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_COND:%.*]]
+; TAILFOLD:       for.cond:
+; TAILFOLD-NEXT:    [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_COND]] ]
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I]], 1
+; TAILFOLD-NEXT:    switch i32 [[I]], label [[FOR_COND]] [
+; TAILFOLD-NEXT:    i32 2096, label [[IF_END:%.*]]
+; TAILFOLD-NEXT:    i32 2097, label [[IF_END2:%.*]]
+; TAILFOLD-NEXT:    ]
+; TAILFOLD:       if.end:
+; TAILFOLD-NEXT:    ret i32 0
+; TAILFOLD:       if.end2:
+; TAILFOLD-NEXT:    ret i32 1
+;
 entry:
   br label %for.cond
 
@@ -338,3 +636,236 @@ if.end:
 if.end2:
   ret i32 1
 }
+
+define i32 @multiple_latch1(i16* %p) {
+; CHECK-LABEL: @multiple_latch1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[I_02:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY_BACKEDGE:%.*]] ]
+; CHECK-NEXT:    [[INC]] = add nsw i32 [[I_02]], 1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[INC]], 16
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY_BACKEDGE]], label [[FOR_SECOND:%.*]]
+; CHECK:       for.second:
+; CHECK-NEXT:    [[IPROM:%.*]] = sext i32 [[I_02]] to i64
+; CHECK-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; CHECK-NEXT:    store i16 0, i16* [[B]], align 4
+; CHECK-NEXT:    [[CMPS:%.*]] = icmp sgt i32 [[INC]], 16
+; CHECK-NEXT:    br i1 [[CMPS]], label [[FOR_BODY_BACKEDGE]], label [[FOR_END:%.*]]
+; CHECK:       for.body.backedge:
+; CHECK-NEXT:    br label [[FOR_BODY]]
+; CHECK:       for.end:
+; CHECK-NEXT:    ret i32 0
+;
+; TAILFOLD-LABEL: @multiple_latch1(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_BODY:%.*]]
+; TAILFOLD:       for.body:
+; TAILFOLD-NEXT:    [[I_02:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY_BACKEDGE:%.*]] ]
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I_02]], 1
+; TAILFOLD-NEXT:    [[CMP:%.*]] = icmp slt i32 [[INC]], 16
+; TAILFOLD-NEXT:    br i1 [[CMP]], label [[FOR_BODY_BACKEDGE]], label [[FOR_SECOND:%.*]]
+; TAILFOLD:       for.second:
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I_02]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[CMPS:%.*]] = icmp sgt i32 [[INC]], 16
+; TAILFOLD-NEXT:    br i1 [[CMPS]], label [[FOR_BODY_BACKEDGE]], label [[FOR_END:%.*]]
+; TAILFOLD:       for.body.backedge:
+; TAILFOLD-NEXT:    br label [[FOR_BODY]]
+; TAILFOLD:       for.end:
+; TAILFOLD-NEXT:    ret i32 0
+;
+entry:
+  br label %for.body
+
+for.body:
+  %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body.backedge]
+  %inc = add nsw i32 %i.02, 1
+  %cmp = icmp slt i32 %inc, 16
+  br i1 %cmp, label %for.body.backedge, label %for.second
+
+for.second:
+  %iprom = sext i32 %i.02 to i64
+  %b = getelementptr inbounds i16, i16* %p, i64 %iprom
+  store i16 0, i16* %b, align 4
+  %cmps = icmp sgt i32 %inc, 16
+  br i1 %cmps, label %for.body.backedge, label %for.end
+
+for.body.backedge:
+  br label %for.body
+
+for.end:
+  ret i32 0
+}
+
+
+; two back branches - loop simplify with convert this to the same form
+; as previous before vectorizer sees it, but show that.
+define i32 @multiple_latch2(i16* %p) {
+; CHECK-LABEL: @multiple_latch2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[I_02:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY_BACKEDGE:%.*]] ]
+; CHECK-NEXT:    [[INC]] = add nsw i32 [[I_02]], 1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[INC]], 16
+; CHECK-NEXT:    br i1 [[CMP]], label [[FOR_BODY_BACKEDGE]], label [[FOR_SECOND:%.*]]
+; CHECK:       for.body.backedge:
+; CHECK-NEXT:    br label [[FOR_BODY]]
+; CHECK:       for.second:
+; CHECK-NEXT:    [[IPROM:%.*]] = sext i32 [[I_02]] to i64
+; CHECK-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; CHECK-NEXT:    store i16 0, i16* [[B]], align 4
+; CHECK-NEXT:    [[CMPS:%.*]] = icmp sgt i32 [[INC]], 16
+; CHECK-NEXT:    br i1 [[CMPS]], label [[FOR_BODY_BACKEDGE]], label [[FOR_END:%.*]]
+; CHECK:       for.end:
+; CHECK-NEXT:    ret i32 0
+;
+; TAILFOLD-LABEL: @multiple_latch2(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[FOR_BODY:%.*]]
+; TAILFOLD:       for.body:
+; TAILFOLD-NEXT:    [[I_02:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC:%.*]], [[FOR_BODY_BACKEDGE:%.*]] ]
+; TAILFOLD-NEXT:    [[INC]] = add nsw i32 [[I_02]], 1
+; TAILFOLD-NEXT:    [[CMP:%.*]] = icmp slt i32 [[INC]], 16
+; TAILFOLD-NEXT:    br i1 [[CMP]], label [[FOR_BODY_BACKEDGE]], label [[FOR_SECOND:%.*]]
+; TAILFOLD:       for.body.backedge:
+; TAILFOLD-NEXT:    br label [[FOR_BODY]]
+; TAILFOLD:       for.second:
+; TAILFOLD-NEXT:    [[IPROM:%.*]] = sext i32 [[I_02]] to i64
+; TAILFOLD-NEXT:    [[B:%.*]] = getelementptr inbounds i16, i16* [[P:%.*]], i64 [[IPROM]]
+; TAILFOLD-NEXT:    store i16 0, i16* [[B]], align 4
+; TAILFOLD-NEXT:    [[CMPS:%.*]] = icmp sgt i32 [[INC]], 16
+; TAILFOLD-NEXT:    br i1 [[CMPS]], label [[FOR_BODY_BACKEDGE]], label [[FOR_END:%.*]]
+; TAILFOLD:       for.end:
+; TAILFOLD-NEXT:    ret i32 0
+;
+entry:
+  br label %for.body
+
+for.body:
+  %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ], [%inc, %for.second]
+  %inc = add nsw i32 %i.02, 1
+  %cmp = icmp slt i32 %inc, 16
+  br i1 %cmp, label %for.body, label %for.second
+
+for.second:
+  %iprom = sext i32 %i.02 to i64
+  %b = getelementptr inbounds i16, i16* %p, i64 %iprom
+  store i16 0, i16* %b, align 4
+  %cmps = icmp sgt i32 %inc, 16
+  br i1 %cmps, label %for.body, label %for.end
+
+for.end:
+  ret i32 0
+}
+
+
+; Check interaction between block predication and early exits.  We need the
+; condition on the early exit to remain dead (i.e. not be used when forming
+; the predicate mask).
+define void @scalar_predication(float* %addr) {
+; CHECK-LABEL: @scalar_predication(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ]
+; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr float, float* [[ADDR:%.*]], i64 [[TMP0]]
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr float, float* [[TMP1]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = bitcast float* [[TMP2]] to <2 x float>*
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x float>, <2 x float>* [[TMP3]], align 4
+; CHECK-NEXT:    [[TMP4:%.*]] = fcmp oeq <2 x float> [[WIDE_LOAD]], zeroinitializer
+; CHECK-NEXT:    [[TMP5:%.*]] = xor <2 x i1> [[TMP4]], <i1 true, i1 true>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i1> [[TMP5]], i32 0
+; CHECK-NEXT:    br i1 [[TMP6]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
+; CHECK:       pred.store.if:
+; CHECK-NEXT:    store float 1.000000e+01, float* [[TMP1]], align 4
+; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE]]
+; CHECK:       pred.store.continue:
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i1> [[TMP5]], i32 1
+; CHECK-NEXT:    br i1 [[TMP7]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]]
+; CHECK:       pred.store.if1:
+; CHECK-NEXT:    [[TMP8:%.*]] = add i64 [[INDEX]], 1
+; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr float, float* [[ADDR]], i64 [[TMP8]]
+; CHECK-NEXT:    store float 1.000000e+01, float* [[TMP9]], align 4
+; CHECK-NEXT:    br label [[PRED_STORE_CONTINUE2]]
+; CHECK:       pred.store.continue2:
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 2
+; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
+; CHECK-NEXT:    br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP8:!llvm.loop !.*]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 201, 200
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
+; CHECK:       scalar.ph:
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    br label [[LOOP_HEADER:%.*]]
+; CHECK:       loop.header:
+; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr float, float* [[ADDR]], i64 [[IV]]
+; CHECK-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], 200
+; CHECK-NEXT:    br i1 [[EXITCOND_NOT]], label [[EXIT]], label [[LOOP_BODY:%.*]]
+; CHECK:       loop.body:
+; CHECK-NEXT:    [[TMP11:%.*]] = load float, float* [[GEP]], align 4
+; CHECK-NEXT:    [[PRED:%.*]] = fcmp oeq float [[TMP11]], 0.000000e+00
+; CHECK-NEXT:    br i1 [[PRED]], label [[LOOP_LATCH]], label [[THEN:%.*]]
+; CHECK:       then:
+; CHECK-NEXT:    store float 1.000000e+01, float* [[GEP]], align 4
+; CHECK-NEXT:    br label [[LOOP_LATCH]]
+; CHECK:       loop.latch:
+; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT:    br label [[LOOP_HEADER]], [[LOOP9:!llvm.loop !.*]]
+; CHECK:       exit:
+; CHECK-NEXT:    ret void
+;
+; TAILFOLD-LABEL: @scalar_predication(
+; TAILFOLD-NEXT:  entry:
+; TAILFOLD-NEXT:    br label [[LOOP_HEADER:%.*]]
+; TAILFOLD:       loop.header:
+; TAILFOLD-NEXT:    [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ]
+; TAILFOLD-NEXT:    [[GEP:%.*]] = getelementptr float, float* [[ADDR:%.*]], i64 [[IV]]
+; TAILFOLD-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV]], 200
+; TAILFOLD-NEXT:    br i1 [[EXITCOND_NOT]], label [[EXIT:%.*]], label [[LOOP_BODY:%.*]]
+; TAILFOLD:       loop.body:
+; TAILFOLD-NEXT:    [[TMP0:%.*]] = load float, float* [[GEP]], align 4
+; TAILFOLD-NEXT:    [[PRED:%.*]] = fcmp oeq float [[TMP0]], 0.000000e+00
+; TAILFOLD-NEXT:    br i1 [[PRED]], label [[LOOP_LATCH]], label [[THEN:%.*]]
+; TAILFOLD:       then:
+; TAILFOLD-NEXT:    store float 1.000000e+01, float* [[GEP]], align 4
+; TAILFOLD-NEXT:    br label [[LOOP_LATCH]]
+; TAILFOLD:       loop.latch:
+; TAILFOLD-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; TAILFOLD-NEXT:    br label [[LOOP_HEADER]]
+; TAILFOLD:       exit:
+; TAILFOLD-NEXT:    ret void
+;
+entry:
+  br label %loop.header
+
+loop.header:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
+  %gep = getelementptr float, float* %addr, i64 %iv
+  %exitcond.not = icmp eq i64 %iv, 200
+  br i1 %exitcond.not, label %exit, label %loop.body
+
+loop.body:
+  %0 = load float, float* %gep, align 4
+  %pred = fcmp oeq float %0, 0.0
+  br i1 %pred, label %loop.latch, label %then
+
+then:
+  store float 10.0, float* %gep, align 4
+  br label %loop.latch
+
+loop.latch:
+  %iv.next = add nuw nsw i64 %iv, 1
+  br label %loop.header
+
+exit:
+  ret void
+}
diff --git a/llvm/test/Transforms/LoopVectorize/loop-legality-checks.ll b/llvm/test/Transforms/LoopVectorize/loop-legality-checks.ll
index 4e39181e53dd1..a4a8e99b77ca0 100644
--- a/llvm/test/Transforms/LoopVectorize/loop-legality-checks.ll
+++ b/llvm/test/Transforms/LoopVectorize/loop-legality-checks.ll
@@ -1,30 +1,9 @@
 ; RUN: opt < %s -loop-vectorize -debug-only=loop-vectorize -S -disable-output 2>&1 | FileCheck %s
 ; REQUIRES: asserts
 
-; Make sure LV legal bails out when the exiting block != loop latch.
-; CHECK-LABEL: "latch_is_not_exiting"
-; CHECK: LV: Not vectorizing: The exiting block is not the loop latch.
-define i32 @latch_is_not_exiting() {
-entry:
-  br label %for.body
-
-for.body:
-  %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ], [%inc, %for.second]
-  %inc = add nsw i32 %i.02, 1
-  %cmp = icmp slt i32 %inc, 16
-  br i1 %cmp, label %for.body, label %for.second
-
-for.second:
-  %cmps = icmp sgt i32 %inc, 16
-  br i1 %cmps, label %for.body, label %for.end
-
-for.end:
-  ret i32 0
-}
-
 ; Make sure LV legal bails out when there is no exiting block
 ; CHECK-LABEL: "no_exiting_block"
-; CHECK: LV: Not vectorizing: The loop must have an exiting block.
+; CHECK: LV: Not vectorizing: The loop must have a unique exit block.
 define i32 @no_exiting_block() {
 entry:
   br label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
index 15542255765f2..a070ba7f516ba 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop-pred.ll
@@ -1528,7 +1528,7 @@ define float @reduction_conditional(float* %A, float* %B, float* %C, float %S) {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
 ; CHECK:       vector.ph:
-; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[S:%.*]], i32 0
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[S:%.*]], i32 0
 ; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; CHECK:       vector.body:
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
index 67608ef3aba87..23bfc39bf6465 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-inloop.ll
@@ -800,7 +800,7 @@ define float @reduction_conditional(float* %A, float* %B, float* %C, float %S) {
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
 ; CHECK:       vector.ph:
-; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[S:%.*]], i32 0
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float [[S:%.*]], i32 0
 ; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
 ; CHECK:       vector.body:
 ; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll b/llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
new file mode 100644
index 0000000000000..3b0ba312fde85
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/skeleton-lcssa-crash.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -loop-vectorize -force-vector-width=2 -force-vector-interleave=1 -S %s | FileCheck %s
+
+; Make sure LV does not crash when creating runtime checks involving values from
+; other loops.
+define i16 @test(i16** %arg, i64 %N) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[OUTER:%.*]]
+; CHECK:       outer:
+; CHECK-NEXT:    [[L_1:%.*]] = load i16*, i16** [[ARG:%.*]], align 8
+; CHECK-NEXT:    [[L_2:%.*]] = load i16*, i16** [[ARG]], align 8
+; CHECK-NEXT:    [[C_1:%.*]] = call i1 @cond()
+; CHECK-NEXT:    br i1 [[C_1]], label [[OUTER_BACKEDGE:%.*]], label [[INNER_PREHEADER:%.*]]
+; CHECK:       outer.backedge:
+; CHECK-NEXT:    br label [[OUTER]]
+; CHECK:       inner.preheader:
+; CHECK-NEXT:    br label [[INNER:%.*]]
+; CHECK:       inner:
+; CHECK-NEXT:    [[C_2:%.*]] = call i1 @cond()
+; CHECK-NEXT:    br i1 [[C_2]], label [[OUTER_LATCH:%.*]], label [[INNER_BB:%.*]]
+; CHECK:       inner.bb:
+; CHECK-NEXT:    [[C_3:%.*]] = call i1 @cond()
+; CHECK-NEXT:    br i1 [[C_3]], label [[LOOP3_PREHEADER:%.*]], label [[INNER_LATCH:%.*]]
+; CHECK:       loop3.preheader:
+; CHECK-NEXT:    [[L_1_LCSSA11:%.*]] = phi i16* [ [[L_1]], [[INNER_BB]] ]
+; CHECK-NEXT:    [[L_1_LCSSA:%.*]] = phi i16* [ [[L_1]], [[INNER_BB]] ]
+; CHECK-NEXT:    [[L_2_LCSSA:%.*]] = phi i16* [ [[L_2]], [[INNER_BB]] ]
+; CHECK-NEXT:    [[L_2_LCSSA4:%.*]] = bitcast i16* [[L_2_LCSSA]] to i8*
+; CHECK-NEXT:    [[TMP0:%.*]] = add i64 [[N:%.*]], 1
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
+; CHECK:       vector.memcheck:
+; CHECK-NEXT:    [[UGLYGEP:%.*]] = getelementptr i8, i8* [[L_2_LCSSA4]], i64 1
+; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i16, i16* [[L_1_LCSSA]], i64 1
+; CHECK-NEXT:    [[SCEVGEP9:%.*]] = bitcast i16* [[SCEVGEP]] to i8*
+; CHECK-NEXT:    [[TMP1:%.*]] = add i64 [[N]], 2
+; CHECK-NEXT:    [[SCEVGEP10:%.*]] = getelementptr i16, i16* [[L_1_LCSSA11]], i64 [[TMP1]]
+; CHECK-NEXT:    [[SCEVGEP1013:%.*]] = bitcast i16* [[SCEVGEP10]] to i8*
+; CHECK-NEXT:    [[BOUND0:%.*]] = icmp ult i8* [[L_2_LCSSA4]], [[SCEVGEP1013]]
+; CHECK-NEXT:    [[BOUND1:%.*]] = icmp ult i8* [[SCEVGEP9]], [[UGLYGEP]]
+; CHECK-NEXT:    [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
+; CHECK-NEXT:    [[MEMCHECK_CONFLICT:%.*]] = and i1 [[FOUND_CONFLICT]], true
+; CHECK-NEXT:    br i1 [[MEMCHECK_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
+; CHECK:       vector.ph:
+; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2
+; CHECK-NEXT:    [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
+; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
+; CHECK:       vector.body:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i64 [[INDEX]], 0
+; CHECK-NEXT:    [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
+; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i16, i16* [[L_1]], i64 [[TMP3]]
+; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i16, i16* [[TMP4]], i32 0
+; CHECK-NEXT:    [[TMP6:%.*]] = bitcast i16* [[TMP5]] to <2 x i16>*
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <2 x i16>, <2 x i16>* [[TMP6]], align 2, !alias.scope !0
+; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i16, i16* [[L_2]], i64 0
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <2 x i16> [[WIDE_LOAD]], i32 0
+; CHECK-NEXT:    store i16 [[TMP8]], i16* [[TMP7]], align 2, !alias.scope !3, !noalias !0
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <2 x i16> [[WIDE_LOAD]], i32 1
+; CHECK-NEXT:    store i16 [[TMP9]], i16* [[TMP7]], align 2, !alias.scope !3, !noalias !0
+; CHECK-NEXT:    [[INDEX_NEXT]] = add i64 [[INDEX]], 2
+; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], [[LOOP5:!llvm.loop !.*]]
+; CHECK:       middle.block:
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label [[EXIT_LOOPEXIT:%.*]], label [[SCALAR_PH]]
+; CHECK:       scalar.ph:
+; CHECK-NEXT:    [[L_18:%.*]] = phi i16* [ [[L_1_LCSSA]], [[VECTOR_MEMCHECK]] ], [ [[L_1_LCSSA]], [[LOOP3_PREHEADER]] ], [ [[L_1_LCSSA]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT:    [[L_23:%.*]] = phi i16* [ [[L_2_LCSSA]], [[VECTOR_MEMCHECK]] ], [ [[L_2_LCSSA]], [[LOOP3_PREHEADER]] ], [ [[L_2_LCSSA]], [[MIDDLE_BLOCK]] ]
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[LOOP3_PREHEADER]] ], [ 0, [[VECTOR_MEMCHECK]] ]
+; CHECK-NEXT:    br label [[LOOP3:%.*]]
+; CHECK:       inner.latch:
+; CHECK-NEXT:    [[C_4:%.*]] = call i1 @cond()
+; CHECK-NEXT:    br i1 [[C_4]], label [[EXIT_LOOPEXIT1:%.*]], label [[INNER]]
+; CHECK:       outer.latch:
+; CHECK-NEXT:    br label [[OUTER_BACKEDGE]]
+; CHECK:       loop3:
+; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP3]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
+; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT:    [[C_5:%.*]] = icmp ult i64 [[IV]], [[N]]
+; CHECK-NEXT:    [[GEP_1:%.*]] = getelementptr inbounds i16, i16* [[L_18]], i64 [[IV_NEXT]]
+; CHECK-NEXT:    [[LOOP_L_1:%.*]] = load i16, i16* [[GEP_1]], align 2
+; CHECK-NEXT:    [[GEP_2:%.*]] = getelementptr inbounds i16, i16* [[L_23]], i64 0
+; CHECK-NEXT:    store i16 [[LOOP_L_1]], i16* [[GEP_2]], align 2
+; CHECK-NEXT:    br i1 [[C_5]], label [[LOOP3]], label [[EXIT_LOOPEXIT]], [[LOOP7:!llvm.loop !.*]]
+; CHECK:       exit.loopexit:
+; CHECK-NEXT:    [[L_17:%.*]] = phi i16* [ [[L_1_LCSSA]], [[MIDDLE_BLOCK]] ], [ [[L_18]], [[LOOP3]] ]
+; CHECK-NEXT:    br label [[EXIT:%.*]]
+; CHECK:       exit.loopexit1:
+; CHECK-NEXT:    [[L_1_LCSSA5:%.*]] = phi i16* [ [[L_1]], [[INNER_LATCH]] ]
+; CHECK-NEXT:    br label [[EXIT]]
+; CHECK:       exit:
+; CHECK-NEXT:    [[L_16:%.*]] = phi i16* [ [[L_1_LCSSA5]], [[EXIT_LOOPEXIT1]] ], [ [[L_17]], [[EXIT_LOOPEXIT]] ]
+; CHECK-NEXT:    [[L_3:%.*]] = load i16, i16* [[L_16]], align 2
+; CHECK-NEXT:    ret i16 [[L_3]]
+;
+entry:
+  br label %outer
+
+outer:
+  %l.1 = load i16*, i16** %arg, align 8
+  %l.2 = load i16*, i16** %arg, align 8
+  %c.1 = call i1 @cond()
+  br i1 %c.1, label %outer, label %inner
+
+inner:                                              ; preds = %bb15, %bb1
+  %c.2 = call i1 @cond()
+  br i1 %c.2, label %outer.latch, label %inner.bb
+
+inner.bb:                                              ; preds = %bb3
+  %c.3 = call i1 @cond()
+  br i1 %c.3, label %loop3, label %inner.latch
+
+inner.latch:                                             ; preds = %bb4
+  %c.4 = call i1 @cond()
+  br i1 %c.4, label %exit, label %inner
+
+outer.latch:                                             ; preds = %bb3
+  br label %outer
+
+loop3:                                              ; preds = %bb9, %bb4
+  %iv = phi i64 [ %iv.next, %loop3 ], [ 0, %inner.bb ]
+  %iv.next = add nsw nuw i64 %iv, 1
+  %c.5  = icmp ult i64 %iv, %N
+  %gep.1 = getelementptr inbounds i16, i16* %l.1, i64 %iv.next
+  %loop.l.1 = load i16, i16* %gep.1, align 2
+  %gep.2 = getelementptr inbounds i16, i16* %l.2, i64 0
+  store i16 %loop.l.1, i16* %gep.2 , align 2
+  br i1 %c.5, label %loop3, label %exit
+
+exit:                                             ; preds = %bb15, %bb5
+  %l.3 = load i16, i16* %l.1, align 2
+  ret i16 %l.3
+}
+
+declare i1 @cond()
diff --git a/llvm/test/Transforms/NewGVN/2016-08-30-MaskedScatterGather-xfail-inseltpoison.ll b/llvm/test/Transforms/NewGVN/2016-08-30-MaskedScatterGather-xfail-inseltpoison.ll
new file mode 100644
index 0000000000000..8160620324543
--- /dev/null
+++ b/llvm/test/Transforms/NewGVN/2016-08-30-MaskedScatterGather-xfail-inseltpoison.ll
@@ -0,0 +1,43 @@
+; XFAIL: *
+; RUN: opt < %s -basic-aa -newgvn -S | FileCheck %s
+
+declare void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> , <2 x i32*> , i32 , <2 x i1> )
+declare <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*>, i32, <2 x i1>, <2 x i32>)
+
+; This test ensures that masked scatter and gather operations, which take vectors of pointers,
+; do not have pointer aliasing ignored when being processed.
+; No scatter/gather calls should end up eliminated
+; CHECK: llvm.masked.gather
+; CHECK: llvm.masked.gather
+; CHECK: llvm.masked.scatter
+; CHECK: llvm.masked.gather
+; CHECK: llvm.masked.scatter
+; CHECK: llvm.masked.gather
+define spir_kernel void @test(<2 x i32*> %in1, <2 x i32*> %in2, i32* %out) {
+entry:
+  ; Just some temporary storage
+  %tmp.0 = alloca i32
+  %tmp.1 = alloca i32
+  %tmp.i = insertelement <2 x i32*> poison, i32* %tmp.0, i32 0
+  %tmp = insertelement <2 x i32*> %tmp.i, i32* %tmp.1, i32 1
+  ; Read from in1 and in2
+  %in1.v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %in1, i32 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1
+  %in2.v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %in2, i32 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1
+  ; Store in1 to the allocas
+  call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %in1.v, <2 x i32*> %tmp, i32 1, <2 x i1> <i1 true, i1 true>);
+  ; Read in1 from the allocas
+  ; This gather should alias the scatter we just saw
+  %tmp.v.0 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %tmp, i32 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1
+  ; Store in2 to the allocas
+  call void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32> %in2.v, <2 x i32*> %tmp, i32 1, <2 x i1> <i1 true, i1 true>);
+  ; Read in2 from the allocas
+  ; This gather should alias the scatter we just saw, and not be eliminated
+  %tmp.v.1 = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %tmp, i32 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1
+  ; Store in2 to out for good measure
+  %tmp.v.1.0 = extractelement <2 x i32> %tmp.v.1, i32 0
+  %tmp.v.1.1 = extractelement <2 x i32> %tmp.v.1, i32 1
+  store i32 %tmp.v.1.0, i32* %out
+  %out.1 = getelementptr i32, i32* %out, i32 1
+  store i32 %tmp.v.1.1, i32* %out.1
+  ret void
+}
diff --git a/llvm/test/Transforms/PGOProfile/counter_promo_nest-inseltpoison.ll b/llvm/test/Transforms/PGOProfile/counter_promo_nest-inseltpoison.ll
new file mode 100644
index 0000000000000..9252041499281
--- /dev/null
+++ b/llvm/test/Transforms/PGOProfile/counter_promo_nest-inseltpoison.ll
@@ -0,0 +1,165 @@
+; TEST that counter updates are promoted outside the whole loop nest
+; RUN: opt < %s -pgo-instr-gen -instrprof -do-counter-promotion=true -S | FileCheck --check-prefix=PROMO  %s
+; RUN: opt < %s --passes=pgo-instr-gen,instrprof -do-counter-promotion=true -S | FileCheck --check-prefix=PROMO  %s 
+
+@g = common local_unnamed_addr global i32 0, align 4
+@c = local_unnamed_addr global i32 10, align 4
+
+; Function Attrs: noinline norecurse nounwind uwtable
+define void @bar() local_unnamed_addr #0 {
+bb:
+  %tmp2 = load i32, i32* @g, align 4, !tbaa !2
+  %tmp3 = add nsw i32 %tmp2, 1
+  store i32 %tmp3, i32* @g, align 4, !tbaa !2
+  ret void
+}
+
+; Function Attrs: norecurse nounwind uwtable
+define i32 @main() local_unnamed_addr #1 {
+bb:
+  store i32 0, i32* @g, align 4, !tbaa !2
+  %tmp = load i32, i32* @c, align 4, !tbaa !2
+  %tmp1 = icmp sgt i32 %tmp, 0
+  br i1 %tmp1, label %bb2_1, label %bb84
+
+bb2_1:
+  br label %bb2
+
+bb2:                                              ; preds = %bb39, %bb
+  %tmp3 = phi i32 [ %tmp40, %bb39 ], [ %tmp, %bb2_1 ]
+  %tmp5 = phi i32 [ %tmp43, %bb39 ], [ 0, %bb2_1 ]
+  %tmp7 = icmp sgt i32 %tmp3, 0
+  br i1 %tmp7, label %bb14_1, label %bb39
+
+bb8:                                              ; preds = %bb39
+; PROMO-LABEL: bb8
+; PROMO: load {{.*}} @__profc_main{{.*}}
+; PROMO-NEXT: add
+; PROMO-NEXT: store {{.*}}@__profc_main{{.*}}
+; PROMO-NEXT: load {{.*}} @__profc_main{{.*}}
+; PROMO-NEXT: add
+; PROMO-NEXT: store {{.*}}@__profc_main{{.*}}
+; PROMO-NEXT: load {{.*}} @__profc_main{{.*}}
+; PROMO-NEXT: add
+; PROMO-NEXT: store {{.*}}@__profc_main{{.*}}
+; PROMO-NEXT: load {{.*}} @__profc_main{{.*}}
+; PROMO-NEXT: add
+; PROMO-NEXT: store {{.*}}@__profc_main{{.*}}
+; PROMO-NEXT: load {{.*}} @__profc_main{{.*}}
+; PROMO-NEXT: add
+; PROMO-NEXT: store {{.*}}@__profc_main{{.*}}
+
+  %tmp13 = icmp sgt i32 %tmp40, 0
+  br i1 %tmp13, label %bb45, label %bb84
+
+bb14_1:
+  br label %bb14
+
+bb14:                                             ; preds = %bb29, %bb2
+  %tmp15 = phi i32 [ %tmp30, %bb29 ], [ %tmp3, %bb14_1 ]
+  %tmp16 = phi i64 [ %tmp31, %bb29 ], [ 0, %bb14_1 ]
+  %tmp17 = phi i64 [ %tmp32, %bb29 ], [ 0, %bb14_1 ]
+  %tmp18 = phi i32 [ %tmp33, %bb29 ], [ 0, %bb14_1 ]
+  %tmp19 = icmp sgt i32 %tmp15, 0
+  br i1 %tmp19, label %bb20_split, label %bb29
+
+bb20_split:                                             
+ br label %bb20
+
+bb20:                                             ; preds = %bb20, %bb14
+  %tmp21 = phi i64 [ %tmp23, %bb20 ], [ 0, %bb20_split ]
+  %tmp22 = phi i32 [ %tmp24, %bb20 ], [ 0, %bb20_split ]
+  %tmp23 = add nuw i64 %tmp21, 1
+  tail call void @bar()
+  %tmp24 = add nuw nsw i32 %tmp22, 1
+  %tmp25 = load i32, i32* @c, align 4, !tbaa !2
+  %tmp26 = icmp slt i32 %tmp24, %tmp25
+  br i1 %tmp26, label %bb20, label %bb27
+
+bb27:                                             ; preds = %bb20
+  %tmp28 = add i64 %tmp23, %tmp16
+  br label %bb29
+
+bb29:                                             ; preds = %bb27, %bb14
+  %tmp30 = phi i32 [ %tmp25, %bb27 ], [ %tmp15, %bb14 ]
+  %tmp31 = phi i64 [ %tmp28, %bb27 ], [ %tmp16, %bb14 ]
+  %tmp32 = add nuw i64 %tmp17, 1
+  %tmp33 = add nuw nsw i32 %tmp18, 1
+  %tmp34 = icmp slt i32 %tmp33, %tmp30
+  br i1 %tmp34, label %bb14, label %bb35
+
+bb35:                                             ; preds = %bb29
+  %tmp36 = insertelement <2 x i64> poison, i64 %tmp31, i32 0
+  br label %bb39
+
+bb39:                                             ; preds = %bb35, %bb2
+  %tmp40 = phi i32 [ %tmp30, %bb35 ], [ %tmp3, %bb2 ]
+  %tmp43 = add nuw nsw i32 %tmp5, 1
+  %tmp44 = icmp slt i32 %tmp43, %tmp40
+  br i1 %tmp44, label %bb2, label %bb8
+
+bb45:                                             ; preds = %bb67, %bb8
+  %tmp46 = phi i32 [ %tmp68, %bb67 ], [ %tmp40, %bb8 ]
+  %tmp47 = phi i64 [ %tmp69, %bb67 ], [ 0, %bb8 ]
+  %tmp48 = phi i64 [ %tmp70, %bb67 ], [ 0, %bb8 ]
+  %tmp49 = phi i32 [ %tmp71, %bb67 ], [ 0, %bb8 ]
+  %tmp50 = icmp sgt i32 %tmp46, 0
+  br i1 %tmp50, label %bb57, label %bb67
+
+bb51:                                             ; preds = %bb67
+  %tmp56 = icmp sgt i32 %tmp68, 0
+  br i1 %tmp56, label %bb73, label %bb84
+
+bb57:                                             ; preds = %bb57, %bb45
+  %tmp58 = phi i64 [ %tmp60, %bb57 ], [ 0, %bb45 ]
+  %tmp59 = phi i32 [ %tmp61, %bb57 ], [ 0, %bb45 ]
+  %tmp60 = add nuw i64 %tmp58, 1
+  tail call void @bar()
+  %tmp61 = add nuw nsw i32 %tmp59, 1
+  %tmp62 = load i32, i32* @c, align 4, !tbaa !2
+  %tmp63 = mul nsw i32 %tmp62, 10
+  %tmp64 = icmp slt i32 %tmp61, %tmp63
+  br i1 %tmp64, label %bb57, label %bb65
+
+bb65:                                             ; preds = %bb57
+  %tmp66 = add i64 %tmp60, %tmp47
+  br label %bb67
+
+bb67:                                             ; preds = %bb65, %bb45
+  %tmp68 = phi i32 [ %tmp62, %bb65 ], [ %tmp46, %bb45 ]
+  %tmp69 = phi i64 [ %tmp66, %bb65 ], [ %tmp47, %bb45 ]
+  %tmp70 = add nuw i64 %tmp48, 1
+  %tmp71 = add nuw nsw i32 %tmp49, 1
+  %tmp72 = icmp slt i32 %tmp71, %tmp68
+  br i1 %tmp72, label %bb45, label %bb51
+
+bb73:                                             ; preds = %bb73, %bb51
+  %tmp74 = phi i64 [ %tmp76, %bb73 ], [ 0, %bb51 ]
+  %tmp75 = phi i32 [ %tmp77, %bb73 ], [ 0, %bb51 ]
+  %tmp76 = add nuw i64 %tmp74, 1
+  tail call void @bar()
+  %tmp77 = add nuw nsw i32 %tmp75, 1
+  %tmp78 = load i32, i32* @c, align 4, !tbaa !2
+  %tmp79 = mul nsw i32 %tmp78, 100
+  %tmp80 = icmp slt i32 %tmp77, %tmp79
+  br i1 %tmp80, label %bb73, label %bb81
+
+bb81:                                             ; preds = %bb73
+  br label %bb84
+
+bb84:                                             ; preds = %bb81, %bb51, %bb8, %bb
+  ret i32 0
+}
+
+attributes #0 = { noinline }
+attributes #1 = { norecurse nounwind uwtable } 
+
+!llvm.module.flags = !{!0}
+!llvm.ident = !{!1}
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!1 = !{!"clang version 5.0.0 (trunk 307355)"}
+!2 = !{!3, !3, i64 0}
+!3 = !{!"int", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C/C++ TBAA"}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll b/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
new file mode 100644
index 0000000000000..71444a9251c0c
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/addsub-inseltpoison.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -O3 -S                                        | FileCheck %s
+; RUN: opt < %s -passes='default<O3>' -aa-pipeline=default -S | FileCheck %s
+
+target triple = "x86_64--"
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+; Ideally, this should reach the backend with 1 fsub, 1 fadd, and 1 shuffle.
+; That may require some coordination between VectorCombine, SLP, and other passes.
+; The end goal is to get a single "vaddsubps" instruction for x86 with AVX.
+
+define <4 x float> @PR45015(<4 x float> %arg, <4 x float> %arg1) {
+; CHECK-LABEL: @PR45015(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <4 x float> [[ARG:%.*]], [[ARG1:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = fadd <4 x float> [[ARG]], [[ARG1]]
+; CHECK-NEXT:    [[T16:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP2]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT:    ret <4 x float> [[T16]]
+;
+  %t = extractelement <4 x float> %arg, i32 0
+  %t2 = extractelement <4 x float> %arg1, i32 0
+  %t3 = fsub float %t, %t2
+  %t4 = insertelement <4 x float> poison, float %t3, i32 0
+  %t5 = extractelement <4 x float> %arg, i32 1
+  %t6 = extractelement <4 x float> %arg1, i32 1
+  %t7 = fadd float %t5, %t6
+  %t8 = insertelement <4 x float> %t4, float %t7, i32 1
+  %t9 = extractelement <4 x float> %arg, i32 2
+  %t10 = extractelement <4 x float> %arg1, i32 2
+  %t11 = fsub float %t9, %t10
+  %t12 = insertelement <4 x float> %t8, float %t11, i32 2
+  %t13 = extractelement <4 x float> %arg, i32 3
+  %t14 = extractelement <4 x float> %arg1, i32 3
+  %t15 = fadd float %t13, %t14
+  %t16 = insertelement <4 x float> %t12, float %t15, i32 3
+  ret <4 x float> %t16
+}
+
+; PR42022 - https://bugs.llvm.org/show_bug.cgi?id=42022
+
+%struct.Vector4 = type { float, float, float, float }
+
+define { <2 x float>, <2 x float> } @add_aggregate(<2 x float> %a0, <2 x float> %a1, <2 x float> %b0, <2 x float> %b1) {
+; CHECK-LABEL: @add_aggregate(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x float> [[A0:%.*]], [[B0:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = fadd <2 x float> [[A1:%.*]], [[B1:%.*]]
+; CHECK-NEXT:    [[FCA_0_INSERT:%.*]] = insertvalue { <2 x float>, <2 x float> } undef, <2 x float> [[TMP1]], 0
+; CHECK-NEXT:    [[FCA_1_INSERT:%.*]] = insertvalue { <2 x float>, <2 x float> } [[FCA_0_INSERT]], <2 x float> [[TMP2]], 1
+; CHECK-NEXT:    ret { <2 x float>, <2 x float> } [[FCA_1_INSERT]]
+;
+  %a00 = extractelement <2 x float> %a0, i32 0
+  %b00 = extractelement <2 x float> %b0, i32 0
+  %add = fadd float %a00, %b00
+  %retval.0.0.insert = insertelement <2 x float> poison, float %add, i32 0
+  %a01 = extractelement <2 x float> %a0, i32 1
+  %b01 = extractelement <2 x float> %b0, i32 1
+  %add4 = fadd float %a01, %b01
+  %retval.0.1.insert = insertelement <2 x float> %retval.0.0.insert, float %add4, i32 1
+  %a10 = extractelement <2 x float> %a1, i32 0
+  %b10 = extractelement <2 x float> %b1, i32 0
+  %add7 = fadd float %a10, %b10
+  %retval.1.0.insert = insertelement <2 x float> poison, float %add7, i32 0
+  %a11 = extractelement <2 x float> %a1, i32 1
+  %b11 = extractelement <2 x float> %b1, i32 1
+  %add10 = fadd float %a11, %b11
+  %retval.1.1.insert = insertelement <2 x float> %retval.1.0.insert, float %add10, i32 1
+  %fca.0.insert = insertvalue { <2 x float>, <2 x float> } undef, <2 x float> %retval.0.1.insert, 0
+  %fca.1.insert = insertvalue { <2 x float>, <2 x float> } %fca.0.insert, <2 x float> %retval.1.1.insert, 1
+  ret { <2 x float>, <2 x float> } %fca.1.insert
+}
+
+define void @add_aggregate_store(<2 x float> %a0, <2 x float> %a1, <2 x float> %b0, <2 x float> %b1, %struct.Vector4* nocapture dereferenceable(16) %r) {
+; CHECK-LABEL: @add_aggregate_store(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x float> [[A0:%.*]], [[B0:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = fadd <2 x float> [[A1:%.*]], [[B1:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast %struct.Vector4* [[R:%.*]] to <4 x float>*
+; CHECK-NEXT:    store <4 x float> [[TMP3]], <4 x float>* [[TMP4]], align 4
+; CHECK-NEXT:    ret void
+;
+  %a00 = extractelement <2 x float> %a0, i32 0
+  %b00 = extractelement <2 x float> %b0, i32 0
+  %add = fadd float %a00, %b00
+  %r0 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 0
+  store float %add, float* %r0, align 4
+  %a01 = extractelement <2 x float> %a0, i32 1
+  %b01 = extractelement <2 x float> %b0, i32 1
+  %add4 = fadd float %a01, %b01
+  %r1 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 1
+  store float %add4, float* %r1, align 4
+  %a10 = extractelement <2 x float> %a1, i32 0
+  %b10 = extractelement <2 x float> %b1, i32 0
+  %add7 = fadd float %a10, %b10
+  %r2 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 2
+  store float %add7, float* %r2, align 4
+  %a11 = extractelement <2 x float> %a1, i32 1
+  %b11 = extractelement <2 x float> %b1, i32 1
+  %add10 = fadd float %a11, %b11
+  %r3 = getelementptr inbounds %struct.Vector4, %struct.Vector4* %r, i64 0, i32 3
+  store float %add10, float* %r3, align 4
+  ret void
+}
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/horiz-math-inseltpoison.ll b/llvm/test/Transforms/PhaseOrdering/X86/horiz-math-inseltpoison.ll
new file mode 100644
index 0000000000000..9d8bafa591c74
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/horiz-math-inseltpoison.ll
@@ -0,0 +1,153 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -O3                   -S < %s  | FileCheck %s
+; RUN: opt -passes='default<O3>' -S < %s  | FileCheck %s
+
+target triple = "x86_64--"
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+; PR41813 - https://bugs.llvm.org/show_bug.cgi?id=41813
+
+define <4 x float> @hadd_reverse_v4f32(<4 x float> %a, <4 x float> %b) #0 {
+; CHECK-LABEL: @hadd_reverse_v4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i32> <i32 3, i32 1, i32 7, i32 5>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x float> [[A]], <4 x float> [[B]], <4 x i32> <i32 2, i32 0, i32 6, i32 4>
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x float> [[TMP3]]
+;
+  %shuffle = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %shuffle1 = shufflevector <4 x float> %b, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  %vecext = extractelement <4 x float> %shuffle, i32 0
+  %vecext2 = extractelement <4 x float> %shuffle, i32 1
+  %add = fadd float %vecext, %vecext2
+  %vecinit = insertelement <4 x float> poison, float %add, i32 0
+  %vecext3 = extractelement <4 x float> %shuffle, i32 2
+  %vecext4 = extractelement <4 x float> %shuffle, i32 3
+  %add5 = fadd float %vecext3, %vecext4
+  %vecinit6 = insertelement <4 x float> %vecinit, float %add5, i32 1
+  %vecext7 = extractelement <4 x float> %shuffle1, i32 0
+  %vecext8 = extractelement <4 x float> %shuffle1, i32 1
+  %add9 = fadd float %vecext7, %vecext8
+  %vecinit10 = insertelement <4 x float> %vecinit6, float %add9, i32 2
+  %vecext11 = extractelement <4 x float> %shuffle1, i32 2
+  %vecext12 = extractelement <4 x float> %shuffle1, i32 3
+  %add13 = fadd float %vecext11, %vecext12
+  %vecinit14 = insertelement <4 x float> %vecinit10, float %add13, i32 3
+  ret <4 x float> %vecinit14
+}
+
+define <4 x float> @reverse_hadd_v4f32(<4 x float> %a, <4 x float> %b) #0 {
+; CHECK-LABEL: @reverse_hadd_v4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[B:%.*]], <4 x float> [[A:%.*]], <4 x i32> <i32 2, i32 0, i32 6, i32 4>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x float> [[B]], <4 x float> [[A]], <4 x i32> <i32 3, i32 1, i32 7, i32 5>
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x float> [[TMP3]]
+;
+  %vecext = extractelement <4 x float> %a, i32 0
+  %vecext1 = extractelement <4 x float> %a, i32 1
+  %add = fadd float %vecext, %vecext1
+  %vecinit = insertelement <4 x float> poison, float %add, i32 0
+  %vecext2 = extractelement <4 x float> %a, i32 2
+  %vecext3 = extractelement <4 x float> %a, i32 3
+  %add4 = fadd float %vecext2, %vecext3
+  %vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1
+  %vecext6 = extractelement <4 x float> %b, i32 0
+  %vecext7 = extractelement <4 x float> %b, i32 1
+  %add8 = fadd float %vecext6, %vecext7
+  %vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 2
+  %vecext10 = extractelement <4 x float> %b, i32 2
+  %vecext11 = extractelement <4 x float> %b, i32 3
+  %add12 = fadd float %vecext10, %vecext11
+  %vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 3
+  %shuffle = shufflevector <4 x float> %vecinit13, <4 x float> %a, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x float> %shuffle
+}
+
+define <8 x float> @hadd_reverse_v8f32(<8 x float> %a, <8 x float> %b) #0 {
+; CHECK-LABEL: @hadd_reverse_v8f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 7, i32 5, i32 15, i32 13, i32 3, i32 1, i32 11, i32 9>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 6, i32 4, i32 14, i32 12, i32 2, i32 0, i32 10, i32 8>
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <8 x float> [[TMP3]]
+;
+  %shuffle = shufflevector <8 x float> %a, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+  %shuffle1 = shufflevector <8 x float> %b, <8 x float> %b, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+  %vecext = extractelement <8 x float> %shuffle, i32 0
+  %vecext2 = extractelement <8 x float> %shuffle, i32 1
+  %add = fadd float %vecext, %vecext2
+  %vecinit = insertelement <8 x float> poison, float %add, i32 0
+  %vecext3 = extractelement <8 x float> %shuffle, i32 2
+  %vecext4 = extractelement <8 x float> %shuffle, i32 3
+  %add5 = fadd float %vecext3, %vecext4
+  %vecinit6 = insertelement <8 x float> %vecinit, float %add5, i32 1
+  %vecext7 = extractelement <8 x float> %shuffle1, i32 0
+  %vecext8 = extractelement <8 x float> %shuffle1, i32 1
+  %add9 = fadd float %vecext7, %vecext8
+  %vecinit10 = insertelement <8 x float> %vecinit6, float %add9, i32 2
+  %vecext11 = extractelement <8 x float> %shuffle1, i32 2
+  %vecext12 = extractelement <8 x float> %shuffle1, i32 3
+  %add13 = fadd float %vecext11, %vecext12
+  %vecinit14 = insertelement <8 x float> %vecinit10, float %add13, i32 3
+  %vecext15 = extractelement <8 x float> %shuffle, i32 4
+  %vecext16 = extractelement <8 x float> %shuffle, i32 5
+  %add17 = fadd float %vecext15, %vecext16
+  %vecinit18 = insertelement <8 x float> %vecinit14, float %add17, i32 4
+  %vecext19 = extractelement <8 x float> %shuffle, i32 6
+  %vecext20 = extractelement <8 x float> %shuffle, i32 7
+  %add21 = fadd float %vecext19, %vecext20
+  %vecinit22 = insertelement <8 x float> %vecinit18, float %add21, i32 5
+  %vecext23 = extractelement <8 x float> %shuffle1, i32 4
+  %vecext24 = extractelement <8 x float> %shuffle1, i32 5
+  %add25 = fadd float %vecext23, %vecext24
+  %vecinit26 = insertelement <8 x float> %vecinit22, float %add25, i32 6
+  %vecext27 = extractelement <8 x float> %shuffle1, i32 6
+  %vecext28 = extractelement <8 x float> %shuffle1, i32 7
+  %add29 = fadd float %vecext27, %vecext28
+  %vecinit30 = insertelement <8 x float> %vecinit26, float %add29, i32 7
+  ret <8 x float> %vecinit30
+}
+
+define <8 x float> @reverse_hadd_v8f32(<8 x float> %a, <8 x float> %b) #0 {
+; CHECK-LABEL: @reverse_hadd_v8f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    ret <8 x float> [[SHUFFLE]]
+;
+  %vecext = extractelement <8 x float> %a, i32 0
+  %vecext1 = extractelement <8 x float> %a, i32 1
+  %add = fadd float %vecext, %vecext1
+  %vecinit = insertelement <8 x float> poison, float %add, i32 0
+  %vecext2 = extractelement <8 x float> %a, i32 2
+  %vecext3 = extractelement <8 x float> %a, i32 3
+  %add4 = fadd float %vecext2, %vecext3
+  %vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 1
+  %vecext6 = extractelement <8 x float> %b, i32 0
+  %vecext7 = extractelement <8 x float> %b, i32 1
+  %add8 = fadd float %vecext6, %vecext7
+  %vecinit9 = insertelement <8 x float> %vecinit5, float %add8, i32 2
+  %vecext10 = extractelement <8 x float> %b, i32 2
+  %vecext11 = extractelement <8 x float> %b, i32 3
+  %add12 = fadd float %vecext10, %vecext11
+  %vecinit13 = insertelement <8 x float> %vecinit9, float %add12, i32 3
+  %vecext14 = extractelement <8 x float> %a, i32 4
+  %vecext15 = extractelement <8 x float> %a, i32 5
+  %add16 = fadd float %vecext14, %vecext15
+  %vecinit17 = insertelement <8 x float> %vecinit13, float %add16, i32 4
+  %vecext18 = extractelement <8 x float> %a, i32 6
+  %vecext19 = extractelement <8 x float> %a, i32 7
+  %add20 = fadd float %vecext18, %vecext19
+  %vecinit21 = insertelement <8 x float> %vecinit17, float %add20, i32 5
+  %vecext22 = extractelement <8 x float> %b, i32 4
+  %vecext23 = extractelement <8 x float> %b, i32 5
+  %add24 = fadd float %vecext22, %vecext23
+  %vecinit25 = insertelement <8 x float> %vecinit21, float %add24, i32 6
+  %vecext26 = extractelement <8 x float> %b, i32 6
+  %vecext27 = extractelement <8 x float> %b, i32 7
+  %add28 = fadd float %vecext26, %vecext27
+  %vecinit29 = insertelement <8 x float> %vecinit25, float %add28, i32 7
+  %shuffle = shufflevector <8 x float> %vecinit29, <8 x float> %a, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+  ret <8 x float> %shuffle
+}
+
+attributes #0 = { "min-legal-vector-width"="128" "target-cpu"="btver2" "target-features"="+avx,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+sse4a,+ssse3" }
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/horiz-math.ll b/llvm/test/Transforms/PhaseOrdering/X86/horiz-math.ll
index 37f6968c876bf..4bea3e1de88ac 100644
--- a/llvm/test/Transforms/PhaseOrdering/X86/horiz-math.ll
+++ b/llvm/test/Transforms/PhaseOrdering/X86/horiz-math.ll
@@ -111,7 +111,7 @@ define <8 x float> @reverse_hadd_v8f32(<8 x float> %a, <8 x float> %b) #0 {
 ; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
 ; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
 ; CHECK-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
-; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <8 x float> [[TMP3]], <8 x float> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
 ; CHECK-NEXT:    ret <8 x float> [[SHUFFLE]]
 ;
   %vecext = extractelement <8 x float> %a, i32 0
diff --git a/llvm/test/Transforms/PhaseOrdering/X86/scalarization-inseltpoison.ll b/llvm/test/Transforms/PhaseOrdering/X86/scalarization-inseltpoison.ll
new file mode 100644
index 0000000000000..c01c9562274a0
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/X86/scalarization-inseltpoison.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -O3                   -S < %s  | FileCheck %s
+; RUN: opt -passes='default<O3>' -S < %s  | FileCheck %s
+
+target triple = "x86_64--"
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+; PR42174 - https://bugs.llvm.org/show_bug.cgi?id=42174
+; This test should match the IR produced by clang after running -mem2reg.
+; All math before the final 'add' should be scalarized.
+
+define <4 x i32> @square(<4 x i32> %num, i32 %y, i32 %x, i32 %h, i32 %k, i32 %w, i32 %p, i32 %j, i32 %u) {
+; CHECK-LABEL: @square(
+; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[K:%.*]], 2
+; CHECK-NEXT:    [[MUL:%.*]] = mul nsw i32 [[P:%.*]], 6234
+; CHECK-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[H:%.*]], 75
+; CHECK-NEXT:    [[DIV9:%.*]] = sdiv i32 [[J:%.*]], 3452
+; CHECK-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[W:%.*]], 53
+; CHECK-NEXT:    [[DIV17:%.*]] = sdiv i32 [[X:%.*]], 820
+; CHECK-NEXT:    [[MUL21:%.*]] = shl nsw i32 [[U:%.*]], 2
+; CHECK-NEXT:    [[DOTSCALAR:%.*]] = add i32 [[Y:%.*]], 1
+; CHECK-NEXT:    [[DOTSCALAR1:%.*]] = add i32 [[DOTSCALAR]], [[DIV17]]
+; CHECK-NEXT:    [[DOTSCALAR2:%.*]] = add i32 [[DOTSCALAR1]], [[MUL5]]
+; CHECK-NEXT:    [[DOTSCALAR3:%.*]] = add i32 [[DOTSCALAR2]], [[DIV]]
+; CHECK-NEXT:    [[DOTSCALAR4:%.*]] = add i32 [[DOTSCALAR3]], [[MUL13]]
+; CHECK-NEXT:    [[DOTSCALAR5:%.*]] = add i32 [[DOTSCALAR4]], [[MUL]]
+; CHECK-NEXT:    [[DOTSCALAR6:%.*]] = add i32 [[DOTSCALAR5]], [[DIV9]]
+; CHECK-NEXT:    [[DOTSCALAR7:%.*]] = add i32 [[DOTSCALAR6]], [[MUL21]]
+; CHECK-NEXT:    [[DOTSCALAR8:%.*]] = add i32 [[DOTSCALAR7]], 317425
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[DOTSCALAR8]], i64 0
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[ADD29:%.*]] = add <4 x i32> [[TMP2]], [[NUM:%.*]]
+; CHECK-NEXT:    ret <4 x i32> [[ADD29]]
+;
+  %add = add <4 x i32> %num, <i32 1, i32 1, i32 1, i32 1>
+  %div = sdiv i32 %k, 2
+  %splatinsert = insertelement <4 x i32> poison, i32 %div, i32 0
+  %splat = shufflevector <4 x i32> %splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
+  %add1 = add <4 x i32> %add, %splat
+  %mul = mul nsw i32 %p, 6234
+  %splatinsert2 = insertelement <4 x i32> poison, i32 %mul, i32 0
+  %splat3 = shufflevector <4 x i32> %splatinsert2, <4 x i32> undef, <4 x i32> zeroinitializer
+  %add4 = add <4 x i32> %add1, %splat3
+  %mul5 = mul nsw i32 75, %h
+  %splatinsert6 = insertelement <4 x i32> poison, i32 %mul5, i32 0
+  %splat7 = shufflevector <4 x i32> %splatinsert6, <4 x i32> undef, <4 x i32> zeroinitializer
+  %add8 = add <4 x i32> %add4, %splat7
+  %div9 = sdiv i32 %j, 3452
+  %splatinsert10 = insertelement <4 x i32> poison, i32 %div9, i32 0
+  %splat11 = shufflevector <4 x i32> %splatinsert10, <4 x i32> undef, <4 x i32> zeroinitializer
+  %add12 = add <4 x i32> %add8, %splat11
+  %mul13 = mul nsw i32 53, %w
+  %splatinsert14 = insertelement <4 x i32> poison, i32 %mul13, i32 0
+  %splat15 = shufflevector <4 x i32> %splatinsert14, <4 x i32> undef, <4 x i32> zeroinitializer
+  %add16 = add <4 x i32> %add12, %splat15
+  %div17 = sdiv i32 %x, 820
+  %splatinsert18 = insertelement <4 x i32> poison, i32 %div17, i32 0
+  %splat19 = shufflevector <4 x i32> %splatinsert18, <4 x i32> undef, <4 x i32> zeroinitializer
+  %add20 = add <4 x i32> %add16, %splat19
+  %mul21 = mul nsw i32 4, %u
+  %splatinsert22 = insertelement <4 x i32> poison, i32 %mul21, i32 0
+  %splat23 = shufflevector <4 x i32> %splatinsert22, <4 x i32> undef, <4 x i32> zeroinitializer
+  %add24 = add <4 x i32> %add20, %splat23
+  %splatinsert25 = insertelement <4 x i32> poison, i32 %y, i32 0
+  %splat26 = shufflevector <4 x i32> %splatinsert25, <4 x i32> undef, <4 x i32> zeroinitializer
+  %add27 = add <4 x i32> %add24, %splat26
+  %add28 = add <4 x i32> %add27, <i32 25, i32 25, i32 25, i32 25>
+  %add29 = add <4 x i32> %add28, <i32 317400, i32 317400, i32 317400, i32 317400>
+  ret <4 x i32> %add29
+}
+
diff --git a/llvm/test/Transforms/PhaseOrdering/vector-trunc-inseltpoison.ll b/llvm/test/Transforms/PhaseOrdering/vector-trunc-inseltpoison.ll
new file mode 100644
index 0000000000000..b9cfc53bdac74
--- /dev/null
+++ b/llvm/test/Transforms/PhaseOrdering/vector-trunc-inseltpoison.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -O2                   -S -data-layout="e" < %s | FileCheck %s
+; RUN: opt -passes='default<O2>' -S -data-layout="e" < %s | FileCheck %s
+
+define <4 x i16> @truncate(<4 x i32> %x) {
+; CHECK-LABEL: @truncate(
+; CHECK-NEXT:    [[V3:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i16>
+; CHECK-NEXT:    ret <4 x i16> [[V3]]
+;
+  %x0 = extractelement <4 x i32> %x, i32 0
+  %t0 = trunc i32 %x0 to i16
+  %v0 = insertelement <4 x i16> poison, i16 %t0, i32 0
+  %x1 = extractelement <4 x i32> %x, i32 1
+  %t1 = trunc i32 %x1 to i16
+  %v1 = insertelement <4 x i16> %v0, i16 %t1, i32 1
+  %x2 = extractelement <4 x i32> %x, i32 2
+  %t2 = trunc i32 %x2 to i16
+  %v2 = insertelement <4 x i16> %v1, i16 %t2, i32 2
+  %x3 = extractelement <4 x i32> %x, i32 3
+  %t3 = trunc i32 %x3 to i16
+  %v3 = insertelement <4 x i16> %v2, i16 %t3, i32 3
+  ret <4 x i16> %v3
+}
diff --git a/llvm/test/Transforms/RewriteStatepointsForGC/base-vector-inseltpoison.ll b/llvm/test/Transforms/RewriteStatepointsForGC/base-vector-inseltpoison.ll
new file mode 100644
index 0000000000000..b7f4e131d9395
--- /dev/null
+++ b/llvm/test/Transforms/RewriteStatepointsForGC/base-vector-inseltpoison.ll
@@ -0,0 +1,279 @@
+; RUN: opt < %s -rewrite-statepoints-for-gc -S | FileCheck  %s
+; RUN: opt < %s -passes=rewrite-statepoints-for-gc -S | FileCheck  %s
+
+
+define i64 addrspace(1)* @test(<2 x i64 addrspace(1)*> %vec, i32 %idx) gc "statepoint-example" {
+; CHECK-LABEL: @test
+; CHECK: extractelement
+; CHECK: extractelement
+; CHECK: statepoint
+; CHECK: gc.relocate
+; CHECK-DAG: ; (%base_ee, %obj)
+; CHECK: gc.relocate
+; CHECK-DAG: ; (%base_ee, %base_ee)
+; Note that the second extractelement is actually redundant here.  A correct output would
+; be to reuse the existing obj as a base since it is actually a base pointer.
+entry:
+  %obj = extractelement <2 x i64 addrspace(1)*> %vec, i32 %idx
+  call void @do_safepoint() [ "deopt"() ]
+  ret i64 addrspace(1)* %obj
+}
+
+define i64 addrspace(1)* @test2(<2 x i64 addrspace(1)*>* %ptr, i1 %cnd, i32 %idx1, i32 %idx2) gc "statepoint-example" {
+; CHECK-LABEL: test2
+entry:
+  br i1 %cnd, label %taken, label %untaken
+
+taken:                                            ; preds = %entry
+  %obja = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr
+  br label %merge
+
+untaken:                                          ; preds = %entry
+  %objb = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr
+  br label %merge
+
+merge:                                            ; preds = %untaken, %taken
+  %vec = phi <2 x i64 addrspace(1)*> [ %obja, %taken ], [ %objb, %untaken ]
+  br i1 %cnd, label %taken2, label %untaken2
+
+taken2:                                           ; preds = %merge
+  %obj0 = extractelement <2 x i64 addrspace(1)*> %vec, i32 %idx1
+  br label %merge2
+
+untaken2:                                         ; preds = %merge
+  %obj1 = extractelement <2 x i64 addrspace(1)*> %vec, i32 %idx2
+  br label %merge2
+
+merge2:                                           ; preds = %untaken2, %taken2
+; CHECK-LABEL: merge2:
+; CHECK: %obj.base = phi i64 addrspace(1)*
+; CHECK: %obj = phi i64 addrspace(1)*
+; CHECK: statepoint
+; CHECK: gc.relocate
+; CHECK-DAG: ; (%obj.base, %obj)
+; CHECK: gc.relocate
+; CHECK-DAG: ; (%obj.base, %obj.base)
+  %obj = phi i64 addrspace(1)* [ %obj0, %taken2 ], [ %obj1, %untaken2 ]
+  call void @do_safepoint() [ "deopt"() ]
+  ret i64 addrspace(1)* %obj
+}
+
+define i64 addrspace(1)* @test3(i64 addrspace(1)* %ptr) gc "statepoint-example" {
+; CHECK-LABEL: test3
+; CHECK: insertelement
+; CHECK: extractelement
+; CHECK: statepoint
+; CHECK: gc.relocate
+; CHECK-DAG: (%obj.base, %obj)
+entry:
+  %vec = insertelement <2 x i64 addrspace(1)*> poison, i64 addrspace(1)* %ptr, i32 0
+  %obj = extractelement <2 x i64 addrspace(1)*> %vec, i32 0
+  call void @do_safepoint() [ "deopt"() ]
+  ret i64 addrspace(1)* %obj
+}
+
+define i64 addrspace(1)* @test4(i64 addrspace(1)* %ptr) gc "statepoint-example" {
+; CHECK-LABEL: test4
+; CHECK: statepoint
+; CHECK: gc.relocate
+; CHECK-DAG: ; (%obj.base, %obj)
+; When we can optimize an extractelement from a known
+; index and avoid introducing new base pointer instructions
+entry:
+  %derived = getelementptr i64, i64 addrspace(1)* %ptr, i64 16
+  %veca = insertelement <2 x i64 addrspace(1)*> poison, i64 addrspace(1)* %derived, i32 0
+  %vec = insertelement <2 x i64 addrspace(1)*> %veca, i64 addrspace(1)* %ptr, i32 1
+  %obj = extractelement <2 x i64 addrspace(1)*> %vec, i32 0
+  call void @do_safepoint() [ "deopt"() ]
+  ret i64 addrspace(1)* %obj
+}
+
+declare void @use(i64 addrspace(1)*) "gc-leaf-function"
+declare void @use_vec(<4 x i64 addrspace(1)*>) "gc-leaf-function"
+
+define void @test5(i1 %cnd, i64 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: @test5
+; CHECK: gc.relocate
+; CHECK-DAG: (%bdv.base, %bdv)
+; When we fundementally have to duplicate
+entry:
+  %gep = getelementptr i64, i64 addrspace(1)* %obj, i64 1
+  %vec = insertelement <2 x i64 addrspace(1)*> poison, i64 addrspace(1)* %gep, i32 0
+  %bdv = extractelement <2 x i64 addrspace(1)*> %vec, i32 0
+  call void @do_safepoint() [ "deopt"(i32 0, i32 -1, i32 0, i32 0, i32 0) ]
+  call void @use(i64 addrspace(1)* %bdv)
+  ret void
+}
+
+define void @test6(i1 %cnd, i64 addrspace(1)* %obj, i64 %idx) gc "statepoint-example" {
+; CHECK-LABEL: @test6
+; CHECK: %gep = getelementptr i64, i64 addrspace(1)* %obj, i64 1
+; CHECK: %vec.base = insertelement <2 x i64 addrspace(1)*> zeroinitializer, i64 addrspace(1)* %obj, i32 0, !is_base_value !0
+; CHECK: %vec = insertelement <2 x i64 addrspace(1)*> poison, i64 addrspace(1)* %gep, i32 0
+; CHECK: %bdv.base = extractelement <2 x i64 addrspace(1)*> %vec.base, i64 %idx, !is_base_value !0
+; CHECK:  %bdv = extractelement <2 x i64 addrspace(1)*> %vec, i64 %idx
+; CHECK: gc.statepoint
+; CHECK: gc.relocate
+; CHECK-DAG: (%bdv.base, %bdv)
+; A more complicated example involving vector and scalar bases.
+; This is derived from a failing test case when we didn't have correct
+; insertelement handling.
+entry:
+  %gep = getelementptr i64, i64 addrspace(1)* %obj, i64 1
+  %vec = insertelement <2 x i64 addrspace(1)*> poison, i64 addrspace(1)* %gep, i32 0
+  %bdv = extractelement <2 x i64 addrspace(1)*> %vec, i64 %idx
+  call void @do_safepoint() [ "deopt"(i32 0, i32 -1, i32 0, i32 0, i32 0) ]
+  call void @use(i64 addrspace(1)* %bdv)
+  ret void
+}
+
+define i64 addrspace(1)* @test7(i1 %cnd, i64 addrspace(1)* %obj, i64 addrspace(1)* %obj2) gc "statepoint-example" {
+; CHECK-LABEL: @test7
+entry:
+  %vec = insertelement <2 x i64 addrspace(1)*> poison, i64 addrspace(1)* %obj2, i32 0
+  br label %merge1
+
+merge1:                                           ; preds = %merge1, %entry
+; CHECK-LABEL: merge1:
+; CHECK: vec2.base
+; CHECK: vec2
+; CHECK: gep
+; CHECK: vec3.base
+; CHECK: vec3
+  %vec2 = phi <2 x i64 addrspace(1)*> [ %vec, %entry ], [ %vec3, %merge1 ]
+  %gep = getelementptr i64, i64 addrspace(1)* %obj2, i64 1
+  %vec3 = insertelement <2 x i64 addrspace(1)*> poison, i64 addrspace(1)* %gep, i32 0
+  br i1 %cnd, label %merge1, label %next1
+
+next1:                                            ; preds = %merge1
+; CHECK-LABEL: next1:
+; CHECK: bdv.base = 
+; CHECK: bdv = 
+  %bdv = extractelement <2 x i64 addrspace(1)*> %vec2, i32 0
+  br label %merge
+
+merge:                                            ; preds = %merge, %next1
+; CHECK-LABEL: merge:
+; CHECK: %objb.base
+; CHECK: %objb
+; CHECK: gc.statepoint
+; CHECK: gc.relocate
+; CHECK-DAG: (%objb.base, %objb)
+  %objb = phi i64 addrspace(1)* [ %obj, %next1 ], [ %bdv, %merge ]
+  br i1 %cnd, label %merge, label %next
+
+next:                                             ; preds = %merge
+  call void @do_safepoint() [ "deopt"(i32 0, i32 -1, i32 0, i32 0, i32 0) ]
+  ret i64 addrspace(1)* %objb
+}
+
+; identify base for shufflevector
+define void @test8(i64 addrspace(1)* %obj, i64 %idx) gc "statepoint-example" {
+; CHECK-LABEL: @test8
+; CHECK: %gep = getelementptr i64, i64 addrspace(1)* %obj, i64 1
+; CHECK: %gep2 = getelementptr i64, i64 addrspace(1)* %obj, i64 2
+; CHECK: %vec1.base = insertelement <4 x i64 addrspace(1)*> zeroinitializer, i64 addrspace(1)* %obj, i32 0, !is_base_value !0
+; CHECK: %vec1 = insertelement <4 x i64 addrspace(1)*> poison, i64 addrspace(1)* %gep, i32 0
+; CHECK: %vec2.base = insertelement <4 x i64 addrspace(1)*> zeroinitializer, i64 addrspace(1)* %obj, i32 2, !is_base_value !0
+; CHECK: %vec2 = insertelement <4 x i64 addrspace(1)*> poison, i64 addrspace(1)* %gep2, i32 2
+; CHECK: %vec.base = shufflevector <4 x i64 addrspace(1)*> %vec1.base, <4 x i64 addrspace(1)*> %vec2.base, <2 x i32> <i32 0, i32 2>, !is_base_value !0
+; CHECK: %vec = shufflevector <4 x i64 addrspace(1)*> %vec1, <4 x i64 addrspace(1)*> %vec2, <2 x i32> <i32 0, i32 2>
+; CHECK: %bdv.base = extractelement <2 x i64 addrspace(1)*> %vec.base, i64 %idx, !is_base_value !0
+; CHECK: %bdv = extractelement <2 x i64 addrspace(1)*> %vec, i64 %idx
+; CHECK: gc.statepoint
+; CHECK: gc.relocate
+; CHECK-DAG: (%bdv.base, %bdv)
+entry:
+  %gep = getelementptr i64, i64 addrspace(1)* %obj, i64 1
+  %gep2 = getelementptr i64, i64 addrspace(1)* %obj, i64 2
+  %vec1 = insertelement <4 x i64 addrspace(1)*> poison, i64 addrspace(1)* %gep, i32 0
+  %vec2 = insertelement <4 x i64 addrspace(1)*> poison, i64 addrspace(1)* %gep2, i32 2
+  %vec = shufflevector <4 x i64 addrspace(1)*> %vec1, <4 x i64 addrspace(1)*> %vec2, <2 x i32> <i32 0, i32 2>
+  %bdv = extractelement <2 x i64 addrspace(1)*> %vec, i64 %idx
+  call void @do_safepoint() [ "deopt"(i32 0, i32 -1, i32 0, i32 0, i32 0) ]
+  call void @use(i64 addrspace(1)* %bdv)
+  ret void
+}
+
+; Since the same 'base' vector is used in the shuffle operands, we do not need
+; create a shufflevector base.
+define void @test9(<4 x i64 addrspace(1)*> %vec1, i64 %idx) gc "statepoint-example" {
+; CHECK-LABEL: @test9
+; CHECK: %vec = shufflevector <4 x i64 addrspace(1)*> %vec1, <4 x i64 addrspace(1)*> %vec1, <2 x i32> <i32 0, i32 2>
+; CHECK: %base_ee = extractelement <4 x i64 addrspace(1)*> %vec1, i64 %idx, !is_base_value !0
+; CHECK: %bdv = extractelement <2 x i64 addrspace(1)*> %vec, i64 %idx
+; CHECK: gc.statepoint
+; CHECK: gc.relocate
+; CHECK-DAG: (%base_ee, %bdv)
+entry:
+ ; shrinking vec1 into vec
+  %vec = shufflevector <4 x i64 addrspace(1)*> %vec1, <4 x i64 addrspace(1)*> %vec1, <2 x i32> <i32 0, i32 2>
+  %bdv = extractelement <2 x i64 addrspace(1)*> %vec, i64 %idx
+  call void @do_safepoint() [ "deopt"(i32 0, i32 -1, i32 0, i32 0, i32 0) ]
+  call void @use(i64 addrspace(1)* %bdv)
+  ret void
+}
+
+; vector operand of shufflevector is a phi
+define i64 addrspace(1)* @test10(i1 %cnd, i64 addrspace(1)* %obj, i64 addrspace(1)* %obj2) gc "statepoint-example" {
+; CHECK-LABEL: @test10
+entry:
+  %vec1 = insertelement <4 x i64 addrspace(1)*> poison, i64 addrspace(1)* %obj, i32 0
+  br i1 %cnd, label %here, label %merge
+
+here:
+  %vec2 = insertelement <4 x i64 addrspace(1)*> poison, i64 addrspace(1)* %obj2, i32 2
+  br label %merge
+
+merge:                                           ; preds = %merge, %entry, %here
+; CHECK-LABEL: merge:
+; CHECK: %vec.base = phi <4 x i64 addrspace(1)*> [ %vec1.base, %entry ], [ %vec2.base, %here ], [ %vec3.base, %merge ], !is_base_value !0
+; CHECK: vec
+; CHECK: vec3.base = shufflevector <4 x i64 addrspace(1)*> %vec.base, <4 x i64 addrspace(1)*> %vec.base
+; CHECK: vec3
+; CHECK: bdv.base
+; CHECK: bdv
+  %vec = phi <4 x i64 addrspace(1)*> [ %vec1, %entry ], [ %vec2, %here], [ %vec3, %merge]
+  %vec3 = shufflevector <4 x i64 addrspace(1)*> %vec, <4 x i64 addrspace(1)*> %vec, <4 x i32> <i32 2, i32 0, i32 1, i32 3>
+  %bdv = extractelement <4 x i64 addrspace(1)*> %vec3, i32 0
+  br i1 %cnd, label %merge, label %next
+
+next:
+; CHECK-LABEL: next:
+; CHECK: gc.statepoint
+; CHECK: gc.relocate
+; CHECK-DAG: (%bdv.base, %bdv)
+  call void @do_safepoint() [ "deopt"(i32 0, i32 -1, i32 0, i32 0, i32 0) ]
+  ret i64 addrspace(1)* %bdv
+}
+declare void @do_safepoint()
+
+define void @test11(<4 x i64 addrspace(1)*> %vec1) gc "statepoint-example" {
+; CHECK-LABEL: @test11(
+; CHECK: @llvm.experimental.gc.statepoint.p0f_isVoidf{{.*}}<4 x i64 addrspace(1)*> %vec1)
+; CHECK: %vec1.relocated = call coldcc <4 x i8 addrspace(1)*> @llvm.experimental.gc.relocate.v4p1i8
+; CHECK: %vec1.relocated.casted = bitcast <4 x i8 addrspace(1)*> %vec1.relocated to <4 x i64 addrspace(1)*>
+; CHECK: %vec2.remat = getelementptr i64, <4 x i64 addrspace(1)*> %vec1.relocated.casted, i32 1024
+; CHECK: call void @use_vec(<4 x i64 addrspace(1)*> %vec2.remat)
+entry:
+  %vec2 = getelementptr i64, <4 x i64 addrspace(1)*> %vec1, i32 1024
+  call void @do_safepoint() [ "deopt"(i32 0, i32 -1, i32 0, i32 0, i32 0) ]
+  call void @use_vec(<4 x i64 addrspace(1) *> %vec2)
+  ret void
+}
+
+declare <4 x i64 addrspace(1)*> @def_vec() "gc-leaf-function"
+
+define void @test12(<4 x i64 addrspace(1)*> %vec1) gc "statepoint-example" {
+; CHECK-LABEL: @test12(
+; CHECK: @llvm.experimental.gc.statepoint.p0f_isVoidf{{.*}}<4 x i64 addrspace(1)*> %vec)
+; CHECK-NEXT: %vec.relocated = call coldcc <4 x i8 addrspace(1)*> @llvm.experimental.gc.relocate.v4p1i8(
+; CHECK-NEXT: %vec.relocated.casted = bitcast <4 x i8 addrspace(1)*> %vec.relocated to <4 x i64 addrspace(1)*>
+; CHECK-NEXT: call void @use_vec(<4 x i64 addrspace(1)*> %vec.relocated.casted)
+; CHECK-NEXT: ret void
+entry:
+  %vec = call <4 x i64 addrspace(1)*> @def_vec()
+  call void @do_safepoint() [ "deopt"() ]
+  call void @use_vec(<4 x i64 addrspace(1)*> %vec)
+  ret void
+}
diff --git a/llvm/test/Transforms/RewriteStatepointsForGC/check_traversal_order-inseltpoison.ll b/llvm/test/Transforms/RewriteStatepointsForGC/check_traversal_order-inseltpoison.ll
new file mode 100644
index 0000000000000..7a7d65117cabc
--- /dev/null
+++ b/llvm/test/Transforms/RewriteStatepointsForGC/check_traversal_order-inseltpoison.ll
@@ -0,0 +1,38 @@
+; RUN: opt -S -rewrite-statepoints-for-gc < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare void @f()
+declare void @g(i8 addrspace(1)*, i8 addrspace(1)*)
+declare i32 @personality_function()
+
+; Make sure that we do not fail assertion because we process call of @g before
+; we process the call of @f.
+
+define void @test_01(i8 addrspace(1)* %p, i1 %cond) gc "statepoint-example" personality i32 ()* @personality_function {
+
+; CHECK-LABEL: @test_01(
+
+entry:
+  %tmp0 = insertelement <2 x i8 addrspace(1)*> poison, i8 addrspace(1)* %p, i32 0
+  %tmp1 = insertelement <2 x i8 addrspace(1)*> %tmp0, i8 addrspace(1)* %p, i32 1
+  %tmp2 = extractelement <2 x i8 addrspace(1)*> %tmp1, i32 1
+  %tmp3 = extractelement <2 x i8 addrspace(1)*> %tmp1, i32 0
+  br label %loop
+
+loop:
+  br i1 %cond, label %cond_block, label %exit
+
+cond_block:
+  br i1 %cond, label %backedge, label %exit
+
+exit:
+  %tmp4 = phi i8 addrspace(1)* [ %tmp2, %loop ], [ %tmp2, %cond_block ]
+  call void @g(i8 addrspace(1)* %tmp3, i8 addrspace(1)* %tmp4)
+  ret void
+
+backedge:
+  call void @f()
+  br label %loop
+}
diff --git a/llvm/test/Transforms/RewriteStatepointsForGC/live-vector-nosplit-inseltpoison.ll b/llvm/test/Transforms/RewriteStatepointsForGC/live-vector-nosplit-inseltpoison.ll
new file mode 100644
index 0000000000000..3051655f4e29b
--- /dev/null
+++ b/llvm/test/Transforms/RewriteStatepointsForGC/live-vector-nosplit-inseltpoison.ll
@@ -0,0 +1,119 @@
+; Test that we can correctly handle vectors of pointers in statepoint 
+; rewriting.  
+; RUN: opt < %s -rewrite-statepoints-for-gc -S | FileCheck  %s
+; RUN: opt < %s -passes=rewrite-statepoints-for-gc -S | FileCheck  %s
+
+; A non-vector relocation for comparison
+define i64 addrspace(1)* @test(i64 addrspace(1)* %obj) gc "statepoint-example" {
+; CHECK-LABEL: test
+; CHECK: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: ret i64 addrspace(1)*
+; A base vector from a argument
+entry:
+  call void @do_safepoint() [ "deopt"() ]
+  ret i64 addrspace(1)* %obj
+}
+
+; A vector argument
+define <2 x i64 addrspace(1)*> @test2(<2 x i64 addrspace(1)*> %obj) gc "statepoint-example" {
+; CHECK-LABEL: test2
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*>
+  call void @do_safepoint() [ "deopt"() ]
+  ret <2 x i64 addrspace(1)*> %obj
+}
+
+; A load
+define <2 x i64 addrspace(1)*> @test3(<2 x i64 addrspace(1)*>* %ptr) gc "statepoint-example" {
+; CHECK-LABEL: test3
+; CHECK: load
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*>
+entry:
+  %obj = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr
+  call void @do_safepoint() [ "deopt"() ]
+  ret <2 x i64 addrspace(1)*> %obj
+}
+
+declare i32 @fake_personality_function()
+
+; When a statepoint is an invoke rather than a call
+define <2 x i64 addrspace(1)*> @test4(<2 x i64 addrspace(1)*>* %ptr) gc "statepoint-example" personality i32 ()* @fake_personality_function {
+; CHECK-LABEL: test4
+; CHECK: load
+; CHECK-NEXT: gc.statepoint
+entry:
+  %obj = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr
+  invoke void @do_safepoint() [ "deopt"() ]
+          to label %normal_return unwind label %exceptional_return
+
+normal_return:                                    ; preds = %entry
+; CHECK-LABEL: normal_return:
+; CHECK: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*>
+  ret <2 x i64 addrspace(1)*> %obj
+
+exceptional_return:                               ; preds = %entry
+; CHECK-LABEL: exceptional_return:
+; CHECK: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*>
+  %landing_pad4 = landingpad token
+          cleanup
+  ret <2 x i64 addrspace(1)*> %obj
+}
+
+; A newly created vector
+define <2 x i64 addrspace(1)*> @test5(i64 addrspace(1)* %p) gc "statepoint-example" {
+; CHECK-LABEL: test5
+; CHECK: insertelement
+; CHECK-NEXT: insertelement
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*> %vec.relocated.casted
+entry:
+  %vec = insertelement <2 x i64 addrspace(1)*> poison, i64 addrspace(1)* %p, i32 0
+  call void @do_safepoint() [ "deopt"() ]
+  ret <2 x i64 addrspace(1)*> %vec
+}
+
+; A merge point
+define <2 x i64 addrspace(1)*> @test6(i1 %cnd, <2 x i64 addrspace(1)*>* %ptr) gc "statepoint-example" {
+; CHECK-LABEL: test6
+entry:
+  br i1 %cnd, label %taken, label %untaken
+
+taken:                                            ; preds = %entry
+  %obja = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr
+  br label %merge
+
+untaken:                                          ; preds = %entry
+  %objb = load <2 x i64 addrspace(1)*>, <2 x i64 addrspace(1)*>* %ptr
+  br label %merge
+
+merge:                                            ; preds = %untaken, %taken
+; CHECK-LABEL: merge:
+; CHECK-NEXT: = phi
+; CHECK-NEXT: = phi
+; CHECK-NEXT: gc.statepoint
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: gc.relocate
+; CHECK-NEXT: bitcast
+; CHECK-NEXT: ret <2 x i64 addrspace(1)*>
+  %obj = phi <2 x i64 addrspace(1)*> [ %obja, %taken ], [ %objb, %untaken ]
+  call void @do_safepoint() [ "deopt"() ]
+  ret <2 x i64 addrspace(1)*> %obj
+}
+
+declare void @do_safepoint()
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
new file mode 100644
index 0000000000000..2e437ead6d2c2
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/accelerate-vector-functions-inseltpoison.ll
@@ -0,0 +1,1300 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -inject-tli-mappings -slp-vectorizer -vector-library=Accelerate -S %s | FileCheck %s
+; RUN: opt -inject-tli-mappings -slp-vectorizer -S %s | FileCheck --check-prefix NOACCELERATE %s
+
+target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+target triple = "arm64-apple-ios14.0.0"
+
+declare float @llvm.sin.f32(float)
+
+; Accelerate provides sin() for <4 x float>
+define <4 x float> @int_sin_4x(<4 x float>* %a) {
+; CHECK-LABEL: @int_sin_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vsinf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @int_sin_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @llvm.sin.f32(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @llvm.sin.f32(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @llvm.sin.f32(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @llvm.sin.f32(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+
+declare float @ceilf(float) readonly
+
+define <4 x float> @ceil_4x(<4 x float>* %a) {
+; CHECK-LABEL: @ceil_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @ceil_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.ceil.v4f32(<4 x float> [[TMP0]])
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; NOACCELERATE-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @ceilf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @ceilf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @ceilf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @ceilf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+
+declare float @fabsf(float) readonly
+
+define <4 x float> @fabs_4x(<4 x float>* %a) {
+; CHECK-LABEL: @fabs_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @fabs_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]])
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; NOACCELERATE-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @fabsf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @fabsf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @fabsf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @fabsf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @llvm.fabs.f32(float)
+define <4 x float> @int_fabs_4x(<4 x float>* %a) {
+; CHECK-LABEL: @int_fabs_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @int_fabs_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP0]])
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; NOACCELERATE-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @llvm.fabs.f32(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @llvm.fabs.f32(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @llvm.fabs.f32(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @llvm.fabs.f32(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @floorf(float) readonly
+define <4 x float> @floor_4x(<4 x float>* %a) {
+; CHECK-LABEL: @floor_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.floor.v4f32(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @floor_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.floor.v4f32(<4 x float> [[TMP0]])
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; NOACCELERATE-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @floorf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @floorf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @floorf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @floorf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @sqrtf(float) readonly
+define <4 x float> @sqrt_4x(<4 x float>* %a) {
+; CHECK-LABEL: @sqrt_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @sqrt_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]])
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; NOACCELERATE-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @sqrtf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @sqrtf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @sqrtf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @sqrtf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @expf(float) readonly
+define <4 x float> @exp_4x(<4 x float>* %a) {
+; CHECK-LABEL: @exp_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vexpf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @exp_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @expf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @expf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @expf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @expf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @expf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @expf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @expf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @expf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @expm1f(float) readonly
+define <4 x float> @expm1_4x(<4 x float>* %a) {
+; CHECK-LABEL: @expm1_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vexpm1f(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @expm1_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @expm1f(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @expm1f(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @expm1f(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @expm1f(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @expm1f(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @expm1f(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @expm1f(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @expm1f(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @logf(float) readonly
+define <4 x float> @log_4x(<4 x float>* %a) {
+; CHECK-LABEL: @log_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vlogf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @log_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @logf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @logf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @logf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @logf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @logf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @logf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @logf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @logf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @log1pf(float) readonly
+define <4 x float> @log1p_4x(<4 x float>* %a) {
+; CHECK-LABEL: @log1p_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vlog1pf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @log1p_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @log1pf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @log1pf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @log1pf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @log1pf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @log1pf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @log1pf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @log1pf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @log1pf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @log10pf(float) readonly
+define <4 x float> @log10p_4x(<4 x float>* %a) {
+; CHECK-LABEL: @log10p_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call fast float @log10pf(float [[VECEXT]])
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call fast float @log10pf(float [[VECEXT_1]])
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; CHECK-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call fast float @log10pf(float [[VECEXT_2]])
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; CHECK-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; CHECK-NEXT:    [[TMP4:%.*]] = tail call fast float @log10pf(float [[VECEXT_3]])
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @log10p_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @log10pf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @log10pf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @log10pf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @log10pf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @log10pf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @log10pf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @log10pf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @log10pf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @logbf(float) readonly
+define <4 x float> @logb_4x(<4 x float>* %a) {
+; CHECK-LABEL: @logb_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vlogbf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @logb_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @logbf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @logbf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @logbf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @logbf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @logbf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @logbf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @logbf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @logbf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @sinf(float) readonly
+define <4 x float> @sin_4x(<4 x float>* %a) {
+; CHECK-LABEL: @sin_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vsinf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @sin_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @sinf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @sinf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @sinf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @sinf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @sinf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @sinf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @sinf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @sinf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @cosf(float) readonly
+define <4 x float> @cos_4x(<4 x float>* %a) {
+; CHECK-LABEL: @cos_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vcosf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @cos_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @cosf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @cosf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @cosf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @cosf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @cosf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @cosf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @cosf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @cosf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @tanf(float) readonly
+define <4 x float> @tan_4x(<4 x float>* %a) {
+; CHECK-LABEL: @tan_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vtanf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @tan_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @tanf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @tanf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @tanf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @tanf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @tanf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @tanf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @tanf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @tanf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @asinf(float) readonly
+define <4 x float> @asin_4x(<4 x float>* %a) {
+; CHECK-LABEL: @asin_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vasinf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @asin_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @asinf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @asinf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @asinf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @asinf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @asinf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @asinf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @asinf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @asinf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @acosf(float) readonly
+define <4 x float> @acos_4x(<4 x float>* %a) {
+; CHECK-LABEL: @acos_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vacosf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @acos_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @acosf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @acosf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @acosf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @acosf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @acosf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @acosf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @acosf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @acosf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @atanf(float) readonly
+define <4 x float> @atan_4x(<4 x float>* %a) {
+; CHECK-LABEL: @atan_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vatanf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @atan_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @atanf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @atanf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @atanf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @atanf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @atanf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @atanf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @atanf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @atanf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @sinhf(float) readonly
+define <4 x float> @sinh_4x(<4 x float>* %a) {
+; CHECK-LABEL: @sinh_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vsinhf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @sinh_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @sinhf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @sinhf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @sinhf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @sinhf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @sinhf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @sinhf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @sinhf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @sinhf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @coshf(float) readonly
+define <4 x float> @cosh_4x(<4 x float>* %a) {
+; CHECK-LABEL: @cosh_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vcoshf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @cosh_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @coshf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @coshf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @coshf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @coshf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @coshf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @coshf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @coshf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @coshf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @tanhf(float) readonly
+define <4 x float> @tanh_4x(<4 x float>* %a) {
+; CHECK-LABEL: @tanh_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vtanhf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @tanh_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @tanhf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @tanhf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @tanhf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @tanhf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @tanhf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @tanhf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @tanhf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @tanhf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @asinhf(float) readonly
+define <4 x float> @asinh_4x(<4 x float>* %a) {
+; CHECK-LABEL: @asinh_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vasinhf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @asinh_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @asinhf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @asinhf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @asinhf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @asinhf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @asinhf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @asinhf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @asinhf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @asinhf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @acoshf(float) readonly
+define <4 x float> @acosh_4x(<4 x float>* %a) {
+; CHECK-LABEL: @acosh_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vacoshf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @acosh_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @acoshf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @acoshf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @acoshf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @acoshf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @acoshf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @acoshf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @acoshf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @acoshf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+declare float @atanhf(float) readonly
+define <4 x float> @atanh_4x(<4 x float>* %a) {
+; CHECK-LABEL: @atanh_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vatanhf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @atanh_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @atanhf(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @atanhf(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @atanhf(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @atanhf(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @atanhf(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @atanhf(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @atanhf(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @atanhf(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+
+; Accelerate *does not* provide sin() for <2 x float>.
+define <2 x float> @sin_2x(<2 x float>* %a) {
+; CHECK-LABEL: @sin_2x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x float>, <2 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <2 x float> [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT]]) [[ATTR2:#.*]]
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECEXT_1:%.*]] = extractelement <2 x float> [[TMP0]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT_1]]) [[ATTR2]]
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <2 x float> [[VECINS]], float [[TMP2]], i32 1
+; CHECK-NEXT:    ret <2 x float> [[VECINS_1]]
+;
+; NOACCELERATE-LABEL: @sin_2x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <2 x float>, <2 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <2 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <2 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @llvm.sin.f32(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <2 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    ret <2 x float> [[VECINS_1]]
+;
+entry:
+  %0 = load <2 x float>, <2 x float>* %a, align 16
+  %vecext = extractelement <2 x float> %0, i32 0
+  %1 = tail call fast float @llvm.sin.f32(float %vecext)
+  %vecins = insertelement <2 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <2 x float> %0, i32 1
+  %2 = tail call fast float @llvm.sin.f32(float %vecext.1)
+  %vecins.1 = insertelement <2 x float> %vecins, float %2, i32 1
+  ret <2 x float> %vecins.1
+}
+
+
+declare float @llvm.cos.f32(float)
+
+; Accelerate provides cos() for <4 x float>
+define <4 x float> @int_cos_4x(<4 x float>* %a) {
+; CHECK-LABEL: @int_cos_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vcosf(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+; NOACCELERATE-LABEL: @int_cos_4x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @llvm.cos.f32(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @llvm.cos.f32(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; NOACCELERATE-NEXT:    [[TMP3:%.*]] = tail call fast float @llvm.cos.f32(float [[VECEXT_2]])
+; NOACCELERATE-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; NOACCELERATE-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; NOACCELERATE-NEXT:    [[TMP4:%.*]] = tail call fast float @llvm.cos.f32(float [[VECEXT_3]])
+; NOACCELERATE-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; NOACCELERATE-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @llvm.cos.f32(float %vecext)
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @llvm.cos.f32(float %vecext.1)
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @llvm.cos.f32(float %vecext.2)
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @llvm.cos.f32(float %vecext.3)
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+
+; Accelerate *does not* provide cos() for <2 x float>.
+define <2 x float> @cos_2x(<2 x float>* %a) {
+; CHECK-LABEL: @cos_2x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <2 x float>, <2 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <2 x float> [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call fast float @llvm.cos.f32(float [[VECEXT]]) [[ATTR3:#.*]]
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECEXT_1:%.*]] = extractelement <2 x float> [[TMP0]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call fast float @llvm.cos.f32(float [[VECEXT_1]]) [[ATTR3]]
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <2 x float> [[VECINS]], float [[TMP2]], i32 1
+; CHECK-NEXT:    ret <2 x float> [[VECINS_1]]
+;
+; NOACCELERATE-LABEL: @cos_2x(
+; NOACCELERATE-NEXT:  entry:
+; NOACCELERATE-NEXT:    [[TMP0:%.*]] = load <2 x float>, <2 x float>* [[A:%.*]], align 16
+; NOACCELERATE-NEXT:    [[VECEXT:%.*]] = extractelement <2 x float> [[TMP0]], i32 0
+; NOACCELERATE-NEXT:    [[TMP1:%.*]] = tail call fast float @llvm.cos.f32(float [[VECEXT]])
+; NOACCELERATE-NEXT:    [[VECINS:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
+; NOACCELERATE-NEXT:    [[VECEXT_1:%.*]] = extractelement <2 x float> [[TMP0]], i32 1
+; NOACCELERATE-NEXT:    [[TMP2:%.*]] = tail call fast float @llvm.cos.f32(float [[VECEXT_1]])
+; NOACCELERATE-NEXT:    [[VECINS_1:%.*]] = insertelement <2 x float> [[VECINS]], float [[TMP2]], i32 1
+; NOACCELERATE-NEXT:    ret <2 x float> [[VECINS_1]]
+;
+entry:
+  %0 = load <2 x float>, <2 x float>* %a, align 16
+  %vecext = extractelement <2 x float> %0, i32 0
+  %1 = tail call fast float @llvm.cos.f32(float %vecext)
+  %vecins = insertelement <2 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <2 x float> %0, i32 1
+  %2 = tail call fast float @llvm.cos.f32(float %vecext.1)
+  %vecins.1 = insertelement <2 x float> %vecins, float %2, i32 1
+  ret <2 x float> %vecins.1
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
index 3dae1a7ca6d37..8539a5e9d8a60 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/getelementptr.ll
@@ -46,7 +46,7 @@ define i32 @getelementptr_4x32(i32* nocapture readonly %g, i32 %n, i32 %x, i32 %
 ; CHECK-NEXT:    [[CMP31:%.*]] = icmp sgt i32 [[N:%.*]], 0
 ; CHECK-NEXT:    br i1 [[CMP31]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]]
 ; CHECK:       for.body.preheader:
-; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>, i32 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, i32 [[X:%.*]], i32 1
 ; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> [[TMP0]], i32 [[Y:%.*]], i32 2
 ; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[Z:%.*]], i32 3
 ; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
@@ -84,7 +84,7 @@ define i32 @getelementptr_4x32(i32* nocapture readonly %g, i32 %n, i32 %x, i32 %
 ; CHECK-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[G]], i64 [[TMP17]]
 ; CHECK-NEXT:    [[T12:%.*]] = load i32, i32* [[ARRAYIDX15]], align 4
 ; CHECK-NEXT:    [[TMP18:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[ADD11]], i32 1
-; CHECK-NEXT:    [[TMP19:%.*]] = insertelement <2 x i32> <i32 1, i32 undef>, i32 [[T12]], i32 1
+; CHECK-NEXT:    [[TMP19:%.*]] = insertelement <2 x i32> <i32 1, i32 poison>, i32 [[T12]], i32 1
 ; CHECK-NEXT:    [[TMP20]] = add nsw <2 x i32> [[TMP18]], [[TMP19]]
 ; CHECK-NEXT:    [[TMP21:%.*]] = extractelement <2 x i32> [[TMP20]], i32 0
 ; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[TMP21]], [[N]]
@@ -188,7 +188,7 @@ define i32 @getelementptr_2x32(i32* nocapture readonly %g, i32 %n, i32 %x, i32 %
 ; CHECK-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds i32, i32* [[G]], i64 [[TMP14]]
 ; CHECK-NEXT:    [[T12:%.*]] = load i32, i32* [[ARRAYIDX15]], align 4
 ; CHECK-NEXT:    [[TMP15:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[ADD11]], i32 1
-; CHECK-NEXT:    [[TMP16:%.*]] = insertelement <2 x i32> <i32 1, i32 undef>, i32 [[T12]], i32 1
+; CHECK-NEXT:    [[TMP16:%.*]] = insertelement <2 x i32> <i32 1, i32 poison>, i32 [[T12]], i32 1
 ; CHECK-NEXT:    [[TMP17]] = add nsw <2 x i32> [[TMP15]], [[TMP16]]
 ; CHECK-NEXT:    [[TMP18:%.*]] = extractelement <2 x i32> [[TMP17]], i32 0
 ; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i32 [[TMP18]], [[N]]
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/insertelement-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/insertelement-inseltpoison.ll
new file mode 100644
index 0000000000000..bf81c9e2f10d3
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/insertelement-inseltpoison.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -S 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; WARN-NOT: warning
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-unknown-linux-gnu"
+
+define <2 x float> @insertelement-fixed-vector() {
+; CHECK-LABEL: @insertelement-fixed-vector(
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <2 x float> @llvm.fabs.v2f32(<2 x float> undef)
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <2 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <2 x float> [[I0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    ret <2 x float> [[I1]]
+;
+  %f0 = tail call fast float @llvm.fabs.f32(float undef)
+  %f1 = tail call fast float @llvm.fabs.f32(float undef)
+  %i0 = insertelement <2 x float> poison, float %f0, i32 0
+  %i1 = insertelement <2 x float> %i0, float %f1, i32 1
+  ret <2 x float> %i1
+}
+
+; TODO: llvm.fabs could be optimized in vector form. It's legal to extract
+; elements from fixed-length vector and insert into scalable vector.
+define <vscale x 2 x float> @insertelement-scalable-vector() {
+; CHECK-LABEL: @insertelement-scalable-vector(
+; CHECK-NEXT:    [[F0:%.*]] = tail call fast float @llvm.fabs.f32(float undef)
+; CHECK-NEXT:    [[F1:%.*]] = tail call fast float @llvm.fabs.f32(float undef)
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <vscale x 2 x float> poison, float [[F0]], i32 0
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <vscale x 2 x float> [[I0]], float [[F1]], i32 1
+; CHECK-NEXT:    ret <vscale x 2 x float> [[I1]]
+;
+  %f0 = tail call fast float @llvm.fabs.f32(float undef)
+  %f1 = tail call fast float @llvm.fabs.f32(float undef)
+  %i0 = insertelement <vscale x 2 x float> poison, float %f0, i32 0
+  %i1 = insertelement <vscale x 2 x float> %i0, float %f1, i32 1
+  ret <vscale x 2 x float> %i1
+}
+
+; Function Attrs: nounwind readnone speculatable willreturn
+declare float @llvm.fabs.f32(float)
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll
new file mode 100644
index 0000000000000..5f953aa6d9950
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/transpose-inseltpoison.ll
@@ -0,0 +1,294 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -instcombine -S | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+define <2 x i64> @build_vec_v2i64(<2 x i64> %v0, <2 x i64> %v1) {
+; CHECK-LABEL: @build_vec_v2i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i64> [[V0:%.*]], <2 x i64> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[V1:%.*]], <2 x i64> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    [[TMP3:%.*]] = add <2 x i64> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = sub <2 x i64> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP4]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[TMP6:%.*]] = add <2 x i64> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP7:%.*]] = sub <2 x i64> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> [[TMP7]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[TMP9:%.*]] = add <2 x i64> [[TMP8]], [[TMP5]]
+; CHECK-NEXT:    ret <2 x i64> [[TMP9]]
+;
+  %v0.0 = extractelement <2 x i64> %v0, i32 0
+  %v0.1 = extractelement <2 x i64> %v0, i32 1
+  %v1.0 = extractelement <2 x i64> %v1, i32 0
+  %v1.1 = extractelement <2 x i64> %v1, i32 1
+  %tmp0.0 = add i64 %v0.0, %v1.0
+  %tmp0.1 = add i64 %v0.1, %v1.1
+  %tmp1.0 = sub i64 %v0.0, %v1.0
+  %tmp1.1 = sub i64 %v0.1, %v1.1
+  %tmp2.0 = add i64 %tmp0.0, %tmp0.1
+  %tmp2.1 = add i64 %tmp1.0, %tmp1.1
+  %tmp3.0 = insertelement <2 x i64> poison, i64 %tmp2.0, i32 0
+  %tmp3.1 = insertelement <2 x i64> %tmp3.0, i64 %tmp2.1, i32 1
+  ret <2 x i64> %tmp3.1
+}
+
+define void @store_chain_v2i64(i64* %a, i64* %b, i64* %c) {
+; CHECK-LABEL: @store_chain_v2i64(
+; CHECK-NEXT:    [[A_1:%.*]] = getelementptr i64, i64* [[A:%.*]], i64 1
+; CHECK-NEXT:    [[B_1:%.*]] = getelementptr i64, i64* [[B:%.*]], i64 1
+; CHECK-NEXT:    [[C_1:%.*]] = getelementptr i64, i64* [[C:%.*]], i64 1
+; CHECK-NEXT:    [[V0_0:%.*]] = load i64, i64* [[A]], align 8
+; CHECK-NEXT:    [[V0_1:%.*]] = load i64, i64* [[A_1]], align 8
+; CHECK-NEXT:    [[V1_0:%.*]] = load i64, i64* [[B]], align 8
+; CHECK-NEXT:    [[V1_1:%.*]] = load i64, i64* [[B_1]], align 8
+; CHECK-NEXT:    [[TMP0_0:%.*]] = add i64 [[V0_0]], [[V1_0]]
+; CHECK-NEXT:    [[TMP0_1:%.*]] = add i64 [[V0_1]], [[V1_1]]
+; CHECK-NEXT:    [[TMP1_0:%.*]] = sub i64 [[V0_0]], [[V1_0]]
+; CHECK-NEXT:    [[TMP1_1:%.*]] = sub i64 [[V0_1]], [[V1_1]]
+; CHECK-NEXT:    [[TMP2_0:%.*]] = add i64 [[TMP0_0]], [[TMP0_1]]
+; CHECK-NEXT:    [[TMP2_1:%.*]] = add i64 [[TMP1_0]], [[TMP1_1]]
+; CHECK-NEXT:    store i64 [[TMP2_0]], i64* [[C]], align 8
+; CHECK-NEXT:    store i64 [[TMP2_1]], i64* [[C_1]], align 8
+; CHECK-NEXT:    ret void
+;
+  %a.0 = getelementptr i64, i64* %a, i64 0
+  %a.1 = getelementptr i64, i64* %a, i64 1
+  %b.0 = getelementptr i64, i64* %b, i64 0
+  %b.1 = getelementptr i64, i64* %b, i64 1
+  %c.0 = getelementptr i64, i64* %c, i64 0
+  %c.1 = getelementptr i64, i64* %c, i64 1
+  %v0.0 = load i64, i64* %a.0, align 8
+  %v0.1 = load i64, i64* %a.1, align 8
+  %v1.0 = load i64, i64* %b.0, align 8
+  %v1.1 = load i64, i64* %b.1, align 8
+  %tmp0.0 = add i64 %v0.0, %v1.0
+  %tmp0.1 = add i64 %v0.1, %v1.1
+  %tmp1.0 = sub i64 %v0.0, %v1.0
+  %tmp1.1 = sub i64 %v0.1, %v1.1
+  %tmp2.0 = add i64 %tmp0.0, %tmp0.1
+  %tmp2.1 = add i64 %tmp1.0, %tmp1.1
+  store i64 %tmp2.0, i64* %c.0, align 8
+  store i64 %tmp2.1, i64* %c.1, align 8
+  ret void
+}
+
+define <4 x i32> @build_vec_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @build_vec_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+; CHECK-NEXT:    [[TMP3:%.*]] = add <4 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = sub <4 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT:    [[TMP6:%.*]] = add <4 x i32> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP7:%.*]] = sub <4 x i32> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; CHECK-NEXT:    [[TMP9:%.*]] = add <4 x i32> [[TMP8]], [[TMP5]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP9]]
+;
+  %v0.0 = extractelement <4 x i32> %v0, i32 0
+  %v0.1 = extractelement <4 x i32> %v0, i32 1
+  %v0.2 = extractelement <4 x i32> %v0, i32 2
+  %v0.3 = extractelement <4 x i32> %v0, i32 3
+  %v1.0 = extractelement <4 x i32> %v1, i32 0
+  %v1.1 = extractelement <4 x i32> %v1, i32 1
+  %v1.2 = extractelement <4 x i32> %v1, i32 2
+  %v1.3 = extractelement <4 x i32> %v1, i32 3
+  %tmp0.0 = add i32 %v0.0, %v1.0
+  %tmp0.1 = add i32 %v0.1, %v1.1
+  %tmp0.2 = add i32 %v0.2, %v1.2
+  %tmp0.3 = add i32 %v0.3, %v1.3
+  %tmp1.0 = sub i32 %v0.0, %v1.0
+  %tmp1.1 = sub i32 %v0.1, %v1.1
+  %tmp1.2 = sub i32 %v0.2, %v1.2
+  %tmp1.3 = sub i32 %v0.3, %v1.3
+  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
+  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
+  %tmp2.2 = add i32 %tmp0.2, %tmp0.3
+  %tmp2.3 = add i32 %tmp1.2, %tmp1.3
+  %tmp3.0 = insertelement <4 x i32> poison, i32 %tmp2.0, i32 0
+  %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
+  %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 2
+  %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 3
+  ret <4 x i32> %tmp3.3
+}
+
+define <4 x i32> @build_vec_v4i32_reuse_0(<2 x i32> %v0, <2 x i32> %v1) {
+; CHECK-LABEL: @build_vec_v4i32_reuse_0(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i32> [[V1:%.*]], <2 x i32> undef, <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    [[TMP3:%.*]] = add <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = sub <2 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[TMP6:%.*]] = add <2 x i32> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP7:%.*]] = sub <2 x i32> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> [[TMP7]], <2 x i32> <i32 0, i32 3>
+; CHECK-NEXT:    [[TMP9:%.*]] = add <2 x i32> [[TMP8]], [[TMP5]]
+; CHECK-NEXT:    [[TMP3_3:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+; CHECK-NEXT:    ret <4 x i32> [[TMP3_3]]
+;
+  %v0.0 = extractelement <2 x i32> %v0, i32 0
+  %v0.1 = extractelement <2 x i32> %v0, i32 1
+  %v1.0 = extractelement <2 x i32> %v1, i32 0
+  %v1.1 = extractelement <2 x i32> %v1, i32 1
+  %tmp0.0 = add i32 %v0.0, %v1.0
+  %tmp0.1 = add i32 %v0.1, %v1.1
+  %tmp1.0 = sub i32 %v0.0, %v1.0
+  %tmp1.1 = sub i32 %v0.1, %v1.1
+  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
+  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
+  %tmp3.0 = insertelement <4 x i32> poison, i32 %tmp2.0, i32 0
+  %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
+  %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.0, i32 2
+  %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.1, i32 3
+  ret <4 x i32> %tmp3.3
+}
+
+define <4 x i32> @build_vec_v4i32_reuse_1(<2 x i32> %v0, <2 x i32> %v1) {
+; CHECK-LABEL: @build_vec_v4i32_reuse_1(
+; CHECK-NEXT:    [[V0_0:%.*]] = extractelement <2 x i32> [[V0:%.*]], i32 0
+; CHECK-NEXT:    [[V0_1:%.*]] = extractelement <2 x i32> [[V0]], i32 1
+; CHECK-NEXT:    [[V1_0:%.*]] = extractelement <2 x i32> [[V1:%.*]], i32 0
+; CHECK-NEXT:    [[V1_1:%.*]] = extractelement <2 x i32> [[V1]], i32 1
+; CHECK-NEXT:    [[TMP0_0:%.*]] = add i32 [[V0_0]], [[V1_0]]
+; CHECK-NEXT:    [[TMP0_1:%.*]] = add i32 [[V0_1]], [[V1_1]]
+; CHECK-NEXT:    [[TMP0_2:%.*]] = xor i32 [[V0_0]], [[V1_0]]
+; CHECK-NEXT:    [[TMP0_3:%.*]] = xor i32 [[V0_1]], [[V1_1]]
+; CHECK-NEXT:    [[TMP1_0:%.*]] = sub i32 [[TMP0_0]], [[TMP0_1]]
+; CHECK-NEXT:    [[TMP1_1:%.*]] = sub i32 [[TMP0_0]], [[TMP0_1]]
+; CHECK-NEXT:    [[TMP1_2:%.*]] = sub i32 [[TMP0_2]], [[TMP0_3]]
+; CHECK-NEXT:    [[TMP1_3:%.*]] = sub i32 [[TMP0_3]], [[TMP0_2]]
+; CHECK-NEXT:    [[TMP2_0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1_0]], i32 0
+; CHECK-NEXT:    [[TMP2_1:%.*]] = insertelement <4 x i32> [[TMP2_0]], i32 [[TMP1_1]], i32 1
+; CHECK-NEXT:    [[TMP2_2:%.*]] = insertelement <4 x i32> [[TMP2_1]], i32 [[TMP1_2]], i32 2
+; CHECK-NEXT:    [[TMP2_3:%.*]] = insertelement <4 x i32> [[TMP2_2]], i32 [[TMP1_3]], i32 3
+; CHECK-NEXT:    ret <4 x i32> [[TMP2_3]]
+;
+  %v0.0 = extractelement <2 x i32> %v0, i32 0
+  %v0.1 = extractelement <2 x i32> %v0, i32 1
+  %v1.0 = extractelement <2 x i32> %v1, i32 0
+  %v1.1 = extractelement <2 x i32> %v1, i32 1
+  %tmp0.0 = add i32 %v0.0, %v1.0
+  %tmp0.1 = add i32 %v0.1, %v1.1
+  %tmp0.2 = xor i32 %v0.0, %v1.0
+  %tmp0.3 = xor i32 %v0.1, %v1.1
+  %tmp1.0 = sub i32 %tmp0.0, %tmp0.1
+  %tmp1.1 = sub i32 %tmp0.0, %tmp0.1
+  %tmp1.2 = sub i32 %tmp0.2, %tmp0.3
+  %tmp1.3 = sub i32 %tmp0.3, %tmp0.2
+  %tmp2.0 = insertelement <4 x i32> poison, i32 %tmp1.0, i32 0
+  %tmp2.1 = insertelement <4 x i32> %tmp2.0, i32 %tmp1.1, i32 1
+  %tmp2.2 = insertelement <4 x i32> %tmp2.1, i32 %tmp1.2, i32 2
+  %tmp2.3 = insertelement <4 x i32> %tmp2.2, i32 %tmp1.3, i32 3
+  ret <4 x i32> %tmp2.3
+}
+
+define <4 x i32> @build_vec_v4i32_3_binops(<2 x i32> %v0, <2 x i32> %v1) {
+; CHECK-LABEL: @build_vec_v4i32_3_binops(
+; CHECK-NEXT:    [[V0_0:%.*]] = extractelement <2 x i32> [[V0:%.*]], i32 0
+; CHECK-NEXT:    [[V0_1:%.*]] = extractelement <2 x i32> [[V0]], i32 1
+; CHECK-NEXT:    [[V1_0:%.*]] = extractelement <2 x i32> [[V1:%.*]], i32 0
+; CHECK-NEXT:    [[V1_1:%.*]] = extractelement <2 x i32> [[V1]], i32 1
+; CHECK-NEXT:    [[TMP0_0:%.*]] = add i32 [[V0_0]], [[V1_0]]
+; CHECK-NEXT:    [[TMP0_1:%.*]] = add i32 [[V0_1]], [[V1_1]]
+; CHECK-NEXT:    [[TMP1_0:%.*]] = mul i32 [[V0_0]], [[V1_0]]
+; CHECK-NEXT:    [[TMP1_1:%.*]] = mul i32 [[V0_1]], [[V1_1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor <2 x i32> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = xor <2 x i32> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>
+; CHECK-NEXT:    [[TMP2_0:%.*]] = add i32 [[TMP0_0]], [[TMP0_1]]
+; CHECK-NEXT:    [[TMP2_1:%.*]] = add i32 [[TMP1_0]], [[TMP1_1]]
+; CHECK-NEXT:    [[TMP5:%.*]] = add <2 x i32> [[TMP2]], [[TMP4]]
+; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP5]], <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP3_0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2_0]], i32 0
+; CHECK-NEXT:    [[TMP3_1:%.*]] = insertelement <4 x i32> [[TMP3_0]], i32 [[TMP2_1]], i32 1
+; CHECK-NEXT:    [[TMP3_3:%.*]] = shufflevector <4 x i32> [[TMP3_1]], <4 x i32> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; CHECK-NEXT:    ret <4 x i32> [[TMP3_3]]
+;
+  %v0.0 = extractelement <2 x i32> %v0, i32 0
+  %v0.1 = extractelement <2 x i32> %v0, i32 1
+  %v1.0 = extractelement <2 x i32> %v1, i32 0
+  %v1.1 = extractelement <2 x i32> %v1, i32 1
+  %tmp0.0 = add i32 %v0.0, %v1.0
+  %tmp0.1 = add i32 %v0.1, %v1.1
+  %tmp0.2 = xor i32 %v0.0, %v1.0
+  %tmp0.3 = xor i32 %v0.1, %v1.1
+  %tmp1.0 = mul i32 %v0.0, %v1.0
+  %tmp1.1 = mul i32 %v0.1, %v1.1
+  %tmp1.2 = xor i32 %v0.0, %v1.0
+  %tmp1.3 = xor i32 %v0.1, %v1.1
+  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
+  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
+  %tmp2.2 = add i32 %tmp0.2, %tmp0.3
+  %tmp2.3 = add i32 %tmp1.2, %tmp1.3
+  %tmp3.0 = insertelement <4 x i32> poison, i32 %tmp2.0, i32 0
+  %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
+  %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 2
+  %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 3
+  ret <4 x i32> %tmp3.3
+}
+
+define i32 @reduction_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
+; CHECK-LABEL: @reduction_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+; CHECK-NEXT:    [[TMP3:%.*]] = sub <4 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP4:%.*]] = add <4 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT:    [[TMP6:%.*]] = sub <4 x i32> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP7:%.*]] = add <4 x i32> [[V0]], [[V1]]
+; CHECK-NEXT:    [[TMP8:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> [[TMP7]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT:    [[TMP9:%.*]] = add <4 x i32> [[TMP8]], [[TMP5]]
+; CHECK-NEXT:    [[TMP10:%.*]] = lshr <4 x i32> [[TMP9]], <i32 15, i32 15, i32 15, i32 15>
+; CHECK-NEXT:    [[TMP11:%.*]] = and <4 x i32> [[TMP10]], <i32 65537, i32 65537, i32 65537, i32 65537>
+; CHECK-NEXT:    [[TMP12:%.*]] = mul nuw <4 x i32> [[TMP11]], <i32 65535, i32 65535, i32 65535, i32 65535>
+; CHECK-NEXT:    [[TMP13:%.*]] = add <4 x i32> [[TMP12]], [[TMP9]]
+; CHECK-NEXT:    [[TMP14:%.*]] = xor <4 x i32> [[TMP13]], [[TMP12]]
+; CHECK-NEXT:    [[TMP15:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[TMP14]])
+; CHECK-NEXT:    ret i32 [[TMP15]]
+;
+  %v0.0 = extractelement <4 x i32> %v0, i32 0
+  %v0.1 = extractelement <4 x i32> %v0, i32 1
+  %v0.2 = extractelement <4 x i32> %v0, i32 2
+  %v0.3 = extractelement <4 x i32> %v0, i32 3
+  %v1.0 = extractelement <4 x i32> %v1, i32 0
+  %v1.1 = extractelement <4 x i32> %v1, i32 1
+  %v1.2 = extractelement <4 x i32> %v1, i32 2
+  %v1.3 = extractelement <4 x i32> %v1, i32 3
+  %tmp0.0 = add i32 %v0.0, %v1.0
+  %tmp0.1 = add i32 %v0.1, %v1.1
+  %tmp0.2 = add i32 %v0.2, %v1.2
+  %tmp0.3 = add i32 %v0.3, %v1.3
+  %tmp1.0 = sub i32 %v0.0, %v1.0
+  %tmp1.1 = sub i32 %v0.1, %v1.1
+  %tmp1.2 = sub i32 %v0.2, %v1.2
+  %tmp1.3 = sub i32 %v0.3, %v1.3
+  %tmp2.0 = add i32 %tmp0.0, %tmp0.1
+  %tmp2.1 = add i32 %tmp1.0, %tmp1.1
+  %tmp2.2 = add i32 %tmp0.2, %tmp0.3
+  %tmp2.3 = add i32 %tmp1.2, %tmp1.3
+  %tmp3.0 = lshr i32 %tmp2.0, 15
+  %tmp3.1 = lshr i32 %tmp2.1, 15
+  %tmp3.2 = lshr i32 %tmp2.2, 15
+  %tmp3.3 = lshr i32 %tmp2.3, 15
+  %tmp4.0 = and i32 %tmp3.0, 65537
+  %tmp4.1 = and i32 %tmp3.1, 65537
+  %tmp4.2 = and i32 %tmp3.2, 65537
+  %tmp4.3 = and i32 %tmp3.3, 65537
+  %tmp5.0 = mul nuw i32 %tmp4.0, 65535
+  %tmp5.1 = mul nuw i32 %tmp4.1, 65535
+  %tmp5.2 = mul nuw i32 %tmp4.2, 65535
+  %tmp5.3 = mul nuw i32 %tmp4.3, 65535
+  %tmp6.0 = add i32 %tmp5.0, %tmp2.0
+  %tmp6.1 = add i32 %tmp5.1, %tmp2.1
+  %tmp6.2 = add i32 %tmp5.2, %tmp2.2
+  %tmp6.3 = add i32 %tmp5.3, %tmp2.3
+  %tmp7.0 = xor i32 %tmp6.0, %tmp5.0
+  %tmp7.1 = xor i32 %tmp6.1, %tmp5.1
+  %tmp7.2 = xor i32 %tmp6.2, %tmp5.2
+  %tmp7.3 = xor i32 %tmp6.3, %tmp5.3
+  %reduce.0 = add i32 %tmp7.1, %tmp7.0
+  %reduce.1 = add i32 %reduce.0, %tmp7.2
+  %reduce.2 = add i32 %reduce.1, %tmp7.3
+  ret i32 %reduce.2
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll
new file mode 100644
index 0000000000000..b9dabe966bcdc
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat-inseltpoison.ll
@@ -0,0 +1,336 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -slp-vectorizer -instcombine %s | FileCheck -check-prefixes=GCN,GFX7 %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -slp-vectorizer -instcombine %s | FileCheck -check-prefixes=GCN,GFX8 %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -slp-vectorizer -instcombine %s | FileCheck -check-prefixes=GCN,GFX8 %s
+
+define <2 x i16> @uadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) {
+; GFX7-LABEL: @uadd_sat_v2i16(
+; GFX7-NEXT:  bb:
+; GFX7-NEXT:    [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
+; GFX7-NEXT:    [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
+; GFX7-NEXT:    [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
+; GFX7-NEXT:    [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
+; GFX7-NEXT:    [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
+; GFX7-NEXT:    [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
+; GFX7-NEXT:    [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
+; GFX7-NEXT:    [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
+; GFX7-NEXT:    ret <2 x i16> [[INS_1]]
+;
+; GFX8-LABEL: @uadd_sat_v2i16(
+; GFX8-NEXT:  bb:
+; GFX8-NEXT:    [[TMP0:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
+; GFX8-NEXT:    ret <2 x i16> [[TMP0]]
+;
+bb:
+  %arg0.0 = extractelement <2 x i16> %arg0, i64 0
+  %arg0.1 = extractelement <2 x i16> %arg0, i64 1
+  %arg1.0 = extractelement <2 x i16> %arg1, i64 0
+  %arg1.1 = extractelement <2 x i16> %arg1, i64 1
+  %add.0 = call i16 @llvm.uadd.sat.i16(i16 %arg0.0, i16 %arg1.0)
+  %add.1 = call i16 @llvm.uadd.sat.i16(i16 %arg0.1, i16 %arg1.1)
+  %ins.0 = insertelement <2 x i16> poison, i16 %add.0, i64 0
+  %ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1
+  ret <2 x i16> %ins.1
+}
+
+define <2 x i16> @usub_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) {
+; GFX7-LABEL: @usub_sat_v2i16(
+; GFX7-NEXT:  bb:
+; GFX7-NEXT:    [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
+; GFX7-NEXT:    [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
+; GFX7-NEXT:    [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
+; GFX7-NEXT:    [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
+; GFX7-NEXT:    [[ADD_0:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
+; GFX7-NEXT:    [[ADD_1:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
+; GFX7-NEXT:    [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
+; GFX7-NEXT:    [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
+; GFX7-NEXT:    ret <2 x i16> [[INS_1]]
+;
+; GFX8-LABEL: @usub_sat_v2i16(
+; GFX8-NEXT:  bb:
+; GFX8-NEXT:    [[TMP0:%.*]] = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
+; GFX8-NEXT:    ret <2 x i16> [[TMP0]]
+;
+bb:
+  %arg0.0 = extractelement <2 x i16> %arg0, i64 0
+  %arg0.1 = extractelement <2 x i16> %arg0, i64 1
+  %arg1.0 = extractelement <2 x i16> %arg1, i64 0
+  %arg1.1 = extractelement <2 x i16> %arg1, i64 1
+  %add.0 = call i16 @llvm.usub.sat.i16(i16 %arg0.0, i16 %arg1.0)
+  %add.1 = call i16 @llvm.usub.sat.i16(i16 %arg0.1, i16 %arg1.1)
+  %ins.0 = insertelement <2 x i16> poison, i16 %add.0, i64 0
+  %ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1
+  ret <2 x i16> %ins.1
+}
+
+define <2 x i16> @sadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) {
+; GFX7-LABEL: @sadd_sat_v2i16(
+; GFX7-NEXT:  bb:
+; GFX7-NEXT:    [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
+; GFX7-NEXT:    [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
+; GFX7-NEXT:    [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
+; GFX7-NEXT:    [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
+; GFX7-NEXT:    [[ADD_0:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
+; GFX7-NEXT:    [[ADD_1:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
+; GFX7-NEXT:    [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
+; GFX7-NEXT:    [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
+; GFX7-NEXT:    ret <2 x i16> [[INS_1]]
+;
+; GFX8-LABEL: @sadd_sat_v2i16(
+; GFX8-NEXT:  bb:
+; GFX8-NEXT:    [[TMP0:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
+; GFX8-NEXT:    ret <2 x i16> [[TMP0]]
+;
+bb:
+  %arg0.0 = extractelement <2 x i16> %arg0, i64 0
+  %arg0.1 = extractelement <2 x i16> %arg0, i64 1
+  %arg1.0 = extractelement <2 x i16> %arg1, i64 0
+  %arg1.1 = extractelement <2 x i16> %arg1, i64 1
+  %add.0 = call i16 @llvm.sadd.sat.i16(i16 %arg0.0, i16 %arg1.0)
+  %add.1 = call i16 @llvm.sadd.sat.i16(i16 %arg0.1, i16 %arg1.1)
+  %ins.0 = insertelement <2 x i16> poison, i16 %add.0, i64 0
+  %ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1
+  ret <2 x i16> %ins.1
+}
+
+define <2 x i16> @ssub_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) {
+; GFX7-LABEL: @ssub_sat_v2i16(
+; GFX7-NEXT:  bb:
+; GFX7-NEXT:    [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
+; GFX7-NEXT:    [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
+; GFX7-NEXT:    [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
+; GFX7-NEXT:    [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
+; GFX7-NEXT:    [[ADD_0:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
+; GFX7-NEXT:    [[ADD_1:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
+; GFX7-NEXT:    [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
+; GFX7-NEXT:    [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
+; GFX7-NEXT:    ret <2 x i16> [[INS_1]]
+;
+; GFX8-LABEL: @ssub_sat_v2i16(
+; GFX8-NEXT:  bb:
+; GFX8-NEXT:    [[TMP0:%.*]] = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
+; GFX8-NEXT:    ret <2 x i16> [[TMP0]]
+;
+bb:
+  %arg0.0 = extractelement <2 x i16> %arg0, i64 0
+  %arg0.1 = extractelement <2 x i16> %arg0, i64 1
+  %arg1.0 = extractelement <2 x i16> %arg1, i64 0
+  %arg1.1 = extractelement <2 x i16> %arg1, i64 1
+  %add.0 = call i16 @llvm.ssub.sat.i16(i16 %arg0.0, i16 %arg1.0)
+  %add.1 = call i16 @llvm.ssub.sat.i16(i16 %arg0.1, i16 %arg1.1)
+  %ins.0 = insertelement <2 x i16> poison, i16 %add.0, i64 0
+  %ins.1 = insertelement <2 x i16> %ins.0, i16 %add.1, i64 1
+  ret <2 x i16> %ins.1
+}
+
+define <2 x i32> @uadd_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
+; GCN-LABEL: @uadd_sat_v2i32(
+; GCN-NEXT:  bb:
+; GCN-NEXT:    [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
+; GCN-NEXT:    [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
+; GCN-NEXT:    [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
+; GCN-NEXT:    [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
+; GCN-NEXT:    [[ADD_0:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
+; GCN-NEXT:    [[ADD_1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
+; GCN-NEXT:    [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
+; GCN-NEXT:    [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
+; GCN-NEXT:    ret <2 x i32> [[INS_1]]
+;
+bb:
+  %arg0.0 = extractelement <2 x i32> %arg0, i64 0
+  %arg0.1 = extractelement <2 x i32> %arg0, i64 1
+  %arg1.0 = extractelement <2 x i32> %arg1, i64 0
+  %arg1.1 = extractelement <2 x i32> %arg1, i64 1
+  %add.0 = call i32 @llvm.uadd.sat.i32(i32 %arg0.0, i32 %arg1.0)
+  %add.1 = call i32 @llvm.uadd.sat.i32(i32 %arg0.1, i32 %arg1.1)
+  %ins.0 = insertelement <2 x i32> poison, i32 %add.0, i64 0
+  %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
+  ret <2 x i32> %ins.1
+}
+
+define <2 x i32> @usub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
+; GCN-LABEL: @usub_sat_v2i32(
+; GCN-NEXT:  bb:
+; GCN-NEXT:    [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
+; GCN-NEXT:    [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
+; GCN-NEXT:    [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
+; GCN-NEXT:    [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
+; GCN-NEXT:    [[ADD_0:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
+; GCN-NEXT:    [[ADD_1:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
+; GCN-NEXT:    [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
+; GCN-NEXT:    [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
+; GCN-NEXT:    ret <2 x i32> [[INS_1]]
+;
+bb:
+  %arg0.0 = extractelement <2 x i32> %arg0, i64 0
+  %arg0.1 = extractelement <2 x i32> %arg0, i64 1
+  %arg1.0 = extractelement <2 x i32> %arg1, i64 0
+  %arg1.1 = extractelement <2 x i32> %arg1, i64 1
+  %add.0 = call i32 @llvm.usub.sat.i32(i32 %arg0.0, i32 %arg1.0)
+  %add.1 = call i32 @llvm.usub.sat.i32(i32 %arg0.1, i32 %arg1.1)
+  %ins.0 = insertelement <2 x i32> poison, i32 %add.0, i64 0
+  %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
+  ret <2 x i32> %ins.1
+}
+
+define <2 x i32> @sadd_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
+; GCN-LABEL: @sadd_sat_v2i32(
+; GCN-NEXT:  bb:
+; GCN-NEXT:    [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
+; GCN-NEXT:    [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
+; GCN-NEXT:    [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
+; GCN-NEXT:    [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
+; GCN-NEXT:    [[ADD_0:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
+; GCN-NEXT:    [[ADD_1:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
+; GCN-NEXT:    [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
+; GCN-NEXT:    [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
+; GCN-NEXT:    ret <2 x i32> [[INS_1]]
+;
+bb:
+  %arg0.0 = extractelement <2 x i32> %arg0, i64 0
+  %arg0.1 = extractelement <2 x i32> %arg0, i64 1
+  %arg1.0 = extractelement <2 x i32> %arg1, i64 0
+  %arg1.1 = extractelement <2 x i32> %arg1, i64 1
+  %add.0 = call i32 @llvm.sadd.sat.i32(i32 %arg0.0, i32 %arg1.0)
+  %add.1 = call i32 @llvm.sadd.sat.i32(i32 %arg0.1, i32 %arg1.1)
+  %ins.0 = insertelement <2 x i32> poison, i32 %add.0, i64 0
+  %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
+  ret <2 x i32> %ins.1
+}
+
+define <2 x i32> @ssub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
+; GCN-LABEL: @ssub_sat_v2i32(
+; GCN-NEXT:  bb:
+; GCN-NEXT:    [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
+; GCN-NEXT:    [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
+; GCN-NEXT:    [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
+; GCN-NEXT:    [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
+; GCN-NEXT:    [[ADD_0:%.*]] = call i32 @llvm.ssub.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
+; GCN-NEXT:    [[ADD_1:%.*]] = call i32 @llvm.ssub.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
+; GCN-NEXT:    [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
+; GCN-NEXT:    [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
+; GCN-NEXT:    ret <2 x i32> [[INS_1]]
+;
+bb:
+  %arg0.0 = extractelement <2 x i32> %arg0, i64 0
+  %arg0.1 = extractelement <2 x i32> %arg0, i64 1
+  %arg1.0 = extractelement <2 x i32> %arg1, i64 0
+  %arg1.1 = extractelement <2 x i32> %arg1, i64 1
+  %add.0 = call i32 @llvm.ssub.sat.i32(i32 %arg0.0, i32 %arg1.0)
+  %add.1 = call i32 @llvm.ssub.sat.i32(i32 %arg0.1, i32 %arg1.1)
+  %ins.0 = insertelement <2 x i32> poison, i32 %add.0, i64 0
+  %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
+  ret <2 x i32> %ins.1
+}
+
+define <3 x i16> @uadd_sat_v3i16(<3 x i16> %arg0, <3 x i16> %arg1) {
+; GFX7-LABEL: @uadd_sat_v3i16(
+; GFX7-NEXT:  bb:
+; GFX7-NEXT:    [[ARG0_0:%.*]] = extractelement <3 x i16> [[ARG0:%.*]], i64 0
+; GFX7-NEXT:    [[ARG0_1:%.*]] = extractelement <3 x i16> [[ARG0]], i64 1
+; GFX7-NEXT:    [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0]], i64 2
+; GFX7-NEXT:    [[ARG1_0:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 0
+; GFX7-NEXT:    [[ARG1_1:%.*]] = extractelement <3 x i16> [[ARG1]], i64 1
+; GFX7-NEXT:    [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1]], i64 2
+; GFX7-NEXT:    [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
+; GFX7-NEXT:    [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
+; GFX7-NEXT:    [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
+; GFX7-NEXT:    [[INS_0:%.*]] = insertelement <3 x i16> poison, i16 [[ADD_0]], i64 0
+; GFX7-NEXT:    [[INS_1:%.*]] = insertelement <3 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
+; GFX7-NEXT:    [[INS_2:%.*]] = insertelement <3 x i16> [[INS_1]], i16 [[ADD_2]], i64 2
+; GFX7-NEXT:    ret <3 x i16> [[INS_2]]
+;
+; GFX8-LABEL: @uadd_sat_v3i16(
+; GFX8-NEXT:  bb:
+; GFX8-NEXT:    [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0:%.*]], i64 2
+; GFX8-NEXT:    [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 2
+; GFX8-NEXT:    [[TMP0:%.*]] = shufflevector <3 x i16> [[ARG0]], <3 x i16> undef, <2 x i32> <i32 0, i32 1>
+; GFX8-NEXT:    [[TMP1:%.*]] = shufflevector <3 x i16> [[ARG1]], <3 x i16> undef, <2 x i32> <i32 0, i32 1>
+; GFX8-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+; GFX8-NEXT:    [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
+; GFX8-NEXT:    [[TMP3:%.*]] = extractelement <2 x i16> [[TMP2]], i32 0
+; GFX8-NEXT:    [[INS_0:%.*]] = insertelement <3 x i16> poison, i16 [[TMP3]], i64 0
+; GFX8-NEXT:    [[TMP4:%.*]] = extractelement <2 x i16> [[TMP2]], i32 1
+; GFX8-NEXT:    [[INS_1:%.*]] = insertelement <3 x i16> [[INS_0]], i16 [[TMP4]], i64 1
+; GFX8-NEXT:    [[INS_2:%.*]] = insertelement <3 x i16> [[INS_1]], i16 [[ADD_2]], i64 2
+; GFX8-NEXT:    ret <3 x i16> [[INS_2]]
+;
+bb:
+  %arg0.0 = extractelement <3 x i16> %arg0, i64 0
+  %arg0.1 = extractelement <3 x i16> %arg0, i64 1
+  %arg0.2 = extractelement <3 x i16> %arg0, i64 2
+  %arg1.0 = extractelement <3 x i16> %arg1, i64 0
+  %arg1.1 = extractelement <3 x i16> %arg1, i64 1
+  %arg1.2 = extractelement <3 x i16> %arg1, i64 2
+  %add.0 = call i16 @llvm.uadd.sat.i16(i16 %arg0.0, i16 %arg1.0)
+  %add.1 = call i16 @llvm.uadd.sat.i16(i16 %arg0.1, i16 %arg1.1)
+  %add.2 = call i16 @llvm.uadd.sat.i16(i16 %arg0.2, i16 %arg1.2)
+  %ins.0 = insertelement <3 x i16> poison, i16 %add.0, i64 0
+  %ins.1 = insertelement <3 x i16> %ins.0, i16 %add.1, i64 1
+  %ins.2 = insertelement <3 x i16> %ins.1, i16 %add.2, i64 2
+  ret <3 x i16> %ins.2
+}
+
+define <4 x i16> @uadd_sat_v4i16(<4 x i16> %arg0, <4 x i16> %arg1) {
+; GFX7-LABEL: @uadd_sat_v4i16(
+; GFX7-NEXT:  bb:
+; GFX7-NEXT:    [[ARG0_0:%.*]] = extractelement <4 x i16> [[ARG0:%.*]], i64 0
+; GFX7-NEXT:    [[ARG0_1:%.*]] = extractelement <4 x i16> [[ARG0]], i64 1
+; GFX7-NEXT:    [[ARG0_2:%.*]] = extractelement <4 x i16> [[ARG0]], i64 2
+; GFX7-NEXT:    [[ARG0_3:%.*]] = extractelement <4 x i16> [[ARG0]], i64 3
+; GFX7-NEXT:    [[ARG1_0:%.*]] = extractelement <4 x i16> [[ARG1:%.*]], i64 0
+; GFX7-NEXT:    [[ARG1_1:%.*]] = extractelement <4 x i16> [[ARG1]], i64 1
+; GFX7-NEXT:    [[ARG1_2:%.*]] = extractelement <4 x i16> [[ARG1]], i64 2
+; GFX7-NEXT:    [[ARG1_3:%.*]] = extractelement <4 x i16> [[ARG1]], i64 3
+; GFX7-NEXT:    [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
+; GFX7-NEXT:    [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
+; GFX7-NEXT:    [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
+; GFX7-NEXT:    [[ADD_3:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_3]], i16 [[ARG1_3]])
+; GFX7-NEXT:    [[INS_0:%.*]] = insertelement <4 x i16> poison, i16 [[ADD_0]], i64 0
+; GFX7-NEXT:    [[INS_1:%.*]] = insertelement <4 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
+; GFX7-NEXT:    [[INS_2:%.*]] = insertelement <4 x i16> [[INS_1]], i16 [[ADD_2]], i64 2
+; GFX7-NEXT:    [[INS_3:%.*]] = insertelement <4 x i16> [[INS_2]], i16 [[ADD_3]], i64 3
+; GFX7-NEXT:    ret <4 x i16> [[INS_3]]
+;
+; GFX8-LABEL: @uadd_sat_v4i16(
+; GFX8-NEXT:  bb:
+; GFX8-NEXT:    [[TMP0:%.*]] = shufflevector <4 x i16> [[ARG0:%.*]], <4 x i16> undef, <2 x i32> <i32 0, i32 1>
+; GFX8-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i16> [[ARG1:%.*]], <4 x i16> undef, <2 x i32> <i32 0, i32 1>
+; GFX8-NEXT:    [[TMP2:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP0]], <2 x i16> [[TMP1]])
+; GFX8-NEXT:    [[TMP3:%.*]] = shufflevector <4 x i16> [[ARG0]], <4 x i16> undef, <2 x i32> <i32 2, i32 3>
+; GFX8-NEXT:    [[TMP4:%.*]] = shufflevector <4 x i16> [[ARG1]], <4 x i16> undef, <2 x i32> <i32 2, i32 3>
+; GFX8-NEXT:    [[TMP5:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[TMP3]], <2 x i16> [[TMP4]])
+; GFX8-NEXT:    [[INS_3:%.*]] = shufflevector <2 x i16> [[TMP2]], <2 x i16> [[TMP5]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; GFX8-NEXT:    ret <4 x i16> [[INS_3]]
+;
+bb:
+  %arg0.0 = extractelement <4 x i16> %arg0, i64 0
+  %arg0.1 = extractelement <4 x i16> %arg0, i64 1
+  %arg0.2 = extractelement <4 x i16> %arg0, i64 2
+  %arg0.3 = extractelement <4 x i16> %arg0, i64 3
+  %arg1.0 = extractelement <4 x i16> %arg1, i64 0
+  %arg1.1 = extractelement <4 x i16> %arg1, i64 1
+  %arg1.2 = extractelement <4 x i16> %arg1, i64 2
+  %arg1.3 = extractelement <4 x i16> %arg1, i64 3
+  %add.0 = call i16 @llvm.uadd.sat.i16(i16 %arg0.0, i16 %arg1.0)
+  %add.1 = call i16 @llvm.uadd.sat.i16(i16 %arg0.1, i16 %arg1.1)
+  %add.2 = call i16 @llvm.uadd.sat.i16(i16 %arg0.2, i16 %arg1.2)
+  %add.3 = call i16 @llvm.uadd.sat.i16(i16 %arg0.3, i16 %arg1.3)
+  %ins.0 = insertelement <4 x i16> poison, i16 %add.0, i64 0
+  %ins.1 = insertelement <4 x i16> %ins.0, i16 %add.1, i64 1
+  %ins.2 = insertelement <4 x i16> %ins.1, i16 %add.2, i64 2
+  %ins.3 = insertelement <4 x i16> %ins.2, i16 %add.3, i64 3
+  ret <4 x i16> %ins.3
+}
+
+declare i16 @llvm.uadd.sat.i16(i16, i16) #0
+declare i16 @llvm.usub.sat.i16(i16, i16) #0
+declare i16 @llvm.sadd.sat.i16(i16, i16) #0
+declare i16 @llvm.ssub.sat.i16(i16, i16) #0
+
+declare i32 @llvm.uadd.sat.i32(i32, i32) #0
+declare i32 @llvm.usub.sat.i32(i32, i32) #0
+declare i32 @llvm.sadd.sat.i32(i32, i32) #0
+declare i32 @llvm.ssub.sat.i32(i32, i32) #0
+
+attributes #0 = { nounwind readnone speculatable willreturn }
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll
new file mode 100644
index 0000000000000..0dacc72541bfa
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/bswap-inseltpoison.ll
@@ -0,0 +1,38 @@
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s
+
+; GCN-LABEL: @bswap_v2i16(
+; GFX7: call i16 @llvm.bswap.i16(
+; GFX7: call i16 @llvm.bswap.i16(
+
+; GFX8: call <2 x i16> @llvm.bswap.v2i16(
+define <2 x i16> @bswap_v2i16(<2 x i16> %arg) {
+bb:
+  %tmp = extractelement <2 x i16> %arg, i64 0
+  %tmp1 = tail call i16 @llvm.bswap.i16(i16 %tmp)
+  %tmp2 = insertelement <2 x i16> poison, i16 %tmp1, i64 0
+  %tmp3 = extractelement <2 x i16> %arg, i64 1
+  %tmp4 = tail call i16 @llvm.bswap.i16(i16 %tmp3)
+  %tmp5 = insertelement <2 x i16> %tmp2, i16 %tmp4, i64 1
+  ret <2 x i16> %tmp5
+}
+
+; GCN-LABEL: @bswap_v2i32(
+; GCN: call i32 @llvm.bswap.i32
+; GCN: call i32 @llvm.bswap.i32
+define <2 x i32> @bswap_v2i32(<2 x i32> %arg) {
+bb:
+  %tmp = extractelement <2 x i32> %arg, i64 0
+  %tmp1 = tail call i32 @llvm.bswap.i32(i32 %tmp)
+  %tmp2 = insertelement <2 x i32> poison, i32 %tmp1, i64 0
+  %tmp3 = extractelement <2 x i32> %arg, i64 1
+  %tmp4 = tail call i32 @llvm.bswap.i32(i32 %tmp3)
+  %tmp5 = insertelement <2 x i32> %tmp2, i32 %tmp4, i64 1
+  ret <2 x i32> %tmp5
+}
+
+declare i16 @llvm.bswap.i16(i16) #0
+declare i32 @llvm.bswap.i32(i32) #0
+
+attributes #0 = { nounwind readnone speculatable willreturn }
diff --git a/llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll
new file mode 100644
index 0000000000000..b2e4449318025
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AMDGPU/round-inseltpoison.ll
@@ -0,0 +1,38 @@
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX7 %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -slp-vectorizer %s | FileCheck -check-prefixes=GCN,GFX8 %s
+
+; GCN-LABEL: @round_v2f16(
+; GFX7: call half @llvm.round.f16(
+; GFX7: call half @llvm.round.f16(
+
+; GFX8: call <2 x half> @llvm.round.v2f16(
+define <2 x half> @round_v2f16(<2 x half> %arg) {
+bb:
+  %tmp = extractelement <2 x half> %arg, i64 0
+  %tmp1 = tail call half @llvm.round.half(half %tmp)
+  %tmp2 = insertelement <2 x half> poison, half %tmp1, i64 0
+  %tmp3 = extractelement <2 x half> %arg, i64 1
+  %tmp4 = tail call half @llvm.round.half(half %tmp3)
+  %tmp5 = insertelement <2 x half> %tmp2, half %tmp4, i64 1
+  ret <2 x half> %tmp5
+}
+
+; GCN-LABEL: @round_v2f32(
+; GCN: call float @llvm.round.f32(
+; GCN: call float @llvm.round.f32(
+define <2 x float> @round_v2f32(<2 x float> %arg) {
+bb:
+  %tmp = extractelement <2 x float> %arg, i64 0
+  %tmp1 = tail call float @llvm.round.f32(float %tmp)
+  %tmp2 = insertelement <2 x float> poison, float %tmp1, i64 0
+  %tmp3 = extractelement <2 x float> %arg, i64 1
+  %tmp4 = tail call float @llvm.round.f32(float %tmp3)
+  %tmp5 = insertelement <2 x float> %tmp2, float %tmp4, i64 1
+  ret <2 x float> %tmp5
+}
+
+declare half @llvm.round.half(half) #0
+declare float @llvm.round.f32(float) #0
+
+attributes #0 = { nounwind readnone speculatable willreturn }
diff --git a/llvm/test/Transforms/SLPVectorizer/ARM/extract-insert-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/ARM/extract-insert-inseltpoison.ll
new file mode 100644
index 0000000000000..9d3102566258c
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/ARM/extract-insert-inseltpoison.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -S -mtriple=thumb7 -mcpu=swift | FileCheck %s
+
+define <4 x i32> @PR13837(<4 x float> %in) {
+; CHECK-LABEL: @PR13837(
+; CHECK-NEXT:    [[TMP1:%.*]] = fptosi <4 x float> [[IN:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[TMP1]], i32 0
+; CHECK-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP1]], i32 2
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
+; CHECK-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x i32> [[V3]]
+;
+  %t0 = extractelement <4 x float> %in, i64 0
+  %t1 = extractelement <4 x float> %in, i64 1
+  %t2 = extractelement <4 x float> %in, i64 2
+  %t3 = extractelement <4 x float> %in, i64 3
+  %c0 = fptosi float %t0 to i32
+  %c1 = fptosi float %t1 to i32
+  %c2 = fptosi float %t2 to i32
+  %c3 = fptosi float %t3 to i32
+  %v0 = insertelement <4 x i32> poison, i32 %c0, i32 0
+  %v1 = insertelement <4 x i32> %v0, i32 %c1, i32 1
+  %v2 = insertelement <4 x i32> %v1, i32 %c2, i32 2
+  %v3 = insertelement <4 x i32> %v2, i32 %c3, i32 3
+  ret <4 x i32> %v3
+}
+
diff --git a/llvm/test/Transforms/SLPVectorizer/NVPTX/non-vectorizable-intrinsic-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/NVPTX/non-vectorizable-intrinsic-inseltpoison.ll
new file mode 100644
index 0000000000000..b55d0662cbd89
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/NVPTX/non-vectorizable-intrinsic-inseltpoison.ll
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -o - -S -slp-threshold=-1000 | FileCheck %s
+
+target datalayout = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"
+target triple = "nvptx--nvidiacl"
+
+; CTLZ cannot be vectorized currently because the second argument is a scalar
+; for both the scalar and vector forms of the intrinsic. In the future it
+; should be possible to vectorize such functions.
+; Test causes an assert if LLVM tries to vectorize CTLZ.
+
+define <2 x i8> @cltz_test(<2 x i8> %x) #0 {
+; CHECK-LABEL: @cltz_test(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = extractelement <2 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[CALL_I:%.*]] = call i8 @llvm.ctlz.i8(i8 [[TMP0]], i1 false)
+; CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <2 x i8> poison, i8 [[CALL_I]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i8> [[X]], i32 1
+; CHECK-NEXT:    [[CALL_I4:%.*]] = call i8 @llvm.ctlz.i8(i8 [[TMP1]], i1 false)
+; CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <2 x i8> [[VECINIT]], i8 [[CALL_I4]], i32 1
+; CHECK-NEXT:    ret <2 x i8> [[VECINIT2]]
+;
+entry:
+  %0 = extractelement <2 x i8> %x, i32 0
+  %call.i = call i8 @llvm.ctlz.i8(i8 %0, i1 false)
+  %vecinit = insertelement <2 x i8> poison, i8 %call.i, i32 0
+  %1 = extractelement <2 x i8> %x, i32 1
+  %call.i4 = call i8 @llvm.ctlz.i8(i8 %1, i1 false)
+  %vecinit2 = insertelement <2 x i8> %vecinit, i8 %call.i4, i32 1
+  ret <2 x i8> %vecinit2
+}
+
+define <2 x i8> @cltz_test2(<2 x i8> %x) #1 {
+; CHECK-LABEL: @cltz_test2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = extractelement <2 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x i8> [[X]], i32 1
+; CHECK-NEXT:    [[CALL_I:%.*]] = call i8 @llvm.ctlz.i8(i8 [[TMP0]], i1 false)
+; CHECK-NEXT:    [[CALL_I4:%.*]] = call i8 @llvm.ctlz.i8(i8 [[TMP1]], i1 false)
+; CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <2 x i8> poison, i8 [[CALL_I]], i32 0
+; CHECK-NEXT:    [[VECINIT2:%.*]] = insertelement <2 x i8> [[VECINIT]], i8 [[CALL_I4]], i32 1
+; CHECK-NEXT:    ret <2 x i8> [[VECINIT2]]
+;
+entry:
+  %0 = extractelement <2 x i8> %x, i32 0
+  %1 = extractelement <2 x i8> %x, i32 1
+  %call.i = call i8 @llvm.ctlz.i8(i8 %0, i1 false)
+  %call.i4 = call i8 @llvm.ctlz.i8(i8 %1, i1 false)
+  %vecinit = insertelement <2 x i8> poison, i8 %call.i, i32 0
+  %vecinit2 = insertelement <2 x i8> %vecinit, i8 %call.i4, i32 1
+  ret <2 x i8> %vecinit2
+}
+
+declare i8 @llvm.ctlz.i8(i8, i1) #3
+
+attributes #0 = { alwaysinline nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR35865-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR35865-inseltpoison.ll
new file mode 100644
index 0000000000000..b6d9c0dbbe263
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR35865-inseltpoison.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer < %s -S -o - -mtriple=x86_64-apple-macosx10.10.0 -mcpu=core2 | FileCheck %s
+
+define void @_Z10fooConvertPDv4_xS0_S0_PKS_() {
+; CHECK-LABEL: @_Z10fooConvertPDv4_xS0_S0_PKS_(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = extractelement <16 x half> undef, i32 4
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <16 x half> undef, i32 5
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x half> undef, half [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <2 x half> [[TMP2]], half [[TMP1]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = fpext <2 x half> [[TMP3]] to <2 x float>
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast <2 x float> [[TMP4]] to <2 x i32>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i32> [[TMP5]], i32 0
+; CHECK-NEXT:    [[VECINS_I_4_I:%.*]] = insertelement <8 x i32> poison, i32 [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i32> [[TMP5]], i32 1
+; CHECK-NEXT:    [[VECINS_I_5_I:%.*]] = insertelement <8 x i32> [[VECINS_I_4_I]], i32 [[TMP7]], i32 5
+; CHECK-NEXT:    ret void
+;
+entry:
+  %0 = extractelement <16 x half> undef, i32 4
+  %conv.i.4.i = fpext half %0 to float
+  %1 = bitcast float %conv.i.4.i to i32
+  %vecins.i.4.i = insertelement <8 x i32> poison, i32 %1, i32 4
+  %2 = extractelement <16 x half> undef, i32 5
+  %conv.i.5.i = fpext half %2 to float
+  %3 = bitcast float %conv.i.5.i to i32
+  %vecins.i.5.i = insertelement <8 x i32> %vecins.i.4.i, i32 %3, i32 5
+  ret void
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
new file mode 100644
index 0000000000000..a3407151a332c
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-calls-inseltpoison.ll
@@ -0,0 +1,65 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s
+
+define <8 x float> @ceil_floor(<8 x float> %a) {
+; CHECK-LABEL: @ceil_floor(
+; CHECK-NEXT:    [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
+; CHECK-NEXT:    [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
+; CHECK-NEXT:    [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
+; CHECK-NEXT:    [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
+; CHECK-NEXT:    [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
+; CHECK-NEXT:    [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
+; CHECK-NEXT:    [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
+; CHECK-NEXT:    [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
+; CHECK-NEXT:    [[AB0:%.*]] = call float @llvm.ceil.f32(float [[A0]])
+; CHECK-NEXT:    [[AB1:%.*]] = call float @llvm.floor.f32(float [[A1]])
+; CHECK-NEXT:    [[AB2:%.*]] = call float @llvm.floor.f32(float [[A2]])
+; CHECK-NEXT:    [[AB3:%.*]] = call float @llvm.ceil.f32(float [[A3]])
+; CHECK-NEXT:    [[AB4:%.*]] = call float @llvm.ceil.f32(float [[A4]])
+; CHECK-NEXT:    [[AB5:%.*]] = call float @llvm.ceil.f32(float [[A5]])
+; CHECK-NEXT:    [[AB6:%.*]] = call float @llvm.floor.f32(float [[A6]])
+; CHECK-NEXT:    [[AB7:%.*]] = call float @llvm.floor.f32(float [[A7]])
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[AB0]], i32 0
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[AB1]], i32 1
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[AB2]], i32 2
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[AB3]], i32 3
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
+; CHECK-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %ab0 = call float @llvm.ceil.f32(float %a0)
+  %ab1 = call float @llvm.floor.f32(float %a1)
+  %ab2 = call float @llvm.floor.f32(float %a2)
+  %ab3 = call float @llvm.ceil.f32(float %a3)
+  %ab4 = call float @llvm.ceil.f32(float %a4)
+  %ab5 = call float @llvm.ceil.f32(float %a5)
+  %ab6 = call float @llvm.floor.f32(float %a6)
+  %ab7 = call float @llvm.floor.f32(float %a7)
+  %r0 = insertelement <8 x float> poison, float %ab0, i32 0
+  %r1 = insertelement <8 x float>   %r0, float %ab1, i32 1
+  %r2 = insertelement <8 x float>   %r1, float %ab2, i32 2
+  %r3 = insertelement <8 x float>   %r2, float %ab3, i32 3
+  %r4 = insertelement <8 x float>   %r3, float %ab4, i32 4
+  %r5 = insertelement <8 x float>   %r4, float %ab5, i32 5
+  %r6 = insertelement <8 x float>   %r5, float %ab6, i32 6
+  %r7 = insertelement <8 x float>   %r6, float %ab7, i32 7
+  ret <8 x float> %r7
+}
+
+declare float @llvm.ceil.f32(float)
+declare float @llvm.floor.f32(float)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
new file mode 100644
index 0000000000000..6654dbc47bd57
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-cast-inseltpoison.ll
@@ -0,0 +1,466 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
+
+define <8 x float> @sitofp_uitofp(<8 x i32> %a) {
+; SSE-LABEL: @sitofp_uitofp(
+; SSE-NEXT:    [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
+; SSE-NEXT:    [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
+; SSE-NEXT:    [[A2:%.*]] = extractelement <8 x i32> [[A]], i32 2
+; SSE-NEXT:    [[A3:%.*]] = extractelement <8 x i32> [[A]], i32 3
+; SSE-NEXT:    [[A4:%.*]] = extractelement <8 x i32> [[A]], i32 4
+; SSE-NEXT:    [[A5:%.*]] = extractelement <8 x i32> [[A]], i32 5
+; SSE-NEXT:    [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
+; SSE-NEXT:    [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
+; SSE-NEXT:    [[AB0:%.*]] = sitofp i32 [[A0]] to float
+; SSE-NEXT:    [[AB1:%.*]] = sitofp i32 [[A1]] to float
+; SSE-NEXT:    [[AB2:%.*]] = sitofp i32 [[A2]] to float
+; SSE-NEXT:    [[AB3:%.*]] = sitofp i32 [[A3]] to float
+; SSE-NEXT:    [[AB4:%.*]] = uitofp i32 [[A4]] to float
+; SSE-NEXT:    [[AB5:%.*]] = uitofp i32 [[A5]] to float
+; SSE-NEXT:    [[AB6:%.*]] = uitofp i32 [[A6]] to float
+; SSE-NEXT:    [[AB7:%.*]] = uitofp i32 [[A7]] to float
+; SSE-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[AB0]], i32 0
+; SSE-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[AB1]], i32 1
+; SSE-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[AB2]], i32 2
+; SSE-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[AB3]], i32 3
+; SSE-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
+; SSE-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
+; SSE-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
+; SSE-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
+; SSE-NEXT:    ret <8 x float> [[R7]]
+;
+; SLM-LABEL: @sitofp_uitofp(
+; SLM-NEXT:    [[TMP1:%.*]] = sitofp <8 x i32> [[A:%.*]] to <8 x float>
+; SLM-NEXT:    [[TMP2:%.*]] = uitofp <8 x i32> [[A]] to <8 x float>
+; SLM-NEXT:    [[R7:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; SLM-NEXT:    ret <8 x float> [[R7]]
+;
+; AVX-LABEL: @sitofp_uitofp(
+; AVX-NEXT:    [[TMP1:%.*]] = sitofp <8 x i32> [[A:%.*]] to <8 x float>
+; AVX-NEXT:    [[TMP2:%.*]] = uitofp <8 x i32> [[A]] to <8 x float>
+; AVX-NEXT:    [[R7:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; AVX-NEXT:    ret <8 x float> [[R7]]
+;
+; AVX512-LABEL: @sitofp_uitofp(
+; AVX512-NEXT:    [[TMP1:%.*]] = sitofp <8 x i32> [[A:%.*]] to <8 x float>
+; AVX512-NEXT:    [[TMP2:%.*]] = uitofp <8 x i32> [[A]] to <8 x float>
+; AVX512-NEXT:    [[R7:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; AVX512-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %ab0 = sitofp i32 %a0 to float
+  %ab1 = sitofp i32 %a1 to float
+  %ab2 = sitofp i32 %a2 to float
+  %ab3 = sitofp i32 %a3 to float
+  %ab4 = uitofp i32 %a4 to float
+  %ab5 = uitofp i32 %a5 to float
+  %ab6 = uitofp i32 %a6 to float
+  %ab7 = uitofp i32 %a7 to float
+  %r0 = insertelement <8 x float> poison, float %ab0, i32 0
+  %r1 = insertelement <8 x float>   %r0, float %ab1, i32 1
+  %r2 = insertelement <8 x float>   %r1, float %ab2, i32 2
+  %r3 = insertelement <8 x float>   %r2, float %ab3, i32 3
+  %r4 = insertelement <8 x float>   %r3, float %ab4, i32 4
+  %r5 = insertelement <8 x float>   %r4, float %ab5, i32 5
+  %r6 = insertelement <8 x float>   %r5, float %ab6, i32 6
+  %r7 = insertelement <8 x float>   %r6, float %ab7, i32 7
+  ret <8 x float> %r7
+}
+
+define <8 x i32> @fptosi_fptoui(<8 x float> %a) {
+; SSE-LABEL: @fptosi_fptoui(
+; SSE-NEXT:    [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
+; SSE-NEXT:    [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
+; SSE-NEXT:    [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
+; SSE-NEXT:    [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
+; SSE-NEXT:    [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
+; SSE-NEXT:    [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
+; SSE-NEXT:    [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
+; SSE-NEXT:    [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
+; SSE-NEXT:    [[AB0:%.*]] = fptosi float [[A0]] to i32
+; SSE-NEXT:    [[AB1:%.*]] = fptosi float [[A1]] to i32
+; SSE-NEXT:    [[AB2:%.*]] = fptosi float [[A2]] to i32
+; SSE-NEXT:    [[AB3:%.*]] = fptosi float [[A3]] to i32
+; SSE-NEXT:    [[AB4:%.*]] = fptoui float [[A4]] to i32
+; SSE-NEXT:    [[AB5:%.*]] = fptoui float [[A5]] to i32
+; SSE-NEXT:    [[AB6:%.*]] = fptoui float [[A6]] to i32
+; SSE-NEXT:    [[AB7:%.*]] = fptoui float [[A7]] to i32
+; SSE-NEXT:    [[R0:%.*]] = insertelement <8 x i32> poison, i32 [[AB0]], i32 0
+; SSE-NEXT:    [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
+; SSE-NEXT:    [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
+; SSE-NEXT:    [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
+; SSE-NEXT:    [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB4]], i32 4
+; SSE-NEXT:    [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
+; SSE-NEXT:    [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
+; SSE-NEXT:    [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
+; SSE-NEXT:    ret <8 x i32> [[R7]]
+;
+; SLM-LABEL: @fptosi_fptoui(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
+; SLM-NEXT:    [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
+; SLM-NEXT:    [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
+; SLM-NEXT:    [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
+; SLM-NEXT:    [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
+; SLM-NEXT:    [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
+; SLM-NEXT:    [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
+; SLM-NEXT:    [[AB0:%.*]] = fptosi float [[A0]] to i32
+; SLM-NEXT:    [[AB1:%.*]] = fptosi float [[A1]] to i32
+; SLM-NEXT:    [[AB2:%.*]] = fptosi float [[A2]] to i32
+; SLM-NEXT:    [[AB3:%.*]] = fptosi float [[A3]] to i32
+; SLM-NEXT:    [[AB4:%.*]] = fptoui float [[A4]] to i32
+; SLM-NEXT:    [[AB5:%.*]] = fptoui float [[A5]] to i32
+; SLM-NEXT:    [[AB6:%.*]] = fptoui float [[A6]] to i32
+; SLM-NEXT:    [[AB7:%.*]] = fptoui float [[A7]] to i32
+; SLM-NEXT:    [[R0:%.*]] = insertelement <8 x i32> poison, i32 [[AB0]], i32 0
+; SLM-NEXT:    [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
+; SLM-NEXT:    [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
+; SLM-NEXT:    [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
+; SLM-NEXT:    [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB4]], i32 4
+; SLM-NEXT:    [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
+; SLM-NEXT:    [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
+; SLM-NEXT:    [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
+; SLM-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX-LABEL: @fptosi_fptoui(
+; AVX-NEXT:    [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
+; AVX-NEXT:    [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
+; AVX-NEXT:    [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
+; AVX-NEXT:    [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
+; AVX-NEXT:    [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
+; AVX-NEXT:    [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
+; AVX-NEXT:    [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
+; AVX-NEXT:    [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
+; AVX-NEXT:    [[AB0:%.*]] = fptosi float [[A0]] to i32
+; AVX-NEXT:    [[AB1:%.*]] = fptosi float [[A1]] to i32
+; AVX-NEXT:    [[AB2:%.*]] = fptosi float [[A2]] to i32
+; AVX-NEXT:    [[AB3:%.*]] = fptosi float [[A3]] to i32
+; AVX-NEXT:    [[AB4:%.*]] = fptoui float [[A4]] to i32
+; AVX-NEXT:    [[AB5:%.*]] = fptoui float [[A5]] to i32
+; AVX-NEXT:    [[AB6:%.*]] = fptoui float [[A6]] to i32
+; AVX-NEXT:    [[AB7:%.*]] = fptoui float [[A7]] to i32
+; AVX-NEXT:    [[R0:%.*]] = insertelement <8 x i32> poison, i32 [[AB0]], i32 0
+; AVX-NEXT:    [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
+; AVX-NEXT:    [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
+; AVX-NEXT:    [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
+; AVX-NEXT:    [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB4]], i32 4
+; AVX-NEXT:    [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
+; AVX-NEXT:    [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
+; AVX-NEXT:    [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
+; AVX-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX512-LABEL: @fptosi_fptoui(
+; AVX512-NEXT:    [[TMP1:%.*]] = fptosi <8 x float> [[A:%.*]] to <8 x i32>
+; AVX512-NEXT:    [[TMP2:%.*]] = fptoui <8 x float> [[A]] to <8 x i32>
+; AVX512-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; AVX512-NEXT:    ret <8 x i32> [[R7]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %ab0 = fptosi float %a0 to i32
+  %ab1 = fptosi float %a1 to i32
+  %ab2 = fptosi float %a2 to i32
+  %ab3 = fptosi float %a3 to i32
+  %ab4 = fptoui float %a4 to i32
+  %ab5 = fptoui float %a5 to i32
+  %ab6 = fptoui float %a6 to i32
+  %ab7 = fptoui float %a7 to i32
+  %r0 = insertelement <8 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <8 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <8 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <8 x i32>   %r2, i32 %ab3, i32 3
+  %r4 = insertelement <8 x i32>   %r3, i32 %ab4, i32 4
+  %r5 = insertelement <8 x i32>   %r4, i32 %ab5, i32 5
+  %r6 = insertelement <8 x i32>   %r5, i32 %ab6, i32 6
+  %r7 = insertelement <8 x i32>   %r6, i32 %ab7, i32 7
+  ret <8 x i32> %r7
+}
+
+define <8 x float> @fneg_fabs(<8 x float> %a) {
+; CHECK-LABEL: @fneg_fabs(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x float> [[A:%.*]] to <8 x i32>
+; CHECK-NEXT:    [[TMP2:%.*]] = xor <8 x i32> [[TMP1]], <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP3:%.*]] = and <8 x i32> [[TMP1]], <i32 poison, i32 poison, i32 poison, i32 poison, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast <8 x i32> [[TMP4]] to <8 x float>
+; CHECK-NEXT:    ret <8 x float> [[TMP5]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %aa0 = bitcast float %a0 to i32
+  %aa1 = bitcast float %a1 to i32
+  %aa2 = bitcast float %a2 to i32
+  %aa3 = bitcast float %a3 to i32
+  %aa4 = bitcast float %a4 to i32
+  %aa5 = bitcast float %a5 to i32
+  %aa6 = bitcast float %a6 to i32
+  %aa7 = bitcast float %a7 to i32
+  %ab0 = xor i32 %aa0, -2147483648
+  %ab1 = xor i32 %aa1, -2147483648
+  %ab2 = xor i32 %aa2, -2147483648
+  %ab3 = xor i32 %aa3, -2147483648
+  %ab4 = and i32 %aa4, 2147483647
+  %ab5 = and i32 %aa5, 2147483647
+  %ab6 = and i32 %aa6, 2147483647
+  %ab7 = and i32 %aa7, 2147483647
+  %ac0 = bitcast i32 %ab0 to float
+  %ac1 = bitcast i32 %ab1 to float
+  %ac2 = bitcast i32 %ab2 to float
+  %ac3 = bitcast i32 %ab3 to float
+  %ac4 = bitcast i32 %ab4 to float
+  %ac5 = bitcast i32 %ab5 to float
+  %ac6 = bitcast i32 %ab6 to float
+  %ac7 = bitcast i32 %ab7 to float
+  %r0 = insertelement <8 x float> poison, float %ac0, i32 0
+  %r1 = insertelement <8 x float>   %r0, float %ac1, i32 1
+  %r2 = insertelement <8 x float>   %r1, float %ac2, i32 2
+  %r3 = insertelement <8 x float>   %r2, float %ac3, i32 3
+  %r4 = insertelement <8 x float>   %r3, float %ac4, i32 4
+  %r5 = insertelement <8 x float>   %r4, float %ac5, i32 5
+  %r6 = insertelement <8 x float>   %r5, float %ac6, i32 6
+  %r7 = insertelement <8 x float>   %r6, float %ac7, i32 7
+  ret <8 x float> %r7
+}
+
+define <8 x i32> @sext_zext(<8 x i16> %a) {
+; CHECK-LABEL: @sext_zext(
+; CHECK-NEXT:    [[TMP1:%.*]] = sext <8 x i16> [[A:%.*]] to <8 x i32>
+; CHECK-NEXT:    [[TMP2:%.*]] = zext <8 x i16> [[A]] to <8 x i32>
+; CHECK-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT:    ret <8 x i32> [[R7]]
+;
+  %a0 = extractelement <8 x i16> %a, i32 0
+  %a1 = extractelement <8 x i16> %a, i32 1
+  %a2 = extractelement <8 x i16> %a, i32 2
+  %a3 = extractelement <8 x i16> %a, i32 3
+  %a4 = extractelement <8 x i16> %a, i32 4
+  %a5 = extractelement <8 x i16> %a, i32 5
+  %a6 = extractelement <8 x i16> %a, i32 6
+  %a7 = extractelement <8 x i16> %a, i32 7
+  %ab0 = sext i16 %a0 to i32
+  %ab1 = sext i16 %a1 to i32
+  %ab2 = sext i16 %a2 to i32
+  %ab3 = sext i16 %a3 to i32
+  %ab4 = zext i16 %a4 to i32
+  %ab5 = zext i16 %a5 to i32
+  %ab6 = zext i16 %a6 to i32
+  %ab7 = zext i16 %a7 to i32
+  %r0 = insertelement <8 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <8 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <8 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <8 x i32>   %r2, i32 %ab3, i32 3
+  %r4 = insertelement <8 x i32>   %r3, i32 %ab4, i32 4
+  %r5 = insertelement <8 x i32>   %r4, i32 %ab5, i32 5
+  %r6 = insertelement <8 x i32>   %r5, i32 %ab6, i32 6
+  %r7 = insertelement <8 x i32>   %r6, i32 %ab7, i32 7
+  ret <8 x i32> %r7
+}
+
+define <8 x float> @sitofp_4i32_8i16(<4 x i32> %a, <8 x i16> %b) {
+; CHECK-LABEL: @sitofp_4i32_8i16(
+; CHECK-NEXT:    [[B0:%.*]] = extractelement <8 x i16> [[B:%.*]], i32 0
+; CHECK-NEXT:    [[B1:%.*]] = extractelement <8 x i16> [[B]], i32 1
+; CHECK-NEXT:    [[B2:%.*]] = extractelement <8 x i16> [[B]], i32 2
+; CHECK-NEXT:    [[B3:%.*]] = extractelement <8 x i16> [[B]], i32 3
+; CHECK-NEXT:    [[TMP1:%.*]] = sitofp <4 x i32> [[A:%.*]] to <4 x float>
+; CHECK-NEXT:    [[AB4:%.*]] = sitofp i16 [[B0]] to float
+; CHECK-NEXT:    [[AB5:%.*]] = sitofp i16 [[B1]] to float
+; CHECK-NEXT:    [[AB6:%.*]] = sitofp i16 [[B2]] to float
+; CHECK-NEXT:    [[AB7:%.*]] = sitofp i16 [[B3]] to float
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
+; CHECK-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %b0 = extractelement <8 x i16> %b, i32 0
+  %b1 = extractelement <8 x i16> %b, i32 1
+  %b2 = extractelement <8 x i16> %b, i32 2
+  %b3 = extractelement <8 x i16> %b, i32 3
+  %ab0 = sitofp i32 %a0 to float
+  %ab1 = sitofp i32 %a1 to float
+  %ab2 = sitofp i32 %a2 to float
+  %ab3 = sitofp i32 %a3 to float
+  %ab4 = sitofp i16 %b0 to float
+  %ab5 = sitofp i16 %b1 to float
+  %ab6 = sitofp i16 %b2 to float
+  %ab7 = sitofp i16 %b3 to float
+  %r0 = insertelement <8 x float> poison, float %ab0, i32 0
+  %r1 = insertelement <8 x float>   %r0, float %ab1, i32 1
+  %r2 = insertelement <8 x float>   %r1, float %ab2, i32 2
+  %r3 = insertelement <8 x float>   %r2, float %ab3, i32 3
+  %r4 = insertelement <8 x float>   %r3, float %ab4, i32 4
+  %r5 = insertelement <8 x float>   %r4, float %ab5, i32 5
+  %r6 = insertelement <8 x float>   %r5, float %ab6, i32 6
+  %r7 = insertelement <8 x float>   %r6, float %ab7, i32 7
+  ret <8 x float> %r7
+}
+
+; Inspired by PR38154
+define <8 x float> @sitofp_uitofp_4i32_8i16_16i8(<4 x i32> %a, <8 x i16> %b, <16 x i8> %c) {
+; SSE-LABEL: @sitofp_uitofp_4i32_8i16_16i8(
+; SSE-NEXT:    [[A0:%.*]] = extractelement <4 x i32> [[A:%.*]], i32 0
+; SSE-NEXT:    [[A1:%.*]] = extractelement <4 x i32> [[A]], i32 1
+; SSE-NEXT:    [[A2:%.*]] = extractelement <4 x i32> [[A]], i32 2
+; SSE-NEXT:    [[A3:%.*]] = extractelement <4 x i32> [[A]], i32 3
+; SSE-NEXT:    [[B0:%.*]] = extractelement <8 x i16> [[B:%.*]], i32 0
+; SSE-NEXT:    [[B1:%.*]] = extractelement <8 x i16> [[B]], i32 1
+; SSE-NEXT:    [[C0:%.*]] = extractelement <16 x i8> [[C:%.*]], i32 0
+; SSE-NEXT:    [[C1:%.*]] = extractelement <16 x i8> [[C]], i32 1
+; SSE-NEXT:    [[AB0:%.*]] = sitofp i32 [[A0]] to float
+; SSE-NEXT:    [[AB1:%.*]] = sitofp i32 [[A1]] to float
+; SSE-NEXT:    [[AB2:%.*]] = uitofp i32 [[A2]] to float
+; SSE-NEXT:    [[AB3:%.*]] = uitofp i32 [[A3]] to float
+; SSE-NEXT:    [[AB4:%.*]] = sitofp i16 [[B0]] to float
+; SSE-NEXT:    [[AB5:%.*]] = uitofp i16 [[B1]] to float
+; SSE-NEXT:    [[AB6:%.*]] = sitofp i8 [[C0]] to float
+; SSE-NEXT:    [[AB7:%.*]] = uitofp i8 [[C1]] to float
+; SSE-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[AB0]], i32 0
+; SSE-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[AB1]], i32 1
+; SSE-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[AB2]], i32 2
+; SSE-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[AB3]], i32 3
+; SSE-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
+; SSE-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
+; SSE-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
+; SSE-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
+; SSE-NEXT:    ret <8 x float> [[R7]]
+;
+; SLM-LABEL: @sitofp_uitofp_4i32_8i16_16i8(
+; SLM-NEXT:    [[B0:%.*]] = extractelement <8 x i16> [[B:%.*]], i32 0
+; SLM-NEXT:    [[B1:%.*]] = extractelement <8 x i16> [[B]], i32 1
+; SLM-NEXT:    [[C0:%.*]] = extractelement <16 x i8> [[C:%.*]], i32 0
+; SLM-NEXT:    [[C1:%.*]] = extractelement <16 x i8> [[C]], i32 1
+; SLM-NEXT:    [[TMP1:%.*]] = sitofp <4 x i32> [[A:%.*]] to <4 x float>
+; SLM-NEXT:    [[TMP2:%.*]] = uitofp <4 x i32> [[A]] to <4 x float>
+; SLM-NEXT:    [[AB4:%.*]] = sitofp i16 [[B0]] to float
+; SLM-NEXT:    [[AB5:%.*]] = uitofp i16 [[B1]] to float
+; SLM-NEXT:    [[AB6:%.*]] = sitofp i8 [[C0]] to float
+; SLM-NEXT:    [[AB7:%.*]] = uitofp i8 [[C1]] to float
+; SLM-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; SLM-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i32 0
+; SLM-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; SLM-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[TMP4]], i32 1
+; SLM-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
+; SLM-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[TMP5]], i32 2
+; SLM-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
+; SLM-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[TMP6]], i32 3
+; SLM-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
+; SLM-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
+; SLM-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
+; SLM-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
+; SLM-NEXT:    ret <8 x float> [[R7]]
+;
+; AVX-LABEL: @sitofp_uitofp_4i32_8i16_16i8(
+; AVX-NEXT:    [[A0:%.*]] = extractelement <4 x i32> [[A:%.*]], i32 0
+; AVX-NEXT:    [[A1:%.*]] = extractelement <4 x i32> [[A]], i32 1
+; AVX-NEXT:    [[A2:%.*]] = extractelement <4 x i32> [[A]], i32 2
+; AVX-NEXT:    [[A3:%.*]] = extractelement <4 x i32> [[A]], i32 3
+; AVX-NEXT:    [[B0:%.*]] = extractelement <8 x i16> [[B:%.*]], i32 0
+; AVX-NEXT:    [[B1:%.*]] = extractelement <8 x i16> [[B]], i32 1
+; AVX-NEXT:    [[C0:%.*]] = extractelement <16 x i8> [[C:%.*]], i32 0
+; AVX-NEXT:    [[C1:%.*]] = extractelement <16 x i8> [[C]], i32 1
+; AVX-NEXT:    [[AB0:%.*]] = sitofp i32 [[A0]] to float
+; AVX-NEXT:    [[AB1:%.*]] = sitofp i32 [[A1]] to float
+; AVX-NEXT:    [[AB2:%.*]] = uitofp i32 [[A2]] to float
+; AVX-NEXT:    [[AB3:%.*]] = uitofp i32 [[A3]] to float
+; AVX-NEXT:    [[AB4:%.*]] = sitofp i16 [[B0]] to float
+; AVX-NEXT:    [[AB5:%.*]] = uitofp i16 [[B1]] to float
+; AVX-NEXT:    [[AB6:%.*]] = sitofp i8 [[C0]] to float
+; AVX-NEXT:    [[AB7:%.*]] = uitofp i8 [[C1]] to float
+; AVX-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[AB0]], i32 0
+; AVX-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[AB1]], i32 1
+; AVX-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[AB2]], i32 2
+; AVX-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[AB3]], i32 3
+; AVX-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
+; AVX-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
+; AVX-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
+; AVX-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
+; AVX-NEXT:    ret <8 x float> [[R7]]
+;
+; AVX512-LABEL: @sitofp_uitofp_4i32_8i16_16i8(
+; AVX512-NEXT:    [[B0:%.*]] = extractelement <8 x i16> [[B:%.*]], i32 0
+; AVX512-NEXT:    [[B1:%.*]] = extractelement <8 x i16> [[B]], i32 1
+; AVX512-NEXT:    [[C0:%.*]] = extractelement <16 x i8> [[C:%.*]], i32 0
+; AVX512-NEXT:    [[C1:%.*]] = extractelement <16 x i8> [[C]], i32 1
+; AVX512-NEXT:    [[TMP1:%.*]] = sitofp <4 x i32> [[A:%.*]] to <4 x float>
+; AVX512-NEXT:    [[TMP2:%.*]] = uitofp <4 x i32> [[A]] to <4 x float>
+; AVX512-NEXT:    [[AB4:%.*]] = sitofp i16 [[B0]] to float
+; AVX512-NEXT:    [[AB5:%.*]] = uitofp i16 [[B1]] to float
+; AVX512-NEXT:    [[AB6:%.*]] = sitofp i8 [[C0]] to float
+; AVX512-NEXT:    [[AB7:%.*]] = uitofp i8 [[C1]] to float
+; AVX512-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; AVX512-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[TMP3]], i32 0
+; AVX512-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; AVX512-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[TMP4]], i32 1
+; AVX512-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
+; AVX512-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[TMP5]], i32 2
+; AVX512-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
+; AVX512-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[TMP6]], i32 3
+; AVX512-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
+; AVX512-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
+; AVX512-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
+; AVX512-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
+; AVX512-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %b0 = extractelement <8 x i16> %b, i32 0
+  %b1 = extractelement <8 x i16> %b, i32 1
+  %c0 = extractelement <16 x i8> %c, i32 0
+  %c1 = extractelement <16 x i8> %c, i32 1
+  %ab0 = sitofp i32 %a0 to float
+  %ab1 = sitofp i32 %a1 to float
+  %ab2 = uitofp i32 %a2 to float
+  %ab3 = uitofp i32 %a3 to float
+  %ab4 = sitofp i16 %b0 to float
+  %ab5 = uitofp i16 %b1 to float
+  %ab6 = sitofp  i8 %c0 to float
+  %ab7 = uitofp  i8 %c1 to float
+  %r0 = insertelement <8 x float> poison, float %ab0, i32 0
+  %r1 = insertelement <8 x float>   %r0, float %ab1, i32 1
+  %r2 = insertelement <8 x float>   %r1, float %ab2, i32 2
+  %r3 = insertelement <8 x float>   %r2, float %ab3, i32 3
+  %r4 = insertelement <8 x float>   %r3, float %ab4, i32 4
+  %r5 = insertelement <8 x float>   %r4, float %ab5, i32 5
+  %r6 = insertelement <8 x float>   %r5, float %ab6, i32 6
+  %r7 = insertelement <8 x float>   %r6, float %ab7, i32 7
+  ret <8 x float> %r7
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
index 34dd1cc8c3237..d2abbeb1a6fa9 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-cast.ll
@@ -197,8 +197,8 @@ define <8 x i32> @fptosi_fptoui(<8 x float> %a) {
 define <8 x float> @fneg_fabs(<8 x float> %a) {
 ; CHECK-LABEL: @fneg_fabs(
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x float> [[A:%.*]] to <8 x i32>
-; CHECK-NEXT:    [[TMP2:%.*]] = xor <8 x i32> [[TMP1]], <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 undef, i32 undef, i32 undef, i32 undef>
-; CHECK-NEXT:    [[TMP3:%.*]] = and <8 x i32> [[TMP1]], <i32 undef, i32 undef, i32 undef, i32 undef, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    [[TMP2:%.*]] = xor <8 x i32> [[TMP1]], <i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT:    [[TMP3:%.*]] = and <8 x i32> [[TMP1]], <i32 poison, i32 poison, i32 poison, i32 poison, i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
 ; CHECK-NEXT:    [[TMP4:%.*]] = shufflevector <8 x i32> [[TMP2]], <8 x i32> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
 ; CHECK-NEXT:    [[TMP5:%.*]] = bitcast <8 x i32> [[TMP4]] to <8 x float>
 ; CHECK-NEXT:    ret <8 x float> [[TMP5]]
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-fp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-fp-inseltpoison.ll
new file mode 100644
index 0000000000000..638b2c3f75fce
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-fp-inseltpoison.ll
@@ -0,0 +1,179 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512
+
+define <8 x float> @fadd_fsub_v8f32(<8 x float> %a, <8 x float> %b) {
+; CHECK-LABEL: @fadd_fsub_v8f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <8 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = fsub <8 x float> [[A]], [[B]]
+; CHECK-NEXT:    [[R7:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 4, i32 13, i32 14, i32 7>
+; CHECK-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %b0 = extractelement <8 x float> %b, i32 0
+  %b1 = extractelement <8 x float> %b, i32 1
+  %b2 = extractelement <8 x float> %b, i32 2
+  %b3 = extractelement <8 x float> %b, i32 3
+  %b4 = extractelement <8 x float> %b, i32 4
+  %b5 = extractelement <8 x float> %b, i32 5
+  %b6 = extractelement <8 x float> %b, i32 6
+  %b7 = extractelement <8 x float> %b, i32 7
+  %ab0 = fadd float %a0, %b0
+  %ab1 = fsub float %a1, %b1
+  %ab2 = fsub float %a2, %b2
+  %ab3 = fadd float %a3, %b3
+  %ab4 = fadd float %a4, %b4
+  %ab5 = fsub float %a5, %b5
+  %ab6 = fsub float %a6, %b6
+  %ab7 = fadd float %a7, %b7
+  %r0 = insertelement <8 x float> poison, float %ab0, i32 0
+  %r1 = insertelement <8 x float>   %r0, float %ab1, i32 1
+  %r2 = insertelement <8 x float>   %r1, float %ab2, i32 2
+  %r3 = insertelement <8 x float>   %r2, float %ab3, i32 3
+  %r4 = insertelement <8 x float>   %r3, float %ab4, i32 4
+  %r5 = insertelement <8 x float>   %r4, float %ab5, i32 5
+  %r6 = insertelement <8 x float>   %r5, float %ab6, i32 6
+  %r7 = insertelement <8 x float>   %r6, float %ab7, i32 7
+  ret <8 x float> %r7
+}
+
+define <8 x float> @fmul_fdiv_v8f32(<8 x float> %a, <8 x float> %b) {
+; SSE-LABEL: @fmul_fdiv_v8f32(
+; SSE-NEXT:    [[TMP1:%.*]] = fmul <8 x float> [[A:%.*]], [[B:%.*]]
+; SSE-NEXT:    [[TMP2:%.*]] = fdiv <8 x float> [[A]], [[B]]
+; SSE-NEXT:    [[R7:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 4, i32 13, i32 14, i32 7>
+; SSE-NEXT:    ret <8 x float> [[R7]]
+;
+; SLM-LABEL: @fmul_fdiv_v8f32(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <8 x float> [[A]], i32 1
+; SLM-NEXT:    [[A2:%.*]] = extractelement <8 x float> [[A]], i32 2
+; SLM-NEXT:    [[A3:%.*]] = extractelement <8 x float> [[A]], i32 3
+; SLM-NEXT:    [[A4:%.*]] = extractelement <8 x float> [[A]], i32 4
+; SLM-NEXT:    [[A5:%.*]] = extractelement <8 x float> [[A]], i32 5
+; SLM-NEXT:    [[A6:%.*]] = extractelement <8 x float> [[A]], i32 6
+; SLM-NEXT:    [[A7:%.*]] = extractelement <8 x float> [[A]], i32 7
+; SLM-NEXT:    [[B0:%.*]] = extractelement <8 x float> [[B:%.*]], i32 0
+; SLM-NEXT:    [[B1:%.*]] = extractelement <8 x float> [[B]], i32 1
+; SLM-NEXT:    [[B2:%.*]] = extractelement <8 x float> [[B]], i32 2
+; SLM-NEXT:    [[B3:%.*]] = extractelement <8 x float> [[B]], i32 3
+; SLM-NEXT:    [[B4:%.*]] = extractelement <8 x float> [[B]], i32 4
+; SLM-NEXT:    [[B5:%.*]] = extractelement <8 x float> [[B]], i32 5
+; SLM-NEXT:    [[B6:%.*]] = extractelement <8 x float> [[B]], i32 6
+; SLM-NEXT:    [[B7:%.*]] = extractelement <8 x float> [[B]], i32 7
+; SLM-NEXT:    [[AB0:%.*]] = fmul float [[A0]], [[B0]]
+; SLM-NEXT:    [[AB1:%.*]] = fdiv float [[A1]], [[B1]]
+; SLM-NEXT:    [[AB2:%.*]] = fdiv float [[A2]], [[B2]]
+; SLM-NEXT:    [[AB3:%.*]] = fmul float [[A3]], [[B3]]
+; SLM-NEXT:    [[AB4:%.*]] = fmul float [[A4]], [[B4]]
+; SLM-NEXT:    [[AB5:%.*]] = fdiv float [[A5]], [[B5]]
+; SLM-NEXT:    [[AB6:%.*]] = fdiv float [[A6]], [[B6]]
+; SLM-NEXT:    [[AB7:%.*]] = fmul float [[A7]], [[B7]]
+; SLM-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[AB0]], i32 0
+; SLM-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[AB1]], i32 1
+; SLM-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[AB2]], i32 2
+; SLM-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[AB3]], i32 3
+; SLM-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[AB4]], i32 4
+; SLM-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[AB5]], i32 5
+; SLM-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[AB6]], i32 6
+; SLM-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[AB7]], i32 7
+; SLM-NEXT:    ret <8 x float> [[R7]]
+;
+; AVX-LABEL: @fmul_fdiv_v8f32(
+; AVX-NEXT:    [[TMP1:%.*]] = fmul <8 x float> [[A:%.*]], [[B:%.*]]
+; AVX-NEXT:    [[TMP2:%.*]] = fdiv <8 x float> [[A]], [[B]]
+; AVX-NEXT:    [[R7:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 4, i32 13, i32 14, i32 7>
+; AVX-NEXT:    ret <8 x float> [[R7]]
+;
+; AVX512-LABEL: @fmul_fdiv_v8f32(
+; AVX512-NEXT:    [[TMP1:%.*]] = fmul <8 x float> [[A:%.*]], [[B:%.*]]
+; AVX512-NEXT:    [[TMP2:%.*]] = fdiv <8 x float> [[A]], [[B]]
+; AVX512-NEXT:    [[R7:%.*]] = shufflevector <8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x i32> <i32 0, i32 9, i32 10, i32 3, i32 4, i32 13, i32 14, i32 7>
+; AVX512-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %b0 = extractelement <8 x float> %b, i32 0
+  %b1 = extractelement <8 x float> %b, i32 1
+  %b2 = extractelement <8 x float> %b, i32 2
+  %b3 = extractelement <8 x float> %b, i32 3
+  %b4 = extractelement <8 x float> %b, i32 4
+  %b5 = extractelement <8 x float> %b, i32 5
+  %b6 = extractelement <8 x float> %b, i32 6
+  %b7 = extractelement <8 x float> %b, i32 7
+  %ab0 = fmul float %a0, %b0
+  %ab1 = fdiv float %a1, %b1
+  %ab2 = fdiv float %a2, %b2
+  %ab3 = fmul float %a3, %b3
+  %ab4 = fmul float %a4, %b4
+  %ab5 = fdiv float %a5, %b5
+  %ab6 = fdiv float %a6, %b6
+  %ab7 = fmul float %a7, %b7
+  %r0 = insertelement <8 x float> poison, float %ab0, i32 0
+  %r1 = insertelement <8 x float>   %r0, float %ab1, i32 1
+  %r2 = insertelement <8 x float>   %r1, float %ab2, i32 2
+  %r3 = insertelement <8 x float>   %r2, float %ab3, i32 3
+  %r4 = insertelement <8 x float>   %r3, float %ab4, i32 4
+  %r5 = insertelement <8 x float>   %r4, float %ab5, i32 5
+  %r6 = insertelement <8 x float>   %r5, float %ab6, i32 6
+  %r7 = insertelement <8 x float>   %r6, float %ab7, i32 7
+  ret <8 x float> %r7
+}
+
+define <4 x float> @fmul_fdiv_v4f32_const(<4 x float> %a) {
+; SSE-LABEL: @fmul_fdiv_v4f32_const(
+; SSE-NEXT:    [[TMP1:%.*]] = fmul <4 x float> [[A:%.*]], <float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00>
+; SSE-NEXT:    ret <4 x float> [[TMP1]]
+;
+; SLM-LABEL: @fmul_fdiv_v4f32_const(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
+; SLM-NEXT:    [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
+; SLM-NEXT:    [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
+; SLM-NEXT:    [[AB0:%.*]] = fmul float [[A0]], 2.000000e+00
+; SLM-NEXT:    [[AB3:%.*]] = fmul float [[A3]], 2.000000e+00
+; SLM-NEXT:    [[R0:%.*]] = insertelement <4 x float> poison, float [[AB0]], i32 0
+; SLM-NEXT:    [[R1:%.*]] = insertelement <4 x float> [[R0]], float [[A1]], i32 1
+; SLM-NEXT:    [[R2:%.*]] = insertelement <4 x float> [[R1]], float [[A2]], i32 2
+; SLM-NEXT:    [[R3:%.*]] = insertelement <4 x float> [[R2]], float [[AB3]], i32 3
+; SLM-NEXT:    ret <4 x float> [[R3]]
+;
+; AVX-LABEL: @fmul_fdiv_v4f32_const(
+; AVX-NEXT:    [[TMP1:%.*]] = fmul <4 x float> [[A:%.*]], <float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00>
+; AVX-NEXT:    ret <4 x float> [[TMP1]]
+;
+; AVX512-LABEL: @fmul_fdiv_v4f32_const(
+; AVX512-NEXT:    [[TMP1:%.*]] = fmul <4 x float> [[A:%.*]], <float 2.000000e+00, float 1.000000e+00, float 1.000000e+00, float 2.000000e+00>
+; AVX512-NEXT:    ret <4 x float> [[TMP1]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %ab0 = fmul float %a0, 2.0
+  %ab1 = fmul float %a1, 1.0
+  %ab2 = fdiv float %a2, 1.0
+  %ab3 = fdiv float %a3, 0.5
+  %r0 = insertelement <4 x float> poison, float %ab0, i32 0
+  %r1 = insertelement <4 x float>   %r0, float %ab1, i32 1
+  %r2 = insertelement <4 x float>   %r1, float %ab2, i32 2
+  %r3 = insertelement <4 x float>   %r2, float %ab3, i32 3
+  ret <4 x float> %r3
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
new file mode 100644
index 0000000000000..702ab0db22191
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/alternate-int-inseltpoison.ll
@@ -0,0 +1,497 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefixes=CHECK,AVX1
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefixes=CHECK,AVX2
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefixes=CHECK,AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefixes=CHECK,AVX512
+
+define <8 x i32> @add_sub_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; CHECK-LABEL: @add_sub_v8i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <8 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sub <8 x i32> [[A]], [[B]]
+; CHECK-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT:    ret <8 x i32> [[R7]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %b0 = extractelement <8 x i32> %b, i32 0
+  %b1 = extractelement <8 x i32> %b, i32 1
+  %b2 = extractelement <8 x i32> %b, i32 2
+  %b3 = extractelement <8 x i32> %b, i32 3
+  %b4 = extractelement <8 x i32> %b, i32 4
+  %b5 = extractelement <8 x i32> %b, i32 5
+  %b6 = extractelement <8 x i32> %b, i32 6
+  %b7 = extractelement <8 x i32> %b, i32 7
+  %ab0 = add i32 %a0, %b0
+  %ab1 = add i32 %a1, %b1
+  %ab2 = add i32 %a2, %b2
+  %ab3 = add i32 %a3, %b3
+  %ab4 = sub i32 %a4, %b4
+  %ab5 = sub i32 %a5, %b5
+  %ab6 = sub i32 %a6, %b6
+  %ab7 = sub i32 %a7, %b7
+  %r0 = insertelement <8 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <8 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <8 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <8 x i32>   %r2, i32 %ab3, i32 3
+  %r4 = insertelement <8 x i32>   %r3, i32 %ab4, i32 4
+  %r5 = insertelement <8 x i32>   %r4, i32 %ab5, i32 5
+  %r6 = insertelement <8 x i32>   %r5, i32 %ab6, i32 6
+  %r7 = insertelement <8 x i32>   %r6, i32 %ab7, i32 7
+  ret <8 x i32> %r7
+}
+
+define <4 x i32> @add_and_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @add_and_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = and <4 x i32> [[A]], [[B]]
+; CHECK-NEXT:    [[R3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; CHECK-NEXT:    ret <4 x i32> [[R3]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %b0 = extractelement <4 x i32> %b, i32 0
+  %b1 = extractelement <4 x i32> %b, i32 1
+  %b2 = extractelement <4 x i32> %b, i32 2
+  %b3 = extractelement <4 x i32> %b, i32 3
+  %ab0 = add i32 %a0, %b0
+  %ab1 = add i32 %a1, %b1
+  %ab2 = and i32 %a2, %b2
+  %ab3 = and i32 %a3, %b3
+  %r0 = insertelement <4 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <4 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <4 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <4 x i32>   %r2, i32 %ab3, i32 3
+  ret <4 x i32> %r3
+}
+
+define <4 x i32> @add_mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @add_mul_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = mul <4 x i32> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add <4 x i32> [[A]], [[B]]
+; CHECK-NEXT:    [[R3:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP2]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
+; CHECK-NEXT:    ret <4 x i32> [[R3]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %b0 = extractelement <4 x i32> %b, i32 0
+  %b1 = extractelement <4 x i32> %b, i32 1
+  %b2 = extractelement <4 x i32> %b, i32 2
+  %b3 = extractelement <4 x i32> %b, i32 3
+  %ab0 = mul i32 %a0, %b0
+  %ab1 = add i32 %a1, %b1
+  %ab2 = add i32 %a2, %b2
+  %ab3 = mul i32 %a3, %b3
+  %r0 = insertelement <4 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <4 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <4 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <4 x i32>   %r2, i32 %ab3, i32 3
+  ret <4 x i32> %r3
+}
+
+define <8 x i32> @ashr_shl_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; SSE-LABEL: @ashr_shl_v8i32(
+; SSE-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], [[B:%.*]]
+; SSE-NEXT:    [[TMP2:%.*]] = shl <8 x i32> [[A]], [[B]]
+; SSE-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; SSE-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX1-LABEL: @ashr_shl_v8i32(
+; AVX1-NEXT:    [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
+; AVX1-NEXT:    [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
+; AVX1-NEXT:    [[A2:%.*]] = extractelement <8 x i32> [[A]], i32 2
+; AVX1-NEXT:    [[A3:%.*]] = extractelement <8 x i32> [[A]], i32 3
+; AVX1-NEXT:    [[B0:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 0
+; AVX1-NEXT:    [[B1:%.*]] = extractelement <8 x i32> [[B]], i32 1
+; AVX1-NEXT:    [[B2:%.*]] = extractelement <8 x i32> [[B]], i32 2
+; AVX1-NEXT:    [[B3:%.*]] = extractelement <8 x i32> [[B]], i32 3
+; AVX1-NEXT:    [[AB0:%.*]] = ashr i32 [[A0]], [[B0]]
+; AVX1-NEXT:    [[AB1:%.*]] = ashr i32 [[A1]], [[B1]]
+; AVX1-NEXT:    [[AB2:%.*]] = ashr i32 [[A2]], [[B2]]
+; AVX1-NEXT:    [[AB3:%.*]] = ashr i32 [[A3]], [[B3]]
+; AVX1-NEXT:    [[TMP1:%.*]] = shl <8 x i32> [[A]], [[B]]
+; AVX1-NEXT:    [[R0:%.*]] = insertelement <8 x i32> poison, i32 [[AB0]], i32 0
+; AVX1-NEXT:    [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
+; AVX1-NEXT:    [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i32 2
+; AVX1-NEXT:    [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i32 3
+; AVX1-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[R3]], <8 x i32> [[TMP1]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; AVX1-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX2-LABEL: @ashr_shl_v8i32(
+; AVX2-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], [[B:%.*]]
+; AVX2-NEXT:    [[TMP2:%.*]] = shl <8 x i32> [[A]], [[B]]
+; AVX2-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; AVX2-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX512-LABEL: @ashr_shl_v8i32(
+; AVX512-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], [[B:%.*]]
+; AVX512-NEXT:    [[TMP2:%.*]] = shl <8 x i32> [[A]], [[B]]
+; AVX512-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; AVX512-NEXT:    ret <8 x i32> [[R7]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %b0 = extractelement <8 x i32> %b, i32 0
+  %b1 = extractelement <8 x i32> %b, i32 1
+  %b2 = extractelement <8 x i32> %b, i32 2
+  %b3 = extractelement <8 x i32> %b, i32 3
+  %b4 = extractelement <8 x i32> %b, i32 4
+  %b5 = extractelement <8 x i32> %b, i32 5
+  %b6 = extractelement <8 x i32> %b, i32 6
+  %b7 = extractelement <8 x i32> %b, i32 7
+  %ab0 = ashr i32 %a0, %b0
+  %ab1 = ashr i32 %a1, %b1
+  %ab2 = ashr i32 %a2, %b2
+  %ab3 = ashr i32 %a3, %b3
+  %ab4 = shl  i32 %a4, %b4
+  %ab5 = shl  i32 %a5, %b5
+  %ab6 = shl  i32 %a6, %b6
+  %ab7 = shl  i32 %a7, %b7
+  %r0 = insertelement <8 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <8 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <8 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <8 x i32>   %r2, i32 %ab3, i32 3
+  %r4 = insertelement <8 x i32>   %r3, i32 %ab4, i32 4
+  %r5 = insertelement <8 x i32>   %r4, i32 %ab5, i32 5
+  %r6 = insertelement <8 x i32>   %r5, i32 %ab6, i32 6
+  %r7 = insertelement <8 x i32>   %r6, i32 %ab7, i32 7
+  ret <8 x i32> %r7
+}
+
+define <8 x i32> @ashr_shl_v8i32_const(<8 x i32> %a) {
+; SSE-LABEL: @ashr_shl_v8i32_const(
+; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; SSE-NEXT:    [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], <i32 2, i32 2, i32 2, i32 2>
+; SSE-NEXT:    [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+; SSE-NEXT:    [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], <i32 3, i32 3, i32 3, i32 3>
+; SSE-NEXT:    [[R7:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; SSE-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX1-LABEL: @ashr_shl_v8i32_const(
+; AVX1-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; AVX1-NEXT:    [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], <i32 2, i32 2, i32 2, i32 2>
+; AVX1-NEXT:    [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
+; AVX1-NEXT:    [[TMP4:%.*]] = shl <4 x i32> [[TMP3]], <i32 3, i32 3, i32 3, i32 3>
+; AVX1-NEXT:    [[R7:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; AVX1-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX2-LABEL: @ashr_shl_v8i32_const(
+; AVX2-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], <i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>
+; AVX2-NEXT:    [[TMP2:%.*]] = shl <8 x i32> [[A]], <i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>
+; AVX2-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; AVX2-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX512-LABEL: @ashr_shl_v8i32_const(
+; AVX512-NEXT:    [[TMP1:%.*]] = ashr <8 x i32> [[A:%.*]], <i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>
+; AVX512-NEXT:    [[TMP2:%.*]] = shl <8 x i32> [[A]], <i32 2, i32 2, i32 2, i32 2, i32 3, i32 3, i32 3, i32 3>
+; AVX512-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> [[TMP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; AVX512-NEXT:    ret <8 x i32> [[R7]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %ab0 = ashr i32 %a0, 2
+  %ab1 = ashr i32 %a1, 2
+  %ab2 = ashr i32 %a2, 2
+  %ab3 = ashr i32 %a3, 2
+  %ab4 = shl  i32 %a4, 3
+  %ab5 = shl  i32 %a5, 3
+  %ab6 = shl  i32 %a6, 3
+  %ab7 = shl  i32 %a7, 3
+  %r0 = insertelement <8 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <8 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <8 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <8 x i32>   %r2, i32 %ab3, i32 3
+  %r4 = insertelement <8 x i32>   %r3, i32 %ab4, i32 4
+  %r5 = insertelement <8 x i32>   %r4, i32 %ab5, i32 5
+  %r6 = insertelement <8 x i32>   %r5, i32 %ab6, i32 6
+  %r7 = insertelement <8 x i32>   %r6, i32 %ab7, i32 7
+  ret <8 x i32> %r7
+}
+
+define <8 x i32> @ashr_lshr_shl_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; SSE-LABEL: @ashr_lshr_shl_v8i32(
+; SSE-NEXT:    [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
+; SSE-NEXT:    [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
+; SSE-NEXT:    [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
+; SSE-NEXT:    [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
+; SSE-NEXT:    [[B0:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 0
+; SSE-NEXT:    [[B1:%.*]] = extractelement <8 x i32> [[B]], i32 1
+; SSE-NEXT:    [[B6:%.*]] = extractelement <8 x i32> [[B]], i32 6
+; SSE-NEXT:    [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
+; SSE-NEXT:    [[AB0:%.*]] = ashr i32 [[A0]], [[B0]]
+; SSE-NEXT:    [[AB1:%.*]] = ashr i32 [[A1]], [[B1]]
+; SSE-NEXT:    [[TMP1:%.*]] = lshr <8 x i32> [[A]], [[B]]
+; SSE-NEXT:    [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
+; SSE-NEXT:    [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
+; SSE-NEXT:    [[R0:%.*]] = insertelement <8 x i32> poison, i32 [[AB0]], i32 0
+; SSE-NEXT:    [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
+; SSE-NEXT:    [[TMP2:%.*]] = extractelement <8 x i32> [[TMP1]], i32 2
+; SSE-NEXT:    [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[TMP2]], i32 2
+; SSE-NEXT:    [[TMP3:%.*]] = extractelement <8 x i32> [[TMP1]], i32 3
+; SSE-NEXT:    [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[TMP3]], i32 3
+; SSE-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP1]], i32 4
+; SSE-NEXT:    [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[TMP4]], i32 4
+; SSE-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP1]], i32 5
+; SSE-NEXT:    [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[TMP5]], i32 5
+; SSE-NEXT:    [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
+; SSE-NEXT:    [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
+; SSE-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX1-LABEL: @ashr_lshr_shl_v8i32(
+; AVX1-NEXT:    [[A0:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 0
+; AVX1-NEXT:    [[A1:%.*]] = extractelement <8 x i32> [[A]], i32 1
+; AVX1-NEXT:    [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
+; AVX1-NEXT:    [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
+; AVX1-NEXT:    [[B0:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 0
+; AVX1-NEXT:    [[B1:%.*]] = extractelement <8 x i32> [[B]], i32 1
+; AVX1-NEXT:    [[B6:%.*]] = extractelement <8 x i32> [[B]], i32 6
+; AVX1-NEXT:    [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
+; AVX1-NEXT:    [[AB0:%.*]] = ashr i32 [[A0]], [[B0]]
+; AVX1-NEXT:    [[AB1:%.*]] = ashr i32 [[A1]], [[B1]]
+; AVX1-NEXT:    [[TMP1:%.*]] = lshr <8 x i32> [[A]], [[B]]
+; AVX1-NEXT:    [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
+; AVX1-NEXT:    [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
+; AVX1-NEXT:    [[R0:%.*]] = insertelement <8 x i32> poison, i32 [[AB0]], i32 0
+; AVX1-NEXT:    [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[AB1]], i32 1
+; AVX1-NEXT:    [[TMP2:%.*]] = extractelement <8 x i32> [[TMP1]], i32 2
+; AVX1-NEXT:    [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[TMP2]], i32 2
+; AVX1-NEXT:    [[TMP3:%.*]] = extractelement <8 x i32> [[TMP1]], i32 3
+; AVX1-NEXT:    [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[TMP3]], i32 3
+; AVX1-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP1]], i32 4
+; AVX1-NEXT:    [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[TMP4]], i32 4
+; AVX1-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP1]], i32 5
+; AVX1-NEXT:    [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[TMP5]], i32 5
+; AVX1-NEXT:    [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
+; AVX1-NEXT:    [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
+; AVX1-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX2-LABEL: @ashr_lshr_shl_v8i32(
+; AVX2-NEXT:    [[A6:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 6
+; AVX2-NEXT:    [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
+; AVX2-NEXT:    [[B6:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 6
+; AVX2-NEXT:    [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
+; AVX2-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; AVX2-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; AVX2-NEXT:    [[TMP3:%.*]] = ashr <4 x i32> [[TMP1]], [[TMP2]]
+; AVX2-NEXT:    [[TMP4:%.*]] = lshr <4 x i32> [[TMP1]], [[TMP2]]
+; AVX2-NEXT:    [[TMP5:%.*]] = lshr <8 x i32> [[A]], [[B]]
+; AVX2-NEXT:    [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
+; AVX2-NEXT:    [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
+; AVX2-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; AVX2-NEXT:    [[R0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP6]], i32 0
+; AVX2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; AVX2-NEXT:    [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[TMP7]], i32 1
+; AVX2-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[TMP4]], i32 2
+; AVX2-NEXT:    [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[TMP8]], i32 2
+; AVX2-NEXT:    [[TMP9:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3
+; AVX2-NEXT:    [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[TMP9]], i32 3
+; AVX2-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP5]], i32 4
+; AVX2-NEXT:    [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[TMP10]], i32 4
+; AVX2-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP5]], i32 5
+; AVX2-NEXT:    [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[TMP11]], i32 5
+; AVX2-NEXT:    [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
+; AVX2-NEXT:    [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
+; AVX2-NEXT:    ret <8 x i32> [[R7]]
+;
+; AVX512-LABEL: @ashr_lshr_shl_v8i32(
+; AVX512-NEXT:    [[A6:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 6
+; AVX512-NEXT:    [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
+; AVX512-NEXT:    [[B6:%.*]] = extractelement <8 x i32> [[B:%.*]], i32 6
+; AVX512-NEXT:    [[B7:%.*]] = extractelement <8 x i32> [[B]], i32 7
+; AVX512-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i32> [[B]], <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; AVX512-NEXT:    [[TMP3:%.*]] = ashr <4 x i32> [[TMP1]], [[TMP2]]
+; AVX512-NEXT:    [[TMP4:%.*]] = lshr <4 x i32> [[TMP1]], [[TMP2]]
+; AVX512-NEXT:    [[TMP5:%.*]] = lshr <8 x i32> [[A]], [[B]]
+; AVX512-NEXT:    [[AB6:%.*]] = shl i32 [[A6]], [[B6]]
+; AVX512-NEXT:    [[AB7:%.*]] = shl i32 [[A7]], [[B7]]
+; AVX512-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; AVX512-NEXT:    [[R0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP6]], i32 0
+; AVX512-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; AVX512-NEXT:    [[R1:%.*]] = insertelement <8 x i32> [[R0]], i32 [[TMP7]], i32 1
+; AVX512-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[TMP4]], i32 2
+; AVX512-NEXT:    [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[TMP8]], i32 2
+; AVX512-NEXT:    [[TMP9:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3
+; AVX512-NEXT:    [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[TMP9]], i32 3
+; AVX512-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP5]], i32 4
+; AVX512-NEXT:    [[R4:%.*]] = insertelement <8 x i32> [[R3]], i32 [[TMP10]], i32 4
+; AVX512-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP5]], i32 5
+; AVX512-NEXT:    [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[TMP11]], i32 5
+; AVX512-NEXT:    [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
+; AVX512-NEXT:    [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
+; AVX512-NEXT:    ret <8 x i32> [[R7]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %b0 = extractelement <8 x i32> %b, i32 0
+  %b1 = extractelement <8 x i32> %b, i32 1
+  %b2 = extractelement <8 x i32> %b, i32 2
+  %b3 = extractelement <8 x i32> %b, i32 3
+  %b4 = extractelement <8 x i32> %b, i32 4
+  %b5 = extractelement <8 x i32> %b, i32 5
+  %b6 = extractelement <8 x i32> %b, i32 6
+  %b7 = extractelement <8 x i32> %b, i32 7
+  %ab0 = ashr i32 %a0, %b0
+  %ab1 = ashr i32 %a1, %b1
+  %ab2 = lshr i32 %a2, %b2
+  %ab3 = lshr i32 %a3, %b3
+  %ab4 = lshr i32 %a4, %b4
+  %ab5 = lshr i32 %a5, %b5
+  %ab6 = shl  i32 %a6, %b6
+  %ab7 = shl  i32 %a7, %b7
+  %r0 = insertelement <8 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <8 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <8 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <8 x i32>   %r2, i32 %ab3, i32 3
+  %r4 = insertelement <8 x i32>   %r3, i32 %ab4, i32 4
+  %r5 = insertelement <8 x i32>   %r4, i32 %ab5, i32 5
+  %r6 = insertelement <8 x i32>   %r5, i32 %ab6, i32 6
+  %r7 = insertelement <8 x i32>   %r6, i32 %ab7, i32 7
+  ret <8 x i32> %r7
+}
+
+define <8 x i32> @add_v8i32_undefs(<8 x i32> %a) {
+; CHECK-LABEL: @add_v8i32_undefs(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <8 x i32> [[A:%.*]], <i32 undef, i32 4, i32 8, i32 16, i32 undef, i32 4, i32 8, i32 16>
+; CHECK-NEXT:    ret <8 x i32> [[TMP1]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %ab0 = add i32 %a0, undef
+  %ab1 = add i32 %a1, 4
+  %ab2 = add i32 %a2, 8
+  %ab3 = add i32 %a3, 16
+  %ab4 = add i32 %a4, undef
+  %ab5 = add i32 %a5, 4
+  %ab6 = add i32 %a6, 8
+  %ab7 = add i32 %a7, 16
+  %r0 = insertelement <8 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <8 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <8 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <8 x i32>   %r2, i32 %ab3, i32 3
+  %r4 = insertelement <8 x i32>   %r3, i32 %ab4, i32 4
+  %r5 = insertelement <8 x i32>   %r4, i32 %ab5, i32 5
+  %r6 = insertelement <8 x i32>   %r5, i32 %ab6, i32 6
+  %r7 = insertelement <8 x i32>   %r6, i32 %ab7, i32 7
+  ret <8 x i32> %r7
+}
+
+define <8 x i32> @sdiv_v8i32_undefs(<8 x i32> %a) {
+; CHECK-LABEL: @sdiv_v8i32_undefs(
+; CHECK-NEXT:    [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i32 1
+; CHECK-NEXT:    [[A2:%.*]] = extractelement <8 x i32> [[A]], i32 2
+; CHECK-NEXT:    [[A3:%.*]] = extractelement <8 x i32> [[A]], i32 3
+; CHECK-NEXT:    [[A5:%.*]] = extractelement <8 x i32> [[A]], i32 5
+; CHECK-NEXT:    [[A6:%.*]] = extractelement <8 x i32> [[A]], i32 6
+; CHECK-NEXT:    [[A7:%.*]] = extractelement <8 x i32> [[A]], i32 7
+; CHECK-NEXT:    [[AB1:%.*]] = sdiv i32 [[A1]], 4
+; CHECK-NEXT:    [[AB2:%.*]] = sdiv i32 [[A2]], 8
+; CHECK-NEXT:    [[AB3:%.*]] = sdiv i32 [[A3]], 16
+; CHECK-NEXT:    [[AB5:%.*]] = sdiv i32 [[A5]], 4
+; CHECK-NEXT:    [[AB6:%.*]] = sdiv i32 [[A6]], 8
+; CHECK-NEXT:    [[AB7:%.*]] = sdiv i32 [[A7]], 16
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <8 x i32> <i32 undef, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <8 x i32> [[TMP1]], i32 [[AB2]], i32 2
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[AB3]], i32 3
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x i32> [[R4]], i32 [[AB5]], i32 5
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i32 6
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i32 7
+; CHECK-NEXT:    ret <8 x i32> [[R7]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %ab0 = sdiv i32 %a0, undef
+  %ab1 = sdiv i32 %a1, 4
+  %ab2 = sdiv i32 %a2, 8
+  %ab3 = sdiv i32 %a3, 16
+  %ab4 = sdiv i32 %a4, undef
+  %ab5 = sdiv i32 %a5, 4
+  %ab6 = sdiv i32 %a6, 8
+  %ab7 = sdiv i32 %a7, 16
+  %r0 = insertelement <8 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <8 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <8 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <8 x i32>   %r2, i32 %ab3, i32 3
+  %r4 = insertelement <8 x i32>   %r3, i32 %ab4, i32 4
+  %r5 = insertelement <8 x i32>   %r4, i32 %ab5, i32 5
+  %r6 = insertelement <8 x i32>   %r5, i32 %ab6, i32 6
+  %r7 = insertelement <8 x i32>   %r6, i32 %ab7, i32 7
+  ret <8 x i32> %r7
+}
+
+define <8 x i32> @add_sub_v8i32_splat(<8 x i32> %a, i32 %b) {
+; CHECK-LABEL: @add_sub_v8i32_splat(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <8 x i32> undef, i32 [[B:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP3:%.*]] = add <8 x i32> [[TMP2]], [[A:%.*]]
+; CHECK-NEXT:    [[TMP4:%.*]] = sub <8 x i32> [[TMP2]], [[A]]
+; CHECK-NEXT:    [[R7:%.*]] = shufflevector <8 x i32> [[TMP3]], <8 x i32> [[TMP4]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT:    ret <8 x i32> [[R7]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %ab0 = add i32 %a0, %b
+  %ab1 = add i32 %b, %a1
+  %ab2 = add i32 %a2, %b
+  %ab3 = add i32 %b, %a3
+  %ab4 = sub i32 %b, %a4
+  %ab5 = sub i32 %b, %a5
+  %ab6 = sub i32 %b, %a6
+  %ab7 = sub i32 %b, %a7
+  %r0 = insertelement <8 x i32> poison, i32 %ab0, i32 0
+  %r1 = insertelement <8 x i32>   %r0, i32 %ab1, i32 1
+  %r2 = insertelement <8 x i32>   %r1, i32 %ab2, i32 2
+  %r3 = insertelement <8 x i32>   %r2, i32 %ab3, i32 3
+  %r4 = insertelement <8 x i32>   %r3, i32 %ab4, i32 4
+  %r5 = insertelement <8 x i32>   %r4, i32 %ab5, i32 5
+  %r6 = insertelement <8 x i32>   %r5, i32 %ab6, i32 6
+  %r7 = insertelement <8 x i32>   %r6, i32 %ab7, i32 7
+  ret <8 x i32> %r7
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/arith-fp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/arith-fp-inseltpoison.ll
new file mode 100644
index 0000000000000..68a8c8684b68b
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/arith-fp-inseltpoison.ll
@@ -0,0 +1,1365 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SLM
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -mattr=-prefer-128-bit -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -mattr=+prefer-128-bit -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -mattr=-prefer-128-bit -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -mattr=+prefer-128-bit -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX512
+
+;
+; 128-bit Vectors
+;
+
+define <2 x double> @buildvector_add_2f64(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @buildvector_add_2f64(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[TMP3]], i32 1
+; CHECK-NEXT:    ret <2 x double> [[R1]]
+;
+  %a0 = extractelement <2 x double> %a, i32 0
+  %a1 = extractelement <2 x double> %a, i32 1
+  %b0 = extractelement <2 x double> %b, i32 0
+  %b1 = extractelement <2 x double> %b, i32 1
+  %c0 = fadd double %a0, %b0
+  %c1 = fadd double %a1, %b1
+  %r0 = insertelement <2 x double> poison, double %c0, i32 0
+  %r1 = insertelement <2 x double> %r0,   double %c1, i32 1
+  ret <2 x double> %r1
+}
+
+define <2 x double> @buildvector_sub_2f64(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @buildvector_sub_2f64(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <2 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[TMP3]], i32 1
+; CHECK-NEXT:    ret <2 x double> [[R1]]
+;
+  %a0 = extractelement <2 x double> %a, i32 0
+  %a1 = extractelement <2 x double> %a, i32 1
+  %b0 = extractelement <2 x double> %b, i32 0
+  %b1 = extractelement <2 x double> %b, i32 1
+  %c0 = fsub double %a0, %b0
+  %c1 = fsub double %a1, %b1
+  %r0 = insertelement <2 x double> poison, double %c0, i32 0
+  %r1 = insertelement <2 x double> %r0,   double %c1, i32 1
+  ret <2 x double> %r1
+}
+
+define <2 x double> @buildvector_mul_2f64(<2 x double> %a, <2 x double> %b) {
+; CHECK-LABEL: @buildvector_mul_2f64(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <2 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[TMP3]], i32 1
+; CHECK-NEXT:    ret <2 x double> [[R1]]
+;
+  %a0 = extractelement <2 x double> %a, i32 0
+  %a1 = extractelement <2 x double> %a, i32 1
+  %b0 = extractelement <2 x double> %b, i32 0
+  %b1 = extractelement <2 x double> %b, i32 1
+  %c0 = fmul double %a0, %b0
+  %c1 = fmul double %a1, %b1
+  %r0 = insertelement <2 x double> poison, double %c0, i32 0
+  %r1 = insertelement <2 x double> %r0,   double %c1, i32 1
+  ret <2 x double> %r1
+}
+
+define <2 x double> @buildvector_div_2f64(<2 x double> %a, <2 x double> %b) {
+; SSE-LABEL: @buildvector_div_2f64(
+; SSE-NEXT:    [[TMP1:%.*]] = fdiv <2 x double> [[A:%.*]], [[B:%.*]]
+; SSE-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
+; SSE-NEXT:    [[R0:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i32 0
+; SSE-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; SSE-NEXT:    [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[TMP3]], i32 1
+; SSE-NEXT:    ret <2 x double> [[R1]]
+;
+; SLM-LABEL: @buildvector_div_2f64(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <2 x double> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <2 x double> [[A]], i32 1
+; SLM-NEXT:    [[B0:%.*]] = extractelement <2 x double> [[B:%.*]], i32 0
+; SLM-NEXT:    [[B1:%.*]] = extractelement <2 x double> [[B]], i32 1
+; SLM-NEXT:    [[C0:%.*]] = fdiv double [[A0]], [[B0]]
+; SLM-NEXT:    [[C1:%.*]] = fdiv double [[A1]], [[B1]]
+; SLM-NEXT:    [[R0:%.*]] = insertelement <2 x double> poison, double [[C0]], i32 0
+; SLM-NEXT:    [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[C1]], i32 1
+; SLM-NEXT:    ret <2 x double> [[R1]]
+;
+; AVX-LABEL: @buildvector_div_2f64(
+; AVX-NEXT:    [[TMP1:%.*]] = fdiv <2 x double> [[A:%.*]], [[B:%.*]]
+; AVX-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
+; AVX-NEXT:    [[R0:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i32 0
+; AVX-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; AVX-NEXT:    [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[TMP3]], i32 1
+; AVX-NEXT:    ret <2 x double> [[R1]]
+;
+; AVX512-LABEL: @buildvector_div_2f64(
+; AVX512-NEXT:    [[TMP1:%.*]] = fdiv <2 x double> [[A:%.*]], [[B:%.*]]
+; AVX512-NEXT:    [[TMP2:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
+; AVX512-NEXT:    [[R0:%.*]] = insertelement <2 x double> poison, double [[TMP2]], i32 0
+; AVX512-NEXT:    [[TMP3:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; AVX512-NEXT:    [[R1:%.*]] = insertelement <2 x double> [[R0]], double [[TMP3]], i32 1
+; AVX512-NEXT:    ret <2 x double> [[R1]]
+;
+  %a0 = extractelement <2 x double> %a, i32 0
+  %a1 = extractelement <2 x double> %a, i32 1
+  %b0 = extractelement <2 x double> %b, i32 0
+  %b1 = extractelement <2 x double> %b, i32 1
+  %c0 = fdiv double %a0, %b0
+  %c1 = fdiv double %a1, %b1
+  %r0 = insertelement <2 x double> poison, double %c0, i32 0
+  %r1 = insertelement <2 x double> %r0,   double %c1, i32 1
+  ret <2 x double> %r1
+}
+
+define <4 x float> @buildvector_add_4f32(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @buildvector_add_4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <4 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <4 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <4 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[R3]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %c0 = fadd float %a0, %b0
+  %c1 = fadd float %a1, %b1
+  %c2 = fadd float %a2, %b2
+  %c3 = fadd float %a3, %b3
+  %r0 = insertelement <4 x float> poison, float %c0, i32 0
+  %r1 = insertelement <4 x float> %r0,   float %c1, i32 1
+  %r2 = insertelement <4 x float> %r1,   float %c2, i32 2
+  %r3 = insertelement <4 x float> %r2,   float %c3, i32 3
+  ret <4 x float> %r3
+}
+
+define <4 x float> @buildvector_sub_4f32(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @buildvector_sub_4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <4 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <4 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <4 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[R3]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %c0 = fsub float %a0, %b0
+  %c1 = fsub float %a1, %b1
+  %c2 = fsub float %a2, %b2
+  %c3 = fsub float %a3, %b3
+  %r0 = insertelement <4 x float> poison, float %c0, i32 0
+  %r1 = insertelement <4 x float> %r0,   float %c1, i32 1
+  %r2 = insertelement <4 x float> %r1,   float %c2, i32 2
+  %r3 = insertelement <4 x float> %r2,   float %c3, i32 3
+  ret <4 x float> %r3
+}
+
+define <4 x float> @buildvector_mul_4f32(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @buildvector_mul_4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <4 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <4 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <4 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[R3]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %c0 = fmul float %a0, %b0
+  %c1 = fmul float %a1, %b1
+  %c2 = fmul float %a2, %b2
+  %c3 = fmul float %a3, %b3
+  %r0 = insertelement <4 x float> poison, float %c0, i32 0
+  %r1 = insertelement <4 x float> %r0,   float %c1, i32 1
+  %r2 = insertelement <4 x float> %r1,   float %c2, i32 2
+  %r3 = insertelement <4 x float> %r2,   float %c3, i32 3
+  ret <4 x float> %r3
+}
+
+define <4 x float> @buildvector_div_4f32(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @buildvector_div_4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <4 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <4 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <4 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[R3]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %c0 = fdiv float %a0, %b0
+  %c1 = fdiv float %a1, %b1
+  %c2 = fdiv float %a2, %b2
+  %c3 = fdiv float %a3, %b3
+  %r0 = insertelement <4 x float> poison, float %c0, i32 0
+  %r1 = insertelement <4 x float> %r0,   float %c1, i32 1
+  %r2 = insertelement <4 x float> %r1,   float %c2, i32 2
+  %r3 = insertelement <4 x float> %r2,   float %c3, i32 3
+  ret <4 x float> %r3
+}
+
+;
+; 256-bit Vectors
+;
+
+define <4 x double> @buildvector_add_4f64(<4 x double> %a, <4 x double> %b) {
+; CHECK-LABEL: @buildvector_add_4f64(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <4 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x double> [[R3]]
+;
+  %a0 = extractelement <4 x double> %a, i32 0
+  %a1 = extractelement <4 x double> %a, i32 1
+  %a2 = extractelement <4 x double> %a, i32 2
+  %a3 = extractelement <4 x double> %a, i32 3
+  %b0 = extractelement <4 x double> %b, i32 0
+  %b1 = extractelement <4 x double> %b, i32 1
+  %b2 = extractelement <4 x double> %b, i32 2
+  %b3 = extractelement <4 x double> %b, i32 3
+  %c0 = fadd double %a0, %b0
+  %c1 = fadd double %a1, %b1
+  %c2 = fadd double %a2, %b2
+  %c3 = fadd double %a3, %b3
+  %r0 = insertelement <4 x double> poison, double %c0, i32 0
+  %r1 = insertelement <4 x double> %r0,   double %c1, i32 1
+  %r2 = insertelement <4 x double> %r1,   double %c2, i32 2
+  %r3 = insertelement <4 x double> %r2,   double %c3, i32 3
+  ret <4 x double> %r3
+}
+
+define <4 x double> @buildvector_sub_4f64(<4 x double> %a, <4 x double> %b) {
+; CHECK-LABEL: @buildvector_sub_4f64(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <4 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x double> [[R3]]
+;
+  %a0 = extractelement <4 x double> %a, i32 0
+  %a1 = extractelement <4 x double> %a, i32 1
+  %a2 = extractelement <4 x double> %a, i32 2
+  %a3 = extractelement <4 x double> %a, i32 3
+  %b0 = extractelement <4 x double> %b, i32 0
+  %b1 = extractelement <4 x double> %b, i32 1
+  %b2 = extractelement <4 x double> %b, i32 2
+  %b3 = extractelement <4 x double> %b, i32 3
+  %c0 = fsub double %a0, %b0
+  %c1 = fsub double %a1, %b1
+  %c2 = fsub double %a2, %b2
+  %c3 = fsub double %a3, %b3
+  %r0 = insertelement <4 x double> poison, double %c0, i32 0
+  %r1 = insertelement <4 x double> %r0,   double %c1, i32 1
+  %r2 = insertelement <4 x double> %r1,   double %c2, i32 2
+  %r3 = insertelement <4 x double> %r2,   double %c3, i32 3
+  ret <4 x double> %r3
+}
+
+define <4 x double> @buildvector_mul_4f64(<4 x double> %a, <4 x double> %b) {
+; CHECK-LABEL: @buildvector_mul_4f64(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <4 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x double> [[R3]]
+;
+  %a0 = extractelement <4 x double> %a, i32 0
+  %a1 = extractelement <4 x double> %a, i32 1
+  %a2 = extractelement <4 x double> %a, i32 2
+  %a3 = extractelement <4 x double> %a, i32 3
+  %b0 = extractelement <4 x double> %b, i32 0
+  %b1 = extractelement <4 x double> %b, i32 1
+  %b2 = extractelement <4 x double> %b, i32 2
+  %b3 = extractelement <4 x double> %b, i32 3
+  %c0 = fmul double %a0, %b0
+  %c1 = fmul double %a1, %b1
+  %c2 = fmul double %a2, %b2
+  %c3 = fmul double %a3, %b3
+  %r0 = insertelement <4 x double> poison, double %c0, i32 0
+  %r1 = insertelement <4 x double> %r0,   double %c1, i32 1
+  %r2 = insertelement <4 x double> %r1,   double %c2, i32 2
+  %r3 = insertelement <4 x double> %r2,   double %c3, i32 3
+  ret <4 x double> %r3
+}
+
+define <4 x double> @buildvector_div_4f64(<4 x double> %a, <4 x double> %b) {
+; SSE-LABEL: @buildvector_div_4f64(
+; SSE-NEXT:    [[TMP1:%.*]] = fdiv <4 x double> [[A:%.*]], [[B:%.*]]
+; SSE-NEXT:    [[TMP2:%.*]] = extractelement <4 x double> [[TMP1]], i32 0
+; SSE-NEXT:    [[R0:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i32 0
+; SSE-NEXT:    [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 1
+; SSE-NEXT:    [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[TMP3]], i32 1
+; SSE-NEXT:    [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 2
+; SSE-NEXT:    [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[TMP4]], i32 2
+; SSE-NEXT:    [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 3
+; SSE-NEXT:    [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[TMP5]], i32 3
+; SSE-NEXT:    ret <4 x double> [[R3]]
+;
+; SLM-LABEL: @buildvector_div_4f64(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <4 x double> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <4 x double> [[A]], i32 1
+; SLM-NEXT:    [[A2:%.*]] = extractelement <4 x double> [[A]], i32 2
+; SLM-NEXT:    [[A3:%.*]] = extractelement <4 x double> [[A]], i32 3
+; SLM-NEXT:    [[B0:%.*]] = extractelement <4 x double> [[B:%.*]], i32 0
+; SLM-NEXT:    [[B1:%.*]] = extractelement <4 x double> [[B]], i32 1
+; SLM-NEXT:    [[B2:%.*]] = extractelement <4 x double> [[B]], i32 2
+; SLM-NEXT:    [[B3:%.*]] = extractelement <4 x double> [[B]], i32 3
+; SLM-NEXT:    [[C0:%.*]] = fdiv double [[A0]], [[B0]]
+; SLM-NEXT:    [[C1:%.*]] = fdiv double [[A1]], [[B1]]
+; SLM-NEXT:    [[C2:%.*]] = fdiv double [[A2]], [[B2]]
+; SLM-NEXT:    [[C3:%.*]] = fdiv double [[A3]], [[B3]]
+; SLM-NEXT:    [[R0:%.*]] = insertelement <4 x double> poison, double [[C0]], i32 0
+; SLM-NEXT:    [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[C1]], i32 1
+; SLM-NEXT:    [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[C2]], i32 2
+; SLM-NEXT:    [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[C3]], i32 3
+; SLM-NEXT:    ret <4 x double> [[R3]]
+;
+; AVX-LABEL: @buildvector_div_4f64(
+; AVX-NEXT:    [[TMP1:%.*]] = fdiv <4 x double> [[A:%.*]], [[B:%.*]]
+; AVX-NEXT:    [[TMP2:%.*]] = extractelement <4 x double> [[TMP1]], i32 0
+; AVX-NEXT:    [[R0:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i32 0
+; AVX-NEXT:    [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 1
+; AVX-NEXT:    [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[TMP3]], i32 1
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 2
+; AVX-NEXT:    [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[TMP4]], i32 2
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 3
+; AVX-NEXT:    [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[TMP5]], i32 3
+; AVX-NEXT:    ret <4 x double> [[R3]]
+;
+; AVX512-LABEL: @buildvector_div_4f64(
+; AVX512-NEXT:    [[TMP1:%.*]] = fdiv <4 x double> [[A:%.*]], [[B:%.*]]
+; AVX512-NEXT:    [[TMP2:%.*]] = extractelement <4 x double> [[TMP1]], i32 0
+; AVX512-NEXT:    [[R0:%.*]] = insertelement <4 x double> poison, double [[TMP2]], i32 0
+; AVX512-NEXT:    [[TMP3:%.*]] = extractelement <4 x double> [[TMP1]], i32 1
+; AVX512-NEXT:    [[R1:%.*]] = insertelement <4 x double> [[R0]], double [[TMP3]], i32 1
+; AVX512-NEXT:    [[TMP4:%.*]] = extractelement <4 x double> [[TMP1]], i32 2
+; AVX512-NEXT:    [[R2:%.*]] = insertelement <4 x double> [[R1]], double [[TMP4]], i32 2
+; AVX512-NEXT:    [[TMP5:%.*]] = extractelement <4 x double> [[TMP1]], i32 3
+; AVX512-NEXT:    [[R3:%.*]] = insertelement <4 x double> [[R2]], double [[TMP5]], i32 3
+; AVX512-NEXT:    ret <4 x double> [[R3]]
+;
+  %a0 = extractelement <4 x double> %a, i32 0
+  %a1 = extractelement <4 x double> %a, i32 1
+  %a2 = extractelement <4 x double> %a, i32 2
+  %a3 = extractelement <4 x double> %a, i32 3
+  %b0 = extractelement <4 x double> %b, i32 0
+  %b1 = extractelement <4 x double> %b, i32 1
+  %b2 = extractelement <4 x double> %b, i32 2
+  %b3 = extractelement <4 x double> %b, i32 3
+  %c0 = fdiv double %a0, %b0
+  %c1 = fdiv double %a1, %b1
+  %c2 = fdiv double %a2, %b2
+  %c3 = fdiv double %a3, %b3
+  %r0 = insertelement <4 x double> poison, double %c0, i32 0
+  %r1 = insertelement <4 x double> %r0,   double %c1, i32 1
+  %r2 = insertelement <4 x double> %r1,   double %c2, i32 2
+  %r3 = insertelement <4 x double> %r2,   double %c3, i32 3
+  ret <4 x double> %r3
+}
+
+define <8 x float> @buildvector_add_8f32(<8 x float> %a, <8 x float> %b) {
+; CHECK-LABEL: @buildvector_add_8f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <8 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <8 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <8 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x float> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x float> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x float> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x float> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[TMP9]], i32 7
+; CHECK-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %b0 = extractelement <8 x float> %b, i32 0
+  %b1 = extractelement <8 x float> %b, i32 1
+  %b2 = extractelement <8 x float> %b, i32 2
+  %b3 = extractelement <8 x float> %b, i32 3
+  %b4 = extractelement <8 x float> %b, i32 4
+  %b5 = extractelement <8 x float> %b, i32 5
+  %b6 = extractelement <8 x float> %b, i32 6
+  %b7 = extractelement <8 x float> %b, i32 7
+  %c0 = fadd float %a0, %b0
+  %c1 = fadd float %a1, %b1
+  %c2 = fadd float %a2, %b2
+  %c3 = fadd float %a3, %b3
+  %c4 = fadd float %a4, %b4
+  %c5 = fadd float %a5, %b5
+  %c6 = fadd float %a6, %b6
+  %c7 = fadd float %a7, %b7
+  %r0 = insertelement <8 x float> poison, float %c0, i32 0
+  %r1 = insertelement <8 x float> %r0,   float %c1, i32 1
+  %r2 = insertelement <8 x float> %r1,   float %c2, i32 2
+  %r3 = insertelement <8 x float> %r2,   float %c3, i32 3
+  %r4 = insertelement <8 x float> %r3,   float %c4, i32 4
+  %r5 = insertelement <8 x float> %r4,   float %c5, i32 5
+  %r6 = insertelement <8 x float> %r5,   float %c6, i32 6
+  %r7 = insertelement <8 x float> %r6,   float %c7, i32 7
+  ret <8 x float> %r7
+}
+
+define <8 x float> @buildvector_sub_8f32(<8 x float> %a, <8 x float> %b) {
+; CHECK-LABEL: @buildvector_sub_8f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <8 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <8 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <8 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x float> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x float> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x float> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x float> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[TMP9]], i32 7
+; CHECK-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %b0 = extractelement <8 x float> %b, i32 0
+  %b1 = extractelement <8 x float> %b, i32 1
+  %b2 = extractelement <8 x float> %b, i32 2
+  %b3 = extractelement <8 x float> %b, i32 3
+  %b4 = extractelement <8 x float> %b, i32 4
+  %b5 = extractelement <8 x float> %b, i32 5
+  %b6 = extractelement <8 x float> %b, i32 6
+  %b7 = extractelement <8 x float> %b, i32 7
+  %c0 = fsub float %a0, %b0
+  %c1 = fsub float %a1, %b1
+  %c2 = fsub float %a2, %b2
+  %c3 = fsub float %a3, %b3
+  %c4 = fsub float %a4, %b4
+  %c5 = fsub float %a5, %b5
+  %c6 = fsub float %a6, %b6
+  %c7 = fsub float %a7, %b7
+  %r0 = insertelement <8 x float> poison, float %c0, i32 0
+  %r1 = insertelement <8 x float> %r0,   float %c1, i32 1
+  %r2 = insertelement <8 x float> %r1,   float %c2, i32 2
+  %r3 = insertelement <8 x float> %r2,   float %c3, i32 3
+  %r4 = insertelement <8 x float> %r3,   float %c4, i32 4
+  %r5 = insertelement <8 x float> %r4,   float %c5, i32 5
+  %r6 = insertelement <8 x float> %r5,   float %c6, i32 6
+  %r7 = insertelement <8 x float> %r6,   float %c7, i32 7
+  ret <8 x float> %r7
+}
+
+define <8 x float> @buildvector_mul_8f32(<8 x float> %a, <8 x float> %b) {
+; CHECK-LABEL: @buildvector_mul_8f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <8 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <8 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <8 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x float> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x float> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x float> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x float> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[TMP9]], i32 7
+; CHECK-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %b0 = extractelement <8 x float> %b, i32 0
+  %b1 = extractelement <8 x float> %b, i32 1
+  %b2 = extractelement <8 x float> %b, i32 2
+  %b3 = extractelement <8 x float> %b, i32 3
+  %b4 = extractelement <8 x float> %b, i32 4
+  %b5 = extractelement <8 x float> %b, i32 5
+  %b6 = extractelement <8 x float> %b, i32 6
+  %b7 = extractelement <8 x float> %b, i32 7
+  %c0 = fmul float %a0, %b0
+  %c1 = fmul float %a1, %b1
+  %c2 = fmul float %a2, %b2
+  %c3 = fmul float %a3, %b3
+  %c4 = fmul float %a4, %b4
+  %c5 = fmul float %a5, %b5
+  %c6 = fmul float %a6, %b6
+  %c7 = fmul float %a7, %b7
+  %r0 = insertelement <8 x float> poison, float %c0, i32 0
+  %r1 = insertelement <8 x float> %r0,   float %c1, i32 1
+  %r2 = insertelement <8 x float> %r1,   float %c2, i32 2
+  %r3 = insertelement <8 x float> %r2,   float %c3, i32 3
+  %r4 = insertelement <8 x float> %r3,   float %c4, i32 4
+  %r5 = insertelement <8 x float> %r4,   float %c5, i32 5
+  %r6 = insertelement <8 x float> %r5,   float %c6, i32 6
+  %r7 = insertelement <8 x float> %r6,   float %c7, i32 7
+  ret <8 x float> %r7
+}
+
+define <8 x float> @buildvector_div_8f32(<8 x float> %a, <8 x float> %b) {
+; CHECK-LABEL: @buildvector_div_8f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <8 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <8 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <8 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <8 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <8 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <8 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <8 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x float> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x float> [[R3]], float [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x float> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x float> [[R4]], float [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x float> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x float> [[R5]], float [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x float> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x float> [[R6]], float [[TMP9]], i32 7
+; CHECK-NEXT:    ret <8 x float> [[R7]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %b0 = extractelement <8 x float> %b, i32 0
+  %b1 = extractelement <8 x float> %b, i32 1
+  %b2 = extractelement <8 x float> %b, i32 2
+  %b3 = extractelement <8 x float> %b, i32 3
+  %b4 = extractelement <8 x float> %b, i32 4
+  %b5 = extractelement <8 x float> %b, i32 5
+  %b6 = extractelement <8 x float> %b, i32 6
+  %b7 = extractelement <8 x float> %b, i32 7
+  %c0 = fdiv float %a0, %b0
+  %c1 = fdiv float %a1, %b1
+  %c2 = fdiv float %a2, %b2
+  %c3 = fdiv float %a3, %b3
+  %c4 = fdiv float %a4, %b4
+  %c5 = fdiv float %a5, %b5
+  %c6 = fdiv float %a6, %b6
+  %c7 = fdiv float %a7, %b7
+  %r0 = insertelement <8 x float> poison, float %c0, i32 0
+  %r1 = insertelement <8 x float> %r0,   float %c1, i32 1
+  %r2 = insertelement <8 x float> %r1,   float %c2, i32 2
+  %r3 = insertelement <8 x float> %r2,   float %c3, i32 3
+  %r4 = insertelement <8 x float> %r3,   float %c4, i32 4
+  %r5 = insertelement <8 x float> %r4,   float %c5, i32 5
+  %r6 = insertelement <8 x float> %r5,   float %c6, i32 6
+  %r7 = insertelement <8 x float> %r6,   float %c7, i32 7
+  ret <8 x float> %r7
+}
+
+;
+; 512-bit Vectors
+;
+
+define <8 x double> @buildvector_add_8f64(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @buildvector_add_8f64(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <8 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <8 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <8 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x double> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x double> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x double> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x double> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x double> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x double> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[TMP9]], i32 7
+; CHECK-NEXT:    ret <8 x double> [[R7]]
+;
+  %a0 = extractelement <8 x double> %a, i32 0
+  %a1 = extractelement <8 x double> %a, i32 1
+  %a2 = extractelement <8 x double> %a, i32 2
+  %a3 = extractelement <8 x double> %a, i32 3
+  %a4 = extractelement <8 x double> %a, i32 4
+  %a5 = extractelement <8 x double> %a, i32 5
+  %a6 = extractelement <8 x double> %a, i32 6
+  %a7 = extractelement <8 x double> %a, i32 7
+  %b0 = extractelement <8 x double> %b, i32 0
+  %b1 = extractelement <8 x double> %b, i32 1
+  %b2 = extractelement <8 x double> %b, i32 2
+  %b3 = extractelement <8 x double> %b, i32 3
+  %b4 = extractelement <8 x double> %b, i32 4
+  %b5 = extractelement <8 x double> %b, i32 5
+  %b6 = extractelement <8 x double> %b, i32 6
+  %b7 = extractelement <8 x double> %b, i32 7
+  %c0 = fadd double %a0, %b0
+  %c1 = fadd double %a1, %b1
+  %c2 = fadd double %a2, %b2
+  %c3 = fadd double %a3, %b3
+  %c4 = fadd double %a4, %b4
+  %c5 = fadd double %a5, %b5
+  %c6 = fadd double %a6, %b6
+  %c7 = fadd double %a7, %b7
+  %r0 = insertelement <8 x double> poison, double %c0, i32 0
+  %r1 = insertelement <8 x double> %r0,   double %c1, i32 1
+  %r2 = insertelement <8 x double> %r1,   double %c2, i32 2
+  %r3 = insertelement <8 x double> %r2,   double %c3, i32 3
+  %r4 = insertelement <8 x double> %r3,   double %c4, i32 4
+  %r5 = insertelement <8 x double> %r4,   double %c5, i32 5
+  %r6 = insertelement <8 x double> %r5,   double %c6, i32 6
+  %r7 = insertelement <8 x double> %r6,   double %c7, i32 7
+  ret <8 x double> %r7
+}
+
+define <8 x double> @buildvector_sub_8f64(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @buildvector_sub_8f64(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <8 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <8 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <8 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x double> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x double> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x double> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x double> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x double> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x double> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[TMP9]], i32 7
+; CHECK-NEXT:    ret <8 x double> [[R7]]
+;
+  %a0 = extractelement <8 x double> %a, i32 0
+  %a1 = extractelement <8 x double> %a, i32 1
+  %a2 = extractelement <8 x double> %a, i32 2
+  %a3 = extractelement <8 x double> %a, i32 3
+  %a4 = extractelement <8 x double> %a, i32 4
+  %a5 = extractelement <8 x double> %a, i32 5
+  %a6 = extractelement <8 x double> %a, i32 6
+  %a7 = extractelement <8 x double> %a, i32 7
+  %b0 = extractelement <8 x double> %b, i32 0
+  %b1 = extractelement <8 x double> %b, i32 1
+  %b2 = extractelement <8 x double> %b, i32 2
+  %b3 = extractelement <8 x double> %b, i32 3
+  %b4 = extractelement <8 x double> %b, i32 4
+  %b5 = extractelement <8 x double> %b, i32 5
+  %b6 = extractelement <8 x double> %b, i32 6
+  %b7 = extractelement <8 x double> %b, i32 7
+  %c0 = fsub double %a0, %b0
+  %c1 = fsub double %a1, %b1
+  %c2 = fsub double %a2, %b2
+  %c3 = fsub double %a3, %b3
+  %c4 = fsub double %a4, %b4
+  %c5 = fsub double %a5, %b5
+  %c6 = fsub double %a6, %b6
+  %c7 = fsub double %a7, %b7
+  %r0 = insertelement <8 x double> poison, double %c0, i32 0
+  %r1 = insertelement <8 x double> %r0,   double %c1, i32 1
+  %r2 = insertelement <8 x double> %r1,   double %c2, i32 2
+  %r3 = insertelement <8 x double> %r2,   double %c3, i32 3
+  %r4 = insertelement <8 x double> %r3,   double %c4, i32 4
+  %r5 = insertelement <8 x double> %r4,   double %c5, i32 5
+  %r6 = insertelement <8 x double> %r5,   double %c6, i32 6
+  %r7 = insertelement <8 x double> %r6,   double %c7, i32 7
+  ret <8 x double> %r7
+}
+
+define <8 x double> @buildvector_mul_8f64(<8 x double> %a, <8 x double> %b) {
+; CHECK-LABEL: @buildvector_mul_8f64(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <8 x double> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <8 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <8 x double> poison, double [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <8 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x double> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x double> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x double> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x double> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x double> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x double> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[TMP9]], i32 7
+; CHECK-NEXT:    ret <8 x double> [[R7]]
+;
+  %a0 = extractelement <8 x double> %a, i32 0
+  %a1 = extractelement <8 x double> %a, i32 1
+  %a2 = extractelement <8 x double> %a, i32 2
+  %a3 = extractelement <8 x double> %a, i32 3
+  %a4 = extractelement <8 x double> %a, i32 4
+  %a5 = extractelement <8 x double> %a, i32 5
+  %a6 = extractelement <8 x double> %a, i32 6
+  %a7 = extractelement <8 x double> %a, i32 7
+  %b0 = extractelement <8 x double> %b, i32 0
+  %b1 = extractelement <8 x double> %b, i32 1
+  %b2 = extractelement <8 x double> %b, i32 2
+  %b3 = extractelement <8 x double> %b, i32 3
+  %b4 = extractelement <8 x double> %b, i32 4
+  %b5 = extractelement <8 x double> %b, i32 5
+  %b6 = extractelement <8 x double> %b, i32 6
+  %b7 = extractelement <8 x double> %b, i32 7
+  %c0 = fmul double %a0, %b0
+  %c1 = fmul double %a1, %b1
+  %c2 = fmul double %a2, %b2
+  %c3 = fmul double %a3, %b3
+  %c4 = fmul double %a4, %b4
+  %c5 = fmul double %a5, %b5
+  %c6 = fmul double %a6, %b6
+  %c7 = fmul double %a7, %b7
+  %r0 = insertelement <8 x double> poison, double %c0, i32 0
+  %r1 = insertelement <8 x double> %r0,   double %c1, i32 1
+  %r2 = insertelement <8 x double> %r1,   double %c2, i32 2
+  %r3 = insertelement <8 x double> %r2,   double %c3, i32 3
+  %r4 = insertelement <8 x double> %r3,   double %c4, i32 4
+  %r5 = insertelement <8 x double> %r4,   double %c5, i32 5
+  %r6 = insertelement <8 x double> %r5,   double %c6, i32 6
+  %r7 = insertelement <8 x double> %r6,   double %c7, i32 7
+  ret <8 x double> %r7
+}
+
+define <8 x double> @buildvector_div_8f64(<8 x double> %a, <8 x double> %b) {
+; SSE-LABEL: @buildvector_div_8f64(
+; SSE-NEXT:    [[TMP1:%.*]] = fdiv <8 x double> [[A:%.*]], [[B:%.*]]
+; SSE-NEXT:    [[TMP2:%.*]] = extractelement <8 x double> [[TMP1]], i32 0
+; SSE-NEXT:    [[R0:%.*]] = insertelement <8 x double> poison, double [[TMP2]], i32 0
+; SSE-NEXT:    [[TMP3:%.*]] = extractelement <8 x double> [[TMP1]], i32 1
+; SSE-NEXT:    [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[TMP3]], i32 1
+; SSE-NEXT:    [[TMP4:%.*]] = extractelement <8 x double> [[TMP1]], i32 2
+; SSE-NEXT:    [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[TMP4]], i32 2
+; SSE-NEXT:    [[TMP5:%.*]] = extractelement <8 x double> [[TMP1]], i32 3
+; SSE-NEXT:    [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[TMP5]], i32 3
+; SSE-NEXT:    [[TMP6:%.*]] = extractelement <8 x double> [[TMP1]], i32 4
+; SSE-NEXT:    [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[TMP6]], i32 4
+; SSE-NEXT:    [[TMP7:%.*]] = extractelement <8 x double> [[TMP1]], i32 5
+; SSE-NEXT:    [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[TMP7]], i32 5
+; SSE-NEXT:    [[TMP8:%.*]] = extractelement <8 x double> [[TMP1]], i32 6
+; SSE-NEXT:    [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[TMP8]], i32 6
+; SSE-NEXT:    [[TMP9:%.*]] = extractelement <8 x double> [[TMP1]], i32 7
+; SSE-NEXT:    [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[TMP9]], i32 7
+; SSE-NEXT:    ret <8 x double> [[R7]]
+;
+; SLM-LABEL: @buildvector_div_8f64(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <8 x double> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <8 x double> [[A]], i32 1
+; SLM-NEXT:    [[A2:%.*]] = extractelement <8 x double> [[A]], i32 2
+; SLM-NEXT:    [[A3:%.*]] = extractelement <8 x double> [[A]], i32 3
+; SLM-NEXT:    [[A4:%.*]] = extractelement <8 x double> [[A]], i32 4
+; SLM-NEXT:    [[A5:%.*]] = extractelement <8 x double> [[A]], i32 5
+; SLM-NEXT:    [[A6:%.*]] = extractelement <8 x double> [[A]], i32 6
+; SLM-NEXT:    [[A7:%.*]] = extractelement <8 x double> [[A]], i32 7
+; SLM-NEXT:    [[B0:%.*]] = extractelement <8 x double> [[B:%.*]], i32 0
+; SLM-NEXT:    [[B1:%.*]] = extractelement <8 x double> [[B]], i32 1
+; SLM-NEXT:    [[B2:%.*]] = extractelement <8 x double> [[B]], i32 2
+; SLM-NEXT:    [[B3:%.*]] = extractelement <8 x double> [[B]], i32 3
+; SLM-NEXT:    [[B4:%.*]] = extractelement <8 x double> [[B]], i32 4
+; SLM-NEXT:    [[B5:%.*]] = extractelement <8 x double> [[B]], i32 5
+; SLM-NEXT:    [[B6:%.*]] = extractelement <8 x double> [[B]], i32 6
+; SLM-NEXT:    [[B7:%.*]] = extractelement <8 x double> [[B]], i32 7
+; SLM-NEXT:    [[C0:%.*]] = fdiv double [[A0]], [[B0]]
+; SLM-NEXT:    [[C1:%.*]] = fdiv double [[A1]], [[B1]]
+; SLM-NEXT:    [[C2:%.*]] = fdiv double [[A2]], [[B2]]
+; SLM-NEXT:    [[C3:%.*]] = fdiv double [[A3]], [[B3]]
+; SLM-NEXT:    [[C4:%.*]] = fdiv double [[A4]], [[B4]]
+; SLM-NEXT:    [[C5:%.*]] = fdiv double [[A5]], [[B5]]
+; SLM-NEXT:    [[C6:%.*]] = fdiv double [[A6]], [[B6]]
+; SLM-NEXT:    [[C7:%.*]] = fdiv double [[A7]], [[B7]]
+; SLM-NEXT:    [[R0:%.*]] = insertelement <8 x double> poison, double [[C0]], i32 0
+; SLM-NEXT:    [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[C1]], i32 1
+; SLM-NEXT:    [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[C2]], i32 2
+; SLM-NEXT:    [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[C3]], i32 3
+; SLM-NEXT:    [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[C4]], i32 4
+; SLM-NEXT:    [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[C5]], i32 5
+; SLM-NEXT:    [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[C6]], i32 6
+; SLM-NEXT:    [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[C7]], i32 7
+; SLM-NEXT:    ret <8 x double> [[R7]]
+;
+; AVX-LABEL: @buildvector_div_8f64(
+; AVX-NEXT:    [[TMP1:%.*]] = fdiv <8 x double> [[A:%.*]], [[B:%.*]]
+; AVX-NEXT:    [[TMP2:%.*]] = extractelement <8 x double> [[TMP1]], i32 0
+; AVX-NEXT:    [[R0:%.*]] = insertelement <8 x double> poison, double [[TMP2]], i32 0
+; AVX-NEXT:    [[TMP3:%.*]] = extractelement <8 x double> [[TMP1]], i32 1
+; AVX-NEXT:    [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[TMP3]], i32 1
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <8 x double> [[TMP1]], i32 2
+; AVX-NEXT:    [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[TMP4]], i32 2
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <8 x double> [[TMP1]], i32 3
+; AVX-NEXT:    [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[TMP5]], i32 3
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <8 x double> [[TMP1]], i32 4
+; AVX-NEXT:    [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[TMP6]], i32 4
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <8 x double> [[TMP1]], i32 5
+; AVX-NEXT:    [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[TMP7]], i32 5
+; AVX-NEXT:    [[TMP8:%.*]] = extractelement <8 x double> [[TMP1]], i32 6
+; AVX-NEXT:    [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[TMP8]], i32 6
+; AVX-NEXT:    [[TMP9:%.*]] = extractelement <8 x double> [[TMP1]], i32 7
+; AVX-NEXT:    [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[TMP9]], i32 7
+; AVX-NEXT:    ret <8 x double> [[R7]]
+;
+; AVX512-LABEL: @buildvector_div_8f64(
+; AVX512-NEXT:    [[TMP1:%.*]] = fdiv <8 x double> [[A:%.*]], [[B:%.*]]
+; AVX512-NEXT:    [[TMP2:%.*]] = extractelement <8 x double> [[TMP1]], i32 0
+; AVX512-NEXT:    [[R0:%.*]] = insertelement <8 x double> poison, double [[TMP2]], i32 0
+; AVX512-NEXT:    [[TMP3:%.*]] = extractelement <8 x double> [[TMP1]], i32 1
+; AVX512-NEXT:    [[R1:%.*]] = insertelement <8 x double> [[R0]], double [[TMP3]], i32 1
+; AVX512-NEXT:    [[TMP4:%.*]] = extractelement <8 x double> [[TMP1]], i32 2
+; AVX512-NEXT:    [[R2:%.*]] = insertelement <8 x double> [[R1]], double [[TMP4]], i32 2
+; AVX512-NEXT:    [[TMP5:%.*]] = extractelement <8 x double> [[TMP1]], i32 3
+; AVX512-NEXT:    [[R3:%.*]] = insertelement <8 x double> [[R2]], double [[TMP5]], i32 3
+; AVX512-NEXT:    [[TMP6:%.*]] = extractelement <8 x double> [[TMP1]], i32 4
+; AVX512-NEXT:    [[R4:%.*]] = insertelement <8 x double> [[R3]], double [[TMP6]], i32 4
+; AVX512-NEXT:    [[TMP7:%.*]] = extractelement <8 x double> [[TMP1]], i32 5
+; AVX512-NEXT:    [[R5:%.*]] = insertelement <8 x double> [[R4]], double [[TMP7]], i32 5
+; AVX512-NEXT:    [[TMP8:%.*]] = extractelement <8 x double> [[TMP1]], i32 6
+; AVX512-NEXT:    [[R6:%.*]] = insertelement <8 x double> [[R5]], double [[TMP8]], i32 6
+; AVX512-NEXT:    [[TMP9:%.*]] = extractelement <8 x double> [[TMP1]], i32 7
+; AVX512-NEXT:    [[R7:%.*]] = insertelement <8 x double> [[R6]], double [[TMP9]], i32 7
+; AVX512-NEXT:    ret <8 x double> [[R7]]
+;
+  %a0 = extractelement <8 x double> %a, i32 0
+  %a1 = extractelement <8 x double> %a, i32 1
+  %a2 = extractelement <8 x double> %a, i32 2
+  %a3 = extractelement <8 x double> %a, i32 3
+  %a4 = extractelement <8 x double> %a, i32 4
+  %a5 = extractelement <8 x double> %a, i32 5
+  %a6 = extractelement <8 x double> %a, i32 6
+  %a7 = extractelement <8 x double> %a, i32 7
+  %b0 = extractelement <8 x double> %b, i32 0
+  %b1 = extractelement <8 x double> %b, i32 1
+  %b2 = extractelement <8 x double> %b, i32 2
+  %b3 = extractelement <8 x double> %b, i32 3
+  %b4 = extractelement <8 x double> %b, i32 4
+  %b5 = extractelement <8 x double> %b, i32 5
+  %b6 = extractelement <8 x double> %b, i32 6
+  %b7 = extractelement <8 x double> %b, i32 7
+  %c0 = fdiv double %a0, %b0
+  %c1 = fdiv double %a1, %b1
+  %c2 = fdiv double %a2, %b2
+  %c3 = fdiv double %a3, %b3
+  %c4 = fdiv double %a4, %b4
+  %c5 = fdiv double %a5, %b5
+  %c6 = fdiv double %a6, %b6
+  %c7 = fdiv double %a7, %b7
+  %r0 = insertelement <8 x double> poison, double %c0, i32 0
+  %r1 = insertelement <8 x double> %r0,   double %c1, i32 1
+  %r2 = insertelement <8 x double> %r1,   double %c2, i32 2
+  %r3 = insertelement <8 x double> %r2,   double %c3, i32 3
+  %r4 = insertelement <8 x double> %r3,   double %c4, i32 4
+  %r5 = insertelement <8 x double> %r4,   double %c5, i32 5
+  %r6 = insertelement <8 x double> %r5,   double %c6, i32 6
+  %r7 = insertelement <8 x double> %r6,   double %c7, i32 7
+  ret <8 x double> %r7
+}
+
+define <16 x float> @buildvector_add_16f32(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @buildvector_add_16f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <16 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <16 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <16 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <16 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <16 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <16 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <16 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <16 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <16 x float> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <16 x float> [[R3]], float [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <16 x float> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <16 x float> [[R4]], float [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <16 x float> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <16 x float> [[R5]], float [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <16 x float> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <16 x float> [[R6]], float [[TMP9]], i32 7
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <16 x float> [[TMP1]], i32 8
+; CHECK-NEXT:    [[R8:%.*]] = insertelement <16 x float> [[R7]], float [[TMP10]], i32 8
+; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <16 x float> [[TMP1]], i32 9
+; CHECK-NEXT:    [[R9:%.*]] = insertelement <16 x float> [[R8]], float [[TMP11]], i32 9
+; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <16 x float> [[TMP1]], i32 10
+; CHECK-NEXT:    [[R10:%.*]] = insertelement <16 x float> [[R9]], float [[TMP12]], i32 10
+; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <16 x float> [[TMP1]], i32 11
+; CHECK-NEXT:    [[R11:%.*]] = insertelement <16 x float> [[R10]], float [[TMP13]], i32 11
+; CHECK-NEXT:    [[TMP14:%.*]] = extractelement <16 x float> [[TMP1]], i32 12
+; CHECK-NEXT:    [[R12:%.*]] = insertelement <16 x float> [[R11]], float [[TMP14]], i32 12
+; CHECK-NEXT:    [[TMP15:%.*]] = extractelement <16 x float> [[TMP1]], i32 13
+; CHECK-NEXT:    [[R13:%.*]] = insertelement <16 x float> [[R12]], float [[TMP15]], i32 13
+; CHECK-NEXT:    [[TMP16:%.*]] = extractelement <16 x float> [[TMP1]], i32 14
+; CHECK-NEXT:    [[R14:%.*]] = insertelement <16 x float> [[R13]], float [[TMP16]], i32 14
+; CHECK-NEXT:    [[TMP17:%.*]] = extractelement <16 x float> [[TMP1]], i32 15
+; CHECK-NEXT:    [[R15:%.*]] = insertelement <16 x float> [[R14]], float [[TMP17]], i32 15
+; CHECK-NEXT:    ret <16 x float> [[R15]]
+;
+  %a0  = extractelement <16 x float> %a, i32 0
+  %a1  = extractelement <16 x float> %a, i32 1
+  %a2  = extractelement <16 x float> %a, i32 2
+  %a3  = extractelement <16 x float> %a, i32 3
+  %a4  = extractelement <16 x float> %a, i32 4
+  %a5  = extractelement <16 x float> %a, i32 5
+  %a6  = extractelement <16 x float> %a, i32 6
+  %a7  = extractelement <16 x float> %a, i32 7
+  %a8  = extractelement <16 x float> %a, i32 8
+  %a9  = extractelement <16 x float> %a, i32 9
+  %a10 = extractelement <16 x float> %a, i32 10
+  %a11 = extractelement <16 x float> %a, i32 11
+  %a12 = extractelement <16 x float> %a, i32 12
+  %a13 = extractelement <16 x float> %a, i32 13
+  %a14 = extractelement <16 x float> %a, i32 14
+  %a15 = extractelement <16 x float> %a, i32 15
+  %b0  = extractelement <16 x float> %b, i32 0
+  %b1  = extractelement <16 x float> %b, i32 1
+  %b2  = extractelement <16 x float> %b, i32 2
+  %b3  = extractelement <16 x float> %b, i32 3
+  %b4  = extractelement <16 x float> %b, i32 4
+  %b5  = extractelement <16 x float> %b, i32 5
+  %b6  = extractelement <16 x float> %b, i32 6
+  %b7  = extractelement <16 x float> %b, i32 7
+  %b8  = extractelement <16 x float> %b, i32 8
+  %b9  = extractelement <16 x float> %b, i32 9
+  %b10 = extractelement <16 x float> %b, i32 10
+  %b11 = extractelement <16 x float> %b, i32 11
+  %b12 = extractelement <16 x float> %b, i32 12
+  %b13 = extractelement <16 x float> %b, i32 13
+  %b14 = extractelement <16 x float> %b, i32 14
+  %b15 = extractelement <16 x float> %b, i32 15
+  %c0  = fadd float %a0 , %b0
+  %c1  = fadd float %a1 , %b1
+  %c2  = fadd float %a2 , %b2
+  %c3  = fadd float %a3 , %b3
+  %c4  = fadd float %a4 , %b4
+  %c5  = fadd float %a5 , %b5
+  %c6  = fadd float %a6 , %b6
+  %c7  = fadd float %a7 , %b7
+  %c8  = fadd float %a8 , %b8
+  %c9  = fadd float %a9 , %b9
+  %c10 = fadd float %a10, %b10
+  %c11 = fadd float %a11, %b11
+  %c12 = fadd float %a12, %b12
+  %c13 = fadd float %a13, %b13
+  %c14 = fadd float %a14, %b14
+  %c15 = fadd float %a15, %b15
+  %r0  = insertelement <16 x float> poison, float %c0 , i32 0
+  %r1  = insertelement <16 x float> %r0 ,  float %c1 , i32 1
+  %r2  = insertelement <16 x float> %r1 ,  float %c2 , i32 2
+  %r3  = insertelement <16 x float> %r2 ,  float %c3 , i32 3
+  %r4  = insertelement <16 x float> %r3 ,  float %c4 , i32 4
+  %r5  = insertelement <16 x float> %r4 ,  float %c5 , i32 5
+  %r6  = insertelement <16 x float> %r5 ,  float %c6 , i32 6
+  %r7  = insertelement <16 x float> %r6 ,  float %c7 , i32 7
+  %r8  = insertelement <16 x float> %r7 ,  float %c8 , i32 8
+  %r9  = insertelement <16 x float> %r8 ,  float %c9 , i32 9
+  %r10 = insertelement <16 x float> %r9 ,  float %c10, i32 10
+  %r11 = insertelement <16 x float> %r10,  float %c11, i32 11
+  %r12 = insertelement <16 x float> %r11,  float %c12, i32 12
+  %r13 = insertelement <16 x float> %r12,  float %c13, i32 13
+  %r14 = insertelement <16 x float> %r13,  float %c14, i32 14
+  %r15 = insertelement <16 x float> %r14,  float %c15, i32 15
+  ret <16 x float> %r15
+}
+
+define <16 x float> @buildvector_sub_16f32(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @buildvector_sub_16f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <16 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <16 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <16 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <16 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <16 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <16 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <16 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <16 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <16 x float> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <16 x float> [[R3]], float [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <16 x float> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <16 x float> [[R4]], float [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <16 x float> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <16 x float> [[R5]], float [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <16 x float> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <16 x float> [[R6]], float [[TMP9]], i32 7
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <16 x float> [[TMP1]], i32 8
+; CHECK-NEXT:    [[R8:%.*]] = insertelement <16 x float> [[R7]], float [[TMP10]], i32 8
+; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <16 x float> [[TMP1]], i32 9
+; CHECK-NEXT:    [[R9:%.*]] = insertelement <16 x float> [[R8]], float [[TMP11]], i32 9
+; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <16 x float> [[TMP1]], i32 10
+; CHECK-NEXT:    [[R10:%.*]] = insertelement <16 x float> [[R9]], float [[TMP12]], i32 10
+; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <16 x float> [[TMP1]], i32 11
+; CHECK-NEXT:    [[R11:%.*]] = insertelement <16 x float> [[R10]], float [[TMP13]], i32 11
+; CHECK-NEXT:    [[TMP14:%.*]] = extractelement <16 x float> [[TMP1]], i32 12
+; CHECK-NEXT:    [[R12:%.*]] = insertelement <16 x float> [[R11]], float [[TMP14]], i32 12
+; CHECK-NEXT:    [[TMP15:%.*]] = extractelement <16 x float> [[TMP1]], i32 13
+; CHECK-NEXT:    [[R13:%.*]] = insertelement <16 x float> [[R12]], float [[TMP15]], i32 13
+; CHECK-NEXT:    [[TMP16:%.*]] = extractelement <16 x float> [[TMP1]], i32 14
+; CHECK-NEXT:    [[R14:%.*]] = insertelement <16 x float> [[R13]], float [[TMP16]], i32 14
+; CHECK-NEXT:    [[TMP17:%.*]] = extractelement <16 x float> [[TMP1]], i32 15
+; CHECK-NEXT:    [[R15:%.*]] = insertelement <16 x float> [[R14]], float [[TMP17]], i32 15
+; CHECK-NEXT:    ret <16 x float> [[R15]]
+;
+  %a0  = extractelement <16 x float> %a, i32 0
+  %a1  = extractelement <16 x float> %a, i32 1
+  %a2  = extractelement <16 x float> %a, i32 2
+  %a3  = extractelement <16 x float> %a, i32 3
+  %a4  = extractelement <16 x float> %a, i32 4
+  %a5  = extractelement <16 x float> %a, i32 5
+  %a6  = extractelement <16 x float> %a, i32 6
+  %a7  = extractelement <16 x float> %a, i32 7
+  %a8  = extractelement <16 x float> %a, i32 8
+  %a9  = extractelement <16 x float> %a, i32 9
+  %a10 = extractelement <16 x float> %a, i32 10
+  %a11 = extractelement <16 x float> %a, i32 11
+  %a12 = extractelement <16 x float> %a, i32 12
+  %a13 = extractelement <16 x float> %a, i32 13
+  %a14 = extractelement <16 x float> %a, i32 14
+  %a15 = extractelement <16 x float> %a, i32 15
+  %b0  = extractelement <16 x float> %b, i32 0
+  %b1  = extractelement <16 x float> %b, i32 1
+  %b2  = extractelement <16 x float> %b, i32 2
+  %b3  = extractelement <16 x float> %b, i32 3
+  %b4  = extractelement <16 x float> %b, i32 4
+  %b5  = extractelement <16 x float> %b, i32 5
+  %b6  = extractelement <16 x float> %b, i32 6
+  %b7  = extractelement <16 x float> %b, i32 7
+  %b8  = extractelement <16 x float> %b, i32 8
+  %b9  = extractelement <16 x float> %b, i32 9
+  %b10 = extractelement <16 x float> %b, i32 10
+  %b11 = extractelement <16 x float> %b, i32 11
+  %b12 = extractelement <16 x float> %b, i32 12
+  %b13 = extractelement <16 x float> %b, i32 13
+  %b14 = extractelement <16 x float> %b, i32 14
+  %b15 = extractelement <16 x float> %b, i32 15
+  %c0  = fsub float %a0 , %b0
+  %c1  = fsub float %a1 , %b1
+  %c2  = fsub float %a2 , %b2
+  %c3  = fsub float %a3 , %b3
+  %c4  = fsub float %a4 , %b4
+  %c5  = fsub float %a5 , %b5
+  %c6  = fsub float %a6 , %b6
+  %c7  = fsub float %a7 , %b7
+  %c8  = fsub float %a8 , %b8
+  %c9  = fsub float %a9 , %b9
+  %c10 = fsub float %a10, %b10
+  %c11 = fsub float %a11, %b11
+  %c12 = fsub float %a12, %b12
+  %c13 = fsub float %a13, %b13
+  %c14 = fsub float %a14, %b14
+  %c15 = fsub float %a15, %b15
+  %r0  = insertelement <16 x float> poison, float %c0 , i32 0
+  %r1  = insertelement <16 x float> %r0 ,  float %c1 , i32 1
+  %r2  = insertelement <16 x float> %r1 ,  float %c2 , i32 2
+  %r3  = insertelement <16 x float> %r2 ,  float %c3 , i32 3
+  %r4  = insertelement <16 x float> %r3 ,  float %c4 , i32 4
+  %r5  = insertelement <16 x float> %r4 ,  float %c5 , i32 5
+  %r6  = insertelement <16 x float> %r5 ,  float %c6 , i32 6
+  %r7  = insertelement <16 x float> %r6 ,  float %c7 , i32 7
+  %r8  = insertelement <16 x float> %r7 ,  float %c8 , i32 8
+  %r9  = insertelement <16 x float> %r8 ,  float %c9 , i32 9
+  %r10 = insertelement <16 x float> %r9 ,  float %c10, i32 10
+  %r11 = insertelement <16 x float> %r10,  float %c11, i32 11
+  %r12 = insertelement <16 x float> %r11,  float %c12, i32 12
+  %r13 = insertelement <16 x float> %r12,  float %c13, i32 13
+  %r14 = insertelement <16 x float> %r13,  float %c14, i32 14
+  %r15 = insertelement <16 x float> %r14,  float %c15, i32 15
+  ret <16 x float> %r15
+}
+
+define <16 x float> @buildvector_mul_16f32(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @buildvector_mul_16f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <16 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <16 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <16 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <16 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <16 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <16 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <16 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <16 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <16 x float> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <16 x float> [[R3]], float [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <16 x float> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <16 x float> [[R4]], float [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <16 x float> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <16 x float> [[R5]], float [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <16 x float> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <16 x float> [[R6]], float [[TMP9]], i32 7
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <16 x float> [[TMP1]], i32 8
+; CHECK-NEXT:    [[R8:%.*]] = insertelement <16 x float> [[R7]], float [[TMP10]], i32 8
+; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <16 x float> [[TMP1]], i32 9
+; CHECK-NEXT:    [[R9:%.*]] = insertelement <16 x float> [[R8]], float [[TMP11]], i32 9
+; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <16 x float> [[TMP1]], i32 10
+; CHECK-NEXT:    [[R10:%.*]] = insertelement <16 x float> [[R9]], float [[TMP12]], i32 10
+; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <16 x float> [[TMP1]], i32 11
+; CHECK-NEXT:    [[R11:%.*]] = insertelement <16 x float> [[R10]], float [[TMP13]], i32 11
+; CHECK-NEXT:    [[TMP14:%.*]] = extractelement <16 x float> [[TMP1]], i32 12
+; CHECK-NEXT:    [[R12:%.*]] = insertelement <16 x float> [[R11]], float [[TMP14]], i32 12
+; CHECK-NEXT:    [[TMP15:%.*]] = extractelement <16 x float> [[TMP1]], i32 13
+; CHECK-NEXT:    [[R13:%.*]] = insertelement <16 x float> [[R12]], float [[TMP15]], i32 13
+; CHECK-NEXT:    [[TMP16:%.*]] = extractelement <16 x float> [[TMP1]], i32 14
+; CHECK-NEXT:    [[R14:%.*]] = insertelement <16 x float> [[R13]], float [[TMP16]], i32 14
+; CHECK-NEXT:    [[TMP17:%.*]] = extractelement <16 x float> [[TMP1]], i32 15
+; CHECK-NEXT:    [[R15:%.*]] = insertelement <16 x float> [[R14]], float [[TMP17]], i32 15
+; CHECK-NEXT:    ret <16 x float> [[R15]]
+;
+  %a0  = extractelement <16 x float> %a, i32 0
+  %a1  = extractelement <16 x float> %a, i32 1
+  %a2  = extractelement <16 x float> %a, i32 2
+  %a3  = extractelement <16 x float> %a, i32 3
+  %a4  = extractelement <16 x float> %a, i32 4
+  %a5  = extractelement <16 x float> %a, i32 5
+  %a6  = extractelement <16 x float> %a, i32 6
+  %a7  = extractelement <16 x float> %a, i32 7
+  %a8  = extractelement <16 x float> %a, i32 8
+  %a9  = extractelement <16 x float> %a, i32 9
+  %a10 = extractelement <16 x float> %a, i32 10
+  %a11 = extractelement <16 x float> %a, i32 11
+  %a12 = extractelement <16 x float> %a, i32 12
+  %a13 = extractelement <16 x float> %a, i32 13
+  %a14 = extractelement <16 x float> %a, i32 14
+  %a15 = extractelement <16 x float> %a, i32 15
+  %b0  = extractelement <16 x float> %b, i32 0
+  %b1  = extractelement <16 x float> %b, i32 1
+  %b2  = extractelement <16 x float> %b, i32 2
+  %b3  = extractelement <16 x float> %b, i32 3
+  %b4  = extractelement <16 x float> %b, i32 4
+  %b5  = extractelement <16 x float> %b, i32 5
+  %b6  = extractelement <16 x float> %b, i32 6
+  %b7  = extractelement <16 x float> %b, i32 7
+  %b8  = extractelement <16 x float> %b, i32 8
+  %b9  = extractelement <16 x float> %b, i32 9
+  %b10 = extractelement <16 x float> %b, i32 10
+  %b11 = extractelement <16 x float> %b, i32 11
+  %b12 = extractelement <16 x float> %b, i32 12
+  %b13 = extractelement <16 x float> %b, i32 13
+  %b14 = extractelement <16 x float> %b, i32 14
+  %b15 = extractelement <16 x float> %b, i32 15
+  %c0  = fmul float %a0 , %b0
+  %c1  = fmul float %a1 , %b1
+  %c2  = fmul float %a2 , %b2
+  %c3  = fmul float %a3 , %b3
+  %c4  = fmul float %a4 , %b4
+  %c5  = fmul float %a5 , %b5
+  %c6  = fmul float %a6 , %b6
+  %c7  = fmul float %a7 , %b7
+  %c8  = fmul float %a8 , %b8
+  %c9  = fmul float %a9 , %b9
+  %c10 = fmul float %a10, %b10
+  %c11 = fmul float %a11, %b11
+  %c12 = fmul float %a12, %b12
+  %c13 = fmul float %a13, %b13
+  %c14 = fmul float %a14, %b14
+  %c15 = fmul float %a15, %b15
+  %r0  = insertelement <16 x float> poison, float %c0 , i32 0
+  %r1  = insertelement <16 x float> %r0 ,  float %c1 , i32 1
+  %r2  = insertelement <16 x float> %r1 ,  float %c2 , i32 2
+  %r3  = insertelement <16 x float> %r2 ,  float %c3 , i32 3
+  %r4  = insertelement <16 x float> %r3 ,  float %c4 , i32 4
+  %r5  = insertelement <16 x float> %r4 ,  float %c5 , i32 5
+  %r6  = insertelement <16 x float> %r5 ,  float %c6 , i32 6
+  %r7  = insertelement <16 x float> %r6 ,  float %c7 , i32 7
+  %r8  = insertelement <16 x float> %r7 ,  float %c8 , i32 8
+  %r9  = insertelement <16 x float> %r8 ,  float %c9 , i32 9
+  %r10 = insertelement <16 x float> %r9 ,  float %c10, i32 10
+  %r11 = insertelement <16 x float> %r10,  float %c11, i32 11
+  %r12 = insertelement <16 x float> %r11,  float %c12, i32 12
+  %r13 = insertelement <16 x float> %r12,  float %c13, i32 13
+  %r14 = insertelement <16 x float> %r13,  float %c14, i32 14
+  %r15 = insertelement <16 x float> %r14,  float %c15, i32 15
+  ret <16 x float> %r15
+}
+
+define <16 x float> @buildvector_div_16f32(<16 x float> %a, <16 x float> %b) {
+; CHECK-LABEL: @buildvector_div_16f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = fdiv <16 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <16 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[R0:%.*]] = insertelement <16 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <16 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[R1:%.*]] = insertelement <16 x float> [[R0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <16 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[R2:%.*]] = insertelement <16 x float> [[R1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <16 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[R3:%.*]] = insertelement <16 x float> [[R2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <16 x float> [[TMP1]], i32 4
+; CHECK-NEXT:    [[R4:%.*]] = insertelement <16 x float> [[R3]], float [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <16 x float> [[TMP1]], i32 5
+; CHECK-NEXT:    [[R5:%.*]] = insertelement <16 x float> [[R4]], float [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <16 x float> [[TMP1]], i32 6
+; CHECK-NEXT:    [[R6:%.*]] = insertelement <16 x float> [[R5]], float [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <16 x float> [[TMP1]], i32 7
+; CHECK-NEXT:    [[R7:%.*]] = insertelement <16 x float> [[R6]], float [[TMP9]], i32 7
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <16 x float> [[TMP1]], i32 8
+; CHECK-NEXT:    [[R8:%.*]] = insertelement <16 x float> [[R7]], float [[TMP10]], i32 8
+; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <16 x float> [[TMP1]], i32 9
+; CHECK-NEXT:    [[R9:%.*]] = insertelement <16 x float> [[R8]], float [[TMP11]], i32 9
+; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <16 x float> [[TMP1]], i32 10
+; CHECK-NEXT:    [[R10:%.*]] = insertelement <16 x float> [[R9]], float [[TMP12]], i32 10
+; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <16 x float> [[TMP1]], i32 11
+; CHECK-NEXT:    [[R11:%.*]] = insertelement <16 x float> [[R10]], float [[TMP13]], i32 11
+; CHECK-NEXT:    [[TMP14:%.*]] = extractelement <16 x float> [[TMP1]], i32 12
+; CHECK-NEXT:    [[R12:%.*]] = insertelement <16 x float> [[R11]], float [[TMP14]], i32 12
+; CHECK-NEXT:    [[TMP15:%.*]] = extractelement <16 x float> [[TMP1]], i32 13
+; CHECK-NEXT:    [[R13:%.*]] = insertelement <16 x float> [[R12]], float [[TMP15]], i32 13
+; CHECK-NEXT:    [[TMP16:%.*]] = extractelement <16 x float> [[TMP1]], i32 14
+; CHECK-NEXT:    [[R14:%.*]] = insertelement <16 x float> [[R13]], float [[TMP16]], i32 14
+; CHECK-NEXT:    [[TMP17:%.*]] = extractelement <16 x float> [[TMP1]], i32 15
+; CHECK-NEXT:    [[R15:%.*]] = insertelement <16 x float> [[R14]], float [[TMP17]], i32 15
+; CHECK-NEXT:    ret <16 x float> [[R15]]
+;
+  %a0  = extractelement <16 x float> %a, i32 0
+  %a1  = extractelement <16 x float> %a, i32 1
+  %a2  = extractelement <16 x float> %a, i32 2
+  %a3  = extractelement <16 x float> %a, i32 3
+  %a4  = extractelement <16 x float> %a, i32 4
+  %a5  = extractelement <16 x float> %a, i32 5
+  %a6  = extractelement <16 x float> %a, i32 6
+  %a7  = extractelement <16 x float> %a, i32 7
+  %a8  = extractelement <16 x float> %a, i32 8
+  %a9  = extractelement <16 x float> %a, i32 9
+  %a10 = extractelement <16 x float> %a, i32 10
+  %a11 = extractelement <16 x float> %a, i32 11
+  %a12 = extractelement <16 x float> %a, i32 12
+  %a13 = extractelement <16 x float> %a, i32 13
+  %a14 = extractelement <16 x float> %a, i32 14
+  %a15 = extractelement <16 x float> %a, i32 15
+  %b0  = extractelement <16 x float> %b, i32 0
+  %b1  = extractelement <16 x float> %b, i32 1
+  %b2  = extractelement <16 x float> %b, i32 2
+  %b3  = extractelement <16 x float> %b, i32 3
+  %b4  = extractelement <16 x float> %b, i32 4
+  %b5  = extractelement <16 x float> %b, i32 5
+  %b6  = extractelement <16 x float> %b, i32 6
+  %b7  = extractelement <16 x float> %b, i32 7
+  %b8  = extractelement <16 x float> %b, i32 8
+  %b9  = extractelement <16 x float> %b, i32 9
+  %b10 = extractelement <16 x float> %b, i32 10
+  %b11 = extractelement <16 x float> %b, i32 11
+  %b12 = extractelement <16 x float> %b, i32 12
+  %b13 = extractelement <16 x float> %b, i32 13
+  %b14 = extractelement <16 x float> %b, i32 14
+  %b15 = extractelement <16 x float> %b, i32 15
+  %c0  = fdiv float %a0 , %b0
+  %c1  = fdiv float %a1 , %b1
+  %c2  = fdiv float %a2 , %b2
+  %c3  = fdiv float %a3 , %b3
+  %c4  = fdiv float %a4 , %b4
+  %c5  = fdiv float %a5 , %b5
+  %c6  = fdiv float %a6 , %b6
+  %c7  = fdiv float %a7 , %b7
+  %c8  = fdiv float %a8 , %b8
+  %c9  = fdiv float %a9 , %b9
+  %c10 = fdiv float %a10, %b10
+  %c11 = fdiv float %a11, %b11
+  %c12 = fdiv float %a12, %b12
+  %c13 = fdiv float %a13, %b13
+  %c14 = fdiv float %a14, %b14
+  %c15 = fdiv float %a15, %b15
+  %r0  = insertelement <16 x float> poison, float %c0 , i32 0
+  %r1  = insertelement <16 x float> %r0 ,  float %c1 , i32 1
+  %r2  = insertelement <16 x float> %r1 ,  float %c2 , i32 2
+  %r3  = insertelement <16 x float> %r2 ,  float %c3 , i32 3
+  %r4  = insertelement <16 x float> %r3 ,  float %c4 , i32 4
+  %r5  = insertelement <16 x float> %r4 ,  float %c5 , i32 5
+  %r6  = insertelement <16 x float> %r5 ,  float %c6 , i32 6
+  %r7  = insertelement <16 x float> %r6 ,  float %c7 , i32 7
+  %r8  = insertelement <16 x float> %r7 ,  float %c8 , i32 8
+  %r9  = insertelement <16 x float> %r8 ,  float %c9 , i32 9
+  %r10 = insertelement <16 x float> %r9 ,  float %c10, i32 10
+  %r11 = insertelement <16 x float> %r10,  float %c11, i32 11
+  %r12 = insertelement <16 x float> %r11,  float %c12, i32 12
+  %r13 = insertelement <16 x float> %r12,  float %c13, i32 13
+  %r14 = insertelement <16 x float> %r13,  float %c14, i32 14
+  %r15 = insertelement <16 x float> %r14,  float %c15, i32 15
+  ret <16 x float> %r15
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
new file mode 100644
index 0000000000000..68c5bd8505900
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
@@ -0,0 +1,200 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -instcombine | FileCheck %s
+
+define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @g(
+; CHECK-NEXT:    [[X0:%.*]] = extractelement <2 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[Y1:%.*]] = extractelement <2 x i8> [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[X0X0:%.*]] = mul i8 [[X0]], [[X0]]
+; CHECK-NEXT:    [[Y1Y1:%.*]] = mul i8 [[Y1]], [[Y1]]
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <2 x i8> poison, i8 [[X0X0]], i32 0
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <2 x i8> [[INS1]], i8 [[Y1Y1]], i32 1
+; CHECK-NEXT:    ret <2 x i8> [[INS2]]
+;
+  %x0 = extractelement <2 x i8> %x, i32 0
+  %y1 = extractelement <2 x i8> %y, i32 1
+  %x0x0 = mul i8 %x0, %x0
+  %y1y1 = mul i8 %y1, %y1
+  %ins1 = insertelement <2 x i8> poison, i8 %x0x0, i32 0
+  %ins2 = insertelement <2 x i8> %ins1, i8 %y1y1, i32 1
+  ret <2 x i8> %ins2
+}
+
+define <4 x i8> @h(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @h(
+; CHECK-NEXT:    [[X0:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[X3:%.*]] = extractelement <4 x i8> [[X]], i32 3
+; CHECK-NEXT:    [[Y1:%.*]] = extractelement <4 x i8> [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[Y2:%.*]] = extractelement <4 x i8> [[Y]], i32 2
+; CHECK-NEXT:    [[X0X0:%.*]] = mul i8 [[X0]], [[X0]]
+; CHECK-NEXT:    [[X3X3:%.*]] = mul i8 [[X3]], [[X3]]
+; CHECK-NEXT:    [[Y1Y1:%.*]] = mul i8 [[Y1]], [[Y1]]
+; CHECK-NEXT:    [[Y2Y2:%.*]] = mul i8 [[Y2]], [[Y2]]
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <4 x i8> poison, i8 [[X0X0]], i32 0
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x i8> [[INS1]], i8 [[X3X3]], i32 1
+; CHECK-NEXT:    [[INS3:%.*]] = insertelement <4 x i8> [[INS2]], i8 [[Y1Y1]], i32 2
+; CHECK-NEXT:    [[INS4:%.*]] = insertelement <4 x i8> [[INS3]], i8 [[Y2Y2]], i32 3
+; CHECK-NEXT:    ret <4 x i8> [[INS4]]
+;
+  %x0 = extractelement <4 x i8> %x, i32 0
+  %x3 = extractelement <4 x i8> %x, i32 3
+  %y1 = extractelement <4 x i8> %y, i32 1
+  %y2 = extractelement <4 x i8> %y, i32 2
+  %x0x0 = mul i8 %x0, %x0
+  %x3x3 = mul i8 %x3, %x3
+  %y1y1 = mul i8 %y1, %y1
+  %y2y2 = mul i8 %y2, %y2
+  %ins1 = insertelement <4 x i8> poison, i8 %x0x0, i32 0
+  %ins2 = insertelement <4 x i8> %ins1, i8 %x3x3, i32 1
+  %ins3 = insertelement <4 x i8> %ins2, i8 %y1y1, i32 2
+  %ins4 = insertelement <4 x i8> %ins3, i8 %y2y2, i32 3
+  ret <4 x i8> %ins4
+}
+
+define <4 x i8> @h_undef(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @h_undef(
+; CHECK-NEXT:    [[X3:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 3
+; CHECK-NEXT:    [[Y1:%.*]] = extractelement <4 x i8> [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[Y2:%.*]] = extractelement <4 x i8> [[Y]], i32 2
+; CHECK-NEXT:    [[X3X3:%.*]] = mul i8 [[X3]], [[X3]]
+; CHECK-NEXT:    [[Y1Y1:%.*]] = mul i8 [[Y1]], [[Y1]]
+; CHECK-NEXT:    [[Y2Y2:%.*]] = mul i8 [[Y2]], [[Y2]]
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <4 x i8> <i8 undef, i8 poison, i8 poison, i8 poison>, i8 [[X3X3]], i32 1
+; CHECK-NEXT:    [[INS3:%.*]] = insertelement <4 x i8> [[INS2]], i8 [[Y1Y1]], i32 2
+; CHECK-NEXT:    [[INS4:%.*]] = insertelement <4 x i8> [[INS3]], i8 [[Y2Y2]], i32 3
+; CHECK-NEXT:    ret <4 x i8> [[INS4]]
+;
+  %x0 = extractelement <4 x i8> undef, i32 0
+  %x3 = extractelement <4 x i8> %x, i32 3
+  %y1 = extractelement <4 x i8> %y, i32 1
+  %y2 = extractelement <4 x i8> %y, i32 2
+  %x0x0 = mul i8 %x0, %x0
+  %x3x3 = mul i8 %x3, %x3
+  %y1y1 = mul i8 %y1, %y1
+  %y2y2 = mul i8 %y2, %y2
+  %ins1 = insertelement <4 x i8> poison, i8 %x0x0, i32 0
+  %ins2 = insertelement <4 x i8> %ins1, i8 %x3x3, i32 1
+  %ins3 = insertelement <4 x i8> %ins2, i8 %y1y1, i32 2
+  %ins4 = insertelement <4 x i8> %ins3, i8 %y2y2, i32 3
+  ret <4 x i8> %ins4
+}
+
+define i8 @i(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @i(
+; CHECK-NEXT:    [[X0:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[X3:%.*]] = extractelement <4 x i8> [[X]], i32 3
+; CHECK-NEXT:    [[Y1:%.*]] = extractelement <4 x i8> [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[Y2:%.*]] = extractelement <4 x i8> [[Y]], i32 2
+; CHECK-NEXT:    [[X0X0:%.*]] = mul i8 [[X0]], [[X0]]
+; CHECK-NEXT:    [[X3X3:%.*]] = mul i8 [[X3]], [[X3]]
+; CHECK-NEXT:    [[Y1Y1:%.*]] = mul i8 [[Y1]], [[Y1]]
+; CHECK-NEXT:    [[Y2Y2:%.*]] = mul i8 [[Y2]], [[Y2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X0X0]], [[X3X3]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[Y1Y1]], [[Y2Y2]]
+; CHECK-NEXT:    [[TMP3:%.*]] = add i8 [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret i8 [[TMP3]]
+;
+  %x0 = extractelement <4 x i8> %x, i32 0
+  %x3 = extractelement <4 x i8> %x, i32 3
+  %y1 = extractelement <4 x i8> %y, i32 1
+  %y2 = extractelement <4 x i8> %y, i32 2
+  %x0x0 = mul i8 %x0, %x0
+  %x3x3 = mul i8 %x3, %x3
+  %y1y1 = mul i8 %y1, %y1
+  %y2y2 = mul i8 %y2, %y2
+  %1 = add i8 %x0x0, %x3x3
+  %2 = add i8 %y1y1, %y2y2
+  %3 = add i8 %1, %2
+  ret i8 %3
+}
+
+define i8 @j(<4 x i8> %x, <4 x i8> %y) {
+; CHECK-LABEL: @j(
+; CHECK-NEXT:    [[X0:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[X3:%.*]] = extractelement <4 x i8> [[X]], i32 3
+; CHECK-NEXT:    [[Y1:%.*]] = extractelement <4 x i8> [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[Y2:%.*]] = extractelement <4 x i8> [[Y]], i32 2
+; CHECK-NEXT:    [[X0X0:%.*]] = mul i8 [[X0]], [[X0]]
+; CHECK-NEXT:    [[X3X3:%.*]] = mul i8 [[X3]], [[X3]]
+; CHECK-NEXT:    [[Y1Y1:%.*]] = mul i8 [[Y1]], [[Y1]]
+; CHECK-NEXT:    [[Y2Y2:%.*]] = mul i8 [[Y2]], [[Y2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X0X0]], [[X3X3]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[Y1Y1]], [[Y2Y2]]
+; CHECK-NEXT:    [[TMP3:%.*]] = sdiv i8 [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret i8 [[TMP3]]
+;
+  %x0 = extractelement <4 x i8> %x, i32 0
+  %x3 = extractelement <4 x i8> %x, i32 3
+  %y1 = extractelement <4 x i8> %y, i32 1
+  %y2 = extractelement <4 x i8> %y, i32 2
+  %x0x0 = mul i8 %x0, %x0
+  %x3x3 = mul i8 %x3, %x3
+  %y1y1 = mul i8 %y1, %y1
+  %y2y2 = mul i8 %y2, %y2
+  %1 = add i8 %x0x0, %x3x3
+  %2 = add i8 %y1y1, %y2y2
+  %3 = sdiv i8 %1, %2
+  ret i8 %3
+}
+
+define i8 @k(<4 x i8> %x) {
+; CHECK-LABEL: @k(
+; CHECK-NEXT:    [[X0:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[X3:%.*]] = extractelement <4 x i8> [[X]], i32 3
+; CHECK-NEXT:    [[X1:%.*]] = extractelement <4 x i8> [[X]], i32 1
+; CHECK-NEXT:    [[X2:%.*]] = extractelement <4 x i8> [[X]], i32 2
+; CHECK-NEXT:    [[X0X0:%.*]] = mul i8 [[X0]], [[X0]]
+; CHECK-NEXT:    [[X3X3:%.*]] = mul i8 [[X3]], [[X3]]
+; CHECK-NEXT:    [[X1X1:%.*]] = mul i8 [[X1]], [[X1]]
+; CHECK-NEXT:    [[X2X2:%.*]] = mul i8 [[X2]], [[X2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X0X0]], [[X3X3]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[X1X1]], [[X2X2]]
+; CHECK-NEXT:    [[TMP3:%.*]] = sdiv i8 [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret i8 [[TMP3]]
+;
+  %x0 = extractelement <4 x i8> %x, i32 0
+  %x3 = extractelement <4 x i8> %x, i32 3
+  %x1 = extractelement <4 x i8> %x, i32 1
+  %x2 = extractelement <4 x i8> %x, i32 2
+  %x0x0 = mul i8 %x0, %x0
+  %x3x3 = mul i8 %x3, %x3
+  %x1x1 = mul i8 %x1, %x1
+  %x2x2 = mul i8 %x2, %x2
+  %1 = add i8 %x0x0, %x3x3
+  %2 = add i8 %x1x1, %x2x2
+  %3 = sdiv i8 %1, %2
+  ret i8 %3
+}
+
+define i8 @k_bb(<4 x i8> %x) {
+; CHECK-LABEL: @k_bb(
+; CHECK-NEXT:    [[X0:%.*]] = extractelement <4 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    br label [[BB1:%.*]]
+; CHECK:       bb1:
+; CHECK-NEXT:    [[X3:%.*]] = extractelement <4 x i8> [[X]], i32 3
+; CHECK-NEXT:    [[X1:%.*]] = extractelement <4 x i8> [[X]], i32 1
+; CHECK-NEXT:    [[X2:%.*]] = extractelement <4 x i8> [[X]], i32 2
+; CHECK-NEXT:    [[X0X0:%.*]] = mul i8 [[X0]], [[X0]]
+; CHECK-NEXT:    [[X3X3:%.*]] = mul i8 [[X3]], [[X3]]
+; CHECK-NEXT:    [[X1X1:%.*]] = mul i8 [[X1]], [[X1]]
+; CHECK-NEXT:    [[X2X2:%.*]] = mul i8 [[X2]], [[X2]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X0X0]], [[X3X3]]
+; CHECK-NEXT:    [[TMP2:%.*]] = add i8 [[X1X1]], [[X2X2]]
+; CHECK-NEXT:    [[TMP3:%.*]] = sdiv i8 [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret i8 [[TMP3]]
+;
+  %x0 = extractelement <4 x i8> %x, i32 0
+  br label %bb1
+bb1:
+  %x3 = extractelement <4 x i8> %x, i32 3
+  %x1 = extractelement <4 x i8> %x, i32 1
+  %x2 = extractelement <4 x i8> %x, i32 2
+  %x0x0 = mul i8 %x0, %x0
+  %x3x3 = mul i8 %x3, %x3
+  %x1x1 = mul i8 %x1, %x1
+  %x2x2 = mul i8 %x2, %x2
+  %1 = add i8 %x0x0, %x3x3
+  %2 = add i8 %x1x1, %x2x2
+  %3 = sdiv i8 %1, %2
+  ret i8 %3
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll
new file mode 100644
index 0000000000000..c096a0bac7a9b
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/cmp_commute-inseltpoison.ll
@@ -0,0 +1,283 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+sse2 | FileCheck %s
+; RUN: opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64--- -mattr=+avx  | FileCheck %s
+
+;
+; Check that we can commute operands based on the predicate.
+;
+
+define <4 x i32> @icmp_eq_v4i32(<4 x i32> %a, i32* %b) {
+; CHECK-LABEL: @icmp_eq_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[B:%.*]] to <4 x i32>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq <4 x i32> [[TMP2]], [[A:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %p0 = getelementptr inbounds i32, i32* %b, i32 0
+  %p1 = getelementptr inbounds i32, i32* %b, i32 1
+  %p2 = getelementptr inbounds i32, i32* %b, i32 2
+  %p3 = getelementptr inbounds i32, i32* %b, i32 3
+  %b0 = load i32, i32* %p0, align 4
+  %b1 = load i32, i32* %p1, align 4
+  %b2 = load i32, i32* %p2, align 4
+  %b3 = load i32, i32* %p3, align 4
+  %c0 = icmp eq i32 %a0, %b0
+  %c1 = icmp eq i32 %b1, %a1
+  %c2 = icmp eq i32 %b2, %a2
+  %c3 = icmp eq i32 %a3, %b3
+  %d0 = insertelement <4 x i1> poison, i1 %c0, i32 0
+  %d1 = insertelement <4 x i1>   %d0, i1 %c1, i32 1
+  %d2 = insertelement <4 x i1>   %d1, i1 %c2, i32 2
+  %d3 = insertelement <4 x i1>   %d2, i1 %c3, i32 3
+  %r = sext <4 x i1> %d3 to <4 x i32>
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @icmp_ne_v4i32(<4 x i32> %a, i32* %b) {
+; CHECK-LABEL: @icmp_ne_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[B:%.*]] to <4 x i32>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], [[A:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %p0 = getelementptr inbounds i32, i32* %b, i32 0
+  %p1 = getelementptr inbounds i32, i32* %b, i32 1
+  %p2 = getelementptr inbounds i32, i32* %b, i32 2
+  %p3 = getelementptr inbounds i32, i32* %b, i32 3
+  %b0 = load i32, i32* %p0, align 4
+  %b1 = load i32, i32* %p1, align 4
+  %b2 = load i32, i32* %p2, align 4
+  %b3 = load i32, i32* %p3, align 4
+  %c0 = icmp ne i32 %a0, %b0
+  %c1 = icmp ne i32 %b1, %a1
+  %c2 = icmp ne i32 %b2, %a2
+  %c3 = icmp ne i32 %a3, %b3
+  %d0 = insertelement <4 x i1> poison, i1 %c0, i32 0
+  %d1 = insertelement <4 x i1>   %d0, i1 %c1, i32 1
+  %d2 = insertelement <4 x i1>   %d1, i1 %c2, i32 2
+  %d3 = insertelement <4 x i1>   %d2, i1 %c3, i32 3
+  %r = sext <4 x i1> %d3 to <4 x i32>
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @fcmp_oeq_v4i32(<4 x float> %a, float* %b) {
+; CHECK-LABEL: @fcmp_oeq_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = fcmp oeq <4 x float> [[TMP2]], [[A:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %p0 = getelementptr inbounds float, float* %b, i32 0
+  %p1 = getelementptr inbounds float, float* %b, i32 1
+  %p2 = getelementptr inbounds float, float* %b, i32 2
+  %p3 = getelementptr inbounds float, float* %b, i32 3
+  %b0 = load float, float* %p0, align 4
+  %b1 = load float, float* %p1, align 4
+  %b2 = load float, float* %p2, align 4
+  %b3 = load float, float* %p3, align 4
+  %c0 = fcmp oeq float %a0, %b0
+  %c1 = fcmp oeq float %b1, %a1
+  %c2 = fcmp oeq float %b2, %a2
+  %c3 = fcmp oeq float %a3, %b3
+  %d0 = insertelement <4 x i1> poison, i1 %c0, i32 0
+  %d1 = insertelement <4 x i1>   %d0, i1 %c1, i32 1
+  %d2 = insertelement <4 x i1>   %d1, i1 %c2, i32 2
+  %d3 = insertelement <4 x i1>   %d2, i1 %c3, i32 3
+  %r = sext <4 x i1> %d3 to <4 x i32>
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @fcmp_uno_v4i32(<4 x float> %a, float* %b) {
+; CHECK-LABEL: @fcmp_uno_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = fcmp uno <4 x float> [[TMP2]], [[A:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %p0 = getelementptr inbounds float, float* %b, i32 0
+  %p1 = getelementptr inbounds float, float* %b, i32 1
+  %p2 = getelementptr inbounds float, float* %b, i32 2
+  %p3 = getelementptr inbounds float, float* %b, i32 3
+  %b0 = load float, float* %p0, align 4
+  %b1 = load float, float* %p1, align 4
+  %b2 = load float, float* %p2, align 4
+  %b3 = load float, float* %p3, align 4
+  %c0 = fcmp uno float %a0, %b0
+  %c1 = fcmp uno float %b1, %a1
+  %c2 = fcmp uno float %b2, %a2
+  %c3 = fcmp uno float %a3, %b3
+  %d0 = insertelement <4 x i1> poison, i1 %c0, i32 0
+  %d1 = insertelement <4 x i1>   %d0, i1 %c1, i32 1
+  %d2 = insertelement <4 x i1>   %d1, i1 %c2, i32 2
+  %d3 = insertelement <4 x i1>   %d2, i1 %c3, i32 3
+  %r = sext <4 x i1> %d3 to <4 x i32>
+  ret <4 x i32> %r
+}
+
+;
+; Check that we can commute operands by swapping the predicate.
+;
+
+define <4 x i32> @icmp_sgt_slt_v4i32(<4 x i32> %a, i32* %b) {
+; CHECK-LABEL: @icmp_sgt_slt_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[B:%.*]] to <4 x i32>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt <4 x i32> [[TMP2]], [[A:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %p0 = getelementptr inbounds i32, i32* %b, i32 0
+  %p1 = getelementptr inbounds i32, i32* %b, i32 1
+  %p2 = getelementptr inbounds i32, i32* %b, i32 2
+  %p3 = getelementptr inbounds i32, i32* %b, i32 3
+  %b0 = load i32, i32* %p0, align 4
+  %b1 = load i32, i32* %p1, align 4
+  %b2 = load i32, i32* %p2, align 4
+  %b3 = load i32, i32* %p3, align 4
+  %c0 = icmp sgt i32 %a0, %b0
+  %c1 = icmp slt i32 %b1, %a1
+  %c2 = icmp slt i32 %b2, %a2
+  %c3 = icmp sgt i32 %a3, %b3
+  %d0 = insertelement <4 x i1> poison, i1 %c0, i32 0
+  %d1 = insertelement <4 x i1>   %d0, i1 %c1, i32 1
+  %d2 = insertelement <4 x i1>   %d1, i1 %c2, i32 2
+  %d3 = insertelement <4 x i1>   %d2, i1 %c3, i32 3
+  %r = sext <4 x i1> %d3 to <4 x i32>
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @icmp_uge_ule_v4i32(<4 x i32> %a, i32* %b) {
+; CHECK-LABEL: @icmp_uge_ule_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[B:%.*]] to <4 x i32>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp ule <4 x i32> [[TMP2]], [[A:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %p0 = getelementptr inbounds i32, i32* %b, i32 0
+  %p1 = getelementptr inbounds i32, i32* %b, i32 1
+  %p2 = getelementptr inbounds i32, i32* %b, i32 2
+  %p3 = getelementptr inbounds i32, i32* %b, i32 3
+  %b0 = load i32, i32* %p0, align 4
+  %b1 = load i32, i32* %p1, align 4
+  %b2 = load i32, i32* %p2, align 4
+  %b3 = load i32, i32* %p3, align 4
+  %c0 = icmp uge i32 %a0, %b0
+  %c1 = icmp ule i32 %b1, %a1
+  %c2 = icmp ule i32 %b2, %a2
+  %c3 = icmp uge i32 %a3, %b3
+  %d0 = insertelement <4 x i1> poison, i1 %c0, i32 0
+  %d1 = insertelement <4 x i1>   %d0, i1 %c1, i32 1
+  %d2 = insertelement <4 x i1>   %d1, i1 %c2, i32 2
+  %d3 = insertelement <4 x i1>   %d2, i1 %c3, i32 3
+  %r = sext <4 x i1> %d3 to <4 x i32>
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @fcmp_ogt_olt_v4i32(<4 x float> %a, float* %b) {
+; CHECK-LABEL: @fcmp_ogt_olt_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = fcmp olt <4 x float> [[TMP2]], [[A:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %p0 = getelementptr inbounds float, float* %b, i32 0
+  %p1 = getelementptr inbounds float, float* %b, i32 1
+  %p2 = getelementptr inbounds float, float* %b, i32 2
+  %p3 = getelementptr inbounds float, float* %b, i32 3
+  %b0 = load float, float* %p0, align 4
+  %b1 = load float, float* %p1, align 4
+  %b2 = load float, float* %p2, align 4
+  %b3 = load float, float* %p3, align 4
+  %c0 = fcmp ogt float %a0, %b0
+  %c1 = fcmp olt float %b1, %a1
+  %c2 = fcmp olt float %b2, %a2
+  %c3 = fcmp ogt float %a3, %b3
+  %d0 = insertelement <4 x i1> poison, i1 %c0, i32 0
+  %d1 = insertelement <4 x i1>   %d0, i1 %c1, i32 1
+  %d2 = insertelement <4 x i1>   %d1, i1 %c2, i32 2
+  %d3 = insertelement <4 x i1>   %d2, i1 %c3, i32 3
+  %r = sext <4 x i1> %d3 to <4 x i32>
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @fcmp_ord_uno_v4i32(<4 x float> %a, float* %b) {
+; CHECK-LABEL: @fcmp_ord_uno_v4i32(
+; CHECK-NEXT:    [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
+; CHECK-NEXT:    [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
+; CHECK-NEXT:    [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
+; CHECK-NEXT:    [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
+; CHECK-NEXT:    [[P1:%.*]] = getelementptr inbounds float, float* [[B:%.*]], i64 1
+; CHECK-NEXT:    [[P2:%.*]] = getelementptr inbounds float, float* [[B]], i64 2
+; CHECK-NEXT:    [[P3:%.*]] = getelementptr inbounds float, float* [[B]], i64 3
+; CHECK-NEXT:    [[B0:%.*]] = load float, float* [[B]], align 4
+; CHECK-NEXT:    [[B1:%.*]] = load float, float* [[P1]], align 4
+; CHECK-NEXT:    [[B2:%.*]] = load float, float* [[P2]], align 4
+; CHECK-NEXT:    [[B3:%.*]] = load float, float* [[P3]], align 4
+; CHECK-NEXT:    [[C0:%.*]] = fcmp ord float [[A0]], [[B0]]
+; CHECK-NEXT:    [[C1:%.*]] = fcmp uno float [[B1]], [[A1]]
+; CHECK-NEXT:    [[C2:%.*]] = fcmp uno float [[B2]], [[A2]]
+; CHECK-NEXT:    [[C3:%.*]] = fcmp ord float [[A3]], [[B3]]
+; CHECK-NEXT:    [[D0:%.*]] = insertelement <4 x i1> poison, i1 [[C0]], i32 0
+; CHECK-NEXT:    [[D1:%.*]] = insertelement <4 x i1> [[D0]], i1 [[C1]], i32 1
+; CHECK-NEXT:    [[D2:%.*]] = insertelement <4 x i1> [[D1]], i1 [[C2]], i32 2
+; CHECK-NEXT:    [[D3:%.*]] = insertelement <4 x i1> [[D2]], i1 [[C3]], i32 3
+; CHECK-NEXT:    [[R:%.*]] = sext <4 x i1> [[D3]] to <4 x i32>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %p0 = getelementptr inbounds float, float* %b, i32 0
+  %p1 = getelementptr inbounds float, float* %b, i32 1
+  %p2 = getelementptr inbounds float, float* %b, i32 2
+  %p3 = getelementptr inbounds float, float* %b, i32 3
+  %b0 = load float, float* %p0, align 4
+  %b1 = load float, float* %p1, align 4
+  %b2 = load float, float* %p2, align 4
+  %b3 = load float, float* %p3, align 4
+  %c0 = fcmp ord float %a0, %b0
+  %c1 = fcmp uno float %b1, %a1
+  %c2 = fcmp uno float %b2, %a2
+  %c3 = fcmp ord float %a3, %b3
+  %d0 = insertelement <4 x i1> poison, i1 %c0, i32 0
+  %d1 = insertelement <4 x i1>   %d0, i1 %c1, i32 1
+  %d2 = insertelement <4 x i1>   %d1, i1 %c2, i32 2
+  %d3 = insertelement <4 x i1>   %d2, i1 %c3, i32 3
+  %r = sext <4 x i1> %d3 to <4 x i32>
+  ret <4 x i32> %r
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll
new file mode 100644
index 0000000000000..348aed4a48e5a
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/crash_scheduling-inseltpoison.ll
@@ -0,0 +1,81 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -basic-aa -slp-vectorizer -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7 | FileCheck %s
+
+target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-apple-darwin13.3.0"
+
+define void @_foo(double %p1, double %p2, double %p3) #0 {
+; CHECK-LABEL: @_foo(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TAB1:%.*]] = alloca [256 x i32], align 16
+; CHECK-NEXT:    [[TAB2:%.*]] = alloca [256 x i32], align 16
+; CHECK-NEXT:    br label [[BB1:%.*]]
+; CHECK:       bb1:
+; CHECK-NEXT:    [[MUL19:%.*]] = fmul double [[P1:%.*]], 1.638400e+04
+; CHECK-NEXT:    [[MUL20:%.*]] = fmul double [[P3:%.*]], 1.638400e+04
+; CHECK-NEXT:    [[ADD:%.*]] = fadd double [[MUL20]], 8.192000e+03
+; CHECK-NEXT:    [[MUL21:%.*]] = fmul double [[P2:%.*]], 1.638400e+04
+; CHECK-NEXT:    br label [[FOR_BODY:%.*]]
+; CHECK:       for.body:
+; CHECK-NEXT:    [[INDVARS_IV266:%.*]] = phi i64 [ 0, [[BB1]] ], [ [[INDVARS_IV_NEXT267:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[T_0259:%.*]] = phi double [ 0.000000e+00, [[BB1]] ], [ [[ADD27:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[P3_ADDR_0258:%.*]] = phi double [ [[ADD]], [[BB1]] ], [ [[ADD28:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT:    [[VECINIT_I_I237:%.*]] = insertelement <2 x double> poison, double [[T_0259]], i32 0
+; CHECK-NEXT:    [[X13:%.*]] = tail call i32 @_xfn(<2 x double> [[VECINIT_I_I237]])
+; CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [256 x i32], [256 x i32]* [[TAB1]], i64 0, i64 [[INDVARS_IV266]]
+; CHECK-NEXT:    store i32 [[X13]], i32* [[ARRAYIDX]], align 4, [[TBAA0:!tbaa !.*]]
+; CHECK-NEXT:    [[VECINIT_I_I:%.*]] = insertelement <2 x double> poison, double [[P3_ADDR_0258]], i32 0
+; CHECK-NEXT:    [[X14:%.*]] = tail call i32 @_xfn(<2 x double> [[VECINIT_I_I]])
+; CHECK-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds [256 x i32], [256 x i32]* [[TAB2]], i64 0, i64 [[INDVARS_IV266]]
+; CHECK-NEXT:    store i32 [[X14]], i32* [[ARRAYIDX26]], align 4, [[TBAA0]]
+; CHECK-NEXT:    [[ADD27]] = fadd double [[MUL19]], [[T_0259]]
+; CHECK-NEXT:    [[ADD28]] = fadd double [[MUL21]], [[P3_ADDR_0258]]
+; CHECK-NEXT:    [[INDVARS_IV_NEXT267]] = add nuw nsw i64 [[INDVARS_IV266]], 1
+; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT267]], 256
+; CHECK-NEXT:    br i1 [[EXITCOND]], label [[RETURN:%.*]], label [[FOR_BODY]]
+; CHECK:       return:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %tab1 = alloca [256 x i32], align 16
+  %tab2 = alloca [256 x i32], align 16
+  br label %bb1
+
+
+bb1:
+  %mul19 = fmul double %p1, 1.638400e+04
+  %mul20 = fmul double %p3, 1.638400e+04
+  %add = fadd double %mul20, 8.192000e+03
+  %mul21 = fmul double %p2, 1.638400e+04
+  ; The SLPVectorizer crashed when scheduling this block after it inserted an
+  ; insertelement instruction (during vectorizing the for.body block) at this position.
+  br label %for.body
+
+for.body:
+  %indvars.iv266 = phi i64 [ 0, %bb1 ], [ %indvars.iv.next267, %for.body ]
+  %t.0259 = phi double [ 0.000000e+00, %bb1 ], [ %add27, %for.body ]
+  %p3.addr.0258 = phi double [ %add, %bb1 ], [ %add28, %for.body ]
+  %vecinit.i.i237 = insertelement <2 x double> poison, double %t.0259, i32 0
+  %x13 = tail call i32 @_xfn(<2 x double> %vecinit.i.i237) #2
+  %arrayidx = getelementptr inbounds [256 x i32], [256 x i32]* %tab1, i64 0, i64 %indvars.iv266
+  store i32 %x13, i32* %arrayidx, align 4, !tbaa !4
+  %vecinit.i.i = insertelement <2 x double> poison, double %p3.addr.0258, i32 0
+  %x14 = tail call i32 @_xfn(<2 x double> %vecinit.i.i) #2
+  %arrayidx26 = getelementptr inbounds [256 x i32], [256 x i32]* %tab2, i64 0, i64 %indvars.iv266
+  store i32 %x14, i32* %arrayidx26, align 4, !tbaa !4
+  %add27 = fadd double %mul19, %t.0259
+  %add28 = fadd double %mul21, %p3.addr.0258
+  %indvars.iv.next267 = add nuw nsw i64 %indvars.iv266, 1
+  %exitcond = icmp eq i64 %indvars.iv.next267, 256
+  br i1 %exitcond, label %return, label %for.body
+
+return:
+  ret void
+}
+
+declare i32 @_xfn(<2 x double>) #4
+
+!3 = !{!"int", !5, i64 0}
+!4 = !{!3, !3, i64 0}
+!5 = !{!"omnipotent char", !6, i64 0}
+!6 = !{!"Simple C/C++ TBAA"}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_load-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_load-inseltpoison.ll
new file mode 100644
index 0000000000000..45b65f1657861
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/external_user_jumbled_load-inseltpoison.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -S -mtriple=x86_64-unknown -mattr=+avx -slp-vectorizer | FileCheck %s
+
+@array = external global [20 x [13 x i32]]
+
+define void @hoge(i64 %idx, <4 x i32>* %sink) {
+; CHECK-LABEL: @hoge(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [20 x [13 x i32]], [20 x [13 x i32]]* @array, i64 0, i64 [[IDX:%.*]], i64 5
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [20 x [13 x i32]], [20 x [13 x i32]]* @array, i64 0, i64 [[IDX]], i64 6
+; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [20 x [13 x i32]], [20 x [13 x i32]]* @array, i64 0, i64 [[IDX]], i64 7
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [20 x [13 x i32]], [20 x [13 x i32]]* @array, i64 0, i64 [[IDX]], i64 8
+; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i32* [[TMP0]] to <4 x i32>*
+; CHECK-NEXT:    [[TMP5:%.*]] = load <4 x i32>, <4 x i32>* [[TMP4]], align 4
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[SHUFFLE]], i32 0
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x i32> poison, i32 [[TMP6]], i32 0
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[SHUFFLE]], i32 1
+; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <4 x i32> [[TMP7]], i32 [[TMP8]], i32 1
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <4 x i32> [[SHUFFLE]], i32 2
+; CHECK-NEXT:    [[TMP11:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP10]], i32 2
+; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <4 x i32> [[SHUFFLE]], i32 3
+; CHECK-NEXT:    [[TMP13:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP12]], i32 3
+; CHECK-NEXT:    store <4 x i32> [[TMP13]], <4 x i32>* [[SINK:%.*]], align 16
+; CHECK-NEXT:    ret void
+;
+bb:
+  %0 = getelementptr inbounds [20 x [13 x i32]], [20 x [13 x i32]]* @array, i64 0, i64 %idx, i64 5
+  %1 = getelementptr inbounds [20 x [13 x i32]], [20 x [13 x i32]]* @array, i64 0, i64 %idx, i64 6
+  %2 = getelementptr inbounds [20 x [13 x i32]], [20 x [13 x i32]]* @array, i64 0, i64 %idx, i64 7
+  %3 = getelementptr inbounds [20 x [13 x i32]], [20 x [13 x i32]]* @array, i64 0, i64 %idx, i64 8
+  %4 = load i32, i32* %1, align 4
+  %5 = insertelement <4 x i32> poison, i32 %4, i32 0
+  %6 = load i32, i32* %2, align 4
+  %7 = insertelement <4 x i32> %5, i32 %6, i32 1
+  %8 = load i32, i32* %3, align 4
+  %9 = insertelement <4 x i32> %7, i32 %8, i32 2
+  %10 = load i32, i32* %0, align 4
+  %11 = insertelement <4 x i32> %9, i32 %10, i32 3
+  store <4 x i32> %11, <4 x i32>* %sink
+  ret void
+}
+
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll
new file mode 100644
index 0000000000000..f98b0dcd830bb
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -slp-schedule-budget=1 | FileCheck %s
+
+define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
+; CHECK-LABEL: @g(
+; CHECK-NEXT:    [[X0:%.*]] = extractelement <2 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[Y1:%.*]] = extractelement <2 x i8> [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[X0X0:%.*]] = mul i8 [[X0]], [[X0]]
+; CHECK-NEXT:    [[Y1Y1:%.*]] = mul i8 [[Y1]], [[Y1]]
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <2 x i8> poison, i8 [[X0X0]], i32 0
+; CHECK-NEXT:    [[INS2:%.*]] = insertelement <2 x i8> [[INS1]], i8 [[Y1Y1]], i32 1
+; CHECK-NEXT:    ret <2 x i8> [[INS2]]
+;
+  %x0 = extractelement <2 x i8> %x, i32 0
+  %y1 = extractelement <2 x i8> %y, i32 1
+  %x0x0 = mul i8 %x0, %x0
+  %y1y1 = mul i8 %y1, %y1
+  %ins1 = insertelement <2 x i8> poison, i8 %x0x0, i32 0
+  %ins2 = insertelement <2 x i8> %ins1, i8 %y1y1, i32 1
+  ret <2 x i8> %ins2
+}
+
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
index e03f3f808a4ff..23f2196b2425b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
@@ -338,4 +338,151 @@ define void @fmaxnum_16f32() #0 {
   ret void
 }
 
+define float @reduction_v4f32_fast(float* %p) {
+; CHECK-LABEL: @reduction_v4f32_fast(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
+; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
+; CHECK-NEXT:    [[T0:%.*]] = load float, float* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load float, float* [[G1]], align 4
+; CHECK-NEXT:    [[T2:%.*]] = load float, float* [[G2]], align 4
+; CHECK-NEXT:    [[T3:%.*]] = load float, float* [[G3]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call fast float @llvm.maxnum.f32(float [[T1]], float [[T0]])
+; CHECK-NEXT:    [[M2:%.*]] = tail call fast float @llvm.maxnum.f32(float [[T2]], float [[M1]])
+; CHECK-NEXT:    [[M3:%.*]] = tail call fast float @llvm.maxnum.f32(float [[T3]], float [[M2]])
+; CHECK-NEXT:    ret float [[M3]]
+;
+  %g1 = getelementptr inbounds float, float* %p, i64 1
+  %g2 = getelementptr inbounds float, float* %p, i64 2
+  %g3 = getelementptr inbounds float, float* %p, i64 3
+  %t0 = load float, float* %p, align 4
+  %t1 = load float, float* %g1, align 4
+  %t2 = load float, float* %g2, align 4
+  %t3 = load float, float* %g3, align 4
+  %m1 = tail call fast float @llvm.maxnum.f32(float %t1, float %t0)
+  %m2 = tail call fast float @llvm.maxnum.f32(float %t2, float %m1)
+  %m3 = tail call fast float @llvm.maxnum.f32(float %t3, float %m2)
+  ret float %m3
+}
+
+define float @reduction_v4f32_nnan(float* %p) {
+; CHECK-LABEL: @reduction_v4f32_nnan(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
+; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
+; CHECK-NEXT:    [[T0:%.*]] = load float, float* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load float, float* [[G1]], align 4
+; CHECK-NEXT:    [[T2:%.*]] = load float, float* [[G2]], align 4
+; CHECK-NEXT:    [[T3:%.*]] = load float, float* [[G3]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call nnan float @llvm.maxnum.f32(float [[T1]], float [[T0]])
+; CHECK-NEXT:    [[M2:%.*]] = tail call nnan float @llvm.maxnum.f32(float [[T2]], float [[M1]])
+; CHECK-NEXT:    [[M3:%.*]] = tail call nnan float @llvm.maxnum.f32(float [[T3]], float [[M2]])
+; CHECK-NEXT:    ret float [[M3]]
+;
+  %g1 = getelementptr inbounds float, float* %p, i64 1
+  %g2 = getelementptr inbounds float, float* %p, i64 2
+  %g3 = getelementptr inbounds float, float* %p, i64 3
+  %t0 = load float, float* %p, align 4
+  %t1 = load float, float* %g1, align 4
+  %t2 = load float, float* %g2, align 4
+  %t3 = load float, float* %g3, align 4
+  %m1 = tail call nnan float @llvm.maxnum.f32(float %t1, float %t0)
+  %m2 = tail call nnan float @llvm.maxnum.f32(float %t2, float %m1)
+  %m3 = tail call nnan float @llvm.maxnum.f32(float %t3, float %m2)
+  ret float %m3
+}
+
+define float @reduction_v8f32_fast(float* %p) {
+; CHECK-LABEL: @reduction_v8f32_fast(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
+; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
+; CHECK-NEXT:    [[G4:%.*]] = getelementptr inbounds float, float* [[P]], i64 4
+; CHECK-NEXT:    [[G5:%.*]] = getelementptr inbounds float, float* [[P]], i64 5
+; CHECK-NEXT:    [[G6:%.*]] = getelementptr inbounds float, float* [[P]], i64 6
+; CHECK-NEXT:    [[G7:%.*]] = getelementptr inbounds float, float* [[P]], i64 7
+; CHECK-NEXT:    [[T0:%.*]] = load float, float* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load float, float* [[G1]], align 4
+; CHECK-NEXT:    [[T2:%.*]] = load float, float* [[G2]], align 4
+; CHECK-NEXT:    [[T3:%.*]] = load float, float* [[G3]], align 4
+; CHECK-NEXT:    [[T4:%.*]] = load float, float* [[G4]], align 4
+; CHECK-NEXT:    [[T5:%.*]] = load float, float* [[G5]], align 4
+; CHECK-NEXT:    [[T6:%.*]] = load float, float* [[G6]], align 4
+; CHECK-NEXT:    [[T7:%.*]] = load float, float* [[G7]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call fast float @llvm.maxnum.f32(float [[T1]], float [[T0]])
+; CHECK-NEXT:    [[M2:%.*]] = tail call fast float @llvm.maxnum.f32(float [[T2]], float [[M1]])
+; CHECK-NEXT:    [[M3:%.*]] = tail call fast float @llvm.maxnum.f32(float [[T3]], float [[M2]])
+; CHECK-NEXT:    [[M4:%.*]] = tail call fast float @llvm.maxnum.f32(float [[T4]], float [[M3]])
+; CHECK-NEXT:    [[M5:%.*]] = tail call fast float @llvm.maxnum.f32(float [[M4]], float [[T6]])
+; CHECK-NEXT:    [[M6:%.*]] = tail call fast float @llvm.maxnum.f32(float [[M5]], float [[T5]])
+; CHECK-NEXT:    [[M7:%.*]] = tail call fast float @llvm.maxnum.f32(float [[M6]], float [[T7]])
+; CHECK-NEXT:    ret float [[M7]]
+;
+  %g1 = getelementptr inbounds float, float* %p, i64 1
+  %g2 = getelementptr inbounds float, float* %p, i64 2
+  %g3 = getelementptr inbounds float, float* %p, i64 3
+  %g4 = getelementptr inbounds float, float* %p, i64 4
+  %g5 = getelementptr inbounds float, float* %p, i64 5
+  %g6 = getelementptr inbounds float, float* %p, i64 6
+  %g7 = getelementptr inbounds float, float* %p, i64 7
+  %t0 = load float, float* %p, align 4
+  %t1 = load float, float* %g1, align 4
+  %t2 = load float, float* %g2, align 4
+  %t3 = load float, float* %g3, align 4
+  %t4 = load float, float* %g4, align 4
+  %t5 = load float, float* %g5, align 4
+  %t6 = load float, float* %g6, align 4
+  %t7 = load float, float* %g7, align 4
+  %m1 = tail call fast float @llvm.maxnum.f32(float %t1, float %t0)
+  %m2 = tail call fast float @llvm.maxnum.f32(float %t2, float %m1)
+  %m3 = tail call fast float @llvm.maxnum.f32(float %t3, float %m2)
+  %m4 = tail call fast float @llvm.maxnum.f32(float %t4, float %m3)
+  %m5 = tail call fast float @llvm.maxnum.f32(float %m4, float %t6)
+  %m6 = tail call fast float @llvm.maxnum.f32(float %m5, float %t5)
+  %m7 = tail call fast float @llvm.maxnum.f32(float %m6, float %t7)
+  ret float %m7
+}
+
+define double @reduction_v2f64_fast(double* %p) {
+; CHECK-LABEL: @reduction_v2f64_fast(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds double, double* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[T0:%.*]] = load double, double* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load double, double* [[G1]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call fast double @llvm.maxnum.f64(double [[T1]], double [[T0]])
+; CHECK-NEXT:    ret double [[M1]]
+;
+  %g1 = getelementptr inbounds double, double* %p, i64 1
+  %t0 = load double, double* %p, align 4
+  %t1 = load double, double* %g1, align 4
+  %m1 = tail call fast double @llvm.maxnum.f64(double %t1, double %t0)
+  ret double %m1
+}
+
+define double @reduction_v4f64_fast(double* %p) {
+; CHECK-LABEL: @reduction_v4f64_fast(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds double, double* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds double, double* [[P]], i64 2
+; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds double, double* [[P]], i64 3
+; CHECK-NEXT:    [[T0:%.*]] = load double, double* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load double, double* [[G1]], align 4
+; CHECK-NEXT:    [[T2:%.*]] = load double, double* [[G2]], align 4
+; CHECK-NEXT:    [[T3:%.*]] = load double, double* [[G3]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call fast double @llvm.maxnum.f64(double [[T1]], double [[T0]])
+; CHECK-NEXT:    [[M2:%.*]] = tail call fast double @llvm.maxnum.f64(double [[T2]], double [[M1]])
+; CHECK-NEXT:    [[M3:%.*]] = tail call fast double @llvm.maxnum.f64(double [[T3]], double [[M2]])
+; CHECK-NEXT:    ret double [[M3]]
+;
+  %g1 = getelementptr inbounds double, double* %p, i64 1
+  %g2 = getelementptr inbounds double, double* %p, i64 2
+  %g3 = getelementptr inbounds double, double* %p, i64 3
+  %t0 = load double, double* %p, align 4
+  %t1 = load double, double* %g1, align 4
+  %t2 = load double, double* %g2, align 4
+  %t3 = load double, double* %g3, align 4
+  %m1 = tail call fast double @llvm.maxnum.f64(double %t1, double %t0)
+  %m2 = tail call fast double @llvm.maxnum.f64(double %t2, double %m1)
+  %m3 = tail call fast double @llvm.maxnum.f64(double %t3, double %m2)
+  ret double %m3
+}
+
 attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
index b830d826c2e96..81bcfb2f1e9b7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
@@ -338,4 +338,151 @@ define void @fminnum_16f32() #0 {
   ret void
 }
 
+define float @reduction_v4f32_fast(float* %p) {
+; CHECK-LABEL: @reduction_v4f32_fast(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
+; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
+; CHECK-NEXT:    [[T0:%.*]] = load float, float* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load float, float* [[G1]], align 4
+; CHECK-NEXT:    [[T2:%.*]] = load float, float* [[G2]], align 4
+; CHECK-NEXT:    [[T3:%.*]] = load float, float* [[G3]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call fast float @llvm.minnum.f32(float [[T1]], float [[T0]])
+; CHECK-NEXT:    [[M2:%.*]] = tail call fast float @llvm.minnum.f32(float [[T2]], float [[M1]])
+; CHECK-NEXT:    [[M3:%.*]] = tail call fast float @llvm.minnum.f32(float [[T3]], float [[M2]])
+; CHECK-NEXT:    ret float [[M3]]
+;
+  %g1 = getelementptr inbounds float, float* %p, i64 1
+  %g2 = getelementptr inbounds float, float* %p, i64 2
+  %g3 = getelementptr inbounds float, float* %p, i64 3
+  %t0 = load float, float* %p, align 4
+  %t1 = load float, float* %g1, align 4
+  %t2 = load float, float* %g2, align 4
+  %t3 = load float, float* %g3, align 4
+  %m1 = tail call fast float @llvm.minnum.f32(float %t1, float %t0)
+  %m2 = tail call fast float @llvm.minnum.f32(float %t2, float %m1)
+  %m3 = tail call fast float @llvm.minnum.f32(float %t3, float %m2)
+  ret float %m3
+}
+
+define float @reduction_v4f32_nnan(float* %p) {
+; CHECK-LABEL: @reduction_v4f32_nnan(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
+; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
+; CHECK-NEXT:    [[T0:%.*]] = load float, float* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load float, float* [[G1]], align 4
+; CHECK-NEXT:    [[T2:%.*]] = load float, float* [[G2]], align 4
+; CHECK-NEXT:    [[T3:%.*]] = load float, float* [[G3]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call nnan float @llvm.minnum.f32(float [[T1]], float [[T0]])
+; CHECK-NEXT:    [[M2:%.*]] = tail call nnan float @llvm.minnum.f32(float [[T2]], float [[M1]])
+; CHECK-NEXT:    [[M3:%.*]] = tail call nnan float @llvm.minnum.f32(float [[T3]], float [[M2]])
+; CHECK-NEXT:    ret float [[M3]]
+;
+  %g1 = getelementptr inbounds float, float* %p, i64 1
+  %g2 = getelementptr inbounds float, float* %p, i64 2
+  %g3 = getelementptr inbounds float, float* %p, i64 3
+  %t0 = load float, float* %p, align 4
+  %t1 = load float, float* %g1, align 4
+  %t2 = load float, float* %g2, align 4
+  %t3 = load float, float* %g3, align 4
+  %m1 = tail call nnan float @llvm.minnum.f32(float %t1, float %t0)
+  %m2 = tail call nnan float @llvm.minnum.f32(float %t2, float %m1)
+  %m3 = tail call nnan float @llvm.minnum.f32(float %t3, float %m2)
+  ret float %m3
+}
+
+define float @reduction_v8f32_fast(float* %p) {
+; CHECK-LABEL: @reduction_v8f32_fast(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds float, float* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds float, float* [[P]], i64 2
+; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds float, float* [[P]], i64 3
+; CHECK-NEXT:    [[G4:%.*]] = getelementptr inbounds float, float* [[P]], i64 4
+; CHECK-NEXT:    [[G5:%.*]] = getelementptr inbounds float, float* [[P]], i64 5
+; CHECK-NEXT:    [[G6:%.*]] = getelementptr inbounds float, float* [[P]], i64 6
+; CHECK-NEXT:    [[G7:%.*]] = getelementptr inbounds float, float* [[P]], i64 7
+; CHECK-NEXT:    [[T0:%.*]] = load float, float* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load float, float* [[G1]], align 4
+; CHECK-NEXT:    [[T2:%.*]] = load float, float* [[G2]], align 4
+; CHECK-NEXT:    [[T3:%.*]] = load float, float* [[G3]], align 4
+; CHECK-NEXT:    [[T4:%.*]] = load float, float* [[G4]], align 4
+; CHECK-NEXT:    [[T5:%.*]] = load float, float* [[G5]], align 4
+; CHECK-NEXT:    [[T6:%.*]] = load float, float* [[G6]], align 4
+; CHECK-NEXT:    [[T7:%.*]] = load float, float* [[G7]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call fast float @llvm.minnum.f32(float [[T1]], float [[T0]])
+; CHECK-NEXT:    [[M2:%.*]] = tail call fast float @llvm.minnum.f32(float [[T2]], float [[M1]])
+; CHECK-NEXT:    [[M3:%.*]] = tail call fast float @llvm.minnum.f32(float [[T3]], float [[M2]])
+; CHECK-NEXT:    [[M4:%.*]] = tail call fast float @llvm.minnum.f32(float [[T4]], float [[M3]])
+; CHECK-NEXT:    [[M5:%.*]] = tail call fast float @llvm.minnum.f32(float [[M4]], float [[T6]])
+; CHECK-NEXT:    [[M6:%.*]] = tail call fast float @llvm.minnum.f32(float [[M5]], float [[T5]])
+; CHECK-NEXT:    [[M7:%.*]] = tail call fast float @llvm.minnum.f32(float [[M6]], float [[T7]])
+; CHECK-NEXT:    ret float [[M7]]
+;
+  %g1 = getelementptr inbounds float, float* %p, i64 1
+  %g2 = getelementptr inbounds float, float* %p, i64 2
+  %g3 = getelementptr inbounds float, float* %p, i64 3
+  %g4 = getelementptr inbounds float, float* %p, i64 4
+  %g5 = getelementptr inbounds float, float* %p, i64 5
+  %g6 = getelementptr inbounds float, float* %p, i64 6
+  %g7 = getelementptr inbounds float, float* %p, i64 7
+  %t0 = load float, float* %p, align 4
+  %t1 = load float, float* %g1, align 4
+  %t2 = load float, float* %g2, align 4
+  %t3 = load float, float* %g3, align 4
+  %t4 = load float, float* %g4, align 4
+  %t5 = load float, float* %g5, align 4
+  %t6 = load float, float* %g6, align 4
+  %t7 = load float, float* %g7, align 4
+  %m1 = tail call fast float @llvm.minnum.f32(float %t1, float %t0)
+  %m2 = tail call fast float @llvm.minnum.f32(float %t2, float %m1)
+  %m3 = tail call fast float @llvm.minnum.f32(float %t3, float %m2)
+  %m4 = tail call fast float @llvm.minnum.f32(float %t4, float %m3)
+  %m5 = tail call fast float @llvm.minnum.f32(float %m4, float %t6)
+  %m6 = tail call fast float @llvm.minnum.f32(float %m5, float %t5)
+  %m7 = tail call fast float @llvm.minnum.f32(float %m6, float %t7)
+  ret float %m7
+}
+
+define double @reduction_v2f64_fast(double* %p) {
+; CHECK-LABEL: @reduction_v2f64_fast(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds double, double* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[T0:%.*]] = load double, double* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load double, double* [[G1]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call fast double @llvm.minnum.f64(double [[T1]], double [[T0]])
+; CHECK-NEXT:    ret double [[M1]]
+;
+  %g1 = getelementptr inbounds double, double* %p, i64 1
+  %t0 = load double, double* %p, align 4
+  %t1 = load double, double* %g1, align 4
+  %m1 = tail call fast double @llvm.minnum.f64(double %t1, double %t0)
+  ret double %m1
+}
+
+define double @reduction_v4f64_fast(double* %p) {
+; CHECK-LABEL: @reduction_v4f64_fast(
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds double, double* [[P:%.*]], i64 1
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds double, double* [[P]], i64 2
+; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds double, double* [[P]], i64 3
+; CHECK-NEXT:    [[T0:%.*]] = load double, double* [[P]], align 4
+; CHECK-NEXT:    [[T1:%.*]] = load double, double* [[G1]], align 4
+; CHECK-NEXT:    [[T2:%.*]] = load double, double* [[G2]], align 4
+; CHECK-NEXT:    [[T3:%.*]] = load double, double* [[G3]], align 4
+; CHECK-NEXT:    [[M1:%.*]] = tail call fast double @llvm.minnum.f64(double [[T1]], double [[T0]])
+; CHECK-NEXT:    [[M2:%.*]] = tail call fast double @llvm.minnum.f64(double [[T2]], double [[M1]])
+; CHECK-NEXT:    [[M3:%.*]] = tail call fast double @llvm.minnum.f64(double [[T3]], double [[M2]])
+; CHECK-NEXT:    ret double [[M3]]
+;
+  %g1 = getelementptr inbounds double, double* %p, i64 1
+  %g2 = getelementptr inbounds double, double* %p, i64 2
+  %g3 = getelementptr inbounds double, double* %p, i64 3
+  %t0 = load double, double* %p, align 4
+  %t1 = load double, double* %g1, align 4
+  %t2 = load double, double* %g2, align 4
+  %t3 = load double, double* %g3, align 4
+  %m1 = tail call fast double @llvm.minnum.f64(double %t1, double %t0)
+  %m2 = tail call fast double @llvm.minnum.f64(double %t2, double %m1)
+  %m3 = tail call fast double @llvm.minnum.f64(double %t3, double %m2)
+  ret double %m3
+}
+
 attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
new file mode 100644
index 0000000000000..8bc8639a0eb64
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
@@ -0,0 +1,534 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+@src64 = common global [8 x double] zeroinitializer, align 64
+@src32 = common global [16 x float] zeroinitializer, align 64
+@dst64 = common global [8 x i64] zeroinitializer, align 64
+@dst32 = common global [16 x i32] zeroinitializer, align 64
+@dst16 = common global [32 x i16] zeroinitializer, align 64
+@dst8 = common global [64 x i8] zeroinitializer, align 64
+
+;
+; FPTOSI vXf64
+;
+
+define void @fptosi_8f64_8i64() #0 {
+; SSE-LABEL: @fptosi_8f64_8i64(
+; SSE-NEXT:    [[A0:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 0), align 8
+; SSE-NEXT:    [[A1:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 1), align 8
+; SSE-NEXT:    [[A2:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 2), align 8
+; SSE-NEXT:    [[A3:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 3), align 8
+; SSE-NEXT:    [[A4:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 4), align 8
+; SSE-NEXT:    [[A5:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 5), align 8
+; SSE-NEXT:    [[A6:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 6), align 8
+; SSE-NEXT:    [[A7:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 7), align 8
+; SSE-NEXT:    [[CVT0:%.*]] = fptosi double [[A0]] to i64
+; SSE-NEXT:    [[CVT1:%.*]] = fptosi double [[A1]] to i64
+; SSE-NEXT:    [[CVT2:%.*]] = fptosi double [[A2]] to i64
+; SSE-NEXT:    [[CVT3:%.*]] = fptosi double [[A3]] to i64
+; SSE-NEXT:    [[CVT4:%.*]] = fptosi double [[A4]] to i64
+; SSE-NEXT:    [[CVT5:%.*]] = fptosi double [[A5]] to i64
+; SSE-NEXT:    [[CVT6:%.*]] = fptosi double [[A6]] to i64
+; SSE-NEXT:    [[CVT7:%.*]] = fptosi double [[A7]] to i64
+; SSE-NEXT:    store i64 [[CVT0]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 0), align 8
+; SSE-NEXT:    store i64 [[CVT1]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store i64 [[CVT2]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 2), align 8
+; SSE-NEXT:    store i64 [[CVT3]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    store i64 [[CVT4]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 4), align 8
+; SSE-NEXT:    store i64 [[CVT5]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 5), align 8
+; SSE-NEXT:    store i64 [[CVT6]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 6), align 8
+; SSE-NEXT:    store i64 [[CVT7]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 7), align 8
+; SSE-NEXT:    ret void
+;
+; AVX256NODQ-LABEL: @fptosi_8f64_8i64(
+; AVX256NODQ-NEXT:    [[A0:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 0), align 8
+; AVX256NODQ-NEXT:    [[A1:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    [[A2:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 2), align 8
+; AVX256NODQ-NEXT:    [[A3:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 3), align 8
+; AVX256NODQ-NEXT:    [[A4:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 4), align 8
+; AVX256NODQ-NEXT:    [[A5:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 5), align 8
+; AVX256NODQ-NEXT:    [[A6:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 6), align 8
+; AVX256NODQ-NEXT:    [[A7:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 7), align 8
+; AVX256NODQ-NEXT:    [[CVT0:%.*]] = fptosi double [[A0]] to i64
+; AVX256NODQ-NEXT:    [[CVT1:%.*]] = fptosi double [[A1]] to i64
+; AVX256NODQ-NEXT:    [[CVT2:%.*]] = fptosi double [[A2]] to i64
+; AVX256NODQ-NEXT:    [[CVT3:%.*]] = fptosi double [[A3]] to i64
+; AVX256NODQ-NEXT:    [[CVT4:%.*]] = fptosi double [[A4]] to i64
+; AVX256NODQ-NEXT:    [[CVT5:%.*]] = fptosi double [[A5]] to i64
+; AVX256NODQ-NEXT:    [[CVT6:%.*]] = fptosi double [[A6]] to i64
+; AVX256NODQ-NEXT:    [[CVT7:%.*]] = fptosi double [[A7]] to i64
+; AVX256NODQ-NEXT:    store i64 [[CVT0]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 0), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT1]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT2]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 2), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT3]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 3), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT4]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 4), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT5]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 5), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT6]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 6), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT7]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 7), align 8
+; AVX256NODQ-NEXT:    ret void
+;
+; AVX512-LABEL: @fptosi_8f64_8i64(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <8 x double>, <8 x double>* bitcast ([8 x double]* @src64 to <8 x double>*), align 8
+; AVX512-NEXT:    [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i64>
+; AVX512-NEXT:    store <8 x i64> [[TMP2]], <8 x i64>* bitcast ([8 x i64]* @dst64 to <8 x i64>*), align 8
+; AVX512-NEXT:    ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f64_8i64(
+; AVX256DQ-NEXT:    [[TMP1:%.*]] = load <4 x double>, <4 x double>* bitcast ([8 x double]* @src64 to <4 x double>*), align 8
+; AVX256DQ-NEXT:    [[TMP2:%.*]] = load <4 x double>, <4 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 4) to <4 x double>*), align 8
+; AVX256DQ-NEXT:    [[TMP3:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i64>
+; AVX256DQ-NEXT:    [[TMP4:%.*]] = fptosi <4 x double> [[TMP2]] to <4 x i64>
+; AVX256DQ-NEXT:    store <4 x i64> [[TMP3]], <4 x i64>* bitcast ([8 x i64]* @dst64 to <4 x i64>*), align 8
+; AVX256DQ-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 4) to <4 x i64>*), align 8
+; AVX256DQ-NEXT:    ret void
+;
+  %a0 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 0), align 8
+  %a1 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 1), align 8
+  %a2 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 2), align 8
+  %a3 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 3), align 8
+  %a4 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 4), align 8
+  %a5 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 5), align 8
+  %a6 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 6), align 8
+  %a7 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 7), align 8
+  %cvt0 = fptosi double %a0 to i64
+  %cvt1 = fptosi double %a1 to i64
+  %cvt2 = fptosi double %a2 to i64
+  %cvt3 = fptosi double %a3 to i64
+  %cvt4 = fptosi double %a4 to i64
+  %cvt5 = fptosi double %a5 to i64
+  %cvt6 = fptosi double %a6 to i64
+  %cvt7 = fptosi double %a7 to i64
+  store i64 %cvt0, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 0), align 8
+  store i64 %cvt1, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 1), align 8
+  store i64 %cvt2, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 2), align 8
+  store i64 %cvt3, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 3), align 8
+  store i64 %cvt4, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 4), align 8
+  store i64 %cvt5, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 5), align 8
+  store i64 %cvt6, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 6), align 8
+  store i64 %cvt7, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 7), align 8
+  ret void
+}
+
+define void @fptosi_8f64_8i32() #0 {
+; SSE-LABEL: @fptosi_8f64_8i32(
+; SSE-NEXT:    [[TMP1:%.*]] = load <4 x double>, <4 x double>* bitcast ([8 x double]* @src64 to <4 x double>*), align 8
+; SSE-NEXT:    [[TMP2:%.*]] = load <4 x double>, <4 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 4) to <4 x double>*), align 8
+; SSE-NEXT:    [[TMP3:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i32>
+; SSE-NEXT:    [[TMP4:%.*]] = fptosi <4 x double> [[TMP2]] to <4 x i32>
+; SSE-NEXT:    store <4 x i32> [[TMP3]], <4 x i32>* bitcast ([16 x i32]* @dst32 to <4 x i32>*), align 4
+; SSE-NEXT:    store <4 x i32> [[TMP4]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 4) to <4 x i32>*), align 4
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @fptosi_8f64_8i32(
+; AVX-NEXT:    [[TMP1:%.*]] = load <8 x double>, <8 x double>* bitcast ([8 x double]* @src64 to <8 x double>*), align 8
+; AVX-NEXT:    [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX-NEXT:    store <8 x i32> [[TMP2]], <8 x i32>* bitcast ([16 x i32]* @dst32 to <8 x i32>*), align 4
+; AVX-NEXT:    ret void
+;
+  %a0 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 0), align 8
+  %a1 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 1), align 8
+  %a2 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 2), align 8
+  %a3 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 3), align 8
+  %a4 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 4), align 8
+  %a5 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 5), align 8
+  %a6 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 6), align 8
+  %a7 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 7), align 8
+  %cvt0 = fptosi double %a0 to i32
+  %cvt1 = fptosi double %a1 to i32
+  %cvt2 = fptosi double %a2 to i32
+  %cvt3 = fptosi double %a3 to i32
+  %cvt4 = fptosi double %a4 to i32
+  %cvt5 = fptosi double %a5 to i32
+  %cvt6 = fptosi double %a6 to i32
+  %cvt7 = fptosi double %a7 to i32
+  store i32 %cvt0, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 0), align 4
+  store i32 %cvt1, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 1), align 4
+  store i32 %cvt2, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 2), align 4
+  store i32 %cvt3, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 3), align 4
+  store i32 %cvt4, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 4), align 4
+  store i32 %cvt5, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 5), align 4
+  store i32 %cvt6, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 6), align 4
+  store i32 %cvt7, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 7), align 4
+  ret void
+}
+
+define void @fptosi_8f64_8i16() #0 {
+; CHECK-LABEL: @fptosi_8f64_8i16(
+; CHECK-NEXT:    [[TMP1:%.*]] = load <8 x double>, <8 x double>* bitcast ([8 x double]* @src64 to <8 x double>*), align 8
+; CHECK-NEXT:    [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i16>
+; CHECK-NEXT:    store <8 x i16> [[TMP2]], <8 x i16>* bitcast ([32 x i16]* @dst16 to <8 x i16>*), align 2
+; CHECK-NEXT:    ret void
+;
+  %a0 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 0), align 8
+  %a1 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 1), align 8
+  %a2 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 2), align 8
+  %a3 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 3), align 8
+  %a4 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 4), align 8
+  %a5 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 5), align 8
+  %a6 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 6), align 8
+  %a7 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 7), align 8
+  %cvt0 = fptosi double %a0 to i16
+  %cvt1 = fptosi double %a1 to i16
+  %cvt2 = fptosi double %a2 to i16
+  %cvt3 = fptosi double %a3 to i16
+  %cvt4 = fptosi double %a4 to i16
+  %cvt5 = fptosi double %a5 to i16
+  %cvt6 = fptosi double %a6 to i16
+  %cvt7 = fptosi double %a7 to i16
+  store i16 %cvt0, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 0), align 2
+  store i16 %cvt1, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 1), align 2
+  store i16 %cvt2, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 2), align 2
+  store i16 %cvt3, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 3), align 2
+  store i16 %cvt4, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 4), align 2
+  store i16 %cvt5, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 5), align 2
+  store i16 %cvt6, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 6), align 2
+  store i16 %cvt7, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 7), align 2
+  ret void
+}
+
+define void @fptosi_8f64_8i8() #0 {
+; CHECK-LABEL: @fptosi_8f64_8i8(
+; CHECK-NEXT:    [[A0:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 0), align 8
+; CHECK-NEXT:    [[A1:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 1), align 8
+; CHECK-NEXT:    [[A2:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 2), align 8
+; CHECK-NEXT:    [[A3:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 3), align 8
+; CHECK-NEXT:    [[A4:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 4), align 8
+; CHECK-NEXT:    [[A5:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 5), align 8
+; CHECK-NEXT:    [[A6:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 6), align 8
+; CHECK-NEXT:    [[A7:%.*]] = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 7), align 8
+; CHECK-NEXT:    [[CVT0:%.*]] = fptosi double [[A0]] to i8
+; CHECK-NEXT:    [[CVT1:%.*]] = fptosi double [[A1]] to i8
+; CHECK-NEXT:    [[CVT2:%.*]] = fptosi double [[A2]] to i8
+; CHECK-NEXT:    [[CVT3:%.*]] = fptosi double [[A3]] to i8
+; CHECK-NEXT:    [[CVT4:%.*]] = fptosi double [[A4]] to i8
+; CHECK-NEXT:    [[CVT5:%.*]] = fptosi double [[A5]] to i8
+; CHECK-NEXT:    [[CVT6:%.*]] = fptosi double [[A6]] to i8
+; CHECK-NEXT:    [[CVT7:%.*]] = fptosi double [[A7]] to i8
+; CHECK-NEXT:    store i8 [[CVT0]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 0), align 1
+; CHECK-NEXT:    store i8 [[CVT1]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 1), align 1
+; CHECK-NEXT:    store i8 [[CVT2]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 2), align 1
+; CHECK-NEXT:    store i8 [[CVT3]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 3), align 1
+; CHECK-NEXT:    store i8 [[CVT4]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 4), align 1
+; CHECK-NEXT:    store i8 [[CVT5]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 5), align 1
+; CHECK-NEXT:    store i8 [[CVT6]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 6), align 1
+; CHECK-NEXT:    store i8 [[CVT7]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 7), align 1
+; CHECK-NEXT:    ret void
+;
+  %a0 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 0), align 8
+  %a1 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 1), align 8
+  %a2 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 2), align 8
+  %a3 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 3), align 8
+  %a4 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 4), align 8
+  %a5 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 5), align 8
+  %a6 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 6), align 8
+  %a7 = load double, double* getelementptr inbounds ([8 x double], [8 x double]* @src64, i32 0, i64 7), align 8
+  %cvt0 = fptosi double %a0 to i8
+  %cvt1 = fptosi double %a1 to i8
+  %cvt2 = fptosi double %a2 to i8
+  %cvt3 = fptosi double %a3 to i8
+  %cvt4 = fptosi double %a4 to i8
+  %cvt5 = fptosi double %a5 to i8
+  %cvt6 = fptosi double %a6 to i8
+  %cvt7 = fptosi double %a7 to i8
+  store i8 %cvt0, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 0), align 1
+  store i8 %cvt1, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 1), align 1
+  store i8 %cvt2, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 2), align 1
+  store i8 %cvt3, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 3), align 1
+  store i8 %cvt4, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 4), align 1
+  store i8 %cvt5, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 5), align 1
+  store i8 %cvt6, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 6), align 1
+  store i8 %cvt7, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 7), align 1
+  ret void
+}
+
+;
+; FPTOSI vXf32
+;
+
+define void @fptosi_8f32_8i64() #0 {
+; SSE-LABEL: @fptosi_8f32_8i64(
+; SSE-NEXT:    [[A0:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 0), align 4
+; SSE-NEXT:    [[A1:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 1), align 4
+; SSE-NEXT:    [[A2:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 2), align 4
+; SSE-NEXT:    [[A3:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 3), align 4
+; SSE-NEXT:    [[A4:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 4), align 4
+; SSE-NEXT:    [[A5:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 5), align 4
+; SSE-NEXT:    [[A6:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 6), align 4
+; SSE-NEXT:    [[A7:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 7), align 4
+; SSE-NEXT:    [[CVT0:%.*]] = fptosi float [[A0]] to i64
+; SSE-NEXT:    [[CVT1:%.*]] = fptosi float [[A1]] to i64
+; SSE-NEXT:    [[CVT2:%.*]] = fptosi float [[A2]] to i64
+; SSE-NEXT:    [[CVT3:%.*]] = fptosi float [[A3]] to i64
+; SSE-NEXT:    [[CVT4:%.*]] = fptosi float [[A4]] to i64
+; SSE-NEXT:    [[CVT5:%.*]] = fptosi float [[A5]] to i64
+; SSE-NEXT:    [[CVT6:%.*]] = fptosi float [[A6]] to i64
+; SSE-NEXT:    [[CVT7:%.*]] = fptosi float [[A7]] to i64
+; SSE-NEXT:    store i64 [[CVT0]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 0), align 8
+; SSE-NEXT:    store i64 [[CVT1]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store i64 [[CVT2]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 2), align 8
+; SSE-NEXT:    store i64 [[CVT3]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    store i64 [[CVT4]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 4), align 8
+; SSE-NEXT:    store i64 [[CVT5]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 5), align 8
+; SSE-NEXT:    store i64 [[CVT6]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 6), align 8
+; SSE-NEXT:    store i64 [[CVT7]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 7), align 8
+; SSE-NEXT:    ret void
+;
+; AVX256NODQ-LABEL: @fptosi_8f32_8i64(
+; AVX256NODQ-NEXT:    [[A0:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 0), align 4
+; AVX256NODQ-NEXT:    [[A1:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 1), align 4
+; AVX256NODQ-NEXT:    [[A2:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 2), align 4
+; AVX256NODQ-NEXT:    [[A3:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 3), align 4
+; AVX256NODQ-NEXT:    [[A4:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 4), align 4
+; AVX256NODQ-NEXT:    [[A5:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 5), align 4
+; AVX256NODQ-NEXT:    [[A6:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 6), align 4
+; AVX256NODQ-NEXT:    [[A7:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 7), align 4
+; AVX256NODQ-NEXT:    [[CVT0:%.*]] = fptosi float [[A0]] to i64
+; AVX256NODQ-NEXT:    [[CVT1:%.*]] = fptosi float [[A1]] to i64
+; AVX256NODQ-NEXT:    [[CVT2:%.*]] = fptosi float [[A2]] to i64
+; AVX256NODQ-NEXT:    [[CVT3:%.*]] = fptosi float [[A3]] to i64
+; AVX256NODQ-NEXT:    [[CVT4:%.*]] = fptosi float [[A4]] to i64
+; AVX256NODQ-NEXT:    [[CVT5:%.*]] = fptosi float [[A5]] to i64
+; AVX256NODQ-NEXT:    [[CVT6:%.*]] = fptosi float [[A6]] to i64
+; AVX256NODQ-NEXT:    [[CVT7:%.*]] = fptosi float [[A7]] to i64
+; AVX256NODQ-NEXT:    store i64 [[CVT0]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 0), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT1]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT2]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 2), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT3]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 3), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT4]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 4), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT5]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 5), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT6]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 6), align 8
+; AVX256NODQ-NEXT:    store i64 [[CVT7]], i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 7), align 8
+; AVX256NODQ-NEXT:    ret void
+;
+; AVX512-LABEL: @fptosi_8f32_8i64(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <8 x float>, <8 x float>* bitcast ([16 x float]* @src32 to <8 x float>*), align 4
+; AVX512-NEXT:    [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i64>
+; AVX512-NEXT:    store <8 x i64> [[TMP2]], <8 x i64>* bitcast ([8 x i64]* @dst64 to <8 x i64>*), align 8
+; AVX512-NEXT:    ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f32_8i64(
+; AVX256DQ-NEXT:    [[TMP1:%.*]] = load <4 x float>, <4 x float>* bitcast ([16 x float]* @src32 to <4 x float>*), align 4
+; AVX256DQ-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 4) to <4 x float>*), align 4
+; AVX256DQ-NEXT:    [[TMP3:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i64>
+; AVX256DQ-NEXT:    [[TMP4:%.*]] = fptosi <4 x float> [[TMP2]] to <4 x i64>
+; AVX256DQ-NEXT:    store <4 x i64> [[TMP3]], <4 x i64>* bitcast ([8 x i64]* @dst64 to <4 x i64>*), align 8
+; AVX256DQ-NEXT:    store <4 x i64> [[TMP4]], <4 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 4) to <4 x i64>*), align 8
+; AVX256DQ-NEXT:    ret void
+;
+  %a0 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 0), align 4
+  %a1 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 1), align 4
+  %a2 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 2), align 4
+  %a3 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 3), align 4
+  %a4 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 4), align 4
+  %a5 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 5), align 4
+  %a6 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 6), align 4
+  %a7 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 7), align 4
+  %cvt0 = fptosi float %a0 to i64
+  %cvt1 = fptosi float %a1 to i64
+  %cvt2 = fptosi float %a2 to i64
+  %cvt3 = fptosi float %a3 to i64
+  %cvt4 = fptosi float %a4 to i64
+  %cvt5 = fptosi float %a5 to i64
+  %cvt6 = fptosi float %a6 to i64
+  %cvt7 = fptosi float %a7 to i64
+  store i64 %cvt0, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 0), align 8
+  store i64 %cvt1, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 1), align 8
+  store i64 %cvt2, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 2), align 8
+  store i64 %cvt3, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 3), align 8
+  store i64 %cvt4, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 4), align 8
+  store i64 %cvt5, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 5), align 8
+  store i64 %cvt6, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 6), align 8
+  store i64 %cvt7, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @dst64, i32 0, i64 7), align 8
+  ret void
+}
+
+define void @fptosi_8f32_8i32() #0 {
+; SSE-LABEL: @fptosi_8f32_8i32(
+; SSE-NEXT:    [[TMP1:%.*]] = load <4 x float>, <4 x float>* bitcast ([16 x float]* @src32 to <4 x float>*), align 4
+; SSE-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 4) to <4 x float>*), align 4
+; SSE-NEXT:    [[TMP3:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i32>
+; SSE-NEXT:    [[TMP4:%.*]] = fptosi <4 x float> [[TMP2]] to <4 x i32>
+; SSE-NEXT:    store <4 x i32> [[TMP3]], <4 x i32>* bitcast ([16 x i32]* @dst32 to <4 x i32>*), align 4
+; SSE-NEXT:    store <4 x i32> [[TMP4]], <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 4) to <4 x i32>*), align 4
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @fptosi_8f32_8i32(
+; AVX-NEXT:    [[TMP1:%.*]] = load <8 x float>, <8 x float>* bitcast ([16 x float]* @src32 to <8 x float>*), align 4
+; AVX-NEXT:    [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX-NEXT:    store <8 x i32> [[TMP2]], <8 x i32>* bitcast ([16 x i32]* @dst32 to <8 x i32>*), align 4
+; AVX-NEXT:    ret void
+;
+  %a0 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 0), align 4
+  %a1 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 1), align 4
+  %a2 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 2), align 4
+  %a3 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 3), align 4
+  %a4 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 4), align 4
+  %a5 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 5), align 4
+  %a6 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 6), align 4
+  %a7 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 7), align 4
+  %cvt0 = fptosi float %a0 to i32
+  %cvt1 = fptosi float %a1 to i32
+  %cvt2 = fptosi float %a2 to i32
+  %cvt3 = fptosi float %a3 to i32
+  %cvt4 = fptosi float %a4 to i32
+  %cvt5 = fptosi float %a5 to i32
+  %cvt6 = fptosi float %a6 to i32
+  %cvt7 = fptosi float %a7 to i32
+  store i32 %cvt0, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 0), align 4
+  store i32 %cvt1, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 1), align 4
+  store i32 %cvt2, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 2), align 4
+  store i32 %cvt3, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 3), align 4
+  store i32 %cvt4, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 4), align 4
+  store i32 %cvt5, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 5), align 4
+  store i32 %cvt6, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 6), align 4
+  store i32 %cvt7, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @dst32, i32 0, i64 7), align 4
+  ret void
+}
+
+define void @fptosi_8f32_8i16() #0 {
+; CHECK-LABEL: @fptosi_8f32_8i16(
+; CHECK-NEXT:    [[TMP1:%.*]] = load <8 x float>, <8 x float>* bitcast ([16 x float]* @src32 to <8 x float>*), align 4
+; CHECK-NEXT:    [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i16>
+; CHECK-NEXT:    store <8 x i16> [[TMP2]], <8 x i16>* bitcast ([32 x i16]* @dst16 to <8 x i16>*), align 2
+; CHECK-NEXT:    ret void
+;
+  %a0 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 0), align 4
+  %a1 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 1), align 4
+  %a2 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 2), align 4
+  %a3 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 3), align 4
+  %a4 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 4), align 4
+  %a5 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 5), align 4
+  %a6 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 6), align 4
+  %a7 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 7), align 4
+  %cvt0 = fptosi float %a0 to i16
+  %cvt1 = fptosi float %a1 to i16
+  %cvt2 = fptosi float %a2 to i16
+  %cvt3 = fptosi float %a3 to i16
+  %cvt4 = fptosi float %a4 to i16
+  %cvt5 = fptosi float %a5 to i16
+  %cvt6 = fptosi float %a6 to i16
+  %cvt7 = fptosi float %a7 to i16
+  store i16 %cvt0, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 0), align 2
+  store i16 %cvt1, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 1), align 2
+  store i16 %cvt2, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 2), align 2
+  store i16 %cvt3, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 3), align 2
+  store i16 %cvt4, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 4), align 2
+  store i16 %cvt5, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 5), align 2
+  store i16 %cvt6, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 6), align 2
+  store i16 %cvt7, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @dst16, i32 0, i64 7), align 2
+  ret void
+}
+
+define void @fptosi_8f32_8i8() #0 {
+; CHECK-LABEL: @fptosi_8f32_8i8(
+; CHECK-NEXT:    [[A0:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 0), align 4
+; CHECK-NEXT:    [[A1:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 1), align 4
+; CHECK-NEXT:    [[A2:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 2), align 4
+; CHECK-NEXT:    [[A3:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 3), align 4
+; CHECK-NEXT:    [[A4:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 4), align 4
+; CHECK-NEXT:    [[A5:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 5), align 4
+; CHECK-NEXT:    [[A6:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 6), align 4
+; CHECK-NEXT:    [[A7:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 7), align 4
+; CHECK-NEXT:    [[CVT0:%.*]] = fptosi float [[A0]] to i8
+; CHECK-NEXT:    [[CVT1:%.*]] = fptosi float [[A1]] to i8
+; CHECK-NEXT:    [[CVT2:%.*]] = fptosi float [[A2]] to i8
+; CHECK-NEXT:    [[CVT3:%.*]] = fptosi float [[A3]] to i8
+; CHECK-NEXT:    [[CVT4:%.*]] = fptosi float [[A4]] to i8
+; CHECK-NEXT:    [[CVT5:%.*]] = fptosi float [[A5]] to i8
+; CHECK-NEXT:    [[CVT6:%.*]] = fptosi float [[A6]] to i8
+; CHECK-NEXT:    [[CVT7:%.*]] = fptosi float [[A7]] to i8
+; CHECK-NEXT:    store i8 [[CVT0]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 0), align 1
+; CHECK-NEXT:    store i8 [[CVT1]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 1), align 1
+; CHECK-NEXT:    store i8 [[CVT2]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 2), align 1
+; CHECK-NEXT:    store i8 [[CVT3]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 3), align 1
+; CHECK-NEXT:    store i8 [[CVT4]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 4), align 1
+; CHECK-NEXT:    store i8 [[CVT5]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 5), align 1
+; CHECK-NEXT:    store i8 [[CVT6]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 6), align 1
+; CHECK-NEXT:    store i8 [[CVT7]], i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 7), align 1
+; CHECK-NEXT:    ret void
+;
+  %a0 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 0), align 4
+  %a1 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 1), align 4
+  %a2 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 2), align 4
+  %a3 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 3), align 4
+  %a4 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 4), align 4
+  %a5 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 5), align 4
+  %a6 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 6), align 4
+  %a7 = load float, float* getelementptr inbounds ([16 x float], [16 x float]* @src32, i32 0, i64 7), align 4
+  %cvt0 = fptosi float %a0 to i8
+  %cvt1 = fptosi float %a1 to i8
+  %cvt2 = fptosi float %a2 to i8
+  %cvt3 = fptosi float %a3 to i8
+  %cvt4 = fptosi float %a4 to i8
+  %cvt5 = fptosi float %a5 to i8
+  %cvt6 = fptosi float %a6 to i8
+  %cvt7 = fptosi float %a7 to i8
+  store i8 %cvt0, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 0), align 1
+  store i8 %cvt1, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 1), align 1
+  store i8 %cvt2, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 2), align 1
+  store i8 %cvt3, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 3), align 1
+  store i8 %cvt4, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 4), align 1
+  store i8 %cvt5, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 5), align 1
+  store i8 %cvt6, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 6), align 1
+  store i8 %cvt7, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @dst8, i32 0, i64 7), align 1
+  ret void
+}
+
+;
+; FPTOSI BUILDVECTOR
+;
+
+define <4 x i32> @fptosi_4xf64_4i32(double %a0, double %a1, double %a2, double %a3) #0 {
+; CHECK-LABEL: @fptosi_4xf64_4i32(
+; CHECK-NEXT:    [[CVT0:%.*]] = fptosi double [[A0:%.*]] to i32
+; CHECK-NEXT:    [[CVT1:%.*]] = fptosi double [[A1:%.*]] to i32
+; CHECK-NEXT:    [[CVT2:%.*]] = fptosi double [[A2:%.*]] to i32
+; CHECK-NEXT:    [[CVT3:%.*]] = fptosi double [[A3:%.*]] to i32
+; CHECK-NEXT:    [[RES0:%.*]] = insertelement <4 x i32> poison, i32 [[CVT0]], i32 0
+; CHECK-NEXT:    [[RES1:%.*]] = insertelement <4 x i32> [[RES0]], i32 [[CVT1]], i32 1
+; CHECK-NEXT:    [[RES2:%.*]] = insertelement <4 x i32> [[RES1]], i32 [[CVT2]], i32 2
+; CHECK-NEXT:    [[RES3:%.*]] = insertelement <4 x i32> [[RES2]], i32 [[CVT3]], i32 3
+; CHECK-NEXT:    ret <4 x i32> [[RES3]]
+;
+  %cvt0 = fptosi double %a0 to i32
+  %cvt1 = fptosi double %a1 to i32
+  %cvt2 = fptosi double %a2 to i32
+  %cvt3 = fptosi double %a3 to i32
+  %res0 = insertelement <4 x i32> poison, i32 %cvt0, i32 0
+  %res1 = insertelement <4 x i32> %res0, i32 %cvt1, i32 1
+  %res2 = insertelement <4 x i32> %res1, i32 %cvt2, i32 2
+  %res3 = insertelement <4 x i32> %res2, i32 %cvt3, i32 3
+  ret <4 x i32> %res3
+}
+
+define <4 x i32> @fptosi_4xf32_4i32(float %a0, float %a1, float %a2, float %a3) #0 {
+; CHECK-LABEL: @fptosi_4xf32_4i32(
+; CHECK-NEXT:    [[CVT0:%.*]] = fptosi float [[A0:%.*]] to i32
+; CHECK-NEXT:    [[CVT1:%.*]] = fptosi float [[A1:%.*]] to i32
+; CHECK-NEXT:    [[CVT2:%.*]] = fptosi float [[A2:%.*]] to i32
+; CHECK-NEXT:    [[CVT3:%.*]] = fptosi float [[A3:%.*]] to i32
+; CHECK-NEXT:    [[RES0:%.*]] = insertelement <4 x i32> poison, i32 [[CVT0]], i32 0
+; CHECK-NEXT:    [[RES1:%.*]] = insertelement <4 x i32> [[RES0]], i32 [[CVT1]], i32 1
+; CHECK-NEXT:    [[RES2:%.*]] = insertelement <4 x i32> [[RES1]], i32 [[CVT2]], i32 2
+; CHECK-NEXT:    [[RES3:%.*]] = insertelement <4 x i32> [[RES2]], i32 [[CVT3]], i32 3
+; CHECK-NEXT:    ret <4 x i32> [[RES3]]
+;
+  %cvt0 = fptosi float %a0 to i32
+  %cvt1 = fptosi float %a1 to i32
+  %cvt2 = fptosi float %a2 to i32
+  %cvt3 = fptosi float %a3 to i32
+  %res0 = insertelement <4 x i32> poison, i32 %cvt0, i32 0
+  %res1 = insertelement <4 x i32> %res0, i32 %cvt1, i32 1
+  %res2 = insertelement <4 x i32> %res1, i32 %cvt2, i32 2
+  %res3 = insertelement <4 x i32> %res2, i32 %cvt3, i32 3
+  ret <4 x i32> %res3
+}
+
+attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/hadd-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/hadd-inseltpoison.ll
new file mode 100644
index 0000000000000..97775135d0257
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/hadd-inseltpoison.ll
@@ -0,0 +1,433 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+
+;
+; 128-bit vectors
+;
+
+define <2 x double> @test_v2f64(<2 x double> %a, <2 x double> %b) {
+; SSE-LABEL: @test_v2f64(
+; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x i32> <i32 0, i32 2>
+; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i32 1, i32 3>
+; SSE-NEXT:    [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]]
+; SSE-NEXT:    ret <2 x double> [[TMP3]]
+;
+; SLM-LABEL: @test_v2f64(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <2 x double> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <2 x double> [[A]], i32 1
+; SLM-NEXT:    [[B0:%.*]] = extractelement <2 x double> [[B:%.*]], i32 0
+; SLM-NEXT:    [[B1:%.*]] = extractelement <2 x double> [[B]], i32 1
+; SLM-NEXT:    [[R0:%.*]] = fadd double [[A0]], [[A1]]
+; SLM-NEXT:    [[R1:%.*]] = fadd double [[B0]], [[B1]]
+; SLM-NEXT:    [[R00:%.*]] = insertelement <2 x double> poison, double [[R0]], i32 0
+; SLM-NEXT:    [[R01:%.*]] = insertelement <2 x double> [[R00]], double [[R1]], i32 1
+; SLM-NEXT:    ret <2 x double> [[R01]]
+;
+; AVX-LABEL: @test_v2f64(
+; AVX-NEXT:    [[TMP1:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x i32> <i32 0, i32 2>
+; AVX-NEXT:    [[TMP2:%.*]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i32 1, i32 3>
+; AVX-NEXT:    [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]]
+; AVX-NEXT:    ret <2 x double> [[TMP3]]
+;
+  %a0 = extractelement <2 x double> %a, i32 0
+  %a1 = extractelement <2 x double> %a, i32 1
+  %b0 = extractelement <2 x double> %b, i32 0
+  %b1 = extractelement <2 x double> %b, i32 1
+  %r0 = fadd double %a0, %a1
+  %r1 = fadd double %b0, %b1
+  %r00 = insertelement <2 x double> poison, double %r0, i32 0
+  %r01 = insertelement <2 x double>  %r00, double %r1, i32 1
+  ret <2 x double> %r01
+}
+
+define <4 x float> @test_v4f32(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_v4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x float> [[A]], <4 x float> [[B]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x float> [[TMP3]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %r0 = fadd float %a0, %a1
+  %r1 = fadd float %a2, %a3
+  %r2 = fadd float %b0, %b1
+  %r3 = fadd float %b2, %b3
+  %r00 = insertelement <4 x float> poison, float %r0, i32 0
+  %r01 = insertelement <4 x float>  %r00, float %r1, i32 1
+  %r02 = insertelement <4 x float>  %r01, float %r2, i32 2
+  %r03 = insertelement <4 x float>  %r02, float %r3, i32 3
+  ret <4 x float> %r03
+}
+
+define <2 x i64> @test_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @test_v2i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]], <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[A]], <2 x i64> [[B]], <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = add <2 x i64> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
+;
+  %a0 = extractelement <2 x i64> %a, i32 0
+  %a1 = extractelement <2 x i64> %a, i32 1
+  %b0 = extractelement <2 x i64> %b, i32 0
+  %b1 = extractelement <2 x i64> %b, i32 1
+  %r0 = add i64 %a0, %a1
+  %r1 = add i64 %b0, %b1
+  %r00 = insertelement <2 x i64> poison, i64 %r0, i32 0
+  %r01 = insertelement <2 x i64>  %r00, i64 %r1, i32 1
+  ret <2 x i64> %r01
+}
+
+define <4 x i32> @test_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @test_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[B]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT:    [[TMP3:%.*]] = add <4 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %b0 = extractelement <4 x i32> %b, i32 0
+  %b1 = extractelement <4 x i32> %b, i32 1
+  %b2 = extractelement <4 x i32> %b, i32 2
+  %b3 = extractelement <4 x i32> %b, i32 3
+  %r0 = add i32 %a0, %a1
+  %r1 = add i32 %a2, %a3
+  %r2 = add i32 %b0, %b1
+  %r3 = add i32 %b2, %b3
+  %r00 = insertelement <4 x i32> poison, i32 %r0, i32 0
+  %r01 = insertelement <4 x i32>  %r00, i32 %r1, i32 1
+  %r02 = insertelement <4 x i32>  %r01, i32 %r2, i32 2
+  %r03 = insertelement <4 x i32>  %r02, i32 %r3, i32 3
+  ret <4 x i32> %r03
+}
+
+define <8 x i16> @test_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: @test_v8i16(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[B]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+; CHECK-NEXT:    [[TMP3:%.*]] = add <8 x i16> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+;
+  %a0 = extractelement <8 x i16> %a, i32 0
+  %a1 = extractelement <8 x i16> %a, i32 1
+  %a2 = extractelement <8 x i16> %a, i32 2
+  %a3 = extractelement <8 x i16> %a, i32 3
+  %a4 = extractelement <8 x i16> %a, i32 4
+  %a5 = extractelement <8 x i16> %a, i32 5
+  %a6 = extractelement <8 x i16> %a, i32 6
+  %a7 = extractelement <8 x i16> %a, i32 7
+  %b0 = extractelement <8 x i16> %b, i32 0
+  %b1 = extractelement <8 x i16> %b, i32 1
+  %b2 = extractelement <8 x i16> %b, i32 2
+  %b3 = extractelement <8 x i16> %b, i32 3
+  %b4 = extractelement <8 x i16> %b, i32 4
+  %b5 = extractelement <8 x i16> %b, i32 5
+  %b6 = extractelement <8 x i16> %b, i32 6
+  %b7 = extractelement <8 x i16> %b, i32 7
+  %r0 = add i16 %a0, %a1
+  %r1 = add i16 %a2, %a3
+  %r2 = add i16 %a4, %a5
+  %r3 = add i16 %a6, %a7
+  %r4 = add i16 %b0, %b1
+  %r5 = add i16 %b2, %b3
+  %r6 = add i16 %b4, %b5
+  %r7 = add i16 %b6, %b7
+  %r00 = insertelement <8 x i16> poison, i16 %r0, i32 0
+  %r01 = insertelement <8 x i16>  %r00, i16 %r1, i32 1
+  %r02 = insertelement <8 x i16>  %r01, i16 %r2, i32 2
+  %r03 = insertelement <8 x i16>  %r02, i16 %r3, i32 3
+  %r04 = insertelement <8 x i16>  %r03, i16 %r4, i32 4
+  %r05 = insertelement <8 x i16>  %r04, i16 %r5, i32 5
+  %r06 = insertelement <8 x i16>  %r05, i16 %r6, i32 6
+  %r07 = insertelement <8 x i16>  %r06, i16 %r7, i32 7
+  ret <8 x i16> %r07
+}
+
+;
+; 256-bit vectors
+;
+
+define <4 x double> @test_v4f64(<4 x double> %a, <4 x double> %b) {
+; SSE-LABEL: @test_v4f64(
+; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> <i32 0, i32 4>
+; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> <i32 1, i32 5>
+; SSE-NEXT:    [[TMP3:%.*]] = fadd <2 x double> [[TMP1]], [[TMP2]]
+; SSE-NEXT:    [[TMP4:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> <i32 2, i32 6>
+; SSE-NEXT:    [[TMP5:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> <i32 3, i32 7>
+; SSE-NEXT:    [[TMP6:%.*]] = fadd <2 x double> [[TMP4]], [[TMP5]]
+; SSE-NEXT:    [[R03:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; SSE-NEXT:    ret <4 x double> [[R03]]
+;
+; SLM-LABEL: @test_v4f64(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <4 x double> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <4 x double> [[A]], i32 1
+; SLM-NEXT:    [[A2:%.*]] = extractelement <4 x double> [[A]], i32 2
+; SLM-NEXT:    [[A3:%.*]] = extractelement <4 x double> [[A]], i32 3
+; SLM-NEXT:    [[B0:%.*]] = extractelement <4 x double> [[B:%.*]], i32 0
+; SLM-NEXT:    [[B1:%.*]] = extractelement <4 x double> [[B]], i32 1
+; SLM-NEXT:    [[B2:%.*]] = extractelement <4 x double> [[B]], i32 2
+; SLM-NEXT:    [[B3:%.*]] = extractelement <4 x double> [[B]], i32 3
+; SLM-NEXT:    [[R0:%.*]] = fadd double [[A0]], [[A1]]
+; SLM-NEXT:    [[R1:%.*]] = fadd double [[B0]], [[B1]]
+; SLM-NEXT:    [[R2:%.*]] = fadd double [[A2]], [[A3]]
+; SLM-NEXT:    [[R3:%.*]] = fadd double [[B2]], [[B3]]
+; SLM-NEXT:    [[R00:%.*]] = insertelement <4 x double> poison, double [[R0]], i32 0
+; SLM-NEXT:    [[R01:%.*]] = insertelement <4 x double> [[R00]], double [[R1]], i32 1
+; SLM-NEXT:    [[R02:%.*]] = insertelement <4 x double> [[R01]], double [[R2]], i32 2
+; SLM-NEXT:    [[R03:%.*]] = insertelement <4 x double> [[R02]], double [[R3]], i32 3
+; SLM-NEXT:    ret <4 x double> [[R03]]
+;
+; AVX-LABEL: @test_v4f64(
+; AVX-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+; AVX-NEXT:    [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+; AVX-NEXT:    [[TMP3:%.*]] = fadd <4 x double> [[TMP1]], [[TMP2]]
+; AVX-NEXT:    ret <4 x double> [[TMP3]]
+;
+  %a0 = extractelement <4 x double> %a, i32 0
+  %a1 = extractelement <4 x double> %a, i32 1
+  %a2 = extractelement <4 x double> %a, i32 2
+  %a3 = extractelement <4 x double> %a, i32 3
+  %b0 = extractelement <4 x double> %b, i32 0
+  %b1 = extractelement <4 x double> %b, i32 1
+  %b2 = extractelement <4 x double> %b, i32 2
+  %b3 = extractelement <4 x double> %b, i32 3
+  %r0 = fadd double %a0, %a1
+  %r1 = fadd double %b0, %b1
+  %r2 = fadd double %a2, %a3
+  %r3 = fadd double %b2, %b3
+  %r00 = insertelement <4 x double> poison, double %r0, i32 0
+  %r01 = insertelement <4 x double>  %r00, double %r1, i32 1
+  %r02 = insertelement <4 x double>  %r01, double %r2, i32 2
+  %r03 = insertelement <4 x double>  %r02, double %r3, i32 3
+  ret <4 x double> %r03
+}
+
+define <8 x float> @test_v8f32(<8 x float> %a, <8 x float> %b) {
+; SSE-LABEL: @test_v8f32(
+; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
+; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
+; SSE-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
+; SSE-NEXT:    ret <8 x float> [[TMP3]]
+;
+; SLM-LABEL: @test_v8f32(
+; SLM-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <4 x i32> <i32 0, i32 2, i32 8, i32 10>
+; SLM-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <4 x i32> <i32 1, i32 3, i32 9, i32 11>
+; SLM-NEXT:    [[TMP3:%.*]] = fadd <4 x float> [[TMP1]], [[TMP2]]
+; SLM-NEXT:    [[TMP4:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <4 x i32> <i32 4, i32 6, i32 12, i32 14>
+; SLM-NEXT:    [[TMP5:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <4 x i32> <i32 5, i32 7, i32 13, i32 15>
+; SLM-NEXT:    [[TMP6:%.*]] = fadd <4 x float> [[TMP4]], [[TMP5]]
+; SLM-NEXT:    [[R07:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; SLM-NEXT:    ret <8 x float> [[R07]]
+;
+; AVX-LABEL: @test_v8f32(
+; AVX-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
+; AVX-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
+; AVX-NEXT:    [[TMP3:%.*]] = fadd <8 x float> [[TMP1]], [[TMP2]]
+; AVX-NEXT:    ret <8 x float> [[TMP3]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %b0 = extractelement <8 x float> %b, i32 0
+  %b1 = extractelement <8 x float> %b, i32 1
+  %b2 = extractelement <8 x float> %b, i32 2
+  %b3 = extractelement <8 x float> %b, i32 3
+  %b4 = extractelement <8 x float> %b, i32 4
+  %b5 = extractelement <8 x float> %b, i32 5
+  %b6 = extractelement <8 x float> %b, i32 6
+  %b7 = extractelement <8 x float> %b, i32 7
+  %r0 = fadd float %a0, %a1
+  %r1 = fadd float %a2, %a3
+  %r2 = fadd float %b0, %b1
+  %r3 = fadd float %b2, %b3
+  %r4 = fadd float %a4, %a5
+  %r5 = fadd float %a6, %a7
+  %r6 = fadd float %b4, %b5
+  %r7 = fadd float %b6, %b7
+  %r00 = insertelement <8 x float> poison, float %r0, i32 0
+  %r01 = insertelement <8 x float>  %r00, float %r1, i32 1
+  %r02 = insertelement <8 x float>  %r01, float %r2, i32 2
+  %r03 = insertelement <8 x float>  %r02, float %r3, i32 3
+  %r04 = insertelement <8 x float>  %r03, float %r4, i32 4
+  %r05 = insertelement <8 x float>  %r04, float %r5, i32 5
+  %r06 = insertelement <8 x float>  %r05, float %r6, i32 6
+  %r07 = insertelement <8 x float>  %r06, float %r7, i32 7
+  ret <8 x float> %r07
+}
+
+define <4 x i64> @test_v4i64(<4 x i64> %a, <4 x i64> %b) {
+; CHECK-LABEL: @test_v4i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i64> [[A:%.*]], <4 x i64> [[B:%.*]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i64> [[A]], <4 x i64> [[B]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+; CHECK-NEXT:    [[TMP3:%.*]] = add <4 x i64> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP3]]
+;
+  %a0 = extractelement <4 x i64> %a, i32 0
+  %a1 = extractelement <4 x i64> %a, i32 1
+  %a2 = extractelement <4 x i64> %a, i32 2
+  %a3 = extractelement <4 x i64> %a, i32 3
+  %b0 = extractelement <4 x i64> %b, i32 0
+  %b1 = extractelement <4 x i64> %b, i32 1
+  %b2 = extractelement <4 x i64> %b, i32 2
+  %b3 = extractelement <4 x i64> %b, i32 3
+  %r0 = add i64 %a0, %a1
+  %r1 = add i64 %b0, %b1
+  %r2 = add i64 %a2, %a3
+  %r3 = add i64 %b2, %b3
+  %r00 = insertelement <4 x i64> poison, i64 %r0, i32 0
+  %r01 = insertelement <4 x i64>  %r00, i64 %r1, i32 1
+  %r02 = insertelement <4 x i64>  %r01, i64 %r2, i32 2
+  %r03 = insertelement <4 x i64>  %r02, i64 %r3, i32 3
+  ret <4 x i64> %r03
+}
+
+define <8 x i32> @test_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; CHECK-LABEL: @test_v8i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
+; CHECK-NEXT:    [[TMP3:%.*]] = add <8 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP3]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %b0 = extractelement <8 x i32> %b, i32 0
+  %b1 = extractelement <8 x i32> %b, i32 1
+  %b2 = extractelement <8 x i32> %b, i32 2
+  %b3 = extractelement <8 x i32> %b, i32 3
+  %b4 = extractelement <8 x i32> %b, i32 4
+  %b5 = extractelement <8 x i32> %b, i32 5
+  %b6 = extractelement <8 x i32> %b, i32 6
+  %b7 = extractelement <8 x i32> %b, i32 7
+  %r0 = add i32 %a0, %a1
+  %r1 = add i32 %a2, %a3
+  %r2 = add i32 %b0, %b1
+  %r3 = add i32 %b2, %b3
+  %r4 = add i32 %a4, %a5
+  %r5 = add i32 %a6, %a7
+  %r6 = add i32 %b4, %b5
+  %r7 = add i32 %b6, %b7
+  %r00 = insertelement <8 x i32> poison, i32 %r0, i32 0
+  %r01 = insertelement <8 x i32>  %r00, i32 %r1, i32 1
+  %r02 = insertelement <8 x i32>  %r01, i32 %r2, i32 2
+  %r03 = insertelement <8 x i32>  %r02, i32 %r3, i32 3
+  %r04 = insertelement <8 x i32>  %r03, i32 %r4, i32 4
+  %r05 = insertelement <8 x i32>  %r04, i32 %r5, i32 5
+  %r06 = insertelement <8 x i32>  %r05, i32 %r6, i32 6
+  %r07 = insertelement <8 x i32>  %r06, i32 %r7, i32 7
+  ret <8 x i32> %r07
+}
+
+define <16 x i16> @test_v16i16(<16 x i16> %a, <16 x i16> %b) {
+; SSE-LABEL: @test_v16i16(
+; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22>
+; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23>
+; SSE-NEXT:    [[TMP3:%.*]] = add <8 x i16> [[TMP1]], [[TMP2]]
+; SSE-NEXT:    [[TMP4:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <8 x i32> <i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
+; SSE-NEXT:    [[TMP5:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <8 x i32> <i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
+; SSE-NEXT:    [[TMP6:%.*]] = add <8 x i16> [[TMP4]], [[TMP5]]
+; SSE-NEXT:    [[RV15:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> [[TMP6]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; SSE-NEXT:    ret <16 x i16> [[RV15]]
+;
+; SLM-LABEL: @test_v16i16(
+; SLM-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B:%.*]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
+; SLM-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
+; SLM-NEXT:    [[TMP3:%.*]] = add <16 x i16> [[TMP1]], [[TMP2]]
+; SLM-NEXT:    ret <16 x i16> [[TMP3]]
+;
+; AVX-LABEL: @test_v16i16(
+; AVX-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B:%.*]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
+; AVX-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
+; AVX-NEXT:    [[TMP3:%.*]] = add <16 x i16> [[TMP1]], [[TMP2]]
+; AVX-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %a0  = extractelement <16 x i16> %a, i32 0
+  %a1  = extractelement <16 x i16> %a, i32 1
+  %a2  = extractelement <16 x i16> %a, i32 2
+  %a3  = extractelement <16 x i16> %a, i32 3
+  %a4  = extractelement <16 x i16> %a, i32 4
+  %a5  = extractelement <16 x i16> %a, i32 5
+  %a6  = extractelement <16 x i16> %a, i32 6
+  %a7  = extractelement <16 x i16> %a, i32 7
+  %a8  = extractelement <16 x i16> %a, i32 8
+  %a9  = extractelement <16 x i16> %a, i32 9
+  %a10 = extractelement <16 x i16> %a, i32 10
+  %a11 = extractelement <16 x i16> %a, i32 11
+  %a12 = extractelement <16 x i16> %a, i32 12
+  %a13 = extractelement <16 x i16> %a, i32 13
+  %a14 = extractelement <16 x i16> %a, i32 14
+  %a15 = extractelement <16 x i16> %a, i32 15
+  %b0  = extractelement <16 x i16> %b, i32 0
+  %b1  = extractelement <16 x i16> %b, i32 1
+  %b2  = extractelement <16 x i16> %b, i32 2
+  %b3  = extractelement <16 x i16> %b, i32 3
+  %b4  = extractelement <16 x i16> %b, i32 4
+  %b5  = extractelement <16 x i16> %b, i32 5
+  %b6  = extractelement <16 x i16> %b, i32 6
+  %b7  = extractelement <16 x i16> %b, i32 7
+  %b8  = extractelement <16 x i16> %b, i32 8
+  %b9  = extractelement <16 x i16> %b, i32 9
+  %b10 = extractelement <16 x i16> %b, i32 10
+  %b11 = extractelement <16 x i16> %b, i32 11
+  %b12 = extractelement <16 x i16> %b, i32 12
+  %b13 = extractelement <16 x i16> %b, i32 13
+  %b14 = extractelement <16 x i16> %b, i32 14
+  %b15 = extractelement <16 x i16> %b, i32 15
+  %r0  = add i16 %a0 , %a1
+  %r1  = add i16 %a2 , %a3
+  %r2  = add i16 %a4 , %a5
+  %r3  = add i16 %a6 , %a7
+  %r4  = add i16 %b0 , %b1
+  %r5  = add i16 %b2 , %b3
+  %r6  = add i16 %b4 , %b5
+  %r7  = add i16 %b6 , %b7
+  %r8  = add i16 %a8 , %a9
+  %r9  = add i16 %a10, %a11
+  %r10 = add i16 %a12, %a13
+  %r11 = add i16 %a14, %a15
+  %r12 = add i16 %b8 , %b9
+  %r13 = add i16 %b10, %b11
+  %r14 = add i16 %b12, %b13
+  %r15 = add i16 %b14, %b15
+  %rv0  = insertelement <16 x i16> poison, i16 %r0 , i32 0
+  %rv1  = insertelement <16 x i16> %rv0 , i16 %r1 , i32 1
+  %rv2  = insertelement <16 x i16> %rv1 , i16 %r2 , i32 2
+  %rv3  = insertelement <16 x i16> %rv2 , i16 %r3 , i32 3
+  %rv4  = insertelement <16 x i16> %rv3 , i16 %r4 , i32 4
+  %rv5  = insertelement <16 x i16> %rv4 , i16 %r5 , i32 5
+  %rv6  = insertelement <16 x i16> %rv5 , i16 %r6 , i32 6
+  %rv7  = insertelement <16 x i16> %rv6 , i16 %r7 , i32 7
+  %rv8  = insertelement <16 x i16> %rv7 , i16 %r8 , i32 8
+  %rv9  = insertelement <16 x i16> %rv8 , i16 %r9 , i32 9
+  %rv10 = insertelement <16 x i16> %rv9 , i16 %r10, i32 10
+  %rv11 = insertelement <16 x i16> %rv10, i16 %r11, i32 11
+  %rv12 = insertelement <16 x i16> %rv11, i16 %r12, i32 12
+  %rv13 = insertelement <16 x i16> %rv12, i16 %r13, i32 13
+  %rv14 = insertelement <16 x i16> %rv13, i16 %r14, i32 14
+  %rv15 = insertelement <16 x i16> %rv14, i16 %r15, i32 15
+  ret <16 x i16> %rv15
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/hsub-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/hsub-inseltpoison.ll
new file mode 100644
index 0000000000000..51711dc352fa2
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/hsub-inseltpoison.ll
@@ -0,0 +1,433 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=SLM
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -basic-aa -slp-vectorizer -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
+
+;
+; 128-bit vectors
+;
+
+define <2 x double> @test_v2f64(<2 x double> %a, <2 x double> %b) {
+; SSE-LABEL: @test_v2f64(
+; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x i32> <i32 0, i32 2>
+; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i32 1, i32 3>
+; SSE-NEXT:    [[TMP3:%.*]] = fsub <2 x double> [[TMP1]], [[TMP2]]
+; SSE-NEXT:    ret <2 x double> [[TMP3]]
+;
+; SLM-LABEL: @test_v2f64(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <2 x double> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <2 x double> [[A]], i32 1
+; SLM-NEXT:    [[B0:%.*]] = extractelement <2 x double> [[B:%.*]], i32 0
+; SLM-NEXT:    [[B1:%.*]] = extractelement <2 x double> [[B]], i32 1
+; SLM-NEXT:    [[R0:%.*]] = fsub double [[A0]], [[A1]]
+; SLM-NEXT:    [[R1:%.*]] = fsub double [[B0]], [[B1]]
+; SLM-NEXT:    [[R00:%.*]] = insertelement <2 x double> poison, double [[R0]], i32 0
+; SLM-NEXT:    [[R01:%.*]] = insertelement <2 x double> [[R00]], double [[R1]], i32 1
+; SLM-NEXT:    ret <2 x double> [[R01]]
+;
+; AVX-LABEL: @test_v2f64(
+; AVX-NEXT:    [[TMP1:%.*]] = shufflevector <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x i32> <i32 0, i32 2>
+; AVX-NEXT:    [[TMP2:%.*]] = shufflevector <2 x double> [[A]], <2 x double> [[B]], <2 x i32> <i32 1, i32 3>
+; AVX-NEXT:    [[TMP3:%.*]] = fsub <2 x double> [[TMP1]], [[TMP2]]
+; AVX-NEXT:    ret <2 x double> [[TMP3]]
+;
+  %a0 = extractelement <2 x double> %a, i32 0
+  %a1 = extractelement <2 x double> %a, i32 1
+  %b0 = extractelement <2 x double> %b, i32 0
+  %b1 = extractelement <2 x double> %b, i32 1
+  %r0 = fsub double %a0, %a1
+  %r1 = fsub double %b0, %b1
+  %r00 = insertelement <2 x double> poison, double %r0, i32 0
+  %r01 = insertelement <2 x double>  %r00, double %r1, i32 1
+  ret <2 x double> %r01
+}
+
+define <4 x float> @test_v4f32(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @test_v4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x float> [[A]], <4 x float> [[B]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT:    [[TMP3:%.*]] = fsub <4 x float> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x float> [[TMP3]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %r0 = fsub float %a0, %a1
+  %r1 = fsub float %a2, %a3
+  %r2 = fsub float %b0, %b1
+  %r3 = fsub float %b2, %b3
+  %r00 = insertelement <4 x float> poison, float %r0, i32 0
+  %r01 = insertelement <4 x float>  %r00, float %r1, i32 1
+  %r02 = insertelement <4 x float>  %r01, float %r2, i32 2
+  %r03 = insertelement <4 x float>  %r02, float %r3, i32 3
+  ret <4 x float> %r03
+}
+
+define <2 x i64> @test_v2i64(<2 x i64> %a, <2 x i64> %b) {
+; CHECK-LABEL: @test_v2i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]], <2 x i32> <i32 0, i32 2>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <2 x i64> [[A]], <2 x i64> [[B]], <2 x i32> <i32 1, i32 3>
+; CHECK-NEXT:    [[TMP3:%.*]] = sub <2 x i64> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <2 x i64> [[TMP3]]
+;
+  %a0 = extractelement <2 x i64> %a, i32 0
+  %a1 = extractelement <2 x i64> %a, i32 1
+  %b0 = extractelement <2 x i64> %b, i32 0
+  %b1 = extractelement <2 x i64> %b, i32 1
+  %r0 = sub i64 %a0, %a1
+  %r1 = sub i64 %b0, %b1
+  %r00 = insertelement <2 x i64> poison, i64 %r0, i32 0
+  %r01 = insertelement <2 x i64>  %r00, i64 %r1, i32 1
+  ret <2 x i64> %r01
+}
+
+define <4 x i32> @test_v4i32(<4 x i32> %a, <4 x i32> %b) {
+; CHECK-LABEL: @test_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[B]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>
+; CHECK-NEXT:    [[TMP3:%.*]] = sub <4 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x i32> [[TMP3]]
+;
+  %a0 = extractelement <4 x i32> %a, i32 0
+  %a1 = extractelement <4 x i32> %a, i32 1
+  %a2 = extractelement <4 x i32> %a, i32 2
+  %a3 = extractelement <4 x i32> %a, i32 3
+  %b0 = extractelement <4 x i32> %b, i32 0
+  %b1 = extractelement <4 x i32> %b, i32 1
+  %b2 = extractelement <4 x i32> %b, i32 2
+  %b3 = extractelement <4 x i32> %b, i32 3
+  %r0 = sub i32 %a0, %a1
+  %r1 = sub i32 %a2, %a3
+  %r2 = sub i32 %b0, %b1
+  %r3 = sub i32 %b2, %b3
+  %r00 = insertelement <4 x i32> poison, i32 %r0, i32 0
+  %r01 = insertelement <4 x i32>  %r00, i32 %r1, i32 1
+  %r02 = insertelement <4 x i32>  %r01, i32 %r2, i32 2
+  %r03 = insertelement <4 x i32>  %r02, i32 %r3, i32 3
+  ret <4 x i32> %r03
+}
+
+define <8 x i16> @test_v8i16(<8 x i16> %a, <8 x i16> %b) {
+; CHECK-LABEL: @test_v8i16(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[B]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
+; CHECK-NEXT:    [[TMP3:%.*]] = sub <8 x i16> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <8 x i16> [[TMP3]]
+;
+  %a0 = extractelement <8 x i16> %a, i32 0
+  %a1 = extractelement <8 x i16> %a, i32 1
+  %a2 = extractelement <8 x i16> %a, i32 2
+  %a3 = extractelement <8 x i16> %a, i32 3
+  %a4 = extractelement <8 x i16> %a, i32 4
+  %a5 = extractelement <8 x i16> %a, i32 5
+  %a6 = extractelement <8 x i16> %a, i32 6
+  %a7 = extractelement <8 x i16> %a, i32 7
+  %b0 = extractelement <8 x i16> %b, i32 0
+  %b1 = extractelement <8 x i16> %b, i32 1
+  %b2 = extractelement <8 x i16> %b, i32 2
+  %b3 = extractelement <8 x i16> %b, i32 3
+  %b4 = extractelement <8 x i16> %b, i32 4
+  %b5 = extractelement <8 x i16> %b, i32 5
+  %b6 = extractelement <8 x i16> %b, i32 6
+  %b7 = extractelement <8 x i16> %b, i32 7
+  %r0 = sub i16 %a0, %a1
+  %r1 = sub i16 %a2, %a3
+  %r2 = sub i16 %a4, %a5
+  %r3 = sub i16 %a6, %a7
+  %r4 = sub i16 %b0, %b1
+  %r5 = sub i16 %b2, %b3
+  %r6 = sub i16 %b4, %b5
+  %r7 = sub i16 %b6, %b7
+  %r00 = insertelement <8 x i16> poison, i16 %r0, i32 0
+  %r01 = insertelement <8 x i16>  %r00, i16 %r1, i32 1
+  %r02 = insertelement <8 x i16>  %r01, i16 %r2, i32 2
+  %r03 = insertelement <8 x i16>  %r02, i16 %r3, i32 3
+  %r04 = insertelement <8 x i16>  %r03, i16 %r4, i32 4
+  %r05 = insertelement <8 x i16>  %r04, i16 %r5, i32 5
+  %r06 = insertelement <8 x i16>  %r05, i16 %r6, i32 6
+  %r07 = insertelement <8 x i16>  %r06, i16 %r7, i32 7
+  ret <8 x i16> %r07
+}
+
+;
+; 256-bit vectors
+;
+
+define <4 x double> @test_v4f64(<4 x double> %a, <4 x double> %b) {
+; SSE-LABEL: @test_v4f64(
+; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <2 x i32> <i32 0, i32 4>
+; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> <i32 1, i32 5>
+; SSE-NEXT:    [[TMP3:%.*]] = fsub <2 x double> [[TMP1]], [[TMP2]]
+; SSE-NEXT:    [[TMP4:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> <i32 2, i32 6>
+; SSE-NEXT:    [[TMP5:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <2 x i32> <i32 3, i32 7>
+; SSE-NEXT:    [[TMP6:%.*]] = fsub <2 x double> [[TMP4]], [[TMP5]]
+; SSE-NEXT:    [[R03:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP6]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+; SSE-NEXT:    ret <4 x double> [[R03]]
+;
+; SLM-LABEL: @test_v4f64(
+; SLM-NEXT:    [[A0:%.*]] = extractelement <4 x double> [[A:%.*]], i32 0
+; SLM-NEXT:    [[A1:%.*]] = extractelement <4 x double> [[A]], i32 1
+; SLM-NEXT:    [[A2:%.*]] = extractelement <4 x double> [[A]], i32 2
+; SLM-NEXT:    [[A3:%.*]] = extractelement <4 x double> [[A]], i32 3
+; SLM-NEXT:    [[B0:%.*]] = extractelement <4 x double> [[B:%.*]], i32 0
+; SLM-NEXT:    [[B1:%.*]] = extractelement <4 x double> [[B]], i32 1
+; SLM-NEXT:    [[B2:%.*]] = extractelement <4 x double> [[B]], i32 2
+; SLM-NEXT:    [[B3:%.*]] = extractelement <4 x double> [[B]], i32 3
+; SLM-NEXT:    [[R0:%.*]] = fsub double [[A0]], [[A1]]
+; SLM-NEXT:    [[R1:%.*]] = fsub double [[B0]], [[B1]]
+; SLM-NEXT:    [[R2:%.*]] = fsub double [[A2]], [[A3]]
+; SLM-NEXT:    [[R3:%.*]] = fsub double [[B2]], [[B3]]
+; SLM-NEXT:    [[R00:%.*]] = insertelement <4 x double> poison, double [[R0]], i32 0
+; SLM-NEXT:    [[R01:%.*]] = insertelement <4 x double> [[R00]], double [[R1]], i32 1
+; SLM-NEXT:    [[R02:%.*]] = insertelement <4 x double> [[R01]], double [[R2]], i32 2
+; SLM-NEXT:    [[R03:%.*]] = insertelement <4 x double> [[R02]], double [[R3]], i32 3
+; SLM-NEXT:    ret <4 x double> [[R03]]
+;
+; AVX-LABEL: @test_v4f64(
+; AVX-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[A:%.*]], <4 x double> [[B:%.*]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+; AVX-NEXT:    [[TMP2:%.*]] = shufflevector <4 x double> [[A]], <4 x double> [[B]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+; AVX-NEXT:    [[TMP3:%.*]] = fsub <4 x double> [[TMP1]], [[TMP2]]
+; AVX-NEXT:    ret <4 x double> [[TMP3]]
+;
+  %a0 = extractelement <4 x double> %a, i32 0
+  %a1 = extractelement <4 x double> %a, i32 1
+  %a2 = extractelement <4 x double> %a, i32 2
+  %a3 = extractelement <4 x double> %a, i32 3
+  %b0 = extractelement <4 x double> %b, i32 0
+  %b1 = extractelement <4 x double> %b, i32 1
+  %b2 = extractelement <4 x double> %b, i32 2
+  %b3 = extractelement <4 x double> %b, i32 3
+  %r0 = fsub double %a0, %a1
+  %r1 = fsub double %b0, %b1
+  %r2 = fsub double %a2, %a3
+  %r3 = fsub double %b2, %b3
+  %r00 = insertelement <4 x double> poison, double %r0, i32 0
+  %r01 = insertelement <4 x double>  %r00, double %r1, i32 1
+  %r02 = insertelement <4 x double>  %r01, double %r2, i32 2
+  %r03 = insertelement <4 x double>  %r02, double %r3, i32 3
+  ret <4 x double> %r03
+}
+
+define <8 x float> @test_v8f32(<8 x float> %a, <8 x float> %b) {
+; SSE-LABEL: @test_v8f32(
+; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
+; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
+; SSE-NEXT:    [[TMP3:%.*]] = fsub <8 x float> [[TMP1]], [[TMP2]]
+; SSE-NEXT:    ret <8 x float> [[TMP3]]
+;
+; SLM-LABEL: @test_v8f32(
+; SLM-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <4 x i32> <i32 0, i32 2, i32 8, i32 10>
+; SLM-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <4 x i32> <i32 1, i32 3, i32 9, i32 11>
+; SLM-NEXT:    [[TMP3:%.*]] = fsub <4 x float> [[TMP1]], [[TMP2]]
+; SLM-NEXT:    [[TMP4:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <4 x i32> <i32 4, i32 6, i32 12, i32 14>
+; SLM-NEXT:    [[TMP5:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <4 x i32> <i32 5, i32 7, i32 13, i32 15>
+; SLM-NEXT:    [[TMP6:%.*]] = fsub <4 x float> [[TMP4]], [[TMP5]]
+; SLM-NEXT:    [[R07:%.*]] = shufflevector <4 x float> [[TMP3]], <4 x float> [[TMP6]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+; SLM-NEXT:    ret <8 x float> [[R07]]
+;
+; AVX-LABEL: @test_v8f32(
+; AVX-NEXT:    [[TMP1:%.*]] = shufflevector <8 x float> [[A:%.*]], <8 x float> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
+; AVX-NEXT:    [[TMP2:%.*]] = shufflevector <8 x float> [[A]], <8 x float> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
+; AVX-NEXT:    [[TMP3:%.*]] = fsub <8 x float> [[TMP1]], [[TMP2]]
+; AVX-NEXT:    ret <8 x float> [[TMP3]]
+;
+  %a0 = extractelement <8 x float> %a, i32 0
+  %a1 = extractelement <8 x float> %a, i32 1
+  %a2 = extractelement <8 x float> %a, i32 2
+  %a3 = extractelement <8 x float> %a, i32 3
+  %a4 = extractelement <8 x float> %a, i32 4
+  %a5 = extractelement <8 x float> %a, i32 5
+  %a6 = extractelement <8 x float> %a, i32 6
+  %a7 = extractelement <8 x float> %a, i32 7
+  %b0 = extractelement <8 x float> %b, i32 0
+  %b1 = extractelement <8 x float> %b, i32 1
+  %b2 = extractelement <8 x float> %b, i32 2
+  %b3 = extractelement <8 x float> %b, i32 3
+  %b4 = extractelement <8 x float> %b, i32 4
+  %b5 = extractelement <8 x float> %b, i32 5
+  %b6 = extractelement <8 x float> %b, i32 6
+  %b7 = extractelement <8 x float> %b, i32 7
+  %r0 = fsub float %a0, %a1
+  %r1 = fsub float %a2, %a3
+  %r2 = fsub float %b0, %b1
+  %r3 = fsub float %b2, %b3
+  %r4 = fsub float %a4, %a5
+  %r5 = fsub float %a6, %a7
+  %r6 = fsub float %b4, %b5
+  %r7 = fsub float %b6, %b7
+  %r00 = insertelement <8 x float> poison, float %r0, i32 0
+  %r01 = insertelement <8 x float>  %r00, float %r1, i32 1
+  %r02 = insertelement <8 x float>  %r01, float %r2, i32 2
+  %r03 = insertelement <8 x float>  %r02, float %r3, i32 3
+  %r04 = insertelement <8 x float>  %r03, float %r4, i32 4
+  %r05 = insertelement <8 x float>  %r04, float %r5, i32 5
+  %r06 = insertelement <8 x float>  %r05, float %r6, i32 6
+  %r07 = insertelement <8 x float>  %r06, float %r7, i32 7
+  ret <8 x float> %r07
+}
+
+define <4 x i64> @test_v4i64(<4 x i64> %a, <4 x i64> %b) {
+; CHECK-LABEL: @test_v4i64(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x i64> [[A:%.*]], <4 x i64> [[B:%.*]], <4 x i32> <i32 0, i32 4, i32 2, i32 6>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i64> [[A]], <4 x i64> [[B]], <4 x i32> <i32 1, i32 5, i32 3, i32 7>
+; CHECK-NEXT:    [[TMP3:%.*]] = sub <4 x i64> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <4 x i64> [[TMP3]]
+;
+  %a0 = extractelement <4 x i64> %a, i32 0
+  %a1 = extractelement <4 x i64> %a, i32 1
+  %a2 = extractelement <4 x i64> %a, i32 2
+  %a3 = extractelement <4 x i64> %a, i32 3
+  %b0 = extractelement <4 x i64> %b, i32 0
+  %b1 = extractelement <4 x i64> %b, i32 1
+  %b2 = extractelement <4 x i64> %b, i32 2
+  %b3 = extractelement <4 x i64> %b, i32 3
+  %r0 = sub i64 %a0, %a1
+  %r1 = sub i64 %b0, %b1
+  %r2 = sub i64 %a2, %a3
+  %r3 = sub i64 %b2, %b3
+  %r00 = insertelement <4 x i64> poison, i64 %r0, i32 0
+  %r01 = insertelement <4 x i64>  %r00, i64 %r1, i32 1
+  %r02 = insertelement <4 x i64>  %r01, i64 %r2, i32 2
+  %r03 = insertelement <4 x i64>  %r02, i64 %r3, i32 3
+  ret <4 x i64> %r03
+}
+
+define <8 x i32> @test_v8i32(<8 x i32> %a, <8 x i32> %b) {
+; CHECK-LABEL: @test_v8i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
+; CHECK-NEXT:    [[TMP2:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> [[B]], <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
+; CHECK-NEXT:    [[TMP3:%.*]] = sub <8 x i32> [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    ret <8 x i32> [[TMP3]]
+;
+  %a0 = extractelement <8 x i32> %a, i32 0
+  %a1 = extractelement <8 x i32> %a, i32 1
+  %a2 = extractelement <8 x i32> %a, i32 2
+  %a3 = extractelement <8 x i32> %a, i32 3
+  %a4 = extractelement <8 x i32> %a, i32 4
+  %a5 = extractelement <8 x i32> %a, i32 5
+  %a6 = extractelement <8 x i32> %a, i32 6
+  %a7 = extractelement <8 x i32> %a, i32 7
+  %b0 = extractelement <8 x i32> %b, i32 0
+  %b1 = extractelement <8 x i32> %b, i32 1
+  %b2 = extractelement <8 x i32> %b, i32 2
+  %b3 = extractelement <8 x i32> %b, i32 3
+  %b4 = extractelement <8 x i32> %b, i32 4
+  %b5 = extractelement <8 x i32> %b, i32 5
+  %b6 = extractelement <8 x i32> %b, i32 6
+  %b7 = extractelement <8 x i32> %b, i32 7
+  %r0 = sub i32 %a0, %a1
+  %r1 = sub i32 %a2, %a3
+  %r2 = sub i32 %b0, %b1
+  %r3 = sub i32 %b2, %b3
+  %r4 = sub i32 %a4, %a5
+  %r5 = sub i32 %a6, %a7
+  %r6 = sub i32 %b4, %b5
+  %r7 = sub i32 %b6, %b7
+  %r00 = insertelement <8 x i32> poison, i32 %r0, i32 0
+  %r01 = insertelement <8 x i32>  %r00, i32 %r1, i32 1
+  %r02 = insertelement <8 x i32>  %r01, i32 %r2, i32 2
+  %r03 = insertelement <8 x i32>  %r02, i32 %r3, i32 3
+  %r04 = insertelement <8 x i32>  %r03, i32 %r4, i32 4
+  %r05 = insertelement <8 x i32>  %r04, i32 %r5, i32 5
+  %r06 = insertelement <8 x i32>  %r05, i32 %r6, i32 6
+  %r07 = insertelement <8 x i32>  %r06, i32 %r7, i32 7
+  ret <8 x i32> %r07
+}
+
+define <16 x i16> @test_v16i16(<16 x i16> %a, <16 x i16> %b) {
+; SSE-LABEL: @test_v16i16(
+; SSE-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B:%.*]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22>
+; SSE-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23>
+; SSE-NEXT:    [[TMP3:%.*]] = sub <8 x i16> [[TMP1]], [[TMP2]]
+; SSE-NEXT:    [[TMP4:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <8 x i32> <i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
+; SSE-NEXT:    [[TMP5:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <8 x i32> <i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
+; SSE-NEXT:    [[TMP6:%.*]] = sub <8 x i16> [[TMP4]], [[TMP5]]
+; SSE-NEXT:    [[RV15:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> [[TMP6]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+; SSE-NEXT:    ret <16 x i16> [[RV15]]
+;
+; SLM-LABEL: @test_v16i16(
+; SLM-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B:%.*]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
+; SLM-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
+; SLM-NEXT:    [[TMP3:%.*]] = sub <16 x i16> [[TMP1]], [[TMP2]]
+; SLM-NEXT:    ret <16 x i16> [[TMP3]]
+;
+; AVX-LABEL: @test_v16i16(
+; AVX-NEXT:    [[TMP1:%.*]] = shufflevector <16 x i16> [[A:%.*]], <16 x i16> [[B:%.*]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
+; AVX-NEXT:    [[TMP2:%.*]] = shufflevector <16 x i16> [[A]], <16 x i16> [[B]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
+; AVX-NEXT:    [[TMP3:%.*]] = sub <16 x i16> [[TMP1]], [[TMP2]]
+; AVX-NEXT:    ret <16 x i16> [[TMP3]]
+;
+  %a0  = extractelement <16 x i16> %a, i32 0
+  %a1  = extractelement <16 x i16> %a, i32 1
+  %a2  = extractelement <16 x i16> %a, i32 2
+  %a3  = extractelement <16 x i16> %a, i32 3
+  %a4  = extractelement <16 x i16> %a, i32 4
+  %a5  = extractelement <16 x i16> %a, i32 5
+  %a6  = extractelement <16 x i16> %a, i32 6
+  %a7  = extractelement <16 x i16> %a, i32 7
+  %a8  = extractelement <16 x i16> %a, i32 8
+  %a9  = extractelement <16 x i16> %a, i32 9
+  %a10 = extractelement <16 x i16> %a, i32 10
+  %a11 = extractelement <16 x i16> %a, i32 11
+  %a12 = extractelement <16 x i16> %a, i32 12
+  %a13 = extractelement <16 x i16> %a, i32 13
+  %a14 = extractelement <16 x i16> %a, i32 14
+  %a15 = extractelement <16 x i16> %a, i32 15
+  %b0  = extractelement <16 x i16> %b, i32 0
+  %b1  = extractelement <16 x i16> %b, i32 1
+  %b2  = extractelement <16 x i16> %b, i32 2
+  %b3  = extractelement <16 x i16> %b, i32 3
+  %b4  = extractelement <16 x i16> %b, i32 4
+  %b5  = extractelement <16 x i16> %b, i32 5
+  %b6  = extractelement <16 x i16> %b, i32 6
+  %b7  = extractelement <16 x i16> %b, i32 7
+  %b8  = extractelement <16 x i16> %b, i32 8
+  %b9  = extractelement <16 x i16> %b, i32 9
+  %b10 = extractelement <16 x i16> %b, i32 10
+  %b11 = extractelement <16 x i16> %b, i32 11
+  %b12 = extractelement <16 x i16> %b, i32 12
+  %b13 = extractelement <16 x i16> %b, i32 13
+  %b14 = extractelement <16 x i16> %b, i32 14
+  %b15 = extractelement <16 x i16> %b, i32 15
+  %r0  = sub i16 %a0 , %a1
+  %r1  = sub i16 %a2 , %a3
+  %r2  = sub i16 %a4 , %a5
+  %r3  = sub i16 %a6 , %a7
+  %r4  = sub i16 %b0 , %b1
+  %r5  = sub i16 %b2 , %b3
+  %r6  = sub i16 %b4 , %b5
+  %r7  = sub i16 %b6 , %b7
+  %r8  = sub i16 %a8 , %a9
+  %r9  = sub i16 %a10, %a11
+  %r10 = sub i16 %a12, %a13
+  %r11 = sub i16 %a14, %a15
+  %r12 = sub i16 %b8 , %b9
+  %r13 = sub i16 %b10, %b11
+  %r14 = sub i16 %b12, %b13
+  %r15 = sub i16 %b14, %b15
+  %rv0  = insertelement <16 x i16> poison, i16 %r0 , i32 0
+  %rv1  = insertelement <16 x i16> %rv0 , i16 %r1 , i32 1
+  %rv2  = insertelement <16 x i16> %rv1 , i16 %r2 , i32 2
+  %rv3  = insertelement <16 x i16> %rv2 , i16 %r3 , i32 3
+  %rv4  = insertelement <16 x i16> %rv3 , i16 %r4 , i32 4
+  %rv5  = insertelement <16 x i16> %rv4 , i16 %r5 , i32 5
+  %rv6  = insertelement <16 x i16> %rv5 , i16 %r6 , i32 6
+  %rv7  = insertelement <16 x i16> %rv6 , i16 %r7 , i32 7
+  %rv8  = insertelement <16 x i16> %rv7 , i16 %r8 , i32 8
+  %rv9  = insertelement <16 x i16> %rv8 , i16 %r9 , i32 9
+  %rv10 = insertelement <16 x i16> %rv9 , i16 %r10, i32 10
+  %rv11 = insertelement <16 x i16> %rv10, i16 %r11, i32 11
+  %rv12 = insertelement <16 x i16> %rv11, i16 %r12, i32 12
+  %rv13 = insertelement <16 x i16> %rv12, i16 %r13, i32 13
+  %rv14 = insertelement <16 x i16> %rv13, i16 %r14, i32 14
+  %rv15 = insertelement <16 x i16> %rv14, i16 %r15, i32 15
+  ret <16 x i16> %rv15
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll
new file mode 100644
index 0000000000000..003db8629786c
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/insert-element-build-vector-inseltpoison.ll
@@ -0,0 +1,540 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -slp-vectorizer -slp-threshold=-10000 < %s | FileCheck %s
+; RUN: opt -S -slp-vectorizer -slp-threshold=0 < %s | FileCheck %s
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-n8:16:32:64-S128"
+target triple = "x86_64-apple-macosx10.8.0"
+
+define <4 x float> @simple_select(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @simple_select(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[C:%.*]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    [[RA:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP2]], i32 1
+; CHECK-NEXT:    [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[TMP4]], i32 1
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
+; CHECK-NEXT:    [[RC:%.*]] = insertelement <4 x float> [[RB]], float [[TMP5]], i32 2
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
+; CHECK-NEXT:    [[RD:%.*]] = insertelement <4 x float> [[RC]], float [[TMP6]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[RD]]
+;
+  %c0 = extractelement <4 x i32> %c, i32 0
+  %c1 = extractelement <4 x i32> %c, i32 1
+  %c2 = extractelement <4 x i32> %c, i32 2
+  %c3 = extractelement <4 x i32> %c, i32 3
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %cmp0 = icmp ne i32 %c0, 0
+  %cmp1 = icmp ne i32 %c1, 0
+  %cmp2 = icmp ne i32 %c2, 0
+  %cmp3 = icmp ne i32 %c3, 0
+  %s0 = select i1 %cmp0, float %a0, float %b0
+  %s1 = select i1 %cmp1, float %a1, float %b1
+  %s2 = select i1 %cmp2, float %a2, float %b2
+  %s3 = select i1 %cmp3, float %a3, float %b3
+  %ra = insertelement <4 x float> poison, float %s0, i32 0
+  %rb = insertelement <4 x float> %ra, float %s1, i32 1
+  %rc = insertelement <4 x float> %rb, float %s2, i32 2
+  %rd = insertelement <4 x float> %rc, float %s3, i32 3
+  ret <4 x float> %rd
+}
+
+declare void @llvm.assume(i1) nounwind
+
+; This entire tree is ephemeral, don't vectorize any of it.
+define <4 x float> @simple_select_eph(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @simple_select_eph(
+; CHECK-NEXT:    [[C0:%.*]] = extractelement <4 x i32> [[C:%.*]], i32 0
+; CHECK-NEXT:    [[C1:%.*]] = extractelement <4 x i32> [[C]], i32 1
+; CHECK-NEXT:    [[C2:%.*]] = extractelement <4 x i32> [[C]], i32 2
+; CHECK-NEXT:    [[C3:%.*]] = extractelement <4 x i32> [[C]], i32 3
+; CHECK-NEXT:    [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
+; CHECK-NEXT:    [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
+; CHECK-NEXT:    [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
+; CHECK-NEXT:    [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
+; CHECK-NEXT:    [[B0:%.*]] = extractelement <4 x float> [[B:%.*]], i32 0
+; CHECK-NEXT:    [[B1:%.*]] = extractelement <4 x float> [[B]], i32 1
+; CHECK-NEXT:    [[B2:%.*]] = extractelement <4 x float> [[B]], i32 2
+; CHECK-NEXT:    [[B3:%.*]] = extractelement <4 x float> [[B]], i32 3
+; CHECK-NEXT:    [[CMP0:%.*]] = icmp ne i32 [[C0]], 0
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[C1]], 0
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[C2]], 0
+; CHECK-NEXT:    [[CMP3:%.*]] = icmp ne i32 [[C3]], 0
+; CHECK-NEXT:    [[S0:%.*]] = select i1 [[CMP0]], float [[A0]], float [[B0]]
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[CMP1]], float [[A1]], float [[B1]]
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[CMP2]], float [[A2]], float [[B2]]
+; CHECK-NEXT:    [[S3:%.*]] = select i1 [[CMP3]], float [[A3]], float [[B3]]
+; CHECK-NEXT:    [[RA:%.*]] = insertelement <4 x float> poison, float [[S0]], i32 0
+; CHECK-NEXT:    [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[S1]], i32 1
+; CHECK-NEXT:    [[RC:%.*]] = insertelement <4 x float> [[RB]], float [[S2]], i32 2
+; CHECK-NEXT:    [[RD:%.*]] = insertelement <4 x float> [[RC]], float [[S3]], i32 3
+; CHECK-NEXT:    [[Q0:%.*]] = extractelement <4 x float> [[RD]], i32 0
+; CHECK-NEXT:    [[Q1:%.*]] = extractelement <4 x float> [[RD]], i32 1
+; CHECK-NEXT:    [[Q2:%.*]] = extractelement <4 x float> [[RD]], i32 2
+; CHECK-NEXT:    [[Q3:%.*]] = extractelement <4 x float> [[RD]], i32 3
+; CHECK-NEXT:    [[Q4:%.*]] = fadd float [[Q0]], [[Q1]]
+; CHECK-NEXT:    [[Q5:%.*]] = fadd float [[Q2]], [[Q3]]
+; CHECK-NEXT:    [[Q6:%.*]] = fadd float [[Q4]], [[Q5]]
+; CHECK-NEXT:    [[QI:%.*]] = fcmp olt float [[Q6]], [[Q5]]
+; CHECK-NEXT:    call void @llvm.assume(i1 [[QI]])
+; CHECK-NEXT:    ret <4 x float> undef
+;
+  %c0 = extractelement <4 x i32> %c, i32 0
+  %c1 = extractelement <4 x i32> %c, i32 1
+  %c2 = extractelement <4 x i32> %c, i32 2
+  %c3 = extractelement <4 x i32> %c, i32 3
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %cmp0 = icmp ne i32 %c0, 0
+  %cmp1 = icmp ne i32 %c1, 0
+  %cmp2 = icmp ne i32 %c2, 0
+  %cmp3 = icmp ne i32 %c3, 0
+  %s0 = select i1 %cmp0, float %a0, float %b0
+  %s1 = select i1 %cmp1, float %a1, float %b1
+  %s2 = select i1 %cmp2, float %a2, float %b2
+  %s3 = select i1 %cmp3, float %a3, float %b3
+  %ra = insertelement <4 x float> poison, float %s0, i32 0
+  %rb = insertelement <4 x float> %ra, float %s1, i32 1
+  %rc = insertelement <4 x float> %rb, float %s2, i32 2
+  %rd = insertelement <4 x float> %rc, float %s3, i32 3
+  %q0 = extractelement <4 x float> %rd, i32 0
+  %q1 = extractelement <4 x float> %rd, i32 1
+  %q2 = extractelement <4 x float> %rd, i32 2
+  %q3 = extractelement <4 x float> %rd, i32 3
+  %q4 = fadd float %q0, %q1
+  %q5 = fadd float %q2, %q3
+  %q6 = fadd float %q4, %q5
+  %qi = fcmp olt float %q6, %q5
+  call void @llvm.assume(i1 %qi)
+  ret <4 x float> undef
+}
+
+; Insert in an order different from the vector indices to make sure it
+; doesn't matter
+define <4 x float> @simple_select_insert_out_of_order(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @simple_select_insert_out_of_order(
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[C:%.*]], <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
+; CHECK-NEXT:    [[SHUFFLE1:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
+; CHECK-NEXT:    [[SHUFFLE2:%.*]] = shufflevector <4 x float> [[B:%.*]], <4 x float> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[SHUFFLE]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[SHUFFLE1]], <4 x float> [[SHUFFLE2]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
+; CHECK-NEXT:    [[RA:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i32 2
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP2]], i32 1
+; CHECK-NEXT:    [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[TMP4]], i32 1
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    [[RC:%.*]] = insertelement <4 x float> [[RB]], float [[TMP5]], i32 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
+; CHECK-NEXT:    [[RD:%.*]] = insertelement <4 x float> [[RC]], float [[TMP6]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[RD]]
+;
+  %c0 = extractelement <4 x i32> %c, i32 0
+  %c1 = extractelement <4 x i32> %c, i32 1
+  %c2 = extractelement <4 x i32> %c, i32 2
+  %c3 = extractelement <4 x i32> %c, i32 3
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %cmp0 = icmp ne i32 %c0, 0
+  %cmp1 = icmp ne i32 %c1, 0
+  %cmp2 = icmp ne i32 %c2, 0
+  %cmp3 = icmp ne i32 %c3, 0
+  %s0 = select i1 %cmp0, float %a0, float %b0
+  %s1 = select i1 %cmp1, float %a1, float %b1
+  %s2 = select i1 %cmp2, float %a2, float %b2
+  %s3 = select i1 %cmp3, float %a3, float %b3
+  %ra = insertelement <4 x float> poison, float %s0, i32 2
+  %rb = insertelement <4 x float> %ra, float %s1, i32 1
+  %rc = insertelement <4 x float> %rb, float %s2, i32 0
+  %rd = insertelement <4 x float> %rc, float %s3, i32 3
+  ret <4 x float> %rd
+}
+
+declare void @v4f32_user(<4 x float>) #0
+declare void @f32_user(float) #0
+
+; Multiple users of the final constructed vector
+define <4 x float> @simple_select_users(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @simple_select_users(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <4 x i32> [[C:%.*]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    [[RA:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP2]], i32 1
+; CHECK-NEXT:    [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[TMP4]], i32 1
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP2]], i32 2
+; CHECK-NEXT:    [[RC:%.*]] = insertelement <4 x float> [[RB]], float [[TMP5]], i32 2
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP2]], i32 3
+; CHECK-NEXT:    [[RD:%.*]] = insertelement <4 x float> [[RC]], float [[TMP6]], i32 3
+; CHECK-NEXT:    call void @v4f32_user(<4 x float> [[RD]]) [[ATTR0:#.*]]
+; CHECK-NEXT:    ret <4 x float> [[RD]]
+;
+  %c0 = extractelement <4 x i32> %c, i32 0
+  %c1 = extractelement <4 x i32> %c, i32 1
+  %c2 = extractelement <4 x i32> %c, i32 2
+  %c3 = extractelement <4 x i32> %c, i32 3
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %cmp0 = icmp ne i32 %c0, 0
+  %cmp1 = icmp ne i32 %c1, 0
+  %cmp2 = icmp ne i32 %c2, 0
+  %cmp3 = icmp ne i32 %c3, 0
+  %s0 = select i1 %cmp0, float %a0, float %b0
+  %s1 = select i1 %cmp1, float %a1, float %b1
+  %s2 = select i1 %cmp2, float %a2, float %b2
+  %s3 = select i1 %cmp3, float %a3, float %b3
+  %ra = insertelement <4 x float> poison, float %s0, i32 0
+  %rb = insertelement <4 x float> %ra, float %s1, i32 1
+  %rc = insertelement <4 x float> %rb, float %s2, i32 2
+  %rd = insertelement <4 x float> %rc, float %s3, i32 3
+  call void @v4f32_user(<4 x float> %rd) #0
+  ret <4 x float> %rd
+}
+
+; Unused insertelement
+define <4 x float> @simple_select_no_users(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @simple_select_no_users(
+; CHECK-NEXT:    [[C0:%.*]] = extractelement <4 x i32> [[C:%.*]], i32 0
+; CHECK-NEXT:    [[C1:%.*]] = extractelement <4 x i32> [[C]], i32 1
+; CHECK-NEXT:    [[C2:%.*]] = extractelement <4 x i32> [[C]], i32 2
+; CHECK-NEXT:    [[C3:%.*]] = extractelement <4 x i32> [[C]], i32 3
+; CHECK-NEXT:    [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
+; CHECK-NEXT:    [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
+; CHECK-NEXT:    [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
+; CHECK-NEXT:    [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
+; CHECK-NEXT:    [[B0:%.*]] = extractelement <4 x float> [[B:%.*]], i32 0
+; CHECK-NEXT:    [[B1:%.*]] = extractelement <4 x float> [[B]], i32 1
+; CHECK-NEXT:    [[B2:%.*]] = extractelement <4 x float> [[B]], i32 2
+; CHECK-NEXT:    [[B3:%.*]] = extractelement <4 x float> [[B]], i32 3
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i32> undef, i32 [[C0]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[C1]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x i32> undef, i32 [[C2]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <2 x i32> [[TMP4]], i32 [[C3]], i32 1
+; CHECK-NEXT:    [[TMP6:%.*]] = icmp ne <2 x i32> [[TMP5]], zeroinitializer
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <2 x float> undef, float [[A0]], i32 0
+; CHECK-NEXT:    [[TMP8:%.*]] = insertelement <2 x float> [[TMP7]], float [[A1]], i32 1
+; CHECK-NEXT:    [[TMP9:%.*]] = insertelement <2 x float> undef, float [[B0]], i32 0
+; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <2 x float> [[TMP9]], float [[B1]], i32 1
+; CHECK-NEXT:    [[TMP11:%.*]] = select <2 x i1> [[TMP3]], <2 x float> [[TMP8]], <2 x float> [[TMP10]]
+; CHECK-NEXT:    [[TMP12:%.*]] = insertelement <2 x float> undef, float [[A2]], i32 0
+; CHECK-NEXT:    [[TMP13:%.*]] = insertelement <2 x float> [[TMP12]], float [[A3]], i32 1
+; CHECK-NEXT:    [[TMP14:%.*]] = insertelement <2 x float> undef, float [[B2]], i32 0
+; CHECK-NEXT:    [[TMP15:%.*]] = insertelement <2 x float> [[TMP14]], float [[B3]], i32 1
+; CHECK-NEXT:    [[TMP16:%.*]] = select <2 x i1> [[TMP6]], <2 x float> [[TMP13]], <2 x float> [[TMP15]]
+; CHECK-NEXT:    [[TMP17:%.*]] = extractelement <2 x float> [[TMP11]], i32 0
+; CHECK-NEXT:    [[RA:%.*]] = insertelement <4 x float> poison, float [[TMP17]], i32 0
+; CHECK-NEXT:    [[TMP18:%.*]] = extractelement <2 x float> [[TMP11]], i32 1
+; CHECK-NEXT:    [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[TMP18]], i32 1
+; CHECK-NEXT:    [[TMP19:%.*]] = extractelement <2 x float> [[TMP16]], i32 0
+; CHECK-NEXT:    [[RC:%.*]] = insertelement <4 x float> poison, float [[TMP19]], i32 2
+; CHECK-NEXT:    [[TMP20:%.*]] = extractelement <2 x float> [[TMP16]], i32 1
+; CHECK-NEXT:    [[RD:%.*]] = insertelement <4 x float> [[RC]], float [[TMP20]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[RD]]
+;
+  %c0 = extractelement <4 x i32> %c, i32 0
+  %c1 = extractelement <4 x i32> %c, i32 1
+  %c2 = extractelement <4 x i32> %c, i32 2
+  %c3 = extractelement <4 x i32> %c, i32 3
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+  %cmp0 = icmp ne i32 %c0, 0
+  %cmp1 = icmp ne i32 %c1, 0
+  %cmp2 = icmp ne i32 %c2, 0
+  %cmp3 = icmp ne i32 %c3, 0
+  %s0 = select i1 %cmp0, float %a0, float %b0
+  %s1 = select i1 %cmp1, float %a1, float %b1
+  %s2 = select i1 %cmp2, float %a2, float %b2
+  %s3 = select i1 %cmp3, float %a3, float %b3
+  %ra = insertelement <4 x float> poison, float %s0, i32 0
+  %rb = insertelement <4 x float> %ra, float %s1, i32 1
+  %rc = insertelement <4 x float> poison, float %s2, i32 2
+  %rd = insertelement <4 x float> %rc, float %s3, i32 3
+  ret <4 x float> %rd
+}
+
+; Make sure infinite loop doesn't happen which I ran into when trying
+; to do this backwards this backwards
+define <4 x i32> @reconstruct(<4 x i32> %c) #0 {
+; CHECK-LABEL: @reconstruct(
+; CHECK-NEXT:    [[C0:%.*]] = extractelement <4 x i32> [[C:%.*]], i32 0
+; CHECK-NEXT:    [[C1:%.*]] = extractelement <4 x i32> [[C]], i32 1
+; CHECK-NEXT:    [[C2:%.*]] = extractelement <4 x i32> [[C]], i32 2
+; CHECK-NEXT:    [[C3:%.*]] = extractelement <4 x i32> [[C]], i32 3
+; CHECK-NEXT:    [[RA:%.*]] = insertelement <4 x i32> poison, i32 [[C0]], i32 0
+; CHECK-NEXT:    [[RB:%.*]] = insertelement <4 x i32> [[RA]], i32 [[C1]], i32 1
+; CHECK-NEXT:    [[RC:%.*]] = insertelement <4 x i32> [[RB]], i32 [[C2]], i32 2
+; CHECK-NEXT:    [[RD:%.*]] = insertelement <4 x i32> [[RC]], i32 [[C3]], i32 3
+; CHECK-NEXT:    ret <4 x i32> [[RD]]
+;
+  %c0 = extractelement <4 x i32> %c, i32 0
+  %c1 = extractelement <4 x i32> %c, i32 1
+  %c2 = extractelement <4 x i32> %c, i32 2
+  %c3 = extractelement <4 x i32> %c, i32 3
+  %ra = insertelement <4 x i32> poison, i32 %c0, i32 0
+  %rb = insertelement <4 x i32> %ra, i32 %c1, i32 1
+  %rc = insertelement <4 x i32> %rb, i32 %c2, i32 2
+  %rd = insertelement <4 x i32> %rc, i32 %c3, i32 3
+  ret <4 x i32> %rd
+}
+
+define <2 x float> @simple_select_v2(<2 x float> %a, <2 x float> %b, <2 x i32> %c) #0 {
+; CHECK-LABEL: @simple_select_v2(
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ne <2 x i32> [[C:%.*]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x float> [[A:%.*]], <2 x float> [[B:%.*]]
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    [[RA:%.*]] = insertelement <2 x float> poison, float [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; CHECK-NEXT:    [[RB:%.*]] = insertelement <2 x float> [[RA]], float [[TMP4]], i32 1
+; CHECK-NEXT:    ret <2 x float> [[RB]]
+;
+  %c0 = extractelement <2 x i32> %c, i32 0
+  %c1 = extractelement <2 x i32> %c, i32 1
+  %a0 = extractelement <2 x float> %a, i32 0
+  %a1 = extractelement <2 x float> %a, i32 1
+  %b0 = extractelement <2 x float> %b, i32 0
+  %b1 = extractelement <2 x float> %b, i32 1
+  %cmp0 = icmp ne i32 %c0, 0
+  %cmp1 = icmp ne i32 %c1, 0
+  %s0 = select i1 %cmp0, float %a0, float %b0
+  %s1 = select i1 %cmp1, float %a1, float %b1
+  %ra = insertelement <2 x float> poison, float %s0, i32 0
+  %rb = insertelement <2 x float> %ra, float %s1, i32 1
+  ret <2 x float> %rb
+}
+
+; Make sure when we construct partial vectors, we don't keep
+; re-visiting the insertelement chains starting with undef
+; (low cost threshold needed to force this to happen)
+define <4 x float> @simple_select_partial_vector(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
+; CHECK-LABEL: @simple_select_partial_vector(
+; CHECK-NEXT:    [[C0:%.*]] = extractelement <4 x i32> [[C:%.*]], i32 0
+; CHECK-NEXT:    [[C1:%.*]] = extractelement <4 x i32> [[C]], i32 1
+; CHECK-NEXT:    [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
+; CHECK-NEXT:    [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
+; CHECK-NEXT:    [[B0:%.*]] = extractelement <4 x float> [[B:%.*]], i32 0
+; CHECK-NEXT:    [[B1:%.*]] = extractelement <4 x float> [[B]], i32 1
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[C0]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[C1]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], zeroinitializer
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <2 x float> poison, float [[A0]], i32 0
+; CHECK-NEXT:    [[TMP5:%.*]] = insertelement <2 x float> [[TMP4]], float [[A1]], i32 1
+; CHECK-NEXT:    [[TMP6:%.*]] = insertelement <2 x float> poison, float [[B0]], i32 0
+; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <2 x float> [[TMP6]], float [[B1]], i32 1
+; CHECK-NEXT:    [[TMP8:%.*]] = select <2 x i1> [[TMP3]], <2 x float> [[TMP5]], <2 x float> [[TMP7]]
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <2 x float> [[TMP8]], i32 0
+; CHECK-NEXT:    [[RA:%.*]] = insertelement <4 x float> poison, float [[TMP9]], i32 0
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <2 x float> [[TMP8]], i32 1
+; CHECK-NEXT:    [[RB:%.*]] = insertelement <4 x float> [[RA]], float [[TMP10]], i32 1
+; CHECK-NEXT:    ret <4 x float> [[RB]]
+;
+  %c0 = extractelement <4 x i32> %c, i32 0
+  %c1 = extractelement <4 x i32> %c, i32 1
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %1 = insertelement <2 x i32> poison, i32 %c0, i32 0
+  %2 = insertelement <2 x i32> %1, i32 %c1, i32 1
+  %3 = icmp ne <2 x i32> %2, zeroinitializer
+  %4 = insertelement <2 x float> poison, float %a0, i32 0
+  %5 = insertelement <2 x float> %4, float %a1, i32 1
+  %6 = insertelement <2 x float> poison, float %b0, i32 0
+  %7 = insertelement <2 x float> %6, float %b1, i32 1
+  %8 = select <2 x i1> %3, <2 x float> %5, <2 x float> %7
+  %9 = extractelement <2 x float> %8, i32 0
+  %ra = insertelement <4 x float> poison, float %9, i32 0
+  %10 = extractelement <2 x float> %8, i32 1
+  %rb = insertelement <4 x float> %ra, float %10, i32 1
+  ret <4 x float> %rb
+}
+
+; Make sure that vectorization happens even if insertelements operations
+; must be rescheduled. The case here is from compiling Julia.
+define <4 x float> @reschedule_extract(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @reschedule_extract(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[V0:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <4 x float> [[V0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[V3]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %b0 = extractelement <4 x float> %b, i32 0
+  %c0 = fadd float %a0, %b0
+  %v0 = insertelement <4 x float> poison, float %c0, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %b1 = extractelement <4 x float> %b, i32 1
+  %c1 = fadd float %a1, %b1
+  %v1 = insertelement <4 x float> %v0, float %c1, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %b2 = extractelement <4 x float> %b, i32 2
+  %c2 = fadd float %a2, %b2
+  %v2 = insertelement <4 x float> %v1, float %c2, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b3 = extractelement <4 x float> %b, i32 3
+  %c3 = fadd float %a3, %b3
+  %v3 = insertelement <4 x float> %v2, float %c3, i32 3
+  ret <4 x float> %v3
+}
+
+; Check that cost model for vectorization takes credit for
+; instructions that are erased.
+define <4 x float> @take_credit(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @take_credit(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <4 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[V0:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <4 x float> [[V0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[V3]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %b0 = extractelement <4 x float> %b, i32 0
+  %c0 = fadd float %a0, %b0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %b1 = extractelement <4 x float> %b, i32 1
+  %c1 = fadd float %a1, %b1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %b2 = extractelement <4 x float> %b, i32 2
+  %c2 = fadd float %a2, %b2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %b3 = extractelement <4 x float> %b, i32 3
+  %c3 = fadd float %a3, %b3
+  %v0 = insertelement <4 x float> poison, float %c0, i32 0
+  %v1 = insertelement <4 x float> %v0, float %c1, i32 1
+  %v2 = insertelement <4 x float> %v1, float %c2, i32 2
+  %v3 = insertelement <4 x float> %v2, float %c3, i32 3
+  ret <4 x float> %v3
+}
+
+; Make sure we handle multiple trees that feed one build vector correctly.
+define <4 x double> @multi_tree(double %w, double %x, double %y, double %z) {
+; CHECK-LABEL: @multi_tree(
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x double> undef, double [[Z:%.*]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x double> [[TMP1]], double [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <4 x double> [[TMP2]], double [[X:%.*]], i32 2
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x double> [[TMP3]], double [[W:%.*]], i32 3
+; CHECK-NEXT:    [[TMP5:%.*]] = fadd <4 x double> [[TMP4]], <double 3.000000e+00, double 2.000000e+00, double 1.000000e+00, double 0.000000e+00>
+; CHECK-NEXT:    [[TMP6:%.*]] = fmul <4 x double> [[TMP5]], <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00>
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <4 x double> [[TMP6]], i32 3
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x double> poison, double [[TMP7]], i32 3
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <4 x double> [[TMP6]], i32 2
+; CHECK-NEXT:    [[I2:%.*]] = insertelement <4 x double> [[I1]], double [[TMP8]], i32 2
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <4 x double> [[TMP6]], i32 1
+; CHECK-NEXT:    [[I3:%.*]] = insertelement <4 x double> [[I2]], double [[TMP9]], i32 1
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <4 x double> [[TMP6]], i32 0
+; CHECK-NEXT:    [[I4:%.*]] = insertelement <4 x double> [[I3]], double [[TMP10]], i32 0
+; CHECK-NEXT:    ret <4 x double> [[I4]]
+;
+  %t0 = fadd double %w , 0.000000e+00
+  %t1 = fadd double %x , 1.000000e+00
+  %t2 = fadd double %y , 2.000000e+00
+  %t3 = fadd double %z , 3.000000e+00
+  %t4 = fmul double %t0, 1.000000e+00
+  %i1 = insertelement <4 x double> poison, double %t4, i32 3
+  %t5 = fmul double %t1, 1.000000e+00
+  %i2 = insertelement <4 x double> %i1, double %t5, i32 2
+  %t6 = fmul double %t2, 1.000000e+00
+  %i3 = insertelement <4 x double> %i2, double %t6, i32 1
+  %t7 = fmul double %t3, 1.000000e+00
+  %i4 = insertelement <4 x double> %i3, double %t7, i32 0
+  ret <4 x double> %i4
+}
+
+define <8 x float> @_vadd256(<8 x float> %a, <8 x float> %b) local_unnamed_addr #0 {
+; CHECK-LABEL: @_vadd256(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <8 x float> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <8 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINIT_I:%.*]] = insertelement <8 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <8 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINIT1_I:%.*]] = insertelement <8 x float> [[VECINIT_I]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINIT2_I:%.*]] = insertelement <8 x float> [[VECINIT1_I]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINIT3_I:%.*]] = insertelement <8 x float> [[VECINIT2_I]], float [[TMP5]], i32 3
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x float> [[TMP1]], i32 4
+; CHECK-NEXT:    [[VECINIT4_I:%.*]] = insertelement <8 x float> [[VECINIT3_I]], float [[TMP6]], i32 4
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x float> [[TMP1]], i32 5
+; CHECK-NEXT:    [[VECINIT5_I:%.*]] = insertelement <8 x float> [[VECINIT4_I]], float [[TMP7]], i32 5
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x float> [[TMP1]], i32 6
+; CHECK-NEXT:    [[VECINIT6_I:%.*]] = insertelement <8 x float> [[VECINIT5_I]], float [[TMP8]], i32 6
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x float> [[TMP1]], i32 7
+; CHECK-NEXT:    [[VECINIT7_I:%.*]] = insertelement <8 x float> [[VECINIT6_I]], float [[TMP9]], i32 7
+; CHECK-NEXT:    ret <8 x float> [[VECINIT7_I]]
+;
+  %vecext = extractelement <8 x float> %a, i32 0
+  %vecext1 = extractelement <8 x float> %b, i32 0
+  %add = fadd float %vecext, %vecext1
+  %vecext2 = extractelement <8 x float> %a, i32 1
+  %vecext3 = extractelement <8 x float> %b, i32 1
+  %add4 = fadd float %vecext2, %vecext3
+  %vecext5 = extractelement <8 x float> %a, i32 2
+  %vecext6 = extractelement <8 x float> %b, i32 2
+  %add7 = fadd float %vecext5, %vecext6
+  %vecext8 = extractelement <8 x float> %a, i32 3
+  %vecext9 = extractelement <8 x float> %b, i32 3
+  %add10 = fadd float %vecext8, %vecext9
+  %vecext11 = extractelement <8 x float> %a, i32 4
+  %vecext12 = extractelement <8 x float> %b, i32 4
+  %add13 = fadd float %vecext11, %vecext12
+  %vecext14 = extractelement <8 x float> %a, i32 5
+  %vecext15 = extractelement <8 x float> %b, i32 5
+  %add16 = fadd float %vecext14, %vecext15
+  %vecext17 = extractelement <8 x float> %a, i32 6
+  %vecext18 = extractelement <8 x float> %b, i32 6
+  %add19 = fadd float %vecext17, %vecext18
+  %vecext20 = extractelement <8 x float> %a, i32 7
+  %vecext21 = extractelement <8 x float> %b, i32 7
+  %add22 = fadd float %vecext20, %vecext21
+  %vecinit.i = insertelement <8 x float> poison, float %add, i32 0
+  %vecinit1.i = insertelement <8 x float> %vecinit.i, float %add4, i32 1
+  %vecinit2.i = insertelement <8 x float> %vecinit1.i, float %add7, i32 2
+  %vecinit3.i = insertelement <8 x float> %vecinit2.i, float %add10, i32 3
+  %vecinit4.i = insertelement <8 x float> %vecinit3.i, float %add13, i32 4
+  %vecinit5.i = insertelement <8 x float> %vecinit4.i, float %add16, i32 5
+  %vecinit6.i = insertelement <8 x float> %vecinit5.i, float %add19, i32 6
+  %vecinit7.i = insertelement <8 x float> %vecinit6.i, float %add22, i32 7
+  ret <8 x float> %vecinit7.i
+}
+
+attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
new file mode 100644
index 0000000000000..c844156421308
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/load-merge-inseltpoison.ll
@@ -0,0 +1,208 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-apple-macosx -mcpu=haswell | FileCheck %s
+
+;unsigned load_le32(unsigned char *data) {
+;    unsigned le32 = (data[0]<<0) | (data[1]<<8) | (data[2]<<16) | (data[3]<<24);
+;    return le32;
+;}
+
+define i32 @_Z9load_le32Ph(i8* nocapture readonly %data) {
+; CHECK-LABEL: @_Z9load_le32Ph(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load i8, i8* [[DATA:%.*]], align 1
+; CHECK-NEXT:    [[CONV:%.*]] = zext i8 [[TMP0]] to i32
+; CHECK-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds i8, i8* [[DATA]], i64 1
+; CHECK-NEXT:    [[TMP1:%.*]] = load i8, i8* [[ARRAYIDX1]], align 1
+; CHECK-NEXT:    [[CONV2:%.*]] = zext i8 [[TMP1]] to i32
+; CHECK-NEXT:    [[SHL3:%.*]] = shl nuw nsw i32 [[CONV2]], 8
+; CHECK-NEXT:    [[OR:%.*]] = or i32 [[SHL3]], [[CONV]]
+; CHECK-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds i8, i8* [[DATA]], i64 2
+; CHECK-NEXT:    [[TMP2:%.*]] = load i8, i8* [[ARRAYIDX4]], align 1
+; CHECK-NEXT:    [[CONV5:%.*]] = zext i8 [[TMP2]] to i32
+; CHECK-NEXT:    [[SHL6:%.*]] = shl nuw nsw i32 [[CONV5]], 16
+; CHECK-NEXT:    [[OR7:%.*]] = or i32 [[OR]], [[SHL6]]
+; CHECK-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i8, i8* [[DATA]], i64 3
+; CHECK-NEXT:    [[TMP3:%.*]] = load i8, i8* [[ARRAYIDX8]], align 1
+; CHECK-NEXT:    [[CONV9:%.*]] = zext i8 [[TMP3]] to i32
+; CHECK-NEXT:    [[SHL10:%.*]] = shl nuw i32 [[CONV9]], 24
+; CHECK-NEXT:    [[OR11:%.*]] = or i32 [[OR7]], [[SHL10]]
+; CHECK-NEXT:    ret i32 [[OR11]]
+;
+entry:
+  %0 = load i8, i8* %data, align 1
+  %conv = zext i8 %0 to i32
+  %arrayidx1 = getelementptr inbounds i8, i8* %data, i64 1
+  %1 = load i8, i8* %arrayidx1, align 1
+  %conv2 = zext i8 %1 to i32
+  %shl3 = shl nuw nsw i32 %conv2, 8
+  %or = or i32 %shl3, %conv
+  %arrayidx4 = getelementptr inbounds i8, i8* %data, i64 2
+  %2 = load i8, i8* %arrayidx4, align 1
+  %conv5 = zext i8 %2 to i32
+  %shl6 = shl nuw nsw i32 %conv5, 16
+  %or7 = or i32 %or, %shl6
+  %arrayidx8 = getelementptr inbounds i8, i8* %data, i64 3
+  %3 = load i8, i8* %arrayidx8, align 1
+  %conv9 = zext i8 %3 to i32
+  %shl10 = shl nuw i32 %conv9, 24
+  %or11 = or i32 %or7, %shl10
+  ret i32 %or11
+}
+
+define <4 x float> @PR16739_byref(<4 x float>* nocapture readonly dereferenceable(16) %x) {
+; CHECK-LABEL: @PR16739_byref(
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[X:%.*]], i64 0, i64 0
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[X]], i64 0, i64 1
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[X]], i64 0, i64 2
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[GEP0]] to <2 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <2 x float>, <2 x float>* [[TMP1]], align 4
+; CHECK-NEXT:    [[X2:%.*]] = load float, float* [[GEP2]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i32 0
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x float> [[I0]], float [[TMP4]], i32 1
+; CHECK-NEXT:    [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[X2]], i32 2
+; CHECK-NEXT:    [[I3:%.*]] = insertelement <4 x float> [[I2]], float [[X2]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[I3]]
+;
+  %gep0 = getelementptr inbounds <4 x float>, <4 x float>* %x, i64 0, i64 0
+  %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %x, i64 0, i64 1
+  %gep2 = getelementptr inbounds <4 x float>, <4 x float>* %x, i64 0, i64 2
+  %x0 = load float, float* %gep0
+  %x1 = load float, float* %gep1
+  %x2 = load float, float* %gep2
+  %i0 = insertelement <4 x float> poison, float %x0, i32 0
+  %i1 = insertelement <4 x float> %i0, float %x1, i32 1
+  %i2 = insertelement <4 x float> %i1, float %x2, i32 2
+  %i3 = insertelement <4 x float> %i2, float %x2, i32 3
+  ret <4 x float> %i3
+}
+
+define <4 x float> @PR16739_byref_alt(<4 x float>* nocapture readonly dereferenceable(16) %x) {
+; CHECK-LABEL: @PR16739_byref_alt(
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[X:%.*]], i64 0, i64 0
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[X]], i64 0, i64 1
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[GEP0]] to <2 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <2 x float>, <2 x float>* [[TMP1]], align 4
+; CHECK-NEXT:    [[SHUFFLE:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[SHUFFLE]], i32 0
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i32 0
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x float> [[I0]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[SHUFFLE]], i32 2
+; CHECK-NEXT:    [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[I3:%.*]] = insertelement <4 x float> [[I2]], float [[TMP4]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[I3]]
+;
+  %gep0 = getelementptr inbounds <4 x float>, <4 x float>* %x, i64 0, i64 0
+  %gep1 = getelementptr inbounds <4 x float>, <4 x float>* %x, i64 0, i64 1
+  %x0 = load float, float* %gep0
+  %x1 = load float, float* %gep1
+  %i0 = insertelement <4 x float> poison, float %x0, i32 0
+  %i1 = insertelement <4 x float> %i0, float %x0, i32 1
+  %i2 = insertelement <4 x float> %i1, float %x1, i32 2
+  %i3 = insertelement <4 x float> %i2, float %x1, i32 3
+  ret <4 x float> %i3
+}
+
+define <4 x float> @PR16739_byval(<4 x float>* nocapture readonly dereferenceable(16) %x) {
+; CHECK-LABEL: @PR16739_byval(
+; CHECK-NEXT:    [[T0:%.*]] = bitcast <4 x float>* [[X:%.*]] to i64*
+; CHECK-NEXT:    [[T1:%.*]] = load i64, i64* [[T0]], align 16
+; CHECK-NEXT:    [[T2:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[X]], i64 0, i64 2
+; CHECK-NEXT:    [[T3:%.*]] = bitcast float* [[T2]] to i64*
+; CHECK-NEXT:    [[T4:%.*]] = load i64, i64* [[T3]], align 8
+; CHECK-NEXT:    [[T5:%.*]] = trunc i64 [[T1]] to i32
+; CHECK-NEXT:    [[T6:%.*]] = bitcast i32 [[T5]] to float
+; CHECK-NEXT:    [[T7:%.*]] = insertelement <4 x float> poison, float [[T6]], i32 0
+; CHECK-NEXT:    [[T8:%.*]] = lshr i64 [[T1]], 32
+; CHECK-NEXT:    [[T9:%.*]] = trunc i64 [[T8]] to i32
+; CHECK-NEXT:    [[T10:%.*]] = bitcast i32 [[T9]] to float
+; CHECK-NEXT:    [[T11:%.*]] = insertelement <4 x float> [[T7]], float [[T10]], i32 1
+; CHECK-NEXT:    [[T12:%.*]] = trunc i64 [[T4]] to i32
+; CHECK-NEXT:    [[T13:%.*]] = bitcast i32 [[T12]] to float
+; CHECK-NEXT:    [[T14:%.*]] = insertelement <4 x float> [[T11]], float [[T13]], i32 2
+; CHECK-NEXT:    [[T15:%.*]] = insertelement <4 x float> [[T14]], float [[T13]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[T15]]
+;
+  %t0 = bitcast <4 x float>* %x to i64*
+  %t1 = load i64, i64* %t0, align 16
+  %t2 = getelementptr inbounds <4 x float>, <4 x float>* %x, i64 0, i64 2
+  %t3 = bitcast float* %t2 to i64*
+  %t4 = load i64, i64* %t3, align 8
+  %t5 = trunc i64 %t1 to i32
+  %t6 = bitcast i32 %t5 to float
+  %t7 = insertelement <4 x float> poison, float %t6, i32 0
+  %t8 = lshr i64 %t1, 32
+  %t9 = trunc i64 %t8 to i32
+  %t10 = bitcast i32 %t9 to float
+  %t11 = insertelement <4 x float> %t7, float %t10, i32 1
+  %t12 = trunc i64 %t4 to i32
+  %t13 = bitcast i32 %t12 to float
+  %t14 = insertelement <4 x float> %t11, float %t13, i32 2
+  %t15 = insertelement <4 x float> %t14, float %t13, i32 3
+  ret <4 x float> %t15
+}
+
+define void @PR43578_prefer128(i32* %r, i64* %p, i64* %q) #0 {
+; CHECK-LABEL: @PR43578_prefer128(
+; CHECK-NEXT:    [[P0:%.*]] = getelementptr inbounds i64, i64* [[P:%.*]], i64 0
+; CHECK-NEXT:    [[P1:%.*]] = getelementptr inbounds i64, i64* [[P]], i64 1
+; CHECK-NEXT:    [[P2:%.*]] = getelementptr inbounds i64, i64* [[P]], i64 2
+; CHECK-NEXT:    [[P3:%.*]] = getelementptr inbounds i64, i64* [[P]], i64 3
+; CHECK-NEXT:    [[Q0:%.*]] = getelementptr inbounds i64, i64* [[Q:%.*]], i64 0
+; CHECK-NEXT:    [[Q1:%.*]] = getelementptr inbounds i64, i64* [[Q]], i64 1
+; CHECK-NEXT:    [[Q2:%.*]] = getelementptr inbounds i64, i64* [[Q]], i64 2
+; CHECK-NEXT:    [[Q3:%.*]] = getelementptr inbounds i64, i64* [[Q]], i64 3
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i64* [[P0]] to <2 x i64>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* [[TMP1]], align 2
+; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i64* [[P2]] to <2 x i64>*
+; CHECK-NEXT:    [[TMP4:%.*]] = load <2 x i64>, <2 x i64>* [[TMP3]], align 2
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i64* [[Q0]] to <2 x i64>*
+; CHECK-NEXT:    [[TMP6:%.*]] = load <2 x i64>, <2 x i64>* [[TMP5]], align 2
+; CHECK-NEXT:    [[TMP7:%.*]] = bitcast i64* [[Q2]] to <2 x i64>*
+; CHECK-NEXT:    [[TMP8:%.*]] = load <2 x i64>, <2 x i64>* [[TMP7]], align 2
+; CHECK-NEXT:    [[TMP9:%.*]] = sub nsw <2 x i64> [[TMP2]], [[TMP6]]
+; CHECK-NEXT:    [[TMP10:%.*]] = sub nsw <2 x i64> [[TMP4]], [[TMP8]]
+; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <2 x i64> [[TMP9]], i32 0
+; CHECK-NEXT:    [[G0:%.*]] = getelementptr inbounds i32, i32* [[R:%.*]], i64 [[TMP11]]
+; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <2 x i64> [[TMP9]], i32 1
+; CHECK-NEXT:    [[G1:%.*]] = getelementptr inbounds i32, i32* [[R]], i64 [[TMP12]]
+; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <2 x i64> [[TMP10]], i32 0
+; CHECK-NEXT:    [[G2:%.*]] = getelementptr inbounds i32, i32* [[R]], i64 [[TMP13]]
+; CHECK-NEXT:    [[TMP14:%.*]] = extractelement <2 x i64> [[TMP10]], i32 1
+; CHECK-NEXT:    [[G3:%.*]] = getelementptr inbounds i32, i32* [[R]], i64 [[TMP14]]
+; CHECK-NEXT:    ret void
+;
+  %p0 = getelementptr inbounds i64, i64* %p, i64 0
+  %p1 = getelementptr inbounds i64, i64* %p, i64 1
+  %p2 = getelementptr inbounds i64, i64* %p, i64 2
+  %p3 = getelementptr inbounds i64, i64* %p, i64 3
+
+  %q0 = getelementptr inbounds i64, i64* %q, i64 0
+  %q1 = getelementptr inbounds i64, i64* %q, i64 1
+  %q2 = getelementptr inbounds i64, i64* %q, i64 2
+  %q3 = getelementptr inbounds i64, i64* %q, i64 3
+
+  %x0 = load i64, i64* %p0, align 2
+  %x1 = load i64, i64* %p1, align 2
+  %x2 = load i64, i64* %p2, align 2
+  %x3 = load i64, i64* %p3, align 2
+
+  %y0 = load i64, i64* %q0, align 2
+  %y1 = load i64, i64* %q1, align 2
+  %y2 = load i64, i64* %q2, align 2
+  %y3 = load i64, i64* %q3, align 2
+
+  %sub0 = sub nsw i64 %x0, %y0
+  %sub1 = sub nsw i64 %x1, %y1
+  %sub2 = sub nsw i64 %x2, %y2
+  %sub3 = sub nsw i64 %x3, %y3
+
+  %g0 = getelementptr inbounds i32, i32* %r, i64 %sub0
+  %g1 = getelementptr inbounds i32, i32* %r, i64 %sub1
+  %g2 = getelementptr inbounds i32, i32* %r, i64 %sub2
+  %g3 = getelementptr inbounds i32, i32* %r, i64 %sub3
+  ret void
+}
+
+attributes #0 = { "prefer-vector-width"="128" }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr31599-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr31599-inseltpoison.ll
new file mode 100644
index 0000000000000..448480d23b413
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr31599-inseltpoison.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define <2 x float> @foo() {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[SOURCE:%.*]] = insertelement <2 x float> poison, float undef, i32 0
+; CHECK-NEXT:    [[TMP0:%.*]] = fsub <2 x float> [[SOURCE]], [[SOURCE]]
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <2 x float> [[TMP0]], i32 0
+; CHECK-NEXT:    [[RES1:%.*]] = insertelement <2 x float> poison, float [[TMP1]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <2 x float> [[TMP0]], i32 1
+; CHECK-NEXT:    [[RES2:%.*]] = insertelement <2 x float> [[RES1]], float [[TMP2]], i32 1
+; CHECK-NEXT:    ret <2 x float> [[RES2]]
+;
+entry:
+  %source = insertelement <2 x float> poison, float undef, i32 0
+  %e0 = extractelement <2 x float> %source, i32 0
+  %e0.dup = extractelement <2 x float> %source, i32 0
+  %sub1 = fsub float %e0, %e0.dup
+  %e1 = extractelement <2 x float> %source, i32 1
+  %e1.dup = extractelement <2 x float> %source, i32 1
+  %sub2 = fsub float %e1, %e1.dup
+  %res1 = insertelement <2 x float> poison, float %sub1, i32 0
+  %res2 = insertelement <2 x float> %res1, float %sub2, i32 1
+  ret <2 x float> %res2
+}
+
+!llvm.ident = !{!0, !0}
+
+!0 = !{!"clang version 4.0.0 "}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll
new file mode 100644
index 0000000000000..a136a6ead561e
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr42022-inseltpoison.ll
@@ -0,0 +1,278 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; See https://reviews.llvm.org/D70068 and https://reviews.llvm.org/D70587 for context
+
+; Checks that vector insertvalues into the struct become SLP seeds.
+define { <2 x float>, <2 x float> } @StructOfVectors(float *%Ptr) {
+; CHECK-LABEL: @StructOfVectors(
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr inbounds float, float* [[PTR:%.*]], i64 0
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 1
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 2
+; CHECK-NEXT:    [[GEP3:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 3
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[GEP0]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], <float 1.100000e+01, float 1.200000e+01, float 1.300000e+01, float 1.400000e+01>
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT:    [[VECIN0:%.*]] = insertelement <2 x float> poison, float [[TMP4]], i64 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT:    [[VECIN1:%.*]] = insertelement <2 x float> [[VECIN0]], float [[TMP5]], i64 1
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
+; CHECK-NEXT:    [[VECIN2:%.*]] = insertelement <2 x float> poison, float [[TMP6]], i64 0
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
+; CHECK-NEXT:    [[VECIN3:%.*]] = insertelement <2 x float> [[VECIN2]], float [[TMP7]], i64 1
+; CHECK-NEXT:    [[RET0:%.*]] = insertvalue { <2 x float>, <2 x float> } undef, <2 x float> [[VECIN1]], 0
+; CHECK-NEXT:    [[RET1:%.*]] = insertvalue { <2 x float>, <2 x float> } [[RET0]], <2 x float> [[VECIN3]], 1
+; CHECK-NEXT:    ret { <2 x float>, <2 x float> } [[RET1]]
+;
+  %GEP0 = getelementptr inbounds float, float* %Ptr, i64 0
+  %L0 = load float, float * %GEP0
+  %GEP1 = getelementptr inbounds float, float* %Ptr, i64 1
+  %L1 = load float, float * %GEP1
+  %GEP2 = getelementptr inbounds float, float* %Ptr, i64 2
+  %L2 = load float, float * %GEP2
+  %GEP3 = getelementptr inbounds float, float* %Ptr, i64 3
+  %L3 = load float, float * %GEP3
+
+  %Fadd0 = fadd fast float %L0, 1.1e+01
+  %Fadd1 = fadd fast float %L1, 1.2e+01
+  %Fadd2 = fadd fast float %L2, 1.3e+01
+  %Fadd3 = fadd fast float %L3, 1.4e+01
+
+  %VecIn0 = insertelement <2 x float> poison, float %Fadd0, i64 0
+  %VecIn1 = insertelement <2 x float> %VecIn0, float %Fadd1, i64 1
+
+  %VecIn2 = insertelement <2 x float> poison, float %Fadd2, i64 0
+  %VecIn3 = insertelement <2 x float> %VecIn2, float %Fadd3, i64 1
+
+  %Ret0 = insertvalue {<2 x float>, <2 x float>} undef, <2 x float> %VecIn1, 0
+  %Ret1 = insertvalue {<2 x float>, <2 x float>} %Ret0, <2 x float> %VecIn3, 1
+  ret {<2 x float>, <2 x float>} %Ret1
+}
+
+%StructTy = type { float, float}
+
+define [2 x %StructTy] @ArrayOfStruct(float *%Ptr) {
+; CHECK-LABEL: @ArrayOfStruct(
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr inbounds float, float* [[PTR:%.*]], i64 0
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 1
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 2
+; CHECK-NEXT:    [[GEP3:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 3
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[GEP0]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], <float 1.100000e+01, float 1.200000e+01, float 1.300000e+01, float 1.400000e+01>
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT:    [[STRUCTIN0:%.*]] = insertvalue [[STRUCTTY:%.*]] undef, float [[TMP4]], 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT:    [[STRUCTIN1:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN0]], float [[TMP5]], 1
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
+; CHECK-NEXT:    [[STRUCTIN2:%.*]] = insertvalue [[STRUCTTY]] undef, float [[TMP6]], 0
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
+; CHECK-NEXT:    [[STRUCTIN3:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN2]], float [[TMP7]], 1
+; CHECK-NEXT:    [[RET0:%.*]] = insertvalue [2 x %StructTy] undef, [[STRUCTTY]] [[STRUCTIN1]], 0
+; CHECK-NEXT:    [[RET1:%.*]] = insertvalue [2 x %StructTy] [[RET0]], [[STRUCTTY]] [[STRUCTIN3]], 1
+; CHECK-NEXT:    ret [2 x %StructTy] [[RET1]]
+;
+  %GEP0 = getelementptr inbounds float, float* %Ptr, i64 0
+  %L0 = load float, float * %GEP0
+  %GEP1 = getelementptr inbounds float, float* %Ptr, i64 1
+  %L1 = load float, float * %GEP1
+  %GEP2 = getelementptr inbounds float, float* %Ptr, i64 2
+  %L2 = load float, float * %GEP2
+  %GEP3 = getelementptr inbounds float, float* %Ptr, i64 3
+  %L3 = load float, float * %GEP3
+
+  %Fadd0 = fadd fast float %L0, 1.1e+01
+  %Fadd1 = fadd fast float %L1, 1.2e+01
+  %Fadd2 = fadd fast float %L2, 1.3e+01
+  %Fadd3 = fadd fast float %L3, 1.4e+01
+
+  %StructIn0 = insertvalue %StructTy undef, float %Fadd0, 0
+  %StructIn1 = insertvalue %StructTy %StructIn0, float %Fadd1, 1
+
+  %StructIn2 = insertvalue %StructTy undef, float %Fadd2, 0
+  %StructIn3 = insertvalue %StructTy %StructIn2, float %Fadd3, 1
+
+  %Ret0 = insertvalue [2 x %StructTy] undef, %StructTy %StructIn1, 0
+  %Ret1 = insertvalue [2 x %StructTy] %Ret0, %StructTy %StructIn3, 1
+  ret [2 x %StructTy] %Ret1
+}
+
+define {%StructTy, %StructTy} @StructOfStruct(float *%Ptr) {
+; CHECK-LABEL: @StructOfStruct(
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr inbounds float, float* [[PTR:%.*]], i64 0
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 1
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 2
+; CHECK-NEXT:    [[GEP3:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 3
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[GEP0]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd fast <4 x float> [[TMP2]], <float 1.100000e+01, float 1.200000e+01, float 1.300000e+01, float 1.400000e+01>
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP3]], i32 0
+; CHECK-NEXT:    [[STRUCTIN0:%.*]] = insertvalue [[STRUCTTY:%.*]] undef, float [[TMP4]], 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP3]], i32 1
+; CHECK-NEXT:    [[STRUCTIN1:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN0]], float [[TMP5]], 1
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <4 x float> [[TMP3]], i32 2
+; CHECK-NEXT:    [[STRUCTIN2:%.*]] = insertvalue [[STRUCTTY]] undef, float [[TMP6]], 0
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <4 x float> [[TMP3]], i32 3
+; CHECK-NEXT:    [[STRUCTIN3:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN2]], float [[TMP7]], 1
+; CHECK-NEXT:    [[RET0:%.*]] = insertvalue { [[STRUCTTY]], [[STRUCTTY]] } undef, [[STRUCTTY]] [[STRUCTIN1]], 0
+; CHECK-NEXT:    [[RET1:%.*]] = insertvalue { [[STRUCTTY]], [[STRUCTTY]] } [[RET0]], [[STRUCTTY]] [[STRUCTIN3]], 1
+; CHECK-NEXT:    ret { [[STRUCTTY]], [[STRUCTTY]] } [[RET1]]
+;
+  %GEP0 = getelementptr inbounds float, float* %Ptr, i64 0
+  %L0 = load float, float * %GEP0
+  %GEP1 = getelementptr inbounds float, float* %Ptr, i64 1
+  %L1 = load float, float * %GEP1
+  %GEP2 = getelementptr inbounds float, float* %Ptr, i64 2
+  %L2 = load float, float * %GEP2
+  %GEP3 = getelementptr inbounds float, float* %Ptr, i64 3
+  %L3 = load float, float * %GEP3
+
+  %Fadd0 = fadd fast float %L0, 1.1e+01
+  %Fadd1 = fadd fast float %L1, 1.2e+01
+  %Fadd2 = fadd fast float %L2, 1.3e+01
+  %Fadd3 = fadd fast float %L3, 1.4e+01
+
+  %StructIn0 = insertvalue %StructTy undef, float %Fadd0, 0
+  %StructIn1 = insertvalue %StructTy %StructIn0, float %Fadd1, 1
+
+  %StructIn2 = insertvalue %StructTy undef, float %Fadd2, 0
+  %StructIn3 = insertvalue %StructTy %StructIn2, float %Fadd3, 1
+
+  %Ret0 = insertvalue {%StructTy, %StructTy} undef, %StructTy %StructIn1, 0
+  %Ret1 = insertvalue {%StructTy, %StructTy} %Ret0, %StructTy %StructIn3, 1
+  ret {%StructTy, %StructTy} %Ret1
+}
+
+define {%StructTy, float, float} @NonHomogeneousStruct(float *%Ptr) {
+; CHECK-LABEL: @NonHomogeneousStruct(
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr inbounds float, float* [[PTR:%.*]], i64 0
+; CHECK-NEXT:    [[L0:%.*]] = load float, float* [[GEP0]], align 4
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 1
+; CHECK-NEXT:    [[L1:%.*]] = load float, float* [[GEP1]], align 4
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 2
+; CHECK-NEXT:    [[L2:%.*]] = load float, float* [[GEP2]], align 4
+; CHECK-NEXT:    [[GEP3:%.*]] = getelementptr inbounds float, float* [[PTR]], i64 3
+; CHECK-NEXT:    [[L3:%.*]] = load float, float* [[GEP3]], align 4
+; CHECK-NEXT:    [[FADD0:%.*]] = fadd fast float [[L0]], 1.100000e+01
+; CHECK-NEXT:    [[FADD1:%.*]] = fadd fast float [[L1]], 1.200000e+01
+; CHECK-NEXT:    [[FADD2:%.*]] = fadd fast float [[L2]], 1.300000e+01
+; CHECK-NEXT:    [[FADD3:%.*]] = fadd fast float [[L3]], 1.400000e+01
+; CHECK-NEXT:    [[STRUCTIN0:%.*]] = insertvalue [[STRUCTTY:%.*]] undef, float [[FADD0]], 0
+; CHECK-NEXT:    [[STRUCTIN1:%.*]] = insertvalue [[STRUCTTY]] [[STRUCTIN0]], float [[FADD1]], 1
+; CHECK-NEXT:    [[RET0:%.*]] = insertvalue { [[STRUCTTY]], float, float } undef, [[STRUCTTY]] [[STRUCTIN1]], 0
+; CHECK-NEXT:    [[RET1:%.*]] = insertvalue { [[STRUCTTY]], float, float } [[RET0]], float [[FADD2]], 1
+; CHECK-NEXT:    [[RET2:%.*]] = insertvalue { [[STRUCTTY]], float, float } [[RET1]], float [[FADD3]], 2
+; CHECK-NEXT:    ret { [[STRUCTTY]], float, float } [[RET2]]
+;
+  %GEP0 = getelementptr inbounds float, float* %Ptr, i64 0
+  %L0 = load float, float * %GEP0
+  %GEP1 = getelementptr inbounds float, float* %Ptr, i64 1
+  %L1 = load float, float * %GEP1
+  %GEP2 = getelementptr inbounds float, float* %Ptr, i64 2
+  %L2 = load float, float * %GEP2
+  %GEP3 = getelementptr inbounds float, float* %Ptr, i64 3
+  %L3 = load float, float * %GEP3
+
+  %Fadd0 = fadd fast float %L0, 1.1e+01
+  %Fadd1 = fadd fast float %L1, 1.2e+01
+  %Fadd2 = fadd fast float %L2, 1.3e+01
+  %Fadd3 = fadd fast float %L3, 1.4e+01
+
+  %StructIn0 = insertvalue %StructTy undef, float %Fadd0, 0
+  %StructIn1 = insertvalue %StructTy %StructIn0, float %Fadd1, 1
+
+  %Ret0 = insertvalue {%StructTy, float, float} undef, %StructTy %StructIn1, 0
+  %Ret1 = insertvalue {%StructTy, float, float} %Ret0, float %Fadd2, 1
+  %Ret2 = insertvalue {%StructTy, float, float} %Ret1, float %Fadd3, 2
+  ret {%StructTy, float, float} %Ret2
+}
+
+%Struct1Ty = type { i16, i16 }
+%Struct2Ty = type { %Struct1Ty, %Struct1Ty}
+
+define {%Struct2Ty, %Struct2Ty} @StructOfStructOfStruct(i16 *%Ptr) {
+; CHECK-LABEL: @StructOfStructOfStruct(
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr inbounds i16, i16* [[PTR:%.*]], i64 0
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 1
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 2
+; CHECK-NEXT:    [[GEP3:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 3
+; CHECK-NEXT:    [[GEP4:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 4
+; CHECK-NEXT:    [[GEP5:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 5
+; CHECK-NEXT:    [[GEP6:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 6
+; CHECK-NEXT:    [[GEP7:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 7
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16* [[GEP0]] to <8 x i16>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
+; CHECK-NEXT:    [[TMP3:%.*]] = add <8 x i16> [[TMP2]], <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; CHECK-NEXT:    [[STRUCTIN0:%.*]] = insertvalue [[STRUCT1TY:%.*]] undef, i16 [[TMP4]], 0
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; CHECK-NEXT:    [[STRUCTIN1:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN0]], i16 [[TMP5]], 1
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; CHECK-NEXT:    [[STRUCTIN2:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP6]], 0
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; CHECK-NEXT:    [[STRUCTIN3:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN2]], i16 [[TMP7]], 1
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; CHECK-NEXT:    [[STRUCTIN4:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP8]], 0
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; CHECK-NEXT:    [[STRUCTIN5:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN4]], i16 [[TMP9]], 1
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; CHECK-NEXT:    [[STRUCTIN6:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP10]], 0
+; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; CHECK-NEXT:    [[STRUCTIN7:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN6]], i16 [[TMP11]], 1
+; CHECK-NEXT:    [[STRUCT2IN0:%.*]] = insertvalue [[STRUCT2TY:%.*]] undef, [[STRUCT1TY]] [[STRUCTIN1]], 0
+; CHECK-NEXT:    [[STRUCT2IN1:%.*]] = insertvalue [[STRUCT2TY]] [[STRUCT2IN0]], [[STRUCT1TY]] [[STRUCTIN3]], 1
+; CHECK-NEXT:    [[STRUCT2IN2:%.*]] = insertvalue [[STRUCT2TY]] undef, [[STRUCT1TY]] [[STRUCTIN5]], 0
+; CHECK-NEXT:    [[STRUCT2IN3:%.*]] = insertvalue [[STRUCT2TY]] [[STRUCT2IN2]], [[STRUCT1TY]] [[STRUCTIN7]], 1
+; CHECK-NEXT:    [[RET0:%.*]] = insertvalue { [[STRUCT2TY]], [[STRUCT2TY]] } undef, [[STRUCT2TY]] [[STRUCT2IN1]], 0
+; CHECK-NEXT:    [[RET1:%.*]] = insertvalue { [[STRUCT2TY]], [[STRUCT2TY]] } [[RET0]], [[STRUCT2TY]] [[STRUCT2IN3]], 1
+; CHECK-NEXT:    ret { [[STRUCT2TY]], [[STRUCT2TY]] } [[RET1]]
+;
+  %GEP0 = getelementptr inbounds i16, i16* %Ptr, i64 0
+  %L0 = load i16, i16 * %GEP0
+  %GEP1 = getelementptr inbounds i16, i16* %Ptr, i64 1
+  %L1 = load i16, i16 * %GEP1
+  %GEP2 = getelementptr inbounds i16, i16* %Ptr, i64 2
+  %L2 = load i16, i16 * %GEP2
+  %GEP3 = getelementptr inbounds i16, i16* %Ptr, i64 3
+  %L3 = load i16, i16 * %GEP3
+  %GEP4 = getelementptr inbounds i16, i16* %Ptr, i64 4
+  %L4 = load i16, i16 * %GEP4
+  %GEP5 = getelementptr inbounds i16, i16* %Ptr, i64 5
+  %L5 = load i16, i16 * %GEP5
+  %GEP6 = getelementptr inbounds i16, i16* %Ptr, i64 6
+  %L6 = load i16, i16 * %GEP6
+  %GEP7 = getelementptr inbounds i16, i16* %Ptr, i64 7
+  %L7 = load i16, i16 * %GEP7
+
+  %Fadd0 = add i16 %L0, 1
+  %Fadd1 = add i16 %L1, 2
+  %Fadd2 = add i16 %L2, 3
+  %Fadd3 = add i16 %L3, 4
+  %Fadd4 = add i16 %L4, 5
+  %Fadd5 = add i16 %L5, 6
+  %Fadd6 = add i16 %L6, 7
+  %Fadd7 = add i16 %L7, 8
+
+  %StructIn0 = insertvalue %Struct1Ty undef, i16 %Fadd0, 0
+  %StructIn1 = insertvalue %Struct1Ty %StructIn0, i16 %Fadd1, 1
+
+  %StructIn2 = insertvalue %Struct1Ty undef, i16 %Fadd2, 0
+  %StructIn3 = insertvalue %Struct1Ty %StructIn2, i16 %Fadd3, 1
+
+  %StructIn4 = insertvalue %Struct1Ty undef, i16 %Fadd4, 0
+  %StructIn5 = insertvalue %Struct1Ty %StructIn4, i16 %Fadd5, 1
+
+  %StructIn6 = insertvalue %Struct1Ty undef, i16 %Fadd6, 0
+  %StructIn7 = insertvalue %Struct1Ty %StructIn6, i16 %Fadd7, 1
+
+  %Struct2In0 = insertvalue %Struct2Ty undef, %Struct1Ty %StructIn1, 0
+  %Struct2In1 = insertvalue %Struct2Ty %Struct2In0, %Struct1Ty %StructIn3, 1
+
+  %Struct2In2 = insertvalue %Struct2Ty undef, %Struct1Ty %StructIn5, 0
+  %Struct2In3 = insertvalue %Struct2Ty %Struct2In2, %Struct1Ty %StructIn7, 1
+
+  %Ret0 = insertvalue {%Struct2Ty, %Struct2Ty} undef, %Struct2Ty %Struct2In1, 0
+  %Ret1 = insertvalue {%Struct2Ty, %Struct2Ty} %Ret0, %Struct2Ty %Struct2In3, 1
+  ret {%Struct2Ty, %Struct2Ty} %Ret1
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
new file mode 100644
index 0000000000000..35a296820b3bf
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr44067-inseltpoison.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+; See https://reviews.llvm.org/D83779
+
+define <2 x float> @foo({{float, float}}* %A) {
+; CHECK-LABEL: @foo(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast { { float, float } }* [[A:%.*]] to <2 x float>*
+; CHECK-NEXT:    [[TMP1:%.*]] = load <2 x float>, <2 x float>* [[TMP0]], align 8
+; CHECK-NEXT:    [[TMP2:%.*]] = fmul <2 x float> [[TMP1]], <float 2.000000e+00, float 2.000000e+00>
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <2 x float> [[TMP2]], i32 1
+; CHECK-NEXT:    [[INS1:%.*]] = insertelement <2 x float> poison, float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <2 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    [[INS0:%.*]] = insertelement <2 x float> [[INS1]], float [[TMP4]], i32 0
+; CHECK-NEXT:    ret <2 x float> [[INS0]]
+;
+entry:
+  %0 = bitcast {{float, float}}* %A to <2 x float>*
+  %1 = load <2 x float>, <2 x float>* %0
+  %L0 = extractelement <2 x float> %1, i32 0
+  %L1 = extractelement <2 x float> %1, i32 1
+  %Mul0 = fmul float %L0, 2.000000e+00
+  %Mul1 = fmul float %L1, 2.000000e+00
+  %Ins1 = insertelement <2 x float> poison, float %Mul1, i32 1
+  %Ins0 = insertelement <2 x float> %Ins1, float %Mul0, i32 0
+  ret <2 x float> %Ins0
+}
+
+
+%Struct1Ty = type { i16, i16 }
+%Struct2Ty = type { %Struct1Ty, %Struct1Ty}
+
+define {%Struct2Ty, %Struct2Ty} @StructOfStructOfStruct(i16 *%Ptr) {
+; CHECK-LABEL: @StructOfStructOfStruct(
+; CHECK-NEXT:    [[GEP0:%.*]] = getelementptr inbounds i16, i16* [[PTR:%.*]], i64 0
+; CHECK-NEXT:    [[GEP1:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 1
+; CHECK-NEXT:    [[GEP2:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 2
+; CHECK-NEXT:    [[GEP3:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 3
+; CHECK-NEXT:    [[GEP4:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 4
+; CHECK-NEXT:    [[GEP5:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 5
+; CHECK-NEXT:    [[GEP6:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 6
+; CHECK-NEXT:    [[GEP7:%.*]] = getelementptr inbounds i16, i16* [[PTR]], i64 7
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16* [[GEP0]] to <8 x i16>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
+; CHECK-NEXT:    [[TMP3:%.*]] = add <8 x i16> [[TMP2]], <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; CHECK-NEXT:    [[STRUCTIN0:%.*]] = insertvalue [[STRUCT1TY:%.*]] undef, i16 [[TMP4]], 1
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; CHECK-NEXT:    [[STRUCTIN1:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN0]], i16 [[TMP5]], 0
+; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; CHECK-NEXT:    [[STRUCTIN2:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP6]], 0
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; CHECK-NEXT:    [[STRUCTIN3:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN2]], i16 [[TMP7]], 1
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; CHECK-NEXT:    [[STRUCTIN4:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP8]], 0
+; CHECK-NEXT:    [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; CHECK-NEXT:    [[STRUCTIN5:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN4]], i16 [[TMP9]], 1
+; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; CHECK-NEXT:    [[STRUCTIN6:%.*]] = insertvalue [[STRUCT1TY]] undef, i16 [[TMP10]], 1
+; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; CHECK-NEXT:    [[STRUCTIN7:%.*]] = insertvalue [[STRUCT1TY]] [[STRUCTIN6]], i16 [[TMP11]], 0
+; CHECK-NEXT:    [[STRUCT2IN0:%.*]] = insertvalue [[STRUCT2TY:%.*]] undef, [[STRUCT1TY]] [[STRUCTIN1]], 0
+; CHECK-NEXT:    [[STRUCT2IN1:%.*]] = insertvalue [[STRUCT2TY]] [[STRUCT2IN0]], [[STRUCT1TY]] [[STRUCTIN3]], 1
+; CHECK-NEXT:    [[STRUCT2IN2:%.*]] = insertvalue [[STRUCT2TY]] undef, [[STRUCT1TY]] [[STRUCTIN5]], 0
+; CHECK-NEXT:    [[STRUCT2IN3:%.*]] = insertvalue [[STRUCT2TY]] [[STRUCT2IN2]], [[STRUCT1TY]] [[STRUCTIN7]], 1
+; CHECK-NEXT:    [[RET0:%.*]] = insertvalue { [[STRUCT2TY]], [[STRUCT2TY]] } undef, [[STRUCT2TY]] [[STRUCT2IN3]], 1
+; CHECK-NEXT:    [[RET1:%.*]] = insertvalue { [[STRUCT2TY]], [[STRUCT2TY]] } [[RET0]], [[STRUCT2TY]] [[STRUCT2IN1]], 0
+; CHECK-NEXT:    ret { [[STRUCT2TY]], [[STRUCT2TY]] } [[RET1]]
+;
+  %GEP0 = getelementptr inbounds i16, i16* %Ptr, i64 0
+  %L0 = load i16, i16 * %GEP0
+  %GEP1 = getelementptr inbounds i16, i16* %Ptr, i64 1
+  %L1 = load i16, i16 * %GEP1
+  %GEP2 = getelementptr inbounds i16, i16* %Ptr, i64 2
+  %L2 = load i16, i16 * %GEP2
+  %GEP3 = getelementptr inbounds i16, i16* %Ptr, i64 3
+  %L3 = load i16, i16 * %GEP3
+  %GEP4 = getelementptr inbounds i16, i16* %Ptr, i64 4
+  %L4 = load i16, i16 * %GEP4
+  %GEP5 = getelementptr inbounds i16, i16* %Ptr, i64 5
+  %L5 = load i16, i16 * %GEP5
+  %GEP6 = getelementptr inbounds i16, i16* %Ptr, i64 6
+  %L6 = load i16, i16 * %GEP6
+  %GEP7 = getelementptr inbounds i16, i16* %Ptr, i64 7
+  %L7 = load i16, i16 * %GEP7
+
+  %Fadd0 = add i16 %L0, 1
+  %Fadd1 = add i16 %L1, 2
+  %Fadd2 = add i16 %L2, 3
+  %Fadd3 = add i16 %L3, 4
+  %Fadd4 = add i16 %L4, 5
+  %Fadd5 = add i16 %L5, 6
+  %Fadd6 = add i16 %L6, 7
+  %Fadd7 = add i16 %L7, 8
+
+  %StructIn0 = insertvalue %Struct1Ty undef, i16 %Fadd1, 1
+  %StructIn1 = insertvalue %Struct1Ty %StructIn0, i16 %Fadd0, 0
+
+  %StructIn2 = insertvalue %Struct1Ty undef, i16 %Fadd2, 0
+  %StructIn3 = insertvalue %Struct1Ty %StructIn2, i16 %Fadd3, 1
+
+  %StructIn4 = insertvalue %Struct1Ty undef, i16 %Fadd4, 0
+  %StructIn5 = insertvalue %Struct1Ty %StructIn4, i16 %Fadd5, 1
+
+  %StructIn6 = insertvalue %Struct1Ty undef, i16 %Fadd7, 1
+  %StructIn7 = insertvalue %Struct1Ty %StructIn6, i16 %Fadd6, 0
+
+  %Struct2In0 = insertvalue %Struct2Ty undef, %Struct1Ty %StructIn1, 0
+  %Struct2In1 = insertvalue %Struct2Ty %Struct2In0, %Struct1Ty %StructIn3, 1
+
+  %Struct2In2 = insertvalue %Struct2Ty undef, %Struct1Ty %StructIn5, 0
+  %Struct2In3 = insertvalue %Struct2Ty %Struct2In2, %Struct1Ty %StructIn7, 1
+
+  %Ret0 = insertvalue {%Struct2Ty, %Struct2Ty} undef, %Struct2Ty %Struct2In3, 1
+  %Ret1 = insertvalue {%Struct2Ty, %Struct2Ty} %Ret0, %Struct2Ty %Struct2In1, 0
+  ret {%Struct2Ty, %Struct2Ty} %Ret1
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
new file mode 100644
index 0000000000000..090a9ea0dd1d6
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
@@ -0,0 +1,664 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN:  opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64-unknown-linux -mattr=+sse2     | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN:  opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx      | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN:  opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx2     | FileCheck %s --check-prefixes=CHECK,AVX2
+; RUN:  opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx512f  | FileCheck %s --check-prefixes=CHECK,AVX512
+; RUN:  opt < %s -slp-vectorizer -instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX512
+
+define void @gather_load(i32* noalias nocapture %0, i32* noalias nocapture readonly %1) {
+; CHECK-LABEL: @gather_load(
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP1:%.*]], i64 1
+; CHECK-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP1]], align 4, [[TBAA0:!tbaa !.*]]
+; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 11
+; CHECK-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4, [[TBAA0]]
+; CHECK-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 4
+; CHECK-NEXT:    [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4, [[TBAA0]]
+; CHECK-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP3]], align 4, [[TBAA0]]
+; CHECK-NEXT:    [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; CHECK-NEXT:    [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i32 1
+; CHECK-NEXT:    [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i32 2
+; CHECK-NEXT:    [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i32 3
+; CHECK-NEXT:    [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4>
+; CHECK-NEXT:    [[TMP15:%.*]] = bitcast i32* [[TMP0:%.*]] to <4 x i32>*
+; CHECK-NEXT:    store <4 x i32> [[TMP14]], <4 x i32>* [[TMP15]], align 4, [[TBAA0]]
+; CHECK-NEXT:    ret void
+;
+  %3 = getelementptr inbounds i32, i32* %1, i64 1
+  %4 = load i32, i32* %1, align 4, !tbaa !2
+  %5 = getelementptr inbounds i32, i32* %0, i64 1
+  %6 = getelementptr inbounds i32, i32* %1, i64 11
+  %7 = load i32, i32* %6, align 4, !tbaa !2
+  %8 = getelementptr inbounds i32, i32* %0, i64 2
+  %9 = getelementptr inbounds i32, i32* %1, i64 4
+  %10 = load i32, i32* %9, align 4, !tbaa !2
+  %11 = getelementptr inbounds i32, i32* %0, i64 3
+  %12 = load i32, i32* %3, align 4, !tbaa !2
+  %13 = insertelement <4 x i32> poison, i32 %4, i32 0
+  %14 = insertelement <4 x i32> %13, i32 %7, i32 1
+  %15 = insertelement <4 x i32> %14, i32 %10, i32 2
+  %16 = insertelement <4 x i32> %15, i32 %12, i32 3
+  %17 = add nsw <4 x i32> %16, <i32 1, i32 2, i32 3, i32 4>
+  %18 = bitcast i32* %0 to <4 x i32>*
+  store <4 x i32> %17, <4 x i32>* %18, align 4, !tbaa !2
+  ret void
+}
+
+define void @gather_load_2(i32* noalias nocapture %0, i32* noalias nocapture readonly %1) {
+; SSE-LABEL: @gather_load_2(
+; SSE-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP1:%.*]], i64 1
+; SSE-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4, [[TBAA0:!tbaa !.*]]
+; SSE-NEXT:    [[TMP5:%.*]] = add nsw i32 [[TMP4]], 1
+; SSE-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP0:%.*]], i64 1
+; SSE-NEXT:    store i32 [[TMP5]], i32* [[TMP0]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 10
+; SSE-NEXT:    [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP9:%.*]] = add nsw i32 [[TMP8]], 2
+; SSE-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 2
+; SSE-NEXT:    store i32 [[TMP9]], i32* [[TMP6]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 3
+; SSE-NEXT:    [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP13:%.*]] = add nsw i32 [[TMP12]], 3
+; SSE-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 3
+; SSE-NEXT:    store i32 [[TMP13]], i32* [[TMP10]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP15:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 5
+; SSE-NEXT:    [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP17:%.*]] = add nsw i32 [[TMP16]], 4
+; SSE-NEXT:    store i32 [[TMP17]], i32* [[TMP14]], align 4, [[TBAA0]]
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @gather_load_2(
+; AVX-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP1:%.*]], i64 1
+; AVX-NEXT:    [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4, [[TBAA0:!tbaa !.*]]
+; AVX-NEXT:    [[TMP5:%.*]] = add nsw i32 [[TMP4]], 1
+; AVX-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP0:%.*]], i64 1
+; AVX-NEXT:    store i32 [[TMP5]], i32* [[TMP0]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 10
+; AVX-NEXT:    [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP9:%.*]] = add nsw i32 [[TMP8]], 2
+; AVX-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 2
+; AVX-NEXT:    store i32 [[TMP9]], i32* [[TMP6]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 3
+; AVX-NEXT:    [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP13:%.*]] = add nsw i32 [[TMP12]], 3
+; AVX-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 3
+; AVX-NEXT:    store i32 [[TMP13]], i32* [[TMP10]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP15:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 5
+; AVX-NEXT:    [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP17:%.*]] = add nsw i32 [[TMP16]], 4
+; AVX-NEXT:    store i32 [[TMP17]], i32* [[TMP14]], align 4, [[TBAA0]]
+; AVX-NEXT:    ret void
+;
+; AVX2-LABEL: @gather_load_2(
+; AVX2-NEXT:    [[TMP3:%.*]] = insertelement <4 x i32*> undef, i32* [[TMP1:%.*]], i32 0
+; AVX2-NEXT:    [[TMP4:%.*]] = shufflevector <4 x i32*> [[TMP3]], <4 x i32*> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:    [[TMP5:%.*]] = getelementptr i32, <4 x i32*> [[TMP4]], <4 x i64> <i64 1, i64 10, i64 3, i64 5>
+; AVX2-NEXT:    [[TMP6:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP5]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef), [[TBAA0:!tbaa !.*]]
+; AVX2-NEXT:    [[TMP7:%.*]] = add nsw <4 x i32> [[TMP6]], <i32 1, i32 2, i32 3, i32 4>
+; AVX2-NEXT:    [[TMP8:%.*]] = bitcast i32* [[TMP0:%.*]] to <4 x i32>*
+; AVX2-NEXT:    store <4 x i32> [[TMP7]], <4 x i32>* [[TMP8]], align 4, [[TBAA0]]
+; AVX2-NEXT:    ret void
+;
+; AVX512-LABEL: @gather_load_2(
+; AVX512-NEXT:    [[TMP3:%.*]] = insertelement <4 x i32*> undef, i32* [[TMP1:%.*]], i32 0
+; AVX512-NEXT:    [[TMP4:%.*]] = shufflevector <4 x i32*> [[TMP3]], <4 x i32*> undef, <4 x i32> zeroinitializer
+; AVX512-NEXT:    [[TMP5:%.*]] = getelementptr i32, <4 x i32*> [[TMP4]], <4 x i64> <i64 1, i64 10, i64 3, i64 5>
+; AVX512-NEXT:    [[TMP6:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP5]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef), [[TBAA0:!tbaa !.*]]
+; AVX512-NEXT:    [[TMP7:%.*]] = add nsw <4 x i32> [[TMP6]], <i32 1, i32 2, i32 3, i32 4>
+; AVX512-NEXT:    [[TMP8:%.*]] = bitcast i32* [[TMP0:%.*]] to <4 x i32>*
+; AVX512-NEXT:    store <4 x i32> [[TMP7]], <4 x i32>* [[TMP8]], align 4, [[TBAA0]]
+; AVX512-NEXT:    ret void
+;
+  %3 = getelementptr inbounds i32, i32* %1, i64 1
+  %4 = load i32, i32* %3, align 4, !tbaa !2
+  %5 = add nsw i32 %4, 1
+  %6 = getelementptr inbounds i32, i32* %0, i64 1
+  store i32 %5, i32* %0, align 4, !tbaa !2
+  %7 = getelementptr inbounds i32, i32* %1, i64 10
+  %8 = load i32, i32* %7, align 4, !tbaa !2
+  %9 = add nsw i32 %8, 2
+  %10 = getelementptr inbounds i32, i32* %0, i64 2
+  store i32 %9, i32* %6, align 4, !tbaa !2
+  %11 = getelementptr inbounds i32, i32* %1, i64 3
+  %12 = load i32, i32* %11, align 4, !tbaa !2
+  %13 = add nsw i32 %12, 3
+  %14 = getelementptr inbounds i32, i32* %0, i64 3
+  store i32 %13, i32* %10, align 4, !tbaa !2
+  %15 = getelementptr inbounds i32, i32* %1, i64 5
+  %16 = load i32, i32* %15, align 4, !tbaa !2
+  %17 = add nsw i32 %16, 4
+  store i32 %17, i32* %14, align 4, !tbaa !2
+  ret void
+}
+
+
+define void @gather_load_3(i32* noalias nocapture %0, i32* noalias nocapture readonly %1) {
+; SSE-LABEL: @gather_load_3(
+; SSE-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1:%.*]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP4:%.*]] = add i32 [[TMP3]], 1
+; SSE-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[TMP0:%.*]], i64 1
+; SSE-NEXT:    store i32 [[TMP4]], i32* [[TMP0]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 11
+; SSE-NEXT:    [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP8:%.*]] = add i32 [[TMP7]], 2
+; SSE-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 2
+; SSE-NEXT:    store i32 [[TMP8]], i32* [[TMP5]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 4
+; SSE-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP12:%.*]] = add i32 [[TMP11]], 3
+; SSE-NEXT:    [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 3
+; SSE-NEXT:    store i32 [[TMP12]], i32* [[TMP9]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 15
+; SSE-NEXT:    [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP16:%.*]] = add i32 [[TMP15]], 4
+; SSE-NEXT:    [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 4
+; SSE-NEXT:    store i32 [[TMP16]], i32* [[TMP13]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP18:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 18
+; SSE-NEXT:    [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP20:%.*]] = add i32 [[TMP19]], 1
+; SSE-NEXT:    [[TMP21:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 5
+; SSE-NEXT:    store i32 [[TMP20]], i32* [[TMP17]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP22:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 9
+; SSE-NEXT:    [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP24:%.*]] = add i32 [[TMP23]], 2
+; SSE-NEXT:    [[TMP25:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 6
+; SSE-NEXT:    store i32 [[TMP24]], i32* [[TMP21]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP26:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 6
+; SSE-NEXT:    [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP28:%.*]] = add i32 [[TMP27]], 3
+; SSE-NEXT:    [[TMP29:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 7
+; SSE-NEXT:    store i32 [[TMP28]], i32* [[TMP25]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP30:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 21
+; SSE-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP32:%.*]] = add i32 [[TMP31]], 4
+; SSE-NEXT:    store i32 [[TMP32]], i32* [[TMP29]], align 4, [[TBAA0]]
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @gather_load_3(
+; AVX-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1:%.*]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP4:%.*]] = add i32 [[TMP3]], 1
+; AVX-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[TMP0:%.*]], i64 1
+; AVX-NEXT:    store i32 [[TMP4]], i32* [[TMP0]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 11
+; AVX-NEXT:    [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP8:%.*]] = add i32 [[TMP7]], 2
+; AVX-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 2
+; AVX-NEXT:    store i32 [[TMP8]], i32* [[TMP5]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 4
+; AVX-NEXT:    [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP12:%.*]] = add i32 [[TMP11]], 3
+; AVX-NEXT:    [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 3
+; AVX-NEXT:    store i32 [[TMP12]], i32* [[TMP9]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP14:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 15
+; AVX-NEXT:    [[TMP15:%.*]] = load i32, i32* [[TMP14]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP16:%.*]] = add i32 [[TMP15]], 4
+; AVX-NEXT:    [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 4
+; AVX-NEXT:    store i32 [[TMP16]], i32* [[TMP13]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP18:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 18
+; AVX-NEXT:    [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP20:%.*]] = add i32 [[TMP19]], 1
+; AVX-NEXT:    [[TMP21:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 5
+; AVX-NEXT:    store i32 [[TMP20]], i32* [[TMP17]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP22:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 9
+; AVX-NEXT:    [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP24:%.*]] = add i32 [[TMP23]], 2
+; AVX-NEXT:    [[TMP25:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 6
+; AVX-NEXT:    store i32 [[TMP24]], i32* [[TMP21]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP26:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 6
+; AVX-NEXT:    [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP28:%.*]] = add i32 [[TMP27]], 3
+; AVX-NEXT:    [[TMP29:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 7
+; AVX-NEXT:    store i32 [[TMP28]], i32* [[TMP25]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP30:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 21
+; AVX-NEXT:    [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[TMP32:%.*]] = add i32 [[TMP31]], 4
+; AVX-NEXT:    store i32 [[TMP32]], i32* [[TMP29]], align 4, [[TBAA0]]
+; AVX-NEXT:    ret void
+;
+; AVX2-LABEL: @gather_load_3(
+; AVX2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1:%.*]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP4:%.*]] = add i32 [[TMP3]], 1
+; AVX2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[TMP0:%.*]], i64 1
+; AVX2-NEXT:    store i32 [[TMP4]], i32* [[TMP0]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP6:%.*]] = insertelement <4 x i32*> undef, i32* [[TMP1]], i32 0
+; AVX2-NEXT:    [[TMP7:%.*]] = shufflevector <4 x i32*> [[TMP6]], <4 x i32*> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:    [[TMP8:%.*]] = getelementptr i32, <4 x i32*> [[TMP7]], <4 x i64> <i64 11, i64 4, i64 15, i64 18>
+; AVX2-NEXT:    [[TMP9:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP8]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef), [[TBAA0]]
+; AVX2-NEXT:    [[TMP10:%.*]] = add <4 x i32> [[TMP9]], <i32 2, i32 3, i32 4, i32 1>
+; AVX2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 5
+; AVX2-NEXT:    [[TMP12:%.*]] = bitcast i32* [[TMP5]] to <4 x i32>*
+; AVX2-NEXT:    store <4 x i32> [[TMP10]], <4 x i32>* [[TMP12]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 9
+; AVX2-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP15:%.*]] = add i32 [[TMP14]], 2
+; AVX2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 6
+; AVX2-NEXT:    store i32 [[TMP15]], i32* [[TMP11]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 6
+; AVX2-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP19:%.*]] = add i32 [[TMP18]], 3
+; AVX2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 7
+; AVX2-NEXT:    store i32 [[TMP19]], i32* [[TMP16]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 21
+; AVX2-NEXT:    [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP23:%.*]] = add i32 [[TMP22]], 4
+; AVX2-NEXT:    store i32 [[TMP23]], i32* [[TMP20]], align 4, [[TBAA0]]
+; AVX2-NEXT:    ret void
+;
+; AVX512-LABEL: @gather_load_3(
+; AVX512-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP1:%.*]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP4:%.*]] = add i32 [[TMP3]], 1
+; AVX512-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i32, i32* [[TMP0:%.*]], i64 1
+; AVX512-NEXT:    store i32 [[TMP4]], i32* [[TMP0]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP6:%.*]] = insertelement <4 x i32*> undef, i32* [[TMP1]], i32 0
+; AVX512-NEXT:    [[TMP7:%.*]] = shufflevector <4 x i32*> [[TMP6]], <4 x i32*> undef, <4 x i32> zeroinitializer
+; AVX512-NEXT:    [[TMP8:%.*]] = getelementptr i32, <4 x i32*> [[TMP7]], <4 x i64> <i64 11, i64 4, i64 15, i64 18>
+; AVX512-NEXT:    [[TMP9:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP8]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef), [[TBAA0]]
+; AVX512-NEXT:    [[TMP10:%.*]] = add <4 x i32> [[TMP9]], <i32 2, i32 3, i32 4, i32 1>
+; AVX512-NEXT:    [[TMP11:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 5
+; AVX512-NEXT:    [[TMP12:%.*]] = bitcast i32* [[TMP5]] to <4 x i32>*
+; AVX512-NEXT:    store <4 x i32> [[TMP10]], <4 x i32>* [[TMP12]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP13:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 9
+; AVX512-NEXT:    [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP15:%.*]] = add i32 [[TMP14]], 2
+; AVX512-NEXT:    [[TMP16:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 6
+; AVX512-NEXT:    store i32 [[TMP15]], i32* [[TMP11]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP17:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 6
+; AVX512-NEXT:    [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP19:%.*]] = add i32 [[TMP18]], 3
+; AVX512-NEXT:    [[TMP20:%.*]] = getelementptr inbounds i32, i32* [[TMP0]], i64 7
+; AVX512-NEXT:    store i32 [[TMP19]], i32* [[TMP16]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP21:%.*]] = getelementptr inbounds i32, i32* [[TMP1]], i64 21
+; AVX512-NEXT:    [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP23:%.*]] = add i32 [[TMP22]], 4
+; AVX512-NEXT:    store i32 [[TMP23]], i32* [[TMP20]], align 4, [[TBAA0]]
+; AVX512-NEXT:    ret void
+;
+  %3 = load i32, i32* %1, align 4, !tbaa !2
+  %4 = add i32 %3, 1
+  %5 = getelementptr inbounds i32, i32* %0, i64 1
+  store i32 %4, i32* %0, align 4, !tbaa !2
+  %6 = getelementptr inbounds i32, i32* %1, i64 11
+  %7 = load i32, i32* %6, align 4, !tbaa !2
+  %8 = add i32 %7, 2
+  %9 = getelementptr inbounds i32, i32* %0, i64 2
+  store i32 %8, i32* %5, align 4, !tbaa !2
+  %10 = getelementptr inbounds i32, i32* %1, i64 4
+  %11 = load i32, i32* %10, align 4, !tbaa !2
+  %12 = add i32 %11, 3
+  %13 = getelementptr inbounds i32, i32* %0, i64 3
+  store i32 %12, i32* %9, align 4, !tbaa !2
+  %14 = getelementptr inbounds i32, i32* %1, i64 15
+  %15 = load i32, i32* %14, align 4, !tbaa !2
+  %16 = add i32 %15, 4
+  %17 = getelementptr inbounds i32, i32* %0, i64 4
+  store i32 %16, i32* %13, align 4, !tbaa !2
+  %18 = getelementptr inbounds i32, i32* %1, i64 18
+  %19 = load i32, i32* %18, align 4, !tbaa !2
+  %20 = add i32 %19, 1
+  %21 = getelementptr inbounds i32, i32* %0, i64 5
+  store i32 %20, i32* %17, align 4, !tbaa !2
+  %22 = getelementptr inbounds i32, i32* %1, i64 9
+  %23 = load i32, i32* %22, align 4, !tbaa !2
+  %24 = add i32 %23, 2
+  %25 = getelementptr inbounds i32, i32* %0, i64 6
+  store i32 %24, i32* %21, align 4, !tbaa !2
+  %26 = getelementptr inbounds i32, i32* %1, i64 6
+  %27 = load i32, i32* %26, align 4, !tbaa !2
+  %28 = add i32 %27, 3
+  %29 = getelementptr inbounds i32, i32* %0, i64 7
+  store i32 %28, i32* %25, align 4, !tbaa !2
+  %30 = getelementptr inbounds i32, i32* %1, i64 21
+  %31 = load i32, i32* %30, align 4, !tbaa !2
+  %32 = add i32 %31, 4
+  store i32 %32, i32* %29, align 4, !tbaa !2
+  ret void
+}
+
+define void @gather_load_4(i32* noalias nocapture %t0, i32* noalias nocapture readonly %t1) {
+; SSE-LABEL: @gather_load_4(
+; SSE-NEXT:    [[T5:%.*]] = getelementptr inbounds i32, i32* [[T0:%.*]], i64 1
+; SSE-NEXT:    [[T6:%.*]] = getelementptr inbounds i32, i32* [[T1:%.*]], i64 11
+; SSE-NEXT:    [[T9:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 2
+; SSE-NEXT:    [[T10:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 4
+; SSE-NEXT:    [[T13:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 3
+; SSE-NEXT:    [[T14:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 15
+; SSE-NEXT:    [[T17:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 4
+; SSE-NEXT:    [[T18:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 18
+; SSE-NEXT:    [[T21:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 5
+; SSE-NEXT:    [[T22:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 9
+; SSE-NEXT:    [[T25:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 6
+; SSE-NEXT:    [[T26:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 6
+; SSE-NEXT:    [[T29:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 7
+; SSE-NEXT:    [[T30:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 21
+; SSE-NEXT:    [[T3:%.*]] = load i32, i32* [[T1]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[T7:%.*]] = load i32, i32* [[T6]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[T11:%.*]] = load i32, i32* [[T10]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[T15:%.*]] = load i32, i32* [[T14]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[T19:%.*]] = load i32, i32* [[T18]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[T23:%.*]] = load i32, i32* [[T22]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[T27:%.*]] = load i32, i32* [[T26]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[T31:%.*]] = load i32, i32* [[T30]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[T4:%.*]] = add i32 [[T3]], 1
+; SSE-NEXT:    [[T8:%.*]] = add i32 [[T7]], 2
+; SSE-NEXT:    [[T12:%.*]] = add i32 [[T11]], 3
+; SSE-NEXT:    [[T16:%.*]] = add i32 [[T15]], 4
+; SSE-NEXT:    [[T20:%.*]] = add i32 [[T19]], 1
+; SSE-NEXT:    [[T24:%.*]] = add i32 [[T23]], 2
+; SSE-NEXT:    [[T28:%.*]] = add i32 [[T27]], 3
+; SSE-NEXT:    [[T32:%.*]] = add i32 [[T31]], 4
+; SSE-NEXT:    store i32 [[T4]], i32* [[T0]], align 4, [[TBAA0]]
+; SSE-NEXT:    store i32 [[T8]], i32* [[T5]], align 4, [[TBAA0]]
+; SSE-NEXT:    store i32 [[T12]], i32* [[T9]], align 4, [[TBAA0]]
+; SSE-NEXT:    store i32 [[T16]], i32* [[T13]], align 4, [[TBAA0]]
+; SSE-NEXT:    store i32 [[T20]], i32* [[T17]], align 4, [[TBAA0]]
+; SSE-NEXT:    store i32 [[T24]], i32* [[T21]], align 4, [[TBAA0]]
+; SSE-NEXT:    store i32 [[T28]], i32* [[T25]], align 4, [[TBAA0]]
+; SSE-NEXT:    store i32 [[T32]], i32* [[T29]], align 4, [[TBAA0]]
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @gather_load_4(
+; AVX-NEXT:    [[T5:%.*]] = getelementptr inbounds i32, i32* [[T0:%.*]], i64 1
+; AVX-NEXT:    [[T6:%.*]] = getelementptr inbounds i32, i32* [[T1:%.*]], i64 11
+; AVX-NEXT:    [[T9:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 2
+; AVX-NEXT:    [[T10:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 4
+; AVX-NEXT:    [[T13:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 3
+; AVX-NEXT:    [[T14:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 15
+; AVX-NEXT:    [[T17:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 4
+; AVX-NEXT:    [[T18:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 18
+; AVX-NEXT:    [[T21:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 5
+; AVX-NEXT:    [[T22:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 9
+; AVX-NEXT:    [[T25:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 6
+; AVX-NEXT:    [[T26:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 6
+; AVX-NEXT:    [[T29:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 7
+; AVX-NEXT:    [[T30:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 21
+; AVX-NEXT:    [[T3:%.*]] = load i32, i32* [[T1]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[T7:%.*]] = load i32, i32* [[T6]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[T11:%.*]] = load i32, i32* [[T10]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[T15:%.*]] = load i32, i32* [[T14]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[T19:%.*]] = load i32, i32* [[T18]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[T23:%.*]] = load i32, i32* [[T22]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[T27:%.*]] = load i32, i32* [[T26]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[T31:%.*]] = load i32, i32* [[T30]], align 4, [[TBAA0]]
+; AVX-NEXT:    [[T4:%.*]] = add i32 [[T3]], 1
+; AVX-NEXT:    [[T8:%.*]] = add i32 [[T7]], 2
+; AVX-NEXT:    [[T12:%.*]] = add i32 [[T11]], 3
+; AVX-NEXT:    [[T16:%.*]] = add i32 [[T15]], 4
+; AVX-NEXT:    [[T20:%.*]] = add i32 [[T19]], 1
+; AVX-NEXT:    [[T24:%.*]] = add i32 [[T23]], 2
+; AVX-NEXT:    [[T28:%.*]] = add i32 [[T27]], 3
+; AVX-NEXT:    [[T32:%.*]] = add i32 [[T31]], 4
+; AVX-NEXT:    store i32 [[T4]], i32* [[T0]], align 4, [[TBAA0]]
+; AVX-NEXT:    store i32 [[T8]], i32* [[T5]], align 4, [[TBAA0]]
+; AVX-NEXT:    store i32 [[T12]], i32* [[T9]], align 4, [[TBAA0]]
+; AVX-NEXT:    store i32 [[T16]], i32* [[T13]], align 4, [[TBAA0]]
+; AVX-NEXT:    store i32 [[T20]], i32* [[T17]], align 4, [[TBAA0]]
+; AVX-NEXT:    store i32 [[T24]], i32* [[T21]], align 4, [[TBAA0]]
+; AVX-NEXT:    store i32 [[T28]], i32* [[T25]], align 4, [[TBAA0]]
+; AVX-NEXT:    store i32 [[T32]], i32* [[T29]], align 4, [[TBAA0]]
+; AVX-NEXT:    ret void
+;
+; AVX2-LABEL: @gather_load_4(
+; AVX2-NEXT:    [[T5:%.*]] = getelementptr inbounds i32, i32* [[T0:%.*]], i64 1
+; AVX2-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32*> undef, i32* [[T1:%.*]], i32 0
+; AVX2-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32*> [[TMP1]], <4 x i32*> undef, <4 x i32> zeroinitializer
+; AVX2-NEXT:    [[TMP3:%.*]] = getelementptr i32, <4 x i32*> [[TMP2]], <4 x i64> <i64 11, i64 4, i64 15, i64 18>
+; AVX2-NEXT:    [[T21:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 5
+; AVX2-NEXT:    [[T22:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 9
+; AVX2-NEXT:    [[T25:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 6
+; AVX2-NEXT:    [[T26:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 6
+; AVX2-NEXT:    [[T29:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 7
+; AVX2-NEXT:    [[T30:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 21
+; AVX2-NEXT:    [[T3:%.*]] = load i32, i32* [[T1]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP3]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef), [[TBAA0]]
+; AVX2-NEXT:    [[T23:%.*]] = load i32, i32* [[T22]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[T27:%.*]] = load i32, i32* [[T26]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[T31:%.*]] = load i32, i32* [[T30]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[T4:%.*]] = add i32 [[T3]], 1
+; AVX2-NEXT:    [[TMP5:%.*]] = add <4 x i32> [[TMP4]], <i32 2, i32 3, i32 4, i32 1>
+; AVX2-NEXT:    [[T24:%.*]] = add i32 [[T23]], 2
+; AVX2-NEXT:    [[T28:%.*]] = add i32 [[T27]], 3
+; AVX2-NEXT:    [[T32:%.*]] = add i32 [[T31]], 4
+; AVX2-NEXT:    store i32 [[T4]], i32* [[T0]], align 4, [[TBAA0]]
+; AVX2-NEXT:    [[TMP6:%.*]] = bitcast i32* [[T5]] to <4 x i32>*
+; AVX2-NEXT:    store <4 x i32> [[TMP5]], <4 x i32>* [[TMP6]], align 4, [[TBAA0]]
+; AVX2-NEXT:    store i32 [[T24]], i32* [[T21]], align 4, [[TBAA0]]
+; AVX2-NEXT:    store i32 [[T28]], i32* [[T25]], align 4, [[TBAA0]]
+; AVX2-NEXT:    store i32 [[T32]], i32* [[T29]], align 4, [[TBAA0]]
+; AVX2-NEXT:    ret void
+;
+; AVX512-LABEL: @gather_load_4(
+; AVX512-NEXT:    [[T5:%.*]] = getelementptr inbounds i32, i32* [[T0:%.*]], i64 1
+; AVX512-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32*> undef, i32* [[T1:%.*]], i32 0
+; AVX512-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32*> [[TMP1]], <4 x i32*> undef, <4 x i32> zeroinitializer
+; AVX512-NEXT:    [[TMP3:%.*]] = getelementptr i32, <4 x i32*> [[TMP2]], <4 x i64> <i64 11, i64 4, i64 15, i64 18>
+; AVX512-NEXT:    [[T21:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 5
+; AVX512-NEXT:    [[T22:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 9
+; AVX512-NEXT:    [[T25:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 6
+; AVX512-NEXT:    [[T26:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 6
+; AVX512-NEXT:    [[T29:%.*]] = getelementptr inbounds i32, i32* [[T0]], i64 7
+; AVX512-NEXT:    [[T30:%.*]] = getelementptr inbounds i32, i32* [[T1]], i64 21
+; AVX512-NEXT:    [[T3:%.*]] = load i32, i32* [[T1]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP4:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> [[TMP3]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef), [[TBAA0]]
+; AVX512-NEXT:    [[T23:%.*]] = load i32, i32* [[T22]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[T27:%.*]] = load i32, i32* [[T26]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[T31:%.*]] = load i32, i32* [[T30]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[T4:%.*]] = add i32 [[T3]], 1
+; AVX512-NEXT:    [[TMP5:%.*]] = add <4 x i32> [[TMP4]], <i32 2, i32 3, i32 4, i32 1>
+; AVX512-NEXT:    [[T24:%.*]] = add i32 [[T23]], 2
+; AVX512-NEXT:    [[T28:%.*]] = add i32 [[T27]], 3
+; AVX512-NEXT:    [[T32:%.*]] = add i32 [[T31]], 4
+; AVX512-NEXT:    store i32 [[T4]], i32* [[T0]], align 4, [[TBAA0]]
+; AVX512-NEXT:    [[TMP6:%.*]] = bitcast i32* [[T5]] to <4 x i32>*
+; AVX512-NEXT:    store <4 x i32> [[TMP5]], <4 x i32>* [[TMP6]], align 4, [[TBAA0]]
+; AVX512-NEXT:    store i32 [[T24]], i32* [[T21]], align 4, [[TBAA0]]
+; AVX512-NEXT:    store i32 [[T28]], i32* [[T25]], align 4, [[TBAA0]]
+; AVX512-NEXT:    store i32 [[T32]], i32* [[T29]], align 4, [[TBAA0]]
+; AVX512-NEXT:    ret void
+;
+  %t5 = getelementptr inbounds i32, i32* %t0, i64 1
+  %t6 = getelementptr inbounds i32, i32* %t1, i64 11
+  %t9 = getelementptr inbounds i32, i32* %t0, i64 2
+  %t10 = getelementptr inbounds i32, i32* %t1, i64 4
+  %t13 = getelementptr inbounds i32, i32* %t0, i64 3
+  %t14 = getelementptr inbounds i32, i32* %t1, i64 15
+  %t17 = getelementptr inbounds i32, i32* %t0, i64 4
+  %t18 = getelementptr inbounds i32, i32* %t1, i64 18
+  %t21 = getelementptr inbounds i32, i32* %t0, i64 5
+  %t22 = getelementptr inbounds i32, i32* %t1, i64 9
+  %t25 = getelementptr inbounds i32, i32* %t0, i64 6
+  %t26 = getelementptr inbounds i32, i32* %t1, i64 6
+  %t29 = getelementptr inbounds i32, i32* %t0, i64 7
+  %t30 = getelementptr inbounds i32, i32* %t1, i64 21
+
+  %t3 = load i32, i32* %t1, align 4, !tbaa !2
+  %t7 = load i32, i32* %t6, align 4, !tbaa !2
+  %t11 = load i32, i32* %t10, align 4, !tbaa !2
+  %t15 = load i32, i32* %t14, align 4, !tbaa !2
+  %t19 = load i32, i32* %t18, align 4, !tbaa !2
+  %t23 = load i32, i32* %t22, align 4, !tbaa !2
+  %t27 = load i32, i32* %t26, align 4, !tbaa !2
+  %t31 = load i32, i32* %t30, align 4, !tbaa !2
+
+  %t4 = add i32 %t3, 1
+  %t8 = add i32 %t7, 2
+  %t12 = add i32 %t11, 3
+  %t16 = add i32 %t15, 4
+  %t20 = add i32 %t19, 1
+  %t24 = add i32 %t23, 2
+  %t28 = add i32 %t27, 3
+  %t32 = add i32 %t31, 4
+
+  store i32 %t4, i32* %t0, align 4, !tbaa !2
+  store i32 %t8, i32* %t5, align 4, !tbaa !2
+  store i32 %t12, i32* %t9, align 4, !tbaa !2
+  store i32 %t16, i32* %t13, align 4, !tbaa !2
+  store i32 %t20, i32* %t17, align 4, !tbaa !2
+  store i32 %t24, i32* %t21, align 4, !tbaa !2
+  store i32 %t28, i32* %t25, align 4, !tbaa !2
+  store i32 %t32, i32* %t29, align 4, !tbaa !2
+
+  ret void
+}
+
+
+define void @gather_load_div(float* noalias nocapture %0, float* noalias nocapture readonly %1) {
+; SSE-LABEL: @gather_load_div(
+; SSE-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, float* [[TMP1:%.*]], i64 10
+; SSE-NEXT:    [[TMP4:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3
+; SSE-NEXT:    [[TMP5:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 14
+; SSE-NEXT:    [[TMP6:%.*]] = insertelement <4 x float*> undef, float* [[TMP1]], i32 0
+; SSE-NEXT:    [[TMP7:%.*]] = insertelement <4 x float*> [[TMP6]], float* [[TMP3]], i32 1
+; SSE-NEXT:    [[TMP8:%.*]] = insertelement <4 x float*> [[TMP7]], float* [[TMP4]], i32 2
+; SSE-NEXT:    [[TMP9:%.*]] = insertelement <4 x float*> [[TMP8]], float* [[TMP5]], i32 3
+; SSE-NEXT:    [[TMP10:%.*]] = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> [[TMP9]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef), [[TBAA0]]
+; SSE-NEXT:    [[TMP11:%.*]] = shufflevector <4 x float*> [[TMP6]], <4 x float*> undef, <4 x i32> zeroinitializer
+; SSE-NEXT:    [[TMP12:%.*]] = getelementptr float, <4 x float*> [[TMP11]], <4 x i64> <i64 4, i64 13, i64 11, i64 44>
+; SSE-NEXT:    [[TMP13:%.*]] = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> [[TMP12]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef), [[TBAA0]]
+; SSE-NEXT:    [[TMP14:%.*]] = fdiv <4 x float> [[TMP10]], [[TMP13]]
+; SSE-NEXT:    [[TMP15:%.*]] = getelementptr inbounds float, float* [[TMP0:%.*]], i64 4
+; SSE-NEXT:    [[TMP16:%.*]] = bitcast float* [[TMP0]] to <4 x float>*
+; SSE-NEXT:    store <4 x float> [[TMP14]], <4 x float>* [[TMP16]], align 4, [[TBAA0]]
+; SSE-NEXT:    [[TMP17:%.*]] = getelementptr float, <4 x float*> [[TMP11]], <4 x i64> <i64 17, i64 8, i64 5, i64 20>
+; SSE-NEXT:    [[TMP18:%.*]] = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> [[TMP17]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef), [[TBAA0]]
+; SSE-NEXT:    [[TMP19:%.*]] = getelementptr float, <4 x float*> [[TMP11]], <4 x i64> <i64 33, i64 30, i64 27, i64 23>
+; SSE-NEXT:    [[TMP20:%.*]] = call <4 x float> @llvm.masked.gather.v4f32.v4p0f32(<4 x float*> [[TMP19]], i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> undef), [[TBAA0]]
+; SSE-NEXT:    [[TMP21:%.*]] = fdiv <4 x float> [[TMP18]], [[TMP20]]
+; SSE-NEXT:    [[TMP22:%.*]] = bitcast float* [[TMP15]] to <4 x float>*
+; SSE-NEXT:    store <4 x float> [[TMP21]], <4 x float>* [[TMP22]], align 4, [[TBAA0]]
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @gather_load_div(
+; AVX-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, float* [[TMP1:%.*]], i64 10
+; AVX-NEXT:    [[TMP4:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3
+; AVX-NEXT:    [[TMP5:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 14
+; AVX-NEXT:    [[TMP6:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 17
+; AVX-NEXT:    [[TMP7:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 8
+; AVX-NEXT:    [[TMP8:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 5
+; AVX-NEXT:    [[TMP9:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 20
+; AVX-NEXT:    [[TMP10:%.*]] = insertelement <8 x float*> undef, float* [[TMP1]], i32 0
+; AVX-NEXT:    [[TMP11:%.*]] = insertelement <8 x float*> [[TMP10]], float* [[TMP3]], i32 1
+; AVX-NEXT:    [[TMP12:%.*]] = insertelement <8 x float*> [[TMP11]], float* [[TMP4]], i32 2
+; AVX-NEXT:    [[TMP13:%.*]] = insertelement <8 x float*> [[TMP12]], float* [[TMP5]], i32 3
+; AVX-NEXT:    [[TMP14:%.*]] = insertelement <8 x float*> [[TMP13]], float* [[TMP6]], i32 4
+; AVX-NEXT:    [[TMP15:%.*]] = insertelement <8 x float*> [[TMP14]], float* [[TMP7]], i32 5
+; AVX-NEXT:    [[TMP16:%.*]] = insertelement <8 x float*> [[TMP15]], float* [[TMP8]], i32 6
+; AVX-NEXT:    [[TMP17:%.*]] = insertelement <8 x float*> [[TMP16]], float* [[TMP9]], i32 7
+; AVX-NEXT:    [[TMP18:%.*]] = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> [[TMP17]], i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef), [[TBAA0]]
+; AVX-NEXT:    [[TMP19:%.*]] = shufflevector <8 x float*> [[TMP10]], <8 x float*> undef, <8 x i32> zeroinitializer
+; AVX-NEXT:    [[TMP20:%.*]] = getelementptr float, <8 x float*> [[TMP19]], <8 x i64> <i64 4, i64 13, i64 11, i64 44, i64 33, i64 30, i64 27, i64 23>
+; AVX-NEXT:    [[TMP21:%.*]] = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> [[TMP20]], i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef), [[TBAA0]]
+; AVX-NEXT:    [[TMP22:%.*]] = fdiv <8 x float> [[TMP18]], [[TMP21]]
+; AVX-NEXT:    [[TMP23:%.*]] = bitcast float* [[TMP0:%.*]] to <8 x float>*
+; AVX-NEXT:    store <8 x float> [[TMP22]], <8 x float>* [[TMP23]], align 4, [[TBAA0]]
+; AVX-NEXT:    ret void
+;
+; AVX2-LABEL: @gather_load_div(
+; AVX2-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, float* [[TMP1:%.*]], i64 10
+; AVX2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3
+; AVX2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 14
+; AVX2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 17
+; AVX2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 8
+; AVX2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 5
+; AVX2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 20
+; AVX2-NEXT:    [[TMP10:%.*]] = insertelement <8 x float*> undef, float* [[TMP1]], i32 0
+; AVX2-NEXT:    [[TMP11:%.*]] = insertelement <8 x float*> [[TMP10]], float* [[TMP3]], i32 1
+; AVX2-NEXT:    [[TMP12:%.*]] = insertelement <8 x float*> [[TMP11]], float* [[TMP4]], i32 2
+; AVX2-NEXT:    [[TMP13:%.*]] = insertelement <8 x float*> [[TMP12]], float* [[TMP5]], i32 3
+; AVX2-NEXT:    [[TMP14:%.*]] = insertelement <8 x float*> [[TMP13]], float* [[TMP6]], i32 4
+; AVX2-NEXT:    [[TMP15:%.*]] = insertelement <8 x float*> [[TMP14]], float* [[TMP7]], i32 5
+; AVX2-NEXT:    [[TMP16:%.*]] = insertelement <8 x float*> [[TMP15]], float* [[TMP8]], i32 6
+; AVX2-NEXT:    [[TMP17:%.*]] = insertelement <8 x float*> [[TMP16]], float* [[TMP9]], i32 7
+; AVX2-NEXT:    [[TMP18:%.*]] = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> [[TMP17]], i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef), [[TBAA0]]
+; AVX2-NEXT:    [[TMP19:%.*]] = shufflevector <8 x float*> [[TMP10]], <8 x float*> undef, <8 x i32> zeroinitializer
+; AVX2-NEXT:    [[TMP20:%.*]] = getelementptr float, <8 x float*> [[TMP19]], <8 x i64> <i64 4, i64 13, i64 11, i64 44, i64 33, i64 30, i64 27, i64 23>
+; AVX2-NEXT:    [[TMP21:%.*]] = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> [[TMP20]], i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef), [[TBAA0]]
+; AVX2-NEXT:    [[TMP22:%.*]] = fdiv <8 x float> [[TMP18]], [[TMP21]]
+; AVX2-NEXT:    [[TMP23:%.*]] = bitcast float* [[TMP0:%.*]] to <8 x float>*
+; AVX2-NEXT:    store <8 x float> [[TMP22]], <8 x float>* [[TMP23]], align 4, [[TBAA0]]
+; AVX2-NEXT:    ret void
+;
+; AVX512-LABEL: @gather_load_div(
+; AVX512-NEXT:    [[TMP3:%.*]] = getelementptr inbounds float, float* [[TMP1:%.*]], i64 10
+; AVX512-NEXT:    [[TMP4:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 3
+; AVX512-NEXT:    [[TMP5:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 14
+; AVX512-NEXT:    [[TMP6:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 17
+; AVX512-NEXT:    [[TMP7:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 8
+; AVX512-NEXT:    [[TMP8:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 5
+; AVX512-NEXT:    [[TMP9:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 20
+; AVX512-NEXT:    [[TMP10:%.*]] = insertelement <8 x float*> undef, float* [[TMP1]], i32 0
+; AVX512-NEXT:    [[TMP11:%.*]] = insertelement <8 x float*> [[TMP10]], float* [[TMP3]], i32 1
+; AVX512-NEXT:    [[TMP12:%.*]] = insertelement <8 x float*> [[TMP11]], float* [[TMP4]], i32 2
+; AVX512-NEXT:    [[TMP13:%.*]] = insertelement <8 x float*> [[TMP12]], float* [[TMP5]], i32 3
+; AVX512-NEXT:    [[TMP14:%.*]] = insertelement <8 x float*> [[TMP13]], float* [[TMP6]], i32 4
+; AVX512-NEXT:    [[TMP15:%.*]] = insertelement <8 x float*> [[TMP14]], float* [[TMP7]], i32 5
+; AVX512-NEXT:    [[TMP16:%.*]] = insertelement <8 x float*> [[TMP15]], float* [[TMP8]], i32 6
+; AVX512-NEXT:    [[TMP17:%.*]] = insertelement <8 x float*> [[TMP16]], float* [[TMP9]], i32 7
+; AVX512-NEXT:    [[TMP18:%.*]] = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> [[TMP17]], i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef), [[TBAA0]]
+; AVX512-NEXT:    [[TMP19:%.*]] = shufflevector <8 x float*> [[TMP10]], <8 x float*> undef, <8 x i32> zeroinitializer
+; AVX512-NEXT:    [[TMP20:%.*]] = getelementptr float, <8 x float*> [[TMP19]], <8 x i64> <i64 4, i64 13, i64 11, i64 44, i64 33, i64 30, i64 27, i64 23>
+; AVX512-NEXT:    [[TMP21:%.*]] = call <8 x float> @llvm.masked.gather.v8f32.v8p0f32(<8 x float*> [[TMP20]], i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x float> undef), [[TBAA0]]
+; AVX512-NEXT:    [[TMP22:%.*]] = fdiv <8 x float> [[TMP18]], [[TMP21]]
+; AVX512-NEXT:    [[TMP23:%.*]] = bitcast float* [[TMP0:%.*]] to <8 x float>*
+; AVX512-NEXT:    store <8 x float> [[TMP22]], <8 x float>* [[TMP23]], align 4, [[TBAA0]]
+; AVX512-NEXT:    ret void
+;
+  %3 = load float, float* %1, align 4, !tbaa !2
+  %4 = getelementptr inbounds float, float* %1, i64 4
+  %5 = load float, float* %4, align 4, !tbaa !2
+  %6 = fdiv float %3, %5
+  %7 = getelementptr inbounds float, float* %0, i64 1
+  store float %6, float* %0, align 4, !tbaa !2
+  %8 = getelementptr inbounds float, float* %1, i64 10
+  %9 = load float, float* %8, align 4, !tbaa !2
+  %10 = getelementptr inbounds float, float* %1, i64 13
+  %11 = load float, float* %10, align 4, !tbaa !2
+  %12 = fdiv float %9, %11
+  %13 = getelementptr inbounds float, float* %0, i64 2
+  store float %12, float* %7, align 4, !tbaa !2
+  %14 = getelementptr inbounds float, float* %1, i64 3
+  %15 = load float, float* %14, align 4, !tbaa !2
+  %16 = getelementptr inbounds float, float* %1, i64 11
+  %17 = load float, float* %16, align 4, !tbaa !2
+  %18 = fdiv float %15, %17
+  %19 = getelementptr inbounds float, float* %0, i64 3
+  store float %18, float* %13, align 4, !tbaa !2
+  %20 = getelementptr inbounds float, float* %1, i64 14
+  %21 = load float, float* %20, align 4, !tbaa !2
+  %22 = getelementptr inbounds float, float* %1, i64 44
+  %23 = load float, float* %22, align 4, !tbaa !2
+  %24 = fdiv float %21, %23
+  %25 = getelementptr inbounds float, float* %0, i64 4
+  store float %24, float* %19, align 4, !tbaa !2
+  %26 = getelementptr inbounds float, float* %1, i64 17
+  %27 = load float, float* %26, align 4, !tbaa !2
+  %28 = getelementptr inbounds float, float* %1, i64 33
+  %29 = load float, float* %28, align 4, !tbaa !2
+  %30 = fdiv float %27, %29
+  %31 = getelementptr inbounds float, float* %0, i64 5
+  store float %30, float* %25, align 4, !tbaa !2
+  %32 = getelementptr inbounds float, float* %1, i64 8
+  %33 = load float, float* %32, align 4, !tbaa !2
+  %34 = getelementptr inbounds float, float* %1, i64 30
+  %35 = load float, float* %34, align 4, !tbaa !2
+  %36 = fdiv float %33, %35
+  %37 = getelementptr inbounds float, float* %0, i64 6
+  store float %36, float* %31, align 4, !tbaa !2
+  %38 = getelementptr inbounds float, float* %1, i64 5
+  %39 = load float, float* %38, align 4, !tbaa !2
+  %40 = getelementptr inbounds float, float* %1, i64 27
+  %41 = load float, float* %40, align 4, !tbaa !2
+  %42 = fdiv float %39, %41
+  %43 = getelementptr inbounds float, float* %0, i64 7
+  store float %42, float* %37, align 4, !tbaa !2
+  %44 = getelementptr inbounds float, float* %1, i64 20
+  %45 = load float, float* %44, align 4, !tbaa !2
+  %46 = getelementptr inbounds float, float* %1, i64 23
+  %47 = load float, float* %46, align 4, !tbaa !2
+  %48 = fdiv float %45, %47
+  store float %48, float* %43, align 4, !tbaa !2
+  ret void
+}
+
+!2 = !{!3, !3, i64 0}
+!3 = !{!"short", !4, i64 0}
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!"Simple C++ TBAA"}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sext-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sext-inseltpoison.ll
new file mode 100644
index 0000000000000..d1690f4b3ac92
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sext-inseltpoison.ll
@@ -0,0 +1,1039 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=SSE,SSE2
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=SSE,SLM
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -mattr=+avx512bw -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
+
+;
+; vXi8
+;
+
+define <2 x i64> @loadext_2i8_to_2i64(i8* %p0) {
+; SSE-LABEL: @loadext_2i8_to_2i64(
+; SSE-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SSE-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SSE-NEXT:    [[X0:%.*]] = sext i8 [[I0]] to i64
+; SSE-NEXT:    [[X1:%.*]] = sext i8 [[I1]] to i64
+; SSE-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[X0]], i32 0
+; SSE-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[X1]], i32 1
+; SSE-NEXT:    ret <2 x i64> [[V1]]
+;
+; AVX-LABEL: @loadext_2i8_to_2i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <2 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <2 x i8>, <2 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <2 x i8> [[TMP2]] to <2 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    ret <2 x i64> [[V1]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %x0 = sext i8 %i0 to i64
+  %x1 = sext i8 %i1 to i64
+  %v0 = insertelement <2 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <2 x i64>   %v0, i64 %x1, i32 1
+  ret <2 x i64> %v1
+}
+
+define <4 x i32> @loadext_4i8_to_4i32(i8* %p0) {
+; SSE2-LABEL: @loadext_4i8_to_4i32(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <4 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i32>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[TMP7]], i32 3
+; SSE2-NEXT:    ret <4 x i32> [[V3]]
+;
+; SLM-LABEL: @loadext_4i8_to_4i32(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SLM-NEXT:    [[X0:%.*]] = sext i8 [[I0]] to i32
+; SLM-NEXT:    [[X1:%.*]] = sext i8 [[I1]] to i32
+; SLM-NEXT:    [[X2:%.*]] = sext i8 [[I2]] to i32
+; SLM-NEXT:    [[X3:%.*]] = sext i8 [[I3]] to i32
+; SLM-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[X3]], i32 3
+; SLM-NEXT:    ret <4 x i32> [[V3]]
+;
+; AVX-LABEL: @loadext_4i8_to_4i32(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <4 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i32>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i32> [[V3]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2 = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3 = getelementptr inbounds i8, i8* %p0, i64 3
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %i2 = load i8, i8* %p2, align 1
+  %i3 = load i8, i8* %p3, align 1
+  %x0 = sext i8 %i0 to i32
+  %x1 = sext i8 %i1 to i32
+  %x2 = sext i8 %i2 to i32
+  %x3 = sext i8 %i3 to i32
+  %v0 = insertelement <4 x i32> poison, i32 %x0, i32 0
+  %v1 = insertelement <4 x i32>   %v0, i32 %x1, i32 1
+  %v2 = insertelement <4 x i32>   %v1, i32 %x2, i32 2
+  %v3 = insertelement <4 x i32>   %v2, i32 %x3, i32 3
+  ret <4 x i32> %v3
+}
+
+define <4 x i64> @loadext_4i8_to_4i64(i8* %p0) {
+; SSE-LABEL: @loadext_4i8_to_4i64(
+; SSE-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SSE-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SSE-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SSE-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SSE-NEXT:    [[X0:%.*]] = sext i8 [[I0]] to i64
+; SSE-NEXT:    [[X1:%.*]] = sext i8 [[I1]] to i64
+; SSE-NEXT:    [[X2:%.*]] = sext i8 [[I2]] to i64
+; SSE-NEXT:    [[X3:%.*]] = sext i8 [[I3]] to i64
+; SSE-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[X0]], i32 0
+; SSE-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[X1]], i32 1
+; SSE-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[X2]], i32 2
+; SSE-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[X3]], i32 3
+; SSE-NEXT:    ret <4 x i64> [[V3]]
+;
+; AVX-LABEL: @loadext_4i8_to_4i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <4 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <4 x i8> [[TMP2]] to <4 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i64> [[V3]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2 = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3 = getelementptr inbounds i8, i8* %p0, i64 3
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %i2 = load i8, i8* %p2, align 1
+  %i3 = load i8, i8* %p3, align 1
+  %x0 = sext i8 %i0 to i64
+  %x1 = sext i8 %i1 to i64
+  %x2 = sext i8 %i2 to i64
+  %x3 = sext i8 %i3 to i64
+  %v0 = insertelement <4 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <4 x i64>   %v0, i64 %x1, i32 1
+  %v2 = insertelement <4 x i64>   %v1, i64 %x2, i32 2
+  %v3 = insertelement <4 x i64>   %v2, i64 %x3, i32 3
+  ret <4 x i64> %v3
+}
+
+define <8 x i16> @loadext_8i8_to_8i16(i8* %p0) {
+; SSE2-LABEL: @loadext_8i8_to_8i16(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE2-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SSE2-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SSE2-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SSE2-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <8 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = sext <8 x i8> [[TMP2]] to <8 x i16>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <8 x i16> [[V0]], i16 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <8 x i16> [[V1]], i16 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <8 x i16> [[V2]], i16 [[TMP7]], i32 3
+; SSE2-NEXT:    [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; SSE2-NEXT:    [[V4:%.*]] = insertelement <8 x i16> [[V3]], i16 [[TMP8]], i32 4
+; SSE2-NEXT:    [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; SSE2-NEXT:    [[V5:%.*]] = insertelement <8 x i16> [[V4]], i16 [[TMP9]], i32 5
+; SSE2-NEXT:    [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; SSE2-NEXT:    [[V6:%.*]] = insertelement <8 x i16> [[V5]], i16 [[TMP10]], i32 6
+; SSE2-NEXT:    [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; SSE2-NEXT:    [[V7:%.*]] = insertelement <8 x i16> [[V6]], i16 [[TMP11]], i32 7
+; SSE2-NEXT:    ret <8 x i16> [[V7]]
+;
+; SLM-LABEL: @loadext_8i8_to_8i16(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SLM-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SLM-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SLM-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SLM-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SLM-NEXT:    [[I4:%.*]] = load i8, i8* [[P4]], align 1
+; SLM-NEXT:    [[I5:%.*]] = load i8, i8* [[P5]], align 1
+; SLM-NEXT:    [[I6:%.*]] = load i8, i8* [[P6]], align 1
+; SLM-NEXT:    [[I7:%.*]] = load i8, i8* [[P7]], align 1
+; SLM-NEXT:    [[X0:%.*]] = sext i8 [[I0]] to i16
+; SLM-NEXT:    [[X1:%.*]] = sext i8 [[I1]] to i16
+; SLM-NEXT:    [[X2:%.*]] = sext i8 [[I2]] to i16
+; SLM-NEXT:    [[X3:%.*]] = sext i8 [[I3]] to i16
+; SLM-NEXT:    [[X4:%.*]] = sext i8 [[I4]] to i16
+; SLM-NEXT:    [[X5:%.*]] = sext i8 [[I5]] to i16
+; SLM-NEXT:    [[X6:%.*]] = sext i8 [[I6]] to i16
+; SLM-NEXT:    [[X7:%.*]] = sext i8 [[I7]] to i16
+; SLM-NEXT:    [[V0:%.*]] = insertelement <8 x i16> poison, i16 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <8 x i16> [[V0]], i16 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <8 x i16> [[V1]], i16 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <8 x i16> [[V2]], i16 [[X3]], i32 3
+; SLM-NEXT:    [[V4:%.*]] = insertelement <8 x i16> [[V3]], i16 [[X4]], i32 4
+; SLM-NEXT:    [[V5:%.*]] = insertelement <8 x i16> [[V4]], i16 [[X5]], i32 5
+; SLM-NEXT:    [[V6:%.*]] = insertelement <8 x i16> [[V5]], i16 [[X6]], i32 6
+; SLM-NEXT:    [[V7:%.*]] = insertelement <8 x i16> [[V6]], i16 [[X7]], i32 7
+; SLM-NEXT:    ret <8 x i16> [[V7]]
+;
+; AVX-LABEL: @loadext_8i8_to_8i16(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; AVX-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; AVX-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; AVX-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <8 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <8 x i8> [[TMP2]] to <8 x i16>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <8 x i16> [[V0]], i16 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <8 x i16> [[V1]], i16 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <8 x i16> [[V2]], i16 [[TMP7]], i32 3
+; AVX-NEXT:    [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; AVX-NEXT:    [[V4:%.*]] = insertelement <8 x i16> [[V3]], i16 [[TMP8]], i32 4
+; AVX-NEXT:    [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; AVX-NEXT:    [[V5:%.*]] = insertelement <8 x i16> [[V4]], i16 [[TMP9]], i32 5
+; AVX-NEXT:    [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; AVX-NEXT:    [[V6:%.*]] = insertelement <8 x i16> [[V5]], i16 [[TMP10]], i32 6
+; AVX-NEXT:    [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; AVX-NEXT:    [[V7:%.*]] = insertelement <8 x i16> [[V6]], i16 [[TMP11]], i32 7
+; AVX-NEXT:    ret <8 x i16> [[V7]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2 = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3 = getelementptr inbounds i8, i8* %p0, i64 3
+  %p4 = getelementptr inbounds i8, i8* %p0, i64 4
+  %p5 = getelementptr inbounds i8, i8* %p0, i64 5
+  %p6 = getelementptr inbounds i8, i8* %p0, i64 6
+  %p7 = getelementptr inbounds i8, i8* %p0, i64 7
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %i2 = load i8, i8* %p2, align 1
+  %i3 = load i8, i8* %p3, align 1
+  %i4 = load i8, i8* %p4, align 1
+  %i5 = load i8, i8* %p5, align 1
+  %i6 = load i8, i8* %p6, align 1
+  %i7 = load i8, i8* %p7, align 1
+  %x0 = sext i8 %i0 to i16
+  %x1 = sext i8 %i1 to i16
+  %x2 = sext i8 %i2 to i16
+  %x3 = sext i8 %i3 to i16
+  %x4 = sext i8 %i4 to i16
+  %x5 = sext i8 %i5 to i16
+  %x6 = sext i8 %i6 to i16
+  %x7 = sext i8 %i7 to i16
+  %v0 = insertelement <8 x i16> poison, i16 %x0, i32 0
+  %v1 = insertelement <8 x i16>   %v0, i16 %x1, i32 1
+  %v2 = insertelement <8 x i16>   %v1, i16 %x2, i32 2
+  %v3 = insertelement <8 x i16>   %v2, i16 %x3, i32 3
+  %v4 = insertelement <8 x i16>   %v3, i16 %x4, i32 4
+  %v5 = insertelement <8 x i16>   %v4, i16 %x5, i32 5
+  %v6 = insertelement <8 x i16>   %v5, i16 %x6, i32 6
+  %v7 = insertelement <8 x i16>   %v6, i16 %x7, i32 7
+  ret <8 x i16> %v7
+}
+
+define <8 x i32> @loadext_8i8_to_8i32(i8* %p0) {
+; SSE2-LABEL: @loadext_8i8_to_8i32(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE2-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SSE2-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SSE2-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SSE2-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <8 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = sext <8 x i8> [[TMP2]] to <8 x i32>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <8 x i32> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <8 x i32> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[TMP7]], i32 3
+; SSE2-NEXT:    [[TMP8:%.*]] = extractelement <8 x i32> [[TMP3]], i32 4
+; SSE2-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[TMP8]], i32 4
+; SSE2-NEXT:    [[TMP9:%.*]] = extractelement <8 x i32> [[TMP3]], i32 5
+; SSE2-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[TMP9]], i32 5
+; SSE2-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP3]], i32 6
+; SSE2-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[TMP10]], i32 6
+; SSE2-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP3]], i32 7
+; SSE2-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[TMP11]], i32 7
+; SSE2-NEXT:    ret <8 x i32> [[V7]]
+;
+; SLM-LABEL: @loadext_8i8_to_8i32(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SLM-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SLM-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SLM-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SLM-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SLM-NEXT:    [[I4:%.*]] = load i8, i8* [[P4]], align 1
+; SLM-NEXT:    [[I5:%.*]] = load i8, i8* [[P5]], align 1
+; SLM-NEXT:    [[I6:%.*]] = load i8, i8* [[P6]], align 1
+; SLM-NEXT:    [[I7:%.*]] = load i8, i8* [[P7]], align 1
+; SLM-NEXT:    [[X0:%.*]] = sext i8 [[I0]] to i32
+; SLM-NEXT:    [[X1:%.*]] = sext i8 [[I1]] to i32
+; SLM-NEXT:    [[X2:%.*]] = sext i8 [[I2]] to i32
+; SLM-NEXT:    [[X3:%.*]] = sext i8 [[I3]] to i32
+; SLM-NEXT:    [[X4:%.*]] = sext i8 [[I4]] to i32
+; SLM-NEXT:    [[X5:%.*]] = sext i8 [[I5]] to i32
+; SLM-NEXT:    [[X6:%.*]] = sext i8 [[I6]] to i32
+; SLM-NEXT:    [[X7:%.*]] = sext i8 [[I7]] to i32
+; SLM-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[X3]], i32 3
+; SLM-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[X4]], i32 4
+; SLM-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[X5]], i32 5
+; SLM-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[X6]], i32 6
+; SLM-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[X7]], i32 7
+; SLM-NEXT:    ret <8 x i32> [[V7]]
+;
+; AVX-LABEL: @loadext_8i8_to_8i32(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; AVX-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; AVX-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; AVX-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <8 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <8 x i8> [[TMP2]] to <8 x i32>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <8 x i32> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <8 x i32> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[TMP7]], i32 3
+; AVX-NEXT:    [[TMP8:%.*]] = extractelement <8 x i32> [[TMP3]], i32 4
+; AVX-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[TMP8]], i32 4
+; AVX-NEXT:    [[TMP9:%.*]] = extractelement <8 x i32> [[TMP3]], i32 5
+; AVX-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[TMP9]], i32 5
+; AVX-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP3]], i32 6
+; AVX-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[TMP10]], i32 6
+; AVX-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP3]], i32 7
+; AVX-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[TMP11]], i32 7
+; AVX-NEXT:    ret <8 x i32> [[V7]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2 = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3 = getelementptr inbounds i8, i8* %p0, i64 3
+  %p4 = getelementptr inbounds i8, i8* %p0, i64 4
+  %p5 = getelementptr inbounds i8, i8* %p0, i64 5
+  %p6 = getelementptr inbounds i8, i8* %p0, i64 6
+  %p7 = getelementptr inbounds i8, i8* %p0, i64 7
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %i2 = load i8, i8* %p2, align 1
+  %i3 = load i8, i8* %p3, align 1
+  %i4 = load i8, i8* %p4, align 1
+  %i5 = load i8, i8* %p5, align 1
+  %i6 = load i8, i8* %p6, align 1
+  %i7 = load i8, i8* %p7, align 1
+  %x0 = sext i8 %i0 to i32
+  %x1 = sext i8 %i1 to i32
+  %x2 = sext i8 %i2 to i32
+  %x3 = sext i8 %i3 to i32
+  %x4 = sext i8 %i4 to i32
+  %x5 = sext i8 %i5 to i32
+  %x6 = sext i8 %i6 to i32
+  %x7 = sext i8 %i7 to i32
+  %v0 = insertelement <8 x i32> poison, i32 %x0, i32 0
+  %v1 = insertelement <8 x i32>   %v0, i32 %x1, i32 1
+  %v2 = insertelement <8 x i32>   %v1, i32 %x2, i32 2
+  %v3 = insertelement <8 x i32>   %v2, i32 %x3, i32 3
+  %v4 = insertelement <8 x i32>   %v3, i32 %x4, i32 4
+  %v5 = insertelement <8 x i32>   %v4, i32 %x5, i32 5
+  %v6 = insertelement <8 x i32>   %v5, i32 %x6, i32 6
+  %v7 = insertelement <8 x i32>   %v6, i32 %x7, i32 7
+  ret <8 x i32> %v7
+}
+
+define <16 x i16> @loadext_16i8_to_16i16(i8* %p0) {
+; SSE2-LABEL: @loadext_16i8_to_16i16(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE2-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SSE2-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SSE2-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SSE2-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SSE2-NEXT:    [[P8:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 8
+; SSE2-NEXT:    [[P9:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 9
+; SSE2-NEXT:    [[P10:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 10
+; SSE2-NEXT:    [[P11:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 11
+; SSE2-NEXT:    [[P12:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 12
+; SSE2-NEXT:    [[P13:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 13
+; SSE2-NEXT:    [[P14:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 14
+; SSE2-NEXT:    [[P15:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 15
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <16 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = sext <16 x i8> [[TMP2]] to <16 x i16>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <16 x i16> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <16 x i16> poison, i16 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <16 x i16> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <16 x i16> [[V0]], i16 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <16 x i16> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <16 x i16> [[V1]], i16 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <16 x i16> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <16 x i16> [[V2]], i16 [[TMP7]], i32 3
+; SSE2-NEXT:    [[TMP8:%.*]] = extractelement <16 x i16> [[TMP3]], i32 4
+; SSE2-NEXT:    [[V4:%.*]] = insertelement <16 x i16> [[V3]], i16 [[TMP8]], i32 4
+; SSE2-NEXT:    [[TMP9:%.*]] = extractelement <16 x i16> [[TMP3]], i32 5
+; SSE2-NEXT:    [[V5:%.*]] = insertelement <16 x i16> [[V4]], i16 [[TMP9]], i32 5
+; SSE2-NEXT:    [[TMP10:%.*]] = extractelement <16 x i16> [[TMP3]], i32 6
+; SSE2-NEXT:    [[V6:%.*]] = insertelement <16 x i16> [[V5]], i16 [[TMP10]], i32 6
+; SSE2-NEXT:    [[TMP11:%.*]] = extractelement <16 x i16> [[TMP3]], i32 7
+; SSE2-NEXT:    [[V7:%.*]] = insertelement <16 x i16> [[V6]], i16 [[TMP11]], i32 7
+; SSE2-NEXT:    [[TMP12:%.*]] = extractelement <16 x i16> [[TMP3]], i32 8
+; SSE2-NEXT:    [[V8:%.*]] = insertelement <16 x i16> [[V7]], i16 [[TMP12]], i32 8
+; SSE2-NEXT:    [[TMP13:%.*]] = extractelement <16 x i16> [[TMP3]], i32 9
+; SSE2-NEXT:    [[V9:%.*]] = insertelement <16 x i16> [[V8]], i16 [[TMP13]], i32 9
+; SSE2-NEXT:    [[TMP14:%.*]] = extractelement <16 x i16> [[TMP3]], i32 10
+; SSE2-NEXT:    [[V10:%.*]] = insertelement <16 x i16> [[V9]], i16 [[TMP14]], i32 10
+; SSE2-NEXT:    [[TMP15:%.*]] = extractelement <16 x i16> [[TMP3]], i32 11
+; SSE2-NEXT:    [[V11:%.*]] = insertelement <16 x i16> [[V10]], i16 [[TMP15]], i32 11
+; SSE2-NEXT:    [[TMP16:%.*]] = extractelement <16 x i16> [[TMP3]], i32 12
+; SSE2-NEXT:    [[V12:%.*]] = insertelement <16 x i16> [[V11]], i16 [[TMP16]], i32 12
+; SSE2-NEXT:    [[TMP17:%.*]] = extractelement <16 x i16> [[TMP3]], i32 13
+; SSE2-NEXT:    [[V13:%.*]] = insertelement <16 x i16> [[V12]], i16 [[TMP17]], i32 13
+; SSE2-NEXT:    [[TMP18:%.*]] = extractelement <16 x i16> [[TMP3]], i32 14
+; SSE2-NEXT:    [[V14:%.*]] = insertelement <16 x i16> [[V13]], i16 [[TMP18]], i32 14
+; SSE2-NEXT:    [[TMP19:%.*]] = extractelement <16 x i16> [[TMP3]], i32 15
+; SSE2-NEXT:    [[V15:%.*]] = insertelement <16 x i16> [[V14]], i16 [[TMP19]], i32 15
+; SSE2-NEXT:    ret <16 x i16> [[V15]]
+;
+; SLM-LABEL: @loadext_16i8_to_16i16(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SLM-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SLM-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SLM-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SLM-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SLM-NEXT:    [[P8:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 8
+; SLM-NEXT:    [[P9:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 9
+; SLM-NEXT:    [[P10:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 10
+; SLM-NEXT:    [[P11:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 11
+; SLM-NEXT:    [[P12:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 12
+; SLM-NEXT:    [[P13:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 13
+; SLM-NEXT:    [[P14:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 14
+; SLM-NEXT:    [[P15:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 15
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SLM-NEXT:    [[I4:%.*]] = load i8, i8* [[P4]], align 1
+; SLM-NEXT:    [[I5:%.*]] = load i8, i8* [[P5]], align 1
+; SLM-NEXT:    [[I6:%.*]] = load i8, i8* [[P6]], align 1
+; SLM-NEXT:    [[I7:%.*]] = load i8, i8* [[P7]], align 1
+; SLM-NEXT:    [[I8:%.*]] = load i8, i8* [[P8]], align 1
+; SLM-NEXT:    [[I9:%.*]] = load i8, i8* [[P9]], align 1
+; SLM-NEXT:    [[I10:%.*]] = load i8, i8* [[P10]], align 1
+; SLM-NEXT:    [[I11:%.*]] = load i8, i8* [[P11]], align 1
+; SLM-NEXT:    [[I12:%.*]] = load i8, i8* [[P12]], align 1
+; SLM-NEXT:    [[I13:%.*]] = load i8, i8* [[P13]], align 1
+; SLM-NEXT:    [[I14:%.*]] = load i8, i8* [[P14]], align 1
+; SLM-NEXT:    [[I15:%.*]] = load i8, i8* [[P15]], align 1
+; SLM-NEXT:    [[X0:%.*]] = sext i8 [[I0]] to i16
+; SLM-NEXT:    [[X1:%.*]] = sext i8 [[I1]] to i16
+; SLM-NEXT:    [[X2:%.*]] = sext i8 [[I2]] to i16
+; SLM-NEXT:    [[X3:%.*]] = sext i8 [[I3]] to i16
+; SLM-NEXT:    [[X4:%.*]] = sext i8 [[I4]] to i16
+; SLM-NEXT:    [[X5:%.*]] = sext i8 [[I5]] to i16
+; SLM-NEXT:    [[X6:%.*]] = sext i8 [[I6]] to i16
+; SLM-NEXT:    [[X7:%.*]] = sext i8 [[I7]] to i16
+; SLM-NEXT:    [[X8:%.*]] = sext i8 [[I8]] to i16
+; SLM-NEXT:    [[X9:%.*]] = sext i8 [[I9]] to i16
+; SLM-NEXT:    [[X10:%.*]] = sext i8 [[I10]] to i16
+; SLM-NEXT:    [[X11:%.*]] = sext i8 [[I11]] to i16
+; SLM-NEXT:    [[X12:%.*]] = sext i8 [[I12]] to i16
+; SLM-NEXT:    [[X13:%.*]] = sext i8 [[I13]] to i16
+; SLM-NEXT:    [[X14:%.*]] = sext i8 [[I14]] to i16
+; SLM-NEXT:    [[X15:%.*]] = sext i8 [[I15]] to i16
+; SLM-NEXT:    [[V0:%.*]] = insertelement <16 x i16> poison, i16 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <16 x i16> [[V0]], i16 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <16 x i16> [[V1]], i16 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <16 x i16> [[V2]], i16 [[X3]], i32 3
+; SLM-NEXT:    [[V4:%.*]] = insertelement <16 x i16> [[V3]], i16 [[X4]], i32 4
+; SLM-NEXT:    [[V5:%.*]] = insertelement <16 x i16> [[V4]], i16 [[X5]], i32 5
+; SLM-NEXT:    [[V6:%.*]] = insertelement <16 x i16> [[V5]], i16 [[X6]], i32 6
+; SLM-NEXT:    [[V7:%.*]] = insertelement <16 x i16> [[V6]], i16 [[X7]], i32 7
+; SLM-NEXT:    [[V8:%.*]] = insertelement <16 x i16> [[V7]], i16 [[X8]], i32 8
+; SLM-NEXT:    [[V9:%.*]] = insertelement <16 x i16> [[V8]], i16 [[X9]], i32 9
+; SLM-NEXT:    [[V10:%.*]] = insertelement <16 x i16> [[V9]], i16 [[X10]], i32 10
+; SLM-NEXT:    [[V11:%.*]] = insertelement <16 x i16> [[V10]], i16 [[X11]], i32 11
+; SLM-NEXT:    [[V12:%.*]] = insertelement <16 x i16> [[V11]], i16 [[X12]], i32 12
+; SLM-NEXT:    [[V13:%.*]] = insertelement <16 x i16> [[V12]], i16 [[X13]], i32 13
+; SLM-NEXT:    [[V14:%.*]] = insertelement <16 x i16> [[V13]], i16 [[X14]], i32 14
+; SLM-NEXT:    [[V15:%.*]] = insertelement <16 x i16> [[V14]], i16 [[X15]], i32 15
+; SLM-NEXT:    ret <16 x i16> [[V15]]
+;
+; AVX-LABEL: @loadext_16i8_to_16i16(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; AVX-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; AVX-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; AVX-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; AVX-NEXT:    [[P8:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 8
+; AVX-NEXT:    [[P9:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 9
+; AVX-NEXT:    [[P10:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 10
+; AVX-NEXT:    [[P11:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 11
+; AVX-NEXT:    [[P12:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 12
+; AVX-NEXT:    [[P13:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 13
+; AVX-NEXT:    [[P14:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 14
+; AVX-NEXT:    [[P15:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 15
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <16 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <16 x i8> [[TMP2]] to <16 x i16>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <16 x i16> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <16 x i16> poison, i16 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <16 x i16> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <16 x i16> [[V0]], i16 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <16 x i16> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <16 x i16> [[V1]], i16 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <16 x i16> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <16 x i16> [[V2]], i16 [[TMP7]], i32 3
+; AVX-NEXT:    [[TMP8:%.*]] = extractelement <16 x i16> [[TMP3]], i32 4
+; AVX-NEXT:    [[V4:%.*]] = insertelement <16 x i16> [[V3]], i16 [[TMP8]], i32 4
+; AVX-NEXT:    [[TMP9:%.*]] = extractelement <16 x i16> [[TMP3]], i32 5
+; AVX-NEXT:    [[V5:%.*]] = insertelement <16 x i16> [[V4]], i16 [[TMP9]], i32 5
+; AVX-NEXT:    [[TMP10:%.*]] = extractelement <16 x i16> [[TMP3]], i32 6
+; AVX-NEXT:    [[V6:%.*]] = insertelement <16 x i16> [[V5]], i16 [[TMP10]], i32 6
+; AVX-NEXT:    [[TMP11:%.*]] = extractelement <16 x i16> [[TMP3]], i32 7
+; AVX-NEXT:    [[V7:%.*]] = insertelement <16 x i16> [[V6]], i16 [[TMP11]], i32 7
+; AVX-NEXT:    [[TMP12:%.*]] = extractelement <16 x i16> [[TMP3]], i32 8
+; AVX-NEXT:    [[V8:%.*]] = insertelement <16 x i16> [[V7]], i16 [[TMP12]], i32 8
+; AVX-NEXT:    [[TMP13:%.*]] = extractelement <16 x i16> [[TMP3]], i32 9
+; AVX-NEXT:    [[V9:%.*]] = insertelement <16 x i16> [[V8]], i16 [[TMP13]], i32 9
+; AVX-NEXT:    [[TMP14:%.*]] = extractelement <16 x i16> [[TMP3]], i32 10
+; AVX-NEXT:    [[V10:%.*]] = insertelement <16 x i16> [[V9]], i16 [[TMP14]], i32 10
+; AVX-NEXT:    [[TMP15:%.*]] = extractelement <16 x i16> [[TMP3]], i32 11
+; AVX-NEXT:    [[V11:%.*]] = insertelement <16 x i16> [[V10]], i16 [[TMP15]], i32 11
+; AVX-NEXT:    [[TMP16:%.*]] = extractelement <16 x i16> [[TMP3]], i32 12
+; AVX-NEXT:    [[V12:%.*]] = insertelement <16 x i16> [[V11]], i16 [[TMP16]], i32 12
+; AVX-NEXT:    [[TMP17:%.*]] = extractelement <16 x i16> [[TMP3]], i32 13
+; AVX-NEXT:    [[V13:%.*]] = insertelement <16 x i16> [[V12]], i16 [[TMP17]], i32 13
+; AVX-NEXT:    [[TMP18:%.*]] = extractelement <16 x i16> [[TMP3]], i32 14
+; AVX-NEXT:    [[V14:%.*]] = insertelement <16 x i16> [[V13]], i16 [[TMP18]], i32 14
+; AVX-NEXT:    [[TMP19:%.*]] = extractelement <16 x i16> [[TMP3]], i32 15
+; AVX-NEXT:    [[V15:%.*]] = insertelement <16 x i16> [[V14]], i16 [[TMP19]], i32 15
+; AVX-NEXT:    ret <16 x i16> [[V15]]
+;
+  %p1  = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2  = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3  = getelementptr inbounds i8, i8* %p0, i64 3
+  %p4  = getelementptr inbounds i8, i8* %p0, i64 4
+  %p5  = getelementptr inbounds i8, i8* %p0, i64 5
+  %p6  = getelementptr inbounds i8, i8* %p0, i64 6
+  %p7  = getelementptr inbounds i8, i8* %p0, i64 7
+  %p8  = getelementptr inbounds i8, i8* %p0, i64 8
+  %p9  = getelementptr inbounds i8, i8* %p0, i64 9
+  %p10 = getelementptr inbounds i8, i8* %p0, i64 10
+  %p11 = getelementptr inbounds i8, i8* %p0, i64 11
+  %p12 = getelementptr inbounds i8, i8* %p0, i64 12
+  %p13 = getelementptr inbounds i8, i8* %p0, i64 13
+  %p14 = getelementptr inbounds i8, i8* %p0, i64 14
+  %p15 = getelementptr inbounds i8, i8* %p0, i64 15
+  %i0  = load i8, i8* %p0,  align 1
+  %i1  = load i8, i8* %p1,  align 1
+  %i2  = load i8, i8* %p2,  align 1
+  %i3  = load i8, i8* %p3,  align 1
+  %i4  = load i8, i8* %p4,  align 1
+  %i5  = load i8, i8* %p5,  align 1
+  %i6  = load i8, i8* %p6,  align 1
+  %i7  = load i8, i8* %p7,  align 1
+  %i8  = load i8, i8* %p8,  align 1
+  %i9  = load i8, i8* %p9,  align 1
+  %i10 = load i8, i8* %p10, align 1
+  %i11 = load i8, i8* %p11, align 1
+  %i12 = load i8, i8* %p12, align 1
+  %i13 = load i8, i8* %p13, align 1
+  %i14 = load i8, i8* %p14, align 1
+  %i15 = load i8, i8* %p15, align 1
+  %x0  = sext i8 %i0  to i16
+  %x1  = sext i8 %i1  to i16
+  %x2  = sext i8 %i2  to i16
+  %x3  = sext i8 %i3  to i16
+  %x4  = sext i8 %i4  to i16
+  %x5  = sext i8 %i5  to i16
+  %x6  = sext i8 %i6  to i16
+  %x7  = sext i8 %i7  to i16
+  %x8  = sext i8 %i8  to i16
+  %x9  = sext i8 %i9  to i16
+  %x10 = sext i8 %i10 to i16
+  %x11 = sext i8 %i11 to i16
+  %x12 = sext i8 %i12 to i16
+  %x13 = sext i8 %i13 to i16
+  %x14 = sext i8 %i14 to i16
+  %x15 = sext i8 %i15 to i16
+  %v0  = insertelement <16 x i16> poison, i16 %x0,  i32 0
+  %v1  = insertelement <16 x i16>  %v0,  i16 %x1,  i32 1
+  %v2  = insertelement <16 x i16>  %v1,  i16 %x2,  i32 2
+  %v3  = insertelement <16 x i16>  %v2,  i16 %x3,  i32 3
+  %v4  = insertelement <16 x i16>  %v3,  i16 %x4,  i32 4
+  %v5  = insertelement <16 x i16>  %v4,  i16 %x5,  i32 5
+  %v6  = insertelement <16 x i16>  %v5,  i16 %x6,  i32 6
+  %v7  = insertelement <16 x i16>  %v6,  i16 %x7,  i32 7
+  %v8  = insertelement <16 x i16>  %v7,  i16 %x8,  i32 8
+  %v9  = insertelement <16 x i16>  %v8,  i16 %x9,  i32 9
+  %v10 = insertelement <16 x i16>  %v9,  i16 %x10, i32 10
+  %v11 = insertelement <16 x i16>  %v10, i16 %x11, i32 11
+  %v12 = insertelement <16 x i16>  %v11, i16 %x12, i32 12
+  %v13 = insertelement <16 x i16>  %v12, i16 %x13, i32 13
+  %v14 = insertelement <16 x i16>  %v13, i16 %x14, i32 14
+  %v15 = insertelement <16 x i16>  %v14, i16 %x15, i32 15
+  ret <16 x i16> %v15
+}
+
+;
+; vXi16
+;
+
+define <2 x i64> @loadext_2i16_to_2i64(i16* %p0) {
+; SSE-LABEL: @loadext_2i16_to_2i64(
+; SSE-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SSE-NEXT:    [[I0:%.*]] = load i16, i16* [[P0]], align 1
+; SSE-NEXT:    [[I1:%.*]] = load i16, i16* [[P1]], align 1
+; SSE-NEXT:    [[X0:%.*]] = sext i16 [[I0]] to i64
+; SSE-NEXT:    [[X1:%.*]] = sext i16 [[I1]] to i64
+; SSE-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[X0]], i32 0
+; SSE-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[X1]], i32 1
+; SSE-NEXT:    ret <2 x i64> [[V1]]
+;
+; AVX-LABEL: @loadext_2i16_to_2i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <2 x i16>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <2 x i16>, <2 x i16>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <2 x i16> [[TMP2]] to <2 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    ret <2 x i64> [[V1]]
+;
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  %i0 = load i16, i16* %p0, align 1
+  %i1 = load i16, i16* %p1, align 1
+  %x0 = sext i16 %i0 to i64
+  %x1 = sext i16 %i1 to i64
+  %v0 = insertelement <2 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <2 x i64>   %v0, i64 %x1, i32 1
+  ret <2 x i64> %v1
+}
+
+define <4 x i32> @loadext_4i16_to_4i32(i16* %p0) {
+; SSE2-LABEL: @loadext_4i16_to_4i32(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <4 x i16>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = sext <4 x i16> [[TMP2]] to <4 x i32>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[TMP7]], i32 3
+; SSE2-NEXT:    ret <4 x i32> [[V3]]
+;
+; SLM-LABEL: @loadext_4i16_to_4i32(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SLM-NEXT:    [[I0:%.*]] = load i16, i16* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i16, i16* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i16, i16* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i16, i16* [[P3]], align 1
+; SLM-NEXT:    [[X0:%.*]] = sext i16 [[I0]] to i32
+; SLM-NEXT:    [[X1:%.*]] = sext i16 [[I1]] to i32
+; SLM-NEXT:    [[X2:%.*]] = sext i16 [[I2]] to i32
+; SLM-NEXT:    [[X3:%.*]] = sext i16 [[I3]] to i32
+; SLM-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[X3]], i32 3
+; SLM-NEXT:    ret <4 x i32> [[V3]]
+;
+; AVX-LABEL: @loadext_4i16_to_4i32(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <4 x i16>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <4 x i16> [[TMP2]] to <4 x i32>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i32> [[V3]]
+;
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  %p2 = getelementptr inbounds i16, i16* %p0, i64 2
+  %p3 = getelementptr inbounds i16, i16* %p0, i64 3
+  %i0 = load i16, i16* %p0, align 1
+  %i1 = load i16, i16* %p1, align 1
+  %i2 = load i16, i16* %p2, align 1
+  %i3 = load i16, i16* %p3, align 1
+  %x0 = sext i16 %i0 to i32
+  %x1 = sext i16 %i1 to i32
+  %x2 = sext i16 %i2 to i32
+  %x3 = sext i16 %i3 to i32
+  %v0 = insertelement <4 x i32> poison, i32 %x0, i32 0
+  %v1 = insertelement <4 x i32>   %v0, i32 %x1, i32 1
+  %v2 = insertelement <4 x i32>   %v1, i32 %x2, i32 2
+  %v3 = insertelement <4 x i32>   %v2, i32 %x3, i32 3
+  ret <4 x i32> %v3
+}
+
+define <4 x i64> @loadext_4i16_to_4i64(i16* %p0) {
+; SSE-LABEL: @loadext_4i16_to_4i64(
+; SSE-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SSE-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SSE-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SSE-NEXT:    [[I0:%.*]] = load i16, i16* [[P0]], align 1
+; SSE-NEXT:    [[I1:%.*]] = load i16, i16* [[P1]], align 1
+; SSE-NEXT:    [[I2:%.*]] = load i16, i16* [[P2]], align 1
+; SSE-NEXT:    [[I3:%.*]] = load i16, i16* [[P3]], align 1
+; SSE-NEXT:    [[X0:%.*]] = sext i16 [[I0]] to i64
+; SSE-NEXT:    [[X1:%.*]] = sext i16 [[I1]] to i64
+; SSE-NEXT:    [[X2:%.*]] = sext i16 [[I2]] to i64
+; SSE-NEXT:    [[X3:%.*]] = sext i16 [[I3]] to i64
+; SSE-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[X0]], i32 0
+; SSE-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[X1]], i32 1
+; SSE-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[X2]], i32 2
+; SSE-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[X3]], i32 3
+; SSE-NEXT:    ret <4 x i64> [[V3]]
+;
+; AVX-LABEL: @loadext_4i16_to_4i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <4 x i16>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <4 x i16> [[TMP2]] to <4 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i64> [[V3]]
+;
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  %p2 = getelementptr inbounds i16, i16* %p0, i64 2
+  %p3 = getelementptr inbounds i16, i16* %p0, i64 3
+  %i0 = load i16, i16* %p0, align 1
+  %i1 = load i16, i16* %p1, align 1
+  %i2 = load i16, i16* %p2, align 1
+  %i3 = load i16, i16* %p3, align 1
+  %x0 = sext i16 %i0 to i64
+  %x1 = sext i16 %i1 to i64
+  %x2 = sext i16 %i2 to i64
+  %x3 = sext i16 %i3 to i64
+  %v0 = insertelement <4 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <4 x i64>   %v0, i64 %x1, i32 1
+  %v2 = insertelement <4 x i64>   %v1, i64 %x2, i32 2
+  %v3 = insertelement <4 x i64>   %v2, i64 %x3, i32 3
+  ret <4 x i64> %v3
+}
+
+define <8 x i32> @loadext_8i16_to_8i32(i16* %p0) {
+; SSE2-LABEL: @loadext_8i16_to_8i32(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SSE2-NEXT:    [[P4:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 4
+; SSE2-NEXT:    [[P5:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 5
+; SSE2-NEXT:    [[P6:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 6
+; SSE2-NEXT:    [[P7:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 7
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <8 x i16>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = sext <8 x i16> [[TMP2]] to <8 x i32>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <8 x i32> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <8 x i32> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[TMP7]], i32 3
+; SSE2-NEXT:    [[TMP8:%.*]] = extractelement <8 x i32> [[TMP3]], i32 4
+; SSE2-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[TMP8]], i32 4
+; SSE2-NEXT:    [[TMP9:%.*]] = extractelement <8 x i32> [[TMP3]], i32 5
+; SSE2-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[TMP9]], i32 5
+; SSE2-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP3]], i32 6
+; SSE2-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[TMP10]], i32 6
+; SSE2-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP3]], i32 7
+; SSE2-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[TMP11]], i32 7
+; SSE2-NEXT:    ret <8 x i32> [[V7]]
+;
+; SLM-LABEL: @loadext_8i16_to_8i32(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SLM-NEXT:    [[P4:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 4
+; SLM-NEXT:    [[P5:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 5
+; SLM-NEXT:    [[P6:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 6
+; SLM-NEXT:    [[P7:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 7
+; SLM-NEXT:    [[I0:%.*]] = load i16, i16* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i16, i16* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i16, i16* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i16, i16* [[P3]], align 1
+; SLM-NEXT:    [[I4:%.*]] = load i16, i16* [[P4]], align 1
+; SLM-NEXT:    [[I5:%.*]] = load i16, i16* [[P5]], align 1
+; SLM-NEXT:    [[I6:%.*]] = load i16, i16* [[P6]], align 1
+; SLM-NEXT:    [[I7:%.*]] = load i16, i16* [[P7]], align 1
+; SLM-NEXT:    [[X0:%.*]] = sext i16 [[I0]] to i32
+; SLM-NEXT:    [[X1:%.*]] = sext i16 [[I1]] to i32
+; SLM-NEXT:    [[X2:%.*]] = sext i16 [[I2]] to i32
+; SLM-NEXT:    [[X3:%.*]] = sext i16 [[I3]] to i32
+; SLM-NEXT:    [[X4:%.*]] = sext i16 [[I4]] to i32
+; SLM-NEXT:    [[X5:%.*]] = sext i16 [[I5]] to i32
+; SLM-NEXT:    [[X6:%.*]] = sext i16 [[I6]] to i32
+; SLM-NEXT:    [[X7:%.*]] = sext i16 [[I7]] to i32
+; SLM-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[X3]], i32 3
+; SLM-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[X4]], i32 4
+; SLM-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[X5]], i32 5
+; SLM-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[X6]], i32 6
+; SLM-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[X7]], i32 7
+; SLM-NEXT:    ret <8 x i32> [[V7]]
+;
+; AVX-LABEL: @loadext_8i16_to_8i32(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; AVX-NEXT:    [[P4:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 4
+; AVX-NEXT:    [[P5:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 5
+; AVX-NEXT:    [[P6:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 6
+; AVX-NEXT:    [[P7:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 7
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <8 x i16>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <8 x i16> [[TMP2]] to <8 x i32>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <8 x i32> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <8 x i32> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[TMP7]], i32 3
+; AVX-NEXT:    [[TMP8:%.*]] = extractelement <8 x i32> [[TMP3]], i32 4
+; AVX-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[TMP8]], i32 4
+; AVX-NEXT:    [[TMP9:%.*]] = extractelement <8 x i32> [[TMP3]], i32 5
+; AVX-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[TMP9]], i32 5
+; AVX-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP3]], i32 6
+; AVX-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[TMP10]], i32 6
+; AVX-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP3]], i32 7
+; AVX-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[TMP11]], i32 7
+; AVX-NEXT:    ret <8 x i32> [[V7]]
+;
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  %p2 = getelementptr inbounds i16, i16* %p0, i64 2
+  %p3 = getelementptr inbounds i16, i16* %p0, i64 3
+  %p4 = getelementptr inbounds i16, i16* %p0, i64 4
+  %p5 = getelementptr inbounds i16, i16* %p0, i64 5
+  %p6 = getelementptr inbounds i16, i16* %p0, i64 6
+  %p7 = getelementptr inbounds i16, i16* %p0, i64 7
+  %i0 = load i16, i16* %p0, align 1
+  %i1 = load i16, i16* %p1, align 1
+  %i2 = load i16, i16* %p2, align 1
+  %i3 = load i16, i16* %p3, align 1
+  %i4 = load i16, i16* %p4, align 1
+  %i5 = load i16, i16* %p5, align 1
+  %i6 = load i16, i16* %p6, align 1
+  %i7 = load i16, i16* %p7, align 1
+  %x0 = sext i16 %i0 to i32
+  %x1 = sext i16 %i1 to i32
+  %x2 = sext i16 %i2 to i32
+  %x3 = sext i16 %i3 to i32
+  %x4 = sext i16 %i4 to i32
+  %x5 = sext i16 %i5 to i32
+  %x6 = sext i16 %i6 to i32
+  %x7 = sext i16 %i7 to i32
+  %v0 = insertelement <8 x i32> poison, i32 %x0, i32 0
+  %v1 = insertelement <8 x i32>   %v0, i32 %x1, i32 1
+  %v2 = insertelement <8 x i32>   %v1, i32 %x2, i32 2
+  %v3 = insertelement <8 x i32>   %v2, i32 %x3, i32 3
+  %v4 = insertelement <8 x i32>   %v3, i32 %x4, i32 4
+  %v5 = insertelement <8 x i32>   %v4, i32 %x5, i32 5
+  %v6 = insertelement <8 x i32>   %v5, i32 %x6, i32 6
+  %v7 = insertelement <8 x i32>   %v6, i32 %x7, i32 7
+  ret <8 x i32> %v7
+}
+
+;
+; vXi32
+;
+
+define <2 x i64> @loadext_2i32_to_2i64(i32* %p0) {
+; SSE-LABEL: @loadext_2i32_to_2i64(
+; SSE-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; SSE-NEXT:    [[I0:%.*]] = load i32, i32* [[P0]], align 1
+; SSE-NEXT:    [[I1:%.*]] = load i32, i32* [[P1]], align 1
+; SSE-NEXT:    [[X0:%.*]] = sext i32 [[I0]] to i64
+; SSE-NEXT:    [[X1:%.*]] = sext i32 [[I1]] to i64
+; SSE-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[X0]], i32 0
+; SSE-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[X1]], i32 1
+; SSE-NEXT:    ret <2 x i64> [[V1]]
+;
+; AVX-LABEL: @loadext_2i32_to_2i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i32* [[P0]] to <2 x i32>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <2 x i32>, <2 x i32>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <2 x i32> [[TMP2]] to <2 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    ret <2 x i64> [[V1]]
+;
+  %p1 = getelementptr inbounds i32, i32* %p0, i64 1
+  %i0 = load i32, i32* %p0, align 1
+  %i1 = load i32, i32* %p1, align 1
+  %x0 = sext i32 %i0 to i64
+  %x1 = sext i32 %i1 to i64
+  %v0 = insertelement <2 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <2 x i64>   %v0, i64 %x1, i32 1
+  ret <2 x i64> %v1
+}
+
+define <4 x i64> @loadext_4i32_to_4i64(i32* %p0) {
+; SSE-LABEL: @loadext_4i32_to_4i64(
+; SSE-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; SSE-NEXT:    [[P2:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 2
+; SSE-NEXT:    [[P3:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 3
+; SSE-NEXT:    [[I0:%.*]] = load i32, i32* [[P0]], align 1
+; SSE-NEXT:    [[I1:%.*]] = load i32, i32* [[P1]], align 1
+; SSE-NEXT:    [[I2:%.*]] = load i32, i32* [[P2]], align 1
+; SSE-NEXT:    [[I3:%.*]] = load i32, i32* [[P3]], align 1
+; SSE-NEXT:    [[X0:%.*]] = sext i32 [[I0]] to i64
+; SSE-NEXT:    [[X1:%.*]] = sext i32 [[I1]] to i64
+; SSE-NEXT:    [[X2:%.*]] = sext i32 [[I2]] to i64
+; SSE-NEXT:    [[X3:%.*]] = sext i32 [[I3]] to i64
+; SSE-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[X0]], i32 0
+; SSE-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[X1]], i32 1
+; SSE-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[X2]], i32 2
+; SSE-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[X3]], i32 3
+; SSE-NEXT:    ret <4 x i64> [[V3]]
+;
+; AVX-LABEL: @loadext_4i32_to_4i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i32* [[P0]] to <4 x i32>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = sext <4 x i32> [[TMP2]] to <4 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i64> [[V3]]
+;
+  %p1 = getelementptr inbounds i32, i32* %p0, i64 1
+  %p2 = getelementptr inbounds i32, i32* %p0, i64 2
+  %p3 = getelementptr inbounds i32, i32* %p0, i64 3
+  %i0 = load i32, i32* %p0, align 1
+  %i1 = load i32, i32* %p1, align 1
+  %i2 = load i32, i32* %p2, align 1
+  %i3 = load i32, i32* %p3, align 1
+  %x0 = sext i32 %i0 to i64
+  %x1 = sext i32 %i1 to i64
+  %x2 = sext i32 %i2 to i64
+  %x3 = sext i32 %i3 to i64
+  %v0 = insertelement <4 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <4 x i64>   %v0, i64 %x1, i32 1
+  %v2 = insertelement <4 x i64>   %v1, i64 %x2, i32 2
+  %v3 = insertelement <4 x i64>   %v2, i64 %x3, i32 3
+  ret <4 x i64> %v3
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sign-extend-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sign-extend-inseltpoison.ll
new file mode 100644
index 0000000000000..296486b49e148
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sign-extend-inseltpoison.ll
@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer < %s -S -o - -mtriple=x86_64-apple-macosx10.10.0 -mcpu=core2 | FileCheck %s
+
+define <4 x i32> @sign_extend_v_v(<4 x i16> %lhs) {
+; CHECK-LABEL: @sign_extend_v_v(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = sext <4 x i16> [[LHS:%.*]] to <4 x i32>
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i32 0
+; CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0]], i32 1
+; CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <4 x i32> [[VECINIT]], i32 [[TMP2]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i32> [[TMP0]], i32 2
+; CHECK-NEXT:    [[VECINIT6:%.*]] = insertelement <4 x i32> [[VECINIT3]], i32 [[TMP3]], i32 2
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP0]], i32 3
+; CHECK-NEXT:    [[VECINIT9:%.*]] = insertelement <4 x i32> [[VECINIT6]], i32 [[TMP4]], i32 3
+; CHECK-NEXT:    ret <4 x i32> [[VECINIT9]]
+;
+entry:
+  %vecext = extractelement <4 x i16> %lhs, i32 0
+  %conv = sext i16 %vecext to i32
+  %vecinit = insertelement <4 x i32> poison, i32 %conv, i32 0
+  %vecext1 = extractelement <4 x i16> %lhs, i32 1
+  %conv2 = sext i16 %vecext1 to i32
+  %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
+  %vecext4 = extractelement <4 x i16> %lhs, i32 2
+  %conv5 = sext i16 %vecext4 to i32
+  %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
+  %vecext7 = extractelement <4 x i16> %lhs, i32 3
+  %conv8 = sext i16 %vecext7 to i32
+  %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
+  ret <4 x i32> %vecinit9
+}
+
+define <4 x i16> @truncate_v_v(<4 x i32> %lhs) {
+; CHECK-LABEL: @truncate_v_v(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = trunc <4 x i32> [[LHS:%.*]] to <4 x i16>
+; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i16> [[TMP0]], i32 0
+; CHECK-NEXT:    [[VECINIT:%.*]] = insertelement <4 x i16> poison, i16 [[TMP1]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x i16> [[TMP0]], i32 1
+; CHECK-NEXT:    [[VECINIT3:%.*]] = insertelement <4 x i16> [[VECINIT]], i16 [[TMP2]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i16> [[TMP0]], i32 2
+; CHECK-NEXT:    [[VECINIT6:%.*]] = insertelement <4 x i16> [[VECINIT3]], i16 [[TMP3]], i32 2
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x i16> [[TMP0]], i32 3
+; CHECK-NEXT:    [[VECINIT9:%.*]] = insertelement <4 x i16> [[VECINIT6]], i16 [[TMP4]], i32 3
+; CHECK-NEXT:    ret <4 x i16> [[VECINIT9]]
+;
+entry:
+  %vecext = extractelement <4 x i32> %lhs, i32 0
+  %conv = trunc i32 %vecext to i16
+  %vecinit = insertelement <4 x i16> poison, i16 %conv, i32 0
+  %vecext1 = extractelement <4 x i32> %lhs, i32 1
+  %conv2 = trunc i32 %vecext1 to i16
+  %vecinit3 = insertelement <4 x i16> %vecinit, i16 %conv2, i32 1
+  %vecext4 = extractelement <4 x i32> %lhs, i32 2
+  %conv5 = trunc i32 %vecext4 to i16
+  %vecinit6 = insertelement <4 x i16> %vecinit3, i16 %conv5, i32 2
+  %vecext7 = extractelement <4 x i32> %lhs, i32 3
+  %conv8 = trunc i32 %vecext7 to i16
+  %vecinit9 = insertelement <4 x i16> %vecinit6, i16 %conv8, i32 3
+  ret <4 x i16> %vecinit9
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
new file mode 100644
index 0000000000000..7718bcd727a30
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
@@ -0,0 +1,1331 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256 --check-prefix=AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256 --check-prefix=AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256 --check-prefix=AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256 --check-prefix=AVX256DQ
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+@src64 = common global [8 x i64] zeroinitializer, align 64
+@src32 = common global [16 x i32] zeroinitializer, align 64
+@src16 = common global [32 x i16] zeroinitializer, align 64
+@src8  = common global [64 x i8] zeroinitializer, align 64
+
+@dst64 = common global [8 x double] zeroinitializer, align 64
+@dst32 = common global [16 x float] zeroinitializer, align 64
+
+;
+; SITOFP to vXf64
+;
+
+define void @sitofp_2i64_2f64() #0 {
+; SSE-LABEL: @sitofp_2i64_2f64(
+; SSE-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; SSE-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; SSE-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    ret void
+;
+; AVX256NODQ-LABEL: @sitofp_2i64_2f64(
+; AVX256NODQ-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX256NODQ-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX256NODQ-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_2i64_2f64(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @src64 to <2 x i64>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX512-NEXT:    store <2 x double> [[TMP2]], <2 x double>* bitcast ([8 x double]* @dst64 to <2 x double>*), align 64
+; AVX512-NEXT:    ret void
+;
+; AVX256DQ-LABEL: @sitofp_2i64_2f64(
+; AVX256DQ-NEXT:    [[TMP1:%.*]] = load <2 x i64>, <2 x i64>* bitcast ([8 x i64]* @src64 to <2 x i64>*), align 64
+; AVX256DQ-NEXT:    [[TMP2:%.*]] = sitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX256DQ-NEXT:    store <2 x double> [[TMP2]], <2 x double>* bitcast ([8 x double]* @dst64 to <2 x double>*), align 64
+; AVX256DQ-NEXT:    ret void
+;
+  %ld0 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+  %ld1 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+  %cvt0 = sitofp i64 %ld0 to double
+  %cvt1 = sitofp i64 %ld1 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  ret void
+}
+
+define void @sitofp_4i64_4f64() #0 {
+; SSE-LABEL: @sitofp_4i64_4f64(
+; SSE-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; SSE-NEXT:    [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+; SSE-NEXT:    [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; SSE-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; SSE-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; SSE-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    ret void
+;
+; AVX256NODQ-LABEL: @sitofp_4i64_4f64(
+; AVX256NODQ-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+; AVX256NODQ-NEXT:    [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+; AVX256NODQ-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX256NODQ-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX256NODQ-NEXT:    [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX256NODQ-NEXT:    [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX256NODQ-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; AVX256NODQ-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; AVX256NODQ-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_4i64_4f64(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
+; AVX512-NEXT:    store <4 x double> [[TMP2]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
+; AVX512-NEXT:    ret void
+;
+; AVX256DQ-LABEL: @sitofp_4i64_4f64(
+; AVX256DQ-NEXT:    [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
+; AVX256DQ-NEXT:    [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT:    store <4 x double> [[TMP2]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
+; AVX256DQ-NEXT:    ret void
+;
+  %ld0 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+  %ld1 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+  %ld2 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+  %ld3 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+  %cvt0 = sitofp i64 %ld0 to double
+  %cvt1 = sitofp i64 %ld1 to double
+  %cvt2 = sitofp i64 %ld2 to double
+  %cvt3 = sitofp i64 %ld3 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  store double %cvt2, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+  store double %cvt3, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+  ret void
+}
+
+define void @sitofp_8i64_8f64() #0 {
+; SSE-LABEL: @sitofp_8i64_8f64(
+; SSE-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; SSE-NEXT:    [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+; SSE-NEXT:    [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+; SSE-NEXT:    [[LD4:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4), align 32
+; SSE-NEXT:    [[LD5:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 5), align 8
+; SSE-NEXT:    [[LD6:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 6), align 16
+; SSE-NEXT:    [[LD7:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 7), align 8
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; SSE-NEXT:    [[CVT4:%.*]] = sitofp i64 [[LD4]] to double
+; SSE-NEXT:    [[CVT5:%.*]] = sitofp i64 [[LD5]] to double
+; SSE-NEXT:    [[CVT6:%.*]] = sitofp i64 [[LD6]] to double
+; SSE-NEXT:    [[CVT7:%.*]] = sitofp i64 [[LD7]] to double
+; SSE-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; SSE-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; SSE-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    store double [[CVT4]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
+; SSE-NEXT:    store double [[CVT5]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
+; SSE-NEXT:    store double [[CVT6]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
+; SSE-NEXT:    store double [[CVT7]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
+; SSE-NEXT:    ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i64_8f64(
+; AVX256NODQ-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+; AVX256NODQ-NEXT:    [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+; AVX256NODQ-NEXT:    [[LD4:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4), align 32
+; AVX256NODQ-NEXT:    [[LD5:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 5), align 8
+; AVX256NODQ-NEXT:    [[LD6:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 6), align 16
+; AVX256NODQ-NEXT:    [[LD7:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 7), align 8
+; AVX256NODQ-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX256NODQ-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX256NODQ-NEXT:    [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX256NODQ-NEXT:    [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX256NODQ-NEXT:    [[CVT4:%.*]] = sitofp i64 [[LD4]] to double
+; AVX256NODQ-NEXT:    [[CVT5:%.*]] = sitofp i64 [[LD5]] to double
+; AVX256NODQ-NEXT:    [[CVT6:%.*]] = sitofp i64 [[LD6]] to double
+; AVX256NODQ-NEXT:    [[CVT7:%.*]] = sitofp i64 [[LD7]] to double
+; AVX256NODQ-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; AVX256NODQ-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; AVX256NODQ-NEXT:    store double [[CVT4]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
+; AVX256NODQ-NEXT:    store double [[CVT5]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
+; AVX256NODQ-NEXT:    store double [[CVT6]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
+; AVX256NODQ-NEXT:    store double [[CVT7]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
+; AVX256NODQ-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_8i64_8f64(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <8 x i64>, <8 x i64>* bitcast ([8 x i64]* @src64 to <8 x i64>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x double>
+; AVX512-NEXT:    store <8 x double> [[TMP2]], <8 x double>* bitcast ([8 x double]* @dst64 to <8 x double>*), align 64
+; AVX512-NEXT:    ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i64_8f64(
+; AVX256DQ-NEXT:    [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
+; AVX256DQ-NEXT:    [[TMP2:%.*]] = load <4 x i64>, <4 x i64>* bitcast (i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4) to <4 x i64>*), align 32
+; AVX256DQ-NEXT:    [[TMP3:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT:    [[TMP4:%.*]] = sitofp <4 x i64> [[TMP2]] to <4 x double>
+; AVX256DQ-NEXT:    store <4 x double> [[TMP3]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
+; AVX256DQ-NEXT:    store <4 x double> [[TMP4]], <4 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4) to <4 x double>*), align 32
+; AVX256DQ-NEXT:    ret void
+;
+  %ld0 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+  %ld1 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+  %ld2 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+  %ld3 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+  %ld4 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4), align 32
+  %ld5 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 5), align 8
+  %ld6 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 6), align 16
+  %ld7 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 7), align 8
+  %cvt0 = sitofp i64 %ld0 to double
+  %cvt1 = sitofp i64 %ld1 to double
+  %cvt2 = sitofp i64 %ld2 to double
+  %cvt3 = sitofp i64 %ld3 to double
+  %cvt4 = sitofp i64 %ld4 to double
+  %cvt5 = sitofp i64 %ld5 to double
+  %cvt6 = sitofp i64 %ld6 to double
+  %cvt7 = sitofp i64 %ld7 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  store double %cvt2, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+  store double %cvt3, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+  store double %cvt4, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
+  store double %cvt5, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
+  store double %cvt6, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
+  store double %cvt7, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
+  ret void
+}
+
+define void @sitofp_2i32_2f64() #0 {
+; CHECK-LABEL: @sitofp_2i32_2f64(
+; CHECK-NEXT:    [[LD0:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 0), align 64
+; CHECK-NEXT:    [[LD1:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 1), align 4
+; CHECK-NEXT:    [[CVT0:%.*]] = sitofp i32 [[LD0]] to double
+; CHECK-NEXT:    [[CVT1:%.*]] = sitofp i32 [[LD1]] to double
+; CHECK-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; CHECK-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; CHECK-NEXT:    ret void
+;
+  %ld0 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 0), align 64
+  %ld1 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 1), align 4
+  %cvt0 = sitofp i32 %ld0 to double
+  %cvt1 = sitofp i32 %ld1 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  ret void
+}
+
+define void @sitofp_4i32_4f64() #0 {
+; SSE-LABEL: @sitofp_4i32_4f64(
+; SSE-NEXT:    [[LD0:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 1), align 4
+; SSE-NEXT:    [[LD2:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 2), align 8
+; SSE-NEXT:    [[LD3:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 3), align 4
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i32 [[LD0]] to double
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i32 [[LD1]] to double
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i32 [[LD2]] to double
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i32 [[LD3]] to double
+; SSE-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; SSE-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; SSE-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @sitofp_4i32_4f64(
+; AVX-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @src32 to <4 x i32>*), align 64
+; AVX-NEXT:    [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX-NEXT:    store <4 x double> [[TMP2]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
+; AVX-NEXT:    ret void
+;
+  %ld0 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 0), align 64
+  %ld1 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 1), align 4
+  %ld2 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 2), align 8
+  %ld3 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 3), align 4
+  %cvt0 = sitofp i32 %ld0 to double
+  %cvt1 = sitofp i32 %ld1 to double
+  %cvt2 = sitofp i32 %ld2 to double
+  %cvt3 = sitofp i32 %ld3 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  store double %cvt2, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+  store double %cvt3, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+  ret void
+}
+
+define void @sitofp_8i32_8f64() #0 {
+; SSE-LABEL: @sitofp_8i32_8f64(
+; SSE-NEXT:    [[LD0:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 1), align 4
+; SSE-NEXT:    [[LD2:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 2), align 8
+; SSE-NEXT:    [[LD3:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 3), align 4
+; SSE-NEXT:    [[LD4:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 4), align 16
+; SSE-NEXT:    [[LD5:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 5), align 4
+; SSE-NEXT:    [[LD6:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 6), align 8
+; SSE-NEXT:    [[LD7:%.*]] = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 7), align 4
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i32 [[LD0]] to double
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i32 [[LD1]] to double
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i32 [[LD2]] to double
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i32 [[LD3]] to double
+; SSE-NEXT:    [[CVT4:%.*]] = sitofp i32 [[LD4]] to double
+; SSE-NEXT:    [[CVT5:%.*]] = sitofp i32 [[LD5]] to double
+; SSE-NEXT:    [[CVT6:%.*]] = sitofp i32 [[LD6]] to double
+; SSE-NEXT:    [[CVT7:%.*]] = sitofp i32 [[LD7]] to double
+; SSE-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; SSE-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; SSE-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    store double [[CVT4]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
+; SSE-NEXT:    store double [[CVT5]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
+; SSE-NEXT:    store double [[CVT6]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
+; SSE-NEXT:    store double [[CVT7]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
+; SSE-NEXT:    ret void
+;
+; AVX256-LABEL: @sitofp_8i32_8f64(
+; AVX256-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @src32 to <4 x i32>*), align 64
+; AVX256-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 4) to <4 x i32>*), align 16
+; AVX256-NEXT:    [[TMP3:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX256-NEXT:    [[TMP4:%.*]] = sitofp <4 x i32> [[TMP2]] to <4 x double>
+; AVX256-NEXT:    store <4 x double> [[TMP3]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
+; AVX256-NEXT:    store <4 x double> [[TMP4]], <4 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4) to <4 x double>*), align 32
+; AVX256-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_8i32_8f64(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([16 x i32]* @src32 to <8 x i32>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x double>
+; AVX512-NEXT:    store <8 x double> [[TMP2]], <8 x double>* bitcast ([8 x double]* @dst64 to <8 x double>*), align 64
+; AVX512-NEXT:    ret void
+;
+  %ld0 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 0), align 64
+  %ld1 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 1), align 4
+  %ld2 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 2), align 8
+  %ld3 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 3), align 4
+  %ld4 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 4), align 16
+  %ld5 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 5), align 4
+  %ld6 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 6), align 8
+  %ld7 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 7), align 4
+  %cvt0 = sitofp i32 %ld0 to double
+  %cvt1 = sitofp i32 %ld1 to double
+  %cvt2 = sitofp i32 %ld2 to double
+  %cvt3 = sitofp i32 %ld3 to double
+  %cvt4 = sitofp i32 %ld4 to double
+  %cvt5 = sitofp i32 %ld5 to double
+  %cvt6 = sitofp i32 %ld6 to double
+  %cvt7 = sitofp i32 %ld7 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  store double %cvt2, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+  store double %cvt3, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+  store double %cvt4, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
+  store double %cvt5, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
+  store double %cvt6, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
+  store double %cvt7, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
+  ret void
+}
+
+define void @sitofp_2i16_2f64() #0 {
+; CHECK-LABEL: @sitofp_2i16_2f64(
+; CHECK-NEXT:    [[LD0:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+; CHECK-NEXT:    [[LD1:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+; CHECK-NEXT:    [[CVT0:%.*]] = sitofp i16 [[LD0]] to double
+; CHECK-NEXT:    [[CVT1:%.*]] = sitofp i16 [[LD1]] to double
+; CHECK-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; CHECK-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; CHECK-NEXT:    ret void
+;
+  %ld0 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+  %ld1 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+  %cvt0 = sitofp i16 %ld0 to double
+  %cvt1 = sitofp i16 %ld1 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  ret void
+}
+
+define void @sitofp_4i16_4f64() #0 {
+; SSE-LABEL: @sitofp_4i16_4f64(
+; SSE-NEXT:    [[LD0:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+; SSE-NEXT:    [[LD2:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2), align 4
+; SSE-NEXT:    [[LD3:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3), align 2
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i16 [[LD0]] to double
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i16 [[LD1]] to double
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i16 [[LD2]] to double
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i16 [[LD3]] to double
+; SSE-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; SSE-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; SSE-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @sitofp_4i16_4f64(
+; AVX-NEXT:    [[TMP1:%.*]] = load <4 x i16>, <4 x i16>* bitcast ([32 x i16]* @src16 to <4 x i16>*), align 64
+; AVX-NEXT:    [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX-NEXT:    store <4 x double> [[TMP2]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
+; AVX-NEXT:    ret void
+;
+  %ld0 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+  %ld1 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+  %ld2 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2), align 4
+  %ld3 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3), align 2
+  %cvt0 = sitofp i16 %ld0 to double
+  %cvt1 = sitofp i16 %ld1 to double
+  %cvt2 = sitofp i16 %ld2 to double
+  %cvt3 = sitofp i16 %ld3 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  store double %cvt2, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+  store double %cvt3, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+  ret void
+}
+
+define void @sitofp_8i16_8f64() #0 {
+; SSE-LABEL: @sitofp_8i16_8f64(
+; SSE-NEXT:    [[LD0:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+; SSE-NEXT:    [[LD2:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2), align 4
+; SSE-NEXT:    [[LD3:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3), align 2
+; SSE-NEXT:    [[LD4:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 4), align 8
+; SSE-NEXT:    [[LD5:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 5), align 2
+; SSE-NEXT:    [[LD6:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 6), align 4
+; SSE-NEXT:    [[LD7:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 7), align 2
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i16 [[LD0]] to double
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i16 [[LD1]] to double
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i16 [[LD2]] to double
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i16 [[LD3]] to double
+; SSE-NEXT:    [[CVT4:%.*]] = sitofp i16 [[LD4]] to double
+; SSE-NEXT:    [[CVT5:%.*]] = sitofp i16 [[LD5]] to double
+; SSE-NEXT:    [[CVT6:%.*]] = sitofp i16 [[LD6]] to double
+; SSE-NEXT:    [[CVT7:%.*]] = sitofp i16 [[LD7]] to double
+; SSE-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; SSE-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; SSE-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    store double [[CVT4]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
+; SSE-NEXT:    store double [[CVT5]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
+; SSE-NEXT:    store double [[CVT6]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
+; SSE-NEXT:    store double [[CVT7]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
+; SSE-NEXT:    ret void
+;
+; AVX256-LABEL: @sitofp_8i16_8f64(
+; AVX256-NEXT:    [[TMP1:%.*]] = load <4 x i16>, <4 x i16>* bitcast ([32 x i16]* @src16 to <4 x i16>*), align 64
+; AVX256-NEXT:    [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 4) to <4 x i16>*), align 8
+; AVX256-NEXT:    [[TMP3:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX256-NEXT:    [[TMP4:%.*]] = sitofp <4 x i16> [[TMP2]] to <4 x double>
+; AVX256-NEXT:    store <4 x double> [[TMP3]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
+; AVX256-NEXT:    store <4 x double> [[TMP4]], <4 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4) to <4 x double>*), align 32
+; AVX256-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_8i16_8f64(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([32 x i16]* @src16 to <8 x i16>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x double>
+; AVX512-NEXT:    store <8 x double> [[TMP2]], <8 x double>* bitcast ([8 x double]* @dst64 to <8 x double>*), align 64
+; AVX512-NEXT:    ret void
+;
+  %ld0 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+  %ld1 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+  %ld2 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2), align 4
+  %ld3 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3), align 2
+  %ld4 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 4), align 8
+  %ld5 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 5), align 2
+  %ld6 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 6), align 4
+  %ld7 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 7), align 2
+  %cvt0 = sitofp i16 %ld0 to double
+  %cvt1 = sitofp i16 %ld1 to double
+  %cvt2 = sitofp i16 %ld2 to double
+  %cvt3 = sitofp i16 %ld3 to double
+  %cvt4 = sitofp i16 %ld4 to double
+  %cvt5 = sitofp i16 %ld5 to double
+  %cvt6 = sitofp i16 %ld6 to double
+  %cvt7 = sitofp i16 %ld7 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  store double %cvt2, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+  store double %cvt3, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+  store double %cvt4, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
+  store double %cvt5, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
+  store double %cvt6, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
+  store double %cvt7, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
+  ret void
+}
+
+define void @sitofp_2i8_2f64() #0 {
+; CHECK-LABEL: @sitofp_2i8_2f64(
+; CHECK-NEXT:    [[LD0:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 0), align 64
+; CHECK-NEXT:    [[LD1:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 1), align 1
+; CHECK-NEXT:    [[CVT0:%.*]] = sitofp i8 [[LD0]] to double
+; CHECK-NEXT:    [[CVT1:%.*]] = sitofp i8 [[LD1]] to double
+; CHECK-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; CHECK-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; CHECK-NEXT:    ret void
+;
+  %ld0 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 0), align 64
+  %ld1 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 1), align 1
+  %cvt0 = sitofp i8 %ld0 to double
+  %cvt1 = sitofp i8 %ld1 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  ret void
+}
+
+define void @sitofp_4i8_4f64() #0 {
+; SSE-LABEL: @sitofp_4i8_4f64(
+; SSE-NEXT:    [[LD0:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 1), align 1
+; SSE-NEXT:    [[LD2:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 2), align 2
+; SSE-NEXT:    [[LD3:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 3), align 1
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i8 [[LD0]] to double
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i8 [[LD1]] to double
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i8 [[LD2]] to double
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i8 [[LD3]] to double
+; SSE-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; SSE-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; SSE-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @sitofp_4i8_4f64(
+; AVX-NEXT:    [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* bitcast ([64 x i8]* @src8 to <4 x i8>*), align 64
+; AVX-NEXT:    [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX-NEXT:    store <4 x double> [[TMP2]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
+; AVX-NEXT:    ret void
+;
+  %ld0 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 0), align 64
+  %ld1 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 1), align 1
+  %ld2 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 2), align 2
+  %ld3 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 3), align 1
+  %cvt0 = sitofp i8 %ld0 to double
+  %cvt1 = sitofp i8 %ld1 to double
+  %cvt2 = sitofp i8 %ld2 to double
+  %cvt3 = sitofp i8 %ld3 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  store double %cvt2, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+  store double %cvt3, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+  ret void
+}
+
+define void @sitofp_8i8_8f64() #0 {
+; SSE-LABEL: @sitofp_8i8_8f64(
+; SSE-NEXT:    [[LD0:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 1), align 1
+; SSE-NEXT:    [[LD2:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 2), align 2
+; SSE-NEXT:    [[LD3:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 3), align 1
+; SSE-NEXT:    [[LD4:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 4), align 4
+; SSE-NEXT:    [[LD5:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 5), align 1
+; SSE-NEXT:    [[LD6:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 6), align 2
+; SSE-NEXT:    [[LD7:%.*]] = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 7), align 1
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i8 [[LD0]] to double
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i8 [[LD1]] to double
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i8 [[LD2]] to double
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i8 [[LD3]] to double
+; SSE-NEXT:    [[CVT4:%.*]] = sitofp i8 [[LD4]] to double
+; SSE-NEXT:    [[CVT5:%.*]] = sitofp i8 [[LD5]] to double
+; SSE-NEXT:    [[CVT6:%.*]] = sitofp i8 [[LD6]] to double
+; SSE-NEXT:    [[CVT7:%.*]] = sitofp i8 [[LD7]] to double
+; SSE-NEXT:    store double [[CVT0]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+; SSE-NEXT:    store double [[CVT1]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+; SSE-NEXT:    store double [[CVT2]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+; SSE-NEXT:    store double [[CVT3]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+; SSE-NEXT:    store double [[CVT4]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
+; SSE-NEXT:    store double [[CVT5]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
+; SSE-NEXT:    store double [[CVT6]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
+; SSE-NEXT:    store double [[CVT7]], double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
+; SSE-NEXT:    ret void
+;
+; AVX256-LABEL: @sitofp_8i8_8f64(
+; AVX256-NEXT:    [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* bitcast ([64 x i8]* @src8 to <4 x i8>*), align 64
+; AVX256-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* bitcast (i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 4) to <4 x i8>*), align 4
+; AVX256-NEXT:    [[TMP3:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX256-NEXT:    [[TMP4:%.*]] = sitofp <4 x i8> [[TMP2]] to <4 x double>
+; AVX256-NEXT:    store <4 x double> [[TMP3]], <4 x double>* bitcast ([8 x double]* @dst64 to <4 x double>*), align 64
+; AVX256-NEXT:    store <4 x double> [[TMP4]], <4 x double>* bitcast (double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4) to <4 x double>*), align 32
+; AVX256-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_8i8_8f64(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* bitcast ([64 x i8]* @src8 to <8 x i8>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x double>
+; AVX512-NEXT:    store <8 x double> [[TMP2]], <8 x double>* bitcast ([8 x double]* @dst64 to <8 x double>*), align 64
+; AVX512-NEXT:    ret void
+;
+  %ld0 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 0), align 64
+  %ld1 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 1), align 1
+  %ld2 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 2), align 2
+  %ld3 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 3), align 1
+  %ld4 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 4), align 4
+  %ld5 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 5), align 1
+  %ld6 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 6), align 2
+  %ld7 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 7), align 1
+  %cvt0 = sitofp i8 %ld0 to double
+  %cvt1 = sitofp i8 %ld1 to double
+  %cvt2 = sitofp i8 %ld2 to double
+  %cvt3 = sitofp i8 %ld3 to double
+  %cvt4 = sitofp i8 %ld4 to double
+  %cvt5 = sitofp i8 %ld5 to double
+  %cvt6 = sitofp i8 %ld6 to double
+  %cvt7 = sitofp i8 %ld7 to double
+  store double %cvt0, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 0), align 64
+  store double %cvt1, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 1), align 8
+  store double %cvt2, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 2), align 16
+  store double %cvt3, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 3), align 8
+  store double %cvt4, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 4), align 32
+  store double %cvt5, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 5), align 8
+  store double %cvt6, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 6), align 16
+  store double %cvt7, double* getelementptr inbounds ([8 x double], [8 x double]* @dst64, i32 0, i64 7), align 8
+  ret void
+}
+
+;
+; SITOFP to vXf32
+;
+
+define void @sitofp_2i64_2f32() #0 {
+; CHECK-LABEL: @sitofp_2i64_2f32(
+; CHECK-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; CHECK-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; CHECK-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
+; CHECK-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
+; CHECK-NEXT:    store float [[CVT0]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+; CHECK-NEXT:    store float [[CVT1]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+; CHECK-NEXT:    ret void
+;
+  %ld0 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+  %ld1 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+  %cvt0 = sitofp i64 %ld0 to float
+  %cvt1 = sitofp i64 %ld1 to float
+  store float %cvt0, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+  store float %cvt1, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+  ret void
+}
+
+define void @sitofp_4i64_4f32() #0 {
+; SSE-LABEL: @sitofp_4i64_4f32(
+; SSE-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; SSE-NEXT:    [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+; SSE-NEXT:    [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i64 [[LD2]] to float
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i64 [[LD3]] to float
+; SSE-NEXT:    store float [[CVT0]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+; SSE-NEXT:    store float [[CVT1]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+; SSE-NEXT:    store float [[CVT2]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+; SSE-NEXT:    store float [[CVT3]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+; SSE-NEXT:    ret void
+;
+; AVX256NODQ-LABEL: @sitofp_4i64_4f32(
+; AVX256NODQ-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+; AVX256NODQ-NEXT:    [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+; AVX256NODQ-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
+; AVX256NODQ-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
+; AVX256NODQ-NEXT:    [[CVT2:%.*]] = sitofp i64 [[LD2]] to float
+; AVX256NODQ-NEXT:    [[CVT3:%.*]] = sitofp i64 [[LD3]] to float
+; AVX256NODQ-NEXT:    store float [[CVT0]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    store float [[CVT1]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+; AVX256NODQ-NEXT:    store float [[CVT2]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+; AVX256NODQ-NEXT:    store float [[CVT3]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+; AVX256NODQ-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_4i64_4f32(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x float>
+; AVX512-NEXT:    store <4 x float> [[TMP2]], <4 x float>* bitcast ([16 x float]* @dst32 to <4 x float>*), align 64
+; AVX512-NEXT:    ret void
+;
+; AVX256DQ-LABEL: @sitofp_4i64_4f32(
+; AVX256DQ-NEXT:    [[TMP1:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([8 x i64]* @src64 to <4 x i64>*), align 64
+; AVX256DQ-NEXT:    [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x float>
+; AVX256DQ-NEXT:    store <4 x float> [[TMP2]], <4 x float>* bitcast ([16 x float]* @dst32 to <4 x float>*), align 64
+; AVX256DQ-NEXT:    ret void
+;
+  %ld0 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+  %ld1 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+  %ld2 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+  %ld3 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+  %cvt0 = sitofp i64 %ld0 to float
+  %cvt1 = sitofp i64 %ld1 to float
+  %cvt2 = sitofp i64 %ld2 to float
+  %cvt3 = sitofp i64 %ld3 to float
+  store float %cvt0, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+  store float %cvt1, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+  store float %cvt2, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+  store float %cvt3, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+  ret void
+}
+
+define void @sitofp_8i64_8f32() #0 {
+; SSE-LABEL: @sitofp_8i64_8f32(
+; SSE-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; SSE-NEXT:    [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+; SSE-NEXT:    [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+; SSE-NEXT:    [[LD4:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4), align 32
+; SSE-NEXT:    [[LD5:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 5), align 8
+; SSE-NEXT:    [[LD6:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 6), align 16
+; SSE-NEXT:    [[LD7:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 7), align 8
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i64 [[LD2]] to float
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i64 [[LD3]] to float
+; SSE-NEXT:    [[CVT4:%.*]] = sitofp i64 [[LD4]] to float
+; SSE-NEXT:    [[CVT5:%.*]] = sitofp i64 [[LD5]] to float
+; SSE-NEXT:    [[CVT6:%.*]] = sitofp i64 [[LD6]] to float
+; SSE-NEXT:    [[CVT7:%.*]] = sitofp i64 [[LD7]] to float
+; SSE-NEXT:    store float [[CVT0]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+; SSE-NEXT:    store float [[CVT1]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+; SSE-NEXT:    store float [[CVT2]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+; SSE-NEXT:    store float [[CVT3]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+; SSE-NEXT:    store float [[CVT4]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4), align 16
+; SSE-NEXT:    store float [[CVT5]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5), align 4
+; SSE-NEXT:    store float [[CVT6]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6), align 8
+; SSE-NEXT:    store float [[CVT7]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7), align 4
+; SSE-NEXT:    ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i64_8f32(
+; AVX256NODQ-NEXT:    [[LD0:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    [[LD1:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+; AVX256NODQ-NEXT:    [[LD2:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+; AVX256NODQ-NEXT:    [[LD3:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+; AVX256NODQ-NEXT:    [[LD4:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4), align 32
+; AVX256NODQ-NEXT:    [[LD5:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 5), align 8
+; AVX256NODQ-NEXT:    [[LD6:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 6), align 16
+; AVX256NODQ-NEXT:    [[LD7:%.*]] = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 7), align 8
+; AVX256NODQ-NEXT:    [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
+; AVX256NODQ-NEXT:    [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
+; AVX256NODQ-NEXT:    [[CVT2:%.*]] = sitofp i64 [[LD2]] to float
+; AVX256NODQ-NEXT:    [[CVT3:%.*]] = sitofp i64 [[LD3]] to float
+; AVX256NODQ-NEXT:    [[CVT4:%.*]] = sitofp i64 [[LD4]] to float
+; AVX256NODQ-NEXT:    [[CVT5:%.*]] = sitofp i64 [[LD5]] to float
+; AVX256NODQ-NEXT:    [[CVT6:%.*]] = sitofp i64 [[LD6]] to float
+; AVX256NODQ-NEXT:    [[CVT7:%.*]] = sitofp i64 [[LD7]] to float
+; AVX256NODQ-NEXT:    store float [[CVT0]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+; AVX256NODQ-NEXT:    store float [[CVT1]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+; AVX256NODQ-NEXT:    store float [[CVT2]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+; AVX256NODQ-NEXT:    store float [[CVT3]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+; AVX256NODQ-NEXT:    store float [[CVT4]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4), align 16
+; AVX256NODQ-NEXT:    store float [[CVT5]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5), align 4
+; AVX256NODQ-NEXT:    store float [[CVT6]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6), align 8
+; AVX256NODQ-NEXT:    store float [[CVT7]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7), align 4
+; AVX256NODQ-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_8i64_8f32(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <8 x i64>, <8 x i64>* bitcast ([8 x i64]* @src64 to <8 x i64>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
+; AVX512-NEXT:    store <8 x float> [[TMP2]], <8 x float>* bitcast ([16 x float]* @dst32 to <8 x float>*), align 64
+; AVX512-NEXT:    ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i64_8f32(
+; AVX256DQ-NEXT:    [[TMP1:%.*]] = load <8 x i64>, <8 x i64>* bitcast ([8 x i64]* @src64 to <8 x i64>*), align 64
+; AVX256DQ-NEXT:    [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT:    store <8 x float> [[TMP2]], <8 x float>* bitcast ([16 x float]* @dst32 to <8 x float>*), align 64
+; AVX256DQ-NEXT:    ret void
+;
+  %ld0 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 0), align 64
+  %ld1 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 1), align 8
+  %ld2 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 2), align 16
+  %ld3 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 3), align 8
+  %ld4 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 4), align 32
+  %ld5 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 5), align 8
+  %ld6 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 6), align 16
+  %ld7 = load i64, i64* getelementptr inbounds ([8 x i64], [8 x i64]* @src64, i32 0, i64 7), align 8
+  %cvt0 = sitofp i64 %ld0 to float
+  %cvt1 = sitofp i64 %ld1 to float
+  %cvt2 = sitofp i64 %ld2 to float
+  %cvt3 = sitofp i64 %ld3 to float
+  %cvt4 = sitofp i64 %ld4 to float
+  %cvt5 = sitofp i64 %ld5 to float
+  %cvt6 = sitofp i64 %ld6 to float
+  %cvt7 = sitofp i64 %ld7 to float
+  store float %cvt0, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+  store float %cvt1, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+  store float %cvt2, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+  store float %cvt3, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+  store float %cvt4, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4), align 16
+  store float %cvt5, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5), align 4
+  store float %cvt6, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6), align 8
+  store float %cvt7, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7), align 4
+  ret void
+}
+
+define void @sitofp_4i32_4f32() #0 {
+; CHECK-LABEL: @sitofp_4i32_4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @src32 to <4 x i32>*), align 64
+; CHECK-NEXT:    [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; CHECK-NEXT:    store <4 x float> [[TMP2]], <4 x float>* bitcast ([16 x float]* @dst32 to <4 x float>*), align 64
+; CHECK-NEXT:    ret void
+;
+  %ld0 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 0), align 64
+  %ld1 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 1), align 4
+  %ld2 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 2), align 8
+  %ld3 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 3), align 4
+  %cvt0 = sitofp i32 %ld0 to float
+  %cvt1 = sitofp i32 %ld1 to float
+  %cvt2 = sitofp i32 %ld2 to float
+  %cvt3 = sitofp i32 %ld3 to float
+  store float %cvt0, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+  store float %cvt1, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+  store float %cvt2, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+  store float %cvt3, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+  ret void
+}
+
+define void @sitofp_8i32_8f32() #0 {
+; SSE-LABEL: @sitofp_8i32_8f32(
+; SSE-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @src32 to <4 x i32>*), align 64
+; SSE-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 4) to <4 x i32>*), align 16
+; SSE-NEXT:    [[TMP3:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; SSE-NEXT:    [[TMP4:%.*]] = sitofp <4 x i32> [[TMP2]] to <4 x float>
+; SSE-NEXT:    store <4 x float> [[TMP3]], <4 x float>* bitcast ([16 x float]* @dst32 to <4 x float>*), align 64
+; SSE-NEXT:    store <4 x float> [[TMP4]], <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4) to <4 x float>*), align 16
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @sitofp_8i32_8f32(
+; AVX-NEXT:    [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([16 x i32]* @src32 to <8 x i32>*), align 64
+; AVX-NEXT:    [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX-NEXT:    store <8 x float> [[TMP2]], <8 x float>* bitcast ([16 x float]* @dst32 to <8 x float>*), align 64
+; AVX-NEXT:    ret void
+;
+  %ld0 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 0), align 64
+  %ld1 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 1), align 4
+  %ld2 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 2), align 8
+  %ld3 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 3), align 4
+  %ld4 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 4), align 16
+  %ld5 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 5), align 4
+  %ld6 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 6), align 8
+  %ld7 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 7), align 4
+  %cvt0 = sitofp i32 %ld0 to float
+  %cvt1 = sitofp i32 %ld1 to float
+  %cvt2 = sitofp i32 %ld2 to float
+  %cvt3 = sitofp i32 %ld3 to float
+  %cvt4 = sitofp i32 %ld4 to float
+  %cvt5 = sitofp i32 %ld5 to float
+  %cvt6 = sitofp i32 %ld6 to float
+  %cvt7 = sitofp i32 %ld7 to float
+  store float %cvt0, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+  store float %cvt1, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+  store float %cvt2, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+  store float %cvt3, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+  store float %cvt4, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4), align 16
+  store float %cvt5, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5), align 4
+  store float %cvt6, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6), align 8
+  store float %cvt7, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7), align 4
+  ret void
+}
+
+define void @sitofp_16i32_16f32() #0 {
+; SSE-LABEL: @sitofp_16i32_16f32(
+; SSE-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* bitcast ([16 x i32]* @src32 to <4 x i32>*), align 64
+; SSE-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 4) to <4 x i32>*), align 16
+; SSE-NEXT:    [[TMP3:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 8) to <4 x i32>*), align 32
+; SSE-NEXT:    [[TMP4:%.*]] = load <4 x i32>, <4 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 12) to <4 x i32>*), align 16
+; SSE-NEXT:    [[TMP5:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; SSE-NEXT:    [[TMP6:%.*]] = sitofp <4 x i32> [[TMP2]] to <4 x float>
+; SSE-NEXT:    [[TMP7:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
+; SSE-NEXT:    [[TMP8:%.*]] = sitofp <4 x i32> [[TMP4]] to <4 x float>
+; SSE-NEXT:    store <4 x float> [[TMP5]], <4 x float>* bitcast ([16 x float]* @dst32 to <4 x float>*), align 64
+; SSE-NEXT:    store <4 x float> [[TMP6]], <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4) to <4 x float>*), align 16
+; SSE-NEXT:    store <4 x float> [[TMP7]], <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 8) to <4 x float>*), align 32
+; SSE-NEXT:    store <4 x float> [[TMP8]], <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 12) to <4 x float>*), align 16
+; SSE-NEXT:    ret void
+;
+; AVX256-LABEL: @sitofp_16i32_16f32(
+; AVX256-NEXT:    [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* bitcast ([16 x i32]* @src32 to <8 x i32>*), align 64
+; AVX256-NEXT:    [[TMP2:%.*]] = load <8 x i32>, <8 x i32>* bitcast (i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 8) to <8 x i32>*), align 32
+; AVX256-NEXT:    [[TMP3:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX256-NEXT:    [[TMP4:%.*]] = sitofp <8 x i32> [[TMP2]] to <8 x float>
+; AVX256-NEXT:    store <8 x float> [[TMP3]], <8 x float>* bitcast ([16 x float]* @dst32 to <8 x float>*), align 64
+; AVX256-NEXT:    store <8 x float> [[TMP4]], <8 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 8) to <8 x float>*), align 32
+; AVX256-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_16i32_16f32(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* bitcast ([16 x i32]* @src32 to <16 x i32>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <16 x i32> [[TMP1]] to <16 x float>
+; AVX512-NEXT:    store <16 x float> [[TMP2]], <16 x float>* bitcast ([16 x float]* @dst32 to <16 x float>*), align 64
+; AVX512-NEXT:    ret void
+;
+  %ld0  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 0 ), align 64
+  %ld1  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 1 ), align 4
+  %ld2  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 2 ), align 8
+  %ld3  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 3 ), align 4
+  %ld4  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 4 ), align 16
+  %ld5  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 5 ), align 4
+  %ld6  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 6 ), align 8
+  %ld7  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 7 ), align 4
+  %ld8  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 8 ), align 32
+  %ld9  = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 9 ), align 4
+  %ld10 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 10), align 8
+  %ld11 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 11), align 4
+  %ld12 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 12), align 16
+  %ld13 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 13), align 4
+  %ld14 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 14), align 8
+  %ld15 = load i32, i32* getelementptr inbounds ([16 x i32], [16 x i32]* @src32, i32 0, i64 15), align 4
+  %cvt0  = sitofp i32 %ld0  to float
+  %cvt1  = sitofp i32 %ld1  to float
+  %cvt2  = sitofp i32 %ld2  to float
+  %cvt3  = sitofp i32 %ld3  to float
+  %cvt4  = sitofp i32 %ld4  to float
+  %cvt5  = sitofp i32 %ld5  to float
+  %cvt6  = sitofp i32 %ld6  to float
+  %cvt7  = sitofp i32 %ld7  to float
+  %cvt8  = sitofp i32 %ld8  to float
+  %cvt9  = sitofp i32 %ld9  to float
+  %cvt10 = sitofp i32 %ld10 to float
+  %cvt11 = sitofp i32 %ld11 to float
+  %cvt12 = sitofp i32 %ld12 to float
+  %cvt13 = sitofp i32 %ld13 to float
+  %cvt14 = sitofp i32 %ld14 to float
+  %cvt15 = sitofp i32 %ld15 to float
+  store float %cvt0 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0 ), align 64
+  store float %cvt1 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1 ), align 4
+  store float %cvt2 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2 ), align 8
+  store float %cvt3 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3 ), align 4
+  store float %cvt4 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4 ), align 16
+  store float %cvt5 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5 ), align 4
+  store float %cvt6 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6 ), align 8
+  store float %cvt7 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7 ), align 4
+  store float %cvt8 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 8 ), align 32
+  store float %cvt9 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 9 ), align 4
+  store float %cvt10, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 10), align 8
+  store float %cvt11, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 11), align 4
+  store float %cvt12, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 12), align 16
+  store float %cvt13, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 13), align 4
+  store float %cvt14, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 14), align 8
+  store float %cvt15, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 15), align 4
+  ret void
+}
+
+define void @sitofp_4i16_4f32() #0 {
+; SSE-LABEL: @sitofp_4i16_4f32(
+; SSE-NEXT:    [[LD0:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+; SSE-NEXT:    [[LD2:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2), align 4
+; SSE-NEXT:    [[LD3:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3), align 2
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i16 [[LD0]] to float
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i16 [[LD1]] to float
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i16 [[LD2]] to float
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i16 [[LD3]] to float
+; SSE-NEXT:    store float [[CVT0]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+; SSE-NEXT:    store float [[CVT1]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+; SSE-NEXT:    store float [[CVT2]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+; SSE-NEXT:    store float [[CVT3]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @sitofp_4i16_4f32(
+; AVX-NEXT:    [[TMP1:%.*]] = load <4 x i16>, <4 x i16>* bitcast ([32 x i16]* @src16 to <4 x i16>*), align 64
+; AVX-NEXT:    [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX-NEXT:    store <4 x float> [[TMP2]], <4 x float>* bitcast ([16 x float]* @dst32 to <4 x float>*), align 64
+; AVX-NEXT:    ret void
+;
+  %ld0 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+  %ld1 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+  %ld2 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2), align 4
+  %ld3 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3), align 2
+  %cvt0 = sitofp i16 %ld0 to float
+  %cvt1 = sitofp i16 %ld1 to float
+  %cvt2 = sitofp i16 %ld2 to float
+  %cvt3 = sitofp i16 %ld3 to float
+  store float %cvt0, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+  store float %cvt1, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+  store float %cvt2, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+  store float %cvt3, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+  ret void
+}
+
+define void @sitofp_8i16_8f32() #0 {
+; SSE-LABEL: @sitofp_8i16_8f32(
+; SSE-NEXT:    [[LD0:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+; SSE-NEXT:    [[LD2:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2), align 4
+; SSE-NEXT:    [[LD3:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3), align 2
+; SSE-NEXT:    [[LD4:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 4), align 8
+; SSE-NEXT:    [[LD5:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 5), align 2
+; SSE-NEXT:    [[LD6:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 6), align 4
+; SSE-NEXT:    [[LD7:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 7), align 2
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i16 [[LD0]] to float
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i16 [[LD1]] to float
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i16 [[LD2]] to float
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i16 [[LD3]] to float
+; SSE-NEXT:    [[CVT4:%.*]] = sitofp i16 [[LD4]] to float
+; SSE-NEXT:    [[CVT5:%.*]] = sitofp i16 [[LD5]] to float
+; SSE-NEXT:    [[CVT6:%.*]] = sitofp i16 [[LD6]] to float
+; SSE-NEXT:    [[CVT7:%.*]] = sitofp i16 [[LD7]] to float
+; SSE-NEXT:    store float [[CVT0]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+; SSE-NEXT:    store float [[CVT1]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+; SSE-NEXT:    store float [[CVT2]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+; SSE-NEXT:    store float [[CVT3]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+; SSE-NEXT:    store float [[CVT4]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4), align 16
+; SSE-NEXT:    store float [[CVT5]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5), align 4
+; SSE-NEXT:    store float [[CVT6]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6), align 8
+; SSE-NEXT:    store float [[CVT7]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7), align 4
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @sitofp_8i16_8f32(
+; AVX-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([32 x i16]* @src16 to <8 x i16>*), align 64
+; AVX-NEXT:    [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX-NEXT:    store <8 x float> [[TMP2]], <8 x float>* bitcast ([16 x float]* @dst32 to <8 x float>*), align 64
+; AVX-NEXT:    ret void
+;
+  %ld0 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+  %ld1 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+  %ld2 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2), align 4
+  %ld3 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3), align 2
+  %ld4 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 4), align 8
+  %ld5 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 5), align 2
+  %ld6 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 6), align 4
+  %ld7 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 7), align 2
+  %cvt0 = sitofp i16 %ld0 to float
+  %cvt1 = sitofp i16 %ld1 to float
+  %cvt2 = sitofp i16 %ld2 to float
+  %cvt3 = sitofp i16 %ld3 to float
+  %cvt4 = sitofp i16 %ld4 to float
+  %cvt5 = sitofp i16 %ld5 to float
+  %cvt6 = sitofp i16 %ld6 to float
+  %cvt7 = sitofp i16 %ld7 to float
+  store float %cvt0, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+  store float %cvt1, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+  store float %cvt2, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+  store float %cvt3, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+  store float %cvt4, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4), align 16
+  store float %cvt5, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5), align 4
+  store float %cvt6, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6), align 8
+  store float %cvt7, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7), align 4
+  ret void
+}
+
+define void @sitofp_16i16_16f32() #0 {
+; SSE-LABEL: @sitofp_16i16_16f32(
+; SSE-NEXT:    [[LD0:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0), align 64
+; SSE-NEXT:    [[LD1:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1), align 2
+; SSE-NEXT:    [[LD2:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2), align 4
+; SSE-NEXT:    [[LD3:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3), align 2
+; SSE-NEXT:    [[LD4:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 4), align 8
+; SSE-NEXT:    [[LD5:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 5), align 2
+; SSE-NEXT:    [[LD6:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 6), align 4
+; SSE-NEXT:    [[LD7:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 7), align 2
+; SSE-NEXT:    [[LD8:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 8), align 16
+; SSE-NEXT:    [[LD9:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 9), align 2
+; SSE-NEXT:    [[LD10:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 10), align 4
+; SSE-NEXT:    [[LD11:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 11), align 2
+; SSE-NEXT:    [[LD12:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 12), align 8
+; SSE-NEXT:    [[LD13:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 13), align 2
+; SSE-NEXT:    [[LD14:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 14), align 4
+; SSE-NEXT:    [[LD15:%.*]] = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 15), align 2
+; SSE-NEXT:    [[CVT0:%.*]] = sitofp i16 [[LD0]] to float
+; SSE-NEXT:    [[CVT1:%.*]] = sitofp i16 [[LD1]] to float
+; SSE-NEXT:    [[CVT2:%.*]] = sitofp i16 [[LD2]] to float
+; SSE-NEXT:    [[CVT3:%.*]] = sitofp i16 [[LD3]] to float
+; SSE-NEXT:    [[CVT4:%.*]] = sitofp i16 [[LD4]] to float
+; SSE-NEXT:    [[CVT5:%.*]] = sitofp i16 [[LD5]] to float
+; SSE-NEXT:    [[CVT6:%.*]] = sitofp i16 [[LD6]] to float
+; SSE-NEXT:    [[CVT7:%.*]] = sitofp i16 [[LD7]] to float
+; SSE-NEXT:    [[CVT8:%.*]] = sitofp i16 [[LD8]] to float
+; SSE-NEXT:    [[CVT9:%.*]] = sitofp i16 [[LD9]] to float
+; SSE-NEXT:    [[CVT10:%.*]] = sitofp i16 [[LD10]] to float
+; SSE-NEXT:    [[CVT11:%.*]] = sitofp i16 [[LD11]] to float
+; SSE-NEXT:    [[CVT12:%.*]] = sitofp i16 [[LD12]] to float
+; SSE-NEXT:    [[CVT13:%.*]] = sitofp i16 [[LD13]] to float
+; SSE-NEXT:    [[CVT14:%.*]] = sitofp i16 [[LD14]] to float
+; SSE-NEXT:    [[CVT15:%.*]] = sitofp i16 [[LD15]] to float
+; SSE-NEXT:    store float [[CVT0]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+; SSE-NEXT:    store float [[CVT1]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+; SSE-NEXT:    store float [[CVT2]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+; SSE-NEXT:    store float [[CVT3]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+; SSE-NEXT:    store float [[CVT4]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4), align 16
+; SSE-NEXT:    store float [[CVT5]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5), align 4
+; SSE-NEXT:    store float [[CVT6]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6), align 8
+; SSE-NEXT:    store float [[CVT7]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7), align 4
+; SSE-NEXT:    store float [[CVT8]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 8), align 32
+; SSE-NEXT:    store float [[CVT9]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 9), align 4
+; SSE-NEXT:    store float [[CVT10]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 10), align 8
+; SSE-NEXT:    store float [[CVT11]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 11), align 4
+; SSE-NEXT:    store float [[CVT12]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 12), align 16
+; SSE-NEXT:    store float [[CVT13]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 13), align 4
+; SSE-NEXT:    store float [[CVT14]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 14), align 8
+; SSE-NEXT:    store float [[CVT15]], float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 15), align 4
+; SSE-NEXT:    ret void
+;
+; AVX256-LABEL: @sitofp_16i16_16f32(
+; AVX256-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* bitcast ([32 x i16]* @src16 to <8 x i16>*), align 64
+; AVX256-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* bitcast (i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 8) to <8 x i16>*), align 16
+; AVX256-NEXT:    [[TMP3:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX256-NEXT:    [[TMP4:%.*]] = sitofp <8 x i16> [[TMP2]] to <8 x float>
+; AVX256-NEXT:    store <8 x float> [[TMP3]], <8 x float>* bitcast ([16 x float]* @dst32 to <8 x float>*), align 64
+; AVX256-NEXT:    store <8 x float> [[TMP4]], <8 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 8) to <8 x float>*), align 32
+; AVX256-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_16i16_16f32(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <16 x i16>, <16 x i16>* bitcast ([32 x i16]* @src16 to <16 x i16>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <16 x i16> [[TMP1]] to <16 x float>
+; AVX512-NEXT:    store <16 x float> [[TMP2]], <16 x float>* bitcast ([16 x float]* @dst32 to <16 x float>*), align 64
+; AVX512-NEXT:    ret void
+;
+  %ld0  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 0 ), align 64
+  %ld1  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 1 ), align 2
+  %ld2  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 2 ), align 4
+  %ld3  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 3 ), align 2
+  %ld4  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 4 ), align 8
+  %ld5  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 5 ), align 2
+  %ld6  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 6 ), align 4
+  %ld7  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 7 ), align 2
+  %ld8  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 8 ), align 16
+  %ld9  = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 9 ), align 2
+  %ld10 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 10), align 4
+  %ld11 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 11), align 2
+  %ld12 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 12), align 8
+  %ld13 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 13), align 2
+  %ld14 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 14), align 4
+  %ld15 = load i16, i16* getelementptr inbounds ([32 x i16], [32 x i16]* @src16, i32 0, i64 15), align 2
+  %cvt0  = sitofp i16 %ld0  to float
+  %cvt1  = sitofp i16 %ld1  to float
+  %cvt2  = sitofp i16 %ld2  to float
+  %cvt3  = sitofp i16 %ld3  to float
+  %cvt4  = sitofp i16 %ld4  to float
+  %cvt5  = sitofp i16 %ld5  to float
+  %cvt6  = sitofp i16 %ld6  to float
+  %cvt7  = sitofp i16 %ld7  to float
+  %cvt8  = sitofp i16 %ld8  to float
+  %cvt9  = sitofp i16 %ld9  to float
+  %cvt10 = sitofp i16 %ld10 to float
+  %cvt11 = sitofp i16 %ld11 to float
+  %cvt12 = sitofp i16 %ld12 to float
+  %cvt13 = sitofp i16 %ld13 to float
+  %cvt14 = sitofp i16 %ld14 to float
+  %cvt15 = sitofp i16 %ld15 to float
+  store float %cvt0 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0 ), align 64
+  store float %cvt1 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1 ), align 4
+  store float %cvt2 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2 ), align 8
+  store float %cvt3 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3 ), align 4
+  store float %cvt4 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4 ), align 16
+  store float %cvt5 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5 ), align 4
+  store float %cvt6 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6 ), align 8
+  store float %cvt7 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7 ), align 4
+  store float %cvt8 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 8 ), align 32
+  store float %cvt9 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 9 ), align 4
+  store float %cvt10, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 10), align 8
+  store float %cvt11, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 11), align 4
+  store float %cvt12, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 12), align 16
+  store float %cvt13, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 13), align 4
+  store float %cvt14, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 14), align 8
+  store float %cvt15, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 15), align 4
+  ret void
+}
+
+define void @sitofp_4i8_4f32() #0 {
+; CHECK-LABEL: @sitofp_4i8_4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* bitcast ([64 x i8]* @src8 to <4 x i8>*), align 64
+; CHECK-NEXT:    [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; CHECK-NEXT:    store <4 x float> [[TMP2]], <4 x float>* bitcast ([16 x float]* @dst32 to <4 x float>*), align 64
+; CHECK-NEXT:    ret void
+;
+  %ld0 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 0), align 64
+  %ld1 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 1), align 1
+  %ld2 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 2), align 2
+  %ld3 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 3), align 1
+  %cvt0 = sitofp i8 %ld0 to float
+  %cvt1 = sitofp i8 %ld1 to float
+  %cvt2 = sitofp i8 %ld2 to float
+  %cvt3 = sitofp i8 %ld3 to float
+  store float %cvt0, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+  store float %cvt1, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+  store float %cvt2, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+  store float %cvt3, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+  ret void
+}
+
+define void @sitofp_8i8_8f32() #0 {
+; SSE-LABEL: @sitofp_8i8_8f32(
+; SSE-NEXT:    [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* bitcast ([64 x i8]* @src8 to <4 x i8>*), align 64
+; SSE-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* bitcast (i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 4) to <4 x i8>*), align 4
+; SSE-NEXT:    [[TMP3:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; SSE-NEXT:    [[TMP4:%.*]] = sitofp <4 x i8> [[TMP2]] to <4 x float>
+; SSE-NEXT:    store <4 x float> [[TMP3]], <4 x float>* bitcast ([16 x float]* @dst32 to <4 x float>*), align 64
+; SSE-NEXT:    store <4 x float> [[TMP4]], <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4) to <4 x float>*), align 16
+; SSE-NEXT:    ret void
+;
+; AVX-LABEL: @sitofp_8i8_8f32(
+; AVX-NEXT:    [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* bitcast ([64 x i8]* @src8 to <8 x i8>*), align 64
+; AVX-NEXT:    [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX-NEXT:    store <8 x float> [[TMP2]], <8 x float>* bitcast ([16 x float]* @dst32 to <8 x float>*), align 64
+; AVX-NEXT:    ret void
+;
+  %ld0 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 0), align 64
+  %ld1 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 1), align 1
+  %ld2 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 2), align 2
+  %ld3 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 3), align 1
+  %ld4 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 4), align 4
+  %ld5 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 5), align 1
+  %ld6 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 6), align 2
+  %ld7 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 7), align 1
+  %cvt0 = sitofp i8 %ld0 to float
+  %cvt1 = sitofp i8 %ld1 to float
+  %cvt2 = sitofp i8 %ld2 to float
+  %cvt3 = sitofp i8 %ld3 to float
+  %cvt4 = sitofp i8 %ld4 to float
+  %cvt5 = sitofp i8 %ld5 to float
+  %cvt6 = sitofp i8 %ld6 to float
+  %cvt7 = sitofp i8 %ld7 to float
+  store float %cvt0, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0), align 64
+  store float %cvt1, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1), align 4
+  store float %cvt2, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2), align 8
+  store float %cvt3, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3), align 4
+  store float %cvt4, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4), align 16
+  store float %cvt5, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5), align 4
+  store float %cvt6, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6), align 8
+  store float %cvt7, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7), align 4
+  ret void
+}
+
+define void @sitofp_16i8_16f32() #0 {
+; SSE-LABEL: @sitofp_16i8_16f32(
+; SSE-NEXT:    [[TMP1:%.*]] = load <4 x i8>, <4 x i8>* bitcast ([64 x i8]* @src8 to <4 x i8>*), align 64
+; SSE-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* bitcast (i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 4) to <4 x i8>*), align 4
+; SSE-NEXT:    [[TMP3:%.*]] = load <4 x i8>, <4 x i8>* bitcast (i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 8) to <4 x i8>*), align 8
+; SSE-NEXT:    [[TMP4:%.*]] = load <4 x i8>, <4 x i8>* bitcast (i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 12) to <4 x i8>*), align 4
+; SSE-NEXT:    [[TMP5:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; SSE-NEXT:    [[TMP6:%.*]] = sitofp <4 x i8> [[TMP2]] to <4 x float>
+; SSE-NEXT:    [[TMP7:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
+; SSE-NEXT:    [[TMP8:%.*]] = sitofp <4 x i8> [[TMP4]] to <4 x float>
+; SSE-NEXT:    store <4 x float> [[TMP5]], <4 x float>* bitcast ([16 x float]* @dst32 to <4 x float>*), align 64
+; SSE-NEXT:    store <4 x float> [[TMP6]], <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4) to <4 x float>*), align 16
+; SSE-NEXT:    store <4 x float> [[TMP7]], <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 8) to <4 x float>*), align 32
+; SSE-NEXT:    store <4 x float> [[TMP8]], <4 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 12) to <4 x float>*), align 16
+; SSE-NEXT:    ret void
+;
+; AVX256-LABEL: @sitofp_16i8_16f32(
+; AVX256-NEXT:    [[TMP1:%.*]] = load <8 x i8>, <8 x i8>* bitcast ([64 x i8]* @src8 to <8 x i8>*), align 64
+; AVX256-NEXT:    [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* bitcast (i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 8) to <8 x i8>*), align 8
+; AVX256-NEXT:    [[TMP3:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX256-NEXT:    [[TMP4:%.*]] = sitofp <8 x i8> [[TMP2]] to <8 x float>
+; AVX256-NEXT:    store <8 x float> [[TMP3]], <8 x float>* bitcast ([16 x float]* @dst32 to <8 x float>*), align 64
+; AVX256-NEXT:    store <8 x float> [[TMP4]], <8 x float>* bitcast (float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 8) to <8 x float>*), align 32
+; AVX256-NEXT:    ret void
+;
+; AVX512-LABEL: @sitofp_16i8_16f32(
+; AVX512-NEXT:    [[TMP1:%.*]] = load <16 x i8>, <16 x i8>* bitcast ([64 x i8]* @src8 to <16 x i8>*), align 64
+; AVX512-NEXT:    [[TMP2:%.*]] = sitofp <16 x i8> [[TMP1]] to <16 x float>
+; AVX512-NEXT:    store <16 x float> [[TMP2]], <16 x float>* bitcast ([16 x float]* @dst32 to <16 x float>*), align 64
+; AVX512-NEXT:    ret void
+;
+  %ld0  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 0 ), align 64
+  %ld1  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 1 ), align 1
+  %ld2  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 2 ), align 2
+  %ld3  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 3 ), align 1
+  %ld4  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 4 ), align 4
+  %ld5  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 5 ), align 1
+  %ld6  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 6 ), align 2
+  %ld7  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 7 ), align 1
+  %ld8  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 8 ), align 8
+  %ld9  = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 9 ), align 1
+  %ld10 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 10), align 2
+  %ld11 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 11), align 1
+  %ld12 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 12), align 4
+  %ld13 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 13), align 1
+  %ld14 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 14), align 2
+  %ld15 = load i8, i8* getelementptr inbounds ([64 x i8], [64 x i8]* @src8, i32 0, i64 15), align 1
+  %cvt0  = sitofp i8 %ld0  to float
+  %cvt1  = sitofp i8 %ld1  to float
+  %cvt2  = sitofp i8 %ld2  to float
+  %cvt3  = sitofp i8 %ld3  to float
+  %cvt4  = sitofp i8 %ld4  to float
+  %cvt5  = sitofp i8 %ld5  to float
+  %cvt6  = sitofp i8 %ld6  to float
+  %cvt7  = sitofp i8 %ld7  to float
+  %cvt8  = sitofp i8 %ld8  to float
+  %cvt9  = sitofp i8 %ld9  to float
+  %cvt10 = sitofp i8 %ld10 to float
+  %cvt11 = sitofp i8 %ld11 to float
+  %cvt12 = sitofp i8 %ld12 to float
+  %cvt13 = sitofp i8 %ld13 to float
+  %cvt14 = sitofp i8 %ld14 to float
+  %cvt15 = sitofp i8 %ld15 to float
+  store float %cvt0 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 0 ), align 64
+  store float %cvt1 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 1 ), align 4
+  store float %cvt2 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 2 ), align 8
+  store float %cvt3 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 3 ), align 4
+  store float %cvt4 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 4 ), align 16
+  store float %cvt5 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 5 ), align 4
+  store float %cvt6 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 6 ), align 8
+  store float %cvt7 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 7 ), align 4
+  store float %cvt8 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 8 ), align 32
+  store float %cvt9 , float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 9 ), align 4
+  store float %cvt10, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 10), align 8
+  store float %cvt11, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 11), align 4
+  store float %cvt12, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 12), align 16
+  store float %cvt13, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 13), align 4
+  store float %cvt14, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 14), align 8
+  store float %cvt15, float* getelementptr inbounds ([16 x float], [16 x float]* @dst32, i32 0, i64 15), align 4
+  ret void
+}
+
+;
+; SITOFP BUILDVECTOR
+;
+
+define <4 x double> @sitofp_4xi32_4f64(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
+; CHECK-LABEL: @sitofp_4xi32_4f64(
+; CHECK-NEXT:    [[CVT0:%.*]] = sitofp i32 [[A0:%.*]] to double
+; CHECK-NEXT:    [[CVT1:%.*]] = sitofp i32 [[A1:%.*]] to double
+; CHECK-NEXT:    [[CVT2:%.*]] = sitofp i32 [[A2:%.*]] to double
+; CHECK-NEXT:    [[CVT3:%.*]] = sitofp i32 [[A3:%.*]] to double
+; CHECK-NEXT:    [[RES0:%.*]] = insertelement <4 x double> poison, double [[CVT0]], i32 0
+; CHECK-NEXT:    [[RES1:%.*]] = insertelement <4 x double> [[RES0]], double [[CVT1]], i32 1
+; CHECK-NEXT:    [[RES2:%.*]] = insertelement <4 x double> [[RES1]], double [[CVT2]], i32 2
+; CHECK-NEXT:    [[RES3:%.*]] = insertelement <4 x double> [[RES2]], double [[CVT3]], i32 3
+; CHECK-NEXT:    ret <4 x double> [[RES3]]
+;
+  %cvt0 = sitofp i32 %a0 to double
+  %cvt1 = sitofp i32 %a1 to double
+  %cvt2 = sitofp i32 %a2 to double
+  %cvt3 = sitofp i32 %a3 to double
+  %res0 = insertelement <4 x double> poison, double %cvt0, i32 0
+  %res1 = insertelement <4 x double> %res0, double %cvt1, i32 1
+  %res2 = insertelement <4 x double> %res1, double %cvt2, i32 2
+  %res3 = insertelement <4 x double> %res2, double %cvt3, i32 3
+  ret <4 x double> %res3
+}
+
+define <4 x float> @sitofp_4xi32_4f32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
+; CHECK-LABEL: @sitofp_4xi32_4f32(
+; CHECK-NEXT:    [[CVT0:%.*]] = sitofp i32 [[A0:%.*]] to float
+; CHECK-NEXT:    [[CVT1:%.*]] = sitofp i32 [[A1:%.*]] to float
+; CHECK-NEXT:    [[CVT2:%.*]] = sitofp i32 [[A2:%.*]] to float
+; CHECK-NEXT:    [[CVT3:%.*]] = sitofp i32 [[A3:%.*]] to float
+; CHECK-NEXT:    [[RES0:%.*]] = insertelement <4 x float> poison, float [[CVT0]], i32 0
+; CHECK-NEXT:    [[RES1:%.*]] = insertelement <4 x float> [[RES0]], float [[CVT1]], i32 1
+; CHECK-NEXT:    [[RES2:%.*]] = insertelement <4 x float> [[RES1]], float [[CVT2]], i32 2
+; CHECK-NEXT:    [[RES3:%.*]] = insertelement <4 x float> [[RES2]], float [[CVT3]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[RES3]]
+;
+  %cvt0 = sitofp i32 %a0 to float
+  %cvt1 = sitofp i32 %a1 to float
+  %cvt2 = sitofp i32 %a2 to float
+  %cvt3 = sitofp i32 %a3 to float
+  %res0 = insertelement <4 x float> poison, float %cvt0, i32 0
+  %res1 = insertelement <4 x float> %res0, float %cvt1, i32 1
+  %res2 = insertelement <4 x float> %res1, float %cvt2, i32 2
+  %res3 = insertelement <4 x float> %res2, float %cvt3, i32 3
+  ret <4 x float> %res3
+}
+
+attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/value-bug-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/value-bug-inseltpoison.ll
new file mode 100644
index 0000000000000..8f815afc9bfe4
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/value-bug-inseltpoison.ll
@@ -0,0 +1,108 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer < %s -S -mtriple="x86_64-grtev3-linux-gnu" -mcpu=corei7-avx | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+; We used to crash on this example because we were building a constant
+; expression during vectorization and the vectorizer expects instructions
+; as elements of the vectorized tree.
+; PR19621
+
+define void @test() {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:  bb279:
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <2 x float> undef, float undef, i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x float> [[TMP0]], float undef, i32 1
+; CHECK-NEXT:    br label [[BB283:%.*]]
+; CHECK:       bb283:
+; CHECK-NEXT:    [[TMP2:%.*]] = phi <2 x float> [ undef, [[BB279:%.*]] ], [ [[TMP13:%.*]], [[EXIT:%.*]] ]
+; CHECK-NEXT:    [[TMP3:%.*]] = phi <2 x float> [ undef, [[BB279]] ], [ [[TMP1]], [[EXIT]] ]
+; CHECK-NEXT:    br label [[BB284:%.*]]
+; CHECK:       bb284:
+; CHECK-NEXT:    [[TMP4:%.*]] = fpext <2 x float> [[TMP2]] to <2 x double>
+; CHECK-NEXT:    [[TMP5:%.*]] = fsub <2 x double> [[TMP4]], undef
+; CHECK-NEXT:    [[TMP6:%.*]] = fsub <2 x double> [[TMP5]], undef
+; CHECK-NEXT:    br label [[BB21_I:%.*]]
+; CHECK:       bb21.i:
+; CHECK-NEXT:    br i1 undef, label [[BB22_I:%.*]], label [[EXIT]]
+; CHECK:       bb22.i:
+; CHECK-NEXT:    [[TMP7:%.*]] = fadd <2 x double> undef, [[TMP6]]
+; CHECK-NEXT:    br label [[BB32_I:%.*]]
+; CHECK:       bb32.i:
+; CHECK-NEXT:    [[TMP8:%.*]] = phi <2 x double> [ [[TMP7]], [[BB22_I]] ], [ zeroinitializer, [[BB32_I]] ]
+; CHECK-NEXT:    br i1 undef, label [[BB32_I]], label [[BB21_I]]
+; CHECK:       exit:
+; CHECK-NEXT:    [[TMP9:%.*]] = fpext <2 x float> [[TMP3]] to <2 x double>
+; CHECK-NEXT:    [[TMP10:%.*]] = fmul <2 x double> [[TMP9]], <double undef, double 0.000000e+00>
+; CHECK-NEXT:    [[TMP11:%.*]] = fadd <2 x double> undef, [[TMP10]]
+; CHECK-NEXT:    [[TMP12:%.*]] = fadd <2 x double> [[TMP11]], undef
+; CHECK-NEXT:    [[TMP13]] = fptrunc <2 x double> [[TMP12]] to <2 x float>
+; CHECK-NEXT:    br label [[BB283]]
+;
+bb279:
+  br label %bb283
+
+bb283:
+  %Av.sroa.8.0 = phi float [ undef, %bb279 ], [ %tmp315, %exit ]
+  %Av.sroa.5.0 = phi float [ undef, %bb279 ], [ %tmp319, %exit ]
+  %Av.sroa.3.0 = phi float [ undef, %bb279 ], [ %tmp307, %exit ]
+  %Av.sroa.0.0 = phi float [ undef, %bb279 ], [ %tmp317, %exit ]
+  br label %bb284
+
+bb284:
+  %tmp7.i = fpext float %Av.sroa.3.0 to double
+  %tmp8.i = fsub double %tmp7.i, undef
+  %tmp9.i = fsub double %tmp8.i, undef
+  %tmp17.i = fpext float %Av.sroa.8.0 to double
+  %tmp19.i = fsub double %tmp17.i, undef
+  %tmp20.i = fsub double %tmp19.i, undef
+  br label %bb21.i
+
+bb21.i:
+  br i1 undef, label %bb22.i, label %exit
+
+bb22.i:
+  %tmp24.i = fadd double undef, %tmp9.i
+  %tmp26.i = fadd double undef, %tmp20.i
+  br label %bb32.i
+
+bb32.i:
+  %xs.0.i = phi double [ %tmp24.i, %bb22.i ], [ 0.000000e+00, %bb32.i ]
+  %ys.0.i = phi double [ %tmp26.i, %bb22.i ], [ 0.000000e+00, %bb32.i ]
+  br i1 undef, label %bb32.i, label %bb21.i
+
+exit:
+  %tmp303 = fpext float %Av.sroa.0.0 to double
+  %tmp304 = fmul double %tmp303, undef
+  %tmp305 = fadd double undef, %tmp304
+  %tmp306 = fadd double %tmp305, undef
+  %tmp307 = fptrunc double %tmp306 to float
+  %tmp311 = fpext float %Av.sroa.5.0 to double
+  %tmp312 = fmul double %tmp311, 0.000000e+00
+  %tmp313 = fadd double undef, %tmp312
+  %tmp314 = fadd double %tmp313, undef
+  %tmp315 = fptrunc double %tmp314 to float
+  %tmp317 = fptrunc double undef to float
+  %tmp319 = fptrunc double undef to float
+  br label %bb283
+}
+
+; Make sure that we probably handle constant folded vectorized trees. The
+; vectorizer starts at the type (%t2, %t3) and wil constant fold the tree.
+; The code that handles insertelement instructions must handle this.
+define <4 x double> @constant_folding() {
+; CHECK-LABEL: @constant_folding(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x double> poison, double 1.000000e+00, i32 1
+; CHECK-NEXT:    [[I2:%.*]] = insertelement <4 x double> [[I1]], double 2.000000e+00, i32 0
+; CHECK-NEXT:    ret <4 x double> [[I2]]
+;
+entry:
+  %t0 = fadd double 1.000000e+00 , 0.000000e+00
+  %t1 = fadd double 1.000000e+00 , 1.000000e+00
+  %t2 = fmul double %t0, 1.000000e+00
+  %i1 = insertelement <4 x double> poison, double %t2, i32 1
+  %t3 = fmul double %t1, 1.000000e+00
+  %i2 = insertelement <4 x double> %i1, double %t3, i32 0
+  ret <4 x double> %i2
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
new file mode 100644
index 0000000000000..7f2243e8d6c3f
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vec_list_bias-inseltpoison.ll
@@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake -S | FileCheck %s
+
+; Check no vectorization triggered with any portion of
+; insertelement <8 x i32> instructions that build entire vector.
+; Vectorization triggered by cost bias caused by subtracting
+; the cost of entire "aggregate build" sequence while
+; building vectorizable tree from only a portion of it.
+
+define void @test(i32* nocapture %t2) {
+; CHECK-LABEL: @test(
+; CHECK-NEXT:    [[T3:%.*]] = load i32, i32* [[T2:%.*]], align 4
+; CHECK-NEXT:    [[T4:%.*]] = getelementptr inbounds i32, i32* [[T2]], i64 7
+; CHECK-NEXT:    [[T5:%.*]] = load i32, i32* [[T4]], align 4
+; CHECK-NEXT:    [[T8:%.*]] = getelementptr inbounds i32, i32* [[T2]], i64 1
+; CHECK-NEXT:    [[T9:%.*]] = load i32, i32* [[T8]], align 4
+; CHECK-NEXT:    [[T10:%.*]] = getelementptr inbounds i32, i32* [[T2]], i64 6
+; CHECK-NEXT:    [[T11:%.*]] = load i32, i32* [[T10]], align 4
+; CHECK-NEXT:    [[T14:%.*]] = getelementptr inbounds i32, i32* [[T2]], i64 2
+; CHECK-NEXT:    [[T15:%.*]] = load i32, i32* [[T14]], align 4
+; CHECK-NEXT:    [[T16:%.*]] = getelementptr inbounds i32, i32* [[T2]], i64 5
+; CHECK-NEXT:    [[T17:%.*]] = load i32, i32* [[T16]], align 4
+; CHECK-NEXT:    [[T20:%.*]] = getelementptr inbounds i32, i32* [[T2]], i64 3
+; CHECK-NEXT:    [[T21:%.*]] = load i32, i32* [[T20]], align 4
+; CHECK-NEXT:    [[T22:%.*]] = getelementptr inbounds i32, i32* [[T2]], i64 4
+; CHECK-NEXT:    [[T23:%.*]] = load i32, i32* [[T22]], align 4
+; CHECK-NEXT:    [[T24:%.*]] = add nsw i32 [[T23]], [[T21]]
+; CHECK-NEXT:    [[T25:%.*]] = sub nsw i32 [[T21]], [[T23]]
+; CHECK-NEXT:    [[T27:%.*]] = sub nsw i32 [[T3]], [[T24]]
+; CHECK-NEXT:    [[T28:%.*]] = add nsw i32 [[T15]], [[T9]]
+; CHECK-NEXT:    [[T29:%.*]] = sub nsw i32 [[T9]], [[T15]]
+; CHECK-NEXT:    [[T30:%.*]] = add nsw i32 [[T27]], [[T29]]
+; CHECK-NEXT:    [[T31:%.*]] = mul nsw i32 [[T30]], 4433
+; CHECK-NEXT:    [[T32:%.*]] = mul nsw i32 [[T27]], 6270
+; CHECK-NEXT:    [[T34:%.*]] = mul nsw i32 [[T29]], -15137
+; CHECK-NEXT:    [[T37:%.*]] = add nsw i32 [[T25]], [[T11]]
+; CHECK-NEXT:    [[T38:%.*]] = add nsw i32 [[T17]], [[T5]]
+; CHECK-NEXT:    [[T39:%.*]] = add nsw i32 [[T37]], [[T38]]
+; CHECK-NEXT:    [[T40:%.*]] = mul nsw i32 [[T39]], 9633
+; CHECK-NEXT:    [[T41:%.*]] = mul nsw i32 [[T25]], 2446
+; CHECK-NEXT:    [[T42:%.*]] = mul nsw i32 [[T17]], 16819
+; CHECK-NEXT:    [[T47:%.*]] = mul nsw i32 [[T37]], -16069
+; CHECK-NEXT:    [[T48:%.*]] = mul nsw i32 [[T38]], -3196
+; CHECK-NEXT:    [[T49:%.*]] = add nsw i32 [[T40]], [[T47]]
+; CHECK-NEXT:    [[T50:%.*]] = add nsw i32 [[T40]], [[T48]]
+; CHECK-NEXT:    [[T65:%.*]] = insertelement <8 x i32> poison, i32 [[T28]], i32 0
+; CHECK-NEXT:    [[T66:%.*]] = insertelement <8 x i32> [[T65]], i32 [[T50]], i32 1
+; CHECK-NEXT:    [[T67:%.*]] = insertelement <8 x i32> [[T66]], i32 [[T32]], i32 2
+; CHECK-NEXT:    [[T68:%.*]] = insertelement <8 x i32> [[T67]], i32 [[T49]], i32 3
+; CHECK-NEXT:    [[T69:%.*]] = insertelement <8 x i32> [[T68]], i32 [[T28]], i32 4
+; CHECK-NEXT:    [[T70:%.*]] = insertelement <8 x i32> [[T69]], i32 [[T50]], i32 5
+; CHECK-NEXT:    [[T71:%.*]] = insertelement <8 x i32> [[T70]], i32 [[T34]], i32 6
+; CHECK-NEXT:    [[T72:%.*]] = insertelement <8 x i32> [[T71]], i32 [[T49]], i32 7
+; CHECK-NEXT:    [[T76:%.*]] = shl <8 x i32> [[T72]], <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
+; CHECK-NEXT:    [[T79:%.*]] = bitcast i32* [[T2]] to <8 x i32>*
+; CHECK-NEXT:    store <8 x i32> [[T76]], <8 x i32>* [[T79]], align 4
+; CHECK-NEXT:    ret void
+;
+  %t3 = load i32, i32* %t2, align 4
+  %t4 = getelementptr inbounds i32, i32* %t2, i64 7
+  %t5 = load i32, i32* %t4, align 4
+  %t8 = getelementptr inbounds i32, i32* %t2, i64 1
+  %t9 = load i32, i32* %t8, align 4
+  %t10 = getelementptr inbounds i32, i32* %t2, i64 6
+  %t11 = load i32, i32* %t10, align 4
+  %t14 = getelementptr inbounds i32, i32* %t2, i64 2
+  %t15 = load i32, i32* %t14, align 4
+  %t16 = getelementptr inbounds i32, i32* %t2, i64 5
+  %t17 = load i32, i32* %t16, align 4
+  %t20 = getelementptr inbounds i32, i32* %t2, i64 3
+  %t21 = load i32, i32* %t20, align 4
+  %t22 = getelementptr inbounds i32, i32* %t2, i64 4
+  %t23 = load i32, i32* %t22, align 4
+  %t24 = add nsw i32 %t23, %t21
+  %t25 = sub nsw i32 %t21, %t23
+  %t27 = sub nsw i32 %t3, %t24
+  %t28 = add nsw i32 %t15, %t9
+  %t29 = sub nsw i32 %t9, %t15
+  %t30 = add nsw i32 %t27, %t29
+  %t31 = mul nsw i32 %t30, 4433
+  %t32 = mul nsw i32 %t27, 6270
+  %t34 = mul nsw i32 %t29, -15137
+  %t37 = add nsw i32 %t25, %t11
+  %t38 = add nsw i32 %t17, %t5
+  %t39 = add nsw i32 %t37, %t38
+  %t40 = mul nsw i32 %t39, 9633
+  %t41 = mul nsw i32 %t25, 2446
+  %t42 = mul nsw i32 %t17, 16819
+  %t47 = mul nsw i32 %t37, -16069
+  %t48 = mul nsw i32 %t38, -3196
+  %t49 = add nsw i32 %t40, %t47
+  %t50 = add nsw i32 %t40, %t48
+  %t65 = insertelement <8 x i32> poison, i32 %t28, i32 0
+  %t66 = insertelement <8 x i32> %t65, i32 %t50, i32 1
+  %t67 = insertelement <8 x i32> %t66, i32 %t32, i32 2
+  %t68 = insertelement <8 x i32> %t67, i32 %t49, i32 3
+  %t69 = insertelement <8 x i32> %t68, i32 %t28, i32 4
+  %t70 = insertelement <8 x i32> %t69, i32 %t50, i32 5
+  %t71 = insertelement <8 x i32> %t70, i32 %t34, i32 6
+  %t72 = insertelement <8 x i32> %t71, i32 %t49, i32 7
+  %t76 = shl <8 x i32> %t72, <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
+  %t79 = bitcast i32* %t2 to <8 x i32>*
+  store <8 x i32> %t76, <8 x i32>* %t79, align 4
+  ret void
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/zext-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/zext-inseltpoison.ll
new file mode 100644
index 0000000000000..c16a988565ba7
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/zext-inseltpoison.ll
@@ -0,0 +1,1123 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -mtriple=x86_64-unknown -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=SSE2
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=slm -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=SLM
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=knl -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skx -mattr=+avx512bw -basic-aa -slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
+
+;
+; vXi8
+;
+
+define <2 x i64> @loadext_2i8_to_2i64(i8* %p0) {
+; SSE2-LABEL: @loadext_2i8_to_2i64(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <2 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <2 x i8>, <2 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i64>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[TMP5]], i32 1
+; SSE2-NEXT:    ret <2 x i64> [[V1]]
+;
+; SLM-LABEL: @loadext_2i8_to_2i64(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i8 [[I0]] to i64
+; SLM-NEXT:    [[X1:%.*]] = zext i8 [[I1]] to i64
+; SLM-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[X1]], i32 1
+; SLM-NEXT:    ret <2 x i64> [[V1]]
+;
+; AVX-LABEL: @loadext_2i8_to_2i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <2 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <2 x i8>, <2 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <2 x i8> [[TMP2]] to <2 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    ret <2 x i64> [[V1]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %x0 = zext i8 %i0 to i64
+  %x1 = zext i8 %i1 to i64
+  %v0 = insertelement <2 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <2 x i64>   %v0, i64 %x1, i32 1
+  ret <2 x i64> %v1
+}
+
+define <4 x i32> @loadext_4i8_to_4i32(i8* %p0) {
+; SSE2-LABEL: @loadext_4i8_to_4i32(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <4 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[TMP7]], i32 3
+; SSE2-NEXT:    ret <4 x i32> [[V3]]
+;
+; SLM-LABEL: @loadext_4i8_to_4i32(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i8 [[I0]] to i32
+; SLM-NEXT:    [[X1:%.*]] = zext i8 [[I1]] to i32
+; SLM-NEXT:    [[X2:%.*]] = zext i8 [[I2]] to i32
+; SLM-NEXT:    [[X3:%.*]] = zext i8 [[I3]] to i32
+; SLM-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[X3]], i32 3
+; SLM-NEXT:    ret <4 x i32> [[V3]]
+;
+; AVX-LABEL: @loadext_4i8_to_4i32(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <4 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i32> [[V3]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2 = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3 = getelementptr inbounds i8, i8* %p0, i64 3
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %i2 = load i8, i8* %p2, align 1
+  %i3 = load i8, i8* %p3, align 1
+  %x0 = zext i8 %i0 to i32
+  %x1 = zext i8 %i1 to i32
+  %x2 = zext i8 %i2 to i32
+  %x3 = zext i8 %i3 to i32
+  %v0 = insertelement <4 x i32> poison, i32 %x0, i32 0
+  %v1 = insertelement <4 x i32>   %v0, i32 %x1, i32 1
+  %v2 = insertelement <4 x i32>   %v1, i32 %x2, i32 2
+  %v3 = insertelement <4 x i32>   %v2, i32 %x3, i32 3
+  ret <4 x i32> %v3
+}
+
+define <4 x i64> @loadext_4i8_to_4i64(i8* %p0) {
+; SSE2-LABEL: @loadext_4i8_to_4i64(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <4 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i64>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[TMP7]], i32 3
+; SSE2-NEXT:    ret <4 x i64> [[V3]]
+;
+; SLM-LABEL: @loadext_4i8_to_4i64(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i8 [[I0]] to i64
+; SLM-NEXT:    [[X1:%.*]] = zext i8 [[I1]] to i64
+; SLM-NEXT:    [[X2:%.*]] = zext i8 [[I2]] to i64
+; SLM-NEXT:    [[X3:%.*]] = zext i8 [[I3]] to i64
+; SLM-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[X3]], i32 3
+; SLM-NEXT:    ret <4 x i64> [[V3]]
+;
+; AVX-LABEL: @loadext_4i8_to_4i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <4 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i64> [[V3]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2 = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3 = getelementptr inbounds i8, i8* %p0, i64 3
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %i2 = load i8, i8* %p2, align 1
+  %i3 = load i8, i8* %p3, align 1
+  %x0 = zext i8 %i0 to i64
+  %x1 = zext i8 %i1 to i64
+  %x2 = zext i8 %i2 to i64
+  %x3 = zext i8 %i3 to i64
+  %v0 = insertelement <4 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <4 x i64>   %v0, i64 %x1, i32 1
+  %v2 = insertelement <4 x i64>   %v1, i64 %x2, i32 2
+  %v3 = insertelement <4 x i64>   %v2, i64 %x3, i32 3
+  ret <4 x i64> %v3
+}
+
+define <8 x i16> @loadext_8i8_to_8i16(i8* %p0) {
+; SSE2-LABEL: @loadext_8i8_to_8i16(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE2-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SSE2-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SSE2-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SSE2-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <8 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i16>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <8 x i16> [[V0]], i16 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <8 x i16> [[V1]], i16 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <8 x i16> [[V2]], i16 [[TMP7]], i32 3
+; SSE2-NEXT:    [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; SSE2-NEXT:    [[V4:%.*]] = insertelement <8 x i16> [[V3]], i16 [[TMP8]], i32 4
+; SSE2-NEXT:    [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; SSE2-NEXT:    [[V5:%.*]] = insertelement <8 x i16> [[V4]], i16 [[TMP9]], i32 5
+; SSE2-NEXT:    [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; SSE2-NEXT:    [[V6:%.*]] = insertelement <8 x i16> [[V5]], i16 [[TMP10]], i32 6
+; SSE2-NEXT:    [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; SSE2-NEXT:    [[V7:%.*]] = insertelement <8 x i16> [[V6]], i16 [[TMP11]], i32 7
+; SSE2-NEXT:    ret <8 x i16> [[V7]]
+;
+; SLM-LABEL: @loadext_8i8_to_8i16(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SLM-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SLM-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SLM-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SLM-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SLM-NEXT:    [[I4:%.*]] = load i8, i8* [[P4]], align 1
+; SLM-NEXT:    [[I5:%.*]] = load i8, i8* [[P5]], align 1
+; SLM-NEXT:    [[I6:%.*]] = load i8, i8* [[P6]], align 1
+; SLM-NEXT:    [[I7:%.*]] = load i8, i8* [[P7]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i8 [[I0]] to i16
+; SLM-NEXT:    [[X1:%.*]] = zext i8 [[I1]] to i16
+; SLM-NEXT:    [[X2:%.*]] = zext i8 [[I2]] to i16
+; SLM-NEXT:    [[X3:%.*]] = zext i8 [[I3]] to i16
+; SLM-NEXT:    [[X4:%.*]] = zext i8 [[I4]] to i16
+; SLM-NEXT:    [[X5:%.*]] = zext i8 [[I5]] to i16
+; SLM-NEXT:    [[X6:%.*]] = zext i8 [[I6]] to i16
+; SLM-NEXT:    [[X7:%.*]] = zext i8 [[I7]] to i16
+; SLM-NEXT:    [[V0:%.*]] = insertelement <8 x i16> poison, i16 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <8 x i16> [[V0]], i16 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <8 x i16> [[V1]], i16 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <8 x i16> [[V2]], i16 [[X3]], i32 3
+; SLM-NEXT:    [[V4:%.*]] = insertelement <8 x i16> [[V3]], i16 [[X4]], i32 4
+; SLM-NEXT:    [[V5:%.*]] = insertelement <8 x i16> [[V4]], i16 [[X5]], i32 5
+; SLM-NEXT:    [[V6:%.*]] = insertelement <8 x i16> [[V5]], i16 [[X6]], i32 6
+; SLM-NEXT:    [[V7:%.*]] = insertelement <8 x i16> [[V6]], i16 [[X7]], i32 7
+; SLM-NEXT:    ret <8 x i16> [[V7]]
+;
+; AVX-LABEL: @loadext_8i8_to_8i16(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; AVX-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; AVX-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; AVX-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <8 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i16>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <8 x i16> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <8 x i16> poison, i16 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <8 x i16> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <8 x i16> [[V0]], i16 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <8 x i16> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <8 x i16> [[V1]], i16 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <8 x i16> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <8 x i16> [[V2]], i16 [[TMP7]], i32 3
+; AVX-NEXT:    [[TMP8:%.*]] = extractelement <8 x i16> [[TMP3]], i32 4
+; AVX-NEXT:    [[V4:%.*]] = insertelement <8 x i16> [[V3]], i16 [[TMP8]], i32 4
+; AVX-NEXT:    [[TMP9:%.*]] = extractelement <8 x i16> [[TMP3]], i32 5
+; AVX-NEXT:    [[V5:%.*]] = insertelement <8 x i16> [[V4]], i16 [[TMP9]], i32 5
+; AVX-NEXT:    [[TMP10:%.*]] = extractelement <8 x i16> [[TMP3]], i32 6
+; AVX-NEXT:    [[V6:%.*]] = insertelement <8 x i16> [[V5]], i16 [[TMP10]], i32 6
+; AVX-NEXT:    [[TMP11:%.*]] = extractelement <8 x i16> [[TMP3]], i32 7
+; AVX-NEXT:    [[V7:%.*]] = insertelement <8 x i16> [[V6]], i16 [[TMP11]], i32 7
+; AVX-NEXT:    ret <8 x i16> [[V7]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2 = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3 = getelementptr inbounds i8, i8* %p0, i64 3
+  %p4 = getelementptr inbounds i8, i8* %p0, i64 4
+  %p5 = getelementptr inbounds i8, i8* %p0, i64 5
+  %p6 = getelementptr inbounds i8, i8* %p0, i64 6
+  %p7 = getelementptr inbounds i8, i8* %p0, i64 7
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %i2 = load i8, i8* %p2, align 1
+  %i3 = load i8, i8* %p3, align 1
+  %i4 = load i8, i8* %p4, align 1
+  %i5 = load i8, i8* %p5, align 1
+  %i6 = load i8, i8* %p6, align 1
+  %i7 = load i8, i8* %p7, align 1
+  %x0 = zext i8 %i0 to i16
+  %x1 = zext i8 %i1 to i16
+  %x2 = zext i8 %i2 to i16
+  %x3 = zext i8 %i3 to i16
+  %x4 = zext i8 %i4 to i16
+  %x5 = zext i8 %i5 to i16
+  %x6 = zext i8 %i6 to i16
+  %x7 = zext i8 %i7 to i16
+  %v0 = insertelement <8 x i16> poison, i16 %x0, i32 0
+  %v1 = insertelement <8 x i16>   %v0, i16 %x1, i32 1
+  %v2 = insertelement <8 x i16>   %v1, i16 %x2, i32 2
+  %v3 = insertelement <8 x i16>   %v2, i16 %x3, i32 3
+  %v4 = insertelement <8 x i16>   %v3, i16 %x4, i32 4
+  %v5 = insertelement <8 x i16>   %v4, i16 %x5, i32 5
+  %v6 = insertelement <8 x i16>   %v5, i16 %x6, i32 6
+  %v7 = insertelement <8 x i16>   %v6, i16 %x7, i32 7
+  ret <8 x i16> %v7
+}
+
+define <8 x i32> @loadext_8i8_to_8i32(i8* %p0) {
+; SSE2-LABEL: @loadext_8i8_to_8i32(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE2-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SSE2-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SSE2-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SSE2-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <8 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i32>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <8 x i32> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <8 x i32> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[TMP7]], i32 3
+; SSE2-NEXT:    [[TMP8:%.*]] = extractelement <8 x i32> [[TMP3]], i32 4
+; SSE2-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[TMP8]], i32 4
+; SSE2-NEXT:    [[TMP9:%.*]] = extractelement <8 x i32> [[TMP3]], i32 5
+; SSE2-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[TMP9]], i32 5
+; SSE2-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP3]], i32 6
+; SSE2-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[TMP10]], i32 6
+; SSE2-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP3]], i32 7
+; SSE2-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[TMP11]], i32 7
+; SSE2-NEXT:    ret <8 x i32> [[V7]]
+;
+; SLM-LABEL: @loadext_8i8_to_8i32(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SLM-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SLM-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SLM-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SLM-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SLM-NEXT:    [[I4:%.*]] = load i8, i8* [[P4]], align 1
+; SLM-NEXT:    [[I5:%.*]] = load i8, i8* [[P5]], align 1
+; SLM-NEXT:    [[I6:%.*]] = load i8, i8* [[P6]], align 1
+; SLM-NEXT:    [[I7:%.*]] = load i8, i8* [[P7]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i8 [[I0]] to i32
+; SLM-NEXT:    [[X1:%.*]] = zext i8 [[I1]] to i32
+; SLM-NEXT:    [[X2:%.*]] = zext i8 [[I2]] to i32
+; SLM-NEXT:    [[X3:%.*]] = zext i8 [[I3]] to i32
+; SLM-NEXT:    [[X4:%.*]] = zext i8 [[I4]] to i32
+; SLM-NEXT:    [[X5:%.*]] = zext i8 [[I5]] to i32
+; SLM-NEXT:    [[X6:%.*]] = zext i8 [[I6]] to i32
+; SLM-NEXT:    [[X7:%.*]] = zext i8 [[I7]] to i32
+; SLM-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[X3]], i32 3
+; SLM-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[X4]], i32 4
+; SLM-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[X5]], i32 5
+; SLM-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[X6]], i32 6
+; SLM-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[X7]], i32 7
+; SLM-NEXT:    ret <8 x i32> [[V7]]
+;
+; AVX-LABEL: @loadext_8i8_to_8i32(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; AVX-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; AVX-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; AVX-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <8 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i32>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <8 x i32> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <8 x i32> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[TMP7]], i32 3
+; AVX-NEXT:    [[TMP8:%.*]] = extractelement <8 x i32> [[TMP3]], i32 4
+; AVX-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[TMP8]], i32 4
+; AVX-NEXT:    [[TMP9:%.*]] = extractelement <8 x i32> [[TMP3]], i32 5
+; AVX-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[TMP9]], i32 5
+; AVX-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP3]], i32 6
+; AVX-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[TMP10]], i32 6
+; AVX-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP3]], i32 7
+; AVX-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[TMP11]], i32 7
+; AVX-NEXT:    ret <8 x i32> [[V7]]
+;
+  %p1 = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2 = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3 = getelementptr inbounds i8, i8* %p0, i64 3
+  %p4 = getelementptr inbounds i8, i8* %p0, i64 4
+  %p5 = getelementptr inbounds i8, i8* %p0, i64 5
+  %p6 = getelementptr inbounds i8, i8* %p0, i64 6
+  %p7 = getelementptr inbounds i8, i8* %p0, i64 7
+  %i0 = load i8, i8* %p0, align 1
+  %i1 = load i8, i8* %p1, align 1
+  %i2 = load i8, i8* %p2, align 1
+  %i3 = load i8, i8* %p3, align 1
+  %i4 = load i8, i8* %p4, align 1
+  %i5 = load i8, i8* %p5, align 1
+  %i6 = load i8, i8* %p6, align 1
+  %i7 = load i8, i8* %p7, align 1
+  %x0 = zext i8 %i0 to i32
+  %x1 = zext i8 %i1 to i32
+  %x2 = zext i8 %i2 to i32
+  %x3 = zext i8 %i3 to i32
+  %x4 = zext i8 %i4 to i32
+  %x5 = zext i8 %i5 to i32
+  %x6 = zext i8 %i6 to i32
+  %x7 = zext i8 %i7 to i32
+  %v0 = insertelement <8 x i32> poison, i32 %x0, i32 0
+  %v1 = insertelement <8 x i32>   %v0, i32 %x1, i32 1
+  %v2 = insertelement <8 x i32>   %v1, i32 %x2, i32 2
+  %v3 = insertelement <8 x i32>   %v2, i32 %x3, i32 3
+  %v4 = insertelement <8 x i32>   %v3, i32 %x4, i32 4
+  %v5 = insertelement <8 x i32>   %v4, i32 %x5, i32 5
+  %v6 = insertelement <8 x i32>   %v5, i32 %x6, i32 6
+  %v7 = insertelement <8 x i32>   %v6, i32 %x7, i32 7
+  ret <8 x i32> %v7
+}
+
+define <16 x i16> @loadext_16i8_to_16i16(i8* %p0) {
+; SSE2-LABEL: @loadext_16i8_to_16i16(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SSE2-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SSE2-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SSE2-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SSE2-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SSE2-NEXT:    [[P8:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 8
+; SSE2-NEXT:    [[P9:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 9
+; SSE2-NEXT:    [[P10:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 10
+; SSE2-NEXT:    [[P11:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 11
+; SSE2-NEXT:    [[P12:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 12
+; SSE2-NEXT:    [[P13:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 13
+; SSE2-NEXT:    [[P14:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 14
+; SSE2-NEXT:    [[P15:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 15
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <16 x i8>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <16 x i8> [[TMP2]] to <16 x i16>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <16 x i16> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <16 x i16> poison, i16 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <16 x i16> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <16 x i16> [[V0]], i16 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <16 x i16> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <16 x i16> [[V1]], i16 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <16 x i16> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <16 x i16> [[V2]], i16 [[TMP7]], i32 3
+; SSE2-NEXT:    [[TMP8:%.*]] = extractelement <16 x i16> [[TMP3]], i32 4
+; SSE2-NEXT:    [[V4:%.*]] = insertelement <16 x i16> [[V3]], i16 [[TMP8]], i32 4
+; SSE2-NEXT:    [[TMP9:%.*]] = extractelement <16 x i16> [[TMP3]], i32 5
+; SSE2-NEXT:    [[V5:%.*]] = insertelement <16 x i16> [[V4]], i16 [[TMP9]], i32 5
+; SSE2-NEXT:    [[TMP10:%.*]] = extractelement <16 x i16> [[TMP3]], i32 6
+; SSE2-NEXT:    [[V6:%.*]] = insertelement <16 x i16> [[V5]], i16 [[TMP10]], i32 6
+; SSE2-NEXT:    [[TMP11:%.*]] = extractelement <16 x i16> [[TMP3]], i32 7
+; SSE2-NEXT:    [[V7:%.*]] = insertelement <16 x i16> [[V6]], i16 [[TMP11]], i32 7
+; SSE2-NEXT:    [[TMP12:%.*]] = extractelement <16 x i16> [[TMP3]], i32 8
+; SSE2-NEXT:    [[V8:%.*]] = insertelement <16 x i16> [[V7]], i16 [[TMP12]], i32 8
+; SSE2-NEXT:    [[TMP13:%.*]] = extractelement <16 x i16> [[TMP3]], i32 9
+; SSE2-NEXT:    [[V9:%.*]] = insertelement <16 x i16> [[V8]], i16 [[TMP13]], i32 9
+; SSE2-NEXT:    [[TMP14:%.*]] = extractelement <16 x i16> [[TMP3]], i32 10
+; SSE2-NEXT:    [[V10:%.*]] = insertelement <16 x i16> [[V9]], i16 [[TMP14]], i32 10
+; SSE2-NEXT:    [[TMP15:%.*]] = extractelement <16 x i16> [[TMP3]], i32 11
+; SSE2-NEXT:    [[V11:%.*]] = insertelement <16 x i16> [[V10]], i16 [[TMP15]], i32 11
+; SSE2-NEXT:    [[TMP16:%.*]] = extractelement <16 x i16> [[TMP3]], i32 12
+; SSE2-NEXT:    [[V12:%.*]] = insertelement <16 x i16> [[V11]], i16 [[TMP16]], i32 12
+; SSE2-NEXT:    [[TMP17:%.*]] = extractelement <16 x i16> [[TMP3]], i32 13
+; SSE2-NEXT:    [[V13:%.*]] = insertelement <16 x i16> [[V12]], i16 [[TMP17]], i32 13
+; SSE2-NEXT:    [[TMP18:%.*]] = extractelement <16 x i16> [[TMP3]], i32 14
+; SSE2-NEXT:    [[V14:%.*]] = insertelement <16 x i16> [[V13]], i16 [[TMP18]], i32 14
+; SSE2-NEXT:    [[TMP19:%.*]] = extractelement <16 x i16> [[TMP3]], i32 15
+; SSE2-NEXT:    [[V15:%.*]] = insertelement <16 x i16> [[V14]], i16 [[TMP19]], i32 15
+; SSE2-NEXT:    ret <16 x i16> [[V15]]
+;
+; SLM-LABEL: @loadext_16i8_to_16i16(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; SLM-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; SLM-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; SLM-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; SLM-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; SLM-NEXT:    [[P8:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 8
+; SLM-NEXT:    [[P9:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 9
+; SLM-NEXT:    [[P10:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 10
+; SLM-NEXT:    [[P11:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 11
+; SLM-NEXT:    [[P12:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 12
+; SLM-NEXT:    [[P13:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 13
+; SLM-NEXT:    [[P14:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 14
+; SLM-NEXT:    [[P15:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 15
+; SLM-NEXT:    [[I0:%.*]] = load i8, i8* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i8, i8* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i8, i8* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i8, i8* [[P3]], align 1
+; SLM-NEXT:    [[I4:%.*]] = load i8, i8* [[P4]], align 1
+; SLM-NEXT:    [[I5:%.*]] = load i8, i8* [[P5]], align 1
+; SLM-NEXT:    [[I6:%.*]] = load i8, i8* [[P6]], align 1
+; SLM-NEXT:    [[I7:%.*]] = load i8, i8* [[P7]], align 1
+; SLM-NEXT:    [[I8:%.*]] = load i8, i8* [[P8]], align 1
+; SLM-NEXT:    [[I9:%.*]] = load i8, i8* [[P9]], align 1
+; SLM-NEXT:    [[I10:%.*]] = load i8, i8* [[P10]], align 1
+; SLM-NEXT:    [[I11:%.*]] = load i8, i8* [[P11]], align 1
+; SLM-NEXT:    [[I12:%.*]] = load i8, i8* [[P12]], align 1
+; SLM-NEXT:    [[I13:%.*]] = load i8, i8* [[P13]], align 1
+; SLM-NEXT:    [[I14:%.*]] = load i8, i8* [[P14]], align 1
+; SLM-NEXT:    [[I15:%.*]] = load i8, i8* [[P15]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i8 [[I0]] to i16
+; SLM-NEXT:    [[X1:%.*]] = zext i8 [[I1]] to i16
+; SLM-NEXT:    [[X2:%.*]] = zext i8 [[I2]] to i16
+; SLM-NEXT:    [[X3:%.*]] = zext i8 [[I3]] to i16
+; SLM-NEXT:    [[X4:%.*]] = zext i8 [[I4]] to i16
+; SLM-NEXT:    [[X5:%.*]] = zext i8 [[I5]] to i16
+; SLM-NEXT:    [[X6:%.*]] = zext i8 [[I6]] to i16
+; SLM-NEXT:    [[X7:%.*]] = zext i8 [[I7]] to i16
+; SLM-NEXT:    [[X8:%.*]] = zext i8 [[I8]] to i16
+; SLM-NEXT:    [[X9:%.*]] = zext i8 [[I9]] to i16
+; SLM-NEXT:    [[X10:%.*]] = zext i8 [[I10]] to i16
+; SLM-NEXT:    [[X11:%.*]] = zext i8 [[I11]] to i16
+; SLM-NEXT:    [[X12:%.*]] = zext i8 [[I12]] to i16
+; SLM-NEXT:    [[X13:%.*]] = zext i8 [[I13]] to i16
+; SLM-NEXT:    [[X14:%.*]] = zext i8 [[I14]] to i16
+; SLM-NEXT:    [[X15:%.*]] = zext i8 [[I15]] to i16
+; SLM-NEXT:    [[V0:%.*]] = insertelement <16 x i16> poison, i16 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <16 x i16> [[V0]], i16 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <16 x i16> [[V1]], i16 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <16 x i16> [[V2]], i16 [[X3]], i32 3
+; SLM-NEXT:    [[V4:%.*]] = insertelement <16 x i16> [[V3]], i16 [[X4]], i32 4
+; SLM-NEXT:    [[V5:%.*]] = insertelement <16 x i16> [[V4]], i16 [[X5]], i32 5
+; SLM-NEXT:    [[V6:%.*]] = insertelement <16 x i16> [[V5]], i16 [[X6]], i32 6
+; SLM-NEXT:    [[V7:%.*]] = insertelement <16 x i16> [[V6]], i16 [[X7]], i32 7
+; SLM-NEXT:    [[V8:%.*]] = insertelement <16 x i16> [[V7]], i16 [[X8]], i32 8
+; SLM-NEXT:    [[V9:%.*]] = insertelement <16 x i16> [[V8]], i16 [[X9]], i32 9
+; SLM-NEXT:    [[V10:%.*]] = insertelement <16 x i16> [[V9]], i16 [[X10]], i32 10
+; SLM-NEXT:    [[V11:%.*]] = insertelement <16 x i16> [[V10]], i16 [[X11]], i32 11
+; SLM-NEXT:    [[V12:%.*]] = insertelement <16 x i16> [[V11]], i16 [[X12]], i32 12
+; SLM-NEXT:    [[V13:%.*]] = insertelement <16 x i16> [[V12]], i16 [[X13]], i32 13
+; SLM-NEXT:    [[V14:%.*]] = insertelement <16 x i16> [[V13]], i16 [[X14]], i32 14
+; SLM-NEXT:    [[V15:%.*]] = insertelement <16 x i16> [[V14]], i16 [[X15]], i32 15
+; SLM-NEXT:    ret <16 x i16> [[V15]]
+;
+; AVX-LABEL: @loadext_16i8_to_16i16(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, i8* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 3
+; AVX-NEXT:    [[P4:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 4
+; AVX-NEXT:    [[P5:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 5
+; AVX-NEXT:    [[P6:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 6
+; AVX-NEXT:    [[P7:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 7
+; AVX-NEXT:    [[P8:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 8
+; AVX-NEXT:    [[P9:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 9
+; AVX-NEXT:    [[P10:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 10
+; AVX-NEXT:    [[P11:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 11
+; AVX-NEXT:    [[P12:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 12
+; AVX-NEXT:    [[P13:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 13
+; AVX-NEXT:    [[P14:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 14
+; AVX-NEXT:    [[P15:%.*]] = getelementptr inbounds i8, i8* [[P0]], i64 15
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i8* [[P0]] to <16 x i8>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <16 x i8> [[TMP2]] to <16 x i16>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <16 x i16> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <16 x i16> poison, i16 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <16 x i16> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <16 x i16> [[V0]], i16 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <16 x i16> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <16 x i16> [[V1]], i16 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <16 x i16> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <16 x i16> [[V2]], i16 [[TMP7]], i32 3
+; AVX-NEXT:    [[TMP8:%.*]] = extractelement <16 x i16> [[TMP3]], i32 4
+; AVX-NEXT:    [[V4:%.*]] = insertelement <16 x i16> [[V3]], i16 [[TMP8]], i32 4
+; AVX-NEXT:    [[TMP9:%.*]] = extractelement <16 x i16> [[TMP3]], i32 5
+; AVX-NEXT:    [[V5:%.*]] = insertelement <16 x i16> [[V4]], i16 [[TMP9]], i32 5
+; AVX-NEXT:    [[TMP10:%.*]] = extractelement <16 x i16> [[TMP3]], i32 6
+; AVX-NEXT:    [[V6:%.*]] = insertelement <16 x i16> [[V5]], i16 [[TMP10]], i32 6
+; AVX-NEXT:    [[TMP11:%.*]] = extractelement <16 x i16> [[TMP3]], i32 7
+; AVX-NEXT:    [[V7:%.*]] = insertelement <16 x i16> [[V6]], i16 [[TMP11]], i32 7
+; AVX-NEXT:    [[TMP12:%.*]] = extractelement <16 x i16> [[TMP3]], i32 8
+; AVX-NEXT:    [[V8:%.*]] = insertelement <16 x i16> [[V7]], i16 [[TMP12]], i32 8
+; AVX-NEXT:    [[TMP13:%.*]] = extractelement <16 x i16> [[TMP3]], i32 9
+; AVX-NEXT:    [[V9:%.*]] = insertelement <16 x i16> [[V8]], i16 [[TMP13]], i32 9
+; AVX-NEXT:    [[TMP14:%.*]] = extractelement <16 x i16> [[TMP3]], i32 10
+; AVX-NEXT:    [[V10:%.*]] = insertelement <16 x i16> [[V9]], i16 [[TMP14]], i32 10
+; AVX-NEXT:    [[TMP15:%.*]] = extractelement <16 x i16> [[TMP3]], i32 11
+; AVX-NEXT:    [[V11:%.*]] = insertelement <16 x i16> [[V10]], i16 [[TMP15]], i32 11
+; AVX-NEXT:    [[TMP16:%.*]] = extractelement <16 x i16> [[TMP3]], i32 12
+; AVX-NEXT:    [[V12:%.*]] = insertelement <16 x i16> [[V11]], i16 [[TMP16]], i32 12
+; AVX-NEXT:    [[TMP17:%.*]] = extractelement <16 x i16> [[TMP3]], i32 13
+; AVX-NEXT:    [[V13:%.*]] = insertelement <16 x i16> [[V12]], i16 [[TMP17]], i32 13
+; AVX-NEXT:    [[TMP18:%.*]] = extractelement <16 x i16> [[TMP3]], i32 14
+; AVX-NEXT:    [[V14:%.*]] = insertelement <16 x i16> [[V13]], i16 [[TMP18]], i32 14
+; AVX-NEXT:    [[TMP19:%.*]] = extractelement <16 x i16> [[TMP3]], i32 15
+; AVX-NEXT:    [[V15:%.*]] = insertelement <16 x i16> [[V14]], i16 [[TMP19]], i32 15
+; AVX-NEXT:    ret <16 x i16> [[V15]]
+;
+  %p1  = getelementptr inbounds i8, i8* %p0, i64 1
+  %p2  = getelementptr inbounds i8, i8* %p0, i64 2
+  %p3  = getelementptr inbounds i8, i8* %p0, i64 3
+  %p4  = getelementptr inbounds i8, i8* %p0, i64 4
+  %p5  = getelementptr inbounds i8, i8* %p0, i64 5
+  %p6  = getelementptr inbounds i8, i8* %p0, i64 6
+  %p7  = getelementptr inbounds i8, i8* %p0, i64 7
+  %p8  = getelementptr inbounds i8, i8* %p0, i64 8
+  %p9  = getelementptr inbounds i8, i8* %p0, i64 9
+  %p10 = getelementptr inbounds i8, i8* %p0, i64 10
+  %p11 = getelementptr inbounds i8, i8* %p0, i64 11
+  %p12 = getelementptr inbounds i8, i8* %p0, i64 12
+  %p13 = getelementptr inbounds i8, i8* %p0, i64 13
+  %p14 = getelementptr inbounds i8, i8* %p0, i64 14
+  %p15 = getelementptr inbounds i8, i8* %p0, i64 15
+  %i0  = load i8, i8* %p0,  align 1
+  %i1  = load i8, i8* %p1,  align 1
+  %i2  = load i8, i8* %p2,  align 1
+  %i3  = load i8, i8* %p3,  align 1
+  %i4  = load i8, i8* %p4,  align 1
+  %i5  = load i8, i8* %p5,  align 1
+  %i6  = load i8, i8* %p6,  align 1
+  %i7  = load i8, i8* %p7,  align 1
+  %i8  = load i8, i8* %p8,  align 1
+  %i9  = load i8, i8* %p9,  align 1
+  %i10 = load i8, i8* %p10, align 1
+  %i11 = load i8, i8* %p11, align 1
+  %i12 = load i8, i8* %p12, align 1
+  %i13 = load i8, i8* %p13, align 1
+  %i14 = load i8, i8* %p14, align 1
+  %i15 = load i8, i8* %p15, align 1
+  %x0  = zext i8 %i0  to i16
+  %x1  = zext i8 %i1  to i16
+  %x2  = zext i8 %i2  to i16
+  %x3  = zext i8 %i3  to i16
+  %x4  = zext i8 %i4  to i16
+  %x5  = zext i8 %i5  to i16
+  %x6  = zext i8 %i6  to i16
+  %x7  = zext i8 %i7  to i16
+  %x8  = zext i8 %i8  to i16
+  %x9  = zext i8 %i9  to i16
+  %x10 = zext i8 %i10 to i16
+  %x11 = zext i8 %i11 to i16
+  %x12 = zext i8 %i12 to i16
+  %x13 = zext i8 %i13 to i16
+  %x14 = zext i8 %i14 to i16
+  %x15 = zext i8 %i15 to i16
+  %v0  = insertelement <16 x i16> poison, i16 %x0,  i32 0
+  %v1  = insertelement <16 x i16>  %v0,  i16 %x1,  i32 1
+  %v2  = insertelement <16 x i16>  %v1,  i16 %x2,  i32 2
+  %v3  = insertelement <16 x i16>  %v2,  i16 %x3,  i32 3
+  %v4  = insertelement <16 x i16>  %v3,  i16 %x4,  i32 4
+  %v5  = insertelement <16 x i16>  %v4,  i16 %x5,  i32 5
+  %v6  = insertelement <16 x i16>  %v5,  i16 %x6,  i32 6
+  %v7  = insertelement <16 x i16>  %v6,  i16 %x7,  i32 7
+  %v8  = insertelement <16 x i16>  %v7,  i16 %x8,  i32 8
+  %v9  = insertelement <16 x i16>  %v8,  i16 %x9,  i32 9
+  %v10 = insertelement <16 x i16>  %v9,  i16 %x10, i32 10
+  %v11 = insertelement <16 x i16>  %v10, i16 %x11, i32 11
+  %v12 = insertelement <16 x i16>  %v11, i16 %x12, i32 12
+  %v13 = insertelement <16 x i16>  %v12, i16 %x13, i32 13
+  %v14 = insertelement <16 x i16>  %v13, i16 %x14, i32 14
+  %v15 = insertelement <16 x i16>  %v14, i16 %x15, i32 15
+  ret <16 x i16> %v15
+}
+
+;
+; vXi16
+;
+
+define <2 x i64> @loadext_2i16_to_2i64(i16* %p0) {
+; SSE2-LABEL: @loadext_2i16_to_2i64(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <2 x i16>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <2 x i16>, <2 x i16>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i64>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[TMP5]], i32 1
+; SSE2-NEXT:    ret <2 x i64> [[V1]]
+;
+; SLM-LABEL: @loadext_2i16_to_2i64(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[I0:%.*]] = load i16, i16* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i16, i16* [[P1]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i16 [[I0]] to i64
+; SLM-NEXT:    [[X1:%.*]] = zext i16 [[I1]] to i64
+; SLM-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[X1]], i32 1
+; SLM-NEXT:    ret <2 x i64> [[V1]]
+;
+; AVX-LABEL: @loadext_2i16_to_2i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <2 x i16>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <2 x i16>, <2 x i16>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <2 x i16> [[TMP2]] to <2 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    ret <2 x i64> [[V1]]
+;
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  %i0 = load i16, i16* %p0, align 1
+  %i1 = load i16, i16* %p1, align 1
+  %x0 = zext i16 %i0 to i64
+  %x1 = zext i16 %i1 to i64
+  %v0 = insertelement <2 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <2 x i64>   %v0, i64 %x1, i32 1
+  ret <2 x i64> %v1
+}
+
+define <4 x i32> @loadext_4i16_to_4i32(i16* %p0) {
+; SSE2-LABEL: @loadext_4i16_to_4i32(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <4 x i16>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i32>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[TMP7]], i32 3
+; SSE2-NEXT:    ret <4 x i32> [[V3]]
+;
+; SLM-LABEL: @loadext_4i16_to_4i32(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SLM-NEXT:    [[I0:%.*]] = load i16, i16* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i16, i16* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i16, i16* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i16, i16* [[P3]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i16 [[I0]] to i32
+; SLM-NEXT:    [[X1:%.*]] = zext i16 [[I1]] to i32
+; SLM-NEXT:    [[X2:%.*]] = zext i16 [[I2]] to i32
+; SLM-NEXT:    [[X3:%.*]] = zext i16 [[I3]] to i32
+; SLM-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[X3]], i32 3
+; SLM-NEXT:    ret <4 x i32> [[V3]]
+;
+; AVX-LABEL: @loadext_4i16_to_4i32(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <4 x i16>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i32>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i32> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i32> [[V0]], i32 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i32> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i32> [[V1]], i32 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i32> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i32> [[V2]], i32 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i32> [[V3]]
+;
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  %p2 = getelementptr inbounds i16, i16* %p0, i64 2
+  %p3 = getelementptr inbounds i16, i16* %p0, i64 3
+  %i0 = load i16, i16* %p0, align 1
+  %i1 = load i16, i16* %p1, align 1
+  %i2 = load i16, i16* %p2, align 1
+  %i3 = load i16, i16* %p3, align 1
+  %x0 = zext i16 %i0 to i32
+  %x1 = zext i16 %i1 to i32
+  %x2 = zext i16 %i2 to i32
+  %x3 = zext i16 %i3 to i32
+  %v0 = insertelement <4 x i32> poison, i32 %x0, i32 0
+  %v1 = insertelement <4 x i32>   %v0, i32 %x1, i32 1
+  %v2 = insertelement <4 x i32>   %v1, i32 %x2, i32 2
+  %v3 = insertelement <4 x i32>   %v2, i32 %x3, i32 3
+  ret <4 x i32> %v3
+}
+
+define <4 x i64> @loadext_4i16_to_4i64(i16* %p0) {
+; SSE2-LABEL: @loadext_4i16_to_4i64(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <4 x i16>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i64>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[TMP7]], i32 3
+; SSE2-NEXT:    ret <4 x i64> [[V3]]
+;
+; SLM-LABEL: @loadext_4i16_to_4i64(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SLM-NEXT:    [[I0:%.*]] = load i16, i16* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i16, i16* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i16, i16* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i16, i16* [[P3]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i16 [[I0]] to i64
+; SLM-NEXT:    [[X1:%.*]] = zext i16 [[I1]] to i64
+; SLM-NEXT:    [[X2:%.*]] = zext i16 [[I2]] to i64
+; SLM-NEXT:    [[X3:%.*]] = zext i16 [[I3]] to i64
+; SLM-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[X3]], i32 3
+; SLM-NEXT:    ret <4 x i64> [[V3]]
+;
+; AVX-LABEL: @loadext_4i16_to_4i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <4 x i16>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i16>, <4 x i16>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i64> [[V3]]
+;
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  %p2 = getelementptr inbounds i16, i16* %p0, i64 2
+  %p3 = getelementptr inbounds i16, i16* %p0, i64 3
+  %i0 = load i16, i16* %p0, align 1
+  %i1 = load i16, i16* %p1, align 1
+  %i2 = load i16, i16* %p2, align 1
+  %i3 = load i16, i16* %p3, align 1
+  %x0 = zext i16 %i0 to i64
+  %x1 = zext i16 %i1 to i64
+  %x2 = zext i16 %i2 to i64
+  %x3 = zext i16 %i3 to i64
+  %v0 = insertelement <4 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <4 x i64>   %v0, i64 %x1, i32 1
+  %v2 = insertelement <4 x i64>   %v1, i64 %x2, i32 2
+  %v3 = insertelement <4 x i64>   %v2, i64 %x3, i32 3
+  ret <4 x i64> %v3
+}
+
+define <8 x i32> @loadext_8i16_to_8i32(i16* %p0) {
+; SSE2-LABEL: @loadext_8i16_to_8i32(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SSE2-NEXT:    [[P4:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 4
+; SSE2-NEXT:    [[P5:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 5
+; SSE2-NEXT:    [[P6:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 6
+; SSE2-NEXT:    [[P7:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 7
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <8 x i16>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <8 x i16> [[TMP2]] to <8 x i32>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <8 x i32> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <8 x i32> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[TMP7]], i32 3
+; SSE2-NEXT:    [[TMP8:%.*]] = extractelement <8 x i32> [[TMP3]], i32 4
+; SSE2-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[TMP8]], i32 4
+; SSE2-NEXT:    [[TMP9:%.*]] = extractelement <8 x i32> [[TMP3]], i32 5
+; SSE2-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[TMP9]], i32 5
+; SSE2-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP3]], i32 6
+; SSE2-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[TMP10]], i32 6
+; SSE2-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP3]], i32 7
+; SSE2-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[TMP11]], i32 7
+; SSE2-NEXT:    ret <8 x i32> [[V7]]
+;
+; SLM-LABEL: @loadext_8i16_to_8i32(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; SLM-NEXT:    [[P4:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 4
+; SLM-NEXT:    [[P5:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 5
+; SLM-NEXT:    [[P6:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 6
+; SLM-NEXT:    [[P7:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 7
+; SLM-NEXT:    [[I0:%.*]] = load i16, i16* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i16, i16* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i16, i16* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i16, i16* [[P3]], align 1
+; SLM-NEXT:    [[I4:%.*]] = load i16, i16* [[P4]], align 1
+; SLM-NEXT:    [[I5:%.*]] = load i16, i16* [[P5]], align 1
+; SLM-NEXT:    [[I6:%.*]] = load i16, i16* [[P6]], align 1
+; SLM-NEXT:    [[I7:%.*]] = load i16, i16* [[P7]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i16 [[I0]] to i32
+; SLM-NEXT:    [[X1:%.*]] = zext i16 [[I1]] to i32
+; SLM-NEXT:    [[X2:%.*]] = zext i16 [[I2]] to i32
+; SLM-NEXT:    [[X3:%.*]] = zext i16 [[I3]] to i32
+; SLM-NEXT:    [[X4:%.*]] = zext i16 [[I4]] to i32
+; SLM-NEXT:    [[X5:%.*]] = zext i16 [[I5]] to i32
+; SLM-NEXT:    [[X6:%.*]] = zext i16 [[I6]] to i32
+; SLM-NEXT:    [[X7:%.*]] = zext i16 [[I7]] to i32
+; SLM-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[X3]], i32 3
+; SLM-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[X4]], i32 4
+; SLM-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[X5]], i32 5
+; SLM-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[X6]], i32 6
+; SLM-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[X7]], i32 7
+; SLM-NEXT:    ret <8 x i32> [[V7]]
+;
+; AVX-LABEL: @loadext_8i16_to_8i32(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i16, i16* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 3
+; AVX-NEXT:    [[P4:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 4
+; AVX-NEXT:    [[P5:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 5
+; AVX-NEXT:    [[P6:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 6
+; AVX-NEXT:    [[P7:%.*]] = getelementptr inbounds i16, i16* [[P0]], i64 7
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i16* [[P0]] to <8 x i16>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <8 x i16> [[TMP2]] to <8 x i32>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <8 x i32> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <8 x i32> poison, i32 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <8 x i32> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <8 x i32> [[V0]], i32 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <8 x i32> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <8 x i32> [[V1]], i32 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <8 x i32> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <8 x i32> [[V2]], i32 [[TMP7]], i32 3
+; AVX-NEXT:    [[TMP8:%.*]] = extractelement <8 x i32> [[TMP3]], i32 4
+; AVX-NEXT:    [[V4:%.*]] = insertelement <8 x i32> [[V3]], i32 [[TMP8]], i32 4
+; AVX-NEXT:    [[TMP9:%.*]] = extractelement <8 x i32> [[TMP3]], i32 5
+; AVX-NEXT:    [[V5:%.*]] = insertelement <8 x i32> [[V4]], i32 [[TMP9]], i32 5
+; AVX-NEXT:    [[TMP10:%.*]] = extractelement <8 x i32> [[TMP3]], i32 6
+; AVX-NEXT:    [[V6:%.*]] = insertelement <8 x i32> [[V5]], i32 [[TMP10]], i32 6
+; AVX-NEXT:    [[TMP11:%.*]] = extractelement <8 x i32> [[TMP3]], i32 7
+; AVX-NEXT:    [[V7:%.*]] = insertelement <8 x i32> [[V6]], i32 [[TMP11]], i32 7
+; AVX-NEXT:    ret <8 x i32> [[V7]]
+;
+  %p1 = getelementptr inbounds i16, i16* %p0, i64 1
+  %p2 = getelementptr inbounds i16, i16* %p0, i64 2
+  %p3 = getelementptr inbounds i16, i16* %p0, i64 3
+  %p4 = getelementptr inbounds i16, i16* %p0, i64 4
+  %p5 = getelementptr inbounds i16, i16* %p0, i64 5
+  %p6 = getelementptr inbounds i16, i16* %p0, i64 6
+  %p7 = getelementptr inbounds i16, i16* %p0, i64 7
+  %i0 = load i16, i16* %p0, align 1
+  %i1 = load i16, i16* %p1, align 1
+  %i2 = load i16, i16* %p2, align 1
+  %i3 = load i16, i16* %p3, align 1
+  %i4 = load i16, i16* %p4, align 1
+  %i5 = load i16, i16* %p5, align 1
+  %i6 = load i16, i16* %p6, align 1
+  %i7 = load i16, i16* %p7, align 1
+  %x0 = zext i16 %i0 to i32
+  %x1 = zext i16 %i1 to i32
+  %x2 = zext i16 %i2 to i32
+  %x3 = zext i16 %i3 to i32
+  %x4 = zext i16 %i4 to i32
+  %x5 = zext i16 %i5 to i32
+  %x6 = zext i16 %i6 to i32
+  %x7 = zext i16 %i7 to i32
+  %v0 = insertelement <8 x i32> poison, i32 %x0, i32 0
+  %v1 = insertelement <8 x i32>   %v0, i32 %x1, i32 1
+  %v2 = insertelement <8 x i32>   %v1, i32 %x2, i32 2
+  %v3 = insertelement <8 x i32>   %v2, i32 %x3, i32 3
+  %v4 = insertelement <8 x i32>   %v3, i32 %x4, i32 4
+  %v5 = insertelement <8 x i32>   %v4, i32 %x5, i32 5
+  %v6 = insertelement <8 x i32>   %v5, i32 %x6, i32 6
+  %v7 = insertelement <8 x i32>   %v6, i32 %x7, i32 7
+  ret <8 x i32> %v7
+}
+
+;
+; vXi32
+;
+
+define <2 x i64> @loadext_2i32_to_2i64(i32* %p0) {
+; SSE2-LABEL: @loadext_2i32_to_2i64(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i32* [[P0]] to <2 x i32>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <2 x i32>, <2 x i32>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[TMP5]], i32 1
+; SSE2-NEXT:    ret <2 x i64> [[V1]]
+;
+; SLM-LABEL: @loadext_2i32_to_2i64(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[I0:%.*]] = load i32, i32* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i32, i32* [[P1]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i32 [[I0]] to i64
+; SLM-NEXT:    [[X1:%.*]] = zext i32 [[I1]] to i64
+; SLM-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[X1]], i32 1
+; SLM-NEXT:    ret <2 x i64> [[V1]]
+;
+; AVX-LABEL: @loadext_2i32_to_2i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i32* [[P0]] to <2 x i32>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <2 x i32>, <2 x i32>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <2 x i32> [[TMP2]] to <2 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <2 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <2 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <2 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    ret <2 x i64> [[V1]]
+;
+  %p1 = getelementptr inbounds i32, i32* %p0, i64 1
+  %i0 = load i32, i32* %p0, align 1
+  %i1 = load i32, i32* %p1, align 1
+  %x0 = zext i32 %i0 to i64
+  %x1 = zext i32 %i1 to i64
+  %v0 = insertelement <2 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <2 x i64>   %v0, i64 %x1, i32 1
+  ret <2 x i64> %v1
+}
+
+define <4 x i64> @loadext_4i32_to_4i64(i32* %p0) {
+; SSE2-LABEL: @loadext_4i32_to_4i64(
+; SSE2-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; SSE2-NEXT:    [[P2:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 2
+; SSE2-NEXT:    [[P3:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 3
+; SSE2-NEXT:    [[TMP1:%.*]] = bitcast i32* [[P0]] to <4 x i32>*
+; SSE2-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 1
+; SSE2-NEXT:    [[TMP3:%.*]] = zext <4 x i32> [[TMP2]] to <4 x i64>
+; SSE2-NEXT:    [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; SSE2-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; SSE2-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; SSE2-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[TMP5]], i32 1
+; SSE2-NEXT:    [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; SSE2-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[TMP6]], i32 2
+; SSE2-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; SSE2-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[TMP7]], i32 3
+; SSE2-NEXT:    ret <4 x i64> [[V3]]
+;
+; SLM-LABEL: @loadext_4i32_to_4i64(
+; SLM-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; SLM-NEXT:    [[P2:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 2
+; SLM-NEXT:    [[P3:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 3
+; SLM-NEXT:    [[I0:%.*]] = load i32, i32* [[P0]], align 1
+; SLM-NEXT:    [[I1:%.*]] = load i32, i32* [[P1]], align 1
+; SLM-NEXT:    [[I2:%.*]] = load i32, i32* [[P2]], align 1
+; SLM-NEXT:    [[I3:%.*]] = load i32, i32* [[P3]], align 1
+; SLM-NEXT:    [[X0:%.*]] = zext i32 [[I0]] to i64
+; SLM-NEXT:    [[X1:%.*]] = zext i32 [[I1]] to i64
+; SLM-NEXT:    [[X2:%.*]] = zext i32 [[I2]] to i64
+; SLM-NEXT:    [[X3:%.*]] = zext i32 [[I3]] to i64
+; SLM-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[X0]], i32 0
+; SLM-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[X1]], i32 1
+; SLM-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[X2]], i32 2
+; SLM-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[X3]], i32 3
+; SLM-NEXT:    ret <4 x i64> [[V3]]
+;
+; AVX-LABEL: @loadext_4i32_to_4i64(
+; AVX-NEXT:    [[P1:%.*]] = getelementptr inbounds i32, i32* [[P0:%.*]], i64 1
+; AVX-NEXT:    [[P2:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 2
+; AVX-NEXT:    [[P3:%.*]] = getelementptr inbounds i32, i32* [[P0]], i64 3
+; AVX-NEXT:    [[TMP1:%.*]] = bitcast i32* [[P0]] to <4 x i32>*
+; AVX-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 1
+; AVX-NEXT:    [[TMP3:%.*]] = zext <4 x i32> [[TMP2]] to <4 x i64>
+; AVX-NEXT:    [[TMP4:%.*]] = extractelement <4 x i64> [[TMP3]], i32 0
+; AVX-NEXT:    [[V0:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i32 0
+; AVX-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP3]], i32 1
+; AVX-NEXT:    [[V1:%.*]] = insertelement <4 x i64> [[V0]], i64 [[TMP5]], i32 1
+; AVX-NEXT:    [[TMP6:%.*]] = extractelement <4 x i64> [[TMP3]], i32 2
+; AVX-NEXT:    [[V2:%.*]] = insertelement <4 x i64> [[V1]], i64 [[TMP6]], i32 2
+; AVX-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP3]], i32 3
+; AVX-NEXT:    [[V3:%.*]] = insertelement <4 x i64> [[V2]], i64 [[TMP7]], i32 3
+; AVX-NEXT:    ret <4 x i64> [[V3]]
+;
+  %p1 = getelementptr inbounds i32, i32* %p0, i64 1
+  %p2 = getelementptr inbounds i32, i32* %p0, i64 2
+  %p3 = getelementptr inbounds i32, i32* %p0, i64 3
+  %i0 = load i32, i32* %p0, align 1
+  %i1 = load i32, i32* %p1, align 1
+  %i2 = load i32, i32* %p2, align 1
+  %i3 = load i32, i32* %p3, align 1
+  %x0 = zext i32 %i0 to i64
+  %x1 = zext i32 %i1 to i64
+  %x2 = zext i32 %i2 to i64
+  %x3 = zext i32 %i3 to i64
+  %v0 = insertelement <4 x i64> poison, i64 %x0, i32 0
+  %v1 = insertelement <4 x i64>   %v0, i64 %x1, i32 1
+  %v2 = insertelement <4 x i64>   %v1, i64 %x2, i32 2
+  %v3 = insertelement <4 x i64>   %v2, i64 %x3, i32 3
+  ret <4 x i64> %v3
+}
diff --git a/llvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
new file mode 100644
index 0000000000000..b17f202fa55c6
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/vectorizable-functions-inseltpoison.ll
@@ -0,0 +1,78 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -slp-vectorizer -S %s | FileCheck %s
+
+declare float @memread(float) readonly #0
+declare <4 x float> @vmemread(<4 x float>)
+
+define <4 x float> @memread_4x(<4 x float>* %a) {
+; CHECK-LABEL: @memread_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[TMP1:%.*]] = call fast <4 x float> @vmemread(<4 x float> [[TMP0]])
+; CHECK-NEXT:    [[TMP2:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP2]], i32 0
+; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x float> [[TMP1]], i32 1
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP3]], i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP4]], i32 2
+; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x float> [[TMP1]], i32 3
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP5]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @memread(float %vecext) #0
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @memread(float %vecext.1) #0
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @memread(float %vecext.2) #0
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @memread(float %vecext.3) #0
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+
+declare float @memwrite(float) #1
+declare <4 x float> @vmemwrite(<4 x float>)
+
+define <4 x float> @memwrite_4x(<4 x float>* %a) {
+; CHECK-LABEL: @memwrite_4x(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <4 x float>, <4 x float>* [[A:%.*]], align 16
+; CHECK-NEXT:    [[VECEXT:%.*]] = extractelement <4 x float> [[TMP0]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call fast float @memwrite(float [[VECEXT]]) [[ATTR1:#.*]]
+; CHECK-NEXT:    [[VECINS:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0
+; CHECK-NEXT:    [[VECEXT_1:%.*]] = extractelement <4 x float> [[TMP0]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = tail call fast float @memwrite(float [[VECEXT_1]]) [[ATTR1]]
+; CHECK-NEXT:    [[VECINS_1:%.*]] = insertelement <4 x float> [[VECINS]], float [[TMP2]], i32 1
+; CHECK-NEXT:    [[VECEXT_2:%.*]] = extractelement <4 x float> [[TMP0]], i32 2
+; CHECK-NEXT:    [[TMP3:%.*]] = tail call fast float @memwrite(float [[VECEXT_2]]) [[ATTR1]]
+; CHECK-NEXT:    [[VECINS_2:%.*]] = insertelement <4 x float> [[VECINS_1]], float [[TMP3]], i32 2
+; CHECK-NEXT:    [[VECEXT_3:%.*]] = extractelement <4 x float> [[TMP0]], i32 3
+; CHECK-NEXT:    [[TMP4:%.*]] = tail call fast float @memwrite(float [[VECEXT_3]]) [[ATTR1]]
+; CHECK-NEXT:    [[VECINS_3:%.*]] = insertelement <4 x float> [[VECINS_2]], float [[TMP4]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINS_3]]
+;
+entry:
+  %0 = load <4 x float>, <4 x float>* %a, align 16
+  %vecext = extractelement <4 x float> %0, i32 0
+  %1 = tail call fast float @memwrite(float %vecext) #1
+  %vecins = insertelement <4 x float> poison, float %1, i32 0
+  %vecext.1 = extractelement <4 x float> %0, i32 1
+  %2 = tail call fast float @memwrite(float %vecext.1) #1
+  %vecins.1 = insertelement <4 x float> %vecins, float %2, i32 1
+  %vecext.2 = extractelement <4 x float> %0, i32 2
+  %3 = tail call fast float @memwrite(float %vecext.2) #1
+  %vecins.2 = insertelement <4 x float> %vecins.1, float %3, i32 2
+  %vecext.3 = extractelement <4 x float> %0, i32 3
+  %4 = tail call fast float @memwrite(float %vecext.3) #1
+  %vecins.3 = insertelement <4 x float> %vecins.2, float %4, i32 3
+  ret <4 x float> %vecins.3
+}
+
+attributes #0 = { "vector-function-abi-variant"="_ZGV_LLVM_N4v_memread(vmemread)" }
+attributes #1 = { "vector-function-abi-variant"="_ZGV_LLVM_N4v_memwrite(vmemwrite)" }
diff --git a/llvm/test/Transforms/Scalarizer/basic-inseltpoison.ll b/llvm/test/Transforms/Scalarizer/basic-inseltpoison.ll
new file mode 100644
index 0000000000000..26fb97278d728
--- /dev/null
+++ b/llvm/test/Transforms/Scalarizer/basic-inseltpoison.ll
@@ -0,0 +1,561 @@
+; RUN: opt %s -scalarizer -scalarize-load-store -dce -S | FileCheck %s
+; RUN: opt %s -passes='function(scalarizer,dce)' -scalarize-load-store -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
+
+declare <4 x float> @ext(<4 x float>)
+@g = global <4 x float> zeroinitializer
+
+define void @f1(<4 x float> %init, <4 x float> *%base, i32 %count) {
+; CHECK-LABEL: @f1(
+; CHECK: entry:
+; CHECK:   %init.i0 = extractelement <4 x float> %init, i32 0
+; CHECK:   %init.i1 = extractelement <4 x float> %init, i32 1
+; CHECK:   %init.i2 = extractelement <4 x float> %init, i32 2
+; CHECK:   %init.i3 = extractelement <4 x float> %init, i32 3
+; CHECK:   br label %loop
+; CHECK: loop:
+; CHECK:   %i = phi i32 [ %count, %entry ], [ %nexti, %loop ]
+; CHECK:   %acc.i0 = phi float [ %init.i0, %entry ], [ %sel.i0, %loop ]
+; CHECK:   %acc.i1 = phi float [ %init.i1, %entry ], [ %sel.i1, %loop ]
+; CHECK:   %acc.i2 = phi float [ %init.i2, %entry ], [ %sel.i2, %loop ]
+; CHECK:   %acc.i3 = phi float [ %init.i3, %entry ], [ %sel.i3, %loop ]
+; CHECK:   %nexti = sub i32 %i, 1
+; CHECK:   %ptr = getelementptr <4 x float>, <4 x float>* %base, i32 %i
+; CHECK:   %ptr.i0 = bitcast <4 x float>* %ptr to float*
+; CHECK:   %val.i0 = load float, float* %ptr.i0, align 16
+; CHECK:   %ptr.i1 = getelementptr float, float* %ptr.i0, i32 1
+; CHECK:   %val.i1 = load float, float* %ptr.i1, align 4
+; CHECK:   %ptr.i2 = getelementptr float, float* %ptr.i0, i32 2
+; CHECK:   %val.i2 = load float, float* %ptr.i2, align 8
+; CHECK:   %ptr.i3 = getelementptr float, float* %ptr.i0, i32 3
+; CHECK:   %val.i3 = load float, float* %ptr.i3, align 4
+; CHECK:   %add.i0 = fadd float %val.i0, %val.i2
+; CHECK:   %add.i1 = fadd float %val.i1, %val.i3
+; CHECK:   %add.i2 = fadd float %acc.i0, %acc.i2
+; CHECK:   %add.i3 = fadd float %acc.i1, %acc.i3
+; CHECK:   %add.upto0 = insertelement <4 x float> undef, float %add.i0, i32 0
+; CHECK:   %add.upto1 = insertelement <4 x float> %add.upto0, float %add.i1, i32 1
+; CHECK:   %add.upto2 = insertelement <4 x float> %add.upto1, float %add.i2, i32 2
+; CHECK:   %add = insertelement <4 x float> %add.upto2, float %add.i3, i32 3
+; CHECK:   %call = call <4 x float> @ext(<4 x float> %add)
+; CHECK:   %call.i0 = extractelement <4 x float> %call, i32 0
+; CHECK:   %cmp.i0 = fcmp ogt float %call.i0, 1.0
+; CHECK:   %call.i1 = extractelement <4 x float> %call, i32 1
+; CHECK:   %cmp.i1 = fcmp ogt float %call.i1, 2.0
+; CHECK:   %call.i2 = extractelement <4 x float> %call, i32 2
+; CHECK:   %cmp.i2 = fcmp ogt float %call.i2, 3.0
+; CHECK:   %call.i3 = extractelement <4 x float> %call, i32 3
+; CHECK:   %cmp.i3 = fcmp ogt float %call.i3, 4.0
+; CHECK:   %sel.i0 = select i1 %cmp.i0, float %call.i0, float 5.0
+; CHECK:   %sel.i1 = select i1 %cmp.i1, float %call.i1, float 6.0
+; CHECK:   %sel.i2 = select i1 %cmp.i2, float %call.i2, float 7.0
+; CHECK:   %sel.i3 = select i1 %cmp.i3, float %call.i3, float 8.0
+; CHECK:   store float %sel.i0, float* %ptr.i0
+; CHECK:   store float %sel.i1, float* %ptr.i1
+; CHECK:   store float %sel.i2, float* %ptr.i2
+; CHECK:   store float %sel.i3, float* %ptr.i3
+; CHECK:   %test = icmp eq i32 %nexti, 0
+; CHECK:   br i1 %test, label %loop, label %exit
+; CHECK: exit:
+; CHECK:   ret void
+entry:
+  br label %loop
+
+loop:
+  %i = phi i32 [ %count, %entry ], [ %nexti, %loop ]
+  %acc = phi <4 x float> [ %init, %entry ], [ %sel, %loop ]
+  %nexti = sub i32 %i, 1
+
+  %ptr = getelementptr <4 x float>, <4 x float> *%base, i32 %i
+  %val = load <4 x float> , <4 x float> *%ptr
+  %dval = bitcast <4 x float> %val to <2 x double>
+  %dacc = bitcast <4 x float> %acc to <2 x double>
+  %shuffle1 = shufflevector <2 x double> %dval, <2 x double> %dacc,
+                            <2 x i32> <i32 0, i32 2>
+  %shuffle2 = shufflevector <2 x double> %dval, <2 x double> %dacc,
+                            <2 x i32> <i32 1, i32 3>
+  %f1 = bitcast <2 x double> %shuffle1 to <4 x float>
+  %f2 = bitcast <2 x double> %shuffle2 to <4 x float>
+  %add = fadd <4 x float> %f1, %f2
+  %call = call <4 x float> @ext(<4 x float> %add)
+  %cmp = fcmp ogt <4 x float> %call,
+                  <float 1.0, float 2.0, float 3.0, float 4.0>
+  %sel = select <4 x i1> %cmp, <4 x float> %call,
+                <4 x float> <float 5.0, float 6.0, float 7.0, float 8.0>
+  store <4 x float> %sel, <4 x float> *%ptr
+
+  %test = icmp eq i32 %nexti, 0
+  br i1 %test, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+define void @f2(<4 x i32> %init, <4 x i8> *%base, i32 %count) {
+; CHECK-LABEL: define void @f2(<4 x i32> %init, <4 x i8>* %base, i32 %count) {
+; CHECK: entry:
+; CHECK:   %init.i0 = extractelement <4 x i32> %init, i32 0
+; CHECK:   %init.i1 = extractelement <4 x i32> %init, i32 1
+; CHECK:   %init.i2 = extractelement <4 x i32> %init, i32 2
+; CHECK:   %init.i3 = extractelement <4 x i32> %init, i32 3
+; CHECK:   br label %loop
+; CHECK: loop:
+; CHECK:   %i = phi i32 [ %count, %entry ], [ %nexti, %loop ]
+; CHECK:   %acc.i0 = phi i32 [ %init.i0, %entry ], [ %sel.i0, %loop ]
+; CHECK:   %acc.i1 = phi i32 [ %init.i1, %entry ], [ %sel.i1, %loop ]
+; CHECK:   %acc.i2 = phi i32 [ %init.i2, %entry ], [ %sel.i2, %loop ]
+; CHECK:   %acc.i3 = phi i32 [ %init.i3, %entry ], [ %sel.i3, %loop ]
+; CHECK:   %nexti = sub i32 %i, 1
+; CHECK:   %ptr = getelementptr <4 x i8>, <4 x i8>* %base, i32 %i
+; CHECK:   %ptr.i0 = bitcast <4 x i8>* %ptr to i8*
+; CHECK:   %val.i0 = load i8, i8* %ptr.i0, align 4
+; CHECK:   %ptr.i1 = getelementptr i8, i8* %ptr.i0, i32 1
+; CHECK:   %val.i1 = load i8, i8* %ptr.i1, align 1
+; CHECK:   %ptr.i2 = getelementptr i8, i8* %ptr.i0, i32 2
+; CHECK:   %val.i2 = load i8, i8* %ptr.i2, align 2
+; CHECK:   %ptr.i3 = getelementptr i8, i8* %ptr.i0, i32 3
+; CHECK:   %val.i3 = load i8, i8* %ptr.i3, align 1
+; CHECK:   %ext.i0 = sext i8 %val.i0 to i32
+; CHECK:   %ext.i1 = sext i8 %val.i1 to i32
+; CHECK:   %ext.i2 = sext i8 %val.i2 to i32
+; CHECK:   %ext.i3 = sext i8 %val.i3 to i32
+; CHECK:   %add.i0 = add i32 %ext.i0, %acc.i0
+; CHECK:   %add.i1 = add i32 %ext.i1, %acc.i1
+; CHECK:   %add.i2 = add i32 %ext.i2, %acc.i2
+; CHECK:   %add.i3 = add i32 %ext.i3, %acc.i3
+; CHECK:   %cmp.i0 = icmp slt i32 %add.i0, -10
+; CHECK:   %cmp.i1 = icmp slt i32 %add.i1, -11
+; CHECK:   %cmp.i2 = icmp slt i32 %add.i2, -12
+; CHECK:   %cmp.i3 = icmp slt i32 %add.i3, -13
+; CHECK:   %sel.i0 = select i1 %cmp.i0, i32 %add.i0, i32 %i
+; CHECK:   %sel.i1 = select i1 %cmp.i1, i32 %add.i1, i32 %i
+; CHECK:   %sel.i2 = select i1 %cmp.i2, i32 %add.i2, i32 %i
+; CHECK:   %sel.i3 = select i1 %cmp.i3, i32 %add.i3, i32 %i
+; CHECK:   %trunc.i0 = trunc i32 %sel.i0 to i8
+; CHECK:   %trunc.i1 = trunc i32 %sel.i1 to i8
+; CHECK:   %trunc.i2 = trunc i32 %sel.i2 to i8
+; CHECK:   %trunc.i3 = trunc i32 %sel.i3 to i8
+; CHECK:   store i8 %trunc.i0, i8* %ptr.i0, align 4
+; CHECK:   store i8 %trunc.i1, i8* %ptr.i1, align 1
+; CHECK:   store i8 %trunc.i2, i8* %ptr.i2, align 2
+; CHECK:   store i8 %trunc.i3, i8* %ptr.i3, align 1
+; CHECK:   %test = icmp eq i32 %nexti, 0
+; CHECK:   br i1 %test, label %loop, label %exit
+; CHECK: exit:
+; CHECK:   ret void
+entry:
+  br label %loop
+
+loop:
+  %i = phi i32 [ %count, %entry ], [ %nexti, %loop ]
+  %acc = phi <4 x i32> [ %init, %entry ], [ %sel, %loop ]
+  %nexti = sub i32 %i, 1
+
+  %ptr = getelementptr <4 x i8>, <4 x i8> *%base, i32 %i
+  %val = load <4 x i8> , <4 x i8> *%ptr
+  %ext = sext <4 x i8> %val to <4 x i32>
+  %add = add <4 x i32> %ext, %acc
+  %cmp = icmp slt <4 x i32> %add, <i32 -10, i32 -11, i32 -12, i32 -13>
+  %single = insertelement <4 x i32> poison, i32 %i, i32 0
+  %limit = shufflevector <4 x i32> %single, <4 x i32> undef,
+                         <4 x i32> zeroinitializer
+  %sel = select <4 x i1> %cmp, <4 x i32> %add, <4 x i32> %limit
+  %trunc = trunc <4 x i32> %sel to <4 x i8>
+  store <4 x i8> %trunc, <4 x i8> *%ptr
+
+  %test = icmp eq i32 %nexti, 0
+  br i1 %test, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; Check that !tbaa information is preserved.
+define void @f3(<4 x i32> *%src, <4 x i32> *%dst) {
+; CHECK-LABEL: @f3(
+; CHECK: %val.i0 = load i32, i32* %src.i0, align 16, !tbaa ![[TAG:[0-9]*]]
+; CHECK: %val.i1 = load i32, i32* %src.i1, align 4, !tbaa ![[TAG]]
+; CHECK: %val.i2 = load i32, i32* %src.i2, align 8, !tbaa ![[TAG]]
+; CHECK: %val.i3 = load i32, i32* %src.i3, align 4, !tbaa ![[TAG]]
+; CHECK: store i32 %add.i0, i32* %dst.i0, align 16, !tbaa ![[TAG:[0-9]*]]
+; CHECK: store i32 %add.i1, i32* %dst.i1, align 4, !tbaa ![[TAG]]
+; CHECK: store i32 %add.i2, i32* %dst.i2, align 8, !tbaa ![[TAG]]
+; CHECK: store i32 %add.i3, i32* %dst.i3, align 4, !tbaa ![[TAG]]
+; CHECK: ret void
+  %val = load <4 x i32> , <4 x i32> *%src, !tbaa !1
+  %add = add <4 x i32> %val, %val
+  store <4 x i32> %add, <4 x i32> *%dst, !tbaa !2
+  ret void
+}
+
+; Check that !tbaa.struct information is preserved.
+define void @f4(<4 x i32> *%src, <4 x i32> *%dst) {
+; CHECK-LABEL: @f4(
+; CHECK: %val.i0 = load i32, i32* %src.i0, align 16, !tbaa.struct ![[TAG:[0-9]*]]
+; CHECK: %val.i1 = load i32, i32* %src.i1, align 4, !tbaa.struct ![[TAG]]
+; CHECK: %val.i2 = load i32, i32* %src.i2, align 8, !tbaa.struct ![[TAG]]
+; CHECK: %val.i3 = load i32, i32* %src.i3, align 4, !tbaa.struct ![[TAG]]
+; CHECK: store i32 %add.i0, i32* %dst.i0, align 16, !tbaa.struct ![[TAG]]
+; CHECK: store i32 %add.i1, i32* %dst.i1, align 4, !tbaa.struct ![[TAG]]
+; CHECK: store i32 %add.i2, i32* %dst.i2, align 8, !tbaa.struct ![[TAG]]
+; CHECK: store i32 %add.i3, i32* %dst.i3, align 4, !tbaa.struct ![[TAG]]
+; CHECK: ret void
+  %val = load <4 x i32> , <4 x i32> *%src, !tbaa.struct !5
+  %add = add <4 x i32> %val, %val
+  store <4 x i32> %add, <4 x i32> *%dst, !tbaa.struct !5
+  ret void
+}
+
+; Check that llvm.access.group information is preserved.
+define void @f5(i32 %count, <4 x i32> *%src, <4 x i32> *%dst) {
+; CHECK-LABEL: @f5(
+; CHECK: %val.i0 = load i32, i32* %this_src.i0, align 16, !llvm.access.group ![[TAG:[0-9]*]]
+; CHECK: %val.i1 = load i32, i32* %this_src.i1, align 4, !llvm.access.group ![[TAG]]
+; CHECK: %val.i2 = load i32, i32* %this_src.i2, align 8, !llvm.access.group ![[TAG]]
+; CHECK: %val.i3 = load i32, i32* %this_src.i3, align 4, !llvm.access.group ![[TAG]]
+; CHECK: store i32 %add.i0, i32* %this_dst.i0, align 16, !llvm.access.group ![[TAG]]
+; CHECK: store i32 %add.i1, i32* %this_dst.i1, align 4, !llvm.access.group ![[TAG]]
+; CHECK: store i32 %add.i2, i32* %this_dst.i2, align 8, !llvm.access.group ![[TAG]]
+; CHECK: store i32 %add.i3, i32* %this_dst.i3, align 4, !llvm.access.group ![[TAG]]
+; CHECK: ret void
+entry:
+  br label %loop
+
+loop:
+  %index = phi i32 [ 0, %entry ], [ %next_index, %loop ]
+  %this_src = getelementptr <4 x i32>, <4 x i32> *%src, i32 %index
+  %this_dst = getelementptr <4 x i32>, <4 x i32> *%dst, i32 %index
+  %val = load <4 x i32> , <4 x i32> *%this_src, !llvm.access.group !13
+  %add = add <4 x i32> %val, %val
+  store <4 x i32> %add, <4 x i32> *%this_dst, !llvm.access.group !13
+  %next_index = add i32 %index, -1
+  %continue = icmp ne i32 %next_index, %count
+  br i1 %continue, label %loop, label %end, !llvm.loop !3
+
+end:
+  ret void
+}
+
+; Check that fpmath information is preserved.
+define <4 x float> @f6(<4 x float> %x) {
+; CHECK-LABEL: @f6(
+; CHECK: %x.i0 = extractelement <4 x float> %x, i32 0
+; CHECK: %res.i0 = fadd float %x.i0, 1.0{{[e+0]*}}, !fpmath ![[TAG:[0-9]*]]
+; CHECK: %x.i1 = extractelement <4 x float> %x, i32 1
+; CHECK: %res.i1 = fadd float %x.i1, 2.0{{[e+0]*}}, !fpmath ![[TAG]]
+; CHECK: %x.i2 = extractelement <4 x float> %x, i32 2
+; CHECK: %res.i2 = fadd float %x.i2, 3.0{{[e+0]*}}, !fpmath ![[TAG]]
+; CHECK: %x.i3 = extractelement <4 x float> %x, i32 3
+; CHECK: %res.i3 = fadd float %x.i3, 4.0{{[e+0]*}}, !fpmath ![[TAG]]
+; CHECK: %res.upto0 = insertelement <4 x float> undef, float %res.i0, i32 0
+; CHECK: %res.upto1 = insertelement <4 x float> %res.upto0, float %res.i1, i32 1
+; CHECK: %res.upto2 = insertelement <4 x float> %res.upto1, float %res.i2, i32 2
+; CHECK: %res = insertelement <4 x float> %res.upto2, float %res.i3, i32 3
+; CHECK: ret <4 x float> %res
+  %res = fadd <4 x float> %x, <float 1.0, float 2.0, float 3.0, float 4.0>,
+    !fpmath !4
+  ret <4 x float> %res
+}
+
+; Check that random metadata isn't kept.
+define void @f7(<4 x i32> *%src, <4 x i32> *%dst) {
+; CHECK-LABEL: @f7(
+; CHECK-NOT: !foo
+; CHECK: ret void
+  %val = load <4 x i32> , <4 x i32> *%src, !foo !5
+  %add = add <4 x i32> %val, %val
+  store <4 x i32> %add, <4 x i32> *%dst, !foo !5
+  ret void
+}
+
+; Test GEP with vectors.
+define void @f8(<4 x float *> *%dest, <4 x float *> %ptr0, <4 x i32> %i0,
+                float *%other) {
+; CHECK-LABEL: @f8(
+; CHECK: %dest.i0 = bitcast <4 x float*>* %dest to float**
+; CHECK: %dest.i1 = getelementptr float*, float** %dest.i0, i32 1
+; CHECK: %dest.i2 = getelementptr float*, float** %dest.i0, i32 2
+; CHECK: %dest.i3 = getelementptr float*, float** %dest.i0, i32 3
+; CHECK: %ptr0.i0 = extractelement <4 x float*> %ptr0, i32 0
+; CHECK: %ptr0.i2 = extractelement <4 x float*> %ptr0, i32 2
+; CHECK: %ptr0.i3 = extractelement <4 x float*> %ptr0, i32 3
+; CHECK: %i0.i1 = extractelement <4 x i32> %i0, i32 1
+; CHECK: %i0.i3 = extractelement <4 x i32> %i0, i32 3
+; CHECK: %val.i0 = getelementptr float, float* %ptr0.i0, i32 100
+; CHECK: %val.i1 = getelementptr float, float* %other, i32 %i0.i1
+; CHECK: %val.i2 = getelementptr float, float* %ptr0.i2, i32 100
+; CHECK: %val.i3 = getelementptr float, float* %ptr0.i3, i32 %i0.i3
+; CHECK: store float* %val.i0, float** %dest.i0, align 32
+; CHECK: store float* %val.i1, float** %dest.i1, align 8
+; CHECK: store float* %val.i2, float** %dest.i2, align 16
+; CHECK: store float* %val.i3, float** %dest.i3, align 8
+; CHECK: ret void
+  %i1 = insertelement <4 x i32> %i0, i32 100, i32 0
+  %i2 = insertelement <4 x i32> %i1, i32 100, i32 2
+  %ptr1 = insertelement <4 x float *> %ptr0, float *%other, i32 1
+  %val = getelementptr float, <4 x float *> %ptr1, <4 x i32> %i2
+  store <4 x float *> %val, <4 x float *> *%dest
+  ret void
+}
+
+; Test the handling of unaligned loads.
+define void @f9(<4 x float> *%dest, <4 x float> *%src) {
+; CHECK: @f9(
+; CHECK: %dest.i0 = bitcast <4 x float>* %dest to float*
+; CHECK: %dest.i1 = getelementptr float, float* %dest.i0, i32 1
+; CHECK: %dest.i2 = getelementptr float, float* %dest.i0, i32 2
+; CHECK: %dest.i3 = getelementptr float, float* %dest.i0, i32 3
+; CHECK: %src.i0 = bitcast <4 x float>* %src to float*
+; CHECK: %val.i0 = load float, float* %src.i0, align 4
+; CHECK: %src.i1 = getelementptr float, float* %src.i0, i32 1
+; CHECK: %val.i1 = load float, float* %src.i1, align 4
+; CHECK: %src.i2 = getelementptr float, float* %src.i0, i32 2
+; CHECK: %val.i2 = load float, float* %src.i2, align 4
+; CHECK: %src.i3 = getelementptr float, float* %src.i0, i32 3
+; CHECK: %val.i3 = load float, float* %src.i3, align 4
+; CHECK: store float %val.i0, float* %dest.i0, align 8
+; CHECK: store float %val.i1, float* %dest.i1, align 4
+; CHECK: store float %val.i2, float* %dest.i2, align 8
+; CHECK: store float %val.i3, float* %dest.i3, align 4
+; CHECK: ret void
+  %val = load <4 x float> , <4 x float> *%src, align 4
+  store <4 x float> %val, <4 x float> *%dest, align 8
+  ret void
+}
+
+; ...and again with subelement alignment.
+define void @f10(<4 x float> *%dest, <4 x float> *%src) {
+; CHECK: @f10(
+; CHECK: %dest.i0 = bitcast <4 x float>* %dest to float*
+; CHECK: %dest.i1 = getelementptr float, float* %dest.i0, i32 1
+; CHECK: %dest.i2 = getelementptr float, float* %dest.i0, i32 2
+; CHECK: %dest.i3 = getelementptr float, float* %dest.i0, i32 3
+; CHECK: %src.i0 = bitcast <4 x float>* %src to float*
+; CHECK: %val.i0 = load float, float* %src.i0, align 1
+; CHECK: %src.i1 = getelementptr float, float* %src.i0, i32 1
+; CHECK: %val.i1 = load float, float* %src.i1, align 1
+; CHECK: %src.i2 = getelementptr float, float* %src.i0, i32 2
+; CHECK: %val.i2 = load float, float* %src.i2, align 1
+; CHECK: %src.i3 = getelementptr float, float* %src.i0, i32 3
+; CHECK: %val.i3 = load float, float* %src.i3, align 1
+; CHECK: store float %val.i0, float* %dest.i0, align 2
+; CHECK: store float %val.i1, float* %dest.i1, align 2
+; CHECK: store float %val.i2, float* %dest.i2, align 2
+; CHECK: store float %val.i3, float* %dest.i3, align 2
+; CHECK: ret void
+  %val = load <4 x float> , <4 x float> *%src, align 1
+  store <4 x float> %val, <4 x float> *%dest, align 2
+  ret void
+}
+
+; Test that sub-byte loads aren't scalarized.
+define void @f11(<32 x i1> *%dest, <32 x i1> *%src0) {
+; CHECK: @f11(
+; CHECK: %val0 = load <32 x i1>, <32 x i1>* %src0
+; CHECK: %val1 = load <32 x i1>, <32 x i1>* %src1
+; CHECK: store <32 x i1> %and, <32 x i1>* %dest
+; CHECK: ret void
+  %src1 = getelementptr <32 x i1>, <32 x i1> *%src0, i32 1
+  %val0 = load <32 x i1> , <32 x i1> *%src0
+  %val1 = load <32 x i1> , <32 x i1> *%src1
+  %and = and <32 x i1> %val0, %val1
+  store <32 x i1> %and, <32 x i1> *%dest
+  ret void
+}
+
+; Test vector GEPs with more than one index.
+define void @f13(<4 x float *> *%dest, <4 x [4 x float] *> %ptr, <4 x i32> %i,
+                 float *%other) {
+; CHECK-LABEL: @f13(
+; CHECK: %dest.i0 = bitcast <4 x float*>* %dest to float**
+; CHECK: %dest.i1 = getelementptr float*, float** %dest.i0, i32 1
+; CHECK: %dest.i2 = getelementptr float*, float** %dest.i0, i32 2
+; CHECK: %dest.i3 = getelementptr float*, float** %dest.i0, i32 3
+; CHECK: %i.i0 = extractelement <4 x i32> %i, i32 0
+; CHECK: %ptr.i0 = extractelement <4 x [4 x float]*> %ptr, i32 0
+; CHECK: %val.i0 = getelementptr inbounds [4 x float], [4 x float]* %ptr.i0, i32 0, i32 %i.i0
+; CHECK: %i.i1 = extractelement <4 x i32> %i, i32 1
+; CHECK: %ptr.i1 = extractelement <4 x [4 x float]*> %ptr, i32 1
+; CHECK: %val.i1 = getelementptr inbounds [4 x float], [4 x float]* %ptr.i1, i32 1, i32 %i.i1
+; CHECK: %i.i2 = extractelement <4 x i32> %i, i32 2
+; CHECK: %ptr.i2 = extractelement <4 x [4 x float]*> %ptr, i32 2
+; CHECK: %val.i2 = getelementptr inbounds [4 x float], [4 x float]* %ptr.i2, i32 2, i32 %i.i2
+; CHECK: %i.i3 = extractelement <4 x i32> %i, i32 3
+; CHECK: %ptr.i3 = extractelement <4 x [4 x float]*> %ptr, i32 3
+; CHECK: %val.i3 = getelementptr inbounds [4 x float], [4 x float]* %ptr.i3, i32 3, i32 %i.i3
+; CHECK: store float* %val.i0, float** %dest.i0, align 32
+; CHECK: store float* %val.i1, float** %dest.i1, align 8
+; CHECK: store float* %val.i2, float** %dest.i2, align 16
+; CHECK: store float* %val.i3, float** %dest.i3, align 8
+; CHECK: ret void
+  %val = getelementptr inbounds [4 x float], <4 x [4 x float] *> %ptr,
+                                <4 x i32> <i32 0, i32 1, i32 2, i32 3>,
+                                <4 x i32> %i
+  store <4 x float *> %val, <4 x float *> *%dest
+  ret void
+}
+
+; Test combinations of vector and non-vector PHIs.
+define <4 x float> @f14(<4 x float> %acc, i32 %count) {
+; CHECK-LABEL: @f14(
+; CHECK: %this_acc.i0 = phi float [ %acc.i0, %entry ], [ %next_acc.i0, %loop ]
+; CHECK: %this_acc.i1 = phi float [ %acc.i1, %entry ], [ %next_acc.i1, %loop ]
+; CHECK: %this_acc.i2 = phi float [ %acc.i2, %entry ], [ %next_acc.i2, %loop ]
+; CHECK: %this_acc.i3 = phi float [ %acc.i3, %entry ], [ %next_acc.i3, %loop ]
+; CHECK: %this_count = phi i32 [ %count, %entry ], [ %next_count, %loop ]
+; CHECK: %this_acc.upto0 = insertelement <4 x float> undef, float %this_acc.i0, i32 0
+; CHECK: %this_acc.upto1 = insertelement <4 x float> %this_acc.upto0, float %this_acc.i1, i32 1
+; CHECK: %this_acc.upto2 = insertelement <4 x float> %this_acc.upto1, float %this_acc.i2, i32 2
+; CHECK: %this_acc = insertelement <4 x float> %this_acc.upto2, float %this_acc.i3, i32 3
+; CHECK: ret <4 x float> %next_acc
+entry:
+  br label %loop
+
+loop:
+  %this_acc = phi <4 x float> [ %acc, %entry ], [ %next_acc, %loop ]
+  %this_count = phi i32 [ %count, %entry ], [ %next_count, %loop ]
+  %foo = call <4 x float> @ext(<4 x float> %this_acc)
+  %next_acc = fadd <4 x float> %this_acc, %foo
+  %next_count = sub i32 %this_count, 1
+  %cmp = icmp eq i32 %next_count, 0
+  br i1 %cmp, label %loop, label %exit
+
+exit:
+  ret <4 x float> %next_acc
+}
+
+; Test unary operator scalarization.
+define void @f15(<4 x float> %init, <4 x float> *%base, i32 %count) {
+; CHECK-LABEL: @f15(
+; CHECK: %ptr = getelementptr <4 x float>, <4 x float>* %base, i32 %i
+; CHECK: %ptr.i0 = bitcast <4 x float>* %ptr to float*
+; CHECK: %val.i0 = load float, float* %ptr.i0, align 16
+; CHECK: %ptr.i1 = getelementptr float, float* %ptr.i0, i32 1
+; CHECK: %val.i1 = load float, float* %ptr.i1, align 4
+; CHECK: %ptr.i2 = getelementptr float, float* %ptr.i0, i32 2
+; CHECK: %val.i2 = load float, float* %ptr.i2, align 8
+; CHECK: %ptr.i3 = getelementptr float, float* %ptr.i0, i32 3
+; CHECK: %val.i3 = load float, float* %ptr.i3, align 4
+; CHECK: %neg.i0 = fneg float %val.i0
+; CHECK: %neg.i1 = fneg float %val.i1
+; CHECK: %neg.i2 = fneg float %val.i2
+; CHECK: %neg.i3 = fneg float %val.i3
+; CHECK: %neg.upto0 = insertelement <4 x float> undef, float %neg.i0, i32 0
+; CHECK: %neg.upto1 = insertelement <4 x float> %neg.upto0, float %neg.i1, i32 1
+; CHECK: %neg.upto2 = insertelement <4 x float> %neg.upto1, float %neg.i2, i32 2
+; CHECK: %neg = insertelement <4 x float> %neg.upto2, float %neg.i3, i32 3
+; CHECK: %call = call <4 x float> @ext(<4 x float> %neg)
+; CHECK: %call.i0 = extractelement <4 x float> %call, i32 0
+; CHECK: %cmp.i0 = fcmp ogt float %call.i0, 1.000000e+00
+; CHECK: %call.i1 = extractelement <4 x float> %call, i32 1
+; CHECK: %cmp.i1 = fcmp ogt float %call.i1, 2.000000e+00
+; CHECK: %call.i2 = extractelement <4 x float> %call, i32 2
+; CHECK: %cmp.i2 = fcmp ogt float %call.i2, 3.000000e+00
+; CHECK: %call.i3 = extractelement <4 x float> %call, i32 3
+; CHECK: %cmp.i3 = fcmp ogt float %call.i3, 4.000000e+00
+; CHECK: %sel.i0 = select i1 %cmp.i0, float %call.i0, float 5.000000e+00
+; CHECK: %sel.i1 = select i1 %cmp.i1, float %call.i1, float 6.000000e+00
+; CHECK: %sel.i2 = select i1 %cmp.i2, float %call.i2, float 7.000000e+00
+; CHECK: %sel.i3 = select i1 %cmp.i3, float %call.i3, float 8.000000e+00
+; CHECK: store float %sel.i0, float* %ptr.i0, align 16
+; CHECK: store float %sel.i1, float* %ptr.i1, align 4
+; CHECK: store float %sel.i2, float* %ptr.i2, align 8
+; CHECK: store float %sel.i3, float* %ptr.i3, align 4
+entry:
+  br label %loop
+
+loop:
+  %i = phi i32 [ %count, %entry ], [ %nexti, %loop ]
+  %acc = phi <4 x float> [ %init, %entry ], [ %sel, %loop ]
+  %nexti = sub i32 %i, 1
+
+  %ptr = getelementptr <4 x float>, <4 x float> *%base, i32 %i
+  %val = load <4 x float> , <4 x float> *%ptr
+  %neg = fneg <4 x float> %val
+  %call = call <4 x float> @ext(<4 x float> %neg)
+  %cmp = fcmp ogt <4 x float> %call,
+  <float 1.0, float 2.0, float 3.0, float 4.0>
+  %sel = select <4 x i1> %cmp, <4 x float> %call,
+  <4 x float> <float 5.0, float 6.0, float 7.0, float 8.0>
+  store <4 x float> %sel, <4 x float> *%ptr
+
+  %test = icmp eq i32 %nexti, 0
+  br i1 %test, label %loop, label %exit
+
+exit:
+  ret void
+}
+
+; Check that IR flags are preserved.
+define <2 x i32> @f16(<2 x i32> %i, <2 x i32> %j) {
+; CHECK-LABEL: @f16(
+; CHECK: %res.i0 = add nuw nsw i32
+; CHECK: %res.i1 = add nuw nsw i32
+  %res = add nuw nsw <2 x i32> %i, %j
+  ret <2 x i32> %res
+}
+define <2 x i32> @f17(<2 x i32> %i, <2 x i32> %j) {
+; CHECK-LABEL: @f17(
+; CHECK: %res.i0 = sdiv exact i32
+; CHECK: %res.i1 = sdiv exact i32
+  %res = sdiv exact <2 x i32> %i, %j
+  ret <2 x i32> %res
+}
+define <2 x float> @f18(<2 x float> %x, <2 x float> %y) {
+; CHECK-LABEL: @f18(
+; CHECK: %res.i0 = fadd fast float
+; CHECK: %res.i1 = fadd fast float
+  %res = fadd fast <2 x float> %x, %y
+  ret <2 x float> %res
+}
+define <2 x float> @f19(<2 x float> %x) {
+; CHECK-LABEL: @f19(
+; CHECK: %res.i0 = fneg fast float
+; CHECK: %res.i1 = fneg fast float
+  %res = fneg fast <2 x float> %x
+  ret <2 x float> %res
+}
+define <2 x i1> @f20(<2 x float> %x, <2 x float> %y) {
+; CHECK-LABEL: @f20(
+; CHECK: %res.i0 = fcmp fast ogt float
+; CHECK: %res.i1 = fcmp fast ogt float
+  %res = fcmp fast ogt <2 x float> %x, %y
+  ret <2 x i1> %res
+}
+declare <2 x float> @llvm.sqrt.v2f32(<2 x float>)
+define <2 x float> @f21(<2 x float> %x) {
+; CHECK-LABEL: @f21(
+; CHECK: %res.i0 = call fast float @llvm.sqrt.f32
+; CHECK: %res.i1 = call fast float @llvm.sqrt.f32
+  %res = call fast <2 x float> @llvm.sqrt.v2f32(<2 x float> %x)
+  ret <2 x float> %res
+}
+declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>)
+define <2 x float> @f22(<2 x float> %x, <2 x float> %y, <2 x float> %z) {
+; CHECK-LABEL: @f22(
+; CHECK: %res.i0 = call fast float @llvm.fma.f32
+; CHECK: %res.i1 = call fast float @llvm.fma.f32
+  %res = call fast <2 x float> @llvm.fma.v2f32(<2 x float> %x, <2 x float> %y, <2 x float> %z)
+  ret <2 x float> %res
+}
+
+; See https://reviews.llvm.org/D83101#2133062
+define <2 x i32> @f23_crash(<2 x i32> %srcvec, i32 %v1) {
+; CHECK-LABEL: @f23_crash(
+; CHECK: %v0 = extractelement <2 x i32> %srcvec, i32 0
+; CHECK: %t1.upto0 = insertelement <2 x i32> undef, i32 %v0, i32 0
+; CHECK: %t1 = insertelement <2 x i32> %t1.upto0, i32 %v1, i32 1
+; CHECK: ret <2 x i32> %t1
+  %v0 = extractelement <2 x i32> %srcvec, i32 0
+  %t0 = insertelement <2 x i32> poison, i32 %v0, i32 0
+  %t1 = insertelement <2 x i32> %t0, i32 %v1, i32 1
+  ret <2 x i32> %t1
+}
+
+!0 = !{ !"root" }
+!1 = !{ !"set1", !0 }
+!2 = !{ !"set2", !0 }
+!3 = !{ !3, !{!"llvm.loop.parallel_accesses", !13} }
+!4 = !{ float 4.0 }
+!5 = !{ i64 0, i64 8, null }
+!13 = distinct !{}
diff --git a/llvm/test/Transforms/Scalarizer/dbgloc-bug-inseltpoison.ll b/llvm/test/Transforms/Scalarizer/dbgloc-bug-inseltpoison.ll
new file mode 100644
index 0000000000000..718018b28523e
--- /dev/null
+++ b/llvm/test/Transforms/Scalarizer/dbgloc-bug-inseltpoison.ll
@@ -0,0 +1,44 @@
+; RUN: opt -S -march=x86 -scalarizer %s | FileCheck %s
+; RUN: opt -S -march=x86 -passes='function(scalarizer)' %s | FileCheck %s
+
+; Reproducer for pr27938
+; https://llvm.org/bugs/show_bug.cgi?id=27938
+
+define i16 @f1() !dbg !5 {
+  ret i16 undef, !dbg !9
+}
+
+define void @f2() !dbg !10 {
+bb1:
+  %_tmp7 = tail call i16 @f1(), !dbg !13
+; CHECK: call i16 @f1(), !dbg !13
+  %broadcast.splatinsert5 = insertelement <4 x i16> poison, i16 %_tmp7, i32 0
+  %broadcast.splat6 = shufflevector <4 x i16> %broadcast.splatinsert5, <4 x i16> undef, <4 x i32> zeroinitializer
+  br label %vector.body
+
+vector.body:
+  br i1 undef, label %middle.block, label %vector.body
+
+middle.block:
+  ret void, !dbg !15
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!3, !4}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, enums: !2, retainedTypes: !2)
+!1 = !DIFile(filename: "dbgloc-bug.c", directory: ".")
+!2 = !{}
+!3 = !{i32 2, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = distinct !DISubprogram(name: "f1", scope: !1, file: !1, line: 9, type: !6, isLocal: false, isDefinition: true, scopeLine: 10, isOptimized: true, unit: !0, retainedNodes: !2)
+!6 = !DISubroutineType(types: !7)
+!7 = !{!8}
+!8 = !DIBasicType(name: "short", size: 16, align: 16, encoding: DW_ATE_signed)
+!9 = !DILocation(line: 11, column: 5, scope: !5)
+!10 = distinct !DISubprogram(name: "f2", scope: !1, file: !1, line: 14, type: !11, isLocal: false, isDefinition: true, scopeLine: 15, isOptimized: true, unit: !0, retainedNodes: !2)
+!11 = !DISubroutineType(types: !12)
+!12 = !{null}
+!13 = !DILocation(line: 24, column: 9, scope: !14)
+!14 = !DILexicalBlock(scope: !10, file: !1, line: 17, column: 5)
+!15 = !DILocation(line: 28, column: 1, scope: !10)
diff --git a/llvm/test/Transforms/Scalarizer/order-bug-inseltpoison.ll b/llvm/test/Transforms/Scalarizer/order-bug-inseltpoison.ll
new file mode 100644
index 0000000000000..fd7e009166efc
--- /dev/null
+++ b/llvm/test/Transforms/Scalarizer/order-bug-inseltpoison.ll
@@ -0,0 +1,24 @@
+; RUN: opt %s -scalarizer -S -o - | FileCheck %s
+; RUN: opt %s -passes='function(scalarizer)' -S -o - | FileCheck %s
+
+; This input caused the scalarizer to replace & erase gathered results when 
+; future gathered results depended on them being alive
+
+define dllexport spir_func <4 x i32> @main(float %a) {
+entry:
+  %i = insertelement <4 x float> poison, float %a, i32 0
+  br label %z
+
+y:
+; CHECK: %f.upto0 = insertelement <4 x i32> undef, i32 %b.i0, i32 0
+; CHECK: %f.upto1 = insertelement <4 x i32> %f.upto0, i32 %b.i0, i32 1
+; CHECK: %f.upto2 = insertelement <4 x i32> %f.upto1, i32 %b.i0, i32 2
+; CHECK: %f = insertelement <4 x i32> %f.upto2, i32 %b.i0, i32 3
+  %f = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %f
+
+z:
+; CHECK: %b.i0 = bitcast float %a to i32
+  %b = bitcast <4 x float> %i to <4 x i32>
+  br label %y
+}
diff --git a/llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-ops-inseltpoison.ll b/llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-ops-inseltpoison.ll
new file mode 100644
index 0000000000000..b50abd6ad1827
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-ops-inseltpoison.ll
@@ -0,0 +1,112 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -mtriple=thumbv8.1m.main -mattr=+mve -S %s -o - | FileCheck %s --check-prefix=CHECK-MVE
+; RUN: opt -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -mtriple=thumbv8.1m.main -S %s -o - | FileCheck %s --check-prefix=CHECK-NOMVE
+
+define i32 @speculate_vector_extract(i32 %d, <4 x i32> %v) {
+; CHECK-MVE-LABEL: @speculate_vector_extract(
+; CHECK-MVE-NEXT:  entry:
+; CHECK-MVE-NEXT:    [[CONV:%.*]] = insertelement <4 x i32> poison, i32 [[D:%.*]], i32 0
+; CHECK-MVE-NEXT:    [[CONV2:%.*]] = insertelement <4 x i32> [[CONV]], i32 [[D]], i32 1
+; CHECK-MVE-NEXT:    [[CONV3:%.*]] = insertelement <4 x i32> [[CONV2]], i32 [[D]], i32 2
+; CHECK-MVE-NEXT:    [[CONV4:%.*]] = insertelement <4 x i32> [[CONV3]], i32 [[D]], i32 3
+; CHECK-MVE-NEXT:    [[TMP6:%.*]] = add nsw <4 x i32> [[CONV4]], <i32 0, i32 -1, i32 -2, i32 -3>
+; CHECK-MVE-NEXT:    [[CMP:%.*]] = icmp eq <4 x i32> [[TMP6]], zeroinitializer
+; CHECK-MVE-NEXT:    [[CMP_EXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
+; CHECK-MVE-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 0
+; CHECK-MVE-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[TMP8]], 0
+; CHECK-MVE-NEXT:    br i1 [[TOBOOL]], label [[COND_ELSE:%.*]], label [[COND_THEN:%.*]]
+; CHECK-MVE:       cond.then:
+; CHECK-MVE-NEXT:    [[TMP10:%.*]] = extractelement <4 x i32> [[V:%.*]], i32 0
+; CHECK-MVE-NEXT:    br label [[COND_END:%.*]]
+; CHECK-MVE:       cond.else:
+; CHECK-MVE-NEXT:    [[TMP12:%.*]] = extractelement <4 x i32> [[V]], i32 3
+; CHECK-MVE-NEXT:    br label [[COND_END]]
+; CHECK-MVE:       cond.end:
+; CHECK-MVE-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_THEN]] ], [ [[TMP12]], [[COND_ELSE]] ]
+; CHECK-MVE-NEXT:    [[TMP14:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 1
+; CHECK-MVE-NEXT:    [[TOBOOL15:%.*]] = icmp eq i32 [[TMP14]], 0
+; CHECK-MVE-NEXT:    [[TMP20:%.*]] = extractelement <4 x i32> [[V]], i32 1
+; CHECK-MVE-NEXT:    [[COND22:%.*]] = select i1 [[TOBOOL15]], i32 [[COND]], i32 [[TMP20]]
+; CHECK-MVE-NEXT:    [[TMP24:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 2
+; CHECK-MVE-NEXT:    [[TOBOOL25:%.*]] = icmp eq i32 [[TMP24]], 0
+; CHECK-MVE-NEXT:    [[TMP30:%.*]] = extractelement <4 x i32> [[V]], i32 2
+; CHECK-MVE-NEXT:    [[COND32:%.*]] = select i1 [[TOBOOL25]], i32 [[COND22]], i32 [[TMP30]]
+; CHECK-MVE-NEXT:    ret i32 [[COND32]]
+;
+; CHECK-NOMVE-LABEL: @speculate_vector_extract(
+; CHECK-NOMVE-NEXT:  entry:
+; CHECK-NOMVE-NEXT:    [[CONV:%.*]] = insertelement <4 x i32> poison, i32 [[D:%.*]], i32 0
+; CHECK-NOMVE-NEXT:    [[CONV2:%.*]] = insertelement <4 x i32> [[CONV]], i32 [[D]], i32 1
+; CHECK-NOMVE-NEXT:    [[CONV3:%.*]] = insertelement <4 x i32> [[CONV2]], i32 [[D]], i32 2
+; CHECK-NOMVE-NEXT:    [[CONV4:%.*]] = insertelement <4 x i32> [[CONV3]], i32 [[D]], i32 3
+; CHECK-NOMVE-NEXT:    [[TMP6:%.*]] = add nsw <4 x i32> [[CONV4]], <i32 0, i32 -1, i32 -2, i32 -3>
+; CHECK-NOMVE-NEXT:    [[CMP:%.*]] = icmp eq <4 x i32> [[TMP6]], zeroinitializer
+; CHECK-NOMVE-NEXT:    [[CMP_EXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
+; CHECK-NOMVE-NEXT:    [[TMP8:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 0
+; CHECK-NOMVE-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[TMP8]], 0
+; CHECK-NOMVE-NEXT:    [[TMP10:%.*]] = extractelement <4 x i32> [[V:%.*]], i32 0
+; CHECK-NOMVE-NEXT:    [[TMP12:%.*]] = extractelement <4 x i32> [[V]], i32 3
+; CHECK-NOMVE-NEXT:    [[COND:%.*]] = select i1 [[TOBOOL]], i32 [[TMP12]], i32 [[TMP10]]
+; CHECK-NOMVE-NEXT:    [[TMP14:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 1
+; CHECK-NOMVE-NEXT:    [[TOBOOL15:%.*]] = icmp eq i32 [[TMP14]], 0
+; CHECK-NOMVE-NEXT:    [[TMP20:%.*]] = extractelement <4 x i32> [[V]], i32 1
+; CHECK-NOMVE-NEXT:    [[COND22:%.*]] = select i1 [[TOBOOL15]], i32 [[COND]], i32 [[TMP20]]
+; CHECK-NOMVE-NEXT:    [[TMP24:%.*]] = extractelement <4 x i32> [[CMP_EXT]], i32 2
+; CHECK-NOMVE-NEXT:    [[TOBOOL25:%.*]] = icmp eq i32 [[TMP24]], 0
+; CHECK-NOMVE-NEXT:    [[TMP30:%.*]] = extractelement <4 x i32> [[V]], i32 2
+; CHECK-NOMVE-NEXT:    [[COND32:%.*]] = select i1 [[TOBOOL25]], i32 [[COND22]], i32 [[TMP30]]
+; CHECK-NOMVE-NEXT:    ret i32 [[COND32]]
+;
+entry:
+  %conv = insertelement <4 x i32> poison, i32 %d, i32 0
+  %conv2 = insertelement <4 x i32> %conv, i32 %d, i32 1
+  %conv3 = insertelement <4 x i32> %conv2, i32 %d, i32 2
+  %conv4 = insertelement <4 x i32> %conv3, i32 %d, i32 3
+  %tmp6 = add nsw <4 x i32> %conv4, <i32 0, i32 -1, i32 -2, i32 -3>
+  %cmp = icmp eq <4 x i32> %tmp6, zeroinitializer
+  %cmp.ext = sext <4 x i1> %cmp to <4 x i32>
+  %tmp8 = extractelement <4 x i32> %cmp.ext, i32 0
+  %tobool = icmp eq i32 %tmp8, 0
+  br i1 %tobool, label %cond.else, label %cond.then
+
+return:                                           ; preds = %cond.end28
+  ret i32 %cond32
+
+cond.then:                                        ; preds = %entry
+  %tmp10 = extractelement <4 x i32> %v, i32 0
+  br label %cond.end
+
+cond.else:                                        ; preds = %entry
+  %tmp12 = extractelement <4 x i32> %v, i32 3
+  br label %cond.end
+
+cond.end:                                         ; preds = %cond.else, %cond.then
+  %cond = phi i32 [ %tmp10, %cond.then ], [ %tmp12, %cond.else ]
+  %tmp14 = extractelement <4 x i32> %cmp.ext, i32 1
+  %tobool15 = icmp eq i32 %tmp14, 0
+  br i1 %tobool15, label %cond.else17, label %cond.then16
+
+cond.then16:                                      ; preds = %cond.end
+  %tmp20 = extractelement <4 x i32> %v, i32 1
+  br label %cond.end18
+
+cond.else17:                                      ; preds = %cond.end
+  br label %cond.end18
+
+cond.end18:                                       ; preds = %cond.else17, %cond.then16
+  %cond22 = phi i32 [ %tmp20, %cond.then16 ], [ %cond, %cond.else17 ]
+  %tmp24 = extractelement <4 x i32> %cmp.ext, i32 2
+  %tobool25 = icmp eq i32 %tmp24, 0
+  br i1 %tobool25, label %cond.else27, label %cond.then26
+
+cond.then26:                                      ; preds = %cond.end18
+  %tmp30 = extractelement <4 x i32> %v, i32 2
+  br label %cond.end28
+
+cond.else27:                                      ; preds = %cond.end18
+  br label %cond.end28
+
+cond.end28:                                       ; preds = %cond.else27, %cond.then26
+  %cond32 = phi i32 [ %tmp30, %cond.then26 ], [ %cond22, %cond.else27 ]
+  br label %return
+}
diff --git a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
index 3a70241fed167..7455cc691cf9e 100644
--- a/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
+++ b/llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll
@@ -836,3 +836,57 @@ for.bodythread-pre-split.loopback:
 if.end.loopexit:
   ret void
 }
+
+@f.b = external global i16, align 1
+define void @pr48450_3() {
+; CHECK-LABEL: @pr48450_3(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br label [[FOR_COND1:%.*]]
+; CHECK:       for.cond1:
+; CHECK-NEXT:    [[V:%.*]] = load i16, i16* @f.b, align 1
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i16 [[V]], 1
+; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT:    br label [[FOR_COND1]]
+;
+entry:
+  br label %for.cond1
+
+for.cond1:
+  %v = load i16, i16* @f.b, align 1
+  %cmp = icmp slt i16 %v, 1
+  br i1 %cmp, label %for.body, label %for.end
+
+for.body:
+  br label %for.cond1
+
+for.end:
+  %tobool = icmp ne i16 %v, 0
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+  unreachable
+
+if.end:
+  br label %for.cond2
+
+for.cond2:
+  %c.0 = phi i16 [ undef, %if.end ], [ %inc, %if.end7 ]
+  %cmp3 = icmp slt i16 %c.0, 1
+  br i1 %cmp3, label %for.body4, label %for.cond.cleanup
+
+for.cond.cleanup:
+  br label %cleanup
+
+for.body4:
+  br i1 undef, label %if.then6, label %if.end7
+
+if.then6:
+  br label %cleanup
+
+if.end7:
+  %inc = add nsw i16 %c.0, 1
+  br label %for.cond2
+
+cleanup:
+  unreachable
+}
diff --git a/llvm/test/Transforms/SimplifyCFG/speculate-vector-ops-inseltpoison.ll b/llvm/test/Transforms/SimplifyCFG/speculate-vector-ops-inseltpoison.ll
new file mode 100644
index 0000000000000..7a694481f149f
--- /dev/null
+++ b/llvm/test/Transforms/SimplifyCFG/speculate-vector-ops-inseltpoison.ll
@@ -0,0 +1,60 @@
+; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
+
+define i32 @speculate_vector_extract(i32 %d, <4 x i32> %v) #0 {
+; CHECK-LABEL: @speculate_vector_extract(
+; CHECK-NOT: br
+entry:
+  %conv = insertelement <4 x i32> poison, i32 %d, i32 0
+  %conv2 = insertelement <4 x i32> %conv, i32 %d, i32 1
+  %conv3 = insertelement <4 x i32> %conv2, i32 %d, i32 2
+  %conv4 = insertelement <4 x i32> %conv3, i32 %d, i32 3
+  %tmp6 = add nsw <4 x i32> %conv4, <i32 0, i32 -1, i32 -2, i32 -3>
+  %cmp = icmp eq <4 x i32> %tmp6, zeroinitializer
+  %cmp.ext = sext <4 x i1> %cmp to <4 x i32>
+  %tmp8 = extractelement <4 x i32> %cmp.ext, i32 0
+  %tobool = icmp eq i32 %tmp8, 0
+  br i1 %tobool, label %cond.else, label %cond.then
+
+return:                                           ; preds = %cond.end28
+  ret i32 %cond32
+
+cond.then:                                        ; preds = %entry
+  %tmp10 = extractelement <4 x i32> %v, i32 0
+  br label %cond.end
+
+cond.else:                                        ; preds = %entry
+  %tmp12 = extractelement <4 x i32> %v, i32 3
+  br label %cond.end
+
+cond.end:                                         ; preds = %cond.else, %cond.then
+  %cond = phi i32 [ %tmp10, %cond.then ], [ %tmp12, %cond.else ]
+  %tmp14 = extractelement <4 x i32> %cmp.ext, i32 1
+  %tobool15 = icmp eq i32 %tmp14, 0
+  br i1 %tobool15, label %cond.else17, label %cond.then16
+
+cond.then16:                                      ; preds = %cond.end
+  %tmp20 = extractelement <4 x i32> %v, i32 1
+  br label %cond.end18
+
+cond.else17:                                      ; preds = %cond.end
+  br label %cond.end18
+
+cond.end18:                                       ; preds = %cond.else17, %cond.then16
+  %cond22 = phi i32 [ %tmp20, %cond.then16 ], [ %cond, %cond.else17 ]
+  %tmp24 = extractelement <4 x i32> %cmp.ext, i32 2
+  %tobool25 = icmp eq i32 %tmp24, 0
+  br i1 %tobool25, label %cond.else27, label %cond.then26
+
+cond.then26:                                      ; preds = %cond.end18
+  %tmp30 = extractelement <4 x i32> %v, i32 2
+  br label %cond.end28
+
+cond.else27:                                      ; preds = %cond.end18
+  br label %cond.end28
+
+cond.end28:                                       ; preds = %cond.else27, %cond.then26
+  %cond32 = phi i32 [ %tmp30, %cond.then26 ], [ %cond22, %cond.else27 ]
+  br label %return
+}
+
+attributes #0 = { nounwind }
diff --git a/llvm/test/Transforms/SpeculativeExecution/spec-other-inseltpoison.ll b/llvm/test/Transforms/SpeculativeExecution/spec-other-inseltpoison.ll
new file mode 100644
index 0000000000000..c2eb266abbb09
--- /dev/null
+++ b/llvm/test/Transforms/SpeculativeExecution/spec-other-inseltpoison.ll
@@ -0,0 +1,88 @@
+; RUN: opt < %s -S -speculative-execution \
+; RUN:   -spec-exec-max-speculation-cost 4 -spec-exec-max-not-hoisted 3 \
+; RUN:   | FileCheck %s
+
+; CHECK-LABEL: @ifThen_shuffle(
+; CHECK: shufflevector
+; CHECK: br i1 true
+define void @ifThen_shuffle() {
+  br i1 true, label %a, label %b
+
+a:
+  %x = shufflevector <2 x float> undef, <2 x float> undef, <2 x i32> zeroinitializer
+  br label %b
+
+b:
+  ret void
+}
+
+; CHECK-LABEL: @ifThen_extract(
+; CHECK: extractelement
+; CHECK: br i1 true
+define void @ifThen_extract() {
+  br i1 true, label %a, label %b
+
+a:
+  %x = extractelement <2 x float> undef, i32 1
+  br label %b
+
+b:
+  ret void
+}
+
+
+; CHECK-LABEL: @ifThen_insert(
+; CHECK: insertelement
+; CHECK: br i1 true
+define void @ifThen_insert() {
+  br i1 true, label %a, label %b
+
+a:
+  %x = insertelement <2 x float> poison, float undef, i32 1
+  br label %b
+
+b:
+  ret void
+}
+
+; CHECK-LABEL: @ifThen_extractvalue(
+; CHECK: extractvalue
+; CHECK: br i1 true
+define void @ifThen_extractvalue() {
+  br i1 true, label %a, label %b
+
+a:
+  %x = extractvalue { i32, i32 } undef, 0
+  br label %b
+
+b:
+  ret void
+}
+
+; CHECK-LABEL: @ifThen_insertvalue(
+; CHECK: insertvalue
+; CHECK: br i1 true
+define void @ifThen_insertvalue() {
+  br i1 true, label %a, label %b
+
+a:
+  %x = insertvalue { i32, i32 } undef, i32 undef, 0
+  br label %b
+
+b:
+  ret void
+}
+
+; CHECK-LABEL: @ifThen_freeze(
+; CHECK: freeze
+; CHECK: br i1 true
+define void @ifThen_freeze() {
+  br i1 true, label %a, label %b
+
+a:
+  %x = freeze i32 undef
+  br label %b
+
+b:
+  ret void
+}
diff --git a/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll b/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
new file mode 100644
index 0000000000000..392dfd4620eeb
--- /dev/null
+++ b/llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-inseltpoison.ll
@@ -0,0 +1,53 @@
+; RUN: opt -o /dev/null -structurizecfg %s
+
+; The following function caused an infinite loop inside the structurizer's
+; rebuildSSA routine, where we were iterating over an instruction's uses while
+; modifying the use list, without taking care to do this safely.
+
+target triple = "amdgcn--"
+
+define amdgpu_vs void @wrapper(i32 inreg %arg, i32 %arg1) {
+main_body:
+  %tmp = add i32 %arg1, %arg
+  %tmp2 = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> undef, i32 %tmp, i32 0, i32 0, i32 0)
+  %tmp3 = extractelement <4 x float> %tmp2, i32 1
+  %tmp4 = fptosi float %tmp3 to i32
+  %tmp5 = insertelement <2 x i32> poison, i32 %tmp4, i32 1
+  br label %loop11.i
+
+loop11.i:                                         ; preds = %endif46.i, %main_body
+  %tmp6 = phi i32 [ 0, %main_body ], [ %tmp14, %endif46.i ]
+  %tmp7 = icmp sgt i32 %tmp6, 999
+  br i1 %tmp7, label %main.exit, label %if16.i
+
+if16.i:                                           ; preds = %loop11.i
+  %tmp8 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp5, <8 x i32> undef, i32 15, i1 true, i1 false, i1 false, i1 false)
+  %tmp9 = extractelement <4 x float> %tmp8, i32 0
+  %tmp10 = fcmp ult float 0.000000e+00, %tmp9
+  br i1 %tmp10, label %if28.i, label %endif46.i
+
+if28.i:                                           ; preds = %if16.i
+  %tmp11 = bitcast float %tmp9 to i32
+  %tmp12 = shl i32 %tmp11, 16
+  %tmp13 = bitcast i32 %tmp12 to float
+  br label %main.exit
+
+endif46.i:                                        ; preds = %if16.i
+  %tmp14 = add i32 %tmp6, 1
+  br label %loop11.i
+
+main.exit:                                        ; preds = %if28.i, %loop11.i
+  %tmp15 = phi float [ %tmp13, %if28.i ], [ 0x36F0800000000000, %loop11.i ]
+  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp15, float 0.000000e+00, float 0.000000e+00, float 0x36A0000000000000, i1 false, i1 false) #0
+  ret void
+}
+
+; Function Attrs: nounwind
+declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
+
+declare <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32>, i32, i32, i32, i32 immarg) #2
+declare <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind readonly }
diff --git a/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
new file mode 100644
index 0000000000000..51d5f71e55369
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltpoison.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s --check-prefixes=CHECK
+
+; ModuleID = 'load-as-transition.ll'
+target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
+target triple = "amdgcn-amd-amdhsa"
+
+%struct.hoge = type { float }
+
+define protected amdgpu_kernel void @load_from_other_as(<4 x float>* nocapture nonnull %resultptr) local_unnamed_addr #0 {
+; CHECK-LABEL: @load_from_other_as(
+; CHECK-NEXT:  bb:
+; CHECK-NEXT:    [[A:%.*]] = alloca [[STRUCT_HOGE:%.*]], align 4, addrspace(5)
+; CHECK-NEXT:    [[B:%.*]] = addrspacecast [[STRUCT_HOGE]] addrspace(5)* [[A]] to %struct.hoge*
+; CHECK-NEXT:    [[C:%.*]] = getelementptr inbounds [[STRUCT_HOGE]], %struct.hoge* [[B]], i64 0, i32 0
+; CHECK-NEXT:    [[TMP0:%.*]] = bitcast float* [[C]] to <1 x float>*
+; CHECK-NEXT:    [[TMP1:%.*]] = load <1 x float>, <1 x float>* [[TMP0]], align 4
+; CHECK-NEXT:    [[E:%.*]] = shufflevector <1 x float> [[TMP1]], <1 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    store <4 x float> [[E]], <4 x float>* [[RESULTPTR:%.*]], align 16
+; CHECK-NEXT:    ret void
+;
+bb:
+  %a = alloca %struct.hoge, align 4, addrspace(5)
+  %b = addrspacecast %struct.hoge addrspace(5)* %a to %struct.hoge*
+  %c = getelementptr inbounds %struct.hoge, %struct.hoge* %b, i64 0, i32 0
+  %d = load float, float* %c, align 4
+  %e = insertelement <4 x float> poison, float %d, i32 0
+  store <4 x float> %e, <4 x float>* %resultptr, align 16
+  ret void
+}
+
+attributes #0 = { "use-soft-float"="false" }
+
+!llvm.ident = !{!0}
+
+!0 = !{!"clang version 12.0.0"}
diff --git a/llvm/test/Transforms/VectorCombine/Hexagon/load-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/Hexagon/load-inseltpoison.ll
new file mode 100644
index 0000000000000..da19dcf53fcca
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/Hexagon/load-inseltpoison.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=hexagon-- | FileCheck %s --check-prefixes=CHECK
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+; This would crash because TTI returns "0" for vector length.
+
+define <4 x float> @load_f32_insert_v4f32(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_f32_insert_v4f32(
+; CHECK-NEXT:    [[S:%.*]] = load float, float* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> poison, float [[S]], i32 0
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %s = load float, float* %p, align 4
+  %r = insertelement <4 x float> poison, float %s, i32 0
+  ret <4 x float> %r
+}
diff --git a/llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
new file mode 100644
index 0000000000000..c182b35f55393
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll
@@ -0,0 +1,575 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=SSE2 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=AVX2 | FileCheck %s --check-prefixes=CHECK,AVX
+
+declare void @use_i8(i8)
+declare void @use_f32(float)
+
+; Eliminating extract is profitable.
+
+define i8 @ext0_ext0_add(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @ext0_ext0_add(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <16 x i8> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <16 x i8> [[TMP1]], i32 0
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 0
+  %e1 = extractelement <16 x i8> %y, i32 0
+  %r = add i8 %e0, %e1
+  ret i8 %r
+}
+
+; Eliminating extract is still profitable. Flags propagate.
+
+define i8 @ext1_ext1_add_flags(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @ext1_ext1_add_flags(
+; CHECK-NEXT:    [[TMP1:%.*]] = add nuw nsw <16 x i8> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <16 x i8> [[TMP1]], i32 1
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 1
+  %e1 = extractelement <16 x i8> %y, i32 1
+  %r = add nsw nuw i8 %e0, %e1
+  ret i8 %r
+}
+
+; Negative test - eliminating extract is profitable, but vector shift is expensive.
+
+define i8 @ext1_ext1_shl(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @ext1_ext1_shl(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 1
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[R:%.*]] = shl i8 [[E0]], [[E1]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 1
+  %e1 = extractelement <16 x i8> %y, i32 1
+  %r = shl i8 %e0, %e1
+  ret i8 %r
+}
+
+; Negative test - eliminating extract is profitable, but vector multiply is expensive.
+
+define i8 @ext13_ext13_mul(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @ext13_ext13_mul(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 13
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 13
+; CHECK-NEXT:    [[R:%.*]] = mul i8 [[E0]], [[E1]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 13
+  %e1 = extractelement <16 x i8> %y, i32 13
+  %r = mul i8 %e0, %e1
+  ret i8 %r
+}
+
+; Negative test - cost is irrelevant because sdiv has potential UB.
+
+define i8 @ext0_ext0_sdiv(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @ext0_ext0_sdiv(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = sdiv i8 [[E0]], [[E1]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 0
+  %e1 = extractelement <16 x i8> %y, i32 0
+  %r = sdiv i8 %e0, %e1
+  ret i8 %r
+}
+
+; Extracts are free and vector op has same cost as scalar, but we
+; speculatively transform to vector to create more optimization
+; opportunities..
+
+define double @ext0_ext0_fadd(<2 x double> %x, <2 x double> %y) {
+; CHECK-LABEL: @ext0_ext0_fadd(
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <2 x double> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
+; CHECK-NEXT:    ret double [[R]]
+;
+  %e0 = extractelement <2 x double> %x, i32 0
+  %e1 = extractelement <2 x double> %y, i32 0
+  %r = fadd double %e0, %e1
+  ret double %r
+}
+
+; Eliminating extract is profitable. Flags propagate.
+
+define double @ext1_ext1_fsub(<2 x double> %x, <2 x double> %y) {
+; CHECK-LABEL: @ext1_ext1_fsub(
+; CHECK-NEXT:    [[TMP1:%.*]] = fsub fast <2 x double> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <2 x double> [[TMP1]], i32 1
+; CHECK-NEXT:    ret double [[R]]
+;
+  %e0 = extractelement <2 x double> %x, i32 1
+  %e1 = extractelement <2 x double> %y, i32 1
+  %r = fsub fast double %e0, %e1
+  ret double %r
+}
+
+; Negative test - type mismatch.
+
+define double @ext1_ext1_fadd_different_types(<2 x double> %x, <4 x double> %y) {
+; CHECK-LABEL: @ext1_ext1_fadd_different_types(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <2 x double> [[X:%.*]], i32 1
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <4 x double> [[Y:%.*]], i32 1
+; CHECK-NEXT:    [[R:%.*]] = fadd fast double [[E0]], [[E1]]
+; CHECK-NEXT:    ret double [[R]]
+;
+  %e0 = extractelement <2 x double> %x, i32 1
+  %e1 = extractelement <4 x double> %y, i32 1
+  %r = fadd fast double %e0, %e1
+  ret double %r
+}
+
+; Disguised same vector operand; scalar code is not cheaper (with default
+; x86 target), so aggressively form vector binop.
+
+define i32 @ext1_ext1_add_same_vec(<4 x i32> %x) {
+; CHECK-LABEL: @ext1_ext1_add_same_vec(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], [[X]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %e0 = extractelement <4 x i32> %x, i32 1
+  %e1 = extractelement <4 x i32> %x, i32 1
+  %r = add i32 %e0, %e1
+  ret i32 %r
+}
+
+; Functionally equivalent to above test; should transform as above.
+
+define i32 @ext1_ext1_add_same_vec_cse(<4 x i32> %x) {
+; CHECK-LABEL: @ext1_ext1_add_same_vec_cse(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], [[X]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %e0 = extractelement <4 x i32> %x, i32 1
+  %r = add i32 %e0, %e0
+  ret i32 %r
+}
+
+; Don't assert if extract indices have different types.
+
+define i32 @ext1_ext1_add_same_vec_diff_idx_ty(<4 x i32> %x) {
+; CHECK-LABEL: @ext1_ext1_add_same_vec_diff_idx_ty(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[X:%.*]], [[X]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x i32> [[TMP1]], i32 1
+; CHECK-NEXT:    ret i32 [[R]]
+;
+  %e0 = extractelement <4 x i32> %x, i32 1
+  %e1 = extractelement <4 x i32> %x, i64 1
+  %r = add i32 %e0, %e1
+  ret i32 %r
+}
+
+; Negative test - same vector operand; scalar code is cheaper than general case
+;                 and vector code would be more expensive still.
+
+define i8 @ext1_ext1_add_same_vec_extra_use0(<16 x i8> %x) {
+; CHECK-LABEL: @ext1_ext1_add_same_vec_extra_use0(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    call void @use_i8(i8 [[E0]])
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[X]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = add i8 [[E0]], [[E1]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 0
+  call void @use_i8(i8 %e0)
+  %e1 = extractelement <16 x i8> %x, i32 0
+  %r = add i8 %e0, %e1
+  ret i8 %r
+}
+
+; Negative test - same vector operand; scalar code is cheaper than general case
+;                 and vector code would be more expensive still.
+
+define i8 @ext1_ext1_add_same_vec_extra_use1(<16 x i8> %x) {
+; CHECK-LABEL: @ext1_ext1_add_same_vec_extra_use1(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[X]], i32 0
+; CHECK-NEXT:    call void @use_i8(i8 [[E1]])
+; CHECK-NEXT:    [[R:%.*]] = add i8 [[E0]], [[E1]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 0
+  %e1 = extractelement <16 x i8> %x, i32 0
+  call void @use_i8(i8 %e1)
+  %r = add i8 %e0, %e1
+  ret i8 %r
+}
+
+; Negative test - same vector operand; scalar code is cheaper than general case
+;                 and vector code would be more expensive still.
+
+define i8 @ext1_ext1_add_same_vec_cse_extra_use(<16 x i8> %x) {
+; CHECK-LABEL: @ext1_ext1_add_same_vec_cse_extra_use(
+; CHECK-NEXT:    [[E:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    call void @use_i8(i8 [[E]])
+; CHECK-NEXT:    [[R:%.*]] = add i8 [[E]], [[E]]
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e = extractelement <16 x i8> %x, i32 0
+  call void @use_i8(i8 %e)
+  %r = add i8 %e, %e
+  ret i8 %r
+}
+
+; Vector code costs the same as scalar, so aggressively form vector op.
+
+define i8 @ext1_ext1_add_uses1(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @ext1_ext1_add_uses1(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0
+; CHECK-NEXT:    call void @use_i8(i8 [[E0]])
+; CHECK-NEXT:    [[TMP1:%.*]] = add <16 x i8> [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <16 x i8> [[TMP1]], i32 0
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 0
+  call void @use_i8(i8 %e0)
+  %e1 = extractelement <16 x i8> %y, i32 0
+  %r = add i8 %e0, %e1
+  ret i8 %r
+}
+
+; Vector code costs the same as scalar, so aggressively form vector op.
+
+define i8 @ext1_ext1_add_uses2(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: @ext1_ext1_add_uses2(
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 0
+; CHECK-NEXT:    call void @use_i8(i8 [[E1]])
+; CHECK-NEXT:    [[TMP1:%.*]] = add <16 x i8> [[X:%.*]], [[Y]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <16 x i8> [[TMP1]], i32 0
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 0
+  %e1 = extractelement <16 x i8> %y, i32 0
+  call void @use_i8(i8 %e1)
+  %r = add i8 %e0, %e1
+  ret i8 %r
+}
+
+define i8 @ext0_ext1_add(<16 x i8> %x, <16 x i8> %y) {
+; SSE-LABEL: @ext0_ext1_add(
+; SSE-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 0
+; SSE-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 1
+; SSE-NEXT:    [[R:%.*]] = add nuw i8 [[E0]], [[E1]]
+; SSE-NEXT:    ret i8 [[R]]
+;
+; AVX-LABEL: @ext0_ext1_add(
+; AVX-NEXT:    [[SHIFT:%.*]] = shufflevector <16 x i8> [[Y:%.*]], <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; AVX-NEXT:    [[TMP1:%.*]] = add nuw <16 x i8> [[X:%.*]], [[SHIFT]]
+; AVX-NEXT:    [[R:%.*]] = extractelement <16 x i8> [[TMP1]], i32 0
+; AVX-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 0
+  %e1 = extractelement <16 x i8> %y, i32 1
+  %r = add nuw i8 %e0, %e1
+  ret i8 %r
+}
+
+define i8 @ext5_ext0_add(<16 x i8> %x, <16 x i8> %y) {
+; SSE-LABEL: @ext5_ext0_add(
+; SSE-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 5
+; SSE-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 0
+; SSE-NEXT:    [[R:%.*]] = sub nsw i8 [[E0]], [[E1]]
+; SSE-NEXT:    ret i8 [[R]]
+;
+; AVX-LABEL: @ext5_ext0_add(
+; AVX-NEXT:    [[SHIFT:%.*]] = shufflevector <16 x i8> [[X:%.*]], <16 x i8> undef, <16 x i32> <i32 5, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; AVX-NEXT:    [[TMP1:%.*]] = sub nsw <16 x i8> [[SHIFT]], [[Y:%.*]]
+; AVX-NEXT:    [[R:%.*]] = extractelement <16 x i8> [[TMP1]], i64 0
+; AVX-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 5
+  %e1 = extractelement <16 x i8> %y, i32 0
+  %r = sub nsw i8 %e0, %e1
+  ret i8 %r
+}
+
+define i8 @ext1_ext6_add(<16 x i8> %x, <16 x i8> %y) {
+; SSE-LABEL: @ext1_ext6_add(
+; SSE-NEXT:    [[E0:%.*]] = extractelement <16 x i8> [[X:%.*]], i32 1
+; SSE-NEXT:    [[E1:%.*]] = extractelement <16 x i8> [[Y:%.*]], i32 6
+; SSE-NEXT:    [[R:%.*]] = and i8 [[E0]], [[E1]]
+; SSE-NEXT:    ret i8 [[R]]
+;
+; AVX-LABEL: @ext1_ext6_add(
+; AVX-NEXT:    [[SHIFT:%.*]] = shufflevector <16 x i8> [[Y:%.*]], <16 x i8> undef, <16 x i32> <i32 undef, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; AVX-NEXT:    [[TMP1:%.*]] = and <16 x i8> [[X:%.*]], [[SHIFT]]
+; AVX-NEXT:    [[R:%.*]] = extractelement <16 x i8> [[TMP1]], i32 1
+; AVX-NEXT:    ret i8 [[R]]
+;
+  %e0 = extractelement <16 x i8> %x, i32 1
+  %e1 = extractelement <16 x i8> %y, i32 6
+  %r = and i8 %e0, %e1
+  ret i8 %r
+}
+
+define float @ext1_ext0_fmul(<4 x float> %x) {
+; CHECK-LABEL: @ext1_ext0_fmul(
+; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul <4 x float> [[SHIFT]], [[X]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x float> [[TMP1]], i64 0
+; CHECK-NEXT:    ret float [[R]]
+;
+  %e0 = extractelement <4 x float> %x, i32 1
+  %e1 = extractelement <4 x float> %x, i32 0
+  %r = fmul float %e0, %e1
+  ret float %r
+}
+
+define float @ext0_ext3_fmul_extra_use1(<4 x float> %x) {
+; CHECK-LABEL: @ext0_ext3_fmul_extra_use1(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <4 x float> [[X:%.*]], i32 0
+; CHECK-NEXT:    call void @use_f32(float [[E0]])
+; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <4 x float> [[X]], <4 x float> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = fmul nnan <4 x float> [[X]], [[SHIFT]]
+; CHECK-NEXT:    [[R:%.*]] = extractelement <4 x float> [[TMP1]], i32 0
+; CHECK-NEXT:    ret float [[R]]
+;
+  %e0 = extractelement <4 x float> %x, i32 0
+  call void @use_f32(float %e0)
+  %e1 = extractelement <4 x float> %x, i32 3
+  %r = fmul nnan float %e0, %e1
+  ret float %r
+}
+
+define float @ext0_ext3_fmul_extra_use2(<4 x float> %x) {
+; CHECK-LABEL: @ext0_ext3_fmul_extra_use2(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <4 x float> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <4 x float> [[X]], i32 3
+; CHECK-NEXT:    call void @use_f32(float [[E1]])
+; CHECK-NEXT:    [[R:%.*]] = fmul ninf nsz float [[E0]], [[E1]]
+; CHECK-NEXT:    ret float [[R]]
+;
+  %e0 = extractelement <4 x float> %x, i32 0
+  %e1 = extractelement <4 x float> %x, i32 3
+  call void @use_f32(float %e1)
+  %r = fmul ninf nsz float %e0, %e1
+  ret float %r
+}
+
+define float @ext0_ext4_fmul_v8f32(<8 x float> %x) {
+; SSE-LABEL: @ext0_ext4_fmul_v8f32(
+; SSE-NEXT:    [[E0:%.*]] = extractelement <8 x float> [[X:%.*]], i32 0
+; SSE-NEXT:    [[E1:%.*]] = extractelement <8 x float> [[X]], i32 4
+; SSE-NEXT:    [[R:%.*]] = fadd float [[E0]], [[E1]]
+; SSE-NEXT:    ret float [[R]]
+;
+; AVX-LABEL: @ext0_ext4_fmul_v8f32(
+; AVX-NEXT:    [[SHIFT:%.*]] = shufflevector <8 x float> [[X:%.*]], <8 x float> undef, <8 x i32> <i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; AVX-NEXT:    [[TMP1:%.*]] = fadd <8 x float> [[X]], [[SHIFT]]
+; AVX-NEXT:    [[R:%.*]] = extractelement <8 x float> [[TMP1]], i32 0
+; AVX-NEXT:    ret float [[R]]
+;
+  %e0 = extractelement <8 x float> %x, i32 0
+  %e1 = extractelement <8 x float> %x, i32 4
+  %r = fadd float %e0, %e1
+  ret float %r
+}
+
+define float @ext7_ext4_fmul_v8f32(<8 x float> %x) {
+; SSE-LABEL: @ext7_ext4_fmul_v8f32(
+; SSE-NEXT:    [[E0:%.*]] = extractelement <8 x float> [[X:%.*]], i32 7
+; SSE-NEXT:    [[E1:%.*]] = extractelement <8 x float> [[X]], i32 4
+; SSE-NEXT:    [[R:%.*]] = fadd float [[E0]], [[E1]]
+; SSE-NEXT:    ret float [[R]]
+;
+; AVX-LABEL: @ext7_ext4_fmul_v8f32(
+; AVX-NEXT:    [[SHIFT:%.*]] = shufflevector <8 x float> [[X:%.*]], <8 x float> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef>
+; AVX-NEXT:    [[TMP1:%.*]] = fadd <8 x float> [[SHIFT]], [[X]]
+; AVX-NEXT:    [[R:%.*]] = extractelement <8 x float> [[TMP1]], i64 4
+; AVX-NEXT:    ret float [[R]]
+;
+  %e0 = extractelement <8 x float> %x, i32 7
+  %e1 = extractelement <8 x float> %x, i32 4
+  %r = fadd float %e0, %e1
+  ret float %r
+}
+
+define float @ext0_ext8_fmul_v16f32(<16 x float> %x) {
+; CHECK-LABEL: @ext0_ext8_fmul_v16f32(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x float> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x float> [[X]], i32 8
+; CHECK-NEXT:    [[R:%.*]] = fadd float [[E0]], [[E1]]
+; CHECK-NEXT:    ret float [[R]]
+;
+  %e0 = extractelement <16 x float> %x, i32 0
+  %e1 = extractelement <16 x float> %x, i32 8
+  %r = fadd float %e0, %e1
+  ret float %r
+}
+
+define float @ext14_ext15_fmul_v16f32(<16 x float> %x) {
+; CHECK-LABEL: @ext14_ext15_fmul_v16f32(
+; CHECK-NEXT:    [[E0:%.*]] = extractelement <16 x float> [[X:%.*]], i32 14
+; CHECK-NEXT:    [[E1:%.*]] = extractelement <16 x float> [[X]], i32 15
+; CHECK-NEXT:    [[R:%.*]] = fadd float [[E0]], [[E1]]
+; CHECK-NEXT:    ret float [[R]]
+;
+  %e0 = extractelement <16 x float> %x, i32 14
+  %e1 = extractelement <16 x float> %x, i32 15
+  %r = fadd float %e0, %e1
+  ret float %r
+}
+
+define <4 x float> @ins_bo_ext_ext(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @ins_bo_ext_ext(
+; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <4 x float> [[SHIFT]], [[A]]
+; CHECK-NEXT:    [[A23:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
+; CHECK-NEXT:    [[V3:%.*]] = insertelement <4 x float> [[B:%.*]], float [[A23]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[V3]]
+;
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %a23 = fadd float %a2, %a3
+  %v3 = insertelement <4 x float> %b, float %a23, i32 3
+  ret <4 x float> %v3
+}
+
+; TODO: This is conservatively left to extract from the lower index value,
+;       but it is likely that extracting from index 3 is the better option.
+
+define <4 x float> @ins_bo_ext_ext_uses(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @ins_bo_ext_ext_uses(
+; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 3, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <4 x float> [[A]], [[SHIFT]]
+; CHECK-NEXT:    [[A23:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    call void @use_f32(float [[A23]])
+; CHECK-NEXT:    [[V3:%.*]] = insertelement <4 x float> [[B:%.*]], float [[A23]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[V3]]
+;
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+  %a23 = fadd float %a2, %a3
+  call void @use_f32(float %a23)
+  %v3 = insertelement <4 x float> %b, float %a23, i32 3
+  ret <4 x float> %v3
+}
+
+define <4 x float> @PR34724(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: @PR34724(
+; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <4 x float> [[A:%.*]], <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 3, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = fadd <4 x float> [[A]], [[SHIFT]]
+; CHECK-NEXT:    [[A23:%.*]] = extractelement <4 x float> [[TMP1]], i32 2
+; CHECK-NEXT:    [[SHIFT1:%.*]] = shufflevector <4 x float> [[B:%.*]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = fadd <4 x float> [[B]], [[SHIFT1]]
+; CHECK-NEXT:    [[B01:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
+; CHECK-NEXT:    [[SHIFT2:%.*]] = shufflevector <4 x float> [[B]], <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>
+; CHECK-NEXT:    [[TMP3:%.*]] = fadd <4 x float> [[SHIFT2]], [[B]]
+; CHECK-NEXT:    [[B23:%.*]] = extractelement <4 x float> [[TMP3]], i64 3
+; CHECK-NEXT:    [[V1:%.*]] = insertelement <4 x float> poison, float [[A23]], i32 1
+; CHECK-NEXT:    [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[B01]], i32 2
+; CHECK-NEXT:    [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[B23]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[V3]]
+;
+  %a0 = extractelement <4 x float> %a, i32 0
+  %a1 = extractelement <4 x float> %a, i32 1
+  %a2 = extractelement <4 x float> %a, i32 2
+  %a3 = extractelement <4 x float> %a, i32 3
+
+  %b0 = extractelement <4 x float> %b, i32 0
+  %b1 = extractelement <4 x float> %b, i32 1
+  %b2 = extractelement <4 x float> %b, i32 2
+  %b3 = extractelement <4 x float> %b, i32 3
+
+  %a23 = fadd float %a2, %a3
+  %b01 = fadd float %b0, %b1
+  %b23 = fadd float %b2, %b3
+
+  %v1 = insertelement <4 x float> poison, float %a23, i32 1
+  %v2 = insertelement <4 x float> %v1, float %b01, i32 2
+  %v3 = insertelement <4 x float> %v2, float %b23, i32 3
+  ret <4 x float> %v3
+}
+
+define i32 @ext_ext_or_reduction_v4i32(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @ext_ext_or_reduction_v4i32(
+; CHECK-NEXT:    [[Z:%.*]] = and <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <4 x i32> [[Z]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = or <4 x i32> [[Z]], [[SHIFT]]
+; CHECK-NEXT:    [[SHIFT1:%.*]] = shufflevector <4 x i32> [[Z]], <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = or <4 x i32> [[TMP1]], [[SHIFT1]]
+; CHECK-NEXT:    [[SHIFT2:%.*]] = shufflevector <4 x i32> [[Z]], <4 x i32> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP3:%.*]] = or <4 x i32> [[SHIFT2]], [[TMP2]]
+; CHECK-NEXT:    [[Z0123:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0
+; CHECK-NEXT:    ret i32 [[Z0123]]
+;
+  %z = and <4 x i32> %x, %y
+  %z0 = extractelement <4 x i32> %z, i32 0
+  %z1 = extractelement <4 x i32> %z, i32 1
+  %z01 = or i32 %z0, %z1
+  %z2 = extractelement <4 x i32> %z, i32 2
+  %z012 = or i32 %z01, %z2
+  %z3 = extractelement <4 x i32> %z, i32 3
+  %z0123 = or i32 %z3, %z012
+  ret i32 %z0123
+}
+
+define i32 @ext_ext_partial_add_reduction_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: @ext_ext_partial_add_reduction_v4i32(
+; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[SHIFT]], [[X]]
+; CHECK-NEXT:    [[SHIFT1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = add <4 x i32> [[SHIFT1]], [[TMP1]]
+; CHECK-NEXT:    [[X210:%.*]] = extractelement <4 x i32> [[TMP2]], i64 0
+; CHECK-NEXT:    ret i32 [[X210]]
+;
+  %x0 = extractelement <4 x i32> %x, i32 0
+  %x1 = extractelement <4 x i32> %x, i32 1
+  %x10 = add i32 %x1, %x0
+  %x2 = extractelement <4 x i32> %x, i32 2
+  %x210 = add i32 %x2, %x10
+  ret i32 %x210
+}
+
+define i32 @ext_ext_partial_add_reduction_and_extra_add_v4i32(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @ext_ext_partial_add_reduction_and_extra_add_v4i32(
+; CHECK-NEXT:    [[SHIFT:%.*]] = shufflevector <4 x i32> [[Y:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP1:%.*]] = add <4 x i32> [[SHIFT]], [[Y]]
+; CHECK-NEXT:    [[SHIFT1:%.*]] = shufflevector <4 x i32> [[Y]], <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP2:%.*]] = add <4 x i32> [[SHIFT1]], [[TMP1]]
+; CHECK-NEXT:    [[SHIFT2:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    [[TMP3:%.*]] = add <4 x i32> [[SHIFT2]], [[TMP2]]
+; CHECK-NEXT:    [[X2Y210:%.*]] = extractelement <4 x i32> [[TMP3]], i64 0
+; CHECK-NEXT:    ret i32 [[X2Y210]]
+;
+  %y0 = extractelement <4 x i32> %y, i32 0
+  %y1 = extractelement <4 x i32> %y, i32 1
+  %y10 = add i32 %y1, %y0
+  %y2 = extractelement <4 x i32> %y, i32 2
+  %y210 = add i32 %y2, %y10
+  %x2 = extractelement <4 x i32> %x, i32 2
+  %x2y210 = add i32 %x2, %y210
+  ret i32 %x2y210
+}
+
+define i32 @constant_fold_crash(<4 x i32> %x) {
+; CHECK-LABEL: @constant_fold_crash(
+; CHECK-NEXT:    [[A:%.*]] = extractelement <4 x i32> <i32 16, i32 17, i32 18, i32 19>, i32 1
+; CHECK-NEXT:    [[B:%.*]] = extractelement <4 x i32> [[X:%.*]], i32 0
+; CHECK-NEXT:    [[C:%.*]] = add i32 [[A]], [[B]]
+; CHECK-NEXT:    ret i32 [[C]]
+;
+  %a = extractelement <4 x i32> <i32 16, i32 17, i32 18, i32 19>, i32 1
+  %b = extractelement <4 x i32> %x, i32 0
+  %c = add i32 %a, %b
+  ret i32 %c
+}
+
+define float @constant_fold_crash_commute(<4 x float> %x) {
+; CHECK-LABEL: @constant_fold_crash_commute(
+; CHECK-NEXT:    [[A:%.*]] = extractelement <4 x float> <float 1.600000e+01, float 1.700000e+01, float 1.800000e+01, float 1.900000e+01>, i32 3
+; CHECK-NEXT:    [[B:%.*]] = extractelement <4 x float> [[X:%.*]], i32 1
+; CHECK-NEXT:    [[C:%.*]] = fadd float [[B]], [[A]]
+; CHECK-NEXT:    ret float [[C]]
+;
+  %a = extractelement <4 x float> <float 16.0, float 17.0, float 18.0, float 19.0>, i32 3
+  %b = extractelement <4 x float> %x, i32 1
+  %c = fadd float %b, %a
+  ret float %c
+}
diff --git a/llvm/test/Transforms/VectorCombine/X86/insert-binop-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/X86/insert-binop-inseltpoison.ll
new file mode 100644
index 0000000000000..8a6b1e98c9687
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/X86/insert-binop-inseltpoison.ll
@@ -0,0 +1,234 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=SSE2 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=AVX2 | FileCheck %s --check-prefixes=CHECK,AVX
+
+declare void @use(<4 x i32>)
+declare void @usef(<4 x float>)
+
+; Eliminating an insert is profitable.
+
+define <16 x i8> @ins0_ins0_add(i8 %x, i8 %y) {
+; CHECK-LABEL: @ins0_ins0_add(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = add i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <16 x i8> poison, i8 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <16 x i8> [[R]]
+;
+  %i0 = insertelement <16 x i8> poison, i8 %x, i32 0
+  %i1 = insertelement <16 x i8> poison, i8 %y, i32 0
+  %r = add <16 x i8> %i0, %i1
+  ret <16 x i8> %r
+}
+
+; Eliminating an insert is still profitable. Flags propagate. Mismatch types on index is ok.
+
+define <8 x i16> @ins0_ins0_sub_flags(i16 %x, i16 %y) {
+; CHECK-LABEL: @ins0_ins0_sub_flags(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = sub nuw nsw i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <8 x i16> poison, i16 [[R_SCALAR]], i64 5
+; CHECK-NEXT:    ret <8 x i16> [[R]]
+;
+  %i0 = insertelement <8 x i16> poison, i16 %x, i8 5
+  %i1 = insertelement <8 x i16> poison, i16 %y, i32 5
+  %r = sub nsw nuw <8 x i16> %i0, %i1
+  ret <8 x i16> %r
+}
+
+; The new vector constant is calculated by constant folding.
+; This is conservatively created as zero rather than undef for 'undef ^ undef'.
+
+define <2 x i64> @ins1_ins1_xor(i64 %x, i64 %y) {
+; CHECK-LABEL: @ins1_ins1_xor(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = xor i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i64> poison, i64 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[R]]
+;
+  %i0 = insertelement <2 x i64> poison, i64 %x, i64 1
+  %i1 = insertelement <2 x i64> poison, i64 %y, i32 1
+  %r = xor <2 x i64> %i0, %i1
+  ret <2 x i64> %r
+}
+
+define <2 x i64> @ins1_ins1_iterate(i64 %w, i64 %x, i64 %y, i64 %z) {
+; CHECK-LABEL: @ins1_ins1_iterate(
+; CHECK-NEXT:    [[S0_SCALAR:%.*]] = sub i64 [[W:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[S1_SCALAR:%.*]] = or i64 [[S0_SCALAR]], [[Y:%.*]]
+; CHECK-NEXT:    [[S2_SCALAR:%.*]] = shl i64 [[Z:%.*]], [[S1_SCALAR]]
+; CHECK-NEXT:    [[S2:%.*]] = insertelement <2 x i64> poison, i64 [[S2_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[S2]]
+;
+  %i0 = insertelement <2 x i64> poison, i64 %w, i64 1
+  %i1 = insertelement <2 x i64> poison, i64 %x, i32 1
+  %s0 = sub <2 x i64> %i0, %i1
+  %i2 = insertelement <2 x i64> poison, i64 %y, i32 1
+  %s1 = or <2 x i64> %s0, %i2
+  %i3 = insertelement <2 x i64> poison, i64 %z, i32 1
+  %s2 = shl <2 x i64> %i3, %s1
+  ret <2 x i64> %s2
+}
+
+; The inserts are free, but it's still better to scalarize.
+
+define <2 x double> @ins0_ins0_fadd(double %x, double %y) {
+; CHECK-LABEL: @ins0_ins0_fadd(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = fadd reassoc nsz double [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x double> poison, double [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[R]]
+;
+  %i0 = insertelement <2 x double> poison, double %x, i32 0
+  %i1 = insertelement <2 x double> poison, double %y, i32 0
+  %r = fadd reassoc nsz <2 x double> %i0, %i1
+  ret <2 x double> %r
+}
+
+; Negative test - mismatched indexes (but could fold this).
+
+define <16 x i8> @ins1_ins0_add(i8 %x, i8 %y) {
+; CHECK-LABEL: @ins1_ins0_add(
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <16 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <16 x i8> poison, i8 [[Y:%.*]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = add <16 x i8> [[I0]], [[I1]]
+; CHECK-NEXT:    ret <16 x i8> [[R]]
+;
+  %i0 = insertelement <16 x i8> poison, i8 %x, i32 1
+  %i1 = insertelement <16 x i8> poison, i8 %y, i32 0
+  %r = add <16 x i8> %i0, %i1
+  ret <16 x i8> %r
+}
+
+; Base vector does not have to be undef.
+
+define <4 x i32> @ins0_ins0_mul(i32 %x, i32 %y) {
+; CHECK-LABEL: @ins0_ins0_mul(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = mul i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i32> poison, i32 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %i0 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
+  %i1 = insertelement <4 x i32> poison, i32 %y, i32 0
+  %r = mul <4 x i32> %i0, %i1
+  ret <4 x i32> %r
+}
+
+; It is safe to scalarize any binop (no extra UB/poison danger).
+
+define <2 x i64> @ins1_ins1_sdiv(i64 %x, i64 %y) {
+; CHECK-LABEL: @ins1_ins1_sdiv(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = sdiv i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i64> <i64 -6, i64 0>, i64 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[R]]
+;
+  %i0 = insertelement <2 x i64> <i64 42, i64 -42>, i64 %x, i64 1
+  %i1 = insertelement <2 x i64> <i64 -7, i64 128>, i64 %y, i32 1
+  %r = sdiv <2 x i64> %i0, %i1
+  ret <2 x i64> %r
+}
+
+; Constant folding deals with undef per element - the entire value does not become undef.
+
+define <2 x i64> @ins1_ins1_udiv(i64 %x, i64 %y) {
+; CHECK-LABEL: @ins1_ins1_udiv(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = udiv i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i64> <i64 6, i64 poison>, i64 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[R]]
+;
+  %i0 = insertelement <2 x i64> <i64 42, i64 undef>, i64 %x, i32 1
+  %i1 = insertelement <2 x i64> <i64 7, i64 undef>, i64 %y, i32 1
+  %r = udiv <2 x i64> %i0, %i1
+  ret <2 x i64> %r
+}
+
+; This could be simplified -- creates immediate UB without the transform because
+; divisor has an undef element -- but that is hidden after the transform.
+
+define <2 x i64> @ins1_ins1_urem(i64 %x, i64 %y) {
+; CHECK-LABEL: @ins1_ins1_urem(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = urem i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i64> <i64 poison, i64 0>, i64 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[R]]
+;
+  %i0 = insertelement <2 x i64> <i64 42, i64 undef>, i64 %x, i64 1
+  %i1 = insertelement <2 x i64> <i64 undef, i64 128>, i64 %y, i32 1
+  %r = urem <2 x i64> %i0, %i1
+  ret <2 x i64> %r
+}
+
+; Extra use is accounted for in cost calculation.
+
+define <4 x i32> @ins0_ins0_xor(i32 %x, i32 %y) {
+; CHECK-LABEL: @ins0_ins0_xor(
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK-NEXT:    call void @use(<4 x i32> [[I0]])
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = xor i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i32> poison, i32 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %i0 = insertelement <4 x i32> poison, i32 %x, i32 0
+  call void @use(<4 x i32> %i0)
+  %i1 = insertelement <4 x i32> poison, i32 %y, i32 0
+  %r = xor <4 x i32> %i0, %i1
+  ret <4 x i32> %r
+}
+
+; Extra use is accounted for in cost calculation.
+
+define <4 x float> @ins1_ins1_fmul(float %x, float %y) {
+; CHECK-LABEL: @ins1_ins1_fmul(
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x float> poison, float [[Y:%.*]], i32 1
+; CHECK-NEXT:    call void @usef(<4 x float> [[I1]])
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = fmul float [[X:%.*]], [[Y]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> poison, float [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %i0 = insertelement <4 x float> poison, float %x, i32 1
+  %i1 = insertelement <4 x float> poison, float %y, i32 1
+  call void @usef(<4 x float> %i1)
+  %r = fmul <4 x float> %i0, %i1
+  ret <4 x float> %r
+}
+
+; If the scalar binop is not cheaper than the vector binop, extra uses can prevent the transform.
+
+define <4 x float> @ins2_ins2_fsub(float %x, float %y) {
+; CHECK-LABEL: @ins2_ins2_fsub(
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 2
+; CHECK-NEXT:    call void @usef(<4 x float> [[I0]])
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x float> poison, float [[Y:%.*]], i32 2
+; CHECK-NEXT:    call void @usef(<4 x float> [[I1]])
+; CHECK-NEXT:    [[R:%.*]] = fsub <4 x float> [[I0]], [[I1]]
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %i0 = insertelement <4 x float> poison, float %x, i32 2
+  call void @usef(<4 x float> %i0)
+  %i1 = insertelement <4 x float> poison, float %y, i32 2
+  call void @usef(<4 x float> %i1)
+  %r = fsub <4 x float> %i0, %i1
+  ret <4 x float> %r
+}
+
+; It may be worth scalarizing an expensive binop even if both inserts have extra uses.
+
+define <4 x float> @ins3_ins3_fdiv(float %x, float %y) {
+; SSE-LABEL: @ins3_ins3_fdiv(
+; SSE-NEXT:    [[I0:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 3
+; SSE-NEXT:    call void @usef(<4 x float> [[I0]])
+; SSE-NEXT:    [[I1:%.*]] = insertelement <4 x float> poison, float [[Y:%.*]], i32 3
+; SSE-NEXT:    call void @usef(<4 x float> [[I1]])
+; SSE-NEXT:    [[R_SCALAR:%.*]] = fdiv float [[X]], [[Y]]
+; SSE-NEXT:    [[R:%.*]] = insertelement <4 x float> poison, float [[R_SCALAR]], i64 3
+; SSE-NEXT:    ret <4 x float> [[R]]
+;
+; AVX-LABEL: @ins3_ins3_fdiv(
+; AVX-NEXT:    [[I0:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 3
+; AVX-NEXT:    call void @usef(<4 x float> [[I0]])
+; AVX-NEXT:    [[I1:%.*]] = insertelement <4 x float> poison, float [[Y:%.*]], i32 3
+; AVX-NEXT:    call void @usef(<4 x float> [[I1]])
+; AVX-NEXT:    [[R:%.*]] = fdiv <4 x float> [[I0]], [[I1]]
+; AVX-NEXT:    ret <4 x float> [[R]]
+;
+  %i0 = insertelement <4 x float> poison, float %x, i32 3
+  call void @usef(<4 x float> %i0)
+  %i1 = insertelement <4 x float> poison, float %y, i32 3
+  call void @usef(<4 x float> %i1)
+  %r = fdiv <4 x float> %i0, %i1
+  ret <4 x float> %r
+}
diff --git a/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant-inseltpoison.ll
new file mode 100644
index 0000000000000..9f41db0c9e324
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/X86/insert-binop-with-constant-inseltpoison.ll
@@ -0,0 +1,728 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=SSE2 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=AVX2 | FileCheck %s --check-prefixes=CHECK,AVX
+
+define <2 x i64> @add_constant(i64 %x) {
+; CHECK-LABEL: @add_constant(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = add i64 [[X:%.*]], 42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = add <2 x i64> %ins, <i64 42, i64 undef>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @add_constant_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @add_constant_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = add i64 [[X:%.*]], 42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = add <2 x i64> %ins, <i64 42, i64 -42>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @add_constant_load(i64* %p) {
+; CHECK-LABEL: @add_constant_load(
+; CHECK-NEXT:    [[LD:%.*]] = load i64, i64* [[P:%.*]], align 4
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i64> poison, i64 [[LD]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = add <2 x i64> [[INS]], <i64 42, i64 -42>
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ld = load i64, i64* %p
+  %ins = insertelement <2 x i64> poison, i64 %ld, i32 0
+  %bo = add <2 x i64> %ins, <i64 42, i64 -42>
+  ret <2 x i64> %bo
+}
+
+; IR flags are not required, but they should propagate.
+
+define <4 x i32> @sub_constant_op0(i32 %x) {
+; CHECK-LABEL: @sub_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = sub nuw nsw i32 -42, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <4 x i32> poison, i32 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <4 x i32> [[BO]]
+;
+  %ins = insertelement <4 x i32> poison, i32 %x, i32 1
+  %bo = sub nsw nuw <4 x i32> <i32 undef, i32 -42, i32 undef, i32 undef>, %ins
+  ret <4 x i32> %bo
+}
+
+define <4 x i32> @sub_constant_op0_not_undef_lane(i32 %x) {
+; CHECK-LABEL: @sub_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = sub nuw i32 42, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <4 x i32> poison, i32 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <4 x i32> [[BO]]
+;
+  %ins = insertelement <4 x i32> poison, i32 %x, i32 1
+  %bo = sub nuw <4 x i32> <i32 1, i32 42, i32 42, i32 -42>, %ins
+  ret <4 x i32> %bo
+}
+
+define <8 x i16> @sub_constant_op1(i16 %x) {
+; CHECK-LABEL: @sub_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = sub nuw i16 [[X:%.*]], 42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <8 x i16> poison, i16 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <8 x i16> [[BO]]
+;
+  %ins = insertelement <8 x i16> poison, i16 %x, i32 0
+  %bo = sub nuw <8 x i16> %ins, <i16 42, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>
+  ret <8 x i16> %bo
+}
+
+define <8 x i16> @sub_constant_op1_not_undef_lane(i16 %x) {
+; CHECK-LABEL: @sub_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = sub nuw i16 [[X:%.*]], 42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <8 x i16> poison, i16 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <8 x i16> [[BO]]
+;
+  %ins = insertelement <8 x i16> poison, i16 %x, i32 0
+  %bo = sub nuw <8 x i16> %ins, <i16 42, i16 -42, i16 0, i16 1, i16 -2, i16 3, i16 -4, i16 5>
+  ret <8 x i16> %bo
+}
+
+define <16 x i8> @mul_constant(i8 %x) {
+; CHECK-LABEL: @mul_constant(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = mul i8 [[X:%.*]], -42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <16 x i8> poison, i8 [[BO_SCALAR]], i64 2
+; CHECK-NEXT:    ret <16 x i8> [[BO]]
+;
+  %ins = insertelement <16 x i8> poison, i8 %x, i32 2
+  %bo = mul <16 x i8> %ins, <i8 undef, i8 undef, i8 -42, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>
+  ret <16 x i8> %bo
+}
+
+define <3 x i64> @mul_constant_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @mul_constant_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = mul i64 [[X:%.*]], -42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <3 x i64> poison, i64 [[BO_SCALAR]], i64 2
+; CHECK-NEXT:    ret <3 x i64> [[BO]]
+;
+  %ins = insertelement <3 x i64> poison, i64 %x, i32 2
+  %bo = mul <3 x i64> %ins, <i64 42, i64 undef, i64 -42>
+  ret <3 x i64> %bo
+}
+
+define <16 x i8> @mul_constant_multiuse(i8 %a0, <16 x i8> %a1) {
+; SSE-LABEL: @mul_constant_multiuse(
+; SSE-NEXT:    [[INS:%.*]] = insertelement <16 x i8> <i8 undef, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, i8 [[A0:%.*]], i32 0
+; SSE-NEXT:    [[MUL:%.*]] = mul <16 x i8> [[INS]], <i8 3, i8 7, i8 9, i8 11, i8 13, i8 15, i8 17, i8 19, i8 21, i8 23, i8 25, i8 27, i8 29, i8 31, i8 33, i8 35>
+; SSE-NEXT:    [[AND:%.*]] = and <16 x i8> [[INS]], [[A1:%.*]]
+; SSE-NEXT:    [[XOR:%.*]] = xor <16 x i8> [[AND]], [[MUL]]
+; SSE-NEXT:    ret <16 x i8> [[XOR]]
+;
+; AVX-LABEL: @mul_constant_multiuse(
+; AVX-NEXT:    [[INS:%.*]] = insertelement <16 x i8> <i8 undef, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, i8 [[A0:%.*]], i32 0
+; AVX-NEXT:    [[MUL_SCALAR:%.*]] = mul i8 [[A0]], 3
+; AVX-NEXT:    [[MUL:%.*]] = insertelement <16 x i8> <i8 undef, i8 7, i8 18, i8 33, i8 52, i8 75, i8 102, i8 -123, i8 -88, i8 -49, i8 -6, i8 41, i8 92, i8 -109, i8 -50, i8 13>, i8 [[MUL_SCALAR]], i64 0
+; AVX-NEXT:    [[AND:%.*]] = and <16 x i8> [[INS]], [[A1:%.*]]
+; AVX-NEXT:    [[XOR:%.*]] = xor <16 x i8> [[AND]], [[MUL]]
+; AVX-NEXT:    ret <16 x i8> [[XOR]]
+;
+  %ins = insertelement <16 x i8> <i8 undef, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, i8 %a0, i32 0
+  %mul = mul <16 x i8> %ins, <i8 3, i8 7, i8 9, i8 11, i8 13, i8 15, i8 17, i8 19, i8 21, i8 23, i8 25, i8 27, i8 29, i8 31, i8 33, i8 35>
+  %and = and <16 x i8> %ins, %a1
+  %xor = xor <16 x i8> %and, %mul
+  ret <16 x i8> %xor
+}
+
+define <2 x i64> @shl_constant_op0(i64 %x) {
+; CHECK-LABEL: @shl_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = shl i64 2, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = shl <2 x i64> <i64 undef, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @shl_constant_op0_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @shl_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = shl i64 2, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = shl <2 x i64> <i64 5, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @shl_constant_op0_load(i64* %p) {
+; CHECK-LABEL: @shl_constant_op0_load(
+; CHECK-NEXT:    [[LD:%.*]] = load i64, i64* [[P:%.*]], align 4
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i64> poison, i64 [[LD]], i32 1
+; CHECK-NEXT:    [[BO:%.*]] = shl <2 x i64> <i64 undef, i64 2>, [[INS]]
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ld = load i64, i64* %p
+  %ins = insertelement <2 x i64> poison, i64 %ld, i32 1
+  %bo = shl <2 x i64> <i64 undef, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <4 x i32> @shl_constant_op0_multiuse(i32 %a0, <4 x i32> %a1) {
+; SSE-LABEL: @shl_constant_op0_multiuse(
+; SSE-NEXT:    [[INS:%.*]] = insertelement <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, i32 [[A0:%.*]], i32 0
+; SSE-NEXT:    [[MUL_SCALAR:%.*]] = shl i32 [[A0]], 3
+; SSE-NEXT:    [[MUL:%.*]] = insertelement <4 x i32> <i32 0, i32 16, i32 64, i32 192>, i32 [[MUL_SCALAR]], i64 0
+; SSE-NEXT:    [[AND:%.*]] = and <4 x i32> [[INS]], [[A1:%.*]]
+; SSE-NEXT:    [[XOR:%.*]] = xor <4 x i32> [[AND]], [[MUL]]
+; SSE-NEXT:    ret <4 x i32> [[XOR]]
+;
+; AVX-LABEL: @shl_constant_op0_multiuse(
+; AVX-NEXT:    [[INS:%.*]] = insertelement <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, i32 [[A0:%.*]], i32 0
+; AVX-NEXT:    [[MUL:%.*]] = shl <4 x i32> [[INS]], <i32 3, i32 4, i32 5, i32 6>
+; AVX-NEXT:    [[AND:%.*]] = and <4 x i32> [[INS]], [[A1:%.*]]
+; AVX-NEXT:    [[XOR:%.*]] = xor <4 x i32> [[AND]], [[MUL]]
+; AVX-NEXT:    ret <4 x i32> [[XOR]]
+;
+  %ins = insertelement <4 x i32> <i32 undef, i32 1, i32 2, i32 3>, i32 %a0, i32 0
+  %mul = shl <4 x i32> %ins, <i32 3, i32 4, i32 5, i32 6>
+  %and = and <4 x i32> %ins, %a1
+  %xor = xor <4 x i32> %and, %mul
+  ret <4 x i32> %xor
+}
+
+define <2 x i64> @shl_constant_op1(i64 %x) {
+; CHECK-LABEL: @shl_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = shl nuw i64 [[X:%.*]], 5
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = shl nuw <2 x i64> %ins, <i64 5, i64 undef>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @shl_constant_op1_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @shl_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = shl nuw i64 [[X:%.*]], 5
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = shl nuw <2 x i64> %ins, <i64 5, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @shl_constant_op1_load(i64* %p) {
+; CHECK-LABEL: @shl_constant_op1_load(
+; CHECK-NEXT:    [[LD:%.*]] = load i64, i64* [[P:%.*]], align 4
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i64> poison, i64 [[LD]], i32 0
+; CHECK-NEXT:    [[BO:%.*]] = shl nuw <2 x i64> [[INS]], <i64 5, i64 2>
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ld = load i64, i64* %p
+  %ins = insertelement <2 x i64> poison, i64 %ld, i32 0
+  %bo = shl nuw <2 x i64> %ins, <i64 5, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @ashr_constant_op0(i64 %x) {
+; CHECK-LABEL: @ashr_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = ashr exact i64 2, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = ashr exact <2 x i64> <i64 undef, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @ashr_constant_op0_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @ashr_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = ashr exact i64 2, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = ashr exact <2 x i64> <i64 5, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @ashr_constant_op1(i64 %x) {
+; CHECK-LABEL: @ashr_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = ashr i64 [[X:%.*]], 5
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = ashr <2 x i64> %ins, <i64 5, i64 undef>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @ashr_constant_op1_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @ashr_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = ashr i64 [[X:%.*]], 5
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = ashr <2 x i64> %ins, <i64 5, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @lshr_constant_op0(i64 %x) {
+; CHECK-LABEL: @lshr_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = lshr i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = lshr <2 x i64> <i64 5, i64 undef>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @lshr_constant_op0_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @lshr_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = lshr i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = lshr <2 x i64> <i64 5, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @lshr_constant_op1(i64 %x) {
+; CHECK-LABEL: @lshr_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = lshr exact i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = lshr exact <2 x i64> %ins, <i64 undef, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @lshr_constant_op1_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @lshr_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = lshr exact i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = lshr exact <2 x i64> %ins, <i64 5, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @urem_constant_op0(i64 %x) {
+; CHECK-LABEL: @urem_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = urem i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = urem <2 x i64> <i64 5, i64 undef>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @urem_constant_op0_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @urem_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = urem i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = urem <2 x i64> <i64 5, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @urem_constant_op1(i64 %x) {
+; CHECK-LABEL: @urem_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = urem i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = urem <2 x i64> %ins, <i64 undef, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @urem_constant_op1_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @urem_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = urem i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = urem <2 x i64> %ins, <i64 5, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @srem_constant_op0(i64 %x) {
+; CHECK-LABEL: @srem_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = srem i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = srem <2 x i64> <i64 5, i64 undef>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @srem_constant_op0_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @srem_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = srem i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = srem <2 x i64> <i64 5, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @srem_constant_op1(i64 %x) {
+; CHECK-LABEL: @srem_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = srem i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = srem <2 x i64> %ins, <i64 undef, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @srem_constant_op1_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @srem_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = srem i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = srem <2 x i64> %ins, <i64 5, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @udiv_constant_op0(i64 %x) {
+; CHECK-LABEL: @udiv_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = udiv exact i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = udiv exact <2 x i64> <i64 5, i64 undef>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @udiv_constant_op0_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @udiv_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = udiv exact i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = udiv exact <2 x i64> <i64 5, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @udiv_constant_op1(i64 %x) {
+; CHECK-LABEL: @udiv_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = udiv i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = udiv <2 x i64> %ins, <i64 undef, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @udiv_constant_op1_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @udiv_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = udiv i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = udiv <2 x i64> %ins, <i64 5, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @sdiv_constant_op0(i64 %x) {
+; CHECK-LABEL: @sdiv_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = sdiv i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = sdiv <2 x i64> <i64 5, i64 undef>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @sdiv_constant_op0_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @sdiv_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = sdiv i64 5, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = sdiv <2 x i64> <i64 5, i64 2>, %ins
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @sdiv_constant_op1(i64 %x) {
+; CHECK-LABEL: @sdiv_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = sdiv exact i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = sdiv exact <2 x i64> %ins, <i64 undef, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @sdiv_constant_op1_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @sdiv_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = sdiv exact i64 [[X:%.*]], 2
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = sdiv exact <2 x i64> %ins, <i64 5, i64 2>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @and_constant(i64 %x) {
+; CHECK-LABEL: @and_constant(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = and i64 [[X:%.*]], 42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = and <2 x i64> %ins, <i64 42, i64 undef>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @and_constant_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @and_constant_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = and i64 [[X:%.*]], 42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = and <2 x i64> %ins, <i64 42, i64 -42>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @or_constant(i64 %x) {
+; CHECK-LABEL: @or_constant(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = or i64 [[X:%.*]], -42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = or <2 x i64> %ins, <i64 undef, i64 -42>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @or_constant_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @or_constant_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = or i64 [[X:%.*]], -42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 1
+  %bo = or <2 x i64> %ins, <i64 42, i64 -42>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @xor_constant(i64 %x) {
+; CHECK-LABEL: @xor_constant(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = xor i64 [[X:%.*]], 42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = xor <2 x i64> %ins, <i64 42, i64 undef>
+  ret <2 x i64> %bo
+}
+
+define <2 x i64> @xor_constant_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @xor_constant_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = xor i64 [[X:%.*]], 42
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x i64> poison, i64 [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i64> [[BO]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %bo = xor <2 x i64> %ins, <i64 42, i64 -42>
+  ret <2 x i64> %bo
+}
+
+define <2 x double> @fadd_constant(double %x) {
+; CHECK-LABEL: @fadd_constant(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fadd double [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %bo = fadd <2 x double> %ins, <double 42.0, double undef>
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fadd_constant_not_undef_lane(double %x) {
+; CHECK-LABEL: @fadd_constant_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fadd double [[X:%.*]], -4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 1
+  %bo = fadd <2 x double> %ins, <double 42.0, double -42.0>
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fsub_constant_op0(double %x) {
+; CHECK-LABEL: @fsub_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fsub fast double 4.200000e+01, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %bo = fsub fast <2 x double> <double 42.0, double undef>, %ins
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fsub_constant_op0_not_undef_lane(double %x) {
+; CHECK-LABEL: @fsub_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fsub nsz double -4.200000e+01, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 1
+  %bo = fsub nsz <2 x double> <double 42.0, double -42.0>, %ins
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fsub_constant_op1(double %x) {
+; CHECK-LABEL: @fsub_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fsub double [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 1
+  %bo = fsub <2 x double> %ins, <double undef, double 42.0>
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fsub_constant_op1_not_undef_lane(double %x) {
+; CHECK-LABEL: @fsub_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fsub double [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %bo = fsub <2 x double> %ins, <double 42.0, double -42.0>
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fmul_constant(double %x) {
+; CHECK-LABEL: @fmul_constant(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fmul reassoc double [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %bo = fmul reassoc <2 x double> %ins, <double 42.0, double undef>
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fmul_constant_not_undef_lane(double %x) {
+; CHECK-LABEL: @fmul_constant_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fmul double [[X:%.*]], -4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 1
+  %bo = fmul <2 x double> %ins, <double 42.0, double -42.0>
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fdiv_constant_op0(double %x) {
+; CHECK-LABEL: @fdiv_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fdiv nnan double 4.200000e+01, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 1
+  %bo = fdiv nnan <2 x double> <double undef, double 42.0>, %ins
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fdiv_constant_op0_not_undef_lane(double %x) {
+; CHECK-LABEL: @fdiv_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fdiv ninf double 4.200000e+01, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %bo = fdiv ninf <2 x double> <double 42.0, double -42.0>, %ins
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fdiv_constant_op1(double %x) {
+; CHECK-LABEL: @fdiv_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fdiv double [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %bo = fdiv <2 x double> %ins, <double 42.0, double undef>
+  ret <2 x double> %bo
+}
+
+define <2 x double> @fdiv_constant_op1_not_undef_lane(double %x) {
+; CHECK-LABEL: @fdiv_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = fdiv double [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %bo = fdiv <2 x double> %ins, <double 42.0, double -42.0>
+  ret <2 x double> %bo
+}
+
+define <2 x double> @frem_constant_op0(double %x) {
+; CHECK-LABEL: @frem_constant_op0(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = frem fast double 4.200000e+01, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %bo = frem fast <2 x double> <double 42.0, double undef>, %ins
+  ret <2 x double> %bo
+}
+
+define <2 x double> @frem_constant_op0_not_undef_lane(double %x) {
+; CHECK-LABEL: @frem_constant_op0_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = frem double -4.200000e+01, [[X:%.*]]
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 1
+  %bo = frem <2 x double> <double 42.0, double -42.0>, %ins
+  ret <2 x double> %bo
+}
+
+define <2 x double> @frem_constant_op1(double %x) {
+; CHECK-LABEL: @frem_constant_op1(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = frem ninf double [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 1
+  %bo = frem ninf <2 x double> %ins, <double undef, double 42.0>
+  ret <2 x double> %bo
+}
+
+define <2 x double> @frem_constant_op1_not_undef_lane(double %x) {
+; CHECK-LABEL: @frem_constant_op1_not_undef_lane(
+; CHECK-NEXT:    [[BO_SCALAR:%.*]] = frem nnan double [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[BO:%.*]] = insertelement <2 x double> poison, double [[BO_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x double> [[BO]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %bo = frem nnan <2 x double> %ins, <double 42.0, double -42.0>
+  ret <2 x double> %bo
+}
diff --git a/llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
new file mode 100644
index 0000000000000..dd0ef45c7f02e
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/X86/load-inseltpoison.ll
@@ -0,0 +1,649 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=sse2 | FileCheck %s --check-prefixes=CHECK,SSE2
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s --check-prefixes=CHECK,AVX2
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+define float @matching_fp_scalar(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @matching_fp_scalar(
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[P:%.*]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %r = load float, float* %p, align 16
+  ret float %r
+}
+
+define float @matching_fp_scalar_volatile(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @matching_fp_scalar_volatile(
+; CHECK-NEXT:    [[R:%.*]] = load volatile float, float* [[P:%.*]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %r = load volatile float, float* %p, align 16
+  ret float %r
+}
+
+define double @larger_fp_scalar(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @larger_fp_scalar(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast float* [[P:%.*]] to double*
+; CHECK-NEXT:    [[R:%.*]] = load double, double* [[BC]], align 16
+; CHECK-NEXT:    ret double [[R]]
+;
+  %bc = bitcast float* %p to double*
+  %r = load double, double* %bc, align 16
+  ret double %r
+}
+
+define float @smaller_fp_scalar(double* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @smaller_fp_scalar(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast double* [[P:%.*]] to float*
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[BC]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %bc = bitcast double* %p to float*
+  %r = load float, float* %bc, align 16
+  ret float %r
+}
+
+define float @matching_fp_vector(<4 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @matching_fp_vector(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <4 x float>* [[P:%.*]] to float*
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[BC]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %bc = bitcast <4 x float>* %p to float*
+  %r = load float, float* %bc, align 16
+  ret float %r
+}
+
+define float @matching_fp_vector_gep00(<4 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @matching_fp_vector_gep00(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[P:%.*]], i64 0, i64 0
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[GEP]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %gep = getelementptr inbounds <4 x float>, <4 x float>* %p, i64 0, i64 0
+  %r = load float, float* %gep, align 16
+  ret float %r
+}
+
+define float @matching_fp_vector_gep01(<4 x float>* align 16 dereferenceable(20) %p) {
+; CHECK-LABEL: @matching_fp_vector_gep01(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[P:%.*]], i64 0, i64 1
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[GEP]], align 4
+; CHECK-NEXT:    ret float [[R]]
+;
+  %gep = getelementptr inbounds <4 x float>, <4 x float>* %p, i64 0, i64 1
+  %r = load float, float* %gep, align 4
+  ret float %r
+}
+
+define float @matching_fp_vector_gep01_deref(<4 x float>* align 16 dereferenceable(19) %p) {
+; CHECK-LABEL: @matching_fp_vector_gep01_deref(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[P:%.*]], i64 0, i64 1
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[GEP]], align 4
+; CHECK-NEXT:    ret float [[R]]
+;
+  %gep = getelementptr inbounds <4 x float>, <4 x float>* %p, i64 0, i64 1
+  %r = load float, float* %gep, align 4
+  ret float %r
+}
+
+define float @matching_fp_vector_gep10(<4 x float>* align 16 dereferenceable(32) %p) {
+; CHECK-LABEL: @matching_fp_vector_gep10(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[P:%.*]], i64 1, i64 0
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[GEP]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %gep = getelementptr inbounds <4 x float>, <4 x float>* %p, i64 1, i64 0
+  %r = load float, float* %gep, align 16
+  ret float %r
+}
+
+define float @matching_fp_vector_gep10_deref(<4 x float>* align 16 dereferenceable(31) %p) {
+; CHECK-LABEL: @matching_fp_vector_gep10_deref(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <4 x float>, <4 x float>* [[P:%.*]], i64 1, i64 0
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[GEP]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %gep = getelementptr inbounds <4 x float>, <4 x float>* %p, i64 1, i64 0
+  %r = load float, float* %gep, align 16
+  ret float %r
+}
+
+define float @nonmatching_int_vector(<2 x i64>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @nonmatching_int_vector(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <2 x i64>* [[P:%.*]] to float*
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[BC]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %bc = bitcast <2 x i64>* %p to float*
+  %r = load float, float* %bc, align 16
+  ret float %r
+}
+
+define double @less_aligned(double* align 4 dereferenceable(16) %p) {
+; CHECK-LABEL: @less_aligned(
+; CHECK-NEXT:    [[R:%.*]] = load double, double* [[P:%.*]], align 4
+; CHECK-NEXT:    ret double [[R]]
+;
+  %r = load double, double* %p, align 4
+  ret double %r
+}
+
+define float @matching_fp_scalar_small_deref(float* align 16 dereferenceable(15) %p) {
+; CHECK-LABEL: @matching_fp_scalar_small_deref(
+; CHECK-NEXT:    [[R:%.*]] = load float, float* [[P:%.*]], align 16
+; CHECK-NEXT:    ret float [[R]]
+;
+  %r = load float, float* %p, align 16
+  ret float %r
+}
+
+define i64 @larger_int_scalar(<4 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @larger_int_scalar(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <4 x float>* [[P:%.*]] to i64*
+; CHECK-NEXT:    [[R:%.*]] = load i64, i64* [[BC]], align 16
+; CHECK-NEXT:    ret i64 [[R]]
+;
+  %bc = bitcast <4 x float>* %p to i64*
+  %r = load i64, i64* %bc, align 16
+  ret i64 %r
+}
+
+define i8 @smaller_int_scalar(<4 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @smaller_int_scalar(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <4 x float>* [[P:%.*]] to i8*
+; CHECK-NEXT:    [[R:%.*]] = load i8, i8* [[BC]], align 16
+; CHECK-NEXT:    ret i8 [[R]]
+;
+  %bc = bitcast <4 x float>* %p to i8*
+  %r = load i8, i8* %bc, align 16
+  ret i8 %r
+}
+
+define double @larger_fp_scalar_256bit_vec(<8 x float>* align 32 dereferenceable(32) %p) {
+; CHECK-LABEL: @larger_fp_scalar_256bit_vec(
+; CHECK-NEXT:    [[BC:%.*]] = bitcast <8 x float>* [[P:%.*]] to double*
+; CHECK-NEXT:    [[R:%.*]] = load double, double* [[BC]], align 32
+; CHECK-NEXT:    ret double [[R]]
+;
+  %bc = bitcast <8 x float>* %p to double*
+  %r = load double, double* %bc, align 32
+  ret double %r
+}
+
+define <4 x float> @load_f32_insert_v4f32(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_f32_insert_v4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[P:%.*]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %s = load float, float* %p, align 4
+  %r = insertelement <4 x float> poison, float %s, i32 0
+  ret <4 x float> %r
+}
+
+define <4 x float> @casted_load_f32_insert_v4f32(<4 x float>* align 4 dereferenceable(16) %p) {
+; CHECK-LABEL: @casted_load_f32_insert_v4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %b = bitcast <4 x float>* %p to float*
+  %s = load float, float* %b, align 4
+  %r = insertelement <4 x float> poison, float %s, i32 0
+  ret <4 x float> %r
+}
+
+; Element type does not change cost.
+
+define <4 x i32> @load_i32_insert_v4i32(i32* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_i32_insert_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[P:%.*]] to <4 x i32>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %s = load i32, i32* %p, align 4
+  %r = insertelement <4 x i32> poison, i32 %s, i32 0
+  ret <4 x i32> %r
+}
+
+; Pointer type does not change cost.
+
+define <4 x i32> @casted_load_i32_insert_v4i32(<16 x i8>* align 4 dereferenceable(16) %p) {
+; CHECK-LABEL: @casted_load_i32_insert_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8>* [[P:%.*]] to <4 x i32>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %b = bitcast <16 x i8>* %p to i32*
+  %s = load i32, i32* %b, align 4
+  %r = insertelement <4 x i32> poison, i32 %s, i32 0
+  ret <4 x i32> %r
+}
+
+; This is canonical form for vector element access.
+
+define <4 x float> @gep00_load_f32_insert_v4f32(<4 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @gep00_load_f32_insert_v4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x float>, <4 x float>* [[P:%.*]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %gep = getelementptr inbounds <4 x float>, <4 x float>* %p, i64 0, i64 0
+  %s = load float, float* %gep, align 16
+  %r = insertelement <4 x float> poison, float %s, i64 0
+  ret <4 x float> %r
+}
+
+; Should work with addrspace as well.
+
+define <4 x float> @gep00_load_f32_insert_v4f32_addrspace(<4 x float> addrspace(44)* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @gep00_load_f32_insert_v4f32_addrspace(
+; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x float>, <4 x float> addrspace(44)* [[P:%.*]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(44)* %p, i64 0, i64 0
+  %s = load float, float addrspace(44)* %gep, align 16
+  %r = insertelement <4 x float> poison, float %s, i64 0
+  ret <4 x float> %r
+}
+
+; If there are enough dereferenceable bytes, we can offset the vector load.
+
+define <8 x i16> @gep01_load_i16_insert_v8i16(<8 x i16>* align 16 dereferenceable(18) %p) {
+; CHECK-LABEL: @gep01_load_i16_insert_v8i16(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[P:%.*]], i64 0, i64 1
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16* [[GEP]] to <8 x i16>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 2
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i64 0, i64 1
+  %s = load i16, i16* %gep, align 2
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
+
+; Can't safely load the offset vector, but can load+shuffle if it is profitable.
+
+define <8 x i16> @gep01_load_i16_insert_v8i16_deref(<8 x i16>* align 16 dereferenceable(17) %p) {
+; SSE2-LABEL: @gep01_load_i16_insert_v8i16_deref(
+; SSE2-NEXT:    [[GEP:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[P:%.*]], i64 0, i64 1
+; SSE2-NEXT:    [[S:%.*]] = load i16, i16* [[GEP]], align 2
+; SSE2-NEXT:    [[R:%.*]] = insertelement <8 x i16> poison, i16 [[S]], i64 0
+; SSE2-NEXT:    ret <8 x i16> [[R]]
+;
+; AVX2-LABEL: @gep01_load_i16_insert_v8i16_deref(
+; AVX2-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[P:%.*]], align 16
+; AVX2-NEXT:    [[R:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; AVX2-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i64 0, i64 1
+  %s = load i16, i16* %gep, align 2
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
+
+; Verify that alignment of the new load is not over-specified.
+
+define <8 x i16> @gep01_load_i16_insert_v8i16_deref_minalign(<8 x i16>* align 2 dereferenceable(16) %p) {
+; SSE2-LABEL: @gep01_load_i16_insert_v8i16_deref_minalign(
+; SSE2-NEXT:    [[GEP:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[P:%.*]], i64 0, i64 1
+; SSE2-NEXT:    [[S:%.*]] = load i16, i16* [[GEP]], align 8
+; SSE2-NEXT:    [[R:%.*]] = insertelement <8 x i16> poison, i16 [[S]], i64 0
+; SSE2-NEXT:    ret <8 x i16> [[R]]
+;
+; AVX2-LABEL: @gep01_load_i16_insert_v8i16_deref_minalign(
+; AVX2-NEXT:    [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[P:%.*]], align 2
+; AVX2-NEXT:    [[R:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; AVX2-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i64 0, i64 1
+  %s = load i16, i16* %gep, align 8
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
+
+; Negative test - if we are shuffling a load from the base pointer, the address offset
+; must be a multiple of element size.
+; TODO: Could bitcast around this limitation.
+
+define <4 x i32> @gep01_bitcast_load_i32_insert_v4i32(<16 x i8>* align 1 dereferenceable(16) %p) {
+; CHECK-LABEL: @gep01_bitcast_load_i32_insert_v4i32(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[P:%.*]], i64 0, i64 1
+; CHECK-NEXT:    [[B:%.*]] = bitcast i8* [[GEP]] to i32*
+; CHECK-NEXT:    [[S:%.*]] = load i32, i32* [[B]], align 1
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i32> poison, i32 [[S]], i64 0
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %gep = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i64 0, i64 1
+  %b = bitcast i8* %gep to i32*
+  %s = load i32, i32* %b, align 1
+  %r = insertelement <4 x i32> poison, i32 %s, i64 0
+  ret <4 x i32> %r
+}
+
+define <4 x i32> @gep012_bitcast_load_i32_insert_v4i32(<16 x i8>* align 1 dereferenceable(20) %p) {
+; CHECK-LABEL: @gep012_bitcast_load_i32_insert_v4i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <16 x i8>* [[P:%.*]] to <4 x i32>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 1
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %gep = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i64 0, i64 12
+  %b = bitcast i8* %gep to i32*
+  %s = load i32, i32* %b, align 1
+  %r = insertelement <4 x i32> poison, i32 %s, i64 0
+  ret <4 x i32> %r
+}
+
+; Negative test - if we are shuffling a load from the base pointer, the address offset
+; must be a multiple of element size and the offset must be low enough to fit in the vector
+; (bitcasting would not help this case).
+
+define <4 x i32> @gep013_bitcast_load_i32_insert_v4i32(<16 x i8>* align 1 dereferenceable(20) %p) {
+; CHECK-LABEL: @gep013_bitcast_load_i32_insert_v4i32(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <16 x i8>, <16 x i8>* [[P:%.*]], i64 0, i64 13
+; CHECK-NEXT:    [[B:%.*]] = bitcast i8* [[GEP]] to i32*
+; CHECK-NEXT:    [[S:%.*]] = load i32, i32* [[B]], align 1
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i32> poison, i32 [[S]], i64 0
+; CHECK-NEXT:    ret <4 x i32> [[R]]
+;
+  %gep = getelementptr inbounds <16 x i8>, <16 x i8>* %p, i64 0, i64 13
+  %b = bitcast i8* %gep to i32*
+  %s = load i32, i32* %b, align 1
+  %r = insertelement <4 x i32> poison, i32 %s, i64 0
+  ret <4 x i32> %r
+}
+
+; If there are enough dereferenceable bytes, we can offset the vector load.
+
+define <8 x i16> @gep10_load_i16_insert_v8i16(<8 x i16>* align 16 dereferenceable(32) %p) {
+; CHECK-LABEL: @gep10_load_i16_insert_v8i16(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[P:%.*]], i64 1, i64 0
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i16* [[GEP]] to <8 x i16>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i64 1, i64 0
+  %s = load i16, i16* %gep, align 16
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
+
+; Negative test - disable under asan because widened load can cause spurious
+; use-after-poison issues when __asan_poison_memory_region is used.
+
+define <8 x i16> @gep10_load_i16_insert_v8i16_asan(<8 x i16>* align 16 dereferenceable(32) %p) sanitize_address {
+; CHECK-LABEL: @gep10_load_i16_insert_v8i16_asan(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[P:%.*]], i64 1, i64 0
+; CHECK-NEXT:    [[S:%.*]] = load i16, i16* [[GEP]], align 16
+; CHECK-NEXT:    [[R:%.*]] = insertelement <8 x i16> poison, i16 [[S]], i64 0
+; CHECK-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i64 1, i64 0
+  %s = load i16, i16* %gep, align 16
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
+
+; hwasan and memtag should be similarly suppressed.
+
+define <8 x i16> @gep10_load_i16_insert_v8i16_hwasan(<8 x i16>* align 16 dereferenceable(32) %p) sanitize_hwaddress {
+; CHECK-LABEL: @gep10_load_i16_insert_v8i16_hwasan(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[P:%.*]], i64 1, i64 0
+; CHECK-NEXT:    [[S:%.*]] = load i16, i16* [[GEP]], align 16
+; CHECK-NEXT:    [[R:%.*]] = insertelement <8 x i16> poison, i16 [[S]], i64 0
+; CHECK-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i64 1, i64 0
+  %s = load i16, i16* %gep, align 16
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
+
+define <8 x i16> @gep10_load_i16_insert_v8i16_memtag(<8 x i16>* align 16 dereferenceable(32) %p) sanitize_memtag {
+; CHECK-LABEL: @gep10_load_i16_insert_v8i16_memtag(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[P:%.*]], i64 1, i64 0
+; CHECK-NEXT:    [[S:%.*]] = load i16, i16* [[GEP]], align 16
+; CHECK-NEXT:    [[R:%.*]] = insertelement <8 x i16> poison, i16 [[S]], i64 0
+; CHECK-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i64 1, i64 0
+  %s = load i16, i16* %gep, align 16
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
+
+; Negative test - disable under tsan because widened load may overlap bytes
+; being concurrently modified. tsan does not know that some bytes are undef.
+
+define <8 x i16> @gep10_load_i16_insert_v8i16_tsan(<8 x i16>* align 16 dereferenceable(32) %p) sanitize_thread {
+; CHECK-LABEL: @gep10_load_i16_insert_v8i16_tsan(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[P:%.*]], i64 1, i64 0
+; CHECK-NEXT:    [[S:%.*]] = load i16, i16* [[GEP]], align 16
+; CHECK-NEXT:    [[R:%.*]] = insertelement <8 x i16> poison, i16 [[S]], i64 0
+; CHECK-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i64 1, i64 0
+  %s = load i16, i16* %gep, align 16
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
+
+; Negative test - can't safely load the offset vector, but could load+shuffle.
+
+define <8 x i16> @gep10_load_i16_insert_v8i16_deref(<8 x i16>* align 16 dereferenceable(31) %p) {
+; CHECK-LABEL: @gep10_load_i16_insert_v8i16_deref(
+; CHECK-NEXT:    [[GEP:%.*]] = getelementptr inbounds <8 x i16>, <8 x i16>* [[P:%.*]], i64 1, i64 0
+; CHECK-NEXT:    [[S:%.*]] = load i16, i16* [[GEP]], align 16
+; CHECK-NEXT:    [[R:%.*]] = insertelement <8 x i16> poison, i16 [[S]], i64 0
+; CHECK-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <8 x i16>, <8 x i16>* %p, i64 1, i64 0
+  %s = load i16, i16* %gep, align 16
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
+
+; Negative test - do not alter volatile.
+
+define <4 x float> @load_f32_insert_v4f32_volatile(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_f32_insert_v4f32_volatile(
+; CHECK-NEXT:    [[S:%.*]] = load volatile float, float* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> poison, float [[S]], i32 0
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %s = load volatile float, float* %p, align 4
+  %r = insertelement <4 x float> poison, float %s, i32 0
+  ret <4 x float> %r
+}
+
+; Pointer is not as aligned as load, but that's ok.
+; The new load uses the larger alignment value.
+
+define <4 x float> @load_f32_insert_v4f32_align(float* align 1 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_f32_insert_v4f32_align(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[P:%.*]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %s = load float, float* %p, align 4
+  %r = insertelement <4 x float> poison, float %s, i32 0
+  ret <4 x float> %r
+}
+
+; Negative test - not enough bytes.
+
+define <4 x float> @load_f32_insert_v4f32_deref(float* align 4 dereferenceable(15) %p) {
+; CHECK-LABEL: @load_f32_insert_v4f32_deref(
+; CHECK-NEXT:    [[S:%.*]] = load float, float* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x float> poison, float [[S]], i32 0
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %s = load float, float* %p, align 4
+  %r = insertelement <4 x float> poison, float %s, i32 0
+  ret <4 x float> %r
+}
+
+define <8 x i32> @load_i32_insert_v8i32(i32* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_i32_insert_v8i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i32* [[P:%.*]] to <4 x i32>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <8 x i32> [[R]]
+;
+  %s = load i32, i32* %p, align 4
+  %r = insertelement <8 x i32> poison, i32 %s, i32 0
+  ret <8 x i32> %r
+}
+
+define <8 x i32> @casted_load_i32_insert_v8i32(<4 x i32>* align 4 dereferenceable(16) %p) {
+; CHECK-LABEL: @casted_load_i32_insert_v8i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = load <4 x i32>, <4 x i32>* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <8 x i32> [[R]]
+;
+  %b = bitcast <4 x i32>* %p to i32*
+  %s = load i32, i32* %b, align 4
+  %r = insertelement <8 x i32> poison, i32 %s, i32 0
+  ret <8 x i32> %r
+}
+
+define <16 x float> @load_f32_insert_v16f32(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_f32_insert_v16f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[P:%.*]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> undef, <16 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <16 x float> [[R]]
+;
+  %s = load float, float* %p, align 4
+  %r = insertelement <16 x float> poison, float %s, i32 0
+  ret <16 x float> %r
+}
+
+define <2 x float> @load_f32_insert_v2f32(float* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_f32_insert_v2f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast float* [[P:%.*]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> undef, <2 x i32> <i32 0, i32 undef>
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %s = load float, float* %p, align 4
+  %r = insertelement <2 x float> poison, float %s, i32 0
+  ret <2 x float> %r
+}
+
+; Negative test - suppress load widening for asan/hwasan/memtag/tsan.
+
+define <2 x float> @load_f32_insert_v2f32_asan(float* align 16 dereferenceable(16) %p) sanitize_address {
+; CHECK-LABEL: @load_f32_insert_v2f32_asan(
+; CHECK-NEXT:    [[S:%.*]] = load float, float* [[P:%.*]], align 4
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x float> poison, float [[S]], i32 0
+; CHECK-NEXT:    ret <2 x float> [[R]]
+;
+  %s = load float, float* %p, align 4
+  %r = insertelement <2 x float> poison, float %s, i32 0
+  ret <2 x float> %r
+}
+
+declare float* @getscaleptr()
+define void @PR47558_multiple_use_load(<2 x float>* nocapture nonnull %resultptr, <2 x float>* nocapture nonnull readonly %opptr) {
+; CHECK-LABEL: @PR47558_multiple_use_load(
+; CHECK-NEXT:    [[SCALEPTR:%.*]] = tail call nonnull align 16 dereferenceable(64) float* @getscaleptr()
+; CHECK-NEXT:    [[OP:%.*]] = load <2 x float>, <2 x float>* [[OPPTR:%.*]], align 4
+; CHECK-NEXT:    [[SCALE:%.*]] = load float, float* [[SCALEPTR]], align 16
+; CHECK-NEXT:    [[T1:%.*]] = insertelement <2 x float> poison, float [[SCALE]], i32 0
+; CHECK-NEXT:    [[T2:%.*]] = insertelement <2 x float> [[T1]], float [[SCALE]], i32 1
+; CHECK-NEXT:    [[T3:%.*]] = fmul <2 x float> [[OP]], [[T2]]
+; CHECK-NEXT:    [[T4:%.*]] = extractelement <2 x float> [[T3]], i32 0
+; CHECK-NEXT:    [[RESULT0:%.*]] = insertelement <2 x float> poison, float [[T4]], i32 0
+; CHECK-NEXT:    [[T5:%.*]] = extractelement <2 x float> [[T3]], i32 1
+; CHECK-NEXT:    [[RESULT1:%.*]] = insertelement <2 x float> [[RESULT0]], float [[T5]], i32 1
+; CHECK-NEXT:    store <2 x float> [[RESULT1]], <2 x float>* [[RESULTPTR:%.*]], align 8
+; CHECK-NEXT:    ret void
+;
+  %scaleptr = tail call nonnull align 16 dereferenceable(64) float* @getscaleptr()
+  %op = load <2 x float>, <2 x float>* %opptr, align 4
+  %scale = load float, float* %scaleptr, align 16
+  %t1 = insertelement <2 x float> poison, float %scale, i32 0
+  %t2 = insertelement <2 x float> %t1, float %scale, i32 1
+  %t3 = fmul <2 x float> %op, %t2
+  %t4 = extractelement <2 x float> %t3, i32 0
+  %result0 = insertelement <2 x float> poison, float %t4, i32 0
+  %t5 = extractelement <2 x float> %t3, i32 1
+  %result1 = insertelement <2 x float> %result0, float %t5, i32 1
+  store <2 x float> %result1, <2 x float>* %resultptr, align 8
+  ret void
+}
+
+define <4 x float> @load_v2f32_extract_insert_v4f32(<2 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_v2f32_extract_insert_v4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <2 x float>* [[P:%.*]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %l = load <2 x float>, <2 x float>* %p, align 4
+  %s = extractelement <2 x float> %l, i32 0
+  %r = insertelement <4 x float> poison, float %s, i32 0
+  ret <4 x float> %r
+}
+
+define <4 x float> @load_v8f32_extract_insert_v4f32(<8 x float>* align 16 dereferenceable(16) %p) {
+; CHECK-LABEL: @load_v8f32_extract_insert_v4f32(
+; CHECK-NEXT:    [[TMP1:%.*]] = bitcast <8 x float>* [[P:%.*]] to <4 x float>*
+; CHECK-NEXT:    [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 16
+; CHECK-NEXT:    [[R:%.*]] = shufflevector <4 x float> [[TMP2]], <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %l = load <8 x float>, <8 x float>* %p, align 4
+  %s = extractelement <8 x float> %l, i32 0
+  %r = insertelement <4 x float> poison, float %s, i32 0
+  ret <4 x float> %r
+}
+
+define <8 x i32> @load_v1i32_extract_insert_v8i32_extra_use(<1 x i32>* align 16 dereferenceable(16) %p, <1 x i32>* %store_ptr) {
+; CHECK-LABEL: @load_v1i32_extract_insert_v8i32_extra_use(
+; CHECK-NEXT:    [[L:%.*]] = load <1 x i32>, <1 x i32>* [[P:%.*]], align 4
+; CHECK-NEXT:    store <1 x i32> [[L]], <1 x i32>* [[STORE_PTR:%.*]], align 4
+; CHECK-NEXT:    [[S:%.*]] = extractelement <1 x i32> [[L]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = insertelement <8 x i32> poison, i32 [[S]], i32 0
+; CHECK-NEXT:    ret <8 x i32> [[R]]
+;
+  %l = load <1 x i32>, <1 x i32>* %p, align 4
+  store <1 x i32> %l, <1 x i32>* %store_ptr
+  %s = extractelement <1 x i32> %l, i32 0
+  %r = insertelement <8 x i32> poison, i32 %s, i32 0
+  ret <8 x i32> %r
+}
+
+; Can't safely load the offset vector, but can load+shuffle if it is profitable.
+
+define <8 x i16> @gep1_load_v2i16_extract_insert_v8i16(<2 x i16>* align 1 dereferenceable(16) %p) {
+; SSE2-LABEL: @gep1_load_v2i16_extract_insert_v8i16(
+; SSE2-NEXT:    [[GEP:%.*]] = getelementptr inbounds <2 x i16>, <2 x i16>* [[P:%.*]], i64 1
+; SSE2-NEXT:    [[L:%.*]] = load <2 x i16>, <2 x i16>* [[GEP]], align 8
+; SSE2-NEXT:    [[S:%.*]] = extractelement <2 x i16> [[L]], i32 0
+; SSE2-NEXT:    [[R:%.*]] = insertelement <8 x i16> poison, i16 [[S]], i64 0
+; SSE2-NEXT:    ret <8 x i16> [[R]]
+;
+; AVX2-LABEL: @gep1_load_v2i16_extract_insert_v8i16(
+; AVX2-NEXT:    [[TMP1:%.*]] = bitcast <2 x i16>* [[P:%.*]] to <8 x i16>*
+; AVX2-NEXT:    [[TMP2:%.*]] = load <8 x i16>, <8 x i16>* [[TMP1]], align 4
+; AVX2-NEXT:    [[R:%.*]] = shufflevector <8 x i16> [[TMP2]], <8 x i16> undef, <8 x i32> <i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+; AVX2-NEXT:    ret <8 x i16> [[R]]
+;
+  %gep = getelementptr inbounds <2 x i16>, <2 x i16>* %p, i64 1
+  %l = load <2 x i16>, <2 x i16>* %gep, align 8
+  %s = extractelement <2 x i16> %l, i32 0
+  %r = insertelement <8 x i16> poison, i16 %s, i64 0
+  ret <8 x i16> %r
+}
diff --git a/llvm/test/Transforms/VectorCombine/X86/scalarize-cmp-inseltpoison.ll b/llvm/test/Transforms/VectorCombine/X86/scalarize-cmp-inseltpoison.ll
new file mode 100644
index 0000000000000..a9214aa26e767
--- /dev/null
+++ b/llvm/test/Transforms/VectorCombine/X86/scalarize-cmp-inseltpoison.ll
@@ -0,0 +1,290 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=sse2 | FileCheck %s
+; RUN: opt < %s -vector-combine -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s
+
+declare void @use(<4 x i32>)
+declare void @usef(<4 x float>)
+
+; Eliminating an insert is profitable.
+
+define <16 x i1> @ins0_ins0_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: @ins0_ins0_i8(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = icmp eq i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <16 x i1> poison, i1 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <16 x i1> [[R]]
+;
+  %i0 = insertelement <16 x i8> poison, i8 %x, i32 0
+  %i1 = insertelement <16 x i8> poison, i8 %y, i32 0
+  %r = icmp eq <16 x i8> %i0, %i1
+  ret <16 x i1> %r
+}
+
+; Eliminating an insert is still profitable. Mismatch types on index is ok.
+
+define <8 x i1> @ins5_ins5_i16(i16 %x, i16 %y) {
+; CHECK-LABEL: @ins5_ins5_i16(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = icmp sgt i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <8 x i1> poison, i1 [[R_SCALAR]], i64 5
+; CHECK-NEXT:    ret <8 x i1> [[R]]
+;
+  %i0 = insertelement <8 x i16> poison, i16 %x, i8 5
+  %i1 = insertelement <8 x i16> poison, i16 %y, i32 5
+  %r = icmp sgt <8 x i16> %i0, %i1
+  ret <8 x i1> %r
+}
+
+; The new vector constant is calculated by constant folding.
+
+define <2 x i1> @ins1_ins1_i64(i64 %x, i64 %y) {
+; CHECK-LABEL: @ins1_ins1_i64(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = icmp sle i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i1> <i1 true, i1 false>, i1 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %i0 = insertelement <2 x i64> zeroinitializer, i64 %x, i64 1
+  %i1 = insertelement <2 x i64> <i64 1, i64 -1>, i64 %y, i32 1
+  %r = icmp sle <2 x i64> %i0, %i1
+  ret <2 x i1> %r
+}
+
+; The inserts are free, but it's still better to scalarize.
+
+define <2 x i1> @ins0_ins0_f64(double %x, double %y) {
+; CHECK-LABEL: @ins0_ins0_f64(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = fcmp nnan ninf uge double [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i1> poison, i1 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %i0 = insertelement <2 x double> poison, double %x, i32 0
+  %i1 = insertelement <2 x double> poison, double %y, i32 0
+  %r = fcmp nnan ninf uge <2 x double> %i0, %i1
+  ret <2 x i1> %r
+}
+
+; Negative test - mismatched indexes (but could fold this).
+
+define <16 x i1> @ins1_ins0_i8(i8 %x, i8 %y) {
+; CHECK-LABEL: @ins1_ins0_i8(
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <16 x i8> poison, i8 [[X:%.*]], i32 1
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <16 x i8> poison, i8 [[Y:%.*]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = icmp sle <16 x i8> [[I0]], [[I1]]
+; CHECK-NEXT:    ret <16 x i1> [[R]]
+;
+  %i0 = insertelement <16 x i8> poison, i8 %x, i32 1
+  %i1 = insertelement <16 x i8> poison, i8 %y, i32 0
+  %r = icmp sle <16 x i8> %i0, %i1
+  ret <16 x i1> %r
+}
+
+; Base vector does not have to be undef.
+
+define <4 x i1> @ins0_ins0_i32(i32 %x, i32 %y) {
+; CHECK-LABEL: @ins0_ins0_i32(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = icmp ne i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i1> poison, i1 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <4 x i1> [[R]]
+;
+  %i0 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0
+  %i1 = insertelement <4 x i32> poison, i32 %y, i32 0
+  %r = icmp ne <4 x i32> %i0, %i1
+  ret <4 x i1> %r
+}
+
+; Extra use is accounted for in cost calculation.
+
+define <4 x i1> @ins0_ins0_i32_use(i32 %x, i32 %y) {
+; CHECK-LABEL: @ins0_ins0_i32_use(
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <4 x i32> poison, i32 [[X:%.*]], i32 0
+; CHECK-NEXT:    call void @use(<4 x i32> [[I0]])
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = icmp ugt i32 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i1> poison, i1 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <4 x i1> [[R]]
+;
+  %i0 = insertelement <4 x i32> poison, i32 %x, i32 0
+  call void @use(<4 x i32> %i0)
+  %i1 = insertelement <4 x i32> poison, i32 %y, i32 0
+  %r = icmp ugt <4 x i32> %i0, %i1
+  ret <4 x i1> %r
+}
+
+; Extra use is accounted for in cost calculation.
+
+define <4 x i1> @ins1_ins1_f32_use(float %x, float %y) {
+; CHECK-LABEL: @ins1_ins1_f32_use(
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x float> poison, float [[Y:%.*]], i32 1
+; CHECK-NEXT:    call void @usef(<4 x float> [[I1]])
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = fcmp ogt float [[X:%.*]], [[Y]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i1> poison, i1 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <4 x i1> [[R]]
+;
+  %i0 = insertelement <4 x float> poison, float %x, i32 1
+  %i1 = insertelement <4 x float> poison, float %y, i32 1
+  call void @usef(<4 x float> %i1)
+  %r = fcmp ogt <4 x float> %i0, %i1
+  ret <4 x i1> %r
+}
+
+; If the scalar cmp is not cheaper than the vector cmp, extra uses can prevent the transform.
+
+define <4 x i1> @ins2_ins2_f32_uses(float %x, float %y) {
+; CHECK-LABEL: @ins2_ins2_f32_uses(
+; CHECK-NEXT:    [[I0:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i32 2
+; CHECK-NEXT:    call void @usef(<4 x float> [[I0]])
+; CHECK-NEXT:    [[I1:%.*]] = insertelement <4 x float> poison, float [[Y:%.*]], i32 2
+; CHECK-NEXT:    call void @usef(<4 x float> [[I1]])
+; CHECK-NEXT:    [[R:%.*]] = fcmp oeq <4 x float> [[I0]], [[I1]]
+; CHECK-NEXT:    ret <4 x i1> [[R]]
+;
+  %i0 = insertelement <4 x float> poison, float %x, i32 2
+  call void @usef(<4 x float> %i0)
+  %i1 = insertelement <4 x float> poison, float %y, i32 2
+  call void @usef(<4 x float> %i1)
+  %r = fcmp oeq <4 x float> %i0, %i1
+  ret <4 x i1> %r
+}
+
+define <2 x i1> @constant_op1_i64(i64 %x) {
+; CHECK-LABEL: @constant_op1_i64(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = icmp ne i64 [[X:%.*]], 42
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i1> poison, i1 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %r = icmp ne <2 x i64> %ins, <i64 42, i64 undef>
+  ret <2 x i1> %r
+}
+
+define <2 x i1> @constant_op1_i64_not_undef_lane(i64 %x) {
+; CHECK-LABEL: @constant_op1_i64_not_undef_lane(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = icmp sge i64 [[X:%.*]], 42
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i1> poison, i1 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %ins = insertelement <2 x i64> poison, i64 %x, i32 0
+  %r = icmp sge <2 x i64> %ins, <i64 42, i64 -42>
+  ret <2 x i1> %r
+}
+
+; negative test - load prevents the transform
+
+define <2 x i1> @constant_op1_i64_load(i64* %p) {
+; CHECK-LABEL: @constant_op1_i64_load(
+; CHECK-NEXT:    [[LD:%.*]] = load i64, i64* [[P:%.*]], align 4
+; CHECK-NEXT:    [[INS:%.*]] = insertelement <2 x i64> poison, i64 [[LD]], i32 0
+; CHECK-NEXT:    [[R:%.*]] = icmp eq <2 x i64> [[INS]], <i64 42, i64 -42>
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %ld = load i64, i64* %p
+  %ins = insertelement <2 x i64> poison, i64 %ld, i32 0
+  %r = icmp eq <2 x i64> %ins, <i64 42, i64 -42>
+  ret <2 x i1> %r
+}
+
+define <4 x i1> @constant_op0_i32(i32 %x) {
+; CHECK-LABEL: @constant_op0_i32(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = icmp ult i32 -42, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i1> poison, i1 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <4 x i1> [[R]]
+;
+  %ins = insertelement <4 x i32> poison, i32 %x, i32 1
+  %r = icmp ult <4 x i32> <i32 undef, i32 -42, i32 undef, i32 undef>, %ins
+  ret <4 x i1> %r
+}
+
+define <4 x i1> @constant_op0_i32_not_undef_lane(i32 %x) {
+; CHECK-LABEL: @constant_op0_i32_not_undef_lane(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = icmp ule i32 42, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i1> poison, i1 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <4 x i1> [[R]]
+;
+  %ins = insertelement <4 x i32> poison, i32 %x, i32 1
+  %r = icmp ule <4 x i32> <i32 1, i32 42, i32 42, i32 -42>, %ins
+  ret <4 x i1> %r
+}
+
+define <2 x i1> @constant_op0_f64(double %x) {
+; CHECK-LABEL: @constant_op0_f64(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = fcmp fast olt double 4.200000e+01, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i1> poison, i1 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 0
+  %r = fcmp fast olt <2 x double> <double 42.0, double undef>, %ins
+  ret <2 x i1> %r
+}
+
+define <2 x i1> @constant_op0_f64_not_undef_lane(double %x) {
+; CHECK-LABEL: @constant_op0_f64_not_undef_lane(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = fcmp nnan ueq double -4.200000e+01, [[X:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i1> poison, i1 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 1
+  %r = fcmp nnan ueq <2 x double> <double 42.0, double -42.0>, %ins
+  ret <2 x i1> %r
+}
+
+define <2 x i1> @constant_op1_f64(double %x) {
+; CHECK-LABEL: @constant_op1_f64(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = fcmp one double [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[R:%.*]] = insertelement <2 x i1> poison, i1 [[R_SCALAR]], i64 1
+; CHECK-NEXT:    ret <2 x i1> [[R]]
+;
+  %ins = insertelement <2 x double> poison, double %x, i32 1
+  %r = fcmp one <2 x double> %ins, <double undef, double 42.0>
+  ret <2 x i1> %r
+}
+
+define <4 x i1> @constant_op1_f32_not_undef_lane(float %x) {
+; CHECK-LABEL: @constant_op1_f32_not_undef_lane(
+; CHECK-NEXT:    [[R_SCALAR:%.*]] = fcmp uge float [[X:%.*]], 4.200000e+01
+; CHECK-NEXT:    [[R:%.*]] = insertelement <4 x i1> poison, i1 [[R_SCALAR]], i64 0
+; CHECK-NEXT:    ret <4 x i1> [[R]]
+;
+  %ins = insertelement <4 x float> poison, float %x, i32 0
+  %r = fcmp uge <4 x float> %ins, <float 42.0, float -42.0, float 0.0, float 1.0>
+  ret <4 x i1> %r
+}
+
+; negative test - select prevents the transform
+
+define <4 x float> @vec_select_use1(<4 x float> %x, <4 x float> %y, i32 %a, i32 %b) {
+; CHECK-LABEL: @vec_select_use1(
+; CHECK-NEXT:    [[VECA:%.*]] = insertelement <4 x i32> poison, i32 [[A:%.*]], i8 0
+; CHECK-NEXT:    [[VECB:%.*]] = insertelement <4 x i32> poison, i32 [[B:%.*]], i8 0
+; CHECK-NEXT:    [[COND:%.*]] = icmp eq <4 x i32> [[VECA]], [[VECB]]
+; CHECK-NEXT:    [[R:%.*]] = select <4 x i1> [[COND]], <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %veca = insertelement <4 x i32> poison, i32 %a, i8 0
+  %vecb = insertelement <4 x i32> poison, i32 %b, i8 0
+  %cond = icmp eq <4 x i32> %veca, %vecb
+  %r = select <4 x i1> %cond, <4 x float> %x, <4 x float> %y
+  ret <4 x float> %r
+}
+
+; negative test - select prevents the transform
+
+define <4 x float> @vec_select_use2(<4 x float> %x, <4 x float> %y, float %a) {
+; CHECK-LABEL: @vec_select_use2(
+; CHECK-NEXT:    [[VECA:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i8 0
+; CHECK-NEXT:    [[COND:%.*]] = fcmp oeq <4 x float> [[VECA]], zeroinitializer
+; CHECK-NEXT:    [[R:%.*]] = select <4 x i1> [[COND]], <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]
+; CHECK-NEXT:    ret <4 x float> [[R]]
+;
+  %veca = insertelement <4 x float> poison, float %a, i8 0
+  %cond = fcmp oeq <4 x float> %veca, zeroinitializer
+  %r = select <4 x i1> %cond, <4 x float> %x, <4 x float> %y
+  ret <4 x float> %r
+}
+
+define <4 x i1> @vector_of_pointers(i32* %t1) {
+; CHECK-LABEL: @vector_of_pointers(
+; CHECK-NEXT:    [[T6_SCALAR:%.*]] = icmp ne i32* [[T1:%.*]], null
+; CHECK-NEXT:    [[T6:%.*]] = insertelement <4 x i1> poison, i1 [[T6_SCALAR]], i64 0
+; CHECK-NEXT:    ret <4 x i1> [[T6]]
+;
+  %t5 = insertelement <4 x i32*> poison, i32* %t1, i32 0
+  %t6 = icmp ne <4 x i32*> %t5, zeroinitializer
+  ret <4 x i1> %t6
+}
diff --git a/llvm/test/tools/llvm-readobj/ELF/file-types.test b/llvm/test/tools/llvm-readobj/ELF/file-types.test
index 767ce4d646fff..f06f302b86423 100644
--- a/llvm/test/tools/llvm-readobj/ELF/file-types.test
+++ b/llvm/test/tools/llvm-readobj/ELF/file-types.test
@@ -62,7 +62,7 @@ FileHeader:
 # RUN: llvm-readelf -h %t.unknown | FileCheck %s --match-full-lines --check-prefix GNU-UNNKNOWN
 
 # LLVM-UNNKNOWN: ElfHeader {
-# LLVM-UNNKNOWN:   Type: 0xFDFF
+# LLVM-UNNKNOWN:   Type: Unknown (0xFDFF)
 
 # GNU-UNNKNOWN: ELF Header:
 # GNU-UNNKNOWN:   Type: <unknown>: fdff
@@ -72,7 +72,7 @@ FileHeader:
 # RUN: llvm-readelf -h %t6 | FileCheck %s --match-full-lines --check-prefix GNU-LOOS
 
 # LLVM-LOOS: ElfHeader {
-# LLVM-LOOS:   Type: 0xFE00
+# LLVM-LOOS:   Type: OS Specific (0xFE00)
 
 # GNU-LOOS: ELF Header:
 # GNU-LOOS:   Type: OS Specific: (fe00)
@@ -82,7 +82,7 @@ FileHeader:
 # RUN: llvm-readelf -h %t7 | FileCheck %s --match-full-lines --check-prefix GNU-HIOS
 
 # LLVM-HIOS: ElfHeader {
-# LLVM-HIOS:   Type: 0xFEFF
+# LLVM-HIOS:   Type: OS Specific (0xFEFF)
 
 # GNU-HIOS: ELF Header:
 # GNU-HIOS:   Type: OS Specific: (feff)
@@ -92,7 +92,7 @@ FileHeader:
 # RUN: llvm-readelf -h %t8 | FileCheck %s --match-full-lines --check-prefix GNU-LOPROC
 
 # LLVM-LOPROC: ElfHeader {
-# LLVM-LOPROC:   Type: 0xFF00
+# LLVM-LOPROC:   Type: Processor Specific (0xFF00)
 
 # GNU-LOPROC: ELF Header:
 # GNU-LOPROC:   Type: Processor Specific: (ff00)
@@ -102,7 +102,7 @@ FileHeader:
 # RUN: llvm-readelf -h %t9 | FileCheck %s --match-full-lines --check-prefix GNU-HIPROC
 
 # LLVM-HIPROC: ElfHeader {
-# LLVM-HIPROC:   Type: 0xFFFF
+# LLVM-HIPROC:   Type: Processor Specific (0xFFFF)
 
 # GNU-HIPROC: ELF Header:
 # GNU-HIPROC:   Type: Processor Specific: (ffff)
diff --git a/llvm/test/tools/llvm-readobj/ELF/stack-sizes.test b/llvm/test/tools/llvm-readobj/ELF/stack-sizes.test
index 9d0c0b532e5eb..8a8e481d8ff3b 100644
--- a/llvm/test/tools/llvm-readobj/ELF/stack-sizes.test
+++ b/llvm/test/tools/llvm-readobj/ELF/stack-sizes.test
@@ -442,11 +442,13 @@ Symbols:
 ## ends in a byte with the high bit set.
 
 # RUN: yaml2obj --docnum=6 %s -o %t06
-# RUN: llvm-readelf --stack-sizes %t06 2>&1 | FileCheck %s --check-prefix=BADSIZE -DFILE=%t06
-# RUN: llvm-readobj --stack-sizes %t06 2>&1 | FileCheck %s --check-prefix=BADSIZE -DFILE=%t06
+# RUN: llvm-readelf --stack-sizes %t06 2>&1 | \
+# RUN:   FileCheck %s --check-prefix=BADSIZE -DFILE=%t06 --implicit-check-not=warning:
+# RUN: llvm-readobj --stack-sizes %t06 2>&1 | \
+# RUN:   FileCheck %s --check-prefix=BADSIZE -DFILE=%t06 --implicit-check-not=warning:
 
-# BADSIZE: warning: '[[FILE]]': could not extract a valid stack size from SHT_PROGBITS section with index 2
-# BADSIZE: warning: '[[FILE]]': could not extract a valid stack size from SHT_PROGBITS section with index 3
+# BADSIZE: warning: '[[FILE]]': could not extract a valid stack size from SHT_PROGBITS section with index 2: unable to decode LEB128 at offset 0x00000008: malformed uleb128, extends past end
+# BADSIZE: warning: '[[FILE]]': could not extract a valid stack size from SHT_PROGBITS section with index 3: unable to decode LEB128 at offset 0x00000008: malformed uleb128, extends past end
 
 --- !ELF
 FileHeader:
diff --git a/llvm/test/tools/obj2yaml/ELF/gnu-hash-section.yaml b/llvm/test/tools/obj2yaml/ELF/gnu-hash-section.yaml
index 7dd0a7c870ea0..00861c0131001 100644
--- a/llvm/test/tools/obj2yaml/ELF/gnu-hash-section.yaml
+++ b/llvm/test/tools/obj2yaml/ELF/gnu-hash-section.yaml
@@ -54,9 +54,12 @@ Sections:
 # INVALID-NEXT: - Name:        .gnu.hash.broken.maskwords
 # INVALID-NEXT:   Type:        SHT_GNU_HASH
 # INVALID-NEXT:   Content:     '00000000000000000100000000000000'
-# INVALID-NEXT: - Name:        .gnu.hash.broken.nbuckets
+# INVALID-NEXT: - Name:        .gnu.hash.broken.nbuckets.a
 # INVALID-NEXT:   Type:        SHT_GNU_HASH
 # INVALID-NEXT:   Content:     '01000000000000000000000000000000'
+# INVALID-NEXT: - Name:        .gnu.hash.broken.nbuckets.b
+# INVALID-NEXT:   Type:        SHT_GNU_HASH
+# INVALID-NEXT:   Content:     FFFFFFFF000000000100000000000000{{$}}
 # INVALID-NEXT: - Name:        .gnu.hash.hashvalues.ok
 # INVALID-NEXT:   Type:        SHT_GNU_HASH
 # INVALID-NEXT:   Header:
@@ -108,9 +111,9 @@ Sections:
     BloomFilter: []
     HashBuckets: []
     HashValues:  []
-## Case 4: NBuckets field is broken, it says that the number of entries
+## Case 4(a): NBuckets field is broken, it says that the number of entries
 ## in the hash buckets is 1, but it is empty.
-  - Name:  .gnu.hash.broken.nbuckets
+  - Name:  .gnu.hash.broken.nbuckets.a
     Type:  SHT_GNU_HASH
     Header:
       SymNdx: 0x0
@@ -120,6 +123,18 @@ Sections:
     BloomFilter: []
     HashBuckets: []
     HashValues:  []
+## Case 4(b): NBuckets = 0xFFFFFFFF is incorrect. The result will cause 32-bit
+## unsigned overflows if we keep intermediate expressions uint32_t.
+  - Name:  .gnu.hash.broken.nbuckets.b
+    Type:  SHT_GNU_HASH
+    Header:
+      SymNdx: 0x0
+      Shift2: 0x0
+      MaskWords: 0x1
+      NBuckets:  0xFFFFFFFF
+    BloomFilter: []
+    HashBuckets: []
+    HashValues:  []
 ## Case 5: Check that we use the various properties to dump the data when it
 ## has a size that is a multiple of 4, but fallback to dumping the whole section
 ## using the "Content" property otherwise.
diff --git a/llvm/test/tools/obj2yaml/ELF/hash-section.yaml b/llvm/test/tools/obj2yaml/ELF/hash-section.yaml
index 389b4bbb6972a..57d823b3a0be6 100644
--- a/llvm/test/tools/obj2yaml/ELF/hash-section.yaml
+++ b/llvm/test/tools/obj2yaml/ELF/hash-section.yaml
@@ -49,6 +49,13 @@ Sections:
 # CONTENT-NEXT: - Name:    .oversized
 # CONTENT-NEXT:   Type:    SHT_HASH
 # CONTENT-NEXT:   Content: '0100000002000000030000000400000000'
+# CONTENT-NEXT: - Name:    .overflow1
+# CONTENT-NEXT:   Type:    SHT_HASH
+# CONTENT-NEXT:   Content: 01000000FFFFFFFF{{$}}
+# CONTENT-NEXT: - Name:    .overflow2
+# CONTENT-NEXT:   Type:    SHT_HASH
+# CONTENT-NEXT:   Content: FFFFFFFF01000000{{$}}
+# CONTENT-NEXT: ...
 
 --- !ELF
 FileHeader:
@@ -74,6 +81,20 @@ Sections:
   - Name:    .oversized
     Type:    SHT_HASH
     Content: '0100000002000000030000000400000000'
+## Case 5, 6: NChain/NBucket are incorrect and causing 32-bit
+##            unsigned overflows of intermediate expressions.
+  - Name:    .overflow1
+    Type:    SHT_HASH
+    Bucket:  [ ]
+    Chain:   [ ]
+    NBucket: 0x1
+    NChain:  0xffffffff
+  - Name:    .overflow2
+    Type:    SHT_HASH
+    Bucket:  [ ]
+    Chain:   [ ]
+    NBucket: 0xffffffff
+    NChain:  0x1
 
 ## Check how we dump the "EntSize" field. When the sh_entsize is 4,
 ## we don't print it, because it is the default value for the SHT_HASH section.
diff --git a/llvm/test/tools/sycl-post-link/erase_used.ll b/llvm/test/tools/sycl-post-link/erase_used.ll
index 18b712abc8eab..bfdb095ed5dec 100644
--- a/llvm/test/tools/sycl-post-link/erase_used.ll
+++ b/llvm/test/tools/sycl-post-link/erase_used.ll
@@ -1,9 +1,9 @@
 ; This test checks that the post-link tool does not add "llvm.used" global to
 ; the output modules when splitting kernels.
 ;
-; RUN: sycl-post-link -split=kernel -S %s -o %T/files.table
-; RUN: FileCheck %s -input-file=%T/files_0.ll
-; RUN: FileCheck %s -input-file=%T/files_1.ll
+; RUN: sycl-post-link -split=kernel -S %s -o %t.files.table
+; RUN: FileCheck %s -input-file=%t.files_0.ll
+; RUN: FileCheck %s -input-file=%t.files_1.ll
 
 target triple = "spir64-unknown-unknown-sycldevice"
 
diff --git a/llvm/test/tools/sycl-post-link/one-kernel-per-module.ll b/llvm/test/tools/sycl-post-link/one-kernel-per-module.ll
index 0e0b829182766..c14a0e3a15962 100644
--- a/llvm/test/tools/sycl-post-link/one-kernel-per-module.ll
+++ b/llvm/test/tools/sycl-post-link/one-kernel-per-module.ll
@@ -1,10 +1,10 @@
-; RUN: sycl-post-link -split=kernel -symbols -S %s -o %T/files.table
-; RUN: FileCheck %s -input-file=%T/files_0.ll --check-prefixes CHECK-MODULE0,CHECK
-; RUN: FileCheck %s -input-file=%T/files_1.ll --check-prefixes CHECK-MODULE1,CHECK
-; RUN: FileCheck %s -input-file=%T/files_2.ll --check-prefixes CHECK-MODULE2,CHECK
-; RUN: FileCheck %s -input-file=%T/files_0.sym --check-prefixes CHECK-MODULE0-TXT
-; RUN: FileCheck %s -input-file=%T/files_1.sym --check-prefixes CHECK-MODULE1-TXT
-; RUN: FileCheck %s -input-file=%T/files_2.sym --check-prefixes CHECK-MODULE2-TXT
+; RUN: sycl-post-link -split=kernel -symbols -S %s -o %t.files.table
+; RUN: FileCheck %s -input-file=%t.files_0.ll --check-prefixes CHECK-MODULE0,CHECK
+; RUN: FileCheck %s -input-file=%t.files_1.ll --check-prefixes CHECK-MODULE1,CHECK
+; RUN: FileCheck %s -input-file=%t.files_2.ll --check-prefixes CHECK-MODULE2,CHECK
+; RUN: FileCheck %s -input-file=%t.files_0.sym --check-prefixes CHECK-MODULE0-TXT
+; RUN: FileCheck %s -input-file=%t.files_1.sym --check-prefixes CHECK-MODULE1-TXT
+; RUN: FileCheck %s -input-file=%t.files_2.sym --check-prefixes CHECK-MODULE2-TXT
 ; ModuleID = 'one-kernel-per-module.ll'
 source_filename = "one-kernel-per-module.ll"
 target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
diff --git a/llvm/tools/llvm-cov/CodeCoverage.cpp b/llvm/tools/llvm-cov/CodeCoverage.cpp
index 8ef4b747a0fbb..a453e975fca9d 100644
--- a/llvm/tools/llvm-cov/CodeCoverage.cpp
+++ b/llvm/tools/llvm-cov/CodeCoverage.cpp
@@ -436,16 +436,11 @@ void CodeCoverageTool::remapPathNames(const CoverageMapping &Coverage) {
 void CodeCoverageTool::removeUnmappedInputs(const CoverageMapping &Coverage) {
   std::vector<StringRef> CoveredFiles = Coverage.getUniqueSourceFiles();
 
-  auto UncoveredFilesIt = SourceFiles.end();
   // The user may have specified source files which aren't in the coverage
   // mapping. Filter these files away.
-  UncoveredFilesIt = std::remove_if(
-      SourceFiles.begin(), SourceFiles.end(), [&](const std::string &SF) {
-        return !std::binary_search(CoveredFiles.begin(), CoveredFiles.end(),
-                                   SF);
-      });
-
-  SourceFiles.erase(UncoveredFilesIt, SourceFiles.end());
+  llvm::erase_if(SourceFiles, [&](const std::string &SF) {
+    return !std::binary_search(CoveredFiles.begin(), CoveredFiles.end(), SF);
+  });
 }
 
 void CodeCoverageTool::demangleSymbols(const CoverageMapping &Coverage) {
diff --git a/llvm/tools/llvm-lipo/llvm-lipo.cpp b/llvm/tools/llvm-lipo/llvm-lipo.cpp
index 6761f9951e58a..7fbe489ecc6fd 100644
--- a/llvm/tools/llvm-lipo/llvm-lipo.cpp
+++ b/llvm/tools/llvm-lipo/llvm-lipo.cpp
@@ -538,9 +538,8 @@ static void updateAlignments(Range &Slices,
 static void checkUnusedAlignments(ArrayRef<Slice> Slices,
                                   const StringMap<const uint32_t> &Alignments) {
   auto HasArch = [&](StringRef Arch) {
-    return llvm::find_if(Slices, [Arch](Slice S) {
-             return S.getArchString() == Arch;
-           }) != Slices.end();
+    return llvm::any_of(Slices,
+                        [Arch](Slice S) { return S.getArchString() == Arch; });
   };
   for (StringRef Arch : Alignments.keys())
     if (!HasArch(Arch))
diff --git a/llvm/tools/llvm-nm/llvm-nm.cpp b/llvm/tools/llvm-nm/llvm-nm.cpp
index 9680149d4f8cf..d9dc1f1b419ce 100644
--- a/llvm/tools/llvm-nm/llvm-nm.cpp
+++ b/llvm/tools/llvm-nm/llvm-nm.cpp
@@ -1811,9 +1811,7 @@ static bool checkMachOAndArchFlags(SymbolicFile *O, std::string &Filename) {
                                        &McpuDefault, &ArchFlag);
   }
   const std::string ArchFlagName(ArchFlag);
-  if (none_of(ArchFlags, [&](const std::string &Name) {
-        return Name == ArchFlagName;
-      })) {
+  if (!llvm::is_contained(ArchFlags, ArchFlagName)) {
     error("No architecture specified", Filename);
     return false;
   }
@@ -2115,8 +2113,7 @@ static void dumpSymbolNamesFromFile(std::string &Filename) {
     for (const TapiUniversal::ObjectForArch &I : TU->objects()) {
       StringRef ArchName = I.getArchFlagName();
       const bool ShowArch =
-          ArchFlags.empty() ||
-          any_of(ArchFlags, [&](StringRef Name) { return Name == ArchName; });
+          ArchFlags.empty() || llvm::is_contained(ArchFlags, ArchName);
       if (!ShowArch)
         continue;
       if (!AddInlinedInfo && !I.isTopLevelLib())
diff --git a/llvm/tools/llvm-objcopy/COFF/Object.cpp b/llvm/tools/llvm-objcopy/COFF/Object.cpp
index 2a57f9707055f..cf3afe5e545ef 100644
--- a/llvm/tools/llvm-objcopy/COFF/Object.cpp
+++ b/llvm/tools/llvm-objcopy/COFF/Object.cpp
@@ -40,17 +40,14 @@ const Symbol *Object::findSymbol(size_t UniqueId) const {
 Error Object::removeSymbols(
     function_ref<Expected<bool>(const Symbol &)> ToRemove) {
   Error Errs = Error::success();
-  Symbols.erase(std::remove_if(std::begin(Symbols), std::end(Symbols),
-                               [ToRemove, &Errs](const Symbol &Sym) {
-                                 Expected<bool> ShouldRemove = ToRemove(Sym);
-                                 if (!ShouldRemove) {
-                                   Errs = joinErrors(std::move(Errs),
-                                                     ShouldRemove.takeError());
-                                   return false;
-                                 }
-                                 return *ShouldRemove;
-                               }),
-                std::end(Symbols));
+  llvm::erase_if(Symbols, [ToRemove, &Errs](const Symbol &Sym) {
+    Expected<bool> ShouldRemove = ToRemove(Sym);
+    if (!ShouldRemove) {
+      Errs = joinErrors(std::move(Errs), ShouldRemove.takeError());
+      return false;
+    }
+    return *ShouldRemove;
+  });
 
   updateSymbols();
   return Errs;
diff --git a/llvm/tools/llvm-objcopy/MachO/Object.cpp b/llvm/tools/llvm-objcopy/MachO/Object.cpp
index e0a59b1804654..cdb97531fb66f 100644
--- a/llvm/tools/llvm-objcopy/MachO/Object.cpp
+++ b/llvm/tools/llvm-objcopy/MachO/Object.cpp
@@ -26,9 +26,7 @@ SymbolEntry *SymbolTable::getSymbolByIndex(uint32_t Index) {
 
 void SymbolTable::removeSymbols(
     function_ref<bool(const std::unique_ptr<SymbolEntry> &)> ToRemove) {
-  Symbols.erase(
-      std::remove_if(std::begin(Symbols), std::end(Symbols), ToRemove),
-      std::end(Symbols));
+  llvm::erase_if(Symbols, ToRemove);
 }
 
 void Object::updateLoadCommandIndexes() {
diff --git a/llvm/tools/llvm-objcopy/wasm/Object.cpp b/llvm/tools/llvm-objcopy/wasm/Object.cpp
index 0c416483663f2..e7a2956fedcaf 100644
--- a/llvm/tools/llvm-objcopy/wasm/Object.cpp
+++ b/llvm/tools/llvm-objcopy/wasm/Object.cpp
@@ -26,9 +26,7 @@ void Object::addSectionWithOwnedContents(
 
 void Object::removeSections(function_ref<bool(const Section &)> ToRemove) {
   // TODO: remove reloc sections for the removed section, handle symbols, etc.
-  Sections.erase(
-      std::remove_if(std::begin(Sections), std::end(Sections), ToRemove),
-      std::end(Sections));
+  llvm::erase_if(Sections, ToRemove);
 }
 
 } // end namespace wasm
diff --git a/llvm/tools/llvm-objdump/MachODump.cpp b/llvm/tools/llvm-objdump/MachODump.cpp
index b3ec20f97c97b..1fa9879c821a6 100644
--- a/llvm/tools/llvm-objdump/MachODump.cpp
+++ b/llvm/tools/llvm-objdump/MachODump.cpp
@@ -1889,9 +1889,7 @@ static bool checkMachOAndArchFlags(ObjectFile *O, StringRef Filename) {
                                        &McpuDefault, &ArchFlag);
   }
   const std::string ArchFlagName(ArchFlag);
-  if (none_of(ArchFlags, [&](const std::string &Name) {
-        return Name == ArchFlagName;
-      })) {
+  if (!llvm::is_contained(ArchFlags, ArchFlagName)) {
     WithColor::error(errs(), "llvm-objdump")
         << Filename << ": no architecture specified.\n";
     return false;
diff --git a/llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp b/llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
index 00092e71c6b49..19f4880ab5eb7 100644
--- a/llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
+++ b/llvm/tools/llvm-pdbutil/llvm-pdbutil.cpp
@@ -892,9 +892,9 @@ static void dumpBytes(StringRef Path) {
 bool opts::pretty::shouldDumpSymLevel(SymLevel Search) {
   if (SymTypes.empty())
     return true;
-  if (llvm::find(SymTypes, Search) != SymTypes.end())
+  if (llvm::is_contained(SymTypes, Search))
     return true;
-  if (llvm::find(SymTypes, SymLevel::All) != SymTypes.end())
+  if (llvm::is_contained(SymTypes, SymLevel::All))
     return true;
   return false;
 }
diff --git a/llvm/tools/llvm-profgen/llvm-profgen.cpp b/llvm/tools/llvm-profgen/llvm-profgen.cpp
index 665ee7c791a7a..0f4d8f015439b 100644
--- a/llvm/tools/llvm-profgen/llvm-profgen.cpp
+++ b/llvm/tools/llvm-profgen/llvm-profgen.cpp
@@ -35,13 +35,13 @@ using namespace sampleprof;
 int main(int argc, const char *argv[]) {
   InitLLVM X(argc, argv);
 
-  cl::ParseCommandLineOptions(argc, argv, "llvm SPGO profile generator\n");
-
   // Initialize targets and assembly printers/parsers.
   InitializeAllTargetInfos();
   InitializeAllTargetMCs();
   InitializeAllDisassemblers();
 
+  cl::ParseCommandLineOptions(argc, argv, "llvm SPGO profile generator\n");
+
   // Load binaries and parse perf events and samples
   PerfReader Reader(BinaryFilenames);
   Reader.parsePerfTraces(PerfTraceFilenames);
diff --git a/llvm/tools/llvm-readobj/ELFDumper.cpp b/llvm/tools/llvm-readobj/ELFDumper.cpp
index 178cca87f2d4a..8fbef39c5a258 100644
--- a/llvm/tools/llvm-readobj/ELFDumper.cpp
+++ b/llvm/tools/llvm-readobj/ELFDumper.cpp
@@ -80,35 +80,6 @@ using namespace ELF;
 #define ENUM_ENT_1(enum)                                                       \
   { #enum, #enum, ELF::enum }
 
-#define TYPEDEF_ELF_TYPES(ELFT)                                                \
-  using ELFO = ELFFile<ELFT>;                                                  \
-  using Elf_Addr = typename ELFT::Addr;                                        \
-  using Elf_Shdr = typename ELFT::Shdr;                                        \
-  using Elf_Sym = typename ELFT::Sym;                                          \
-  using Elf_Dyn = typename ELFT::Dyn;                                          \
-  using Elf_Dyn_Range = typename ELFT::DynRange;                               \
-  using Elf_Rel = typename ELFT::Rel;                                          \
-  using Elf_Rela = typename ELFT::Rela;                                        \
-  using Elf_Relr = typename ELFT::Relr;                                        \
-  using Elf_Rel_Range = typename ELFT::RelRange;                               \
-  using Elf_Rela_Range = typename ELFT::RelaRange;                             \
-  using Elf_Relr_Range = typename ELFT::RelrRange;                             \
-  using Elf_Phdr = typename ELFT::Phdr;                                        \
-  using Elf_Half = typename ELFT::Half;                                        \
-  using Elf_Ehdr = typename ELFT::Ehdr;                                        \
-  using Elf_Word = typename ELFT::Word;                                        \
-  using Elf_Hash = typename ELFT::Hash;                                        \
-  using Elf_GnuHash = typename ELFT::GnuHash;                                  \
-  using Elf_Note  = typename ELFT::Note;                                       \
-  using Elf_Sym_Range = typename ELFT::SymRange;                               \
-  using Elf_Versym = typename ELFT::Versym;                                    \
-  using Elf_Verneed = typename ELFT::Verneed;                                  \
-  using Elf_Vernaux = typename ELFT::Vernaux;                                  \
-  using Elf_Verdef = typename ELFT::Verdef;                                    \
-  using Elf_Verdaux = typename ELFT::Verdaux;                                  \
-  using Elf_CGProfile = typename ELFT::CGProfile;                              \
-  using uintX_t = typename ELFT::uint;
-
 namespace {
 
 template <class ELFT> class DumpStyle;
@@ -304,7 +275,7 @@ template <typename ELFT> class ELFDumper : public ObjDumper {
 private:
   std::unique_ptr<DumpStyle<ELFT>> ELFDumperStyle;
 
-  TYPEDEF_ELF_TYPES(ELFT)
+  LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
 
   Expected<DynRegionInfo> createDRI(uint64_t Offset, uint64_t Size,
                                     uint64_t EntSize) {
@@ -505,7 +476,9 @@ Expected<ArrayRef<typename ELFT::Versym>>
 ELFDumper<ELFT>::getVersionTable(const Elf_Shdr &Sec, ArrayRef<Elf_Sym> *SymTab,
                                  StringRef *StrTab) const {
   assert((!SymTab && !StrTab) || (SymTab && StrTab));
-  if (uintptr_t(Obj.base() + Sec.sh_offset) % sizeof(uint16_t) != 0)
+  if (reinterpret_cast<uintptr_t>(Obj.base() + Sec.sh_offset) %
+          sizeof(uint16_t) !=
+      0)
     return createError("the " + describe(Sec) + " is misaligned");
 
   Expected<ArrayRef<Elf_Versym>> VersionsOrErr =
@@ -576,7 +549,7 @@ ELFDumper<ELFT>::getVersionDefinitions(const Elf_Shdr &Sec) const {
       return createError("invalid " + describe(Sec) + ": version definition " +
                          Twine(I) + " goes past the end of the section");
 
-    if (uintptr_t(VerdefBuf) % sizeof(uint32_t) != 0)
+    if (reinterpret_cast<uintptr_t>(VerdefBuf) % sizeof(uint32_t) != 0)
       return createError(
           "invalid " + describe(Sec) +
           ": found a misaligned version definition entry at offset 0x" +
@@ -598,7 +571,7 @@ ELFDumper<ELFT>::getVersionDefinitions(const Elf_Shdr &Sec) const {
 
     const uint8_t *VerdauxBuf = VerdefBuf + D->vd_aux;
     for (unsigned J = 0; J < D->vd_cnt; ++J) {
-      if (uintptr_t(VerdauxBuf) % sizeof(uint32_t) != 0)
+      if (reinterpret_cast<uintptr_t>(VerdauxBuf) % sizeof(uint32_t) != 0)
         return createError("invalid " + describe(Sec) +
                            ": found a misaligned auxiliary entry at offset 0x" +
                            Twine::utohexstr(VerdauxBuf - Start));
@@ -644,7 +617,7 @@ ELFDumper<ELFT>::getVersionDependencies(const Elf_Shdr &Sec) const {
       return createError("invalid " + describe(Sec) + ": version dependency " +
                          Twine(I) + " goes past the end of the section");
 
-    if (uintptr_t(VerneedBuf) % sizeof(uint32_t) != 0)
+    if (reinterpret_cast<uintptr_t>(VerneedBuf) % sizeof(uint32_t) != 0)
       return createError(
           "invalid " + describe(Sec) +
           ": found a misaligned version dependency entry at offset 0x" +
@@ -670,7 +643,7 @@ ELFDumper<ELFT>::getVersionDependencies(const Elf_Shdr &Sec) const {
 
     const uint8_t *VernauxBuf = VerneedBuf + Verneed->vn_aux;
     for (unsigned J = 0; J < Verneed->vn_cnt; ++J) {
-      if (uintptr_t(VernauxBuf) % sizeof(uint32_t) != 0)
+      if (reinterpret_cast<uintptr_t>(VernauxBuf) % sizeof(uint32_t) != 0)
         return createError("invalid " + describe(Sec) +
                            ": found a misaligned auxiliary entry at offset 0x" +
                            Twine::utohexstr(VernauxBuf - Start));
@@ -748,7 +721,7 @@ template <class ELFT> class MipsGOTParser;
 
 template <typename ELFT> class DumpStyle {
 public:
-  TYPEDEF_ELF_TYPES(ELFT)
+  LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
 
   DumpStyle(const ELFDumper<ELFT> &Dumper)
       : Obj(Dumper.getElfObject().getELFFile()), ElfObj(Dumper.getElfObject()),
@@ -786,7 +759,7 @@ template <typename ELFT> class DumpStyle {
   virtual void printStackSizes() = 0;
   void printNonRelocatableStackSizes(std::function<void()> PrintHeader);
   void printRelocatableStackSizes(std::function<void()> PrintHeader);
-  void printFunctionStackSize(uint64_t SymValue,
+  bool printFunctionStackSize(uint64_t SymValue,
                               Optional<const Elf_Shdr *> FunctionSec,
                               const Elf_Shdr &StackSizeSec, DataExtractor Data,
                               uint64_t *Offset);
@@ -838,7 +811,7 @@ template <typename ELFT> class GNUStyle : public DumpStyle<ELFT> {
   formatted_raw_ostream &OS;
 
 public:
-  TYPEDEF_ELF_TYPES(ELFT)
+  LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
 
   GNUStyle(ScopedPrinter &W, const ELFDumper<ELFT> &Dumper)
       : DumpStyle<ELFT>(Dumper),
@@ -965,7 +938,7 @@ void DumpStyle<ELFT>::reportUniqueWarning(const Twine &Msg) const {
 
 template <typename ELFT> class LLVMStyle : public DumpStyle<ELFT> {
 public:
-  TYPEDEF_ELF_TYPES(ELFT)
+  LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
 
   LLVMStyle(ScopedPrinter &W, const ELFDumper<ELFT> &Dumper)
       : DumpStyle<ELFT>(Dumper), W(W) {}
@@ -2938,12 +2911,12 @@ namespace {
 
 template <class ELFT> class MipsGOTParser {
 public:
-  TYPEDEF_ELF_TYPES(ELFT)
-  using Entry = typename ELFO::Elf_Addr;
+  LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
+  using Entry = typename ELFT::Addr;
   using Entries = ArrayRef<Entry>;
 
   const bool IsStatic;
-  const ELFO &Obj;
+  const ELFFile<ELFT> &Obj;
   const ELFDumper<ELFT> &Dumper;
 
   MipsGOTParser(const ELFDumper<ELFT> &D);
@@ -3513,6 +3486,15 @@ static std::string getSectionHeaderTableIndexString(const ELFFile<ELFT> &Obj,
          to_string((*ArrOrErr)[0].sh_link) + ")";
 }
 
+static const EnumEntry<unsigned> *getObjectFileEnumEntry(unsigned Type) {
+  auto It = llvm::find_if(ElfObjectFileType, [&](const EnumEntry<unsigned> &E) {
+    return E.Value == Type;
+  });
+  if (It != makeArrayRef(ElfObjectFileType).end())
+    return It;
+  return nullptr;
+}
+
 template <class ELFT> void GNUStyle<ELFT>::printFileHeaders() {
   const Elf_Ehdr &e = this->Obj.getHeader();
   OS << "ELF Header:\n";
@@ -3537,17 +3519,15 @@ template <class ELFT> void GNUStyle<ELFT>::printFileHeaders() {
   printFields(OS,
               "ABI Version:", std::to_string(e.e_ident[ELF::EI_ABIVERSION]));
 
-  Str = printEnum(e.e_type, makeArrayRef(ElfObjectFileType));
-  if (makeArrayRef(ElfObjectFileType).end() ==
-      llvm::find_if(ElfObjectFileType, [&](const EnumEntry<unsigned> &E) {
-        return E.Value == e.e_type;
-      })) {
+  if (const EnumEntry<unsigned> *E = getObjectFileEnumEntry(e.e_type)) {
+    Str = E->AltName.str();
+  } else {
     if (e.e_type >= ET_LOPROC)
-      Str = "Processor Specific: (" + Str + ")";
+      Str = "Processor Specific: (" + to_hexString(e.e_type, false) + ")";
     else if (e.e_type >= ET_LOOS)
-      Str = "OS Specific: (" + Str + ")";
+      Str = "OS Specific: (" + to_hexString(e.e_type, false) + ")";
     else
-      Str = "<unknown>: " + Str;
+      Str = "<unknown>: " + to_hexString(e.e_type, false);
   }
   printFields(OS, "Type:", Str);
 
@@ -5853,7 +5833,7 @@ template <class ELFT> void GNUStyle<ELFT>::printDependentLibs() {
 }
 
 template <class ELFT>
-void DumpStyle<ELFT>::printFunctionStackSize(
+bool DumpStyle<ELFT>::printFunctionStackSize(
     uint64_t SymValue, Optional<const Elf_Shdr *> FunctionSec,
     const Elf_Shdr &StackSizeSec, DataExtractor Data, uint64_t *Offset) {
   uint32_t FuncSymIndex = 0;
@@ -5913,16 +5893,16 @@ void DumpStyle<ELFT>::printFunctionStackSize(
 
   // Extract the size. The expectation is that Offset is pointing to the right
   // place, i.e. past the function address.
-  uint64_t PrevOffset = *Offset;
-  uint64_t StackSize = Data.getULEB128(Offset);
-  // getULEB128() does not advance Offset if it is not able to extract a valid
-  // integer.
-  if (*Offset == PrevOffset) {
+  Error Err = Error::success();
+  uint64_t StackSize = Data.getULEB128(Offset, &Err);
+  if (Err) {
     reportUniqueWarning("could not extract a valid stack size from " +
-                        describe(Obj, StackSizeSec));
-    return;
+                        describe(Obj, StackSizeSec) + ": " +
+                        toString(std::move(Err)));
+    return false;
   }
   printStackSizeEntry(StackSize, FuncName);
+  return true;
 }
 
 template <class ELFT>
@@ -6011,8 +5991,9 @@ void DumpStyle<ELFT>::printNonRelocatableStackSizes(
         break;
       }
       uint64_t SymValue = Data.getAddress(&Offset);
-      printFunctionStackSize(SymValue, /*FunctionSec=*/None, Sec, Data,
-                             &Offset);
+      if (!printFunctionStackSize(SymValue, /*FunctionSec=*/None, Sec, Data,
+                                  &Offset))
+        break;
     }
   }
 }
@@ -6341,7 +6322,19 @@ template <class ELFT> void LLVMStyle<ELFT>::printFileHeaders() {
       W.printBinary("Unused", makeArrayRef(E.e_ident).slice(ELF::EI_PAD));
     }
 
-    W.printEnum("Type", E.e_type, makeArrayRef(ElfObjectFileType));
+    std::string TypeStr;
+    if (const EnumEntry<unsigned> *Ent = getObjectFileEnumEntry(E.e_type)) {
+      TypeStr = Ent->Name.str();
+    } else {
+      if (E.e_type >= ET_LOPROC)
+        TypeStr = "Processor Specific";
+      else if (E.e_type >= ET_LOOS)
+        TypeStr = "OS Specific";
+      else
+        TypeStr = "Unknown";
+    }
+    W.printString("Type", TypeStr + " (0x" + to_hexString(E.e_type) + ")");
+
     W.printEnum("Machine", E.e_machine, makeArrayRef(ElfMachineType));
     W.printNumber("Version", E.e_version);
     W.printHex("Entry", E.e_entry);
diff --git a/llvm/tools/llvm-size/llvm-size.cpp b/llvm/tools/llvm-size/llvm-size.cpp
index 987270e98c483..4f98a4c0ec10b 100644
--- a/llvm/tools/llvm-size/llvm-size.cpp
+++ b/llvm/tools/llvm-size/llvm-size.cpp
@@ -542,9 +542,7 @@ static bool checkMachOAndArchFlags(ObjectFile *O, StringRef Filename) {
     H = MachO->MachOObjectFile::getHeader();
     T = MachOObjectFile::getArchTriple(H.cputype, H.cpusubtype);
   }
-  if (none_of(ArchFlags, [&](const std::string &Name) {
-        return Name == T.getArchName();
-      })) {
+  if (!is_contained(ArchFlags, T.getArchName())) {
     error("no architecture specified", Filename);
     return false;
   }
diff --git a/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp b/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
index 358e0e284fca0..9c68acee0ae26 100644
--- a/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
+++ b/llvm/tools/llvm-symbolizer/llvm-symbolizer.cpp
@@ -329,10 +329,8 @@ int main(int argc, char **argv) {
     while (fgets(InputString, sizeof(InputString), stdin)) {
       // Strip newline characters.
       std::string StrippedInputString(InputString);
-      StrippedInputString.erase(
-          std::remove_if(StrippedInputString.begin(), StrippedInputString.end(),
-                         [](char c) { return c == '\r' || c == '\n'; }),
-          StrippedInputString.end());
+      llvm::erase_if(StrippedInputString,
+                     [](char c) { return c == '\r' || c == '\n'; });
       symbolizeInput(Args, AdjustVMA, IsAddr2Line, OutputStyle,
                      StrippedInputString, Symbolizer, Printer);
       outs().flush();
diff --git a/llvm/tools/obj2yaml/elf2yaml.cpp b/llvm/tools/obj2yaml/elf2yaml.cpp
index 1f9ff88f042a5..da32eaba5a692 100644
--- a/llvm/tools/obj2yaml/elf2yaml.cpp
+++ b/llvm/tools/obj2yaml/elf2yaml.cpp
@@ -24,15 +24,7 @@ namespace {
 
 template <class ELFT>
 class ELFDumper {
-  typedef object::Elf_Sym_Impl<ELFT> Elf_Sym;
-  typedef typename ELFT::Dyn Elf_Dyn;
-  typedef typename ELFT::Shdr Elf_Shdr;
-  typedef typename ELFT::Word Elf_Word;
-  typedef typename ELFT::Rel Elf_Rel;
-  typedef typename ELFT::Rela Elf_Rela;
-  using Elf_Relr = typename ELFT::Relr;
-  using Elf_Nhdr = typename ELFT::Nhdr;
-  using Elf_Note = typename ELFT::Note;
+  LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
 
   ArrayRef<Elf_Shdr> Sections;
   ArrayRef<Elf_Sym> SymTable;
@@ -1232,8 +1224,8 @@ ELFDumper<ELFT>::dumpHashSection(const Elf_Shdr *Shdr) {
 
   DataExtractor::Cursor Cur(0);
   DataExtractor Data(Content, Obj.isLE(), /*AddressSize=*/0);
-  uint32_t NBucket = Data.getU32(Cur);
-  uint32_t NChain = Data.getU32(Cur);
+  uint64_t NBucket = Data.getU32(Cur);
+  uint64_t NChain = Data.getU32(Cur);
   if (Content.size() != (2 + NBucket + NChain) * 4) {
     S->Content = yaml::BinaryRef(Content);
     if (Cur)
@@ -1271,9 +1263,9 @@ ELFDumper<ELFT>::dumpGnuHashSection(const Elf_Shdr *Shdr) {
 
   ELFYAML::GnuHashHeader Header;
   DataExtractor::Cursor Cur(0);
-  uint32_t NBuckets = Data.getU32(Cur);
+  uint64_t NBuckets = Data.getU32(Cur);
   Header.SymNdx = Data.getU32(Cur);
-  uint32_t MaskWords = Data.getU32(Cur);
+  uint64_t MaskWords = Data.getU32(Cur);
   Header.Shift2 = Data.getU32(Cur);
 
   // Set just the raw binary content if we were unable to read the header
@@ -1308,9 +1300,6 @@ ELFDumper<ELFT>::dumpGnuHashSection(const Elf_Shdr *Shdr) {
 template <class ELFT>
 Expected<ELFYAML::VerdefSection *>
 ELFDumper<ELFT>::dumpVerdefSection(const Elf_Shdr *Shdr) {
-  typedef typename ELFT::Verdef Elf_Verdef;
-  typedef typename ELFT::Verdaux Elf_Verdaux;
-
   auto S = std::make_unique<ELFYAML::VerdefSection>();
   if (Error E = dumpCommonSection(Shdr, *S))
     return std::move(E);
@@ -1360,8 +1349,6 @@ ELFDumper<ELFT>::dumpVerdefSection(const Elf_Shdr *Shdr) {
 template <class ELFT>
 Expected<ELFYAML::SymverSection *>
 ELFDumper<ELFT>::dumpSymverSection(const Elf_Shdr *Shdr) {
-  typedef typename ELFT::Half Elf_Half;
-
   auto S = std::make_unique<ELFYAML::SymverSection>();
   if (Error E = dumpCommonSection(Shdr, *S))
     return std::move(E);
@@ -1380,9 +1367,6 @@ ELFDumper<ELFT>::dumpSymverSection(const Elf_Shdr *Shdr) {
 template <class ELFT>
 Expected<ELFYAML::VerneedSection *>
 ELFDumper<ELFT>::dumpVerneedSection(const Elf_Shdr *Shdr) {
-  typedef typename ELFT::Verneed Elf_Verneed;
-  typedef typename ELFT::Vernaux Elf_Vernaux;
-
   auto S = std::make_unique<ELFYAML::VerneedSection>();
   if (Error E = dumpCommonSection(Shdr, *S))
     return std::move(E);
diff --git a/llvm/tools/sycl-post-link/SPIRKernelParamOptInfo.cpp b/llvm/tools/sycl-post-link/SPIRKernelParamOptInfo.cpp
index bb404c6211239..9532ee0e0f836 100644
--- a/llvm/tools/sycl-post-link/SPIRKernelParamOptInfo.cpp
+++ b/llvm/tools/sycl-post-link/SPIRKernelParamOptInfo.cpp
@@ -36,10 +36,10 @@ SPIRKernelParamOptInfoAnalysis::run(Module &M, ModuleAnalysisManager &AM) {
     assert(Ins.second && "duplicate kernel?");
     BitVector &ParamDropped = Ins.first->second;
 
-    for (unsigned int I = 0; I < MD->getNumOperands(); ++I) {
-      const auto *MDInt1 = cast<ConstantAsMetadata>(MD->getOperand(I));
+    for (const MDOperand &MDOp : MD->operands()) {
+      const auto *MDConst = cast<ConstantAsMetadata>(MDOp);
       unsigned ID = static_cast<unsigned>(
-          cast<ConstantInt>(MDInt1->getValue())->getValue().getZExtValue());
+          cast<ConstantInt>(MDConst->getValue())->getValue().getZExtValue());
       ParamDropped.push_back(ID != 0);
     }
   }
diff --git a/llvm/tools/sycl-post-link/sycl-post-link.cpp b/llvm/tools/sycl-post-link/sycl-post-link.cpp
index d253c836a2033..9ee3c604794f3 100644
--- a/llvm/tools/sycl-post-link/sycl-post-link.cpp
+++ b/llvm/tools/sycl-post-link/sycl-post-link.cpp
@@ -602,7 +602,7 @@ static string_vector saveResultSymbolsLists(string_vector &ResSymbolsLists) {
     writeToFile(CurOutFileName, ResSymbolsLists[I]);
     Res.emplace_back(std::move(CurOutFileName));
   }
-  return std::move(Res);
+  return Res;
 }
 
 #define CHECK_AND_EXIT(E)                                                      \
@@ -614,6 +614,91 @@ static string_vector saveResultSymbolsLists(string_vector &ResSymbolsLists) {
     }                                                                          \
   }
 
+static int processOneModule(std::unique_ptr<Module> M,
+                            util::SimpleTable &Table) {
+  std::map<StringRef, std::vector<Function *>> GlobalsSet;
+
+  bool DoSplit = SplitMode.getNumOccurrences() > 0;
+  bool DoSpecConst = SpecConstLower.getNumOccurrences() > 0;
+
+  if (DoSplit || DoSymGen) {
+    KernelMapEntryScope Scope = Scope_Global;
+    if (DoSplit) {
+      if (SplitMode == SPLIT_AUTO)
+        Scope = selectDeviceCodeSplitScopeAutomatically(*M);
+      else
+        Scope =
+            SplitMode == SPLIT_PER_KERNEL ? Scope_PerKernel : Scope_PerModule;
+    }
+    collectKernelModuleMap(*M, GlobalsSet, Scope);
+  }
+
+  std::vector<std::unique_ptr<Module>> ResultModules;
+  string_vector ResultSymbolsLists;
+
+  bool SpecConstsMet = false;
+  bool SetSpecConstAtRT = DoSpecConst && (SpecConstLower == SC_USE_RT_VAL);
+
+  if (DoSpecConst) {
+    // perform the spec constant intrinsics transformation and enumeration on
+    // the whole module
+    ModulePassManager RunSpecConst;
+    ModuleAnalysisManager MAM;
+    SpecConstantsPass SCP(SetSpecConstAtRT);
+    // Register required analysis
+    MAM.registerPass([&] { return PassInstrumentationAnalysis(); });
+    RunSpecConst.addPass(SCP);
+    if (!DoSplit)
+      // This pass deletes unreachable globals. Code splitter runs it later.
+      RunSpecConst.addPass(GlobalDCEPass());
+    PreservedAnalyses Res = RunSpecConst.run(*M, MAM);
+    SpecConstsMet = !Res.areAllPreserved();
+  }
+  if (IROutputOnly) {
+    // the result is the transformed input LLVMIR file rather than a file table
+    saveModule(*M, OutputFilename);
+    return 0;
+  }
+  if (DoSplit) {
+    splitModule(*M, GlobalsSet, ResultModules);
+    // post-link always produces a code result, even if it is unmodified input
+    if (ResultModules.size() == 0)
+      ResultModules.push_back(std::move(M));
+  } else
+    ResultModules.push_back(std::move(M));
+
+  {
+    // reuse input module if there were no spec constants and no splitting
+    string_vector Files = SpecConstsMet || (ResultModules.size() > 1)
+                              ? saveResultModules(ResultModules)
+                              : string_vector{InputFilename};
+    // "Code" column is always output
+    Error Err = Table.addColumn(COL_CODE, Files);
+    CHECK_AND_EXIT(Err);
+  }
+
+  {
+    ImagePropSaveInfo ImgPSInfo = {true, DoSpecConst, SetSpecConstAtRT,
+                                   SpecConstsMet, EmitKernelParamInfo};
+    string_vector Files = saveDeviceImageProperty(ResultModules, ImgPSInfo);
+    Error Err = Table.addColumn(COL_PROPS, Files);
+    CHECK_AND_EXIT(Err);
+  }
+  if (DoSymGen) {
+    // extract symbols per each module
+    collectSymbolsLists(GlobalsSet, ResultSymbolsLists);
+    if (ResultSymbolsLists.empty()) {
+      // push empty symbols list for consistency
+      assert(ResultModules.size() == 1);
+      ResultSymbolsLists.push_back("");
+    }
+    string_vector Files = saveResultSymbolsLists(ResultSymbolsLists);
+    Error Err = Table.addColumn(COL_SYM, Files);
+    CHECK_AND_EXIT(Err);
+  }
+  return 0;
+}
+
 int main(int argc, char **argv) {
   InitLLVM X{argc, argv};
 
@@ -689,9 +774,13 @@ int main(int argc, char **argv) {
     return 1;
   }
 
-  // Special "llvm.used" variable which holds references to global values in the
-  // module is known to cause problems for tools which run later in pipeline, so
-  // remove it from the module before perfroming any other actions.
+  // After linking device bitcode "llvm.used" holds references to the kernels
+  // that are defined in the device image. But after splitting device image into
+  // separate kernels we may end up with having references to kernel declaration
+  // originating from "llvm.used" in the IR that is passed to llvm-spirv tool,
+  // and these declarations cause an assertion in llvm-spirv. To workaround this
+  // issue remove "llvm.used" from the input module before performing any other
+  // actions.
   if (GlobalVariable *GV = MPtr->getGlobalVariable("llvm.used")) {
     assert(GV->user_empty() && "unexpected llvm.used users");
     GV->eraseFromParent();
@@ -700,84 +789,14 @@ int main(int argc, char **argv) {
   if (OutputFilename.getNumOccurrences() == 0)
     OutputFilename = (Twine(sys::path::stem(InputFilename)) + ".files").str();
 
-  std::map<StringRef, std::vector<Function *>> GlobalsSet;
-
-  if (DoSplit || DoSymGen) {
-    KernelMapEntryScope Scope = Scope_Global;
-    if (DoSplit) {
-      if (SplitMode == SPLIT_AUTO)
-        Scope = selectDeviceCodeSplitScopeAutomatically(*MPtr);
-      else
-        Scope =
-            SplitMode == SPLIT_PER_KERNEL ? Scope_PerKernel : Scope_PerModule;
-    }
-    collectKernelModuleMap(*MPtr, GlobalsSet, Scope);
-  }
-
-  std::vector<std::unique_ptr<Module>> ResultModules;
-  string_vector ResultSymbolsLists;
-
   util::SimpleTable Table;
-  bool SpecConstsMet = false;
-  bool SetSpecConstAtRT = DoSpecConst && (SpecConstLower == SC_USE_RT_VAL);
+  int Res = processOneModule(std::move(M), Table);
+  if (Res)
+    return Res;
 
-  if (DoSpecConst) {
-    // perform the spec constant intrinsics transformation and enumeration on
-    // the whole module
-    ModulePassManager RunSpecConst;
-    ModuleAnalysisManager MAM;
-    SpecConstantsPass SCP(SetSpecConstAtRT);
-    // Register required analysis
-    MAM.registerPass([&] { return PassInstrumentationAnalysis(); });
-    RunSpecConst.addPass(SCP);
-    if (!DoSplit)
-      // This pass deletes unreachable globals. Code splitter runs it later.
-      RunSpecConst.addPass(GlobalDCEPass());
-    PreservedAnalyses Res = RunSpecConst.run(*MPtr, MAM);
-    SpecConstsMet = !Res.areAllPreserved();
-  }
-  if (IROutputOnly) {
-    // the result is the transformed input LLVMIR file rather than a file table
-    saveModule(*MPtr, OutputFilename);
+  if (IROutputOnly)
     return 0;
-  }
-  if (DoSplit) {
-    splitModule(*MPtr, GlobalsSet, ResultModules);
-    // post-link always produces a code result, even if it is unmodified input
-    if (ResultModules.size() == 0)
-      ResultModules.push_back(std::move(M));
-  } else
-    ResultModules.push_back(std::move(M));
 
-  {
-    // reuse input module if there were no spec constants and no splitting
-    string_vector Files = SpecConstsMet || (ResultModules.size() > 1)
-                              ? saveResultModules(ResultModules)
-                              : string_vector{InputFilename};
-    // "Code" column is always output
-    Error Err = Table.addColumn(COL_CODE, Files);
-    CHECK_AND_EXIT(Err);
-  }
-
-  {
-    ImagePropSaveInfo ImgPSInfo = {true, DoSpecConst, SetSpecConstAtRT,
-                                   SpecConstsMet, EmitKernelParamInfo};
-    string_vector Files = saveDeviceImageProperty(ResultModules, ImgPSInfo);
-    Error Err = Table.addColumn(COL_PROPS, Files);
-    CHECK_AND_EXIT(Err);
-  }
-  if (DoSymGen) {
-    // extract symbols per each module
-    collectSymbolsLists(GlobalsSet, ResultSymbolsLists);
-    if (ResultSymbolsLists.empty()) {
-      // push empty symbols list for consistency
-      assert(ResultModules.size() == 1);
-      ResultSymbolsLists.push_back("");
-    }
-    string_vector Files = saveResultSymbolsLists(ResultSymbolsLists);
-    Error Err = Table.addColumn(COL_SYM, Files);
-    CHECK_AND_EXIT(Err);
-  }
   {
     std::error_code EC;
     raw_fd_ostream Out{OutputFilename, EC, sys::fs::OF_None};
diff --git a/llvm/unittests/ADT/SmallVectorTest.cpp b/llvm/unittests/ADT/SmallVectorTest.cpp
index 957412f3083f3..d97ab577524f4 100644
--- a/llvm/unittests/ADT/SmallVectorTest.cpp
+++ b/llvm/unittests/ADT/SmallVectorTest.cpp
@@ -341,6 +341,31 @@ TYPED_TEST(SmallVectorTest, ResizeFillTest) {
   this->assertValuesInOrder(this->theVector, 3u, 77, 77, 77);
 }
 
+TEST(SmallVectorTest, ResizeForOverwrite) {
+  {
+    // Heap allocated storage.
+    SmallVector<unsigned, 0> V;
+    V.push_back(5U);
+    V.pop_back();
+    V.resize_for_overwrite(V.size() + 1U);
+    EXPECT_EQ(5U, V.back());
+    V.pop_back();
+    V.resize(V.size() + 1);
+    EXPECT_EQ(0U, V.back());
+  }
+  {
+    // Inline storage.
+    SmallVector<unsigned, 2> V;
+    V.push_back(5U);
+    V.pop_back();
+    V.resize_for_overwrite(V.size() + 1U);
+    EXPECT_EQ(5U, V.back());
+    V.pop_back();
+    V.resize(V.size() + 1);
+    EXPECT_EQ(0U, V.back());
+  }
+}
+
 // Overflow past fixed size.
 TYPED_TEST(SmallVectorTest, OverflowTest) {
   SCOPED_TRACE("OverflowTest");
diff --git a/llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp b/llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
index 60459c2001749..a28847b47126d 100644
--- a/llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
+++ b/llvm/unittests/Analysis/IRSimilarityIdentifierTest.cpp
@@ -154,8 +154,9 @@ TEST(IRInstructionMapper, PredicateDifferentiation) {
   ASSERT_TRUE(UnsignedVec[0] != UnsignedVec[1]);
 }
 
-// Checks that predicates with the same swapped predicate map to different
-// values.
+// Checks that predicates where that can be considered the same when the
+// operands are swapped, i.e. greater than to less than are mapped to the same
+// unsigned integer.
 TEST(IRInstructionMapper, PredicateIsomorphism) {
   StringRef ModuleString = R"(
                           define i32 @f(i32 %a, i32 %b) {
@@ -177,7 +178,7 @@ TEST(IRInstructionMapper, PredicateIsomorphism) {
 
   ASSERT_TRUE(InstrList.size() == UnsignedVec.size());
   ASSERT_TRUE(UnsignedVec.size() == 3);
-  ASSERT_TRUE(UnsignedVec[0] != UnsignedVec[1]);
+  ASSERT_TRUE(UnsignedVec[0] == UnsignedVec[1]);
 }
 
 // Checks that the same predicate maps to the same value.
@@ -1375,6 +1376,51 @@ TEST(IRSimilarityCandidate, CheckIdenticalInstructions) {
   ASSERT_TRUE(IRSimilarityCandidate::isSimilar(Cand1, Cand2));
 }
 
+// Checks that comparison instructions are found to be similar instructions
+// when the operands are flipped and the predicate is also swapped.
+TEST(IRSimilarityCandidate, PredicateIsomorphism) {
+  StringRef ModuleString = R"(
+                          define i32 @f(i32 %a, i32 %b) {
+                          bb0:
+                             %0 = icmp sgt i32 %a, %b
+                             %1 = add i32 %b, %a
+                             br label %bb1
+                          bb1:
+                             %2 = icmp slt i32 %a, %b
+                             %3 = add i32 %a, %b
+                             ret i32 0
+                          })";
+  LLVMContext Context;
+  std::unique_ptr<Module> M = makeLLVMModule(Context, ModuleString);
+
+  std::vector<IRInstructionData *> InstrList;
+  std::vector<unsigned> UnsignedVec;
+
+  SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
+  SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
+  IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
+  getVectors(*M, Mapper, InstrList, UnsignedVec);
+
+  ASSERT_TRUE(InstrList.size() > 5);
+  ASSERT_TRUE(InstrList.size() == UnsignedVec.size());
+
+  std::vector<IRInstructionData *>::iterator Start, End;
+  Start = InstrList.begin();
+  End = InstrList.begin();
+  
+  std::advance(End, 1);
+  IRSimilarityCandidate Cand1(0, 2, *Start, *End);
+
+  Start = InstrList.begin();
+  End = InstrList.begin();
+  
+  std::advance(Start, 3);
+  std::advance(End, 4);
+  IRSimilarityCandidate Cand2(3, 2, *Start, *End);
+
+  ASSERT_TRUE(IRSimilarityCandidate::isSimilar(Cand1, Cand2));
+}
+
 // Checks that IRSimilarityCandidates wrapping these two regions of instructions
 // are able to differentiate between instructions that have different opcodes.
 TEST(IRSimilarityCandidate, CheckRegionsDifferentInstruction) {
@@ -1567,6 +1613,67 @@ TEST(IRSimilarityCandidate, DifferentStructure) {
   ASSERT_FALSE(longSimCandCompare(InstrList, true));
 }
 
+// Checks that comparison instructions are found to have the same structure
+// when the operands are flipped and the predicate is also swapped.
+TEST(IRSimilarityCandidate, PredicateIsomorphismStructure) {
+  StringRef ModuleString = R"(
+                          define i32 @f(i32 %a, i32 %b) {
+                          bb0:
+                             %0 = icmp sgt i32 %a, %b
+                             %1 = add i32 %a, %b
+                             br label %bb1
+                          bb1:
+                             %2 = icmp slt i32 %b, %a
+                             %3 = add i32 %a, %b
+                             ret i32 0
+                          })";
+  LLVMContext Context;
+  std::unique_ptr<Module> M = makeLLVMModule(Context, ModuleString);
+
+  std::vector<IRInstructionData *> InstrList;
+  std::vector<unsigned> UnsignedVec;
+
+  SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
+  SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
+  IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
+  getVectors(*M, Mapper, InstrList, UnsignedVec);
+
+  ASSERT_TRUE(InstrList.size() > 5);
+  ASSERT_TRUE(InstrList.size() == UnsignedVec.size());
+
+  ASSERT_TRUE(longSimCandCompare(InstrList, true));
+}
+
+// Checks that different predicates are counted as diferent.
+TEST(IRSimilarityCandidate, PredicateDifference) {
+  StringRef ModuleString = R"(
+                          define i32 @f(i32 %a, i32 %b) {
+                          bb0:
+                             %0 = icmp sge i32 %a, %b
+                             %1 = add i32 %b, %a
+                             br label %bb1
+                          bb1:
+                             %2 = icmp slt i32 %b, %a
+                             %3 = add i32 %a, %b
+                             ret i32 0
+                          })";
+  LLVMContext Context;
+  std::unique_ptr<Module> M = makeLLVMModule(Context, ModuleString);
+
+  std::vector<IRInstructionData *> InstrList;
+  std::vector<unsigned> UnsignedVec;
+
+  SpecificBumpPtrAllocator<IRInstructionData> InstDataAllocator;
+  SpecificBumpPtrAllocator<IRInstructionDataList> IDLAllocator;
+  IRInstructionMapper Mapper(&InstDataAllocator, &IDLAllocator);
+  getVectors(*M, Mapper, InstrList, UnsignedVec);
+
+  ASSERT_TRUE(InstrList.size() > 5);
+  ASSERT_TRUE(InstrList.size() == UnsignedVec.size());
+
+  ASSERT_FALSE(longSimCandCompare(InstrList));
+}
+
 // Checks that the same structure is recognized between two candidates. The
 // items %a and %b are used in the same way in both sets of instructions.
 TEST(IRSimilarityCandidate, SameStructure) {
@@ -1688,8 +1795,8 @@ TEST(IRSimilarityIdentifier, InstructionDifference) {
   ASSERT_TRUE(SimilarityCandidates.empty());
 }
 
-// This test checks to see whether we can detect similarity for commutativen
-// instructions where the operands have been reversed.  Right now, we cannot.
+// This test checks to see whether we can detect similarity for commutative
+// instructions where the operands have been reversed.
 TEST(IRSimilarityIdentifier, CommutativeSimilarity) {
   StringRef ModuleString = R"(
                           define i32 @f(i32 %a, i32 %b) {
@@ -1708,13 +1815,45 @@ TEST(IRSimilarityIdentifier, CommutativeSimilarity) {
   std::vector<std::vector<IRSimilarityCandidate>> SimilarityCandidates;
   getSimilarities(*M, SimilarityCandidates);
 
-  ASSERT_TRUE(SimilarityCandidates.empty());
+  ASSERT_TRUE(SimilarityCandidates.size() == 1);
+  for (std::vector<IRSimilarityCandidate> &Cands : SimilarityCandidates) {
+    ASSERT_TRUE(Cands.size() == 2);
+    unsigned InstIdx = 0;
+    for (IRSimilarityCandidate &Cand : Cands) {
+      ASSERT_TRUE(Cand.getStartIdx() == InstIdx);
+      InstIdx += 3;
+    }
+  }
 }
 
-// Check that we are not finding commutative similarity in non commutative
+// This test checks to see whether we can detect different structure in
+// commutative instructions.  In this case, the second operand in the second
+// add is different.
+TEST(IRSimilarityIdentifier, NoCommutativeSimilarity) {
+  StringRef ModuleString = R"(
+                          define i32 @f(i32 %a, i32 %b) {
+                          bb0:
+                             %0 = add i32 %a, %b
+                             %1 = add i32 %1, %b
+                             br label %bb1
+                          bb1:
+                             %2 = add i32 %a, %b
+                             %3 = add i32 %2, %a
+                             ret i32 0
+                          })";
+  LLVMContext Context;
+  std::unique_ptr<Module> M = makeLLVMModule(Context, ModuleString);
+
+  std::vector<std::vector<IRSimilarityCandidate>> SimilarityCandidates;
+  getSimilarities(*M, SimilarityCandidates);
+
+  ASSERT_TRUE(SimilarityCandidates.size() == 0);
+}
+
+// Check that we are not finding similarity in non commutative
 // instructions.  That is, while the instruction and operands used are the same
-// in the two subtraction sequences, they cannot be counted as the same since
-// a subtraction is not commutative.
+// in the two subtraction sequences, they are in a different order, and cannot
+// be counted as the same since a subtraction is not commutative.
 TEST(IRSimilarityIdentifier, NonCommutativeDifference) {
   StringRef ModuleString = R"(
                           define i32 @f(i32 %a, i32 %b) {
@@ -1766,6 +1905,39 @@ TEST(IRSimilarityIdentifier, MappingSimilarity) {
   }
 }
 
+// Check that we find instances of swapped predicate isomorphism.  That is,
+// for predicates that can be flipped, e.g. greater than to less than,
+// we can identify that instances of these different literal predicates, but are
+// the same within a single swap can be found.
+TEST(IRSimilarityIdentifier, PredicateIsomorphism) {
+  StringRef ModuleString = R"(
+                          define i32 @f(i32 %a, i32 %b) {
+                          bb0:
+                             %0 = add i32 %a, %b
+                             %1 = icmp sgt i32 %b, %a
+                             br label %bb1
+                          bb1:
+                             %2 = add i32 %a, %b
+                             %3 = icmp slt i32 %a, %b
+                             ret i32 0
+                          })";
+  LLVMContext Context;
+  std::unique_ptr<Module> M = makeLLVMModule(Context, ModuleString);
+
+  std::vector<std::vector<IRSimilarityCandidate>> SimilarityCandidates;
+  getSimilarities(*M, SimilarityCandidates);
+
+  ASSERT_TRUE(SimilarityCandidates.size() == 1);
+  for (std::vector<IRSimilarityCandidate> &Cands : SimilarityCandidates) {
+    ASSERT_TRUE(Cands.size() == 2);
+    unsigned InstIdx = 0;
+    for (IRSimilarityCandidate &Cand : Cands) {
+      ASSERT_TRUE(Cand.getStartIdx() == InstIdx);
+      InstIdx += 3;
+    }
+  }
+}
+
 // Checks that constants are detected as the same operand in each use in the
 // sequences of instructions.  Also checks that we can find structural
 // equivalence using constants.  In this case the 1 has the same use pattern as
diff --git a/llvm/unittests/Analysis/ValueTrackingTest.cpp b/llvm/unittests/Analysis/ValueTrackingTest.cpp
index 721a342040ba4..8d24f524b59df 100644
--- a/llvm/unittests/Analysis/ValueTrackingTest.cpp
+++ b/llvm/unittests/Analysis/ValueTrackingTest.cpp
@@ -67,6 +67,9 @@ class ValueTrackingTest : public testing::Test {
 
     A = findInstructionByNameOrNull(F, "A");
     ASSERT_TRUE(A) << "@test must have an instruction %A";
+    A2 = findInstructionByNameOrNull(F, "A2");
+    A3 = findInstructionByNameOrNull(F, "A3");
+    A4 = findInstructionByNameOrNull(F, "A4");
 
     CxtI = findInstructionByNameOrNull(F, "CxtI");
     CxtI2 = findInstructionByNameOrNull(F, "CxtI2");
@@ -77,6 +80,8 @@ class ValueTrackingTest : public testing::Test {
   std::unique_ptr<Module> M;
   Function *F = nullptr;
   Instruction *A = nullptr;
+  // Instructions (optional)
+  Instruction *A2 = nullptr, *A3 = nullptr, *A4 = nullptr;
 
   // Context instructions (optional)
   Instruction *CxtI = nullptr, *CxtI2 = nullptr, *CxtI3 = nullptr;
@@ -1004,6 +1009,130 @@ TEST_F(ComputeKnownBitsTest, ComputeKnownMulBits) {
   expectKnownBits(/*zero*/ 95u, /*one*/ 32u);
 }
 
+TEST_F(ValueTrackingTest, KnownNonZeroFromDomCond) {
+  parseAssembly(R"(
+    declare i8* @f_i8()
+    define void @test(i1 %c) {
+      %A = call i8* @f_i8()
+      %B = call i8* @f_i8()
+      %c1 = icmp ne i8* %A, null
+      %cond = and i1 %c1, %c
+      br i1 %cond, label %T, label %Q
+    T:
+      %CxtI = add i32 0, 0
+      ret void
+    Q:
+      %CxtI2 = add i32 0, 0
+      ret void
+    }
+  )");
+  AssumptionCache AC(*F);
+  DominatorTree DT(*F);
+  DataLayout DL = M->getDataLayout();
+  EXPECT_EQ(isKnownNonZero(A, DL, 0, &AC, CxtI, &DT), true);
+  EXPECT_EQ(isKnownNonZero(A, DL, 0, &AC, CxtI2, &DT), false);
+}
+
+TEST_F(ValueTrackingTest, KnownNonZeroFromDomCond2) {
+  parseAssembly(R"(
+    declare i8* @f_i8()
+    define void @test(i1 %c) {
+      %A = call i8* @f_i8()
+      %B = call i8* @f_i8()
+      %c1 = icmp ne i8* %A, null
+      %cond = select i1 %c, i1 %c1, i1 false
+      br i1 %cond, label %T, label %Q
+    T:
+      %CxtI = add i32 0, 0
+      ret void
+    Q:
+      %CxtI2 = add i32 0, 0
+      ret void
+    }
+  )");
+  AssumptionCache AC(*F);
+  DominatorTree DT(*F);
+  DataLayout DL = M->getDataLayout();
+  EXPECT_EQ(isKnownNonZero(A, DL, 0, &AC, CxtI, &DT), true);
+  EXPECT_EQ(isKnownNonZero(A, DL, 0, &AC, CxtI2, &DT), false);
+}
+
+TEST_F(ValueTrackingTest, IsImpliedConditionAnd) {
+  parseAssembly(R"(
+    define void @test(i32 %x, i32 %y) {
+      %c1 = icmp ult i32 %x, 10
+      %c2 = icmp ult i32 %y, 15
+      %A = and i1 %c1, %c2
+      ; x < 10 /\ y < 15
+      %A2 = icmp ult i32 %x, 20
+      %A3 = icmp uge i32 %y, 20
+      %A4 = icmp ult i32 %x, 5
+      ret void
+    }
+  )");
+  DataLayout DL = M->getDataLayout();
+  EXPECT_EQ(isImpliedCondition(A, A2, DL), true);
+  EXPECT_EQ(isImpliedCondition(A, A3, DL), false);
+  EXPECT_EQ(isImpliedCondition(A, A4, DL), None);
+}
+
+TEST_F(ValueTrackingTest, IsImpliedConditionAnd2) {
+  parseAssembly(R"(
+    define void @test(i32 %x, i32 %y) {
+      %c1 = icmp ult i32 %x, 10
+      %c2 = icmp ult i32 %y, 15
+      %A = select i1 %c1, i1 %c2, i1 false
+      ; x < 10 /\ y < 15
+      %A2 = icmp ult i32 %x, 20
+      %A3 = icmp uge i32 %y, 20
+      %A4 = icmp ult i32 %x, 5
+      ret void
+    }
+  )");
+  DataLayout DL = M->getDataLayout();
+  EXPECT_EQ(isImpliedCondition(A, A2, DL), true);
+  EXPECT_EQ(isImpliedCondition(A, A3, DL), false);
+  EXPECT_EQ(isImpliedCondition(A, A4, DL), None);
+}
+
+TEST_F(ValueTrackingTest, IsImpliedConditionOr) {
+  parseAssembly(R"(
+    define void @test(i32 %x, i32 %y) {
+      %c1 = icmp ult i32 %x, 10
+      %c2 = icmp ult i32 %y, 15
+      %A = or i1 %c1, %c2 ; negated
+      ; x >= 10 /\ y >= 15
+      %A2 = icmp ult i32 %x, 5
+      %A3 = icmp uge i32 %y, 10
+      %A4 = icmp ult i32 %x, 15
+      ret void
+    }
+  )");
+  DataLayout DL = M->getDataLayout();
+  EXPECT_EQ(isImpliedCondition(A, A2, DL, false), false);
+  EXPECT_EQ(isImpliedCondition(A, A3, DL, false), true);
+  EXPECT_EQ(isImpliedCondition(A, A4, DL, false), None);
+}
+
+TEST_F(ValueTrackingTest, IsImpliedConditionOr2) {
+  parseAssembly(R"(
+    define void @test(i32 %x, i32 %y) {
+      %c1 = icmp ult i32 %x, 10
+      %c2 = icmp ult i32 %y, 15
+      %A = select i1 %c1, i1 true, i1 %c2 ; negated
+      ; x >= 10 /\ y >= 15
+      %A2 = icmp ult i32 %x, 5
+      %A3 = icmp uge i32 %y, 10
+      %A4 = icmp ult i32 %x, 15
+      ret void
+    }
+  )");
+  DataLayout DL = M->getDataLayout();
+  EXPECT_EQ(isImpliedCondition(A, A2, DL, false), false);
+  EXPECT_EQ(isImpliedCondition(A, A3, DL, false), true);
+  EXPECT_EQ(isImpliedCondition(A, A4, DL, false), None);
+}
+
 TEST_F(ComputeKnownBitsTest, KnownNonZeroShift) {
   // %q is known nonzero without known bits.
   // Because %q is nonzero, %A[0] is known to be zero.
diff --git a/llvm/unittests/Support/KnownBitsTest.cpp b/llvm/unittests/Support/KnownBitsTest.cpp
index c5eb96efc85ee..528a645ec51ad 100644
--- a/llvm/unittests/Support/KnownBitsTest.cpp
+++ b/llvm/unittests/Support/KnownBitsTest.cpp
@@ -295,6 +295,20 @@ TEST(KnownBitsTest, GetMinMaxVal) {
   });
 }
 
+TEST(KnownBitsTest, GetSignedMinMaxVal) {
+  unsigned Bits = 4;
+  ForeachKnownBits(Bits, [&](const KnownBits &Known) {
+    APInt Min = APInt::getSignedMaxValue(Bits);
+    APInt Max = APInt::getSignedMinValue(Bits);
+    ForeachNumInKnownBits(Known, [&](const APInt &N) {
+      Min = APIntOps::smin(Min, N);
+      Max = APIntOps::smax(Max, N);
+    });
+    EXPECT_EQ(Min, Known.getSignedMinValue());
+    EXPECT_EQ(Max, Known.getSignedMaxValue());
+  });
+}
+
 TEST(KnownBitsTest, SExtOrTrunc) {
   const unsigned NarrowerSize = 4;
   const unsigned BaseSize = 6;
diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp
index 8407397e4ed87..bc2fd6243aa5f 100644
--- a/llvm/unittests/Support/TargetParserTest.cpp
+++ b/llvm/unittests/Support/TargetParserTest.cpp
@@ -8,7 +8,9 @@
 
 #include "llvm/Support/TargetParser.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/ARMBuildAttributes.h"
+#include "llvm/Support/FormatVariadic.h"
 #include "gtest/gtest.h"
 #include <string>
 
@@ -31,308 +33,357 @@ const char *ARMArch[] = {
     "armv8m.main", "iwmmxt",       "iwmmxt2",     "xscale",       "armv8.1-m.main",
 };
 
-bool testARMCPU(StringRef CPUName, StringRef ExpectedArch,
-                StringRef ExpectedFPU, uint64_t ExpectedFlags,
-                StringRef CPUAttr) {
-  ARM::ArchKind AK = ARM::parseCPUArch(CPUName);
-  bool pass = ARM::getArchName(AK).equals(ExpectedArch);
-  unsigned FPUKind = ARM::getDefaultFPU(CPUName, AK);
-  pass &= ARM::getFPUName(FPUKind).equals(ExpectedFPU);
-
-  uint64_t ExtKind = ARM::getDefaultExtensions(CPUName, AK);
-  if (ExtKind > 1 && (ExtKind & ARM::AEK_NONE))
-    pass &= ((ExtKind ^ ARM::AEK_NONE) == ExpectedFlags);
-  else
-    pass &= (ExtKind == ExpectedFlags);
-  pass &= ARM::getCPUAttr(AK).equals(CPUAttr);
-
-  return pass;
+template <ARM::ISAKind ISAKind>
+std::string FormatExtensionFlags(uint64_t Flags) {
+  std::vector<StringRef> Features;
+
+  if (ISAKind == ARM::ISAKind::AARCH64) {
+    // AEK_NONE is not meant to be shown to the user so the target parser
+    // does not recognise it. It is relevant here though.
+    if (Flags & AArch64::AEK_NONE)
+      Features.push_back("none");
+    AArch64::getExtensionFeatures(Flags, Features);
+  } else {
+    if (Flags & ARM::AEK_NONE)
+      Features.push_back("none");
+    ARM::getExtensionFeatures(Flags, Features);
+  }
+
+  // The target parser also includes every extension you don't have.
+  // E.g. if AEK_CRC is not set then it adds "-crc". Not useful here.
+  Features.erase(std::remove_if(Features.begin(), Features.end(),
+                                [](StringRef extension) {
+                                  return extension.startswith("-");
+                                }),
+                 Features.end());
+
+  return llvm::join(Features, ", ");
+}
+
+template <ARM::ISAKind ISAKind>
+testing::AssertionResult
+AssertSameExtensionFlags(const char *m_expr, const char *n_expr,
+                         uint64_t ExpectedFlags, uint64_t GotFlags) {
+  if (ExpectedFlags == GotFlags)
+    return testing::AssertionSuccess();
+
+  return testing::AssertionFailure() << llvm::formatv(
+             "Expected extension flags: {0} ({1:x})\n"
+             "     Got extension flags: {2} ({3:x})\n",
+             FormatExtensionFlags<ISAKind>(ExpectedFlags), ExpectedFlags,
+             FormatExtensionFlags<ISAKind>(GotFlags), GotFlags);
+}
+
+struct ARMCPUTestParams {
+  ARMCPUTestParams(StringRef CPUName, StringRef ExpectedArch,
+                   StringRef ExpectedFPU, uint64_t ExpectedFlags,
+                   StringRef CPUAttr)
+      : CPUName(CPUName), ExpectedArch(ExpectedArch), ExpectedFPU(ExpectedFPU),
+        ExpectedFlags(ExpectedFlags), CPUAttr(CPUAttr) {}
+
+  friend std::ostream &operator<<(std::ostream &os,
+                                  const ARMCPUTestParams &params) {
+    return os << "\"" << params.CPUName.str() << "\", \""
+              << params.ExpectedArch.str() << "\", \""
+              << params.ExpectedFPU.str() << "\", 0x" << std::hex
+              << params.ExpectedFlags << ", \"" << params.CPUAttr.str() << "\"";
+  }
+
+  StringRef CPUName;
+  StringRef ExpectedArch;
+  StringRef ExpectedFPU;
+  uint64_t ExpectedFlags;
+  StringRef CPUAttr;
+};
+
+class ARMCPUTestFixture : public ::testing::TestWithParam<ARMCPUTestParams> {};
+
+TEST_P(ARMCPUTestFixture, ARMCPUTests) {
+  auto params = GetParam();
+
+  ARM::ArchKind AK = ARM::parseCPUArch(params.CPUName);
+  EXPECT_EQ(params.ExpectedArch, ARM::getArchName(AK));
+
+  unsigned FPUKind = ARM::getDefaultFPU(params.CPUName, AK);
+  EXPECT_EQ(params.ExpectedFPU, ARM::getFPUName(FPUKind));
+
+  uint64_t default_extensions = ARM::getDefaultExtensions(params.CPUName, AK);
+  EXPECT_PRED_FORMAT2(AssertSameExtensionFlags<ARM::ISAKind::ARM>,
+                      params.ExpectedFlags, default_extensions);
+
+  EXPECT_EQ(params.CPUAttr, ARM::getCPUAttr(AK));
 }
 
-TEST(TargetParserTest, testARMCPU) {
-  EXPECT_TRUE(testARMCPU("invalid", "invalid", "invalid",
-                         ARM::AEK_NONE, ""));
-  EXPECT_TRUE(testARMCPU("generic", "invalid", "none",
-                         ARM::AEK_NONE, ""));
-
-  EXPECT_TRUE(testARMCPU("arm2", "armv2", "none",
-                         ARM::AEK_NONE, "2"));
-  EXPECT_TRUE(testARMCPU("arm3", "armv2a", "none",
-                         ARM::AEK_NONE, "2A"));
-  EXPECT_TRUE(testARMCPU("arm6", "armv3", "none",
-                         ARM::AEK_NONE, "3"));
-  EXPECT_TRUE(testARMCPU("arm7m", "armv3m", "none",
-                         ARM::AEK_NONE, "3M"));
-  EXPECT_TRUE(testARMCPU("arm8", "armv4", "none",
-                         ARM::AEK_NONE, "4"));
-  EXPECT_TRUE(testARMCPU("arm810", "armv4", "none",
-                         ARM::AEK_NONE, "4"));
-  EXPECT_TRUE(testARMCPU("strongarm", "armv4", "none",
-                         ARM::AEK_NONE, "4"));
-  EXPECT_TRUE(testARMCPU("strongarm110", "armv4", "none",
-                         ARM::AEK_NONE, "4"));
-  EXPECT_TRUE(testARMCPU("strongarm1100", "armv4", "none",
-                         ARM::AEK_NONE, "4"));
-  EXPECT_TRUE(testARMCPU("strongarm1110", "armv4", "none",
-                         ARM::AEK_NONE, "4"));
-  EXPECT_TRUE(testARMCPU("arm7tdmi", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm7tdmi-s", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm710t", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm720t", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm9", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm9tdmi", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm920", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm920t", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm922t", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm9312", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm940t", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("ep9312", "armv4t", "none",
-                         ARM::AEK_NONE, "4T"));
-  EXPECT_TRUE(testARMCPU("arm10tdmi", "armv5t", "none",
-                         ARM::AEK_NONE, "5T"));
-  EXPECT_TRUE(testARMCPU("arm1020t", "armv5t", "none",
-                         ARM::AEK_NONE, "5T"));
-  EXPECT_TRUE(testARMCPU("arm9e", "armv5te", "none",
-                         ARM::AEK_DSP, "5TE"));
-  EXPECT_TRUE(testARMCPU("arm946e-s", "armv5te", "none",
-                         ARM::AEK_DSP, "5TE"));
-  EXPECT_TRUE(testARMCPU("arm966e-s", "armv5te", "none",
-                         ARM::AEK_DSP, "5TE"));
-  EXPECT_TRUE(testARMCPU("arm968e-s", "armv5te", "none",
-                         ARM::AEK_DSP, "5TE"));
-  EXPECT_TRUE(testARMCPU("arm10e", "armv5te", "none",
-                         ARM::AEK_DSP, "5TE"));
-  EXPECT_TRUE(testARMCPU("arm1020e", "armv5te", "none",
-                         ARM::AEK_DSP, "5TE"));
-  EXPECT_TRUE(testARMCPU("arm1022e", "armv5te", "none",
-                         ARM::AEK_DSP, "5TE"));
-  EXPECT_TRUE(testARMCPU("arm926ej-s", "armv5tej", "none",
-                         ARM::AEK_DSP, "5TEJ"));
-  EXPECT_TRUE(testARMCPU("arm1136j-s", "armv6", "none",
-                         ARM::AEK_DSP, "6"));
-  EXPECT_TRUE(testARMCPU("arm1136jf-s", "armv6", "vfpv2",
-                         ARM::AEK_DSP, "6"));
-  EXPECT_TRUE(testARMCPU("arm1136jz-s", "armv6", "none",
-                         ARM::AEK_DSP, "6"));
-  EXPECT_TRUE(testARMCPU("arm1176jz-s", "armv6kz", "none",
-                         ARM::AEK_SEC | ARM::AEK_DSP, "6KZ"));
-  EXPECT_TRUE(testARMCPU("mpcore", "armv6k", "vfpv2",
-                         ARM::AEK_DSP, "6K"));
-  EXPECT_TRUE(testARMCPU("mpcorenovfp", "armv6k", "none",
-                         ARM::AEK_DSP, "6K"));
-  EXPECT_TRUE(testARMCPU("arm1176jzf-s", "armv6kz", "vfpv2",
-                         ARM::AEK_SEC | ARM::AEK_DSP, "6KZ"));
-  EXPECT_TRUE(testARMCPU("arm1156t2-s", "armv6t2", "none",
-                         ARM::AEK_DSP, "6T2"));
-  EXPECT_TRUE(testARMCPU("arm1156t2f-s", "armv6t2", "vfpv2",
-                         ARM::AEK_DSP, "6T2"));
-  EXPECT_TRUE(testARMCPU("cortex-m0", "armv6-m", "none",
-                         ARM::AEK_NONE, "6-M"));
-  EXPECT_TRUE(testARMCPU("cortex-m0plus", "armv6-m", "none",
-                         ARM::AEK_NONE, "6-M"));
-  EXPECT_TRUE(testARMCPU("cortex-m1", "armv6-m", "none",
-                         ARM::AEK_NONE, "6-M"));
-  EXPECT_TRUE(testARMCPU("sc000", "armv6-m", "none",
-                         ARM::AEK_NONE, "6-M"));
-  EXPECT_TRUE(testARMCPU("cortex-a5", "armv7-a", "neon-vfpv4",
-                         ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a7", "armv7-a", "neon-vfpv4",
+// Note that we include ARM::AEK_NONE even when there are other extensions
+// we expect. This is because the default extensions for a CPU are the sum
+// of the default extensions for its architecture and for the CPU.
+// So if a CPU has no extra extensions, it adds AEK_NONE.
+INSTANTIATE_TEST_CASE_P(
+    ARMCPUTestsPart1, ARMCPUTestFixture,
+    ::testing::Values(
+        ARMCPUTestParams("invalid", "invalid", "invalid", ARM::AEK_NONE, ""),
+        ARMCPUTestParams("generic", "invalid", "none", ARM::AEK_NONE, ""),
+
+        ARMCPUTestParams("arm2", "armv2", "none", ARM::AEK_NONE, "2"),
+        ARMCPUTestParams("arm3", "armv2a", "none", ARM::AEK_NONE, "2A"),
+        ARMCPUTestParams("arm6", "armv3", "none", ARM::AEK_NONE, "3"),
+        ARMCPUTestParams("arm7m", "armv3m", "none", ARM::AEK_NONE, "3M"),
+        ARMCPUTestParams("arm8", "armv4", "none", ARM::AEK_NONE, "4"),
+        ARMCPUTestParams("arm810", "armv4", "none", ARM::AEK_NONE, "4"),
+        ARMCPUTestParams("strongarm", "armv4", "none", ARM::AEK_NONE, "4"),
+        ARMCPUTestParams("strongarm110", "armv4", "none", ARM::AEK_NONE, "4"),
+        ARMCPUTestParams("strongarm1100", "armv4", "none", ARM::AEK_NONE, "4"),
+        ARMCPUTestParams("strongarm1110", "armv4", "none", ARM::AEK_NONE, "4"),
+        ARMCPUTestParams("arm7tdmi", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm7tdmi-s", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm710t", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm720t", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm9", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm9tdmi", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm920", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm920t", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm922t", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm9312", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm940t", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("ep9312", "armv4t", "none", ARM::AEK_NONE, "4T"),
+        ARMCPUTestParams("arm10tdmi", "armv5t", "none", ARM::AEK_NONE, "5T"),
+        ARMCPUTestParams("arm1020t", "armv5t", "none", ARM::AEK_NONE, "5T"),
+        ARMCPUTestParams("arm9e", "armv5te", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "5TE"),
+        ARMCPUTestParams("arm946e-s", "armv5te", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "5TE"),
+        ARMCPUTestParams("arm966e-s", "armv5te", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "5TE"),
+        ARMCPUTestParams("arm968e-s", "armv5te", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "5TE"),
+        ARMCPUTestParams("arm10e", "armv5te", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "5TE"),
+        ARMCPUTestParams("arm1020e", "armv5te", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "5TE"),
+        ARMCPUTestParams("arm1022e", "armv5te", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "5TE"),
+        ARMCPUTestParams("arm926ej-s", "armv5tej", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "5TEJ"),
+        ARMCPUTestParams("arm1136j-s", "armv6", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "6"),
+        ARMCPUTestParams("arm1136jf-s", "armv6", "vfpv2",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "6"),
+        ARMCPUTestParams("arm1136jz-s", "armv6", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "6"),
+        ARMCPUTestParams("arm1176jz-s", "armv6kz", "none",
+                         ARM::AEK_NONE | ARM::AEK_SEC | ARM::AEK_DSP, "6KZ"),
+        ARMCPUTestParams("mpcore", "armv6k", "vfpv2",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "6K"),
+        ARMCPUTestParams("mpcorenovfp", "armv6k", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "6K"),
+        ARMCPUTestParams("arm1176jzf-s", "armv6kz", "vfpv2",
+                         ARM::AEK_NONE | ARM::AEK_SEC | ARM::AEK_DSP, "6KZ"),
+        ARMCPUTestParams("arm1156t2-s", "armv6t2", "none",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "6T2"),
+        ARMCPUTestParams("arm1156t2f-s", "armv6t2", "vfpv2",
+                         ARM::AEK_NONE | ARM::AEK_DSP, "6T2"),
+        ARMCPUTestParams("cortex-m0", "armv6-m", "none", ARM::AEK_NONE, "6-M"),
+        ARMCPUTestParams("cortex-m0plus", "armv6-m", "none", ARM::AEK_NONE,
+                         "6-M"),
+        ARMCPUTestParams("cortex-m1", "armv6-m", "none", ARM::AEK_NONE, "6-M"),
+        ARMCPUTestParams("sc000", "armv6-m", "none", ARM::AEK_NONE, "6-M"),
+        ARMCPUTestParams("cortex-a5", "armv7-a", "neon-vfpv4",
+                         ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A"),
+        ARMCPUTestParams("cortex-a7", "armv7-a", "neon-vfpv4",
                          ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM | ARM::AEK_MP |
                              ARM::AEK_SEC | ARM::AEK_VIRT | ARM::AEK_DSP,
-                         "7-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a8", "armv7-a", "neon",
-                         ARM::AEK_SEC | ARM::AEK_DSP, "7-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a9", "armv7-a", "neon-fp16",
-                         ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a12", "armv7-a", "neon-vfpv4",
+                         "7-A"),
+        ARMCPUTestParams("cortex-a8", "armv7-a", "neon",
+                         ARM::AEK_SEC | ARM::AEK_DSP, "7-A")), );
+
+// gtest in llvm has a limit of 50 test cases when using ::Values so we split
+// them into 2 blocks
+INSTANTIATE_TEST_CASE_P(
+    ARMCPUTestsPart2, ARMCPUTestFixture,
+    ::testing::Values(
+        ARMCPUTestParams("cortex-a9", "armv7-a", "neon-fp16",
+                         ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_DSP, "7-A"),
+        ARMCPUTestParams("cortex-a12", "armv7-a", "neon-vfpv4",
                          ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
                              ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
                              ARM::AEK_DSP,
-                         "7-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a15", "armv7-a", "neon-vfpv4",
+                         "7-A"),
+        ARMCPUTestParams("cortex-a15", "armv7-a", "neon-vfpv4",
                          ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
                              ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
                              ARM::AEK_DSP,
-                         "7-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a17", "armv7-a", "neon-vfpv4",
+                         "7-A"),
+        ARMCPUTestParams("cortex-a17", "armv7-a", "neon-vfpv4",
                          ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
                              ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
                              ARM::AEK_DSP,
-                         "7-A"));
-  EXPECT_TRUE(testARMCPU("krait", "armv7-a", "neon-vfpv4",
+                         "7-A"),
+        ARMCPUTestParams("krait", "armv7-a", "neon-vfpv4",
                          ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "7-A"));
-  EXPECT_TRUE(testARMCPU("cortex-r4", "armv7-r", "none",
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7-R"));
-  EXPECT_TRUE(testARMCPU("cortex-r4f", "armv7-r", "vfpv3-d16",
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7-R"));
-  EXPECT_TRUE(testARMCPU("cortex-r5", "armv7-r", "vfpv3-d16",
+                         "7-A"),
+        ARMCPUTestParams("cortex-r4", "armv7-r", "none",
+                         ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+                         "7-R"),
+        ARMCPUTestParams("cortex-r4f", "armv7-r", "vfpv3-d16",
+                         ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+                         "7-R"),
+        ARMCPUTestParams("cortex-r5", "armv7-r", "vfpv3-d16",
                          ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
                              ARM::AEK_DSP,
-                         "7-R"));
-  EXPECT_TRUE(testARMCPU("cortex-r7", "armv7-r", "vfpv3-d16-fp16",
+                         "7-R"),
+        ARMCPUTestParams("cortex-r7", "armv7-r", "vfpv3-d16-fp16",
                          ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
                              ARM::AEK_DSP,
-                         "7-R"));
-  EXPECT_TRUE(testARMCPU("cortex-r8", "armv7-r", "vfpv3-d16-fp16",
+                         "7-R"),
+        ARMCPUTestParams("cortex-r8", "armv7-r", "vfpv3-d16-fp16",
                          ARM::AEK_MP | ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
                              ARM::AEK_DSP,
-                         "7-R"));
-  EXPECT_TRUE(testARMCPU("cortex-r52", "armv8-r", "neon-fp-armv8",
-                         ARM::AEK_CRC | ARM::AEK_MP | ARM::AEK_VIRT |
-                             ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
-                             ARM::AEK_DSP,
-                         "8-R"));
-  EXPECT_TRUE(
-      testARMCPU("sc300", "armv7-m", "none", ARM::AEK_HWDIVTHUMB, "7-M"));
-  EXPECT_TRUE(
-      testARMCPU("cortex-m3", "armv7-m", "none", ARM::AEK_HWDIVTHUMB, "7-M"));
-  EXPECT_TRUE(testARMCPU("cortex-m4", "armv7e-m", "fpv4-sp-d16",
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7E-M"));
-  EXPECT_TRUE(testARMCPU("cortex-m7", "armv7e-m", "fpv5-d16",
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7E-M"));
-  EXPECT_TRUE(testARMCPU("cortex-a32", "armv8-a", "crypto-neon-fp-armv8",
+                         "7-R"),
+        ARMCPUTestParams("cortex-r52", "armv8-r", "neon-fp-armv8",
+                         ARM::AEK_NONE | ARM::AEK_CRC | ARM::AEK_MP |
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+                         "8-R"),
+        ARMCPUTestParams("sc300", "armv7-m", "none",
+                         ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB, "7-M"),
+        ARMCPUTestParams("cortex-m3", "armv7-m", "none",
+                         ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB, "7-M"),
+        ARMCPUTestParams("cortex-m4", "armv7e-m", "fpv4-sp-d16",
+                         ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+                         "7E-M"),
+        ARMCPUTestParams("cortex-m7", "armv7e-m", "fpv5-d16",
+                         ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+                         "7E-M"),
+        ARMCPUTestParams("cortex-a32", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
                              ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                              ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "8-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
+                         "8-A"),
+        ARMCPUTestParams("cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
                              ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                              ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "8-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a53", "armv8-a", "crypto-neon-fp-armv8",
+                         "8-A"),
+        ARMCPUTestParams("cortex-a53", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
                              ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                              ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "8-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
+                         "8-A"),
+        ARMCPUTestParams("cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
-                         ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
-                         ARM::AEK_RAS | ARM::AEK_DOTPROD,
-                         "8.2-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
+                             ARM::AEK_FP16 | ARM::AEK_RAS | ARM::AEK_DOTPROD,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
                              ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                              ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "8-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a72", "armv8-a", "crypto-neon-fp-armv8",
+                         "8-A"),
+        ARMCPUTestParams("cortex-a72", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
                              ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                              ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "8-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a73", "armv8-a", "crypto-neon-fp-armv8",
+                         "8-A"),
+        ARMCPUTestParams("cortex-a73", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
                              ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                              ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "8-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8",
+                         "8-A"),
+        ARMCPUTestParams("cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
-                         ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
-                         ARM::AEK_RAS | ARM::AEK_DOTPROD,
-                         "8.2-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a76", "armv8.2-a", "crypto-neon-fp-armv8",
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
+                             ARM::AEK_FP16 | ARM::AEK_RAS | ARM::AEK_DOTPROD,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a76", "armv8.2-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
-                         ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
-                         ARM::AEK_RAS | ARM::AEK_DOTPROD,
-                         "8.2-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a76ae", "armv8.2-a", "crypto-neon-fp-armv8",
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
+                             ARM::AEK_FP16 | ARM::AEK_RAS | ARM::AEK_DOTPROD,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a76ae", "armv8.2-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
-                         ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
-                         ARM::AEK_RAS | ARM::AEK_DOTPROD,
-                         "8.2-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a77", "armv8.2-a", "crypto-neon-fp-armv8",
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
+                             ARM::AEK_FP16 | ARM::AEK_RAS | ARM::AEK_DOTPROD,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a77", "armv8.2-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
-                         ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
-                         ARM::AEK_RAS | ARM::AEK_DOTPROD,
-                         "8.2-A"));
-  EXPECT_TRUE(testARMCPU("cortex-a78", "armv8.2-a", "crypto-neon-fp-armv8",
-                         ARM::AEK_DOTPROD | ARM::AEK_FP16 |
-                         ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
-                         ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
-                         ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS,
-                         "8.2-A"));
-  EXPECT_TRUE(testARMCPU("cortex-x1", "armv8.2-a", "crypto-neon-fp-armv8",
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
+                             ARM::AEK_FP16 | ARM::AEK_RAS | ARM::AEK_DOTPROD,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a78", "armv8.2-a", "crypto-neon-fp-armv8",
+                         ARM::AEK_DOTPROD | ARM::AEK_FP16 | ARM::AEK_SEC |
+                             ARM::AEK_MP | ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_CRC |
+                             ARM::AEK_RAS,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-x1", "armv8.2-a", "crypto-neon-fp-armv8",
                          ARM::AEK_RAS | ARM::AEK_FP16 | ARM::AEK_DOTPROD |
+                             ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
+                             ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+                             ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS,
+                         "8.2-A"),
+        ARMCPUTestParams("neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
+                         ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
+                             ARM::AEK_FP16 | ARM::AEK_RAS | ARM::AEK_DOTPROD,
+                         "8.2-A"),
+        ARMCPUTestParams("neoverse-n2", "armv8.5-a", "crypto-neon-fp-armv8",
+                         ARM::AEK_CRC | ARM::AEK_HWDIVTHUMB |
+                             ARM::AEK_HWDIVARM | ARM::AEK_MP | ARM::AEK_SEC |
+                             ARM::AEK_VIRT | ARM::AEK_DSP | ARM::AEK_BF16 |
+                             ARM::AEK_DOTPROD | ARM::AEK_RAS | ARM::AEK_I8MM |
+                             ARM::AEK_SB,
+                         "8.5-A"),
+        ARMCPUTestParams("neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
                          ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
-                         ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
-                         ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS,
-                         "8.2-A"));
-  EXPECT_TRUE(testARMCPU("neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
-                        ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
-                        ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                        ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_FP16 |
-                        ARM::AEK_RAS | ARM::AEK_DOTPROD,
-                        "8.2-A"));
-  EXPECT_TRUE(testARMCPU("neoverse-n2", "armv8.5-a", "crypto-neon-fp-armv8",
-                         ARM::AEK_CRC | ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM |
-                         ARM::AEK_MP | ARM::AEK_SEC | ARM::AEK_VIRT |
-                         ARM::AEK_DSP | ARM::AEK_BF16 | ARM::AEK_DOTPROD |
-                         ARM::AEK_RAS | ARM::AEK_I8MM | ARM::AEK_SB,
-                        "8.5-A"));
-  EXPECT_TRUE(testARMCPU("neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
-                         ARM::AEK_SEC | ARM::AEK_MP | ARM::AEK_VIRT |
-                         ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
-                         ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
-                         ARM::AEK_FP16 | ARM::AEK_BF16 | ARM::AEK_DOTPROD,
-                         "8.4-A"));
-  EXPECT_TRUE(testARMCPU("cyclone", "armv8-a", "crypto-neon-fp-armv8",
+                             ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB |
+                             ARM::AEK_DSP | ARM::AEK_CRC | ARM::AEK_RAS |
+                             ARM::AEK_FP16 | ARM::AEK_BF16 | ARM::AEK_DOTPROD,
+                         "8.4-A"),
+        ARMCPUTestParams("cyclone", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
                              ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                              ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "8-A"));
-  EXPECT_TRUE(testARMCPU("exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
+                         "8-A"),
+        ARMCPUTestParams("exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
-                         ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "8-A"));
-  EXPECT_TRUE(testARMCPU("exynos-m4", "armv8.2-a", "crypto-neon-fp-armv8",
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+                         "8-A"),
+        ARMCPUTestParams("exynos-m4", "armv8.2-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
-                         ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_DOTPROD |
-                         ARM::AEK_FP16 | ARM::AEK_RAS,
-                         "8.2-A"));
-  EXPECT_TRUE(testARMCPU("exynos-m5", "armv8.2-a", "crypto-neon-fp-armv8",
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
+                             ARM::AEK_DOTPROD | ARM::AEK_FP16 | ARM::AEK_RAS,
+                         "8.2-A"),
+        ARMCPUTestParams("exynos-m5", "armv8.2-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
-                         ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_DOTPROD |
-                         ARM::AEK_FP16 | ARM::AEK_RAS,
-                         "8.2-A"));
-  EXPECT_TRUE(testARMCPU("cortex-m23", "armv8-m.base", "none",
-                         ARM::AEK_HWDIVTHUMB, "8-M.Baseline"));
-  EXPECT_TRUE(testARMCPU("cortex-m33", "armv8-m.main", "fpv5-sp-d16",
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "8-M.Mainline"));
-  EXPECT_TRUE(testARMCPU("cortex-m35p", "armv8-m.main", "fpv5-sp-d16",
-                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "8-M.Mainline"));
-  EXPECT_TRUE(testARMCPU("cortex-m55", "armv8.1-m.main", "fp-armv8-fullfp16-d16",
+                             ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
+                             ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP |
+                             ARM::AEK_DOTPROD | ARM::AEK_FP16 | ARM::AEK_RAS,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-m23", "armv8-m.base", "none",
+                         ARM::AEK_NONE | ARM::AEK_HWDIVTHUMB, "8-M.Baseline"),
+        ARMCPUTestParams("cortex-m33", "armv8-m.main", "fpv5-sp-d16",
+                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "8-M.Mainline"),
+        ARMCPUTestParams("cortex-m35p", "armv8-m.main", "fpv5-sp-d16",
+                         ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "8-M.Mainline"),
+        ARMCPUTestParams("cortex-m55", "armv8.1-m.main",
+                         "fp-armv8-fullfp16-d16",
                          ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP | ARM::AEK_SIMD |
-                         ARM::AEK_FP         | ARM::AEK_RAS | ARM::AEK_LOB |
-                         ARM::AEK_FP16,
-                        "8.1-M.Mainline"));
-  EXPECT_TRUE(testARMCPU("iwmmxt", "iwmmxt", "none",
-                         ARM::AEK_NONE, "iwmmxt"));
-  EXPECT_TRUE(testARMCPU("xscale", "xscale", "none",
-                         ARM::AEK_NONE, "xscale"));
-  EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4",
+                             ARM::AEK_FP | ARM::AEK_RAS | ARM::AEK_LOB |
+                             ARM::AEK_FP16,
+                         "8.1-M.Mainline"),
+        ARMCPUTestParams("iwmmxt", "iwmmxt", "none", ARM::AEK_NONE, "iwmmxt"),
+        ARMCPUTestParams("xscale", "xscale", "none", ARM::AEK_NONE, "xscale"),
+        ARMCPUTestParams("swift", "armv7s", "neon-vfpv4",
                          ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
-                         "7-S"));
-}
+                         "7-S")), );
 
 static constexpr unsigned NumARMCPUArchs = 91;
 
@@ -798,278 +849,308 @@ TEST(TargetParserTest, ARMparseArchVersion) {
       EXPECT_EQ(5u, ARM::parseArchVersion(ARMArch[i]));
 }
 
-bool testAArch64CPU(StringRef CPUName, StringRef ExpectedArch,
-                    StringRef ExpectedFPU, uint64_t ExpectedFlags,
-                    StringRef CPUAttr) {
-  AArch64::ArchKind AK = AArch64::parseCPUArch(CPUName);
-  bool pass = AArch64::getArchName(AK).equals(ExpectedArch);
+class AArch64CPUTestFixture
+    : public ::testing::TestWithParam<ARMCPUTestParams> {};
 
-  uint64_t ExtKind = AArch64::getDefaultExtensions(CPUName, AK);
-  if (ExtKind > 1 && (ExtKind & AArch64::AEK_NONE))
-    pass &= ((ExtKind ^ AArch64::AEK_NONE) == ExpectedFlags);
-  else
-    pass &= (ExtKind == ExpectedFlags);
+TEST_P(AArch64CPUTestFixture, testAArch64CPU) {
+  ARMCPUTestParams params = GetParam();
 
-  unsigned FPUKind = AArch64::getDefaultFPU(CPUName, AK);
-  pass &= ARM::getFPUName(FPUKind).equals(ExpectedFPU);
+  AArch64::ArchKind AK = AArch64::parseCPUArch(params.CPUName);
+  EXPECT_EQ(params.ExpectedArch, AArch64::getArchName(AK));
 
-  pass &= AArch64::getCPUAttr(AK).equals(CPUAttr);
+  uint64_t default_extensions =
+      AArch64::getDefaultExtensions(params.CPUName, AK);
+  EXPECT_PRED_FORMAT2(AssertSameExtensionFlags<ARM::ISAKind::AARCH64>,
+                      params.ExpectedFlags, default_extensions);
 
-  return pass;
-}
+  unsigned FPUKind = AArch64::getDefaultFPU(params.CPUName, AK);
+  EXPECT_EQ(params.ExpectedFPU, ARM::getFPUName(FPUKind));
 
-TEST(TargetParserTest, testAArch64CPU) {
-  EXPECT_TRUE(testAArch64CPU(
-      "invalid", "invalid", "invalid",
-      AArch64::AEK_NONE, ""));
-  EXPECT_TRUE(testAArch64CPU(
-      "generic", "invalid", "none",
-      AArch64::AEK_NONE, ""));
-
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a34", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a53", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
-      AArch64::AEK_RDM | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
-      AArch64::AEK_RCPC, "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a65", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_DOTPROD |
-      AArch64::AEK_FP | AArch64::AEK_FP16 | AArch64::AEK_LSE |
-      AArch64::AEK_RAS | AArch64::AEK_RCPC | AArch64::AEK_RDM |
-      AArch64::AEK_SIMD | AArch64::AEK_SSBS,
-      "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a65ae", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_DOTPROD |
-      AArch64::AEK_FP | AArch64::AEK_FP16 | AArch64::AEK_LSE |
-      AArch64::AEK_RAS | AArch64::AEK_RCPC | AArch64::AEK_RDM |
-      AArch64::AEK_SIMD | AArch64::AEK_SSBS,
-      "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a72", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a73", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
-      AArch64::AEK_RDM | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
-      AArch64::AEK_RCPC, "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a76", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_RDM | AArch64::AEK_SIMD | AArch64::AEK_RAS |
-      AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
-      AArch64::AEK_RCPC| AArch64::AEK_SSBS, "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a76ae", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_RDM | AArch64::AEK_SIMD | AArch64::AEK_RAS |
-      AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
-      AArch64::AEK_RCPC| AArch64::AEK_SSBS, "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a77", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_RDM | AArch64::AEK_SIMD | AArch64::AEK_RAS |
-      AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
-      AArch64::AEK_RCPC | AArch64::AEK_SSBS, "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-a78", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO  | AArch64::AEK_FP |
-      AArch64::AEK_RDM | AArch64::AEK_SIMD | AArch64::AEK_RAS |
-      AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
-      AArch64::AEK_RCPC | AArch64::AEK_SSBS,
-      "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
-      AArch64::AEK_RCPC | AArch64::AEK_CRC | AArch64::AEK_FP |
-      AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
-      AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
-      AArch64::AEK_CRYPTO | AArch64::AEK_FP16 | AArch64::AEK_BF16,
-      "8.4-A"));
-  EXPECT_TRUE(testAArch64CPU(
-     "cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC     | AArch64::AEK_RDM  | AArch64::AEK_SSBS |
-      AArch64::AEK_DOTPROD | AArch64::AEK_FP   | AArch64::AEK_SIMD |
-      AArch64::AEK_FP16    | AArch64::AEK_FP16FML | AArch64::AEK_RAS |
-      AArch64::AEK_RCPC    | AArch64::AEK_LSE  | AArch64::AEK_SB,
-      "8-R"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cortex-x1", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_RDM | AArch64::AEK_SIMD | AArch64::AEK_RAS |
-      AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
-      AArch64::AEK_RCPC | AArch64::AEK_SSBS,
-      "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "cyclone", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "apple-a7", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "apple-a8", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "apple-a9", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU("apple-a10", "armv8-a", "crypto-neon-fp-armv8",
-                             AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
-                                 AArch64::AEK_FP | AArch64::AEK_RDM |
-                                 AArch64::AEK_SIMD,
-                             "8-A"));
-  EXPECT_TRUE(testAArch64CPU("apple-a11", "armv8.2-a", "crypto-neon-fp-armv8",
-                             AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
-                                 AArch64::AEK_FP | AArch64::AEK_LSE |
-                                 AArch64::AEK_RAS | AArch64::AEK_RDM |
-                                 AArch64::AEK_SIMD,
-                             "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "apple-a12", "armv8.3-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-          AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_RAS |
-          AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_FP16,
-      "8.3-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "apple-a13", "armv8.4-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-          AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_RAS |
-          AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
-          AArch64::AEK_FP16 | AArch64::AEK_FP16FML,
-      "8.4-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "apple-s4", "armv8.3-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-          AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_RAS |
-          AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_FP16,
-      "8.3-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "apple-s5", "armv8.3-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-          AArch64::AEK_SIMD | AArch64::AEK_LSE | AArch64::AEK_RAS |
-          AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_FP16,
-      "8.3-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "exynos-m4", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
-      AArch64::AEK_DOTPROD | AArch64::AEK_FP | AArch64::AEK_FP16 |
-      AArch64::AEK_LSE | AArch64::AEK_RAS | AArch64::AEK_RDM |
-      AArch64::AEK_SIMD, "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "exynos-m5", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
-      AArch64::AEK_DOTPROD | AArch64::AEK_FP | AArch64::AEK_FP16 |
-      AArch64::AEK_LSE | AArch64::AEK_RAS | AArch64::AEK_RDM |
-      AArch64::AEK_SIMD, "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "falkor", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD | AArch64::AEK_RDM, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "kryo", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD, "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-     "neoverse-e1", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_DOTPROD |
-      AArch64::AEK_FP | AArch64::AEK_FP16 | AArch64::AEK_LSE |
-      AArch64::AEK_RAS | AArch64::AEK_RCPC | AArch64::AEK_RDM |
-      AArch64::AEK_SIMD | AArch64::AEK_SSBS,
-     "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-     "neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_DOTPROD |
-      AArch64::AEK_FP | AArch64::AEK_FP16 | AArch64::AEK_LSE |
-      AArch64::AEK_PROFILE | AArch64::AEK_RAS | AArch64::AEK_RCPC |
-      AArch64::AEK_RDM | AArch64::AEK_SIMD | AArch64::AEK_SSBS,
-     "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-     "neoverse-n2", "armv8.5-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
-      AArch64::AEK_LSE | AArch64::AEK_SVE | AArch64::AEK_DOTPROD |
-      AArch64::AEK_RCPC | AArch64::AEK_RDM | AArch64::AEK_MTE |
-      AArch64::AEK_SSBS | AArch64::AEK_SB | AArch64::AEK_SVE2 |
-      AArch64::AEK_SVE2BITPERM | AArch64::AEK_BF16 | AArch64::AEK_I8MM,
-     "8.5-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
-      AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD, "8.1-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "thunderx3t110", "armv8.3-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
-          AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD |
-          AArch64::AEK_PROFILE | AArch64::AEK_RAS | AArch64::AEK_RAND |
-          AArch64::AEK_RCPC,
-      "8.3-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "thunderx", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
-      AArch64::AEK_FP | AArch64::AEK_PROFILE,
-      "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "thunderxt81", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
-      AArch64::AEK_FP | AArch64::AEK_PROFILE,
-      "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "thunderxt83", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
-      AArch64::AEK_FP | AArch64::AEK_PROFILE,
-      "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "thunderxt88", "armv8-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
-      AArch64::AEK_FP | AArch64::AEK_PROFILE,
-      "8-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "tsv110", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
-      AArch64::AEK_RDM | AArch64::AEK_PROFILE | AArch64::AEK_FP16 |
-      AArch64::AEK_FP16FML | AArch64::AEK_DOTPROD,
-      "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "a64fx", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
-      AArch64::AEK_LSE | AArch64::AEK_SVE | AArch64::AEK_RDM,
-      "8.2-A"));
-  EXPECT_TRUE(testAArch64CPU(
-      "carmel", "armv8.2-a", "crypto-neon-fp-armv8",
-      AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
-      AArch64::AEK_SIMD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
-      AArch64::AEK_LSE | AArch64::AEK_RDM,
-      "8.2-A"));
+  EXPECT_EQ(params.CPUAttr, AArch64::getCPUAttr(AK));
 }
 
+INSTANTIATE_TEST_CASE_P(
+    AArch64CPUTests, AArch64CPUTestFixture,
+    ::testing::Values(
+        ARMCPUTestParams("invalid", "invalid", "invalid", AArch64::AEK_NONE,
+                         ""),
+        ARMCPUTestParams("generic", "invalid", "none", AArch64::AEK_NONE, ""),
+
+        ARMCPUTestParams("cortex-a34", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("cortex-a53", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("cortex-a55", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_RAS | AArch64::AEK_LSE |
+                             AArch64::AEK_RDM | AArch64::AEK_FP16 |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("cortex-a65", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_FP |
+                             AArch64::AEK_FP16 | AArch64::AEK_LSE |
+                             AArch64::AEK_RAS | AArch64::AEK_RCPC |
+                             AArch64::AEK_RDM | AArch64::AEK_SIMD |
+                             AArch64::AEK_SSBS,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a65ae", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_FP |
+                             AArch64::AEK_FP16 | AArch64::AEK_LSE |
+                             AArch64::AEK_RAS | AArch64::AEK_RCPC |
+                             AArch64::AEK_RDM | AArch64::AEK_SIMD |
+                             AArch64::AEK_SSBS,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a72", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("cortex-a73", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("cortex-a75", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_RAS | AArch64::AEK_LSE |
+                             AArch64::AEK_RDM | AArch64::AEK_FP16 |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a76", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_RDM |
+                             AArch64::AEK_SIMD | AArch64::AEK_RAS |
+                             AArch64::AEK_LSE | AArch64::AEK_FP16 |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+                             AArch64::AEK_SSBS,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a76ae", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_RDM |
+                             AArch64::AEK_SIMD | AArch64::AEK_RAS |
+                             AArch64::AEK_LSE | AArch64::AEK_FP16 |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+                             AArch64::AEK_SSBS,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a77", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_RDM |
+                             AArch64::AEK_SIMD | AArch64::AEK_RAS |
+                             AArch64::AEK_LSE | AArch64::AEK_FP16 |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+                             AArch64::AEK_SSBS,
+                         "8.2-A"),
+        ARMCPUTestParams("cortex-a78", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_RDM |
+                             AArch64::AEK_SIMD | AArch64::AEK_RAS |
+                             AArch64::AEK_LSE | AArch64::AEK_FP16 |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+                             AArch64::AEK_SSBS,
+                         "8.2-A"),
+        ARMCPUTestParams(
+            "neoverse-v1", "armv8.4-a", "crypto-neon-fp-armv8",
+            AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS |
+                AArch64::AEK_RCPC | AArch64::AEK_CRC | AArch64::AEK_FP |
+                AArch64::AEK_SIMD | AArch64::AEK_RAS | AArch64::AEK_LSE |
+                AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+                AArch64::AEK_CRYPTO | AArch64::AEK_FP16 | AArch64::AEK_BF16,
+            "8.4-A"),
+        ARMCPUTestParams("cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_RDM |
+                             AArch64::AEK_SSBS | AArch64::AEK_DOTPROD |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_FP16 | AArch64::AEK_FP16FML |
+                             AArch64::AEK_RAS | AArch64::AEK_RCPC |
+                             AArch64::AEK_LSE | AArch64::AEK_SB,
+                         "8-R"),
+        ARMCPUTestParams("cortex-x1", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_RDM |
+                             AArch64::AEK_SIMD | AArch64::AEK_RAS |
+                             AArch64::AEK_LSE | AArch64::AEK_FP16 |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+                             AArch64::AEK_SSBS,
+                         "8.2-A"),
+        ARMCPUTestParams("cyclone", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("apple-a7", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("apple-a8", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("apple-a9", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("apple-a10", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_RDM |
+                             AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("apple-a11", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_NONE | AArch64::AEK_CRC |
+                             AArch64::AEK_CRYPTO | AArch64::AEK_FP |
+                             AArch64::AEK_LSE | AArch64::AEK_RAS |
+                             AArch64::AEK_RDM | AArch64::AEK_SIMD,
+                         "8.2-A"),
+        ARMCPUTestParams("apple-a12", "armv8.3-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_LSE | AArch64::AEK_RAS |
+                             AArch64::AEK_RDM | AArch64::AEK_RCPC |
+                             AArch64::AEK_FP16,
+                         "8.3-A"),
+        ARMCPUTestParams("apple-a13", "armv8.4-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_LSE | AArch64::AEK_RAS |
+                             AArch64::AEK_RDM | AArch64::AEK_RCPC |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_FP16 |
+                             AArch64::AEK_FP16FML,
+                         "8.4-A"),
+        ARMCPUTestParams("apple-s4", "armv8.3-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_LSE | AArch64::AEK_RAS |
+                             AArch64::AEK_RDM | AArch64::AEK_RCPC |
+                             AArch64::AEK_FP16,
+                         "8.3-A"),
+        ARMCPUTestParams("apple-s5", "armv8.3-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_LSE | AArch64::AEK_RAS |
+                             AArch64::AEK_RDM | AArch64::AEK_RCPC |
+                             AArch64::AEK_FP16,
+                         "8.3-A"),
+        ARMCPUTestParams("exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("exynos-m4", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_FP |
+                             AArch64::AEK_FP16 | AArch64::AEK_LSE |
+                             AArch64::AEK_RAS | AArch64::AEK_RDM |
+                             AArch64::AEK_SIMD,
+                         "8.2-A"),
+        ARMCPUTestParams("exynos-m5", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_FP |
+                             AArch64::AEK_FP16 | AArch64::AEK_LSE |
+                             AArch64::AEK_RAS | AArch64::AEK_RDM |
+                             AArch64::AEK_SIMD,
+                         "8.2-A"),
+        ARMCPUTestParams("falkor", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_RDM,
+                         "8-A"),
+        ARMCPUTestParams("kryo", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD,
+                         "8-A"),
+        ARMCPUTestParams("neoverse-e1", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_FP |
+                             AArch64::AEK_FP16 | AArch64::AEK_LSE |
+                             AArch64::AEK_RAS | AArch64::AEK_RCPC |
+                             AArch64::AEK_RDM | AArch64::AEK_SIMD |
+                             AArch64::AEK_SSBS,
+                         "8.2-A"),
+        ARMCPUTestParams("neoverse-n1", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_FP |
+                             AArch64::AEK_FP16 | AArch64::AEK_LSE |
+                             AArch64::AEK_PROFILE | AArch64::AEK_RAS |
+                             AArch64::AEK_RCPC | AArch64::AEK_RDM |
+                             AArch64::AEK_SIMD | AArch64::AEK_SSBS,
+                         "8.2-A"),
+        ARMCPUTestParams("neoverse-n2", "armv8.5-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_FP16 | AArch64::AEK_RAS |
+                             AArch64::AEK_LSE | AArch64::AEK_SVE |
+                             AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
+                             AArch64::AEK_RDM | AArch64::AEK_MTE |
+                             AArch64::AEK_SSBS | AArch64::AEK_SB |
+                             AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
+                             AArch64::AEK_BF16 | AArch64::AEK_I8MM,
+                         "8.5-A"),
+        ARMCPUTestParams("thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_NONE | AArch64::AEK_CRC |
+                             AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
+                             AArch64::AEK_RDM | AArch64::AEK_FP |
+                             AArch64::AEK_SIMD,
+                         "8.1-A"),
+        ARMCPUTestParams("thunderx3t110", "armv8.3-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_LSE | AArch64::AEK_RDM |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_PROFILE | AArch64::AEK_RAS |
+                             AArch64::AEK_RAND | AArch64::AEK_RCPC,
+                         "8.3-A"),
+        ARMCPUTestParams("thunderx", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_SIMD | AArch64::AEK_FP |
+                             AArch64::AEK_PROFILE,
+                         "8-A"),
+        ARMCPUTestParams("thunderxt81", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_SIMD | AArch64::AEK_FP |
+                             AArch64::AEK_PROFILE,
+                         "8-A"),
+        ARMCPUTestParams("thunderxt83", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_SIMD | AArch64::AEK_FP |
+                             AArch64::AEK_PROFILE,
+                         "8-A"),
+        ARMCPUTestParams("thunderxt88", "armv8-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_SIMD | AArch64::AEK_FP |
+                             AArch64::AEK_PROFILE,
+                         "8-A"),
+        ARMCPUTestParams("tsv110", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_RAS | AArch64::AEK_LSE |
+                             AArch64::AEK_RDM | AArch64::AEK_PROFILE |
+                             AArch64::AEK_FP16 | AArch64::AEK_FP16FML |
+                             AArch64::AEK_DOTPROD,
+                         "8.2-A"),
+        ARMCPUTestParams("a64fx", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_FP16 | AArch64::AEK_RAS |
+                             AArch64::AEK_LSE | AArch64::AEK_SVE |
+                             AArch64::AEK_RDM,
+                         "8.2-A"),
+        ARMCPUTestParams("carmel", "armv8.2-a", "crypto-neon-fp-armv8",
+                         AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+                             AArch64::AEK_FP | AArch64::AEK_SIMD |
+                             AArch64::AEK_FP16 | AArch64::AEK_RAS |
+                             AArch64::AEK_LSE | AArch64::AEK_RDM,
+                         "8.2-A")), );
+
 static constexpr unsigned NumAArch64CPUArchs = 45;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
@@ -1350,4 +1431,5 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
               AArch64::getArchExtFeature(ArchExt[i][1]));
   }
 }
-}
+
+} // namespace
diff --git a/llvm/unittests/Transforms/Scalar/LoopPassManagerTest.cpp b/llvm/unittests/Transforms/Scalar/LoopPassManagerTest.cpp
index fc41bfa00ead6..a03d43b10ba41 100644
--- a/llvm/unittests/Transforms/Scalar/LoopPassManagerTest.cpp
+++ b/llvm/unittests/Transforms/Scalar/LoopPassManagerTest.cpp
@@ -1603,28 +1603,69 @@ TEST_F(LoopPassManagerTest, LoopDeletion) {
 }
 
 TEST_F(LoopPassManagerTest, HandleLoopNestPass) {
-  ::testing::InSequence MakeExpectationsSequenced;
+  ::testing::Sequence FSequence, GSequence;
 
-  EXPECT_CALL(MLPHandle, run(HasName("loop.0.0"), _, _, _)).Times(2);
-  EXPECT_CALL(MLPHandle, run(HasName("loop.0.1"), _, _, _)).Times(2);
-  EXPECT_CALL(MLPHandle, run(HasName("loop.0"), _, _, _));
-  EXPECT_CALL(MLNPHandle, run(HasName("loop.0"), _, _, _));
-  EXPECT_CALL(MLPHandle, run(HasName("loop.0"), _, _, _));
-  EXPECT_CALL(MLNPHandle, run(HasName("loop.0"), _, _, _));
-  EXPECT_CALL(MLPHandle, run(HasName("loop.g.0"), _, _, _));
-  EXPECT_CALL(MLNPHandle, run(HasName("loop.g.0"), _, _, _));
-  EXPECT_CALL(MLPHandle, run(HasName("loop.g.0"), _, _, _));
-  EXPECT_CALL(MLNPHandle, run(HasName("loop.g.0"), _, _, _));
+  EXPECT_CALL(MLPHandle, run(HasName("loop.0.0"), _, _, _))
+      .Times(2)
+      .InSequence(FSequence);
+  EXPECT_CALL(MLPHandle, run(HasName("loop.0.1"), _, _, _))
+      .Times(2)
+      .InSequence(FSequence);
+  EXPECT_CALL(MLPHandle, run(HasName("loop.0"), _, _, _)).InSequence(FSequence);
+  EXPECT_CALL(MLNPHandle, run(HasName("loop.0"), _, _, _))
+      .InSequence(FSequence);
+  EXPECT_CALL(MLPHandle, run(HasName("loop.0"), _, _, _)).InSequence(FSequence);
+  EXPECT_CALL(MLNPHandle, run(HasName("loop.0"), _, _, _))
+      .InSequence(FSequence);
+  EXPECT_CALL(MLPHandle, run(HasName("loop.g.0"), _, _, _))
+      .InSequence(GSequence);
+  EXPECT_CALL(MLNPHandle, run(HasName("loop.g.0"), _, _, _))
+      .InSequence(GSequence);
+  EXPECT_CALL(MLPHandle, run(HasName("loop.g.0"), _, _, _))
+      .InSequence(GSequence);
+  EXPECT_CALL(MLNPHandle, run(HasName("loop.g.0"), _, _, _))
+      .InSequence(GSequence);
 
-  LoopPassManager LPM(true);
-  LPM.addPass(MLPHandle.getPass());
-  LPM.addPass(MLNPHandle.getPass());
-  LPM.addPass(MLPHandle.getPass());
-  LPM.addPass(MLNPHandle.getPass());
+  EXPECT_CALL(MLNPHandle, run(HasName("loop.0"), _, _, _))
+      .InSequence(FSequence);
+  EXPECT_CALL(MLNPHandle, run(HasName("loop.g.0"), _, _, _))
+      .InSequence(GSequence);
+
+  EXPECT_CALL(MLNPHandle, run(HasName("loop.0"), _, _, _))
+      .InSequence(FSequence);
+  EXPECT_CALL(MLNPHandle, run(HasName("loop.g.0"), _, _, _))
+      .InSequence(GSequence);
 
   ModulePassManager MPM(true);
-  MPM.addPass(createModuleToFunctionPassAdaptor(
-      createFunctionToLoopPassAdaptor(std::move(LPM))));
+  FunctionPassManager FPM(true);
+
+  {
+    LoopPassManager LPM(true);
+    LPM.addPass(MLPHandle.getPass());
+    LPM.addPass(MLNPHandle.getPass());
+    LPM.addPass(MLPHandle.getPass());
+    LPM.addPass(MLNPHandle.getPass());
+
+    auto Adaptor = createFunctionToLoopPassAdaptor(std::move(LPM));
+    ASSERT_FALSE(Adaptor.isLoopNestMode());
+    FPM.addPass(std::move(Adaptor));
+  }
+
+  {
+    auto Adaptor = createFunctionToLoopPassAdaptor(MLNPHandle.getPass());
+    ASSERT_TRUE(Adaptor.isLoopNestMode());
+    FPM.addPass(std::move(Adaptor));
+  }
+
+  {
+    LoopPassManager LPM(true);
+    LPM.addPass(MLNPHandle.getPass());
+    auto Adaptor = createFunctionToLoopPassAdaptor(MLNPHandle.getPass());
+    ASSERT_TRUE(Adaptor.isLoopNestMode());
+    FPM.addPass(std::move(Adaptor));
+  }
+
+  MPM.addPass(createModuleToFunctionPassAdaptor(std::move(FPM)));
   MPM.run(*M, MAM);
 }
 
diff --git a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
index f89abc8769b41..c0230774bd907 100644
--- a/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
+++ b/llvm/unittests/Transforms/Vectorize/VPlanTest.cpp
@@ -8,6 +8,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "../lib/Transforms/Vectorize/VPlan.h"
+#include "llvm/Analysis/VectorUtils.h"
 #include "llvm/IR/Instruction.h"
 #include "llvm/IR/Instructions.h"
 #include "gtest/gtest.h"
@@ -364,7 +365,7 @@ TEST(VPRecipeTest, CastVPInstructionToVPUser) {
   EXPECT_TRUE(isa<VPUser>(&Recipe));
   VPRecipeBase *BaseR = &Recipe;
   EXPECT_TRUE(isa<VPUser>(BaseR));
-  EXPECT_EQ(&Recipe, BaseR->toVPUser());
+  EXPECT_EQ(&Recipe, BaseR);
 }
 
 TEST(VPRecipeTest, CastVPWidenRecipeToVPUser) {
@@ -382,11 +383,11 @@ TEST(VPRecipeTest, CastVPWidenRecipeToVPUser) {
   EXPECT_TRUE(isa<VPUser>(&WidenR));
   VPRecipeBase *WidenRBase = &WidenR;
   EXPECT_TRUE(isa<VPUser>(WidenRBase));
-  EXPECT_EQ(&WidenR, WidenRBase->toVPUser());
+  EXPECT_EQ(&WidenR, WidenRBase);
   delete AI;
 }
 
-TEST(VPRecipeTest, CastVPWidenCallRecipeToVPUser) {
+TEST(VPRecipeTest, CastVPWidenCallRecipeToVPUserAndVPDef) {
   LLVMContext C;
 
   IntegerType *Int32 = IntegerType::get(C, 32);
@@ -401,11 +402,16 @@ TEST(VPRecipeTest, CastVPWidenCallRecipeToVPUser) {
   EXPECT_TRUE(isa<VPUser>(&Recipe));
   VPRecipeBase *BaseR = &Recipe;
   EXPECT_TRUE(isa<VPUser>(BaseR));
-  EXPECT_EQ(&Recipe, BaseR->toVPUser());
+  EXPECT_EQ(&Recipe, BaseR);
+
+  VPValue *VPV = &Recipe;
+  EXPECT_TRUE(isa<VPRecipeBase>(VPV->getDef()));
+  EXPECT_EQ(&Recipe, dyn_cast<VPRecipeBase>(VPV->getDef()));
+
   delete Call;
 }
 
-TEST(VPRecipeTest, CastVPWidenSelectRecipeToVPUser) {
+TEST(VPRecipeTest, CastVPWidenSelectRecipeToVPUserAndVPDef) {
   LLVMContext C;
 
   IntegerType *Int1 = IntegerType::get(C, 1);
@@ -424,11 +430,16 @@ TEST(VPRecipeTest, CastVPWidenSelectRecipeToVPUser) {
   EXPECT_TRUE(isa<VPUser>(&WidenSelectR));
   VPRecipeBase *BaseR = &WidenSelectR;
   EXPECT_TRUE(isa<VPUser>(BaseR));
-  EXPECT_EQ(&WidenSelectR, BaseR->toVPUser());
+  EXPECT_EQ(&WidenSelectR, BaseR);
+
+  VPValue *VPV = &WidenSelectR;
+  EXPECT_TRUE(isa<VPRecipeBase>(VPV->getDef()));
+  EXPECT_EQ(&WidenSelectR, dyn_cast<VPRecipeBase>(VPV->getDef()));
+
   delete SelectI;
 }
 
-TEST(VPRecipeTest, CastVPWidenGEPRecipeToVPUser) {
+TEST(VPRecipeTest, CastVPWidenGEPRecipeToVPUserAndVPDef) {
   LLVMContext C;
 
   IntegerType *Int32 = IntegerType::get(C, 32);
@@ -444,7 +455,12 @@ TEST(VPRecipeTest, CastVPWidenGEPRecipeToVPUser) {
   EXPECT_TRUE(isa<VPUser>(&Recipe));
   VPRecipeBase *BaseR = &Recipe;
   EXPECT_TRUE(isa<VPUser>(BaseR));
-  EXPECT_EQ(&Recipe, BaseR->toVPUser());
+  EXPECT_EQ(&Recipe, BaseR);
+
+  VPValue *VPV = &Recipe;
+  EXPECT_TRUE(isa<VPRecipeBase>(VPV->getDef()));
+  EXPECT_EQ(&Recipe, dyn_cast<VPRecipeBase>(VPV->getDef()));
+
   delete GEP;
 }
 
@@ -470,11 +486,12 @@ TEST(VPRecipeTest, CastVPInterleaveRecipeToVPUser) {
 
   VPValue Addr;
   VPValue Mask;
-  VPInterleaveRecipe Recipe(nullptr, &Addr, {}, &Mask);
+  InterleaveGroup<Instruction> IG(4, false, Align(4));
+  VPInterleaveRecipe Recipe(&IG, &Addr, {}, &Mask);
   EXPECT_TRUE(isa<VPUser>(&Recipe));
   VPRecipeBase *BaseR = &Recipe;
   EXPECT_TRUE(isa<VPUser>(BaseR));
-  EXPECT_EQ(&Recipe, BaseR->toVPUser());
+  EXPECT_EQ(&Recipe, BaseR);
 }
 
 TEST(VPRecipeTest, CastVPReplicateRecipeToVPUser) {
@@ -501,10 +518,10 @@ TEST(VPRecipeTest, CastVPBranchOnMaskRecipeToVPUser) {
   EXPECT_TRUE(isa<VPUser>(&Recipe));
   VPRecipeBase *BaseR = &Recipe;
   EXPECT_TRUE(isa<VPUser>(BaseR));
-  EXPECT_EQ(&Recipe, BaseR->toVPUser());
+  EXPECT_EQ(&Recipe, BaseR);
 }
 
-TEST(VPRecipeTest, CastVPWidenMemoryInstructionRecipeToVPUser) {
+TEST(VPRecipeTest, CastVPWidenMemoryInstructionRecipeToVPUserAndVPDef) {
   LLVMContext C;
 
   IntegerType *Int32 = IntegerType::get(C, 32);
@@ -517,7 +534,12 @@ TEST(VPRecipeTest, CastVPWidenMemoryInstructionRecipeToVPUser) {
   EXPECT_TRUE(isa<VPUser>(&Recipe));
   VPRecipeBase *BaseR = &Recipe;
   EXPECT_TRUE(isa<VPUser>(BaseR));
-  EXPECT_EQ(&Recipe, BaseR->toVPUser());
+  EXPECT_EQ(&Recipe, BaseR);
+
+  VPValue *VPV = Recipe.getVPValue();
+  EXPECT_TRUE(isa<VPRecipeBase>(VPV->getDef()));
+  EXPECT_EQ(&Recipe, dyn_cast<VPRecipeBase>(VPV->getDef()));
+
   delete Load;
 }
 
@@ -534,11 +556,16 @@ TEST(VPRecipeTest, CastVPReductionRecipeToVPUser) {
   EXPECT_TRUE(isa<VPUser>(BaseR));
 }
 
-struct VPDoubleValueDef : public VPUser, public VPDef {
-  VPDoubleValueDef(ArrayRef<VPValue *> Operands) : VPUser(Operands), VPDef() {
+struct VPDoubleValueDef : public VPRecipeBase, public VPUser {
+  VPDoubleValueDef(ArrayRef<VPValue *> Operands)
+      : VPRecipeBase(99), VPUser(Operands) {
     new VPValue(nullptr, this);
     new VPValue(nullptr, this);
   }
+
+  void execute(struct VPTransformState &State) override{};
+  void print(raw_ostream &O, const Twine &Indent,
+             VPSlotTracker &SlotTracker) const override {}
 };
 
 TEST(VPDoubleValueDefTest, traverseUseLists) {
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index 9a5908827b4ef..3e27bd78b376f 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -522,10 +522,8 @@ void AsmWriterEmitter::EmitPrintInstruction(
   }
 
   // Okay, delete instructions with no operand info left.
-  auto I = llvm::remove_if(Instructions,
-                     [](AsmWriterInst &Inst) { return Inst.Operands.empty(); });
-  Instructions.erase(I, Instructions.end());
-
+  llvm::erase_if(Instructions,
+                 [](AsmWriterInst &Inst) { return Inst.Operands.empty(); });
 
   // Because this is a vector, we want to emit from the end.  Reverse all of the
   // elements in the vector.
diff --git a/llvm/utils/TableGen/DirectiveEmitter.cpp b/llvm/utils/TableGen/DirectiveEmitter.cpp
index ff6050b07f52b..9e8aa4d9f74fb 100644
--- a/llvm/utils/TableGen/DirectiveEmitter.cpp
+++ b/llvm/utils/TableGen/DirectiveEmitter.cpp
@@ -107,6 +107,12 @@ void GenerateEnumClauseVal(const std::vector<Record *> &Records,
       EnumHelperFuncs += (llvm::Twine(EnumName) + llvm::Twine(" get") +
                           llvm::Twine(EnumName) + llvm::Twine("(StringRef);\n"))
                              .str();
+
+      EnumHelperFuncs +=
+          (llvm::Twine("llvm::StringRef get") + llvm::Twine(DirLang.getName()) +
+           llvm::Twine(EnumName) + llvm::Twine("Name(") +
+           llvm::Twine(EnumName) + llvm::Twine(");\n"))
+              .str();
     }
   }
 }
@@ -336,6 +342,22 @@ void GenerateGetKindClauseVal(const DirectiveLanguage &DirLang,
     }
     OS << "    .Default(" << DefaultName << ");\n";
     OS << "}\n";
+
+    OS << "\n";
+    OS << "llvm::StringRef llvm::" << DirLang.getCppNamespace() << "::get"
+       << DirLang.getName() << EnumName
+       << "Name(llvm::" << DirLang.getCppNamespace() << "::" << EnumName
+       << " x) {\n";
+    OS << "  switch (x) {\n";
+    for (const auto &CV : ClauseVals) {
+      ClauseVal CVal{CV};
+      OS << "    case " << CV->getName() << ":\n";
+      OS << "      return \"" << CVal.getFormattedName() << "\";\n";
+    }
+    OS << "  }\n"; // switch
+    OS << "  llvm_unreachable(\"Invalid " << DirLang.getName() << " "
+       << EnumName << " kind\");\n";
+    OS << "}\n";
   }
 }
 
@@ -627,7 +649,7 @@ void GenerateFlangClauseUnparse(const DirectiveLanguage &DirLang,
   }
 }
 
-// Generate the implemenation section for the enumeration in the directive
+// Generate the implementation section for the enumeration in the directive
 // language
 void EmitDirectivesFlangImpl(const DirectiveLanguage &DirLang,
                              raw_ostream &OS) {
@@ -711,7 +733,7 @@ void GenerateClauseClassMacro(const DirectiveLanguage &DirLang,
   OS << "#undef CLAUSE\n";
 }
 
-// Generate the implemenation section for the enumeration in the directive
+// Generate the implementation section for the enumeration in the directive
 // language.
 void EmitDirectivesGen(RecordKeeper &Records, raw_ostream &OS) {
   const auto DirLang = DirectiveLanguage{Records};
@@ -723,7 +745,7 @@ void EmitDirectivesGen(RecordKeeper &Records, raw_ostream &OS) {
   GenerateClauseClassMacro(DirLang, OS);
 }
 
-// Generate the implemenation for the enumeration in the directive
+// Generate the implementation for the enumeration in the directive
 // language. This code can be included in library.
 void EmitDirectivesImpl(RecordKeeper &Records, raw_ostream &OS) {
   const auto DirLang = DirectiveLanguage{Records};
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 156fa6d18d2ee..71d8eadaa61e4 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -182,11 +182,10 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
       if (Constraint.isNone())
         Res += "0";
       else if (Constraint.isEarlyClobber())
-        Res += "(1 << MCOI::EARLY_CLOBBER)";
+        Res += "MCOI_EARLY_CLOBBER";
       else {
         assert(Constraint.isTied());
-        Res += "((" + utostr(Constraint.getTiedOperand()) +
-                    " << 16) | (1 << MCOI::TIED_TO))";
+        Res += "MCOI_TIED_TO(" + utostr(Constraint.getTiedOperand()) + ")";
       }
 
       Result.push_back(Res);
diff --git a/llvm/utils/TableGen/OptParserEmitter.cpp b/llvm/utils/TableGen/OptParserEmitter.cpp
index b3fe9d7a91d16..a08a837e5e70c 100644
--- a/llvm/utils/TableGen/OptParserEmitter.cpp
+++ b/llvm/utils/TableGen/OptParserEmitter.cpp
@@ -219,13 +219,12 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   PrefixesT Prefixes;
   Prefixes.insert(std::make_pair(PrefixKeyT(), "prefix_0"));
   unsigned CurPrefix = 0;
-  for (unsigned i = 0, e = Opts.size(); i != e; ++i) {
-    const Record &R = *Opts[i];
-    std::vector<StringRef> prf = R.getValueAsListOfStrings("Prefixes");
-    PrefixKeyT prfkey(prf.begin(), prf.end());
+  for (const Record &R : llvm::make_pointee_range(Opts)) {
+    std::vector<StringRef> RPrefixes = R.getValueAsListOfStrings("Prefixes");
+    PrefixKeyT PrefixKey(RPrefixes.begin(), RPrefixes.end());
     unsigned NewPrefix = CurPrefix + 1;
-    if (Prefixes.insert(std::make_pair(prfkey, (Twine("prefix_") +
-                                              Twine(NewPrefix)).str())).second)
+    std::string Prefix = (Twine("prefix_") + Twine(NewPrefix)).str();
+    if (Prefixes.insert(std::make_pair(PrefixKey, Prefix)).second)
       CurPrefix = NewPrefix;
   }
 
@@ -235,19 +234,16 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   OS << "// Prefixes\n\n";
   OS << "#ifdef PREFIX\n";
   OS << "#define COMMA ,\n";
-  for (PrefixesT::const_iterator I = Prefixes.begin(), E = Prefixes.end();
-                                  I != E; ++I) {
+  for (const auto &Prefix : Prefixes) {
     OS << "PREFIX(";
 
     // Prefix name.
-    OS << I->second;
+    OS << Prefix.second;
 
     // Prefix values.
     OS << ", {";
-    for (PrefixKeyT::const_iterator PI = I->first.begin(),
-                                    PE = I->first.end(); PI != PE; ++PI) {
-      OS << "\"" << *PI << "\" COMMA ";
-    }
+    for (StringRef PrefixKey : Prefix.first)
+      OS << "\"" << PrefixKey << "\" COMMA ";
     OS << "nullptr})\n";
   }
   OS << "#undef COMMA\n";
@@ -256,9 +252,7 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   OS << "/////////\n";
   OS << "// Groups\n\n";
   OS << "#ifdef OPTION\n";
-  for (unsigned i = 0, e = Groups.size(); i != e; ++i) {
-    const Record &R = *Groups[i];
-
+  for (const Record &R : llvm::make_pointee_range(Groups)) {
     // Start a single option entry.
     OS << "OPTION(";
 
@@ -305,8 +299,8 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
 
   auto WriteOptRecordFields = [&](raw_ostream &OS, const Record &R) {
     // The option prefix;
-    std::vector<StringRef> prf = R.getValueAsListOfStrings("Prefixes");
-    OS << Prefixes[PrefixKeyT(prf.begin(), prf.end())] << ", ";
+    std::vector<StringRef> RPrefixes = R.getValueAsListOfStrings("Prefixes");
+    OS << Prefixes[PrefixKeyT(RPrefixes.begin(), RPrefixes.end())] << ", ";
 
     // The option string.
     emitNameUsingSpelling(OS, R);
@@ -343,8 +337,8 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
       OS << "nullptr";
     } else {
       OS << "\"";
-      for (size_t i = 0, e = AliasArgs.size(); i != e; ++i)
-        OS << AliasArgs[i] << "\\0";
+      for (StringRef AliasArg : AliasArgs)
+        OS << AliasArg << "\\0";
       OS << "\"";
     }
 
@@ -394,9 +388,7 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   };
 
   std::vector<const Record *> OptsWithMarshalling;
-  for (unsigned I = 0, E = Opts.size(); I != E; ++I) {
-    const Record &R = *Opts[I];
-
+  for (const Record &R : llvm::make_pointee_range(Opts)) {
     // Start a single option entry.
     OS << "OPTION(";
     WriteOptRecordFields(OS, R);
@@ -462,8 +454,7 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) {
   OS << "#ifdef OPTTABLE_ARG_INIT\n";
   OS << "//////////\n";
   OS << "// Option Values\n\n";
-  for (unsigned I = 0, E = Opts.size(); I != E; ++I) {
-    const Record &R = *Opts[I];
+  for (const Record &R : llvm::make_pointee_range(Opts)) {
     if (isa<UnsetInit>(R.getValueInit("ValuesCode")))
       continue;
     OS << "{\n";
diff --git a/llvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn b/llvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
index 908dce6a12e5b..c07a61fe61e43 100644
--- a/llvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang-tools-extra/clangd/BUILD.gn
@@ -11,13 +11,15 @@ config("features_config") {
 write_cmake_config("features") {
   input = "Features.inc.in"
   output = "$target_gen_dir/Features.inc"
-  values = []
+  values = [
+    "CLANGD_ENABLE_REMOTE=0",
+    "CLANGD_MALLOC_TRIM=1",
+  ]
   if (clangd_build_xpc) {
     values += [ "CLANGD_BUILD_XPC=1" ]
   } else {
     values += [ "CLANGD_BUILD_XPC=0" ]
   }
-  values += [ "CLANGD_ENABLE_REMOTE=0" ]
   public_configs = [ ":features_config" ]
 }
 
diff --git a/llvm/utils/gn/secondary/clang/unittests/BUILD.gn b/llvm/utils/gn/secondary/clang/unittests/BUILD.gn
index d1382919b5e29..23f5d2dfac85c 100644
--- a/llvm/utils/gn/secondary/clang/unittests/BUILD.gn
+++ b/llvm/utils/gn/secondary/clang/unittests/BUILD.gn
@@ -10,6 +10,7 @@ group("unittests") {
     "CrossTU:CrossTUTests",
     "Driver:ClangDriverTests",
     "Format:FormatTests",
+    "Frontend:FrontendTests",
     "Index:IndexTests",
     "Lex:LexTests",
     "Rename:ClangRenameTests",
@@ -22,7 +23,6 @@ group("unittests") {
   if (clang_enable_static_analyzer) {
     deps += [
       "Analysis:ClangAnalysisTests",
-      "Frontend:FrontendTests",
       "StaticAnalyzer:StaticAnalysisTests",
     ]
   }
diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
index b9154a449557b..fdc0751231b5a 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
@@ -112,6 +112,7 @@ static_library("LLVMAMDGPUCodeGen") {
     "//llvm/lib/CodeGen/SelectionDAG",
     "//llvm/lib/IR",
     "//llvm/lib/MC",
+    "//llvm/lib/Passes",
     "//llvm/lib/Support",
     "//llvm/lib/Target",
     "//llvm/lib/Transforms/IPO",
diff --git a/mlir/docs/ConversionToLLVMDialect.md b/mlir/docs/ConversionToLLVMDialect.md
index 778eea6184c9e..2b5f98b376861 100644
--- a/mlir/docs/ConversionToLLVMDialect.md
+++ b/mlir/docs/ConversionToLLVMDialect.md
@@ -280,470 +280,3 @@ Examples:
 !llvm.func<struct<(struct<(ptr<float>, ptr<float>, i64)>,
                    struct<(ptr<double>, ptr<double>, i64)>)> ()>
 ```
-
-## Calling Convention for Standard Calls
-
-<!-- TODO: This should be moved to a separate file, and the remaining file
-     renamed decouple the description of built-in type conversion from standard
-     dialect ops conversion. -->
-
-### Result Packing
-
-In case of multi-result functions, the returned values are inserted into a
-structure-typed value before being returned and extracted from it at the call
-site. This transformation is a part of the conversion and is transparent to the
-defines and uses of the values being returned.
-
-Example:
-
-```mlir
-func @foo(%arg0: i32, %arg1: i64) -> (i32, i64) {
-  return %arg0, %arg1 : i32, i64
-}
-func @bar() {
-  %0 = constant 42 : i32
-  %1 = constant 17 : i64
-  %2:2 = call @foo(%0, %1) : (i32, i64) -> (i32, i64)
-  "use_i32"(%2#0) : (i32) -> ()
-  "use_i64"(%2#1) : (i64) -> ()
-}
-
-// is transformed into
-
-func @foo(%arg0: !llvm.i32, %arg1: !llvm.i64) -> !llvm<"{i32, i64}"> {
-  // insert the vales into a structure
-  %0 = llvm.mlir.undef :  !llvm<"{i32, i64}">
-  %1 = llvm.insertvalue %arg0, %0[0] : !llvm<"{i32, i64}">
-  %2 = llvm.insertvalue %arg1, %1[1] : !llvm<"{i32, i64}">
-
-  // return the structure value
-  llvm.return %2 : !llvm<"{i32, i64}">
-}
-func @bar() {
-  %0 = llvm.mlir.constant(42 : i32) : !llvm.i32
-  %1 = llvm.mlir.constant(17) : !llvm.i64
-
-  // call and extract the values from the structure
-  %2 = llvm.call @bar(%0, %1) : (%arg0: !llvm.i32, %arg1: !llvm.i32) -> !llvm<"{i32, i64}">
-  %3 = llvm.extractvalue %2[0] : !llvm<"{i32, i64}">
-  %4 = llvm.extractvalue %2[1] : !llvm<"{i32, i64}">
-
-  // use as before
-  "use_i32"(%3) : (!llvm.i32) -> ()
-  "use_i64"(%4) : (!llvm.i64) -> ()
-}
-```
-
-### Calling Convention for Ranked `memref`
-
-Function _arguments_ of `memref` type, ranked or unranked, are _expanded_ into a
-list of arguments of non-aggregate types that the memref descriptor defined
-above comprises. That is, the outer struct type and the inner array types are
-replaced with individual arguments.
-
-This convention is implemented in the conversion of `std.func` and `std.call` to
-the LLVM dialect, with the former unpacking the descriptor into a set of
-individual values and the latter packing those values back into a descriptor so
-as to make it transparently usable by other operations. Conversions from other
-dialects should take this convention into account.
-
-This specific convention is motivated by the necessity to specify alignment and
-aliasing attributes on the raw pointers underpinning the memref.
-
-Examples:
-
-```mlir
-func @foo(%arg0: memref<?xf32>) -> () {
-  "use"(%arg0) : (memref<?xf32>) -> ()
-  return
-}
-
-// Gets converted to the following.
-
-llvm.func @foo(%arg0: !llvm<"float*">,   // Allocated pointer.
-               %arg1: !llvm<"float*">,   // Aligned pointer.
-               %arg2: !llvm.i64,         // Offset.
-               %arg3: !llvm.i64,         // Size in dim 0.
-               %arg4: !llvm.i64) {       // Stride in dim 0.
-  // Populate memref descriptor structure.
-  %0 = llvm.mlir.undef : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-  %1 = llvm.insertvalue %arg0, %0[0] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-  %2 = llvm.insertvalue %arg1, %1[1] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-  %3 = llvm.insertvalue %arg2, %2[2] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-  %4 = llvm.insertvalue %arg3, %3[3, 0] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-  %5 = llvm.insertvalue %arg4, %4[4, 0] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-
-  // Descriptor is now usable as a single value.
-  "use"(%5) : (!llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">) -> ()
-  llvm.return
-}
-```
-
-```mlir
-func @bar() {
-  %0 = "get"() : () -> (memref<?xf32>)
-  call @foo(%0) : (memref<?xf32>) -> ()
-  return
-}
-
-// Gets converted to the following.
-
-llvm.func @bar() {
-  %0 = "get"() : () -> !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-
-  // Unpack the memref descriptor.
-  %1 = llvm.extractvalue %0[0] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-  %2 = llvm.extractvalue %0[1] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-  %3 = llvm.extractvalue %0[2] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-  %4 = llvm.extractvalue %0[3, 0] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-  %5 = llvm.extractvalue %0[4, 0] : !llvm<"{ float*, float*, i64, [1 x i64], [1 x i64] }">
-
-  // Pass individual values to the callee.
-  llvm.call @foo(%1, %2, %3, %4, %5) : (!llvm<"float*">, !llvm<"float*">, !llvm.i64, !llvm.i64, !llvm.i64) -> ()
-  llvm.return
-}
-
-```
-
-### Calling Convention for Unranked `memref`
-
-For unranked memrefs, the list of function arguments always contains two
-elements, same as the unranked memref descriptor: an integer rank, and a
-type-erased (`!llvm<"i8*">`) pointer to the ranked memref descriptor. Note that
-while the _calling convention_ does not require stack allocation, _casting_ to
-unranked memref does since one cannot take an address of an SSA value containing
-the ranked memref. The caller is in charge of ensuring the thread safety and
-eventually removing unnecessary stack allocations in cast operations.
-
-Example
-
-```mlir
-llvm.func @foo(%arg0: memref<*xf32>) -> () {
-  "use"(%arg0) : (memref<*xf32>) -> ()
-  return
-}
-
-// Gets converted to the following.
-
-llvm.func @foo(%arg0: !llvm.i64       // Rank.
-               %arg1: !llvm<"i8*">) { // Type-erased pointer to descriptor.
-  // Pack the unranked memref descriptor.
-  %0 = llvm.mlir.undef : !llvm<"{ i64, i8* }">
-  %1 = llvm.insertvalue %arg0, %0[0] : !llvm<"{ i64, i8* }">
-  %2 = llvm.insertvalue %arg1, %1[1] : !llvm<"{ i64, i8* }">
-
-  "use"(%2) : (!llvm<"{ i64, i8* }">) -> ()
-  llvm.return
-}
-```
-
-```mlir
-llvm.func @bar() {
-  %0 = "get"() : () -> (memref<*xf32>)
-  call @foo(%0): (memref<*xf32>) -> ()
-  return
-}
-
-// Gets converted to the following.
-
-llvm.func @bar() {
-  %0 = "get"() : () -> (!llvm<"{ i64, i8* }">)
-
-  // Unpack the memref descriptor.
-  %1 = llvm.extractvalue %0[0] : !llvm<"{ i64, i8* }">
-  %2 = llvm.extractvalue %0[1] : !llvm<"{ i64, i8* }">
-
-  // Pass individual values to the callee.
-  llvm.call @foo(%1, %2) : (!llvm.i64, !llvm<"i8*">)
-  llvm.return
-}
-```
-
-**Lifetime.** The second element of the unranked memref descriptor points to
-some memory in which the ranked memref descriptor is stored. By convention, this
-memory is allocated on stack and has the lifetime of the function. (*Note:* due
-to function-length lifetime, creation of multiple unranked memref descriptors,
-e.g., in a loop, may lead to stack overflows.) If an unranked descriptor has to
-be returned from a function, the ranked descriptor it points to is copied into
-dynamically allocated memory, and the pointer in the unranked descriptor is
-updated accordingly. The allocation happens immediately before returning. It is
-the responsibility of the caller to free the dynamically allocated memory. The
-default conversion of `std.call` and `std.call_indirect` copies the ranked
-descriptor to newly allocated memory on the caller's stack. Thus, the convention
-of the ranked memref descriptor pointed to by an unranked memref descriptor
-being stored on stack is respected.
-
-*This convention may or may not apply if the conversion of MemRef types is
-overridden by the user.*
-
-### C-compatible wrapper emission
-
-In practical cases, it may be desirable to have externally-facing functions with
-a single attribute corresponding to a MemRef argument. When interfacing with
-LLVM IR produced from C, the code needs to respect the corresponding calling
-convention. The conversion to the LLVM dialect provides an option to generate
-wrapper functions that take memref descriptors as pointers-to-struct compatible
-with data types produced by Clang when compiling C sources. The generation of
-such wrapper functions can additionally be controlled at a function granularity
-by setting the `llvm.emit_c_interface` unit attribute.
-
-More specifically, a memref argument is converted into a pointer-to-struct
-argument of type `{T*, T*, i64, i64[N], i64[N]}*` in the wrapper function, where
-`T` is the converted element type and `N` is the memref rank. This type is
-compatible with that produced by Clang for the following C++ structure template
-instantiations or their equivalents in C.
-
-```cpp
-template<typename T, size_t N>
-struct MemRefDescriptor {
-  T *allocated;
-  T *aligned;
-  intptr_t offset;
-  intptr_t sizes[N];
-  intptr_t strides[N];
-};
-```
-
-If enabled, the option will do the following. For _external_ functions declared
-in the MLIR module.
-
-1. Declare a new function `_mlir_ciface_<original name>` where memref arguments
-   are converted to pointer-to-struct and the remaining arguments are converted
-   as usual.
-1. Add a body to the original function (making it non-external) that
-   1. allocates a memref descriptor,
-   1. populates it, and
-   1. passes the pointer to it into the newly declared interface function, then
-   1. collects the result of the call and returns it to the caller.
-
-For (non-external) functions defined in the MLIR module.
-
-1. Define a new function `_mlir_ciface_<original name>` where memref arguments
-   are converted to pointer-to-struct and the remaining arguments are converted
-   as usual.
-1. Populate the body of the newly defined function with IR that
-   1. loads descriptors from pointers;
-   1. unpacks descriptor into individual non-aggregate values;
-   1. passes these values into the original function;
-   1. collects the result of the call and returns it to the caller.
-
-Examples:
-
-```mlir
-
-func @qux(%arg0: memref<?x?xf32>)
-
-// Gets converted into the following.
-
-// Function with unpacked arguments.
-llvm.func @qux(%arg0: !llvm<"float*">, %arg1: !llvm<"float*">, %arg2: !llvm.i64,
-               %arg3: !llvm.i64, %arg4: !llvm.i64, %arg5: !llvm.i64,
-               %arg6: !llvm.i64) {
-  // Populate memref descriptor (as per calling convention).
-  %0 = llvm.mlir.undef : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %1 = llvm.insertvalue %arg0, %0[0] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %2 = llvm.insertvalue %arg1, %1[1] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %3 = llvm.insertvalue %arg2, %2[2] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %4 = llvm.insertvalue %arg3, %3[3, 0] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %5 = llvm.insertvalue %arg5, %4[4, 0] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %6 = llvm.insertvalue %arg4, %5[3, 1] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %7 = llvm.insertvalue %arg6, %6[4, 1] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-
-  // Store the descriptor in a stack-allocated space.
-  %8 = llvm.mlir.constant(1 : index) : !llvm.i64
-  %9 = llvm.alloca %8 x !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-                 : (!llvm.i64) -> !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }*">
-  llvm.store %7, %9 : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }*">
-
-  // Call the interface function.
-  llvm.call @_mlir_ciface_qux(%9) : (!llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }*">) -> ()
-
-  // The stored descriptor will be freed on return.
-  llvm.return
-}
-
-// Interface function.
-llvm.func @_mlir_ciface_qux(!llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }*">)
-```
-
-```mlir
-func @foo(%arg0: memref<?x?xf32>) {
-  return
-}
-
-// Gets converted into the following.
-
-// Function with unpacked arguments.
-llvm.func @foo(%arg0: !llvm<"float*">, %arg1: !llvm<"float*">, %arg2: !llvm.i64,
-               %arg3: !llvm.i64, %arg4: !llvm.i64, %arg5: !llvm.i64,
-               %arg6: !llvm.i64) {
-  llvm.return
-}
-
-// Interface function callable from C.
-llvm.func @_mlir_ciface_foo(%arg0: !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }*">) {
-  // Load the descriptor.
-  %0 = llvm.load %arg0 : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }*">
-
-  // Unpack the descriptor as per calling convention.
-  %1 = llvm.extractvalue %0[0] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %2 = llvm.extractvalue %0[1] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %3 = llvm.extractvalue %0[2] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %4 = llvm.extractvalue %0[3, 0] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %5 = llvm.extractvalue %0[3, 1] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %6 = llvm.extractvalue %0[4, 0] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  %7 = llvm.extractvalue %0[4, 1] : !llvm<"{ float*, float*, i64, [2 x i64], [2 x i64] }">
-  llvm.call @foo(%1, %2, %3, %4, %5, %6, %7)
-    : (!llvm<"float*">, !llvm<"float*">, !llvm.i64, !llvm.i64, !llvm.i64,
-       !llvm.i64, !llvm.i64) -> ()
-  llvm.return
-}
-```
-
-Rationale: Introducing auxiliary functions for C-compatible interfaces is
-preferred to modifying the calling convention since it will minimize the effect
-of C compatibility on intra-module calls or calls between MLIR-generated
-functions. In particular, when calling external functions from an MLIR module in
-a (parallel) loop, the fact of storing a memref descriptor on stack can lead to
-stack exhaustion and/or concurrent access to the same address. Auxiliary
-interface function serves as an allocation scope in this case. Furthermore, when
-targeting accelerators with separate memory spaces such as GPUs, stack-allocated
-descriptors passed by pointer would have to be transferred to the device memory,
-which introduces significant overhead. In such situations, auxiliary interface
-functions are executed on host and only pass the values through device function
-invocation mechanism.
-
-## Repeated Successor Removal
-
-Since the goal of the LLVM IR dialect is to reflect LLVM IR in MLIR, the dialect
-and the conversion procedure must account for the differences between block
-arguments and LLVM IR PHI nodes. In particular, LLVM IR disallows PHI nodes with
-different values coming from the same source. Therefore, the LLVM IR dialect
-disallows operations that have identical successors accepting arguments, which
-would lead to invalid PHI nodes. The conversion process resolves the potential
-PHI source ambiguity by injecting dummy blocks if the same block is used more
-than once as a successor in an instruction. These dummy blocks branch
-unconditionally to the original successors, pass them the original operands
-(available in the dummy block because it is dominated by the original block) and
-are used instead of them in the original terminator operation.
-
-Example:
-
-```mlir
-  cond_br %0, ^bb1(%1 : i32), ^bb1(%2 : i32)
-^bb1(%3 : i32)
-  "use"(%3) : (i32) -> ()
-```
-
-leads to a new basic block being inserted,
-
-```mlir
-  cond_br %0, ^bb1(%1 : i32), ^dummy
-^bb1(%3 : i32):
-  "use"(%3) : (i32) -> ()
-^dummy:
-  br ^bb1(%4 : i32)
-```
-
-before the conversion to the LLVM IR dialect:
-
-```mlir
-  llvm.cond_br  %0, ^bb1(%1 : !llvm.i32), ^dummy
-^bb1(%3 : !llvm<"i32">):
-  "use"(%3) : (!llvm.i32) -> ()
-^dummy:
-  llvm.br ^bb1(%2 : !llvm.i32)
-```
-
-## Default Memref Model
-
-### Memref Descriptor
-
-Within a converted function, a `memref`-typed value is represented by a memref
-_descriptor_, the type of which is the structure type obtained by converting
-from the memref type. This descriptor holds all the necessary information to
-produce an address of a specific element. In particular, it holds dynamic values
-for static sizes, and they are expected to match at all times.
-
-It is created by the allocation operation and is updated by the conversion
-operations that may change static dimensions into dynamic dimensions and vice versa.
-
-**Note**: LLVM IR conversion does not support `memref`s with layouts that are
-not amenable to the strided form.
-
-### Index Linearization
-
-Accesses to a memref element are transformed into an access to an element of the
-buffer pointed to by the descriptor. The position of the element in the buffer
-is calculated by linearizing memref indices in row-major order (lexically first
-index is the slowest varying, similar to C, but accounting for strides). The
-computation of the linear address is emitted as arithmetic operation in the LLVM
-IR dialect. Strides are extracted from the memref descriptor.
-
-Accesses to zero-dimensional memref (that are interpreted as pointers to the
-elemental type) are directly converted into `llvm.load` or `llvm.store` without
-any pointer manipulations.
-
-Examples:
-
-An access to a zero-dimensional memref is converted into a plain load:
-
-```mlir
-// before
-%0 = load %m[] : memref<f32>
-
-// after
-%0 = llvm.load %m : !llvm<"float*">
-```
-
-An access to a memref with indices:
-
-```mlir
-%0 = load %m[1,2,3,4] : memref<10x?x13x?xf32>
-```
-
-is transformed into the equivalent of the following code:
-
-```mlir
-// Compute the linearized index from strides. Each block below extracts one
-// stride from the descriptor, multiplies it with the index and accumulates
-// the total offset.
-%stride1 = llvm.extractvalue[4, 0] : !llvm<"{float*, float*, i64, i64[4], i64[4]}">
-%idx1 = llvm.mlir.constant(1 : index) !llvm.i64
-%addr1 = muli %stride1, %idx1 : !llvm.i64
-
-%stride2 = llvm.extractvalue[4, 1] : !llvm<"{float*, float*, i64, i64[4], i64[4]}">
-%idx2 = llvm.mlir.constant(2 : index) !llvm.i64
-%addr2 = muli %stride2, %idx2 : !llvm.i64
-%addr3 = addi %addr1, %addr2 : !llvm.i64
-
-%stride3 = llvm.extractvalue[4, 2] : !llvm<"{float*, float*, i64, i64[4], i64[4]}">
-%idx3 = llvm.mlir.constant(3 : index) !llvm.i64
-%addr4 = muli %stride3, %idx3 : !llvm.i64
-%addr5 = addi %addr3, %addr4 : !llvm.i64
-
-%stride4 = llvm.extractvalue[4, 3] : !llvm<"{float*, float*, i64, i64[4], i64[4]}">
-%idx4 = llvm.mlir.constant(4 : index) !llvm.i64
-%addr6 = muli %stride4, %idx4 : !llvm.i64
-%addr7 = addi %addr5, %addr6 : !llvm.i64
-
-// Add the linear offset to the address.
-%offset = llvm.extractvalue[2] : !llvm<"{float*, float*, i64, i64[4], i64[4]}">
-%addr8 = addi %addr7, %offset : !llvm.i64
-
-// Obtain the aligned pointer.
-%aligned = llvm.extractvalue[1] : !llvm<"{float*, float*, i64, i64[4], i64[4]}">
-
-// Get the address of the data pointer.
-%ptr = llvm.getelementptr %aligned[%addr8]
-    : !llvm<"{float*, float*, i64, i64[4], i64[4]}"> -> !llvm<"float*">
-
-// Perform the actual load.
-%0 = llvm.load %ptr : !llvm<"float*">
-```
-
-For stores, the address computation code is identical and only the actual store
-operation is different.
-
-Note: the conversion does not perform any sort of common subexpression
-elimination when emitting memref accesses.
diff --git a/mlir/docs/Dialects/Linalg.md b/mlir/docs/Dialects/Linalg.md
index 02508a81b63ae..18473f4cb7966 100644
--- a/mlir/docs/Dialects/Linalg.md
+++ b/mlir/docs/Dialects/Linalg.md
@@ -21,8 +21,8 @@ Linalg. They are all implemented in terms of the properties of the
 one-off op knowledge.
 
 The textual form description of these transformations is left for future work.
-Still, it is useful to at least the key transformations that are performed on
-the Linalg IR and that have influenced its design:
+Still, it is useful to list the key transformations that are performed on the
+Linalg IR and that have influenced its design:
 
 1.  Progressive Buffer Allocation.
 1.  Parametric Tiling.
@@ -42,8 +42,25 @@ Linalg takes at least some inspiration from all previously
 [key transformations](#key_transformations), including lowering to scalar
 load/store and other operations or to external library calls and intrinsics.
 
-These ops can have ***either tensor or buffer operands***, subject to
-[conventions and limitations](#tensors_and_buffers).
+These ops can have ***either tensor or buffer*** as both input and output
+operands. Output tensors operands serve the purpose of providing a unifying
+abstraction and give a shape to the results. Output tensors can come in 2
+flavors and are always associated with a corresponding op result:
+
+1.  an "init tensor" output value which provides an initial value for a tensor
+    that is created by iteratively updating the result (also called "destructive
+    updates"). Such tensor is always materialized in some form. If enough fusion
+    occurs it may end up being materialized only as a register-level SSA value.
+    It is expected (but not required) that the destructive update pattern can be
+    rewritten as an inplace update on buffers.
+
+2.  a "shape-only" tensor output value whose underlying elements are not used in
+    the payload computation and only serves the purpose of carrying shape
+    information to lower levels of abstraction. In the future this will be
+    replaced by an appropriate shape type when it is available as a builtin type
+    (see the discourse discussion
+    [Linalg and Shapes](https://llvm.discourse.group/t/linalg-and-shapes/2421)
+    for more details).
 
 ### Payload-Carrying Ops<a name="payload_ops"></a>
 
@@ -125,14 +142,15 @@ instance, it guarantees no out-of bounds access can occur by construction
 (assuming dynamic operand dimensions agree with each other, which is the purpose
 of the `assert` runtime check).
 
-Before lowering to loop form, loop induction variables and iterators are *not
-yet materialized*. This is a necessary property if we want an abstraction that
-works on both tensor values and buffers because ***values don’t escape
-loops/nesting***.
+Before lowering to loop form, loop induction variables and iterators are
+implicit (i.e. *not yet materialized*).
 
-The main implications are that: 1. The semantics of the ops are *restricted to
-operate on structured data types*, on which we can define an iterator. 2. This
-does not model arbitrary code with side-effects.
+The main implications are that:
+
+1.  The semantics of the ops are *restricted to operate on structured data
+    types*, on which we can define an iterator.
+
+2.  This does not model arbitrary code with side-effects.
 
 We do not think these are serious limitations in practice because MLIR is all
 about mixing different levels of abstractions in the same IR. As long as Linalg
@@ -483,76 +501,6 @@ because of empirical evidence building and working on multiple high-level
 compilers. As we lay those down and engage more with the community, we expect
 multiple rounds of discussions and design changes to the original architecture.
 
-### Tensors and Buffers: Conventions and Limitations <a name="tensors_and_buffers"></a>
-
-Tensors are immutable SSA values, buffers are mutable regions of memory subject
-to side-effects and aliasing. As a consequence, output buffers are passed as
-operands whereas output tensors are new SSA values corresponding to op results.
-Inputs can be arbitrary tensors or buffers and are always passed as operands.
-
-The following convention is currently in-flight and is in the process of
-replacing other existing conventions. The following convention currently applies
-to "named" structured ops which are auto-generated by the linalg-ods tool.
-
-The convention adopted is as follows:
-
-1.  A first block of `ins` op operands hold read-only inputs of ShapedType.
-2.  An optional second block of `outs` op operands hold read-write output
-    buffers of MemRefType.
-3.  An optional third block of `init` operands hold initialization tensors of
-    RankedTensorType. Such tensors can appear when the op performs a reduction
-    and returns a tensor.
-
-Structured ops with fully parallel semantics, have empty `init`. They may either
-write in-place into `outs` buffers or return new tensors.
-
-Structured ops with reduction semantics and output tensor(s) however have
-additional restrictions:
-
-1.  They can only return a single tensor for now.
-2.  They cannot have any output buffer operand (i.e. `outs` is empty).
-3.  They have exactly one `init` tensor of the same type as the unique output
-    tensor. Such an `init` tensor does not have an explicit associate indexing
-    map. Instead the map of the result tensor is used to signify that the `init`
-    and the `result` are "tied".
-
-Points 1. and 2. keep complexity of the representation in check by allowing only
-a single result tensor, when reductions are present.
-
-Point 3. is related to the fact that SSA values cannot represent in-place
-updates. Instead, linalg adopts a similar convention that exists in e.g.
-`vector.outerproduct`: the value that is reduced into is passed as an explicit
-argument and a new result of the same shape is produced.
-
-It is expected buffer allocation will fold this last input onto the result in a
-single output buffer argument, which is why the same indexing map is required:
-the last input operand is said to be "tied" to the result.
-
-Alternative, more complex representations, would allow for:
-
-1.  Multiple results and `init` tensors in arbitrary orders, which could be
-    captured by an extra ArrayAttr of position pairs.
-2.  Relaxing the conditions on the indexing map equalities on the each pair and
-    e.g. allow implicit broadcasts of the input.
-
-These representations are deemed unnecessarily complex for now and are left for
-future discussion.
-
-As an illustration, the syntax for a `linalg.matmul` writing into a buffer is:
-
-```
-linalg.matmul ins(%a, %b : memref<?x?xf32>, tensor<?x?xf32>)
-             outs(%c : memref<?x?xf32>)
-```
-
-, whereas the syntax for a `linalg.matmul` returning a new tensor is:
-
-```
-%d = linalg.matmul ins(%a, %b : tensor<?x?xf32>, memref<?x?xf32>)
-                  init(%c : tensor<?x?xf32>)
-                    -> tensor<?x?xf32>
-```
-
 ### Data Representation: Views<a name="views"></a>
 
 The current implementation uses the
diff --git a/mlir/docs/Dialects/SPIR-V.md b/mlir/docs/Dialects/SPIR-V.md
index f30d82fd28101..acace47c2c6f0 100644
--- a/mlir/docs/Dialects/SPIR-V.md
+++ b/mlir/docs/Dialects/SPIR-V.md
@@ -1145,7 +1145,7 @@ in a few places:
     are at [lib/Conversion/StandardToSPIRV][MlirStdToSpirvLibs].
 
 These dialect to dialect conversions have their dedicated libraries,
-`MLIRGPUToSPIRVTransforms` and `MLIRStandardToSPIRVTransforms`, respectively.
+`MLIRGPUToSPIRV` and `MLIRStandardToSPIRV`, respectively.
 
 There are also common utilities when targeting SPIR-V from any dialect:
 
diff --git a/mlir/docs/LLVMDialectMemRefConvention.md b/mlir/docs/LLVMDialectMemRefConvention.md
new file mode 100644
index 0000000000000..94ca718bd744a
--- /dev/null
+++ b/mlir/docs/LLVMDialectMemRefConvention.md
@@ -0,0 +1,439 @@
+# Built-in Function and MemRef Calling Convention
+
+This documents describes the calling convention implemented in the conversion of
+built-in [function operation](LangRef.md#functions), standard
+[`call`](Dialects/Standard.md#stdcall-callop) operations and the handling of
+[`memref`](LangRef.md#memref-type) type equivalents in the
+[LLVM dialect](Dialects/LLVM.md). The conversion assumes the _default_
+convention was used when converting
+[built-in to the LLVM dialect types](ConversionToLLVMDialect.md).
+
+## Function Result Packing
+
+In case of multi-result functions, the returned values are inserted into a
+structure-typed value before being returned and extracted from it at the call
+site. This transformation is a part of the conversion and is transparent to the
+defines and uses of the values being returned.
+
+Example:
+
+```mlir
+func @foo(%arg0: i32, %arg1: i64) -> (i32, i64) {
+  return %arg0, %arg1 : i32, i64
+}
+func @bar() {
+  %0 = constant 42 : i32
+  %1 = constant 17 : i64
+  %2:2 = call @foo(%0, %1) : (i32, i64) -> (i32, i64)
+  "use_i32"(%2#0) : (i32) -> ()
+  "use_i64"(%2#1) : (i64) -> ()
+}
+
+// is transformed into
+
+llvm.func @foo(%arg0: !llvm.i32, %arg1: !llvm.i64) -> !llvm.struct<(i32, i64)> {
+  // insert the vales into a structure
+  %0 = llvm.mlir.undef : !llvm.struct<(i32, i64)>
+  %1 = llvm.insertvalue %arg0, %0[0] : !llvm.struct<(i32, i64)>
+  %2 = llvm.insertvalue %arg1, %1[1] : !llvm.struct<(i32, i64)>
+
+  // return the structure value
+  llvm.return %2 : !llvm.struct<(i32, i64)>
+}
+llvm.func @bar() {
+  %0 = llvm.mlir.constant(42 : i32) : !llvm.i32
+  %1 = llvm.mlir.constant(17) : !llvm.i64
+
+  // call and extract the values from the structure
+  %2 = llvm.call @bar(%0, %1)
+     : (!llvm.i32, !llvm.i32) -> !llvm.struct<(i32, i64)>
+  %3 = llvm.extractvalue %2[0] : !llvm.struct<(i32, i64)>
+  %4 = llvm.extractvalue %2[1] : !llvm.struct<(i32, i64)>
+
+  // use as before
+  "use_i32"(%3) : (!llvm.i32) -> ()
+  "use_i64"(%4) : (!llvm.i64) -> ()
+}
+```
+
+## Calling Convention for Ranked `memref`
+
+Function _arguments_ of `memref` type, ranked or unranked, are _expanded_ into a
+list of arguments of non-aggregate types that the memref descriptor defined
+above comprises. That is, the outer struct type and the inner array types are
+replaced with individual arguments.
+
+This convention is implemented in the conversion of `std.func` and `std.call` to
+the LLVM dialect, with the former unpacking the descriptor into a set of
+individual values and the latter packing those values back into a descriptor so
+as to make it transparently usable by other operations. Conversions from other
+dialects should take this convention into account.
+
+This specific convention is motivated by the necessity to specify alignment and
+aliasing attributes on the raw pointers underpinning the memref.
+
+Examples:
+
+```mlir
+func @foo(%arg0: memref<?xf32>) -> () {
+  "use"(%arg0) : (memref<?xf32>) -> ()
+  return
+}
+
+// Gets converted to the following
+// (using type alias for brevity):
+!llvm.memref_1d = type !llvm.struct<(ptr<float>, ptr<float>, i64,
+                                     array<1xi64>, array<1xi64>)>
+
+llvm.func @foo(%arg0: !llvm.ptr<float>,  // Allocated pointer.
+               %arg1: !llvm.ptr<float>,  // Aligned pointer.
+               %arg2: !llvm.i64,         // Offset.
+               %arg3: !llvm.i64,         // Size in dim 0.
+               %arg4: !llvm.i64) {       // Stride in dim 0.
+  // Populate memref descriptor structure.
+  %0 = llvm.mlir.undef :
+  %1 = llvm.insertvalue %arg0, %0[0] : !llvm.memref_1d
+  %2 = llvm.insertvalue %arg1, %1[1] : !llvm.memref_1d
+  %3 = llvm.insertvalue %arg2, %2[2] : !llvm.memref_1d
+  %4 = llvm.insertvalue %arg3, %3[3, 0] : !llvm.memref_1d
+  %5 = llvm.insertvalue %arg4, %4[4, 0] : !llvm.memref_1d
+
+  // Descriptor is now usable as a single value.
+  "use"(%5) : (!llvm.memref_1d) -> ()
+  llvm.return
+}
+```
+
+```mlir
+func @bar() {
+  %0 = "get"() : () -> (memref<?xf32>)
+  call @foo(%0) : (memref<?xf32>) -> ()
+  return
+}
+
+// Gets converted to the following
+// (using type alias for brevity):
+!llvm.memref_1d = type !llvm.struct<(ptr<float>, ptr<float>, i64,
+                                     array<1xi64>, array<1xi64>)>
+
+llvm.func @bar() {
+  %0 = "get"() : () -> !llvm.memref_1d
+
+  // Unpack the memref descriptor.
+  %1 = llvm.extractvalue %0[0] : !llvm.memref_1d
+  %2 = llvm.extractvalue %0[1] : !llvm.memref_1d
+  %3 = llvm.extractvalue %0[2] : !llvm.memref_1d
+  %4 = llvm.extractvalue %0[3, 0] : !llvm.memref_1d
+  %5 = llvm.extractvalue %0[4, 0] : !llvm.memref_1d
+
+  // Pass individual values to the callee.
+  llvm.call @foo(%1, %2, %3, %4, %5) : (!llvm.memref_1d) -> ()
+  llvm.return
+}
+
+```
+
+## Calling Convention for Unranked `memref`
+
+For unranked memrefs, the list of function arguments always contains two
+elements, same as the unranked memref descriptor: an integer rank, and a
+type-erased (`!llvm<"i8*">`) pointer to the ranked memref descriptor. Note that
+while the _calling convention_ does not require stack allocation, _casting_ to
+unranked memref does since one cannot take an address of an SSA value containing
+the ranked memref. The caller is in charge of ensuring the thread safety and
+eventually removing unnecessary stack allocations in cast operations.
+
+Example
+
+```mlir
+llvm.func @foo(%arg0: memref<*xf32>) -> () {
+  "use"(%arg0) : (memref<*xf32>) -> ()
+  return
+}
+
+// Gets converted to the following.
+
+llvm.func @foo(%arg0: !llvm.i64        // Rank.
+               %arg1: !llvm.ptr<i8>) { // Type-erased pointer to descriptor.
+  // Pack the unranked memref descriptor.
+  %0 = llvm.mlir.undef : !llvm.struct<(i64, ptr<i8>)>
+  %1 = llvm.insertvalue %arg0, %0[0] : !llvm.struct<(i64, ptr<i8>)>
+  %2 = llvm.insertvalue %arg1, %1[1] : !llvm.struct<(i64, ptr<i8>)>
+
+  "use"(%2) : (!llvm.struct<(i64, ptr<i8>)>) -> ()
+  llvm.return
+}
+```
+
+```mlir
+llvm.func @bar() {
+  %0 = "get"() : () -> (memref<*xf32>)
+  call @foo(%0): (memref<*xf32>) -> ()
+  return
+}
+
+// Gets converted to the following.
+
+llvm.func @bar() {
+  %0 = "get"() : () -> (!llvm.struct<(i64, ptr<i8>)>)
+
+  // Unpack the memref descriptor.
+  %1 = llvm.extractvalue %0[0] : !llvm.struct<(i64, ptr<i8>)>
+  %2 = llvm.extractvalue %0[1] : !llvm.struct<(i64, ptr<i8>)>
+
+  // Pass individual values to the callee.
+  llvm.call @foo(%1, %2) : (!llvm.i64, !llvm.ptr<i8>)
+  llvm.return
+}
+```
+
+**Lifetime.** The second element of the unranked memref descriptor points to
+some memory in which the ranked memref descriptor is stored. By convention, this
+memory is allocated on stack and has the lifetime of the function. (*Note:* due
+to function-length lifetime, creation of multiple unranked memref descriptors,
+e.g., in a loop, may lead to stack overflows.) If an unranked descriptor has to
+be returned from a function, the ranked descriptor it points to is copied into
+dynamically allocated memory, and the pointer in the unranked descriptor is
+updated accordingly. The allocation happens immediately before returning. It is
+the responsibility of the caller to free the dynamically allocated memory. The
+default conversion of `std.call` and `std.call_indirect` copies the ranked
+descriptor to newly allocated memory on the caller's stack. Thus, the convention
+of the ranked memref descriptor pointed to by an unranked memref descriptor
+being stored on stack is respected.
+
+*This convention may or may not apply if the conversion of MemRef types is
+overridden by the user.*
+
+## C-compatible wrapper emission
+
+In practical cases, it may be desirable to have externally-facing functions with
+a single attribute corresponding to a MemRef argument. When interfacing with
+LLVM IR produced from C, the code needs to respect the corresponding calling
+convention. The conversion to the LLVM dialect provides an option to generate
+wrapper functions that take memref descriptors as pointers-to-struct compatible
+with data types produced by Clang when compiling C sources. The generation of
+such wrapper functions can additionally be controlled at a function granularity
+by setting the `llvm.emit_c_interface` unit attribute.
+
+More specifically, a memref argument is converted into a pointer-to-struct
+argument of type `{T*, T*, i64, i64[N], i64[N]}*` in the wrapper function, where
+`T` is the converted element type and `N` is the memref rank. This type is
+compatible with that produced by Clang for the following C++ structure template
+instantiations or their equivalents in C.
+
+```cpp
+template<typename T, size_t N>
+struct MemRefDescriptor {
+  T *allocated;
+  T *aligned;
+  intptr_t offset;
+  intptr_t sizes[N];
+  intptr_t strides[N];
+};
+```
+
+If enabled, the option will do the following. For _external_ functions declared
+in the MLIR module.
+
+1.  Declare a new function `_mlir_ciface_<original name>` where memref arguments
+    are converted to pointer-to-struct and the remaining arguments are converted
+    as usual.
+1.  Add a body to the original function (making it non-external) that
+    1.  allocates a memref descriptor,
+    1.  populates it, and
+    1.  passes the pointer to it into the newly declared interface function,
+        then
+    1.  collects the result of the call and returns it to the caller.
+
+For (non-external) functions defined in the MLIR module.
+
+1.  Define a new function `_mlir_ciface_<original name>` where memref arguments
+    are converted to pointer-to-struct and the remaining arguments are converted
+    as usual.
+1.  Populate the body of the newly defined function with IR that
+    1.  loads descriptors from pointers;
+    1.  unpacks descriptor into individual non-aggregate values;
+    1.  passes these values into the original function;
+    1.  collects the result of the call and returns it to the caller.
+
+Examples:
+
+```mlir
+
+func @qux(%arg0: memref<?x?xf32>)
+
+// Gets converted into the following
+// (using type alias for brevity):
+!llvm.memref_2d = type !llvm.struct<(ptr<float>, ptr<float>, i64,
+                                     array<2xi64>, array<2xi64>)>
+
+// Function with unpacked arguments.
+llvm.func @qux(%arg0: !llvm.ptr<float>, %arg1: !llvm.ptr<float>,
+               %arg2: !llvm.i64, %arg3: !llvm.i64, %arg4: !llvm.i64,
+               %arg5: !llvm.i64, %arg6: !llvm.i64) {
+  // Populate memref descriptor (as per calling convention).
+  %0 = llvm.mlir.undef : !llvm.memref_2d
+  %1 = llvm.insertvalue %arg0, %0[0] : !llvm.memref_2d
+  %2 = llvm.insertvalue %arg1, %1[1] : !llvm.memref_2d
+  %3 = llvm.insertvalue %arg2, %2[2] : !llvm.memref_2d
+  %4 = llvm.insertvalue %arg3, %3[3, 0] : !llvm.memref_2d
+  %5 = llvm.insertvalue %arg5, %4[4, 0] : !llvm.memref_2d
+  %6 = llvm.insertvalue %arg4, %5[3, 1] : !llvm.memref_2d
+  %7 = llvm.insertvalue %arg6, %6[4, 1] : !llvm.memref_2d
+
+  // Store the descriptor in a stack-allocated space.
+  %8 = llvm.mlir.constant(1 : index) : !llvm.i64
+  %9 = llvm.alloca %8 x !llvm.memref_2d
+     : (!llvm.i64) -> !llvm.ptr<struct<(ptr<float>, ptr<float>, i64,
+                                        array<2xi64>, array<2xi64>)>>
+  llvm.store %7, %9 : !llvm.ptr<struct<(ptr<float>, ptr<float>, i64,
+                                        array<2xi64>, array<2xi64>)>>
+
+  // Call the interface function.
+  llvm.call @_mlir_ciface_qux(%9)
+     : (!llvm.ptr<struct<(ptr<float>, ptr<float>, i64,
+                          array<2xi64>, array<2xi64>)>>) -> ()
+
+  // The stored descriptor will be freed on return.
+  llvm.return
+}
+
+// Interface function.
+llvm.func @_mlir_ciface_qux(!llvm.ptr<struct<(ptr<float>, ptr<float>, i64,
+                                              array<2xi64>, array<2xi64>)>>)
+```
+
+```mlir
+func @foo(%arg0: memref<?x?xf32>) {
+  return
+}
+
+// Gets converted into the following
+// (using type alias for brevity):
+!llvm.memref_2d = type !llvm.struct<(ptr<float>, ptr<float>, i64,
+                                     array<2xi64>, array<2xi64>)>
+!llvm.memref_2d_ptr = type !llvm.ptr<struct<(ptr<float>, ptr<float>, i64,
+                                             array<2xi64>, array<2xi64>)>>
+
+// Function with unpacked arguments.
+llvm.func @foo(%arg0: !llvm.ptr<float>, %arg1: !llvm.ptr<float>,
+               %arg2: !llvm.i64, %arg3: !llvm.i64, %arg4: !llvm.i64,
+               %arg5: !llvm.i64, %arg6: !llvm.i64) {
+  llvm.return
+}
+
+// Interface function callable from C.
+llvm.func @_mlir_ciface_foo(%arg0: !llvm.memref_2d_ptr) {
+  // Load the descriptor.
+  %0 = llvm.load %arg0 : !llvm.memref_2d_ptr
+
+  // Unpack the descriptor as per calling convention.
+  %1 = llvm.extractvalue %0[0] : !llvm.memref_2d
+  %2 = llvm.extractvalue %0[1] : !llvm.memref_2d
+  %3 = llvm.extractvalue %0[2] : !llvm.memref_2d
+  %4 = llvm.extractvalue %0[3, 0] : !llvm.memref_2d
+  %5 = llvm.extractvalue %0[3, 1] : !llvm.memref_2d
+  %6 = llvm.extractvalue %0[4, 0] : !llvm.memref_2d
+  %7 = llvm.extractvalue %0[4, 1] : !llvm.memref_2d
+  llvm.call @foo(%1, %2, %3, %4, %5, %6, %7)
+    : (!llvm.ptr<float>, !llvm.ptr<float>, !llvm.i64, !llvm.i64, !llvm.i64,
+       !llvm.i64, !llvm.i64) -> ()
+  llvm.return
+}
+```
+
+Rationale: Introducing auxiliary functions for C-compatible interfaces is
+preferred to modifying the calling convention since it will minimize the effect
+of C compatibility on intra-module calls or calls between MLIR-generated
+functions. In particular, when calling external functions from an MLIR module in
+a (parallel) loop, the fact of storing a memref descriptor on stack can lead to
+stack exhaustion and/or concurrent access to the same address. Auxiliary
+interface function serves as an allocation scope in this case. Furthermore, when
+targeting accelerators with separate memory spaces such as GPUs, stack-allocated
+descriptors passed by pointer would have to be transferred to the device memory,
+which introduces significant overhead. In such situations, auxiliary interface
+functions are executed on host and only pass the values through device function
+invocation mechanism.
+
+## Default Memref Model
+
+### Memref Descriptor
+
+Within a converted function, a `memref`-typed value is represented by a memref
+_descriptor_, the type of which is the structure type obtained by converting
+from the memref type. This descriptor holds all the necessary information to
+produce an address of a specific element. In particular, it holds dynamic values
+for static sizes, and they are expected to match at all times.
+
+It is created by the allocation operation and is updated by the conversion
+operations that may change static dimensions into dynamic dimensions and vice
+versa.
+
+**Note**: LLVM IR conversion does not support `memref`s with layouts that are
+not amenable to the strided form.
+
+### Index Linearization
+
+Accesses to a memref element are transformed into an access to an element of the
+buffer pointed to by the descriptor. The position of the element in the buffer
+is calculated by linearizing memref indices in row-major order (lexically first
+index is the slowest varying, similar to C, but accounting for strides). The
+computation of the linear address is emitted as arithmetic operation in the LLVM
+IR dialect. Strides are extracted from the memref descriptor.
+
+Examples:
+
+An access to a memref with indices:
+
+```mlir
+%0 = load %m[%1,%2,%3,%4] : memref<?x?x4x8xf32, offset: ?>
+```
+
+is transformed into the equivalent of the following code:
+
+```mlir
+// Compute the linearized index from strides.
+// When strides or, in absence of explicit strides, the corresponding sizes are
+// dynamic, extract the stride value from the descriptor.
+%stride1 = llvm.extractvalue[4, 0] : !llvm.struct<(ptr<float>, ptr<float>, i64,
+                                                   array<4xi64>, array<4xi64>)>
+%addr1 = muli %stride1, %1 : !llvm.i64
+
+// When the stride or, in absence of explicit strides, the trailing sizes are
+// known statically, this value is used as a constant. The natural value of
+// strides is the product of all sizes following the current dimension.
+%stride2 = llvm.mlir.constant(32 : index) : !llvm.i64
+%addr2 = muli %stride2, %2 : !llvm.i64
+%addr3 = addi %addr1, %addr2 : !llvm.i64
+
+%stride3 = llvm.mlir.constant(8 : index) : !llvm.i64
+%addr4 = muli %stride3, %3 : !llvm.i64
+%addr5 = addi %addr3, %addr4 : !llvm.i64
+
+// Multiplication with the known unit stride can be omitted.
+%addr6 = addi %addr5, %4 : !llvm.i64
+
+// If the linear offset is known to be zero, it can also be omitted. If it is
+// dynamic, it is extracted from the descriptor.
+%offset = llvm.extractvalue[2] : !llvm.struct<(ptr<float>, ptr<float>, i64,
+                                               array<4xi64>, array<4xi64>)>
+%addr7 = addi %addr6, %offset : !llvm.i64
+
+// All accesses are based on the aligned pointer.
+%aligned = llvm.extractvalue[1] : !llvm.struct<(ptr<float>, ptr<float>, i64,
+                                                array<4xi64>, array<4xi64>)>
+
+// Get the address of the data pointer.
+%ptr = llvm.getelementptr %aligned[%addr8]
+     : !llvm.struct<(ptr<float>, ptr<float>, i64, array<4xi64>, array<4xi64>)>
+     -> !llvm.ptr<float>
+
+// Perform the actual load.
+%0 = llvm.load %ptr : !llvm.ptr<float>
+```
+
+For stores, the address computation code is identical and only the actual store
+operation is different.
+
+Note: the conversion does not perform any sort of common subexpression
+elimination when emitting memref accesses.
diff --git a/mlir/docs/Passes.md b/mlir/docs/Passes.md
index c7ac56f84ea9f..fdf2893e880ab 100644
--- a/mlir/docs/Passes.md
+++ b/mlir/docs/Passes.md
@@ -56,6 +56,10 @@ This document describes the available MLIR passes and their contracts.
 
 [include "StandardPasses.md"]
 
+## `tensor` Dialect Passes
+
+[include "TensorPasses.md"]
+
 ## TOSA Dialect Passes
 
 [include "TosaPasses.md"]
diff --git a/mlir/docs/PatternRewriter.md b/mlir/docs/PatternRewriter.md
index ab93245395a34..fba5a9b8eac19 100644
--- a/mlir/docs/PatternRewriter.md
+++ b/mlir/docs/PatternRewriter.md
@@ -238,7 +238,7 @@ between, and within dialects using a concept of "legality". This framework
 allows for transforming illegal operations to those supported by a provided
 conversion target, via a set of pattern-based operation rewriting patterns. This
 framework also provides support for type conversions. More information on this
-driver can be found [here](DialectConversion.nd).
+driver can be found [here](DialectConversion.md).
 
 ### Greedy Pattern Rewrite Driver
 
diff --git a/mlir/docs/SPIRVToLLVMDialectConversion.md b/mlir/docs/SPIRVToLLVMDialectConversion.md
index 3aa4d0fa43a19..bdae08c1e230f 100644
--- a/mlir/docs/SPIRVToLLVMDialectConversion.md
+++ b/mlir/docs/SPIRVToLLVMDialectConversion.md
@@ -377,7 +377,7 @@ entry points in LLVM. At the moment, we use the following approach:
   entry point. For example, `LocalSize` provides information about the
   work-group size that can be reused.
 
-  In order to preserve this inforamtion, `spv.ExecutionMode` is converted to
+  In order to preserve this information, `spv.ExecutionMode` is converted to
   a struct global variable that stores the execution mode id and any variables
   associated with it. In C, the struct has the structure shown below.
 
@@ -816,7 +816,140 @@ to LLVM ops. At the moment, SPIR-V module attributes are ignored.
 
 ## `mlir-spirv-cpu-runner`
 
-**Note: this is a section in progress, more information will appear soon**
+`mlir-spirv-cpu-runner` allows to execute `gpu` dialect kernel on the CPU via
+SPIR-V to LLVM dialect conversion. Currently, only single-threaded kernel is
+supported.
+
+To build the runner, add the following option to `cmake`:
+```bash
+-DMLIR_SPIRV_CPU_RUNNER_ENABLED=1
+```
+
+### Pipeline
+
+The `gpu` module with the kernel and the host code undergo the following
+transformations:
+
+*   Convert the `gpu` module into SPIR-V dialect, lower ABI attributes and
+    update version, capability and extension.
+
+*   Emulate the kernel call by converting the launching operation into a normal
+    function call. The data from the host side to the device is passed via
+    copying to global variables. These are created in both the host and the
+    kernel code and later linked when nested modules are folded.
+
+*   Convert SPIR-V dialect kernel to LLVM dialect via the new conversion path.
+
+After these passes, the IR transforms into a nested LLVM module - a main module
+representing the host code and a kernel module. These modules are linked and
+executed using `ExecutionEngine`.
+
+### Walk-through
+
+This section gives a detailed overview of the IR changes while running
+`mlir-spirv-cpu-runner`. First, consider that we have the following IR. (For
+simplicity some type annotations and function implementations have been
+omitted).
+
+```mlir
+gpu.module @foo {
+  gpu.func @bar(%arg: memref<8xi32>) {
+    // Kernel code.
+    gpu.return
+  }
+}
+
+func @main() {
+  // Fill the buffer with some data
+  %buffer = alloc : memref<8xi32>
+  %data = ...
+  call fillBuffer(%buffer, %data)
+
+  "gpu.launch_func"(/*grid dimensions*/, %buffer) {
+    kernel = @foo::bar
+  }
+}
+```
+
+Lowering `gpu` dialect to SPIR-V dialect results in
+
+```mlir
+spv.module @__spv__foo /*VCE triple and other metadata here*/ {
+  spv.globalVariable @__spv__foo_arg bind(0,0) : ...
+  spv.func @bar() {
+    // Kernel code.
+  }
+  spv.EntryPoint @bar, ...
+}
+
+func @main() {
+  // Fill the buffer with some data.
+  %buffer = alloc : memref<8xi32>
+  %data = ...
+  call fillBuffer(%buffer, %data)
+
+  "gpu.launch_func"(/*grid dimensions*/, %buffer) {
+    kernel = @foo::bar
+  }
+}
+```
+
+Then, the lowering from standard dialect to LLVM dialect is applied to the host
+code.
+
+```mlir
+spv.module @__spv__foo /*VCE triple and other metadata here*/ {
+  spv.globalVariable @__spv__foo_arg bind(0,0) : ...
+  spv.func @bar() {
+    // Kernel code.
+  }
+  spv.EntryPoint @bar, ...
+}
+
+// Kernel function declaration.
+llvm.func @__spv__foo_bar() : ...
+
+llvm.func @main() {
+  // Fill the buffer with some data.
+  llvm.call fillBuffer(%buffer, %data)
+
+  // Copy data to the global variable, call kernel, and copy the data back.
+  %addr = llvm.mlir.addressof @__spv__foo_arg_descriptor_set0_binding0 : ...
+  "llvm.intr.memcpy"(%addr, %buffer) : ...
+  llvm.call @__spv__foo_bar()
+  "llvm.intr.memcpy"(%buffer, %addr) : ...
+
+  llvm.return
+}
+```
+
+Finally, SPIR-V module is converted to LLVM and the symbol names are resolved
+for the linkage.
+
+```mlir
+module @__spv__foo {
+  llvm.mlir.global @__spv__foo_arg_descriptor_set0_binding0 : ...
+  llvm.func @__spv__foo_bar() {
+    // Kernel code.
+  }
+}
+
+// Kernel function declaration.
+llvm.func @__spv__foo_bar() : ...
+
+llvm.func @main() {
+  // Fill the buffer with some data.
+  llvm.call fillBuffer(%buffer, %data)
+
+  // Copy data to the global variable, call kernel, and copy the data back.
+  %addr = llvm.mlir.addressof @__spv__foo_arg_descriptor_set0_binding0 : ...
+  "llvm.intr.memcpy"(%addr, %buffer) : ...
+  llvm.call @__spv__foo_bar()
+  "llvm.intr.memcpy"(%buffer, %addr) : ...
+
+  llvm.return
+}
+```
 
 [LLVMFunctionAttributes]: https://llvm.org/docs/LangRef.html#function-attributes
 [SPIRVFunctionAttributes]: https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html#_a_id_function_control_a_function_control
diff --git a/mlir/docs/Tutorials/Toy/Ch-2.md b/mlir/docs/Tutorials/Toy/Ch-2.md
index be76dc3519129..6c9b93ae40660 100644
--- a/mlir/docs/Tutorials/Toy/Ch-2.md
+++ b/mlir/docs/Tutorials/Toy/Ch-2.md
@@ -210,7 +210,9 @@ class ConstantOp : public mlir::Op<ConstantOp,
                      /// The ConstantOp takes no inputs.
                      mlir::OpTrait::ZeroOperands,
                      /// The ConstantOp returns a single result.
-                     mlir::OpTrait::OneResult> {
+                     mlir::OpTrait::OneResult,
+                     /// The result of getType is `Type`.
+                     mlir::OpTraits::OneTypedResult<Type>::Impl> {
 
  public:
   /// Inherit the constructors from the base Op class.
diff --git a/mlir/examples/standalone/include/Standalone/StandaloneOps.h b/mlir/examples/standalone/include/Standalone/StandaloneOps.h
index 5a8c5d1040e62..a56c2867b1c8b 100644
--- a/mlir/examples/standalone/include/Standalone/StandaloneOps.h
+++ b/mlir/examples/standalone/include/Standalone/StandaloneOps.h
@@ -9,6 +9,7 @@
 #ifndef STANDALONE_STANDALONEOPS_H
 #define STANDALONE_STANDALONEOPS_H
 
+#include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Dialect.h"
 #include "mlir/IR/OpDefinition.h"
 #include "mlir/Interfaces/SideEffectInterfaces.h"
diff --git a/mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp b/mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
index a04b3ecd4daee..6fbf29f4128d7 100644
--- a/mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
+++ b/mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp
@@ -111,10 +111,11 @@ class PrintOpLowering : public ConversionPattern {
 
     // Create a function declaration for printf, the signature is:
     //   * `i32 (i8*, ...)`
-    auto llvmI32Ty = LLVM::LLVMType::getInt32Ty(context);
-    auto llvmI8PtrTy = LLVM::LLVMType::getInt8PtrTy(context);
-    auto llvmFnType = LLVM::LLVMType::getFunctionTy(llvmI32Ty, llvmI8PtrTy,
-                                                    /*isVarArg=*/true);
+    auto llvmI32Ty = LLVM::LLVMIntegerType::get(context, 32);
+    auto llvmI8PtrTy =
+        LLVM::LLVMPointerType::get(LLVM::LLVMIntegerType::get(context, 8));
+    auto llvmFnType = LLVM::LLVMFunctionType::get(llvmI32Ty, llvmI8PtrTy,
+                                                  /*isVarArg=*/true);
 
     // Insert the printf function into the body of the parent module.
     PatternRewriter::InsertionGuard insertGuard(rewriter);
@@ -133,8 +134,8 @@ class PrintOpLowering : public ConversionPattern {
     if (!(global = module.lookupSymbol<LLVM::GlobalOp>(name))) {
       OpBuilder::InsertionGuard insertGuard(builder);
       builder.setInsertionPointToStart(module.getBody());
-      auto type = LLVM::LLVMType::getArrayTy(
-          LLVM::LLVMType::getInt8Ty(builder.getContext()), value.size());
+      auto type = LLVM::LLVMArrayType::get(
+          LLVM::LLVMIntegerType::get(builder.getContext(), 8), value.size());
       global = builder.create<LLVM::GlobalOp>(loc, type, /*isConstant=*/true,
                                               LLVM::Linkage::Internal, name,
                                               builder.getStringAttr(value));
@@ -143,11 +144,13 @@ class PrintOpLowering : public ConversionPattern {
     // Get the pointer to the first character in the global string.
     Value globalPtr = builder.create<LLVM::AddressOfOp>(loc, global);
     Value cst0 = builder.create<LLVM::ConstantOp>(
-        loc, LLVM::LLVMType::getInt64Ty(builder.getContext()),
+        loc, LLVM::LLVMIntegerType::get(builder.getContext(), 64),
         builder.getIntegerAttr(builder.getIndexType(), 0));
     return builder.create<LLVM::GEPOp>(
-        loc, LLVM::LLVMType::getInt8PtrTy(builder.getContext()), globalPtr,
-        ArrayRef<Value>({cst0, cst0}));
+        loc,
+        LLVM::LLVMPointerType::get(
+            LLVM::LLVMIntegerType::get(builder.getContext(), 8)),
+        globalPtr, ArrayRef<Value>({cst0, cst0}));
   }
 };
 } // end anonymous namespace
diff --git a/mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp b/mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
index a04b3ecd4daee..6fbf29f4128d7 100644
--- a/mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
+++ b/mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp
@@ -111,10 +111,11 @@ class PrintOpLowering : public ConversionPattern {
 
     // Create a function declaration for printf, the signature is:
     //   * `i32 (i8*, ...)`
-    auto llvmI32Ty = LLVM::LLVMType::getInt32Ty(context);
-    auto llvmI8PtrTy = LLVM::LLVMType::getInt8PtrTy(context);
-    auto llvmFnType = LLVM::LLVMType::getFunctionTy(llvmI32Ty, llvmI8PtrTy,
-                                                    /*isVarArg=*/true);
+    auto llvmI32Ty = LLVM::LLVMIntegerType::get(context, 32);
+    auto llvmI8PtrTy =
+        LLVM::LLVMPointerType::get(LLVM::LLVMIntegerType::get(context, 8));
+    auto llvmFnType = LLVM::LLVMFunctionType::get(llvmI32Ty, llvmI8PtrTy,
+                                                  /*isVarArg=*/true);
 
     // Insert the printf function into the body of the parent module.
     PatternRewriter::InsertionGuard insertGuard(rewriter);
@@ -133,8 +134,8 @@ class PrintOpLowering : public ConversionPattern {
     if (!(global = module.lookupSymbol<LLVM::GlobalOp>(name))) {
       OpBuilder::InsertionGuard insertGuard(builder);
       builder.setInsertionPointToStart(module.getBody());
-      auto type = LLVM::LLVMType::getArrayTy(
-          LLVM::LLVMType::getInt8Ty(builder.getContext()), value.size());
+      auto type = LLVM::LLVMArrayType::get(
+          LLVM::LLVMIntegerType::get(builder.getContext(), 8), value.size());
       global = builder.create<LLVM::GlobalOp>(loc, type, /*isConstant=*/true,
                                               LLVM::Linkage::Internal, name,
                                               builder.getStringAttr(value));
@@ -143,11 +144,13 @@ class PrintOpLowering : public ConversionPattern {
     // Get the pointer to the first character in the global string.
     Value globalPtr = builder.create<LLVM::AddressOfOp>(loc, global);
     Value cst0 = builder.create<LLVM::ConstantOp>(
-        loc, LLVM::LLVMType::getInt64Ty(builder.getContext()),
+        loc, LLVM::LLVMIntegerType::get(builder.getContext(), 64),
         builder.getIntegerAttr(builder.getIndexType(), 0));
     return builder.create<LLVM::GEPOp>(
-        loc, LLVM::LLVMType::getInt8PtrTy(builder.getContext()), globalPtr,
-        ArrayRef<Value>({cst0, cst0}));
+        loc,
+        LLVM::LLVMPointerType::get(
+            LLVM::LLVMIntegerType::get(builder.getContext(), 8)),
+        globalPtr, ArrayRef<Value>({cst0, cst0}));
   }
 };
 } // end anonymous namespace
diff --git a/mlir/include/mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.h b/mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h
similarity index 73%
rename from mlir/include/mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.h
rename to mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h
index 8bdb228c9ccce..ad5dac0038972 100644
--- a/mlir/include/mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.h
+++ b/mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h
@@ -1,4 +1,4 @@
-//===- ConvertGPUToSPIRV.h - GPU Ops to SPIR-V dialect patterns ----C++ -*-===//
+//===- GPUToSPIRV.h - GPU to SPIR-V Patterns --------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,12 +6,12 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Provides patterns for lowering GPU Ops to SPIR-V dialect.
+// Provides patterns to convert GPU dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_CONVERSION_GPUTOSPIRV_CONVERTGPUTOSPIRV_H
-#define MLIR_CONVERSION_GPUTOSPIRV_CONVERTGPUTOSPIRV_H
+#ifndef MLIR_CONVERSION_GPUTOSPIRV_GPUTOSPIRV_H
+#define MLIR_CONVERSION_GPUTOSPIRV_GPUTOSPIRV_H
 
 #include "mlir/Transforms/DialectConversion.h"
 
@@ -26,4 +26,4 @@ void populateGPUToSPIRVPatterns(MLIRContext *context,
                                 OwningRewritePatternList &patterns);
 } // namespace mlir
 
-#endif // MLIR_CONVERSION_GPUTOSPIRV_CONVERTGPUTOSPIRV_H
+#endif // MLIR_CONVERSION_GPUTOSPIRV_GPUTOSPIRV_H
diff --git a/mlir/include/mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h b/mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRVPass.h
similarity index 52%
rename from mlir/include/mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h
rename to mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRVPass.h
index f22db8477d848..dba8d274c7a92 100644
--- a/mlir/include/mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h
+++ b/mlir/include/mlir/Conversion/GPUToSPIRV/GPUToSPIRVPass.h
@@ -1,4 +1,4 @@
-//===- ConvertGPUToSPIRVPass.h - GPU to SPIR-V conversion pass --*- C++ -*-===//
+//===- GPUToSPIRVPass.h - GPU to SPIR-V Passes ------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,25 +6,24 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Provides a pass to convert GPU ops to SPIRV ops.
+// Provides passes to convert GPU dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_CONVERSION_GPUTOSPIRV_CONVERTGPUTOSPIRVPASS_H
-#define MLIR_CONVERSION_GPUTOSPIRV_CONVERTGPUTOSPIRVPASS_H
-
-#include "mlir/Support/LLVM.h"
+#ifndef MLIR_CONVERSION_GPUTOSPIRV_GPUTOSPIRVPASS_H
+#define MLIR_CONVERSION_GPUTOSPIRV_GPUTOSPIRVPASS_H
 
 #include <memory>
 
 namespace mlir {
 
 class ModuleOp;
-template <typename T> class OperationPass;
+template <typename T>
+class OperationPass;
 
-/// Pass to convert GPU Ops to SPIR-V ops. For a gpu.func to be converted, it
-/// should have a spv.entry_point_abi attribute.
+/// Creates a pass to convert GPU Ops to SPIR-V ops. For a gpu.func to be
+/// converted, it should have a spv.entry_point_abi attribute.
 std::unique_ptr<OperationPass<ModuleOp>> createConvertGPUToSPIRVPass();
 
 } // namespace mlir
-#endif // MLIR_CONVERSION_GPUTOSPIRV_CONVERTGPUTOSPIRVPASS_H
+#endif // MLIR_CONVERSION_GPUTOSPIRV_GPUTOSPIRVPASS_H
diff --git a/mlir/include/mlir/Conversion/LinalgToSPIRV/LinalgToSPIRV.h b/mlir/include/mlir/Conversion/LinalgToSPIRV/LinalgToSPIRV.h
index a37048ad258d1..b2fc9e4e91385 100644
--- a/mlir/include/mlir/Conversion/LinalgToSPIRV/LinalgToSPIRV.h
+++ b/mlir/include/mlir/Conversion/LinalgToSPIRV/LinalgToSPIRV.h
@@ -1,4 +1,4 @@
-//===- LinalgToSPIRV.h - Linalg to SPIR-V dialect conversion ----*- C++ -*-===//
+//===- LinalgToSPIRV.h - Linalg to SPIR-V Patterns --------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file provides patterns for Linalg to SPIR-V dialect conversion.
+// Provides patterns to convert Linalg dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
diff --git a/mlir/include/mlir/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h b/mlir/include/mlir/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h
index 9b10b4b705d5d..b758b87c80afb 100644
--- a/mlir/include/mlir/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h
+++ b/mlir/include/mlir/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h
@@ -1,4 +1,4 @@
-//===- LinalgToSPIRVPass.h -  Linalg to SPIR-V conversion pass --*- C++ -*-===//
+//===- LinalgToSPIRVPass.h -  Linalg to SPIR-V Passes -----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file provides a pass for Linalg to SPIR-V dialect conversion.
+// Provides passes to convert Linalg dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
diff --git a/mlir/include/mlir/Conversion/Passes.h b/mlir/include/mlir/Conversion/Passes.h
index cc4f59c12496d..64b99d33ab61f 100644
--- a/mlir/include/mlir/Conversion/Passes.h
+++ b/mlir/include/mlir/Conversion/Passes.h
@@ -14,7 +14,7 @@
 #include "mlir/Conversion/GPUCommon/GPUCommonPass.h"
 #include "mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h"
 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h"
-#include "mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h"
+#include "mlir/Conversion/GPUToSPIRV/GPUToSPIRVPass.h"
 #include "mlir/Conversion/GPUToVulkan/ConvertGPUToVulkanPass.h"
 #include "mlir/Conversion/LinalgToLLVM/LinalgToLLVM.h"
 #include "mlir/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h"
@@ -23,15 +23,16 @@
 #include "mlir/Conversion/PDLToPDLInterp/PDLToPDLInterp.h"
 #include "mlir/Conversion/SCFToGPU/SCFToGPUPass.h"
 #include "mlir/Conversion/SCFToOpenMP/SCFToOpenMP.h"
+#include "mlir/Conversion/SCFToSPIRV/SCFToSPIRVPass.h"
 #include "mlir/Conversion/SCFToStandard/SCFToStandard.h"
-#include "mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h"
+#include "mlir/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.h"
 #include "mlir/Conversion/ShapeToStandard/ShapeToStandard.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
-#include "mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.h"
+#include "mlir/Conversion/StandardToSPIRV/StandardToSPIRVPass.h"
 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h"
 #include "mlir/Conversion/VectorToROCDL/VectorToROCDL.h"
 #include "mlir/Conversion/VectorToSCF/VectorToSCF.h"
-#include "mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRVPass.h"
+#include "mlir/Conversion/VectorToSPIRV/VectorToSPIRVPass.h"
 
 namespace mlir {
 
diff --git a/mlir/include/mlir/Conversion/Passes.td b/mlir/include/mlir/Conversion/Passes.td
index b364700bd849f..2dc438534a448 100644
--- a/mlir/include/mlir/Conversion/Passes.td
+++ b/mlir/include/mlir/Conversion/Passes.td
@@ -230,6 +230,23 @@ def ConvertSCFToOpenMP : FunctionPass<"convert-scf-to-openmp"> {
   let dependentDialects = ["omp::OpenMPDialect"];
 }
 
+//===----------------------------------------------------------------------===//
+// SCFToSPIRV
+//===----------------------------------------------------------------------===//
+
+def SCFToSPIRV : Pass<"convert-scf-to-spirv", "ModuleOp"> {
+  let summary = "Convert SCF dialect to SPIR-V dialect.";
+  let description = [{
+    This pass converts SCF ops into SPIR-V structured control flow ops.
+    SPIR-V structured control flow ops does not support yielding values.
+    So for SCF ops yielding values, SPIR-V variables are created for
+    holding the values and load/store operations are emitted for updating
+    them.
+  }];
+  let constructor = "mlir::createConvertSCFToSPIRVPass()";
+  let dependentDialects = ["spirv::SPIRVDialect"];
+}
+
 //===----------------------------------------------------------------------===//
 // SCFToStandard
 //===----------------------------------------------------------------------===//
diff --git a/mlir/include/mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h b/mlir/include/mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h
index 59fa0082e0cff..e0bab2759753b 100644
--- a/mlir/include/mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h
+++ b/mlir/include/mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h
@@ -1,4 +1,4 @@
-//===------------ SCFToSPIRV.h - Pass entrypoint ----------------*- C++ -*-===//
+//===- SCFToSPIRV.h - SCF to SPIR-V Patterns --------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Provides patterns for lowering SCF ops to SPIR-V dialect.
+// Provides patterns to convert SCF dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 #ifndef MLIR_CONVERSION_SCFTOSPIRV_SCFTOSPIRV_H_
diff --git a/mlir/include/mlir/Conversion/SCFToSPIRV/SCFToSPIRVPass.h b/mlir/include/mlir/Conversion/SCFToSPIRV/SCFToSPIRVPass.h
new file mode 100644
index 0000000000000..5e35d6267086e
--- /dev/null
+++ b/mlir/include/mlir/Conversion/SCFToSPIRV/SCFToSPIRVPass.h
@@ -0,0 +1,25 @@
+//===- SCFToSPIRVPass.h - SCF to SPIR-V Passes ------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Provides passes to convert SCF dialect to SPIR-V dialect.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_CONVERSION_SCFTOSPIRV_SCFTOSPIRVPASS_H
+#define MLIR_CONVERSION_SCFTOSPIRV_SCFTOSPIRVPASS_H
+
+#include "mlir/Pass/Pass.h"
+
+namespace mlir {
+
+/// Creates a pass to convert SCF ops into SPIR-V ops.
+std::unique_ptr<OperationPass<ModuleOp>> createConvertSCFToSPIRVPass();
+
+} // namespace mlir
+
+#endif // MLIR_CONVERSION_SCFTOSPIRV_SCFTOSPIRVPASS_H
diff --git a/mlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h b/mlir/include/mlir/Conversion/SPIRVToLLVM/SPIRVToLLVM.h
similarity index 89%
rename from mlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h
rename to mlir/include/mlir/Conversion/SPIRVToLLVM/SPIRVToLLVM.h
index dd9fb68fa80be..3ba24eaac1a0d 100644
--- a/mlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h
+++ b/mlir/include/mlir/Conversion/SPIRVToLLVM/SPIRVToLLVM.h
@@ -1,4 +1,4 @@
-//===- ConvertSPIRVToLLVM.h - Convert SPIR-V to LLVM dialect ----*- C++ -*-===//
+//===- SPIRVToLLVM.h - SPIR-V to LLVM Patterns ------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -10,8 +10,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_CONVERSION_SPIRVTOLLVM_CONVERTSPIRVTOLLVM_H
-#define MLIR_CONVERSION_SPIRVTOLLVM_CONVERTSPIRVTOLLVM_H
+#ifndef MLIR_CONVERSION_SPIRVTOLLVM_SPIRVTOLLVM_H
+#define MLIR_CONVERSION_SPIRVTOLLVM_SPIRVTOLLVM_H
 
 #include "mlir/Transforms/DialectConversion.h"
 
@@ -57,4 +57,4 @@ void populateSPIRVToLLVMModuleConversionPatterns(
 
 } // namespace mlir
 
-#endif // MLIR_CONVERSION_SPIRVTOLLVM_CONVERTSPIRVTOLLVM_H
+#endif // MLIR_CONVERSION_SPIRVTOLLVM_SPIRVTOLLVM_H
diff --git a/mlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h b/mlir/include/mlir/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.h
similarity index 78%
rename from mlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h
rename to mlir/include/mlir/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.h
index 9525a1eac9845..bc70736c7d3bd 100644
--- a/mlir/include/mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h
+++ b/mlir/include/mlir/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.h
@@ -1,4 +1,4 @@
-//===- ConvertSPIRVToLLVMPass.h - SPIR-V dialect to LLVM pass ---*- C++ -*-===//
+//===- SPIRVToLLVMPass.h - SPIR-V to LLVM Passes ----------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,12 +6,12 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Provides a pass to lower from SPIR-V dialect to LLVM dialect.
+// Provides passes to convert SPIR-V dialect to LLVM dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_CONVERSION_SPIRVTOLLVM_CONVERTSPIRVTOLLVMPASS_H
-#define MLIR_CONVERSION_SPIRVTOLLVM_CONVERTSPIRVTOLLVMPASS_H
+#ifndef MLIR_CONVERSION_SPIRVTOLLVM_SPIRVTOLLVMPASS_H
+#define MLIR_CONVERSION_SPIRVTOLLVM_SPIRVTOLLVMPASS_H
 
 #include <memory>
 
@@ -35,4 +35,4 @@ std::unique_ptr<OperationPass<ModuleOp>> createConvertSPIRVToLLVMPass();
 
 } // namespace mlir
 
-#endif // MLIR_CONVERSION_SPIRVTOLLVM_CONVERTSPIRVTOLLVMPASS_H_
+#endif // MLIR_CONVERSION_SPIRVTOLLVM_SPIRVTOLLVMPASS_H
diff --git a/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h b/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
index 7c069c9cd5566..d5c1e923fab98 100644
--- a/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
+++ b/mlir/include/mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h
@@ -446,7 +446,8 @@ class UnrankedMemRefDescriptor : public StructBuilder {
   /// Builds IR extracting the pointer to the first element of the size array.
   static Value sizeBasePtr(OpBuilder &builder, Location loc,
                            LLVMTypeConverter &typeConverter,
-                           Value memRefDescPtr, LLVM::LLVMType elemPtrPtrType);
+                           Value memRefDescPtr,
+                           LLVM::LLVMPointerType elemPtrPtrType);
   /// Builds IR extracting the size[index] from the descriptor.
   static Value size(OpBuilder &builder, Location loc,
                     LLVMTypeConverter typeConverter, Value sizeBasePtr,
@@ -511,13 +512,9 @@ class ConvertToLLVMPattern : public ConversionPattern {
                              ValueRange indices,
                              ConversionPatternRewriter &rewriter) const;
 
-  // Forwards to getStridedElementPtr. TODO: remove.
-  Value getDataPtr(Location loc, MemRefType type, Value memRefDesc,
-                   ValueRange indices,
-                   ConversionPatternRewriter &rewriter) const;
-
-  /// Returns if the givem memref type is supported.
-  bool isSupportedMemRefType(MemRefType type) const;
+  /// Returns if the given memref has identity maps and the element type is
+  /// convertible to LLVM.
+  bool isConvertibleAndHasIdentityMaps(MemRefType type) const;
 
   /// Returns the type of a pointer to an element of the memref.
   Type getElementPtrType(MemRefType type) const;
diff --git a/mlir/include/mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.h b/mlir/include/mlir/Conversion/StandardToSPIRV/StandardToSPIRV.h
similarity index 68%
rename from mlir/include/mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.h
rename to mlir/include/mlir/Conversion/StandardToSPIRV/StandardToSPIRV.h
index 6e19358e2f4e7..6cea1999f368c 100644
--- a/mlir/include/mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.h
+++ b/mlir/include/mlir/Conversion/StandardToSPIRV/StandardToSPIRV.h
@@ -1,4 +1,4 @@
-//===- ConvertStandardToSPIRV.h - Convert to SPIR-V dialect -----*- C++ -*-===//
+//===- StandardToSPIRV.h - Standard to SPIR-V Patterns --------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,21 +6,21 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Provides patterns to lower StandardOps to SPIR-V dialect.
+// Provides patterns to convert Standard dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_CONVERSION_STANDARDTOSPIRV_CONVERTSTANDARDTOSPIRV_H
-#define MLIR_CONVERSION_STANDARDTOSPIRV_CONVERTSTANDARDTOSPIRV_H
+#ifndef MLIR_CONVERSION_STANDARDTOSPIRV_STANDARDTOSPIRV_H
+#define MLIR_CONVERSION_STANDARDTOSPIRV_STANDARDTOSPIRV_H
 
 #include "mlir/Transforms/DialectConversion.h"
 
 namespace mlir {
 class SPIRVTypeConverter;
 
-/// Appends to a pattern list additional patterns for translating StandardOps to
-/// SPIR-V ops. Also adds the patterns legalize ops not directly translated to
-/// SPIR-V dialect.
+/// Appends to a pattern list additional patterns for translating standard ops
+/// to SPIR-V ops. Also adds the patterns to legalize ops not directly
+/// translated to SPIR-V dialect.
 void populateStandardToSPIRVPatterns(MLIRContext *context,
                                      SPIRVTypeConverter &typeConverter,
                                      OwningRewritePatternList &patterns);
@@ -32,4 +32,4 @@ void populateStdLegalizationPatternsForSPIRVLowering(
 
 } // namespace mlir
 
-#endif // MLIR_CONVERSION_STANDARDTOSPIRV_CONVERTSTANDARDTOSPIRV_H
+#endif // MLIR_CONVERSION_STANDARDTOSPIRV_STANDARDTOSPIRV_H
diff --git a/mlir/include/mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.h b/mlir/include/mlir/Conversion/StandardToSPIRV/StandardToSPIRVPass.h
similarity index 57%
rename from mlir/include/mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.h
rename to mlir/include/mlir/Conversion/StandardToSPIRV/StandardToSPIRVPass.h
index 29e1d635a00f2..e987527e56f5d 100644
--- a/mlir/include/mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.h
+++ b/mlir/include/mlir/Conversion/StandardToSPIRV/StandardToSPIRVPass.h
@@ -1,4 +1,4 @@
-//===- ConvertStandardToSPIRVPass.h - StdOps to SPIR-V pass -----*- C++ -*-===//
+//===- StandardToSPIRVPass.h - Standard to SPIR-V Passes --------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,23 +6,23 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Provides a pass to lower from StandardOps to SPIR-V dialect.
+// Provides passes to convert Standard dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_CONVERSION_STANDARDTOSPIRV_CONVERTSTANDARDTOSPIRVPASS_H
-#define MLIR_CONVERSION_STANDARDTOSPIRV_CONVERTSTANDARDTOSPIRVPASS_H
+#ifndef MLIR_CONVERSION_STANDARDTOSPIRV_STANDARDTOSPIRVPASS_H
+#define MLIR_CONVERSION_STANDARDTOSPIRV_STANDARDTOSPIRVPASS_H
 
 #include "mlir/Pass/Pass.h"
 
 namespace mlir {
 
-/// Pass to convert StandardOps to SPIR-V ops.
+/// Creates a pass to convert standard ops to SPIR-V ops.
 std::unique_ptr<OperationPass<ModuleOp>> createConvertStandardToSPIRVPass();
 
-/// Pass to legalize ops that are not directly lowered to SPIR-V.
+/// Creates a pass to legalize ops that are not directly lowered to SPIR-V.
 std::unique_ptr<Pass> createLegalizeStdOpsForSPIRVLoweringPass();
 
 } // namespace mlir
 
-#endif // MLIR_CONVERSION_STANDARDTOSPIRV_CONVERTSTANDARDTOSPIRVPASS_H
+#endif // MLIR_CONVERSION_STANDARDTOSPIRV_STANDARDTOSPIRVPASS_H
diff --git a/mlir/include/mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRV.h b/mlir/include/mlir/Conversion/VectorToSPIRV/VectorToSPIRV.h
similarity index 67%
rename from mlir/include/mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRV.h
rename to mlir/include/mlir/Conversion/VectorToSPIRV/VectorToSPIRV.h
index de664df83e83b..7908f6ed3b6f9 100644
--- a/mlir/include/mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRV.h
+++ b/mlir/include/mlir/Conversion/VectorToSPIRV/VectorToSPIRV.h
@@ -1,4 +1,4 @@
-//=- ConvertVectorToSPIRV.h - Vector Ops to SPIR-V dialect patterns - C++ -*-=//
+//=- VectorToSPIRV.h - Vector to SPIR-V Patterns ------------------*- C++ -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,12 +6,12 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Provides patterns for lowering Vector Ops to SPIR-V dialect.
+// Provides patterns to convert Vector dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_INCLUDE_MLIR_CONVERSION_VECTORTOSPIRV_CONVERTVECTORTOSPIRV_H_
-#define MLIR_INCLUDE_MLIR_CONVERSION_VECTORTOSPIRV_CONVERTVECTORTOSPIRV_H_
+#ifndef MLIR_INCLUDE_MLIR_CONVERSION_VECTORTOSPIRV_VECTORTOSPIRV_H
+#define MLIR_INCLUDE_MLIR_CONVERSION_VECTORTOSPIRV_VECTORTOSPIRV_H
 
 #include "mlir/Transforms/DialectConversion.h"
 
@@ -26,4 +26,4 @@ void populateVectorToSPIRVPatterns(MLIRContext *context,
 
 } // namespace mlir
 
-#endif // MLIR_INCLUDE_MLIR_CONVERSION_VECTORTOSPIRV_CONVERTVECTORTOSPIRV_H_
+#endif // MLIR_INCLUDE_MLIR_CONVERSION_VECTORTOSPIRV_VECTORTOSPIRV_H
diff --git a/mlir/include/mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRVPass.h b/mlir/include/mlir/Conversion/VectorToSPIRV/VectorToSPIRVPass.h
similarity index 58%
rename from mlir/include/mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRVPass.h
rename to mlir/include/mlir/Conversion/VectorToSPIRV/VectorToSPIRVPass.h
index 7d4c7c1fb0259..3a9d0a17d025d 100644
--- a/mlir/include/mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRVPass.h
+++ b/mlir/include/mlir/Conversion/VectorToSPIRV/VectorToSPIRVPass.h
@@ -1,4 +1,4 @@
-//=- ConvertVectorToSPIRVPass.h - Pass converting Vector to SPIRV -*- C++ -*-=//
+//=- VectorToSPIRVPass.h - Vector to SPIR-V Passes ----------------*- C++ -*-=//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,20 +6,20 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// Provides a pass to convert Vector ops to SPIR-V ops.
+// Provides passes to convert Vector dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef MLIR_CONVERSION_VECTORTOSPIRV_CONVERTGPUTOSPIRVPASS_H
-#define MLIR_CONVERSION_VECTORTOSPIRV_CONVERTGPUTOSPIRVPASS_H
+#ifndef MLIR_CONVERSION_VECTORTOSPIRV_GPUTOSPIRVPASS_H
+#define MLIR_CONVERSION_VECTORTOSPIRV_GPUTOSPIRVPASS_H
 
 #include "mlir/Pass/Pass.h"
 
 namespace mlir {
 
-/// Pass to convert Vector Ops to SPIR-V ops.
+/// Creates a pass to convert Vector Ops to SPIR-V ops.
 std::unique_ptr<OperationPass<ModuleOp>> createConvertVectorToSPIRVPass();
 
 } // namespace mlir
 
-#endif // MLIR_CONVERSION_VECTORTOSPIRV_CONVERTGPUTOSPIRVPASS_H
+#endif // MLIR_CONVERSION_VECTORTOSPIRV_GPUTOSPIRVPASS_H
diff --git a/mlir/include/mlir/Dialect/AVX512/AVX512Dialect.h b/mlir/include/mlir/Dialect/AVX512/AVX512Dialect.h
index aae3dbdf179fb..eddee61d6b19e 100644
--- a/mlir/include/mlir/Dialect/AVX512/AVX512Dialect.h
+++ b/mlir/include/mlir/Dialect/AVX512/AVX512Dialect.h
@@ -13,6 +13,7 @@
 #ifndef MLIR_DIALECT_AVX512_AVX512DIALECT_H_
 #define MLIR_DIALECT_AVX512_AVX512DIALECT_H_
 
+#include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Dialect.h"
 #include "mlir/IR/OpDefinition.h"
 #include "mlir/Interfaces/SideEffectInterfaces.h"
diff --git a/mlir/include/mlir/Dialect/ArmNeon/ArmNeonDialect.h b/mlir/include/mlir/Dialect/ArmNeon/ArmNeonDialect.h
index 76153af976893..18535353a104c 100644
--- a/mlir/include/mlir/Dialect/ArmNeon/ArmNeonDialect.h
+++ b/mlir/include/mlir/Dialect/ArmNeon/ArmNeonDialect.h
@@ -13,6 +13,7 @@
 #ifndef MLIR_DIALECT_ARMNEON_ARMNEONDIALECT_H_
 #define MLIR_DIALECT_ARMNEON_ARMNEONDIALECT_H_
 
+#include "mlir/IR/BuiltinTypes.h"
 #include "mlir/IR/Dialect.h"
 #include "mlir/IR/OpDefinition.h"
 #include "mlir/Interfaces/SideEffectInterfaces.h"
diff --git a/mlir/include/mlir/Dialect/GPU/GPUOps.td b/mlir/include/mlir/Dialect/GPU/GPUOps.td
index 953a2d5c282c9..457477f7f3c1a 100644
--- a/mlir/include/mlir/Dialect/GPU/GPUOps.td
+++ b/mlir/include/mlir/Dialect/GPU/GPUOps.td
@@ -879,4 +879,39 @@ def GPU_DeallocOp : GPU_Op<"dealloc", [
   }];
 }
 
+def GPU_MemcpyOp : GPU_Op<"memcpy", [
+    GPU_AsyncOpInterface, MemoryEffects<[MemRead, MemWrite]>
+  ]> {
+
+  let summary = "GPU memcpy operation";
+
+  let description = [{
+    The `gpu.memcpy` operation copies the content of one memref to another.
+
+    The op does not execute before all async dependencies have finished
+    executing.
+
+    If the `async` keyword is present, the op is executed asynchronously (i.e.
+    it does not block until the execution has finished on the device). In
+    that case, it returns a !gpu.async.token.
+
+    Example:
+
+    ```mlir
+    %token = gpu.memcpy async [%dep] %dst, %src : memref<?xf32, 1>, memref<?xf32>
+    ```
+  }];
+
+  let arguments = (ins Variadic<GPU_AsyncToken>:$asyncDependencies,
+                   Arg<AnyMemRef, "", [MemWrite]>:$dst,
+                   Arg<AnyMemRef, "", [MemRead]>:$src);
+  let results = (outs Optional<GPU_AsyncToken>:$asyncToken);
+
+  let assemblyFormat = [{
+    custom<AsyncDependencies>(type($asyncToken), $asyncDependencies)
+    $dst`,` $src `:` type($dst)`,` type($src) attr-dict
+  }];
+  let verifier = [{ return ::verify(*this); }];
+}
+
 #endif // GPU_OPS
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
index df022ef47b331..4968b33f47a47 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
@@ -51,7 +51,7 @@ def LLVM_VoidResultTypeOpBuilder :
   [{
     auto llvmType = resultType.dyn_cast<LLVMType>(); (void)llvmType;
     assert(llvmType && "result must be an LLVM type");
-    assert(llvmType.isVoidTy() &&
+    assert(llvmType.isa<LLVMVoidType>() &&
            "for zero-result operands, only 'void' is accepted as result type");
     build($_builder, $_state, operands, attributes);
   }]>;
@@ -150,7 +150,7 @@ def LLVM_ICmpOp : LLVM_Op<"icmp", [NoSideEffect]> {
   let builders = [
     OpBuilderDAG<(ins "ICmpPredicate":$predicate, "Value":$lhs, "Value":$rhs),
     [{
-      build($_builder, $_state, LLVMType::getInt1Ty(lhs.getType().getContext()),
+      build($_builder, $_state, LLVMIntegerType::get(lhs.getType().getContext(), 1),
             $_builder.getI64IntegerAttr(static_cast<int64_t>(predicate)), lhs, rhs);
     }]>];
   let parser = [{ return parseCmpOp<ICmpPredicate>(parser, result); }];
@@ -198,7 +198,7 @@ def LLVM_FCmpOp : LLVM_Op<"fcmp", [NoSideEffect]> {
   let builders = [
     OpBuilderDAG<(ins "FCmpPredicate":$predicate, "Value":$lhs, "Value":$rhs),
     [{
-      build($_builder, $_state, LLVMType::getInt1Ty(lhs.getType().getContext()),
+      build($_builder, $_state, LLVMIntegerType::get(lhs.getType().getContext(), 1),
             $_builder.getI64IntegerAttr(static_cast<int64_t>(predicate)), lhs, rhs);
     }]>];
   let parser = [{ return parseCmpOp<FCmpPredicate>(parser, result); }];
@@ -288,7 +288,7 @@ def LLVM_LoadOp : LLVM_Op<"load">, MemoryOpWithAlignmentAndAttributes {
     OpBuilderDAG<(ins "Value":$addr, CArg<"unsigned", "0">:$alignment,
       CArg<"bool", "false">:$isVolatile, CArg<"bool", "false">:$isNonTemporal),
     [{
-      auto type = addr.getType().cast<LLVMType>().getPointerElementTy();
+      auto type = addr.getType().cast<LLVMPointerType>().getElementType();
       build($_builder, $_state, type, addr, alignment, isVolatile, isNonTemporal);
     }]>,
     OpBuilderDAG<(ins "Type":$t, "Value":$addr,
@@ -443,8 +443,8 @@ def LLVM_CallOp : LLVM_Op<"call"> {
     OpBuilderDAG<(ins "LLVMFuncOp":$func, "ValueRange":$operands,
       CArg<"ArrayRef<NamedAttribute>", "{}">:$attributes),
     [{
-      LLVMType resultType = func.getType().getFunctionResultType();
-      if (!resultType.isVoidTy())
+      LLVMType resultType = func.getType().getReturnType();
+      if (!resultType.isa<LLVM::LLVMVoidType>())
         $_state.addTypes(resultType);
       $_state.addAttribute("callee", $_builder.getSymbolRefAttr(func));
       $_state.addAttributes(attributes);
@@ -515,12 +515,10 @@ def LLVM_ShuffleVectorOp : LLVM_Op<"shufflevector", [NoSideEffect]> {
     OpBuilderDAG<(ins "Value":$v1, "Value":$v2, "ArrayAttr":$mask,
       CArg<"ArrayRef<NamedAttribute>", "{}">:$attrs)>];
   let verifier = [{
-    auto wrappedVectorType1 = v1().getType().cast<LLVMType>();
-    auto wrappedVectorType2 = v2().getType().cast<LLVMType>();
-    if (!wrappedVectorType2.isVectorTy())
-      return emitOpError("expected LLVM IR Dialect vector type for operand #2");
-    if (wrappedVectorType1.getVectorElementType() !=
-        wrappedVectorType2.getVectorElementType())
+    auto wrappedVectorType1 = v1().getType().cast<LLVMVectorType>();
+    auto wrappedVectorType2 = v2().getType().cast<LLVMVectorType>();
+    if (wrappedVectorType1.getElementType() !=
+        wrappedVectorType2.getElementType())
       return emitOpError("expected matching LLVM IR Dialect element types");
     return success();
   }];
@@ -768,13 +766,13 @@ def LLVM_AddressOfOp : LLVM_Op<"mlir.addressof"> {
       CArg<"ArrayRef<NamedAttribute>", "{}">:$attrs),
     [{
       build($_builder, $_state,
-            global.getType().getPointerTo(global.addr_space()),
+            LLVM::LLVMPointerType::get(global.getType(), global.addr_space()),
             global.sym_name(), attrs);}]>,
     OpBuilderDAG<(ins "LLVMFuncOp":$func,
       CArg<"ArrayRef<NamedAttribute>", "{}">:$attrs),
     [{
       build($_builder, $_state,
-            func.getType().getPointerTo(), func.getName(), attrs);}]>
+            LLVM::LLVMPointerType::get(func.getType()), func.getName(), attrs);}]>
   ];
 
   let extraClassDeclaration = [{
@@ -970,12 +968,12 @@ def LLVM_LLVMFuncOp : LLVM_Op<"func",
     // to match the signature of the function.
     Block *addEntryBlock();
 
-    LLVMType getType() {
+    LLVMFunctionType getType() {
       return (*this)->getAttrOfType<TypeAttr>(getTypeAttrName())
-          .getValue().cast<LLVMType>();
+          .getValue().cast<LLVMFunctionType>();
     }
     bool isVarArg() {
-      return getType().isFunctionVarArg();
+      return getType().isVarArg();
     }
 
     // Hook for OpTrait::FunctionLike, returns the number of function arguments`.
diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
index f92bdf9e3041a..7c7731946ba80 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
+++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h
@@ -53,9 +53,7 @@ class LLVMIntegerType;
 ///
 /// The LLVM dialect in MLIR fully reflects the LLVM IR type system, prodiving a
 /// separate MLIR type for each LLVM IR type. All types are represented as
-/// separate subclasses and are compatible with the isa/cast infrastructure. For
-/// convenience, the base class provides most of the APIs available on
-/// llvm::Type in addition to MLIR-compatible APIs.
+/// separate subclasses and are compatible with the isa/cast infrastructure.
 ///
 /// The LLVM dialect type system is closed: parametric types can only refer to
 /// other LLVM dialect types. This is consistent with LLVM IR and enables a more
@@ -64,6 +62,11 @@ class LLVMIntegerType;
 /// Similarly to other MLIR types, LLVM dialect types are owned by the MLIR
 /// context, have an immutable identifier (for most types except identified
 /// structs, the entire type is the identifier) and are thread-safe.
+///
+/// This class is a thin common base class for different types available in the
+/// LLVM dialect. It intentionally does not provide the API similar to
+/// llvm::Type to avoid confusion and highlight potentially expensive operations
+/// (e.g., type creation in MLIR takes a lock, so it's better to cache types).
 class LLVMType : public Type {
 public:
   /// Inherit base constructors.
@@ -79,153 +82,6 @@ class LLVMType : public Type {
   static bool classof(Type type);
 
   LLVMDialect &getDialect();
-
-  /// Returns the size of a primitive type (including vectors) in bits, for
-  /// example, the size of !llvm.i16 is 16 and the size of !llvm.vec<4 x i16>
-  /// is 64. Returns 0 for non-primitive (aggregates such as struct) or types
-  /// that don't have a size (such as void).
-  llvm::TypeSize getPrimitiveSizeInBits();
-
-  /// Floating-point type utilities.
-  bool isBFloatTy() { return isa<LLVMBFloatType>(); }
-  bool isHalfTy() { return isa<LLVMHalfType>(); }
-  bool isFloatTy() { return isa<LLVMFloatType>(); }
-  bool isDoubleTy() { return isa<LLVMDoubleType>(); }
-  bool isFP128Ty() { return isa<LLVMFP128Type>(); }
-  bool isX86_FP80Ty() { return isa<LLVMX86FP80Type>(); }
-  bool isFloatingPointTy() {
-    return isa<LLVMHalfType>() || isa<LLVMBFloatType>() ||
-           isa<LLVMFloatType>() || isa<LLVMDoubleType>() ||
-           isa<LLVMFP128Type>() || isa<LLVMX86FP80Type>();
-  }
-
-  /// Array type utilities.
-  LLVMType getArrayElementType();
-  unsigned getArrayNumElements();
-  bool isArrayTy();
-
-  /// Integer type utilities.
-  bool isIntegerTy() { return isa<LLVMIntegerType>(); }
-  bool isIntegerTy(unsigned bitwidth);
-  unsigned getIntegerBitWidth();
-
-  /// Vector type utilities.
-  LLVMType getVectorElementType();
-  unsigned getVectorNumElements();
-  llvm::ElementCount getVectorElementCount();
-  bool isVectorTy();
-
-  /// Function type utilities.
-  LLVMType getFunctionParamType(unsigned argIdx);
-  unsigned getFunctionNumParams();
-  LLVMType getFunctionResultType();
-  bool isFunctionTy();
-  bool isFunctionVarArg();
-
-  /// Pointer type utilities.
-  LLVMType getPointerTo(unsigned addrSpace = 0);
-  LLVMType getPointerElementTy();
-  bool isPointerTy();
-
-  /// Struct type utilities.
-  LLVMType getStructElementType(unsigned i);
-  unsigned getStructNumElements();
-  bool isStructTy();
-
-  /// Utilities used to generate floating point types.
-  static LLVMType getDoubleTy(MLIRContext *context);
-  static LLVMType getFloatTy(MLIRContext *context);
-  static LLVMType getBFloatTy(MLIRContext *context);
-  static LLVMType getHalfTy(MLIRContext *context);
-  static LLVMType getFP128Ty(MLIRContext *context);
-  static LLVMType getX86_FP80Ty(MLIRContext *context);
-
-  /// Utilities used to generate integer types.
-  static LLVMType getIntNTy(MLIRContext *context, unsigned numBits);
-  static LLVMType getInt1Ty(MLIRContext *context) {
-    return getIntNTy(context, /*numBits=*/1);
-  }
-  static LLVMType getInt8Ty(MLIRContext *context) {
-    return getIntNTy(context, /*numBits=*/8);
-  }
-  static LLVMType getInt8PtrTy(MLIRContext *context) {
-    return getInt8Ty(context).getPointerTo();
-  }
-  static LLVMType getInt16Ty(MLIRContext *context) {
-    return getIntNTy(context, /*numBits=*/16);
-  }
-  static LLVMType getInt32Ty(MLIRContext *context) {
-    return getIntNTy(context, /*numBits=*/32);
-  }
-  static LLVMType getInt64Ty(MLIRContext *context) {
-    return getIntNTy(context, /*numBits=*/64);
-  }
-
-  /// Utilities used to generate other miscellaneous types.
-  static LLVMType getArrayTy(LLVMType elementType, uint64_t numElements);
-  static LLVMType getFunctionTy(LLVMType result, ArrayRef<LLVMType> params,
-                                bool isVarArg);
-  static LLVMType getFunctionTy(LLVMType result, bool isVarArg) {
-    return getFunctionTy(result, llvm::None, isVarArg);
-  }
-  static LLVMType getStructTy(MLIRContext *context, ArrayRef<LLVMType> elements,
-                              bool isPacked = false);
-  static LLVMType getStructTy(MLIRContext *context, bool isPacked = false) {
-    return getStructTy(context, llvm::None, isPacked);
-  }
-  template <typename... Args>
-  static typename std::enable_if<llvm::are_base_of<LLVMType, Args...>::value,
-                                 LLVMType>::type
-  getStructTy(LLVMType elt1, Args... elts) {
-    SmallVector<LLVMType, 8> fields({elt1, elts...});
-    return getStructTy(elt1.getContext(), fields);
-  }
-  static LLVMType getVectorTy(LLVMType elementType, unsigned numElements);
-
-  /// Void type utilities.
-  static LLVMType getVoidTy(MLIRContext *context);
-  bool isVoidTy();
-
-  // Creation and setting of LLVM's identified struct types
-  static LLVMType createStructTy(MLIRContext *context,
-                                 ArrayRef<LLVMType> elements,
-                                 Optional<StringRef> name,
-                                 bool isPacked = false);
-
-  static LLVMType createStructTy(MLIRContext *context,
-                                 Optional<StringRef> name) {
-    return createStructTy(context, llvm::None, name);
-  }
-
-  static LLVMType createStructTy(ArrayRef<LLVMType> elements,
-                                 Optional<StringRef> name,
-                                 bool isPacked = false) {
-    assert(!elements.empty() &&
-           "This method may not be invoked with an empty list");
-    LLVMType ele0 = elements.front();
-    return createStructTy(ele0.getContext(), elements, name, isPacked);
-  }
-
-  template <typename... Args>
-  static typename std::enable_if_t<llvm::are_base_of<LLVMType, Args...>::value,
-                                   LLVMType>
-  createStructTy(StringRef name, LLVMType elt1, Args... elts) {
-    SmallVector<LLVMType, 8> fields({elt1, elts...});
-    Optional<StringRef> opt_name(name);
-    return createStructTy(elt1.getContext(), fields, opt_name);
-  }
-
-  static LLVMType setStructTyBody(LLVMType structType,
-                                  ArrayRef<LLVMType> elements,
-                                  bool isPacked = false);
-
-  template <typename... Args>
-  static typename std::enable_if_t<llvm::are_base_of<LLVMType, Args...>::value,
-                                   LLVMType>
-  setStructTyBody(LLVMType structType, LLVMType elt1, Args... elts) {
-    SmallVector<LLVMType, 8> fields({elt1, elts...});
-    return setStructTyBody(structType, fields);
-  }
 };
 
 //===----------------------------------------------------------------------===//
@@ -441,6 +297,14 @@ class LLVMStructType : public Type::TypeBase<LLVMStructType, LLVMType,
   static LLVMStructType getIdentified(MLIRContext *context, StringRef name);
   static LLVMStructType getIdentifiedChecked(Location loc, StringRef name);
 
+  /// Gets a new identified struct with the given body. The body _cannot_ be
+  /// changed later. If a struct with the given name already exists, renames
+  /// the struct by appending a `.` followed by a number to the name. Renaming
+  /// happens even if the existing struct has the same body.
+  static LLVMStructType getNewIdentified(MLIRContext *context, StringRef name,
+                                         ArrayRef<LLVMType> elements,
+                                         bool isPacked = false);
+
   /// Gets or creates a literal struct with the given body in the provided
   /// context.
   static LLVMStructType getLiteral(MLIRContext *context,
@@ -585,6 +449,24 @@ LLVMType parseType(DialectAsmParser &parser);
 void printType(LLVMType type, DialectAsmPrinter &printer);
 } // namespace detail
 
+//===----------------------------------------------------------------------===//
+// Utility functions.
+//===----------------------------------------------------------------------===//
+
+/// Returns `true` if the given type is compatible with the LLVM dialect.
+inline bool isCompatibleType(Type type) { return type.isa<LLVMType>(); }
+
+inline bool isCompatibleFloatingPointType(Type type) {
+  return type.isa<LLVMHalfType, LLVMBFloatType, LLVMFloatType, LLVMDoubleType,
+                  LLVMFP128Type, LLVMX86FP80Type>();
+}
+
+/// Returns the size of the given primitive LLVM dialect-compatible type
+/// (including vectors) in bits, for example, the size of !llvm.i16 is 16 and
+/// the size of !llvm.vec<4 x i16> is 64. Returns 0 for non-primitive
+/// (aggregates such as struct) or types that don't have a size (such as void).
+llvm::TypeSize getPrimitiveTypeSizeInBits(Type type);
+
 } // namespace LLVM
 } // namespace mlir
 
diff --git a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
index 1f9b860eb52eb..3c73cdf64eb70 100644
--- a/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
+++ b/mlir/include/mlir/Dialect/LLVMIR/NVVMOps.td
@@ -109,10 +109,11 @@ def NVVM_ShflBflyOp :
   let verifier = [{
     if (!(*this)->getAttrOfType<UnitAttr>("return_value_and_is_valid"))
       return success();
-    auto type = getType().cast<LLVM::LLVMType>();
-    if (!type.isStructTy() || type.getStructNumElements() != 2 ||
-        !type.getStructElementType(1).isIntegerTy(
-            /*Bitwidth=*/1))
+    auto type = getType().dyn_cast<LLVM::LLVMStructType>();
+    auto elementType = (type && type.getBody().size() == 2)
+                     ? type.getBody()[1].dyn_cast<LLVM::LLVMIntegerType>()
+                     : nullptr;
+    if (!elementType || elementType.getBitWidth() != 1)
       return emitError("expected return type to be a two-element struct with "
                        "i1 as the second element");
     return success();
diff --git a/mlir/include/mlir/Dialect/Linalg/Analysis/DependenceAnalysis.h b/mlir/include/mlir/Dialect/Linalg/Analysis/DependenceAnalysis.h
index 4ee5fac7f677a..9aa50c25cd794 100644
--- a/mlir/include/mlir/Dialect/Linalg/Analysis/DependenceAnalysis.h
+++ b/mlir/include/mlir/Dialect/Linalg/Analysis/DependenceAnalysis.h
@@ -45,19 +45,17 @@ class Aliases {
 class LinalgDependenceGraph {
 public:
   enum DependenceType { RAR = 0, RAW, WAR, WAW, NumTypes };
-  struct LinalgOpView {
-    Operation *op;
-    unsigned operandIndex;
-  };
+  // TODO: OpOperand tracks dependencies on buffer operands. Tensor result will
+  // need an extension to use OpResult.
   struct LinalgDependenceGraphElem {
     // dependentOpView may be either:
     //   1. src in the case of dependencesIntoGraphs.
     //   2. dst in the case of dependencesFromDstGraphs.
-    LinalgOpView dependentOpView;
+    OpOperand *dependentOpView;
     // View in the op that is used to index in the graph:
     //   1. src in the case of dependencesFromDstGraphs.
     //   2. dst in the case of dependencesIntoGraphs.
-    LinalgOpView indexingOpView;
+    OpOperand *indexingOpView;
     // Type of the dependence.
     DependenceType dependenceType;
   };
@@ -161,8 +159,8 @@ class LinalgDependenceGraph {
   // Uses std::pair to keep operations and view together and avoid usage errors
   // related to src/dst and producer/consumer terminology in the context of
   // dependences.
-  void addDependenceElem(DependenceType dt, LinalgOpView indexingOpView,
-                         LinalgOpView dependentOpView);
+  void addDependenceElem(DependenceType dt, OpOperand *indexingOpView,
+                         OpOperand *dependentOpView);
 
   /// Implementation detail for findCoveringxxx.
   SmallVector<Operation *, 8>
diff --git a/mlir/include/mlir/Dialect/Linalg/EDSC/Builders.h b/mlir/include/mlir/Dialect/Linalg/EDSC/Builders.h
index ac9ca9581f0d2..43dff8150f770 100644
--- a/mlir/include/mlir/Dialect/Linalg/EDSC/Builders.h
+++ b/mlir/include/mlir/Dialect/Linalg/EDSC/Builders.h
@@ -30,8 +30,8 @@ class ParallelOp;
 namespace edsc {
 inline void defaultRegionBuilder(ValueRange args) {}
 
-/// Build a `linalg.generic` op with the specified `inputs`, `outputBuffers`,
-/// `initTensors`, `resultTensorsTypes` and `region`.
+/// Build a `linalg.generic` op with the specified `inputs`, `outputs`,
+/// `resultTensorsTypes` and `region`.
 ///
 /// `otherValues` and `otherAttributes` may be passed and will be appended as
 /// operands and attributes respectively.
@@ -41,15 +41,12 @@ inline void defaultRegionBuilder(ValueRange args) {}
 ///
 /// 1. `inputs` may contain StructuredIndexed that capture either buffer or
 /// tensor values.
-/// 2. `outputsBuffers` may contain StructuredIndexed that capture buffer
-/// values.
-/// 3. `initTensors` contain tensor values, without indexing maps.
-/// 4. `resultTensorTypes` may contain StructuredIndexed that capture return
-/// tensor types.
+/// 2. `outputs` may contain StructuredIndexed that capture either buffer or
+/// tensor values. In the future this will be extended with ranked shape values.
+/// 4. `resultTensorTypes` may contain return tensor types.
 Operation *makeGenericLinalgOp(
     ArrayRef<IteratorType> iteratorTypes, ArrayRef<StructuredIndexed> inputs,
-    ArrayRef<StructuredIndexed> outputBuffers, ArrayRef<Value> initTensors,
-    ArrayRef<StructuredIndexed> resultTensorTypes,
+    ArrayRef<StructuredIndexed> outputs, TypeRange resultTensorTypes,
     function_ref<void(ValueRange)> regionBuilder = defaultRegionBuilder,
     ArrayRef<Value> otherValues = {}, ArrayRef<Attribute> otherAttributes = {});
 
diff --git a/mlir/include/mlir/Dialect/Linalg/EDSC/Intrinsics.h b/mlir/include/mlir/Dialect/Linalg/EDSC/Intrinsics.h
index d842069f65705..0b53fc7573a5a 100644
--- a/mlir/include/mlir/Dialect/Linalg/EDSC/Intrinsics.h
+++ b/mlir/include/mlir/Dialect/Linalg/EDSC/Intrinsics.h
@@ -18,6 +18,7 @@ namespace intrinsics {
 using linalg_copy = OperationBuilder<linalg::CopyOp>;
 using linalg_dot = OperationBuilder<linalg::DotOp>;
 using linalg_fill = OperationBuilder<linalg::FillOp>;
+using linalg_init_tensor = ValueBuilder<linalg::InitTensorOp>;
 using linalg_matmul = OperationBuilder<linalg::MatmulOp>;
 using linalg_matvec = OperationBuilder<linalg::MatvecOp>;
 using linalg_vecmat = OperationBuilder<linalg::VecmatOp>;
diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h
index 2438338a534fa..b1ac1a3b48b61 100644
--- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h
+++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.h
@@ -9,7 +9,6 @@
 #ifndef MLIR_DIALECT_LINALG_LINALGOPS_H_
 #define MLIR_DIALECT_LINALG_LINALGOPS_H_
 
-#include "mlir/Dialect/Linalg/IR/LinalgTraits.h"
 #include "mlir/Dialect/Linalg/IR/LinalgTypes.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/Dialect/Utils/StructuredOpsUtils.h"
@@ -111,9 +110,17 @@ SmallVector<AffineExpr, 4> concat(ArrayRef<AffineExpr> a,
 void getDimsOfType(Operation *op, StringRef iteratorTypeName,
                    SmallVectorImpl<AffineExpr> &res);
 
+namespace detail {
+LogicalResult verifyStructuredOpInterface(Operation *op);
+} // namespace detail
 } // namespace linalg
 } // namespace mlir
 
+namespace mlir {
+namespace linalg {
+class IndexedGenericOp;
+} // namespace linalg
+} // namespace mlir
 #include "mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterfaces.h.inc"
 
 #define GET_OP_CLASSES
diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
index 66f39104d7e7c..26db4c2f6735e 100644
--- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
+++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOps.td
@@ -19,26 +19,6 @@ include "mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td"
 include "mlir/Interfaces/CopyOpInterface.td"
 include "mlir/Interfaces/SideEffectInterfaces.td"
 
-// The Linalg `NInputs` trait provides the API for ops that are known
-// to have a specified number of inputs, all passed as operands.
-// See Linalg/LinalgTraits.h for implementation details and usage.
-class NInputs<int n> :
-  NativeOpTrait<"linalg::NInputs<" # !cast<string>(n) # ">::Impl"> {}
-
-// The Linalg `ZeroInitTensors` trait provides the API for ops that are known
-// to not have input tensor operands.
-// See Linalg/LinalgTraits.h for implementation details and usage.
-def ZeroInitTensors : NativeOpTrait<"linalg::ZeroInitTensors"> {}
-
-// The Linalg `NOutputs` trait provides the API for ops that are known
-// to have a specified number of outputs, all passed as operands.
-// See Linalg/LinalgTraits.h for implementation details and usage.
-class NOutputs<int n> :
-  NativeOpTrait<"linalg::NOutputs<" # !cast<string>(n) # ">::Impl"> {}
-
-def StructuredOpTraits : NativeOpTrait<"linalg::StructuredOpTraits">;
-def NamedStructuredOpTrait : NativeOpTrait<"linalg::NamedStructuredOpTrait">;
-
 // Base Tablegen class for Linalg ops.
 // Linalg ops that correspond to library calls operate on ShapedType as their
 // first operands. These may be optionally followed by non-view operands
@@ -50,7 +30,6 @@ class LinalgStructuredBase_Op<string mnemonic, list<OpTrait> props>
 class LinalgStructured_Op<string mnemonic, list<OpTrait> props>
   : LinalgStructuredBase_Op<mnemonic,
        !listconcat(props, [
-         StructuredOpTraits,
          DeclareOpInterfaceMethods<MemoryEffectsOpInterface>])> {
   code libraryCallName = [{
     std::string getLibraryCallName() {
@@ -65,12 +44,7 @@ class LinalgStructured_Op<string mnemonic, list<OpTrait> props>
 //===----------------------------------------------------------------------===//
 // At the moment these are not declarative and require a bunch of C++ code.
 // In the future, these should be migrated to a declarative specification.
-def CopyOp : LinalgStructured_Op<"copy", [
-    CopyOpInterface,
-    NInputs<1>,
-    ZeroInitTensors,
-    NOutputs<1>
-  ]> {
+def CopyOp : LinalgStructured_Op<"copy", [CopyOpInterface]> {
   let description = [{
     Copies the data in the input view into the output view.
 
@@ -137,6 +111,9 @@ def CopyOp : LinalgStructured_Op<"copy", [
     }]>];
 
   let extraClassDeclaration = libraryCallName # [{
+    ValueRange inputs() { return getOperands().take_front(); }
+    ValueRange outputs() { return getOperands().take_back(); }
+
     // Rank-polymorphic.
     //   filling_value -> O(ivs) with parallel iterators.
     ArrayAttr iterator_types() {
@@ -170,14 +147,13 @@ def CopyOp : LinalgStructured_Op<"copy", [
   let hasCanonicalizer = 1;
 }
 
-def FillOp : LinalgStructured_Op<"fill", [
-    NInputs<0>,
-    ZeroInitTensors,
-    NOutputs<1>]> {
-
+def FillOp : LinalgStructured_Op<"fill", []> {
   let arguments = (ins AnyStridedMemRef:$output,
                    AnyTypeOf<[AnyFloat, AnySignlessInteger, AnyVector]>:$value);
   let extraClassDeclaration = libraryCallName # [{
+    ValueRange inputs() { return {}; }
+    ValueRange outputs() { return getOperands().take_front(); }
+
     // Rank-polymorphic.
     //   filling_value -> O(ivs) with parallel iterators.
     ArrayAttr iterator_types() {
@@ -276,13 +252,8 @@ class PoolingBase_Op<string mnemonic, list<OpTrait> props>
   }];
 }
 
-def ConvOp : PoolingBase_Op<"conv", [
-    NInputs<2>,
-    // Despite having reductions, this manually defined ConvOp may only take
-    // memref operands and can never have init tensors.
-    ZeroInitTensors,
-    NOutputs<1>]> {
-
+// Only support buffer semantics.
+def ConvOp : PoolingBase_Op<"conv", []> {
   let description = [{
     Generic n-D convolution as described in the TF documentation:
     https://www.tensorflow.org/versions/r2.0/api_docs/python/tf/nn/convolution
@@ -313,6 +284,9 @@ def ConvOp : PoolingBase_Op<"conv", [
                    OptionalAttr<I64ElementsAttr>:$padding);
 
   let extraClassDeclaration = commonUtils # [{
+    ValueRange inputs() { return getOperands().slice(0, 2); }
+    ValueRange outputs() { return getOperands().take_back(); }
+
     // TODO: extend to support more than 1 dimensions and potentially grouping
     // too.
     unsigned getNumBatchDimensions() { return 1; }
@@ -335,6 +309,12 @@ def ConvOp : PoolingBase_Op<"conv", [
       // parallelized across; i.e. [zs] in the TF notation above whose number
       // match `xs` (i.e. 1 window loop per "image" dimension).
       // This may evolve in the future.
+      // Conditionally check nPar is large enough for cases of ill-formed op: 
+      // this avoids overflows before hitting the verifier.
+      assert(nPar > getNumBatchDimensions() + getNumInputFeatureDimensions() &&
+             "expected at least one window dimension (i.e. memref ranks greater "
+             "than 2). See 'func @conv_rank_limit' in "
+             "mlir/test/Dialect/Linalg/invalid.mlir");
       unsigned nWin =
         nPar - getNumBatchDimensions() - getNumInputFeatureDimensions();
       SmallVector<StringRef, 8> iters(nPar, getParallelIteratorTypeName());
@@ -352,7 +332,8 @@ def ConvOp : PoolingBase_Op<"conv", [
     ArrayAttr indexing_maps() {
       MLIRContext *context = getContext();
       auto nWin = getNumWindowLoops();
-      assert(nWin > 0 && "expected at least one window dimension");
+      assert(nWin > 0 && "expected at least one window dimension (i.e. memref "
+                         "ranks greater than 2)");
       unsigned idx = 0;
       // In the following, AffineDimExprs are indexed in loop order:
       //   [ b, xs, k,           q,                     zs]
@@ -394,13 +375,9 @@ def ConvOp : PoolingBase_Op<"conv", [
   let hasCanonicalizer = 1;
 }
 
+// Only support buffer semantics.
 class SingleInputPoolingBase_Op<string mnemonic>
-  : PoolingBase_Op<mnemonic, [
-    NInputs<2>,
-    // Despite having reductions, this manually defined ConvOp may only take
-    // memref operands and can never have init tensors.
-    ZeroInitTensors,
-    NOutputs<1>]> {
+    : PoolingBase_Op<mnemonic, []> {
   let description = [{
     A base class for single input pooling function.
 
@@ -420,6 +397,9 @@ class SingleInputPoolingBase_Op<string mnemonic>
                    OptionalAttr<I64ElementsAttr>:$padding);
 
   let extraClassDeclaration = commonUtils# [{
+    ValueRange inputs() { return getOperands().slice(0, 2); }
+    ValueRange outputs() { return getOperands().take_back(); }
+
     ArrayAttr iterator_types() {
       // Outer parallel loops are always the number of output dimensions.
       unsigned nPar = getOutputShapedType(0).getRank();
@@ -493,11 +473,9 @@ class LinalgOperandOfRank<int rank>: Type<
 class GenericOpBase<string mnemonic> : LinalgStructuredBase_Op<mnemonic, [
     AttrSizedOperandSegments,
     DeclareOpInterfaceMethods<MemoryEffectsOpInterface>,
-    NamedStructuredOpTrait,
     SingleBlockImplicitTerminator<"YieldOp">]> {
   let arguments = (ins Variadic<AnyShaped>:$inputs,
-                       Variadic<AnyMemRef>:$output_buffers,
-                       Variadic<AnyRankedTensor>:$init_tensors,
+                       Variadic<AnyShaped>:$outputs,
                        AffineMapArrayAttr:$indexing_maps,
                        ArrayAttr:$iterator_types,
                        OptionalAttr<StrAttr>:$doc,
@@ -622,34 +600,26 @@ def GenericOp : GenericOpBase<"generic"> {
     ```mlir
     %C = linalg.generic #trait_attribute
       ins(%A, %B : tensor<?x?xf32>, memref<?x?xf32, stride_specification>)
-      init(%C : tensor<?x?xf32>)
+      outs(%C : tensor<?x?xf32>)
       {other-optional-attributes}
       {region}
       -> (tensor<?x?xf32>)
     ```
-
-    The `init` operand and the conventions around mixing tensors and buffers are
-    described in more detail in the "Tensors and Buffers: Conventions and
-    Limitations" section in the [Linalg Document](../docs/Linalg.md)
-
-    Tensor values must be legalized by a buffer allocation pass before most
-    transformations can be applied. Such legalizations move tensor return values
-    into output buffer operands and updates the region arguments accordingly.
   }];
 
   let builders = [
     OpBuilderDAG<(ins "TypeRange":$resultTensorTypes, "ValueRange":$inputs,
-      "ValueRange":$outputBuffers, "ValueRange":$initTensors,
-      "ArrayRef<AffineMap>":$indexingMaps, "ArrayRef<StringRef>":$iteratorTypes,
-      "StringRef":$doc, "StringRef":$libraryCall,
+      "ValueRange":$outputs, "ArrayRef<AffineMap>":$indexingMaps,
+      "ArrayRef<StringRef>":$iteratorTypes, "StringRef":$doc,
+      "StringRef":$libraryCall,
       CArg<"function_ref<void(OpBuilder &, Location, ValueRange)>", "nullptr">)>,
     OpBuilderDAG<(ins "ValueRange":$inputs, "ValueRange":$outputBuffers,
       "ArrayRef<AffineMap>":$indexingMaps, "ArrayRef<StringRef>":$iteratorTypes,
       "StringRef":$doc, "StringRef":$libraryCall,
       CArg<"function_ref<void(OpBuilder &, Location, ValueRange)>", "nullptr">)>,
     OpBuilderDAG<(ins "TypeRange":$resultTensorTypes, "ValueRange":$inputs,
-      "ValueRange":$outputBuffers, "ValueRange":$initTensors,
-      "ArrayRef<AffineMap>":$indexingMaps, "ArrayRef<StringRef>":$iteratorTypes,
+      "ValueRange":$outputs, "ArrayRef<AffineMap>":$indexingMaps,
+      "ArrayRef<StringRef>":$iteratorTypes,
       CArg<"function_ref<void(OpBuilder &, Location, ValueRange)>", "nullptr">)>,
     OpBuilderDAG<(ins "ValueRange":$inputs, "ValueRange":$outputBuffers,
       "ArrayRef<AffineMap>":$indexingMaps, "ArrayRef<StringRef>":$iteratorTypes,
@@ -714,8 +684,8 @@ def IndexedGenericOp : GenericOpBase<"indexed_generic"> {
 
     ```mlir
       linalg.indexed_generic #matmul_trait
-        ins(%A, %B : memref<?x?xf32, stride_specification>,
-                     memref<?x?xf32, stride_specification>)
+         ins(%A, %B : memref<?x?xf32, stride_specification>,
+                      memref<?x?xf32, stride_specification>)
         outs(%C : memref<?x?xf32, stride_specification>) {
       (%offset_m: index, %offset_n: index, %offset_k: index,
        %a: f32, %b: f32, %c: f32) :
@@ -761,27 +731,19 @@ def IndexedGenericOp : GenericOpBase<"indexed_generic"> {
 
     ```mlir
     %C = linalg.indexed_generic #trait_attribute
-      ins(%A, %B : tensor<?x?xf32>, memref<?x?xf32, stride_specification>)
-      init(%C : tensor<?x?xf32>)
+       ins(%A, %B : tensor<?x?xf32>, memref<?x?xf32, stride_specification>)
+      outs(%C : tensor<?x?xf32>)
       {other-optional-attributes}
       {region_with_index_arguments}
       -> (tensor<?x?xf32>)
     ```
-
-    The `init` operand and the conventions around mixing tensors and buffers are
-    described in more detail in the "Tensors and Buffers: Conventions and
-    Limitations" section in the [Linalg Document](../docs/Linalg.md)
-
-    Tensor values must be legalized by a buffer allocation pass before most
-    transformations can be applied. Such legalizations move tensor return values
-    into output buffer operands and update the region arguments accordingly.
   }];
 
   let builders = [
     OpBuilderDAG<(ins "TypeRange":$resultTensorTypes, "ValueRange":$inputs,
-      "ValueRange":$outputBuffers, "ValueRange":$initTensors,
-      "ArrayRef<AffineMap>":$indexingMaps, "ArrayRef<StringRef>":$iteratorTypes,
-      "StringRef":$doc, "StringRef":$libraryCall,
+      "ValueRange":$outputs, "ArrayRef<AffineMap>":$indexingMaps,
+      "ArrayRef<StringRef>":$iteratorTypes, "StringRef":$doc,
+      "StringRef":$libraryCall,
       CArg<"function_ref<void(OpBuilder &, Location, ValueRange, ValueRange)>",
            "nullptr">)>,
     OpBuilderDAG<(ins "ValueRange":$inputs, "ValueRange":$outputBuffers,
@@ -790,8 +752,8 @@ def IndexedGenericOp : GenericOpBase<"indexed_generic"> {
       CArg<"function_ref<void(OpBuilder &, Location, ValueRange, ValueRange)>",
            "nullptr">)>,
     OpBuilderDAG<(ins "TypeRange":$resultTensorTypes, "ValueRange":$inputs,
-      "ValueRange":$outputBuffers, "ValueRange":$initTensors,
-      "ArrayRef<AffineMap>":$indexingMaps, "ArrayRef<StringRef>":$iteratorTypes,
+      "ValueRange":$outputs, "ArrayRef<AffineMap>":$indexingMaps,
+      "ArrayRef<StringRef>":$iteratorTypes,
       CArg<"function_ref<void(OpBuilder &, Location, ValueRange, ValueRange)>",
            "nullptr">)>,
     OpBuilderDAG<(ins "ValueRange":$inputs, "ValueRange":$outputBuffers,
diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
index 74ca666d63a5e..3fc3fa4a5556e 100644
--- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
+++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgStructuredOpsInterface.td
@@ -20,6 +20,24 @@ include "mlir/Dialect/Linalg/IR/LinalgBase.td"
 def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
   let cppNamespace = "::mlir::linalg";
   let methods = [
+    //===------------------------------------------------------------------===//
+    // Loop types handling.
+    //===------------------------------------------------------------------===//
+    InterfaceMethod<
+      /*desc=*/[{
+        Return the number of induction variables in the basic block. This should
+        always be 0 for index-free linalg ops. For IndexedGeneric, this must be
+        equal to numLoops
+      }],
+      /*retTy=*/"unsigned",
+      /*methodName=*/"getNumPayloadInductionVariables",
+      /*args=*/(ins),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        return isa<IndexedGenericOp>(this->getOperation()) ?
+          $_op.getNumLoops() : 0;
+      }]
+    >,
     //===------------------------------------------------------------------===//
     // Loop types handling.
     //===------------------------------------------------------------------===//
@@ -125,42 +143,60 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
                getNumIterators(getReductionIteratorTypeName(), iters) == 1;
       }]>,
     //===------------------------------------------------------------------===//
-    // Num input/output/initTensors arguments handling.
+    // Num input/output arguments handling.
     //===------------------------------------------------------------------===//
-    // These special methods must be defined by each op that wants to implement
-    // the LinalgStructuredInterface. For now, this is either:
-    // - Explicitly specified in the op definition.
-    // - Derived from variadic attributes (for "named" ops, linalg.generic and
-    //   linalg.indexed_generic ops).
+    // `inputs` must be defined by each op that wants to implement the
+    // LinalgStructuredInterface.
+    InterfaceMethod<
+      /*desc=*/[{
+        Return the input shape operands.
+      }],
+      /*retTy=*/"ValueRange",
+      /*methodName=*/"inputs",
+      /*args=*/(ins)
+    >,
+    // These special methods rely on `inputs` and `outputs` being defined by
+    // each op that wants to implement the LinalgStructuredInterface.
     InterfaceMethod<
       /*desc=*/[{
         Return the number of inputs.
       }],
       /*retTy=*/"unsigned",
-      /*methodName=*/"getNumInputs"
+      /*methodName=*/"getNumInputs",
+      /*args=*/(ins),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        return $_op.inputs().size();
+      }]
     >,
+    // `outputs` must be defined by each op that wants to implement the
+    // LinalgStructuredInterface.
     InterfaceMethod<
       /*desc=*/[{
-        Return the number of init tensors.
+        Return the output shape operands.
       }],
-      /*retTy=*/"unsigned",
-      /*methodName=*/"getNumInitTensors"
+      /*retTy=*/"ValueRange",
+      /*methodName=*/"outputs",
+      /*args=*/(ins)
     >,
     InterfaceMethod<
       /*desc=*/[{
         Return the number of outputs.
       }],
       /*retTy=*/"unsigned",
-      /*methodName=*/"getNumOutputs"
+      /*methodName=*/"getNumOutputs",
+      /*args=*/(ins),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        return $_op.outputs().size();
+      }]
     >,
     //===------------------------------------------------------------------===//
-    // Input arguments handling.
+    // Input operands handling.
     //===------------------------------------------------------------------===//
     InterfaceMethod<
       /*desc=*/[{
-        Return the `i`-th input value.
-        The `i^th` input argument is always the `i^th` operand regardless of
-        whether we have tensors or buffers.
+        Return the `i`-th input operand.
       }],
       /*retTy=*/"Value",
       /*methodName=*/"getInput",
@@ -173,24 +209,7 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the index of the given input value `v`, or `None` if the value is
-        not an input.
-      }],
-      /*retTy=*/"llvm::Optional<unsigned>",
-      /*methodName=*/"getIndexOfInput",
-      /*args=*/(ins "Value":$value),
-      /*methodBody=*/"",
-      /*defaultImplementation=*/[{
-        auto it = llvm::find(getInputs(), value);
-        if (it != getInputs().end())
-          return it - getInputs().begin();
-        return llvm::None;
-      }]
-    >,
-    InterfaceMethod<
-      /*desc=*/[{
-        Return the `i`-th input shaped type, irrespective of buffer or tensor
-        type.
+        Return the `i`-th input shaped type
       }],
       /*retTy=*/"ShapedType",
       /*methodName=*/"getInputShapedType",
@@ -202,7 +221,7 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the input operands.
+        Return the range of input operands.
       }],
       /*retTy=*/"Operation::operand_range",
       /*methodName=*/"getInputs",
@@ -215,7 +234,19 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the range over the input operands that are of buffer type.
+        Return the OpOperands for the input operands.
+      }],
+      /*retTy=*/" MutableArrayRef<OpOperand>",
+      /*methodName=*/"getInputOpOperands",
+      /*args=*/(ins),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        return this->getOperation()->getOpOperands().take_front(getNumInputs());
+      }]
+    >,
+    InterfaceMethod<
+      /*desc=*/[{
+        Return the subset of input operands that are of buffer type.
       }],
       /*retTy=*/"SmallVector<Value, 4>",
       /*methodName=*/"getInputBuffers",
@@ -223,417 +254,504 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
         return llvm::to_vector<4>(llvm::make_filter_range(
-          getInputs(), [](Value in){ return in.getType().isa<MemRefType>(); }));
+          getInputs(), [](Value in){ return in.getType().template isa<MemRefType>(); }));
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the subset of input operands that are of ranked tensor type.
+        Return the number of input buffer operands.
       }],
-      /*retTy=*/"SmallVector<RankedTensorType, 4>",
-      /*methodName=*/"getInputTensorTypes" ,
+      /*retTy=*/"unsigned",
+      /*methodName=*/"getNumInputBuffers",
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        SmallVector<RankedTensorType, 4> res;
-        for (Type type : getInputs().getTypes())
-          if (auto t = type.template dyn_cast<RankedTensorType>())
-            res.push_back(t);
-        return res;
+        return $_op.getInputBuffers().size();
       }]
     >,
-    //===------------------------------------------------------------------===//
-    // Output arguments handling.
-    //===------------------------------------------------------------------===//
     InterfaceMethod<
       /*desc=*/[{
-        Return the output buffer at the given index, asserts that this is a
-        buffer operand and not a tensor result.
-        The `i^th` output argument is an operand (resp. a return value) iff it
-        is a value of buffer type (resp. a return value of tensor type).
+        Return the `index`^th input buffer.
       }],
       /*retTy=*/"Value",
-      /*methodName=*/"getOutputBuffer",
-      /*args=*/(ins "unsigned":$i),
+      /*methodName=*/"getInputBuffer",
+      /*args=*/(ins "unsigned":$index),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        // Output buffers are passed as output buffer operands (side-effecting).
-        // Output tensors are results.
-        // The union of the 2 are all the outputs and we want to ensure i does
-        // not overflow the buffer operands.
-        assert(i + this->getOperation()->getNumResults() < $_op.getNumOutputs()
-               && "overflowing output buffer index");
-        return this->getOperation()->getOperand($_op.getNumInputs() + i);
+        assert(index < getNumInputBuffers());
+        return getInputBuffers()[index];
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the index of the given buffer value, or `None` if the value is
-        not part of the output buffers.
+        Return the subset of input operands that are of buffer type.
       }],
-      /*retTy=*/"llvm::Optional<unsigned>",
-      /*methodName=*/"getIndexOfOutputBuffer",
-      /*args=*/(ins "Value":$value),
+      /*retTy=*/"SmallVector<OpOperand*, 4>",
+      /*methodName=*/"getInputBuffersOpOperands",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        auto it = llvm::find(getOutputBuffers(), value);
-        if (it != getOutputBuffers().end())
-          return it - getOutputBuffers().begin();
-        return llvm::None;
+        SmallVector<OpOperand*, 4> res;
+        res.reserve(getNumInputs());
+        for (OpOperand &o : getInputOpOperands())
+          if (o.get().getType().isa<MemRefType>())
+            res.push_back(&o);
+        return res;
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the type of the output buffer at the given index.
+        Return the subset of input operands that are of tensor type.
       }],
-      /*retTy=*/"MemRefType",
-      /*methodName=*/"getOutputBufferType",
-      /*args=*/(ins "unsigned":$i),
+      /*retTy=*/"SmallVector<Value, 4>",
+      /*methodName=*/"getInputTensors",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        return getOutputBuffer(i).getType().template cast<MemRefType>();
-      }]>,
+        return llvm::to_vector<4>(llvm::make_filter_range(
+          getInputs(),
+          [](Value in){ return in.getType().template isa<RankedTensorType>(); }));
+      }]
+    >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the `i`-th output shaped type, irrespective of buffer or tensor
-        type.
+        Return the subset of op operands that are of tensor type.
       }],
-      /*retTy=*/"ShapedType",
-      /*methodName=*/"getOutputShapedType",
-      /*args=*/(ins "unsigned":$i),
+      /*retTy=*/"SmallVector<OpOperand*, 4>",
+      /*methodName=*/"getInputTensorsOpOperands",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        return getShapedType(i + $_op.getNumInputs());
-      }]>,
+        SmallVector<OpOperand*, 4> res;
+        res.reserve(getNumInputs());
+        for (OpOperand &o : getInputOpOperands())
+          if (o.get().getType().isa<RankedTensorType>())
+            res.push_back(&o);
+        return res;
+      }]
+    >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the results that are of ranked tensor type.
+        Return the types of the subset of input operands that are of buffer type.
       }],
-      /*retTy=*/"SmallVector<RankedTensorType, 4>",
-      /*methodName=*/"getOutputTensorTypes",
+      /*retTy=*/"SmallVector<MemRefType, 4>",
+      /*methodName=*/"getInputBufferTypes" ,
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        SmallVector<RankedTensorType, 4> res;
-        for (Type type : this->getOperation()->getResults().getTypes())
-          res.push_back(type.template cast<RankedTensorType>());
-        return res;
-      }]>,
+        return llvm::to_vector<4>(
+          llvm::map_range(
+            llvm::make_filter_range(
+              ValueRange(getInputs()).getTypes(),
+              [](Type in){ return in.isa<MemRefType>(); }),
+            [](Type in){ return in.cast<MemRefType>(); }));
+      }]
+    >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the output buffers (operands).
+        Return the types of the subset of input operands that are of ranked
+        tensor type.
       }],
-      /*retTy=*/"Operation::operand_range",
-      /*methodName=*/"getOutputBuffers",
+      /*retTy=*/"SmallVector<RankedTensorType, 4>",
+      /*methodName=*/"getInputTensorTypes" ,
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        auto range = this->getOperation()->getOperands();
-        return {range.begin() + $_op.getNumInputs(),
-                range.begin() + getNumInputsAndOutputBuffers()};
+        return llvm::to_vector<4>(
+          llvm::map_range(
+            llvm::make_filter_range(
+              ValueRange(getInputs()).getTypes(),
+              [](Type in){ return in.isa<RankedTensorType>(); }),
+            [](Type in){ return in.cast<RankedTensorType>(); }));
       }]
     >,
 
     //===------------------------------------------------------------------===//
-    // Input and Output arguments handling.
+    // Output operands handling.
     //===------------------------------------------------------------------===//
     InterfaceMethod<
       /*desc=*/[{
-        Return one single buffer at position `$i`.
+        Return the `i`-th output operand.
       }],
       /*retTy=*/"Value",
-      /*methodName=*/"getBuffer",
+      /*methodName=*/"getOutput",
       /*args=*/(ins "unsigned":$i),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        assert(i < getNumInputsAndOutputBuffers() && "overflowing buffers index");
-        return this->getOperation()->getOperand(i);
+        assert(i < $_op.getNumOutputs());
+        return this->getOperation()->getOperand(i + $_op.getNumInputs());
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the number of output buffers
+        Return the `i`-th output shaped type
       }],
-      /*retTy=*/"unsigned",
-      /*methodName=*/"getNumOutputBuffers",
+      /*retTy=*/"ShapedType",
+      /*methodName=*/"getOutputShapedType",
+      /*args=*/(ins "unsigned":$i),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        return getOutput(i).getType().template cast<ShapedType>();
+      }]
+    >,
+    InterfaceMethod<
+      /*desc=*/[{
+        Return the range of output operands.
+      }],
+      /*retTy=*/"Operation::operand_range",
+      /*methodName=*/"getOutputs",
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        return $_op.getNumOutputs() - this->getOperation()->getNumResults();
+        auto start =
+          this->getOperation()->getOperands().begin() + $_op.getNumInputs();
+        return {start, start + $_op.getNumOutputs()};
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the number of inputs and outputs, irrespective of their buffer or
-        tensor type.
+        Return the OpOperands for the output operands.
       }],
-      /*retTy=*/"unsigned",
-      /*methodName=*/"getNumInputsAndOutputs",
+      /*retTy=*/" MutableArrayRef<OpOperand>",
+      /*methodName=*/"getOutputOpOperands",
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        return $_op.getNumInputs() + $_op.getNumOutputs();
+        return this->getOperation()->getOpOperands().slice(
+          getNumInputs(), getNumOutputs());
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the number of inputs, irrespective of their buffer or tensor type
-        and output buffers
+        Return the subset of output operands that are of buffer type.
       }],
-      /*retTy=*/"unsigned",
-      /*methodName=*/"getNumInputsAndOutputBuffers",
+      /*retTy=*/"SmallVector<Value, 4>",
+      /*methodName=*/"getOutputBuffers",
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        return $_op.getNumInputs() + $_op.getNumOutputs() -
-          this->getOperation()->getNumResults();
+        return llvm::to_vector<4>(llvm::make_filter_range(
+          getOutputs(), [](Value in){ return in.getType().template isa<MemRefType>(); }));
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the range over inputs (irrespective of type) and output buffers.
+        Return the `index`^th output buffer.
       }],
-      /*retTy=*/"Operation::operand_range",
-      /*methodName=*/"getInputsAndOutputBuffers",
+      /*retTy=*/"Value",
+      /*methodName=*/"getOutputBuffer",
+      /*args=*/(ins "unsigned":$index),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        assert(index < getNumOutputBuffers());
+        return getOutputBuffers()[index];
+      }]
+    >,
+    InterfaceMethod<
+      /*desc=*/[{
+        Return the subset of output operands that are of buffer type.
+      }],
+      /*retTy=*/"SmallVector<OpOperand*, 4>",
+      /*methodName=*/"getOutputBuffersOpOperands",
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        auto range = this->getOperation()->getOperands();
-        return {range.begin(), range.begin() + getNumInputsAndOutputBuffers()};
+        SmallVector<OpOperand*, 4> res;
+        res.reserve(getNumOutputs());
+        for (OpOperand &o : getOutputOpOperands())
+          if (o.get().getType().isa<MemRefType>())
+            res.push_back(&o);
+        return res;
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the range over init tensors.
+        Return the number of output buffer operands.
       }],
-      /*retTy=*/"Operation::operand_range",
-      /*methodName=*/"getInitTensors",
+      /*retTy=*/"unsigned",
+      /*methodName=*/"getNumOutputBuffers",
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        auto range = this->getOperation()->getOperands();
-        auto base = range.begin() + getNumInputsAndOutputBuffers();
-        return {base, base + $_op.getNumInitTensors()};
+        return $_op.getOutputBuffers().size();
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return one single init tensor at position `$i`.
+        Return the subset of output operands that are of tensor type.
       }],
-      /*retTy=*/"Value",
-      /*methodName=*/"getInitTensor",
-      /*args=*/(ins "unsigned":$i),
+      /*retTy=*/"SmallVector<Value, 4>",
+      /*methodName=*/"getOutputTensors",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        assert(i < $_op.getNumInitTensors() && "overflowing init tensor index");
-        return getInitTensors()[i];
+        return llvm::to_vector<4>(llvm::make_filter_range(
+          getOutputs(),
+          [](Value in){ return in.getType().template isa<RankedTensorType>(); }));
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return true if the shaped operand index `i` is the index of an init
-        tensor.
+        Return the subset of output operands that are of tensor type.
       }],
-      /*retTy=*/"bool",
-      /*methodName=*/"isIndexOfAnInitTensor",
-      /*args=*/(ins "unsigned":$i),
+      /*retTy=*/"SmallVector<OpOperand*, 4>",
+      /*methodName=*/"getOutputTensorsOpOperands",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        assert(i < $_op.getNumShapedOperands() && "overflowing shaped operand index");
-        return i >= $_op.getNumInputs() + getNumOutputBuffers();
+        SmallVector<OpOperand*, 4> res;
+        res.reserve(getNumOutputs());
+        for (OpOperand &o : getOutputOpOperands())
+          if (o.get().getType().isa<RankedTensorType>())
+            res.push_back(&o);
+        return res;
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the relative init tensor index of the shaped operand index.
+        Return the number of output tensor operands.
       }],
       /*retTy=*/"unsigned",
-      /*methodName=*/"getInitTensorIndexFromShapedIndex",
-      /*args=*/(ins "unsigned":$i),
+      /*methodName=*/"getNumOutputTensors",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        assert(isIndexOfAnInitTensor(i) && "expected an init tensor index");
-        return i - $_op.getNumInputs() - getNumOutputBuffers();
+        return $_op.getOutputTensors().size();
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the index of the given init tensor value, or `None` if the value 
-        is not part of the init tensors.
+        Return the types of the subset of output operands that are of buffer type.
       }],
-      /*retTy=*/"llvm::Optional<unsigned>",
-      /*methodName=*/"getIndexOfInitTensor",
-      /*args=*/(ins "Value":$value),
+      /*retTy=*/"SmallVector<MemRefType, 4>",
+      /*methodName=*/"getOutputBufferTypes" ,
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        auto it = llvm::find(getInitTensors(), value);
-        if (it != getInitTensors().end())
-          return it - getInitTensors().begin();
-        return llvm::None;
+        return llvm::to_vector<4>(
+          llvm::map_range(
+            llvm::make_filter_range(
+              ValueRange(getOutputs()).getTypes(),
+              [](Type in){ return in.isa<MemRefType>(); }),
+            [](Type in){ return in.cast<MemRefType>(); }));
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the number of inputs, output buffers and init tensors operands.
+        Return the types of the subset of output operands that are of ranked
+        tensor type.
       }],
-      /*retTy=*/"unsigned",
-      /*methodName=*/"getNumShapedOperands",
+      /*retTy=*/"SmallVector<RankedTensorType, 4>",
+      /*methodName=*/"getOutputTensorTypes" ,
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        return getNumInputsAndOutputBuffers() + $_op.getNumInitTensors();
+        return llvm::to_vector<4>(
+          llvm::map_range(
+            llvm::make_filter_range(
+              ValueRange(getOutputs()).getTypes(),
+              [](Type in){ return in.isa<RankedTensorType>(); }),
+            [](Type in){ return in.cast<RankedTensorType>(); }));
       }]
     >,
+
+    //===------------------------------------------------------------------===//
+    // Input and Output arguments handling.
+    //===------------------------------------------------------------------===//
     InterfaceMethod<
       /*desc=*/[{
-        Return the `i`-th shaped operand value, which can be an arbitrary input
-        tensor/buffer, init tensor or output buffer.
+        Return true if the payload uses the value loaded from `opOperand`. This
+        is useful to avoid loading from "write-only" memory that may be
+        uninitialized, as well as properly cloning "read-write" operands.
       }],
-      /*retTy=*/"Value",
-      /*methodName=*/"getShapedOperand",
-      /*args=*/(ins "unsigned":$i),
+      /*retTy=*/"bool",
+      /*methodName=*/"payloadUsesValueFromOpOperand",
+      /*args=*/(ins "OpOperand *":$opOperand),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        assert(i < $_op.getNumShapedOperands());
-        return this->getOperation()->getOperand(i);
+        unsigned bbArgNumber =
+          getNumPayloadInductionVariables() + opOperand->getOperandNumber();
+        // Safeguard against the named linalg ops that are manually defined and
+        // that only support buffer semantics: we should not be there.
+        // Such ops have an empty regionBuilder and are not constructed with a
+        // region for now. In the future they are slated to disappear.
+        assert(this->getOperation()->getNumRegions() == 1 && "unexpected "
+               "missing region (calling `payloadUsesValueFromOpOperand` on "
+               "manually defined named Linalg op?)");
+        Block &block = this->getOperation()->getRegion(0).front();
+        // Init tensors have uses.
+        return !block.getArgument(bbArgNumber).use_empty();
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the range over inputs, output buffers and init tensors.
+        Return true if the payload uses the value loaded from input operand
+        `index`.
       }],
-      /*retTy=*/"Operation::operand_range",
-      /*methodName=*/"getShapedOperands",
-      /*args=*/(ins),
+      /*retTy=*/"bool",
+      /*methodName=*/"payloadUsesValueFromInputOperandIndex",
+      /*args=*/(ins "unsigned":$index),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        auto range = this->getOperation()->getOperands();
-        return {range.begin(), range.begin() + getNumShapedOperands()};
+        return payloadUsesValueFromOpOperand(&getInputOpOperands()[index]);
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the `i`-th shaped type, there are 3 cases:
-          1. if `i < $_op.getNumInputs()` then return `getInputShapedType(i)`;
-             otherwise
-          2. if `i < getNumInputsAndOutputBuffers()` then return the
-             `getOutputBufferType(i - $_op.getNumInputs())`; otherwise
-          3. return the `i - getNumInputsAndOutputBuffers()` result type.
+        Return true if the payload uses the value loaded from output operand
+        `index`.
       }],
-      /*retTy=*/"ShapedType",
-      /*methodName=*/"getShapedType",
-      /*args=*/(ins "unsigned":$i),
+      /*retTy=*/"bool",
+      /*methodName=*/"payloadUsesValueFromOutputOperandIndex",
+      /*args=*/(ins "unsigned":$index),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        if (i < $_op.getNumInputs())
-          return getInputShapedType(i);
-        if (i < getNumInputsAndOutputBuffers())
-          return getOutputBufferType(i - $_op.getNumInputs());
-        return this->getOperation()->getResult(
-          i - getNumInputsAndOutputBuffers()).
-          getType().template cast<ShapedType>();
-      }]>,
+        return payloadUsesValueFromOpOperand(&getOutputOpOperands()[index]);
+      }]
+    >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the shaped types for all the inputs and outputs
+        Return true if `opOperand` is an init tensor. This is true when it is
+        an output tensor operand whose value is used in the payload region.
       }],
-      /*retTy=*/"SmallVector<ShapedType, 4>",
-      /*methodName=*/"getInputOutputShapedTypes",
+      /*retTy=*/"bool",
+      /*methodName=*/"isInitTensor",
+      /*args=*/(ins "OpOperand *":$opOperand),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        if (!opOperand->get().getType().template isa<RankedTensorType>())
+          return false;
+        if (opOperand->getOperandNumber() < $_op.getNumInputs())
+          return false;
+        return payloadUsesValueFromOpOperand(opOperand);
+      }]
+    >,
+    InterfaceMethod<
+      /*desc=*/[{
+        Return true if the operand at output index `index` is an init tensor.
+      }],
+      /*retTy=*/"bool",
+      /*methodName=*/"isIndexOfInitTensor",
+      /*args=*/(ins "unsigned":$index),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        assert(index < getNumOutputs());
+        return isInitTensor(
+          &this->getOperation()->getOpOperands()[$_op.getNumInputs() + index]);
+      }]
+    >,
+    InterfaceMethod<
+      /*desc=*/[{
+        Return the output operands that are init tensors.
+      }],
+      /*retTy=*/"SmallVector<Value, 4>",
+      /*methodName=*/"getInitTensors",
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        SmallVector<Type, 4> inputOutputTypes(
-            this->getOperation()->operand_type_begin(),
-            this->getOperation()->operand_type_end());
-        inputOutputTypes.append(this->getOperation()->result_type_begin(),
-                                this->getOperation()->result_type_end());
+        auto start =
+          this->getOperation()->getOpOperands().begin() + $_op.getNumInputs();
         return llvm::to_vector<4>(
-            llvm::map_range(inputOutputTypes, [](Type type) -> ShapedType {
-              return type.cast<ShapedType>();
-            }));
+          llvm::map_range(
+            llvm::make_filter_range(
+              llvm::make_range(start, start + $_op.getNumOutputs()),
+              [&](OpOperand &opOperand) {
+                return $_op.isInitTensor(&opOperand);
+              }),
+              [&](OpOperand &opOperand) {
+                return opOperand.get();
+              }));
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Return the first position of the shaped operand in the operand list.
+        Return the number of init tensor operands.
       }],
-      /*retTy=*/"Optional<unsigned>",
-      /*methodName=*/"getIndexOfShapedOperand",
-      /*args=*/(ins "Value":$value),
+      /*retTy=*/"unsigned",
+      /*methodName=*/"getNumInitTensors",
+      /*args=*/(ins),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        return getInitTensors().size();
+      }]
+    >,
+    InterfaceMethod<
+      /*desc=*/[{
+        Return the number of input and output operands.
+      }],
+      /*retTy=*/"unsigned",
+      /*methodName=*/"getNumShapedOperands",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        Optional<unsigned> inputIndex = getIndexOfInput(value);
-        if (inputIndex.hasValue()) return inputIndex.getValue();
-        Optional<unsigned> outputIndex = getIndexOfOutputBuffer(value);
-        if (outputIndex.hasValue())
-          return $_op.getNumInputs() + outputIndex.getValue();
-        Optional<unsigned> initTensorIndex = getIndexOfInitTensor(value);
-        if (initTensorIndex.hasValue())
-          return $_op.getNumInputs() + $_op.getNumOutputBuffers() + initTensorIndex.getValue();
-        return llvm::None;
+        return $_op.getNumInputs() + $_op.getNumOutputs();
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Returns the operand index given the input index. Returns None
-        of the input index is invalid.
+        Return the `i`-th shaped operand value.
       }],
-      /*retTy=*/"Optional<unsigned>",
-      /*methodName=*/"getOperandIndexForInputIndex",
-      /*args=*/(ins "unsigned":$input_index),
+      /*retTy=*/"Value",
+      /*methodName=*/"getShapedOperand",
+      /*args=*/(ins "unsigned":$i),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        if (input_index >= $_op.getNumInputs())
-          return llvm::None;
-        return input_index;
+        assert(i < $_op.getNumShapedOperands());
+        return this->getOperation()->getOperand(i);
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Returns the operand index given the output index. Returns None
-        of the output index is invalid.
+        Return the range over input and output operands.
       }],
-      /*retTy=*/"Optional<unsigned>",
-      /*methodName=*/"getOperandIndexForOutputIndex",
-      /*args=*/(ins "unsigned":$output_index),
+      /*retTy=*/"Operation::operand_range",
+      /*methodName=*/"getShapedOperands",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        if (output_index >= $_op.getNumOutputs())
-          return llvm::None;
-        return output_index + $_op.getNumInputs();
+        auto range = this->getOperation()->getOperands();
+        return {range.begin(), range.begin() + getNumShapedOperands()};
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Returns the input index given the operand index. Return None
-        if the operand index doesnt corresponding to an input.
+        Return the OpOperands for all the shaped operands.
       }],
-      /*retTy=*/"Optional<unsigned>",
-      /*methodName=*/"getInputIndex",
-      /*args=*/(ins "unsigned":$operand_index),
+      /*retTy=*/" MutableArrayRef<OpOperand>",
+      /*methodName=*/"getShapedOpOperands",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-         if (operand_index >= $_op.getNumInputs())
-           return llvm::None;
-         return operand_index;
+        return this->getOperation()->getOpOperands().take_front(
+          getNumShapedOperands());
       }]
     >,
     InterfaceMethod<
       /*desc=*/[{
-        Returns the output index given the operand index. Return None
-        if the operand index doesnt corresponding to an output.
+        Return the range over input and output operands.
       }],
-      /*retTy=*/"Optional<unsigned>",
-      /*methodName=*/"getOutputIndex",
-      /*args=*/(ins "unsigned":$operand_index),
+      /*retTy=*/"SmallVector<ShapedType, 4>",
+      /*methodName=*/"getShapedOperandTypes",
+      /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-         if (operand_index < $_op.getNumInputs() ||
-             operand_index >= $_op.getNumInputs() + $_op.getNumOutputs())
-           return llvm::None;
-         return operand_index - $_op.getNumInputs();
+        return llvm::to_vector<4>(
+          llvm::map_range(
+            getShapedOperands(),
+            [](Value v) { return v.getType().cast<ShapedType>(); }));
       }]
     >,
+    InterfaceMethod<
+      /*desc=*/[{
+        Return the `i`-th shaped type
+      }],
+      /*retTy=*/"ShapedType",
+      /*methodName=*/"getShapedType",
+      /*args=*/(ins "unsigned":$i),
+      /*methodBody=*/"",
+      /*defaultImplementation=*/[{
+        return $_op.getShapedOperand(i).getType().template cast<ShapedType>();
+      }]>,
 
     //===------------------------------------------------------------------===//
     // Other interface methods.
@@ -679,7 +797,7 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
       /*args=*/(ins "unsigned":$i),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        assert(i < getNumInputsAndOutputs());
+        assert(i < $_op.getNumShapedOperands());
         return getIndexingMaps()[i];
       }]
     >,
@@ -719,8 +837,8 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
         return this->getOperation()->getNumResults() == 0 &&
-          llvm::all_of(getInputs(),
-                       [](Value v) { return v.getType().isa<MemRefType>(); });
+          llvm::all_of(getShapedOperands(), [](Value v) {
+            return v.getType().template isa<MemRefType>(); });
       }]
     >,
     InterfaceMethod<
@@ -732,11 +850,9 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        auto isTensorType = [](Value v) {
-          return v.getType().isa<RankedTensorType>();
-        };
-        return llvm::all_of(getInputs(), isTensorType) &&
-               llvm::all_of(this->getOperation()->getResults(), isTensorType);
+        return llvm::all_of(getShapedOperands(), [](Value v) {
+          return v.getType().template isa<RankedTensorType>();
+        });
       }]
     >,
     InterfaceMethod<
@@ -748,7 +864,8 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
-        return $_op->getAttr(getSparseAttrName()).template dyn_cast_or_null<ArrayAttr>() != nullptr;
+        return $_op->getAttr(getSparseAttrName()).
+          template dyn_cast_or_null<ArrayAttr>() != nullptr;
       }]
     >,
     InterfaceMethod<
@@ -871,7 +988,7 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
   ];
 
   let extraClassDeclaration = [{
-    /// Return the flat list of all operand dimension sizes in the order they 
+    /// Return the flat list of all operand dimension sizes in the order they
     /// appear in the operands.
     SmallVector<Value, 4> createFlatListOfOperandDims(OpBuilder &, Location);
 
@@ -893,7 +1010,7 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
       for (unsigned i = 0; i < nExtraOperands; ++i) {
         res.push_back(getOperation()->getOperand(numShapedOperands + i));
         assert((res.back().getType().isSignlessIntOrIndexOrFloat()
-                || res.back().getType().isa<VectorType>()) &&
+                || res.back().getType().template isa<VectorType>()) &&
                "expected scalar or vector type");
       }
       return res;
@@ -904,7 +1021,6 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
     //========================================================================//
     void setNumInputs(unsigned num) { setOperandSegmentAt(0, num); }
     void setNumOutputBuffers(unsigned num) { setOperandSegmentAt(1, num); }
-    void setNumInitTensors(unsigned num) { setOperandSegmentAt(2, num); }
 
     private:
     void setOperandSegmentAt(unsigned idx, unsigned val) {
@@ -916,6 +1032,8 @@ def LinalgStructuredInterface : OpInterface<"LinalgOp"> {
       getOperation()->setAttr("operand_segment_sizes", newAttr);
     }
   }];
+
+  let verify = [{ return detail::verifyStructuredOpInterface($_op); }];
 }
 
 #endif // LINALG_IR_STRUCTURED_OPS_INTERFACE
diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h b/mlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h
deleted file mode 100644
index adfa6a6f1af93..0000000000000
--- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgTraits.h
+++ /dev/null
@@ -1,166 +0,0 @@
-//===- LinalgTraits.h - Linalg Traits ---------------------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef MLIR_DIALECT_LINALG_LINALGTRAITS_H_
-#define MLIR_DIALECT_LINALG_LINALGTRAITS_H_
-
-#include "mlir/Dialect/Linalg/IR/LinalgTypes.h"
-#include "mlir/Dialect/Utils/StructuredOpsUtils.h"
-#include "mlir/IR/AffineMap.h"
-#include "mlir/IR/BuiltinOps.h"
-#include "mlir/IR/BuiltinTypes.h"
-#include "mlir/IR/OpDefinition.h"
-#include "mlir/Support/LLVM.h"
-
-namespace mlir {
-namespace OpTrait {
-namespace linalg {
-
-/// This class provides the API for ops that are known to have a specified
-/// number of inputs, all passed as operands. Use as a trait as follows:
-///
-///   class DotOp : public Op<DotOp, OpTrait::NInputs<2>::Impl> {
-///
-template <unsigned N> class NInputs {
-public:
-  template <typename ConcreteType>
-  class Impl : public OpTrait::TraitBase<ConcreteType, NInputs<N>::Impl> {
-  public:
-    static unsigned getNumInputs() { return N; }
-  };
-};
-
-/// This class provides the API for ops that are known to not have init tensor
-/// operands. Use as a trait as follows:
-///
-///   class CopyOp : public Op<CopyOp, OpTrait::ZeroInitTensors> {
-///
-template <typename ConcreteType>
-class ZeroInitTensors : public TraitBase<ConcreteType, ZeroInitTensors> {
-public:
-  static unsigned getNumInitTensors() { return 0; }
-};
-
-/// This class provides the API for ops that are known to have a specified
-/// number of outputs, all passed as operands. Use as a trait as follows:
-///
-///   class DotOp : public Op<DotOp, OpTrait::NOutputs<2>::Impl> {
-///
-template <unsigned N> class NOutputs {
-public:
-  template <typename ConcreteType>
-  class Impl : public OpTrait::TraitBase<ConcreteType, NOutputs<N>::Impl> {
-  public:
-    static unsigned getNumOutputs() { return N; }
-  };
-};
-
-/// This class provides a verifier for structured ops that are known to operate
-/// on buffers or tensors. This trait must be used in conjunction with an op
-/// definition or a trait that provides the methods `getNumInputs` and
-/// `getNumOutputs`. Use as a trait as follows:
-///
-///   class DotOp : public Op<DotOp, OpTrait::StructuredOpTraits> {
-///
-template <typename ConcreteType>
-class StructuredOpTraits
-    : public OpTrait::TraitBase<ConcreteType, StructuredOpTraits> {
-public:
-  static LogicalResult verifyTrait(Operation *op) {
-    ConcreteType concreteOp = cast<ConcreteType>(op);
-    auto nOperands = concreteOp.getNumInputsAndOutputBuffers();
-    if (failed(OpTrait::impl::verifyAtLeastNOperands(op, nOperands)))
-      return failure();
-    if (op->getNumResults() > concreteOp.getNumOutputs())
-      return op->emitError("unexpected #results > #outputs");
-    return success();
-  }
-};
-
-/// This class provides a verifier for structured ops that are known to operate
-/// on buffers or tensors and that support `ins`, `outs` and `init` arguments.
-/// This trait must be used in conjunction with an op definition or a trait that
-/// provides the methods `getNumInputs` and `getNumOutputs`.
-///
-/// Use as a trait as follows:
-///
-///   class MatmulOp : public Op<MatmulOp, OpTrait::NamedStructuredOpTrait> {
-///
-template <typename ConcreteType>
-class NamedStructuredOpTrait
-    : public OpTrait::TraitBase<ConcreteType, NamedStructuredOpTrait> {
-public:
-  unsigned getNumInputs() {
-    return cast<ConcreteType>(this->getOperation()).inputs().size();
-  }
-  unsigned getNumInitTensors() {
-    return cast<ConcreteType>(this->getOperation()).init_tensors().size();
-  }
-  unsigned getNumOutputs() {
-    ConcreteType concreteOp = cast<ConcreteType>(this->getOperation());
-    return concreteOp.output_buffers().size() +
-           concreteOp.result_tensors().size();
-  }
-  static LogicalResult verifyTrait(Operation *op) {
-    ConcreteType concreteOp = cast<ConcreteType>(op);
-    unsigned nInputAndBufferOperands =
-        concreteOp.getNumInputsAndOutputBuffers();
-    if (failed(
-            OpTrait::impl::verifyAtLeastNOperands(op, nInputAndBufferOperands)))
-      return failure();
-
-    SmallVector<AffineExpr, 4> redDims;
-    concreteOp.getReductionDims(redDims);
-    // If no result and no reduction, only check there is no init tensor and we
-    // are done.
-    if (redDims.empty() || op->getNumResults() == 0) {
-      if (!concreteOp.init_tensors().empty())
-        return op->emitError("expected empty `init` when op has no "
-                             "results or no reduction dims");
-      return success();
-    }
-
-    // Only a single tensor result supported atm.
-    if (op->getNumResults() != 1)
-      return op->emitError(
-          "expected single tensor result when reduction present");
-
-    if (concreteOp.init_tensors().size() != op->getNumResults())
-      return op->emitError(
-          "expected #init tensors to match #results when reduction present");
-
-    for (unsigned idx = 0, e = op->getNumResults(); idx < e; ++idx)
-      if (concreteOp.init_tensors()[idx].getType() != op->getResultTypes()[idx])
-        return op->emitError("expected init tensor #")
-               << idx << " of the same type as result #" << idx;
-
-    // Output tensor indexing map may not depend on reduction index.
-    // TODO: this is not yet tested. Add a test when linalg.generic switches to
-    // this representation.
-    for (unsigned idx = 0, e = concreteOp.getNumOutputs(); idx < e; ++idx) {
-      AffineMap outputMap = concreteOp.getOutputIndexingMap(idx);
-      for (auto expr : outputMap.getResults()) {
-        for (auto dim : redDims) {
-          unsigned pos = dim.cast<AffineDimExpr>().getPosition();
-          if (expr.isFunctionOfDim(pos))
-            return op->emitError(
-                       "unexpected single tensor output indexing map ")
-                   << "is function of reduction dim @" << pos;
-        }
-      }
-    }
-
-    return success();
-  }
-};
-
-} // namespace linalg
-} // namespace OpTrait
-} // namespace mlir
-
-#endif // MLIR_DIALECT_LINALG_LINALGTRAITS_H_
diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
index f915afcf32c95..6c6230f0c2e8a 100644
--- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
+++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
@@ -185,6 +185,11 @@ def WsLoopOp : OpenMP_Op<"wsloop", [AttrSizedOperandSegments]> {
   ];
 
   let regions = (region AnyRegion:$region);
+
+  let extraClassDeclaration = [{
+    /// Returns the number of loops in the workshape loop nest.
+    unsigned getNumLoops() { return lowerBound().size(); }
+  }];
 }
 
 def YieldOp : OpenMP_Op<"yield", [NoSideEffect, ReturnLike, Terminator,
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h
new file mode 100644
index 0000000000000..1921dbbcfc70e
--- /dev/null
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h
@@ -0,0 +1,31 @@
+//===- SPIRVGLSLCanonicalization.h - GLSL-specific patterns -----*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares a function to register SPIR-V GLSL-specific
+// canonicalization patterns.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_DIALECT_SPIRV_IR_SPIRVGLSLCANONICALIZATION_H_
+#define MLIR_DIALECT_SPIRV_IR_SPIRVGLSLCANONICALIZATION_H_
+
+#include "mlir/IR/MLIRContext.h"
+#include "mlir/IR/PatternMatch.h"
+
+//===----------------------------------------------------------------------===//
+// GLSL canonicalization patterns
+//===----------------------------------------------------------------------===//
+
+namespace mlir {
+namespace spirv {
+void populateSPIRVGLSLCanonicalizationPatterns(
+    mlir::OwningRewritePatternList &results, mlir::MLIRContext *context);
+} // namespace spirv
+} // namespace mlir
+
+#endif // MLIR_DIALECT_SPIRV_IR_SPIRVGLSLCANONICALIZATION_H_
diff --git a/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td b/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
index 7af44f8435ffa..ba78db68214f4 100644
--- a/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
+++ b/mlir/include/mlir/Dialect/StandardOps/IR/Ops.td
@@ -69,7 +69,9 @@ class CastOp<string mnemonic, list<OpTrait> traits = []> :
 
 // Base class for arithmetic cast operations.
 class ArithmeticCastOp<string mnemonic, list<OpTrait> traits = []> :
-    CastOp<mnemonic, !listconcat(traits, [ElementwiseMappable])> {
+    CastOp<mnemonic,
+    !listconcat(traits, [ElementwiseMappable,
+                         DeclareOpInterfaceMethods<VectorUnrollOpInterface>])> {
 }
 
 // Base class for unary ops. Requires single operand and result. Individual
@@ -104,6 +106,7 @@ class ArithmeticOp<string mnemonic, list<OpTrait> traits = []> :
     Op<StandardOps_Dialect, mnemonic,
        !listconcat(traits, [NoSideEffect,
                             SameOperandsAndResultType,
+                            DeclareOpInterfaceMethods<VectorUnrollOpInterface>,
                             ElementwiseMappable])> {
 
   let results = (outs AnyType:$result);
@@ -992,6 +995,7 @@ def CmpFPredicateAttr : I64EnumAttr<
 
 def CmpFOp : Std_Op<"cmpf",
     [NoSideEffect, SameTypeOperands, ElementwiseMappable,
+     DeclareOpInterfaceMethods<VectorUnrollOpInterface>,
      TypesMatchWith<
        "result type has i1 element type and same shape as operands",
        "lhs", "result", "getI1SameShape($_self)">]> {
@@ -1076,6 +1080,7 @@ def CmpIPredicateAttr : I64EnumAttr<
 
 def CmpIOp : Std_Op<"cmpi",
     [NoSideEffect, SameTypeOperands, ElementwiseMappable,
+     DeclareOpInterfaceMethods<VectorUnrollOpInterface>,
      TypesMatchWith<
        "result type has i1 element type and same shape as operands",
        "lhs", "result", "getI1SameShape($_self)">]> {
@@ -2548,7 +2553,7 @@ def RsqrtOp : FloatUnaryOp<"rsqrt"> {
 
 def SelectOp : Std_Op<"select", [NoSideEffect,
      AllTypesMatch<["true_value", "false_value", "result"]>,
-     ElementwiseMappable]> {
+     ElementwiseMappable, DeclareOpInterfaceMethods<VectorUnrollOpInterface>]> {
   let summary = "select operation";
   let description = [{
     The `select` operation chooses one value based on a binary condition
@@ -2779,7 +2784,8 @@ def SignedShiftRightOp : IntArithmeticOp<"shift_right_signed"> {
 //===----------------------------------------------------------------------===//
 
 def SignExtendIOp : Std_Op<"sexti",
-    [NoSideEffect, ElementwiseMappable]> {
+    [NoSideEffect, ElementwiseMappable,
+    DeclareOpInterfaceMethods<VectorUnrollOpInterface>]> {
   let summary = "integer sign extension operation";
   let description = [{
     The integer sign extension operation takes an integer input of
@@ -3595,7 +3601,9 @@ def TransposeOp : Std_Op<"transpose", [NoSideEffect]>,
 // TruncateIOp
 //===----------------------------------------------------------------------===//
 
-def TruncateIOp : Std_Op<"trunci", [NoSideEffect, ElementwiseMappable]> {
+def TruncateIOp : Std_Op<"trunci",
+  [NoSideEffect, ElementwiseMappable,
+   DeclareOpInterfaceMethods<VectorUnrollOpInterface>,]> {
   let summary = "integer truncation operation";
   let description = [{
     The integer truncation operation takes an integer input of
@@ -3862,7 +3870,9 @@ def XOrOp : IntArithmeticOp<"xor", [Commutative]> {
 // ZeroExtendIOp
 //===----------------------------------------------------------------------===//
 
-def ZeroExtendIOp : Std_Op<"zexti", [NoSideEffect, ElementwiseMappable]> {
+def ZeroExtendIOp : Std_Op<"zexti",
+  [NoSideEffect, ElementwiseMappable,
+   DeclareOpInterfaceMethods<VectorUnrollOpInterface>,]> {
   let summary = "integer zero extension operation";
   let description = [{
     The integer zero extension operation takes an integer input of
diff --git a/mlir/include/mlir/Dialect/Vector/VectorOps.h b/mlir/include/mlir/Dialect/Vector/VectorOps.h
index 95964665ced64..5540a56a4043c 100644
--- a/mlir/include/mlir/Dialect/Vector/VectorOps.h
+++ b/mlir/include/mlir/Dialect/Vector/VectorOps.h
@@ -126,7 +126,7 @@ namespace impl {
 /// Build the default minor identity map suitable for a vector transfer. This
 /// also handles the case memref<... x vector<...>> -> vector<...> in which the
 /// rank of the identity map must take the vector element type into account.
-AffineMap getTransferMinorIdentityMap(MemRefType memRefType,
+AffineMap getTransferMinorIdentityMap(ShapedType shapedType,
                                       VectorType vectorType);
 } // namespace impl
 } // end namespace vector
diff --git a/mlir/include/mlir/Dialect/Vector/VectorOps.td b/mlir/include/mlir/Dialect/Vector/VectorOps.td
index de77e3b034830..e031f87cfb8e5 100644
--- a/mlir/include/mlir/Dialect/Vector/VectorOps.td
+++ b/mlir/include/mlir/Dialect/Vector/VectorOps.td
@@ -271,6 +271,7 @@ def Vector_BroadcastOp :
   }];
   let assemblyFormat = "$source attr-dict `:` type($source) `to` type($vector)";
   let hasFolder = 1;
+  let hasCanonicalizer = 1;
 }
 
 def Vector_ShuffleOp :
@@ -1056,7 +1057,7 @@ def Vector_TransferReadOp :
       DeclareOpInterfaceMethods<VectorTransferOpInterface>,
       DeclareOpInterfaceMethods<VectorUnrollOpInterface, ["getShapeForUnroll"]>
     ]>,
-    Arguments<(ins AnyMemRef:$memref, Variadic<Index>:$indices,
+    Arguments<(ins AnyShaped:$source, Variadic<Index>:$indices,
                AffineMapAttr:$permutation_map, AnyType:$padding,
                OptionalAttr<BoolArrayAttr>:$masked)>,
     Results<(outs AnyVector:$vector)> {
@@ -1065,15 +1066,16 @@ def Vector_TransferReadOp :
 
   let description = [{
     The `vector.transfer_read` op performs a read from a slice within a
-    [MemRef](../LangRef.md#memref-type) supplied as its first operand
-    into a [vector](../LangRef.md#vector-type) of the same base elemental type.
+    [MemRef](../LangRef.md#memref-type) or a Ranked
+    [Tensor](../LangRef.md#tensor-type) supplied as its first operand into a
+    [vector](../LangRef.md#vector-type) of the same base elemental type.
 
-    A memref operand with vector element type, must have its vector element
-    type match a suffix (shape and element type) of the vector (e.g.
+    A memref/tensor operand with vector element type, must have its vector
+    element type match a suffix (shape and element type) of the vector (e.g.
     memref<3x2x6x4x3xf32>, vector<1x1x4x3xf32>).
 
-    The slice is further defined by a full-rank index within the MemRef,
-    supplied as the operands `2 .. 1 + rank(memref)`.
+    The slice is further defined by a full-rank index within the MemRef/Tensor,
+    supplied as the operands `2 .. 1 + rank(memref/tensor)`.
 
     The permutation_map [attribute](../LangRef.md#attributes) is an
     [affine-map](Affine.md#affine-maps) which specifies the transposition on the
@@ -1084,8 +1086,9 @@ def Vector_TransferReadOp :
     The size of the slice is specified by the size of the vector, given as the
     return type.
 
-    An `ssa-value` of the same elemental type as the MemRef is provided as the
-    last operand to specify padding in the case of out-of-bounds accesses.
+    An `ssa-value` of the same elemental type as the MemRef/Tensor is provided
+    as the last operand to specify padding in the case of out-of-bounds
+    accesses.
 
     An optional boolean array attribute is provided to specify which dimensions
     of the transfer need masking. When a dimension is specified as not requiring
@@ -1196,17 +1199,22 @@ def Vector_TransferReadOp :
     %4 = vector.transfer_read %arg1[%c3, %c3], %vf0
       {permutation_map = (d0, d1)->(d0, d1)}
         : memref<?x?xvector<4x3xf32>>, vector<1x1x4x3xf32>
+
+    // Read from a tensor with vector element type.
+    %4 = vector.transfer_read %arg1[%c3, %c3], %vf0
+      {permutation_map = (d0, d1)->(d0, d1)}
+        : tensor<?x?xvector<4x3xf32>>, vector<1x1x4x3xf32>
     ```
   }];
 
   let builders = [
     // Builder that sets padding to zero.
-    OpBuilderDAG<(ins "VectorType":$vector, "Value":$memref,
+    OpBuilderDAG<(ins "VectorType":$vector, "Value":$source,
       "ValueRange":$indices, "AffineMap":$permutationMap,
       CArg<"ArrayRef<bool>", "{}">:$maybeMasked)>,
     // Builder that sets permutation map (resp. padding) to
     // 'getMinorIdentityMap' (resp. zero).
-    OpBuilderDAG<(ins "VectorType":$vector, "Value":$memref,
+    OpBuilderDAG<(ins "VectorType":$vector, "Value":$source,
       "ValueRange":$indices, CArg<"ArrayRef<bool>", "{}">:$maybeMasked)>
   ];
 
@@ -1217,26 +1225,29 @@ def Vector_TransferWriteOp :
   Vector_Op<"transfer_write", [
       DeclareOpInterfaceMethods<VectorTransferOpInterface>,
       DeclareOpInterfaceMethods<VectorUnrollOpInterface, ["getShapeForUnroll"]>
-    ]>,
-    Arguments<(ins AnyVector:$vector, AnyMemRef:$memref,
+  ]>,
+    Arguments<(ins AnyVector:$vector, AnyShaped:$source,
                Variadic<Index>:$indices,
                AffineMapAttr:$permutation_map,
-               OptionalAttr<BoolArrayAttr>:$masked)> {
+               OptionalAttr<BoolArrayAttr>:$masked)>,
+    Results<(outs Optional<AnyRankedTensor>:$result)> {
 
   let summary = "The vector.transfer_write op writes a supervector to memory.";
 
   let description = [{
     The `vector.transfer_write` op performs a write from a
     [vector](../LangRef.md#vector-type), supplied as its first operand, into a
-    slice within a [MemRef](../LangRef.md#memref-type) of the same base
-    elemental type, supplied as its second operand.
+    slice within a [MemRef](../LangRef.md#memref-type) or a Ranked
+    [Tensor](../LangRef.md#tensor-type) of the same base elemental type,
+    supplied as its second operand.
 
-    A vector memref operand must have its vector element type match a suffix
-    (shape and element type) of the vector (e.g. memref<3x2x6x4x3xf32>,
-    vector<1x1x4x3xf32>).
+    A vector memref/tensor operand must have its vector element type match a
+    suffix (shape and element type) of the vector (e.g. memref<3x2x6x4x3xf32>,
+    vector<1x1x4x3xf32>). If the operand is a tensor, the operation returns a
+    new tensor of the same type.
 
-    The slice is further defined by a full-rank index within the MemRef,
-    supplied as the operands `3 .. 2 + rank(memref)`.
+    The slice is further defined by a full-rank index within the MemRef/Tensor,
+    supplied as the operands `3 .. 2 + rank(memref/tensor)`.
 
     The permutation_map [attribute](../LangRef.md#attributes) is an
     [affine-map](Affine.md#affine-maps) which specifies the transposition on the
@@ -1280,15 +1291,24 @@ def Vector_TransferWriteOp :
     vector.transfer_write %4, %arg1[%c3, %c3]
       {permutation_map = (d0, d1)->(d0, d1)}
         : vector<1x1x4x3xf32>, memref<?x?xvector<4x3xf32>>
+
+    // return a tensor where the vector is inserted into the source tensor.
+    %5 = vector.transfer_write %4, %arg1[%c3, %c3]
+      {permutation_map = (d0, d1)->(d0, d1)}
+        : vector<1x1x4x3xf32>, tensor<?x?xvector<4x3xf32>>
     ```
   }];
 
   let builders = [
     // Builder that sets permutation map to 'getMinorIdentityMap'.
-    OpBuilderDAG<(ins "Value":$vector, "Value":$memref, "ValueRange":$indices,
+    OpBuilderDAG<(ins "Value":$vector, "Value":$source, "ValueRange":$indices,
       CArg<"ArrayRef<bool>", "{}">:$maybeMasked)>,
-    OpBuilderDAG<(ins "Value":$vector, "Value":$memref, "ValueRange":$indices,
+    OpBuilderDAG<(ins "Value":$vector, "Value":$source, "ValueRange":$indices,
       "AffineMap":$permutationMap)>,
+    OpBuilderDAG<(ins "Value":$vector, "Value":$source, "ValueRange":$indices,
+      "AffineMapAttr":$permutationMap, "ArrayAttr":$masked)>,
+    OpBuilderDAG<(ins "Value":$vector, "Value":$source, "ValueRange":$indices,
+      "AffineMap":$permutationMap, "ArrayAttr":$masked)>,
   ];
 
   let hasFolder = 1;
diff --git a/mlir/include/mlir/Dialect/Vector/VectorUtils.h b/mlir/include/mlir/Dialect/Vector/VectorUtils.h
index f70fba819b66d..a06bc8cf65622 100644
--- a/mlir/include/mlir/Dialect/Vector/VectorUtils.h
+++ b/mlir/include/mlir/Dialect/Vector/VectorUtils.h
@@ -20,9 +20,9 @@ class AffineApplyOp;
 class AffineForOp;
 class AffineMap;
 class Location;
-class MemRefType;
 class OpBuilder;
 class Operation;
+class ShapedType;
 class Value;
 class VectorType;
 class VectorTransferOpInterface;
@@ -157,7 +157,7 @@ makePermutationMap(Operation *op, ArrayRef<Value> indices,
 /// Build the default minor identity map suitable for a vector transfer. This
 /// also handles the case memref<... x vector<...>> -> vector<...> in which the
 /// rank of the identity map must take the vector element type into account.
-AffineMap getTransferMinorIdentityMap(MemRefType memRefType,
+AffineMap getTransferMinorIdentityMap(ShapedType shapedType,
                                       VectorType vectorType);
 
 /// Return true if we can prove that the transfer operations access disjoint
diff --git a/mlir/include/mlir/ExecutionEngine/AsyncRuntime.h b/mlir/include/mlir/ExecutionEngine/AsyncRuntime.h
index e3d90198f36c3..0fe44cd1c1273 100644
--- a/mlir/include/mlir/ExecutionEngine/AsyncRuntime.h
+++ b/mlir/include/mlir/ExecutionEngine/AsyncRuntime.h
@@ -45,6 +45,12 @@ typedef struct AsyncToken AsyncToken;
 // Runtime implementation of `async.group` data type.
 typedef struct AsyncGroup AsyncGroup;
 
+// Runtime implementation of `async.value` data type.
+typedef struct AsyncValue AsyncValue;
+
+// Async value payload stored in a memory owned by the async.value.
+using ValueStorage = void *;
+
 // Async runtime uses LLVM coroutines to represent asynchronous tasks. Task
 // function is a coroutine handle and a resume function that continue coroutine
 // execution from a suspension point.
@@ -66,6 +72,13 @@ extern "C" MLIR_ASYNCRUNTIME_EXPORT void
 // Create a new `async.token` in not-ready state.
 extern "C" MLIR_ASYNCRUNTIME_EXPORT AsyncToken *mlirAsyncRuntimeCreateToken();
 
+// Create a new `async.value` in not-ready state. Size parameter specifies the
+// number of bytes that will be allocated for the async value storage. Storage
+// is owned by the `async.value` and deallocated when the async value is
+// destructed (reference count drops to zero).
+extern "C" MLIR_ASYNCRUNTIME_EXPORT AsyncValue *
+    mlirAsyncRuntimeCreateValue(int32_t);
+
 // Create a new `async.group` in empty state.
 extern "C" MLIR_ASYNCRUNTIME_EXPORT AsyncGroup *mlirAsyncRuntimeCreateGroup();
 
@@ -76,14 +89,26 @@ mlirAsyncRuntimeAddTokenToGroup(AsyncToken *, AsyncGroup *);
 extern "C" MLIR_ASYNCRUNTIME_EXPORT void
 mlirAsyncRuntimeEmplaceToken(AsyncToken *);
 
+// Switches `async.value` to ready state and runs all awaiters.
+extern "C" MLIR_ASYNCRUNTIME_EXPORT void
+mlirAsyncRuntimeEmplaceValue(AsyncValue *);
+
 // Blocks the caller thread until the token becomes ready.
 extern "C" MLIR_ASYNCRUNTIME_EXPORT void
 mlirAsyncRuntimeAwaitToken(AsyncToken *);
 
+// Blocks the caller thread until the value becomes ready.
+extern "C" MLIR_ASYNCRUNTIME_EXPORT void
+mlirAsyncRuntimeAwaitValue(AsyncValue *);
+
 // Blocks the caller thread until the elements in the group become ready.
 extern "C" MLIR_ASYNCRUNTIME_EXPORT void
 mlirAsyncRuntimeAwaitAllInGroup(AsyncGroup *);
 
+// Returns a pointer to the storage owned by the async value.
+extern "C" MLIR_ASYNCRUNTIME_EXPORT ValueStorage
+mlirAsyncRuntimeGetValueStorage(AsyncValue *);
+
 // Executes the task (coro handle + resume function) in one of the threads
 // managed by the runtime.
 extern "C" MLIR_ASYNCRUNTIME_EXPORT void mlirAsyncRuntimeExecute(CoroHandle,
@@ -94,6 +119,11 @@ extern "C" MLIR_ASYNCRUNTIME_EXPORT void mlirAsyncRuntimeExecute(CoroHandle,
 extern "C" MLIR_ASYNCRUNTIME_EXPORT void
 mlirAsyncRuntimeAwaitTokenAndExecute(AsyncToken *, CoroHandle, CoroResume);
 
+// Executes the task (coro handle + resume function) in one of the threads
+// managed by the runtime after the value becomes ready.
+extern "C" MLIR_ASYNCRUNTIME_EXPORT void
+mlirAsyncRuntimeAwaitValueAndExecute(AsyncValue *, CoroHandle, CoroResume);
+
 // Executes the task (coro handle + resume function) in one of the threads
 // managed by the runtime after the all members of the group become ready.
 extern "C" MLIR_ASYNCRUNTIME_EXPORT void
diff --git a/mlir/include/mlir/IR/ImplicitLocOpBuilder.h b/mlir/include/mlir/IR/ImplicitLocOpBuilder.h
new file mode 100644
index 0000000000000..2dc7c34f4e855
--- /dev/null
+++ b/mlir/include/mlir/IR/ImplicitLocOpBuilder.h
@@ -0,0 +1,123 @@
+//===- ImplicitLocOpBuilder.h - Convenience OpBuilder -----------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Helper class to create ops with a modally set location.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef MLIR_IR_IMPLICITLOCOPBUILDER_H
+#define MLIR_IR_IMPLICITLOCOPBUILDER_H
+
+#include "mlir/IR/Builders.h"
+
+namespace mlir {
+
+/// ImplictLocOpBuilder maintains a 'current location', allowing use of the
+/// create<> method without specifying the location.  It is otherwise the same
+/// as OpBuilder.
+class ImplicitLocOpBuilder : public mlir::OpBuilder {
+public:
+  /// Create an ImplicitLocOpBuilder using the insertion point and listener from
+  /// an existing OpBuilder.
+  ImplicitLocOpBuilder(Location loc, const OpBuilder &builder)
+      : OpBuilder(builder), curLoc(loc) {}
+
+  /// OpBuilder has a bunch of convenience constructors - we support them all
+  /// with the additional Location.
+  template <typename T>
+  ImplicitLocOpBuilder(Location loc, T &&operand, Listener *listener = nullptr)
+      : OpBuilder(std::forward<T>(operand), listener), curLoc(loc) {}
+
+  ImplicitLocOpBuilder(Location loc, Block *block, Block::iterator insertPoint,
+                       Listener *listener = nullptr)
+      : OpBuilder(block, insertPoint, listener), curLoc(loc) {}
+
+  /// Create a builder and set the insertion point to before the first operation
+  /// in the block but still inside the block.
+  static ImplicitLocOpBuilder atBlockBegin(Location loc, Block *block,
+                                           Listener *listener = nullptr) {
+    return ImplicitLocOpBuilder(loc, block, block->begin(), listener);
+  }
+
+  /// Create a builder and set the insertion point to after the last operation
+  /// in the block but still inside the block.
+  static ImplicitLocOpBuilder atBlockEnd(Location loc, Block *block,
+                                         Listener *listener = nullptr) {
+    return ImplicitLocOpBuilder(loc, block, block->end(), listener);
+  }
+
+  /// Create a builder and set the insertion point to before the block
+  /// terminator.
+  static ImplicitLocOpBuilder atBlockTerminator(Location loc, Block *block,
+                                                Listener *listener = nullptr) {
+    auto *terminator = block->getTerminator();
+    assert(terminator != nullptr && "the block has no terminator");
+    return ImplicitLocOpBuilder(loc, block, Block::iterator(terminator),
+                                listener);
+  }
+
+  /// Accessors for the implied location.
+  Location getLoc() const { return curLoc; }
+  void setLoc(Location loc) { curLoc = loc; }
+
+  // We allow clients to use the explicit-loc version of create as well.
+  using OpBuilder::create;
+  using OpBuilder::createOrFold;
+
+  /// Create an operation of specific op type at the current insertion point and
+  /// location.
+  template <typename OpTy, typename... Args>
+  OpTy create(Args &&... args) {
+    return OpBuilder::create<OpTy>(curLoc, std::forward<Args>(args)...);
+  }
+
+  /// Create an operation of specific op type at the current insertion point,
+  /// and immediately try to fold it. This functions populates 'results' with
+  /// the results after folding the operation.
+  template <typename OpTy, typename... Args>
+  void createOrFold(llvm::SmallVectorImpl<Value> &results, Args &&... args) {
+    OpBuilder::createOrFold<OpTy>(results, curLoc, std::forward<Args>(args)...);
+  }
+
+  /// Overload to create or fold a single result operation.
+  template <typename OpTy, typename... Args>
+  typename std::enable_if<OpTy::template hasTrait<mlir::OpTrait::OneResult>(),
+                          Value>::type
+  createOrFold(Args &&... args) {
+    return OpBuilder::createOrFold<OpTy>(curLoc, std::forward<Args>(args)...);
+  }
+
+  /// Overload to create or fold a zero result operation.
+  template <typename OpTy, typename... Args>
+  typename std::enable_if<OpTy::template hasTrait<mlir::OpTrait::ZeroResult>(),
+                          OpTy>::type
+  createOrFold(Args &&... args) {
+    return OpBuilder::createOrFold<OpTy>(curLoc, std::forward<Args>(args)...);
+  }
+
+  /// This builder can also be used to emit diagnostics to the current location.
+  mlir::InFlightDiagnostic
+  emitError(const llvm::Twine &message = llvm::Twine()) {
+    return mlir::emitError(curLoc, message);
+  }
+  mlir::InFlightDiagnostic
+  emitWarning(const llvm::Twine &message = llvm::Twine()) {
+    return mlir::emitWarning(curLoc, message);
+  }
+  mlir::InFlightDiagnostic
+  emitRemark(const llvm::Twine &message = llvm::Twine()) {
+    return mlir::emitRemark(curLoc, message);
+  }
+
+private:
+  Location curLoc;
+};
+
+} // namespace mlir
+
+#endif // MLIR_IR_IMPLICITLOCOPBUILDER_H
\ No newline at end of file
diff --git a/mlir/include/mlir/IR/OpBase.td b/mlir/include/mlir/IR/OpBase.td
index 552ac75bfee5d..857a652f17d95 100644
--- a/mlir/include/mlir/IR/OpBase.td
+++ b/mlir/include/mlir/IR/OpBase.td
@@ -175,8 +175,12 @@ class Constraint<Pred pred, string desc = ""> {
 // are considered as uncategorized constraints.
 
 // Subclass for constraints on a type.
-class TypeConstraint<Pred predicate, string description = ""> :
-    Constraint<predicate, description>;
+class TypeConstraint<Pred predicate, string description = "",
+                     string cppClassNameParam = "::mlir::Type"> :
+    Constraint<predicate, description> {
+  // The name of the C++ Type class if known, or Type if not.
+  string cppClassName = cppClassNameParam;
+}
 
 // Subclass for constraints on an attribute.
 class AttrConstraint<Pred predicate, string description = ""> :
@@ -285,8 +289,9 @@ class Dialect {
 //===----------------------------------------------------------------------===//
 
 // A type, carries type constraints.
-class Type<Pred condition, string descr = ""> :
-    TypeConstraint<condition, descr> {
+class Type<Pred condition, string descr = "",
+           string cppClassName = "::mlir::Type"> :
+    TypeConstraint<condition, descr, cppClassName> {
   string typeDescription = "";
   string builderCall = "";
 }
@@ -299,8 +304,9 @@ class TypeAlias<Type t, string description = t.description> :
 }
 
 // A type of a specific dialect.
-class DialectType<Dialect d, Pred condition, string descr = ""> :
-    Type<condition, descr> {
+class DialectType<Dialect d, Pred condition, string descr = "",
+                  string cppClassName = "::mlir::Type"> :
+    Type<condition, descr, cppClassName> {
   Dialect dialect = d;
 }
 
@@ -331,11 +337,13 @@ class BuildableType<code builder> {
 def AnyType : Type<CPred<"true">, "any type">;
 
 // None type
-def NoneType : Type<CPred<"$_self.isa<::mlir::NoneType>()">, "none type">,
+def NoneType : Type<CPred<"$_self.isa<::mlir::NoneType>()">, "none type",
+                    "::mlir::NoneType">,
       BuildableType<"$_builder.getType<::mlir::NoneType>()">;
 
 // Any type from the given list
-class AnyTypeOf<list<Type> allowedTypes, string description = ""> : Type<
+class AnyTypeOf<list<Type> allowedTypes, string description = "",
+                string cppClassName = "::mlir::Type"> : Type<
     // Satisfy any of the allowed type's condition
     Or<!foreach(allowedtype, allowedTypes, allowedtype.predicate)>,
     !if(!eq(description, ""),
@@ -345,7 +353,8 @@ class AnyTypeOf<list<Type> allowedTypes, string description = ""> : Type<
 // Integer types.
 
 // Any integer type irrespective of its width and signedness semantics.
-def AnyInteger : Type<CPred<"$_self.isa<::mlir::IntegerType>()">, "integer">;
+def AnyInteger : Type<CPred<"$_self.isa<::mlir::IntegerType>()">, "integer",
+                      "::mlir::IntegerType">;
 
 // Any integer type (regardless of signedness semantics) of a specific width.
 class AnyI<int width>
@@ -355,7 +364,8 @@ class AnyI<int width>
 
 class AnyIntOfWidths<list<int> widths> :
     AnyTypeOf<!foreach(w, widths, AnyI<w>),
-              StrJoinInt<widths, "/">.result # "-bit integer">;
+              StrJoinInt<widths, "/">.result # "-bit integer",
+              "::mlir::IntegerType">;
 
 def AnyI1  : AnyI<1>;
 def AnyI8  : AnyI<8>;
@@ -365,12 +375,13 @@ def AnyI64 : AnyI<64>;
 
 // Any signless integer type irrespective of its width.
 def AnySignlessInteger : Type<
-  CPred<"$_self.isSignlessInteger()">, "signless integer">;
+  CPred<"$_self.isSignlessInteger()">, "signless integer",
+        "::mlir::IntegerType">;
 
 // Signless integer type of a specific width.
 class I<int width>
     : Type<CPred<"$_self.isSignlessInteger(" # width # ")">,
-                  width # "-bit signless integer">,
+                  width # "-bit signless integer", "::mlir::IntegerType">,
       BuildableType<"$_builder.getIntegerType(" # width # ")"> {
   int bitwidth = width;
 }
@@ -392,7 +403,7 @@ def AnySignedInteger : Type<
 // Signed integer type of a specific width.
 class SI<int width>
     : Type<CPred<"$_self.isSignedInteger(" # width # ")">,
-                  width # "-bit signed integer">,
+                  width # "-bit signed integer", "::mlir::IntegerType">,
       BuildableType<
         "$_builder.getIntegerType(" # width # ", /*isSigned=*/true)"> {
   int bitwidth = width;
@@ -415,7 +426,7 @@ def AnyUnsignedInteger : Type<
 // Unsigned integer type of a specific width.
 class UI<int width>
     : Type<CPred<"$_self.isUnsignedInteger(" # width # ")">,
-                  width # "-bit unsigned integer">,
+                  width # "-bit unsigned integer", "::mlir::IntegerType">,
       BuildableType<
         "$_builder.getIntegerType(" # width # ", /*isSigned=*/false)"> {
   int bitwidth = width;
@@ -432,18 +443,20 @@ def UI32 : UI<32>;
 def UI64 : UI<64>;
 
 // Index type.
-def Index : Type<CPred<"$_self.isa<::mlir::IndexType>()">, "index">,
+def Index : Type<CPred<"$_self.isa<::mlir::IndexType>()">, "index",
+                 "::mlir::IndexType">,
             BuildableType<"$_builder.getIndexType()">;
 
 // Floating point types.
 
 // Any float type irrespective of its width.
-def AnyFloat : Type<CPred<"$_self.isa<::mlir::FloatType>()">, "floating-point">;
+def AnyFloat : Type<CPred<"$_self.isa<::mlir::FloatType>()">, "floating-point",
+                    "::mlir::FloatType">;
 
 // Float type of a specific width.
 class F<int width>
     : Type<CPred<"$_self.isF" # width # "()">,
-                width # "-bit float">,
+           width # "-bit float", "::mlir::FloatType">,
       BuildableType<"$_builder.getF" # width # "Type()"> {
   int bitwidth = width;
 }
@@ -465,16 +478,17 @@ class Complex<Type type>
           SubstLeaves<"$_self",
                       "$_self.cast<::mlir::ComplexType>().getElementType()",
            type.predicate>]>,
-           "complex type with " # type.description # " elements"> {
+           "complex type with " # type.description # " elements",
+           "::mlir::ComplexType"> {
   Type elementType = type;
 }
 
 def AnyComplex : Type<CPred<"$_self.isa<::mlir::ComplexType>()">,
-                            "complex-type">;
+                      "complex-type", "::mlir::ComplexType">;
 
 class OpaqueType<string dialect, string name, string description>
   : Type<CPred<"isOpaqueTypeWithName($_self, \""#dialect#"\", \""#name#"\")">,
-         description>,
+         description, "::mlir::OpaqueType">,
     BuildableType<"::mlir::OpaqueType::get($_builder.getContext(), "
                   "$_builder.getIdentifier(\"" # dialect # "\"), \""
                   # name # "\")">;
@@ -483,17 +497,17 @@ class OpaqueType<string dialect, string name, string description>
 
 // Any function type.
 def FunctionType : Type<CPred<"$_self.isa<::mlir::FunctionType>()">,
-                              "function type">;
+                              "function type", "::mlir::FunctionType">;
 
 // A container type is a type that has another type embedded within it.
 class ContainerType<Type etype, Pred containerPred, code elementTypeCall,
-                    string descr> :
+                    string descr, string cppClassName = "::mlir::Type"> :
     // First, check the container predicate.  Then, substitute the extracted
     // element into the element type checker.
     Type<And<[containerPred,
                 SubstLeaves<"$_self", !cast<string>(elementTypeCall),
                 etype.predicate>]>,
-         descr # " of " # etype.description # " values"> {
+         descr # " of " # etype.description # " values", cppClassName> {
   // The type of elements in the container.
   Type elementType = etype;
 
@@ -502,9 +516,11 @@ class ContainerType<Type etype, Pred containerPred, code elementTypeCall,
 }
 
 class ShapedContainerType<list<Type> allowedTypes,
-                          Pred containerPred, string descr> :
+                          Pred containerPred, string descr,
+                          string cppClassName = "::mlir::Type"> :
     ContainerType<AnyTypeOf<allowedTypes>, containerPred,
-                  "$_self.cast<::mlir::ShapedType>().getElementType()", descr>;
+                  "$_self.cast<::mlir::ShapedType>().getElementType()", descr,
+                  cppClassName>;
 
 // Whether a shaped type is ranked.
 def HasRankPred : CPred<"$_self.cast<::mlir::ShapedType>().hasRank()">;
@@ -520,7 +536,8 @@ class HasAnyRankOfPred<list<int> ranks> : And<[
 // Vector types.
 
 class VectorOf<list<Type> allowedTypes> :
-  ShapedContainerType<allowedTypes, IsVectorTypePred, "vector">;
+  ShapedContainerType<allowedTypes, IsVectorTypePred, "vector",
+                      "::mlir::VectorType">;
 
 // Whether the number of elements of a vector is from the given
 // `allowedRanks` list
@@ -534,7 +551,7 @@ class IsVectorOfRankPred<list<int> allowedRanks> :
 // Any vector where the rank is from the given `allowedRanks` list
 class VectorOfRank<list<int> allowedRanks> : Type<
   IsVectorOfRankPred<allowedRanks>,
-  " of ranks " # StrJoinInt<allowedRanks, "/">.result>;
+  " of ranks " # StrJoinInt<allowedRanks, "/">.result, "::mlir::VectorType">;
 
 // Any vector where the rank is from the given `allowedRanks` list and the type
 // is from the given `allowedTypes` list
@@ -543,7 +560,8 @@ class VectorOfRankAndType<list<int> allowedRanks,
   And<[VectorOf<allowedTypes>.predicate,
        VectorOfRank<allowedRanks>.predicate]>,
   VectorOf<allowedTypes>.description #
-  VectorOfRank<allowedRanks>.description>;
+  VectorOfRank<allowedRanks>.description,
+  "::mlir::VectorType">;
 
 // Whether the number of elements of a vector is from the given
 // `allowedLengths` list
@@ -558,7 +576,8 @@ class IsVectorOfLengthPred<list<int> allowedLengths> :
 // `allowedLengths` list
 class VectorOfLength<list<int> allowedLengths> : Type<
   IsVectorOfLengthPred<allowedLengths>,
-  " of length " # StrJoinInt<allowedLengths, "/">.result>;
+  " of length " # StrJoinInt<allowedLengths, "/">.result,
+  "::mlir::VectorType">;
 
 
 // Any vector where the number of elements is from the given
@@ -569,30 +588,34 @@ class VectorOfLengthAndType<list<int> allowedLengths,
   And<[VectorOf<allowedTypes>.predicate,
        VectorOfLength<allowedLengths>.predicate]>,
   VectorOf<allowedTypes>.description #
-  VectorOfLength<allowedLengths>.description>;
+  VectorOfLength<allowedLengths>.description,
+  "::mlir::VectorType">;
 
 def AnyVector : VectorOf<[AnyType]>;
 
 // Shaped types.
 
-def AnyShaped: ShapedContainerType<[AnyType], IsShapedTypePred, "shaped">;
+def AnyShaped: ShapedContainerType<[AnyType], IsShapedTypePred, "shaped",
+                                   "::mlir::ShapedType">;
 
 // Tensor types.
 
 // Any tensor type whose element type is from the given `allowedTypes` list
 class TensorOf<list<Type> allowedTypes> :
-  ShapedContainerType<allowedTypes, IsTensorTypePred, "tensor">;
+  ShapedContainerType<allowedTypes, IsTensorTypePred, "tensor",
+                      "::mlir::TensorType">;
 
 def AnyTensor : TensorOf<[AnyType]>;
 
 def AnyRankedTensor :
   ShapedContainerType<[AnyType], And<[IsTensorTypePred, HasRankPred]>,
-  "ranked tensor">;
+  "ranked tensor", "::mlir::TensorType">;
 
 // TODO: Have an easy way to add another constraint to a type.
 class StaticShapeTensorOf<list<Type> allowedTypes>
     : Type<And<[TensorOf<allowedTypes>.predicate, HasStaticShapePred]>,
-           "statically shaped " # TensorOf<allowedTypes>.description>;
+           "statically shaped " # TensorOf<allowedTypes>.description,
+           "::mlir::TensorType">;
 
 def AnyStaticShapeTensor : StaticShapeTensorOf<[AnyType]>;
 
@@ -612,7 +635,7 @@ def F64Tensor  : TensorOf<[F64]>;
 class TensorRankOf<list<Type> allowedTypes, list<int> ranks> :
     Type<And<[TensorOf<allowedTypes>.predicate, HasAnyRankOfPred<ranks>]>,
          StrJoin<!foreach(rank, ranks, rank # "D"), "/">.result # " " #
-         TensorOf<allowedTypes>.description>;
+         TensorOf<allowedTypes>.description, "::mlir::TensorType">;
 
 class 0DTensorOf<list<Type> allowedTypes> : TensorRankOf<allowedTypes, [0]>;
 class 1DTensorOf<list<Type> allowedTypes> : TensorRankOf<allowedTypes, [1]>;
@@ -623,12 +646,14 @@ class 4DTensorOf<list<Type> allowedTypes> : TensorRankOf<allowedTypes, [4]>;
 // Unranked Memref type
 def AnyUnrankedMemRef :
     ShapedContainerType<[AnyType],
-                        IsUnrankedMemRefTypePred, "unranked.memref">;
+                        IsUnrankedMemRefTypePred, "unranked.memref",
+                        "::mlir::MemRefType">;
 // Memref type.
 
 // Memrefs are blocks of data with fixed type and rank.
 class MemRefOf<list<Type> allowedTypes> :
-    ShapedContainerType<allowedTypes, IsMemRefTypePred, "memref">;
+    ShapedContainerType<allowedTypes, IsMemRefTypePred, "memref",
+                        "::mlir::MemRefType">;
 
 def AnyMemRef : MemRefOf<[AnyType]>;
 
@@ -673,8 +698,13 @@ class AnyStridedMemRefOfRank<int rank> :
             MemRefRankOf<[AnyType], [rank]>.predicate]>,
        AnyStridedMemRef.description # " of rank " # rank>;
 
+class StridedMemRefRankOf<list<Type> allowedTypes, list<int> ranks> :
+    Type<And<[MemRefOf<allowedTypes>.predicate, HasAnyRankOfPred<ranks>]>,
+         StrJoin<!foreach(rank, ranks, rank # "D"), "/">.result # " " #
+         MemRefOf<allowedTypes>.description>;
+
 // This represents a generic tuple without any constraints on element type.
-def AnyTuple : Type<IsTupleTypePred, "tuple">;
+def AnyTuple : Type<IsTupleTypePred, "tuple", "::mlir::TupleType">;
 
 // A container type that has other types embedded in it, but (unlike
 // ContainerType) can hold elements with a mix of types. Requires a call that
@@ -1934,15 +1964,6 @@ def region;
 // Marker used to identify the successor list for an op.
 def successor;
 
-// Base class for custom builders. This is a transient class that will go away
-// when the transition to the DAG form of builder declaration is complete.
-// Should not be used directly.
-class OpBuilderBase<dag dp, code b> {
-  string params = ?;
-  dag dagParams = dp;
-  code body = b;
-}
-
 // Class for defining a custom builder.
 //
 // TableGen generates several generic builders for each op by default (see
@@ -1981,11 +2002,9 @@ class OpBuilderBase<dag dp, code b> {
 // If an empty string is passed in for `body`, then *only* the builder
 // declaration will be generated; this provides a way to define complicated
 // builders entirely in C++.
-class OpBuilderDAG<dag p, code b = ""> : OpBuilderBase<p, b>;
-
-// Deprecated version of OpBuilder that takes the builder signature as string.
-class OpBuilder<string p, code b = ""> : OpBuilderBase<(ins), b> {
-  let params = p;
+class OpBuilderDAG<dag p, code b = ""> {
+  dag dagParams = p;
+  code body = b;
 }
 
 // A base decorator class that may optionally be added to OpVariables.
@@ -2063,7 +2082,7 @@ class Op<Dialect dialect, string mnemonic, list<OpTrait> props = []> {
   //                   ValueRange operands,
   //                   ArrayRef<NamedAttribute> attributes);
   // ```
-  list<OpBuilderBase> builders = ?;
+  list<OpBuilderDAG> builders = ?;
 
   // Avoid generating default build functions.  Custom builders must be
   // provided.
@@ -2420,9 +2439,7 @@ def replaceWithValue;
 // the given C++ base class.
 class TypeDef<Dialect dialect, string name,
               string baseCppClass = "::mlir::Type">
-    : DialectType<dialect, CPred<"">> {
-  // The name of the C++ Type class.
-  string cppClassName = name # "Type";
+    : DialectType<dialect, CPred<"">, /*descr*/"", name # "Type"> {
   // The name of the C++ base class to use for this Type.
   string cppBaseClassName = baseCppClass;
 
diff --git a/mlir/include/mlir/IR/OpDefinition.h b/mlir/include/mlir/IR/OpDefinition.h
index ddfee8e3a1c70..11dc4b77b677b 100644
--- a/mlir/include/mlir/IR/OpDefinition.h
+++ b/mlir/include/mlir/IR/OpDefinition.h
@@ -28,10 +28,6 @@ namespace mlir {
 class Builder;
 class OpBuilder;
 
-namespace OpTrait {
-template <typename ConcreteType> class OneResult;
-}
-
 /// This class represents success/failure for operation parsing. It is
 /// essentially a simple wrapper class around LogicalResult that allows for
 /// explicit conversion to bool. This allows for the parser to chain together
@@ -188,7 +184,8 @@ class OpState {
   void setAttrs(DictionaryAttr newAttrs) { state->setAttrs(newAttrs); }
 
   /// Set the dialect attributes for this operation, and preserve all dependent.
-  template <typename DialectAttrs> void setDialectAttrs(DialectAttrs &&attrs) {
+  template <typename DialectAttrs>
+  void setDialectAttrs(DialectAttrs &&attrs) {
     state->setDialectAttrs(std::forward<DialectAttrs>(attrs));
   }
 
@@ -424,7 +421,8 @@ class OneOperand : public TraitBase<ConcreteType, OneOperand> {
 ///
 ///   class FooOp : public Op<FooOp, OpTrait::NOperands<2>::Impl> {
 ///
-template <unsigned N> class NOperands {
+template <unsigned N>
+class NOperands {
 public:
   static_assert(N > 1, "use ZeroOperands/OneOperand for N < 2");
 
@@ -443,7 +441,8 @@ template <unsigned N> class NOperands {
 ///
 ///   class FooOp : public Op<FooOp, OpTrait::AtLeastNOperands<2>::Impl> {
 ///
-template <unsigned N> class AtLeastNOperands {
+template <unsigned N>
+class AtLeastNOperands {
 public:
   template <typename ConcreteType>
   class Impl : public detail::MultiOperandTraitBase<ConcreteType,
@@ -517,7 +516,8 @@ class OneRegion : public TraitBase<ConcreteType, OneRegion> {
 
 /// This class provides the API for ops that are known to have a specified
 /// number of regions.
-template <unsigned N> class NRegions {
+template <unsigned N>
+class NRegions {
 public:
   static_assert(N > 1, "use ZeroRegion/OneRegion for N < 2");
 
@@ -533,7 +533,8 @@ template <unsigned N> class NRegions {
 
 /// This class provides APIs for ops that are known to have at least a specified
 /// number of regions.
-template <unsigned N> class AtLeastNRegions {
+template <unsigned N>
+class AtLeastNRegions {
 public:
   template <typename ConcreteType>
   class Impl : public detail::MultiRegionTraitBase<ConcreteType,
@@ -582,7 +583,8 @@ struct MultiResultTraitBase : public TraitBase<ConcreteType, TraitType> {
 
   /// Replace all uses of results of this operation with the provided 'values'.
   /// 'values' may correspond to an existing operation, or a range of 'Value'.
-  template <typename ValuesT> void replaceAllUsesWith(ValuesT &&values) {
+  template <typename ValuesT>
+  void replaceAllUsesWith(ValuesT &&values) {
     this->getOperation()->replaceAllUsesWith(std::forward<ValuesT>(values));
   }
 
@@ -610,20 +612,19 @@ struct MultiResultTraitBase : public TraitBase<ConcreteType, TraitType> {
 } // end namespace detail
 
 /// This class provides return value APIs for ops that are known to have a
-/// single result.
+/// single result.  ResultType is the concrete type returned by getType().
 template <typename ConcreteType>
 class OneResult : public TraitBase<ConcreteType, OneResult> {
 public:
   Value getResult() { return this->getOperation()->getResult(0); }
-  Type getType() { return getResult().getType(); }
 
   /// If the operation returns a single value, then the Op can be implicitly
   /// converted to an Value. This yields the value of the only result.
   operator Value() { return getResult(); }
 
-  /// Replace all uses of 'this' value with the new value, updating anything in
-  /// the IR that uses 'this' to use the other value instead.  When this returns
-  /// there are zero uses of 'this'.
+  /// Replace all uses of 'this' value with the new value, updating anything
+  /// in the IR that uses 'this' to use the other value instead.  When this
+  /// returns there are zero uses of 'this'.
   void replaceAllUsesWith(Value newValue) {
     getResult().replaceAllUsesWith(newValue);
   }
@@ -638,12 +639,33 @@ class OneResult : public TraitBase<ConcreteType, OneResult> {
   }
 };
 
+/// This trait is used for return value APIs for ops that are known to have a
+/// specific type other than `Type`.  This allows the "getType()" member to be
+/// more specific for an op.  This should be used in conjunction with OneResult,
+/// and occur in the trait list before OneResult.
+template <typename ResultType>
+class OneTypedResult {
+public:
+  /// This class provides return value APIs for ops that are known to have a
+  /// single result.  ResultType is the concrete type returned by getType().
+  template <typename ConcreteType>
+  class Impl
+      : public TraitBase<ConcreteType, OneTypedResult<ResultType>::Impl> {
+  public:
+    ResultType getType() {
+      auto resultTy = this->getOperation()->getResult(0).getType();
+      return resultTy.template cast<ResultType>();
+    }
+  };
+};
+
 /// This class provides the API for ops that are known to have a specified
 /// number of results.  This is used as a trait like this:
 ///
 ///   class FooOp : public Op<FooOp, OpTrait::NResults<2>::Impl> {
 ///
-template <unsigned N> class NResults {
+template <unsigned N>
+class NResults {
 public:
   static_assert(N > 1, "use ZeroResult/OneResult for N < 2");
 
@@ -662,7 +684,8 @@ template <unsigned N> class NResults {
 ///
 ///   class FooOp : public Op<FooOp, OpTrait::AtLeastNResults<2>::Impl> {
 ///
-template <unsigned N> class AtLeastNResults {
+template <unsigned N>
+class AtLeastNResults {
 public:
   template <typename ConcreteType>
   class Impl : public detail::MultiResultTraitBase<ConcreteType,
@@ -1573,7 +1596,8 @@ class Op : public OpState, public Traits<ConcreteType>... {
   using has_fold = decltype(
       std::declval<T>().fold(std::declval<ArrayRef<Attribute>>(),
                              std::declval<SmallVectorImpl<OpFoldResult> &>()));
-  template <typename T> using detect_has_fold = llvm::is_detected<has_fold, T>;
+  template <typename T>
+  using detect_has_fold = llvm::is_detected<has_fold, T>;
   /// Trait to check if T provides a 'print' method.
   template <typename T, typename... Args>
   using has_print =
diff --git a/mlir/include/mlir/Interfaces/VectorInterfaces.td b/mlir/include/mlir/Interfaces/VectorInterfaces.td
index 73332afd8825e..3f60de5831c9f 100644
--- a/mlir/include/mlir/Interfaces/VectorInterfaces.td
+++ b/mlir/include/mlir/Interfaces/VectorInterfaces.td
@@ -47,7 +47,7 @@ def VectorUnrollOpInterface : OpInterface<"VectorUnrollOpInterface"> {
 
 def VectorTransferOpInterface : OpInterface<"VectorTransferOpInterface"> {
   let description = [{
-    Encodes properties of an operation on vectors that can be unrolled.
+    Encodes properties of a transfer read or write operation.
   }];
   let cppNamespace = "::mlir";
 
@@ -83,11 +83,11 @@ def VectorTransferOpInterface : OpInterface<"VectorTransferOpInterface"> {
       }]
     >,
     InterfaceMethod<
-      /*desc=*/"Return the memref operand.",
+      /*desc=*/"Return the memref or ranked tensor operand.",
       /*retTy=*/"Value",
-      /*methodName=*/"memref",
+      /*methodName=*/"source",
       /*args=*/(ins),
-      /*methodBody=*/"return $_op.memref();"
+      /*methodBody=*/"return $_op.source();"
       /*defaultImplementation=*/
     >,
     InterfaceMethod<
@@ -123,13 +123,13 @@ def VectorTransferOpInterface : OpInterface<"VectorTransferOpInterface"> {
       /*defaultImplementation=*/
     >,
     InterfaceMethod<
-      /*desc=*/"Return the MemRefType.",
-      /*retTy=*/"MemRefType",
-      /*methodName=*/"getMemRefType",
+      /*desc=*/"Return the ShapedType.",
+      /*retTy=*/"ShapedType",
+      /*methodName=*/"getShapedType",
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/
-        "return $_op.memref().getType().template cast<MemRefType>();"
+        "return $_op.source().getType().template cast<ShapedType>();"
     >,
     InterfaceMethod<
       /*desc=*/"Return the VectorType.",
@@ -152,14 +152,14 @@ def VectorTransferOpInterface : OpInterface<"VectorTransferOpInterface"> {
         "return $_op.permutation_map().getNumResults();"
     >,
     InterfaceMethod<
-      /*desc=*/[{ Return the number of leading memref dimensions that do not
+      /*desc=*/[{ Return the number of leading shaped dimensions that do not
                   participate in the permutation map.}],
       /*retTy=*/"unsigned",
-      /*methodName=*/"getLeadingMemRefRank",
+      /*methodName=*/"getLeadingShapedRank",
       /*args=*/(ins),
       /*methodBody=*/"",
       /*defaultImplementation=*/
-        "return $_op.getMemRefType().getRank() - $_op.getTransferRank();"
+        "return $_op.getShapedType().getRank() - $_op.getTransferRank();"
     >,
     InterfaceMethod<
       /*desc=*/[{ Returns true if at least one of the dimensions is masked.}],
@@ -178,8 +178,8 @@ def VectorTransferOpInterface : OpInterface<"VectorTransferOpInterface"> {
       /*desc=*/[{
       Helper function to account for the fact that `permutationMap` results and
       `op.indices` sizes may not match and may not be aligned. The first
-      `getLeadingMemRefRank()` indices may just be indexed and not transferred
-      from/into the vector.
+      `getLeadingShapedRank()` indices may just be indexed and not
+      transferred from/into the vector.
       For example:
       ```
          vector.transfer %0[%i, %j, %k, %c0] :
@@ -195,7 +195,7 @@ def VectorTransferOpInterface : OpInterface<"VectorTransferOpInterface"> {
       /*methodBody=*/"",
       /*defaultImplementation=*/[{
         for (int64_t resultIdx = 0,
-                   indicesIdx = $_op.getLeadingMemRefRank(),
+                   indicesIdx = $_op.getLeadingShapedRank(),
                    eResult = $_op.getTransferRank();
            resultIdx < eResult;
            ++resultIdx, ++indicesIdx)
diff --git a/mlir/include/mlir/TableGen/Type.h b/mlir/include/mlir/TableGen/Type.h
index 2653b90196f78..37024f51bdc92 100644
--- a/mlir/include/mlir/TableGen/Type.h
+++ b/mlir/include/mlir/TableGen/Type.h
@@ -47,6 +47,9 @@ class TypeConstraint : public Constraint {
   // Returns the builder call for this constraint if this is a buildable type,
   // returns None otherwise.
   Optional<StringRef> getBuilderCall() const;
+
+  // Return the C++ class name for this type (which may just be ::mlir::Type).
+  StringRef getCPPClassName() const;
 };
 
 // Wrapper class with helper methods for accessing Types defined in TableGen.
diff --git a/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h b/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
index d3d289414b382..5259ed7fe182c 100644
--- a/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
+++ b/mlir/include/mlir/Target/LLVMIR/ModuleTranslation.h
@@ -100,6 +100,9 @@ class ModuleTranslation {
                            llvm::BasicBlock &continuationIP,
                            llvm::IRBuilder<> &builder,
                            LogicalResult &bodyGenStatus);
+  virtual LogicalResult convertOmpWsLoop(Operation &opInst,
+                                         llvm::IRBuilder<> &builder);
+
   /// Converts the type from MLIR LLVM dialect to LLVM.
   llvm::Type *convertType(LLVMType type);
 
diff --git a/mlir/integration_test/Dialect/Linalg/CPU/test-tensor-matmul.mlir b/mlir/integration_test/Dialect/Linalg/CPU/test-tensor-matmul.mlir
index 38d97332f0d70..9e4b9f39f7fbf 100644
--- a/mlir/integration_test/Dialect/Linalg/CPU/test-tensor-matmul.mlir
+++ b/mlir/integration_test/Dialect/Linalg/CPU/test-tensor-matmul.mlir
@@ -22,7 +22,7 @@ func @main() {
   %C = constant dense<1000.0> : tensor<2x4xf32>
 
   %D = linalg.matmul ins(%A, %B: tensor<2x3xf32>, tensor<3x4xf32>)
-                     init(%C: tensor<2x4xf32>) -> tensor<2x4xf32>
+                     outs(%C: tensor<2x4xf32>) -> tensor<2x4xf32>
 
   %unranked = tensor.cast %D : tensor<2x4xf32> to tensor<*xf32>
   call @print_memref_f32(%unranked) : (tensor<*xf32>) -> ()
diff --git a/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp b/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
index 58f44b6ed2078..8721e6b96ed7d 100644
--- a/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
+++ b/mlir/lib/Conversion/AffineToStandard/AffineToStandard.cpp
@@ -334,7 +334,13 @@ class AffineYieldOpLowering : public OpRewritePattern<AffineYieldOp> {
 
   LogicalResult matchAndRewrite(AffineYieldOp op,
                                 PatternRewriter &rewriter) const override {
-    rewriter.replaceOpWithNewOp<scf::YieldOp>(op);
+    if (isa<scf::ParallelOp>(op.getParentOp())) {
+      // scf.parallel does not yield any values via its terminator scf.yield but
+      // models reductions differently using additional ops in its region.
+      rewriter.replaceOpWithNewOp<scf::YieldOp>(op);
+      return success();
+    }
+    rewriter.replaceOpWithNewOp<scf::YieldOp>(op, op.operands());
     return success();
   }
 };
@@ -349,14 +355,55 @@ class AffineForLowering : public OpRewritePattern<AffineForOp> {
     Value lowerBound = lowerAffineLowerBound(op, rewriter);
     Value upperBound = lowerAffineUpperBound(op, rewriter);
     Value step = rewriter.create<ConstantIndexOp>(loc, op.getStep());
-    auto f = rewriter.create<scf::ForOp>(loc, lowerBound, upperBound, step);
-    rewriter.eraseBlock(f.getBody());
-    rewriter.inlineRegionBefore(op.region(), f.region(), f.region().end());
-    rewriter.eraseOp(op);
+    auto scfForOp = rewriter.create<scf::ForOp>(loc, lowerBound, upperBound,
+                                                step, op.getIterOperands());
+    rewriter.eraseBlock(scfForOp.getBody());
+    rewriter.inlineRegionBefore(op.region(), scfForOp.region(),
+                                scfForOp.region().end());
+    rewriter.replaceOp(op, scfForOp.results());
     return success();
   }
 };
 
+/// Returns the identity value associated with an AtomicRMWKind op.
+static Value getIdentityValue(AtomicRMWKind op, OpBuilder &builder,
+                              Location loc) {
+  switch (op) {
+  case AtomicRMWKind::addf:
+    return builder.create<ConstantOp>(loc, builder.getF32FloatAttr(0));
+  case AtomicRMWKind::addi:
+    return builder.create<ConstantOp>(loc, builder.getI32IntegerAttr(0));
+  case AtomicRMWKind::mulf:
+    return builder.create<ConstantOp>(loc, builder.getF32FloatAttr(1));
+  case AtomicRMWKind::muli:
+    return builder.create<ConstantOp>(loc, builder.getI32IntegerAttr(1));
+  // TODO: Add remaining reduction operations.
+  default:
+    emitOptionalError(loc, "Reduction operation type not supported");
+  }
+  return nullptr;
+}
+
+/// Return the value obtained by applying the reduction operation kind
+/// associated with a binary AtomicRMWKind op to `lhs` and `rhs`.
+static Value getReductionOp(AtomicRMWKind op, OpBuilder &builder, Location loc,
+                            Value lhs, Value rhs) {
+  switch (op) {
+  case AtomicRMWKind::addf:
+    return builder.create<AddFOp>(loc, lhs, rhs);
+  case AtomicRMWKind::addi:
+    return builder.create<AddIOp>(loc, lhs, rhs);
+  case AtomicRMWKind::mulf:
+    return builder.create<MulFOp>(loc, lhs, rhs);
+  case AtomicRMWKind::muli:
+    return builder.create<MulIOp>(loc, lhs, rhs);
+  // TODO: Add remaining reduction operations.
+  default:
+    emitOptionalError(loc, "Reduction operation type not supported");
+  }
+  return nullptr;
+}
+
 /// Convert an `affine.parallel` (loop nest) operation into a `scf.parallel`
 /// operation.
 class AffineParallelLowering : public OpRewritePattern<AffineParallelOp> {
@@ -369,12 +416,13 @@ class AffineParallelLowering : public OpRewritePattern<AffineParallelOp> {
     SmallVector<Value, 8> steps;
     SmallVector<Value, 8> upperBoundTuple;
     SmallVector<Value, 8> lowerBoundTuple;
+    SmallVector<Value, 8> identityVals;
     // Finding lower and upper bound by expanding the map expression.
     // Checking if expandAffineMap is not giving NULL.
-    Optional<SmallVector<Value, 8>> upperBound = expandAffineMap(
-        rewriter, loc, op.upperBoundsMap(), op.getUpperBoundsOperands());
     Optional<SmallVector<Value, 8>> lowerBound = expandAffineMap(
         rewriter, loc, op.lowerBoundsMap(), op.getLowerBoundsOperands());
+    Optional<SmallVector<Value, 8>> upperBound = expandAffineMap(
+        rewriter, loc, op.upperBoundsMap(), op.getUpperBoundsOperands());
     if (!lowerBound || !upperBound)
       return failure();
     upperBoundTuple = *upperBound;
@@ -383,13 +431,62 @@ class AffineParallelLowering : public OpRewritePattern<AffineParallelOp> {
     for (Attribute step : op.steps())
       steps.push_back(rewriter.create<ConstantIndexOp>(
           loc, step.cast<IntegerAttr>().getInt()));
-    // Creating empty scf.parallel op body with appropriate bounds.
-    auto parallelOp = rewriter.create<scf::ParallelOp>(loc, lowerBoundTuple,
-                                                       upperBoundTuple, steps);
-    rewriter.eraseBlock(parallelOp.getBody());
-    rewriter.inlineRegionBefore(op.region(), parallelOp.region(),
-                                parallelOp.region().end());
-    rewriter.eraseOp(op);
+    // Get the terminator op.
+    Operation *affineParOpTerminator = op.getBody()->getTerminator();
+    scf::ParallelOp parOp;
+    if (op.results().empty()) {
+      // Case with no reduction operations/return values.
+      parOp = rewriter.create<scf::ParallelOp>(loc, lowerBoundTuple,
+                                               upperBoundTuple, steps,
+                                               /*bodyBuilderFn=*/nullptr);
+      rewriter.eraseBlock(parOp.getBody());
+      rewriter.inlineRegionBefore(op.region(), parOp.region(),
+                                  parOp.region().end());
+      rewriter.replaceOp(op, parOp.results());
+      return success();
+    }
+    // Case with affine.parallel with reduction operations/return values.
+    // scf.parallel handles the reduction operation differently unlike
+    // affine.parallel.
+    ArrayRef<Attribute> reductions = op.reductions().getValue();
+    for (Attribute reduction : reductions) {
+      // For each of the reduction operations get the identity values for
+      // initialization of the result values.
+      Optional<AtomicRMWKind> reductionOp = symbolizeAtomicRMWKind(
+          static_cast<uint64_t>(reduction.cast<IntegerAttr>().getInt()));
+      assert(reductionOp.hasValue() &&
+             "Reduction operation cannot be of None Type");
+      AtomicRMWKind reductionOpValue = reductionOp.getValue();
+      identityVals.push_back(getIdentityValue(reductionOpValue, rewriter, loc));
+    }
+    parOp = rewriter.create<scf::ParallelOp>(
+        loc, lowerBoundTuple, upperBoundTuple, steps, identityVals,
+        /*bodyBuilderFn=*/nullptr);
+
+    //  Copy the body of the affine.parallel op.
+    rewriter.eraseBlock(parOp.getBody());
+    rewriter.inlineRegionBefore(op.region(), parOp.region(),
+                                parOp.region().end());
+    assert(reductions.size() == affineParOpTerminator->getNumOperands() &&
+           "Unequal number of reductions and operands.");
+    for (unsigned i = 0, end = reductions.size(); i < end; i++) {
+      // For each of the reduction operations get the respective mlir::Value.
+      Optional<AtomicRMWKind> reductionOp =
+          symbolizeAtomicRMWKind(reductions[i].cast<IntegerAttr>().getInt());
+      assert(reductionOp.hasValue() &&
+             "Reduction Operation cannot be of None Type");
+      AtomicRMWKind reductionOpValue = reductionOp.getValue();
+      rewriter.setInsertionPoint(&parOp.getBody()->back());
+      auto reduceOp = rewriter.create<scf::ReduceOp>(
+          loc, affineParOpTerminator->getOperand(i));
+      rewriter.setInsertionPointToEnd(&reduceOp.reductionOperator().front());
+      Value reductionResult =
+          getReductionOp(reductionOpValue, rewriter, loc,
+                         reduceOp.reductionOperator().front().getArgument(0),
+                         reduceOp.reductionOperator().front().getArgument(1));
+      rewriter.create<scf::ReduceReturnOp>(loc, reductionResult);
+    }
+    rewriter.replaceOp(op, parOp.results());
     return success();
   }
 };
diff --git a/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp b/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
index 273754fe2480c..517c8d2c6f569 100644
--- a/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
+++ b/mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp
@@ -9,11 +9,13 @@
 #include "mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h"
 
 #include "../PassDetail.h"
+#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
 #include "mlir/Dialect/Async/IR/Async.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
+#include "mlir/Dialect/StandardOps/Transforms/FuncConversions.h"
 #include "mlir/IR/BlockAndValueMapping.h"
-#include "mlir/IR/Builders.h"
+#include "mlir/IR/ImplicitLocOpBuilder.h"
 #include "mlir/IR/TypeUtilities.h"
 #include "mlir/Pass/Pass.h"
 #include "mlir/Transforms/DialectConversion.h"
@@ -36,23 +38,39 @@ static constexpr const char kAsyncFnPrefix[] = "async_execute_fn";
 static constexpr const char *kAddRef = "mlirAsyncRuntimeAddRef";
 static constexpr const char *kDropRef = "mlirAsyncRuntimeDropRef";
 static constexpr const char *kCreateToken = "mlirAsyncRuntimeCreateToken";
+static constexpr const char *kCreateValue = "mlirAsyncRuntimeCreateValue";
 static constexpr const char *kCreateGroup = "mlirAsyncRuntimeCreateGroup";
 static constexpr const char *kEmplaceToken = "mlirAsyncRuntimeEmplaceToken";
+static constexpr const char *kEmplaceValue = "mlirAsyncRuntimeEmplaceValue";
 static constexpr const char *kAwaitToken = "mlirAsyncRuntimeAwaitToken";
+static constexpr const char *kAwaitValue = "mlirAsyncRuntimeAwaitValue";
 static constexpr const char *kAwaitGroup = "mlirAsyncRuntimeAwaitAllInGroup";
 static constexpr const char *kExecute = "mlirAsyncRuntimeExecute";
+static constexpr const char *kGetValueStorage =
+    "mlirAsyncRuntimeGetValueStorage";
 static constexpr const char *kAddTokenToGroup =
     "mlirAsyncRuntimeAddTokenToGroup";
-static constexpr const char *kAwaitAndExecute =
+static constexpr const char *kAwaitTokenAndExecute =
     "mlirAsyncRuntimeAwaitTokenAndExecute";
+static constexpr const char *kAwaitValueAndExecute =
+    "mlirAsyncRuntimeAwaitValueAndExecute";
 static constexpr const char *kAwaitAllAndExecute =
     "mlirAsyncRuntimeAwaitAllInGroupAndExecute";
 
 namespace {
-// Async Runtime API function types.
+/// Async Runtime API function types.
+///
+/// Because we can't create API function signature for type parametrized
+/// async.value type, we use opaque pointers (!llvm.ptr<i8>) instead. After
+/// lowering all async data types become opaque pointers at runtime.
 struct AsyncAPI {
+  // All async types are lowered to opaque i8* LLVM pointers at runtime.
+  static LLVM::LLVMPointerType opaquePointerType(MLIRContext *ctx) {
+    return LLVM::LLVMPointerType::get(LLVM::LLVMIntegerType::get(ctx, 8));
+  }
+
   static FunctionType addOrDropRefFunctionType(MLIRContext *ctx) {
-    auto ref = LLVM::LLVMType::getInt8PtrTy(ctx);
+    auto ref = opaquePointerType(ctx);
     auto count = IntegerType::get(ctx, 32);
     return FunctionType::get(ctx, {ref, count}, {});
   }
@@ -61,25 +79,47 @@ struct AsyncAPI {
     return FunctionType::get(ctx, {}, {TokenType::get(ctx)});
   }
 
+  static FunctionType createValueFunctionType(MLIRContext *ctx) {
+    auto i32 = IntegerType::get(ctx, 32);
+    auto value = opaquePointerType(ctx);
+    return FunctionType::get(ctx, {i32}, {value});
+  }
+
   static FunctionType createGroupFunctionType(MLIRContext *ctx) {
     return FunctionType::get(ctx, {}, {GroupType::get(ctx)});
   }
 
+  static FunctionType getValueStorageFunctionType(MLIRContext *ctx) {
+    auto value = opaquePointerType(ctx);
+    auto storage = opaquePointerType(ctx);
+    return FunctionType::get(ctx, {value}, {storage});
+  }
+
   static FunctionType emplaceTokenFunctionType(MLIRContext *ctx) {
     return FunctionType::get(ctx, {TokenType::get(ctx)}, {});
   }
 
+  static FunctionType emplaceValueFunctionType(MLIRContext *ctx) {
+    auto value = opaquePointerType(ctx);
+    return FunctionType::get(ctx, {value}, {});
+  }
+
   static FunctionType awaitTokenFunctionType(MLIRContext *ctx) {
     return FunctionType::get(ctx, {TokenType::get(ctx)}, {});
   }
 
+  static FunctionType awaitValueFunctionType(MLIRContext *ctx) {
+    auto value = opaquePointerType(ctx);
+    return FunctionType::get(ctx, {value}, {});
+  }
+
   static FunctionType awaitGroupFunctionType(MLIRContext *ctx) {
     return FunctionType::get(ctx, {GroupType::get(ctx)}, {});
   }
 
   static FunctionType executeFunctionType(MLIRContext *ctx) {
-    auto hdl = LLVM::LLVMType::getInt8PtrTy(ctx);
-    auto resume = resumeFunctionType(ctx).getPointerTo();
+    auto hdl = opaquePointerType(ctx);
+    auto resume = LLVM::LLVMPointerType::get(resumeFunctionType(ctx));
     return FunctionType::get(ctx, {hdl, resume}, {});
   }
 
@@ -89,48 +129,63 @@ struct AsyncAPI {
                              {i64});
   }
 
-  static FunctionType awaitAndExecuteFunctionType(MLIRContext *ctx) {
-    auto hdl = LLVM::LLVMType::getInt8PtrTy(ctx);
-    auto resume = resumeFunctionType(ctx).getPointerTo();
+  static FunctionType awaitTokenAndExecuteFunctionType(MLIRContext *ctx) {
+    auto hdl = opaquePointerType(ctx);
+    auto resume = LLVM::LLVMPointerType::get(resumeFunctionType(ctx));
     return FunctionType::get(ctx, {TokenType::get(ctx), hdl, resume}, {});
   }
 
+  static FunctionType awaitValueAndExecuteFunctionType(MLIRContext *ctx) {
+    auto value = opaquePointerType(ctx);
+    auto hdl = opaquePointerType(ctx);
+    auto resume = LLVM::LLVMPointerType::get(resumeFunctionType(ctx));
+    return FunctionType::get(ctx, {value, hdl, resume}, {});
+  }
+
   static FunctionType awaitAllAndExecuteFunctionType(MLIRContext *ctx) {
-    auto hdl = LLVM::LLVMType::getInt8PtrTy(ctx);
-    auto resume = resumeFunctionType(ctx).getPointerTo();
+    auto hdl = opaquePointerType(ctx);
+    auto resume = LLVM::LLVMPointerType::get(resumeFunctionType(ctx));
     return FunctionType::get(ctx, {GroupType::get(ctx), hdl, resume}, {});
   }
 
   // Auxiliary coroutine resume intrinsic wrapper.
   static LLVM::LLVMType resumeFunctionType(MLIRContext *ctx) {
-    auto voidTy = LLVM::LLVMType::getVoidTy(ctx);
-    auto i8Ptr = LLVM::LLVMType::getInt8PtrTy(ctx);
-    return LLVM::LLVMType::getFunctionTy(voidTy, {i8Ptr}, false);
+    auto voidTy = LLVM::LLVMVoidType::get(ctx);
+    auto i8Ptr = opaquePointerType(ctx);
+    return LLVM::LLVMFunctionType::get(voidTy, {i8Ptr}, false);
   }
 };
 } // namespace
 
-// Adds Async Runtime C API declarations to the module.
+/// Adds Async Runtime C API declarations to the module.
 static void addAsyncRuntimeApiDeclarations(ModuleOp module) {
-  auto builder = OpBuilder::atBlockTerminator(module.getBody());
+  auto builder = ImplicitLocOpBuilder::atBlockTerminator(module.getLoc(),
+                                                         module.getBody());
 
   auto addFuncDecl = [&](StringRef name, FunctionType type) {
     if (module.lookupSymbol(name))
       return;
-    builder.create<FuncOp>(module.getLoc(), name, type).setPrivate();
+    builder.create<FuncOp>(name, type).setPrivate();
   };
 
   MLIRContext *ctx = module.getContext();
   addFuncDecl(kAddRef, AsyncAPI::addOrDropRefFunctionType(ctx));
   addFuncDecl(kDropRef, AsyncAPI::addOrDropRefFunctionType(ctx));
   addFuncDecl(kCreateToken, AsyncAPI::createTokenFunctionType(ctx));
+  addFuncDecl(kCreateValue, AsyncAPI::createValueFunctionType(ctx));
   addFuncDecl(kCreateGroup, AsyncAPI::createGroupFunctionType(ctx));
   addFuncDecl(kEmplaceToken, AsyncAPI::emplaceTokenFunctionType(ctx));
+  addFuncDecl(kEmplaceValue, AsyncAPI::emplaceValueFunctionType(ctx));
   addFuncDecl(kAwaitToken, AsyncAPI::awaitTokenFunctionType(ctx));
+  addFuncDecl(kAwaitValue, AsyncAPI::awaitValueFunctionType(ctx));
   addFuncDecl(kAwaitGroup, AsyncAPI::awaitGroupFunctionType(ctx));
   addFuncDecl(kExecute, AsyncAPI::executeFunctionType(ctx));
+  addFuncDecl(kGetValueStorage, AsyncAPI::getValueStorageFunctionType(ctx));
   addFuncDecl(kAddTokenToGroup, AsyncAPI::addTokenToGroupFunctionType(ctx));
-  addFuncDecl(kAwaitAndExecute, AsyncAPI::awaitAndExecuteFunctionType(ctx));
+  addFuncDecl(kAwaitTokenAndExecute,
+              AsyncAPI::awaitTokenAndExecuteFunctionType(ctx));
+  addFuncDecl(kAwaitValueAndExecute,
+              AsyncAPI::awaitValueAndExecuteFunctionType(ctx));
   addFuncDecl(kAwaitAllAndExecute,
               AsyncAPI::awaitAllAndExecuteFunctionType(ctx));
 }
@@ -149,13 +204,13 @@ static constexpr const char *kCoroFree = "llvm.coro.free";
 static constexpr const char *kCoroResume = "llvm.coro.resume";
 
 /// Adds an LLVM function declaration to a module.
-static void addLLVMFuncDecl(ModuleOp module, OpBuilder &builder, StringRef name,
-                            LLVM::LLVMType ret,
+static void addLLVMFuncDecl(ModuleOp module, ImplicitLocOpBuilder &builder,
+                            StringRef name, LLVM::LLVMType ret,
                             ArrayRef<LLVM::LLVMType> params) {
   if (module.lookupSymbol(name))
     return;
-  LLVM::LLVMType type = LLVM::LLVMType::getFunctionTy(ret, params, false);
-  builder.create<LLVM::LLVMFuncOp>(module.getLoc(), name, type);
+  LLVM::LLVMType type = LLVM::LLVMFunctionType::get(ret, params);
+  builder.create<LLVM::LLVMFuncOp>(name, type);
 }
 
 /// Adds coroutine intrinsics declarations to the module.
@@ -163,16 +218,17 @@ static void addCoroutineIntrinsicsDeclarations(ModuleOp module) {
   using namespace mlir::LLVM;
 
   MLIRContext *ctx = module.getContext();
-  OpBuilder builder(module.getBody()->getTerminator());
+  ImplicitLocOpBuilder builder(module.getLoc(),
+                               module.getBody()->getTerminator());
 
   auto token = LLVMTokenType::get(ctx);
-  auto voidTy = LLVMType::getVoidTy(ctx);
+  auto voidTy = LLVMVoidType::get(ctx);
 
-  auto i8 = LLVMType::getInt8Ty(ctx);
-  auto i1 = LLVMType::getInt1Ty(ctx);
-  auto i32 = LLVMType::getInt32Ty(ctx);
-  auto i64 = LLVMType::getInt64Ty(ctx);
-  auto i8Ptr = LLVMType::getInt8PtrTy(ctx);
+  auto i8 = LLVMIntegerType::get(ctx, 8);
+  auto i1 = LLVMIntegerType::get(ctx, 1);
+  auto i32 = LLVMIntegerType::get(ctx, 32);
+  auto i64 = LLVMIntegerType::get(ctx, 64);
+  auto i8Ptr = LLVMPointerType::get(i8);
 
   addLLVMFuncDecl(module, builder, kCoroId, token, {i32, i8Ptr, i8Ptr, i8Ptr});
   addLLVMFuncDecl(module, builder, kCoroSizeI64, i64, {});
@@ -196,11 +252,12 @@ static void addCRuntimeDeclarations(ModuleOp module) {
   using namespace mlir::LLVM;
 
   MLIRContext *ctx = module.getContext();
-  OpBuilder builder(module.getBody()->getTerminator());
+  ImplicitLocOpBuilder builder(module.getLoc(),
+                               module.getBody()->getTerminator());
 
-  auto voidTy = LLVMType::getVoidTy(ctx);
-  auto i64 = LLVMType::getInt64Ty(ctx);
-  auto i8Ptr = LLVMType::getInt8PtrTy(ctx);
+  auto voidTy = LLVMVoidType::get(ctx);
+  auto i64 = LLVMIntegerType::get(ctx, 64);
+  auto i8Ptr = LLVMPointerType::get(LLVMIntegerType::get(ctx, 8));
 
   addLLVMFuncDecl(module, builder, kMalloc, i8Ptr, {i64});
   addLLVMFuncDecl(module, builder, kFree, voidTy, {i8Ptr});
@@ -212,9 +269,9 @@ static void addCRuntimeDeclarations(ModuleOp module) {
 
 static constexpr const char *kResume = "__resume";
 
-// A function that takes a coroutine handle and calls a `llvm.coro.resume`
-// intrinsics. We need this function to be able to pass it to the async
-// runtime execute API.
+/// A function that takes a coroutine handle and calls a `llvm.coro.resume`
+/// intrinsics. We need this function to be able to pass it to the async
+/// runtime execute API.
 static void addResumeFunction(ModuleOp module) {
   MLIRContext *ctx = module.getContext();
 
@@ -224,91 +281,140 @@ static void addResumeFunction(ModuleOp module) {
   if (module.lookupSymbol(kResume))
     return;
 
-  auto voidTy = LLVM::LLVMType::getVoidTy(ctx);
-  auto i8Ptr = LLVM::LLVMType::getInt8PtrTy(ctx);
+  auto voidTy = LLVM::LLVMVoidType::get(ctx);
+  auto i8Ptr = LLVM::LLVMPointerType::get(LLVM::LLVMIntegerType::get(ctx, 8));
 
   auto resumeOp = moduleBuilder.create<LLVM::LLVMFuncOp>(
-      loc, kResume, LLVM::LLVMType::getFunctionTy(voidTy, {i8Ptr}, false));
+      loc, kResume, LLVM::LLVMFunctionType::get(voidTy, {i8Ptr}));
   resumeOp.setPrivate();
 
   auto *block = resumeOp.addEntryBlock();
-  OpBuilder blockBuilder = OpBuilder::atBlockEnd(block);
+  auto blockBuilder = ImplicitLocOpBuilder::atBlockEnd(loc, block);
 
-  blockBuilder.create<LLVM::CallOp>(loc, TypeRange(),
+  blockBuilder.create<LLVM::CallOp>(TypeRange(),
                                     blockBuilder.getSymbolRefAttr(kCoroResume),
                                     resumeOp.getArgument(0));
 
-  blockBuilder.create<LLVM::ReturnOp>(loc, ValueRange());
+  blockBuilder.create<LLVM::ReturnOp>(ValueRange());
 }
 
 //===----------------------------------------------------------------------===//
 // async.execute op outlining to the coroutine functions.
 //===----------------------------------------------------------------------===//
 
-// Function targeted for coroutine transformation has two additional blocks at
-// the end: coroutine cleanup and coroutine suspension.
-//
-// async.await op lowering additionaly creates a resume block for each
-// operation to enable non-blocking waiting via coroutine suspension.
+/// Function targeted for coroutine transformation has two additional blocks at
+/// the end: coroutine cleanup and coroutine suspension.
+///
+/// async.await op lowering additionaly creates a resume block for each
+/// operation to enable non-blocking waiting via coroutine suspension.
 namespace {
 struct CoroMachinery {
-  Value asyncToken;
+  // Async execute region returns a completion token, and an async value for
+  // each yielded value.
+  //
+  //   %token, %result = async.execute -> !async.value<T> {
+  //     %0 = constant ... : T
+  //     async.yield %0 : T
+  //   }
+  Value asyncToken; // token representing completion of the async region
+  llvm::SmallVector<Value, 4> returnValues; // returned async values
+
   Value coroHandle;
   Block *cleanup;
   Block *suspend;
 };
 } // namespace
 
-// Builds an coroutine template compatible with LLVM coroutines lowering.
-//
-//  - `entry` block sets up the coroutine.
-//  - `cleanup` block cleans up the coroutine state.
-//  - `suspend block after the @llvm.coro.end() defines what value will be
-//    returned to the initial caller of a coroutine. Everything before the
-//    @llvm.coro.end() will be executed at every suspension point.
-//
-// Coroutine structure (only the important bits):
-//
-//   func @async_execute_fn(<function-arguments>) -> !async.token {
-//     ^entryBlock(<function-arguments>):
-//       %token = <async token> : !async.token // create async runtime token
-//       %hdl = llvm.call @llvm.coro.id(...)   // create a coroutine handle
-//       br ^cleanup
-//
-//     ^cleanup:
-//       llvm.call @llvm.coro.free(...)        // delete coroutine state
-//       br ^suspend
-//
-//     ^suspend:
-//       llvm.call @llvm.coro.end(...)         // marks the end of a coroutine
-//       return %token : !async.token
-//   }
-//
-// The actual code for the async.execute operation body region will be inserted
-// before the entry block terminator.
-//
-//
+/// Builds an coroutine template compatible with LLVM coroutines lowering.
+///
+///  - `entry` block sets up the coroutine.
+///  - `cleanup` block cleans up the coroutine state.
+///  - `suspend block after the @llvm.coro.end() defines what value will be
+///    returned to the initial caller of a coroutine. Everything before the
+///    @llvm.coro.end() will be executed at every suspension point.
+///
+/// Coroutine structure (only the important bits):
+///
+///   func @async_execute_fn(<function-arguments>)
+///        -> (!async.token, !async.value<T>)
+///   {
+///     ^entryBlock(<function-arguments>):
+///       %token = <async token> : !async.token    // create async runtime token
+///       %value = <async value> : !async.value<T> // create async value
+///       %hdl = llvm.call @llvm.coro.id(...)      // create a coroutine handle
+///       br ^cleanup
+///
+///     ^cleanup:
+///       llvm.call @llvm.coro.free(...)  // delete coroutine state
+///       br ^suspend
+///
+///     ^suspend:
+///       llvm.call @llvm.coro.end(...)  // marks the end of a coroutine
+///       return %token, %value : !async.token, !async.value<T>
+///   }
+///
+/// The actual code for the async.execute operation body region will be inserted
+/// before the entry block terminator.
+///
+///
 static CoroMachinery setupCoroMachinery(FuncOp func) {
   assert(func.getBody().empty() && "Function must have empty body");
 
   MLIRContext *ctx = func.getContext();
 
   auto token = LLVM::LLVMTokenType::get(ctx);
-  auto i1 = LLVM::LLVMType::getInt1Ty(ctx);
-  auto i32 = LLVM::LLVMType::getInt32Ty(ctx);
-  auto i64 = LLVM::LLVMType::getInt64Ty(ctx);
-  auto i8Ptr = LLVM::LLVMType::getInt8PtrTy(ctx);
+  auto i1 = LLVM::LLVMIntegerType::get(ctx, 1);
+  auto i32 = LLVM::LLVMIntegerType::get(ctx, 32);
+  auto i64 = LLVM::LLVMIntegerType::get(ctx, 64);
+  auto i8Ptr = LLVM::LLVMPointerType::get(LLVM::LLVMIntegerType::get(ctx, 8));
 
   Block *entryBlock = func.addEntryBlock();
   Location loc = func.getBody().getLoc();
 
-  OpBuilder builder = OpBuilder::atBlockBegin(entryBlock);
+  auto builder = ImplicitLocOpBuilder::atBlockBegin(loc, entryBlock);
 
   // ------------------------------------------------------------------------ //
   // Allocate async tokens/values that we will return from a ramp function.
   // ------------------------------------------------------------------------ //
-  auto createToken =
-      builder.create<CallOp>(loc, kCreateToken, TokenType::get(ctx));
+  auto createToken = builder.create<CallOp>(kCreateToken, TokenType::get(ctx));
+
+  // Async value operands and results must be convertible to LLVM types. This is
+  // verified before the function outlining.
+  LLVMTypeConverter converter(ctx);
+
+  // Returns the size requirements for the async value storage.
+  // http://nondot.org/sabre/LLVMNotes/SizeOf-OffsetOf-VariableSizedStructs.txt
+  auto sizeOf = [&](ValueType valueType) -> Value {
+    auto storedType = converter.convertType(valueType.getValueType());
+    auto storagePtrType =
+        LLVM::LLVMPointerType::get(storedType.cast<LLVM::LLVMType>());
+
+    // %Size = getelementptr %T* null, int 1
+    // %SizeI = ptrtoint %T* %Size to i32
+    auto nullPtr = builder.create<LLVM::NullOp>(loc, storagePtrType);
+    auto one = builder.create<LLVM::ConstantOp>(loc, i32,
+                                                builder.getI32IntegerAttr(1));
+    auto gep = builder.create<LLVM::GEPOp>(loc, storagePtrType, nullPtr,
+                                           one.getResult());
+    auto size = builder.create<LLVM::PtrToIntOp>(loc, i32, gep);
+
+    // Cast to std type because runtime API defined using std types.
+    return builder.create<LLVM::DialectCastOp>(loc, builder.getI32Type(),
+                                               size.getResult());
+  };
+
+  // We use the `async.value` type as a return type although it does not match
+  // the `kCreateValue` function signature, because it will be later lowered to
+  // the runtime type (opaque i8* pointer).
+  llvm::SmallVector<CallOp, 4> createValues;
+  for (auto resultType : func.getCallableResults().drop_front(1))
+    createValues.emplace_back(builder.create<CallOp>(
+        loc, kCreateValue, resultType, sizeOf(resultType.cast<ValueType>())));
+
+  auto createdValues = llvm::map_range(
+      createValues, [](CallOp call) { return call.getResult(0); });
+  llvm::SmallVector<Value, 4> returnValues(createdValues.begin(),
+                                           createdValues.end());
 
   // ------------------------------------------------------------------------ //
   // Initialize coroutine: allocate frame, get coroutine handle.
@@ -316,28 +422,28 @@ static CoroMachinery setupCoroMachinery(FuncOp func) {
 
   // Constants for initializing coroutine frame.
   auto constZero =
-      builder.create<LLVM::ConstantOp>(loc, i32, builder.getI32IntegerAttr(0));
+      builder.create<LLVM::ConstantOp>(i32, builder.getI32IntegerAttr(0));
   auto constFalse =
-      builder.create<LLVM::ConstantOp>(loc, i1, builder.getBoolAttr(false));
-  auto nullPtr = builder.create<LLVM::NullOp>(loc, i8Ptr);
+      builder.create<LLVM::ConstantOp>(i1, builder.getBoolAttr(false));
+  auto nullPtr = builder.create<LLVM::NullOp>(i8Ptr);
 
   // Get coroutine id: @llvm.coro.id
   auto coroId = builder.create<LLVM::CallOp>(
-      loc, token, builder.getSymbolRefAttr(kCoroId),
+      token, builder.getSymbolRefAttr(kCoroId),
       ValueRange({constZero, nullPtr, nullPtr, nullPtr}));
 
   // Get coroutine frame size: @llvm.coro.size.i64
   auto coroSize = builder.create<LLVM::CallOp>(
-      loc, i64, builder.getSymbolRefAttr(kCoroSizeI64), ValueRange());
+      i64, builder.getSymbolRefAttr(kCoroSizeI64), ValueRange());
 
   // Allocate memory for coroutine frame.
-  auto coroAlloc = builder.create<LLVM::CallOp>(
-      loc, i8Ptr, builder.getSymbolRefAttr(kMalloc),
-      ValueRange(coroSize.getResult(0)));
+  auto coroAlloc =
+      builder.create<LLVM::CallOp>(i8Ptr, builder.getSymbolRefAttr(kMalloc),
+                                   ValueRange(coroSize.getResult(0)));
 
   // Begin a coroutine: @llvm.coro.begin
   auto coroHdl = builder.create<LLVM::CallOp>(
-      loc, i8Ptr, builder.getSymbolRefAttr(kCoroBegin),
+      i8Ptr, builder.getSymbolRefAttr(kCoroBegin),
       ValueRange({coroId.getResult(0), coroAlloc.getResult(0)}));
 
   Block *cleanupBlock = func.addBlock();
@@ -350,15 +456,14 @@ static CoroMachinery setupCoroMachinery(FuncOp func) {
 
   // Get a pointer to the coroutine frame memory: @llvm.coro.free.
   auto coroMem = builder.create<LLVM::CallOp>(
-      loc, i8Ptr, builder.getSymbolRefAttr(kCoroFree),
+      i8Ptr, builder.getSymbolRefAttr(kCoroFree),
       ValueRange({coroId.getResult(0), coroHdl.getResult(0)}));
 
   // Free the memory.
-  builder.create<LLVM::CallOp>(loc, TypeRange(),
-                               builder.getSymbolRefAttr(kFree),
+  builder.create<LLVM::CallOp>(TypeRange(), builder.getSymbolRefAttr(kFree),
                                ValueRange(coroMem.getResult(0)));
   // Branch into the suspend block.
-  builder.create<BranchOp>(loc, suspendBlock);
+  builder.create<BranchOp>(suspendBlock);
 
   // ------------------------------------------------------------------------ //
   // Coroutine suspend block: mark the end of a coroutine and return allocated
@@ -367,61 +472,68 @@ static CoroMachinery setupCoroMachinery(FuncOp func) {
   builder.setInsertionPointToStart(suspendBlock);
 
   // Mark the end of a coroutine: @llvm.coro.end.
-  builder.create<LLVM::CallOp>(loc, i1, builder.getSymbolRefAttr(kCoroEnd),
+  builder.create<LLVM::CallOp>(i1, builder.getSymbolRefAttr(kCoroEnd),
                                ValueRange({coroHdl.getResult(0), constFalse}));
 
-  // Return created `async.token` from the suspend block. This will be the
-  // return value of a coroutine ramp function.
-  builder.create<ReturnOp>(loc, createToken.getResult(0));
+  // Return created `async.token` and `async.values` from the suspend block.
+  // This will be the return value of a coroutine ramp function.
+  SmallVector<Value, 4> ret{createToken.getResult(0)};
+  ret.insert(ret.end(), returnValues.begin(), returnValues.end());
+  builder.create<ReturnOp>(loc, ret);
 
   // Branch from the entry block to the cleanup block to create a valid CFG.
   builder.setInsertionPointToEnd(entryBlock);
 
-  builder.create<BranchOp>(loc, cleanupBlock);
+  builder.create<BranchOp>(cleanupBlock);
 
   // `async.await` op lowering will create resume blocks for async
   // continuations, and will conditionally branch to cleanup or suspend blocks.
 
-  return {createToken.getResult(0), coroHdl.getResult(0), cleanupBlock,
-          suspendBlock};
+  CoroMachinery machinery;
+  machinery.asyncToken = createToken.getResult(0);
+  machinery.returnValues = returnValues;
+  machinery.coroHandle = coroHdl.getResult(0);
+  machinery.cleanup = cleanupBlock;
+  machinery.suspend = suspendBlock;
+  return machinery;
 }
 
-// Add a LLVM coroutine suspension point to the end of suspended block, to
-// resume execution in resume block. The caller is responsible for creating the
-// two suspended/resume blocks with the desired ops contained in each block.
-// This function merely provides the required control flow logic.
-//
-// `coroState` must be a value returned from the call to @llvm.coro.save(...)
-// intrinsic (saved coroutine state).
-//
-// Before:
-//
-//   ^bb0:
-//     "opBefore"(...)
-//     "op"(...)
-//   ^cleanup: ...
-//   ^suspend: ...
-//   ^resume:
-//     "op"(...)
-//
-// After:
-//
-//   ^bb0:
-//     "opBefore"(...)
-//     %suspend = llmv.call @llvm.coro.suspend(...)
-//     switch %suspend [-1: ^suspend, 0: ^resume, 1: ^cleanup]
-//   ^resume:
-//     "op"(...)
-//   ^cleanup: ...
-//   ^suspend: ...
-//
+/// Add a LLVM coroutine suspension point to the end of suspended block, to
+/// resume execution in resume block. The caller is responsible for creating the
+/// two suspended/resume blocks with the desired ops contained in each block.
+/// This function merely provides the required control flow logic.
+///
+/// `coroState` must be a value returned from the call to @llvm.coro.save(...)
+/// intrinsic (saved coroutine state).
+///
+/// Before:
+///
+///   ^bb0:
+///     "opBefore"(...)
+///     "op"(...)
+///   ^cleanup: ...
+///   ^suspend: ...
+///   ^resume:
+///     "op"(...)
+///
+/// After:
+///
+///   ^bb0:
+///     "opBefore"(...)
+///     %suspend = llmv.call @llvm.coro.suspend(...)
+///     switch %suspend [-1: ^suspend, 0: ^resume, 1: ^cleanup]
+///   ^resume:
+///     "op"(...)
+///   ^cleanup: ...
+///   ^suspend: ...
+///
 static void addSuspensionPoint(CoroMachinery coro, Value coroState,
                                Operation *op, Block *suspended, Block *resume,
                                OpBuilder &builder) {
   Location loc = op->getLoc();
   MLIRContext *ctx = op->getContext();
-  auto i1 = LLVM::LLVMType::getInt1Ty(ctx);
-  auto i8 = LLVM::LLVMType::getInt8Ty(ctx);
+  auto i1 = LLVM::LLVMIntegerType::get(ctx, 1);
+  auto i8 = LLVM::LLVMIntegerType::get(ctx, 8);
 
   // Add a coroutine suspension in place of original `op` in the split block.
   OpBuilder::InsertionGuard guard(builder);
@@ -460,10 +572,10 @@ static void addSuspensionPoint(CoroMachinery coro, Value coroState,
                                  /*falseDest=*/coro.cleanup);
 }
 
-// Outline the body region attached to the `async.execute` op into a standalone
-// function.
-//
-// Note that this is not reversible transformation.
+/// Outline the body region attached to the `async.execute` op into a standalone
+/// function.
+///
+/// Note that this is not reversible transformation.
 static std::pair<FuncOp, CoroMachinery>
 outlineExecuteOp(SymbolTable &symbolTable, ExecuteOp execute) {
   ModuleOp module = execute->getParentOfType<ModuleOp>();
@@ -471,11 +583,10 @@ outlineExecuteOp(SymbolTable &symbolTable, ExecuteOp execute) {
   MLIRContext *ctx = module.getContext();
   Location loc = execute.getLoc();
 
-  OpBuilder moduleBuilder(module.getBody()->getTerminator());
-
   // Collect all outlined function inputs.
   llvm::SetVector<mlir::Value> functionInputs(execute.dependencies().begin(),
                                               execute.dependencies().end());
+  functionInputs.insert(execute.operands().begin(), execute.operands().end());
   getUsedValuesDefinedAbove(execute.body(), functionInputs);
 
   // Collect types for the outlined function inputs and outputs.
@@ -484,13 +595,13 @@ outlineExecuteOp(SymbolTable &symbolTable, ExecuteOp execute) {
   SmallVector<Type, 4> inputTypes(typesRange.begin(), typesRange.end());
   auto outputTypes = execute.getResultTypes();
 
-  auto funcType = moduleBuilder.getFunctionType(inputTypes, outputTypes);
+  auto funcType = FunctionType::get(ctx, inputTypes, outputTypes);
   auto funcAttrs = ArrayRef<NamedAttribute>();
 
   // TODO: Derive outlined function name from the parent FuncOp (support
   // multiple nested async.execute operations).
   FuncOp func = FuncOp::create(loc, kAsyncFnPrefix, funcType, funcAttrs);
-  symbolTable.insert(func, moduleBuilder.getInsertionPoint());
+  symbolTable.insert(func, Block::iterator(module.getBody()->getTerminator()));
 
   SymbolTable::setSymbolVisibility(func, SymbolTable::Visibility::Private);
 
@@ -502,21 +613,21 @@ outlineExecuteOp(SymbolTable &symbolTable, ExecuteOp execute) {
   // Async execute API (execution will be resumed in a thread managed by the
   // async runtime).
   Block *entryBlock = &func.getBlocks().front();
-  OpBuilder builder = OpBuilder::atBlockTerminator(entryBlock);
+  auto builder = ImplicitLocOpBuilder::atBlockTerminator(loc, entryBlock);
 
   // A pointer to coroutine resume intrinsic wrapper.
   auto resumeFnTy = AsyncAPI::resumeFunctionType(ctx);
   auto resumePtr = builder.create<LLVM::AddressOfOp>(
-      loc, resumeFnTy.getPointerTo(), kResume);
+      LLVM::LLVMPointerType::get(resumeFnTy), kResume);
 
   // Save the coroutine state: @llvm.coro.save
   auto coroSave = builder.create<LLVM::CallOp>(
-      loc, LLVM::LLVMTokenType::get(ctx), builder.getSymbolRefAttr(kCoroSave),
+      LLVM::LLVMTokenType::get(ctx), builder.getSymbolRefAttr(kCoroSave),
       ValueRange({coro.coroHandle}));
 
   // Call async runtime API to execute a coroutine in the managed thread.
   SmallVector<Value, 2> executeArgs = {coro.coroHandle, resumePtr.res()};
-  builder.create<CallOp>(loc, TypeRange(), kExecute, executeArgs);
+  builder.create<CallOp>(TypeRange(), kExecute, executeArgs);
 
   // Split the entry block before the terminator.
   auto *terminatorOp = entryBlock->getTerminator();
@@ -525,32 +636,36 @@ outlineExecuteOp(SymbolTable &symbolTable, ExecuteOp execute) {
   addSuspensionPoint(coro, coroSave.getResult(0), terminatorOp, suspended,
                      resume, builder);
 
+  size_t numDependencies = execute.dependencies().size();
+  size_t numOperands = execute.operands().size();
+
   // Await on all dependencies before starting to execute the body region.
   builder.setInsertionPointToStart(resume);
-  for (size_t i = 0; i < execute.dependencies().size(); ++i)
-    builder.create<AwaitOp>(loc, func.getArgument(i));
+  for (size_t i = 0; i < numDependencies; ++i)
+    builder.create<AwaitOp>(func.getArgument(i));
+
+  // Await on all async value operands and unwrap the payload.
+  SmallVector<Value, 4> unwrappedOperands(numOperands);
+  for (size_t i = 0; i < numOperands; ++i) {
+    Value operand = func.getArgument(numDependencies + i);
+    unwrappedOperands[i] = builder.create<AwaitOp>(loc, operand).result();
+  }
 
   // Map from function inputs defined above the execute op to the function
   // arguments.
   BlockAndValueMapping valueMapping;
   valueMapping.map(functionInputs, func.getArguments());
+  valueMapping.map(execute.body().getArguments(), unwrappedOperands);
 
   // Clone all operations from the execute operation body into the outlined
-  // function body, and replace all `async.yield` operations with a call
-  // to async runtime to emplace the result token.
-  for (Operation &op : execute.body().getOps()) {
-    if (isa<async::YieldOp>(op)) {
-      builder.create<CallOp>(loc, kEmplaceToken, TypeRange(), coro.asyncToken);
-      continue;
-    }
+  // function body.
+  for (Operation &op : execute.body().getOps())
     builder.clone(op, valueMapping);
-  }
 
   // Replace the original `async.execute` with a call to outlined function.
-  OpBuilder callBuilder(execute);
-  auto callOutlinedFunc =
-      callBuilder.create<CallOp>(loc, func.getName(), execute.getResultTypes(),
-                                 functionInputs.getArrayRef());
+  ImplicitLocOpBuilder callBuilder(loc, execute);
+  auto callOutlinedFunc = callBuilder.create<CallOp>(
+      func.getName(), execute.getResultTypes(), functionInputs.getArrayRef());
   execute.replaceAllUsesWith(callOutlinedFunc.getResults());
   execute.erase();
 
@@ -562,42 +677,38 @@ outlineExecuteOp(SymbolTable &symbolTable, ExecuteOp execute) {
 //===----------------------------------------------------------------------===//
 
 namespace {
+
+/// AsyncRuntimeTypeConverter only converts types from the Async dialect to
+/// their runtime type (opaque pointers) and does not convert any other types.
 class AsyncRuntimeTypeConverter : public TypeConverter {
 public:
-  AsyncRuntimeTypeConverter() { addConversion(convertType); }
-
-  static Type convertType(Type type) {
-    MLIRContext *ctx = type.getContext();
-    // Convert async tokens and groups to opaque pointers.
-    if (type.isa<TokenType, GroupType>())
-      return LLVM::LLVMType::getInt8PtrTy(ctx);
-    return type;
+  AsyncRuntimeTypeConverter() {
+    addConversion([](Type type) { return type; });
+    addConversion(convertAsyncTypes);
+  }
+
+  static Optional<Type> convertAsyncTypes(Type type) {
+    if (type.isa<TokenType, GroupType, ValueType>())
+      return AsyncAPI::opaquePointerType(type.getContext());
+    return llvm::None;
   }
 };
 } // namespace
 
 //===----------------------------------------------------------------------===//
-// Convert types for all call operations to lowered async types.
+// Convert return operations that return async values from async regions.
 //===----------------------------------------------------------------------===//
 
 namespace {
-class CallOpOpConversion : public ConversionPattern {
+class ReturnOpOpConversion : public ConversionPattern {
 public:
-  explicit CallOpOpConversion(MLIRContext *ctx)
-      : ConversionPattern(CallOp::getOperationName(), 1, ctx) {}
+  explicit ReturnOpOpConversion(TypeConverter &converter, MLIRContext *ctx)
+      : ConversionPattern(ReturnOp::getOperationName(), 1, converter, ctx) {}
 
   LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
-    AsyncRuntimeTypeConverter converter;
-
-    SmallVector<Type, 5> resultTypes;
-    converter.convertTypes(op->getResultTypes(), resultTypes);
-
-    CallOp call = cast<CallOp>(op);
-    rewriter.replaceOpWithNewOp<CallOp>(op, resultTypes, call.callee(),
-                                        operands);
-
+    rewriter.replaceOpWithNewOp<ReturnOp>(op, operands);
     return success();
   }
 };
@@ -613,8 +724,9 @@ namespace {
 template <typename RefCountingOp>
 class RefCountingOpLowering : public ConversionPattern {
 public:
-  explicit RefCountingOpLowering(MLIRContext *ctx, StringRef apiFunctionName)
-      : ConversionPattern(RefCountingOp::getOperationName(), 1, ctx),
+  explicit RefCountingOpLowering(TypeConverter &converter, MLIRContext *ctx,
+                                 StringRef apiFunctionName)
+      : ConversionPattern(RefCountingOp::getOperationName(), 1, converter, ctx),
         apiFunctionName(apiFunctionName) {}
 
   LogicalResult
@@ -636,18 +748,18 @@ class RefCountingOpLowering : public ConversionPattern {
   StringRef apiFunctionName;
 };
 
-// async.drop_ref op lowering to mlirAsyncRuntimeDropRef function call.
+/// async.drop_ref op lowering to mlirAsyncRuntimeDropRef function call.
 class AddRefOpLowering : public RefCountingOpLowering<AddRefOp> {
 public:
-  explicit AddRefOpLowering(MLIRContext *ctx)
-      : RefCountingOpLowering(ctx, kAddRef) {}
+  explicit AddRefOpLowering(TypeConverter &converter, MLIRContext *ctx)
+      : RefCountingOpLowering(converter, ctx, kAddRef) {}
 };
 
-// async.create_group op lowering to mlirAsyncRuntimeCreateGroup function call.
+/// async.create_group op lowering to mlirAsyncRuntimeCreateGroup function call.
 class DropRefOpLowering : public RefCountingOpLowering<DropRefOp> {
 public:
-  explicit DropRefOpLowering(MLIRContext *ctx)
-      : RefCountingOpLowering(ctx, kDropRef) {}
+  explicit DropRefOpLowering(TypeConverter &converter, MLIRContext *ctx)
+      : RefCountingOpLowering(converter, ctx, kDropRef) {}
 };
 
 } // namespace
@@ -659,8 +771,9 @@ class DropRefOpLowering : public RefCountingOpLowering<DropRefOp> {
 namespace {
 class CreateGroupOpLowering : public ConversionPattern {
 public:
-  explicit CreateGroupOpLowering(MLIRContext *ctx)
-      : ConversionPattern(CreateGroupOp::getOperationName(), 1, ctx) {}
+  explicit CreateGroupOpLowering(TypeConverter &converter, MLIRContext *ctx)
+      : ConversionPattern(CreateGroupOp::getOperationName(), 1, converter,
+                          ctx) {}
 
   LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
@@ -679,8 +792,9 @@ class CreateGroupOpLowering : public ConversionPattern {
 namespace {
 class AddToGroupOpLowering : public ConversionPattern {
 public:
-  explicit AddToGroupOpLowering(MLIRContext *ctx)
-      : ConversionPattern(AddToGroupOp::getOperationName(), 1, ctx) {}
+  explicit AddToGroupOpLowering(TypeConverter &converter, MLIRContext *ctx)
+      : ConversionPattern(AddToGroupOp::getOperationName(), 1, converter, ctx) {
+  }
 
   LogicalResult
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
@@ -708,10 +822,10 @@ template <typename AwaitType, typename AwaitableType>
 class AwaitOpLoweringBase : public ConversionPattern {
 protected:
   explicit AwaitOpLoweringBase(
-      MLIRContext *ctx,
+      TypeConverter &converter, MLIRContext *ctx,
       const llvm::DenseMap<FuncOp, CoroMachinery> &outlinedFunctions,
       StringRef blockingAwaitFuncName, StringRef coroAwaitFuncName)
-      : ConversionPattern(AwaitType::getOperationName(), 1, ctx),
+      : ConversionPattern(AwaitType::getOperationName(), 1, converter, ctx),
         outlinedFunctions(outlinedFunctions),
         blockingAwaitFuncName(blockingAwaitFuncName),
         coroAwaitFuncName(coroAwaitFuncName) {}
@@ -721,7 +835,7 @@ class AwaitOpLoweringBase : public ConversionPattern {
   matchAndRewrite(Operation *op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     // We can only await on one the `AwaitableType` (for `await` it can be
-    // only a `token`, for `await_all` it is a `group`).
+    // a `token` or a `value`, for `await_all` it must be a `group`).
     auto await = cast<AwaitType>(op);
     if (!await.operand().getType().template isa<AwaitableType>())
       return failure();
@@ -744,24 +858,24 @@ class AwaitOpLoweringBase : public ConversionPattern {
     if (isInCoroutine) {
       const CoroMachinery &coro = outlined->getSecond();
 
-      OpBuilder builder(op, rewriter.getListener());
+      ImplicitLocOpBuilder builder(loc, op, rewriter.getListener());
       MLIRContext *ctx = op->getContext();
 
       // A pointer to coroutine resume intrinsic wrapper.
       auto resumeFnTy = AsyncAPI::resumeFunctionType(ctx);
       auto resumePtr = builder.create<LLVM::AddressOfOp>(
-          loc, resumeFnTy.getPointerTo(), kResume);
+          LLVM::LLVMPointerType::get(resumeFnTy), kResume);
 
       // Save the coroutine state: @llvm.coro.save
       auto coroSave = builder.create<LLVM::CallOp>(
-          loc, LLVM::LLVMTokenType::get(ctx),
-          builder.getSymbolRefAttr(kCoroSave), ValueRange(coro.coroHandle));
+          LLVM::LLVMTokenType::get(ctx), builder.getSymbolRefAttr(kCoroSave),
+          ValueRange(coro.coroHandle));
 
       // Call async runtime API to resume a coroutine in the managed thread when
       // the async await argument becomes ready.
       SmallVector<Value, 3> awaitAndExecuteArgs = {operands[0], coro.coroHandle,
                                                    resumePtr.res()};
-      builder.create<CallOp>(loc, TypeRange(), coroAwaitFuncName,
+      builder.create<CallOp>(TypeRange(), coroAwaitFuncName,
                              awaitAndExecuteArgs);
 
       Block *suspended = op->getBlock();
@@ -770,44 +884,163 @@ class AwaitOpLoweringBase : public ConversionPattern {
       Block *resume = rewriter.splitBlock(suspended, Block::iterator(op));
       addSuspensionPoint(coro, coroSave.getResult(0), op, suspended, resume,
                          builder);
+
+      // Make sure that replacement value will be constructed in resume block.
+      rewriter.setInsertionPointToStart(resume);
     }
 
-    // Original operation was replaced by function call or suspension point.
-    rewriter.eraseOp(op);
+    // Replace or erase the await operation with the new value.
+    if (Value replaceWith = getReplacementValue(op, operands[0], rewriter))
+      rewriter.replaceOp(op, replaceWith);
+    else
+      rewriter.eraseOp(op);
 
     return success();
   }
 
+  virtual Value getReplacementValue(Operation *op, Value operand,
+                                    ConversionPatternRewriter &rewriter) const {
+    return Value();
+  }
+
 private:
   const llvm::DenseMap<FuncOp, CoroMachinery> &outlinedFunctions;
   StringRef blockingAwaitFuncName;
   StringRef coroAwaitFuncName;
 };
 
-// Lowering for `async.await` operation (only token operands are supported).
-class AwaitOpLowering : public AwaitOpLoweringBase<AwaitOp, TokenType> {
+/// Lowering for `async.await` with a token operand.
+class AwaitTokenOpLowering : public AwaitOpLoweringBase<AwaitOp, TokenType> {
   using Base = AwaitOpLoweringBase<AwaitOp, TokenType>;
 
 public:
-  explicit AwaitOpLowering(
-      MLIRContext *ctx,
+  explicit AwaitTokenOpLowering(
+      TypeConverter &converter, MLIRContext *ctx,
       const llvm::DenseMap<FuncOp, CoroMachinery> &outlinedFunctions)
-      : Base(ctx, outlinedFunctions, kAwaitToken, kAwaitAndExecute) {}
+      : Base(converter, ctx, outlinedFunctions, kAwaitToken,
+             kAwaitTokenAndExecute) {}
 };
 
-// Lowering for `async.await_all` operation.
+/// Lowering for `async.await` with a value operand.
+class AwaitValueOpLowering : public AwaitOpLoweringBase<AwaitOp, ValueType> {
+  using Base = AwaitOpLoweringBase<AwaitOp, ValueType>;
+
+public:
+  explicit AwaitValueOpLowering(
+      TypeConverter &converter, MLIRContext *ctx,
+      const llvm::DenseMap<FuncOp, CoroMachinery> &outlinedFunctions)
+      : Base(converter, ctx, outlinedFunctions, kAwaitValue,
+             kAwaitValueAndExecute) {}
+
+  Value
+  getReplacementValue(Operation *op, Value operand,
+                      ConversionPatternRewriter &rewriter) const override {
+    Location loc = op->getLoc();
+    auto i8Ptr = AsyncAPI::opaquePointerType(rewriter.getContext());
+
+    // Get the underlying value type from the `async.value`.
+    auto await = cast<AwaitOp>(op);
+    auto valueType = await.operand().getType().cast<ValueType>().getValueType();
+
+    // Get a pointer to an async value storage from the runtime.
+    auto storage = rewriter.create<CallOp>(loc, kGetValueStorage,
+                                           TypeRange(i8Ptr), operand);
+
+    // Cast from i8* to the pointer pointer to LLVM type.
+    auto llvmValueType = getTypeConverter()->convertType(valueType);
+    auto castedStorage = rewriter.create<LLVM::BitcastOp>(
+        loc, LLVM::LLVMPointerType::get(llvmValueType.cast<LLVM::LLVMType>()),
+        storage.getResult(0));
+
+    // Load from the async value storage.
+    auto loaded = rewriter.create<LLVM::LoadOp>(loc, castedStorage.getResult());
+
+    // Cast from LLVM type to the expected value type. This cast will become
+    // no-op after lowering to LLVM.
+    return rewriter.create<LLVM::DialectCastOp>(loc, valueType, loaded);
+  }
+};
+
+/// Lowering for `async.await_all` operation.
 class AwaitAllOpLowering : public AwaitOpLoweringBase<AwaitAllOp, GroupType> {
   using Base = AwaitOpLoweringBase<AwaitAllOp, GroupType>;
 
 public:
   explicit AwaitAllOpLowering(
-      MLIRContext *ctx,
+      TypeConverter &converter, MLIRContext *ctx,
       const llvm::DenseMap<FuncOp, CoroMachinery> &outlinedFunctions)
-      : Base(ctx, outlinedFunctions, kAwaitGroup, kAwaitAllAndExecute) {}
+      : Base(converter, ctx, outlinedFunctions, kAwaitGroup,
+             kAwaitAllAndExecute) {}
 };
 
 } // namespace
 
+//===----------------------------------------------------------------------===//
+// async.yield op lowerings to the corresponding async runtime function calls.
+//===----------------------------------------------------------------------===//
+
+class YieldOpLowering : public ConversionPattern {
+public:
+  explicit YieldOpLowering(
+      TypeConverter &converter, MLIRContext *ctx,
+      const llvm::DenseMap<FuncOp, CoroMachinery> &outlinedFunctions)
+      : ConversionPattern(async::YieldOp::getOperationName(), 1, converter,
+                          ctx),
+        outlinedFunctions(outlinedFunctions) {}
+
+  LogicalResult
+  matchAndRewrite(Operation *op, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const override {
+    // Check if yield operation is inside the outlined coroutine function.
+    auto func = op->template getParentOfType<FuncOp>();
+    auto outlined = outlinedFunctions.find(func);
+    if (outlined == outlinedFunctions.end())
+      return op->emitOpError(
+          "async.yield is not inside the outlined coroutine function");
+
+    Location loc = op->getLoc();
+    const CoroMachinery &coro = outlined->getSecond();
+
+    // Store yielded values into the async values storage and emplace them.
+    auto i8Ptr = AsyncAPI::opaquePointerType(rewriter.getContext());
+
+    for (auto tuple : llvm::zip(operands, coro.returnValues)) {
+      // Store `yieldValue` into the `asyncValue` storage.
+      Value yieldValue = std::get<0>(tuple);
+      Value asyncValue = std::get<1>(tuple);
+
+      // Get an opaque i8* pointer to an async value storage from the runtime.
+      auto storage = rewriter.create<CallOp>(loc, kGetValueStorage,
+                                             TypeRange(i8Ptr), asyncValue);
+
+      // Cast storage pointer to the yielded value type.
+      auto castedStorage = rewriter.create<LLVM::BitcastOp>(
+          loc,
+          LLVM::LLVMPointerType::get(
+              yieldValue.getType().cast<LLVM::LLVMType>()),
+          storage.getResult(0));
+
+      // Store the yielded value into the async value storage.
+      rewriter.create<LLVM::StoreOp>(loc, yieldValue,
+                                     castedStorage.getResult());
+
+      // Emplace the `async.value` to mark it ready.
+      rewriter.create<CallOp>(loc, kEmplaceValue, TypeRange(), asyncValue);
+    }
+
+    // Emplace the completion token to mark it ready.
+    rewriter.create<CallOp>(loc, kEmplaceToken, TypeRange(), coro.asyncToken);
+
+    // Original operation was replaced by the function call(s).
+    rewriter.eraseOp(op);
+
+    return success();
+  }
+
+private:
+  const llvm::DenseMap<FuncOp, CoroMachinery> &outlinedFunctions;
+};
+
 //===----------------------------------------------------------------------===//
 
 namespace {
@@ -820,15 +1053,30 @@ void ConvertAsyncToLLVMPass::runOnOperation() {
   ModuleOp module = getOperation();
   SymbolTable symbolTable(module);
 
+  MLIRContext *ctx = &getContext();
+
   // Outline all `async.execute` body regions into async functions (coroutines).
   llvm::DenseMap<FuncOp, CoroMachinery> outlinedFunctions;
 
+  // We use conversion to LLVM type to ensure that all `async.value` operands
+  // and results can be lowered to LLVM load and store operations.
+  LLVMTypeConverter llvmConverter(ctx);
+  llvmConverter.addConversion(AsyncRuntimeTypeConverter::convertAsyncTypes);
+
+  // Returns true if the `async.value` payload is convertible to LLVM.
+  auto isConvertibleToLlvm = [&](Type type) -> bool {
+    auto valueType = type.cast<ValueType>().getValueType();
+    return static_cast<bool>(llvmConverter.convertType(valueType));
+  };
+
   WalkResult outlineResult = module.walk([&](ExecuteOp execute) {
-    // We currently do not support execute operations that have async value
-    // operands or produce async results.
-    if (!execute.operands().empty() || !execute.results().empty()) {
-      execute.emitOpError("can't outline async.execute op with async value "
-                          "operands or returned async results");
+    // All operands and results must be convertible to LLVM.
+    if (!llvm::all_of(execute.operands().getTypes(), isConvertibleToLlvm)) {
+      execute.emitOpError("operands payload must be convertible to LLVM type");
+      return WalkResult::interrupt();
+    }
+    if (!llvm::all_of(execute.results().getTypes(), isConvertibleToLlvm)) {
+      execute.emitOpError("results payload must be convertible to LLVM type");
       return WalkResult::interrupt();
     }
 
@@ -854,26 +1102,44 @@ void ConvertAsyncToLLVMPass::runOnOperation() {
   addCoroutineIntrinsicsDeclarations(module);
   addCRuntimeDeclarations(module);
 
-  MLIRContext *ctx = &getContext();
-
   // Convert async dialect types and operations to LLVM dialect.
   AsyncRuntimeTypeConverter converter;
   OwningRewritePatternList patterns;
 
+  // Convert async types in function signatures and function calls.
   populateFuncOpTypeConversionPattern(patterns, ctx, converter);
-  patterns.insert<CallOpOpConversion>(ctx);
-  patterns.insert<AddRefOpLowering, DropRefOpLowering>(ctx);
-  patterns.insert<CreateGroupOpLowering, AddToGroupOpLowering>(ctx);
-  patterns.insert<AwaitOpLowering, AwaitAllOpLowering>(ctx, outlinedFunctions);
+  populateCallOpTypeConversionPattern(patterns, ctx, converter);
+
+  // Convert return operations inside async.execute regions.
+  patterns.insert<ReturnOpOpConversion>(converter, ctx);
+
+  // Lower async operations to async runtime API calls.
+  patterns.insert<AddRefOpLowering, DropRefOpLowering>(converter, ctx);
+  patterns.insert<CreateGroupOpLowering, AddToGroupOpLowering>(converter, ctx);
+
+  // Use LLVM type converter to automatically convert between the async value
+  // payload type and LLVM type when loading/storing from/to the async
+  // value storage which is an opaque i8* pointer using LLVM load/store ops.
+  patterns
+      .insert<AwaitTokenOpLowering, AwaitValueOpLowering, AwaitAllOpLowering>(
+          llvmConverter, ctx, outlinedFunctions);
+  patterns.insert<YieldOpLowering>(llvmConverter, ctx, outlinedFunctions);
 
   ConversionTarget target(*ctx);
   target.addLegalOp<ConstantOp>();
   target.addLegalDialect<LLVM::LLVMDialect>();
+
+  // All operations from Async dialect must be lowered to the runtime API calls.
   target.addIllegalDialect<AsyncDialect>();
+
+  // Add dynamic legality constraints to apply conversions defined above.
   target.addDynamicallyLegalOp<FuncOp>(
       [&](FuncOp op) { return converter.isSignatureLegal(op.getType()); });
-  target.addDynamicallyLegalOp<CallOp>(
-      [&](CallOp op) { return converter.isLegal(op.getResultTypes()); });
+  target.addDynamicallyLegalOp<ReturnOp>(
+      [&](ReturnOp op) { return converter.isLegal(op.getOperandTypes()); });
+  target.addDynamicallyLegalOp<CallOp>([&](CallOp op) {
+    return converter.isSignatureLegal(op.getCalleeType());
+  });
 
   if (failed(applyPartialConversion(module, target, std::move(patterns))))
     signalPassFailure();
diff --git a/mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt b/mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt
index 005712c6cb485..48c2e0155ae1c 100644
--- a/mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt
+++ b/mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt
@@ -13,5 +13,7 @@ add_mlir_conversion_library(MLIRAsyncToLLVM
   LINK_LIBS PUBLIC
   MLIRAsync
   MLIRLLVMIR
+  MLIRStandardOpsTransforms
+  MLIRStandardToLLVM
   MLIRTransforms
   )
diff --git a/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp b/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
index 3b4b39e57d557..6859834de67f5 100644
--- a/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
+++ b/mlir/lib/Conversion/GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp
@@ -55,14 +55,13 @@ class FunctionCallBuilder {
   FunctionCallBuilder(StringRef functionName, LLVM::LLVMType returnType,
                       ArrayRef<LLVM::LLVMType> argumentTypes)
       : functionName(functionName),
-        functionType(LLVM::LLVMType::getFunctionTy(returnType, argumentTypes,
-                                                   /*isVarArg=*/false)) {}
+        functionType(LLVM::LLVMFunctionType::get(returnType, argumentTypes)) {}
   LLVM::CallOp create(Location loc, OpBuilder &builder,
                       ArrayRef<Value> arguments) const;
 
 private:
   StringRef functionName;
-  LLVM::LLVMType functionType;
+  LLVM::LLVMFunctionType functionType;
 };
 
 template <typename OpTy>
@@ -74,13 +73,15 @@ class ConvertOpToGpuRuntimeCallPattern : public ConvertOpToLLVMPattern<OpTy> {
 protected:
   MLIRContext *context = &this->getTypeConverter()->getContext();
 
-  LLVM::LLVMType llvmVoidType = LLVM::LLVMType::getVoidTy(context);
-  LLVM::LLVMType llvmPointerType = LLVM::LLVMType::getInt8PtrTy(context);
-  LLVM::LLVMType llvmPointerPointerType = llvmPointerType.getPointerTo();
-  LLVM::LLVMType llvmInt8Type = LLVM::LLVMType::getInt8Ty(context);
-  LLVM::LLVMType llvmInt32Type = LLVM::LLVMType::getInt32Ty(context);
-  LLVM::LLVMType llvmInt64Type = LLVM::LLVMType::getInt64Ty(context);
-  LLVM::LLVMType llvmIntPtrType = LLVM::LLVMType::getIntNTy(
+  LLVM::LLVMType llvmVoidType = LLVM::LLVMVoidType::get(context);
+  LLVM::LLVMType llvmPointerType =
+      LLVM::LLVMPointerType::get(LLVM::LLVMIntegerType::get(context, 8));
+  LLVM::LLVMType llvmPointerPointerType =
+      LLVM::LLVMPointerType::get(llvmPointerType);
+  LLVM::LLVMType llvmInt8Type = LLVM::LLVMIntegerType::get(context, 8);
+  LLVM::LLVMType llvmInt32Type = LLVM::LLVMIntegerType::get(context, 32);
+  LLVM::LLVMType llvmInt64Type = LLVM::LLVMIntegerType::get(context, 64);
+  LLVM::LLVMType llvmIntPtrType = LLVM::LLVMIntegerType::get(
       context, this->getTypeConverter()->getPointerBitwidth(0));
 
   FunctionCallBuilder moduleLoadCallBuilder = {
@@ -151,6 +152,12 @@ class ConvertOpToGpuRuntimeCallPattern : public ConvertOpToLLVMPattern<OpTy> {
       "mgpuMemFree",
       llvmVoidType,
       {llvmPointerType /* void *ptr */, llvmPointerType /* void *stream */}};
+  FunctionCallBuilder memcpyCallBuilder = {
+      "mgpuMemcpy",
+      llvmVoidType,
+      {llvmPointerType /* void *dst */, llvmPointerType /* void *src */,
+       llvmIntPtrType /* intptr_t sizeBytes */,
+       llvmPointerType /* void *stream */}};
 };
 
 /// A rewrite pattern to convert gpu.host_register operations into a GPU runtime
@@ -268,6 +275,20 @@ class EraseGpuModuleOpPattern : public OpRewritePattern<gpu::GPUModuleOp> {
     return success();
   }
 };
+
+/// A rewrite pattern to convert gpu.memcpy operations into a GPU runtime
+/// call. Currently it supports CUDA and ROCm (HIP).
+class ConvertMemcpyOpToGpuRuntimeCallPattern
+    : public ConvertOpToGpuRuntimeCallPattern<gpu::MemcpyOp> {
+public:
+  ConvertMemcpyOpToGpuRuntimeCallPattern(LLVMTypeConverter &typeConverter)
+      : ConvertOpToGpuRuntimeCallPattern<gpu::MemcpyOp>(typeConverter) {}
+
+private:
+  LogicalResult
+  matchAndRewrite(gpu::MemcpyOp memcpyOp, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const override;
+};
 } // namespace
 
 void GpuToLLVMConversionPass::runOnOperation() {
@@ -292,7 +313,7 @@ LLVM::CallOp FunctionCallBuilder::create(Location loc, OpBuilder &builder,
         .create<LLVM::LLVMFuncOp>(loc, functionName, functionType);
   }();
   return builder.create<LLVM::CallOp>(
-      loc, const_cast<LLVM::LLVMType &>(functionType).getFunctionResultType(),
+      loc, const_cast<LLVM::LLVMFunctionType &>(functionType).getReturnType(),
       builder.getSymbolRefAttr(function), arguments);
 }
 
@@ -348,7 +369,7 @@ LogicalResult ConvertAllocOpToGpuRuntimeCallPattern::matchAndRewrite(
   MemRefType memRefType = allocOp.getType();
 
   if (failed(areAllLLVMTypes(allocOp, operands, rewriter)) ||
-      !isSupportedMemRefType(memRefType) ||
+      !isConvertibleAndHasIdentityMaps(memRefType) ||
       failed(isAsyncWithOneDependency(rewriter, allocOp)))
     return failure();
 
@@ -494,11 +515,12 @@ Value ConvertLaunchFuncOpToGpuRuntimeCallPattern::generateParamsArray(
   argumentTypes.reserve(numArguments);
   for (auto argument : arguments)
     argumentTypes.push_back(argument.getType().cast<LLVM::LLVMType>());
-  auto structType = LLVM::LLVMType::createStructTy(argumentTypes, StringRef());
+  auto structType = LLVM::LLVMStructType::getNewIdentified(context, StringRef(),
+                                                           argumentTypes);
   auto one = builder.create<LLVM::ConstantOp>(loc, llvmInt32Type,
                                               builder.getI32IntegerAttr(1));
   auto structPtr = builder.create<LLVM::AllocaOp>(
-      loc, structType.getPointerTo(), one, /*alignment=*/0);
+      loc, LLVM::LLVMPointerType::get(structType), one, /*alignment=*/0);
   auto arraySize = builder.create<LLVM::ConstantOp>(
       loc, llvmInt32Type, builder.getI32IntegerAttr(numArguments));
   auto arrayPtr = builder.create<LLVM::AllocaOp>(loc, llvmPointerPointerType,
@@ -509,7 +531,7 @@ Value ConvertLaunchFuncOpToGpuRuntimeCallPattern::generateParamsArray(
     auto index = builder.create<LLVM::ConstantOp>(
         loc, llvmInt32Type, builder.getI32IntegerAttr(en.index()));
     auto fieldPtr = builder.create<LLVM::GEPOp>(
-        loc, argumentTypes[en.index()].getPointerTo(), structPtr,
+        loc, LLVM::LLVMPointerType::get(argumentTypes[en.index()]), structPtr,
         ArrayRef<Value>{zero, index.getResult()});
     builder.create<LLVM::StoreOp>(loc, en.value(), fieldPtr);
     auto elementPtr = builder.create<LLVM::GEPOp>(loc, llvmPointerPointerType,
@@ -643,6 +665,50 @@ LogicalResult ConvertLaunchFuncOpToGpuRuntimeCallPattern::matchAndRewrite(
   return success();
 }
 
+LogicalResult ConvertMemcpyOpToGpuRuntimeCallPattern::matchAndRewrite(
+    gpu::MemcpyOp memcpyOp, ArrayRef<Value> operands,
+    ConversionPatternRewriter &rewriter) const {
+  auto memRefType = memcpyOp.src().getType().cast<MemRefType>();
+
+  if (failed(areAllLLVMTypes(memcpyOp, operands, rewriter)) ||
+      !isConvertibleAndHasIdentityMaps(memRefType) ||
+      failed(isAsyncWithOneDependency(rewriter, memcpyOp)))
+    return failure();
+
+  auto loc = memcpyOp.getLoc();
+  auto adaptor = gpu::MemcpyOpAdaptor(operands, memcpyOp->getAttrDictionary());
+
+  MemRefDescriptor srcDesc(adaptor.src());
+
+  Value numElements =
+      memRefType.hasStaticShape()
+          ? createIndexConstant(rewriter, loc, memRefType.getNumElements())
+          // For identity layouts (verified above), the number of elements is
+          // stride[0] * size[0].
+          : rewriter.create<LLVM::MulOp>(loc, srcDesc.stride(rewriter, loc, 0),
+                                         srcDesc.size(rewriter, loc, 0));
+
+  Type elementPtrType = getElementPtrType(memRefType);
+  Value nullPtr = rewriter.create<LLVM::NullOp>(loc, elementPtrType);
+  Value gepPtr = rewriter.create<LLVM::GEPOp>(
+      loc, elementPtrType, ArrayRef<Value>{nullPtr, numElements});
+  auto sizeBytes =
+      rewriter.create<LLVM::PtrToIntOp>(loc, getIndexType(), gepPtr);
+
+  auto src = rewriter.create<LLVM::BitcastOp>(
+      loc, llvmPointerType, srcDesc.alignedPtr(rewriter, loc));
+  auto dst = rewriter.create<LLVM::BitcastOp>(
+      loc, llvmPointerType,
+      MemRefDescriptor(adaptor.dst()).alignedPtr(rewriter, loc));
+
+  auto stream = adaptor.asyncDependencies().front();
+  memcpyCallBuilder.create(loc, rewriter, {dst, src, sizeBytes, stream});
+
+  rewriter.replaceOp(memcpyOp, {stream});
+
+  return success();
+}
+
 std::unique_ptr<mlir::OperationPass<mlir::ModuleOp>>
 mlir::createGpuToLLVMConversionPass(StringRef gpuBinaryAnnotation) {
   return std::make_unique<GpuToLLVMConversionPass>(gpuBinaryAnnotation);
@@ -651,13 +717,14 @@ mlir::createGpuToLLVMConversionPass(StringRef gpuBinaryAnnotation) {
 void mlir::populateGpuToLLVMConversionPatterns(
     LLVMTypeConverter &converter, OwningRewritePatternList &patterns,
     StringRef gpuBinaryAnnotation) {
-  converter.addConversion(
-      [context = &converter.getContext()](gpu::AsyncTokenType type) -> Type {
-        return LLVM::LLVMType::getInt8PtrTy(context);
-      });
+  converter.addConversion([context = &converter.getContext()](
+                              gpu::AsyncTokenType type) -> Type {
+    return LLVM::LLVMPointerType::get(LLVM::LLVMIntegerType::get(context, 8));
+  });
   patterns.insert<ConvertAllocOpToGpuRuntimeCallPattern,
                   ConvertDeallocOpToGpuRuntimeCallPattern,
                   ConvertHostRegisterOpToGpuRuntimeCallPattern,
+                  ConvertMemcpyOpToGpuRuntimeCallPattern,
                   ConvertWaitAsyncOpToGpuRuntimeCallPattern,
                   ConvertWaitOpToGpuRuntimeCallPattern>(converter);
   patterns.insert<ConvertLaunchFuncOpToGpuRuntimeCallPattern>(
diff --git a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
index bf17200e594f1..3acc73415ef12 100644
--- a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
+++ b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h
@@ -39,7 +39,7 @@ struct GPUFuncOpLowering : ConvertOpToLLVMPattern<gpu::GPUFuncOp> {
 
       auto elementType = typeConverter->convertType(type.getElementType())
                              .template cast<LLVM::LLVMType>();
-      auto arrayType = LLVM::LLVMType::getArrayTy(elementType, numElements);
+      auto arrayType = LLVM::LLVMArrayType::get(elementType, numElements);
       std::string name = std::string(
           llvm::formatv("__wg_{0}_{1}", gpuFuncOp.getName(), en.index()));
       auto globalOp = rewriter.create<LLVM::GlobalOp>(
@@ -51,8 +51,8 @@ struct GPUFuncOpLowering : ConvertOpToLLVMPattern<gpu::GPUFuncOp> {
 
     // Rewrite the original GPU function to an LLVM function.
     auto funcType = typeConverter->convertType(gpuFuncOp.getType())
-                        .template cast<LLVM::LLVMType>()
-                        .getPointerElementTy();
+                        .template cast<LLVM::LLVMPointerType>()
+                        .getElementType();
 
     // Remap proper input types.
     TypeConverter::SignatureConversion signatureConversion(
@@ -85,7 +85,7 @@ struct GPUFuncOpLowering : ConvertOpToLLVMPattern<gpu::GPUFuncOp> {
       // Rewrite workgroup memory attributions to addresses of global buffers.
       rewriter.setInsertionPointToStart(&gpuFuncOp.front());
       unsigned numProperArguments = gpuFuncOp.getNumArguments();
-      auto i32Type = LLVM::LLVMType::getInt32Ty(rewriter.getContext());
+      auto i32Type = LLVM::LLVMIntegerType::get(rewriter.getContext(), 32);
 
       Value zero = nullptr;
       if (!workgroupBuffers.empty())
@@ -94,10 +94,11 @@ struct GPUFuncOpLowering : ConvertOpToLLVMPattern<gpu::GPUFuncOp> {
       for (auto en : llvm::enumerate(workgroupBuffers)) {
         LLVM::GlobalOp global = en.value();
         Value address = rewriter.create<LLVM::AddressOfOp>(loc, global);
-        auto elementType = global.getType().getArrayElementType();
+        auto elementType =
+            global.getType().cast<LLVM::LLVMArrayType>().getElementType();
         Value memory = rewriter.create<LLVM::GEPOp>(
-            loc, elementType.getPointerTo(global.addr_space()), address,
-            ArrayRef<Value>{zero, zero});
+            loc, LLVM::LLVMPointerType::get(elementType, global.addr_space()),
+            address, ArrayRef<Value>{zero, zero});
 
         // Build a memref descriptor pointing to the buffer to plug with the
         // existing memref infrastructure. This may use more registers than
@@ -113,7 +114,7 @@ struct GPUFuncOpLowering : ConvertOpToLLVMPattern<gpu::GPUFuncOp> {
       // Rewrite private memory attributions to alloca'ed buffers.
       unsigned numWorkgroupAttributions =
           gpuFuncOp.getNumWorkgroupAttributions();
-      auto int64Ty = LLVM::LLVMType::getInt64Ty(rewriter.getContext());
+      auto int64Ty = LLVM::LLVMIntegerType::get(rewriter.getContext(), 64);
       for (auto en : llvm::enumerate(gpuFuncOp.getPrivateAttributions())) {
         Value attribution = en.value();
         auto type = attribution.getType().cast<MemRefType>();
@@ -123,9 +124,10 @@ struct GPUFuncOpLowering : ConvertOpToLLVMPattern<gpu::GPUFuncOp> {
         // Explicitly drop memory space when lowering private memory
         // attributions since NVVM models it as `alloca`s in the default
         // memory space and does not support `alloca`s with addrspace(5).
-        auto ptrType = typeConverter->convertType(type.getElementType())
-                           .template cast<LLVM::LLVMType>()
-                           .getPointerTo(AllocaAddrSpace);
+        auto ptrType = LLVM::LLVMPointerType::get(
+            typeConverter->convertType(type.getElementType())
+                .template cast<LLVM::LLVMType>(),
+            AllocaAddrSpace);
         Value numElements = rewriter.create<LLVM::ConstantOp>(
             gpuFuncOp.getLoc(), int64Ty,
             rewriter.getI64IntegerAttr(type.getNumElements()));
diff --git a/mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h b/mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
index a51dff51cac4b..0a1e76b99dbe2 100644
--- a/mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
+++ b/mlir/lib/Conversion/GPUCommon/IndexIntrinsicsOpLowering.h
@@ -48,13 +48,16 @@ struct GPUIndexIntrinsicOpLowering : public ConvertOpToLLVMPattern<Op> {
     Value newOp;
     switch (dimensionToIndex(op)) {
     case X:
-      newOp = rewriter.create<XOp>(loc, LLVM::LLVMType::getInt32Ty(context));
+      newOp =
+          rewriter.create<XOp>(loc, LLVM::LLVMIntegerType::get(context, 32));
       break;
     case Y:
-      newOp = rewriter.create<YOp>(loc, LLVM::LLVMType::getInt32Ty(context));
+      newOp =
+          rewriter.create<YOp>(loc, LLVM::LLVMIntegerType::get(context, 32));
       break;
     case Z:
-      newOp = rewriter.create<ZOp>(loc, LLVM::LLVMType::getInt32Ty(context));
+      newOp =
+          rewriter.create<ZOp>(loc, LLVM::LLVMIntegerType::get(context, 32));
       break;
     default:
       return failure();
@@ -62,10 +65,10 @@ struct GPUIndexIntrinsicOpLowering : public ConvertOpToLLVMPattern<Op> {
 
     if (indexBitwidth > 32) {
       newOp = rewriter.create<LLVM::SExtOp>(
-          loc, LLVM::LLVMType::getIntNTy(context, indexBitwidth), newOp);
+          loc, LLVM::LLVMIntegerType::get(context, indexBitwidth), newOp);
     } else if (indexBitwidth < 32) {
       newOp = rewriter.create<LLVM::TruncOp>(
-          loc, LLVM::LLVMType::getIntNTy(context, indexBitwidth), newOp);
+          loc, LLVM::LLVMIntegerType::get(context, indexBitwidth), newOp);
     }
 
     rewriter.replaceOp(op, {newOp});
diff --git a/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h b/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
index 9d08aeee19061..631eca5cd32db 100644
--- a/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
+++ b/mlir/lib/Conversion/GPUCommon/OpToFuncCallLowering.h
@@ -57,7 +57,8 @@ struct OpToFuncCallLowering : public ConvertOpToLLVMPattern<SourceOp> {
     LLVMType resultType =
         castedOperands.front().getType().cast<LLVM::LLVMType>();
     LLVMType funcType = getFunctionType(resultType, castedOperands);
-    StringRef funcName = getFunctionName(funcType.getFunctionResultType());
+    StringRef funcName = getFunctionName(
+        funcType.cast<LLVM::LLVMFunctionType>().getReturnType());
     if (funcName.empty())
       return failure();
 
@@ -80,11 +81,11 @@ struct OpToFuncCallLowering : public ConvertOpToLLVMPattern<SourceOp> {
 private:
   Value maybeCast(Value operand, PatternRewriter &rewriter) const {
     LLVM::LLVMType type = operand.getType().cast<LLVM::LLVMType>();
-    if (!type.isHalfTy())
+    if (!type.isa<LLVM::LLVMHalfType>())
       return operand;
 
     return rewriter.create<LLVM::FPExtOp>(
-        operand.getLoc(), LLVM::LLVMType::getFloatTy(rewriter.getContext()),
+        operand.getLoc(), LLVM::LLVMFloatType::get(rewriter.getContext()),
         operand);
   }
 
@@ -95,14 +96,13 @@ struct OpToFuncCallLowering : public ConvertOpToLLVMPattern<SourceOp> {
     for (Value operand : operands) {
       operandTypes.push_back(operand.getType().cast<LLVMType>());
     }
-    return LLVMType::getFunctionTy(resultType, operandTypes,
-                                   /*isVarArg=*/false);
+    return LLVM::LLVMFunctionType::get(resultType, operandTypes);
   }
 
   StringRef getFunctionName(LLVM::LLVMType type) const {
-    if (type.isFloatTy())
+    if (type.isa<LLVM::LLVMFloatType>())
       return f32Func;
-    if (type.isDoubleTy())
+    if (type.isa<LLVM::LLVMDoubleType>())
       return f64Func;
     return "";
   }
diff --git a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
index cea1cdc7e25fc..f747f519c66b6 100644
--- a/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
+++ b/mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp
@@ -57,10 +57,10 @@ struct GPUShuffleOpLowering : public ConvertOpToLLVMPattern<gpu::ShuffleOp> {
     gpu::ShuffleOpAdaptor adaptor(operands);
 
     auto valueTy = adaptor.value().getType().cast<LLVM::LLVMType>();
-    auto int32Type = LLVM::LLVMType::getInt32Ty(rewriter.getContext());
-    auto predTy = LLVM::LLVMType::getInt1Ty(rewriter.getContext());
-    auto resultTy =
-        LLVM::LLVMType::getStructTy(rewriter.getContext(), {valueTy, predTy});
+    auto int32Type = LLVM::LLVMIntegerType::get(rewriter.getContext(), 32);
+    auto predTy = LLVM::LLVMIntegerType::get(rewriter.getContext(), 1);
+    auto resultTy = LLVM::LLVMStructType::getLiteral(rewriter.getContext(),
+                                                     {valueTy, predTy});
 
     Value one = rewriter.create<LLVM::ConstantOp>(
         loc, int32Type, rewriter.getI32IntegerAttr(1));
diff --git a/mlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt b/mlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt
index fba29cf5f3426..01fa3e1448437 100644
--- a/mlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt
+++ b/mlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt
@@ -2,9 +2,9 @@ set(LLVM_TARGET_DEFINITIONS GPUToSPIRV.td)
 mlir_tablegen(GPUToSPIRV.cpp.inc -gen-rewriters)
 add_public_tablegen_target(MLIRGPUToSPIRVIncGen)
 
-add_mlir_conversion_library(MLIRGPUToSPIRVTransforms
-  ConvertGPUToSPIRV.cpp
-  ConvertGPUToSPIRVPass.cpp
+add_mlir_conversion_library(MLIRGPUToSPIRV
+  GPUToSPIRV.cpp
+  GPUToSPIRVPass.cpp
 
   DEPENDS
   MLIRConversionPassIncGen
@@ -18,7 +18,7 @@ add_mlir_conversion_library(MLIRGPUToSPIRVTransforms
   MLIRSPIRV
   MLIRSPIRVConversion
   MLIRStandard
-  MLIRStandardToSPIRVTransforms
+  MLIRStandardToSPIRV
   MLIRSupport
   MLIRTransforms
   )
diff --git a/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp b/mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
similarity index 98%
rename from mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
rename to mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
index 259acd7a9ce72..e84269e9418db 100644
--- a/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp
+++ b/mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRV.cpp
@@ -1,4 +1,4 @@
-//===- ConvertGPUToSPIRV.cpp - Convert GPU ops to SPIR-V dialect ----------===//
+//===- GPUToSPIRV.cpp - GPU to SPIR-V Patterns ----------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,10 +6,11 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the conversion patterns from GPU ops to SPIR-V dialect.
+// This file implements patterns to convert GPU dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
-#include "mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.h"
+
+#include "mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h"
 #include "mlir/Dialect/GPU/GPUDialect.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
diff --git a/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.cpp b/mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp
similarity index 83%
rename from mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.cpp
rename to mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp
index 973aa3d79bd85..8edb42e9a0f63 100644
--- a/mlir/lib/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.cpp
+++ b/mlir/lib/Conversion/GPUToSPIRV/GPUToSPIRVPass.cpp
@@ -1,4 +1,4 @@
-//===- ConvertGPUToSPIRVPass.cpp - GPU to SPIR-V dialect lowering passes --===//
+//===- GPUToSPIRVPass.cpp - GPU to SPIR-V Passes --------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -7,17 +7,16 @@
 //===----------------------------------------------------------------------===//
 //
 // This file implements a pass to convert a kernel function in the GPU Dialect
-// into a spv.module operation
+// into a spv.module operation.
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h"
+#include "mlir/Conversion/GPUToSPIRV/GPUToSPIRVPass.h"
+
 #include "../PassDetail.h"
-#include "mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRV.h"
-#include "mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h"
-#include "mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.h"
+#include "mlir/Conversion/GPUToSPIRV/GPUToSPIRV.h"
+#include "mlir/Conversion/StandardToSPIRV/StandardToSPIRV.h"
 #include "mlir/Dialect/GPU/GPUDialect.h"
-#include "mlir/Dialect/SCF/SCF.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
 #include "mlir/Dialect/SPIRV/Transforms/SPIRVConversion.h"
@@ -58,10 +57,8 @@ void GPUToSPIRVPass::runOnOperation() {
       spirv::SPIRVConversionTarget::get(targetAttr);
 
   SPIRVTypeConverter typeConverter(targetAttr);
-  ScfToSPIRVContext scfContext;
   OwningRewritePatternList patterns;
   populateGPUToSPIRVPatterns(context, typeConverter, patterns);
-  populateSCFToSPIRVPatterns(context, typeConverter,scfContext, patterns);
   populateStandardToSPIRVPatterns(context, typeConverter, patterns);
 
   if (failed(applyFullConversion(kernelModules, *target, std::move(patterns))))
diff --git a/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp b/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
index 355bced96ae75..4b657d25f51e3 100644
--- a/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
+++ b/mlir/lib/Conversion/GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp
@@ -57,11 +57,12 @@ class VulkanLaunchFuncToVulkanCallsPass
           VulkanLaunchFuncToVulkanCallsPass> {
 private:
   void initializeCachedTypes() {
-    llvmFloatType = LLVM::LLVMType::getFloatTy(&getContext());
-    llvmVoidType = LLVM::LLVMType::getVoidTy(&getContext());
-    llvmPointerType = LLVM::LLVMType::getInt8PtrTy(&getContext());
-    llvmInt32Type = LLVM::LLVMType::getInt32Ty(&getContext());
-    llvmInt64Type = LLVM::LLVMType::getInt64Ty(&getContext());
+    llvmFloatType = LLVM::LLVMFloatType::get(&getContext());
+    llvmVoidType = LLVM::LLVMVoidType::get(&getContext());
+    llvmPointerType = LLVM::LLVMPointerType::get(
+        LLVM::LLVMIntegerType::get(&getContext(), 8));
+    llvmInt32Type = LLVM::LLVMIntegerType::get(&getContext(), 32);
+    llvmInt64Type = LLVM::LLVMIntegerType::get(&getContext(), 64);
   }
 
   LLVM::LLVMType getMemRefType(uint32_t rank, LLVM::LLVMType elemenType) {
@@ -75,14 +76,14 @@ class VulkanLaunchFuncToVulkanCallsPass
     //   int64_t sizes[Rank]; // omitted when rank == 0
     //   int64_t strides[Rank]; // omitted when rank == 0
     // };
-    auto llvmPtrToElementType = elemenType.getPointerTo();
+    auto llvmPtrToElementType = LLVM::LLVMPointerType::get(elemenType);
     auto llvmArrayRankElementSizeType =
-        LLVM::LLVMType::getArrayTy(getInt64Type(), rank);
+        LLVM::LLVMArrayType::get(getInt64Type(), rank);
 
     // Create a type
     // `!llvm<"{ `element-type`*, `element-type`*, i64,
     // [`rank` x i64], [`rank` x i64]}">`.
-    return LLVM::LLVMType::getStructTy(
+    return LLVM::LLVMStructType::getLiteral(
         &getContext(),
         {llvmPtrToElementType, llvmPtrToElementType, getInt64Type(),
          llvmArrayRankElementSizeType, llvmArrayRankElementSizeType});
@@ -131,16 +132,18 @@ class VulkanLaunchFuncToVulkanCallsPass
 
   /// Returns a string representation from the given `type`.
   StringRef stringifyType(LLVM::LLVMType type) {
-    if (type.isFloatTy())
+    if (type.isa<LLVM::LLVMFloatType>())
       return "Float";
-    if (type.isHalfTy())
+    if (type.isa<LLVM::LLVMHalfType>())
       return "Half";
-    if (type.isIntegerTy(32))
-      return "Int32";
-    if (type.isIntegerTy(16))
-      return "Int16";
-    if (type.isIntegerTy(8))
-      return "Int8";
+    if (auto intType = type.dyn_cast<LLVM::LLVMIntegerType>()) {
+      if (intType.getBitWidth() == 32)
+        return "Int32";
+      if (intType.getBitWidth() == 16)
+        return "Int16";
+      if (intType.getBitWidth() == 8)
+        return "Int8";
+    }
 
     llvm_unreachable("unsupported type");
   }
@@ -238,11 +241,11 @@ void VulkanLaunchFuncToVulkanCallsPass::createBindMemRefCalls(
         llvm::formatv("bindMemRef{0}D{1}", rank, stringifyType(type)).str();
     // Special case for fp16 type. Since it is not a supported type in C we use
     // int16_t and bitcast the descriptor.
-    if (type.isHalfTy()) {
+    if (type.isa<LLVM::LLVMHalfType>()) {
       auto memRefTy =
-          getMemRefType(rank, LLVM::LLVMType::getInt16Ty(&getContext()));
+          getMemRefType(rank, LLVM::LLVMIntegerType::get(&getContext(), 16));
       ptrToMemRefDescriptor = builder.create<LLVM::BitcastOp>(
-          loc, memRefTy.getPointerTo(), ptrToMemRefDescriptor);
+          loc, LLVM::LLVMPointerType::get(memRefTy), ptrToMemRefDescriptor);
     }
     // Create call to `bindMemRef`.
     builder.create<LLVM::CallOp>(
@@ -257,11 +260,12 @@ void VulkanLaunchFuncToVulkanCallsPass::createBindMemRefCalls(
 LogicalResult VulkanLaunchFuncToVulkanCallsPass::deduceMemRefRankAndType(
     Value ptrToMemRefDescriptor, uint32_t &rank, LLVM::LLVMType &type) {
   auto llvmPtrDescriptorTy =
-      ptrToMemRefDescriptor.getType().dyn_cast<LLVM::LLVMType>();
+      ptrToMemRefDescriptor.getType().dyn_cast<LLVM::LLVMPointerType>();
   if (!llvmPtrDescriptorTy)
     return failure();
 
-  auto llvmDescriptorTy = llvmPtrDescriptorTy.getPointerElementTy();
+  auto llvmDescriptorTy =
+      llvmPtrDescriptorTy.getElementType().dyn_cast<LLVM::LLVMStructType>();
   // template <typename Elem, size_t Rank>
   // struct {
   //   Elem *allocated;
@@ -270,15 +274,19 @@ LogicalResult VulkanLaunchFuncToVulkanCallsPass::deduceMemRefRankAndType(
   //   int64_t sizes[Rank]; // omitted when rank == 0
   //   int64_t strides[Rank]; // omitted when rank == 0
   // };
-  if (!llvmDescriptorTy || !llvmDescriptorTy.isStructTy())
+  if (!llvmDescriptorTy)
     return failure();
 
-  type = llvmDescriptorTy.getStructElementType(0).getPointerElementTy();
-  if (llvmDescriptorTy.getStructNumElements() == 3) {
+  type = llvmDescriptorTy.getBody()[0]
+             .cast<LLVM::LLVMPointerType>()
+             .getElementType();
+  if (llvmDescriptorTy.getBody().size() == 3) {
     rank = 0;
     return success();
   }
-  rank = llvmDescriptorTy.getStructElementType(3).getArrayNumElements();
+  rank = llvmDescriptorTy.getBody()[3]
+             .cast<LLVM::LLVMArrayType>()
+             .getNumElements();
   return success();
 }
 
@@ -289,50 +297,49 @@ void VulkanLaunchFuncToVulkanCallsPass::declareVulkanFunctions(Location loc) {
   if (!module.lookupSymbol(kSetEntryPoint)) {
     builder.create<LLVM::LLVMFuncOp>(
         loc, kSetEntryPoint,
-        LLVM::LLVMType::getFunctionTy(getVoidType(),
-                                      {getPointerType(), getPointerType()},
-                                      /*isVarArg=*/false));
+        LLVM::LLVMFunctionType::get(getVoidType(),
+                                    {getPointerType(), getPointerType()}));
   }
 
   if (!module.lookupSymbol(kSetNumWorkGroups)) {
     builder.create<LLVM::LLVMFuncOp>(
         loc, kSetNumWorkGroups,
-        LLVM::LLVMType::getFunctionTy(
-            getVoidType(),
-            {getPointerType(), getInt64Type(), getInt64Type(), getInt64Type()},
-            /*isVarArg=*/false));
+        LLVM::LLVMFunctionType::get(getVoidType(),
+                                    {getPointerType(), getInt64Type(),
+                                     getInt64Type(), getInt64Type()}));
   }
 
   if (!module.lookupSymbol(kSetBinaryShader)) {
     builder.create<LLVM::LLVMFuncOp>(
         loc, kSetBinaryShader,
-        LLVM::LLVMType::getFunctionTy(
-            getVoidType(), {getPointerType(), getPointerType(), getInt32Type()},
-            /*isVarArg=*/false));
+        LLVM::LLVMFunctionType::get(
+            getVoidType(),
+            {getPointerType(), getPointerType(), getInt32Type()}));
   }
 
   if (!module.lookupSymbol(kRunOnVulkan)) {
     builder.create<LLVM::LLVMFuncOp>(
         loc, kRunOnVulkan,
-        LLVM::LLVMType::getFunctionTy(getVoidType(), {getPointerType()},
-                                      /*isVarArg=*/false));
+        LLVM::LLVMFunctionType::get(getVoidType(), {getPointerType()}));
   }
 
   for (unsigned i = 1; i <= 3; i++) {
-    for (LLVM::LLVMType type : {LLVM::LLVMType::getFloatTy(&getContext()),
-                                LLVM::LLVMType::getInt32Ty(&getContext()),
-                                LLVM::LLVMType::getInt16Ty(&getContext()),
-                                LLVM::LLVMType::getInt8Ty(&getContext()),
-                                LLVM::LLVMType::getHalfTy(&getContext())}) {
+    SmallVector<LLVM::LLVMType, 5> types{
+        LLVM::LLVMFloatType::get(&getContext()),
+        LLVM::LLVMIntegerType::get(&getContext(), 32),
+        LLVM::LLVMIntegerType::get(&getContext(), 16),
+        LLVM::LLVMIntegerType::get(&getContext(), 8),
+        LLVM::LLVMHalfType::get(&getContext())};
+    for (auto type : types) {
       std::string fnName = "bindMemRef" + std::to_string(i) + "D" +
                            std::string(stringifyType(type));
-      if (type.isHalfTy())
-        type = LLVM::LLVMType::getInt16Ty(&getContext());
+      if (type.isa<LLVM::LLVMHalfType>())
+        type = LLVM::LLVMIntegerType::get(&getContext(), 16);
       if (!module.lookupSymbol(fnName)) {
-        auto fnType = LLVM::LLVMType::getFunctionTy(
+        auto fnType = LLVM::LLVMFunctionType::get(
             getVoidType(),
             {getPointerType(), getInt32Type(), getInt32Type(),
-             getMemRefType(i, type).getPointerTo()},
+             LLVM::LLVMPointerType::get(getMemRefType(i, type))},
             /*isVarArg=*/false);
         builder.create<LLVM::LLVMFuncOp>(loc, fnName, fnType);
       }
@@ -341,16 +348,13 @@ void VulkanLaunchFuncToVulkanCallsPass::declareVulkanFunctions(Location loc) {
 
   if (!module.lookupSymbol(kInitVulkan)) {
     builder.create<LLVM::LLVMFuncOp>(
-        loc, kInitVulkan,
-        LLVM::LLVMType::getFunctionTy(getPointerType(), {},
-                                      /*isVarArg=*/false));
+        loc, kInitVulkan, LLVM::LLVMFunctionType::get(getPointerType(), {}));
   }
 
   if (!module.lookupSymbol(kDeinitVulkan)) {
     builder.create<LLVM::LLVMFuncOp>(
         loc, kDeinitVulkan,
-        LLVM::LLVMType::getFunctionTy(getVoidType(), {getPointerType()},
-                                      /*isVarArg=*/false));
+        LLVM::LLVMFunctionType::get(getVoidType(), {getPointerType()}));
   }
 }
 
diff --git a/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp b/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
index 5546c82a9e699..c86ae710aac63 100644
--- a/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
+++ b/mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp
@@ -86,7 +86,7 @@ static Type convertRangeType(RangeType t, LLVMTypeConverter &converter) {
   auto *context = t.getContext();
   auto int64Ty = converter.convertType(IntegerType::get(context, 64))
                      .cast<LLVM::LLVMType>();
-  return LLVMType::getStructTy(int64Ty, int64Ty, int64Ty);
+  return LLVMStructType::getLiteral(context, {int64Ty, int64Ty, int64Ty});
 }
 
 namespace {
diff --git a/mlir/lib/Conversion/LinalgToSPIRV/CMakeLists.txt b/mlir/lib/Conversion/LinalgToSPIRV/CMakeLists.txt
index a40abba0351f2..27f7febd70065 100644
--- a/mlir/lib/Conversion/LinalgToSPIRV/CMakeLists.txt
+++ b/mlir/lib/Conversion/LinalgToSPIRV/CMakeLists.txt
@@ -1,4 +1,4 @@
-add_mlir_conversion_library(MLIRLinalgToSPIRVTransforms
+add_mlir_conversion_library(MLIRLinalgToSPIRV
   LinalgToSPIRV.cpp
   LinalgToSPIRVPass.cpp
 
diff --git a/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp b/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp
index 0e09d9596a62f..8133a37aa7ad4 100644
--- a/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp
+++ b/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp
@@ -1,4 +1,4 @@
-//===- LinalgToSPIRV.cpp - Linalg to SPIR-V dialect conversion ------------===//
+//===- LinalgToSPIRV.cpp - Linalg to SPIR-V Patterns ----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
diff --git a/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp b/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp
index 1ce2f41f46b88..ddcc97d359ca9 100644
--- a/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp
+++ b/mlir/lib/Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp
@@ -1,4 +1,4 @@
-//===- LinalgToSPIRVPass.cpp - Linalg to SPIR-V conversion pass -----------===//
+//===- LinalgToSPIRVPass.cpp - Linalg to SPIR-V Passes --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
diff --git a/mlir/lib/Conversion/SCFToSPIRV/CMakeLists.txt b/mlir/lib/Conversion/SCFToSPIRV/CMakeLists.txt
index d77a759d5f384..5361fc742431c 100644
--- a/mlir/lib/Conversion/SCFToSPIRV/CMakeLists.txt
+++ b/mlir/lib/Conversion/SCFToSPIRV/CMakeLists.txt
@@ -1,5 +1,6 @@
 add_mlir_conversion_library(MLIRSCFToSPIRV
   SCFToSPIRV.cpp
+  SCFToSPIRVPass.cpp
 
   ADDITIONAL_HEADER_DIRS
   ${MLIR_MAIN_INCLUDE_DIR}/mlir/Conversion/SCFToSPIRV
@@ -8,12 +9,10 @@ add_mlir_conversion_library(MLIRSCFToSPIRV
   MLIRConversionPassIncGen
 
   LINK_LIBS PUBLIC
-  MLIRAffine
-  MLIRAffineToStandard
   MLIRSPIRV
   MLIRSPIRVConversion
+  MLIRStandardToSPIRV
   MLIRIR
-  MLIRLinalg
   MLIRPass
   MLIRStandard
   MLIRSupport
diff --git a/mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp b/mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp
index 576f38fba8191..da2488db1182f 100644
--- a/mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp
+++ b/mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp
@@ -1,4 +1,4 @@
-//===- SCFToSPIRV.cpp - Convert SCF ops to SPIR-V dialect -----------------===//
+//===- SCFToSPIRV.cpp - SCF to SPIR-V Patterns ----------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,9 +6,10 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the conversion patterns from SCF ops to SPIR-V dialect.
+// This file implements patterns to convert SCF dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
+
 #include "mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h"
 #include "mlir/Dialect/SCF/SCF.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
diff --git a/mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRVPass.cpp b/mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRVPass.cpp
new file mode 100644
index 0000000000000..b0d879974a56a
--- /dev/null
+++ b/mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRVPass.cpp
@@ -0,0 +1,51 @@
+//===- SCFToSPIRVPass.cpp - SCF to SPIR-V Passes --------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a pass to convert SCF dialect into SPIR-V dialect.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Conversion/SCFToSPIRV/SCFToSPIRVPass.h"
+
+#include "../PassDetail.h"
+#include "mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h"
+#include "mlir/Conversion/StandardToSPIRV/StandardToSPIRV.h"
+#include "mlir/Dialect/SCF/SCF.h"
+#include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
+#include "mlir/Dialect/SPIRV/Transforms/SPIRVConversion.h"
+
+using namespace mlir;
+
+namespace {
+struct SCFToSPIRVPass : public SCFToSPIRVBase<SCFToSPIRVPass> {
+  void runOnOperation() override;
+};
+} // namespace
+
+void SCFToSPIRVPass::runOnOperation() {
+  MLIRContext *context = &getContext();
+  ModuleOp module = getOperation();
+
+  auto targetAttr = spirv::lookupTargetEnvOrDefault(module);
+  std::unique_ptr<ConversionTarget> target =
+      spirv::SPIRVConversionTarget::get(targetAttr);
+
+  SPIRVTypeConverter typeConverter(targetAttr);
+  ScfToSPIRVContext scfContext;
+  OwningRewritePatternList patterns;
+  populateSCFToSPIRVPatterns(context, typeConverter, scfContext, patterns);
+  populateStandardToSPIRVPatterns(context, typeConverter, patterns);
+  populateBuiltinFuncToSPIRVPatterns(context, typeConverter, patterns);
+
+  if (failed(applyPartialConversion(module, *target, std::move(patterns))))
+    return signalPassFailure();
+}
+
+std::unique_ptr<OperationPass<ModuleOp>> mlir::createConvertSCFToSPIRVPass() {
+  return std::make_unique<SCFToSPIRVPass>();
+}
diff --git a/mlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt b/mlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt
index 8d3cbc6c7c337..f57e42cff29e9 100644
--- a/mlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt
+++ b/mlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt
@@ -1,7 +1,7 @@
 add_mlir_conversion_library(MLIRSPIRVToLLVM
   ConvertLaunchFuncToLLVMCalls.cpp
-  ConvertSPIRVToLLVM.cpp
-  ConvertSPIRVToLLVMPass.cpp
+  SPIRVToLLVM.cpp
+  SPIRVToLLVMPass.cpp
 
   ADDITIONAL_HEADER_DIRS
   ${MLIR_MAIN_INCLUDE_DIR}/mlir/Conversion/SPIRVToLLVM
diff --git a/mlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp b/mlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
index 1724c7044339d..c293dacf8ec53 100644
--- a/mlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
+++ b/mlir/lib/Conversion/SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp
@@ -12,8 +12,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "../PassDetail.h"
-#include "mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h"
-#include "mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h"
+#include "mlir/Conversion/SPIRVToLLVM/SPIRVToLLVM.h"
+#include "mlir/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
 #include "mlir/Dialect/GPU/GPUDialect.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
@@ -60,7 +60,7 @@ static unsigned calculateGlobalIndex(spirv::GlobalVariableOp op) {
 static void copy(Location loc, Value dst, Value src, Value size,
                  OpBuilder &builder) {
   MLIRContext *context = builder.getContext();
-  auto llvmI1Type = LLVM::LLVMType::getInt1Ty(context);
+  auto llvmI1Type = LLVM::LLVMIntegerType::get(context, 1);
   Value isVolatile = builder.create<LLVM::ConstantOp>(
       loc, llvmI1Type, builder.getBoolAttr(false));
   builder.create<LLVM::MemcpyOp>(loc, dst, src, size, isVolatile);
@@ -183,9 +183,8 @@ class GPULaunchLowering : public ConvertOpToLLVMPattern<gpu::LaunchFuncOp> {
       rewriter.setInsertionPointToStart(module.getBody());
       kernelFunc = rewriter.create<LLVM::LLVMFuncOp>(
           rewriter.getUnknownLoc(), newKernelFuncName,
-          LLVM::LLVMType::getFunctionTy(LLVM::LLVMType::getVoidTy(context),
-                                        ArrayRef<LLVM::LLVMType>(),
-                                        /*isVarArg=*/false));
+          LLVM::LLVMFunctionType::get(LLVM::LLVMVoidType::get(context),
+                                      ArrayRef<LLVM::LLVMType>()));
       rewriter.setInsertionPoint(launchOp);
     }
 
diff --git a/mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp b/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
similarity index 98%
rename from mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp
rename to mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
index cacb4787edd4e..76a4e0b2e07ef 100644
--- a/mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.cpp
+++ b/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
@@ -1,4 +1,4 @@
-//===- ConvertSPIRVToLLVM.cpp - SPIR-V dialect to LLVM dialect conversion -===//
+//===- SPIRVToLLVM.cpp - SPIR-V to LLVM Patterns --------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -10,7 +10,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h"
+#include "mlir/Conversion/SPIRVToLLVM/SPIRVToLLVM.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
@@ -66,8 +66,10 @@ static unsigned getBitWidth(Type type) {
 
 /// Returns the bit width of LLVMType integer or vector.
 static unsigned getLLVMTypeBitWidth(LLVM::LLVMType type) {
-  return type.isVectorTy() ? type.getVectorElementType().getIntegerBitWidth()
-                           : type.getIntegerBitWidth();
+  auto vectorType = type.dyn_cast<LLVM::LLVMVectorType>();
+  return (vectorType ? vectorType.getElementType() : type)
+      .cast<LLVM::LLVMIntegerType>()
+      .getBitWidth();
 }
 
 /// Creates `IntegerAttribute` with all bits set for given type
@@ -193,8 +195,8 @@ convertStructTypeWithOffset(spirv::StructType type,
       llvm::map_range(type.getElementTypes(), [&](Type elementType) {
         return converter.convertType(elementType).cast<LLVM::LLVMType>();
       }));
-  return LLVM::LLVMType::getStructTy(type.getContext(), elementsVector,
-                                     /*isPacked=*/false);
+  return LLVM::LLVMStructType::getLiteral(type.getContext(), elementsVector,
+                                          /*isPacked=*/false);
 }
 
 /// Converts SPIR-V struct with no offset to packed LLVM struct.
@@ -204,15 +206,15 @@ static Type convertStructTypePacked(spirv::StructType type,
       llvm::map_range(type.getElementTypes(), [&](Type elementType) {
         return converter.convertType(elementType).cast<LLVM::LLVMType>();
       }));
-  return LLVM::LLVMType::getStructTy(type.getContext(), elementsVector,
-                                     /*isPacked=*/true);
+  return LLVM::LLVMStructType::getLiteral(type.getContext(), elementsVector,
+                                          /*isPacked=*/true);
 }
 
 /// Creates LLVM dialect constant with the given value.
 static Value createI32ConstantOf(Location loc, PatternRewriter &rewriter,
                                  unsigned value) {
   return rewriter.create<LLVM::ConstantOp>(
-      loc, LLVM::LLVMType::getInt32Ty(rewriter.getContext()),
+      loc, LLVM::LLVMIntegerType::get(rewriter.getContext(), 32),
       rewriter.getIntegerAttr(rewriter.getI32Type(), value));
 }
 
@@ -256,7 +258,7 @@ static Optional<Type> convertArrayType(spirv::ArrayType type,
   auto llvmElementType =
       converter.convertType(elementType).cast<LLVM::LLVMType>();
   unsigned numElements = type.getNumElements();
-  return LLVM::LLVMType::getArrayTy(llvmElementType, numElements);
+  return LLVM::LLVMArrayType::get(llvmElementType, numElements);
 }
 
 /// Converts SPIR-V pointer type to LLVM pointer. Pointer's storage class is not
@@ -265,7 +267,7 @@ static Type convertPointerType(spirv::PointerType type,
                                TypeConverter &converter) {
   auto pointeeType =
       converter.convertType(type.getPointeeType()).cast<LLVM::LLVMType>();
-  return pointeeType.getPointerTo();
+  return LLVM::LLVMPointerType::get(pointeeType);
 }
 
 /// Converts SPIR-V runtime array to LLVM array. Since LLVM allows indexing over
@@ -277,7 +279,7 @@ static Optional<Type> convertRuntimeArrayType(spirv::RuntimeArrayType type,
     return llvm::None;
   auto elementType =
       converter.convertType(type.getElementType()).cast<LLVM::LLVMType>();
-  return LLVM::LLVMType::getArrayTy(elementType, 0);
+  return LLVM::LLVMArrayType::get(elementType, 0);
 }
 
 /// Converts SPIR-V struct to LLVM struct. There is no support of structs with
@@ -664,15 +666,15 @@ class ExecutionModePattern
     //   int32_t executionMode;
     //   int32_t values[];          // optional values
     // };
-    auto llvmI32Type = LLVM::LLVMType::getInt32Ty(context);
+    auto llvmI32Type = LLVM::LLVMIntegerType::get(context, 32);
     SmallVector<LLVM::LLVMType, 2> fields;
     fields.push_back(llvmI32Type);
     ArrayAttr values = op.values();
     if (!values.empty()) {
-      auto arrayType = LLVM::LLVMType::getArrayTy(llvmI32Type, values.size());
+      auto arrayType = LLVM::LLVMArrayType::get(llvmI32Type, values.size());
       fields.push_back(arrayType);
     }
-    auto structType = LLVM::LLVMType::getStructTy(context, fields);
+    auto structType = LLVM::LLVMStructType::getLiteral(context, fields);
 
     // Create `llvm.mlir.global` with initializer region containing one block.
     auto global = rewriter.create<LLVM::GlobalOp>(
@@ -892,7 +894,7 @@ class LoadStorePattern : public SPIRVToLLVMConversion<SPIRVop> {
 
     if (!op.memory_access().hasValue()) {
       replaceWithLoadOrStore(op, rewriter, this->typeConverter, /*alignment=*/0,
-                             /*isVolatile=*/false, /*isNonTemporal=*/ false);
+                             /*isVolatile=*/false, /*isNonTemporal=*/false);
       return success();
     }
     auto memoryAccess = op.memory_access().getValue();
diff --git a/mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.cpp b/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.cpp
similarity index 91%
rename from mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.cpp
rename to mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.cpp
index b93ce48cb8042..2a4113f307fa8 100644
--- a/mlir/lib/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.cpp
+++ b/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.cpp
@@ -1,4 +1,4 @@
-//===- ConvertSPIRVToLLVMPass.cpp - Convert SPIR-V ops to LLVM ops --------===//
+//===- SPIRVToLLVMPass.cpp - SPIR-V to LLVM Passes ------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -10,9 +10,9 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h"
+#include "mlir/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.h"
 #include "../PassDetail.h"
-#include "mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVM.h"
+#include "mlir/Conversion/SPIRVToLLVM/SPIRVToLLVM.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
diff --git a/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp b/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
index 6fbcc220a86b0..233c2eadc77c1 100644
--- a/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
+++ b/mlir/lib/Conversion/StandardToLLVM/StandardToLLVM.cpp
@@ -171,7 +171,7 @@ MLIRContext &LLVMTypeConverter::getContext() {
 }
 
 LLVM::LLVMType LLVMTypeConverter::getIndexType() {
-  return LLVM::LLVMType::getIntNTy(&getContext(), getIndexTypeBitwidth());
+  return LLVM::LLVMIntegerType::get(&getContext(), getIndexTypeBitwidth());
 }
 
 unsigned LLVMTypeConverter::getPointerBitwidth(unsigned addressSpace) {
@@ -183,18 +183,18 @@ Type LLVMTypeConverter::convertIndexType(IndexType type) {
 }
 
 Type LLVMTypeConverter::convertIntegerType(IntegerType type) {
-  return LLVM::LLVMType::getIntNTy(&getContext(), type.getWidth());
+  return LLVM::LLVMIntegerType::get(&getContext(), type.getWidth());
 }
 
 Type LLVMTypeConverter::convertFloatType(FloatType type) {
   if (type.isa<Float32Type>())
-    return LLVM::LLVMType::getFloatTy(&getContext());
+    return LLVM::LLVMFloatType::get(&getContext());
   if (type.isa<Float64Type>())
-    return LLVM::LLVMType::getDoubleTy(&getContext());
+    return LLVM::LLVMDoubleType::get(&getContext());
   if (type.isa<Float16Type>())
-    return LLVM::LLVMType::getHalfTy(&getContext());
+    return LLVM::LLVMHalfType::get(&getContext());
   if (type.isa<BFloat16Type>())
-    return LLVM::LLVMType::getBFloatTy(&getContext());
+    return LLVM::LLVMBFloatType::get(&getContext());
   llvm_unreachable("non-float type in convertFloatType");
 }
 
@@ -206,7 +206,8 @@ static constexpr unsigned kRealPosInComplexNumberStruct = 0;
 static constexpr unsigned kImaginaryPosInComplexNumberStruct = 1;
 Type LLVMTypeConverter::convertComplexType(ComplexType type) {
   auto elementType = convertType(type.getElementType()).cast<LLVM::LLVMType>();
-  return LLVM::LLVMType::getStructTy(&getContext(), {elementType, elementType});
+  return LLVM::LLVMStructType::getLiteral(&getContext(),
+                                          {elementType, elementType});
 }
 
 // Except for signatures, MLIR function types are converted into LLVM
@@ -215,7 +216,7 @@ Type LLVMTypeConverter::convertFunctionType(FunctionType type) {
   SignatureConversion conversion(type.getNumInputs());
   LLVM::LLVMType converted =
       convertFunctionSignature(type, /*isVariadic=*/false, conversion);
-  return converted.getPointerTo();
+  return LLVM::LLVMPointerType::get(converted);
 }
 
 
@@ -249,11 +250,11 @@ LLVM::LLVMType LLVMTypeConverter::convertFunctionSignature(
   // a struct.
   LLVM::LLVMType resultType =
       funcTy.getNumResults() == 0
-          ? LLVM::LLVMType::getVoidTy(&getContext())
+          ? LLVM::LLVMVoidType::get(&getContext())
           : unwrap(packFunctionResults(funcTy.getResults()));
   if (!resultType)
     return {};
-  return LLVM::LLVMType::getFunctionTy(resultType, argTypes, isVariadic);
+  return LLVM::LLVMFunctionType::get(resultType, argTypes, isVariadic);
 }
 
 /// Converts the function type to a C-compatible format, in particular using
@@ -267,18 +268,18 @@ LLVMTypeConverter::convertFunctionTypeCWrapper(FunctionType type) {
     if (!converted)
       return {};
     if (t.isa<MemRefType, UnrankedMemRefType>())
-      converted = converted.getPointerTo();
+      converted = LLVM::LLVMPointerType::get(converted);
     inputs.push_back(converted);
   }
 
   LLVM::LLVMType resultType =
       type.getNumResults() == 0
-          ? LLVM::LLVMType::getVoidTy(&getContext())
+          ? LLVM::LLVMVoidType::get(&getContext())
           : unwrap(packFunctionResults(type.getResults()));
   if (!resultType)
     return {};
 
-  return LLVM::LLVMType::getFunctionTy(resultType, inputs, false);
+  return LLVM::LLVMFunctionType::get(resultType, inputs);
 }
 
 static constexpr unsigned kAllocatedPtrPosInMemRefDescriptor = 0;
@@ -324,7 +325,7 @@ LLVMTypeConverter::getMemRefDescriptorFields(MemRefType type,
   LLVM::LLVMType elementType = unwrap(convertType(type.getElementType()));
   if (!elementType)
     return {};
-  auto ptrTy = elementType.getPointerTo(type.getMemorySpace());
+  auto ptrTy = LLVM::LLVMPointerType::get(elementType, type.getMemorySpace());
   auto indexTy = getIndexType();
 
   SmallVector<LLVM::LLVMType, 5> results = {ptrTy, ptrTy, indexTy};
@@ -335,7 +336,7 @@ LLVMTypeConverter::getMemRefDescriptorFields(MemRefType type,
   if (unpackAggregates)
     results.insert(results.end(), 2 * rank, indexTy);
   else
-    results.insert(results.end(), 2, LLVM::LLVMType::getArrayTy(indexTy, rank));
+    results.insert(results.end(), 2, LLVM::LLVMArrayType::get(indexTy, rank));
   return results;
 }
 
@@ -346,7 +347,7 @@ Type LLVMTypeConverter::convertMemRefType(MemRefType type) {
   // unpack the `sizes` and `strides` arrays.
   SmallVector<LLVM::LLVMType, 5> types =
       getMemRefDescriptorFields(type, /*unpackAggregates=*/false);
-  return LLVM::LLVMType::getStructTy(&getContext(), types);
+  return LLVM::LLVMStructType::getLiteral(&getContext(), types);
 }
 
 static constexpr unsigned kRankInUnrankedMemRefDescriptor = 0;
@@ -361,12 +362,13 @@ static constexpr unsigned kPtrInUnrankedMemRefDescriptor = 1;
 ///    be unranked.
 SmallVector<LLVM::LLVMType, 2>
 LLVMTypeConverter::getUnrankedMemRefDescriptorFields() {
-  return {getIndexType(), LLVM::LLVMType::getInt8PtrTy(&getContext())};
+  return {getIndexType(), LLVM::LLVMPointerType::get(
+                              LLVM::LLVMIntegerType::get(&getContext(), 8))};
 }
 
 Type LLVMTypeConverter::convertUnrankedMemRefType(UnrankedMemRefType type) {
-  return LLVM::LLVMType::getStructTy(&getContext(),
-                                     getUnrankedMemRefDescriptorFields());
+  return LLVM::LLVMStructType::getLiteral(&getContext(),
+                                          getUnrankedMemRefDescriptorFields());
 }
 
 /// Convert a memref type to a bare pointer to the memref element type.
@@ -396,7 +398,7 @@ Type LLVMTypeConverter::convertMemRefToBarePtr(BaseMemRefType type) {
   LLVM::LLVMType elementType = unwrap(convertType(type.getElementType()));
   if (!elementType)
     return {};
-  return elementType.getPointerTo(type.getMemorySpace());
+  return LLVM::LLVMPointerType::get(elementType, type.getMemorySpace());
 }
 
 // Convert an n-D vector type to an LLVM vector type via (n-1)-D array type when
@@ -407,11 +409,11 @@ Type LLVMTypeConverter::convertVectorType(VectorType type) {
   auto elementType = unwrap(convertType(type.getElementType()));
   if (!elementType)
     return {};
-  auto vectorType =
-      LLVM::LLVMType::getVectorTy(elementType, type.getShape().back());
+  LLVM::LLVMType vectorType =
+      LLVM::LLVMFixedVectorType::get(elementType, type.getShape().back());
   auto shape = type.getShape();
   for (int i = shape.size() - 2; i >= 0; --i)
-    vectorType = LLVM::LLVMType::getArrayTy(vectorType, shape[i]);
+    vectorType = LLVM::LLVMArrayType::get(vectorType, shape[i]);
   return vectorType;
 }
 
@@ -460,7 +462,7 @@ StructBuilder::StructBuilder(Value v) : value(v) {
 
 Value StructBuilder::extractPtr(OpBuilder &builder, Location loc,
                                 unsigned pos) {
-  Type type = structType.cast<LLVM::LLVMType>().getStructElementType(pos);
+  Type type = structType.cast<LLVM::LLVMStructType>().getBody()[pos];
   return builder.create<LLVM::ExtractValueOp>(loc, type, value,
                                               builder.getI64ArrayAttr(pos));
 }
@@ -507,8 +509,9 @@ Value ComplexStructBuilder::imaginary(OpBuilder &builder, Location loc) {
 MemRefDescriptor::MemRefDescriptor(Value descriptor)
     : StructBuilder(descriptor) {
   assert(value != nullptr && "value cannot be null");
-  indexType = value.getType().cast<LLVM::LLVMType>().getStructElementType(
-      kOffsetPosInMemRefDescriptor);
+  indexType = value.getType()
+                  .cast<LLVM::LLVMStructType>()
+                  .getBody()[kOffsetPosInMemRefDescriptor];
 }
 
 /// Builds IR creating an `undef` value of the descriptor type.
@@ -618,9 +621,9 @@ Value MemRefDescriptor::size(OpBuilder &builder, Location loc, unsigned pos) {
 Value MemRefDescriptor::size(OpBuilder &builder, Location loc, Value pos,
                              int64_t rank) {
   auto indexTy = indexType.cast<LLVM::LLVMType>();
-  auto indexPtrTy = indexTy.getPointerTo();
-  auto arrayTy = LLVM::LLVMType::getArrayTy(indexTy, rank);
-  auto arrayPtrTy = arrayTy.getPointerTo();
+  auto indexPtrTy = LLVM::LLVMPointerType::get(indexTy);
+  auto arrayTy = LLVM::LLVMArrayType::get(indexTy, rank);
+  auto arrayPtrTy = LLVM::LLVMPointerType::get(arrayTy);
 
   // Copy size values to stack-allocated memory.
   auto zero = createIndexAttrConstant(builder, loc, indexType, 0);
@@ -675,8 +678,8 @@ void MemRefDescriptor::setConstantStride(OpBuilder &builder, Location loc,
 
 LLVM::LLVMPointerType MemRefDescriptor::getElementPtrType() {
   return value.getType()
-      .cast<LLVM::LLVMType>()
-      .getStructElementType(kAlignedPtrPosInMemRefDescriptor)
+      .cast<LLVM::LLVMStructType>()
+      .getBody()[kAlignedPtrPosInMemRefDescriptor]
       .cast<LLVM::LLVMPointerType>();
 }
 
@@ -922,7 +925,7 @@ Value UnrankedMemRefDescriptor::offset(OpBuilder &builder, Location loc,
   Value offsetGep = builder.create<LLVM::GEPOp>(
       loc, elemPtrPtrType, elementPtrPtr, ValueRange({two}));
   offsetGep = builder.create<LLVM::BitcastOp>(
-      loc, typeConverter.getIndexType().getPointerTo(), offsetGep);
+      loc, LLVM::LLVMPointerType::get(typeConverter.getIndexType()), offsetGep);
   return builder.create<LLVM::LoadOp>(loc, offsetGep);
 }
 
@@ -939,19 +942,18 @@ void UnrankedMemRefDescriptor::setOffset(OpBuilder &builder, Location loc,
   Value offsetGep = builder.create<LLVM::GEPOp>(
       loc, elemPtrPtrType, elementPtrPtr, ValueRange({two}));
   offsetGep = builder.create<LLVM::BitcastOp>(
-      loc, typeConverter.getIndexType().getPointerTo(), offsetGep);
+      loc, LLVM::LLVMPointerType::get(typeConverter.getIndexType()), offsetGep);
   builder.create<LLVM::StoreOp>(loc, offset, offsetGep);
 }
 
-Value UnrankedMemRefDescriptor::sizeBasePtr(OpBuilder &builder, Location loc,
-                                            LLVMTypeConverter &typeConverter,
-                                            Value memRefDescPtr,
-                                            LLVM::LLVMType elemPtrPtrType) {
-  LLVM::LLVMType elemPtrTy = elemPtrPtrType.getPointerElementTy();
+Value UnrankedMemRefDescriptor::sizeBasePtr(
+    OpBuilder &builder, Location loc, LLVMTypeConverter &typeConverter,
+    Value memRefDescPtr, LLVM::LLVMPointerType elemPtrPtrType) {
+  LLVM::LLVMType elemPtrTy = elemPtrPtrType.getElementType();
   LLVM::LLVMType indexTy = typeConverter.getIndexType();
   LLVM::LLVMType structPtrTy =
-      LLVM::LLVMType::getStructTy(elemPtrTy, elemPtrTy, indexTy, indexTy)
-          .getPointerTo();
+      LLVM::LLVMPointerType::get(LLVM::LLVMStructType::getLiteral(
+          indexTy.getContext(), {elemPtrTy, elemPtrTy, indexTy, indexTy}));
   Value structPtr =
       builder.create<LLVM::BitcastOp>(loc, structPtrTy, memRefDescPtr);
 
@@ -961,14 +963,15 @@ Value UnrankedMemRefDescriptor::sizeBasePtr(OpBuilder &builder, Location loc,
       createIndexAttrConstant(builder, loc, typeConverter.getIndexType(), 0);
   Value three = builder.create<LLVM::ConstantOp>(loc, int32_type,
                                                  builder.getI32IntegerAttr(3));
-  return builder.create<LLVM::GEPOp>(loc, indexTy.getPointerTo(), structPtr,
-                                     ValueRange({zero, three}));
+  return builder.create<LLVM::GEPOp>(loc, LLVM::LLVMPointerType::get(indexTy),
+                                     structPtr, ValueRange({zero, three}));
 }
 
 Value UnrankedMemRefDescriptor::size(OpBuilder &builder, Location loc,
                                      LLVMTypeConverter typeConverter,
                                      Value sizeBasePtr, Value index) {
-  LLVM::LLVMType indexPtrTy = typeConverter.getIndexType().getPointerTo();
+  LLVM::LLVMType indexPtrTy =
+      LLVM::LLVMPointerType::get(typeConverter.getIndexType());
   Value sizeStoreGep = builder.create<LLVM::GEPOp>(loc, indexPtrTy, sizeBasePtr,
                                                    ValueRange({index}));
   return builder.create<LLVM::LoadOp>(loc, sizeStoreGep);
@@ -978,7 +981,8 @@ void UnrankedMemRefDescriptor::setSize(OpBuilder &builder, Location loc,
                                        LLVMTypeConverter typeConverter,
                                        Value sizeBasePtr, Value index,
                                        Value size) {
-  LLVM::LLVMType indexPtrTy = typeConverter.getIndexType().getPointerTo();
+  LLVM::LLVMType indexPtrTy =
+      LLVM::LLVMPointerType::get(typeConverter.getIndexType());
   Value sizeStoreGep = builder.create<LLVM::GEPOp>(loc, indexPtrTy, sizeBasePtr,
                                                    ValueRange({index}));
   builder.create<LLVM::StoreOp>(loc, size, sizeStoreGep);
@@ -987,7 +991,8 @@ void UnrankedMemRefDescriptor::setSize(OpBuilder &builder, Location loc,
 Value UnrankedMemRefDescriptor::strideBasePtr(OpBuilder &builder, Location loc,
                                               LLVMTypeConverter &typeConverter,
                                               Value sizeBasePtr, Value rank) {
-  LLVM::LLVMType indexPtrTy = typeConverter.getIndexType().getPointerTo();
+  LLVM::LLVMType indexPtrTy =
+      LLVM::LLVMPointerType::get(typeConverter.getIndexType());
   return builder.create<LLVM::GEPOp>(loc, indexPtrTy, sizeBasePtr,
                                      ValueRange({rank}));
 }
@@ -996,7 +1001,8 @@ Value UnrankedMemRefDescriptor::stride(OpBuilder &builder, Location loc,
                                        LLVMTypeConverter typeConverter,
                                        Value strideBasePtr, Value index,
                                        Value stride) {
-  LLVM::LLVMType indexPtrTy = typeConverter.getIndexType().getPointerTo();
+  LLVM::LLVMType indexPtrTy =
+      LLVM::LLVMPointerType::get(typeConverter.getIndexType());
   Value strideStoreGep = builder.create<LLVM::GEPOp>(
       loc, indexPtrTy, strideBasePtr, ValueRange({index}));
   return builder.create<LLVM::LoadOp>(loc, strideStoreGep);
@@ -1006,7 +1012,8 @@ void UnrankedMemRefDescriptor::setStride(OpBuilder &builder, Location loc,
                                          LLVMTypeConverter typeConverter,
                                          Value strideBasePtr, Value index,
                                          Value stride) {
-  LLVM::LLVMType indexPtrTy = typeConverter.getIndexType().getPointerTo();
+  LLVM::LLVMType indexPtrTy =
+      LLVM::LLVMPointerType::get(typeConverter.getIndexType());
   Value strideStoreGep = builder.create<LLVM::GEPOp>(
       loc, indexPtrTy, strideBasePtr, ValueRange({index}));
   builder.create<LLVM::StoreOp>(loc, stride, strideStoreGep);
@@ -1027,17 +1034,18 @@ LLVM::LLVMType ConvertToLLVMPattern::getIndexType() const {
 
 LLVM::LLVMType
 ConvertToLLVMPattern::getIntPtrType(unsigned addressSpace) const {
-  return LLVM::LLVMType::getIntNTy(
+  return LLVM::LLVMIntegerType::get(
       &getTypeConverter()->getContext(),
       getTypeConverter()->getPointerBitwidth(addressSpace));
 }
 
 LLVM::LLVMType ConvertToLLVMPattern::getVoidType() const {
-  return LLVM::LLVMType::getVoidTy(&getTypeConverter()->getContext());
+  return LLVM::LLVMVoidType::get(&getTypeConverter()->getContext());
 }
 
 LLVM::LLVMType ConvertToLLVMPattern::getVoidPtrType() const {
-  return LLVM::LLVMType::getInt8PtrTy(&getTypeConverter()->getContext());
+  return LLVM::LLVMPointerType::get(
+      LLVM::LLVMIntegerType::get(&getTypeConverter()->getContext(), 8));
 }
 
 Value ConvertToLLVMPattern::createIndexConstant(
@@ -1081,15 +1089,10 @@ Value ConvertToLLVMPattern::getStridedElementPtr(
                : base;
 }
 
-Value ConvertToLLVMPattern::getDataPtr(
-    Location loc, MemRefType type, Value memRefDesc, ValueRange indices,
-    ConversionPatternRewriter &rewriter) const {
-  return getStridedElementPtr(loc, type, memRefDesc, indices, rewriter);
-}
-
 // Check if the MemRefType `type` is supported by the lowering. We currently
 // only support memrefs with identity maps.
-bool ConvertToLLVMPattern::isSupportedMemRefType(MemRefType type) const {
+bool ConvertToLLVMPattern::isConvertibleAndHasIdentityMaps(
+    MemRefType type) const {
   if (!typeConverter->convertType(type.getElementType()))
     return false;
   return type.getAffineMaps().empty() ||
@@ -1100,14 +1103,14 @@ bool ConvertToLLVMPattern::isSupportedMemRefType(MemRefType type) const {
 Type ConvertToLLVMPattern::getElementPtrType(MemRefType type) const {
   auto elementType = type.getElementType();
   auto structElementType = unwrap(typeConverter->convertType(elementType));
-  return structElementType.getPointerTo(type.getMemorySpace());
+  return LLVM::LLVMPointerType::get(structElementType, type.getMemorySpace());
 }
 
 void ConvertToLLVMPattern::getMemRefDescriptorSizes(
     Location loc, MemRefType memRefType, ArrayRef<Value> dynamicSizes,
     ConversionPatternRewriter &rewriter, SmallVectorImpl<Value> &sizes,
     SmallVectorImpl<Value> &strides, Value &sizeBytes) const {
-  assert(isSupportedMemRefType(memRefType) &&
+  assert(isConvertibleAndHasIdentityMaps(memRefType) &&
          "layout maps must have been normalized away");
 
   sizes.reserve(memRefType.getRank());
@@ -1158,8 +1161,8 @@ Value ConvertToLLVMPattern::getSizeInBytes(
   //   %0 = getelementptr %elementType* null, %indexType 1
   //   %1 = ptrtoint %elementType* %0 to %indexType
   // which is a common pattern of getting the size of a type in bytes.
-  auto convertedPtrType =
-      typeConverter->convertType(type).cast<LLVM::LLVMType>().getPointerTo();
+  auto convertedPtrType = LLVM::LLVMPointerType::get(
+      typeConverter->convertType(type).cast<LLVM::LLVMType>());
   auto nullPtr = rewriter.create<LLVM::NullOp>(loc, convertedPtrType);
   auto gep = rewriter.create<LLVM::GEPOp>(
       loc, convertedPtrType,
@@ -1315,7 +1318,8 @@ static void wrapExternalFunction(OpBuilder &builder, Location loc,
                     builder, loc, typeConverter, unrankedMemRefType,
                     wrapperArgsRange.take_front(numToDrop));
 
-      auto ptrTy = packed.getType().cast<LLVM::LLVMType>().getPointerTo();
+      auto ptrTy =
+          LLVM::LLVMPointerType::get(packed.getType().cast<LLVM::LLVMType>());
       Value one = builder.create<LLVM::ConstantOp>(
           loc, typeConverter.convertType(builder.getIndexType()),
           builder.getIntegerAttr(builder.getIndexType(), 1));
@@ -1512,11 +1516,12 @@ static NDVectorTypeInfo extractNDVectorTypeInfo(VectorType vectorType,
     return info;
   info.arraySizes.reserve(vectorType.getRank() - 1);
   auto llvmTy = info.llvmArrayTy;
-  while (llvmTy.isArrayTy()) {
-    info.arraySizes.push_back(llvmTy.getArrayNumElements());
-    llvmTy = llvmTy.getArrayElementType();
+  while (llvmTy.isa<LLVM::LLVMArrayType>()) {
+    info.arraySizes.push_back(
+        llvmTy.cast<LLVM::LLVMArrayType>().getNumElements());
+    llvmTy = llvmTy.cast<LLVM::LLVMArrayType>().getElementType();
   }
-  if (!llvmTy.isVectorTy())
+  if (!llvmTy.isa<LLVM::LLVMVectorType>())
     return info;
   info.llvmVectorTy = llvmTy;
   return info;
@@ -1644,7 +1649,7 @@ LogicalResult LLVM::detail::vectorOneToOneRewrite(
     return failure();
 
   auto llvmArrayTy = operands[0].getType().cast<LLVM::LLVMType>();
-  if (!llvmArrayTy.isArrayTy())
+  if (!llvmArrayTy.isa<LLVM::LLVMArrayType>())
     return oneToOneRewrite(op, targetOp, operands, typeConverter, rewriter);
 
   auto callback = [op, targetOp, &rewriter](LLVM::LLVMType llvmVectorTy,
@@ -1723,8 +1728,7 @@ struct AssertOpLowering : public ConvertOpToLLVMPattern<AssertOp> {
     if (!abortFunc) {
       OpBuilder::InsertionGuard guard(rewriter);
       rewriter.setInsertionPointToStart(module.getBody());
-      auto abortFuncTy =
-          LLVM::LLVMType::getFunctionTy(getVoidType(), {}, /*isVarArg=*/false);
+      auto abortFuncTy = LLVM::LLVMFunctionType::get(getVoidType(), {});
       abortFunc = rewriter.create<LLVM::LLVMFuncOp>(rewriter.getUnknownLoc(),
                                                     "abort", abortFuncTy);
     }
@@ -1949,8 +1953,7 @@ struct AllocLikeOpLowering : public ConvertToLLVMPattern {
       for (Value param : params)
         paramTypes.push_back(param.getType().cast<LLVM::LLVMType>());
       auto allocFuncType =
-          LLVM::LLVMType::getFunctionTy(getVoidPtrType(), paramTypes,
-                                        /*isVarArg=*/false);
+          LLVM::LLVMFunctionType::get(getVoidPtrType(), paramTypes);
       OpBuilder::InsertionGuard guard(rewriter);
       rewriter.setInsertionPointToStart(module.getBody());
       allocFuncOp = rewriter.create<LLVM::LLVMFuncOp>(rewriter.getUnknownLoc(),
@@ -1977,7 +1980,7 @@ struct AllocLikeOpLowering : public ConvertToLLVMPattern {
 
   LogicalResult match(Operation *op) const override {
     MemRefType memRefType = getMemRefResultType(op);
-    return success(isSupportedMemRefType(memRefType));
+    return success(isConvertibleAndHasIdentityMaps(memRefType));
   }
 
   // An `alloc` is converted into a definition of a memref descriptor value and
@@ -2202,9 +2205,10 @@ static LogicalResult copyUnrankedDescriptors(OpBuilder &builder, Location loc,
 
   // Get frequently used types.
   MLIRContext *context = builder.getContext();
-  auto voidType = LLVM::LLVMType::getVoidTy(context);
-  auto voidPtrType = LLVM::LLVMType::getInt8PtrTy(context);
-  auto i1Type = LLVM::LLVMType::getInt1Ty(context);
+  auto voidType = LLVM::LLVMVoidType::get(context);
+  LLVM::LLVMType voidPtrType =
+      LLVM::LLVMPointerType::get(LLVM::LLVMIntegerType::get(context, 8));
+  auto i1Type = LLVM::LLVMIntegerType::get(context, 1);
   LLVM::LLVMType indexType = typeConverter.getIndexType();
 
   // Find the malloc and free, or declare them if necessary.
@@ -2215,8 +2219,8 @@ static LogicalResult copyUnrankedDescriptors(OpBuilder &builder, Location loc,
     builder.setInsertionPointToStart(module.getBody());
     mallocFunc = builder.create<LLVM::LLVMFuncOp>(
         builder.getUnknownLoc(), "malloc",
-        LLVM::LLVMType::getFunctionTy(
-            voidPtrType, llvm::makeArrayRef(indexType), /*isVarArg=*/false));
+        LLVM::LLVMFunctionType::get(voidPtrType, llvm::makeArrayRef(indexType),
+                                    /*isVarArg=*/false));
   }
   auto freeFunc = module.lookupSymbol<LLVM::LLVMFuncOp>("free");
   if (!freeFunc && !toDynamic) {
@@ -2224,8 +2228,8 @@ static LogicalResult copyUnrankedDescriptors(OpBuilder &builder, Location loc,
     builder.setInsertionPointToStart(module.getBody());
     freeFunc = builder.create<LLVM::LLVMFuncOp>(
         builder.getUnknownLoc(), "free",
-        LLVM::LLVMType::getFunctionTy(voidType, llvm::makeArrayRef(voidPtrType),
-                                      /*isVarArg=*/false));
+        LLVM::LLVMFunctionType::get(voidType, llvm::makeArrayRef(voidPtrType),
+                                    /*isVarArg=*/false));
   }
 
   // Initialize shared constants.
@@ -2371,8 +2375,7 @@ struct DeallocOpLowering : public ConvertOpToLLVMPattern<DeallocOp> {
           op->getParentOfType<ModuleOp>().getBody());
       freeFunc = rewriter.create<LLVM::LLVMFuncOp>(
           rewriter.getUnknownLoc(), "free",
-          LLVM::LLVMType::getFunctionTy(getVoidType(), getVoidPtrType(),
-                                        /*isVarArg=*/false));
+          LLVM::LLVMFunctionType::get(getVoidType(), getVoidPtrType()));
     }
 
     MemRefDescriptor memref(transformed.memref());
@@ -2399,7 +2402,7 @@ convertGlobalMemrefTypeToLLVM(MemRefType type,
   LLVM::LLVMType arrayTy = elementType;
   // Shape has the outermost dim at index 0, so need to walk it backwards
   for (int64_t dim : llvm::reverse(type.getShape()))
-    arrayTy = LLVM::LLVMType::getArrayTy(arrayTy, dim);
+    arrayTy = LLVM::LLVMArrayType::get(arrayTy, dim);
   return arrayTy;
 }
 
@@ -2411,7 +2414,7 @@ struct GlobalMemrefOpLowering : public ConvertOpToLLVMPattern<GlobalMemrefOp> {
   matchAndRewrite(GlobalMemrefOp global, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     MemRefType type = global.type().cast<MemRefType>();
-    if (!isSupportedMemRefType(type))
+    if (!isConvertibleAndHasIdentityMaps(type))
       return failure();
 
     LLVM::LLVMType arrayTy =
@@ -2457,13 +2460,14 @@ struct GetGlobalMemrefOpLowering : public AllocLikeOpLowering {
     LLVM::LLVMType arrayTy =
         convertGlobalMemrefTypeToLLVM(type, *getTypeConverter());
     auto addressOf = rewriter.create<LLVM::AddressOfOp>(
-        loc, arrayTy.getPointerTo(memSpace), getGlobalOp.name());
+        loc, LLVM::LLVMPointerType::get(arrayTy, memSpace), getGlobalOp.name());
 
     // Get the address of the first element in the array by creating a GEP with
     // the address of the GV as the base, and (rank + 1) number of 0 indices.
     LLVM::LLVMType elementType =
         unwrap(typeConverter->convertType(type.getElementType()));
-    LLVM::LLVMType elementPtrType = elementType.getPointerTo(memSpace);
+    LLVM::LLVMType elementPtrType =
+        LLVM::LLVMPointerType::get(elementType, memSpace);
 
     SmallVector<Value, 4> operands = {addressOf};
     operands.insert(operands.end(), type.getRank() + 1,
@@ -2504,9 +2508,9 @@ struct RsqrtOpLowering : public ConvertOpToLLVMPattern<RsqrtOp> {
     auto floatType = getElementTypeOrSelf(resultType).cast<FloatType>();
     auto floatOne = rewriter.getFloatAttr(floatType, 1.0);
 
-    if (!operandType.isArrayTy()) {
+    if (!operandType.isa<LLVM::LLVMArrayType>()) {
       LLVM::ConstantOp one;
-      if (operandType.isVectorTy()) {
+      if (operandType.isa<LLVM::LLVMVectorType>()) {
         one = rewriter.create<LLVM::ConstantOp>(
             loc, operandType,
             SplatElementsAttr::get(resultType.cast<ShapedType>(), floatOne));
@@ -2526,8 +2530,10 @@ struct RsqrtOpLowering : public ConvertOpToLLVMPattern<RsqrtOp> {
         op.getOperation(), operands, *getTypeConverter(),
         [&](LLVM::LLVMType llvmVectorTy, ValueRange operands) {
           auto splatAttr = SplatElementsAttr::get(
-              mlir::VectorType::get({llvmVectorTy.getVectorNumElements()},
-                                    floatType),
+              mlir::VectorType::get(
+                  {llvmVectorTy.cast<LLVM::LLVMFixedVectorType>()
+                       .getNumElements()},
+                  floatType),
               floatOne);
           auto one =
               rewriter.create<LLVM::ConstantOp>(loc, llvmVectorTy, splatAttr);
@@ -2614,12 +2620,13 @@ struct MemRefCastOpLowering : public ConvertOpToLLVMPattern<MemRefCastOp> {
       // ptr = ExtractValueOp src, 1
       auto ptr = memRefDesc.memRefDescPtr(rewriter, loc);
       // castPtr = BitCastOp i8* to structTy*
-      auto castPtr =
-          rewriter
-              .create<LLVM::BitcastOp>(
-                  loc, targetStructType.cast<LLVM::LLVMType>().getPointerTo(),
-                  ptr)
-              .getResult();
+      auto castPtr = rewriter
+                         .create<LLVM::BitcastOp>(
+                             loc,
+                             LLVM::LLVMPointerType::get(
+                                 targetStructType.cast<LLVM::LLVMType>()),
+                             ptr)
+                         .getResult();
       // struct = LoadOp castPtr
       auto loadOp = rewriter.create<LLVM::LoadOp>(loc, castPtr);
       rewriter.replaceOp(memRefCastOp, loadOp.getResult());
@@ -2654,8 +2661,8 @@ static void extractPointersAndOffset(Location loc,
   Type elementType = operandType.cast<UnrankedMemRefType>().getElementType();
   LLVM::LLVMType llvmElementType =
       unwrap(typeConverter.convertType(elementType));
-  LLVM::LLVMType elementPtrPtrType =
-      llvmElementType.getPointerTo(memorySpace).getPointerTo();
+  LLVM::LLVMType elementPtrPtrType = LLVM::LLVMPointerType::get(
+      LLVM::LLVMPointerType::get(llvmElementType, memorySpace));
 
   // Extract pointer to the underlying ranked memref descriptor and cast it to
   // ElemType**.
@@ -2700,8 +2707,8 @@ struct MemRefReinterpretCastOpLowering
     MemRefType targetMemRefType =
         castOp.getResult().getType().cast<MemRefType>();
     auto llvmTargetDescriptorTy = typeConverter->convertType(targetMemRefType)
-                                      .dyn_cast_or_null<LLVM::LLVMType>();
-    if (!llvmTargetDescriptorTy || !llvmTargetDescriptorTy.isStructTy())
+                                      .dyn_cast_or_null<LLVM::LLVMStructType>();
+    if (!llvmTargetDescriptorTy)
       return failure();
 
     // Create descriptor.
@@ -2804,8 +2811,8 @@ struct MemRefReshapeOpLowering
     // Set pointers and offset.
     LLVM::LLVMType llvmElementType =
         unwrap(typeConverter->convertType(elementType));
-    LLVM::LLVMType elementPtrPtrType =
-        llvmElementType.getPointerTo(addressSpace).getPointerTo();
+    auto elementPtrPtrType = LLVM::LLVMPointerType::get(
+        LLVM::LLVMPointerType::get(llvmElementType, addressSpace));
     UnrankedMemRefDescriptor::setAllocatedPtr(rewriter, loc, underlyingDescPtr,
                                               elementPtrPtrType, allocatedPtr);
     UnrankedMemRefDescriptor::setAlignedPtr(rewriter, loc, *getTypeConverter(),
@@ -2850,7 +2857,7 @@ struct MemRefReshapeOpLowering
 
     Value zeroIndex = createIndexConstant(rewriter, loc, 0);
     Value pred = rewriter.create<LLVM::ICmpOp>(
-        loc, LLVM::LLVMType::getInt1Ty(rewriter.getContext()),
+        loc, LLVM::LLVMIntegerType::get(rewriter.getContext(), 1),
         LLVM::ICmpPredicate::sge, indexArg, zeroIndex);
 
     Block *bodyBlock =
@@ -2858,7 +2865,7 @@ struct MemRefReshapeOpLowering
     rewriter.setInsertionPointToStart(bodyBlock);
 
     // Copy size from shape to descriptor.
-    LLVM::LLVMType llvmIndexPtrType = indexType.getPointerTo();
+    LLVM::LLVMType llvmIndexPtrType = LLVM::LLVMPointerType::get(indexType);
     Value sizeLoadGep = rewriter.create<LLVM::GEPOp>(
         loc, llvmIndexPtrType, shapeOperandPtr, ValueRange{indexArg});
     Value size = rewriter.create<LLVM::LoadOp>(loc, sizeLoadGep);
@@ -2950,14 +2957,14 @@ struct DimOpLowering : public ConvertOpToLLVMPattern<DimOp> {
     Value underlyingRankedDesc = unrankedDesc.memRefDescPtr(rewriter, loc);
     Value scalarMemRefDescPtr = rewriter.create<LLVM::BitcastOp>(
         loc,
-        typeConverter->convertType(scalarMemRefType)
-            .cast<LLVM::LLVMType>()
-            .getPointerTo(addressSpace),
+        LLVM::LLVMPointerType::get(
+            typeConverter->convertType(scalarMemRefType).cast<LLVM::LLVMType>(),
+            addressSpace),
         underlyingRankedDesc);
 
     // Get pointer to offset field of memref<element_type> descriptor.
-    Type indexPtrTy =
-        getTypeConverter()->getIndexType().getPointerTo(addressSpace);
+    Type indexPtrTy = LLVM::LLVMPointerType::get(
+        getTypeConverter()->getIndexType(), addressSpace);
     Value two = rewriter.create<LLVM::ConstantOp>(
         loc, typeConverter->convertType(rewriter.getI32Type()),
         rewriter.getI32IntegerAttr(2));
@@ -3027,12 +3034,12 @@ struct RankOpLowering : public ConvertOpToLLVMPattern<RankOp> {
 template <typename Derived>
 struct LoadStoreOpLowering : public ConvertOpToLLVMPattern<Derived> {
   using ConvertOpToLLVMPattern<Derived>::ConvertOpToLLVMPattern;
-  using ConvertOpToLLVMPattern<Derived>::isSupportedMemRefType;
+  using ConvertOpToLLVMPattern<Derived>::isConvertibleAndHasIdentityMaps;
   using Base = LoadStoreOpLowering<Derived>;
 
   LogicalResult match(Derived op) const override {
     MemRefType type = op.getMemRefType();
-    return isSupportedMemRefType(type) ? success() : failure();
+    return isConvertibleAndHasIdentityMaps(type) ? success() : failure();
   }
 };
 
@@ -3120,10 +3127,10 @@ struct IndexCastOpLowering : public ConvertOpToLLVMPattern<IndexCastOp> {
 
     auto targetType =
         typeConverter->convertType(indexCastOp.getResult().getType())
-            .cast<LLVM::LLVMType>();
-    auto sourceType = transformed.in().getType().cast<LLVM::LLVMType>();
-    unsigned targetBits = targetType.getIntegerBitWidth();
-    unsigned sourceBits = sourceType.getIntegerBitWidth();
+            .cast<LLVM::LLVMIntegerType>();
+    auto sourceType = transformed.in().getType().cast<LLVM::LLVMIntegerType>();
+    unsigned targetBits = targetType.getBitWidth();
+    unsigned sourceBits = sourceType.getBitWidth();
 
     if (targetBits == sourceBits)
       rewriter.replaceOp(indexCastOp, transformed.in());
@@ -3462,14 +3469,18 @@ struct SubViewOpLowering : public ConvertOpToLLVMPattern<SubViewOp> {
     // Copy the buffer pointer from the old descriptor to the new one.
     Value extracted = sourceMemRef.allocatedPtr(rewriter, loc);
     Value bitcastPtr = rewriter.create<LLVM::BitcastOp>(
-        loc, targetElementTy.getPointerTo(viewMemRefType.getMemorySpace()),
+        loc,
+        LLVM::LLVMPointerType::get(targetElementTy,
+                                   viewMemRefType.getMemorySpace()),
         extracted);
     targetMemRef.setAllocatedPtr(rewriter, loc, bitcastPtr);
 
     // Copy the buffer pointer from the old descriptor to the new one.
     extracted = sourceMemRef.alignedPtr(rewriter, loc);
     bitcastPtr = rewriter.create<LLVM::BitcastOp>(
-        loc, targetElementTy.getPointerTo(viewMemRefType.getMemorySpace()),
+        loc,
+        LLVM::LLVMPointerType::get(targetElementTy,
+                                   viewMemRefType.getMemorySpace()),
         extracted);
     targetMemRef.setAlignedPtr(rewriter, loc, bitcastPtr);
 
@@ -3662,7 +3673,9 @@ struct ViewOpLowering : public ConvertOpToLLVMPattern<ViewOp> {
     Value allocatedPtr = sourceMemRef.allocatedPtr(rewriter, loc);
     auto srcMemRefType = viewOp.source().getType().cast<MemRefType>();
     Value bitcastPtr = rewriter.create<LLVM::BitcastOp>(
-        loc, targetElementTy.getPointerTo(srcMemRefType.getMemorySpace()),
+        loc,
+        LLVM::LLVMPointerType::get(targetElementTy,
+                                   srcMemRefType.getMemorySpace()),
         allocatedPtr);
     targetMemRef.setAllocatedPtr(rewriter, loc, bitcastPtr);
 
@@ -3671,7 +3684,9 @@ struct ViewOpLowering : public ConvertOpToLLVMPattern<ViewOp> {
     alignedPtr = rewriter.create<LLVM::GEPOp>(loc, alignedPtr.getType(),
                                               alignedPtr, adaptor.byte_shift());
     bitcastPtr = rewriter.create<LLVM::BitcastOp>(
-        loc, targetElementTy.getPointerTo(srcMemRefType.getMemorySpace()),
+        loc,
+        LLVM::LLVMPointerType::get(targetElementTy,
+                                   srcMemRefType.getMemorySpace()),
         alignedPtr);
     targetMemRef.setAlignedPtr(rewriter, loc, bitcastPtr);
 
@@ -3876,8 +3891,9 @@ struct GenericAtomicRMWOpLowering
     // Append the cmpxchg op to the end of the loop block.
     auto successOrdering = LLVM::AtomicOrdering::acq_rel;
     auto failureOrdering = LLVM::AtomicOrdering::monotonic;
-    auto boolType = LLVM::LLVMType::getInt1Ty(rewriter.getContext());
-    auto pairType = LLVM::LLVMType::getStructTy(valueType, boolType);
+    auto boolType = LLVM::LLVMIntegerType::get(rewriter.getContext(), 1);
+    auto pairType = LLVM::LLVMStructType::getLiteral(rewriter.getContext(),
+                                                     {valueType, boolType});
     auto cmpxchg = rewriter.create<LLVM::AtomicCmpXchgOp>(
         loc, pairType, dataPtr, loopArgument, result, successOrdering,
         failureOrdering);
@@ -4054,17 +4070,18 @@ Type LLVMTypeConverter::packFunctionResults(ArrayRef<Type> types) {
     resultTypes.push_back(converted);
   }
 
-  return LLVM::LLVMType::getStructTy(&getContext(), resultTypes);
+  return LLVM::LLVMStructType::getLiteral(&getContext(), resultTypes);
 }
 
 Value LLVMTypeConverter::promoteOneMemRefDescriptor(Location loc, Value operand,
                                                     OpBuilder &builder) {
   auto *context = builder.getContext();
-  auto int64Ty = LLVM::LLVMType::getInt64Ty(builder.getContext());
+  auto int64Ty = LLVM::LLVMIntegerType::get(builder.getContext(), 64);
   auto indexType = IndexType::get(context);
   // Alloca with proper alignment. We do not expect optimizations of this
   // alloca op and so we omit allocating at the entry block.
-  auto ptrType = operand.getType().cast<LLVM::LLVMType>().getPointerTo();
+  auto ptrType =
+      LLVM::LLVMPointerType::get(operand.getType().cast<LLVM::LLVMType>());
   Value one = builder.create<LLVM::ConstantOp>(loc, int64Ty,
                                                IntegerAttr::get(indexType, 1));
   Value allocated =
diff --git a/mlir/lib/Conversion/StandardToSPIRV/CMakeLists.txt b/mlir/lib/Conversion/StandardToSPIRV/CMakeLists.txt
index 4af5d7d4f83a4..7c5d62ff4c191 100644
--- a/mlir/lib/Conversion/StandardToSPIRV/CMakeLists.txt
+++ b/mlir/lib/Conversion/StandardToSPIRV/CMakeLists.txt
@@ -1,7 +1,7 @@
-add_mlir_conversion_library(MLIRStandardToSPIRVTransforms
-  ConvertStandardToSPIRV.cpp
-  ConvertStandardToSPIRVPass.cpp
+add_mlir_conversion_library(MLIRStandardToSPIRV
   LegalizeStandardForSPIRV.cpp
+  StandardToSPIRV.cpp
+  StandardToSPIRVPass.cpp
 
   ADDITIONAL_HEADER_DIRS
   ${MLIR_MAIN_INCLUDE_DIR}/mlir/Dialect/SPIRV
diff --git a/mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp b/mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
index ea483aa6abaeb..96fdcb593c042 100644
--- a/mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
+++ b/mlir/lib/Conversion/StandardToSPIRV/LegalizeStandardForSPIRV.cpp
@@ -12,8 +12,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "../PassDetail.h"
-#include "mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.h"
-#include "mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.h"
+#include "mlir/Conversion/StandardToSPIRV/StandardToSPIRV.h"
+#include "mlir/Conversion/StandardToSPIRV/StandardToSPIRVPass.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
 #include "mlir/Dialect/Vector/VectorOps.h"
@@ -22,6 +22,17 @@
 
 using namespace mlir;
 
+/// Helpers to access the memref operand for each op.
+static Value getMemRefOperand(LoadOp op) { return op.memref(); }
+
+static Value getMemRefOperand(vector::TransferReadOp op) { return op.source(); }
+
+static Value getMemRefOperand(StoreOp op) { return op.memref(); }
+
+static Value getMemRefOperand(vector::TransferWriteOp op) {
+  return op.source();
+}
+
 namespace {
 /// Merges subview operation with load/transferRead operation.
 template <typename OpTy>
@@ -141,7 +152,7 @@ template <typename OpTy>
 LogicalResult
 LoadOpOfSubViewFolder<OpTy>::matchAndRewrite(OpTy loadOp,
                                              PatternRewriter &rewriter) const {
-  auto subViewOp = loadOp.memref().template getDefiningOp<SubViewOp>();
+  auto subViewOp = getMemRefOperand(loadOp).template getDefiningOp<SubViewOp>();
   if (!subViewOp) {
     return failure();
   }
@@ -162,7 +173,8 @@ template <typename OpTy>
 LogicalResult
 StoreOpOfSubViewFolder<OpTy>::matchAndRewrite(OpTy storeOp,
                                               PatternRewriter &rewriter) const {
-  auto subViewOp = storeOp.memref().template getDefiningOp<SubViewOp>();
+  auto subViewOp =
+      getMemRefOperand(storeOp).template getDefiningOp<SubViewOp>();
   if (!subViewOp) {
     return failure();
   }
diff --git a/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp b/mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
similarity index 99%
rename from mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
rename to mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
index d15623568212c..164ed36095ac2 100644
--- a/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.cpp
+++ b/mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRV.cpp
@@ -1,4 +1,4 @@
-//===- ConvertStandardToSPIRV.cpp - Standard to SPIR-V dialect conversion--===//
+//===- StandardToSPIRV.cpp - Standard to SPIR-V Patterns ------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,7 +6,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements patterns to convert standard ops to SPIR-V ops.
+// This file implements patterns to convert standard dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
@@ -924,10 +924,14 @@ LoadOpPattern::matchAndRewrite(LoadOp loadOp, ArrayRef<Value> operands,
 LogicalResult
 ReturnOpPattern::matchAndRewrite(ReturnOp returnOp, ArrayRef<Value> operands,
                                  ConversionPatternRewriter &rewriter) const {
-  if (returnOp.getNumOperands()) {
+  if (returnOp.getNumOperands() > 1)
     return failure();
+
+  if (returnOp.getNumOperands() == 1) {
+    rewriter.replaceOpWithNewOp<spirv::ReturnValueOp>(returnOp, operands[0]);
+  } else {
+    rewriter.replaceOpWithNewOp<spirv::ReturnOp>(returnOp);
   }
-  rewriter.replaceOpWithNewOp<spirv::ReturnOp>(returnOp);
   return success();
 }
 
diff --git a/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.cpp b/mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRVPass.cpp
similarity index 83%
rename from mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.cpp
rename to mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRVPass.cpp
index c2477e8523076..8ae67cc6a16ad 100644
--- a/mlir/lib/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.cpp
+++ b/mlir/lib/Conversion/StandardToSPIRV/StandardToSPIRVPass.cpp
@@ -1,4 +1,4 @@
-//===- ConvertStandardToSPIRVPass.cpp - Convert Std Ops to SPIR-V Ops -----===//
+//===- StandardToSPIRVPass.cpp - Standard to SPIR-V Passes ----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,14 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements a pass to convert MLIR standard ops into the SPIR-V
-// ops.
+// This file implements a pass to convert standard dialect to SPIR-V dialect.
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.h"
+#include "mlir/Conversion/StandardToSPIRV/StandardToSPIRVPass.h"
 #include "../PassDetail.h"
-#include "mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRV.h"
+#include "mlir/Conversion/StandardToSPIRV/StandardToSPIRV.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
 #include "mlir/Dialect/SPIRV/Transforms/SPIRVConversion.h"
 
diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
index ebe07366f6eca..e023b6da460b5 100644
--- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
+++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
@@ -141,12 +141,10 @@ static Value buildVectorComparison(ConversionPatternRewriter &rewriter,
   return rewriter.create<CmpIOp>(loc, CmpIPredicate::slt, indices, bounds);
 }
 
-// Helper that returns data layout alignment of an operation with memref.
-template <typename T>
-LogicalResult getMemRefAlignment(LLVMTypeConverter &typeConverter, T op,
-                                 unsigned &align) {
-  Type elementTy =
-      typeConverter.convertType(op.getMemRefType().getElementType());
+// Helper that returns data layout alignment of a memref.
+LogicalResult getMemRefAlignment(LLVMTypeConverter &typeConverter,
+                                 MemRefType memrefType, unsigned &align) {
+  Type elementTy = typeConverter.convertType(memrefType.getElementType());
   if (!elementTy)
     return failure();
 
@@ -195,7 +193,7 @@ static LogicalResult getBasePtr(ConversionPatternRewriter &rewriter,
   Value base;
   if (failed(getBase(rewriter, loc, memref, memRefType, base)))
     return failure();
-  auto pType = type.template cast<LLVM::LLVMType>().getPointerTo();
+  auto pType = LLVM::LLVMPointerType::get(type.template cast<LLVM::LLVMType>());
   base = rewriter.create<LLVM::BitcastOp>(loc, pType, base);
   ptr = rewriter.create<LLVM::GEPOp>(loc, pType, base);
   return success();
@@ -211,7 +209,7 @@ static LogicalResult getIndexedPtrs(ConversionPatternRewriter &rewriter,
   if (failed(getBase(rewriter, loc, memref, memRefType, base)))
     return failure();
   auto pType = MemRefDescriptor(memref).getElementPtrType();
-  auto ptrsType = LLVM::LLVMType::getVectorTy(pType, vType.getDimSize(0));
+  auto ptrsType = LLVM::LLVMFixedVectorType::get(pType, vType.getDimSize(0));
   ptrs = rewriter.create<LLVM::GEPOp>(loc, ptrsType, base, indices);
   return success();
 }
@@ -222,7 +220,8 @@ replaceTransferOpWithLoadOrStore(ConversionPatternRewriter &rewriter,
                                  TransferReadOp xferOp,
                                  ArrayRef<Value> operands, Value dataPtr) {
   unsigned align;
-  if (failed(getMemRefAlignment(typeConverter, xferOp, align)))
+  if (failed(getMemRefAlignment(
+          typeConverter, xferOp.getShapedType().cast<MemRefType>(), align)))
     return failure();
   rewriter.replaceOpWithNewOp<LLVM::LoadOp>(xferOp, dataPtr, align);
   return success();
@@ -243,7 +242,8 @@ replaceTransferOpWithMasked(ConversionPatternRewriter &rewriter,
     return failure();
 
   unsigned align;
-  if (failed(getMemRefAlignment(typeConverter, xferOp, align)))
+  if (failed(getMemRefAlignment(
+          typeConverter, xferOp.getShapedType().cast<MemRefType>(), align)))
     return failure();
 
   rewriter.replaceOpWithNewOp<LLVM::MaskedLoadOp>(
@@ -258,7 +258,8 @@ replaceTransferOpWithLoadOrStore(ConversionPatternRewriter &rewriter,
                                  TransferWriteOp xferOp,
                                  ArrayRef<Value> operands, Value dataPtr) {
   unsigned align;
-  if (failed(getMemRefAlignment(typeConverter, xferOp, align)))
+  if (failed(getMemRefAlignment(
+          typeConverter, xferOp.getShapedType().cast<MemRefType>(), align)))
     return failure();
   auto adaptor = TransferWriteOpAdaptor(operands);
   rewriter.replaceOpWithNewOp<LLVM::StoreOp>(xferOp, adaptor.vector(), dataPtr,
@@ -272,7 +273,8 @@ replaceTransferOpWithMasked(ConversionPatternRewriter &rewriter,
                             TransferWriteOp xferOp, ArrayRef<Value> operands,
                             Value dataPtr, Value mask) {
   unsigned align;
-  if (failed(getMemRefAlignment(typeConverter, xferOp, align)))
+  if (failed(getMemRefAlignment(
+          typeConverter, xferOp.getShapedType().cast<MemRefType>(), align)))
     return failure();
 
   auto adaptor = TransferWriteOpAdaptor(operands);
@@ -345,7 +347,8 @@ class VectorMaskedLoadOpConversion
 
     // Resolve alignment.
     unsigned align;
-    if (failed(getMemRefAlignment(*getTypeConverter(), load, align)))
+    if (failed(getMemRefAlignment(*getTypeConverter(), load.getMemRefType(),
+                                  align)))
       return failure();
 
     auto vtype = typeConverter->convertType(load.getResultVectorType());
@@ -375,7 +378,8 @@ class VectorMaskedStoreOpConversion
 
     // Resolve alignment.
     unsigned align;
-    if (failed(getMemRefAlignment(*getTypeConverter(), store, align)))
+    if (failed(getMemRefAlignment(*getTypeConverter(), store.getMemRefType(),
+                                  align)))
       return failure();
 
     auto vtype = typeConverter->convertType(store.getValueVectorType());
@@ -405,7 +409,8 @@ class VectorGatherOpConversion
 
     // Resolve alignment.
     unsigned align;
-    if (failed(getMemRefAlignment(*getTypeConverter(), gather, align)))
+    if (failed(getMemRefAlignment(*getTypeConverter(), gather.getMemRefType(),
+                                  align)))
       return failure();
 
     // Get index ptrs.
@@ -438,7 +443,8 @@ class VectorScatterOpConversion
 
     // Resolve alignment.
     unsigned align;
-    if (failed(getMemRefAlignment(*getTypeConverter(), scatter, align)))
+    if (failed(getMemRefAlignment(*getTypeConverter(), scatter.getMemRefType(),
+                                  align)))
       return failure();
 
     // Get index ptrs.
@@ -606,7 +612,7 @@ class VectorCreateMaskOpConversion
   LogicalResult
   matchAndRewrite(vector::CreateMaskOp op, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
-    auto dstType = op->getResult(0).getType().cast<VectorType>();
+    auto dstType = op.getType();
     int64_t rank = dstType.getRank();
     if (rank == 1) {
       rewriter.replaceOp(
@@ -742,7 +748,7 @@ class VectorExtractOpConversion
 
     // Remaining extraction of element from 1-D LLVM vector
     auto position = positionAttrs.back().cast<IntegerAttr>();
-    auto i64Type = LLVM::LLVMType::getInt64Ty(rewriter.getContext());
+    auto i64Type = LLVM::LLVMIntegerType::get(rewriter.getContext(), 64);
     auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position);
     extracted =
         rewriter.create<LLVM::ExtractElementOp>(loc, extracted, constant);
@@ -850,7 +856,7 @@ class VectorInsertOpConversion
     }
 
     // Insertion of an element into a 1-D LLVM vector.
-    auto i64Type = LLVM::LLVMType::getInt64Ty(rewriter.getContext());
+    auto i64Type = LLVM::LLVMIntegerType::get(rewriter.getContext(), 64);
     auto constant = rewriter.create<LLVM::ConstantOp>(loc, i64Type, position);
     Value inserted = rewriter.create<LLVM::InsertElementOp>(
         loc, typeConverter->convertType(oneDVectorType), extracted,
@@ -1085,8 +1091,7 @@ class VectorTypeCastOpConversion
     auto loc = castOp->getLoc();
     MemRefType sourceMemRefType =
         castOp.getOperand().getType().cast<MemRefType>();
-    MemRefType targetMemRefType =
-        castOp.getResult().getType().cast<MemRefType>();
+    MemRefType targetMemRefType = castOp.getType();
 
     // Only static shape casts supported atm.
     if (!sourceMemRefType.hasStaticShape() ||
@@ -1094,14 +1099,14 @@ class VectorTypeCastOpConversion
       return failure();
 
     auto llvmSourceDescriptorTy =
-        operands[0].getType().dyn_cast<LLVM::LLVMType>();
-    if (!llvmSourceDescriptorTy || !llvmSourceDescriptorTy.isStructTy())
+        operands[0].getType().dyn_cast<LLVM::LLVMStructType>();
+    if (!llvmSourceDescriptorTy)
       return failure();
     MemRefDescriptor sourceMemRef(operands[0]);
 
     auto llvmTargetDescriptorTy = typeConverter->convertType(targetMemRefType)
-                                      .dyn_cast_or_null<LLVM::LLVMType>();
-    if (!llvmTargetDescriptorTy || !llvmTargetDescriptorTy.isStructTy())
+                                      .dyn_cast_or_null<LLVM::LLVMStructType>();
+    if (!llvmTargetDescriptorTy)
       return failure();
 
     // Only contiguous source buffers supported atm.
@@ -1117,7 +1122,7 @@ class VectorTypeCastOpConversion
         }))
       return failure();
 
-    auto int64Ty = LLVM::LLVMType::getInt64Ty(rewriter.getContext());
+    auto int64Ty = LLVM::LLVMIntegerType::get(rewriter.getContext(), 64);
 
     // Create descriptor.
     auto desc = MemRefDescriptor::undef(rewriter, loc, llvmTargetDescriptorTy);
@@ -1182,8 +1187,11 @@ class VectorTransferConversion : public ConvertOpToLLVMPattern<ConcreteOp> {
                                        xferOp.getVectorType().getRank(),
                                        xferOp->getContext()))
       return failure();
+    auto memRefType = xferOp.getShapedType().template dyn_cast<MemRefType>();
+    if (!memRefType)
+      return failure();
     // Only contiguous source tensors supported atm.
-    auto strides = computeContiguousStrides(xferOp.getMemRefType());
+    auto strides = computeContiguousStrides(memRefType);
     if (!strides)
       return failure();
 
@@ -1192,10 +1200,9 @@ class VectorTransferConversion : public ConvertOpToLLVMPattern<ConcreteOp> {
     };
 
     Location loc = xferOp->getLoc();
-    MemRefType memRefType = xferOp.getMemRefType();
 
     if (auto memrefVectorElementType =
-            memRefType.getElementType().dyn_cast<VectorType>()) {
+            memRefType.getElementType().template dyn_cast<VectorType>()) {
       // Memref has vector element type.
       if (memrefVectorElementType.getElementType() !=
           xferOp.getVectorType().getElementType())
@@ -1222,16 +1229,16 @@ class VectorTransferConversion : public ConvertOpToLLVMPattern<ConcreteOp> {
     //    address space 0.
     // TODO: support alignment when possible.
     Value dataPtr = this->getStridedElementPtr(
-        loc, memRefType, adaptor.memref(), adaptor.indices(), rewriter);
-    auto vecTy =
-        toLLVMTy(xferOp.getVectorType()).template cast<LLVM::LLVMType>();
+        loc, memRefType, adaptor.source(), adaptor.indices(), rewriter);
+    auto vecTy = toLLVMTy(xferOp.getVectorType())
+                     .template cast<LLVM::LLVMFixedVectorType>();
     Value vectorDataPtr;
     if (memRefType.getMemorySpace() == 0)
-      vectorDataPtr =
-          rewriter.create<LLVM::BitcastOp>(loc, vecTy.getPointerTo(), dataPtr);
+      vectorDataPtr = rewriter.create<LLVM::BitcastOp>(
+          loc, LLVM::LLVMPointerType::get(vecTy), dataPtr);
     else
       vectorDataPtr = rewriter.create<LLVM::AddrSpaceCastOp>(
-          loc, vecTy.getPointerTo(), dataPtr);
+          loc, LLVM::LLVMPointerType::get(vecTy), dataPtr);
 
     if (!xferOp.isMaskedDim(0))
       return replaceTransferOpWithLoadOrStore(rewriter,
@@ -1245,10 +1252,10 @@ class VectorTransferConversion : public ConvertOpToLLVMPattern<ConcreteOp> {
     //
     // TODO: when the leaf transfer rank is k > 1, we need the last `k`
     //       dimensions here.
-    unsigned vecWidth = vecTy.getVectorNumElements();
+    unsigned vecWidth = vecTy.getNumElements();
     unsigned lastIndex = llvm::size(xferOp.indices()) - 1;
     Value off = xferOp.indices()[lastIndex];
-    Value dim = rewriter.create<DimOp>(loc, xferOp.memref(), lastIndex);
+    Value dim = rewriter.create<DimOp>(loc, xferOp.source(), lastIndex);
     Value mask = buildVectorComparison(
         rewriter, xferOp, enableIndexOptimizations, vecWidth, dim, &off);
 
@@ -1354,11 +1361,11 @@ class VectorPrintOpConversion : public ConvertOpToLLVMPattern<vector::PrintOp> {
       switch (conversion) {
       case PrintConversion::ZeroExt64:
         value = rewriter.create<ZeroExtendIOp>(
-            loc, value, LLVM::LLVMType::getInt64Ty(rewriter.getContext()));
+            loc, value, LLVM::LLVMIntegerType::get(rewriter.getContext(), 64));
         break;
       case PrintConversion::SignExt64:
         value = rewriter.create<SignExtendIOp>(
-            loc, value, LLVM::LLVMType::getInt64Ty(rewriter.getContext()));
+            loc, value, LLVM::LLVMIntegerType::get(rewriter.getContext(), 64));
         break;
       case PrintConversion::None:
         break;
@@ -1402,27 +1409,25 @@ class VectorPrintOpConversion : public ConvertOpToLLVMPattern<vector::PrintOp> {
     OpBuilder moduleBuilder(module.getBodyRegion());
     return moduleBuilder.create<LLVM::LLVMFuncOp>(
         op->getLoc(), name,
-        LLVM::LLVMType::getFunctionTy(
-            LLVM::LLVMType::getVoidTy(op->getContext()), params,
-            /*isVarArg=*/false));
+        LLVM::LLVMFunctionType::get(LLVM::LLVMVoidType::get(op->getContext()),
+                                    params));
   }
 
   // Helpers for method names.
   Operation *getPrintI64(Operation *op) const {
     return getPrint(op, "printI64",
-                    LLVM::LLVMType::getInt64Ty(op->getContext()));
+                    LLVM::LLVMIntegerType::get(op->getContext(), 64));
   }
   Operation *getPrintU64(Operation *op) const {
     return getPrint(op, "printU64",
-                    LLVM::LLVMType::getInt64Ty(op->getContext()));
+                    LLVM::LLVMIntegerType::get(op->getContext(), 64));
   }
   Operation *getPrintFloat(Operation *op) const {
-    return getPrint(op, "printF32",
-                    LLVM::LLVMType::getFloatTy(op->getContext()));
+    return getPrint(op, "printF32", LLVM::LLVMFloatType::get(op->getContext()));
   }
   Operation *getPrintDouble(Operation *op) const {
     return getPrint(op, "printF64",
-                    LLVM::LLVMType::getDoubleTy(op->getContext()));
+                    LLVM::LLVMDoubleType::get(op->getContext()));
   }
   Operation *getPrintOpen(Operation *op) const {
     return getPrint(op, "printOpen", {});
@@ -1453,7 +1458,7 @@ class VectorExtractStridedSliceOpConversion
 
   LogicalResult matchAndRewrite(ExtractStridedSliceOp op,
                                 PatternRewriter &rewriter) const override {
-    auto dstType = op.getResult().getType().cast<VectorType>();
+    auto dstType = op.getType();
 
     assert(!op.offsets().getValue().empty() && "Unexpected empty offsets");
 
diff --git a/mlir/lib/Conversion/VectorToROCDL/VectorToROCDL.cpp b/mlir/lib/Conversion/VectorToROCDL/VectorToROCDL.cpp
index e5474abfd3e37..3e3ddc6aaff67 100644
--- a/mlir/lib/Conversion/VectorToROCDL/VectorToROCDL.cpp
+++ b/mlir/lib/Conversion/VectorToROCDL/VectorToROCDL.cpp
@@ -78,9 +78,9 @@ class VectorTransferConversion : public ConvertOpToLLVMPattern<ConcreteOp> {
     auto toLLVMTy = [&](Type t) {
       return this->getTypeConverter()->convertType(t);
     };
-    LLVM::LLVMType vecTy =
-        toLLVMTy(xferOp.getVectorType()).template cast<LLVM::LLVMType>();
-    unsigned vecWidth = vecTy.getVectorNumElements();
+    auto vecTy = toLLVMTy(xferOp.getVectorType())
+                     .template cast<LLVM::LLVMFixedVectorType>();
+    unsigned vecWidth = vecTy.getNumElements();
     Location loc = xferOp->getLoc();
 
     // The backend result vector scalarization have trouble scalarize
@@ -89,7 +89,9 @@ class VectorTransferConversion : public ConvertOpToLLVMPattern<ConcreteOp> {
       return failure();
 
     // Obtain dataPtr and elementType from the memref.
-    MemRefType memRefType = xferOp.getMemRefType();
+    auto memRefType = xferOp.getShapedType().template dyn_cast<MemRefType>();
+    if (!memRefType)
+      return failure();
     // MUBUF instruction operate only on addresspace 0(unified) or 1(global)
     // In case of 3(LDS): fall back to vector->llvm pass
     // In case of 5(VGPR): wrong
@@ -101,7 +103,7 @@ class VectorTransferConversion : public ConvertOpToLLVMPattern<ConcreteOp> {
     // indices, so no need to calculate offset size in bytes again in
     // the MUBUF instruction.
     Value dataPtr = this->getStridedElementPtr(
-        loc, memRefType, adaptor.memref(), adaptor.indices(), rewriter);
+        loc, memRefType, adaptor.source(), adaptor.indices(), rewriter);
 
     // 1. Create and fill a <4 x i32> dwordConfig with:
     //    1st two elements holding the address of dataPtr.
@@ -119,7 +121,7 @@ class VectorTransferConversion : public ConvertOpToLLVMPattern<ConcreteOp> {
     Type i64Ty = rewriter.getIntegerType(64);
     Value i64x2Ty = rewriter.create<LLVM::BitcastOp>(
         loc,
-        LLVM::LLVMType::getVectorTy(
+        LLVM::LLVMFixedVectorType::get(
             toLLVMTy(i64Ty).template cast<LLVM::LLVMType>(), 2),
         constConfig);
     Value dataPtrAsI64 = rewriter.create<LLVM::PtrToIntOp>(
@@ -127,7 +129,7 @@ class VectorTransferConversion : public ConvertOpToLLVMPattern<ConcreteOp> {
     Value zero = this->createIndexConstant(rewriter, loc, 0);
     Value dwordConfig = rewriter.create<LLVM::InsertElementOp>(
         loc,
-        LLVM::LLVMType::getVectorTy(
+        LLVM::LLVMFixedVectorType::get(
             toLLVMTy(i64Ty).template cast<LLVM::LLVMType>(), 2),
         i64x2Ty, dataPtrAsI64, zero);
     dwordConfig =
diff --git a/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp b/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
index c05e9da2c9498..b0f1b46b2459b 100644
--- a/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
+++ b/mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
@@ -107,7 +107,7 @@ class NDTransferOpHelper {
     // TODO: when we go to k > 1-D vectors adapt minorRank.
     minorRank = 1;
     majorRank = vectorType.getRank() - minorRank;
-    leadingRank = xferOp.getLeadingMemRefRank();
+    leadingRank = xferOp.getLeadingShapedRank();
     majorVectorType =
         VectorType::get(vectorType.getShape().take_front(majorRank),
                         vectorType.getElementType());
@@ -115,9 +115,9 @@ class NDTransferOpHelper {
         VectorType::get(vectorType.getShape().take_back(minorRank),
                         vectorType.getElementType());
     /// Memref of minor vector type is used for individual transfers.
-    memRefMinorVectorType =
-        MemRefType::get(majorVectorType.getShape(), minorVectorType, {},
-                        xferOp.getMemRefType().getMemorySpace());
+    memRefMinorVectorType = MemRefType::get(
+        majorVectorType.getShape(), minorVectorType, {},
+        xferOp.getShapedType().template cast<MemRefType>().getMemorySpace());
   }
 
   LogicalResult doReplace();
@@ -155,7 +155,7 @@ void NDTransferOpHelper<ConcreteOp>::emitLoops(
                             const MemRefBoundsCapture &)>
         loopBodyBuilder) {
   /// Loop nest operates on the major dimensions
-  MemRefBoundsCapture memrefBoundsCapture(xferOp.memref());
+  MemRefBoundsCapture memrefBoundsCapture(xferOp.source());
 
   if (options.unroll) {
     auto shape = majorVectorType.getShape();
@@ -272,9 +272,9 @@ LogicalResult NDTransferOpHelper<TransferReadOp>::doReplace() {
       indexing.append(leadingOffsets.begin(), leadingOffsets.end());
       indexing.append(majorIvsPlusOffsets.begin(), majorIvsPlusOffsets.end());
       indexing.append(minorOffsets.begin(), minorOffsets.end());
-      Value memref = xferOp.memref();
+      Value memref = xferOp.source();
       auto map =
-          getTransferMinorIdentityMap(xferOp.getMemRefType(), minorVectorType);
+          getTransferMinorIdentityMap(xferOp.getShapedType(), minorVectorType);
       ArrayAttr masked;
       if (!xferOp.isMaskedDim(xferOp.getVectorType().getRank() - 1)) {
         OpBuilder &b = ScopedContext::getBuilderRef();
@@ -379,13 +379,13 @@ LogicalResult NDTransferOpHelper<TransferWriteOp>::doReplace() {
       else
         result = std_load(alloc, majorIvs);
       auto map =
-          getTransferMinorIdentityMap(xferOp.getMemRefType(), minorVectorType);
+          getTransferMinorIdentityMap(xferOp.getShapedType(), minorVectorType);
       ArrayAttr masked;
       if (!xferOp.isMaskedDim(xferOp.getVectorType().getRank() - 1)) {
         OpBuilder &b = ScopedContext::getBuilderRef();
         masked = b.getBoolArrayAttr({false});
       }
-      vector_transfer_write(result, xferOp.memref(), indexing,
+      vector_transfer_write(result, xferOp.source(), indexing,
                             AffineMapAttr::get(map), masked);
     };
 
@@ -422,7 +422,7 @@ template <typename TransferOpTy>
 static int computeCoalescedIndex(TransferOpTy transfer) {
   // rank of the remote memory access, coalescing behavior occurs on the
   // innermost memory dimension.
-  auto remoteRank = transfer.getMemRefType().getRank();
+  auto remoteRank = transfer.getShapedType().getRank();
   // Iterate over the results expressions of the permutation map to determine
   // the loop order for creating pointwise copies between remote and local
   // memories.
@@ -536,13 +536,14 @@ LogicalResult VectorTransferRewriter<TransferReadOp>::matchAndRewrite(
   using namespace mlir::edsc::op;
 
   TransferReadOp transfer = cast<TransferReadOp>(op);
-
+  auto memRefType = transfer.getShapedType().dyn_cast<MemRefType>();
+  if (!memRefType)
+    return failure();
   // Fall back to a loop if the fastest varying stride is not 1 or it is
   // permuted.
   int64_t offset;
   SmallVector<int64_t, 4> strides;
-  auto successStrides =
-      getStridesAndOffset(transfer.getMemRefType(), strides, offset);
+  auto successStrides = getStridesAndOffset(memRefType, strides, offset);
   if (succeeded(successStrides) && strides.back() == 1 &&
       transfer.permutation_map().isMinorIdentity()) {
     // If > 1D, emit a bunch of loops around 1-D vector transfers.
@@ -557,8 +558,8 @@ LogicalResult VectorTransferRewriter<TransferReadOp>::matchAndRewrite(
   // Conservative lowering to scalar load / stores.
   // 1. Setup all the captures.
   ScopedContext scope(rewriter, transfer.getLoc());
-  StdIndexedValue remote(transfer.memref());
-  MemRefBoundsCapture memRefBoundsCapture(transfer.memref());
+  StdIndexedValue remote(transfer.source());
+  MemRefBoundsCapture memRefBoundsCapture(transfer.source());
   VectorBoundsCapture vectorBoundsCapture(transfer.vector());
   int coalescedIdx = computeCoalescedIndex(transfer);
   // Swap the vectorBoundsCapture which will reorder loop bounds.
@@ -621,13 +622,15 @@ LogicalResult VectorTransferRewriter<TransferWriteOp>::matchAndRewrite(
   using namespace edsc::op;
 
   TransferWriteOp transfer = cast<TransferWriteOp>(op);
+  auto memRefType = transfer.getShapedType().template dyn_cast<MemRefType>();
+  if (!memRefType)
+    return failure();
 
   // Fall back to a loop if the fastest varying stride is not 1 or it is
   // permuted.
   int64_t offset;
   SmallVector<int64_t, 4> strides;
-  auto successStrides =
-      getStridesAndOffset(transfer.getMemRefType(), strides, offset);
+  auto successStrides = getStridesAndOffset(memRefType, strides, offset);
   if (succeeded(successStrides) && strides.back() == 1 &&
       transfer.permutation_map().isMinorIdentity()) {
     // If > 1D, emit a bunch of loops around 1-D vector transfers.
@@ -641,8 +644,8 @@ LogicalResult VectorTransferRewriter<TransferWriteOp>::matchAndRewrite(
 
   // 1. Setup all the captures.
   ScopedContext scope(rewriter, transfer.getLoc());
-  StdIndexedValue remote(transfer.memref());
-  MemRefBoundsCapture memRefBoundsCapture(transfer.memref());
+  StdIndexedValue remote(transfer.source());
+  MemRefBoundsCapture memRefBoundsCapture(transfer.source());
   Value vectorValue(transfer.vector());
   VectorBoundsCapture vectorBoundsCapture(transfer.vector());
   int coalescedIdx = computeCoalescedIndex(transfer);
diff --git a/mlir/lib/Conversion/VectorToSPIRV/CMakeLists.txt b/mlir/lib/Conversion/VectorToSPIRV/CMakeLists.txt
index 060afdfbbddb9..76518839531c4 100644
--- a/mlir/lib/Conversion/VectorToSPIRV/CMakeLists.txt
+++ b/mlir/lib/Conversion/VectorToSPIRV/CMakeLists.txt
@@ -1,5 +1,6 @@
 add_mlir_conversion_library(MLIRVectorToSPIRV
   VectorToSPIRV.cpp
+  VectorToSPIRVPass.cpp
 
   ADDITIONAL_HEADER_DIRS
   ${MLIR_MAIN_INCLUDE_DIR}/mlir/Conversion/VectorToSPIRV
diff --git a/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp b/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
index 7f73391901152..a2735e646bec0 100644
--- a/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
+++ b/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp
@@ -1,4 +1,4 @@
-//===------- VectorToSPIRV.cpp - Vector to SPIRV lowering passes ----------===//
+//===- VectorToSPIRV.cpp - Vector to SPIR-V Patterns ----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,20 +6,18 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements a pass to generate SPIRV operations for Vector
-// operations.
+// This file implements patterns to convert Vector dialect to SPIRV dialect.
 //
 //===----------------------------------------------------------------------===//
 
+#include "mlir/Conversion/VectorToSPIRV/VectorToSPIRV.h"
+
 #include "../PassDetail.h"
-#include "mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRV.h"
-#include "mlir/Conversion/VectorToSPIRV/ConvertVectorToSPIRVPass.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVTypes.h"
 #include "mlir/Dialect/SPIRV/Transforms/SPIRVConversion.h"
 #include "mlir/Dialect/Vector/VectorOps.h"
-#include "mlir/Pass/Pass.h"
 #include "mlir/Transforms/DialectConversion.h"
 
 using namespace mlir;
@@ -68,7 +66,7 @@ struct VectorInsertOpConvert final : public SPIRVOpLowering<vector::InsertOp> {
   matchAndRewrite(vector::InsertOp insertOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     if (insertOp.getSourceType().isa<VectorType>() ||
-        !spirv::CompositeType::isValid(insertOp.getDestVectorType())) 
+        !spirv::CompositeType::isValid(insertOp.getDestVectorType()))
       return failure();
     vector::InsertOp::Adaptor adaptor(operands);
     int32_t id = insertOp.position().begin()->cast<IntegerAttr>().getInt();
@@ -124,34 +122,3 @@ void mlir::populateVectorToSPIRVPatterns(MLIRContext *context,
                   VectorInsertOpConvert, VectorExtractElementOpConvert,
                   VectorInsertElementOpConvert>(context, typeConverter);
 }
-
-namespace {
-struct LowerVectorToSPIRVPass
-    : public ConvertVectorToSPIRVBase<LowerVectorToSPIRVPass> {
-  void runOnOperation() override;
-};
-} // namespace
-
-void LowerVectorToSPIRVPass::runOnOperation() {
-  MLIRContext *context = &getContext();
-  ModuleOp module = getOperation();
-
-  auto targetAttr = spirv::lookupTargetEnvOrDefault(module);
-  std::unique_ptr<ConversionTarget> target =
-      spirv::SPIRVConversionTarget::get(targetAttr);
-
-  SPIRVTypeConverter typeConverter(targetAttr);
-  OwningRewritePatternList patterns;
-  populateVectorToSPIRVPatterns(context, typeConverter, patterns);
-
-  target->addLegalOp<ModuleOp, ModuleTerminatorOp>();
-  target->addLegalOp<FuncOp>();
-
-  if (failed(applyFullConversion(module, *target, std::move(patterns))))
-    return signalPassFailure();
-}
-
-std::unique_ptr<OperationPass<ModuleOp>>
-mlir::createConvertVectorToSPIRVPass() {
-  return std::make_unique<LowerVectorToSPIRVPass>();
-}
diff --git a/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRVPass.cpp b/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRVPass.cpp
new file mode 100644
index 0000000000000..9a4d09f9ad0e6
--- /dev/null
+++ b/mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRVPass.cpp
@@ -0,0 +1,53 @@
+//===- VectorToSPIRVPass.cpp - Vector to SPIR-V Passes --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements a pass to convert Vector dialect to SPIRV dialect.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Conversion/VectorToSPIRV/VectorToSPIRVPass.h"
+
+#include "../PassDetail.h"
+#include "mlir/Conversion/VectorToSPIRV/VectorToSPIRV.h"
+#include "mlir/Dialect/SPIRV/IR/SPIRVDialect.h"
+#include "mlir/Dialect/SPIRV/Transforms/SPIRVConversion.h"
+#include "mlir/Pass/Pass.h"
+#include "mlir/Transforms/DialectConversion.h"
+
+using namespace mlir;
+
+namespace {
+struct LowerVectorToSPIRVPass
+    : public ConvertVectorToSPIRVBase<LowerVectorToSPIRVPass> {
+  void runOnOperation() override;
+};
+} // namespace
+
+void LowerVectorToSPIRVPass::runOnOperation() {
+  MLIRContext *context = &getContext();
+  ModuleOp module = getOperation();
+
+  auto targetAttr = spirv::lookupTargetEnvOrDefault(module);
+  std::unique_ptr<ConversionTarget> target =
+      spirv::SPIRVConversionTarget::get(targetAttr);
+
+  SPIRVTypeConverter typeConverter(targetAttr);
+  OwningRewritePatternList patterns;
+  populateVectorToSPIRVPatterns(context, typeConverter, patterns);
+
+  target->addLegalOp<ModuleOp, ModuleTerminatorOp>();
+  target->addLegalOp<FuncOp>();
+
+  if (failed(applyFullConversion(module, *target, std::move(patterns))))
+    return signalPassFailure();
+}
+
+std::unique_ptr<OperationPass<ModuleOp>>
+mlir::createConvertVectorToSPIRVPass() {
+  return std::make_unique<LowerVectorToSPIRVPass>();
+}
diff --git a/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp b/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
index e8a90acf8830f..d3fa2ccb6dcd2 100644
--- a/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
+++ b/mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
@@ -22,6 +22,7 @@
 #include "mlir/IR/FunctionImplementation.h"
 #include "mlir/IR/OpImplementation.h"
 #include "mlir/IR/PatternMatch.h"
+#include "mlir/IR/TypeUtilities.h"
 #include "llvm/ADT/TypeSwitch.h"
 
 using namespace mlir;
@@ -842,6 +843,23 @@ static void print(OpAsmPrinter &p, GPUModuleOp op) {
                 /*printBlockTerminators=*/false);
 }
 
+//===----------------------------------------------------------------------===//
+// GPUMemcpyOp
+//===----------------------------------------------------------------------===//
+
+static LogicalResult verify(MemcpyOp op) {
+  auto srcType = op.src().getType();
+  auto dstType = op.dst().getType();
+
+  if (getElementTypeOrSelf(srcType) != getElementTypeOrSelf(dstType))
+    return op.emitOpError("arguments have incompatible element type");
+
+  if (failed(verifyCompatibleShape(srcType, dstType)))
+    return op.emitOpError("arguments have incompatible shape");
+
+  return success();
+}
+
 static ParseResult parseAsyncDependencies(
     OpAsmParser &parser, Type &asyncTokenType,
     SmallVectorImpl<OpAsmParser::OperandType> &asyncDependencies) {
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
index 7b1300da1783f..765538ca7a537 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp
@@ -101,13 +101,15 @@ static ParseResult parseCmpOp(OpAsmParser &parser, OperationState &result) {
 
   // The result type is either i1 or a vector type <? x i1> if the inputs are
   // vectors.
-  auto resultType = LLVMType::getInt1Ty(builder.getContext());
+  LLVMType resultType = LLVMIntegerType::get(builder.getContext(), 1);
   auto argType = type.dyn_cast<LLVM::LLVMType>();
   if (!argType)
     return parser.emitError(trailingTypeLoc, "expected LLVM IR dialect type");
-  if (argType.isVectorTy())
+  if (auto vecArgType = argType.dyn_cast<LLVM::LLVMFixedVectorType>())
     resultType =
-        LLVMType::getVectorTy(resultType, argType.getVectorNumElements());
+        LLVMFixedVectorType::get(resultType, vecArgType.getNumElements());
+  assert(!argType.isa<LLVM::LLVMScalableVectorType>() &&
+         "unhandled scalable vector");
 
   result.addTypes({resultType});
   return success();
@@ -118,7 +120,7 @@ static ParseResult parseCmpOp(OpAsmParser &parser, OperationState &result) {
 //===----------------------------------------------------------------------===//
 
 static void printAllocaOp(OpAsmPrinter &p, AllocaOp &op) {
-  auto elemTy = op.getType().cast<LLVM::LLVMType>().getPointerElementTy();
+  auto elemTy = op.getType().cast<LLVM::LLVMPointerType>().getElementType();
 
   auto funcTy = FunctionType::get(op.getContext(), {op.arraySize().getType()},
                                   {op.getType()});
@@ -363,14 +365,11 @@ static void printLoadOp(OpAsmPrinter &p, LoadOp &op) {
 // the resulting type wrapped in MLIR, or nullptr on error.
 static Type getLoadStoreElementType(OpAsmParser &parser, Type type,
                                     llvm::SMLoc trailingTypeLoc) {
-  auto llvmTy = type.dyn_cast<LLVM::LLVMType>();
+  auto llvmTy = type.dyn_cast<LLVM::LLVMPointerType>();
   if (!llvmTy)
-    return parser.emitError(trailingTypeLoc, "expected LLVM IR dialect type"),
-           nullptr;
-  if (!llvmTy.isPointerTy())
     return parser.emitError(trailingTypeLoc, "expected LLVM pointer type"),
            nullptr;
-  return llvmTy.getPointerElementTy();
+  return llvmTy.getElementType();
 }
 
 // <operation> ::= `llvm.load` `volatile` ssa-use attribute-dict? `:` type
@@ -549,7 +548,7 @@ static ParseResult parseInvokeOp(OpAsmParser &parser, OperationState &result) {
 
     LLVM::LLVMType llvmResultType;
     if (funcType.getNumResults() == 0) {
-      llvmResultType = LLVM::LLVMType::getVoidTy(builder.getContext());
+      llvmResultType = LLVM::LLVMVoidType::get(builder.getContext());
     } else {
       llvmResultType = funcType.getResult(0).dyn_cast<LLVM::LLVMType>();
       if (!llvmResultType)
@@ -567,9 +566,8 @@ static ParseResult parseInvokeOp(OpAsmParser &parser, OperationState &result) {
                                 "expected LLVM types as inputs");
     }
 
-    auto llvmFuncType = LLVM::LLVMType::getFunctionTy(llvmResultType, argTypes,
-                                                      /*isVarArg=*/false);
-    auto wrappedFuncType = llvmFuncType.getPointerTo();
+    auto llvmFuncType = LLVM::LLVMFunctionType::get(llvmResultType, argTypes);
+    auto wrappedFuncType = LLVM::LLVMPointerType::get(llvmFuncType);
 
     auto funcArguments = llvm::makeArrayRef(operands).drop_front();
 
@@ -613,7 +611,7 @@ static LogicalResult verify(LandingpadOp op) {
 
   for (unsigned idx = 0, ie = op.getNumOperands(); idx < ie; idx++) {
     value = op.getOperand(idx);
-    bool isFilter = value.getType().cast<LLVMType>().isArrayTy();
+    bool isFilter = value.getType().isa<LLVMArrayType>();
     if (isFilter) {
       // FIXME: Verify filter clauses when arrays are appropriately handled
     } else {
@@ -646,7 +644,7 @@ static void printLandingpadOp(OpAsmPrinter &p, LandingpadOp &op) {
   for (auto value : op.getOperands()) {
     // Similar to llvm - if clause is an array type then it is filter
     // clause else catch clause
-    bool isArrayTy = value.getType().cast<LLVMType>().isArrayTy();
+    bool isArrayTy = value.getType().isa<LLVMArrayType>();
     p << '(' << (isArrayTy ? "filter " : "catch ") << value << " : "
       << value.getType() << ") ";
   }
@@ -728,37 +726,37 @@ static LogicalResult verify(CallOp &op) {
 
     fnType = fn.getType();
   }
-  if (!fnType.isFunctionTy())
+
+  LLVMFunctionType funcType = fnType.dyn_cast<LLVMFunctionType>();
+  if (!funcType)
     return op.emitOpError("callee does not have a functional type: ") << fnType;
 
   // Verify that the operand and result types match the callee.
 
-  if (!fnType.isFunctionVarArg() &&
-      fnType.getFunctionNumParams() != (op.getNumOperands() - isIndirect))
+  if (!funcType.isVarArg() &&
+      funcType.getNumParams() != (op.getNumOperands() - isIndirect))
     return op.emitOpError()
            << "incorrect number of operands ("
            << (op.getNumOperands() - isIndirect)
-           << ") for callee (expecting: " << fnType.getFunctionNumParams()
-           << ")";
+           << ") for callee (expecting: " << funcType.getNumParams() << ")";
 
-  if (fnType.getFunctionNumParams() > (op.getNumOperands() - isIndirect))
+  if (funcType.getNumParams() > (op.getNumOperands() - isIndirect))
     return op.emitOpError() << "incorrect number of operands ("
                             << (op.getNumOperands() - isIndirect)
                             << ") for varargs callee (expecting at least: "
-                            << fnType.getFunctionNumParams() << ")";
+                            << funcType.getNumParams() << ")";
 
-  for (unsigned i = 0, e = fnType.getFunctionNumParams(); i != e; ++i)
-    if (op.getOperand(i + isIndirect).getType() !=
-        fnType.getFunctionParamType(i))
+  for (unsigned i = 0, e = funcType.getNumParams(); i != e; ++i)
+    if (op.getOperand(i + isIndirect).getType() != funcType.getParamType(i))
       return op.emitOpError() << "operand type mismatch for operand " << i
                               << ": " << op.getOperand(i + isIndirect).getType()
-                              << " != " << fnType.getFunctionParamType(i);
+                              << " != " << funcType.getParamType(i);
 
   if (op.getNumResults() &&
-      op.getResult(0).getType() != fnType.getFunctionResultType())
+      op.getResult(0).getType() != funcType.getReturnType())
     return op.emitOpError()
            << "result type mismatch: " << op.getResult(0).getType()
-           << " != " << fnType.getFunctionResultType();
+           << " != " << funcType.getReturnType();
 
   return success();
 }
@@ -829,7 +827,7 @@ static ParseResult parseCallOp(OpAsmParser &parser, OperationState &result) {
     Builder &builder = parser.getBuilder();
     LLVM::LLVMType llvmResultType;
     if (funcType.getNumResults() == 0) {
-      llvmResultType = LLVM::LLVMType::getVoidTy(builder.getContext());
+      llvmResultType = LLVM::LLVMVoidType::get(builder.getContext());
     } else {
       llvmResultType = funcType.getResult(0).dyn_cast<LLVM::LLVMType>();
       if (!llvmResultType)
@@ -846,9 +844,8 @@ static ParseResult parseCallOp(OpAsmParser &parser, OperationState &result) {
                                 "expected LLVM types as inputs");
       argTypes.push_back(argType);
     }
-    auto llvmFuncType = LLVM::LLVMType::getFunctionTy(llvmResultType, argTypes,
-                                                      /*isVarArg=*/false);
-    auto wrappedFuncType = llvmFuncType.getPointerTo();
+    auto llvmFuncType = LLVM::LLVMFunctionType::get(llvmResultType, argTypes);
+    auto wrappedFuncType = LLVM::LLVMPointerType::get(llvmFuncType);
 
     auto funcArguments =
         ArrayRef<OpAsmParser::OperandType>(operands).drop_front();
@@ -875,8 +872,8 @@ static ParseResult parseCallOp(OpAsmParser &parser, OperationState &result) {
 void LLVM::ExtractElementOp::build(OpBuilder &b, OperationState &result,
                                    Value vector, Value position,
                                    ArrayRef<NamedAttribute> attrs) {
-  auto wrappedVectorType = vector.getType().cast<LLVM::LLVMType>();
-  auto llvmType = wrappedVectorType.getVectorElementType();
+  auto vectorType = vector.getType().cast<LLVM::LLVMVectorType>();
+  auto llvmType = vectorType.getElementType();
   build(b, result, llvmType, vector, position);
   result.addAttributes(attrs);
 }
@@ -903,11 +900,11 @@ static ParseResult parseExtractElementOp(OpAsmParser &parser,
       parser.resolveOperand(vector, type, result.operands) ||
       parser.resolveOperand(position, positionType, result.operands))
     return failure();
-  auto wrappedVectorType = type.dyn_cast<LLVM::LLVMType>();
-  if (!wrappedVectorType || !wrappedVectorType.isVectorTy())
+  auto vectorType = type.dyn_cast<LLVM::LLVMVectorType>();
+  if (!vectorType)
     return parser.emitError(
         loc, "expected LLVM IR dialect vector type for operand #1");
-  result.addTypes(wrappedVectorType.getVectorElementType());
+  result.addTypes(vectorType.getElementType());
   return success();
 }
 
@@ -930,8 +927,8 @@ static LLVM::LLVMType getInsertExtractValueElementType(OpAsmParser &parser,
                                                        ArrayAttr positionAttr,
                                                        llvm::SMLoc attributeLoc,
                                                        llvm::SMLoc typeLoc) {
-  auto wrappedContainerType = containerType.dyn_cast<LLVM::LLVMType>();
-  if (!wrappedContainerType)
+  auto llvmType = containerType.dyn_cast<LLVM::LLVMType>();
+  if (!llvmType)
     return parser.emitError(typeLoc, "expected LLVM IR Dialect type"), nullptr;
 
   // Infer the element type from the structure type: iteratively step inside the
@@ -945,26 +942,24 @@ static LLVM::LLVMType getInsertExtractValueElementType(OpAsmParser &parser,
                               "expected an array of integer literals"),
              nullptr;
     int position = positionElementAttr.getInt();
-    if (wrappedContainerType.isArrayTy()) {
-      if (position < 0 || static_cast<unsigned>(position) >=
-                              wrappedContainerType.getArrayNumElements())
+    if (auto arrayType = llvmType.dyn_cast<LLVMArrayType>()) {
+      if (position < 0 ||
+          static_cast<unsigned>(position) >= arrayType.getNumElements())
         return parser.emitError(attributeLoc, "position out of bounds"),
                nullptr;
-      wrappedContainerType = wrappedContainerType.getArrayElementType();
-    } else if (wrappedContainerType.isStructTy()) {
-      if (position < 0 || static_cast<unsigned>(position) >=
-                              wrappedContainerType.getStructNumElements())
+      llvmType = arrayType.getElementType();
+    } else if (auto structType = llvmType.dyn_cast<LLVMStructType>()) {
+      if (position < 0 ||
+          static_cast<unsigned>(position) >= structType.getBody().size())
         return parser.emitError(attributeLoc, "position out of bounds"),
                nullptr;
-      wrappedContainerType =
-          wrappedContainerType.getStructElementType(position);
+      llvmType = structType.getBody()[position];
     } else {
-      return parser.emitError(typeLoc,
-                              "expected wrapped LLVM IR structure/array type"),
+      return parser.emitError(typeLoc, "expected LLVM IR structure/array type"),
              nullptr;
     }
   }
-  return wrappedContainerType;
+  return llvmType;
 }
 
 // <operation> ::= `llvm.extractvalue` ssa-use
@@ -1021,11 +1016,11 @@ static ParseResult parseInsertElementOp(OpAsmParser &parser,
       parser.parseColonType(vectorType))
     return failure();
 
-  auto wrappedVectorType = vectorType.dyn_cast<LLVM::LLVMType>();
-  if (!wrappedVectorType || !wrappedVectorType.isVectorTy())
+  auto llvmVectorType = vectorType.dyn_cast<LLVM::LLVMVectorType>();
+  if (!llvmVectorType)
     return parser.emitError(
         loc, "expected LLVM IR dialect vector type for operand #1");
-  auto valueType = wrappedVectorType.getVectorElementType();
+  Type valueType = llvmVectorType.getElementType();
   if (!valueType)
     return failure();
 
@@ -1145,12 +1140,14 @@ static LogicalResult verify(AddressOfOp op) {
     return op.emitOpError(
         "must reference a global defined by 'llvm.mlir.global' or 'llvm.func'");
 
-  if (global && global.getType().getPointerTo(global.addr_space()) !=
-                    op.getResult().getType())
+  if (global &&
+      LLVM::LLVMPointerType::get(global.getType(), global.addr_space()) !=
+          op.getResult().getType())
     return op.emitOpError(
         "the type must be a pointer to the type of the referenced global");
 
-  if (function && function.getType().getPointerTo() != op.getResult().getType())
+  if (function && LLVM::LLVMPointerType::get(function.getType()) !=
+                      op.getResult().getType())
     return op.emitOpError(
         "the type must be a pointer to the type of the referenced function");
 
@@ -1276,11 +1273,11 @@ static LogicalResult verifyCast(DialectCastOp op, LLVMType llvmType,
     if (vectorType.getRank() != 1)
       return op->emitOpError("only 1-d vector is allowed");
 
-    auto llvmVector = llvmType.dyn_cast<LLVMVectorType>();
-    if (llvmVector.isa<LLVMScalableVectorType>())
+    auto llvmVector = llvmType.dyn_cast<LLVMFixedVectorType>();
+    if (!llvmVector)
       return op->emitOpError("only fixed-sized vector is allowed");
 
-    if (vectorType.getDimSize(0) != llvmVector.getVectorNumElements())
+    if (vectorType.getDimSize(0) != llvmVector.getNumElements())
       return op->emitOpError(
           "invalid cast between vectors with mismatching sizes");
 
@@ -1375,7 +1372,10 @@ static LogicalResult verifyCast(DialectCastOp op, LLVMType llvmType,
                              "be an index-compatible integer");
 
     auto ptrType = structType.getBody()[1].dyn_cast<LLVMPointerType>();
-    if (!ptrType || !ptrType.getPointerElementTy().isIntegerTy(8))
+    auto ptrElementType =
+        ptrType ? ptrType.getElementType().dyn_cast<LLVMIntegerType>()
+                : nullptr;
+    if (!ptrElementType || ptrElementType.getBitWidth() != 8)
       return op->emitOpError("expected second element of a memref descriptor "
                              "to be an !llvm.ptr<i8>");
 
@@ -1476,8 +1476,8 @@ static ParseResult parseGlobalOp(OpAsmParser &parser, OperationState &result) {
   if (types.empty()) {
     if (auto strAttr = value.dyn_cast_or_null<StringAttr>()) {
       MLIRContext *context = parser.getBuilder().getContext();
-      auto arrayType = LLVM::LLVMType::getArrayTy(
-          LLVM::LLVMType::getInt8Ty(context), strAttr.getValue().size());
+      auto arrayType = LLVM::LLVMArrayType::get(
+          LLVM::LLVMIntegerType::get(context, 8), strAttr.getValue().size());
       types.push_back(arrayType);
     } else {
       return parser.emitError(parser.getNameLoc(),
@@ -1503,9 +1503,11 @@ static LogicalResult verify(GlobalOp op) {
     return op.emitOpError("must appear at the module level");
 
   if (auto strAttr = op.getValueOrNull().dyn_cast_or_null<StringAttr>()) {
-    auto type = op.getType();
-    if (!type.isArrayTy() || !type.getArrayElementType().isIntegerTy(8) ||
-        type.getArrayNumElements() != strAttr.getValue().size())
+    auto type = op.getType().dyn_cast<LLVMArrayType>();
+    LLVMIntegerType elementType =
+        type ? type.getElementType().dyn_cast<LLVMIntegerType>() : nullptr;
+    if (!elementType || elementType.getBitWidth() != 8 ||
+        type.getNumElements() != strAttr.getValue().size())
       return op.emitOpError(
           "requires an i8 array type of the length equal to that of the string "
           "attribute");
@@ -1534,9 +1536,9 @@ static LogicalResult verify(GlobalOp op) {
 void LLVM::ShuffleVectorOp::build(OpBuilder &b, OperationState &result,
                                   Value v1, Value v2, ArrayAttr mask,
                                   ArrayRef<NamedAttribute> attrs) {
-  auto wrappedContainerType1 = v1.getType().cast<LLVM::LLVMType>();
-  auto vType = LLVMType::getVectorTy(
-      wrappedContainerType1.getVectorElementType(), mask.size());
+  auto containerType = v1.getType().cast<LLVM::LLVMVectorType>();
+  auto vType =
+      LLVMFixedVectorType::get(containerType.getElementType(), mask.size());
   build(b, result, vType, v1, v2, mask);
   result.addAttributes(attrs);
 }
@@ -1566,12 +1568,12 @@ static ParseResult parseShuffleVectorOp(OpAsmParser &parser,
       parser.resolveOperand(v1, typeV1, result.operands) ||
       parser.resolveOperand(v2, typeV2, result.operands))
     return failure();
-  auto wrappedContainerType1 = typeV1.dyn_cast<LLVM::LLVMType>();
-  if (!wrappedContainerType1 || !wrappedContainerType1.isVectorTy())
+  auto containerType = typeV1.dyn_cast<LLVM::LLVMVectorType>();
+  if (!containerType)
     return parser.emitError(
         loc, "expected LLVM IR dialect vector type for operand #1");
-  auto vType = LLVMType::getVectorTy(
-      wrappedContainerType1.getVectorElementType(), maskAttr.size());
+  auto vType =
+      LLVMFixedVectorType::get(containerType.getElementType(), maskAttr.size());
   result.addTypes(vType);
   return success();
 }
@@ -1588,9 +1590,9 @@ Block *LLVMFuncOp::addEntryBlock() {
   auto *entry = new Block;
   push_back(entry);
 
-  LLVMType type = getType();
-  for (unsigned i = 0, e = type.getFunctionNumParams(); i < e; ++i)
-    entry->addArgument(type.getFunctionParamType(i));
+  LLVMFunctionType type = getType();
+  for (unsigned i = 0, e = type.getNumParams(); i < e; ++i)
+    entry->addArgument(type.getParamType(i));
   return entry;
 }
 
@@ -1608,7 +1610,7 @@ void LLVMFuncOp::build(OpBuilder &builder, OperationState &result,
   if (argAttrs.empty())
     return;
 
-  unsigned numInputs = type.getFunctionNumParams();
+  unsigned numInputs = type.cast<LLVMFunctionType>().getNumParams();
   assert(numInputs == argAttrs.size() &&
          "expected as many argument attribute lists as arguments");
   SmallString<8> argAttrName;
@@ -1643,15 +1645,15 @@ static Type buildLLVMFunctionType(OpAsmParser &parser, llvm::SMLoc loc,
   }
 
   // No output is denoted as "void" in LLVM type system.
-  LLVMType llvmOutput = outputs.empty() ? LLVMType::getVoidTy(b.getContext())
+  LLVMType llvmOutput = outputs.empty() ? LLVMVoidType::get(b.getContext())
                                         : outputs.front().dyn_cast<LLVMType>();
   if (!llvmOutput) {
     parser.emitError(loc, "failed to construct function type: expected LLVM "
                           "type for function results");
     return {};
   }
-  return LLVMType::getFunctionTy(llvmOutput, llvmInputs,
-                                 variadicFlag.isVariadic());
+  return LLVMFunctionType::get(llvmOutput, llvmInputs,
+                               variadicFlag.isVariadic());
 }
 
 // Parses an LLVM function.
@@ -1711,15 +1713,15 @@ static void printLLVMFuncOp(OpAsmPrinter &p, LLVMFuncOp op) {
     p << stringifyLinkage(op.linkage()) << ' ';
   p.printSymbolName(op.getName());
 
-  LLVMType fnType = op.getType();
+  LLVMFunctionType fnType = op.getType();
   SmallVector<Type, 8> argTypes;
   SmallVector<Type, 1> resTypes;
-  argTypes.reserve(fnType.getFunctionNumParams());
-  for (unsigned i = 0, e = fnType.getFunctionNumParams(); i < e; ++i)
-    argTypes.push_back(fnType.getFunctionParamType(i));
+  argTypes.reserve(fnType.getNumParams());
+  for (unsigned i = 0, e = fnType.getNumParams(); i < e; ++i)
+    argTypes.push_back(fnType.getParamType(i));
 
-  LLVMType returnType = fnType.getFunctionResultType();
-  if (!returnType.isVoidTy())
+  LLVMType returnType = fnType.getReturnType();
+  if (!returnType.isa<LLVMVoidType>())
     resTypes.push_back(returnType);
 
   impl::printFunctionSignature(p, op, argTypes, op.isVarArg(), resTypes);
@@ -1737,8 +1739,8 @@ static void printLLVMFuncOp(OpAsmPrinter &p, LLVMFuncOp op) {
 // attribute is present.  This can check for preconditions of the
 // getNumArguments hook not failing.
 LogicalResult LLVMFuncOp::verifyType() {
-  auto llvmType = getTypeAttr().getValue().dyn_cast_or_null<LLVMType>();
-  if (!llvmType || !llvmType.isFunctionTy())
+  auto llvmType = getTypeAttr().getValue().dyn_cast_or_null<LLVMFunctionType>();
+  if (!llvmType)
     return emitOpError("requires '" + getTypeAttrName() +
                        "' attribute of wrapped LLVM function type");
 
@@ -1747,9 +1749,7 @@ LogicalResult LLVMFuncOp::verifyType() {
 
 // Hook for OpTrait::FunctionLike, returns the number of function arguments.
 // Depends on the type attribute being correct as checked by verifyType
-unsigned LLVMFuncOp::getNumFuncArguments() {
-  return getType().getFunctionNumParams();
-}
+unsigned LLVMFuncOp::getNumFuncArguments() { return getType().getNumParams(); }
 
 // Hook for OpTrait::FunctionLike, returns the number of function results.
 // Depends on the type attribute being correct as checked by verifyType
@@ -1759,7 +1759,7 @@ unsigned LLVMFuncOp::getNumFuncResults() {
   // If we modeled a void return as one result, then it would be possible to
   // attach an MLIR result attribute to it, and it isn't clear what semantics we
   // would assign to that.
-  if (getType().getFunctionResultType().isVoidTy())
+  if (getType().getReturnType().isa<LLVMVoidType>())
     return 0;
   return 1;
 }
@@ -1788,7 +1788,7 @@ static LogicalResult verify(LLVMFuncOp op) {
   if (op.isVarArg())
     return op.emitOpError("only external functions can be variadic");
 
-  unsigned numArguments = op.getType().getFunctionNumParams();
+  unsigned numArguments = op.getType().getNumParams();
   Block &entryBlock = op.front();
   for (unsigned i = 0; i < numArguments; ++i) {
     Type argType = entryBlock.getArgument(i).getType();
@@ -1796,7 +1796,7 @@ static LogicalResult verify(LLVMFuncOp op) {
     if (!argLLVMType)
       return op.emitOpError("entry block argument #")
              << i << " is not of LLVM type";
-    if (op.getType().getFunctionParamType(i) != argLLVMType)
+    if (op.getType().getParamType(i) != argLLVMType)
       return op.emitOpError("the type of entry block argument #")
              << i << " does not match the function signature";
   }
@@ -1896,7 +1896,8 @@ static ParseResult parseAtomicRMWOp(OpAsmParser &parser,
       parseAtomicOrdering(parser, result, "ordering") ||
       parser.parseOptionalAttrDict(result.attributes) ||
       parser.parseColonType(type) ||
-      parser.resolveOperand(ptr, type.getPointerTo(), result.operands) ||
+      parser.resolveOperand(ptr, LLVM::LLVMPointerType::get(type),
+                            result.operands) ||
       parser.resolveOperand(val, type, result.operands))
     return failure();
 
@@ -1905,9 +1906,9 @@ static ParseResult parseAtomicRMWOp(OpAsmParser &parser,
 }
 
 static LogicalResult verify(AtomicRMWOp op) {
-  auto ptrType = op.ptr().getType().cast<LLVM::LLVMType>();
+  auto ptrType = op.ptr().getType().cast<LLVM::LLVMPointerType>();
   auto valType = op.val().getType().cast<LLVM::LLVMType>();
-  if (valType != ptrType.getPointerElementTy())
+  if (valType != ptrType.getElementType())
     return op.emitOpError("expected LLVM IR element type for operand #0 to "
                           "match type for operand #1");
   auto resType = op.res().getType().cast<LLVM::LLVMType>();
@@ -1915,17 +1916,21 @@ static LogicalResult verify(AtomicRMWOp op) {
     return op.emitOpError(
         "expected LLVM IR result type to match type for operand #1");
   if (op.bin_op() == AtomicBinOp::fadd || op.bin_op() == AtomicBinOp::fsub) {
-    if (!valType.isFloatingPointTy())
+    if (!mlir::LLVM::isCompatibleFloatingPointType(valType))
       return op.emitOpError("expected LLVM IR floating point type");
   } else if (op.bin_op() == AtomicBinOp::xchg) {
-    if (!valType.isIntegerTy(8) && !valType.isIntegerTy(16) &&
-        !valType.isIntegerTy(32) && !valType.isIntegerTy(64) &&
-        !valType.isBFloatTy() && !valType.isHalfTy() && !valType.isFloatTy() &&
-        !valType.isDoubleTy())
+    auto intType = valType.dyn_cast<LLVMIntegerType>();
+    unsigned intBitWidth = intType ? intType.getBitWidth() : 0;
+    if (intBitWidth != 8 && intBitWidth != 16 && intBitWidth != 32 &&
+        intBitWidth != 64 && !valType.isa<LLVMBFloatType>() &&
+        !valType.isa<LLVMHalfType>() && !valType.isa<LLVMFloatType>() &&
+        !valType.isa<LLVMDoubleType>())
       return op.emitOpError("unexpected LLVM IR type for 'xchg' bin_op");
   } else {
-    if (!valType.isIntegerTy(8) && !valType.isIntegerTy(16) &&
-        !valType.isIntegerTy(32) && !valType.isIntegerTy(64))
+    auto intType = valType.dyn_cast<LLVMIntegerType>();
+    unsigned intBitWidth = intType ? intType.getBitWidth() : 0;
+    if (intBitWidth != 8 && intBitWidth != 16 && intBitWidth != 32 &&
+        intBitWidth != 64)
       return op.emitOpError("expected LLVM IR integer type");
   }
   return success();
@@ -1958,31 +1963,35 @@ static ParseResult parseAtomicCmpXchgOp(OpAsmParser &parser,
       parseAtomicOrdering(parser, result, "failure_ordering") ||
       parser.parseOptionalAttrDict(result.attributes) ||
       parser.parseColonType(type) ||
-      parser.resolveOperand(ptr, type.getPointerTo(), result.operands) ||
+      parser.resolveOperand(ptr, LLVM::LLVMPointerType::get(type),
+                            result.operands) ||
       parser.resolveOperand(cmp, type, result.operands) ||
       parser.resolveOperand(val, type, result.operands))
     return failure();
 
-  auto boolType = LLVMType::getInt1Ty(builder.getContext());
-  auto resultType = LLVMType::getStructTy(type, boolType);
+  auto boolType = LLVMIntegerType::get(builder.getContext(), 1);
+  auto resultType =
+      LLVMStructType::getLiteral(builder.getContext(), {type, boolType});
   result.addTypes(resultType);
 
   return success();
 }
 
 static LogicalResult verify(AtomicCmpXchgOp op) {
-  auto ptrType = op.ptr().getType().cast<LLVM::LLVMType>();
-  if (!ptrType.isPointerTy())
+  auto ptrType = op.ptr().getType().cast<LLVM::LLVMPointerType>();
+  if (!ptrType)
     return op.emitOpError("expected LLVM IR pointer type for operand #0");
   auto cmpType = op.cmp().getType().cast<LLVM::LLVMType>();
   auto valType = op.val().getType().cast<LLVM::LLVMType>();
-  if (cmpType != ptrType.getPointerElementTy() || cmpType != valType)
+  if (cmpType != ptrType.getElementType() || cmpType != valType)
     return op.emitOpError("expected LLVM IR element type for operand #0 to "
                           "match type for all other operands");
-  if (!valType.isPointerTy() && !valType.isIntegerTy(8) &&
-      !valType.isIntegerTy(16) && !valType.isIntegerTy(32) &&
-      !valType.isIntegerTy(64) && !valType.isBFloatTy() &&
-      !valType.isHalfTy() && !valType.isFloatTy() && !valType.isDoubleTy())
+  auto intType = valType.dyn_cast<LLVMIntegerType>();
+  unsigned intBitWidth = intType ? intType.getBitWidth() : 0;
+  if (!valType.isa<LLVMPointerType>() && intBitWidth != 8 &&
+      intBitWidth != 16 && intBitWidth != 32 && intBitWidth != 64 &&
+      !valType.isa<LLVMBFloatType>() && !valType.isa<LLVMHalfType>() &&
+      !valType.isa<LLVMFloatType>() && !valType.isa<LLVMDoubleType>())
     return op.emitOpError("unexpected LLVM IR type");
   if (op.success_ordering() < AtomicOrdering::monotonic ||
       op.failure_ordering() < AtomicOrdering::monotonic)
@@ -2150,8 +2159,8 @@ Value mlir::LLVM::createGlobalString(Location loc, OpBuilder &builder,
   // Create the global at the entry of the module.
   OpBuilder moduleBuilder(module.getBodyRegion());
   MLIRContext *ctx = builder.getContext();
-  auto type =
-      LLVM::LLVMType::getArrayTy(LLVM::LLVMType::getInt8Ty(ctx), value.size());
+  auto type = LLVM::LLVMArrayType::get(LLVM::LLVMIntegerType::get(ctx, 8),
+                                       value.size());
   auto global = moduleBuilder.create<LLVM::GlobalOp>(
       loc, type, /*isConstant=*/true, linkage, name,
       builder.getStringAttr(value));
@@ -2159,10 +2168,11 @@ Value mlir::LLVM::createGlobalString(Location loc, OpBuilder &builder,
   // Get the pointer to the first character in the global string.
   Value globalPtr = builder.create<LLVM::AddressOfOp>(loc, global);
   Value cst0 = builder.create<LLVM::ConstantOp>(
-      loc, LLVM::LLVMType::getInt64Ty(ctx),
+      loc, LLVM::LLVMIntegerType::get(ctx, 64),
       builder.getIntegerAttr(builder.getIndexType(), 0));
-  return builder.create<LLVM::GEPOp>(loc, LLVM::LLVMType::getInt8PtrTy(ctx),
-                                     globalPtr, ValueRange{cst0, cst0});
+  return builder.create<LLVM::GEPOp>(
+      loc, LLVM::LLVMPointerType::get(LLVMIntegerType::get(ctx, 8)), globalPtr,
+      ValueRange{cst0, cst0});
 }
 
 bool mlir::LLVM::satisfiesLLVMModule(Operation *op) {
diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
index a89287b764e5d..3d75245a1fb36 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp
@@ -36,227 +36,9 @@ LLVMDialect &LLVMType::getDialect() {
   return static_cast<LLVMDialect &>(Type::getDialect());
 }
 
-//----------------------------------------------------------------------------//
-// Misc type utilities.
-
-llvm::TypeSize LLVMType::getPrimitiveSizeInBits() {
-  return llvm::TypeSwitch<LLVMType, llvm::TypeSize>(*this)
-      .Case<LLVMHalfType, LLVMBFloatType>(
-          [](LLVMType) { return llvm::TypeSize::Fixed(16); })
-      .Case<LLVMFloatType>([](LLVMType) { return llvm::TypeSize::Fixed(32); })
-      .Case<LLVMDoubleType, LLVMX86MMXType>(
-          [](LLVMType) { return llvm::TypeSize::Fixed(64); })
-      .Case<LLVMIntegerType>([](LLVMIntegerType intTy) {
-        return llvm::TypeSize::Fixed(intTy.getBitWidth());
-      })
-      .Case<LLVMX86FP80Type>([](LLVMType) { return llvm::TypeSize::Fixed(80); })
-      .Case<LLVMPPCFP128Type, LLVMFP128Type>(
-          [](LLVMType) { return llvm::TypeSize::Fixed(128); })
-      .Case<LLVMVectorType>([](LLVMVectorType t) {
-        llvm::TypeSize elementSize =
-            t.getElementType().getPrimitiveSizeInBits();
-        llvm::ElementCount elementCount = t.getElementCount();
-        assert(!elementSize.isScalable() &&
-               "vector type should have fixed-width elements");
-        return llvm::TypeSize(elementSize.getFixedSize() *
-                                  elementCount.getKnownMinValue(),
-                              elementCount.isScalable());
-      })
-      .Default([](LLVMType ty) {
-        assert((ty.isa<LLVMVoidType, LLVMLabelType, LLVMMetadataType,
-                       LLVMTokenType, LLVMStructType, LLVMArrayType,
-                       LLVMPointerType, LLVMFunctionType>()) &&
-               "unexpected missing support for primitive type");
-        return llvm::TypeSize::Fixed(0);
-      });
-}
-
-//----------------------------------------------------------------------------//
-// Integer type utilities.
-
-bool LLVMType::isIntegerTy(unsigned bitwidth) {
-  if (auto intType = dyn_cast<LLVMIntegerType>())
-    return intType.getBitWidth() == bitwidth;
-  return false;
-}
-unsigned LLVMType::getIntegerBitWidth() {
-  return cast<LLVMIntegerType>().getBitWidth();
-}
-
-LLVMType LLVMType::getArrayElementType() {
-  return cast<LLVMArrayType>().getElementType();
-}
-
-//----------------------------------------------------------------------------//
-// Array type utilities.
-
-unsigned LLVMType::getArrayNumElements() {
-  return cast<LLVMArrayType>().getNumElements();
-}
-
-bool LLVMType::isArrayTy() { return isa<LLVMArrayType>(); }
-
-//----------------------------------------------------------------------------//
-// Vector type utilities.
-
-LLVMType LLVMType::getVectorElementType() {
-  return cast<LLVMVectorType>().getElementType();
-}
-
-unsigned LLVMType::getVectorNumElements() {
-  return cast<LLVMFixedVectorType>().getNumElements();
-}
-llvm::ElementCount LLVMType::getVectorElementCount() {
-  return cast<LLVMVectorType>().getElementCount();
-}
-
-bool LLVMType::isVectorTy() { return isa<LLVMVectorType>(); }
-
-//----------------------------------------------------------------------------//
-// Function type utilities.
-
-LLVMType LLVMType::getFunctionParamType(unsigned argIdx) {
-  return cast<LLVMFunctionType>().getParamType(argIdx);
-}
-
-unsigned LLVMType::getFunctionNumParams() {
-  return cast<LLVMFunctionType>().getNumParams();
-}
-
-LLVMType LLVMType::getFunctionResultType() {
-  return cast<LLVMFunctionType>().getReturnType();
-}
-
-bool LLVMType::isFunctionTy() { return isa<LLVMFunctionType>(); }
-
-bool LLVMType::isFunctionVarArg() {
-  return cast<LLVMFunctionType>().isVarArg();
-}
-
-//----------------------------------------------------------------------------//
-// Pointer type utilities.
-
-LLVMType LLVMType::getPointerTo(unsigned addrSpace) {
-  return LLVMPointerType::get(*this, addrSpace);
-}
-
-LLVMType LLVMType::getPointerElementTy() {
-  return cast<LLVMPointerType>().getElementType();
-}
-
-bool LLVMType::isPointerTy() { return isa<LLVMPointerType>(); }
-
-//----------------------------------------------------------------------------//
-// Struct type utilities.
-
-LLVMType LLVMType::getStructElementType(unsigned i) {
-  return cast<LLVMStructType>().getBody()[i];
-}
-
-unsigned LLVMType::getStructNumElements() {
-  return cast<LLVMStructType>().getBody().size();
-}
-
-bool LLVMType::isStructTy() { return isa<LLVMStructType>(); }
-
-//----------------------------------------------------------------------------//
-// Utilities used to generate floating point types.
-
-LLVMType LLVMType::getDoubleTy(MLIRContext *context) {
-  return LLVMDoubleType::get(context);
-}
-
-LLVMType LLVMType::getFloatTy(MLIRContext *context) {
-  return LLVMFloatType::get(context);
-}
-
-LLVMType LLVMType::getBFloatTy(MLIRContext *context) {
-  return LLVMBFloatType::get(context);
-}
-
-LLVMType LLVMType::getHalfTy(MLIRContext *context) {
-  return LLVMHalfType::get(context);
-}
-
-LLVMType LLVMType::getFP128Ty(MLIRContext *context) {
-  return LLVMFP128Type::get(context);
-}
-
-LLVMType LLVMType::getX86_FP80Ty(MLIRContext *context) {
-  return LLVMX86FP80Type::get(context);
-}
-
-//----------------------------------------------------------------------------//
-// Utilities used to generate integer types.
-
-LLVMType LLVMType::getIntNTy(MLIRContext *context, unsigned numBits) {
-  return LLVMIntegerType::get(context, numBits);
-}
-
-//----------------------------------------------------------------------------//
-// Utilities used to generate other miscellaneous types.
-
-LLVMType LLVMType::getArrayTy(LLVMType elementType, uint64_t numElements) {
-  return LLVMArrayType::get(elementType, numElements);
-}
-
-LLVMType LLVMType::getFunctionTy(LLVMType result, ArrayRef<LLVMType> params,
-                                 bool isVarArg) {
-  return LLVMFunctionType::get(result, params, isVarArg);
-}
-
-LLVMType LLVMType::getStructTy(MLIRContext *context,
-                               ArrayRef<LLVMType> elements, bool isPacked) {
-  return LLVMStructType::getLiteral(context, elements, isPacked);
-}
-
-LLVMType LLVMType::getVectorTy(LLVMType elementType, unsigned numElements) {
-  return LLVMFixedVectorType::get(elementType, numElements);
-}
-
-//----------------------------------------------------------------------------//
-// Void type utilities.
-
-LLVMType LLVMType::getVoidTy(MLIRContext *context) {
-  return LLVMVoidType::get(context);
-}
-
-bool LLVMType::isVoidTy() { return isa<LLVMVoidType>(); }
-
-//----------------------------------------------------------------------------//
-// Creation and setting of LLVM's identified struct types
-
-LLVMType LLVMType::createStructTy(MLIRContext *context,
-                                  ArrayRef<LLVMType> elements,
-                                  Optional<StringRef> name, bool isPacked) {
-  assert(name.hasValue() &&
-         "identified structs with no identifier not supported");
-  StringRef stringNameBase = name.getValueOr("");
-  std::string stringName = stringNameBase.str();
-  unsigned counter = 0;
-  do {
-    auto type = LLVMStructType::getIdentified(context, stringName);
-    if (type.isInitialized() || failed(type.setBody(elements, isPacked))) {
-      counter += 1;
-      stringName =
-          (Twine(stringNameBase) + "." + std::to_string(counter)).str();
-      continue;
-    }
-    return type;
-  } while (true);
-}
-
-LLVMType LLVMType::setStructTyBody(LLVMType structType,
-                                   ArrayRef<LLVMType> elements, bool isPacked) {
-  LogicalResult couldSet =
-      structType.cast<LLVMStructType>().setBody(elements, isPacked);
-  assert(succeeded(couldSet) && "failed to set the body");
-  (void)couldSet;
-  return structType;
-}
-
 //===----------------------------------------------------------------------===//
 // Array type.
+//===----------------------------------------------------------------------===//
 
 bool LLVMArrayType::isValidElementType(LLVMType type) {
   return !type.isa<LLVMVoidType, LLVMLabelType, LLVMMetadataType,
@@ -288,6 +70,7 @@ LLVMArrayType::verifyConstructionInvariants(Location loc, LLVMType elementType,
 
 //===----------------------------------------------------------------------===//
 // Function type.
+//===----------------------------------------------------------------------===//
 
 bool LLVMFunctionType::isValidArgumentType(LLVMType type) {
   return !type.isa<LLVMVoidType, LLVMFunctionType>();
@@ -343,6 +126,7 @@ LogicalResult LLVMFunctionType::verifyConstructionInvariants(
 
 //===----------------------------------------------------------------------===//
 // Integer type.
+//===----------------------------------------------------------------------===//
 
 LLVMIntegerType LLVMIntegerType::get(MLIRContext *ctx, unsigned bitwidth) {
   return Base::get(ctx, bitwidth);
@@ -364,6 +148,7 @@ LogicalResult LLVMIntegerType::verifyConstructionInvariants(Location loc,
 
 //===----------------------------------------------------------------------===//
 // Pointer type.
+//===----------------------------------------------------------------------===//
 
 bool LLVMPointerType::isValidElementType(LLVMType type) {
   return !type.isa<LLVMVoidType, LLVMTokenType, LLVMMetadataType,
@@ -394,6 +179,7 @@ LogicalResult LLVMPointerType::verifyConstructionInvariants(Location loc,
 
 //===----------------------------------------------------------------------===//
 // Struct type.
+//===----------------------------------------------------------------------===//
 
 bool LLVMStructType::isValidElementType(LLVMType type) {
   return !type.isa<LLVMVoidType, LLVMLabelType, LLVMMetadataType,
@@ -410,6 +196,23 @@ LLVMStructType LLVMStructType::getIdentifiedChecked(Location loc,
   return Base::getChecked(loc, name, /*opaque=*/false);
 }
 
+LLVMStructType LLVMStructType::getNewIdentified(MLIRContext *context,
+                                                StringRef name,
+                                                ArrayRef<LLVMType> elements,
+                                                bool isPacked) {
+  std::string stringName = name.str();
+  unsigned counter = 0;
+  do {
+    auto type = LLVMStructType::getIdentified(context, stringName);
+    if (type.isInitialized() || failed(type.setBody(elements, isPacked))) {
+      counter += 1;
+      stringName = (Twine(name) + "." + std::to_string(counter)).str();
+      continue;
+    }
+    return type;
+  } while (true);
+}
+
 LLVMStructType LLVMStructType::getLiteral(MLIRContext *context,
                                           ArrayRef<LLVMType> types,
                                           bool isPacked) {
@@ -467,10 +270,11 @@ LLVMStructType::verifyConstructionInvariants(Location loc,
 
 //===----------------------------------------------------------------------===//
 // Vector types.
+//===----------------------------------------------------------------------===//
 
 bool LLVMVectorType::isValidElementType(LLVMType type) {
   return type.isa<LLVMIntegerType, LLVMPointerType>() ||
-         type.isFloatingPointTy();
+         mlir::LLVM::isCompatibleFloatingPointType(type);
 }
 
 /// Support type casting functionality.
@@ -536,3 +340,42 @@ LLVMScalableVectorType::getChecked(Location loc, LLVMType elementType,
 unsigned LLVMScalableVectorType::getMinNumElements() {
   return getImpl()->numElements;
 }
+
+//===----------------------------------------------------------------------===//
+// Utility functions.
+//===----------------------------------------------------------------------===//
+
+llvm::TypeSize mlir::LLVM::getPrimitiveTypeSizeInBits(Type type) {
+  assert(isCompatibleType(type) &&
+         "expected a type compatible with the LLVM dialect");
+
+  return llvm::TypeSwitch<Type, llvm::TypeSize>(type)
+      .Case<LLVMHalfType, LLVMBFloatType>(
+          [](LLVMType) { return llvm::TypeSize::Fixed(16); })
+      .Case<LLVMFloatType>([](LLVMType) { return llvm::TypeSize::Fixed(32); })
+      .Case<LLVMDoubleType, LLVMX86MMXType>(
+          [](LLVMType) { return llvm::TypeSize::Fixed(64); })
+      .Case<LLVMIntegerType>([](LLVMIntegerType intTy) {
+        return llvm::TypeSize::Fixed(intTy.getBitWidth());
+      })
+      .Case<LLVMX86FP80Type>([](LLVMType) { return llvm::TypeSize::Fixed(80); })
+      .Case<LLVMPPCFP128Type, LLVMFP128Type>(
+          [](LLVMType) { return llvm::TypeSize::Fixed(128); })
+      .Case<LLVMVectorType>([](LLVMVectorType t) {
+        llvm::TypeSize elementSize =
+            getPrimitiveTypeSizeInBits(t.getElementType());
+        llvm::ElementCount elementCount = t.getElementCount();
+        assert(!elementSize.isScalable() &&
+               "vector type should have fixed-width elements");
+        return llvm::TypeSize(elementSize.getFixedSize() *
+                                  elementCount.getKnownMinValue(),
+                              elementCount.isScalable());
+      })
+      .Default([](Type ty) {
+        assert((ty.isa<LLVMVoidType, LLVMLabelType, LLVMMetadataType,
+                       LLVMTokenType, LLVMStructType, LLVMArrayType,
+                       LLVMPointerType, LLVMFunctionType>()) &&
+               "unexpected missing support for primitive type");
+        return llvm::TypeSize::Fixed(0);
+      });
+}
diff --git a/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
index 707ff7c1b089b..c2f689be493aa 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp
@@ -57,12 +57,14 @@ static ParseResult parseNVVMShflSyncBflyOp(OpAsmParser &parser,
   for (auto &attr : result.attributes) {
     if (attr.first != "return_value_and_is_valid")
       continue;
-    if (type.isStructTy() && type.getStructNumElements() > 0)
-      type = type.getStructElementType(0);
+    auto structType = type.dyn_cast<LLVM::LLVMStructType>();
+    if (structType && !structType.getBody().empty())
+      type = structType.getBody()[0];
     break;
   }
 
-  auto int32Ty = LLVM::LLVMType::getInt32Ty(parser.getBuilder().getContext());
+  auto int32Ty =
+      LLVM::LLVMIntegerType::get(parser.getBuilder().getContext(), 32);
   return parser.resolveOperands(ops, {int32Ty, type, int32Ty, int32Ty},
                                 parser.getNameLoc(), result.operands);
 }
@@ -71,8 +73,8 @@ static ParseResult parseNVVMShflSyncBflyOp(OpAsmParser &parser,
 static ParseResult parseNVVMVoteBallotOp(OpAsmParser &parser,
                                          OperationState &result) {
   MLIRContext *context = parser.getBuilder().getContext();
-  auto int32Ty = LLVM::LLVMType::getInt32Ty(context);
-  auto int1Ty = LLVM::LLVMType::getInt1Ty(context);
+  auto int32Ty = LLVM::LLVMIntegerType::get(context, 32);
+  auto int1Ty = LLVM::LLVMIntegerType::get(context, 1);
 
   SmallVector<OpAsmParser::OperandType, 8> ops;
   Type type;
@@ -86,12 +88,12 @@ static ParseResult parseNVVMVoteBallotOp(OpAsmParser &parser,
 
 static LogicalResult verify(MmaOp op) {
   MLIRContext *context = op.getContext();
-  auto f16Ty = LLVM::LLVMType::getHalfTy(context);
-  auto f16x2Ty = LLVM::LLVMType::getVectorTy(f16Ty, 2);
-  auto f32Ty = LLVM::LLVMType::getFloatTy(context);
-  auto f16x2x4StructTy = LLVM::LLVMType::getStructTy(
+  auto f16Ty = LLVM::LLVMHalfType::get(context);
+  auto f16x2Ty = LLVM::LLVMFixedVectorType::get(f16Ty, 2);
+  auto f32Ty = LLVM::LLVMFloatType::get(context);
+  auto f16x2x4StructTy = LLVM::LLVMStructType::getLiteral(
       context, {f16x2Ty, f16x2Ty, f16x2Ty, f16x2Ty});
-  auto f32x8StructTy = LLVM::LLVMType::getStructTy(
+  auto f32x8StructTy = LLVM::LLVMStructType::getLiteral(
       context, {f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty, f32Ty});
 
   SmallVector<Type, 12> operand_types(op.getOperandTypes().begin(),
diff --git a/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp b/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
index 8d0c96ce2aa1a..f50c49f03a079 100644
--- a/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
+++ b/mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp
@@ -46,9 +46,9 @@ static ParseResult parseROCDLMubufLoadOp(OpAsmParser &parser,
     return failure();
 
   MLIRContext *context = parser.getBuilder().getContext();
-  auto int32Ty = LLVM::LLVMType::getInt32Ty(context);
-  auto int1Ty = LLVM::LLVMType::getInt1Ty(context);
-  auto i32x4Ty = LLVM::LLVMType::getVectorTy(int32Ty, 4);
+  auto int32Ty = LLVM::LLVMIntegerType::get(context, 32);
+  auto int1Ty = LLVM::LLVMIntegerType::get(context, 1);
+  auto i32x4Ty = LLVM::LLVMFixedVectorType::get(int32Ty, 4);
   return parser.resolveOperands(ops,
                                 {i32x4Ty, int32Ty, int32Ty, int1Ty, int1Ty},
                                 parser.getNameLoc(), result.operands);
@@ -65,9 +65,9 @@ static ParseResult parseROCDLMubufStoreOp(OpAsmParser &parser,
     return failure();
 
   MLIRContext *context = parser.getBuilder().getContext();
-  auto int32Ty = LLVM::LLVMType::getInt32Ty(context);
-  auto int1Ty = LLVM::LLVMType::getInt1Ty(context);
-  auto i32x4Ty = LLVM::LLVMType::getVectorTy(int32Ty, 4);
+  auto int32Ty = LLVM::LLVMIntegerType::get(context, 32);
+  auto int1Ty = LLVM::LLVMIntegerType::get(context, 1);
+  auto i32x4Ty = LLVM::LLVMFixedVectorType::get(int32Ty, 4);
 
   if (parser.resolveOperands(ops,
                              {type, i32x4Ty, int32Ty, int32Ty, int1Ty, int1Ty},
diff --git a/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp b/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
index ca2d16e8de863..1042930b1ef7c 100644
--- a/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
+++ b/mlir/lib/Dialect/Linalg/Analysis/DependenceAnalysis.cpp
@@ -13,6 +13,7 @@
 #include "mlir/Dialect/Linalg/Analysis/DependenceAnalysis.h"
 #include "mlir/Dialect/Linalg/IR/LinalgOps.h"
 #include "mlir/Dialect/StandardOps/IR/Ops.h"
+#include "mlir/IR/BuiltinOps.h"
 
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
@@ -113,15 +114,16 @@ LinalgDependenceGraph::LinalgDependenceGraph(Aliases &aliases,
 }
 
 void LinalgDependenceGraph::addDependenceElem(DependenceType dt,
-                                              LinalgOpView indexingOpView,
-                                              LinalgOpView dependentOpView) {
+                                              OpOperand *indexingOpView,
+                                              OpOperand *dependentOpView) {
   LLVM_DEBUG(dbgs() << "\nAdd dep type " << getDependenceTypeStr(dt) << ":\t ("
-                    << *indexingOpView.op << ", " << indexingOpView.operandIndex
-                    << ") -> \n\t\t(" << *dependentOpView.op << ", "
-                    << dependentOpView.operandIndex << ")");
-  dependencesFromGraphs[dt][indexingOpView.op].push_back(
+                    << indexingOpView->get() << " @"
+                    << indexingOpView->getOperandNumber() << ") -> \n\t\t("
+                    << dependentOpView->get() << " @"
+                    << dependentOpView->getOperandNumber() << ")");
+  dependencesFromGraphs[dt][indexingOpView->getOwner()].push_back(
       LinalgDependenceGraphElem{dependentOpView, indexingOpView, dt});
-  dependencesIntoGraphs[dt][dependentOpView.op].push_back(
+  dependencesIntoGraphs[dt][dependentOpView->getOwner()].push_back(
       LinalgDependenceGraphElem{indexingOpView, dependentOpView, dt});
 }
 
@@ -156,57 +158,25 @@ LinalgDependenceGraph::getDependencesInto(
 }
 
 void LinalgDependenceGraph::addDependencesBetween(LinalgOp src, LinalgOp dst) {
-  for (auto srcView : llvm::enumerate(src.getOutputBuffers())) { // W
-    unsigned srcIndex =
-        src.getOperandIndexForOutputIndex(srcView.index()).getValue();
+  for (OpOperand *srcOpOperand : src.getOutputBuffersOpOperands()) { // W
     // RAW graph
-    for (auto dstView : llvm::enumerate(dst.getInputBuffers())) { // R
-      if (aliases.alias(srcView.value(),
-                        dstView.value())) { // if alias, fill RAW
-        unsigned dstIndex =
-            dst.getOperandIndexForInputIndex(dstView.index()).getValue();
-        addDependenceElem(DependenceType::RAW,
-                          LinalgOpView{src.getOperation(), srcIndex},
-                          LinalgOpView{dst.getOperation(), dstIndex});
-      }
-    }
+    for (OpOperand *dstOpOperand : dst.getInputBuffersOpOperands()) // R
+      if (aliases.alias(srcOpOperand->get(), dstOpOperand->get()))  // RAW alias
+        addDependenceElem(DependenceType::RAW, srcOpOperand, dstOpOperand);
     // WAW graph
-    for (auto dstView : llvm::enumerate(dst.getOutputBuffers())) { // W
-      if (aliases.alias(srcView.value(),
-                        dstView.value())) { // if alias, fill WAW
-        unsigned dstIndex =
-            dst.getOperandIndexForOutputIndex(dstView.index()).getValue();
-        addDependenceElem(DependenceType::WAW,
-                          LinalgOpView{src.getOperation(), srcIndex},
-                          LinalgOpView{dst.getOperation(), dstIndex});
-      }
-    }
+    for (OpOperand *dstOpOperand : dst.getOutputBuffersOpOperands()) // W
+      if (aliases.alias(srcOpOperand->get(), dstOpOperand->get())) // WAW alias
+        addDependenceElem(DependenceType::WAW, srcOpOperand, dstOpOperand);
   }
-  for (auto srcView : llvm::enumerate(src.getInputBuffers())) { // R
-    unsigned srcIndex =
-        src.getOperandIndexForInputIndex(srcView.index()).getValue();
+  for (OpOperand *srcOpOperand : src.getInputBuffersOpOperands()) { // R
     // RAR graph
-    for (auto dstView : llvm::enumerate(dst.getInputBuffers())) { // R
-      if (aliases.alias(srcView.value(),
-                        dstView.value())) { // if alias, fill RAR
-        unsigned dstIndex =
-            dst.getOperandIndexForInputIndex(dstView.index()).getValue();
-        addDependenceElem(DependenceType::RAR,
-                          LinalgOpView{src.getOperation(), srcIndex},
-                          LinalgOpView{dst.getOperation(), dstIndex});
-      }
-    }
+    for (OpOperand *dstOpOperand : dst.getInputBuffersOpOperands()) // R
+      if (aliases.alias(srcOpOperand->get(), dstOpOperand->get()))  // RAR alias
+        addDependenceElem(DependenceType::RAR, srcOpOperand, dstOpOperand);
     // WAR graph
-    for (auto dstView : llvm::enumerate(dst.getOutputBuffers())) { // W
-      if (aliases.alias(srcView.value(),
-                        dstView.value())) { // if alias, fill WAR
-        unsigned dstIndex =
-            dst.getOperandIndexForOutputIndex(dstView.index()).getValue();
-        addDependenceElem(DependenceType::WAR,
-                          LinalgOpView{src.getOperation(), srcIndex},
-                          LinalgOpView{dst.getOperation(), dstIndex});
-      }
-    }
+    for (OpOperand *dstOpOperand : dst.getOutputBuffersOpOperands()) // W
+      if (aliases.alias(srcOpOperand->get(), dstOpOperand->get())) // WAR alias
+        addDependenceElem(DependenceType::WAR, srcOpOperand, dstOpOperand);
   }
 }
 
@@ -248,17 +218,15 @@ LinalgDependenceGraph::findOperationsWithCoveringDependences(
   // TODO: we are not considering paths yet, just interleaved positions.
   for (auto dt : types) {
     for (auto dependence : getDependencesFrom(src, dt)) {
-      auto interimPos = linalgOpPositions.lookup(dependence.dependentOpView.op);
+      auto interimPos =
+          linalgOpPositions.lookup(dependence.dependentOpView->getOwner());
       // Skip if not interleaved.
       if (interimPos >= dstPos || interimPos <= srcPos)
         continue;
-      linalg::LinalgOp consumer =
-          cast<linalg::LinalgOp>(dependence.indexingOpView.op);
-      Value consumerView =
-          consumer.getShapedOperand(dependence.indexingOpView.operandIndex);
+      Value consumerView = dependence.indexingOpView->get();
       if (view && !aliases.alias(view, consumerView))
         continue;
-      auto *op = dependence.dependentOpView.op;
+      auto *op = dependence.dependentOpView->getOwner();
       LLVM_DEBUG(dbgs() << "\n***Found covering dependence of type "
                         << getDependenceTypeStr(dt) << ": " << *src << " -> "
                         << *op << " on " << consumerView);
@@ -271,12 +239,10 @@ LinalgDependenceGraph::findOperationsWithCoveringDependences(
 bool LinalgDependenceGraph::hasDependenceFrom(
     LinalgOp srcLinalgOp, LinalgOp dstLinalgOp,
     ArrayRef<LinalgDependenceGraph::DependenceType> depTypes) const {
-  for (auto dep : depTypes) {
-    for (auto dependence : getDependencesInto(dstLinalgOp, dep)) {
-      if (dependence.dependentOpView.op == srcLinalgOp)
+  for (auto dep : depTypes)
+    for (auto dependence : getDependencesInto(dstLinalgOp, dep))
+      if (dependence.dependentOpView->getOwner() == srcLinalgOp)
         return true;
-    }
-  }
   return false;
 }
 
diff --git a/mlir/lib/Dialect/Linalg/EDSC/Builders.cpp b/mlir/lib/Dialect/Linalg/EDSC/Builders.cpp
index 0ae1efe10b7fd..3c3b2777d6c14 100644
--- a/mlir/lib/Dialect/Linalg/EDSC/Builders.cpp
+++ b/mlir/lib/Dialect/Linalg/EDSC/Builders.cpp
@@ -23,36 +23,25 @@ using namespace mlir::scf;
 
 Operation *mlir::edsc::makeGenericLinalgOp(
     ArrayRef<IteratorType> iteratorTypes, ArrayRef<StructuredIndexed> inputs,
-    ArrayRef<StructuredIndexed> outputBuffers, ArrayRef<Value> initTensors,
-    ArrayRef<StructuredIndexed> resultTensorTypes,
+    ArrayRef<StructuredIndexed> outputs, TypeRange resultTensorTypes,
     function_ref<void(ValueRange)> regionBuilder, ArrayRef<Value> otherValues,
     ArrayRef<Attribute> otherAttributes) {
   OpBuilder &builder = edsc::ScopedContext::getBuilderRef();
 
   // Build maps
   SmallVector<SmallVector<AffineExpr, 4>, 4> exprsList;
-  exprsList.reserve(inputs.size() + outputBuffers.size() + initTensors.size());
-  for (auto container : {inputs, outputBuffers, resultTensorTypes})
+  exprsList.reserve(inputs.size() + outputs.size());
+
+  for (auto container : {inputs, outputs})
     for (const StructuredIndexed &s : container)
       exprsList.emplace_back(s.getExprs().begin(), s.getExprs().end());
   auto maps = AffineMap::inferFromExprList(exprsList);
 
-  SmallVector<Type, 4> types;
-  assert(llvm::all_of(resultTensorTypes, [](const StructuredIndexed &s) {
-    return !s.hasValue();
-  }));
-  std::copy(resultTensorTypes.begin(), resultTensorTypes.end(),
-            std::back_inserter(types));
-
-  SmallVector<Value, 4> inputValues, outputBufferValues, initTensorValues;
+  SmallVector<Value, 4> inputValues, outputValues;
   inputValues.reserve(inputs.size());
-  outputBufferValues.reserve(outputBuffers.size());
-  initTensorValues.reserve(initTensors.size());
+  outputValues.reserve(outputs.size());
   std::copy(inputs.begin(), inputs.end(), std::back_inserter(inputValues));
-  std::copy(outputBuffers.begin(), outputBuffers.end(),
-            std::back_inserter(outputBufferValues));
-  std::copy(initTensors.begin(), initTensors.end(),
-            std::back_inserter(initTensorValues));
+  std::copy(outputs.begin(), outputs.end(), std::back_inserter(outputValues));
 
   auto iteratorStrTypes =
       llvm::to_vector<8>(llvm::map_range(iteratorTypes, toString));
@@ -61,10 +50,9 @@ Operation *mlir::edsc::makeGenericLinalgOp(
       edsc::ScopedContext::getBuilderRef()
           .create<linalg::GenericOp>(
               edsc::ScopedContext::getLocation(),
-              types,
+              resultTensorTypes,
               inputValues,
-              outputBufferValues,
-              initTensorValues,
+              outputValues,
               builder.getAffineMapArrayAttr(maps),
               builder.getStrArrayAttr(iteratorStrTypes),
               StringAttr() /*doc*/,
@@ -77,12 +65,10 @@ Operation *mlir::edsc::makeGenericLinalgOp(
 
   using namespace edsc;
   SmallVector<Type, 4> blockTypes;
-  blockTypes.reserve(inputs.size() + outputBuffers.size() + initTensors.size());
-  for (auto container : {inputs, outputBuffers})
+  blockTypes.reserve(inputs.size() + outputs.size());
+  for (auto container : {inputs, outputs})
     for (const StructuredIndexed &s : container)
       blockTypes.push_back(getElementTypeOrSelf(s.getType()));
-  for (Value v : initTensors)
-    blockTypes.push_back(getElementTypeOrSelf(v.getType()));
 
   assert(op->getNumRegions() == 1);
   assert(op->getRegion(0).empty());
@@ -119,11 +105,10 @@ Operation *mlir::edsc::ops::linalg_generic_pointwise(
     linalg_yield(unaryOp(a));
   };
   if (O.getType().isa<RankedTensorType>())
-    return makeGenericLinalgOp(iterTypes, /*inputs=*/{I}, /*outputBuffers=*/{},
-                               /*initTensors=*/{}, /*resultTensorTypes=*/{O},
-                               fun);
-  return makeGenericLinalgOp(iterTypes, /*inputs=*/{I}, /*outputBuffers=*/{O},
-                             /*initTensors=*/{}, /*resultTensorTypes=*/{}, fun);
+    return makeGenericLinalgOp(iterTypes, /*inputs=*/{I}, /*outputs=*/{O},
+                               /*resultTensorTypes=*/{O}, fun);
+  return makeGenericLinalgOp(iterTypes, /*inputs=*/{I}, /*outputs=*/{O},
+                             /*resultTensorTypes=*/{}, fun);
 }
 
 Operation *mlir::edsc::ops::linalg_generic_pointwise_tanh(StructuredIndexed I,
@@ -144,12 +129,10 @@ Operation *mlir::edsc::ops::linalg_generic_pointwise(
     linalg_yield(binaryOp(a, b));
   };
   if (O.getType().isa<RankedTensorType>())
-    return makeGenericLinalgOp(
-        iterTypes, /*inputs=*/{I1, I2}, /*outputBuffers=*/{},
-        /*initTensors=*/{}, /*resultTensorTypes=*/{O}, fun);
+    return makeGenericLinalgOp(iterTypes, /*inputs=*/{I1, I2}, /*outputs=*/{O},
+                               /*resultTensorTypes=*/{O}, fun);
   return makeGenericLinalgOp(iterTypes, /*inputs=*/{I1, I2},
-                             /*outputBuffers=*/{O},
-                             /*initTensors=*/{}, /*resultTensorTypes=*/{}, fun);
+                             /*outputs=*/{O}, /*resultTensorTypes=*/{}, fun);
 }
 
 Operation *mlir::edsc::ops::linalg_generic_pointwise_add(StructuredIndexed I1,
@@ -181,8 +164,7 @@ mlir::edsc::ops::linalg_generic_matmul(Value vA, Value vB, Value vC,
   return makeGenericLinalgOp(
     {IteratorType::Parallel, IteratorType::Parallel, IteratorType::Reduction},
     /*inputs=*/{A({m, k}), B({k, n})},
-    /*outputBuffers=*/{C({m, n})},
-    /*initTensors=*/{},
+    /*outputs=*/{C({m, n})},
     /*resultTensorTypes=*/{},
     regionBuilder);
   // clang-format on
@@ -199,8 +181,7 @@ mlir::edsc::ops::linalg_generic_matmul(Value vA, Value vB, Value vC,
   return makeGenericLinalgOp(
     {IteratorType::Parallel, IteratorType::Parallel, IteratorType::Reduction},
     /*inputs=*/{A({m, k}), B({k, n})},
-    /*outputBuffers=*/{},
-    /*initTensors=*/{C({m, n})},
+    /*outputs=*/{C({m, n})},
     /*resultTensorTypes=*/{D({m, n})},
     regionBuilder);
   // clang-format on
@@ -236,8 +217,7 @@ Operation *mlir::edsc::ops::linalg_generic_conv_nhwc(Value vI, Value vW,
          simplifyAffineExpr(s[1] * w + d[1] * kw, numDims, 0),
          c}),
       W({kh, kw, c, f}) },
-    /*outputBuffers=*/{ O({b, h, w, f}) },
-    /*initTensors=*/{},
+    /*outputs=*/{ O({b, h, w, f}) },
     /*resultTensorTypes=*/{},
     macRegionBuilder);
   // clang-format on
@@ -272,9 +252,8 @@ Operation *mlir::edsc::ops::linalg_generic_dilated_conv_nhwc(
          simplifyAffineExpr(s[1] * w + d[1] * kw, numDims, 0),
          c}),
       W({kh, kw, c, dm})},
-    /*outputBuffers=*/{
+    /*outputs=*/{
       O({b, h, w, simplifyAffineExpr(c * depth_multiplier + dm, numDims, 0)})},
-    /*initTensors=*/{},
     /*resultTensorTypes=*/{},
     macRegionBuilder);
   // clang-format on
diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
index 3a7249df8e793..bcbd6d9036121 100644
--- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
+++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp
@@ -88,22 +88,20 @@ SmallVector<Range, 4> LinalgOp::createLoopRanges(OpBuilder &b, Location loc) {
 
 /// Forward declarations.
 template <typename NamedStructuredOpType>
-static void buildNamedStructuredOpRegionAndAttributes(
-    OpBuilder &opBuilder, OperationState &result, TypeRange inputTypes,
-    TypeRange outputBufferTypes, TypeRange initTensorTypes,
-    TypeRange resultTypes);
+static void buildNamedStructuredOpRegionAndAttributes(OpBuilder &opBuilder,
+                                                      OperationState &result,
+                                                      TypeRange inputTypes,
+                                                      TypeRange outputTypes);
 
 static ParseResult
 parseCommonStructuredOpParts(OpAsmParser &parser, OperationState &result,
                              SmallVectorImpl<Type> &inputTypes,
-                             SmallVectorImpl<Type> &outputBufferTypes,
-                             SmallVectorImpl<Type> &initTensorTypes);
+                             SmallVectorImpl<Type> &outputTypes);
 
 template <typename NamedStructuredOpType>
 static ParseResult
 parseNamedStructuredOpRegion(OpAsmParser &parser, Region &region,
-                             TypeRange inputTypes, TypeRange outputBufferTypes,
-                             TypeRange initTensorTypes, TypeRange resultTypes);
+                             TypeRange inputTypes, TypeRange outputTypes);
 static ParseResult
 parseNamedStructuredOpResults(OpAsmParser &parser,
                               SmallVectorImpl<Type> &resultTypes);
@@ -122,9 +120,6 @@ static void printNamedStructuredOpResults(OpAsmPrinter &p,
 template <typename NamedStructuredOpType>
 static void printNamedStructuredOp(OpAsmPrinter &p, NamedStructuredOpType op);
 
-template <typename NamedStructuredOpType>
-static LogicalResult verifyNamedStructuredOp(NamedStructuredOpType op);
-
 /// This is a common class used for patterns of the form
 /// ```
 ///    someop(memrefcast) -> someop
@@ -152,11 +147,10 @@ static LogicalResult foldMemRefCast(Operation *op) {
 //===----------------------------------------------------------------------===//
 void GenericOp::build(
     OpBuilder &builder, OperationState &result, TypeRange resultTensorTypes,
-    ValueRange inputs, ValueRange outputBuffers, ValueRange initTensors,
-    ArrayRef<AffineMap> indexingMaps, ArrayRef<StringRef> iteratorTypes,
-    StringRef doc, StringRef libraryCall,
+    ValueRange inputs, ValueRange outputs, ArrayRef<AffineMap> indexingMaps,
+    ArrayRef<StringRef> iteratorTypes, StringRef doc, StringRef libraryCall,
     function_ref<void(OpBuilder &, Location, ValueRange)> bodyBuild) {
-  build(builder, result, resultTensorTypes, inputs, outputBuffers, initTensors,
+  build(builder, result, resultTensorTypes, inputs, outputs,
         builder.getAffineMapArrayAttr(indexingMaps),
         builder.getStrArrayAttr(iteratorTypes),
         doc.empty() ? StringAttr() : builder.getStringAttr(doc),
@@ -166,7 +160,7 @@ void GenericOp::build(
     return;
 
   SmallVector<Type, 4> blockArgTypes;
-  for (ValueRange container : {inputs, outputBuffers, initTensors})
+  for (ValueRange container : {inputs, outputs})
     for (Value v : container)
       blockArgTypes.push_back(v.getType().cast<ShapedType>().getElementType());
 
@@ -178,41 +172,40 @@ void GenericOp::build(
 
 void GenericOp::build(
     OpBuilder &builder, OperationState &result, ValueRange inputs,
-    ValueRange outputBuffers, ArrayRef<AffineMap> indexingMaps,
+    ValueRange outputs, ArrayRef<AffineMap> indexingMaps,
     ArrayRef<StringRef> iteratorTypes, StringRef doc, StringRef libraryCall,
     function_ref<void(OpBuilder &, Location, ValueRange)> bodyBuild) {
-  build(builder, result, TypeRange{}, inputs, outputBuffers, ValueRange{},
-        indexingMaps, iteratorTypes, doc, libraryCall, bodyBuild);
+  build(builder, result, TypeRange{}, inputs, outputs, indexingMaps,
+        iteratorTypes, doc, libraryCall, bodyBuild);
 }
 
 void GenericOp::build(
     OpBuilder &builder, OperationState &result, ValueRange inputs,
-    ValueRange outputBuffers, ArrayRef<AffineMap> indexingMaps,
+    ValueRange outputs, ArrayRef<AffineMap> indexingMaps,
     ArrayRef<StringRef> iteratorTypes,
     function_ref<void(OpBuilder &, Location, ValueRange)> bodyBuild) {
-  build(builder, result, inputs, outputBuffers, indexingMaps, iteratorTypes,
+  build(builder, result, inputs, outputs, indexingMaps, iteratorTypes,
         /*doc=*/"",
         /*libraryCall=*/"", bodyBuild);
 }
 
 void GenericOp::build(
     OpBuilder &builder, OperationState &result, TypeRange resultTensorTypes,
-    ValueRange inputs, ValueRange outputBuffers, ValueRange initTensors,
-    ArrayRef<AffineMap> indexingMaps, ArrayRef<StringRef> iteratorTypes,
+    ValueRange inputs, ValueRange outputs, ArrayRef<AffineMap> indexingMaps,
+    ArrayRef<StringRef> iteratorTypes,
     function_ref<void(OpBuilder &, Location, ValueRange)> bodyBuild) {
-  build(builder, result, resultTensorTypes, inputs, outputBuffers, initTensors,
-        indexingMaps, iteratorTypes,
+  build(builder, result, resultTensorTypes, inputs, outputs, indexingMaps,
+        iteratorTypes,
         /*doc=*/"",
         /*libraryCall=*/"", bodyBuild);
 }
 void IndexedGenericOp::build(
     OpBuilder &builder, OperationState &result, TypeRange resultTensorTypes,
-    ValueRange inputs, ValueRange outputBuffers, ValueRange initTensors,
-    ArrayRef<AffineMap> indexingMaps, ArrayRef<StringRef> iteratorTypes,
-    StringRef doc, StringRef libraryCall,
+    ValueRange inputs, ValueRange outputs, ArrayRef<AffineMap> indexingMaps,
+    ArrayRef<StringRef> iteratorTypes, StringRef doc, StringRef libraryCall,
     function_ref<void(OpBuilder &, Location, ValueRange, ValueRange)>
         bodyBuild) {
-  build(builder, result, resultTensorTypes, inputs, outputBuffers, initTensors,
+  build(builder, result, resultTensorTypes, inputs, outputs,
         builder.getAffineMapArrayAttr(indexingMaps),
         builder.getStrArrayAttr(iteratorTypes),
         doc.empty() ? StringAttr() : builder.getStringAttr(doc),
@@ -223,7 +216,7 @@ void IndexedGenericOp::build(
 
   unsigned nLoops = iteratorTypes.size();
   SmallVector<Type, 4> blockArgTypes(nLoops, builder.getIndexType());
-  for (ValueRange container : {inputs, outputBuffers, initTensors})
+  for (ValueRange container : {inputs, outputs})
     for (Value v : container)
       blockArgTypes.push_back(v.getType().cast<ShapedType>().getElementType());
 
@@ -237,32 +230,32 @@ void IndexedGenericOp::build(
 
 void IndexedGenericOp::build(
     OpBuilder &builder, OperationState &result, ValueRange inputs,
-    ValueRange outputBuffers, ArrayRef<AffineMap> indexingMaps,
+    ValueRange outputs, ArrayRef<AffineMap> indexingMaps,
     ArrayRef<StringRef> iteratorTypes, StringRef doc, StringRef libraryCall,
     function_ref<void(OpBuilder &, Location, ValueRange, ValueRange)>
         bodyBuild) {
-  build(builder, result, TypeRange{}, inputs, outputBuffers, ValueRange{},
-        indexingMaps, iteratorTypes, doc, libraryCall, bodyBuild);
+  build(builder, result, TypeRange{}, inputs, outputs, indexingMaps,
+        iteratorTypes, doc, libraryCall, bodyBuild);
 }
 
 void IndexedGenericOp::build(
     OpBuilder &builder, OperationState &result, ValueRange inputs,
-    ValueRange outputBuffers, ArrayRef<AffineMap> indexingMaps,
+    ValueRange outputs, ArrayRef<AffineMap> indexingMaps,
     ArrayRef<StringRef> iteratorTypes,
     function_ref<void(OpBuilder &, Location, ValueRange, ValueRange)>
         bodyBuild) {
-  build(builder, result, inputs, outputBuffers, indexingMaps, iteratorTypes,
+  build(builder, result, inputs, outputs, indexingMaps, iteratorTypes,
         /*doc=*/"", /*libraryCall=*/"", bodyBuild);
 }
 
 void IndexedGenericOp::build(
     OpBuilder &builder, OperationState &result, TypeRange resultTensorTypes,
-    ValueRange inputs, ValueRange outputBuffers, ValueRange initTensors,
-    ArrayRef<AffineMap> indexingMaps, ArrayRef<StringRef> iteratorTypes,
+    ValueRange inputs, ValueRange outputs, ArrayRef<AffineMap> indexingMaps,
+    ArrayRef<StringRef> iteratorTypes,
     function_ref<void(OpBuilder &, Location, ValueRange, ValueRange)>
         bodyBuild) {
-  build(builder, result, resultTensorTypes, inputs, outputBuffers, initTensors,
-        indexingMaps, iteratorTypes,
+  build(builder, result, resultTensorTypes, inputs, outputs, indexingMaps,
+        iteratorTypes,
         /*doc=*/"",
         /*libraryCall=*/"", bodyBuild);
 }
@@ -327,9 +320,8 @@ static ParseResult parseGenericOp(OpAsmParser &parser, OperationState &result) {
                            dictAttr.getValue().end());
 
   // Parsing is shared with named ops, except for the region.
-  SmallVector<Type, 1> inputTypes, outputBufferTypes, initTensorTypes;
-  if (parseCommonStructuredOpParts(parser, result, inputTypes,
-                                   outputBufferTypes, initTensorTypes))
+  SmallVector<Type, 1> inputTypes, outputTypes;
+  if (parseCommonStructuredOpParts(parser, result, inputTypes, outputTypes))
     return failure();
 
   // Optional attributes may be added.
@@ -360,7 +352,7 @@ static ParseResult parseGenericOp(OpAsmParser &parser, OperationState &result) {
 static void getGenericEffectsImpl(
     SmallVectorImpl<SideEffects::EffectInstance<MemoryEffects::Effect>>
         &effects,
-    ValueRange results, ValueRange inputBuffers, ValueRange outputBuffers) {
+    ValueRange results, ValueRange inputBuffers, ValueRange outputs) {
   for (Value value : results) {
     effects.emplace_back(MemoryEffects::Allocate::get(), value,
                          SideEffects::DefaultResource::get());
@@ -369,7 +361,7 @@ static void getGenericEffectsImpl(
     effects.emplace_back(MemoryEffects::Read::get(), value,
                          SideEffects::DefaultResource::get());
   }
-  for (Value value : outputBuffers) {
+  for (Value value : outputs) {
     effects.emplace_back(MemoryEffects::Read::get(), value,
                          SideEffects::DefaultResource::get());
     effects.emplace_back(MemoryEffects::Write::get(), value,
@@ -391,65 +383,150 @@ void IndexedGenericOp::getEffects(
                         getInputBuffers(), getOutputBuffers());
 }
 
-namespace {
+LogicalResult mlir::linalg::detail::verifyStructuredOpInterface(Operation *op) {
+  LinalgOp linalgOp = cast<LinalgOp>(op);
+  // Expect at least one shaped operand.
+  // This means an op that constructs a tensor out of indices cannot be a
+  // LinalgOp at the moment. For now this will have to be a special op until we
+  // have output shape operands that are not tensors.
+  auto nShapedOperands = linalgOp.getNumShapedOperands();
+  if (nShapedOperands == 0)
+    return linalgOp.emitOpError("expected at least 1 Shaped operand");
+  if (failed(OpTrait::impl::verifyAtLeastNOperands(op, nShapedOperands)))
+    return failure();
+  // Should have at least one output tensor per result tensor.
+  // Can also have outbut buffers that do not correspond to results.
+  if (op->getNumResults() > linalgOp.getNumOutputTensors())
+    return op->emitError("unexpected #results > #outputs");
+
+  // All shaped operands must be indexed.
+  if (linalgOp.indexing_maps().size() != linalgOp.getNumShapedOperands())
+    return linalgOp.emitOpError("expected the number of indexing_map (")
+           << linalgOp.indexing_maps().size()
+           << ") to be equal to the number of shaped operands ("
+           << linalgOp.getNumShapedOperands() << ")";
 
-template <typename GenericOpType>
-struct BlockArgsVerifier {
-  static LogicalResult verify(GenericOpType op, Block &block);
-};
+  SmallVector<AffineMap, 4> indexingMaps;
+  indexingMaps.reserve(linalgOp.indexing_maps().size());
+  for (auto en : llvm::enumerate(linalgOp.indexing_maps())) {
+    auto idx = en.index();
+    auto m = en.value().template cast<AffineMapAttr>().getValue();
+    indexingMaps.push_back(m); // Save reference to map for further checks.
+    auto shapedValue = linalgOp.getShapedType(idx);
 
-template <typename GenericOpType>
-LogicalResult BlockArgsVerifier<GenericOpType>::verify(GenericOpType op,
-                                                       Block &block) {
-  auto nOperands = op.getNumOperands();
-  if (block.getNumArguments() != nOperands)
-    return op.emitOpError("expected number of block arguments to match number "
-                          "of operands");
+    // Symbols disallowed.
+    if (m.getNumSymbols() != 0)
+      return linalgOp.emitOpError("unexpected symbols in indexing_map #")
+             << idx;
 
-  // Note: the number and type of yield values are checked in the YieldOp.
-  auto nInputViews = op.getNumInputs();
-  for (unsigned i = 0; i < nOperands; ++i) {
-    auto viewType = op.getShapedType(i);
-    if (viewType.getElementType() != block.getArgument(i).getType())
-      return op.emitOpError("expected block argument ")
-             << (i + 1) << " of the same type as elemental type of "
-             << ((i < nInputViews) ? "input " : "output ")
-             << "operand: " << viewType;
+    // Domain must be consistent.
+    auto nLoops = linalgOp.getNumLoops();
+    if (m.getNumDims() != nLoops)
+      return linalgOp.emitOpError("expected indexing_map #")
+             << idx << " to have " << nLoops
+             << " dim(s) to match the number of loops";
+
+    if (m.getNumResults() != shapedValue.getRank())
+      return linalgOp.emitOpError("expected shaped value rank (")
+             << shapedValue.getRank()
+             << ") to match the result rank of indexing_map #" << idx << " ("
+             << m.getNumResults() << ")";
   }
-  return success();
-}
 
-template <>
-LogicalResult BlockArgsVerifier<IndexedGenericOp>::verify(IndexedGenericOp op,
-                                                          Block &block) {
-  auto nInputViews = op.getNumInputs();
-  auto nLoops = op.getNumLoops();
-  auto nOperands = op.getNumOperands();
-  if (block.getNumArguments() != nOperands + nLoops)
-    return op.emitOpError(
-        "expected number of block arguments to match number of operands + "
-        "number of loops");
+  SmallVector<AffineExpr, 4> redDims;
+  linalgOp.getReductionDims(redDims);
+
+  // Simplifying assumption: either full tensor or full buffer mode.
+  // This allows simpler verification of output operands vs result types
+  // without premature tracking of which operand is what in mixed-mode.
+  // TODO: relax when mixed-mode needs to pass verification.
+  if (linalgOp.getNumOutputBuffers() > 0 && linalgOp.getNumOutputTensors() > 0)
+    return op->emitError("expected output operands to all have tensor type or "
+                         "all have buffer type");
+
+  for (auto it :
+       llvm::zip(linalgOp.getOutputOpOperands(), op->getResultTypes())) {
+    if (!std::get<0>(it).get().getType().isa<RankedTensorType>())
+      continue;
+    if (std::get<0>(it).get().getType() != std::get<1>(it))
+      return op->emitError("expected type of operand #")
+             << std::get<0>(it).getOperandNumber() << " ("
+             << std::get<0>(it).get().getType() << ")"
+             << " to match type of corresponding result (" << std::get<1>(it)
+             << ")";
+  }
+
+  // Output tensor indexing map may not depend on reduction indices.
+  for (OpOperand &opOperand : linalgOp.getOutputOpOperands()) {
+    AffineMap outputMap = linalgOp.getIndexingMap(opOperand.getOperandNumber());
+    for (auto expr : outputMap.getResults()) {
+      for (auto dim : redDims) {
+        unsigned pos = dim.cast<AffineDimExpr>().getPosition();
+        if (expr.isFunctionOfDim(pos)) {
+          std::string exprStr;
+          {
+            llvm::raw_string_ostream os(exprStr);
+            os << expr;
+          }
+          return op->emitError(
+                     "unexpected output tensor expression in indexing map #")
+                 << (opOperand.getOperandNumber() - linalgOp.getNumInputs())
+                 << " a.k.a '" << exprStr
+                 << "' is function of reduction iterator 'd" << pos << "'";
+        }
+      }
+    }
+  }
+
+  // Named ops that are defined manually have a region builder but no region at
+  // this time. Assume the region is well-formed by specification.
+  // TODO: use linalg-ods-gen for all ops when we have enough expressive power.
+  if (linalgOp->getNumRegions() == 0) {
+    assert(!linalgOp.getRegionBuilder() && "regionBuilder but no region");
+    return success();
+  }
+
+  auto &region = linalgOp->getRegion(0);
+  if (linalgOp->getNumRegions() > 1 || !llvm::hasSingleElement(region))
+    return op->emitOpError("expected 1 region with 1 block");
+
+  if (!linalgOp.getShapesToLoopsMap())
+    return op->emitOpError("expected the shape-to-loops map to be non-null");
+
+  // Simplifying assumption: bbargs match 1-1 with shape operands elemental
+  // types.
+  // TODO: once ranked shape types are plugged in, we may want to drop the
+  // corresponding bbargs, that can never be read from. This will be subject to
+  // consistency discussions (i.e. what to do with output tensors whose bbarg is
+  // not used).
+  Block &block = linalgOp->getRegion(0).front();
+  unsigned numBBIvs = linalgOp.getNumPayloadInductionVariables();
+
+  if (linalgOp.getNumShapedOperands() + numBBIvs != block.getNumArguments())
+    return op->emitError("expected as many non-induction variable region "
+                         "arguments as the number of shaped operands");
 
   // Note: the number and type of yield values are checked in the YieldOp.
-  for (unsigned i = 0; i < nLoops; ++i)
+  for (unsigned i = 0; i < numBBIvs; ++i)
     if (!block.getArgument(i).getType().isIndex())
-      return op.emitOpError("expected block argument ")
-             << (i + 1) << " to be an index";
-
-  for (unsigned i = 0; i < nOperands; ++i) {
-    unsigned memrefArgIndex = i + nLoops;
-    auto viewType = op.getShapedType(i);
-    if (viewType.getElementType() !=
-        block.getArgument(memrefArgIndex).getType())
-      return op.emitOpError("expected block argument ")
-             << (memrefArgIndex + 1)
-             << " of the same type as elemental type of "
-             << ((i < nInputViews) ? "input " : "output ")
-             << "operand: " << viewType;
+      return op->emitOpError("expected index block argument #") << i;
+
+  unsigned idx = 0;
+  for (auto it : llvm::zip(linalgOp.getShapedOperandTypes(),
+                           block.getArguments().drop_front(numBBIvs))) {
+    if (std::get<0>(it).getElementType() != std::get<1>(it).getType())
+      return op->emitError("expected type of bb argument #")
+             << (idx + numBBIvs) << " (" << std::get<1>(it).getType() << ")"
+             << " to match element type of corresponding shaped operand ("
+             << std::get<0>(it).getElementType() << ")";
+    ++idx;
   }
+
   return success();
 }
 
+namespace {
+
 template <typename GenericOpType>
 struct AnnotationsVerifier {
   static LogicalResult verify(GenericOpType op) { return success(); }
@@ -465,7 +542,7 @@ LogicalResult AnnotationsVerifier<GenericOp>::verify(GenericOp op) {
     return op.emitOpError("expected sparse annotations on tensors only");
   if (op.getNumOutputs() != 1)
     return op.emitOpError("expected single output tensor");
-  unsigned numTensors = op.getNumInputsAndOutputs();
+  unsigned numTensors = op.getNumShapedOperands();
   if (sparseAttr.size() != numTensors)
     return op.emitOpError("expected one sparse annotation for each tensor");
   for (unsigned t = 0; t < numTensors; t++) {
@@ -497,49 +574,6 @@ LogicalResult AnnotationsVerifier<GenericOp>::verify(GenericOp op) {
 
 template <typename GenericOpType>
 static LogicalResult verifyGenericOp(GenericOpType op) {
-  auto nLoops = op.getNumLoops();
-
-  if (op.inputs().size() + op.output_buffers().size() +
-          op.init_tensors().size() + op.getNumResults() ==
-      0)
-    return op.emitOpError("expected at least 1 Shaped operand or return");
-
-  auto &region = op.region();
-  if (!llvm::hasSingleElement(region))
-    return op.emitOpError("expected region with 1 block");
-  if (failed(BlockArgsVerifier<GenericOpType>::verify(op, region.front())))
-    return failure();
-
-  if (op.indexing_maps().size() != op.getNumInputsAndOutputs())
-    return op.emitOpError("expected the number of indexing_map (")
-           << op.indexing_maps().size()
-           << ") to be equal to the number of inputs and outputs ("
-           << op.getNumInputsAndOutputs() << ")";
-
-  SmallVector<AffineMap, 4> indexingMaps;
-  indexingMaps.reserve(op.indexing_maps().size());
-  for (auto en : llvm::enumerate(op.indexing_maps())) {
-    auto idx = en.index();
-    auto m = en.value().template cast<AffineMapAttr>().getValue();
-    indexingMaps.push_back(m); // Save reference to map for further checks.
-    auto view = op.getShapedType(idx);
-
-    if (m.getNumSymbols() != 0)
-      return op.emitOpError("unexpected symbols in indexing_map #") << idx;
-
-    if (m.getNumDims() != nLoops)
-      return op.emitOpError("expected indexing_map #")
-             << idx << " to have " << nLoops
-             << " dim(s) to match the number of loops";
-
-    if (m.getNumResults() != view.getRank())
-      return op.emitOpError("expected indexing_map #")
-             << idx << " results to match view rank: " << view;
-  }
-
-  if (!op.getShapesToLoopsMap())
-    return op.emitOpError("expected the shape-to-loops map to be non-null");
-
   if (failed(AnnotationsVerifier<GenericOpType>::verify(op)))
     return failure();
 
@@ -1380,8 +1414,6 @@ static LogicalResult verify(ConvOp op) {
     return op.emitOpError("expects memref elemental types to match");
   if (oType.getRank() != iType.getRank() || oType.getRank() != fType.getRank())
     return op.emitOpError("expects memref ranks to match");
-  if (oType.getRank() <= 2)
-    return op.emitOpError("expects memref ranks to be greater than 2");
   if (auto strides = op.strides()) {
     if (failed(
             verifyStrideOrDilation(op, strides->getValue(), /*isStride=*/true)))
@@ -1591,13 +1623,12 @@ OpFoldResult TensorReshapeOp::fold(ArrayRef<Attribute> operands) {
 template <typename NamedStructuredOpType>
 static void buildNamedStructuredOpRegionAndAttributesImpl(
     OpBuilder &opBuilder, Region &region, TypeRange inputTypes,
-    TypeRange outputBufferTypes, TypeRange initTensorTypes,
-    TypeRange resultTypes,
+    TypeRange outputTypes,
     std::function<void(unsigned, unsigned)> errorHandler) {
   // TODO: atm all operands go through getElementTypeOrSelf,
   // reconsider when we have evidence we need to.
   SmallVector<Type, 8> argTypes;
-  for (auto containers : {inputTypes, outputBufferTypes, resultTypes})
+  for (auto containers : {inputTypes, outputTypes})
     for (auto t : containers)
       argTypes.push_back(getElementTypeOrSelf(t));
 
@@ -1622,13 +1653,11 @@ template <typename NamedStructuredOpType>
 void buildNamedStructuredOpRegionAndAttributes(OpBuilder &opBuilder,
                                                OperationState &result,
                                                TypeRange inputTypes,
-                                               TypeRange outputBufferTypes,
-                                               TypeRange initTensorTypes,
-                                               TypeRange resultTypes) {
+                                               TypeRange outputTypes) {
   Region &region = *result.addRegion();
   buildNamedStructuredOpRegionAndAttributesImpl<NamedStructuredOpType>(
-      opBuilder, region, inputTypes, outputBufferTypes, initTensorTypes,
-      resultTypes, [&](unsigned expected, unsigned actual) {
+      opBuilder, region, inputTypes, outputTypes,
+      [&](unsigned expected, unsigned actual) {
         llvm::errs() << "region expects " << expected << " args, got "
                      << actual;
         assert(expected != actual && "incorrect number of arguments");
@@ -1638,13 +1667,12 @@ void buildNamedStructuredOpRegionAndAttributes(OpBuilder &opBuilder,
 template <typename NamedStructuredOpType>
 static ParseResult
 parseNamedStructuredOpRegion(OpAsmParser &parser, Region &region,
-                             TypeRange inputTypes, TypeRange outputBufferTypes,
-                             TypeRange initTensorTypes, TypeRange resultTypes) {
+                             TypeRange inputTypes, TypeRange outputTypes) {
   ParseResult res = success();
   OpBuilder opBuilder(parser.getBuilder().getContext());
   buildNamedStructuredOpRegionAndAttributesImpl<NamedStructuredOpType>(
-      opBuilder, region, inputTypes, outputBufferTypes, initTensorTypes,
-      resultTypes, [&](unsigned expected, unsigned actual) {
+      opBuilder, region, inputTypes, outputTypes,
+      [&](unsigned expected, unsigned actual) {
         res = parser.emitError(parser.getCurrentLocation(),
                                llvm::formatv("region expects {0} args, got {1}",
                                              expected, actual));
@@ -1664,12 +1692,9 @@ parseNamedStructuredOpResults(OpAsmParser &parser,
 static ParseResult
 parseCommonStructuredOpParts(OpAsmParser &parser, OperationState &result,
                              SmallVectorImpl<Type> &inputTypes,
-                             SmallVectorImpl<Type> &outputBufferTypes,
-                             SmallVectorImpl<Type> &initTensorTypes) {
-  llvm::SMLoc inputsOperandsLoc, outputBuffersOperandsLoc,
-      initTensorsOperandsLoc;
-  SmallVector<OpAsmParser::OperandType, 4> inputsOperands,
-      outputBuffersOperands, initTensorsOperands;
+                             SmallVectorImpl<Type> &outputTypes) {
+  llvm::SMLoc inputsOperandsLoc, outputsOperandsLoc;
+  SmallVector<OpAsmParser::OperandType, 4> inputsOperands, outputsOperands;
 
   parser.parseOptionalAttrDict(result.attributes);
 
@@ -1684,41 +1709,30 @@ parseCommonStructuredOpParts(OpAsmParser &parser, OperationState &result,
   }
 
   if (succeeded(parser.parseOptionalKeyword("outs"))) {
-    outputBuffersOperandsLoc = parser.getCurrentLocation();
-    if (parser.parseLParen() ||
-        parser.parseOperandList(outputBuffersOperands) ||
-        parser.parseColonTypeList(outputBufferTypes) || parser.parseRParen())
-      return failure();
-  }
-  if (succeeded(parser.parseOptionalKeyword("init"))) {
-    initTensorsOperandsLoc = parser.getCurrentLocation();
-    if (parser.parseLParen() || parser.parseOperandList(initTensorsOperands) ||
-        parser.parseColonTypeList(initTensorTypes) || parser.parseRParen())
+    outputsOperandsLoc = parser.getCurrentLocation();
+    if (parser.parseLParen() || parser.parseOperandList(outputsOperands) ||
+        parser.parseColonTypeList(outputTypes) || parser.parseRParen())
       return failure();
   }
 
   if (parser.resolveOperands(inputsOperands, inputTypes, inputsOperandsLoc,
                              result.operands) ||
-      parser.resolveOperands(outputBuffersOperands, outputBufferTypes,
-                             outputBuffersOperandsLoc, result.operands) ||
-      parser.resolveOperands(initTensorsOperands, initTensorTypes,
-                             initTensorsOperandsLoc, result.operands))
+      parser.resolveOperands(outputsOperands, outputTypes, outputsOperandsLoc,
+                             result.operands))
     return failure();
 
   result.addAttribute("operand_segment_sizes",
                       parser.getBuilder().getI32VectorAttr(
                           {static_cast<int32_t>(inputsOperands.size()),
-                           static_cast<int32_t>(outputBuffersOperands.size()),
-                           static_cast<int32_t>(initTensorsOperands.size())}));
+                           static_cast<int32_t>(outputsOperands.size())}));
   return success();
 }
 
 template <typename NamedStructuredOpType>
 static ParseResult parseNamedStructuredOp(OpAsmParser &parser,
                                           OperationState &result) {
-  SmallVector<Type, 1> inputTypes, outputBufferTypes, initTensorTypes;
-  if (parseCommonStructuredOpParts(parser, result, inputTypes,
-                                   outputBufferTypes, initTensorTypes))
+  SmallVector<Type, 1> inputTypes, outputTypes;
+  if (parseCommonStructuredOpParts(parser, result, inputTypes, outputTypes))
     return failure();
 
   // TODO: consider merging results parsing into region parsing.
@@ -1730,8 +1744,7 @@ static ParseResult parseNamedStructuredOp(OpAsmParser &parser,
 
   std::unique_ptr<Region> region = std::make_unique<Region>();
   if (parseNamedStructuredOpRegion<NamedStructuredOpType>(
-          parser, *region, inputTypes, outputBufferTypes, initTensorTypes,
-          outputTensorsTypes))
+          parser, *region, inputTypes, outputTypes))
     return failure();
   result.addRegion(std::move(region));
 
@@ -1750,12 +1763,8 @@ static void printCommonStructuredOpParts(OpAsmPrinter &p,
                                          NamedStructuredOpType op) {
   if (!op.inputs().empty())
     p << " ins(" << op.inputs() << " : " << op.inputs().getTypes() << ")";
-  if (!op.output_buffers().empty())
-    p << " outs(" << op.output_buffers() << " : "
-      << op.output_buffers().getTypes() << ")";
-  if (!op.init_tensors().empty())
-    p << " init(" << op.init_tensors() << " : " << op.init_tensors().getTypes()
-      << ") ";
+  if (!op.outputs().empty())
+    p << " outs(" << op.outputs() << " : " << op.outputs().getTypes() << ")";
 }
 
 template <typename NamedStructuredOpType>
@@ -1789,7 +1798,7 @@ struct EraseDeadLinalgOp : public RewritePattern {
     auto linalgOp = dyn_cast<LinalgOp>(op);
     if (!linalgOp)
       return failure();
-    for (Value v : linalgOp.getInputsAndOutputBuffers()) {
+    for (Value v : linalgOp.getShapedOperands()) {
       // Linalg "inputs" may be either tensor or memref type.
       // tensor<0xelt_type> is a convention that may not always mean
       // "0 iterations". Only erase in cases we see memref<...x0x...>.
@@ -1836,11 +1845,8 @@ struct FoldTensorCastOp : public RewritePattern {
       newOperands.push_back(
           canFoldIntoConsumerOp(tensorCastOp) ? tensorCastOp.source() : v);
     }
-    // Output buffers are memrefs, they don't fold.
-    newOperands.append(linalgOp.getOutputBuffers().begin(),
-                       linalgOp.getOutputBuffers().end());
     // Init tensors may fold, in which case the resultType must also change.
-    for (Value v : linalgOp.getInitTensors()) {
+    for (Value v : linalgOp.getOutputs()) {
       auto tensorCastOp = v.getDefiningOp<tensor::CastOp>();
       bool fold = canFoldIntoConsumerOp(tensorCastOp);
       newOperands.push_back(fold ? tensorCastOp.getOperand() : v);
@@ -1904,8 +1910,7 @@ struct DeduplicateInputs : public RewritePattern {
     for (auto v : llvm::enumerate(linalgOp.getInputs()))
       if (canonicalInputIndices[v.index()] == static_cast<int>(v.index()))
         newOperands.push_back(v.value());
-    llvm::append_range(newOperands, linalgOp.getOutputBuffers());
-    llvm::append_range(newOperands, linalgOp.getInitTensors());
+    llvm::append_range(newOperands, linalgOp.getOutputs());
     llvm::append_range(newOperands, linalgOp.getAssumedNonShapedOperands());
 
     // Clone the old op with new operands.
@@ -1929,11 +1934,8 @@ struct DeduplicateInputs : public RewritePattern {
     newLinalgOp.setNumInputs(canonicalInput.size());
 
     // linalg.indexed_generic payloads have additional arguments prepended to
-    // the block arg list. The number of such args is one per dimension of the
-    // iteration space.
-    int bbArgBaseOffset = 0;
-    if (isa<IndexedGenericOp>(op))
-      bbArgBaseOffset = newIndexingMaps[0].getNumInputs();
+    // the block arg list.
+    int bbArgBaseOffset = newLinalgOp.getNumPayloadInductionVariables();
 
     // Repair the payload entry block by RAUW'ing redundant arguments and
     // erasing them.
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp b/mlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp
index b36d74bad3fbc..a3ab6f45b26eb 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Bufferize.cpp
@@ -21,21 +21,22 @@
 using namespace ::mlir;
 using namespace ::mlir::linalg;
 
-static Value maybeConvertToIndex(Location loc, Value val, OpBuilder &b) {
-  if (val.getType().isIndex())
-    return val;
-  return b.create<IndexCastOp>(loc, val, b.getIndexType());
-}
-
-static Value cloneMemref(Location loc, Value memref, OpBuilder &b) {
-  auto memrefType = memref.getType().cast<MemRefType>();
+static SmallVector<Value, 4> getDynOperands(Location loc, Value val,
+                                            OpBuilder &b) {
   SmallVector<Value, 4> dynOperands;
-  for (auto dim : llvm::enumerate(memrefType.getShape())) {
+  auto shapedType = val.getType().cast<ShapedType>();
+  for (auto dim : llvm::enumerate(shapedType.getShape())) {
     if (dim.value() == TensorType::kDynamicSize) {
-      dynOperands.push_back(b.create<DimOp>(loc, memref, dim.index()));
+      dynOperands.push_back(b.create<DimOp>(loc, val, dim.index()));
     }
   }
-  auto alloc = b.create<AllocOp>(loc, memrefType, dynOperands);
+  return dynOperands;
+}
+
+static Value cloneMemref(Location loc, Value memref, OpBuilder &b) {
+  auto memrefType = memref.getType().cast<MemRefType>();
+  auto alloc =
+      b.create<AllocOp>(loc, memrefType, getDynOperands(loc, memref, b));
   b.create<linalg::CopyOp>(loc, memref, alloc);
   return alloc;
 }
@@ -48,6 +49,7 @@ allocateBuffersForResults(Location loc, LinalgOp linalgOp,
   SmallVector<Range, 4> loopRanges;
 
   // Allocate a buffer for every tensor result.
+  assert(linalgOp.getNumOutputs() == linalgOp->getNumResults());
   for (auto en : llvm::enumerate(linalgOp->getResultTypes())) {
     size_t resultIndex = en.index();
     Type resultType = en.value();
@@ -60,46 +62,26 @@ allocateBuffersForResults(Location loc, LinalgOp linalgOp,
     }
     auto tensorShape = tensorType.getShape();
     auto memrefType = MemRefType::get(tensorShape, tensorType.getElementType());
+    Value resultTensor = adaptor.outputs()[resultIndex];
 
-    // Allocate buffers for init tensors that are assumed to fold onto the first
-    // results.
-    // TODO: update this assumption because the reality is more complex
-    // under linalg on tensor based transformations.
-    bool hasInitTensor = resultIndex < linalgOp.getNumInitTensors();
-    if (hasInitTensor) {
-      resultBuffers.push_back(
-          cloneMemref(loc, adaptor.init_tensors()[resultIndex], b));
+    // Clone output buffers whose value is actually used.
+    if (linalgOp.payloadUsesValueFromOutputOperandIndex(resultIndex)) {
+      resultBuffers.push_back(cloneMemref(loc, resultTensor, b));
       continue;
     }
 
+    if (auto alloc = resultTensor.getDefiningOp<AllocOp>()) {
+      resultBuffers.push_back(resultTensor);
+      continue;
+    }
     // Allocate buffers for statically-shaped results.
     if (memrefType.hasStaticShape()) {
       resultBuffers.push_back(b.create<AllocOp>(loc, memrefType));
       continue;
     }
 
-    // Perform a naive shape inference for the dynamically-shaped results.
-    // Extract the required element out of the vector.
-    SmallVector<Value, 4> dynOperands;
-    auto resultIndexingMap = linalgOp.getOutputIndexingMap(resultIndex);
-    for (auto shapeElement : llvm::enumerate(tensorType.getShape())) {
-      if (loopRanges.empty())
-        loopRanges = linalgOp.createLoopRanges(b, loc);
-      if (shapeElement.value() != ShapedType::kDynamicSize)
-        continue;
-      AffineExpr expr = resultIndexingMap.getResult(shapeElement.index());
-      switch (expr.getKind()) {
-      case AffineExprKind::DimId: {
-        int64_t loopIndex = expr.cast<AffineDimExpr>().getPosition();
-        Value size = maybeConvertToIndex(loc, loopRanges[loopIndex].size, b);
-        dynOperands.push_back(size);
-        break;
-      }
-      default:
-        return failure();
-      }
-    }
-    resultBuffers.push_back(b.create<AllocOp>(loc, memrefType, dynOperands));
+    resultBuffers.push_back(b.create<AllocOp>(
+        loc, memrefType, getDynOperands(loc, resultTensor, b)));
   }
   return success();
 }
@@ -119,8 +101,7 @@ finalizeBufferAllocationForGenericOp(ConversionPatternRewriter &rewriter,
       genericOp.getLoc(),
       /*resultTensorTypes=*/llvm::None,
       /*inputs=*/inputs,
-      /*outputBuffers=*/outputs,
-      /*initTensors=*/llvm::None, genericOp.indexing_maps(),
+      /*outputs=*/outputs, genericOp.indexing_maps(),
       genericOp.iterator_types(), genericOp.docAttr(),
       genericOp.library_callAttr(), genericOp.sparseAttr());
 
@@ -130,10 +111,6 @@ finalizeBufferAllocationForGenericOp(ConversionPatternRewriter &rewriter,
   Block *newBlock = rewriter.createBlock(&newRegion, newRegion.begin(),
                                          oldBlock->getArgumentTypes());
 
-  // Add the result arguments to the new block.
-  for (Value v : ValueRange(outputs).drop_front(genericOp.getNumInitTensors()))
-    newBlock->addArgument(v.getType().cast<MemRefType>().getElementType());
-
   // Clone the body of the old block to the new block.
   BlockAndValueMapping mapping;
   mapping.map(oldBlock->getArguments(), newBlock->getArguments());
@@ -159,12 +136,8 @@ static void finalizeBufferAllocation(ConversionPatternRewriter &rewriter,
   newOperands.append(outputs.begin(), outputs.end());
   auto otherOperands = linalgOp.getAssumedNonShapedOperands();
   newOperands.append(otherOperands.begin(), otherOperands.end());
-  LinalgOp res = cast<LinalgOp>(linalgOp.clone(rewriter, linalgOp.getLoc(),
-                                               /*resultTypes=*/ArrayRef<Type>{},
-                                               newOperands));
-  // Need to mutate the operands_segment_sizes in the resulting op.
-  res.setNumOutputBuffers(outputs.size());
-  res.setNumInitTensors(0);
+  linalgOp.clone(rewriter, linalgOp.getLoc(),
+                 /*resultTypes=*/ArrayRef<Type>{}, newOperands);
   // Replace the results of the old op with the new output buffers.
   rewriter.replaceOp(linalgOp, outputs);
 }
@@ -174,6 +147,24 @@ static void finalizeBufferAllocation(ConversionPatternRewriter &rewriter,
 //===----------------------------------------------------------------------===//
 
 namespace {
+
+/// Generic conversion pattern that matches any LinalgOp. This avoids template
+/// instantiating one pattern for each LinalgOp.
+class BufferizeInitTensorOp : public OpConversionPattern<InitTensorOp> {
+public:
+  using OpConversionPattern<InitTensorOp>::OpConversionPattern;
+
+  LogicalResult
+  matchAndRewrite(InitTensorOp op, ArrayRef<Value> operands,
+                  ConversionPatternRewriter &rewriter) const final {
+    linalg::InitTensorOpAdaptor adaptor(operands, op->getAttrDictionary());
+    rewriter.replaceOpWithNewOp<AllocOp>(
+        op, getTypeConverter()->convertType(op.getType()).cast<MemRefType>(),
+        adaptor.sizes());
+    return success();
+  }
+};
+
 /// Generic conversion pattern that matches any LinalgOp. This avoids template
 /// instantiating one pattern for each LinalgOp.
 class BufferizeAnyLinalgOp : public ConversionPattern {
@@ -190,13 +181,12 @@ class BufferizeAnyLinalgOp : public ConversionPattern {
       return failure();
 
     // We abuse the GenericOpAdaptor here.
-    // TODO: Manually create an Adaptor that captures inputs, output_buffers and
-    // init_tensors for all linalg::LinalgOp interface ops.
+    // TODO: Manually create an Adaptor that captures inputs and outputs for all
+    // linalg::LinalgOp interface ops.
     linalg::GenericOpAdaptor adaptor(operands, op->getAttrDictionary());
 
     Location loc = linalgOp.getLoc();
-    SmallVector<Value, 2> newOutputBuffers(adaptor.output_buffers().begin(),
-                                           adaptor.output_buffers().end());
+    SmallVector<Value, 2> newOutputBuffers;
 
     if (failed(allocateBuffersForResults(loc, linalgOp, adaptor,
                                          newOutputBuffers, rewriter))) {
@@ -327,7 +317,7 @@ struct LinalgBufferizePass : public LinalgBufferizeBase<LinalgBufferizePass> {
 
     // Mark all Standard operations legal.
     target.addLegalDialect<AffineDialect, StandardOpsDialect>();
-    target.addIllegalOp<SubTensorOp, SubTensorInsertOp>();
+    target.addIllegalOp<InitTensorOp, SubTensorOp, SubTensorInsertOp>();
 
     // Mark all Linalg operations illegal as long as they work on tensors.
     auto isLegalOperation = [&](Operation *op) {
@@ -354,10 +344,11 @@ void mlir::linalg::populateLinalgBufferizePatterns(
     OwningRewritePatternList &patterns) {
   patterns.insert<BufferizeAnyLinalgOp>(typeConverter);
   // TODO: Drop this once tensor constants work in standard.
+  // clang-format off
   patterns.insert<
-      // clang-format off
+      BufferizeInitTensorOp,
       SubTensorOpConverter,
       SubTensorInsertOpConverter
-      // clang-format on
-      >(typeConverter, context);
+    >(typeConverter, context);
+  // clang-format on
 }
diff --git a/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp b/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
index bf488f827f898..8d09d58b9d7a9 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp
@@ -189,7 +189,7 @@ struct FoldUnitDimLoops : public OpRewritePattern<GenericOpTy> {
     if (!invertedMap)
       return failure();
     SmallVector<int64_t, 4> dims;
-    for (ShapedType shapedType : op.getInputOutputShapedTypes())
+    for (ShapedType shapedType : op.getShapedOperandTypes())
       dims.append(shapedType.getShape().begin(), shapedType.getShape().end());
     DenseSet<unsigned> unitDims;
     ArrayAttr iteratorTypes = op.iterator_types();
@@ -295,7 +295,7 @@ struct ReplaceUnitExtentTensors : public OpRewritePattern<GenericOpTy> {
   LogicalResult matchAndRewrite(GenericOpTy op,
                                 PatternRewriter &rewriter) const override {
     // TODO: support init_tensors and reductions.
-    if (!op.hasTensorSemantics() || !op.init_tensors().empty())
+    if (!op.hasTensorSemantics() || op.getNumInitTensors() != 0)
       return failure();
 
     MLIRContext *context = rewriter.getContext();
@@ -306,7 +306,7 @@ struct ReplaceUnitExtentTensors : public OpRewritePattern<GenericOpTy> {
     SmallVector<ShapedType, 4> newInputOutputTypes;
     bool doCanonicalization = false;
     for (auto it :
-         llvm::zip(op.getIndexingMaps(), op.getInputOutputShapedTypes())) {
+         llvm::zip(op.getIndexingMaps(), op.getShapedOperandTypes())) {
       auto replacementInfo = replaceUnitExtents(
           std::get<0>(it), std::get<1>(it).template cast<RankedTensorType>(),
           context);
@@ -342,19 +342,16 @@ struct ReplaceUnitExtentTensors : public OpRewritePattern<GenericOpTy> {
     };
 
     SmallVector<Value, 4> newInputs = insertReshapes(op.inputs());
-    SmallVector<Value, 4> newOutputBuffers =
-        insertReshapes(op.output_buffers());
-    SmallVector<Value, 4> newInitTensors = insertReshapes(op.init_tensors());
+    SmallVector<Value, 4> newOutputs = insertReshapes(op.outputs());
 
-    // If any result type change, insert a reshape to convert from the original
+    // If any result type changes, insert a reshape to convert from the original
     // type to the new type.
     SmallVector<Type, 4> resultTypes;
     resultTypes.reserve(op.getNumResults());
     for (unsigned i : llvm::seq<unsigned>(0, op.getNumResults()))
       resultTypes.push_back(newInputOutputTypes[i + op.getNumInputs()]);
     GenericOpTy replacementOp = rewriter.create<GenericOpTy>(
-        loc, resultTypes, newInputs, newOutputBuffers, newInitTensors,
-        newIndexingMaps,
+        loc, resultTypes, newInputs, newOutputs, newIndexingMaps,
         llvm::to_vector<4>(
             op.iterator_types().template getAsValueRange<StringAttr>()));
     rewriter.inlineRegionBefore(op.region(), replacementOp.region(),
@@ -364,7 +361,7 @@ struct ReplaceUnitExtentTensors : public OpRewritePattern<GenericOpTy> {
     // the original shape.
     SmallVector<Value, 4> resultReplacements;
     for (auto result : llvm::enumerate(replacementOp.getResults())) {
-      unsigned index = result.index() + replacementOp.getNumOperands();
+      unsigned index = result.index() + replacementOp.getNumInputs();
       RankedTensorType origResultType = op.getResult(result.index())
                                             .getType()
                                             .template cast<RankedTensorType>();
diff --git a/mlir/lib/Dialect/Linalg/Transforms/ElementwiseToLinalg.cpp b/mlir/lib/Dialect/Linalg/Transforms/ElementwiseToLinalg.cpp
index 8ee1b389dee83..ada9f8c02b890 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/ElementwiseToLinalg.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/ElementwiseToLinalg.cpp
@@ -25,6 +25,61 @@ static bool isElementwiseMappableOpOnRankedTensors(Operation *op) {
                       [](Type type) { return type.isa<RankedTensorType>(); });
 }
 
+/// Given `op` assumed `isElementwiseMappableOpOnRankedTensors`, iterate over
+/// the result types and return a list of values such that, for each result type
+/// `t` and value `v` at the same index `idx`:
+///   1. `v.getType() == t`
+///   2. If an operand of `op` has type `t`, let `operand_first` be the first
+///      such operand. Then`v == operand_first`.
+///   3. Otherwise, v is a newly created `linalg::InitTensorOp` with:
+///        a. Static and dynamic dims extracted from the first operand of `op`.
+///        b. Elemental type equal to the elemental type of `t`.
+///
+/// This is sufficient because ElementwiseMappable guarantees that "The static
+/// types of all vector (resp. tensor) operands and results must have the same
+/// shape".
+static SmallVector<Value, 4>
+getOrCreateOperandsMatchingResultTypes(OpBuilder &b, Operation *op) {
+  assert(isElementwiseMappableOpOnRankedTensors(op));
+  Location loc = op->getLoc();
+  ValueRange operands = op->getOperands();
+  TypeRange rankedTensorTypes = op->getResultTypes();
+  SmallVector<Value, 4> res;
+  res.reserve(rankedTensorTypes.size());
+  for (Type t : rankedTensorTypes) {
+    // Try to find an operand with type matching the result tensor.
+    bool found = false;
+    for (Value v : operands) {
+      if (v.getType() == t) {
+        found = true;
+        res.push_back(v);
+        break;
+      }
+    }
+    if (found)
+      continue;
+
+    // Extract static / dynamic shape mix from the first operand.
+    Value firstOperand = operands.front();
+    auto rankedTensorType = t.cast<RankedTensorType>();
+    SmallVector<Value, 8> dynamicShape;
+    SmallVector<int64_t, 8> staticShape;
+    dynamicShape.reserve(rankedTensorType.getRank());
+    staticShape.reserve(rankedTensorType.getRank());
+    unsigned idx = 0;
+    for (auto shape : rankedTensorType.getShape()) {
+      staticShape.push_back(shape);
+      if (rankedTensorType.isDynamicDim(idx))
+        dynamicShape.push_back(b.create<DimOp>(loc, firstOperand, idx));
+      ++idx;
+    }
+    // Create init tensor.
+    res.push_back(b.create<linalg::InitTensorOp>(
+        loc, dynamicShape, staticShape, rankedTensorType.getElementType()));
+  }
+  return res;
+}
+
 namespace {
 struct ConvertAnyElementwiseMappableOpOnRankedTensors : public RewritePattern {
   ConvertAnyElementwiseMappableOpOnRankedTensors()
@@ -41,18 +96,19 @@ struct ConvertAnyElementwiseMappableOpOnRankedTensors : public RewritePattern {
         rewriter.getMultiDimIdentityMap(rank));
     SmallVector<StringRef, 6> iteratorTypes(rank,
                                             getParallelIteratorTypeName());
+    auto outputs = getOrCreateOperandsMatchingResultTypes(rewriter, op);
     rewriter.replaceOpWithNewOp<linalg::GenericOp>(
         op, /*resultTensorTypes=*/op->getResultTypes(),
         /*inputs=*/op->getOperands(),
-        /*outputBuffers=*/ValueRange(),
-        /*initTensors=*/ValueRange(),
+        /*outputs=*/outputs,
         /*indexingMaps=*/indexingMaps,
         /*iteratorTypes=*/iteratorTypes,
         /*bodyBuilder=*/
         [&](OpBuilder &builder, Location loc, ValueRange regionArgs) {
           OperationState state(loc, op->getName());
           state.addAttributes(op->getAttrs());
-          state.addOperands(regionArgs);
+          // Only take the input operands in the cloned elementwise op.
+          state.addOperands(regionArgs.take_front(op->getNumOperands()));
           auto resultTypes = llvm::to_vector<6>(
               llvm::map_range(op->getResultTypes(), [](Type type) {
                 return type.cast<TensorType>().getElementType();
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp b/mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
index d9ea7d8ccb294..b525108d22ab6 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp
@@ -169,8 +169,7 @@ getShapeDefiningLoopRange(LinalgOp op, unsigned loopDepth,
   auto maps = op.indexing_maps();
   // Iterate over the inputs and outputs in order.
   // Extract the subranges from the linearized ranges.
-  SmallVector<Value, 8> ios(op.getInputsAndOutputBuffers());
-  for (auto en : llvm::enumerate(ios)) {
+  for (auto en : llvm::enumerate(op.getShapedOperands())) {
     // The method `getRangeFromOperandShape` requires using SubViewOp or
     // SubTensorOps. If the value isnt defined from there continue.
     // todo: The method should be adapted to get the values from
@@ -381,6 +380,8 @@ static bool isSameSubView(Value a, Value b) {
 static Optional<LinalgDependenceGraph::LinalgDependenceGraphElem>
 findFusableProducer(LinalgOp consumer, unsigned consumerIdx,
                     const LinalgDependenceGraph &dependenceGraph) {
+  assert(consumer.hasBufferSemantics() && "revisit usage of shaped operand");
+
   // Only consider RAW and WAW atm.
   for (auto depType : {
            LinalgDependenceGraph::DependenceType::RAW,
@@ -390,26 +391,25 @@ findFusableProducer(LinalgOp consumer, unsigned consumerIdx,
              dependenceGraph.getDependencesInto(consumer, depType),
              [consumerIdx](
                  LinalgDependenceGraph::LinalgDependenceGraphElem elem) {
-               return elem.indexingOpView.operandIndex == consumerIdx;
+               return elem.indexingOpView->getOperandNumber() == consumerIdx;
              })) {
-      auto producer = cast<LinalgOp>(dependence.dependentOpView.op);
 
       // Check that the dependence is indeed on the input `consumerIdx` view.
-      auto consumedView =
-          consumer.getBuffer(dependence.indexingOpView.operandIndex);
-      if (!isSameSubView(consumer.getBuffer(consumerIdx), consumedView))
+      Value consumedView = dependence.indexingOpView->get();
+      if (!isSameSubView(consumer.getShapedOperand(consumerIdx), consumedView))
         continue;
 
       // Consumer consumes this view, `isStructurallyFusableProducer` also
       // checks whether it is a strict subview of the producer view.
-      auto producedView =
-          producer.getBuffer(dependence.dependentOpView.operandIndex);
+      auto producer = cast<LinalgOp>(dependence.dependentOpView->getOwner());
+      Value producedView = dependence.dependentOpView->get();
       LLVM_DEBUG(llvm::dbgs()
                  << "\n"
                  << LinalgDependenceGraph::getDependenceTypeStr(depType)
-                 << "producer: " << *producer.getOperation()
-                 << " view: " << producedView << " output index: "
-                 << dependence.dependentOpView.operandIndex -
+                 << "producer: " << *dependence.dependentOpView->getOwner()
+                 << " view: " << dependence.dependentOpView->get()
+                 << " output index: "
+                 << dependence.dependentOpView->getOperandNumber() -
                         producer.getNumInputs()
                  << "\n");
       (void)producedView;
@@ -433,13 +433,15 @@ mlir::linalg::fuseProducerOfBuffer(OpBuilder &b, LinalgOp consumer,
   if (!fusableDependence)
     return {};
 
-  LinalgOp producerOp = cast<LinalgOp>(fusableDependence->dependentOpView.op);
+  LinalgOp producerOp =
+      cast<LinalgOp>(fusableDependence->dependentOpView->getOwner());
   // If producer is already in the same block as consumer, we are done.
   if (consumer->getBlock() == producerOp->getBlock())
     return {};
 
-  unsigned producerIdx = fusableDependence->dependentOpView.operandIndex -
-                         producerOp.getNumInputs();
+  unsigned producerIdx =
+      fusableDependence->dependentOpView->getOperandNumber() -
+      producerOp.getNumInputs();
   Value consumerView = consumer.getShapedOperand(consumerIdx);
 
   // Must be a subview or a slice to guarantee there are loops we can fuse
@@ -548,12 +550,12 @@ static AffineMap pruneReductionDimsFromMap(ArrayRef<Attribute> iteratorTypes,
 ///       inverse(producerIndexMap).compose(consumerIndexMap)
 static Optional<AffineMap> getConsumerLoopToProducerLoopMap(
     LinalgDependenceGraph::LinalgDependenceGraphElem dependence) {
-  auto producer = cast<LinalgOp>(dependence.dependentOpView.op);
+  auto producer = cast<LinalgOp>(dependence.dependentOpView->getOwner());
   AffineMap producerIndexingMap =
-      producer.getIndexingMap(dependence.dependentOpView.operandIndex);
-  auto consumer = cast<LinalgOp>(dependence.indexingOpView.op);
+      producer.getIndexingMap(dependence.dependentOpView->getOperandNumber());
+  auto consumer = cast<LinalgOp>(dependence.indexingOpView->getOwner());
   AffineMap consumerIndexingMap =
-      consumer.getIndexingMap(dependence.indexingOpView.operandIndex);
+      consumer.getIndexingMap(dependence.indexingOpView->getOperandNumber());
 
   AffineMap prunedProducerIndexingMap = pruneReductionDimsFromMap(
       producer.iterator_types().getValue(), producerIndexingMap);
@@ -733,14 +735,14 @@ FusableOpDependencesTy mlir::linalg::findAllFusableDependences(
   DenseMap<Operation *, AffineMap> fusedProducerIndexingMap;
   for (LinalgOp op : reverse(ops)) {
     for (auto operandIndex :
-         llvm::seq<unsigned>(0, op.getNumInputsAndOutputBuffers())) {
+         llvm::seq<unsigned>(0, op.getNumShapedOperands())) {
       Optional<LinalgDependenceGraph::LinalgDependenceGraphElem>
           fusableDependence =
               findFusableProducer(op, operandIndex, dependenceGraph);
       if (!fusableDependence)
         continue;
       LinalgOp producerOp =
-          cast<LinalgOp>(fusableDependence->dependentOpView.op);
+          cast<LinalgOp>(fusableDependence->dependentOpView->getOwner());
       // Do not fuse dependences that are to operations not in the same basic
       // block. This avoid moving fused operations across loops that might
       // themselves carry dependency making the fusion illegal.
@@ -750,7 +752,8 @@ FusableOpDependencesTy mlir::linalg::findAllFusableDependences(
       }
       // Make sure that the indexing map of the view used for fusion in the
       // producer is a projected permutation.
-      unsigned producerIdx = fusableDependence->dependentOpView.operandIndex;
+      unsigned producerIdx =
+          fusableDependence->dependentOpView->getOperandNumber();
       AffineMap producerMap = producerOp.getIndexingMap(producerIdx);
       if (!producerMap.isProjectedPermutation()) {
         op.emitRemark(
@@ -760,7 +763,8 @@ FusableOpDependencesTy mlir::linalg::findAllFusableDependences(
         return FusableOpDependencesTy{};
       }
 
-      unsigned consumerIdx = fusableDependence->indexingOpView.operandIndex;
+      unsigned consumerIdx =
+          fusableDependence->indexingOpView->getOperandNumber();
       AffineMap consumerMap = op.getIndexingMap(consumerIdx);
       if (!consumerMap.isProjectedPermutation()) {
         op.emitRemark(
diff --git a/mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp b/mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
index 22e03c1e2f92a..b1ea07309b4f8 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/FusionOnTensors.cpp
@@ -128,7 +128,9 @@ static void generateFusedTensorOpRegion(PatternRewriter &rewriter,
   for (auto consumerArg : llvm::enumerate(consumerBlock.getArguments())) {
     if (consumerArg.index() == consumerIdx + numConsumerIndices) {
       // Map the arguments for the args from the producer.
-      for (auto producerArg : llvm::enumerate(producerBlock.getArguments())) {
+      for (auto producerArg :
+           llvm::enumerate(producerBlock.getArguments().take_front(
+               producer.getNumInputs() + numProducerIndices))) {
         // If producer is an indexed_generic op, map the indices from consumer
         // loop to producer loop (because the fusedOp is built based on
         // consumer's perspective).
@@ -213,7 +215,6 @@ fuseTensorOpsImpl(LinalgOp producer, LinalgOp consumer, unsigned consumerIdx,
                         consumerIndexMaps.end());
 
   // Generate the fused op.
-  // Tensor-level fusion is only on ops without initTensors and outputBuffers.
   LinalgOp fusedOp;
   if (isa<GenericOp>(producer.getOperation()) &&
       isa<GenericOp>(consumer.getOperation())) {
@@ -221,8 +222,8 @@ fuseTensorOpsImpl(LinalgOp producer, LinalgOp consumer, unsigned consumerIdx,
         rewriter
             .create<GenericOp>(consumer.getLoc(), consumer->getResultTypes(),
                                /*inputs=*/fusedOperands,
-                               /*outputBuffers=*/ValueRange{},
-                               /*initTensors=*/ValueRange{},
+                               // TODO: handle outputs.
+                               consumer.getOutputs(),
                                rewriter.getArrayAttr(fusedIndexMaps),
                                consumer.iterator_types(),
                                /*doc=*/nullptr,
@@ -230,18 +231,18 @@ fuseTensorOpsImpl(LinalgOp producer, LinalgOp consumer, unsigned consumerIdx,
                                /*sparse=*/nullptr)
             .getOperation();
   } else {
-    fusedOp = rewriter
-                  .create<IndexedGenericOp>(
-                      consumer.getLoc(), consumer->getResultTypes(),
-                      /*inputs=*/fusedOperands,
-                      /*outputBuffers=*/ValueRange{},
-                      /*initTensors=*/ValueRange{},
-                      rewriter.getArrayAttr(fusedIndexMaps),
-                      consumer.iterator_types(),
-                      /*doc=*/nullptr,
-                      /*library_call=*/nullptr,
-                      /*sparse=*/nullptr)
-                  .getOperation();
+    fusedOp =
+        rewriter
+            .create<IndexedGenericOp>(
+                consumer.getLoc(), consumer->getResultTypes(),
+                /*inputs=*/fusedOperands,
+                // TODO: handle outputs.
+                consumer.getOutputs(), rewriter.getArrayAttr(fusedIndexMaps),
+                consumer.iterator_types(),
+                /*doc=*/nullptr,
+                /*library_call=*/nullptr,
+                /*sparse=*/nullptr)
+            .getOperation();
   }
 
   // Construct an AffineMap from consumer loops to producer loops.
@@ -430,6 +431,42 @@ static bool isFusableWithReshapeByDimExpansion(LinalgOp linalgOp,
          });
 }
 
+// Get the output tensor to use for the expanded operation. Creates an
+// `linalg.init_tensor` operation to materialize the tensor that carries the
+// shape information.
+static Value getOutputValueForExpansion(
+    OpBuilder &builder, Location loc, AffineMap outputIndexingMap, Value result,
+    ArrayRef<SmallVector<int64_t, 4>> origDimToExpandedShapeMap) {
+  SmallVector<Value, 4> dynamicDims;
+  SmallVector<int64_t, 4> staticDims;
+  ShapedType resultType = result.getType().cast<ShapedType>();
+  ArrayRef<int64_t> origShape = resultType.getShape();
+  for (AffineExpr expr : outputIndexingMap.getResults()) {
+    unsigned origDimPos = expr.cast<AffineDimExpr>().getPosition();
+    ArrayRef<int64_t> expandedShape(origDimToExpandedShapeMap[origDimPos]);
+    bool foundDynamic = false;
+    int64_t linearizedShape = 1;
+    for (int64_t extent : expandedShape) {
+      if (ShapedType::isDynamic(extent)) {
+        assert(!foundDynamic &&
+               "Expanded dimensions of reshape can have only one dynamic dim");
+        staticDims.push_back(ShapedType::kDynamicSize);
+        foundDynamic = true;
+        continue;
+      }
+      staticDims.push_back(extent);
+      linearizedShape *= extent;
+    }
+    if (ShapedType::isDynamic(origShape[origDimPos])) {
+      Value origDim = builder.create<DimOp>(loc, result, origDimPos);
+      dynamicDims.push_back(builder.create<UnsignedDivIOp>(
+          loc, origDim, builder.create<ConstantIndexOp>(loc, linearizedShape)));
+    }
+  }
+  return builder.create<linalg::InitTensorOp>(loc, dynamicDims, staticDims,
+                                              resultType.getElementType());
+}
+
 /// Implements the fusion of a tensor_reshape op and a generic/indexed_generic
 /// op as explained in `isFusableWithReshapeByExpansion`. Assumes that those
 /// conditions have been satisfied.
@@ -548,7 +585,7 @@ fuseWithReshapeByExpansion(LinalgOp linalgOp, TensorReshapeOp reshapeOp,
       expandedOpOperands.push_back(reshapeOp.src());
       continue;
     }
-    AffineMap indexingMap = linalgOp.getIndexingMap(operand.index());
+    AffineMap indexingMap = linalgOp.getInputIndexingMap(operand.index());
     SmallVector<ReassociationIndices, 4> reassociation;
     SmallVector<int64_t, 4> expandedOperandShape;
     getReshapeInfo(indexingMap, reassociation, expandedOperandShape);
@@ -563,17 +600,17 @@ fuseWithReshapeByExpansion(LinalgOp linalgOp, TensorReshapeOp reshapeOp,
       expandedOpOperands.push_back(operand.value());
     }
   }
-  SmallVector<Type, 1> resultTypes;
+
+  Location loc = linalgOp.getLoc();
+  SmallVector<Value, 1> outputs;
   SmallVector<SmallVector<ReassociationIndices, 4>, 1> resultReassociation;
-  for (auto result : llvm::enumerate(linalgOp->getResults())) {
-    AffineMap indexingMap =
-        linalgOp.getIndexingMap(linalgOp.getNumInputs() + result.index());
+  for (auto result : llvm::enumerate(linalgOp.getOutputs())) {
+    AffineMap indexingMap = linalgOp.getOutputIndexingMap(result.index());
     SmallVector<ReassociationIndices, 4> reassociation;
     SmallVector<int64_t, 4> expandedResultShape;
     getReshapeInfo(indexingMap, reassociation, expandedResultShape);
-    resultTypes.push_back(RankedTensorType::get(
-        expandedResultShape,
-        result.value().getType().cast<ShapedType>().getElementType()));
+    outputs.push_back(getOutputValueForExpansion(
+        rewriter, loc, indexingMap, result.value(), expandedDimsShape));
     resultReassociation.emplace_back(std::move(reassociation));
   }
 
@@ -581,11 +618,11 @@ fuseWithReshapeByExpansion(LinalgOp linalgOp, TensorReshapeOp reshapeOp,
   SmallVector<StringRef, 4> iteratorTypes(remapping.back(),
                                           getParallelIteratorTypeName());
 
+  TypeRange resultTypes = ValueRange(outputs).getTypes();
   LinalgOp fusedOp = createLinalgOpOfSameType(
       linalgOp, rewriter, linalgOp.getLoc(), resultTypes,
-      /*inputs=*/expandedOpOperands,
-      /*outputBuffers=*/ValueRange{},
-      /*initTensors=*/ValueRange{}, expandedOpIndexingMaps, iteratorTypes);
+      /*inputs=*/expandedOpOperands, outputs, expandedOpIndexingMaps,
+      iteratorTypes);
   Region &fusedRegion = fusedOp->getRegion(0);
   Region &originalRegion = linalgOp->getRegion(0);
 
@@ -656,6 +693,47 @@ fuseWithReshapeByExpansion(LinalgOp linalgOp, TensorReshapeOp reshapeOp,
   return resultVals;
 }
 
+static Value
+getOutputValueForLinearization(OpBuilder &builder, Location loc,
+                               Value origOutput,
+                               ArrayRef<AffineMap> reassociationMaps) {
+  SmallVector<Value, 4> dynamicDims;
+  SmallVector<int64_t, 4> staticDims;
+  auto shapedType = origOutput.getType().cast<ShapedType>();
+  ArrayRef<int64_t> origShape = shapedType.getShape();
+  for (auto map : reassociationMaps) {
+    Optional<Value> dynamicDim;
+    int64_t staticLinearizedShape = 1;
+    for (AffineDimExpr expr :
+         llvm::map_range(map.getResults(), [](AffineExpr e) {
+           return e.cast<AffineDimExpr>();
+         })) {
+      unsigned pos = expr.getPosition();
+      if (ShapedType::isDynamic(origShape[pos])) {
+        Value dim = builder.create<DimOp>(loc, origOutput, pos);
+        if (dynamicDim) {
+          dynamicDim = builder.create<MulIOp>(loc, dynamicDim.getValue(), dim);
+        } else {
+          dynamicDim = dim;
+        }
+      } else {
+        staticLinearizedShape *= origShape[pos];
+      }
+    }
+    if (dynamicDim) {
+      dynamicDim = builder.create<MulIOp>(
+          loc, dynamicDim.getValue(),
+          builder.create<ConstantIndexOp>(loc, staticLinearizedShape));
+      dynamicDims.push_back(dynamicDim.getValue());
+      staticDims.push_back(ShapedType::kDynamicSize);
+    } else {
+      staticDims.push_back(staticLinearizedShape);
+    }
+  }
+  return builder.create<InitTensorOp>(loc, dynamicDims, staticDims,
+                                      shapedType.getElementType());
+}
+
 namespace {
 
 /// Pattern to fold tensor_reshape op with its consumer by using the source of
@@ -704,6 +782,8 @@ struct FoldProducerReshapeOpByLinearization
       // Compute the fused operands list,
       SmallVector<Value, 2> fusedOperands(linalgOp.getInputs());
       fusedOperands[operand.index()] = reshapeOp.src();
+      fusedOperands.append(linalgOp.getOutputs().begin(),
+                           linalgOp.getOutputs().end());
 
       // Compute indexing_maps for the fused operation. The indexing_maps for
       // the operands of the consumers that arent fused are the same.
@@ -736,7 +816,7 @@ struct FoldProducerReshapeOpByLinearization
         rewriter.eraseOp(reshapeOp);
       return success();
     }
-    return op.emitRemark("no fusion candidates found");
+    return failure();
   }
 };
 
@@ -816,12 +896,15 @@ struct FoldConsumerReshapeOpByLinearization
     if (!inversePermutation(concatAffineMaps(fusedIndexMaps)))
       return reshapeOp.emitRemark("fused op loop bound computation failed");
 
+    Location loc = producer.getLoc();
+    Value output =
+        getOutputValueForLinearization(rewriter, loc, producer.getOutputs()[0],
+                                       reshapeOp.getReassociationMaps());
     LinalgOp fusedOp = createLinalgOpOfSameType(
-        producer, rewriter, rewriter.getUnknownLoc(), reshapeOp.getResultType(),
+        producer, rewriter, loc, reshapeOp.getResultType(),
         /*inputs=*/producer.getInputs(),
-        /*outputBuffers=*/ValueRange{},
-        /*initTensors=*/ValueRange{}, // no init tensors for now.
-        rewriter.getAffineMapArrayAttr(fusedIndexMaps),
+        // TODO: handle outputs.
+        /*outputs=*/output, rewriter.getAffineMapArrayAttr(fusedIndexMaps),
         producer.iterator_types(),
         /*doc=*/nullptr,
         /*library_call=*/nullptr,
@@ -902,8 +985,7 @@ struct FoldSplatConstants : public OpRewritePattern<LinalgOpTy> {
           linalgOp, rewriter, rewriter.getUnknownLoc(),
           linalgOp->getResultTypes(),
           /*inputs=*/fusedOperands,
-          /*outputBuffers=*/ValueRange{},
-          /*initTensors=*/ValueRange{}, // no init tensors for now.
+          /*outputs=*/linalgOp.getOutputs(),
           rewriter.getAffineMapArrayAttr(fusedIndexMaps),
           linalgOp.iterator_types(),
           /*doc=*/nullptr,
@@ -915,7 +997,7 @@ struct FoldSplatConstants : public OpRewritePattern<LinalgOpTy> {
       Region &linalgOpRegion = linalgOp->getRegion(0);
       Block &entryBlock = *linalgOpRegion.begin();
       unsigned argIndex = entryBlock.getNumArguments() -
-                          linalgOp.getNumInputs() + operand.index();
+                          linalgOp.getNumShapedOperands() + operand.index();
       BlockAndValueMapping mapping;
       mapping.map(entryBlock.getArgument(argIndex), scalarConstant);
       Region &fusedRegion = fusedOp->getRegion(0);
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Generalization.cpp b/mlir/lib/Dialect/Linalg/Transforms/Generalization.cpp
index 3496a77969881..454bbbe3578a4 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Generalization.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Generalization.cpp
@@ -45,8 +45,8 @@ static linalg::GenericOp createGenericOpFromNamedOp(linalg::LinalgOp namedOp,
   SmallVector<Type, 4> types(resultTypes.begin(), resultTypes.end());
 
   return builder.create<linalg::GenericOp>(
-      namedOp.getLoc(), types, namedOp.getInputs(), namedOp.getOutputBuffers(),
-      namedOp.getInitTensors(), indexingMaps, iterators,
+      namedOp.getLoc(), types, namedOp.getInputs(), namedOp.getOutputs(),
+      indexingMaps, iterators,
       [&regionBuilder](OpBuilder &bodyBuilder, Location loc, ValueRange) {
         edsc::ScopedContext scope(bodyBuilder, loc);
         regionBuilder(*bodyBuilder.getBlock());
@@ -153,8 +153,8 @@ linalg::GenericOp GeneralizeConvOp::createGenericOp(linalg::ConvOp convOp,
       llvm::to_vector<4>(convOp.iterator_types().getAsValueRange<StringAttr>());
   return builder.create<linalg::GenericOp>(
       convOp.getLoc(), /*resultTensorTypes=*/ArrayRef<Type>(),
-      convOp.getInputBuffers(), convOp.getOutputBuffers(),
-      /*initTensors=*/ValueRange(), indexingMaps, iterators,
+      convOp.getInputBuffers(), convOp.getOutputBuffers(), indexingMaps,
+      iterators,
       [](OpBuilder &bodyBuilder, Location bodyLoc, ValueRange bodyArgs) {
         Value mul =
             bodyBuilder.create<MulFOp>(bodyLoc, bodyArgs[0], bodyArgs[1]);
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp b/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
index 9e7e7efdd1361..a1797fde7da6b 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Hoisting.cpp
@@ -111,7 +111,7 @@ void mlir::linalg::hoistRedundantVectorTransfers(FuncOp func) {
       vector::TransferWriteOp transferWrite;
       for (auto *sliceOp : llvm::reverse(forwardSlice)) {
         auto candidateWrite = dyn_cast<vector::TransferWriteOp>(sliceOp);
-        if (!candidateWrite || candidateWrite.memref() != transferRead.memref())
+        if (!candidateWrite || candidateWrite.source() != transferRead.source())
           continue;
         transferWrite = candidateWrite;
       }
@@ -142,7 +142,7 @@ void mlir::linalg::hoistRedundantVectorTransfers(FuncOp func) {
       DominanceInfo dom(loop);
       if (!dom.properlyDominates(transferRead.getOperation(), transferWrite))
         return WalkResult::advance();
-      for (auto &use : transferRead.memref().getUses()) {
+      for (auto &use : transferRead.source().getUses()) {
         if (!dom.properlyDominates(loop, use.getOwner()))
           continue;
         if (use.getOwner() == transferRead.getOperation() ||
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp b/mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp
index a7f0660281b5c..cac0ae0d081c4 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp
@@ -64,7 +64,7 @@ LinalgOp mlir::linalg::interchange(LinalgOp op,
   assert(permutationMap && "expected permutation to be invertible");
   SmallVector<Attribute, 4> newIndexingMaps;
   auto indexingMaps = op.indexing_maps().getValue();
-  for (unsigned i = 0, e = op.getNumInputsAndOutputs(); i != e; ++i) {
+  for (unsigned i = 0, e = op.getNumShapedOperands(); i != e; ++i) {
     AffineMap m = indexingMaps[i].cast<AffineMapAttr>().getValue();
     if (!permutationMap.isEmpty())
       m = m.compose(permutationMap);
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp b/mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
index 073673bc33f86..329cc88bd2aed 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp
@@ -172,7 +172,8 @@ LinalgOpInstancePromotionOptions::LinalgOpInstancePromotionOptions(
     LinalgOp linalgOp, const LinalgPromotionOptions &options)
     : subViews(), dynamicBuffers(options.dynamicBuffers),
       alignment(options.alignment) {
-  unsigned nBuffers = linalgOp.getNumInputsAndOutputBuffers();
+  assert(linalgOp.hasBufferSemantics() && "revisit usage of shaped operand");
+  unsigned nBuffers = linalgOp.getNumShapedOperands();
   auto vUseFullTileBuffers =
       options.useFullTileBuffers.getValueOr(llvm::SmallBitVector());
   vUseFullTileBuffers.resize(nBuffers, options.useFullTileBuffersDefault);
@@ -180,7 +181,7 @@ LinalgOpInstancePromotionOptions::LinalgOpInstancePromotionOptions(
   for (unsigned idx = 0; idx != nBuffers; ++idx) {
     if (options.operandsToPromote && !options.operandsToPromote->count(idx))
       continue;
-    auto *op = linalgOp.getBuffer(idx).getDefiningOp();
+    auto *op = linalgOp.getShapedOperand(idx).getDefiningOp();
     if (auto sv = dyn_cast_or_null<SubViewOp>(op)) {
       subViews[idx] = sv;
       useFullTileBuffers[sv] = vUseFullTileBuffers[idx];
@@ -326,10 +327,10 @@ promoteSubViews(OpBuilder &b, LinalgOp op,
   // operands are not views. This is to support cases such as FillOp taking
   // extra scalars etc.  Keep a reference to output buffers;
   SmallVector<Value, 8> opViews;
-  opViews.reserve(op.getNumInputsAndOutputs());
+  opViews.reserve(op.getNumShapedOperands());
   SmallVector<std::pair<Value, Value>, 8> writebackViews;
   writebackViews.reserve(promotedBuffersAndViews->size());
-  for (auto view : llvm::enumerate(op.getInputsAndOutputBuffers())) {
+  for (auto view : llvm::enumerate(op.getShapedOperands())) {
     if (options.subViews.count(view.index()) != 0) {
       if (options.useFullTileBuffers[view.value()])
         opViews.push_back(
@@ -371,7 +372,7 @@ mlir::linalg::promoteSubviewsPrecondition(Operation *op,
   if (!linOp || !linOp.hasBufferSemantics())
     return failure();
   // Check that at least one of the requested operands is indeed a subview.
-  for (auto en : llvm::enumerate(linOp.getInputsAndOutputBuffers())) {
+  for (auto en : llvm::enumerate(linOp.getShapedOperands())) {
     auto sv = isa_and_nonnull<SubViewOp>(en.value().getDefiningOp());
     if (sv) {
       if (!options.operandsToPromote.hasValue() ||
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp b/mlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
index fed2eedd41a45..a6b7277e47e33 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Sparsification.cpp
@@ -334,7 +334,7 @@ struct CodeGen {
 /// Helper method to inspect sparse annotations in the linalg operation.
 /// Fills the per-dimension sparsity information for all tensors.
 static void findSparseAnnotations(Merger &merger, linalg::GenericOp op) {
-  unsigned numTensors = op.getNumInputsAndOutputs();
+  unsigned numTensors = op.getNumShapedOperands();
   ArrayAttr sparseAttr = op.sparseAttr();
   for (unsigned t = 0; t < numTensors; t++) {
     auto map = op.getIndexingMap(t);
@@ -466,8 +466,8 @@ static unsigned buildLattices(Merger &merger, linalg::GenericOp op,
     // set to the undefined index in that dimension. An invariant expression
     // is set to a synthetic tensor with undefined indices only.
     unsigned s = merger.addSet();
-    unsigned t = kind == Kind::kTensor ? merger.exp(exp).e0
-                                       : op.getNumInputsAndOutputs();
+    unsigned t =
+        kind == Kind::kTensor ? merger.exp(exp).e0 : op.getNumShapedOperands();
     merger.set(s).push_back(merger.addLat(t, idx, exp));
     return s;
   }
@@ -504,7 +504,7 @@ static Type genIntType(PatternRewriter &rewriter, linalg::SparseIntType tp) {
 static void genBuffers(Merger &merger, CodeGen &codegen,
                        PatternRewriter &rewriter, linalg::GenericOp op) {
   Location loc = op.getLoc();
-  unsigned numTensors = op.getNumInputsAndOutputs();
+  unsigned numTensors = op.getNumShapedOperands();
   unsigned numInputs = op.getNumInputs();
   assert(numTensors == numInputs + 1);
 
@@ -544,7 +544,7 @@ static void genBuffers(Merger &merger, CodeGen &codegen,
           up = codegen.sizes[i];
           assert(up); // TODO: what else?
         } else {
-          Value arg = t < numInputs ? op.getInput(t) : op.getInitTensor(0);
+          Value arg = t < numInputs ? op.getInput(t) : op.getInitTensors()[0];
           up = rewriter.create<DimOp>(loc, arg, d);
         }
         args.push_back(up);
@@ -597,7 +597,7 @@ static void genTensorStore(Merger &merger, CodeGen &codegen,
                            PatternRewriter &rewriter, linalg::GenericOp op,
                            unsigned tensor, Value rhs) {
   // Test if this is a scalarized reduction.
-  unsigned lhs = op.getNumInputsAndOutputs() - 1;
+  unsigned lhs = op.getNumShapedOperands() - 1;
   if (lhs == tensor && codegen.redVal) {
     codegen.redVal = rhs;
     return;
@@ -670,7 +670,7 @@ static void genInvariants(Merger &merger, CodeGen &codegen,
         atLevel = true;
     }
     // All exhausted at this level (atLevel denotes exactly at this level).
-    unsigned lhs = op.getNumInputsAndOutputs() - 1;
+    unsigned lhs = op.getNumShapedOperands() - 1;
     if (lhs == tensor) {
       codegen.redExp = hoist ? exp : -1u;
     } else if (atLevel) {
@@ -995,7 +995,7 @@ static void genStmt(Merger &merger, CodeGen &codegen, PatternRewriter &rewriter,
                     unsigned exp, unsigned at) {
   // At each leaf, assign remaining tensor (sub)expression to output tensor.
   if (at == topSort.size()) {
-    unsigned lhs = op.getNumInputsAndOutputs() - 1;
+    unsigned lhs = op.getNumShapedOperands() - 1;
     Value rhs = genExp(merger, codegen, rewriter, op, exp);
     genTensorStore(merger, codegen, rewriter, op, lhs, rhs);
     return;
@@ -1073,7 +1073,7 @@ static void genStmt(Merger &merger, CodeGen &codegen, PatternRewriter &rewriter,
   Value red = codegen.redVal;
   if (red) {
     codegen.redVal = merger.exp(codegen.redExp).val = Value(); // end chain
-    unsigned lhs = op.getNumInputsAndOutputs() - 1;
+    unsigned lhs = op.getNumShapedOperands() - 1;
     genTensorStore(merger, codegen, rewriter, op, lhs, red);
   }
   codegen.loops[idx] = Value();
@@ -1095,7 +1095,7 @@ struct GenericOpSparsifier : public OpRewritePattern<linalg::GenericOp> {
     if (!op.hasSparseSemantics())
       return failure();
     assert(op.getNumOutputs() == 1);
-    unsigned numTensors = op.getNumInputsAndOutputs();
+    unsigned numTensors = op.getNumShapedOperands();
     unsigned numLoops = op.iterator_types().getValue().size();
     Merger merger(numTensors, numLoops);
     findSparseAnnotations(merger, op);
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp b/mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
index 423d687c1eb8c..f323d2e50435e 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
@@ -375,9 +375,9 @@ tileLinalgOpImpl(OpBuilder &b, LinalgOp op, ValueRange tileSizes,
   // 2. Create the tiled loops.
   LinalgOp res = op;
   SmallVector<Value, 4> ivs, tensorResults;
-  auto initTensors = op.getInitTensors();
+  auto outputTensors = op.getOutputTensors();
   GenerateLoopNest<LoopTy>::doit(
-      loopRanges, /*iterArgInitValues*/ initTensors, iteratorTypes,
+      loopRanges, /*iterArgInitValues*/ outputTensors, iteratorTypes,
       [&](ValueRange localIvs, ValueRange iterArgs) -> scf::ValueVector {
         auto &b = ScopedContext::getBuilderRef();
         auto loc = ScopedContext::getLocation();
@@ -392,14 +392,16 @@ tileLinalgOpImpl(OpBuilder &b, LinalgOp op, ValueRange tileSizes,
         else
           interchangedIvs.assign(ivs.begin(), ivs.end());
 
-        assert(op.getNumInitTensors() == iterArgs.size() &&
-               "num init tensors must match number of loop iter arguments");
-        // This uses knowledge about position of the init tensor in the list
-        // of operands.
-        auto operands = llvm::to_vector<4>(op.getShapedOperands());
-        std::copy(iterArgs.begin(), iterArgs.end(),
-                  operands.begin() + op.getNumInputsAndOutputBuffers());
+        assert(op.getNumOutputTensors() == iterArgs.size() &&
+               "num output tensors must match number of loop iter arguments");
 
+        auto operands = llvm::to_vector<4>(op.getInputs());
+        SmallVector<Value, 4> outputBuffers = op.getOutputBuffers();
+        // TODO: thanks to simplifying assumption we do not need to worry about
+        // order of output buffers and tensors: there is only ever one kind.
+        assert(outputBuffers.empty() || iterArgs.empty());
+        operands.append(outputBuffers.begin(), outputBuffers.end());
+        operands.append(iterArgs.begin(), iterArgs.end());
         SmallVector<Value, 4> tiledOperands =
             makeTiledShapes(b, loc, op, operands, shapeSizesToLoopsMap,
                             interchangedIvs, tileSizes, allShapeSizes);
@@ -407,41 +409,31 @@ tileLinalgOpImpl(OpBuilder &b, LinalgOp op, ValueRange tileSizes,
         tiledOperands.append(nonShapedOperands.begin(),
                              nonShapedOperands.end());
 
-        // If LinalgOp has results, they must all be tied to init tensors.
-        // We enforce this to ensure all tiled ops have been rewritten in
-        // "init tensor" form. This ensures tiling has anchor values into which
-        // to subtensor / subtensor_insert. Otherwise tiling would need to
-        // allocate which is not acceptable.
-        // This would not be the case with a special terminator op that
-        // generates the whole tensor (instead of inserting a subtensor). But
-        // the generator-based abstraction has other issues.
-        assert(op.getNumInitTensors() == op->getNumResults() &&
-               "expected same number of init tensors as number of results");
-
-        // Handle init tensor operands.
-        // This uses knowledge about position of the init tensor in the list
-        // of operands.
-        // TODO: InterfaceAdaptor ?
+        // TODO: use an interface/adaptor to avoid leaking position in
+        // `tiledOperands`.
         SmallVector<Type, 4> resultTensorTypes;
-        for (auto idx : llvm::seq<unsigned>(0, op.getNumInitTensors()))
+        for (OpOperand *opOperand : op.getOutputTensorsOpOperands())
           resultTensorTypes.push_back(
-              tiledOperands[op.getNumInputsAndOutputBuffers() + idx].getType());
+              tiledOperands[opOperand->getOperandNumber()].getType());
 
         res = op.clone(b, loc, resultTensorTypes, tiledOperands);
 
-        // Insert a subtensor_insert for each init subtensor.
-        for (unsigned idx = 0, e = op.getNumInitTensors(); idx != e; ++idx) {
-          Value initTensor =
-              tiledOperands[op.getNumInputsAndOutputBuffers() + idx];
-          if (auto subtensor = initTensor.getDefiningOp<SubTensorOp>()) {
+        // Insert a subtensor_insert for each output tensor.
+        unsigned resultIdx = 0;
+        for (OpOperand *opOperand : op.getOutputTensorsOpOperands()) {
+          // TODO: use an interface/adaptor to avoid leaking position in
+          // `tiledOperands`.
+          Value outputTensor = tiledOperands[opOperand->getOperandNumber()];
+          if (auto subtensor = outputTensor.getDefiningOp<SubTensorOp>()) {
             tensorResults.push_back(b.create<SubTensorInsertOp>(
-                loc, subtensor.source().getType(), res->getResult(idx),
+                loc, subtensor.source().getType(), res->getResult(resultIdx),
                 subtensor.source(), subtensor.offsets(), subtensor.sizes(),
                 subtensor.strides(), subtensor.static_offsets(),
                 subtensor.static_sizes(), subtensor.static_strides()));
           } else {
-            tensorResults.push_back(res->getResult(idx));
+            tensorResults.push_back(res->getResult(resultIdx));
           }
+          ++resultIdx;
         }
         return scf::ValueVector(tensorResults.begin(), tensorResults.end());
       },
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp b/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
index 804ae6681f8cb..c5d811c41edb0 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
@@ -125,17 +125,6 @@ LogicalResult mlir::linalg::LinalgBaseTilingPattern::matchAndRewriteBase(
   if (failed(marker.checkAndNotify(rewriter, linalgOp)))
     return failure();
 
-  // If LinalgOp has results, they must all be tied to init tensors.
-  // We enforce this to ensure all tiled ops have been rewritten in
-  // "init tensor" form. This ensures tiling has anchor values into which to
-  // subtensor / subtensor_insert. Otherwise tiling would need to allocate which
-  // is not acceptable.
-  // This would not be the case with a special terminator op that generates the
-  // whole tensor (instead of inserting a subtensor). But the generator-based
-  // abstraction has other issues.
-  if (linalgOp.getNumInitTensors() != linalgOp->getNumResults())
-    return failure();
-
   Optional<TiledLinalgOp> res = tileLinalgOp(rewriter, linalgOp, options);
 
   if (!res)
@@ -174,10 +163,10 @@ LogicalResult mlir::linalg::LinalgBaseTileAndFusePattern::matchAndRewrite(
   producers.insert(linalgOp);
   for (auto dependence : dependenceGraph.getDependentOperations(linalgOp)) {
     if (!fusionOptions.indicesToFuse.count(
-            dependence.indexingOpView.operandIndex))
+            dependence.indexingOpView->getOperandNumber()))
       continue;
-    if (isa<LinalgOp>(dependence.dependentOpView.op))
-      producers.insert(dependence.dependentOpView.op);
+    if (isa<LinalgOp>(dependence.dependentOpView->getOwner()))
+      producers.insert(dependence.dependentOpView->getOwner());
   }
 
   SmallVector<LinalgOp, 1> fusionOps;
diff --git a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
index 2df1a9469eabc..23e452df91842 100644
--- a/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
+++ b/mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
@@ -199,9 +199,8 @@ class GenericVectorizer {
     // block argument.
     auto scalarArg = scalarValue.cast<BlockArgument>();
     assert(scalarArg.getOwner() == &generic.region().front());
-    Value vector_arg =
-        generic.getInputsAndOutputBuffers()[scalarArg.getArgNumber()];
-    Value vectorResult = transferReadVector(builder, vector_arg);
+    Value vectorArg = generic.getShapedOperand(scalarArg.getArgNumber());
+    Value vectorResult = transferReadVector(builder, vectorArg);
     valueCache[scalarArg] = vectorResult;
     return vectorResult;
   }
@@ -277,7 +276,7 @@ static void vectorizeElementwise(linalg::GenericOp op, OpBuilder &builder) {
 LogicalResult mlir::linalg::vectorizeLinalgOpPrecondition(Operation *op) {
   auto linalgOp = cast<linalg::LinalgOp>(op);
   // All types must be static shape to go to vector.
-  for (Value operand : linalgOp.getInputsAndOutputBuffers())
+  for (Value operand : linalgOp.getShapedOperands())
     if (!operand.getType().cast<ShapedType>().hasStaticShape())
       return failure();
   for (Type outputTensorType : linalgOp.getOutputTensorTypes())
@@ -411,7 +410,7 @@ LogicalResult LinalgCopyVTRForwardingPattern::matchAndRewrite(
     vector::TransferReadOp xferOp, PatternRewriter &rewriter) const {
 
   // Transfer into `view`.
-  Value viewOrAlloc = xferOp.memref();
+  Value viewOrAlloc = xferOp.source();
   if (!viewOrAlloc.getDefiningOp<ViewOp>() &&
       !viewOrAlloc.getDefiningOp<AllocOp>())
     return failure();
@@ -487,7 +486,7 @@ LogicalResult LinalgCopyVTRForwardingPattern::matchAndRewrite(
 LogicalResult LinalgCopyVTWForwardingPattern::matchAndRewrite(
     vector::TransferWriteOp xferOp, PatternRewriter &rewriter) const {
   // Transfer into `viewOrAlloc`.
-  Value viewOrAlloc = xferOp.memref();
+  Value viewOrAlloc = xferOp.source();
   if (!viewOrAlloc.getDefiningOp<ViewOp>() &&
       !viewOrAlloc.getDefiningOp<AllocOp>())
     return failure();
diff --git a/mlir/lib/Dialect/Linalg/Utils/Utils.cpp b/mlir/lib/Dialect/Linalg/Utils/Utils.cpp
index f44bb6769e616..81bfbc6ecf525 100644
--- a/mlir/lib/Dialect/Linalg/Utils/Utils.cpp
+++ b/mlir/lib/Dialect/Linalg/Utils/Utils.cpp
@@ -104,12 +104,6 @@ SmallVector<int64_t, 8> getStaticShape(LinalgOp linalgOp) {
     auto shape = v.getType().cast<ShapedType>().getShape();
     res.append(shape.begin(), shape.end());
   }
-  if (linalgOp.getNumInitTensors())
-    return res;
-  for (Value v : linalgOp.getOperation()->getResults()) {
-    auto shape = v.getType().cast<ShapedType>().getShape();
-    res.append(shape.begin(), shape.end());
-  }
   return res;
 }
 
diff --git a/mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt b/mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
index dbf62425878b6..42c0047168b91 100644
--- a/mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
+++ b/mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt
@@ -5,6 +5,7 @@ add_public_tablegen_target(MLIRSPIRVCanonicalizationIncGen)
 add_mlir_dialect_library(MLIRSPIRV
   SPIRVAttributes.cpp
   SPIRVCanonicalization.cpp
+  SPIRVGLSLCanonicalization.cpp
   SPIRVDialect.cpp
   SPIRVEnums.cpp
   SPIRVOps.cpp
diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td b/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td
index 125e973608654..6e0ee4488fa14 100644
--- a/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td
+++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td
@@ -38,3 +38,33 @@ def ConvertLogicalNotOfLogicalEqual : Pat<
 def ConvertLogicalNotOfLogicalNotEqual : Pat<
     (SPV_LogicalNotOp (SPV_LogicalNotEqualOp $lhs, $rhs)),
     (SPV_LogicalEqualOp $lhs, $rhs)>;
+
+//===----------------------------------------------------------------------===//
+// Re-write spv.Select + spv.<less_than_op> to a suitable variant of
+// spv.<glsl_clamp_op>
+//===----------------------------------------------------------------------===//
+
+def ValuesAreEqual : Constraint<CPred<"$0 == $1">>;
+
+foreach CmpClampPair = [
+    [SPV_FOrdLessThanOp, SPV_GLSLFClampOp],
+    [SPV_FOrdLessThanEqualOp, SPV_GLSLFClampOp],
+    [SPV_SLessThanOp, SPV_GLSLSClampOp],
+    [SPV_SLessThanEqualOp, SPV_GLSLSClampOp],
+    [SPV_ULessThanOp, SPV_GLSLUClampOp],
+    [SPV_ULessThanEqualOp, SPV_GLSLUClampOp]] in {
+def ConvertComparisonIntoClamp#CmpClampPair[0] : Pat<
+    (SPV_SelectOp
+        (CmpClampPair[0]
+            (SPV_SelectOp:$middle0
+                (CmpClampPair[0] $min, $input),
+                $input,
+                $min
+            ),
+            $max
+        ),
+        $middle1,
+        $max),
+    (CmpClampPair[1] $input, $min, $max),
+    [(ValuesAreEqual $middle0, $middle1)]>;
+}
diff --git a/mlir/lib/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp b/mlir/lib/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp
new file mode 100644
index 0000000000000..0aa413941efd2
--- /dev/null
+++ b/mlir/lib/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp
@@ -0,0 +1,35 @@
+//===- SPIRVGLSLCanonicalization.cpp - SPIR-V GLSL canonicalization patterns =//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the canonicalization patterns for SPIR-V GLSL-specific ops.
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h"
+
+#include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
+
+using namespace mlir;
+
+namespace {
+#include "SPIRVCanonicalization.inc"
+} // end anonymous namespace
+
+namespace mlir {
+namespace spirv {
+void populateSPIRVGLSLCanonicalizationPatterns(
+    OwningRewritePatternList &results, MLIRContext *context) {
+  results.insert<ConvertComparisonIntoClampSPV_FOrdLessThanOp,
+                 ConvertComparisonIntoClampSPV_FOrdLessThanEqualOp,
+                 ConvertComparisonIntoClampSPV_SLessThanOp,
+                 ConvertComparisonIntoClampSPV_SLessThanEqualOp,
+                 ConvertComparisonIntoClampSPV_ULessThanOp,
+                 ConvertComparisonIntoClampSPV_ULessThanEqualOp>(context);
+}
+} // namespace spirv
+} // namespace mlir
diff --git a/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp b/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
index b310d5df7b269..9393f3df64250 100644
--- a/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
+++ b/mlir/lib/Dialect/SPIRV/Transforms/SPIRVConversion.cpp
@@ -473,23 +473,27 @@ LogicalResult
 FuncOpConversion::matchAndRewrite(FuncOp funcOp, ArrayRef<Value> operands,
                                   ConversionPatternRewriter &rewriter) const {
   auto fnType = funcOp.getType();
-  // TODO: support converting functions with one result.
-  if (fnType.getNumResults())
+  if (fnType.getNumResults() > 1)
     return failure();
 
   TypeConverter::SignatureConversion signatureConverter(fnType.getNumInputs());
-  for (auto argType : enumerate(funcOp.getType().getInputs())) {
+  for (auto argType : enumerate(fnType.getInputs())) {
     auto convertedType = typeConverter.convertType(argType.value());
     if (!convertedType)
       return failure();
     signatureConverter.addInputs(argType.index(), convertedType);
   }
 
+  Type resultType;
+  if (fnType.getNumResults() == 1)
+    resultType = typeConverter.convertType(fnType.getResult(0));
+
   // Create the converted spv.func op.
   auto newFuncOp = rewriter.create<spirv::FuncOp>(
       funcOp.getLoc(), funcOp.getName(),
       rewriter.getFunctionType(signatureConverter.getConvertedTypes(),
-                               llvm::None));
+                               resultType ? TypeRange(resultType)
+                                          : TypeRange()));
 
   // Copy over all attributes other than the function name and type.
   for (const auto &namedAttr : funcOp.getAttrs()) {
diff --git a/mlir/lib/Dialect/StandardOps/IR/Ops.cpp b/mlir/lib/Dialect/StandardOps/IR/Ops.cpp
index c0af06314086c..30bf546807c43 100644
--- a/mlir/lib/Dialect/StandardOps/IR/Ops.cpp
+++ b/mlir/lib/Dialect/StandardOps/IR/Ops.cpp
@@ -1477,12 +1477,12 @@ struct DimOfCastOp : public OpRewritePattern<DimOp> {
     return success();
   }
 };
-
 } // end anonymous namespace.
 
 void DimOp::getCanonicalizationPatterns(OwningRewritePatternList &results,
                                         MLIRContext *context) {
-  results.insert<DimOfMemRefReshape, DimOfCastOp<tensor::CastOp>>(context);
+  results.insert<DimOfMemRefReshape, DimOfCastOp<TensorToMemrefOp>,
+                 DimOfCastOp<tensor::CastOp>>(context);
 }
 
 // ---------------------------------------------------------------------------
diff --git a/mlir/lib/Dialect/Vector/VectorOps.cpp b/mlir/lib/Dialect/Vector/VectorOps.cpp
index 5c1f377e589e3..a6a353c979775 100644
--- a/mlir/lib/Dialect/Vector/VectorOps.cpp
+++ b/mlir/lib/Dialect/Vector/VectorOps.cpp
@@ -67,7 +67,7 @@ static MaskFormat get1DMaskFormat(Value mask) {
     ArrayAttr masks = m.mask_dim_sizes();
     assert(masks.size() == 1);
     int64_t i = masks[0].cast<IntegerAttr>().getInt();
-    int64_t u = m.getType().cast<VectorType>().getDimSize(0);
+    int64_t u = m.getType().getDimSize(0);
     if (i >= u)
       return MaskFormat::AllTrue;
     if (i <= 0)
@@ -849,7 +849,7 @@ static Value foldExtractFromShapeCast(ExtractOp extractOp) {
     return Value();
   // Get the nth dimension size starting from lowest dimension.
   auto getDimReverse = [](VectorType type, int64_t n) {
-    return type.getShape().take_back(n+1).front();
+    return type.getShape().take_back(n + 1).front();
   };
   int64_t destinationRank =
       extractOp.getType().isa<VectorType>()
@@ -1110,6 +1110,36 @@ OpFoldResult BroadcastOp::fold(ArrayRef<Attribute> operands) {
   return {};
 }
 
+namespace {
+
+// BroadcastOp can only add dimensions or broadcast a dimension from 1 to N. In
+// the degenerated case where the broadcast only adds dimensions of size 1 it
+// can be replaced by a ShapeCastOp. This canonicalization checks if the total
+// number of elements is the same before and after the broadcast to detect if
+// the only change in the vector type are new dimensions of size 1.
+class BroadcastToShapeCast final : public OpRewritePattern<BroadcastOp> {
+public:
+  using OpRewritePattern<BroadcastOp>::OpRewritePattern;
+
+  LogicalResult matchAndRewrite(BroadcastOp broadcastOp,
+                                PatternRewriter &rewriter) const override {
+    auto srcVecType = broadcastOp.getSourceType().dyn_cast<VectorType>();
+    if (!srcVecType || broadcastOp.getVectorType().getNumElements() !=
+                           srcVecType.getNumElements())
+      return failure();
+    rewriter.replaceOpWithNewOp<ShapeCastOp>(
+        broadcastOp, broadcastOp.getVectorType(), broadcastOp.source());
+    return success();
+  }
+};
+
+} // namespace
+
+void BroadcastOp::getCanonicalizationPatterns(
+    OwningRewritePatternList &results, MLIRContext *context) {
+  results.insert<BroadcastToShapeCast>(context);
+}
+
 //===----------------------------------------------------------------------===//
 // ShuffleOp
 //===----------------------------------------------------------------------===//
@@ -1768,7 +1798,8 @@ void ExtractStridedSliceOp::getOffsets(SmallVectorImpl<int64_t> &results) {
 
 namespace {
 
-// Pattern to rewrite a ExtractStridedSliceOp(ConstantMaskOp) -> ConstantMaskOp.
+// Pattern to rewrite an ExtractStridedSliceOp(ConstantMaskOp) to
+// ConstantMaskOp.
 class StridedSliceConstantMaskFolder final
     : public OpRewritePattern<ExtractStridedSliceOp> {
 public:
@@ -1839,22 +1870,77 @@ class StridedSliceConstantFolder final
     auto dense = constantOp.value().dyn_cast<SplatElementsAttr>();
     if (!dense)
       return failure();
-    auto newAttr = DenseElementsAttr::get(
-        extractStridedSliceOp.getType().cast<VectorType>(),
-        dense.getSplatValue());
+    auto newAttr = DenseElementsAttr::get(extractStridedSliceOp.getType(),
+                                          dense.getSplatValue());
     rewriter.replaceOpWithNewOp<ConstantOp>(extractStridedSliceOp, newAttr);
     return success();
   }
 };
 
+// Helper that returns a subset of `arrayAttr` as a vector of int64_t.
+static SmallVector<int64_t, 4> getI64SubArray(ArrayAttr arrayAttr,
+                                              unsigned dropFront = 0,
+                                              unsigned dropBack = 0) {
+  assert(arrayAttr.size() > dropFront + dropBack && "Out of bounds");
+  auto range = arrayAttr.getAsRange<IntegerAttr>();
+  SmallVector<int64_t, 4> res;
+  res.reserve(arrayAttr.size() - dropFront - dropBack);
+  for (auto it = range.begin() + dropFront, eit = range.end() - dropBack;
+       it != eit; ++it)
+    res.push_back((*it).getValue().getSExtValue());
+  return res;
+}
+
+// Pattern to rewrite an ExtractStridedSliceOp(BroadcastOp) to
+// BroadcastOp(ExtractStrideSliceOp).
+class StridedSliceBroadcast final
+    : public OpRewritePattern<ExtractStridedSliceOp> {
+public:
+  using OpRewritePattern<ExtractStridedSliceOp>::OpRewritePattern;
+
+  LogicalResult matchAndRewrite(ExtractStridedSliceOp op,
+                                PatternRewriter &rewriter) const override {
+    auto broadcast = op.vector().getDefiningOp<BroadcastOp>();
+    if (!broadcast)
+      return failure();
+    auto srcVecType = broadcast.source().getType().dyn_cast<VectorType>();
+    unsigned srcRrank = srcVecType ? srcVecType.getRank() : 0;
+    auto dstVecType = op.getType().cast<VectorType>();
+    unsigned dstRank = dstVecType.getRank();
+    unsigned rankDiff = dstRank - srcRrank;
+    // Check if the most inner dimensions of the source of the broacast are the
+    // same as the destination of the extract. If this is the case we can just
+    // use a broadcast as the original dimensions are untouched.
+    bool lowerDimMatch = true;
+    for (unsigned i = 0; i < srcRrank; i++) {
+      if (srcVecType.getDimSize(i) != dstVecType.getDimSize(i + rankDiff)) {
+        lowerDimMatch = false;
+        break;
+      }
+    }
+    Value source = broadcast.source();
+    if (!lowerDimMatch) {
+      // The inner dimensions don't match, it means we need to extract from the
+      // source of the orignal broadcast and then broadcast the extracted value.
+      source = rewriter.create<ExtractStridedSliceOp>(
+          op->getLoc(), source,
+          getI64SubArray(op.offsets(), /* dropFront=*/rankDiff),
+          getI64SubArray(op.sizes(), /* dropFront=*/rankDiff),
+          getI64SubArray(op.strides(), /* dropFront=*/rankDiff));
+    }
+    rewriter.replaceOpWithNewOp<BroadcastOp>(op, op.getType(), source);
+    return success();
+  }
+};
+
 } // end anonymous namespace
 
 void ExtractStridedSliceOp::getCanonicalizationPatterns(
     OwningRewritePatternList &results, MLIRContext *context) {
   // Pattern to rewrite a ExtractStridedSliceOp(ConstantMaskOp) ->
   // ConstantMaskOp and ExtractStridedSliceOp(ConstantOp) -> ConstantOp.
-  results.insert<StridedSliceConstantMaskFolder, StridedSliceConstantFolder>(
-      context);
+  results.insert<StridedSliceConstantMaskFolder, StridedSliceConstantFolder,
+                 StridedSliceBroadcast>(context);
 }
 
 //===----------------------------------------------------------------------===//
@@ -1890,41 +1976,43 @@ static LogicalResult verifyPermutationMap(AffineMap permutationMap,
   return success();
 }
 
-static LogicalResult verifyTransferOp(Operation *op, MemRefType memrefType,
+static LogicalResult verifyTransferOp(Operation *op, ShapedType shapedType,
                                       VectorType vectorType,
                                       AffineMap permutationMap,
                                       ArrayAttr optionalMasked) {
-  auto memrefElementType = memrefType.getElementType();
-  if (auto memrefVectorElementType = memrefElementType.dyn_cast<VectorType>()) {
-    // Memref has vector element type.
-
-    unsigned memrefVecSize = memrefVectorElementType.getElementTypeBitWidth() *
-                             memrefVectorElementType.getShape().back();
+  if (!shapedType.isa<MemRefType, RankedTensorType>())
+    return op->emitOpError(
+        "requires source to be a memref or ranked tensor type");
+  auto elementType = shapedType.getElementType();
+  if (auto vectorElementType = elementType.dyn_cast<VectorType>()) {
+    // Memref or tensor has vector element type.
+    unsigned sourceVecSize = vectorElementType.getElementTypeBitWidth() *
+                             vectorElementType.getShape().back();
     unsigned resultVecSize =
         vectorType.getElementTypeBitWidth() * vectorType.getShape().back();
-    if (resultVecSize % memrefVecSize != 0)
+    if (resultVecSize % sourceVecSize != 0)
       return op->emitOpError(
           "requires the bitwidth of the minor 1-D vector to be an integral "
-          "multiple of the bitwidth of the minor 1-D vector of the memref");
+          "multiple of the bitwidth of the minor 1-D vector of the source");
 
-    unsigned memrefVecEltRank = memrefVectorElementType.getRank();
+    unsigned sourceVecEltRank = vectorElementType.getRank();
     unsigned resultVecRank = vectorType.getRank();
-    if (memrefVecEltRank > resultVecRank)
+    if (sourceVecEltRank > resultVecRank)
       return op->emitOpError(
-          "requires memref vector element and vector result ranks to match.");
-    unsigned rankOffset = resultVecRank - memrefVecEltRank;
+          "requires source vector element and vector result ranks to match.");
+    unsigned rankOffset = resultVecRank - sourceVecEltRank;
     // Check that permutation map results match 'rankOffset' of vector type.
     if (permutationMap.getNumResults() != rankOffset)
       return op->emitOpError("requires a permutation_map with result dims of "
                              "the same rank as the vector type");
   } else {
-    // Memref has scalar element type.
+    // Memref or tensor has scalar element type.
     unsigned resultVecSize =
         vectorType.getElementTypeBitWidth() * vectorType.getShape().back();
-    if (resultVecSize % memrefElementType.getIntOrFloatBitWidth() != 0)
+    if (resultVecSize % elementType.getIntOrFloatBitWidth() != 0)
       return op->emitOpError(
           "requires the bitwidth of the minor 1-D vector to be an integral "
-          "multiple of the bitwidth of the memref element type");
+          "multiple of the bitwidth of the source element type");
 
     // Check that permutation map results match rank of vector type.
     if (permutationMap.getNumResults() != vectorType.getRank())
@@ -1934,9 +2022,9 @@ static LogicalResult verifyTransferOp(Operation *op, MemRefType memrefType,
 
   if (permutationMap.getNumSymbols() != 0)
     return op->emitOpError("requires permutation_map without symbols");
-  if (permutationMap.getNumInputs() != memrefType.getRank())
+  if (permutationMap.getNumInputs() != shapedType.getRank())
     return op->emitOpError("requires a permutation_map with input dims of the "
-                           "same rank as the memref type");
+                           "same rank as the source type");
 
   if (optionalMasked) {
     if (permutationMap.getNumResults() !=
@@ -1978,7 +2066,7 @@ void TransferReadOp::build(OpBuilder &builder, OperationState &result,
 static void printTransferAttrs(OpAsmPrinter &p, VectorTransferOpInterface op) {
   SmallVector<StringRef, 2> elidedAttrs;
   if (op.permutation_map() ==
-      getTransferMinorIdentityMap(op.getMemRefType(), op.getVectorType()))
+      getTransferMinorIdentityMap(op.getShapedType(), op.getVectorType()))
     elidedAttrs.push_back(op.getPermutationMapAttrName());
   bool elideMasked = true;
   if (auto maybeMasked = op.masked()) {
@@ -1995,21 +2083,21 @@ static void printTransferAttrs(OpAsmPrinter &p, VectorTransferOpInterface op) {
 }
 
 static void print(OpAsmPrinter &p, TransferReadOp op) {
-  p << op.getOperationName() << " " << op.memref() << "[" << op.indices()
+  p << op.getOperationName() << " " << op.source() << "[" << op.indices()
     << "], " << op.padding();
   printTransferAttrs(p, cast<VectorTransferOpInterface>(op.getOperation()));
-  p << " : " << op.getMemRefType() << ", " << op.getVectorType();
+  p << " : " << op.getShapedType() << ", " << op.getVectorType();
 }
 
 static ParseResult parseTransferReadOp(OpAsmParser &parser,
                                        OperationState &result) {
   llvm::SMLoc typesLoc;
-  OpAsmParser::OperandType memrefInfo;
+  OpAsmParser::OperandType sourceInfo;
   SmallVector<OpAsmParser::OperandType, 8> indexInfo;
   OpAsmParser::OperandType paddingInfo;
   SmallVector<Type, 2> types;
   // Parsing with support for paddingValue.
-  if (parser.parseOperand(memrefInfo) ||
+  if (parser.parseOperand(sourceInfo) ||
       parser.parseOperandList(indexInfo, OpAsmParser::Delimiter::Square) ||
       parser.parseComma() || parser.parseOperand(paddingInfo) ||
       parser.parseOptionalAttrDict(result.attributes) ||
@@ -2018,48 +2106,48 @@ static ParseResult parseTransferReadOp(OpAsmParser &parser,
   if (types.size() != 2)
     return parser.emitError(typesLoc, "requires two types");
   auto indexType = parser.getBuilder().getIndexType();
-  MemRefType memRefType = types[0].dyn_cast<MemRefType>();
-  if (!memRefType)
-    return parser.emitError(typesLoc, "requires memref type");
+  auto shapedType = types[0].dyn_cast<ShapedType>();
+  if (!shapedType || !shapedType.isa<MemRefType, RankedTensorType>())
+    return parser.emitError(typesLoc, "requires memref or ranked tensor type");
   VectorType vectorType = types[1].dyn_cast<VectorType>();
   if (!vectorType)
     return parser.emitError(typesLoc, "requires vector type");
   auto permutationAttrName = TransferReadOp::getPermutationMapAttrName();
   auto attr = result.attributes.get(permutationAttrName);
   if (!attr) {
-    auto permMap = getTransferMinorIdentityMap(memRefType, vectorType);
+    auto permMap = getTransferMinorIdentityMap(shapedType, vectorType);
     result.attributes.set(permutationAttrName, AffineMapAttr::get(permMap));
   }
   return failure(
-      parser.resolveOperand(memrefInfo, memRefType, result.operands) ||
+      parser.resolveOperand(sourceInfo, shapedType, result.operands) ||
       parser.resolveOperands(indexInfo, indexType, result.operands) ||
-      parser.resolveOperand(paddingInfo, memRefType.getElementType(),
+      parser.resolveOperand(paddingInfo, shapedType.getElementType(),
                             result.operands) ||
       parser.addTypeToList(vectorType, result.types));
 }
 
 static LogicalResult verify(TransferReadOp op) {
-  // Consistency of elemental types in memref and vector.
-  MemRefType memrefType = op.getMemRefType();
+  // Consistency of elemental types in source and vector.
+  ShapedType shapedType = op.getShapedType();
   VectorType vectorType = op.getVectorType();
   auto paddingType = op.padding().getType();
   auto permutationMap = op.permutation_map();
-  auto memrefElementType = memrefType.getElementType();
+  auto sourceElementType = shapedType.getElementType();
 
-  if (static_cast<int64_t>(op.indices().size()) != memrefType.getRank())
-    return op.emitOpError("requires ") << memrefType.getRank() << " indices";
+  if (static_cast<int64_t>(op.indices().size()) != shapedType.getRank())
+    return op.emitOpError("requires ") << shapedType.getRank() << " indices";
 
-  if (failed(verifyTransferOp(op.getOperation(), memrefType, vectorType,
+  if (failed(verifyTransferOp(op.getOperation(), shapedType, vectorType,
                               permutationMap,
                               op.masked() ? *op.masked() : ArrayAttr())))
     return failure();
 
-  if (auto memrefVectorElementType = memrefElementType.dyn_cast<VectorType>()) {
-    // Memref has vector element type.
-    // Check that 'memrefVectorElementType' and 'paddingType' types match.
-    if (memrefVectorElementType != paddingType)
+  if (auto sourceVectorElementType = sourceElementType.dyn_cast<VectorType>()) {
+    // Source has vector element type.
+    // Check that 'sourceVectorElementType' and 'paddingType' types match.
+    if (sourceVectorElementType != paddingType)
       return op.emitOpError(
-          "requires memref element type and padding type to match.");
+          "requires source element type and padding type to match.");
 
   } else {
     // Check that 'paddingType' is valid to store in a vector type.
@@ -2067,9 +2155,9 @@ static LogicalResult verify(TransferReadOp op) {
       return op.emitOpError("requires valid padding vector elemental type");
 
     // Check that padding type and vector element types match.
-    if (paddingType != memrefElementType)
+    if (paddingType != sourceElementType)
       return op.emitOpError(
-          "requires formal padding and memref of the same elemental type");
+          "requires formal padding and source of the same elemental type");
   }
 
   return verifyPermutationMap(permutationMap,
@@ -2096,18 +2184,18 @@ static LogicalResult foldMemRefCast(Operation *op) {
 template <typename TransferOp>
 static bool isInBounds(TransferOp op, int64_t resultIdx, int64_t indicesIdx) {
   // TODO: support more aggressive createOrFold on:
-  // `op.indices()[indicesIdx] + vectorType < dim(op.memref(), indicesIdx)`
-  if (op.getMemRefType().isDynamicDim(indicesIdx))
+  // `op.indices()[indicesIdx] + vectorType < dim(op.source(), indicesIdx)`
+  if (op.getShapedType().isDynamicDim(indicesIdx))
     return false;
   Value index = op.indices()[indicesIdx];
   auto cstOp = index.getDefiningOp<ConstantIndexOp>();
   if (!cstOp)
     return false;
 
-  int64_t memrefSize = op.getMemRefType().getDimSize(indicesIdx);
+  int64_t sourceSize = op.getShapedType().getDimSize(indicesIdx);
   int64_t vectorSize = op.getVectorType().getDimSize(resultIdx);
 
-  return cstOp.getValue() + vectorSize <= memrefSize;
+  return cstOp.getValue() + vectorSize <= sourceSize;
 }
 
 template <typename TransferOp>
@@ -2159,33 +2247,51 @@ Optional<SmallVector<int64_t, 4>> TransferReadOp::getShapeForUnroll() {
 
 /// Builder that sets permutation map to 'getMinorIdentityMap'.
 void TransferWriteOp::build(OpBuilder &builder, OperationState &result,
-                            Value vector, Value memref, ValueRange indices,
+                            Value vector, Value source, ValueRange indices,
                             ArrayRef<bool> maybeMasked) {
   auto vectorType = vector.getType().cast<VectorType>();
   auto permMap = getTransferMinorIdentityMap(
-      memref.getType().cast<MemRefType>(), vectorType);
+      source.getType().cast<MemRefType>(), vectorType);
   if (maybeMasked.empty())
-    return build(builder, result, vector, memref, indices, permMap,
+    return build(builder, result, vector, source, indices, permMap,
                  ArrayAttr());
   ArrayAttr maskedArrayAttr = builder.getBoolArrayAttr(maybeMasked);
-  build(builder, result, vector, memref, indices, permMap, maskedArrayAttr);
+  build(builder, result, vector, source, indices, permMap, maskedArrayAttr);
 }
 
 void TransferWriteOp::build(OpBuilder &builder, OperationState &result,
-                            Value vector, Value memref, ValueRange indices,
+                            Value vector, Value source, ValueRange indices,
                             AffineMap permutationMap) {
-  build(builder, result, vector, memref, indices, permutationMap,
+  build(builder, result, vector, source, indices, permutationMap,
         /*maybeMasked=*/ArrayAttr());
 }
 
+void TransferWriteOp::build(OpBuilder &builder, OperationState &result,
+                            Value vector, Value source, ValueRange indices,
+                            AffineMapAttr permutationMap,
+                            /*optional*/ ArrayAttr masked) {
+  Type resultType = source.getType().dyn_cast<RankedTensorType>();
+  build(builder, result, resultType, vector, source, indices, permutationMap,
+        masked);
+}
+
+void TransferWriteOp::build(OpBuilder &builder, OperationState &result,
+                            Value vector, Value source, ValueRange indices,
+                            AffineMap permutationMap,
+                            /*optional*/ ArrayAttr masked) {
+  Type resultType = source.getType().dyn_cast<RankedTensorType>();
+  build(builder, result, resultType, vector, source, indices, permutationMap,
+        masked);
+}
+
 static ParseResult parseTransferWriteOp(OpAsmParser &parser,
                                         OperationState &result) {
   llvm::SMLoc typesLoc;
-  OpAsmParser::OperandType vectorInfo, memrefInfo;
+  OpAsmParser::OperandType vectorInfo, sourceInfo;
   SmallVector<OpAsmParser::OperandType, 8> indexInfo;
   SmallVector<Type, 2> types;
   if (parser.parseOperand(vectorInfo) || parser.parseComma() ||
-      parser.parseOperand(memrefInfo) ||
+      parser.parseOperand(sourceInfo) ||
       parser.parseOperandList(indexInfo, OpAsmParser::Delimiter::Square) ||
       parser.parseOptionalAttrDict(result.attributes) ||
       parser.getCurrentLocation(&typesLoc) || parser.parseColonTypeList(types))
@@ -2196,38 +2302,40 @@ static ParseResult parseTransferWriteOp(OpAsmParser &parser,
   VectorType vectorType = types[0].dyn_cast<VectorType>();
   if (!vectorType)
     return parser.emitError(typesLoc, "requires vector type");
-  MemRefType memRefType = types[1].dyn_cast<MemRefType>();
-  if (!memRefType)
-    return parser.emitError(typesLoc, "requires memref type");
+  ShapedType shapedType = types[1].dyn_cast<ShapedType>();
+  if (!shapedType || !shapedType.isa<MemRefType, RankedTensorType>())
+    return parser.emitError(typesLoc, "requires memref or ranked tensor type");
   auto permutationAttrName = TransferWriteOp::getPermutationMapAttrName();
   auto attr = result.attributes.get(permutationAttrName);
   if (!attr) {
-    auto permMap = getTransferMinorIdentityMap(memRefType, vectorType);
+    auto permMap = getTransferMinorIdentityMap(shapedType, vectorType);
     result.attributes.set(permutationAttrName, AffineMapAttr::get(permMap));
   }
   return failure(
       parser.resolveOperand(vectorInfo, vectorType, result.operands) ||
-      parser.resolveOperand(memrefInfo, memRefType, result.operands) ||
-      parser.resolveOperands(indexInfo, indexType, result.operands));
+      parser.resolveOperand(sourceInfo, shapedType, result.operands) ||
+      parser.resolveOperands(indexInfo, indexType, result.operands) ||
+      (shapedType.isa<RankedTensorType>() &&
+       parser.addTypeToList(shapedType, result.types)));
 }
 
 static void print(OpAsmPrinter &p, TransferWriteOp op) {
-  p << op.getOperationName() << " " << op.vector() << ", " << op.memref() << "["
+  p << op.getOperationName() << " " << op.vector() << ", " << op.source() << "["
     << op.indices() << "]";
   printTransferAttrs(p, cast<VectorTransferOpInterface>(op.getOperation()));
-  p << " : " << op.getVectorType() << ", " << op.getMemRefType();
+  p << " : " << op.getVectorType() << ", " << op.getShapedType();
 }
 
 static LogicalResult verify(TransferWriteOp op) {
   // Consistency of elemental types in memref and vector.
-  MemRefType memrefType = op.getMemRefType();
+  ShapedType shapedType = op.getShapedType();
   VectorType vectorType = op.getVectorType();
   auto permutationMap = op.permutation_map();
 
-  if (llvm::size(op.indices()) != memrefType.getRank())
-    return op.emitOpError("requires ") << memrefType.getRank() << " indices";
+  if (llvm::size(op.indices()) != shapedType.getRank())
+    return op.emitOpError("requires ") << shapedType.getRank() << " indices";
 
-  if (failed(verifyTransferOp(op.getOperation(), memrefType, vectorType,
+  if (failed(verifyTransferOp(op.getOperation(), shapedType, vectorType,
                               permutationMap,
                               op.masked() ? *op.masked() : ArrayAttr())))
     return failure();
@@ -2630,10 +2738,12 @@ OpFoldResult ShapeCastOp::fold(ArrayRef<Attribute> operands) {
     return source();
 
   // Canceling shape casts.
-  if (auto otherOp = source().getDefiningOp<ShapeCastOp>())
+  if (auto otherOp = source().getDefiningOp<ShapeCastOp>()) {
     if (result().getType() == otherOp.source().getType())
       return otherOp.source();
-
+    setOperand(otherOp.source());
+    return getResult();
+  }
   return {};
 }
 
diff --git a/mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp b/mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp
index b7de983dd3b1c..ea1189d53b311 100644
--- a/mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp
+++ b/mlir/lib/Dialect/Vector/VectorTransferOpTransforms.cpp
@@ -94,7 +94,7 @@ void TransferOptimization::deadStoreOp(vector::TransferWriteOp write) {
                     << "\n");
   llvm::SmallVector<Operation *, 8> reads;
   Operation *firstOverwriteCandidate = nullptr;
-  for (auto *user : write.memref().getUsers()) {
+  for (auto *user : write.source().getUsers()) {
     if (user == write.getOperation())
       continue;
     if (auto nextWrite = dyn_cast<vector::TransferWriteOp>(user)) {
@@ -163,7 +163,7 @@ void TransferOptimization::storeToLoadForwarding(vector::TransferReadOp read) {
                     << "\n");
   SmallVector<Operation *, 8> blockingWrites;
   vector::TransferWriteOp lastwrite = nullptr;
-  for (Operation *user : read.memref().getUsers()) {
+  for (Operation *user : read.source().getUsers()) {
     if (isa<vector::TransferReadOp>(user))
       continue;
     if (auto write = dyn_cast<vector::TransferWriteOp>(user)) {
diff --git a/mlir/lib/Dialect/Vector/VectorTransforms.cpp b/mlir/lib/Dialect/Vector/VectorTransforms.cpp
index 664426960beb3..f1708db113d45 100644
--- a/mlir/lib/Dialect/Vector/VectorTransforms.cpp
+++ b/mlir/lib/Dialect/Vector/VectorTransforms.cpp
@@ -492,8 +492,9 @@ static void getVectorElementwiseOpUnrollState(Operation *op,
   assert(resultType && "Expected op with vector result type");
   auto resultShape = resultType.getShape();
   // Verify that all operands have the same vector type as result.
-  assert(llvm::all_of(op->getOperandTypes(),
-                      [=](Type type) { return type == resultType; }));
+  assert(llvm::all_of(op->getOperandTypes(), [=](Type type) {
+    return type.cast<VectorType>().getShape() == resultShape;
+  }));
 
   // Create trivial elementwise identity index map based on 'resultShape'.
   DenseMap<int64_t, int64_t> indexMap;
@@ -504,8 +505,9 @@ static void getVectorElementwiseOpUnrollState(Operation *op,
   // Create VectorState each operand and single result.
   unsigned numVectors = op->getNumOperands() + op->getNumResults();
   vectors.resize(numVectors);
-  for (unsigned i = 0; i < op->getNumOperands(); ++i)
-    vectors[i] = {resultType, indexMap, i, false};
+  for (auto it : llvm::enumerate(op->getOperandTypes()))
+    vectors[it.index()] = {it.value().cast<VectorType>(), indexMap,
+                           static_cast<int64_t>(it.index()), false};
   vectors[numVectors - 1] = {resultType, indexMap, -1, false};
   resultIndex = numVectors - 1;
 }
@@ -597,7 +599,7 @@ static Value unrollTransferReadOp(vector::TransferReadOp readOp,
 
   Location loc = readOp.getLoc();
   auto memrefElementType =
-      readOp.memref().getType().cast<MemRefType>().getElementType();
+      readOp.source().getType().cast<MemRefType>().getElementType();
   auto tupleType = generateExtractSlicesOpResultType(
       sourceVectorType, targetShape, strides, builder);
   int64_t numSlices = tupleType.size();
@@ -612,7 +614,7 @@ static Value unrollTransferReadOp(vector::TransferReadOp readOp,
     // `masked` attribute propagates conservatively: if the coarse op didn't
     // need masking, the fine op doesn't either.
     vectorTupleValues[index] = builder.create<vector::TransferReadOp>(
-        loc, sliceVectorType, readOp.memref(), sliceIndices,
+        loc, sliceVectorType, readOp.source(), sliceIndices,
         readOp.permutation_map(), readOp.padding(),
         readOp.masked() ? *readOp.masked() : ArrayAttr());
   };
@@ -644,14 +646,14 @@ mlir::vector::unrollTransferWriteOp(OpBuilder &builder, Operation *op,
   Value tuple = builder.create<vector::ExtractSlicesOp>(
       loc, tupleType, writeOp.vector(), targetShape, strides);
   auto memrefElementType =
-      writeOp.memref().getType().cast<MemRefType>().getElementType();
+      writeOp.source().getType().cast<MemRefType>().getElementType();
   SmallVector<Value, 4> indices(writeOp.indices().begin(),
                                 writeOp.indices().end());
   auto createSlice = [&](unsigned index, ArrayRef<Value> sliceIndices) {
     auto element = builder.create<vector::TupleGetOp>(
         loc, tupleType.getType(index), tuple, builder.getI64IntegerAttr(index));
     builder.create<vector::TransferWriteOp>(
-        loc, element.getResult(), writeOp.memref(), sliceIndices,
+        loc, element.getResult(), writeOp.source(), sliceIndices,
         writeOp.permutation_map(),
         writeOp.masked() ? *writeOp.masked() : ArrayAttr());
   };
@@ -760,7 +762,7 @@ struct SplitTransferWriteOp : public OpRewritePattern<vector::TransferWriteOp> {
 
     Location loc = xferWriteOp.getLoc();
     auto memrefElementType =
-        xferWriteOp.memref().getType().cast<MemRefType>().getElementType();
+        xferWriteOp.source().getType().cast<MemRefType>().getElementType();
     SmallVector<Value, 4> indices(xferWriteOp.indices().begin(),
                                   xferWriteOp.indices().end());
     auto createSlice = [&](unsigned index, ArrayRef<Value> sliceIndices) {
@@ -768,7 +770,7 @@ struct SplitTransferWriteOp : public OpRewritePattern<vector::TransferWriteOp> {
       // `masked` attribute propagates conservatively: if the coarse op didn't
       // need masking, the fine op doesn't either.
       rewriter.create<vector::TransferWriteOp>(
-          loc, tupleOp.getOperand(index), xferWriteOp.memref(), sliceIndices,
+          loc, tupleOp.getOperand(index), xferWriteOp.source(), sliceIndices,
           xferWriteOp.permutation_map(),
           xferWriteOp.masked() ? *xferWriteOp.masked() : ArrayAttr());
     };
@@ -997,8 +999,7 @@ struct ShapeCastOpFolder : public OpRewritePattern<vector::ShapeCastOp> {
       return failure();
     auto operandSourceVectorType =
         sourceShapeCastOp.source().getType().cast<VectorType>();
-    auto operandResultVectorType =
-        sourceShapeCastOp.result().getType().cast<VectorType>();
+    auto operandResultVectorType = sourceShapeCastOp.getType();
 
     // Check if shape cast operations invert each other.
     if (operandSourceVectorType != resultVectorType ||
@@ -1395,7 +1396,7 @@ class ConstantMaskOpLowering : public OpRewritePattern<vector::ConstantMaskOp> {
   LogicalResult matchAndRewrite(vector::ConstantMaskOp op,
                                 PatternRewriter &rewriter) const override {
     auto loc = op.getLoc();
-    auto dstType = op.getResult().getType().cast<VectorType>();
+    auto dstType = op.getType();
     auto eltType = dstType.getElementType();
     auto dimSizes = op.mask_dim_sizes();
     int64_t rank = dimSizes.size();
@@ -2142,7 +2143,7 @@ static Value createScopedInBoundsCond(VectorTransferOpInterface xferOp) {
     // Fold or create the check that `index + vector_size` <= `memref_size`.
     Value sum = xferOp.indices()[indicesIdx] + std_constant_index(vectorSize);
     Value cond =
-        createScopedFoldedSLE(sum, std_dim(xferOp.memref(), indicesIdx));
+        createScopedFoldedSLE(sum, std_dim(xferOp.source(), indicesIdx));
     if (!cond)
       return;
     // Conjunction over all dims for which we are in-bounds.
@@ -2207,23 +2208,23 @@ static MemRefType getCastCompatibleMemRefType(MemRefType aT, MemRefType bT) {
 }
 
 /// Operates under a scoped context to build the intersection between the
-/// view `xferOp.memref()` @ `xferOp.indices()` and the view `alloc`.
+/// view `xferOp.source()` @ `xferOp.indices()` and the view `alloc`.
 // TODO: view intersection/union/differences should be a proper std op.
 static Value createScopedSubViewIntersection(VectorTransferOpInterface xferOp,
                                              Value alloc) {
   using namespace edsc::intrinsics;
-  int64_t memrefRank = xferOp.getMemRefType().getRank();
+  int64_t memrefRank = xferOp.getShapedType().getRank();
   // TODO: relax this precondition, will require rank-reducing subviews.
   assert(memrefRank == alloc.getType().cast<MemRefType>().getRank() &&
          "Expected memref rank to match the alloc rank");
   Value one = std_constant_index(1);
   ValueRange leadingIndices =
-      xferOp.indices().take_front(xferOp.getLeadingMemRefRank());
+      xferOp.indices().take_front(xferOp.getLeadingShapedRank());
   SmallVector<Value, 4> sizes;
   sizes.append(leadingIndices.begin(), leadingIndices.end());
   xferOp.zipResultAndIndexing([&](int64_t resultIdx, int64_t indicesIdx) {
     using MapList = ArrayRef<ArrayRef<AffineExpr>>;
-    Value dimMemRef = std_dim(xferOp.memref(), indicesIdx);
+    Value dimMemRef = std_dim(xferOp.source(), indicesIdx);
     Value dimAlloc = std_dim(alloc, resultIdx);
     Value index = xferOp.indices()[indicesIdx];
     AffineExpr i, j, k;
@@ -2235,7 +2236,7 @@ static Value createScopedSubViewIntersection(VectorTransferOpInterface xferOp,
                                  ValueRange{dimMemRef, index, dimAlloc});
     sizes.push_back(affineMin);
   });
-  return std_sub_view(xferOp.memref(), xferOp.indices(), sizes,
+  return std_sub_view(xferOp.source(), xferOp.indices(), sizes,
                       SmallVector<Value, 4>(memrefRank, one));
 }
 
@@ -2263,12 +2264,12 @@ static scf::IfOp createScopedFullPartialLinalgCopy(
   using namespace edsc::intrinsics;
   scf::IfOp fullPartialIfOp;
   Value zero = std_constant_index(0);
-  Value memref = xferOp.memref();
+  Value memref = xferOp.source();
   conditionBuilder(
       returnTypes, inBoundsCond,
       [&]() -> scf::ValueVector {
         Value res = memref;
-        if (compatibleMemRefType != xferOp.getMemRefType())
+        if (compatibleMemRefType != xferOp.getShapedType())
           res = std_memref_cast(memref, compatibleMemRefType);
         scf::ValueVector viewAndIndices{res};
         viewAndIndices.insert(viewAndIndices.end(), xferOp.indices().begin(),
@@ -2317,12 +2318,12 @@ static scf::IfOp createScopedFullPartialVectorTransferRead(
   using namespace edsc::intrinsics;
   scf::IfOp fullPartialIfOp;
   Value zero = std_constant_index(0);
-  Value memref = xferOp.memref();
+  Value memref = xferOp.source();
   conditionBuilder(
       returnTypes, inBoundsCond,
       [&]() -> scf::ValueVector {
         Value res = memref;
-        if (compatibleMemRefType != xferOp.getMemRefType())
+        if (compatibleMemRefType != xferOp.getShapedType())
           res = std_memref_cast(memref, compatibleMemRefType);
         scf::ValueVector viewAndIndices{res};
         viewAndIndices.insert(viewAndIndices.end(), xferOp.indices().begin(),
@@ -2376,7 +2377,7 @@ static scf::IfOp createScopedFullPartialVectorTransferRead(
 ///
 /// Preconditions:
 ///  1. `xferOp.permutation_map()` must be a minor identity map
-///  2. the rank of the `xferOp.memref()` and the rank of the `xferOp.vector()`
+///  2. the rank of the `xferOp.source()` and the rank of the `xferOp.vector()`
 ///  must be equal. This will be relaxed in the future but requires
 ///  rank-reducing subviews.
 LogicalResult mlir::vector::splitFullAndPartialTransfer(
@@ -2404,8 +2405,8 @@ LogicalResult mlir::vector::splitFullAndPartialTransfer(
     return failure();
 
   OpBuilder::InsertionGuard guard(b);
-  if (xferOp.memref().getDefiningOp())
-    b.setInsertionPointAfter(xferOp.memref().getDefiningOp());
+  if (Operation *sourceOp = xferOp.source().getDefiningOp())
+    b.setInsertionPointAfter(sourceOp);
   else
     b.setInsertionPoint(xferOp);
   ScopedContext scope(b, xferOp.getLoc());
@@ -2426,8 +2427,9 @@ LogicalResult mlir::vector::splitFullAndPartialTransfer(
                        b.getI64IntegerAttr(32));
   }
 
-  MemRefType compatibleMemRefType = getCastCompatibleMemRefType(
-      xferOp.getMemRefType(), alloc.getType().cast<MemRefType>());
+  MemRefType compatibleMemRefType =
+      getCastCompatibleMemRefType(xferOp.getShapedType().cast<MemRefType>(),
+                                  alloc.getType().cast<MemRefType>());
 
   // Read case: full fill + partial copy -> unmasked vector.xfer_read.
   SmallVector<Type, 4> returnTypes(1 + xferOp.getTransferRank(),
@@ -2543,7 +2545,7 @@ struct TransferReadExtractPattern
           extract.ids()[idCount++] *
               std_constant_index(extract.getResultType().getDimSize(pos));
     }
-    Value newRead = vector_transfer_read(extract.getType(), read.memref(),
+    Value newRead = vector_transfer_read(extract.getType(), read.source(),
                                          indices, read.permutation_map(),
                                          read.padding(), read.maskedAttr());
     Value dest = rewriter.create<ConstantOp>(
@@ -2579,7 +2581,7 @@ struct TransferWriteInsertPattern
           insert.ids()[idCount++] *
               std_constant_index(insert.getSourceVectorType().getDimSize(pos));
     }
-    vector_transfer_write(insert.vector(), write.memref(), indices,
+    vector_transfer_write(insert.vector(), write.source(), indices,
                           write.permutation_map(), write.maskedAttr());
     rewriter.eraseOp(write);
     return success();
diff --git a/mlir/lib/Dialect/Vector/VectorUtils.cpp b/mlir/lib/Dialect/Vector/VectorUtils.cpp
index 3ab1f500f5d19..fc08d21b27a5c 100644
--- a/mlir/lib/Dialect/Vector/VectorUtils.cpp
+++ b/mlir/lib/Dialect/Vector/VectorUtils.cpp
@@ -243,16 +243,16 @@ AffineMap mlir::makePermutationMap(
   return ::makePermutationMap(indices, enclosingLoopToVectorDim);
 }
 
-AffineMap mlir::getTransferMinorIdentityMap(MemRefType memRefType,
+AffineMap mlir::getTransferMinorIdentityMap(ShapedType shapedType,
                                             VectorType vectorType) {
   int64_t elementVectorRank = 0;
   VectorType elementVectorType =
-      memRefType.getElementType().dyn_cast<VectorType>();
+      shapedType.getElementType().dyn_cast<VectorType>();
   if (elementVectorType)
     elementVectorRank += elementVectorType.getRank();
   return AffineMap::getMinorIdentityMap(
-      memRefType.getRank(), vectorType.getRank() - elementVectorRank,
-      memRefType.getContext());
+      shapedType.getRank(), vectorType.getRank() - elementVectorRank,
+      shapedType.getContext());
 }
 
 bool matcher::operatesOnSuperVectorsOf(Operation &op,
@@ -314,12 +314,12 @@ bool matcher::operatesOnSuperVectorsOf(Operation &op,
 
 bool mlir::isDisjointTransferSet(VectorTransferOpInterface transferA,
                                  VectorTransferOpInterface transferB) {
-  if (transferA.memref() != transferB.memref())
+  if (transferA.source() != transferB.source())
     return false;
   // For simplicity only look at transfer of same type.
   if (transferA.getVectorType() != transferB.getVectorType())
     return false;
-  unsigned rankOffset = transferA.getLeadingMemRefRank();
+  unsigned rankOffset = transferA.getLeadingShapedRank();
   for (unsigned i = 0, e = transferA.indices().size(); i < e; i++) {
     auto indexA = transferA.indices()[i].getDefiningOp<ConstantOp>();
     auto indexB = transferB.indices()[i].getDefiningOp<ConstantOp>();
diff --git a/mlir/lib/ExecutionEngine/AsyncRuntime.cpp b/mlir/lib/ExecutionEngine/AsyncRuntime.cpp
index 3bfed86aa9960..45bdcb3733b88 100644
--- a/mlir/lib/ExecutionEngine/AsyncRuntime.cpp
+++ b/mlir/lib/ExecutionEngine/AsyncRuntime.cpp
@@ -114,6 +114,7 @@ static AsyncRuntime *getDefaultAsyncRuntimeInstance() {
   return runtime.get();
 }
 
+// Async token provides a mechanism to signal asynchronous operation completion.
 struct AsyncToken : public RefCounted {
   // AsyncToken created with a reference count of 2 because it will be returned
   // to the `async.execute` caller and also will be later on emplaced by the
@@ -130,6 +131,28 @@ struct AsyncToken : public RefCounted {
   std::vector<std::function<void()>> awaiters;
 };
 
+// Async value provides a mechanism to access the result of asynchronous
+// operations. It owns the storage that is used to store/load the value of the
+// underlying type, and a flag to signal if the value is ready or not.
+struct AsyncValue : public RefCounted {
+  // AsyncValue similar to an AsyncToken created with a reference count of 2.
+  AsyncValue(AsyncRuntime *runtime, int32_t size)
+      : RefCounted(runtime, /*count=*/2), storage(size) {}
+
+  // Internal state below guarded by a mutex.
+  std::mutex mu;
+  std::condition_variable cv;
+
+  bool ready = false;
+  std::vector<std::function<void()>> awaiters;
+
+  // Use vector of bytes to store async value payload.
+  std::vector<int8_t> storage;
+};
+
+// Async group provides a mechanism to group together multiple async tokens or
+// values to await on all of them together (wait for the completion of all
+// tokens or values added to the group).
 struct AsyncGroup : public RefCounted {
   AsyncGroup(AsyncRuntime *runtime)
       : RefCounted(runtime), pendingTokens(0), rank(0) {}
@@ -159,12 +182,18 @@ extern "C" void mlirAsyncRuntimeDropRef(RefCountedObjPtr ptr, int32_t count) {
   refCounted->dropRef(count);
 }
 
-// Create a new `async.token` in not-ready state.
+// Creates a new `async.token` in not-ready state.
 extern "C" AsyncToken *mlirAsyncRuntimeCreateToken() {
   AsyncToken *token = new AsyncToken(getDefaultAsyncRuntimeInstance());
   return token;
 }
 
+// Creates a new `async.value` in not-ready state.
+extern "C" AsyncValue *mlirAsyncRuntimeCreateValue(int32_t size) {
+  AsyncValue *value = new AsyncValue(getDefaultAsyncRuntimeInstance(), size);
+  return value;
+}
+
 // Create a new `async.group` in empty state.
 extern "C" AsyncGroup *mlirAsyncRuntimeCreateGroup() {
   AsyncGroup *group = new AsyncGroup(getDefaultAsyncRuntimeInstance());
@@ -228,18 +257,45 @@ extern "C" void mlirAsyncRuntimeEmplaceToken(AsyncToken *token) {
   token->dropRef();
 }
 
+// Switches `async.value` to ready state and runs all awaiters.
+extern "C" void mlirAsyncRuntimeEmplaceValue(AsyncValue *value) {
+  // Make sure that `dropRef` does not destroy the mutex owned by the lock.
+  {
+    std::unique_lock<std::mutex> lock(value->mu);
+    value->ready = true;
+    value->cv.notify_all();
+    for (auto &awaiter : value->awaiters)
+      awaiter();
+  }
+
+  // Async values created with a ref count `2` to keep value alive until the
+  // async task completes. Drop this reference explicitly when value emplaced.
+  value->dropRef();
+}
+
 extern "C" void mlirAsyncRuntimeAwaitToken(AsyncToken *token) {
   std::unique_lock<std::mutex> lock(token->mu);
   if (!token->ready)
     token->cv.wait(lock, [token] { return token->ready; });
 }
 
+extern "C" void mlirAsyncRuntimeAwaitValue(AsyncValue *value) {
+  std::unique_lock<std::mutex> lock(value->mu);
+  if (!value->ready)
+    value->cv.wait(lock, [value] { return value->ready; });
+}
+
 extern "C" void mlirAsyncRuntimeAwaitAllInGroup(AsyncGroup *group) {
   std::unique_lock<std::mutex> lock(group->mu);
   if (group->pendingTokens != 0)
     group->cv.wait(lock, [group] { return group->pendingTokens == 0; });
 }
 
+// Returns a pointer to the storage owned by the async value.
+extern "C" ValueStorage mlirAsyncRuntimeGetValueStorage(AsyncValue *value) {
+  return value->storage.data();
+}
+
 extern "C" void mlirAsyncRuntimeExecute(CoroHandle handle, CoroResume resume) {
   (*resume)(handle);
 }
@@ -255,6 +311,17 @@ extern "C" void mlirAsyncRuntimeAwaitTokenAndExecute(AsyncToken *token,
     token->awaiters.push_back([execute]() { execute(); });
 }
 
+extern "C" void mlirAsyncRuntimeAwaitValueAndExecute(AsyncValue *value,
+                                                     CoroHandle handle,
+                                                     CoroResume resume) {
+  std::unique_lock<std::mutex> lock(value->mu);
+  auto execute = [handle, resume]() { (*resume)(handle); };
+  if (value->ready)
+    execute();
+  else
+    value->awaiters.push_back([execute]() { execute(); });
+}
+
 extern "C" void mlirAsyncRuntimeAwaitAllInGroupAndExecute(AsyncGroup *group,
                                                           CoroHandle handle,
                                                           CoroResume resume) {
diff --git a/mlir/lib/ExecutionEngine/JitRunner.cpp b/mlir/lib/ExecutionEngine/JitRunner.cpp
index a323e68170c1b..bfdae2b4588d5 100644
--- a/mlir/lib/ExecutionEngine/JitRunner.cpp
+++ b/mlir/lib/ExecutionEngine/JitRunner.cpp
@@ -196,19 +196,30 @@ template <typename Type>
 Error checkCompatibleReturnType(LLVM::LLVMFuncOp mainFunction);
 template <>
 Error checkCompatibleReturnType<int32_t>(LLVM::LLVMFuncOp mainFunction) {
-  if (!mainFunction.getType().getFunctionResultType().isIntegerTy(32))
+  auto resultType = mainFunction.getType()
+                        .cast<LLVM::LLVMFunctionType>()
+                        .getReturnType()
+                        .dyn_cast<LLVM::LLVMIntegerType>();
+  if (!resultType || resultType.getBitWidth() != 32)
     return make_string_error("only single llvm.i32 function result supported");
   return Error::success();
 }
 template <>
 Error checkCompatibleReturnType<int64_t>(LLVM::LLVMFuncOp mainFunction) {
-  if (!mainFunction.getType().getFunctionResultType().isIntegerTy(64))
+  auto resultType = mainFunction.getType()
+                        .cast<LLVM::LLVMFunctionType>()
+                        .getReturnType()
+                        .dyn_cast<LLVM::LLVMIntegerType>();
+  if (!resultType || resultType.getBitWidth() != 64)
     return make_string_error("only single llvm.i64 function result supported");
   return Error::success();
 }
 template <>
 Error checkCompatibleReturnType<float>(LLVM::LLVMFuncOp mainFunction) {
-  if (!mainFunction.getType().getFunctionResultType().isFloatTy())
+  if (!mainFunction.getType()
+           .cast<LLVM::LLVMFunctionType>()
+           .getReturnType()
+           .isa<LLVM::LLVMFloatType>())
     return make_string_error("only single llvm.f32 function result supported");
   return Error::success();
 }
@@ -220,7 +231,7 @@ Error compileAndExecuteSingleReturnFunction(Options &options, ModuleOp module,
   if (!mainFunction || mainFunction.isExternal())
     return make_string_error("entry point not found");
 
-  if (mainFunction.getType().getFunctionNumParams() != 0)
+  if (mainFunction.getType().cast<LLVM::LLVMFunctionType>().getNumParams() != 0)
     return make_string_error("function inputs not supported");
 
   if (Error error = checkCompatibleReturnType<Type>(mainFunction))
diff --git a/mlir/lib/IR/Value.cpp b/mlir/lib/IR/Value.cpp
index fd7e5b5d64e5f..b29641a084a06 100644
--- a/mlir/lib/IR/Value.cpp
+++ b/mlir/lib/IR/Value.cpp
@@ -32,6 +32,11 @@ Value::Value(Operation *op, unsigned resultNo) {
 
 /// Return the type of this value.
 Type Value::getType() const {
+  // Support a null Value so the asmprinter doesn't crash on invalid IR (e.g.
+  // operations that have dropAllReferences() called on them).
+  if (!*this)
+    return Type();
+
   if (BlockArgument arg = dyn_cast<BlockArgument>())
     return arg.getType();
 
diff --git a/mlir/lib/TableGen/Type.cpp b/mlir/lib/TableGen/Type.cpp
index 5fe6bbbd5e83b..826821937dca3 100644
--- a/mlir/lib/TableGen/Type.cpp
+++ b/mlir/lib/TableGen/Type.cpp
@@ -53,6 +53,11 @@ Optional<StringRef> TypeConstraint::getBuilderCall() const {
       .Default([](auto *) { return llvm::None; });
 }
 
+// Return the C++ class name for this type (which may just be ::mlir::Type).
+StringRef TypeConstraint::getCPPClassName() const {
+  return def->getValueAsString("cppClassName");
+}
+
 Type::Type(const llvm::Record *record) : TypeConstraint(record) {}
 
 StringRef Type::getTypeDescription() const {
diff --git a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
index 7f89a41de5db7..9786751ef4b0d 100644
--- a/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
+++ b/mlir/lib/Target/LLVMIR/ConvertFromLLVMIR.cpp
@@ -172,57 +172,57 @@ Type Importer::getStdTypeForAttr(LLVMType type) {
   if (!type)
     return nullptr;
 
-  if (type.isIntegerTy())
-    return b.getIntegerType(type.getIntegerBitWidth());
+  if (auto intType = type.dyn_cast<LLVMIntegerType>())
+    return b.getIntegerType(intType.getBitWidth());
 
-  if (type.isFloatTy())
+  if (type.isa<LLVMFloatType>())
     return b.getF32Type();
 
-  if (type.isDoubleTy())
+  if (type.isa<LLVMDoubleType>())
     return b.getF64Type();
 
   // LLVM vectors can only contain scalars.
-  if (type.isVectorTy()) {
-    auto numElements = type.getVectorElementCount();
+  if (auto vectorType = type.dyn_cast<LLVM::LLVMVectorType>()) {
+    auto numElements = vectorType.getElementCount();
     if (numElements.isScalable()) {
       emitError(unknownLoc) << "scalable vectors not supported";
       return nullptr;
     }
-    Type elementType = getStdTypeForAttr(type.getVectorElementType());
+    Type elementType = getStdTypeForAttr(vectorType.getElementType());
     if (!elementType)
       return nullptr;
     return VectorType::get(numElements.getKnownMinValue(), elementType);
   }
 
   // LLVM arrays can contain other arrays or vectors.
-  if (type.isArrayTy()) {
+  if (auto arrayType = type.dyn_cast<LLVMArrayType>()) {
     // Recover the nested array shape.
     SmallVector<int64_t, 4> shape;
-    shape.push_back(type.getArrayNumElements());
-    while (type.getArrayElementType().isArrayTy()) {
-      type = type.getArrayElementType();
-      shape.push_back(type.getArrayNumElements());
+    shape.push_back(arrayType.getNumElements());
+    while (arrayType.getElementType().isa<LLVMArrayType>()) {
+      arrayType = arrayType.getElementType().cast<LLVMArrayType>();
+      shape.push_back(arrayType.getNumElements());
     }
 
     // If the innermost type is a vector, use the multi-dimensional vector as
     // attribute type.
-    if (type.getArrayElementType().isVectorTy()) {
-      LLVMType vectorType = type.getArrayElementType();
-      auto numElements = vectorType.getVectorElementCount();
+    if (auto vectorType =
+            arrayType.getElementType().dyn_cast<LLVMVectorType>()) {
+      auto numElements = vectorType.getElementCount();
       if (numElements.isScalable()) {
         emitError(unknownLoc) << "scalable vectors not supported";
         return nullptr;
       }
       shape.push_back(numElements.getKnownMinValue());
 
-      Type elementType = getStdTypeForAttr(vectorType.getVectorElementType());
+      Type elementType = getStdTypeForAttr(vectorType.getElementType());
       if (!elementType)
         return nullptr;
       return VectorType::get(shape, elementType);
     }
 
     // Otherwise use a tensor.
-    Type elementType = getStdTypeForAttr(type.getArrayElementType());
+    Type elementType = getStdTypeForAttr(arrayType.getElementType());
     if (!elementType)
       return nullptr;
     return RankedTensorType::get(shape, elementType);
@@ -261,7 +261,7 @@ Attribute Importer::getConstantAsAttr(llvm::Constant *value) {
     if (!attrType)
       return nullptr;
 
-    if (type.isIntegerTy()) {
+    if (type.isa<LLVMIntegerType>()) {
       SmallVector<APInt, 8> values;
       values.reserve(cd->getNumElements());
       for (unsigned i = 0, e = cd->getNumElements(); i < e; ++i)
@@ -269,7 +269,7 @@ Attribute Importer::getConstantAsAttr(llvm::Constant *value) {
       return DenseElementsAttr::get(attrType, values);
     }
 
-    if (type.isFloatTy() || type.isDoubleTy()) {
+    if (type.isa<LLVMFloatType>() || type.isa<LLVMDoubleType>()) {
       SmallVector<APFloat, 8> values;
       values.reserve(cd->getNumElements());
       for (unsigned i = 0, e = cd->getNumElements(); i < e; ++i)
@@ -777,7 +777,8 @@ LogicalResult Importer::processFunction(llvm::Function *f) {
   instMap.clear();
   unknownInstMap.clear();
 
-  LLVMType functionType = processType(f->getFunctionType());
+  auto functionType =
+      processType(f->getFunctionType()).dyn_cast<LLVMFunctionType>();
   if (!functionType)
     return failure();
 
@@ -805,8 +806,8 @@ LogicalResult Importer::processFunction(llvm::Function *f) {
 
   // Add function arguments to the entry block.
   for (auto kv : llvm::enumerate(f->args()))
-    instMap[&kv.value()] = blockList[0]->addArgument(
-        functionType.getFunctionParamType(kv.index()));
+    instMap[&kv.value()] =
+        blockList[0]->addArgument(functionType.getParamType(kv.index()));
 
   for (auto bbs : llvm::zip(*f, blockList)) {
     if (failed(processBasicBlock(&std::get<0>(bbs), std::get<1>(bbs))))
diff --git a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
index 8c650506e2d74..c28588d32ad6c 100644
--- a/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
@@ -536,6 +536,126 @@ LogicalResult ModuleTranslation::convertOmpMaster(Operation &opInst,
   return success();
 }
 
+/// Converts an OpenMP workshare loop into LLVM IR using OpenMPIRBuilder.
+LogicalResult ModuleTranslation::convertOmpWsLoop(Operation &opInst,
+                                                  llvm::IRBuilder<> &builder) {
+  auto loop = cast<omp::WsLoopOp>(opInst);
+  // TODO: this should be in the op verifier instead.
+  if (loop.lowerBound().empty())
+    return failure();
+
+  if (loop.getNumLoops() != 1)
+    return opInst.emitOpError("collapsed loops not yet supported");
+
+  if (loop.schedule_val().hasValue() &&
+      omp::symbolizeClauseScheduleKind(loop.schedule_val().getValue()) !=
+          omp::ClauseScheduleKind::Static)
+    return opInst.emitOpError(
+        "only static (default) loop schedule is currently supported");
+
+  llvm::Function *func = builder.GetInsertBlock()->getParent();
+  llvm::LLVMContext &llvmContext = llvmModule->getContext();
+
+  // Find the loop configuration.
+  llvm::Value *lowerBound = valueMapping.lookup(loop.lowerBound()[0]);
+  llvm::Value *upperBound = valueMapping.lookup(loop.upperBound()[0]);
+  llvm::Value *step = valueMapping.lookup(loop.step()[0]);
+  llvm::Type *ivType = step->getType();
+  llvm::Value *chunk = loop.schedule_chunk_var()
+                           ? valueMapping[loop.schedule_chunk_var()]
+                           : llvm::ConstantInt::get(ivType, 1);
+
+  // Set up the source location value for OpenMP runtime.
+  llvm::DISubprogram *subprogram =
+      builder.GetInsertBlock()->getParent()->getSubprogram();
+  const llvm::DILocation *diLoc =
+      debugTranslation->translateLoc(opInst.getLoc(), subprogram);
+  llvm::OpenMPIRBuilder::LocationDescription ompLoc(builder.saveIP(),
+                                                    llvm::DebugLoc(diLoc));
+
+  // Generator of the canonical loop body. Produces an SESE region of basic
+  // blocks.
+  // TODO: support error propagation in OpenMPIRBuilder and use it instead of
+  // relying on captured variables.
+  LogicalResult bodyGenStatus = success();
+  auto bodyGen = [&](llvm::OpenMPIRBuilder::InsertPointTy ip, llvm::Value *iv) {
+    llvm::IRBuilder<>::InsertPointGuard guard(builder);
+
+    // Make sure further conversions know about the induction variable.
+    valueMapping[loop.getRegion().front().getArgument(0)] = iv;
+
+    llvm::BasicBlock *entryBlock = ip.getBlock();
+    llvm::BasicBlock *exitBlock =
+        entryBlock->splitBasicBlock(ip.getPoint(), "omp.wsloop.exit");
+
+    // Convert the body of the loop.
+    Region &region = loop.region();
+    for (Block &bb : region) {
+      llvm::BasicBlock *llvmBB =
+          llvm::BasicBlock::Create(llvmContext, "omp.wsloop.region", func);
+      blockMapping[&bb] = llvmBB;
+
+      // Retarget the branch of the entry block to the entry block of the
+      // converted region (regions are single-entry).
+      if (bb.isEntryBlock()) {
+        auto *branch = cast<llvm::BranchInst>(entryBlock->getTerminator());
+        branch->setSuccessor(0, llvmBB);
+      }
+    }
+
+    // Block conversion creates a new IRBuilder every time so need not bother
+    // about maintaining the insertion point.
+    llvm::SetVector<Block *> blocks = topologicalSort(region);
+    for (Block *bb : blocks) {
+      if (failed(convertBlock(*bb, bb->isEntryBlock()))) {
+        bodyGenStatus = failure();
+        return;
+      }
+
+      // Special handling for `omp.yield` terminators (we may have more than
+      // one): they return the control to the parent WsLoop operation so replace
+      // them with the branch to the exit block. We handle this here to avoid
+      // relying inter-function communication through the ModuleTranslation
+      // class to set up the correct insertion point. This is also consistent
+      // with MLIR's idiom of handling special region terminators in the same
+      // code that handles the region-owning operation.
+      if (isa<omp::YieldOp>(bb->getTerminator())) {
+        llvm::BasicBlock *llvmBB = blockMapping[bb];
+        builder.SetInsertPoint(llvmBB, llvmBB->end());
+        builder.CreateBr(exitBlock);
+      }
+    }
+
+    connectPHINodes(region, valueMapping, blockMapping, branchMapping);
+  };
+
+  // Delegate actual loop construction to the OpenMP IRBuilder.
+  // TODO: this currently assumes WsLoop is semantically similar to SCF loop,
+  // i.e. it has a positive step, uses signed integer semantics, and its upper
+  // bound is not included. Reconsider this code when WsLoop clearly supports
+  // more cases.
+  llvm::BasicBlock *insertBlock = builder.GetInsertBlock();
+  llvm::CanonicalLoopInfo *loopInfo = ompBuilder->createCanonicalLoop(
+      ompLoc, bodyGen, lowerBound, upperBound, step, /*IsSigned=*/true,
+      /*InclusiveStop=*/false);
+  if (failed(bodyGenStatus))
+    return failure();
+
+  // TODO: get the alloca insertion point from the parallel operation builder.
+  // If we insert the at the top of the current function, they will be passed as
+  // extra arguments into the function the parallel operation builder outlines.
+  // Put them at the start of the current block for now.
+  llvm::OpenMPIRBuilder::InsertPointTy allocaIP(
+      insertBlock, insertBlock->getFirstInsertionPt());
+  loopInfo = ompBuilder->createStaticWorkshareLoop(
+      ompLoc, loopInfo, allocaIP,
+      !loop.nowait().hasValue() || loop.nowait().getValue(), chunk);
+
+  // Continue building IR after the loop.
+  builder.restoreIP(loopInfo->getAfterIP());
+  return success();
+}
+
 /// Given an OpenMP MLIR operation, create the corresponding LLVM IR
 /// (including OpenMP runtime calls).
 LogicalResult
@@ -577,6 +697,13 @@ ModuleTranslation::convertOmpOperation(Operation &opInst,
       .Case(
           [&](omp::ParallelOp) { return convertOmpParallel(opInst, builder); })
       .Case([&](omp::MasterOp) { return convertOmpMaster(opInst, builder); })
+      .Case([&](omp::WsLoopOp) { return convertOmpWsLoop(opInst, builder); })
+      .Case([&](omp::YieldOp op) {
+        // Yields are loop terminators that can be just omitted. The loop
+        // structure was created in the function that handles WsLoopOp.
+        assert(op.getNumOperands() == 0 && "unexpected yield with operands");
+        return success();
+      })
       .Default([&](Operation *inst) {
         return inst->emitError("unsupported OpenMP operation: ")
                << inst->getName();
@@ -642,13 +769,12 @@ LogicalResult ModuleTranslation::convertOperation(Operation &opInst,
 
     LLVM::LLVMType resultType;
     if (inlineAsmOp.getNumResults() == 0) {
-      resultType = LLVM::LLVMType::getVoidTy(mlirModule->getContext());
+      resultType = LLVM::LLVMVoidType::get(mlirModule->getContext());
     } else {
       assert(inlineAsmOp.getNumResults() == 1);
       resultType = inlineAsmOp.getResultTypes()[0].cast<LLVM::LLVMType>();
     }
-    auto ft = LLVM::LLVMType::getFunctionTy(resultType, operandTypes,
-                                            /*isVarArg=*/false);
+    auto ft = LLVM::LLVMFunctionType::get(resultType, operandTypes);
     llvm::InlineAsm *inlineAsmInst =
         inlineAsmOp.asm_dialect().hasValue()
             ? llvm::InlineAsm::get(
@@ -969,7 +1095,7 @@ LogicalResult ModuleTranslation::convertOneFunction(LLVMFuncOp func) {
       // NB: Attribute already verified to be boolean, so check if we can indeed
       // attach the attribute to this argument, based on its type.
       auto argTy = mlirArg.getType().dyn_cast<LLVM::LLVMType>();
-      if (!argTy.isPointerTy())
+      if (!argTy.isa<LLVM::LLVMPointerType>())
         return func.emitError(
             "llvm.noalias attribute attached to LLVM non-pointer argument");
       if (attr.getValue())
@@ -981,7 +1107,7 @@ LogicalResult ModuleTranslation::convertOneFunction(LLVMFuncOp func) {
       // NB: Attribute already verified to be int, so check if we can indeed
       // attach the attribute to this argument, based on its type.
       auto argTy = mlirArg.getType().dyn_cast<LLVM::LLVMType>();
-      if (!argTy.isPointerTy())
+      if (!argTy.isa<LLVM::LLVMPointerType>())
         return func.emitError(
             "llvm.align attribute attached to LLVM non-pointer argument");
       llvmArg.addAttrs(
diff --git a/mlir/lib/Target/SPIRV/Deserialization.cpp b/mlir/lib/Target/SPIRV/Deserialization.cpp
index 94ea19f94123c..30f46f6fc6056 100644
--- a/mlir/lib/Target/SPIRV/Deserialization.cpp
+++ b/mlir/lib/Target/SPIRV/Deserialization.cpp
@@ -34,6 +34,10 @@ using namespace mlir;
 
 #define DEBUG_TYPE "spirv-deserialization"
 
+//===----------------------------------------------------------------------===//
+// Utility Functions
+//===----------------------------------------------------------------------===//
+
 /// Decodes a string literal in `words` starting at `wordIndex`. Update the
 /// latter to point to the position in words after the string literal.
 static inline StringRef decodeStringLiteral(ArrayRef<uint32_t> words,
@@ -55,6 +59,10 @@ static inline bool isFnEntryBlock(Block *block) {
 }
 
 namespace {
+//===----------------------------------------------------------------------===//
+// Utility Definitions
+//===----------------------------------------------------------------------===//
+
 /// A struct for containing a header block's merge and continue targets.
 ///
 /// This struct is used to track original structured control flow info from
@@ -124,6 +132,10 @@ struct DeferredStructTypeInfo {
   SmallVector<spirv::StructType::MemberDecorationInfo, 0> memberDecorationsInfo;
 };
 
+//===----------------------------------------------------------------------===//
+// Deserializer Declaration
+//===----------------------------------------------------------------------===//
+
 /// A SPIR-V module serializer.
 ///
 /// A SPIR-V binary module is a single linear stream of instructions; each
@@ -423,6 +435,14 @@ class Deserializer {
                                    ArrayRef<uint32_t> operands,
                                    bool deferInstructions = true);
 
+  /// Processes a SPIR-V instruction from the given `operands`. It should
+  /// deserialize into an op with the given `opName` and `numOperands`.
+  /// This method is a generic one for dispatching any SPIR-V ops without
+  /// variadic operands and attributes in TableGen definitions.
+  LogicalResult processOpWithoutGrammarAttr(ArrayRef<uint32_t> words,
+                                            StringRef opName, bool hasResult,
+                                            unsigned numOperands);
+
   /// Processes a OpUndef instruction. Adds a spv.Undef operation at the current
   /// insertion point.
   LogicalResult processUndef(ArrayRef<uint32_t> operands);
@@ -580,6 +600,10 @@ class Deserializer {
 };
 } // namespace
 
+//===----------------------------------------------------------------------===//
+// Deserializer Method Definitions
+//===----------------------------------------------------------------------===//
+
 Deserializer::Deserializer(ArrayRef<uint32_t> binary, MLIRContext *context)
     : binary(binary), context(context), unknownLoc(UnknownLoc::get(context)),
       module(createModuleOp()), opBuilder(module->body()) {}
@@ -2497,6 +2521,87 @@ LogicalResult Deserializer::processInstruction(spirv::Opcode opcode,
   return dispatchToAutogenDeserialization(opcode, operands);
 }
 
+LogicalResult
+Deserializer::processOpWithoutGrammarAttr(ArrayRef<uint32_t> words,
+                                          StringRef opName, bool hasResult,
+                                          unsigned numOperands) {
+  SmallVector<Type, 1> resultTypes;
+  uint32_t valueID = 0;
+
+  size_t wordIndex= 0;
+  if (hasResult) {
+    if (wordIndex >= words.size())
+      return emitError(unknownLoc,
+                       "expected result type <id> while deserializing for ")
+             << opName;
+
+    // Decode the type <id>
+    auto type = getType(words[wordIndex]);
+    if (!type)
+      return emitError(unknownLoc, "unknown type result <id>: ")
+             << words[wordIndex];
+    resultTypes.push_back(type);
+    ++wordIndex;
+
+    // Decode the result <id>
+    if (wordIndex >= words.size())
+      return emitError(unknownLoc,
+                       "expected result <id> while deserializing for ")
+             << opName;
+    valueID = words[wordIndex];
+    ++wordIndex;
+  }
+
+  SmallVector<Value, 4> operands;
+  SmallVector<NamedAttribute, 4> attributes;
+
+  // Decode operands
+  size_t operandIndex = 0;
+  for (; operandIndex < numOperands && wordIndex < words.size();
+       ++operandIndex, ++wordIndex) {
+    auto arg = getValue(words[wordIndex]);
+    if (!arg)
+      return emitError(unknownLoc, "unknown result <id>: ") << words[wordIndex];
+    operands.push_back(arg);
+  }
+  if (operandIndex != numOperands) {
+    return emitError(
+               unknownLoc,
+               "found less operands than expected when deserializing for ")
+           << opName << "; only " << operandIndex << " of " << numOperands
+           << " processed";
+  }
+  if (wordIndex != words.size()) {
+    return emitError(
+               unknownLoc,
+               "found more operands than expected when deserializing for ")
+           << opName << "; only " << wordIndex << " of " << words.size()
+           << " processed";
+  }
+
+  // Attach attributes from decorations
+  if (decorations.count(valueID)) {
+    auto attrs = decorations[valueID].getAttrs();
+    attributes.append(attrs.begin(), attrs.end());
+  }
+
+  // Create the op and update bookkeeping maps
+  Location loc = createFileLineColLoc(opBuilder);
+  OperationState opState(loc, opName);
+  opState.addOperands(operands);
+  if (hasResult)
+    opState.addTypes(resultTypes);
+  opState.addAttributes(attributes);
+  Operation *op = opBuilder.createOperation(opState);
+  if (hasResult)
+    valueMap[valueID] = op->getResult(0);
+
+  if (op->hasTrait<OpTrait::IsTerminator>())
+    clearDebugLine();
+
+  return success();
+}
+
 LogicalResult Deserializer::processUndef(ArrayRef<uint32_t> operands) {
   if (operands.size() != 2) {
     return emitError(unknownLoc, "OpUndef instruction must have two operands");
@@ -2779,6 +2884,7 @@ Deserializer::processOp<spirv::CopyMemoryOp>(ArrayRef<uint32_t> words) {
 // various Deserializer::processOp<...>() specializations.
 #define GET_DESERIALIZATION_FNS
 #include "mlir/Dialect/SPIRV/IR/SPIRVSerialization.inc"
+
 } // namespace
 
 namespace mlir {
diff --git a/mlir/lib/Target/SPIRV/Serialization.cpp b/mlir/lib/Target/SPIRV/Serialization.cpp
index db00f5ecf8996..c530cccd4232a 100644
--- a/mlir/lib/Target/SPIRV/Serialization.cpp
+++ b/mlir/lib/Target/SPIRV/Serialization.cpp
@@ -364,15 +364,23 @@ class Serializer {
   /// Main dispatch method for serializing an operation.
   LogicalResult processOperation(Operation *op);
 
-  /// Method to dispatch to the serialization function for an operation in
-  /// SPIR-V dialect that is a mirror of an instruction in the SPIR-V spec.
-  /// This is auto-generated from ODS. Dispatch is handled for all operations
-  /// in SPIR-V dialect that have hasOpcode == 1.
+  /// Serializes an operation `op` as core instruction with `opcode` if
+  /// `extInstSet` is empty. Otherwise serializes it as an extended instruction
+  /// with `opcode` from `extInstSet`.
+  /// This method is a generic one for dispatching any SPIR-V ops that has no
+  /// variadic operands and attributes in TableGen definitions.
+  LogicalResult processOpWithoutGrammarAttr(Operation *op, StringRef extInstSet,
+                                            uint32_t opcode);
+
+  /// Dispatches to the serialization function for an operation in SPIR-V
+  /// dialect that is a mirror of an instruction in the SPIR-V spec. This is
+  /// auto-generated from ODS. Dispatch is handled for all operations in SPIR-V
+  /// dialect that have hasOpcode == 1.
   LogicalResult dispatchToAutogenSerialization(Operation *op);
 
-  /// Method to serialize an operation in the SPIR-V dialect that is a mirror of
-  /// an instruction in the SPIR-V spec. This is auto generated if hasOpcode ==
-  /// 1 and autogenSerialization == 1 in ODS.
+  /// Serializes an operation in the SPIR-V dialect that is a mirror of an
+  /// instruction in the SPIR-V spec. This is auto generated if hasOpcode == 1
+  /// and autogenSerialization == 1 in ODS.
   template <typename OpTy>
   LogicalResult processOp(OpTy op) {
     return op.emitError("unsupported op serialization");
@@ -1930,6 +1938,46 @@ LogicalResult Serializer::processOperation(Operation *opInst) {
           [&](Operation *op) { return dispatchToAutogenSerialization(op); });
 }
 
+LogicalResult Serializer::processOpWithoutGrammarAttr(Operation *op,
+                                                      StringRef extInstSet,
+                                                      uint32_t opcode) {
+  SmallVector<uint32_t, 4> operands;
+  Location loc = op->getLoc();
+
+  uint32_t resultID = 0;
+  if (op->getNumResults() != 0) {
+    uint32_t resultTypeID = 0;
+    if (failed(processType(loc, op->getResult(0).getType(), resultTypeID)))
+      return failure();
+    operands.push_back(resultTypeID);
+
+    resultID = getNextID();
+    operands.push_back(resultID);
+    valueIDMap[op->getResult(0)] = resultID;
+  };
+
+  for (Value operand : op->getOperands())
+    operands.push_back(getValueID(operand));
+
+  emitDebugLine(functionBody, loc);
+
+  if (extInstSet.empty()) {
+    encodeInstructionInto(functionBody, static_cast<spirv::Opcode>(opcode),
+                          operands);
+  } else {
+    encodeExtensionInstruction(op, extInstSet, opcode, operands);
+  }
+
+  if (op->getNumResults() != 0) {
+    for (auto attr : op->getAttrs()) {
+      if (failed(processDecoration(loc, resultID, attr)))
+        return failure();
+    }
+  }
+
+  return success();
+}
+
 namespace {
 template <>
 LogicalResult
diff --git a/mlir/test/Conversion/AffineToStandard/lower-affine.mlir b/mlir/test/Conversion/AffineToStandard/lower-affine.mlir
index f89d913cb64a1..38d269913e51c 100644
--- a/mlir/test/Conversion/AffineToStandard/lower-affine.mlir
+++ b/mlir/test/Conversion/AffineToStandard/lower-affine.mlir
@@ -26,6 +26,30 @@ func @simple_loop() {
 
 /////////////////////////////////////////////////////////////////////
 
+func @for_with_yield(%buffer: memref<1024xf32>) -> (f32) {
+  %sum_0 = constant 0.0 : f32
+  %sum = affine.for %i = 0 to 10 step 2 iter_args(%sum_iter = %sum_0) -> (f32) {
+    %t = affine.load %buffer[%i] : memref<1024xf32>
+    %sum_next = addf %sum_iter, %t : f32
+    affine.yield %sum_next : f32
+  }
+  return %sum : f32
+}
+
+// CHECK-LABEL: func @for_with_yield
+// CHECK:         %[[INIT_SUM:.*]] = constant 0.000000e+00 : f32
+// CHECK-NEXT:    %[[LOWER:.*]] = constant 0 : index
+// CHECK-NEXT:    %[[UPPER:.*]] = constant 10 : index
+// CHECK-NEXT:    %[[STEP:.*]] = constant 2 : index
+// CHECK-NEXT:    %[[SUM:.*]] = scf.for %[[IV:.*]] = %[[LOWER]] to %[[UPPER]] step %[[STEP]] iter_args(%[[SUM_ITER:.*]] = %[[INIT_SUM]]) -> (f32) {
+// CHECK-NEXT:      load
+// CHECK-NEXT:      %[[SUM_NEXT:.*]] = addf
+// CHECK-NEXT:      scf.yield %[[SUM_NEXT]] : f32
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return %[[SUM]] : f32
+
+/////////////////////////////////////////////////////////////////////
+
 func private @pre(index) -> ()
 func private @body2(index, index) -> ()
 func private @post(index) -> ()
@@ -674,3 +698,104 @@ func @affine_parallel_tiled(%o: memref<100x100xf32>, %a: memref<100x100xf32>, %b
 // CHECK:             %[[A4:.*]] = load %[[ARG2]][%[[arg8]], %[[arg7]]] : memref<100x100xf32>
 // CHECK:             mulf %[[A3]], %[[A4]] : f32
 // CHECK:             scf.yield
+
+/////////////////////////////////////////////////////////////////////
+
+func @affine_parallel_simple(%arg0: memref<3x3xf32>, %arg1: memref<3x3xf32>) -> (memref<3x3xf32>) {
+  %O = alloc() : memref<3x3xf32>
+  affine.parallel (%kx, %ky) = (0, 0) to (2, 2) {
+      %1 = affine.load %arg0[%kx, %ky] : memref<3x3xf32>
+      %2 = affine.load %arg1[%kx, %ky] : memref<3x3xf32>
+      %3 = mulf %1, %2 : f32
+      affine.store %3, %O[%kx, %ky] : memref<3x3xf32>
+  }
+  return %O : memref<3x3xf32>
+}
+// CHECK-LABEL: func @affine_parallel_simple
+// CHECK:         %[[LOWER_1:.*]] = constant 0 : index
+// CHECK-NEXT:    %[[LOWER_2:.*]] = constant 0 : index
+// CHECK-NEXT:    %[[UPPER_1:.*]] = constant 2 : index
+// CHECK-NEXT:    %[[UPPER_2:.*]] = constant 2 : index
+// CHECK-NEXT:    %[[STEP_1:.*]] = constant 1 : index
+// CHECK-NEXT:    %[[STEP_2:.*]] = constant 1 : index
+// CHECK-NEXT:    scf.parallel (%[[I:.*]], %[[J:.*]]) = (%[[LOWER_1]], %[[LOWER_2]]) to (%[[UPPER_1]], %[[UPPER_2]]) step (%[[STEP_1]], %[[STEP_2]]) {
+// CHECK-NEXT:      %[[VAL_1:.*]] = load
+// CHECK-NEXT:      %[[VAL_2:.*]] = load
+// CHECK-NEXT:      %[[PRODUCT:.*]] = mulf
+// CHECK-NEXT:      store
+// CHECK-NEXT:      scf.yield
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return
+// CHECK-NEXT:  }
+
+/////////////////////////////////////////////////////////////////////
+
+func @affine_parallel_simple_dynamic_bounds(%arg0: memref<?x?xf32>, %arg1: memref<?x?xf32>, %arg2: memref<?x?xf32>) {
+  %c_0 = constant 0 : index
+  %output_dim = dim %arg0, %c_0 : memref<?x?xf32>
+  affine.parallel (%kx, %ky) = (%c_0, %c_0) to (%output_dim, %output_dim) {
+      %1 = affine.load %arg0[%kx, %ky] : memref<?x?xf32>
+      %2 = affine.load %arg1[%kx, %ky] : memref<?x?xf32>
+      %3 = mulf %1, %2 : f32
+      affine.store %3, %arg2[%kx, %ky] : memref<?x?xf32>
+  }
+  return
+}
+// CHECK-LABEL: func @affine_parallel_simple_dynamic_bounds
+// CHECK-SAME:  %[[ARG_0:.*]]: memref<?x?xf32>, %[[ARG_1:.*]]: memref<?x?xf32>, %[[ARG_2:.*]]: memref<?x?xf32>
+// CHECK:         %[[DIM_INDEX:.*]] = constant 0 : index
+// CHECK-NEXT:    %[[UPPER:.*]] = dim %[[ARG_0]], %[[DIM_INDEX]] : memref<?x?xf32>
+// CHECK-NEXT:    %[[LOWER_1:.*]] = constant 0 : index
+// CHECK-NEXT:    %[[LOWER_2:.*]] = constant 0 : index
+// CHECK-NEXT:    %[[STEP_1:.*]] = constant 1 : index
+// CHECK-NEXT:    %[[STEP_2:.*]] = constant 1 : index
+// CHECK-NEXT:    scf.parallel (%[[I:.*]], %[[J:.*]]) = (%[[LOWER_1]], %[[LOWER_2]]) to (%[[UPPER]], %[[UPPER]]) step (%[[STEP_1]], %[[STEP_2]]) {
+// CHECK-NEXT:      %[[VAL_1:.*]] = load
+// CHECK-NEXT:      %[[VAL_2:.*]] = load
+// CHECK-NEXT:      %[[PRODUCT:.*]] = mulf
+// CHECK-NEXT:      store
+// CHECK-NEXT:      scf.yield
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return
+// CHECK-NEXT:  }
+
+/////////////////////////////////////////////////////////////////////
+
+func @affine_parallel_with_reductions(%arg0: memref<3x3xf32>, %arg1: memref<3x3xf32>) -> (f32, f32) {
+  %0:2 = affine.parallel (%kx, %ky) = (0, 0) to (2, 2) reduce ("addf", "mulf") -> (f32, f32) {
+            %1 = affine.load %arg0[%kx, %ky] : memref<3x3xf32>
+            %2 = affine.load %arg1[%kx, %ky] : memref<3x3xf32>
+            %3 = mulf %1, %2 : f32
+            %4 = addf %1, %2 : f32
+            affine.yield %3, %4 : f32, f32
+          }
+  return %0#0, %0#1 : f32, f32
+}
+// CHECK-LABEL: func @affine_parallel_with_reductions
+// CHECK:         %[[LOWER_1:.*]] = constant 0 : index
+// CHECK-NEXT:    %[[LOWER_2:.*]] = constant 0 : index
+// CHECK-NEXT:    %[[UPPER_1:.*]] = constant 2 : index
+// CHECK-NEXT:    %[[UPPER_2:.*]] = constant 2 : index
+// CHECK-NEXT:    %[[STEP_1:.*]] = constant 1 : index
+// CHECK-NEXT:    %[[STEP_2:.*]] = constant 1 : index
+// CHECK-NEXT:    %[[INIT_1:.*]] = constant 0.000000e+00 : f32
+// CHECK-NEXT:    %[[INIT_2:.*]] = constant 1.000000e+00 : f32
+// CHECK-NEXT:    %[[RES:.*]] = scf.parallel (%[[I:.*]], %[[J:.*]]) = (%[[LOWER_1]], %[[LOWER_2]]) to (%[[UPPER_1]], %[[UPPER_2]]) step (%[[STEP_1]], %[[STEP_2]]) init (%[[INIT_1]], %[[INIT_2]]) -> (f32, f32) {
+// CHECK-NEXT:      %[[VAL_1:.*]] = load
+// CHECK-NEXT:      %[[VAL_2:.*]] = load
+// CHECK-NEXT:      %[[PRODUCT:.*]] = mulf
+// CHECK-NEXT:      %[[SUM:.*]] = addf
+// CHECK-NEXT:      scf.reduce(%[[PRODUCT]]) : f32 {
+// CHECK-NEXT:      ^bb0(%[[LHS:.*]]: f32, %[[RHS:.*]]: f32):
+// CHECK-NEXT:        %[[RES:.*]] = addf
+// CHECK-NEXT:        scf.reduce.return %[[RES]] : f32
+// CHECK-NEXT:      }
+// CHECK-NEXT:      scf.reduce(%[[SUM]]) : f32 {
+// CHECK-NEXT:      ^bb0(%[[LHS:.*]]: f32, %[[RHS:.*]]: f32):
+// CHECK-NEXT:        %[[RES:.*]] = mulf
+// CHECK-NEXT:        scf.reduce.return %[[RES]] : f32
+// CHECK-NEXT:      }
+// CHECK-NEXT:      scf.yield
+// CHECK-NEXT:    }
+// CHECK-NEXT:    return
+// CHECK-NEXT:  }
diff --git a/mlir/test/Conversion/AsyncToLLVM/convert-to-llvm.mlir b/mlir/test/Conversion/AsyncToLLVM/convert-to-llvm.mlir
index dadb28dbc0821..75b323490cbb2 100644
--- a/mlir/test/Conversion/AsyncToLLVM/convert-to-llvm.mlir
+++ b/mlir/test/Conversion/AsyncToLLVM/convert-to-llvm.mlir
@@ -211,3 +211,95 @@ func @async_group_await_all(%arg0: f32, %arg1: memref<1xf32>) {
 
 // Emplace result token.
 // CHECK: call @mlirAsyncRuntimeEmplaceToken(%[[RET_1]])
+
+// -----
+
+// CHECK-LABEL: execute_and_return_f32
+func @execute_and_return_f32() -> f32 {
+ // CHECK: %[[RET:.*]]:2 = call @async_execute_fn
+  %token, %result = async.execute -> !async.value<f32> {
+    %c0 = constant 123.0 : f32
+    async.yield %c0 : f32
+  }
+
+  // CHECK: %[[STORAGE:.*]] = call @mlirAsyncRuntimeGetValueStorage(%[[RET]]#1)
+  // CHECK: %[[ST_F32:.*]] = llvm.bitcast %[[STORAGE]]
+  // CHECK: %[[LOADED:.*]] = llvm.load %[[ST_F32]] :  !llvm.ptr<float>
+  // CHECK: %[[CASTED:.*]] = llvm.mlir.cast %[[LOADED]] : !llvm.float to f32
+  %0 = async.await %result : !async.value<f32>
+
+  return %0 : f32
+}
+
+// Function outlined from the async.execute operation.
+// CHECK-LABEL: func private @async_execute_fn()
+// CHECK: %[[TOKEN:.*]] = call @mlirAsyncRuntimeCreateToken()
+// CHECK: %[[VALUE:.*]] = call @mlirAsyncRuntimeCreateValue
+// CHECK: %[[HDL:.*]] = llvm.call @llvm.coro.begin
+
+// Suspend coroutine in the beginning.
+// CHECK: call @mlirAsyncRuntimeExecute(%[[HDL]],
+// CHECK: llvm.call @llvm.coro.suspend
+
+// Emplace result value.
+// CHECK: %[[CST:.*]] = constant 1.230000e+02 : f32
+// CHECK: %[[LLVM_CST:.*]] = llvm.mlir.cast %[[CST]] : f32 to !llvm.float
+// CHECK: %[[STORAGE:.*]] = call @mlirAsyncRuntimeGetValueStorage(%[[VALUE]])
+// CHECK: %[[ST_F32:.*]] = llvm.bitcast %[[STORAGE]]
+// CHECK: llvm.store %[[LLVM_CST]], %[[ST_F32]] : !llvm.ptr<float>
+// CHECK: call @mlirAsyncRuntimeEmplaceValue(%[[VALUE]])
+
+// Emplace result token.
+// CHECK: call @mlirAsyncRuntimeEmplaceToken(%[[TOKEN]])
+
+// -----
+
+// RUN: mlir-opt %s -split-input-file -convert-async-to-llvm | FileCheck %s
+
+func @async_value_operands() {
+  // CHECK: %[[RET:.*]]:2 = call @async_execute_fn
+  %token, %result = async.execute -> !async.value<f32> {
+    %c0 = constant 123.0 : f32
+    async.yield %c0 : f32
+  }
+
+  // CHECK: %[[TOKEN:.*]] = call @async_execute_fn_0(%[[RET]]#1)
+  %token0 = async.execute(%result as %value: !async.value<f32>) {
+    %0 = addf %value, %value : f32
+    async.yield
+  }
+
+  // CHECK: call @mlirAsyncRuntimeAwaitToken(%[[TOKEN]])
+  async.await %token0 : !async.token
+
+  return
+}
+
+// Function outlined from the first async.execute operation.
+// CHECK-LABEL: func private @async_execute_fn()
+
+// Function outlined from the second async.execute operation.
+// CHECK-LABEL: func private @async_execute_fn_0(%arg0: !llvm.ptr<i8>)
+// CHECK: %[[TOKEN:.*]] = call @mlirAsyncRuntimeCreateToken()
+// CHECK: %[[HDL:.*]] = llvm.call @llvm.coro.begin
+
+// Suspend coroutine in the beginning.
+// CHECK: call @mlirAsyncRuntimeExecute(%[[HDL]],
+// CHECK: llvm.call @llvm.coro.suspend
+
+// Suspend coroutine second time waiting for the async operand.
+// CHECK: llvm.call @llvm.coro.save
+// CHECK: call @mlirAsyncRuntimeAwaitValueAndExecute(%arg0, %[[HDL]],
+// CHECK: llvm.call @llvm.coro.suspend
+
+// Get the operand value storage, cast to f32 and add the value.
+// CHECK: %[[STORAGE:.*]] = call @mlirAsyncRuntimeGetValueStorage(%arg0)
+// CHECK: %[[ST_F32:.*]] = llvm.bitcast %[[STORAGE]]
+// CHECK: %[[LOADED:.*]] = llvm.load %[[ST_F32]] :  !llvm.ptr<float>
+// CHECK: %[[CASTED:.*]] = llvm.mlir.cast %[[LOADED]] : !llvm.float to f32
+// CHECK: addf %[[CASTED]], %[[CASTED]] : f32
+
+// Emplace result token.
+// CHECK: call @mlirAsyncRuntimeEmplaceToken(%[[TOKEN]])
+
+
diff --git a/mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir b/mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir
new file mode 100644
index 0000000000000..790c92f92ec96
--- /dev/null
+++ b/mlir/test/Conversion/GPUCommon/lower-memcpy-to-gpu-runtime-calls.mlir
@@ -0,0 +1,19 @@
+// RUN: mlir-opt -allow-unregistered-dialect %s --gpu-to-llvm | FileCheck %s
+
+module attributes {gpu.container_module} {
+
+  // CHECK: func @foo
+  func @foo(%dst : memref<7xf32, 1>, %src : memref<7xf32>) {
+    // CHECK: %[[t0:.*]] = llvm.call @mgpuStreamCreate
+    %t0 = gpu.wait async
+    // CHECK: %[[size_bytes:.*]] = llvm.ptrtoint
+    // CHECK: %[[src:.*]] = llvm.bitcast
+    // CHECK: %[[dst:.*]] = llvm.bitcast
+    // CHECK: llvm.call @mgpuMemcpy(%[[dst]], %[[src]], %[[size_bytes]], %[[t0]])
+    %t1 = gpu.memcpy async [%t0] %dst, %src : memref<7xf32, 1>, memref<7xf32>
+    // CHECK: llvm.call @mgpuStreamSynchronize(%[[t0]])
+    // CHECK: llvm.call @mgpuStreamDestroy(%[[t0]])
+    gpu.wait [%t1]
+    return
+  }
+}
diff --git a/mlir/test/Conversion/GPUToSPIRV/test_spirv_entry_point.mlir b/mlir/test/Conversion/GPUToSPIRV/entry-point.mlir
similarity index 100%
rename from mlir/test/Conversion/GPUToSPIRV/test_spirv_entry_point.mlir
rename to mlir/test/Conversion/GPUToSPIRV/entry-point.mlir
diff --git a/mlir/test/Conversion/GPUToSPIRV/if.mlir b/mlir/test/Conversion/GPUToSPIRV/if.mlir
deleted file mode 100644
index e5e4a4fc7e975..0000000000000
--- a/mlir/test/Conversion/GPUToSPIRV/if.mlir
+++ /dev/null
@@ -1,167 +0,0 @@
-// RUN: mlir-opt -convert-gpu-to-spirv %s -o - | FileCheck %s
-
-module attributes {
-  gpu.container_module,
-  spv.target_env = #spv.target_env<
-    #spv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, {}>
-} {
-  func @main(%arg0 : memref<10xf32>, %arg1 : i1) {
-    %c0 = constant 1 : index
-    gpu.launch_func @kernels::@kernel_simple_selection
-        blocks in (%c0, %c0, %c0) threads in (%c0, %c0, %c0)
-        args(%arg0 : memref<10xf32>, %arg1 : i1)
-    return
-  }
-
-  gpu.module @kernels {
-    // CHECK-LABEL: @kernel_simple_selection
-    gpu.func @kernel_simple_selection(%arg2 : memref<10xf32>, %arg3 : i1) kernel
-    attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} {
-      %value = constant 0.0 : f32
-      %i = constant 0 : index
-
-      // CHECK:       spv.selection {
-      // CHECK-NEXT:    spv.BranchConditional {{%.*}}, [[TRUE:\^.*]], [[MERGE:\^.*]]
-      // CHECK-NEXT:  [[TRUE]]:
-      // CHECK:         spv.Branch [[MERGE]]
-      // CHECK-NEXT:  [[MERGE]]:
-      // CHECK-NEXT:    spv.mlir.merge
-      // CHECK-NEXT:  }
-      // CHECK-NEXT:  spv.Return
-
-      scf.if %arg3 {
-        store %value, %arg2[%i] : memref<10xf32>
-      }
-      gpu.return
-    }
-
-    // CHECK-LABEL: @kernel_nested_selection
-    gpu.func @kernel_nested_selection(%arg3 : memref<10xf32>, %arg4 : memref<10xf32>, %arg5 : i1, %arg6 : i1) kernel
-    attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} {
-      %i = constant 0 : index
-      %j = constant 9 : index
-
-      // CHECK:       spv.selection {
-      // CHECK-NEXT:    spv.BranchConditional {{%.*}}, [[TRUE_TOP:\^.*]], [[FALSE_TOP:\^.*]]
-      // CHECK-NEXT:  [[TRUE_TOP]]:
-      // CHECK-NEXT:    spv.selection {
-      // CHECK-NEXT:      spv.BranchConditional {{%.*}}, [[TRUE_NESTED_TRUE_PATH:\^.*]], [[FALSE_NESTED_TRUE_PATH:\^.*]]
-      // CHECK-NEXT:    [[TRUE_NESTED_TRUE_PATH]]:
-      // CHECK:           spv.Branch [[MERGE_NESTED_TRUE_PATH:\^.*]]
-      // CHECK-NEXT:    [[FALSE_NESTED_TRUE_PATH]]:
-      // CHECK:           spv.Branch [[MERGE_NESTED_TRUE_PATH]]
-      // CHECK-NEXT:    [[MERGE_NESTED_TRUE_PATH]]:
-      // CHECK-NEXT:      spv.mlir.merge
-      // CHECK-NEXT:    }
-      // CHECK-NEXT:    spv.Branch [[MERGE_TOP:\^.*]]
-      // CHECK-NEXT:  [[FALSE_TOP]]:
-      // CHECK-NEXT:    spv.selection {
-      // CHECK-NEXT:      spv.BranchConditional {{%.*}}, [[TRUE_NESTED_FALSE_PATH:\^.*]], [[FALSE_NESTED_FALSE_PATH:\^.*]]
-      // CHECK-NEXT:    [[TRUE_NESTED_FALSE_PATH]]:
-      // CHECK:           spv.Branch [[MERGE_NESTED_FALSE_PATH:\^.*]]
-      // CHECK-NEXT:    [[FALSE_NESTED_FALSE_PATH]]:
-      // CHECK:           spv.Branch [[MERGE_NESTED_FALSE_PATH]]
-      // CHECK:         [[MERGE_NESTED_FALSE_PATH]]:
-      // CHECK-NEXT:      spv.mlir.merge
-      // CHECK-NEXT:    }
-      // CHECK-NEXT:    spv.Branch [[MERGE_TOP]]
-      // CHECK-NEXT:  [[MERGE_TOP]]:
-      // CHECK-NEXT:    spv.mlir.merge
-      // CHECK-NEXT:  }
-      // CHECK-NEXT:  spv.Return
-
-      scf.if %arg5 {
-        scf.if %arg6 {
-          %value = load %arg3[%i] : memref<10xf32>
-          store %value, %arg4[%i] : memref<10xf32>
-        } else {
-          %value = load %arg4[%i] : memref<10xf32>
-          store %value, %arg3[%i] : memref<10xf32>
-        }
-      } else {
-        scf.if %arg6 {
-          %value = load %arg3[%j] : memref<10xf32>
-          store %value, %arg4[%j] : memref<10xf32>
-        } else {
-          %value = load %arg4[%j] : memref<10xf32>
-          store %value, %arg3[%j] : memref<10xf32>
-        }
-      }
-      gpu.return
-    }
-    // CHECK-LABEL: @simple_if_yield
-    gpu.func @simple_if_yield(%arg2 : memref<10xf32>, %arg3 : i1) kernel
-    attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} {
-      // CHECK: %[[VAR1:.*]] = spv.Variable : !spv.ptr<f32, Function>
-      // CHECK: %[[VAR2:.*]] = spv.Variable : !spv.ptr<f32, Function>
-      // CHECK:       spv.selection {
-      // CHECK-NEXT:    spv.BranchConditional {{%.*}}, [[TRUE:\^.*]], [[FALSE:\^.*]]
-      // CHECK-NEXT:  [[TRUE]]:
-      // CHECK:         %[[RET1TRUE:.*]] = spv.constant 0.000000e+00 : f32
-      // CHECK:         %[[RET2TRUE:.*]] = spv.constant 1.000000e+00 : f32
-      // CHECK-DAG:     spv.Store "Function" %[[VAR1]], %[[RET1TRUE]] : f32
-      // CHECK-DAG:     spv.Store "Function" %[[VAR2]], %[[RET2TRUE]] : f32
-      // CHECK:         spv.Branch ^[[MERGE:.*]]
-      // CHECK-NEXT:  [[FALSE]]:
-      // CHECK:         %[[RET2FALSE:.*]] = spv.constant 2.000000e+00 : f32
-      // CHECK:         %[[RET1FALSE:.*]] = spv.constant 3.000000e+00 : f32
-      // CHECK-DAG:     spv.Store "Function" %[[VAR1]], %[[RET1FALSE]] : f32
-      // CHECK-DAG:     spv.Store "Function" %[[VAR2]], %[[RET2FALSE]] : f32
-      // CHECK:         spv.Branch ^[[MERGE]]
-      // CHECK-NEXT:  ^[[MERGE]]:
-      // CHECK:         spv.mlir.merge
-      // CHECK-NEXT:  }
-      // CHECK-DAG:   %[[OUT1:.*]] = spv.Load "Function" %[[VAR1]] : f32
-      // CHECK-DAG:   %[[OUT2:.*]] = spv.Load "Function" %[[VAR2]] : f32
-      // CHECK:       spv.Store "StorageBuffer" {{%.*}}, %[[OUT1]] : f32
-      // CHECK:       spv.Store "StorageBuffer" {{%.*}}, %[[OUT2]] : f32
-      // CHECK:       spv.Return
-      %0:2 = scf.if %arg3 -> (f32, f32) {
-        %c0 = constant 0.0 : f32
-        %c1 = constant 1.0 : f32
-        scf.yield %c0, %c1 : f32, f32
-      } else {
-        %c0 = constant 2.0 : f32
-        %c1 = constant 3.0 : f32
-        scf.yield %c1, %c0 : f32, f32
-      }
-      %i = constant 0 : index
-      %j = constant 1 : index
-      store %0#0, %arg2[%i] : memref<10xf32>
-      store %0#1, %arg2[%j] : memref<10xf32>
-      gpu.return
-    }
-    // TODO: The transformation should only be legal if
-    // VariablePointer capability is supported. This test is still useful to
-    // make sure we can handle scf op result with type change.
-    // CHECK-LABEL: @simple_if_yield_type_change
-    // CHECK:       %[[VAR:.*]] = spv.Variable : !spv.ptr<!spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>, Function>
-    // CHECK:       spv.selection {
-    // CHECK-NEXT:    spv.BranchConditional {{%.*}}, [[TRUE:\^.*]], [[FALSE:\^.*]]
-    // CHECK-NEXT:  [[TRUE]]:
-    // CHECK:         spv.Store "Function" %[[VAR]], {{%.*}} : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>
-    // CHECK:         spv.Branch ^[[MERGE:.*]]
-    // CHECK-NEXT:  [[FALSE]]:
-    // CHECK:         spv.Store "Function" %[[VAR]], {{%.*}} : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>
-    // CHECK:         spv.Branch ^[[MERGE]]
-    // CHECK-NEXT:  ^[[MERGE]]:
-    // CHECK:         spv.mlir.merge
-    // CHECK-NEXT:  }
-    // CHECK:       %[[OUT:.*]] = spv.Load "Function" %[[VAR]] : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>
-    // CHECK:       %[[ADD:.*]] = spv.AccessChain %[[OUT]][{{%.*}}, {{%.*}}] : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>
-    // CHECK:       spv.Store "StorageBuffer" %[[ADD]], {{%.*}} : f32
-    // CHECK:       spv.Return
-    gpu.func @simple_if_yield_type_change(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>, %arg4 : i1) kernel
-    attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} {
-      %i = constant 0 : index
-      %value = constant 0.0 : f32
-      %0 = scf.if %arg4 -> (memref<10xf32>) {
-        scf.yield %arg2 : memref<10xf32>
-      } else {
-        scf.yield %arg3 : memref<10xf32>
-      }
-      store %value, %0[%i] : memref<10xf32>
-      gpu.return
-    }
-  }
-}
diff --git a/mlir/test/Conversion/GPUToSPIRV/loop.mlir b/mlir/test/Conversion/GPUToSPIRV/loop.mlir
deleted file mode 100644
index 812007c1fd64d..0000000000000
--- a/mlir/test/Conversion/GPUToSPIRV/loop.mlir
+++ /dev/null
@@ -1,98 +0,0 @@
-// RUN: mlir-opt -convert-gpu-to-spirv %s -o - | FileCheck %s
-
-module attributes {
-  gpu.container_module,
-  spv.target_env = #spv.target_env<
-    #spv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, {}>
-} {
-  func @loop(%arg0 : memref<10xf32>, %arg1 : memref<10xf32>) {
-    %c0 = constant 1 : index
-    gpu.launch_func @kernels::@loop_kernel
-        blocks in (%c0, %c0, %c0) threads in (%c0, %c0, %c0)
-        args(%arg0 : memref<10xf32>, %arg1 : memref<10xf32>)
-    return
-  }
-
-  gpu.module @kernels {
-    gpu.func @loop_kernel(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>) kernel
-    attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} {
-      // CHECK: %[[LB:.*]] = spv.constant 4 : i32
-      %lb = constant 4 : index
-      // CHECK: %[[UB:.*]] = spv.constant 42 : i32
-      %ub = constant 42 : index
-      // CHECK: %[[STEP:.*]] = spv.constant 2 : i32
-      %step = constant 2 : index
-      // CHECK:      spv.loop {
-      // CHECK-NEXT:   spv.Branch ^[[HEADER:.*]](%[[LB]] : i32)
-      // CHECK:      ^[[HEADER]](%[[INDVAR:.*]]: i32):
-      // CHECK:        %[[CMP:.*]] = spv.SLessThan %[[INDVAR]], %[[UB]] : i32
-      // CHECK:        spv.BranchConditional %[[CMP]], ^[[BODY:.*]], ^[[MERGE:.*]]
-      // CHECK:      ^[[BODY]]:
-      // CHECK:        %[[ZERO1:.*]] = spv.constant 0 : i32
-      // CHECK:        %[[OFFSET1:.*]] = spv.constant 0 : i32
-      // CHECK:        %[[STRIDE1:.*]] = spv.constant 1 : i32
-      // CHECK:        %[[UPDATE1:.*]] = spv.IMul %[[STRIDE1]], %[[INDVAR]] : i32
-      // CHECK:        %[[INDEX1:.*]] = spv.IAdd %[[OFFSET1]], %[[UPDATE1]] : i32
-      // CHECK:        spv.AccessChain {{%.*}}{{\[}}%[[ZERO1]], %[[INDEX1]]{{\]}}
-      // CHECK:        %[[ZERO2:.*]] = spv.constant 0 : i32
-      // CHECK:        %[[OFFSET2:.*]] = spv.constant 0 : i32
-      // CHECK:        %[[STRIDE2:.*]] = spv.constant 1 : i32
-      // CHECK:        %[[UPDATE2:.*]] = spv.IMul %[[STRIDE2]], %[[INDVAR]] : i32
-      // CHECK:        %[[INDEX2:.*]] = spv.IAdd %[[OFFSET2]], %[[UPDATE2]] : i32
-      // CHECK:        spv.AccessChain {{%.*}}[%[[ZERO2]], %[[INDEX2]]]
-      // CHECK:        %[[INCREMENT:.*]] = spv.IAdd %[[INDVAR]], %[[STEP]] : i32
-      // CHECK:        spv.Branch ^[[HEADER]](%[[INCREMENT]] : i32)
-      // CHECK:      ^[[MERGE]]
-      // CHECK:        spv.mlir.merge
-      // CHECK:      }
-      scf.for %arg4 = %lb to %ub step %step {
-        %1 = load %arg2[%arg4] : memref<10xf32>
-        store %1, %arg3[%arg4] : memref<10xf32>
-      }
-      gpu.return
-    }
-
-
-    // CHECK-LABEL: @loop_yield
-    gpu.func @loop_yield(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>) kernel
-    attributes {spv.entry_point_abi = {local_size = dense<[16, 1, 1]>: vector<3xi32>}} {
-      // CHECK: %[[LB:.*]] = spv.constant 4 : i32
-      %lb = constant 4 : index
-      // CHECK: %[[UB:.*]] = spv.constant 42 : i32
-      %ub = constant 42 : index
-      // CHECK: %[[STEP:.*]] = spv.constant 2 : i32
-      %step = constant 2 : index
-      // CHECK: %[[INITVAR1:.*]] = spv.constant 0.000000e+00 : f32
-      %s0 = constant 0.0 : f32
-      // CHECK: %[[INITVAR2:.*]] = spv.constant 1.000000e+00 : f32
-      %s1 = constant 1.0 : f32
-      // CHECK: %[[VAR1:.*]] = spv.Variable : !spv.ptr<f32, Function>
-      // CHECK: %[[VAR2:.*]] = spv.Variable : !spv.ptr<f32, Function>
-      // CHECK: spv.loop {
-      // CHECK:   spv.Branch ^[[HEADER:.*]](%[[LB]], %[[INITVAR1]], %[[INITVAR2]] : i32, f32, f32)
-      // CHECK: ^[[HEADER]](%[[INDVAR:.*]]: i32, %[[CARRIED1:.*]]: f32, %[[CARRIED2:.*]]: f32):
-      // CHECK:   %[[CMP:.*]] = spv.SLessThan %[[INDVAR]], %[[UB]] : i32
-      // CHECK:   spv.BranchConditional %[[CMP]], ^[[BODY:.*]], ^[[MERGE:.*]]
-      // CHECK: ^[[BODY]]:
-      // CHECK:   %[[UPDATED:.*]] = spv.FAdd %[[CARRIED1]], %[[CARRIED1]] : f32
-      // CHECK-DAG:   %[[INCREMENT:.*]] = spv.IAdd %[[INDVAR]], %[[STEP]] : i32
-      // CHECK-DAG:   spv.Store "Function" %[[VAR1]], %[[UPDATED]] : f32
-      // CHECK-DAG:   spv.Store "Function" %[[VAR2]], %[[UPDATED]] : f32
-      // CHECK: spv.Branch ^[[HEADER]](%[[INCREMENT]], %[[UPDATED]], %[[UPDATED]] : i32, f32, f32)
-      // CHECK: ^[[MERGE]]:
-      // CHECK:   spv.mlir.merge
-      // CHECK: }
-      %result:2 = scf.for %i0 = %lb to %ub step %step iter_args(%si = %s0, %sj = %s1) -> (f32, f32) {
-        %sn = addf %si, %si : f32
-        scf.yield %sn, %sn : f32, f32
-      }
-      // CHECK-DAG: %[[OUT1:.*]] = spv.Load "Function" %[[VAR1]] : f32
-      // CHECK-DAG: %[[OUT2:.*]] = spv.Load "Function" %[[VAR2]] : f32
-      // CHECK: spv.Store "StorageBuffer" {{%.*}}, %[[OUT1]] : f32
-      // CHECK: spv.Store "StorageBuffer" {{%.*}}, %[[OUT2]] : f32
-      store %result#0, %arg3[%lb] : memref<10xf32>
-      store %result#1, %arg3[%ub] : memref<10xf32>
-      gpu.return
-    }
-  }
-}
diff --git a/mlir/test/Conversion/SCFToSPIRV/for.mlir b/mlir/test/Conversion/SCFToSPIRV/for.mlir
new file mode 100644
index 0000000000000..3e4545b1b1b50
--- /dev/null
+++ b/mlir/test/Conversion/SCFToSPIRV/for.mlir
@@ -0,0 +1,86 @@
+// RUN: mlir-opt -convert-scf-to-spirv %s -o - | FileCheck %s
+
+module attributes {
+  spv.target_env = #spv.target_env<
+    #spv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, {}>
+} {
+
+func @loop_kernel(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>) {
+  // CHECK: %[[LB:.*]] = spv.constant 4 : i32
+  %lb = constant 4 : index
+  // CHECK: %[[UB:.*]] = spv.constant 42 : i32
+  %ub = constant 42 : index
+  // CHECK: %[[STEP:.*]] = spv.constant 2 : i32
+  %step = constant 2 : index
+  // CHECK:      spv.loop {
+  // CHECK-NEXT:   spv.Branch ^[[HEADER:.*]](%[[LB]] : i32)
+  // CHECK:      ^[[HEADER]](%[[INDVAR:.*]]: i32):
+  // CHECK:        %[[CMP:.*]] = spv.SLessThan %[[INDVAR]], %[[UB]] : i32
+  // CHECK:        spv.BranchConditional %[[CMP]], ^[[BODY:.*]], ^[[MERGE:.*]]
+  // CHECK:      ^[[BODY]]:
+  // CHECK:        %[[ZERO1:.*]] = spv.constant 0 : i32
+  // CHECK:        %[[OFFSET1:.*]] = spv.constant 0 : i32
+  // CHECK:        %[[STRIDE1:.*]] = spv.constant 1 : i32
+  // CHECK:        %[[UPDATE1:.*]] = spv.IMul %[[STRIDE1]], %[[INDVAR]] : i32
+  // CHECK:        %[[INDEX1:.*]] = spv.IAdd %[[OFFSET1]], %[[UPDATE1]] : i32
+  // CHECK:        spv.AccessChain {{%.*}}{{\[}}%[[ZERO1]], %[[INDEX1]]{{\]}}
+  // CHECK:        %[[ZERO2:.*]] = spv.constant 0 : i32
+  // CHECK:        %[[OFFSET2:.*]] = spv.constant 0 : i32
+  // CHECK:        %[[STRIDE2:.*]] = spv.constant 1 : i32
+  // CHECK:        %[[UPDATE2:.*]] = spv.IMul %[[STRIDE2]], %[[INDVAR]] : i32
+  // CHECK:        %[[INDEX2:.*]] = spv.IAdd %[[OFFSET2]], %[[UPDATE2]] : i32
+  // CHECK:        spv.AccessChain {{%.*}}[%[[ZERO2]], %[[INDEX2]]]
+  // CHECK:        %[[INCREMENT:.*]] = spv.IAdd %[[INDVAR]], %[[STEP]] : i32
+  // CHECK:        spv.Branch ^[[HEADER]](%[[INCREMENT]] : i32)
+  // CHECK:      ^[[MERGE]]
+  // CHECK:        spv.mlir.merge
+  // CHECK:      }
+  scf.for %arg4 = %lb to %ub step %step {
+    %1 = load %arg2[%arg4] : memref<10xf32>
+    store %1, %arg3[%arg4] : memref<10xf32>
+  }
+  return
+}
+
+// CHECK-LABEL: @loop_yield
+func @loop_yield(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>) {
+  // CHECK: %[[LB:.*]] = spv.constant 4 : i32
+  %lb = constant 4 : index
+  // CHECK: %[[UB:.*]] = spv.constant 42 : i32
+  %ub = constant 42 : index
+  // CHECK: %[[STEP:.*]] = spv.constant 2 : i32
+  %step = constant 2 : index
+  // CHECK: %[[INITVAR1:.*]] = spv.constant 0.000000e+00 : f32
+  %s0 = constant 0.0 : f32
+  // CHECK: %[[INITVAR2:.*]] = spv.constant 1.000000e+00 : f32
+  %s1 = constant 1.0 : f32
+  // CHECK: %[[VAR1:.*]] = spv.Variable : !spv.ptr<f32, Function>
+  // CHECK: %[[VAR2:.*]] = spv.Variable : !spv.ptr<f32, Function>
+  // CHECK: spv.loop {
+  // CHECK:   spv.Branch ^[[HEADER:.*]](%[[LB]], %[[INITVAR1]], %[[INITVAR2]] : i32, f32, f32)
+  // CHECK: ^[[HEADER]](%[[INDVAR:.*]]: i32, %[[CARRIED1:.*]]: f32, %[[CARRIED2:.*]]: f32):
+  // CHECK:   %[[CMP:.*]] = spv.SLessThan %[[INDVAR]], %[[UB]] : i32
+  // CHECK:   spv.BranchConditional %[[CMP]], ^[[BODY:.*]], ^[[MERGE:.*]]
+  // CHECK: ^[[BODY]]:
+  // CHECK:   %[[UPDATED:.*]] = spv.FAdd %[[CARRIED1]], %[[CARRIED1]] : f32
+  // CHECK-DAG:   %[[INCREMENT:.*]] = spv.IAdd %[[INDVAR]], %[[STEP]] : i32
+  // CHECK-DAG:   spv.Store "Function" %[[VAR1]], %[[UPDATED]] : f32
+  // CHECK-DAG:   spv.Store "Function" %[[VAR2]], %[[UPDATED]] : f32
+  // CHECK: spv.Branch ^[[HEADER]](%[[INCREMENT]], %[[UPDATED]], %[[UPDATED]] : i32, f32, f32)
+  // CHECK: ^[[MERGE]]:
+  // CHECK:   spv.mlir.merge
+  // CHECK: }
+  %result:2 = scf.for %i0 = %lb to %ub step %step iter_args(%si = %s0, %sj = %s1) -> (f32, f32) {
+    %sn = addf %si, %si : f32
+    scf.yield %sn, %sn : f32, f32
+  }
+  // CHECK-DAG: %[[OUT1:.*]] = spv.Load "Function" %[[VAR1]] : f32
+  // CHECK-DAG: %[[OUT2:.*]] = spv.Load "Function" %[[VAR2]] : f32
+  // CHECK: spv.Store "StorageBuffer" {{%.*}}, %[[OUT1]] : f32
+  // CHECK: spv.Store "StorageBuffer" {{%.*}}, %[[OUT2]] : f32
+  store %result#0, %arg3[%lb] : memref<10xf32>
+  store %result#1, %arg3[%ub] : memref<10xf32>
+  return
+}
+
+} // end module
diff --git a/mlir/test/Conversion/SCFToSPIRV/if.mlir b/mlir/test/Conversion/SCFToSPIRV/if.mlir
new file mode 100644
index 0000000000000..d7c048f517abd
--- /dev/null
+++ b/mlir/test/Conversion/SCFToSPIRV/if.mlir
@@ -0,0 +1,156 @@
+// RUN: mlir-opt -convert-scf-to-spirv %s -o - | FileCheck %s
+
+module attributes {
+  spv.target_env = #spv.target_env<
+    #spv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, {}>
+} {
+
+// CHECK-LABEL: @kernel_simple_selection
+func @kernel_simple_selection(%arg2 : memref<10xf32>, %arg3 : i1) {
+  %value = constant 0.0 : f32
+  %i = constant 0 : index
+
+  // CHECK:       spv.selection {
+  // CHECK-NEXT:    spv.BranchConditional {{%.*}}, [[TRUE:\^.*]], [[MERGE:\^.*]]
+  // CHECK-NEXT:  [[TRUE]]:
+  // CHECK:         spv.Branch [[MERGE]]
+  // CHECK-NEXT:  [[MERGE]]:
+  // CHECK-NEXT:    spv.mlir.merge
+  // CHECK-NEXT:  }
+  // CHECK-NEXT:  spv.Return
+
+  scf.if %arg3 {
+    store %value, %arg2[%i] : memref<10xf32>
+  }
+  return
+}
+
+// CHECK-LABEL: @kernel_nested_selection
+func @kernel_nested_selection(%arg3 : memref<10xf32>, %arg4 : memref<10xf32>, %arg5 : i1, %arg6 : i1) {
+  %i = constant 0 : index
+  %j = constant 9 : index
+
+  // CHECK:       spv.selection {
+  // CHECK-NEXT:    spv.BranchConditional {{%.*}}, [[TRUE_TOP:\^.*]], [[FALSE_TOP:\^.*]]
+  // CHECK-NEXT:  [[TRUE_TOP]]:
+  // CHECK-NEXT:    spv.selection {
+  // CHECK-NEXT:      spv.BranchConditional {{%.*}}, [[TRUE_NESTED_TRUE_PATH:\^.*]], [[FALSE_NESTED_TRUE_PATH:\^.*]]
+  // CHECK-NEXT:    [[TRUE_NESTED_TRUE_PATH]]:
+  // CHECK:           spv.Branch [[MERGE_NESTED_TRUE_PATH:\^.*]]
+  // CHECK-NEXT:    [[FALSE_NESTED_TRUE_PATH]]:
+  // CHECK:           spv.Branch [[MERGE_NESTED_TRUE_PATH]]
+  // CHECK-NEXT:    [[MERGE_NESTED_TRUE_PATH]]:
+  // CHECK-NEXT:      spv.mlir.merge
+  // CHECK-NEXT:    }
+  // CHECK-NEXT:    spv.Branch [[MERGE_TOP:\^.*]]
+  // CHECK-NEXT:  [[FALSE_TOP]]:
+  // CHECK-NEXT:    spv.selection {
+  // CHECK-NEXT:      spv.BranchConditional {{%.*}}, [[TRUE_NESTED_FALSE_PATH:\^.*]], [[FALSE_NESTED_FALSE_PATH:\^.*]]
+  // CHECK-NEXT:    [[TRUE_NESTED_FALSE_PATH]]:
+  // CHECK:           spv.Branch [[MERGE_NESTED_FALSE_PATH:\^.*]]
+  // CHECK-NEXT:    [[FALSE_NESTED_FALSE_PATH]]:
+  // CHECK:           spv.Branch [[MERGE_NESTED_FALSE_PATH]]
+  // CHECK:         [[MERGE_NESTED_FALSE_PATH]]:
+  // CHECK-NEXT:      spv.mlir.merge
+  // CHECK-NEXT:    }
+  // CHECK-NEXT:    spv.Branch [[MERGE_TOP]]
+  // CHECK-NEXT:  [[MERGE_TOP]]:
+  // CHECK-NEXT:    spv.mlir.merge
+  // CHECK-NEXT:  }
+  // CHECK-NEXT:  spv.Return
+
+  scf.if %arg5 {
+    scf.if %arg6 {
+      %value = load %arg3[%i] : memref<10xf32>
+      store %value, %arg4[%i] : memref<10xf32>
+    } else {
+      %value = load %arg4[%i] : memref<10xf32>
+      store %value, %arg3[%i] : memref<10xf32>
+    }
+  } else {
+    scf.if %arg6 {
+      %value = load %arg3[%j] : memref<10xf32>
+      store %value, %arg4[%j] : memref<10xf32>
+    } else {
+      %value = load %arg4[%j] : memref<10xf32>
+      store %value, %arg3[%j] : memref<10xf32>
+    }
+  }
+  return
+}
+
+// CHECK-LABEL: @simple_if_yield
+func @simple_if_yield(%arg2 : memref<10xf32>, %arg3 : i1) {
+  // CHECK: %[[VAR1:.*]] = spv.Variable : !spv.ptr<f32, Function>
+  // CHECK: %[[VAR2:.*]] = spv.Variable : !spv.ptr<f32, Function>
+  // CHECK:       spv.selection {
+  // CHECK-NEXT:    spv.BranchConditional {{%.*}}, [[TRUE:\^.*]], [[FALSE:\^.*]]
+  // CHECK-NEXT:  [[TRUE]]:
+  // CHECK:         %[[RET1TRUE:.*]] = spv.constant 0.000000e+00 : f32
+  // CHECK:         %[[RET2TRUE:.*]] = spv.constant 1.000000e+00 : f32
+  // CHECK-DAG:     spv.Store "Function" %[[VAR1]], %[[RET1TRUE]] : f32
+  // CHECK-DAG:     spv.Store "Function" %[[VAR2]], %[[RET2TRUE]] : f32
+  // CHECK:         spv.Branch ^[[MERGE:.*]]
+  // CHECK-NEXT:  [[FALSE]]:
+  // CHECK:         %[[RET2FALSE:.*]] = spv.constant 2.000000e+00 : f32
+  // CHECK:         %[[RET1FALSE:.*]] = spv.constant 3.000000e+00 : f32
+  // CHECK-DAG:     spv.Store "Function" %[[VAR1]], %[[RET1FALSE]] : f32
+  // CHECK-DAG:     spv.Store "Function" %[[VAR2]], %[[RET2FALSE]] : f32
+  // CHECK:         spv.Branch ^[[MERGE]]
+  // CHECK-NEXT:  ^[[MERGE]]:
+  // CHECK:         spv.mlir.merge
+  // CHECK-NEXT:  }
+  // CHECK-DAG:   %[[OUT1:.*]] = spv.Load "Function" %[[VAR1]] : f32
+  // CHECK-DAG:   %[[OUT2:.*]] = spv.Load "Function" %[[VAR2]] : f32
+  // CHECK:       spv.Store "StorageBuffer" {{%.*}}, %[[OUT1]] : f32
+  // CHECK:       spv.Store "StorageBuffer" {{%.*}}, %[[OUT2]] : f32
+  // CHECK:       spv.Return
+  %0:2 = scf.if %arg3 -> (f32, f32) {
+    %c0 = constant 0.0 : f32
+    %c1 = constant 1.0 : f32
+    scf.yield %c0, %c1 : f32, f32
+  } else {
+    %c0 = constant 2.0 : f32
+    %c1 = constant 3.0 : f32
+    scf.yield %c1, %c0 : f32, f32
+  }
+  %i = constant 0 : index
+  %j = constant 1 : index
+  store %0#0, %arg2[%i] : memref<10xf32>
+  store %0#1, %arg2[%j] : memref<10xf32>
+  return
+}
+
+// TODO: The transformation should only be legal if VariablePointer capability
+// is supported. This test is still useful to make sure we can handle scf op
+// result with type change.
+func @simple_if_yield_type_change(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>, %arg4 : i1) {
+  // CHECK-LABEL: @simple_if_yield_type_change
+  // CHECK:       %[[VAR:.*]] = spv.Variable : !spv.ptr<!spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>, Function>
+  // CHECK:       spv.selection {
+  // CHECK-NEXT:    spv.BranchConditional {{%.*}}, [[TRUE:\^.*]], [[FALSE:\^.*]]
+  // CHECK-NEXT:  [[TRUE]]:
+  // CHECK:         spv.Store "Function" %[[VAR]], {{%.*}} : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>
+  // CHECK:         spv.Branch ^[[MERGE:.*]]
+  // CHECK-NEXT:  [[FALSE]]:
+  // CHECK:         spv.Store "Function" %[[VAR]], {{%.*}} : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>
+  // CHECK:         spv.Branch ^[[MERGE]]
+  // CHECK-NEXT:  ^[[MERGE]]:
+  // CHECK:         spv.mlir.merge
+  // CHECK-NEXT:  }
+  // CHECK:       %[[OUT:.*]] = spv.Load "Function" %[[VAR]] : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>
+  // CHECK:       %[[ADD:.*]] = spv.AccessChain %[[OUT]][{{%.*}}, {{%.*}}] : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>
+  // CHECK:       spv.Store "StorageBuffer" %[[ADD]], {{%.*}} : f32
+  // CHECK:       spv.Return
+  %i = constant 0 : index
+  %value = constant 0.0 : f32
+  %0 = scf.if %arg4 -> (memref<10xf32>) {
+    scf.yield %arg2 : memref<10xf32>
+  } else {
+    scf.yield %arg3 : memref<10xf32>
+  }
+  store %value, %0[%i] : memref<10xf32>
+  return
+}
+
+} // end module
diff --git a/mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir b/mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
index 10e43ef4acd78..850e22465d445 100644
--- a/mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
+++ b/mlir/test/Conversion/StandardToSPIRV/std-ops-to-spirv.mlir
@@ -954,3 +954,29 @@ func @store_i16(%arg0: memref<10xi16>, %index: index, %value: i16) {
 }
 
 } // end module
+
+// -----
+
+//===----------------------------------------------------------------------===//
+// std.return
+//===----------------------------------------------------------------------===//
+
+module attributes {
+  spv.target_env = #spv.target_env<#spv.vce<v1.0, [], []>, {}>
+} {
+
+// CHECK-LABEL: spv.func @return_one_val
+//  CHECK-SAME: (%[[ARG:.+]]: f32)
+func @return_one_val(%arg0: f32) -> f32 {
+  // CHECK: spv.ReturnValue %[[ARG]] : f32
+  return %arg0: f32
+}
+
+// Check that multiple-return functions are not converted.
+// CHECK-LABEL: func @return_multi_val
+func @return_multi_val(%arg0: f32) -> (f32, f32) {
+  // CHECK: return
+  return %arg0, %arg0: f32, f32
+}
+
+}
diff --git a/mlir/test/Dialect/GPU/invalid.mlir b/mlir/test/Dialect/GPU/invalid.mlir
index 3dc5be405aac1..1f6058cde3974 100644
--- a/mlir/test/Dialect/GPU/invalid.mlir
+++ b/mlir/test/Dialect/GPU/invalid.mlir
@@ -444,3 +444,17 @@ func @async_wait_without_result() {
   // expected-error @+1 {{custom op 'gpu.wait' needs to be named when marked 'async'}}
   gpu.wait async
 }
+
+// -----
+
+func @memcpy_incompatible_type(%dst : memref<?xf32>, %src : memref<?xi32>) {
+  // expected-error @+1 {{'gpu.memcpy' op arguments have incompatible element type}}
+  gpu.memcpy %dst, %src  : memref<?xf32>, memref<?xi32>
+}
+
+// -----
+
+func @memcpy_incompatible_shape(%dst : memref<7xf32>, %src : memref<9xf32>) {
+  // expected-error @+1 {{'gpu.memcpy' op arguments have incompatible shape}}
+  gpu.memcpy %dst, %src  : memref<7xf32>, memref<9xf32>
+}
diff --git a/mlir/test/Dialect/GPU/ops.mlir b/mlir/test/Dialect/GPU/ops.mlir
index aed4368c22a71..5cea772ce5991 100644
--- a/mlir/test/Dialect/GPU/ops.mlir
+++ b/mlir/test/Dialect/GPU/ops.mlir
@@ -183,4 +183,15 @@ module attributes {gpu.container_module} {
     gpu.wait // Valid, but a no-op.
     return
   }
+
+  func @memcpy(%dst : memref<3x7xf32>, %src : memref<3x7xf32, 1>) {
+    // CHECK-LABEL: func @memcpy
+    // CHECK: gpu.memcpy {{.*}}, {{.*}} : memref<3x7xf32>, memref<3x7xf32, 1>
+    gpu.memcpy %dst, %src : memref<3x7xf32>, memref<3x7xf32, 1>
+    // CHECK: %[[t0:.*]] = gpu.wait async
+    %0 = gpu.wait async
+    // CHECK: {{.*}} = gpu.memcpy async [%[[t0]]] {{.*}}, {{.*}} : memref<3x7xf32>, memref<3x7xf32, 1>
+    %1 = gpu.memcpy async [%0] %dst, %src : memref<3x7xf32>, memref<3x7xf32, 1>
+    return
+  }
 }
diff --git a/mlir/test/Dialect/LLVMIR/invalid.mlir b/mlir/test/Dialect/LLVMIR/invalid.mlir
index 9461ebbd9ede9..d02c252c0bf36 100644
--- a/mlir/test/Dialect/LLVMIR/invalid.mlir
+++ b/mlir/test/Dialect/LLVMIR/invalid.mlir
@@ -98,7 +98,7 @@ func @gep_non_function_type(%pos : !llvm.i64, %base : !llvm.ptr<float>) {
 // -----
 
 func @load_non_llvm_type(%foo : memref<f32>) {
-  // expected-error@+1 {{expected LLVM IR dialect type}}
+  // expected-error@+1 {{expected LLVM pointer type}}
   llvm.load %foo : memref<f32>
 }
 
@@ -112,7 +112,7 @@ func @load_non_ptr_type(%foo : !llvm.float) {
 // -----
 
 func @store_non_llvm_type(%foo : memref<f32>, %bar : !llvm.float) {
-  // expected-error@+1 {{expected LLVM IR dialect type}}
+  // expected-error@+1 {{expected LLVM pointer type}}
   llvm.store %bar, %foo : memref<f32>
 }
 
@@ -267,7 +267,7 @@ func @insertvalue_array_out_of_bounds() {
 // -----
 
 func @insertvalue_wrong_nesting() {
-  // expected-error@+1 {{expected wrapped LLVM IR structure/array type}}
+  // expected-error@+1 {{expected LLVM IR structure/array type}}
   llvm.insertvalue %a, %b[0,0] : !llvm.struct<(i32)>
 }
 
@@ -311,7 +311,7 @@ func @extractvalue_array_out_of_bounds() {
 // -----
 
 func @extractvalue_wrong_nesting() {
-  // expected-error@+1 {{expected wrapped LLVM IR structure/array type}}
+  // expected-error@+1 {{expected LLVM IR structure/array type}}
   llvm.extractvalue %b[0,0] : !llvm.struct<(i32)>
 }
 
diff --git a/mlir/test/Dialect/Linalg/bufferize.mlir b/mlir/test/Dialect/Linalg/bufferize.mlir
index 368568bdcc4a4..08d715f90b5e1 100644
--- a/mlir/test/Dialect/Linalg/bufferize.mlir
+++ b/mlir/test/Dialect/Linalg/bufferize.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt -linalg-bufferize -split-input-file %s | FileCheck %s
+// RUN: mlir-opt -linalg-bufferize  -canonicalize -cse -split-input-file %s | FileCheck %s
 
 #map0 = affine_map<(d0) -> (d0)>
 
@@ -26,8 +26,9 @@ func @basic(%arg0: tensor<4xf32>) -> tensor<4xf32> {
     %0 = linalg.generic {
       indexing_maps = [#map0, #map0],
       iterator_types = ["parallel"]
-    } ins(%arg0 : tensor<4xf32>) {
-      ^bb0(%gen_arg1: f32):
+    } ins(%arg0 : tensor<4xf32>)
+      outs(%arg0 : tensor<4xf32>) {
+      ^bb0(%gen_arg1: f32, %out: f32):
         %tmp1 = exp %gen_arg1 : f32
         linalg.yield %tmp1 : f32
     } -> tensor<4xf32>
@@ -35,6 +36,35 @@ func @basic(%arg0: tensor<4xf32>) -> tensor<4xf32> {
 }
 
 
+// -----
+
+#map0 = affine_map<(d0) -> (d0)>
+
+// Same as above but with linalg.init_tensor op.
+
+// CHECK: #map = affine_map<(d0) -> (d0)>
+// CHECK-LABEL: func @init_tensor(
+// CHECK-SAME:      %[[IN:.*]]: tensor<?xf32>, %[[SIZE:.*]]: index)
+// CHECK:         %[[OUT_BUF:.*]] = alloc(%[[SIZE]]) : memref<?xf32>
+// CHECK:         %[[MEMREF:.*]] = tensor_to_memref %[[IN]] : memref<?xf32>
+// CHECK:         linalg.generic
+// CHECK-SAME:    ins(%[[MEMREF]] : memref<?xf32>)
+// CHECK-SAME:    outs(%[[OUT_BUF]] : memref<?xf32>) {
+func @init_tensor(%in : tensor<?xf32>, %size: index) -> tensor<?xf32> {
+  %init = linalg.init_tensor [%size] : tensor<?xf32>
+  %0 = linalg.generic {
+    indexing_maps = [#map0, #map0],
+    iterator_types = ["parallel"]
+  } ins(%in : tensor<?xf32>)
+    outs(%init : tensor<?xf32>) {
+    ^bb0(%gen_arg1: f32, %out: f32):
+      %tmp1 = exp %gen_arg1 : f32
+      linalg.yield %tmp1 : f32
+  } -> tensor<?xf32>
+  return %0 : tensor<?xf32>
+}
+
+
 // -----
 
 #map0 = affine_map<(d0) -> (d0)>
@@ -50,8 +80,9 @@ func @multiple_results(%arg0: tensor<4xf32>) -> (tensor<4xf32>, tensor<4xf32>) {
     %0, %1 = linalg.generic {
       indexing_maps = [#map0, #map0, #map0],
       iterator_types = ["parallel"]
-    } ins(%arg0 : tensor<4xf32>) {
-      ^bb0(%gen_arg1: f32):
+    } ins(%arg0 : tensor<4xf32>)
+      outs (%arg0, %arg0 : tensor<4xf32>, tensor<4xf32>) {
+      ^bb0(%gen_arg1: f32, %out1: f32, %out2: f32):
         %tmp1 = exp %gen_arg1 : f32
         linalg.yield %tmp1, %tmp1 : f32, f32
     } -> tensor<4xf32>, tensor<4xf32>
@@ -74,8 +105,9 @@ func @multiple_results_indexed(%arg0: tensor<4xi32>)
     %0, %1 = linalg.indexed_generic {
       indexing_maps = [#map0, #map0, #map0],
       iterator_types = ["parallel"]
-    } ins(%arg0 : tensor<4xi32>) {
-      ^bb0(%i: index, %gen_arg1: i32):
+    } ins(%arg0 : tensor<4xi32>)
+      outs (%arg0, %arg0 : tensor<4xi32>, tensor<4xi32>) {
+      ^bb0(%i: index, %gen_arg1: i32, %out1: i32, %out2: i32):
         %i_i32 = index_cast %i : index to i32
         %tmp1 = addi %gen_arg1, %i_i32 : i32
         linalg.yield %tmp1, %tmp1 : i32, i32
@@ -86,32 +118,30 @@ func @multiple_results_indexed(%arg0: tensor<4xi32>)
 // -----
 
 #map_2d = affine_map<(d0, d1) -> (d0, d1)>
-#map_2d_inv = affine_map<(d0, d1) -> (d1, d0)>
 
 // Check that the allocs properly consider the different shapes of the output
 // operands. The permuted indexing maps translate to different output shapes.
 
-// CHECK: #map0 = affine_map<(d0, d1) -> (d0, d1)>
-// CHECK: #map1 = affine_map<(d0, d1) -> (d1, d0)>
 // CHECK-LABEL:   func @dynamic_results(
 // CHECK-SAME:                          %[[ARG:.*]]: tensor<?x?xf32>
-// CHECK:           %[[MEMREF_ARG:.*]] = tensor_to_memref %[[ARG]] : memref<?x?xf32>
 // CHECK:           %[[C0:.*]] = constant 0 : index
-// CHECK:           %[[DIM0:.*]] = dim %[[ARG]], %[[C0]] : tensor<?x?xf32>
 // CHECK:           %[[C1:.*]] = constant 1 : index
+// CHECK:           %[[MEMREF_ARG:.*]] = tensor_to_memref %[[ARG]] : memref<?x?xf32>
+// CHECK:           %[[DIM0:.*]] = dim %[[ARG]], %[[C0]] : tensor<?x?xf32>
 // CHECK:           %[[DIM1:.*]] = dim %[[ARG]], %[[C1]] : tensor<?x?xf32>
 // CHECK:           %[[RESULT0:.*]] = alloc(%[[DIM0]], %[[DIM1]]) : memref<?x?xf32>
-// CHECK:           %[[RESULT1:.*]] = alloc(%[[DIM1]], %[[DIM0]]) : memref<?x?xf32>
-// CHECK:           linalg.generic {indexing_maps = [#map0, #map0, #map1]
+// CHECK:           %[[RESULT1:.*]] = alloc(%[[DIM0]], %[[DIM1]]) : memref<?x?xf32>
+// CHECK:           linalg.generic
 // CHECK-SAME:      ins(%[[MEMREF_ARG]] : memref<?x?xf32>)
 // CHECK-SAME:      outs(%[[RESULT0]], %[[RESULT1]] : memref<?x?xf32>, memref<?x?xf32>)
 func @dynamic_results(%arg0: tensor<?x?xf32>)
          -> (tensor<?x?xf32>, tensor<?x?xf32>) {
     %0, %1 = linalg.generic {
-      indexing_maps = [#map_2d, #map_2d, #map_2d_inv],
+      indexing_maps = [#map_2d, #map_2d, #map_2d],
       iterator_types = ["parallel", "parallel"]
-    } ins(%arg0 : tensor<?x?xf32>) {
-      ^bb0(%gen_arg1: f32):
+    } ins(%arg0 : tensor<?x?xf32>)
+      outs (%arg0, %arg0 : tensor<?x?xf32>, tensor<?x?xf32>) {
+      ^bb0(%gen_arg1: f32, %out1: f32, %out2: f32):
         %tmp1 = exp %gen_arg1 : f32
         linalg.yield %tmp1, %tmp1 : f32, f32
     } -> tensor<?x?xf32>, tensor<?x?xf32>
@@ -147,10 +177,9 @@ func @generic_with_init_tensor(%arg0: tensor<2x3x4xvector<3x4xi4>>,
 
   %0 = linalg.generic #trait
     ins(%arg0 : tensor<2x3x4xvector<3x4xi4>>)
-   init(%arg1 : tensor<3x2xf32>) {
+   outs(%arg1 : tensor<3x2xf32>) {
     ^bb(%v0: vector<3x4xi4>, %v1: f32) :
-      %f0 = constant 0.0 : f32
-      linalg.yield %f0 : f32
+      linalg.yield %v1 : f32
   } -> tensor<3x2xf32>
 
   return %0 : tensor<3x2xf32>
@@ -204,16 +233,16 @@ func @bufferize_subtensor_insert(%t : tensor<?x?xf32>, %st0 : tensor<2x3xf32>, %
     (tensor<?x?xf32>, tensor<?x?xf32>) {
   %c0 = constant 0 : index
   %c1 = constant 1 : index
-  //      CHECK: %[[IDX:.*]] = call @make_index() : () -> index
+  // CHECK-NEXT: %[[C0:.*]] = constant 0 : index
+  // CHECK-NEXT: %[[C1:.*]] = constant 1 : index
   %i0 = call @make_index() : () -> index
+  // CHECK: %[[IDX:.*]] = call @make_index() : () -> index
 
 
-  //  CHECK-DAG: %[[M0:.*]] = tensor_to_memref %[[T]] : memref<?x?xf32>
-  //  CHECK-DAG: %[[SM0:.*]] = tensor_to_memref %[[ST0]] : memref<2x3xf32>
-  // CHECK-NEXT: %[[C0:.*]] = constant 0 : index
-  // CHECK-NEXT: %[[DIM0:.*]] = dim %[[M0]], %[[C0]] : memref<?x?xf32>
-  // CHECK-NEXT: %[[C1:.*]] = constant 1 : index
-  // CHECK-NEXT: %[[DIM1:.*]] = dim %[[M0]], %[[C1]] : memref<?x?xf32>
+  // CHECK-DAG: %[[M0:.*]] = tensor_to_memref %[[T]] : memref<?x?xf32>
+  // CHECK-DAG: %[[SM0:.*]] = tensor_to_memref %[[ST0]] : memref<2x3xf32>
+  // CHECK-NEXT: %[[DIM0:.*]] = dim %[[T]], %[[C0]] : tensor<?x?xf32>
+  // CHECK-NEXT: %[[DIM1:.*]] = dim %[[T]], %[[C1]] : tensor<?x?xf32>
   // CHECK-NEXT: %[[M0_COPY:.*]] = alloc(%[[DIM0]], %[[DIM1]]) : memref<?x?xf32>
   // CHECK-NEXT: linalg.copy(%[[M0]], %[[M0_COPY]]) : memref<?x?xf32>, memref<?x?xf32>
   // CHECK-NEXT: %[[SUBVIEW0:.*]] = subview %[[M0_COPY]][0, 0] [2, 3] [1, 1]
@@ -224,10 +253,6 @@ func @bufferize_subtensor_insert(%t : tensor<?x?xf32>, %st0 : tensor<2x3xf32>, %
 
   //  CHECK-DAG: %[[M1:.*]] = tensor_to_memref %[[T]] : memref<?x?xf32>
   //  CHECK-DAG: %[[SM1:.*]] = tensor_to_memref %[[ST1]] : memref<2x?xf32>
-  // CHECK-NEXT: %[[C0:.*]] = constant 0 : index
-  // CHECK-NEXT: %[[DIM0:.*]] = dim %[[M1]], %[[C0]] : memref<?x?xf32>
-  // CHECK-NEXT: %[[C1:.*]] = constant 1 : index
-  // CHECK-NEXT: %[[DIM1:.*]] = dim %[[M1]], %[[C1]] : memref<?x?xf32>
   // CHECK-NEXT: %[[M1_COPY:.*]] = alloc(%[[DIM0]], %[[DIM1]]) : memref<?x?xf32>
   // CHECK-NEXT: linalg.copy(%[[M1]], %[[M1_COPY]]) : memref<?x?xf32>, memref<?x?xf32>
   // CHECK-NEXT: %[[SUBVIEW1:.*]] = subview %[[M1_COPY]][0, %[[IDX]]] [2, %[[IDX]]] [1, 2]
@@ -239,3 +264,4 @@ func @bufferize_subtensor_insert(%t : tensor<?x?xf32>, %st0 : tensor<2x3xf32>, %
   //     CHECK: return %[[RT0]], %[[RT1]]
   return %t0, %t1: tensor<?x?xf32>, tensor<?x?xf32>
 }
+
diff --git a/mlir/test/Dialect/Linalg/canonicalize-duplicate-inputs.mlir b/mlir/test/Dialect/Linalg/canonicalize-duplicate-inputs.mlir
index 8c08fb390b9ee..de894b9192fb0 100644
--- a/mlir/test/Dialect/Linalg/canonicalize-duplicate-inputs.mlir
+++ b/mlir/test/Dialect/Linalg/canonicalize-duplicate-inputs.mlir
@@ -8,10 +8,12 @@
 // CHECK-LABEL: @basic
 func @basic(%arg0: tensor<?xf32>) -> tensor<?xf32> {
   // CHECK: linalg.generic{{.*}}[#[[$MAP]], #[[$MAP]]]
-  // CHECK:   ^bb0(%[[BBARG:.*]]: f32):
+  // CHECK:   ^bb0(%[[BBARG:.*]]: f32, %{{.*}}: f32):
   // CHECK:     addf %[[BBARG]], %[[BBARG]]
-  %0 = linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = ["parallel"]} ins(%arg0, %arg0 : tensor<?xf32>, tensor<?xf32>) {
-  ^bb0(%arg1: f32, %arg2: f32):
+  %0 = linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = ["parallel"]}
+     ins(%arg0, %arg0 : tensor<?xf32>, tensor<?xf32>)
+    outs(%arg0 : tensor<?xf32>) {
+  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
     %1 = addf %arg1, %arg2 : f32
     linalg.yield %1 : f32
   } -> tensor<?xf32>
@@ -31,8 +33,10 @@ func @basic(%arg0: tensor<?xf32>) -> tensor<?xf32> {
 // CHECK-LABEL: @distinct_affine_maps
 func @distinct_affine_maps(%arg0: tensor<?x?xf32>) -> tensor<?x?xf32> {
   // CHECK: linalg.generic{{.*}}[#[[$MAP0]], #[[$MAP1]], #[[$MAP0]]]
-  %0 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]} ins(%arg0, %arg0 : tensor<?x?xf32>, tensor<?x?xf32>) {
-  ^bb0(%arg1: f32, %arg2: f32):
+  %0 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]}
+     ins(%arg0, %arg0 : tensor<?x?xf32>, tensor<?x?xf32>)
+    outs(%arg0 : tensor<?x?xf32>) {
+  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
     %1 = addf %arg1, %arg2 : f32
     linalg.yield %1 : f32
   } -> tensor<?x?xf32>
@@ -52,10 +56,12 @@ func @distinct_affine_maps(%arg0: tensor<?x?xf32>) -> tensor<?x?xf32> {
 // CHECK-LABEL: @mixed_redundant_non_redundant
 func @mixed_redundant_non_redundant(%arg0: tensor<?x?xf32>) -> tensor<?x?xf32> {
   // CHECK: linalg.generic{{.*}}[#[[$MAP0]], #[[$MAP1]], #[[$MAP0]]]
-  // CHECK:   ^bb0(%[[BBARG0:.*]]: f32, %[[BBARG1:.*]]: f32):
+  // CHECK:   ^bb0(%[[BBARG0:.*]]: f32, %[[BBARG1:.*]]: f32, %{{[a-zA-Z0-9]+}}: f32):
   // CHECK:     "test.elementwise_mappable"(%[[BBARG0]], %[[BBARG1]], %[[BBARG0]])
-  %0 = linalg.generic {indexing_maps = [#map0, #map1, #map0, #map0], iterator_types = ["parallel", "parallel"]} ins(%arg0, %arg0, %arg0 : tensor<?x?xf32>, tensor<?x?xf32>, tensor<?x?xf32>) {
-  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
+  %0 = linalg.generic {indexing_maps = [#map0, #map1, #map0, #map0], iterator_types = ["parallel", "parallel"]}
+     ins(%arg0, %arg0, %arg0 : tensor<?x?xf32>, tensor<?x?xf32>, tensor<?x?xf32>)
+    outs(%arg0 : tensor<?x?xf32>) {
+  ^bb0(%arg1: f32, %arg2: f32, %arg3: f32, %arg4: f32):
     %1 = "test.elementwise_mappable"(%arg1, %arg2, %arg3) : (f32, f32, f32) -> f32
     linalg.yield %1 : f32
   } -> tensor<?x?xf32>
@@ -72,10 +78,12 @@ func @mixed_redundant_non_redundant(%arg0: tensor<?x?xf32>) -> tensor<?x?xf32> {
 // CHECK-LABEL: @multiple_different_redundant_args
 func @multiple_different_redundant_args(%arg0: tensor<?xf32>, %arg1: tensor<?xf32>) -> tensor<?xf32> {
   // CHECK: linalg.generic{{.*}}[#[[$MAP]], #[[$MAP]], #[[$MAP]]]
-  // CHECK:   ^bb0(%[[BBARG0:.*]]: f32, %[[BBARG1:.*]]: f32):
+  // CHECK:   ^bb0(%[[BBARG0:.*]]: f32, %[[BBARG1:.*]]: f32, %{{[a-zA-Z0-9]+}}: f32):
   // CHECK:     "test.elementwise_mappable"(%[[BBARG0]], %[[BBARG1]], %[[BBARG0]], %[[BBARG1]])
-  %0 = linalg.generic {indexing_maps = [#map, #map, #map, #map, #map], iterator_types = ["parallel"]} ins(%arg0, %arg1, %arg0, %arg1 : tensor<?xf32>, tensor<?xf32>, tensor<?xf32>, tensor<?xf32>) {
-  ^bb0(%arg2: f32, %arg3: f32, %arg4: f32, %arg5: f32): 
+  %0 = linalg.generic {indexing_maps = [#map, #map, #map, #map, #map], iterator_types = ["parallel"]}
+     ins(%arg0, %arg1, %arg0, %arg1 : tensor<?xf32>, tensor<?xf32>, tensor<?xf32>, tensor<?xf32>)
+    outs(%arg0 : tensor<?xf32>) {
+  ^bb0(%arg2: f32, %arg3: f32, %arg4: f32, %arg5: f32, %arg6: f32):
     %1 = "test.elementwise_mappable"(%arg2, %arg3, %arg4, %arg5) : (f32, f32, f32, f32) -> f32
     linalg.yield %1 : f32
   } -> tensor<?xf32>
@@ -93,10 +101,12 @@ func @multiple_different_redundant_args(%arg0: tensor<?xf32>, %arg1: tensor<?xf3
 // CHECK-LABEL: @indexed_generic
 func @indexed_generic(%arg0: tensor<?xf32>) -> tensor<?xf32> {
   // CHECK: linalg.indexed_generic
-  // CHECK:   ^bb0(%{{.*}}: index, %[[BBARG:.*]]: f32):
+  // CHECK:   ^bb0(%{{.*}}: index, %[[BBARG:.*]]: f32, %{{[a-zA-Z0-9]+}}: f32):
   // CHECK:     addf %[[BBARG]], %[[BBARG]]
-  %0 = linalg.indexed_generic {indexing_maps = [#map, #map, #map], iterator_types = ["parallel"]} ins(%arg0, %arg0 : tensor<?xf32>, tensor<?xf32>) {
-  ^bb0(%index: index, %arg1: f32, %arg2: f32):
+  %0 = linalg.indexed_generic {indexing_maps = [#map, #map, #map], iterator_types = ["parallel"]}
+      ins(%arg0, %arg0 : tensor<?xf32>, tensor<?xf32>)
+     outs(%arg0 : tensor<?xf32>) {
+  ^bb0(%index: index, %arg1: f32, %arg2: f32, %arg3: f32):
     %1 = addf %arg1, %arg2 : f32
     linalg.yield %1 : f32
   } -> tensor<?xf32>
diff --git a/mlir/test/Dialect/Linalg/canonicalize.mlir b/mlir/test/Dialect/Linalg/canonicalize.mlir
index 6c12070e07f18..f015d5fd64fd9 100644
--- a/mlir/test/Dialect/Linalg/canonicalize.mlir
+++ b/mlir/test/Dialect/Linalg/canonicalize.mlir
@@ -232,7 +232,6 @@ func @no_fold_memref_reshape(%arg0 : memref<?x?xf32>) -> memref<?x?xf32>
 // -----
 
 #accesses = [
-  affine_map<(i) -> (i)>,
   affine_map<(i) -> (i)>
 ]
 
@@ -246,7 +245,7 @@ func @dce_zero_memref(%arg0 : memref<0xf32>, %arg1: tensor<0xf32>) -> tensor<0xf
   linalg.copy(%arg0, %arg0): memref<0xf32>, memref<0xf32>
 
   // tensor<0xf32> cannot be dce'ed
-  %1 = linalg.generic #trait ins(%arg1 : tensor<0xf32>) {
+  %1 = linalg.generic #trait outs(%arg1 : tensor<0xf32>) {
   ^bb(%0: f32) :
     linalg.yield %0 : f32
   } -> tensor<0xf32>
@@ -326,9 +325,9 @@ func @tensor.cast(%a : tensor<3x4xf32>, %b : tensor<4x?xf32>, %c : tensor<3x?xf3
   %tc = tensor.cast %c : tensor<3x?xf32> to tensor<?x?xf32>
 
   //      CHECK:  linalg.matmul ins({{.*}}tensor<3x4xf32>, tensor<4x?xf32>)
-  // CHECK-SAME:    init({{.*}}tensor<3x?xf32>) -> tensor<3x?xf32>
+  // CHECK-SAME:    outs({{.*}}tensor<3x?xf32>) -> tensor<3x?xf32>
   %0 = linalg.matmul ins(%ta, %tb: tensor<?x?xf32>, tensor<?x?xf32>)
-               init(%tc: tensor<?x?xf32>) -> tensor<?x?xf32>
+                    outs(%tc: tensor<?x?xf32>) -> tensor<?x?xf32>
 
   %1 = tensor.cast %0 : tensor<?x?xf32> to tensor<3x?xf32>
 
@@ -344,7 +343,7 @@ func @tensor.cast(%a : tensor<3x4xf32>, %b : tensor<4x?xf32>, %c : tensor<3x?xf3
 func @linalg_effects(%a : tensor<?x?xf32>, %b : memref<?x?xf32>, %c : tensor<?x?xf32>) {
   // CHECK-NOT:   %{{.*}} = linalg.matmul
   %t = linalg.matmul ins(%a, %b : tensor<?x?xf32>, memref<?x?xf32>)
-                    init(%c : tensor<?x?xf32>) -> tensor<?x?xf32>
+                    outs(%c : tensor<?x?xf32>) -> tensor<?x?xf32>
 
   // CHECK-NOT:   %{{.*}} = linalg.matmul
   linalg.matmul ins(%a, %c : tensor<?x?xf32>, tensor<?x?xf32>)
diff --git a/mlir/test/Dialect/Linalg/convert-elementwise-to-linalg.mlir b/mlir/test/Dialect/Linalg/convert-elementwise-to-linalg.mlir
index 7ea78fef7addb..8dca137843bb0 100644
--- a/mlir/test/Dialect/Linalg/convert-elementwise-to-linalg.mlir
+++ b/mlir/test/Dialect/Linalg/convert-elementwise-to-linalg.mlir
@@ -1,14 +1,20 @@
 // RUN: mlir-opt -convert-elementwise-to-linalg -split-input-file %s | FileCheck %s
 
 // In-depth checking of the linalg.generic op for a very trivial case.
-// CHECK: #map = affine_map<() -> ()>
-// CHECK-LABEL:   func @addf_rank0
+// CHECK: #[[$MAP:.*]] = affine_map<() -> ()>
+// CHECK-LABEL: func @addf_rank0
+//  CHECK-SAME:   %[[ARG0:[0-9a-zA-Z]*]]: tensor<f32>
+//  CHECK-SAME:   %[[ARG1:[0-9a-zA-Z]*]]: tensor<f32>
 func @addf_rank0(%arg0: tensor<f32>, %arg1: tensor<f32>) -> tensor<f32> {
-  // CHECK: %{{.*}} = linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = []} ins(%{{.*}}, %{{.*}} : tensor<f32>, tensor<f32>) {
-  // CHECK: ^bb0(%[[LHS:.*]]: f32, %[[RHS:.*]]: f32):
-  // CHECK:   %[[YIELD:.*]] = addf %[[LHS]], %[[RHS]] : f32
-  // CHECK:   linalg.yield %[[YIELD]] : f32
-  // CHECK: } -> tensor<f32>
+  //      CHECK: %{{.*}} = linalg.generic
+  // CHECK-SAME: indexing_maps = [#[[$MAP]], #[[$MAP]], #[[$MAP]]]
+  // CHECK-SAME: iterator_types = []
+  // CHECK-SAME:  ins(%[[ARG0]], %[[ARG1]]
+  // CHECK-SAME: outs(%[[ARG0]]
+  //      CHECK: ^bb0(%[[LHS:.*]]: f32, %[[RHS:.*]]: f32, %{{.*}}: f32):
+  //      CHECK:   %[[YIELD:.*]] = addf %[[LHS]], %[[RHS]] : f32
+  //      CHECK:   linalg.yield %[[YIELD]] : f32
+  //      CHECK: } -> tensor<f32>
   %0 = addf %arg0, %arg1 : tensor<f32>
   return %0 : tensor<f32>
 }
@@ -16,10 +22,14 @@ func @addf_rank0(%arg0: tensor<f32>, %arg1: tensor<f32>) -> tensor<f32> {
 // -----
 
 // Check indexing maps and iterator types for the rank > 0 case.
-// CHECK: #map = affine_map<(d0) -> (d0)>
 // CHECK-LABEL: func @addf_rank1
+//  CHECK-SAME:   %[[ARG0:[0-9a-zA-Z]*]]: tensor<?xf32>
+//  CHECK-SAME:   %[[ARG1:[0-9a-zA-Z]*]]: tensor<?xf32>
 func @addf_rank1(%arg0: tensor<?xf32>, %arg1: tensor<?xf32>) -> tensor<?xf32> {
-  // CHECK: linalg.generic{{.*}}indexing_maps = [#map, #map, #map], iterator_types = ["parallel"]
+  // CHECK: linalg.generic
+  // CHECK-SAME: iterator_types = ["parallel"]
+  // CHECK-SAME:  ins(%[[ARG0]], %[[ARG1]]
+  // CHECK-SAME: outs(%[[ARG0]]
   %0 = addf %arg0, %arg1 : tensor<?xf32>
   return %0 : tensor<?xf32>
 }
@@ -28,9 +38,12 @@ func @addf_rank1(%arg0: tensor<?xf32>, %arg1: tensor<?xf32>) -> tensor<?xf32> {
 
 // Check a unary op.
 // CHECK-LABEL: func @exp
+//  CHECK-SAME:   %[[ARG0:[0-9a-zA-Z]*]]: tensor<f32>
 func @exp(%arg0: tensor<f32>) -> tensor<f32> {
   // CHECK: linalg.generic
-  // CHECK: ^bb0(%[[SCALAR:.*]]: f32):
+  // CHECK-SAME:  ins(%[[ARG0]]
+  // CHECK-SAME: outs(%[[ARG0]]
+  // CHECK: ^bb0(%[[SCALAR:.*]]: f32, %{{.*}}: f32):
   // CHECK:   %[[YIELD:.*]] = exp %[[SCALAR]] : f32
   // CHECK:   linalg.yield %[[YIELD]] : f32
   %0 = exp %arg0 : tensor<f32>
@@ -41,9 +54,14 @@ func @exp(%arg0: tensor<f32>) -> tensor<f32> {
 
 // Check a case with varying operand types.
 // CHECK-LABEL: func @select
+//  CHECK-SAME:   %[[ARG0:[0-9a-zA-Z]*]]: tensor<i1>
+//  CHECK-SAME:   %[[ARG1:[0-9a-zA-Z]*]]: tensor<i32>
+//  CHECK-SAME:   %[[ARG2:[0-9a-zA-Z]*]]: tensor<i32>
 func @select(%arg0: tensor<i1>, %arg1: tensor<i32>, %arg2: tensor<i32>) -> tensor<i32> {
   // CHECK: linalg.generic
-  // CHECK: ^bb0(%[[PRED:.*]]: i1, %[[TRUE_VAL:.*]]: i32, %[[FALSE_VAL:.*]]: i32):
+  // CHECK-SAME:  ins(%[[ARG0]], %[[ARG1]], %[[ARG2]]
+  // CHECK-SAME: outs(%[[ARG1]]
+  // CHECK: ^bb0(%[[PRED:.*]]: i1, %[[TRUE_VAL:.*]]: i32, %[[FALSE_VAL:.*]]: i32, %{{.*}}: i32):
   // CHECK:   select %[[PRED]], %[[TRUE_VAL]], %[[FALSE_VAL]] : i32
   %0 = select %arg0, %arg1, %arg2 : tensor<i1>, tensor<i32>
   return %0 : tensor<i32>
@@ -52,9 +70,41 @@ func @select(%arg0: tensor<i1>, %arg1: tensor<i32>, %arg2: tensor<i32>) -> tenso
 // -----
 
 // Spot-check an op that requires copying attributes properly to the created scalar op.
+// Also checks proper init_tensor usage.
 // CHECK-LABEL: func @cmpf(
+//  CHECK-SAME:   %[[ARG0:[0-9a-zA-Z]*]]: tensor<f32>
+//  CHECK-SAME:   %[[ARG1:[0-9a-zA-Z]*]]: tensor<f32>
 func @cmpf(%arg0: tensor<f32>, %arg1: tensor<f32>) -> tensor<i1> {
+  // CHECK: %[[INIT:.*]] = linalg.init_tensor [] : tensor<i1>
+  // CHECK: linalg.generic
+  // CHECK-SAME:  ins(%[[ARG0]], %[[ARG1]]
+  // CHECK-SAME: outs(%[[INIT]]
+  // CHECK: ^bb0(%{{.*}}: f32, %{{.*}}: f32, %{{.*}}: i1):
   // CHECK: cmpf "olt", %{{.*}}, %{{.*}} : f32
   %0 = cmpf "olt", %arg0, %arg1 : tensor<f32>
   return %0 : tensor<i1>
 }
+
+// -----
+
+// Check proper init_tensor usage in a mixed case.
+// CHECK-LABEL: func @cmpf(
+//  CHECK-SAME:   %[[ARG0:[0-9a-zA-Z]*]]: tensor<4x?x?x8x2x?xf32>
+//  CHECK-SAME:   %[[ARG1:[0-9a-zA-Z]*]]: tensor<4x?x?x8x2x?xf32>
+func @cmpf(%arg0: tensor<4x?x?x8x2x?xf32>, %arg1: tensor<4x?x?x8x2x?xf32>) -> tensor<4x?x?x8x2x?xi1> {
+  // CHECK: %[[C1:.*]] = constant 1 : index
+  // CHECK: %[[D1:.*]] = dim %[[ARG0]], %[[C1]] : tensor<4x?x?x8x2x?xf32>
+  // CHECK: %[[C2:.*]] = constant 2 : index
+  // CHECK: %[[D2:.*]] = dim %[[ARG0]], %[[C2]] : tensor<4x?x?x8x2x?xf32>
+  // CHECK: %[[C5:.*]] = constant 5 : index
+  // CHECK: %[[D5:.*]] = dim %[[ARG0]], %[[C5]] : tensor<4x?x?x8x2x?xf32>
+  // CHECK: %[[INIT:.*]] = linalg.init_tensor [4, %[[D1]], %[[D2]], 8, 2, %[[D5]]] : tensor<4x?x?x8x2x?xi1>
+  // CHECK: linalg.generic
+  // CHECK-SAME:  ins(%[[ARG0]], %[[ARG1]]
+  // CHECK-SAME: outs(%[[INIT]]
+  // CHECK: ^bb0(%{{.*}}: f32, %{{.*}}: f32, %{{.*}}: i1):
+  // CHECK: cmpf "olt", %{{.*}}, %{{.*}} : f32
+  %0 = cmpf "olt", %arg0, %arg1 : tensor<4x?x?x8x2x?xf32>
+  return %0 : tensor<4x?x?x8x2x?xi1>
+}
+
diff --git a/mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir b/mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
index e04d03b4e4938..17b8bda967b1e 100644
--- a/mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
+++ b/mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt %s -linalg-fold-unit-extent-dims -split-input-file | FileCheck %s
+// RUN: mlir-opt %s -split-input-file -linalg-fold-unit-extent-dims | FileCheck %s
 
 #accesses = [
   affine_map<(i, j, k, l, m) -> (i, k, m)>,
@@ -11,12 +11,12 @@
   library_call = "some_external_func"
 }
 
-func @drop_one_trip_loops(%arg0 : tensor<?x1x?xf32>) -> tensor<?x1x?x1x?xf32>
-{
+func @drop_one_trip_loops(%arg0 : tensor<?x1x?xf32>, %shape: tensor<?x1x?x1x?xf32>) -> tensor<?x1x?x1x?xf32> {
   %0 = linalg.generic #trait
-    ins(%arg0 : tensor<?x1x?xf32>) {
-       ^bb0(%arg1 : f32) :
-         linalg.yield %arg1 : f32
+     ins(%arg0 : tensor<?x1x?xf32>)
+    outs(%shape : tensor<?x1x?x1x?xf32>) {
+       ^bb0(%arg2 : f32, %arg3 : f32) :
+         linalg.yield %arg2 : f32
        } -> tensor<?x1x?x1x?xf32>
   return %0 : tensor<?x1x?x1x?xf32>
 }
@@ -48,12 +48,13 @@ func @drop_one_trip_loops(%arg0 : tensor<?x1x?xf32>) -> tensor<?x1x?x1x?xf32>
 }
 
 func @drop_one_trip_loops_indexed_generic
-  (%arg0 : tensor<?x1x?xi32>) -> tensor<?x1x?x1x?xi32>
+  (%arg0 : tensor<?x1x?xi32>, %shape: tensor<?x1x?x1x?xi32>) -> tensor<?x1x?x1x?xi32>
 {
   %0 = linalg.indexed_generic #trait
-    ins(%arg0 : tensor<?x1x?xi32>) {
+     ins(%arg0 : tensor<?x1x?xi32>)
+    outs(%shape: tensor<?x1x?x1x?xi32>) {
        ^bb0(%arg1 : index, %arg2 : index, %arg3 : index, %arg4 : index,
-            %arg5 : index, %arg6 : i32) :
+            %arg5 : index, %arg6 : i32, %arg7 : i32) :
 	 %1 = addi %arg1, %arg2 : index
 	 %2 = addi %1, %arg3 : index
 	 %3 = addi %2, %arg4 : index
@@ -68,7 +69,7 @@ func @drop_one_trip_loops_indexed_generic
 //       CHECK:   linalg.indexed_generic
 //       CHECK:   ^{{.+}}(
 //  CHECK-SAME:     %[[ARG1:[a-zA-Z0-9]+]]: index, %[[ARG2:[a-zA-Z0-9]+]]: index
-//  CHECK-SAME:     %[[ARG3:[a-zA-Z0-9]+]]: index, %[[ARG4:[a-zA-Z0-9]+]]: i32)
+//  CHECK-SAME:     %[[ARG3:[a-zA-Z0-9]+]]: index, %[[ARG4:[a-zA-Z0-9]+]]: i32, %{{.*}}: i32)
 //       CHECK:     %[[T3:.+]] = addi %[[ARG1]], %[[ARG2]]
 //       CHECK:     %[[T4:.+]] = addi %[[T3]], %[[ARG3]]
 //       CHECK:     %[[T5:.+]] = index_cast %[[T4]] : index to i32
@@ -88,8 +89,9 @@ func @drop_one_trip_loops_indexed_generic
 func @drop_all_loops(%arg0 : tensor<1x1xf32>) -> tensor<1x1xf32>
 {
   %0 = linalg.generic #trait
-    ins(%arg0 : tensor<1x1xf32>) {
-       ^bb0(%arg1: f32) :
+     ins(%arg0 : tensor<1x1xf32>)
+    outs(%arg0 : tensor<1x1xf32>) {
+       ^bb0(%arg1: f32, %arg2: f32) :
          linalg.yield %arg1 : f32
        } -> tensor<1x1xf32>
   return %0 : tensor<1x1xf32>
@@ -112,11 +114,11 @@ func @drop_all_loops(%arg0 : tensor<1x1xf32>) -> tensor<1x1xf32>
 }
 
 func @drop_all_loops_indexed_generic
-  (%arg0 : tensor<1x1xi32>) -> tensor<1x1xi32>
-{
+  (%arg0 : tensor<1x1xi32>) -> tensor<1x1xi32>{
   %0 = linalg.indexed_generic #trait
-    ins(%arg0 : tensor<1x1xi32>) {
-       ^bb0(%arg1 : index, %arg2 : index, %arg3: i32) :
+     ins(%arg0 : tensor<1x1xi32>)
+    outs(%arg0 : tensor<1x1xi32>) {
+       ^bb0(%arg1 : index, %arg2 : index, %arg3: i32, %arg4: i32) :
          %1 = addi %arg1, %arg2 : index
 	 %2 = index_cast %1 : index to i32
 	 %3 = addi %2, %arg3 : i32
@@ -127,7 +129,7 @@ func @drop_all_loops_indexed_generic
 
 // CHECK-LABEL: func @drop_all_loops_indexed_generic
 //       CHECK:   linalg.indexed_generic
-//       CHECK:   ^{{.+}}(%[[ARG1:.+]]: i32)
+//       CHECK:   ^{{.+}}(%[[ARG1:.+]]: i32, %[[ARG2:.+]]: i32)
 //       CHECK:     linalg.yield %[[ARG1]] : i32
 
 // -----
@@ -143,10 +145,11 @@ func @drop_all_loops_indexed_generic
   library_call = "some_external_fn"
 }
 
-func @leading_dim_1_canonicalization(%arg0: tensor<1x5xf32>) -> tensor<5xf32> {
+func @leading_dim_1_canonicalization(%arg0: tensor<1x5xf32>, %shape: tensor<5xf32>) -> tensor<5xf32> {
   %0 = linalg.generic #trait
-    ins(%arg0 : tensor<1x5xf32>) {
-  ^bb0(%arg2: f32):     // no predecessors
+     ins(%arg0 : tensor<1x5xf32>)
+    outs(%shape : tensor<5xf32>) {
+  ^bb0(%arg2: f32, %arg3: f32):     // no predecessors
     linalg.yield %arg2 : f32
   } -> tensor<5xf32>
   return %0 : tensor<5xf32>
@@ -172,16 +175,17 @@ func @leading_dim_1_canonicalization(%arg0: tensor<1x5xf32>) -> tensor<5xf32> {
   library_call = "some_external_fn"
 }
 
-func @broadcast_test(%arg0 : tensor<5xf32>, %arg1 : tensor<5xf32>) -> tensor<5x5xf32>
+func @broadcast_test(%arg0 : tensor<5xf32>, %arg1 : tensor<5xf32>, %shape : tensor<5x5xf32>) -> tensor<5x5xf32>
 {
   %0 = linalg.tensor_reshape %arg0 [affine_map<(d0, d1) -> (d0, d1)>] :
        tensor<5xf32> into tensor<1x5xf32>
   %1 = linalg.tensor_reshape %arg1 [affine_map<(d0, d1) -> (d0, d1)>] :
        tensor<5xf32> into tensor<5x1xf32>
   %2 = linalg.generic #trait
-    ins(%0, %1 : tensor<1x5xf32>, tensor<5x1xf32>) {
-       ^bb0(%arg2: f32, %arg3: f32):
-         %3 = addf %arg2, %arg3 : f32
+     ins(%0, %1 : tensor<1x5xf32>, tensor<5x1xf32>)
+    outs(%shape : tensor<5x5xf32>) {
+       ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):
+         %3 = addf %arg3, %arg4 : f32
          linalg.yield %3 : f32
        } -> tensor<5x5xf32>
   return %2 : tensor<5x5xf32>
@@ -209,12 +213,13 @@ func @broadcast_test(%arg0 : tensor<5xf32>, %arg1 : tensor<5xf32>) -> tensor<5x5
   library_call = "some_external_fn"
 }
 
-func @broadcast_scalar(%arg0 : tensor<1x1xf32>) -> tensor<?x?xf32>
+func @broadcast_scalar(%arg0 : tensor<1x1xf32>, %shape : tensor<?x?xf32>) -> tensor<?x?xf32>
 {
    %0 = linalg.generic #trait
-    ins(%arg0 : tensor<1x1xf32>) {
-      ^bb0(%arg1 : f32):
-        linalg.yield %arg1 : f32
+     ins(%arg0 : tensor<1x1xf32>)
+    outs(%shape : tensor<?x?xf32>) {
+      ^bb0(%arg2 : f32, %arg3 : f32):
+        linalg.yield %arg2 : f32
    } -> tensor<?x?xf32>
    return %0 : tensor<?x?xf32>
 }
diff --git a/mlir/test/Dialect/Linalg/fold-unit-trip-loops.mlir b/mlir/test/Dialect/Linalg/fold-unit-trip-loops.mlir
index 6d75c480b5c6a..d0c526e441b69 100644
--- a/mlir/test/Dialect/Linalg/fold-unit-trip-loops.mlir
+++ b/mlir/test/Dialect/Linalg/fold-unit-trip-loops.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt %s -linalg-fold-unit-extent-dims="fold-one-trip-loops-only" -split-input-file | FileCheck %s
+// RUN: mlir-opt %s -split-input-file -linalg-fold-unit-extent-dims="fold-one-trip-loops-only" | FileCheck %s
 
 #accesses = [
   affine_map<(i, j, k, l, m) -> (i, k, m)>,
@@ -11,11 +11,12 @@
   library_call = "some_external_func"
 }
 
-func @drop_one_trip_loops(%arg0 : tensor<?x1x?xf32>) -> tensor<?x1x?x1x?xf32>
+func @drop_one_trip_loops(%arg0 : tensor<?x1x?xf32>, %shape: tensor<?x1x?x1x?xf32>) -> tensor<?x1x?x1x?xf32>
 {
   %0 = linalg.generic #trait
-    ins(%arg0 : tensor<?x1x?xf32>) {
-       ^bb0(%arg1 : f32) :
+    ins(%arg0 : tensor<?x1x?xf32>)
+    outs(%shape : tensor<?x1x?x1x?xf32>) {
+       ^bb0(%arg1 : f32, %arg2 : f32) :
          linalg.yield %arg1 : f32
        } -> tensor<?x1x?x1x?xf32>
   return %0 : tensor<?x1x?x1x?xf32>
@@ -40,8 +41,9 @@ func @drop_one_trip_loops(%arg0 : tensor<?x1x?xf32>) -> tensor<?x1x?x1x?xf32>
 func @drop_all_loops(%arg0 : tensor<1x1xf32>) -> tensor<1x1xf32>
 {
   %0 = linalg.generic #trait
-    ins(%arg0 : tensor<1x1xf32>) {
-       ^bb0(%arg1: f32) :
+     ins(%arg0 : tensor<1x1xf32>)
+    outs(%arg0 : tensor<1x1xf32>) {
+       ^bb0(%arg1: f32, %arg2: f32) :
          linalg.yield %arg1 : f32
        } -> tensor<1x1xf32>
   return %0 : tensor<1x1xf32>
@@ -91,10 +93,11 @@ func @drop_all_loops(%arg0 : memref<1x1xf32>, %arg1 : memref<1x1xf32>)
   library_call = "some_external_fn"
 }
 
-func @leading_dim_1_canonicalization(%arg0: tensor<1x5xf32>) -> tensor<5xf32> {
+func @leading_dim_1_canonicalization(%arg0: tensor<1x5xf32>, %shape: tensor<5xf32>) -> tensor<5xf32> {
   %0 = linalg.generic #trait
-      ins(%arg0 : tensor<1x5xf32>) {
-    ^bb0(%arg2: f32):     // no predecessors
+       ins(%arg0 : tensor<1x5xf32>)
+      outs(%shape : tensor<5xf32>) {
+    ^bb0(%arg2: f32, %arg3: f32):     // no predecessors
       linalg.yield %arg2 : f32
   } -> tensor<5xf32>
   return %0 : tensor<5xf32>
diff --git a/mlir/test/Dialect/Linalg/fusion-tensor.mlir b/mlir/test/Dialect/Linalg/fusion-tensor.mlir
index ff0394f18249c..df7e59d59dde6 100644
--- a/mlir/test/Dialect/Linalg/fusion-tensor.mlir
+++ b/mlir/test/Dialect/Linalg/fusion-tensor.mlir
@@ -6,29 +6,36 @@
 // CHECK-LABEL: @add_mul_fusion
 func @add_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : tensor<?x?xf32>, %arg2 : tensor<?x?xf32>) -> tensor<?x?xf32>
 {
-  %0 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = ["parallel", "parallel"]}
-      ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
-      %1 = addf %arg3, %arg4 : f32
-      linalg.yield %1 : f32
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %0 = dim %arg0, %c0 : tensor<?x?xf32>
+  %1 = dim %arg0, %c1 : tensor<?x?xf32>
+  %2 = linalg.init_tensor [%0, %1] : tensor<?x?xf32>
+  %3 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = ["parallel", "parallel"]}
+      ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%2 : tensor<?x?xf32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       // no predecessors
+      %4 = addf %arg3, %arg4 : f32
+      linalg.yield %4 : f32
   } -> tensor<?x?xf32>
   // CHECK: linalg.generic {
   // CHECK-SAME: indexing_maps = {{\[}}[[$MAP0]], [[$MAP0]], [[$MAP0]], [[$MAP0]]{{\]}}
-  %2 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = ["parallel", "parallel"]}
-      ins(%0, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>) {
+  %4 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = ["parallel", "parallel"]}
+      ins(%3, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%2 : tensor<?x?xf32>) {
     // CHECK: ^{{[a-zA-Z0-9_]*}}
     // CHECK-SAME: [[ARG0:%[a-zA-Z0-9_]*]]
     // CHECK-SAME: [[ARG1:%[a-zA-Z0-9_]*]]
     // CHECK-SAME: [[ARG2:%[a-zA-Z0-9_]*]]
-    ^bb0(%arg5: f32, %arg6: f32):       // no predecessors
+    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):       // no predecessors
       // CHECK: [[T1:%[a-zA-Z0-9_]*]] = addf [[ARG0]], [[ARG1]]
       // CHECK-NOT: linalg.yield
       // CHECK: mulf [[T1]], [[ARG2]]
       // CHECK: linalg.yield
-      %3 = mulf %arg5, %arg6 : f32
-      linalg.yield %3 : f32
+      %5 = mulf %arg5, %arg6 : f32
+      linalg.yield %5 : f32
     } -> tensor<?x?xf32>
-  return %2 : tensor<?x?xf32>
+  return %4 : tensor<?x?xf32>
 }
 
 // -----
@@ -41,21 +48,28 @@ func @add_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : tensor<?x?xf32>, %arg2 : te
 // CHECK-LABEL: @transpose_add_mul_fusion
 func @transpose_add_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : tensor<?x?xf32>, %arg2 : tensor<?x?xf32>) -> tensor<?x?xf32>
 {
-  %0 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]}
-      ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
-      %1 = addf %arg3, %arg4 : f32
-      linalg.yield %1 : f32
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %0 = dim %arg0, %c0 : tensor<?x?xf32>
+  %1 = dim %arg0, %c1 : tensor<?x?xf32>
+  %2 = linalg.init_tensor [%0, %1] : tensor<?x?xf32>
+  %3 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]}
+      ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%2 : tensor<?x?xf32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       // no predecessors
+      %4 = addf %arg3, %arg4 : f32
+      linalg.yield %4 : f32
   } -> tensor<?x?xf32>
   // CHECK: linalg.generic {
   // CHECK-SAME: indexing_maps = {{\[}}[[$MAP0]], [[$MAP1]], [[$MAP0]], [[$MAP0]]{{\]}}
-  %2 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = ["parallel", "parallel"]}
-      ins(%0, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>) {
-    ^bb0(%arg5: f32, %arg6: f32):       // no predecessors
-      %3 = mulf %arg5, %arg6 : f32
-      linalg.yield %3 : f32
+  %4 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = ["parallel", "parallel"]}
+      ins(%3, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%2 : tensor<?x?xf32>) {
+    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):       // no predecessors
+      %5 = mulf %arg5, %arg6 : f32
+      linalg.yield %5 : f32
     } -> tensor<?x?xf32>
-  return %2 : tensor<?x?xf32>
+  return %4 : tensor<?x?xf32>
 }
 
 // -----
@@ -68,21 +82,28 @@ func @transpose_add_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : tensor<?x?xf32>,
 // CHECK-LABEL: @add_transpose_mul_fusion
 func @add_transpose_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : tensor<?x?xf32>, %arg2 : tensor<?x?xf32>) -> tensor<?x?xf32>
 {
-  %0 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]}
-      ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
-      %1 = addf %arg3, %arg4 : f32
-      linalg.yield %1 : f32
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %0 = dim %arg0, %c0 : tensor<?x?xf32>
+  %1 = dim %arg0, %c1 : tensor<?x?xf32>
+  %2 = linalg.init_tensor [%0, %1] : tensor<?x?xf32>
+  %3 = linalg.generic {indexing_maps = [#map0, #map1, #map0], iterator_types = ["parallel", "parallel"]}
+      ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%2 : tensor<?x?xf32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       // no predecessors
+      %4 = addf %arg3, %arg4 : f32
+      linalg.yield %4 : f32
   } -> tensor<?x?xf32>
   // CHECK: linalg.generic {
   // CHECK-SAME: indexing_maps = {{\[}}[[$MAP1]], [[$MAP0]], [[$MAP0]], [[$MAP0]]{{\]}}
-  %2 = linalg.generic {indexing_maps = [#map1, #map0, #map0], iterator_types = ["parallel", "parallel"]}
-      ins(%0, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>) {
-    ^bb0(%arg5: f32, %arg6: f32):       // no predecessors
-      %3 = mulf %arg5, %arg6 : f32
-      linalg.yield %3 : f32
+  %4 = linalg.generic {indexing_maps = [#map1, #map0, #map0], iterator_types = ["parallel", "parallel"]}
+      ins(%3, %arg2 : tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%2 : tensor<?x?xf32>){
+    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):       // no predecessors
+      %5= mulf %arg5, %arg6 : f32
+      linalg.yield %5 : f32
     } -> tensor<?x?xf32>
-  return %2 : tensor<?x?xf32>
+  return %4 : tensor<?x?xf32>
 }
 
 // -----
@@ -96,21 +117,29 @@ func @add_transpose_mul_fusion(%arg0: tensor<?x?xf32>, %arg1 : tensor<?x?xf32>,
 // CHECK-LABEL: @add_broadcast_mul_fusion
 func @add_broadcast_mul_fusion(%arg0: tensor<?xf32>, %arg1 : tensor<?xf32>, %arg2 : tensor<?x?xf32>) -> tensor<?x?xf32>
 {
-  %0 = linalg.generic {indexing_maps = [#map2, #map2, #map2], iterator_types = ["parallel"]}
-      ins(%arg0, %arg1 : tensor<?xf32>, tensor<?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
-      %1 = addf %arg3, %arg4 : f32
-      linalg.yield %1 : f32
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %0 = dim %arg0, %c0 : tensor<?xf32>
+  %1 = linalg.init_tensor [%0] : tensor<?xf32>
+  %2 = linalg.generic {indexing_maps = [#map2, #map2, #map2], iterator_types = ["parallel"]}
+      ins(%arg0, %arg1 : tensor<?xf32>, tensor<?xf32>)
+      outs(%1 : tensor<?xf32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       // no predecessors
+      %3 = addf %arg3, %arg4 : f32
+      linalg.yield %3 : f32
   } -> tensor<?xf32>
   // CHECK: linalg.generic {
   // CHECK-SAME: indexing_maps = {{\[}}[[$MAP1]], [[$MAP1]], [[$MAP0]], [[$MAP0]]
-  %2 = linalg.generic {indexing_maps = [#map1, #map0, #map0], iterator_types = ["parallel", "parallel"]}
-      ins(%0, %arg2 : tensor<?xf32>, tensor<?x?xf32>) {
-    ^bb0(%arg5: f32, %arg6: f32):       // no predecessors
-      %3 = mulf %arg5, %arg6 : f32
-      linalg.yield %3 : f32
+  %3 = dim %arg2, %c1 : tensor<?x?xf32>
+  %4 = linalg.init_tensor [%0, %3] : tensor<?x?xf32>
+  %5 = linalg.generic {indexing_maps = [#map1, #map0, #map0], iterator_types = ["parallel", "parallel"]}
+      ins(%2, %arg2 : tensor<?xf32>, tensor<?x?xf32>)
+      outs(%4 : tensor<?x?xf32>){
+    ^bb0(%arg5: f32, %arg6: f32, %arg7: f32):       // no predecessors
+      %6 = mulf %arg5, %arg6 : f32
+      linalg.yield %6 : f32
     } -> tensor<?x?xf32>
-  return %2 : tensor<?x?xf32>
+  return %5 : tensor<?x?xf32>
 }
 
 // -----
@@ -121,23 +150,26 @@ func @add_broadcast_mul_fusion(%arg0: tensor<?xf32>, %arg1 : tensor<?xf32>, %arg
 // CHECK-LABEL: @add_mul_scalar_fusion
 func @add_mul_scalar_fusion(%arg0: tensor<f32>, %arg1: tensor<f32>, %arg2: tensor<f32>) -> tensor<f32>
 {
-  %0 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = []}
-      ins(%arg0, %arg1 : tensor<f32>, tensor<f32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
-      %1 = addf %arg3, %arg4 : f32
-      linalg.yield %1 : f32
+  %0 = linalg.init_tensor [] : tensor<f32>
+  %1 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = []}
+      ins(%arg0, %arg1 : tensor<f32>, tensor<f32>)
+      outs(%0 : tensor<f32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       // no predecessors
+      %2 = addf %arg3, %arg4 : f32
+      linalg.yield %2 : f32
   } -> tensor<f32>
   // CHECK: linalg.generic {
   // CHECK: addf
   // CHECK: mulf
-  %1 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = []}
-      ins(%0, %arg2 : tensor<f32>, tensor<f32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
-      %1 = mulf %arg3, %arg4 : f32
-      linalg.yield %1 : f32
+  %2 = linalg.generic {indexing_maps = [#map0, #map0, #map0], iterator_types = []}
+      ins(%1, %arg2 : tensor<f32>, tensor<f32>)
+      outs(%0 : tensor<f32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       // no predecessors
+      %3 = mulf %arg3, %arg4 : f32
+      linalg.yield %3 : f32
   } -> tensor<f32>
 
-  return %1 : tensor<f32>
+  return %2 : tensor<f32>
 }
 
 // -----
@@ -146,22 +178,29 @@ func @add_mul_scalar_fusion(%arg0: tensor<f32>, %arg1: tensor<f32>, %arg2: tenso
 #map1 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 func @generic_op_constant_fusion(%arg0 : tensor<5x?x?xf32>) -> tensor<5x?x?xf32>
 {
-  %0 = constant dense<42.0> : tensor<5xf32>
-  %1 = linalg.generic {
-         indexing_maps = [#map0, #map1, #map1],
-         iterator_types = ["parallel", "parallel", "parallel"]}
-         ins(%0, %arg0 : tensor<5xf32>, tensor<5x?x?xf32>) {
-       ^bb0(%arg1: f32, %arg2: f32):
-         %2 = mulf %arg1, %arg2 : f32
-         linalg.yield %2 : f32
-       } -> tensor<5x?x?xf32>
-  return %1 : tensor<5x?x?xf32>
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %c2 = constant 2 : index
+  %cst = constant dense<42.0> : tensor<5xf32>
+  %0 = dim %arg0, %c1 : tensor<5x?x?xf32>
+  %1 = dim %arg0, %c2 : tensor<5x?x?xf32>
+  %2 = linalg.init_tensor [5, %0, %1] : tensor<5x?x?xf32>
+  %3 = linalg.generic {
+    indexing_maps = [#map0, #map1, #map1],
+    iterator_types = ["parallel", "parallel", "parallel"]}
+    ins(%cst, %arg0 : tensor<5xf32>, tensor<5x?x?xf32>)
+    outs(%2 : tensor<5x?x?xf32>) {
+    ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
+      %4 = mulf %arg1, %arg2 : f32
+      linalg.yield %4 : f32
+    } -> tensor<5x?x?xf32>
+  return %3 : tensor<5x?x?xf32>
 }
 //   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 // CHECK-LABEL: func @generic_op_constant_fusion
 //       CHECK:   %[[CST:.*]] = constant {{.*}} : f32
 //       CHECK:   linalg.generic
-//       CHECK:   ^{{.*}}(%[[ARG1:.*]]: f32)
+//       CHECK:   ^{{.+}}(%[[ARG1:[a-zA-Z0-9_]+]]: f32, %{{.+}}: f32):
 //       CHECK:     mulf %[[CST]], %[[ARG1]]
 
 // -----
@@ -171,16 +210,23 @@ func @generic_op_constant_fusion(%arg0 : tensor<5x?x?xf32>) -> tensor<5x?x?xf32>
 func @indexed_generic_op_constant_fusion(%arg0 : tensor<5x?x?xf32>)
                                          -> tensor<5x?x?xf32>
 {
-  %0 = constant dense<42.0> : tensor<5xf32>
-  %1 = linalg.indexed_generic {
-         indexing_maps = [#map0, #map1, #map1],
-         iterator_types = ["parallel", "parallel", "parallel"]}
-         ins(%0, %arg0 : tensor<5xf32>, tensor<5x?x?xf32>) {
-       ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: f32, %arg5 : f32):
-         %2 = mulf %arg4, %arg5 : f32
-         linalg.yield %2 : f32
-       } -> tensor<5x?x?xf32>
-  return %1 : tensor<5x?x?xf32>
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %c2 = constant 2 : index
+  %cst = constant dense<42.0> : tensor<5xf32>
+  %0 = dim %arg0, %c1 : tensor<5x?x?xf32>
+  %1 = dim %arg0, %c2 : tensor<5x?x?xf32>
+  %2 = linalg.init_tensor [5, %0, %1] : tensor<5x?x?xf32>
+  %3 = linalg.indexed_generic {
+    indexing_maps = [#map0, #map1, #map1],
+    iterator_types = ["parallel", "parallel", "parallel"]}
+    ins(%cst, %arg0 : tensor<5xf32>, tensor<5x?x?xf32>)
+    outs(%2 : tensor<5x?x?xf32>) {
+    ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: f32, %arg5 : f32, %arg6 : f32):
+      %4 = mulf %arg4, %arg5 : f32
+      linalg.yield %4 : f32
+    } -> tensor<5x?x?xf32>
+  return %3 : tensor<5x?x?xf32>
 }
 //   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 // CHECK-LABEL: func @indexed_generic_op_constant_fusion
@@ -190,7 +236,7 @@ func @indexed_generic_op_constant_fusion(%arg0 : tensor<5x?x?xf32>)
 //  CHECK-SAME:     %[[ARG1:[a-zA-Z0-9]*]]: index
 //  CHECK-SAME:     %[[ARG2:[a-zA-Z0-9]*]]: index
 //  CHECK-SAME:     %[[ARG3:[a-zA-Z0-9]*]]: index
-//  CHECK-SAME:     %[[ARG4:.*]]: f32)
+//  CHECK-SAME:     %[[ARG4:[a-zA-Z0-9_]*]]: f32, %{{.*}}: f32)
 //       CHECK:     mulf %[[CST]], %[[ARG4]]
 
 // -----
@@ -200,22 +246,29 @@ func @indexed_generic_op_constant_fusion(%arg0 : tensor<5x?x?xf32>)
 func @generic_op_zero_dim_constant_fusion(%arg0 : tensor<5x?x?xf32>)
   -> tensor<5x?x?xf32>
 {
-  %0 = constant dense<42.0> : tensor<f32>
-  %1 = linalg.generic {
-         indexing_maps = [#map0, #map1, #map1],
-         iterator_types = ["parallel", "parallel", "parallel"]}
-         ins(%0, %arg0 : tensor<f32>, tensor<5x?x?xf32>) {
-       ^bb0(%arg1: f32, %arg2: f32):
-         %2 = mulf %arg1, %arg2 : f32
-         linalg.yield %2 : f32
-       } -> tensor<5x?x?xf32>
-  return %1 : tensor<5x?x?xf32>
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %c2 = constant 2 : index
+  %cst = constant dense<42.0> : tensor<f32>
+  %0 = dim %arg0, %c1 : tensor<5x?x?xf32>
+  %1 = dim %arg0, %c2 : tensor<5x?x?xf32>
+  %2 = linalg.init_tensor [5, %0, %1] : tensor<5x?x?xf32>
+  %3 = linalg.generic {
+    indexing_maps = [#map0, #map1, #map1],
+    iterator_types = ["parallel", "parallel", "parallel"]}
+    ins(%cst, %arg0 : tensor<f32>, tensor<5x?x?xf32>)
+    outs(%2 : tensor<5x?x?xf32>) {
+    ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
+      %4 = mulf %arg1, %arg2 : f32
+      linalg.yield %4 : f32
+    } -> tensor<5x?x?xf32>
+  return %3 : tensor<5x?x?xf32>
 }
 //   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 // CHECK-LABEL: func @generic_op_zero_dim_constant_fusion
 //       CHECK:   %[[CST:.*]] = constant {{.*}} : f32
 //       CHECK:   linalg.generic
-//       CHECK:   ^{{.*}}(%[[ARG1:.*]]: f32)
+//       CHECK:   ^{{.*}}(%[[ARG1:[a-zA-Z0-9_]*]]: f32, %{{.*}}: f32)
 //       CHECK:     mulf %[[CST]], %[[ARG1]]
 
 // -----
@@ -225,16 +278,23 @@ func @generic_op_zero_dim_constant_fusion(%arg0 : tensor<5x?x?xf32>)
 func @indexed_generic_op_zero_dim_constant_fusion
   (%arg0 : tensor<5x?x?xf32>) -> tensor<5x?x?xf32>
 {
-  %0 = constant dense<42.0> : tensor<f32>
-  %1 = linalg.indexed_generic {
-         indexing_maps = [#map0, #map1, #map1],
-         iterator_types = ["parallel", "parallel", "parallel"]}
-         ins(%0, %arg0 : tensor<f32>, tensor<5x?x?xf32>) {
-       ^bb0(%arg1 : index, %arg2 : index, %arg3 : index, %arg4: f32, %arg5: f32):
-         %2 = mulf %arg4, %arg5 : f32
-         linalg.yield %2 : f32
-       } -> tensor<5x?x?xf32>
-  return %1 : tensor<5x?x?xf32>
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %c2 = constant 2 : index
+  %cst = constant dense<42.0> : tensor<f32>
+  %0 = dim %arg0, %c1 : tensor<5x?x?xf32>
+  %1 = dim %arg0, %c2 : tensor<5x?x?xf32>
+  %2 = linalg.init_tensor [5, %0, %1] : tensor<5x?x?xf32>
+  %3 = linalg.indexed_generic {
+    indexing_maps = [#map0, #map1, #map1],
+    iterator_types = ["parallel", "parallel", "parallel"]}
+    ins(%cst, %arg0 : tensor<f32>, tensor<5x?x?xf32>)
+    outs(%2 : tensor<5x?x?xf32>) {
+    ^bb0(%arg1 : index, %arg2 : index, %arg3 : index, %arg4: f32, %arg5: f32, %arg6: f32):
+      %4 = mulf %arg4, %arg5 : f32
+      linalg.yield %4 : f32
+    } -> tensor<5x?x?xf32>
+  return %3 : tensor<5x?x?xf32>
 }
 //   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 // CHECK-LABEL: func @indexed_generic_op_zero_dim_constant_fusion
@@ -244,7 +304,7 @@ func @indexed_generic_op_zero_dim_constant_fusion
 //  CHECK-SAME:     %[[ARG1:[a-zA-Z0-9]*]]: index
 //  CHECK-SAME:     %[[ARG2:[a-zA-Z0-9]*]]: index
 //  CHECK-SAME:     %[[ARG3:[a-zA-Z0-9]*]]: index
-//  CHECK-SAME:     %[[ARG4:.*]]: f32)
+//  CHECK-SAME:     %[[ARG4:[a-zA-Z0-9_]*]]: f32, %{{.*}}: f32)
 //       CHECK:     mulf %[[CST]], %[[ARG4]]
 
 // -----
@@ -252,26 +312,33 @@ func @indexed_generic_op_zero_dim_constant_fusion
 #map0 = affine_map<(d0, d1) -> (d0, d1)>
 func @generic_op_indexed_generic_op_fusion(%arg0: tensor<?x?xi32>,
                                            %arg1: tensor<?x?xi32>) -> tensor<?x?xi32> {
-    %0 = linalg.generic {
-      indexing_maps = [#map0, #map0, #map0],
-      iterator_types = ["parallel", "parallel"] }
-      ins(%arg0, %arg1  : tensor<?x?xi32>, tensor<?x?xi32>) {
-    ^bb0(%arg2: i32, %arg3: i32):       // no predecessors
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %0 = dim %arg0, %c0 : tensor<?x?xi32>
+  %1 = dim %arg0, %c1 : tensor<?x?xi32>
+  %2 = linalg.init_tensor [%0, %1] : tensor<?x?xi32>
+  %3 = linalg.generic {
+    indexing_maps = [#map0, #map0, #map0],
+    iterator_types = ["parallel", "parallel"] }
+    ins(%arg0, %arg1  : tensor<?x?xi32>, tensor<?x?xi32>)
+    outs(%2 : tensor<?x?xi32>) {
+    ^bb0(%arg2: i32, %arg3: i32, %arg4: i32):       // no predecessors
       %10 = addi %arg2, %arg3 : i32
       linalg.yield %10 : i32
     } -> tensor<?x?xi32>
-    %1 = linalg.indexed_generic {
-      indexing_maps = [#map0, #map0],
-      iterator_types = ["parallel", "parallel"] }
-      ins(%0 : tensor<?x?xi32>) {
-    ^bb0(%arg2: index, %arg3: index, %arg4: i32):       // no predecessors
-      %2 = index_cast %arg2 : index to i32
-      %3 = index_cast %arg3 : index to i32
-      %4 = addi %arg4, %2 : i32
-      %5 = subi %4, %3 : i32
-      linalg.yield %5 : i32
+  %4 = linalg.indexed_generic {
+    indexing_maps = [#map0, #map0],
+    iterator_types = ["parallel", "parallel"] }
+    ins(%3 : tensor<?x?xi32>)
+    outs(%2 : tensor<?x?xi32>) {
+    ^bb0(%arg2: index, %arg3: index, %arg4: i32, %arg5: i32):       // no predecessors
+      %5 = index_cast %arg2 : index to i32
+      %6 = index_cast %arg3 : index to i32
+      %7 = addi %arg4, %5 : i32
+      %8 = subi %7, %6 : i32
+      linalg.yield %8 : i32
     } -> tensor<?x?xi32>
-  return %1 : tensor<?x?xi32>
+  return %4 : tensor<?x?xi32>
 }
 //   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1) -> (d0, d1)>
 // CHECK-LABEL: func @generic_op_indexed_generic_op_fusion
@@ -295,26 +362,33 @@ func @generic_op_indexed_generic_op_fusion(%arg0: tensor<?x?xi32>,
 #map0 = affine_map<(d0, d1) -> (d0, d1)>
 func @indexed_generic_op_generic_op_fusion(%arg0: tensor<?x?xi32>,
                                            %arg1: tensor<?x?xi32>) -> tensor<?x?xi32> {
-  %0 = linalg.indexed_generic {
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %0 = dim %arg0, %c0 : tensor<?x?xi32>
+  %1 = dim %arg0, %c1 : tensor<?x?xi32>
+  %2 = linalg.init_tensor [%0, %1] : tensor<?x?xi32>
+  %3 = linalg.indexed_generic {
     indexing_maps = [#map0, #map0],
     iterator_types = ["parallel", "parallel"] }
-    ins(%arg0 : tensor<?x?xi32>) {
-  ^bb0(%arg2: index, %arg3: index, %arg4: i32):       // no predecessors
-    %2 = index_cast %arg2 : index to i32
-    %3 = index_cast %arg3 : index to i32
-    %4 = addi %arg4, %2 : i32
-    %5 = subi %4, %3 : i32
-    linalg.yield %5 : i32
-  } -> tensor<?x?xi32>
-  %1 = linalg.generic {
+    ins(%arg0 : tensor<?x?xi32>)
+    outs(%2 : tensor<?x?xi32>) {
+    ^bb0(%arg2: index, %arg3: index, %arg4: i32, %arg5: i32):       // no predecessors
+      %4 = index_cast %arg2 : index to i32
+      %5 = index_cast %arg3 : index to i32
+      %6 = addi %arg4, %4 : i32
+      %7 = subi %6, %5 : i32
+      linalg.yield %7 : i32
+    } -> tensor<?x?xi32>
+  %4 = linalg.generic {
     indexing_maps = [#map0, #map0, #map0],
     iterator_types = ["parallel", "parallel"] }
-    ins(%0, %arg1 : tensor<?x?xi32>, tensor<?x?xi32>) {
-  ^bb0(%arg2: i32, %arg3: i32):       // no predecessors
-    %10 = addi %arg2, %arg3 : i32
-    linalg.yield %10 : i32
-  } -> tensor<?x?xi32>
-  return %1 : tensor<?x?xi32>
+    ins(%3, %arg1 : tensor<?x?xi32>, tensor<?x?xi32>)
+    outs(%2 : tensor<?x?xi32>) {
+    ^bb0(%arg2: i32, %arg3: i32, %arg4: i32):       // no predecessors
+      %10 = addi %arg2, %arg3 : i32
+      linalg.yield %10 : i32
+    } -> tensor<?x?xi32>
+  return %4 : tensor<?x?xi32>
 }
 //   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1) -> (d0, d1)>
 // CHECK-LABEL: func @indexed_generic_op_generic_op_fusion
@@ -339,29 +413,36 @@ func @indexed_generic_op_generic_op_fusion(%arg0: tensor<?x?xi32>,
 #map0 = affine_map<(d0, d1) -> (d1, d0)>
 #map1 = affine_map<(d0, d1) -> (d0, d1)>
 func @indexed_generic_op_fusion(%arg0: tensor<?x?xi32>) -> tensor<?x?xi32> {
-    %0 = linalg.indexed_generic {
-      indexing_maps = [#map0, #map0],
-      iterator_types = ["parallel", "parallel"] }
-      ins(%arg0 : tensor<?x?xi32>) {
-    ^bb0(%arg2: index, %arg3: index, %arg4: i32):       // no predecessors
-      %2 = index_cast %arg2 : index to i32
-      %3 = index_cast %arg3 : index to i32
-      %4 = addi %arg4, %2 : i32
-      %5 = subi %4, %3 : i32
-      linalg.yield %5 : i32
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %0 = dim %arg0, %c0 : tensor<?x?xi32>
+  %1 = dim %arg0, %c1 : tensor<?x?xi32>
+  %2 = linalg.init_tensor [%0, %1] : tensor<?x?xi32>
+  %3 = linalg.indexed_generic {
+    indexing_maps = [#map0, #map0],
+    iterator_types = ["parallel", "parallel"] }
+    ins(%arg0 : tensor<?x?xi32>)
+    outs(%2 : tensor<?x?xi32>) {
+    ^bb0(%arg2: index, %arg3: index, %arg4: i32, %arg5: i32):       // no predecessors
+      %4 = index_cast %arg2 : index to i32
+      %5 = index_cast %arg3 : index to i32
+      %6 = addi %arg4, %4 : i32
+      %7 = subi %5, %6 : i32
+      linalg.yield %7 : i32
     } -> tensor<?x?xi32>
-    %1 = linalg.indexed_generic {
-      indexing_maps = [#map1, #map1],
-      iterator_types = ["parallel", "parallel"] }
-      ins(%0 : tensor<?x?xi32>) {
-    ^bb0(%arg2: index, %arg3: index, %arg4: i32):       // no predecessors
-      %2 = index_cast %arg2 : index to i32
-      %3 = index_cast %arg3 : index to i32
-      %4 = addi %arg4, %2 : i32
-      %5 = subi %4, %3 : i32
-      linalg.yield %5 : i32
+  %4= linalg.indexed_generic {
+    indexing_maps = [#map1, #map1],
+    iterator_types = ["parallel", "parallel"] }
+    ins(%3 : tensor<?x?xi32>)
+    outs(%2 : tensor<?x?xi32>) {
+    ^bb0(%arg2: index, %arg3: index, %arg4: i32, %arg5: i32):       // no predecessors
+      %5 = index_cast %arg2 : index to i32
+      %6 = index_cast %arg3 : index to i32
+      %7 = addi %arg4, %5 : i32
+      %8 = subi %7, %6 : i32
+      linalg.yield %8 : i32
     } -> tensor<?x?xi32>
-  return %1 : tensor<?x?xi32>
+  return %4 : tensor<?x?xi32>
 }
 //   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1) -> (d0, d1)>
 // CHECK-LABEL: func @indexed_generic_op_fusion
@@ -374,7 +455,7 @@ func @indexed_generic_op_fusion(%arg0: tensor<?x?xi32>) -> tensor<?x?xi32> {
 //      CHECK:   %[[ADD_OPERAND1:.+]] = index_cast %[[ARG1]] : index to i32
 //      CHECK:   %[[SUB_OPERAND1:.+]] = index_cast %[[ARG0]] : index to i32
 //      CHECK:   %[[VAL1:.+]] = addi %[[ARG2]], %[[ADD_OPERAND1]] : i32
-//      CHECK:   %[[VAL2:.+]] = subi %[[VAL1]], %[[SUB_OPERAND1]] : i32
+//      CHECK:   %[[VAL2:.+]] = subi %[[SUB_OPERAND1]], %[[VAL1]] : i32
 //      CHECK:   %[[ADD_OPERAND2:.+]] = index_cast %[[ARG0]] : index to i32
 //      CHECK:   %[[SUB_OPERAND2:.+]] = index_cast %[[ARG1]] : index to i32
 //      CHECK:   %[[VAL3:.+]] = addi %[[VAL2]], %[[ADD_OPERAND2]] : i32
@@ -389,25 +470,27 @@ func @scalar_indexed_generic_fusion
 {
   %c0 = constant 0 : index  
   %cst = constant dense<1.000000e+00> : tensor<10xf32>
-  %0 = linalg.indexed_generic
+  %0 = linalg.init_tensor [] : tensor<f32>
+  %1 = linalg.indexed_generic
     {indexing_maps = [affine_map<() -> ()>, affine_map<() -> ()>],
      iterator_types = []}
-    ins(%arg1 : tensor<i32>) {
-    ^bb0(%arg2: i32):  // no predecessors
+    ins(%arg1 : tensor<i32>) outs(%0 : tensor<f32>) {
+    ^bb0(%arg2: i32, %arg3: f32):  // no predecessors
       %3 = index_cast %arg2 : i32 to index
       %4 = tensor.extract %arg0[%3, %c0, %c0] : tensor<5x1x1xf32>
       linalg.yield %4 : f32
     } -> tensor<f32>
-  %1 = linalg.generic
+  %2 = linalg.init_tensor [10] : tensor<10xf32>
+  %3 = linalg.generic
    {indexing_maps = [affine_map<(d0) -> ()>, affine_map<(d0) -> (d0)>,
                      affine_map<(d0) -> (d0)>],
     iterator_types = ["parallel"]}
-    ins(%0, %cst : tensor<f32>, tensor<10xf32>) {
-    ^bb0(%arg2: f32, %arg3: f32):  // no predecessors
-      %3 = mulf %arg2, %arg3 : f32
-      linalg.yield %3 : f32
+    ins(%1, %cst : tensor<f32>, tensor<10xf32>) outs(%2 : tensor<10xf32>) {
+    ^bb0(%arg2: f32, %arg3: f32, %arg4: f32):  // no predecessors
+      %4 = mulf %arg2, %arg3 : f32
+      linalg.yield %4 : f32
     } -> tensor<10xf32>
-  return %1 : tensor<10xf32>
+  return %3 : tensor<10xf32>
 }
 //   CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0) -> ()>
 //   CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0) -> (d0)>
@@ -421,3 +504,35 @@ func @scalar_indexed_generic_fusion
 //       CHECK:     tensor.extract %[[ARG0]]
 //       CHECK:     linalg.yield
 //       CHECK   return %[[T0]]
+
+// -----
+
+func @constant_fusion(%arg0 : tensor<4xf32>) -> (tensor<4xf32>) {
+  %cst = constant dense<1.0> : tensor<4xf32>
+  %1 = linalg.init_tensor [4] : tensor<4xf32>
+  %2 = linalg.generic
+    {indexing_maps = [affine_map<(d0) -> (d0)>, affine_map<(d0) -> (d0)>,
+                      affine_map<(d0) -> (d0)>],
+     iterator_types = ["parallel"]}
+    ins (%arg0, %cst : tensor<4xf32>, tensor<4xf32>)
+    outs (%1 : tensor<4xf32>) {
+    ^bb0(%arg1: f32, %arg2: f32, %arg3: f32):
+      %3 = addf %arg1, %arg2 : f32
+      linalg.yield %3 : f32
+    } -> tensor<4xf32>
+  return %2 : tensor<4xf32>
+}
+
+//  CHECK-DAG: #[[MAP:.+]] = affine_map<(d0) -> (d0)>
+//      CHECK: func @constant_fusion(%[[ARG0:.+]]: tensor<4xf32>)
+//  CHECK-DAG:   %[[CST:.+]] = constant 1.000000e+00 : f32
+//  CHECK-DAG:   %[[T0:.+]] = linalg.init_tensor [4] : tensor<4xf32>
+//      CHECK:   %[[T1:.+]] = linalg.generic
+// CHECK-SAME:     indexing_maps = [#[[MAP]], #[[MAP]]]
+// CHECK-SAME:     ins(%[[ARG0]] : tensor<4xf32>)
+// CHECK-SAME:     outs(%[[T0]] : tensor<4xf32>)
+//      CHECK:   ^{{.+}}(
+// CHECK-SAME:     %[[ARG1:[a-zA-Z0-9_]+]]: f32, %[[ARG2:[a-zA-Z0-9_]+]]: f32)
+//      CHECK:     %[[T2:.+]] = addf %[[ARG1]], %[[CST]]
+//      CHECK:     linalg.yield %[[T2]]
+//      CHECK:   return %[[T1]]
diff --git a/mlir/test/Dialect/Linalg/generalize-named-ops.mlir b/mlir/test/Dialect/Linalg/generalize-named-ops.mlir
index 6db48af3b5730..c9f24844662fb 100644
--- a/mlir/test/Dialect/Linalg/generalize-named-ops.mlir
+++ b/mlir/test/Dialect/Linalg/generalize-named-ops.mlir
@@ -28,7 +28,8 @@ func @generalize_conv(%input : memref<1x225x225x3xf32>, %filter: memref<3x3x3x32
 // -----
 
 func @generalize_matmul_buffer(%A : memref<16x8xf32>, %B: memref<8x32xf32>, %C: memref<16x32xf32>) {
-  linalg.matmul ins(%A, %B: memref<16x8xf32>, memref<8x32xf32>) outs(%C: memref<16x32xf32>)
+  linalg.matmul ins(%A, %B: memref<16x8xf32>, memref<8x32xf32>)
+               outs(%C: memref<16x32xf32>)
   return
 }
 
@@ -45,7 +46,7 @@ func @generalize_matmul_buffer(%A : memref<16x8xf32>, %B: memref<8x32xf32>, %C:
 // CHECK: linalg.generic
 // CHECK-SAME: indexing_maps = [#[[A_MAP]], #[[B_MAP]], #[[C_MAP]]]
 // CHECK-SAME: iterator_types = ["parallel", "parallel", "reduction"]
-// CHECK-SAME: ins(%[[A]], %[[B]]
+// CHECK-SAME:  ins(%[[A]], %[[B]]
 // CHECK-SAME: outs(%[[C]]
 
 // CHECK: ^{{.*}}(%[[A_ARG:.+]]: f32, %[[B_ARG:.+]]: f32, %[[C_ARG:.+]]: f32)
@@ -56,15 +57,16 @@ func @generalize_matmul_buffer(%A : memref<16x8xf32>, %B: memref<8x32xf32>, %C:
 // -----
 
 func @generalize_matmul_tensor(%A : tensor<16x8xf32>, %B: tensor<8x32xf32>, %C: tensor<16x32xf32>) -> tensor<16x32xf32> {
-  %0 = linalg.matmul ins(%A, %B: tensor<16x8xf32>, tensor<8x32xf32>) init(%C: tensor<16x32xf32>) -> tensor<16x32xf32>
+  %0 = linalg.matmul ins(%A, %B: tensor<16x8xf32>, tensor<8x32xf32>)
+                    outs(%C: tensor<16x32xf32>) -> tensor<16x32xf32>
   return %0: tensor<16x32xf32>
 }
 
 // CHECK: func @generalize_matmul_tensor
 
 // CHECK: linalg.generic
-// CHECK-SAME: ins(%{{.+}}, %{{.+}} : tensor<16x8xf32>, tensor<8x32xf32>)
-// CHECK-SAME: init(%{{.+}} : tensor<16x32xf32>)
+// CHECK-SAME:  ins(%{{.+}}, %{{.+}} : tensor<16x8xf32>, tensor<8x32xf32>)
+// CHECK-SAME: outs(%{{.+}} : tensor<16x32xf32>)
 
 // CHECK:      ^{{.*}}(%[[A_ARG:.+]]: f32, %[[B_ARG:.+]]: f32, %[[C_ARG:.+]]: f32)
 // CHECK-NEXT:   %[[MUL:.+]] = mulf %[[A_ARG]], %[[B_ARG]] : f32
diff --git a/mlir/test/Dialect/Linalg/invalid.mlir b/mlir/test/Dialect/Linalg/invalid.mlir
index 8e98a80e77b19..95a663d19f0da 100644
--- a/mlir/test/Dialect/Linalg/invalid.mlir
+++ b/mlir/test/Dialect/Linalg/invalid.mlir
@@ -77,7 +77,7 @@ func @generic_wrong_dim_in_map(%arg0: memref<1xi32>) {
 // -----
 
 func @generic_one_d_view(%arg0: memref<?xf32, affine_map<(i)[off]->(off + i)>>) {
-  // expected-error @+1 {{op expected indexing_map #0 results to match view rank: 'memref<?xf32, affine_map<(d0)[s0] -> (d0 + s0)>>'}}
+  // expected-error @+1 {{expected shaped value rank (1) to match the result rank of indexing_map #0 (2)}}
   linalg.generic {
     indexing_maps =  [ affine_map<() -> (0, 0)> ],
     iterator_types = []}
@@ -143,9 +143,9 @@ func @generic_empty_region(%arg0: memref<f32>) {
 
 func @generic_empty_region(%arg0: memref<f32>) {
   %f0 = constant 0.0: f32
-  // expected-error @+1 {{linalg.generic' op expected region with 1 block}}
+  // expected-error @+1 {{linalg.generic' op expected 1 region with 1 block}}
   linalg.generic {
-    indexing_maps =  [ affine_map<() -> (0)> ],
+    indexing_maps =  [ affine_map<() -> ()> , affine_map<() -> ()> ],
     iterator_types = []}
     ins(%arg0 : memref<f32>)
    outs(%arg0 : memref<f32>) {
@@ -155,12 +155,12 @@ func @generic_empty_region(%arg0: memref<f32>) {
 // -----
 
 func @generic_mismatched_num_arguments(%arg0: memref<f32>) {
-  // expected-error @+1 {{op expected number of block arguments to match number of operands}}
+  // expected-error @+1 {{expected as many non-induction variable region arguments as the number of shaped operands}}
   linalg.generic {
-      indexing_maps =  [ affine_map<() -> (0)> ],
+      indexing_maps =  [ affine_map<() -> ()>, affine_map<() -> ()> ],
       iterator_types = []}
-      outs(%arg0 : memref<f32>) {
-    ^bb(%f: f32, %g: f32):
+      outs(%arg0, %arg0 : memref<f32>, memref<f32>) {
+    ^bb(%f: f32):
       linalg.yield %f: f32
   }
 }
@@ -168,9 +168,9 @@ func @generic_mismatched_num_arguments(%arg0: memref<f32>) {
 // -----
 
 func @generic_block_arg_type(%arg0: memref<f32>) {
-  // expected-error @+1 {{op expected block argument 1 of the same type as elemental type of output operand: 'memref<f32>'}}
+  // expected-error @+1 {{expected type of bb argument #0 ('i1') to match element type of corresponding shaped operand ('f32')}}
   linalg.generic {
-    indexing_maps =  [ affine_map<() -> (0)> ],
+    indexing_maps =  [ affine_map<() -> ()> ],
     iterator_types = []}
       outs(%arg0 : memref<f32>) {
     ^bb(%i: i1):
@@ -180,12 +180,12 @@ func @generic_block_arg_type(%arg0: memref<f32>) {
 
 // -----
 
-func @indexed_generic_block_arg_count(%arg0: memref<f32>) {
-  // expected-error @+1 {{op expected number of block arguments to match number of operands + number of loops}}
+func @indexed_generic_block_arg_count(%arg0: memref<?xf32>) {
+  // expected-error @+1 {{expected as many non-induction variable region arguments as the number of shaped operands}}
   linalg.indexed_generic {
-    indexing_maps =  [ affine_map<(d0) -> (d0)> ],
+    indexing_maps =  [ affine_map<(i) -> (i)> ],
     iterator_types = ["parallel"]}
-      outs(%arg0 : memref<f32>) {
+      outs(%arg0 : memref<?xf32>) {
     ^bb(%f: f32):
       linalg.yield %f : f32
   }
@@ -193,12 +193,12 @@ func @indexed_generic_block_arg_count(%arg0: memref<f32>) {
 
 // -----
 
-func @indexed_generic_block_induction_var_arg_type(%arg0: memref<f32>) {
-  // expected-error @+1 {{op expected block argument 1 to be an index}}
+func @indexed_generic_block_induction_var_arg_type(%arg0: memref<?xf32>) {
+  // expected-error @+1 {{op expected index block argument #0}}
   linalg.indexed_generic {
     indexing_maps =  [ affine_map<(d0) -> (d0)> ],
     iterator_types = ["parallel"]}
-      outs(%arg0 : memref<f32>) {
+      outs(%arg0 : memref<?xf32>) {
     ^bb(%i: f64, %f: f32):
     linalg.yield %f: f32
   }
@@ -206,12 +206,12 @@ func @indexed_generic_block_induction_var_arg_type(%arg0: memref<f32>) {
 
 // -----
 
-func @indexed_generic_block_arg_type(%arg0: memref<f32>) {
-  // expected-error @+1 {{op expected block argument 2 of the same type as elemental type of output operand: 'memref<f32>'}}
+func @indexed_generic_block_arg_type(%arg0: memref<?xf32>) {
+  // expected-error @+1 {{expected type of bb argument #1 ('i1') to match element type of corresponding shaped operand ('f32')}}
   linalg.indexed_generic {
     indexing_maps =  [ affine_map<(d0) -> (d0)> ],
     iterator_types = ["parallel"]}
-      outs(%arg0 : memref<f32>) {
+      outs(%arg0 : memref<?xf32>) {
     ^bb(%i: index, %f: i1):
     linalg.yield %i: index
   }
@@ -220,7 +220,7 @@ func @indexed_generic_block_arg_type(%arg0: memref<f32>) {
 // -----
 
 func @indexed_generic_arg_count(%arg0: memref<f32>) {
-  // expected-error @+1 {{op expected number of block arguments to match number of operands + number of loops}}
+  // expected-error @+1 {{expected as many non-induction variable region arguments as the number of shaped operands}}
   linalg.indexed_generic {
     indexing_maps =  [ affine_map<()[] -> ()> ],
     iterator_types = []}
@@ -233,19 +233,6 @@ func @indexed_generic_arg_count(%arg0: memref<f32>) {
 
 // -----
 
-func @indexed_generic_induction_var_arg_type(%arg0: memref<f32>) {
-  // expected-error @+1 {{op expected block argument 1 to be an index}}
-  linalg.indexed_generic {
-    iterator_types = ["parallel"],
-    indexing_maps = [ affine_map<(i) -> (i)> ]}
-      outs(%arg0 : memref<f32>) {
-    ^bb(%0: i32, %1: f32):
-      linalg.yield %1: f32
-  }
-}
-
-// -----
-
 func @indexed_generic_result_count(%arg0: memref<?xf32>) {
   // expected-error @+6 {{op expected number of yield values (1) to match the number of operands of the enclosing LinalgOp (2)}}
   linalg.indexed_generic {
@@ -273,19 +260,36 @@ func @generic_result_0_element_type(%arg0: memref<?xf32, affine_map<(i)[off]->(o
 
 // -----
 
-func @generic_result_tensor_type(%arg0: memref<?xf32, affine_map<(i)[off]->(off + i)>>) {
-  // expected-error @+1 {{op result #0 must be ranked tensor of any type values, but got 'f32'}}
+func @generic_result_tensor_type(%arg0: memref<?xf32, affine_map<(i)[off]->(off + i)>>,
+                                 %arg1: tensor<?xf32>) {
+  // expected-error @+1 {{expected type of operand #1 ('tensor<?xf32>') to match type of corresponding result ('f32')}}
   %0 = linalg.generic {
-    indexing_maps = [ affine_map<(i) -> (i)> ],
+    indexing_maps = [ affine_map<(i) -> (i)> , affine_map<(i) -> (i)> ],
     iterator_types = ["parallel"]}
-      ins(%arg0 : memref<?xf32, affine_map<(i)[off]->(off + i)>>) {
-    ^bb(%i: f32):
+       ins(%arg0 : memref<?xf32, affine_map<(i)[off]->(off + i)>>)
+      outs(%arg1 : tensor<?xf32>) {
+    ^bb(%i: f32, %j: f32):
       linalg.yield %i: f32
   } -> f32
 }
 
 // -----
 
+func @generic_result_tensor_type(%arg0: memref<?xf32, affine_map<(i)[off]->(off + i)>>,
+                                 %arg1: tensor<?xf32>) {
+  // expected-error @+1 {{unexpected output tensor expression in indexing map #0 a.k.a 'd0' is function of reduction iterator 'd0'}}
+  %0 = linalg.generic {
+    indexing_maps = [ affine_map<(i) -> (i)> , affine_map<(i) -> (i)> ],
+    iterator_types = ["reduction"]}
+       ins(%arg0 : memref<?xf32, affine_map<(i)[off]->(off + i)>>)
+      outs(%arg1 : tensor<?xf32>) {
+    ^bb(%i: f32, %j: f32):
+      linalg.yield %i: f32
+  } -> tensor<?xf32>
+}
+
+// -----
+
 func @generic(%arg0: memref<?x?xi4>) {
   // expected-error @+2 {{op expects regions to end with 'linalg.yield', found 'std.addf'}}
   // expected-note @+1 {{in custom textual format, the absence of terminator implies 'linalg.yield'}}
@@ -301,12 +305,17 @@ func @generic(%arg0: memref<?x?xi4>) {
 
 // -----
 
-func @conv_rank_limit(%arg0: memref<?xf32>, %arg1: memref<?xf32>, %arg2: memref<?xf32>) {
-  // expected-error @+1 {{expects memref ranks to be greater than 2}}
-  linalg.conv(%arg0, %arg1, %arg2) : memref<?xf32>, memref<?xf32>, memref<?xf32>
-}
-
-// -----
+// This test is currently disabled: subject to verifier ordering issues.
+// Instead, when the ranks are not greater than 2, an assertion will be triggered
+// in LinalgStructuredOps.td::ConvOp::iterator_types() for now because the
+// verifier inspects the iterator_types. This is slated to become an
+// autogenerated op in the future, alleviating the issue.
+// func @conv_rank_limit(%arg0: memref<?xf32>, %arg1: memref<?xf32>, %arg2: memref<?xf32>) {
+//   // DISABLED_expected -error @+1 {{expects memref ranks to be greater than 2}}
+//   linalg.conv(%arg0, %arg1, %arg2) : memref<?xf32>, memref<?xf32>, memref<?xf32>
+// }
+//
+// // -----
 
 // expected-error @+1 {{unknown Linalg type}}
 !invalid_type = type !linalg.unknown
@@ -367,7 +376,7 @@ func @reshape(%arg0: memref<?x?x?xf32>) {
 func @pooling_rank_mismatch(%arg0: memref<?x?x?xf32>,
                             %arg1: memref<2x3xf32>,
                             %arg2: memref<?x?x?xf32>) {
-  // expected-error @+1 {{expects memref ranks to match}}
+  // expected-error @+1 {{expected shaped value rank (2) to match the result rank of indexing_map #1 (3)}}
   linalg.pooling_max(%arg0, %arg1, %arg2) {strides = [2, 1, 2]}:
     memref<?x?x?xf32>, memref<2x3xf32>, memref<?x?x?xf32>
   return
@@ -376,7 +385,7 @@ func @pooling_rank_mismatch(%arg0: memref<?x?x?xf32>,
 // -----
 
 func @named_ops(%a3: memref<?x?x?xf32>, %b3: memref<?x?xf32>, %c3: memref<?x?x?xf32>) {
-  // expected-error @+1 {{op expected indexing_map #1 results to match view rank: 'memref<?x?xf32>'}}
+  // expected-error @+1 {{expected shaped value rank (2) to match the result rank of indexing_map #1 (3)}}
   linalg.batch_matmul ins(%a3, %b3: memref<?x?x?xf32>, memref<?x?xf32>)
                      outs(%c3 : memref<?x?x?xf32>)
   return
@@ -384,18 +393,8 @@ func @named_ops(%a3: memref<?x?x?xf32>, %b3: memref<?x?xf32>, %c3: memref<?x?x?x
 
 // -----
 
-func @empty_init_expected(%m: memref<?x?xf32>, %t: tensor<?x?xf32>) {
-  // expected-error @+1 {{expected empty `init` when op has no results or no reduction dims}}
-  linalg.matmul ins(%m, %m: memref<?x?xf32>, memref<?x?xf32>)
-               outs(%m : memref<?x?xf32>)
-               init(%t : tensor<?x?xf32>)
-  return
-}
-
-// -----
-
 func @incorrect_region_arg_count(%m: memref<?x?xf32>) {
-  // expected-error @+3 {{region expects 3 args, got 4}}
+  // expected-error @+3 {{region expects 3 args, got 2}}
   %res = linalg.matmul ins(%m, %m : memref<?x?xf32>, memref<?x?xf32>)
                        -> tensor<?x?xf32>, tensor<?x?xf32>
   return
@@ -403,30 +402,10 @@ func @incorrect_region_arg_count(%m: memref<?x?xf32>) {
 
 // -----
 
-func @single_tensor_result(%m: memref<?x?xf32>, %t: tensor<?x?xf32>) {
-  // expected-error @+1 {{expected single tensor result when reduction present}}
-  %res:2 = linalg.matmul ins(%m : memref<?x?xf32>)
-                        init(%t, %t : tensor<?x?xf32>, tensor<?x?xf32>)
-                          -> tensor<?x?xf32>, tensor<?x?xf32>
-  return
-}
-
-// -----
-
-func @matching_inits(%m: memref<?x?xf32>, %t: tensor<?x?xf32>) {
-  // expected-error @+1 {{expected #init tensors to match #results when reduction present}}
-  %res = linalg.matmul ins(%m, %m : memref<?x?xf32>, memref<?x?xf32>)
-                      init(%t, %t : tensor<?x?xf32>, tensor<?x?xf32>)
-                        -> tensor<?x?xf32>
-  return
-}
-
-// -----
-
 func @matching_inits(%m: memref<?x?xf32>, %t: tensor<?x?xf32>) {
-  // expected-error @+1 {{expected init tensor #0 of the same type as result #0}}
+  // expected-error @+1 {{expected type of operand #2 ('tensor<?x?xf32>') to match type of corresponding result ('tensor<?xf32>')}}
   %res = linalg.matmul ins(%m, %m : memref<?x?xf32>, memref<?x?xf32>)
-                      init(%t : tensor<?x?xf32>)
+                      outs(%t : tensor<?x?xf32>)
                         -> tensor<?xf32>
   return
 }
diff --git a/mlir/test/Dialect/Linalg/parallel-loops.mlir b/mlir/test/Dialect/Linalg/parallel-loops.mlir
index 95eb997f4dbda..8d365af6a5a38 100644
--- a/mlir/test/Dialect/Linalg/parallel-loops.mlir
+++ b/mlir/test/Dialect/Linalg/parallel-loops.mlir
@@ -64,7 +64,7 @@ func @lower_outer_parallel(%A: memref<?x?x?x?xf32>, %B: memref<?x?x?xf32>) {
 
 #accesses = [
   affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d2, d3, d4, d5)>,
-  affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d2, d4, d5)>
+  affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d4, d3)>
 ]
 #trait = {
   iterator_types = ["parallel", "parallel", "reduction", "parallel", "parallel", "reduction"],
@@ -94,4 +94,4 @@ func @lower_mixed_parallel(%A: memref<?x?x?x?x?x?xf32>, %B: memref<?x?x?x?xf32>)
 //       CHECK:     scf.parallel (%[[IV3:.*]], %[[IV4:.*]]) = (%[[C0]], %[[C0]]) to (%[[D3]], %[[D4]]) step (%[[C1]], %[[C1]])
 //       CHECK:       scf.for %[[IV5:.*]] = %[[C0]] to %[[D5]] step %[[C1]]
 //       CHECK:       load %{{.*}}[%[[IV0]], %[[IV1]], %[[IV2]], %[[IV3]], %[[IV4]], %[[IV5]]]
-//       CHECK:       store %{{.*}}, %{{.*}}[%[[IV0]], %[[IV2]], %[[IV4]], %[[IV5]]]
+//       CHECK:       store %{{.*}}, %{{.*}}[%[[IV0]], %[[IV1]], %[[IV4]], %[[IV3]]]
diff --git a/mlir/test/Dialect/Linalg/reshape_fusion.mlir b/mlir/test/Dialect/Linalg/reshape_fusion.mlir
index 66e07cc56d65b..92805218dde7d 100644
--- a/mlir/test/Dialect/Linalg/reshape_fusion.mlir
+++ b/mlir/test/Dialect/Linalg/reshape_fusion.mlir
@@ -1,20 +1,21 @@
-// RUN: mlir-opt %s -linalg-fusion-for-tensor-ops -split-input-file | FileCheck %s
+// RUN: mlir-opt %s -linalg-fusion-for-tensor-ops -split-input-file -verify-each=0 | FileCheck %s
 
 #map0 = affine_map<(d0, d1, d2) -> (d2, d0, d1)>
 #map1 = affine_map<(d0, d1, d2) -> (d1, d2, d0)>
-func @generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x?x?xf32>,
+func @generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x4x?xf32>,
                                          %arg1 : tensor<?x?x?xf32>) ->
                                          tensor<?x?x?xf32>
 {
   %0 = linalg.tensor_reshape %arg0 [affine_map<(i, j, k, l) -> (i)>,
                                     affine_map<(i, j, k, l) -> (j, k)>,
                                     affine_map<(i, j, k, l) -> (l)>] :
-    tensor<?x?x?x?xf32> into tensor<?x?x?xf32>
+    tensor<?x?x4x?xf32> into tensor<?x?x?xf32>
   %1 = linalg.generic {
      indexing_maps = [#map0, #map1, #map1],
      iterator_types = ["parallel", "parallel", "parallel"]}
-      ins(%0, %arg1 : tensor<?x?x?xf32>, tensor<?x?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
+       ins(%0, %arg1 : tensor<?x?x?xf32>, tensor<?x?x?xf32>)
+      outs(%0 : tensor<?x?x?xf32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %s: f32):       // no predecessors
       %1 = mulf %arg3, %arg4 : f32
       linalg.yield %1 : f32
   } -> tensor<?x?x?xf32>
@@ -22,44 +23,58 @@ func @generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x?x?xf32>,
 }
 
 //  CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3) -> (d0)>
-//  CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3) -> (d1)>
-//  CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2, d3) -> (d2, d3)>
-//  CHECK-DAG: #[[MAP3:.+]] = affine_map<(d0, d1, d2, d3) -> (d3, d0, d1, d2)>
-//  CHECK-DAG: #[[MAP4:.+]] = affine_map<(d0, d1, d2, d3) -> (d2, d3, d0, d1)>
+//  CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3) -> (d1, d2)>
+//  CHECK-DAG: #[[MAP2:.+]] = affine_map<(d0, d1, d2, d3) -> (d3)>
+//  CHECK-DAG: #[[MAP3:.+]] = affine_map<(d0, d1, d2, d3) -> (d1)>
+//  CHECK-DAG: #[[MAP4:.+]] = affine_map<(d0, d1, d2, d3) -> (d2, d3)>
+//  CHECK-DAG: #[[MAP5:.+]] = affine_map<(d0, d1, d2, d3) -> (d3, d0, d1, d2)>
+//  CHECK-DAG: #[[MAP6:.+]] = affine_map<(d0, d1, d2, d3) -> (d2, d3, d0, d1)>
 //      CHECK: func @generic_op_reshape_producer_fusion
-// CHECK-SAME:   %[[ARG0:[a-zA-Z0-9_]+]]: tensor<?x?x?x?xf32>
+// CHECK-SAME:   %[[ARG0:[a-zA-Z0-9_]+]]: tensor<?x?x4x?xf32>
 // CHECK-SAME:   %[[ARG1:[a-zA-Z0-9_]+]]: tensor<?x?x?xf32>
-//      CHECK:   %[[T0:.+]] = linalg.tensor_reshape %[[ARG1]]
+//  CHECK-DAG:   %[[C0:.+]] = constant 0 : index
+//  CHECK-DAG:   %[[C1:.+]] = constant 1 : index
+//  CHECK-DAG:   %[[C2:.+]] = constant 2 : index
+//  CHECK-DAG:   %[[C4:.+]] = constant 4 : index
+//      CHECK:   %[[T0:.+]] = linalg.tensor_reshape %[[ARG0]]
 // CHECK-SAME:     [#[[MAP0]], #[[MAP1]], #[[MAP2]]]
-// CHECK-SAME:     tensor<?x?x?xf32> into tensor<?x?x?x?xf32>
-//      CHECK:   %[[T1:.+]] = linalg.generic
-// CHECK-SAME:     indexing_maps = [#[[MAP3]], #[[MAP4]], #[[MAP4]]]
+//      CHECK:   %[[T1:.+]] = linalg.tensor_reshape %[[ARG1]]
+// CHECK-SAME:     [#[[MAP0]], #[[MAP3]], #[[MAP4]]]
+//  CHECK-DAG:   %[[D0:.+]] = dim %[[T0]], %[[C0]]
+//  CHECK-DAG:   %[[D1:.+]] = dim %[[T0]], %[[C1]]
+//  CHECK-DAG:   %[[D2:.+]] = dim %[[T0]], %[[C2]]
+//      CHECK:   %[[D3:.+]] = divi_unsigned %[[D0]], %[[C4]]
+//      CHECK:   %[[T2:.+]] = linalg.init_tensor [%[[D1]], %[[D2]], %[[D3]], 4]
+//      CHECK:   %[[T3:.+]] = linalg.generic
+// CHECK-SAME:     indexing_maps = [#[[MAP5]], #[[MAP6]], #[[MAP6]]]
 // CHECK-SAME:     ["parallel", "parallel", "parallel", "parallel"]
-// CHECK-SAME:     ins(%[[ARG0]], %[[T0]] : tensor<?x?x?x?xf32>, tensor<?x?x?x?xf32>)
-//      CHECK:   %[[T2:.+]] = linalg.tensor_reshape
-// CHECK-SAME:     [#[[MAP0]], #[[MAP1]], #[[MAP2]]]
-// CHECK-SAME:     tensor<?x?x?x?xf32> into tensor<?x?x?xf32>
-//      CHECK:   return %[[T2]]
+// CHECK-SAME:     ins(%[[ARG0]], %[[T1]] : tensor<?x?x4x?xf32>, tensor<?x?x?x4xf32>)
+// CHECK-SAME:     outs(%[[T2]] : tensor<?x?x?x4xf32>)
+//      CHECK:   %[[T4:.+]] = linalg.tensor_reshape %[[T3]]
+// CHECK-SAME:     [#[[MAP0]], #[[MAP3]], #[[MAP4]]]
+// CHECK-SAME:     tensor<?x?x?x4xf32> into tensor<?x?x?xf32>
+//      CHECK:   return %[[T4]]
 
 // -----
 
 #map0 = affine_map<(d0, d1) -> (d0, d1)>
 func @generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?xf32>,
                                          %arg1 : tensor<?x?xf32>) ->
-                                         tensor<?x?x4x5xf32>
+                                         tensor<?x4x?x5xf32>
 {
   %0 = linalg.generic {
      indexing_maps = [#map0, #map0, #map0],
      iterator_types = ["parallel", "parallel"]}
-      ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
+       ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%arg0 : tensor<?x?xf32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %s: f32):       // no predecessors
       %1 = mulf %arg3, %arg4 : f32
       linalg.yield %1 : f32
   } -> tensor<?x?xf32>
   %1 = linalg.tensor_reshape %0 [affine_map<(i, j, k, l) -> (i)>,
                                  affine_map<(i, j, k, l) -> (j, k, l)>] :
-    tensor<?x?xf32> into tensor<?x?x4x5xf32>
-  return %1 : tensor<?x?x4x5xf32>
+    tensor<?x?xf32> into tensor<?x4x?x5xf32>
+  return %1 : tensor<?x4x?x5xf32>
 }
 
 //  CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3) -> (d0)>
@@ -68,31 +83,40 @@ func @generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?xf32>,
 //      CHECK: func @generic_op_reshape_consumer_fusion
 // CHECK-SAME:   %[[ARG0:[a-zA-Z0-9_]+]]: tensor<?x?xf32>
 // CHECK-SAME:   %[[ARG1:[a-zA-Z0-9_]+]]: tensor<?x?xf32>
+//  CHECK-DAG:   %[[C0:.+]] = constant 0 : index
+//  CHECK-DAG:   %[[C1:.+]] = constant 1 : index
+//  CHECK-DAG:   %[[C20:.+]] = constant 20 : index
 //      CHECK:   %[[T0:.+]] = linalg.tensor_reshape %[[ARG0]]
 // CHECK-SAME:     [#[[MAP0]], #[[MAP1]]]
-// CHECK-SAME:     tensor<?x?xf32> into tensor<?x?x4x5xf32>
+// CHECK-SAME:     tensor<?x?xf32> into tensor<?x4x?x5xf32>
 //      CHECK:   %[[T1:.+]] = linalg.tensor_reshape %[[ARG1]]
 // CHECK-SAME:     [#[[MAP0]], #[[MAP1]]]
-// CHECK-SAME:     tensor<?x?xf32> into tensor<?x?x4x5xf32>
-//      CHECK:   %[[T2:.+]] = linalg.generic
+// CHECK-SAME:     tensor<?x?xf32> into tensor<?x4x?x5xf32>
+//  CHECK-DAG:   %[[D0:.+]] = dim %[[ARG0]], %[[C0]]
+//  CHECK-DAG:   %[[D1:.+]] = dim %[[ARG0]], %[[C1]]
+//      CHECK:   %[[D2:.+]] = divi_unsigned %[[D1]], %[[C20]]
+//      CHECK:   %[[T2:.+]] = linalg.init_tensor [%[[D0]], 4, %[[D2]], 5]
+//      CHECK:   %[[T3:.+]] = linalg.generic
 // CHECK-SAME:     indexing_maps = [#[[MAP2]], #[[MAP2]], #[[MAP2]]]
 // CHECK-SAME:     ["parallel", "parallel", "parallel", "parallel"]
-// CHECK-SAME:     ins(%[[T0]], %[[T1]] : tensor<?x?x4x5xf32>, tensor<?x?x4x5xf32>)
-//      CHECK:   return %[[T2]] : tensor<?x?x4x5xf32>
+// CHECK-SAME:     ins(%[[T0]], %[[T1]] : tensor<?x4x?x5xf32>, tensor<?x4x?x5xf32>)
+// CHECK-SAME:     outs(%[[T2]] : tensor<?x4x?x5xf32>)
+//      CHECK:   return %[[T3]] : tensor<?x4x?x5xf32>
 
 
 // -----
 
 func @reshape_as_consumer_permutation
   (%a : tensor<?x?x?xf32>, %b : tensor<?x?xf32>)
-    -> tensor<?x?x?x?x?x?xf32> {
+    -> tensor<?x2x?x3x4x?xf32> {
   %c = linalg.generic {
          indexing_maps = [affine_map<(d0, d1, d2) -> (d1, d0, d2)>,
                           affine_map<(d0, d1, d2) -> (d1, d2)>,
                           affine_map<(d0, d1, d2) -> (d0, d2, d1)>],
          iterator_types = ["parallel", "parallel", "parallel"]}
-         ins(%a, %b : tensor<?x?x?xf32>, tensor<?x?xf32>) {
-       ^bb0(%arg0 : f32, %arg1: f32):
+          ins(%a, %b : tensor<?x?x?xf32>, tensor<?x?xf32>)
+         outs(%a : tensor<?x?x?xf32>) {
+       ^bb0(%arg0 : f32, %arg1: f32, %s: f32):
          %1 = addf %arg0, %arg1 : f32
          linalg.yield %1 : f32
        } -> tensor<?x?x?xf32>
@@ -100,8 +124,8 @@ func @reshape_as_consumer_permutation
          [affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1)>,
           affine_map<(d0, d1, d2, d3, d4, d5) -> (d2)>,
           affine_map<(d0, d1, d2, d3, d4, d5) -> (d3, d4, d5)>]
-       : tensor<?x?x?xf32> into tensor<?x?x?x?x?x?xf32>
-  return %d : tensor<?x?x?x?x?x?xf32>
+       : tensor<?x?x?xf32> into tensor<?x2x?x3x4x?xf32>
+  return %d : tensor<?x2x?x3x4x?xf32>
 }
 //  CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d0, d1, d2)>
 //  CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2, d3, d4, d5) -> (d3, d4)>
@@ -114,17 +138,28 @@ func @reshape_as_consumer_permutation
 //      CHECK: func @reshape_as_consumer_permutation
 // CHECK-SAME:   %[[ARG0:[a-zA-Z0-9_]+]]: tensor<?x?x?xf32>
 // CHECK-SAME:   %[[ARG1:[a-zA-Z0-9_]+]]: tensor<?x?xf32>
+//  CHECK-DAG:   %[[C0:.+]] = constant 0 : index
+//  CHECK-DAG:   %[[C1:.+]] = constant 1 : index
+//  CHECK-DAG:   %[[C2:.+]] = constant 2 : index
+//  CHECK-DAG:   %[[C12:.+]] = constant 12 : index
 //      CHECK:   %[[T0:.+]] = linalg.tensor_reshape %[[ARG0]]
 // CHECK-SAME:     [#[[MAP0]], #[[MAP1]], #[[MAP2]]]
-// CHECK-SAME:     tensor<?x?x?xf32> into tensor<?x?x?x?x?x?xf32>
+// CHECK-SAME:     tensor<?x?x?xf32> into tensor<3x4x?x?x2x?xf32>
 //      CHECK:   %[[T1:.+]] = linalg.tensor_reshape %[[ARG1]]
 // CHECK-SAME:     [#[[MAP3]], #[[MAP4]]]
-// CHECK-SAME:     tensor<?x?xf32> into tensor<?x?x?x?xf32>
-//      CHECK:   %[[T2:.+]] = linalg.generic
+// CHECK-SAME:     tensor<?x?xf32> into tensor<3x4x?x?xf32>
+//  CHECK-DAG:   %[[D0:.+]] = dim %[[ARG0]], %[[C0]]
+//      CHECK:   %[[D1:.+]] = divi_unsigned %[[D0]], %[[C2]]
+//  CHECK-DAG:   %[[D2:.+]] = dim %[[ARG0]], %[[C2]]
+//  CHECK-DAG:   %[[D3:.+]] = dim %[[ARG0]], %[[C1]]
+//  CHECK-DAG:   %[[D4:.+]] = divi_unsigned %[[D3]], %[[C12]]
+//      CHECK:   %[[T2:.+]] = linalg.init_tensor [%[[D1]], 2, %[[D2]], 3, 4, %[[D4]]]
+//      CHECK:   %[[T3:.+]] = linalg.generic
 // CHECK-SAME:     indexing_maps = [#[[MAP5]], #[[MAP6]], #[[MAP7]]]
 // CHECK-SAME:     ["parallel", "parallel", "parallel", "parallel", "parallel", "parallel"]
-// CHECK-SAME:     ins(%[[T0]], %[[T1]] : tensor<?x?x?x?x?x?xf32>, tensor<?x?x?x?xf32>)
-//      CHECK:   return %[[T2]] : tensor<?x?x?x?x?x?xf32>
+// CHECK-SAME:     ins(%[[T0]], %[[T1]] : tensor<3x4x?x?x2x?xf32>, tensor<3x4x?x?xf32>)
+// CHECK-SAME:     outs(%[[T2]] : tensor<?x2x?x3x4x?xf32>)
+//      CHECK:   return %[[T3]] : tensor<?x2x?x3x4x?xf32>
 
 // -----
 
@@ -138,8 +173,9 @@ func @generic_op_reshape_consumer_static(%arg0: tensor<264x4xf32>)
   %0 = linalg.generic {
      indexing_maps = [#map0, #map0, #map0],
      iterator_types = ["parallel", "parallel"]}
-      ins(%arg0, %cst : tensor<264x4xf32>, tensor<264x4xf32>) {
-    ^bb0(%arg1: f32, %arg2: f32):  // no predecessors
+       ins(%arg0, %cst : tensor<264x4xf32>, tensor<264x4xf32>)
+      outs(%arg0 : tensor<264x4xf32>) {
+    ^bb0(%arg1: f32, %arg2: f32, %s: f32):  // no predecessors
       %2 = mulf %arg1, %arg2 : f32
       linalg.yield %2 : f32
     } -> tensor<264x4xf32>
@@ -156,21 +192,27 @@ func @generic_op_reshape_consumer_static(%arg0: tensor<264x4xf32>)
 //      CHECK:   %[[T0:.+]] = linalg.tensor_reshape %[[ARG0]]
 // CHECK-SAME:     [#[[MAP0]], #[[MAP1]]]
 // CHECK-SAME:     tensor<264x4xf32> into tensor<8x33x4xf32>
-//      CHECK:   %[[T1:.+]] = linalg.generic
+//      CHECK:   %[[T1:.+]] = linalg.init_tensor [8, 33, 4] : tensor<8x33x4xf32>
+//      CHECK:   %[[T2:.+]] = linalg.generic
 // CHECK-SAME:     indexing_maps = [#[[MAP2]], #[[MAP2]]]
 // CHECK-SAME:     ["parallel", "parallel", "parallel"]
 // CHECK-SAME:     ins(%[[T0]] : tensor<8x33x4xf32>)
-//      CHECK:   return %[[T1]] : tensor<8x33x4xf32>
+// CHECK-SAME:     outs(%[[T1]] : tensor<8x33x4xf32>)
+//      CHECK:   return %[[T2]] : tensor<8x33x4xf32>
 
 // -----
 
-func @scalar_reshape(%arg0 : tensor<1x10xf32>, %arg1 : tensor<1xf32>)
-                     -> tensor<1x10xf32> {
+func @scalar_reshape(
+  %arg0 : tensor<1x10xf32>, %arg1 : tensor<1xf32>, %shape : tensor<10xf32>)
+    -> tensor<1x10xf32>
+{
   %0 = linalg.tensor_reshape %arg1 [] : tensor<1xf32> into tensor<f32>
   %1 = linalg.generic
     {indexing_maps = [affine_map<(d0) -> ()>, affine_map<(d0) -> (d0)>],
-     iterator_types = ["parallel"]} ins(%0 : tensor<f32>) {
-  ^bb0(%arg2: f32):  // no predecessors
+     iterator_types = ["parallel"]}
+     ins(%0 : tensor<f32>)
+    outs(%shape : tensor<10xf32>) {
+  ^bb0(%arg2: f32, %s: f32):  // no predecessors
     linalg.yield %arg2 : f32
   } -> tensor<10xf32>
   %2 = linalg.tensor_reshape %1 [affine_map<(d0, d1) -> (d0, d1)>]
@@ -185,11 +227,13 @@ func @scalar_reshape(%arg0 : tensor<1x10xf32>, %arg1 : tensor<1xf32>)
 // CHECK-SAME:   %[[ARG1:[a-zA-Z0-9_]+]]: tensor<1xf32>
 //      CHECK:   %[[T0:.+]] = linalg.tensor_reshape %[[ARG1]] []
 // CHECK-SAME:     tensor<1xf32> into tensor<f32>
-//      CHECK:   %[[T1:.+]] = linalg.generic
+//      CHECK:   %[[T1:.+]] = linalg.init_tensor [1, 10] : tensor<1x10xf32>
+//      CHECK:   %[[T2:.+]] = linalg.generic
 // CHECK-SAME:     indexing_maps = [#[[MAP0]], #[[MAP1]]]
 // CHECK-SAME:     iterator_types = ["parallel", "parallel"]
 // CHECK-SAME:     ins(%[[T0]] : tensor<f32>)
-//      CHECK:   return %[[T1]] : tensor<1x10xf32>
+// CHECK-SAME:     outs(%[[T1]] : tensor<1x10xf32>)
+//      CHECK:   return %[[T2]] : tensor<1x10xf32>
 
 // -----
 
@@ -206,8 +250,9 @@ func @indexed_generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x4x?xi32>,
   %1 = linalg.indexed_generic {
      indexing_maps = [#map0, #map1, #map1],
      iterator_types = ["parallel", "parallel", "parallel"]}
-      ins(%0, %arg1 : tensor<?x?x?xi32>, tensor<?x?x?xi32>) {
-    ^bb0(%arg3 : index, %arg4 : index, %arg5 : index, %arg6: i32, %arg7: i32):
+       ins(%0, %arg1 : tensor<?x?x?xi32>, tensor<?x?x?xi32>)
+      outs(%0 : tensor<?x?x?xi32>) {
+    ^bb0(%arg3 : index, %arg4 : index, %arg5 : index, %arg6: i32, %arg7: i32, %s: i32):
       %1 = muli %arg6, %arg7 : i32
       %2 = index_cast %arg3 : index to i32
       %3 = addi %1, %2 : i32
@@ -228,7 +273,8 @@ func @indexed_generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x4x?xi32>,
 //       CHECK:   ^{{.*}}(
 //  CHECK-SAME:     %[[ARG2:[a-zA-Z0-9]+]]: index, %[[ARG3:[a-zA-Z0-9]+]]: index,
 //  CHECK-SAME:     %[[ARG4:[a-zA-Z0-9]+]]: index, %[[ARG5:[a-zA-Z0-9]+]]: index,
-//  CHECK-SAME:     %[[ARG6:[a-zA-Z0-9]+]]: i32, %[[ARG7:[a-zA-Z0-9]+]]: i32)
+//  CHECK-SAME:     %[[ARG6:[a-zA-Z0-9]+]]: i32, %[[ARG7:[a-zA-Z0-9]+]]: i32,
+//  CHECK-SAME:     %[[ARG8:[a-zA-Z0-9]+]]: i32)
 //       CHECK:     %[[T3:.+]] = affine.apply #[[MAP]](%[[ARG2]], %[[ARG3]])
 //       CHECK:     %[[T4:.+]] = muli %[[ARG6]], %[[ARG7]]
 //       CHECK:     %[[T5:.+]] = index_cast %[[T3]]
@@ -249,8 +295,9 @@ func @indexed_generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?xi32>,
   %0 = linalg.indexed_generic {
      indexing_maps = [#map0, #map0, #map0],
      iterator_types = ["parallel", "parallel"]}
-      ins(%arg0, %arg1 : tensor<?x?xi32>, tensor<?x?xi32>) {
-    ^bb0(%arg3 : index, %arg4 : index, %arg5: i32, %arg6: i32):       // no predecessors
+       ins(%arg0, %arg1 : tensor<?x?xi32>, tensor<?x?xi32>)
+      outs(%arg0 : tensor<?x?xi32>) {
+    ^bb0(%arg3 : index, %arg4 : index, %arg5: i32, %arg6: i32, %s: i32):       // no predecessors
       %1 = muli %arg5, %arg6 : i32
       %2 = index_cast %arg3 : index to i32
       %3 = addi %1, %2 : i32
@@ -271,7 +318,8 @@ func @indexed_generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?xi32>,
 //       CHECK:   ^{{.*}}(
 //  CHECK-SAME:     %[[ARG2:[a-zA-Z0-9]+]]: index, %[[ARG3:[a-zA-Z0-9]+]]: index,
 //  CHECK-SAME:     %[[ARG4:[a-zA-Z0-9]+]]: index, %[[ARG5:[a-zA-Z0-9]+]]: index,
-//  CHECK-SAME:     %[[ARG6:[a-zA-Z0-9]+]]: i32, %[[ARG7:[a-zA-Z0-9]+]]: i32)
+//  CHECK-SAME:     %[[ARG6:[a-zA-Z0-9]+]]: i32, %[[ARG7:[a-zA-Z0-9]+]]: i32,
+//  CHECK-SAME:     %[[ARG8:[a-zA-Z0-9]+]]: i32)
 //       CHECK:     %[[T3:.+]] = affine.apply #[[MAP]](%[[ARG3]], %[[ARG4]], %[[ARG5]])
 //       CHECK:     %[[T4:.+]] = muli %[[ARG6]], %[[ARG7]]
 //       CHECK:     %[[T5:.+]] = index_cast %[[ARG2]]
@@ -283,15 +331,16 @@ func @indexed_generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?xi32>,
 // -----
 
 func @reshape_as_consumer_permutation
-  (%a : tensor<210x6x4xi32>, %b : tensor<210x4xi32>)
+  (%a : tensor<210x6x4xi32>, %b : tensor<210x4xi32>, %shape : tensor<6x4x210xi32>)
     -> tensor<2x3x4x5x6x7xi32> {
   %c = linalg.indexed_generic {
          indexing_maps = [affine_map<(d0, d1, d2) -> (d1, d0, d2)>,
                           affine_map<(d0, d1, d2) -> (d1, d2)>,
                           affine_map<(d0, d1, d2) -> (d0, d2, d1)>],
          iterator_types = ["parallel", "parallel", "parallel"]}
-         ins(%a, %b : tensor<210x6x4xi32>, tensor<210x4xi32>) {
-       ^bb0(%arg0 : index, %arg1 : index, %arg2 : index, %arg3 : i32, %arg4: i32):
+          ins(%a, %b : tensor<210x6x4xi32>, tensor<210x4xi32>)
+         outs(%shape : tensor<6x4x210xi32>) {
+       ^bb0(%arg0 : index, %arg1 : index, %arg2 : index, %arg3 : i32, %arg4: i32, %s: i32):
          %1 = addi %arg3, %arg4 : i32
          %2 = index_cast %arg0 : index to i32
          %3 = addi %1, %2 : i32
@@ -327,36 +376,42 @@ func @reshape_as_consumer_permutation
 //  CHECK-SAME:     [#[[MAP0]], #[[MAP1]], #[[MAP2]]]
 //   CHECK-DAG:   %[[T1:.+]] = linalg.tensor_reshape %[[ARG1]]
 //  CHECK-SAME:     [#[[MAP3]], #[[MAP4]]]
-//       CHECK:   %[[T2:.+]] = linalg.indexed_generic
+//       CHECK:   %[[T2:.+]] = linalg.init_tensor [2, 3, 4, 5, 6, 7]
+//       CHECK:   %[[T3:.+]] = linalg.indexed_generic
 //  CHECK-SAME:     indexing_maps = [#[[MAP7]], #[[MAP8]], #[[MAP9]]]
-//  CHECK-SAME:     ins(%[[T0]], %[[T1]] : tensor<{{.+}}>, tensor<{{.+}}>)
+//  CHECK-SAME:     ins(%[[T0]], %[[T1]] : tensor<5x6x7x2x3x4xi32>, tensor<5x6x7x4xi32>)
+//  CHECK-SAME:     outs(%[[T2]] : tensor<2x3x4x5x6x7xi32>)
 //       CHECK:   ^{{.+}}(
 //  CHECK-SAME:     %[[ARG2:[a-zA-Z0-9]+]]: index, %[[ARG3:[a-zA-Z0-9]+]]: index,
 //  CHECK-SAME:     %[[ARG4:[a-zA-Z0-9]+]]: index, %[[ARG5:[a-zA-Z0-9]+]]: index,
 //  CHECK-SAME:     %[[ARG6:[a-zA-Z0-9]+]]: index, %[[ARG7:[a-zA-Z0-9]+]]: index,
-//  CHECK-SAME:     %[[ARG8:[a-zA-Z0-9]+]]: i32, %[[ARG9:[a-zA-Z0-9]+]]: i32)
-//   CHECK-DAG:       %[[T3:.+]] = affine.apply #[[MAP5]](%[[ARG2]], %[[ARG3]])
-//   CHECK-DAG:       %[[T4:.+]] = affine.apply #[[MAP6]](%[[ARG4]], %[[ARG5]], %[[ARG6]])
-//   CHECK-DAG:       %[[T5:.+]] = addi %[[ARG8]], %[[ARG9]]
-//       CHECK:       %[[T6:.+]] = index_cast %[[T3]]
-//       CHECK:       %[[T7:.+]] = addi %[[T5]], %[[T6]]
-//       CHECK:       %[[T8:.+]] = index_cast %[[T4]]
-//       CHECK:       %[[T9:.+]] = addi %[[T7]], %[[T8]]
-//       CHECK:       %[[T10:.+]] = index_cast %[[ARG7]]
-//       CHECK:       %[[T11:.+]] = addi %[[T9]], %[[T10]]
+//  CHECK-SAME:     %[[ARG8:[a-zA-Z0-9]+]]: i32, %[[ARG9:[a-zA-Z0-9]+]]: i32,
+//  CHECK-SAME:     %[[ARG10:[a-zA-Z0-9]+]]: i32)
+//   CHECK-DAG:       %[[T4:.+]] = affine.apply #[[MAP5]](%[[ARG2]], %[[ARG3]])
+//   CHECK-DAG:       %[[T5:.+]] = affine.apply #[[MAP6]](%[[ARG4]], %[[ARG5]], %[[ARG6]])
+//   CHECK-DAG:       %[[T6:.+]] = addi %[[ARG8]], %[[ARG9]]
+//       CHECK:       %[[T7:.+]] = index_cast %[[T4]]
+//       CHECK:       %[[T8:.+]] = addi %[[T6]], %[[T7]]
+//       CHECK:       %[[T9:.+]] = index_cast %[[T5]]
+//       CHECK:       %[[T10:.+]] = addi %[[T8]], %[[T9]]
+//       CHECK:       %[[T11:.+]] = index_cast %[[ARG7]]
+//       CHECK:       %[[T12:.+]] = addi %[[T10]], %[[T11]]
 
 // -----
 
-func @reshape_as_producer_projected_permutation
-  (%arg0 : tensor<33x8x?xi32>) -> tensor<264x?x4xi32> {
+func @reshape_as_producer_projected_permutation(
+    %arg0 : tensor<33x8x?xi32>, %shape : tensor<264x?x4xi32>) -> tensor<264x?x4xi32>
+{
   %0 = linalg.tensor_reshape %arg0 [affine_map<(d0, d1, d2) -> (d0, d1)>,
                                     affine_map<(d0, d1, d2) -> (d2)>]
     : tensor<33x8x?xi32> into tensor<264x?xi32>
   %1 = linalg.indexed_generic
     {indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d1)>,
                       affine_map<(d0, d1, d2) -> (d0, d1, d2)>],
-     iterator_types = ["parallel", "parallel", "parallel"]} ins(%0 : tensor<264x?xi32>) {
-  ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: i32):  // no predecessors
+     iterator_types = ["parallel", "parallel", "parallel"]}
+     ins(%0 : tensor<264x?xi32>)
+    outs(%shape : tensor<264x?x4xi32>) {
+  ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: i32, %s: i32):  // no predecessors
     %2 = index_cast %arg1 : index to i32
     %3 = addi %arg4, %2 : i32
     %4 = index_cast %arg2 : index to i32
@@ -384,7 +439,8 @@ func @reshape_as_producer_projected_permutation
 //  CHECK-SAME:     %[[ARG2:[a-zA-Z0-9]+]]: index,
 //  CHECK-SAME:     %[[ARG3:[a-zA-Z0-9]+]]: index,
 //  CHECK-SAME:     %[[ARG4:[a-zA-Z0-9]+]]: index,
-//  CHECK-SAME:     %[[ARG5:[a-zA-Z0-9]+]]: i32)
+//  CHECK-SAME:     %[[ARG5:[a-zA-Z0-9]+]]: i32,
+//  CHECK-SAME:     %[[ARG7:[a-zA-Z0-9]+]]: i32)
 //       CHECK:       %[[T0:.+]] = affine.apply #[[MAP2]](%[[ARG1]], %[[ARG2]])
 //       CHECK:       %[[T1:.+]] = index_cast %[[T0]] : index to i32
 //       CHECK:       %[[T2:.+]] = addi %[[ARG5]], %[[T1]] : i32
@@ -409,8 +465,9 @@ func @generic_op_reshape_consumer_fusion_projected(%arg0 : tensor<?x?xf32>,
   %0 = linalg.generic {
      indexing_maps = [#map0, #map0, #map1],
      iterator_types = ["parallel", "parallel"]}
-      ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
+       ins(%arg0, %arg1 : tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%arg0 : tensor<?x?xf32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %s: f32):       // no predecessors
       %1 = mulf %arg3, %arg4 : f32
       linalg.yield %1 : f32
   } -> tensor<?x?xf32>
diff --git a/mlir/test/Dialect/Linalg/reshape_linearization_fusion.mlir b/mlir/test/Dialect/Linalg/reshape_linearization_fusion.mlir
index 468ae80a1288b..aff1447a63c7b 100644
--- a/mlir/test/Dialect/Linalg/reshape_linearization_fusion.mlir
+++ b/mlir/test/Dialect/Linalg/reshape_linearization_fusion.mlir
@@ -1,9 +1,5 @@
 // RUN: mlir-opt -split-input-file -linalg-fold-reshape-ops-by-linearization %s | FileCheck %s
 
-
-// CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1 * 4 + d2, d3)>
-// CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
-
 #map0 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 func @generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x?xf32>,
                                          %arg1 : tensor<?x?x4x?xf32>) ->
@@ -14,37 +10,39 @@ func @generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x?xf32>,
                                     affine_map<(i, j, k, l) -> (l)>] :
     tensor<?x?x?xf32> into tensor<?x?x4x?xf32>
   %1 = linalg.generic {
-     indexing_maps = [#map0, #map0, #map0],
-     iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
-      ins(%0, %arg1 : tensor<?x?x4x?xf32>, tensor<?x?x4x?xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
+    indexing_maps = [#map0, #map0, #map0],
+    iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
+    ins(%0, %arg1 : tensor<?x?x4x?xf32>, tensor<?x?x4x?xf32>)
+    outs(%0 : tensor<?x?x4x?xf32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       // no predecessors
       %1 = mulf %arg3, %arg4 : f32
       linalg.yield %1 : f32
   } -> tensor<?x?x4x?xf32>
   return %1 : tensor<?x?x4x?xf32>
 }
 
-// CHECK-LABEL: func @generic_op_reshape_producer_fusion
+//   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1 * 4 + d2, d3)>
+//   CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
+//       CHECK: func @generic_op_reshape_producer_fusion
+//  CHECK-SAME:   %[[ARG0:.+]]: tensor<?x?x?xf32>
 //       CHECK: linalg.generic
 //  CHECK-SAME:   indexing_maps = [#[[$MAP0]], #[[$MAP1]], #[[$MAP1]]]
-//   CHECK-NOT: linalg.generic
-
+//  CHECK-SAME:   ins(%[[ARG0]], %{{.+}} : tensor<?x?x?xf32>, tensor<?x?x4x?xf32>)
+//  CHECK-SAME:   outs(%{{.+}} : tensor<?x?x4x?xf32>)
 
 // -----
 
-// CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
-// CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1 * 20 + d2 * 5 + d3)>
-
 #map0 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 func @generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?x4x5xf32>,
                                          %arg1 : tensor<?x?x4x5xf32>) ->
                                          tensor<?x?xf32>
 {
   %0 = linalg.generic {
-     indexing_maps = [#map0, #map0, #map0],
-     iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
-      ins(%arg0, %arg1 : tensor<?x?x4x5xf32>, tensor<?x?x4x5xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
+    indexing_maps = [#map0, #map0, #map0],
+    iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
+    ins(%arg0, %arg1 : tensor<?x?x4x5xf32>, tensor<?x?x4x5xf32>)
+    outs(%arg0 : tensor<?x?x4x5xf32>){
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       // no predecessors
       %1 = mulf %arg3, %arg4 : f32
       linalg.yield %1 : f32
   } -> tensor<?x?x4x5xf32>
@@ -54,10 +52,21 @@ func @generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?x4x5xf32>,
   return %1 : tensor<?x?xf32>
 }
 
-// CHECK-LABEL: func @generic_op_reshape_consumer_fusion
-//       CHECK: linalg.generic
-//  CHECK-SAME:   indexing_maps = [#[[$MAP0]], #[[$MAP0]], #[[$MAP1]]]
-//   CHECK-NOT: linalg.generic
+
+//   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
+//   CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1 * 20 + d2 * 5 + d3)>
+//       CHECK: func @generic_op_reshape_consumer_fusion
+//  CHECK-SAME:   %[[ARG0:[a-zA-Z0-9_]+]]: tensor<?x?x4x5xf32>
+//   CHECK-DAG:   %[[C0:.+]] = constant 0 : index
+//   CHECK-DAG:   %[[C1:.+]] = constant 1 : index
+//   CHECK-DAG:   %[[C20:.+]] = constant 20 : index
+//       CHECK:   %[[T0:.+]] = dim %[[ARG0]], %[[C0]]
+//       CHECK:   %[[T1:.+]] = dim %[[ARG0]], %[[C1]]
+//       CHECK:   %[[T2:.+]] = muli %[[T1]], %[[C20]]
+//       CHECK:   %[[T3:.+]] = linalg.init_tensor [%[[T0]], %[[T2]]]
+//       CHECK:   linalg.generic
+//  CHECK-SAME:     indexing_maps = [#[[$MAP0]], #[[$MAP0]], #[[$MAP1]]]
+//  CHECK-SAME:     outs(%[[T3]] : tensor<?x?xf32>)
 
 // -----
 
@@ -69,8 +78,9 @@ func @generic_op_reshape_consumer_nofusion(%arg0 : tensor<?x?x?x5xf32>,
   %0 = linalg.generic {
      indexing_maps = [#map0, #map0, #map0],
      iterator_types = ["parallel", "parallel", "parallel", "parallel"]}
-      ins(%arg0, %arg1 : tensor<?x?x?x5xf32>, tensor<?x?x?x5xf32>) {
-    ^bb0(%arg3: f32, %arg4: f32):       // no predecessors
+      ins(%arg0, %arg1 : tensor<?x?x?x5xf32>, tensor<?x?x?x5xf32>)
+      outs(%arg0 : tensor<?x?x?x5xf32>) {
+    ^bb0(%arg3: f32, %arg4: f32, %arg5: f32):       // no predecessors
       %1 = mulf %arg3, %arg4 : f32
       linalg.yield %1 : f32
   } -> tensor<?x?x?x5xf32>
@@ -81,14 +91,11 @@ func @generic_op_reshape_consumer_nofusion(%arg0 : tensor<?x?x?x5xf32>,
 }
 
 // CHECK-LABEL: func @generic_op_reshape_consumer_nofusion
-//       CHECK: linalg.tensor_reshape
+//       CHECK:   %[[T0:.+]] = linalg.generic
+//       CHECK:   linalg.tensor_reshape %[[T0]]
 
 // -----
 
-
-// CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1 * 4 + d2, d3)>
-// CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
-
 #map0 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 func @indexed_generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x?xi32>)
   -> tensor<?x?x4x?xi32> {
@@ -99,8 +106,9 @@ func @indexed_generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x?xi32>)
   %1 = linalg.indexed_generic {
     indexing_maps = [#map0, #map0],
     iterator_types = ["parallel", "parallel", "parallel", "parallel"] }
-    ins(%0 : tensor<?x?x4x?xi32>) {
-  ^bb0(%arg2: index, %arg3: index, %arg4: index, %arg5: index, %arg6: i32):       // no predecessors
+    ins(%0 : tensor<?x?x4x?xi32>)
+    outs(%0 : tensor<?x?x4x?xi32>) {
+  ^bb0(%arg2: index, %arg3: index, %arg4: index, %arg5: index, %arg6: i32, %arg7 : i32):       // no predecessors
     %2 = index_cast %arg2 : index to i32
     %3 = addi %arg6, %2 : i32
     linalg.yield %3 : i32
@@ -108,25 +116,24 @@ func @indexed_generic_op_reshape_producer_fusion(%arg0 : tensor<?x?x?xi32>)
   return %1 : tensor<?x?x4x?xi32>
 }
 
-// CHECK-LABEL: func @indexed_generic_op_reshape_producer_fusion
-//   CHECK-NOT: linalg.tensor_reshape
-//       CHECK: linalg.indexed_generic
-//  CHECK-SAME:   indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
-//   CHECK-NOT: linalg.tensor_reshape
+//   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1 * 4 + d2, d3)>
+//   CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
+//       CHECK: func @indexed_generic_op_reshape_producer_fusion
+//  CHECK-SAME:   %[[ARG0:.+]]: tensor<?x?x?xi32>
+//       CHECK:   linalg.indexed_generic
+//  CHECK-SAME:     indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
+//  CHECK-SAME:     ins(%[[ARG0]] : tensor<?x?x?xi32>)
 
 // -----
 
-// CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
-// CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1 * 20 + d2 * 5 + d3)>
-
 #map0 = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
 func @indexed_generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?x4x5xi32>)
   -> tensor<?x?xi32> {
   %0 = linalg.indexed_generic {
     indexing_maps = [#map0, #map0],
     iterator_types = ["parallel", "parallel", "parallel", "parallel"] }
-    ins(%arg0 : tensor<?x?x4x5xi32>) {
-  ^bb0(%arg2: index, %arg3: index, %arg4: index, %arg5: index, %arg6: i32):       // no predecessors
+    ins(%arg0 : tensor<?x?x4x5xi32>) outs(%arg0 : tensor<?x?x4x5xi32>) {
+  ^bb0(%arg2: index, %arg3: index, %arg4: index, %arg5: index, %arg6: i32, %arg7: i32):       // no predecessors
     %2 = index_cast %arg2 : index to i32
     %3 = addi %arg6, %2 : i32
     linalg.yield %3 : i32
@@ -137,105 +144,124 @@ func @indexed_generic_op_reshape_consumer_fusion(%arg0 : tensor<?x?x4x5xi32>)
   return %1 : tensor<?x?xi32>
 }
 
+//   CHECK-DAG: #[[$MAP0:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>
+//   CHECK-DAG: #[[$MAP1:.*]] = affine_map<(d0, d1, d2, d3) -> (d0, d1 * 20 + d2 * 5 + d3)>
 // CHECK-LABEL: func @indexed_generic_op_reshape_consumer_fusion
-//   CHECK-NOT: linalg.tensor_reshape
-//       CHECK: linalg.indexed_generic
-//  CHECK-SAME:   indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
-//   CHECK-NOT: linalg.tensor_reshape
+//  CHECK-SAME:   %[[ARG0:[a-zA-Z0-9_]+]]: tensor<?x?x4x5xi32>
+//   CHECK-DAG:   %[[C0:.+]] = constant 0 : index
+//   CHECK-DAG:   %[[C1:.+]] = constant 1 : index
+//   CHECK-DAG:   %[[C20:.+]] = constant 20 : index
+//       CHECK:   %[[T0:.+]] = dim %[[ARG0]], %[[C0]]
+//       CHECK:   %[[T1:.+]] = dim %[[ARG0]], %[[C1]]
+//       CHECK:   %[[T2:.+]] = muli %[[T1]], %[[C20]]
+//       CHECK:   %[[T3:.+]] = linalg.init_tensor [%[[T0]], %[[T2]]]
+//       CHECK:   linalg.indexed_generic
+//  CHECK-SAME:     indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
+//  CHECK-SAME:     outs(%[[T3]] : tensor<?x?xi32>)
+//   CHECK-NOT:   linalg.tensor_reshape
 
 // -----
 
-// CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d0, d1 + d2 * 7)>
-// CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
-
 #map0 = affine_map<(d0, d1, d2) -> (d0)>
 #map1 = affine_map<(d0, d1, d2) -> (d1, d2)>
 #map2 = affine_map<(d0, d1, d2) -> (d0, d2, d1)>
 #map3 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 func @generic_op_021_permultation_reshape_producer_fusion(%arg0 : tensor<3x35xf32>) -> tensor<3x7x5xf32> {
   %0 = linalg.tensor_reshape %arg0 [#map0, #map1] : tensor<3x35xf32> into tensor<3x5x7xf32>
-  %1 = linalg.generic {indexing_maps = [#map2, #map3], iterator_types = ["parallel", "parallel", "parallel"]} ins(%0 : tensor<3x5x7xf32>) {
-    ^bb0(%arg2: f32):  // no predecessors
+  %1 = linalg.init_tensor [3, 7, 5] : tensor<3x7x5xf32>
+  %2 = linalg.generic
+    {indexing_maps = [#map2, #map3],
+     iterator_types = ["parallel", "parallel", "parallel"]}
+    ins(%0 : tensor<3x5x7xf32>) outs(%1 : tensor<3x7x5xf32>) {
+    ^bb0(%arg2: f32, %arg3 : f32):  // no predecessors
       linalg.yield %arg2 : f32
     } -> tensor<3x7x5xf32>
-    return %1 : tensor<3x7x5xf32>
+    return %2 : tensor<3x7x5xf32>
 }
 
+// CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d0, d1 + d2 * 7)>
+// CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 // CHECK-LABEL: func @generic_op_021_permultation_reshape_producer_fusion
-//   CHECK-NOT: linalg.tensor_reshape
-//       CHECK: linalg.generic
-//  CHECK-SAME:   indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
-//   CHECK-NOT: linalg.tensor_reshape
+//   CHECK-NOT:   linalg.tensor_reshape
+//       CHECK:   linalg.generic
+//  CHECK-SAME:     indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
 
 // -----
 
-// CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d2, d0 * 7 + d1)>
-// CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
-
 #map0 = affine_map<(d0, d1, d2) -> (d0)>
 #map1 = affine_map<(d0, d1, d2) -> (d1, d2)>
 #map2 = affine_map<(d0, d1, d2) -> (d1, d2, d0)>
 #map3 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 func @generic_op_120_permultation_reshape_producer_fusion(%arg0 : tensor<3x35xf32>) -> tensor<5x7x3xf32> {
   %0 = linalg.tensor_reshape %arg0 [#map0, #map1] : tensor<3x35xf32> into tensor<3x5x7xf32>
-  %1 = linalg.generic {indexing_maps = [#map2, #map3], iterator_types = ["parallel", "parallel", "parallel"]} ins(%0 : tensor<3x5x7xf32>) {
-    ^bb0(%arg2: f32):  // no predecessors
+  %1 = linalg.init_tensor [5, 7, 3] : tensor<5x7x3xf32>
+  %2 = linalg.generic
+    {indexing_maps = [#map2, #map3],
+     iterator_types = ["parallel", "parallel", "parallel"]}
+    ins(%0 : tensor<3x5x7xf32>) outs(%1 : tensor<5x7x3xf32>) {
+    ^bb0(%arg2: f32, %arg3: f32):  // no predecessors
       linalg.yield %arg2 : f32
     } -> tensor<5x7x3xf32>
-    return %1 : tensor<5x7x3xf32>
+    return %2 : tensor<5x7x3xf32>
 }
 
-// CHECK-LABEL: func @generic_op_120_permultation_reshape_producer_fusion
-//   CHECK-NOT: linalg.tensor_reshape
-//       CHECK: linalg.generic
-//  CHECK-SAME:   indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
-//   CHECK-NOT: linalg.tensor_reshape
+//   CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d2, d0 * 7 + d1)>
+//   CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
+//       CHECK: func @generic_op_120_permultation_reshape_producer_fusion
+//   CHECK-NOT:   linalg.tensor_reshape
+//       CHECK:   linalg.generic
+//  CHECK-SAME:     indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
 
 // -----
 
-// CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d1, d0 * 7 + d2)>
-// CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
-
 #map0 = affine_map<(d0, d1, d2) -> (d0)>
 #map1 = affine_map<(d0, d1, d2) -> (d1, d2)>
 #map2 = affine_map<(d0, d1, d2) -> (d1, d0, d2)>
 #map3 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 func @generic_op_102_permultation_reshape_producer_fusion(%arg0 : tensor<3x35xf32>) -> tensor<5x3x7xf32> {
   %0 = linalg.tensor_reshape %arg0 [#map0, #map1] : tensor<3x35xf32> into tensor<3x5x7xf32>
-  %1 = linalg.generic {indexing_maps = [#map2, #map3], iterator_types = ["parallel", "parallel", "parallel"]} ins(%0 : tensor<3x5x7xf32>) {
-    ^bb0(%arg2: f32):  // no predecessors
+  %1 = linalg.init_tensor [5, 3, 7] : tensor<5x3x7xf32>
+  %2 = linalg.generic
+    {indexing_maps = [#map2, #map3],
+     iterator_types = ["parallel", "parallel", "parallel"]}
+    ins(%0 : tensor<3x5x7xf32>) outs(%1 : tensor<5x3x7xf32>) {
+    ^bb0(%arg2: f32, %arg3: f32):  // no predecessors
       linalg.yield %arg2 : f32
     } -> tensor<5x3x7xf32>
-    return %1 : tensor<5x3x7xf32>
+    return %2 : tensor<5x3x7xf32>
 }
 
-// CHECK-LABEL: func @generic_op_102_permultation_reshape_producer_fusion
-//   CHECK-NOT: linalg.tensor_reshape
-//       CHECK: linalg.generic
-//  CHECK-SAME:   indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
-//   CHECK-NOT: linalg.tensor_reshape
-
-// -----
 
-// CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
-// CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d1, d0 * 7 + d2)>
+//   CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d1, d0 * 7 + d2)>
+//   CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
+//       CHECK: func @generic_op_102_permultation_reshape_producer_fusion
+//   CHECK-NOT:   linalg.tensor_reshape
+//       CHECK:   linalg.generic
+//  CHECK-SAME:     indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
 
+// -----
 
 #map0 = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
 #map1 = affine_map<(d0, d1, d2) -> (d1, d0, d2)>
 #map2 = affine_map<(d0, d1, d2) -> (d0)>
 #map3 = affine_map<(d0, d1, d2) -> (d1, d2)>
 func @generic_op_102_permultation_reshape_consumer_fusion(%arg0 : tensor<3x5x7xf32>) -> tensor<5x21xf32> {
-  %0 = linalg.generic {indexing_maps = [#map0, #map1], iterator_types = ["parallel", "parallel", "parallel"]} ins(%arg0 : tensor<3x5x7xf32>) {
-    ^bb0(%arg2: f32):  // no predecessors
+  %0 = linalg.init_tensor [5, 3, 7] : tensor<5x3x7xf32>
+  %1 = linalg.generic
+    {indexing_maps = [#map0, #map1],
+     iterator_types = ["parallel", "parallel", "parallel"]}
+    ins(%arg0 : tensor<3x5x7xf32>) outs(%0 : tensor<5x3x7xf32>) {
+    ^bb0(%arg2: f32, %arg3 : f32):  // no predecessors
       linalg.yield %arg2 : f32
   } -> tensor<5x3x7xf32>
-  %1 = linalg.tensor_reshape %0 [#map2, #map3] : tensor<5x3x7xf32> into tensor<5x21xf32>
-  return %1 : tensor<5x21xf32>
+  %2 = linalg.tensor_reshape %1 [#map2, #map3] : tensor<5x3x7xf32> into tensor<5x21xf32>
+  return %2 : tensor<5x21xf32>
 }
 
-// CHECK-LABEL: func @generic_op_102_permultation_reshape_consumer_fusion
-//   CHECK-NOT: linalg.tensor_reshape
-//       CHECK: linalg.generic
-//  CHECK-SAME:   indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
-//   CHECK-NOT: linalg.tensor_reshape
+
+//   CHECK-DAG: #[[MAP0:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)>
+//   CHECK-DAG: #[[MAP1:.+]] = affine_map<(d0, d1, d2) -> (d1, d0 * 7 + d2)>
+//       CHECK: func @generic_op_102_permultation_reshape_consumer_fusion
+//   CHECK-NOT:   linalg.tensor_reshape
+//       CHECK:   linalg.generic
+//  CHECK-SAME:     indexing_maps = [#[[$MAP0]], #[[$MAP1]]]
diff --git a/mlir/test/Dialect/Linalg/roundtrip.mlir b/mlir/test/Dialect/Linalg/roundtrip.mlir
index be785ceb70d6d..c4eb8f8eac679 100644
--- a/mlir/test/Dialect/Linalg/roundtrip.mlir
+++ b/mlir/test/Dialect/Linalg/roundtrip.mlir
@@ -300,7 +300,7 @@ func @pooling_sum(%arg0: memref<?x?x?xf32>,
 func @generic(%arg0: memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>,
               %arg1: memref<?x?x?xf32, offset: ?, strides: [?, ?, 1]>) {
   linalg.generic #trait
-      ins(%arg0 : memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>)
+       ins(%arg0 : memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>)
       outs(%arg1 : memref<?x?x?xf32, offset: ?, strides: [?, ?, 1]>)
       attrs = {foo = 1} {
     ^bb(%0: vector<3x4xi4>, %1: f32) :
@@ -314,14 +314,14 @@ func @generic(%arg0: memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>,
 //  CHECK-SAME:     indexing_maps = [#{{[0-9a-z]*}}, #{{[0-9a-z]*}}],
 //  CHECK-SAME:     iterator_types = ["parallel", "parallel", "parallel"],
 //  CHECK-SAME:     library_call = "some_external_function_name_1"}
-//  CHECK-SAME:     ins({{.*}} : memref<?x?xvector<3x4xi4>, #[[$strided2D]]>)
+//  CHECK-SAME:      ins({{.*}} : memref<?x?xvector<3x4xi4>, #[[$strided2D]]>)
 //  CHECK-SAME:     outs({{.*}} : memref<?x?x?xf32, #[[$strided3D]]>)
 //  CHECK-SAME:     {foo = 1 : i64}
 
 func @generic_with_tensor_input(%arg0: tensor<?x?xvector<3x4xi4>>,
                                 %arg1: memref<?x?x?xf32, offset: ?, strides: [?, ?, 1]>) {
   linalg.generic #trait
-      ins(%arg0 : tensor<?x?xvector<3x4xi4>>)
+       ins(%arg0 : tensor<?x?xvector<3x4xi4>>)
       outs(%arg1 : memref<?x?x?xf32, offset: ?, strides: [?, ?, 1]>)
       attrs = {foo = 1} {
     ^bb(%0: vector<3x4xi4>, %1: f32) :
@@ -358,14 +358,14 @@ func @generic_without_inputs(%arg0 : memref<?x?x?xf32>) {
 
 // -----
 
-#accesses = [
+#accesses2 = [
   affine_map<(i, j, k) -> (j, i)>,
   affine_map<(i, j, k) -> (i, k, i + j)>,
   affine_map<(i, j, k) -> (i, k, i + j)>
 ]
 
 #trait2 = {
-  indexing_maps = #accesses,
+  indexing_maps = #accesses2,
   iterator_types = ["parallel", "parallel", "parallel"],
   library_call = "some_external_function_name_1"
 }
@@ -374,9 +374,10 @@ func @generic_with_tensor_input_and_output(
     %arg0: tensor<?x?xvector<3x4xi4>>, %arg1: tensor<?x?x?xf32>)
     -> (tensor<?x?x?xf32>) {
   %0 = linalg.generic #trait2
-      ins(%arg0, %arg1 : tensor<?x?xvector<3x4xi4>>, tensor<?x?x?xf32>)
+       ins(%arg0, %arg1 : tensor<?x?xvector<3x4xi4>>, tensor<?x?x?xf32>)
+      outs(%arg1 : tensor<?x?x?xf32>)
       attrs = {foo = 1} {
-    ^bb(%0: vector<3x4xi4>, %1: f32) :
+    ^bb(%0: vector<3x4xi4>, %1: f32, %2: f32) :
       %f0 = constant 0.0 : f32
       linalg.yield %f0 : f32
   } -> tensor<?x?x?xf32>
@@ -386,21 +387,22 @@ func @generic_with_tensor_input_and_output(
 //       CHECK:   linalg.generic {
 //  CHECK-SAME:     indexing_maps = [#{{.*}}, #{{.*}}], iterator_types = ["parallel", "parallel", "parallel"],
 //  CHECK-SAME:     library_call = "some_external_function_name_1"}
-//  CHECK-SAME:     ins({{.*}} : tensor<?x?xvector<3x4xi4>>, tensor<?x?x?xf32>)
+//  CHECK-SAME:      ins({{.*}} : tensor<?x?xvector<3x4xi4>>, tensor<?x?x?xf32>)
+//  CHECK-SAME:     outs({{.*}} : tensor<?x?x?xf32>)
 //  CHECK-SAME:     {foo = 1 : i64}
 //       CHECK:     -> tensor<?x?x?xf32>
 //       CHECK:   return {{.*}} : tensor<?x?x?xf32>
 
 // -----
 
-#accesses = [
+#accesses3 = [
   affine_map<(i, j, k) -> (j, i)>,
   affine_map<(i, j, k) -> (i, k, i + j)>,
   affine_map<(i, j, k) -> (i, k, i + j)>
 ]
 
-#trait2 = {
-  indexing_maps = #accesses,
+#trait3 = {
+  indexing_maps = #accesses3,
   iterator_types = ["parallel", "parallel", "parallel"],
   library_call = "some_external_function_name_1"
 }
@@ -408,10 +410,11 @@ func @generic_with_tensor_input_and_output(
 func @indexed_generic_with_tensor_input_and_output(
     %arg0: tensor<?x?xvector<3x4xi4>>, %arg1: tensor<?x?x?xf32>)
     -> (tensor<?x?x?xf32>) {
-  %0 = linalg.indexed_generic #trait2
-      ins(%arg0, %arg1 : tensor<?x?xvector<3x4xi4>>, tensor<?x?x?xf32>)
+  %0 = linalg.indexed_generic #trait3
+       ins(%arg0, %arg1 : tensor<?x?xvector<3x4xi4>>, tensor<?x?x?xf32>)
+      outs(%arg1 : tensor<?x?x?xf32>)
       attrs = {foo = 1} {
-    ^bb(%i: index, %j: index, %k: index, %0: vector<3x4xi4>, %1: f32) :
+    ^bb(%i: index, %j: index, %k: index, %0: vector<3x4xi4>, %1: f32, %2: f32) :
       %f0 = constant 0.0 : f32
       linalg.yield %f0 : f32
   } -> tensor<?x?x?xf32>
@@ -421,7 +424,8 @@ func @indexed_generic_with_tensor_input_and_output(
 //       CHECK:   linalg.indexed_generic {
 //  CHECK-SAME:     indexing_maps = [#{{.*}}, #{{.*}}], iterator_types = ["parallel", "parallel", "parallel"],
 //  CHECK-SAME:     library_call = "some_external_function_name_1"}
-//  CHECK-SAME:     ins({{.*}} : tensor<?x?xvector<3x4xi4>>, tensor<?x?x?xf32>)
+//  CHECK-SAME:      ins({{.*}} : tensor<?x?xvector<3x4xi4>>, tensor<?x?x?xf32>)
+//  CHECK-SAME:     outs({{.*}} : tensor<?x?x?xf32>)
 //  CHECK-SAME:     {foo = 1 : i64}
 //       CHECK:     -> tensor<?x?x?xf32>
 //       CHECK:   return {{.*}} : tensor<?x?x?xf32>
@@ -439,21 +443,23 @@ func @indexed_generic_with_tensor_input_and_output(
   library_call = "some_broadcast_external_fn"
 }
 
-func @generic_op_zero_rank(%arg0: tensor<f32>) -> (tensor<3x4xf32>)
+func @generic_op_zero_rank(%arg0: tensor<f32>, %arg1 : tensor<3x4xf32>) -> (tensor<3x4xf32>)
 {
   %0 = linalg.generic #trait_broadcast
-      ins(%arg0 : tensor<f32>) {
-    ^bb(%a: f32) :
+       ins(%arg0 : tensor<f32>)
+      outs(%arg1 : tensor<3x4xf32>) {
+    ^bb(%a: f32, %b: f32) :
       linalg.yield %a : f32
   } -> tensor<3x4xf32>
   return %0 : tensor<3x4xf32>
 }
 
-func @indexed_generic_op_zero_rank(%arg0: tensor<f32>) -> (tensor<3x4xf32>)
+func @indexed_generic_op_zero_rank(%arg0: tensor<f32>, %arg1 : tensor<3x4xf32>) -> (tensor<3x4xf32>)
 {
   %0 = linalg.indexed_generic #trait_broadcast
-      ins(%arg0 : tensor<f32>) {
-    ^bb(%i: index, %j: index, %a: f32) :
+       ins(%arg0 : tensor<f32>)
+      outs(%arg1 : tensor<3x4xf32>) {
+    ^bb(%i: index, %j: index, %a: f32, %b: f32) :
       linalg.yield %a : f32
   } -> tensor<3x4xf32>
   return %0 : tensor<3x4xf32>
@@ -478,7 +484,7 @@ func @indexed_generic_op_zero_rank(%arg0: tensor<f32>) -> (tensor<3x4xf32>)
 func @generic_region(%arg0: memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>,
                      %arg1: memref<?x?x?xf32, offset: ?, strides: [?, ?, 1]>) {
   linalg.generic #trait3
-      ins(%arg0 : memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>)
+       ins(%arg0 : memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>)
       outs(%arg1 : memref<?x?x?xf32, offset: ?, strides: [?, ?, 1]>)
       attrs = {foo = 1} {
     ^bb(%a: vector<3x4xi4>, %b: f32) :
@@ -491,7 +497,7 @@ func @generic_region(%arg0: memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1
 //  CHECK-SAME:     indexing_maps = [#{{[0-9a-z]*}}, #{{[0-9a-z]*}}],
 //  CHECK-SAME:     iterator_types = ["parallel", "parallel", "parallel"],
 //  CHECK-SAME:     library_call = "some_external_function_name_2"
-//  CHECK-SAME:     ins({{.*}} : memref<?x?xvector<3x4xi4>, #[[$strided2D]]>)
+//  CHECK-SAME:      ins({{.*}} : memref<?x?xvector<3x4xi4>, #[[$strided2D]]>)
 //  CHECK-SAME:     outs({{.*}} : memref<?x?x?xf32, #[[$strided3D]]>)
 //  CHECK-SAME:     attrs = {foo = 1 : i64} {
 //       CHECK:  ^{{.*}}(%{{.*}}: vector<3x4xi4>, %{{.*}}: f32):
@@ -500,7 +506,7 @@ func @generic_region(%arg0: memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1
 func @indexed_generic(%arg0: memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>,
                       %arg1: memref<?x?x?xf32, offset: ?, strides: [?, ?, 1]>) {
   linalg.indexed_generic #trait3
-      ins(%arg0 : memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>)
+       ins(%arg0 : memref<?x?xvector<3x4xi4>, offset: ?, strides: [?, 1]>)
       outs(%arg1 : memref<?x?x?xf32, offset: ?, strides: [?, ?, 1]>)
       attrs = {foo = 1} {
     ^bb(%i: index, %j: index, %k: index, %a: vector<3x4xi4>, %b: f32) :
@@ -564,8 +570,8 @@ func @reshape_static(%arg0: memref<3x4x5xf32>, %arg1: tensor<3x4x5xf32>, %arg2:
                                      affine_map<(i, j, k, l, m) -> (l, m)>] :
     tensor<3x4x5xf32> into tensor<1x3x4x1x5xf32>
   %rt0 = linalg.tensor_reshape %t0 [affine_map<(i, j, k, l, m) -> (i, j)>,
-                                   affine_map<(i, j, k, l, m) -> (k)>,
-                                   affine_map<(i, j, k, l, m) -> (l, m)>] :
+                                    affine_map<(i, j, k, l, m) -> (k)>,
+                                    affine_map<(i, j, k, l, m) -> (l, m)>] :
     tensor<1x3x4x1x5xf32> into tensor<3x4x5xf32>
   %t1 = linalg.tensor_reshape %arg2 [affine_map<(i, j, k, l, m) -> (i, j)>,
                                      affine_map<(i, j, k, l, m) -> (k)>,
@@ -660,11 +666,13 @@ func @named_ops(%a3: memref<?x?x?xf32>, %b3: memref<?x?x?xf32>, %c3: memref<?x?x
                      outs(%c3: memref<?x?x?xf32>)
   linalg.batch_matmul ins(%ta3, %tb3: tensor<?x?x?xf32>, tensor<?x?x?xf32>)
                      outs(%c3: memref<?x?x?xf32>)
-  %res1 = linalg.batch_matmul ins(%ta3, %tb3: tensor<?x?x?xf32>, tensor<?x?x?xf32>)
-                     init(%tc3: tensor<?x?x?xf32>)
+  %res1 = linalg.batch_matmul
+                      ins(%ta3, %tb3: tensor<?x?x?xf32>, tensor<?x?x?xf32>)
+                     outs(%tc3: tensor<?x?x?xf32>)
                   -> tensor<?x?x?xf32>
-  %res2 = linalg.batch_matmul ins(%ta3, %b3: tensor<?x?x?xf32>, memref<?x?x?xf32>)
-                     init(%tc3: tensor<?x?x?xf32>)
+  %res2 = linalg.batch_matmul
+                      ins(%ta3, %b3: tensor<?x?x?xf32>, memref<?x?x?xf32>)
+                     outs(%tc3: tensor<?x?x?xf32>)
                   -> tensor<?x?x?xf32>
   return %res1, %res2 : tensor<?x?x?xf32>, tensor<?x?x?xf32>
 }
diff --git a/mlir/test/Dialect/Linalg/sparse_1d.mlir b/mlir/test/Dialect/Linalg/sparse_1d.mlir
index 4c14b2e89279d..4baf1d1c14032 100644
--- a/mlir/test/Dialect/Linalg/sparse_1d.mlir
+++ b/mlir/test/Dialect/Linalg/sparse_1d.mlir
@@ -32,8 +32,9 @@
 // CHECK:         }
 func @add_d(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
   %0 = linalg.generic #trait_d
-    ins(%arga: tensor<32xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32xf32>)
+    outs(%arga: tensor<32xf32>) {
+      ^bb(%a: f32, %s : f32):
         %0 = addf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -58,8 +59,9 @@ func @add_d(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
 // CHECK:         }
 func @mul_d(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
   %0 = linalg.generic #trait_d
-    ins(%arga: tensor<32xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32xf32>)
+    outs(%arga: tensor<32xf32>) {
+      ^bb(%a: f32, %s : f32):
         %0 = mulf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -124,8 +126,9 @@ func @mul_d(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
 // CHECK:         }
 func @add_s(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
   %0 = linalg.generic #trait_s
-    ins(%arga: tensor<32xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32xf32>)
+    outs(%arga: tensor<32xf32>) {
+      ^bb(%a: f32, %s : f32):
         %0 = addf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -159,8 +162,9 @@ func @add_s(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
 // CHECK:         }
 func @repeated_add_s(%arga: tensor<32xf32>) -> tensor<32xf32> {
   %0 = linalg.generic #trait_s
-    ins(%arga: tensor<32xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32xf32>)
+    outs(%arga: tensor<32xf32>) {
+      ^bb(%a: f32, %s : f32):
         %0 = addf %a, %a  : f32  // same tensor
         %1 = addf %a, %a  : f32  // should yield
         %2 = addf %0, %1  : f32  // one guard
@@ -192,8 +196,9 @@ func @repeated_add_s(%arga: tensor<32xf32>) -> tensor<32xf32> {
 // CHECK:         }
 func @mul_s(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
   %0 = linalg.generic #trait_s
-    ins(%arga: tensor<32xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32xf32>)
+    outs(%arga: tensor<32xf32>) {
+      ^bb(%a: f32, %s : f32):
         %0 = mulf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -235,8 +240,9 @@ func @mul_s(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
 // CHECK:         }
 func @add_dd(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
   %0 = linalg.generic #trait_dd
-    ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>)
+    outs(%arga : tensor<32xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -263,8 +269,9 @@ func @add_dd(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
 // CHECK:         }
 func @mul_dd(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
   %0 = linalg.generic #trait_dd
-    ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>)
+    outs(%arga : tensor<32xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -335,8 +342,9 @@ func @mul_dd(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
 // CHECK:         }
 func @add_ds(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
   %0 = linalg.generic #trait_ds
-    ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>)
+    outs(%arga : tensor<32xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -368,8 +376,9 @@ func @add_ds(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
 // CHECK:         }
 func @mul_ds(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
   %0 = linalg.generic #trait_ds
-    ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>)
+    outs(%arga : tensor<32xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -440,8 +449,9 @@ func @mul_ds(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
 // CHECK:         }
 func @add_sd(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
   %0 = linalg.generic #trait_sd
-    ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>)
+    outs(%arga : tensor<32xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -473,8 +483,9 @@ func @add_sd(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
 // CHECK:         }
 func @mul_sd(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
   %0 = linalg.generic #trait_sd
-    ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>)
+    outs(%arga : tensor<32xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -569,8 +580,9 @@ func @mul_sd(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
 // CHECK:         }
 func @add_ss(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
   %0 = linalg.generic #trait_ss
-    ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>)
+    outs(%arga : tensor<32xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -628,8 +640,9 @@ func @add_ss(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
 // CHECK:         }
 func @mul_ss(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
   %0 = linalg.generic #trait_ss
-    ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32xf32>, tensor<32xf32>)
+    outs(%arga : tensor<32xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -730,8 +743,9 @@ func @mul_ss(%arga: tensor<32xf32>, %argb: tensor<32xf32>) -> tensor<32xf32> {
 func @two_way_inv(%arga: tensor<16xf32>,
                   %argb: tensor<16xf32>, %argc: f32) -> tensor<16xf32> {
   %0 = linalg.generic #trait_two_way_inv
-    ins(%arga, %argb : tensor<16xf32>, tensor<16xf32>) {
-      ^bb(%a : f32, %b : f32):
+    ins(%arga, %argb : tensor<16xf32>, tensor<16xf32>)
+    outs(%argb : tensor<16xf32>) {
+      ^bb(%a : f32, %b : f32, %c : f32):
         %0 = mulf %a, %argc : f32
         %1 = mulf %b, %argc : f32
         %2 = addf %0, %1 : f32
@@ -819,8 +833,9 @@ func @two_way_inv_alt(%arga: tensor<16xf32>,
                       %argb: tensor<16xf32>, %argc: f32) -> tensor<16xf32> {
   // Same kernel, but now expressed as "x(i) = (a(i) + b(i)) * c".
   %0 = linalg.generic #trait_two_way_inv
-    ins(%arga, %argb : tensor<16xf32>, tensor<16xf32>) {
-      ^bb(%a : f32, %b : f32):
+    ins(%arga, %argb : tensor<16xf32>, tensor<16xf32>)
+    outs(%argb : tensor<16xf32>) {
+      ^bb(%a : f32, %b : f32, %c : f32):
         %0 = addf %a, %b : f32
         %1 = mulf %0, %argc : f32
         linalg.yield %1: f32
@@ -866,7 +881,7 @@ func @two_way_inv_alt(%arga: tensor<16xf32>,
 func @sum_reduction(%arga: tensor<?xf32>, %argx: tensor<f32>) -> tensor<f32> {
   %0 = linalg.generic #trait_sum_reduction
     ins(%arga : tensor<?xf32>)
-    init(%argx : tensor<f32>) {
+    outs(%argx : tensor<f32>) {
       ^bb(%a : f32, %x : f32):
         %0 = addf %x, %a  : f32
         linalg.yield %0: f32
@@ -975,7 +990,7 @@ func @sum_reduction_ss(%arga: tensor<16xf32>,
   // as two separate reductions kernels.
   %0 = linalg.generic #trait_sum_reduction_ss
     ins(%arga, %argb: tensor<16xf32>, tensor<16xf32>)
-    init(%argx : tensor<f32>) {
+    outs(%argx : tensor<f32>) {
       ^bb(%a : f32, %b : f32, %x : f32):
         %0 = addf %a, %b  : f32
         %1 = addf %x, %0  : f32
@@ -1094,7 +1109,7 @@ func @sum_reduction_inv(%arga: tensor<16xf32>,
   // as two separate reductions kernels.
   %0 = linalg.generic #trait_sum_reduction_inv_ss
     ins(%arga, %argb, %argc : tensor<16xf32>, tensor<f32>, tensor<16xf32>)
-    init(%argx : tensor<f32>) {
+    outs(%argx : tensor<f32>) {
       ^bb(%a : f32, %b : f32, %c : f32, %x : f32):
         %0 = mulf %a, %b  : f32
         %1 = addf %0, %c  : f32
diff --git a/mlir/test/Dialect/Linalg/sparse_2d.mlir b/mlir/test/Dialect/Linalg/sparse_2d.mlir
index dea7444cadae2..6612a723f23dd 100644
--- a/mlir/test/Dialect/Linalg/sparse_2d.mlir
+++ b/mlir/test/Dialect/Linalg/sparse_2d.mlir
@@ -39,8 +39,9 @@
 // CHECK:         }
 func @add_dd(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_dd
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga: tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -70,8 +71,9 @@ func @add_dd(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16
 // CHECK:         }
 func @mul_dd(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_dd
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -146,8 +148,9 @@ func @mul_dd(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16
 // CHECK:         }
 func @add_ds(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_ds
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -183,8 +186,9 @@ func @add_ds(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16
 // CHECK:         }
 func @mul_ds(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_ds
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -264,8 +268,9 @@ func @mul_ds(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16
 // CHECK:         }
 func @add_sd(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_sd
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -302,8 +307,9 @@ func @add_sd(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16
 // CHECK:         }
 func @mul_sd(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_sd
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -409,8 +415,9 @@ func @mul_sd(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16
 // CHECK:         }
 func @add_ss(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_ss
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -450,8 +457,9 @@ func @add_ss(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16
 // CHECK:         }
 func @mul_ss(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_ss
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -627,8 +635,9 @@ func @mul_ss(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16
 // CHECK:         }
 func @add_ss_ss(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_ss_ss
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -721,8 +730,9 @@ func @add_ss_ss(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32
 // CHECK:         }
 func @mul_ss_ss(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_ss_ss
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -898,8 +908,9 @@ func @mul_ss_ss(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32
 // CHECK:         }
 func @add_sd_ds(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_ss_ss
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -992,8 +1003,9 @@ func @add_sd_ds(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32
 // CHECK:         }
 func @mul_sd_ds(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32x16xf32> {
   %0 = linalg.generic #trait_ss_ss
-    ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16xf32>, tensor<32x16xf32>)
+    outs(%arga : tensor<32x16xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -1048,8 +1060,8 @@ func @mul_sd_ds(%arga: tensor<32x16xf32>, %argb: tensor<32x16xf32>) -> tensor<32
 // CHECK:         }
 func @matvec(%argA: tensor<16x32xf32>, %argb: tensor<32xf32>, %argx: tensor<16xf32>) -> tensor<16xf32> {
   %0 = linalg.generic #trait_matvec
-      ins(%argA, %argb : tensor<16x32xf32>, tensor<32xf32>)
-      init(%argx : tensor<16xf32>) {
+       ins(%argA, %argb : tensor<16x32xf32>, tensor<32xf32>)
+      outs(%argx : tensor<16xf32>) {
     ^bb(%A: f32, %b: f32, %x: f32):
       %0 = mulf %A, %b : f32
       %1 = addf %0, %x : f32
@@ -1099,8 +1111,8 @@ func @matvec(%argA: tensor<16x32xf32>, %argb: tensor<32xf32>, %argx: tensor<16xf
 // CHECK:         }
 func @sum_reduction(%arga: tensor<10x20xf32>, %argx: tensor<f32>) -> tensor<f32> {
   %0 = linalg.generic #trait_sum_reduction
-    ins(%arga : tensor<10x20xf32>)
-    init(%argx : tensor<f32>) {
+     ins(%arga : tensor<10x20xf32>)
+    outs(%argx : tensor<f32>) {
       ^bb(%a : f32, %x : f32):
         %0 = addf %x, %a  : f32
         linalg.yield %0: f32
@@ -1150,8 +1162,9 @@ func @sum_reduction(%arga: tensor<10x20xf32>, %argx: tensor<f32>) -> tensor<f32>
 func @scale(%arga: tensor<?x?xf64>) -> tensor<?x?xf64> {
   %0 = constant 2.0 : f64
   %1 = linalg.generic #trait_scale
-    ins(%arga: tensor<?x?xf64>) {
-      ^bb(%a: f64):
+     ins(%arga: tensor<?x?xf64>)
+    outs(%arga: tensor<?x?xf64>) {
+      ^bb(%a: f64, %s: f64):
         %2 = mulf %a, %0  : f64
         linalg.yield %2 : f64
   } -> tensor<?x?xf64>
@@ -1224,10 +1237,10 @@ func @scale(%arga: tensor<?x?xf64>) -> tensor<?x?xf64> {
 func @sampled_dense_dense(%args: tensor<?x?xf32>,
                           %arga: tensor<?x?xf32>,
                           %argb: tensor<?x?xf32>,
-			  %argx: tensor<?x?xf32>) -> tensor<?x?xf32> {
+                          %argx: tensor<?x?xf32>) -> tensor<?x?xf32> {
   %0 = linalg.generic #trait_sampled_dense_dense
-    ins(%args, %arga, %argb : tensor<?x?xf32>, tensor<?x?xf32>, tensor<?x?xf32>)
-    init(%argx : tensor<?x?xf32>) {
+     ins(%args, %arga, %argb : tensor<?x?xf32>, tensor<?x?xf32>, tensor<?x?xf32>)
+    outs(%argx : tensor<?x?xf32>) {
       ^bb(%s : f32, %a : f32, %b : f32, %x : f32):
         %0 = mulf %a, %b  : f32
         %1 = mulf %s, %0  : f32
@@ -1457,7 +1470,7 @@ func @sum_kernel_with_inv(%arga: tensor<?x?xf32>,
                                             tensor<?x?xf32>,
                                             tensor<?xf32>,
                                             tensor<f32>)
-    init(%argx : tensor<?xf32>) {
+    outs(%argx : tensor<?xf32>) {
       ^bb(%a : f32, %b : f32, %c : f32, %d : f32, %e : f32, %x : f32):
         %0 = mulf %a, %b  : f32
         %1 = mulf %0, %d  : f32
diff --git a/mlir/test/Dialect/Linalg/sparse_3d.mlir b/mlir/test/Dialect/Linalg/sparse_3d.mlir
index 41818bb982b6b..a32770e635e45 100644
--- a/mlir/test/Dialect/Linalg/sparse_3d.mlir
+++ b/mlir/test/Dialect/Linalg/sparse_3d.mlir
@@ -42,8 +42,9 @@
 // CHECK:         }
 func @add_ddd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_ddd
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s: f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -76,8 +77,9 @@ func @add_ddd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @mul_ddd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_ddd
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -157,8 +159,9 @@ func @mul_ddd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @add_dds(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_dds
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -199,8 +202,9 @@ func @add_dds(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @mul_dds(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_dds
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -284,8 +288,9 @@ func @mul_dds(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @add_dsd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_dsd
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -326,8 +331,9 @@ func @add_dsd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @mul_dsd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_dsd
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -437,8 +443,9 @@ func @mul_dsd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @add_dss(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_dss
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -482,8 +489,9 @@ func @add_dss(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @mul_dss(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_dss
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -572,8 +580,9 @@ func @mul_dss(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @add_sdd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_sdd
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -615,8 +624,9 @@ func @add_sdd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @mul_sdd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_sdd
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -731,8 +741,9 @@ func @mul_sdd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @add_sds(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_sds
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -777,8 +788,9 @@ func @add_sds(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @mul_sds(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_sds
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -897,8 +909,9 @@ func @mul_sds(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @add_ssd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_ssd
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -943,8 +956,9 @@ func @add_ssd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @mul_ssd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_ssd
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -1089,8 +1103,9 @@ func @mul_ssd(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @add_sss(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_sss
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = addf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -1138,8 +1153,9 @@ func @add_sss(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<
 // CHECK:         }
 func @mul_sss(%arga: tensor<32x16x8xf32>, %argb: tensor<32x16x8xf32>) -> tensor<32x16x8xf32> {
   %0 = linalg.generic #trait_sss
-    ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>) {
-      ^bb(%a: f32, %b: f32):
+     ins(%arga, %argb: tensor<32x16x8xf32>, tensor<32x16x8xf32>)
+    outs(%arga : tensor<32x16x8xf32>) {
+      ^bb(%a: f32, %b: f32, %s : f32):
         %0 = mulf %a, %b  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16x8xf32>
@@ -1213,8 +1229,8 @@ func @kernel_3d(%arga: tensor<?x?xf32>,
                 %argc: tensor<?x?xf32>,
 	        %argd: tensor<?x?xf32>) -> tensor<?x?xf32> {
   %0 = linalg.generic #trait_kernel_3d
-      ins(%argb, %argc, %argd : tensor<?x?x?xf32>, tensor<?x?xf32>, tensor<?x?xf32>)
-      init(%arga : tensor<?x?xf32>) {
+       ins(%argb, %argc, %argd : tensor<?x?x?xf32>, tensor<?x?xf32>, tensor<?x?xf32>)
+      outs(%arga : tensor<?x?xf32>) {
     ^bb(%b: f32, %c: f32, %d : f32, %a : f32):
       %0 = mulf %b, %c : f32
       %1 = mulf %0, %d : f32
@@ -1275,8 +1291,8 @@ func @kernel_3d(%arga: tensor<?x?xf32>,
 // CHECK:         }
 func @sum_reduction(%arga: tensor<10x20x30xf32>, %argx: tensor<f32>) -> tensor<f32> {
   %0 = linalg.generic #trait_sum_reduction
-    ins(%arga : tensor<10x20x30xf32>)
-    init(%argx : tensor<f32>) {
+     ins(%arga : tensor<10x20x30xf32>)
+    outs(%argx : tensor<f32>) {
       ^bb(%a : f32, %x : f32):
         %0 = addf %x, %a  : f32
         linalg.yield %0: f32
@@ -1334,7 +1350,7 @@ func @sum_reduction_inv(%arga: tensor<?x?x?xf32>,
 		        %argx: tensor<f32>) -> tensor<f32> {
   %0 = linalg.generic #trait_sum_reduction_inv
     ins(%arga, %argb : tensor<?x?x?xf32>, tensor<?xf32>)
-    init(%argx : tensor<f32>) {
+    outs(%argx : tensor<f32>) {
       ^bb(%a : f32, %b : f32, %x : f32):
         %0 = mulf %a, %b  : f32
         %1 = addf %x, %0  : f32
@@ -1363,7 +1379,8 @@ func @sum_reduction_inv(%arga: tensor<?x?x?xf32>,
 // CHECK-LABEL:   func @invariants(
 // CHECK-SAME:                     %[[VAL_0:.*]]: tensor<10xf32>,
 // CHECK-SAME:                     %[[VAL_1:.*]]: tensor<20xf32>,
-// CHECK-SAME:                     %[[VAL_2:.*]]: tensor<30xf32>) -> tensor<10x20x30xf32> {
+// CHECK-SAME:                     %[[VAL_2:.*]]: tensor<30xf32>,
+// CHECK-SAME:                     %[[SHAPE:.*]]: tensor<10x20x30xf32>) -> tensor<10x20x30xf32> {
 // CHECK:           %[[VAL_3:.*]] = constant 10 : index
 // CHECK:           %[[VAL_4:.*]] = constant 20 : index
 // CHECK:           %[[VAL_5:.*]] = constant 30 : index
@@ -1390,10 +1407,12 @@ func @sum_reduction_inv(%arga: tensor<?x?x?xf32>,
 // CHECK:         }
 func @invariants(%arga: tensor<10xf32>,
                  %argb: tensor<20xf32>,
-                 %argc: tensor<30xf32>) -> tensor<10x20x30xf32> {
+                 %argc: tensor<30xf32>,
+                 %shape : tensor<10x20x30xf32>) -> tensor<10x20x30xf32> {
   %0 = linalg.generic #trait_invariants
-    ins(%arga, %argb, %argc : tensor<10xf32>, tensor<20xf32>, tensor<30xf32>) {
-      ^bb(%a : f32, %b : f32, %c : f32):
+     ins(%arga, %argb, %argc : tensor<10xf32>, tensor<20xf32>, tensor<30xf32>)
+    outs(%shape : tensor<10x20x30xf32>) {
+      ^bb(%a : f32, %b : f32, %c : f32, %s : f32):
         %0 = mulf %a, %b  : f32
         %1 = mulf %0, %c  : f32
         linalg.yield %1: f32
diff --git a/mlir/test/Dialect/Linalg/sparse_invalid.mlir b/mlir/test/Dialect/Linalg/sparse_invalid.mlir
index a75ec361a7a18..bb64e80785fa6 100644
--- a/mlir/test/Dialect/Linalg/sparse_invalid.mlir
+++ b/mlir/test/Dialect/Linalg/sparse_invalid.mlir
@@ -12,11 +12,14 @@
   iterator_types = ["parallel"]
 }
 
-func @invalid_memref(%arga: memref<32xf32>, %argb: f32) -> tensor<32xf32> {
+func @invalid_memref(%arga: memref<32xf32>, %argb: f32, %shape: tensor<32xf32>)
+  -> tensor<32xf32>
+{
   // expected-error@+1 {{'linalg.generic' op expected sparse annotations on tensors only}}
   %0 = linalg.generic #trait_memref
-    ins(%arga: memref<32xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: memref<32xf32>)
+    outs(%shape: tensor<32xf32>) {
+      ^bb(%a: f32, %s: f32):
         %0 = addf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -25,79 +28,6 @@ func @invalid_memref(%arga: memref<32xf32>, %argb: f32) -> tensor<32xf32> {
 
 // -----
 
-#trait_two_out = {
-  indexing_maps = [
-    affine_map<(i) -> (i)>,  // a
-    affine_map<(i) -> (i)>,  // x (out)
-    affine_map<(i) -> (i)>   // y (out)
-  ],
-  sparse = [
-    [ "S" ],  // a
-    [ "D" ],  // x
-    [ "D" ]   // y
-  ],
-  iterator_types = ["parallel"]
-}
-
-func @invalid_two_out(%arga: tensor<32xf32>) -> tensor<32xf32> {
-  // expected-error@+1 {{'linalg.generic' op expected single output tensor}}
-  %0, %1 = linalg.generic #trait_two_out
-    ins(%arga: tensor<32xf32>) {
-      ^bb(%a: f32):
-        %0 = addf %a, %a : f32
-        linalg.yield %a, %0 : f32, f32
-  } -> tensor<32xf32>, tensor<32xf32>
-  return %1 : tensor<32xf32>
-}
-
-// -----
-
-#trait_two_blocks = {
-  indexing_maps = [
-    affine_map<(i) -> (i)>,  // a
-    affine_map<(i) -> (i)>   // x (out)
-  ],
-  sparse = [
-    [ "S" ],  // a
-    [ "D" ]   // x
-  ],
-  iterator_types = ["parallel"]
-}
-
-func @invalid_two_blocks(%arga: tensor<32xf32>) -> tensor<32xf32> {
-  // expected-error@+1 {{'linalg.generic' op expects region #0 to have 0 or 1 blocks}}
-  %0 = linalg.generic #trait_two_blocks
-    ins(%arga: tensor<32xf32>) {
-      ^bb1(%a: f32):
-        %0 = addf %a, %a : f32
-      ^bb2:
-        linalg.yield %0 : f32
-  } -> tensor<32xf32>
-  return %0 : tensor<32xf32>
-}
-
-// -----
-
-#trait_no_block = {
-  indexing_maps = [
-    affine_map<(i) -> (i)>  // a
-  ],
-  sparse = [
-    [ "S" ]  // a
-  ],
-  iterator_types = ["parallel"]
-}
-
-func @invalid_no_block(%arga: tensor<32xf32>) {
-  // expected-error@+1 {{'linalg.generic' op expected region with 1 block}}
-  linalg.generic #trait_no_block
-    ins(%arga: tensor<32xf32>) {
-    }
-  return
-}
-
-// -----
-
 #trait_too_many = {
   indexing_maps = [
     affine_map<(i) -> (i)>,  // a
@@ -114,8 +44,9 @@ func @invalid_no_block(%arga: tensor<32xf32>) {
 func @invalid_too_many(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
   // expected-error@+1 {{'linalg.generic' op expected one sparse annotation for each tensor}}
   %0 = linalg.generic #trait_too_many
-    ins(%arga: tensor<32xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32xf32>)
+    outs(%arga: tensor<32xf32>) {
+      ^bb(%a: f32, %s: f32):
         %0 = addf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -136,8 +67,9 @@ func @invalid_too_many(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
 func @invalid_no_array(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
   // expected-error@+1 {{'linalg.generic' op expected sparse annotation array for tensor 0}}
   %0 = linalg.generic #trait_no_array
-    ins(%arga: tensor<32xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32xf32>)
+    outs(%arga: tensor<32xf32>) {
+      ^bb(%a: f32, %s: f32):
         %0 = addf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -161,8 +93,9 @@ func @invalid_no_array(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
 func @invalid_wrong_rank(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
   // expected-error@+1 {{'linalg.generic' op expected sparse annotation with rank 1 for tensor 1}}
   %0 = linalg.generic #trait_wrong_rank
-    ins(%arga: tensor<32xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32xf32>)
+    outs(%arga: tensor<32xf32>) {
+      ^bb(%a: f32, %s: f32):
         %0 = addf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32xf32>
@@ -186,8 +119,9 @@ func @invalid_wrong_rank(%arga: tensor<32xf32>, %argb: f32) -> tensor<32xf32> {
 func @invalid_no_string(%arga: tensor<32x16xf32>, %argb: f32) -> tensor<32x16xf32> {
   // expected-error@+1 {{'linalg.generic' op expected sparse annotation at position 1 for tensor 0}}
   %0 = linalg.generic #trait_no_string
-    ins(%arga: tensor<32x16xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32x16xf32>)
+    outs(%arga: tensor<32x16xf32>) {
+      ^bb(%a: f32, %s: f32):
         %0 = addf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -211,8 +145,9 @@ func @invalid_no_string(%arga: tensor<32x16xf32>, %argb: f32) -> tensor<32x16xf3
 func @invalid_wrong_symbol(%arga: tensor<32x16xf32>, %argb: f32) -> tensor<32x16xf32> {
   // expected-error@+1 {{'linalg.generic' op expected sparse annotation at position 1 for tensor 1}}
   %0 = linalg.generic #trait_wrong_symbol
-    ins(%arga: tensor<32x16xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32x16xf32>)
+    outs(%arga: tensor<32x16xf32>) {
+      ^bb(%a: f32, %s: f32):
         %0 = addf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
@@ -236,8 +171,9 @@ func @invalid_wrong_symbol(%arga: tensor<32x16xf32>, %argb: f32) -> tensor<32x16
 func @invalid_no_sparse_output(%arga: tensor<32x16xf32>, %argb: f32) -> tensor<32x16xf32> {
   // expected-error@+1 {{'linalg.generic' op sparse output tensors not supported (yet)}}
   %0 = linalg.generic #trait_no_sparse_output
-    ins(%arga: tensor<32x16xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<32x16xf32>)
+    outs(%arga: tensor<32x16xf32>) {
+      ^bb(%a: f32, %s: f32):
         %0 = addf %a, %argb  : f32
         linalg.yield %0 : f32
   } -> tensor<32x16xf32>
diff --git a/mlir/test/Dialect/Linalg/sparse_parallel.mlir b/mlir/test/Dialect/Linalg/sparse_parallel.mlir
index a75406fbab690..3d3d51ae03274 100644
--- a/mlir/test/Dialect/Linalg/sparse_parallel.mlir
+++ b/mlir/test/Dialect/Linalg/sparse_parallel.mlir
@@ -50,8 +50,9 @@
 //
 func @scale_dd(%scale: f32, %arga: tensor<?x?xf32>) -> tensor<?x?xf32> {
   %0 = linalg.generic #trait_dd
-    ins(%arga: tensor<?x?xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<?x?xf32>)
+    outs(%arga: tensor<?x?xf32>) {
+      ^bb(%a: f32, %s: f32):
         %0 = mulf %a, %scale  : f32
         linalg.yield %0 : f32
   } -> tensor<?x?xf32>
@@ -99,8 +100,9 @@ func @scale_dd(%scale: f32, %arga: tensor<?x?xf32>) -> tensor<?x?xf32> {
 //
 func @scale_ss(%scale: f32, %arga: tensor<?x?xf32>) -> tensor<?x?xf32> {
   %0 = linalg.generic #trait_ss
-    ins(%arga: tensor<?x?xf32>) {
-      ^bb(%a: f32):
+     ins(%arga: tensor<?x?xf32>)
+    outs(%arga: tensor<?x?xf32>) {
+      ^bb(%a: f32, %s: f32):
         %0 = mulf %a, %scale  : f32
         linalg.yield %0 : f32
   } -> tensor<?x?xf32>
@@ -151,7 +153,7 @@ func @scale_ss(%scale: f32, %arga: tensor<?x?xf32>) -> tensor<?x?xf32> {
 func @matvec(%argA: tensor<16x32xf32>, %argb: tensor<32xf32>, %argx: tensor<16xf32>) -> tensor<16xf32> {
   %0 = linalg.generic #trait_matvec
       ins(%argA, %argb : tensor<16x32xf32>, tensor<32xf32>)
-      init(%argx : tensor<16xf32>) {
+     outs(%argx : tensor<16xf32>) {
     ^bb(%A: f32, %b: f32, %x: f32):
       %0 = mulf %A, %b : f32
       %1 = addf %0, %x : f32
diff --git a/mlir/test/Dialect/Linalg/sparse_storage.mlir b/mlir/test/Dialect/Linalg/sparse_storage.mlir
index c63bdb1e413d3..69b8e1903d690 100644
--- a/mlir/test/Dialect/Linalg/sparse_storage.mlir
+++ b/mlir/test/Dialect/Linalg/sparse_storage.mlir
@@ -88,8 +88,9 @@
 
 func @mul_dd(%arga: tensor<32xf64>, %argb: tensor<32xf64>) -> tensor<32xf64> {
   %0 = linalg.generic #trait_mul_1d
-    ins(%arga, %argb: tensor<32xf64>, tensor<32xf64>) {
-      ^bb(%a: f64, %b: f64):
+     ins(%arga, %argb: tensor<32xf64>, tensor<32xf64>)
+    outs(%arga : tensor<32xf64>) {
+      ^bb(%a: f64, %b: f64, %s: f64):
         %0 = mulf %a, %b  : f64
         linalg.yield %0 : f64
   } -> tensor<32xf64>
diff --git a/mlir/test/Dialect/Linalg/tile-and-distribute.mlir b/mlir/test/Dialect/Linalg/tile-and-distribute.mlir
index 2a6a7ba7b7e34..fcecf896ac5dc 100644
--- a/mlir/test/Dialect/Linalg/tile-and-distribute.mlir
+++ b/mlir/test/Dialect/Linalg/tile-and-distribute.mlir
@@ -198,14 +198,14 @@ func @matmul_tensors(
 //      CHECK:       %[[sTB:.*]] = subtensor %[[TB]][{{.*}}] : tensor<?x?xf32> to tensor<?x?xf32>
 //      CHECK:       %[[sTC:.*]] = subtensor %[[TC2]][{{.*}}] : tensor<?x?xf32> to tensor<?x?xf32>
 //      CHECK:       %[[sTD:.*]] = linalg.matmul ins(%[[sTA]], %[[sTB]] : tensor<?x?xf32>, tensor<?x?xf32>)
-// CHECK-SAME:                                  init(%[[sTC]] : tensor<?x?xf32>)  -> tensor<?x?xf32>
+// CHECK-SAME:                                  outs(%[[sTC]] : tensor<?x?xf32>)  -> tensor<?x?xf32>
 //      CHECK:       %[[TD:.*]] = subtensor_insert %[[sTD]] into %[[TC2]][{{.*}}]  : tensor<?x?xf32> into tensor<?x?xf32>
 //      CHECK:       scf.yield %[[TD]] : tensor<?x?xf32>
 //      CHECK:     scf.yield %[[TD2]] : tensor<?x?xf32>
 //      CHECK:   scf.yield %[[TD1]] : tensor<?x?xf32>
   %0 = linalg.matmul {__internal_linalg_transform__ = "tensors_distribute1"}
        ins(%arg0, %arg1: tensor<?x?xf32>, tensor<?x?xf32>)
-      init(%arg2: tensor<?x?xf32>)
+      outs(%arg2: tensor<?x?xf32>)
     -> tensor<?x?xf32>
 
 //      CHECK: return %[[TD0]] : tensor<?x?xf32>
diff --git a/mlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir b/mlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir
index 41adff7d46c3f..9e96880885680 100644
--- a/mlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir
+++ b/mlir/test/Dialect/Linalg/tile-and-fuse-tensors.mlir
@@ -8,7 +8,7 @@
 
 func @matmul_tensors(%arg0: tensor<?x?xf32>, %arg1: tensor<?x?xf32>, %arg2: tensor<?x?xf32>) -> tensor<?x?xf32> {
   %t0 = linalg.matmul ins(%arg0, %arg1: tensor<?x?xf32>, tensor<?x?xf32>)
-                     init(%arg2: tensor<?x?xf32>)
+                     outs(%arg2: tensor<?x?xf32>)
     -> tensor<?x?xf32>
 
   %c4 = constant 4 : index
@@ -25,7 +25,7 @@ func @matmul_tensors(%arg0: tensor<?x?xf32>, %arg1: tensor<?x?xf32>, %arg2: tens
         %6 = subtensor %t0[%arg3, %arg7][%c2, 4][1, 1] : tensor<?x?xf32> to tensor<?x4xf32>
         %7 = subtensor %arg1[%arg7, %arg5][4, %c3][1, 1] : tensor<?x?xf32> to tensor<4x?xf32>
         %8 = subtensor %arg8[%arg3, %arg5][%c2, %c3][1, 1] : tensor<?x?xf32> to tensor<?x?xf32>
-        %9 = linalg.matmul ins(%6, %7 : tensor<?x4xf32>, tensor<4x?xf32>) init(%8 : tensor<?x?xf32>) -> tensor<?x?xf32>
+        %9 = linalg.matmul ins(%6, %7 : tensor<?x4xf32>, tensor<4x?xf32>) outs(%8 : tensor<?x?xf32>) -> tensor<?x?xf32>
         %10 = subtensor_insert %9 into %arg8[%arg3, %arg5] [%c2, %c3] [1, 1]  : tensor<?x?xf32> into tensor<?x?xf32>
         scf.yield %10 : tensor<?x?xf32>
       }
@@ -53,6 +53,6 @@ func @matmul_tensors(%arg0: tensor<?x?xf32>, %arg1: tensor<?x?xf32>, %arg2: tens
 // subtensors of the producing matmul.
 //   CHECK-DAG:       %[[stB2:.*]] = subtensor %[[B]][0, %[[K]]] [%[[dA1]], 4] [1, 1]  : tensor<?x?xf32> to tensor<?x4xf32>
 //   CHECK-DAG:       %[[stC:.*]] = subtensor %[[C]][%[[I]], %[[K]]] [2, 4] [1, 1]  : tensor<?x?xf32> to tensor<2x4xf32>
-//       CHECK:       %[[stD:.*]] = linalg.matmul ins(%[[stA]], %[[stB2]] : tensor<2x?xf32>, tensor<?x4xf32>) init(%[[stC]] : tensor<2x4xf32>)  -> tensor<2x4xf32>
-//  CHECK-NEXT:       %[[stG:.*]] = linalg.matmul ins(%[[stD]], %[[stB1]] : tensor<2x4xf32>, tensor<4x3xf32>) init(%[[stF]] : tensor<2x3xf32>)  -> tensor<2x3xf32>
+//       CHECK:       %[[stD:.*]] = linalg.matmul ins(%[[stA]], %[[stB2]] : tensor<2x?xf32>, tensor<?x4xf32>) outs(%[[stC]] : tensor<2x4xf32>)  -> tensor<2x4xf32>
+//  CHECK-NEXT:       %[[stG:.*]] = linalg.matmul ins(%[[stD]], %[[stB1]] : tensor<2x4xf32>, tensor<4x3xf32>) outs(%[[stF]] : tensor<2x3xf32>)  -> tensor<2x3xf32>
 //  CHECK-NEXT:       subtensor_insert %[[stG]] into %[[RES]][%[[I]], %[[J]]]
diff --git a/mlir/test/Dialect/Linalg/tile-tensors.mlir b/mlir/test/Dialect/Linalg/tile-tensors.mlir
index b899cb3e00495..787ea8d2b395b 100644
--- a/mlir/test/Dialect/Linalg/tile-tensors.mlir
+++ b/mlir/test/Dialect/Linalg/tile-tensors.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-opt %s -linalg-tile="linalg-tile-sizes=2,3,4" -mlir-disable-threading=true | FileCheck %s
+// RUN: mlir-opt %s -linalg-tile="linalg-tile-sizes=2,3,4" | FileCheck %s
 
 // CHECK-LABEL: func @matmul_tensors(
 // CHECK-SAME:    %[[TA:[0-9a-z]+]]: tensor<?x?xf32>
@@ -14,13 +14,13 @@ func @matmul_tensors(
 //      CHECK:       %[[sTB:.*]] = subtensor %[[TB]][{{.*}}] : tensor<?x?xf32> to tensor<?x?xf32>
 //      CHECK:       %[[sTC:.*]] = subtensor %[[TC2]][{{.*}}] : tensor<?x?xf32> to tensor<?x?xf32>
 //      CHECK:       %[[sTD:.*]] = linalg.matmul ins(%[[sTA]], %[[sTB]] : tensor<?x?xf32>, tensor<?x?xf32>)
-// CHECK-SAME:                                  init(%[[sTC]] : tensor<?x?xf32>)  -> tensor<?x?xf32>
+// CHECK-SAME:                                  outs(%[[sTC]] : tensor<?x?xf32>)  -> tensor<?x?xf32>
 //      CHECK:       %[[TD:.*]] = subtensor_insert %[[sTD]] into %[[TC2]][{{.*}}]  : tensor<?x?xf32> into tensor<?x?xf32>
 //      CHECK:       scf.yield %[[TD]] : tensor<?x?xf32>
 //      CHECK:     scf.yield %[[TD2]] : tensor<?x?xf32>
 //      CHECK:   scf.yield %[[TD1]] : tensor<?x?xf32>
   %0 = linalg.matmul  ins(%arg0, %arg1: tensor<?x?xf32>, tensor<?x?xf32>)
-                     init(%arg2: tensor<?x?xf32>)
+                     outs(%arg2: tensor<?x?xf32>)
     -> tensor<?x?xf32>
 
 //      CHECK: return %[[TD0]] : tensor<?x?xf32>
diff --git a/mlir/test/Dialect/SPIRV/Transforms/glsl_canonicalize.mlir b/mlir/test/Dialect/SPIRV/Transforms/glsl_canonicalize.mlir
new file mode 100644
index 0000000000000..90e9b85b9035b
--- /dev/null
+++ b/mlir/test/Dialect/SPIRV/Transforms/glsl_canonicalize.mlir
@@ -0,0 +1,113 @@
+// RUN: mlir-opt -test-spirv-glsl-canonicalization -split-input-file -verify-diagnostics %s | FileCheck %s
+
+// CHECK: func @clamp_fordlessthan(%[[INPUT:.*]]: f32)
+func @clamp_fordlessthan(%input: f32) -> f32 {
+  // CHECK: %[[MIN:.*]] = spv.constant
+  %min = spv.constant 0.5 : f32
+  // CHECK: %[[MAX:.*]] = spv.constant
+  %max = spv.constant 1.0 : f32
+
+  // CHECK: [[RES:%.*]] = spv.GLSL.FClamp %[[INPUT]], %[[MIN]], %[[MAX]]
+  %0 = spv.FOrdLessThan %min, %input : f32
+  %mid = spv.Select %0, %input, %min : i1, f32
+  %1 = spv.FOrdLessThan %mid, %max : f32
+  %2 = spv.Select %1, %mid, %max : i1, f32
+
+  // CHECK-NEXT: spv.ReturnValue [[RES]]
+  spv.ReturnValue %2 : f32
+}
+
+// -----
+
+// CHECK: func @clamp_fordlessthanequal(%[[INPUT:.*]]: f32)
+func @clamp_fordlessthanequal(%input: f32) -> f32 {
+  // CHECK: %[[MIN:.*]] = spv.constant
+  %min = spv.constant 0.5 : f32
+  // CHECK: %[[MAX:.*]] = spv.constant
+  %max = spv.constant 1.0 : f32
+
+  // CHECK: [[RES:%.*]] = spv.GLSL.FClamp %[[INPUT]], %[[MIN]], %[[MAX]]
+  %0 = spv.FOrdLessThanEqual %min, %input : f32
+  %mid = spv.Select %0, %input, %min : i1, f32
+  %1 = spv.FOrdLessThanEqual %mid, %max : f32
+  %2 = spv.Select %1, %mid, %max : i1, f32
+
+  // CHECK-NEXT: spv.ReturnValue [[RES]]
+  spv.ReturnValue %2 : f32
+}
+
+// -----
+
+// CHECK: func @clamp_slessthan(%[[INPUT:.*]]: si32)
+func @clamp_slessthan(%input: si32) -> si32 {
+  // CHECK: %[[MIN:.*]] = spv.constant
+  %min = spv.constant 0 : si32
+  // CHECK: %[[MAX:.*]] = spv.constant
+  %max = spv.constant 10 : si32
+
+  // CHECK: [[RES:%.*]] = spv.GLSL.SClamp %[[INPUT]], %[[MIN]], %[[MAX]]
+  %0 = spv.SLessThan %min, %input : si32
+  %mid = spv.Select %0, %input, %min : i1, si32
+  %1 = spv.SLessThan %mid, %max : si32
+  %2 = spv.Select %1, %mid, %max : i1, si32
+
+  // CHECK-NEXT: spv.ReturnValue [[RES]]
+  spv.ReturnValue %2 : si32
+}
+
+// -----
+
+// CHECK: func @clamp_slessthanequal(%[[INPUT:.*]]: si32)
+func @clamp_slessthanequal(%input: si32) -> si32 {
+  // CHECK: %[[MIN:.*]] = spv.constant
+  %min = spv.constant 0 : si32
+  // CHECK: %[[MAX:.*]] = spv.constant
+  %max = spv.constant 10 : si32
+
+  // CHECK: [[RES:%.*]] = spv.GLSL.SClamp %[[INPUT]], %[[MIN]], %[[MAX]]
+  %0 = spv.SLessThanEqual %min, %input : si32
+  %mid = spv.Select %0, %input, %min : i1, si32
+  %1 = spv.SLessThanEqual %mid, %max : si32
+  %2 = spv.Select %1, %mid, %max : i1, si32
+
+  // CHECK-NEXT: spv.ReturnValue [[RES]]
+  spv.ReturnValue %2 : si32
+}
+
+// -----
+
+// CHECK: func @clamp_ulessthan(%[[INPUT:.*]]: i32)
+func @clamp_ulessthan(%input: i32) -> i32 {
+  // CHECK: %[[MIN:.*]] = spv.constant
+  %min = spv.constant 0 : i32
+  // CHECK: %[[MAX:.*]] = spv.constant
+  %max = spv.constant 10 : i32
+
+  // CHECK: [[RES:%.*]] = spv.GLSL.UClamp %[[INPUT]], %[[MIN]], %[[MAX]]
+  %0 = spv.ULessThan %min, %input : i32
+  %mid = spv.Select %0, %input, %min : i1, i32
+  %1 = spv.ULessThan %mid, %max : i32
+  %2 = spv.Select %1, %mid, %max : i1, i32
+
+  // CHECK-NEXT: spv.ReturnValue [[RES]]
+  spv.ReturnValue %2 : i32
+}
+
+// -----
+
+// CHECK: func @clamp_ulessthanequal(%[[INPUT:.*]]: i32)
+func @clamp_ulessthanequal(%input: i32) -> i32 {
+  // CHECK: %[[MIN:.*]] = spv.constant
+  %min = spv.constant 0 : i32
+  // CHECK: %[[MAX:.*]] = spv.constant
+  %max = spv.constant 10 : i32
+
+  // CHECK: [[RES:%.*]] = spv.GLSL.UClamp %[[INPUT]], %[[MIN]], %[[MAX]]
+  %0 = spv.ULessThanEqual %min, %input : i32
+  %mid = spv.Select %0, %input, %min : i1, i32
+  %1 = spv.ULessThanEqual %mid, %max : i32
+  %2 = spv.Select %1, %mid, %max : i1, i32
+
+  // CHECK-NEXT: spv.ReturnValue [[RES]]
+  spv.ReturnValue %2 : i32
+}
diff --git a/mlir/test/Dialect/Vector/canonicalize.mlir b/mlir/test/Dialect/Vector/canonicalize.mlir
index f07285d7d98c9..f94c3bcce5bec 100644
--- a/mlir/test/Dialect/Vector/canonicalize.mlir
+++ b/mlir/test/Dialect/Vector/canonicalize.mlir
@@ -613,4 +613,51 @@ func @extract_strided_constant() -> (vector<12x2xf32>, vector<2x13x3xi32>) {
   return %0, %1 : vector<12x2xf32>, vector<2x13x3xi32>
 }
 
+// -----
+
+// CHECK-LABEL: extract_strided_broadcast
+//       CHECK:   %[[B:.*]] = vector.broadcast %{{.*}} : vector<4xf16> to vector<2x4xf16>
+//  CHECK-NEXT:   return %[[B]] : vector<2x4xf16>
+func @extract_strided_broadcast(%arg0: vector<4xf16>) -> vector<2x4xf16> {
+ %0 = vector.broadcast %arg0 : vector<4xf16> to vector<16x4xf16>
+ %1 = vector.extract_strided_slice %0
+  {offsets = [0, 0], sizes = [2, 4], strides = [1, 1]} :
+  vector<16x4xf16> to vector<2x4xf16>
+  return %1 : vector<2x4xf16>
+}
+
+// -----
+
+// CHECK-LABEL: extract_strided_broadcast2
+//       CHECK:   %[[E:.*]] = vector.extract_strided_slice %{{.*}} {offsets = [0], sizes = [2], strides = [1]} : vector<4xf16> to vector<2xf16>
+//  CHECK-NEXT:   %[[B:.*]] = vector.broadcast %[[E]] : vector<2xf16> to vector<2x2xf16>
+//  CHECK-NEXT:   return %[[B]] : vector<2x2xf16>
+func @extract_strided_broadcast2(%arg0: vector<4xf16>) -> vector<2x2xf16> {
+ %0 = vector.broadcast %arg0 : vector<4xf16> to vector<16x4xf16>
+ %1 = vector.extract_strided_slice %0
+  {offsets = [0, 0], sizes = [2, 2], strides = [1, 1]} :
+  vector<16x4xf16> to vector<2x2xf16>
+  return %1 : vector<2x2xf16>
+}
+
+// -----
+
+// CHECK-LABEL: consecutive_shape_cast
+//       CHECK:   %[[C:.*]] = vector.shape_cast %{{.*}} : vector<16xf16> to vector<4x4xf16>
+//  CHECK-NEXT:   return %[[C]] : vector<4x4xf16>
+func @consecutive_shape_cast(%arg0: vector<16xf16>) -> vector<4x4xf16> {
+  %0 = vector.shape_cast %arg0 : vector<16xf16> to vector<2x8xf16>
+  %1 = vector.shape_cast %0 : vector<2x8xf16> to vector<4x4xf16>
+  return %1 : vector<4x4xf16>
+}
+
+// -----
+
+// CHECK-LABEL: broadcast_to_shapecast
+//       CHECK:   %[[C:.*]] = vector.shape_cast %{{.*}} : vector<4x4xf16> to vector<1x4x4xf16>
+//  CHECK-NEXT:   return %[[C]] : vector<1x4x4xf16>
+func @broadcast_to_shapecast(%arg0: vector<4x4xf16>) -> vector<1x4x4xf16> {
+  %0 = vector.broadcast %arg0 : vector<4x4xf16> to vector<1x4x4xf16>
+  return %0 : vector<1x4x4xf16>
+}
 
diff --git a/mlir/test/Dialect/Vector/invalid.mlir b/mlir/test/Dialect/Vector/invalid.mlir
index 73b1f9e1e06ef..62eaa4e3a14e1 100644
--- a/mlir/test/Dialect/Vector/invalid.mlir
+++ b/mlir/test/Dialect/Vector/invalid.mlir
@@ -269,7 +269,7 @@ func @test_vector.transfer_read(%arg0: vector<4x3xf32>) {
   %c3 = constant 3 : index
   %f0 = constant 0.0 : f32
   %vf0 = splat %f0 : vector<4x3xf32>
-  // expected-error@+1 {{ requires memref type}}
+  // expected-error@+1 {{ requires memref or ranked tensor type}}
   %0 = vector.transfer_read %arg0[%c3, %c3], %vf0 : vector<4x3xf32>, vector<1x1x2x3xf32>
 }
 
@@ -297,7 +297,7 @@ func @test_vector.transfer_read(%arg0: memref<?x?xf32>) {
 func @test_vector.transfer_read(%arg0: memref<?x?xf32>) {
   %c3 = constant 3 : index
   %cst = constant 3.0 : f32
-  // expected-error@+1 {{requires a permutation_map with input dims of the same rank as the memref type}}
+  // expected-error@+1 {{requires a permutation_map with input dims of the same rank as the source type}}
   %0 = vector.transfer_read %arg0[%c3, %c3], %cst {permutation_map = affine_map<(d0)->(d0)>} : memref<?x?xf32>, vector<128xf32>
 }
 
@@ -343,7 +343,7 @@ func @test_vector.transfer_read(%arg0: memref<?x?xvector<4x3xf32>>) {
   %c3 = constant 3 : index
   %f0 = constant 0.0 : f32
   %vf0 = splat %f0 : vector<4x3xf32>
-  // expected-error@+1 {{requires memref vector element and vector result ranks to match}}
+  // expected-error@+1 {{requires source vector element and vector result ranks to match}}
   %0 = vector.transfer_read %arg0[%c3, %c3], %vf0 {permutation_map = affine_map<(d0, d1)->(d0, d1)>} : memref<?x?xvector<4x3xf32>>, vector<3xf32>
 }
 
@@ -353,7 +353,7 @@ func @test_vector.transfer_read(%arg0: memref<?x?xvector<6xf32>>) {
   %c3 = constant 3 : index
   %f0 = constant 0.0 : f32
   %vf0 = splat %f0 : vector<6xf32>
-  // expected-error@+1 {{requires the bitwidth of the minor 1-D vector to be an integral multiple of the bitwidth of the minor 1-D vector of the memref}}
+  // expected-error@+1 {{requires the bitwidth of the minor 1-D vector to be an integral multiple of the bitwidth of the minor 1-D vector of the source}}
   %0 = vector.transfer_read %arg0[%c3, %c3], %vf0 : memref<?x?xvector<6xf32>>, vector<3xf32>
 }
 
@@ -392,7 +392,7 @@ func @test_vector.transfer_write(%arg0: vector<4x3xf32>) {
   %c3 = constant 3 : index
   %f0 = constant 0.0 : f32
   %vf0 = splat %f0 : vector<4x3xf32>
-  // expected-error@+1 {{ requires memref type}}
+  // expected-error@+1 {{ requires memref or ranked tensor type}}
   vector.transfer_write %arg0, %arg0[%c3, %c3] : vector<4x3xf32>, f32
 }
 
@@ -419,7 +419,7 @@ func @test_vector.transfer_write(%arg0: memref<?x?xf32>) {
 func @test_vector.transfer_write(%arg0: memref<?x?xf32>) {
   %c3 = constant 3 : index
   %cst = constant dense<3.0> : vector<128 x f32>
-  // expected-error@+1 {{requires a permutation_map with input dims of the same rank as the memref type}}
+  // expected-error@+1 {{requires a permutation_map with input dims of the same rank as the source type}}
   vector.transfer_write %cst, %arg0[%c3, %c3] {permutation_map = affine_map<(d0)->(d0)>} : vector<128xf32>, memref<?x?xf32>
 }
 
diff --git a/mlir/test/Dialect/Vector/ops.mlir b/mlir/test/Dialect/Vector/ops.mlir
index aab6cabf759d8..07e9d8de3f493 100644
--- a/mlir/test/Dialect/Vector/ops.mlir
+++ b/mlir/test/Dialect/Vector/ops.mlir
@@ -43,6 +43,54 @@ func @vector_transfer_ops(%arg0: memref<?x?xf32>,
   return
 }
 
+
+// CHECK-LABEL: func @vector_transfer_ops_tensor(
+func @vector_transfer_ops_tensor(%arg0: tensor<?x?xf32>,
+                          %arg1 : tensor<?x?xvector<4x3xf32>>,
+                          %arg2 : tensor<?x?xvector<4x3xi32>>) ->
+  (tensor<?x?xf32>, tensor<?x?xf32>, tensor<?x?xvector<4x3xf32>>,
+   tensor<?x?xvector<4x3xf32>>, tensor<?x?xvector<4x3xi32>>){
+  // CHECK: %[[C3:.*]] = constant 3 : index
+  %c3 = constant 3 : index
+  %cst = constant 3.0 : f32
+  %f0 = constant 0.0 : f32
+  %c0 = constant 0 : i32
+  %vf0 = splat %f0 : vector<4x3xf32>
+  %v0 = splat %c0 : vector<4x3xi32>
+
+  //
+  // CHECK: vector.transfer_read
+  %0 = vector.transfer_read %arg0[%c3, %c3], %f0 {permutation_map = affine_map<(d0, d1)->(d0)>} : tensor<?x?xf32>, vector<128xf32>
+  // CHECK: vector.transfer_read
+  %1 = vector.transfer_read %arg0[%c3, %c3], %f0 {permutation_map = affine_map<(d0, d1)->(d1, d0)>} : tensor<?x?xf32>, vector<3x7xf32>
+  // CHECK: vector.transfer_read
+  %2 = vector.transfer_read %arg0[%c3, %c3], %cst {permutation_map = affine_map<(d0, d1)->(d0)>} : tensor<?x?xf32>,  vector<128xf32>
+  // CHECK: vector.transfer_read
+  %3 = vector.transfer_read %arg0[%c3, %c3], %cst {permutation_map = affine_map<(d0, d1)->(d1)>} : tensor<?x?xf32>,  vector<128xf32>
+  // CHECK: vector.transfer_read %{{.*}}[%[[C3]], %[[C3]]], %{{.*}} : tensor<?x?xvector<4x3xf32>>, vector<1x1x4x3xf32>
+  %4 = vector.transfer_read %arg1[%c3, %c3], %vf0 {permutation_map = affine_map<(d0, d1)->(d0, d1)>} : tensor<?x?xvector<4x3xf32>>, vector<1x1x4x3xf32>
+  // CHECK: vector.transfer_read %{{.*}}[%[[C3]], %[[C3]]], %{{.*}} {masked = [true, false]} : tensor<?x?xvector<4x3xf32>>, vector<1x1x4x3xf32>
+  %5 = vector.transfer_read %arg1[%c3, %c3], %vf0 {masked = [true, false]} : tensor<?x?xvector<4x3xf32>>, vector<1x1x4x3xf32>
+  // CHECK: vector.transfer_read %{{.*}}[%[[C3]], %[[C3]]], %{{.*}} : tensor<?x?xvector<4x3xi32>>, vector<5x24xi8>
+  %6 = vector.transfer_read %arg2[%c3, %c3], %v0 : tensor<?x?xvector<4x3xi32>>, vector<5x24xi8>
+
+
+  // CHECK: vector.transfer_write
+  %7 = vector.transfer_write %0, %arg0[%c3, %c3] {permutation_map = affine_map<(d0, d1)->(d0)>} : vector<128xf32>, tensor<?x?xf32>
+  // CHECK: vector.transfer_write
+  %8 = vector.transfer_write %1, %arg0[%c3, %c3] {permutation_map = affine_map<(d0, d1)->(d1, d0)>} : vector<3x7xf32>, tensor<?x?xf32>
+  // CHECK: vector.transfer_write %{{.*}}, %{{.*}}[%[[C3]], %[[C3]]] : vector<1x1x4x3xf32>, tensor<?x?xvector<4x3xf32>>
+  %9 = vector.transfer_write %4, %arg1[%c3, %c3] {permutation_map = affine_map<(d0, d1)->(d0, d1)>} : vector<1x1x4x3xf32>, tensor<?x?xvector<4x3xf32>>
+  // CHECK: vector.transfer_write %{{.*}}, %{{.*}}[%[[C3]], %[[C3]]] : vector<1x1x4x3xf32>, tensor<?x?xvector<4x3xf32>>
+  %10 = vector.transfer_write %5, %arg1[%c3, %c3] {masked = [true, true]} : vector<1x1x4x3xf32>, tensor<?x?xvector<4x3xf32>>
+  // CHECK: vector.transfer_write %{{.*}}, %{{.*}}[%[[C3]], %[[C3]]] : vector<5x24xi8>, tensor<?x?xvector<4x3xi32>>
+  %11 = vector.transfer_write %6, %arg2[%c3, %c3] : vector<5x24xi8>, tensor<?x?xvector<4x3xi32>>
+
+  return %7, %8, %9, %10, %11 :
+    tensor<?x?xf32>, tensor<?x?xf32>,  tensor<?x?xvector<4x3xf32>>,
+    tensor<?x?xvector<4x3xf32>>, tensor<?x?xvector<4x3xi32>>
+}
+
 // CHECK-LABEL: @vector_broadcast
 func @vector_broadcast(%a: f32, %b: vector<16xf32>, %c: vector<1x16xf32>, %d: vector<8x1xf32>) -> vector<8x16xf32> {
   // CHECK: vector.broadcast %{{.*}} : f32 to vector<16xf32>
diff --git a/mlir/test/Dialect/Vector/vector-transforms.mlir b/mlir/test/Dialect/Vector/vector-transforms.mlir
index 167314d36458e..43a83f04dd304 100644
--- a/mlir/test/Dialect/Vector/vector-transforms.mlir
+++ b/mlir/test/Dialect/Vector/vector-transforms.mlir
@@ -1,5 +1,4 @@
 // RUN: mlir-opt %s -test-vector-to-vector-conversion | FileCheck %s
-// RUN: mlir-opt %s -test-vector-unrolling-patterns | FileCheck %s
 
 // CHECK-DAG: #[[MAP1:map[0-9]+]] = affine_map<(d0, d1, d2) -> (d1, d2)>
 
@@ -514,3 +513,38 @@ func @shape_cast_fold(%arg0 : vector<5x4x2xf32>, %arg1 : vector<3x4x2xf32>)
 
   return %6, %7 : vector<5x4x2xf32>, vector<3x4x2xf32>
 }
+
+// CHECK-LABEL: func @elementwise_unroll
+//  CHECK-SAME: (%[[ARG0:.*]]: memref<4x4xf32>, %[[ARG1:.*]]: memref<4x4xf32>)
+//       CHECK:   %[[C0:.*]] = constant 0 : index
+//       CHECK:   %[[C2:.*]] = constant 2 : index
+//       CHECK:   %[[VT0:.*]] = vector.transfer_read %[[ARG0]][%[[C0]], %[[C0]]], {{.*}} : memref<4x4xf32>, vector<2x2xf32>
+//       CHECK:   %[[VT1:.*]] = vector.transfer_read %[[ARG0]][%[[C0]], %[[C2]]], {{.*}} : memref<4x4xf32>, vector<2x2xf32>
+//       CHECK:   %[[VT2:.*]] = vector.transfer_read %[[ARG0]][%[[C2]], %[[C0]]], {{.*}} : memref<4x4xf32>, vector<2x2xf32>
+//       CHECK:   %[[VT3:.*]] = vector.transfer_read %[[ARG0]][%[[C2]], %[[C2]]], {{.*}} : memref<4x4xf32>, vector<2x2xf32>
+//       CHECK:   %[[VT4:.*]] = vector.transfer_read %[[ARG1]][%[[C0]], %[[C0]]], {{.*}} : memref<4x4xf32>, vector<2x2xf32>
+//       CHECK:   %[[VT5:.*]] = vector.transfer_read %[[ARG1]][%[[C0]], %[[C2]]], {{.*}} : memref<4x4xf32>, vector<2x2xf32>
+//       CHECK:   %[[VT6:.*]] = vector.transfer_read %[[ARG1]][%[[C2]], %[[C0]]], {{.*}} : memref<4x4xf32>, vector<2x2xf32>
+//       CHECK:   %[[VT7:.*]] = vector.transfer_read %[[ARG1]][%[[C2]], %[[C2]]], {{.*}} : memref<4x4xf32>, vector<2x2xf32>
+//       CHECK:   %[[CMP0:.*]] = cmpf "ult", %[[VT0]], %[[VT4]] : vector<2x2xf32>
+//       CHECK:   %[[CMP1:.*]] = cmpf "ult", %[[VT1]], %[[VT5]] : vector<2x2xf32>
+//       CHECK:   %[[CMP2:.*]] = cmpf "ult", %[[VT2]], %[[VT6]] : vector<2x2xf32>
+//       CHECK:   %[[CMP3:.*]] = cmpf "ult", %[[VT3]], %[[VT7]] : vector<2x2xf32>
+//       CHECK:   %[[SEL0:.*]] = select %[[CMP0]], %[[VT0]], %[[VT4]] : vector<2x2xi1>, vector<2x2xf32>
+//       CHECK:   %[[SEL1:.*]] = select %[[CMP1]], %[[VT1]], %[[VT5]] : vector<2x2xi1>, vector<2x2xf32>
+//       CHECK:   %[[SEL2:.*]] = select %[[CMP2]], %[[VT2]], %[[VT6]] : vector<2x2xi1>, vector<2x2xf32>
+//       CHECK:   %[[SEL3:.*]] = select %[[CMP3]], %[[VT3]], %[[VT7]] : vector<2x2xi1>, vector<2x2xf32>
+//       CHECK:   vector.transfer_write %[[SEL0]], %[[ARG0]][%[[C0]], %[[C0]]] {{.*}} : vector<2x2xf32>, memref<4x4xf32>
+//       CHECK:   vector.transfer_write %[[SEL1]], %[[ARG0]][%[[C0]], %[[C2]]] {{.*}} : vector<2x2xf32>, memref<4x4xf32>
+//       CHECK:   vector.transfer_write %[[SEL2]], %[[ARG0]][%[[C2]], %[[C0]]] {{.*}} : vector<2x2xf32>, memref<4x4xf32>
+//       CHECK:   vector.transfer_write %[[SEL3]], %[[ARG0]][%[[C2]], %[[C2]]] {{.*}} : vector<2x2xf32>, memref<4x4xf32>
+func @elementwise_unroll(%arg0 : memref<4x4xf32>, %arg1 : memref<4x4xf32>) {
+  %c0 = constant 0 : index
+  %cf0 = constant 0.0 : f32
+  %0 = vector.transfer_read %arg0[%c0, %c0], %cf0 : memref<4x4xf32>, vector<4x4xf32>
+  %1 = vector.transfer_read %arg1[%c0, %c0], %cf0 : memref<4x4xf32>, vector<4x4xf32>
+  %cond = cmpf "ult", %0, %1 : vector<4x4xf32>
+  %2 = select %cond, %0, %1 : vector<4x4xi1>, vector<4x4xf32>
+  vector.transfer_write %2, %arg0[%c0, %c0] : vector<4x4xf32>, memref<4x4xf32>
+  return
+}
diff --git a/mlir/test/EDSC/builder-api-test.cpp b/mlir/test/EDSC/builder-api-test.cpp
index b713ae98b1073..db200ba5f90ff 100644
--- a/mlir/test/EDSC/builder-api-test.cpp
+++ b/mlir/test/EDSC/builder-api-test.cpp
@@ -1101,7 +1101,7 @@ TEST_FUNC(linalg_metadata_ops) {
 //  CHECK-SAME:                      affine_map<(d0, d1, d2) -> (d0, d1)>],
 //  CHECK-SAME:     iterator_types = ["parallel", "parallel", "reduction"]
 // CHECK-SAME: ins(%{{[a-z0-9]*}}, %{{[a-z0-9]*}} : tensor<?x?xf32>, memref<?x?xf32>)
-// CHECK-SAME: init(%{{[a-z0-9]*}} : tensor<?x?xf32>)
+// CHECK-SAME: outs(%{{[a-z0-9]*}} : tensor<?x?xf32>)
 //       CHECK:     mulf
 //       CHECK:     addf
 //       CHECK:   } -> tensor<?x?xf32>
@@ -1115,14 +1115,15 @@ TEST_FUNC(linalg_tensors_test) {
       {ShapedType::kDynamicSize, ShapedType::kDynamicSize}, f32Type, {}, 0);
   auto tensorType = RankedTensorType::get(
       {ShapedType::kDynamicSize, ShapedType::kDynamicSize}, f32Type);
-  auto f = makeFunction("linalg_tensors", {}, {tensorType, memrefType});
+  auto f =
+      makeFunction("linalg_tensors", {}, {tensorType, memrefType, tensorType});
 
   OpBuilder builder(f.getBody());
   ScopedContext scope(builder, f.getLoc());
-  Value A(f.getArgument(0)), B(f.getArgument(1));
+  Value A(f.getArgument(0)), B(f.getArgument(1)), C(f.getArgument(2));
   AffineExpr i, j;
   bindDims(&globalContext(), i, j);
-  StructuredIndexed SA(A), SB(B), SC(tensorType);
+  StructuredIndexed SA(A), SB(B), SC(C);
   Value added = linalg_generic_pointwise_add(SA({i, j}), SB({i, j}), SC({i, j}))
                     ->getResult(0);
   Value maxed = linalg_generic_pointwise_max(
@@ -1223,7 +1224,8 @@ TEST_FUNC(builder_loop_for_yield) {
                                  [&](Value iv, ValueRange args) {
                                    Value sum = args[0] + args[1];
                                    return scf::ValueVector{args[1], sum};
-                                 }).getResults();
+                                 })
+                     .getResults();
   results[0] + results[1];
 
   // clang-format off
diff --git a/mlir/test/Target/openmp-llvm.mlir b/mlir/test/Target/openmp-llvm.mlir
index 0651c6f5df408..c5ef16f4393d0 100644
--- a/mlir/test/Target/openmp-llvm.mlir
+++ b/mlir/test/Target/openmp-llvm.mlir
@@ -1,4 +1,4 @@
-// RUN: mlir-translate -mlir-to-llvmir %s | FileCheck %s
+// RUN: mlir-translate -mlir-to-llvmir -split-input-file %s | FileCheck %s
 
 // CHECK-LABEL: define void @test_stand_alone_directives()
 llvm.func @test_stand_alone_directives() {
@@ -291,3 +291,35 @@ llvm.func @test_omp_master() -> () {
   }
   llvm.return
 }
+
+// -----
+
+// CHECK: %struct.ident_t = type
+// CHECK: @[[$parallel_loc:.*]] = private unnamed_addr constant {{.*}} c";LLVMDialectModule;wsloop_simple;{{[0-9]+}};{{[0-9]+}};;\00"
+// CHECK: @[[$parallel_loc_struct:.*]] = private unnamed_addr constant %struct.ident_t {{.*}} @[[$parallel_loc]], {{.*}}
+
+// CHECK: @[[$wsloop_loc:.*]] = private unnamed_addr constant {{.*}} c";LLVMDialectModule;wsloop_simple;{{[0-9]+}};{{[0-9]+}};;\00"
+// CHECK: @[[$wsloop_loc_struct:.*]] = private unnamed_addr constant %struct.ident_t {{.*}} @[[$wsloop_loc]], {{.*}}
+
+// CHECK-LABEL: @wsloop_simple
+llvm.func @wsloop_simple(%arg0: !llvm.ptr<float>) {
+  %0 = llvm.mlir.constant(42 : index) : !llvm.i64
+  %1 = llvm.mlir.constant(10 : index) : !llvm.i64
+  %2 = llvm.mlir.constant(1 : index) : !llvm.i64
+  omp.parallel {
+    "omp.wsloop"(%1, %0, %2) ( {
+    ^bb0(%arg1: !llvm.i64):
+      // The form of the emitted IR is controlled by OpenMPIRBuilder and
+      // tested there. Just check that the right functions are called.
+      // CHECK: call i32 @__kmpc_global_thread_num
+      // CHECK: call void @__kmpc_for_static_init_{{.*}}(%struct.ident_t* @[[$wsloop_loc_struct]],
+      %3 = llvm.mlir.constant(2.000000e+00 : f32) : !llvm.float
+      %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr<float>, !llvm.i64) -> !llvm.ptr<float>
+      llvm.store %3, %4 : !llvm.ptr<float>
+      omp.yield
+      // CHECK: call void @__kmpc_for_static_fini(%struct.ident_t* @[[$wsloop_loc_struct]],
+    }) {operand_segment_sizes = dense<[1, 1, 1, 0, 0, 0, 0, 0, 0]> : vector<9xi32>} : (!llvm.i64, !llvm.i64, !llvm.i64) -> ()
+    omp.terminator
+  }
+  llvm.return
+}
diff --git a/mlir/test/lib/Dialect/SPIRV/CMakeLists.txt b/mlir/test/lib/Dialect/SPIRV/CMakeLists.txt
index edcbf4ebf1de0..856e5eb7f40da 100644
--- a/mlir/test/lib/Dialect/SPIRV/CMakeLists.txt
+++ b/mlir/test/lib/Dialect/SPIRV/CMakeLists.txt
@@ -2,6 +2,7 @@
 add_mlir_library(MLIRSPIRVTestPasses
   TestAvailability.cpp
   TestEntryPointAbi.cpp
+  TestGLSLCanonicalization.cpp
   TestModuleCombiner.cpp
 
   EXCLUDE_FROM_LIBMLIR
diff --git a/mlir/test/lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp b/mlir/test/lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp
new file mode 100644
index 0000000000000..158601fbc17ab
--- /dev/null
+++ b/mlir/test/lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp
@@ -0,0 +1,39 @@
+//===- TestGLSLCanonicalization.cpp - Pass to test GLSL-specific pattterns ===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "mlir/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h"
+#include "mlir/Dialect/SPIRV/IR/SPIRVModule.h"
+#include "mlir/Pass/Pass.h"
+#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
+
+using namespace mlir;
+
+namespace {
+class TestGLSLCanonicalizationPass
+    : public PassWrapper<TestGLSLCanonicalizationPass,
+                         OperationPass<mlir::ModuleOp>> {
+public:
+  TestGLSLCanonicalizationPass() = default;
+  TestGLSLCanonicalizationPass(const TestGLSLCanonicalizationPass &) {}
+  void runOnOperation() override;
+};
+} // namespace
+
+void TestGLSLCanonicalizationPass::runOnOperation() {
+  OwningRewritePatternList patterns;
+  spirv::populateSPIRVGLSLCanonicalizationPatterns(patterns, &getContext());
+  applyPatternsAndFoldGreedily(getOperation(), std::move(patterns));
+}
+
+namespace mlir {
+void registerTestSpirvGLSLCanonicalizationPass() {
+  PassRegistration<TestGLSLCanonicalizationPass> registration(
+      "test-spirv-glsl-canonicalization",
+      "Tests SPIR-V canonicalization patterns for GLSL extension.");
+}
+} // namespace mlir
diff --git a/mlir/test/lib/Transforms/TestConvertCallOp.cpp b/mlir/test/lib/Transforms/TestConvertCallOp.cpp
index 61062c7938fe2..82cc95aac8a82 100644
--- a/mlir/test/lib/Transforms/TestConvertCallOp.cpp
+++ b/mlir/test/lib/Transforms/TestConvertCallOp.cpp
@@ -45,7 +45,8 @@ class TestConvertCallOp
     // Populate type conversions.
     LLVMTypeConverter type_converter(m.getContext());
     type_converter.addConversion([&](test::TestType type) {
-      return LLVM::LLVMType::getInt8PtrTy(m.getContext());
+      return LLVM::LLVMPointerType::get(
+          LLVM::LLVMIntegerType::get(m.getContext(), 8));
     });
 
     // Populate patterns.
diff --git a/mlir/test/lib/Transforms/TestVectorTransforms.cpp b/mlir/test/lib/Transforms/TestVectorTransforms.cpp
index 99c336ef05653..f219ef04fce56 100644
--- a/mlir/test/lib/Transforms/TestVectorTransforms.cpp
+++ b/mlir/test/lib/Transforms/TestVectorTransforms.cpp
@@ -37,8 +37,11 @@ struct TestVectorToVectorConversion
 private:
   // Return the target shape based on op type.
   static Optional<SmallVector<int64_t, 4>> getShape(Operation *op) {
-    if (isa<AddFOp>(op))
+    if (isa<AddFOp, SelectOp, CmpFOp>(op))
       return SmallVector<int64_t, 4>(2, 2);
+    if (auto transferOp = dyn_cast<VectorTransferOpInterface>(op)) {
+      return SmallVector<int64_t, 4>(transferOp.getVectorType().getRank(), 2);
+    }
     if (isa<vector::ContractionOp>(op))
       return SmallVector<int64_t, 4>(3, 2);
     return llvm::None;
diff --git a/mlir/test/mlir-cpu-runner/async-value.mlir b/mlir/test/mlir-cpu-runner/async-value.mlir
new file mode 100644
index 0000000000000..31ed8860bf087
--- /dev/null
+++ b/mlir/test/mlir-cpu-runner/async-value.mlir
@@ -0,0 +1,81 @@
+// RUN:   mlir-opt %s -async-ref-counting                                      \
+// RUN:               -convert-async-to-llvm                                   \
+// RUN:               -convert-vector-to-llvm                                  \
+// RUN:               -convert-std-to-llvm                                     \
+// RUN: | mlir-cpu-runner                                                      \
+// RUN:     -e main -entry-point-result=void -O0                               \
+// RUN:     -shared-libs=%linalg_test_lib_dir/libmlir_c_runner_utils%shlibext  \
+// RUN:     -shared-libs=%linalg_test_lib_dir/libmlir_runner_utils%shlibext    \
+// RUN:     -shared-libs=%linalg_test_lib_dir/libmlir_async_runtime%shlibext   \
+// RUN: | FileCheck %s --dump-input=always
+
+func @main() {
+
+  // ------------------------------------------------------------------------ //
+  // Blocking async.await outside of the async.execute.
+  // ------------------------------------------------------------------------ //
+  %token, %result = async.execute -> !async.value<f32> {
+    %0 = constant 123.456 : f32
+    async.yield %0 : f32
+  }
+  %1 = async.await %result : !async.value<f32>
+
+  // CHECK: 123.456
+  vector.print %1 : f32
+
+  // ------------------------------------------------------------------------ //
+  // Non-blocking async.await inside the async.execute
+  // ------------------------------------------------------------------------ //
+  %token0, %result0 = async.execute -> !async.value<f32> {
+    %token1, %result2 = async.execute -> !async.value<f32> {
+      %2 = constant 456.789 : f32
+      async.yield %2 : f32
+    }
+    %3 = async.await %result2 : !async.value<f32>
+    async.yield %3 : f32
+  }
+  %4 = async.await %result0 : !async.value<f32>
+
+  // CHECK: 456.789
+  vector.print %4 : f32
+
+  // ------------------------------------------------------------------------ //
+  // Memref allocated inside async.execute region.
+  // ------------------------------------------------------------------------ //
+  %token2, %result2 = async.execute[%token0] -> !async.value<memref<f32>> {
+    %5 = alloc() : memref<f32>
+    %c0 = constant 0.25 : f32
+    store %c0, %5[]: memref<f32>
+    async.yield %5 : memref<f32>
+  }
+  %6 = async.await %result2 : !async.value<memref<f32>>
+  %7 = memref_cast %6 :  memref<f32> to memref<*xf32>
+
+  // CHECK: Unranked Memref
+  // CHECK-SAME: rank = 0 offset = 0 sizes = [] strides = []
+  // CHECK-NEXT: [0.25]
+  call @print_memref_f32(%7): (memref<*xf32>) -> ()
+
+  // ------------------------------------------------------------------------ //
+  // Memref passed as async.execute operand.
+  // ------------------------------------------------------------------------ //
+  %token3 = async.execute(%result2 as %unwrapped : !async.value<memref<f32>>) {
+    %8 = load %unwrapped[]: memref<f32>
+    %9 = addf %8, %8 : f32
+    store %9, %unwrapped[]: memref<f32>
+    async.yield
+  }
+  async.await %token3 : !async.token
+
+  // CHECK: Unranked Memref
+  // CHECK-SAME: rank = 0 offset = 0 sizes = [] strides = []
+  // CHECK-NEXT: [0.5]
+  call @print_memref_f32(%7): (memref<*xf32>) -> ()
+
+  dealloc %6 : memref<f32>
+
+  return
+}
+
+func private @print_memref_f32(memref<*xf32>)
+  attributes { llvm.emit_c_interface }
diff --git a/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc b/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
index 528fae883d19e..f81380f02bb38 100644
--- a/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
+++ b/mlir/test/mlir-linalg-ods-gen/test-linalg-ods-gen.tc
@@ -4,7 +4,6 @@
 // ODS-LABEL: def Test1Op : LinalgStructuredBase_Op<"test1", [
 //  ODS-NEXT:   AttrSizedOperandSegments
 //  ODS-NEXT:   DeclareOpInterfaceMethods<MemoryEffectsOpInterface>,
-//  ODS-NEXT:   NamedStructuredOpTrait
 //  ODS-NEXT:   SingleBlockImplicitTerminator<"YieldOp">
 //
 // IMPL-LABEL:  ArrayAttr Test1Op::iterator_types() {
@@ -29,7 +28,6 @@ def test1(A: f32(M, K), B: f32(K)) -> (C: f32(M)) {
 // ODS-LABEL: def Test2Op : LinalgStructuredBase_Op<"test2", [
 //  ODS-NEXT:   AttrSizedOperandSegments
 //  ODS-NEXT:   DeclareOpInterfaceMethods<MemoryEffectsOpInterface>,
-//  ODS-NEXT:   NamedStructuredOpTrait
 //  ODS-NEXT:   SingleBlockImplicitTerminator<"YieldOp">
 //
 // IMPL-LABEL:  ArrayAttr Test2Op::iterator_types() {
@@ -54,7 +52,6 @@ def test2(A: f32(M, K), B: f32(K, N)) -> (C: f32(M, N)) {
 // ODS-LABEL: def Test3Op : LinalgStructuredBase_Op<"test3", [
 //  ODS-NEXT:   AttrSizedOperandSegments
 //  ODS-NEXT:   DeclareOpInterfaceMethods<MemoryEffectsOpInterface>,
-//  ODS-NEXT:   NamedStructuredOpTrait
 //  ODS-NEXT:   SingleBlockImplicitTerminator<"YieldOp">
 //
 // IMPL-LABEL:  ArrayAttr Test3Op::iterator_types() {
diff --git a/mlir/test/mlir-tblgen/op-decl.td b/mlir/test/mlir-tblgen/op-decl.td
index 29438f1836a77..13daca67c4759 100644
--- a/mlir/test/mlir-tblgen/op-decl.td
+++ b/mlir/test/mlir-tblgen/op-decl.td
@@ -34,8 +34,7 @@ def NS_AOp : NS_Op<"a_op", [IsolatedFromAbove, IsolatedFromAbove]> {
     VariadicRegion<AnyRegion>:$someRegions
   );
   let builders = [OpBuilderDAG<(ins "Value":$val)>,
-                  OpBuilderDAG<(ins CArg<"int", "0">:$integer)>,
-                  OpBuilder<"double deprecatedForm">];
+                  OpBuilderDAG<(ins CArg<"int", "0">:$integer)>];
   let parser = [{ foo }];
   let printer = [{ bar }];
   let verifier = [{ baz }];
@@ -84,7 +83,6 @@ def NS_AOp : NS_Op<"a_op", [IsolatedFromAbove, IsolatedFromAbove]> {
 // CHECK:   ::llvm::Optional< ::llvm::APFloat > attr2();
 // CHECK:   static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, Value val);
 // CHECK:   static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, int integer = 0);
-// CHECK:   static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, double deprecatedForm);
 // CHECK:   static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Type r, ::mlir::TypeRange s, ::mlir::Value a, ::mlir::ValueRange b, ::mlir::IntegerAttr attr1, /*optional*/::mlir::FloatAttr attr2, unsigned someRegionsCount)
 // CHECK:   static void build(::mlir::OpBuilder &odsBuilder, ::mlir::OperationState &odsState, ::mlir::Type r, ::mlir::TypeRange s, ::mlir::Value a, ::mlir::ValueRange b, uint32_t attr1, /*optional*/::mlir::FloatAttr attr2, unsigned someRegionsCount)
 // CHECK:   static void build(::mlir::OpBuilder &, ::mlir::OperationState &odsState, ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes, unsigned numRegions)
diff --git a/mlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp b/mlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp
index a6729b1c0b7d1..72d172889d301 100644
--- a/mlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp
+++ b/mlir/tools/mlir-cuda-runner/cuda-runtime-wrappers.cpp
@@ -117,6 +117,13 @@ extern "C" void mgpuMemFree(void *ptr, CUstream /*stream*/) {
   CUDA_REPORT_IF_ERROR(cuMemFree(reinterpret_cast<CUdeviceptr>(ptr)));
 }
 
+extern "C" void mgpuMemcpy(void *dst, void *src, uint64_t sizeBytes,
+                           CUstream stream) {
+  CUDA_REPORT_IF_ERROR(cuMemcpyAsync(reinterpret_cast<CUdeviceptr>(dst),
+                                     reinterpret_cast<CUdeviceptr>(src),
+                                     sizeBytes, stream));
+}
+
 /// Helper functions for writing mlir example code
 
 // Allows to register byte array with the CUDA runtime. Helpful until we have
diff --git a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
index 45dc115e6c1e9..0342fab5ab9f0 100644
--- a/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
+++ b/mlir/tools/mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp
@@ -1453,54 +1453,45 @@ void TCParser::printODS(llvm::raw_ostream &os, StringRef cppOpName,
   const char *header = R"FMT(  def {0} : LinalgStructuredBase_Op<"{1}", [
     AttrSizedOperandSegments,
     DeclareOpInterfaceMethods<MemoryEffectsOpInterface>,
-    NamedStructuredOpTrait,
     SingleBlockImplicitTerminator<"YieldOp">]> {
       let arguments = (ins Variadic<AnyShaped>:$inputs,
-                           Variadic<AnyMemRef>:$output_buffers,
-                           Variadic<AnyRankedTensor>:$init_tensors);
+                           Variadic<AnyShaped>:$outputs);
       let results = (outs Variadic<AnyRankedTensor>:$result_tensors);
       let regions = (region AnyRegion:$region);
 
       let skipDefaultBuilders = 1;
       let builders = [ OpBuilderDAG<
-        (ins "ValueRange":$inputs, "ValueRange":$outputBuffers),
+        (ins "ValueRange":$inputs, "ValueRange":$outputs),
         [{{
           $_state.addOperands(inputs);
-          $_state.addOperands(outputBuffers);
+          $_state.addOperands(outputs);
           $_state.addAttribute(
             "operand_segment_sizes",
             $_builder.getI32VectorAttr({{
               static_cast<int32_t>(inputs.size()),
-              static_cast<int32_t>(outputBuffers.size()),
-              static_cast<int32_t>(0)}));
+              static_cast<int32_t>(outputs.size())}));
           buildNamedStructuredOpRegionAndAttributes<{0}>(
             $_builder,
             $_state,
             TypeRange(inputs),
-            TypeRange(outputBuffers),
-            TypeRange(),
-            TypeRange());
+            TypeRange(outputs));
         }]>, OpBuilderDAG<
         (ins "TypeRange":$resultTensorTypes, "ValueRange":$inputs,
-             "ValueRange":$outputBuffers, "ValueRange":$initTensors),
+             "ValueRange":$outputs),
         [{{
           $_state.addOperands(inputs);
-          $_state.addOperands(outputBuffers);
-          $_state.addOperands(initTensors);
+          $_state.addOperands(outputs);
           $_state.addTypes(resultTensorTypes);
           $_state.addAttribute(
             "operand_segment_sizes",
             $_builder.getI32VectorAttr({{
               static_cast<int32_t>(inputs.size()),
-              static_cast<int32_t>(outputBuffers.size()),
-              static_cast<int32_t>(initTensors.size())}));
+              static_cast<int32_t>(outputs.size())}));
           buildNamedStructuredOpRegionAndAttributes<{0}>(
             $_builder,
             $_state,
             TypeRange(inputs),
-            TypeRange(outputBuffers),
-            TypeRange(initTensors),
-            resultTensorTypes);
+            TypeRange(outputs));
         }]>, OpBuilderDAG<
         (ins "TypeRange":$resultTensorTypes, "ValueRange":$operands,
              CArg<"ArrayRef<NamedAttribute>", "{{}">:$attributes),
@@ -1513,7 +1504,6 @@ void TCParser::printODS(llvm::raw_ostream &os, StringRef cppOpName,
       ];
       let printer = [{{ return ::printNamedStructuredOp(p, *this); }];
       let parser = [{{ return ::parseNamedStructuredOp<{0}>(parser, result); }];
-      let verifier = [{{ return ::verifyNamedStructuredOp(*this); }];
       let hasFolder = 1;
       let hasCanonicalizer = 1;
 
diff --git a/mlir/tools/mlir-opt/mlir-opt.cpp b/mlir/tools/mlir-opt/mlir-opt.cpp
index 67aa855092efd..dc68f8f4d7789 100644
--- a/mlir/tools/mlir-opt/mlir-opt.cpp
+++ b/mlir/tools/mlir-opt/mlir-opt.cpp
@@ -47,6 +47,7 @@ void registerTestPrintDefUsePass();
 void registerTestPrintNestingPass();
 void registerTestReducer();
 void registerTestSpirvEntryPointABIPass();
+void registerTestSpirvGLSLCanonicalizationPass();
 void registerTestSpirvModuleCombinerPass();
 void registerTestTraitsPass();
 void registerTosaTestQuantUtilAPIPass();
@@ -115,6 +116,7 @@ void registerTestPasses() {
   registerTestPrintNestingPass();
   registerTestReducer();
   registerTestSpirvEntryPointABIPass();
+  registerTestSpirvGLSLCanonicalizationPass();
   registerTestSpirvModuleCombinerPass();
   registerTestTraitsPass();
   registerVectorizerTestPass();
diff --git a/mlir/tools/mlir-rocm-runner/rocm-runtime-wrappers.cpp b/mlir/tools/mlir-rocm-runner/rocm-runtime-wrappers.cpp
index aad7ae27ff892..4f62f204f4a83 100644
--- a/mlir/tools/mlir-rocm-runner/rocm-runtime-wrappers.cpp
+++ b/mlir/tools/mlir-rocm-runner/rocm-runtime-wrappers.cpp
@@ -118,6 +118,11 @@ extern "C" void mgpuMemFree(void *ptr, hipStream_t /*stream*/) {
   HIP_REPORT_IF_ERROR(hipMemFree(ptr));
 }
 
+extern "C" void mgpuMemcpy(void *dst, void *src, uint64_t sizeBytes,
+                           hipStream_t stream) {
+  HIP_REPORT_IF_ERROR(hipMemcpyAsync(dst, src, sizeBytes, stream));
+}
+
 /// Helper functions for writing mlir example code
 
 // Allows to register byte array with the ROCM runtime. Helpful until we have
diff --git a/mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp b/mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
index 31dbae3362181..1684361ffc3f8 100644
--- a/mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
+++ b/mlir/tools/mlir-spirv-cpu-runner/mlir-spirv-cpu-runner.cpp
@@ -12,8 +12,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h"
-#include "mlir/Conversion/SPIRVToLLVM/ConvertSPIRVToLLVMPass.h"
+#include "mlir/Conversion/GPUToSPIRV/GPUToSPIRVPass.h"
+#include "mlir/Conversion/SPIRVToLLVM/SPIRVToLLVMPass.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
 #include "mlir/Dialect/GPU/Passes.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
index 1c8cbfb9db383..995b4cd05cd57 100644
--- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
+++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp
@@ -1304,8 +1304,7 @@ void OpEmitter::genUseAttrAsResultTypeBuilder() {
 /// Updates the context `fctx` to enable replacement of $_builder and $_state
 /// in the body. Reports errors at `loc`.
 static std::string builderSignatureFromDAG(const DagInit *init,
-                                           ArrayRef<llvm::SMLoc> loc,
-                                           FmtContext &fctx) {
+                                           ArrayRef<llvm::SMLoc> loc) {
   auto *defInit = dyn_cast<DefInit>(init->getOperator());
   if (!defInit || !defInit->getDef()->getName().equals("ins"))
     PrintFatalError(loc, "expected 'ins' in builders");
@@ -1351,31 +1350,9 @@ static std::string builderSignatureFromDAG(const DagInit *init,
         llvm::formatv("{0} {1}{2}", type, name, defaultValue).str());
   }
 
-  fctx.withBuilder(builder);
-  fctx.addSubst("_state", builderOpState);
-
   return llvm::join(arguments, ", ");
 }
 
-// Returns a signature fo the builder as defined by a string initializer,
-// optionally injecting the builder and state arguments.
-// TODO: to be removed after the transition is complete.
-static std::string builderSignatureFromString(StringRef params,
-                                              FmtContext &fctx) {
-  bool skipParamGen = params.startswith("OpBuilder") ||
-                      params.startswith("mlir::OpBuilder") ||
-                      params.startswith("::mlir::OpBuilder");
-  if (skipParamGen)
-    return params.str();
-
-  fctx.withBuilder(builder);
-  fctx.addSubst("_state", builderOpState);
-  return std::string(llvm::formatv("::mlir::OpBuilder &{0}, "
-                                   "::mlir::OperationState &{1}{2}{3}",
-                                   builder, builderOpState,
-                                   params.empty() ? "" : ", ", params));
-}
-
 void OpEmitter::genBuilder() {
   // Handle custom builders if provided.
   // TODO: Create wrapper class for OpBuilder to hide the native
@@ -1385,19 +1362,8 @@ void OpEmitter::genBuilder() {
     if (listInit) {
       for (Init *init : listInit->getValues()) {
         Record *builderDef = cast<DefInit>(init)->getDef();
-        llvm::Optional<StringRef> params =
-            builderDef->getValueAsOptionalString("params");
-        FmtContext fctx;
-        if (params.hasValue()) {
-          PrintWarning(op.getLoc(),
-                       "Op uses a deprecated, string-based OpBuilder format; "
-                       "use OpBuilderDAG with '(ins <...>)' instead");
-        }
-        std::string paramStr =
-            params.hasValue() ? builderSignatureFromString(params->trim(), fctx)
-                              : builderSignatureFromDAG(
-                                    builderDef->getValueAsDag("dagParams"),
-                                    op.getLoc(), fctx);
+        std::string paramStr = builderSignatureFromDAG(
+            builderDef->getValueAsDag("dagParams"), op.getLoc());
 
         StringRef body = builderDef->getValueAsString("body");
         bool hasBody = !body.empty();
@@ -1405,6 +1371,10 @@ void OpEmitter::genBuilder() {
             hasBody ? OpMethod::MP_Static : OpMethod::MP_StaticDeclaration;
         auto *method =
             opClass.addMethodAndPrune("void", "build", properties, paramStr);
+
+        FmtContext fctx;
+        fctx.withBuilder(builder);
+        fctx.addSubst("_state", builderOpState);
         if (hasBody)
           method->body() << tgfmt(body, &fctx);
       }
@@ -2167,11 +2137,18 @@ void OpEmitter::genTraits() {
   unsigned numVariadicRegions = op.getNumVariadicRegions();
   addSizeCountTrait(opClass, "Region", numRegions, numVariadicRegions);
 
-  // Add result size trait.
+  // Add result size traits.
   int numResults = op.getNumResults();
   int numVariadicResults = op.getNumVariableLengthResults();
   addSizeCountTrait(opClass, "Result", numResults, numVariadicResults);
 
+  // For single result ops with a known specific type, generate a OneTypedResult
+  // trait.
+  if (numResults == 1 && numVariadicResults == 0) {
+    auto cppName = op.getResults().begin()->constraint.getCPPClassName();
+    opClass.addTrait("::mlir::OpTrait::OneTypedResult<" + cppName + ">::Impl");
+  }
+
   // Add successor size trait.
   unsigned numSuccessors = op.getNumSuccessors();
   unsigned numVariadicSuccessors = op.getNumVariadicSuccessors();
diff --git a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
index cd8be8a984f53..74fe1e0fdb08d 100644
--- a/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
+++ b/mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp
@@ -647,8 +647,7 @@ static void emitDecorationSerialization(const Operator &op, StringRef tabs,
     // All non-argument attributes translated into OpDecorate instruction
     os << tabs << formatv("for (auto attr : {0}->getAttrs()) {{\n", opVar);
     os << tabs
-       << formatv("  if (llvm::any_of({0}, [&](StringRef elided)", elidedAttrs);
-    os << " {return attr.first == elided;})) {\n";
+       << formatv("  if (llvm::is_contained({0}, attr.first)) {{", elidedAttrs);
     os << tabs << "    continue;\n";
     os << tabs << "  }\n";
     os << tabs
@@ -666,14 +665,35 @@ static void emitSerializationFunction(const Record *attrClass,
                                       const Record *record, const Operator &op,
                                       raw_ostream &os) {
   // If the record has 'autogenSerialization' set to 0, nothing to do
-  if (!record->getValueAsBit("autogenSerialization")) {
+  if (!record->getValueAsBit("autogenSerialization"))
     return;
-  }
+
   StringRef opVar("op"), operands("operands"), elidedAttrs("elidedAttrs"),
       resultID("resultID");
+
   os << formatv(
       "template <> LogicalResult\nSerializer::processOp<{0}>({0} {1}) {{\n",
       op.getQualCppClassName(), opVar);
+
+  // Special case for ops without attributes in TableGen definitions
+  if (op.getNumAttributes() == 0 && op.getNumVariableLengthOperands() == 0) {
+    std::string extInstSet;
+    std::string opcode;
+    if (record->isSubClassOf("SPV_ExtInstOp")) {
+      extInstSet =
+          formatv("\"{0}\"", record->getValueAsString("extendedInstSetName"));
+      opcode = std::to_string(record->getValueAsInt("extendedInstOpcode"));
+    } else {
+      extInstSet = "\"\"";
+      opcode = formatv("static_cast<uint32_t>(spirv::Opcode::{0})",
+                       record->getValueAsString("spirvOpName"));
+    }
+
+    os << formatv("  return processOpWithoutGrammarAttr({0}, {1}, {2});\n}\n\n",
+                  opVar, extInstSet, opcode);
+    return;
+  }
+
   os << formatv("  SmallVector<uint32_t, 4> {0};\n", operands);
   os << formatv("  SmallVector<StringRef, 2> {0};\n", elidedAttrs);
 
@@ -914,16 +934,28 @@ static void emitDeserializationFunction(const Record *attrClass,
                                         const Record *record,
                                         const Operator &op, raw_ostream &os) {
   // If the record has 'autogenSerialization' set to 0, nothing to do
-  if (!record->getValueAsBit("autogenSerialization")) {
+  if (!record->getValueAsBit("autogenSerialization"))
     return;
-  }
+
   StringRef resultTypes("resultTypes"), valueID("valueID"), words("words"),
       wordIndex("wordIndex"), opVar("op"), operands("operands"),
       attributes("attributes");
+
+  // Method declaration
   os << formatv("template <> "
                 "LogicalResult\nDeserializer::processOp<{0}>(ArrayRef<"
                 "uint32_t> {1}) {{\n",
                 op.getQualCppClassName(), words);
+
+  // Special case for ops without attributes in TableGen definitions
+  if (op.getNumAttributes() == 0 && op.getNumVariableLengthOperands() == 0) {
+    os << formatv("  return processOpWithoutGrammarAttr("
+                  "{0}, \"{1}\", {2}, {3});\n}\n\n",
+                  words, op.getOperationName(),
+                  op.getNumResults() ? "true" : "false", op.getNumOperands());
+    return;
+  }
+
   os << formatv("  SmallVector<Type, 1> {0};\n", resultTypes);
   os << formatv("  size_t {0} = 0; (void){0};\n", wordIndex);
   os << formatv("  uint32_t {0} = 0; (void){0};\n", valueID);
@@ -938,6 +970,9 @@ static void emitDeserializationFunction(const Record *attrClass,
   emitOperandDeserialization(op, record->getLoc(), "  ", words, wordIndex,
                              operands, attributes, os);
 
+  // Decorations
+  emitDecorationDeserialization(op, "  ", valueID, attributes, os);
+
   os << formatv("  Location loc = createFileLineColLoc(opBuilder);\n");
   os << formatv("  auto {1} = opBuilder.create<{0}>(loc, {2}, {3}, {4}); "
                 "(void){1};\n",
@@ -953,9 +988,6 @@ static void emitDeserializationFunction(const Record *attrClass,
   // next end of block.
   os << formatv("  if ({0}.hasTrait<OpTrait::IsTerminator>())\n", opVar);
   os << formatv("    clearDebugLine();\n");
-
-  // Decorations
-  emitDecorationDeserialization(op, "  ", valueID, attributes, os);
   os << "  return success();\n";
   os << "}\n\n";
 }
diff --git a/mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp b/mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
index 98d3bcff02cfa..936b1d314e841 100644
--- a/mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
+++ b/mlir/tools/mlir-vulkan-runner/mlir-vulkan-runner.cpp
@@ -12,10 +12,10 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "mlir/Conversion/GPUToSPIRV/ConvertGPUToSPIRVPass.h"
+#include "mlir/Conversion/GPUToSPIRV/GPUToSPIRVPass.h"
 #include "mlir/Conversion/GPUToVulkan/ConvertGPUToVulkanPass.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
-#include "mlir/Conversion/StandardToSPIRV/ConvertStandardToSPIRVPass.h"
+#include "mlir/Conversion/StandardToSPIRV/StandardToSPIRVPass.h"
 #include "mlir/Dialect/GPU/Passes.h"
 #include "mlir/Dialect/SPIRV/IR/SPIRVOps.h"
 #include "mlir/Dialect/SPIRV/Transforms/Passes.h"
diff --git a/openmp/docs/SupportAndFAQ.rst b/openmp/docs/SupportAndFAQ.rst
index 6b8f0d2f72b0d..ef209aed17a0e 100644
--- a/openmp/docs/SupportAndFAQ.rst
+++ b/openmp/docs/SupportAndFAQ.rst
@@ -52,22 +52,11 @@ All patches go through the regular `LLVM review process
 Q: How to build an OpenMP offload capable compiler?
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-To build an *effective* OpenMP offload capable compiler we recommend a two
-stage build. The first stage Clang does not require to be offload capable but
-all backends that are targeted by OpenMP need to be enabled. By default, Clang
-will be build with all backends enabled. This initial (stage 1) Clang is used
-to create a second Clang compiler that is offload capable as well as the
-:ref:`device runtime libraries <device_runtime>` that will be linked into the
-offloaded code to provide OpenMP runtime support on the device.
-
-Generic information about building LLVM is available `here
-<https://llvm.org/docs/GettingStarted.html>`__. The CMake options for the
-second stage Clang should include:
-
-- `LIBOMPTARGET_NVPTX_CUDA_COMPILER=$STAGE1/bin/clang` to use the stage one
-  compiler for the device runtime compilation.
-- `LIBOMPTARGET_NVPTX_ENABLE_BCLIB=ON` to enable efficient device runtimes in
-  bitcode format.
+To build an *effective* OpenMP offload capable compiler, only one extra CMake
+option, `LLVM_ENABLE_RUNTIMES="openmp"`, is needed when building LLVM (Generic
+information about building LLVM is available `here <https://llvm.org/docs/GettingStarted.html>`__.).
+Make sure all backends that are targeted by OpenMP to be enabled. By default,
+Clang will be build with all backends enabled.
 
 If your build machine is not the target machine or automatic detection of the
 available GPUs failed, you should also set:
@@ -91,3 +80,32 @@ For now, the answer is most likely *no*. Please see :ref:`build_offload_capable_
 Q: Does OpenMP offloading support work in packages distributed as part of my OS?
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 For now, the answer is most likely *no*. Please see :ref:`build_offload_capable_compiler`.
+
+
+.. _math_and_complex_in_target_regions:
+
+Q: Does Clang support `<math.h>` and `<complex.h>` operations in OpenMP target on GPUs?
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Yes, LLVM/Clang allows math functions and complex arithmetic inside of OpenMP target regions
+that are compiled for GPUs.
+
+Clang provides a set of wrapper headers that are found first when `math.h` and
+`complex.h`, for C, `cmath` and `complex`, for C++, or similar headers are
+included by the application. These wrappers will eventually include the system
+version of the corresponding header file after setting up a target device
+specific environment. The fact that the system header is included is important
+because they differ based on the architecture and operating system and may
+contain preprocessor, variable, and function definitions that need to be
+available in the target region regardless of the targeted device architecture.
+However, various functions may require specialized device versions, e.g.,
+`sin`, and others are only available on certain devices, e.g., `__umul64hi`. To
+provide "native" support for math and complex on the respective architecture,
+Clang will wrap the "native" math functions, e.g., as provided by the device
+vendor, in an OpenMP begin/end declare variant. These functions will then be
+picked up instead of the host versions while host only variables and function
+definitions are still available. Complex arithmetic and functions are support
+through a similar mechanism. It is worth noting that this support requires
+`extensions to the OpenMP begin/end declare variant context selector
+<https://clang.llvm.org/docs/AttributeReference.html#pragma-omp-declare-variant>`__
+that are exposed through LLVM/Clang to the user as well.
diff --git a/openmp/docs/design/Runtimes.rst b/openmp/docs/design/Runtimes.rst
index 61491060ea047..c9f3a55c00679 100644
--- a/openmp/docs/design/Runtimes.rst
+++ b/openmp/docs/design/Runtimes.rst
@@ -16,6 +16,88 @@ the LLVM/OpenMP host runtime, aka.  `libomp.so`, is available as a `pdf
 LLVM/OpenMP Target Host Runtime (``libomptarget``)
 --------------------------------------------------
 
+Environment Variables
+^^^^^^^^^^^^^^^^^^^^^
+
+``libomptarget`` uses environment variables to control different features of the
+library at runtime. This allows the user to obtain useful runtime information as
+well as enable or disable certain features. A full list of supported environment
+variables is defined below.
+
+    * ``LIBOMPTARGET_DEBUG=<Num>``
+    * ``LIBOMPTARGET_PROFILE=<Filename>``
+    * ``LIBOMPTARGET_MEMORY_MANAGER_THRESHOLD=<Num>``
+    * ``LIBOMPTARGET_INFO=<Num>``
+
+LIBOMPTARGET_DEBUG
+""""""""""""""""""
+
+``LIBOMPTARGET_DEBUG`` controls whether or not debugging information will be
+displayed. This feature is only availible if ``libomptarget`` was built with
+``-DOMPTARGET_DEBUG``. The debugging output provided is intended for use by
+``libomptarget`` developers. More user-friendly output is presented when using
+``LIBOMPTARGET_INFO``.
+
+LIBOMPTARGET_PROFILE
+""""""""""""""""""""
+``LIBOMPTARGET_PROFILE`` allows ``libomptarget`` to generate time profile output
+similar to Clang's ``-ftime-trace`` option. This generates a JSON file based on
+`Chrome Tracing`_ that can be viewed with ``chrome://tracing`` or the
+`Speedscope App`_. Building this feature depends on the `LLVM Support Library`_
+for time trace output. Using this library is enabled by default when building
+using the CMake option ``OPENMP_ENABLE_LIBOMPTARGET_PROFILING``. The output will
+be saved to the filename specified by the environment variable.
+
+.. _`Chrome Tracing`: https://www.chromium.org/developers/how-tos/trace-event-profiling-tool
+
+.. _`Speedscope App`: https://www.speedscope.app/
+
+.. _`LLVM Support Library`: https://llvm.org/docs/SupportLibrary.html
+
+LIBOMPTARGET_MEMORY_MANAGER_THRESHOLD
+"""""""""""""""""""""""""""""""""""""
+
+``LIBOMPTARGET_MEMORY_MANAGER_THRESHOLD`` sets the threshold size for which the
+``libomptarget`` memory manager will handle the allocation. Any allocations
+larger than this threshold will not use the memory manager and be freed after
+the device kernel exits. The default threshold value is ``8KB``. If
+``LIBOMPTARGET_MEMORY_MANAGER_THRESHOLD`` is set to ``0`` the memory manager
+will be completely disabled.
+
+LIBOMPTARGET_INFO
+"""""""""""""""""
+
+``LIBOMPTARGET_INFO`` allows the user to request different types of runtime
+information from ``libomptarget``. ``LIBOMPTARGET_INFO`` uses a 32-bit field to
+enable or disable different types of information. This includes information
+about data-mappings and kernel execution. It is recommended to build your
+application with debugging information enabled, this will enable filenames and
+variable declarations in the information messages. OpenMP Debugging information
+is enabled at any level of debugging so a full debug runtime is not required.
+For minimal debugging information compile with `-gline-tables-only`, or compile
+with `-g` for full debug information. A full list of flags supported by
+``LIBOMPTARGET_INFO`` is given below. 
+
+    * Print all data arguments upon entering an OpenMP device kernel: ``0x01``
+    * Indicate when a mapped address already exists in the device mapping table:
+      ``0x02``
+    * Dump the contents of the device pointer map at kernel exit: ``0x04``
+    * Print OpenMP kernel information from device plugins: ``0x10``
+
+Any combination of these flags can be used by setting the appropriate bits. For
+example, to enable printing all data active in an OpenMP target region along
+with ``CUDA`` information, run the following ``bash`` command.
+
+.. code-block:: console
+
+   $ env LIBOMPTARGET_INFO=$((1 << 0x1 | 1 << 0x10)) ./your-application
+
+Or, to enable every flag run with every bit set.
+
+.. code-block:: console
+
+   $ env LIBOMPTARGET_INFO=-1 ./your-application
+
 LLVM/OpenMP Target Host Runtime Plugins (``libomptarget.rtl.XXXX``)
 -------------------------------------------------------------------
 
diff --git a/sycl/CMakeLists.txt b/sycl/CMakeLists.txt
index 90e0aacba9e7b..bad80bc0ebf8a 100644
--- a/sycl/CMakeLists.txt
+++ b/sycl/CMakeLists.txt
@@ -13,7 +13,7 @@ list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake/modules")
 include(AddSYCLExecutable)
 
 set(SYCL_MAJOR_VERSION 5)
-set(SYCL_MINOR_VERSION 0)
+set(SYCL_MINOR_VERSION 1)
 set(SYCL_PATCH_VERSION 0)
 set(SYCL_DEV_ABI_VERSION 0)
 if (SYCL_ADD_DEV_VERSION_POSTFIX)
diff --git a/sycl/include/CL/sycl/INTEL/esimd/esimd.hpp b/sycl/include/CL/sycl/INTEL/esimd/esimd.hpp
index ab61d6208d86a..69715ee22b4df 100644
--- a/sycl/include/CL/sycl/INTEL/esimd/esimd.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/esimd.hpp
@@ -43,8 +43,18 @@ template <typename Ty, int N> class simd {
   /// @{
   /// Constructors.
   constexpr simd() = default;
-  constexpr simd(const simd &other) { set(other.data()); }
-  constexpr simd(simd &&other) { set(other.data()); }
+  template <typename SrcTy> constexpr simd(const simd<SrcTy, N> &other) {
+    if constexpr (std::is_same<SrcTy, Ty>::value)
+      set(other.data());
+    else
+      set(__builtin_convertvector(other.data(), vector_type_t<Ty, N>));
+  }
+  template <typename SrcTy> constexpr simd(simd<SrcTy, N> &&other) {
+    if constexpr (std::is_same<SrcTy, Ty>::value)
+      set(other.data());
+    else
+      set(__builtin_convertvector(other.data(), vector_type_t<Ty, N>));
+  }
   constexpr simd(const vector_type &Val) { set(Val); }
 
   // TODO @rolandschulz
@@ -87,6 +97,7 @@ template <typename Ty, int N> class simd {
   }
   /// @}
 
+  /// conversion operator
   operator const vector_type &() const & { return M_data; }
   operator vector_type &() & { return M_data; }
 
@@ -117,12 +128,6 @@ template <typename Ty, int N> class simd {
     set(Val2.data());
   }
 
-  /// {@
-  /// Assignment operators.
-  constexpr simd &operator=(const simd &) & = default;
-  constexpr simd &operator=(simd &&) & = default;
-  /// @}
-
   /// View this simd object in a different element type.
   template <typename EltTy> auto format() & {
     using TopRegionTy = compute_format_type_t<simd, EltTy>;
@@ -208,6 +213,7 @@ template <typename Ty, int N> class simd {
   DEF_BINOP(-, -=)
   DEF_BINOP(*, *=)
   DEF_BINOP(/, /=)
+  DEF_BINOP(%, %=)
 
 #undef DEF_BINOP
 
@@ -234,15 +240,15 @@ template <typename Ty, int N> class simd {
 
 #undef DEF_RELOP
 
-#define DEF_LOGIC_OP(LOGIC_OP, OPASSIGN)                                       \
-  ESIMD_INLINE friend simd operator LOGIC_OP(const simd &X, const simd &Y) {   \
+#define DEF_BITWISE_OP(BITWISE_OP, OPASSIGN)                                   \
+  ESIMD_INLINE friend simd operator BITWISE_OP(const simd &X, const simd &Y) { \
     static_assert(std::is_integral<Ty>(), "not integeral type");               \
-    auto V2 = X.data() LOGIC_OP Y.data();                                      \
+    auto V2 = X.data() BITWISE_OP Y.data();                                    \
     return simd(V2);                                                           \
   }                                                                            \
   ESIMD_INLINE friend simd &operator OPASSIGN(simd &LHS, const simd &RHS) {    \
     static_assert(std::is_integral<Ty>(), "not integeral type");               \
-    auto V2 = LHS.data() LOGIC_OP RHS.data();                                  \
+    auto V2 = LHS.data() BITWISE_OP RHS.data();                                \
     LHS.write(convert<vector_type>(V2));                                       \
     return LHS;                                                                \
   }                                                                            \
@@ -251,11 +257,13 @@ template <typename Ty, int N> class simd {
     return LHS;                                                                \
   }
 
-  DEF_LOGIC_OP(&, &=)
-  DEF_LOGIC_OP(|, |=)
-  DEF_LOGIC_OP(^, ^=)
+  DEF_BITWISE_OP(&, &=)
+  DEF_BITWISE_OP(|, |=)
+  DEF_BITWISE_OP(^, ^=)
+  DEF_BITWISE_OP(<<, <<=)
+  DEF_BITWISE_OP(>>, >>=)
 
-#undef DEF_LOGIC_OP
+#undef DEF_BITWISE_OP
 
   // Operator ++, --
   simd &operator++() {
@@ -277,6 +285,18 @@ template <typename Ty, int N> class simd {
     return Ret;
   }
 
+#define DEF_UNARY_OP(UNARY_OP)                                                 \
+  simd operator UNARY_OP() {                                                   \
+    auto V = UNARY_OP(data());                                                 \
+    return simd(V);                                                            \
+  }
+  DEF_UNARY_OP(!)
+  DEF_UNARY_OP(~)
+  DEF_UNARY_OP(+)
+  DEF_UNARY_OP(-)
+
+#undef DEF_UNARY_OP
+
   /// \name Replicate
   /// Replicate simd instance given a region.
   /// @{
diff --git a/sycl/include/CL/sycl/INTEL/esimd/esimd_view.hpp b/sycl/include/CL/sycl/INTEL/esimd/esimd_view.hpp
index 90e30450ca1d4..b0636d0e63273 100644
--- a/sycl/include/CL/sycl/INTEL/esimd/esimd_view.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/esimd_view.hpp
@@ -70,8 +70,13 @@ template <typename BaseTy, typename RegionTy> class simd_view {
       : M_base(Other.M_base), M_region(Other.M_region) {}
   /// @}
 
-  /// Conversion to simd value type.
-  operator value_type() const { return read(); }
+  /// Conversion to simd type.
+  template <typename ToTy> operator simd<ToTy, length>() const {
+    if constexpr (std::is_same<element_type, ToTy>::value)
+      return read();
+    else
+      return convert<ToTy, element_type, length>(read());
+  }
 
   /// @{
   /// Assignment operators.
@@ -217,6 +222,7 @@ template <typename BaseTy, typename RegionTy> class simd_view {
   DEF_BINOP(-, -=)
   DEF_BINOP(*, *=)
   DEF_BINOP(/, /=)
+  DEF_BINOP(%, %=)
 
 #undef DEF_BINOP
 
@@ -247,26 +253,26 @@ template <typename BaseTy, typename RegionTy> class simd_view {
 
 #undef DEF_RELOP
 
-#define DEF_LOGIC_OP(LOGIC_OP, OPASSIGN)                                       \
-  ESIMD_INLINE friend auto operator LOGIC_OP(const simd_view &X,               \
-                                             const value_type &Y) {            \
+#define DEF_BITWISE_OP(BITWISE_OP, OPASSIGN)                                   \
+  ESIMD_INLINE friend auto operator BITWISE_OP(const simd_view &X,             \
+                                               const value_type &Y) {          \
     static_assert(std::is_integral<element_type>(), "not integral type");      \
-    auto V2 = X.read().data() LOGIC_OP Y.data();                               \
+    auto V2 = X.read().data() BITWISE_OP Y.data();                             \
     return simd<element_type, length>(V2);                                     \
   }                                                                            \
-  ESIMD_INLINE friend auto operator LOGIC_OP(const value_type &X,              \
-                                             const simd_view &Y) {             \
+  ESIMD_INLINE friend auto operator BITWISE_OP(const value_type &X,            \
+                                               const simd_view &Y) {           \
     static_assert(std::is_integral<element_type>(), "not integral type");      \
-    auto V2 = X.data() LOGIC_OP Y.read().data();                               \
+    auto V2 = X.data() BITWISE_OP Y.read().data();                             \
     return simd<element_type, length>(V2);                                     \
   }                                                                            \
-  ESIMD_INLINE friend auto operator LOGIC_OP(const simd_view &X,               \
-                                             const simd_view &Y) {             \
-    return (X LOGIC_OP Y.read());                                              \
+  ESIMD_INLINE friend auto operator BITWISE_OP(const simd_view &X,             \
+                                               const simd_view &Y) {           \
+    return (X BITWISE_OP Y.read());                                            \
   }                                                                            \
   simd_view &operator OPASSIGN(const value_type &RHS) {                        \
     static_assert(std::is_integral<element_type>(), "not integeral type");     \
-    auto V2 = read().data() LOGIC_OP RHS.data();                               \
+    auto V2 = read().data() BITWISE_OP RHS.data();                             \
     auto V3 = convert<vector_type>(V2);                                        \
     write(V3);                                                                 \
     return *this;                                                              \
@@ -274,11 +280,25 @@ template <typename BaseTy, typename RegionTy> class simd_view {
   simd_view &operator OPASSIGN(const simd_view &RHS) {                         \
     return (*this OPASSIGN RHS.read());                                        \
   }
-  DEF_LOGIC_OP(&, &=)
-  DEF_LOGIC_OP(|, |=)
-  DEF_LOGIC_OP(^, ^=)
+  DEF_BITWISE_OP(&, &=)
+  DEF_BITWISE_OP(|, |=)
+  DEF_BITWISE_OP(^, ^=)
+  DEF_BITWISE_OP(>>, >>=)
+  DEF_BITWISE_OP(<<, <<=)
+
+#undef DEF_BITWISE_OP
+
+#define DEF_UNARY_OP(UNARY_OP)                                                 \
+  auto operator UNARY_OP() {                                                   \
+    auto V = UNARY_OP(read().data());                                          \
+    return simd<element_type, length>(V);                                      \
+  }
+  DEF_UNARY_OP(!)
+  DEF_UNARY_OP(~)
+  DEF_UNARY_OP(+)
+  DEF_UNARY_OP(-)
 
-#undef DEF_LOGIC_OP
+#undef DEF_UNARY_OP
 
   // Operator ++, --
   simd_view &operator++() {
diff --git a/sycl/include/CL/sycl/ONEAPI/sub_group.hpp b/sycl/include/CL/sycl/ONEAPI/sub_group.hpp
index 981ec3acf779a..71ec92f176b47 100644
--- a/sycl/include/CL/sycl/ONEAPI/sub_group.hpp
+++ b/sycl/include/CL/sycl/ONEAPI/sub_group.hpp
@@ -230,7 +230,11 @@ struct sub_group {
       sycl::detail::sub_group::AcceptableForGlobalLoadStore<T, Space>::value, T>
   load(const multi_ptr<T, Space> src) const {
 #ifdef __SYCL_DEVICE_ONLY__
+#ifdef __NVPTX__
+    return src.get()[get_local_id()[0]];
+#else
     return sycl::detail::sub_group::load(src);
+#endif // __NVPTX__
 #else
     (void)src;
     throw runtime_error("Sub-groups are not supported on host device.",
@@ -258,7 +262,15 @@ struct sub_group {
       vec<T, N>>
   load(const multi_ptr<T, Space> src) const {
 #ifdef __SYCL_DEVICE_ONLY__
+#ifdef __NVPTX__
+    vec<T, N> res;
+    for (int i = 0; i < N; ++i) {
+      res[i] = *(src.get() + i * get_max_local_range()[0] + get_local_id()[0]);
+    }
+    return res;
+#else
     return sycl::detail::sub_group::load<N, T>(src);
+#endif // __NVPTX__
 #else
     (void)src;
     throw runtime_error("Sub-groups are not supported on host device.",
@@ -291,7 +303,11 @@ struct sub_group {
       vec<T, 1>>
   load(const multi_ptr<T, Space> src) const {
 #ifdef __SYCL_DEVICE_ONLY__
+#ifdef __NVPTX__
+    return src.get()[get_local_id()[0]];
+#else
     return sycl::detail::sub_group::load(src);
+#endif // __NVPTX__
 #else
     (void)src;
     throw runtime_error("Sub-groups are not supported on host device.",
@@ -304,7 +320,11 @@ struct sub_group {
       sycl::detail::sub_group::AcceptableForGlobalLoadStore<T, Space>::value>
   store(multi_ptr<T, Space> dst, const T &x) const {
 #ifdef __SYCL_DEVICE_ONLY__
+#ifdef __NVPTX__
+    dst.get()[get_local_id()[0]] = x;
+#else
     sycl::detail::sub_group::store(dst, x);
+#endif // __NVPTX__
 #else
     (void)dst;
     (void)x;
@@ -333,7 +353,11 @@ struct sub_group {
       N == 1>
   store(multi_ptr<T, Space> dst, const vec<T, 1> &x) const {
 #ifdef __SYCL_DEVICE_ONLY__
+#ifdef __NVPTX__
+    dst.get()[get_local_id()[0]] = x[0];
+#else
     store<T, Space>(dst, x);
+#endif // __NVPTX__
 #else
     (void)dst;
     (void)x;
@@ -348,7 +372,13 @@ struct sub_group {
       N != 1>
   store(multi_ptr<T, Space> dst, const vec<T, N> &x) const {
 #ifdef __SYCL_DEVICE_ONLY__
+#ifdef __NVPTX__
+    for (int i = 0; i < N; ++i) {
+      *(dst.get() + i * get_max_local_range()[0] + get_local_id()[0]) = x[i];
+    }
+#else
     sycl::detail::sub_group::store(dst, x);
+#endif // __NVPTX__
 #else
     (void)dst;
     (void)x;
diff --git a/sycl/include/CL/sycl/types.hpp b/sycl/include/CL/sycl/types.hpp
index 2181a1defb72c..a5b07eb291537 100644
--- a/sycl/include/CL/sycl/types.hpp
+++ b/sycl/include/CL/sycl/types.hpp
@@ -1817,11 +1817,16 @@ class SwizzleOp {
     return Tmp.template convert<convertT, roundingMode>();
   }
 
-  template <typename asT>
-  typename detail::enable_if_t<asT::getNumElements() == getNumElements(), asT>
-  as() const {
+  template <typename asT> asT as() const {
     // First materialize the swizzle to vec_t and then apply as() to it.
     vec_t Tmp = *this;
+    static_assert((sizeof(Tmp) == sizeof(asT)),
+                  "The new SYCL vec type must have the same storage size in "
+                  "bytes as this SYCL swizzled vec");
+    static_assert(
+        detail::is_contained<asT, detail::gtl::vector_basic_list>::value,
+        "asT must be SYCL vec of a different element type and "
+        "number of elements specified by asT");
     return Tmp.template as<asT>();
   }
 
diff --git a/sycl/plugins/CMakeLists.txt b/sycl/plugins/CMakeLists.txt
index 700e09d1a0c1d..9d75457ef22b9 100644
--- a/sycl/plugins/CMakeLists.txt
+++ b/sycl/plugins/CMakeLists.txt
@@ -1,5 +1,9 @@
 set(CMAKE_WINDOWS_EXPORT_ALL_SYMBOLS ON)
 
+if(NOT MSVC)
+    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Wno-covered-switch-default")
+endif()
+
 if(SYCL_BUILD_PI_CUDA)
  add_subdirectory(cuda)
 endif()
diff --git a/sycl/plugins/level_zero/pi_level_zero.cpp b/sycl/plugins/level_zero/pi_level_zero.cpp
index e87dba352d6b5..604cc595b0dff 100644
--- a/sycl/plugins/level_zero/pi_level_zero.cpp
+++ b/sycl/plugins/level_zero/pi_level_zero.cpp
@@ -117,6 +117,7 @@ pi_result getInfo(size_t param_value_size, void *param_value,
                   size_t *param_value_size_ret, T value) {
 
   auto assignment = [](void *param_value, T value, size_t value_size) {
+    (void)value_size;
     *static_cast<T *>(param_value) = value;
   };
 
@@ -406,6 +407,20 @@ ze_result_t ZeCall::doCall(ze_result_t ZeResult, const char *CallStr,
     return mapError(Result);
 #define ZE_CALL_NOCHECK(Call) ZeCall().doCall(Call, #Call, false)
 
+// Destroy all the command lists associated with this device.
+// This is required when destructing the _pi_device object.
+// During the piTearDown process, platforms and root devices are
+// destroyed automatically regardless of their reference counts.
+// So, this destructor should explicitly call zeCommandListDestroy
+// to avoid memory leaks.
+_pi_device::~_pi_device() {
+  std::lock_guard<std::mutex> Lock(ZeCommandListCacheMutex);
+  for (ze_command_list_handle_t &ZeCommandList : ZeCommandListCache) {
+    if (ZeCommandList)
+      zeCommandListDestroy(ZeCommandList);
+  }
+}
+
 // This helper function increments the reference counter of the Queue
 // without guarding with a lock.
 // It is the caller's responsibility to make sure the lock is acquired
@@ -493,7 +508,7 @@ pi_result _pi_context::finalize() {
   // There could be some memory that may have not been deallocated.
   // For example, zeEventPool could be still alive.
   std::lock_guard<std::mutex> NumEventsLiveInEventPoolGuard(
-      NumEventsLiveInEventPoolMutex, std::adopt_lock);
+      NumEventsLiveInEventPoolMutex);
   if (ZeEventPool && NumEventsLiveInEventPool[ZeEventPool])
     zeEventPoolDestroy(ZeEventPool);
 
@@ -740,22 +755,105 @@ pi_result _pi_queue::executeOpenCommandList() {
   return PI_SUCCESS;
 }
 
-ze_event_handle_t *_pi_event::createZeEventList(pi_uint32 EventListLength,
-                                                const pi_event *EventList) {
-  try {
-    ze_event_handle_t *ZeEventList = new ze_event_handle_t[EventListLength];
+static const bool FilterEventWaitList = [] {
+  const bool RetVal = std::getenv("SYCL_PI_LEVEL_ZERO_FILTER_EVENT_WAIT_LIST");
+  return RetVal;
+}();
 
-    for (pi_uint32 I = 0; I < EventListLength; I++) {
-      ZeEventList[I] = EventList[I]->ZeEvent;
+pi_result
+_pi_ze_event_list_t::createAndRetainPiZeEventList(pi_uint32 EventListLength,
+                                                  const pi_event *EventList) {
+  this->Length = 0;
+  this->ZeEventList = nullptr;
+  this->PiEventList = nullptr;
+
+  if (EventListLength > 0) {
+    try {
+      this->ZeEventList = new ze_event_handle_t[EventListLength];
+      this->PiEventList = new pi_event[EventListLength];
+      pi_uint32 TmpListLength = 0;
+
+      for (pi_uint32 I = 0; I < EventListLength; I++) {
+        auto ZeEvent = EventList[I]->ZeEvent;
+
+        this->ZeEventList[TmpListLength] = ZeEvent;
+        this->PiEventList[TmpListLength] = EventList[I];
+        TmpListLength += 1;
+
+        if (FilterEventWaitList) {
+          auto Res = ZE_CALL_NOCHECK(zeEventQueryStatus(ZeEvent));
+          if (Res == ZE_RESULT_SUCCESS) {
+            // Event has already completed, filter it from the list
+            // by decrementing TmpListLength, and resetting the
+            // event that was stored into the list to nullptr.
+            TmpListLength -= 1;
+            this->ZeEventList[TmpListLength] = nullptr;
+            this->PiEventList[TmpListLength] = nullptr;
+          }
+        }
+      }
+
+      this->Length = TmpListLength;
+    } catch (...) {
+      return PI_OUT_OF_HOST_MEMORY;
     }
-    return ZeEventList;
-  } catch (...) {
-    return nullptr;
+
+    for (pi_uint32 I = 0; I < this->Length; I++) {
+      piEventRetain(this->PiEventList[I]);
+    }
+  }
+
+  return PI_SUCCESS;
+}
+
+static void printZeEventList(_pi_ze_event_list_t &PiZeEventList) {
+  zePrint("  NumEventsInWaitList %d:", PiZeEventList.Length);
+
+  for (pi_uint32 I = 0; I < PiZeEventList.Length; I++) {
+    zePrint(" %#lx", pi_cast<std::uintptr_t>(PiZeEventList.ZeEventList[I]));
   }
+
+  zePrint("\n");
 }
 
-void _pi_event::deleteZeEventList(ze_event_handle_t *ZeEventList) {
-  delete[] ZeEventList;
+pi_result _pi_ze_event_list_t::releaseAndDestroyPiZeEventList() {
+  // acquire a lock before reading the length and list fields.
+  // Acquire the lock, copy the needed data locally, and reset
+  // the fields, then release the lock.
+  // Only then do we do the actual actions to release and destroy,
+  // holding the lock for the minimum time necessary.
+  pi_uint32 LocLength = 0;
+  ze_event_handle_t *LocZeEventList = nullptr;
+  pi_event *LocPiEventList = nullptr;
+
+  {
+    // acquire the lock and copy fields locally
+    // Lock automatically releases when this goes out of scope.
+    std::lock_guard<std::mutex> lock(this->PiZeEventListMutex);
+
+    LocLength = Length;
+    LocZeEventList = ZeEventList;
+    LocPiEventList = PiEventList;
+
+    Length = 0;
+    ZeEventList = nullptr;
+    PiEventList = nullptr;
+
+    // release lock by ending scope.
+  }
+
+  for (pi_uint32 I = 0; I < LocLength; I++) {
+    piEventRelease(LocPiEventList[I]);
+  }
+
+  if (LocZeEventList != nullptr) {
+    delete[] LocZeEventList;
+  }
+  if (LocPiEventList != nullptr) {
+    delete[] LocPiEventList;
+  }
+
+  return PI_SUCCESS;
 }
 
 extern "C" {
@@ -992,8 +1090,8 @@ pi_result piPlatformGetInfo(pi_platform Platform, pi_platform_info ParamName,
     //
     return ReturnValue(Platform->ZeDriverApiVersion.c_str());
   default:
-    // TODO: implement other parameters
-    die("Unsupported ParamName in piPlatformGetInfo");
+    zePrint("piPlatformGetInfo: unrecognized ParamName\n");
+    return PI_INVALID_VALUE;
   }
 
   return PI_SUCCESS;
@@ -1162,17 +1260,9 @@ pi_result piDeviceRelease(pi_device Device) {
   if (Device->RefCount <= 0)
     die("piDeviceRelease: the device has been already released");
 
-  // TODO: OpenCL says root-device ref-count remains unchanged (1),
-  // but when would we free the device's data?
+  // Root devices are destroyed during the piTearDown process.
   if (Device->IsSubDevice) {
     if (--(Device->RefCount) == 0) {
-      // Destroy all the command lists associated with this device.
-      Device->ZeCommandListCacheMutex.lock();
-      for (ze_command_list_handle_t &ZeCommandList :
-           Device->ZeCommandListCache) {
-        zeCommandListDestroy(ZeCommandList);
-      }
-      Device->ZeCommandListCacheMutex.unlock();
       delete Device;
     }
   }
@@ -1823,6 +1913,9 @@ pi_result piContextCreate(const pi_context_properties *Properties,
                                             const void *PrivateInfo, size_t CB,
                                             void *UserData),
                           void *UserData, pi_context *RetContext) {
+  (void)Properties;
+  (void)PFnNotify;
+  (void)UserData;
   PI_ASSERT(Devices, PI_INVALID_DEVICE);
   PI_ASSERT(RetContext, PI_INVALID_VALUE);
 
@@ -1869,6 +1962,9 @@ pi_result piContextGetInfo(pi_context Context, pi_context_info ParamName,
 pi_result piextContextSetExtendedDeleter(pi_context Context,
                                          pi_context_extended_deleter Function,
                                          void *UserData) {
+  (void)Context;
+  (void)Function;
+  (void)UserData;
   die("piextContextSetExtendedDeleter: not supported");
   return PI_SUCCESS;
 }
@@ -2205,6 +2301,11 @@ pi_result piMemGetInfo(pi_mem Mem,
                        cl_mem_info ParamName, // TODO: untie from OpenCL
                        size_t ParamValueSize, void *ParamValue,
                        size_t *ParamValueSizeRet) {
+  (void)Mem;
+  (void)ParamName;
+  (void)ParamValueSize;
+  (void)ParamValue;
+  (void)ParamValueSizeRet;
   die("piMemGetInfo: not implemented");
   return {};
 }
@@ -2407,12 +2508,16 @@ pi_result piMemImageCreate(pi_context Context, pi_mem_flags Flags,
 }
 
 pi_result piextMemGetNativeHandle(pi_mem Mem, pi_native_handle *NativeHandle) {
+  (void)Mem;
+  (void)NativeHandle;
   die("piextMemGetNativeHandle: not supported");
   return PI_SUCCESS;
 }
 
 pi_result piextMemCreateWithNativeHandle(pi_native_handle NativeHandle,
                                          pi_mem *Mem) {
+  (void)NativeHandle;
+  (void)Mem;
   die("piextMemCreateWithNativeHandle: not supported");
   return PI_SUCCESS;
 }
@@ -2493,6 +2598,11 @@ pi_result piclProgramCreateWithSource(pi_context Context, pi_uint32 Count,
                                       const size_t *Lengths,
                                       pi_program *RetProgram) {
 
+  (void)Context;
+  (void)Count;
+  (void)Strings;
+  (void)Lengths;
+  (void)RetProgram;
   zePrint("piclProgramCreateWithSource: not supported in Level Zero\n");
   return PI_INVALID_OPERATION;
 }
@@ -2642,6 +2752,7 @@ pi_result piProgramLink(pi_context Context, pi_uint32 NumDevices,
                         const pi_program *InputPrograms,
                         void (*PFnNotify)(pi_program Program, void *UserData),
                         void *UserData, pi_program *RetProgram) {
+  (void)Options;
 
   // We only support one device with Level Zero currently.
   pi_device Device = Context->Devices[0];
@@ -2756,6 +2867,9 @@ pi_result piProgramCompile(
     const char *Options, pi_uint32 NumInputHeaders,
     const pi_program *InputHeaders, const char **HeaderIncludeNames,
     void (*PFnNotify)(pi_program Program, void *UserData), void *UserData) {
+  (void)NumInputHeaders;
+  (void)InputHeaders;
+  (void)HeaderIncludeNames;
 
   // The OpenCL spec says this should return CL_INVALID_PROGRAM, but there is
   // no corresponding PI error code.
@@ -2881,6 +2995,7 @@ pi_result piProgramGetBuildInfo(pi_program Program, pi_device Device,
                                 cl_program_build_info ParamName,
                                 size_t ParamValueSize, void *ParamValue,
                                 size_t *ParamValueSizeRet) {
+  (void)Device;
 
   ReturnHelper ReturnValue(ParamValueSize, ParamValue, ParamValueSizeRet);
   if (ParamName == CL_PROGRAM_BINARY_TYPE) {
@@ -3313,6 +3428,9 @@ pi_result piKernelGetSubGroupInfo(pi_kernel Kernel, pi_device Device,
                                   size_t InputValueSize, const void *InputValue,
                                   size_t ParamValueSize, void *ParamValue,
                                   size_t *ParamValueSizeRet) {
+  (void)Device;
+  (void)InputValueSize;
+  (void)InputValue;
 
   ze_kernel_properties_t ZeKernelProperties;
   ZE_CALL(zeKernelGetProperties(Kernel->ZeKernel, &ZeKernelProperties));
@@ -3472,32 +3590,25 @@ piEnqueueKernelLaunch(pi_queue Queue, pi_kernel Kernel, pi_uint32 WorkDim,
   // in CommandData.
   piKernelRetain(Kernel);
 
-  ze_event_handle_t *ZeEventWaitList =
-      _pi_event::createZeEventList(NumEventsInWaitList, EventWaitList);
-  if (!ZeEventWaitList)
-    return PI_OUT_OF_HOST_MEMORY;
+  if (auto Res = (*Event)->WaitList.createAndRetainPiZeEventList(
+          NumEventsInWaitList, EventWaitList))
+    return Res;
 
   // Add the command to the command list
   ZE_CALL(zeCommandListAppendLaunchKernel(
       ZeCommandList, Kernel->ZeKernel, &ZeThreadGroupDimensions, ZeEvent,
-      NumEventsInWaitList, ZeEventWaitList));
+      (*Event)->WaitList.Length, (*Event)->WaitList.ZeEventList));
 
   zePrint("calling zeCommandListAppendLaunchKernel() with"
-          "  ZeEvent %lx\n"
-          "  NumEventsInWaitList %d:",
-          pi_cast<std::uintptr_t>(ZeEvent), NumEventsInWaitList);
-  for (pi_uint32 I = 0; I < NumEventsInWaitList; I++) {
-    zePrint(" %lx", pi_cast<std::uintptr_t>(ZeEventWaitList[I]));
-  }
-  zePrint("\n");
+          "  ZeEvent %#lx\n",
+          pi_cast<std::uintptr_t>(ZeEvent));
+  printZeEventList((*Event)->WaitList);
 
   // Execute command list asynchronously, as the event will be used
   // to track down its completion.
   if (auto Res = Queue->executeCommandList(ZeCommandList, ZeFence, false, true))
     return Res;
 
-  _pi_event::deleteZeEventList(ZeEventWaitList);
-
   return PI_SUCCESS;
 }
 
@@ -3638,35 +3749,43 @@ static void cleanupAfterEvent(pi_event Event) {
   // queue to also serve as the thread safety mechanism for the
   // any of the Event's data members that need to be read/reset as
   // part of the cleanup operations.
-  auto Queue = Event->Queue;
-
-  // Lock automatically releases when this goes out of scope.
-  std::lock_guard<std::mutex> lock(Queue->PiQueueMutex);
+  {
+    auto Queue = Event->Queue;
 
-  // Cleanup the command list associated with the event if it hasn't
-  // been cleaned up already.
-  auto EventCommandList = Event->ZeCommandList;
+    // Lock automatically releases when this goes out of scope.
+    std::lock_guard<std::mutex> lock(Queue->PiQueueMutex);
 
-  if (EventCommandList) {
-    // Event has been signalled: If the fence for the associated command list
-    // is signalled, then reset the fence and command list and add them to the
-    // available list for reuse in PI calls.
-    if (Queue->RefCount > 0) {
-      ze_result_t ZeResult = ZE_CALL_NOCHECK(
-          zeFenceQueryStatus(Queue->ZeCommandListFenceMap[EventCommandList]));
-      if (ZeResult == ZE_RESULT_SUCCESS) {
-        Queue->resetCommandListFenceEntry(EventCommandList, true);
-        Event->ZeCommandList = nullptr;
+    // Cleanup the command list associated with the event if it hasn't
+    // been cleaned up already.
+    auto EventCommandList = Event->ZeCommandList;
+
+    if (EventCommandList) {
+      // Event has been signalled: If the fence for the associated command list
+      // is signalled, then reset the fence and command list and add them to the
+      // available list for reuse in PI calls.
+      if (Queue->RefCount > 0) {
+        ze_result_t ZeResult = ZE_CALL_NOCHECK(
+            zeFenceQueryStatus(Queue->ZeCommandListFenceMap[EventCommandList]));
+        if (ZeResult == ZE_RESULT_SUCCESS) {
+          Queue->resetCommandListFenceEntry(EventCommandList, true);
+          Event->ZeCommandList = nullptr;
+        }
       }
     }
-  }
 
-  // Release the kernel associated with this event if there is one.
-  if (Event->CommandType == PI_COMMAND_TYPE_NDRANGE_KERNEL &&
-      Event->CommandData) {
-    piKernelRelease(pi_cast<pi_kernel>(Event->CommandData));
-    Event->CommandData = nullptr;
+    // Release the kernel associated with this event if there is one.
+    if (Event->CommandType == PI_COMMAND_TYPE_NDRANGE_KERNEL &&
+        Event->CommandData) {
+      piKernelRelease(pi_cast<pi_kernel>(Event->CommandData));
+      Event->CommandData = nullptr;
+    }
   }
+
+  // Had to make sure lock of Event's Queue has been released before
+  // the code starts to release the event wait list, as that could
+  // potentially cause recursive calls to cleanupAfterEvent, and
+  // run into a problem trying to do multiple locks on the same Queue.
+  Event->WaitList.releaseAndDestroyPiZeEventList();
 }
 
 pi_result piEventsWait(pi_uint32 NumEvents, const pi_event *EventList) {
@@ -3690,7 +3809,7 @@ pi_result piEventsWait(pi_uint32 NumEvents, const pi_event *EventList) {
 
   for (uint32_t I = 0; I < NumEvents; I++) {
     ze_event_handle_t ZeEvent = EventList[I]->ZeEvent;
-    zePrint("ZeEvent = %lx\n", pi_cast<std::uintptr_t>(ZeEvent));
+    zePrint("ZeEvent = %#lx\n", pi_cast<std::uintptr_t>(ZeEvent));
     ZE_CALL(zeEventHostSynchronize(ZeEvent, UINT32_MAX));
 
     // NOTE: we are cleaning up after the event here to free resources
@@ -3705,11 +3824,17 @@ pi_result piEventSetCallback(pi_event Event, pi_int32 CommandExecCallbackType,
                                                pi_int32 EventCommandStatus,
                                                void *UserData),
                              void *UserData) {
+  (void)Event;
+  (void)CommandExecCallbackType;
+  (void)PFnNotify;
+  (void)UserData;
   die("piEventSetCallback: deprecated, to be removed");
   return PI_SUCCESS;
 }
 
 pi_result piEventSetStatus(pi_event Event, pi_int32 ExecutionStatus) {
+  (void)Event;
+  (void)ExecutionStatus;
   die("piEventSetStatus: deprecated, to be removed");
   return PI_SUCCESS;
 }
@@ -3748,12 +3873,16 @@ pi_result piEventRelease(pi_event Event) {
 
 pi_result piextEventGetNativeHandle(pi_event Event,
                                     pi_native_handle *NativeHandle) {
+  (void)Event;
+  (void)NativeHandle;
   die("piextEventGetNativeHandle: not supported");
   return PI_SUCCESS;
 }
 
 pi_result piextEventCreateWithNativeHandle(pi_native_handle NativeHandle,
                                            pi_event *Event) {
+  (void)NativeHandle;
+  (void)Event;
   die("piextEventCreateWithNativeHandle: not supported");
   return PI_SUCCESS;
 }
@@ -3880,6 +4009,11 @@ pi_result piSamplerCreate(pi_context Context,
 pi_result piSamplerGetInfo(pi_sampler Sampler, pi_sampler_info ParamName,
                            size_t ParamValueSize, void *ParamValue,
                            size_t *ParamValueSizeRet) {
+  (void)Sampler;
+  (void)ParamName;
+  (void)ParamValueSize;
+  (void)ParamValue;
+  (void)ParamValueSizeRet;
 
   die("piSamplerGetInfo: not implemented");
   return {};
@@ -3907,6 +4041,10 @@ pi_result piSamplerRelease(pi_sampler Sampler) {
 //
 pi_result piEnqueueEventsWait(pi_queue Queue, pi_uint32 NumEventsInWaitList,
                               const pi_event *EventWaitList, pi_event *Event) {
+  (void)Queue;
+  (void)NumEventsInWaitList;
+  (void)EventWaitList;
+  (void)Event;
 
   die("piEnqueueEventsWait: not implemented");
   return {};
@@ -3917,6 +4055,7 @@ pi_result piEnqueueEventsWaitWithBarrier(pi_queue Queue,
                                          const pi_event *EventWaitList,
                                          pi_event *Event) {
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
+  PI_ASSERT(Event, PI_INVALID_EVENT);
 
   // Lock automatically releases when this goes out of scope.
   std::lock_guard<std::mutex> lock(Queue->PiQueueMutex);
@@ -3929,25 +4068,19 @@ pi_result piEnqueueEventsWaitWithBarrier(pi_queue Queue,
     return Res;
 
   ze_event_handle_t ZeEvent = nullptr;
-  if (Event) {
-    auto Res = createEventAndAssociateQueue(Queue, Event, PI_COMMAND_TYPE_USER,
-                                            ZeCommandList);
-    if (Res != PI_SUCCESS)
-      return Res;
-    ZeEvent = (*Event)->ZeEvent;
-  }
+  auto Res = createEventAndAssociateQueue(Queue, Event, PI_COMMAND_TYPE_USER,
+                                          ZeCommandList);
+  if (Res != PI_SUCCESS)
+    return Res;
+  ZeEvent = (*Event)->ZeEvent;
 
-  // TODO: use unique_ptr with custom deleter in the whole Level Zero plugin for
-  // wrapping ze_event_handle_t *ZeEventWaitList to avoid memory leaks in case
-  // return will be called in ZE_CALL(ze***(...)), and thus
-  // _pi_event::deleteZeEventList(ZeEventWaitList) won't be called.
-  ze_event_handle_t *ZeEventWaitList =
-      _pi_event::createZeEventList(NumEventsInWaitList, EventWaitList);
+  if (auto Res = (*Event)->WaitList.createAndRetainPiZeEventList(
+          NumEventsInWaitList, EventWaitList))
+    return Res;
 
   ZE_CALL(zeCommandListAppendBarrier(ZeCommandList, ZeEvent,
-                                     NumEventsInWaitList, ZeEventWaitList));
-
-  _pi_event::deleteZeEventList(ZeEventWaitList);
+                                     (*Event)->WaitList.Length,
+                                     (*Event)->WaitList.ZeEventList));
 
   return PI_SUCCESS;
 }
@@ -4001,6 +4134,8 @@ enqueueMemCopyHelper(pi_command_type CommandType, pi_queue Queue, void *Dst,
                      pi_uint32 NumEventsInWaitList,
                      const pi_event *EventWaitList, pi_event *Event) {
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
+  PI_ASSERT(Event, PI_INVALID_EVENT);
+
   // Get a new command list to be used on this call
   ze_command_list_handle_t ZeCommandList = nullptr;
   ze_fence_handle_t ZeFence = nullptr;
@@ -4009,21 +4144,19 @@ enqueueMemCopyHelper(pi_command_type CommandType, pi_queue Queue, void *Dst,
     return Res;
 
   ze_event_handle_t ZeEvent = nullptr;
-  if (Event) {
-    auto Res =
-        createEventAndAssociateQueue(Queue, Event, CommandType, ZeCommandList);
-    if (Res != PI_SUCCESS)
-      return Res;
-    ZeEvent = (*Event)->ZeEvent;
-  }
+  auto Res =
+      createEventAndAssociateQueue(Queue, Event, CommandType, ZeCommandList);
+  if (Res != PI_SUCCESS)
+    return Res;
+  ZeEvent = (*Event)->ZeEvent;
 
-  ze_event_handle_t *ZeEventWaitList =
-      _pi_event::createZeEventList(NumEventsInWaitList, EventWaitList);
-  if (!ZeEventWaitList)
-    return PI_OUT_OF_HOST_MEMORY;
+  if (auto Res = (*Event)->WaitList.createAndRetainPiZeEventList(
+          NumEventsInWaitList, EventWaitList))
+    return Res;
 
-  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList, NumEventsInWaitList,
-                                          ZeEventWaitList));
+  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList,
+                                          (*Event)->WaitList.Length,
+                                          (*Event)->WaitList.ZeEventList));
 
   ZE_CALL(zeCommandListAppendMemoryCopy(ZeCommandList, Dst, Src, Size, ZeEvent,
                                         0, nullptr));
@@ -4033,15 +4166,9 @@ enqueueMemCopyHelper(pi_command_type CommandType, pi_queue Queue, void *Dst,
     return Res;
 
   zePrint("calling zeCommandListAppendMemoryCopy() with\n"
-          "  xe_event %lx\n"
-          "  NumEventsInWaitList %d:",
-          pi_cast<std::uintptr_t>(ZeEvent), NumEventsInWaitList);
-  for (pi_uint32 I = 0; I < NumEventsInWaitList; I++) {
-    zePrint(" %lx", pi_cast<std::uintptr_t>(ZeEventWaitList[I]));
-  }
-  zePrint("\n");
-
-  _pi_event::deleteZeEventList(ZeEventWaitList);
+          "  ZeEvent %#lx\n",
+          pi_cast<std::uintptr_t>(ZeEvent));
+  printZeEventList((*Event)->WaitList);
 
   return PI_SUCCESS;
 }
@@ -4057,6 +4184,7 @@ static pi_result enqueueMemCopyRectHelper(
     const pi_event *EventWaitList, pi_event *Event) {
 
   PI_ASSERT(Region && SrcOrigin && DstOrigin && Queue, PI_INVALID_VALUE);
+  PI_ASSERT(Event, PI_INVALID_EVENT);
 
   // Get a new command list to be used on this call
   ze_command_list_handle_t ZeCommandList = nullptr;
@@ -4066,29 +4194,24 @@ static pi_result enqueueMemCopyRectHelper(
     return Res;
 
   ze_event_handle_t ZeEvent = nullptr;
-  if (Event) {
-    auto Res =
-        createEventAndAssociateQueue(Queue, Event, CommandType, ZeCommandList);
-    if (Res != PI_SUCCESS)
-      return Res;
-    ZeEvent = (*Event)->ZeEvent;
-  }
+  auto Res =
+      createEventAndAssociateQueue(Queue, Event, CommandType, ZeCommandList);
+  if (Res != PI_SUCCESS)
+    return Res;
+  ZeEvent = (*Event)->ZeEvent;
 
-  ze_event_handle_t *ZeEventWaitList =
-      _pi_event::createZeEventList(NumEventsInWaitList, EventWaitList);
-  if (!ZeEventWaitList)
-    return PI_OUT_OF_HOST_MEMORY;
+  if (auto Res = (*Event)->WaitList.createAndRetainPiZeEventList(
+          NumEventsInWaitList, EventWaitList))
+    return Res;
 
-  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList, NumEventsInWaitList,
-                                          ZeEventWaitList));
+  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList,
+                                          (*Event)->WaitList.Length,
+                                          (*Event)->WaitList.ZeEventList));
 
-  zePrint("calling zeCommandListAppendWaitOnEvents() with\n"
-          "  NumEventsInWaitList %d:",
-          pi_cast<std::uintptr_t>(ZeEvent), NumEventsInWaitList);
-  for (pi_uint32 I = 0; I < NumEventsInWaitList; I++) {
-    zePrint(" %lx", pi_cast<std::uintptr_t>(ZeEventWaitList[I]));
-  }
-  zePrint("\n");
+  zePrint("calling zeCommandListAppendMemoryCopy() with\n"
+          "  ZeEvent %#lx\n",
+          pi_cast<std::uintptr_t>(ZeEvent));
+  printZeEventList((*Event)->WaitList);
 
   uint32_t SrcOriginX = pi_cast<uint32_t>(SrcOrigin->x_bytes);
   uint32_t SrcOriginY = pi_cast<uint32_t>(SrcOrigin->y_scalar);
@@ -4129,14 +4252,12 @@ static pi_result enqueueMemCopyRectHelper(
 
   ZE_CALL(zeCommandListAppendBarrier(ZeCommandList, ZeEvent, 0, nullptr));
 
-  zePrint("calling zeCommandListAppendBarrier() with Event %lx\n",
+  zePrint("calling zeCommandListAppendBarrier() with Event %#lx\n",
           pi_cast<std::uintptr_t>(ZeEvent));
 
   if (auto Res = Queue->executeCommandList(ZeCommandList, ZeFence, Blocking))
     return Res;
 
-  _pi_event::deleteZeEventList(ZeEventWaitList);
-
   return PI_SUCCESS;
 }
 
@@ -4236,6 +4357,8 @@ enqueueMemFillHelper(pi_command_type CommandType, pi_queue Queue, void *Ptr,
                      pi_uint32 NumEventsInWaitList,
                      const pi_event *EventWaitList, pi_event *Event) {
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
+  PI_ASSERT(Event, PI_INVALID_EVENT);
+
   // Get a new command list to be used on this call
   ze_command_list_handle_t ZeCommandList = nullptr;
   ze_fence_handle_t ZeFence = nullptr;
@@ -4244,21 +4367,19 @@ enqueueMemFillHelper(pi_command_type CommandType, pi_queue Queue, void *Ptr,
     return Res;
 
   ze_event_handle_t ZeEvent = nullptr;
-  if (Event) {
-    auto Res =
-        createEventAndAssociateQueue(Queue, Event, CommandType, ZeCommandList);
-    if (Res != PI_SUCCESS)
-      return Res;
-    ZeEvent = (*Event)->ZeEvent;
-  }
+  auto Res =
+      createEventAndAssociateQueue(Queue, Event, CommandType, ZeCommandList);
+  if (Res != PI_SUCCESS)
+    return Res;
+  ZeEvent = (*Event)->ZeEvent;
 
-  ze_event_handle_t *ZeEventWaitList =
-      _pi_event::createZeEventList(NumEventsInWaitList, EventWaitList);
-  if (!ZeEventWaitList)
-    return PI_OUT_OF_HOST_MEMORY;
+  if (auto Res = (*Event)->WaitList.createAndRetainPiZeEventList(
+          NumEventsInWaitList, EventWaitList))
+    return Res;
 
-  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList, NumEventsInWaitList,
-                                          ZeEventWaitList));
+  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList,
+                                          (*Event)->WaitList.Length,
+                                          (*Event)->WaitList.ZeEventList));
 
   // Pattern size must be a power of two
   PI_ASSERT((PatternSize > 0) && ((PatternSize & (PatternSize - 1)) == 0),
@@ -4268,21 +4389,15 @@ enqueueMemFillHelper(pi_command_type CommandType, pi_queue Queue, void *Ptr,
       ZeCommandList, Ptr, Pattern, PatternSize, Size, ZeEvent, 0, nullptr));
 
   zePrint("calling zeCommandListAppendMemoryFill() with\n"
-          "  xe_event %lx\n"
-          "  NumEventsInWaitList %d:",
-          pi_cast<pi_uint64>(ZeEvent), NumEventsInWaitList);
-  for (pi_uint32 I = 0; I < NumEventsInWaitList; I++) {
-    zePrint(" %lx", pi_cast<pi_uint64>(ZeEventWaitList[I]));
-  }
-  zePrint("\n");
+          "  ZeEvent %#lx\n",
+          pi_cast<pi_uint64>(ZeEvent));
+  printZeEventList((*Event)->WaitList);
 
   // Execute command list asynchronously, as the event will be used
   // to track down its completion.
   if (auto Res = Queue->executeCommandList(ZeCommandList, ZeFence))
     return Res;
 
-  _pi_event::deleteZeEventList(ZeEventWaitList);
-
   return PI_SUCCESS;
 }
 
@@ -4319,13 +4434,14 @@ pi_result piEnqueueMemBufferMap(pi_queue Queue, pi_mem Buffer,
   // assert((map_flags & PI_MAP_WRITE) != 0);
   PI_ASSERT(Buffer, PI_INVALID_MEM_OBJECT);
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
+  PI_ASSERT(Event, PI_INVALID_EVENT);
 
   // For discrete devices we don't need a commandlist
   ze_command_list_handle_t ZeCommandList = nullptr;
   ze_fence_handle_t ZeFence = nullptr;
   ze_event_handle_t ZeEvent = nullptr;
 
-  if (Event) {
+  {
     // Lock automatically releases when this goes out of scope.
     std::lock_guard<std::mutex> lock(Queue->PiQueueMutex);
 
@@ -4380,8 +4496,9 @@ pi_result piEnqueueMemBufferMap(pi_queue Queue, pi_mem Buffer,
     (*Event)->ZeCommandList = ZeCommandList;
   }
 
-  ze_event_handle_t *ZeEventWaitList =
-      _pi_event::createZeEventList(NumEventsInWaitList, EventWaitList);
+  if (auto Res = (*Event)->WaitList.createAndRetainPiZeEventList(
+          NumEventsInWaitList, EventWaitList))
+    return Res;
 
   if (Buffer->MapHostPtr) {
     *RetMap = Buffer->MapHostPtr + Offset;
@@ -4393,8 +4510,9 @@ pi_result piEnqueueMemBufferMap(pi_queue Queue, pi_mem Buffer,
         zeMemAllocHost(Queue->Context->ZeContext, &ZeDesc, Size, 1, RetMap));
   }
 
-  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList, NumEventsInWaitList,
-                                          ZeEventWaitList));
+  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList,
+                                          (*Event)->WaitList.Length,
+                                          (*Event)->WaitList.ZeEventList));
 
   ZE_CALL(zeCommandListAppendMemoryCopy(
       ZeCommandList, *RetMap, pi_cast<char *>(Buffer->getZeHandle()) + Offset,
@@ -4403,8 +4521,6 @@ pi_result piEnqueueMemBufferMap(pi_queue Queue, pi_mem Buffer,
   if (auto Res = Queue->executeCommandList(ZeCommandList, ZeFence, BlockingMap))
     return Res;
 
-  _pi_event::deleteZeEventList(ZeEventWaitList);
-
   return Buffer->addMapping(*RetMap, Offset, Size);
 }
 
@@ -4412,6 +4528,7 @@ pi_result piEnqueueMemUnmap(pi_queue Queue, pi_mem MemObj, void *MappedPtr,
                             pi_uint32 NumEventsInWaitList,
                             const pi_event *EventWaitList, pi_event *Event) {
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
+  PI_ASSERT(Event, PI_INVALID_EVENT);
 
   // Integrated devices don't need a command list.
   // If discrete we will get a commandlist later.
@@ -4424,7 +4541,7 @@ pi_result piEnqueueMemUnmap(pi_queue Queue, pi_mem MemObj, void *MappedPtr,
 
   ze_event_handle_t ZeEvent = nullptr;
 
-  if (Event) {
+  {
     // Lock automatically releases when this goes out of scope.
     std::lock_guard<std::mutex> lock(Queue->PiQueueMutex);
 
@@ -4472,15 +4589,15 @@ pi_result piEnqueueMemUnmap(pi_queue Queue, pi_mem MemObj, void *MappedPtr,
     return Res;
 
   // Set the commandlist in the event
-  if (Event) {
-    (*Event)->ZeCommandList = ZeCommandList;
-  }
+  (*Event)->ZeCommandList = ZeCommandList;
 
-  ze_event_handle_t *ZeEventWaitList =
-      _pi_event::createZeEventList(NumEventsInWaitList, EventWaitList);
+  if (auto Res = (*Event)->WaitList.createAndRetainPiZeEventList(
+          NumEventsInWaitList, EventWaitList))
+    return Res;
 
-  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList, NumEventsInWaitList,
-                                          ZeEventWaitList));
+  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList,
+                                          (*Event)->WaitList.Length,
+                                          (*Event)->WaitList.ZeEventList));
 
   // TODO: Level Zero is missing the memory "mapping" capabilities, so we are
   // left to doing copy (write back to the device).
@@ -4497,14 +4614,17 @@ pi_result piEnqueueMemUnmap(pi_queue Queue, pi_mem MemObj, void *MappedPtr,
   if (auto Res = Queue->executeCommandList(ZeCommandList, ZeFence))
     return Res;
 
-  _pi_event::deleteZeEventList(ZeEventWaitList);
-
   return PI_SUCCESS;
 }
 
 pi_result piMemImageGetInfo(pi_mem Image, pi_image_info ParamName,
                             size_t ParamValueSize, void *ParamValue,
                             size_t *ParamValueSizeRet) {
+  (void)Image;
+  (void)ParamName;
+  (void)ParamValueSize;
+  (void)ParamValue;
+  (void)ParamValueSizeRet;
 
   die("piMemImageGetInfo: not implemented");
   return {};
@@ -4566,6 +4686,8 @@ enqueueMemImageCommandHelper(pi_command_type CommandType, pi_queue Queue,
                              pi_uint32 NumEventsInWaitList,
                              const pi_event *EventWaitList, pi_event *Event) {
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
+  PI_ASSERT(Event, PI_INVALID_EVENT);
+
   // Get a new command list to be used on this call
   ze_command_list_handle_t ZeCommandList = nullptr;
   ze_fence_handle_t ZeFence = nullptr;
@@ -4574,19 +4696,19 @@ enqueueMemImageCommandHelper(pi_command_type CommandType, pi_queue Queue,
     return Res;
 
   ze_event_handle_t ZeEvent = nullptr;
-  if (Event) {
-    auto Res =
-        createEventAndAssociateQueue(Queue, Event, CommandType, ZeCommandList);
-    if (Res != PI_SUCCESS)
-      return Res;
-    ZeEvent = (*Event)->ZeEvent;
-  }
+  auto Res =
+      createEventAndAssociateQueue(Queue, Event, CommandType, ZeCommandList);
+  if (Res != PI_SUCCESS)
+    return Res;
+  ZeEvent = (*Event)->ZeEvent;
 
-  ze_event_handle_t *ZeEventWaitList =
-      _pi_event::createZeEventList(NumEventsInWaitList, EventWaitList);
+  if (auto Res = (*Event)->WaitList.createAndRetainPiZeEventList(
+          NumEventsInWaitList, EventWaitList))
+    return Res;
 
-  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList, NumEventsInWaitList,
-                                          ZeEventWaitList));
+  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList,
+                                          (*Event)->WaitList.Length,
+                                          (*Event)->WaitList.ZeEventList));
 
   if (CommandType == PI_COMMAND_TYPE_IMAGE_READ) {
     pi_mem SrcMem = pi_cast<pi_mem>(const_cast<void *>(Src));
@@ -4677,8 +4799,6 @@ enqueueMemImageCommandHelper(pi_command_type CommandType, pi_queue Queue,
   if (auto Res = Queue->executeCommandList(ZeCommandList, ZeFence, IsBlocking))
     return Res;
 
-  _pi_event::deleteZeEventList(ZeEventWaitList);
-
   return PI_SUCCESS;
 }
 
@@ -4756,6 +4876,13 @@ pi_result piEnqueueMemImageFill(pi_queue Queue, pi_mem Image,
                                 pi_uint32 NumEventsInWaitList,
                                 const pi_event *EventWaitList,
                                 pi_event *Event) {
+  (void)Image;
+  (void)FillColor;
+  (void)Origin;
+  (void)Region;
+  (void)NumEventsInWaitList;
+  (void)EventWaitList;
+  (void)Event;
 
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
 
@@ -4813,6 +4940,15 @@ pi_result piEnqueueNativeKernel(pi_queue Queue, void (*UserFunc)(void *),
                                 pi_uint32 NumEventsInWaitList,
                                 const pi_event *EventWaitList,
                                 pi_event *Event) {
+  (void)UserFunc;
+  (void)Args;
+  (void)CbArgs;
+  (void)NumMemObjects;
+  (void)MemList;
+  (void)ArgsMemLoc;
+  (void)NumEventsInWaitList;
+  (void)EventWaitList;
+  (void)Event;
 
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
 
@@ -4827,6 +4963,7 @@ pi_result piEnqueueNativeKernel(pi_queue Queue, void (*UserFunc)(void *),
 pi_result piextGetDeviceFunctionPointer(pi_device Device, pi_program Program,
                                         const char *FunctionName,
                                         pi_uint64 *FunctionPointerRet) {
+  (void)Device;
   PI_ASSERT(Program, PI_INVALID_PROGRAM);
 
   if (Program->State != _pi_program::Exe &&
@@ -5159,11 +5296,12 @@ pi_result piextUSMEnqueueMemcpy(pi_queue Queue, pi_bool Blocking, void *DstPtr,
 /// @param Event is the event that represents this operation
 pi_result piextUSMEnqueuePrefetch(pi_queue Queue, const void *Ptr, size_t Size,
                                   pi_usm_migration_flags Flags,
-                                  pi_uint32 NumEventsInWaitlist,
-                                  const pi_event *EventsWaitlist,
+                                  pi_uint32 NumEventsInWaitList,
+                                  const pi_event *EventWaitList,
                                   pi_event *Event) {
   PI_ASSERT(!(Flags & ~PI_USM_MIGRATION_TBD0), PI_INVALID_VALUE);
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
+  PI_ASSERT(Event, PI_INVALID_EVENT);
 
   // Lock automatically releases when this goes out of scope.
   std::lock_guard<std::mutex> lock(Queue->PiQueueMutex);
@@ -5177,19 +5315,19 @@ pi_result piextUSMEnqueuePrefetch(pi_queue Queue, const void *Ptr, size_t Size,
 
   // TODO: do we need to create a unique command type for this?
   ze_event_handle_t ZeEvent = nullptr;
-  if (Event) {
-    auto Res = createEventAndAssociateQueue(Queue, Event, PI_COMMAND_TYPE_USER,
-                                            ZeCommandList);
-    if (Res != PI_SUCCESS)
-      return Res;
-    ZeEvent = (*Event)->ZeEvent;
-  }
+  auto Res = createEventAndAssociateQueue(Queue, Event, PI_COMMAND_TYPE_USER,
+                                          ZeCommandList);
+  if (Res != PI_SUCCESS)
+    return Res;
+  ZeEvent = (*Event)->ZeEvent;
 
-  ze_event_handle_t *ZeEventWaitList =
-      _pi_event::createZeEventList(NumEventsInWaitlist, EventsWaitlist);
+  if (auto Res = (*Event)->WaitList.createAndRetainPiZeEventList(
+          NumEventsInWaitList, EventWaitList))
+    return Res;
 
-  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList, NumEventsInWaitlist,
-                                          ZeEventWaitList));
+  ZE_CALL(zeCommandListAppendWaitOnEvents(ZeCommandList,
+                                          (*Event)->WaitList.Length,
+                                          (*Event)->WaitList.ZeEventList));
 
   // TODO: figure out how to translate "flags"
   ZE_CALL(zeCommandListAppendMemoryPrefetch(ZeCommandList, Ptr, Size));
@@ -5201,8 +5339,6 @@ pi_result piextUSMEnqueuePrefetch(pi_queue Queue, const void *Ptr, size_t Size,
   if (auto Res = Queue->executeCommandList(ZeCommandList, ZeFence, false))
     return Res;
 
-  _pi_event::deleteZeEventList(ZeEventWaitList);
-
   return PI_SUCCESS;
 }
 
@@ -5218,6 +5354,7 @@ pi_result piextUSMEnqueueMemAdvise(pi_queue Queue, const void *Ptr,
                                    size_t Length, pi_mem_advice Advice,
                                    pi_event *Event) {
   PI_ASSERT(Queue, PI_INVALID_QUEUE);
+  PI_ASSERT(Event, PI_INVALID_EVENT);
 
   // Lock automatically releases when this goes out of scope.
   std::lock_guard<std::mutex> lock(Queue->PiQueueMutex);
@@ -5233,13 +5370,11 @@ pi_result piextUSMEnqueueMemAdvise(pi_queue Queue, const void *Ptr,
 
   // TODO: do we need to create a unique command type for this?
   ze_event_handle_t ZeEvent = nullptr;
-  if (Event) {
-    auto Res = createEventAndAssociateQueue(Queue, Event, PI_COMMAND_TYPE_USER,
-                                            ZeCommandList);
-    if (Res != PI_SUCCESS)
-      return Res;
-    ZeEvent = (*Event)->ZeEvent;
-  }
+  auto Res = createEventAndAssociateQueue(Queue, Event, PI_COMMAND_TYPE_USER,
+                                          ZeCommandList);
+  if (Res != PI_SUCCESS)
+    return Res;
+  ZeEvent = (*Event)->ZeEvent;
 
   ZE_CALL(zeCommandListAppendMemAdvise(ZeCommandList, Queue->Device->ZeDevice,
                                        Ptr, Length, ZeAdvice));
@@ -5252,7 +5387,7 @@ pi_result piextUSMEnqueueMemAdvise(pi_queue Queue, const void *Ptr,
   return PI_SUCCESS;
 }
 
-/// API to query information about USM allocated pointers
+/// API to query information about USM allocated pointers.
 /// Valid Queries:
 ///   PI_MEM_ALLOC_TYPE returns host/device/shared pi_usm_type value
 ///   PI_MEM_ALLOC_BASE_PTR returns the base ptr of an allocation if
@@ -5330,6 +5465,7 @@ pi_result piextUSMGetMemAllocInfo(pi_context Context, const void *Ptr,
 
 pi_result piKernelSetExecInfo(pi_kernel Kernel, pi_kernel_exec_info ParamName,
                               size_t ParamValueSize, const void *ParamValue) {
+  (void)ParamValueSize;
   PI_ASSERT(Kernel, PI_INVALID_KERNEL);
   PI_ASSERT(ParamValue, PI_INVALID_VALUE);
 
diff --git a/sycl/plugins/level_zero/pi_level_zero.hpp b/sycl/plugins/level_zero/pi_level_zero.hpp
index 2d8133f9369e4..36a8cc2135afa 100644
--- a/sycl/plugins/level_zero/pi_level_zero.hpp
+++ b/sycl/plugins/level_zero/pi_level_zero.hpp
@@ -142,6 +142,7 @@ struct _pi_device : _pi_object {
     // NOTE: one must additionally call initialize() to complete
     // PI device creation.
   }
+  ~_pi_device();
 
   // Keep the ordinal of a "compute" commands group, where we send all
   // commands currently.
@@ -480,6 +481,35 @@ struct _pi_image final : _pi_mem {
   ze_image_handle_t ZeImage;
 };
 
+struct _pi_ze_event_list_t {
+  // List of level zero events for this event list.
+  ze_event_handle_t *ZeEventList = {nullptr};
+
+  // List of pi_events for this event list.
+  pi_event *PiEventList = {nullptr};
+
+  // length of both the lists.  The actual allocation of these lists
+  // may be longer than this length.  This length is the actual number
+  // of elements in the above arrays that are valid.
+  pi_uint32 Length = {0};
+
+  // A mutex is needed for destroying the event list.
+  // Creation is already thread-safe because we only create the list
+  // when an event in initially created.  However, it might be
+  // possible to have multiple threads racing to destroy the list,
+  // so this will be used to make list destruction thread-safe.
+  std::mutex PiZeEventListMutex;
+
+  // Initialize this using the array of events in EventList, and retain
+  // all the pi_events in the created data structure.
+  pi_result createAndRetainPiZeEventList(pi_uint32 EventListLength,
+                                         const pi_event *EventList);
+
+  // Release all the events in this object's PiEventList, and destroy
+  // the data structures it contains.
+  pi_result releaseAndDestroyPiZeEventList();
+};
+
 struct _pi_event : _pi_object {
   _pi_event(ze_event_handle_t ZeEvent, ze_event_pool_handle_t ZeEventPool,
             pi_context Context, pi_command_type CommandType)
@@ -508,9 +538,11 @@ struct _pi_event : _pi_object {
   // Opaque data to hold any data needed for CommandType.
   void *CommandData;
 
-  // Methods for translating PI events list into Level Zero events list
-  static ze_event_handle_t *createZeEventList(pi_uint32, const pi_event *);
-  static void deleteZeEventList(ze_event_handle_t *);
+  // List of events that were in the wait list of the command that will
+  // signal this event.  These events must be retained when the command is
+  // enqueued, and must then be released when this event has signalled.
+  // This list must be destroyed once the event has signalled.
+  _pi_ze_event_list_t WaitList;
 };
 
 struct _pi_program : _pi_object {
diff --git a/sycl/plugins/opencl/pi_opencl.cpp b/sycl/plugins/opencl/pi_opencl.cpp
index 870efeba517f1..6ae41a09d15e7 100644
--- a/sycl/plugins/opencl/pi_opencl.cpp
+++ b/sycl/plugins/opencl/pi_opencl.cpp
@@ -60,8 +60,6 @@ CONSTFIX char clCreateBufferWithPropertiesName[] =
 CONSTFIX char clSetKernelArgMemPointerName[] = "clSetKernelArgMemPointerINTEL";
 CONSTFIX char clEnqueueMemsetName[] = "clEnqueueMemsetINTEL";
 CONSTFIX char clEnqueueMemcpyName[] = "clEnqueueMemcpyINTEL";
-CONSTFIX char clEnqueueMigrateMemName[] = "clEnqueueMigrateMemINTEL";
-CONSTFIX char clEnqueueMemAdviseName[] = "clEnqueueMemAdviseINTEL";
 CONSTFIX char clGetMemAllocInfoName[] = "clGetMemAllocInfoINTEL";
 CONSTFIX char clSetProgramSpecializationConstantName[] =
     "clSetProgramSpecializationConstant";
@@ -539,6 +537,8 @@ pi_result piextContextCreateWithNativeHandle(pi_native_handle nativeHandle,
                                              pi_uint32 num_devices,
                                              const pi_device *devices,
                                              pi_context *piContext) {
+  (void)num_devices;
+  (void)devices;
   assert(piContext != nullptr);
   *piContext = reinterpret_cast<pi_context>(nativeHandle);
   return PI_SUCCESS;
@@ -663,6 +663,7 @@ pi_result piKernelGetSubGroupInfo(pi_kernel kernel, pi_device device,
                                   const void *input_value,
                                   size_t param_value_size, void *param_value,
                                   size_t *param_value_size_ret) {
+  (void)param_value_size;
   size_t ret_val;
   cl_int ret_err;
   ret_err = cast<pi_result>(clGetKernelSubGroupInfo(
@@ -847,6 +848,7 @@ pi_result piextUSMFree(pi_context context, void *ptr) {
 /// \param arg_value is the pointer argument
 pi_result piextKernelSetArgPointer(pi_kernel kernel, pi_uint32 arg_index,
                                    size_t arg_size, const void *arg_value) {
+  (void)arg_size;
 
   // Size is unused in CL as pointer args are passed by value.
 
@@ -968,6 +970,9 @@ pi_result piextUSMEnqueuePrefetch(pi_queue queue, const void *ptr, size_t size,
                                   pi_uint32 num_events_in_waitlist,
                                   const pi_event *events_waitlist,
                                   pi_event *event) {
+  (void)ptr;
+  (void)size;
+  (void)flags;
 
   return cast<pi_result>(clEnqueueMarkerWithWaitList(
       cast<cl_command_queue>(queue), num_events_in_waitlist,
@@ -1010,6 +1015,9 @@ pi_result piextUSMEnqueuePrefetch(pi_queue queue, const void *ptr, size_t size,
 pi_result piextUSMEnqueueMemAdvise(pi_queue queue, const void *ptr,
                                    size_t length, pi_mem_advice advice,
                                    pi_event *event) {
+  (void)ptr;
+  (void)length;
+  (void)advice;
 
   return cast<pi_result>(
       clEnqueueMarkerWithWaitList(cast<cl_command_queue>(queue), 0, nullptr,
diff --git a/sycl/source/detail/plugin_printers.hpp b/sycl/source/detail/plugin_printers.hpp
index 133de20b35d61..dbbd827d09c11 100644
--- a/sycl/source/detail/plugin_printers.hpp
+++ b/sycl/source/detail/plugin_printers.hpp
@@ -12,15 +12,26 @@
 
 #include <CL/sycl/detail/pi.hpp>
 
+#include <type_traits>
+
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
 namespace detail {
 namespace pi {
 
-template <typename T> inline void print(T val) {
+template <typename T>
+inline typename std::enable_if<!std::is_pointer<T>::value, void>::type
+print(T val) {
   std::cout << "<unknown> : " << val << std::endl;
 }
 
+template <typename T>
+inline typename std::enable_if<std::is_pointer<T>::value, void>::type
+print(T val) {
+  std::cout << "<unknown> : " << reinterpret_cast<const void *>(val)
+            << std::endl;
+}
+
 template <> inline void print<>(PiPlatform val) {
   std::cout << "pi_platform : " << val << std::endl;
 }
diff --git a/sycl/test/CMakeLists.txt b/sycl/test/CMakeLists.txt
index 457b0a6eab25e..721f962d5fe45 100644
--- a/sycl/test/CMakeLists.txt
+++ b/sycl/test/CMakeLists.txt
@@ -113,12 +113,14 @@ if(SYCL_BUILD_PI_CUDA)
   add_lit_testsuite(check-sycl-ptx "Running device-agnostic SYCL regression tests for NVidia PTX"
     ${CMAKE_CURRENT_BINARY_DIR}
     ARGS ${RT_TEST_ARGS}
-    PARAMS "SYCL_TRIPLE=nvptx64-nvidia-cuda-sycldevice"
+    PARAMS "SYCL_TRIPLE=nvptx64-nvidia-cuda-sycldevice;SYCL_PLUGIN=cuda"
     DEPENDS ${SYCL_TEST_DEPS}
     EXCLUDE_FROM_CHECK_ALL
   )
 
-  add_dependencies(check-sycl check-sycl-cuda check-sycl-ptx)
+  add_dependencies(check-sycl-cuda check-sycl-ptx)
+
+  add_dependencies(check-sycl check-sycl-cuda)
 
   add_lit_testsuites(SYCL-CUDA ${CMAKE_CURRENT_SOURCE_DIR}/on-device
     PARAMS "SYCL_PLUGIN=cuda"
diff --git a/sycl/test/basic_tests/vectors/vectors.cpp b/sycl/test/basic_tests/vectors/vectors.cpp
index 3e74c10066859..dafbbc20a3e01 100644
--- a/sycl/test/basic_tests/vectors/vectors.cpp
+++ b/sycl/test/basic_tests/vectors/vectors.cpp
@@ -64,6 +64,12 @@ int main() {
   unsigned long long ull_val = ull_vec.template swizzle<cl::sycl::elem::s0>();
   assert(ull_val == ull_ref);
 
+  // Check that the function as() in swizzle vec class is working correctly
+  cl::sycl::vec<int8_t, 2> inputVec = cl::sycl::vec<int8_t, 2>(0, 1);
+  auto asVec =
+      inputVec.template swizzle<cl::sycl::elem::s0, cl::sycl::elem::s1>()
+          .template as<cl::sycl::vec<int16_t, 1>>();
+
   // Check that [u]long[n] type aliases match vec<[unsigned] long, n> types.
   assert((std::is_same<cl::sycl::vec<long, 2>, cl::sycl::long2>::value));
   assert((std::is_same<cl::sycl::vec<long, 3>, cl::sycl::long3>::value));
diff --git a/sycl/test/esimd/simd.cpp b/sycl/test/esimd/simd.cpp
index 5f949c80e8956..e1e195d28060c 100644
--- a/sycl/test/esimd/simd.cpp
+++ b/sycl/test/esimd/simd.cpp
@@ -15,6 +15,14 @@ bool test_simd_ctors() __attribute__((sycl_device)) {
   return v0[0] + v1[1] + v2[2] + v3[3] == 1 + 1 + 2 + 6;
 }
 
+void test_conversion() __attribute__((sycl_device)) {
+  simd<int, 32> v = 3;
+  simd<float, 32> f = v;
+  simd<char, 32> c = f;
+  simd<char, 16> c1 = f.select<16, 1>(0);
+  f = v + static_cast<simd<int, 32>>(c);
+}
+
 bool test_1d_select() __attribute__((sycl_device)) {
   simd<int, 32> v = 0;
   v.select<8, 1>(0) = 1;
@@ -63,6 +71,7 @@ bool test_simd_bin_ops() __attribute__((sycl_device)) {
   simd<int, 8> v0 = 1;
   simd<int, 8> v1 = 2;
   v0 += v1;
+  v0 %= v1;
   v0 = 2 - v0;
   v0 -= v1;
   v0 -= 2;
@@ -73,6 +82,16 @@ bool test_simd_bin_ops() __attribute__((sycl_device)) {
   return v0[0] == 1;
 }
 
+bool test_simd_unary_ops() __attribute__((sycl_device)) {
+  simd<int, 8> v0 = 1;
+  simd<int, 8> v1 = 2;
+  v0 <<= v1;
+  v1 = -v0;
+  v0 = ~v1;
+  v1 = !v0;
+  return v1[0] == 1;
+}
+
 bool test_nested_1d_select() __attribute__((sycl_device)) {
   simd<int, 8> r0(0, 1);
 
@@ -202,14 +221,12 @@ bool test_replicate2() __attribute__((sycl_device)) {
   simd<int, 8> v0(0, 1);
   auto v0_rep = v0.replicate<2, 4, 2>(1);
 
-  return v0_rep[0] == v0[1] && v0_rep[1] == v0[2] &&
-         v0_rep[2] == v0[5];
+  return v0_rep[0] == v0[1] && v0_rep[1] == v0[2] && v0_rep[2] == v0[5];
 }
 
 bool test_replicate3() __attribute__((sycl_device)) {
   simd<int, 8> v0(0, 1);
   auto v0_rep = v0.replicate<2, 4, 2, 2>(1);
 
-  return v0_rep[0] == v0[1] && v0_rep[1] == v0[3] &&
-         v0_rep[2] == v0[5];
+  return v0_rep[0] == v0[1] && v0_rep[1] == v0[3] && v0_rep[2] == v0[5];
 }
diff --git a/sycl/test/esimd/simd_view.cpp b/sycl/test/esimd/simd_view.cpp
index 15d7624cd2431..7f94b1724b6fe 100644
--- a/sycl/test/esimd/simd_view.cpp
+++ b/sycl/test/esimd/simd_view.cpp
@@ -26,6 +26,7 @@ bool test_simd_view_bin_ops() __attribute__((sycl_device)) {
   auto ref1 = v1.select<8, 2>(0);
   ref0 += ref1;
   ref0 += 2;
+  ref0 %= ref1;
   ref0 -= ref1;
   ref0 -= 2;
   ref0 *= ref1;
@@ -35,6 +36,18 @@ bool test_simd_view_bin_ops() __attribute__((sycl_device)) {
   return v0[0] == 1;
 }
 
+bool test_simd_view_unary_ops() __attribute__((sycl_device)) {
+  simd<int, 16> v0 = 1;
+  simd<int, 16> v1 = 2;
+  auto ref0 = v0.select<8, 2>(0);
+  auto ref1 = v1.select<8, 2>(0);
+  ref0 <<= ref1;
+  ref1 = -ref0;
+  ref0 = ~ref1;
+  ref1 = !ref0;
+  return v1[0] == 1;
+}
+
 bool test_simd_view_assign1() __attribute__((sycl_device)) {
   simd<int, 32> v0(0, 1);
   simd<int, 16> v1(0, 1);
diff --git a/sycl/test/lit.cfg.py b/sycl/test/lit.cfg.py
index f0ae6f4bf808e..e018511479951 100644
--- a/sycl/test/lit.cfg.py
+++ b/sycl/test/lit.cfg.py
@@ -83,6 +83,9 @@
 lit_config.note("Triple: {}".format(triple))
 config.substitutions.append( ('%sycl_triple',  triple ) )
 
+if triple == 'nvptx64-nvidia-cuda-sycldevice':
+    config.available_features.add('cuda')
+
 # Set timeout for test = 10 mins
 try:
     import psutil
diff --git a/sycl/test/on-device/back_to_back_collectives.cpp b/sycl/test/on-device/back_to_back_collectives.cpp
new file mode 100644
index 0000000000000..492ca0b6a157e
--- /dev/null
+++ b/sycl/test/on-device/back_to_back_collectives.cpp
@@ -0,0 +1,70 @@
+// RUN: %clangxx -fsycl -fsycl-targets=%sycl_triple %s -o %t.out
+// RUN: %RUN_ON_HOST %t.out
+// RUN: %CPU_RUN_PLACEHOLDER %t.out
+// RUN: %GPU_RUN_PLACEHOLDER %t.out
+// RUN: %ACC_RUN_PLACEHOLDER %t.out
+
+#include <CL/sycl.hpp>
+#include <numeric>
+#include <vector>
+using namespace cl::sycl;
+using namespace cl::sycl::ONEAPI;
+
+class back_to_back;
+
+int main() {
+  queue q;
+  if (q.get_device().is_host()) {
+    std::cout << "Skipping test\n";
+    return 0;
+  }
+
+  // Use max work-group size to maximize chance of race
+  program prog(q.get_context());
+  prog.build_with_kernel_type<back_to_back>();
+  kernel k = prog.get_kernel<back_to_back>();
+  device d = q.get_device();
+  int N = k.get_info<info::kernel_device_specific::work_group_size>(d);
+
+  std::vector<int> Input(N), Sum(N), EScan(N), IScan(N);
+  std::iota(Input.begin(), Input.end(), 0);
+  std::fill(Sum.begin(), Sum.end(), 0);
+  std::fill(EScan.begin(), EScan.end(), 0);
+  std::fill(IScan.begin(), IScan.end(), 0);
+
+  {
+    buffer<int> InputBuf(Input.data(), N);
+    buffer<int> SumBuf(Sum.data(), N);
+    buffer<int> EScanBuf(EScan.data(), N);
+    buffer<int> IScanBuf(IScan.data(), N);
+    q.submit([&](handler &h) {
+      auto Input = InputBuf.get_access<access::mode::read>(h);
+      auto Sum = SumBuf.get_access<access::mode::write>(h);
+      auto EScan = EScanBuf.get_access<access::mode::write>(h);
+      auto IScan = IScanBuf.get_access<access::mode::write>(h);
+      h.parallel_for<back_to_back>(nd_range<1>(N, N), [=](nd_item<1> it) {
+        size_t i = it.get_global_id(0);
+        auto g = it.get_group();
+        // Loop to increase number of back-to-back calls
+        for (int r = 0; r < 10; ++r) {
+          Sum[i] = reduce(g, Input[i], plus<>());
+          EScan[i] = exclusive_scan(g, Input[i], plus<>());
+          IScan[i] = inclusive_scan(g, Input[i], plus<>());
+        }
+      });
+    });
+  }
+
+  int sum = 0;
+  bool passed = true;
+  for (int i = 0; i < N; ++i) {
+    passed &= (sum == EScan[i]);
+    sum += i;
+    passed &= (sum == IScan[i]);
+  }
+  for (int i = 0; i < N; ++i) {
+    passed &= (sum == Sum[i]);
+  }
+  std::cout << "Test passed." << std::endl;
+  return 0;
+}
diff --git a/sycl/test/extensions/intel-ext-device.cpp b/sycl/test/on-device/extensions/intel-ext-device.cpp
similarity index 100%
rename from sycl/test/extensions/intel-ext-device.cpp
rename to sycl/test/on-device/extensions/intel-ext-device.cpp
diff --git a/sycl/test/plugins/level_zero_batch_test.cpp b/sycl/test/on-device/plugins/level_zero_batch_test.cpp
similarity index 100%
rename from sycl/test/plugins/level_zero_batch_test.cpp
rename to sycl/test/on-device/plugins/level_zero_batch_test.cpp
diff --git a/sycl/test/plugins/level_zero_dynamic_batch_test.cpp b/sycl/test/on-device/plugins/level_zero_dynamic_batch_test.cpp
similarity index 100%
rename from sycl/test/plugins/level_zero_dynamic_batch_test.cpp
rename to sycl/test/on-device/plugins/level_zero_dynamic_batch_test.cpp